%------------------------------------------------------------------------------
% File : Geo-III---2018C
% Problem : HWV008-2.001 : TPTP v8.1.0. Bugfixed v2.7.0.
% Transfm : none
% Format : tptp:raw
% Command : geo -tptp_input -nonempty -inputfile %s
% Computer : n003.cluster.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2620 v4 2.10GHz
% Memory : 8042.1875MB
% OS : Linux 3.10.0-693.el7.x86_64
% CPULimit : 300s
% WCLimit : 300s
% DateTime : Sat Jul 23 06:04:48 EDT 2022
% Result : Unsatisfiable 7.62s 7.81s
% Output : Refutation 7.62s
% Verified :
% SZS Type : -
% Comments :
%------------------------------------------------------------------------------
%----WARNING: Could not form TPTP format derivation
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.06/0.12 % Problem : HWV008-2.001 : TPTP v8.1.0. Bugfixed v2.7.0.
% 0.06/0.12 % Command : geo -tptp_input -nonempty -inputfile %s
% 0.12/0.33 % Computer : n003.cluster.edu
% 0.12/0.33 % Model : x86_64 x86_64
% 0.12/0.33 % CPU : Intel(R) Xeon(R) CPU E5-2620 v4 @ 2.10GHz
% 0.12/0.33 % Memory : 8042.1875MB
% 0.12/0.33 % OS : Linux 3.10.0-693.el7.x86_64
% 0.12/0.33 % CPULimit : 300
% 0.12/0.33 % WCLimit : 300
% 0.12/0.33 % DateTime : Fri Jul 22 17:16:38 EDT 2022
% 0.12/0.33 % CPUTime :
% 7.62/7.81 GeoParameters:
% 7.62/7.81
% 7.62/7.81 tptp_input = 1
% 7.62/7.81 tptp_output = 0
% 7.62/7.81 nonempty = 1
% 7.62/7.81 inputfile = /export/starexec/sandbox2/benchmark/theBenchmark.p
% 7.62/7.81 includepath = /export/starexec/sandbox2/solver/bin/../../benchmark/
% 7.62/7.81
% 7.62/7.81
% 7.62/7.81 % SZS status Unsatisfiable for /export/starexec/sandbox2/benchmark/theBenchmark.p
% 7.62/7.81 % SZS output start Refutation for /export/starexec/sandbox2/benchmark/theBenchmark.p
% 7.62/7.81
% 7.62/7.81 RuleSystem INPUT:
% 7.62/7.81
% 7.62/7.81 Initial Rules:
% 7.62/7.81 #0: input, references = 55, size of lhs = 2:
% 7.62/7.81 connection-{F}(V1,V0), zero-{F}(V1) | zero-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1: input, references = 10, size of lhs = 2:
% 7.62/7.81 connection-{F}(V1,V0), one-{F}(V1) | one-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #2: input, references = 47, size of lhs = 2:
% 7.62/7.81 zero-{F}(V0), connection-{F}(V1,V0) | zero-{T}(V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #3: input, references = 10, size of lhs = 2:
% 7.62/7.81 one-{F}(V0), connection-{F}(V1,V0) | one-{T}(V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #4: input, references = 27, size of lhs = 2:
% 7.62/7.81 zero-{F}(V0), one-{F}(V0) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #5: input, references = 17, size of lhs = 4:
% 7.62/7.81 P_in1-{F}(V0,V1), P_out1-{F}(V0,V2), and_ok-{F}(V0), zero-{F}(V1) | zero-{T}(V2)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #6: input, references = 3, size of lhs = 4:
% 7.62/7.81 P_in2-{F}(V0,V1), P_out1-{F}(V0,V2), and_ok-{F}(V0), zero-{F}(V1) | zero-{T}(V2)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #7: input, references = 3, size of lhs = 6:
% 7.62/7.81 P_in1-{F}(V0,V1), P_in2-{F}(V0,V2), P_out1-{F}(V0,V3), and_ok-{F}(V0), one-{F}(V1), one-{F}(V2) | one-{T}(V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #8: input, references = 3, size of lhs = 5:
% 7.62/7.81 P_out1-{F}(V0,V1), P_in1-{F}(V0,V2), P_in2-{F}(V0,V3), and_ok-{F}(V0), zero-{F}(V1) | zero-{T}(V2), zero-{T}(V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #9: input, references = 3, size of lhs = 4:
% 7.62/7.81 P_out1-{F}(V0,V1), P_in1-{F}(V0,V2), and_ok-{F}(V0), one-{F}(V1) | one-{T}(V2)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #10: input, references = 3, size of lhs = 4:
% 7.62/7.81 P_out1-{F}(V0,V1), P_in2-{F}(V0,V2), and_ok-{F}(V0), one-{F}(V1) | one-{T}(V2)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #11: input, references = 4, size of lhs = 2:
% 7.62/7.81 and_ok-{F}(V0), abnormal-{F}(V0) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #12: input, references = 6, size of lhs = 1:
% 7.62/7.81 logic_and-{F}(V0) | and_ok-{T}(V0), abnormal-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #13: input, references = 3, size of lhs = 4:
% 7.62/7.81 P_in1-{F}(V0,V1), P_out1-{F}(V0,V2), or_ok-{F}(V0), one-{F}(V1) | one-{T}(V2)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #14: input, references = 4, size of lhs = 4:
% 7.62/7.81 P_in2-{F}(V0,V1), P_out1-{F}(V0,V2), or_ok-{F}(V0), one-{F}(V1) | one-{T}(V2)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #15: input, references = 11, size of lhs = 6:
% 7.62/7.81 P_in1-{F}(V0,V1), P_in2-{F}(V0,V2), P_out1-{F}(V0,V3), or_ok-{F}(V0), zero-{F}(V1), zero-{F}(V2) | zero-{T}(V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #16: input, references = 4, size of lhs = 5:
% 7.62/7.81 P_out1-{F}(V0,V1), P_in1-{F}(V0,V2), P_in2-{F}(V0,V3), or_ok-{F}(V0), one-{F}(V1) | one-{T}(V2), one-{T}(V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #17: input, references = 3, size of lhs = 4:
% 7.62/7.81 P_out1-{F}(V0,V1), P_in1-{F}(V0,V2), or_ok-{F}(V0), zero-{F}(V1) | zero-{T}(V2)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #18: input, references = 9, size of lhs = 4:
% 7.62/7.81 P_out1-{F}(V0,V1), P_in2-{F}(V0,V2), or_ok-{F}(V0), zero-{F}(V1) | zero-{T}(V2)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #19: input, references = 3, size of lhs = 2:
% 7.62/7.81 or_ok-{F}(V0), abnormal-{F}(V0) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #20: input, references = 6, size of lhs = 1:
% 7.62/7.81 logic_or-{F}(V0) | or_ok-{T}(V0), abnormal-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #21: input, references = 5, size of lhs = 4:
% 7.62/7.81 P_in1-{F}(V0,V1), P_out1-{F}(V0,V2), not_ok-{F}(V0), zero-{F}(V1) | one-{T}(V2)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #22: input, references = 3, size of lhs = 4:
% 7.62/7.81 P_in1-{F}(V0,V1), P_out1-{F}(V0,V2), not_ok-{F}(V0), one-{F}(V1) | zero-{T}(V2)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #23: input, references = 3, size of lhs = 4:
% 7.62/7.81 P_out1-{F}(V0,V1), P_in1-{F}(V0,V2), not_ok-{F}(V0), zero-{F}(V1) | one-{T}(V2)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #24: input, references = 3, size of lhs = 4:
% 7.62/7.81 P_out1-{F}(V0,V1), P_in1-{F}(V0,V2), not_ok-{F}(V0), one-{F}(V1) | zero-{T}(V2)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #25: input, references = 3, size of lhs = 2:
% 7.62/7.81 not_ok-{F}(V0), abnormal-{F}(V0) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #26: input, references = 4, size of lhs = 1:
% 7.62/7.81 logic_not-{F}(V0) | not_ok-{T}(V0), abnormal-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #27: input, references = 3, size of lhs = 2:
% 7.62/7.81 P_and1-{F}(V0,V1), halfadder-{F}(V0) | logic_and-{T}(V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #28: input, references = 6, size of lhs = 2:
% 7.62/7.81 P_and2-{F}(V0,V1), halfadder-{F}(V0) | logic_and-{T}(V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #29: input, references = 3, size of lhs = 2:
% 7.62/7.81 P_not1-{F}(V0,V1), halfadder-{F}(V0) | logic_not-{T}(V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #30: input, references = 3, size of lhs = 2:
% 7.62/7.81 P_or1-{F}(V0,V1), halfadder-{F}(V0) | logic_or-{T}(V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #31: input, references = 3, size of lhs = 4:
% 7.62/7.81 P_in1-{F}(V0,V1), P_or1-{F}(V0,V2), P_in1-{F}(V2,V3), halfadder-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #32: input, references = 6, size of lhs = 4:
% 7.62/7.81 P_in2-{F}(V0,V1), P_or1-{F}(V0,V2), P_in2-{F}(V2,V3), halfadder-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #33: input, references = 11, size of lhs = 4:
% 7.62/7.81 P_in1-{F}(V0,V1), P_and2-{F}(V0,V2), P_in1-{F}(V2,V3), halfadder-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #34: input, references = 9, size of lhs = 4:
% 7.62/7.81 P_in2-{F}(V0,V1), P_and2-{F}(V0,V2), P_in2-{F}(V2,V3), halfadder-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #35: input, references = 14, size of lhs = 4:
% 7.62/7.81 P_outs-{F}(V0,V1), P_and1-{F}(V0,V2), P_out1-{F}(V2,V3), halfadder-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #36: input, references = 22, size of lhs = 4:
% 7.62/7.81 P_outc-{F}(V0,V1), P_and2-{F}(V0,V2), P_out1-{F}(V2,V3), halfadder-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #37: input, references = 9, size of lhs = 5:
% 7.62/7.81 P_or1-{F}(V0,V1), P_out1-{F}(V1,V2), P_and1-{F}(V0,V3), P_in1-{F}(V3,V4), halfadder-{F}(V0) | connection-{T}(V2,V4)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #38: input, references = 11, size of lhs = 5:
% 7.62/7.81 P_and2-{F}(V0,V1), P_out1-{F}(V1,V2), P_not1-{F}(V0,V3), P_in1-{F}(V3,V4), halfadder-{F}(V0) | connection-{T}(V2,V4)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #39: input, references = 6, size of lhs = 5:
% 7.62/7.81 P_not1-{F}(V0,V1), P_out1-{F}(V1,V2), P_and1-{F}(V0,V3), P_in2-{F}(V3,V4), halfadder-{F}(V0) | connection-{T}(V2,V4)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #40: input, references = 4, size of lhs = 2:
% 7.62/7.81 P_h1-{F}(V0,V1), fulladder-{F}(V0) | halfadder-{T}(V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #41: input, references = 4, size of lhs = 2:
% 7.62/7.81 P_h2-{F}(V0,V1), fulladder-{F}(V0) | halfadder-{T}(V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #42: input, references = 4, size of lhs = 2:
% 7.62/7.81 P_or1-{F}(V0,V1), fulladder-{F}(V0) | logic_or-{T}(V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #43: input, references = 9, size of lhs = 5:
% 7.62/7.81 P_h1-{F}(V0,V1), P_outs-{F}(V1,V2), P_h2-{F}(V0,V3), P_in2-{F}(V3,V4), fulladder-{F}(V0) | connection-{T}(V2,V4)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #44: input, references = 15, size of lhs = 5:
% 7.62/7.81 P_h1-{F}(V0,V1), P_outc-{F}(V1,V2), P_or1-{F}(V0,V3), P_in2-{F}(V3,V4), fulladder-{F}(V0) | connection-{T}(V2,V4)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #45: input, references = 7, size of lhs = 5:
% 7.62/7.81 P_h2-{F}(V0,V1), P_outc-{F}(V1,V2), P_or1-{F}(V0,V3), P_in1-{F}(V3,V4), fulladder-{F}(V0) | connection-{T}(V2,V4)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #46: input, references = 17, size of lhs = 4:
% 7.62/7.81 P_in1-{F}(V0,V1), P_h2-{F}(V0,V2), P_in1-{F}(V2,V3), fulladder-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #47: input, references = 6, size of lhs = 4:
% 7.62/7.81 P_in2-{F}(V0,V1), P_h1-{F}(V0,V2), P_in1-{F}(V2,V3), fulladder-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #48: input, references = 6, size of lhs = 4:
% 7.62/7.81 P_inc-{F}(V0,V1), P_h1-{F}(V0,V2), P_in2-{F}(V2,V3), fulladder-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #49: input, references = 5, size of lhs = 4:
% 7.62/7.81 P_outs-{F}(V0,V1), P_h2-{F}(V0,V2), P_outs-{F}(V2,V3), fulladder-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #50: input, references = 5, size of lhs = 4:
% 7.62/7.81 P_outc-{F}(V0,V1), P_or1-{F}(V0,V2), P_out1-{F}(V2,V3), fulladder-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #51: input, references = 4, size of lhs = 2:
% 7.62/7.81 P_f1-{F}(V0,V1), nbit_adder1-{F}(V0) | fulladder-{T}(V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #52: input, references = 3, size of lhs = 4:
% 7.62/7.81 P_out1-{F}(V0,V1), P_f1-{F}(V0,V2), P_outs-{F}(V2,V3), nbit_adder1-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #53: input, references = 4, size of lhs = 4:
% 7.62/7.81 P_outc-{F}(V0,V1), P_f1-{F}(V0,V2), P_outc-{F}(V2,V3), nbit_adder1-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #54: input, references = 5, size of lhs = 4:
% 7.62/7.81 P_ina1-{F}(V0,V1), P_f1-{F}(V0,V2), P_in1-{F}(V2,V3), nbit_adder1-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #55: input, references = 4, size of lhs = 4:
% 7.62/7.81 P_inb1-{F}(V0,V1), P_f1-{F}(V0,V2), P_in2-{F}(V2,V3), nbit_adder1-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #56: input, references = 3, size of lhs = 4:
% 7.62/7.81 P_inc-{F}(V0,V1), P_f1-{F}(V0,V2), P_inc-{F}(V2,V3), nbit_adder1-{F}(V0) | connection-{T}(V1,V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #57: input, references = 4, size of lhs = 1:
% 7.62/7.81 P_a-{F}(V0) | nbit_adder1-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #58: input, references = 5, size of lhs = 2:
% 7.62/7.81 P_a-{F}(V0), P_ina1-{F}(V0,V1) | zero-{T}(V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #59: input, references = 4, size of lhs = 3:
% 7.62/7.81 P_a-{F}(V0), P_ina1-{F}(V0,V1), P_inb1-{F}(V0,V2) | zero-{T}(V2)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #60: input, references = 3, size of lhs = 4:
% 7.62/7.81 P_a-{F}(V0), P_ina1-{F}(V0,V1), P_inb1-{F}(V0,V2), P_inc-{F}(V0,V3) | zero-{T}(V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #61: input, references = 3, size of lhs = 5:
% 7.62/7.81 P_a-{F}(V0), P_ina1-{F}(V0,V1), P_inb1-{F}(V0,V2), P_inc-{F}(V0,V3), P_out1-{F}(V0,V4) | zero-{T}(V4)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #62: input, references = 5, size of lhs = 6:
% 7.62/7.81 P_a-{F}(V0), P_ina1-{F}(V0,V1), P_inb1-{F}(V0,V2), P_inc-{F}(V0,V3), P_out1-{F}(V0,V4), P_outc-{F}(V0,V5) | one-{T}(V5)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #63: input, references = 3, size of lhs = 9:
% 7.62/7.81 P_a-{F}(V0), P_ina1-{F}(V0,V1), P_inb1-{F}(V0,V2), P_inc-{F}(V0,V3), P_out1-{F}(V0,V4), P_outc-{F}(V0,V5), P_f1-{F}(V0,V6), P_or1-{F}(V6,V7), abnormal-{F}(V7) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #64: input, references = 3, size of lhs = 11:
% 7.62/7.81 P_a-{F}(V0), P_ina1-{F}(V0,V1), P_inb1-{F}(V0,V2), P_inc-{F}(V0,V3), P_out1-{F}(V0,V4), P_outc-{F}(V0,V5), P_f1-{F}(V0,V6), P_or1-{F}(V6,V7), P_h1-{F}(V6,V8), P_and2-{F}(V8,V9), abnormal-{F}(V9) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #65: input, references = 4, size of lhs = 13:
% 7.62/7.81 P_a-{F}(V0), P_ina1-{F}(V0,V1), P_inb1-{F}(V0,V2), P_inc-{F}(V0,V3), P_out1-{F}(V0,V4), P_outc-{F}(V0,V5), P_f1-{F}(V0,V6), P_or1-{F}(V6,V7), P_h1-{F}(V6,V8), P_and2-{F}(V8,V9), P_h2-{F}(V6,V10), P_and2-{F}(V10,V11), abnormal-{F}(V11) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #66: input, references = 21, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_in1-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #67: input, references = 26, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_out1-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #68: input, references = 13, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_in2-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #69: input, references = 3, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_and1-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #70: input, references = 11, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_and2-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #71: input, references = 3, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_not1-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #72: input, references = 4, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_or1-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #73: input, references = 8, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_outs-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #74: input, references = 15, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_outc-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #75: input, references = 4, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_h1-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #76: input, references = 4, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_h2-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #77: input, references = 4, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_inc-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #78: input, references = 4, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_f1-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #79: input, references = 5, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_ina1-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #80: input, references = 5, size of lhs = 1:
% 7.62/7.81 #-{F} V0 | EXISTS V1: P_inb1-{T}(V0,V1)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #81: input, references = 4, size of lhs = 0:
% 7.62/7.81 FALSE | EXISTS V0: P_a-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 number of initial rules = 82
% 7.62/7.81
% 7.62/7.81 Simplifiers:
% 7.62/7.81 #82: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 nbit_adder1-{F}(V0), nbit_adder1-{F}(V1), V0 == V1 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #83: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_in1-{F}(V0,V1), P_in1-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #84: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_out1-{F}(V0,V1), P_out1-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #85: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_in2-{F}(V0,V1), P_in2-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #86: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_and1-{F}(V0,V1), P_and1-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #87: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_and2-{F}(V0,V1), P_and2-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #88: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_not1-{F}(V0,V1), P_not1-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #89: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_or1-{F}(V0,V1), P_or1-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #90: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_outs-{F}(V0,V1), P_outs-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #91: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_outc-{F}(V0,V1), P_outc-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #92: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_h1-{F}(V0,V1), P_h1-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #93: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_h2-{F}(V0,V1), P_h2-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #94: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_inc-{F}(V0,V1), P_inc-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #95: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_f1-{F}(V0,V1), P_f1-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #96: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_ina1-{F}(V0,V1), P_ina1-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #97: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_inb1-{F}(V0,V1), P_inb1-{F}(V0,V3), V1 == V3 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #98: unsound, references = 3, size of lhs = 3:
% 7.62/7.81 P_a-{F}(V0), P_a-{F}(V1), V0 == V1 | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 number of simplifiers = 17
% 7.62/7.81
% 7.62/7.81 Learnt:
% 7.62/7.81 #101: disj( #20, input ), references = 2, size of lhs = 9:
% 7.62/7.81 logic_or-{F}(V0), P_a-{F}(V1), P_ina1-{F}(V1,V2), P_inb1-{F}(V1,V3), P_inc-{F}(V1,V4), P_out1-{F}(V1,V5), P_outc-{F}(V1,V6), P_f1-{F}(V1,V7), P_or1-{F}(V7,V0) | or_ok-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #102: disj( #20, input ), references = 1, size of lhs = 11:
% 7.62/7.81 logic_or-{F}(V0), P_a-{F}(V1), P_ina1-{F}(V1,V2), P_inb1-{F}(V1,V3), P_inc-{F}(V1,V4), P_out1-{F}(V1,V5), P_outc-{F}(V1,V6), P_f1-{F}(V1,V7), P_or1-{F}(V7,V8), P_h1-{F}(V7,V9), P_and2-{F}(V9,V0) | or_ok-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #105: exists( #80, #103 ), references = 4, size of lhs = 6:
% 7.62/7.81 P_a-{F}(V0), P_ina1-{F}(V0,V1), P_inc-{F}(V0,V2), P_out1-{F}(V0,V3), P_outc-{F}(V0,V4), zero-{F}(V4) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #112: exists( #79, #110 ), references = 1, size of lhs = 7:
% 7.62/7.81 nbit_adder1-{F}(V0), P_a-{F}(V0), P_f1-{F}(V0,V1), P_in1-{F}(V1,V2), P_outc-{F}(V0,V2), P_inc-{F}(V0,V3), P_out1-{F}(V0,V4) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #175: exists( #67, #173 ), references = 2, size of lhs = 9:
% 7.62/7.81 halfadder-{F}(V0), P_and2-{F}(V0,V1), P_not1-{F}(V0,V2), P_in1-{F}(V2,V3), one-{F}(V3), halfadder-{F}(V4), P_and1-{F}(V4,V1), P_outs-{F}(V4,V5), zero-{F}(V5) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #179: exists( #73, #177 ), references = 1, size of lhs = 11:
% 7.62/7.81 fulladder-{F}(V0), P_outs-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), halfadder-{F}(V2), halfadder-{F}(V3), P_and2-{F}(V3,V4), P_and1-{F}(V2,V4), P_not1-{F}(V3,V5), P_in1-{F}(V5,V6), one-{F}(V6) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #197: exists( #68, #195 ), references = 1, size of lhs = 8:
% 7.62/7.81 fulladder-{F}(V0), P_inc-{F}(V0,V1), zero-{F}(V1), P_h1-{F}(V0,V2), halfadder-{F}(V3), P_and2-{F}(V3,V2), P_in2-{F}(V3,V4), one-{F}(V4) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #213: exists( #74, #211 ), references = 2, size of lhs = 9:
% 7.62/7.81 fulladder-{F}(V0), P_h2-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in1-{F}(V2,V3), zero-{F}(V3), P_and2-{F}(V1,V4), P_out1-{F}(V4,V5), one-{F}(V5) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #237: exists( #73, #235 ), references = 3, size of lhs = 9:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_h2-{F}(V0,V2), P_in2-{F}(V2,V3), one-{F}(V3), P_and1-{F}(V1,V4), P_out1-{F}(V4,V5), zero-{F}(V5) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #245: exists( #67, #243 ), references = 1, size of lhs = 11:
% 7.62/7.81 halfadder-{F}(V0), P_outc-{F}(V0,V1), zero-{F}(V1), P_and2-{F}(V0,V2), fulladder-{F}(V3), P_h1-{F}(V3,V4), halfadder-{F}(V4), P_and1-{F}(V4,V2), P_h2-{F}(V3,V5), P_in2-{F}(V5,V6), one-{F}(V6) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #263: exists( #74, #261 ), references = 3, size of lhs = 9:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in2-{F}(V2,V3), one-{F}(V3), P_and2-{F}(V1,V4), P_out1-{F}(V4,V5), zero-{F}(V5) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #265: disj( #12, input ), references = 5, size of lhs = 13:
% 7.62/7.81 logic_and-{F}(V0), P_a-{F}(V1), P_ina1-{F}(V1,V2), P_inb1-{F}(V1,V3), P_inc-{F}(V1,V4), P_out1-{F}(V1,V5), P_outc-{F}(V1,V6), P_f1-{F}(V1,V7), P_or1-{F}(V7,V8), P_h1-{F}(V7,V9), P_and2-{F}(V9,V10), P_h2-{F}(V7,V11), P_and2-{F}(V11,V0) | and_ok-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #290: exists( #68, #286 ), references = 2, size of lhs = 8:
% 7.62/7.81 halfadder-{F}(V0), P_in2-{F}(V0,V1), one-{F}(V1), P_and2-{F}(V0,V2), halfadder-{F}(V3), P_or1-{F}(V3,V2), P_in2-{F}(V3,V4), zero-{F}(V4) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #295: disj( #26, #21+#4 ), references = 1, size of lhs = 5:
% 7.62/7.81 logic_not-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_out1-{F}(V0,V2), zero-{F}(V2) | abnormal-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #296: disj( #26, #21+#213 ), references = 3, size of lhs = 12:
% 7.62/7.81 logic_not-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_out1-{F}(V0,V2), fulladder-{F}(V3), P_h2-{F}(V3,V4), halfadder-{F}(V4), P_or1-{F}(V3,V5), P_in1-{F}(V5,V6), zero-{F}(V6), P_and2-{F}(V4,V7), P_out1-{F}(V7,V2) | abnormal-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #303: exists( #67, #299 ), references = 2, size of lhs = 11:
% 7.62/7.81 logic_not-{F}(V0), and_ok-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), fulladder-{F}(V2), P_h2-{F}(V2,V3), halfadder-{F}(V3), P_and2-{F}(V3,V0), P_or1-{F}(V2,V4), P_in1-{F}(V4,V5), zero-{F}(V5) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #304: exists( #67, #300 ), references = 2, size of lhs = 22:
% 7.62/7.81 logic_not-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), fulladder-{F}(V2), P_h2-{F}(V2,V3), halfadder-{F}(V3), P_and2-{F}(V3,V0), P_or1-{F}(V2,V4), P_in1-{F}(V4,V5), zero-{F}(V5), P_a-{F}(V6), P_ina1-{F}(V6,V7), P_inb1-{F}(V6,V8), P_inc-{F}(V6,V9), P_out1-{F}(V6,V10), P_outc-{F}(V6,V11), P_f1-{F}(V6,V12), P_or1-{F}(V12,V13), P_h1-{F}(V12,V14), P_and2-{F}(V14,V15), P_h2-{F}(V12,V16), P_and2-{F}(V16,V0) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #311: exists( #66, #307 ), references = 1, size of lhs = 13:
% 7.62/7.81 halfadder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_and2-{F}(V0,V2), logic_not-{F}(V2), and_ok-{F}(V2), fulladder-{F}(V3), P_h2-{F}(V3,V4), halfadder-{F}(V4), P_and2-{F}(V4,V2), P_or1-{F}(V3,V5), P_in1-{F}(V5,V6), zero-{F}(V6) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #312: exists( #66, #308 ), references = 1, size of lhs = 24:
% 7.62/7.81 halfadder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_and2-{F}(V0,V2), logic_not-{F}(V2), fulladder-{F}(V3), P_h2-{F}(V3,V4), halfadder-{F}(V4), P_and2-{F}(V4,V2), P_or1-{F}(V3,V5), P_in1-{F}(V5,V6), zero-{F}(V6), P_a-{F}(V7), P_ina1-{F}(V7,V8), P_inb1-{F}(V7,V9), P_inc-{F}(V7,V10), P_out1-{F}(V7,V11), P_outc-{F}(V7,V12), P_f1-{F}(V7,V13), P_or1-{F}(V13,V14), P_h1-{F}(V13,V15), P_and2-{F}(V15,V16), P_h2-{F}(V13,V17), P_and2-{F}(V17,V2) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #316: exists( #70, #310 ), references = 1, size of lhs = 23:
% 7.62/7.81 halfadder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_and2-{F}(V0,V2), logic_not-{F}(V2), fulladder-{F}(V3), P_h2-{F}(V3,V4), halfadder-{F}(V4), P_and2-{F}(V4,V2), P_or1-{F}(V3,V5), P_in1-{F}(V5,V6), zero-{F}(V6), P_a-{F}(V7), P_ina1-{F}(V7,V8), P_inb1-{F}(V7,V9), P_inc-{F}(V7,V10), P_out1-{F}(V7,V11), P_outc-{F}(V7,V12), P_f1-{F}(V7,V13), P_or1-{F}(V13,V14), P_h1-{F}(V13,V15), P_h2-{F}(V13,V16), P_and2-{F}(V16,V2) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #317: exists( #70, #313 ), references = 1, size of lhs = 24:
% 7.62/7.81 logic_and-{F}(V0), logic_not-{F}(V0), P_a-{F}(V1), P_ina1-{F}(V1,V2), P_inb1-{F}(V1,V3), P_inc-{F}(V1,V4), P_out1-{F}(V1,V5), P_outc-{F}(V1,V6), P_f1-{F}(V1,V7), P_or1-{F}(V7,V8), P_h1-{F}(V7,V9), P_h2-{F}(V7,V10), P_and2-{F}(V10,V0), halfadder-{F}(V11), P_and2-{F}(V11,V0), P_in1-{F}(V11,V12), zero-{F}(V12), fulladder-{F}(V13), P_h2-{F}(V13,V14), halfadder-{F}(V14), P_and2-{F}(V14,V0), P_or1-{F}(V13,V15), P_in1-{F}(V15,V16), zero-{F}(V16) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #347: exists( #67, #345 ), references = 2, size of lhs = 11:
% 7.62/7.81 halfadder-{F}(V0), P_outc-{F}(V0,V1), zero-{F}(V1), P_and2-{F}(V0,V2), fulladder-{F}(V3), P_h1-{F}(V3,V4), halfadder-{F}(V4), P_and2-{F}(V4,V2), P_or1-{F}(V3,V5), P_in2-{F}(V5,V6), one-{F}(V6) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #372: disj( #12, input ), references = 1, size of lhs = 2:
% 7.62/7.81 logic_and-{F}(V0), or_ok-{F}(V0) | and_ok-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #373: disj( #12, input ), references = 1, size of lhs = 9:
% 7.62/7.81 logic_and-{F}(V0), P_a-{F}(V1), P_ina1-{F}(V1,V2), P_inb1-{F}(V1,V3), P_inc-{F}(V1,V4), P_out1-{F}(V1,V5), P_outc-{F}(V1,V6), P_f1-{F}(V1,V7), P_or1-{F}(V7,V0) | and_ok-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #398: disj( #12, input ), references = 3, size of lhs = 11:
% 7.62/7.81 logic_and-{F}(V0), P_a-{F}(V1), P_ina1-{F}(V1,V2), P_inb1-{F}(V1,V3), P_inc-{F}(V1,V4), P_out1-{F}(V1,V5), P_outc-{F}(V1,V6), P_f1-{F}(V1,V7), P_or1-{F}(V7,V8), P_h1-{F}(V7,V9), P_and2-{F}(V9,V0) | and_ok-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #407: disj( #20, input ), references = 1, size of lhs = 2:
% 7.62/7.81 logic_or-{F}(V0), and_ok-{F}(V0) | or_ok-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #408: disj( #20, input ), references = 2, size of lhs = 13:
% 7.62/7.81 logic_or-{F}(V0), P_a-{F}(V1), P_ina1-{F}(V1,V2), P_inb1-{F}(V1,V3), P_inc-{F}(V1,V4), P_out1-{F}(V1,V5), P_outc-{F}(V1,V6), P_f1-{F}(V1,V7), P_or1-{F}(V7,V8), P_h1-{F}(V7,V9), P_and2-{F}(V9,V10), P_h2-{F}(V7,V11), P_and2-{F}(V11,V0) | or_ok-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #439: exists( #68, #433 ), references = 2, size of lhs = 7:
% 7.62/7.81 halfadder-{F}(V0), P_in2-{F}(V0,V1), one-{F}(V1), P_and2-{F}(V0,V2), or_ok-{F}(V2), P_out1-{F}(V2,V3), zero-{F}(V3) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #440: exists( #68, #434 ), references = 2, size of lhs = 13:
% 7.62/7.81 halfadder-{F}(V0), P_in2-{F}(V0,V1), P_and2-{F}(V0,V2), or_ok-{F}(V2), P_out1-{F}(V2,V3), zero-{F}(V3), halfadder-{F}(V4), P_in2-{F}(V4,V5), one-{F}(V5), P_and2-{F}(V4,V6), halfadder-{F}(V7), P_or1-{F}(V7,V6), P_in2-{F}(V7,V1) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #441: exists( #68, #435 ), references = 1, size of lhs = 16:
% 7.62/7.81 halfadder-{F}(V0), P_in2-{F}(V0,V1), P_and2-{F}(V0,V2), or_ok-{F}(V2), P_out1-{F}(V2,V3), zero-{F}(V3), halfadder-{F}(V4), P_outc-{F}(V4,V1), P_and2-{F}(V4,V5), fulladder-{F}(V6), P_h1-{F}(V6,V7), halfadder-{F}(V7), P_and2-{F}(V7,V5), P_or1-{F}(V6,V8), P_in2-{F}(V8,V9), one-{F}(V9) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #451: exists( #67, #445 ), references = 1, size of lhs = 9:
% 7.62/7.81 halfadder-{F}(V0), P_outc-{F}(V0,V1), zero-{F}(V1), P_and2-{F}(V0,V2), or_ok-{F}(V2), halfadder-{F}(V3), P_and2-{F}(V3,V2), P_in2-{F}(V3,V4), one-{F}(V4) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #452: exists( #67, #446 ), references = 1, size of lhs = 15:
% 7.62/7.81 halfadder-{F}(V0), P_outc-{F}(V0,V1), zero-{F}(V1), P_and2-{F}(V0,V2), or_ok-{F}(V2), halfadder-{F}(V3), P_and2-{F}(V3,V2), P_in2-{F}(V3,V4), halfadder-{F}(V5), P_in2-{F}(V5,V6), one-{F}(V6), P_and2-{F}(V5,V7), halfadder-{F}(V8), P_or1-{F}(V8,V7), P_in2-{F}(V8,V4) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #459: exists( #70, #455 ), references = 2, size of lhs = 21:
% 7.62/7.81 logic_and-{F}(V0), logic_or-{F}(V0), P_a-{F}(V1), P_ina1-{F}(V1,V2), P_inb1-{F}(V1,V3), P_inc-{F}(V1,V4), P_out1-{F}(V1,V5), P_outc-{F}(V1,V6), P_f1-{F}(V1,V7), P_or1-{F}(V7,V8), P_h1-{F}(V7,V9), P_h2-{F}(V7,V10), P_and2-{F}(V10,V0), halfadder-{F}(V11), P_and2-{F}(V11,V0), P_outc-{F}(V11,V12), zero-{F}(V12), halfadder-{F}(V13), P_and2-{F}(V13,V0), P_in2-{F}(V13,V14), one-{F}(V14) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #460: exists( #70, #456 ), references = 1, size of lhs = 27:
% 7.62/7.81 logic_and-{F}(V0), logic_or-{F}(V0), P_a-{F}(V1), P_ina1-{F}(V1,V2), P_inb1-{F}(V1,V3), P_inc-{F}(V1,V4), P_out1-{F}(V1,V5), P_outc-{F}(V1,V6), P_f1-{F}(V1,V7), P_or1-{F}(V7,V8), P_h1-{F}(V7,V9), P_h2-{F}(V7,V10), P_and2-{F}(V10,V0), halfadder-{F}(V11), P_and2-{F}(V11,V0), P_outc-{F}(V11,V12), zero-{F}(V12), halfadder-{F}(V13), P_and2-{F}(V13,V0), P_in2-{F}(V13,V14), halfadder-{F}(V15), P_in2-{F}(V15,V16), one-{F}(V16), P_and2-{F}(V15,V17), halfadder-{F}(V18), P_or1-{F}(V18,V17), P_in2-{F}(V18,V14) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #468: exists( #74, #466 ), references = 1, size of lhs = 24:
% 7.62/7.81 fulladder-{F}(V0), P_h2-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in1-{F}(V2,V3), zero-{F}(V3), logic_and-{F}(V4), logic_or-{F}(V4), P_and2-{F}(V1,V4), P_a-{F}(V5), P_ina1-{F}(V5,V6), P_inb1-{F}(V5,V7), P_inc-{F}(V5,V8), P_out1-{F}(V5,V9), P_outc-{F}(V5,V10), P_f1-{F}(V5,V11), P_or1-{F}(V11,V12), P_h1-{F}(V11,V13), P_h2-{F}(V11,V14), P_and2-{F}(V14,V4), halfadder-{F}(V15), P_and2-{F}(V15,V4), P_in2-{F}(V15,V16), one-{F}(V16) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #487: exists( #68, #485 ), references = 1, size of lhs = 8:
% 7.62/7.81 fulladder-{F}(V0), P_inc-{F}(V0,V1), zero-{F}(V1), P_h1-{F}(V0,V2), halfadder-{F}(V3), P_or1-{F}(V3,V2), P_in2-{F}(V3,V4), one-{F}(V4) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #501: exists( #66, #499 ), references = 2, size of lhs = 9:
% 7.62/7.81 fulladder-{F}(V0), P_in2-{F}(V0,V1), zero-{F}(V1), P_h1-{F}(V0,V2), halfadder-{F}(V3), P_and1-{F}(V3,V2), P_or1-{F}(V3,V4), P_out1-{F}(V4,V5), one-{F}(V5) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #528: disj( #20, #14+#501 ), references = 1, size of lhs = 12:
% 7.62/7.81 logic_or-{F}(V0), P_in2-{F}(V0,V1), one-{F}(V1), P_out1-{F}(V0,V2), fulladder-{F}(V3), P_in2-{F}(V3,V4), zero-{F}(V4), P_h1-{F}(V3,V5), halfadder-{F}(V6), P_and1-{F}(V6,V5), P_or1-{F}(V6,V7), P_out1-{F}(V7,V2) | abnormal-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #529: disj( #20, #18+#105 ), references = 1, size of lhs = 9:
% 7.62/7.81 logic_or-{F}(V0), P_out1-{F}(V0,V1), zero-{F}(V1), P_in2-{F}(V0,V2), P_a-{F}(V3), P_outc-{F}(V3,V2), P_ina1-{F}(V3,V4), P_inc-{F}(V3,V5), P_out1-{F}(V3,V6) | abnormal-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #530: disj( #20, #18+#4 ), references = 1, size of lhs = 5:
% 7.62/7.81 logic_or-{F}(V0), P_out1-{F}(V0,V1), zero-{F}(V1), P_in2-{F}(V0,V2), one-{F}(V2) | abnormal-{T}(V0)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #536: exists( #67, #531 ), references = 2, size of lhs = 10:
% 7.62/7.81 and_ok-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), fulladder-{F}(V2), P_h1-{F}(V2,V3), halfadder-{F}(V3), P_and2-{F}(V3,V0), P_or1-{F}(V2,V4), P_in2-{F}(V4,V5), one-{F}(V5) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #537: exists( #67, #532 ), references = 1, size of lhs = 10:
% 7.62/7.81 and_ok-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), fulladder-{F}(V2), P_h1-{F}(V2,V3), halfadder-{F}(V3), P_and1-{F}(V3,V0), P_h2-{F}(V2,V4), P_in2-{F}(V4,V5), one-{F}(V5) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #545: exists( #66, #543 ), references = 2, size of lhs = 12:
% 7.62/7.81 halfadder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_and2-{F}(V0,V2), and_ok-{F}(V2), fulladder-{F}(V3), P_h1-{F}(V3,V4), halfadder-{F}(V4), P_and2-{F}(V4,V2), P_or1-{F}(V3,V5), P_in2-{F}(V5,V6), one-{F}(V6) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #550: exists( #70, #548 ), references = 2, size of lhs = 17:
% 7.62/7.81 P_a-{F}(V0), P_ina1-{F}(V0,V1), P_inb1-{F}(V0,V2), P_inc-{F}(V0,V3), P_out1-{F}(V0,V4), P_outc-{F}(V0,V5), P_f1-{F}(V0,V6), P_or1-{F}(V6,V7), P_h1-{F}(V6,V8), halfadder-{F}(V8), P_in1-{F}(V8,V9), zero-{F}(V9), fulladder-{F}(V10), P_h1-{F}(V10,V8), P_or1-{F}(V10,V11), P_in2-{F}(V11,V12), one-{F}(V12) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #554: exists( #66, #552 ), references = 2, size of lhs = 19:
% 7.62/7.81 fulladder-{F}(V0), P_in2-{F}(V0,V1), zero-{F}(V1), P_h1-{F}(V0,V2), halfadder-{F}(V2), P_a-{F}(V3), P_ina1-{F}(V3,V4), P_inb1-{F}(V3,V5), P_inc-{F}(V3,V6), P_out1-{F}(V3,V7), P_outc-{F}(V3,V8), P_f1-{F}(V3,V9), P_h1-{F}(V9,V2), P_or1-{F}(V9,V10), fulladder-{F}(V11), P_h1-{F}(V11,V2), P_or1-{F}(V11,V12), P_in2-{F}(V12,V13), one-{F}(V13) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #608: exists( #67, #606 ), references = 1, size of lhs = 14:
% 7.62/7.81 halfadder-{F}(V0), P_or1-{F}(V0,V1), P_and1-{F}(V0,V2), P_in1-{F}(V2,V3), zero-{F}(V3), halfadder-{F}(V4), P_and1-{F}(V4,V1), P_outs-{F}(V4,V5), or_ok-{F}(V6), P_in2-{F}(V6,V5), P_in1-{F}(V6,V7), zero-{F}(V7), P_out1-{F}(V6,V8), one-{F}(V8) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #639: exists( #67, #637 ), references = 1, size of lhs = 15:
% 7.62/7.81 halfadder-{F}(V0), P_or1-{F}(V0,V1), P_and1-{F}(V0,V2), P_in1-{F}(V2,V3), zero-{F}(V3), halfadder-{F}(V4), P_and1-{F}(V4,V1), P_outs-{F}(V4,V5), connection-{F}(V5,V6), or_ok-{F}(V7), P_in2-{F}(V7,V6), P_in1-{F}(V7,V8), zero-{F}(V8), P_out1-{F}(V7,V9), one-{F}(V9) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #642: exists( #73, #640 ), references = 2, size of lhs = 17:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_h2-{F}(V0,V2), P_in2-{F}(V2,V3), halfadder-{F}(V4), P_or1-{F}(V4,V5), P_and1-{F}(V1,V5), P_and1-{F}(V4,V6), P_in1-{F}(V6,V7), zero-{F}(V7), or_ok-{F}(V8), P_in2-{F}(V8,V3), P_in1-{F}(V8,V9), zero-{F}(V9), P_out1-{F}(V8,V10), one-{F}(V10) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #675: exists( #73, #673 ), references = 2, size of lhs = 14:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_h2-{F}(V0,V2), P_in2-{F}(V2,V3), P_and1-{F}(V1,V4), P_out1-{F}(V4,V5), zero-{F}(V5), or_ok-{F}(V6), P_in2-{F}(V6,V3), P_in1-{F}(V6,V7), zero-{F}(V7), P_out1-{F}(V6,V8), one-{F}(V8) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #722: exists( #67, #720 ), references = 1, size of lhs = 14:
% 7.62/7.81 halfadder-{F}(V0), P_or1-{F}(V0,V1), P_and1-{F}(V0,V2), P_in1-{F}(V2,V3), zero-{F}(V3), halfadder-{F}(V4), P_and2-{F}(V4,V1), P_outc-{F}(V4,V5), or_ok-{F}(V6), P_in2-{F}(V6,V5), P_in1-{F}(V6,V7), zero-{F}(V7), P_out1-{F}(V6,V8), one-{F}(V8) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #747: exists( #67, #745 ), references = 1, size of lhs = 15:
% 7.62/7.81 halfadder-{F}(V0), P_or1-{F}(V0,V1), P_and1-{F}(V0,V2), P_in1-{F}(V2,V3), zero-{F}(V3), halfadder-{F}(V4), P_and2-{F}(V4,V1), P_outc-{F}(V4,V5), connection-{F}(V5,V6), or_ok-{F}(V7), P_in2-{F}(V7,V6), P_in1-{F}(V7,V8), zero-{F}(V8), P_out1-{F}(V7,V9), one-{F}(V9) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #750: exists( #74, #748 ), references = 1, size of lhs = 17:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in2-{F}(V2,V3), halfadder-{F}(V4), P_or1-{F}(V4,V5), P_and2-{F}(V1,V5), P_and1-{F}(V4,V6), P_in1-{F}(V6,V7), zero-{F}(V7), or_ok-{F}(V8), P_in2-{F}(V8,V3), P_in1-{F}(V8,V9), zero-{F}(V9), P_out1-{F}(V8,V10), one-{F}(V10) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #780: exists( #74, #778 ), references = 6, size of lhs = 14:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in2-{F}(V2,V3), P_and2-{F}(V1,V4), P_out1-{F}(V4,V5), zero-{F}(V5), or_ok-{F}(V6), P_in2-{F}(V6,V3), P_in1-{F}(V6,V7), zero-{F}(V7), P_out1-{F}(V6,V8), one-{F}(V8) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #787: exists( #68, #785 ), references = 2, size of lhs = 12:
% 7.62/7.81 halfadder-{F}(V0), P_in2-{F}(V0,V1), P_and2-{F}(V0,V2), or_ok-{F}(V2), P_out1-{F}(V2,V3), zero-{F}(V3), or_ok-{F}(V4), P_in2-{F}(V4,V1), P_in1-{F}(V4,V5), zero-{F}(V5), P_out1-{F}(V4,V6), one-{F}(V6) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #791: exists( #67, #789 ), references = 1, size of lhs = 15:
% 7.62/7.81 halfadder-{F}(V0), P_or1-{F}(V0,V1), or_ok-{F}(V1), P_and1-{F}(V0,V2), P_in1-{F}(V2,V3), zero-{F}(V3), halfadder-{F}(V4), P_and2-{F}(V4,V1), P_in2-{F}(V4,V5), or_ok-{F}(V6), P_in2-{F}(V6,V5), P_in1-{F}(V6,V7), zero-{F}(V7), P_out1-{F}(V6,V8), one-{F}(V8) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #794: exists( #70, #792 ), references = 2, size of lhs = 26:
% 7.62/7.81 logic_or-{F}(V0), P_a-{F}(V1), P_ina1-{F}(V1,V2), P_inb1-{F}(V1,V3), P_inc-{F}(V1,V4), P_out1-{F}(V1,V5), P_outc-{F}(V1,V6), P_f1-{F}(V1,V7), P_or1-{F}(V7,V8), P_h1-{F}(V7,V9), P_h2-{F}(V7,V10), P_and2-{F}(V10,V0), halfadder-{F}(V11), P_or1-{F}(V11,V0), P_and1-{F}(V11,V12), P_in1-{F}(V12,V13), zero-{F}(V13), halfadder-{F}(V14), P_and2-{F}(V14,V0), P_in2-{F}(V14,V15), or_ok-{F}(V16), P_in2-{F}(V16,V15), P_in1-{F}(V16,V17), zero-{F}(V17), P_out1-{F}(V16,V18), one-{F}(V18) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #821: exists( #68, #819 ), references = 1, size of lhs = 13:
% 7.62/7.81 fulladder-{F}(V0), P_inc-{F}(V0,V1), zero-{F}(V1), P_h1-{F}(V0,V2), halfadder-{F}(V3), P_or1-{F}(V3,V2), P_in2-{F}(V3,V4), or_ok-{F}(V5), P_in2-{F}(V5,V4), P_in1-{F}(V5,V6), zero-{F}(V6), P_out1-{F}(V5,V7), one-{F}(V7) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #852: exists( #66, #847 ), references = 1, size of lhs = 19:
% 7.62/7.81 halfadder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_and2-{F}(V0,V2), fulladder-{F}(V3), P_h1-{F}(V3,V4), halfadder-{F}(V4), P_h2-{F}(V3,V5), P_in2-{F}(V5,V6), halfadder-{F}(V7), P_and1-{F}(V7,V2), P_or1-{F}(V7,V8), P_and1-{F}(V4,V8), or_ok-{F}(V9), P_in2-{F}(V9,V6), P_in1-{F}(V9,V10), zero-{F}(V10), P_out1-{F}(V9,V11), one-{F}(V11) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #853: exists( #66, #848 ), references = 1, size of lhs = 28:
% 7.62/7.81 halfadder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_and2-{F}(V0,V2), logic_or-{F}(V3), P_a-{F}(V4), P_ina1-{F}(V4,V5), P_inb1-{F}(V4,V6), P_inc-{F}(V4,V7), P_out1-{F}(V4,V8), P_outc-{F}(V4,V9), P_f1-{F}(V4,V10), P_or1-{F}(V10,V11), P_h1-{F}(V10,V12), P_h2-{F}(V10,V13), P_and2-{F}(V13,V3), halfadder-{F}(V14), P_or1-{F}(V14,V3), P_and1-{F}(V14,V2), halfadder-{F}(V15), P_and2-{F}(V15,V3), P_in2-{F}(V15,V16), or_ok-{F}(V17), P_in2-{F}(V17,V16), P_in1-{F}(V17,V18), zero-{F}(V18), P_out1-{F}(V17,V19), one-{F}(V19) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #869: exists( #67, #867 ), references = 2, size of lhs = 15:
% 7.62/7.81 and_ok-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), fulladder-{F}(V2), P_h1-{F}(V2,V3), halfadder-{F}(V3), P_and1-{F}(V3,V0), P_h2-{F}(V2,V4), P_in2-{F}(V4,V5), or_ok-{F}(V6), P_in2-{F}(V6,V5), P_in1-{F}(V6,V7), zero-{F}(V7), P_out1-{F}(V6,V8), one-{F}(V8) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #877: exists( #66, #875 ), references = 1, size of lhs = 17:
% 7.62/7.81 halfadder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_and2-{F}(V0,V2), and_ok-{F}(V2), fulladder-{F}(V3), P_h1-{F}(V3,V4), halfadder-{F}(V4), P_and1-{F}(V4,V2), P_h2-{F}(V3,V5), P_in2-{F}(V5,V6), or_ok-{F}(V7), P_in2-{F}(V7,V6), P_in1-{F}(V7,V8), zero-{F}(V8), P_out1-{F}(V7,V9), one-{F}(V9) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #880: exists( #70, #878 ), references = 1, size of lhs = 28:
% 7.62/7.81 logic_and-{F}(V0), P_a-{F}(V1), P_ina1-{F}(V1,V2), P_inb1-{F}(V1,V3), P_inc-{F}(V1,V4), P_out1-{F}(V1,V5), P_outc-{F}(V1,V6), P_f1-{F}(V1,V7), P_or1-{F}(V7,V8), P_h1-{F}(V7,V9), P_h2-{F}(V7,V10), P_and2-{F}(V10,V0), halfadder-{F}(V11), P_and2-{F}(V11,V0), P_in1-{F}(V11,V12), zero-{F}(V12), fulladder-{F}(V13), P_h1-{F}(V13,V14), halfadder-{F}(V14), P_and1-{F}(V14,V0), P_h2-{F}(V13,V15), P_in2-{F}(V15,V16), or_ok-{F}(V17), P_in2-{F}(V17,V16), P_in1-{F}(V17,V18), zero-{F}(V18), P_out1-{F}(V17,V19), one-{F}(V19) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #902: exists( #67, #900 ), references = 3, size of lhs = 15:
% 7.62/7.81 and_ok-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), fulladder-{F}(V2), P_h1-{F}(V2,V3), halfadder-{F}(V3), P_and2-{F}(V3,V0), P_or1-{F}(V2,V4), P_in2-{F}(V4,V5), or_ok-{F}(V6), P_in2-{F}(V6,V5), P_in1-{F}(V6,V7), zero-{F}(V7), P_out1-{F}(V6,V8), one-{F}(V8) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #906: exists( #66, #904 ), references = 2, size of lhs = 17:
% 7.62/7.81 halfadder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_and2-{F}(V0,V2), and_ok-{F}(V2), fulladder-{F}(V3), P_h1-{F}(V3,V4), halfadder-{F}(V4), P_and2-{F}(V4,V2), P_or1-{F}(V3,V5), P_in2-{F}(V5,V6), or_ok-{F}(V7), P_in2-{F}(V7,V6), P_in1-{F}(V7,V8), zero-{F}(V8), P_out1-{F}(V7,V9), one-{F}(V9) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #915: exists( #70, #913 ), references = 2, size of lhs = 22:
% 7.62/7.81 P_a-{F}(V0), P_ina1-{F}(V0,V1), P_inb1-{F}(V0,V2), P_inc-{F}(V0,V3), P_out1-{F}(V0,V4), P_outc-{F}(V0,V5), P_f1-{F}(V0,V6), P_or1-{F}(V6,V7), P_h1-{F}(V6,V8), halfadder-{F}(V8), P_in1-{F}(V8,V9), zero-{F}(V9), fulladder-{F}(V10), P_h1-{F}(V10,V8), P_or1-{F}(V10,V11), P_in2-{F}(V11,V12), or_ok-{F}(V13), P_in2-{F}(V13,V12), P_in1-{F}(V13,V14), zero-{F}(V14), P_out1-{F}(V13,V15), one-{F}(V15) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #921: exists( #66, #919 ), references = 2, size of lhs = 24:
% 7.62/7.81 fulladder-{F}(V0), P_in2-{F}(V0,V1), zero-{F}(V1), P_h1-{F}(V0,V2), halfadder-{F}(V2), P_a-{F}(V3), P_ina1-{F}(V3,V4), P_inb1-{F}(V3,V5), P_inc-{F}(V3,V6), P_out1-{F}(V3,V7), P_outc-{F}(V3,V8), P_f1-{F}(V3,V9), P_h1-{F}(V9,V2), P_or1-{F}(V9,V10), fulladder-{F}(V11), P_h1-{F}(V11,V2), P_or1-{F}(V11,V12), P_in2-{F}(V12,V13), or_ok-{F}(V14), P_in2-{F}(V14,V13), P_in1-{F}(V14,V15), zero-{F}(V15), P_out1-{F}(V14,V16), one-{F}(V16) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #923: exists( #68, #920 ), references = 5, size of lhs = 22:
% 7.62/7.81 fulladder-{F}(V0), P_in2-{F}(V0,V1), zero-{F}(V1), P_h1-{F}(V0,V2), halfadder-{F}(V2), P_a-{F}(V3), P_ina1-{F}(V3,V4), P_inb1-{F}(V3,V5), P_inc-{F}(V3,V6), P_out1-{F}(V3,V7), P_outc-{F}(V3,V8), P_f1-{F}(V3,V9), P_h1-{F}(V9,V2), P_or1-{F}(V9,V10), fulladder-{F}(V11), P_h1-{F}(V11,V2), P_or1-{F}(V11,V12), or_ok-{F}(V12), P_in1-{F}(V12,V13), zero-{F}(V13), P_out1-{F}(V12,V14), one-{F}(V14) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #927: exists( #67, #925 ), references = 7, size of lhs = 24:
% 7.62/7.81 fulladder-{F}(V0), P_outc-{F}(V0,V1), one-{F}(V1), P_or1-{F}(V0,V2), or_ok-{F}(V2), fulladder-{F}(V3), P_in2-{F}(V3,V4), zero-{F}(V4), P_h1-{F}(V3,V5), halfadder-{F}(V5), P_a-{F}(V6), P_ina1-{F}(V6,V7), P_inb1-{F}(V6,V8), P_inc-{F}(V6,V9), P_out1-{F}(V6,V10), P_outc-{F}(V6,V11), P_f1-{F}(V6,V12), P_h1-{F}(V12,V5), P_or1-{F}(V12,V13), fulladder-{F}(V14), P_h1-{F}(V14,V5), P_or1-{F}(V14,V2), P_in1-{F}(V2,V15), zero-{F}(V15) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #931: exists( #66, #929 ), references = 1, size of lhs = 26:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), or_ok-{F}(V2), fulladder-{F}(V3), P_or1-{F}(V3,V2), P_outc-{F}(V3,V4), one-{F}(V4), fulladder-{F}(V5), P_in2-{F}(V5,V6), zero-{F}(V6), P_h1-{F}(V5,V7), halfadder-{F}(V7), P_a-{F}(V8), P_ina1-{F}(V8,V9), P_inb1-{F}(V8,V10), P_inc-{F}(V8,V11), P_out1-{F}(V8,V12), P_outc-{F}(V8,V13), P_f1-{F}(V8,V14), P_h1-{F}(V14,V7), P_or1-{F}(V14,V15), fulladder-{F}(V16), P_h1-{F}(V16,V7), P_or1-{F}(V16,V2) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #986: exists( #73, #984 ), references = 1, size of lhs = 8:
% 7.62/7.81 fulladder-{F}(V0), P_outs-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), halfadder-{F}(V2), P_and1-{F}(V2,V3), P_out1-{F}(V3,V4), one-{F}(V4) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1040: exists( #74, #1038 ), references = 2, size of lhs = 9:
% 7.62/7.81 fulladder-{F}(V0), P_h2-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in1-{F}(V2,V3), one-{F}(V3), P_and2-{F}(V1,V4), P_out1-{F}(V4,V5), zero-{F}(V5) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1056: exists( #67, #1053 ), references = 2, size of lhs = 10:
% 7.62/7.81 and_ok-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), fulladder-{F}(V2), P_h2-{F}(V2,V3), halfadder-{F}(V3), P_and2-{F}(V3,V0), P_or1-{F}(V2,V4), P_in1-{F}(V4,V5), one-{F}(V5) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1066: exists( #66, #1064 ), references = 1, size of lhs = 12:
% 7.62/7.81 halfadder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_and2-{F}(V0,V2), and_ok-{F}(V2), fulladder-{F}(V3), P_h2-{F}(V3,V4), halfadder-{F}(V4), P_and2-{F}(V4,V2), P_or1-{F}(V3,V5), P_in1-{F}(V5,V6), one-{F}(V6) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1070: exists( #70, #1068 ), references = 1, size of lhs = 19:
% 7.62/7.81 P_a-{F}(V0), P_ina1-{F}(V0,V1), P_inb1-{F}(V0,V2), P_inc-{F}(V0,V3), P_out1-{F}(V0,V4), P_outc-{F}(V0,V5), P_f1-{F}(V0,V6), P_or1-{F}(V6,V7), P_h1-{F}(V6,V8), P_and2-{F}(V8,V9), P_h2-{F}(V6,V10), halfadder-{F}(V10), P_in1-{F}(V10,V11), zero-{F}(V11), fulladder-{F}(V12), P_h2-{F}(V12,V10), P_or1-{F}(V12,V13), P_in1-{F}(V13,V14), one-{F}(V14) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1074: exists( #66, #1072 ), references = 1, size of lhs = 21:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), halfadder-{F}(V2), P_a-{F}(V3), P_ina1-{F}(V3,V4), P_inb1-{F}(V3,V5), P_inc-{F}(V3,V6), P_out1-{F}(V3,V7), P_outc-{F}(V3,V8), P_f1-{F}(V3,V9), P_h2-{F}(V9,V2), P_or1-{F}(V9,V10), P_h1-{F}(V9,V11), P_and2-{F}(V11,V12), fulladder-{F}(V13), P_h2-{F}(V13,V2), P_or1-{F}(V13,V14), P_in1-{F}(V14,V15), one-{F}(V15) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1076: exists( #70, #1073 ), references = 1, size of lhs = 20:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), halfadder-{F}(V2), P_a-{F}(V3), P_ina1-{F}(V3,V4), P_inb1-{F}(V3,V5), P_inc-{F}(V3,V6), P_out1-{F}(V3,V7), P_outc-{F}(V3,V8), P_f1-{F}(V3,V9), P_h2-{F}(V9,V2), P_or1-{F}(V9,V10), P_h1-{F}(V9,V11), fulladder-{F}(V12), P_h2-{F}(V12,V2), P_or1-{F}(V12,V13), P_in1-{F}(V13,V14), one-{F}(V14) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1122: exists( #67, #1116 ), references = 1, size of lhs = 31:
% 7.62/7.81 halfadder-{F}(V0), P_and2-{F}(V0,V1), P_not1-{F}(V0,V2), P_in1-{F}(V2,V3), zero-{F}(V3), halfadder-{F}(V4), P_and2-{F}(V4,V1), P_outc-{F}(V4,V5), fulladder-{F}(V6), P_outc-{F}(V6,V7), one-{F}(V7), P_or1-{F}(V6,V8), or_ok-{F}(V8), P_in1-{F}(V8,V5), fulladder-{F}(V9), P_in2-{F}(V9,V10), zero-{F}(V10), P_h1-{F}(V9,V11), halfadder-{F}(V11), P_a-{F}(V12), P_ina1-{F}(V12,V13), P_inb1-{F}(V12,V14), P_inc-{F}(V12,V15), P_out1-{F}(V12,V16), P_outc-{F}(V12,V17), P_f1-{F}(V12,V18), P_h1-{F}(V18,V11), P_or1-{F}(V18,V19), fulladder-{F}(V20), P_h1-{F}(V20,V11), P_or1-{F}(V20,V8) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1123: exists( #67, #1117 ), references = 1, size of lhs = 29:
% 7.62/7.81 halfadder-{F}(V0), P_and2-{F}(V0,V1), P_not1-{F}(V0,V2), P_in1-{F}(V2,V3), zero-{F}(V3), halfadder-{F}(V4), P_and2-{F}(V4,V1), P_outc-{F}(V4,V5), fulladder-{F}(V6), P_in2-{F}(V6,V7), zero-{F}(V7), P_h1-{F}(V6,V8), halfadder-{F}(V8), P_a-{F}(V9), P_ina1-{F}(V9,V10), P_inb1-{F}(V9,V11), P_inc-{F}(V9,V12), P_out1-{F}(V9,V13), P_outc-{F}(V9,V14), P_f1-{F}(V9,V15), P_h1-{F}(V15,V8), P_or1-{F}(V15,V16), fulladder-{F}(V17), P_h1-{F}(V17,V8), P_or1-{F}(V17,V18), or_ok-{F}(V18), P_in1-{F}(V18,V5), P_out1-{F}(V18,V19), one-{F}(V19) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1124: exists( #67, #1118 ), references = 1, size of lhs = 19:
% 7.62/7.81 halfadder-{F}(V0), P_and2-{F}(V0,V1), P_not1-{F}(V0,V2), P_in1-{F}(V2,V3), zero-{F}(V3), halfadder-{F}(V4), P_and2-{F}(V4,V1), P_outc-{F}(V4,V5), fulladder-{F}(V6), P_h1-{F}(V6,V7), halfadder-{F}(V7), P_and2-{F}(V7,V1), P_or1-{F}(V6,V8), P_in2-{F}(V8,V9), or_ok-{F}(V10), P_in2-{F}(V10,V9), P_in1-{F}(V10,V5), P_out1-{F}(V10,V11), one-{F}(V11) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1161: exists( #67, #1155 ), references = 1, size of lhs = 32:
% 7.62/7.81 halfadder-{F}(V0), P_and2-{F}(V0,V1), P_not1-{F}(V0,V2), P_in1-{F}(V2,V3), zero-{F}(V3), halfadder-{F}(V4), P_and2-{F}(V4,V1), P_outc-{F}(V4,V5), fulladder-{F}(V6), P_outc-{F}(V6,V7), one-{F}(V7), P_or1-{F}(V6,V8), or_ok-{F}(V8), P_in1-{F}(V8,V9), connection-{F}(V5,V9), fulladder-{F}(V10), P_in2-{F}(V10,V11), zero-{F}(V11), P_h1-{F}(V10,V12), halfadder-{F}(V12), P_a-{F}(V13), P_ina1-{F}(V13,V14), P_inb1-{F}(V13,V15), P_inc-{F}(V13,V16), P_out1-{F}(V13,V17), P_outc-{F}(V13,V18), P_f1-{F}(V13,V19), P_h1-{F}(V19,V12), P_or1-{F}(V19,V20), fulladder-{F}(V21), P_h1-{F}(V21,V12), P_or1-{F}(V21,V8) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1162: exists( #67, #1156 ), references = 1, size of lhs = 20:
% 7.62/7.81 halfadder-{F}(V0), P_and2-{F}(V0,V1), P_not1-{F}(V0,V2), P_in1-{F}(V2,V3), zero-{F}(V3), halfadder-{F}(V4), P_and2-{F}(V4,V1), P_outc-{F}(V4,V5), fulladder-{F}(V6), P_h1-{F}(V6,V7), halfadder-{F}(V7), P_and2-{F}(V7,V1), P_or1-{F}(V6,V8), P_in2-{F}(V8,V9), connection-{F}(V5,V10), or_ok-{F}(V11), P_in2-{F}(V11,V9), P_in1-{F}(V11,V10), P_out1-{F}(V11,V12), one-{F}(V12) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1163: exists( #67, #1157 ), references = 1, size of lhs = 30:
% 7.62/7.81 halfadder-{F}(V0), P_and2-{F}(V0,V1), P_not1-{F}(V0,V2), P_in1-{F}(V2,V3), zero-{F}(V3), halfadder-{F}(V4), P_and2-{F}(V4,V1), P_outc-{F}(V4,V5), fulladder-{F}(V6), P_in2-{F}(V6,V7), zero-{F}(V7), P_h1-{F}(V6,V8), halfadder-{F}(V8), P_a-{F}(V9), P_ina1-{F}(V9,V10), P_inb1-{F}(V9,V11), P_inc-{F}(V9,V12), P_out1-{F}(V9,V13), P_outc-{F}(V9,V14), P_f1-{F}(V9,V15), P_h1-{F}(V15,V8), P_or1-{F}(V15,V16), fulladder-{F}(V17), P_h1-{F}(V17,V8), P_or1-{F}(V17,V18), or_ok-{F}(V18), P_in1-{F}(V18,V19), connection-{F}(V5,V19), P_out1-{F}(V18,V20), one-{F}(V20) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1170: exists( #74, #1164 ), references = 2, size of lhs = 34:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in2-{F}(V2,V3), halfadder-{F}(V4), P_and2-{F}(V4,V5), P_and2-{F}(V1,V5), P_not1-{F}(V4,V6), P_in1-{F}(V6,V7), zero-{F}(V7), fulladder-{F}(V8), P_outc-{F}(V8,V9), one-{F}(V9), P_or1-{F}(V8,V10), or_ok-{F}(V10), P_in1-{F}(V10,V3), fulladder-{F}(V11), P_in2-{F}(V11,V12), zero-{F}(V12), P_h1-{F}(V11,V13), halfadder-{F}(V13), P_a-{F}(V14), P_ina1-{F}(V14,V15), P_inb1-{F}(V14,V16), P_inc-{F}(V14,V17), P_out1-{F}(V14,V18), P_outc-{F}(V14,V19), P_f1-{F}(V14,V20), P_h1-{F}(V20,V13), P_or1-{F}(V20,V21), fulladder-{F}(V22), P_h1-{F}(V22,V13), P_or1-{F}(V22,V10) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1171: exists( #74, #1165 ), references = 2, size of lhs = 22:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in2-{F}(V2,V3), halfadder-{F}(V4), P_and2-{F}(V4,V5), P_and2-{F}(V1,V5), P_not1-{F}(V4,V6), P_in1-{F}(V6,V7), zero-{F}(V7), fulladder-{F}(V8), P_h1-{F}(V8,V9), halfadder-{F}(V9), P_and2-{F}(V9,V5), P_or1-{F}(V8,V10), P_in2-{F}(V10,V11), or_ok-{F}(V12), P_in2-{F}(V12,V11), P_in1-{F}(V12,V3), P_out1-{F}(V12,V13), one-{F}(V13) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1172: exists( #74, #1166 ), references = 2, size of lhs = 32:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in2-{F}(V2,V3), halfadder-{F}(V4), P_and2-{F}(V4,V5), P_and2-{F}(V1,V5), P_not1-{F}(V4,V6), P_in1-{F}(V6,V7), zero-{F}(V7), fulladder-{F}(V8), P_in2-{F}(V8,V9), zero-{F}(V9), P_h1-{F}(V8,V10), halfadder-{F}(V10), P_a-{F}(V11), P_ina1-{F}(V11,V12), P_inb1-{F}(V11,V13), P_inc-{F}(V11,V14), P_out1-{F}(V11,V15), P_outc-{F}(V11,V16), P_f1-{F}(V11,V17), P_h1-{F}(V17,V10), P_or1-{F}(V17,V18), fulladder-{F}(V19), P_h1-{F}(V19,V10), P_or1-{F}(V19,V20), or_ok-{F}(V20), P_in1-{F}(V20,V3), P_out1-{F}(V20,V21), one-{F}(V21) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1186: exists( #67, #1184 ), references = 2, size of lhs = 8:
% 7.62/7.81 halfadder-{F}(V0), P_and2-{F}(V0,V1), and_ok-{F}(V1), P_not1-{F}(V0,V2), P_in1-{F}(V2,V3), one-{F}(V3), P_in1-{F}(V1,V4), zero-{F}(V4) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1196: exists( #66, #1194 ), references = 1, size of lhs = 10:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), and_ok-{F}(V2), halfadder-{F}(V3), P_and2-{F}(V3,V2), P_not1-{F}(V3,V4), P_in1-{F}(V4,V5), one-{F}(V5) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1224: exists( #66, #1218 ), references = 1, size of lhs = 36:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), fulladder-{F}(V3), P_h1-{F}(V3,V4), halfadder-{F}(V4), P_or1-{F}(V3,V5), P_in2-{F}(V5,V6), halfadder-{F}(V7), P_not1-{F}(V7,V2), P_and2-{F}(V7,V8), P_and2-{F}(V4,V8), fulladder-{F}(V9), P_outc-{F}(V9,V10), one-{F}(V10), P_or1-{F}(V9,V11), or_ok-{F}(V11), P_in1-{F}(V11,V6), fulladder-{F}(V12), P_in2-{F}(V12,V13), zero-{F}(V13), P_h1-{F}(V12,V14), halfadder-{F}(V14), P_a-{F}(V15), P_ina1-{F}(V15,V16), P_inb1-{F}(V15,V17), P_inc-{F}(V15,V18), P_out1-{F}(V15,V19), P_outc-{F}(V15,V20), P_f1-{F}(V15,V21), P_h1-{F}(V21,V14), P_or1-{F}(V21,V22), fulladder-{F}(V23), P_h1-{F}(V23,V14), P_or1-{F}(V23,V11) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1225: exists( #66, #1219 ), references = 1, size of lhs = 24:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), fulladder-{F}(V3), P_h1-{F}(V3,V4), halfadder-{F}(V4), P_or1-{F}(V3,V5), P_in2-{F}(V5,V6), halfadder-{F}(V7), P_not1-{F}(V7,V2), P_and2-{F}(V7,V8), P_and2-{F}(V4,V8), fulladder-{F}(V9), P_h1-{F}(V9,V10), halfadder-{F}(V10), P_and2-{F}(V10,V8), P_or1-{F}(V9,V11), P_in2-{F}(V11,V12), or_ok-{F}(V13), P_in2-{F}(V13,V12), P_in1-{F}(V13,V6), P_out1-{F}(V13,V14), one-{F}(V14) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1226: exists( #66, #1220 ), references = 1, size of lhs = 34:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), fulladder-{F}(V3), P_h1-{F}(V3,V4), halfadder-{F}(V4), P_or1-{F}(V3,V5), P_in2-{F}(V5,V6), halfadder-{F}(V7), P_not1-{F}(V7,V2), P_and2-{F}(V7,V8), P_and2-{F}(V4,V8), fulladder-{F}(V9), P_in2-{F}(V9,V10), zero-{F}(V10), P_h1-{F}(V9,V11), halfadder-{F}(V11), P_a-{F}(V12), P_ina1-{F}(V12,V13), P_inb1-{F}(V12,V14), P_inc-{F}(V12,V15), P_out1-{F}(V12,V16), P_outc-{F}(V12,V17), P_f1-{F}(V12,V18), P_h1-{F}(V18,V11), P_or1-{F}(V18,V19), fulladder-{F}(V20), P_h1-{F}(V20,V11), P_or1-{F}(V20,V21), or_ok-{F}(V21), P_in1-{F}(V21,V6), P_out1-{F}(V21,V22), one-{F}(V22) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1266: exists( #67, #1262 ), references = 2, size of lhs = 7:
% 7.62/7.81 halfadder-{F}(V0), P_outs-{F}(V0,V1), one-{F}(V1), P_and1-{F}(V0,V2), and_ok-{F}(V2), P_in1-{F}(V2,V3), zero-{F}(V3) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1267: exists( #67, #1263 ), references = 2, size of lhs = 11:
% 7.62/7.81 halfadder-{F}(V0), P_outs-{F}(V0,V1), P_and1-{F}(V0,V2), and_ok-{F}(V2), P_in1-{F}(V2,V3), zero-{F}(V3), P_a-{F}(V4), P_outc-{F}(V4,V1), P_ina1-{F}(V4,V5), P_inc-{F}(V4,V6), P_out1-{F}(V4,V7) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1274: exists( #66, #1270 ), references = 1, size of lhs = 9:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), and_ok-{F}(V2), halfadder-{F}(V3), P_and1-{F}(V3,V2), P_outs-{F}(V3,V4), one-{F}(V4) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1275: exists( #66, #1271 ), references = 1, size of lhs = 13:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), and_ok-{F}(V2), halfadder-{F}(V3), P_and1-{F}(V3,V2), P_outs-{F}(V3,V4), P_a-{F}(V5), P_outc-{F}(V5,V4), P_ina1-{F}(V5,V6), P_inc-{F}(V5,V7), P_out1-{F}(V5,V8) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1306: exists( #67, #1300 ), references = 2, size of lhs = 29:
% 7.62/7.81 halfadder-{F}(V0), P_outs-{F}(V0,V1), P_and1-{F}(V0,V2), and_ok-{F}(V2), P_in1-{F}(V2,V3), zero-{F}(V3), fulladder-{F}(V4), P_outc-{F}(V4,V5), one-{F}(V5), P_or1-{F}(V4,V6), or_ok-{F}(V6), P_in1-{F}(V6,V1), fulladder-{F}(V7), P_in2-{F}(V7,V8), zero-{F}(V8), P_h1-{F}(V7,V9), halfadder-{F}(V9), P_a-{F}(V10), P_ina1-{F}(V10,V11), P_inb1-{F}(V10,V12), P_inc-{F}(V10,V13), P_out1-{F}(V10,V14), P_outc-{F}(V10,V15), P_f1-{F}(V10,V16), P_h1-{F}(V16,V9), P_or1-{F}(V16,V17), fulladder-{F}(V18), P_h1-{F}(V18,V9), P_or1-{F}(V18,V6) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1307: exists( #67, #1301 ), references = 2, size of lhs = 27:
% 7.62/7.81 halfadder-{F}(V0), P_outs-{F}(V0,V1), P_and1-{F}(V0,V2), and_ok-{F}(V2), P_in1-{F}(V2,V3), zero-{F}(V3), fulladder-{F}(V4), P_in2-{F}(V4,V5), zero-{F}(V5), P_h1-{F}(V4,V6), halfadder-{F}(V6), P_a-{F}(V7), P_ina1-{F}(V7,V8), P_inb1-{F}(V7,V9), P_inc-{F}(V7,V10), P_out1-{F}(V7,V11), P_outc-{F}(V7,V12), P_f1-{F}(V7,V13), P_h1-{F}(V13,V6), P_or1-{F}(V13,V14), fulladder-{F}(V15), P_h1-{F}(V15,V6), P_or1-{F}(V15,V16), or_ok-{F}(V16), P_in1-{F}(V16,V1), P_out1-{F}(V16,V17), one-{F}(V17) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1308: exists( #67, #1302 ), references = 2, size of lhs = 17:
% 7.62/7.81 halfadder-{F}(V0), P_outs-{F}(V0,V1), P_and1-{F}(V0,V2), and_ok-{F}(V2), P_in1-{F}(V2,V3), zero-{F}(V3), fulladder-{F}(V4), P_h1-{F}(V4,V5), halfadder-{F}(V5), P_and2-{F}(V5,V2), P_or1-{F}(V4,V6), P_in2-{F}(V6,V7), or_ok-{F}(V8), P_in2-{F}(V8,V7), P_in1-{F}(V8,V1), P_out1-{F}(V8,V9), one-{F}(V9) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1318: exists( #66, #1312 ), references = 1, size of lhs = 31:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), and_ok-{F}(V2), halfadder-{F}(V3), P_and1-{F}(V3,V2), P_outs-{F}(V3,V4), fulladder-{F}(V5), P_outc-{F}(V5,V6), one-{F}(V6), P_or1-{F}(V5,V7), or_ok-{F}(V7), P_in1-{F}(V7,V4), fulladder-{F}(V8), P_in2-{F}(V8,V9), zero-{F}(V9), P_h1-{F}(V8,V10), halfadder-{F}(V10), P_a-{F}(V11), P_ina1-{F}(V11,V12), P_inb1-{F}(V11,V13), P_inc-{F}(V11,V14), P_out1-{F}(V11,V15), P_outc-{F}(V11,V16), P_f1-{F}(V11,V17), P_h1-{F}(V17,V10), P_or1-{F}(V17,V18), fulladder-{F}(V19), P_h1-{F}(V19,V10), P_or1-{F}(V19,V7) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1319: exists( #66, #1313 ), references = 1, size of lhs = 29:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), and_ok-{F}(V2), halfadder-{F}(V3), P_and1-{F}(V3,V2), P_outs-{F}(V3,V4), fulladder-{F}(V5), P_in2-{F}(V5,V6), zero-{F}(V6), P_h1-{F}(V5,V7), halfadder-{F}(V7), P_a-{F}(V8), P_ina1-{F}(V8,V9), P_inb1-{F}(V8,V10), P_inc-{F}(V8,V11), P_out1-{F}(V8,V12), P_outc-{F}(V8,V13), P_f1-{F}(V8,V14), P_h1-{F}(V14,V7), P_or1-{F}(V14,V15), fulladder-{F}(V16), P_h1-{F}(V16,V7), P_or1-{F}(V16,V17), or_ok-{F}(V17), P_in1-{F}(V17,V4), P_out1-{F}(V17,V18), one-{F}(V18) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1320: exists( #66, #1314 ), references = 1, size of lhs = 19:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), and_ok-{F}(V2), halfadder-{F}(V3), P_and1-{F}(V3,V2), P_outs-{F}(V3,V4), fulladder-{F}(V5), P_h1-{F}(V5,V6), halfadder-{F}(V6), P_and2-{F}(V6,V2), P_or1-{F}(V5,V7), P_in2-{F}(V7,V8), or_ok-{F}(V9), P_in2-{F}(V9,V8), P_in1-{F}(V9,V4), P_out1-{F}(V9,V10), one-{F}(V10) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1355: exists( #67, #1349 ), references = 3, size of lhs = 30:
% 7.62/7.81 halfadder-{F}(V0), P_outc-{F}(V0,V1), P_and2-{F}(V0,V2), and_ok-{F}(V2), P_in1-{F}(V2,V3), zero-{F}(V3), connection-{F}(V1,V4), fulladder-{F}(V5), P_outc-{F}(V5,V6), one-{F}(V6), P_or1-{F}(V5,V7), or_ok-{F}(V7), P_in1-{F}(V7,V4), fulladder-{F}(V8), P_in2-{F}(V8,V9), zero-{F}(V9), P_h1-{F}(V8,V10), halfadder-{F}(V10), P_a-{F}(V11), P_ina1-{F}(V11,V12), P_inb1-{F}(V11,V13), P_inc-{F}(V11,V14), P_out1-{F}(V11,V15), P_outc-{F}(V11,V16), P_f1-{F}(V11,V17), P_h1-{F}(V17,V10), P_or1-{F}(V17,V18), fulladder-{F}(V19), P_h1-{F}(V19,V10), P_or1-{F}(V19,V7) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1356: exists( #67, #1350 ), references = 2, size of lhs = 18:
% 7.62/7.81 halfadder-{F}(V0), P_outc-{F}(V0,V1), P_and2-{F}(V0,V2), and_ok-{F}(V2), P_in1-{F}(V2,V3), zero-{F}(V3), connection-{F}(V1,V4), fulladder-{F}(V5), P_h1-{F}(V5,V6), halfadder-{F}(V6), P_and2-{F}(V6,V2), P_or1-{F}(V5,V7), P_in2-{F}(V7,V8), or_ok-{F}(V9), P_in2-{F}(V9,V8), P_in1-{F}(V9,V4), P_out1-{F}(V9,V10), one-{F}(V10) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1357: exists( #67, #1351 ), references = 2, size of lhs = 21:
% 7.62/7.81 halfadder-{F}(V0), P_outc-{F}(V0,V1), P_and2-{F}(V0,V2), and_ok-{F}(V2), P_in1-{F}(V2,V3), zero-{F}(V3), connection-{F}(V1,V4), and_ok-{F}(V5), P_in1-{F}(V5,V6), zero-{F}(V6), fulladder-{F}(V7), P_h1-{F}(V7,V8), halfadder-{F}(V8), P_and2-{F}(V8,V5), P_or1-{F}(V7,V9), P_in2-{F}(V9,V10), or_ok-{F}(V11), P_in2-{F}(V11,V10), P_in1-{F}(V11,V4), P_out1-{F}(V11,V12), one-{F}(V12) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1367: exists( #66, #1361 ), references = 1, size of lhs = 32:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), and_ok-{F}(V2), halfadder-{F}(V3), P_and2-{F}(V3,V2), P_outc-{F}(V3,V4), connection-{F}(V4,V5), fulladder-{F}(V6), P_outc-{F}(V6,V7), one-{F}(V7), P_or1-{F}(V6,V8), or_ok-{F}(V8), P_in1-{F}(V8,V5), fulladder-{F}(V9), P_in2-{F}(V9,V10), zero-{F}(V10), P_h1-{F}(V9,V11), halfadder-{F}(V11), P_a-{F}(V12), P_ina1-{F}(V12,V13), P_inb1-{F}(V12,V14), P_inc-{F}(V12,V15), P_out1-{F}(V12,V16), P_outc-{F}(V12,V17), P_f1-{F}(V12,V18), P_h1-{F}(V18,V11), P_or1-{F}(V18,V19), fulladder-{F}(V20), P_h1-{F}(V20,V11), P_or1-{F}(V20,V8) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1368: exists( #66, #1362 ), references = 1, size of lhs = 20:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), and_ok-{F}(V2), halfadder-{F}(V3), P_and2-{F}(V3,V2), P_outc-{F}(V3,V4), connection-{F}(V4,V5), fulladder-{F}(V6), P_h1-{F}(V6,V7), halfadder-{F}(V7), P_and2-{F}(V7,V2), P_or1-{F}(V6,V8), P_in2-{F}(V8,V9), or_ok-{F}(V10), P_in2-{F}(V10,V9), P_in1-{F}(V10,V5), P_out1-{F}(V10,V11), one-{F}(V11) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1369: exists( #66, #1363 ), references = 1, size of lhs = 20:
% 7.62/7.81 fulladder-{F}(V0), P_in1-{F}(V0,V1), zero-{F}(V1), P_h2-{F}(V0,V2), and_ok-{F}(V2), halfadder-{F}(V3), P_and2-{F}(V3,V2), P_outc-{F}(V3,V4), connection-{F}(V4,V5), fulladder-{F}(V6), P_h1-{F}(V6,V7), halfadder-{F}(V7), P_and2-{F}(V7,V2), P_or1-{F}(V6,V8), P_in2-{F}(V8,V9), or_ok-{F}(V10), P_in2-{F}(V10,V9), P_in1-{F}(V10,V5), P_out1-{F}(V10,V11), one-{F}(V11) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1376: exists( #74, #1370 ), references = 1, size of lhs = 34:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in2-{F}(V2,V3), fulladder-{F}(V4), P_in1-{F}(V4,V5), zero-{F}(V5), P_h2-{F}(V4,V6), and_ok-{F}(V6), P_and2-{F}(V1,V6), fulladder-{F}(V7), P_outc-{F}(V7,V8), one-{F}(V8), P_or1-{F}(V7,V9), or_ok-{F}(V9), P_in1-{F}(V9,V3), fulladder-{F}(V10), P_in2-{F}(V10,V11), zero-{F}(V11), P_h1-{F}(V10,V12), halfadder-{F}(V12), P_a-{F}(V13), P_ina1-{F}(V13,V14), P_inb1-{F}(V13,V15), P_inc-{F}(V13,V16), P_out1-{F}(V13,V17), P_outc-{F}(V13,V18), P_f1-{F}(V13,V19), P_h1-{F}(V19,V12), P_or1-{F}(V19,V20), fulladder-{F}(V21), P_h1-{F}(V21,V12), P_or1-{F}(V21,V9) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1377: exists( #74, #1371 ), references = 1, size of lhs = 22:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in2-{F}(V2,V3), fulladder-{F}(V4), P_in1-{F}(V4,V5), zero-{F}(V5), P_h2-{F}(V4,V6), and_ok-{F}(V6), P_and2-{F}(V1,V6), fulladder-{F}(V7), P_h1-{F}(V7,V8), halfadder-{F}(V8), P_and2-{F}(V8,V6), P_or1-{F}(V7,V9), P_in2-{F}(V9,V10), or_ok-{F}(V11), P_in2-{F}(V11,V10), P_in1-{F}(V11,V3), P_out1-{F}(V11,V12), one-{F}(V12) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1378: exists( #74, #1372 ), references = 1, size of lhs = 22:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in2-{F}(V2,V3), fulladder-{F}(V4), P_in1-{F}(V4,V5), zero-{F}(V5), P_h2-{F}(V4,V6), and_ok-{F}(V6), P_and2-{F}(V1,V6), fulladder-{F}(V7), P_h1-{F}(V7,V8), halfadder-{F}(V8), P_and2-{F}(V8,V6), P_or1-{F}(V7,V9), P_in2-{F}(V9,V10), or_ok-{F}(V11), P_in2-{F}(V11,V10), P_in1-{F}(V11,V3), P_out1-{F}(V11,V12), one-{F}(V12) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1394: exists( #74, #1388 ), references = 1, size of lhs = 32:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in2-{F}(V2,V3), P_and2-{F}(V1,V4), and_ok-{F}(V4), P_in1-{F}(V4,V5), zero-{F}(V5), fulladder-{F}(V6), P_outc-{F}(V6,V7), one-{F}(V7), P_or1-{F}(V6,V8), or_ok-{F}(V8), P_in1-{F}(V8,V3), fulladder-{F}(V9), P_in2-{F}(V9,V10), zero-{F}(V10), P_h1-{F}(V9,V11), halfadder-{F}(V11), P_a-{F}(V12), P_ina1-{F}(V12,V13), P_inb1-{F}(V12,V14), P_inc-{F}(V12,V15), P_out1-{F}(V12,V16), P_outc-{F}(V12,V17), P_f1-{F}(V12,V18), P_h1-{F}(V18,V11), P_or1-{F}(V18,V19), fulladder-{F}(V20), P_h1-{F}(V20,V11), P_or1-{F}(V20,V8) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1395: exists( #74, #1389 ), references = 1, size of lhs = 20:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in2-{F}(V2,V3), P_and2-{F}(V1,V4), and_ok-{F}(V4), P_in1-{F}(V4,V5), zero-{F}(V5), fulladder-{F}(V6), P_h1-{F}(V6,V7), halfadder-{F}(V7), P_and2-{F}(V7,V4), P_or1-{F}(V6,V8), P_in2-{F}(V8,V9), or_ok-{F}(V10), P_in2-{F}(V10,V9), P_in1-{F}(V10,V3), P_out1-{F}(V10,V11), one-{F}(V11) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1396: exists( #74, #1390 ), references = 1, size of lhs = 23:
% 7.62/7.81 fulladder-{F}(V0), P_h1-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in2-{F}(V2,V3), P_and2-{F}(V1,V4), and_ok-{F}(V4), P_in1-{F}(V4,V5), zero-{F}(V5), and_ok-{F}(V6), P_in1-{F}(V6,V7), zero-{F}(V7), fulladder-{F}(V8), P_h1-{F}(V8,V9), halfadder-{F}(V9), P_and2-{F}(V9,V6), P_or1-{F}(V8,V10), P_in2-{F}(V10,V11), or_ok-{F}(V12), P_in2-{F}(V12,V11), P_in1-{F}(V12,V3), P_out1-{F}(V12,V13), one-{F}(V13) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1433: exists( #68, #1427 ), references = 1, size of lhs = 32:
% 7.62/7.81 halfadder-{F}(V0), P_not1-{F}(V0,V1), P_out1-{F}(V1,V2), zero-{F}(V2), P_and1-{F}(V0,V3), fulladder-{F}(V4), P_h2-{F}(V4,V3), P_h1-{F}(V4,V5), P_outs-{F}(V5,V6), fulladder-{F}(V7), P_outc-{F}(V7,V8), one-{F}(V8), P_or1-{F}(V7,V9), or_ok-{F}(V9), P_in1-{F}(V9,V6), fulladder-{F}(V10), P_in2-{F}(V10,V11), zero-{F}(V11), P_h1-{F}(V10,V12), halfadder-{F}(V12), P_a-{F}(V13), P_ina1-{F}(V13,V14), P_inb1-{F}(V13,V15), P_inc-{F}(V13,V16), P_out1-{F}(V13,V17), P_outc-{F}(V13,V18), P_f1-{F}(V13,V19), P_h1-{F}(V19,V12), P_or1-{F}(V19,V20), fulladder-{F}(V21), P_h1-{F}(V21,V12), P_or1-{F}(V21,V9) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1434: exists( #68, #1428 ), references = 1, size of lhs = 30:
% 7.62/7.81 halfadder-{F}(V0), P_not1-{F}(V0,V1), P_out1-{F}(V1,V2), zero-{F}(V2), P_and1-{F}(V0,V3), fulladder-{F}(V4), P_h2-{F}(V4,V3), P_h1-{F}(V4,V5), P_outs-{F}(V5,V6), fulladder-{F}(V7), P_in2-{F}(V7,V8), zero-{F}(V8), P_h1-{F}(V7,V9), halfadder-{F}(V9), P_a-{F}(V10), P_ina1-{F}(V10,V11), P_inb1-{F}(V10,V12), P_inc-{F}(V10,V13), P_out1-{F}(V10,V14), P_outc-{F}(V10,V15), P_f1-{F}(V10,V16), P_h1-{F}(V16,V9), P_or1-{F}(V16,V17), fulladder-{F}(V18), P_h1-{F}(V18,V9), P_or1-{F}(V18,V19), or_ok-{F}(V19), P_in1-{F}(V19,V6), P_out1-{F}(V19,V20), one-{F}(V20) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1435: exists( #68, #1429 ), references = 1, size of lhs = 32:
% 7.62/7.81 halfadder-{F}(V0), P_not1-{F}(V0,V1), P_out1-{F}(V1,V2), zero-{F}(V2), P_and1-{F}(V0,V3), fulladder-{F}(V4), P_h2-{F}(V4,V3), P_h1-{F}(V4,V5), P_outs-{F}(V5,V6), fulladder-{F}(V7), P_in2-{F}(V7,V8), zero-{F}(V8), P_h1-{F}(V7,V9), halfadder-{F}(V9), P_a-{F}(V10), P_ina1-{F}(V10,V11), P_inb1-{F}(V10,V12), P_inc-{F}(V10,V13), P_out1-{F}(V10,V14), P_outc-{F}(V10,V15), P_f1-{F}(V10,V16), P_h1-{F}(V16,V9), P_or1-{F}(V16,V17), fulladder-{F}(V18), P_h1-{F}(V18,V9), P_or1-{F}(V18,V19), P_in2-{F}(V19,V20), or_ok-{F}(V21), P_in2-{F}(V21,V20), P_in1-{F}(V21,V6), P_out1-{F}(V21,V22), one-{F}(V22) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1477: exists( #74, #1471 ), references = 1, size of lhs = 32:
% 7.62/7.81 fulladder-{F}(V0), P_h2-{F}(V0,V1), halfadder-{F}(V1), P_or1-{F}(V0,V2), P_in1-{F}(V2,V3), P_and2-{F}(V1,V4), and_ok-{F}(V4), P_in1-{F}(V4,V5), zero-{F}(V5), fulladder-{F}(V6), P_outc-{F}(V6,V7), one-{F}(V7), P_or1-{F}(V6,V8), or_ok-{F}(V8), P_in1-{F}(V8,V3), fulladder-{F}(V9), P_in2-{F}(V9,V10), zero-{F}(V10), P_h1-{F}(V9,V11), halfadder-{F}(V11), P_a-{F}(V12), P_ina1-{F}(V12,V13), P_inb1-{F}(V12,V14), P_inc-{F}(V12,V15), P_out1-{F}(V12,V16), P_outc-{F}(V12,V17), P_f1-{F}(V12,V18), P_h1-{F}(V18,V11), P_or1-{F}(V18,V19), fulladder-{F}(V20), P_h1-{F}(V20,V11), P_or1-{F}(V20,V8) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1501: disj( #16, exists( #66, #552 ) ), references = 1, size of lhs = 23:
% 7.62/7.81 or_ok-{F}(V0), P_out1-{F}(V0,V1), one-{F}(V1), P_in1-{F}(V0,V2), P_in2-{F}(V0,V3), fulladder-{F}(V4), P_in2-{F}(V4,V5), zero-{F}(V5), P_h1-{F}(V4,V6), halfadder-{F}(V6), P_a-{F}(V7), P_ina1-{F}(V7,V8), P_inb1-{F}(V7,V9), P_inc-{F}(V7,V10), P_out1-{F}(V7,V11), P_outc-{F}(V7,V12), P_f1-{F}(V7,V13), P_h1-{F}(V13,V6), P_or1-{F}(V13,V14), fulladder-{F}(V15), P_h1-{F}(V15,V6), P_or1-{F}(V15,V16), P_in2-{F}(V16,V2) | one-{T}(V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1502: disj( #16, exists( #70, #1073 ) ), references = 2, size of lhs = 24:
% 7.62/7.81 or_ok-{F}(V0), P_out1-{F}(V0,V1), one-{F}(V1), P_in1-{F}(V0,V2), P_in2-{F}(V0,V3), fulladder-{F}(V4), P_in1-{F}(V4,V5), zero-{F}(V5), P_h2-{F}(V4,V6), halfadder-{F}(V6), P_a-{F}(V7), P_ina1-{F}(V7,V8), P_inb1-{F}(V7,V9), P_inc-{F}(V7,V10), P_out1-{F}(V7,V11), P_outc-{F}(V7,V12), P_f1-{F}(V7,V13), P_h2-{F}(V13,V6), P_or1-{F}(V13,V14), P_h1-{F}(V13,V15), fulladder-{F}(V16), P_h2-{F}(V16,V6), P_or1-{F}(V16,V17), P_in1-{F}(V17,V2) | one-{T}(V3)
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1516: mergings( V7 == V21, V11 == V25, V12 == V26, V10 == V24, V13 == V27, V14 == V28, V15 == V20, V8 == V22, V9 == V23; #1506 ), references = 2, size of lhs = 31:
% 7.62/7.81 or_ok-{F}(V0), P_out1-{F}(V0,V1), one-{F}(V1), P_in1-{F}(V0,V2), fulladder-{F}(V3), P_in1-{F}(V3,V4), zero-{F}(V4), P_h2-{F}(V3,V5), halfadder-{F}(V5), fulladder-{F}(V6), P_h2-{F}(V6,V5), P_or1-{F}(V6,V7), P_in1-{F}(V7,V2), fulladder-{F}(V8), P_in2-{F}(V8,V9), zero-{F}(V9), P_h1-{F}(V8,V10), halfadder-{F}(V10), P_a-{F}(V11), P_ina1-{F}(V11,V12), P_inb1-{F}(V11,V13), P_inc-{F}(V11,V14), P_out1-{F}(V11,V15), P_outc-{F}(V11,V16), P_f1-{F}(V11,V17), P_h2-{F}(V17,V5), P_h1-{F}(V17,V10), P_or1-{F}(V17,V18), fulladder-{F}(V19), P_h1-{F}(V19,V10), P_or1-{F}(V19,V0) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1522: exists( #67, #1520 ), references = 1, size of lhs = 33:
% 7.62/7.81 fulladder-{F}(V0), P_outc-{F}(V0,V1), one-{F}(V1), P_or1-{F}(V0,V2), or_ok-{F}(V2), P_in1-{F}(V2,V3), fulladder-{F}(V4), P_in1-{F}(V4,V5), zero-{F}(V5), P_h2-{F}(V4,V6), halfadder-{F}(V6), fulladder-{F}(V7), P_h2-{F}(V7,V6), P_or1-{F}(V7,V8), P_in1-{F}(V8,V3), fulladder-{F}(V9), P_in2-{F}(V9,V10), zero-{F}(V10), P_h1-{F}(V9,V11), halfadder-{F}(V11), P_a-{F}(V12), P_ina1-{F}(V12,V13), P_inb1-{F}(V12,V14), P_inc-{F}(V12,V15), P_out1-{F}(V12,V16), P_outc-{F}(V12,V17), P_f1-{F}(V12,V18), P_h2-{F}(V18,V6), P_h1-{F}(V18,V11), P_or1-{F}(V18,V19), fulladder-{F}(V20), P_h1-{F}(V20,V11), P_or1-{F}(V20,V2) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1524: exists( #66, #1521 ), references = 1, size of lhs = 31:
% 7.62/7.81 fulladder-{F}(V0), P_outc-{F}(V0,V1), one-{F}(V1), P_or1-{F}(V0,V2), or_ok-{F}(V2), fulladder-{F}(V3), P_in1-{F}(V3,V4), zero-{F}(V4), P_h2-{F}(V3,V5), halfadder-{F}(V5), fulladder-{F}(V6), P_h2-{F}(V6,V5), P_or1-{F}(V6,V2), fulladder-{F}(V7), P_in2-{F}(V7,V8), zero-{F}(V8), P_h1-{F}(V7,V9), halfadder-{F}(V9), P_a-{F}(V10), P_ina1-{F}(V10,V11), P_inb1-{F}(V10,V12), P_inc-{F}(V10,V13), P_out1-{F}(V10,V14), P_outc-{F}(V10,V15), P_f1-{F}(V10,V16), P_h2-{F}(V16,V5), P_h1-{F}(V16,V9), P_or1-{F}(V16,V17), fulladder-{F}(V18), P_h1-{F}(V18,V9), P_or1-{F}(V18,V2) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1528: mergings( V4 == V15; #1526 ), references = 1, size of lhs = 25:
% 7.62/7.81 fulladder-{F}(V0), P_outc-{F}(V0,V1), one-{F}(V1), P_or1-{F}(V0,V2), or_ok-{F}(V2), zero-{F}(V3), fulladder-{F}(V4), P_in1-{F}(V4,V3), P_or1-{F}(V4,V2), fulladder-{F}(V5), P_in2-{F}(V5,V6), zero-{F}(V6), P_h1-{F}(V5,V7), halfadder-{F}(V7), P_h1-{F}(V4,V7), P_a-{F}(V8), P_f1-{F}(V8,V4), P_ina1-{F}(V8,V9), P_inb1-{F}(V8,V10), P_inc-{F}(V8,V11), P_out1-{F}(V8,V12), P_outc-{F}(V8,V13), fulladder-{F}(V14), P_h1-{F}(V14,V7), P_or1-{F}(V14,V2) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1532: mergings( V4 == V13; #1530 ), references = 2, size of lhs = 18:
% 7.62/7.81 fulladder-{F}(V0), P_outc-{F}(V0,V1), one-{F}(V1), P_or1-{F}(V0,V2), or_ok-{F}(V2), zero-{F}(V3), zero-{F}(V4), P_a-{F}(V5), P_f1-{F}(V5,V6), P_in1-{F}(V6,V3), P_in2-{F}(V6,V4), fulladder-{F}(V6), P_or1-{F}(V6,V2), P_ina1-{F}(V5,V7), P_inb1-{F}(V5,V8), P_inc-{F}(V5,V9), P_out1-{F}(V5,V10), P_outc-{F}(V5,V11) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1536: exists( #74, #1534 ), references = 1, size of lhs = 20:
% 7.62/7.81 nbit_adder1-{F}(V0), P_outc-{F}(V0,V1), one-{F}(V1), P_f1-{F}(V0,V2), fulladder-{F}(V2), P_or1-{F}(V2,V3), or_ok-{F}(V3), zero-{F}(V4), zero-{F}(V5), P_a-{F}(V6), P_f1-{F}(V6,V7), P_in1-{F}(V7,V4), P_in2-{F}(V7,V5), fulladder-{F}(V7), P_or1-{F}(V7,V3), P_ina1-{F}(V6,V8), P_inb1-{F}(V6,V9), P_inc-{F}(V6,V10), P_out1-{F}(V6,V11), P_outc-{F}(V6,V12) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1546: mergings( V2 == V12, V6 == V16, V7 == V17, V5 == V15, V3 == V13, V4 == V14; #1539 ), references = 2, size of lhs = 16:
% 7.62/7.81 fulladder-{F}(V0), nbit_adder1-{F}(V1), P_f1-{F}(V1,V0), P_outc-{F}(V1,V2), one-{F}(V2), zero-{F}(V3), P_in1-{F}(V0,V3), zero-{F}(V4), P_in2-{F}(V0,V4), P_a-{F}(V5), P_f1-{F}(V5,V0), P_ina1-{F}(V5,V6), P_inb1-{F}(V5,V7), P_inc-{F}(V5,V8), P_out1-{F}(V5,V9), P_outc-{F}(V5,V10) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1551: mergings( V2 == V4; #1549 ), references = 2, size of lhs = 16:
% 7.62/7.81 zero-{F}(V0), fulladder-{F}(V1), nbit_adder1-{F}(V2), P_inb1-{F}(V2,V0), P_f1-{F}(V2,V1), P_outc-{F}(V2,V3), one-{F}(V3), zero-{F}(V4), P_in1-{F}(V1,V4), P_a-{F}(V5), P_f1-{F}(V5,V1), P_ina1-{F}(V5,V6), P_inb1-{F}(V5,V7), P_inc-{F}(V5,V8), P_out1-{F}(V5,V9), P_outc-{F}(V5,V10) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1556: mergings( V2 == V5; #1554 ), references = 2, size of lhs = 16:
% 7.62/7.81 zero-{F}(V0), fulladder-{F}(V1), zero-{F}(V2), nbit_adder1-{F}(V3), P_ina1-{F}(V3,V0), P_inb1-{F}(V3,V2), P_f1-{F}(V3,V1), P_outc-{F}(V3,V4), one-{F}(V4), P_a-{F}(V5), P_f1-{F}(V5,V1), P_ina1-{F}(V5,V6), P_inb1-{F}(V5,V7), P_inc-{F}(V5,V8), P_out1-{F}(V5,V9), P_outc-{F}(V5,V10) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1567: mergings( V5 == V11, V6 == V12, V4 == V10, V7 == V2, V2 == V3, V3 == V9; #1560 ), references = 1, size of lhs = 9:
% 7.62/7.81 zero-{F}(V0), fulladder-{F}(V1), nbit_adder1-{F}(V2), P_a-{F}(V2), P_f1-{F}(V2,V1), P_ina1-{F}(V2,V0), P_inc-{F}(V2,V3), P_out1-{F}(V2,V4), P_outc-{F}(V2,V5) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1573: mergings( V4 == V7, V5 == V8, V3 == V6; #1569 ), references = 1, size of lhs = 7:
% 7.62/7.81 fulladder-{F}(V0), nbit_adder1-{F}(V1), P_a-{F}(V1), P_f1-{F}(V1,V0), P_inc-{F}(V1,V2), P_out1-{F}(V1,V3), P_outc-{F}(V1,V4) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1579: mergings( V3 == V6, V4 == V7, V2 == V5; #1575 ), references = 1, size of lhs = 5:
% 7.62/7.81 nbit_adder1-{F}(V0), P_a-{F}(V0), P_inc-{F}(V0,V1), P_out1-{F}(V0,V2), P_outc-{F}(V0,V3) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1583: mergings( V2 == V4, V3 == V5; #1580 ), references = 1, size of lhs = 4:
% 7.62/7.81 nbit_adder1-{F}(V0), P_a-{F}(V0), P_out1-{F}(V0,V1), P_outc-{F}(V0,V2) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1586: mergings( V2 == V3; #1584 ), references = 1, size of lhs = 3:
% 7.62/7.81 nbit_adder1-{F}(V0), P_a-{F}(V0), P_out1-{F}(V0,V1) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1588: exists( #67, #1584 ), references = 1, size of lhs = 2:
% 7.62/7.81 nbit_adder1-{F}(V0), P_a-{F}(V0) | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 #1591: exists( #81, #1589 ), references = 1, size of lhs = 0:
% 7.62/7.81 FALSE | FALSE
% 7.62/7.81 (used 0 times, uses = {})
% 7.62/7.81
% 7.62/7.81 number of learnt formulas = 134
% 7.62/7.81
% 7.62/7.81
% 7.62/7.81 % SZS output end Refutation for /export/starexec/sandbox2/benchmark/theBenchmark.p
% 7.62/7.81
% 7.62/7.81 randbase = 1
%------------------------------------------------------------------------------