%------------------------------------------------------------------------------ % File : SuperZenon---0.0.1 % Problem : NUM848+2 : TPTP v8.1.0. Released v4.1.0. % Transfm : none % Format : tptp:raw % Command : run_super_zenon -p0 -itptp -om -max-time %d %s % Computer : n027.cluster.edu % Model : x86_64 x86_64 % CPU : Intel(R) Xeon(R) CPU E5-2620 v4 2.10GHz % Memory : 8042.1875MB % OS : Linux 3.10.0-693.el7.x86_64 % CPULimit : 300s % WCLimit : 600s % DateTime : Mon Jul 18 14:46:47 EDT 2022 % Result : Theorem 0.78s 0.96s % Output : Proof 0.78s % Verified : % SZS Type : - % Comments : %------------------------------------------------------------------------------ %----WARNING: Could not form TPTP format derivation %------------------------------------------------------------------------------ %----ORIGINAL SYSTEM OUTPUT % 0.03/0.12 % Problem : NUM848+2 : TPTP v8.1.0. Released v4.1.0. % 0.03/0.13 % Command : run_super_zenon -p0 -itptp -om -max-time %d %s % 0.12/0.34 % Computer : n027.cluster.edu % 0.12/0.34 % Model : x86_64 x86_64 % 0.12/0.34 % CPU : Intel(R) Xeon(R) CPU E5-2620 v4 @ 2.10GHz % 0.12/0.34 % Memory : 8042.1875MB % 0.12/0.34 % OS : Linux 3.10.0-693.el7.x86_64 % 0.12/0.34 % CPULimit : 300 % 0.12/0.34 % WCLimit : 600 % 0.12/0.34 % DateTime : Wed Jul 6 15:04:58 EDT 2022 % 0.12/0.34 % CPUTime : % 0.78/0.96 % SZS status Theorem % 0.78/0.96 (* PROOF-FOUND *) % 0.78/0.96 (* BEGIN-PROOF *) % 0.78/0.96 % SZS output start Proof % 0.78/0.96 1. ((vmul (vd436) (vd437)) != (vmul (vd436) (vd437))) ### Refl(=) % 0.78/0.96 2. ((vplus (vmul (vd436) (vd439)) (vd436)) != (vmul (vd436) (vsucc (vd439)))) ((vmul (vd436) (vsucc (vd439))) = (vplus (vmul (vd436) (vd439)) (vd436))) ### Sym(=) % 0.78/0.96 3. (((vmul (vd436) (vsucc (vd439))) = (vplus (vmul (vd436) (vd439)) (vd436))) /\ ((vmul (vd436) (v1)) = (vd436))) ((vplus (vmul (vd436) (vd439)) (vd436)) != (vmul (vd436) (vsucc (vd439)))) ### And 2 % 0.78/0.96 4. (All Vd397, (((vmul (vd436) (vsucc Vd397)) = (vplus (vmul (vd436) Vd397) (vd436))) /\ ((vmul (vd436) (v1)) = (vd436)))) ((vplus (vmul (vd436) (vd439)) (vd436)) != (vmul (vd436) (vsucc (vd439)))) ### All 3 % 0.78/0.96 5. (All Vd396, (All Vd397, (((vmul Vd396 (vsucc Vd397)) = (vplus (vmul Vd396 Vd397) Vd396)) /\ ((vmul Vd396 (v1)) = Vd396)))) ((vplus (vmul (vd436) (vd439)) (vd436)) != (vmul (vd436) (vsucc (vd439)))) ### All 4 % 0.78/0.96 6. ((vplus (vmul (vd436) (vd437)) (vplus (vmul (vd436) (vd439)) (vd436))) != (vplus (vmul (vd436) (vd437)) (vmul (vd436) (vsucc (vd439))))) (All Vd396, (All Vd397, (((vmul Vd396 (vsucc Vd397)) = (vplus (vmul Vd396 Vd397) Vd396)) /\ ((vmul Vd396 (v1)) = Vd396)))) ### NotEqual 1 5 % 0.78/0.96 % SZS output end Proof % 0.78/0.96 (* END-PROOF *) %------------------------------------------------------------------------------