%------------------------------------------------------------------------------ % File : SPASS---3.9 % Problem : SWV424-1.050 : TPTP v8.1.0. Released v3.5.0. % Transfm : none % Format : tptp % Command : run_spass %d %s % Computer : n011.cluster.edu % Model : x86_64 x86_64 % CPU : Intel(R) Xeon(R) CPU E5-2620 v4 2.10GHz % Memory : 8042.1875MB % OS : Linux 3.10.0-693.el7.x86_64 % CPULimit : 300s % WCLimit : 600s % DateTime : Wed Jul 20 21:42:56 EDT 2022 % Result : Unsatisfiable 75.92s 76.13s % Output : Refutation 156.41s % Verified : % SZS Type : - % Comments : %------------------------------------------------------------------------------ %----WARNING: Could not form TPTP format derivation %------------------------------------------------------------------------------ %----ORIGINAL SYSTEM OUTPUT % 0.06/0.12 % Problem : SWV424-1.050 : TPTP v8.1.0. Released v3.5.0. % 0.06/0.12 % Command : run_spass %d %s % 0.13/0.33 % Computer : n011.cluster.edu % 0.13/0.33 % Model : x86_64 x86_64 % 0.13/0.33 % CPU : Intel(R) Xeon(R) CPU E5-2620 v4 @ 2.10GHz % 0.13/0.33 % Memory : 8042.1875MB % 0.13/0.33 % OS : Linux 3.10.0-693.el7.x86_64 % 0.13/0.33 % CPULimit : 300 % 0.13/0.33 % WCLimit : 600 % 0.13/0.33 % DateTime : Thu Jun 16 02:10:06 EDT 2022 % 0.13/0.34 % CPUTime : % 75.92/76.13 % 75.92/76.13 SPASS V 3.9 % 75.92/76.13 SPASS beiseite: Proof found. % 75.92/76.13 % SZS status Theorem % 75.92/76.13 Problem: /export/starexec/sandbox2/benchmark/theBenchmark.p % 75.92/76.13 SPASS derived 349757 clauses, backtracked 455809 clauses, performed 43208 splits and kept 520162 clauses. % 75.92/76.13 SPASS allocated 303629 KBytes. % 75.92/76.13 SPASS spent 0:1:14.46 on the problem. % 75.92/76.13 0:00:00.03 for the input. % 75.92/76.13 0:00:00.00 for the FLOTTER CNF translation. % 75.92/76.13 0:00:02.90 for inferences. % 75.92/76.13 0:0:38.29 for the backtracking. % 75.92/76.13 0:0:28.31 for the reduction. % 75.92/76.13 % 75.92/76.13 % 75.92/76.13 Here is a proof with depth 101, length 305443 : % 75.92/76.13 % SZS output start Refutation % 75.92/76.13 1[0:Inp] || -> succ(s0,s1)*. % 75.92/76.13 2[0:Inp] || -> succ(s1,s2)*. % 75.92/76.13 3[0:Inp] || -> succ(s2,s3)*. % 75.92/76.13 4[0:Inp] || -> succ(s3,s4)*. % 75.92/76.13 5[0:Inp] || -> succ(s4,s5)*. % 75.92/76.13 6[0:Inp] || -> succ(s5,s6)*. % 75.92/76.13 7[0:Inp] || -> succ(s6,s7)*. % 75.92/76.13 8[0:Inp] || -> succ(s7,s8)*. % 75.92/76.13 9[0:Inp] || -> succ(s8,s9)*. % 75.92/76.13 10[0:Inp] || -> succ(s9,s10)*. % 75.92/76.13 11[0:Inp] || -> succ(s10,s11)*. % 75.92/76.13 12[0:Inp] || -> succ(s11,s12)*. % 75.92/76.13 13[0:Inp] || -> succ(s12,s13)*. % 75.92/76.13 14[0:Inp] || -> succ(s13,s14)*. % 75.92/76.13 15[0:Inp] || -> succ(s14,s15)*. % 75.92/76.13 16[0:Inp] || -> succ(s15,s16)*. % 75.92/76.13 17[0:Inp] || -> succ(s16,s17)*. % 75.92/76.13 18[0:Inp] || -> succ(s17,s18)*. % 75.92/76.13 19[0:Inp] || -> succ(s18,s19)*. % 75.92/76.13 20[0:Inp] || -> succ(s19,s20)*. % 75.92/76.13 21[0:Inp] || -> succ(s20,s21)*. % 75.92/76.13 22[0:Inp] || -> succ(s21,s22)*. % 75.92/76.13 23[0:Inp] || -> succ(s22,s23)*. % 75.92/76.13 24[0:Inp] || -> succ(s23,s24)*. % 75.92/76.13 25[0:Inp] || -> succ(s24,s25)*. % 75.92/76.13 26[0:Inp] || -> succ(s25,s26)*. % 75.92/76.13 27[0:Inp] || -> succ(s26,s27)*. % 75.92/76.13 28[0:Inp] || -> succ(s27,s28)*. % 75.92/76.13 29[0:Inp] || -> succ(s28,s29)*. % 75.92/76.13 30[0:Inp] || -> succ(s29,s30)*. % 75.92/76.13 31[0:Inp] || -> succ(s30,s31)*. % 75.92/76.13 32[0:Inp] || -> succ(s31,s32)*. % 75.92/76.13 33[0:Inp] || -> succ(s32,s33)*. % 75.92/76.13 34[0:Inp] || -> succ(s33,s34)*. % 75.92/76.13 35[0:Inp] || -> succ(s34,s35)*. % 75.92/76.13 36[0:Inp] || -> succ(s35,s36)*. % 75.92/76.13 37[0:Inp] || -> succ(s36,s37)*. % 75.92/76.13 38[0:Inp] || -> succ(s37,s38)*. % 75.92/76.13 39[0:Inp] || -> succ(s38,s39)*. % 75.92/76.13 40[0:Inp] || -> succ(s39,s40)*. % 75.92/76.13 41[0:Inp] || -> succ(s40,s41)*. % 75.92/76.13 42[0:Inp] || -> succ(s41,s42)*. % 75.92/76.13 43[0:Inp] || -> succ(s42,s43)*. % 75.92/76.13 44[0:Inp] || -> succ(s43,s44)*. % 75.92/76.13 45[0:Inp] || -> succ(s44,s45)*. % 75.92/76.13 46[0:Inp] || -> succ(s45,s46)*. % 75.92/76.13 47[0:Inp] || -> succ(s46,s47)*. % 75.92/76.13 48[0:Inp] || -> succ(s47,s48)*. % 75.92/76.13 49[0:Inp] || -> succ(s48,s49)*. % 75.92/76.13 50[0:Inp] || -> last(s49)*. % 75.92/76.13 51[0:Inp] || succ(u,v)+ -> trans(u,v)*. % 75.92/76.13 52[0:Inp] || loop+ -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) trans(s49,s0)*. % 75.92/76.13 53[0:Inp] || -> m_main_v_state(u,c_busy) m_main_v_state(u,c_ready)*. % 75.92/76.13 54[0:Inp] || m_main_v_state(u,c_busy)+ m_main_v_state(u,c_ready)* -> . % 75.92/76.13 55[0:Inp] || -> m_main_v_state(s0,c_ready)*. % 75.92/76.13 58[0:Inp] m_main_v_request(u) || node2(u,v)*+ m_main_v_state(u,c_ready)* -> m_main_v_state(v,c_busy)*. % 75.92/76.13 60[0:Inp] || trans(u,v)+ -> node2(u,v)*. % 75.92/76.13 61[0:Inp] always3(u) || m_main_v_state(u,c_busy)*+ -> . % 75.92/76.13 62[0:Inp] always3(u) || trans(u,v)*+ -> always3(v). % 75.92/76.13 63[0:Inp] last(u) always3(u) || -> loop*. % 75.92/76.13 64[0:Inp] node4(u) || -> m_main_v_request(u)*. % 75.92/76.13 65[0:Inp] node4(u) || -> always3(u)*. % 75.92/76.13 66[0:Inp] until5(u) || -> xuntil6(u) node4(u)*. % 75.92/76.13 67[0:Inp] xuntil6(u) || succ(u,v)*+ -> until5(v). % 75.92/76.13 68[0:Inp] xuntil6(u) last(u) || -> loop*. % 75.92/76.13 69[0:Inp] xuntil6(u) last(u) || trans(u,v)*+ -> until2p7(v). % 75.92/76.13 70[0:Inp] until2p7(u) || -> xuntil2p8(u)* node4(u). % 75.92/76.13 71[0:Inp] xuntil2p8(u) || succ(u,v)*+ -> until2p7(v). % 75.92/76.13 72[0:Inp] xuntil2p8(u) last(u) || -> . % 75.92/76.13 73[0:Inp] || -> until5(s0)*. % 75.92/76.13 74[0:Res:73.0,66.0] || -> xuntil6(s0) node4(s0)*. % 75.92/76.13 76[0:Res:50.0,68.0] xuntil6(s49) || -> loop*. % 75.92/76.13 78[0:Res:50.0,63.1] always3(s49) || -> loop*. % 75.92/76.13 79[0:Res:49.0,71.1] xuntil2p8(s48) || -> until2p7(s49)*. % 75.92/76.13 80[0:Res:48.0,71.1] xuntil2p8(s47) || -> until2p7(s48)*. % 75.92/76.13 81[0:Res:47.0,71.1] xuntil2p8(s46) || -> until2p7(s47)*. % 75.92/76.13 82[0:Res:46.0,71.1] xuntil2p8(s45) || -> until2p7(s46)*. % 75.92/76.13 83[0:Res:45.0,71.1] xuntil2p8(s44) || -> until2p7(s45)*. % 75.92/76.13 84[0:Res:44.0,71.1] xuntil2p8(s43) || -> until2p7(s44)*. % 75.92/76.13 85[0:Res:43.0,71.1] xuntil2p8(s42) || -> until2p7(s43)*. % 75.92/76.13 86[0:Res:42.0,71.1] xuntil2p8(s41) || -> until2p7(s42)*. % 75.92/76.13 87[0:Res:41.0,71.1] xuntil2p8(s40) || -> until2p7(s41)*. % 75.92/76.13 88[0:Res:40.0,71.1] xuntil2p8(s39) || -> until2p7(s40)*. % 75.92/76.13 89[0:Res:39.0,71.1] xuntil2p8(s38) || -> until2p7(s39)*. % 75.92/76.13 90[0:Res:38.0,71.1] xuntil2p8(s37) || -> until2p7(s38)*. % 75.92/76.13 91[0:Res:37.0,71.1] xuntil2p8(s36) || -> until2p7(s37)*. % 75.92/76.13 92[0:Res:36.0,71.1] xuntil2p8(s35) || -> until2p7(s36)*. % 75.92/76.13 93[0:Res:35.0,71.1] xuntil2p8(s34) || -> until2p7(s35)*. % 75.92/76.13 94[0:Res:34.0,71.1] xuntil2p8(s33) || -> until2p7(s34)*. % 75.92/76.13 95[0:Res:33.0,71.1] xuntil2p8(s32) || -> until2p7(s33)*. % 75.92/76.13 96[0:Res:32.0,71.1] xuntil2p8(s31) || -> until2p7(s32)*. % 75.92/76.13 97[0:Res:31.0,71.1] xuntil2p8(s30) || -> until2p7(s31)*. % 75.92/76.13 98[0:Res:30.0,71.1] xuntil2p8(s29) || -> until2p7(s30)*. % 75.92/76.13 99[0:Res:29.0,71.1] xuntil2p8(s28) || -> until2p7(s29)*. % 75.92/76.13 100[0:Res:28.0,71.1] xuntil2p8(s27) || -> until2p7(s28)*. % 75.92/76.13 101[0:Res:27.0,71.1] xuntil2p8(s26) || -> until2p7(s27)*. % 75.92/76.13 102[0:Res:26.0,71.1] xuntil2p8(s25) || -> until2p7(s26)*. % 75.92/76.13 103[0:Res:25.0,71.1] xuntil2p8(s24) || -> until2p7(s25)*. % 75.92/76.13 104[0:Res:24.0,71.1] xuntil2p8(s23) || -> until2p7(s24)*. % 75.92/76.13 105[0:Res:23.0,71.1] xuntil2p8(s22) || -> until2p7(s23)*. % 75.92/76.13 106[0:Res:22.0,71.1] xuntil2p8(s21) || -> until2p7(s22)*. % 75.92/76.13 107[0:Res:21.0,71.1] xuntil2p8(s20) || -> until2p7(s21)*. % 75.92/76.13 108[0:Res:20.0,71.1] xuntil2p8(s19) || -> until2p7(s20)*. % 75.92/76.13 109[0:Res:19.0,71.1] xuntil2p8(s18) || -> until2p7(s19)*. % 75.92/76.13 110[0:Res:18.0,71.1] xuntil2p8(s17) || -> until2p7(s18)*. % 75.92/76.13 111[0:Res:17.0,71.1] xuntil2p8(s16) || -> until2p7(s17)*. % 75.92/76.13 112[0:Res:16.0,71.1] xuntil2p8(s15) || -> until2p7(s16)*. % 75.92/76.13 113[0:Res:15.0,71.1] xuntil2p8(s14) || -> until2p7(s15)*. % 75.92/76.13 114[0:Res:14.0,71.1] xuntil2p8(s13) || -> until2p7(s14)*. % 75.92/76.13 115[0:Res:13.0,71.1] xuntil2p8(s12) || -> until2p7(s13)*. % 75.92/76.13 116[0:Res:12.0,71.1] xuntil2p8(s11) || -> until2p7(s12)*. % 75.92/76.13 117[0:Res:11.0,71.1] xuntil2p8(s10) || -> until2p7(s11)*. % 75.92/76.13 118[0:Res:10.0,71.1] xuntil2p8(s9) || -> until2p7(s10)*. % 75.92/76.13 119[0:Res:9.0,71.1] xuntil2p8(s8) || -> until2p7(s9)*. % 75.92/76.13 120[0:Res:8.0,71.1] xuntil2p8(s7) || -> until2p7(s8)*. % 75.92/76.13 121[0:Res:7.0,71.1] xuntil2p8(s6) || -> until2p7(s7)*. % 75.92/76.13 122[0:Res:6.0,71.1] xuntil2p8(s5) || -> until2p7(s6)*. % 75.92/76.13 123[0:Res:5.0,71.1] xuntil2p8(s4) || -> until2p7(s5)*. % 75.92/76.13 124[0:Res:4.0,71.1] xuntil2p8(s3) || -> until2p7(s4)*. % 75.92/76.13 125[0:Res:3.0,71.1] xuntil2p8(s2) || -> until2p7(s3)*. % 75.92/76.13 126[0:Res:2.0,71.1] xuntil2p8(s1) || -> until2p7(s2)*. % 75.92/76.13 127[0:Res:1.0,71.1] xuntil2p8(s0) || -> until2p7(s1)*. % 75.92/76.13 128[0:Res:49.0,67.1] xuntil6(s48) || -> until5(s49)*. % 75.92/76.13 129[0:Res:48.0,67.1] xuntil6(s47) || -> until5(s48)*. % 75.92/76.13 130[0:Res:47.0,67.1] xuntil6(s46) || -> until5(s47)*. % 75.92/76.13 131[0:Res:46.0,67.1] xuntil6(s45) || -> until5(s46)*. % 75.92/76.13 132[0:Res:45.0,67.1] xuntil6(s44) || -> until5(s45)*. % 75.92/76.13 133[0:Res:44.0,67.1] xuntil6(s43) || -> until5(s44)*. % 75.92/76.13 134[0:Res:43.0,67.1] xuntil6(s42) || -> until5(s43)*. % 75.92/76.13 135[0:Res:42.0,67.1] xuntil6(s41) || -> until5(s42)*. % 75.92/76.13 136[0:Res:41.0,67.1] xuntil6(s40) || -> until5(s41)*. % 75.92/76.13 137[0:Res:40.0,67.1] xuntil6(s39) || -> until5(s40)*. % 75.92/76.13 138[0:Res:39.0,67.1] xuntil6(s38) || -> until5(s39)*. % 75.92/76.13 139[0:Res:38.0,67.1] xuntil6(s37) || -> until5(s38)*. % 75.92/76.13 140[0:Res:37.0,67.1] xuntil6(s36) || -> until5(s37)*. % 75.92/76.13 141[0:Res:36.0,67.1] xuntil6(s35) || -> until5(s36)*. % 75.92/76.13 142[0:Res:35.0,67.1] xuntil6(s34) || -> until5(s35)*. % 75.92/76.13 143[0:Res:34.0,67.1] xuntil6(s33) || -> until5(s34)*. % 75.92/76.13 144[0:Res:33.0,67.1] xuntil6(s32) || -> until5(s33)*. % 75.92/76.13 145[0:Res:32.0,67.1] xuntil6(s31) || -> until5(s32)*. % 75.92/76.13 146[0:Res:31.0,67.1] xuntil6(s30) || -> until5(s31)*. % 75.92/76.13 147[0:Res:30.0,67.1] xuntil6(s29) || -> until5(s30)*. % 75.92/76.13 148[0:Res:29.0,67.1] xuntil6(s28) || -> until5(s29)*. % 75.92/76.13 149[0:Res:28.0,67.1] xuntil6(s27) || -> until5(s28)*. % 75.92/76.13 150[0:Res:27.0,67.1] xuntil6(s26) || -> until5(s27)*. % 75.92/76.13 151[0:Res:26.0,67.1] xuntil6(s25) || -> until5(s26)*. % 75.92/76.13 152[0:Res:25.0,67.1] xuntil6(s24) || -> until5(s25)*. % 75.92/76.13 153[0:Res:24.0,67.1] xuntil6(s23) || -> until5(s24)*. % 75.92/76.13 154[0:Res:23.0,67.1] xuntil6(s22) || -> until5(s23)*. % 75.92/76.13 155[0:Res:22.0,67.1] xuntil6(s21) || -> until5(s22)*. % 75.92/76.13 156[0:Res:21.0,67.1] xuntil6(s20) || -> until5(s21)*. % 75.92/76.13 157[0:Res:20.0,67.1] xuntil6(s19) || -> until5(s20)*. % 75.92/76.13 158[0:Res:19.0,67.1] xuntil6(s18) || -> until5(s19)*. % 75.92/76.13 159[0:Res:18.0,67.1] xuntil6(s17) || -> until5(s18)*. % 75.92/76.13 160[0:Res:17.0,67.1] xuntil6(s16) || -> until5(s17)*. % 75.92/76.13 161[0:Res:16.0,67.1] xuntil6(s15) || -> until5(s16)*. % 75.92/76.13 162[0:Res:15.0,67.1] xuntil6(s14) || -> until5(s15)*. % 75.92/76.13 163[0:Res:14.0,67.1] xuntil6(s13) || -> until5(s14)*. % 75.92/76.13 164[0:Res:13.0,67.1] xuntil6(s12) || -> until5(s13)*. % 75.92/76.13 165[0:Res:12.0,67.1] xuntil6(s11) || -> until5(s12)*. % 75.92/76.13 166[0:Res:11.0,67.1] xuntil6(s10) || -> until5(s11)*. % 75.92/76.13 167[0:Res:10.0,67.1] xuntil6(s9) || -> until5(s10)*. % 75.92/76.13 168[0:Res:9.0,67.1] xuntil6(s8) || -> until5(s9)*. % 75.92/76.13 169[0:Res:8.0,67.1] xuntil6(s7) || -> until5(s8)*. % 75.92/76.13 170[0:Res:7.0,67.1] xuntil6(s6) || -> until5(s7)*. % 75.92/76.13 171[0:Res:6.0,67.1] xuntil6(s5) || -> until5(s6)*. % 75.92/76.13 172[0:Res:5.0,67.1] xuntil6(s4) || -> until5(s5)*. % 75.92/76.13 173[0:Res:4.0,67.1] xuntil6(s3) || -> until5(s4)*. % 75.92/76.13 174[0:Res:3.0,67.1] xuntil6(s2) || -> until5(s3)*. % 75.92/76.13 175[0:Res:2.0,67.1] xuntil6(s1) || -> until5(s2)*. % 75.92/76.13 176[0:Res:1.0,67.1] xuntil6(s0) || -> until5(s1)*. % 75.92/76.13 192[0:SoR:78.0,65.1] node4(s49) || -> loop*. % 75.92/76.13 194[0:EmS:72.0,72.1,70.1,50.0] until2p7(s49) || -> node4(s49)*. % 75.92/76.13 196[0:SoR:127.0,70.1] until2p7(s0) || -> until2p7(s1)* node4(s0). % 75.92/76.13 197[0:SoR:126.0,70.1] until2p7(s1) || -> until2p7(s2)* node4(s1). % 75.92/76.13 198[0:SoR:125.0,70.1] until2p7(s2) || -> until2p7(s3)* node4(s2). % 75.92/76.13 199[0:SoR:124.0,70.1] until2p7(s3) || -> until2p7(s4)* node4(s3). % 75.92/76.13 200[0:SoR:123.0,70.1] until2p7(s4) || -> until2p7(s5)* node4(s4). % 75.92/76.13 201[0:SoR:122.0,70.1] until2p7(s5) || -> until2p7(s6)* node4(s5). % 75.92/76.13 202[0:SoR:121.0,70.1] until2p7(s6) || -> until2p7(s7)* node4(s6). % 75.92/76.13 203[0:SoR:120.0,70.1] until2p7(s7) || -> until2p7(s8)* node4(s7). % 75.92/76.13 204[0:SoR:119.0,70.1] until2p7(s8) || -> until2p7(s9)* node4(s8). % 75.92/76.14 205[0:SoR:118.0,70.1] until2p7(s9) || -> until2p7(s10)* node4(s9). % 75.92/76.14 206[0:SoR:117.0,70.1] until2p7(s10) || -> until2p7(s11)* node4(s10). % 75.92/76.14 207[0:SoR:116.0,70.1] until2p7(s11) || -> until2p7(s12)* node4(s11). % 75.92/76.14 208[0:SoR:115.0,70.1] until2p7(s12) || -> until2p7(s13)* node4(s12). % 75.92/76.14 209[0:SoR:114.0,70.1] until2p7(s13) || -> until2p7(s14)* node4(s13). % 75.92/76.14 210[0:SoR:113.0,70.1] until2p7(s14) || -> until2p7(s15)* node4(s14). % 75.92/76.14 211[0:SoR:112.0,70.1] until2p7(s15) || -> until2p7(s16)* node4(s15). % 75.92/76.14 212[0:SoR:111.0,70.1] until2p7(s16) || -> until2p7(s17)* node4(s16). % 75.92/76.14 213[0:SoR:110.0,70.1] until2p7(s17) || -> until2p7(s18)* node4(s17). % 75.92/76.14 214[0:SoR:109.0,70.1] until2p7(s18) || -> until2p7(s19)* node4(s18). % 75.92/76.14 215[0:SoR:108.0,70.1] until2p7(s19) || -> until2p7(s20)* node4(s19). % 75.92/76.14 216[0:SoR:107.0,70.1] until2p7(s20) || -> until2p7(s21)* node4(s20). % 75.92/76.14 217[0:SoR:106.0,70.1] until2p7(s21) || -> until2p7(s22)* node4(s21). % 75.92/76.14 218[0:SoR:105.0,70.1] until2p7(s22) || -> until2p7(s23)* node4(s22). % 75.92/76.14 219[0:SoR:104.0,70.1] until2p7(s23) || -> until2p7(s24)* node4(s23). % 75.92/76.14 220[0:SoR:103.0,70.1] until2p7(s24) || -> until2p7(s25)* node4(s24). % 75.92/76.14 221[0:SoR:102.0,70.1] until2p7(s25) || -> until2p7(s26)* node4(s25). % 75.92/76.14 222[0:SoR:101.0,70.1] until2p7(s26) || -> until2p7(s27)* node4(s26). % 75.92/76.14 223[0:SoR:100.0,70.1] until2p7(s27) || -> until2p7(s28)* node4(s27). % 75.92/76.14 224[0:SoR:99.0,70.1] until2p7(s28) || -> until2p7(s29)* node4(s28). % 75.92/76.14 225[0:SoR:98.0,70.1] until2p7(s29) || -> until2p7(s30)* node4(s29). % 75.92/76.14 226[0:SoR:97.0,70.1] until2p7(s30) || -> until2p7(s31)* node4(s30). % 75.92/76.14 227[0:SoR:96.0,70.1] until2p7(s31) || -> until2p7(s32)* node4(s31). % 75.92/76.14 228[0:SoR:95.0,70.1] until2p7(s32) || -> until2p7(s33)* node4(s32). % 75.92/76.14 229[0:SoR:94.0,70.1] until2p7(s33) || -> until2p7(s34)* node4(s33). % 75.92/76.14 230[0:SoR:93.0,70.1] until2p7(s34) || -> until2p7(s35)* node4(s34). % 75.92/76.14 231[0:SoR:92.0,70.1] until2p7(s35) || -> until2p7(s36)* node4(s35). % 75.92/76.14 232[0:SoR:91.0,70.1] until2p7(s36) || -> until2p7(s37)* node4(s36). % 75.92/76.14 233[0:SoR:192.0,66.2] until5(s49) || -> loop xuntil6(s49)*. % 75.92/76.14 234[0:MRR:233.2,76.0] until5(s49) || -> loop*. % 75.92/76.14 235[0:SoR:90.0,70.1] until2p7(s37) || -> until2p7(s38)* node4(s37). % 75.92/76.14 236[0:SoR:89.0,70.1] until2p7(s38) || -> until2p7(s39)* node4(s38). % 75.92/76.14 237[0:SoR:88.0,70.1] until2p7(s39) || -> until2p7(s40)* node4(s39). % 75.92/76.14 238[0:SoR:87.0,70.1] until2p7(s40) || -> until2p7(s41)* node4(s40). % 75.92/76.14 239[0:SoR:86.0,70.1] until2p7(s41) || -> until2p7(s42)* node4(s41). % 75.92/76.14 240[0:SoR:85.0,70.1] until2p7(s42) || -> until2p7(s43)* node4(s42). % 75.92/76.14 241[0:SoR:84.0,70.1] until2p7(s43) || -> until2p7(s44)* node4(s43). % 75.92/76.14 242[0:Res:49.0,51.0] || -> trans(s48,s49)*. % 75.92/76.14 243[0:Res:48.0,51.0] || -> trans(s47,s48)*. % 75.92/76.14 244[0:Res:47.0,51.0] || -> trans(s46,s47)*. % 75.92/76.14 245[0:Res:46.0,51.0] || -> trans(s45,s46)*. % 75.92/76.14 246[0:Res:45.0,51.0] || -> trans(s44,s45)*. % 75.92/76.14 247[0:Res:44.0,51.0] || -> trans(s43,s44)*. % 75.92/76.14 248[0:Res:43.0,51.0] || -> trans(s42,s43)*. % 75.92/76.14 249[0:Res:42.0,51.0] || -> trans(s41,s42)*. % 75.92/76.14 250[0:Res:41.0,51.0] || -> trans(s40,s41)*. % 75.92/76.14 251[0:Res:40.0,51.0] || -> trans(s39,s40)*. % 75.92/76.14 252[0:Res:39.0,51.0] || -> trans(s38,s39)*. % 75.92/76.14 253[0:Res:38.0,51.0] || -> trans(s37,s38)*. % 75.92/76.14 254[0:Res:37.0,51.0] || -> trans(s36,s37)*. % 75.92/76.14 255[0:Res:36.0,51.0] || -> trans(s35,s36)*. % 75.92/76.14 256[0:Res:35.0,51.0] || -> trans(s34,s35)*. % 75.92/76.14 257[0:Res:34.0,51.0] || -> trans(s33,s34)*. % 75.92/76.14 258[0:Res:33.0,51.0] || -> trans(s32,s33)*. % 75.92/76.14 259[0:Res:32.0,51.0] || -> trans(s31,s32)*. % 75.92/76.14 260[0:Res:31.0,51.0] || -> trans(s30,s31)*. % 75.92/76.14 261[0:Res:30.0,51.0] || -> trans(s29,s30)*. % 75.92/76.14 262[0:Res:29.0,51.0] || -> trans(s28,s29)*. % 75.92/76.14 263[0:Res:28.0,51.0] || -> trans(s27,s28)*. % 75.92/76.14 264[0:Res:27.0,51.0] || -> trans(s26,s27)*. % 75.92/76.14 265[0:Res:26.0,51.0] || -> trans(s25,s26)*. % 75.92/76.14 266[0:Res:25.0,51.0] || -> trans(s24,s25)*. % 75.92/76.14 267[0:Res:24.0,51.0] || -> trans(s23,s24)*. % 75.92/76.14 268[0:Res:23.0,51.0] || -> trans(s22,s23)*. % 75.92/76.14 269[0:Res:22.0,51.0] || -> trans(s21,s22)*. % 75.92/76.14 270[0:Res:21.0,51.0] || -> trans(s20,s21)*. % 75.92/76.14 271[0:Res:20.0,51.0] || -> trans(s19,s20)*. % 75.92/76.14 272[0:Res:19.0,51.0] || -> trans(s18,s19)*. % 75.92/76.14 273[0:Res:18.0,51.0] || -> trans(s17,s18)*. % 75.92/76.14 274[0:Res:17.0,51.0] || -> trans(s16,s17)*. % 75.92/76.14 275[0:Res:16.0,51.0] || -> trans(s15,s16)*. % 75.92/76.14 276[0:Res:15.0,51.0] || -> trans(s14,s15)*. % 75.92/76.14 277[0:Res:14.0,51.0] || -> trans(s13,s14)*. % 75.92/76.14 278[0:Res:13.0,51.0] || -> trans(s12,s13)*. % 75.92/76.14 279[0:Res:12.0,51.0] || -> trans(s11,s12)*. % 75.92/76.14 280[0:Res:11.0,51.0] || -> trans(s10,s11)*. % 75.92/76.14 281[0:Res:10.0,51.0] || -> trans(s9,s10)*. % 75.92/76.14 282[0:Res:9.0,51.0] || -> trans(s8,s9)*. % 75.92/76.14 283[0:Res:8.0,51.0] || -> trans(s7,s8)*. % 75.92/76.14 284[0:Res:7.0,51.0] || -> trans(s6,s7)*. % 75.92/76.14 285[0:Res:6.0,51.0] || -> trans(s5,s6)*. % 75.92/76.14 286[0:Res:5.0,51.0] || -> trans(s4,s5)*. % 75.92/76.14 287[0:Res:4.0,51.0] || -> trans(s3,s4)*. % 75.92/76.14 288[0:Res:3.0,51.0] || -> trans(s2,s3)*. % 75.92/76.14 289[0:Res:2.0,51.0] || -> trans(s1,s2)*. % 75.92/76.14 290[0:Res:1.0,51.0] || -> trans(s0,s1)*. % 75.92/76.14 291[0:Res:242.0,60.0] || -> node2(s48,s49)*. % 75.92/76.14 292[0:Res:243.0,60.0] || -> node2(s47,s48)*. % 75.92/76.14 293[0:Res:244.0,60.0] || -> node2(s46,s47)*. % 75.92/76.14 294[0:Res:245.0,60.0] || -> node2(s45,s46)*. % 75.92/76.14 295[0:Res:246.0,60.0] || -> node2(s44,s45)*. % 75.92/76.14 296[0:Res:247.0,60.0] || -> node2(s43,s44)*. % 75.92/76.14 297[0:Res:248.0,60.0] || -> node2(s42,s43)*. % 75.92/76.14 298[0:Res:249.0,60.0] || -> node2(s41,s42)*. % 75.92/76.14 299[0:Res:242.0,62.1] always3(s48) || -> always3(s49)*. % 75.92/76.14 300[0:Res:243.0,62.1] always3(s47) || -> always3(s48)*. % 75.92/76.14 301[0:Res:244.0,62.1] always3(s46) || -> always3(s47)*. % 75.92/76.14 302[0:Res:245.0,62.1] always3(s45) || -> always3(s46)*. % 75.92/76.14 303[0:Res:246.0,62.1] always3(s44) || -> always3(s45)*. % 75.92/76.14 304[0:Res:247.0,62.1] always3(s43) || -> always3(s44)*. % 75.92/76.14 305[0:Res:248.0,62.1] always3(s42) || -> always3(s43)*. % 75.92/76.14 306[0:Res:249.0,62.1] always3(s41) || -> always3(s42)*. % 75.92/76.14 307[0:Res:250.0,62.1] always3(s40) || -> always3(s41)*. % 75.92/76.14 308[0:Res:250.0,60.0] || -> node2(s40,s41)*. % 75.92/76.14 309[0:Res:251.0,62.1] always3(s39) || -> always3(s40)*. % 75.92/76.14 310[0:Res:251.0,60.0] || -> node2(s39,s40)*. % 75.92/76.14 311[0:Res:252.0,62.1] always3(s38) || -> always3(s39)*. % 75.92/76.14 312[0:Res:252.0,60.0] || -> node2(s38,s39)*. % 75.92/76.14 313[0:Res:253.0,62.1] always3(s37) || -> always3(s38)*. % 75.92/76.14 314[0:Res:253.0,60.0] || -> node2(s37,s38)*. % 75.92/76.14 364[0:Res:254.0,62.1] always3(s36) || -> always3(s37)*. % 75.92/76.14 365[0:Res:254.0,60.0] || -> node2(s36,s37)*. % 75.92/76.14 366[0:Res:255.0,62.1] always3(s35) || -> always3(s36)*. % 75.92/76.14 367[0:Res:255.0,60.0] || -> node2(s35,s36)*. % 75.92/76.14 368[0:Res:256.0,62.1] always3(s34) || -> always3(s35)*. % 75.92/76.14 369[0:Res:256.0,60.0] || -> node2(s34,s35)*. % 75.92/76.14 370[0:Res:257.0,62.1] always3(s33) || -> always3(s34)*. % 75.92/76.14 371[0:Res:257.0,60.0] || -> node2(s33,s34)*. % 75.92/76.14 421[0:Res:258.0,62.1] always3(s32) || -> always3(s33)*. % 75.92/76.14 422[0:Res:258.0,60.0] || -> node2(s32,s33)*. % 75.92/76.14 423[0:Res:259.0,62.1] always3(s31) || -> always3(s32)*. % 75.92/76.14 424[0:Res:259.0,60.0] || -> node2(s31,s32)*. % 75.92/76.14 425[0:Res:260.0,62.1] always3(s30) || -> always3(s31)*. % 75.92/76.14 426[0:Res:260.0,60.0] || -> node2(s30,s31)*. % 75.92/76.14 427[0:Res:261.0,62.1] always3(s29) || -> always3(s30)*. % 75.92/76.14 428[0:Res:261.0,60.0] || -> node2(s29,s30)*. % 75.92/76.14 450[0:Res:262.0,62.1] always3(s28) || -> always3(s29)*. % 75.92/76.14 451[0:Res:262.0,60.0] || -> node2(s28,s29)*. % 75.92/76.14 453[0:Res:263.0,62.1] always3(s27) || -> always3(s28)*. % 75.92/76.14 454[0:Res:263.0,60.0] || -> node2(s27,s28)*. % 75.92/76.14 456[0:Res:264.0,62.1] always3(s26) || -> always3(s27)*. % 75.92/76.14 457[0:Res:264.0,60.0] || -> node2(s26,s27)*. % 75.92/76.14 459[0:Res:265.0,62.1] always3(s25) || -> always3(s26)*. % 75.92/76.14 460[0:Res:265.0,60.0] || -> node2(s25,s26)*. % 75.92/76.14 462[0:Res:266.0,62.1] always3(s24) || -> always3(s25)*. % 75.92/76.14 463[0:Res:266.0,60.0] || -> node2(s24,s25)*. % 75.92/76.14 465[0:Res:267.0,62.1] always3(s23) || -> always3(s24)*. % 75.92/76.14 466[0:Res:267.0,60.0] || -> node2(s23,s24)*. % 75.92/76.14 468[0:Res:268.0,62.1] always3(s22) || -> always3(s23)*. % 75.92/76.14 469[0:Res:268.0,60.0] || -> node2(s22,s23)*. % 75.92/76.14 471[0:Res:269.0,62.1] always3(s21) || -> always3(s22)*. % 75.92/76.14 472[0:Res:269.0,60.0] || -> node2(s21,s22)*. % 75.92/76.14 474[0:Res:270.0,62.1] always3(s20) || -> always3(s21)*. % 75.92/76.14 475[0:Res:270.0,60.0] || -> node2(s20,s21)*. % 75.92/76.14 477[0:Res:271.0,62.1] always3(s19) || -> always3(s20)*. % 75.92/76.14 478[0:Res:271.0,60.0] || -> node2(s19,s20)*. % 75.92/76.14 480[0:Res:272.0,62.1] always3(s18) || -> always3(s19)*. % 75.92/76.14 481[0:Res:272.0,60.0] || -> node2(s18,s19)*. % 75.92/76.14 483[0:Res:273.0,62.1] always3(s17) || -> always3(s18)*. % 75.92/76.14 484[0:Res:273.0,60.0] || -> node2(s17,s18)*. % 75.92/76.14 486[0:Res:274.0,62.1] always3(s16) || -> always3(s17)*. % 75.92/76.14 487[0:Res:274.0,60.0] || -> node2(s16,s17)*. % 75.92/76.14 489[0:Res:275.0,62.1] always3(s15) || -> always3(s16)*. % 75.92/76.14 490[0:Res:275.0,60.0] || -> node2(s15,s16)*. % 75.92/76.14 492[0:Res:276.0,62.1] always3(s14) || -> always3(s15)*. % 75.92/76.14 493[0:Res:276.0,60.0] || -> node2(s14,s15)*. % 75.92/76.14 495[0:Res:277.0,62.1] always3(s13) || -> always3(s14)*. % 75.92/76.14 496[0:Res:277.0,60.0] || -> node2(s13,s14)*. % 75.92/76.14 498[0:Res:278.0,62.1] always3(s12) || -> always3(s13)*. % 75.92/76.14 499[0:Res:278.0,60.0] || -> node2(s12,s13)*. % 75.92/76.14 501[0:Res:279.0,62.1] always3(s11) || -> always3(s12)*. % 75.92/76.14 502[0:Res:279.0,60.0] || -> node2(s11,s12)*. % 75.92/76.14 504[0:Res:280.0,62.1] always3(s10) || -> always3(s11)*. % 75.92/76.14 505[0:Res:280.0,60.0] || -> node2(s10,s11)*. % 75.92/76.14 507[0:Res:281.0,62.1] always3(s9) || -> always3(s10)*. % 75.92/76.14 508[0:Res:281.0,60.0] || -> node2(s9,s10)*. % 75.92/76.14 510[0:Res:282.0,62.1] always3(s8) || -> always3(s9)*. % 75.92/76.14 511[0:Res:282.0,60.0] || -> node2(s8,s9)*. % 75.92/76.14 513[0:Res:283.0,62.1] always3(s7) || -> always3(s8)*. % 75.92/76.14 514[0:Res:283.0,60.0] || -> node2(s7,s8)*. % 75.92/76.14 516[0:Res:284.0,62.1] always3(s6) || -> always3(s7)*. % 75.92/76.14 517[0:Res:284.0,60.0] || -> node2(s6,s7)*. % 75.92/76.14 519[0:Res:285.0,62.1] always3(s5) || -> always3(s6)*. % 75.92/76.14 520[0:Res:285.0,60.0] || -> node2(s5,s6)*. % 75.92/76.14 522[0:Res:286.0,62.1] always3(s4) || -> always3(s5)*. % 75.92/76.14 523[0:Res:286.0,60.0] || -> node2(s4,s5)*. % 75.92/76.14 525[0:Res:287.0,62.1] always3(s3) || -> always3(s4)*. % 75.92/76.14 526[0:Res:287.0,60.0] || -> node2(s3,s4)*. % 75.92/76.14 528[0:Res:288.0,62.1] always3(s2) || -> always3(s3)*. % 75.92/76.14 529[0:Res:288.0,60.0] || -> node2(s2,s3)*. % 75.92/76.14 531[0:Res:289.0,62.1] always3(s1) || -> always3(s2)*. % 75.92/76.14 532[0:Res:289.0,60.0] || -> node2(s1,s2)*. % 75.92/76.14 534[0:Res:290.0,62.1] always3(s0) || -> always3(s1)*. % 75.92/76.14 535[0:Res:290.0,60.0] || -> node2(s0,s1)*. % 75.92/76.14 536[0:Res:291.0,58.1] m_main_v_request(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy). % 75.92/76.14 537[0:Res:292.0,58.1] m_main_v_request(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy). % 75.92/76.14 538[0:Res:293.0,58.1] m_main_v_request(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy). % 75.92/76.14 539[0:SoR:83.0,70.1] until2p7(s44) || -> until2p7(s45)* node4(s44). % 75.92/76.14 540[0:Res:294.0,58.1] m_main_v_request(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy). % 75.92/76.14 541[0:Res:295.0,58.1] m_main_v_request(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy). % 75.92/76.14 542[0:Res:296.0,58.1] m_main_v_request(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy). % 75.92/76.14 543[0:Res:297.0,58.1] m_main_v_request(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy). % 75.92/76.14 544[0:SoR:82.0,70.1] until2p7(s45) || -> until2p7(s46)* node4(s45). % 75.92/76.14 545[0:Res:298.0,58.1] m_main_v_request(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy). % 75.92/76.14 546[0:Res:308.0,58.1] m_main_v_request(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy). % 75.92/76.14 547[0:Res:310.0,58.1] m_main_v_request(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy). % 75.92/76.14 548[0:Res:312.0,58.1] m_main_v_request(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy). % 75.92/76.14 549[0:SoR:81.0,70.1] until2p7(s46) || -> until2p7(s47)* node4(s46). % 75.92/76.14 550[0:Res:314.0,58.1] m_main_v_request(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy). % 75.92/76.14 551[0:Res:365.0,58.1] m_main_v_request(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy). % 75.92/76.14 552[0:Res:367.0,58.1] m_main_v_request(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy). % 75.92/76.14 553[0:Res:369.0,58.1] m_main_v_request(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy). % 75.92/76.14 554[0:SoR:80.0,70.1] until2p7(s47) || -> until2p7(s48)* node4(s47). % 75.92/76.14 555[0:Res:371.0,58.1] m_main_v_request(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy). % 75.92/76.14 556[0:Res:422.0,58.1] m_main_v_request(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy). % 75.92/76.14 557[0:Res:424.0,58.1] m_main_v_request(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy). % 75.92/76.14 558[0:Res:426.0,58.1] m_main_v_request(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy). % 75.92/76.14 559[0:SoR:79.0,70.1] until2p7(s48) || -> until2p7(s49)* node4(s48). % 75.92/76.14 560[0:Res:428.0,58.1] m_main_v_request(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy). % 75.92/76.14 561[0:Res:451.0,58.1] m_main_v_request(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy). % 75.92/76.14 562[0:Res:454.0,58.1] m_main_v_request(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy). % 75.92/76.14 563[0:Res:457.0,58.1] m_main_v_request(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy). % 75.92/76.14 564[0:Res:460.0,58.1] m_main_v_request(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy). % 75.92/76.14 565[0:Res:463.0,58.1] m_main_v_request(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy). % 75.92/76.14 566[0:Res:466.0,58.1] m_main_v_request(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy). % 75.92/76.14 567[0:Res:469.0,58.1] m_main_v_request(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy). % 75.92/76.14 568[0:Res:472.0,58.1] m_main_v_request(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy). % 75.92/76.14 569[0:Res:475.0,58.1] m_main_v_request(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy). % 75.92/76.14 570[0:Res:478.0,58.1] m_main_v_request(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy). % 75.92/76.14 571[0:Res:481.0,58.1] m_main_v_request(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy). % 75.92/76.14 572[0:Res:484.0,58.1] m_main_v_request(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy). % 75.92/76.14 573[0:Res:487.0,58.1] m_main_v_request(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy). % 75.92/76.14 574[0:Res:490.0,58.1] m_main_v_request(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy). % 75.92/76.14 575[0:Res:493.0,58.1] m_main_v_request(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy). % 75.92/76.14 576[0:Res:496.0,58.1] m_main_v_request(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy). % 75.92/76.14 577[0:Res:499.0,58.1] m_main_v_request(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy). % 75.92/76.14 578[0:Res:502.0,58.1] m_main_v_request(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy). % 75.92/76.14 579[0:Res:505.0,58.1] m_main_v_request(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy). % 75.92/76.14 580[0:Res:508.0,58.1] m_main_v_request(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy). % 75.92/76.14 581[0:Res:511.0,58.1] m_main_v_request(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy). % 75.92/76.14 582[0:Res:514.0,58.1] m_main_v_request(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy). % 75.92/76.14 583[0:Res:517.0,58.1] m_main_v_request(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy). % 75.92/76.14 584[0:Res:520.0,58.1] m_main_v_request(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy). % 75.92/76.14 585[0:Res:523.0,58.1] m_main_v_request(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy). % 75.92/76.14 586[0:Res:526.0,58.1] m_main_v_request(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy). % 75.92/76.14 587[0:Res:529.0,58.1] m_main_v_request(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy). % 75.92/76.14 588[0:Res:532.0,58.1] m_main_v_request(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy). % 75.92/76.14 589[0:Res:535.0,58.1] m_main_v_request(s0) || m_main_v_state(s0,c_ready)* -> m_main_v_state(s1,c_busy). % 75.92/76.14 590[0:MRR:589.1,55.0] m_main_v_request(s0) || -> m_main_v_state(s1,c_busy)*. % 75.92/76.14 591[0:SoR:299.0,65.1] node4(s48) || -> always3(s49)*. % 75.92/76.14 592[0:SoR:300.0,65.1] node4(s47) || -> always3(s48)*. % 75.92/76.14 593[0:SoR:301.0,65.1] node4(s46) || -> always3(s47)*. % 75.92/76.14 594[0:SoR:302.0,65.1] node4(s45) || -> always3(s46)*. % 75.92/76.14 595[0:SoR:303.0,65.1] node4(s44) || -> always3(s45)*. % 75.92/76.14 596[0:SoR:304.0,65.1] node4(s43) || -> always3(s44)*. % 75.92/76.14 597[0:SoR:305.0,65.1] node4(s42) || -> always3(s43)*. % 75.92/76.14 598[0:SoR:306.0,65.1] node4(s41) || -> always3(s42)*. % 75.92/76.14 599[0:SoR:307.0,65.1] node4(s40) || -> always3(s41)*. % 75.92/76.14 600[0:SoR:309.0,65.1] node4(s39) || -> always3(s40)*. % 75.92/76.14 601[0:SoR:311.0,65.1] node4(s38) || -> always3(s39)*. % 75.92/76.14 602[0:SoR:313.0,65.1] node4(s37) || -> always3(s38)*. % 75.92/76.14 603[0:SoR:364.0,65.1] node4(s36) || -> always3(s37)*. % 75.92/76.14 604[0:SoR:366.0,65.1] node4(s35) || -> always3(s36)*. % 75.92/76.14 605[0:SoR:368.0,65.1] node4(s34) || -> always3(s35)*. % 75.92/76.14 606[0:SoR:370.0,65.1] node4(s33) || -> always3(s34)*. % 75.92/76.14 607[0:SoR:421.0,65.1] node4(s32) || -> always3(s33)*. % 75.92/76.14 608[0:SoR:423.0,65.1] node4(s31) || -> always3(s32)*. % 75.92/76.14 609[0:SoR:425.0,65.1] node4(s30) || -> always3(s31)*. % 75.92/76.14 610[0:SoR:427.0,65.1] node4(s29) || -> always3(s30)*. % 75.92/76.14 611[0:SoR:450.0,65.1] node4(s28) || -> always3(s29)*. % 75.92/76.14 612[0:SoR:453.0,65.1] node4(s27) || -> always3(s28)*. % 75.92/76.14 613[0:SoR:456.0,65.1] node4(s26) || -> always3(s27)*. % 75.92/76.14 614[0:SoR:459.0,65.1] node4(s25) || -> always3(s26)*. % 75.92/76.14 615[0:SoR:462.0,65.1] node4(s24) || -> always3(s25)*. % 75.92/76.14 616[0:SoR:465.0,65.1] node4(s23) || -> always3(s24)*. % 75.92/76.14 617[0:SoR:468.0,65.1] node4(s22) || -> always3(s23)*. % 75.92/76.14 618[0:SoR:471.0,65.1] node4(s21) || -> always3(s22)*. % 75.92/76.14 619[0:SoR:474.0,65.1] node4(s20) || -> always3(s21)*. % 75.92/76.14 620[0:SoR:477.0,65.1] node4(s19) || -> always3(s20)*. % 75.92/76.14 621[0:SoR:480.0,65.1] node4(s18) || -> always3(s19)*. % 75.92/76.14 622[0:SoR:483.0,65.1] node4(s17) || -> always3(s18)*. % 75.92/76.14 623[0:SoR:486.0,65.1] node4(s16) || -> always3(s17)*. % 75.92/76.14 624[0:SoR:489.0,65.1] node4(s15) || -> always3(s16)*. % 75.92/76.14 625[0:SoR:492.0,65.1] node4(s14) || -> always3(s15)*. % 75.92/76.14 626[0:SoR:495.0,65.1] node4(s13) || -> always3(s14)*. % 75.92/76.14 627[0:SoR:498.0,65.1] node4(s12) || -> always3(s13)*. % 75.92/76.14 628[0:SoR:501.0,65.1] node4(s11) || -> always3(s12)*. % 75.92/76.14 629[0:SoR:504.0,65.1] node4(s10) || -> always3(s11)*. % 75.92/76.14 630[0:SoR:507.0,65.1] node4(s9) || -> always3(s10)*. % 75.92/76.14 631[0:SoR:510.0,65.1] node4(s8) || -> always3(s9)*. % 75.92/76.14 632[0:SoR:513.0,65.1] node4(s7) || -> always3(s8)*. % 75.92/76.14 633[0:SoR:516.0,65.1] node4(s6) || -> always3(s7)*. % 75.92/76.14 634[0:SoR:519.0,65.1] node4(s5) || -> always3(s6)*. % 75.92/76.14 635[0:SoR:522.0,65.1] node4(s4) || -> always3(s5)*. % 75.92/76.14 636[0:SoR:525.0,65.1] node4(s3) || -> always3(s4)*. % 75.92/76.14 637[0:SoR:528.0,65.1] node4(s2) || -> always3(s3)*. % 75.92/76.14 639[0:SoR:534.0,65.1] node4(s0) || -> always3(s1)*. % 75.92/76.14 640[0:SoR:591.0,66.2] until5(s48) || -> always3(s49)* xuntil6(s48). % 75.92/76.14 641[0:SoR:592.0,66.2] until5(s47) || -> always3(s48)* xuntil6(s47). % 75.92/76.14 642[0:SoR:593.0,66.2] until5(s46) || -> always3(s47)* xuntil6(s46). % 75.92/76.14 643[0:SoR:594.0,66.2] until5(s45) || -> always3(s46)* xuntil6(s45). % 75.92/76.14 644[0:SoR:595.0,66.2] until5(s44) || -> always3(s45)* xuntil6(s44). % 75.92/76.14 645[0:SoR:596.0,66.2] until5(s43) || -> always3(s44)* xuntil6(s43). % 75.92/76.14 646[0:SoR:597.0,66.2] until5(s42) || -> always3(s43)* xuntil6(s42). % 75.92/76.14 647[0:SoR:598.0,66.2] until5(s41) || -> always3(s42)* xuntil6(s41). % 75.92/76.14 648[0:SoR:599.0,66.2] until5(s40) || -> always3(s41)* xuntil6(s40). % 75.92/76.14 649[0:SoR:600.0,66.2] until5(s39) || -> always3(s40)* xuntil6(s39). % 75.92/76.14 650[0:SoR:601.0,66.2] until5(s38) || -> always3(s39)* xuntil6(s38). % 75.92/76.14 651[0:SoR:602.0,66.2] until5(s37) || -> always3(s38)* xuntil6(s37). % 75.92/76.14 652[0:SoR:603.0,66.2] until5(s36) || -> always3(s37)* xuntil6(s36). % 75.92/76.14 653[0:SoR:604.0,66.2] until5(s35) || -> always3(s36)* xuntil6(s35). % 75.92/76.14 654[0:SoR:605.0,66.2] until5(s34) || -> always3(s35)* xuntil6(s34). % 75.92/76.14 655[0:SoR:606.0,66.2] until5(s33) || -> always3(s34)* xuntil6(s33). % 75.92/76.14 656[0:SoR:607.0,66.2] until5(s32) || -> always3(s33)* xuntil6(s32). % 75.92/76.14 657[0:SoR:608.0,66.2] until5(s31) || -> always3(s32)* xuntil6(s31). % 75.92/76.14 658[0:SoR:609.0,66.2] until5(s30) || -> always3(s31)* xuntil6(s30). % 75.92/76.14 659[0:SoR:610.0,66.2] until5(s29) || -> always3(s30)* xuntil6(s29). % 75.92/76.14 660[0:SoR:611.0,66.2] until5(s28) || -> always3(s29)* xuntil6(s28). % 75.92/76.14 661[0:SoR:612.0,66.2] until5(s27) || -> always3(s28)* xuntil6(s27). % 75.92/76.14 662[0:SoR:613.0,66.2] until5(s26) || -> always3(s27)* xuntil6(s26). % 75.92/76.14 663[0:SoR:614.0,66.2] until5(s25) || -> always3(s26)* xuntil6(s25). % 75.92/76.14 664[0:SoR:615.0,66.2] until5(s24) || -> always3(s25)* xuntil6(s24). % 75.92/76.14 665[0:SoR:616.0,66.2] until5(s23) || -> always3(s24)* xuntil6(s23). % 75.92/76.14 666[0:SoR:617.0,66.2] until5(s22) || -> always3(s23)* xuntil6(s22). % 75.92/76.14 667[0:SoR:618.0,66.2] until5(s21) || -> always3(s22)* xuntil6(s21). % 75.92/76.14 668[0:SoR:619.0,66.2] until5(s20) || -> always3(s21)* xuntil6(s20). % 75.92/76.14 669[0:SoR:620.0,66.2] until5(s19) || -> always3(s20)* xuntil6(s19). % 75.92/76.14 670[0:SoR:621.0,66.2] until5(s18) || -> always3(s19)* xuntil6(s18). % 75.92/76.14 671[0:SoR:622.0,66.2] until5(s17) || -> always3(s18)* xuntil6(s17). % 75.92/76.14 672[0:SoR:623.0,66.2] until5(s16) || -> always3(s17)* xuntil6(s16). % 75.92/76.14 673[0:SoR:624.0,66.2] until5(s15) || -> always3(s16)* xuntil6(s15). % 75.92/76.14 674[0:SoR:625.0,66.2] until5(s14) || -> always3(s15)* xuntil6(s14). % 75.92/76.14 675[0:SoR:626.0,66.2] until5(s13) || -> always3(s14)* xuntil6(s13). % 75.92/76.14 676[0:SoR:627.0,66.2] until5(s12) || -> always3(s13)* xuntil6(s12). % 75.92/76.14 677[0:SoR:628.0,66.2] until5(s11) || -> always3(s12)* xuntil6(s11). % 75.92/76.14 678[0:SoR:629.0,66.2] until5(s10) || -> always3(s11)* xuntil6(s10). % 75.92/76.14 679[0:SoR:630.0,66.2] until5(s9) || -> always3(s10)* xuntil6(s9). % 75.92/76.14 680[0:SoR:631.0,66.2] until5(s8) || -> always3(s9)* xuntil6(s8). % 75.92/76.14 681[0:SoR:632.0,66.2] until5(s7) || -> always3(s8)* xuntil6(s7). % 75.92/76.14 682[0:SoR:633.0,66.2] until5(s6) || -> always3(s7)* xuntil6(s6). % 75.92/76.14 683[0:SoR:634.0,66.2] until5(s5) || -> always3(s6)* xuntil6(s5). % 75.92/76.14 684[0:SoR:635.0,66.2] until5(s4) || -> always3(s5)* xuntil6(s4). % 75.92/76.14 685[0:SoR:636.0,66.2] until5(s3) || -> always3(s4)* xuntil6(s3). % 75.92/76.14 686[0:SoR:637.0,66.2] until5(s2) || -> always3(s3)* xuntil6(s2). % 75.92/76.14 689[0:SoR:639.0,74.1] || -> always3(s1)* xuntil6(s0). % 75.92/76.14 690[1:Spt:689.0] || -> always3(s1)*. % 75.92/76.14 691[1:MRR:531.0,690.0] || -> always3(s2)*. % 75.92/76.14 692[1:MRR:528.0,691.0] || -> always3(s3)*. % 75.92/76.14 693[1:MRR:525.0,692.0] || -> always3(s4)*. % 75.92/76.14 694[1:MRR:522.0,693.0] || -> always3(s5)*. % 75.92/76.14 695[1:MRR:519.0,694.0] || -> always3(s6)*. % 75.92/76.14 696[1:MRR:516.0,695.0] || -> always3(s7)*. % 75.92/76.14 697[1:MRR:513.0,696.0] || -> always3(s8)*. % 75.92/76.14 698[1:MRR:510.0,697.0] || -> always3(s9)*. % 75.92/76.14 699[1:MRR:507.0,698.0] || -> always3(s10)*. % 75.92/76.14 700[1:MRR:504.0,699.0] || -> always3(s11)*. % 75.92/76.14 701[1:MRR:501.0,700.0] || -> always3(s12)*. % 75.92/76.14 702[1:MRR:498.0,701.0] || -> always3(s13)*. % 75.92/76.14 703[1:MRR:495.0,702.0] || -> always3(s14)*. % 75.92/76.14 704[1:MRR:492.0,703.0] || -> always3(s15)*. % 75.92/76.14 705[1:MRR:489.0,704.0] || -> always3(s16)*. % 75.92/76.14 706[1:MRR:486.0,705.0] || -> always3(s17)*. % 75.92/76.14 707[1:MRR:483.0,706.0] || -> always3(s18)*. % 75.92/76.14 708[1:MRR:480.0,707.0] || -> always3(s19)*. % 75.92/76.14 709[1:MRR:477.0,708.0] || -> always3(s20)*. % 75.92/76.14 710[1:MRR:474.0,709.0] || -> always3(s21)*. % 75.92/76.14 711[1:MRR:471.0,710.0] || -> always3(s22)*. % 75.92/76.14 712[1:MRR:468.0,711.0] || -> always3(s23)*. % 75.92/76.14 713[1:MRR:465.0,712.0] || -> always3(s24)*. % 75.92/76.14 714[1:MRR:462.0,713.0] || -> always3(s25)*. % 75.92/76.14 715[1:MRR:459.0,714.0] || -> always3(s26)*. % 75.92/76.14 716[1:MRR:456.0,715.0] || -> always3(s27)*. % 75.92/76.14 717[1:MRR:453.0,716.0] || -> always3(s28)*. % 75.92/76.14 718[1:MRR:450.0,717.0] || -> always3(s29)*. % 75.92/76.14 719[1:MRR:427.0,718.0] || -> always3(s30)*. % 75.92/76.14 720[1:MRR:425.0,719.0] || -> always3(s31)*. % 75.92/76.14 721[1:MRR:423.0,720.0] || -> always3(s32)*. % 75.92/76.14 722[1:MRR:421.0,721.0] || -> always3(s33)*. % 75.92/76.14 723[1:MRR:370.0,722.0] || -> always3(s34)*. % 75.92/76.14 724[1:MRR:368.0,723.0] || -> always3(s35)*. % 75.92/76.14 725[1:MRR:366.0,724.0] || -> always3(s36)*. % 75.92/76.14 726[1:MRR:364.0,725.0] || -> always3(s37)*. % 75.92/76.14 727[1:MRR:313.0,726.0] || -> always3(s38)*. % 75.92/76.14 728[1:MRR:311.0,727.0] || -> always3(s39)*. % 75.92/76.14 729[1:MRR:309.0,728.0] || -> always3(s40)*. % 75.92/76.14 730[1:MRR:307.0,729.0] || -> always3(s41)*. % 75.92/76.14 731[1:MRR:306.0,730.0] || -> always3(s42)*. % 75.92/76.14 732[1:MRR:305.0,731.0] || -> always3(s43)*. % 75.92/76.14 733[1:MRR:304.0,732.0] || -> always3(s44)*. % 75.92/76.14 734[1:MRR:303.0,733.0] || -> always3(s45)*. % 75.92/76.14 735[1:MRR:302.0,734.0] || -> always3(s46)*. % 75.92/76.14 736[1:MRR:301.0,735.0] || -> always3(s47)*. % 75.92/76.14 737[1:MRR:300.0,736.0] || -> always3(s48)*. % 75.92/76.14 738[1:MRR:299.0,737.0] || -> always3(s49)*. % 75.92/76.14 739[1:MRR:78.0,738.0] || -> loop*. % 75.92/76.14 740[1:MRR:52.0,739.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) trans(s49,s0)*. % 75.92/76.14 741[1:Res:740.49,69.2] xuntil6(s49) last(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.14 742[1:Res:740.49,62.1] always3(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.14 743[1:Res:740.49,60.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.14 744[1:MRR:742.0,738.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.14 745[1:SSi:741.1,50.0] xuntil6(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.14 746[2:Spt:744.0] || -> trans(s49,s49)*. % 75.92/76.14 747[2:Res:746.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s49)*. % 75.92/76.14 749[2:Res:746.0,60.0] || -> node2(s49,s49)*. % 75.92/76.14 750[2:SSi:747.1,50.0] xuntil6(s49) || -> until2p7(s49)*. % 75.92/76.14 751[2:Res:749.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> m_main_v_state(s49,c_busy). % 75.92/76.14 752[2:MRR:751.1,53.1] m_main_v_request(s49) || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 754[0:SoR:590.0,64.1] node4(s0) || -> m_main_v_state(s1,c_busy)*. % 75.92/76.14 756[2:SoR:752.0,64.1] node4(s49) || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 758[0:SoR:754.0,74.1] || -> m_main_v_state(s1,c_busy)* xuntil6(s0). % 75.92/76.14 759[3:Spt:758.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.14 761[3:Res:759.0,61.1] always3(s1) || -> . % 75.92/76.14 762[3:SSi:761.0,690.0] || -> . % 75.92/76.14 763[3:Spt:762.0,758.0,759.0] || m_main_v_state(s1,c_busy)*+ -> . % 75.92/76.14 764[3:Spt:762.0,758.1] || -> xuntil6(s0)*. % 75.92/76.14 765[3:MRR:176.0,764.0] || -> until5(s1)*. % 75.92/76.14 772[2:SoR:756.0,66.2] until5(s49) || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.14 774[0:SoR:536.0,64.1] node4(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy). % 75.92/76.14 777[0:SoR:537.0,64.1] node4(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy). % 75.92/76.14 780[0:SoR:538.0,64.1] node4(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy). % 75.92/76.14 783[0:SoR:540.0,64.1] node4(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy). % 75.92/76.14 786[0:SoR:541.0,64.1] node4(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy). % 75.92/76.14 789[0:SoR:542.0,64.1] node4(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy). % 75.92/76.14 792[0:SoR:543.0,64.1] node4(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy). % 75.92/76.14 795[0:SoR:545.0,64.1] node4(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy). % 75.92/76.14 798[0:SoR:546.0,64.1] node4(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy). % 75.92/76.14 801[0:SoR:547.0,64.1] node4(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy). % 75.92/76.14 804[0:SoR:548.0,64.1] node4(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy). % 75.92/76.14 807[0:SoR:550.0,64.1] node4(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy). % 75.92/76.14 810[0:SoR:551.0,64.1] node4(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy). % 75.92/76.14 813[0:SoR:552.0,64.1] node4(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy). % 75.92/76.14 816[0:SoR:553.0,64.1] node4(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy). % 75.92/76.14 819[0:SoR:555.0,64.1] node4(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy). % 75.92/76.14 822[0:SoR:556.0,64.1] node4(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy). % 75.92/76.14 825[0:SoR:557.0,64.1] node4(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy). % 75.92/76.14 828[0:SoR:558.0,64.1] node4(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy). % 75.92/76.14 831[0:SoR:560.0,64.1] node4(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy). % 75.92/76.14 834[0:SoR:561.0,64.1] node4(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy). % 75.92/76.14 837[0:SoR:562.0,64.1] node4(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy). % 75.92/76.14 840[0:SoR:563.0,64.1] node4(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy). % 75.92/76.14 843[0:SoR:564.0,64.1] node4(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy). % 75.92/76.14 846[0:SoR:565.0,64.1] node4(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy). % 75.92/76.14 849[0:SoR:566.0,64.1] node4(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy). % 75.92/76.14 852[0:SoR:567.0,64.1] node4(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy). % 75.92/76.14 855[0:SoR:568.0,64.1] node4(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy). % 75.92/76.14 858[0:SoR:569.0,64.1] node4(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy). % 75.92/76.14 861[0:SoR:570.0,64.1] node4(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy). % 75.92/76.14 864[0:SoR:571.0,64.1] node4(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy). % 75.92/76.14 867[0:SoR:572.0,64.1] node4(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy). % 75.92/76.14 870[0:SoR:573.0,64.1] node4(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy). % 75.92/76.14 873[0:SoR:574.0,64.1] node4(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy). % 75.92/76.14 876[0:SoR:575.0,64.1] node4(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy). % 75.92/76.14 879[0:SoR:576.0,64.1] node4(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy). % 75.92/76.14 882[0:SoR:577.0,64.1] node4(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy). % 75.92/76.14 885[0:SoR:578.0,64.1] node4(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy). % 75.92/76.14 888[0:SoR:579.0,64.1] node4(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy). % 75.92/76.14 891[0:SoR:580.0,64.1] node4(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy). % 75.92/76.14 894[0:SoR:581.0,64.1] node4(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy). % 75.92/76.14 897[0:SoR:582.0,64.1] node4(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy). % 75.92/76.14 900[0:SoR:583.0,64.1] node4(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy). % 75.92/76.14 903[0:SoR:584.0,64.1] node4(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy). % 75.92/76.14 906[0:SoR:585.0,64.1] node4(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy). % 75.92/76.14 909[0:SoR:586.0,64.1] node4(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy). % 75.92/76.14 912[0:SoR:587.0,64.1] node4(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy). % 75.92/76.14 915[0:SoR:588.0,64.1] node4(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy). % 75.92/76.14 917[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.14 918[0:SoR:777.0,66.2] until5(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.14 919[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.14 920[0:SoR:783.0,66.2] until5(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.14 921[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.14 922[0:SoR:789.0,66.2] until5(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.14 923[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.14 924[0:SoR:795.0,66.2] until5(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.14 925[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.14 926[0:SoR:801.0,66.2] until5(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.14 927[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.14 928[0:SoR:807.0,66.2] until5(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.14 929[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.14 930[0:SoR:813.0,66.2] until5(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.14 931[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.14 932[0:SoR:819.0,66.2] until5(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.14 933[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.14 934[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.14 935[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.14 936[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.14 937[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.14 938[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.14 939[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.14 940[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.14 941[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.14 942[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.14 943[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.14 944[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.14 945[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.14 946[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.14 947[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.14 948[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.14 949[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.14 950[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.14 951[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.14 952[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.14 953[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.14 954[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.14 955[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.14 956[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.14 957[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.14 958[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.14 959[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.14 960[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.14 961[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.14 962[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.14 963[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.14 964[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.14 965[3:SSi:964.0,690.0,765.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.14 966[4:Spt:965.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.14 968[4:Res:966.0,61.1] always3(s2) || -> . % 75.92/76.14 969[4:SSi:968.0,691.0] || -> . % 75.92/76.14 970[4:Spt:969.0,965.1,966.0] || m_main_v_state(s2,c_busy)*+ -> . % 75.92/76.14 971[4:Spt:969.0,965.0,965.2] || m_main_v_state(s1,c_ready)*+ -> xuntil6(s1). % 75.92/76.14 974[4:Res:53.1,971.0] || -> m_main_v_state(s1,c_busy)* xuntil6(s1). % 75.92/76.14 976[4:MRR:974.0,763.0] || -> xuntil6(s1)*. % 75.92/76.14 977[4:MRR:175.0,976.0] || -> until5(s2)*. % 75.92/76.14 978[4:MRR:963.0,977.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.14 986[5:Spt:978.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.14 988[5:Res:986.0,61.1] always3(s3) || -> . % 75.92/76.14 989[5:SSi:988.0,692.0] || -> . % 75.92/76.14 990[5:Spt:989.0,978.1,986.0] || m_main_v_state(s3,c_busy)*+ -> . % 75.92/76.14 991[5:Spt:989.0,978.0,978.2] || m_main_v_state(s2,c_ready)*+ -> xuntil6(s2). % 75.92/76.14 994[5:Res:53.1,991.0] || -> m_main_v_state(s2,c_busy)* xuntil6(s2). % 75.92/76.14 996[5:MRR:994.0,970.0] || -> xuntil6(s2)*. % 75.92/76.14 997[5:MRR:174.0,996.0] || -> until5(s3)*. % 75.92/76.14 998[5:MRR:962.0,997.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.14 1003[6:Spt:998.2] || -> xuntil6(s3)*. % 75.92/76.14 1004[6:MRR:173.0,1003.0] || -> until5(s4)*. % 75.92/76.14 1005[6:MRR:961.0,1004.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.14 1006[7:Spt:1005.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.14 1008[7:Res:1006.0,61.1] always3(s5) || -> . % 75.92/76.14 1009[7:SSi:1008.0,694.0] || -> . % 75.92/76.14 1010[7:Spt:1009.0,1005.1,1006.0] || m_main_v_state(s5,c_busy)*+ -> . % 75.92/76.14 1011[7:Spt:1009.0,1005.0,1005.2] || m_main_v_state(s4,c_ready)*+ -> xuntil6(s4). % 75.92/76.14 1014[7:Res:53.1,1011.0] || -> m_main_v_state(s4,c_busy)* xuntil6(s4). % 75.92/76.14 1016[8:Spt:1014.1] || -> xuntil6(s4)*. % 75.92/76.14 1017[8:MRR:172.0,1016.0] || -> until5(s5)*. % 75.92/76.14 1018[8:MRR:960.0,1017.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.14 1026[9:Spt:1018.2] || -> xuntil6(s5)*. % 75.92/76.14 1027[9:MRR:171.0,1026.0] || -> until5(s6)*. % 75.92/76.14 1028[9:MRR:959.0,1027.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.14 1029[10:Spt:1028.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.14 1031[10:Res:1029.0,61.1] always3(s7) || -> . % 75.92/76.14 1032[10:SSi:1031.0,696.0] || -> . % 75.92/76.14 1033[10:Spt:1032.0,1028.1,1029.0] || m_main_v_state(s7,c_busy)*+ -> . % 75.92/76.14 1034[10:Spt:1032.0,1028.0,1028.2] || m_main_v_state(s6,c_ready)*+ -> xuntil6(s6). % 75.92/76.14 1037[10:Res:53.1,1034.0] || -> m_main_v_state(s6,c_busy)* xuntil6(s6). % 75.92/76.14 1042[11:Spt:1037.1] || -> xuntil6(s6)*. % 75.92/76.14 1043[11:MRR:170.0,1042.0] || -> until5(s7)*. % 75.92/76.14 1044[11:MRR:958.0,1043.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.14 1046[12:Spt:1044.2] || -> xuntil6(s7)*. % 75.92/76.14 1047[12:MRR:169.0,1046.0] || -> until5(s8)*. % 75.92/76.14 1048[12:MRR:957.0,1047.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.14 1049[13:Spt:1048.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.14 1051[13:Res:1049.0,61.1] always3(s9) || -> . % 75.92/76.14 1052[13:SSi:1051.0,698.0] || -> . % 75.92/76.14 1053[13:Spt:1052.0,1048.1,1049.0] || m_main_v_state(s9,c_busy)*+ -> . % 75.92/76.14 1054[13:Spt:1052.0,1048.0,1048.2] || m_main_v_state(s8,c_ready)*+ -> xuntil6(s8). % 75.92/76.14 1057[13:Res:53.1,1054.0] || -> m_main_v_state(s8,c_busy)* xuntil6(s8). % 75.92/76.14 1059[14:Spt:1057.1] || -> xuntil6(s8)*. % 75.92/76.14 1060[14:MRR:168.0,1059.0] || -> until5(s9)*. % 75.92/76.14 1061[14:MRR:956.0,1060.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.14 1066[15:Spt:1061.2] || -> xuntil6(s9)*. % 75.92/76.14 1067[15:MRR:167.0,1066.0] || -> until5(s10)*. % 75.92/76.14 1068[15:MRR:955.0,1067.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.14 1069[16:Spt:1068.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.14 1071[16:Res:1069.0,61.1] always3(s11) || -> . % 75.92/76.14 1072[16:SSi:1071.0,700.0] || -> . % 75.92/76.14 1073[16:Spt:1072.0,1068.1,1069.0] || m_main_v_state(s11,c_busy)*+ -> . % 75.92/76.14 1074[16:Spt:1072.0,1068.0,1068.2] || m_main_v_state(s10,c_ready)*+ -> xuntil6(s10). % 75.92/76.14 1077[16:Res:53.1,1074.0] || -> m_main_v_state(s10,c_busy)* xuntil6(s10). % 75.92/76.14 1079[17:Spt:1077.1] || -> xuntil6(s10)*. % 75.92/76.14 1080[17:MRR:166.0,1079.0] || -> until5(s11)*. % 75.92/76.14 1081[17:MRR:954.0,1080.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.14 1089[18:Spt:1081.2] || -> xuntil6(s11)*. % 75.92/76.14 1090[18:MRR:165.0,1089.0] || -> until5(s12)*. % 75.92/76.14 1091[18:MRR:953.0,1090.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.14 1092[19:Spt:1091.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.14 1094[19:Res:1092.0,61.1] always3(s13) || -> . % 75.92/76.14 1095[19:SSi:1094.0,702.0] || -> . % 75.92/76.14 1096[19:Spt:1095.0,1091.1,1092.0] || m_main_v_state(s13,c_busy)*+ -> . % 75.92/76.14 1097[19:Spt:1095.0,1091.0,1091.2] || m_main_v_state(s12,c_ready)*+ -> xuntil6(s12). % 75.92/76.14 1100[19:Res:53.1,1097.0] || -> m_main_v_state(s12,c_busy)* xuntil6(s12). % 75.92/76.14 1105[20:Spt:1100.1] || -> xuntil6(s12)*. % 75.92/76.14 1106[20:MRR:164.0,1105.0] || -> until5(s13)*. % 75.92/76.14 1107[20:MRR:952.0,1106.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.14 1109[21:Spt:1107.2] || -> xuntil6(s13)*. % 75.92/76.14 1110[21:MRR:163.0,1109.0] || -> until5(s14)*. % 75.92/76.14 1111[21:MRR:951.0,1110.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.14 1112[22:Spt:1111.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.14 1114[22:Res:1112.0,61.1] always3(s15) || -> . % 75.92/76.14 1115[22:SSi:1114.0,704.0] || -> . % 75.92/76.14 1116[22:Spt:1115.0,1111.1,1112.0] || m_main_v_state(s15,c_busy)*+ -> . % 75.92/76.14 1117[22:Spt:1115.0,1111.0,1111.2] || m_main_v_state(s14,c_ready)*+ -> xuntil6(s14). % 75.92/76.14 1120[22:Res:53.1,1117.0] || -> m_main_v_state(s14,c_busy)* xuntil6(s14). % 75.92/76.14 1122[23:Spt:1120.1] || -> xuntil6(s14)*. % 75.92/76.14 1123[23:MRR:162.0,1122.0] || -> until5(s15)*. % 75.92/76.14 1124[23:MRR:950.0,1123.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.14 1129[24:Spt:1124.2] || -> xuntil6(s15)*. % 75.92/76.14 1130[24:MRR:161.0,1129.0] || -> until5(s16)*. % 75.92/76.14 1131[24:MRR:949.0,1130.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.14 1132[25:Spt:1131.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.14 1134[25:Res:1132.0,61.1] always3(s17) || -> . % 75.92/76.14 1135[25:SSi:1134.0,706.0] || -> . % 75.92/76.14 1136[25:Spt:1135.0,1131.1,1132.0] || m_main_v_state(s17,c_busy)*+ -> . % 75.92/76.14 1137[25:Spt:1135.0,1131.0,1131.2] || m_main_v_state(s16,c_ready)*+ -> xuntil6(s16). % 75.92/76.14 1140[25:Res:53.1,1137.0] || -> m_main_v_state(s16,c_busy)* xuntil6(s16). % 75.92/76.14 1142[26:Spt:1140.1] || -> xuntil6(s16)*. % 75.92/76.14 1143[26:MRR:160.0,1142.0] || -> until5(s17)*. % 75.92/76.14 1144[26:MRR:948.0,1143.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.14 1152[27:Spt:1144.2] || -> xuntil6(s17)*. % 75.92/76.14 1153[27:MRR:159.0,1152.0] || -> until5(s18)*. % 75.92/76.14 1154[27:MRR:947.0,1153.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.14 1155[28:Spt:1154.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.14 1157[28:Res:1155.0,61.1] always3(s19) || -> . % 75.92/76.14 1158[28:SSi:1157.0,708.0] || -> . % 75.92/76.14 1159[28:Spt:1158.0,1154.1,1155.0] || m_main_v_state(s19,c_busy)*+ -> . % 75.92/76.14 1160[28:Spt:1158.0,1154.0,1154.2] || m_main_v_state(s18,c_ready)*+ -> xuntil6(s18). % 75.92/76.14 1163[28:Res:53.1,1160.0] || -> m_main_v_state(s18,c_busy)* xuntil6(s18). % 75.92/76.14 1168[29:Spt:1163.1] || -> xuntil6(s18)*. % 75.92/76.14 1169[29:MRR:158.0,1168.0] || -> until5(s19)*. % 75.92/76.14 1170[29:MRR:946.0,1169.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.14 1172[30:Spt:1170.2] || -> xuntil6(s19)*. % 75.92/76.14 1173[30:MRR:157.0,1172.0] || -> until5(s20)*. % 75.92/76.14 1174[30:MRR:945.0,1173.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.14 1175[31:Spt:1174.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.14 1177[31:Res:1175.0,61.1] always3(s21) || -> . % 75.92/76.14 1178[31:SSi:1177.0,710.0] || -> . % 75.92/76.14 1179[31:Spt:1178.0,1174.1,1175.0] || m_main_v_state(s21,c_busy)*+ -> . % 75.92/76.14 1180[31:Spt:1178.0,1174.0,1174.2] || m_main_v_state(s20,c_ready)*+ -> xuntil6(s20). % 75.92/76.14 1183[31:Res:53.1,1180.0] || -> m_main_v_state(s20,c_busy)* xuntil6(s20). % 75.92/76.14 1185[32:Spt:1183.1] || -> xuntil6(s20)*. % 75.92/76.14 1186[32:MRR:156.0,1185.0] || -> until5(s21)*. % 75.92/76.14 1187[32:MRR:944.0,1186.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.14 1192[33:Spt:1187.2] || -> xuntil6(s21)*. % 75.92/76.14 1193[33:MRR:155.0,1192.0] || -> until5(s22)*. % 75.92/76.14 1194[33:MRR:943.0,1193.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.14 1195[34:Spt:1194.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.14 1197[34:Res:1195.0,61.1] always3(s23) || -> . % 75.92/76.14 1198[34:SSi:1197.0,712.0] || -> . % 75.92/76.14 1199[34:Spt:1198.0,1194.1,1195.0] || m_main_v_state(s23,c_busy)*+ -> . % 75.92/76.14 1200[34:Spt:1198.0,1194.0,1194.2] || m_main_v_state(s22,c_ready)*+ -> xuntil6(s22). % 75.92/76.14 1203[34:Res:53.1,1200.0] || -> m_main_v_state(s22,c_busy)* xuntil6(s22). % 75.92/76.14 1205[35:Spt:1203.1] || -> xuntil6(s22)*. % 75.92/76.14 1206[35:MRR:154.0,1205.0] || -> until5(s23)*. % 75.92/76.14 1207[35:MRR:942.0,1206.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.14 1215[36:Spt:1207.2] || -> xuntil6(s23)*. % 75.92/76.14 1216[36:MRR:153.0,1215.0] || -> until5(s24)*. % 75.92/76.14 1217[36:MRR:941.0,1216.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.14 1218[37:Spt:1217.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.14 1220[37:Res:1218.0,61.1] always3(s25) || -> . % 75.92/76.14 1221[37:SSi:1220.0,714.0] || -> . % 75.92/76.14 1222[37:Spt:1221.0,1217.1,1218.0] || m_main_v_state(s25,c_busy)*+ -> . % 75.92/76.14 1223[37:Spt:1221.0,1217.0,1217.2] || m_main_v_state(s24,c_ready)*+ -> xuntil6(s24). % 75.92/76.14 1226[37:Res:53.1,1223.0] || -> m_main_v_state(s24,c_busy)* xuntil6(s24). % 75.92/76.14 1231[38:Spt:1226.1] || -> xuntil6(s24)*. % 75.92/76.14 1232[38:MRR:152.0,1231.0] || -> until5(s25)*. % 75.92/76.14 1233[38:MRR:940.0,1232.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.14 1235[39:Spt:1233.2] || -> xuntil6(s25)*. % 75.92/76.14 1236[39:MRR:151.0,1235.0] || -> until5(s26)*. % 75.92/76.14 1237[39:MRR:939.0,1236.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.14 1238[40:Spt:1237.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.14 1240[40:Res:1238.0,61.1] always3(s27) || -> . % 75.92/76.14 1241[40:SSi:1240.0,716.0] || -> . % 75.92/76.14 1242[40:Spt:1241.0,1237.1,1238.0] || m_main_v_state(s27,c_busy)*+ -> . % 75.92/76.14 1243[40:Spt:1241.0,1237.0,1237.2] || m_main_v_state(s26,c_ready)*+ -> xuntil6(s26). % 75.92/76.14 1246[40:Res:53.1,1243.0] || -> m_main_v_state(s26,c_busy)* xuntil6(s26). % 75.92/76.14 1248[41:Spt:1246.1] || -> xuntil6(s26)*. % 75.92/76.14 1249[41:MRR:150.0,1248.0] || -> until5(s27)*. % 75.92/76.14 1250[41:MRR:938.0,1249.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.14 1255[42:Spt:1250.2] || -> xuntil6(s27)*. % 75.92/76.14 1256[42:MRR:149.0,1255.0] || -> until5(s28)*. % 75.92/76.14 1257[42:MRR:937.0,1256.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.14 1258[43:Spt:1257.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.14 1260[43:Res:1258.0,61.1] always3(s29) || -> . % 75.92/76.14 1261[43:SSi:1260.0,718.0] || -> . % 75.92/76.14 1262[43:Spt:1261.0,1257.1,1258.0] || m_main_v_state(s29,c_busy)*+ -> . % 75.92/76.14 1263[43:Spt:1261.0,1257.0,1257.2] || m_main_v_state(s28,c_ready)*+ -> xuntil6(s28). % 75.92/76.14 1266[43:Res:53.1,1263.0] || -> m_main_v_state(s28,c_busy)* xuntil6(s28). % 75.92/76.14 1268[44:Spt:1266.1] || -> xuntil6(s28)*. % 75.92/76.14 1269[44:MRR:148.0,1268.0] || -> until5(s29)*. % 75.92/76.14 1270[44:MRR:936.0,1269.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.14 1278[45:Spt:1270.2] || -> xuntil6(s29)*. % 75.92/76.14 1279[45:MRR:147.0,1278.0] || -> until5(s30)*. % 75.92/76.14 1280[45:MRR:935.0,1279.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.14 1281[46:Spt:1280.1] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.14 1283[46:Res:1281.0,61.1] always3(s31) || -> . % 75.92/76.14 1284[46:SSi:1283.0,720.0] || -> . % 75.92/76.14 1285[46:Spt:1284.0,1280.1,1281.0] || m_main_v_state(s31,c_busy)*+ -> . % 75.92/76.14 1286[46:Spt:1284.0,1280.0,1280.2] || m_main_v_state(s30,c_ready)*+ -> xuntil6(s30). % 75.92/76.14 1289[46:Res:53.1,1286.0] || -> m_main_v_state(s30,c_busy)* xuntil6(s30). % 75.92/76.14 1294[47:Spt:1289.1] || -> xuntil6(s30)*. % 75.92/76.14 1295[47:MRR:146.0,1294.0] || -> until5(s31)*. % 75.92/76.14 1296[47:MRR:934.0,1295.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.14 1298[48:Spt:1296.2] || -> xuntil6(s31)*. % 75.92/76.14 1299[48:MRR:145.0,1298.0] || -> until5(s32)*. % 75.92/76.14 1300[48:MRR:933.0,1299.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.14 1301[49:Spt:1300.1] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.14 1303[49:Res:1301.0,61.1] always3(s33) || -> . % 75.92/76.14 1304[49:SSi:1303.0,722.0] || -> . % 75.92/76.14 1305[49:Spt:1304.0,1300.1,1301.0] || m_main_v_state(s33,c_busy)*+ -> . % 75.92/76.14 1306[49:Spt:1304.0,1300.0,1300.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 75.92/76.14 1309[49:Res:53.1,1306.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 75.92/76.14 1311[50:Spt:1309.1] || -> xuntil6(s32)*. % 75.92/76.14 1312[50:MRR:144.0,1311.0] || -> until5(s33)*. % 75.92/76.14 1313[50:MRR:932.0,1312.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.14 1318[51:Spt:1313.2] || -> xuntil6(s33)*. % 75.92/76.14 1319[51:MRR:143.0,1318.0] || -> until5(s34)*. % 75.92/76.14 1320[51:MRR:931.0,1319.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.14 1321[52:Spt:1320.1] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.14 1323[52:Res:1321.0,61.1] always3(s35) || -> . % 75.92/76.14 1324[52:SSi:1323.0,724.0] || -> . % 75.92/76.14 1325[52:Spt:1324.0,1320.1,1321.0] || m_main_v_state(s35,c_busy)*+ -> . % 75.92/76.14 1326[52:Spt:1324.0,1320.0,1320.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 75.92/76.14 1329[52:Res:53.1,1326.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 75.92/76.14 1331[53:Spt:1329.1] || -> xuntil6(s34)*. % 75.92/76.14 1332[53:MRR:142.0,1331.0] || -> until5(s35)*. % 75.92/76.14 1333[53:MRR:930.0,1332.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.14 1341[54:Spt:1333.2] || -> xuntil6(s35)*. % 75.92/76.14 1342[54:MRR:141.0,1341.0] || -> until5(s36)*. % 75.92/76.14 1343[54:MRR:929.0,1342.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.14 1344[55:Spt:1343.1] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.14 1346[55:Res:1344.0,61.1] always3(s37) || -> . % 75.92/76.14 1347[55:SSi:1346.0,726.0] || -> . % 75.92/76.14 1348[55:Spt:1347.0,1343.1,1344.0] || m_main_v_state(s37,c_busy)*+ -> . % 75.92/76.14 1349[55:Spt:1347.0,1343.0,1343.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 75.92/76.14 1352[55:Res:53.1,1349.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 75.92/76.14 1357[56:Spt:1352.1] || -> xuntil6(s36)*. % 75.92/76.14 1358[56:MRR:140.0,1357.0] || -> until5(s37)*. % 75.92/76.14 1359[56:MRR:928.0,1358.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.14 1361[57:Spt:1359.2] || -> xuntil6(s37)*. % 75.92/76.14 1362[57:MRR:139.0,1361.0] || -> until5(s38)*. % 75.92/76.14 1363[57:MRR:927.0,1362.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.14 1364[58:Spt:1363.1] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.14 1366[58:Res:1364.0,61.1] always3(s39) || -> . % 75.92/76.14 1367[58:SSi:1366.0,728.0] || -> . % 75.92/76.14 1368[58:Spt:1367.0,1363.1,1364.0] || m_main_v_state(s39,c_busy)*+ -> . % 75.92/76.14 1369[58:Spt:1367.0,1363.0,1363.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 75.92/76.14 1372[58:Res:53.1,1369.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 75.92/76.14 1374[59:Spt:1372.1] || -> xuntil6(s38)*. % 75.92/76.14 1375[59:MRR:138.0,1374.0] || -> until5(s39)*. % 75.92/76.14 1376[59:MRR:926.0,1375.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.14 1381[60:Spt:1376.2] || -> xuntil6(s39)*. % 75.92/76.14 1382[60:MRR:137.0,1381.0] || -> until5(s40)*. % 75.92/76.14 1383[60:MRR:925.0,1382.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.14 1384[61:Spt:1383.1] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.14 1386[61:Res:1384.0,61.1] always3(s41) || -> . % 75.92/76.14 1387[61:SSi:1386.0,730.0] || -> . % 75.92/76.14 1388[61:Spt:1387.0,1383.1,1384.0] || m_main_v_state(s41,c_busy)*+ -> . % 75.92/76.14 1389[61:Spt:1387.0,1383.0,1383.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 75.92/76.14 1392[61:Res:53.1,1389.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 75.92/76.14 1394[62:Spt:1392.1] || -> xuntil6(s40)*. % 75.92/76.14 1395[62:MRR:136.0,1394.0] || -> until5(s41)*. % 75.92/76.14 1396[62:MRR:924.0,1395.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.14 1404[63:Spt:1396.2] || -> xuntil6(s41)*. % 75.92/76.14 1405[63:MRR:135.0,1404.0] || -> until5(s42)*. % 75.92/76.14 1406[63:MRR:923.0,1405.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.14 1407[64:Spt:1406.1] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.14 1409[64:Res:1407.0,61.1] always3(s43) || -> . % 75.92/76.14 1410[64:SSi:1409.0,732.0] || -> . % 75.92/76.14 1411[64:Spt:1410.0,1406.1,1407.0] || m_main_v_state(s43,c_busy)*+ -> . % 75.92/76.14 1412[64:Spt:1410.0,1406.0,1406.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 75.92/76.14 1415[64:Res:53.1,1412.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 75.92/76.14 1420[65:Spt:1415.1] || -> xuntil6(s42)*. % 75.92/76.14 1421[65:MRR:134.0,1420.0] || -> until5(s43)*. % 75.92/76.14 1422[65:MRR:922.0,1421.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.14 1424[66:Spt:1422.2] || -> xuntil6(s43)*. % 75.92/76.14 1425[66:MRR:133.0,1424.0] || -> until5(s44)*. % 75.92/76.14 1426[66:MRR:921.0,1425.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.14 1427[67:Spt:1426.1] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.14 1429[67:Res:1427.0,61.1] always3(s45) || -> . % 75.92/76.14 1430[67:SSi:1429.0,734.0] || -> . % 75.92/76.14 1431[67:Spt:1430.0,1426.1,1427.0] || m_main_v_state(s45,c_busy)*+ -> . % 75.92/76.14 1432[67:Spt:1430.0,1426.0,1426.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 75.92/76.14 1435[67:Res:53.1,1432.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 75.92/76.14 1437[68:Spt:1435.1] || -> xuntil6(s44)*. % 75.92/76.14 1438[68:MRR:132.0,1437.0] || -> until5(s45)*. % 75.92/76.14 1439[68:MRR:920.0,1438.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.14 1444[69:Spt:1439.2] || -> xuntil6(s45)*. % 75.92/76.14 1445[69:MRR:131.0,1444.0] || -> until5(s46)*. % 75.92/76.14 1446[69:MRR:919.0,1445.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.14 1447[70:Spt:1446.1] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.14 1449[70:Res:1447.0,61.1] always3(s47) || -> . % 75.92/76.14 1450[70:SSi:1449.0,736.0] || -> . % 75.92/76.14 1451[70:Spt:1450.0,1446.1,1447.0] || m_main_v_state(s47,c_busy)*+ -> . % 75.92/76.14 1452[70:Spt:1450.0,1446.0,1446.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 75.92/76.14 1455[70:Res:53.1,1452.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 75.92/76.14 1457[71:Spt:1455.1] || -> xuntil6(s46)*. % 75.92/76.14 1458[71:MRR:130.0,1457.0] || -> until5(s47)*. % 75.92/76.14 1459[71:MRR:918.0,1458.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.14 1467[72:Spt:1459.2] || -> xuntil6(s47)*. % 75.92/76.14 1468[72:MRR:129.0,1467.0] || -> until5(s48)*. % 75.92/76.14 1469[72:MRR:917.0,1468.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.14 1470[73:Spt:1469.1] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 1472[73:Res:1470.0,61.1] always3(s49) || -> . % 75.92/76.14 1473[73:SSi:1472.0,50.0,738.0] || -> . % 75.92/76.14 1474[73:Spt:1473.0,1469.1,1470.0] || m_main_v_state(s49,c_busy)*+ -> . % 75.92/76.14 1475[73:Spt:1473.0,1469.0,1469.2] || m_main_v_state(s48,c_ready)* -> xuntil6(s48). % 75.92/76.14 1477[73:MRR:756.1,1474.0] node4(s49) || -> . % 75.92/76.14 1478[73:MRR:194.1,1477.0] until2p7(s49) || -> . % 75.92/76.14 1480[73:MRR:750.1,1478.0] xuntil6(s49) || -> . % 75.92/76.14 1482[73:MRR:772.1,772.2,1474.0,1480.0] until5(s49) || -> . % 75.92/76.14 1483[73:MRR:128.1,1482.0] xuntil6(s48) || -> . % 75.92/76.14 1484[73:MRR:1475.1,1483.0] || m_main_v_state(s48,c_ready)*+ -> . % 75.92/76.14 1489[73:Res:53.1,1484.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.14 1492[73:Res:1489.0,61.1] always3(s48) || -> . % 75.92/76.14 1493[73:SSi:1492.0,737.0,1468.0] || -> . % 75.92/76.14 1494[72:Spt:1493.0,1459.2,1467.0] || xuntil6(s47)*+ -> . % 75.92/76.14 1495[72:Spt:1493.0,1459.0,1459.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 75.92/76.14 1496[72:Res:53.1,1495.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 75.92/76.14 1498[72:MRR:1496.0,1451.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.14 1500[72:Res:1498.0,61.1] always3(s48) || -> . % 75.92/76.14 1501[72:SSi:1500.0,737.0] || -> . % 75.92/76.14 1502[71:Spt:1501.0,1455.1,1457.0] || xuntil6(s46)* -> . % 75.92/76.14 1503[71:Spt:1501.0,1455.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.14 1506[71:Res:1503.0,61.1] always3(s46) || -> . % 75.92/76.14 1507[71:SSi:1506.0,735.0,1445.0] || -> . % 75.92/76.14 1508[69:Spt:1507.0,1439.2,1444.0] || xuntil6(s45)*+ -> . % 75.92/76.14 1509[69:Spt:1507.0,1439.0,1439.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 75.92/76.14 1510[69:Res:53.1,1509.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 75.92/76.14 1512[69:MRR:1510.0,1431.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.14 1514[69:Res:1512.0,61.1] always3(s46) || -> . % 75.92/76.14 1515[69:SSi:1514.0,735.0] || -> . % 75.92/76.14 1516[68:Spt:1515.0,1435.1,1437.0] || xuntil6(s44)* -> . % 75.92/76.14 1517[68:Spt:1515.0,1435.0] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.14 1520[68:Res:1517.0,61.1] always3(s44) || -> . % 75.92/76.14 1521[68:SSi:1520.0,733.0,1425.0] || -> . % 75.92/76.14 1522[66:Spt:1521.0,1422.2,1424.0] || xuntil6(s43)*+ -> . % 75.92/76.14 1523[66:Spt:1521.0,1422.0,1422.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 75.92/76.14 1524[66:Res:53.1,1523.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 75.92/76.14 1526[66:MRR:1524.0,1411.0] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.14 1529[66:Res:1526.0,61.1] always3(s44) || -> . % 75.92/76.14 1530[66:SSi:1529.0,733.0] || -> . % 75.92/76.14 1531[65:Spt:1530.0,1415.1,1420.0] || xuntil6(s42)* -> . % 75.92/76.14 1532[65:Spt:1530.0,1415.0] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.14 1535[65:Res:1532.0,61.1] always3(s42) || -> . % 75.92/76.14 1536[65:SSi:1535.0,731.0,1405.0] || -> . % 75.92/76.14 1537[63:Spt:1536.0,1396.2,1404.0] || xuntil6(s41)*+ -> . % 75.92/76.14 1538[63:Spt:1536.0,1396.0,1396.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 75.92/76.14 1539[63:Res:53.1,1538.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 75.92/76.14 1541[63:MRR:1539.0,1388.0] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.14 1543[63:Res:1541.0,61.1] always3(s42) || -> . % 75.92/76.14 1544[63:SSi:1543.0,731.0] || -> . % 75.92/76.14 1545[62:Spt:1544.0,1392.1,1394.0] || xuntil6(s40)* -> . % 75.92/76.14 1546[62:Spt:1544.0,1392.0] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.14 1549[62:Res:1546.0,61.1] always3(s40) || -> . % 75.92/76.14 1550[62:SSi:1549.0,729.0,1382.0] || -> . % 75.92/76.14 1551[60:Spt:1550.0,1376.2,1381.0] || xuntil6(s39)*+ -> . % 75.92/76.14 1552[60:Spt:1550.0,1376.0,1376.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 75.92/76.14 1553[60:Res:53.1,1552.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 75.92/76.14 1555[60:MRR:1553.0,1368.0] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.14 1557[60:Res:1555.0,61.1] always3(s40) || -> . % 75.92/76.14 1558[60:SSi:1557.0,729.0] || -> . % 75.92/76.14 1559[59:Spt:1558.0,1372.1,1374.0] || xuntil6(s38)* -> . % 75.92/76.14 1560[59:Spt:1558.0,1372.0] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.14 1563[59:Res:1560.0,61.1] always3(s38) || -> . % 75.92/76.14 1564[59:SSi:1563.0,727.0,1362.0] || -> . % 75.92/76.14 1565[57:Spt:1564.0,1359.2,1361.0] || xuntil6(s37)*+ -> . % 75.92/76.14 1566[57:Spt:1564.0,1359.0,1359.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 75.92/76.14 1567[57:Res:53.1,1566.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 75.92/76.14 1569[57:MRR:1567.0,1348.0] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.14 1571[57:Res:1569.0,61.1] always3(s38) || -> . % 75.92/76.14 1572[57:SSi:1571.0,727.0] || -> . % 75.92/76.14 1573[56:Spt:1572.0,1352.1,1357.0] || xuntil6(s36)* -> . % 75.92/76.14 1574[56:Spt:1572.0,1352.0] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.14 1577[56:Res:1574.0,61.1] always3(s36) || -> . % 75.92/76.14 1578[56:SSi:1577.0,725.0,1342.0] || -> . % 75.92/76.14 1579[54:Spt:1578.0,1333.2,1341.0] || xuntil6(s35)*+ -> . % 75.92/76.14 1580[54:Spt:1578.0,1333.0,1333.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 75.92/76.14 1581[54:Res:53.1,1580.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 75.92/76.14 1583[54:MRR:1581.0,1325.0] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.14 1585[54:Res:1583.0,61.1] always3(s36) || -> . % 75.92/76.14 1586[54:SSi:1585.0,725.0] || -> . % 75.92/76.14 1587[53:Spt:1586.0,1329.1,1331.0] || xuntil6(s34)* -> . % 75.92/76.14 1588[53:Spt:1586.0,1329.0] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.14 1591[53:Res:1588.0,61.1] always3(s34) || -> . % 75.92/76.14 1592[53:SSi:1591.0,723.0,1319.0] || -> . % 75.92/76.14 1593[51:Spt:1592.0,1313.2,1318.0] || xuntil6(s33)*+ -> . % 75.92/76.14 1594[51:Spt:1592.0,1313.0,1313.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 75.92/76.14 1595[51:Res:53.1,1594.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 75.92/76.14 1597[51:MRR:1595.0,1305.0] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.14 1599[51:Res:1597.0,61.1] always3(s34) || -> . % 75.92/76.14 1600[51:SSi:1599.0,723.0] || -> . % 75.92/76.14 1601[50:Spt:1600.0,1309.1,1311.0] || xuntil6(s32)* -> . % 75.92/76.14 1602[50:Spt:1600.0,1309.0] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.14 1605[50:Res:1602.0,61.1] always3(s32) || -> . % 75.92/76.14 1606[50:SSi:1605.0,721.0,1299.0] || -> . % 75.92/76.14 1607[48:Spt:1606.0,1296.2,1298.0] || xuntil6(s31)*+ -> . % 75.92/76.14 1608[48:Spt:1606.0,1296.0,1296.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 75.92/76.14 1609[48:Res:53.1,1608.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 75.92/76.14 1611[48:MRR:1609.0,1285.0] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.14 1613[48:Res:1611.0,61.1] always3(s32) || -> . % 75.92/76.14 1614[48:SSi:1613.0,721.0] || -> . % 75.92/76.14 1615[47:Spt:1614.0,1289.1,1294.0] || xuntil6(s30)* -> . % 75.92/76.14 1616[47:Spt:1614.0,1289.0] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.14 1619[47:Res:1616.0,61.1] always3(s30) || -> . % 75.92/76.14 1620[47:SSi:1619.0,719.0,1279.0] || -> . % 75.92/76.14 1621[45:Spt:1620.0,1270.2,1278.0] || xuntil6(s29)*+ -> . % 75.92/76.14 1622[45:Spt:1620.0,1270.0,1270.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 75.92/76.14 1623[45:Res:53.1,1622.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 75.92/76.14 1625[45:MRR:1623.0,1262.0] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.14 1627[45:Res:1625.0,61.1] always3(s30) || -> . % 75.92/76.14 1628[45:SSi:1627.0,719.0] || -> . % 75.92/76.14 1629[44:Spt:1628.0,1266.1,1268.0] || xuntil6(s28)* -> . % 75.92/76.14 1630[44:Spt:1628.0,1266.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.14 1633[44:Res:1630.0,61.1] always3(s28) || -> . % 75.92/76.14 1634[44:SSi:1633.0,717.0,1256.0] || -> . % 75.92/76.14 1635[42:Spt:1634.0,1250.2,1255.0] || xuntil6(s27)*+ -> . % 75.92/76.14 1636[42:Spt:1634.0,1250.0,1250.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.14 1637[42:Res:53.1,1636.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.14 1639[42:MRR:1637.0,1242.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.14 1641[42:Res:1639.0,61.1] always3(s28) || -> . % 75.92/76.14 1642[42:SSi:1641.0,717.0] || -> . % 75.92/76.14 1643[41:Spt:1642.0,1246.1,1248.0] || xuntil6(s26)* -> . % 75.92/76.14 1644[41:Spt:1642.0,1246.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.14 1647[41:Res:1644.0,61.1] always3(s26) || -> . % 75.92/76.14 1648[41:SSi:1647.0,715.0,1236.0] || -> . % 75.92/76.14 1649[39:Spt:1648.0,1233.2,1235.0] || xuntil6(s25)*+ -> . % 75.92/76.14 1650[39:Spt:1648.0,1233.0,1233.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.14 1651[39:Res:53.1,1650.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.14 1653[39:MRR:1651.0,1222.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.14 1655[39:Res:1653.0,61.1] always3(s26) || -> . % 75.92/76.14 1656[39:SSi:1655.0,715.0] || -> . % 75.92/76.14 1657[38:Spt:1656.0,1226.1,1231.0] || xuntil6(s24)* -> . % 75.92/76.14 1658[38:Spt:1656.0,1226.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.14 1661[38:Res:1658.0,61.1] always3(s24) || -> . % 75.92/76.14 1662[38:SSi:1661.0,713.0,1216.0] || -> . % 75.92/76.14 1663[36:Spt:1662.0,1207.2,1215.0] || xuntil6(s23)*+ -> . % 75.92/76.14 1664[36:Spt:1662.0,1207.0,1207.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.14 1665[36:Res:53.1,1664.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.14 1667[36:MRR:1665.0,1199.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.14 1669[36:Res:1667.0,61.1] always3(s24) || -> . % 75.92/76.14 1670[36:SSi:1669.0,713.0] || -> . % 75.92/76.14 1671[35:Spt:1670.0,1203.1,1205.0] || xuntil6(s22)* -> . % 75.92/76.14 1672[35:Spt:1670.0,1203.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.14 1675[35:Res:1672.0,61.1] always3(s22) || -> . % 75.92/76.14 1676[35:SSi:1675.0,711.0,1193.0] || -> . % 75.92/76.14 1677[33:Spt:1676.0,1187.2,1192.0] || xuntil6(s21)*+ -> . % 75.92/76.14 1678[33:Spt:1676.0,1187.0,1187.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.14 1679[33:Res:53.1,1678.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.14 1681[33:MRR:1679.0,1179.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.14 1683[33:Res:1681.0,61.1] always3(s22) || -> . % 75.92/76.14 1684[33:SSi:1683.0,711.0] || -> . % 75.92/76.14 1685[32:Spt:1684.0,1183.1,1185.0] || xuntil6(s20)* -> . % 75.92/76.14 1686[32:Spt:1684.0,1183.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.14 1689[32:Res:1686.0,61.1] always3(s20) || -> . % 75.92/76.14 1690[32:SSi:1689.0,709.0,1173.0] || -> . % 75.92/76.14 1691[30:Spt:1690.0,1170.2,1172.0] || xuntil6(s19)*+ -> . % 75.92/76.14 1692[30:Spt:1690.0,1170.0,1170.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.14 1693[30:Res:53.1,1692.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.14 1695[30:MRR:1693.0,1159.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.14 1697[30:Res:1695.0,61.1] always3(s20) || -> . % 75.92/76.14 1698[30:SSi:1697.0,709.0] || -> . % 75.92/76.14 1699[29:Spt:1698.0,1163.1,1168.0] || xuntil6(s18)* -> . % 75.92/76.14 1700[29:Spt:1698.0,1163.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.14 1703[29:Res:1700.0,61.1] always3(s18) || -> . % 75.92/76.14 1704[29:SSi:1703.0,707.0,1153.0] || -> . % 75.92/76.14 1705[27:Spt:1704.0,1144.2,1152.0] || xuntil6(s17)*+ -> . % 75.92/76.14 1706[27:Spt:1704.0,1144.0,1144.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.14 1707[27:Res:53.1,1706.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.14 1709[27:MRR:1707.0,1136.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.14 1711[27:Res:1709.0,61.1] always3(s18) || -> . % 75.92/76.14 1712[27:SSi:1711.0,707.0] || -> . % 75.92/76.14 1713[26:Spt:1712.0,1140.1,1142.0] || xuntil6(s16)* -> . % 75.92/76.14 1714[26:Spt:1712.0,1140.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.14 1717[26:Res:1714.0,61.1] always3(s16) || -> . % 75.92/76.14 1718[26:SSi:1717.0,705.0,1130.0] || -> . % 75.92/76.14 1719[24:Spt:1718.0,1124.2,1129.0] || xuntil6(s15)*+ -> . % 75.92/76.14 1720[24:Spt:1718.0,1124.0,1124.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.14 1721[24:Res:53.1,1720.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.14 1723[24:MRR:1721.0,1116.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.14 1725[24:Res:1723.0,61.1] always3(s16) || -> . % 75.92/76.14 1726[24:SSi:1725.0,705.0] || -> . % 75.92/76.14 1727[23:Spt:1726.0,1120.1,1122.0] || xuntil6(s14)* -> . % 75.92/76.14 1728[23:Spt:1726.0,1120.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.14 1731[23:Res:1728.0,61.1] always3(s14) || -> . % 75.92/76.14 1732[23:SSi:1731.0,703.0,1110.0] || -> . % 75.92/76.14 1733[21:Spt:1732.0,1107.2,1109.0] || xuntil6(s13)*+ -> . % 75.92/76.14 1734[21:Spt:1732.0,1107.0,1107.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.14 1735[21:Res:53.1,1734.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.14 1737[21:MRR:1735.0,1096.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.14 1739[21:Res:1737.0,61.1] always3(s14) || -> . % 75.92/76.14 1740[21:SSi:1739.0,703.0] || -> . % 75.92/76.14 1741[20:Spt:1740.0,1100.1,1105.0] || xuntil6(s12)* -> . % 75.92/76.14 1742[20:Spt:1740.0,1100.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.14 1745[20:Res:1742.0,61.1] always3(s12) || -> . % 75.92/76.14 1746[20:SSi:1745.0,701.0,1090.0] || -> . % 75.92/76.14 1747[18:Spt:1746.0,1081.2,1089.0] || xuntil6(s11)*+ -> . % 75.92/76.14 1748[18:Spt:1746.0,1081.0,1081.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.14 1749[18:Res:53.1,1748.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.14 1751[18:MRR:1749.0,1073.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.14 1753[18:Res:1751.0,61.1] always3(s12) || -> . % 75.92/76.14 1754[18:SSi:1753.0,701.0] || -> . % 75.92/76.14 1755[17:Spt:1754.0,1077.1,1079.0] || xuntil6(s10)* -> . % 75.92/76.14 1756[17:Spt:1754.0,1077.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.14 1759[17:Res:1756.0,61.1] always3(s10) || -> . % 75.92/76.14 1760[17:SSi:1759.0,699.0,1067.0] || -> . % 75.92/76.14 1761[15:Spt:1760.0,1061.2,1066.0] || xuntil6(s9)*+ -> . % 75.92/76.14 1762[15:Spt:1760.0,1061.0,1061.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.14 1763[15:Res:53.1,1762.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.14 1765[15:MRR:1763.0,1053.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.14 1767[15:Res:1765.0,61.1] always3(s10) || -> . % 75.92/76.14 1768[15:SSi:1767.0,699.0] || -> . % 75.92/76.14 1769[14:Spt:1768.0,1057.1,1059.0] || xuntil6(s8)* -> . % 75.92/76.14 1770[14:Spt:1768.0,1057.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.14 1773[14:Res:1770.0,61.1] always3(s8) || -> . % 75.92/76.14 1774[14:SSi:1773.0,697.0,1047.0] || -> . % 75.92/76.14 1775[12:Spt:1774.0,1044.2,1046.0] || xuntil6(s7)*+ -> . % 75.92/76.14 1776[12:Spt:1774.0,1044.0,1044.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.14 1777[12:Res:53.1,1776.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.14 1779[12:MRR:1777.0,1033.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.14 1781[12:Res:1779.0,61.1] always3(s8) || -> . % 75.92/76.14 1782[12:SSi:1781.0,697.0] || -> . % 75.92/76.14 1783[11:Spt:1782.0,1037.1,1042.0] || xuntil6(s6)* -> . % 75.92/76.14 1784[11:Spt:1782.0,1037.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.14 1787[11:Res:1784.0,61.1] always3(s6) || -> . % 75.92/76.14 1788[11:SSi:1787.0,695.0,1027.0] || -> . % 75.92/76.14 1789[9:Spt:1788.0,1018.2,1026.0] || xuntil6(s5)*+ -> . % 75.92/76.14 1790[9:Spt:1788.0,1018.0,1018.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.14 1791[9:Res:53.1,1790.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.14 1793[9:MRR:1791.0,1010.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.14 1795[9:Res:1793.0,61.1] always3(s6) || -> . % 75.92/76.14 1796[9:SSi:1795.0,695.0] || -> . % 75.92/76.14 1797[8:Spt:1796.0,1014.1,1016.0] || xuntil6(s4)* -> . % 75.92/76.14 1798[8:Spt:1796.0,1014.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.14 1801[8:Res:1798.0,61.1] always3(s4) || -> . % 75.92/76.14 1802[8:SSi:1801.0,693.0,1004.0] || -> . % 75.92/76.14 1803[6:Spt:1802.0,998.2,1003.0] || xuntil6(s3)*+ -> . % 75.92/76.14 1804[6:Spt:1802.0,998.0,998.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.14 1805[6:Res:53.1,1804.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.14 1807[6:MRR:1805.0,990.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.14 1809[6:Res:1807.0,61.1] always3(s4) || -> . % 75.92/76.14 1810[6:SSi:1809.0,693.0] || -> . % 75.92/76.14 1811[2:Spt:1810.0,744.0,746.0] || trans(s49,s49)*+ -> . % 75.92/76.14 1812[2:Spt:1810.0,744.1,744.2,744.3,744.4,744.5,744.6,744.7,744.8,744.9,744.10,744.11,744.12,744.13,744.14,744.15,744.16,744.17,744.18,744.19,744.20,744.21,744.22,744.23,744.24,744.25,744.26,744.27,744.28,744.29,744.30,744.31,744.32,744.33,744.34,744.35,744.36,744.37,744.38,744.39,744.40,744.41,744.42,744.43,744.44,744.45,744.46,744.47,744.48,744.49] || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.14 1813[2:MRR:743.0,1811.0] || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.14 1815[2:MRR:745.1,1811.0] xuntil6(s49) || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.14 1816[3:Spt:1812.0] || -> trans(s49,s48)*. % 75.92/76.14 1817[3:Res:1816.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s48)*. % 75.92/76.14 1819[3:Res:1816.0,60.0] || -> node2(s49,s48)*. % 75.92/76.14 1820[3:SSi:1817.1,50.0,738.0] xuntil6(s49) || -> until2p7(s48)*. % 75.92/76.14 1821[3:Res:1819.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)*. % 75.92/76.14 1822[4:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.14 1823[4:MRR:176.0,1822.0] || -> until5(s1)*. % 75.92/76.14 1824[4:MRR:964.0,1823.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.14 1828[5:Spt:1824.2] || -> xuntil6(s1)*. % 75.92/76.14 1829[5:MRR:175.0,1828.0] || -> until5(s2)*. % 75.92/76.14 1830[5:MRR:963.0,1829.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.14 1831[6:Spt:1830.2] || -> xuntil6(s2)*. % 75.92/76.14 1832[6:MRR:174.0,1831.0] || -> until5(s3)*. % 75.92/76.14 1833[6:MRR:962.0,1832.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.14 1834[7:Spt:1833.2] || -> xuntil6(s3)*. % 75.92/76.14 1835[7:MRR:173.0,1834.0] || -> until5(s4)*. % 75.92/76.14 1836[7:MRR:961.0,1835.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.14 1840[8:Spt:1836.2] || -> xuntil6(s4)*. % 75.92/76.14 1841[8:MRR:172.0,1840.0] || -> until5(s5)*. % 75.92/76.14 1842[8:MRR:960.0,1841.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.14 1843[9:Spt:1842.2] || -> xuntil6(s5)*. % 75.92/76.14 1844[9:MRR:171.0,1843.0] || -> until5(s6)*. % 75.92/76.14 1845[9:MRR:959.0,1844.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.14 1849[10:Spt:1845.2] || -> xuntil6(s6)*. % 75.92/76.14 1850[10:MRR:170.0,1849.0] || -> until5(s7)*. % 75.92/76.14 1851[10:MRR:958.0,1850.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.14 1852[11:Spt:1851.2] || -> xuntil6(s7)*. % 75.92/76.14 1853[11:MRR:169.0,1852.0] || -> until5(s8)*. % 75.92/76.14 1854[11:MRR:957.0,1853.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.14 1858[12:Spt:1854.2] || -> xuntil6(s8)*. % 75.92/76.14 1859[12:MRR:168.0,1858.0] || -> until5(s9)*. % 75.92/76.14 1860[12:MRR:956.0,1859.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.14 1861[13:Spt:1860.2] || -> xuntil6(s9)*. % 75.92/76.14 1862[13:MRR:167.0,1861.0] || -> until5(s10)*. % 75.92/76.14 1863[13:MRR:955.0,1862.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.14 1867[14:Spt:1863.2] || -> xuntil6(s10)*. % 75.92/76.14 1868[14:MRR:166.0,1867.0] || -> until5(s11)*. % 75.92/76.14 1869[14:MRR:954.0,1868.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.14 1870[15:Spt:1869.2] || -> xuntil6(s11)*. % 75.92/76.14 1871[15:MRR:165.0,1870.0] || -> until5(s12)*. % 75.92/76.14 1872[15:MRR:953.0,1871.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.14 1876[16:Spt:1872.2] || -> xuntil6(s12)*. % 75.92/76.14 1877[16:MRR:164.0,1876.0] || -> until5(s13)*. % 75.92/76.14 1878[16:MRR:952.0,1877.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.14 1879[17:Spt:1878.2] || -> xuntil6(s13)*. % 75.92/76.14 1880[17:MRR:163.0,1879.0] || -> until5(s14)*. % 75.92/76.14 1881[17:MRR:951.0,1880.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.14 1885[18:Spt:1881.2] || -> xuntil6(s14)*. % 75.92/76.14 1886[18:MRR:162.0,1885.0] || -> until5(s15)*. % 75.92/76.14 1887[18:MRR:950.0,1886.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.14 1888[19:Spt:1887.2] || -> xuntil6(s15)*. % 75.92/76.14 1889[19:MRR:161.0,1888.0] || -> until5(s16)*. % 75.92/76.14 1890[19:MRR:949.0,1889.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.14 1894[20:Spt:1890.2] || -> xuntil6(s16)*. % 75.92/76.14 1895[20:MRR:160.0,1894.0] || -> until5(s17)*. % 75.92/76.14 1896[20:MRR:948.0,1895.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.14 1897[21:Spt:1896.2] || -> xuntil6(s17)*. % 75.92/76.14 1898[21:MRR:159.0,1897.0] || -> until5(s18)*. % 75.92/76.14 1899[21:MRR:947.0,1898.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.14 1903[22:Spt:1899.2] || -> xuntil6(s18)*. % 75.92/76.14 1904[22:MRR:158.0,1903.0] || -> until5(s19)*. % 75.92/76.14 1905[22:MRR:946.0,1904.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.14 1906[23:Spt:1905.2] || -> xuntil6(s19)*. % 75.92/76.14 1907[23:MRR:157.0,1906.0] || -> until5(s20)*. % 75.92/76.14 1908[23:MRR:945.0,1907.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.14 1912[24:Spt:1908.2] || -> xuntil6(s20)*. % 75.92/76.14 1913[24:MRR:156.0,1912.0] || -> until5(s21)*. % 75.92/76.14 1914[24:MRR:944.0,1913.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.14 1915[25:Spt:1914.2] || -> xuntil6(s21)*. % 75.92/76.14 1916[25:MRR:155.0,1915.0] || -> until5(s22)*. % 75.92/76.14 1917[25:MRR:943.0,1916.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.14 1921[26:Spt:1917.2] || -> xuntil6(s22)*. % 75.92/76.14 1922[26:MRR:154.0,1921.0] || -> until5(s23)*. % 75.92/76.14 1923[26:MRR:942.0,1922.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.14 1924[27:Spt:1923.2] || -> xuntil6(s23)*. % 75.92/76.14 1925[27:MRR:153.0,1924.0] || -> until5(s24)*. % 75.92/76.14 1926[27:MRR:941.0,1925.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.14 1930[28:Spt:1926.2] || -> xuntil6(s24)*. % 75.92/76.14 1931[28:MRR:152.0,1930.0] || -> until5(s25)*. % 75.92/76.14 1932[28:MRR:940.0,1931.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.14 1933[29:Spt:1932.2] || -> xuntil6(s25)*. % 75.92/76.14 1934[29:MRR:151.0,1933.0] || -> until5(s26)*. % 75.92/76.14 1935[29:MRR:939.0,1934.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.14 1939[30:Spt:1935.2] || -> xuntil6(s26)*. % 75.92/76.14 1940[30:MRR:150.0,1939.0] || -> until5(s27)*. % 75.92/76.14 1941[30:MRR:938.0,1940.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.14 1942[31:Spt:1941.2] || -> xuntil6(s27)*. % 75.92/76.14 1943[31:MRR:149.0,1942.0] || -> until5(s28)*. % 75.92/76.14 1944[31:MRR:937.0,1943.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.14 1948[32:Spt:1944.2] || -> xuntil6(s28)*. % 75.92/76.14 1949[32:MRR:148.0,1948.0] || -> until5(s29)*. % 75.92/76.14 1950[32:MRR:936.0,1949.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.14 1951[33:Spt:1950.2] || -> xuntil6(s29)*. % 75.92/76.14 1952[33:MRR:147.0,1951.0] || -> until5(s30)*. % 75.92/76.14 1953[33:MRR:935.0,1952.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.14 1957[34:Spt:1953.2] || -> xuntil6(s30)*. % 75.92/76.14 1958[34:MRR:146.0,1957.0] || -> until5(s31)*. % 75.92/76.14 1959[34:MRR:934.0,1958.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.14 1960[35:Spt:1959.2] || -> xuntil6(s31)*. % 75.92/76.14 1961[35:MRR:145.0,1960.0] || -> until5(s32)*. % 75.92/76.14 1962[35:MRR:933.0,1961.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.14 1966[36:Spt:1962.2] || -> xuntil6(s32)*. % 75.92/76.14 1967[36:MRR:144.0,1966.0] || -> until5(s33)*. % 75.92/76.14 1968[36:MRR:932.0,1967.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.14 1969[37:Spt:1968.1] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.14 1971[37:Res:1969.0,61.1] always3(s34) || -> . % 75.92/76.14 1972[37:SSi:1971.0,723.0] || -> . % 75.92/76.14 1973[37:Spt:1972.0,1968.1,1969.0] || m_main_v_state(s34,c_busy)*+ -> . % 75.92/76.14 1974[37:Spt:1972.0,1968.0,1968.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 75.92/76.14 1977[37:Res:53.1,1974.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 75.92/76.14 1982[38:Spt:1977.1] || -> xuntil6(s33)*. % 75.92/76.14 1983[38:MRR:143.0,1982.0] || -> until5(s34)*. % 75.92/76.14 1984[38:MRR:931.0,1983.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.14 1986[39:Spt:1984.2] || -> xuntil6(s34)*. % 75.92/76.14 1987[39:MRR:142.0,1986.0] || -> until5(s35)*. % 75.92/76.14 1988[39:MRR:930.0,1987.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.14 1989[40:Spt:1988.1] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.14 1991[40:Res:1989.0,61.1] always3(s36) || -> . % 75.92/76.14 1992[40:SSi:1991.0,725.0] || -> . % 75.92/76.14 1993[40:Spt:1992.0,1988.1,1989.0] || m_main_v_state(s36,c_busy)*+ -> . % 75.92/76.14 1994[40:Spt:1992.0,1988.0,1988.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 75.92/76.14 1997[40:Res:53.1,1994.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 75.92/76.14 1999[41:Spt:1997.1] || -> xuntil6(s35)*. % 75.92/76.14 2000[41:MRR:141.0,1999.0] || -> until5(s36)*. % 75.92/76.14 2001[41:MRR:929.0,2000.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.14 2006[42:Spt:2001.2] || -> xuntil6(s36)*. % 75.92/76.14 2007[42:MRR:140.0,2006.0] || -> until5(s37)*. % 75.92/76.14 2008[42:MRR:928.0,2007.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.14 2009[43:Spt:2008.1] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.14 2011[43:Res:2009.0,61.1] always3(s38) || -> . % 75.92/76.14 2012[43:SSi:2011.0,727.0] || -> . % 75.92/76.14 2013[43:Spt:2012.0,2008.1,2009.0] || m_main_v_state(s38,c_busy)*+ -> . % 75.92/76.14 2014[43:Spt:2012.0,2008.0,2008.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 75.92/76.14 2017[43:Res:53.1,2014.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 75.92/76.14 2019[44:Spt:2017.1] || -> xuntil6(s37)*. % 75.92/76.14 2020[44:MRR:139.0,2019.0] || -> until5(s38)*. % 75.92/76.14 2021[44:MRR:927.0,2020.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.14 2029[45:Spt:2021.2] || -> xuntil6(s38)*. % 75.92/76.14 2030[45:MRR:138.0,2029.0] || -> until5(s39)*. % 75.92/76.14 2031[45:MRR:926.0,2030.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.14 2032[46:Spt:2031.1] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.14 2034[46:Res:2032.0,61.1] always3(s40) || -> . % 75.92/76.14 2035[46:SSi:2034.0,729.0] || -> . % 75.92/76.14 2036[46:Spt:2035.0,2031.1,2032.0] || m_main_v_state(s40,c_busy)*+ -> . % 75.92/76.14 2037[46:Spt:2035.0,2031.0,2031.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 75.92/76.14 2040[46:Res:53.1,2037.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 75.92/76.14 2045[47:Spt:2040.1] || -> xuntil6(s39)*. % 75.92/76.14 2046[47:MRR:137.0,2045.0] || -> until5(s40)*. % 75.92/76.14 2047[47:MRR:925.0,2046.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.14 2049[48:Spt:2047.2] || -> xuntil6(s40)*. % 75.92/76.14 2050[48:MRR:136.0,2049.0] || -> until5(s41)*. % 75.92/76.14 2051[48:MRR:924.0,2050.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.14 2052[49:Spt:2051.1] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.14 2054[49:Res:2052.0,61.1] always3(s42) || -> . % 75.92/76.14 2055[49:SSi:2054.0,731.0] || -> . % 75.92/76.14 2056[49:Spt:2055.0,2051.1,2052.0] || m_main_v_state(s42,c_busy)*+ -> . % 75.92/76.14 2057[49:Spt:2055.0,2051.0,2051.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 75.92/76.14 2060[49:Res:53.1,2057.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 75.92/76.14 2062[50:Spt:2060.1] || -> xuntil6(s41)*. % 75.92/76.14 2063[50:MRR:135.0,2062.0] || -> until5(s42)*. % 75.92/76.14 2064[50:MRR:923.0,2063.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.14 2069[51:Spt:2064.2] || -> xuntil6(s42)*. % 75.92/76.14 2070[51:MRR:134.0,2069.0] || -> until5(s43)*. % 75.92/76.14 2071[51:MRR:922.0,2070.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.14 2072[52:Spt:2071.1] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.14 2074[52:Res:2072.0,61.1] always3(s44) || -> . % 75.92/76.14 2075[52:SSi:2074.0,733.0] || -> . % 75.92/76.14 2076[52:Spt:2075.0,2071.1,2072.0] || m_main_v_state(s44,c_busy)*+ -> . % 75.92/76.14 2077[52:Spt:2075.0,2071.0,2071.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 75.92/76.14 2080[52:Res:53.1,2077.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 75.92/76.14 2082[53:Spt:2080.1] || -> xuntil6(s43)*. % 75.92/76.14 2083[53:MRR:133.0,2082.0] || -> until5(s44)*. % 75.92/76.14 2084[53:MRR:921.0,2083.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.14 2092[54:Spt:2084.2] || -> xuntil6(s44)*. % 75.92/76.14 2093[54:MRR:132.0,2092.0] || -> until5(s45)*. % 75.92/76.14 2094[54:MRR:920.0,2093.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.14 2095[55:Spt:2094.1] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.14 2097[55:Res:2095.0,61.1] always3(s46) || -> . % 75.92/76.14 2098[55:SSi:2097.0,735.0] || -> . % 75.92/76.14 2099[55:Spt:2098.0,2094.1,2095.0] || m_main_v_state(s46,c_busy)*+ -> . % 75.92/76.14 2100[55:Spt:2098.0,2094.0,2094.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 75.92/76.14 2103[55:Res:53.1,2100.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 75.92/76.14 2108[56:Spt:2103.1] || -> xuntil6(s45)*. % 75.92/76.14 2109[56:MRR:131.0,2108.0] || -> until5(s46)*. % 75.92/76.14 2110[56:MRR:919.0,2109.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.14 2112[57:Spt:2110.2] || -> xuntil6(s46)*. % 75.92/76.14 2113[57:MRR:130.0,2112.0] || -> until5(s47)*. % 75.92/76.14 2114[57:MRR:918.0,2113.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.14 2115[58:Spt:2114.1] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.14 2117[58:Res:2115.0,61.1] always3(s48) || -> . % 75.92/76.14 2118[58:SSi:2117.0,737.0] || -> . % 75.92/76.14 2119[58:Spt:2118.0,2114.1,2115.0] || m_main_v_state(s48,c_busy)*+ -> . % 75.92/76.14 2120[58:Spt:2118.0,2114.0,2114.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 75.92/76.14 2123[58:MRR:1821.2,2119.0] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.14 2124[58:Res:53.1,2120.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 75.92/76.14 2126[59:Spt:2124.1] || -> xuntil6(s47)*. % 75.92/76.14 2127[59:MRR:129.0,2126.0] || -> until5(s48)*. % 75.92/76.14 2128[59:MRR:917.0,2127.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.14 2134[58:SoR:2123.0,64.1] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.14 2136[58:SoR:2134.0,66.2] until5(s49) || m_main_v_state(s49,c_ready)* -> xuntil6(s49). % 75.92/76.14 2137[60:Spt:2128.2] || -> xuntil6(s48)*. % 75.92/76.14 2138[60:MRR:128.0,2137.0] || -> until5(s49)*. % 75.92/76.14 2139[60:MRR:2136.0,2138.0] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.14 2140[60:Res:53.1,2139.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.14 2142[61:Spt:2140.1] || -> xuntil6(s49)*. % 75.92/76.14 2143[61:MRR:1820.0,2142.0] || -> until2p7(s48)*. % 75.92/76.14 2144[61:MRR:559.0,2143.0] || -> until2p7(s49)* node4(s48). % 75.92/76.14 2145[62:Spt:2144.0] || -> until2p7(s49)*. % 75.92/76.14 2146[62:MRR:194.0,2145.0] || -> node4(s49)*. % 75.92/76.14 2147[62:MRR:2134.0,2146.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.14 2148[62:Res:53.1,2147.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 2151[62:Res:2148.0,61.1] always3(s49) || -> . % 75.92/76.14 2152[62:SSi:2151.0,50.0,738.0,2138.0,2142.0,2145.0,2146.0] || -> . % 75.92/76.14 2153[62:Spt:2152.0,2144.0,2145.0] || until2p7(s49)*+ -> . % 75.92/76.14 2154[62:Spt:2152.0,2144.1] || -> node4(s48)*. % 75.92/76.14 2156[62:MRR:774.0,2154.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.14 2162[62:Res:53.1,2156.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.14 2164[62:MRR:2162.0,2119.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 2166[62:Res:2164.0,61.1] always3(s49) || -> . % 75.92/76.14 2167[62:SSi:2166.0,50.0,738.0,2138.0,2142.0] || -> . % 75.92/76.14 2168[61:Spt:2167.0,2140.1,2142.0] || xuntil6(s49)* -> . % 75.92/76.14 2169[61:Spt:2167.0,2140.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 2172[61:Res:2169.0,61.1] always3(s49) || -> . % 75.92/76.14 2173[61:SSi:2172.0,50.0,738.0,2138.0] || -> . % 75.92/76.14 2174[60:Spt:2173.0,2128.2,2137.0] || xuntil6(s48)*+ -> . % 75.92/76.14 2175[60:Spt:2173.0,2128.0,2128.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.14 2176[60:Res:53.1,2175.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.14 2178[60:MRR:2176.0,2119.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 2180[60:Res:2178.0,61.1] always3(s49) || -> . % 75.92/76.14 2181[60:SSi:2180.0,50.0,738.0] || -> . % 75.92/76.14 2182[59:Spt:2181.0,2124.1,2126.0] || xuntil6(s47)* -> . % 75.92/76.14 2183[59:Spt:2181.0,2124.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.14 2186[59:Res:2183.0,61.1] always3(s47) || -> . % 75.92/76.14 2187[59:SSi:2186.0,736.0,2113.0] || -> . % 75.92/76.14 2188[57:Spt:2187.0,2110.2,2112.0] || xuntil6(s46)*+ -> . % 75.92/76.14 2189[57:Spt:2187.0,2110.0,2110.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.14 2190[57:Res:53.1,2189.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.14 2192[57:MRR:2190.0,2099.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.14 2194[57:Res:2192.0,61.1] always3(s47) || -> . % 75.92/76.14 2195[57:SSi:2194.0,736.0] || -> . % 75.92/76.14 2196[56:Spt:2195.0,2103.1,2108.0] || xuntil6(s45)* -> . % 75.92/76.14 2197[56:Spt:2195.0,2103.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.14 2200[56:Res:2197.0,61.1] always3(s45) || -> . % 75.92/76.14 2201[56:SSi:2200.0,734.0,2093.0] || -> . % 75.92/76.14 2202[54:Spt:2201.0,2084.2,2092.0] || xuntil6(s44)*+ -> . % 75.92/76.14 2203[54:Spt:2201.0,2084.0,2084.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.14 2204[54:Res:53.1,2203.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.14 2206[54:MRR:2204.0,2076.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.14 2209[54:Res:2206.0,61.1] always3(s45) || -> . % 75.92/76.14 2210[54:SSi:2209.0,734.0] || -> . % 75.92/76.14 2211[53:Spt:2210.0,2080.1,2082.0] || xuntil6(s43)* -> . % 75.92/76.14 2212[53:Spt:2210.0,2080.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.14 2215[53:Res:2212.0,61.1] always3(s43) || -> . % 75.92/76.14 2216[53:SSi:2215.0,732.0,2070.0] || -> . % 75.92/76.14 2217[51:Spt:2216.0,2064.2,2069.0] || xuntil6(s42)*+ -> . % 75.92/76.14 2218[51:Spt:2216.0,2064.0,2064.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.14 2219[51:Res:53.1,2218.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.14 2221[51:MRR:2219.0,2056.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.14 2223[51:Res:2221.0,61.1] always3(s43) || -> . % 75.92/76.14 2224[51:SSi:2223.0,732.0] || -> . % 75.92/76.14 2225[50:Spt:2224.0,2060.1,2062.0] || xuntil6(s41)* -> . % 75.92/76.14 2226[50:Spt:2224.0,2060.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.14 2229[50:Res:2226.0,61.1] always3(s41) || -> . % 75.92/76.14 2230[50:SSi:2229.0,730.0,2050.0] || -> . % 75.92/76.14 2231[48:Spt:2230.0,2047.2,2049.0] || xuntil6(s40)*+ -> . % 75.92/76.14 2232[48:Spt:2230.0,2047.0,2047.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.14 2233[48:Res:53.1,2232.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.14 2235[48:MRR:2233.0,2036.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.14 2238[48:Res:2235.0,61.1] always3(s41) || -> . % 75.92/76.14 2239[48:SSi:2238.0,730.0] || -> . % 75.92/76.14 2240[47:Spt:2239.0,2040.1,2045.0] || xuntil6(s39)* -> . % 75.92/76.14 2241[47:Spt:2239.0,2040.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.14 2244[47:Res:2241.0,61.1] always3(s39) || -> . % 75.92/76.14 2245[47:SSi:2244.0,728.0,2030.0] || -> . % 75.92/76.14 2246[45:Spt:2245.0,2021.2,2029.0] || xuntil6(s38)*+ -> . % 75.92/76.14 2247[45:Spt:2245.0,2021.0,2021.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.14 2248[45:Res:53.1,2247.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.14 2250[45:MRR:2248.0,2013.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.14 2252[45:Res:2250.0,61.1] always3(s39) || -> . % 75.92/76.14 2253[45:SSi:2252.0,728.0] || -> . % 75.92/76.14 2254[44:Spt:2253.0,2017.1,2019.0] || xuntil6(s37)* -> . % 75.92/76.14 2255[44:Spt:2253.0,2017.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.14 2258[44:Res:2255.0,61.1] always3(s37) || -> . % 75.92/76.14 2259[44:SSi:2258.0,726.0,2007.0] || -> . % 75.92/76.14 2260[42:Spt:2259.0,2001.2,2006.0] || xuntil6(s36)*+ -> . % 75.92/76.14 2261[42:Spt:2259.0,2001.0,2001.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.14 2262[42:Res:53.1,2261.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.14 2264[42:MRR:2262.0,1993.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.14 2266[42:Res:2264.0,61.1] always3(s37) || -> . % 75.92/76.14 2267[42:SSi:2266.0,726.0] || -> . % 75.92/76.14 2268[41:Spt:2267.0,1997.1,1999.0] || xuntil6(s35)* -> . % 75.92/76.14 2269[41:Spt:2267.0,1997.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.14 2272[41:Res:2269.0,61.1] always3(s35) || -> . % 75.92/76.14 2273[41:SSi:2272.0,724.0,1987.0] || -> . % 75.92/76.14 2274[39:Spt:2273.0,1984.2,1986.0] || xuntil6(s34)*+ -> . % 75.92/76.14 2275[39:Spt:2273.0,1984.0,1984.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 75.92/76.14 2276[39:Res:53.1,2275.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 75.92/76.14 2278[39:MRR:2276.0,1973.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.14 2280[39:Res:2278.0,61.1] always3(s35) || -> . % 75.92/76.14 2281[39:SSi:2280.0,724.0] || -> . % 75.92/76.14 2282[38:Spt:2281.0,1977.1,1982.0] || xuntil6(s33)* -> . % 75.92/76.14 2283[38:Spt:2281.0,1977.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.14 2286[38:Res:2283.0,61.1] always3(s33) || -> . % 75.92/76.14 2287[38:SSi:2286.0,722.0,1967.0] || -> . % 75.92/76.14 2288[36:Spt:2287.0,1962.2,1966.0] || xuntil6(s32)*+ -> . % 75.92/76.14 2289[36:Spt:2287.0,1962.0,1962.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 75.92/76.14 2290[36:Res:53.1,2289.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 75.92/76.14 2292[37:Spt:2290.0] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.14 2294[37:Res:2292.0,61.1] always3(s32) || -> . % 75.92/76.14 2295[37:SSi:2294.0,721.0,1961.0] || -> . % 75.92/76.14 2296[37:Spt:2295.0,2290.0,2292.0] || m_main_v_state(s32,c_busy)* -> . % 75.92/76.14 2297[37:Spt:2295.0,2290.1] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.14 2301[37:Res:2297.0,61.1] always3(s33) || -> . % 75.92/76.14 2302[37:SSi:2301.0,722.0] || -> . % 75.92/76.14 2303[35:Spt:2302.0,1959.2,1960.0] || xuntil6(s31)*+ -> . % 75.92/76.14 2304[35:Spt:2302.0,1959.0,1959.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 75.92/76.14 2305[35:Res:53.1,2304.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 75.92/76.14 2307[36:Spt:2305.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.14 2309[36:Res:2307.0,61.1] always3(s32) || -> . % 75.92/76.14 2310[36:SSi:2309.0,721.0] || -> . % 75.92/76.14 2311[36:Spt:2310.0,2305.1,2307.0] || m_main_v_state(s32,c_busy)* -> . % 75.92/76.14 2312[36:Spt:2310.0,2305.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.14 2315[36:Res:2312.0,61.1] always3(s31) || -> . % 75.92/76.14 2316[36:SSi:2315.0,720.0,1958.0] || -> . % 75.92/76.14 2317[34:Spt:2316.0,1953.2,1957.0] || xuntil6(s30)*+ -> . % 75.92/76.14 2318[34:Spt:2316.0,1953.0,1953.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.14 2319[34:Res:53.1,2318.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.14 2321[35:Spt:2319.1] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.14 2323[35:Res:2321.0,61.1] always3(s31) || -> . % 75.92/76.14 2324[35:SSi:2323.0,720.0] || -> . % 75.92/76.14 2325[35:Spt:2324.0,2319.1,2321.0] || m_main_v_state(s31,c_busy)* -> . % 75.92/76.14 2326[35:Spt:2324.0,2319.0] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.14 2329[35:Res:2326.0,61.1] always3(s30) || -> . % 75.92/76.14 2330[35:SSi:2329.0,719.0,1952.0] || -> . % 75.92/76.14 2331[33:Spt:2330.0,1950.2,1951.0] || xuntil6(s29)*+ -> . % 75.92/76.14 2332[33:Spt:2330.0,1950.0,1950.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 75.92/76.14 2333[33:Res:53.1,2332.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 75.92/76.14 2335[34:Spt:2333.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.14 2337[34:Res:2335.0,61.1] always3(s30) || -> . % 75.92/76.14 2338[34:SSi:2337.0,719.0] || -> . % 75.92/76.14 2339[34:Spt:2338.0,2333.1,2335.0] || m_main_v_state(s30,c_busy)* -> . % 75.92/76.14 2340[34:Spt:2338.0,2333.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.14 2343[34:Res:2340.0,61.1] always3(s29) || -> . % 75.92/76.14 2344[34:SSi:2343.0,718.0,1949.0] || -> . % 75.92/76.14 2345[32:Spt:2344.0,1944.2,1948.0] || xuntil6(s28)*+ -> . % 75.92/76.14 2346[32:Spt:2344.0,1944.0,1944.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.14 2347[32:Res:53.1,2346.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.14 2349[33:Spt:2347.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.14 2351[33:Res:2349.0,61.1] always3(s29) || -> . % 75.92/76.14 2352[33:SSi:2351.0,718.0] || -> . % 75.92/76.14 2353[33:Spt:2352.0,2347.1,2349.0] || m_main_v_state(s29,c_busy)* -> . % 75.92/76.14 2354[33:Spt:2352.0,2347.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.14 2357[33:Res:2354.0,61.1] always3(s28) || -> . % 75.92/76.14 2358[33:SSi:2357.0,717.0,1943.0] || -> . % 75.92/76.14 2359[31:Spt:2358.0,1941.2,1942.0] || xuntil6(s27)*+ -> . % 75.92/76.14 2360[31:Spt:2358.0,1941.0,1941.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.14 2361[31:Res:53.1,2360.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.14 2363[32:Spt:2361.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.14 2365[32:Res:2363.0,61.1] always3(s28) || -> . % 75.92/76.14 2366[32:SSi:2365.0,717.0] || -> . % 75.92/76.14 2367[32:Spt:2366.0,2361.1,2363.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.14 2368[32:Spt:2366.0,2361.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.14 2371[32:Res:2368.0,61.1] always3(s27) || -> . % 75.92/76.14 2372[32:SSi:2371.0,716.0,1940.0] || -> . % 75.92/76.14 2373[30:Spt:2372.0,1935.2,1939.0] || xuntil6(s26)*+ -> . % 75.92/76.14 2374[30:Spt:2372.0,1935.0,1935.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.14 2375[30:Res:53.1,2374.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.14 2377[31:Spt:2375.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.14 2379[31:Res:2377.0,61.1] always3(s27) || -> . % 75.92/76.14 2380[31:SSi:2379.0,716.0] || -> . % 75.92/76.14 2381[31:Spt:2380.0,2375.1,2377.0] || m_main_v_state(s27,c_busy)* -> . % 75.92/76.14 2382[31:Spt:2380.0,2375.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.14 2385[31:Res:2382.0,61.1] always3(s26) || -> . % 75.92/76.14 2386[31:SSi:2385.0,715.0,1934.0] || -> . % 75.92/76.14 2387[29:Spt:2386.0,1932.2,1933.0] || xuntil6(s25)*+ -> . % 75.92/76.14 2388[29:Spt:2386.0,1932.0,1932.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.14 2389[29:Res:53.1,2388.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.14 2394[30:Spt:2389.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.14 2396[30:Res:2394.0,61.1] always3(s26) || -> . % 75.92/76.14 2397[30:SSi:2396.0,715.0] || -> . % 75.92/76.14 2398[30:Spt:2397.0,2389.1,2394.0] || m_main_v_state(s26,c_busy)* -> . % 75.92/76.14 2399[30:Spt:2397.0,2389.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.14 2402[30:Res:2399.0,61.1] always3(s25) || -> . % 75.92/76.14 2403[30:SSi:2402.0,714.0,1931.0] || -> . % 75.92/76.14 2404[28:Spt:2403.0,1926.2,1930.0] || xuntil6(s24)*+ -> . % 75.92/76.14 2405[28:Spt:2403.0,1926.0,1926.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.14 2406[28:Res:53.1,2405.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.14 2408[29:Spt:2406.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.14 2410[29:Res:2408.0,61.1] always3(s24) || -> . % 75.92/76.14 2411[29:SSi:2410.0,713.0,1925.0] || -> . % 75.92/76.14 2412[29:Spt:2411.0,2406.0,2408.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.14 2413[29:Spt:2411.0,2406.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.14 2417[29:Res:2413.0,61.1] always3(s25) || -> . % 75.92/76.14 2418[29:SSi:2417.0,714.0] || -> . % 75.92/76.14 2419[27:Spt:2418.0,1923.2,1924.0] || xuntil6(s23)*+ -> . % 75.92/76.14 2420[27:Spt:2418.0,1923.0,1923.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.14 2421[27:Res:53.1,2420.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.14 2423[28:Spt:2421.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.14 2425[28:Res:2423.0,61.1] always3(s24) || -> . % 75.92/76.14 2426[28:SSi:2425.0,713.0] || -> . % 75.92/76.14 2427[28:Spt:2426.0,2421.1,2423.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.14 2428[28:Spt:2426.0,2421.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.14 2431[28:Res:2428.0,61.1] always3(s23) || -> . % 75.92/76.14 2432[28:SSi:2431.0,712.0,1922.0] || -> . % 75.92/76.14 2433[26:Spt:2432.0,1917.2,1921.0] || xuntil6(s22)*+ -> . % 75.92/76.14 2434[26:Spt:2432.0,1917.0,1917.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.14 2435[26:Res:53.1,2434.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.14 2440[27:Spt:2435.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.14 2442[27:Res:2440.0,61.1] always3(s22) || -> . % 75.92/76.14 2443[27:SSi:2442.0,711.0,1916.0] || -> . % 75.92/76.14 2444[27:Spt:2443.0,2435.0,2440.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.14 2445[27:Spt:2443.0,2435.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.14 2449[27:Res:2445.0,61.1] always3(s23) || -> . % 75.92/76.14 2450[27:SSi:2449.0,712.0] || -> . % 75.92/76.14 2451[25:Spt:2450.0,1914.2,1915.0] || xuntil6(s21)*+ -> . % 75.92/76.14 2452[25:Spt:2450.0,1914.0,1914.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.14 2453[25:Res:53.1,2452.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.14 2455[26:Spt:2453.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.14 2457[26:Res:2455.0,61.1] always3(s22) || -> . % 75.92/76.14 2458[26:SSi:2457.0,711.0] || -> . % 75.92/76.14 2459[26:Spt:2458.0,2453.1,2455.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.14 2460[26:Spt:2458.0,2453.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.14 2463[26:Res:2460.0,61.1] always3(s21) || -> . % 75.92/76.14 2464[26:SSi:2463.0,710.0,1913.0] || -> . % 75.92/76.14 2465[24:Spt:2464.0,1908.2,1912.0] || xuntil6(s20)*+ -> . % 75.92/76.14 2466[24:Spt:2464.0,1908.0,1908.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.14 2467[24:Res:53.1,2466.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.14 2469[25:Spt:2467.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.14 2471[25:Res:2469.0,61.1] always3(s21) || -> . % 75.92/76.14 2472[25:SSi:2471.0,710.0] || -> . % 75.92/76.14 2473[25:Spt:2472.0,2467.1,2469.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.14 2474[25:Spt:2472.0,2467.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.14 2477[25:Res:2474.0,61.1] always3(s20) || -> . % 75.92/76.14 2478[25:SSi:2477.0,709.0,1907.0] || -> . % 75.92/76.14 2479[23:Spt:2478.0,1905.2,1906.0] || xuntil6(s19)*+ -> . % 75.92/76.14 2480[23:Spt:2478.0,1905.0,1905.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.14 2481[23:Res:53.1,2480.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.14 2486[24:Spt:2481.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.14 2488[24:Res:2486.0,61.1] always3(s20) || -> . % 75.92/76.14 2489[24:SSi:2488.0,709.0] || -> . % 75.92/76.14 2490[24:Spt:2489.0,2481.1,2486.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.14 2491[24:Spt:2489.0,2481.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.14 2494[24:Res:2491.0,61.1] always3(s19) || -> . % 75.92/76.14 2495[24:SSi:2494.0,708.0,1904.0] || -> . % 75.92/76.14 2496[22:Spt:2495.0,1899.2,1903.0] || xuntil6(s18)*+ -> . % 75.92/76.14 2497[22:Spt:2495.0,1899.0,1899.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.14 2498[22:Res:53.1,2497.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.14 2500[23:Spt:2498.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.14 2502[23:Res:2500.0,61.1] always3(s18) || -> . % 75.92/76.14 2503[23:SSi:2502.0,707.0,1898.0] || -> . % 75.92/76.14 2504[23:Spt:2503.0,2498.0,2500.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.14 2505[23:Spt:2503.0,2498.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.14 2509[23:Res:2505.0,61.1] always3(s19) || -> . % 75.92/76.14 2510[23:SSi:2509.0,708.0] || -> . % 75.92/76.14 2511[21:Spt:2510.0,1896.2,1897.0] || xuntil6(s17)*+ -> . % 75.92/76.14 2512[21:Spt:2510.0,1896.0,1896.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.14 2513[21:Res:53.1,2512.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.14 2515[22:Spt:2513.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.14 2517[22:Res:2515.0,61.1] always3(s18) || -> . % 75.92/76.14 2518[22:SSi:2517.0,707.0] || -> . % 75.92/76.14 2519[22:Spt:2518.0,2513.1,2515.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.14 2520[22:Spt:2518.0,2513.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.14 2523[22:Res:2520.0,61.1] always3(s17) || -> . % 75.92/76.14 2524[22:SSi:2523.0,706.0,1895.0] || -> . % 75.92/76.14 2525[20:Spt:2524.0,1890.2,1894.0] || xuntil6(s16)*+ -> . % 75.92/76.14 2526[20:Spt:2524.0,1890.0,1890.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.14 2527[20:Res:53.1,2526.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.14 2532[21:Spt:2527.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.14 2534[21:Res:2532.0,61.1] always3(s16) || -> . % 75.92/76.14 2535[21:SSi:2534.0,705.0,1889.0] || -> . % 75.92/76.14 2536[21:Spt:2535.0,2527.0,2532.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.14 2537[21:Spt:2535.0,2527.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.14 2541[21:Res:2537.0,61.1] always3(s17) || -> . % 75.92/76.14 2542[21:SSi:2541.0,706.0] || -> . % 75.92/76.14 2543[19:Spt:2542.0,1887.2,1888.0] || xuntil6(s15)*+ -> . % 75.92/76.14 2544[19:Spt:2542.0,1887.0,1887.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.14 2545[19:Res:53.1,2544.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.14 2547[20:Spt:2545.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.14 2549[20:Res:2547.0,61.1] always3(s16) || -> . % 75.92/76.14 2550[20:SSi:2549.0,705.0] || -> . % 75.92/76.14 2551[20:Spt:2550.0,2545.1,2547.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.14 2552[20:Spt:2550.0,2545.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.14 2555[20:Res:2552.0,61.1] always3(s15) || -> . % 75.92/76.14 2556[20:SSi:2555.0,704.0,1886.0] || -> . % 75.92/76.14 2557[18:Spt:2556.0,1881.2,1885.0] || xuntil6(s14)*+ -> . % 75.92/76.14 2558[18:Spt:2556.0,1881.0,1881.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.14 2559[18:Res:53.1,2558.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.14 2561[19:Spt:2559.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.14 2563[19:Res:2561.0,61.1] always3(s15) || -> . % 75.92/76.14 2564[19:SSi:2563.0,704.0] || -> . % 75.92/76.14 2565[19:Spt:2564.0,2559.1,2561.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.14 2566[19:Spt:2564.0,2559.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.14 2569[19:Res:2566.0,61.1] always3(s14) || -> . % 75.92/76.14 2570[19:SSi:2569.0,703.0,1880.0] || -> . % 75.92/76.14 2571[17:Spt:2570.0,1878.2,1879.0] || xuntil6(s13)*+ -> . % 75.92/76.14 2572[17:Spt:2570.0,1878.0,1878.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.14 2573[17:Res:53.1,2572.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.14 2578[18:Spt:2573.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.14 2580[18:Res:2578.0,61.1] always3(s14) || -> . % 75.92/76.14 2581[18:SSi:2580.0,703.0] || -> . % 75.92/76.14 2582[18:Spt:2581.0,2573.1,2578.0] || m_main_v_state(s14,c_busy)* -> . % 75.92/76.14 2583[18:Spt:2581.0,2573.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.14 2586[18:Res:2583.0,61.1] always3(s13) || -> . % 75.92/76.14 2587[18:SSi:2586.0,702.0,1877.0] || -> . % 75.92/76.14 2588[16:Spt:2587.0,1872.2,1876.0] || xuntil6(s12)*+ -> . % 75.92/76.14 2589[16:Spt:2587.0,1872.0,1872.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.14 2590[16:Res:53.1,2589.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.14 2592[17:Spt:2590.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.14 2594[17:Res:2592.0,61.1] always3(s12) || -> . % 75.92/76.14 2595[17:SSi:2594.0,701.0,1871.0] || -> . % 75.92/76.14 2596[17:Spt:2595.0,2590.0,2592.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.14 2597[17:Spt:2595.0,2590.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.14 2601[17:Res:2597.0,61.1] always3(s13) || -> . % 75.92/76.14 2602[17:SSi:2601.0,702.0] || -> . % 75.92/76.14 2603[15:Spt:2602.0,1869.2,1870.0] || xuntil6(s11)*+ -> . % 75.92/76.14 2604[15:Spt:2602.0,1869.0,1869.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.14 2605[15:Res:53.1,2604.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.14 2607[16:Spt:2605.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.14 2609[16:Res:2607.0,61.1] always3(s12) || -> . % 75.92/76.14 2610[16:SSi:2609.0,701.0] || -> . % 75.92/76.14 2611[16:Spt:2610.0,2605.1,2607.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.14 2612[16:Spt:2610.0,2605.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.14 2615[16:Res:2612.0,61.1] always3(s11) || -> . % 75.92/76.14 2616[16:SSi:2615.0,700.0,1868.0] || -> . % 75.92/76.14 2617[14:Spt:2616.0,1863.2,1867.0] || xuntil6(s10)*+ -> . % 75.92/76.14 2618[14:Spt:2616.0,1863.0,1863.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.14 2619[14:Res:53.1,2618.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.14 2624[15:Spt:2619.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.14 2626[15:Res:2624.0,61.1] always3(s10) || -> . % 75.92/76.14 2627[15:SSi:2626.0,699.0,1862.0] || -> . % 75.92/76.14 2628[15:Spt:2627.0,2619.0,2624.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.14 2629[15:Spt:2627.0,2619.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.14 2633[15:Res:2629.0,61.1] always3(s11) || -> . % 75.92/76.14 2634[15:SSi:2633.0,700.0] || -> . % 75.92/76.14 2635[13:Spt:2634.0,1860.2,1861.0] || xuntil6(s9)*+ -> . % 75.92/76.14 2636[13:Spt:2634.0,1860.0,1860.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.14 2637[13:Res:53.1,2636.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.14 2639[14:Spt:2637.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.14 2641[14:Res:2639.0,61.1] always3(s10) || -> . % 75.92/76.14 2642[14:SSi:2641.0,699.0] || -> . % 75.92/76.14 2643[14:Spt:2642.0,2637.1,2639.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.14 2644[14:Spt:2642.0,2637.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.14 2647[14:Res:2644.0,61.1] always3(s9) || -> . % 75.92/76.14 2648[14:SSi:2647.0,698.0,1859.0] || -> . % 75.92/76.14 2649[12:Spt:2648.0,1854.2,1858.0] || xuntil6(s8)*+ -> . % 75.92/76.14 2650[12:Spt:2648.0,1854.0,1854.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.14 2651[12:Res:53.1,2650.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.14 2653[13:Spt:2651.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.14 2655[13:Res:2653.0,61.1] always3(s9) || -> . % 75.92/76.14 2656[13:SSi:2655.0,698.0] || -> . % 75.92/76.14 2657[13:Spt:2656.0,2651.1,2653.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.14 2658[13:Spt:2656.0,2651.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.14 2661[13:Res:2658.0,61.1] always3(s8) || -> . % 75.92/76.14 2662[13:SSi:2661.0,697.0,1853.0] || -> . % 75.92/76.14 2663[11:Spt:2662.0,1851.2,1852.0] || xuntil6(s7)*+ -> . % 75.92/76.14 2664[11:Spt:2662.0,1851.0,1851.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.14 2665[11:Res:53.1,2664.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.14 2670[12:Spt:2665.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.14 2672[12:Res:2670.0,61.1] always3(s8) || -> . % 75.92/76.14 2673[12:SSi:2672.0,697.0] || -> . % 75.92/76.14 2674[12:Spt:2673.0,2665.1,2670.0] || m_main_v_state(s8,c_busy)* -> . % 75.92/76.14 2675[12:Spt:2673.0,2665.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.14 2678[12:Res:2675.0,61.1] always3(s7) || -> . % 75.92/76.14 2679[12:SSi:2678.0,696.0,1850.0] || -> . % 75.92/76.14 2680[10:Spt:2679.0,1845.2,1849.0] || xuntil6(s6)*+ -> . % 75.92/76.14 2681[10:Spt:2679.0,1845.0,1845.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.14 2682[10:Res:53.1,2681.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.14 2684[11:Spt:2682.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.14 2686[11:Res:2684.0,61.1] always3(s6) || -> . % 75.92/76.14 2687[11:SSi:2686.0,695.0,1844.0] || -> . % 75.92/76.14 2688[11:Spt:2687.0,2682.0,2684.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.14 2689[11:Spt:2687.0,2682.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.14 2693[11:Res:2689.0,61.1] always3(s7) || -> . % 75.92/76.14 2694[11:SSi:2693.0,696.0] || -> . % 75.92/76.14 2695[9:Spt:2694.0,1842.2,1843.0] || xuntil6(s5)*+ -> . % 75.92/76.14 2696[9:Spt:2694.0,1842.0,1842.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.14 2697[9:Res:53.1,2696.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.14 2699[10:Spt:2697.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.14 2701[10:Res:2699.0,61.1] always3(s6) || -> . % 75.92/76.14 2702[10:SSi:2701.0,695.0] || -> . % 75.92/76.14 2703[10:Spt:2702.0,2697.1,2699.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.14 2704[10:Spt:2702.0,2697.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.14 2707[10:Res:2704.0,61.1] always3(s5) || -> . % 75.92/76.14 2708[10:SSi:2707.0,694.0,1841.0] || -> . % 75.92/76.14 2709[8:Spt:2708.0,1836.2,1840.0] || xuntil6(s4)*+ -> . % 75.92/76.14 2710[8:Spt:2708.0,1836.0,1836.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.14 2711[8:Res:53.1,2710.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.14 2716[9:Spt:2711.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.14 2718[9:Res:2716.0,61.1] always3(s4) || -> . % 75.92/76.14 2719[9:SSi:2718.0,693.0,1835.0] || -> . % 75.92/76.14 2720[9:Spt:2719.0,2711.0,2716.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.14 2721[9:Spt:2719.0,2711.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.14 2725[9:Res:2721.0,61.1] always3(s5) || -> . % 75.92/76.14 2726[9:SSi:2725.0,694.0] || -> . % 75.92/76.14 2727[7:Spt:2726.0,1833.2,1834.0] || xuntil6(s3)*+ -> . % 75.92/76.14 2728[7:Spt:2726.0,1833.0,1833.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.14 2729[7:Res:53.1,2728.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.14 2731[8:Spt:2729.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.14 2733[8:Res:2731.0,61.1] always3(s4) || -> . % 75.92/76.14 2734[8:SSi:2733.0,693.0] || -> . % 75.92/76.14 2735[8:Spt:2734.0,2729.1,2731.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.14 2736[8:Spt:2734.0,2729.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.14 2739[8:Res:2736.0,61.1] always3(s3) || -> . % 75.92/76.14 2740[8:SSi:2739.0,692.0,1832.0] || -> . % 75.92/76.14 2741[6:Spt:2740.0,1830.2,1831.0] || xuntil6(s2)*+ -> . % 75.92/76.14 2742[6:Spt:2740.0,1830.0,1830.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.14 2743[6:Res:53.1,2742.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.14 2745[7:Spt:2743.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.14 2747[7:Res:2745.0,61.1] always3(s3) || -> . % 75.92/76.14 2748[7:SSi:2747.0,692.0] || -> . % 75.92/76.14 2749[7:Spt:2748.0,2743.1,2745.0] || m_main_v_state(s3,c_busy)* -> . % 75.92/76.14 2750[7:Spt:2748.0,2743.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.14 2753[7:Res:2750.0,61.1] always3(s2) || -> . % 75.92/76.14 2754[7:SSi:2753.0,691.0,1829.0] || -> . % 75.92/76.14 2755[5:Spt:2754.0,1824.2,1828.0] || xuntil6(s1)*+ -> . % 75.92/76.14 2756[5:Spt:2754.0,1824.0,1824.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.14 2757[5:Res:53.1,2756.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.14 2762[6:Spt:2757.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.14 2764[6:Res:2762.0,61.1] always3(s1) || -> . % 75.92/76.14 2765[6:SSi:2764.0,690.0,1823.0] || -> . % 75.92/76.14 2766[6:Spt:2765.0,2757.0,2762.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.14 2767[6:Spt:2765.0,2757.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.14 2772[6:Res:2767.0,61.1] always3(s2) || -> . % 75.92/76.14 2773[6:SSi:2772.0,691.0] || -> . % 75.92/76.14 2774[4:Spt:2773.0,74.0,1822.0] || xuntil6(s0)*+ -> . % 75.92/76.14 2775[4:Spt:2773.0,74.1] || -> node4(s0)*. % 75.92/76.14 2776[4:MRR:758.1,2774.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.14 2778[4:Res:2776.0,61.1] always3(s1) || -> . % 75.92/76.14 2779[4:SSi:2778.0,690.0] || -> . % 75.92/76.14 2780[3:Spt:2779.0,1812.0,1816.0] || trans(s49,s48)*+ -> . % 75.92/76.14 2781[3:Spt:2779.0,1812.1,1812.2,1812.3,1812.4,1812.5,1812.6,1812.7,1812.8,1812.9,1812.10,1812.11,1812.12,1812.13,1812.14,1812.15,1812.16,1812.17,1812.18,1812.19,1812.20,1812.21,1812.22,1812.23,1812.24,1812.25,1812.26,1812.27,1812.28,1812.29,1812.30,1812.31,1812.32,1812.33,1812.34,1812.35,1812.36,1812.37,1812.38,1812.39,1812.40,1812.41,1812.42,1812.43,1812.44,1812.45,1812.46,1812.47,1812.48] || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.14 2783[3:MRR:1813.0,2780.0] || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.14 2784[3:MRR:1815.1,2780.0] xuntil6(s49) || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.14 2785[4:Spt:2781.0] || -> trans(s49,s47)*. % 75.92/76.14 2786[4:Res:2785.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s47)*. % 75.92/76.14 2788[4:Res:2785.0,60.0] || -> node2(s49,s47)*. % 75.92/76.14 2789[4:SSi:2786.1,50.0,738.0] xuntil6(s49) || -> until2p7(s47)*. % 75.92/76.14 2790[4:Res:2788.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 75.92/76.14 2791[5:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.14 2792[5:MRR:176.0,2791.0] || -> until5(s1)*. % 75.92/76.14 2793[5:MRR:964.0,2792.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.14 2797[6:Spt:2793.2] || -> xuntil6(s1)*. % 75.92/76.14 2798[6:MRR:175.0,2797.0] || -> until5(s2)*. % 75.92/76.14 2799[6:MRR:963.0,2798.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.14 2800[7:Spt:2799.2] || -> xuntil6(s2)*. % 75.92/76.14 2801[7:MRR:174.0,2800.0] || -> until5(s3)*. % 75.92/76.14 2802[7:MRR:962.0,2801.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.14 2803[8:Spt:2802.2] || -> xuntil6(s3)*. % 75.92/76.14 2804[8:MRR:173.0,2803.0] || -> until5(s4)*. % 75.92/76.14 2805[8:MRR:961.0,2804.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.14 2806[9:Spt:2805.2] || -> xuntil6(s4)*. % 75.92/76.14 2807[9:MRR:172.0,2806.0] || -> until5(s5)*. % 75.92/76.14 2808[9:MRR:960.0,2807.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.14 2812[10:Spt:2808.2] || -> xuntil6(s5)*. % 75.92/76.14 2813[10:MRR:171.0,2812.0] || -> until5(s6)*. % 75.92/76.14 2814[10:MRR:959.0,2813.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.14 2815[11:Spt:2814.2] || -> xuntil6(s6)*. % 75.92/76.14 2816[11:MRR:170.0,2815.0] || -> until5(s7)*. % 75.92/76.14 2817[11:MRR:958.0,2816.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.14 2821[12:Spt:2817.2] || -> xuntil6(s7)*. % 75.92/76.14 2822[12:MRR:169.0,2821.0] || -> until5(s8)*. % 75.92/76.14 2823[12:MRR:957.0,2822.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.14 2824[13:Spt:2823.2] || -> xuntil6(s8)*. % 75.92/76.14 2825[13:MRR:168.0,2824.0] || -> until5(s9)*. % 75.92/76.14 2826[13:MRR:956.0,2825.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.14 2830[14:Spt:2826.2] || -> xuntil6(s9)*. % 75.92/76.14 2831[14:MRR:167.0,2830.0] || -> until5(s10)*. % 75.92/76.14 2832[14:MRR:955.0,2831.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.14 2833[15:Spt:2832.2] || -> xuntil6(s10)*. % 75.92/76.14 2834[15:MRR:166.0,2833.0] || -> until5(s11)*. % 75.92/76.14 2835[15:MRR:954.0,2834.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.14 2839[16:Spt:2835.2] || -> xuntil6(s11)*. % 75.92/76.14 2840[16:MRR:165.0,2839.0] || -> until5(s12)*. % 75.92/76.14 2841[16:MRR:953.0,2840.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.14 2842[17:Spt:2841.2] || -> xuntil6(s12)*. % 75.92/76.14 2843[17:MRR:164.0,2842.0] || -> until5(s13)*. % 75.92/76.14 2844[17:MRR:952.0,2843.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.14 2848[18:Spt:2844.2] || -> xuntil6(s13)*. % 75.92/76.14 2849[18:MRR:163.0,2848.0] || -> until5(s14)*. % 75.92/76.14 2850[18:MRR:951.0,2849.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.14 2851[19:Spt:2850.2] || -> xuntil6(s14)*. % 75.92/76.14 2852[19:MRR:162.0,2851.0] || -> until5(s15)*. % 75.92/76.14 2853[19:MRR:950.0,2852.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.14 2857[20:Spt:2853.2] || -> xuntil6(s15)*. % 75.92/76.14 2858[20:MRR:161.0,2857.0] || -> until5(s16)*. % 75.92/76.14 2859[20:MRR:949.0,2858.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.14 2860[21:Spt:2859.2] || -> xuntil6(s16)*. % 75.92/76.14 2861[21:MRR:160.0,2860.0] || -> until5(s17)*. % 75.92/76.14 2862[21:MRR:948.0,2861.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.14 2866[22:Spt:2862.2] || -> xuntil6(s17)*. % 75.92/76.14 2867[22:MRR:159.0,2866.0] || -> until5(s18)*. % 75.92/76.14 2868[22:MRR:947.0,2867.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.14 2869[23:Spt:2868.2] || -> xuntil6(s18)*. % 75.92/76.14 2870[23:MRR:158.0,2869.0] || -> until5(s19)*. % 75.92/76.14 2871[23:MRR:946.0,2870.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.14 2875[24:Spt:2871.2] || -> xuntil6(s19)*. % 75.92/76.14 2876[24:MRR:157.0,2875.0] || -> until5(s20)*. % 75.92/76.14 2877[24:MRR:945.0,2876.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.14 2878[25:Spt:2877.2] || -> xuntil6(s20)*. % 75.92/76.14 2879[25:MRR:156.0,2878.0] || -> until5(s21)*. % 75.92/76.14 2880[25:MRR:944.0,2879.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.14 2884[26:Spt:2880.2] || -> xuntil6(s21)*. % 75.92/76.14 2885[26:MRR:155.0,2884.0] || -> until5(s22)*. % 75.92/76.14 2886[26:MRR:943.0,2885.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.14 2887[27:Spt:2886.2] || -> xuntil6(s22)*. % 75.92/76.14 2888[27:MRR:154.0,2887.0] || -> until5(s23)*. % 75.92/76.14 2889[27:MRR:942.0,2888.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.14 2893[28:Spt:2889.2] || -> xuntil6(s23)*. % 75.92/76.14 2894[28:MRR:153.0,2893.0] || -> until5(s24)*. % 75.92/76.14 2895[28:MRR:941.0,2894.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.14 2896[29:Spt:2895.2] || -> xuntil6(s24)*. % 75.92/76.14 2897[29:MRR:152.0,2896.0] || -> until5(s25)*. % 75.92/76.14 2898[29:MRR:940.0,2897.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.14 2902[30:Spt:2898.2] || -> xuntil6(s25)*. % 75.92/76.14 2903[30:MRR:151.0,2902.0] || -> until5(s26)*. % 75.92/76.14 2904[30:MRR:939.0,2903.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.14 2905[31:Spt:2904.2] || -> xuntil6(s26)*. % 75.92/76.14 2906[31:MRR:150.0,2905.0] || -> until5(s27)*. % 75.92/76.14 2907[31:MRR:938.0,2906.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.14 2911[32:Spt:2907.2] || -> xuntil6(s27)*. % 75.92/76.14 2912[32:MRR:149.0,2911.0] || -> until5(s28)*. % 75.92/76.14 2913[32:MRR:937.0,2912.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.14 2914[33:Spt:2913.2] || -> xuntil6(s28)*. % 75.92/76.14 2915[33:MRR:148.0,2914.0] || -> until5(s29)*. % 75.92/76.14 2916[33:MRR:936.0,2915.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.14 2920[34:Spt:2916.2] || -> xuntil6(s29)*. % 75.92/76.14 2921[34:MRR:147.0,2920.0] || -> until5(s30)*. % 75.92/76.14 2922[34:MRR:935.0,2921.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.14 2923[35:Spt:2922.2] || -> xuntil6(s30)*. % 75.92/76.14 2924[35:MRR:146.0,2923.0] || -> until5(s31)*. % 75.92/76.14 2925[35:MRR:934.0,2924.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.14 2929[36:Spt:2925.2] || -> xuntil6(s31)*. % 75.92/76.14 2930[36:MRR:145.0,2929.0] || -> until5(s32)*. % 75.92/76.14 2931[36:MRR:933.0,2930.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.14 2932[37:Spt:2931.2] || -> xuntil6(s32)*. % 75.92/76.14 2933[37:MRR:144.0,2932.0] || -> until5(s33)*. % 75.92/76.14 2934[37:MRR:932.0,2933.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.14 2938[38:Spt:2934.1] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.14 2940[38:Res:2938.0,61.1] always3(s34) || -> . % 75.92/76.14 2941[38:SSi:2940.0,723.0] || -> . % 75.92/76.14 2942[38:Spt:2941.0,2934.1,2938.0] || m_main_v_state(s34,c_busy)*+ -> . % 75.92/76.14 2943[38:Spt:2941.0,2934.0,2934.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 75.92/76.14 2946[38:Res:53.1,2943.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 75.92/76.14 2948[39:Spt:2946.1] || -> xuntil6(s33)*. % 75.92/76.14 2949[39:MRR:143.0,2948.0] || -> until5(s34)*. % 75.92/76.14 2950[39:MRR:931.0,2949.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.14 2955[40:Spt:2950.2] || -> xuntil6(s34)*. % 75.92/76.14 2956[40:MRR:142.0,2955.0] || -> until5(s35)*. % 75.92/76.14 2957[40:MRR:930.0,2956.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.14 2958[41:Spt:2957.1] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.14 2960[41:Res:2958.0,61.1] always3(s36) || -> . % 75.92/76.14 2961[41:SSi:2960.0,725.0] || -> . % 75.92/76.14 2962[41:Spt:2961.0,2957.1,2958.0] || m_main_v_state(s36,c_busy)*+ -> . % 75.92/76.14 2963[41:Spt:2961.0,2957.0,2957.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 75.92/76.14 2966[41:Res:53.1,2963.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 75.92/76.14 2968[42:Spt:2966.1] || -> xuntil6(s35)*. % 75.92/76.14 2969[42:MRR:141.0,2968.0] || -> until5(s36)*. % 75.92/76.14 2970[42:MRR:929.0,2969.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.14 2978[43:Spt:2970.2] || -> xuntil6(s36)*. % 75.92/76.14 2979[43:MRR:140.0,2978.0] || -> until5(s37)*. % 75.92/76.14 2980[43:MRR:928.0,2979.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.14 2981[44:Spt:2980.1] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.14 2983[44:Res:2981.0,61.1] always3(s38) || -> . % 75.92/76.14 2984[44:SSi:2983.0,727.0] || -> . % 75.92/76.14 2985[44:Spt:2984.0,2980.1,2981.0] || m_main_v_state(s38,c_busy)*+ -> . % 75.92/76.14 2986[44:Spt:2984.0,2980.0,2980.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 75.92/76.14 2989[44:Res:53.1,2986.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 75.92/76.14 2994[45:Spt:2989.1] || -> xuntil6(s37)*. % 75.92/76.14 2995[45:MRR:139.0,2994.0] || -> until5(s38)*. % 75.92/76.14 2996[45:MRR:927.0,2995.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.14 2998[46:Spt:2996.2] || -> xuntil6(s38)*. % 75.92/76.14 2999[46:MRR:138.0,2998.0] || -> until5(s39)*. % 75.92/76.14 3000[46:MRR:926.0,2999.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.14 3001[47:Spt:3000.1] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.14 3003[47:Res:3001.0,61.1] always3(s40) || -> . % 75.92/76.14 3004[47:SSi:3003.0,729.0] || -> . % 75.92/76.14 3005[47:Spt:3004.0,3000.1,3001.0] || m_main_v_state(s40,c_busy)*+ -> . % 75.92/76.14 3006[47:Spt:3004.0,3000.0,3000.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 75.92/76.14 3009[47:Res:53.1,3006.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 75.92/76.14 3011[48:Spt:3009.1] || -> xuntil6(s39)*. % 75.92/76.14 3012[48:MRR:137.0,3011.0] || -> until5(s40)*. % 75.92/76.14 3013[48:MRR:925.0,3012.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.14 3018[49:Spt:3013.2] || -> xuntil6(s40)*. % 75.92/76.14 3019[49:MRR:136.0,3018.0] || -> until5(s41)*. % 75.92/76.14 3020[49:MRR:924.0,3019.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.14 3021[50:Spt:3020.1] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.14 3023[50:Res:3021.0,61.1] always3(s42) || -> . % 75.92/76.14 3024[50:SSi:3023.0,731.0] || -> . % 75.92/76.14 3025[50:Spt:3024.0,3020.1,3021.0] || m_main_v_state(s42,c_busy)*+ -> . % 75.92/76.14 3026[50:Spt:3024.0,3020.0,3020.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 75.92/76.14 3029[50:Res:53.1,3026.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 75.92/76.14 3031[51:Spt:3029.1] || -> xuntil6(s41)*. % 75.92/76.14 3032[51:MRR:135.0,3031.0] || -> until5(s42)*. % 75.92/76.14 3033[51:MRR:923.0,3032.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.14 3041[52:Spt:3033.2] || -> xuntil6(s42)*. % 75.92/76.14 3042[52:MRR:134.0,3041.0] || -> until5(s43)*. % 75.92/76.14 3043[52:MRR:922.0,3042.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.14 3044[53:Spt:3043.1] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.14 3046[53:Res:3044.0,61.1] always3(s44) || -> . % 75.92/76.14 3047[53:SSi:3046.0,733.0] || -> . % 75.92/76.14 3048[53:Spt:3047.0,3043.1,3044.0] || m_main_v_state(s44,c_busy)*+ -> . % 75.92/76.14 3049[53:Spt:3047.0,3043.0,3043.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 75.92/76.14 3052[53:Res:53.1,3049.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 75.92/76.14 3057[54:Spt:3052.1] || -> xuntil6(s43)*. % 75.92/76.14 3058[54:MRR:133.0,3057.0] || -> until5(s44)*. % 75.92/76.14 3059[54:MRR:921.0,3058.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.14 3061[55:Spt:3059.2] || -> xuntil6(s44)*. % 75.92/76.14 3062[55:MRR:132.0,3061.0] || -> until5(s45)*. % 75.92/76.14 3063[55:MRR:920.0,3062.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.14 3064[56:Spt:3063.1] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.14 3066[56:Res:3064.0,61.1] always3(s46) || -> . % 75.92/76.14 3067[56:SSi:3066.0,735.0] || -> . % 75.92/76.14 3068[56:Spt:3067.0,3063.1,3064.0] || m_main_v_state(s46,c_busy)*+ -> . % 75.92/76.14 3069[56:Spt:3067.0,3063.0,3063.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 75.92/76.14 3072[56:Res:53.1,3069.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 75.92/76.14 3074[57:Spt:3072.1] || -> xuntil6(s45)*. % 75.92/76.14 3075[57:MRR:131.0,3074.0] || -> until5(s46)*. % 75.92/76.14 3076[57:MRR:919.0,3075.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.14 3081[58:Spt:3076.2] || -> xuntil6(s46)*. % 75.92/76.14 3082[58:MRR:130.0,3081.0] || -> until5(s47)*. % 75.92/76.14 3083[58:MRR:918.0,3082.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.14 3084[59:Spt:3083.1] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.14 3086[59:Res:3084.0,61.1] always3(s48) || -> . % 75.92/76.14 3087[59:SSi:3086.0,737.0] || -> . % 75.92/76.14 3088[59:Spt:3087.0,3083.1,3084.0] || m_main_v_state(s48,c_busy)*+ -> . % 75.92/76.14 3089[59:Spt:3087.0,3083.0,3083.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 75.92/76.14 3091[59:MRR:777.2,3088.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 75.92/76.14 3092[59:Res:53.1,3089.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 75.92/76.14 3094[60:Spt:3092.1] || -> xuntil6(s47)*. % 75.92/76.14 3095[60:MRR:129.0,3094.0] || -> until5(s48)*. % 75.92/76.14 3096[60:MRR:917.0,3095.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.14 3104[61:Spt:3096.2] || -> xuntil6(s48)*. % 75.92/76.14 3105[61:MRR:128.0,3104.0] || -> until5(s49)*. % 75.92/76.14 3106[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.14 3107[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.14 3111[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.14 3112[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.14 3116[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.14 3120[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.14 3124[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.14 3131[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.14 3132[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.14 3136[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.14 3140[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.14 3144[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.14 3151[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.14 3152[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.14 3156[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.14 3160[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.14 3164[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.14 3171[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.14 3172[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.14 3176[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.14 3180[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.14 3184[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.14 3191[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.14 3192[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.14 3196[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.14 3200[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.14 3204[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.14 3211[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.14 3212[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.14 3216[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.14 3220[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.14 3224[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.14 3226[4:SoR:2790.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 75.92/76.14 3231[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.14 3235[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.14 3242[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.14 3243[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.14 3247[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.14 3251[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.14 3255[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.14 3259[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.14 3260[4:SoR:3226.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 75.92/76.14 3261[61:SSi:3260.0,50.0,738.0,3105.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 75.92/76.14 3262[62:Spt:3261.1] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.14 3264[62:Res:3262.0,61.1] always3(s47) || -> . % 75.92/76.14 3265[62:SSi:3264.0,736.0,3082.0,3094.0] || -> . % 75.92/76.14 3266[62:Spt:3265.0,3261.1,3262.0] || m_main_v_state(s47,c_busy)*+ -> . % 75.92/76.14 3267[62:Spt:3265.0,3261.0,3261.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.14 3271[62:MRR:3226.2,3266.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.14 3272[62:Res:53.1,3267.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.14 3274[63:Spt:3272.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 3276[63:Res:3274.0,61.1] always3(s49) || -> . % 75.92/76.14 3277[63:SSi:3276.0,50.0,738.0,3105.0] || -> . % 75.92/76.14 3278[63:Spt:3277.0,3272.0,3274.0] || m_main_v_state(s49,c_busy)*+ -> . % 75.92/76.14 3279[63:Spt:3277.0,3272.1] || -> xuntil6(s49)*. % 75.92/76.14 3280[63:MRR:2789.0,3279.0] || -> until2p7(s47)*. % 75.92/76.14 3281[63:MRR:554.0,3280.0] || -> until2p7(s48)* node4(s47). % 75.92/76.14 3283[63:MRR:774.2,3278.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 75.92/76.14 3284[64:Spt:3281.0] || -> until2p7(s48)*. % 75.92/76.14 3285[64:MRR:559.0,3284.0] || -> until2p7(s49)* node4(s48). % 75.92/76.14 3286[65:Spt:3285.0] || -> until2p7(s49)*. % 75.92/76.14 3287[65:MRR:194.0,3286.0] || -> node4(s49)*. % 75.92/76.14 3288[65:MRR:3271.0,3287.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.14 3292[65:Res:53.1,3288.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 3294[65:MRR:3292.0,3278.0] || -> . % 75.92/76.14 3295[65:Spt:3294.0,3285.0,3286.0] || until2p7(s49)*+ -> . % 75.92/76.14 3296[65:Spt:3294.0,3285.1] || -> node4(s48)*. % 75.92/76.14 3297[65:MRR:3283.0,3296.0] || m_main_v_state(s48,c_ready)*+ -> . % 75.92/76.14 3300[65:Res:53.1,3297.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.14 3302[65:MRR:3300.0,3088.0] || -> . % 75.92/76.14 3303[64:Spt:3302.0,3281.0,3284.0] || until2p7(s48)*+ -> . % 75.92/76.14 3304[64:Spt:3302.0,3281.1] || -> node4(s47)*. % 75.92/76.14 3305[64:MRR:3091.0,3304.0] || m_main_v_state(s47,c_ready)*+ -> . % 75.92/76.14 3308[64:Res:53.1,3305.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.14 3310[64:MRR:3308.0,3266.0] || -> . % 75.92/76.14 3311[61:Spt:3310.0,3096.2,3104.0] || xuntil6(s48)*+ -> . % 75.92/76.14 3312[61:Spt:3310.0,3096.0,3096.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.14 3313[61:Res:53.1,3312.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.14 3315[61:MRR:3313.0,3088.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 3317[61:Res:3315.0,61.1] always3(s49) || -> . % 75.92/76.14 3318[61:SSi:3317.0,50.0,738.0] || -> . % 75.92/76.14 3319[60:Spt:3318.0,3092.1,3094.0] || xuntil6(s47)* -> . % 75.92/76.14 3320[60:Spt:3318.0,3092.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.14 3323[60:Res:3320.0,61.1] always3(s47) || -> . % 75.92/76.14 3324[60:SSi:3323.0,736.0,3082.0] || -> . % 75.92/76.14 3325[58:Spt:3324.0,3076.2,3081.0] || xuntil6(s46)*+ -> . % 75.92/76.14 3326[58:Spt:3324.0,3076.0,3076.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.14 3327[58:Res:53.1,3326.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.14 3329[58:MRR:3327.0,3068.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.14 3331[58:Res:3329.0,61.1] always3(s47) || -> . % 75.92/76.14 3332[58:SSi:3331.0,736.0] || -> . % 75.92/76.14 3333[57:Spt:3332.0,3072.1,3074.0] || xuntil6(s45)* -> . % 75.92/76.14 3334[57:Spt:3332.0,3072.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.14 3337[57:Res:3334.0,61.1] always3(s45) || -> . % 75.92/76.14 3338[57:SSi:3337.0,734.0,3062.0] || -> . % 75.92/76.14 3339[55:Spt:3338.0,3059.2,3061.0] || xuntil6(s44)*+ -> . % 75.92/76.14 3340[55:Spt:3338.0,3059.0,3059.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.14 3341[55:Res:53.1,3340.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.14 3343[55:MRR:3341.0,3048.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.14 3345[55:Res:3343.0,61.1] always3(s45) || -> . % 75.92/76.14 3346[55:SSi:3345.0,734.0] || -> . % 75.92/76.14 3347[54:Spt:3346.0,3052.1,3057.0] || xuntil6(s43)* -> . % 75.92/76.14 3348[54:Spt:3346.0,3052.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.14 3351[54:Res:3348.0,61.1] always3(s43) || -> . % 75.92/76.14 3352[54:SSi:3351.0,732.0,3042.0] || -> . % 75.92/76.14 3353[52:Spt:3352.0,3033.2,3041.0] || xuntil6(s42)*+ -> . % 75.92/76.14 3354[52:Spt:3352.0,3033.0,3033.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.14 3355[52:Res:53.1,3354.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.14 3357[52:MRR:3355.0,3025.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.14 3359[52:Res:3357.0,61.1] always3(s43) || -> . % 75.92/76.14 3360[52:SSi:3359.0,732.0] || -> . % 75.92/76.14 3361[51:Spt:3360.0,3029.1,3031.0] || xuntil6(s41)* -> . % 75.92/76.14 3362[51:Spt:3360.0,3029.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.14 3365[51:Res:3362.0,61.1] always3(s41) || -> . % 75.92/76.14 3366[51:SSi:3365.0,730.0,3019.0] || -> . % 75.92/76.14 3367[49:Spt:3366.0,3013.2,3018.0] || xuntil6(s40)*+ -> . % 75.92/76.14 3368[49:Spt:3366.0,3013.0,3013.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.14 3369[49:Res:53.1,3368.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.14 3371[49:MRR:3369.0,3005.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.14 3373[49:Res:3371.0,61.1] always3(s41) || -> . % 75.92/76.14 3374[49:SSi:3373.0,730.0] || -> . % 75.92/76.14 3375[48:Spt:3374.0,3009.1,3011.0] || xuntil6(s39)* -> . % 75.92/76.14 3376[48:Spt:3374.0,3009.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.14 3379[48:Res:3376.0,61.1] always3(s39) || -> . % 75.92/76.14 3380[48:SSi:3379.0,728.0,2999.0] || -> . % 75.92/76.14 3381[46:Spt:3380.0,2996.2,2998.0] || xuntil6(s38)*+ -> . % 75.92/76.14 3382[46:Spt:3380.0,2996.0,2996.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.14 3383[46:Res:53.1,3382.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.14 3385[46:MRR:3383.0,2985.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.14 3388[46:Res:3385.0,61.1] always3(s39) || -> . % 75.92/76.14 3389[46:SSi:3388.0,728.0] || -> . % 75.92/76.14 3390[45:Spt:3389.0,2989.1,2994.0] || xuntil6(s37)* -> . % 75.92/76.14 3391[45:Spt:3389.0,2989.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.14 3394[45:Res:3391.0,61.1] always3(s37) || -> . % 75.92/76.14 3395[45:SSi:3394.0,726.0,2979.0] || -> . % 75.92/76.14 3396[43:Spt:3395.0,2970.2,2978.0] || xuntil6(s36)*+ -> . % 75.92/76.14 3397[43:Spt:3395.0,2970.0,2970.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.14 3398[43:Res:53.1,3397.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.14 3400[43:MRR:3398.0,2962.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.14 3402[43:Res:3400.0,61.1] always3(s37) || -> . % 75.92/76.14 3403[43:SSi:3402.0,726.0] || -> . % 75.92/76.14 3404[42:Spt:3403.0,2966.1,2968.0] || xuntil6(s35)* -> . % 75.92/76.14 3405[42:Spt:3403.0,2966.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.14 3408[42:Res:3405.0,61.1] always3(s35) || -> . % 75.92/76.14 3409[42:SSi:3408.0,724.0,2956.0] || -> . % 75.92/76.14 3410[40:Spt:3409.0,2950.2,2955.0] || xuntil6(s34)*+ -> . % 75.92/76.14 3411[40:Spt:3409.0,2950.0,2950.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 75.92/76.14 3412[40:Res:53.1,3411.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 75.92/76.14 3414[40:MRR:3412.0,2942.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.14 3417[40:Res:3414.0,61.1] always3(s35) || -> . % 75.92/76.14 3418[40:SSi:3417.0,724.0] || -> . % 75.92/76.14 3419[39:Spt:3418.0,2946.1,2948.0] || xuntil6(s33)* -> . % 75.92/76.14 3420[39:Spt:3418.0,2946.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.14 3423[39:Res:3420.0,61.1] always3(s33) || -> . % 75.92/76.14 3424[39:SSi:3423.0,722.0,2933.0] || -> . % 75.92/76.14 3425[37:Spt:3424.0,2931.2,2932.0] || xuntil6(s32)*+ -> . % 75.92/76.14 3426[37:Spt:3424.0,2931.0,2931.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 75.92/76.14 3427[37:Res:53.1,3426.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 75.92/76.14 3430[38:Spt:3427.0] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.14 3432[38:Res:3430.0,61.1] always3(s32) || -> . % 75.92/76.14 3433[38:SSi:3432.0,721.0,2930.0] || -> . % 75.92/76.14 3434[38:Spt:3433.0,3427.0,3430.0] || m_main_v_state(s32,c_busy)* -> . % 75.92/76.14 3435[38:Spt:3433.0,3427.1] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.14 3439[38:Res:3435.0,61.1] always3(s33) || -> . % 75.92/76.14 3440[38:SSi:3439.0,722.0] || -> . % 75.92/76.14 3441[36:Spt:3440.0,2925.2,2929.0] || xuntil6(s31)*+ -> . % 75.92/76.14 3442[36:Spt:3440.0,2925.0,2925.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 75.92/76.14 3443[36:Res:53.1,3442.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 75.92/76.14 3445[37:Spt:3443.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.14 3447[37:Res:3445.0,61.1] always3(s31) || -> . % 75.92/76.14 3448[37:SSi:3447.0,720.0,2924.0] || -> . % 75.92/76.14 3449[37:Spt:3448.0,3443.0,3445.0] || m_main_v_state(s31,c_busy)* -> . % 75.92/76.14 3450[37:Spt:3448.0,3443.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.14 3454[37:Res:3450.0,61.1] always3(s32) || -> . % 75.92/76.14 3455[37:SSi:3454.0,721.0] || -> . % 75.92/76.14 3456[35:Spt:3455.0,2922.2,2923.0] || xuntil6(s30)*+ -> . % 75.92/76.14 3457[35:Spt:3455.0,2922.0,2922.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.14 3458[35:Res:53.1,3457.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.14 3460[36:Spt:3458.0] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.14 3462[36:Res:3460.0,61.1] always3(s30) || -> . % 75.92/76.14 3463[36:SSi:3462.0,719.0,2921.0] || -> . % 75.92/76.14 3464[36:Spt:3463.0,3458.0,3460.0] || m_main_v_state(s30,c_busy)* -> . % 75.92/76.14 3465[36:Spt:3463.0,3458.1] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.14 3469[36:Res:3465.0,61.1] always3(s31) || -> . % 75.92/76.14 3470[36:SSi:3469.0,720.0] || -> . % 75.92/76.14 3471[34:Spt:3470.0,2916.2,2920.0] || xuntil6(s29)*+ -> . % 75.92/76.14 3472[34:Spt:3470.0,2916.0,2916.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 75.92/76.14 3473[34:Res:53.1,3472.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 75.92/76.14 3475[35:Spt:3473.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.14 3477[35:Res:3475.0,61.1] always3(s29) || -> . % 75.92/76.14 3478[35:SSi:3477.0,718.0,2915.0] || -> . % 75.92/76.14 3479[35:Spt:3478.0,3473.0,3475.0] || m_main_v_state(s29,c_busy)* -> . % 75.92/76.14 3480[35:Spt:3478.0,3473.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.14 3484[35:Res:3480.0,61.1] always3(s30) || -> . % 75.92/76.14 3485[35:SSi:3484.0,719.0] || -> . % 75.92/76.14 3486[33:Spt:3485.0,2913.2,2914.0] || xuntil6(s28)*+ -> . % 75.92/76.14 3487[33:Spt:3485.0,2913.0,2913.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.14 3488[33:Res:53.1,3487.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.14 3490[34:Spt:3488.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.14 3492[34:Res:3490.0,61.1] always3(s28) || -> . % 75.92/76.14 3493[34:SSi:3492.0,717.0,2912.0] || -> . % 75.92/76.14 3494[34:Spt:3493.0,3488.0,3490.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.14 3495[34:Spt:3493.0,3488.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.14 3499[34:Res:3495.0,61.1] always3(s29) || -> . % 75.92/76.14 3500[34:SSi:3499.0,718.0] || -> . % 75.92/76.14 3501[32:Spt:3500.0,2907.2,2911.0] || xuntil6(s27)*+ -> . % 75.92/76.14 3502[32:Spt:3500.0,2907.0,2907.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.14 3503[32:Res:53.1,3502.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.14 3505[33:Spt:3503.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.14 3507[33:Res:3505.0,61.1] always3(s27) || -> . % 75.92/76.14 3508[33:SSi:3507.0,716.0,2906.0] || -> . % 75.92/76.14 3509[33:Spt:3508.0,3503.0,3505.0] || m_main_v_state(s27,c_busy)* -> . % 75.92/76.14 3510[33:Spt:3508.0,3503.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.14 3514[33:Res:3510.0,61.1] always3(s28) || -> . % 75.92/76.14 3515[33:SSi:3514.0,717.0] || -> . % 75.92/76.14 3516[31:Spt:3515.0,2904.2,2905.0] || xuntil6(s26)*+ -> . % 75.92/76.14 3517[31:Spt:3515.0,2904.0,2904.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.14 3518[31:Res:53.1,3517.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.14 3520[32:Spt:3518.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.14 3522[32:Res:3520.0,61.1] always3(s26) || -> . % 75.92/76.14 3523[32:SSi:3522.0,715.0,2903.0] || -> . % 75.92/76.14 3524[32:Spt:3523.0,3518.0,3520.0] || m_main_v_state(s26,c_busy)* -> . % 75.92/76.14 3525[32:Spt:3523.0,3518.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.14 3529[32:Res:3525.0,61.1] always3(s27) || -> . % 75.92/76.14 3530[32:SSi:3529.0,716.0] || -> . % 75.92/76.14 3531[30:Spt:3530.0,2898.2,2902.0] || xuntil6(s25)*+ -> . % 75.92/76.14 3532[30:Spt:3530.0,2898.0,2898.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.14 3533[30:Res:53.1,3532.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.14 3535[31:Spt:3533.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.14 3537[31:Res:3535.0,61.1] always3(s25) || -> . % 75.92/76.14 3538[31:SSi:3537.0,714.0,2897.0] || -> . % 75.92/76.14 3539[31:Spt:3538.0,3533.0,3535.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.14 3540[31:Spt:3538.0,3533.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.14 3544[31:Res:3540.0,61.1] always3(s26) || -> . % 75.92/76.14 3545[31:SSi:3544.0,715.0] || -> . % 75.92/76.14 3546[29:Spt:3545.0,2895.2,2896.0] || xuntil6(s24)*+ -> . % 75.92/76.14 3547[29:Spt:3545.0,2895.0,2895.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.14 3548[29:Res:53.1,3547.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.14 3550[30:Spt:3548.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.14 3552[30:Res:3550.0,61.1] always3(s24) || -> . % 75.92/76.14 3553[30:SSi:3552.0,713.0,2894.0] || -> . % 75.92/76.14 3554[30:Spt:3553.0,3548.0,3550.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.14 3555[30:Spt:3553.0,3548.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.14 3559[30:Res:3555.0,61.1] always3(s25) || -> . % 75.92/76.14 3560[30:SSi:3559.0,714.0] || -> . % 75.92/76.14 3561[28:Spt:3560.0,2889.2,2893.0] || xuntil6(s23)*+ -> . % 75.92/76.14 3562[28:Spt:3560.0,2889.0,2889.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.14 3563[28:Res:53.1,3562.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.14 3565[29:Spt:3563.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.14 3567[29:Res:3565.0,61.1] always3(s23) || -> . % 75.92/76.14 3568[29:SSi:3567.0,712.0,2888.0] || -> . % 75.92/76.14 3569[29:Spt:3568.0,3563.0,3565.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.14 3570[29:Spt:3568.0,3563.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.14 3574[29:Res:3570.0,61.1] always3(s24) || -> . % 75.92/76.14 3575[29:SSi:3574.0,713.0] || -> . % 75.92/76.14 3576[27:Spt:3575.0,2886.2,2887.0] || xuntil6(s22)*+ -> . % 75.92/76.14 3577[27:Spt:3575.0,2886.0,2886.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.14 3578[27:Res:53.1,3577.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.14 3583[28:Spt:3578.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.14 3585[28:Res:3583.0,61.1] always3(s22) || -> . % 75.92/76.14 3586[28:SSi:3585.0,711.0,2885.0] || -> . % 75.92/76.14 3587[28:Spt:3586.0,3578.0,3583.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.14 3588[28:Spt:3586.0,3578.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.14 3592[28:Res:3588.0,61.1] always3(s23) || -> . % 75.92/76.14 3593[28:SSi:3592.0,712.0] || -> . % 75.92/76.14 3594[26:Spt:3593.0,2880.2,2884.0] || xuntil6(s21)*+ -> . % 75.92/76.14 3595[26:Spt:3593.0,2880.0,2880.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.14 3596[26:Res:53.1,3595.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.14 3598[27:Spt:3596.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.14 3600[27:Res:3598.0,61.1] always3(s21) || -> . % 75.92/76.14 3601[27:SSi:3600.0,710.0,2879.0] || -> . % 75.92/76.14 3602[27:Spt:3601.0,3596.0,3598.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.14 3603[27:Spt:3601.0,3596.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.14 3607[27:Res:3603.0,61.1] always3(s22) || -> . % 75.92/76.14 3608[27:SSi:3607.0,711.0] || -> . % 75.92/76.14 3609[25:Spt:3608.0,2877.2,2878.0] || xuntil6(s20)*+ -> . % 75.92/76.14 3610[25:Spt:3608.0,2877.0,2877.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.14 3611[25:Res:53.1,3610.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.14 3613[26:Spt:3611.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.14 3615[26:Res:3613.0,61.1] always3(s20) || -> . % 75.92/76.14 3616[26:SSi:3615.0,709.0,2876.0] || -> . % 75.92/76.14 3617[26:Spt:3616.0,3611.0,3613.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.14 3618[26:Spt:3616.0,3611.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.14 3622[26:Res:3618.0,61.1] always3(s21) || -> . % 75.92/76.14 3623[26:SSi:3622.0,710.0] || -> . % 75.92/76.14 3624[24:Spt:3623.0,2871.2,2875.0] || xuntil6(s19)*+ -> . % 75.92/76.14 3625[24:Spt:3623.0,2871.0,2871.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.14 3626[24:Res:53.1,3625.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.14 3631[25:Spt:3626.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.14 3633[25:Res:3631.0,61.1] always3(s19) || -> . % 75.92/76.14 3634[25:SSi:3633.0,708.0,2870.0] || -> . % 75.92/76.14 3635[25:Spt:3634.0,3626.0,3631.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.14 3636[25:Spt:3634.0,3626.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.14 3640[25:Res:3636.0,61.1] always3(s20) || -> . % 75.92/76.14 3641[25:SSi:3640.0,709.0] || -> . % 75.92/76.14 3642[23:Spt:3641.0,2868.2,2869.0] || xuntil6(s18)*+ -> . % 75.92/76.14 3643[23:Spt:3641.0,2868.0,2868.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.14 3644[23:Res:53.1,3643.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.14 3646[24:Spt:3644.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.14 3648[24:Res:3646.0,61.1] always3(s18) || -> . % 75.92/76.14 3649[24:SSi:3648.0,707.0,2867.0] || -> . % 75.92/76.14 3650[24:Spt:3649.0,3644.0,3646.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.14 3651[24:Spt:3649.0,3644.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.14 3655[24:Res:3651.0,61.1] always3(s19) || -> . % 75.92/76.14 3656[24:SSi:3655.0,708.0] || -> . % 75.92/76.14 3657[22:Spt:3656.0,2862.2,2866.0] || xuntil6(s17)*+ -> . % 75.92/76.14 3658[22:Spt:3656.0,2862.0,2862.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.14 3659[22:Res:53.1,3658.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.14 3661[23:Spt:3659.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.14 3663[23:Res:3661.0,61.1] always3(s17) || -> . % 75.92/76.14 3664[23:SSi:3663.0,706.0,2861.0] || -> . % 75.92/76.14 3665[23:Spt:3664.0,3659.0,3661.0] || m_main_v_state(s17,c_busy)* -> . % 75.92/76.14 3666[23:Spt:3664.0,3659.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.14 3670[23:Res:3666.0,61.1] always3(s18) || -> . % 75.92/76.14 3671[23:SSi:3670.0,707.0] || -> . % 75.92/76.14 3672[21:Spt:3671.0,2859.2,2860.0] || xuntil6(s16)*+ -> . % 75.92/76.14 3673[21:Spt:3671.0,2859.0,2859.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.14 3674[21:Res:53.1,3673.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.14 3679[22:Spt:3674.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.14 3681[22:Res:3679.0,61.1] always3(s16) || -> . % 75.92/76.14 3682[22:SSi:3681.0,705.0,2858.0] || -> . % 75.92/76.14 3683[22:Spt:3682.0,3674.0,3679.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.14 3684[22:Spt:3682.0,3674.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.14 3688[22:Res:3684.0,61.1] always3(s17) || -> . % 75.92/76.14 3689[22:SSi:3688.0,706.0] || -> . % 75.92/76.14 3690[20:Spt:3689.0,2853.2,2857.0] || xuntil6(s15)*+ -> . % 75.92/76.14 3691[20:Spt:3689.0,2853.0,2853.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.14 3692[20:Res:53.1,3691.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.14 3694[21:Spt:3692.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.14 3696[21:Res:3694.0,61.1] always3(s15) || -> . % 75.92/76.14 3697[21:SSi:3696.0,704.0,2852.0] || -> . % 75.92/76.14 3698[21:Spt:3697.0,3692.0,3694.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.14 3699[21:Spt:3697.0,3692.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.14 3703[21:Res:3699.0,61.1] always3(s16) || -> . % 75.92/76.14 3704[21:SSi:3703.0,705.0] || -> . % 75.92/76.14 3705[19:Spt:3704.0,2850.2,2851.0] || xuntil6(s14)*+ -> . % 75.92/76.14 3706[19:Spt:3704.0,2850.0,2850.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.14 3707[19:Res:53.1,3706.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.14 3709[20:Spt:3707.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.14 3711[20:Res:3709.0,61.1] always3(s14) || -> . % 75.92/76.14 3712[20:SSi:3711.0,703.0,2849.0] || -> . % 75.92/76.14 3713[20:Spt:3712.0,3707.0,3709.0] || m_main_v_state(s14,c_busy)* -> . % 75.92/76.14 3714[20:Spt:3712.0,3707.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.14 3718[20:Res:3714.0,61.1] always3(s15) || -> . % 75.92/76.14 3719[20:SSi:3718.0,704.0] || -> . % 75.92/76.14 3720[18:Spt:3719.0,2844.2,2848.0] || xuntil6(s13)*+ -> . % 75.92/76.14 3721[18:Spt:3719.0,2844.0,2844.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.14 3722[18:Res:53.1,3721.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.14 3727[19:Spt:3722.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.14 3729[19:Res:3727.0,61.1] always3(s13) || -> . % 75.92/76.14 3730[19:SSi:3729.0,702.0,2843.0] || -> . % 75.92/76.14 3731[19:Spt:3730.0,3722.0,3727.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.14 3732[19:Spt:3730.0,3722.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.14 3736[19:Res:3732.0,61.1] always3(s14) || -> . % 75.92/76.14 3737[19:SSi:3736.0,703.0] || -> . % 75.92/76.14 3738[17:Spt:3737.0,2841.2,2842.0] || xuntil6(s12)*+ -> . % 75.92/76.14 3739[17:Spt:3737.0,2841.0,2841.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.14 3740[17:Res:53.1,3739.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.14 3742[18:Spt:3740.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.14 3744[18:Res:3742.0,61.1] always3(s12) || -> . % 75.92/76.14 3745[18:SSi:3744.0,701.0,2840.0] || -> . % 75.92/76.14 3746[18:Spt:3745.0,3740.0,3742.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.14 3747[18:Spt:3745.0,3740.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.14 3751[18:Res:3747.0,61.1] always3(s13) || -> . % 75.92/76.14 3752[18:SSi:3751.0,702.0] || -> . % 75.92/76.14 3753[16:Spt:3752.0,2835.2,2839.0] || xuntil6(s11)*+ -> . % 75.92/76.14 3754[16:Spt:3752.0,2835.0,2835.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.14 3755[16:Res:53.1,3754.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.14 3757[17:Spt:3755.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.14 3759[17:Res:3757.0,61.1] always3(s11) || -> . % 75.92/76.14 3760[17:SSi:3759.0,700.0,2834.0] || -> . % 75.92/76.14 3761[17:Spt:3760.0,3755.0,3757.0] || m_main_v_state(s11,c_busy)* -> . % 75.92/76.14 3762[17:Spt:3760.0,3755.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.14 3766[17:Res:3762.0,61.1] always3(s12) || -> . % 75.92/76.14 3767[17:SSi:3766.0,701.0] || -> . % 75.92/76.14 3768[15:Spt:3767.0,2832.2,2833.0] || xuntil6(s10)*+ -> . % 75.92/76.14 3769[15:Spt:3767.0,2832.0,2832.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.14 3770[15:Res:53.1,3769.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.14 3775[16:Spt:3770.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.14 3777[16:Res:3775.0,61.1] always3(s10) || -> . % 75.92/76.14 3778[16:SSi:3777.0,699.0,2831.0] || -> . % 75.92/76.14 3779[16:Spt:3778.0,3770.0,3775.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.14 3780[16:Spt:3778.0,3770.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.14 3784[16:Res:3780.0,61.1] always3(s11) || -> . % 75.92/76.14 3785[16:SSi:3784.0,700.0] || -> . % 75.92/76.14 3786[14:Spt:3785.0,2826.2,2830.0] || xuntil6(s9)*+ -> . % 75.92/76.14 3787[14:Spt:3785.0,2826.0,2826.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.14 3788[14:Res:53.1,3787.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.14 3790[15:Spt:3788.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.14 3792[15:Res:3790.0,61.1] always3(s9) || -> . % 75.92/76.14 3793[15:SSi:3792.0,698.0,2825.0] || -> . % 75.92/76.14 3794[15:Spt:3793.0,3788.0,3790.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.14 3795[15:Spt:3793.0,3788.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.14 3799[15:Res:3795.0,61.1] always3(s10) || -> . % 75.92/76.14 3800[15:SSi:3799.0,699.0] || -> . % 75.92/76.14 3801[13:Spt:3800.0,2823.2,2824.0] || xuntil6(s8)*+ -> . % 75.92/76.14 3802[13:Spt:3800.0,2823.0,2823.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.14 3803[13:Res:53.1,3802.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.14 3805[14:Spt:3803.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.14 3807[14:Res:3805.0,61.1] always3(s8) || -> . % 75.92/76.14 3808[14:SSi:3807.0,697.0,2822.0] || -> . % 75.92/76.14 3809[14:Spt:3808.0,3803.0,3805.0] || m_main_v_state(s8,c_busy)* -> . % 75.92/76.14 3810[14:Spt:3808.0,3803.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.14 3814[14:Res:3810.0,61.1] always3(s9) || -> . % 75.92/76.14 3815[14:SSi:3814.0,698.0] || -> . % 75.92/76.14 3816[12:Spt:3815.0,2817.2,2821.0] || xuntil6(s7)*+ -> . % 75.92/76.14 3817[12:Spt:3815.0,2817.0,2817.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.14 3818[12:Res:53.1,3817.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.14 3823[13:Spt:3818.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.14 3825[13:Res:3823.0,61.1] always3(s7) || -> . % 75.92/76.14 3826[13:SSi:3825.0,696.0,2816.0] || -> . % 75.92/76.14 3827[13:Spt:3826.0,3818.0,3823.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.14 3828[13:Spt:3826.0,3818.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.14 3832[13:Res:3828.0,61.1] always3(s8) || -> . % 75.92/76.14 3833[13:SSi:3832.0,697.0] || -> . % 75.92/76.14 3834[11:Spt:3833.0,2814.2,2815.0] || xuntil6(s6)*+ -> . % 75.92/76.14 3835[11:Spt:3833.0,2814.0,2814.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.14 3836[11:Res:53.1,3835.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.14 3838[12:Spt:3836.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.14 3840[12:Res:3838.0,61.1] always3(s6) || -> . % 75.92/76.14 3841[12:SSi:3840.0,695.0,2813.0] || -> . % 75.92/76.14 3842[12:Spt:3841.0,3836.0,3838.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.14 3843[12:Spt:3841.0,3836.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.14 3847[12:Res:3843.0,61.1] always3(s7) || -> . % 75.92/76.14 3848[12:SSi:3847.0,696.0] || -> . % 75.92/76.14 3849[10:Spt:3848.0,2808.2,2812.0] || xuntil6(s5)*+ -> . % 75.92/76.14 3850[10:Spt:3848.0,2808.0,2808.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.14 3851[10:Res:53.1,3850.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.14 3853[11:Spt:3851.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.14 3855[11:Res:3853.0,61.1] always3(s5) || -> . % 75.92/76.14 3856[11:SSi:3855.0,694.0,2807.0] || -> . % 75.92/76.14 3857[11:Spt:3856.0,3851.0,3853.0] || m_main_v_state(s5,c_busy)* -> . % 75.92/76.14 3858[11:Spt:3856.0,3851.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.14 3862[11:Res:3858.0,61.1] always3(s6) || -> . % 75.92/76.14 3863[11:SSi:3862.0,695.0] || -> . % 75.92/76.14 3864[9:Spt:3863.0,2805.2,2806.0] || xuntil6(s4)*+ -> . % 75.92/76.14 3865[9:Spt:3863.0,2805.0,2805.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.14 3866[9:Res:53.1,3865.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.14 3871[10:Spt:3866.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.14 3873[10:Res:3871.0,61.1] always3(s4) || -> . % 75.92/76.14 3874[10:SSi:3873.0,693.0,2804.0] || -> . % 75.92/76.14 3875[10:Spt:3874.0,3866.0,3871.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.14 3876[10:Spt:3874.0,3866.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.14 3880[10:Res:3876.0,61.1] always3(s5) || -> . % 75.92/76.14 3881[10:SSi:3880.0,694.0] || -> . % 75.92/76.14 3882[8:Spt:3881.0,2802.2,2803.0] || xuntil6(s3)*+ -> . % 75.92/76.14 3883[8:Spt:3881.0,2802.0,2802.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.14 3884[8:Res:53.1,3883.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.14 3886[9:Spt:3884.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.14 3888[9:Res:3886.0,61.1] always3(s3) || -> . % 75.92/76.14 3889[9:SSi:3888.0,692.0,2801.0] || -> . % 75.92/76.14 3890[9:Spt:3889.0,3884.0,3886.0] || m_main_v_state(s3,c_busy)* -> . % 75.92/76.14 3891[9:Spt:3889.0,3884.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.14 3895[9:Res:3891.0,61.1] always3(s4) || -> . % 75.92/76.14 3896[9:SSi:3895.0,693.0] || -> . % 75.92/76.14 3897[7:Spt:3896.0,2799.2,2800.0] || xuntil6(s2)*+ -> . % 75.92/76.14 3898[7:Spt:3896.0,2799.0,2799.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.14 3899[7:Res:53.1,3898.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.14 3901[8:Spt:3899.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.14 3903[8:Res:3901.0,61.1] always3(s2) || -> . % 75.92/76.14 3904[8:SSi:3903.0,691.0,2798.0] || -> . % 75.92/76.14 3905[8:Spt:3904.0,3899.0,3901.0] || m_main_v_state(s2,c_busy)* -> . % 75.92/76.14 3906[8:Spt:3904.0,3899.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.14 3910[8:Res:3906.0,61.1] always3(s3) || -> . % 75.92/76.14 3911[8:SSi:3910.0,692.0] || -> . % 75.92/76.14 3912[6:Spt:3911.0,2793.2,2797.0] || xuntil6(s1)*+ -> . % 75.92/76.14 3913[6:Spt:3911.0,2793.0,2793.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.14 3914[6:Res:53.1,3913.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.14 3919[7:Spt:3914.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.14 3921[7:Res:3919.0,61.1] always3(s1) || -> . % 75.92/76.14 3922[7:SSi:3921.0,690.0,2792.0] || -> . % 75.92/76.14 3923[7:Spt:3922.0,3914.0,3919.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.14 3924[7:Spt:3922.0,3914.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.14 3929[7:Res:3924.0,61.1] always3(s2) || -> . % 75.92/76.14 3930[7:SSi:3929.0,691.0] || -> . % 75.92/76.14 3931[5:Spt:3930.0,74.0,2791.0] || xuntil6(s0)*+ -> . % 75.92/76.14 3932[5:Spt:3930.0,74.1] || -> node4(s0)*. % 75.92/76.14 3933[5:MRR:758.1,3931.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.14 3935[5:Res:3933.0,61.1] always3(s1) || -> . % 75.92/76.14 3936[5:SSi:3935.0,690.0] || -> . % 75.92/76.14 3937[4:Spt:3936.0,2781.0,2785.0] || trans(s49,s47)*+ -> . % 75.92/76.14 3938[4:Spt:3936.0,2781.1,2781.2,2781.3,2781.4,2781.5,2781.6,2781.7,2781.8,2781.9,2781.10,2781.11,2781.12,2781.13,2781.14,2781.15,2781.16,2781.17,2781.18,2781.19,2781.20,2781.21,2781.22,2781.23,2781.24,2781.25,2781.26,2781.27,2781.28,2781.29,2781.30,2781.31,2781.32,2781.33,2781.34,2781.35,2781.36,2781.37,2781.38,2781.39,2781.40,2781.41,2781.42,2781.43,2781.44,2781.45,2781.46,2781.47] || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.14 3939[4:MRR:2783.0,3937.0] || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.14 3941[4:MRR:2784.1,3937.0] xuntil6(s49) || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.14 3942[5:Spt:3938.0] || -> trans(s49,s46)*. % 75.92/76.14 3943[5:Res:3942.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s46)*. % 75.92/76.14 3945[5:Res:3942.0,60.0] || -> node2(s49,s46)*. % 75.92/76.14 3946[5:SSi:3943.1,50.0,738.0] xuntil6(s49) || -> until2p7(s46)*. % 75.92/76.14 3947[5:Res:3945.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)*. % 75.92/76.14 3948[6:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.14 3949[6:MRR:176.0,3948.0] || -> until5(s1)*. % 75.92/76.14 3950[6:MRR:3224.0,3949.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.14 3954[7:Spt:3950.2] || -> xuntil6(s1)*. % 75.92/76.14 3955[7:MRR:175.0,3954.0] || -> until5(s2)*. % 75.92/76.14 3956[7:MRR:3220.0,3955.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.14 3957[8:Spt:3956.2] || -> xuntil6(s2)*. % 75.92/76.14 3958[8:MRR:174.0,3957.0] || -> until5(s3)*. % 75.92/76.14 3959[8:MRR:3216.0,3958.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.14 3960[9:Spt:3959.2] || -> xuntil6(s3)*. % 75.92/76.14 3961[9:MRR:173.0,3960.0] || -> until5(s4)*. % 75.92/76.14 3962[9:MRR:3212.0,3961.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.14 3963[10:Spt:3962.2] || -> xuntil6(s4)*. % 75.92/76.14 3964[10:MRR:172.0,3963.0] || -> until5(s5)*. % 75.92/76.14 3965[10:MRR:3211.0,3964.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.14 3969[11:Spt:3965.2] || -> xuntil6(s5)*. % 75.92/76.14 3970[11:MRR:171.0,3969.0] || -> until5(s6)*. % 75.92/76.14 3971[11:MRR:3204.0,3970.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.14 3972[12:Spt:3971.2] || -> xuntil6(s6)*. % 75.92/76.14 3973[12:MRR:170.0,3972.0] || -> until5(s7)*. % 75.92/76.14 3974[12:MRR:3200.0,3973.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.14 3978[13:Spt:3974.2] || -> xuntil6(s7)*. % 75.92/76.14 3979[13:MRR:169.0,3978.0] || -> until5(s8)*. % 75.92/76.14 3980[13:MRR:3196.0,3979.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.14 3981[14:Spt:3980.2] || -> xuntil6(s8)*. % 75.92/76.14 3982[14:MRR:168.0,3981.0] || -> until5(s9)*. % 75.92/76.14 3983[14:MRR:3192.0,3982.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.14 3987[15:Spt:3983.2] || -> xuntil6(s9)*. % 75.92/76.14 3988[15:MRR:167.0,3987.0] || -> until5(s10)*. % 75.92/76.14 3989[15:MRR:3191.0,3988.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.14 3990[16:Spt:3989.2] || -> xuntil6(s10)*. % 75.92/76.14 3991[16:MRR:166.0,3990.0] || -> until5(s11)*. % 75.92/76.14 3992[16:MRR:3184.0,3991.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.14 3996[17:Spt:3992.2] || -> xuntil6(s11)*. % 75.92/76.14 3997[17:MRR:165.0,3996.0] || -> until5(s12)*. % 75.92/76.14 3998[17:MRR:3180.0,3997.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.14 3999[18:Spt:3998.2] || -> xuntil6(s12)*. % 75.92/76.14 4000[18:MRR:164.0,3999.0] || -> until5(s13)*. % 75.92/76.14 4001[18:MRR:3176.0,4000.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.14 4005[19:Spt:4001.2] || -> xuntil6(s13)*. % 75.92/76.14 4006[19:MRR:163.0,4005.0] || -> until5(s14)*. % 75.92/76.14 4007[19:MRR:3172.0,4006.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.14 4008[20:Spt:4007.2] || -> xuntil6(s14)*. % 75.92/76.14 4009[20:MRR:162.0,4008.0] || -> until5(s15)*. % 75.92/76.14 4010[20:MRR:3171.0,4009.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.14 4014[21:Spt:4010.2] || -> xuntil6(s15)*. % 75.92/76.14 4015[21:MRR:161.0,4014.0] || -> until5(s16)*. % 75.92/76.14 4016[21:MRR:3164.0,4015.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.14 4017[22:Spt:4016.2] || -> xuntil6(s16)*. % 75.92/76.14 4018[22:MRR:160.0,4017.0] || -> until5(s17)*. % 75.92/76.14 4019[22:MRR:3160.0,4018.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.14 4023[23:Spt:4019.2] || -> xuntil6(s17)*. % 75.92/76.14 4024[23:MRR:159.0,4023.0] || -> until5(s18)*. % 75.92/76.14 4025[23:MRR:3156.0,4024.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.14 4026[24:Spt:4025.2] || -> xuntil6(s18)*. % 75.92/76.14 4027[24:MRR:158.0,4026.0] || -> until5(s19)*. % 75.92/76.14 4028[24:MRR:3152.0,4027.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.14 4032[25:Spt:4028.2] || -> xuntil6(s19)*. % 75.92/76.14 4033[25:MRR:157.0,4032.0] || -> until5(s20)*. % 75.92/76.14 4034[25:MRR:3151.0,4033.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.14 4035[26:Spt:4034.2] || -> xuntil6(s20)*. % 75.92/76.14 4036[26:MRR:156.0,4035.0] || -> until5(s21)*. % 75.92/76.14 4037[26:MRR:3144.0,4036.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.14 4041[27:Spt:4037.2] || -> xuntil6(s21)*. % 75.92/76.14 4042[27:MRR:155.0,4041.0] || -> until5(s22)*. % 75.92/76.14 4043[27:MRR:3140.0,4042.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.14 4044[28:Spt:4043.2] || -> xuntil6(s22)*. % 75.92/76.14 4045[28:MRR:154.0,4044.0] || -> until5(s23)*. % 75.92/76.14 4046[28:MRR:3136.0,4045.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.14 4050[29:Spt:4046.2] || -> xuntil6(s23)*. % 75.92/76.14 4051[29:MRR:153.0,4050.0] || -> until5(s24)*. % 75.92/76.14 4052[29:MRR:3132.0,4051.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.14 4053[30:Spt:4052.2] || -> xuntil6(s24)*. % 75.92/76.14 4054[30:MRR:152.0,4053.0] || -> until5(s25)*. % 75.92/76.14 4055[30:MRR:3131.0,4054.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.14 4059[31:Spt:4055.2] || -> xuntil6(s25)*. % 75.92/76.14 4060[31:MRR:151.0,4059.0] || -> until5(s26)*. % 75.92/76.14 4061[31:MRR:3124.0,4060.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.14 4062[32:Spt:4061.2] || -> xuntil6(s26)*. % 75.92/76.14 4063[32:MRR:150.0,4062.0] || -> until5(s27)*. % 75.92/76.14 4064[32:MRR:3120.0,4063.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.14 4068[33:Spt:4064.2] || -> xuntil6(s27)*. % 75.92/76.14 4069[33:MRR:149.0,4068.0] || -> until5(s28)*. % 75.92/76.14 4070[33:MRR:3116.0,4069.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.14 4071[34:Spt:4070.2] || -> xuntil6(s28)*. % 75.92/76.14 4072[34:MRR:148.0,4071.0] || -> until5(s29)*. % 75.92/76.14 4073[34:MRR:3112.0,4072.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.14 4077[35:Spt:4073.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.14 4079[35:Res:4077.0,61.1] always3(s30) || -> . % 75.92/76.14 4080[35:SSi:4079.0,719.0] || -> . % 75.92/76.14 4081[35:Spt:4080.0,4073.1,4077.0] || m_main_v_state(s30,c_busy)*+ -> . % 75.92/76.14 4082[35:Spt:4080.0,4073.0,4073.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 75.92/76.14 4085[35:Res:53.1,4082.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 75.92/76.14 4087[36:Spt:4085.1] || -> xuntil6(s29)*. % 75.92/76.14 4088[36:MRR:147.0,4087.0] || -> until5(s30)*. % 75.92/76.14 4089[36:MRR:3111.0,4088.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.14 4094[37:Spt:4089.2] || -> xuntil6(s30)*. % 75.92/76.14 4095[37:MRR:146.0,4094.0] || -> until5(s31)*. % 75.92/76.14 4096[37:MRR:3107.0,4095.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.14 4097[38:Spt:4096.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.14 4099[38:Res:4097.0,61.1] always3(s32) || -> . % 75.92/76.14 4100[38:SSi:4099.0,721.0] || -> . % 75.92/76.14 4101[38:Spt:4100.0,4096.1,4097.0] || m_main_v_state(s32,c_busy)*+ -> . % 75.92/76.14 4102[38:Spt:4100.0,4096.0,4096.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 75.92/76.14 4105[38:Res:53.1,4102.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 75.92/76.14 4107[39:Spt:4105.1] || -> xuntil6(s31)*. % 75.92/76.14 4108[39:MRR:145.0,4107.0] || -> until5(s32)*. % 75.92/76.14 4109[39:MRR:3106.0,4108.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.14 4117[40:Spt:4109.2] || -> xuntil6(s32)*. % 75.92/76.14 4118[40:MRR:144.0,4117.0] || -> until5(s33)*. % 75.92/76.14 4119[40:MRR:932.0,4118.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.14 4120[41:Spt:4119.1] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.14 4122[41:Res:4120.0,61.1] always3(s34) || -> . % 75.92/76.14 4123[41:SSi:4122.0,723.0] || -> . % 75.92/76.14 4124[41:Spt:4123.0,4119.1,4120.0] || m_main_v_state(s34,c_busy)*+ -> . % 75.92/76.14 4125[41:Spt:4123.0,4119.0,4119.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 75.92/76.14 4128[41:Res:53.1,4125.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 75.92/76.14 4133[42:Spt:4128.1] || -> xuntil6(s33)*. % 75.92/76.14 4134[42:MRR:143.0,4133.0] || -> until5(s34)*. % 75.92/76.14 4135[42:MRR:3231.0,4134.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.14 4137[43:Spt:4135.2] || -> xuntil6(s34)*. % 75.92/76.14 4138[43:MRR:142.0,4137.0] || -> until5(s35)*. % 75.92/76.14 4139[43:MRR:930.0,4138.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.14 4140[44:Spt:4139.1] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.14 4142[44:Res:4140.0,61.1] always3(s36) || -> . % 75.92/76.14 4143[44:SSi:4142.0,725.0] || -> . % 75.92/76.14 4144[44:Spt:4143.0,4139.1,4140.0] || m_main_v_state(s36,c_busy)*+ -> . % 75.92/76.14 4145[44:Spt:4143.0,4139.0,4139.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 75.92/76.14 4148[44:Res:53.1,4145.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 75.92/76.14 4150[45:Spt:4148.1] || -> xuntil6(s35)*. % 75.92/76.14 4151[45:MRR:141.0,4150.0] || -> until5(s36)*. % 75.92/76.14 4152[45:MRR:3235.0,4151.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.14 4157[46:Spt:4152.2] || -> xuntil6(s36)*. % 75.92/76.14 4158[46:MRR:140.0,4157.0] || -> until5(s37)*. % 75.92/76.14 4159[46:MRR:928.0,4158.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.14 4160[47:Spt:4159.1] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.14 4162[47:Res:4160.0,61.1] always3(s38) || -> . % 75.92/76.14 4163[47:SSi:4162.0,727.0] || -> . % 75.92/76.14 4164[47:Spt:4163.0,4159.1,4160.0] || m_main_v_state(s38,c_busy)*+ -> . % 75.92/76.14 4165[47:Spt:4163.0,4159.0,4159.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 75.92/76.14 4168[47:Res:53.1,4165.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 75.92/76.14 4170[48:Spt:4168.1] || -> xuntil6(s37)*. % 75.92/76.14 4171[48:MRR:139.0,4170.0] || -> until5(s38)*. % 75.92/76.14 4172[48:MRR:3242.0,4171.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.14 4180[49:Spt:4172.2] || -> xuntil6(s38)*. % 75.92/76.14 4181[49:MRR:138.0,4180.0] || -> until5(s39)*. % 75.92/76.14 4182[49:MRR:926.0,4181.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.14 4183[50:Spt:4182.1] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.14 4185[50:Res:4183.0,61.1] always3(s40) || -> . % 75.92/76.14 4186[50:SSi:4185.0,729.0] || -> . % 75.92/76.14 4187[50:Spt:4186.0,4182.1,4183.0] || m_main_v_state(s40,c_busy)*+ -> . % 75.92/76.14 4188[50:Spt:4186.0,4182.0,4182.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 75.92/76.14 4191[50:Res:53.1,4188.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 75.92/76.14 4196[51:Spt:4191.1] || -> xuntil6(s39)*. % 75.92/76.14 4197[51:MRR:137.0,4196.0] || -> until5(s40)*. % 75.92/76.14 4198[51:MRR:3243.0,4197.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.14 4200[52:Spt:4198.2] || -> xuntil6(s40)*. % 75.92/76.14 4201[52:MRR:136.0,4200.0] || -> until5(s41)*. % 75.92/76.14 4202[52:MRR:924.0,4201.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.14 4203[53:Spt:4202.1] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.14 4205[53:Res:4203.0,61.1] always3(s42) || -> . % 75.92/76.14 4206[53:SSi:4205.0,731.0] || -> . % 75.92/76.14 4207[53:Spt:4206.0,4202.1,4203.0] || m_main_v_state(s42,c_busy)*+ -> . % 75.92/76.14 4208[53:Spt:4206.0,4202.0,4202.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 75.92/76.14 4211[53:Res:53.1,4208.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 75.92/76.14 4213[54:Spt:4211.1] || -> xuntil6(s41)*. % 75.92/76.14 4214[54:MRR:135.0,4213.0] || -> until5(s42)*. % 75.92/76.14 4215[54:MRR:3247.0,4214.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.14 4220[55:Spt:4215.2] || -> xuntil6(s42)*. % 75.92/76.14 4221[55:MRR:134.0,4220.0] || -> until5(s43)*. % 75.92/76.14 4222[55:MRR:922.0,4221.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.14 4223[56:Spt:4222.1] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.14 4225[56:Res:4223.0,61.1] always3(s44) || -> . % 75.92/76.14 4226[56:SSi:4225.0,733.0] || -> . % 75.92/76.14 4227[56:Spt:4226.0,4222.1,4223.0] || m_main_v_state(s44,c_busy)*+ -> . % 75.92/76.14 4228[56:Spt:4226.0,4222.0,4222.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 75.92/76.14 4231[56:Res:53.1,4228.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 75.92/76.14 4233[57:Spt:4231.1] || -> xuntil6(s43)*. % 75.92/76.14 4234[57:MRR:133.0,4233.0] || -> until5(s44)*. % 75.92/76.14 4235[57:MRR:3251.0,4234.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.14 4243[58:Spt:4235.2] || -> xuntil6(s44)*. % 75.92/76.14 4244[58:MRR:132.0,4243.0] || -> until5(s45)*. % 75.92/76.14 4245[58:MRR:920.0,4244.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.14 4246[59:Spt:4245.1] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.14 4248[59:Res:4246.0,61.1] always3(s46) || -> . % 75.92/76.14 4249[59:SSi:4248.0,735.0] || -> . % 75.92/76.14 4250[59:Spt:4249.0,4245.1,4246.0] || m_main_v_state(s46,c_busy)*+ -> . % 75.92/76.14 4251[59:Spt:4249.0,4245.0,4245.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 75.92/76.14 4254[59:MRR:3947.2,4250.0] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.14 4255[59:Res:53.1,4251.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 75.92/76.14 4260[60:Spt:4255.1] || -> xuntil6(s45)*. % 75.92/76.14 4261[60:MRR:131.0,4260.0] || -> until5(s46)*. % 75.92/76.14 4262[60:MRR:3255.0,4261.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.14 4265[59:SoR:4254.0,64.1] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.14 4270[59:SoR:4265.0,66.2] until5(s49) || m_main_v_state(s49,c_ready)* -> xuntil6(s49). % 75.92/76.14 4271[61:Spt:4262.2] || -> xuntil6(s46)*. % 75.92/76.14 4272[61:MRR:130.0,4271.0] || -> until5(s47)*. % 75.92/76.14 4273[61:MRR:918.0,4272.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.14 4277[62:Spt:4273.1] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.14 4279[62:Res:4277.0,61.1] always3(s48) || -> . % 75.92/76.14 4280[62:SSi:4279.0,737.0] || -> . % 75.92/76.14 4281[62:Spt:4280.0,4273.1,4277.0] || m_main_v_state(s48,c_busy)*+ -> . % 75.92/76.14 4282[62:Spt:4280.0,4273.0,4273.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 75.92/76.14 4284[62:MRR:777.2,4281.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 75.92/76.14 4285[62:Res:53.1,4282.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 75.92/76.14 4287[63:Spt:4285.1] || -> xuntil6(s47)*. % 75.92/76.14 4288[63:MRR:129.0,4287.0] || -> until5(s48)*. % 75.92/76.14 4289[63:MRR:3259.0,4288.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.14 4294[64:Spt:4289.2] || -> xuntil6(s48)*. % 75.92/76.14 4295[64:MRR:128.0,4294.0] || -> until5(s49)*. % 75.92/76.14 4296[64:MRR:4270.0,4295.0] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.14 4297[64:Res:53.1,4296.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.14 4302[65:Spt:4297.1] || -> xuntil6(s49)*. % 75.92/76.14 4303[65:MRR:3946.0,4302.0] || -> until2p7(s46)*. % 75.92/76.14 4304[65:MRR:549.0,4303.0] || -> until2p7(s47)* node4(s46). % 75.92/76.14 4305[66:Spt:4304.0] || -> until2p7(s47)*. % 75.92/76.14 4306[66:MRR:554.0,4305.0] || -> until2p7(s48)* node4(s47). % 75.92/76.14 4307[67:Spt:4306.0] || -> until2p7(s48)*. % 75.92/76.14 4308[67:MRR:559.0,4307.0] || -> until2p7(s49)* node4(s48). % 75.92/76.14 4309[68:Spt:4308.0] || -> until2p7(s49)*. % 75.92/76.14 4310[68:MRR:194.0,4309.0] || -> node4(s49)*. % 75.92/76.14 4311[68:MRR:4265.0,4310.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.14 4312[68:Res:53.1,4311.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 4315[68:Res:4312.0,61.1] always3(s49) || -> . % 75.92/76.14 4316[68:SSi:4315.0,50.0,738.0,4295.0,4302.0,4309.0,4310.0] || -> . % 75.92/76.14 4317[68:Spt:4316.0,4308.0,4309.0] || until2p7(s49)*+ -> . % 75.92/76.14 4318[68:Spt:4316.0,4308.1] || -> node4(s48)*. % 75.92/76.14 4320[68:MRR:774.0,4318.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.14 4326[68:Res:53.1,4320.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.14 4328[68:MRR:4326.0,4281.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 4333[68:Res:4328.0,61.1] always3(s49) || -> . % 75.92/76.14 4334[68:SSi:4333.0,50.0,738.0,4295.0,4302.0] || -> . % 75.92/76.14 4335[67:Spt:4334.0,4306.0,4307.0] || until2p7(s48)*+ -> . % 75.92/76.14 4336[67:Spt:4334.0,4306.1] || -> node4(s47)*. % 75.92/76.14 4337[67:MRR:4284.0,4336.0] || m_main_v_state(s47,c_ready)*+ -> . % 75.92/76.14 4340[67:Res:53.1,4337.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.14 4344[67:Res:4340.0,61.1] always3(s47) || -> . % 75.92/76.14 4345[67:SSi:4344.0,736.0,4272.0,4287.0,4305.0,4336.0] || -> . % 75.92/76.14 4346[66:Spt:4345.0,4304.0,4305.0] || until2p7(s47)*+ -> . % 75.92/76.14 4347[66:Spt:4345.0,4304.1] || -> node4(s46)*. % 75.92/76.14 4349[66:MRR:780.0,4347.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.14 4360[66:Res:53.1,4349.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.14 4362[66:MRR:4360.0,4250.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.14 4364[66:Res:4362.0,61.1] always3(s47) || -> . % 75.92/76.14 4365[66:SSi:4364.0,736.0,4272.0,4287.0] || -> . % 75.92/76.14 4366[65:Spt:4365.0,4297.1,4302.0] || xuntil6(s49)* -> . % 75.92/76.14 4367[65:Spt:4365.0,4297.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 4370[65:Res:4367.0,61.1] always3(s49) || -> . % 75.92/76.14 4371[65:SSi:4370.0,50.0,738.0,4295.0] || -> . % 75.92/76.14 4372[64:Spt:4371.0,4289.2,4294.0] || xuntil6(s48)*+ -> . % 75.92/76.14 4373[64:Spt:4371.0,4289.0,4289.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.14 4374[64:Res:53.1,4373.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.14 4376[64:MRR:4374.0,4281.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.14 4378[64:Res:4376.0,61.1] always3(s49) || -> . % 75.92/76.14 4379[64:SSi:4378.0,50.0,738.0] || -> . % 75.92/76.14 4380[63:Spt:4379.0,4285.1,4287.0] || xuntil6(s47)* -> . % 75.92/76.14 4381[63:Spt:4379.0,4285.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.14 4384[63:Res:4381.0,61.1] always3(s47) || -> . % 75.92/76.14 4385[63:SSi:4384.0,736.0,4272.0] || -> . % 75.92/76.14 4386[61:Spt:4385.0,4262.2,4271.0] || xuntil6(s46)*+ -> . % 75.92/76.14 4387[61:Spt:4385.0,4262.0,4262.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.14 4388[61:Res:53.1,4387.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.14 4390[61:MRR:4388.0,4250.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.14 4392[61:Res:4390.0,61.1] always3(s47) || -> . % 75.92/76.14 4393[61:SSi:4392.0,736.0] || -> . % 75.92/76.14 4394[60:Spt:4393.0,4255.1,4260.0] || xuntil6(s45)* -> . % 75.92/76.14 4395[60:Spt:4393.0,4255.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.14 4398[60:Res:4395.0,61.1] always3(s45) || -> . % 75.92/76.14 4399[60:SSi:4398.0,734.0,4244.0] || -> . % 75.92/76.14 4400[58:Spt:4399.0,4235.2,4243.0] || xuntil6(s44)*+ -> . % 75.92/76.14 4401[58:Spt:4399.0,4235.0,4235.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.14 4402[58:Res:53.1,4401.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.14 4404[58:MRR:4402.0,4227.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.14 4406[58:Res:4404.0,61.1] always3(s45) || -> . % 75.92/76.14 4407[58:SSi:4406.0,734.0] || -> . % 75.92/76.14 4408[57:Spt:4407.0,4231.1,4233.0] || xuntil6(s43)* -> . % 75.92/76.14 4409[57:Spt:4407.0,4231.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.14 4412[57:Res:4409.0,61.1] always3(s43) || -> . % 75.92/76.14 4413[57:SSi:4412.0,732.0,4221.0] || -> . % 75.92/76.14 4414[55:Spt:4413.0,4215.2,4220.0] || xuntil6(s42)*+ -> . % 75.92/76.14 4415[55:Spt:4413.0,4215.0,4215.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.14 4416[55:Res:53.1,4415.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.14 4418[55:MRR:4416.0,4207.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.14 4421[55:Res:4418.0,61.1] always3(s43) || -> . % 75.92/76.14 4422[55:SSi:4421.0,732.0] || -> . % 75.92/76.14 4423[54:Spt:4422.0,4211.1,4213.0] || xuntil6(s41)* -> . % 75.92/76.14 4424[54:Spt:4422.0,4211.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.14 4427[54:Res:4424.0,61.1] always3(s41) || -> . % 75.92/76.14 4428[54:SSi:4427.0,730.0,4201.0] || -> . % 75.92/76.14 4429[52:Spt:4428.0,4198.2,4200.0] || xuntil6(s40)*+ -> . % 75.92/76.14 4430[52:Spt:4428.0,4198.0,4198.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.14 4431[52:Res:53.1,4430.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.14 4433[52:MRR:4431.0,4187.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.14 4435[52:Res:4433.0,61.1] always3(s41) || -> . % 75.92/76.14 4436[52:SSi:4435.0,730.0] || -> . % 75.92/76.14 4437[51:Spt:4436.0,4191.1,4196.0] || xuntil6(s39)* -> . % 75.92/76.14 4438[51:Spt:4436.0,4191.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.14 4441[51:Res:4438.0,61.1] always3(s39) || -> . % 75.92/76.14 4442[51:SSi:4441.0,728.0,4181.0] || -> . % 75.92/76.14 4443[49:Spt:4442.0,4172.2,4180.0] || xuntil6(s38)*+ -> . % 75.92/76.14 4444[49:Spt:4442.0,4172.0,4172.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.14 4445[49:Res:53.1,4444.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.14 4447[49:MRR:4445.0,4164.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.14 4450[49:Res:4447.0,61.1] always3(s39) || -> . % 75.92/76.14 4451[49:SSi:4450.0,728.0] || -> . % 75.92/76.14 4452[48:Spt:4451.0,4168.1,4170.0] || xuntil6(s37)* -> . % 75.92/76.14 4453[48:Spt:4451.0,4168.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.14 4456[48:Res:4453.0,61.1] always3(s37) || -> . % 75.92/76.14 4457[48:SSi:4456.0,726.0,4158.0] || -> . % 75.92/76.14 4458[46:Spt:4457.0,4152.2,4157.0] || xuntil6(s36)*+ -> . % 75.92/76.14 4459[46:Spt:4457.0,4152.0,4152.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.14 4460[46:Res:53.1,4459.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.14 4462[46:MRR:4460.0,4144.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.14 4464[46:Res:4462.0,61.1] always3(s37) || -> . % 75.92/76.14 4465[46:SSi:4464.0,726.0] || -> . % 75.92/76.14 4466[45:Spt:4465.0,4148.1,4150.0] || xuntil6(s35)* -> . % 75.92/76.14 4467[45:Spt:4465.0,4148.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.14 4470[45:Res:4467.0,61.1] always3(s35) || -> . % 75.92/76.14 4471[45:SSi:4470.0,724.0,4138.0] || -> . % 75.92/76.14 4472[43:Spt:4471.0,4135.2,4137.0] || xuntil6(s34)*+ -> . % 75.92/76.14 4473[43:Spt:4471.0,4135.0,4135.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 75.92/76.14 4474[43:Res:53.1,4473.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 75.92/76.14 4476[43:MRR:4474.0,4124.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.14 4478[43:Res:4476.0,61.1] always3(s35) || -> . % 75.92/76.14 4479[43:SSi:4478.0,724.0] || -> . % 75.92/76.14 4480[42:Spt:4479.0,4128.1,4133.0] || xuntil6(s33)* -> . % 75.92/76.14 4481[42:Spt:4479.0,4128.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.14 4484[42:Res:4481.0,61.1] always3(s33) || -> . % 75.92/76.14 4485[42:SSi:4484.0,722.0,4118.0] || -> . % 75.92/76.14 4486[40:Spt:4485.0,4109.2,4117.0] || xuntil6(s32)*+ -> . % 75.92/76.14 4487[40:Spt:4485.0,4109.0,4109.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 75.92/76.14 4488[40:Res:53.1,4487.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 75.92/76.14 4490[40:MRR:4488.0,4101.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.14 4492[40:Res:4490.0,61.1] always3(s33) || -> . % 75.92/76.14 4493[40:SSi:4492.0,722.0] || -> . % 75.92/76.14 4494[39:Spt:4493.0,4105.1,4107.0] || xuntil6(s31)* -> . % 75.92/76.14 4495[39:Spt:4493.0,4105.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.14 4498[39:Res:4495.0,61.1] always3(s31) || -> . % 75.92/76.14 4499[39:SSi:4498.0,720.0,4095.0] || -> . % 75.92/76.14 4500[37:Spt:4499.0,4089.2,4094.0] || xuntil6(s30)*+ -> . % 75.92/76.14 4501[37:Spt:4499.0,4089.0,4089.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.14 4502[37:Res:53.1,4501.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.14 4504[37:MRR:4502.0,4081.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.14 4506[37:Res:4504.0,61.1] always3(s31) || -> . % 75.92/76.14 4507[37:SSi:4506.0,720.0] || -> . % 75.92/76.14 4508[36:Spt:4507.0,4085.1,4087.0] || xuntil6(s29)* -> . % 75.92/76.14 4509[36:Spt:4507.0,4085.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.14 4512[36:Res:4509.0,61.1] always3(s29) || -> . % 75.92/76.14 4513[36:SSi:4512.0,718.0,4072.0] || -> . % 75.92/76.14 4514[34:Spt:4513.0,4070.2,4071.0] || xuntil6(s28)*+ -> . % 75.92/76.14 4515[34:Spt:4513.0,4070.0,4070.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.14 4516[34:Res:53.1,4515.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.14 4518[35:Spt:4516.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.14 4520[35:Res:4518.0,61.1] always3(s28) || -> . % 75.92/76.14 4521[35:SSi:4520.0,717.0,4069.0] || -> . % 75.92/76.14 4522[35:Spt:4521.0,4516.0,4518.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.14 4523[35:Spt:4521.0,4516.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.14 4527[35:Res:4523.0,61.1] always3(s29) || -> . % 75.92/76.14 4528[35:SSi:4527.0,718.0] || -> . % 75.92/76.14 4529[33:Spt:4528.0,4064.2,4068.0] || xuntil6(s27)*+ -> . % 75.92/76.14 4530[33:Spt:4528.0,4064.0,4064.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.14 4531[33:Res:53.1,4530.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.14 4533[34:Spt:4531.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.14 4535[34:Res:4533.0,61.1] always3(s27) || -> . % 75.92/76.14 4536[34:SSi:4535.0,716.0,4063.0] || -> . % 75.92/76.14 4537[34:Spt:4536.0,4531.0,4533.0] || m_main_v_state(s27,c_busy)* -> . % 75.92/76.14 4538[34:Spt:4536.0,4531.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.14 4542[34:Res:4538.0,61.1] always3(s28) || -> . % 75.92/76.14 4543[34:SSi:4542.0,717.0] || -> . % 75.92/76.14 4544[32:Spt:4543.0,4061.2,4062.0] || xuntil6(s26)*+ -> . % 75.92/76.14 4545[32:Spt:4543.0,4061.0,4061.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.14 4546[32:Res:53.1,4545.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.14 4548[33:Spt:4546.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.14 4550[33:Res:4548.0,61.1] always3(s26) || -> . % 75.92/76.14 4551[33:SSi:4550.0,715.0,4060.0] || -> . % 75.92/76.14 4552[33:Spt:4551.0,4546.0,4548.0] || m_main_v_state(s26,c_busy)* -> . % 75.92/76.14 4553[33:Spt:4551.0,4546.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.14 4557[33:Res:4553.0,61.1] always3(s27) || -> . % 75.92/76.14 4558[33:SSi:4557.0,716.0] || -> . % 75.92/76.14 4559[31:Spt:4558.0,4055.2,4059.0] || xuntil6(s25)*+ -> . % 75.92/76.14 4560[31:Spt:4558.0,4055.0,4055.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.14 4561[31:Res:53.1,4560.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.14 4563[32:Spt:4561.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.14 4565[32:Res:4563.0,61.1] always3(s25) || -> . % 75.92/76.14 4566[32:SSi:4565.0,714.0,4054.0] || -> . % 75.92/76.14 4567[32:Spt:4566.0,4561.0,4563.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.14 4568[32:Spt:4566.0,4561.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.14 4572[32:Res:4568.0,61.1] always3(s26) || -> . % 75.92/76.14 4573[32:SSi:4572.0,715.0] || -> . % 75.92/76.14 4574[30:Spt:4573.0,4052.2,4053.0] || xuntil6(s24)*+ -> . % 75.92/76.14 4575[30:Spt:4573.0,4052.0,4052.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.14 4576[30:Res:53.1,4575.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.14 4578[31:Spt:4576.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.14 4580[31:Res:4578.0,61.1] always3(s24) || -> . % 75.92/76.14 4581[31:SSi:4580.0,713.0,4051.0] || -> . % 75.92/76.14 4582[31:Spt:4581.0,4576.0,4578.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.14 4583[31:Spt:4581.0,4576.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.14 4587[31:Res:4583.0,61.1] always3(s25) || -> . % 75.92/76.14 4588[31:SSi:4587.0,714.0] || -> . % 75.92/76.14 4589[29:Spt:4588.0,4046.2,4050.0] || xuntil6(s23)*+ -> . % 75.92/76.14 4590[29:Spt:4588.0,4046.0,4046.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.14 4591[29:Res:53.1,4590.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.14 4593[30:Spt:4591.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.14 4595[30:Res:4593.0,61.1] always3(s23) || -> . % 75.92/76.14 4596[30:SSi:4595.0,712.0,4045.0] || -> . % 75.92/76.14 4597[30:Spt:4596.0,4591.0,4593.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.14 4598[30:Spt:4596.0,4591.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.14 4602[30:Res:4598.0,61.1] always3(s24) || -> . % 75.92/76.14 4603[30:SSi:4602.0,713.0] || -> . % 75.92/76.14 4604[28:Spt:4603.0,4043.2,4044.0] || xuntil6(s22)*+ -> . % 75.92/76.14 4605[28:Spt:4603.0,4043.0,4043.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.14 4606[28:Res:53.1,4605.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.14 4608[29:Spt:4606.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.14 4610[29:Res:4608.0,61.1] always3(s22) || -> . % 75.92/76.14 4611[29:SSi:4610.0,711.0,4042.0] || -> . % 75.92/76.14 4612[29:Spt:4611.0,4606.0,4608.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.14 4613[29:Spt:4611.0,4606.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.14 4617[29:Res:4613.0,61.1] always3(s23) || -> . % 75.92/76.14 4618[29:SSi:4617.0,712.0] || -> . % 75.92/76.14 4619[27:Spt:4618.0,4037.2,4041.0] || xuntil6(s21)*+ -> . % 75.92/76.14 4620[27:Spt:4618.0,4037.0,4037.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.14 4621[27:Res:53.1,4620.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.14 4623[28:Spt:4621.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.14 4625[28:Res:4623.0,61.1] always3(s22) || -> . % 75.92/76.14 4626[28:SSi:4625.0,711.0] || -> . % 75.92/76.14 4627[28:Spt:4626.0,4621.1,4623.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.14 4628[28:Spt:4626.0,4621.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.14 4631[28:Res:4628.0,61.1] always3(s21) || -> . % 75.92/76.14 4632[28:SSi:4631.0,710.0,4036.0] || -> . % 75.92/76.14 4633[26:Spt:4632.0,4034.2,4035.0] || xuntil6(s20)*+ -> . % 75.92/76.14 4634[26:Spt:4632.0,4034.0,4034.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.14 4635[26:Res:53.1,4634.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.14 4637[27:Spt:4635.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.14 4639[27:Res:4637.0,61.1] always3(s21) || -> . % 75.92/76.14 4640[27:SSi:4639.0,710.0] || -> . % 75.92/76.14 4641[27:Spt:4640.0,4635.1,4637.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.14 4642[27:Spt:4640.0,4635.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.14 4645[27:Res:4642.0,61.1] always3(s20) || -> . % 75.92/76.14 4646[27:SSi:4645.0,709.0,4033.0] || -> . % 75.92/76.14 4647[25:Spt:4646.0,4028.2,4032.0] || xuntil6(s19)*+ -> . % 75.92/76.14 4648[25:Spt:4646.0,4028.0,4028.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.14 4649[25:Res:53.1,4648.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.14 4651[26:Spt:4649.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.14 4653[26:Res:4651.0,61.1] always3(s20) || -> . % 75.92/76.14 4654[26:SSi:4653.0,709.0] || -> . % 75.92/76.14 4655[26:Spt:4654.0,4649.1,4651.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.14 4656[26:Spt:4654.0,4649.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.14 4659[26:Res:4656.0,61.1] always3(s19) || -> . % 75.92/76.14 4660[26:SSi:4659.0,708.0,4027.0] || -> . % 75.92/76.14 4661[24:Spt:4660.0,4025.2,4026.0] || xuntil6(s18)*+ -> . % 75.92/76.14 4662[24:Spt:4660.0,4025.0,4025.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.14 4663[24:Res:53.1,4662.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.14 4668[25:Spt:4663.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.14 4670[25:Res:4668.0,61.1] always3(s18) || -> . % 75.92/76.14 4671[25:SSi:4670.0,707.0,4024.0] || -> . % 75.92/76.14 4672[25:Spt:4671.0,4663.0,4668.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.14 4673[25:Spt:4671.0,4663.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.14 4677[25:Res:4673.0,61.1] always3(s19) || -> . % 75.92/76.14 4678[25:SSi:4677.0,708.0] || -> . % 75.92/76.14 4679[23:Spt:4678.0,4019.2,4023.0] || xuntil6(s17)*+ -> . % 75.92/76.14 4680[23:Spt:4678.0,4019.0,4019.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.14 4681[23:Res:53.1,4680.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.14 4683[24:Spt:4681.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.14 4685[24:Res:4683.0,61.1] always3(s18) || -> . % 75.92/76.14 4686[24:SSi:4685.0,707.0] || -> . % 75.92/76.14 4687[24:Spt:4686.0,4681.1,4683.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.14 4688[24:Spt:4686.0,4681.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.14 4691[24:Res:4688.0,61.1] always3(s17) || -> . % 75.92/76.14 4692[24:SSi:4691.0,706.0,4018.0] || -> . % 75.92/76.14 4693[22:Spt:4692.0,4016.2,4017.0] || xuntil6(s16)*+ -> . % 75.92/76.14 4694[22:Spt:4692.0,4016.0,4016.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.14 4695[22:Res:53.1,4694.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.14 4697[23:Spt:4695.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.14 4699[23:Res:4697.0,61.1] always3(s17) || -> . % 75.92/76.14 4700[23:SSi:4699.0,706.0] || -> . % 75.92/76.14 4701[23:Spt:4700.0,4695.1,4697.0] || m_main_v_state(s17,c_busy)* -> . % 75.92/76.14 4702[23:Spt:4700.0,4695.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.14 4705[23:Res:4702.0,61.1] always3(s16) || -> . % 75.92/76.14 4706[23:SSi:4705.0,705.0,4015.0] || -> . % 75.92/76.14 4707[21:Spt:4706.0,4010.2,4014.0] || xuntil6(s15)*+ -> . % 75.92/76.14 4708[21:Spt:4706.0,4010.0,4010.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.14 4709[21:Res:53.1,4708.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.14 4714[22:Spt:4709.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.14 4716[22:Res:4714.0,61.1] always3(s15) || -> . % 75.92/76.14 4717[22:SSi:4716.0,704.0,4009.0] || -> . % 75.92/76.14 4718[22:Spt:4717.0,4709.0,4714.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.14 4719[22:Spt:4717.0,4709.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.14 4723[22:Res:4719.0,61.1] always3(s16) || -> . % 75.92/76.14 4724[22:SSi:4723.0,705.0] || -> . % 75.92/76.14 4725[20:Spt:4724.0,4007.2,4008.0] || xuntil6(s14)*+ -> . % 75.92/76.14 4726[20:Spt:4724.0,4007.0,4007.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.14 4727[20:Res:53.1,4726.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.14 4729[21:Spt:4727.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.14 4731[21:Res:4729.0,61.1] always3(s15) || -> . % 75.92/76.14 4732[21:SSi:4731.0,704.0] || -> . % 75.92/76.14 4733[21:Spt:4732.0,4727.1,4729.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.14 4734[21:Spt:4732.0,4727.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.14 4737[21:Res:4734.0,61.1] always3(s14) || -> . % 75.92/76.14 4738[21:SSi:4737.0,703.0,4006.0] || -> . % 75.92/76.14 4739[19:Spt:4738.0,4001.2,4005.0] || xuntil6(s13)*+ -> . % 75.92/76.14 4740[19:Spt:4738.0,4001.0,4001.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.14 4741[19:Res:53.1,4740.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.14 4743[20:Spt:4741.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.14 4745[20:Res:4743.0,61.1] always3(s14) || -> . % 75.92/76.14 4746[20:SSi:4745.0,703.0] || -> . % 75.92/76.14 4747[20:Spt:4746.0,4741.1,4743.0] || m_main_v_state(s14,c_busy)* -> . % 75.92/76.14 4748[20:Spt:4746.0,4741.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.14 4751[20:Res:4748.0,61.1] always3(s13) || -> . % 75.92/76.14 4752[20:SSi:4751.0,702.0,4000.0] || -> . % 75.92/76.14 4753[18:Spt:4752.0,3998.2,3999.0] || xuntil6(s12)*+ -> . % 75.92/76.14 4754[18:Spt:4752.0,3998.0,3998.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.14 4755[18:Res:53.1,4754.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.14 4760[19:Spt:4755.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.14 4762[19:Res:4760.0,61.1] always3(s12) || -> . % 75.92/76.14 4763[19:SSi:4762.0,701.0,3997.0] || -> . % 75.92/76.14 4764[19:Spt:4763.0,4755.0,4760.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.14 4765[19:Spt:4763.0,4755.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.14 4769[19:Res:4765.0,61.1] always3(s13) || -> . % 75.92/76.14 4770[19:SSi:4769.0,702.0] || -> . % 75.92/76.14 4771[17:Spt:4770.0,3992.2,3996.0] || xuntil6(s11)*+ -> . % 75.92/76.14 4772[17:Spt:4770.0,3992.0,3992.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.14 4773[17:Res:53.1,4772.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.14 4775[18:Spt:4773.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.14 4777[18:Res:4775.0,61.1] always3(s12) || -> . % 75.92/76.14 4778[18:SSi:4777.0,701.0] || -> . % 75.92/76.14 4779[18:Spt:4778.0,4773.1,4775.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.14 4780[18:Spt:4778.0,4773.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.14 4783[18:Res:4780.0,61.1] always3(s11) || -> . % 75.92/76.14 4784[18:SSi:4783.0,700.0,3991.0] || -> . % 75.92/76.14 4785[16:Spt:4784.0,3989.2,3990.0] || xuntil6(s10)*+ -> . % 75.92/76.14 4786[16:Spt:4784.0,3989.0,3989.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.14 4787[16:Res:53.1,4786.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.14 4789[17:Spt:4787.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.14 4791[17:Res:4789.0,61.1] always3(s11) || -> . % 75.92/76.14 4792[17:SSi:4791.0,700.0] || -> . % 75.92/76.14 4793[17:Spt:4792.0,4787.1,4789.0] || m_main_v_state(s11,c_busy)* -> . % 75.92/76.14 4794[17:Spt:4792.0,4787.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.14 4797[17:Res:4794.0,61.1] always3(s10) || -> . % 75.92/76.14 4798[17:SSi:4797.0,699.0,3988.0] || -> . % 75.92/76.14 4799[15:Spt:4798.0,3983.2,3987.0] || xuntil6(s9)*+ -> . % 75.92/76.14 4800[15:Spt:4798.0,3983.0,3983.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.14 4801[15:Res:53.1,4800.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.14 4806[16:Spt:4801.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.14 4808[16:Res:4806.0,61.1] always3(s9) || -> . % 75.92/76.14 4809[16:SSi:4808.0,698.0,3982.0] || -> . % 75.92/76.14 4810[16:Spt:4809.0,4801.0,4806.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.14 4811[16:Spt:4809.0,4801.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.14 4815[16:Res:4811.0,61.1] always3(s10) || -> . % 75.92/76.14 4816[16:SSi:4815.0,699.0] || -> . % 75.92/76.14 4817[14:Spt:4816.0,3980.2,3981.0] || xuntil6(s8)*+ -> . % 75.92/76.14 4818[14:Spt:4816.0,3980.0,3980.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.14 4819[14:Res:53.1,4818.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.14 4821[15:Spt:4819.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.14 4823[15:Res:4821.0,61.1] always3(s9) || -> . % 75.92/76.14 4824[15:SSi:4823.0,698.0] || -> . % 75.92/76.14 4825[15:Spt:4824.0,4819.1,4821.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.14 4826[15:Spt:4824.0,4819.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.14 4829[15:Res:4826.0,61.1] always3(s8) || -> . % 75.92/76.14 4830[15:SSi:4829.0,697.0,3979.0] || -> . % 75.92/76.14 4831[13:Spt:4830.0,3974.2,3978.0] || xuntil6(s7)*+ -> . % 75.92/76.14 4832[13:Spt:4830.0,3974.0,3974.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.14 4833[13:Res:53.1,4832.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.14 4835[14:Spt:4833.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.14 4837[14:Res:4835.0,61.1] always3(s8) || -> . % 75.92/76.14 4838[14:SSi:4837.0,697.0] || -> . % 75.92/76.14 4839[14:Spt:4838.0,4833.1,4835.0] || m_main_v_state(s8,c_busy)* -> . % 75.92/76.14 4840[14:Spt:4838.0,4833.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.14 4843[14:Res:4840.0,61.1] always3(s7) || -> . % 75.92/76.14 4844[14:SSi:4843.0,696.0,3973.0] || -> . % 75.92/76.14 4845[12:Spt:4844.0,3971.2,3972.0] || xuntil6(s6)*+ -> . % 75.92/76.14 4846[12:Spt:4844.0,3971.0,3971.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.14 4847[12:Res:53.1,4846.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.14 4852[13:Spt:4847.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.14 4854[13:Res:4852.0,61.1] always3(s6) || -> . % 75.92/76.14 4855[13:SSi:4854.0,695.0,3970.0] || -> . % 75.92/76.14 4856[13:Spt:4855.0,4847.0,4852.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.14 4857[13:Spt:4855.0,4847.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.14 4861[13:Res:4857.0,61.1] always3(s7) || -> . % 75.92/76.14 4862[13:SSi:4861.0,696.0] || -> . % 75.92/76.14 4863[11:Spt:4862.0,3965.2,3969.0] || xuntil6(s5)*+ -> . % 75.92/76.14 4864[11:Spt:4862.0,3965.0,3965.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.14 4865[11:Res:53.1,4864.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.14 4867[12:Spt:4865.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.14 4869[12:Res:4867.0,61.1] always3(s6) || -> . % 75.92/76.14 4870[12:SSi:4869.0,695.0] || -> . % 75.92/76.14 4871[12:Spt:4870.0,4865.1,4867.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.14 4872[12:Spt:4870.0,4865.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.14 4875[12:Res:4872.0,61.1] always3(s5) || -> . % 75.92/76.14 4876[12:SSi:4875.0,694.0,3964.0] || -> . % 75.92/76.14 4877[10:Spt:4876.0,3962.2,3963.0] || xuntil6(s4)*+ -> . % 75.92/76.14 4878[10:Spt:4876.0,3962.0,3962.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.14 4879[10:Res:53.1,4878.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.14 4881[11:Spt:4879.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.14 4883[11:Res:4881.0,61.1] always3(s5) || -> . % 75.92/76.14 4884[11:SSi:4883.0,694.0] || -> . % 75.92/76.14 4885[11:Spt:4884.0,4879.1,4881.0] || m_main_v_state(s5,c_busy)* -> . % 75.92/76.14 4886[11:Spt:4884.0,4879.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.14 4889[11:Res:4886.0,61.1] always3(s4) || -> . % 75.92/76.14 4890[11:SSi:4889.0,693.0,3961.0] || -> . % 75.92/76.14 4891[9:Spt:4890.0,3959.2,3960.0] || xuntil6(s3)*+ -> . % 75.92/76.14 4892[9:Spt:4890.0,3959.0,3959.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.14 4893[9:Res:53.1,4892.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.14 4898[10:Spt:4893.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.14 4900[10:Res:4898.0,61.1] always3(s3) || -> . % 75.92/76.14 4901[10:SSi:4900.0,692.0,3958.0] || -> . % 75.92/76.14 4902[10:Spt:4901.0,4893.0,4898.0] || m_main_v_state(s3,c_busy)* -> . % 75.92/76.14 4903[10:Spt:4901.0,4893.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.14 4907[10:Res:4903.0,61.1] always3(s4) || -> . % 75.92/76.14 4908[10:SSi:4907.0,693.0] || -> . % 75.92/76.14 4909[8:Spt:4908.0,3956.2,3957.0] || xuntil6(s2)*+ -> . % 75.92/76.14 4910[8:Spt:4908.0,3956.0,3956.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.14 4911[8:Res:53.1,4910.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.14 4913[9:Spt:4911.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.14 4915[9:Res:4913.0,61.1] always3(s3) || -> . % 75.92/76.14 4916[9:SSi:4915.0,692.0] || -> . % 75.92/76.14 4917[9:Spt:4916.0,4911.1,4913.0] || m_main_v_state(s3,c_busy)* -> . % 75.92/76.14 4918[9:Spt:4916.0,4911.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.14 4921[9:Res:4918.0,61.1] always3(s2) || -> . % 75.92/76.14 4922[9:SSi:4921.0,691.0,3955.0] || -> . % 75.92/76.14 4923[7:Spt:4922.0,3950.2,3954.0] || xuntil6(s1)*+ -> . % 75.92/76.14 4924[7:Spt:4922.0,3950.0,3950.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.14 4925[7:Res:53.1,4924.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.14 4927[8:Spt:4925.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.14 4929[8:Res:4927.0,61.1] always3(s1) || -> . % 75.92/76.14 4930[8:SSi:4929.0,690.0,3949.0] || -> . % 75.92/76.14 4931[8:Spt:4930.0,4925.0,4927.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.14 4932[8:Spt:4930.0,4925.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.14 4937[8:Res:4932.0,61.1] always3(s2) || -> . % 75.92/76.14 4938[8:SSi:4937.0,691.0] || -> . % 75.92/76.14 4939[6:Spt:4938.0,74.0,3948.0] || xuntil6(s0)*+ -> . % 75.92/76.14 4940[6:Spt:4938.0,74.1] || -> node4(s0)*. % 75.92/76.14 4941[6:MRR:758.1,4939.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.14 4943[6:Res:4941.0,61.1] always3(s1) || -> . % 75.92/76.14 4944[6:SSi:4943.0,690.0] || -> . % 75.92/76.14 4945[5:Spt:4944.0,3938.0,3942.0] || trans(s49,s46)*+ -> . % 75.92/76.14 4946[5:Spt:4944.0,3938.1,3938.2,3938.3,3938.4,3938.5,3938.6,3938.7,3938.8,3938.9,3938.10,3938.11,3938.12,3938.13,3938.14,3938.15,3938.16,3938.17,3938.18,3938.19,3938.20,3938.21,3938.22,3938.23,3938.24,3938.25,3938.26,3938.27,3938.28,3938.29,3938.30,3938.31,3938.32,3938.33,3938.34,3938.35,3938.36,3938.37,3938.38,3938.39,3938.40,3938.41,3938.42,3938.43,3938.44,3938.45,3938.46] || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.15 4948[5:MRR:3939.0,4945.0] || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.15 4949[5:MRR:3941.1,4945.0] xuntil6(s49) || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.15 4950[6:Spt:4946.0] || -> trans(s49,s45)*. % 75.92/76.15 4951[6:Res:4950.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s45)*. % 75.92/76.15 4953[6:Res:4950.0,60.0] || -> node2(s49,s45)*. % 75.92/76.15 4954[6:SSi:4951.1,50.0,738.0] xuntil6(s49) || -> until2p7(s45)*. % 75.92/76.15 4955[6:Res:4953.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 4956[7:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.15 4957[7:MRR:176.0,4956.0] || -> until5(s1)*. % 75.92/76.15 4958[7:MRR:3224.0,4957.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.15 4962[8:Spt:4958.2] || -> xuntil6(s1)*. % 75.92/76.15 4963[8:MRR:175.0,4962.0] || -> until5(s2)*. % 75.92/76.15 4964[8:MRR:3220.0,4963.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.15 4968[9:Spt:4964.2] || -> xuntil6(s2)*. % 75.92/76.15 4969[9:MRR:174.0,4968.0] || -> until5(s3)*. % 75.92/76.15 4970[9:MRR:3216.0,4969.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.15 4971[10:Spt:4970.2] || -> xuntil6(s3)*. % 75.92/76.15 4972[10:MRR:173.0,4971.0] || -> until5(s4)*. % 75.92/76.15 4973[10:MRR:3212.0,4972.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.15 4977[11:Spt:4973.2] || -> xuntil6(s4)*. % 75.92/76.15 4978[11:MRR:172.0,4977.0] || -> until5(s5)*. % 75.92/76.15 4979[11:MRR:3211.0,4978.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.15 4980[12:Spt:4979.2] || -> xuntil6(s5)*. % 75.92/76.15 4981[12:MRR:171.0,4980.0] || -> until5(s6)*. % 75.92/76.15 4982[12:MRR:3204.0,4981.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.15 4986[13:Spt:4982.2] || -> xuntil6(s6)*. % 75.92/76.15 4987[13:MRR:170.0,4986.0] || -> until5(s7)*. % 75.92/76.15 4988[13:MRR:3200.0,4987.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.15 4989[14:Spt:4988.2] || -> xuntil6(s7)*. % 75.92/76.15 4990[14:MRR:169.0,4989.0] || -> until5(s8)*. % 75.92/76.15 4991[14:MRR:3196.0,4990.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.15 4995[15:Spt:4991.2] || -> xuntil6(s8)*. % 75.92/76.15 4996[15:MRR:168.0,4995.0] || -> until5(s9)*. % 75.92/76.15 4997[15:MRR:3192.0,4996.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.15 4998[16:Spt:4997.2] || -> xuntil6(s9)*. % 75.92/76.15 4999[16:MRR:167.0,4998.0] || -> until5(s10)*. % 75.92/76.15 5000[16:MRR:3191.0,4999.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.15 5004[17:Spt:5000.2] || -> xuntil6(s10)*. % 75.92/76.15 5005[17:MRR:166.0,5004.0] || -> until5(s11)*. % 75.92/76.15 5006[17:MRR:3184.0,5005.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.15 5007[18:Spt:5006.2] || -> xuntil6(s11)*. % 75.92/76.15 5008[18:MRR:165.0,5007.0] || -> until5(s12)*. % 75.92/76.15 5009[18:MRR:3180.0,5008.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.15 5013[19:Spt:5009.2] || -> xuntil6(s12)*. % 75.92/76.15 5014[19:MRR:164.0,5013.0] || -> until5(s13)*. % 75.92/76.15 5015[19:MRR:3176.0,5014.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.15 5016[20:Spt:5015.2] || -> xuntil6(s13)*. % 75.92/76.15 5017[20:MRR:163.0,5016.0] || -> until5(s14)*. % 75.92/76.15 5018[20:MRR:3172.0,5017.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.15 5022[21:Spt:5018.2] || -> xuntil6(s14)*. % 75.92/76.15 5023[21:MRR:162.0,5022.0] || -> until5(s15)*. % 75.92/76.15 5024[21:MRR:3171.0,5023.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.15 5025[22:Spt:5024.2] || -> xuntil6(s15)*. % 75.92/76.15 5026[22:MRR:161.0,5025.0] || -> until5(s16)*. % 75.92/76.15 5027[22:MRR:3164.0,5026.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.15 5031[23:Spt:5027.2] || -> xuntil6(s16)*. % 75.92/76.15 5032[23:MRR:160.0,5031.0] || -> until5(s17)*. % 75.92/76.15 5033[23:MRR:3160.0,5032.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.15 5034[24:Spt:5033.2] || -> xuntil6(s17)*. % 75.92/76.15 5035[24:MRR:159.0,5034.0] || -> until5(s18)*. % 75.92/76.15 5036[24:MRR:3156.0,5035.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.15 5040[25:Spt:5036.2] || -> xuntil6(s18)*. % 75.92/76.15 5041[25:MRR:158.0,5040.0] || -> until5(s19)*. % 75.92/76.15 5042[25:MRR:3152.0,5041.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.15 5043[26:Spt:5042.2] || -> xuntil6(s19)*. % 75.92/76.15 5044[26:MRR:157.0,5043.0] || -> until5(s20)*. % 75.92/76.15 5045[26:MRR:3151.0,5044.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.15 5049[27:Spt:5045.2] || -> xuntil6(s20)*. % 75.92/76.15 5050[27:MRR:156.0,5049.0] || -> until5(s21)*. % 75.92/76.15 5051[27:MRR:3144.0,5050.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.15 5052[28:Spt:5051.2] || -> xuntil6(s21)*. % 75.92/76.15 5053[28:MRR:155.0,5052.0] || -> until5(s22)*. % 75.92/76.15 5054[28:MRR:3140.0,5053.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.15 5058[29:Spt:5054.2] || -> xuntil6(s22)*. % 75.92/76.15 5059[29:MRR:154.0,5058.0] || -> until5(s23)*. % 75.92/76.15 5060[29:MRR:3136.0,5059.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.15 5061[30:Spt:5060.2] || -> xuntil6(s23)*. % 75.92/76.15 5062[30:MRR:153.0,5061.0] || -> until5(s24)*. % 75.92/76.15 5063[30:MRR:3132.0,5062.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.15 5067[31:Spt:5063.2] || -> xuntil6(s24)*. % 75.92/76.15 5068[31:MRR:152.0,5067.0] || -> until5(s25)*. % 75.92/76.15 5069[31:MRR:3131.0,5068.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.15 5070[32:Spt:5069.2] || -> xuntil6(s25)*. % 75.92/76.15 5071[32:MRR:151.0,5070.0] || -> until5(s26)*. % 75.92/76.15 5072[32:MRR:3124.0,5071.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.15 5076[33:Spt:5072.2] || -> xuntil6(s26)*. % 75.92/76.15 5077[33:MRR:150.0,5076.0] || -> until5(s27)*. % 75.92/76.15 5078[33:MRR:3120.0,5077.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.15 5079[34:Spt:5078.2] || -> xuntil6(s27)*. % 75.92/76.15 5080[34:MRR:149.0,5079.0] || -> until5(s28)*. % 75.92/76.15 5081[34:MRR:3116.0,5080.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.15 5085[35:Spt:5081.2] || -> xuntil6(s28)*. % 75.92/76.15 5086[35:MRR:148.0,5085.0] || -> until5(s29)*. % 75.92/76.15 5087[35:MRR:3112.0,5086.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.15 5088[36:Spt:5087.2] || -> xuntil6(s29)*. % 75.92/76.15 5089[36:MRR:147.0,5088.0] || -> until5(s30)*. % 75.92/76.15 5090[36:MRR:3111.0,5089.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.15 5094[37:Spt:5090.2] || -> xuntil6(s30)*. % 75.92/76.15 5095[37:MRR:146.0,5094.0] || -> until5(s31)*. % 75.92/76.15 5096[37:MRR:3107.0,5095.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.15 5097[38:Spt:5096.2] || -> xuntil6(s31)*. % 75.92/76.15 5098[38:MRR:145.0,5097.0] || -> until5(s32)*. % 75.92/76.15 5099[38:MRR:3106.0,5098.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.15 5103[39:Spt:5099.1] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.15 5105[39:Res:5103.0,61.1] always3(s33) || -> . % 75.92/76.15 5106[39:SSi:5105.0,722.0] || -> . % 75.92/76.15 5107[39:Spt:5106.0,5099.1,5103.0] || m_main_v_state(s33,c_busy)*+ -> . % 75.92/76.15 5108[39:Spt:5106.0,5099.0,5099.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 75.92/76.15 5111[39:Res:53.1,5108.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 75.92/76.15 5113[40:Spt:5111.1] || -> xuntil6(s32)*. % 75.92/76.15 5114[40:MRR:144.0,5113.0] || -> until5(s33)*. % 75.92/76.15 5115[40:MRR:932.0,5114.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.15 5120[41:Spt:5115.2] || -> xuntil6(s33)*. % 75.92/76.15 5121[41:MRR:143.0,5120.0] || -> until5(s34)*. % 75.92/76.15 5122[41:MRR:3231.0,5121.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.15 5123[42:Spt:5122.1] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.15 5125[42:Res:5123.0,61.1] always3(s35) || -> . % 75.92/76.15 5126[42:SSi:5125.0,724.0] || -> . % 75.92/76.15 5127[42:Spt:5126.0,5122.1,5123.0] || m_main_v_state(s35,c_busy)*+ -> . % 75.92/76.15 5128[42:Spt:5126.0,5122.0,5122.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 75.92/76.15 5131[42:Res:53.1,5128.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 75.92/76.15 5133[43:Spt:5131.1] || -> xuntil6(s34)*. % 75.92/76.15 5134[43:MRR:142.0,5133.0] || -> until5(s35)*. % 75.92/76.15 5135[43:MRR:930.0,5134.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.15 5143[44:Spt:5135.2] || -> xuntil6(s35)*. % 75.92/76.15 5144[44:MRR:141.0,5143.0] || -> until5(s36)*. % 75.92/76.15 5145[44:MRR:3235.0,5144.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.15 5146[45:Spt:5145.1] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.15 5148[45:Res:5146.0,61.1] always3(s37) || -> . % 75.92/76.15 5149[45:SSi:5148.0,726.0] || -> . % 75.92/76.15 5150[45:Spt:5149.0,5145.1,5146.0] || m_main_v_state(s37,c_busy)*+ -> . % 75.92/76.15 5151[45:Spt:5149.0,5145.0,5145.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 75.92/76.15 5154[45:Res:53.1,5151.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 75.92/76.15 5159[46:Spt:5154.1] || -> xuntil6(s36)*. % 75.92/76.15 5160[46:MRR:140.0,5159.0] || -> until5(s37)*. % 75.92/76.15 5161[46:MRR:928.0,5160.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.15 5163[47:Spt:5161.2] || -> xuntil6(s37)*. % 75.92/76.15 5164[47:MRR:139.0,5163.0] || -> until5(s38)*. % 75.92/76.15 5165[47:MRR:3242.0,5164.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.15 5166[48:Spt:5165.1] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.15 5168[48:Res:5166.0,61.1] always3(s39) || -> . % 75.92/76.15 5169[48:SSi:5168.0,728.0] || -> . % 75.92/76.15 5170[48:Spt:5169.0,5165.1,5166.0] || m_main_v_state(s39,c_busy)*+ -> . % 75.92/76.15 5171[48:Spt:5169.0,5165.0,5165.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 75.92/76.15 5174[48:Res:53.1,5171.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 75.92/76.15 5176[49:Spt:5174.1] || -> xuntil6(s38)*. % 75.92/76.15 5177[49:MRR:138.0,5176.0] || -> until5(s39)*. % 75.92/76.15 5178[49:MRR:926.0,5177.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.15 5183[50:Spt:5178.2] || -> xuntil6(s39)*. % 75.92/76.15 5184[50:MRR:137.0,5183.0] || -> until5(s40)*. % 75.92/76.15 5185[50:MRR:3243.0,5184.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.15 5186[51:Spt:5185.1] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.15 5188[51:Res:5186.0,61.1] always3(s41) || -> . % 75.92/76.15 5189[51:SSi:5188.0,730.0] || -> . % 75.92/76.15 5190[51:Spt:5189.0,5185.1,5186.0] || m_main_v_state(s41,c_busy)*+ -> . % 75.92/76.15 5191[51:Spt:5189.0,5185.0,5185.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 75.92/76.15 5194[51:Res:53.1,5191.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 75.92/76.15 5196[52:Spt:5194.1] || -> xuntil6(s40)*. % 75.92/76.15 5197[52:MRR:136.0,5196.0] || -> until5(s41)*. % 75.92/76.15 5198[52:MRR:924.0,5197.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.15 5206[53:Spt:5198.2] || -> xuntil6(s41)*. % 75.92/76.15 5207[53:MRR:135.0,5206.0] || -> until5(s42)*. % 75.92/76.15 5208[53:MRR:3247.0,5207.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.15 5209[54:Spt:5208.1] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 5211[54:Res:5209.0,61.1] always3(s43) || -> . % 75.92/76.15 5212[54:SSi:5211.0,732.0] || -> . % 75.92/76.15 5213[54:Spt:5212.0,5208.1,5209.0] || m_main_v_state(s43,c_busy)*+ -> . % 75.92/76.15 5214[54:Spt:5212.0,5208.0,5208.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 75.92/76.15 5217[54:Res:53.1,5214.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 75.92/76.15 5222[55:Spt:5217.1] || -> xuntil6(s42)*. % 75.92/76.15 5223[55:MRR:134.0,5222.0] || -> until5(s43)*. % 75.92/76.15 5224[55:MRR:922.0,5223.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.15 5226[56:Spt:5224.2] || -> xuntil6(s43)*. % 75.92/76.15 5227[56:MRR:133.0,5226.0] || -> until5(s44)*. % 75.92/76.15 5228[56:MRR:3251.0,5227.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.15 5229[57:Spt:5228.1] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 5231[57:Res:5229.0,61.1] always3(s45) || -> . % 75.92/76.15 5232[57:SSi:5231.0,734.0] || -> . % 75.92/76.15 5233[57:Spt:5232.0,5228.1,5229.0] || m_main_v_state(s45,c_busy)*+ -> . % 75.92/76.15 5234[57:Spt:5232.0,5228.0,5228.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 75.92/76.15 5237[57:MRR:4955.2,5233.0] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.15 5238[57:Res:53.1,5234.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 75.92/76.15 5240[58:Spt:5238.1] || -> xuntil6(s44)*. % 75.92/76.15 5241[58:MRR:132.0,5240.0] || -> until5(s45)*. % 75.92/76.15 5242[58:MRR:920.0,5241.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.15 5248[57:SoR:5237.0,64.1] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.15 5250[57:SoR:5248.0,66.2] until5(s49) || m_main_v_state(s49,c_ready)* -> xuntil6(s49). % 75.92/76.15 5251[59:Spt:5242.2] || -> xuntil6(s45)*. % 75.92/76.15 5252[59:MRR:131.0,5251.0] || -> until5(s46)*. % 75.92/76.15 5253[59:MRR:3255.0,5252.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.15 5254[60:Spt:5253.1] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 5256[60:Res:5254.0,61.1] always3(s47) || -> . % 75.92/76.15 5257[60:SSi:5256.0,736.0] || -> . % 75.92/76.15 5258[60:Spt:5257.0,5253.1,5254.0] || m_main_v_state(s47,c_busy)*+ -> . % 75.92/76.15 5259[60:Spt:5257.0,5253.0,5253.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 75.92/76.15 5261[60:MRR:780.2,5258.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 75.92/76.15 5262[60:Res:53.1,5259.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 75.92/76.15 5264[61:Spt:5262.1] || -> xuntil6(s46)*. % 75.92/76.15 5265[61:MRR:130.0,5264.0] || -> until5(s47)*. % 75.92/76.15 5266[61:MRR:918.0,5265.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.15 5271[62:Spt:5266.2] || -> xuntil6(s47)*. % 75.92/76.15 5272[62:MRR:129.0,5271.0] || -> until5(s48)*. % 75.92/76.15 5273[62:MRR:3259.0,5272.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.15 5277[63:Spt:5273.1] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 5279[63:Res:5277.0,61.1] always3(s49) || -> . % 75.92/76.15 5280[63:SSi:5279.0,50.0,738.0] || -> . % 75.92/76.15 5281[63:Spt:5280.0,5273.1,5277.0] || m_main_v_state(s49,c_busy)*+ -> . % 75.92/76.15 5282[63:Spt:5280.0,5273.0,5273.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 75.92/76.15 5284[63:MRR:774.2,5281.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 75.92/76.15 5285[63:Res:53.1,5282.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 75.92/76.15 5287[64:Spt:5285.1] || -> xuntil6(s48)*. % 75.92/76.15 5288[64:MRR:128.0,5287.0] || -> until5(s49)*. % 75.92/76.15 5289[64:MRR:5250.0,5288.0] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.15 5293[64:Res:53.1,5289.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.15 5295[64:MRR:5293.0,5281.0] || -> xuntil6(s49)*. % 75.92/76.15 5296[64:MRR:4954.0,5295.0] || -> until2p7(s45)*. % 75.92/76.15 5297[64:MRR:544.0,5296.0] || -> until2p7(s46)* node4(s45). % 75.92/76.15 5298[65:Spt:5297.0] || -> until2p7(s46)*. % 75.92/76.15 5299[65:MRR:549.0,5298.0] || -> until2p7(s47)* node4(s46). % 75.92/76.15 5300[66:Spt:5299.0] || -> until2p7(s47)*. % 75.92/76.15 5301[66:MRR:554.0,5300.0] || -> until2p7(s48)* node4(s47). % 75.92/76.15 5302[67:Spt:5301.0] || -> until2p7(s48)*. % 75.92/76.15 5303[67:MRR:559.0,5302.0] || -> until2p7(s49)* node4(s48). % 75.92/76.15 5304[68:Spt:5303.0] || -> until2p7(s49)*. % 75.92/76.15 5305[68:MRR:194.0,5304.0] || -> node4(s49)*. % 75.92/76.15 5306[68:MRR:5248.0,5305.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.15 5307[68:Res:53.1,5306.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 5309[68:MRR:5307.0,5281.0] || -> . % 75.92/76.15 5310[68:Spt:5309.0,5303.0,5304.0] || until2p7(s49)*+ -> . % 75.92/76.15 5311[68:Spt:5309.0,5303.1] || -> node4(s48)*. % 75.92/76.15 5312[68:MRR:5284.0,5311.0] || m_main_v_state(s48,c_ready)*+ -> . % 75.92/76.15 5315[68:Res:53.1,5312.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.15 5318[68:Res:5315.0,61.1] always3(s48) || -> . % 75.92/76.15 5319[68:SSi:5318.0,737.0,5272.0,5287.0,5302.0,5311.0] || -> . % 75.92/76.15 5320[67:Spt:5319.0,5301.0,5302.0] || until2p7(s48)*+ -> . % 75.92/76.15 5321[67:Spt:5319.0,5301.1] || -> node4(s47)*. % 75.92/76.15 5323[67:MRR:777.0,5321.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 75.92/76.15 5334[67:Res:53.1,5323.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 75.92/76.15 5336[67:MRR:5334.0,5258.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.15 5338[67:Res:5336.0,61.1] always3(s48) || -> . % 75.92/76.15 5339[67:SSi:5338.0,737.0,5272.0,5287.0] || -> . % 75.92/76.15 5340[66:Spt:5339.0,5299.0,5300.0] || until2p7(s47)*+ -> . % 75.92/76.15 5341[66:Spt:5339.0,5299.1] || -> node4(s46)*. % 75.92/76.15 5342[66:MRR:5261.0,5341.0] || m_main_v_state(s46,c_ready)*+ -> . % 75.92/76.15 5345[66:Res:53.1,5342.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.15 5348[66:Res:5345.0,61.1] always3(s46) || -> . % 75.92/76.15 5349[66:SSi:5348.0,735.0,5252.0,5264.0,5298.0,5341.0] || -> . % 75.92/76.15 5350[65:Spt:5349.0,5297.0,5298.0] || until2p7(s46)*+ -> . % 75.92/76.15 5351[65:Spt:5349.0,5297.1] || -> node4(s45)*. % 75.92/76.15 5353[65:MRR:783.0,5351.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 75.92/76.15 5365[65:Res:53.1,5353.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 75.92/76.15 5367[65:MRR:5365.0,5233.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.15 5372[65:Res:5367.0,61.1] always3(s46) || -> . % 75.92/76.15 5373[65:SSi:5372.0,735.0,5252.0,5264.0] || -> . % 75.92/76.15 5374[64:Spt:5373.0,5285.1,5287.0] || xuntil6(s48)* -> . % 75.92/76.15 5375[64:Spt:5373.0,5285.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.15 5378[64:Res:5375.0,61.1] always3(s48) || -> . % 75.92/76.15 5379[64:SSi:5378.0,737.0,5272.0] || -> . % 75.92/76.15 5380[62:Spt:5379.0,5266.2,5271.0] || xuntil6(s47)*+ -> . % 75.92/76.15 5381[62:Spt:5379.0,5266.0,5266.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 75.92/76.15 5382[62:Res:53.1,5381.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 75.92/76.15 5384[62:MRR:5382.0,5258.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.15 5386[62:Res:5384.0,61.1] always3(s48) || -> . % 75.92/76.15 5387[62:SSi:5386.0,737.0] || -> . % 75.92/76.15 5388[61:Spt:5387.0,5262.1,5264.0] || xuntil6(s46)* -> . % 75.92/76.15 5389[61:Spt:5387.0,5262.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.15 5392[61:Res:5389.0,61.1] always3(s46) || -> . % 75.92/76.15 5393[61:SSi:5392.0,735.0,5252.0] || -> . % 75.92/76.15 5394[59:Spt:5393.0,5242.2,5251.0] || xuntil6(s45)*+ -> . % 75.92/76.15 5395[59:Spt:5393.0,5242.0,5242.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 75.92/76.15 5396[59:Res:53.1,5395.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 75.92/76.15 5398[59:MRR:5396.0,5233.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.15 5401[59:Res:5398.0,61.1] always3(s46) || -> . % 75.92/76.15 5402[59:SSi:5401.0,735.0] || -> . % 75.92/76.15 5403[58:Spt:5402.0,5238.1,5240.0] || xuntil6(s44)* -> . % 75.92/76.15 5404[58:Spt:5402.0,5238.0] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.15 5407[58:Res:5404.0,61.1] always3(s44) || -> . % 75.92/76.15 5408[58:SSi:5407.0,733.0,5227.0] || -> . % 75.92/76.15 5409[56:Spt:5408.0,5224.2,5226.0] || xuntil6(s43)*+ -> . % 75.92/76.15 5410[56:Spt:5408.0,5224.0,5224.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 75.92/76.15 5411[56:Res:53.1,5410.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 75.92/76.15 5413[56:MRR:5411.0,5213.0] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.15 5415[56:Res:5413.0,61.1] always3(s44) || -> . % 75.92/76.15 5416[56:SSi:5415.0,733.0] || -> . % 75.92/76.15 5417[55:Spt:5416.0,5217.1,5222.0] || xuntil6(s42)* -> . % 75.92/76.15 5418[55:Spt:5416.0,5217.0] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.15 5421[55:Res:5418.0,61.1] always3(s42) || -> . % 75.92/76.15 5422[55:SSi:5421.0,731.0,5207.0] || -> . % 75.92/76.15 5423[53:Spt:5422.0,5198.2,5206.0] || xuntil6(s41)*+ -> . % 75.92/76.15 5424[53:Spt:5422.0,5198.0,5198.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 75.92/76.15 5425[53:Res:53.1,5424.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 75.92/76.15 5427[53:MRR:5425.0,5190.0] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.15 5429[53:Res:5427.0,61.1] always3(s42) || -> . % 75.92/76.15 5430[53:SSi:5429.0,731.0] || -> . % 75.92/76.15 5431[52:Spt:5430.0,5194.1,5196.0] || xuntil6(s40)* -> . % 75.92/76.15 5432[52:Spt:5430.0,5194.0] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.15 5435[52:Res:5432.0,61.1] always3(s40) || -> . % 75.92/76.15 5436[52:SSi:5435.0,729.0,5184.0] || -> . % 75.92/76.15 5437[50:Spt:5436.0,5178.2,5183.0] || xuntil6(s39)*+ -> . % 75.92/76.15 5438[50:Spt:5436.0,5178.0,5178.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 75.92/76.15 5439[50:Res:53.1,5438.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 75.92/76.15 5441[50:MRR:5439.0,5170.0] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.15 5443[50:Res:5441.0,61.1] always3(s40) || -> . % 75.92/76.15 5444[50:SSi:5443.0,729.0] || -> . % 75.92/76.15 5445[49:Spt:5444.0,5174.1,5176.0] || xuntil6(s38)* -> . % 75.92/76.15 5446[49:Spt:5444.0,5174.0] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.15 5449[49:Res:5446.0,61.1] always3(s38) || -> . % 75.92/76.15 5450[49:SSi:5449.0,727.0,5164.0] || -> . % 75.92/76.15 5451[47:Spt:5450.0,5161.2,5163.0] || xuntil6(s37)*+ -> . % 75.92/76.15 5452[47:Spt:5450.0,5161.0,5161.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 75.92/76.15 5453[47:Res:53.1,5452.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 75.92/76.15 5455[47:MRR:5453.0,5150.0] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.15 5458[47:Res:5455.0,61.1] always3(s38) || -> . % 75.92/76.15 5459[47:SSi:5458.0,727.0] || -> . % 75.92/76.15 5460[46:Spt:5459.0,5154.1,5159.0] || xuntil6(s36)* -> . % 75.92/76.15 5461[46:Spt:5459.0,5154.0] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.15 5464[46:Res:5461.0,61.1] always3(s36) || -> . % 75.92/76.15 5465[46:SSi:5464.0,725.0,5144.0] || -> . % 75.92/76.15 5466[44:Spt:5465.0,5135.2,5143.0] || xuntil6(s35)*+ -> . % 75.92/76.15 5467[44:Spt:5465.0,5135.0,5135.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 75.92/76.15 5468[44:Res:53.1,5467.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 75.92/76.15 5470[44:MRR:5468.0,5127.0] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.15 5472[44:Res:5470.0,61.1] always3(s36) || -> . % 75.92/76.15 5473[44:SSi:5472.0,725.0] || -> . % 75.92/76.15 5474[43:Spt:5473.0,5131.1,5133.0] || xuntil6(s34)* -> . % 75.92/76.15 5475[43:Spt:5473.0,5131.0] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.15 5478[43:Res:5475.0,61.1] always3(s34) || -> . % 75.92/76.15 5479[43:SSi:5478.0,723.0,5121.0] || -> . % 75.92/76.15 5480[41:Spt:5479.0,5115.2,5120.0] || xuntil6(s33)*+ -> . % 75.92/76.15 5481[41:Spt:5479.0,5115.0,5115.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 75.92/76.15 5482[41:Res:53.1,5481.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 75.92/76.15 5484[41:MRR:5482.0,5107.0] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.15 5486[41:Res:5484.0,61.1] always3(s34) || -> . % 75.92/76.15 5487[41:SSi:5486.0,723.0] || -> . % 75.92/76.15 5488[40:Spt:5487.0,5111.1,5113.0] || xuntil6(s32)* -> . % 75.92/76.15 5489[40:Spt:5487.0,5111.0] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.15 5492[40:Res:5489.0,61.1] always3(s32) || -> . % 75.92/76.15 5493[40:SSi:5492.0,721.0,5098.0] || -> . % 75.92/76.15 5494[38:Spt:5493.0,5096.2,5097.0] || xuntil6(s31)*+ -> . % 75.92/76.15 5495[38:Spt:5493.0,5096.0,5096.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 75.92/76.15 5496[38:Res:53.1,5495.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 75.92/76.15 5498[39:Spt:5496.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.15 5500[39:Res:5498.0,61.1] always3(s31) || -> . % 75.92/76.15 5501[39:SSi:5500.0,720.0,5095.0] || -> . % 75.92/76.15 5502[39:Spt:5501.0,5496.0,5498.0] || m_main_v_state(s31,c_busy)* -> . % 75.92/76.15 5503[39:Spt:5501.0,5496.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.15 5507[39:Res:5503.0,61.1] always3(s32) || -> . % 75.92/76.15 5508[39:SSi:5507.0,721.0] || -> . % 75.92/76.15 5509[37:Spt:5508.0,5090.2,5094.0] || xuntil6(s30)*+ -> . % 75.92/76.15 5510[37:Spt:5508.0,5090.0,5090.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.15 5511[37:Res:53.1,5510.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.15 5513[38:Spt:5511.0] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.15 5515[38:Res:5513.0,61.1] always3(s30) || -> . % 75.92/76.15 5516[38:SSi:5515.0,719.0,5089.0] || -> . % 75.92/76.15 5517[38:Spt:5516.0,5511.0,5513.0] || m_main_v_state(s30,c_busy)* -> . % 75.92/76.15 5518[38:Spt:5516.0,5511.1] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.15 5522[38:Res:5518.0,61.1] always3(s31) || -> . % 75.92/76.15 5523[38:SSi:5522.0,720.0] || -> . % 75.92/76.15 5524[36:Spt:5523.0,5087.2,5088.0] || xuntil6(s29)*+ -> . % 75.92/76.15 5525[36:Spt:5523.0,5087.0,5087.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 75.92/76.15 5526[36:Res:53.1,5525.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 75.92/76.15 5528[37:Spt:5526.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.15 5530[37:Res:5528.0,61.1] always3(s29) || -> . % 75.92/76.15 5531[37:SSi:5530.0,718.0,5086.0] || -> . % 75.92/76.15 5532[37:Spt:5531.0,5526.0,5528.0] || m_main_v_state(s29,c_busy)* -> . % 75.92/76.15 5533[37:Spt:5531.0,5526.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.15 5537[37:Res:5533.0,61.1] always3(s30) || -> . % 75.92/76.15 5538[37:SSi:5537.0,719.0] || -> . % 75.92/76.15 5539[35:Spt:5538.0,5081.2,5085.0] || xuntil6(s28)*+ -> . % 75.92/76.15 5540[35:Spt:5538.0,5081.0,5081.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.15 5541[35:Res:53.1,5540.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.15 5543[36:Spt:5541.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.15 5545[36:Res:5543.0,61.1] always3(s29) || -> . % 75.92/76.15 5546[36:SSi:5545.0,718.0] || -> . % 75.92/76.15 5547[36:Spt:5546.0,5541.1,5543.0] || m_main_v_state(s29,c_busy)* -> . % 75.92/76.15 5548[36:Spt:5546.0,5541.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.15 5551[36:Res:5548.0,61.1] always3(s28) || -> . % 75.92/76.15 5552[36:SSi:5551.0,717.0,5080.0] || -> . % 75.92/76.15 5553[34:Spt:5552.0,5078.2,5079.0] || xuntil6(s27)*+ -> . % 75.92/76.15 5554[34:Spt:5552.0,5078.0,5078.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.15 5555[34:Res:53.1,5554.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.15 5557[35:Spt:5555.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.15 5559[35:Res:5557.0,61.1] always3(s28) || -> . % 75.92/76.15 5560[35:SSi:5559.0,717.0] || -> . % 75.92/76.15 5561[35:Spt:5560.0,5555.1,5557.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.15 5562[35:Spt:5560.0,5555.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.15 5565[35:Res:5562.0,61.1] always3(s27) || -> . % 75.92/76.15 5566[35:SSi:5565.0,716.0,5077.0] || -> . % 75.92/76.15 5567[33:Spt:5566.0,5072.2,5076.0] || xuntil6(s26)*+ -> . % 75.92/76.15 5568[33:Spt:5566.0,5072.0,5072.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.15 5569[33:Res:53.1,5568.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.15 5571[34:Spt:5569.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.15 5573[34:Res:5571.0,61.1] always3(s27) || -> . % 75.92/76.15 5574[34:SSi:5573.0,716.0] || -> . % 75.92/76.15 5575[34:Spt:5574.0,5569.1,5571.0] || m_main_v_state(s27,c_busy)* -> . % 75.92/76.15 5576[34:Spt:5574.0,5569.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.15 5579[34:Res:5576.0,61.1] always3(s26) || -> . % 75.92/76.15 5580[34:SSi:5579.0,715.0,5071.0] || -> . % 75.92/76.15 5581[32:Spt:5580.0,5069.2,5070.0] || xuntil6(s25)*+ -> . % 75.92/76.15 5582[32:Spt:5580.0,5069.0,5069.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.15 5583[32:Res:53.1,5582.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.15 5588[33:Spt:5583.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.15 5590[33:Res:5588.0,61.1] always3(s25) || -> . % 75.92/76.15 5591[33:SSi:5590.0,714.0,5068.0] || -> . % 75.92/76.15 5592[33:Spt:5591.0,5583.0,5588.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.15 5593[33:Spt:5591.0,5583.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.15 5597[33:Res:5593.0,61.1] always3(s26) || -> . % 75.92/76.15 5598[33:SSi:5597.0,715.0] || -> . % 75.92/76.15 5599[31:Spt:5598.0,5063.2,5067.0] || xuntil6(s24)*+ -> . % 75.92/76.15 5600[31:Spt:5598.0,5063.0,5063.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.15 5601[31:Res:53.1,5600.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.15 5603[32:Spt:5601.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.15 5605[32:Res:5603.0,61.1] always3(s25) || -> . % 75.92/76.15 5606[32:SSi:5605.0,714.0] || -> . % 75.92/76.15 5607[32:Spt:5606.0,5601.1,5603.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.15 5608[32:Spt:5606.0,5601.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.15 5611[32:Res:5608.0,61.1] always3(s24) || -> . % 75.92/76.15 5612[32:SSi:5611.0,713.0,5062.0] || -> . % 75.92/76.15 5613[30:Spt:5612.0,5060.2,5061.0] || xuntil6(s23)*+ -> . % 75.92/76.15 5614[30:Spt:5612.0,5060.0,5060.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.15 5615[30:Res:53.1,5614.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.15 5617[31:Spt:5615.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.15 5619[31:Res:5617.0,61.1] always3(s24) || -> . % 75.92/76.15 5620[31:SSi:5619.0,713.0] || -> . % 75.92/76.15 5621[31:Spt:5620.0,5615.1,5617.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.15 5622[31:Spt:5620.0,5615.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.15 5625[31:Res:5622.0,61.1] always3(s23) || -> . % 75.92/76.15 5626[31:SSi:5625.0,712.0,5059.0] || -> . % 75.92/76.15 5627[29:Spt:5626.0,5054.2,5058.0] || xuntil6(s22)*+ -> . % 75.92/76.15 5628[29:Spt:5626.0,5054.0,5054.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.15 5629[29:Res:53.1,5628.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.15 5634[30:Spt:5629.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.15 5636[30:Res:5634.0,61.1] always3(s22) || -> . % 75.92/76.15 5637[30:SSi:5636.0,711.0,5053.0] || -> . % 75.92/76.15 5638[30:Spt:5637.0,5629.0,5634.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.15 5639[30:Spt:5637.0,5629.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.15 5643[30:Res:5639.0,61.1] always3(s23) || -> . % 75.92/76.15 5644[30:SSi:5643.0,712.0] || -> . % 75.92/76.15 5645[28:Spt:5644.0,5051.2,5052.0] || xuntil6(s21)*+ -> . % 75.92/76.15 5646[28:Spt:5644.0,5051.0,5051.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.15 5647[28:Res:53.1,5646.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.15 5649[29:Spt:5647.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.15 5651[29:Res:5649.0,61.1] always3(s22) || -> . % 75.92/76.15 5652[29:SSi:5651.0,711.0] || -> . % 75.92/76.15 5653[29:Spt:5652.0,5647.1,5649.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.15 5654[29:Spt:5652.0,5647.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.15 5657[29:Res:5654.0,61.1] always3(s21) || -> . % 75.92/76.15 5658[29:SSi:5657.0,710.0,5050.0] || -> . % 75.92/76.15 5659[27:Spt:5658.0,5045.2,5049.0] || xuntil6(s20)*+ -> . % 75.92/76.15 5660[27:Spt:5658.0,5045.0,5045.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.15 5661[27:Res:53.1,5660.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.15 5663[28:Spt:5661.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.15 5665[28:Res:5663.0,61.1] always3(s21) || -> . % 75.92/76.15 5666[28:SSi:5665.0,710.0] || -> . % 75.92/76.15 5667[28:Spt:5666.0,5661.1,5663.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.15 5668[28:Spt:5666.0,5661.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.15 5671[28:Res:5668.0,61.1] always3(s20) || -> . % 75.92/76.15 5672[28:SSi:5671.0,709.0,5044.0] || -> . % 75.92/76.15 5673[26:Spt:5672.0,5042.2,5043.0] || xuntil6(s19)*+ -> . % 75.92/76.15 5674[26:Spt:5672.0,5042.0,5042.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.15 5675[26:Res:53.1,5674.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.15 5680[27:Spt:5675.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.15 5682[27:Res:5680.0,61.1] always3(s19) || -> . % 75.92/76.15 5683[27:SSi:5682.0,708.0,5041.0] || -> . % 75.92/76.15 5684[27:Spt:5683.0,5675.0,5680.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.15 5685[27:Spt:5683.0,5675.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.15 5689[27:Res:5685.0,61.1] always3(s20) || -> . % 75.92/76.15 5690[27:SSi:5689.0,709.0] || -> . % 75.92/76.15 5691[25:Spt:5690.0,5036.2,5040.0] || xuntil6(s18)*+ -> . % 75.92/76.15 5692[25:Spt:5690.0,5036.0,5036.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.15 5693[25:Res:53.1,5692.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.15 5695[26:Spt:5693.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.15 5697[26:Res:5695.0,61.1] always3(s19) || -> . % 75.92/76.15 5698[26:SSi:5697.0,708.0] || -> . % 75.92/76.15 5699[26:Spt:5698.0,5693.1,5695.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.15 5700[26:Spt:5698.0,5693.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.15 5703[26:Res:5700.0,61.1] always3(s18) || -> . % 75.92/76.15 5704[26:SSi:5703.0,707.0,5035.0] || -> . % 75.92/76.15 5705[24:Spt:5704.0,5033.2,5034.0] || xuntil6(s17)*+ -> . % 75.92/76.15 5706[24:Spt:5704.0,5033.0,5033.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.15 5707[24:Res:53.1,5706.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.15 5709[25:Spt:5707.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.15 5711[25:Res:5709.0,61.1] always3(s18) || -> . % 75.92/76.15 5712[25:SSi:5711.0,707.0] || -> . % 75.92/76.15 5713[25:Spt:5712.0,5707.1,5709.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.15 5714[25:Spt:5712.0,5707.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.15 5717[25:Res:5714.0,61.1] always3(s17) || -> . % 75.92/76.15 5718[25:SSi:5717.0,706.0,5032.0] || -> . % 75.92/76.15 5719[23:Spt:5718.0,5027.2,5031.0] || xuntil6(s16)*+ -> . % 75.92/76.15 5720[23:Spt:5718.0,5027.0,5027.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.15 5721[23:Res:53.1,5720.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.15 5726[24:Spt:5721.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.15 5728[24:Res:5726.0,61.1] always3(s16) || -> . % 75.92/76.15 5729[24:SSi:5728.0,705.0,5026.0] || -> . % 75.92/76.15 5730[24:Spt:5729.0,5721.0,5726.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.15 5731[24:Spt:5729.0,5721.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.15 5735[24:Res:5731.0,61.1] always3(s17) || -> . % 75.92/76.15 5736[24:SSi:5735.0,706.0] || -> . % 75.92/76.15 5737[22:Spt:5736.0,5024.2,5025.0] || xuntil6(s15)*+ -> . % 75.92/76.15 5738[22:Spt:5736.0,5024.0,5024.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.15 5739[22:Res:53.1,5738.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.15 5741[23:Spt:5739.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.15 5743[23:Res:5741.0,61.1] always3(s16) || -> . % 75.92/76.15 5744[23:SSi:5743.0,705.0] || -> . % 75.92/76.15 5745[23:Spt:5744.0,5739.1,5741.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.15 5746[23:Spt:5744.0,5739.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.15 5749[23:Res:5746.0,61.1] always3(s15) || -> . % 75.92/76.15 5750[23:SSi:5749.0,704.0,5023.0] || -> . % 75.92/76.15 5751[21:Spt:5750.0,5018.2,5022.0] || xuntil6(s14)*+ -> . % 75.92/76.15 5752[21:Spt:5750.0,5018.0,5018.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.15 5753[21:Res:53.1,5752.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.15 5755[22:Spt:5753.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.15 5757[22:Res:5755.0,61.1] always3(s15) || -> . % 75.92/76.15 5758[22:SSi:5757.0,704.0] || -> . % 75.92/76.15 5759[22:Spt:5758.0,5753.1,5755.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.15 5760[22:Spt:5758.0,5753.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.15 5763[22:Res:5760.0,61.1] always3(s14) || -> . % 75.92/76.15 5764[22:SSi:5763.0,703.0,5017.0] || -> . % 75.92/76.15 5765[20:Spt:5764.0,5015.2,5016.0] || xuntil6(s13)*+ -> . % 75.92/76.15 5766[20:Spt:5764.0,5015.0,5015.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.15 5767[20:Res:53.1,5766.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.15 5772[21:Spt:5767.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.15 5774[21:Res:5772.0,61.1] always3(s13) || -> . % 75.92/76.15 5775[21:SSi:5774.0,702.0,5014.0] || -> . % 75.92/76.15 5776[21:Spt:5775.0,5767.0,5772.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.15 5777[21:Spt:5775.0,5767.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.15 5781[21:Res:5777.0,61.1] always3(s14) || -> . % 75.92/76.15 5782[21:SSi:5781.0,703.0] || -> . % 75.92/76.15 5783[19:Spt:5782.0,5009.2,5013.0] || xuntil6(s12)*+ -> . % 75.92/76.15 5784[19:Spt:5782.0,5009.0,5009.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.15 5785[19:Res:53.1,5784.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.15 5787[20:Spt:5785.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.15 5789[20:Res:5787.0,61.1] always3(s13) || -> . % 75.92/76.15 5790[20:SSi:5789.0,702.0] || -> . % 75.92/76.15 5791[20:Spt:5790.0,5785.1,5787.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.15 5792[20:Spt:5790.0,5785.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.15 5795[20:Res:5792.0,61.1] always3(s12) || -> . % 75.92/76.15 5796[20:SSi:5795.0,701.0,5008.0] || -> . % 75.92/76.15 5797[18:Spt:5796.0,5006.2,5007.0] || xuntil6(s11)*+ -> . % 75.92/76.15 5798[18:Spt:5796.0,5006.0,5006.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.15 5799[18:Res:53.1,5798.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.15 5801[19:Spt:5799.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.15 5803[19:Res:5801.0,61.1] always3(s12) || -> . % 75.92/76.15 5804[19:SSi:5803.0,701.0] || -> . % 75.92/76.15 5805[19:Spt:5804.0,5799.1,5801.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.15 5806[19:Spt:5804.0,5799.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.15 5809[19:Res:5806.0,61.1] always3(s11) || -> . % 75.92/76.15 5810[19:SSi:5809.0,700.0,5005.0] || -> . % 75.92/76.15 5811[17:Spt:5810.0,5000.2,5004.0] || xuntil6(s10)*+ -> . % 75.92/76.15 5812[17:Spt:5810.0,5000.0,5000.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.15 5813[17:Res:53.1,5812.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.15 5818[18:Spt:5813.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.15 5820[18:Res:5818.0,61.1] always3(s10) || -> . % 75.92/76.15 5821[18:SSi:5820.0,699.0,4999.0] || -> . % 75.92/76.15 5822[18:Spt:5821.0,5813.0,5818.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.15 5823[18:Spt:5821.0,5813.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.15 5827[18:Res:5823.0,61.1] always3(s11) || -> . % 75.92/76.15 5828[18:SSi:5827.0,700.0] || -> . % 75.92/76.15 5829[16:Spt:5828.0,4997.2,4998.0] || xuntil6(s9)*+ -> . % 75.92/76.15 5830[16:Spt:5828.0,4997.0,4997.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.15 5831[16:Res:53.1,5830.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.15 5833[17:Spt:5831.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.15 5835[17:Res:5833.0,61.1] always3(s10) || -> . % 75.92/76.15 5836[17:SSi:5835.0,699.0] || -> . % 75.92/76.15 5837[17:Spt:5836.0,5831.1,5833.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.15 5838[17:Spt:5836.0,5831.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.15 5841[17:Res:5838.0,61.1] always3(s9) || -> . % 75.92/76.15 5842[17:SSi:5841.0,698.0,4996.0] || -> . % 75.92/76.15 5843[15:Spt:5842.0,4991.2,4995.0] || xuntil6(s8)*+ -> . % 75.92/76.15 5844[15:Spt:5842.0,4991.0,4991.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.15 5845[15:Res:53.1,5844.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.15 5847[16:Spt:5845.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.15 5849[16:Res:5847.0,61.1] always3(s9) || -> . % 75.92/76.15 5850[16:SSi:5849.0,698.0] || -> . % 75.92/76.15 5851[16:Spt:5850.0,5845.1,5847.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.15 5852[16:Spt:5850.0,5845.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.15 5855[16:Res:5852.0,61.1] always3(s8) || -> . % 75.92/76.15 5856[16:SSi:5855.0,697.0,4990.0] || -> . % 75.92/76.15 5857[14:Spt:5856.0,4988.2,4989.0] || xuntil6(s7)*+ -> . % 75.92/76.15 5858[14:Spt:5856.0,4988.0,4988.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.15 5859[14:Res:53.1,5858.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.15 5864[15:Spt:5859.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.15 5866[15:Res:5864.0,61.1] always3(s7) || -> . % 75.92/76.15 5867[15:SSi:5866.0,696.0,4987.0] || -> . % 75.92/76.15 5868[15:Spt:5867.0,5859.0,5864.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.15 5869[15:Spt:5867.0,5859.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.15 5873[15:Res:5869.0,61.1] always3(s8) || -> . % 75.92/76.15 5874[15:SSi:5873.0,697.0] || -> . % 75.92/76.15 5875[13:Spt:5874.0,4982.2,4986.0] || xuntil6(s6)*+ -> . % 75.92/76.15 5876[13:Spt:5874.0,4982.0,4982.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.15 5877[13:Res:53.1,5876.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.15 5879[14:Spt:5877.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.15 5881[14:Res:5879.0,61.1] always3(s7) || -> . % 75.92/76.15 5882[14:SSi:5881.0,696.0] || -> . % 75.92/76.15 5883[14:Spt:5882.0,5877.1,5879.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.15 5884[14:Spt:5882.0,5877.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.15 5887[14:Res:5884.0,61.1] always3(s6) || -> . % 75.92/76.15 5888[14:SSi:5887.0,695.0,4981.0] || -> . % 75.92/76.15 5889[12:Spt:5888.0,4979.2,4980.0] || xuntil6(s5)*+ -> . % 75.92/76.15 5890[12:Spt:5888.0,4979.0,4979.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.15 5891[12:Res:53.1,5890.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.15 5893[13:Spt:5891.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.15 5895[13:Res:5893.0,61.1] always3(s6) || -> . % 75.92/76.15 5896[13:SSi:5895.0,695.0] || -> . % 75.92/76.15 5897[13:Spt:5896.0,5891.1,5893.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.15 5898[13:Spt:5896.0,5891.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.15 5901[13:Res:5898.0,61.1] always3(s5) || -> . % 75.92/76.15 5902[13:SSi:5901.0,694.0,4978.0] || -> . % 75.92/76.15 5903[11:Spt:5902.0,4973.2,4977.0] || xuntil6(s4)*+ -> . % 75.92/76.15 5904[11:Spt:5902.0,4973.0,4973.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.15 5905[11:Res:53.1,5904.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.15 5910[12:Spt:5905.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.15 5912[12:Res:5910.0,61.1] always3(s4) || -> . % 75.92/76.15 5913[12:SSi:5912.0,693.0,4972.0] || -> . % 75.92/76.15 5914[12:Spt:5913.0,5905.0,5910.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.15 5915[12:Spt:5913.0,5905.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.15 5919[12:Res:5915.0,61.1] always3(s5) || -> . % 75.92/76.15 5920[12:SSi:5919.0,694.0] || -> . % 75.92/76.15 5921[10:Spt:5920.0,4970.2,4971.0] || xuntil6(s3)*+ -> . % 75.92/76.15 5922[10:Spt:5920.0,4970.0,4970.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.15 5923[10:Res:53.1,5922.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.15 5925[11:Spt:5923.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.15 5927[11:Res:5925.0,61.1] always3(s4) || -> . % 75.92/76.15 5928[11:SSi:5927.0,693.0] || -> . % 75.92/76.15 5929[11:Spt:5928.0,5923.1,5925.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.15 5930[11:Spt:5928.0,5923.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.15 5933[11:Res:5930.0,61.1] always3(s3) || -> . % 75.92/76.15 5934[11:SSi:5933.0,692.0,4969.0] || -> . % 75.92/76.15 5935[9:Spt:5934.0,4964.2,4968.0] || xuntil6(s2)*+ -> . % 75.92/76.15 5936[9:Spt:5934.0,4964.0,4964.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.15 5937[9:Res:53.1,5936.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.15 5939[10:Spt:5937.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.15 5941[10:Res:5939.0,61.1] always3(s3) || -> . % 75.92/76.15 5942[10:SSi:5941.0,692.0] || -> . % 75.92/76.15 5943[10:Spt:5942.0,5937.1,5939.0] || m_main_v_state(s3,c_busy)* -> . % 75.92/76.15 5944[10:Spt:5942.0,5937.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.15 5947[10:Res:5944.0,61.1] always3(s2) || -> . % 75.92/76.15 5948[10:SSi:5947.0,691.0,4963.0] || -> . % 75.92/76.15 5949[8:Spt:5948.0,4958.2,4962.0] || xuntil6(s1)*+ -> . % 75.92/76.15 5950[8:Spt:5948.0,4958.0,4958.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.15 5951[8:Res:53.1,5950.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.15 5956[9:Spt:5951.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.15 5958[9:Res:5956.0,61.1] always3(s1) || -> . % 75.92/76.15 5959[9:SSi:5958.0,690.0,4957.0] || -> . % 75.92/76.15 5960[9:Spt:5959.0,5951.0,5956.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.15 5961[9:Spt:5959.0,5951.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.15 5966[9:Res:5961.0,61.1] always3(s2) || -> . % 75.92/76.15 5967[9:SSi:5966.0,691.0] || -> . % 75.92/76.15 5968[7:Spt:5967.0,74.0,4956.0] || xuntil6(s0)*+ -> . % 75.92/76.15 5969[7:Spt:5967.0,74.1] || -> node4(s0)*. % 75.92/76.15 5970[7:MRR:758.1,5968.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.15 5972[7:Res:5970.0,61.1] always3(s1) || -> . % 75.92/76.15 5973[7:SSi:5972.0,690.0] || -> . % 75.92/76.15 5974[6:Spt:5973.0,4946.0,4950.0] || trans(s49,s45)*+ -> . % 75.92/76.15 5975[6:Spt:5973.0,4946.1,4946.2,4946.3,4946.4,4946.5,4946.6,4946.7,4946.8,4946.9,4946.10,4946.11,4946.12,4946.13,4946.14,4946.15,4946.16,4946.17,4946.18,4946.19,4946.20,4946.21,4946.22,4946.23,4946.24,4946.25,4946.26,4946.27,4946.28,4946.29,4946.30,4946.31,4946.32,4946.33,4946.34,4946.35,4946.36,4946.37,4946.38,4946.39,4946.40,4946.41,4946.42,4946.43,4946.44,4946.45] || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.15 5976[6:MRR:4948.0,5974.0] || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.15 5978[6:MRR:4949.1,5974.0] xuntil6(s49) || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.15 5979[7:Spt:5975.0] || -> trans(s49,s44)*. % 75.92/76.15 5980[7:Res:5979.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s44)*. % 75.92/76.15 5982[7:Res:5979.0,60.0] || -> node2(s49,s44)*. % 75.92/76.15 5983[7:SSi:5980.1,50.0,738.0] xuntil6(s49) || -> until2p7(s44)*. % 75.92/76.15 5984[7:Res:5982.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)*. % 75.92/76.15 5985[8:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.15 5986[8:MRR:176.0,5985.0] || -> until5(s1)*. % 75.92/76.15 5987[8:MRR:3224.0,5986.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.15 5991[9:Spt:5987.2] || -> xuntil6(s1)*. % 75.92/76.15 5992[9:MRR:175.0,5991.0] || -> until5(s2)*. % 75.92/76.15 5993[9:MRR:3220.0,5992.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.15 5994[10:Spt:5993.2] || -> xuntil6(s2)*. % 75.92/76.15 5995[10:MRR:174.0,5994.0] || -> until5(s3)*. % 75.92/76.15 5996[10:MRR:3216.0,5995.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.15 5997[11:Spt:5996.2] || -> xuntil6(s3)*. % 75.92/76.15 5998[11:MRR:173.0,5997.0] || -> until5(s4)*. % 75.92/76.15 5999[11:MRR:3212.0,5998.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.15 6000[12:Spt:5999.2] || -> xuntil6(s4)*. % 75.92/76.15 6001[12:MRR:172.0,6000.0] || -> until5(s5)*. % 75.92/76.15 6002[12:MRR:3211.0,6001.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.15 6006[13:Spt:6002.2] || -> xuntil6(s5)*. % 75.92/76.15 6007[13:MRR:171.0,6006.0] || -> until5(s6)*. % 75.92/76.15 6008[13:MRR:3204.0,6007.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.15 6009[14:Spt:6008.2] || -> xuntil6(s6)*. % 75.92/76.15 6010[14:MRR:170.0,6009.0] || -> until5(s7)*. % 75.92/76.15 6011[14:MRR:3200.0,6010.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.15 6015[15:Spt:6011.2] || -> xuntil6(s7)*. % 75.92/76.15 6016[15:MRR:169.0,6015.0] || -> until5(s8)*. % 75.92/76.15 6017[15:MRR:3196.0,6016.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.15 6018[16:Spt:6017.2] || -> xuntil6(s8)*. % 75.92/76.15 6019[16:MRR:168.0,6018.0] || -> until5(s9)*. % 75.92/76.15 6020[16:MRR:3192.0,6019.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.15 6024[17:Spt:6020.2] || -> xuntil6(s9)*. % 75.92/76.15 6025[17:MRR:167.0,6024.0] || -> until5(s10)*. % 75.92/76.15 6026[17:MRR:3191.0,6025.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.15 6027[18:Spt:6026.2] || -> xuntil6(s10)*. % 75.92/76.15 6028[18:MRR:166.0,6027.0] || -> until5(s11)*. % 75.92/76.15 6029[18:MRR:3184.0,6028.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.15 6033[19:Spt:6029.2] || -> xuntil6(s11)*. % 75.92/76.15 6034[19:MRR:165.0,6033.0] || -> until5(s12)*. % 75.92/76.15 6035[19:MRR:3180.0,6034.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.15 6036[20:Spt:6035.2] || -> xuntil6(s12)*. % 75.92/76.15 6037[20:MRR:164.0,6036.0] || -> until5(s13)*. % 75.92/76.15 6038[20:MRR:3176.0,6037.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.15 6042[21:Spt:6038.2] || -> xuntil6(s13)*. % 75.92/76.15 6043[21:MRR:163.0,6042.0] || -> until5(s14)*. % 75.92/76.15 6044[21:MRR:3172.0,6043.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.15 6045[22:Spt:6044.2] || -> xuntil6(s14)*. % 75.92/76.15 6046[22:MRR:162.0,6045.0] || -> until5(s15)*. % 75.92/76.15 6047[22:MRR:3171.0,6046.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.15 6051[23:Spt:6047.2] || -> xuntil6(s15)*. % 75.92/76.15 6052[23:MRR:161.0,6051.0] || -> until5(s16)*. % 75.92/76.15 6053[23:MRR:3164.0,6052.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.15 6054[24:Spt:6053.2] || -> xuntil6(s16)*. % 75.92/76.15 6055[24:MRR:160.0,6054.0] || -> until5(s17)*. % 75.92/76.15 6056[24:MRR:3160.0,6055.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.15 6060[25:Spt:6056.2] || -> xuntil6(s17)*. % 75.92/76.15 6061[25:MRR:159.0,6060.0] || -> until5(s18)*. % 75.92/76.15 6062[25:MRR:3156.0,6061.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.15 6063[26:Spt:6062.2] || -> xuntil6(s18)*. % 75.92/76.15 6064[26:MRR:158.0,6063.0] || -> until5(s19)*. % 75.92/76.15 6065[26:MRR:3152.0,6064.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.15 6069[27:Spt:6065.2] || -> xuntil6(s19)*. % 75.92/76.15 6070[27:MRR:157.0,6069.0] || -> until5(s20)*. % 75.92/76.15 6071[27:MRR:3151.0,6070.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.15 6072[28:Spt:6071.2] || -> xuntil6(s20)*. % 75.92/76.15 6073[28:MRR:156.0,6072.0] || -> until5(s21)*. % 75.92/76.15 6074[28:MRR:3144.0,6073.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.15 6078[29:Spt:6074.2] || -> xuntil6(s21)*. % 75.92/76.15 6079[29:MRR:155.0,6078.0] || -> until5(s22)*. % 75.92/76.15 6080[29:MRR:3140.0,6079.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.15 6081[30:Spt:6080.2] || -> xuntil6(s22)*. % 75.92/76.15 6082[30:MRR:154.0,6081.0] || -> until5(s23)*. % 75.92/76.15 6083[30:MRR:3136.0,6082.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.15 6087[31:Spt:6083.2] || -> xuntil6(s23)*. % 75.92/76.15 6088[31:MRR:153.0,6087.0] || -> until5(s24)*. % 75.92/76.15 6089[31:MRR:3132.0,6088.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.15 6090[32:Spt:6089.2] || -> xuntil6(s24)*. % 75.92/76.15 6091[32:MRR:152.0,6090.0] || -> until5(s25)*. % 75.92/76.15 6092[32:MRR:3131.0,6091.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.15 6096[33:Spt:6092.2] || -> xuntil6(s25)*. % 75.92/76.15 6097[33:MRR:151.0,6096.0] || -> until5(s26)*. % 75.92/76.15 6098[33:MRR:3124.0,6097.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.15 6099[34:Spt:6098.2] || -> xuntil6(s26)*. % 75.92/76.15 6100[34:MRR:150.0,6099.0] || -> until5(s27)*. % 75.92/76.15 6101[34:MRR:3120.0,6100.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.15 6105[35:Spt:6101.2] || -> xuntil6(s27)*. % 75.92/76.15 6106[35:MRR:149.0,6105.0] || -> until5(s28)*. % 75.92/76.15 6107[35:MRR:3116.0,6106.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.15 6108[36:Spt:6107.2] || -> xuntil6(s28)*. % 75.92/76.15 6109[36:MRR:148.0,6108.0] || -> until5(s29)*. % 75.92/76.15 6110[36:MRR:3112.0,6109.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.15 6114[37:Spt:6110.2] || -> xuntil6(s29)*. % 75.92/76.15 6115[37:MRR:147.0,6114.0] || -> until5(s30)*. % 75.92/76.15 6116[37:MRR:3111.0,6115.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.15 6117[38:Spt:6116.2] || -> xuntil6(s30)*. % 75.92/76.15 6118[38:MRR:146.0,6117.0] || -> until5(s31)*. % 75.92/76.15 6119[38:MRR:3107.0,6118.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.15 6123[39:Spt:6119.2] || -> xuntil6(s31)*. % 75.92/76.15 6124[39:MRR:145.0,6123.0] || -> until5(s32)*. % 75.92/76.15 6125[39:MRR:3106.0,6124.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.15 6126[40:Spt:6125.2] || -> xuntil6(s32)*. % 75.92/76.15 6127[40:MRR:144.0,6126.0] || -> until5(s33)*. % 75.92/76.15 6128[40:MRR:932.0,6127.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.15 6132[41:Spt:6128.1] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.15 6134[41:Res:6132.0,61.1] always3(s34) || -> . % 75.92/76.15 6135[41:SSi:6134.0,723.0] || -> . % 75.92/76.15 6136[41:Spt:6135.0,6128.1,6132.0] || m_main_v_state(s34,c_busy)*+ -> . % 75.92/76.15 6137[41:Spt:6135.0,6128.0,6128.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 75.92/76.15 6140[41:Res:53.1,6137.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 75.92/76.15 6142[42:Spt:6140.1] || -> xuntil6(s33)*. % 75.92/76.15 6143[42:MRR:143.0,6142.0] || -> until5(s34)*. % 75.92/76.15 6144[42:MRR:3231.0,6143.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.15 6149[43:Spt:6144.2] || -> xuntil6(s34)*. % 75.92/76.15 6150[43:MRR:142.0,6149.0] || -> until5(s35)*. % 75.92/76.15 6151[43:MRR:930.0,6150.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.15 6152[44:Spt:6151.1] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.15 6154[44:Res:6152.0,61.1] always3(s36) || -> . % 75.92/76.15 6155[44:SSi:6154.0,725.0] || -> . % 75.92/76.15 6156[44:Spt:6155.0,6151.1,6152.0] || m_main_v_state(s36,c_busy)*+ -> . % 75.92/76.15 6157[44:Spt:6155.0,6151.0,6151.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 75.92/76.15 6160[44:Res:53.1,6157.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 75.92/76.15 6162[45:Spt:6160.1] || -> xuntil6(s35)*. % 75.92/76.15 6163[45:MRR:141.0,6162.0] || -> until5(s36)*. % 75.92/76.15 6164[45:MRR:3235.0,6163.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.15 6172[46:Spt:6164.2] || -> xuntil6(s36)*. % 75.92/76.15 6173[46:MRR:140.0,6172.0] || -> until5(s37)*. % 75.92/76.15 6174[46:MRR:928.0,6173.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.15 6175[47:Spt:6174.1] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.15 6177[47:Res:6175.0,61.1] always3(s38) || -> . % 75.92/76.15 6178[47:SSi:6177.0,727.0] || -> . % 75.92/76.15 6179[47:Spt:6178.0,6174.1,6175.0] || m_main_v_state(s38,c_busy)*+ -> . % 75.92/76.15 6180[47:Spt:6178.0,6174.0,6174.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 75.92/76.15 6183[47:Res:53.1,6180.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 75.92/76.15 6188[48:Spt:6183.1] || -> xuntil6(s37)*. % 75.92/76.15 6189[48:MRR:139.0,6188.0] || -> until5(s38)*. % 75.92/76.15 6190[48:MRR:3242.0,6189.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.15 6192[49:Spt:6190.2] || -> xuntil6(s38)*. % 75.92/76.15 6193[49:MRR:138.0,6192.0] || -> until5(s39)*. % 75.92/76.15 6194[49:MRR:926.0,6193.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.15 6195[50:Spt:6194.1] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.15 6197[50:Res:6195.0,61.1] always3(s40) || -> . % 75.92/76.15 6198[50:SSi:6197.0,729.0] || -> . % 75.92/76.15 6199[50:Spt:6198.0,6194.1,6195.0] || m_main_v_state(s40,c_busy)*+ -> . % 75.92/76.15 6200[50:Spt:6198.0,6194.0,6194.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 75.92/76.15 6203[50:Res:53.1,6200.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 75.92/76.15 6205[51:Spt:6203.1] || -> xuntil6(s39)*. % 75.92/76.15 6206[51:MRR:137.0,6205.0] || -> until5(s40)*. % 75.92/76.15 6207[51:MRR:3243.0,6206.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.15 6212[52:Spt:6207.2] || -> xuntil6(s40)*. % 75.92/76.15 6213[52:MRR:136.0,6212.0] || -> until5(s41)*. % 75.92/76.15 6214[52:MRR:924.0,6213.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.15 6215[53:Spt:6214.1] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.15 6217[53:Res:6215.0,61.1] always3(s42) || -> . % 75.92/76.15 6218[53:SSi:6217.0,731.0] || -> . % 75.92/76.15 6219[53:Spt:6218.0,6214.1,6215.0] || m_main_v_state(s42,c_busy)*+ -> . % 75.92/76.15 6220[53:Spt:6218.0,6214.0,6214.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 75.92/76.15 6223[53:Res:53.1,6220.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 75.92/76.15 6225[54:Spt:6223.1] || -> xuntil6(s41)*. % 75.92/76.15 6226[54:MRR:135.0,6225.0] || -> until5(s42)*. % 75.92/76.15 6227[54:MRR:3247.0,6226.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.15 6235[55:Spt:6227.2] || -> xuntil6(s42)*. % 75.92/76.15 6236[55:MRR:134.0,6235.0] || -> until5(s43)*. % 75.92/76.15 6237[55:MRR:922.0,6236.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.15 6238[56:Spt:6237.1] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.15 6240[56:Res:6238.0,61.1] always3(s44) || -> . % 75.92/76.15 6241[56:SSi:6240.0,733.0] || -> . % 75.92/76.15 6242[56:Spt:6241.0,6237.1,6238.0] || m_main_v_state(s44,c_busy)*+ -> . % 75.92/76.15 6243[56:Spt:6241.0,6237.0,6237.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 75.92/76.15 6246[56:MRR:5984.2,6242.0] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.15 6247[56:Res:53.1,6243.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 75.92/76.15 6252[57:Spt:6247.1] || -> xuntil6(s43)*. % 75.92/76.15 6253[57:MRR:133.0,6252.0] || -> until5(s44)*. % 75.92/76.15 6254[57:MRR:3251.0,6253.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.15 6257[56:SoR:6246.0,64.1] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.15 6262[56:SoR:6257.0,66.2] until5(s49) || m_main_v_state(s49,c_ready)* -> xuntil6(s49). % 75.92/76.15 6263[58:Spt:6254.2] || -> xuntil6(s44)*. % 75.92/76.15 6264[58:MRR:132.0,6263.0] || -> until5(s45)*. % 75.92/76.15 6265[58:MRR:920.0,6264.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.15 6269[59:Spt:6265.1] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.15 6271[59:Res:6269.0,61.1] always3(s46) || -> . % 75.92/76.15 6272[59:SSi:6271.0,735.0] || -> . % 75.92/76.15 6273[59:Spt:6272.0,6265.1,6269.0] || m_main_v_state(s46,c_busy)*+ -> . % 75.92/76.15 6274[59:Spt:6272.0,6265.0,6265.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 75.92/76.15 6276[59:MRR:783.2,6273.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 75.92/76.15 6277[59:Res:53.1,6274.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 75.92/76.15 6279[60:Spt:6277.1] || -> xuntil6(s45)*. % 75.92/76.15 6280[60:MRR:131.0,6279.0] || -> until5(s46)*. % 75.92/76.15 6281[60:MRR:3255.0,6280.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.15 6286[61:Spt:6281.2] || -> xuntil6(s46)*. % 75.92/76.15 6287[61:MRR:130.0,6286.0] || -> until5(s47)*. % 75.92/76.15 6288[61:MRR:918.0,6287.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.15 6289[62:Spt:6288.1] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.15 6291[62:Res:6289.0,61.1] always3(s48) || -> . % 75.92/76.15 6292[62:SSi:6291.0,737.0] || -> . % 75.92/76.15 6293[62:Spt:6292.0,6288.1,6289.0] || m_main_v_state(s48,c_busy)*+ -> . % 75.92/76.15 6294[62:Spt:6292.0,6288.0,6288.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 75.92/76.15 6296[62:MRR:777.2,6293.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 75.92/76.15 6297[62:Res:53.1,6294.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 75.92/76.15 6299[63:Spt:6297.1] || -> xuntil6(s47)*. % 75.92/76.15 6300[63:MRR:129.0,6299.0] || -> until5(s48)*. % 75.92/76.15 6301[63:MRR:3259.0,6300.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.15 6309[64:Spt:6301.2] || -> xuntil6(s48)*. % 75.92/76.15 6310[64:MRR:128.0,6309.0] || -> until5(s49)*. % 75.92/76.15 6311[64:MRR:6262.0,6310.0] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.15 6312[64:Res:53.1,6311.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.15 6314[65:Spt:6312.1] || -> xuntil6(s49)*. % 75.92/76.15 6315[65:MRR:5983.0,6314.0] || -> until2p7(s44)*. % 75.92/76.15 6316[65:MRR:539.0,6315.0] || -> until2p7(s45)* node4(s44). % 75.92/76.15 6317[66:Spt:6316.0] || -> until2p7(s45)*. % 75.92/76.15 6318[66:MRR:544.0,6317.0] || -> until2p7(s46)* node4(s45). % 75.92/76.15 6319[67:Spt:6318.0] || -> until2p7(s46)*. % 75.92/76.15 6320[67:MRR:549.0,6319.0] || -> until2p7(s47)* node4(s46). % 75.92/76.15 6321[68:Spt:6320.0] || -> until2p7(s47)*. % 75.92/76.15 6322[68:MRR:554.0,6321.0] || -> until2p7(s48)* node4(s47). % 75.92/76.15 6323[69:Spt:6322.0] || -> until2p7(s48)*. % 75.92/76.15 6324[69:MRR:559.0,6323.0] || -> until2p7(s49)* node4(s48). % 75.92/76.15 6325[70:Spt:6324.0] || -> until2p7(s49)*. % 75.92/76.15 6326[70:MRR:194.0,6325.0] || -> node4(s49)*. % 75.92/76.15 6327[70:MRR:6257.0,6326.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.15 6328[70:Res:53.1,6327.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 6331[70:Res:6328.0,61.1] always3(s49) || -> . % 75.92/76.15 6332[70:SSi:6331.0,50.0,738.0,6310.0,6314.0,6325.0,6326.0] || -> . % 75.92/76.15 6333[70:Spt:6332.0,6324.0,6325.0] || until2p7(s49)*+ -> . % 75.92/76.15 6334[70:Spt:6332.0,6324.1] || -> node4(s48)*. % 75.92/76.15 6336[70:MRR:774.0,6334.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.15 6342[70:Res:53.1,6336.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.15 6344[70:MRR:6342.0,6293.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 6349[70:Res:6344.0,61.1] always3(s49) || -> . % 75.92/76.15 6350[70:SSi:6349.0,50.0,738.0,6310.0,6314.0] || -> . % 75.92/76.15 6351[69:Spt:6350.0,6322.0,6323.0] || until2p7(s48)*+ -> . % 75.92/76.15 6352[69:Spt:6350.0,6322.1] || -> node4(s47)*. % 75.92/76.15 6353[69:MRR:6296.0,6352.0] || m_main_v_state(s47,c_ready)*+ -> . % 75.92/76.15 6356[69:Res:53.1,6353.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 6360[69:Res:6356.0,61.1] always3(s47) || -> . % 75.92/76.15 6361[69:SSi:6360.0,736.0,6287.0,6299.0,6321.0,6352.0] || -> . % 75.92/76.15 6362[68:Spt:6361.0,6320.0,6321.0] || until2p7(s47)*+ -> . % 75.92/76.15 6363[68:Spt:6361.0,6320.1] || -> node4(s46)*. % 75.92/76.15 6365[68:MRR:780.0,6363.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.15 6376[68:Res:53.1,6365.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.15 6378[68:MRR:6376.0,6273.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 6380[68:Res:6378.0,61.1] always3(s47) || -> . % 75.92/76.15 6381[68:SSi:6380.0,736.0,6287.0,6299.0] || -> . % 75.92/76.15 6382[67:Spt:6381.0,6318.0,6319.0] || until2p7(s46)*+ -> . % 75.92/76.15 6383[67:Spt:6381.0,6318.1] || -> node4(s45)*. % 75.92/76.15 6384[67:MRR:6276.0,6383.0] || m_main_v_state(s45,c_ready)*+ -> . % 75.92/76.15 6388[67:Res:53.1,6384.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 6391[67:Res:6388.0,61.1] always3(s45) || -> . % 75.92/76.15 6392[67:SSi:6391.0,734.0,6264.0,6279.0,6317.0,6383.0] || -> . % 75.92/76.15 6393[66:Spt:6392.0,6316.0,6317.0] || until2p7(s45)*+ -> . % 75.92/76.15 6394[66:Spt:6392.0,6316.1] || -> node4(s44)*. % 75.92/76.15 6396[66:MRR:786.0,6394.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.15 6407[66:Res:53.1,6396.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.15 6409[66:MRR:6407.0,6242.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 6411[66:Res:6409.0,61.1] always3(s45) || -> . % 75.92/76.15 6412[66:SSi:6411.0,734.0,6264.0,6279.0] || -> . % 75.92/76.15 6413[65:Spt:6412.0,6312.1,6314.0] || xuntil6(s49)* -> . % 75.92/76.15 6414[65:Spt:6412.0,6312.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 6417[65:Res:6414.0,61.1] always3(s49) || -> . % 75.92/76.15 6418[65:SSi:6417.0,50.0,738.0,6310.0] || -> . % 75.92/76.15 6419[64:Spt:6418.0,6301.2,6309.0] || xuntil6(s48)*+ -> . % 75.92/76.15 6420[64:Spt:6418.0,6301.0,6301.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.15 6421[64:Res:53.1,6420.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.15 6423[64:MRR:6421.0,6293.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 6426[64:Res:6423.0,61.1] always3(s49) || -> . % 75.92/76.15 6427[64:SSi:6426.0,50.0,738.0] || -> . % 75.92/76.15 6428[63:Spt:6427.0,6297.1,6299.0] || xuntil6(s47)* -> . % 75.92/76.15 6429[63:Spt:6427.0,6297.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 6432[63:Res:6429.0,61.1] always3(s47) || -> . % 75.92/76.15 6433[63:SSi:6432.0,736.0,6287.0] || -> . % 75.92/76.15 6434[61:Spt:6433.0,6281.2,6286.0] || xuntil6(s46)*+ -> . % 75.92/76.15 6435[61:Spt:6433.0,6281.0,6281.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.15 6436[61:Res:53.1,6435.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.15 6438[61:MRR:6436.0,6273.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 6440[61:Res:6438.0,61.1] always3(s47) || -> . % 75.92/76.15 6441[61:SSi:6440.0,736.0] || -> . % 75.92/76.15 6442[60:Spt:6441.0,6277.1,6279.0] || xuntil6(s45)* -> . % 75.92/76.15 6443[60:Spt:6441.0,6277.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 6446[60:Res:6443.0,61.1] always3(s45) || -> . % 75.92/76.15 6447[60:SSi:6446.0,734.0,6264.0] || -> . % 75.92/76.15 6448[58:Spt:6447.0,6254.2,6263.0] || xuntil6(s44)*+ -> . % 75.92/76.15 6449[58:Spt:6447.0,6254.0,6254.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.15 6450[58:Res:53.1,6449.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.15 6452[58:MRR:6450.0,6242.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 6455[58:Res:6452.0,61.1] always3(s45) || -> . % 75.92/76.15 6456[58:SSi:6455.0,734.0] || -> . % 75.92/76.15 6457[57:Spt:6456.0,6247.1,6252.0] || xuntil6(s43)* -> . % 75.92/76.15 6458[57:Spt:6456.0,6247.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 6461[57:Res:6458.0,61.1] always3(s43) || -> . % 75.92/76.15 6462[57:SSi:6461.0,732.0,6236.0] || -> . % 75.92/76.15 6463[55:Spt:6462.0,6227.2,6235.0] || xuntil6(s42)*+ -> . % 75.92/76.15 6464[55:Spt:6462.0,6227.0,6227.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.15 6465[55:Res:53.1,6464.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.15 6467[55:MRR:6465.0,6219.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 6469[55:Res:6467.0,61.1] always3(s43) || -> . % 75.92/76.15 6470[55:SSi:6469.0,732.0] || -> . % 75.92/76.15 6471[54:Spt:6470.0,6223.1,6225.0] || xuntil6(s41)* -> . % 75.92/76.15 6472[54:Spt:6470.0,6223.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.15 6475[54:Res:6472.0,61.1] always3(s41) || -> . % 75.92/76.15 6476[54:SSi:6475.0,730.0,6213.0] || -> . % 75.92/76.15 6477[52:Spt:6476.0,6207.2,6212.0] || xuntil6(s40)*+ -> . % 75.92/76.15 6478[52:Spt:6476.0,6207.0,6207.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.15 6479[52:Res:53.1,6478.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.15 6481[52:MRR:6479.0,6199.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.15 6483[52:Res:6481.0,61.1] always3(s41) || -> . % 75.92/76.15 6484[52:SSi:6483.0,730.0] || -> . % 75.92/76.15 6485[51:Spt:6484.0,6203.1,6205.0] || xuntil6(s39)* -> . % 75.92/76.15 6486[51:Spt:6484.0,6203.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.15 6489[51:Res:6486.0,61.1] always3(s39) || -> . % 75.92/76.15 6490[51:SSi:6489.0,728.0,6193.0] || -> . % 75.92/76.15 6491[49:Spt:6490.0,6190.2,6192.0] || xuntil6(s38)*+ -> . % 75.92/76.15 6492[49:Spt:6490.0,6190.0,6190.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.15 6493[49:Res:53.1,6492.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.15 6495[49:MRR:6493.0,6179.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.15 6497[49:Res:6495.0,61.1] always3(s39) || -> . % 75.92/76.15 6498[49:SSi:6497.0,728.0] || -> . % 75.92/76.15 6499[48:Spt:6498.0,6183.1,6188.0] || xuntil6(s37)* -> . % 75.92/76.15 6500[48:Spt:6498.0,6183.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.15 6503[48:Res:6500.0,61.1] always3(s37) || -> . % 75.92/76.15 6504[48:SSi:6503.0,726.0,6173.0] || -> . % 75.92/76.15 6505[46:Spt:6504.0,6164.2,6172.0] || xuntil6(s36)*+ -> . % 75.92/76.15 6506[46:Spt:6504.0,6164.0,6164.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.15 6507[46:Res:53.1,6506.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.15 6509[46:MRR:6507.0,6156.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.15 6511[46:Res:6509.0,61.1] always3(s37) || -> . % 75.92/76.15 6512[46:SSi:6511.0,726.0] || -> . % 75.92/76.15 6513[45:Spt:6512.0,6160.1,6162.0] || xuntil6(s35)* -> . % 75.92/76.15 6514[45:Spt:6512.0,6160.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.15 6517[45:Res:6514.0,61.1] always3(s35) || -> . % 75.92/76.15 6518[45:SSi:6517.0,724.0,6150.0] || -> . % 75.92/76.15 6519[43:Spt:6518.0,6144.2,6149.0] || xuntil6(s34)*+ -> . % 75.92/76.15 6520[43:Spt:6518.0,6144.0,6144.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 75.92/76.15 6521[43:Res:53.1,6520.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 75.92/76.15 6523[43:MRR:6521.0,6136.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.15 6525[43:Res:6523.0,61.1] always3(s35) || -> . % 75.92/76.15 6526[43:SSi:6525.0,724.0] || -> . % 75.92/76.15 6527[42:Spt:6526.0,6140.1,6142.0] || xuntil6(s33)* -> . % 75.92/76.15 6528[42:Spt:6526.0,6140.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.15 6531[42:Res:6528.0,61.1] always3(s33) || -> . % 75.92/76.15 6532[42:SSi:6531.0,722.0,6127.0] || -> . % 75.92/76.15 6533[40:Spt:6532.0,6125.2,6126.0] || xuntil6(s32)*+ -> . % 75.92/76.15 6534[40:Spt:6532.0,6125.0,6125.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 75.92/76.15 6535[40:Res:53.1,6534.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 75.92/76.15 6537[41:Spt:6535.0] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.15 6539[41:Res:6537.0,61.1] always3(s32) || -> . % 75.92/76.15 6540[41:SSi:6539.0,721.0,6124.0] || -> . % 75.92/76.15 6541[41:Spt:6540.0,6535.0,6537.0] || m_main_v_state(s32,c_busy)* -> . % 75.92/76.15 6542[41:Spt:6540.0,6535.1] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.15 6546[41:Res:6542.0,61.1] always3(s33) || -> . % 75.92/76.15 6547[41:SSi:6546.0,722.0] || -> . % 75.92/76.15 6548[39:Spt:6547.0,6119.2,6123.0] || xuntil6(s31)*+ -> . % 75.92/76.15 6549[39:Spt:6547.0,6119.0,6119.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 75.92/76.15 6550[39:Res:53.1,6549.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 75.92/76.15 6552[40:Spt:6550.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.15 6554[40:Res:6552.0,61.1] always3(s31) || -> . % 75.92/76.15 6555[40:SSi:6554.0,720.0,6118.0] || -> . % 75.92/76.15 6556[40:Spt:6555.0,6550.0,6552.0] || m_main_v_state(s31,c_busy)* -> . % 75.92/76.15 6557[40:Spt:6555.0,6550.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.15 6561[40:Res:6557.0,61.1] always3(s32) || -> . % 75.92/76.15 6562[40:SSi:6561.0,721.0] || -> . % 75.92/76.15 6563[38:Spt:6562.0,6116.2,6117.0] || xuntil6(s30)*+ -> . % 75.92/76.15 6564[38:Spt:6562.0,6116.0,6116.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.15 6565[38:Res:53.1,6564.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.15 6567[39:Spt:6565.0] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.15 6569[39:Res:6567.0,61.1] always3(s30) || -> . % 75.92/76.15 6570[39:SSi:6569.0,719.0,6115.0] || -> . % 75.92/76.15 6571[39:Spt:6570.0,6565.0,6567.0] || m_main_v_state(s30,c_busy)* -> . % 75.92/76.15 6572[39:Spt:6570.0,6565.1] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.15 6576[39:Res:6572.0,61.1] always3(s31) || -> . % 75.92/76.15 6577[39:SSi:6576.0,720.0] || -> . % 75.92/76.15 6578[37:Spt:6577.0,6110.2,6114.0] || xuntil6(s29)*+ -> . % 75.92/76.15 6579[37:Spt:6577.0,6110.0,6110.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 75.92/76.15 6580[37:Res:53.1,6579.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 75.92/76.15 6582[38:Spt:6580.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.15 6584[38:Res:6582.0,61.1] always3(s29) || -> . % 75.92/76.15 6585[38:SSi:6584.0,718.0,6109.0] || -> . % 75.92/76.15 6586[38:Spt:6585.0,6580.0,6582.0] || m_main_v_state(s29,c_busy)* -> . % 75.92/76.15 6587[38:Spt:6585.0,6580.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.15 6591[38:Res:6587.0,61.1] always3(s30) || -> . % 75.92/76.15 6592[38:SSi:6591.0,719.0] || -> . % 75.92/76.15 6593[36:Spt:6592.0,6107.2,6108.0] || xuntil6(s28)*+ -> . % 75.92/76.15 6594[36:Spt:6592.0,6107.0,6107.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.15 6595[36:Res:53.1,6594.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.15 6597[37:Spt:6595.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.15 6599[37:Res:6597.0,61.1] always3(s28) || -> . % 75.92/76.15 6600[37:SSi:6599.0,717.0,6106.0] || -> . % 75.92/76.15 6601[37:Spt:6600.0,6595.0,6597.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.15 6602[37:Spt:6600.0,6595.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.15 6606[37:Res:6602.0,61.1] always3(s29) || -> . % 75.92/76.15 6607[37:SSi:6606.0,718.0] || -> . % 75.92/76.15 6608[35:Spt:6607.0,6101.2,6105.0] || xuntil6(s27)*+ -> . % 75.92/76.15 6609[35:Spt:6607.0,6101.0,6101.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.15 6610[35:Res:53.1,6609.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.15 6612[36:Spt:6610.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.15 6614[36:Res:6612.0,61.1] always3(s28) || -> . % 75.92/76.15 6615[36:SSi:6614.0,717.0] || -> . % 75.92/76.15 6616[36:Spt:6615.0,6610.1,6612.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.15 6617[36:Spt:6615.0,6610.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.15 6620[36:Res:6617.0,61.1] always3(s27) || -> . % 75.92/76.15 6621[36:SSi:6620.0,716.0,6100.0] || -> . % 75.92/76.15 6622[34:Spt:6621.0,6098.2,6099.0] || xuntil6(s26)*+ -> . % 75.92/76.15 6623[34:Spt:6621.0,6098.0,6098.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.15 6624[34:Res:53.1,6623.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.15 6626[35:Spt:6624.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.15 6628[35:Res:6626.0,61.1] always3(s27) || -> . % 75.92/76.15 6629[35:SSi:6628.0,716.0] || -> . % 75.92/76.15 6630[35:Spt:6629.0,6624.1,6626.0] || m_main_v_state(s27,c_busy)* -> . % 75.92/76.15 6631[35:Spt:6629.0,6624.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.15 6634[35:Res:6631.0,61.1] always3(s26) || -> . % 75.92/76.15 6635[35:SSi:6634.0,715.0,6097.0] || -> . % 75.92/76.15 6636[33:Spt:6635.0,6092.2,6096.0] || xuntil6(s25)*+ -> . % 75.92/76.15 6637[33:Spt:6635.0,6092.0,6092.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.15 6638[33:Res:53.1,6637.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.15 6640[34:Spt:6638.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.15 6642[34:Res:6640.0,61.1] always3(s26) || -> . % 75.92/76.15 6643[34:SSi:6642.0,715.0] || -> . % 75.92/76.15 6644[34:Spt:6643.0,6638.1,6640.0] || m_main_v_state(s26,c_busy)* -> . % 75.92/76.15 6645[34:Spt:6643.0,6638.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.15 6648[34:Res:6645.0,61.1] always3(s25) || -> . % 75.92/76.15 6649[34:SSi:6648.0,714.0,6091.0] || -> . % 75.92/76.15 6650[32:Spt:6649.0,6089.2,6090.0] || xuntil6(s24)*+ -> . % 75.92/76.15 6651[32:Spt:6649.0,6089.0,6089.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.15 6652[32:Res:53.1,6651.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.15 6654[33:Spt:6652.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.15 6656[33:Res:6654.0,61.1] always3(s25) || -> . % 75.92/76.15 6657[33:SSi:6656.0,714.0] || -> . % 75.92/76.15 6658[33:Spt:6657.0,6652.1,6654.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.15 6659[33:Spt:6657.0,6652.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.15 6662[33:Res:6659.0,61.1] always3(s24) || -> . % 75.92/76.15 6663[33:SSi:6662.0,713.0,6088.0] || -> . % 75.92/76.15 6664[31:Spt:6663.0,6083.2,6087.0] || xuntil6(s23)*+ -> . % 75.92/76.15 6665[31:Spt:6663.0,6083.0,6083.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.15 6666[31:Res:53.1,6665.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.15 6671[32:Spt:6666.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.15 6673[32:Res:6671.0,61.1] always3(s23) || -> . % 75.92/76.15 6674[32:SSi:6673.0,712.0,6082.0] || -> . % 75.92/76.15 6675[32:Spt:6674.0,6666.0,6671.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.15 6676[32:Spt:6674.0,6666.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.15 6680[32:Res:6676.0,61.1] always3(s24) || -> . % 75.92/76.15 6681[32:SSi:6680.0,713.0] || -> . % 75.92/76.15 6682[30:Spt:6681.0,6080.2,6081.0] || xuntil6(s22)*+ -> . % 75.92/76.15 6683[30:Spt:6681.0,6080.0,6080.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.15 6684[30:Res:53.1,6683.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.15 6686[31:Spt:6684.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.15 6688[31:Res:6686.0,61.1] always3(s23) || -> . % 75.92/76.15 6689[31:SSi:6688.0,712.0] || -> . % 75.92/76.15 6690[31:Spt:6689.0,6684.1,6686.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.15 6691[31:Spt:6689.0,6684.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.15 6694[31:Res:6691.0,61.1] always3(s22) || -> . % 75.92/76.15 6695[31:SSi:6694.0,711.0,6079.0] || -> . % 75.92/76.15 6696[29:Spt:6695.0,6074.2,6078.0] || xuntil6(s21)*+ -> . % 75.92/76.15 6697[29:Spt:6695.0,6074.0,6074.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.15 6698[29:Res:53.1,6697.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.15 6700[30:Spt:6698.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.15 6702[30:Res:6700.0,61.1] always3(s22) || -> . % 75.92/76.15 6703[30:SSi:6702.0,711.0] || -> . % 75.92/76.15 6704[30:Spt:6703.0,6698.1,6700.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.15 6705[30:Spt:6703.0,6698.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.15 6708[30:Res:6705.0,61.1] always3(s21) || -> . % 75.92/76.15 6709[30:SSi:6708.0,710.0,6073.0] || -> . % 75.92/76.15 6710[28:Spt:6709.0,6071.2,6072.0] || xuntil6(s20)*+ -> . % 75.92/76.15 6711[28:Spt:6709.0,6071.0,6071.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.15 6712[28:Res:53.1,6711.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.15 6717[29:Spt:6712.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.15 6719[29:Res:6717.0,61.1] always3(s20) || -> . % 75.92/76.15 6720[29:SSi:6719.0,709.0,6070.0] || -> . % 75.92/76.15 6721[29:Spt:6720.0,6712.0,6717.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.15 6722[29:Spt:6720.0,6712.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.15 6726[29:Res:6722.0,61.1] always3(s21) || -> . % 75.92/76.15 6727[29:SSi:6726.0,710.0] || -> . % 75.92/76.15 6728[27:Spt:6727.0,6065.2,6069.0] || xuntil6(s19)*+ -> . % 75.92/76.15 6729[27:Spt:6727.0,6065.0,6065.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.15 6730[27:Res:53.1,6729.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.15 6732[28:Spt:6730.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.15 6734[28:Res:6732.0,61.1] always3(s20) || -> . % 75.92/76.15 6735[28:SSi:6734.0,709.0] || -> . % 75.92/76.15 6736[28:Spt:6735.0,6730.1,6732.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.15 6737[28:Spt:6735.0,6730.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.15 6740[28:Res:6737.0,61.1] always3(s19) || -> . % 75.92/76.15 6741[28:SSi:6740.0,708.0,6064.0] || -> . % 75.92/76.15 6742[26:Spt:6741.0,6062.2,6063.0] || xuntil6(s18)*+ -> . % 75.92/76.15 6743[26:Spt:6741.0,6062.0,6062.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.15 6744[26:Res:53.1,6743.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.15 6746[27:Spt:6744.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.15 6748[27:Res:6746.0,61.1] always3(s19) || -> . % 75.92/76.15 6749[27:SSi:6748.0,708.0] || -> . % 75.92/76.15 6750[27:Spt:6749.0,6744.1,6746.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.15 6751[27:Spt:6749.0,6744.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.15 6754[27:Res:6751.0,61.1] always3(s18) || -> . % 75.92/76.15 6755[27:SSi:6754.0,707.0,6061.0] || -> . % 75.92/76.15 6756[25:Spt:6755.0,6056.2,6060.0] || xuntil6(s17)*+ -> . % 75.92/76.15 6757[25:Spt:6755.0,6056.0,6056.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.15 6758[25:Res:53.1,6757.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.15 6763[26:Spt:6758.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.15 6765[26:Res:6763.0,61.1] always3(s17) || -> . % 75.92/76.15 6766[26:SSi:6765.0,706.0,6055.0] || -> . % 75.92/76.15 6767[26:Spt:6766.0,6758.0,6763.0] || m_main_v_state(s17,c_busy)* -> . % 75.92/76.15 6768[26:Spt:6766.0,6758.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.15 6772[26:Res:6768.0,61.1] always3(s18) || -> . % 75.92/76.15 6773[26:SSi:6772.0,707.0] || -> . % 75.92/76.15 6774[24:Spt:6773.0,6053.2,6054.0] || xuntil6(s16)*+ -> . % 75.92/76.15 6775[24:Spt:6773.0,6053.0,6053.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.15 6776[24:Res:53.1,6775.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.15 6778[25:Spt:6776.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.15 6780[25:Res:6778.0,61.1] always3(s17) || -> . % 75.92/76.15 6781[25:SSi:6780.0,706.0] || -> . % 75.92/76.15 6782[25:Spt:6781.0,6776.1,6778.0] || m_main_v_state(s17,c_busy)* -> . % 75.92/76.15 6783[25:Spt:6781.0,6776.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.15 6786[25:Res:6783.0,61.1] always3(s16) || -> . % 75.92/76.15 6787[25:SSi:6786.0,705.0,6052.0] || -> . % 75.92/76.15 6788[23:Spt:6787.0,6047.2,6051.0] || xuntil6(s15)*+ -> . % 75.92/76.15 6789[23:Spt:6787.0,6047.0,6047.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.15 6790[23:Res:53.1,6789.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.15 6792[24:Spt:6790.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.15 6794[24:Res:6792.0,61.1] always3(s16) || -> . % 75.92/76.15 6795[24:SSi:6794.0,705.0] || -> . % 75.92/76.15 6796[24:Spt:6795.0,6790.1,6792.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.15 6797[24:Spt:6795.0,6790.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.15 6800[24:Res:6797.0,61.1] always3(s15) || -> . % 75.92/76.15 6801[24:SSi:6800.0,704.0,6046.0] || -> . % 75.92/76.15 6802[22:Spt:6801.0,6044.2,6045.0] || xuntil6(s14)*+ -> . % 75.92/76.15 6803[22:Spt:6801.0,6044.0,6044.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.15 6804[22:Res:53.1,6803.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.15 6809[23:Spt:6804.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.15 6811[23:Res:6809.0,61.1] always3(s14) || -> . % 75.92/76.15 6812[23:SSi:6811.0,703.0,6043.0] || -> . % 75.92/76.15 6813[23:Spt:6812.0,6804.0,6809.0] || m_main_v_state(s14,c_busy)* -> . % 75.92/76.15 6814[23:Spt:6812.0,6804.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.15 6818[23:Res:6814.0,61.1] always3(s15) || -> . % 75.92/76.15 6819[23:SSi:6818.0,704.0] || -> . % 75.92/76.15 6820[21:Spt:6819.0,6038.2,6042.0] || xuntil6(s13)*+ -> . % 75.92/76.15 6821[21:Spt:6819.0,6038.0,6038.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.15 6822[21:Res:53.1,6821.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.15 6824[22:Spt:6822.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.15 6826[22:Res:6824.0,61.1] always3(s14) || -> . % 75.92/76.15 6827[22:SSi:6826.0,703.0] || -> . % 75.92/76.15 6828[22:Spt:6827.0,6822.1,6824.0] || m_main_v_state(s14,c_busy)* -> . % 75.92/76.15 6829[22:Spt:6827.0,6822.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.15 6832[22:Res:6829.0,61.1] always3(s13) || -> . % 75.92/76.15 6833[22:SSi:6832.0,702.0,6037.0] || -> . % 75.92/76.15 6834[20:Spt:6833.0,6035.2,6036.0] || xuntil6(s12)*+ -> . % 75.92/76.15 6835[20:Spt:6833.0,6035.0,6035.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.15 6836[20:Res:53.1,6835.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.15 6838[21:Spt:6836.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.15 6840[21:Res:6838.0,61.1] always3(s13) || -> . % 75.92/76.15 6841[21:SSi:6840.0,702.0] || -> . % 75.92/76.15 6842[21:Spt:6841.0,6836.1,6838.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.15 6843[21:Spt:6841.0,6836.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.15 6846[21:Res:6843.0,61.1] always3(s12) || -> . % 75.92/76.15 6847[21:SSi:6846.0,701.0,6034.0] || -> . % 75.92/76.15 6848[19:Spt:6847.0,6029.2,6033.0] || xuntil6(s11)*+ -> . % 75.92/76.15 6849[19:Spt:6847.0,6029.0,6029.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.15 6850[19:Res:53.1,6849.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.15 6855[20:Spt:6850.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.15 6857[20:Res:6855.0,61.1] always3(s11) || -> . % 75.92/76.15 6858[20:SSi:6857.0,700.0,6028.0] || -> . % 75.92/76.15 6859[20:Spt:6858.0,6850.0,6855.0] || m_main_v_state(s11,c_busy)* -> . % 75.92/76.15 6860[20:Spt:6858.0,6850.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.15 6864[20:Res:6860.0,61.1] always3(s12) || -> . % 75.92/76.15 6865[20:SSi:6864.0,701.0] || -> . % 75.92/76.15 6866[18:Spt:6865.0,6026.2,6027.0] || xuntil6(s10)*+ -> . % 75.92/76.15 6867[18:Spt:6865.0,6026.0,6026.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.15 6868[18:Res:53.1,6867.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.15 6870[19:Spt:6868.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.15 6872[19:Res:6870.0,61.1] always3(s11) || -> . % 75.92/76.15 6873[19:SSi:6872.0,700.0] || -> . % 75.92/76.15 6874[19:Spt:6873.0,6868.1,6870.0] || m_main_v_state(s11,c_busy)* -> . % 75.92/76.15 6875[19:Spt:6873.0,6868.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.15 6878[19:Res:6875.0,61.1] always3(s10) || -> . % 75.92/76.15 6879[19:SSi:6878.0,699.0,6025.0] || -> . % 75.92/76.15 6880[17:Spt:6879.0,6020.2,6024.0] || xuntil6(s9)*+ -> . % 75.92/76.15 6881[17:Spt:6879.0,6020.0,6020.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.15 6882[17:Res:53.1,6881.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.15 6884[18:Spt:6882.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.15 6886[18:Res:6884.0,61.1] always3(s10) || -> . % 75.92/76.15 6887[18:SSi:6886.0,699.0] || -> . % 75.92/76.15 6888[18:Spt:6887.0,6882.1,6884.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.15 6889[18:Spt:6887.0,6882.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.15 6892[18:Res:6889.0,61.1] always3(s9) || -> . % 75.92/76.15 6893[18:SSi:6892.0,698.0,6019.0] || -> . % 75.92/76.15 6894[16:Spt:6893.0,6017.2,6018.0] || xuntil6(s8)*+ -> . % 75.92/76.15 6895[16:Spt:6893.0,6017.0,6017.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.15 6896[16:Res:53.1,6895.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.15 6901[17:Spt:6896.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.15 6903[17:Res:6901.0,61.1] always3(s8) || -> . % 75.92/76.15 6904[17:SSi:6903.0,697.0,6016.0] || -> . % 75.92/76.15 6905[17:Spt:6904.0,6896.0,6901.0] || m_main_v_state(s8,c_busy)* -> . % 75.92/76.15 6906[17:Spt:6904.0,6896.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.15 6910[17:Res:6906.0,61.1] always3(s9) || -> . % 75.92/76.15 6911[17:SSi:6910.0,698.0] || -> . % 75.92/76.15 6912[15:Spt:6911.0,6011.2,6015.0] || xuntil6(s7)*+ -> . % 75.92/76.15 6913[15:Spt:6911.0,6011.0,6011.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.15 6914[15:Res:53.1,6913.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.15 6916[16:Spt:6914.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.15 6918[16:Res:6916.0,61.1] always3(s8) || -> . % 75.92/76.15 6919[16:SSi:6918.0,697.0] || -> . % 75.92/76.15 6920[16:Spt:6919.0,6914.1,6916.0] || m_main_v_state(s8,c_busy)* -> . % 75.92/76.15 6921[16:Spt:6919.0,6914.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.15 6924[16:Res:6921.0,61.1] always3(s7) || -> . % 75.92/76.15 6925[16:SSi:6924.0,696.0,6010.0] || -> . % 75.92/76.15 6926[14:Spt:6925.0,6008.2,6009.0] || xuntil6(s6)*+ -> . % 75.92/76.15 6927[14:Spt:6925.0,6008.0,6008.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.15 6928[14:Res:53.1,6927.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.15 6930[15:Spt:6928.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.15 6932[15:Res:6930.0,61.1] always3(s7) || -> . % 75.92/76.15 6933[15:SSi:6932.0,696.0] || -> . % 75.92/76.15 6934[15:Spt:6933.0,6928.1,6930.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.15 6935[15:Spt:6933.0,6928.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.15 6938[15:Res:6935.0,61.1] always3(s6) || -> . % 75.92/76.15 6939[15:SSi:6938.0,695.0,6007.0] || -> . % 75.92/76.15 6940[13:Spt:6939.0,6002.2,6006.0] || xuntil6(s5)*+ -> . % 75.92/76.15 6941[13:Spt:6939.0,6002.0,6002.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.15 6942[13:Res:53.1,6941.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.15 6947[14:Spt:6942.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.15 6949[14:Res:6947.0,61.1] always3(s5) || -> . % 75.92/76.15 6950[14:SSi:6949.0,694.0,6001.0] || -> . % 75.92/76.15 6951[14:Spt:6950.0,6942.0,6947.0] || m_main_v_state(s5,c_busy)* -> . % 75.92/76.15 6952[14:Spt:6950.0,6942.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.15 6956[14:Res:6952.0,61.1] always3(s6) || -> . % 75.92/76.15 6957[14:SSi:6956.0,695.0] || -> . % 75.92/76.15 6958[12:Spt:6957.0,5999.2,6000.0] || xuntil6(s4)*+ -> . % 75.92/76.15 6959[12:Spt:6957.0,5999.0,5999.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.15 6960[12:Res:53.1,6959.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.15 6962[13:Spt:6960.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.15 6964[13:Res:6962.0,61.1] always3(s5) || -> . % 75.92/76.15 6965[13:SSi:6964.0,694.0] || -> . % 75.92/76.15 6966[13:Spt:6965.0,6960.1,6962.0] || m_main_v_state(s5,c_busy)* -> . % 75.92/76.15 6967[13:Spt:6965.0,6960.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.15 6970[13:Res:6967.0,61.1] always3(s4) || -> . % 75.92/76.15 6971[13:SSi:6970.0,693.0,5998.0] || -> . % 75.92/76.15 6972[11:Spt:6971.0,5996.2,5997.0] || xuntil6(s3)*+ -> . % 75.92/76.15 6973[11:Spt:6971.0,5996.0,5996.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.15 6974[11:Res:53.1,6973.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.15 6976[12:Spt:6974.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.15 6978[12:Res:6976.0,61.1] always3(s4) || -> . % 75.92/76.15 6979[12:SSi:6978.0,693.0] || -> . % 75.92/76.15 6980[12:Spt:6979.0,6974.1,6976.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.15 6981[12:Spt:6979.0,6974.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.15 6984[12:Res:6981.0,61.1] always3(s3) || -> . % 75.92/76.15 6985[12:SSi:6984.0,692.0,5995.0] || -> . % 75.92/76.15 6986[10:Spt:6985.0,5993.2,5994.0] || xuntil6(s2)*+ -> . % 75.92/76.15 6987[10:Spt:6985.0,5993.0,5993.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.15 6988[10:Res:53.1,6987.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.15 6993[11:Spt:6988.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.15 6995[11:Res:6993.0,61.1] always3(s2) || -> . % 75.92/76.15 6996[11:SSi:6995.0,691.0,5992.0] || -> . % 75.92/76.15 6997[11:Spt:6996.0,6988.0,6993.0] || m_main_v_state(s2,c_busy)* -> . % 75.92/76.15 6998[11:Spt:6996.0,6988.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.15 7002[11:Res:6998.0,61.1] always3(s3) || -> . % 75.92/76.15 7003[11:SSi:7002.0,692.0] || -> . % 75.92/76.15 7004[9:Spt:7003.0,5987.2,5991.0] || xuntil6(s1)*+ -> . % 75.92/76.15 7005[9:Spt:7003.0,5987.0,5987.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.15 7006[9:Res:53.1,7005.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.15 7008[10:Spt:7006.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.15 7010[10:Res:7008.0,61.1] always3(s1) || -> . % 75.92/76.15 7011[10:SSi:7010.0,690.0,5986.0] || -> . % 75.92/76.15 7012[10:Spt:7011.0,7006.0,7008.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.15 7013[10:Spt:7011.0,7006.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.15 7018[10:Res:7013.0,61.1] always3(s2) || -> . % 75.92/76.15 7019[10:SSi:7018.0,691.0] || -> . % 75.92/76.15 7020[8:Spt:7019.0,74.0,5985.0] || xuntil6(s0)*+ -> . % 75.92/76.15 7021[8:Spt:7019.0,74.1] || -> node4(s0)*. % 75.92/76.15 7022[8:MRR:758.1,7020.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.15 7024[8:Res:7022.0,61.1] always3(s1) || -> . % 75.92/76.15 7025[8:SSi:7024.0,690.0] || -> . % 75.92/76.15 7026[7:Spt:7025.0,5975.0,5979.0] || trans(s49,s44)*+ -> . % 75.92/76.15 7027[7:Spt:7025.0,5975.1,5975.2,5975.3,5975.4,5975.5,5975.6,5975.7,5975.8,5975.9,5975.10,5975.11,5975.12,5975.13,5975.14,5975.15,5975.16,5975.17,5975.18,5975.19,5975.20,5975.21,5975.22,5975.23,5975.24,5975.25,5975.26,5975.27,5975.28,5975.29,5975.30,5975.31,5975.32,5975.33,5975.34,5975.35,5975.36,5975.37,5975.38,5975.39,5975.40,5975.41,5975.42,5975.43,5975.44] || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.15 7029[7:MRR:5976.0,7026.0] || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.15 7030[7:MRR:5978.1,7026.0] xuntil6(s49) || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.15 7031[8:Spt:7027.0] || -> trans(s49,s43)*. % 75.92/76.15 7032[8:Res:7031.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s43)*. % 75.92/76.15 7034[8:Res:7031.0,60.0] || -> node2(s49,s43)*. % 75.92/76.15 7035[8:SSi:7032.1,50.0,738.0] xuntil6(s49) || -> until2p7(s43)*. % 75.92/76.15 7036[8:Res:7034.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 7037[9:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.15 7038[9:MRR:176.0,7037.0] || -> until5(s1)*. % 75.92/76.15 7039[9:MRR:3224.0,7038.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.15 7046[10:Spt:7039.2] || -> xuntil6(s1)*. % 75.92/76.15 7047[10:MRR:175.0,7046.0] || -> until5(s2)*. % 75.92/76.15 7048[10:MRR:3220.0,7047.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.15 7049[11:Spt:7048.2] || -> xuntil6(s2)*. % 75.92/76.15 7050[11:MRR:174.0,7049.0] || -> until5(s3)*. % 75.92/76.15 7051[11:MRR:3216.0,7050.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.15 7055[12:Spt:7051.2] || -> xuntil6(s3)*. % 75.92/76.15 7056[12:MRR:173.0,7055.0] || -> until5(s4)*. % 75.92/76.15 7057[12:MRR:3212.0,7056.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.15 7058[13:Spt:7057.2] || -> xuntil6(s4)*. % 75.92/76.15 7059[13:MRR:172.0,7058.0] || -> until5(s5)*. % 75.92/76.15 7060[13:MRR:3211.0,7059.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.15 7064[14:Spt:7060.2] || -> xuntil6(s5)*. % 75.92/76.15 7065[14:MRR:171.0,7064.0] || -> until5(s6)*. % 75.92/76.15 7066[14:MRR:3204.0,7065.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.15 7067[15:Spt:7066.2] || -> xuntil6(s6)*. % 75.92/76.15 7068[15:MRR:170.0,7067.0] || -> until5(s7)*. % 75.92/76.15 7069[15:MRR:3200.0,7068.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.15 7073[16:Spt:7069.2] || -> xuntil6(s7)*. % 75.92/76.15 7074[16:MRR:169.0,7073.0] || -> until5(s8)*. % 75.92/76.15 7075[16:MRR:3196.0,7074.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.15 7076[17:Spt:7075.2] || -> xuntil6(s8)*. % 75.92/76.15 7077[17:MRR:168.0,7076.0] || -> until5(s9)*. % 75.92/76.15 7078[17:MRR:3192.0,7077.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.15 7082[18:Spt:7078.2] || -> xuntil6(s9)*. % 75.92/76.15 7083[18:MRR:167.0,7082.0] || -> until5(s10)*. % 75.92/76.15 7084[18:MRR:3191.0,7083.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.15 7085[19:Spt:7084.2] || -> xuntil6(s10)*. % 75.92/76.15 7086[19:MRR:166.0,7085.0] || -> until5(s11)*. % 75.92/76.15 7087[19:MRR:3184.0,7086.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.15 7091[20:Spt:7087.2] || -> xuntil6(s11)*. % 75.92/76.15 7092[20:MRR:165.0,7091.0] || -> until5(s12)*. % 75.92/76.15 7093[20:MRR:3180.0,7092.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.15 7094[21:Spt:7093.2] || -> xuntil6(s12)*. % 75.92/76.15 7095[21:MRR:164.0,7094.0] || -> until5(s13)*. % 75.92/76.15 7096[21:MRR:3176.0,7095.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.15 7100[22:Spt:7096.2] || -> xuntil6(s13)*. % 75.92/76.15 7101[22:MRR:163.0,7100.0] || -> until5(s14)*. % 75.92/76.15 7102[22:MRR:3172.0,7101.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.15 7103[23:Spt:7102.2] || -> xuntil6(s14)*. % 75.92/76.15 7104[23:MRR:162.0,7103.0] || -> until5(s15)*. % 75.92/76.15 7105[23:MRR:3171.0,7104.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.15 7109[24:Spt:7105.2] || -> xuntil6(s15)*. % 75.92/76.15 7110[24:MRR:161.0,7109.0] || -> until5(s16)*. % 75.92/76.15 7111[24:MRR:3164.0,7110.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.15 7112[25:Spt:7111.2] || -> xuntil6(s16)*. % 75.92/76.15 7113[25:MRR:160.0,7112.0] || -> until5(s17)*. % 75.92/76.15 7114[25:MRR:3160.0,7113.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.15 7118[26:Spt:7114.2] || -> xuntil6(s17)*. % 75.92/76.15 7119[26:MRR:159.0,7118.0] || -> until5(s18)*. % 75.92/76.15 7120[26:MRR:3156.0,7119.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.15 7121[27:Spt:7120.2] || -> xuntil6(s18)*. % 75.92/76.15 7122[27:MRR:158.0,7121.0] || -> until5(s19)*. % 75.92/76.15 7123[27:MRR:3152.0,7122.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.15 7127[28:Spt:7123.2] || -> xuntil6(s19)*. % 75.92/76.15 7128[28:MRR:157.0,7127.0] || -> until5(s20)*. % 75.92/76.15 7129[28:MRR:3151.0,7128.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.15 7130[29:Spt:7129.2] || -> xuntil6(s20)*. % 75.92/76.15 7131[29:MRR:156.0,7130.0] || -> until5(s21)*. % 75.92/76.15 7132[29:MRR:3144.0,7131.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.15 7136[30:Spt:7132.2] || -> xuntil6(s21)*. % 75.92/76.15 7137[30:MRR:155.0,7136.0] || -> until5(s22)*. % 75.92/76.15 7138[30:MRR:3140.0,7137.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.15 7139[31:Spt:7138.2] || -> xuntil6(s22)*. % 75.92/76.15 7140[31:MRR:154.0,7139.0] || -> until5(s23)*. % 75.92/76.15 7141[31:MRR:3136.0,7140.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.15 7145[32:Spt:7141.2] || -> xuntil6(s23)*. % 75.92/76.15 7146[32:MRR:153.0,7145.0] || -> until5(s24)*. % 75.92/76.15 7147[32:MRR:3132.0,7146.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.15 7148[33:Spt:7147.2] || -> xuntil6(s24)*. % 75.92/76.15 7149[33:MRR:152.0,7148.0] || -> until5(s25)*. % 75.92/76.15 7150[33:MRR:3131.0,7149.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.15 7154[34:Spt:7150.2] || -> xuntil6(s25)*. % 75.92/76.15 7155[34:MRR:151.0,7154.0] || -> until5(s26)*. % 75.92/76.15 7156[34:MRR:3124.0,7155.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.15 7157[35:Spt:7156.2] || -> xuntil6(s26)*. % 75.92/76.15 7158[35:MRR:150.0,7157.0] || -> until5(s27)*. % 75.92/76.15 7159[35:MRR:3120.0,7158.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.15 7163[36:Spt:7159.2] || -> xuntil6(s27)*. % 75.92/76.15 7164[36:MRR:149.0,7163.0] || -> until5(s28)*. % 75.92/76.15 7165[36:MRR:3116.0,7164.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.15 7166[37:Spt:7165.2] || -> xuntil6(s28)*. % 75.92/76.15 7167[37:MRR:148.0,7166.0] || -> until5(s29)*. % 75.92/76.15 7168[37:MRR:3112.0,7167.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.15 7172[38:Spt:7168.2] || -> xuntil6(s29)*. % 75.92/76.15 7173[38:MRR:147.0,7172.0] || -> until5(s30)*. % 75.92/76.15 7174[38:MRR:3111.0,7173.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.15 7175[39:Spt:7174.2] || -> xuntil6(s30)*. % 75.92/76.15 7176[39:MRR:146.0,7175.0] || -> until5(s31)*. % 75.92/76.15 7177[39:MRR:3107.0,7176.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.15 7181[40:Spt:7177.2] || -> xuntil6(s31)*. % 75.92/76.15 7182[40:MRR:145.0,7181.0] || -> until5(s32)*. % 75.92/76.15 7183[40:MRR:3106.0,7182.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.15 7184[41:Spt:7183.2] || -> xuntil6(s32)*. % 75.92/76.15 7185[41:MRR:144.0,7184.0] || -> until5(s33)*. % 75.92/76.15 7186[41:MRR:932.0,7185.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.15 7190[42:Spt:7186.1] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.15 7192[42:Res:7190.0,61.1] always3(s34) || -> . % 75.92/76.15 7193[42:SSi:7192.0,723.0] || -> . % 75.92/76.15 7194[42:Spt:7193.0,7186.1,7190.0] || m_main_v_state(s34,c_busy)*+ -> . % 75.92/76.15 7195[42:Spt:7193.0,7186.0,7186.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 75.92/76.15 7198[42:Res:53.1,7195.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 75.92/76.15 7200[43:Spt:7198.1] || -> xuntil6(s33)*. % 75.92/76.15 7201[43:MRR:143.0,7200.0] || -> until5(s34)*. % 75.92/76.15 7202[43:MRR:3231.0,7201.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.15 7207[44:Spt:7202.2] || -> xuntil6(s34)*. % 75.92/76.15 7208[44:MRR:142.0,7207.0] || -> until5(s35)*. % 75.92/76.15 7209[44:MRR:930.0,7208.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.15 7210[45:Spt:7209.1] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.15 7212[45:Res:7210.0,61.1] always3(s36) || -> . % 75.92/76.15 7213[45:SSi:7212.0,725.0] || -> . % 75.92/76.15 7214[45:Spt:7213.0,7209.1,7210.0] || m_main_v_state(s36,c_busy)*+ -> . % 75.92/76.15 7215[45:Spt:7213.0,7209.0,7209.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 75.92/76.15 7218[45:Res:53.1,7215.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 75.92/76.15 7220[46:Spt:7218.1] || -> xuntil6(s35)*. % 75.92/76.15 7221[46:MRR:141.0,7220.0] || -> until5(s36)*. % 75.92/76.15 7222[46:MRR:3235.0,7221.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.15 7230[47:Spt:7222.2] || -> xuntil6(s36)*. % 75.92/76.15 7231[47:MRR:140.0,7230.0] || -> until5(s37)*. % 75.92/76.15 7232[47:MRR:928.0,7231.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.15 7233[48:Spt:7232.1] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.15 7235[48:Res:7233.0,61.1] always3(s38) || -> . % 75.92/76.15 7236[48:SSi:7235.0,727.0] || -> . % 75.92/76.15 7237[48:Spt:7236.0,7232.1,7233.0] || m_main_v_state(s38,c_busy)*+ -> . % 75.92/76.15 7238[48:Spt:7236.0,7232.0,7232.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 75.92/76.15 7241[48:Res:53.1,7238.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 75.92/76.15 7246[49:Spt:7241.1] || -> xuntil6(s37)*. % 75.92/76.15 7247[49:MRR:139.0,7246.0] || -> until5(s38)*. % 75.92/76.15 7248[49:MRR:3242.0,7247.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.15 7250[50:Spt:7248.2] || -> xuntil6(s38)*. % 75.92/76.15 7251[50:MRR:138.0,7250.0] || -> until5(s39)*. % 75.92/76.15 7252[50:MRR:926.0,7251.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.15 7253[51:Spt:7252.1] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.15 7255[51:Res:7253.0,61.1] always3(s40) || -> . % 75.92/76.15 7256[51:SSi:7255.0,729.0] || -> . % 75.92/76.15 7257[51:Spt:7256.0,7252.1,7253.0] || m_main_v_state(s40,c_busy)*+ -> . % 75.92/76.15 7258[51:Spt:7256.0,7252.0,7252.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 75.92/76.15 7261[51:Res:53.1,7258.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 75.92/76.15 7263[52:Spt:7261.1] || -> xuntil6(s39)*. % 75.92/76.15 7264[52:MRR:137.0,7263.0] || -> until5(s40)*. % 75.92/76.15 7265[52:MRR:3243.0,7264.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.15 7270[53:Spt:7265.2] || -> xuntil6(s40)*. % 75.92/76.15 7271[53:MRR:136.0,7270.0] || -> until5(s41)*. % 75.92/76.15 7272[53:MRR:924.0,7271.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.15 7273[54:Spt:7272.1] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.15 7275[54:Res:7273.0,61.1] always3(s42) || -> . % 75.92/76.15 7276[54:SSi:7275.0,731.0] || -> . % 75.92/76.15 7277[54:Spt:7276.0,7272.1,7273.0] || m_main_v_state(s42,c_busy)*+ -> . % 75.92/76.15 7278[54:Spt:7276.0,7272.0,7272.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 75.92/76.15 7281[54:Res:53.1,7278.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 75.92/76.15 7283[55:Spt:7281.1] || -> xuntil6(s41)*. % 75.92/76.15 7284[55:MRR:135.0,7283.0] || -> until5(s42)*. % 75.92/76.15 7285[55:MRR:3247.0,7284.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.15 7293[56:Spt:7285.2] || -> xuntil6(s42)*. % 75.92/76.15 7294[56:MRR:134.0,7293.0] || -> until5(s43)*. % 75.92/76.15 7295[56:MRR:922.0,7294.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.15 7296[57:Spt:7295.1] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.15 7298[57:Res:7296.0,61.1] always3(s44) || -> . % 75.92/76.15 7299[57:SSi:7298.0,733.0] || -> . % 75.92/76.15 7300[57:Spt:7299.0,7295.1,7296.0] || m_main_v_state(s44,c_busy)*+ -> . % 75.92/76.15 7301[57:Spt:7299.0,7295.0,7295.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 75.92/76.15 7303[57:MRR:789.2,7300.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 75.92/76.15 7304[57:Res:53.1,7301.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 75.92/76.15 7309[58:Spt:7304.1] || -> xuntil6(s43)*. % 75.92/76.15 7310[58:MRR:133.0,7309.0] || -> until5(s44)*. % 75.92/76.15 7311[58:MRR:3251.0,7310.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.15 7313[59:Spt:7311.2] || -> xuntil6(s44)*. % 75.92/76.15 7314[59:MRR:132.0,7313.0] || -> until5(s45)*. % 75.92/76.15 7315[59:MRR:920.0,7314.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.15 7316[60:Spt:7315.1] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.15 7318[60:Res:7316.0,61.1] always3(s46) || -> . % 75.92/76.15 7319[60:SSi:7318.0,735.0] || -> . % 75.92/76.15 7320[60:Spt:7319.0,7315.1,7316.0] || m_main_v_state(s46,c_busy)*+ -> . % 75.92/76.15 7321[60:Spt:7319.0,7315.0,7315.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 75.92/76.15 7323[60:MRR:783.2,7320.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 75.92/76.15 7324[60:Res:53.1,7321.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 75.92/76.15 7326[61:Spt:7324.1] || -> xuntil6(s45)*. % 75.92/76.15 7327[61:MRR:131.0,7326.0] || -> until5(s46)*. % 75.92/76.15 7328[61:MRR:3255.0,7327.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.15 7333[62:Spt:7328.2] || -> xuntil6(s46)*. % 75.92/76.15 7334[62:MRR:130.0,7333.0] || -> until5(s47)*. % 75.92/76.15 7335[62:MRR:918.0,7334.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.15 7336[63:Spt:7335.1] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.15 7338[63:Res:7336.0,61.1] always3(s48) || -> . % 75.92/76.15 7339[63:SSi:7338.0,737.0] || -> . % 75.92/76.15 7340[63:Spt:7339.0,7335.1,7336.0] || m_main_v_state(s48,c_busy)*+ -> . % 75.92/76.15 7341[63:Spt:7339.0,7335.0,7335.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 75.92/76.15 7343[63:MRR:777.2,7340.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 75.92/76.15 7344[63:Res:53.1,7341.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 75.92/76.15 7346[64:Spt:7344.1] || -> xuntil6(s47)*. % 75.92/76.15 7347[64:MRR:129.0,7346.0] || -> until5(s48)*. % 75.92/76.15 7348[64:MRR:3259.0,7347.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.15 7356[65:Spt:7348.2] || -> xuntil6(s48)*. % 75.92/76.15 7357[65:MRR:128.0,7356.0] || -> until5(s49)*. % 75.92/76.15 7358[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.15 7359[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.15 7363[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.15 7364[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.15 7365[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.15 7372[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.15 7373[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.15 7377[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.15 7381[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.15 7385[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.15 7392[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.15 7393[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.15 7397[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.15 7401[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.15 7405[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.15 7412[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.15 7413[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.15 7417[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.15 7421[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.15 7425[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.15 7432[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.15 7433[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.15 7437[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.15 7441[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.15 7445[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.15 7452[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.15 7453[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.15 7457[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.15 7461[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.15 7465[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.15 7472[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.15 7473[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.15 7475[8:SoR:7036.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 7483[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.15 7484[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.15 7488[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.15 7492[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.15 7496[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.15 7503[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.15 7504[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.15 7508[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.15 7509[8:SoR:7475.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 75.92/76.15 7510[65:SSi:7509.0,50.0,738.0,7357.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 75.92/76.15 7511[66:Spt:7510.1] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 7513[66:Res:7511.0,61.1] always3(s43) || -> . % 75.92/76.15 7514[66:SSi:7513.0,732.0,7294.0,7309.0] || -> . % 75.92/76.15 7515[66:Spt:7514.0,7510.1,7511.0] || m_main_v_state(s43,c_busy)*+ -> . % 75.92/76.15 7516[66:Spt:7514.0,7510.0,7510.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.15 7520[66:MRR:7475.2,7515.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.15 7521[66:Res:53.1,7516.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.15 7523[67:Spt:7521.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 7525[67:Res:7523.0,61.1] always3(s49) || -> . % 75.92/76.15 7526[67:SSi:7525.0,50.0,738.0,7357.0] || -> . % 75.92/76.15 7527[67:Spt:7526.0,7521.0,7523.0] || m_main_v_state(s49,c_busy)*+ -> . % 75.92/76.15 7528[67:Spt:7526.0,7521.1] || -> xuntil6(s49)*. % 75.92/76.15 7529[67:MRR:7035.0,7528.0] || -> until2p7(s43)*. % 75.92/76.15 7530[67:MRR:241.0,7529.0] || -> until2p7(s44)* node4(s43). % 75.92/76.15 7532[67:MRR:774.2,7527.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 75.92/76.15 7533[68:Spt:7530.0] || -> until2p7(s44)*. % 75.92/76.15 7534[68:MRR:539.0,7533.0] || -> until2p7(s45)* node4(s44). % 75.92/76.15 7535[69:Spt:7534.0] || -> until2p7(s45)*. % 75.92/76.15 7536[69:MRR:544.0,7535.0] || -> until2p7(s46)* node4(s45). % 75.92/76.15 7537[70:Spt:7536.0] || -> until2p7(s46)*. % 75.92/76.15 7538[70:MRR:549.0,7537.0] || -> until2p7(s47)* node4(s46). % 75.92/76.15 7539[71:Spt:7538.0] || -> until2p7(s47)*. % 75.92/76.15 7540[71:MRR:554.0,7539.0] || -> until2p7(s48)* node4(s47). % 75.92/76.15 7541[72:Spt:7540.0] || -> until2p7(s48)*. % 75.92/76.15 7542[72:MRR:559.0,7541.0] || -> until2p7(s49)* node4(s48). % 75.92/76.15 7543[73:Spt:7542.0] || -> until2p7(s49)*. % 75.92/76.15 7544[73:MRR:194.0,7543.0] || -> node4(s49)*. % 75.92/76.15 7545[73:MRR:7520.0,7544.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.15 7546[73:Res:53.1,7545.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 7548[73:MRR:7546.0,7527.0] || -> . % 75.92/76.15 7549[73:Spt:7548.0,7542.0,7543.0] || until2p7(s49)*+ -> . % 75.92/76.15 7550[73:Spt:7548.0,7542.1] || -> node4(s48)*. % 75.92/76.15 7551[73:MRR:7532.0,7550.0] || m_main_v_state(s48,c_ready)*+ -> . % 75.92/76.15 7554[73:Res:53.1,7551.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.15 7556[73:MRR:7554.0,7340.0] || -> . % 75.92/76.15 7557[72:Spt:7556.0,7540.0,7541.0] || until2p7(s48)*+ -> . % 75.92/76.15 7558[72:Spt:7556.0,7540.1] || -> node4(s47)*. % 75.92/76.15 7559[72:MRR:7343.0,7558.0] || m_main_v_state(s47,c_ready)*+ -> . % 75.92/76.15 7562[72:Res:53.1,7559.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 7565[72:Res:7562.0,61.1] always3(s47) || -> . % 75.92/76.15 7566[72:SSi:7565.0,736.0,7334.0,7346.0,7539.0,7558.0] || -> . % 75.92/76.15 7567[71:Spt:7566.0,7538.0,7539.0] || until2p7(s47)*+ -> . % 75.92/76.15 7568[71:Spt:7566.0,7538.1] || -> node4(s46)*. % 75.92/76.15 7570[71:MRR:780.0,7568.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.15 7594[71:Res:53.1,7570.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.15 7596[71:MRR:7594.0,7320.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 7598[71:Res:7596.0,61.1] always3(s47) || -> . % 75.92/76.15 7599[71:SSi:7598.0,736.0,7334.0,7346.0] || -> . % 75.92/76.15 7600[70:Spt:7599.0,7536.0,7537.0] || until2p7(s46)*+ -> . % 75.92/76.15 7601[70:Spt:7599.0,7536.1] || -> node4(s45)*. % 75.92/76.15 7602[70:MRR:7323.0,7601.0] || m_main_v_state(s45,c_ready)*+ -> . % 75.92/76.15 7605[70:Res:53.1,7602.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 7608[70:Res:7605.0,61.1] always3(s45) || -> . % 75.92/76.15 7609[70:SSi:7608.0,734.0,7314.0,7326.0,7535.0,7601.0] || -> . % 75.92/76.15 7610[69:Spt:7609.0,7534.0,7535.0] || until2p7(s45)*+ -> . % 75.92/76.15 7611[69:Spt:7609.0,7534.1] || -> node4(s44)*. % 75.92/76.15 7613[69:MRR:786.0,7611.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.15 7625[69:Res:53.1,7613.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.15 7627[69:MRR:7625.0,7300.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 7632[69:Res:7627.0,61.1] always3(s45) || -> . % 75.92/76.15 7633[69:SSi:7632.0,734.0,7314.0,7326.0] || -> . % 75.92/76.15 7634[68:Spt:7633.0,7530.0,7533.0] || until2p7(s44)*+ -> . % 75.92/76.15 7635[68:Spt:7633.0,7530.1] || -> node4(s43)*. % 75.92/76.15 7636[68:MRR:7303.0,7635.0] || m_main_v_state(s43,c_ready)*+ -> . % 75.92/76.15 7639[68:Res:53.1,7636.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 7641[68:MRR:7639.0,7515.0] || -> . % 75.92/76.15 7642[65:Spt:7641.0,7348.2,7356.0] || xuntil6(s48)*+ -> . % 75.92/76.15 7643[65:Spt:7641.0,7348.0,7348.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.15 7644[65:Res:53.1,7643.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.15 7646[65:MRR:7644.0,7340.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 7648[65:Res:7646.0,61.1] always3(s49) || -> . % 75.92/76.15 7649[65:SSi:7648.0,50.0,738.0] || -> . % 75.92/76.15 7650[64:Spt:7649.0,7344.1,7346.0] || xuntil6(s47)* -> . % 75.92/76.15 7651[64:Spt:7649.0,7344.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 7654[64:Res:7651.0,61.1] always3(s47) || -> . % 75.92/76.15 7655[64:SSi:7654.0,736.0,7334.0] || -> . % 75.92/76.15 7656[62:Spt:7655.0,7328.2,7333.0] || xuntil6(s46)*+ -> . % 75.92/76.15 7657[62:Spt:7655.0,7328.0,7328.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.15 7658[62:Res:53.1,7657.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.15 7660[62:MRR:7658.0,7320.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 7662[62:Res:7660.0,61.1] always3(s47) || -> . % 75.92/76.15 7663[62:SSi:7662.0,736.0] || -> . % 75.92/76.15 7664[61:Spt:7663.0,7324.1,7326.0] || xuntil6(s45)* -> . % 75.92/76.15 7665[61:Spt:7663.0,7324.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 7668[61:Res:7665.0,61.1] always3(s45) || -> . % 75.92/76.15 7669[61:SSi:7668.0,734.0,7314.0] || -> . % 75.92/76.15 7670[59:Spt:7669.0,7311.2,7313.0] || xuntil6(s44)*+ -> . % 75.92/76.15 7671[59:Spt:7669.0,7311.0,7311.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.15 7672[59:Res:53.1,7671.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.15 7674[59:MRR:7672.0,7300.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 7677[59:Res:7674.0,61.1] always3(s45) || -> . % 75.92/76.15 7678[59:SSi:7677.0,734.0] || -> . % 75.92/76.15 7679[58:Spt:7678.0,7304.1,7309.0] || xuntil6(s43)* -> . % 75.92/76.15 7680[58:Spt:7678.0,7304.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 7683[58:Res:7680.0,61.1] always3(s43) || -> . % 75.92/76.15 7684[58:SSi:7683.0,732.0,7294.0] || -> . % 75.92/76.15 7685[56:Spt:7684.0,7285.2,7293.0] || xuntil6(s42)*+ -> . % 75.92/76.15 7686[56:Spt:7684.0,7285.0,7285.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.15 7687[56:Res:53.1,7686.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.15 7689[56:MRR:7687.0,7277.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 7691[56:Res:7689.0,61.1] always3(s43) || -> . % 75.92/76.15 7692[56:SSi:7691.0,732.0] || -> . % 75.92/76.15 7693[55:Spt:7692.0,7281.1,7283.0] || xuntil6(s41)* -> . % 75.92/76.15 7694[55:Spt:7692.0,7281.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.15 7697[55:Res:7694.0,61.1] always3(s41) || -> . % 75.92/76.15 7698[55:SSi:7697.0,730.0,7271.0] || -> . % 75.92/76.15 7699[53:Spt:7698.0,7265.2,7270.0] || xuntil6(s40)*+ -> . % 75.92/76.15 7700[53:Spt:7698.0,7265.0,7265.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.15 7701[53:Res:53.1,7700.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.15 7703[53:MRR:7701.0,7257.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.15 7706[53:Res:7703.0,61.1] always3(s41) || -> . % 75.92/76.15 7707[53:SSi:7706.0,730.0] || -> . % 75.92/76.15 7708[52:Spt:7707.0,7261.1,7263.0] || xuntil6(s39)* -> . % 75.92/76.15 7709[52:Spt:7707.0,7261.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.15 7712[52:Res:7709.0,61.1] always3(s39) || -> . % 75.92/76.15 7713[52:SSi:7712.0,728.0,7251.0] || -> . % 75.92/76.15 7714[50:Spt:7713.0,7248.2,7250.0] || xuntil6(s38)*+ -> . % 75.92/76.15 7715[50:Spt:7713.0,7248.0,7248.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.15 7716[50:Res:53.1,7715.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.15 7718[50:MRR:7716.0,7237.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.15 7720[50:Res:7718.0,61.1] always3(s39) || -> . % 75.92/76.15 7721[50:SSi:7720.0,728.0] || -> . % 75.92/76.15 7722[49:Spt:7721.0,7241.1,7246.0] || xuntil6(s37)* -> . % 75.92/76.15 7723[49:Spt:7721.0,7241.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.15 7726[49:Res:7723.0,61.1] always3(s37) || -> . % 75.92/76.15 7727[49:SSi:7726.0,726.0,7231.0] || -> . % 75.92/76.15 7728[47:Spt:7727.0,7222.2,7230.0] || xuntil6(s36)*+ -> . % 75.92/76.15 7729[47:Spt:7727.0,7222.0,7222.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.15 7730[47:Res:53.1,7729.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.15 7732[47:MRR:7730.0,7214.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.15 7735[47:Res:7732.0,61.1] always3(s37) || -> . % 75.92/76.15 7736[47:SSi:7735.0,726.0] || -> . % 75.92/76.15 7737[46:Spt:7736.0,7218.1,7220.0] || xuntil6(s35)* -> . % 75.92/76.15 7738[46:Spt:7736.0,7218.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.15 7741[46:Res:7738.0,61.1] always3(s35) || -> . % 75.92/76.15 7742[46:SSi:7741.0,724.0,7208.0] || -> . % 75.92/76.15 7743[44:Spt:7742.0,7202.2,7207.0] || xuntil6(s34)*+ -> . % 75.92/76.15 7744[44:Spt:7742.0,7202.0,7202.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 75.92/76.15 7745[44:Res:53.1,7744.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 75.92/76.15 7747[44:MRR:7745.0,7194.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.15 7749[44:Res:7747.0,61.1] always3(s35) || -> . % 75.92/76.15 7750[44:SSi:7749.0,724.0] || -> . % 75.92/76.15 7751[43:Spt:7750.0,7198.1,7200.0] || xuntil6(s33)* -> . % 75.92/76.15 7752[43:Spt:7750.0,7198.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.15 7755[43:Res:7752.0,61.1] always3(s33) || -> . % 75.92/76.15 7756[43:SSi:7755.0,722.0,7185.0] || -> . % 75.92/76.15 7757[41:Spt:7756.0,7183.2,7184.0] || xuntil6(s32)*+ -> . % 75.92/76.15 7758[41:Spt:7756.0,7183.0,7183.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 75.92/76.15 7759[41:Res:53.1,7758.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 75.92/76.15 7761[42:Spt:7759.0] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.15 7763[42:Res:7761.0,61.1] always3(s32) || -> . % 75.92/76.15 7764[42:SSi:7763.0,721.0,7182.0] || -> . % 75.92/76.15 7765[42:Spt:7764.0,7759.0,7761.0] || m_main_v_state(s32,c_busy)* -> . % 75.92/76.15 7766[42:Spt:7764.0,7759.1] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.15 7770[42:Res:7766.0,61.1] always3(s33) || -> . % 75.92/76.15 7771[42:SSi:7770.0,722.0] || -> . % 75.92/76.15 7772[40:Spt:7771.0,7177.2,7181.0] || xuntil6(s31)*+ -> . % 75.92/76.15 7773[40:Spt:7771.0,7177.0,7177.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 75.92/76.15 7774[40:Res:53.1,7773.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 75.92/76.15 7776[41:Spt:7774.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.15 7778[41:Res:7776.0,61.1] always3(s31) || -> . % 75.92/76.15 7779[41:SSi:7778.0,720.0,7176.0] || -> . % 75.92/76.15 7780[41:Spt:7779.0,7774.0,7776.0] || m_main_v_state(s31,c_busy)* -> . % 75.92/76.15 7781[41:Spt:7779.0,7774.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.15 7785[41:Res:7781.0,61.1] always3(s32) || -> . % 75.92/76.15 7786[41:SSi:7785.0,721.0] || -> . % 75.92/76.15 7787[39:Spt:7786.0,7174.2,7175.0] || xuntil6(s30)*+ -> . % 75.92/76.15 7788[39:Spt:7786.0,7174.0,7174.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.15 7789[39:Res:53.1,7788.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.15 7791[40:Spt:7789.0] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.15 7793[40:Res:7791.0,61.1] always3(s30) || -> . % 75.92/76.15 7794[40:SSi:7793.0,719.0,7173.0] || -> . % 75.92/76.15 7795[40:Spt:7794.0,7789.0,7791.0] || m_main_v_state(s30,c_busy)* -> . % 75.92/76.15 7796[40:Spt:7794.0,7789.1] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.15 7800[40:Res:7796.0,61.1] always3(s31) || -> . % 75.92/76.15 7801[40:SSi:7800.0,720.0] || -> . % 75.92/76.15 7802[38:Spt:7801.0,7168.2,7172.0] || xuntil6(s29)*+ -> . % 75.92/76.15 7803[38:Spt:7801.0,7168.0,7168.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 75.92/76.15 7804[38:Res:53.1,7803.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 75.92/76.15 7806[39:Spt:7804.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.15 7808[39:Res:7806.0,61.1] always3(s29) || -> . % 75.92/76.15 7809[39:SSi:7808.0,718.0,7167.0] || -> . % 75.92/76.15 7810[39:Spt:7809.0,7804.0,7806.0] || m_main_v_state(s29,c_busy)* -> . % 75.92/76.15 7811[39:Spt:7809.0,7804.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.15 7815[39:Res:7811.0,61.1] always3(s30) || -> . % 75.92/76.15 7816[39:SSi:7815.0,719.0] || -> . % 75.92/76.15 7817[37:Spt:7816.0,7165.2,7166.0] || xuntil6(s28)*+ -> . % 75.92/76.15 7818[37:Spt:7816.0,7165.0,7165.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.15 7819[37:Res:53.1,7818.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.15 7821[38:Spt:7819.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.15 7823[38:Res:7821.0,61.1] always3(s28) || -> . % 75.92/76.15 7824[38:SSi:7823.0,717.0,7164.0] || -> . % 75.92/76.15 7825[38:Spt:7824.0,7819.0,7821.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.15 7826[38:Spt:7824.0,7819.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.15 7830[38:Res:7826.0,61.1] always3(s29) || -> . % 75.92/76.15 7831[38:SSi:7830.0,718.0] || -> . % 75.92/76.15 7832[36:Spt:7831.0,7159.2,7163.0] || xuntil6(s27)*+ -> . % 75.92/76.15 7833[36:Spt:7831.0,7159.0,7159.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.15 7834[36:Res:53.1,7833.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.15 7836[37:Spt:7834.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.15 7838[37:Res:7836.0,61.1] always3(s27) || -> . % 75.92/76.15 7839[37:SSi:7838.0,716.0,7158.0] || -> . % 75.92/76.15 7840[37:Spt:7839.0,7834.0,7836.0] || m_main_v_state(s27,c_busy)* -> . % 75.92/76.15 7841[37:Spt:7839.0,7834.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.15 7845[37:Res:7841.0,61.1] always3(s28) || -> . % 75.92/76.15 7846[37:SSi:7845.0,717.0] || -> . % 75.92/76.15 7847[35:Spt:7846.0,7156.2,7157.0] || xuntil6(s26)*+ -> . % 75.92/76.15 7848[35:Spt:7846.0,7156.0,7156.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.15 7849[35:Res:53.1,7848.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.15 7851[36:Spt:7849.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.15 7853[36:Res:7851.0,61.1] always3(s26) || -> . % 75.92/76.15 7854[36:SSi:7853.0,715.0,7155.0] || -> . % 75.92/76.15 7855[36:Spt:7854.0,7849.0,7851.0] || m_main_v_state(s26,c_busy)* -> . % 75.92/76.15 7856[36:Spt:7854.0,7849.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.15 7860[36:Res:7856.0,61.1] always3(s27) || -> . % 75.92/76.15 7861[36:SSi:7860.0,716.0] || -> . % 75.92/76.15 7862[34:Spt:7861.0,7150.2,7154.0] || xuntil6(s25)*+ -> . % 75.92/76.15 7863[34:Spt:7861.0,7150.0,7150.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.15 7864[34:Res:53.1,7863.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.15 7866[35:Spt:7864.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.15 7868[35:Res:7866.0,61.1] always3(s25) || -> . % 75.92/76.15 7869[35:SSi:7868.0,714.0,7149.0] || -> . % 75.92/76.15 7870[35:Spt:7869.0,7864.0,7866.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.15 7871[35:Spt:7869.0,7864.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.15 7875[35:Res:7871.0,61.1] always3(s26) || -> . % 75.92/76.15 7876[35:SSi:7875.0,715.0] || -> . % 75.92/76.15 7877[33:Spt:7876.0,7147.2,7148.0] || xuntil6(s24)*+ -> . % 75.92/76.15 7878[33:Spt:7876.0,7147.0,7147.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.15 7879[33:Res:53.1,7878.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.15 7881[34:Spt:7879.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.15 7883[34:Res:7881.0,61.1] always3(s24) || -> . % 75.92/76.15 7884[34:SSi:7883.0,713.0,7146.0] || -> . % 75.92/76.15 7885[34:Spt:7884.0,7879.0,7881.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.15 7886[34:Spt:7884.0,7879.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.15 7890[34:Res:7886.0,61.1] always3(s25) || -> . % 75.92/76.15 7891[34:SSi:7890.0,714.0] || -> . % 75.92/76.15 7892[32:Spt:7891.0,7141.2,7145.0] || xuntil6(s23)*+ -> . % 75.92/76.15 7893[32:Spt:7891.0,7141.0,7141.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.15 7894[32:Res:53.1,7893.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.15 7896[33:Spt:7894.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.15 7898[33:Res:7896.0,61.1] always3(s23) || -> . % 75.92/76.15 7899[33:SSi:7898.0,712.0,7140.0] || -> . % 75.92/76.15 7900[33:Spt:7899.0,7894.0,7896.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.15 7901[33:Spt:7899.0,7894.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.15 7905[33:Res:7901.0,61.1] always3(s24) || -> . % 75.92/76.15 7906[33:SSi:7905.0,713.0] || -> . % 75.92/76.15 7907[31:Spt:7906.0,7138.2,7139.0] || xuntil6(s22)*+ -> . % 75.92/76.15 7908[31:Spt:7906.0,7138.0,7138.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.15 7909[31:Res:53.1,7908.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.15 7911[32:Spt:7909.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.15 7913[32:Res:7911.0,61.1] always3(s22) || -> . % 75.92/76.15 7914[32:SSi:7913.0,711.0,7137.0] || -> . % 75.92/76.15 7915[32:Spt:7914.0,7909.0,7911.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.15 7916[32:Spt:7914.0,7909.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.15 7920[32:Res:7916.0,61.1] always3(s23) || -> . % 75.92/76.15 7921[32:SSi:7920.0,712.0] || -> . % 75.92/76.15 7922[30:Spt:7921.0,7132.2,7136.0] || xuntil6(s21)*+ -> . % 75.92/76.15 7923[30:Spt:7921.0,7132.0,7132.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.15 7924[30:Res:53.1,7923.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.15 7926[31:Spt:7924.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.15 7928[31:Res:7926.0,61.1] always3(s21) || -> . % 75.92/76.15 7929[31:SSi:7928.0,710.0,7131.0] || -> . % 75.92/76.15 7930[31:Spt:7929.0,7924.0,7926.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.15 7931[31:Spt:7929.0,7924.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.15 7935[31:Res:7931.0,61.1] always3(s22) || -> . % 75.92/76.15 7936[31:SSi:7935.0,711.0] || -> . % 75.92/76.15 7937[29:Spt:7936.0,7129.2,7130.0] || xuntil6(s20)*+ -> . % 75.92/76.15 7938[29:Spt:7936.0,7129.0,7129.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.15 7939[29:Res:53.1,7938.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.15 7941[30:Spt:7939.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.15 7943[30:Res:7941.0,61.1] always3(s20) || -> . % 75.92/76.15 7944[30:SSi:7943.0,709.0,7128.0] || -> . % 75.92/76.15 7945[30:Spt:7944.0,7939.0,7941.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.15 7946[30:Spt:7944.0,7939.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.15 7950[30:Res:7946.0,61.1] always3(s21) || -> . % 75.92/76.15 7951[30:SSi:7950.0,710.0] || -> . % 75.92/76.15 7952[28:Spt:7951.0,7123.2,7127.0] || xuntil6(s19)*+ -> . % 75.92/76.15 7953[28:Spt:7951.0,7123.0,7123.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.15 7954[28:Res:53.1,7953.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.15 7959[29:Spt:7954.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.15 7961[29:Res:7959.0,61.1] always3(s19) || -> . % 75.92/76.15 7962[29:SSi:7961.0,708.0,7122.0] || -> . % 75.92/76.15 7963[29:Spt:7962.0,7954.0,7959.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.15 7964[29:Spt:7962.0,7954.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.15 7968[29:Res:7964.0,61.1] always3(s20) || -> . % 75.92/76.15 7969[29:SSi:7968.0,709.0] || -> . % 75.92/76.15 7970[27:Spt:7969.0,7120.2,7121.0] || xuntil6(s18)*+ -> . % 75.92/76.15 7971[27:Spt:7969.0,7120.0,7120.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.15 7972[27:Res:53.1,7971.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.15 7974[28:Spt:7972.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.15 7976[28:Res:7974.0,61.1] always3(s18) || -> . % 75.92/76.15 7977[28:SSi:7976.0,707.0,7119.0] || -> . % 75.92/76.15 7978[28:Spt:7977.0,7972.0,7974.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.15 7979[28:Spt:7977.0,7972.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.15 7983[28:Res:7979.0,61.1] always3(s19) || -> . % 75.92/76.15 7984[28:SSi:7983.0,708.0] || -> . % 75.92/76.15 7985[26:Spt:7984.0,7114.2,7118.0] || xuntil6(s17)*+ -> . % 75.92/76.15 7986[26:Spt:7984.0,7114.0,7114.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.15 7987[26:Res:53.1,7986.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.15 7989[27:Spt:7987.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.15 7991[27:Res:7989.0,61.1] always3(s17) || -> . % 75.92/76.15 7992[27:SSi:7991.0,706.0,7113.0] || -> . % 75.92/76.15 7993[27:Spt:7992.0,7987.0,7989.0] || m_main_v_state(s17,c_busy)* -> . % 75.92/76.15 7994[27:Spt:7992.0,7987.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.15 7998[27:Res:7994.0,61.1] always3(s18) || -> . % 75.92/76.15 7999[27:SSi:7998.0,707.0] || -> . % 75.92/76.15 8000[25:Spt:7999.0,7111.2,7112.0] || xuntil6(s16)*+ -> . % 75.92/76.15 8001[25:Spt:7999.0,7111.0,7111.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.15 8002[25:Res:53.1,8001.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.15 8007[26:Spt:8002.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.15 8009[26:Res:8007.0,61.1] always3(s16) || -> . % 75.92/76.15 8010[26:SSi:8009.0,705.0,7110.0] || -> . % 75.92/76.15 8011[26:Spt:8010.0,8002.0,8007.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.15 8012[26:Spt:8010.0,8002.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.15 8016[26:Res:8012.0,61.1] always3(s17) || -> . % 75.92/76.15 8017[26:SSi:8016.0,706.0] || -> . % 75.92/76.15 8018[24:Spt:8017.0,7105.2,7109.0] || xuntil6(s15)*+ -> . % 75.92/76.15 8019[24:Spt:8017.0,7105.0,7105.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.15 8020[24:Res:53.1,8019.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.15 8022[25:Spt:8020.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.15 8024[25:Res:8022.0,61.1] always3(s15) || -> . % 75.92/76.15 8025[25:SSi:8024.0,704.0,7104.0] || -> . % 75.92/76.15 8026[25:Spt:8025.0,8020.0,8022.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.15 8027[25:Spt:8025.0,8020.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.15 8031[25:Res:8027.0,61.1] always3(s16) || -> . % 75.92/76.15 8032[25:SSi:8031.0,705.0] || -> . % 75.92/76.15 8033[23:Spt:8032.0,7102.2,7103.0] || xuntil6(s14)*+ -> . % 75.92/76.15 8034[23:Spt:8032.0,7102.0,7102.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.15 8035[23:Res:53.1,8034.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.15 8037[24:Spt:8035.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.15 8039[24:Res:8037.0,61.1] always3(s14) || -> . % 75.92/76.15 8040[24:SSi:8039.0,703.0,7101.0] || -> . % 75.92/76.15 8041[24:Spt:8040.0,8035.0,8037.0] || m_main_v_state(s14,c_busy)* -> . % 75.92/76.15 8042[24:Spt:8040.0,8035.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.15 8046[24:Res:8042.0,61.1] always3(s15) || -> . % 75.92/76.15 8047[24:SSi:8046.0,704.0] || -> . % 75.92/76.15 8048[22:Spt:8047.0,7096.2,7100.0] || xuntil6(s13)*+ -> . % 75.92/76.15 8049[22:Spt:8047.0,7096.0,7096.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.15 8050[22:Res:53.1,8049.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.15 8055[23:Spt:8050.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.15 8057[23:Res:8055.0,61.1] always3(s13) || -> . % 75.92/76.15 8058[23:SSi:8057.0,702.0,7095.0] || -> . % 75.92/76.15 8059[23:Spt:8058.0,8050.0,8055.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.15 8060[23:Spt:8058.0,8050.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.15 8064[23:Res:8060.0,61.1] always3(s14) || -> . % 75.92/76.15 8065[23:SSi:8064.0,703.0] || -> . % 75.92/76.15 8066[21:Spt:8065.0,7093.2,7094.0] || xuntil6(s12)*+ -> . % 75.92/76.15 8067[21:Spt:8065.0,7093.0,7093.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.15 8068[21:Res:53.1,8067.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.15 8070[22:Spt:8068.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.15 8072[22:Res:8070.0,61.1] always3(s12) || -> . % 75.92/76.15 8073[22:SSi:8072.0,701.0,7092.0] || -> . % 75.92/76.15 8074[22:Spt:8073.0,8068.0,8070.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.15 8075[22:Spt:8073.0,8068.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.15 8079[22:Res:8075.0,61.1] always3(s13) || -> . % 75.92/76.15 8080[22:SSi:8079.0,702.0] || -> . % 75.92/76.15 8081[20:Spt:8080.0,7087.2,7091.0] || xuntil6(s11)*+ -> . % 75.92/76.15 8082[20:Spt:8080.0,7087.0,7087.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.15 8083[20:Res:53.1,8082.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.15 8085[21:Spt:8083.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.15 8087[21:Res:8085.0,61.1] always3(s11) || -> . % 75.92/76.15 8088[21:SSi:8087.0,700.0,7086.0] || -> . % 75.92/76.15 8089[21:Spt:8088.0,8083.0,8085.0] || m_main_v_state(s11,c_busy)* -> . % 75.92/76.15 8090[21:Spt:8088.0,8083.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.15 8094[21:Res:8090.0,61.1] always3(s12) || -> . % 75.92/76.15 8095[21:SSi:8094.0,701.0] || -> . % 75.92/76.15 8096[19:Spt:8095.0,7084.2,7085.0] || xuntil6(s10)*+ -> . % 75.92/76.15 8097[19:Spt:8095.0,7084.0,7084.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.15 8098[19:Res:53.1,8097.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.15 8103[20:Spt:8098.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.15 8105[20:Res:8103.0,61.1] always3(s10) || -> . % 75.92/76.15 8106[20:SSi:8105.0,699.0,7083.0] || -> . % 75.92/76.15 8107[20:Spt:8106.0,8098.0,8103.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.15 8108[20:Spt:8106.0,8098.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.15 8112[20:Res:8108.0,61.1] always3(s11) || -> . % 75.92/76.15 8113[20:SSi:8112.0,700.0] || -> . % 75.92/76.15 8114[18:Spt:8113.0,7078.2,7082.0] || xuntil6(s9)*+ -> . % 75.92/76.15 8115[18:Spt:8113.0,7078.0,7078.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.15 8116[18:Res:53.1,8115.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.15 8118[19:Spt:8116.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.15 8120[19:Res:8118.0,61.1] always3(s9) || -> . % 75.92/76.15 8121[19:SSi:8120.0,698.0,7077.0] || -> . % 75.92/76.15 8122[19:Spt:8121.0,8116.0,8118.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.15 8123[19:Spt:8121.0,8116.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.15 8127[19:Res:8123.0,61.1] always3(s10) || -> . % 75.92/76.15 8128[19:SSi:8127.0,699.0] || -> . % 75.92/76.15 8129[17:Spt:8128.0,7075.2,7076.0] || xuntil6(s8)*+ -> . % 75.92/76.15 8130[17:Spt:8128.0,7075.0,7075.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.15 8131[17:Res:53.1,8130.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.15 8133[18:Spt:8131.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.15 8135[18:Res:8133.0,61.1] always3(s8) || -> . % 75.92/76.15 8136[18:SSi:8135.0,697.0,7074.0] || -> . % 75.92/76.15 8137[18:Spt:8136.0,8131.0,8133.0] || m_main_v_state(s8,c_busy)* -> . % 75.92/76.15 8138[18:Spt:8136.0,8131.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.15 8142[18:Res:8138.0,61.1] always3(s9) || -> . % 75.92/76.15 8143[18:SSi:8142.0,698.0] || -> . % 75.92/76.15 8144[16:Spt:8143.0,7069.2,7073.0] || xuntil6(s7)*+ -> . % 75.92/76.15 8145[16:Spt:8143.0,7069.0,7069.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.15 8146[16:Res:53.1,8145.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.15 8151[17:Spt:8146.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.15 8153[17:Res:8151.0,61.1] always3(s7) || -> . % 75.92/76.15 8154[17:SSi:8153.0,696.0,7068.0] || -> . % 75.92/76.15 8155[17:Spt:8154.0,8146.0,8151.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.15 8156[17:Spt:8154.0,8146.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.15 8160[17:Res:8156.0,61.1] always3(s8) || -> . % 75.92/76.15 8161[17:SSi:8160.0,697.0] || -> . % 75.92/76.15 8162[15:Spt:8161.0,7066.2,7067.0] || xuntil6(s6)*+ -> . % 75.92/76.15 8163[15:Spt:8161.0,7066.0,7066.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.15 8164[15:Res:53.1,8163.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.15 8166[16:Spt:8164.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.15 8168[16:Res:8166.0,61.1] always3(s6) || -> . % 75.92/76.15 8169[16:SSi:8168.0,695.0,7065.0] || -> . % 75.92/76.15 8170[16:Spt:8169.0,8164.0,8166.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.15 8171[16:Spt:8169.0,8164.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.15 8175[16:Res:8171.0,61.1] always3(s7) || -> . % 75.92/76.15 8176[16:SSi:8175.0,696.0] || -> . % 75.92/76.15 8177[14:Spt:8176.0,7060.2,7064.0] || xuntil6(s5)*+ -> . % 75.92/76.15 8178[14:Spt:8176.0,7060.0,7060.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.15 8179[14:Res:53.1,8178.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.15 8181[15:Spt:8179.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.15 8183[15:Res:8181.0,61.1] always3(s5) || -> . % 75.92/76.15 8184[15:SSi:8183.0,694.0,7059.0] || -> . % 75.92/76.15 8185[15:Spt:8184.0,8179.0,8181.0] || m_main_v_state(s5,c_busy)* -> . % 75.92/76.15 8186[15:Spt:8184.0,8179.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.15 8190[15:Res:8186.0,61.1] always3(s6) || -> . % 75.92/76.15 8191[15:SSi:8190.0,695.0] || -> . % 75.92/76.15 8192[13:Spt:8191.0,7057.2,7058.0] || xuntil6(s4)*+ -> . % 75.92/76.15 8193[13:Spt:8191.0,7057.0,7057.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.15 8194[13:Res:53.1,8193.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.15 8199[14:Spt:8194.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.15 8201[14:Res:8199.0,61.1] always3(s4) || -> . % 75.92/76.15 8202[14:SSi:8201.0,693.0,7056.0] || -> . % 75.92/76.15 8203[14:Spt:8202.0,8194.0,8199.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.15 8204[14:Spt:8202.0,8194.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.15 8208[14:Res:8204.0,61.1] always3(s5) || -> . % 75.92/76.15 8209[14:SSi:8208.0,694.0] || -> . % 75.92/76.15 8210[12:Spt:8209.0,7051.2,7055.0] || xuntil6(s3)*+ -> . % 75.92/76.15 8211[12:Spt:8209.0,7051.0,7051.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.15 8212[12:Res:53.1,8211.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.15 8214[13:Spt:8212.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.15 8216[13:Res:8214.0,61.1] always3(s3) || -> . % 75.92/76.15 8217[13:SSi:8216.0,692.0,7050.0] || -> . % 75.92/76.15 8218[13:Spt:8217.0,8212.0,8214.0] || m_main_v_state(s3,c_busy)* -> . % 75.92/76.15 8219[13:Spt:8217.0,8212.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.15 8223[13:Res:8219.0,61.1] always3(s4) || -> . % 75.92/76.15 8224[13:SSi:8223.0,693.0] || -> . % 75.92/76.15 8225[11:Spt:8224.0,7048.2,7049.0] || xuntil6(s2)*+ -> . % 75.92/76.15 8226[11:Spt:8224.0,7048.0,7048.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.15 8227[11:Res:53.1,8226.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.15 8229[12:Spt:8227.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.15 8231[12:Res:8229.0,61.1] always3(s2) || -> . % 75.92/76.15 8232[12:SSi:8231.0,691.0,7047.0] || -> . % 75.92/76.15 8233[12:Spt:8232.0,8227.0,8229.0] || m_main_v_state(s2,c_busy)* -> . % 75.92/76.15 8234[12:Spt:8232.0,8227.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.15 8238[12:Res:8234.0,61.1] always3(s3) || -> . % 75.92/76.15 8239[12:SSi:8238.0,692.0] || -> . % 75.92/76.15 8240[10:Spt:8239.0,7039.2,7046.0] || xuntil6(s1)*+ -> . % 75.92/76.15 8241[10:Spt:8239.0,7039.0,7039.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.15 8242[10:Res:53.1,8241.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.15 8247[11:Spt:8242.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.15 8249[11:Res:8247.0,61.1] always3(s1) || -> . % 75.92/76.15 8250[11:SSi:8249.0,690.0,7038.0] || -> . % 75.92/76.15 8251[11:Spt:8250.0,8242.0,8247.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.15 8252[11:Spt:8250.0,8242.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.15 8257[11:Res:8252.0,61.1] always3(s2) || -> . % 75.92/76.15 8258[11:SSi:8257.0,691.0] || -> . % 75.92/76.15 8259[9:Spt:8258.0,74.0,7037.0] || xuntil6(s0)*+ -> . % 75.92/76.15 8260[9:Spt:8258.0,74.1] || -> node4(s0)*. % 75.92/76.15 8261[9:MRR:758.1,8259.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.15 8263[9:Res:8261.0,61.1] always3(s1) || -> . % 75.92/76.15 8264[9:SSi:8263.0,690.0] || -> . % 75.92/76.15 8265[8:Spt:8264.0,7027.0,7031.0] || trans(s49,s43)*+ -> . % 75.92/76.15 8266[8:Spt:8264.0,7027.1,7027.2,7027.3,7027.4,7027.5,7027.6,7027.7,7027.8,7027.9,7027.10,7027.11,7027.12,7027.13,7027.14,7027.15,7027.16,7027.17,7027.18,7027.19,7027.20,7027.21,7027.22,7027.23,7027.24,7027.25,7027.26,7027.27,7027.28,7027.29,7027.30,7027.31,7027.32,7027.33,7027.34,7027.35,7027.36,7027.37,7027.38,7027.39,7027.40,7027.41,7027.42,7027.43] || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.15 8267[8:MRR:7029.0,8265.0] || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.15 8269[8:MRR:7030.1,8265.0] xuntil6(s49) || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.15 8270[9:Spt:8266.0] || -> trans(s49,s42)*. % 75.92/76.15 8271[9:Res:8270.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s42)*. % 75.92/76.15 8273[9:Res:8270.0,60.0] || -> node2(s49,s42)*. % 75.92/76.15 8274[9:SSi:8271.1,50.0,738.0] xuntil6(s49) || -> until2p7(s42)*. % 75.92/76.15 8275[9:Res:8273.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)*. % 75.92/76.15 8276[10:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.15 8277[10:MRR:176.0,8276.0] || -> until5(s1)*. % 75.92/76.15 8278[10:MRR:7473.0,8277.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.15 8282[11:Spt:8278.2] || -> xuntil6(s1)*. % 75.92/76.15 8283[11:MRR:175.0,8282.0] || -> until5(s2)*. % 75.92/76.15 8284[11:MRR:7472.0,8283.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.15 8285[12:Spt:8284.2] || -> xuntil6(s2)*. % 75.92/76.15 8286[12:MRR:174.0,8285.0] || -> until5(s3)*. % 75.92/76.15 8287[12:MRR:7465.0,8286.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.15 8288[13:Spt:8287.2] || -> xuntil6(s3)*. % 75.92/76.15 8289[13:MRR:173.0,8288.0] || -> until5(s4)*. % 75.92/76.15 8290[13:MRR:7461.0,8289.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.15 8291[14:Spt:8290.2] || -> xuntil6(s4)*. % 75.92/76.15 8292[14:MRR:172.0,8291.0] || -> until5(s5)*. % 75.92/76.15 8293[14:MRR:7457.0,8292.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.15 8297[15:Spt:8293.2] || -> xuntil6(s5)*. % 75.92/76.15 8298[15:MRR:171.0,8297.0] || -> until5(s6)*. % 75.92/76.15 8299[15:MRR:7453.0,8298.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.15 8300[16:Spt:8299.2] || -> xuntil6(s6)*. % 75.92/76.15 8301[16:MRR:170.0,8300.0] || -> until5(s7)*. % 75.92/76.15 8302[16:MRR:7452.0,8301.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.15 8306[17:Spt:8302.2] || -> xuntil6(s7)*. % 75.92/76.15 8307[17:MRR:169.0,8306.0] || -> until5(s8)*. % 75.92/76.15 8308[17:MRR:7445.0,8307.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.15 8309[18:Spt:8308.2] || -> xuntil6(s8)*. % 75.92/76.15 8310[18:MRR:168.0,8309.0] || -> until5(s9)*. % 75.92/76.15 8311[18:MRR:7441.0,8310.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.15 8315[19:Spt:8311.2] || -> xuntil6(s9)*. % 75.92/76.15 8316[19:MRR:167.0,8315.0] || -> until5(s10)*. % 75.92/76.15 8317[19:MRR:7437.0,8316.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.15 8318[20:Spt:8317.2] || -> xuntil6(s10)*. % 75.92/76.15 8319[20:MRR:166.0,8318.0] || -> until5(s11)*. % 75.92/76.15 8320[20:MRR:7433.0,8319.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.15 8324[21:Spt:8320.2] || -> xuntil6(s11)*. % 75.92/76.15 8325[21:MRR:165.0,8324.0] || -> until5(s12)*. % 75.92/76.15 8326[21:MRR:7432.0,8325.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.15 8327[22:Spt:8326.2] || -> xuntil6(s12)*. % 75.92/76.15 8328[22:MRR:164.0,8327.0] || -> until5(s13)*. % 75.92/76.15 8329[22:MRR:7425.0,8328.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.15 8333[23:Spt:8329.2] || -> xuntil6(s13)*. % 75.92/76.15 8334[23:MRR:163.0,8333.0] || -> until5(s14)*. % 75.92/76.15 8335[23:MRR:7421.0,8334.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.15 8336[24:Spt:8335.2] || -> xuntil6(s14)*. % 75.92/76.15 8337[24:MRR:162.0,8336.0] || -> until5(s15)*. % 75.92/76.15 8338[24:MRR:7417.0,8337.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.15 8342[25:Spt:8338.2] || -> xuntil6(s15)*. % 75.92/76.15 8343[25:MRR:161.0,8342.0] || -> until5(s16)*. % 75.92/76.15 8344[25:MRR:7413.0,8343.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.15 8345[26:Spt:8344.2] || -> xuntil6(s16)*. % 75.92/76.15 8346[26:MRR:160.0,8345.0] || -> until5(s17)*. % 75.92/76.15 8347[26:MRR:7412.0,8346.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.15 8351[27:Spt:8347.2] || -> xuntil6(s17)*. % 75.92/76.15 8352[27:MRR:159.0,8351.0] || -> until5(s18)*. % 75.92/76.15 8353[27:MRR:7405.0,8352.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.15 8354[28:Spt:8353.2] || -> xuntil6(s18)*. % 75.92/76.15 8355[28:MRR:158.0,8354.0] || -> until5(s19)*. % 75.92/76.15 8356[28:MRR:7401.0,8355.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.15 8360[29:Spt:8356.2] || -> xuntil6(s19)*. % 75.92/76.15 8361[29:MRR:157.0,8360.0] || -> until5(s20)*. % 75.92/76.15 8362[29:MRR:7397.0,8361.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.15 8363[30:Spt:8362.2] || -> xuntil6(s20)*. % 75.92/76.15 8364[30:MRR:156.0,8363.0] || -> until5(s21)*. % 75.92/76.15 8365[30:MRR:7393.0,8364.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.15 8369[31:Spt:8365.2] || -> xuntil6(s21)*. % 75.92/76.15 8370[31:MRR:155.0,8369.0] || -> until5(s22)*. % 75.92/76.15 8371[31:MRR:7392.0,8370.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.15 8372[32:Spt:8371.2] || -> xuntil6(s22)*. % 75.92/76.15 8373[32:MRR:154.0,8372.0] || -> until5(s23)*. % 75.92/76.15 8374[32:MRR:7385.0,8373.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.15 8378[33:Spt:8374.2] || -> xuntil6(s23)*. % 75.92/76.15 8379[33:MRR:153.0,8378.0] || -> until5(s24)*. % 75.92/76.15 8380[33:MRR:7381.0,8379.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.15 8381[34:Spt:8380.2] || -> xuntil6(s24)*. % 75.92/76.15 8382[34:MRR:152.0,8381.0] || -> until5(s25)*. % 75.92/76.15 8383[34:MRR:7377.0,8382.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.15 8387[35:Spt:8383.2] || -> xuntil6(s25)*. % 75.92/76.15 8388[35:MRR:151.0,8387.0] || -> until5(s26)*. % 75.92/76.15 8389[35:MRR:7373.0,8388.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.15 8390[36:Spt:8389.2] || -> xuntil6(s26)*. % 75.92/76.15 8391[36:MRR:150.0,8390.0] || -> until5(s27)*. % 75.92/76.15 8392[36:MRR:7372.0,8391.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.15 8396[37:Spt:8392.2] || -> xuntil6(s27)*. % 75.92/76.15 8397[37:MRR:149.0,8396.0] || -> until5(s28)*. % 75.92/76.15 8398[37:MRR:7365.0,8397.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.15 8399[38:Spt:8398.2] || -> xuntil6(s28)*. % 75.92/76.15 8400[38:MRR:148.0,8399.0] || -> until5(s29)*. % 75.92/76.15 8401[38:MRR:7364.0,8400.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.15 8405[39:Spt:8401.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.15 8407[39:Res:8405.0,61.1] always3(s30) || -> . % 75.92/76.15 8408[39:SSi:8407.0,719.0] || -> . % 75.92/76.15 8409[39:Spt:8408.0,8401.1,8405.0] || m_main_v_state(s30,c_busy)*+ -> . % 75.92/76.15 8410[39:Spt:8408.0,8401.0,8401.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 75.92/76.15 8413[39:Res:53.1,8410.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 75.92/76.15 8415[40:Spt:8413.1] || -> xuntil6(s29)*. % 75.92/76.15 8416[40:MRR:147.0,8415.0] || -> until5(s30)*. % 75.92/76.15 8417[40:MRR:7363.0,8416.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.15 8422[41:Spt:8417.2] || -> xuntil6(s30)*. % 75.92/76.15 8423[41:MRR:146.0,8422.0] || -> until5(s31)*. % 75.92/76.15 8424[41:MRR:7359.0,8423.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.15 8425[42:Spt:8424.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.15 8427[42:Res:8425.0,61.1] always3(s32) || -> . % 75.92/76.15 8428[42:SSi:8427.0,721.0] || -> . % 75.92/76.15 8429[42:Spt:8428.0,8424.1,8425.0] || m_main_v_state(s32,c_busy)*+ -> . % 75.92/76.15 8430[42:Spt:8428.0,8424.0,8424.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 75.92/76.15 8433[42:Res:53.1,8430.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 75.92/76.15 8435[43:Spt:8433.1] || -> xuntil6(s31)*. % 75.92/76.15 8436[43:MRR:145.0,8435.0] || -> until5(s32)*. % 75.92/76.15 8437[43:MRR:7358.0,8436.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.15 8445[44:Spt:8437.2] || -> xuntil6(s32)*. % 75.92/76.15 8446[44:MRR:144.0,8445.0] || -> until5(s33)*. % 75.92/76.15 8447[44:MRR:932.0,8446.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.15 8448[45:Spt:8447.1] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.15 8450[45:Res:8448.0,61.1] always3(s34) || -> . % 75.92/76.15 8451[45:SSi:8450.0,723.0] || -> . % 75.92/76.15 8452[45:Spt:8451.0,8447.1,8448.0] || m_main_v_state(s34,c_busy)*+ -> . % 75.92/76.15 8453[45:Spt:8451.0,8447.0,8447.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 75.92/76.15 8456[45:Res:53.1,8453.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 75.92/76.15 8461[46:Spt:8456.1] || -> xuntil6(s33)*. % 75.92/76.15 8462[46:MRR:143.0,8461.0] || -> until5(s34)*. % 75.92/76.15 8463[46:MRR:7483.0,8462.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.15 8465[47:Spt:8463.2] || -> xuntil6(s34)*. % 75.92/76.15 8466[47:MRR:142.0,8465.0] || -> until5(s35)*. % 75.92/76.15 8467[47:MRR:930.0,8466.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.15 8468[48:Spt:8467.1] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.15 8470[48:Res:8468.0,61.1] always3(s36) || -> . % 75.92/76.15 8471[48:SSi:8470.0,725.0] || -> . % 75.92/76.15 8472[48:Spt:8471.0,8467.1,8468.0] || m_main_v_state(s36,c_busy)*+ -> . % 75.92/76.15 8473[48:Spt:8471.0,8467.0,8467.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 75.92/76.15 8476[48:Res:53.1,8473.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 75.92/76.15 8478[49:Spt:8476.1] || -> xuntil6(s35)*. % 75.92/76.15 8479[49:MRR:141.0,8478.0] || -> until5(s36)*. % 75.92/76.15 8480[49:MRR:7484.0,8479.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.15 8485[50:Spt:8480.2] || -> xuntil6(s36)*. % 75.92/76.15 8486[50:MRR:140.0,8485.0] || -> until5(s37)*. % 75.92/76.15 8487[50:MRR:928.0,8486.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.15 8488[51:Spt:8487.1] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.15 8490[51:Res:8488.0,61.1] always3(s38) || -> . % 75.92/76.15 8491[51:SSi:8490.0,727.0] || -> . % 75.92/76.15 8492[51:Spt:8491.0,8487.1,8488.0] || m_main_v_state(s38,c_busy)*+ -> . % 75.92/76.15 8493[51:Spt:8491.0,8487.0,8487.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 75.92/76.15 8496[51:Res:53.1,8493.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 75.92/76.15 8498[52:Spt:8496.1] || -> xuntil6(s37)*. % 75.92/76.15 8499[52:MRR:139.0,8498.0] || -> until5(s38)*. % 75.92/76.15 8500[52:MRR:7488.0,8499.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.15 8508[53:Spt:8500.2] || -> xuntil6(s38)*. % 75.92/76.15 8509[53:MRR:138.0,8508.0] || -> until5(s39)*. % 75.92/76.15 8510[53:MRR:926.0,8509.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.15 8511[54:Spt:8510.1] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.15 8513[54:Res:8511.0,61.1] always3(s40) || -> . % 75.92/76.15 8514[54:SSi:8513.0,729.0] || -> . % 75.92/76.15 8515[54:Spt:8514.0,8510.1,8511.0] || m_main_v_state(s40,c_busy)*+ -> . % 75.92/76.15 8516[54:Spt:8514.0,8510.0,8510.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 75.92/76.15 8519[54:Res:53.1,8516.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 75.92/76.15 8524[55:Spt:8519.1] || -> xuntil6(s39)*. % 75.92/76.15 8525[55:MRR:137.0,8524.0] || -> until5(s40)*. % 75.92/76.15 8526[55:MRR:7492.0,8525.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.15 8528[56:Spt:8526.2] || -> xuntil6(s40)*. % 75.92/76.15 8529[56:MRR:136.0,8528.0] || -> until5(s41)*. % 75.92/76.15 8530[56:MRR:924.0,8529.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.15 8531[57:Spt:8530.1] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.15 8533[57:Res:8531.0,61.1] always3(s42) || -> . % 75.92/76.15 8534[57:SSi:8533.0,731.0] || -> . % 75.92/76.15 8535[57:Spt:8534.0,8530.1,8531.0] || m_main_v_state(s42,c_busy)*+ -> . % 75.92/76.15 8536[57:Spt:8534.0,8530.0,8530.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 75.92/76.15 8539[57:MRR:8275.2,8535.0] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.15 8540[57:Res:53.1,8536.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 75.92/76.15 8542[58:Spt:8540.1] || -> xuntil6(s41)*. % 75.92/76.15 8543[58:MRR:135.0,8542.0] || -> until5(s42)*. % 75.92/76.15 8544[58:MRR:7496.0,8543.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.15 8550[57:SoR:8539.0,64.1] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.15 8552[57:SoR:8550.0,66.2] until5(s49) || m_main_v_state(s49,c_ready)* -> xuntil6(s49). % 75.92/76.15 8553[59:Spt:8544.2] || -> xuntil6(s42)*. % 75.92/76.15 8554[59:MRR:134.0,8553.0] || -> until5(s43)*. % 75.92/76.15 8555[59:MRR:922.0,8554.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.15 8556[60:Spt:8555.1] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.15 8558[60:Res:8556.0,61.1] always3(s44) || -> . % 75.92/76.15 8559[60:SSi:8558.0,733.0] || -> . % 75.92/76.15 8560[60:Spt:8559.0,8555.1,8556.0] || m_main_v_state(s44,c_busy)*+ -> . % 75.92/76.15 8561[60:Spt:8559.0,8555.0,8555.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 75.92/76.15 8563[60:MRR:789.2,8560.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 75.92/76.15 8564[60:Res:53.1,8561.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 75.92/76.15 8566[61:Spt:8564.1] || -> xuntil6(s43)*. % 75.92/76.15 8567[61:MRR:133.0,8566.0] || -> until5(s44)*. % 75.92/76.15 8568[61:MRR:7503.0,8567.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.15 8573[62:Spt:8568.2] || -> xuntil6(s44)*. % 75.92/76.15 8574[62:MRR:132.0,8573.0] || -> until5(s45)*. % 75.92/76.15 8575[62:MRR:920.0,8574.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.15 8579[63:Spt:8575.1] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.15 8581[63:Res:8579.0,61.1] always3(s46) || -> . % 75.92/76.15 8582[63:SSi:8581.0,735.0] || -> . % 75.92/76.15 8583[63:Spt:8582.0,8575.1,8579.0] || m_main_v_state(s46,c_busy)*+ -> . % 75.92/76.15 8584[63:Spt:8582.0,8575.0,8575.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 75.92/76.15 8586[63:MRR:783.2,8583.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 75.92/76.15 8587[63:Res:53.1,8584.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 75.92/76.15 8589[64:Spt:8587.1] || -> xuntil6(s45)*. % 75.92/76.15 8590[64:MRR:131.0,8589.0] || -> until5(s46)*. % 75.92/76.15 8591[64:MRR:7504.0,8590.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.15 8596[65:Spt:8591.2] || -> xuntil6(s46)*. % 75.92/76.15 8597[65:MRR:130.0,8596.0] || -> until5(s47)*. % 75.92/76.15 8598[65:MRR:918.0,8597.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.15 8599[66:Spt:8598.1] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.15 8601[66:Res:8599.0,61.1] always3(s48) || -> . % 75.92/76.15 8602[66:SSi:8601.0,737.0] || -> . % 75.92/76.15 8603[66:Spt:8602.0,8598.1,8599.0] || m_main_v_state(s48,c_busy)*+ -> . % 75.92/76.15 8604[66:Spt:8602.0,8598.0,8598.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 75.92/76.15 8606[66:MRR:777.2,8603.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 75.92/76.15 8607[66:Res:53.1,8604.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 75.92/76.15 8609[67:Spt:8607.1] || -> xuntil6(s47)*. % 75.92/76.15 8610[67:MRR:129.0,8609.0] || -> until5(s48)*. % 75.92/76.15 8611[67:MRR:7508.0,8610.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.15 8619[68:Spt:8611.2] || -> xuntil6(s48)*. % 75.92/76.15 8620[68:MRR:128.0,8619.0] || -> until5(s49)*. % 75.92/76.15 8621[68:MRR:8552.0,8620.0] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.15 8622[68:Res:53.1,8621.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.15 8624[69:Spt:8622.1] || -> xuntil6(s49)*. % 75.92/76.15 8625[69:MRR:8274.0,8624.0] || -> until2p7(s42)*. % 75.92/76.15 8626[69:MRR:240.0,8625.0] || -> until2p7(s43)* node4(s42). % 75.92/76.15 8627[70:Spt:8626.0] || -> until2p7(s43)*. % 75.92/76.15 8628[70:MRR:241.0,8627.0] || -> until2p7(s44)* node4(s43). % 75.92/76.15 8629[71:Spt:8628.0] || -> until2p7(s44)*. % 75.92/76.15 8630[71:MRR:539.0,8629.0] || -> until2p7(s45)* node4(s44). % 75.92/76.15 8631[72:Spt:8630.0] || -> until2p7(s45)*. % 75.92/76.15 8632[72:MRR:544.0,8631.0] || -> until2p7(s46)* node4(s45). % 75.92/76.15 8633[73:Spt:8632.0] || -> until2p7(s46)*. % 75.92/76.15 8634[73:MRR:549.0,8633.0] || -> until2p7(s47)* node4(s46). % 75.92/76.15 8635[74:Spt:8634.0] || -> until2p7(s47)*. % 75.92/76.15 8636[74:MRR:554.0,8635.0] || -> until2p7(s48)* node4(s47). % 75.92/76.15 8637[75:Spt:8636.0] || -> until2p7(s48)*. % 75.92/76.15 8638[75:MRR:559.0,8637.0] || -> until2p7(s49)* node4(s48). % 75.92/76.15 8639[76:Spt:8638.0] || -> until2p7(s49)*. % 75.92/76.15 8640[76:MRR:194.0,8639.0] || -> node4(s49)*. % 75.92/76.15 8641[76:MRR:8550.0,8640.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.15 8642[76:Res:53.1,8641.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 8648[76:Res:8642.0,61.1] always3(s49) || -> . % 75.92/76.15 8649[76:SSi:8648.0,50.0,738.0,8620.0,8624.0,8639.0,8640.0] || -> . % 75.92/76.15 8650[76:Spt:8649.0,8638.0,8639.0] || until2p7(s49)*+ -> . % 75.92/76.15 8651[76:Spt:8649.0,8638.1] || -> node4(s48)*. % 75.92/76.15 8653[76:MRR:774.0,8651.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.15 8662[76:Res:53.1,8653.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.15 8664[76:MRR:8662.0,8603.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 8666[76:Res:8664.0,61.1] always3(s49) || -> . % 75.92/76.15 8667[76:SSi:8666.0,50.0,738.0,8620.0,8624.0] || -> . % 75.92/76.15 8668[75:Spt:8667.0,8636.0,8637.0] || until2p7(s48)*+ -> . % 75.92/76.15 8669[75:Spt:8667.0,8636.1] || -> node4(s47)*. % 75.92/76.15 8670[75:MRR:8606.0,8669.0] || m_main_v_state(s47,c_ready)*+ -> . % 75.92/76.15 8673[75:Res:53.1,8670.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 8676[75:Res:8673.0,61.1] always3(s47) || -> . % 75.92/76.15 8677[75:SSi:8676.0,736.0,8597.0,8609.0,8635.0,8669.0] || -> . % 75.92/76.15 8678[74:Spt:8677.0,8634.0,8635.0] || until2p7(s47)*+ -> . % 75.92/76.15 8679[74:Spt:8677.0,8634.1] || -> node4(s46)*. % 75.92/76.15 8681[74:MRR:780.0,8679.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.15 8693[74:Res:53.1,8681.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.15 8695[74:MRR:8693.0,8583.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 8700[74:Res:8695.0,61.1] always3(s47) || -> . % 75.92/76.15 8701[74:SSi:8700.0,736.0,8597.0,8609.0] || -> . % 75.92/76.15 8702[73:Spt:8701.0,8632.0,8633.0] || until2p7(s46)*+ -> . % 75.92/76.15 8703[73:Spt:8701.0,8632.1] || -> node4(s45)*. % 75.92/76.15 8704[73:MRR:8586.0,8703.0] || m_main_v_state(s45,c_ready)*+ -> . % 75.92/76.15 8707[73:Res:53.1,8704.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 8711[73:Res:8707.0,61.1] always3(s45) || -> . % 75.92/76.15 8712[73:SSi:8711.0,734.0,8574.0,8589.0,8631.0,8703.0] || -> . % 75.92/76.15 8713[72:Spt:8712.0,8630.0,8631.0] || until2p7(s45)*+ -> . % 75.92/76.15 8714[72:Spt:8712.0,8630.1] || -> node4(s44)*. % 75.92/76.15 8716[72:MRR:786.0,8714.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.15 8727[72:Res:53.1,8716.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.15 8729[72:MRR:8727.0,8560.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 8731[72:Res:8729.0,61.1] always3(s45) || -> . % 75.92/76.15 8732[72:SSi:8731.0,734.0,8574.0,8589.0] || -> . % 75.92/76.15 8733[71:Spt:8732.0,8628.0,8629.0] || until2p7(s44)*+ -> . % 75.92/76.15 8734[71:Spt:8732.0,8628.1] || -> node4(s43)*. % 75.92/76.15 8735[71:MRR:8563.0,8734.0] || m_main_v_state(s43,c_ready)*+ -> . % 75.92/76.15 8739[71:Res:53.1,8735.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 8742[71:Res:8739.0,61.1] always3(s43) || -> . % 75.92/76.15 8743[71:SSi:8742.0,732.0,8554.0,8566.0,8627.0,8734.0] || -> . % 75.92/76.15 8744[70:Spt:8743.0,8626.0,8627.0] || until2p7(s43)*+ -> . % 75.92/76.15 8745[70:Spt:8743.0,8626.1] || -> node4(s42)*. % 75.92/76.15 8747[70:MRR:792.0,8745.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.15 8758[70:Res:53.1,8747.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.15 8760[70:MRR:8758.0,8535.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 8762[70:Res:8760.0,61.1] always3(s43) || -> . % 75.92/76.15 8763[70:SSi:8762.0,732.0,8554.0,8566.0] || -> . % 75.92/76.15 8764[69:Spt:8763.0,8622.1,8624.0] || xuntil6(s49)* -> . % 75.92/76.15 8765[69:Spt:8763.0,8622.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 8768[69:Res:8765.0,61.1] always3(s49) || -> . % 75.92/76.15 8769[69:SSi:8768.0,50.0,738.0,8620.0] || -> . % 75.92/76.15 8770[68:Spt:8769.0,8611.2,8619.0] || xuntil6(s48)*+ -> . % 75.92/76.15 8771[68:Spt:8769.0,8611.0,8611.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.15 8772[68:Res:53.1,8771.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.15 8774[68:MRR:8772.0,8603.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 8777[68:Res:8774.0,61.1] always3(s49) || -> . % 75.92/76.15 8778[68:SSi:8777.0,50.0,738.0] || -> . % 75.92/76.15 8779[67:Spt:8778.0,8607.1,8609.0] || xuntil6(s47)* -> . % 75.92/76.15 8780[67:Spt:8778.0,8607.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 8783[67:Res:8780.0,61.1] always3(s47) || -> . % 75.92/76.15 8784[67:SSi:8783.0,736.0,8597.0] || -> . % 75.92/76.15 8785[65:Spt:8784.0,8591.2,8596.0] || xuntil6(s46)*+ -> . % 75.92/76.15 8786[65:Spt:8784.0,8591.0,8591.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.15 8787[65:Res:53.1,8786.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.15 8789[65:MRR:8787.0,8583.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 8791[65:Res:8789.0,61.1] always3(s47) || -> . % 75.92/76.15 8792[65:SSi:8791.0,736.0] || -> . % 75.92/76.15 8793[64:Spt:8792.0,8587.1,8589.0] || xuntil6(s45)* -> . % 75.92/76.15 8794[64:Spt:8792.0,8587.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 8797[64:Res:8794.0,61.1] always3(s45) || -> . % 75.92/76.15 8798[64:SSi:8797.0,734.0,8574.0] || -> . % 75.92/76.15 8799[62:Spt:8798.0,8568.2,8573.0] || xuntil6(s44)*+ -> . % 75.92/76.15 8800[62:Spt:8798.0,8568.0,8568.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.15 8801[62:Res:53.1,8800.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.15 8803[62:MRR:8801.0,8560.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 8806[62:Res:8803.0,61.1] always3(s45) || -> . % 75.92/76.15 8807[62:SSi:8806.0,734.0] || -> . % 75.92/76.15 8808[61:Spt:8807.0,8564.1,8566.0] || xuntil6(s43)* -> . % 75.92/76.15 8809[61:Spt:8807.0,8564.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 8812[61:Res:8809.0,61.1] always3(s43) || -> . % 75.92/76.15 8813[61:SSi:8812.0,732.0,8554.0] || -> . % 75.92/76.15 8814[59:Spt:8813.0,8544.2,8553.0] || xuntil6(s42)*+ -> . % 75.92/76.15 8815[59:Spt:8813.0,8544.0,8544.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.15 8816[59:Res:53.1,8815.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.15 8818[59:MRR:8816.0,8535.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 8820[59:Res:8818.0,61.1] always3(s43) || -> . % 75.92/76.15 8821[59:SSi:8820.0,732.0] || -> . % 75.92/76.15 8822[58:Spt:8821.0,8540.1,8542.0] || xuntil6(s41)* -> . % 75.92/76.15 8823[58:Spt:8821.0,8540.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.15 8826[58:Res:8823.0,61.1] always3(s41) || -> . % 75.92/76.15 8827[58:SSi:8826.0,730.0,8529.0] || -> . % 75.92/76.15 8828[56:Spt:8827.0,8526.2,8528.0] || xuntil6(s40)*+ -> . % 75.92/76.15 8829[56:Spt:8827.0,8526.0,8526.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.15 8830[56:Res:53.1,8829.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.15 8832[56:MRR:8830.0,8515.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.15 8834[56:Res:8832.0,61.1] always3(s41) || -> . % 75.92/76.15 8835[56:SSi:8834.0,730.0] || -> . % 75.92/76.15 8836[55:Spt:8835.0,8519.1,8524.0] || xuntil6(s39)* -> . % 75.92/76.15 8837[55:Spt:8835.0,8519.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.15 8840[55:Res:8837.0,61.1] always3(s39) || -> . % 75.92/76.15 8841[55:SSi:8840.0,728.0,8509.0] || -> . % 75.92/76.15 8842[53:Spt:8841.0,8500.2,8508.0] || xuntil6(s38)*+ -> . % 75.92/76.15 8843[53:Spt:8841.0,8500.0,8500.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.15 8844[53:Res:53.1,8843.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.15 8846[53:MRR:8844.0,8492.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.15 8848[53:Res:8846.0,61.1] always3(s39) || -> . % 75.92/76.15 8849[53:SSi:8848.0,728.0] || -> . % 75.92/76.15 8850[52:Spt:8849.0,8496.1,8498.0] || xuntil6(s37)* -> . % 75.92/76.15 8851[52:Spt:8849.0,8496.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.15 8854[52:Res:8851.0,61.1] always3(s37) || -> . % 75.92/76.15 8855[52:SSi:8854.0,726.0,8486.0] || -> . % 75.92/76.15 8856[50:Spt:8855.0,8480.2,8485.0] || xuntil6(s36)*+ -> . % 75.92/76.15 8857[50:Spt:8855.0,8480.0,8480.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.15 8858[50:Res:53.1,8857.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.15 8860[50:MRR:8858.0,8472.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.15 8862[50:Res:8860.0,61.1] always3(s37) || -> . % 75.92/76.15 8863[50:SSi:8862.0,726.0] || -> . % 75.92/76.15 8864[49:Spt:8863.0,8476.1,8478.0] || xuntil6(s35)* -> . % 75.92/76.15 8865[49:Spt:8863.0,8476.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.15 8868[49:Res:8865.0,61.1] always3(s35) || -> . % 75.92/76.15 8869[49:SSi:8868.0,724.0,8466.0] || -> . % 75.92/76.15 8870[47:Spt:8869.0,8463.2,8465.0] || xuntil6(s34)*+ -> . % 75.92/76.15 8871[47:Spt:8869.0,8463.0,8463.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 75.92/76.15 8872[47:Res:53.1,8871.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 75.92/76.15 8874[47:MRR:8872.0,8452.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.15 8876[47:Res:8874.0,61.1] always3(s35) || -> . % 75.92/76.15 8877[47:SSi:8876.0,724.0] || -> . % 75.92/76.15 8878[46:Spt:8877.0,8456.1,8461.0] || xuntil6(s33)* -> . % 75.92/76.15 8879[46:Spt:8877.0,8456.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.15 8882[46:Res:8879.0,61.1] always3(s33) || -> . % 75.92/76.15 8883[46:SSi:8882.0,722.0,8446.0] || -> . % 75.92/76.15 8884[44:Spt:8883.0,8437.2,8445.0] || xuntil6(s32)*+ -> . % 75.92/76.15 8885[44:Spt:8883.0,8437.0,8437.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 75.92/76.15 8886[44:Res:53.1,8885.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 75.92/76.15 8888[44:MRR:8886.0,8429.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.15 8890[44:Res:8888.0,61.1] always3(s33) || -> . % 75.92/76.15 8891[44:SSi:8890.0,722.0] || -> . % 75.92/76.15 8892[43:Spt:8891.0,8433.1,8435.0] || xuntil6(s31)* -> . % 75.92/76.15 8893[43:Spt:8891.0,8433.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.15 8896[43:Res:8893.0,61.1] always3(s31) || -> . % 75.92/76.15 8897[43:SSi:8896.0,720.0,8423.0] || -> . % 75.92/76.15 8898[41:Spt:8897.0,8417.2,8422.0] || xuntil6(s30)*+ -> . % 75.92/76.15 8899[41:Spt:8897.0,8417.0,8417.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.15 8900[41:Res:53.1,8899.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.15 8902[41:MRR:8900.0,8409.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.15 8904[41:Res:8902.0,61.1] always3(s31) || -> . % 75.92/76.15 8905[41:SSi:8904.0,720.0] || -> . % 75.92/76.15 8906[40:Spt:8905.0,8413.1,8415.0] || xuntil6(s29)* -> . % 75.92/76.15 8907[40:Spt:8905.0,8413.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.15 8910[40:Res:8907.0,61.1] always3(s29) || -> . % 75.92/76.15 8911[40:SSi:8910.0,718.0,8400.0] || -> . % 75.92/76.15 8912[38:Spt:8911.0,8398.2,8399.0] || xuntil6(s28)*+ -> . % 75.92/76.15 8913[38:Spt:8911.0,8398.0,8398.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.15 8914[38:Res:53.1,8913.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.15 8916[39:Spt:8914.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.15 8918[39:Res:8916.0,61.1] always3(s28) || -> . % 75.92/76.15 8919[39:SSi:8918.0,717.0,8397.0] || -> . % 75.92/76.15 8920[39:Spt:8919.0,8914.0,8916.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.15 8921[39:Spt:8919.0,8914.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.15 8925[39:Res:8921.0,61.1] always3(s29) || -> . % 75.92/76.15 8926[39:SSi:8925.0,718.0] || -> . % 75.92/76.15 8927[37:Spt:8926.0,8392.2,8396.0] || xuntil6(s27)*+ -> . % 75.92/76.15 8928[37:Spt:8926.0,8392.0,8392.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.15 8929[37:Res:53.1,8928.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.15 8931[38:Spt:8929.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.15 8933[38:Res:8931.0,61.1] always3(s27) || -> . % 75.92/76.15 8934[38:SSi:8933.0,716.0,8391.0] || -> . % 75.92/76.15 8935[38:Spt:8934.0,8929.0,8931.0] || m_main_v_state(s27,c_busy)* -> . % 75.92/76.15 8936[38:Spt:8934.0,8929.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.15 8940[38:Res:8936.0,61.1] always3(s28) || -> . % 75.92/76.15 8941[38:SSi:8940.0,717.0] || -> . % 75.92/76.15 8942[36:Spt:8941.0,8389.2,8390.0] || xuntil6(s26)*+ -> . % 75.92/76.15 8943[36:Spt:8941.0,8389.0,8389.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.15 8944[36:Res:53.1,8943.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.15 8946[37:Spt:8944.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.15 8948[37:Res:8946.0,61.1] always3(s26) || -> . % 75.92/76.15 8949[37:SSi:8948.0,715.0,8388.0] || -> . % 75.92/76.15 8950[37:Spt:8949.0,8944.0,8946.0] || m_main_v_state(s26,c_busy)* -> . % 75.92/76.15 8951[37:Spt:8949.0,8944.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.15 8955[37:Res:8951.0,61.1] always3(s27) || -> . % 75.92/76.15 8956[37:SSi:8955.0,716.0] || -> . % 75.92/76.15 8957[35:Spt:8956.0,8383.2,8387.0] || xuntil6(s25)*+ -> . % 75.92/76.15 8958[35:Spt:8956.0,8383.0,8383.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.15 8959[35:Res:53.1,8958.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.15 8961[36:Spt:8959.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.15 8963[36:Res:8961.0,61.1] always3(s25) || -> . % 75.92/76.15 8964[36:SSi:8963.0,714.0,8382.0] || -> . % 75.92/76.15 8965[36:Spt:8964.0,8959.0,8961.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.15 8966[36:Spt:8964.0,8959.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.15 8970[36:Res:8966.0,61.1] always3(s26) || -> . % 75.92/76.15 8971[36:SSi:8970.0,715.0] || -> . % 75.92/76.15 8972[34:Spt:8971.0,8380.2,8381.0] || xuntil6(s24)*+ -> . % 75.92/76.15 8973[34:Spt:8971.0,8380.0,8380.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.15 8974[34:Res:53.1,8973.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.15 8976[35:Spt:8974.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.15 8978[35:Res:8976.0,61.1] always3(s24) || -> . % 75.92/76.15 8979[35:SSi:8978.0,713.0,8379.0] || -> . % 75.92/76.15 8980[35:Spt:8979.0,8974.0,8976.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.15 8981[35:Spt:8979.0,8974.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.15 8985[35:Res:8981.0,61.1] always3(s25) || -> . % 75.92/76.15 8986[35:SSi:8985.0,714.0] || -> . % 75.92/76.15 8987[33:Spt:8986.0,8374.2,8378.0] || xuntil6(s23)*+ -> . % 75.92/76.15 8988[33:Spt:8986.0,8374.0,8374.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.15 8989[33:Res:53.1,8988.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.15 8991[34:Spt:8989.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.15 8993[34:Res:8991.0,61.1] always3(s23) || -> . % 75.92/76.15 8994[34:SSi:8993.0,712.0,8373.0] || -> . % 75.92/76.15 8995[34:Spt:8994.0,8989.0,8991.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.15 8996[34:Spt:8994.0,8989.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.15 9000[34:Res:8996.0,61.1] always3(s24) || -> . % 75.92/76.15 9001[34:SSi:9000.0,713.0] || -> . % 75.92/76.15 9002[32:Spt:9001.0,8371.2,8372.0] || xuntil6(s22)*+ -> . % 75.92/76.15 9003[32:Spt:9001.0,8371.0,8371.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.15 9004[32:Res:53.1,9003.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.15 9006[33:Spt:9004.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.15 9008[33:Res:9006.0,61.1] always3(s23) || -> . % 75.92/76.15 9009[33:SSi:9008.0,712.0] || -> . % 75.92/76.15 9010[33:Spt:9009.0,9004.1,9006.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.15 9011[33:Spt:9009.0,9004.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.15 9014[33:Res:9011.0,61.1] always3(s22) || -> . % 75.92/76.15 9015[33:SSi:9014.0,711.0,8370.0] || -> . % 75.92/76.15 9016[31:Spt:9015.0,8365.2,8369.0] || xuntil6(s21)*+ -> . % 75.92/76.15 9017[31:Spt:9015.0,8365.0,8365.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.15 9018[31:Res:53.1,9017.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.15 9020[32:Spt:9018.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.15 9022[32:Res:9020.0,61.1] always3(s22) || -> . % 75.92/76.15 9023[32:SSi:9022.0,711.0] || -> . % 75.92/76.15 9024[32:Spt:9023.0,9018.1,9020.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.15 9025[32:Spt:9023.0,9018.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.15 9028[32:Res:9025.0,61.1] always3(s21) || -> . % 75.92/76.15 9029[32:SSi:9028.0,710.0,8364.0] || -> . % 75.92/76.15 9030[30:Spt:9029.0,8362.2,8363.0] || xuntil6(s20)*+ -> . % 75.92/76.15 9031[30:Spt:9029.0,8362.0,8362.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.15 9032[30:Res:53.1,9031.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.15 9037[31:Spt:9032.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.15 9039[31:Res:9037.0,61.1] always3(s20) || -> . % 75.92/76.15 9040[31:SSi:9039.0,709.0,8361.0] || -> . % 75.92/76.15 9041[31:Spt:9040.0,9032.0,9037.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.15 9042[31:Spt:9040.0,9032.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.15 9046[31:Res:9042.0,61.1] always3(s21) || -> . % 75.92/76.15 9047[31:SSi:9046.0,710.0] || -> . % 75.92/76.15 9048[29:Spt:9047.0,8356.2,8360.0] || xuntil6(s19)*+ -> . % 75.92/76.15 9049[29:Spt:9047.0,8356.0,8356.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.15 9050[29:Res:53.1,9049.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.15 9052[30:Spt:9050.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.15 9054[30:Res:9052.0,61.1] always3(s20) || -> . % 75.92/76.15 9055[30:SSi:9054.0,709.0] || -> . % 75.92/76.15 9056[30:Spt:9055.0,9050.1,9052.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.15 9057[30:Spt:9055.0,9050.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.15 9060[30:Res:9057.0,61.1] always3(s19) || -> . % 75.92/76.15 9061[30:SSi:9060.0,708.0,8355.0] || -> . % 75.92/76.15 9062[28:Spt:9061.0,8353.2,8354.0] || xuntil6(s18)*+ -> . % 75.92/76.15 9063[28:Spt:9061.0,8353.0,8353.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.15 9064[28:Res:53.1,9063.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.15 9066[29:Spt:9064.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.15 9068[29:Res:9066.0,61.1] always3(s19) || -> . % 75.92/76.15 9069[29:SSi:9068.0,708.0] || -> . % 75.92/76.15 9070[29:Spt:9069.0,9064.1,9066.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.15 9071[29:Spt:9069.0,9064.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.15 9074[29:Res:9071.0,61.1] always3(s18) || -> . % 75.92/76.15 9075[29:SSi:9074.0,707.0,8352.0] || -> . % 75.92/76.15 9076[27:Spt:9075.0,8347.2,8351.0] || xuntil6(s17)*+ -> . % 75.92/76.15 9077[27:Spt:9075.0,8347.0,8347.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.15 9078[27:Res:53.1,9077.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.15 9083[28:Spt:9078.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.15 9085[28:Res:9083.0,61.1] always3(s17) || -> . % 75.92/76.15 9086[28:SSi:9085.0,706.0,8346.0] || -> . % 75.92/76.15 9087[28:Spt:9086.0,9078.0,9083.0] || m_main_v_state(s17,c_busy)* -> . % 75.92/76.15 9088[28:Spt:9086.0,9078.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.15 9092[28:Res:9088.0,61.1] always3(s18) || -> . % 75.92/76.15 9093[28:SSi:9092.0,707.0] || -> . % 75.92/76.15 9094[26:Spt:9093.0,8344.2,8345.0] || xuntil6(s16)*+ -> . % 75.92/76.15 9095[26:Spt:9093.0,8344.0,8344.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.15 9096[26:Res:53.1,9095.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.15 9098[27:Spt:9096.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.15 9100[27:Res:9098.0,61.1] always3(s17) || -> . % 75.92/76.15 9101[27:SSi:9100.0,706.0] || -> . % 75.92/76.15 9102[27:Spt:9101.0,9096.1,9098.0] || m_main_v_state(s17,c_busy)* -> . % 75.92/76.15 9103[27:Spt:9101.0,9096.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.15 9106[27:Res:9103.0,61.1] always3(s16) || -> . % 75.92/76.15 9107[27:SSi:9106.0,705.0,8343.0] || -> . % 75.92/76.15 9108[25:Spt:9107.0,8338.2,8342.0] || xuntil6(s15)*+ -> . % 75.92/76.15 9109[25:Spt:9107.0,8338.0,8338.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.15 9110[25:Res:53.1,9109.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.15 9112[26:Spt:9110.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.15 9114[26:Res:9112.0,61.1] always3(s16) || -> . % 75.92/76.15 9115[26:SSi:9114.0,705.0] || -> . % 75.92/76.15 9116[26:Spt:9115.0,9110.1,9112.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.15 9117[26:Spt:9115.0,9110.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.15 9120[26:Res:9117.0,61.1] always3(s15) || -> . % 75.92/76.15 9121[26:SSi:9120.0,704.0,8337.0] || -> . % 75.92/76.15 9122[24:Spt:9121.0,8335.2,8336.0] || xuntil6(s14)*+ -> . % 75.92/76.15 9123[24:Spt:9121.0,8335.0,8335.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.15 9124[24:Res:53.1,9123.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.15 9129[25:Spt:9124.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.15 9131[25:Res:9129.0,61.1] always3(s14) || -> . % 75.92/76.15 9132[25:SSi:9131.0,703.0,8334.0] || -> . % 75.92/76.15 9133[25:Spt:9132.0,9124.0,9129.0] || m_main_v_state(s14,c_busy)* -> . % 75.92/76.15 9134[25:Spt:9132.0,9124.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.15 9138[25:Res:9134.0,61.1] always3(s15) || -> . % 75.92/76.15 9139[25:SSi:9138.0,704.0] || -> . % 75.92/76.15 9140[23:Spt:9139.0,8329.2,8333.0] || xuntil6(s13)*+ -> . % 75.92/76.15 9141[23:Spt:9139.0,8329.0,8329.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.15 9142[23:Res:53.1,9141.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.15 9144[24:Spt:9142.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.15 9146[24:Res:9144.0,61.1] always3(s14) || -> . % 75.92/76.15 9147[24:SSi:9146.0,703.0] || -> . % 75.92/76.15 9148[24:Spt:9147.0,9142.1,9144.0] || m_main_v_state(s14,c_busy)* -> . % 75.92/76.15 9149[24:Spt:9147.0,9142.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.15 9152[24:Res:9149.0,61.1] always3(s13) || -> . % 75.92/76.15 9153[24:SSi:9152.0,702.0,8328.0] || -> . % 75.92/76.15 9154[22:Spt:9153.0,8326.2,8327.0] || xuntil6(s12)*+ -> . % 75.92/76.15 9155[22:Spt:9153.0,8326.0,8326.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.15 9156[22:Res:53.1,9155.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.15 9158[23:Spt:9156.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.15 9160[23:Res:9158.0,61.1] always3(s13) || -> . % 75.92/76.15 9161[23:SSi:9160.0,702.0] || -> . % 75.92/76.15 9162[23:Spt:9161.0,9156.1,9158.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.15 9163[23:Spt:9161.0,9156.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.15 9166[23:Res:9163.0,61.1] always3(s12) || -> . % 75.92/76.15 9167[23:SSi:9166.0,701.0,8325.0] || -> . % 75.92/76.15 9168[21:Spt:9167.0,8320.2,8324.0] || xuntil6(s11)*+ -> . % 75.92/76.15 9169[21:Spt:9167.0,8320.0,8320.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.15 9170[21:Res:53.1,9169.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.15 9175[22:Spt:9170.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.15 9177[22:Res:9175.0,61.1] always3(s11) || -> . % 75.92/76.15 9178[22:SSi:9177.0,700.0,8319.0] || -> . % 75.92/76.15 9179[22:Spt:9178.0,9170.0,9175.0] || m_main_v_state(s11,c_busy)* -> . % 75.92/76.15 9180[22:Spt:9178.0,9170.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.15 9184[22:Res:9180.0,61.1] always3(s12) || -> . % 75.92/76.15 9185[22:SSi:9184.0,701.0] || -> . % 75.92/76.15 9186[20:Spt:9185.0,8317.2,8318.0] || xuntil6(s10)*+ -> . % 75.92/76.15 9187[20:Spt:9185.0,8317.0,8317.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.15 9188[20:Res:53.1,9187.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.15 9190[21:Spt:9188.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.15 9192[21:Res:9190.0,61.1] always3(s11) || -> . % 75.92/76.15 9193[21:SSi:9192.0,700.0] || -> . % 75.92/76.15 9194[21:Spt:9193.0,9188.1,9190.0] || m_main_v_state(s11,c_busy)* -> . % 75.92/76.15 9195[21:Spt:9193.0,9188.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.15 9198[21:Res:9195.0,61.1] always3(s10) || -> . % 75.92/76.15 9199[21:SSi:9198.0,699.0,8316.0] || -> . % 75.92/76.15 9200[19:Spt:9199.0,8311.2,8315.0] || xuntil6(s9)*+ -> . % 75.92/76.15 9201[19:Spt:9199.0,8311.0,8311.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.15 9202[19:Res:53.1,9201.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.15 9204[20:Spt:9202.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.15 9206[20:Res:9204.0,61.1] always3(s10) || -> . % 75.92/76.15 9207[20:SSi:9206.0,699.0] || -> . % 75.92/76.15 9208[20:Spt:9207.0,9202.1,9204.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.15 9209[20:Spt:9207.0,9202.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.15 9212[20:Res:9209.0,61.1] always3(s9) || -> . % 75.92/76.15 9213[20:SSi:9212.0,698.0,8310.0] || -> . % 75.92/76.15 9214[18:Spt:9213.0,8308.2,8309.0] || xuntil6(s8)*+ -> . % 75.92/76.15 9215[18:Spt:9213.0,8308.0,8308.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.15 9216[18:Res:53.1,9215.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.15 9221[19:Spt:9216.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.15 9223[19:Res:9221.0,61.1] always3(s8) || -> . % 75.92/76.15 9224[19:SSi:9223.0,697.0,8307.0] || -> . % 75.92/76.15 9225[19:Spt:9224.0,9216.0,9221.0] || m_main_v_state(s8,c_busy)* -> . % 75.92/76.15 9226[19:Spt:9224.0,9216.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.15 9230[19:Res:9226.0,61.1] always3(s9) || -> . % 75.92/76.15 9231[19:SSi:9230.0,698.0] || -> . % 75.92/76.15 9232[17:Spt:9231.0,8302.2,8306.0] || xuntil6(s7)*+ -> . % 75.92/76.15 9233[17:Spt:9231.0,8302.0,8302.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.15 9234[17:Res:53.1,9233.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.15 9236[18:Spt:9234.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.15 9238[18:Res:9236.0,61.1] always3(s8) || -> . % 75.92/76.15 9239[18:SSi:9238.0,697.0] || -> . % 75.92/76.15 9240[18:Spt:9239.0,9234.1,9236.0] || m_main_v_state(s8,c_busy)* -> . % 75.92/76.15 9241[18:Spt:9239.0,9234.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.15 9244[18:Res:9241.0,61.1] always3(s7) || -> . % 75.92/76.15 9245[18:SSi:9244.0,696.0,8301.0] || -> . % 75.92/76.15 9246[16:Spt:9245.0,8299.2,8300.0] || xuntil6(s6)*+ -> . % 75.92/76.15 9247[16:Spt:9245.0,8299.0,8299.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.15 9248[16:Res:53.1,9247.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.15 9250[17:Spt:9248.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.15 9252[17:Res:9250.0,61.1] always3(s7) || -> . % 75.92/76.15 9253[17:SSi:9252.0,696.0] || -> . % 75.92/76.15 9254[17:Spt:9253.0,9248.1,9250.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.15 9255[17:Spt:9253.0,9248.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.15 9258[17:Res:9255.0,61.1] always3(s6) || -> . % 75.92/76.15 9259[17:SSi:9258.0,695.0,8298.0] || -> . % 75.92/76.15 9260[15:Spt:9259.0,8293.2,8297.0] || xuntil6(s5)*+ -> . % 75.92/76.15 9261[15:Spt:9259.0,8293.0,8293.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.15 9262[15:Res:53.1,9261.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.15 9267[16:Spt:9262.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.15 9269[16:Res:9267.0,61.1] always3(s5) || -> . % 75.92/76.15 9270[16:SSi:9269.0,694.0,8292.0] || -> . % 75.92/76.15 9271[16:Spt:9270.0,9262.0,9267.0] || m_main_v_state(s5,c_busy)* -> . % 75.92/76.15 9272[16:Spt:9270.0,9262.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.15 9276[16:Res:9272.0,61.1] always3(s6) || -> . % 75.92/76.15 9277[16:SSi:9276.0,695.0] || -> . % 75.92/76.15 9278[14:Spt:9277.0,8290.2,8291.0] || xuntil6(s4)*+ -> . % 75.92/76.15 9279[14:Spt:9277.0,8290.0,8290.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.15 9280[14:Res:53.1,9279.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.15 9282[15:Spt:9280.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.15 9284[15:Res:9282.0,61.1] always3(s5) || -> . % 75.92/76.15 9285[15:SSi:9284.0,694.0] || -> . % 75.92/76.15 9286[15:Spt:9285.0,9280.1,9282.0] || m_main_v_state(s5,c_busy)* -> . % 75.92/76.15 9287[15:Spt:9285.0,9280.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.15 9290[15:Res:9287.0,61.1] always3(s4) || -> . % 75.92/76.15 9291[15:SSi:9290.0,693.0,8289.0] || -> . % 75.92/76.15 9292[13:Spt:9291.0,8287.2,8288.0] || xuntil6(s3)*+ -> . % 75.92/76.15 9293[13:Spt:9291.0,8287.0,8287.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.15 9294[13:Res:53.1,9293.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.15 9296[14:Spt:9294.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.15 9298[14:Res:9296.0,61.1] always3(s4) || -> . % 75.92/76.15 9299[14:SSi:9298.0,693.0] || -> . % 75.92/76.15 9300[14:Spt:9299.0,9294.1,9296.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.15 9301[14:Spt:9299.0,9294.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.15 9304[14:Res:9301.0,61.1] always3(s3) || -> . % 75.92/76.15 9305[14:SSi:9304.0,692.0,8286.0] || -> . % 75.92/76.15 9306[12:Spt:9305.0,8284.2,8285.0] || xuntil6(s2)*+ -> . % 75.92/76.15 9307[12:Spt:9305.0,8284.0,8284.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.15 9308[12:Res:53.1,9307.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.15 9313[13:Spt:9308.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.15 9315[13:Res:9313.0,61.1] always3(s2) || -> . % 75.92/76.15 9316[13:SSi:9315.0,691.0,8283.0] || -> . % 75.92/76.15 9317[13:Spt:9316.0,9308.0,9313.0] || m_main_v_state(s2,c_busy)* -> . % 75.92/76.15 9318[13:Spt:9316.0,9308.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.15 9322[13:Res:9318.0,61.1] always3(s3) || -> . % 75.92/76.15 9323[13:SSi:9322.0,692.0] || -> . % 75.92/76.15 9324[11:Spt:9323.0,8278.2,8282.0] || xuntil6(s1)*+ -> . % 75.92/76.15 9325[11:Spt:9323.0,8278.0,8278.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.15 9326[11:Res:53.1,9325.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.15 9328[12:Spt:9326.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.15 9330[12:Res:9328.0,61.1] always3(s1) || -> . % 75.92/76.15 9331[12:SSi:9330.0,690.0,8277.0] || -> . % 75.92/76.15 9332[12:Spt:9331.0,9326.0,9328.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.15 9333[12:Spt:9331.0,9326.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.15 9338[12:Res:9333.0,61.1] always3(s2) || -> . % 75.92/76.15 9339[12:SSi:9338.0,691.0] || -> . % 75.92/76.15 9340[10:Spt:9339.0,74.0,8276.0] || xuntil6(s0)*+ -> . % 75.92/76.15 9341[10:Spt:9339.0,74.1] || -> node4(s0)*. % 75.92/76.15 9342[10:MRR:758.1,9340.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.15 9344[10:Res:9342.0,61.1] always3(s1) || -> . % 75.92/76.15 9345[10:SSi:9344.0,690.0] || -> . % 75.92/76.15 9346[9:Spt:9345.0,8266.0,8270.0] || trans(s49,s42)*+ -> . % 75.92/76.15 9347[9:Spt:9345.0,8266.1,8266.2,8266.3,8266.4,8266.5,8266.6,8266.7,8266.8,8266.9,8266.10,8266.11,8266.12,8266.13,8266.14,8266.15,8266.16,8266.17,8266.18,8266.19,8266.20,8266.21,8266.22,8266.23,8266.24,8266.25,8266.26,8266.27,8266.28,8266.29,8266.30,8266.31,8266.32,8266.33,8266.34,8266.35,8266.36,8266.37,8266.38,8266.39,8266.40,8266.41,8266.42] || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.15 9349[9:MRR:8267.0,9346.0] || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.15 9350[9:MRR:8269.1,9346.0] xuntil6(s49) || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.15 9351[10:Spt:9347.0] || -> trans(s49,s41)*. % 75.92/76.15 9352[10:Res:9351.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s41)*. % 75.92/76.15 9354[10:Res:9351.0,60.0] || -> node2(s49,s41)*. % 75.92/76.15 9355[10:SSi:9352.1,50.0,738.0] xuntil6(s49) || -> until2p7(s41)*. % 75.92/76.15 9356[10:Res:9354.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)*. % 75.92/76.15 9357[11:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.15 9358[11:MRR:176.0,9357.0] || -> until5(s1)*. % 75.92/76.15 9359[11:MRR:7473.0,9358.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.15 9366[12:Spt:9359.2] || -> xuntil6(s1)*. % 75.92/76.15 9367[12:MRR:175.0,9366.0] || -> until5(s2)*. % 75.92/76.15 9368[12:MRR:7472.0,9367.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.15 9369[13:Spt:9368.2] || -> xuntil6(s2)*. % 75.92/76.15 9370[13:MRR:174.0,9369.0] || -> until5(s3)*. % 75.92/76.15 9371[13:MRR:7465.0,9370.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.15 9375[14:Spt:9371.2] || -> xuntil6(s3)*. % 75.92/76.15 9376[14:MRR:173.0,9375.0] || -> until5(s4)*. % 75.92/76.15 9377[14:MRR:7461.0,9376.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.15 9378[15:Spt:9377.2] || -> xuntil6(s4)*. % 75.92/76.15 9379[15:MRR:172.0,9378.0] || -> until5(s5)*. % 75.92/76.15 9380[15:MRR:7457.0,9379.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.15 9384[16:Spt:9380.2] || -> xuntil6(s5)*. % 75.92/76.15 9385[16:MRR:171.0,9384.0] || -> until5(s6)*. % 75.92/76.15 9386[16:MRR:7453.0,9385.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.15 9387[17:Spt:9386.2] || -> xuntil6(s6)*. % 75.92/76.15 9388[17:MRR:170.0,9387.0] || -> until5(s7)*. % 75.92/76.15 9389[17:MRR:7452.0,9388.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.15 9393[18:Spt:9389.2] || -> xuntil6(s7)*. % 75.92/76.15 9394[18:MRR:169.0,9393.0] || -> until5(s8)*. % 75.92/76.15 9395[18:MRR:7445.0,9394.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.15 9396[19:Spt:9395.2] || -> xuntil6(s8)*. % 75.92/76.15 9397[19:MRR:168.0,9396.0] || -> until5(s9)*. % 75.92/76.15 9398[19:MRR:7441.0,9397.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.15 9402[20:Spt:9398.2] || -> xuntil6(s9)*. % 75.92/76.15 9403[20:MRR:167.0,9402.0] || -> until5(s10)*. % 75.92/76.15 9404[20:MRR:7437.0,9403.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.15 9405[21:Spt:9404.2] || -> xuntil6(s10)*. % 75.92/76.15 9406[21:MRR:166.0,9405.0] || -> until5(s11)*. % 75.92/76.15 9407[21:MRR:7433.0,9406.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.15 9411[22:Spt:9407.2] || -> xuntil6(s11)*. % 75.92/76.15 9412[22:MRR:165.0,9411.0] || -> until5(s12)*. % 75.92/76.15 9413[22:MRR:7432.0,9412.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.15 9414[23:Spt:9413.2] || -> xuntil6(s12)*. % 75.92/76.15 9415[23:MRR:164.0,9414.0] || -> until5(s13)*. % 75.92/76.15 9416[23:MRR:7425.0,9415.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.15 9420[24:Spt:9416.2] || -> xuntil6(s13)*. % 75.92/76.15 9421[24:MRR:163.0,9420.0] || -> until5(s14)*. % 75.92/76.15 9422[24:MRR:7421.0,9421.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.15 9423[25:Spt:9422.2] || -> xuntil6(s14)*. % 75.92/76.15 9424[25:MRR:162.0,9423.0] || -> until5(s15)*. % 75.92/76.15 9425[25:MRR:7417.0,9424.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.15 9429[26:Spt:9425.2] || -> xuntil6(s15)*. % 75.92/76.15 9430[26:MRR:161.0,9429.0] || -> until5(s16)*. % 75.92/76.15 9431[26:MRR:7413.0,9430.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.15 9432[27:Spt:9431.2] || -> xuntil6(s16)*. % 75.92/76.15 9433[27:MRR:160.0,9432.0] || -> until5(s17)*. % 75.92/76.15 9434[27:MRR:7412.0,9433.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.15 9438[28:Spt:9434.2] || -> xuntil6(s17)*. % 75.92/76.15 9439[28:MRR:159.0,9438.0] || -> until5(s18)*. % 75.92/76.15 9440[28:MRR:7405.0,9439.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.15 9441[29:Spt:9440.2] || -> xuntil6(s18)*. % 75.92/76.15 9442[29:MRR:158.0,9441.0] || -> until5(s19)*. % 75.92/76.15 9443[29:MRR:7401.0,9442.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.15 9447[30:Spt:9443.2] || -> xuntil6(s19)*. % 75.92/76.15 9448[30:MRR:157.0,9447.0] || -> until5(s20)*. % 75.92/76.15 9449[30:MRR:7397.0,9448.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.15 9450[31:Spt:9449.2] || -> xuntil6(s20)*. % 75.92/76.15 9451[31:MRR:156.0,9450.0] || -> until5(s21)*. % 75.92/76.15 9452[31:MRR:7393.0,9451.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.15 9456[32:Spt:9452.2] || -> xuntil6(s21)*. % 75.92/76.15 9457[32:MRR:155.0,9456.0] || -> until5(s22)*. % 75.92/76.15 9458[32:MRR:7392.0,9457.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.15 9459[33:Spt:9458.2] || -> xuntil6(s22)*. % 75.92/76.15 9460[33:MRR:154.0,9459.0] || -> until5(s23)*. % 75.92/76.15 9461[33:MRR:7385.0,9460.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.15 9465[34:Spt:9461.2] || -> xuntil6(s23)*. % 75.92/76.15 9466[34:MRR:153.0,9465.0] || -> until5(s24)*. % 75.92/76.15 9467[34:MRR:7381.0,9466.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.15 9468[35:Spt:9467.2] || -> xuntil6(s24)*. % 75.92/76.15 9469[35:MRR:152.0,9468.0] || -> until5(s25)*. % 75.92/76.15 9470[35:MRR:7377.0,9469.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.15 9474[36:Spt:9470.2] || -> xuntil6(s25)*. % 75.92/76.15 9475[36:MRR:151.0,9474.0] || -> until5(s26)*. % 75.92/76.15 9476[36:MRR:7373.0,9475.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.15 9477[37:Spt:9476.2] || -> xuntil6(s26)*. % 75.92/76.15 9478[37:MRR:150.0,9477.0] || -> until5(s27)*. % 75.92/76.15 9479[37:MRR:7372.0,9478.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.15 9483[38:Spt:9479.2] || -> xuntil6(s27)*. % 75.92/76.15 9484[38:MRR:149.0,9483.0] || -> until5(s28)*. % 75.92/76.15 9485[38:MRR:7365.0,9484.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.15 9486[39:Spt:9485.2] || -> xuntil6(s28)*. % 75.92/76.15 9487[39:MRR:148.0,9486.0] || -> until5(s29)*. % 75.92/76.15 9488[39:MRR:7364.0,9487.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.15 9492[40:Spt:9488.2] || -> xuntil6(s29)*. % 75.92/76.15 9493[40:MRR:147.0,9492.0] || -> until5(s30)*. % 75.92/76.15 9494[40:MRR:7363.0,9493.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.15 9495[41:Spt:9494.2] || -> xuntil6(s30)*. % 75.92/76.15 9496[41:MRR:146.0,9495.0] || -> until5(s31)*. % 75.92/76.15 9497[41:MRR:7359.0,9496.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.15 9501[42:Spt:9497.2] || -> xuntil6(s31)*. % 75.92/76.15 9502[42:MRR:145.0,9501.0] || -> until5(s32)*. % 75.92/76.15 9503[42:MRR:7358.0,9502.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.15 9504[43:Spt:9503.1] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.15 9506[43:Res:9504.0,61.1] always3(s33) || -> . % 75.92/76.15 9507[43:SSi:9506.0,722.0] || -> . % 75.92/76.15 9508[43:Spt:9507.0,9503.1,9504.0] || m_main_v_state(s33,c_busy)*+ -> . % 75.92/76.15 9509[43:Spt:9507.0,9503.0,9503.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 75.92/76.15 9512[43:Res:53.1,9509.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 75.92/76.15 9517[44:Spt:9512.1] || -> xuntil6(s32)*. % 75.92/76.15 9518[44:MRR:144.0,9517.0] || -> until5(s33)*. % 75.92/76.15 9519[44:MRR:932.0,9518.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.15 9521[45:Spt:9519.2] || -> xuntil6(s33)*. % 75.92/76.15 9522[45:MRR:143.0,9521.0] || -> until5(s34)*. % 75.92/76.15 9523[45:MRR:7483.0,9522.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.15 9524[46:Spt:9523.1] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.15 9526[46:Res:9524.0,61.1] always3(s35) || -> . % 75.92/76.15 9527[46:SSi:9526.0,724.0] || -> . % 75.92/76.15 9528[46:Spt:9527.0,9523.1,9524.0] || m_main_v_state(s35,c_busy)*+ -> . % 75.92/76.15 9529[46:Spt:9527.0,9523.0,9523.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 75.92/76.15 9532[46:Res:53.1,9529.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 75.92/76.15 9534[47:Spt:9532.1] || -> xuntil6(s34)*. % 75.92/76.15 9535[47:MRR:142.0,9534.0] || -> until5(s35)*. % 75.92/76.15 9536[47:MRR:930.0,9535.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.15 9541[48:Spt:9536.2] || -> xuntil6(s35)*. % 75.92/76.15 9542[48:MRR:141.0,9541.0] || -> until5(s36)*. % 75.92/76.15 9543[48:MRR:7484.0,9542.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.15 9544[49:Spt:9543.1] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.15 9546[49:Res:9544.0,61.1] always3(s37) || -> . % 75.92/76.15 9547[49:SSi:9546.0,726.0] || -> . % 75.92/76.15 9548[49:Spt:9547.0,9543.1,9544.0] || m_main_v_state(s37,c_busy)*+ -> . % 75.92/76.15 9549[49:Spt:9547.0,9543.0,9543.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 75.92/76.15 9552[49:Res:53.1,9549.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 75.92/76.15 9554[50:Spt:9552.1] || -> xuntil6(s36)*. % 75.92/76.15 9555[50:MRR:140.0,9554.0] || -> until5(s37)*. % 75.92/76.15 9556[50:MRR:928.0,9555.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.15 9564[51:Spt:9556.2] || -> xuntil6(s37)*. % 75.92/76.15 9565[51:MRR:139.0,9564.0] || -> until5(s38)*. % 75.92/76.15 9566[51:MRR:7488.0,9565.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.15 9567[52:Spt:9566.1] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.15 9569[52:Res:9567.0,61.1] always3(s39) || -> . % 75.92/76.15 9570[52:SSi:9569.0,728.0] || -> . % 75.92/76.15 9571[52:Spt:9570.0,9566.1,9567.0] || m_main_v_state(s39,c_busy)*+ -> . % 75.92/76.15 9572[52:Spt:9570.0,9566.0,9566.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 75.92/76.15 9575[52:Res:53.1,9572.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 75.92/76.15 9580[53:Spt:9575.1] || -> xuntil6(s38)*. % 75.92/76.15 9581[53:MRR:138.0,9580.0] || -> until5(s39)*. % 75.92/76.15 9582[53:MRR:926.0,9581.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.15 9584[54:Spt:9582.2] || -> xuntil6(s39)*. % 75.92/76.15 9585[54:MRR:137.0,9584.0] || -> until5(s40)*. % 75.92/76.15 9586[54:MRR:7492.0,9585.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.15 9587[55:Spt:9586.1] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.15 9589[55:Res:9587.0,61.1] always3(s41) || -> . % 75.92/76.15 9590[55:SSi:9589.0,730.0] || -> . % 75.92/76.15 9591[55:Spt:9590.0,9586.1,9587.0] || m_main_v_state(s41,c_busy)*+ -> . % 75.92/76.15 9592[55:Spt:9590.0,9586.0,9586.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 75.92/76.15 9595[55:MRR:9356.2,9591.0] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.15 9596[55:Res:53.1,9592.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 75.92/76.15 9598[56:Spt:9596.1] || -> xuntil6(s40)*. % 75.92/76.15 9599[56:MRR:136.0,9598.0] || -> until5(s41)*. % 75.92/76.15 9600[56:MRR:924.0,9599.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.15 9606[55:SoR:9595.0,64.1] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.15 9608[55:SoR:9606.0,66.2] until5(s49) || m_main_v_state(s49,c_ready)* -> xuntil6(s49). % 75.92/76.15 9609[57:Spt:9600.2] || -> xuntil6(s41)*. % 75.92/76.15 9610[57:MRR:135.0,9609.0] || -> until5(s42)*. % 75.92/76.15 9611[57:MRR:7496.0,9610.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.15 9612[58:Spt:9611.1] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.15 9614[58:Res:9612.0,61.1] always3(s43) || -> . % 75.92/76.15 9615[58:SSi:9614.0,732.0] || -> . % 75.92/76.15 9616[58:Spt:9615.0,9611.1,9612.0] || m_main_v_state(s43,c_busy)*+ -> . % 75.92/76.15 9617[58:Spt:9615.0,9611.0,9611.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 75.92/76.15 9619[58:MRR:792.2,9616.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 75.92/76.15 9620[58:Res:53.1,9617.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 75.92/76.15 9622[59:Spt:9620.1] || -> xuntil6(s42)*. % 75.92/76.15 9623[59:MRR:134.0,9622.0] || -> until5(s43)*. % 75.92/76.15 9624[59:MRR:922.0,9623.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.15 9629[60:Spt:9624.2] || -> xuntil6(s43)*. % 75.92/76.15 9630[60:MRR:133.0,9629.0] || -> until5(s44)*. % 75.92/76.15 9631[60:MRR:7503.0,9630.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.15 9635[61:Spt:9631.1] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.15 9637[61:Res:9635.0,61.1] always3(s45) || -> . % 75.92/76.15 9638[61:SSi:9637.0,734.0] || -> . % 75.92/76.15 9639[61:Spt:9638.0,9631.1,9635.0] || m_main_v_state(s45,c_busy)*+ -> . % 75.92/76.15 9640[61:Spt:9638.0,9631.0,9631.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 75.92/76.15 9642[61:MRR:786.2,9639.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 75.92/76.15 9643[61:Res:53.1,9640.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 75.92/76.15 9645[62:Spt:9643.1] || -> xuntil6(s44)*. % 75.92/76.15 9646[62:MRR:132.0,9645.0] || -> until5(s45)*. % 75.92/76.15 9647[62:MRR:920.0,9646.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.15 9652[63:Spt:9647.2] || -> xuntil6(s45)*. % 75.92/76.15 9653[63:MRR:131.0,9652.0] || -> until5(s46)*. % 75.92/76.15 9654[63:MRR:7504.0,9653.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.15 9655[64:Spt:9654.1] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.15 9657[64:Res:9655.0,61.1] always3(s47) || -> . % 75.92/76.15 9658[64:SSi:9657.0,736.0] || -> . % 75.92/76.15 9659[64:Spt:9658.0,9654.1,9655.0] || m_main_v_state(s47,c_busy)*+ -> . % 75.92/76.15 9660[64:Spt:9658.0,9654.0,9654.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 75.92/76.15 9662[64:MRR:780.2,9659.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 75.92/76.15 9663[64:Res:53.1,9660.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 75.92/76.15 9665[65:Spt:9663.1] || -> xuntil6(s46)*. % 75.92/76.15 9666[65:MRR:130.0,9665.0] || -> until5(s47)*. % 75.92/76.15 9667[65:MRR:918.0,9666.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.15 9675[66:Spt:9667.2] || -> xuntil6(s47)*. % 75.92/76.15 9676[66:MRR:129.0,9675.0] || -> until5(s48)*. % 75.92/76.15 9677[66:MRR:7508.0,9676.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.15 9678[67:Spt:9677.1] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 9680[67:Res:9678.0,61.1] always3(s49) || -> . % 75.92/76.15 9681[67:SSi:9680.0,50.0,738.0] || -> . % 75.92/76.15 9682[67:Spt:9681.0,9677.1,9678.0] || m_main_v_state(s49,c_busy)*+ -> . % 75.92/76.15 9683[67:Spt:9681.0,9677.0,9677.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 75.92/76.15 9685[67:MRR:774.2,9682.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 75.92/76.15 9686[67:Res:53.1,9683.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 75.92/76.15 9691[68:Spt:9686.1] || -> xuntil6(s48)*. % 75.92/76.15 9692[68:MRR:128.0,9691.0] || -> until5(s49)*. % 75.92/76.15 9693[68:MRR:9608.0,9692.0] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.15 9694[68:Res:53.1,9693.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.15 9696[68:MRR:9694.0,9682.0] || -> xuntil6(s49)*. % 75.92/76.15 9697[68:MRR:9355.0,9696.0] || -> until2p7(s41)*. % 75.92/76.15 9698[68:MRR:239.0,9697.0] || -> until2p7(s42)* node4(s41). % 75.92/76.15 9699[69:Spt:9698.0] || -> until2p7(s42)*. % 75.92/76.15 9700[69:MRR:240.0,9699.0] || -> until2p7(s43)* node4(s42). % 75.92/76.15 9701[70:Spt:9700.0] || -> until2p7(s43)*. % 75.92/76.15 9702[70:MRR:241.0,9701.0] || -> until2p7(s44)* node4(s43). % 75.92/76.15 9703[71:Spt:9702.0] || -> until2p7(s44)*. % 75.92/76.15 9704[71:MRR:539.0,9703.0] || -> until2p7(s45)* node4(s44). % 75.92/76.15 9705[72:Spt:9704.0] || -> until2p7(s45)*. % 75.92/76.15 9706[72:MRR:544.0,9705.0] || -> until2p7(s46)* node4(s45). % 75.92/76.15 9707[73:Spt:9706.0] || -> until2p7(s46)*. % 75.92/76.15 9708[73:MRR:549.0,9707.0] || -> until2p7(s47)* node4(s46). % 75.92/76.15 9709[74:Spt:9708.0] || -> until2p7(s47)*. % 75.92/76.15 9710[74:MRR:554.0,9709.0] || -> until2p7(s48)* node4(s47). % 75.92/76.15 9711[75:Spt:9710.0] || -> until2p7(s48)*. % 75.92/76.15 9712[75:MRR:559.0,9711.0] || -> until2p7(s49)* node4(s48). % 75.92/76.15 9713[76:Spt:9712.0] || -> until2p7(s49)*. % 75.92/76.15 9714[76:MRR:194.0,9713.0] || -> node4(s49)*. % 75.92/76.15 9715[76:MRR:9606.0,9714.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.15 9719[76:Res:53.1,9715.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.15 9721[76:MRR:9719.0,9682.0] || -> . % 75.92/76.15 9722[76:Spt:9721.0,9712.0,9713.0] || until2p7(s49)*+ -> . % 75.92/76.15 9723[76:Spt:9721.0,9712.1] || -> node4(s48)*. % 75.92/76.15 9724[76:MRR:9685.0,9723.0] || m_main_v_state(s48,c_ready)*+ -> . % 75.92/76.15 9727[76:Res:53.1,9724.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.15 9730[76:Res:9727.0,61.1] always3(s48) || -> . % 75.92/76.15 9731[76:SSi:9730.0,737.0,9676.0,9691.0,9711.0,9723.0] || -> . % 75.92/76.15 9732[75:Spt:9731.0,9710.0,9711.0] || until2p7(s48)*+ -> . % 75.92/76.15 9733[75:Spt:9731.0,9710.1] || -> node4(s47)*. % 75.92/76.15 9735[75:MRR:777.0,9733.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 75.92/76.15 9749[75:Res:53.1,9735.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 75.92/76.15 9751[75:MRR:9749.0,9659.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.15 9753[75:Res:9751.0,61.1] always3(s48) || -> . % 75.92/76.15 9754[75:SSi:9753.0,737.0,9676.0,9691.0] || -> . % 75.92/76.15 9755[74:Spt:9754.0,9708.0,9709.0] || until2p7(s47)*+ -> . % 75.92/76.15 9756[74:Spt:9754.0,9708.1] || -> node4(s46)*. % 75.92/76.15 9757[74:MRR:9662.0,9756.0] || m_main_v_state(s46,c_ready)*+ -> . % 75.92/76.15 9761[74:Res:53.1,9757.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.15 9764[74:Res:9761.0,61.1] always3(s46) || -> . % 75.92/76.15 9765[74:SSi:9764.0,735.0,9653.0,9665.0,9707.0,9756.0] || -> . % 75.92/76.15 9766[73:Spt:9765.0,9706.0,9707.0] || until2p7(s46)*+ -> . % 75.92/76.15 9767[73:Spt:9765.0,9706.1] || -> node4(s45)*. % 75.92/76.15 9769[73:MRR:783.0,9767.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 75.92/76.15 9780[73:Res:53.1,9769.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 75.92/76.15 9782[73:MRR:9780.0,9639.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.15 9784[73:Res:9782.0,61.1] always3(s46) || -> . % 75.92/76.15 9785[73:SSi:9784.0,735.0,9653.0,9665.0] || -> . % 75.92/76.15 9786[72:Spt:9785.0,9704.0,9705.0] || until2p7(s45)*+ -> . % 75.92/76.15 9787[72:Spt:9785.0,9704.1] || -> node4(s44)*. % 75.92/76.15 9788[72:MRR:9642.0,9787.0] || m_main_v_state(s44,c_ready)*+ -> . % 75.92/76.15 9791[72:Res:53.1,9788.0] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.15 9794[72:Res:9791.0,61.1] always3(s44) || -> . % 75.92/76.15 9795[72:SSi:9794.0,733.0,9630.0,9645.0,9703.0,9787.0] || -> . % 75.92/76.15 9796[71:Spt:9795.0,9702.0,9703.0] || until2p7(s44)*+ -> . % 75.92/76.15 9797[71:Spt:9795.0,9702.1] || -> node4(s43)*. % 75.92/76.15 9799[71:MRR:789.0,9797.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 75.92/76.15 9811[71:Res:53.1,9799.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 75.92/76.15 9813[71:MRR:9811.0,9616.0] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.15 9815[71:Res:9813.0,61.1] always3(s44) || -> . % 75.92/76.16 9816[71:SSi:9815.0,733.0,9630.0,9645.0] || -> . % 75.92/76.16 9817[70:Spt:9816.0,9700.0,9701.0] || until2p7(s43)*+ -> . % 75.92/76.16 9818[70:Spt:9816.0,9700.1] || -> node4(s42)*. % 75.92/76.16 9819[70:MRR:9619.0,9818.0] || m_main_v_state(s42,c_ready)*+ -> . % 75.92/76.16 9822[70:Res:53.1,9819.0] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.16 9825[70:Res:9822.0,61.1] always3(s42) || -> . % 75.92/76.16 9826[70:SSi:9825.0,731.0,9610.0,9622.0,9699.0,9818.0] || -> . % 75.92/76.16 9827[69:Spt:9826.0,9698.0,9699.0] || until2p7(s42)*+ -> . % 75.92/76.16 9828[69:Spt:9826.0,9698.1] || -> node4(s41)*. % 75.92/76.16 9830[69:MRR:795.0,9828.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 75.92/76.16 9842[69:Res:53.1,9830.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 75.92/76.16 9844[69:MRR:9842.0,9591.0] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.16 9849[69:Res:9844.0,61.1] always3(s42) || -> . % 75.92/76.16 9850[69:SSi:9849.0,731.0,9610.0,9622.0] || -> . % 75.92/76.16 9851[68:Spt:9850.0,9686.1,9691.0] || xuntil6(s48)* -> . % 75.92/76.16 9852[68:Spt:9850.0,9686.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.16 9855[68:Res:9852.0,61.1] always3(s48) || -> . % 75.92/76.16 9856[68:SSi:9855.0,737.0,9676.0] || -> . % 75.92/76.16 9857[66:Spt:9856.0,9667.2,9675.0] || xuntil6(s47)*+ -> . % 75.92/76.16 9858[66:Spt:9856.0,9667.0,9667.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 75.92/76.16 9859[66:Res:53.1,9858.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 75.92/76.16 9861[66:MRR:9859.0,9659.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.16 9863[66:Res:9861.0,61.1] always3(s48) || -> . % 75.92/76.16 9864[66:SSi:9863.0,737.0] || -> . % 75.92/76.16 9865[65:Spt:9864.0,9663.1,9665.0] || xuntil6(s46)* -> . % 75.92/76.16 9866[65:Spt:9864.0,9663.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.16 9869[65:Res:9866.0,61.1] always3(s46) || -> . % 75.92/76.16 9870[65:SSi:9869.0,735.0,9653.0] || -> . % 75.92/76.16 9871[63:Spt:9870.0,9647.2,9652.0] || xuntil6(s45)*+ -> . % 75.92/76.16 9872[63:Spt:9870.0,9647.0,9647.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 75.92/76.16 9873[63:Res:53.1,9872.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 75.92/76.16 9875[63:MRR:9873.0,9639.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.16 9878[63:Res:9875.0,61.1] always3(s46) || -> . % 75.92/76.16 9879[63:SSi:9878.0,735.0] || -> . % 75.92/76.16 9880[62:Spt:9879.0,9643.1,9645.0] || xuntil6(s44)* -> . % 75.92/76.16 9881[62:Spt:9879.0,9643.0] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.16 9884[62:Res:9881.0,61.1] always3(s44) || -> . % 75.92/76.16 9885[62:SSi:9884.0,733.0,9630.0] || -> . % 75.92/76.16 9886[60:Spt:9885.0,9624.2,9629.0] || xuntil6(s43)*+ -> . % 75.92/76.16 9887[60:Spt:9885.0,9624.0,9624.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 75.92/76.16 9888[60:Res:53.1,9887.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 75.92/76.16 9890[60:MRR:9888.0,9616.0] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.16 9892[60:Res:9890.0,61.1] always3(s44) || -> . % 75.92/76.16 9893[60:SSi:9892.0,733.0] || -> . % 75.92/76.16 9894[59:Spt:9893.0,9620.1,9622.0] || xuntil6(s42)* -> . % 75.92/76.16 9895[59:Spt:9893.0,9620.0] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.16 9898[59:Res:9895.0,61.1] always3(s42) || -> . % 75.92/76.16 9899[59:SSi:9898.0,731.0,9610.0] || -> . % 75.92/76.16 9900[57:Spt:9899.0,9600.2,9609.0] || xuntil6(s41)*+ -> . % 75.92/76.16 9901[57:Spt:9899.0,9600.0,9600.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 75.92/76.16 9902[57:Res:53.1,9901.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 75.92/76.16 9904[57:MRR:9902.0,9591.0] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.16 9906[57:Res:9904.0,61.1] always3(s42) || -> . % 75.92/76.16 9907[57:SSi:9906.0,731.0] || -> . % 75.92/76.16 9908[56:Spt:9907.0,9596.1,9598.0] || xuntil6(s40)* -> . % 75.92/76.16 9909[56:Spt:9907.0,9596.0] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.16 9912[56:Res:9909.0,61.1] always3(s40) || -> . % 75.92/76.16 9913[56:SSi:9912.0,729.0,9585.0] || -> . % 75.92/76.16 9914[54:Spt:9913.0,9582.2,9584.0] || xuntil6(s39)*+ -> . % 75.92/76.16 9915[54:Spt:9913.0,9582.0,9582.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 75.92/76.16 9916[54:Res:53.1,9915.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 75.92/76.16 9918[54:MRR:9916.0,9571.0] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.16 9920[54:Res:9918.0,61.1] always3(s40) || -> . % 75.92/76.16 9921[54:SSi:9920.0,729.0] || -> . % 75.92/76.16 9922[53:Spt:9921.0,9575.1,9580.0] || xuntil6(s38)* -> . % 75.92/76.16 9923[53:Spt:9921.0,9575.0] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.16 9926[53:Res:9923.0,61.1] always3(s38) || -> . % 75.92/76.16 9927[53:SSi:9926.0,727.0,9565.0] || -> . % 75.92/76.16 9928[51:Spt:9927.0,9556.2,9564.0] || xuntil6(s37)*+ -> . % 75.92/76.16 9929[51:Spt:9927.0,9556.0,9556.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 75.92/76.16 9930[51:Res:53.1,9929.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 75.92/76.16 9932[51:MRR:9930.0,9548.0] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.16 9935[51:Res:9932.0,61.1] always3(s38) || -> . % 75.92/76.16 9936[51:SSi:9935.0,727.0] || -> . % 75.92/76.16 9937[50:Spt:9936.0,9552.1,9554.0] || xuntil6(s36)* -> . % 75.92/76.16 9938[50:Spt:9936.0,9552.0] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.16 9941[50:Res:9938.0,61.1] always3(s36) || -> . % 75.92/76.16 9942[50:SSi:9941.0,725.0,9542.0] || -> . % 75.92/76.16 9943[48:Spt:9942.0,9536.2,9541.0] || xuntil6(s35)*+ -> . % 75.92/76.16 9944[48:Spt:9942.0,9536.0,9536.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 75.92/76.16 9945[48:Res:53.1,9944.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 75.92/76.16 9947[48:MRR:9945.0,9528.0] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.16 9949[48:Res:9947.0,61.1] always3(s36) || -> . % 75.92/76.16 9950[48:SSi:9949.0,725.0] || -> . % 75.92/76.16 9951[47:Spt:9950.0,9532.1,9534.0] || xuntil6(s34)* -> . % 75.92/76.16 9952[47:Spt:9950.0,9532.0] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.16 9955[47:Res:9952.0,61.1] always3(s34) || -> . % 75.92/76.16 9956[47:SSi:9955.0,723.0,9522.0] || -> . % 75.92/76.16 9957[45:Spt:9956.0,9519.2,9521.0] || xuntil6(s33)*+ -> . % 75.92/76.16 9958[45:Spt:9956.0,9519.0,9519.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 75.92/76.16 9959[45:Res:53.1,9958.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 75.92/76.16 9961[45:MRR:9959.0,9508.0] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.16 9963[45:Res:9961.0,61.1] always3(s34) || -> . % 75.92/76.16 9964[45:SSi:9963.0,723.0] || -> . % 75.92/76.16 9965[44:Spt:9964.0,9512.1,9517.0] || xuntil6(s32)* -> . % 75.92/76.16 9966[44:Spt:9964.0,9512.0] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.16 9969[44:Res:9966.0,61.1] always3(s32) || -> . % 75.92/76.16 9970[44:SSi:9969.0,721.0,9502.0] || -> . % 75.92/76.16 9971[42:Spt:9970.0,9497.2,9501.0] || xuntil6(s31)*+ -> . % 75.92/76.16 9972[42:Spt:9970.0,9497.0,9497.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 75.92/76.16 9973[42:Res:53.1,9972.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 75.92/76.16 9975[43:Spt:9973.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.16 9977[43:Res:9975.0,61.1] always3(s31) || -> . % 75.92/76.16 9978[43:SSi:9977.0,720.0,9496.0] || -> . % 75.92/76.16 9979[43:Spt:9978.0,9973.0,9975.0] || m_main_v_state(s31,c_busy)* -> . % 75.92/76.16 9980[43:Spt:9978.0,9973.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.16 9984[43:Res:9980.0,61.1] always3(s32) || -> . % 75.92/76.16 9985[43:SSi:9984.0,721.0] || -> . % 75.92/76.16 9986[41:Spt:9985.0,9494.2,9495.0] || xuntil6(s30)*+ -> . % 75.92/76.16 9987[41:Spt:9985.0,9494.0,9494.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.16 9988[41:Res:53.1,9987.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.16 9990[42:Spt:9988.0] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.16 9992[42:Res:9990.0,61.1] always3(s30) || -> . % 75.92/76.16 9993[42:SSi:9992.0,719.0,9493.0] || -> . % 75.92/76.16 9994[42:Spt:9993.0,9988.0,9990.0] || m_main_v_state(s30,c_busy)* -> . % 75.92/76.16 9995[42:Spt:9993.0,9988.1] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.16 9999[42:Res:9995.0,61.1] always3(s31) || -> . % 75.92/76.16 10000[42:SSi:9999.0,720.0] || -> . % 75.92/76.16 10001[40:Spt:10000.0,9488.2,9492.0] || xuntil6(s29)*+ -> . % 75.92/76.16 10002[40:Spt:10000.0,9488.0,9488.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 75.92/76.16 10003[40:Res:53.1,10002.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 75.92/76.16 10005[41:Spt:10003.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.16 10007[41:Res:10005.0,61.1] always3(s29) || -> . % 75.92/76.16 10008[41:SSi:10007.0,718.0,9487.0] || -> . % 75.92/76.16 10009[41:Spt:10008.0,10003.0,10005.0] || m_main_v_state(s29,c_busy)* -> . % 75.92/76.16 10010[41:Spt:10008.0,10003.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.16 10014[41:Res:10010.0,61.1] always3(s30) || -> . % 75.92/76.16 10015[41:SSi:10014.0,719.0] || -> . % 75.92/76.16 10016[39:Spt:10015.0,9485.2,9486.0] || xuntil6(s28)*+ -> . % 75.92/76.16 10017[39:Spt:10015.0,9485.0,9485.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.16 10018[39:Res:53.1,10017.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.16 10020[40:Spt:10018.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.16 10022[40:Res:10020.0,61.1] always3(s28) || -> . % 75.92/76.16 10023[40:SSi:10022.0,717.0,9484.0] || -> . % 75.92/76.16 10024[40:Spt:10023.0,10018.0,10020.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.16 10025[40:Spt:10023.0,10018.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.16 10029[40:Res:10025.0,61.1] always3(s29) || -> . % 75.92/76.16 10030[40:SSi:10029.0,718.0] || -> . % 75.92/76.16 10031[38:Spt:10030.0,9479.2,9483.0] || xuntil6(s27)*+ -> . % 75.92/76.16 10032[38:Spt:10030.0,9479.0,9479.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.16 10033[38:Res:53.1,10032.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.16 10035[39:Spt:10033.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.16 10037[39:Res:10035.0,61.1] always3(s27) || -> . % 75.92/76.16 10038[39:SSi:10037.0,716.0,9478.0] || -> . % 75.92/76.16 10039[39:Spt:10038.0,10033.0,10035.0] || m_main_v_state(s27,c_busy)* -> . % 75.92/76.16 10040[39:Spt:10038.0,10033.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.16 10044[39:Res:10040.0,61.1] always3(s28) || -> . % 75.92/76.16 10045[39:SSi:10044.0,717.0] || -> . % 75.92/76.16 10046[37:Spt:10045.0,9476.2,9477.0] || xuntil6(s26)*+ -> . % 75.92/76.16 10047[37:Spt:10045.0,9476.0,9476.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.16 10048[37:Res:53.1,10047.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.16 10050[38:Spt:10048.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.16 10052[38:Res:10050.0,61.1] always3(s27) || -> . % 75.92/76.16 10053[38:SSi:10052.0,716.0] || -> . % 75.92/76.16 10054[38:Spt:10053.0,10048.1,10050.0] || m_main_v_state(s27,c_busy)* -> . % 75.92/76.16 10055[38:Spt:10053.0,10048.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.16 10058[38:Res:10055.0,61.1] always3(s26) || -> . % 75.92/76.16 10059[38:SSi:10058.0,715.0,9475.0] || -> . % 75.92/76.16 10060[36:Spt:10059.0,9470.2,9474.0] || xuntil6(s25)*+ -> . % 75.92/76.16 10061[36:Spt:10059.0,9470.0,9470.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.16 10062[36:Res:53.1,10061.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.16 10067[37:Spt:10062.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.16 10069[37:Res:10067.0,61.1] always3(s25) || -> . % 75.92/76.16 10070[37:SSi:10069.0,714.0,9469.0] || -> . % 75.92/76.16 10071[37:Spt:10070.0,10062.0,10067.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.16 10072[37:Spt:10070.0,10062.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.16 10076[37:Res:10072.0,61.1] always3(s26) || -> . % 75.92/76.16 10077[37:SSi:10076.0,715.0] || -> . % 75.92/76.16 10078[35:Spt:10077.0,9467.2,9468.0] || xuntil6(s24)*+ -> . % 75.92/76.16 10079[35:Spt:10077.0,9467.0,9467.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.16 10080[35:Res:53.1,10079.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.16 10082[36:Spt:10080.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.16 10084[36:Res:10082.0,61.1] always3(s25) || -> . % 75.92/76.16 10085[36:SSi:10084.0,714.0] || -> . % 75.92/76.16 10086[36:Spt:10085.0,10080.1,10082.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.16 10087[36:Spt:10085.0,10080.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.16 10090[36:Res:10087.0,61.1] always3(s24) || -> . % 75.92/76.16 10091[36:SSi:10090.0,713.0,9466.0] || -> . % 75.92/76.16 10092[34:Spt:10091.0,9461.2,9465.0] || xuntil6(s23)*+ -> . % 75.92/76.16 10093[34:Spt:10091.0,9461.0,9461.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.16 10094[34:Res:53.1,10093.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.16 10096[35:Spt:10094.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.16 10098[35:Res:10096.0,61.1] always3(s24) || -> . % 75.92/76.16 10099[35:SSi:10098.0,713.0] || -> . % 75.92/76.16 10100[35:Spt:10099.0,10094.1,10096.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.16 10101[35:Spt:10099.0,10094.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.16 10104[35:Res:10101.0,61.1] always3(s23) || -> . % 75.92/76.16 10105[35:SSi:10104.0,712.0,9460.0] || -> . % 75.92/76.16 10106[33:Spt:10105.0,9458.2,9459.0] || xuntil6(s22)*+ -> . % 75.92/76.16 10107[33:Spt:10105.0,9458.0,9458.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.16 10108[33:Res:53.1,10107.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.16 10113[34:Spt:10108.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.16 10115[34:Res:10113.0,61.1] always3(s22) || -> . % 75.92/76.16 10116[34:SSi:10115.0,711.0,9457.0] || -> . % 75.92/76.16 10117[34:Spt:10116.0,10108.0,10113.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.16 10118[34:Spt:10116.0,10108.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.16 10122[34:Res:10118.0,61.1] always3(s23) || -> . % 75.92/76.16 10123[34:SSi:10122.0,712.0] || -> . % 75.92/76.16 10124[32:Spt:10123.0,9452.2,9456.0] || xuntil6(s21)*+ -> . % 75.92/76.16 10125[32:Spt:10123.0,9452.0,9452.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.16 10126[32:Res:53.1,10125.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.16 10128[33:Spt:10126.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.16 10130[33:Res:10128.0,61.1] always3(s22) || -> . % 75.92/76.16 10131[33:SSi:10130.0,711.0] || -> . % 75.92/76.16 10132[33:Spt:10131.0,10126.1,10128.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.16 10133[33:Spt:10131.0,10126.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.16 10136[33:Res:10133.0,61.1] always3(s21) || -> . % 75.92/76.16 10137[33:SSi:10136.0,710.0,9451.0] || -> . % 75.92/76.16 10138[31:Spt:10137.0,9449.2,9450.0] || xuntil6(s20)*+ -> . % 75.92/76.16 10139[31:Spt:10137.0,9449.0,9449.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.16 10140[31:Res:53.1,10139.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.16 10142[32:Spt:10140.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.16 10144[32:Res:10142.0,61.1] always3(s21) || -> . % 75.92/76.16 10145[32:SSi:10144.0,710.0] || -> . % 75.92/76.16 10146[32:Spt:10145.0,10140.1,10142.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.16 10147[32:Spt:10145.0,10140.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.16 10150[32:Res:10147.0,61.1] always3(s20) || -> . % 75.92/76.16 10151[32:SSi:10150.0,709.0,9448.0] || -> . % 75.92/76.16 10152[30:Spt:10151.0,9443.2,9447.0] || xuntil6(s19)*+ -> . % 75.92/76.16 10153[30:Spt:10151.0,9443.0,9443.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.16 10154[30:Res:53.1,10153.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.16 10159[31:Spt:10154.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.16 10161[31:Res:10159.0,61.1] always3(s19) || -> . % 75.92/76.16 10162[31:SSi:10161.0,708.0,9442.0] || -> . % 75.92/76.16 10163[31:Spt:10162.0,10154.0,10159.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.16 10164[31:Spt:10162.0,10154.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.16 10168[31:Res:10164.0,61.1] always3(s20) || -> . % 75.92/76.16 10169[31:SSi:10168.0,709.0] || -> . % 75.92/76.16 10170[29:Spt:10169.0,9440.2,9441.0] || xuntil6(s18)*+ -> . % 75.92/76.16 10171[29:Spt:10169.0,9440.0,9440.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.16 10172[29:Res:53.1,10171.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.16 10174[30:Spt:10172.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.16 10176[30:Res:10174.0,61.1] always3(s19) || -> . % 75.92/76.16 10177[30:SSi:10176.0,708.0] || -> . % 75.92/76.16 10178[30:Spt:10177.0,10172.1,10174.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.16 10179[30:Spt:10177.0,10172.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.16 10182[30:Res:10179.0,61.1] always3(s18) || -> . % 75.92/76.16 10183[30:SSi:10182.0,707.0,9439.0] || -> . % 75.92/76.16 10184[28:Spt:10183.0,9434.2,9438.0] || xuntil6(s17)*+ -> . % 75.92/76.16 10185[28:Spt:10183.0,9434.0,9434.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.16 10186[28:Res:53.1,10185.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.16 10188[29:Spt:10186.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.16 10190[29:Res:10188.0,61.1] always3(s18) || -> . % 75.92/76.16 10191[29:SSi:10190.0,707.0] || -> . % 75.92/76.16 10192[29:Spt:10191.0,10186.1,10188.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.16 10193[29:Spt:10191.0,10186.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.16 10196[29:Res:10193.0,61.1] always3(s17) || -> . % 75.92/76.16 10197[29:SSi:10196.0,706.0,9433.0] || -> . % 75.92/76.16 10198[27:Spt:10197.0,9431.2,9432.0] || xuntil6(s16)*+ -> . % 75.92/76.16 10199[27:Spt:10197.0,9431.0,9431.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.16 10200[27:Res:53.1,10199.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.16 10205[28:Spt:10200.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.16 10207[28:Res:10205.0,61.1] always3(s16) || -> . % 75.92/76.16 10208[28:SSi:10207.0,705.0,9430.0] || -> . % 75.92/76.16 10209[28:Spt:10208.0,10200.0,10205.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.16 10210[28:Spt:10208.0,10200.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.16 10214[28:Res:10210.0,61.1] always3(s17) || -> . % 75.92/76.16 10215[28:SSi:10214.0,706.0] || -> . % 75.92/76.16 10216[26:Spt:10215.0,9425.2,9429.0] || xuntil6(s15)*+ -> . % 75.92/76.16 10217[26:Spt:10215.0,9425.0,9425.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.16 10218[26:Res:53.1,10217.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.16 10220[27:Spt:10218.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.16 10222[27:Res:10220.0,61.1] always3(s16) || -> . % 75.92/76.16 10223[27:SSi:10222.0,705.0] || -> . % 75.92/76.16 10224[27:Spt:10223.0,10218.1,10220.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.16 10225[27:Spt:10223.0,10218.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.16 10228[27:Res:10225.0,61.1] always3(s15) || -> . % 75.92/76.16 10229[27:SSi:10228.0,704.0,9424.0] || -> . % 75.92/76.16 10230[25:Spt:10229.0,9422.2,9423.0] || xuntil6(s14)*+ -> . % 75.92/76.16 10231[25:Spt:10229.0,9422.0,9422.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.16 10232[25:Res:53.1,10231.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.16 10234[26:Spt:10232.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.16 10236[26:Res:10234.0,61.1] always3(s15) || -> . % 75.92/76.16 10237[26:SSi:10236.0,704.0] || -> . % 75.92/76.16 10238[26:Spt:10237.0,10232.1,10234.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.16 10239[26:Spt:10237.0,10232.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.16 10242[26:Res:10239.0,61.1] always3(s14) || -> . % 75.92/76.16 10243[26:SSi:10242.0,703.0,9421.0] || -> . % 75.92/76.16 10244[24:Spt:10243.0,9416.2,9420.0] || xuntil6(s13)*+ -> . % 75.92/76.16 10245[24:Spt:10243.0,9416.0,9416.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.16 10246[24:Res:53.1,10245.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.16 10251[25:Spt:10246.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.16 10253[25:Res:10251.0,61.1] always3(s13) || -> . % 75.92/76.16 10254[25:SSi:10253.0,702.0,9415.0] || -> . % 75.92/76.16 10255[25:Spt:10254.0,10246.0,10251.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.16 10256[25:Spt:10254.0,10246.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.16 10260[25:Res:10256.0,61.1] always3(s14) || -> . % 75.92/76.16 10261[25:SSi:10260.0,703.0] || -> . % 75.92/76.16 10262[23:Spt:10261.0,9413.2,9414.0] || xuntil6(s12)*+ -> . % 75.92/76.16 10263[23:Spt:10261.0,9413.0,9413.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.16 10264[23:Res:53.1,10263.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.16 10266[24:Spt:10264.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.16 10268[24:Res:10266.0,61.1] always3(s13) || -> . % 75.92/76.16 10269[24:SSi:10268.0,702.0] || -> . % 75.92/76.16 10270[24:Spt:10269.0,10264.1,10266.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.16 10271[24:Spt:10269.0,10264.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.16 10274[24:Res:10271.0,61.1] always3(s12) || -> . % 75.92/76.16 10275[24:SSi:10274.0,701.0,9412.0] || -> . % 75.92/76.16 10276[22:Spt:10275.0,9407.2,9411.0] || xuntil6(s11)*+ -> . % 75.92/76.16 10277[22:Spt:10275.0,9407.0,9407.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.16 10278[22:Res:53.1,10277.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.16 10280[23:Spt:10278.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.16 10282[23:Res:10280.0,61.1] always3(s12) || -> . % 75.92/76.16 10283[23:SSi:10282.0,701.0] || -> . % 75.92/76.16 10284[23:Spt:10283.0,10278.1,10280.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.16 10285[23:Spt:10283.0,10278.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.16 10288[23:Res:10285.0,61.1] always3(s11) || -> . % 75.92/76.16 10289[23:SSi:10288.0,700.0,9406.0] || -> . % 75.92/76.16 10290[21:Spt:10289.0,9404.2,9405.0] || xuntil6(s10)*+ -> . % 75.92/76.16 10291[21:Spt:10289.0,9404.0,9404.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.16 10292[21:Res:53.1,10291.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.16 10297[22:Spt:10292.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.16 10299[22:Res:10297.0,61.1] always3(s10) || -> . % 75.92/76.16 10300[22:SSi:10299.0,699.0,9403.0] || -> . % 75.92/76.16 10301[22:Spt:10300.0,10292.0,10297.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.16 10302[22:Spt:10300.0,10292.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.16 10306[22:Res:10302.0,61.1] always3(s11) || -> . % 75.92/76.16 10307[22:SSi:10306.0,700.0] || -> . % 75.92/76.16 10308[20:Spt:10307.0,9398.2,9402.0] || xuntil6(s9)*+ -> . % 75.92/76.16 10309[20:Spt:10307.0,9398.0,9398.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.16 10310[20:Res:53.1,10309.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.16 10312[21:Spt:10310.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.16 10314[21:Res:10312.0,61.1] always3(s10) || -> . % 75.92/76.16 10315[21:SSi:10314.0,699.0] || -> . % 75.92/76.16 10316[21:Spt:10315.0,10310.1,10312.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.16 10317[21:Spt:10315.0,10310.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.16 10320[21:Res:10317.0,61.1] always3(s9) || -> . % 75.92/76.16 10321[21:SSi:10320.0,698.0,9397.0] || -> . % 75.92/76.16 10322[19:Spt:10321.0,9395.2,9396.0] || xuntil6(s8)*+ -> . % 75.92/76.16 10323[19:Spt:10321.0,9395.0,9395.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.16 10324[19:Res:53.1,10323.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.16 10326[20:Spt:10324.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.16 10328[20:Res:10326.0,61.1] always3(s9) || -> . % 75.92/76.16 10329[20:SSi:10328.0,698.0] || -> . % 75.92/76.16 10330[20:Spt:10329.0,10324.1,10326.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.16 10331[20:Spt:10329.0,10324.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.16 10334[20:Res:10331.0,61.1] always3(s8) || -> . % 75.92/76.16 10335[20:SSi:10334.0,697.0,9394.0] || -> . % 75.92/76.16 10336[18:Spt:10335.0,9389.2,9393.0] || xuntil6(s7)*+ -> . % 75.92/76.16 10337[18:Spt:10335.0,9389.0,9389.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.16 10338[18:Res:53.1,10337.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.16 10343[19:Spt:10338.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.16 10345[19:Res:10343.0,61.1] always3(s7) || -> . % 75.92/76.16 10346[19:SSi:10345.0,696.0,9388.0] || -> . % 75.92/76.16 10347[19:Spt:10346.0,10338.0,10343.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.16 10348[19:Spt:10346.0,10338.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.16 10352[19:Res:10348.0,61.1] always3(s8) || -> . % 75.92/76.16 10353[19:SSi:10352.0,697.0] || -> . % 75.92/76.16 10354[17:Spt:10353.0,9386.2,9387.0] || xuntil6(s6)*+ -> . % 75.92/76.16 10355[17:Spt:10353.0,9386.0,9386.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.16 10356[17:Res:53.1,10355.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.16 10358[18:Spt:10356.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.16 10360[18:Res:10358.0,61.1] always3(s7) || -> . % 75.92/76.16 10361[18:SSi:10360.0,696.0] || -> . % 75.92/76.16 10362[18:Spt:10361.0,10356.1,10358.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.16 10363[18:Spt:10361.0,10356.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.16 10366[18:Res:10363.0,61.1] always3(s6) || -> . % 75.92/76.16 10367[18:SSi:10366.0,695.0,9385.0] || -> . % 75.92/76.16 10368[16:Spt:10367.0,9380.2,9384.0] || xuntil6(s5)*+ -> . % 75.92/76.16 10369[16:Spt:10367.0,9380.0,9380.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.16 10370[16:Res:53.1,10369.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.16 10372[17:Spt:10370.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.16 10374[17:Res:10372.0,61.1] always3(s6) || -> . % 75.92/76.16 10375[17:SSi:10374.0,695.0] || -> . % 75.92/76.16 10376[17:Spt:10375.0,10370.1,10372.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.16 10377[17:Spt:10375.0,10370.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.16 10380[17:Res:10377.0,61.1] always3(s5) || -> . % 75.92/76.16 10381[17:SSi:10380.0,694.0,9379.0] || -> . % 75.92/76.16 10382[15:Spt:10381.0,9377.2,9378.0] || xuntil6(s4)*+ -> . % 75.92/76.16 10383[15:Spt:10381.0,9377.0,9377.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.16 10384[15:Res:53.1,10383.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.16 10389[16:Spt:10384.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.16 10391[16:Res:10389.0,61.1] always3(s4) || -> . % 75.92/76.16 10392[16:SSi:10391.0,693.0,9376.0] || -> . % 75.92/76.16 10393[16:Spt:10392.0,10384.0,10389.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.16 10394[16:Spt:10392.0,10384.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.16 10398[16:Res:10394.0,61.1] always3(s5) || -> . % 75.92/76.16 10399[16:SSi:10398.0,694.0] || -> . % 75.92/76.16 10400[14:Spt:10399.0,9371.2,9375.0] || xuntil6(s3)*+ -> . % 75.92/76.16 10401[14:Spt:10399.0,9371.0,9371.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.16 10402[14:Res:53.1,10401.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.16 10404[15:Spt:10402.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.16 10406[15:Res:10404.0,61.1] always3(s4) || -> . % 75.92/76.16 10407[15:SSi:10406.0,693.0] || -> . % 75.92/76.16 10408[15:Spt:10407.0,10402.1,10404.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.16 10409[15:Spt:10407.0,10402.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.16 10412[15:Res:10409.0,61.1] always3(s3) || -> . % 75.92/76.16 10413[15:SSi:10412.0,692.0,9370.0] || -> . % 75.92/76.16 10414[13:Spt:10413.0,9368.2,9369.0] || xuntil6(s2)*+ -> . % 75.92/76.16 10415[13:Spt:10413.0,9368.0,9368.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.16 10416[13:Res:53.1,10415.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.16 10418[14:Spt:10416.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.16 10420[14:Res:10418.0,61.1] always3(s3) || -> . % 75.92/76.16 10421[14:SSi:10420.0,692.0] || -> . % 75.92/76.16 10422[14:Spt:10421.0,10416.1,10418.0] || m_main_v_state(s3,c_busy)* -> . % 75.92/76.16 10423[14:Spt:10421.0,10416.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.16 10426[14:Res:10423.0,61.1] always3(s2) || -> . % 75.92/76.16 10427[14:SSi:10426.0,691.0,9367.0] || -> . % 75.92/76.16 10428[12:Spt:10427.0,9359.2,9366.0] || xuntil6(s1)*+ -> . % 75.92/76.16 10429[12:Spt:10427.0,9359.0,9359.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.16 10430[12:Res:53.1,10429.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.16 10435[13:Spt:10430.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.16 10437[13:Res:10435.0,61.1] always3(s1) || -> . % 75.92/76.16 10438[13:SSi:10437.0,690.0,9358.0] || -> . % 75.92/76.16 10439[13:Spt:10438.0,10430.0,10435.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.16 10440[13:Spt:10438.0,10430.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.16 10445[13:Res:10440.0,61.1] always3(s2) || -> . % 75.92/76.16 10446[13:SSi:10445.0,691.0] || -> . % 75.92/76.16 10447[11:Spt:10446.0,74.0,9357.0] || xuntil6(s0)*+ -> . % 75.92/76.16 10448[11:Spt:10446.0,74.1] || -> node4(s0)*. % 75.92/76.16 10449[11:MRR:758.1,10447.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.16 10451[11:Res:10449.0,61.1] always3(s1) || -> . % 75.92/76.16 10452[11:SSi:10451.0,690.0] || -> . % 75.92/76.16 10453[10:Spt:10452.0,9347.0,9351.0] || trans(s49,s41)*+ -> . % 75.92/76.16 10454[10:Spt:10452.0,9347.1,9347.2,9347.3,9347.4,9347.5,9347.6,9347.7,9347.8,9347.9,9347.10,9347.11,9347.12,9347.13,9347.14,9347.15,9347.16,9347.17,9347.18,9347.19,9347.20,9347.21,9347.22,9347.23,9347.24,9347.25,9347.26,9347.27,9347.28,9347.29,9347.30,9347.31,9347.32,9347.33,9347.34,9347.35,9347.36,9347.37,9347.38,9347.39,9347.40,9347.41] || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.16 10455[10:MRR:9349.0,10453.0] || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.16 10457[10:MRR:9350.1,10453.0] xuntil6(s49) || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.16 10458[11:Spt:10454.0] || -> trans(s49,s40)*. % 75.92/76.16 10459[11:Res:10458.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s40)*. % 75.92/76.16 10461[11:Res:10458.0,60.0] || -> node2(s49,s40)*. % 75.92/76.16 10462[11:SSi:10459.1,50.0,738.0] xuntil6(s49) || -> until2p7(s40)*. % 75.92/76.16 10463[11:Res:10461.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)*. % 75.92/76.16 10464[12:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.16 10465[12:MRR:176.0,10464.0] || -> until5(s1)*. % 75.92/76.16 10466[12:MRR:7473.0,10465.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.16 10470[13:Spt:10466.2] || -> xuntil6(s1)*. % 75.92/76.16 10471[13:MRR:175.0,10470.0] || -> until5(s2)*. % 75.92/76.16 10472[13:MRR:7472.0,10471.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.16 10473[14:Spt:10472.2] || -> xuntil6(s2)*. % 75.92/76.16 10474[14:MRR:174.0,10473.0] || -> until5(s3)*. % 75.92/76.16 10475[14:MRR:7465.0,10474.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.16 10476[15:Spt:10475.2] || -> xuntil6(s3)*. % 75.92/76.16 10477[15:MRR:173.0,10476.0] || -> until5(s4)*. % 75.92/76.16 10478[15:MRR:7461.0,10477.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.16 10479[16:Spt:10478.2] || -> xuntil6(s4)*. % 75.92/76.16 10480[16:MRR:172.0,10479.0] || -> until5(s5)*. % 75.92/76.16 10481[16:MRR:7457.0,10480.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.16 10485[17:Spt:10481.2] || -> xuntil6(s5)*. % 75.92/76.16 10486[17:MRR:171.0,10485.0] || -> until5(s6)*. % 75.92/76.16 10487[17:MRR:7453.0,10486.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.16 10488[18:Spt:10487.2] || -> xuntil6(s6)*. % 75.92/76.16 10489[18:MRR:170.0,10488.0] || -> until5(s7)*. % 75.92/76.16 10490[18:MRR:7452.0,10489.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.16 10494[19:Spt:10490.2] || -> xuntil6(s7)*. % 75.92/76.16 10495[19:MRR:169.0,10494.0] || -> until5(s8)*. % 75.92/76.16 10496[19:MRR:7445.0,10495.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.16 10497[20:Spt:10496.2] || -> xuntil6(s8)*. % 75.92/76.16 10498[20:MRR:168.0,10497.0] || -> until5(s9)*. % 75.92/76.16 10499[20:MRR:7441.0,10498.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.16 10503[21:Spt:10499.2] || -> xuntil6(s9)*. % 75.92/76.16 10504[21:MRR:167.0,10503.0] || -> until5(s10)*. % 75.92/76.16 10505[21:MRR:7437.0,10504.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.16 10506[22:Spt:10505.2] || -> xuntil6(s10)*. % 75.92/76.16 10507[22:MRR:166.0,10506.0] || -> until5(s11)*. % 75.92/76.16 10508[22:MRR:7433.0,10507.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.16 10512[23:Spt:10508.2] || -> xuntil6(s11)*. % 75.92/76.16 10513[23:MRR:165.0,10512.0] || -> until5(s12)*. % 75.92/76.16 10514[23:MRR:7432.0,10513.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.16 10515[24:Spt:10514.2] || -> xuntil6(s12)*. % 75.92/76.16 10516[24:MRR:164.0,10515.0] || -> until5(s13)*. % 75.92/76.16 10517[24:MRR:7425.0,10516.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.16 10521[25:Spt:10517.2] || -> xuntil6(s13)*. % 75.92/76.16 10522[25:MRR:163.0,10521.0] || -> until5(s14)*. % 75.92/76.16 10523[25:MRR:7421.0,10522.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.16 10524[26:Spt:10523.2] || -> xuntil6(s14)*. % 75.92/76.16 10525[26:MRR:162.0,10524.0] || -> until5(s15)*. % 75.92/76.16 10526[26:MRR:7417.0,10525.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.16 10530[27:Spt:10526.2] || -> xuntil6(s15)*. % 75.92/76.16 10531[27:MRR:161.0,10530.0] || -> until5(s16)*. % 75.92/76.16 10532[27:MRR:7413.0,10531.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.16 10533[28:Spt:10532.2] || -> xuntil6(s16)*. % 75.92/76.16 10534[28:MRR:160.0,10533.0] || -> until5(s17)*. % 75.92/76.16 10535[28:MRR:7412.0,10534.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.16 10539[29:Spt:10535.2] || -> xuntil6(s17)*. % 75.92/76.16 10540[29:MRR:159.0,10539.0] || -> until5(s18)*. % 75.92/76.16 10541[29:MRR:7405.0,10540.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.16 10542[30:Spt:10541.2] || -> xuntil6(s18)*. % 75.92/76.16 10543[30:MRR:158.0,10542.0] || -> until5(s19)*. % 75.92/76.16 10544[30:MRR:7401.0,10543.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.16 10548[31:Spt:10544.2] || -> xuntil6(s19)*. % 75.92/76.16 10549[31:MRR:157.0,10548.0] || -> until5(s20)*. % 75.92/76.16 10550[31:MRR:7397.0,10549.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.16 10551[32:Spt:10550.2] || -> xuntil6(s20)*. % 75.92/76.16 10552[32:MRR:156.0,10551.0] || -> until5(s21)*. % 75.92/76.16 10553[32:MRR:7393.0,10552.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.16 10557[33:Spt:10553.2] || -> xuntil6(s21)*. % 75.92/76.16 10558[33:MRR:155.0,10557.0] || -> until5(s22)*. % 75.92/76.16 10559[33:MRR:7392.0,10558.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.16 10560[34:Spt:10559.2] || -> xuntil6(s22)*. % 75.92/76.16 10561[34:MRR:154.0,10560.0] || -> until5(s23)*. % 75.92/76.16 10562[34:MRR:7385.0,10561.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.16 10566[35:Spt:10562.2] || -> xuntil6(s23)*. % 75.92/76.16 10567[35:MRR:153.0,10566.0] || -> until5(s24)*. % 75.92/76.16 10568[35:MRR:7381.0,10567.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.16 10569[36:Spt:10568.2] || -> xuntil6(s24)*. % 75.92/76.16 10570[36:MRR:152.0,10569.0] || -> until5(s25)*. % 75.92/76.16 10571[36:MRR:7377.0,10570.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.16 10575[37:Spt:10571.2] || -> xuntil6(s25)*. % 75.92/76.16 10576[37:MRR:151.0,10575.0] || -> until5(s26)*. % 75.92/76.16 10577[37:MRR:7373.0,10576.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.16 10578[38:Spt:10577.2] || -> xuntil6(s26)*. % 75.92/76.16 10579[38:MRR:150.0,10578.0] || -> until5(s27)*. % 75.92/76.16 10580[38:MRR:7372.0,10579.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.16 10584[39:Spt:10580.2] || -> xuntil6(s27)*. % 75.92/76.16 10585[39:MRR:149.0,10584.0] || -> until5(s28)*. % 75.92/76.16 10586[39:MRR:7365.0,10585.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.16 10587[40:Spt:10586.2] || -> xuntil6(s28)*. % 75.92/76.16 10588[40:MRR:148.0,10587.0] || -> until5(s29)*. % 75.92/76.16 10589[40:MRR:7364.0,10588.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.16 10593[41:Spt:10589.2] || -> xuntil6(s29)*. % 75.92/76.16 10594[41:MRR:147.0,10593.0] || -> until5(s30)*. % 75.92/76.16 10595[41:MRR:7363.0,10594.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.16 10596[42:Spt:10595.2] || -> xuntil6(s30)*. % 75.92/76.16 10597[42:MRR:146.0,10596.0] || -> until5(s31)*. % 75.92/76.16 10598[42:MRR:7359.0,10597.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.16 10602[43:Spt:10598.2] || -> xuntil6(s31)*. % 75.92/76.16 10603[43:MRR:145.0,10602.0] || -> until5(s32)*. % 75.92/76.16 10604[43:MRR:7358.0,10603.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.16 10605[44:Spt:10604.2] || -> xuntil6(s32)*. % 75.92/76.16 10606[44:MRR:144.0,10605.0] || -> until5(s33)*. % 75.92/76.16 10607[44:MRR:932.0,10606.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.16 10611[45:Spt:10607.1] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.16 10613[45:Res:10611.0,61.1] always3(s34) || -> . % 75.92/76.16 10614[45:SSi:10613.0,723.0] || -> . % 75.92/76.16 10615[45:Spt:10614.0,10607.1,10611.0] || m_main_v_state(s34,c_busy)*+ -> . % 75.92/76.16 10616[45:Spt:10614.0,10607.0,10607.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 75.92/76.16 10619[45:Res:53.1,10616.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 75.92/76.16 10621[46:Spt:10619.1] || -> xuntil6(s33)*. % 75.92/76.16 10622[46:MRR:143.0,10621.0] || -> until5(s34)*. % 75.92/76.16 10623[46:MRR:7483.0,10622.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.16 10628[47:Spt:10623.2] || -> xuntil6(s34)*. % 75.92/76.16 10629[47:MRR:142.0,10628.0] || -> until5(s35)*. % 75.92/76.16 10630[47:MRR:930.0,10629.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.16 10631[48:Spt:10630.1] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.16 10633[48:Res:10631.0,61.1] always3(s36) || -> . % 75.92/76.16 10634[48:SSi:10633.0,725.0] || -> . % 75.92/76.16 10635[48:Spt:10634.0,10630.1,10631.0] || m_main_v_state(s36,c_busy)*+ -> . % 75.92/76.16 10636[48:Spt:10634.0,10630.0,10630.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 75.92/76.16 10639[48:Res:53.1,10636.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 75.92/76.16 10641[49:Spt:10639.1] || -> xuntil6(s35)*. % 75.92/76.16 10642[49:MRR:141.0,10641.0] || -> until5(s36)*. % 75.92/76.16 10643[49:MRR:7484.0,10642.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.16 10651[50:Spt:10643.2] || -> xuntil6(s36)*. % 75.92/76.16 10652[50:MRR:140.0,10651.0] || -> until5(s37)*. % 75.92/76.16 10653[50:MRR:928.0,10652.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.16 10654[51:Spt:10653.1] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.16 10656[51:Res:10654.0,61.1] always3(s38) || -> . % 75.92/76.16 10657[51:SSi:10656.0,727.0] || -> . % 75.92/76.16 10658[51:Spt:10657.0,10653.1,10654.0] || m_main_v_state(s38,c_busy)*+ -> . % 75.92/76.16 10659[51:Spt:10657.0,10653.0,10653.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 75.92/76.16 10662[51:Res:53.1,10659.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 75.92/76.16 10667[52:Spt:10662.1] || -> xuntil6(s37)*. % 75.92/76.16 10668[52:MRR:139.0,10667.0] || -> until5(s38)*. % 75.92/76.16 10669[52:MRR:7488.0,10668.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.16 10671[53:Spt:10669.2] || -> xuntil6(s38)*. % 75.92/76.16 10672[53:MRR:138.0,10671.0] || -> until5(s39)*. % 75.92/76.16 10673[53:MRR:926.0,10672.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.16 10674[54:Spt:10673.1] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.16 10676[54:Res:10674.0,61.1] always3(s40) || -> . % 75.92/76.16 10677[54:SSi:10676.0,729.0] || -> . % 75.92/76.16 10678[54:Spt:10677.0,10673.1,10674.0] || m_main_v_state(s40,c_busy)*+ -> . % 75.92/76.16 10679[54:Spt:10677.0,10673.0,10673.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 75.92/76.16 10682[54:MRR:10463.2,10678.0] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.16 10683[54:Res:53.1,10679.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 75.92/76.16 10685[55:Spt:10683.1] || -> xuntil6(s39)*. % 75.92/76.16 10686[55:MRR:137.0,10685.0] || -> until5(s40)*. % 75.92/76.16 10687[55:MRR:7492.0,10686.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.16 10693[54:SoR:10682.0,64.1] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.16 10695[54:SoR:10693.0,66.2] until5(s49) || m_main_v_state(s49,c_ready)* -> xuntil6(s49). % 75.92/76.16 10696[56:Spt:10687.2] || -> xuntil6(s40)*. % 75.92/76.16 10697[56:MRR:136.0,10696.0] || -> until5(s41)*. % 75.92/76.16 10698[56:MRR:924.0,10697.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.16 10699[57:Spt:10698.1] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.16 10701[57:Res:10699.0,61.1] always3(s42) || -> . % 75.92/76.16 10702[57:SSi:10701.0,731.0] || -> . % 75.92/76.16 10703[57:Spt:10702.0,10698.1,10699.0] || m_main_v_state(s42,c_busy)*+ -> . % 75.92/76.16 10704[57:Spt:10702.0,10698.0,10698.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 75.92/76.16 10706[57:MRR:795.2,10703.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 75.92/76.16 10707[57:Res:53.1,10704.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 75.92/76.16 10709[58:Spt:10707.1] || -> xuntil6(s41)*. % 75.92/76.16 10710[58:MRR:135.0,10709.0] || -> until5(s42)*. % 75.92/76.16 10711[58:MRR:7496.0,10710.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.16 10716[59:Spt:10711.2] || -> xuntil6(s42)*. % 75.92/76.16 10717[59:MRR:134.0,10716.0] || -> until5(s43)*. % 75.92/76.16 10718[59:MRR:922.0,10717.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.16 10722[60:Spt:10718.1] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.16 10724[60:Res:10722.0,61.1] always3(s44) || -> . % 75.92/76.16 10725[60:SSi:10724.0,733.0] || -> . % 75.92/76.16 10726[60:Spt:10725.0,10718.1,10722.0] || m_main_v_state(s44,c_busy)*+ -> . % 75.92/76.16 10727[60:Spt:10725.0,10718.0,10718.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 75.92/76.16 10729[60:MRR:789.2,10726.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 75.92/76.16 10730[60:Res:53.1,10727.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 75.92/76.16 10732[61:Spt:10730.1] || -> xuntil6(s43)*. % 75.92/76.16 10733[61:MRR:133.0,10732.0] || -> until5(s44)*. % 75.92/76.16 10734[61:MRR:7503.0,10733.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.16 10739[62:Spt:10734.2] || -> xuntil6(s44)*. % 75.92/76.16 10740[62:MRR:132.0,10739.0] || -> until5(s45)*. % 75.92/76.16 10741[62:MRR:920.0,10740.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.16 10742[63:Spt:10741.1] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.16 10744[63:Res:10742.0,61.1] always3(s46) || -> . % 75.92/76.16 10745[63:SSi:10744.0,735.0] || -> . % 75.92/76.16 10746[63:Spt:10745.0,10741.1,10742.0] || m_main_v_state(s46,c_busy)*+ -> . % 75.92/76.16 10747[63:Spt:10745.0,10741.0,10741.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 75.92/76.16 10749[63:MRR:783.2,10746.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 75.92/76.16 10750[63:Res:53.1,10747.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 75.92/76.16 10752[64:Spt:10750.1] || -> xuntil6(s45)*. % 75.92/76.16 10753[64:MRR:131.0,10752.0] || -> until5(s46)*. % 75.92/76.16 10754[64:MRR:7504.0,10753.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.16 10762[65:Spt:10754.2] || -> xuntil6(s46)*. % 75.92/76.16 10763[65:MRR:130.0,10762.0] || -> until5(s47)*. % 75.92/76.16 10764[65:MRR:918.0,10763.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.16 10765[66:Spt:10764.1] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.16 10767[66:Res:10765.0,61.1] always3(s48) || -> . % 75.92/76.16 10768[66:SSi:10767.0,737.0] || -> . % 75.92/76.16 10769[66:Spt:10768.0,10764.1,10765.0] || m_main_v_state(s48,c_busy)*+ -> . % 75.92/76.16 10770[66:Spt:10768.0,10764.0,10764.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 75.92/76.16 10772[66:MRR:777.2,10769.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 75.92/76.16 10773[66:Res:53.1,10770.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 75.92/76.16 10778[67:Spt:10773.1] || -> xuntil6(s47)*. % 75.92/76.16 10779[67:MRR:129.0,10778.0] || -> until5(s48)*. % 75.92/76.16 10780[67:MRR:7508.0,10779.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.16 10782[68:Spt:10780.2] || -> xuntil6(s48)*. % 75.92/76.16 10783[68:MRR:128.0,10782.0] || -> until5(s49)*. % 75.92/76.16 10784[68:MRR:10695.0,10783.0] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.16 10785[68:Res:53.1,10784.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.16 10787[69:Spt:10785.1] || -> xuntil6(s49)*. % 75.92/76.16 10788[69:MRR:10462.0,10787.0] || -> until2p7(s40)*. % 75.92/76.16 10789[69:MRR:238.0,10788.0] || -> until2p7(s41)* node4(s40). % 75.92/76.16 10790[70:Spt:10789.0] || -> until2p7(s41)*. % 75.92/76.16 10791[70:MRR:239.0,10790.0] || -> until2p7(s42)* node4(s41). % 75.92/76.16 10792[71:Spt:10791.0] || -> until2p7(s42)*. % 75.92/76.16 10793[71:MRR:240.0,10792.0] || -> until2p7(s43)* node4(s42). % 75.92/76.16 10794[72:Spt:10793.0] || -> until2p7(s43)*. % 75.92/76.16 10795[72:MRR:241.0,10794.0] || -> until2p7(s44)* node4(s43). % 75.92/76.16 10796[73:Spt:10795.0] || -> until2p7(s44)*. % 75.92/76.16 10797[73:MRR:539.0,10796.0] || -> until2p7(s45)* node4(s44). % 75.92/76.16 10798[74:Spt:10797.0] || -> until2p7(s45)*. % 75.92/76.16 10799[74:MRR:544.0,10798.0] || -> until2p7(s46)* node4(s45). % 75.92/76.16 10800[75:Spt:10799.0] || -> until2p7(s46)*. % 75.92/76.16 10801[75:MRR:549.0,10800.0] || -> until2p7(s47)* node4(s46). % 75.92/76.16 10802[76:Spt:10801.0] || -> until2p7(s47)*. % 75.92/76.16 10803[76:MRR:554.0,10802.0] || -> until2p7(s48)* node4(s47). % 75.92/76.16 10804[77:Spt:10803.0] || -> until2p7(s48)*. % 75.92/76.16 10805[77:MRR:559.0,10804.0] || -> until2p7(s49)* node4(s48). % 75.92/76.16 10806[78:Spt:10805.0] || -> until2p7(s49)*. % 75.92/76.16 10807[78:MRR:194.0,10806.0] || -> node4(s49)*. % 75.92/76.16 10808[78:MRR:10693.0,10807.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.16 10809[78:Res:53.1,10808.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.16 10815[78:Res:10809.0,61.1] always3(s49) || -> . % 75.92/76.16 10816[78:SSi:10815.0,50.0,738.0,10783.0,10787.0,10806.0,10807.0] || -> . % 75.92/76.16 10817[78:Spt:10816.0,10805.0,10806.0] || until2p7(s49)*+ -> . % 75.92/76.16 10818[78:Spt:10816.0,10805.1] || -> node4(s48)*. % 75.92/76.16 10820[78:MRR:774.0,10818.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.16 10829[78:Res:53.1,10820.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.16 10831[78:MRR:10829.0,10769.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.16 10833[78:Res:10831.0,61.1] always3(s49) || -> . % 75.92/76.16 10834[78:SSi:10833.0,50.0,738.0,10783.0,10787.0] || -> . % 75.92/76.16 10835[77:Spt:10834.0,10803.0,10804.0] || until2p7(s48)*+ -> . % 75.92/76.16 10836[77:Spt:10834.0,10803.1] || -> node4(s47)*. % 75.92/76.16 10837[77:MRR:10772.0,10836.0] || m_main_v_state(s47,c_ready)*+ -> . % 75.92/76.16 10840[77:Res:53.1,10837.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.16 10843[77:Res:10840.0,61.1] always3(s47) || -> . % 75.92/76.16 10844[77:SSi:10843.0,736.0,10763.0,10778.0,10802.0,10836.0] || -> . % 75.92/76.16 10845[76:Spt:10844.0,10801.0,10802.0] || until2p7(s47)*+ -> . % 75.92/76.16 10846[76:Spt:10844.0,10801.1] || -> node4(s46)*. % 75.92/76.16 10848[76:MRR:780.0,10846.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.16 10860[76:Res:53.1,10848.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.16 10862[76:MRR:10860.0,10746.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.16 10867[76:Res:10862.0,61.1] always3(s47) || -> . % 75.92/76.16 10868[76:SSi:10867.0,736.0,10763.0,10778.0] || -> . % 75.92/76.16 10869[75:Spt:10868.0,10799.0,10800.0] || until2p7(s46)*+ -> . % 75.92/76.16 10870[75:Spt:10868.0,10799.1] || -> node4(s45)*. % 75.92/76.16 10871[75:MRR:10749.0,10870.0] || m_main_v_state(s45,c_ready)*+ -> . % 75.92/76.16 10874[75:Res:53.1,10871.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.16 10878[75:Res:10874.0,61.1] always3(s45) || -> . % 75.92/76.16 10879[75:SSi:10878.0,734.0,10740.0,10752.0,10798.0,10870.0] || -> . % 75.92/76.16 10880[74:Spt:10879.0,10797.0,10798.0] || until2p7(s45)*+ -> . % 75.92/76.16 10881[74:Spt:10879.0,10797.1] || -> node4(s44)*. % 75.92/76.16 10883[74:MRR:786.0,10881.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.16 10894[74:Res:53.1,10883.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.16 10896[74:MRR:10894.0,10726.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.16 10898[74:Res:10896.0,61.1] always3(s45) || -> . % 75.92/76.16 10899[74:SSi:10898.0,734.0,10740.0,10752.0] || -> . % 75.92/76.16 10900[73:Spt:10899.0,10795.0,10796.0] || until2p7(s44)*+ -> . % 75.92/76.16 10901[73:Spt:10899.0,10795.1] || -> node4(s43)*. % 75.92/76.16 10902[73:MRR:10729.0,10901.0] || m_main_v_state(s43,c_ready)*+ -> . % 75.92/76.16 10906[73:Res:53.1,10902.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.16 10909[73:Res:10906.0,61.1] always3(s43) || -> . % 75.92/76.16 10910[73:SSi:10909.0,732.0,10717.0,10732.0,10794.0,10901.0] || -> . % 75.92/76.16 10911[72:Spt:10910.0,10793.0,10794.0] || until2p7(s43)*+ -> . % 75.92/76.16 10912[72:Spt:10910.0,10793.1] || -> node4(s42)*. % 75.92/76.16 10914[72:MRR:792.0,10912.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.16 10925[72:Res:53.1,10914.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.16 10927[72:MRR:10925.0,10703.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.16 10929[72:Res:10927.0,61.1] always3(s43) || -> . % 75.92/76.16 10930[72:SSi:10929.0,732.0,10717.0,10732.0] || -> . % 75.92/76.16 10931[71:Spt:10930.0,10791.0,10792.0] || until2p7(s42)*+ -> . % 75.92/76.16 10932[71:Spt:10930.0,10791.1] || -> node4(s41)*. % 75.92/76.16 10933[71:MRR:10706.0,10932.0] || m_main_v_state(s41,c_ready)*+ -> . % 75.92/76.16 10936[71:Res:53.1,10933.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.16 10939[71:Res:10936.0,61.1] always3(s41) || -> . % 75.92/76.16 10940[71:SSi:10939.0,730.0,10697.0,10709.0,10790.0,10932.0] || -> . % 75.92/76.16 10941[70:Spt:10940.0,10789.0,10790.0] || until2p7(s41)*+ -> . % 75.92/76.16 10942[70:Spt:10940.0,10789.1] || -> node4(s40)*. % 75.92/76.16 10944[70:MRR:798.0,10942.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.16 10956[70:Res:53.1,10944.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.16 10958[70:MRR:10956.0,10678.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.16 10960[70:Res:10958.0,61.1] always3(s41) || -> . % 75.92/76.16 10961[70:SSi:10960.0,730.0,10697.0,10709.0] || -> . % 75.92/76.16 10962[69:Spt:10961.0,10785.1,10787.0] || xuntil6(s49)* -> . % 75.92/76.16 10963[69:Spt:10961.0,10785.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.16 10966[69:Res:10963.0,61.1] always3(s49) || -> . % 75.92/76.16 10967[69:SSi:10966.0,50.0,738.0,10783.0] || -> . % 75.92/76.16 10968[68:Spt:10967.0,10780.2,10782.0] || xuntil6(s48)*+ -> . % 75.92/76.16 10969[68:Spt:10967.0,10780.0,10780.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.16 10970[68:Res:53.1,10969.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.16 10972[68:MRR:10970.0,10769.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.16 10974[68:Res:10972.0,61.1] always3(s49) || -> . % 75.92/76.16 10975[68:SSi:10974.0,50.0,738.0] || -> . % 75.92/76.16 10976[67:Spt:10975.0,10773.1,10778.0] || xuntil6(s47)* -> . % 75.92/76.16 10977[67:Spt:10975.0,10773.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.16 10980[67:Res:10977.0,61.1] always3(s47) || -> . % 75.92/76.16 10981[67:SSi:10980.0,736.0,10763.0] || -> . % 75.92/76.16 10982[65:Spt:10981.0,10754.2,10762.0] || xuntil6(s46)*+ -> . % 75.92/76.16 10983[65:Spt:10981.0,10754.0,10754.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.16 10984[65:Res:53.1,10983.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.16 10986[65:MRR:10984.0,10746.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.16 10988[65:Res:10986.0,61.1] always3(s47) || -> . % 75.92/76.16 10989[65:SSi:10988.0,736.0] || -> . % 75.92/76.16 10990[64:Spt:10989.0,10750.1,10752.0] || xuntil6(s45)* -> . % 75.92/76.16 10991[64:Spt:10989.0,10750.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.16 10994[64:Res:10991.0,61.1] always3(s45) || -> . % 75.92/76.16 10995[64:SSi:10994.0,734.0,10740.0] || -> . % 75.92/76.16 10996[62:Spt:10995.0,10734.2,10739.0] || xuntil6(s44)*+ -> . % 75.92/76.16 10997[62:Spt:10995.0,10734.0,10734.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.16 10998[62:Res:53.1,10997.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.16 11000[62:MRR:10998.0,10726.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.16 11003[62:Res:11000.0,61.1] always3(s45) || -> . % 75.92/76.16 11004[62:SSi:11003.0,734.0] || -> . % 75.92/76.16 11005[61:Spt:11004.0,10730.1,10732.0] || xuntil6(s43)* -> . % 75.92/76.16 11006[61:Spt:11004.0,10730.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.16 11009[61:Res:11006.0,61.1] always3(s43) || -> . % 75.92/76.16 11010[61:SSi:11009.0,732.0,10717.0] || -> . % 75.92/76.16 11011[59:Spt:11010.0,10711.2,10716.0] || xuntil6(s42)*+ -> . % 75.92/76.16 11012[59:Spt:11010.0,10711.0,10711.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.16 11013[59:Res:53.1,11012.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.16 11015[59:MRR:11013.0,10703.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.16 11017[59:Res:11015.0,61.1] always3(s43) || -> . % 75.92/76.16 11018[59:SSi:11017.0,732.0] || -> . % 75.92/76.16 11019[58:Spt:11018.0,10707.1,10709.0] || xuntil6(s41)* -> . % 75.92/76.16 11020[58:Spt:11018.0,10707.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.16 11023[58:Res:11020.0,61.1] always3(s41) || -> . % 75.92/76.16 11024[58:SSi:11023.0,730.0,10697.0] || -> . % 75.92/76.16 11025[56:Spt:11024.0,10687.2,10696.0] || xuntil6(s40)*+ -> . % 75.92/76.16 11026[56:Spt:11024.0,10687.0,10687.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.16 11027[56:Res:53.1,11026.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.16 11029[56:MRR:11027.0,10678.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.16 11032[56:Res:11029.0,61.1] always3(s41) || -> . % 75.92/76.16 11033[56:SSi:11032.0,730.0] || -> . % 75.92/76.16 11034[55:Spt:11033.0,10683.1,10685.0] || xuntil6(s39)* -> . % 75.92/76.16 11035[55:Spt:11033.0,10683.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.16 11038[55:Res:11035.0,61.1] always3(s39) || -> . % 75.92/76.16 11039[55:SSi:11038.0,728.0,10672.0] || -> . % 75.92/76.16 11040[53:Spt:11039.0,10669.2,10671.0] || xuntil6(s38)*+ -> . % 75.92/76.16 11041[53:Spt:11039.0,10669.0,10669.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.16 11042[53:Res:53.1,11041.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.16 11044[53:MRR:11042.0,10658.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.16 11046[53:Res:11044.0,61.1] always3(s39) || -> . % 75.92/76.16 11047[53:SSi:11046.0,728.0] || -> . % 75.92/76.16 11048[52:Spt:11047.0,10662.1,10667.0] || xuntil6(s37)* -> . % 75.92/76.16 11049[52:Spt:11047.0,10662.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.16 11052[52:Res:11049.0,61.1] always3(s37) || -> . % 75.92/76.16 11053[52:SSi:11052.0,726.0,10652.0] || -> . % 75.92/76.16 11054[50:Spt:11053.0,10643.2,10651.0] || xuntil6(s36)*+ -> . % 75.92/76.16 11055[50:Spt:11053.0,10643.0,10643.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.16 11056[50:Res:53.1,11055.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.16 11058[50:MRR:11056.0,10635.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.16 11060[50:Res:11058.0,61.1] always3(s37) || -> . % 75.92/76.16 11061[50:SSi:11060.0,726.0] || -> . % 75.92/76.16 11062[49:Spt:11061.0,10639.1,10641.0] || xuntil6(s35)* -> . % 75.92/76.16 11063[49:Spt:11061.0,10639.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.16 11066[49:Res:11063.0,61.1] always3(s35) || -> . % 75.92/76.16 11067[49:SSi:11066.0,724.0,10629.0] || -> . % 75.92/76.16 11068[47:Spt:11067.0,10623.2,10628.0] || xuntil6(s34)*+ -> . % 75.92/76.16 11069[47:Spt:11067.0,10623.0,10623.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 75.92/76.16 11070[47:Res:53.1,11069.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 75.92/76.16 11072[47:MRR:11070.0,10615.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.16 11074[47:Res:11072.0,61.1] always3(s35) || -> . % 75.92/76.16 11075[47:SSi:11074.0,724.0] || -> . % 75.92/76.16 11076[46:Spt:11075.0,10619.1,10621.0] || xuntil6(s33)* -> . % 75.92/76.16 11077[46:Spt:11075.0,10619.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.16 11080[46:Res:11077.0,61.1] always3(s33) || -> . % 75.92/76.16 11081[46:SSi:11080.0,722.0,10606.0] || -> . % 75.92/76.16 11082[44:Spt:11081.0,10604.2,10605.0] || xuntil6(s32)*+ -> . % 75.92/76.16 11083[44:Spt:11081.0,10604.0,10604.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 75.92/76.16 11084[44:Res:53.1,11083.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 75.92/76.16 11086[45:Spt:11084.0] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.16 11088[45:Res:11086.0,61.1] always3(s32) || -> . % 75.92/76.16 11089[45:SSi:11088.0,721.0,10603.0] || -> . % 75.92/76.16 11090[45:Spt:11089.0,11084.0,11086.0] || m_main_v_state(s32,c_busy)* -> . % 75.92/76.16 11091[45:Spt:11089.0,11084.1] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.16 11095[45:Res:11091.0,61.1] always3(s33) || -> . % 75.92/76.16 11096[45:SSi:11095.0,722.0] || -> . % 75.92/76.16 11097[43:Spt:11096.0,10598.2,10602.0] || xuntil6(s31)*+ -> . % 75.92/76.16 11098[43:Spt:11096.0,10598.0,10598.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 75.92/76.16 11099[43:Res:53.1,11098.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 75.92/76.16 11101[44:Spt:11099.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.16 11103[44:Res:11101.0,61.1] always3(s31) || -> . % 75.92/76.16 11104[44:SSi:11103.0,720.0,10597.0] || -> . % 75.92/76.16 11105[44:Spt:11104.0,11099.0,11101.0] || m_main_v_state(s31,c_busy)* -> . % 75.92/76.16 11106[44:Spt:11104.0,11099.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.16 11110[44:Res:11106.0,61.1] always3(s32) || -> . % 75.92/76.16 11111[44:SSi:11110.0,721.0] || -> . % 75.92/76.16 11112[42:Spt:11111.0,10595.2,10596.0] || xuntil6(s30)*+ -> . % 75.92/76.16 11113[42:Spt:11111.0,10595.0,10595.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.16 11114[42:Res:53.1,11113.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.16 11116[43:Spt:11114.0] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.16 11118[43:Res:11116.0,61.1] always3(s30) || -> . % 75.92/76.16 11119[43:SSi:11118.0,719.0,10594.0] || -> . % 75.92/76.16 11120[43:Spt:11119.0,11114.0,11116.0] || m_main_v_state(s30,c_busy)* -> . % 75.92/76.16 11121[43:Spt:11119.0,11114.1] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.16 11125[43:Res:11121.0,61.1] always3(s31) || -> . % 75.92/76.16 11126[43:SSi:11125.0,720.0] || -> . % 75.92/76.16 11127[41:Spt:11126.0,10589.2,10593.0] || xuntil6(s29)*+ -> . % 75.92/76.16 11128[41:Spt:11126.0,10589.0,10589.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 75.92/76.16 11129[41:Res:53.1,11128.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 75.92/76.16 11131[42:Spt:11129.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.16 11133[42:Res:11131.0,61.1] always3(s29) || -> . % 75.92/76.16 11134[42:SSi:11133.0,718.0,10588.0] || -> . % 75.92/76.16 11135[42:Spt:11134.0,11129.0,11131.0] || m_main_v_state(s29,c_busy)* -> . % 75.92/76.16 11136[42:Spt:11134.0,11129.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.16 11140[42:Res:11136.0,61.1] always3(s30) || -> . % 75.92/76.16 11141[42:SSi:11140.0,719.0] || -> . % 75.92/76.16 11142[40:Spt:11141.0,10586.2,10587.0] || xuntil6(s28)*+ -> . % 75.92/76.16 11143[40:Spt:11141.0,10586.0,10586.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.16 11144[40:Res:53.1,11143.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.16 11146[41:Spt:11144.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.16 11148[41:Res:11146.0,61.1] always3(s28) || -> . % 75.92/76.16 11149[41:SSi:11148.0,717.0,10585.0] || -> . % 75.92/76.16 11150[41:Spt:11149.0,11144.0,11146.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.16 11151[41:Spt:11149.0,11144.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.16 11155[41:Res:11151.0,61.1] always3(s29) || -> . % 75.92/76.16 11156[41:SSi:11155.0,718.0] || -> . % 75.92/76.16 11157[39:Spt:11156.0,10580.2,10584.0] || xuntil6(s27)*+ -> . % 75.92/76.16 11158[39:Spt:11156.0,10580.0,10580.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.16 11159[39:Res:53.1,11158.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.16 11161[40:Spt:11159.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.16 11163[40:Res:11161.0,61.1] always3(s28) || -> . % 75.92/76.16 11164[40:SSi:11163.0,717.0] || -> . % 75.92/76.16 11165[40:Spt:11164.0,11159.1,11161.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.16 11166[40:Spt:11164.0,11159.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.16 11169[40:Res:11166.0,61.1] always3(s27) || -> . % 75.92/76.16 11170[40:SSi:11169.0,716.0,10579.0] || -> . % 75.92/76.16 11171[38:Spt:11170.0,10577.2,10578.0] || xuntil6(s26)*+ -> . % 75.92/76.16 11172[38:Spt:11170.0,10577.0,10577.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.16 11173[38:Res:53.1,11172.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.16 11175[39:Spt:11173.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.16 11177[39:Res:11175.0,61.1] always3(s27) || -> . % 75.92/76.16 11178[39:SSi:11177.0,716.0] || -> . % 75.92/76.16 11179[39:Spt:11178.0,11173.1,11175.0] || m_main_v_state(s27,c_busy)* -> . % 75.92/76.16 11180[39:Spt:11178.0,11173.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.16 11183[39:Res:11180.0,61.1] always3(s26) || -> . % 75.92/76.16 11184[39:SSi:11183.0,715.0,10576.0] || -> . % 75.92/76.16 11185[37:Spt:11184.0,10571.2,10575.0] || xuntil6(s25)*+ -> . % 75.92/76.16 11186[37:Spt:11184.0,10571.0,10571.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.16 11187[37:Res:53.1,11186.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.16 11192[38:Spt:11187.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.16 11194[38:Res:11192.0,61.1] always3(s25) || -> . % 75.92/76.16 11195[38:SSi:11194.0,714.0,10570.0] || -> . % 75.92/76.16 11196[38:Spt:11195.0,11187.0,11192.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.16 11197[38:Spt:11195.0,11187.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.16 11201[38:Res:11197.0,61.1] always3(s26) || -> . % 75.92/76.16 11202[38:SSi:11201.0,715.0] || -> . % 75.92/76.16 11203[36:Spt:11202.0,10568.2,10569.0] || xuntil6(s24)*+ -> . % 75.92/76.16 11204[36:Spt:11202.0,10568.0,10568.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.16 11205[36:Res:53.1,11204.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.16 11207[37:Spt:11205.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.16 11209[37:Res:11207.0,61.1] always3(s25) || -> . % 75.92/76.16 11210[37:SSi:11209.0,714.0] || -> . % 75.92/76.16 11211[37:Spt:11210.0,11205.1,11207.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.16 11212[37:Spt:11210.0,11205.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.16 11215[37:Res:11212.0,61.1] always3(s24) || -> . % 75.92/76.16 11216[37:SSi:11215.0,713.0,10567.0] || -> . % 75.92/76.16 11217[35:Spt:11216.0,10562.2,10566.0] || xuntil6(s23)*+ -> . % 75.92/76.16 11218[35:Spt:11216.0,10562.0,10562.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.16 11219[35:Res:53.1,11218.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.16 11221[36:Spt:11219.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.16 11223[36:Res:11221.0,61.1] always3(s24) || -> . % 75.92/76.16 11224[36:SSi:11223.0,713.0] || -> . % 75.92/76.16 11225[36:Spt:11224.0,11219.1,11221.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.16 11226[36:Spt:11224.0,11219.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.16 11229[36:Res:11226.0,61.1] always3(s23) || -> . % 75.92/76.16 11230[36:SSi:11229.0,712.0,10561.0] || -> . % 75.92/76.16 11231[34:Spt:11230.0,10559.2,10560.0] || xuntil6(s22)*+ -> . % 75.92/76.16 11232[34:Spt:11230.0,10559.0,10559.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.16 11233[34:Res:53.1,11232.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.16 11238[35:Spt:11233.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.16 11240[35:Res:11238.0,61.1] always3(s22) || -> . % 75.92/76.16 11241[35:SSi:11240.0,711.0,10558.0] || -> . % 75.92/76.16 11242[35:Spt:11241.0,11233.0,11238.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.16 11243[35:Spt:11241.0,11233.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.16 11247[35:Res:11243.0,61.1] always3(s23) || -> . % 75.92/76.16 11248[35:SSi:11247.0,712.0] || -> . % 75.92/76.16 11249[33:Spt:11248.0,10553.2,10557.0] || xuntil6(s21)*+ -> . % 75.92/76.16 11250[33:Spt:11248.0,10553.0,10553.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.16 11251[33:Res:53.1,11250.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.16 11253[34:Spt:11251.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.16 11255[34:Res:11253.0,61.1] always3(s22) || -> . % 75.92/76.16 11256[34:SSi:11255.0,711.0] || -> . % 75.92/76.16 11257[34:Spt:11256.0,11251.1,11253.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.16 11258[34:Spt:11256.0,11251.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.16 11261[34:Res:11258.0,61.1] always3(s21) || -> . % 75.92/76.16 11262[34:SSi:11261.0,710.0,10552.0] || -> . % 75.92/76.16 11263[32:Spt:11262.0,10550.2,10551.0] || xuntil6(s20)*+ -> . % 75.92/76.16 11264[32:Spt:11262.0,10550.0,10550.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.16 11265[32:Res:53.1,11264.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.16 11267[33:Spt:11265.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.16 11269[33:Res:11267.0,61.1] always3(s21) || -> . % 75.92/76.16 11270[33:SSi:11269.0,710.0] || -> . % 75.92/76.16 11271[33:Spt:11270.0,11265.1,11267.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.16 11272[33:Spt:11270.0,11265.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.16 11275[33:Res:11272.0,61.1] always3(s20) || -> . % 75.92/76.16 11276[33:SSi:11275.0,709.0,10549.0] || -> . % 75.92/76.16 11277[31:Spt:11276.0,10544.2,10548.0] || xuntil6(s19)*+ -> . % 75.92/76.16 11278[31:Spt:11276.0,10544.0,10544.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.16 11279[31:Res:53.1,11278.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.16 11284[32:Spt:11279.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.16 11286[32:Res:11284.0,61.1] always3(s19) || -> . % 75.92/76.16 11287[32:SSi:11286.0,708.0,10543.0] || -> . % 75.92/76.16 11288[32:Spt:11287.0,11279.0,11284.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.16 11289[32:Spt:11287.0,11279.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.16 11293[32:Res:11289.0,61.1] always3(s20) || -> . % 75.92/76.16 11294[32:SSi:11293.0,709.0] || -> . % 75.92/76.16 11295[30:Spt:11294.0,10541.2,10542.0] || xuntil6(s18)*+ -> . % 75.92/76.16 11296[30:Spt:11294.0,10541.0,10541.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.16 11297[30:Res:53.1,11296.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.16 11299[31:Spt:11297.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.16 11301[31:Res:11299.0,61.1] always3(s19) || -> . % 75.92/76.16 11302[31:SSi:11301.0,708.0] || -> . % 75.92/76.16 11303[31:Spt:11302.0,11297.1,11299.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.16 11304[31:Spt:11302.0,11297.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.16 11307[31:Res:11304.0,61.1] always3(s18) || -> . % 75.92/76.16 11308[31:SSi:11307.0,707.0,10540.0] || -> . % 75.92/76.16 11309[29:Spt:11308.0,10535.2,10539.0] || xuntil6(s17)*+ -> . % 75.92/76.16 11310[29:Spt:11308.0,10535.0,10535.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.16 11311[29:Res:53.1,11310.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.16 11313[30:Spt:11311.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.16 11315[30:Res:11313.0,61.1] always3(s18) || -> . % 75.92/76.16 11316[30:SSi:11315.0,707.0] || -> . % 75.92/76.16 11317[30:Spt:11316.0,11311.1,11313.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.16 11318[30:Spt:11316.0,11311.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.16 11321[30:Res:11318.0,61.1] always3(s17) || -> . % 75.92/76.16 11322[30:SSi:11321.0,706.0,10534.0] || -> . % 75.92/76.16 11323[28:Spt:11322.0,10532.2,10533.0] || xuntil6(s16)*+ -> . % 75.92/76.16 11324[28:Spt:11322.0,10532.0,10532.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.16 11325[28:Res:53.1,11324.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.16 11330[29:Spt:11325.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.16 11332[29:Res:11330.0,61.1] always3(s16) || -> . % 75.92/76.16 11333[29:SSi:11332.0,705.0,10531.0] || -> . % 75.92/76.16 11334[29:Spt:11333.0,11325.0,11330.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.16 11335[29:Spt:11333.0,11325.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.16 11339[29:Res:11335.0,61.1] always3(s17) || -> . % 75.92/76.16 11340[29:SSi:11339.0,706.0] || -> . % 75.92/76.16 11341[27:Spt:11340.0,10526.2,10530.0] || xuntil6(s15)*+ -> . % 75.92/76.16 11342[27:Spt:11340.0,10526.0,10526.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.16 11343[27:Res:53.1,11342.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.16 11345[28:Spt:11343.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.16 11347[28:Res:11345.0,61.1] always3(s16) || -> . % 75.92/76.16 11348[28:SSi:11347.0,705.0] || -> . % 75.92/76.16 11349[28:Spt:11348.0,11343.1,11345.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.16 11350[28:Spt:11348.0,11343.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.16 11353[28:Res:11350.0,61.1] always3(s15) || -> . % 75.92/76.16 11354[28:SSi:11353.0,704.0,10525.0] || -> . % 75.92/76.16 11355[26:Spt:11354.0,10523.2,10524.0] || xuntil6(s14)*+ -> . % 75.92/76.16 11356[26:Spt:11354.0,10523.0,10523.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.16 11357[26:Res:53.1,11356.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.16 11359[27:Spt:11357.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.16 11361[27:Res:11359.0,61.1] always3(s15) || -> . % 75.92/76.16 11362[27:SSi:11361.0,704.0] || -> . % 75.92/76.16 11363[27:Spt:11362.0,11357.1,11359.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.16 11364[27:Spt:11362.0,11357.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.16 11367[27:Res:11364.0,61.1] always3(s14) || -> . % 75.92/76.16 11368[27:SSi:11367.0,703.0,10522.0] || -> . % 75.92/76.16 11369[25:Spt:11368.0,10517.2,10521.0] || xuntil6(s13)*+ -> . % 75.92/76.16 11370[25:Spt:11368.0,10517.0,10517.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.16 11371[25:Res:53.1,11370.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.16 11376[26:Spt:11371.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.16 11378[26:Res:11376.0,61.1] always3(s13) || -> . % 75.92/76.16 11379[26:SSi:11378.0,702.0,10516.0] || -> . % 75.92/76.16 11380[26:Spt:11379.0,11371.0,11376.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.16 11381[26:Spt:11379.0,11371.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.16 11385[26:Res:11381.0,61.1] always3(s14) || -> . % 75.92/76.16 11386[26:SSi:11385.0,703.0] || -> . % 75.92/76.16 11387[24:Spt:11386.0,10514.2,10515.0] || xuntil6(s12)*+ -> . % 75.92/76.16 11388[24:Spt:11386.0,10514.0,10514.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.16 11389[24:Res:53.1,11388.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.16 11391[25:Spt:11389.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.16 11393[25:Res:11391.0,61.1] always3(s13) || -> . % 75.92/76.16 11394[25:SSi:11393.0,702.0] || -> . % 75.92/76.16 11395[25:Spt:11394.0,11389.1,11391.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.16 11396[25:Spt:11394.0,11389.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.16 11399[25:Res:11396.0,61.1] always3(s12) || -> . % 75.92/76.16 11400[25:SSi:11399.0,701.0,10513.0] || -> . % 75.92/76.16 11401[23:Spt:11400.0,10508.2,10512.0] || xuntil6(s11)*+ -> . % 75.92/76.16 11402[23:Spt:11400.0,10508.0,10508.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.16 11403[23:Res:53.1,11402.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.16 11405[24:Spt:11403.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.16 11407[24:Res:11405.0,61.1] always3(s12) || -> . % 75.92/76.16 11408[24:SSi:11407.0,701.0] || -> . % 75.92/76.16 11409[24:Spt:11408.0,11403.1,11405.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.16 11410[24:Spt:11408.0,11403.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.16 11413[24:Res:11410.0,61.1] always3(s11) || -> . % 75.92/76.16 11414[24:SSi:11413.0,700.0,10507.0] || -> . % 75.92/76.16 11415[22:Spt:11414.0,10505.2,10506.0] || xuntil6(s10)*+ -> . % 75.92/76.16 11416[22:Spt:11414.0,10505.0,10505.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.16 11417[22:Res:53.1,11416.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.16 11422[23:Spt:11417.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.16 11424[23:Res:11422.0,61.1] always3(s10) || -> . % 75.92/76.16 11425[23:SSi:11424.0,699.0,10504.0] || -> . % 75.92/76.16 11426[23:Spt:11425.0,11417.0,11422.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.16 11427[23:Spt:11425.0,11417.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.16 11431[23:Res:11427.0,61.1] always3(s11) || -> . % 75.92/76.16 11432[23:SSi:11431.0,700.0] || -> . % 75.92/76.16 11433[21:Spt:11432.0,10499.2,10503.0] || xuntil6(s9)*+ -> . % 75.92/76.16 11434[21:Spt:11432.0,10499.0,10499.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.16 11435[21:Res:53.1,11434.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.16 11437[22:Spt:11435.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.16 11439[22:Res:11437.0,61.1] always3(s10) || -> . % 75.92/76.16 11440[22:SSi:11439.0,699.0] || -> . % 75.92/76.16 11441[22:Spt:11440.0,11435.1,11437.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.16 11442[22:Spt:11440.0,11435.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.16 11445[22:Res:11442.0,61.1] always3(s9) || -> . % 75.92/76.16 11446[22:SSi:11445.0,698.0,10498.0] || -> . % 75.92/76.16 11447[20:Spt:11446.0,10496.2,10497.0] || xuntil6(s8)*+ -> . % 75.92/76.16 11448[20:Spt:11446.0,10496.0,10496.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.16 11449[20:Res:53.1,11448.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.16 11451[21:Spt:11449.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.16 11453[21:Res:11451.0,61.1] always3(s9) || -> . % 75.92/76.16 11454[21:SSi:11453.0,698.0] || -> . % 75.92/76.16 11455[21:Spt:11454.0,11449.1,11451.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.16 11456[21:Spt:11454.0,11449.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.16 11459[21:Res:11456.0,61.1] always3(s8) || -> . % 75.92/76.16 11460[21:SSi:11459.0,697.0,10495.0] || -> . % 75.92/76.16 11461[19:Spt:11460.0,10490.2,10494.0] || xuntil6(s7)*+ -> . % 75.92/76.16 11462[19:Spt:11460.0,10490.0,10490.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.16 11463[19:Res:53.1,11462.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.16 11468[20:Spt:11463.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.16 11470[20:Res:11468.0,61.1] always3(s7) || -> . % 75.92/76.16 11471[20:SSi:11470.0,696.0,10489.0] || -> . % 75.92/76.16 11472[20:Spt:11471.0,11463.0,11468.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.16 11473[20:Spt:11471.0,11463.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.16 11477[20:Res:11473.0,61.1] always3(s8) || -> . % 75.92/76.16 11478[20:SSi:11477.0,697.0] || -> . % 75.92/76.16 11479[18:Spt:11478.0,10487.2,10488.0] || xuntil6(s6)*+ -> . % 75.92/76.16 11480[18:Spt:11478.0,10487.0,10487.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.16 11481[18:Res:53.1,11480.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.16 11483[19:Spt:11481.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.16 11485[19:Res:11483.0,61.1] always3(s7) || -> . % 75.92/76.16 11486[19:SSi:11485.0,696.0] || -> . % 75.92/76.16 11487[19:Spt:11486.0,11481.1,11483.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.16 11488[19:Spt:11486.0,11481.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.16 11491[19:Res:11488.0,61.1] always3(s6) || -> . % 75.92/76.16 11492[19:SSi:11491.0,695.0,10486.0] || -> . % 75.92/76.16 11493[17:Spt:11492.0,10481.2,10485.0] || xuntil6(s5)*+ -> . % 75.92/76.16 11494[17:Spt:11492.0,10481.0,10481.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.16 11495[17:Res:53.1,11494.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.16 11497[18:Spt:11495.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.16 11499[18:Res:11497.0,61.1] always3(s6) || -> . % 75.92/76.16 11500[18:SSi:11499.0,695.0] || -> . % 75.92/76.16 11501[18:Spt:11500.0,11495.1,11497.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.16 11502[18:Spt:11500.0,11495.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.16 11505[18:Res:11502.0,61.1] always3(s5) || -> . % 75.92/76.16 11506[18:SSi:11505.0,694.0,10480.0] || -> . % 75.92/76.16 11507[16:Spt:11506.0,10478.2,10479.0] || xuntil6(s4)*+ -> . % 75.92/76.16 11508[16:Spt:11506.0,10478.0,10478.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.16 11509[16:Res:53.1,11508.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.16 11514[17:Spt:11509.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.16 11516[17:Res:11514.0,61.1] always3(s4) || -> . % 75.92/76.16 11517[17:SSi:11516.0,693.0,10477.0] || -> . % 75.92/76.16 11518[17:Spt:11517.0,11509.0,11514.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.16 11519[17:Spt:11517.0,11509.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.16 11523[17:Res:11519.0,61.1] always3(s5) || -> . % 75.92/76.16 11524[17:SSi:11523.0,694.0] || -> . % 75.92/76.16 11525[15:Spt:11524.0,10475.2,10476.0] || xuntil6(s3)*+ -> . % 75.92/76.16 11526[15:Spt:11524.0,10475.0,10475.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.16 11527[15:Res:53.1,11526.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.16 11529[16:Spt:11527.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.16 11531[16:Res:11529.0,61.1] always3(s4) || -> . % 75.92/76.16 11532[16:SSi:11531.0,693.0] || -> . % 75.92/76.16 11533[16:Spt:11532.0,11527.1,11529.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.16 11534[16:Spt:11532.0,11527.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.16 11537[16:Res:11534.0,61.1] always3(s3) || -> . % 75.92/76.16 11538[16:SSi:11537.0,692.0,10474.0] || -> . % 75.92/76.16 11539[14:Spt:11538.0,10472.2,10473.0] || xuntil6(s2)*+ -> . % 75.92/76.16 11540[14:Spt:11538.0,10472.0,10472.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.16 11541[14:Res:53.1,11540.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.16 11543[15:Spt:11541.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.16 11545[15:Res:11543.0,61.1] always3(s3) || -> . % 75.92/76.16 11546[15:SSi:11545.0,692.0] || -> . % 75.92/76.16 11547[15:Spt:11546.0,11541.1,11543.0] || m_main_v_state(s3,c_busy)* -> . % 75.92/76.16 11548[15:Spt:11546.0,11541.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.16 11551[15:Res:11548.0,61.1] always3(s2) || -> . % 75.92/76.16 11552[15:SSi:11551.0,691.0,10471.0] || -> . % 75.92/76.16 11553[13:Spt:11552.0,10466.2,10470.0] || xuntil6(s1)*+ -> . % 75.92/76.16 11554[13:Spt:11552.0,10466.0,10466.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.16 11555[13:Res:53.1,11554.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.16 11560[14:Spt:11555.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.16 11562[14:Res:11560.0,61.1] always3(s1) || -> . % 75.92/76.16 11563[14:SSi:11562.0,690.0,10465.0] || -> . % 75.92/76.16 11564[14:Spt:11563.0,11555.0,11560.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.16 11565[14:Spt:11563.0,11555.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.16 11570[14:Res:11565.0,61.1] always3(s2) || -> . % 75.92/76.16 11571[14:SSi:11570.0,691.0] || -> . % 75.92/76.16 11572[12:Spt:11571.0,74.0,10464.0] || xuntil6(s0)*+ -> . % 75.92/76.16 11573[12:Spt:11571.0,74.1] || -> node4(s0)*. % 75.92/76.16 11574[12:MRR:758.1,11572.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.16 11576[12:Res:11574.0,61.1] always3(s1) || -> . % 75.92/76.16 11577[12:SSi:11576.0,690.0] || -> . % 75.92/76.16 11578[11:Spt:11577.0,10454.0,10458.0] || trans(s49,s40)*+ -> . % 75.92/76.16 11579[11:Spt:11577.0,10454.1,10454.2,10454.3,10454.4,10454.5,10454.6,10454.7,10454.8,10454.9,10454.10,10454.11,10454.12,10454.13,10454.14,10454.15,10454.16,10454.17,10454.18,10454.19,10454.20,10454.21,10454.22,10454.23,10454.24,10454.25,10454.26,10454.27,10454.28,10454.29,10454.30,10454.31,10454.32,10454.33,10454.34,10454.35,10454.36,10454.37,10454.38,10454.39,10454.40] || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.16 11581[11:MRR:10455.0,11578.0] || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.16 11582[11:MRR:10457.1,11578.0] xuntil6(s49) || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.16 11583[12:Spt:11579.0] || -> trans(s49,s39)*. % 75.92/76.16 11584[12:Res:11583.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s39)*. % 75.92/76.16 11586[12:Res:11583.0,60.0] || -> node2(s49,s39)*. % 75.92/76.16 11587[12:SSi:11584.1,50.0,738.0] xuntil6(s49) || -> until2p7(s39)*. % 75.92/76.16 11588[12:Res:11586.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 75.92/76.16 11589[13:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.16 11590[13:MRR:176.0,11589.0] || -> until5(s1)*. % 75.92/76.16 11591[13:MRR:7473.0,11590.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.16 11595[14:Spt:11591.2] || -> xuntil6(s1)*. % 75.92/76.16 11596[14:MRR:175.0,11595.0] || -> until5(s2)*. % 75.92/76.16 11597[14:MRR:7472.0,11596.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.16 11598[15:Spt:11597.2] || -> xuntil6(s2)*. % 75.92/76.16 11599[15:MRR:174.0,11598.0] || -> until5(s3)*. % 75.92/76.16 11600[15:MRR:7465.0,11599.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.16 11601[16:Spt:11600.2] || -> xuntil6(s3)*. % 75.92/76.16 11602[16:MRR:173.0,11601.0] || -> until5(s4)*. % 75.92/76.16 11603[16:MRR:7461.0,11602.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.16 11604[17:Spt:11603.2] || -> xuntil6(s4)*. % 75.92/76.16 11605[17:MRR:172.0,11604.0] || -> until5(s5)*. % 75.92/76.16 11606[17:MRR:7457.0,11605.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.16 11610[18:Spt:11606.2] || -> xuntil6(s5)*. % 75.92/76.16 11611[18:MRR:171.0,11610.0] || -> until5(s6)*. % 75.92/76.16 11612[18:MRR:7453.0,11611.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.16 11613[19:Spt:11612.2] || -> xuntil6(s6)*. % 75.92/76.16 11614[19:MRR:170.0,11613.0] || -> until5(s7)*. % 75.92/76.16 11615[19:MRR:7452.0,11614.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.16 11619[20:Spt:11615.2] || -> xuntil6(s7)*. % 75.92/76.16 11620[20:MRR:169.0,11619.0] || -> until5(s8)*. % 75.92/76.16 11621[20:MRR:7445.0,11620.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.16 11622[21:Spt:11621.2] || -> xuntil6(s8)*. % 75.92/76.16 11623[21:MRR:168.0,11622.0] || -> until5(s9)*. % 75.92/76.16 11624[21:MRR:7441.0,11623.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.16 11628[22:Spt:11624.2] || -> xuntil6(s9)*. % 75.92/76.16 11629[22:MRR:167.0,11628.0] || -> until5(s10)*. % 75.92/76.16 11630[22:MRR:7437.0,11629.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.16 11631[23:Spt:11630.2] || -> xuntil6(s10)*. % 75.92/76.16 11632[23:MRR:166.0,11631.0] || -> until5(s11)*. % 75.92/76.16 11633[23:MRR:7433.0,11632.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.16 11637[24:Spt:11633.2] || -> xuntil6(s11)*. % 75.92/76.16 11638[24:MRR:165.0,11637.0] || -> until5(s12)*. % 75.92/76.16 11639[24:MRR:7432.0,11638.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.16 11640[25:Spt:11639.2] || -> xuntil6(s12)*. % 75.92/76.16 11641[25:MRR:164.0,11640.0] || -> until5(s13)*. % 75.92/76.16 11642[25:MRR:7425.0,11641.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.16 11646[26:Spt:11642.2] || -> xuntil6(s13)*. % 75.92/76.16 11647[26:MRR:163.0,11646.0] || -> until5(s14)*. % 75.92/76.16 11648[26:MRR:7421.0,11647.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.16 11649[27:Spt:11648.2] || -> xuntil6(s14)*. % 75.92/76.16 11650[27:MRR:162.0,11649.0] || -> until5(s15)*. % 75.92/76.16 11651[27:MRR:7417.0,11650.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.16 11655[28:Spt:11651.2] || -> xuntil6(s15)*. % 75.92/76.16 11656[28:MRR:161.0,11655.0] || -> until5(s16)*. % 75.92/76.16 11657[28:MRR:7413.0,11656.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.16 11658[29:Spt:11657.2] || -> xuntil6(s16)*. % 75.92/76.16 11659[29:MRR:160.0,11658.0] || -> until5(s17)*. % 75.92/76.16 11660[29:MRR:7412.0,11659.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.16 11664[30:Spt:11660.2] || -> xuntil6(s17)*. % 75.92/76.16 11665[30:MRR:159.0,11664.0] || -> until5(s18)*. % 75.92/76.16 11666[30:MRR:7405.0,11665.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.16 11667[31:Spt:11666.2] || -> xuntil6(s18)*. % 75.92/76.16 11668[31:MRR:158.0,11667.0] || -> until5(s19)*. % 75.92/76.16 11669[31:MRR:7401.0,11668.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.16 11673[32:Spt:11669.2] || -> xuntil6(s19)*. % 75.92/76.16 11674[32:MRR:157.0,11673.0] || -> until5(s20)*. % 75.92/76.16 11675[32:MRR:7397.0,11674.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.16 11676[33:Spt:11675.2] || -> xuntil6(s20)*. % 75.92/76.16 11677[33:MRR:156.0,11676.0] || -> until5(s21)*. % 75.92/76.16 11678[33:MRR:7393.0,11677.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.16 11682[34:Spt:11678.2] || -> xuntil6(s21)*. % 75.92/76.16 11683[34:MRR:155.0,11682.0] || -> until5(s22)*. % 75.92/76.16 11684[34:MRR:7392.0,11683.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.16 11685[35:Spt:11684.2] || -> xuntil6(s22)*. % 75.92/76.16 11686[35:MRR:154.0,11685.0] || -> until5(s23)*. % 75.92/76.16 11687[35:MRR:7385.0,11686.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.16 11691[36:Spt:11687.2] || -> xuntil6(s23)*. % 75.92/76.16 11692[36:MRR:153.0,11691.0] || -> until5(s24)*. % 75.92/76.16 11693[36:MRR:7381.0,11692.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.16 11694[37:Spt:11693.2] || -> xuntil6(s24)*. % 75.92/76.16 11695[37:MRR:152.0,11694.0] || -> until5(s25)*. % 75.92/76.16 11696[37:MRR:7377.0,11695.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.16 11700[38:Spt:11696.2] || -> xuntil6(s25)*. % 75.92/76.16 11701[38:MRR:151.0,11700.0] || -> until5(s26)*. % 75.92/76.16 11702[38:MRR:7373.0,11701.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.16 11703[39:Spt:11702.2] || -> xuntil6(s26)*. % 75.92/76.16 11704[39:MRR:150.0,11703.0] || -> until5(s27)*. % 75.92/76.16 11705[39:MRR:7372.0,11704.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.16 11709[40:Spt:11705.2] || -> xuntil6(s27)*. % 75.92/76.16 11710[40:MRR:149.0,11709.0] || -> until5(s28)*. % 75.92/76.16 11711[40:MRR:7365.0,11710.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.16 11712[41:Spt:11711.2] || -> xuntil6(s28)*. % 75.92/76.16 11713[41:MRR:148.0,11712.0] || -> until5(s29)*. % 75.92/76.16 11714[41:MRR:7364.0,11713.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.16 11718[42:Spt:11714.2] || -> xuntil6(s29)*. % 75.92/76.16 11719[42:MRR:147.0,11718.0] || -> until5(s30)*. % 75.92/76.16 11720[42:MRR:7363.0,11719.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.16 11721[43:Spt:11720.2] || -> xuntil6(s30)*. % 75.92/76.16 11722[43:MRR:146.0,11721.0] || -> until5(s31)*. % 75.92/76.16 11723[43:MRR:7359.0,11722.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.16 11727[44:Spt:11723.2] || -> xuntil6(s31)*. % 75.92/76.16 11728[44:MRR:145.0,11727.0] || -> until5(s32)*. % 75.92/76.16 11729[44:MRR:7358.0,11728.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.16 11730[45:Spt:11729.2] || -> xuntil6(s32)*. % 75.92/76.16 11731[45:MRR:144.0,11730.0] || -> until5(s33)*. % 75.92/76.16 11732[45:MRR:932.0,11731.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.16 11736[46:Spt:11732.1] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.16 11738[46:Res:11736.0,61.1] always3(s34) || -> . % 75.92/76.16 11739[46:SSi:11738.0,723.0] || -> . % 75.92/76.16 11740[46:Spt:11739.0,11732.1,11736.0] || m_main_v_state(s34,c_busy)*+ -> . % 75.92/76.16 11741[46:Spt:11739.0,11732.0,11732.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 75.92/76.16 11744[46:Res:53.1,11741.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 75.92/76.16 11746[47:Spt:11744.1] || -> xuntil6(s33)*. % 75.92/76.16 11747[47:MRR:143.0,11746.0] || -> until5(s34)*. % 75.92/76.16 11748[47:MRR:7483.0,11747.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.16 11753[48:Spt:11748.2] || -> xuntil6(s34)*. % 75.92/76.16 11754[48:MRR:142.0,11753.0] || -> until5(s35)*. % 75.92/76.16 11755[48:MRR:930.0,11754.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.16 11756[49:Spt:11755.1] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.16 11758[49:Res:11756.0,61.1] always3(s36) || -> . % 75.92/76.16 11759[49:SSi:11758.0,725.0] || -> . % 75.92/76.16 11760[49:Spt:11759.0,11755.1,11756.0] || m_main_v_state(s36,c_busy)*+ -> . % 75.92/76.16 11761[49:Spt:11759.0,11755.0,11755.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 75.92/76.16 11764[49:Res:53.1,11761.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 75.92/76.16 11766[50:Spt:11764.1] || -> xuntil6(s35)*. % 75.92/76.16 11767[50:MRR:141.0,11766.0] || -> until5(s36)*. % 75.92/76.16 11768[50:MRR:7484.0,11767.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.16 11776[51:Spt:11768.2] || -> xuntil6(s36)*. % 75.92/76.16 11777[51:MRR:140.0,11776.0] || -> until5(s37)*. % 75.92/76.16 11778[51:MRR:928.0,11777.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.16 11779[52:Spt:11778.1] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.16 11781[52:Res:11779.0,61.1] always3(s38) || -> . % 75.92/76.16 11782[52:SSi:11781.0,727.0] || -> . % 75.92/76.16 11783[52:Spt:11782.0,11778.1,11779.0] || m_main_v_state(s38,c_busy)*+ -> . % 75.92/76.16 11784[52:Spt:11782.0,11778.0,11778.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 75.92/76.16 11787[52:Res:53.1,11784.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 75.92/76.16 11792[53:Spt:11787.1] || -> xuntil6(s37)*. % 75.92/76.16 11793[53:MRR:139.0,11792.0] || -> until5(s38)*. % 75.92/76.16 11794[53:MRR:7488.0,11793.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.16 11796[54:Spt:11794.2] || -> xuntil6(s38)*. % 75.92/76.16 11797[54:MRR:138.0,11796.0] || -> until5(s39)*. % 75.92/76.16 11798[54:MRR:926.0,11797.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.16 11799[55:Spt:11798.1] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.16 11801[55:Res:11799.0,61.1] always3(s40) || -> . % 75.92/76.16 11802[55:SSi:11801.0,729.0] || -> . % 75.92/76.16 11803[55:Spt:11802.0,11798.1,11799.0] || m_main_v_state(s40,c_busy)*+ -> . % 75.92/76.16 11804[55:Spt:11802.0,11798.0,11798.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 75.92/76.16 11806[55:MRR:801.2,11803.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 75.92/76.16 11807[55:Res:53.1,11804.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 75.92/76.16 11809[56:Spt:11807.1] || -> xuntil6(s39)*. % 75.92/76.16 11810[56:MRR:137.0,11809.0] || -> until5(s40)*. % 75.92/76.16 11811[56:MRR:7492.0,11810.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.16 11816[57:Spt:11811.2] || -> xuntil6(s40)*. % 75.92/76.16 11817[57:MRR:136.0,11816.0] || -> until5(s41)*. % 75.92/76.16 11818[57:MRR:924.0,11817.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.16 11819[58:Spt:11818.1] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.16 11821[58:Res:11819.0,61.1] always3(s42) || -> . % 75.92/76.16 11822[58:SSi:11821.0,731.0] || -> . % 75.92/76.16 11823[58:Spt:11822.0,11818.1,11819.0] || m_main_v_state(s42,c_busy)*+ -> . % 75.92/76.16 11824[58:Spt:11822.0,11818.0,11818.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 75.92/76.16 11826[58:MRR:795.2,11823.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 75.92/76.16 11827[58:Res:53.1,11824.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 75.92/76.16 11829[59:Spt:11827.1] || -> xuntil6(s41)*. % 75.92/76.16 11830[59:MRR:135.0,11829.0] || -> until5(s42)*. % 75.92/76.16 11831[59:MRR:7496.0,11830.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.16 11839[60:Spt:11831.2] || -> xuntil6(s42)*. % 75.92/76.16 11840[60:MRR:134.0,11839.0] || -> until5(s43)*. % 75.92/76.16 11841[60:MRR:922.0,11840.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.16 11842[61:Spt:11841.1] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.16 11844[61:Res:11842.0,61.1] always3(s44) || -> . % 75.92/76.16 11845[61:SSi:11844.0,733.0] || -> . % 75.92/76.16 11846[61:Spt:11845.0,11841.1,11842.0] || m_main_v_state(s44,c_busy)*+ -> . % 75.92/76.16 11847[61:Spt:11845.0,11841.0,11841.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 75.92/76.16 11849[61:MRR:789.2,11846.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 75.92/76.16 11850[61:Res:53.1,11847.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 75.92/76.16 11855[62:Spt:11850.1] || -> xuntil6(s43)*. % 75.92/76.16 11856[62:MRR:133.0,11855.0] || -> until5(s44)*. % 75.92/76.16 11857[62:MRR:7503.0,11856.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.16 11859[63:Spt:11857.2] || -> xuntil6(s44)*. % 75.92/76.16 11860[63:MRR:132.0,11859.0] || -> until5(s45)*. % 75.92/76.16 11861[63:MRR:920.0,11860.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.16 11862[64:Spt:11861.1] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.16 11864[64:Res:11862.0,61.1] always3(s46) || -> . % 75.92/76.16 11865[64:SSi:11864.0,735.0] || -> . % 75.92/76.16 11866[64:Spt:11865.0,11861.1,11862.0] || m_main_v_state(s46,c_busy)*+ -> . % 75.92/76.16 11867[64:Spt:11865.0,11861.0,11861.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 75.92/76.16 11869[64:MRR:783.2,11866.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 75.92/76.16 11870[64:Res:53.1,11867.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 75.92/76.16 11872[65:Spt:11870.1] || -> xuntil6(s45)*. % 75.92/76.16 11873[65:MRR:131.0,11872.0] || -> until5(s46)*. % 75.92/76.16 11874[65:MRR:7504.0,11873.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.16 11879[66:Spt:11874.2] || -> xuntil6(s46)*. % 75.92/76.16 11880[66:MRR:130.0,11879.0] || -> until5(s47)*. % 75.92/76.16 11881[66:MRR:918.0,11880.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.16 11882[67:Spt:11881.1] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.16 11884[67:Res:11882.0,61.1] always3(s48) || -> . % 75.92/76.16 11885[67:SSi:11884.0,737.0] || -> . % 75.92/76.16 11886[67:Spt:11885.0,11881.1,11882.0] || m_main_v_state(s48,c_busy)*+ -> . % 75.92/76.16 11887[67:Spt:11885.0,11881.0,11881.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 75.92/76.16 11889[67:MRR:777.2,11886.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 75.92/76.16 11890[67:Res:53.1,11887.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 75.92/76.16 11892[68:Spt:11890.1] || -> xuntil6(s47)*. % 75.92/76.16 11893[68:MRR:129.0,11892.0] || -> until5(s48)*. % 75.92/76.16 11894[68:MRR:7508.0,11893.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.16 11902[69:Spt:11894.2] || -> xuntil6(s48)*. % 75.92/76.16 11903[69:MRR:128.0,11902.0] || -> until5(s49)*. % 75.92/76.16 11904[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.16 11905[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.16 11909[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.16 11910[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.16 11914[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.16 11918[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.16 11922[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.16 11929[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.16 11930[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.16 11934[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.16 11938[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.16 11942[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.16 11949[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.16 11950[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.16 11954[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.16 11958[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.16 11962[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.16 11969[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.16 11970[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.16 11974[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.16 11978[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.16 11982[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.16 11989[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.16 11990[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.16 11994[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.16 11998[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.16 12002[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.16 12009[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.16 12010[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.16 12014[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.16 12018[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.16 12022[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.16 12024[12:SoR:11588.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 75.92/76.16 12029[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.16 12033[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.16 12040[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.16 12041[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.16 12045[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.16 12049[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.16 12053[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.16 12057[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.16 12058[12:SoR:12024.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 75.92/76.16 12059[69:SSi:12058.0,50.0,738.0,11903.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 75.92/76.16 12060[70:Spt:12059.1] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.16 12062[70:Res:12060.0,61.1] always3(s39) || -> . % 75.92/76.16 12063[70:SSi:12062.0,728.0,11797.0,11809.0] || -> . % 75.92/76.16 12064[70:Spt:12063.0,12059.1,12060.0] || m_main_v_state(s39,c_busy)*+ -> . % 75.92/76.16 12065[70:Spt:12063.0,12059.0,12059.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.16 12069[70:MRR:12024.2,12064.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.16 12070[70:Res:53.1,12065.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.16 12072[71:Spt:12070.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.16 12074[71:Res:12072.0,61.1] always3(s49) || -> . % 75.92/76.16 12075[71:SSi:12074.0,50.0,738.0,11903.0] || -> . % 75.92/76.16 12076[71:Spt:12075.0,12070.0,12072.0] || m_main_v_state(s49,c_busy)*+ -> . % 75.92/76.16 12077[71:Spt:12075.0,12070.1] || -> xuntil6(s49)*. % 75.92/76.16 12078[71:MRR:11587.0,12077.0] || -> until2p7(s39)*. % 75.92/76.16 12079[71:MRR:237.0,12078.0] || -> until2p7(s40)* node4(s39). % 75.92/76.16 12081[71:MRR:774.2,12076.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 75.92/76.16 12082[72:Spt:12079.0] || -> until2p7(s40)*. % 75.92/76.16 12083[72:MRR:238.0,12082.0] || -> until2p7(s41)* node4(s40). % 75.92/76.16 12084[73:Spt:12083.0] || -> until2p7(s41)*. % 75.92/76.16 12085[73:MRR:239.0,12084.0] || -> until2p7(s42)* node4(s41). % 75.92/76.16 12086[74:Spt:12085.0] || -> until2p7(s42)*. % 75.92/76.16 12087[74:MRR:240.0,12086.0] || -> until2p7(s43)* node4(s42). % 75.92/76.16 12088[75:Spt:12087.0] || -> until2p7(s43)*. % 75.92/76.16 12089[75:MRR:241.0,12088.0] || -> until2p7(s44)* node4(s43). % 75.92/76.16 12090[76:Spt:12089.0] || -> until2p7(s44)*. % 75.92/76.16 12091[76:MRR:539.0,12090.0] || -> until2p7(s45)* node4(s44). % 75.92/76.16 12092[77:Spt:12091.0] || -> until2p7(s45)*. % 75.92/76.16 12093[77:MRR:544.0,12092.0] || -> until2p7(s46)* node4(s45). % 75.92/76.16 12094[78:Spt:12093.0] || -> until2p7(s46)*. % 75.92/76.16 12095[78:MRR:549.0,12094.0] || -> until2p7(s47)* node4(s46). % 75.92/76.16 12096[79:Spt:12095.0] || -> until2p7(s47)*. % 75.92/76.16 12097[79:MRR:554.0,12096.0] || -> until2p7(s48)* node4(s47). % 75.92/76.16 12098[80:Spt:12097.0] || -> until2p7(s48)*. % 75.92/76.16 12099[80:MRR:559.0,12098.0] || -> until2p7(s49)* node4(s48). % 75.92/76.16 12100[81:Spt:12099.0] || -> until2p7(s49)*. % 75.92/76.16 12101[81:MRR:194.0,12100.0] || -> node4(s49)*. % 75.92/76.16 12102[81:MRR:12069.0,12101.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.16 12103[81:Res:53.1,12102.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.16 12105[81:MRR:12103.0,12076.0] || -> . % 75.92/76.16 12106[81:Spt:12105.0,12099.0,12100.0] || until2p7(s49)*+ -> . % 75.92/76.16 12107[81:Spt:12105.0,12099.1] || -> node4(s48)*. % 75.92/76.16 12108[81:MRR:12081.0,12107.0] || m_main_v_state(s48,c_ready)*+ -> . % 75.92/76.16 12111[81:Res:53.1,12108.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.16 12113[81:MRR:12111.0,11886.0] || -> . % 75.92/76.16 12114[80:Spt:12113.0,12097.0,12098.0] || until2p7(s48)*+ -> . % 75.92/76.16 12115[80:Spt:12113.0,12097.1] || -> node4(s47)*. % 75.92/76.16 12116[80:MRR:11889.0,12115.0] || m_main_v_state(s47,c_ready)*+ -> . % 75.92/76.16 12119[80:Res:53.1,12116.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.16 12122[80:Res:12119.0,61.1] always3(s47) || -> . % 75.92/76.16 12123[80:SSi:12122.0,736.0,11880.0,11892.0,12096.0,12115.0] || -> . % 75.92/76.16 12124[79:Spt:12123.0,12095.0,12096.0] || until2p7(s47)*+ -> . % 75.92/76.16 12125[79:Spt:12123.0,12095.1] || -> node4(s46)*. % 75.92/76.16 12127[79:MRR:780.0,12125.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.16 12151[79:Res:53.1,12127.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.16 12153[79:MRR:12151.0,11866.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.16 12155[79:Res:12153.0,61.1] always3(s47) || -> . % 75.92/76.16 12156[79:SSi:12155.0,736.0,11880.0,11892.0] || -> . % 75.92/76.16 12157[78:Spt:12156.0,12093.0,12094.0] || until2p7(s46)*+ -> . % 75.92/76.16 12158[78:Spt:12156.0,12093.1] || -> node4(s45)*. % 75.92/76.16 12159[78:MRR:11869.0,12158.0] || m_main_v_state(s45,c_ready)*+ -> . % 75.92/76.16 12162[78:Res:53.1,12159.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.16 12165[78:Res:12162.0,61.1] always3(s45) || -> . % 75.92/76.16 12166[78:SSi:12165.0,734.0,11860.0,11872.0,12092.0,12158.0] || -> . % 75.92/76.16 12167[77:Spt:12166.0,12091.0,12092.0] || until2p7(s45)*+ -> . % 75.92/76.16 12168[77:Spt:12166.0,12091.1] || -> node4(s44)*. % 75.92/76.16 12170[77:MRR:786.0,12168.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.16 12182[77:Res:53.1,12170.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.16 12184[77:MRR:12182.0,11846.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.16 12189[77:Res:12184.0,61.1] always3(s45) || -> . % 75.92/76.16 12190[77:SSi:12189.0,734.0,11860.0,11872.0] || -> . % 75.92/76.16 12191[76:Spt:12190.0,12089.0,12090.0] || until2p7(s44)*+ -> . % 75.92/76.16 12192[76:Spt:12190.0,12089.1] || -> node4(s43)*. % 75.92/76.16 12193[76:MRR:11849.0,12192.0] || m_main_v_state(s43,c_ready)*+ -> . % 75.92/76.16 12196[76:Res:53.1,12193.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.16 12200[76:Res:12196.0,61.1] always3(s43) || -> . % 75.92/76.16 12201[76:SSi:12200.0,732.0,11840.0,11855.0,12088.0,12192.0] || -> . % 75.92/76.16 12202[75:Spt:12201.0,12087.0,12088.0] || until2p7(s43)*+ -> . % 75.92/76.16 12203[75:Spt:12201.0,12087.1] || -> node4(s42)*. % 75.92/76.16 12205[75:MRR:792.0,12203.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.16 12216[75:Res:53.1,12205.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.16 12218[75:MRR:12216.0,11823.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.16 12220[75:Res:12218.0,61.1] always3(s43) || -> . % 75.92/76.16 12221[75:SSi:12220.0,732.0,11840.0,11855.0] || -> . % 75.92/76.16 12222[74:Spt:12221.0,12085.0,12086.0] || until2p7(s42)*+ -> . % 75.92/76.16 12223[74:Spt:12221.0,12085.1] || -> node4(s41)*. % 75.92/76.16 12224[74:MRR:11826.0,12223.0] || m_main_v_state(s41,c_ready)*+ -> . % 75.92/76.16 12228[74:Res:53.1,12224.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.16 12231[74:Res:12228.0,61.1] always3(s41) || -> . % 75.92/76.16 12232[74:SSi:12231.0,730.0,11817.0,11829.0,12084.0,12223.0] || -> . % 75.92/76.16 12233[73:Spt:12232.0,12083.0,12084.0] || until2p7(s41)*+ -> . % 75.92/76.16 12234[73:Spt:12232.0,12083.1] || -> node4(s40)*. % 75.92/76.16 12236[73:MRR:798.0,12234.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.16 12247[73:Res:53.1,12236.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.16 12249[73:MRR:12247.0,11803.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.16 12251[73:Res:12249.0,61.1] always3(s41) || -> . % 75.92/76.16 12252[73:SSi:12251.0,730.0,11817.0,11829.0] || -> . % 75.92/76.16 12253[72:Spt:12252.0,12079.0,12082.0] || until2p7(s40)*+ -> . % 75.92/76.16 12254[72:Spt:12252.0,12079.1] || -> node4(s39)*. % 75.92/76.16 12255[72:MRR:11806.0,12254.0] || m_main_v_state(s39,c_ready)*+ -> . % 75.92/76.16 12258[72:Res:53.1,12255.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.16 12260[72:MRR:12258.0,12064.0] || -> . % 75.92/76.16 12261[69:Spt:12260.0,11894.2,11902.0] || xuntil6(s48)*+ -> . % 75.92/76.16 12262[69:Spt:12260.0,11894.0,11894.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.16 12263[69:Res:53.1,12262.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.16 12265[69:MRR:12263.0,11886.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.16 12267[69:Res:12265.0,61.1] always3(s49) || -> . % 75.92/76.16 12268[69:SSi:12267.0,50.0,738.0] || -> . % 75.92/76.16 12269[68:Spt:12268.0,11890.1,11892.0] || xuntil6(s47)* -> . % 75.92/76.16 12270[68:Spt:12268.0,11890.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.16 12273[68:Res:12270.0,61.1] always3(s47) || -> . % 75.92/76.16 12274[68:SSi:12273.0,736.0,11880.0] || -> . % 75.92/76.16 12275[66:Spt:12274.0,11874.2,11879.0] || xuntil6(s46)*+ -> . % 75.92/76.16 12276[66:Spt:12274.0,11874.0,11874.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.16 12277[66:Res:53.1,12276.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.16 12279[66:MRR:12277.0,11866.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.16 12282[66:Res:12279.0,61.1] always3(s47) || -> . % 75.92/76.16 12283[66:SSi:12282.0,736.0] || -> . % 75.92/76.16 12284[65:Spt:12283.0,11870.1,11872.0] || xuntil6(s45)* -> . % 75.92/76.16 12285[65:Spt:12283.0,11870.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.16 12288[65:Res:12285.0,61.1] always3(s45) || -> . % 75.92/76.16 12289[65:SSi:12288.0,734.0,11860.0] || -> . % 75.92/76.16 12290[63:Spt:12289.0,11857.2,11859.0] || xuntil6(s44)*+ -> . % 75.92/76.16 12291[63:Spt:12289.0,11857.0,11857.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.16 12292[63:Res:53.1,12291.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.16 12294[63:MRR:12292.0,11846.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.16 12296[63:Res:12294.0,61.1] always3(s45) || -> . % 75.92/76.16 12297[63:SSi:12296.0,734.0] || -> . % 75.92/76.16 12298[62:Spt:12297.0,11850.1,11855.0] || xuntil6(s43)* -> . % 75.92/76.16 12299[62:Spt:12297.0,11850.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.16 12302[62:Res:12299.0,61.1] always3(s43) || -> . % 75.92/76.16 12303[62:SSi:12302.0,732.0,11840.0] || -> . % 75.92/76.16 12304[60:Spt:12303.0,11831.2,11839.0] || xuntil6(s42)*+ -> . % 75.92/76.16 12305[60:Spt:12303.0,11831.0,11831.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.16 12306[60:Res:53.1,12305.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.16 12308[60:MRR:12306.0,11823.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.16 12311[60:Res:12308.0,61.1] always3(s43) || -> . % 75.92/76.16 12312[60:SSi:12311.0,732.0] || -> . % 75.92/76.16 12313[59:Spt:12312.0,11827.1,11829.0] || xuntil6(s41)* -> . % 75.92/76.16 12314[59:Spt:12312.0,11827.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.16 12317[59:Res:12314.0,61.1] always3(s41) || -> . % 75.92/76.16 12318[59:SSi:12317.0,730.0,11817.0] || -> . % 75.92/76.16 12319[57:Spt:12318.0,11811.2,11816.0] || xuntil6(s40)*+ -> . % 75.92/76.16 12320[57:Spt:12318.0,11811.0,11811.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.16 12321[57:Res:53.1,12320.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.16 12323[57:MRR:12321.0,11803.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.16 12325[57:Res:12323.0,61.1] always3(s41) || -> . % 75.92/76.16 12326[57:SSi:12325.0,730.0] || -> . % 75.92/76.16 12327[56:Spt:12326.0,11807.1,11809.0] || xuntil6(s39)* -> . % 75.92/76.16 12328[56:Spt:12326.0,11807.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.16 12331[56:Res:12328.0,61.1] always3(s39) || -> . % 75.92/76.16 12332[56:SSi:12331.0,728.0,11797.0] || -> . % 75.92/76.16 12333[54:Spt:12332.0,11794.2,11796.0] || xuntil6(s38)*+ -> . % 75.92/76.16 12334[54:Spt:12332.0,11794.0,11794.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.16 12335[54:Res:53.1,12334.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.16 12337[54:MRR:12335.0,11783.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.16 12340[54:Res:12337.0,61.1] always3(s39) || -> . % 75.92/76.16 12341[54:SSi:12340.0,728.0] || -> . % 75.92/76.16 12342[53:Spt:12341.0,11787.1,11792.0] || xuntil6(s37)* -> . % 75.92/76.16 12343[53:Spt:12341.0,11787.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.16 12346[53:Res:12343.0,61.1] always3(s37) || -> . % 75.92/76.16 12347[53:SSi:12346.0,726.0,11777.0] || -> . % 75.92/76.16 12348[51:Spt:12347.0,11768.2,11776.0] || xuntil6(s36)*+ -> . % 75.92/76.16 12349[51:Spt:12347.0,11768.0,11768.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.16 12350[51:Res:53.1,12349.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.16 12352[51:MRR:12350.0,11760.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.16 12354[51:Res:12352.0,61.1] always3(s37) || -> . % 75.92/76.16 12355[51:SSi:12354.0,726.0] || -> . % 75.92/76.16 12356[50:Spt:12355.0,11764.1,11766.0] || xuntil6(s35)* -> . % 75.92/76.16 12357[50:Spt:12355.0,11764.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.16 12360[50:Res:12357.0,61.1] always3(s35) || -> . % 75.92/76.16 12361[50:SSi:12360.0,724.0,11754.0] || -> . % 75.92/76.16 12362[48:Spt:12361.0,11748.2,11753.0] || xuntil6(s34)*+ -> . % 75.92/76.16 12363[48:Spt:12361.0,11748.0,11748.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 75.92/76.16 12364[48:Res:53.1,12363.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 75.92/76.16 12366[48:MRR:12364.0,11740.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.16 12368[48:Res:12366.0,61.1] always3(s35) || -> . % 75.92/76.16 12369[48:SSi:12368.0,724.0] || -> . % 75.92/76.16 12370[47:Spt:12369.0,11744.1,11746.0] || xuntil6(s33)* -> . % 75.92/76.16 12371[47:Spt:12369.0,11744.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.16 12374[47:Res:12371.0,61.1] always3(s33) || -> . % 75.92/76.16 12375[47:SSi:12374.0,722.0,11731.0] || -> . % 75.92/76.16 12376[45:Spt:12375.0,11729.2,11730.0] || xuntil6(s32)*+ -> . % 75.92/76.16 12377[45:Spt:12375.0,11729.0,11729.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 75.92/76.16 12378[45:Res:53.1,12377.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 75.92/76.16 12380[46:Spt:12378.0] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.16 12382[46:Res:12380.0,61.1] always3(s32) || -> . % 75.92/76.16 12383[46:SSi:12382.0,721.0,11728.0] || -> . % 75.92/76.16 12384[46:Spt:12383.0,12378.0,12380.0] || m_main_v_state(s32,c_busy)* -> . % 75.92/76.16 12385[46:Spt:12383.0,12378.1] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.16 12389[46:Res:12385.0,61.1] always3(s33) || -> . % 75.92/76.16 12390[46:SSi:12389.0,722.0] || -> . % 75.92/76.16 12391[44:Spt:12390.0,11723.2,11727.0] || xuntil6(s31)*+ -> . % 75.92/76.16 12392[44:Spt:12390.0,11723.0,11723.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 75.92/76.16 12393[44:Res:53.1,12392.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 75.92/76.16 12395[45:Spt:12393.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.16 12397[45:Res:12395.0,61.1] always3(s31) || -> . % 75.92/76.16 12398[45:SSi:12397.0,720.0,11722.0] || -> . % 75.92/76.16 12399[45:Spt:12398.0,12393.0,12395.0] || m_main_v_state(s31,c_busy)* -> . % 75.92/76.16 12400[45:Spt:12398.0,12393.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.16 12404[45:Res:12400.0,61.1] always3(s32) || -> . % 75.92/76.16 12405[45:SSi:12404.0,721.0] || -> . % 75.92/76.16 12406[43:Spt:12405.0,11720.2,11721.0] || xuntil6(s30)*+ -> . % 75.92/76.16 12407[43:Spt:12405.0,11720.0,11720.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.16 12408[43:Res:53.1,12407.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.16 12410[44:Spt:12408.0] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.16 12412[44:Res:12410.0,61.1] always3(s30) || -> . % 75.92/76.16 12413[44:SSi:12412.0,719.0,11719.0] || -> . % 75.92/76.16 12414[44:Spt:12413.0,12408.0,12410.0] || m_main_v_state(s30,c_busy)* -> . % 75.92/76.16 12415[44:Spt:12413.0,12408.1] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.16 12419[44:Res:12415.0,61.1] always3(s31) || -> . % 75.92/76.16 12420[44:SSi:12419.0,720.0] || -> . % 75.92/76.16 12421[42:Spt:12420.0,11714.2,11718.0] || xuntil6(s29)*+ -> . % 75.92/76.16 12422[42:Spt:12420.0,11714.0,11714.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 75.92/76.16 12423[42:Res:53.1,12422.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 75.92/76.16 12425[43:Spt:12423.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.16 12427[43:Res:12425.0,61.1] always3(s29) || -> . % 75.92/76.16 12428[43:SSi:12427.0,718.0,11713.0] || -> . % 75.92/76.16 12429[43:Spt:12428.0,12423.0,12425.0] || m_main_v_state(s29,c_busy)* -> . % 75.92/76.16 12430[43:Spt:12428.0,12423.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.16 12434[43:Res:12430.0,61.1] always3(s30) || -> . % 75.92/76.16 12435[43:SSi:12434.0,719.0] || -> . % 75.92/76.16 12436[41:Spt:12435.0,11711.2,11712.0] || xuntil6(s28)*+ -> . % 75.92/76.16 12437[41:Spt:12435.0,11711.0,11711.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.16 12438[41:Res:53.1,12437.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.16 12440[42:Spt:12438.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.16 12442[42:Res:12440.0,61.1] always3(s28) || -> . % 75.92/76.16 12443[42:SSi:12442.0,717.0,11710.0] || -> . % 75.92/76.16 12444[42:Spt:12443.0,12438.0,12440.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.16 12445[42:Spt:12443.0,12438.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.16 12449[42:Res:12445.0,61.1] always3(s29) || -> . % 75.92/76.16 12450[42:SSi:12449.0,718.0] || -> . % 75.92/76.16 12451[40:Spt:12450.0,11705.2,11709.0] || xuntil6(s27)*+ -> . % 75.92/76.16 12452[40:Spt:12450.0,11705.0,11705.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.16 12453[40:Res:53.1,12452.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.16 12455[41:Spt:12453.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.16 12457[41:Res:12455.0,61.1] always3(s27) || -> . % 75.92/76.16 12458[41:SSi:12457.0,716.0,11704.0] || -> . % 75.92/76.16 12459[41:Spt:12458.0,12453.0,12455.0] || m_main_v_state(s27,c_busy)* -> . % 75.92/76.16 12460[41:Spt:12458.0,12453.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.16 12464[41:Res:12460.0,61.1] always3(s28) || -> . % 75.92/76.16 12465[41:SSi:12464.0,717.0] || -> . % 75.92/76.16 12466[39:Spt:12465.0,11702.2,11703.0] || xuntil6(s26)*+ -> . % 75.92/76.16 12467[39:Spt:12465.0,11702.0,11702.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.16 12468[39:Res:53.1,12467.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.16 12470[40:Spt:12468.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.16 12472[40:Res:12470.0,61.1] always3(s26) || -> . % 75.92/76.16 12473[40:SSi:12472.0,715.0,11701.0] || -> . % 75.92/76.16 12474[40:Spt:12473.0,12468.0,12470.0] || m_main_v_state(s26,c_busy)* -> . % 75.92/76.16 12475[40:Spt:12473.0,12468.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.16 12479[40:Res:12475.0,61.1] always3(s27) || -> . % 75.92/76.16 12480[40:SSi:12479.0,716.0] || -> . % 75.92/76.16 12481[38:Spt:12480.0,11696.2,11700.0] || xuntil6(s25)*+ -> . % 75.92/76.16 12482[38:Spt:12480.0,11696.0,11696.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.16 12483[38:Res:53.1,12482.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.16 12485[39:Spt:12483.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.16 12487[39:Res:12485.0,61.1] always3(s25) || -> . % 75.92/76.16 12488[39:SSi:12487.0,714.0,11695.0] || -> . % 75.92/76.16 12489[39:Spt:12488.0,12483.0,12485.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.16 12490[39:Spt:12488.0,12483.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.16 12494[39:Res:12490.0,61.1] always3(s26) || -> . % 75.92/76.16 12495[39:SSi:12494.0,715.0] || -> . % 75.92/76.16 12496[37:Spt:12495.0,11693.2,11694.0] || xuntil6(s24)*+ -> . % 75.92/76.16 12497[37:Spt:12495.0,11693.0,11693.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.16 12498[37:Res:53.1,12497.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.16 12500[38:Spt:12498.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.16 12502[38:Res:12500.0,61.1] always3(s24) || -> . % 75.92/76.16 12503[38:SSi:12502.0,713.0,11692.0] || -> . % 75.92/76.16 12504[38:Spt:12503.0,12498.0,12500.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.16 12505[38:Spt:12503.0,12498.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.16 12509[38:Res:12505.0,61.1] always3(s25) || -> . % 75.92/76.16 12510[38:SSi:12509.0,714.0] || -> . % 75.92/76.16 12511[36:Spt:12510.0,11687.2,11691.0] || xuntil6(s23)*+ -> . % 75.92/76.16 12512[36:Spt:12510.0,11687.0,11687.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.16 12513[36:Res:53.1,12512.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.16 12518[37:Spt:12513.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.16 12520[37:Res:12518.0,61.1] always3(s23) || -> . % 75.92/76.16 12521[37:SSi:12520.0,712.0,11686.0] || -> . % 75.92/76.16 12522[37:Spt:12521.0,12513.0,12518.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.16 12523[37:Spt:12521.0,12513.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.16 12527[37:Res:12523.0,61.1] always3(s24) || -> . % 75.92/76.16 12528[37:SSi:12527.0,713.0] || -> . % 75.92/76.16 12529[35:Spt:12528.0,11684.2,11685.0] || xuntil6(s22)*+ -> . % 75.92/76.16 12530[35:Spt:12528.0,11684.0,11684.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.16 12531[35:Res:53.1,12530.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.16 12533[36:Spt:12531.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.16 12535[36:Res:12533.0,61.1] always3(s22) || -> . % 75.92/76.16 12536[36:SSi:12535.0,711.0,11683.0] || -> . % 75.92/76.16 12537[36:Spt:12536.0,12531.0,12533.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.16 12538[36:Spt:12536.0,12531.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.16 12542[36:Res:12538.0,61.1] always3(s23) || -> . % 75.92/76.16 12543[36:SSi:12542.0,712.0] || -> . % 75.92/76.16 12544[34:Spt:12543.0,11678.2,11682.0] || xuntil6(s21)*+ -> . % 75.92/76.16 12545[34:Spt:12543.0,11678.0,11678.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.16 12546[34:Res:53.1,12545.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.16 12548[35:Spt:12546.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.16 12550[35:Res:12548.0,61.1] always3(s21) || -> . % 75.92/76.16 12551[35:SSi:12550.0,710.0,11677.0] || -> . % 75.92/76.16 12552[35:Spt:12551.0,12546.0,12548.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.16 12553[35:Spt:12551.0,12546.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.16 12557[35:Res:12553.0,61.1] always3(s22) || -> . % 75.92/76.16 12558[35:SSi:12557.0,711.0] || -> . % 75.92/76.16 12559[33:Spt:12558.0,11675.2,11676.0] || xuntil6(s20)*+ -> . % 75.92/76.16 12560[33:Spt:12558.0,11675.0,11675.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.16 12561[33:Res:53.1,12560.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.16 12566[34:Spt:12561.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.16 12568[34:Res:12566.0,61.1] always3(s20) || -> . % 75.92/76.16 12569[34:SSi:12568.0,709.0,11674.0] || -> . % 75.92/76.16 12570[34:Spt:12569.0,12561.0,12566.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.16 12571[34:Spt:12569.0,12561.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.16 12575[34:Res:12571.0,61.1] always3(s21) || -> . % 75.92/76.16 12576[34:SSi:12575.0,710.0] || -> . % 75.92/76.16 12577[32:Spt:12576.0,11669.2,11673.0] || xuntil6(s19)*+ -> . % 75.92/76.16 12578[32:Spt:12576.0,11669.0,11669.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.16 12579[32:Res:53.1,12578.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.16 12581[33:Spt:12579.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.16 12583[33:Res:12581.0,61.1] always3(s19) || -> . % 75.92/76.16 12584[33:SSi:12583.0,708.0,11668.0] || -> . % 75.92/76.16 12585[33:Spt:12584.0,12579.0,12581.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.16 12586[33:Spt:12584.0,12579.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.16 12590[33:Res:12586.0,61.1] always3(s20) || -> . % 75.92/76.16 12591[33:SSi:12590.0,709.0] || -> . % 75.92/76.16 12592[31:Spt:12591.0,11666.2,11667.0] || xuntil6(s18)*+ -> . % 75.92/76.16 12593[31:Spt:12591.0,11666.0,11666.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.16 12594[31:Res:53.1,12593.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.16 12596[32:Spt:12594.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.16 12598[32:Res:12596.0,61.1] always3(s18) || -> . % 75.92/76.16 12599[32:SSi:12598.0,707.0,11665.0] || -> . % 75.92/76.16 12600[32:Spt:12599.0,12594.0,12596.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.16 12601[32:Spt:12599.0,12594.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.16 12605[32:Res:12601.0,61.1] always3(s19) || -> . % 75.92/76.16 12606[32:SSi:12605.0,708.0] || -> . % 75.92/76.16 12607[30:Spt:12606.0,11660.2,11664.0] || xuntil6(s17)*+ -> . % 75.92/76.16 12608[30:Spt:12606.0,11660.0,11660.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.16 12609[30:Res:53.1,12608.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.16 12614[31:Spt:12609.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.16 12616[31:Res:12614.0,61.1] always3(s17) || -> . % 75.92/76.16 12617[31:SSi:12616.0,706.0,11659.0] || -> . % 75.92/76.16 12618[31:Spt:12617.0,12609.0,12614.0] || m_main_v_state(s17,c_busy)* -> . % 75.92/76.16 12619[31:Spt:12617.0,12609.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.16 12623[31:Res:12619.0,61.1] always3(s18) || -> . % 75.92/76.16 12624[31:SSi:12623.0,707.0] || -> . % 75.92/76.16 12625[29:Spt:12624.0,11657.2,11658.0] || xuntil6(s16)*+ -> . % 75.92/76.16 12626[29:Spt:12624.0,11657.0,11657.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.16 12627[29:Res:53.1,12626.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.16 12629[30:Spt:12627.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.16 12631[30:Res:12629.0,61.1] always3(s16) || -> . % 75.92/76.16 12632[30:SSi:12631.0,705.0,11656.0] || -> . % 75.92/76.16 12633[30:Spt:12632.0,12627.0,12629.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.16 12634[30:Spt:12632.0,12627.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.16 12638[30:Res:12634.0,61.1] always3(s17) || -> . % 75.92/76.16 12639[30:SSi:12638.0,706.0] || -> . % 75.92/76.16 12640[28:Spt:12639.0,11651.2,11655.0] || xuntil6(s15)*+ -> . % 75.92/76.16 12641[28:Spt:12639.0,11651.0,11651.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.16 12642[28:Res:53.1,12641.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.16 12644[29:Spt:12642.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.16 12646[29:Res:12644.0,61.1] always3(s15) || -> . % 75.92/76.16 12647[29:SSi:12646.0,704.0,11650.0] || -> . % 75.92/76.16 12648[29:Spt:12647.0,12642.0,12644.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.16 12649[29:Spt:12647.0,12642.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.16 12653[29:Res:12649.0,61.1] always3(s16) || -> . % 75.92/76.16 12654[29:SSi:12653.0,705.0] || -> . % 75.92/76.16 12655[27:Spt:12654.0,11648.2,11649.0] || xuntil6(s14)*+ -> . % 75.92/76.16 12656[27:Spt:12654.0,11648.0,11648.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.16 12657[27:Res:53.1,12656.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.16 12662[28:Spt:12657.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.16 12664[28:Res:12662.0,61.1] always3(s14) || -> . % 75.92/76.16 12665[28:SSi:12664.0,703.0,11647.0] || -> . % 75.92/76.16 12666[28:Spt:12665.0,12657.0,12662.0] || m_main_v_state(s14,c_busy)* -> . % 75.92/76.16 12667[28:Spt:12665.0,12657.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.16 12671[28:Res:12667.0,61.1] always3(s15) || -> . % 75.92/76.16 12672[28:SSi:12671.0,704.0] || -> . % 75.92/76.16 12673[26:Spt:12672.0,11642.2,11646.0] || xuntil6(s13)*+ -> . % 75.92/76.16 12674[26:Spt:12672.0,11642.0,11642.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.16 12675[26:Res:53.1,12674.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.16 12677[27:Spt:12675.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.16 12679[27:Res:12677.0,61.1] always3(s13) || -> . % 75.92/76.16 12680[27:SSi:12679.0,702.0,11641.0] || -> . % 75.92/76.16 12681[27:Spt:12680.0,12675.0,12677.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.16 12682[27:Spt:12680.0,12675.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.16 12686[27:Res:12682.0,61.1] always3(s14) || -> . % 75.92/76.16 12687[27:SSi:12686.0,703.0] || -> . % 75.92/76.16 12688[25:Spt:12687.0,11639.2,11640.0] || xuntil6(s12)*+ -> . % 75.92/76.16 12689[25:Spt:12687.0,11639.0,11639.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.16 12690[25:Res:53.1,12689.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.16 12692[26:Spt:12690.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.16 12694[26:Res:12692.0,61.1] always3(s12) || -> . % 75.92/76.16 12695[26:SSi:12694.0,701.0,11638.0] || -> . % 75.92/76.16 12696[26:Spt:12695.0,12690.0,12692.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.16 12697[26:Spt:12695.0,12690.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.16 12701[26:Res:12697.0,61.1] always3(s13) || -> . % 75.92/76.16 12702[26:SSi:12701.0,702.0] || -> . % 75.92/76.16 12703[24:Spt:12702.0,11633.2,11637.0] || xuntil6(s11)*+ -> . % 75.92/76.16 12704[24:Spt:12702.0,11633.0,11633.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.16 12705[24:Res:53.1,12704.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.16 12710[25:Spt:12705.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.16 12712[25:Res:12710.0,61.1] always3(s11) || -> . % 75.92/76.16 12713[25:SSi:12712.0,700.0,11632.0] || -> . % 75.92/76.16 12714[25:Spt:12713.0,12705.0,12710.0] || m_main_v_state(s11,c_busy)* -> . % 75.92/76.16 12715[25:Spt:12713.0,12705.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.16 12719[25:Res:12715.0,61.1] always3(s12) || -> . % 75.92/76.16 12720[25:SSi:12719.0,701.0] || -> . % 75.92/76.16 12721[23:Spt:12720.0,11630.2,11631.0] || xuntil6(s10)*+ -> . % 75.92/76.16 12722[23:Spt:12720.0,11630.0,11630.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.16 12723[23:Res:53.1,12722.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.16 12725[24:Spt:12723.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.16 12727[24:Res:12725.0,61.1] always3(s10) || -> . % 75.92/76.16 12728[24:SSi:12727.0,699.0,11629.0] || -> . % 75.92/76.16 12729[24:Spt:12728.0,12723.0,12725.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.16 12730[24:Spt:12728.0,12723.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.16 12734[24:Res:12730.0,61.1] always3(s11) || -> . % 75.92/76.16 12735[24:SSi:12734.0,700.0] || -> . % 75.92/76.16 12736[22:Spt:12735.0,11624.2,11628.0] || xuntil6(s9)*+ -> . % 75.92/76.16 12737[22:Spt:12735.0,11624.0,11624.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.16 12738[22:Res:53.1,12737.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.16 12740[23:Spt:12738.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.16 12742[23:Res:12740.0,61.1] always3(s9) || -> . % 75.92/76.16 12743[23:SSi:12742.0,698.0,11623.0] || -> . % 75.92/76.16 12744[23:Spt:12743.0,12738.0,12740.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.16 12745[23:Spt:12743.0,12738.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.16 12749[23:Res:12745.0,61.1] always3(s10) || -> . % 75.92/76.16 12750[23:SSi:12749.0,699.0] || -> . % 75.92/76.16 12751[21:Spt:12750.0,11621.2,11622.0] || xuntil6(s8)*+ -> . % 75.92/76.16 12752[21:Spt:12750.0,11621.0,11621.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.16 12753[21:Res:53.1,12752.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.16 12758[22:Spt:12753.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.16 12760[22:Res:12758.0,61.1] always3(s8) || -> . % 75.92/76.16 12761[22:SSi:12760.0,697.0,11620.0] || -> . % 75.92/76.16 12762[22:Spt:12761.0,12753.0,12758.0] || m_main_v_state(s8,c_busy)* -> . % 75.92/76.16 12763[22:Spt:12761.0,12753.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.16 12767[22:Res:12763.0,61.1] always3(s9) || -> . % 75.92/76.16 12768[22:SSi:12767.0,698.0] || -> . % 75.92/76.16 12769[20:Spt:12768.0,11615.2,11619.0] || xuntil6(s7)*+ -> . % 75.92/76.16 12770[20:Spt:12768.0,11615.0,11615.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.16 12771[20:Res:53.1,12770.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.16 12773[21:Spt:12771.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.16 12775[21:Res:12773.0,61.1] always3(s7) || -> . % 75.92/76.16 12776[21:SSi:12775.0,696.0,11614.0] || -> . % 75.92/76.16 12777[21:Spt:12776.0,12771.0,12773.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.16 12778[21:Spt:12776.0,12771.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.16 12782[21:Res:12778.0,61.1] always3(s8) || -> . % 75.92/76.16 12783[21:SSi:12782.0,697.0] || -> . % 75.92/76.16 12784[19:Spt:12783.0,11612.2,11613.0] || xuntil6(s6)*+ -> . % 75.92/76.16 12785[19:Spt:12783.0,11612.0,11612.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.16 12786[19:Res:53.1,12785.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.16 12788[20:Spt:12786.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.16 12790[20:Res:12788.0,61.1] always3(s6) || -> . % 75.92/76.16 12791[20:SSi:12790.0,695.0,11611.0] || -> . % 75.92/76.16 12792[20:Spt:12791.0,12786.0,12788.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.16 12793[20:Spt:12791.0,12786.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.16 12797[20:Res:12793.0,61.1] always3(s7) || -> . % 75.92/76.16 12798[20:SSi:12797.0,696.0] || -> . % 75.92/76.16 12799[18:Spt:12798.0,11606.2,11610.0] || xuntil6(s5)*+ -> . % 75.92/76.16 12800[18:Spt:12798.0,11606.0,11606.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.16 12801[18:Res:53.1,12800.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.16 12806[19:Spt:12801.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.16 12808[19:Res:12806.0,61.1] always3(s5) || -> . % 75.92/76.16 12809[19:SSi:12808.0,694.0,11605.0] || -> . % 75.92/76.16 12810[19:Spt:12809.0,12801.0,12806.0] || m_main_v_state(s5,c_busy)* -> . % 75.92/76.16 12811[19:Spt:12809.0,12801.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.16 12815[19:Res:12811.0,61.1] always3(s6) || -> . % 75.92/76.16 12816[19:SSi:12815.0,695.0] || -> . % 75.92/76.16 12817[17:Spt:12816.0,11603.2,11604.0] || xuntil6(s4)*+ -> . % 75.92/76.16 12818[17:Spt:12816.0,11603.0,11603.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.16 12819[17:Res:53.1,12818.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.16 12821[18:Spt:12819.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.16 12823[18:Res:12821.0,61.1] always3(s4) || -> . % 75.92/76.16 12824[18:SSi:12823.0,693.0,11602.0] || -> . % 75.92/76.16 12825[18:Spt:12824.0,12819.0,12821.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.16 12826[18:Spt:12824.0,12819.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.16 12830[18:Res:12826.0,61.1] always3(s5) || -> . % 75.92/76.16 12831[18:SSi:12830.0,694.0] || -> . % 75.92/76.16 12832[16:Spt:12831.0,11600.2,11601.0] || xuntil6(s3)*+ -> . % 75.92/76.16 12833[16:Spt:12831.0,11600.0,11600.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.16 12834[16:Res:53.1,12833.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.16 12836[17:Spt:12834.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.16 12838[17:Res:12836.0,61.1] always3(s3) || -> . % 75.92/76.16 12839[17:SSi:12838.0,692.0,11599.0] || -> . % 75.92/76.16 12840[17:Spt:12839.0,12834.0,12836.0] || m_main_v_state(s3,c_busy)* -> . % 75.92/76.16 12841[17:Spt:12839.0,12834.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.16 12845[17:Res:12841.0,61.1] always3(s4) || -> . % 75.92/76.16 12846[17:SSi:12845.0,693.0] || -> . % 75.92/76.16 12847[15:Spt:12846.0,11597.2,11598.0] || xuntil6(s2)*+ -> . % 75.92/76.16 12848[15:Spt:12846.0,11597.0,11597.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.16 12849[15:Res:53.1,12848.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.16 12854[16:Spt:12849.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.16 12856[16:Res:12854.0,61.1] always3(s2) || -> . % 75.92/76.16 12857[16:SSi:12856.0,691.0,11596.0] || -> . % 75.92/76.16 12858[16:Spt:12857.0,12849.0,12854.0] || m_main_v_state(s2,c_busy)* -> . % 75.92/76.16 12859[16:Spt:12857.0,12849.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.16 12863[16:Res:12859.0,61.1] always3(s3) || -> . % 75.92/76.16 12864[16:SSi:12863.0,692.0] || -> . % 75.92/76.16 12865[14:Spt:12864.0,11591.2,11595.0] || xuntil6(s1)*+ -> . % 75.92/76.16 12866[14:Spt:12864.0,11591.0,11591.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.16 12867[14:Res:53.1,12866.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.16 12869[15:Spt:12867.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.16 12871[15:Res:12869.0,61.1] always3(s1) || -> . % 75.92/76.16 12872[15:SSi:12871.0,690.0,11590.0] || -> . % 75.92/76.16 12873[15:Spt:12872.0,12867.0,12869.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.16 12874[15:Spt:12872.0,12867.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.16 12879[15:Res:12874.0,61.1] always3(s2) || -> . % 75.92/76.16 12880[15:SSi:12879.0,691.0] || -> . % 75.92/76.16 12881[13:Spt:12880.0,74.0,11589.0] || xuntil6(s0)*+ -> . % 75.92/76.16 12882[13:Spt:12880.0,74.1] || -> node4(s0)*. % 75.92/76.16 12883[13:MRR:758.1,12881.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.16 12885[13:Res:12883.0,61.1] always3(s1) || -> . % 75.92/76.16 12886[13:SSi:12885.0,690.0] || -> . % 75.92/76.16 12887[12:Spt:12886.0,11579.0,11583.0] || trans(s49,s39)*+ -> . % 75.92/76.16 12888[12:Spt:12886.0,11579.1,11579.2,11579.3,11579.4,11579.5,11579.6,11579.7,11579.8,11579.9,11579.10,11579.11,11579.12,11579.13,11579.14,11579.15,11579.16,11579.17,11579.18,11579.19,11579.20,11579.21,11579.22,11579.23,11579.24,11579.25,11579.26,11579.27,11579.28,11579.29,11579.30,11579.31,11579.32,11579.33,11579.34,11579.35,11579.36,11579.37,11579.38,11579.39] || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.16 12889[12:MRR:11581.0,12887.0] || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.16 12891[12:MRR:11582.1,12887.0] xuntil6(s49) || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.16 12892[13:Spt:12888.0] || -> trans(s49,s38)*. % 75.92/76.16 12893[13:Res:12892.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s38)*. % 75.92/76.16 12895[13:Res:12892.0,60.0] || -> node2(s49,s38)*. % 75.92/76.16 12896[13:SSi:12893.1,50.0,738.0] xuntil6(s49) || -> until2p7(s38)*. % 75.92/76.16 12897[13:Res:12895.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)*. % 75.92/76.16 12898[14:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.16 12899[14:MRR:176.0,12898.0] || -> until5(s1)*. % 75.92/76.16 12900[14:MRR:12022.0,12899.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.16 12907[15:Spt:12900.2] || -> xuntil6(s1)*. % 75.92/76.16 12908[15:MRR:175.0,12907.0] || -> until5(s2)*. % 75.92/76.16 12909[15:MRR:12018.0,12908.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.16 12910[16:Spt:12909.2] || -> xuntil6(s2)*. % 75.92/76.16 12911[16:MRR:174.0,12910.0] || -> until5(s3)*. % 75.92/76.16 12912[16:MRR:12014.0,12911.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.16 12916[17:Spt:12912.2] || -> xuntil6(s3)*. % 75.92/76.16 12917[17:MRR:173.0,12916.0] || -> until5(s4)*. % 75.92/76.16 12918[17:MRR:12010.0,12917.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.16 12919[18:Spt:12918.2] || -> xuntil6(s4)*. % 75.92/76.16 12920[18:MRR:172.0,12919.0] || -> until5(s5)*. % 75.92/76.16 12921[18:MRR:12009.0,12920.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.16 12925[19:Spt:12921.2] || -> xuntil6(s5)*. % 75.92/76.16 12926[19:MRR:171.0,12925.0] || -> until5(s6)*. % 75.92/76.16 12927[19:MRR:12002.0,12926.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.16 12928[20:Spt:12927.2] || -> xuntil6(s6)*. % 75.92/76.16 12929[20:MRR:170.0,12928.0] || -> until5(s7)*. % 75.92/76.16 12930[20:MRR:11998.0,12929.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.16 12934[21:Spt:12930.2] || -> xuntil6(s7)*. % 75.92/76.16 12935[21:MRR:169.0,12934.0] || -> until5(s8)*. % 75.92/76.16 12936[21:MRR:11994.0,12935.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.16 12937[22:Spt:12936.2] || -> xuntil6(s8)*. % 75.92/76.16 12938[22:MRR:168.0,12937.0] || -> until5(s9)*. % 75.92/76.16 12939[22:MRR:11990.0,12938.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.16 12943[23:Spt:12939.2] || -> xuntil6(s9)*. % 75.92/76.16 12944[23:MRR:167.0,12943.0] || -> until5(s10)*. % 75.92/76.16 12945[23:MRR:11989.0,12944.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.16 12946[24:Spt:12945.2] || -> xuntil6(s10)*. % 75.92/76.16 12947[24:MRR:166.0,12946.0] || -> until5(s11)*. % 75.92/76.16 12948[24:MRR:11982.0,12947.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.16 12952[25:Spt:12948.2] || -> xuntil6(s11)*. % 75.92/76.16 12953[25:MRR:165.0,12952.0] || -> until5(s12)*. % 75.92/76.16 12954[25:MRR:11978.0,12953.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.16 12955[26:Spt:12954.2] || -> xuntil6(s12)*. % 75.92/76.16 12956[26:MRR:164.0,12955.0] || -> until5(s13)*. % 75.92/76.16 12957[26:MRR:11974.0,12956.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.16 12961[27:Spt:12957.2] || -> xuntil6(s13)*. % 75.92/76.16 12962[27:MRR:163.0,12961.0] || -> until5(s14)*. % 75.92/76.16 12963[27:MRR:11970.0,12962.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.16 12964[28:Spt:12963.2] || -> xuntil6(s14)*. % 75.92/76.16 12965[28:MRR:162.0,12964.0] || -> until5(s15)*. % 75.92/76.16 12966[28:MRR:11969.0,12965.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.16 12970[29:Spt:12966.2] || -> xuntil6(s15)*. % 75.92/76.16 12971[29:MRR:161.0,12970.0] || -> until5(s16)*. % 75.92/76.16 12972[29:MRR:11962.0,12971.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.16 12973[30:Spt:12972.2] || -> xuntil6(s16)*. % 75.92/76.16 12974[30:MRR:160.0,12973.0] || -> until5(s17)*. % 75.92/76.16 12975[30:MRR:11958.0,12974.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.16 12979[31:Spt:12975.2] || -> xuntil6(s17)*. % 75.92/76.16 12980[31:MRR:159.0,12979.0] || -> until5(s18)*. % 75.92/76.16 12981[31:MRR:11954.0,12980.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.16 12982[32:Spt:12981.2] || -> xuntil6(s18)*. % 75.92/76.16 12983[32:MRR:158.0,12982.0] || -> until5(s19)*. % 75.92/76.16 12984[32:MRR:11950.0,12983.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.16 12988[33:Spt:12984.2] || -> xuntil6(s19)*. % 75.92/76.16 12989[33:MRR:157.0,12988.0] || -> until5(s20)*. % 75.92/76.16 12990[33:MRR:11949.0,12989.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.16 12991[34:Spt:12990.2] || -> xuntil6(s20)*. % 75.92/76.16 12992[34:MRR:156.0,12991.0] || -> until5(s21)*. % 75.92/76.16 12993[34:MRR:11942.0,12992.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.16 12997[35:Spt:12993.2] || -> xuntil6(s21)*. % 75.92/76.16 12998[35:MRR:155.0,12997.0] || -> until5(s22)*. % 75.92/76.16 12999[35:MRR:11938.0,12998.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.16 13000[36:Spt:12999.2] || -> xuntil6(s22)*. % 75.92/76.16 13001[36:MRR:154.0,13000.0] || -> until5(s23)*. % 75.92/76.16 13002[36:MRR:11934.0,13001.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.16 13006[37:Spt:13002.2] || -> xuntil6(s23)*. % 75.92/76.16 13007[37:MRR:153.0,13006.0] || -> until5(s24)*. % 75.92/76.16 13008[37:MRR:11930.0,13007.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.16 13009[38:Spt:13008.2] || -> xuntil6(s24)*. % 75.92/76.16 13010[38:MRR:152.0,13009.0] || -> until5(s25)*. % 75.92/76.16 13011[38:MRR:11929.0,13010.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.16 13015[39:Spt:13011.2] || -> xuntil6(s25)*. % 75.92/76.16 13016[39:MRR:151.0,13015.0] || -> until5(s26)*. % 75.92/76.16 13017[39:MRR:11922.0,13016.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.16 13018[40:Spt:13017.2] || -> xuntil6(s26)*. % 75.92/76.16 13019[40:MRR:150.0,13018.0] || -> until5(s27)*. % 75.92/76.16 13020[40:MRR:11918.0,13019.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.16 13024[41:Spt:13020.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.16 13026[41:Res:13024.0,61.1] always3(s28) || -> . % 75.92/76.16 13027[41:SSi:13026.0,717.0] || -> . % 75.92/76.16 13028[41:Spt:13027.0,13020.1,13024.0] || m_main_v_state(s28,c_busy)*+ -> . % 75.92/76.16 13029[41:Spt:13027.0,13020.0,13020.2] || m_main_v_state(s27,c_ready)*+ -> xuntil6(s27). % 75.92/76.16 13032[41:Res:53.1,13029.0] || -> m_main_v_state(s27,c_busy)* xuntil6(s27). % 75.92/76.16 13034[42:Spt:13032.1] || -> xuntil6(s27)*. % 75.92/76.16 13035[42:MRR:149.0,13034.0] || -> until5(s28)*. % 75.92/76.16 13036[42:MRR:11914.0,13035.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.16 13041[43:Spt:13036.2] || -> xuntil6(s28)*. % 75.92/76.16 13042[43:MRR:148.0,13041.0] || -> until5(s29)*. % 75.92/76.16 13043[43:MRR:11910.0,13042.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.16 13044[44:Spt:13043.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.16 13046[44:Res:13044.0,61.1] always3(s30) || -> . % 75.92/76.16 13047[44:SSi:13046.0,719.0] || -> . % 75.92/76.16 13048[44:Spt:13047.0,13043.1,13044.0] || m_main_v_state(s30,c_busy)*+ -> . % 75.92/76.16 13049[44:Spt:13047.0,13043.0,13043.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 75.92/76.16 13052[44:Res:53.1,13049.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 75.92/76.16 13054[45:Spt:13052.1] || -> xuntil6(s29)*. % 75.92/76.16 13055[45:MRR:147.0,13054.0] || -> until5(s30)*. % 75.92/76.16 13056[45:MRR:11909.0,13055.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.16 13064[46:Spt:13056.2] || -> xuntil6(s30)*. % 75.92/76.16 13065[46:MRR:146.0,13064.0] || -> until5(s31)*. % 75.92/76.16 13066[46:MRR:11905.0,13065.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.16 13067[47:Spt:13066.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.16 13069[47:Res:13067.0,61.1] always3(s32) || -> . % 75.92/76.16 13070[47:SSi:13069.0,721.0] || -> . % 75.92/76.16 13071[47:Spt:13070.0,13066.1,13067.0] || m_main_v_state(s32,c_busy)*+ -> . % 75.92/76.16 13072[47:Spt:13070.0,13066.0,13066.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 75.92/76.16 13075[47:Res:53.1,13072.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 75.92/76.16 13080[48:Spt:13075.1] || -> xuntil6(s31)*. % 75.92/76.16 13081[48:MRR:145.0,13080.0] || -> until5(s32)*. % 75.92/76.16 13082[48:MRR:11904.0,13081.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.16 13084[49:Spt:13082.2] || -> xuntil6(s32)*. % 75.92/76.16 13085[49:MRR:144.0,13084.0] || -> until5(s33)*. % 75.92/76.16 13086[49:MRR:932.0,13085.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.16 13087[50:Spt:13086.1] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.16 13089[50:Res:13087.0,61.1] always3(s34) || -> . % 75.92/76.16 13090[50:SSi:13089.0,723.0] || -> . % 75.92/76.16 13091[50:Spt:13090.0,13086.1,13087.0] || m_main_v_state(s34,c_busy)*+ -> . % 75.92/76.16 13092[50:Spt:13090.0,13086.0,13086.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 75.92/76.16 13095[50:Res:53.1,13092.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 75.92/76.16 13097[51:Spt:13095.1] || -> xuntil6(s33)*. % 75.92/76.16 13098[51:MRR:143.0,13097.0] || -> until5(s34)*. % 75.92/76.16 13099[51:MRR:12029.0,13098.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.16 13104[52:Spt:13099.2] || -> xuntil6(s34)*. % 75.92/76.16 13105[52:MRR:142.0,13104.0] || -> until5(s35)*. % 75.92/76.16 13106[52:MRR:930.0,13105.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.16 13107[53:Spt:13106.1] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.16 13109[53:Res:13107.0,61.1] always3(s36) || -> . % 75.92/76.16 13110[53:SSi:13109.0,725.0] || -> . % 75.92/76.16 13111[53:Spt:13110.0,13106.1,13107.0] || m_main_v_state(s36,c_busy)*+ -> . % 75.92/76.16 13112[53:Spt:13110.0,13106.0,13106.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 75.92/76.16 13115[53:Res:53.1,13112.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 75.92/76.16 13117[54:Spt:13115.1] || -> xuntil6(s35)*. % 75.92/76.16 13118[54:MRR:141.0,13117.0] || -> until5(s36)*. % 75.92/76.16 13119[54:MRR:12033.0,13118.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.16 13127[55:Spt:13119.2] || -> xuntil6(s36)*. % 75.92/76.16 13128[55:MRR:140.0,13127.0] || -> until5(s37)*. % 75.92/76.16 13129[55:MRR:928.0,13128.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.16 13130[56:Spt:13129.1] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.16 13132[56:Res:13130.0,61.1] always3(s38) || -> . % 75.92/76.16 13133[56:SSi:13132.0,727.0] || -> . % 75.92/76.16 13134[56:Spt:13133.0,13129.1,13130.0] || m_main_v_state(s38,c_busy)*+ -> . % 75.92/76.16 13135[56:Spt:13133.0,13129.0,13129.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 75.92/76.16 13138[56:MRR:12897.2,13134.0] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.16 13139[56:Res:53.1,13135.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 75.92/76.16 13144[57:Spt:13139.1] || -> xuntil6(s37)*. % 75.92/76.16 13145[57:MRR:139.0,13144.0] || -> until5(s38)*. % 75.92/76.16 13146[57:MRR:12040.0,13145.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.16 13149[56:SoR:13138.0,64.1] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.16 13154[56:SoR:13149.0,66.2] until5(s49) || m_main_v_state(s49,c_ready)* -> xuntil6(s49). % 75.92/76.16 13155[58:Spt:13146.2] || -> xuntil6(s38)*. % 75.92/76.16 13156[58:MRR:138.0,13155.0] || -> until5(s39)*. % 75.92/76.16 13157[58:MRR:926.0,13156.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.16 13161[59:Spt:13157.1] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.16 13163[59:Res:13161.0,61.1] always3(s40) || -> . % 75.92/76.16 13164[59:SSi:13163.0,729.0] || -> . % 75.92/76.16 13165[59:Spt:13164.0,13157.1,13161.0] || m_main_v_state(s40,c_busy)*+ -> . % 75.92/76.16 13166[59:Spt:13164.0,13157.0,13157.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 75.92/76.16 13168[59:MRR:801.2,13165.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 75.92/76.16 13169[59:Res:53.1,13166.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 75.92/76.16 13171[60:Spt:13169.1] || -> xuntil6(s39)*. % 75.92/76.16 13172[60:MRR:137.0,13171.0] || -> until5(s40)*. % 75.92/76.16 13173[60:MRR:12041.0,13172.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.16 13178[61:Spt:13173.2] || -> xuntil6(s40)*. % 75.92/76.16 13179[61:MRR:136.0,13178.0] || -> until5(s41)*. % 75.92/76.16 13180[61:MRR:924.0,13179.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.16 13181[62:Spt:13180.1] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.16 13183[62:Res:13181.0,61.1] always3(s42) || -> . % 75.92/76.16 13184[62:SSi:13183.0,731.0] || -> . % 75.92/76.16 13185[62:Spt:13184.0,13180.1,13181.0] || m_main_v_state(s42,c_busy)*+ -> . % 75.92/76.16 13186[62:Spt:13184.0,13180.0,13180.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 75.92/76.16 13188[62:MRR:795.2,13185.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 75.92/76.16 13189[62:Res:53.1,13186.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 75.92/76.16 13191[63:Spt:13189.1] || -> xuntil6(s41)*. % 75.92/76.16 13192[63:MRR:135.0,13191.0] || -> until5(s42)*. % 75.92/76.16 13193[63:MRR:12045.0,13192.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.16 13201[64:Spt:13193.2] || -> xuntil6(s42)*. % 75.92/76.16 13202[64:MRR:134.0,13201.0] || -> until5(s43)*. % 75.92/76.16 13203[64:MRR:922.0,13202.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.16 13204[65:Spt:13203.1] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.16 13206[65:Res:13204.0,61.1] always3(s44) || -> . % 75.92/76.16 13207[65:SSi:13206.0,733.0] || -> . % 75.92/76.16 13208[65:Spt:13207.0,13203.1,13204.0] || m_main_v_state(s44,c_busy)*+ -> . % 75.92/76.16 13209[65:Spt:13207.0,13203.0,13203.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 75.92/76.16 13211[65:MRR:789.2,13208.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 75.92/76.16 13212[65:Res:53.1,13209.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 75.92/76.16 13217[66:Spt:13212.1] || -> xuntil6(s43)*. % 75.92/76.16 13218[66:MRR:133.0,13217.0] || -> until5(s44)*. % 75.92/76.16 13219[66:MRR:12049.0,13218.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.16 13221[67:Spt:13219.2] || -> xuntil6(s44)*. % 75.92/76.16 13222[67:MRR:132.0,13221.0] || -> until5(s45)*. % 75.92/76.16 13223[67:MRR:920.0,13222.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.16 13224[68:Spt:13223.1] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.16 13226[68:Res:13224.0,61.1] always3(s46) || -> . % 75.92/76.16 13227[68:SSi:13226.0,735.0] || -> . % 75.92/76.16 13228[68:Spt:13227.0,13223.1,13224.0] || m_main_v_state(s46,c_busy)*+ -> . % 75.92/76.16 13229[68:Spt:13227.0,13223.0,13223.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 75.92/76.16 13231[68:MRR:783.2,13228.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 75.92/76.16 13232[68:Res:53.1,13229.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 75.92/76.16 13234[69:Spt:13232.1] || -> xuntil6(s45)*. % 75.92/76.16 13235[69:MRR:131.0,13234.0] || -> until5(s46)*. % 75.92/76.16 13236[69:MRR:12053.0,13235.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.16 13241[70:Spt:13236.2] || -> xuntil6(s46)*. % 75.92/76.16 13242[70:MRR:130.0,13241.0] || -> until5(s47)*. % 75.92/76.16 13243[70:MRR:918.0,13242.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.16 13244[71:Spt:13243.1] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.16 13246[71:Res:13244.0,61.1] always3(s48) || -> . % 75.92/76.16 13247[71:SSi:13246.0,737.0] || -> . % 75.92/76.16 13248[71:Spt:13247.0,13243.1,13244.0] || m_main_v_state(s48,c_busy)*+ -> . % 75.92/76.16 13249[71:Spt:13247.0,13243.0,13243.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 75.92/76.16 13251[71:MRR:777.2,13248.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 75.92/76.16 13252[71:Res:53.1,13249.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 75.92/76.16 13254[72:Spt:13252.1] || -> xuntil6(s47)*. % 75.92/76.16 13255[72:MRR:129.0,13254.0] || -> until5(s48)*. % 75.92/76.16 13256[72:MRR:12057.0,13255.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.16 13264[73:Spt:13256.2] || -> xuntil6(s48)*. % 75.92/76.16 13265[73:MRR:128.0,13264.0] || -> until5(s49)*. % 75.92/76.16 13266[73:MRR:13154.0,13265.0] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.16 13267[73:Res:53.1,13266.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.16 13269[74:Spt:13267.1] || -> xuntil6(s49)*. % 75.92/76.16 13270[74:MRR:12896.0,13269.0] || -> until2p7(s38)*. % 75.92/76.16 13271[74:MRR:236.0,13270.0] || -> until2p7(s39)* node4(s38). % 75.92/76.16 13272[75:Spt:13271.0] || -> until2p7(s39)*. % 75.92/76.16 13273[75:MRR:237.0,13272.0] || -> until2p7(s40)* node4(s39). % 75.92/76.16 13274[76:Spt:13273.0] || -> until2p7(s40)*. % 75.92/76.16 13275[76:MRR:238.0,13274.0] || -> until2p7(s41)* node4(s40). % 75.92/76.16 13276[77:Spt:13275.0] || -> until2p7(s41)*. % 75.92/76.16 13277[77:MRR:239.0,13276.0] || -> until2p7(s42)* node4(s41). % 75.92/76.16 13278[78:Spt:13277.0] || -> until2p7(s42)*. % 75.92/76.16 13279[78:MRR:240.0,13278.0] || -> until2p7(s43)* node4(s42). % 75.92/76.16 13280[79:Spt:13279.0] || -> until2p7(s43)*. % 75.92/76.16 13281[79:MRR:241.0,13280.0] || -> until2p7(s44)* node4(s43). % 75.92/76.16 13282[80:Spt:13281.0] || -> until2p7(s44)*. % 75.92/76.16 13283[80:MRR:539.0,13282.0] || -> until2p7(s45)* node4(s44). % 75.92/76.16 13284[81:Spt:13283.0] || -> until2p7(s45)*. % 75.92/76.16 13285[81:MRR:544.0,13284.0] || -> until2p7(s46)* node4(s45). % 75.92/76.16 13286[82:Spt:13285.0] || -> until2p7(s46)*. % 75.92/76.16 13287[82:MRR:549.0,13286.0] || -> until2p7(s47)* node4(s46). % 75.92/76.16 13288[83:Spt:13287.0] || -> until2p7(s47)*. % 75.92/76.16 13289[83:MRR:554.0,13288.0] || -> until2p7(s48)* node4(s47). % 75.92/76.16 13290[84:Spt:13289.0] || -> until2p7(s48)*. % 75.92/76.16 13291[84:MRR:559.0,13290.0] || -> until2p7(s49)* node4(s48). % 75.92/76.16 13292[85:Spt:13291.0] || -> until2p7(s49)*. % 75.92/76.16 13293[85:MRR:194.0,13292.0] || -> node4(s49)*. % 75.92/76.16 13294[85:MRR:13149.0,13293.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.16 13295[85:Res:53.1,13294.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.16 13298[85:Res:13295.0,61.1] always3(s49) || -> . % 75.92/76.16 13299[85:SSi:13298.0,50.0,738.0,13265.0,13269.0,13292.0,13293.0] || -> . % 75.92/76.16 13300[85:Spt:13299.0,13291.0,13292.0] || until2p7(s49)*+ -> . % 75.92/76.16 13301[85:Spt:13299.0,13291.1] || -> node4(s48)*. % 75.92/76.16 13303[85:MRR:774.0,13301.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.16 13312[85:Res:53.1,13303.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.16 13314[85:MRR:13312.0,13248.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.16 13316[85:Res:13314.0,61.1] always3(s49) || -> . % 75.92/76.16 13317[85:SSi:13316.0,50.0,738.0,13265.0,13269.0] || -> . % 75.92/76.16 13318[84:Spt:13317.0,13289.0,13290.0] || until2p7(s48)*+ -> . % 75.92/76.16 13319[84:Spt:13317.0,13289.1] || -> node4(s47)*. % 75.92/76.16 13320[84:MRR:13251.0,13319.0] || m_main_v_state(s47,c_ready)*+ -> . % 75.92/76.16 13324[84:Res:53.1,13320.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.16 13327[84:Res:13324.0,61.1] always3(s47) || -> . % 75.92/76.16 13328[84:SSi:13327.0,736.0,13242.0,13254.0,13288.0,13319.0] || -> . % 75.92/76.16 13329[83:Spt:13328.0,13287.0,13288.0] || until2p7(s47)*+ -> . % 75.92/76.16 13330[83:Spt:13328.0,13287.1] || -> node4(s46)*. % 75.92/76.16 13332[83:MRR:780.0,13330.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.16 13343[83:Res:53.1,13332.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.16 13345[83:MRR:13343.0,13228.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.16 13347[83:Res:13345.0,61.1] always3(s47) || -> . % 75.92/76.16 13348[83:SSi:13347.0,736.0,13242.0,13254.0] || -> . % 75.92/76.16 13349[82:Spt:13348.0,13285.0,13286.0] || until2p7(s46)*+ -> . % 75.92/76.16 13350[82:Spt:13348.0,13285.1] || -> node4(s45)*. % 75.92/76.16 13351[82:MRR:13231.0,13350.0] || m_main_v_state(s45,c_ready)*+ -> . % 75.92/76.16 13354[82:Res:53.1,13351.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.16 13357[82:Res:13354.0,61.1] always3(s45) || -> . % 75.92/76.16 13358[82:SSi:13357.0,734.0,13222.0,13234.0,13284.0,13350.0] || -> . % 75.92/76.16 13359[81:Spt:13358.0,13283.0,13284.0] || until2p7(s45)*+ -> . % 75.92/76.16 13360[81:Spt:13358.0,13283.1] || -> node4(s44)*. % 75.92/76.16 13362[81:MRR:786.0,13360.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.16 13374[81:Res:53.1,13362.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.16 13376[81:MRR:13374.0,13208.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.16 13378[81:Res:13376.0,61.1] always3(s45) || -> . % 75.92/76.16 13379[81:SSi:13378.0,734.0,13222.0,13234.0] || -> . % 75.92/76.16 13380[80:Spt:13379.0,13281.0,13282.0] || until2p7(s44)*+ -> . % 75.92/76.16 13381[80:Spt:13379.0,13281.1] || -> node4(s43)*. % 75.92/76.16 13382[80:MRR:13211.0,13381.0] || m_main_v_state(s43,c_ready)*+ -> . % 75.92/76.16 13385[80:Res:53.1,13382.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.16 13388[80:Res:13385.0,61.1] always3(s43) || -> . % 75.92/76.16 13389[80:SSi:13388.0,732.0,13202.0,13217.0,13280.0,13381.0] || -> . % 75.92/76.16 13390[79:Spt:13389.0,13279.0,13280.0] || until2p7(s43)*+ -> . % 75.92/76.16 13391[79:Spt:13389.0,13279.1] || -> node4(s42)*. % 75.92/76.16 13393[79:MRR:792.0,13391.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.16 13405[79:Res:53.1,13393.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.16 13407[79:MRR:13405.0,13185.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.16 13412[79:Res:13407.0,61.1] always3(s43) || -> . % 75.92/76.16 13413[79:SSi:13412.0,732.0,13202.0,13217.0] || -> . % 75.92/76.16 13414[78:Spt:13413.0,13277.0,13278.0] || until2p7(s42)*+ -> . % 75.92/76.16 13415[78:Spt:13413.0,13277.1] || -> node4(s41)*. % 75.92/76.16 13416[78:MRR:13188.0,13415.0] || m_main_v_state(s41,c_ready)*+ -> . % 75.92/76.16 13419[78:Res:53.1,13416.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.16 13423[78:Res:13419.0,61.1] always3(s41) || -> . % 75.92/76.16 13424[78:SSi:13423.0,730.0,13179.0,13191.0,13276.0,13415.0] || -> . % 75.92/76.16 13425[77:Spt:13424.0,13275.0,13276.0] || until2p7(s41)*+ -> . % 75.92/76.16 13426[77:Spt:13424.0,13275.1] || -> node4(s40)*. % 75.92/76.16 13428[77:MRR:798.0,13426.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.16 13439[77:Res:53.1,13428.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.16 13441[77:MRR:13439.0,13165.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.16 13443[77:Res:13441.0,61.1] always3(s41) || -> . % 75.92/76.16 13444[77:SSi:13443.0,730.0,13179.0,13191.0] || -> . % 75.92/76.16 13445[76:Spt:13444.0,13273.0,13274.0] || until2p7(s40)*+ -> . % 75.92/76.16 13446[76:Spt:13444.0,13273.1] || -> node4(s39)*. % 75.92/76.16 13447[76:MRR:13168.0,13446.0] || m_main_v_state(s39,c_ready)*+ -> . % 75.92/76.16 13451[76:Res:53.1,13447.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.16 13454[76:Res:13451.0,61.1] always3(s39) || -> . % 75.92/76.16 13455[76:SSi:13454.0,728.0,13156.0,13171.0,13272.0,13446.0] || -> . % 75.92/76.16 13456[75:Spt:13455.0,13271.0,13272.0] || until2p7(s39)*+ -> . % 75.92/76.16 13457[75:Spt:13455.0,13271.1] || -> node4(s38)*. % 75.92/76.16 13459[75:MRR:804.0,13457.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.16 13470[75:Res:53.1,13459.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.16 13472[75:MRR:13470.0,13134.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.16 13474[75:Res:13472.0,61.1] always3(s39) || -> . % 75.92/76.16 13475[75:SSi:13474.0,728.0,13156.0,13171.0] || -> . % 75.92/76.16 13476[74:Spt:13475.0,13267.1,13269.0] || xuntil6(s49)* -> . % 75.92/76.16 13477[74:Spt:13475.0,13267.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.16 13480[74:Res:13477.0,61.1] always3(s49) || -> . % 75.92/76.16 13481[74:SSi:13480.0,50.0,738.0,13265.0] || -> . % 75.92/76.16 13482[73:Spt:13481.0,13256.2,13264.0] || xuntil6(s48)*+ -> . % 75.92/76.16 13483[73:Spt:13481.0,13256.0,13256.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.16 13484[73:Res:53.1,13483.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.16 13486[73:MRR:13484.0,13248.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.16 13489[73:Res:13486.0,61.1] always3(s49) || -> . % 75.92/76.16 13490[73:SSi:13489.0,50.0,738.0] || -> . % 75.92/76.16 13491[72:Spt:13490.0,13252.1,13254.0] || xuntil6(s47)* -> . % 75.92/76.16 13492[72:Spt:13490.0,13252.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.16 13495[72:Res:13492.0,61.1] always3(s47) || -> . % 75.92/76.16 13496[72:SSi:13495.0,736.0,13242.0] || -> . % 75.92/76.16 13497[70:Spt:13496.0,13236.2,13241.0] || xuntil6(s46)*+ -> . % 75.92/76.16 13498[70:Spt:13496.0,13236.0,13236.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.16 13499[70:Res:53.1,13498.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.16 13501[70:MRR:13499.0,13228.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.16 13503[70:Res:13501.0,61.1] always3(s47) || -> . % 75.92/76.16 13504[70:SSi:13503.0,736.0] || -> . % 75.92/76.16 13505[69:Spt:13504.0,13232.1,13234.0] || xuntil6(s45)* -> . % 75.92/76.16 13506[69:Spt:13504.0,13232.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.16 13509[69:Res:13506.0,61.1] always3(s45) || -> . % 75.92/76.16 13510[69:SSi:13509.0,734.0,13222.0] || -> . % 75.92/76.16 13511[67:Spt:13510.0,13219.2,13221.0] || xuntil6(s44)*+ -> . % 75.92/76.16 13512[67:Spt:13510.0,13219.0,13219.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.16 13513[67:Res:53.1,13512.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.16 13515[67:MRR:13513.0,13208.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.16 13518[67:Res:13515.0,61.1] always3(s45) || -> . % 75.92/76.16 13519[67:SSi:13518.0,734.0] || -> . % 75.92/76.16 13520[66:Spt:13519.0,13212.1,13217.0] || xuntil6(s43)* -> . % 75.92/76.16 13521[66:Spt:13519.0,13212.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.16 13524[66:Res:13521.0,61.1] always3(s43) || -> . % 75.92/76.16 13525[66:SSi:13524.0,732.0,13202.0] || -> . % 75.92/76.16 13526[64:Spt:13525.0,13193.2,13201.0] || xuntil6(s42)*+ -> . % 75.92/76.16 13527[64:Spt:13525.0,13193.0,13193.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.16 13528[64:Res:53.1,13527.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.16 13530[64:MRR:13528.0,13185.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.16 13532[64:Res:13530.0,61.1] always3(s43) || -> . % 75.92/76.16 13533[64:SSi:13532.0,732.0] || -> . % 75.92/76.16 13534[63:Spt:13533.0,13189.1,13191.0] || xuntil6(s41)* -> . % 75.92/76.16 13535[63:Spt:13533.0,13189.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.16 13538[63:Res:13535.0,61.1] always3(s41) || -> . % 75.92/76.16 13539[63:SSi:13538.0,730.0,13179.0] || -> . % 75.92/76.16 13540[61:Spt:13539.0,13173.2,13178.0] || xuntil6(s40)*+ -> . % 75.92/76.16 13541[61:Spt:13539.0,13173.0,13173.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.16 13542[61:Res:53.1,13541.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.16 13544[61:MRR:13542.0,13165.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.16 13546[61:Res:13544.0,61.1] always3(s41) || -> . % 75.92/76.16 13547[61:SSi:13546.0,730.0] || -> . % 75.92/76.16 13548[60:Spt:13547.0,13169.1,13171.0] || xuntil6(s39)* -> . % 75.92/76.16 13549[60:Spt:13547.0,13169.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.16 13552[60:Res:13549.0,61.1] always3(s39) || -> . % 75.92/76.16 13553[60:SSi:13552.0,728.0,13156.0] || -> . % 75.92/76.16 13554[58:Spt:13553.0,13146.2,13155.0] || xuntil6(s38)*+ -> . % 75.92/76.16 13555[58:Spt:13553.0,13146.0,13146.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.16 13556[58:Res:53.1,13555.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.16 13558[58:MRR:13556.0,13134.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.16 13560[58:Res:13558.0,61.1] always3(s39) || -> . % 75.92/76.16 13561[58:SSi:13560.0,728.0] || -> . % 75.92/76.16 13562[57:Spt:13561.0,13139.1,13144.0] || xuntil6(s37)* -> . % 75.92/76.16 13563[57:Spt:13561.0,13139.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.16 13566[57:Res:13563.0,61.1] always3(s37) || -> . % 75.92/76.16 13567[57:SSi:13566.0,726.0,13128.0] || -> . % 75.92/76.16 13568[55:Spt:13567.0,13119.2,13127.0] || xuntil6(s36)*+ -> . % 75.92/76.16 13569[55:Spt:13567.0,13119.0,13119.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.16 13570[55:Res:53.1,13569.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.16 13572[55:MRR:13570.0,13111.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.16 13574[55:Res:13572.0,61.1] always3(s37) || -> . % 75.92/76.16 13575[55:SSi:13574.0,726.0] || -> . % 75.92/76.16 13576[54:Spt:13575.0,13115.1,13117.0] || xuntil6(s35)* -> . % 75.92/76.16 13577[54:Spt:13575.0,13115.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.16 13580[54:Res:13577.0,61.1] always3(s35) || -> . % 75.92/76.16 13581[54:SSi:13580.0,724.0,13105.0] || -> . % 75.92/76.16 13582[52:Spt:13581.0,13099.2,13104.0] || xuntil6(s34)*+ -> . % 75.92/76.16 13583[52:Spt:13581.0,13099.0,13099.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 75.92/76.16 13584[52:Res:53.1,13583.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 75.92/76.16 13586[52:MRR:13584.0,13091.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.16 13588[52:Res:13586.0,61.1] always3(s35) || -> . % 75.92/76.16 13589[52:SSi:13588.0,724.0] || -> . % 75.92/76.16 13590[51:Spt:13589.0,13095.1,13097.0] || xuntil6(s33)* -> . % 75.92/76.16 13591[51:Spt:13589.0,13095.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.16 13594[51:Res:13591.0,61.1] always3(s33) || -> . % 75.92/76.16 13595[51:SSi:13594.0,722.0,13085.0] || -> . % 75.92/76.16 13596[49:Spt:13595.0,13082.2,13084.0] || xuntil6(s32)*+ -> . % 75.92/76.16 13597[49:Spt:13595.0,13082.0,13082.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 75.92/76.16 13598[49:Res:53.1,13597.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 75.92/76.16 13600[49:MRR:13598.0,13071.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.16 13602[49:Res:13600.0,61.1] always3(s33) || -> . % 75.92/76.16 13603[49:SSi:13602.0,722.0] || -> . % 75.92/76.16 13604[48:Spt:13603.0,13075.1,13080.0] || xuntil6(s31)* -> . % 75.92/76.16 13605[48:Spt:13603.0,13075.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.16 13608[48:Res:13605.0,61.1] always3(s31) || -> . % 75.92/76.16 13609[48:SSi:13608.0,720.0,13065.0] || -> . % 75.92/76.16 13610[46:Spt:13609.0,13056.2,13064.0] || xuntil6(s30)*+ -> . % 75.92/76.16 13611[46:Spt:13609.0,13056.0,13056.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.16 13612[46:Res:53.1,13611.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.16 13614[46:MRR:13612.0,13048.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.16 13616[46:Res:13614.0,61.1] always3(s31) || -> . % 75.92/76.16 13617[46:SSi:13616.0,720.0] || -> . % 75.92/76.16 13618[45:Spt:13617.0,13052.1,13054.0] || xuntil6(s29)* -> . % 75.92/76.16 13619[45:Spt:13617.0,13052.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.16 13622[45:Res:13619.0,61.1] always3(s29) || -> . % 75.92/76.16 13623[45:SSi:13622.0,718.0,13042.0] || -> . % 75.92/76.16 13624[43:Spt:13623.0,13036.2,13041.0] || xuntil6(s28)*+ -> . % 75.92/76.16 13625[43:Spt:13623.0,13036.0,13036.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.16 13626[43:Res:53.1,13625.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.16 13628[43:MRR:13626.0,13028.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.16 13630[43:Res:13628.0,61.1] always3(s29) || -> . % 75.92/76.16 13631[43:SSi:13630.0,718.0] || -> . % 75.92/76.16 13632[42:Spt:13631.0,13032.1,13034.0] || xuntil6(s27)* -> . % 75.92/76.16 13633[42:Spt:13631.0,13032.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.16 13636[42:Res:13633.0,61.1] always3(s27) || -> . % 75.92/76.16 13637[42:SSi:13636.0,716.0,13019.0] || -> . % 75.92/76.16 13638[40:Spt:13637.0,13017.2,13018.0] || xuntil6(s26)*+ -> . % 75.92/76.16 13639[40:Spt:13637.0,13017.0,13017.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.16 13640[40:Res:53.1,13639.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.16 13642[41:Spt:13640.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.16 13644[41:Res:13642.0,61.1] always3(s26) || -> . % 75.92/76.16 13645[41:SSi:13644.0,715.0,13016.0] || -> . % 75.92/76.16 13646[41:Spt:13645.0,13640.0,13642.0] || m_main_v_state(s26,c_busy)* -> . % 75.92/76.16 13647[41:Spt:13645.0,13640.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.16 13651[41:Res:13647.0,61.1] always3(s27) || -> . % 75.92/76.16 13652[41:SSi:13651.0,716.0] || -> . % 75.92/76.16 13653[39:Spt:13652.0,13011.2,13015.0] || xuntil6(s25)*+ -> . % 75.92/76.16 13654[39:Spt:13652.0,13011.0,13011.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.16 13655[39:Res:53.1,13654.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.16 13657[40:Spt:13655.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.16 13659[40:Res:13657.0,61.1] always3(s25) || -> . % 75.92/76.16 13660[40:SSi:13659.0,714.0,13010.0] || -> . % 75.92/76.16 13661[40:Spt:13660.0,13655.0,13657.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.16 13662[40:Spt:13660.0,13655.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.16 13666[40:Res:13662.0,61.1] always3(s26) || -> . % 75.92/76.16 13667[40:SSi:13666.0,715.0] || -> . % 75.92/76.16 13668[38:Spt:13667.0,13008.2,13009.0] || xuntil6(s24)*+ -> . % 75.92/76.16 13669[38:Spt:13667.0,13008.0,13008.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.16 13670[38:Res:53.1,13669.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.16 13672[39:Spt:13670.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.16 13674[39:Res:13672.0,61.1] always3(s24) || -> . % 75.92/76.16 13675[39:SSi:13674.0,713.0,13007.0] || -> . % 75.92/76.16 13676[39:Spt:13675.0,13670.0,13672.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.16 13677[39:Spt:13675.0,13670.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.16 13681[39:Res:13677.0,61.1] always3(s25) || -> . % 75.92/76.16 13682[39:SSi:13681.0,714.0] || -> . % 75.92/76.16 13683[37:Spt:13682.0,13002.2,13006.0] || xuntil6(s23)*+ -> . % 75.92/76.16 13684[37:Spt:13682.0,13002.0,13002.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.16 13685[37:Res:53.1,13684.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.16 13687[38:Spt:13685.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.16 13689[38:Res:13687.0,61.1] always3(s23) || -> . % 75.92/76.16 13690[38:SSi:13689.0,712.0,13001.0] || -> . % 75.92/76.16 13691[38:Spt:13690.0,13685.0,13687.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.16 13692[38:Spt:13690.0,13685.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.16 13696[38:Res:13692.0,61.1] always3(s24) || -> . % 75.92/76.16 13697[38:SSi:13696.0,713.0] || -> . % 75.92/76.16 13698[36:Spt:13697.0,12999.2,13000.0] || xuntil6(s22)*+ -> . % 75.92/76.16 13699[36:Spt:13697.0,12999.0,12999.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.16 13700[36:Res:53.1,13699.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.16 13702[37:Spt:13700.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.16 13704[37:Res:13702.0,61.1] always3(s22) || -> . % 75.92/76.16 13705[37:SSi:13704.0,711.0,12998.0] || -> . % 75.92/76.16 13706[37:Spt:13705.0,13700.0,13702.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.16 13707[37:Spt:13705.0,13700.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.16 13711[37:Res:13707.0,61.1] always3(s23) || -> . % 75.92/76.16 13712[37:SSi:13711.0,712.0] || -> . % 75.92/76.16 13713[35:Spt:13712.0,12993.2,12997.0] || xuntil6(s21)*+ -> . % 75.92/76.16 13714[35:Spt:13712.0,12993.0,12993.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.16 13715[35:Res:53.1,13714.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.16 13717[36:Spt:13715.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.16 13719[36:Res:13717.0,61.1] always3(s21) || -> . % 75.92/76.16 13720[36:SSi:13719.0,710.0,12992.0] || -> . % 75.92/76.16 13721[36:Spt:13720.0,13715.0,13717.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.16 13722[36:Spt:13720.0,13715.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.16 13726[36:Res:13722.0,61.1] always3(s22) || -> . % 75.92/76.16 13727[36:SSi:13726.0,711.0] || -> . % 75.92/76.16 13728[34:Spt:13727.0,12990.2,12991.0] || xuntil6(s20)*+ -> . % 75.92/76.16 13729[34:Spt:13727.0,12990.0,12990.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.16 13730[34:Res:53.1,13729.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.16 13732[35:Spt:13730.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.16 13734[35:Res:13732.0,61.1] always3(s20) || -> . % 75.92/76.16 13735[35:SSi:13734.0,709.0,12989.0] || -> . % 75.92/76.16 13736[35:Spt:13735.0,13730.0,13732.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.16 13737[35:Spt:13735.0,13730.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.16 13741[35:Res:13737.0,61.1] always3(s21) || -> . % 75.92/76.16 13742[35:SSi:13741.0,710.0] || -> . % 75.92/76.16 13743[33:Spt:13742.0,12984.2,12988.0] || xuntil6(s19)*+ -> . % 75.92/76.16 13744[33:Spt:13742.0,12984.0,12984.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.16 13745[33:Res:53.1,13744.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.16 13747[34:Spt:13745.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.16 13749[34:Res:13747.0,61.1] always3(s20) || -> . % 75.92/76.16 13750[34:SSi:13749.0,709.0] || -> . % 75.92/76.16 13751[34:Spt:13750.0,13745.1,13747.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.16 13752[34:Spt:13750.0,13745.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.16 13755[34:Res:13752.0,61.1] always3(s19) || -> . % 75.92/76.16 13756[34:SSi:13755.0,708.0,12983.0] || -> . % 75.92/76.16 13757[32:Spt:13756.0,12981.2,12982.0] || xuntil6(s18)*+ -> . % 75.92/76.16 13758[32:Spt:13756.0,12981.0,12981.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.16 13759[32:Res:53.1,13758.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.16 13761[33:Spt:13759.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.16 13763[33:Res:13761.0,61.1] always3(s19) || -> . % 75.92/76.16 13764[33:SSi:13763.0,708.0] || -> . % 75.92/76.16 13765[33:Spt:13764.0,13759.1,13761.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.16 13766[33:Spt:13764.0,13759.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.16 13769[33:Res:13766.0,61.1] always3(s18) || -> . % 75.92/76.16 13770[33:SSi:13769.0,707.0,12980.0] || -> . % 75.92/76.16 13771[31:Spt:13770.0,12975.2,12979.0] || xuntil6(s17)*+ -> . % 75.92/76.16 13772[31:Spt:13770.0,12975.0,12975.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.16 13773[31:Res:53.1,13772.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.16 13775[32:Spt:13773.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.16 13777[32:Res:13775.0,61.1] always3(s18) || -> . % 75.92/76.16 13778[32:SSi:13777.0,707.0] || -> . % 75.92/76.16 13779[32:Spt:13778.0,13773.1,13775.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.16 13780[32:Spt:13778.0,13773.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.16 13783[32:Res:13780.0,61.1] always3(s17) || -> . % 75.92/76.16 13784[32:SSi:13783.0,706.0,12974.0] || -> . % 75.92/76.16 13785[30:Spt:13784.0,12972.2,12973.0] || xuntil6(s16)*+ -> . % 75.92/76.16 13786[30:Spt:13784.0,12972.0,12972.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.16 13787[30:Res:53.1,13786.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.16 13792[31:Spt:13787.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.16 13794[31:Res:13792.0,61.1] always3(s16) || -> . % 75.92/76.16 13795[31:SSi:13794.0,705.0,12971.0] || -> . % 75.92/76.16 13796[31:Spt:13795.0,13787.0,13792.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.16 13797[31:Spt:13795.0,13787.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.16 13801[31:Res:13797.0,61.1] always3(s17) || -> . % 75.92/76.16 13802[31:SSi:13801.0,706.0] || -> . % 75.92/76.16 13803[29:Spt:13802.0,12966.2,12970.0] || xuntil6(s15)*+ -> . % 75.92/76.16 13804[29:Spt:13802.0,12966.0,12966.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.16 13805[29:Res:53.1,13804.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.16 13807[30:Spt:13805.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.16 13809[30:Res:13807.0,61.1] always3(s16) || -> . % 75.92/76.16 13810[30:SSi:13809.0,705.0] || -> . % 75.92/76.16 13811[30:Spt:13810.0,13805.1,13807.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.16 13812[30:Spt:13810.0,13805.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.16 13815[30:Res:13812.0,61.1] always3(s15) || -> . % 75.92/76.16 13816[30:SSi:13815.0,704.0,12965.0] || -> . % 75.92/76.16 13817[28:Spt:13816.0,12963.2,12964.0] || xuntil6(s14)*+ -> . % 75.92/76.16 13818[28:Spt:13816.0,12963.0,12963.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.16 13819[28:Res:53.1,13818.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.16 13821[29:Spt:13819.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.16 13823[29:Res:13821.0,61.1] always3(s15) || -> . % 75.92/76.16 13824[29:SSi:13823.0,704.0] || -> . % 75.92/76.16 13825[29:Spt:13824.0,13819.1,13821.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.16 13826[29:Spt:13824.0,13819.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.16 13829[29:Res:13826.0,61.1] always3(s14) || -> . % 75.92/76.16 13830[29:SSi:13829.0,703.0,12962.0] || -> . % 75.92/76.16 13831[27:Spt:13830.0,12957.2,12961.0] || xuntil6(s13)*+ -> . % 75.92/76.16 13832[27:Spt:13830.0,12957.0,12957.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.16 13833[27:Res:53.1,13832.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.16 13838[28:Spt:13833.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.16 13840[28:Res:13838.0,61.1] always3(s13) || -> . % 75.92/76.16 13841[28:SSi:13840.0,702.0,12956.0] || -> . % 75.92/76.16 13842[28:Spt:13841.0,13833.0,13838.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.16 13843[28:Spt:13841.0,13833.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.16 13847[28:Res:13843.0,61.1] always3(s14) || -> . % 75.92/76.16 13848[28:SSi:13847.0,703.0] || -> . % 75.92/76.16 13849[26:Spt:13848.0,12954.2,12955.0] || xuntil6(s12)*+ -> . % 75.92/76.16 13850[26:Spt:13848.0,12954.0,12954.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.16 13851[26:Res:53.1,13850.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.16 13853[27:Spt:13851.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.16 13855[27:Res:13853.0,61.1] always3(s13) || -> . % 75.92/76.16 13856[27:SSi:13855.0,702.0] || -> . % 75.92/76.16 13857[27:Spt:13856.0,13851.1,13853.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.16 13858[27:Spt:13856.0,13851.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.16 13861[27:Res:13858.0,61.1] always3(s12) || -> . % 75.92/76.16 13862[27:SSi:13861.0,701.0,12953.0] || -> . % 75.92/76.16 13863[25:Spt:13862.0,12948.2,12952.0] || xuntil6(s11)*+ -> . % 75.92/76.16 13864[25:Spt:13862.0,12948.0,12948.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.16 13865[25:Res:53.1,13864.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.16 13867[26:Spt:13865.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.16 13869[26:Res:13867.0,61.1] always3(s12) || -> . % 75.92/76.16 13870[26:SSi:13869.0,701.0] || -> . % 75.92/76.16 13871[26:Spt:13870.0,13865.1,13867.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.16 13872[26:Spt:13870.0,13865.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.16 13875[26:Res:13872.0,61.1] always3(s11) || -> . % 75.92/76.16 13876[26:SSi:13875.0,700.0,12947.0] || -> . % 75.92/76.16 13877[24:Spt:13876.0,12945.2,12946.0] || xuntil6(s10)*+ -> . % 75.92/76.16 13878[24:Spt:13876.0,12945.0,12945.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.16 13879[24:Res:53.1,13878.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.16 13884[25:Spt:13879.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.16 13886[25:Res:13884.0,61.1] always3(s10) || -> . % 75.92/76.16 13887[25:SSi:13886.0,699.0,12944.0] || -> . % 75.92/76.16 13888[25:Spt:13887.0,13879.0,13884.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.16 13889[25:Spt:13887.0,13879.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.16 13893[25:Res:13889.0,61.1] always3(s11) || -> . % 75.92/76.16 13894[25:SSi:13893.0,700.0] || -> . % 75.92/76.16 13895[23:Spt:13894.0,12939.2,12943.0] || xuntil6(s9)*+ -> . % 75.92/76.16 13896[23:Spt:13894.0,12939.0,12939.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.16 13897[23:Res:53.1,13896.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.16 13899[24:Spt:13897.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.16 13901[24:Res:13899.0,61.1] always3(s10) || -> . % 75.92/76.16 13902[24:SSi:13901.0,699.0] || -> . % 75.92/76.16 13903[24:Spt:13902.0,13897.1,13899.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.16 13904[24:Spt:13902.0,13897.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.16 13907[24:Res:13904.0,61.1] always3(s9) || -> . % 75.92/76.16 13908[24:SSi:13907.0,698.0,12938.0] || -> . % 75.92/76.16 13909[22:Spt:13908.0,12936.2,12937.0] || xuntil6(s8)*+ -> . % 75.92/76.16 13910[22:Spt:13908.0,12936.0,12936.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.16 13911[22:Res:53.1,13910.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.16 13913[23:Spt:13911.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.16 13915[23:Res:13913.0,61.1] always3(s9) || -> . % 75.92/76.16 13916[23:SSi:13915.0,698.0] || -> . % 75.92/76.16 13917[23:Spt:13916.0,13911.1,13913.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.16 13918[23:Spt:13916.0,13911.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.16 13921[23:Res:13918.0,61.1] always3(s8) || -> . % 75.92/76.16 13922[23:SSi:13921.0,697.0,12935.0] || -> . % 75.92/76.16 13923[21:Spt:13922.0,12930.2,12934.0] || xuntil6(s7)*+ -> . % 75.92/76.16 13924[21:Spt:13922.0,12930.0,12930.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.16 13925[21:Res:53.1,13924.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.16 13930[22:Spt:13925.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.16 13932[22:Res:13930.0,61.1] always3(s7) || -> . % 75.92/76.16 13933[22:SSi:13932.0,696.0,12929.0] || -> . % 75.92/76.16 13934[22:Spt:13933.0,13925.0,13930.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.16 13935[22:Spt:13933.0,13925.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.16 13939[22:Res:13935.0,61.1] always3(s8) || -> . % 75.92/76.16 13940[22:SSi:13939.0,697.0] || -> . % 75.92/76.16 13941[20:Spt:13940.0,12927.2,12928.0] || xuntil6(s6)*+ -> . % 75.92/76.16 13942[20:Spt:13940.0,12927.0,12927.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.16 13943[20:Res:53.1,13942.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.16 13945[21:Spt:13943.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.16 13947[21:Res:13945.0,61.1] always3(s7) || -> . % 75.92/76.16 13948[21:SSi:13947.0,696.0] || -> . % 75.92/76.16 13949[21:Spt:13948.0,13943.1,13945.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.16 13950[21:Spt:13948.0,13943.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.16 13953[21:Res:13950.0,61.1] always3(s6) || -> . % 75.92/76.16 13954[21:SSi:13953.0,695.0,12926.0] || -> . % 75.92/76.16 13955[19:Spt:13954.0,12921.2,12925.0] || xuntil6(s5)*+ -> . % 75.92/76.16 13956[19:Spt:13954.0,12921.0,12921.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.16 13957[19:Res:53.1,13956.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.16 13959[20:Spt:13957.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.16 13961[20:Res:13959.0,61.1] always3(s6) || -> . % 75.92/76.16 13962[20:SSi:13961.0,695.0] || -> . % 75.92/76.16 13963[20:Spt:13962.0,13957.1,13959.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.16 13964[20:Spt:13962.0,13957.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.16 13967[20:Res:13964.0,61.1] always3(s5) || -> . % 75.92/76.16 13968[20:SSi:13967.0,694.0,12920.0] || -> . % 75.92/76.16 13969[18:Spt:13968.0,12918.2,12919.0] || xuntil6(s4)*+ -> . % 75.92/76.16 13970[18:Spt:13968.0,12918.0,12918.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.16 13971[18:Res:53.1,13970.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.16 13976[19:Spt:13971.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.16 13978[19:Res:13976.0,61.1] always3(s4) || -> . % 75.92/76.16 13979[19:SSi:13978.0,693.0,12917.0] || -> . % 75.92/76.16 13980[19:Spt:13979.0,13971.0,13976.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.16 13981[19:Spt:13979.0,13971.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.16 13985[19:Res:13981.0,61.1] always3(s5) || -> . % 75.92/76.16 13986[19:SSi:13985.0,694.0] || -> . % 75.92/76.16 13987[17:Spt:13986.0,12912.2,12916.0] || xuntil6(s3)*+ -> . % 75.92/76.16 13988[17:Spt:13986.0,12912.0,12912.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.16 13989[17:Res:53.1,13988.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.16 13991[18:Spt:13989.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.16 13993[18:Res:13991.0,61.1] always3(s4) || -> . % 75.92/76.16 13994[18:SSi:13993.0,693.0] || -> . % 75.92/76.16 13995[18:Spt:13994.0,13989.1,13991.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.16 13996[18:Spt:13994.0,13989.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.16 13999[18:Res:13996.0,61.1] always3(s3) || -> . % 75.92/76.16 14000[18:SSi:13999.0,692.0,12911.0] || -> . % 75.92/76.16 14001[16:Spt:14000.0,12909.2,12910.0] || xuntil6(s2)*+ -> . % 75.92/76.16 14002[16:Spt:14000.0,12909.0,12909.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.16 14003[16:Res:53.1,14002.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.16 14005[17:Spt:14003.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.16 14007[17:Res:14005.0,61.1] always3(s3) || -> . % 75.92/76.16 14008[17:SSi:14007.0,692.0] || -> . % 75.92/76.16 14009[17:Spt:14008.0,14003.1,14005.0] || m_main_v_state(s3,c_busy)* -> . % 75.92/76.16 14010[17:Spt:14008.0,14003.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.16 14013[17:Res:14010.0,61.1] always3(s2) || -> . % 75.92/76.16 14014[17:SSi:14013.0,691.0,12908.0] || -> . % 75.92/76.16 14015[15:Spt:14014.0,12900.2,12907.0] || xuntil6(s1)*+ -> . % 75.92/76.16 14016[15:Spt:14014.0,12900.0,12900.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.16 14017[15:Res:53.1,14016.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.16 14022[16:Spt:14017.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.16 14024[16:Res:14022.0,61.1] always3(s1) || -> . % 75.92/76.16 14025[16:SSi:14024.0,690.0,12899.0] || -> . % 75.92/76.16 14026[16:Spt:14025.0,14017.0,14022.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.16 14027[16:Spt:14025.0,14017.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.16 14032[16:Res:14027.0,61.1] always3(s2) || -> . % 75.92/76.16 14033[16:SSi:14032.0,691.0] || -> . % 75.92/76.16 14034[14:Spt:14033.0,74.0,12898.0] || xuntil6(s0)*+ -> . % 75.92/76.16 14035[14:Spt:14033.0,74.1] || -> node4(s0)*. % 75.92/76.16 14036[14:MRR:758.1,14034.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.16 14038[14:Res:14036.0,61.1] always3(s1) || -> . % 75.92/76.16 14039[14:SSi:14038.0,690.0] || -> . % 75.92/76.16 14040[13:Spt:14039.0,12888.0,12892.0] || trans(s49,s38)*+ -> . % 75.92/76.16 14041[13:Spt:14039.0,12888.1,12888.2,12888.3,12888.4,12888.5,12888.6,12888.7,12888.8,12888.9,12888.10,12888.11,12888.12,12888.13,12888.14,12888.15,12888.16,12888.17,12888.18,12888.19,12888.20,12888.21,12888.22,12888.23,12888.24,12888.25,12888.26,12888.27,12888.28,12888.29,12888.30,12888.31,12888.32,12888.33,12888.34,12888.35,12888.36,12888.37,12888.38] || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.16 14043[13:MRR:12889.0,14040.0] || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.16 14044[13:MRR:12891.1,14040.0] xuntil6(s49) || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.16 14045[14:Spt:14041.0] || -> trans(s49,s37)*. % 75.92/76.16 14046[14:Res:14045.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s37)*. % 75.92/76.16 14048[14:Res:14045.0,60.0] || -> node2(s49,s37)*. % 75.92/76.16 14049[14:SSi:14046.1,50.0,738.0] xuntil6(s49) || -> until2p7(s37)*. % 75.92/76.16 14050[14:Res:14048.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)*. % 75.92/76.16 14051[15:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.16 14052[15:MRR:176.0,14051.0] || -> until5(s1)*. % 75.92/76.16 14053[15:MRR:12022.0,14052.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.16 14057[16:Spt:14053.2] || -> xuntil6(s1)*. % 75.92/76.16 14058[16:MRR:175.0,14057.0] || -> until5(s2)*. % 75.92/76.16 14059[16:MRR:12018.0,14058.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.16 14060[17:Spt:14059.2] || -> xuntil6(s2)*. % 75.92/76.16 14061[17:MRR:174.0,14060.0] || -> until5(s3)*. % 75.92/76.16 14062[17:MRR:12014.0,14061.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.16 14063[18:Spt:14062.2] || -> xuntil6(s3)*. % 75.92/76.16 14064[18:MRR:173.0,14063.0] || -> until5(s4)*. % 75.92/76.16 14065[18:MRR:12010.0,14064.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.16 14066[19:Spt:14065.2] || -> xuntil6(s4)*. % 75.92/76.16 14067[19:MRR:172.0,14066.0] || -> until5(s5)*. % 75.92/76.16 14068[19:MRR:12009.0,14067.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.16 14072[20:Spt:14068.2] || -> xuntil6(s5)*. % 75.92/76.16 14073[20:MRR:171.0,14072.0] || -> until5(s6)*. % 75.92/76.16 14074[20:MRR:12002.0,14073.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.16 14075[21:Spt:14074.2] || -> xuntil6(s6)*. % 75.92/76.16 14076[21:MRR:170.0,14075.0] || -> until5(s7)*. % 75.92/76.16 14077[21:MRR:11998.0,14076.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.16 14081[22:Spt:14077.2] || -> xuntil6(s7)*. % 75.92/76.16 14082[22:MRR:169.0,14081.0] || -> until5(s8)*. % 75.92/76.16 14083[22:MRR:11994.0,14082.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.16 14084[23:Spt:14083.2] || -> xuntil6(s8)*. % 75.92/76.16 14085[23:MRR:168.0,14084.0] || -> until5(s9)*. % 75.92/76.16 14086[23:MRR:11990.0,14085.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.16 14090[24:Spt:14086.2] || -> xuntil6(s9)*. % 75.92/76.16 14091[24:MRR:167.0,14090.0] || -> until5(s10)*. % 75.92/76.16 14092[24:MRR:11989.0,14091.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.16 14093[25:Spt:14092.2] || -> xuntil6(s10)*. % 75.92/76.16 14094[25:MRR:166.0,14093.0] || -> until5(s11)*. % 75.92/76.16 14095[25:MRR:11982.0,14094.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.16 14099[26:Spt:14095.2] || -> xuntil6(s11)*. % 75.92/76.16 14100[26:MRR:165.0,14099.0] || -> until5(s12)*. % 75.92/76.16 14101[26:MRR:11978.0,14100.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.16 14102[27:Spt:14101.2] || -> xuntil6(s12)*. % 75.92/76.16 14103[27:MRR:164.0,14102.0] || -> until5(s13)*. % 75.92/76.16 14104[27:MRR:11974.0,14103.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.16 14108[28:Spt:14104.2] || -> xuntil6(s13)*. % 75.92/76.16 14109[28:MRR:163.0,14108.0] || -> until5(s14)*. % 75.92/76.16 14110[28:MRR:11970.0,14109.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.16 14111[29:Spt:14110.2] || -> xuntil6(s14)*. % 75.92/76.16 14112[29:MRR:162.0,14111.0] || -> until5(s15)*. % 75.92/76.16 14113[29:MRR:11969.0,14112.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.16 14117[30:Spt:14113.2] || -> xuntil6(s15)*. % 75.92/76.16 14118[30:MRR:161.0,14117.0] || -> until5(s16)*. % 75.92/76.16 14119[30:MRR:11962.0,14118.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.16 14120[31:Spt:14119.2] || -> xuntil6(s16)*. % 75.92/76.16 14121[31:MRR:160.0,14120.0] || -> until5(s17)*. % 75.92/76.16 14122[31:MRR:11958.0,14121.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.16 14126[32:Spt:14122.2] || -> xuntil6(s17)*. % 75.92/76.16 14127[32:MRR:159.0,14126.0] || -> until5(s18)*. % 75.92/76.16 14128[32:MRR:11954.0,14127.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.16 14129[33:Spt:14128.2] || -> xuntil6(s18)*. % 75.92/76.16 14130[33:MRR:158.0,14129.0] || -> until5(s19)*. % 75.92/76.16 14131[33:MRR:11950.0,14130.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.16 14135[34:Spt:14131.2] || -> xuntil6(s19)*. % 75.92/76.16 14136[34:MRR:157.0,14135.0] || -> until5(s20)*. % 75.92/76.16 14137[34:MRR:11949.0,14136.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.16 14138[35:Spt:14137.2] || -> xuntil6(s20)*. % 75.92/76.16 14139[35:MRR:156.0,14138.0] || -> until5(s21)*. % 75.92/76.16 14140[35:MRR:11942.0,14139.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.16 14144[36:Spt:14140.2] || -> xuntil6(s21)*. % 75.92/76.16 14145[36:MRR:155.0,14144.0] || -> until5(s22)*. % 75.92/76.16 14146[36:MRR:11938.0,14145.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.16 14147[37:Spt:14146.2] || -> xuntil6(s22)*. % 75.92/76.16 14148[37:MRR:154.0,14147.0] || -> until5(s23)*. % 75.92/76.16 14149[37:MRR:11934.0,14148.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.16 14153[38:Spt:14149.2] || -> xuntil6(s23)*. % 75.92/76.16 14154[38:MRR:153.0,14153.0] || -> until5(s24)*. % 75.92/76.16 14155[38:MRR:11930.0,14154.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.16 14156[39:Spt:14155.2] || -> xuntil6(s24)*. % 75.92/76.16 14157[39:MRR:152.0,14156.0] || -> until5(s25)*. % 75.92/76.16 14158[39:MRR:11929.0,14157.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.16 14162[40:Spt:14158.2] || -> xuntil6(s25)*. % 75.92/76.16 14163[40:MRR:151.0,14162.0] || -> until5(s26)*. % 75.92/76.16 14164[40:MRR:11922.0,14163.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.16 14165[41:Spt:14164.2] || -> xuntil6(s26)*. % 75.92/76.16 14166[41:MRR:150.0,14165.0] || -> until5(s27)*. % 75.92/76.16 14167[41:MRR:11918.0,14166.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.16 14171[42:Spt:14167.2] || -> xuntil6(s27)*. % 75.92/76.16 14172[42:MRR:149.0,14171.0] || -> until5(s28)*. % 75.92/76.16 14173[42:MRR:11914.0,14172.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.16 14174[43:Spt:14173.2] || -> xuntil6(s28)*. % 75.92/76.16 14175[43:MRR:148.0,14174.0] || -> until5(s29)*. % 75.92/76.16 14176[43:MRR:11910.0,14175.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.16 14180[44:Spt:14176.2] || -> xuntil6(s29)*. % 75.92/76.16 14181[44:MRR:147.0,14180.0] || -> until5(s30)*. % 75.92/76.16 14182[44:MRR:11909.0,14181.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.16 14183[45:Spt:14182.2] || -> xuntil6(s30)*. % 75.92/76.16 14184[45:MRR:146.0,14183.0] || -> until5(s31)*. % 75.92/76.16 14185[45:MRR:11905.0,14184.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.16 14189[46:Spt:14185.2] || -> xuntil6(s31)*. % 75.92/76.16 14190[46:MRR:145.0,14189.0] || -> until5(s32)*. % 75.92/76.16 14191[46:MRR:11904.0,14190.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.16 14192[47:Spt:14191.2] || -> xuntil6(s32)*. % 75.92/76.16 14193[47:MRR:144.0,14192.0] || -> until5(s33)*. % 75.92/76.16 14194[47:MRR:932.0,14193.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.16 14198[48:Spt:14194.2] || -> xuntil6(s33)*. % 75.92/76.16 14199[48:MRR:143.0,14198.0] || -> until5(s34)*. % 75.92/76.16 14200[48:MRR:12029.0,14199.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.16 14201[49:Spt:14200.1] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.16 14203[49:Res:14201.0,61.1] always3(s35) || -> . % 75.92/76.16 14204[49:SSi:14203.0,724.0] || -> . % 75.92/76.16 14205[49:Spt:14204.0,14200.1,14201.0] || m_main_v_state(s35,c_busy)*+ -> . % 75.92/76.16 14206[49:Spt:14204.0,14200.0,14200.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 75.92/76.16 14209[49:Res:53.1,14206.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 75.92/76.16 14214[50:Spt:14209.1] || -> xuntil6(s34)*. % 75.92/76.16 14215[50:MRR:142.0,14214.0] || -> until5(s35)*. % 75.92/76.16 14216[50:MRR:930.0,14215.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.16 14218[51:Spt:14216.2] || -> xuntil6(s35)*. % 75.92/76.16 14219[51:MRR:141.0,14218.0] || -> until5(s36)*. % 75.92/76.16 14220[51:MRR:12033.0,14219.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.16 14221[52:Spt:14220.1] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.16 14223[52:Res:14221.0,61.1] always3(s37) || -> . % 75.92/76.16 14224[52:SSi:14223.0,726.0] || -> . % 75.92/76.16 14225[52:Spt:14224.0,14220.1,14221.0] || m_main_v_state(s37,c_busy)*+ -> . % 75.92/76.16 14226[52:Spt:14224.0,14220.0,14220.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 75.92/76.16 14229[52:MRR:14050.2,14225.0] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.16 14230[52:Res:53.1,14226.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 75.92/76.16 14232[53:Spt:14230.1] || -> xuntil6(s36)*. % 75.92/76.16 14233[53:MRR:140.0,14232.0] || -> until5(s37)*. % 75.92/76.16 14234[53:MRR:928.0,14233.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.16 14240[52:SoR:14229.0,64.1] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.16 14242[52:SoR:14240.0,66.2] until5(s49) || m_main_v_state(s49,c_ready)* -> xuntil6(s49). % 75.92/76.16 14243[54:Spt:14234.2] || -> xuntil6(s37)*. % 75.92/76.16 14244[54:MRR:139.0,14243.0] || -> until5(s38)*. % 75.92/76.16 14245[54:MRR:12040.0,14244.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.16 14246[55:Spt:14245.1] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.16 14248[55:Res:14246.0,61.1] always3(s39) || -> . % 75.92/76.16 14249[55:SSi:14248.0,728.0] || -> . % 75.92/76.16 14250[55:Spt:14249.0,14245.1,14246.0] || m_main_v_state(s39,c_busy)*+ -> . % 75.92/76.16 14251[55:Spt:14249.0,14245.0,14245.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 75.92/76.16 14253[55:MRR:804.2,14250.0] node4(s38) || m_main_v_state(s38,c_ready)* -> . % 75.92/76.16 14254[55:Res:53.1,14251.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 75.92/76.16 14256[56:Spt:14254.1] || -> xuntil6(s38)*. % 75.92/76.16 14257[56:MRR:138.0,14256.0] || -> until5(s39)*. % 75.92/76.16 14258[56:MRR:926.0,14257.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.16 14263[57:Spt:14258.2] || -> xuntil6(s39)*. % 75.92/76.16 14264[57:MRR:137.0,14263.0] || -> until5(s40)*. % 75.92/76.16 14265[57:MRR:12041.0,14264.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.16 14269[58:Spt:14265.1] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.16 14271[58:Res:14269.0,61.1] always3(s41) || -> . % 75.92/76.16 14272[58:SSi:14271.0,730.0] || -> . % 75.92/76.16 14273[58:Spt:14272.0,14265.1,14269.0] || m_main_v_state(s41,c_busy)*+ -> . % 75.92/76.16 14274[58:Spt:14272.0,14265.0,14265.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 75.92/76.16 14276[58:MRR:798.2,14273.0] node4(s40) || m_main_v_state(s40,c_ready)* -> . % 75.92/76.16 14277[58:Res:53.1,14274.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 75.92/76.16 14279[59:Spt:14277.1] || -> xuntil6(s40)*. % 75.92/76.16 14280[59:MRR:136.0,14279.0] || -> until5(s41)*. % 75.92/76.16 14281[59:MRR:924.0,14280.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.16 14286[60:Spt:14281.2] || -> xuntil6(s41)*. % 75.92/76.16 14287[60:MRR:135.0,14286.0] || -> until5(s42)*. % 75.92/76.16 14288[60:MRR:12045.0,14287.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.16 14289[61:Spt:14288.1] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.16 14291[61:Res:14289.0,61.1] always3(s43) || -> . % 75.92/76.16 14292[61:SSi:14291.0,732.0] || -> . % 75.92/76.16 14293[61:Spt:14292.0,14288.1,14289.0] || m_main_v_state(s43,c_busy)*+ -> . % 75.92/76.16 14294[61:Spt:14292.0,14288.0,14288.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 75.92/76.16 14296[61:MRR:792.2,14293.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 75.92/76.16 14297[61:Res:53.1,14294.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 75.92/76.16 14299[62:Spt:14297.1] || -> xuntil6(s42)*. % 75.92/76.16 14300[62:MRR:134.0,14299.0] || -> until5(s43)*. % 75.92/76.16 14301[62:MRR:922.0,14300.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.16 14309[63:Spt:14301.2] || -> xuntil6(s43)*. % 75.92/76.16 14310[63:MRR:133.0,14309.0] || -> until5(s44)*. % 75.92/76.16 14311[63:MRR:12049.0,14310.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.16 14312[64:Spt:14311.1] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.16 14314[64:Res:14312.0,61.1] always3(s45) || -> . % 75.92/76.16 14315[64:SSi:14314.0,734.0] || -> . % 75.92/76.16 14316[64:Spt:14315.0,14311.1,14312.0] || m_main_v_state(s45,c_busy)*+ -> . % 75.92/76.16 14317[64:Spt:14315.0,14311.0,14311.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 75.92/76.16 14319[64:MRR:786.2,14316.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 75.92/76.16 14320[64:Res:53.1,14317.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 75.92/76.16 14325[65:Spt:14320.1] || -> xuntil6(s44)*. % 75.92/76.16 14326[65:MRR:132.0,14325.0] || -> until5(s45)*. % 75.92/76.16 14327[65:MRR:920.0,14326.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.16 14329[66:Spt:14327.2] || -> xuntil6(s45)*. % 75.92/76.16 14330[66:MRR:131.0,14329.0] || -> until5(s46)*. % 75.92/76.16 14331[66:MRR:12053.0,14330.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.16 14332[67:Spt:14331.1] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.16 14334[67:Res:14332.0,61.1] always3(s47) || -> . % 75.92/76.16 14335[67:SSi:14334.0,736.0] || -> . % 75.92/76.16 14336[67:Spt:14335.0,14331.1,14332.0] || m_main_v_state(s47,c_busy)*+ -> . % 75.92/76.16 14337[67:Spt:14335.0,14331.0,14331.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 75.92/76.16 14339[67:MRR:780.2,14336.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 75.92/76.16 14340[67:Res:53.1,14337.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 75.92/76.16 14342[68:Spt:14340.1] || -> xuntil6(s46)*. % 75.92/76.16 14343[68:MRR:130.0,14342.0] || -> until5(s47)*. % 75.92/76.16 14344[68:MRR:918.0,14343.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.16 14349[69:Spt:14344.2] || -> xuntil6(s47)*. % 75.92/76.16 14350[69:MRR:129.0,14349.0] || -> until5(s48)*. % 75.92/76.16 14351[69:MRR:12057.0,14350.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.16 14352[70:Spt:14351.1] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.16 14354[70:Res:14352.0,61.1] always3(s49) || -> . % 75.92/76.16 14355[70:SSi:14354.0,50.0,738.0] || -> . % 75.92/76.16 14356[70:Spt:14355.0,14351.1,14352.0] || m_main_v_state(s49,c_busy)*+ -> . % 75.92/76.16 14357[70:Spt:14355.0,14351.0,14351.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 75.92/76.16 14359[70:MRR:774.2,14356.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 75.92/76.16 14360[70:Res:53.1,14357.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 75.92/76.16 14362[71:Spt:14360.1] || -> xuntil6(s48)*. % 75.92/76.16 14363[71:MRR:128.0,14362.0] || -> until5(s49)*. % 75.92/76.16 14364[71:MRR:14242.0,14363.0] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.16 14365[71:Res:53.1,14364.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.16 14367[71:MRR:14365.0,14356.0] || -> xuntil6(s49)*. % 75.92/76.16 14368[71:MRR:14049.0,14367.0] || -> until2p7(s37)*. % 75.92/76.16 14369[71:MRR:235.0,14368.0] || -> until2p7(s38)* node4(s37). % 75.92/76.16 14370[72:Spt:14369.0] || -> until2p7(s38)*. % 75.92/76.16 14371[72:MRR:236.0,14370.0] || -> until2p7(s39)* node4(s38). % 75.92/76.16 14372[73:Spt:14371.0] || -> until2p7(s39)*. % 75.92/76.16 14373[73:MRR:237.0,14372.0] || -> until2p7(s40)* node4(s39). % 75.92/76.16 14374[74:Spt:14373.0] || -> until2p7(s40)*. % 75.92/76.16 14375[74:MRR:238.0,14374.0] || -> until2p7(s41)* node4(s40). % 75.92/76.16 14376[75:Spt:14375.0] || -> until2p7(s41)*. % 75.92/76.16 14377[75:MRR:239.0,14376.0] || -> until2p7(s42)* node4(s41). % 75.92/76.16 14378[76:Spt:14377.0] || -> until2p7(s42)*. % 75.92/76.16 14379[76:MRR:240.0,14378.0] || -> until2p7(s43)* node4(s42). % 75.92/76.16 14380[77:Spt:14379.0] || -> until2p7(s43)*. % 75.92/76.16 14381[77:MRR:241.0,14380.0] || -> until2p7(s44)* node4(s43). % 75.92/76.16 14382[78:Spt:14381.0] || -> until2p7(s44)*. % 75.92/76.16 14383[78:MRR:539.0,14382.0] || -> until2p7(s45)* node4(s44). % 75.92/76.16 14384[79:Spt:14383.0] || -> until2p7(s45)*. % 75.92/76.16 14385[79:MRR:544.0,14384.0] || -> until2p7(s46)* node4(s45). % 75.92/76.16 14386[80:Spt:14385.0] || -> until2p7(s46)*. % 75.92/76.16 14387[80:MRR:549.0,14386.0] || -> until2p7(s47)* node4(s46). % 75.92/76.16 14388[81:Spt:14387.0] || -> until2p7(s47)*. % 75.92/76.16 14389[81:MRR:554.0,14388.0] || -> until2p7(s48)* node4(s47). % 75.92/76.16 14390[82:Spt:14389.0] || -> until2p7(s48)*. % 75.92/76.16 14391[82:MRR:559.0,14390.0] || -> until2p7(s49)* node4(s48). % 75.92/76.16 14392[83:Spt:14391.0] || -> until2p7(s49)*. % 75.92/76.16 14393[83:MRR:194.0,14392.0] || -> node4(s49)*. % 75.92/76.16 14394[83:MRR:14240.0,14393.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.16 14395[83:Res:53.1,14394.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.16 14397[83:MRR:14395.0,14356.0] || -> . % 75.92/76.16 14398[83:Spt:14397.0,14391.0,14392.0] || until2p7(s49)*+ -> . % 75.92/76.16 14399[83:Spt:14397.0,14391.1] || -> node4(s48)*. % 75.92/76.16 14400[83:MRR:14359.0,14399.0] || m_main_v_state(s48,c_ready)*+ -> . % 75.92/76.16 14403[83:Res:53.1,14400.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.16 14406[83:Res:14403.0,61.1] always3(s48) || -> . % 75.92/76.16 14407[83:SSi:14406.0,737.0,14350.0,14362.0,14390.0,14399.0] || -> . % 75.92/76.16 14408[82:Spt:14407.0,14389.0,14390.0] || until2p7(s48)*+ -> . % 75.92/76.16 14409[82:Spt:14407.0,14389.1] || -> node4(s47)*. % 75.92/76.16 14411[82:MRR:777.0,14409.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 75.92/76.16 14422[82:Res:53.1,14411.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 75.92/76.16 14424[82:MRR:14422.0,14336.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.16 14426[82:Res:14424.0,61.1] always3(s48) || -> . % 75.92/76.16 14427[82:SSi:14426.0,737.0,14350.0,14362.0] || -> . % 75.92/76.16 14428[81:Spt:14427.0,14387.0,14388.0] || until2p7(s47)*+ -> . % 75.92/76.16 14429[81:Spt:14427.0,14387.1] || -> node4(s46)*. % 75.92/76.16 14430[81:MRR:14339.0,14429.0] || m_main_v_state(s46,c_ready)*+ -> . % 75.92/76.16 14433[81:Res:53.1,14430.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.16 14436[81:Res:14433.0,61.1] always3(s46) || -> . % 75.92/76.16 14437[81:SSi:14436.0,735.0,14330.0,14342.0,14386.0,14429.0] || -> . % 75.92/76.16 14438[80:Spt:14437.0,14385.0,14386.0] || until2p7(s46)*+ -> . % 75.92/76.16 14439[80:Spt:14437.0,14385.1] || -> node4(s45)*. % 75.92/76.16 14441[80:MRR:783.0,14439.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 75.92/76.16 14453[80:Res:53.1,14441.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 75.92/76.16 14455[80:MRR:14453.0,14316.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.16 14460[80:Res:14455.0,61.1] always3(s46) || -> . % 75.92/76.16 14461[80:SSi:14460.0,735.0,14330.0,14342.0] || -> . % 75.92/76.16 14462[79:Spt:14461.0,14383.0,14384.0] || until2p7(s45)*+ -> . % 75.92/76.16 14463[79:Spt:14461.0,14383.1] || -> node4(s44)*. % 75.92/76.16 14464[79:MRR:14319.0,14463.0] || m_main_v_state(s44,c_ready)*+ -> . % 75.92/76.16 14467[79:Res:53.1,14464.0] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.16 14471[79:Res:14467.0,61.1] always3(s44) || -> . % 75.92/76.16 14472[79:SSi:14471.0,733.0,14310.0,14325.0,14382.0,14463.0] || -> . % 75.92/76.16 14473[78:Spt:14472.0,14381.0,14382.0] || until2p7(s44)*+ -> . % 75.92/76.16 14474[78:Spt:14472.0,14381.1] || -> node4(s43)*. % 75.92/76.16 14476[78:MRR:789.0,14474.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 75.92/76.16 14487[78:Res:53.1,14476.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 75.92/76.16 14489[78:MRR:14487.0,14293.0] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.16 14491[78:Res:14489.0,61.1] always3(s44) || -> . % 75.92/76.16 14492[78:SSi:14491.0,733.0,14310.0,14325.0] || -> . % 75.92/76.16 14493[77:Spt:14492.0,14379.0,14380.0] || until2p7(s43)*+ -> . % 75.92/76.16 14494[77:Spt:14492.0,14379.1] || -> node4(s42)*. % 75.92/76.16 14495[77:MRR:14296.0,14494.0] || m_main_v_state(s42,c_ready)*+ -> . % 75.92/76.16 14499[77:Res:53.1,14495.0] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.16 14502[77:Res:14499.0,61.1] always3(s42) || -> . % 75.92/76.16 14503[77:SSi:14502.0,731.0,14287.0,14299.0,14378.0,14494.0] || -> . % 75.92/76.16 14504[76:Spt:14503.0,14377.0,14378.0] || until2p7(s42)*+ -> . % 75.92/76.16 14505[76:Spt:14503.0,14377.1] || -> node4(s41)*. % 75.92/76.16 14507[76:MRR:795.0,14505.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 75.92/76.16 14518[76:Res:53.1,14507.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 75.92/76.16 14520[76:MRR:14518.0,14273.0] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.16 14522[76:Res:14520.0,61.1] always3(s42) || -> . % 75.92/76.16 14523[76:SSi:14522.0,731.0,14287.0,14299.0] || -> . % 75.92/76.16 14524[75:Spt:14523.0,14375.0,14376.0] || until2p7(s41)*+ -> . % 75.92/76.16 14525[75:Spt:14523.0,14375.1] || -> node4(s40)*. % 75.92/76.16 14526[75:MRR:14276.0,14525.0] || m_main_v_state(s40,c_ready)*+ -> . % 75.92/76.16 14529[75:Res:53.1,14526.0] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.16 14532[75:Res:14529.0,61.1] always3(s40) || -> . % 75.92/76.16 14533[75:SSi:14532.0,729.0,14264.0,14279.0,14374.0,14525.0] || -> . % 75.92/76.16 14534[74:Spt:14533.0,14373.0,14374.0] || until2p7(s40)*+ -> . % 75.92/76.16 14535[74:Spt:14533.0,14373.1] || -> node4(s39)*. % 75.92/76.16 14537[74:MRR:801.0,14535.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 75.92/76.16 14549[74:Res:53.1,14537.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 75.92/76.16 14551[74:MRR:14549.0,14250.0] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.16 14553[74:Res:14551.0,61.1] always3(s40) || -> . % 75.92/76.16 14554[74:SSi:14553.0,729.0,14264.0,14279.0] || -> . % 75.92/76.16 14555[73:Spt:14554.0,14371.0,14372.0] || until2p7(s39)*+ -> . % 75.92/76.16 14556[73:Spt:14554.0,14371.1] || -> node4(s38)*. % 75.92/76.16 14557[73:MRR:14253.0,14556.0] || m_main_v_state(s38,c_ready)*+ -> . % 75.92/76.16 14560[73:Res:53.1,14557.0] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.16 14563[73:Res:14560.0,61.1] always3(s38) || -> . % 75.92/76.16 14564[73:SSi:14563.0,727.0,14244.0,14256.0,14370.0,14556.0] || -> . % 75.92/76.16 14565[72:Spt:14564.0,14369.0,14370.0] || until2p7(s38)*+ -> . % 75.92/76.16 14566[72:Spt:14564.0,14369.1] || -> node4(s37)*. % 75.92/76.16 14568[72:MRR:807.0,14566.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 75.92/76.16 14580[72:Res:53.1,14568.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 75.92/76.16 14582[72:MRR:14580.0,14225.0] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.16 14587[72:Res:14582.0,61.1] always3(s38) || -> . % 75.92/76.16 14588[72:SSi:14587.0,727.0,14244.0,14256.0] || -> . % 75.92/76.16 14589[71:Spt:14588.0,14360.1,14362.0] || xuntil6(s48)* -> . % 75.92/76.16 14590[71:Spt:14588.0,14360.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.16 14593[71:Res:14590.0,61.1] always3(s48) || -> . % 75.92/76.16 14594[71:SSi:14593.0,737.0,14350.0] || -> . % 75.92/76.16 14595[69:Spt:14594.0,14344.2,14349.0] || xuntil6(s47)*+ -> . % 75.92/76.16 14596[69:Spt:14594.0,14344.0,14344.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 75.92/76.16 14597[69:Res:53.1,14596.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 75.92/76.16 14599[69:MRR:14597.0,14336.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.16 14601[69:Res:14599.0,61.1] always3(s48) || -> . % 75.92/76.16 14602[69:SSi:14601.0,737.0] || -> . % 75.92/76.16 14603[68:Spt:14602.0,14340.1,14342.0] || xuntil6(s46)* -> . % 75.92/76.16 14604[68:Spt:14602.0,14340.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.16 14607[68:Res:14604.0,61.1] always3(s46) || -> . % 75.92/76.16 14608[68:SSi:14607.0,735.0,14330.0] || -> . % 75.92/76.16 14609[66:Spt:14608.0,14327.2,14329.0] || xuntil6(s45)*+ -> . % 75.92/76.16 14610[66:Spt:14608.0,14327.0,14327.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 75.92/76.16 14611[66:Res:53.1,14610.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 75.92/76.16 14613[66:MRR:14611.0,14316.0] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.16 14616[66:Res:14613.0,61.1] always3(s46) || -> . % 75.92/76.16 14617[66:SSi:14616.0,735.0] || -> . % 75.92/76.16 14618[65:Spt:14617.0,14320.1,14325.0] || xuntil6(s44)* -> . % 75.92/76.16 14619[65:Spt:14617.0,14320.0] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.16 14622[65:Res:14619.0,61.1] always3(s44) || -> . % 75.92/76.16 14623[65:SSi:14622.0,733.0,14310.0] || -> . % 75.92/76.16 14624[63:Spt:14623.0,14301.2,14309.0] || xuntil6(s43)*+ -> . % 75.92/76.16 14625[63:Spt:14623.0,14301.0,14301.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 75.92/76.16 14626[63:Res:53.1,14625.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 75.92/76.16 14628[63:MRR:14626.0,14293.0] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.16 14630[63:Res:14628.0,61.1] always3(s44) || -> . % 75.92/76.16 14631[63:SSi:14630.0,733.0] || -> . % 75.92/76.16 14632[62:Spt:14631.0,14297.1,14299.0] || xuntil6(s42)* -> . % 75.92/76.16 14633[62:Spt:14631.0,14297.0] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.16 14636[62:Res:14633.0,61.1] always3(s42) || -> . % 75.92/76.16 14637[62:SSi:14636.0,731.0,14287.0] || -> . % 75.92/76.16 14638[60:Spt:14637.0,14281.2,14286.0] || xuntil6(s41)*+ -> . % 75.92/76.16 14639[60:Spt:14637.0,14281.0,14281.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 75.92/76.16 14640[60:Res:53.1,14639.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 75.92/76.16 14642[60:MRR:14640.0,14273.0] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.16 14644[60:Res:14642.0,61.1] always3(s42) || -> . % 75.92/76.16 14645[60:SSi:14644.0,731.0] || -> . % 75.92/76.16 14646[59:Spt:14645.0,14277.1,14279.0] || xuntil6(s40)* -> . % 75.92/76.16 14647[59:Spt:14645.0,14277.0] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.16 14650[59:Res:14647.0,61.1] always3(s40) || -> . % 75.92/76.16 14651[59:SSi:14650.0,729.0,14264.0] || -> . % 75.92/76.16 14652[57:Spt:14651.0,14258.2,14263.0] || xuntil6(s39)*+ -> . % 75.92/76.16 14653[57:Spt:14651.0,14258.0,14258.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 75.92/76.16 14654[57:Res:53.1,14653.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 75.92/76.16 14656[57:MRR:14654.0,14250.0] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.16 14658[57:Res:14656.0,61.1] always3(s40) || -> . % 75.92/76.16 14659[57:SSi:14658.0,729.0] || -> . % 75.92/76.16 14660[56:Spt:14659.0,14254.1,14256.0] || xuntil6(s38)* -> . % 75.92/76.16 14661[56:Spt:14659.0,14254.0] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.16 14664[56:Res:14661.0,61.1] always3(s38) || -> . % 75.92/76.16 14665[56:SSi:14664.0,727.0,14244.0] || -> . % 75.92/76.16 14666[54:Spt:14665.0,14234.2,14243.0] || xuntil6(s37)*+ -> . % 75.92/76.16 14667[54:Spt:14665.0,14234.0,14234.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 75.92/76.16 14668[54:Res:53.1,14667.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 75.92/76.16 14670[54:MRR:14668.0,14225.0] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.16 14673[54:Res:14670.0,61.1] always3(s38) || -> . % 75.92/76.16 14674[54:SSi:14673.0,727.0] || -> . % 75.92/76.16 14675[53:Spt:14674.0,14230.1,14232.0] || xuntil6(s36)* -> . % 75.92/76.16 14676[53:Spt:14674.0,14230.0] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.16 14679[53:Res:14676.0,61.1] always3(s36) || -> . % 75.92/76.16 14680[53:SSi:14679.0,725.0,14219.0] || -> . % 75.92/76.16 14681[51:Spt:14680.0,14216.2,14218.0] || xuntil6(s35)*+ -> . % 75.92/76.16 14682[51:Spt:14680.0,14216.0,14216.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 75.92/76.16 14683[51:Res:53.1,14682.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 75.92/76.16 14685[51:MRR:14683.0,14205.0] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.16 14687[51:Res:14685.0,61.1] always3(s36) || -> . % 75.92/76.16 14688[51:SSi:14687.0,725.0] || -> . % 75.92/76.16 14689[50:Spt:14688.0,14209.1,14214.0] || xuntil6(s34)* -> . % 75.92/76.16 14690[50:Spt:14688.0,14209.0] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.16 14693[50:Res:14690.0,61.1] always3(s34) || -> . % 75.92/76.16 14694[50:SSi:14693.0,723.0,14199.0] || -> . % 75.92/76.16 14695[48:Spt:14694.0,14194.2,14198.0] || xuntil6(s33)*+ -> . % 75.92/76.16 14696[48:Spt:14694.0,14194.0,14194.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 75.92/76.16 14697[48:Res:53.1,14696.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 75.92/76.16 14699[49:Spt:14697.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.16 14701[49:Res:14699.0,61.1] always3(s33) || -> . % 75.92/76.16 14702[49:SSi:14701.0,722.0,14193.0] || -> . % 75.92/76.17 14703[49:Spt:14702.0,14697.0,14699.0] || m_main_v_state(s33,c_busy)* -> . % 75.92/76.17 14704[49:Spt:14702.0,14697.1] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.17 14708[49:Res:14704.0,61.1] always3(s34) || -> . % 75.92/76.17 14709[49:SSi:14708.0,723.0] || -> . % 75.92/76.17 14710[47:Spt:14709.0,14191.2,14192.0] || xuntil6(s32)*+ -> . % 75.92/76.17 14711[47:Spt:14709.0,14191.0,14191.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 75.92/76.17 14712[47:Res:53.1,14711.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 75.92/76.17 14714[48:Spt:14712.0] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.17 14716[48:Res:14714.0,61.1] always3(s32) || -> . % 75.92/76.17 14717[48:SSi:14716.0,721.0,14190.0] || -> . % 75.92/76.17 14718[48:Spt:14717.0,14712.0,14714.0] || m_main_v_state(s32,c_busy)* -> . % 75.92/76.17 14719[48:Spt:14717.0,14712.1] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.17 14723[48:Res:14719.0,61.1] always3(s33) || -> . % 75.92/76.17 14724[48:SSi:14723.0,722.0] || -> . % 75.92/76.17 14725[46:Spt:14724.0,14185.2,14189.0] || xuntil6(s31)*+ -> . % 75.92/76.17 14726[46:Spt:14724.0,14185.0,14185.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 75.92/76.17 14727[46:Res:53.1,14726.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 75.92/76.17 14729[47:Spt:14727.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.17 14731[47:Res:14729.0,61.1] always3(s31) || -> . % 75.92/76.17 14732[47:SSi:14731.0,720.0,14184.0] || -> . % 75.92/76.17 14733[47:Spt:14732.0,14727.0,14729.0] || m_main_v_state(s31,c_busy)* -> . % 75.92/76.17 14734[47:Spt:14732.0,14727.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.17 14738[47:Res:14734.0,61.1] always3(s32) || -> . % 75.92/76.17 14739[47:SSi:14738.0,721.0] || -> . % 75.92/76.17 14740[45:Spt:14739.0,14182.2,14183.0] || xuntil6(s30)*+ -> . % 75.92/76.17 14741[45:Spt:14739.0,14182.0,14182.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.17 14742[45:Res:53.1,14741.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.17 14744[46:Spt:14742.1] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.17 14746[46:Res:14744.0,61.1] always3(s31) || -> . % 75.92/76.17 14747[46:SSi:14746.0,720.0] || -> . % 75.92/76.17 14748[46:Spt:14747.0,14742.1,14744.0] || m_main_v_state(s31,c_busy)* -> . % 75.92/76.17 14749[46:Spt:14747.0,14742.0] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.17 14752[46:Res:14749.0,61.1] always3(s30) || -> . % 75.92/76.17 14753[46:SSi:14752.0,719.0,14181.0] || -> . % 75.92/76.17 14754[44:Spt:14753.0,14176.2,14180.0] || xuntil6(s29)*+ -> . % 75.92/76.17 14755[44:Spt:14753.0,14176.0,14176.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 75.92/76.17 14756[44:Res:53.1,14755.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 75.92/76.17 14758[45:Spt:14756.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.17 14760[45:Res:14758.0,61.1] always3(s29) || -> . % 75.92/76.17 14761[45:SSi:14760.0,718.0,14175.0] || -> . % 75.92/76.17 14762[45:Spt:14761.0,14756.0,14758.0] || m_main_v_state(s29,c_busy)* -> . % 75.92/76.17 14763[45:Spt:14761.0,14756.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.17 14767[45:Res:14763.0,61.1] always3(s30) || -> . % 75.92/76.17 14768[45:SSi:14767.0,719.0] || -> . % 75.92/76.17 14769[43:Spt:14768.0,14173.2,14174.0] || xuntil6(s28)*+ -> . % 75.92/76.17 14770[43:Spt:14768.0,14173.0,14173.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.17 14771[43:Res:53.1,14770.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.17 14773[44:Spt:14771.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.17 14775[44:Res:14773.0,61.1] always3(s29) || -> . % 75.92/76.17 14776[44:SSi:14775.0,718.0] || -> . % 75.92/76.17 14777[44:Spt:14776.0,14771.1,14773.0] || m_main_v_state(s29,c_busy)* -> . % 75.92/76.17 14778[44:Spt:14776.0,14771.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.17 14781[44:Res:14778.0,61.1] always3(s28) || -> . % 75.92/76.17 14782[44:SSi:14781.0,717.0,14172.0] || -> . % 75.92/76.17 14783[42:Spt:14782.0,14167.2,14171.0] || xuntil6(s27)*+ -> . % 75.92/76.17 14784[42:Spt:14782.0,14167.0,14167.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.17 14785[42:Res:53.1,14784.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.17 14787[43:Spt:14785.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.17 14789[43:Res:14787.0,61.1] always3(s28) || -> . % 75.92/76.17 14790[43:SSi:14789.0,717.0] || -> . % 75.92/76.17 14791[43:Spt:14790.0,14785.1,14787.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.17 14792[43:Spt:14790.0,14785.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.17 14795[43:Res:14792.0,61.1] always3(s27) || -> . % 75.92/76.17 14796[43:SSi:14795.0,716.0,14166.0] || -> . % 75.92/76.17 14797[41:Spt:14796.0,14164.2,14165.0] || xuntil6(s26)*+ -> . % 75.92/76.17 14798[41:Spt:14796.0,14164.0,14164.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.17 14799[41:Res:53.1,14798.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.17 14801[42:Spt:14799.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.17 14803[42:Res:14801.0,61.1] always3(s27) || -> . % 75.92/76.17 14804[42:SSi:14803.0,716.0] || -> . % 75.92/76.17 14805[42:Spt:14804.0,14799.1,14801.0] || m_main_v_state(s27,c_busy)* -> . % 75.92/76.17 14806[42:Spt:14804.0,14799.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.17 14809[42:Res:14806.0,61.1] always3(s26) || -> . % 75.92/76.17 14810[42:SSi:14809.0,715.0,14163.0] || -> . % 75.92/76.17 14811[40:Spt:14810.0,14158.2,14162.0] || xuntil6(s25)*+ -> . % 75.92/76.17 14812[40:Spt:14810.0,14158.0,14158.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.17 14813[40:Res:53.1,14812.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.17 14815[41:Spt:14813.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.17 14817[41:Res:14815.0,61.1] always3(s26) || -> . % 75.92/76.17 14818[41:SSi:14817.0,715.0] || -> . % 75.92/76.17 14819[41:Spt:14818.0,14813.1,14815.0] || m_main_v_state(s26,c_busy)* -> . % 75.92/76.17 14820[41:Spt:14818.0,14813.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.17 14823[41:Res:14820.0,61.1] always3(s25) || -> . % 75.92/76.17 14824[41:SSi:14823.0,714.0,14157.0] || -> . % 75.92/76.17 14825[39:Spt:14824.0,14155.2,14156.0] || xuntil6(s24)*+ -> . % 75.92/76.17 14826[39:Spt:14824.0,14155.0,14155.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.17 14827[39:Res:53.1,14826.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.17 14832[40:Spt:14827.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.17 14834[40:Res:14832.0,61.1] always3(s24) || -> . % 75.92/76.17 14835[40:SSi:14834.0,713.0,14154.0] || -> . % 75.92/76.17 14836[40:Spt:14835.0,14827.0,14832.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.17 14837[40:Spt:14835.0,14827.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.17 14841[40:Res:14837.0,61.1] always3(s25) || -> . % 75.92/76.17 14842[40:SSi:14841.0,714.0] || -> . % 75.92/76.17 14843[38:Spt:14842.0,14149.2,14153.0] || xuntil6(s23)*+ -> . % 75.92/76.17 14844[38:Spt:14842.0,14149.0,14149.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.17 14845[38:Res:53.1,14844.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.17 14847[39:Spt:14845.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.17 14849[39:Res:14847.0,61.1] always3(s24) || -> . % 75.92/76.17 14850[39:SSi:14849.0,713.0] || -> . % 75.92/76.17 14851[39:Spt:14850.0,14845.1,14847.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.17 14852[39:Spt:14850.0,14845.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.17 14855[39:Res:14852.0,61.1] always3(s23) || -> . % 75.92/76.17 14856[39:SSi:14855.0,712.0,14148.0] || -> . % 75.92/76.17 14857[37:Spt:14856.0,14146.2,14147.0] || xuntil6(s22)*+ -> . % 75.92/76.17 14858[37:Spt:14856.0,14146.0,14146.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.17 14859[37:Res:53.1,14858.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.17 14861[38:Spt:14859.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.17 14863[38:Res:14861.0,61.1] always3(s23) || -> . % 75.92/76.17 14864[38:SSi:14863.0,712.0] || -> . % 75.92/76.17 14865[38:Spt:14864.0,14859.1,14861.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.17 14866[38:Spt:14864.0,14859.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.17 14869[38:Res:14866.0,61.1] always3(s22) || -> . % 75.92/76.17 14870[38:SSi:14869.0,711.0,14145.0] || -> . % 75.92/76.17 14871[36:Spt:14870.0,14140.2,14144.0] || xuntil6(s21)*+ -> . % 75.92/76.17 14872[36:Spt:14870.0,14140.0,14140.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.17 14873[36:Res:53.1,14872.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.17 14878[37:Spt:14873.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.17 14880[37:Res:14878.0,61.1] always3(s21) || -> . % 75.92/76.17 14881[37:SSi:14880.0,710.0,14139.0] || -> . % 75.92/76.17 14882[37:Spt:14881.0,14873.0,14878.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.17 14883[37:Spt:14881.0,14873.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.17 14887[37:Res:14883.0,61.1] always3(s22) || -> . % 75.92/76.17 14888[37:SSi:14887.0,711.0] || -> . % 75.92/76.17 14889[35:Spt:14888.0,14137.2,14138.0] || xuntil6(s20)*+ -> . % 75.92/76.17 14890[35:Spt:14888.0,14137.0,14137.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.17 14891[35:Res:53.1,14890.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.17 14893[36:Spt:14891.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.17 14895[36:Res:14893.0,61.1] always3(s21) || -> . % 75.92/76.17 14896[36:SSi:14895.0,710.0] || -> . % 75.92/76.17 14897[36:Spt:14896.0,14891.1,14893.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.17 14898[36:Spt:14896.0,14891.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.17 14901[36:Res:14898.0,61.1] always3(s20) || -> . % 75.92/76.17 14902[36:SSi:14901.0,709.0,14136.0] || -> . % 75.92/76.17 14903[34:Spt:14902.0,14131.2,14135.0] || xuntil6(s19)*+ -> . % 75.92/76.17 14904[34:Spt:14902.0,14131.0,14131.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.17 14905[34:Res:53.1,14904.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.17 14907[35:Spt:14905.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.17 14909[35:Res:14907.0,61.1] always3(s20) || -> . % 75.92/76.17 14910[35:SSi:14909.0,709.0] || -> . % 75.92/76.17 14911[35:Spt:14910.0,14905.1,14907.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.17 14912[35:Spt:14910.0,14905.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.17 14915[35:Res:14912.0,61.1] always3(s19) || -> . % 75.92/76.17 14916[35:SSi:14915.0,708.0,14130.0] || -> . % 75.92/76.17 14917[33:Spt:14916.0,14128.2,14129.0] || xuntil6(s18)*+ -> . % 75.92/76.17 14918[33:Spt:14916.0,14128.0,14128.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.17 14919[33:Res:53.1,14918.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.17 14924[34:Spt:14919.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.17 14926[34:Res:14924.0,61.1] always3(s18) || -> . % 75.92/76.17 14927[34:SSi:14926.0,707.0,14127.0] || -> . % 75.92/76.17 14928[34:Spt:14927.0,14919.0,14924.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.17 14929[34:Spt:14927.0,14919.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.17 14933[34:Res:14929.0,61.1] always3(s19) || -> . % 75.92/76.17 14934[34:SSi:14933.0,708.0] || -> . % 75.92/76.17 14935[32:Spt:14934.0,14122.2,14126.0] || xuntil6(s17)*+ -> . % 75.92/76.17 14936[32:Spt:14934.0,14122.0,14122.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.17 14937[32:Res:53.1,14936.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.17 14939[33:Spt:14937.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.17 14941[33:Res:14939.0,61.1] always3(s18) || -> . % 75.92/76.17 14942[33:SSi:14941.0,707.0] || -> . % 75.92/76.17 14943[33:Spt:14942.0,14937.1,14939.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.17 14944[33:Spt:14942.0,14937.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.17 14947[33:Res:14944.0,61.1] always3(s17) || -> . % 75.92/76.17 14948[33:SSi:14947.0,706.0,14121.0] || -> . % 75.92/76.17 14949[31:Spt:14948.0,14119.2,14120.0] || xuntil6(s16)*+ -> . % 75.92/76.17 14950[31:Spt:14948.0,14119.0,14119.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.17 14951[31:Res:53.1,14950.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.17 14953[32:Spt:14951.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.17 14955[32:Res:14953.0,61.1] always3(s17) || -> . % 75.92/76.17 14956[32:SSi:14955.0,706.0] || -> . % 75.92/76.17 14957[32:Spt:14956.0,14951.1,14953.0] || m_main_v_state(s17,c_busy)* -> . % 75.92/76.17 14958[32:Spt:14956.0,14951.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.17 14961[32:Res:14958.0,61.1] always3(s16) || -> . % 75.92/76.17 14962[32:SSi:14961.0,705.0,14118.0] || -> . % 75.92/76.17 14963[30:Spt:14962.0,14113.2,14117.0] || xuntil6(s15)*+ -> . % 75.92/76.17 14964[30:Spt:14962.0,14113.0,14113.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.17 14965[30:Res:53.1,14964.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.17 14970[31:Spt:14965.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.17 14972[31:Res:14970.0,61.1] always3(s15) || -> . % 75.92/76.17 14973[31:SSi:14972.0,704.0,14112.0] || -> . % 75.92/76.17 14974[31:Spt:14973.0,14965.0,14970.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.17 14975[31:Spt:14973.0,14965.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.17 14979[31:Res:14975.0,61.1] always3(s16) || -> . % 75.92/76.17 14980[31:SSi:14979.0,705.0] || -> . % 75.92/76.17 14981[29:Spt:14980.0,14110.2,14111.0] || xuntil6(s14)*+ -> . % 75.92/76.17 14982[29:Spt:14980.0,14110.0,14110.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.17 14983[29:Res:53.1,14982.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.17 14985[30:Spt:14983.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.17 14987[30:Res:14985.0,61.1] always3(s15) || -> . % 75.92/76.17 14988[30:SSi:14987.0,704.0] || -> . % 75.92/76.17 14989[30:Spt:14988.0,14983.1,14985.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.17 14990[30:Spt:14988.0,14983.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.17 14993[30:Res:14990.0,61.1] always3(s14) || -> . % 75.92/76.17 14994[30:SSi:14993.0,703.0,14109.0] || -> . % 75.92/76.17 14995[28:Spt:14994.0,14104.2,14108.0] || xuntil6(s13)*+ -> . % 75.92/76.17 14996[28:Spt:14994.0,14104.0,14104.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.17 14997[28:Res:53.1,14996.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.17 14999[29:Spt:14997.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.17 15001[29:Res:14999.0,61.1] always3(s14) || -> . % 75.92/76.17 15002[29:SSi:15001.0,703.0] || -> . % 75.92/76.17 15003[29:Spt:15002.0,14997.1,14999.0] || m_main_v_state(s14,c_busy)* -> . % 75.92/76.17 15004[29:Spt:15002.0,14997.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.17 15007[29:Res:15004.0,61.1] always3(s13) || -> . % 75.92/76.17 15008[29:SSi:15007.0,702.0,14103.0] || -> . % 75.92/76.17 15009[27:Spt:15008.0,14101.2,14102.0] || xuntil6(s12)*+ -> . % 75.92/76.17 15010[27:Spt:15008.0,14101.0,14101.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.17 15011[27:Res:53.1,15010.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.17 15016[28:Spt:15011.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.17 15018[28:Res:15016.0,61.1] always3(s12) || -> . % 75.92/76.17 15019[28:SSi:15018.0,701.0,14100.0] || -> . % 75.92/76.17 15020[28:Spt:15019.0,15011.0,15016.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.17 15021[28:Spt:15019.0,15011.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.17 15025[28:Res:15021.0,61.1] always3(s13) || -> . % 75.92/76.17 15026[28:SSi:15025.0,702.0] || -> . % 75.92/76.17 15027[26:Spt:15026.0,14095.2,14099.0] || xuntil6(s11)*+ -> . % 75.92/76.17 15028[26:Spt:15026.0,14095.0,14095.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.17 15029[26:Res:53.1,15028.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.17 15031[27:Spt:15029.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.17 15033[27:Res:15031.0,61.1] always3(s12) || -> . % 75.92/76.17 15034[27:SSi:15033.0,701.0] || -> . % 75.92/76.17 15035[27:Spt:15034.0,15029.1,15031.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.17 15036[27:Spt:15034.0,15029.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.17 15039[27:Res:15036.0,61.1] always3(s11) || -> . % 75.92/76.17 15040[27:SSi:15039.0,700.0,14094.0] || -> . % 75.92/76.17 15041[25:Spt:15040.0,14092.2,14093.0] || xuntil6(s10)*+ -> . % 75.92/76.17 15042[25:Spt:15040.0,14092.0,14092.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.17 15043[25:Res:53.1,15042.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.17 15045[26:Spt:15043.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.17 15047[26:Res:15045.0,61.1] always3(s11) || -> . % 75.92/76.17 15048[26:SSi:15047.0,700.0] || -> . % 75.92/76.17 15049[26:Spt:15048.0,15043.1,15045.0] || m_main_v_state(s11,c_busy)* -> . % 75.92/76.17 15050[26:Spt:15048.0,15043.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.17 15053[26:Res:15050.0,61.1] always3(s10) || -> . % 75.92/76.17 15054[26:SSi:15053.0,699.0,14091.0] || -> . % 75.92/76.17 15055[24:Spt:15054.0,14086.2,14090.0] || xuntil6(s9)*+ -> . % 75.92/76.17 15056[24:Spt:15054.0,14086.0,14086.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.17 15057[24:Res:53.1,15056.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.17 15062[25:Spt:15057.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.17 15064[25:Res:15062.0,61.1] always3(s9) || -> . % 75.92/76.17 15065[25:SSi:15064.0,698.0,14085.0] || -> . % 75.92/76.17 15066[25:Spt:15065.0,15057.0,15062.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.17 15067[25:Spt:15065.0,15057.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.17 15071[25:Res:15067.0,61.1] always3(s10) || -> . % 75.92/76.17 15072[25:SSi:15071.0,699.0] || -> . % 75.92/76.17 15073[23:Spt:15072.0,14083.2,14084.0] || xuntil6(s8)*+ -> . % 75.92/76.17 15074[23:Spt:15072.0,14083.0,14083.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.17 15075[23:Res:53.1,15074.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.17 15077[24:Spt:15075.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.17 15079[24:Res:15077.0,61.1] always3(s9) || -> . % 75.92/76.17 15080[24:SSi:15079.0,698.0] || -> . % 75.92/76.17 15081[24:Spt:15080.0,15075.1,15077.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.17 15082[24:Spt:15080.0,15075.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.17 15085[24:Res:15082.0,61.1] always3(s8) || -> . % 75.92/76.17 15086[24:SSi:15085.0,697.0,14082.0] || -> . % 75.92/76.17 15087[22:Spt:15086.0,14077.2,14081.0] || xuntil6(s7)*+ -> . % 75.92/76.17 15088[22:Spt:15086.0,14077.0,14077.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.17 15089[22:Res:53.1,15088.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.17 15091[23:Spt:15089.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.17 15093[23:Res:15091.0,61.1] always3(s8) || -> . % 75.92/76.17 15094[23:SSi:15093.0,697.0] || -> . % 75.92/76.17 15095[23:Spt:15094.0,15089.1,15091.0] || m_main_v_state(s8,c_busy)* -> . % 75.92/76.17 15096[23:Spt:15094.0,15089.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.17 15099[23:Res:15096.0,61.1] always3(s7) || -> . % 75.92/76.17 15100[23:SSi:15099.0,696.0,14076.0] || -> . % 75.92/76.17 15101[21:Spt:15100.0,14074.2,14075.0] || xuntil6(s6)*+ -> . % 75.92/76.17 15102[21:Spt:15100.0,14074.0,14074.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.17 15103[21:Res:53.1,15102.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.17 15108[22:Spt:15103.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.17 15110[22:Res:15108.0,61.1] always3(s6) || -> . % 75.92/76.17 15111[22:SSi:15110.0,695.0,14073.0] || -> . % 75.92/76.17 15112[22:Spt:15111.0,15103.0,15108.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.17 15113[22:Spt:15111.0,15103.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.17 15117[22:Res:15113.0,61.1] always3(s7) || -> . % 75.92/76.17 15118[22:SSi:15117.0,696.0] || -> . % 75.92/76.17 15119[20:Spt:15118.0,14068.2,14072.0] || xuntil6(s5)*+ -> . % 75.92/76.17 15120[20:Spt:15118.0,14068.0,14068.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.17 15121[20:Res:53.1,15120.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.17 15123[21:Spt:15121.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.17 15125[21:Res:15123.0,61.1] always3(s6) || -> . % 75.92/76.17 15126[21:SSi:15125.0,695.0] || -> . % 75.92/76.17 15127[21:Spt:15126.0,15121.1,15123.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.17 15128[21:Spt:15126.0,15121.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.17 15131[21:Res:15128.0,61.1] always3(s5) || -> . % 75.92/76.17 15132[21:SSi:15131.0,694.0,14067.0] || -> . % 75.92/76.17 15133[19:Spt:15132.0,14065.2,14066.0] || xuntil6(s4)*+ -> . % 75.92/76.17 15134[19:Spt:15132.0,14065.0,14065.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.17 15135[19:Res:53.1,15134.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.17 15137[20:Spt:15135.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.17 15139[20:Res:15137.0,61.1] always3(s5) || -> . % 75.92/76.17 15140[20:SSi:15139.0,694.0] || -> . % 75.92/76.17 15141[20:Spt:15140.0,15135.1,15137.0] || m_main_v_state(s5,c_busy)* -> . % 75.92/76.17 15142[20:Spt:15140.0,15135.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.17 15145[20:Res:15142.0,61.1] always3(s4) || -> . % 75.92/76.17 15146[20:SSi:15145.0,693.0,14064.0] || -> . % 75.92/76.17 15147[18:Spt:15146.0,14062.2,14063.0] || xuntil6(s3)*+ -> . % 75.92/76.17 15148[18:Spt:15146.0,14062.0,14062.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.17 15149[18:Res:53.1,15148.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.17 15154[19:Spt:15149.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.17 15156[19:Res:15154.0,61.1] always3(s3) || -> . % 75.92/76.17 15157[19:SSi:15156.0,692.0,14061.0] || -> . % 75.92/76.17 15158[19:Spt:15157.0,15149.0,15154.0] || m_main_v_state(s3,c_busy)* -> . % 75.92/76.17 15159[19:Spt:15157.0,15149.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.17 15163[19:Res:15159.0,61.1] always3(s4) || -> . % 75.92/76.17 15164[19:SSi:15163.0,693.0] || -> . % 75.92/76.17 15165[17:Spt:15164.0,14059.2,14060.0] || xuntil6(s2)*+ -> . % 75.92/76.17 15166[17:Spt:15164.0,14059.0,14059.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.17 15167[17:Res:53.1,15166.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.17 15169[18:Spt:15167.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.17 15171[18:Res:15169.0,61.1] always3(s3) || -> . % 75.92/76.17 15172[18:SSi:15171.0,692.0] || -> . % 75.92/76.17 15173[18:Spt:15172.0,15167.1,15169.0] || m_main_v_state(s3,c_busy)* -> . % 75.92/76.17 15174[18:Spt:15172.0,15167.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.17 15177[18:Res:15174.0,61.1] always3(s2) || -> . % 75.92/76.17 15178[18:SSi:15177.0,691.0,14058.0] || -> . % 75.92/76.17 15179[16:Spt:15178.0,14053.2,14057.0] || xuntil6(s1)*+ -> . % 75.92/76.17 15180[16:Spt:15178.0,14053.0,14053.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.17 15181[16:Res:53.1,15180.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.17 15183[17:Spt:15181.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.17 15185[17:Res:15183.0,61.1] always3(s1) || -> . % 75.92/76.17 15186[17:SSi:15185.0,690.0,14052.0] || -> . % 75.92/76.17 15187[17:Spt:15186.0,15181.0,15183.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.17 15188[17:Spt:15186.0,15181.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.17 15193[17:Res:15188.0,61.1] always3(s2) || -> . % 75.92/76.17 15194[17:SSi:15193.0,691.0] || -> . % 75.92/76.17 15195[15:Spt:15194.0,74.0,14051.0] || xuntil6(s0)*+ -> . % 75.92/76.17 15196[15:Spt:15194.0,74.1] || -> node4(s0)*. % 75.92/76.17 15197[15:MRR:758.1,15195.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.17 15199[15:Res:15197.0,61.1] always3(s1) || -> . % 75.92/76.17 15200[15:SSi:15199.0,690.0] || -> . % 75.92/76.17 15201[14:Spt:15200.0,14041.0,14045.0] || trans(s49,s37)*+ -> . % 75.92/76.17 15202[14:Spt:15200.0,14041.1,14041.2,14041.3,14041.4,14041.5,14041.6,14041.7,14041.8,14041.9,14041.10,14041.11,14041.12,14041.13,14041.14,14041.15,14041.16,14041.17,14041.18,14041.19,14041.20,14041.21,14041.22,14041.23,14041.24,14041.25,14041.26,14041.27,14041.28,14041.29,14041.30,14041.31,14041.32,14041.33,14041.34,14041.35,14041.36,14041.37] || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.17 15203[14:MRR:14043.0,15201.0] || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.17 15205[14:MRR:14044.1,15201.0] xuntil6(s49) || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.17 15206[15:Spt:15202.0] || -> trans(s49,s36)*. % 75.92/76.17 15207[15:Res:15206.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s36)*. % 75.92/76.17 15209[15:Res:15206.0,60.0] || -> node2(s49,s36)*. % 75.92/76.17 15210[15:SSi:15207.1,50.0,738.0] xuntil6(s49) || -> until2p7(s36)*. % 75.92/76.17 15211[15:Res:15209.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)*. % 75.92/76.17 15212[16:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.17 15213[16:MRR:176.0,15212.0] || -> until5(s1)*. % 75.92/76.17 15214[16:MRR:12022.0,15213.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.17 15218[17:Spt:15214.2] || -> xuntil6(s1)*. % 75.92/76.17 15219[17:MRR:175.0,15218.0] || -> until5(s2)*. % 75.92/76.17 15220[17:MRR:12018.0,15219.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.17 15224[18:Spt:15220.2] || -> xuntil6(s2)*. % 75.92/76.17 15225[18:MRR:174.0,15224.0] || -> until5(s3)*. % 75.92/76.17 15226[18:MRR:12014.0,15225.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.17 15227[19:Spt:15226.2] || -> xuntil6(s3)*. % 75.92/76.17 15228[19:MRR:173.0,15227.0] || -> until5(s4)*. % 75.92/76.17 15229[19:MRR:12010.0,15228.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.17 15233[20:Spt:15229.2] || -> xuntil6(s4)*. % 75.92/76.17 15234[20:MRR:172.0,15233.0] || -> until5(s5)*. % 75.92/76.17 15235[20:MRR:12009.0,15234.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.17 15236[21:Spt:15235.2] || -> xuntil6(s5)*. % 75.92/76.17 15237[21:MRR:171.0,15236.0] || -> until5(s6)*. % 75.92/76.17 15238[21:MRR:12002.0,15237.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.17 15242[22:Spt:15238.2] || -> xuntil6(s6)*. % 75.92/76.17 15243[22:MRR:170.0,15242.0] || -> until5(s7)*. % 75.92/76.17 15244[22:MRR:11998.0,15243.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.17 15245[23:Spt:15244.2] || -> xuntil6(s7)*. % 75.92/76.17 15246[23:MRR:169.0,15245.0] || -> until5(s8)*. % 75.92/76.17 15247[23:MRR:11994.0,15246.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.17 15251[24:Spt:15247.2] || -> xuntil6(s8)*. % 75.92/76.17 15252[24:MRR:168.0,15251.0] || -> until5(s9)*. % 75.92/76.17 15253[24:MRR:11990.0,15252.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.17 15254[25:Spt:15253.2] || -> xuntil6(s9)*. % 75.92/76.17 15255[25:MRR:167.0,15254.0] || -> until5(s10)*. % 75.92/76.17 15256[25:MRR:11989.0,15255.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.17 15260[26:Spt:15256.2] || -> xuntil6(s10)*. % 75.92/76.17 15261[26:MRR:166.0,15260.0] || -> until5(s11)*. % 75.92/76.17 15262[26:MRR:11982.0,15261.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.17 15263[27:Spt:15262.2] || -> xuntil6(s11)*. % 75.92/76.17 15264[27:MRR:165.0,15263.0] || -> until5(s12)*. % 75.92/76.17 15265[27:MRR:11978.0,15264.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.17 15269[28:Spt:15265.2] || -> xuntil6(s12)*. % 75.92/76.17 15270[28:MRR:164.0,15269.0] || -> until5(s13)*. % 75.92/76.17 15271[28:MRR:11974.0,15270.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.17 15272[29:Spt:15271.2] || -> xuntil6(s13)*. % 75.92/76.17 15273[29:MRR:163.0,15272.0] || -> until5(s14)*. % 75.92/76.17 15274[29:MRR:11970.0,15273.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.17 15278[30:Spt:15274.2] || -> xuntil6(s14)*. % 75.92/76.17 15279[30:MRR:162.0,15278.0] || -> until5(s15)*. % 75.92/76.17 15280[30:MRR:11969.0,15279.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.17 15281[31:Spt:15280.2] || -> xuntil6(s15)*. % 75.92/76.17 15282[31:MRR:161.0,15281.0] || -> until5(s16)*. % 75.92/76.17 15283[31:MRR:11962.0,15282.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.17 15287[32:Spt:15283.2] || -> xuntil6(s16)*. % 75.92/76.17 15288[32:MRR:160.0,15287.0] || -> until5(s17)*. % 75.92/76.17 15289[32:MRR:11958.0,15288.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.17 15290[33:Spt:15289.2] || -> xuntil6(s17)*. % 75.92/76.17 15291[33:MRR:159.0,15290.0] || -> until5(s18)*. % 75.92/76.17 15292[33:MRR:11954.0,15291.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.17 15296[34:Spt:15292.2] || -> xuntil6(s18)*. % 75.92/76.17 15297[34:MRR:158.0,15296.0] || -> until5(s19)*. % 75.92/76.17 15298[34:MRR:11950.0,15297.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.17 15299[35:Spt:15298.2] || -> xuntil6(s19)*. % 75.92/76.17 15300[35:MRR:157.0,15299.0] || -> until5(s20)*. % 75.92/76.17 15301[35:MRR:11949.0,15300.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.17 15305[36:Spt:15301.2] || -> xuntil6(s20)*. % 75.92/76.17 15306[36:MRR:156.0,15305.0] || -> until5(s21)*. % 75.92/76.17 15307[36:MRR:11942.0,15306.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.17 15308[37:Spt:15307.2] || -> xuntil6(s21)*. % 75.92/76.17 15309[37:MRR:155.0,15308.0] || -> until5(s22)*. % 75.92/76.17 15310[37:MRR:11938.0,15309.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.17 15314[38:Spt:15310.2] || -> xuntil6(s22)*. % 75.92/76.17 15315[38:MRR:154.0,15314.0] || -> until5(s23)*. % 75.92/76.17 15316[38:MRR:11934.0,15315.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.17 15317[39:Spt:15316.2] || -> xuntil6(s23)*. % 75.92/76.17 15318[39:MRR:153.0,15317.0] || -> until5(s24)*. % 75.92/76.17 15319[39:MRR:11930.0,15318.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.17 15323[40:Spt:15319.2] || -> xuntil6(s24)*. % 75.92/76.17 15324[40:MRR:152.0,15323.0] || -> until5(s25)*. % 75.92/76.17 15325[40:MRR:11929.0,15324.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.17 15326[41:Spt:15325.2] || -> xuntil6(s25)*. % 75.92/76.17 15327[41:MRR:151.0,15326.0] || -> until5(s26)*. % 75.92/76.17 15328[41:MRR:11922.0,15327.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.17 15332[42:Spt:15328.2] || -> xuntil6(s26)*. % 75.92/76.17 15333[42:MRR:150.0,15332.0] || -> until5(s27)*. % 75.92/76.17 15334[42:MRR:11918.0,15333.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.17 15335[43:Spt:15334.2] || -> xuntil6(s27)*. % 75.92/76.17 15336[43:MRR:149.0,15335.0] || -> until5(s28)*. % 75.92/76.17 15337[43:MRR:11914.0,15336.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.17 15341[44:Spt:15337.2] || -> xuntil6(s28)*. % 75.92/76.17 15342[44:MRR:148.0,15341.0] || -> until5(s29)*. % 75.92/76.17 15343[44:MRR:11910.0,15342.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.17 15344[45:Spt:15343.2] || -> xuntil6(s29)*. % 75.92/76.17 15345[45:MRR:147.0,15344.0] || -> until5(s30)*. % 75.92/76.17 15346[45:MRR:11909.0,15345.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.17 15350[46:Spt:15346.2] || -> xuntil6(s30)*. % 75.92/76.17 15351[46:MRR:146.0,15350.0] || -> until5(s31)*. % 75.92/76.17 15352[46:MRR:11905.0,15351.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.17 15353[47:Spt:15352.2] || -> xuntil6(s31)*. % 75.92/76.17 15354[47:MRR:145.0,15353.0] || -> until5(s32)*. % 75.92/76.17 15355[47:MRR:11904.0,15354.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.17 15359[48:Spt:15355.2] || -> xuntil6(s32)*. % 75.92/76.17 15360[48:MRR:144.0,15359.0] || -> until5(s33)*. % 75.92/76.17 15361[48:MRR:932.0,15360.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.17 15362[49:Spt:15361.1] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.17 15364[49:Res:15362.0,61.1] always3(s34) || -> . % 75.92/76.17 15365[49:SSi:15364.0,723.0] || -> . % 75.92/76.17 15366[49:Spt:15365.0,15361.1,15362.0] || m_main_v_state(s34,c_busy)*+ -> . % 75.92/76.17 15367[49:Spt:15365.0,15361.0,15361.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 75.92/76.17 15370[49:Res:53.1,15367.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 75.92/76.17 15375[50:Spt:15370.1] || -> xuntil6(s33)*. % 75.92/76.17 15376[50:MRR:143.0,15375.0] || -> until5(s34)*. % 75.92/76.17 15377[50:MRR:12029.0,15376.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.17 15379[51:Spt:15377.2] || -> xuntil6(s34)*. % 75.92/76.17 15380[51:MRR:142.0,15379.0] || -> until5(s35)*. % 75.92/76.17 15381[51:MRR:930.0,15380.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.17 15382[52:Spt:15381.1] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.17 15384[52:Res:15382.0,61.1] always3(s36) || -> . % 75.92/76.17 15385[52:SSi:15384.0,725.0] || -> . % 75.92/76.17 15386[52:Spt:15385.0,15381.1,15382.0] || m_main_v_state(s36,c_busy)*+ -> . % 75.92/76.17 15387[52:Spt:15385.0,15381.0,15381.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 75.92/76.17 15390[52:MRR:15211.2,15386.0] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.17 15391[52:Res:53.1,15387.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 75.92/76.17 15393[53:Spt:15391.1] || -> xuntil6(s35)*. % 75.92/76.17 15394[53:MRR:141.0,15393.0] || -> until5(s36)*. % 75.92/76.17 15395[53:MRR:12033.0,15394.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.17 15401[52:SoR:15390.0,64.1] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.17 15403[52:SoR:15401.0,66.2] until5(s49) || m_main_v_state(s49,c_ready)* -> xuntil6(s49). % 75.92/76.17 15404[54:Spt:15395.2] || -> xuntil6(s36)*. % 75.92/76.17 15405[54:MRR:140.0,15404.0] || -> until5(s37)*. % 75.92/76.17 15406[54:MRR:928.0,15405.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.17 15407[55:Spt:15406.1] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.17 15409[55:Res:15407.0,61.1] always3(s38) || -> . % 75.92/76.17 15410[55:SSi:15409.0,727.0] || -> . % 75.92/76.17 15411[55:Spt:15410.0,15406.1,15407.0] || m_main_v_state(s38,c_busy)*+ -> . % 75.92/76.17 15412[55:Spt:15410.0,15406.0,15406.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 75.92/76.17 15414[55:MRR:807.2,15411.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 75.92/76.17 15415[55:Res:53.1,15412.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 75.92/76.17 15417[56:Spt:15415.1] || -> xuntil6(s37)*. % 75.92/76.17 15418[56:MRR:139.0,15417.0] || -> until5(s38)*. % 75.92/76.17 15419[56:MRR:12040.0,15418.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.17 15424[57:Spt:15419.2] || -> xuntil6(s38)*. % 75.92/76.17 15425[57:MRR:138.0,15424.0] || -> until5(s39)*. % 75.92/76.17 15426[57:MRR:926.0,15425.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.17 15430[58:Spt:15426.1] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.17 15432[58:Res:15430.0,61.1] always3(s40) || -> . % 75.92/76.17 15433[58:SSi:15432.0,729.0] || -> . % 75.92/76.17 15434[58:Spt:15433.0,15426.1,15430.0] || m_main_v_state(s40,c_busy)*+ -> . % 75.92/76.17 15435[58:Spt:15433.0,15426.0,15426.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 75.92/76.17 15437[58:MRR:801.2,15434.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 75.92/76.17 15438[58:Res:53.1,15435.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 75.92/76.17 15440[59:Spt:15438.1] || -> xuntil6(s39)*. % 75.92/76.17 15441[59:MRR:137.0,15440.0] || -> until5(s40)*. % 75.92/76.17 15442[59:MRR:12041.0,15441.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.17 15447[60:Spt:15442.2] || -> xuntil6(s40)*. % 75.92/76.17 15448[60:MRR:136.0,15447.0] || -> until5(s41)*. % 75.92/76.17 15449[60:MRR:924.0,15448.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.17 15450[61:Spt:15449.1] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.17 15452[61:Res:15450.0,61.1] always3(s42) || -> . % 75.92/76.17 15453[61:SSi:15452.0,731.0] || -> . % 75.92/76.17 15454[61:Spt:15453.0,15449.1,15450.0] || m_main_v_state(s42,c_busy)*+ -> . % 75.92/76.17 15455[61:Spt:15453.0,15449.0,15449.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 75.92/76.17 15457[61:MRR:795.2,15454.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 75.92/76.17 15458[61:Res:53.1,15455.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 75.92/76.17 15460[62:Spt:15458.1] || -> xuntil6(s41)*. % 75.92/76.17 15461[62:MRR:135.0,15460.0] || -> until5(s42)*. % 75.92/76.17 15462[62:MRR:12045.0,15461.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.17 15470[63:Spt:15462.2] || -> xuntil6(s42)*. % 75.92/76.17 15471[63:MRR:134.0,15470.0] || -> until5(s43)*. % 75.92/76.17 15472[63:MRR:922.0,15471.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.17 15473[64:Spt:15472.1] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.17 15475[64:Res:15473.0,61.1] always3(s44) || -> . % 75.92/76.17 15476[64:SSi:15475.0,733.0] || -> . % 75.92/76.17 15477[64:Spt:15476.0,15472.1,15473.0] || m_main_v_state(s44,c_busy)*+ -> . % 75.92/76.17 15478[64:Spt:15476.0,15472.0,15472.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 75.92/76.17 15480[64:MRR:789.2,15477.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 75.92/76.17 15481[64:Res:53.1,15478.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 75.92/76.17 15486[65:Spt:15481.1] || -> xuntil6(s43)*. % 75.92/76.17 15487[65:MRR:133.0,15486.0] || -> until5(s44)*. % 75.92/76.17 15488[65:MRR:12049.0,15487.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.17 15490[66:Spt:15488.2] || -> xuntil6(s44)*. % 75.92/76.17 15491[66:MRR:132.0,15490.0] || -> until5(s45)*. % 75.92/76.17 15492[66:MRR:920.0,15491.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.17 15493[67:Spt:15492.1] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.17 15495[67:Res:15493.0,61.1] always3(s46) || -> . % 75.92/76.17 15496[67:SSi:15495.0,735.0] || -> . % 75.92/76.17 15497[67:Spt:15496.0,15492.1,15493.0] || m_main_v_state(s46,c_busy)*+ -> . % 75.92/76.17 15498[67:Spt:15496.0,15492.0,15492.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 75.92/76.17 15500[67:MRR:783.2,15497.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 75.92/76.17 15501[67:Res:53.1,15498.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 75.92/76.17 15503[68:Spt:15501.1] || -> xuntil6(s45)*. % 75.92/76.17 15504[68:MRR:131.0,15503.0] || -> until5(s46)*. % 75.92/76.17 15505[68:MRR:12053.0,15504.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.17 15510[69:Spt:15505.2] || -> xuntil6(s46)*. % 75.92/76.17 15511[69:MRR:130.0,15510.0] || -> until5(s47)*. % 75.92/76.17 15512[69:MRR:918.0,15511.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.17 15513[70:Spt:15512.1] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.17 15515[70:Res:15513.0,61.1] always3(s48) || -> . % 75.92/76.17 15516[70:SSi:15515.0,737.0] || -> . % 75.92/76.17 15517[70:Spt:15516.0,15512.1,15513.0] || m_main_v_state(s48,c_busy)*+ -> . % 75.92/76.17 15518[70:Spt:15516.0,15512.0,15512.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 75.92/76.17 15520[70:MRR:777.2,15517.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 75.92/76.17 15521[70:Res:53.1,15518.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 75.92/76.17 15523[71:Spt:15521.1] || -> xuntil6(s47)*. % 75.92/76.17 15524[71:MRR:129.0,15523.0] || -> until5(s48)*. % 75.92/76.17 15525[71:MRR:12057.0,15524.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.17 15533[72:Spt:15525.2] || -> xuntil6(s48)*. % 75.92/76.17 15534[72:MRR:128.0,15533.0] || -> until5(s49)*. % 75.92/76.17 15535[72:MRR:15403.0,15534.0] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.17 15536[72:Res:53.1,15535.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.17 15538[73:Spt:15536.1] || -> xuntil6(s49)*. % 75.92/76.17 15539[73:MRR:15210.0,15538.0] || -> until2p7(s36)*. % 75.92/76.17 15540[73:MRR:232.0,15539.0] || -> until2p7(s37)* node4(s36). % 75.92/76.17 15541[74:Spt:15540.0] || -> until2p7(s37)*. % 75.92/76.17 15542[74:MRR:235.0,15541.0] || -> until2p7(s38)* node4(s37). % 75.92/76.17 15543[75:Spt:15542.0] || -> until2p7(s38)*. % 75.92/76.17 15544[75:MRR:236.0,15543.0] || -> until2p7(s39)* node4(s38). % 75.92/76.17 15545[76:Spt:15544.0] || -> until2p7(s39)*. % 75.92/76.17 15546[76:MRR:237.0,15545.0] || -> until2p7(s40)* node4(s39). % 75.92/76.17 15547[77:Spt:15546.0] || -> until2p7(s40)*. % 75.92/76.17 15548[77:MRR:238.0,15547.0] || -> until2p7(s41)* node4(s40). % 75.92/76.17 15549[78:Spt:15548.0] || -> until2p7(s41)*. % 75.92/76.17 15550[78:MRR:239.0,15549.0] || -> until2p7(s42)* node4(s41). % 75.92/76.17 15551[79:Spt:15550.0] || -> until2p7(s42)*. % 75.92/76.17 15552[79:MRR:240.0,15551.0] || -> until2p7(s43)* node4(s42). % 75.92/76.17 15553[80:Spt:15552.0] || -> until2p7(s43)*. % 75.92/76.17 15554[80:MRR:241.0,15553.0] || -> until2p7(s44)* node4(s43). % 75.92/76.17 15555[81:Spt:15554.0] || -> until2p7(s44)*. % 75.92/76.17 15556[81:MRR:539.0,15555.0] || -> until2p7(s45)* node4(s44). % 75.92/76.17 15557[82:Spt:15556.0] || -> until2p7(s45)*. % 75.92/76.17 15558[82:MRR:544.0,15557.0] || -> until2p7(s46)* node4(s45). % 75.92/76.17 15559[83:Spt:15558.0] || -> until2p7(s46)*. % 75.92/76.17 15560[83:MRR:549.0,15559.0] || -> until2p7(s47)* node4(s46). % 75.92/76.17 15561[84:Spt:15560.0] || -> until2p7(s47)*. % 75.92/76.17 15562[84:MRR:554.0,15561.0] || -> until2p7(s48)* node4(s47). % 75.92/76.17 15563[85:Spt:15562.0] || -> until2p7(s48)*. % 75.92/76.17 15564[85:MRR:559.0,15563.0] || -> until2p7(s49)* node4(s48). % 75.92/76.17 15565[86:Spt:15564.0] || -> until2p7(s49)*. % 75.92/76.17 15566[86:MRR:194.0,15565.0] || -> node4(s49)*. % 75.92/76.17 15567[86:MRR:15401.0,15566.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.17 15571[86:Res:53.1,15567.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.17 15574[86:Res:15571.0,61.1] always3(s49) || -> . % 75.92/76.17 15575[86:SSi:15574.0,50.0,738.0,15534.0,15538.0,15565.0,15566.0] || -> . % 75.92/76.17 15576[86:Spt:15575.0,15564.0,15565.0] || until2p7(s49)*+ -> . % 75.92/76.17 15577[86:Spt:15575.0,15564.1] || -> node4(s48)*. % 75.92/76.17 15579[86:MRR:774.0,15577.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.17 15585[86:Res:53.1,15579.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.17 15587[86:MRR:15585.0,15517.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.17 15589[86:Res:15587.0,61.1] always3(s49) || -> . % 75.92/76.17 15590[86:SSi:15589.0,50.0,738.0,15534.0,15538.0] || -> . % 75.92/76.17 15591[85:Spt:15590.0,15562.0,15563.0] || until2p7(s48)*+ -> . % 75.92/76.17 15592[85:Spt:15590.0,15562.1] || -> node4(s47)*. % 75.92/76.17 15593[85:MRR:15520.0,15592.0] || m_main_v_state(s47,c_ready)*+ -> . % 75.92/76.17 15596[85:Res:53.1,15593.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.17 15599[85:Res:15596.0,61.1] always3(s47) || -> . % 75.92/76.17 15600[85:SSi:15599.0,736.0,15511.0,15523.0,15561.0,15592.0] || -> . % 75.92/76.17 15601[84:Spt:15600.0,15560.0,15561.0] || until2p7(s47)*+ -> . % 75.92/76.17 15602[84:Spt:15600.0,15560.1] || -> node4(s46)*. % 75.92/76.17 15604[84:MRR:780.0,15602.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.17 15616[84:Res:53.1,15604.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.17 15618[84:MRR:15616.0,15497.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.17 15623[84:Res:15618.0,61.1] always3(s47) || -> . % 75.92/76.17 15624[84:SSi:15623.0,736.0,15511.0,15523.0] || -> . % 75.92/76.17 15625[83:Spt:15624.0,15558.0,15559.0] || until2p7(s46)*+ -> . % 75.92/76.17 15626[83:Spt:15624.0,15558.1] || -> node4(s45)*. % 75.92/76.17 15627[83:MRR:15500.0,15626.0] || m_main_v_state(s45,c_ready)*+ -> . % 75.92/76.17 15630[83:Res:53.1,15627.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.17 15634[83:Res:15630.0,61.1] always3(s45) || -> . % 75.92/76.17 15635[83:SSi:15634.0,734.0,15491.0,15503.0,15557.0,15626.0] || -> . % 75.92/76.17 15636[82:Spt:15635.0,15556.0,15557.0] || until2p7(s45)*+ -> . % 75.92/76.17 15637[82:Spt:15635.0,15556.1] || -> node4(s44)*. % 75.92/76.17 15639[82:MRR:786.0,15637.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.17 15650[82:Res:53.1,15639.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.17 15652[82:MRR:15650.0,15477.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.17 15654[82:Res:15652.0,61.1] always3(s45) || -> . % 75.92/76.17 15655[82:SSi:15654.0,734.0,15491.0,15503.0] || -> . % 75.92/76.17 15656[81:Spt:15655.0,15554.0,15555.0] || until2p7(s44)*+ -> . % 75.92/76.17 15657[81:Spt:15655.0,15554.1] || -> node4(s43)*. % 75.92/76.17 15658[81:MRR:15480.0,15657.0] || m_main_v_state(s43,c_ready)*+ -> . % 75.92/76.17 15662[81:Res:53.1,15658.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.17 15665[81:Res:15662.0,61.1] always3(s43) || -> . % 75.92/76.17 15666[81:SSi:15665.0,732.0,15471.0,15486.0,15553.0,15657.0] || -> . % 75.92/76.17 15667[80:Spt:15666.0,15552.0,15553.0] || until2p7(s43)*+ -> . % 75.92/76.17 15668[80:Spt:15666.0,15552.1] || -> node4(s42)*. % 75.92/76.17 15670[80:MRR:792.0,15668.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.17 15681[80:Res:53.1,15670.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.17 15683[80:MRR:15681.0,15454.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.17 15685[80:Res:15683.0,61.1] always3(s43) || -> . % 75.92/76.17 15686[80:SSi:15685.0,732.0,15471.0,15486.0] || -> . % 75.92/76.17 15687[79:Spt:15686.0,15550.0,15551.0] || until2p7(s42)*+ -> . % 75.92/76.17 15688[79:Spt:15686.0,15550.1] || -> node4(s41)*. % 75.92/76.17 15689[79:MRR:15457.0,15688.0] || m_main_v_state(s41,c_ready)*+ -> . % 75.92/76.17 15692[79:Res:53.1,15689.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.17 15695[79:Res:15692.0,61.1] always3(s41) || -> . % 75.92/76.17 15696[79:SSi:15695.0,730.0,15448.0,15460.0,15549.0,15688.0] || -> . % 75.92/76.17 15697[78:Spt:15696.0,15548.0,15549.0] || until2p7(s41)*+ -> . % 75.92/76.17 15698[78:Spt:15696.0,15548.1] || -> node4(s40)*. % 75.92/76.17 15700[78:MRR:798.0,15698.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.17 15712[78:Res:53.1,15700.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.17 15714[78:MRR:15712.0,15434.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.17 15716[78:Res:15714.0,61.1] always3(s41) || -> . % 75.92/76.17 15717[78:SSi:15716.0,730.0,15448.0,15460.0] || -> . % 75.92/76.17 15718[77:Spt:15717.0,15546.0,15547.0] || until2p7(s40)*+ -> . % 75.92/76.17 15719[77:Spt:15717.0,15546.1] || -> node4(s39)*. % 75.92/76.17 15720[77:MRR:15437.0,15719.0] || m_main_v_state(s39,c_ready)*+ -> . % 75.92/76.17 15723[77:Res:53.1,15720.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.17 15726[77:Res:15723.0,61.1] always3(s39) || -> . % 75.92/76.17 15727[77:SSi:15726.0,728.0,15425.0,15440.0,15545.0,15719.0] || -> . % 75.92/76.17 15728[76:Spt:15727.0,15544.0,15545.0] || until2p7(s39)*+ -> . % 75.92/76.17 15729[76:Spt:15727.0,15544.1] || -> node4(s38)*. % 75.92/76.17 15731[76:MRR:804.0,15729.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.17 15743[76:Res:53.1,15731.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.17 15745[76:MRR:15743.0,15411.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.17 15750[76:Res:15745.0,61.1] always3(s39) || -> . % 75.92/76.17 15751[76:SSi:15750.0,728.0,15425.0,15440.0] || -> . % 75.92/76.17 15752[75:Spt:15751.0,15542.0,15543.0] || until2p7(s38)*+ -> . % 75.92/76.17 15753[75:Spt:15751.0,15542.1] || -> node4(s37)*. % 75.92/76.17 15754[75:MRR:15414.0,15753.0] || m_main_v_state(s37,c_ready)*+ -> . % 75.92/76.17 15757[75:Res:53.1,15754.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.17 15761[75:Res:15757.0,61.1] always3(s37) || -> . % 75.92/76.17 15762[75:SSi:15761.0,726.0,15405.0,15417.0,15541.0,15753.0] || -> . % 75.92/76.17 15763[74:Spt:15762.0,15540.0,15541.0] || until2p7(s37)*+ -> . % 75.92/76.17 15764[74:Spt:15762.0,15540.1] || -> node4(s36)*. % 75.92/76.17 15766[74:MRR:810.0,15764.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.17 15777[74:Res:53.1,15766.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.17 15779[74:MRR:15777.0,15386.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.17 15781[74:Res:15779.0,61.1] always3(s37) || -> . % 75.92/76.17 15782[74:SSi:15781.0,726.0,15405.0,15417.0] || -> . % 75.92/76.17 15783[73:Spt:15782.0,15536.1,15538.0] || xuntil6(s49)* -> . % 75.92/76.17 15784[73:Spt:15782.0,15536.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.17 15787[73:Res:15784.0,61.1] always3(s49) || -> . % 75.92/76.17 15788[73:SSi:15787.0,50.0,738.0,15534.0] || -> . % 75.92/76.17 15789[72:Spt:15788.0,15525.2,15533.0] || xuntil6(s48)*+ -> . % 75.92/76.17 15790[72:Spt:15788.0,15525.0,15525.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.17 15791[72:Res:53.1,15790.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.17 15793[72:MRR:15791.0,15517.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.17 15795[72:Res:15793.0,61.1] always3(s49) || -> . % 75.92/76.17 15796[72:SSi:15795.0,50.0,738.0] || -> . % 75.92/76.17 15797[71:Spt:15796.0,15521.1,15523.0] || xuntil6(s47)* -> . % 75.92/76.17 15798[71:Spt:15796.0,15521.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.17 15801[71:Res:15798.0,61.1] always3(s47) || -> . % 75.92/76.17 15802[71:SSi:15801.0,736.0,15511.0] || -> . % 75.92/76.17 15803[69:Spt:15802.0,15505.2,15510.0] || xuntil6(s46)*+ -> . % 75.92/76.17 15804[69:Spt:15802.0,15505.0,15505.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.17 15805[69:Res:53.1,15804.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.17 15807[69:MRR:15805.0,15497.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.17 15809[69:Res:15807.0,61.1] always3(s47) || -> . % 75.92/76.17 15810[69:SSi:15809.0,736.0] || -> . % 75.92/76.17 15811[68:Spt:15810.0,15501.1,15503.0] || xuntil6(s45)* -> . % 75.92/76.17 15812[68:Spt:15810.0,15501.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.17 15815[68:Res:15812.0,61.1] always3(s45) || -> . % 75.92/76.17 15816[68:SSi:15815.0,734.0,15491.0] || -> . % 75.92/76.17 15817[66:Spt:15816.0,15488.2,15490.0] || xuntil6(s44)*+ -> . % 75.92/76.17 15818[66:Spt:15816.0,15488.0,15488.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.17 15819[66:Res:53.1,15818.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.17 15821[66:MRR:15819.0,15477.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.17 15823[66:Res:15821.0,61.1] always3(s45) || -> . % 75.92/76.17 15824[66:SSi:15823.0,734.0] || -> . % 75.92/76.17 15825[65:Spt:15824.0,15481.1,15486.0] || xuntil6(s43)* -> . % 75.92/76.17 15826[65:Spt:15824.0,15481.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.17 15829[65:Res:15826.0,61.1] always3(s43) || -> . % 75.92/76.17 15830[65:SSi:15829.0,732.0,15471.0] || -> . % 75.92/76.17 15831[63:Spt:15830.0,15462.2,15470.0] || xuntil6(s42)*+ -> . % 75.92/76.17 15832[63:Spt:15830.0,15462.0,15462.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.17 15833[63:Res:53.1,15832.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.17 15835[63:MRR:15833.0,15454.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.17 15838[63:Res:15835.0,61.1] always3(s43) || -> . % 75.92/76.17 15839[63:SSi:15838.0,732.0] || -> . % 75.92/76.17 15840[62:Spt:15839.0,15458.1,15460.0] || xuntil6(s41)* -> . % 75.92/76.17 15841[62:Spt:15839.0,15458.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.17 15844[62:Res:15841.0,61.1] always3(s41) || -> . % 75.92/76.17 15845[62:SSi:15844.0,730.0,15448.0] || -> . % 75.92/76.17 15846[60:Spt:15845.0,15442.2,15447.0] || xuntil6(s40)*+ -> . % 75.92/76.17 15847[60:Spt:15845.0,15442.0,15442.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.17 15848[60:Res:53.1,15847.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.17 15850[60:MRR:15848.0,15434.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.17 15852[60:Res:15850.0,61.1] always3(s41) || -> . % 75.92/76.17 15853[60:SSi:15852.0,730.0] || -> . % 75.92/76.17 15854[59:Spt:15853.0,15438.1,15440.0] || xuntil6(s39)* -> . % 75.92/76.17 15855[59:Spt:15853.0,15438.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.17 15858[59:Res:15855.0,61.1] always3(s39) || -> . % 75.92/76.17 15859[59:SSi:15858.0,728.0,15425.0] || -> . % 75.92/76.17 15860[57:Spt:15859.0,15419.2,15424.0] || xuntil6(s38)*+ -> . % 75.92/76.17 15861[57:Spt:15859.0,15419.0,15419.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.17 15862[57:Res:53.1,15861.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.17 15864[57:MRR:15862.0,15411.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.17 15867[57:Res:15864.0,61.1] always3(s39) || -> . % 75.92/76.17 15868[57:SSi:15867.0,728.0] || -> . % 75.92/76.17 15869[56:Spt:15868.0,15415.1,15417.0] || xuntil6(s37)* -> . % 75.92/76.17 15870[56:Spt:15868.0,15415.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.17 15873[56:Res:15870.0,61.1] always3(s37) || -> . % 75.92/76.17 15874[56:SSi:15873.0,726.0,15405.0] || -> . % 75.92/76.17 15875[54:Spt:15874.0,15395.2,15404.0] || xuntil6(s36)*+ -> . % 75.92/76.17 15876[54:Spt:15874.0,15395.0,15395.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.17 15877[54:Res:53.1,15876.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.17 15879[54:MRR:15877.0,15386.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.17 15881[54:Res:15879.0,61.1] always3(s37) || -> . % 75.92/76.17 15882[54:SSi:15881.0,726.0] || -> . % 75.92/76.17 15883[53:Spt:15882.0,15391.1,15393.0] || xuntil6(s35)* -> . % 75.92/76.17 15884[53:Spt:15882.0,15391.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.17 15887[53:Res:15884.0,61.1] always3(s35) || -> . % 75.92/76.17 15888[53:SSi:15887.0,724.0,15380.0] || -> . % 75.92/76.17 15889[51:Spt:15888.0,15377.2,15379.0] || xuntil6(s34)*+ -> . % 75.92/76.17 15890[51:Spt:15888.0,15377.0,15377.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 75.92/76.17 15891[51:Res:53.1,15890.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 75.92/76.17 15893[51:MRR:15891.0,15366.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.17 15895[51:Res:15893.0,61.1] always3(s35) || -> . % 75.92/76.17 15896[51:SSi:15895.0,724.0] || -> . % 75.92/76.17 15897[50:Spt:15896.0,15370.1,15375.0] || xuntil6(s33)* -> . % 75.92/76.17 15898[50:Spt:15896.0,15370.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.17 15901[50:Res:15898.0,61.1] always3(s33) || -> . % 75.92/76.17 15902[50:SSi:15901.0,722.0,15360.0] || -> . % 75.92/76.17 15903[48:Spt:15902.0,15355.2,15359.0] || xuntil6(s32)*+ -> . % 75.92/76.17 15904[48:Spt:15902.0,15355.0,15355.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 75.92/76.17 15905[48:Res:53.1,15904.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 75.92/76.17 15907[49:Spt:15905.0] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.17 15909[49:Res:15907.0,61.1] always3(s32) || -> . % 75.92/76.17 15910[49:SSi:15909.0,721.0,15354.0] || -> . % 75.92/76.17 15911[49:Spt:15910.0,15905.0,15907.0] || m_main_v_state(s32,c_busy)* -> . % 75.92/76.17 15912[49:Spt:15910.0,15905.1] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.17 15916[49:Res:15912.0,61.1] always3(s33) || -> . % 75.92/76.17 15917[49:SSi:15916.0,722.0] || -> . % 75.92/76.17 15918[47:Spt:15917.0,15352.2,15353.0] || xuntil6(s31)*+ -> . % 75.92/76.17 15919[47:Spt:15917.0,15352.0,15352.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 75.92/76.17 15920[47:Res:53.1,15919.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 75.92/76.17 15922[48:Spt:15920.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.17 15924[48:Res:15922.0,61.1] always3(s31) || -> . % 75.92/76.17 15925[48:SSi:15924.0,720.0,15351.0] || -> . % 75.92/76.17 15926[48:Spt:15925.0,15920.0,15922.0] || m_main_v_state(s31,c_busy)* -> . % 75.92/76.17 15927[48:Spt:15925.0,15920.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.17 15931[48:Res:15927.0,61.1] always3(s32) || -> . % 75.92/76.17 15932[48:SSi:15931.0,721.0] || -> . % 75.92/76.17 15933[46:Spt:15932.0,15346.2,15350.0] || xuntil6(s30)*+ -> . % 75.92/76.17 15934[46:Spt:15932.0,15346.0,15346.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.17 15935[46:Res:53.1,15934.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.17 15937[47:Spt:15935.0] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.17 15939[47:Res:15937.0,61.1] always3(s30) || -> . % 75.92/76.17 15940[47:SSi:15939.0,719.0,15345.0] || -> . % 75.92/76.17 15941[47:Spt:15940.0,15935.0,15937.0] || m_main_v_state(s30,c_busy)* -> . % 75.92/76.17 15942[47:Spt:15940.0,15935.1] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.17 15946[47:Res:15942.0,61.1] always3(s31) || -> . % 75.92/76.17 15947[47:SSi:15946.0,720.0] || -> . % 75.92/76.17 15948[45:Spt:15947.0,15343.2,15344.0] || xuntil6(s29)*+ -> . % 75.92/76.17 15949[45:Spt:15947.0,15343.0,15343.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 75.92/76.17 15950[45:Res:53.1,15949.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 75.92/76.17 15952[46:Spt:15950.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.17 15954[46:Res:15952.0,61.1] always3(s29) || -> . % 75.92/76.17 15955[46:SSi:15954.0,718.0,15342.0] || -> . % 75.92/76.17 15956[46:Spt:15955.0,15950.0,15952.0] || m_main_v_state(s29,c_busy)* -> . % 75.92/76.17 15957[46:Spt:15955.0,15950.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.17 15961[46:Res:15957.0,61.1] always3(s30) || -> . % 75.92/76.17 15962[46:SSi:15961.0,719.0] || -> . % 75.92/76.17 15963[44:Spt:15962.0,15337.2,15341.0] || xuntil6(s28)*+ -> . % 75.92/76.17 15964[44:Spt:15962.0,15337.0,15337.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.17 15965[44:Res:53.1,15964.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.17 15967[45:Spt:15965.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.17 15969[45:Res:15967.0,61.1] always3(s28) || -> . % 75.92/76.17 15970[45:SSi:15969.0,717.0,15336.0] || -> . % 75.92/76.17 15971[45:Spt:15970.0,15965.0,15967.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.17 15972[45:Spt:15970.0,15965.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.17 15976[45:Res:15972.0,61.1] always3(s29) || -> . % 75.92/76.17 15977[45:SSi:15976.0,718.0] || -> . % 75.92/76.17 15978[43:Spt:15977.0,15334.2,15335.0] || xuntil6(s27)*+ -> . % 75.92/76.17 15979[43:Spt:15977.0,15334.0,15334.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.17 15980[43:Res:53.1,15979.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.17 15982[44:Spt:15980.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.17 15984[44:Res:15982.0,61.1] always3(s28) || -> . % 75.92/76.17 15985[44:SSi:15984.0,717.0] || -> . % 75.92/76.17 15986[44:Spt:15985.0,15980.1,15982.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.17 15987[44:Spt:15985.0,15980.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.17 15990[44:Res:15987.0,61.1] always3(s27) || -> . % 75.92/76.17 15991[44:SSi:15990.0,716.0,15333.0] || -> . % 75.92/76.17 15992[42:Spt:15991.0,15328.2,15332.0] || xuntil6(s26)*+ -> . % 75.92/76.17 15993[42:Spt:15991.0,15328.0,15328.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.17 15994[42:Res:53.1,15993.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.17 15999[43:Spt:15994.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.17 16001[43:Res:15999.0,61.1] always3(s26) || -> . % 75.92/76.17 16002[43:SSi:16001.0,715.0,15327.0] || -> . % 75.92/76.17 16003[43:Spt:16002.0,15994.0,15999.0] || m_main_v_state(s26,c_busy)* -> . % 75.92/76.17 16004[43:Spt:16002.0,15994.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.17 16008[43:Res:16004.0,61.1] always3(s27) || -> . % 75.92/76.17 16009[43:SSi:16008.0,716.0] || -> . % 75.92/76.17 16010[41:Spt:16009.0,15325.2,15326.0] || xuntil6(s25)*+ -> . % 75.92/76.17 16011[41:Spt:16009.0,15325.0,15325.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.17 16012[41:Res:53.1,16011.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.17 16014[42:Spt:16012.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.17 16016[42:Res:16014.0,61.1] always3(s26) || -> . % 75.92/76.17 16017[42:SSi:16016.0,715.0] || -> . % 75.92/76.17 16018[42:Spt:16017.0,16012.1,16014.0] || m_main_v_state(s26,c_busy)* -> . % 75.92/76.17 16019[42:Spt:16017.0,16012.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.17 16022[42:Res:16019.0,61.1] always3(s25) || -> . % 75.92/76.17 16023[42:SSi:16022.0,714.0,15324.0] || -> . % 75.92/76.17 16024[40:Spt:16023.0,15319.2,15323.0] || xuntil6(s24)*+ -> . % 75.92/76.17 16025[40:Spt:16023.0,15319.0,15319.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.17 16026[40:Res:53.1,16025.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.17 16028[41:Spt:16026.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.17 16030[41:Res:16028.0,61.1] always3(s25) || -> . % 75.92/76.17 16031[41:SSi:16030.0,714.0] || -> . % 75.92/76.17 16032[41:Spt:16031.0,16026.1,16028.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.17 16033[41:Spt:16031.0,16026.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.17 16036[41:Res:16033.0,61.1] always3(s24) || -> . % 75.92/76.17 16037[41:SSi:16036.0,713.0,15318.0] || -> . % 75.92/76.17 16038[39:Spt:16037.0,15316.2,15317.0] || xuntil6(s23)*+ -> . % 75.92/76.17 16039[39:Spt:16037.0,15316.0,15316.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.17 16040[39:Res:53.1,16039.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.17 16045[40:Spt:16040.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.17 16047[40:Res:16045.0,61.1] always3(s23) || -> . % 75.92/76.17 16048[40:SSi:16047.0,712.0,15315.0] || -> . % 75.92/76.17 16049[40:Spt:16048.0,16040.0,16045.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.17 16050[40:Spt:16048.0,16040.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.17 16054[40:Res:16050.0,61.1] always3(s24) || -> . % 75.92/76.17 16055[40:SSi:16054.0,713.0] || -> . % 75.92/76.17 16056[38:Spt:16055.0,15310.2,15314.0] || xuntil6(s22)*+ -> . % 75.92/76.17 16057[38:Spt:16055.0,15310.0,15310.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.17 16058[38:Res:53.1,16057.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.17 16060[39:Spt:16058.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.17 16062[39:Res:16060.0,61.1] always3(s23) || -> . % 75.92/76.17 16063[39:SSi:16062.0,712.0] || -> . % 75.92/76.17 16064[39:Spt:16063.0,16058.1,16060.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.17 16065[39:Spt:16063.0,16058.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.17 16068[39:Res:16065.0,61.1] always3(s22) || -> . % 75.92/76.17 16069[39:SSi:16068.0,711.0,15309.0] || -> . % 75.92/76.17 16070[37:Spt:16069.0,15307.2,15308.0] || xuntil6(s21)*+ -> . % 75.92/76.17 16071[37:Spt:16069.0,15307.0,15307.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.17 16072[37:Res:53.1,16071.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.17 16074[38:Spt:16072.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.17 16076[38:Res:16074.0,61.1] always3(s22) || -> . % 75.92/76.17 16077[38:SSi:16076.0,711.0] || -> . % 75.92/76.17 16078[38:Spt:16077.0,16072.1,16074.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.17 16079[38:Spt:16077.0,16072.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.17 16082[38:Res:16079.0,61.1] always3(s21) || -> . % 75.92/76.17 16083[38:SSi:16082.0,710.0,15306.0] || -> . % 75.92/76.17 16084[36:Spt:16083.0,15301.2,15305.0] || xuntil6(s20)*+ -> . % 75.92/76.17 16085[36:Spt:16083.0,15301.0,15301.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.17 16086[36:Res:53.1,16085.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.17 16091[37:Spt:16086.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.17 16093[37:Res:16091.0,61.1] always3(s20) || -> . % 75.92/76.17 16094[37:SSi:16093.0,709.0,15300.0] || -> . % 75.92/76.17 16095[37:Spt:16094.0,16086.0,16091.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.17 16096[37:Spt:16094.0,16086.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.17 16100[37:Res:16096.0,61.1] always3(s21) || -> . % 75.92/76.17 16101[37:SSi:16100.0,710.0] || -> . % 75.92/76.17 16102[35:Spt:16101.0,15298.2,15299.0] || xuntil6(s19)*+ -> . % 75.92/76.17 16103[35:Spt:16101.0,15298.0,15298.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.17 16104[35:Res:53.1,16103.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.17 16106[36:Spt:16104.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.17 16108[36:Res:16106.0,61.1] always3(s20) || -> . % 75.92/76.17 16109[36:SSi:16108.0,709.0] || -> . % 75.92/76.17 16110[36:Spt:16109.0,16104.1,16106.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.17 16111[36:Spt:16109.0,16104.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.17 16114[36:Res:16111.0,61.1] always3(s19) || -> . % 75.92/76.17 16115[36:SSi:16114.0,708.0,15297.0] || -> . % 75.92/76.17 16116[34:Spt:16115.0,15292.2,15296.0] || xuntil6(s18)*+ -> . % 75.92/76.17 16117[34:Spt:16115.0,15292.0,15292.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.17 16118[34:Res:53.1,16117.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.17 16120[35:Spt:16118.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.17 16122[35:Res:16120.0,61.1] always3(s19) || -> . % 75.92/76.17 16123[35:SSi:16122.0,708.0] || -> . % 75.92/76.17 16124[35:Spt:16123.0,16118.1,16120.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.17 16125[35:Spt:16123.0,16118.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.17 16128[35:Res:16125.0,61.1] always3(s18) || -> . % 75.92/76.17 16129[35:SSi:16128.0,707.0,15291.0] || -> . % 75.92/76.17 16130[33:Spt:16129.0,15289.2,15290.0] || xuntil6(s17)*+ -> . % 75.92/76.17 16131[33:Spt:16129.0,15289.0,15289.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.17 16132[33:Res:53.1,16131.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.17 16137[34:Spt:16132.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.17 16139[34:Res:16137.0,61.1] always3(s17) || -> . % 75.92/76.17 16140[34:SSi:16139.0,706.0,15288.0] || -> . % 75.92/76.17 16141[34:Spt:16140.0,16132.0,16137.0] || m_main_v_state(s17,c_busy)* -> . % 75.92/76.17 16142[34:Spt:16140.0,16132.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.17 16146[34:Res:16142.0,61.1] always3(s18) || -> . % 75.92/76.17 16147[34:SSi:16146.0,707.0] || -> . % 75.92/76.17 16148[32:Spt:16147.0,15283.2,15287.0] || xuntil6(s16)*+ -> . % 75.92/76.17 16149[32:Spt:16147.0,15283.0,15283.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.17 16150[32:Res:53.1,16149.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.17 16152[33:Spt:16150.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.17 16154[33:Res:16152.0,61.1] always3(s17) || -> . % 75.92/76.17 16155[33:SSi:16154.0,706.0] || -> . % 75.92/76.17 16156[33:Spt:16155.0,16150.1,16152.0] || m_main_v_state(s17,c_busy)* -> . % 75.92/76.17 16157[33:Spt:16155.0,16150.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.17 16160[33:Res:16157.0,61.1] always3(s16) || -> . % 75.92/76.17 16161[33:SSi:16160.0,705.0,15282.0] || -> . % 75.92/76.17 16162[31:Spt:16161.0,15280.2,15281.0] || xuntil6(s15)*+ -> . % 75.92/76.17 16163[31:Spt:16161.0,15280.0,15280.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.17 16164[31:Res:53.1,16163.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.17 16166[32:Spt:16164.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.17 16168[32:Res:16166.0,61.1] always3(s16) || -> . % 75.92/76.17 16169[32:SSi:16168.0,705.0] || -> . % 75.92/76.17 16170[32:Spt:16169.0,16164.1,16166.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.17 16171[32:Spt:16169.0,16164.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.17 16174[32:Res:16171.0,61.1] always3(s15) || -> . % 75.92/76.17 16175[32:SSi:16174.0,704.0,15279.0] || -> . % 75.92/76.17 16176[30:Spt:16175.0,15274.2,15278.0] || xuntil6(s14)*+ -> . % 75.92/76.17 16177[30:Spt:16175.0,15274.0,15274.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.17 16178[30:Res:53.1,16177.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.17 16183[31:Spt:16178.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.17 16185[31:Res:16183.0,61.1] always3(s14) || -> . % 75.92/76.17 16186[31:SSi:16185.0,703.0,15273.0] || -> . % 75.92/76.17 16187[31:Spt:16186.0,16178.0,16183.0] || m_main_v_state(s14,c_busy)* -> . % 75.92/76.17 16188[31:Spt:16186.0,16178.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.17 16192[31:Res:16188.0,61.1] always3(s15) || -> . % 75.92/76.17 16193[31:SSi:16192.0,704.0] || -> . % 75.92/76.17 16194[29:Spt:16193.0,15271.2,15272.0] || xuntil6(s13)*+ -> . % 75.92/76.17 16195[29:Spt:16193.0,15271.0,15271.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.17 16196[29:Res:53.1,16195.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.17 16198[30:Spt:16196.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.17 16200[30:Res:16198.0,61.1] always3(s14) || -> . % 75.92/76.17 16201[30:SSi:16200.0,703.0] || -> . % 75.92/76.17 16202[30:Spt:16201.0,16196.1,16198.0] || m_main_v_state(s14,c_busy)* -> . % 75.92/76.17 16203[30:Spt:16201.0,16196.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.17 16206[30:Res:16203.0,61.1] always3(s13) || -> . % 75.92/76.17 16207[30:SSi:16206.0,702.0,15270.0] || -> . % 75.92/76.17 16208[28:Spt:16207.0,15265.2,15269.0] || xuntil6(s12)*+ -> . % 75.92/76.17 16209[28:Spt:16207.0,15265.0,15265.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.17 16210[28:Res:53.1,16209.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.17 16212[29:Spt:16210.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.17 16214[29:Res:16212.0,61.1] always3(s13) || -> . % 75.92/76.17 16215[29:SSi:16214.0,702.0] || -> . % 75.92/76.17 16216[29:Spt:16215.0,16210.1,16212.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.17 16217[29:Spt:16215.0,16210.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.17 16220[29:Res:16217.0,61.1] always3(s12) || -> . % 75.92/76.17 16221[29:SSi:16220.0,701.0,15264.0] || -> . % 75.92/76.17 16222[27:Spt:16221.0,15262.2,15263.0] || xuntil6(s11)*+ -> . % 75.92/76.17 16223[27:Spt:16221.0,15262.0,15262.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.17 16224[27:Res:53.1,16223.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.17 16229[28:Spt:16224.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.17 16231[28:Res:16229.0,61.1] always3(s11) || -> . % 75.92/76.17 16232[28:SSi:16231.0,700.0,15261.0] || -> . % 75.92/76.17 16233[28:Spt:16232.0,16224.0,16229.0] || m_main_v_state(s11,c_busy)* -> . % 75.92/76.17 16234[28:Spt:16232.0,16224.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.17 16238[28:Res:16234.0,61.1] always3(s12) || -> . % 75.92/76.17 16239[28:SSi:16238.0,701.0] || -> . % 75.92/76.17 16240[26:Spt:16239.0,15256.2,15260.0] || xuntil6(s10)*+ -> . % 75.92/76.17 16241[26:Spt:16239.0,15256.0,15256.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.17 16242[26:Res:53.1,16241.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.17 16244[27:Spt:16242.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.17 16246[27:Res:16244.0,61.1] always3(s11) || -> . % 75.92/76.17 16247[27:SSi:16246.0,700.0] || -> . % 75.92/76.17 16248[27:Spt:16247.0,16242.1,16244.0] || m_main_v_state(s11,c_busy)* -> . % 75.92/76.17 16249[27:Spt:16247.0,16242.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.17 16252[27:Res:16249.0,61.1] always3(s10) || -> . % 75.92/76.17 16253[27:SSi:16252.0,699.0,15255.0] || -> . % 75.92/76.17 16254[25:Spt:16253.0,15253.2,15254.0] || xuntil6(s9)*+ -> . % 75.92/76.17 16255[25:Spt:16253.0,15253.0,15253.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.17 16256[25:Res:53.1,16255.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.17 16258[26:Spt:16256.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.17 16260[26:Res:16258.0,61.1] always3(s10) || -> . % 75.92/76.17 16261[26:SSi:16260.0,699.0] || -> . % 75.92/76.17 16262[26:Spt:16261.0,16256.1,16258.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.17 16263[26:Spt:16261.0,16256.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.17 16266[26:Res:16263.0,61.1] always3(s9) || -> . % 75.92/76.17 16267[26:SSi:16266.0,698.0,15252.0] || -> . % 75.92/76.17 16268[24:Spt:16267.0,15247.2,15251.0] || xuntil6(s8)*+ -> . % 75.92/76.17 16269[24:Spt:16267.0,15247.0,15247.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.17 16270[24:Res:53.1,16269.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.17 16275[25:Spt:16270.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.17 16277[25:Res:16275.0,61.1] always3(s8) || -> . % 75.92/76.17 16278[25:SSi:16277.0,697.0,15246.0] || -> . % 75.92/76.17 16279[25:Spt:16278.0,16270.0,16275.0] || m_main_v_state(s8,c_busy)* -> . % 75.92/76.17 16280[25:Spt:16278.0,16270.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.17 16284[25:Res:16280.0,61.1] always3(s9) || -> . % 75.92/76.17 16285[25:SSi:16284.0,698.0] || -> . % 75.92/76.17 16286[23:Spt:16285.0,15244.2,15245.0] || xuntil6(s7)*+ -> . % 75.92/76.17 16287[23:Spt:16285.0,15244.0,15244.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.17 16288[23:Res:53.1,16287.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.17 16290[24:Spt:16288.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.17 16292[24:Res:16290.0,61.1] always3(s8) || -> . % 75.92/76.17 16293[24:SSi:16292.0,697.0] || -> . % 75.92/76.17 16294[24:Spt:16293.0,16288.1,16290.0] || m_main_v_state(s8,c_busy)* -> . % 75.92/76.17 16295[24:Spt:16293.0,16288.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.17 16298[24:Res:16295.0,61.1] always3(s7) || -> . % 75.92/76.17 16299[24:SSi:16298.0,696.0,15243.0] || -> . % 75.92/76.17 16300[22:Spt:16299.0,15238.2,15242.0] || xuntil6(s6)*+ -> . % 75.92/76.17 16301[22:Spt:16299.0,15238.0,15238.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.17 16302[22:Res:53.1,16301.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.17 16304[23:Spt:16302.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.17 16306[23:Res:16304.0,61.1] always3(s7) || -> . % 75.92/76.17 16307[23:SSi:16306.0,696.0] || -> . % 75.92/76.17 16308[23:Spt:16307.0,16302.1,16304.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.17 16309[23:Spt:16307.0,16302.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.17 16312[23:Res:16309.0,61.1] always3(s6) || -> . % 75.92/76.17 16313[23:SSi:16312.0,695.0,15237.0] || -> . % 75.92/76.17 16314[21:Spt:16313.0,15235.2,15236.0] || xuntil6(s5)*+ -> . % 75.92/76.17 16315[21:Spt:16313.0,15235.0,15235.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.17 16316[21:Res:53.1,16315.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.17 16321[22:Spt:16316.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.17 16323[22:Res:16321.0,61.1] always3(s5) || -> . % 75.92/76.17 16324[22:SSi:16323.0,694.0,15234.0] || -> . % 75.92/76.17 16325[22:Spt:16324.0,16316.0,16321.0] || m_main_v_state(s5,c_busy)* -> . % 75.92/76.17 16326[22:Spt:16324.0,16316.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.17 16330[22:Res:16326.0,61.1] always3(s6) || -> . % 75.92/76.17 16331[22:SSi:16330.0,695.0] || -> . % 75.92/76.17 16332[20:Spt:16331.0,15229.2,15233.0] || xuntil6(s4)*+ -> . % 75.92/76.17 16333[20:Spt:16331.0,15229.0,15229.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.17 16334[20:Res:53.1,16333.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.17 16336[21:Spt:16334.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.17 16338[21:Res:16336.0,61.1] always3(s5) || -> . % 75.92/76.17 16339[21:SSi:16338.0,694.0] || -> . % 75.92/76.17 16340[21:Spt:16339.0,16334.1,16336.0] || m_main_v_state(s5,c_busy)* -> . % 75.92/76.17 16341[21:Spt:16339.0,16334.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.17 16344[21:Res:16341.0,61.1] always3(s4) || -> . % 75.92/76.17 16345[21:SSi:16344.0,693.0,15228.0] || -> . % 75.92/76.17 16346[19:Spt:16345.0,15226.2,15227.0] || xuntil6(s3)*+ -> . % 75.92/76.17 16347[19:Spt:16345.0,15226.0,15226.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.17 16348[19:Res:53.1,16347.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.17 16350[20:Spt:16348.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.17 16352[20:Res:16350.0,61.1] always3(s4) || -> . % 75.92/76.17 16353[20:SSi:16352.0,693.0] || -> . % 75.92/76.17 16354[20:Spt:16353.0,16348.1,16350.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.17 16355[20:Spt:16353.0,16348.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.17 16358[20:Res:16355.0,61.1] always3(s3) || -> . % 75.92/76.17 16359[20:SSi:16358.0,692.0,15225.0] || -> . % 75.92/76.17 16360[18:Spt:16359.0,15220.2,15224.0] || xuntil6(s2)*+ -> . % 75.92/76.17 16361[18:Spt:16359.0,15220.0,15220.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.17 16362[18:Res:53.1,16361.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.17 16367[19:Spt:16362.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.17 16369[19:Res:16367.0,61.1] always3(s2) || -> . % 75.92/76.17 16370[19:SSi:16369.0,691.0,15219.0] || -> . % 75.92/76.17 16371[19:Spt:16370.0,16362.0,16367.0] || m_main_v_state(s2,c_busy)* -> . % 75.92/76.17 16372[19:Spt:16370.0,16362.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.17 16376[19:Res:16372.0,61.1] always3(s3) || -> . % 75.92/76.17 16377[19:SSi:16376.0,692.0] || -> . % 75.92/76.17 16378[17:Spt:16377.0,15214.2,15218.0] || xuntil6(s1)*+ -> . % 75.92/76.17 16379[17:Spt:16377.0,15214.0,15214.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.17 16380[17:Res:53.1,16379.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.17 16382[18:Spt:16380.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.17 16384[18:Res:16382.0,61.1] always3(s1) || -> . % 75.92/76.17 16385[18:SSi:16384.0,690.0,15213.0] || -> . % 75.92/76.17 16386[18:Spt:16385.0,16380.0,16382.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.17 16387[18:Spt:16385.0,16380.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.17 16392[18:Res:16387.0,61.1] always3(s2) || -> . % 75.92/76.17 16393[18:SSi:16392.0,691.0] || -> . % 75.92/76.17 16394[16:Spt:16393.0,74.0,15212.0] || xuntil6(s0)*+ -> . % 75.92/76.17 16395[16:Spt:16393.0,74.1] || -> node4(s0)*. % 75.92/76.17 16396[16:MRR:758.1,16394.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.17 16398[16:Res:16396.0,61.1] always3(s1) || -> . % 75.92/76.17 16399[16:SSi:16398.0,690.0] || -> . % 75.92/76.17 16400[15:Spt:16399.0,15202.0,15206.0] || trans(s49,s36)*+ -> . % 75.92/76.17 16401[15:Spt:16399.0,15202.1,15202.2,15202.3,15202.4,15202.5,15202.6,15202.7,15202.8,15202.9,15202.10,15202.11,15202.12,15202.13,15202.14,15202.15,15202.16,15202.17,15202.18,15202.19,15202.20,15202.21,15202.22,15202.23,15202.24,15202.25,15202.26,15202.27,15202.28,15202.29,15202.30,15202.31,15202.32,15202.33,15202.34,15202.35,15202.36] || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.17 16403[15:MRR:15203.0,16400.0] || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.17 16404[15:MRR:15205.1,16400.0] xuntil6(s49) || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.17 16405[16:Spt:16401.0] || -> trans(s49,s35)*. % 75.92/76.17 16406[16:Res:16405.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s35)*. % 75.92/76.17 16408[16:Res:16405.0,60.0] || -> node2(s49,s35)*. % 75.92/76.17 16409[16:SSi:16406.1,50.0,738.0] xuntil6(s49) || -> until2p7(s35)*. % 75.92/76.17 16410[16:Res:16408.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 75.92/76.17 16411[17:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.17 16412[17:MRR:176.0,16411.0] || -> until5(s1)*. % 75.92/76.17 16413[17:MRR:12022.0,16412.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.17 16420[18:Spt:16413.2] || -> xuntil6(s1)*. % 75.92/76.17 16421[18:MRR:175.0,16420.0] || -> until5(s2)*. % 75.92/76.17 16422[18:MRR:12018.0,16421.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.17 16423[19:Spt:16422.2] || -> xuntil6(s2)*. % 75.92/76.17 16424[19:MRR:174.0,16423.0] || -> until5(s3)*. % 75.92/76.17 16425[19:MRR:12014.0,16424.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.17 16429[20:Spt:16425.2] || -> xuntil6(s3)*. % 75.92/76.17 16430[20:MRR:173.0,16429.0] || -> until5(s4)*. % 75.92/76.17 16431[20:MRR:12010.0,16430.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.17 16432[21:Spt:16431.2] || -> xuntil6(s4)*. % 75.92/76.17 16433[21:MRR:172.0,16432.0] || -> until5(s5)*. % 75.92/76.17 16434[21:MRR:12009.0,16433.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.17 16438[22:Spt:16434.2] || -> xuntil6(s5)*. % 75.92/76.17 16439[22:MRR:171.0,16438.0] || -> until5(s6)*. % 75.92/76.17 16440[22:MRR:12002.0,16439.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.17 16441[23:Spt:16440.2] || -> xuntil6(s6)*. % 75.92/76.17 16442[23:MRR:170.0,16441.0] || -> until5(s7)*. % 75.92/76.17 16443[23:MRR:11998.0,16442.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.17 16447[24:Spt:16443.2] || -> xuntil6(s7)*. % 75.92/76.17 16448[24:MRR:169.0,16447.0] || -> until5(s8)*. % 75.92/76.17 16449[24:MRR:11994.0,16448.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.17 16450[25:Spt:16449.2] || -> xuntil6(s8)*. % 75.92/76.17 16451[25:MRR:168.0,16450.0] || -> until5(s9)*. % 75.92/76.17 16452[25:MRR:11990.0,16451.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.17 16456[26:Spt:16452.2] || -> xuntil6(s9)*. % 75.92/76.17 16457[26:MRR:167.0,16456.0] || -> until5(s10)*. % 75.92/76.17 16458[26:MRR:11989.0,16457.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.17 16459[27:Spt:16458.2] || -> xuntil6(s10)*. % 75.92/76.17 16460[27:MRR:166.0,16459.0] || -> until5(s11)*. % 75.92/76.17 16461[27:MRR:11982.0,16460.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.17 16465[28:Spt:16461.2] || -> xuntil6(s11)*. % 75.92/76.17 16466[28:MRR:165.0,16465.0] || -> until5(s12)*. % 75.92/76.17 16467[28:MRR:11978.0,16466.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.17 16468[29:Spt:16467.2] || -> xuntil6(s12)*. % 75.92/76.17 16469[29:MRR:164.0,16468.0] || -> until5(s13)*. % 75.92/76.17 16470[29:MRR:11974.0,16469.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.17 16474[30:Spt:16470.2] || -> xuntil6(s13)*. % 75.92/76.17 16475[30:MRR:163.0,16474.0] || -> until5(s14)*. % 75.92/76.17 16476[30:MRR:11970.0,16475.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.17 16477[31:Spt:16476.2] || -> xuntil6(s14)*. % 75.92/76.17 16478[31:MRR:162.0,16477.0] || -> until5(s15)*. % 75.92/76.17 16479[31:MRR:11969.0,16478.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.17 16483[32:Spt:16479.2] || -> xuntil6(s15)*. % 75.92/76.17 16484[32:MRR:161.0,16483.0] || -> until5(s16)*. % 75.92/76.17 16485[32:MRR:11962.0,16484.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.17 16486[33:Spt:16485.2] || -> xuntil6(s16)*. % 75.92/76.17 16487[33:MRR:160.0,16486.0] || -> until5(s17)*. % 75.92/76.17 16488[33:MRR:11958.0,16487.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.17 16492[34:Spt:16488.2] || -> xuntil6(s17)*. % 75.92/76.17 16493[34:MRR:159.0,16492.0] || -> until5(s18)*. % 75.92/76.17 16494[34:MRR:11954.0,16493.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.17 16495[35:Spt:16494.2] || -> xuntil6(s18)*. % 75.92/76.17 16496[35:MRR:158.0,16495.0] || -> until5(s19)*. % 75.92/76.17 16497[35:MRR:11950.0,16496.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.17 16501[36:Spt:16497.2] || -> xuntil6(s19)*. % 75.92/76.17 16502[36:MRR:157.0,16501.0] || -> until5(s20)*. % 75.92/76.17 16503[36:MRR:11949.0,16502.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.17 16504[37:Spt:16503.2] || -> xuntil6(s20)*. % 75.92/76.17 16505[37:MRR:156.0,16504.0] || -> until5(s21)*. % 75.92/76.17 16506[37:MRR:11942.0,16505.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.17 16510[38:Spt:16506.2] || -> xuntil6(s21)*. % 75.92/76.17 16511[38:MRR:155.0,16510.0] || -> until5(s22)*. % 75.92/76.17 16512[38:MRR:11938.0,16511.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.17 16513[39:Spt:16512.2] || -> xuntil6(s22)*. % 75.92/76.17 16514[39:MRR:154.0,16513.0] || -> until5(s23)*. % 75.92/76.17 16515[39:MRR:11934.0,16514.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.17 16519[40:Spt:16515.2] || -> xuntil6(s23)*. % 75.92/76.17 16520[40:MRR:153.0,16519.0] || -> until5(s24)*. % 75.92/76.17 16521[40:MRR:11930.0,16520.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.17 16522[41:Spt:16521.2] || -> xuntil6(s24)*. % 75.92/76.17 16523[41:MRR:152.0,16522.0] || -> until5(s25)*. % 75.92/76.17 16524[41:MRR:11929.0,16523.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.17 16528[42:Spt:16524.2] || -> xuntil6(s25)*. % 75.92/76.17 16529[42:MRR:151.0,16528.0] || -> until5(s26)*. % 75.92/76.17 16530[42:MRR:11922.0,16529.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.17 16531[43:Spt:16530.2] || -> xuntil6(s26)*. % 75.92/76.17 16532[43:MRR:150.0,16531.0] || -> until5(s27)*. % 75.92/76.17 16533[43:MRR:11918.0,16532.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.17 16537[44:Spt:16533.2] || -> xuntil6(s27)*. % 75.92/76.17 16538[44:MRR:149.0,16537.0] || -> until5(s28)*. % 75.92/76.17 16539[44:MRR:11914.0,16538.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.17 16540[45:Spt:16539.2] || -> xuntil6(s28)*. % 75.92/76.17 16541[45:MRR:148.0,16540.0] || -> until5(s29)*. % 75.92/76.17 16542[45:MRR:11910.0,16541.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.17 16546[46:Spt:16542.2] || -> xuntil6(s29)*. % 75.92/76.17 16547[46:MRR:147.0,16546.0] || -> until5(s30)*. % 75.92/76.17 16548[46:MRR:11909.0,16547.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.17 16549[47:Spt:16548.2] || -> xuntil6(s30)*. % 75.92/76.17 16550[47:MRR:146.0,16549.0] || -> until5(s31)*. % 75.92/76.17 16551[47:MRR:11905.0,16550.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.17 16555[48:Spt:16551.2] || -> xuntil6(s31)*. % 75.92/76.17 16556[48:MRR:145.0,16555.0] || -> until5(s32)*. % 75.92/76.17 16557[48:MRR:11904.0,16556.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.17 16558[49:Spt:16557.2] || -> xuntil6(s32)*. % 75.92/76.17 16559[49:MRR:144.0,16558.0] || -> until5(s33)*. % 75.92/76.17 16560[49:MRR:932.0,16559.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.17 16564[50:Spt:16560.1] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.17 16566[50:Res:16564.0,61.1] always3(s34) || -> . % 75.92/76.17 16567[50:SSi:16566.0,723.0] || -> . % 75.92/76.17 16568[50:Spt:16567.0,16560.1,16564.0] || m_main_v_state(s34,c_busy)*+ -> . % 75.92/76.17 16569[50:Spt:16567.0,16560.0,16560.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 75.92/76.17 16572[50:Res:53.1,16569.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 75.92/76.17 16574[51:Spt:16572.1] || -> xuntil6(s33)*. % 75.92/76.17 16575[51:MRR:143.0,16574.0] || -> until5(s34)*. % 75.92/76.17 16576[51:MRR:12029.0,16575.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.17 16581[52:Spt:16576.2] || -> xuntil6(s34)*. % 75.92/76.17 16582[52:MRR:142.0,16581.0] || -> until5(s35)*. % 75.92/76.17 16583[52:MRR:930.0,16582.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.17 16584[53:Spt:16583.1] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.17 16586[53:Res:16584.0,61.1] always3(s36) || -> . % 75.92/76.17 16587[53:SSi:16586.0,725.0] || -> . % 75.92/76.17 16588[53:Spt:16587.0,16583.1,16584.0] || m_main_v_state(s36,c_busy)*+ -> . % 75.92/76.17 16589[53:Spt:16587.0,16583.0,16583.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 75.92/76.17 16591[53:MRR:813.2,16588.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 75.92/76.17 16592[53:Res:53.1,16589.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 75.92/76.17 16594[54:Spt:16592.1] || -> xuntil6(s35)*. % 75.92/76.17 16595[54:MRR:141.0,16594.0] || -> until5(s36)*. % 75.92/76.17 16596[54:MRR:12033.0,16595.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.17 16604[55:Spt:16596.2] || -> xuntil6(s36)*. % 75.92/76.17 16605[55:MRR:140.0,16604.0] || -> until5(s37)*. % 75.92/76.17 16606[55:MRR:928.0,16605.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.17 16607[56:Spt:16606.1] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.17 16609[56:Res:16607.0,61.1] always3(s38) || -> . % 75.92/76.17 16610[56:SSi:16609.0,727.0] || -> . % 75.92/76.17 16611[56:Spt:16610.0,16606.1,16607.0] || m_main_v_state(s38,c_busy)*+ -> . % 75.92/76.17 16612[56:Spt:16610.0,16606.0,16606.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 75.92/76.17 16614[56:MRR:807.2,16611.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 75.92/76.17 16615[56:Res:53.1,16612.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 75.92/76.17 16620[57:Spt:16615.1] || -> xuntil6(s37)*. % 75.92/76.17 16621[57:MRR:139.0,16620.0] || -> until5(s38)*. % 75.92/76.17 16622[57:MRR:12040.0,16621.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.17 16624[58:Spt:16622.2] || -> xuntil6(s38)*. % 75.92/76.17 16625[58:MRR:138.0,16624.0] || -> until5(s39)*. % 75.92/76.17 16626[58:MRR:926.0,16625.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.17 16627[59:Spt:16626.1] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.17 16629[59:Res:16627.0,61.1] always3(s40) || -> . % 75.92/76.17 16630[59:SSi:16629.0,729.0] || -> . % 75.92/76.17 16631[59:Spt:16630.0,16626.1,16627.0] || m_main_v_state(s40,c_busy)*+ -> . % 75.92/76.17 16632[59:Spt:16630.0,16626.0,16626.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 75.92/76.17 16634[59:MRR:801.2,16631.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 75.92/76.17 16635[59:Res:53.1,16632.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 75.92/76.17 16637[60:Spt:16635.1] || -> xuntil6(s39)*. % 75.92/76.17 16638[60:MRR:137.0,16637.0] || -> until5(s40)*. % 75.92/76.17 16639[60:MRR:12041.0,16638.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.17 16644[61:Spt:16639.2] || -> xuntil6(s40)*. % 75.92/76.17 16645[61:MRR:136.0,16644.0] || -> until5(s41)*. % 75.92/76.17 16646[61:MRR:924.0,16645.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.17 16647[62:Spt:16646.1] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.17 16649[62:Res:16647.0,61.1] always3(s42) || -> . % 75.92/76.17 16650[62:SSi:16649.0,731.0] || -> . % 75.92/76.17 16651[62:Spt:16650.0,16646.1,16647.0] || m_main_v_state(s42,c_busy)*+ -> . % 75.92/76.17 16652[62:Spt:16650.0,16646.0,16646.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 75.92/76.17 16654[62:MRR:795.2,16651.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 75.92/76.17 16655[62:Res:53.1,16652.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 75.92/76.17 16657[63:Spt:16655.1] || -> xuntil6(s41)*. % 75.92/76.17 16658[63:MRR:135.0,16657.0] || -> until5(s42)*. % 75.92/76.17 16659[63:MRR:12045.0,16658.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.17 16667[64:Spt:16659.2] || -> xuntil6(s42)*. % 75.92/76.17 16668[64:MRR:134.0,16667.0] || -> until5(s43)*. % 75.92/76.17 16669[64:MRR:922.0,16668.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.17 16670[65:Spt:16669.1] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.17 16672[65:Res:16670.0,61.1] always3(s44) || -> . % 75.92/76.17 16673[65:SSi:16672.0,733.0] || -> . % 75.92/76.17 16674[65:Spt:16673.0,16669.1,16670.0] || m_main_v_state(s44,c_busy)*+ -> . % 75.92/76.17 16675[65:Spt:16673.0,16669.0,16669.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 75.92/76.17 16677[65:MRR:789.2,16674.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 75.92/76.17 16678[65:Res:53.1,16675.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 75.92/76.17 16683[66:Spt:16678.1] || -> xuntil6(s43)*. % 75.92/76.17 16684[66:MRR:133.0,16683.0] || -> until5(s44)*. % 75.92/76.17 16685[66:MRR:12049.0,16684.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.17 16687[67:Spt:16685.2] || -> xuntil6(s44)*. % 75.92/76.17 16688[67:MRR:132.0,16687.0] || -> until5(s45)*. % 75.92/76.17 16689[67:MRR:920.0,16688.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.17 16690[68:Spt:16689.1] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.17 16692[68:Res:16690.0,61.1] always3(s46) || -> . % 75.92/76.17 16693[68:SSi:16692.0,735.0] || -> . % 75.92/76.17 16694[68:Spt:16693.0,16689.1,16690.0] || m_main_v_state(s46,c_busy)*+ -> . % 75.92/76.17 16695[68:Spt:16693.0,16689.0,16689.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 75.92/76.17 16697[68:MRR:783.2,16694.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 75.92/76.17 16698[68:Res:53.1,16695.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 75.92/76.17 16700[69:Spt:16698.1] || -> xuntil6(s45)*. % 75.92/76.17 16701[69:MRR:131.0,16700.0] || -> until5(s46)*. % 75.92/76.17 16702[69:MRR:12053.0,16701.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.17 16707[70:Spt:16702.2] || -> xuntil6(s46)*. % 75.92/76.17 16708[70:MRR:130.0,16707.0] || -> until5(s47)*. % 75.92/76.17 16709[70:MRR:918.0,16708.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.17 16710[71:Spt:16709.1] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.17 16712[71:Res:16710.0,61.1] always3(s48) || -> . % 75.92/76.17 16713[71:SSi:16712.0,737.0] || -> . % 75.92/76.17 16714[71:Spt:16713.0,16709.1,16710.0] || m_main_v_state(s48,c_busy)*+ -> . % 75.92/76.17 16715[71:Spt:16713.0,16709.0,16709.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 75.92/76.17 16717[71:MRR:777.2,16714.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 75.92/76.17 16718[71:Res:53.1,16715.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 75.92/76.17 16720[72:Spt:16718.1] || -> xuntil6(s47)*. % 75.92/76.17 16721[72:MRR:129.0,16720.0] || -> until5(s48)*. % 75.92/76.17 16722[72:MRR:12057.0,16721.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.17 16730[73:Spt:16722.2] || -> xuntil6(s48)*. % 75.92/76.17 16731[73:MRR:128.0,16730.0] || -> until5(s49)*. % 75.92/76.17 16732[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.17 16733[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.17 16737[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.17 16738[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.17 16739[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.17 16746[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.17 16747[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.17 16751[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.17 16755[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.17 16759[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.17 16766[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.17 16767[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.17 16771[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.17 16775[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.17 16779[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.17 16786[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.17 16787[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.17 16791[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.17 16795[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.17 16799[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.17 16806[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.17 16807[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.17 16811[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.17 16815[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.17 16819[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.17 16826[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.17 16827[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.17 16831[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.17 16835[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.17 16839[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.17 16846[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.17 16847[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.17 16849[16:SoR:16410.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 75.92/76.17 16857[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.17 16858[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.17 16862[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.17 16866[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.17 16870[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.17 16877[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.17 16878[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.17 16882[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.17 16883[16:SoR:16849.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 75.92/76.17 16884[73:SSi:16883.0,50.0,738.0,16731.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 75.92/76.17 16885[74:Spt:16884.1] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.17 16887[74:Res:16885.0,61.1] always3(s35) || -> . % 75.92/76.17 16888[74:SSi:16887.0,724.0,16582.0,16594.0] || -> . % 75.92/76.17 16889[74:Spt:16888.0,16884.1,16885.0] || m_main_v_state(s35,c_busy)*+ -> . % 75.92/76.17 16890[74:Spt:16888.0,16884.0,16884.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.17 16894[74:MRR:16849.2,16889.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.17 16895[74:Res:53.1,16890.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.17 16897[75:Spt:16895.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.17 16899[75:Res:16897.0,61.1] always3(s49) || -> . % 75.92/76.17 16900[75:SSi:16899.0,50.0,738.0,16731.0] || -> . % 75.92/76.17 16901[75:Spt:16900.0,16895.0,16897.0] || m_main_v_state(s49,c_busy)*+ -> . % 75.92/76.17 16902[75:Spt:16900.0,16895.1] || -> xuntil6(s49)*. % 75.92/76.17 16903[75:MRR:16409.0,16902.0] || -> until2p7(s35)*. % 75.92/76.17 16904[75:MRR:231.0,16903.0] || -> until2p7(s36)* node4(s35). % 75.92/76.17 16906[75:MRR:774.2,16901.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 75.92/76.17 16907[76:Spt:16904.0] || -> until2p7(s36)*. % 75.92/76.17 16908[76:MRR:232.0,16907.0] || -> until2p7(s37)* node4(s36). % 75.92/76.17 16909[77:Spt:16908.0] || -> until2p7(s37)*. % 75.92/76.17 16910[77:MRR:235.0,16909.0] || -> until2p7(s38)* node4(s37). % 75.92/76.17 16911[78:Spt:16910.0] || -> until2p7(s38)*. % 75.92/76.17 16912[78:MRR:236.0,16911.0] || -> until2p7(s39)* node4(s38). % 75.92/76.17 16913[79:Spt:16912.0] || -> until2p7(s39)*. % 75.92/76.17 16914[79:MRR:237.0,16913.0] || -> until2p7(s40)* node4(s39). % 75.92/76.17 16915[80:Spt:16914.0] || -> until2p7(s40)*. % 75.92/76.17 16916[80:MRR:238.0,16915.0] || -> until2p7(s41)* node4(s40). % 75.92/76.17 16917[81:Spt:16916.0] || -> until2p7(s41)*. % 75.92/76.17 16918[81:MRR:239.0,16917.0] || -> until2p7(s42)* node4(s41). % 75.92/76.17 16919[82:Spt:16918.0] || -> until2p7(s42)*. % 75.92/76.17 16920[82:MRR:240.0,16919.0] || -> until2p7(s43)* node4(s42). % 75.92/76.17 16921[83:Spt:16920.0] || -> until2p7(s43)*. % 75.92/76.17 16922[83:MRR:241.0,16921.0] || -> until2p7(s44)* node4(s43). % 75.92/76.17 16923[84:Spt:16922.0] || -> until2p7(s44)*. % 75.92/76.17 16924[84:MRR:539.0,16923.0] || -> until2p7(s45)* node4(s44). % 75.92/76.17 16925[85:Spt:16924.0] || -> until2p7(s45)*. % 75.92/76.17 16926[85:MRR:544.0,16925.0] || -> until2p7(s46)* node4(s45). % 75.92/76.17 16927[86:Spt:16926.0] || -> until2p7(s46)*. % 75.92/76.17 16928[86:MRR:549.0,16927.0] || -> until2p7(s47)* node4(s46). % 75.92/76.17 16929[87:Spt:16928.0] || -> until2p7(s47)*. % 75.92/76.17 16930[87:MRR:554.0,16929.0] || -> until2p7(s48)* node4(s47). % 75.92/76.17 16931[88:Spt:16930.0] || -> until2p7(s48)*. % 75.92/76.17 16932[88:MRR:559.0,16931.0] || -> until2p7(s49)* node4(s48). % 75.92/76.17 16933[89:Spt:16932.0] || -> until2p7(s49)*. % 75.92/76.17 16934[89:MRR:194.0,16933.0] || -> node4(s49)*. % 75.92/76.17 16935[89:MRR:16894.0,16934.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.17 16936[89:Res:53.1,16935.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.17 16938[89:MRR:16936.0,16901.0] || -> . % 75.92/76.17 16939[89:Spt:16938.0,16932.0,16933.0] || until2p7(s49)*+ -> . % 75.92/76.17 16940[89:Spt:16938.0,16932.1] || -> node4(s48)*. % 75.92/76.17 16941[89:MRR:16906.0,16940.0] || m_main_v_state(s48,c_ready)*+ -> . % 75.92/76.17 16944[89:Res:53.1,16941.0] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.17 16946[89:MRR:16944.0,16714.0] || -> . % 75.92/76.17 16947[88:Spt:16946.0,16930.0,16931.0] || until2p7(s48)*+ -> . % 75.92/76.17 16948[88:Spt:16946.0,16930.1] || -> node4(s47)*. % 75.92/76.17 16949[88:MRR:16717.0,16948.0] || m_main_v_state(s47,c_ready)*+ -> . % 75.92/76.17 16952[88:Res:53.1,16949.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.17 16955[88:Res:16952.0,61.1] always3(s47) || -> . % 75.92/76.17 16956[88:SSi:16955.0,736.0,16708.0,16720.0,16929.0,16948.0] || -> . % 75.92/76.17 16957[87:Spt:16956.0,16928.0,16929.0] || until2p7(s47)*+ -> . % 75.92/76.17 16958[87:Spt:16956.0,16928.1] || -> node4(s46)*. % 75.92/76.17 16960[87:MRR:780.0,16958.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.17 16984[87:Res:53.1,16960.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.17 16986[87:MRR:16984.0,16694.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.17 16988[87:Res:16986.0,61.1] always3(s47) || -> . % 75.92/76.17 16989[87:SSi:16988.0,736.0,16708.0,16720.0] || -> . % 75.92/76.17 16990[86:Spt:16989.0,16926.0,16927.0] || until2p7(s46)*+ -> . % 75.92/76.17 16991[86:Spt:16989.0,16926.1] || -> node4(s45)*. % 75.92/76.17 16992[86:MRR:16697.0,16991.0] || m_main_v_state(s45,c_ready)*+ -> . % 75.92/76.17 16996[86:Res:53.1,16992.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.17 16999[86:Res:16996.0,61.1] always3(s45) || -> . % 75.92/76.17 17000[86:SSi:16999.0,734.0,16688.0,16700.0,16925.0,16991.0] || -> . % 75.92/76.17 17001[85:Spt:17000.0,16924.0,16925.0] || until2p7(s45)*+ -> . % 75.92/76.17 17002[85:Spt:17000.0,16924.1] || -> node4(s44)*. % 75.92/76.17 17004[85:MRR:786.0,17002.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.17 17015[85:Res:53.1,17004.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.17 17017[85:MRR:17015.0,16674.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.17 17019[85:Res:17017.0,61.1] always3(s45) || -> . % 75.92/76.17 17020[85:SSi:17019.0,734.0,16688.0,16700.0] || -> . % 75.92/76.17 17021[84:Spt:17020.0,16922.0,16923.0] || until2p7(s44)*+ -> . % 75.92/76.17 17022[84:Spt:17020.0,16922.1] || -> node4(s43)*. % 75.92/76.17 17023[84:MRR:16677.0,17022.0] || m_main_v_state(s43,c_ready)*+ -> . % 75.92/76.17 17026[84:Res:53.1,17023.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.17 17029[84:Res:17026.0,61.1] always3(s43) || -> . % 75.92/76.17 17030[84:SSi:17029.0,732.0,16668.0,16683.0,16921.0,17022.0] || -> . % 75.92/76.17 17031[83:Spt:17030.0,16920.0,16921.0] || until2p7(s43)*+ -> . % 75.92/76.17 17032[83:Spt:17030.0,16920.1] || -> node4(s42)*. % 75.92/76.17 17034[83:MRR:792.0,17032.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.17 17046[83:Res:53.1,17034.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.17 17048[83:MRR:17046.0,16651.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.17 17050[83:Res:17048.0,61.1] always3(s43) || -> . % 75.92/76.17 17051[83:SSi:17050.0,732.0,16668.0,16683.0] || -> . % 75.92/76.17 17052[82:Spt:17051.0,16918.0,16919.0] || until2p7(s42)*+ -> . % 75.92/76.17 17053[82:Spt:17051.0,16918.1] || -> node4(s41)*. % 75.92/76.17 17054[82:MRR:16654.0,17053.0] || m_main_v_state(s41,c_ready)*+ -> . % 75.92/76.17 17057[82:Res:53.1,17054.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.17 17060[82:Res:17057.0,61.1] always3(s41) || -> . % 75.92/76.17 17061[82:SSi:17060.0,730.0,16645.0,16657.0,16917.0,17053.0] || -> . % 75.92/76.17 17062[81:Spt:17061.0,16916.0,16917.0] || until2p7(s41)*+ -> . % 75.92/76.17 17063[81:Spt:17061.0,16916.1] || -> node4(s40)*. % 75.92/76.17 17065[81:MRR:798.0,17063.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.17 17077[81:Res:53.1,17065.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.17 17079[81:MRR:17077.0,16631.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.17 17084[81:Res:17079.0,61.1] always3(s41) || -> . % 75.92/76.17 17085[81:SSi:17084.0,730.0,16645.0,16657.0] || -> . % 75.92/76.17 17086[80:Spt:17085.0,16914.0,16915.0] || until2p7(s40)*+ -> . % 75.92/76.17 17087[80:Spt:17085.0,16914.1] || -> node4(s39)*. % 75.92/76.17 17088[80:MRR:16634.0,17087.0] || m_main_v_state(s39,c_ready)*+ -> . % 75.92/76.17 17091[80:Res:53.1,17088.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.17 17095[80:Res:17091.0,61.1] always3(s39) || -> . % 75.92/76.17 17096[80:SSi:17095.0,728.0,16625.0,16637.0,16913.0,17087.0] || -> . % 75.92/76.17 17097[79:Spt:17096.0,16912.0,16913.0] || until2p7(s39)*+ -> . % 75.92/76.17 17098[79:Spt:17096.0,16912.1] || -> node4(s38)*. % 75.92/76.17 17100[79:MRR:804.0,17098.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.17 17111[79:Res:53.1,17100.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.17 17113[79:MRR:17111.0,16611.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.17 17115[79:Res:17113.0,61.1] always3(s39) || -> . % 75.92/76.17 17116[79:SSi:17115.0,728.0,16625.0,16637.0] || -> . % 75.92/76.17 17117[78:Spt:17116.0,16910.0,16911.0] || until2p7(s38)*+ -> . % 75.92/76.17 17118[78:Spt:17116.0,16910.1] || -> node4(s37)*. % 75.92/76.17 17119[78:MRR:16614.0,17118.0] || m_main_v_state(s37,c_ready)*+ -> . % 75.92/76.17 17123[78:Res:53.1,17119.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.17 17126[78:Res:17123.0,61.1] always3(s37) || -> . % 75.92/76.17 17127[78:SSi:17126.0,726.0,16605.0,16620.0,16909.0,17118.0] || -> . % 75.92/76.17 17128[77:Spt:17127.0,16908.0,16909.0] || until2p7(s37)*+ -> . % 75.92/76.17 17129[77:Spt:17127.0,16908.1] || -> node4(s36)*. % 75.92/76.17 17131[77:MRR:810.0,17129.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.17 17142[77:Res:53.1,17131.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.17 17144[77:MRR:17142.0,16588.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.17 17146[77:Res:17144.0,61.1] always3(s37) || -> . % 75.92/76.17 17147[77:SSi:17146.0,726.0,16605.0,16620.0] || -> . % 75.92/76.17 17148[76:Spt:17147.0,16904.0,16907.0] || until2p7(s36)*+ -> . % 75.92/76.17 17149[76:Spt:17147.0,16904.1] || -> node4(s35)*. % 75.92/76.17 17150[76:MRR:16591.0,17149.0] || m_main_v_state(s35,c_ready)*+ -> . % 75.92/76.17 17153[76:Res:53.1,17150.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.17 17155[76:MRR:17153.0,16889.0] || -> . % 75.92/76.17 17156[73:Spt:17155.0,16722.2,16730.0] || xuntil6(s48)*+ -> . % 75.92/76.17 17157[73:Spt:17155.0,16722.0,16722.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.17 17158[73:Res:53.1,17157.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.17 17160[73:MRR:17158.0,16714.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.17 17162[73:Res:17160.0,61.1] always3(s49) || -> . % 75.92/76.17 17163[73:SSi:17162.0,50.0,738.0] || -> . % 75.92/76.17 17164[72:Spt:17163.0,16718.1,16720.0] || xuntil6(s47)* -> . % 75.92/76.17 17165[72:Spt:17163.0,16718.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.17 17168[72:Res:17165.0,61.1] always3(s47) || -> . % 75.92/76.17 17169[72:SSi:17168.0,736.0,16708.0] || -> . % 75.92/76.17 17170[70:Spt:17169.0,16702.2,16707.0] || xuntil6(s46)*+ -> . % 75.92/76.17 17171[70:Spt:17169.0,16702.0,16702.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.17 17172[70:Res:53.1,17171.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.17 17174[70:MRR:17172.0,16694.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.17 17177[70:Res:17174.0,61.1] always3(s47) || -> . % 75.92/76.17 17178[70:SSi:17177.0,736.0] || -> . % 75.92/76.17 17179[69:Spt:17178.0,16698.1,16700.0] || xuntil6(s45)* -> . % 75.92/76.17 17180[69:Spt:17178.0,16698.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.17 17183[69:Res:17180.0,61.1] always3(s45) || -> . % 75.92/76.17 17184[69:SSi:17183.0,734.0,16688.0] || -> . % 75.92/76.17 17185[67:Spt:17184.0,16685.2,16687.0] || xuntil6(s44)*+ -> . % 75.92/76.17 17186[67:Spt:17184.0,16685.0,16685.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.17 17187[67:Res:53.1,17186.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.17 17189[67:MRR:17187.0,16674.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.17 17191[67:Res:17189.0,61.1] always3(s45) || -> . % 75.92/76.17 17192[67:SSi:17191.0,734.0] || -> . % 75.92/76.17 17193[66:Spt:17192.0,16678.1,16683.0] || xuntil6(s43)* -> . % 75.92/76.17 17194[66:Spt:17192.0,16678.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.17 17197[66:Res:17194.0,61.1] always3(s43) || -> . % 75.92/76.17 17198[66:SSi:17197.0,732.0,16668.0] || -> . % 75.92/76.17 17199[64:Spt:17198.0,16659.2,16667.0] || xuntil6(s42)*+ -> . % 75.92/76.17 17200[64:Spt:17198.0,16659.0,16659.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.17 17201[64:Res:53.1,17200.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.17 17203[64:MRR:17201.0,16651.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.17 17206[64:Res:17203.0,61.1] always3(s43) || -> . % 75.92/76.17 17207[64:SSi:17206.0,732.0] || -> . % 75.92/76.17 17208[63:Spt:17207.0,16655.1,16657.0] || xuntil6(s41)* -> . % 75.92/76.17 17209[63:Spt:17207.0,16655.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.17 17212[63:Res:17209.0,61.1] always3(s41) || -> . % 75.92/76.17 17213[63:SSi:17212.0,730.0,16645.0] || -> . % 75.92/76.17 17214[61:Spt:17213.0,16639.2,16644.0] || xuntil6(s40)*+ -> . % 75.92/76.17 17215[61:Spt:17213.0,16639.0,16639.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.17 17216[61:Res:53.1,17215.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.17 17218[61:MRR:17216.0,16631.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.17 17220[61:Res:17218.0,61.1] always3(s41) || -> . % 75.92/76.17 17221[61:SSi:17220.0,730.0] || -> . % 75.92/76.17 17222[60:Spt:17221.0,16635.1,16637.0] || xuntil6(s39)* -> . % 75.92/76.17 17223[60:Spt:17221.0,16635.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.17 17226[60:Res:17223.0,61.1] always3(s39) || -> . % 75.92/76.17 17227[60:SSi:17226.0,728.0,16625.0] || -> . % 75.92/76.17 17228[58:Spt:17227.0,16622.2,16624.0] || xuntil6(s38)*+ -> . % 75.92/76.17 17229[58:Spt:17227.0,16622.0,16622.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.17 17230[58:Res:53.1,17229.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.17 17232[58:MRR:17230.0,16611.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.17 17235[58:Res:17232.0,61.1] always3(s39) || -> . % 75.92/76.17 17236[58:SSi:17235.0,728.0] || -> . % 75.92/76.17 17237[57:Spt:17236.0,16615.1,16620.0] || xuntil6(s37)* -> . % 75.92/76.17 17238[57:Spt:17236.0,16615.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.17 17241[57:Res:17238.0,61.1] always3(s37) || -> . % 75.92/76.17 17242[57:SSi:17241.0,726.0,16605.0] || -> . % 75.92/76.17 17243[55:Spt:17242.0,16596.2,16604.0] || xuntil6(s36)*+ -> . % 75.92/76.17 17244[55:Spt:17242.0,16596.0,16596.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.17 17245[55:Res:53.1,17244.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.17 17247[55:MRR:17245.0,16588.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.17 17249[55:Res:17247.0,61.1] always3(s37) || -> . % 75.92/76.17 17250[55:SSi:17249.0,726.0] || -> . % 75.92/76.17 17251[54:Spt:17250.0,16592.1,16594.0] || xuntil6(s35)* -> . % 75.92/76.17 17252[54:Spt:17250.0,16592.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.17 17255[54:Res:17252.0,61.1] always3(s35) || -> . % 75.92/76.17 17256[54:SSi:17255.0,724.0,16582.0] || -> . % 75.92/76.17 17257[52:Spt:17256.0,16576.2,16581.0] || xuntil6(s34)*+ -> . % 75.92/76.17 17258[52:Spt:17256.0,16576.0,16576.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 75.92/76.17 17259[52:Res:53.1,17258.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 75.92/76.17 17261[52:MRR:17259.0,16568.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.17 17263[52:Res:17261.0,61.1] always3(s35) || -> . % 75.92/76.17 17264[52:SSi:17263.0,724.0] || -> . % 75.92/76.17 17265[51:Spt:17264.0,16572.1,16574.0] || xuntil6(s33)* -> . % 75.92/76.17 17266[51:Spt:17264.0,16572.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.17 17269[51:Res:17266.0,61.1] always3(s33) || -> . % 75.92/76.17 17270[51:SSi:17269.0,722.0,16559.0] || -> . % 75.92/76.17 17271[49:Spt:17270.0,16557.2,16558.0] || xuntil6(s32)*+ -> . % 75.92/76.17 17272[49:Spt:17270.0,16557.0,16557.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 75.92/76.17 17273[49:Res:53.1,17272.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 75.92/76.17 17275[50:Spt:17273.0] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.17 17277[50:Res:17275.0,61.1] always3(s32) || -> . % 75.92/76.17 17278[50:SSi:17277.0,721.0,16556.0] || -> . % 75.92/76.17 17279[50:Spt:17278.0,17273.0,17275.0] || m_main_v_state(s32,c_busy)* -> . % 75.92/76.17 17280[50:Spt:17278.0,17273.1] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.17 17284[50:Res:17280.0,61.1] always3(s33) || -> . % 75.92/76.17 17285[50:SSi:17284.0,722.0] || -> . % 75.92/76.17 17286[48:Spt:17285.0,16551.2,16555.0] || xuntil6(s31)*+ -> . % 75.92/76.17 17287[48:Spt:17285.0,16551.0,16551.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 75.92/76.17 17288[48:Res:53.1,17287.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 75.92/76.17 17290[49:Spt:17288.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.17 17292[49:Res:17290.0,61.1] always3(s31) || -> . % 75.92/76.17 17293[49:SSi:17292.0,720.0,16550.0] || -> . % 75.92/76.17 17294[49:Spt:17293.0,17288.0,17290.0] || m_main_v_state(s31,c_busy)* -> . % 75.92/76.17 17295[49:Spt:17293.0,17288.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.17 17299[49:Res:17295.0,61.1] always3(s32) || -> . % 75.92/76.17 17300[49:SSi:17299.0,721.0] || -> . % 75.92/76.17 17301[47:Spt:17300.0,16548.2,16549.0] || xuntil6(s30)*+ -> . % 75.92/76.17 17302[47:Spt:17300.0,16548.0,16548.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.17 17303[47:Res:53.1,17302.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.17 17305[48:Spt:17303.0] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.17 17307[48:Res:17305.0,61.1] always3(s30) || -> . % 75.92/76.17 17308[48:SSi:17307.0,719.0,16547.0] || -> . % 75.92/76.17 17309[48:Spt:17308.0,17303.0,17305.0] || m_main_v_state(s30,c_busy)* -> . % 75.92/76.17 17310[48:Spt:17308.0,17303.1] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.17 17314[48:Res:17310.0,61.1] always3(s31) || -> . % 75.92/76.17 17315[48:SSi:17314.0,720.0] || -> . % 75.92/76.17 17316[46:Spt:17315.0,16542.2,16546.0] || xuntil6(s29)*+ -> . % 75.92/76.17 17317[46:Spt:17315.0,16542.0,16542.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 75.92/76.17 17318[46:Res:53.1,17317.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 75.92/76.17 17320[47:Spt:17318.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.17 17322[47:Res:17320.0,61.1] always3(s29) || -> . % 75.92/76.17 17323[47:SSi:17322.0,718.0,16541.0] || -> . % 75.92/76.17 17324[47:Spt:17323.0,17318.0,17320.0] || m_main_v_state(s29,c_busy)* -> . % 75.92/76.17 17325[47:Spt:17323.0,17318.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.17 17329[47:Res:17325.0,61.1] always3(s30) || -> . % 75.92/76.17 17330[47:SSi:17329.0,719.0] || -> . % 75.92/76.17 17331[45:Spt:17330.0,16539.2,16540.0] || xuntil6(s28)*+ -> . % 75.92/76.17 17332[45:Spt:17330.0,16539.0,16539.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.17 17333[45:Res:53.1,17332.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.17 17335[46:Spt:17333.0] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.17 17337[46:Res:17335.0,61.1] always3(s28) || -> . % 75.92/76.17 17338[46:SSi:17337.0,717.0,16538.0] || -> . % 75.92/76.17 17339[46:Spt:17338.0,17333.0,17335.0] || m_main_v_state(s28,c_busy)* -> . % 75.92/76.17 17340[46:Spt:17338.0,17333.1] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.17 17344[46:Res:17340.0,61.1] always3(s29) || -> . % 75.92/76.17 17345[46:SSi:17344.0,718.0] || -> . % 75.92/76.17 17346[44:Spt:17345.0,16533.2,16537.0] || xuntil6(s27)*+ -> . % 75.92/76.17 17347[44:Spt:17345.0,16533.0,16533.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 75.92/76.17 17348[44:Res:53.1,17347.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 75.92/76.17 17350[45:Spt:17348.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.17 17352[45:Res:17350.0,61.1] always3(s27) || -> . % 75.92/76.17 17353[45:SSi:17352.0,716.0,16532.0] || -> . % 75.92/76.17 17354[45:Spt:17353.0,17348.0,17350.0] || m_main_v_state(s27,c_busy)* -> . % 75.92/76.17 17355[45:Spt:17353.0,17348.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.17 17359[45:Res:17355.0,61.1] always3(s28) || -> . % 75.92/76.17 17360[45:SSi:17359.0,717.0] || -> . % 75.92/76.17 17361[43:Spt:17360.0,16530.2,16531.0] || xuntil6(s26)*+ -> . % 75.92/76.17 17362[43:Spt:17360.0,16530.0,16530.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.17 17363[43:Res:53.1,17362.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.17 17365[44:Spt:17363.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.17 17367[44:Res:17365.0,61.1] always3(s26) || -> . % 75.92/76.17 17368[44:SSi:17367.0,715.0,16529.0] || -> . % 75.92/76.17 17369[44:Spt:17368.0,17363.0,17365.0] || m_main_v_state(s26,c_busy)* -> . % 75.92/76.17 17370[44:Spt:17368.0,17363.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.17 17374[44:Res:17370.0,61.1] always3(s27) || -> . % 75.92/76.17 17375[44:SSi:17374.0,716.0] || -> . % 75.92/76.17 17376[42:Spt:17375.0,16524.2,16528.0] || xuntil6(s25)*+ -> . % 75.92/76.17 17377[42:Spt:17375.0,16524.0,16524.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.17 17378[42:Res:53.1,17377.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.17 17380[43:Spt:17378.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.17 17382[43:Res:17380.0,61.1] always3(s25) || -> . % 75.92/76.17 17383[43:SSi:17382.0,714.0,16523.0] || -> . % 75.92/76.17 17384[43:Spt:17383.0,17378.0,17380.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.17 17385[43:Spt:17383.0,17378.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.17 17389[43:Res:17385.0,61.1] always3(s26) || -> . % 75.92/76.17 17390[43:SSi:17389.0,715.0] || -> . % 75.92/76.17 17391[41:Spt:17390.0,16521.2,16522.0] || xuntil6(s24)*+ -> . % 75.92/76.17 17392[41:Spt:17390.0,16521.0,16521.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.17 17393[41:Res:53.1,17392.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.17 17395[42:Spt:17393.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.17 17397[42:Res:17395.0,61.1] always3(s24) || -> . % 75.92/76.17 17398[42:SSi:17397.0,713.0,16520.0] || -> . % 75.92/76.17 17399[42:Spt:17398.0,17393.0,17395.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.17 17400[42:Spt:17398.0,17393.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.17 17404[42:Res:17400.0,61.1] always3(s25) || -> . % 75.92/76.17 17405[42:SSi:17404.0,714.0] || -> . % 75.92/76.17 17406[40:Spt:17405.0,16515.2,16519.0] || xuntil6(s23)*+ -> . % 75.92/76.17 17407[40:Spt:17405.0,16515.0,16515.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.17 17408[40:Res:53.1,17407.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.17 17413[41:Spt:17408.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.17 17415[41:Res:17413.0,61.1] always3(s23) || -> . % 75.92/76.17 17416[41:SSi:17415.0,712.0,16514.0] || -> . % 75.92/76.17 17417[41:Spt:17416.0,17408.0,17413.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.17 17418[41:Spt:17416.0,17408.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.17 17422[41:Res:17418.0,61.1] always3(s24) || -> . % 75.92/76.17 17423[41:SSi:17422.0,713.0] || -> . % 75.92/76.17 17424[39:Spt:17423.0,16512.2,16513.0] || xuntil6(s22)*+ -> . % 75.92/76.17 17425[39:Spt:17423.0,16512.0,16512.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.17 17426[39:Res:53.1,17425.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.17 17428[40:Spt:17426.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.17 17430[40:Res:17428.0,61.1] always3(s22) || -> . % 75.92/76.17 17431[40:SSi:17430.0,711.0,16511.0] || -> . % 75.92/76.17 17432[40:Spt:17431.0,17426.0,17428.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.17 17433[40:Spt:17431.0,17426.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.17 17437[40:Res:17433.0,61.1] always3(s23) || -> . % 75.92/76.17 17438[40:SSi:17437.0,712.0] || -> . % 75.92/76.17 17439[38:Spt:17438.0,16506.2,16510.0] || xuntil6(s21)*+ -> . % 75.92/76.17 17440[38:Spt:17438.0,16506.0,16506.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.17 17441[38:Res:53.1,17440.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.17 17443[39:Spt:17441.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.17 17445[39:Res:17443.0,61.1] always3(s21) || -> . % 75.92/76.17 17446[39:SSi:17445.0,710.0,16505.0] || -> . % 75.92/76.17 17447[39:Spt:17446.0,17441.0,17443.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.17 17448[39:Spt:17446.0,17441.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.17 17452[39:Res:17448.0,61.1] always3(s22) || -> . % 75.92/76.17 17453[39:SSi:17452.0,711.0] || -> . % 75.92/76.17 17454[37:Spt:17453.0,16503.2,16504.0] || xuntil6(s20)*+ -> . % 75.92/76.17 17455[37:Spt:17453.0,16503.0,16503.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.17 17456[37:Res:53.1,17455.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.17 17461[38:Spt:17456.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.17 17463[38:Res:17461.0,61.1] always3(s20) || -> . % 75.92/76.17 17464[38:SSi:17463.0,709.0,16502.0] || -> . % 75.92/76.17 17465[38:Spt:17464.0,17456.0,17461.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.17 17466[38:Spt:17464.0,17456.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.17 17470[38:Res:17466.0,61.1] always3(s21) || -> . % 75.92/76.17 17471[38:SSi:17470.0,710.0] || -> . % 75.92/76.17 17472[36:Spt:17471.0,16497.2,16501.0] || xuntil6(s19)*+ -> . % 75.92/76.17 17473[36:Spt:17471.0,16497.0,16497.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.17 17474[36:Res:53.1,17473.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.17 17476[37:Spt:17474.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.17 17478[37:Res:17476.0,61.1] always3(s19) || -> . % 75.92/76.17 17479[37:SSi:17478.0,708.0,16496.0] || -> . % 75.92/76.17 17480[37:Spt:17479.0,17474.0,17476.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.17 17481[37:Spt:17479.0,17474.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.17 17485[37:Res:17481.0,61.1] always3(s20) || -> . % 75.92/76.17 17486[37:SSi:17485.0,709.0] || -> . % 75.92/76.17 17487[35:Spt:17486.0,16494.2,16495.0] || xuntil6(s18)*+ -> . % 75.92/76.17 17488[35:Spt:17486.0,16494.0,16494.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.17 17489[35:Res:53.1,17488.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.17 17491[36:Spt:17489.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.17 17493[36:Res:17491.0,61.1] always3(s18) || -> . % 75.92/76.17 17494[36:SSi:17493.0,707.0,16493.0] || -> . % 75.92/76.17 17495[36:Spt:17494.0,17489.0,17491.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.17 17496[36:Spt:17494.0,17489.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.17 17500[36:Res:17496.0,61.1] always3(s19) || -> . % 75.92/76.17 17501[36:SSi:17500.0,708.0] || -> . % 75.92/76.17 17502[34:Spt:17501.0,16488.2,16492.0] || xuntil6(s17)*+ -> . % 75.92/76.17 17503[34:Spt:17501.0,16488.0,16488.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.17 17504[34:Res:53.1,17503.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.17 17509[35:Spt:17504.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.17 17511[35:Res:17509.0,61.1] always3(s17) || -> . % 75.92/76.17 17512[35:SSi:17511.0,706.0,16487.0] || -> . % 75.92/76.17 17513[35:Spt:17512.0,17504.0,17509.0] || m_main_v_state(s17,c_busy)* -> . % 75.92/76.17 17514[35:Spt:17512.0,17504.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.17 17518[35:Res:17514.0,61.1] always3(s18) || -> . % 75.92/76.17 17519[35:SSi:17518.0,707.0] || -> . % 75.92/76.17 17520[33:Spt:17519.0,16485.2,16486.0] || xuntil6(s16)*+ -> . % 75.92/76.17 17521[33:Spt:17519.0,16485.0,16485.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.17 17522[33:Res:53.1,17521.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.17 17524[34:Spt:17522.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.17 17526[34:Res:17524.0,61.1] always3(s16) || -> . % 75.92/76.17 17527[34:SSi:17526.0,705.0,16484.0] || -> . % 75.92/76.17 17528[34:Spt:17527.0,17522.0,17524.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.17 17529[34:Spt:17527.0,17522.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.17 17533[34:Res:17529.0,61.1] always3(s17) || -> . % 75.92/76.17 17534[34:SSi:17533.0,706.0] || -> . % 75.92/76.17 17535[32:Spt:17534.0,16479.2,16483.0] || xuntil6(s15)*+ -> . % 75.92/76.17 17536[32:Spt:17534.0,16479.0,16479.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.17 17537[32:Res:53.1,17536.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.17 17539[33:Spt:17537.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.17 17541[33:Res:17539.0,61.1] always3(s15) || -> . % 75.92/76.17 17542[33:SSi:17541.0,704.0,16478.0] || -> . % 75.92/76.17 17543[33:Spt:17542.0,17537.0,17539.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.17 17544[33:Spt:17542.0,17537.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.17 17548[33:Res:17544.0,61.1] always3(s16) || -> . % 75.92/76.17 17549[33:SSi:17548.0,705.0] || -> . % 75.92/76.17 17550[31:Spt:17549.0,16476.2,16477.0] || xuntil6(s14)*+ -> . % 75.92/76.17 17551[31:Spt:17549.0,16476.0,16476.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.17 17552[31:Res:53.1,17551.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.17 17557[32:Spt:17552.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.17 17559[32:Res:17557.0,61.1] always3(s14) || -> . % 75.92/76.17 17560[32:SSi:17559.0,703.0,16475.0] || -> . % 75.92/76.17 17561[32:Spt:17560.0,17552.0,17557.0] || m_main_v_state(s14,c_busy)* -> . % 75.92/76.17 17562[32:Spt:17560.0,17552.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.17 17566[32:Res:17562.0,61.1] always3(s15) || -> . % 75.92/76.17 17567[32:SSi:17566.0,704.0] || -> . % 75.92/76.17 17568[30:Spt:17567.0,16470.2,16474.0] || xuntil6(s13)*+ -> . % 75.92/76.17 17569[30:Spt:17567.0,16470.0,16470.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.17 17570[30:Res:53.1,17569.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.17 17572[31:Spt:17570.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.17 17574[31:Res:17572.0,61.1] always3(s13) || -> . % 75.92/76.17 17575[31:SSi:17574.0,702.0,16469.0] || -> . % 75.92/76.17 17576[31:Spt:17575.0,17570.0,17572.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.17 17577[31:Spt:17575.0,17570.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.17 17581[31:Res:17577.0,61.1] always3(s14) || -> . % 75.92/76.17 17582[31:SSi:17581.0,703.0] || -> . % 75.92/76.17 17583[29:Spt:17582.0,16467.2,16468.0] || xuntil6(s12)*+ -> . % 75.92/76.17 17584[29:Spt:17582.0,16467.0,16467.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.17 17585[29:Res:53.1,17584.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.17 17587[30:Spt:17585.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.17 17589[30:Res:17587.0,61.1] always3(s12) || -> . % 75.92/76.17 17590[30:SSi:17589.0,701.0,16466.0] || -> . % 75.92/76.17 17591[30:Spt:17590.0,17585.0,17587.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.17 17592[30:Spt:17590.0,17585.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.17 17596[30:Res:17592.0,61.1] always3(s13) || -> . % 75.92/76.17 17597[30:SSi:17596.0,702.0] || -> . % 75.92/76.17 17598[28:Spt:17597.0,16461.2,16465.0] || xuntil6(s11)*+ -> . % 75.92/76.17 17599[28:Spt:17597.0,16461.0,16461.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.17 17600[28:Res:53.1,17599.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.17 17605[29:Spt:17600.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.17 17607[29:Res:17605.0,61.1] always3(s11) || -> . % 75.92/76.17 17608[29:SSi:17607.0,700.0,16460.0] || -> . % 75.92/76.17 17609[29:Spt:17608.0,17600.0,17605.0] || m_main_v_state(s11,c_busy)* -> . % 75.92/76.17 17610[29:Spt:17608.0,17600.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.17 17614[29:Res:17610.0,61.1] always3(s12) || -> . % 75.92/76.17 17615[29:SSi:17614.0,701.0] || -> . % 75.92/76.17 17616[27:Spt:17615.0,16458.2,16459.0] || xuntil6(s10)*+ -> . % 75.92/76.17 17617[27:Spt:17615.0,16458.0,16458.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.17 17618[27:Res:53.1,17617.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.17 17620[28:Spt:17618.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.17 17622[28:Res:17620.0,61.1] always3(s10) || -> . % 75.92/76.17 17623[28:SSi:17622.0,699.0,16457.0] || -> . % 75.92/76.17 17624[28:Spt:17623.0,17618.0,17620.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.17 17625[28:Spt:17623.0,17618.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.17 17629[28:Res:17625.0,61.1] always3(s11) || -> . % 75.92/76.17 17630[28:SSi:17629.0,700.0] || -> . % 75.92/76.17 17631[26:Spt:17630.0,16452.2,16456.0] || xuntil6(s9)*+ -> . % 75.92/76.17 17632[26:Spt:17630.0,16452.0,16452.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.17 17633[26:Res:53.1,17632.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.17 17635[27:Spt:17633.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.17 17637[27:Res:17635.0,61.1] always3(s9) || -> . % 75.92/76.17 17638[27:SSi:17637.0,698.0,16451.0] || -> . % 75.92/76.17 17639[27:Spt:17638.0,17633.0,17635.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.17 17640[27:Spt:17638.0,17633.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.17 17644[27:Res:17640.0,61.1] always3(s10) || -> . % 75.92/76.17 17645[27:SSi:17644.0,699.0] || -> . % 75.92/76.17 17646[25:Spt:17645.0,16449.2,16450.0] || xuntil6(s8)*+ -> . % 75.92/76.17 17647[25:Spt:17645.0,16449.0,16449.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.17 17648[25:Res:53.1,17647.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.17 17653[26:Spt:17648.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.17 17655[26:Res:17653.0,61.1] always3(s8) || -> . % 75.92/76.17 17656[26:SSi:17655.0,697.0,16448.0] || -> . % 75.92/76.17 17657[26:Spt:17656.0,17648.0,17653.0] || m_main_v_state(s8,c_busy)* -> . % 75.92/76.17 17658[26:Spt:17656.0,17648.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.17 17662[26:Res:17658.0,61.1] always3(s9) || -> . % 75.92/76.17 17663[26:SSi:17662.0,698.0] || -> . % 75.92/76.17 17664[24:Spt:17663.0,16443.2,16447.0] || xuntil6(s7)*+ -> . % 75.92/76.17 17665[24:Spt:17663.0,16443.0,16443.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.17 17666[24:Res:53.1,17665.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.17 17668[25:Spt:17666.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.17 17670[25:Res:17668.0,61.1] always3(s7) || -> . % 75.92/76.17 17671[25:SSi:17670.0,696.0,16442.0] || -> . % 75.92/76.17 17672[25:Spt:17671.0,17666.0,17668.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.17 17673[25:Spt:17671.0,17666.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.17 17677[25:Res:17673.0,61.1] always3(s8) || -> . % 75.92/76.17 17678[25:SSi:17677.0,697.0] || -> . % 75.92/76.17 17679[23:Spt:17678.0,16440.2,16441.0] || xuntil6(s6)*+ -> . % 75.92/76.17 17680[23:Spt:17678.0,16440.0,16440.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.17 17681[23:Res:53.1,17680.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.17 17683[24:Spt:17681.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.17 17685[24:Res:17683.0,61.1] always3(s6) || -> . % 75.92/76.17 17686[24:SSi:17685.0,695.0,16439.0] || -> . % 75.92/76.17 17687[24:Spt:17686.0,17681.0,17683.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.17 17688[24:Spt:17686.0,17681.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.17 17692[24:Res:17688.0,61.1] always3(s7) || -> . % 75.92/76.17 17693[24:SSi:17692.0,696.0] || -> . % 75.92/76.17 17694[22:Spt:17693.0,16434.2,16438.0] || xuntil6(s5)*+ -> . % 75.92/76.17 17695[22:Spt:17693.0,16434.0,16434.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.17 17696[22:Res:53.1,17695.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.17 17701[23:Spt:17696.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.17 17703[23:Res:17701.0,61.1] always3(s5) || -> . % 75.92/76.17 17704[23:SSi:17703.0,694.0,16433.0] || -> . % 75.92/76.17 17705[23:Spt:17704.0,17696.0,17701.0] || m_main_v_state(s5,c_busy)* -> . % 75.92/76.17 17706[23:Spt:17704.0,17696.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.17 17710[23:Res:17706.0,61.1] always3(s6) || -> . % 75.92/76.17 17711[23:SSi:17710.0,695.0] || -> . % 75.92/76.17 17712[21:Spt:17711.0,16431.2,16432.0] || xuntil6(s4)*+ -> . % 75.92/76.17 17713[21:Spt:17711.0,16431.0,16431.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.17 17714[21:Res:53.1,17713.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.17 17716[22:Spt:17714.0] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.17 17718[22:Res:17716.0,61.1] always3(s4) || -> . % 75.92/76.17 17719[22:SSi:17718.0,693.0,16430.0] || -> . % 75.92/76.17 17720[22:Spt:17719.0,17714.0,17716.0] || m_main_v_state(s4,c_busy)* -> . % 75.92/76.17 17721[22:Spt:17719.0,17714.1] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.17 17725[22:Res:17721.0,61.1] always3(s5) || -> . % 75.92/76.17 17726[22:SSi:17725.0,694.0] || -> . % 75.92/76.17 17727[20:Spt:17726.0,16425.2,16429.0] || xuntil6(s3)*+ -> . % 75.92/76.17 17728[20:Spt:17726.0,16425.0,16425.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 75.92/76.17 17729[20:Res:53.1,17728.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 75.92/76.17 17731[21:Spt:17729.0] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.17 17733[21:Res:17731.0,61.1] always3(s3) || -> . % 75.92/76.17 17734[21:SSi:17733.0,692.0,16424.0] || -> . % 75.92/76.17 17735[21:Spt:17734.0,17729.0,17731.0] || m_main_v_state(s3,c_busy)* -> . % 75.92/76.17 17736[21:Spt:17734.0,17729.1] || -> m_main_v_state(s4,c_busy)*. % 75.92/76.17 17740[21:Res:17736.0,61.1] always3(s4) || -> . % 75.92/76.17 17741[21:SSi:17740.0,693.0] || -> . % 75.92/76.17 17742[19:Spt:17741.0,16422.2,16423.0] || xuntil6(s2)*+ -> . % 75.92/76.17 17743[19:Spt:17741.0,16422.0,16422.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 75.92/76.17 17744[19:Res:53.1,17743.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 75.92/76.17 17749[20:Spt:17744.0] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.17 17751[20:Res:17749.0,61.1] always3(s2) || -> . % 75.92/76.17 17752[20:SSi:17751.0,691.0,16421.0] || -> . % 75.92/76.17 17753[20:Spt:17752.0,17744.0,17749.0] || m_main_v_state(s2,c_busy)* -> . % 75.92/76.17 17754[20:Spt:17752.0,17744.1] || -> m_main_v_state(s3,c_busy)*. % 75.92/76.17 17758[20:Res:17754.0,61.1] always3(s3) || -> . % 75.92/76.17 17759[20:SSi:17758.0,692.0] || -> . % 75.92/76.17 17760[18:Spt:17759.0,16413.2,16420.0] || xuntil6(s1)*+ -> . % 75.92/76.17 17761[18:Spt:17759.0,16413.0,16413.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 75.92/76.17 17762[18:Res:53.1,17761.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 75.92/76.17 17764[19:Spt:17762.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.17 17766[19:Res:17764.0,61.1] always3(s1) || -> . % 75.92/76.17 17767[19:SSi:17766.0,690.0,16412.0] || -> . % 75.92/76.17 17768[19:Spt:17767.0,17762.0,17764.0] || m_main_v_state(s1,c_busy)* -> . % 75.92/76.17 17769[19:Spt:17767.0,17762.1] || -> m_main_v_state(s2,c_busy)*. % 75.92/76.17 17774[19:Res:17769.0,61.1] always3(s2) || -> . % 75.92/76.17 17775[19:SSi:17774.0,691.0] || -> . % 75.92/76.17 17776[17:Spt:17775.0,74.0,16411.0] || xuntil6(s0)*+ -> . % 75.92/76.17 17777[17:Spt:17775.0,74.1] || -> node4(s0)*. % 75.92/76.17 17778[17:MRR:758.1,17776.0] || -> m_main_v_state(s1,c_busy)*. % 75.92/76.17 17780[17:Res:17778.0,61.1] always3(s1) || -> . % 75.92/76.17 17781[17:SSi:17780.0,690.0] || -> . % 75.92/76.17 17782[16:Spt:17781.0,16401.0,16405.0] || trans(s49,s35)*+ -> . % 75.92/76.17 17783[16:Spt:17781.0,16401.1,16401.2,16401.3,16401.4,16401.5,16401.6,16401.7,16401.8,16401.9,16401.10,16401.11,16401.12,16401.13,16401.14,16401.15,16401.16,16401.17,16401.18,16401.19,16401.20,16401.21,16401.22,16401.23,16401.24,16401.25,16401.26,16401.27,16401.28,16401.29,16401.30,16401.31,16401.32,16401.33,16401.34,16401.35] || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 75.92/76.17 17784[16:MRR:16403.0,17782.0] || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 75.92/76.17 17786[16:MRR:16404.1,17782.0] xuntil6(s49) || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 75.92/76.17 17787[17:Spt:17783.0] || -> trans(s49,s34)*. % 75.92/76.17 17788[17:Res:17787.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s34)*. % 75.92/76.17 17790[17:Res:17787.0,60.0] || -> node2(s49,s34)*. % 75.92/76.17 17791[17:SSi:17788.1,50.0,738.0] xuntil6(s49) || -> until2p7(s34)*. % 75.92/76.17 17792[17:Res:17790.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)*. % 75.92/76.17 17793[18:Spt:74.0] || -> xuntil6(s0)*. % 75.92/76.17 17794[18:MRR:176.0,17793.0] || -> until5(s1)*. % 75.92/76.17 17795[18:MRR:16847.0,17794.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 75.92/76.17 17802[19:Spt:17795.2] || -> xuntil6(s1)*. % 75.92/76.17 17803[19:MRR:175.0,17802.0] || -> until5(s2)*. % 75.92/76.17 17804[19:MRR:16846.0,17803.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 75.92/76.17 17805[20:Spt:17804.2] || -> xuntil6(s2)*. % 75.92/76.17 17806[20:MRR:174.0,17805.0] || -> until5(s3)*. % 75.92/76.17 17807[20:MRR:16839.0,17806.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 75.92/76.17 17811[21:Spt:17807.2] || -> xuntil6(s3)*. % 75.92/76.17 17812[21:MRR:173.0,17811.0] || -> until5(s4)*. % 75.92/76.17 17813[21:MRR:16835.0,17812.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 75.92/76.17 17814[22:Spt:17813.2] || -> xuntil6(s4)*. % 75.92/76.17 17815[22:MRR:172.0,17814.0] || -> until5(s5)*. % 75.92/76.17 17816[22:MRR:16831.0,17815.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 75.92/76.17 17820[23:Spt:17816.2] || -> xuntil6(s5)*. % 75.92/76.17 17821[23:MRR:171.0,17820.0] || -> until5(s6)*. % 75.92/76.17 17822[23:MRR:16827.0,17821.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 75.92/76.17 17823[24:Spt:17822.2] || -> xuntil6(s6)*. % 75.92/76.17 17824[24:MRR:170.0,17823.0] || -> until5(s7)*. % 75.92/76.17 17825[24:MRR:16826.0,17824.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 75.92/76.17 17829[25:Spt:17825.2] || -> xuntil6(s7)*. % 75.92/76.17 17830[25:MRR:169.0,17829.0] || -> until5(s8)*. % 75.92/76.17 17831[25:MRR:16819.0,17830.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 75.92/76.17 17832[26:Spt:17831.2] || -> xuntil6(s8)*. % 75.92/76.17 17833[26:MRR:168.0,17832.0] || -> until5(s9)*. % 75.92/76.17 17834[26:MRR:16815.0,17833.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 75.92/76.17 17838[27:Spt:17834.2] || -> xuntil6(s9)*. % 75.92/76.17 17839[27:MRR:167.0,17838.0] || -> until5(s10)*. % 75.92/76.17 17840[27:MRR:16811.0,17839.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 75.92/76.17 17841[28:Spt:17840.2] || -> xuntil6(s10)*. % 75.92/76.17 17842[28:MRR:166.0,17841.0] || -> until5(s11)*. % 75.92/76.17 17843[28:MRR:16807.0,17842.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 75.92/76.17 17847[29:Spt:17843.2] || -> xuntil6(s11)*. % 75.92/76.17 17848[29:MRR:165.0,17847.0] || -> until5(s12)*. % 75.92/76.17 17849[29:MRR:16806.0,17848.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 75.92/76.17 17850[30:Spt:17849.2] || -> xuntil6(s12)*. % 75.92/76.17 17851[30:MRR:164.0,17850.0] || -> until5(s13)*. % 75.92/76.17 17852[30:MRR:16799.0,17851.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 75.92/76.17 17856[31:Spt:17852.2] || -> xuntil6(s13)*. % 75.92/76.17 17857[31:MRR:163.0,17856.0] || -> until5(s14)*. % 75.92/76.17 17858[31:MRR:16795.0,17857.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 75.92/76.17 17859[32:Spt:17858.2] || -> xuntil6(s14)*. % 75.92/76.17 17860[32:MRR:162.0,17859.0] || -> until5(s15)*. % 75.92/76.17 17861[32:MRR:16791.0,17860.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 75.92/76.17 17865[33:Spt:17861.2] || -> xuntil6(s15)*. % 75.92/76.17 17866[33:MRR:161.0,17865.0] || -> until5(s16)*. % 75.92/76.17 17867[33:MRR:16787.0,17866.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 75.92/76.17 17868[34:Spt:17867.2] || -> xuntil6(s16)*. % 75.92/76.17 17869[34:MRR:160.0,17868.0] || -> until5(s17)*. % 75.92/76.17 17870[34:MRR:16786.0,17869.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 75.92/76.17 17874[35:Spt:17870.2] || -> xuntil6(s17)*. % 75.92/76.17 17875[35:MRR:159.0,17874.0] || -> until5(s18)*. % 75.92/76.17 17876[35:MRR:16779.0,17875.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 75.92/76.17 17877[36:Spt:17876.2] || -> xuntil6(s18)*. % 75.92/76.17 17878[36:MRR:158.0,17877.0] || -> until5(s19)*. % 75.92/76.17 17879[36:MRR:16775.0,17878.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 75.92/76.17 17883[37:Spt:17879.2] || -> xuntil6(s19)*. % 75.92/76.17 17884[37:MRR:157.0,17883.0] || -> until5(s20)*. % 75.92/76.17 17885[37:MRR:16771.0,17884.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 75.92/76.17 17886[38:Spt:17885.2] || -> xuntil6(s20)*. % 75.92/76.17 17887[38:MRR:156.0,17886.0] || -> until5(s21)*. % 75.92/76.17 17888[38:MRR:16767.0,17887.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 75.92/76.17 17892[39:Spt:17888.2] || -> xuntil6(s21)*. % 75.92/76.17 17893[39:MRR:155.0,17892.0] || -> until5(s22)*. % 75.92/76.17 17894[39:MRR:16766.0,17893.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 75.92/76.17 17895[40:Spt:17894.2] || -> xuntil6(s22)*. % 75.92/76.17 17896[40:MRR:154.0,17895.0] || -> until5(s23)*. % 75.92/76.17 17897[40:MRR:16759.0,17896.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 75.92/76.17 17901[41:Spt:17897.2] || -> xuntil6(s23)*. % 75.92/76.17 17902[41:MRR:153.0,17901.0] || -> until5(s24)*. % 75.92/76.17 17903[41:MRR:16755.0,17902.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 75.92/76.17 17904[42:Spt:17903.2] || -> xuntil6(s24)*. % 75.92/76.17 17905[42:MRR:152.0,17904.0] || -> until5(s25)*. % 75.92/76.17 17906[42:MRR:16751.0,17905.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 75.92/76.17 17910[43:Spt:17906.2] || -> xuntil6(s25)*. % 75.92/76.17 17911[43:MRR:151.0,17910.0] || -> until5(s26)*. % 75.92/76.17 17912[43:MRR:16747.0,17911.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 75.92/76.17 17913[44:Spt:17912.2] || -> xuntil6(s26)*. % 75.92/76.17 17914[44:MRR:150.0,17913.0] || -> until5(s27)*. % 75.92/76.17 17915[44:MRR:16746.0,17914.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 75.92/76.17 17919[45:Spt:17915.1] || -> m_main_v_state(s28,c_busy)*. % 75.92/76.17 17921[45:Res:17919.0,61.1] always3(s28) || -> . % 75.92/76.17 17922[45:SSi:17921.0,717.0] || -> . % 75.92/76.17 17923[45:Spt:17922.0,17915.1,17919.0] || m_main_v_state(s28,c_busy)*+ -> . % 75.92/76.17 17924[45:Spt:17922.0,17915.0,17915.2] || m_main_v_state(s27,c_ready)*+ -> xuntil6(s27). % 75.92/76.17 17927[45:Res:53.1,17924.0] || -> m_main_v_state(s27,c_busy)* xuntil6(s27). % 75.92/76.17 17929[46:Spt:17927.1] || -> xuntil6(s27)*. % 75.92/76.17 17930[46:MRR:149.0,17929.0] || -> until5(s28)*. % 75.92/76.17 17931[46:MRR:16739.0,17930.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 75.92/76.17 17936[47:Spt:17931.2] || -> xuntil6(s28)*. % 75.92/76.17 17937[47:MRR:148.0,17936.0] || -> until5(s29)*. % 75.92/76.17 17938[47:MRR:16738.0,17937.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 75.92/76.17 17939[48:Spt:17938.1] || -> m_main_v_state(s30,c_busy)*. % 75.92/76.17 17941[48:Res:17939.0,61.1] always3(s30) || -> . % 75.92/76.17 17942[48:SSi:17941.0,719.0] || -> . % 75.92/76.17 17943[48:Spt:17942.0,17938.1,17939.0] || m_main_v_state(s30,c_busy)*+ -> . % 75.92/76.17 17944[48:Spt:17942.0,17938.0,17938.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 75.92/76.17 17947[48:Res:53.1,17944.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 75.92/76.17 17949[49:Spt:17947.1] || -> xuntil6(s29)*. % 75.92/76.17 17950[49:MRR:147.0,17949.0] || -> until5(s30)*. % 75.92/76.17 17951[49:MRR:16737.0,17950.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 75.92/76.17 17959[50:Spt:17951.2] || -> xuntil6(s30)*. % 75.92/76.17 17960[50:MRR:146.0,17959.0] || -> until5(s31)*. % 75.92/76.17 17961[50:MRR:16733.0,17960.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 75.92/76.17 17962[51:Spt:17961.1] || -> m_main_v_state(s32,c_busy)*. % 75.92/76.17 17964[51:Res:17962.0,61.1] always3(s32) || -> . % 75.92/76.17 17965[51:SSi:17964.0,721.0] || -> . % 75.92/76.17 17966[51:Spt:17965.0,17961.1,17962.0] || m_main_v_state(s32,c_busy)*+ -> . % 75.92/76.17 17967[51:Spt:17965.0,17961.0,17961.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 75.92/76.17 17970[51:Res:53.1,17967.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 75.92/76.17 17975[52:Spt:17970.1] || -> xuntil6(s31)*. % 75.92/76.17 17976[52:MRR:145.0,17975.0] || -> until5(s32)*. % 75.92/76.17 17977[52:MRR:16732.0,17976.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 75.92/76.17 17979[53:Spt:17977.2] || -> xuntil6(s32)*. % 75.92/76.17 17980[53:MRR:144.0,17979.0] || -> until5(s33)*. % 75.92/76.17 17981[53:MRR:932.0,17980.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 75.92/76.17 17982[54:Spt:17981.1] || -> m_main_v_state(s34,c_busy)*. % 75.92/76.17 17984[54:Res:17982.0,61.1] always3(s34) || -> . % 75.92/76.17 17985[54:SSi:17984.0,723.0] || -> . % 75.92/76.17 17986[54:Spt:17985.0,17981.1,17982.0] || m_main_v_state(s34,c_busy)*+ -> . % 75.92/76.17 17987[54:Spt:17985.0,17981.0,17981.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 75.92/76.17 17990[54:MRR:17792.2,17986.0] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.17 17991[54:Res:53.1,17987.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 75.92/76.17 17993[55:Spt:17991.1] || -> xuntil6(s33)*. % 75.92/76.17 17994[55:MRR:143.0,17993.0] || -> until5(s34)*. % 75.92/76.17 17995[55:MRR:16857.0,17994.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 75.92/76.17 18001[54:SoR:17990.0,64.1] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 75.92/76.17 18003[54:SoR:18001.0,66.2] until5(s49) || m_main_v_state(s49,c_ready)* -> xuntil6(s49). % 75.92/76.17 18004[56:Spt:17995.2] || -> xuntil6(s34)*. % 75.92/76.17 18005[56:MRR:142.0,18004.0] || -> until5(s35)*. % 75.92/76.17 18006[56:MRR:930.0,18005.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 75.92/76.17 18007[57:Spt:18006.1] || -> m_main_v_state(s36,c_busy)*. % 75.92/76.17 18009[57:Res:18007.0,61.1] always3(s36) || -> . % 75.92/76.17 18010[57:SSi:18009.0,725.0] || -> . % 75.92/76.17 18011[57:Spt:18010.0,18006.1,18007.0] || m_main_v_state(s36,c_busy)*+ -> . % 75.92/76.17 18012[57:Spt:18010.0,18006.0,18006.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 75.92/76.17 18014[57:MRR:813.2,18011.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 75.92/76.17 18015[57:Res:53.1,18012.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 75.92/76.17 18017[58:Spt:18015.1] || -> xuntil6(s35)*. % 75.92/76.17 18018[58:MRR:141.0,18017.0] || -> until5(s36)*. % 75.92/76.17 18019[58:MRR:16858.0,18018.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 75.92/76.17 18024[59:Spt:18019.2] || -> xuntil6(s36)*. % 75.92/76.17 18025[59:MRR:140.0,18024.0] || -> until5(s37)*. % 75.92/76.17 18026[59:MRR:928.0,18025.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 75.92/76.17 18030[60:Spt:18026.1] || -> m_main_v_state(s38,c_busy)*. % 75.92/76.17 18032[60:Res:18030.0,61.1] always3(s38) || -> . % 75.92/76.17 18033[60:SSi:18032.0,727.0] || -> . % 75.92/76.17 18034[60:Spt:18033.0,18026.1,18030.0] || m_main_v_state(s38,c_busy)*+ -> . % 75.92/76.17 18035[60:Spt:18033.0,18026.0,18026.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 75.92/76.17 18037[60:MRR:807.2,18034.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 75.92/76.17 18038[60:Res:53.1,18035.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 75.92/76.17 18040[61:Spt:18038.1] || -> xuntil6(s37)*. % 75.92/76.17 18041[61:MRR:139.0,18040.0] || -> until5(s38)*. % 75.92/76.17 18042[61:MRR:16862.0,18041.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 75.92/76.17 18047[62:Spt:18042.2] || -> xuntil6(s38)*. % 75.92/76.17 18048[62:MRR:138.0,18047.0] || -> until5(s39)*. % 75.92/76.17 18049[62:MRR:926.0,18048.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 75.92/76.17 18050[63:Spt:18049.1] || -> m_main_v_state(s40,c_busy)*. % 75.92/76.17 18052[63:Res:18050.0,61.1] always3(s40) || -> . % 75.92/76.17 18053[63:SSi:18052.0,729.0] || -> . % 75.92/76.17 18054[63:Spt:18053.0,18049.1,18050.0] || m_main_v_state(s40,c_busy)*+ -> . % 75.92/76.17 18055[63:Spt:18053.0,18049.0,18049.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 75.92/76.17 18057[63:MRR:801.2,18054.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 75.92/76.17 18058[63:Res:53.1,18055.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 75.92/76.17 18060[64:Spt:18058.1] || -> xuntil6(s39)*. % 75.92/76.17 18061[64:MRR:137.0,18060.0] || -> until5(s40)*. % 75.92/76.17 18062[64:MRR:16866.0,18061.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 75.92/76.17 18070[65:Spt:18062.2] || -> xuntil6(s40)*. % 75.92/76.17 18071[65:MRR:136.0,18070.0] || -> until5(s41)*. % 75.92/76.17 18072[65:MRR:924.0,18071.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 75.92/76.17 18073[66:Spt:18072.1] || -> m_main_v_state(s42,c_busy)*. % 75.92/76.17 18075[66:Res:18073.0,61.1] always3(s42) || -> . % 75.92/76.17 18076[66:SSi:18075.0,731.0] || -> . % 75.92/76.17 18077[66:Spt:18076.0,18072.1,18073.0] || m_main_v_state(s42,c_busy)*+ -> . % 75.92/76.17 18078[66:Spt:18076.0,18072.0,18072.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 75.92/76.17 18080[66:MRR:795.2,18077.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 75.92/76.17 18081[66:Res:53.1,18078.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 75.92/76.17 18086[67:Spt:18081.1] || -> xuntil6(s41)*. % 75.92/76.17 18087[67:MRR:135.0,18086.0] || -> until5(s42)*. % 75.92/76.17 18088[67:MRR:16870.0,18087.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 75.92/76.17 18090[68:Spt:18088.2] || -> xuntil6(s42)*. % 75.92/76.17 18091[68:MRR:134.0,18090.0] || -> until5(s43)*. % 75.92/76.17 18092[68:MRR:922.0,18091.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 75.92/76.17 18093[69:Spt:18092.1] || -> m_main_v_state(s44,c_busy)*. % 75.92/76.17 18095[69:Res:18093.0,61.1] always3(s44) || -> . % 75.92/76.17 18096[69:SSi:18095.0,733.0] || -> . % 75.92/76.17 18097[69:Spt:18096.0,18092.1,18093.0] || m_main_v_state(s44,c_busy)*+ -> . % 75.92/76.17 18098[69:Spt:18096.0,18092.0,18092.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 75.92/76.17 18100[69:MRR:789.2,18097.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 75.92/76.17 18101[69:Res:53.1,18098.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 75.92/76.17 18103[70:Spt:18101.1] || -> xuntil6(s43)*. % 75.92/76.17 18104[70:MRR:133.0,18103.0] || -> until5(s44)*. % 75.92/76.17 18105[70:MRR:16877.0,18104.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 75.92/76.17 18110[71:Spt:18105.2] || -> xuntil6(s44)*. % 75.92/76.17 18111[71:MRR:132.0,18110.0] || -> until5(s45)*. % 75.92/76.17 18112[71:MRR:920.0,18111.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 75.92/76.17 18113[72:Spt:18112.1] || -> m_main_v_state(s46,c_busy)*. % 75.92/76.17 18115[72:Res:18113.0,61.1] always3(s46) || -> . % 75.92/76.17 18116[72:SSi:18115.0,735.0] || -> . % 75.92/76.17 18117[72:Spt:18116.0,18112.1,18113.0] || m_main_v_state(s46,c_busy)*+ -> . % 75.92/76.17 18118[72:Spt:18116.0,18112.0,18112.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 75.92/76.17 18120[72:MRR:783.2,18117.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 75.92/76.17 18121[72:Res:53.1,18118.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 75.92/76.17 18123[73:Spt:18121.1] || -> xuntil6(s45)*. % 75.92/76.17 18124[73:MRR:131.0,18123.0] || -> until5(s46)*. % 75.92/76.17 18125[73:MRR:16878.0,18124.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 75.92/76.17 18133[74:Spt:18125.2] || -> xuntil6(s46)*. % 75.92/76.17 18134[74:MRR:130.0,18133.0] || -> until5(s47)*. % 75.92/76.17 18135[74:MRR:918.0,18134.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 75.92/76.17 18136[75:Spt:18135.1] || -> m_main_v_state(s48,c_busy)*. % 75.92/76.17 18138[75:Res:18136.0,61.1] always3(s48) || -> . % 75.92/76.17 18139[75:SSi:18138.0,737.0] || -> . % 75.92/76.17 18140[75:Spt:18139.0,18135.1,18136.0] || m_main_v_state(s48,c_busy)*+ -> . % 75.92/76.17 18141[75:Spt:18139.0,18135.0,18135.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 75.92/76.17 18143[75:MRR:777.2,18140.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 75.92/76.17 18144[75:Res:53.1,18141.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 75.92/76.17 18149[76:Spt:18144.1] || -> xuntil6(s47)*. % 75.92/76.17 18150[76:MRR:129.0,18149.0] || -> until5(s48)*. % 75.92/76.17 18151[76:MRR:16882.0,18150.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 75.92/76.17 18153[77:Spt:18151.2] || -> xuntil6(s48)*. % 75.92/76.17 18154[77:MRR:128.0,18153.0] || -> until5(s49)*. % 75.92/76.17 18155[77:MRR:18003.0,18154.0] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 75.92/76.17 18156[77:Res:53.1,18155.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 75.92/76.17 18158[78:Spt:18156.1] || -> xuntil6(s49)*. % 75.92/76.17 18159[78:MRR:17791.0,18158.0] || -> until2p7(s34)*. % 75.92/76.17 18160[78:MRR:230.0,18159.0] || -> until2p7(s35)* node4(s34). % 75.92/76.17 18161[79:Spt:18160.0] || -> until2p7(s35)*. % 75.92/76.17 18162[79:MRR:231.0,18161.0] || -> until2p7(s36)* node4(s35). % 75.92/76.17 18163[80:Spt:18162.0] || -> until2p7(s36)*. % 75.92/76.17 18164[80:MRR:232.0,18163.0] || -> until2p7(s37)* node4(s36). % 75.92/76.17 18165[81:Spt:18164.0] || -> until2p7(s37)*. % 75.92/76.17 18166[81:MRR:235.0,18165.0] || -> until2p7(s38)* node4(s37). % 75.92/76.17 18167[82:Spt:18166.0] || -> until2p7(s38)*. % 75.92/76.17 18168[82:MRR:236.0,18167.0] || -> until2p7(s39)* node4(s38). % 75.92/76.17 18169[83:Spt:18168.0] || -> until2p7(s39)*. % 75.92/76.17 18170[83:MRR:237.0,18169.0] || -> until2p7(s40)* node4(s39). % 75.92/76.17 18171[84:Spt:18170.0] || -> until2p7(s40)*. % 75.92/76.17 18172[84:MRR:238.0,18171.0] || -> until2p7(s41)* node4(s40). % 75.92/76.17 18173[85:Spt:18172.0] || -> until2p7(s41)*. % 75.92/76.17 18174[85:MRR:239.0,18173.0] || -> until2p7(s42)* node4(s41). % 75.92/76.17 18175[86:Spt:18174.0] || -> until2p7(s42)*. % 75.92/76.17 18176[86:MRR:240.0,18175.0] || -> until2p7(s43)* node4(s42). % 75.92/76.17 18177[87:Spt:18176.0] || -> until2p7(s43)*. % 75.92/76.17 18178[87:MRR:241.0,18177.0] || -> until2p7(s44)* node4(s43). % 75.92/76.17 18179[88:Spt:18178.0] || -> until2p7(s44)*. % 75.92/76.17 18180[88:MRR:539.0,18179.0] || -> until2p7(s45)* node4(s44). % 75.92/76.17 18181[89:Spt:18180.0] || -> until2p7(s45)*. % 75.92/76.17 18182[89:MRR:544.0,18181.0] || -> until2p7(s46)* node4(s45). % 75.92/76.17 18183[90:Spt:18182.0] || -> until2p7(s46)*. % 75.92/76.17 18184[90:MRR:549.0,18183.0] || -> until2p7(s47)* node4(s46). % 75.92/76.17 18185[91:Spt:18184.0] || -> until2p7(s47)*. % 75.92/76.17 18186[91:MRR:554.0,18185.0] || -> until2p7(s48)* node4(s47). % 75.92/76.17 18187[92:Spt:18186.0] || -> until2p7(s48)*. % 75.92/76.17 18188[92:MRR:559.0,18187.0] || -> until2p7(s49)* node4(s48). % 75.92/76.17 18189[93:Spt:18188.0] || -> until2p7(s49)*. % 75.92/76.17 18190[93:MRR:194.0,18189.0] || -> node4(s49)*. % 75.92/76.17 18191[93:MRR:18001.0,18190.0] || m_main_v_state(s49,c_ready)*+ -> . % 75.92/76.17 18195[93:Res:53.1,18191.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.17 18198[93:Res:18195.0,61.1] always3(s49) || -> . % 75.92/76.17 18199[93:SSi:18198.0,50.0,738.0,18154.0,18158.0,18189.0,18190.0] || -> . % 75.92/76.17 18200[93:Spt:18199.0,18188.0,18189.0] || until2p7(s49)*+ -> . % 75.92/76.17 18201[93:Spt:18199.0,18188.1] || -> node4(s48)*. % 75.92/76.17 18203[93:MRR:774.0,18201.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.17 18209[93:Res:53.1,18203.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.17 18211[93:MRR:18209.0,18140.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.17 18213[93:Res:18211.0,61.1] always3(s49) || -> . % 75.92/76.17 18214[93:SSi:18213.0,50.0,738.0,18154.0,18158.0] || -> . % 75.92/76.17 18215[92:Spt:18214.0,18186.0,18187.0] || until2p7(s48)*+ -> . % 75.92/76.17 18216[92:Spt:18214.0,18186.1] || -> node4(s47)*. % 75.92/76.17 18217[92:MRR:18143.0,18216.0] || m_main_v_state(s47,c_ready)*+ -> . % 75.92/76.17 18220[92:Res:53.1,18217.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.17 18223[92:Res:18220.0,61.1] always3(s47) || -> . % 75.92/76.17 18224[92:SSi:18223.0,736.0,18134.0,18149.0,18185.0,18216.0] || -> . % 75.92/76.17 18225[91:Spt:18224.0,18184.0,18185.0] || until2p7(s47)*+ -> . % 75.92/76.17 18226[91:Spt:18224.0,18184.1] || -> node4(s46)*. % 75.92/76.17 18228[91:MRR:780.0,18226.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.17 18240[91:Res:53.1,18228.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.17 18242[91:MRR:18240.0,18117.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.17 18247[91:Res:18242.0,61.1] always3(s47) || -> . % 75.92/76.17 18248[91:SSi:18247.0,736.0,18134.0,18149.0] || -> . % 75.92/76.17 18249[90:Spt:18248.0,18182.0,18183.0] || until2p7(s46)*+ -> . % 75.92/76.17 18250[90:Spt:18248.0,18182.1] || -> node4(s45)*. % 75.92/76.17 18251[90:MRR:18120.0,18250.0] || m_main_v_state(s45,c_ready)*+ -> . % 75.92/76.17 18254[90:Res:53.1,18251.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.17 18258[90:Res:18254.0,61.1] always3(s45) || -> . % 75.92/76.17 18259[90:SSi:18258.0,734.0,18111.0,18123.0,18181.0,18250.0] || -> . % 75.92/76.17 18260[89:Spt:18259.0,18180.0,18181.0] || until2p7(s45)*+ -> . % 75.92/76.17 18261[89:Spt:18259.0,18180.1] || -> node4(s44)*. % 75.92/76.17 18263[89:MRR:786.0,18261.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.17 18274[89:Res:53.1,18263.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.17 18276[89:MRR:18274.0,18097.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.17 18278[89:Res:18276.0,61.1] always3(s45) || -> . % 75.92/76.17 18279[89:SSi:18278.0,734.0,18111.0,18123.0] || -> . % 75.92/76.17 18280[88:Spt:18279.0,18178.0,18179.0] || until2p7(s44)*+ -> . % 75.92/76.17 18281[88:Spt:18279.0,18178.1] || -> node4(s43)*. % 75.92/76.17 18282[88:MRR:18100.0,18281.0] || m_main_v_state(s43,c_ready)*+ -> . % 75.92/76.17 18286[88:Res:53.1,18282.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.17 18289[88:Res:18286.0,61.1] always3(s43) || -> . % 75.92/76.17 18290[88:SSi:18289.0,732.0,18091.0,18103.0,18177.0,18281.0] || -> . % 75.92/76.17 18291[87:Spt:18290.0,18176.0,18177.0] || until2p7(s43)*+ -> . % 75.92/76.17 18292[87:Spt:18290.0,18176.1] || -> node4(s42)*. % 75.92/76.17 18294[87:MRR:792.0,18292.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.17 18305[87:Res:53.1,18294.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.17 18307[87:MRR:18305.0,18077.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.17 18309[87:Res:18307.0,61.1] always3(s43) || -> . % 75.92/76.17 18310[87:SSi:18309.0,732.0,18091.0,18103.0] || -> . % 75.92/76.17 18311[86:Spt:18310.0,18174.0,18175.0] || until2p7(s42)*+ -> . % 75.92/76.17 18312[86:Spt:18310.0,18174.1] || -> node4(s41)*. % 75.92/76.17 18313[86:MRR:18080.0,18312.0] || m_main_v_state(s41,c_ready)*+ -> . % 75.92/76.17 18316[86:Res:53.1,18313.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.17 18319[86:Res:18316.0,61.1] always3(s41) || -> . % 75.92/76.17 18320[86:SSi:18319.0,730.0,18071.0,18086.0,18173.0,18312.0] || -> . % 75.92/76.17 18321[85:Spt:18320.0,18172.0,18173.0] || until2p7(s41)*+ -> . % 75.92/76.17 18322[85:Spt:18320.0,18172.1] || -> node4(s40)*. % 75.92/76.17 18324[85:MRR:798.0,18322.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.17 18336[85:Res:53.1,18324.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.17 18338[85:MRR:18336.0,18054.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.17 18340[85:Res:18338.0,61.1] always3(s41) || -> . % 75.92/76.17 18341[85:SSi:18340.0,730.0,18071.0,18086.0] || -> . % 75.92/76.17 18342[84:Spt:18341.0,18170.0,18171.0] || until2p7(s40)*+ -> . % 75.92/76.17 18343[84:Spt:18341.0,18170.1] || -> node4(s39)*. % 75.92/76.17 18344[84:MRR:18057.0,18343.0] || m_main_v_state(s39,c_ready)*+ -> . % 75.92/76.17 18347[84:Res:53.1,18344.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.17 18350[84:Res:18347.0,61.1] always3(s39) || -> . % 75.92/76.17 18351[84:SSi:18350.0,728.0,18048.0,18060.0,18169.0,18343.0] || -> . % 75.92/76.17 18352[83:Spt:18351.0,18168.0,18169.0] || until2p7(s39)*+ -> . % 75.92/76.17 18353[83:Spt:18351.0,18168.1] || -> node4(s38)*. % 75.92/76.17 18355[83:MRR:804.0,18353.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.17 18367[83:Res:53.1,18355.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.17 18369[83:MRR:18367.0,18034.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.17 18374[83:Res:18369.0,61.1] always3(s39) || -> . % 75.92/76.17 18375[83:SSi:18374.0,728.0,18048.0,18060.0] || -> . % 75.92/76.17 18376[82:Spt:18375.0,18166.0,18167.0] || until2p7(s38)*+ -> . % 75.92/76.17 18377[82:Spt:18375.0,18166.1] || -> node4(s37)*. % 75.92/76.17 18378[82:MRR:18037.0,18377.0] || m_main_v_state(s37,c_ready)*+ -> . % 75.92/76.17 18381[82:Res:53.1,18378.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.17 18385[82:Res:18381.0,61.1] always3(s37) || -> . % 75.92/76.17 18386[82:SSi:18385.0,726.0,18025.0,18040.0,18165.0,18377.0] || -> . % 75.92/76.17 18387[81:Spt:18386.0,18164.0,18165.0] || until2p7(s37)*+ -> . % 75.92/76.17 18388[81:Spt:18386.0,18164.1] || -> node4(s36)*. % 75.92/76.17 18390[81:MRR:810.0,18388.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.17 18401[81:Res:53.1,18390.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.17 18403[81:MRR:18401.0,18011.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.17 18405[81:Res:18403.0,61.1] always3(s37) || -> . % 75.92/76.17 18406[81:SSi:18405.0,726.0,18025.0,18040.0] || -> . % 75.92/76.17 18407[80:Spt:18406.0,18162.0,18163.0] || until2p7(s36)*+ -> . % 75.92/76.17 18408[80:Spt:18406.0,18162.1] || -> node4(s35)*. % 75.92/76.17 18409[80:MRR:18014.0,18408.0] || m_main_v_state(s35,c_ready)*+ -> . % 75.92/76.17 18413[80:Res:53.1,18409.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.17 18416[80:Res:18413.0,61.1] always3(s35) || -> . % 75.92/76.17 18417[80:SSi:18416.0,724.0,18005.0,18017.0,18161.0,18408.0] || -> . % 75.92/76.17 18418[79:Spt:18417.0,18160.0,18161.0] || until2p7(s35)*+ -> . % 75.92/76.17 18419[79:Spt:18417.0,18160.1] || -> node4(s34)*. % 75.92/76.17 18421[79:MRR:816.0,18419.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 75.92/76.17 18432[79:Res:53.1,18421.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 75.92/76.17 18434[79:MRR:18432.0,17986.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.17 18436[79:Res:18434.0,61.1] always3(s35) || -> . % 75.92/76.17 18437[79:SSi:18436.0,724.0,18005.0,18017.0] || -> . % 75.92/76.17 18438[78:Spt:18437.0,18156.1,18158.0] || xuntil6(s49)* -> . % 75.92/76.17 18439[78:Spt:18437.0,18156.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.17 18442[78:Res:18439.0,61.1] always3(s49) || -> . % 75.92/76.17 18443[78:SSi:18442.0,50.0,738.0,18154.0] || -> . % 75.92/76.17 18444[77:Spt:18443.0,18151.2,18153.0] || xuntil6(s48)*+ -> . % 75.92/76.17 18445[77:Spt:18443.0,18151.0,18151.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 75.92/76.17 18446[77:Res:53.1,18445.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 75.92/76.17 18448[77:MRR:18446.0,18140.0] || -> m_main_v_state(s49,c_busy)*. % 75.92/76.17 18451[77:Res:18448.0,61.1] always3(s49) || -> . % 75.92/76.17 18452[77:SSi:18451.0,50.0,738.0] || -> . % 75.92/76.17 18453[76:Spt:18452.0,18144.1,18149.0] || xuntil6(s47)* -> . % 75.92/76.17 18454[76:Spt:18452.0,18144.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.17 18457[76:Res:18454.0,61.1] always3(s47) || -> . % 75.92/76.17 18458[76:SSi:18457.0,736.0,18134.0] || -> . % 75.92/76.17 18459[74:Spt:18458.0,18125.2,18133.0] || xuntil6(s46)*+ -> . % 75.92/76.17 18460[74:Spt:18458.0,18125.0,18125.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 75.92/76.17 18461[74:Res:53.1,18460.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 75.92/76.17 18463[74:MRR:18461.0,18117.0] || -> m_main_v_state(s47,c_busy)*. % 75.92/76.17 18465[74:Res:18463.0,61.1] always3(s47) || -> . % 75.92/76.17 18466[74:SSi:18465.0,736.0] || -> . % 75.92/76.17 18467[73:Spt:18466.0,18121.1,18123.0] || xuntil6(s45)* -> . % 75.92/76.17 18468[73:Spt:18466.0,18121.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.17 18471[73:Res:18468.0,61.1] always3(s45) || -> . % 75.92/76.17 18472[73:SSi:18471.0,734.0,18111.0] || -> . % 75.92/76.17 18473[71:Spt:18472.0,18105.2,18110.0] || xuntil6(s44)*+ -> . % 75.92/76.17 18474[71:Spt:18472.0,18105.0,18105.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 75.92/76.17 18475[71:Res:53.1,18474.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 75.92/76.17 18477[71:MRR:18475.0,18097.0] || -> m_main_v_state(s45,c_busy)*. % 75.92/76.17 18480[71:Res:18477.0,61.1] always3(s45) || -> . % 75.92/76.17 18481[71:SSi:18480.0,734.0] || -> . % 75.92/76.17 18482[70:Spt:18481.0,18101.1,18103.0] || xuntil6(s43)* -> . % 75.92/76.17 18483[70:Spt:18481.0,18101.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.17 18486[70:Res:18483.0,61.1] always3(s43) || -> . % 75.92/76.17 18487[70:SSi:18486.0,732.0,18091.0] || -> . % 75.92/76.17 18488[68:Spt:18487.0,18088.2,18090.0] || xuntil6(s42)*+ -> . % 75.92/76.17 18489[68:Spt:18487.0,18088.0,18088.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 75.92/76.17 18490[68:Res:53.1,18489.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 75.92/76.17 18492[68:MRR:18490.0,18077.0] || -> m_main_v_state(s43,c_busy)*. % 75.92/76.17 18494[68:Res:18492.0,61.1] always3(s43) || -> . % 75.92/76.17 18495[68:SSi:18494.0,732.0] || -> . % 75.92/76.17 18496[67:Spt:18495.0,18081.1,18086.0] || xuntil6(s41)* -> . % 75.92/76.17 18497[67:Spt:18495.0,18081.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.17 18500[67:Res:18497.0,61.1] always3(s41) || -> . % 75.92/76.17 18501[67:SSi:18500.0,730.0,18071.0] || -> . % 75.92/76.17 18502[65:Spt:18501.0,18062.2,18070.0] || xuntil6(s40)*+ -> . % 75.92/76.17 18503[65:Spt:18501.0,18062.0,18062.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 75.92/76.17 18504[65:Res:53.1,18503.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 75.92/76.17 18506[65:MRR:18504.0,18054.0] || -> m_main_v_state(s41,c_busy)*. % 75.92/76.17 18508[65:Res:18506.0,61.1] always3(s41) || -> . % 75.92/76.17 18509[65:SSi:18508.0,730.0] || -> . % 75.92/76.17 18510[64:Spt:18509.0,18058.1,18060.0] || xuntil6(s39)* -> . % 75.92/76.17 18511[64:Spt:18509.0,18058.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.17 18514[64:Res:18511.0,61.1] always3(s39) || -> . % 75.92/76.17 18515[64:SSi:18514.0,728.0,18048.0] || -> . % 75.92/76.17 18516[62:Spt:18515.0,18042.2,18047.0] || xuntil6(s38)*+ -> . % 75.92/76.17 18517[62:Spt:18515.0,18042.0,18042.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 75.92/76.17 18518[62:Res:53.1,18517.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 75.92/76.17 18520[62:MRR:18518.0,18034.0] || -> m_main_v_state(s39,c_busy)*. % 75.92/76.17 18522[62:Res:18520.0,61.1] always3(s39) || -> . % 75.92/76.17 18523[62:SSi:18522.0,728.0] || -> . % 75.92/76.17 18524[61:Spt:18523.0,18038.1,18040.0] || xuntil6(s37)* -> . % 75.92/76.17 18525[61:Spt:18523.0,18038.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.17 18528[61:Res:18525.0,61.1] always3(s37) || -> . % 75.92/76.17 18529[61:SSi:18528.0,726.0,18025.0] || -> . % 75.92/76.17 18530[59:Spt:18529.0,18019.2,18024.0] || xuntil6(s36)*+ -> . % 75.92/76.17 18531[59:Spt:18529.0,18019.0,18019.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 75.92/76.17 18532[59:Res:53.1,18531.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 75.92/76.17 18534[59:MRR:18532.0,18011.0] || -> m_main_v_state(s37,c_busy)*. % 75.92/76.17 18536[59:Res:18534.0,61.1] always3(s37) || -> . % 75.92/76.17 18537[59:SSi:18536.0,726.0] || -> . % 75.92/76.17 18538[58:Spt:18537.0,18015.1,18017.0] || xuntil6(s35)* -> . % 75.92/76.17 18539[58:Spt:18537.0,18015.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.17 18542[58:Res:18539.0,61.1] always3(s35) || -> . % 75.92/76.17 18543[58:SSi:18542.0,724.0,18005.0] || -> . % 75.92/76.17 18544[56:Spt:18543.0,17995.2,18004.0] || xuntil6(s34)*+ -> . % 75.92/76.17 18545[56:Spt:18543.0,17995.0,17995.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 75.92/76.17 18546[56:Res:53.1,18545.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 75.92/76.17 18548[56:MRR:18546.0,17986.0] || -> m_main_v_state(s35,c_busy)*. % 75.92/76.17 18550[56:Res:18548.0,61.1] always3(s35) || -> . % 75.92/76.17 18551[56:SSi:18550.0,724.0] || -> . % 75.92/76.17 18552[55:Spt:18551.0,17991.1,17993.0] || xuntil6(s33)* -> . % 75.92/76.17 18553[55:Spt:18551.0,17991.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.17 18556[55:Res:18553.0,61.1] always3(s33) || -> . % 75.92/76.17 18557[55:SSi:18556.0,722.0,17980.0] || -> . % 75.92/76.17 18558[53:Spt:18557.0,17977.2,17979.0] || xuntil6(s32)*+ -> . % 75.92/76.17 18559[53:Spt:18557.0,17977.0,17977.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 75.92/76.17 18560[53:Res:53.1,18559.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 75.92/76.17 18562[53:MRR:18560.0,17966.0] || -> m_main_v_state(s33,c_busy)*. % 75.92/76.17 18564[53:Res:18562.0,61.1] always3(s33) || -> . % 75.92/76.17 18565[53:SSi:18564.0,722.0] || -> . % 75.92/76.17 18566[52:Spt:18565.0,17970.1,17975.0] || xuntil6(s31)* -> . % 75.92/76.17 18567[52:Spt:18565.0,17970.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.17 18570[52:Res:18567.0,61.1] always3(s31) || -> . % 75.92/76.17 18571[52:SSi:18570.0,720.0,17960.0] || -> . % 75.92/76.17 18572[50:Spt:18571.0,17951.2,17959.0] || xuntil6(s30)*+ -> . % 75.92/76.17 18573[50:Spt:18571.0,17951.0,17951.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 75.92/76.17 18574[50:Res:53.1,18573.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 75.92/76.17 18576[50:MRR:18574.0,17943.0] || -> m_main_v_state(s31,c_busy)*. % 75.92/76.17 18578[50:Res:18576.0,61.1] always3(s31) || -> . % 75.92/76.17 18579[50:SSi:18578.0,720.0] || -> . % 75.92/76.17 18580[49:Spt:18579.0,17947.1,17949.0] || xuntil6(s29)* -> . % 75.92/76.17 18581[49:Spt:18579.0,17947.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.17 18584[49:Res:18581.0,61.1] always3(s29) || -> . % 75.92/76.17 18585[49:SSi:18584.0,718.0,17937.0] || -> . % 75.92/76.17 18586[47:Spt:18585.0,17931.2,17936.0] || xuntil6(s28)*+ -> . % 75.92/76.17 18587[47:Spt:18585.0,17931.0,17931.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 75.92/76.17 18588[47:Res:53.1,18587.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 75.92/76.17 18590[47:MRR:18588.0,17923.0] || -> m_main_v_state(s29,c_busy)*. % 75.92/76.17 18592[47:Res:18590.0,61.1] always3(s29) || -> . % 75.92/76.17 18593[47:SSi:18592.0,718.0] || -> . % 75.92/76.17 18594[46:Spt:18593.0,17927.1,17929.0] || xuntil6(s27)* -> . % 75.92/76.17 18595[46:Spt:18593.0,17927.0] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.17 18598[46:Res:18595.0,61.1] always3(s27) || -> . % 75.92/76.17 18599[46:SSi:18598.0,716.0,17914.0] || -> . % 75.92/76.17 18600[44:Spt:18599.0,17912.2,17913.0] || xuntil6(s26)*+ -> . % 75.92/76.17 18601[44:Spt:18599.0,17912.0,17912.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 75.92/76.17 18602[44:Res:53.1,18601.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 75.92/76.17 18604[45:Spt:18602.0] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.17 18606[45:Res:18604.0,61.1] always3(s26) || -> . % 75.92/76.17 18607[45:SSi:18606.0,715.0,17911.0] || -> . % 75.92/76.17 18608[45:Spt:18607.0,18602.0,18604.0] || m_main_v_state(s26,c_busy)* -> . % 75.92/76.17 18609[45:Spt:18607.0,18602.1] || -> m_main_v_state(s27,c_busy)*. % 75.92/76.17 18613[45:Res:18609.0,61.1] always3(s27) || -> . % 75.92/76.17 18614[45:SSi:18613.0,716.0] || -> . % 75.92/76.17 18615[43:Spt:18614.0,17906.2,17910.0] || xuntil6(s25)*+ -> . % 75.92/76.17 18616[43:Spt:18614.0,17906.0,17906.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 75.92/76.17 18617[43:Res:53.1,18616.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 75.92/76.17 18619[44:Spt:18617.0] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.17 18621[44:Res:18619.0,61.1] always3(s25) || -> . % 75.92/76.17 18622[44:SSi:18621.0,714.0,17905.0] || -> . % 75.92/76.17 18623[44:Spt:18622.0,18617.0,18619.0] || m_main_v_state(s25,c_busy)* -> . % 75.92/76.17 18624[44:Spt:18622.0,18617.1] || -> m_main_v_state(s26,c_busy)*. % 75.92/76.17 18628[44:Res:18624.0,61.1] always3(s26) || -> . % 75.92/76.17 18629[44:SSi:18628.0,715.0] || -> . % 75.92/76.17 18630[42:Spt:18629.0,17903.2,17904.0] || xuntil6(s24)*+ -> . % 75.92/76.17 18631[42:Spt:18629.0,17903.0,17903.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 75.92/76.17 18632[42:Res:53.1,18631.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 75.92/76.17 18634[43:Spt:18632.0] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.17 18636[43:Res:18634.0,61.1] always3(s24) || -> . % 75.92/76.17 18637[43:SSi:18636.0,713.0,17902.0] || -> . % 75.92/76.17 18638[43:Spt:18637.0,18632.0,18634.0] || m_main_v_state(s24,c_busy)* -> . % 75.92/76.17 18639[43:Spt:18637.0,18632.1] || -> m_main_v_state(s25,c_busy)*. % 75.92/76.17 18643[43:Res:18639.0,61.1] always3(s25) || -> . % 75.92/76.17 18644[43:SSi:18643.0,714.0] || -> . % 75.92/76.17 18645[41:Spt:18644.0,17897.2,17901.0] || xuntil6(s23)*+ -> . % 75.92/76.17 18646[41:Spt:18644.0,17897.0,17897.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 75.92/76.17 18647[41:Res:53.1,18646.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 75.92/76.17 18649[42:Spt:18647.0] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.17 18651[42:Res:18649.0,61.1] always3(s23) || -> . % 75.92/76.17 18652[42:SSi:18651.0,712.0,17896.0] || -> . % 75.92/76.17 18653[42:Spt:18652.0,18647.0,18649.0] || m_main_v_state(s23,c_busy)* -> . % 75.92/76.17 18654[42:Spt:18652.0,18647.1] || -> m_main_v_state(s24,c_busy)*. % 75.92/76.17 18658[42:Res:18654.0,61.1] always3(s24) || -> . % 75.92/76.17 18659[42:SSi:18658.0,713.0] || -> . % 75.92/76.17 18660[40:Spt:18659.0,17894.2,17895.0] || xuntil6(s22)*+ -> . % 75.92/76.17 18661[40:Spt:18659.0,17894.0,17894.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 75.92/76.17 18662[40:Res:53.1,18661.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 75.92/76.17 18664[41:Spt:18662.0] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.17 18666[41:Res:18664.0,61.1] always3(s22) || -> . % 75.92/76.17 18667[41:SSi:18666.0,711.0,17893.0] || -> . % 75.92/76.17 18668[41:Spt:18667.0,18662.0,18664.0] || m_main_v_state(s22,c_busy)* -> . % 75.92/76.17 18669[41:Spt:18667.0,18662.1] || -> m_main_v_state(s23,c_busy)*. % 75.92/76.17 18673[41:Res:18669.0,61.1] always3(s23) || -> . % 75.92/76.17 18674[41:SSi:18673.0,712.0] || -> . % 75.92/76.17 18675[39:Spt:18674.0,17888.2,17892.0] || xuntil6(s21)*+ -> . % 75.92/76.17 18676[39:Spt:18674.0,17888.0,17888.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 75.92/76.17 18677[39:Res:53.1,18676.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 75.92/76.17 18679[40:Spt:18677.0] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.17 18681[40:Res:18679.0,61.1] always3(s21) || -> . % 75.92/76.17 18682[40:SSi:18681.0,710.0,17887.0] || -> . % 75.92/76.17 18683[40:Spt:18682.0,18677.0,18679.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.17 18684[40:Spt:18682.0,18677.1] || -> m_main_v_state(s22,c_busy)*. % 75.92/76.17 18688[40:Res:18684.0,61.1] always3(s22) || -> . % 75.92/76.17 18689[40:SSi:18688.0,711.0] || -> . % 75.92/76.17 18690[38:Spt:18689.0,17885.2,17886.0] || xuntil6(s20)*+ -> . % 75.92/76.17 18691[38:Spt:18689.0,17885.0,17885.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 75.92/76.17 18692[38:Res:53.1,18691.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 75.92/76.17 18694[39:Spt:18692.1] || -> m_main_v_state(s21,c_busy)*. % 75.92/76.17 18696[39:Res:18694.0,61.1] always3(s21) || -> . % 75.92/76.17 18697[39:SSi:18696.0,710.0] || -> . % 75.92/76.17 18698[39:Spt:18697.0,18692.1,18694.0] || m_main_v_state(s21,c_busy)* -> . % 75.92/76.17 18699[39:Spt:18697.0,18692.0] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.17 18702[39:Res:18699.0,61.1] always3(s20) || -> . % 75.92/76.17 18703[39:SSi:18702.0,709.0,17884.0] || -> . % 75.92/76.17 18704[37:Spt:18703.0,17879.2,17883.0] || xuntil6(s19)*+ -> . % 75.92/76.17 18705[37:Spt:18703.0,17879.0,17879.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 75.92/76.17 18706[37:Res:53.1,18705.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 75.92/76.17 18708[38:Spt:18706.1] || -> m_main_v_state(s20,c_busy)*. % 75.92/76.17 18710[38:Res:18708.0,61.1] always3(s20) || -> . % 75.92/76.17 18711[38:SSi:18710.0,709.0] || -> . % 75.92/76.17 18712[38:Spt:18711.0,18706.1,18708.0] || m_main_v_state(s20,c_busy)* -> . % 75.92/76.17 18713[38:Spt:18711.0,18706.0] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.17 18716[38:Res:18713.0,61.1] always3(s19) || -> . % 75.92/76.17 18717[38:SSi:18716.0,708.0,17878.0] || -> . % 75.92/76.17 18718[36:Spt:18717.0,17876.2,17877.0] || xuntil6(s18)*+ -> . % 75.92/76.17 18719[36:Spt:18717.0,17876.0,17876.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 75.92/76.17 18720[36:Res:53.1,18719.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 75.92/76.17 18722[37:Spt:18720.1] || -> m_main_v_state(s19,c_busy)*. % 75.92/76.17 18724[37:Res:18722.0,61.1] always3(s19) || -> . % 75.92/76.17 18725[37:SSi:18724.0,708.0] || -> . % 75.92/76.17 18726[37:Spt:18725.0,18720.1,18722.0] || m_main_v_state(s19,c_busy)* -> . % 75.92/76.17 18727[37:Spt:18725.0,18720.0] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.17 18730[37:Res:18727.0,61.1] always3(s18) || -> . % 75.92/76.17 18731[37:SSi:18730.0,707.0,17875.0] || -> . % 75.92/76.17 18732[35:Spt:18731.0,17870.2,17874.0] || xuntil6(s17)*+ -> . % 75.92/76.17 18733[35:Spt:18731.0,17870.0,17870.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 75.92/76.17 18734[35:Res:53.1,18733.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 75.92/76.17 18736[36:Spt:18734.1] || -> m_main_v_state(s18,c_busy)*. % 75.92/76.17 18738[36:Res:18736.0,61.1] always3(s18) || -> . % 75.92/76.17 18739[36:SSi:18738.0,707.0] || -> . % 75.92/76.17 18740[36:Spt:18739.0,18734.1,18736.0] || m_main_v_state(s18,c_busy)* -> . % 75.92/76.17 18741[36:Spt:18739.0,18734.0] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.17 18744[36:Res:18741.0,61.1] always3(s17) || -> . % 75.92/76.17 18745[36:SSi:18744.0,706.0,17869.0] || -> . % 75.92/76.17 18746[34:Spt:18745.0,17867.2,17868.0] || xuntil6(s16)*+ -> . % 75.92/76.17 18747[34:Spt:18745.0,17867.0,17867.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 75.92/76.17 18748[34:Res:53.1,18747.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 75.92/76.17 18753[35:Spt:18748.0] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.17 18755[35:Res:18753.0,61.1] always3(s16) || -> . % 75.92/76.17 18756[35:SSi:18755.0,705.0,17866.0] || -> . % 75.92/76.17 18757[35:Spt:18756.0,18748.0,18753.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.17 18758[35:Spt:18756.0,18748.1] || -> m_main_v_state(s17,c_busy)*. % 75.92/76.17 18762[35:Res:18758.0,61.1] always3(s17) || -> . % 75.92/76.17 18763[35:SSi:18762.0,706.0] || -> . % 75.92/76.17 18764[33:Spt:18763.0,17861.2,17865.0] || xuntil6(s15)*+ -> . % 75.92/76.17 18765[33:Spt:18763.0,17861.0,17861.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 75.92/76.17 18766[33:Res:53.1,18765.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 75.92/76.17 18768[34:Spt:18766.1] || -> m_main_v_state(s16,c_busy)*. % 75.92/76.17 18770[34:Res:18768.0,61.1] always3(s16) || -> . % 75.92/76.17 18771[34:SSi:18770.0,705.0] || -> . % 75.92/76.17 18772[34:Spt:18771.0,18766.1,18768.0] || m_main_v_state(s16,c_busy)* -> . % 75.92/76.17 18773[34:Spt:18771.0,18766.0] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.17 18776[34:Res:18773.0,61.1] always3(s15) || -> . % 75.92/76.17 18777[34:SSi:18776.0,704.0,17860.0] || -> . % 75.92/76.17 18778[32:Spt:18777.0,17858.2,17859.0] || xuntil6(s14)*+ -> . % 75.92/76.17 18779[32:Spt:18777.0,17858.0,17858.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 75.92/76.17 18780[32:Res:53.1,18779.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 75.92/76.17 18782[33:Spt:18780.1] || -> m_main_v_state(s15,c_busy)*. % 75.92/76.17 18784[33:Res:18782.0,61.1] always3(s15) || -> . % 75.92/76.17 18785[33:SSi:18784.0,704.0] || -> . % 75.92/76.17 18786[33:Spt:18785.0,18780.1,18782.0] || m_main_v_state(s15,c_busy)* -> . % 75.92/76.17 18787[33:Spt:18785.0,18780.0] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.17 18790[33:Res:18787.0,61.1] always3(s14) || -> . % 75.92/76.17 18791[33:SSi:18790.0,703.0,17857.0] || -> . % 75.92/76.17 18792[31:Spt:18791.0,17852.2,17856.0] || xuntil6(s13)*+ -> . % 75.92/76.17 18793[31:Spt:18791.0,17852.0,17852.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 75.92/76.17 18794[31:Res:53.1,18793.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 75.92/76.17 18799[32:Spt:18794.0] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.17 18801[32:Res:18799.0,61.1] always3(s13) || -> . % 75.92/76.17 18802[32:SSi:18801.0,702.0,17851.0] || -> . % 75.92/76.17 18803[32:Spt:18802.0,18794.0,18799.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.17 18804[32:Spt:18802.0,18794.1] || -> m_main_v_state(s14,c_busy)*. % 75.92/76.17 18808[32:Res:18804.0,61.1] always3(s14) || -> . % 75.92/76.17 18809[32:SSi:18808.0,703.0] || -> . % 75.92/76.17 18810[30:Spt:18809.0,17849.2,17850.0] || xuntil6(s12)*+ -> . % 75.92/76.17 18811[30:Spt:18809.0,17849.0,17849.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 75.92/76.17 18812[30:Res:53.1,18811.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 75.92/76.17 18814[31:Spt:18812.1] || -> m_main_v_state(s13,c_busy)*. % 75.92/76.17 18816[31:Res:18814.0,61.1] always3(s13) || -> . % 75.92/76.17 18817[31:SSi:18816.0,702.0] || -> . % 75.92/76.17 18818[31:Spt:18817.0,18812.1,18814.0] || m_main_v_state(s13,c_busy)* -> . % 75.92/76.17 18819[31:Spt:18817.0,18812.0] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.17 18822[31:Res:18819.0,61.1] always3(s12) || -> . % 75.92/76.17 18823[31:SSi:18822.0,701.0,17848.0] || -> . % 75.92/76.17 18824[29:Spt:18823.0,17843.2,17847.0] || xuntil6(s11)*+ -> . % 75.92/76.17 18825[29:Spt:18823.0,17843.0,17843.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 75.92/76.17 18826[29:Res:53.1,18825.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 75.92/76.17 18828[30:Spt:18826.1] || -> m_main_v_state(s12,c_busy)*. % 75.92/76.17 18830[30:Res:18828.0,61.1] always3(s12) || -> . % 75.92/76.17 18831[30:SSi:18830.0,701.0] || -> . % 75.92/76.17 18832[30:Spt:18831.0,18826.1,18828.0] || m_main_v_state(s12,c_busy)* -> . % 75.92/76.17 18833[30:Spt:18831.0,18826.0] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.17 18836[30:Res:18833.0,61.1] always3(s11) || -> . % 75.92/76.17 18837[30:SSi:18836.0,700.0,17842.0] || -> . % 75.92/76.17 18838[28:Spt:18837.0,17840.2,17841.0] || xuntil6(s10)*+ -> . % 75.92/76.17 18839[28:Spt:18837.0,17840.0,17840.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 75.92/76.17 18840[28:Res:53.1,18839.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 75.92/76.17 18845[29:Spt:18840.0] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.17 18847[29:Res:18845.0,61.1] always3(s10) || -> . % 75.92/76.17 18848[29:SSi:18847.0,699.0,17839.0] || -> . % 75.92/76.17 18849[29:Spt:18848.0,18840.0,18845.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.17 18850[29:Spt:18848.0,18840.1] || -> m_main_v_state(s11,c_busy)*. % 75.92/76.17 18854[29:Res:18850.0,61.1] always3(s11) || -> . % 75.92/76.17 18855[29:SSi:18854.0,700.0] || -> . % 75.92/76.17 18856[27:Spt:18855.0,17834.2,17838.0] || xuntil6(s9)*+ -> . % 75.92/76.17 18857[27:Spt:18855.0,17834.0,17834.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 75.92/76.17 18858[27:Res:53.1,18857.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 75.92/76.17 18860[28:Spt:18858.1] || -> m_main_v_state(s10,c_busy)*. % 75.92/76.17 18862[28:Res:18860.0,61.1] always3(s10) || -> . % 75.92/76.17 18863[28:SSi:18862.0,699.0] || -> . % 75.92/76.17 18864[28:Spt:18863.0,18858.1,18860.0] || m_main_v_state(s10,c_busy)* -> . % 75.92/76.17 18865[28:Spt:18863.0,18858.0] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.17 18868[28:Res:18865.0,61.1] always3(s9) || -> . % 75.92/76.17 18869[28:SSi:18868.0,698.0,17833.0] || -> . % 75.92/76.17 18870[26:Spt:18869.0,17831.2,17832.0] || xuntil6(s8)*+ -> . % 75.92/76.17 18871[26:Spt:18869.0,17831.0,17831.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 75.92/76.17 18872[26:Res:53.1,18871.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 75.92/76.17 18874[27:Spt:18872.1] || -> m_main_v_state(s9,c_busy)*. % 75.92/76.17 18876[27:Res:18874.0,61.1] always3(s9) || -> . % 75.92/76.17 18877[27:SSi:18876.0,698.0] || -> . % 75.92/76.17 18878[27:Spt:18877.0,18872.1,18874.0] || m_main_v_state(s9,c_busy)* -> . % 75.92/76.17 18879[27:Spt:18877.0,18872.0] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.17 18882[27:Res:18879.0,61.1] always3(s8) || -> . % 75.92/76.17 18883[27:SSi:18882.0,697.0,17830.0] || -> . % 75.92/76.17 18884[25:Spt:18883.0,17825.2,17829.0] || xuntil6(s7)*+ -> . % 75.92/76.17 18885[25:Spt:18883.0,17825.0,17825.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 75.92/76.17 18886[25:Res:53.1,18885.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 75.92/76.17 18891[26:Spt:18886.0] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.17 18893[26:Res:18891.0,61.1] always3(s7) || -> . % 75.92/76.17 18894[26:SSi:18893.0,696.0,17824.0] || -> . % 75.92/76.17 18895[26:Spt:18894.0,18886.0,18891.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.17 18896[26:Spt:18894.0,18886.1] || -> m_main_v_state(s8,c_busy)*. % 75.92/76.17 18900[26:Res:18896.0,61.1] always3(s8) || -> . % 75.92/76.17 18901[26:SSi:18900.0,697.0] || -> . % 75.92/76.17 18902[24:Spt:18901.0,17822.2,17823.0] || xuntil6(s6)*+ -> . % 75.92/76.17 18903[24:Spt:18901.0,17822.0,17822.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 75.92/76.17 18904[24:Res:53.1,18903.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 75.92/76.17 18906[25:Spt:18904.1] || -> m_main_v_state(s7,c_busy)*. % 75.92/76.17 18908[25:Res:18906.0,61.1] always3(s7) || -> . % 75.92/76.17 18909[25:SSi:18908.0,696.0] || -> . % 75.92/76.17 18910[25:Spt:18909.0,18904.1,18906.0] || m_main_v_state(s7,c_busy)* -> . % 75.92/76.17 18911[25:Spt:18909.0,18904.0] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.17 18914[25:Res:18911.0,61.1] always3(s6) || -> . % 75.92/76.17 18915[25:SSi:18914.0,695.0,17821.0] || -> . % 75.92/76.17 18916[23:Spt:18915.0,17816.2,17820.0] || xuntil6(s5)*+ -> . % 75.92/76.17 18917[23:Spt:18915.0,17816.0,17816.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 75.92/76.17 18918[23:Res:53.1,18917.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 75.92/76.17 18920[24:Spt:18918.1] || -> m_main_v_state(s6,c_busy)*. % 75.92/76.17 18922[24:Res:18920.0,61.1] always3(s6) || -> . % 75.92/76.17 18923[24:SSi:18922.0,695.0] || -> . % 75.92/76.17 18924[24:Spt:18923.0,18918.1,18920.0] || m_main_v_state(s6,c_busy)* -> . % 75.92/76.17 18925[24:Spt:18923.0,18918.0] || -> m_main_v_state(s5,c_busy)*. % 75.92/76.17 18928[24:Res:18925.0,61.1] always3(s5) || -> . % 75.92/76.17 18929[24:SSi:18928.0,694.0,17815.0] || -> . % 75.92/76.17 18930[22:Spt:18929.0,17813.2,17814.0] || xuntil6(s4)*+ -> . % 75.92/76.17 18931[22:Spt:18929.0,17813.0,17813.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 75.92/76.17 18932[22:Res:53.1,18931.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 75.92/76.17 18937[23:Spt:18932.0] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.17 18939[23:Res:18937.0,61.1] always3(s4) || -> . % 76.01/76.17 18940[23:SSi:18939.0,693.0,17812.0] || -> . % 76.01/76.17 18941[23:Spt:18940.0,18932.0,18937.0] || m_main_v_state(s4,c_busy)* -> . % 76.01/76.17 18942[23:Spt:18940.0,18932.1] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.17 18946[23:Res:18942.0,61.1] always3(s5) || -> . % 76.01/76.17 18947[23:SSi:18946.0,694.0] || -> . % 76.01/76.17 18948[21:Spt:18947.0,17807.2,17811.0] || xuntil6(s3)*+ -> . % 76.01/76.17 18949[21:Spt:18947.0,17807.0,17807.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.01/76.17 18950[21:Res:53.1,18949.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.01/76.17 18952[22:Spt:18950.1] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.17 18954[22:Res:18952.0,61.1] always3(s4) || -> . % 76.01/76.17 18955[22:SSi:18954.0,693.0] || -> . % 76.01/76.17 18956[22:Spt:18955.0,18950.1,18952.0] || m_main_v_state(s4,c_busy)* -> . % 76.01/76.17 18957[22:Spt:18955.0,18950.0] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.17 18960[22:Res:18957.0,61.1] always3(s3) || -> . % 76.01/76.17 18961[22:SSi:18960.0,692.0,17806.0] || -> . % 76.01/76.17 18962[20:Spt:18961.0,17804.2,17805.0] || xuntil6(s2)*+ -> . % 76.01/76.17 18963[20:Spt:18961.0,17804.0,17804.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.01/76.17 18964[20:Res:53.1,18963.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.01/76.17 18966[21:Spt:18964.1] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.17 18968[21:Res:18966.0,61.1] always3(s3) || -> . % 76.01/76.17 18969[21:SSi:18968.0,692.0] || -> . % 76.01/76.17 18970[21:Spt:18969.0,18964.1,18966.0] || m_main_v_state(s3,c_busy)* -> . % 76.01/76.17 18971[21:Spt:18969.0,18964.0] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.17 18974[21:Res:18971.0,61.1] always3(s2) || -> . % 76.01/76.17 18975[21:SSi:18974.0,691.0,17803.0] || -> . % 76.01/76.17 18976[19:Spt:18975.0,17795.2,17802.0] || xuntil6(s1)*+ -> . % 76.01/76.17 18977[19:Spt:18975.0,17795.0,17795.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.01/76.17 18978[19:Res:53.1,18977.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.01/76.17 18983[20:Spt:18978.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.17 18985[20:Res:18983.0,61.1] always3(s1) || -> . % 76.01/76.17 18986[20:SSi:18985.0,690.0,17794.0] || -> . % 76.01/76.17 18987[20:Spt:18986.0,18978.0,18983.0] || m_main_v_state(s1,c_busy)* -> . % 76.01/76.17 18988[20:Spt:18986.0,18978.1] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.17 18993[20:Res:18988.0,61.1] always3(s2) || -> . % 76.01/76.17 18994[20:SSi:18993.0,691.0] || -> . % 76.01/76.17 18995[18:Spt:18994.0,74.0,17793.0] || xuntil6(s0)*+ -> . % 76.01/76.17 18996[18:Spt:18994.0,74.1] || -> node4(s0)*. % 76.01/76.17 18997[18:MRR:758.1,18995.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.17 18999[18:Res:18997.0,61.1] always3(s1) || -> . % 76.01/76.17 19000[18:SSi:18999.0,690.0] || -> . % 76.01/76.17 19001[17:Spt:19000.0,17783.0,17787.0] || trans(s49,s34)*+ -> . % 76.01/76.17 19002[17:Spt:19000.0,17783.1,17783.2,17783.3,17783.4,17783.5,17783.6,17783.7,17783.8,17783.9,17783.10,17783.11,17783.12,17783.13,17783.14,17783.15,17783.16,17783.17,17783.18,17783.19,17783.20,17783.21,17783.22,17783.23,17783.24,17783.25,17783.26,17783.27,17783.28,17783.29,17783.30,17783.31,17783.32,17783.33,17783.34] || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.01/76.17 19004[17:MRR:17784.0,19001.0] || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.01/76.17 19005[17:MRR:17786.1,19001.0] xuntil6(s49) || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.01/76.17 19006[18:Spt:19002.0] || -> trans(s49,s33)*. % 76.01/76.17 19007[18:Res:19006.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s33)*. % 76.01/76.17 19009[18:Res:19006.0,60.0] || -> node2(s49,s33)*. % 76.01/76.17 19010[18:SSi:19007.1,50.0,738.0] xuntil6(s49) || -> until2p7(s33)*. % 76.01/76.17 19011[18:Res:19009.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.01/76.17 19012[19:Spt:74.0] || -> xuntil6(s0)*. % 76.01/76.17 19013[19:MRR:176.0,19012.0] || -> until5(s1)*. % 76.01/76.17 19014[19:MRR:16847.0,19013.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.17 19018[20:Spt:19014.2] || -> xuntil6(s1)*. % 76.01/76.17 19019[20:MRR:175.0,19018.0] || -> until5(s2)*. % 76.01/76.17 19020[20:MRR:16846.0,19019.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.17 19021[21:Spt:19020.2] || -> xuntil6(s2)*. % 76.01/76.17 19022[21:MRR:174.0,19021.0] || -> until5(s3)*. % 76.01/76.17 19023[21:MRR:16839.0,19022.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.17 19024[22:Spt:19023.2] || -> xuntil6(s3)*. % 76.01/76.17 19025[22:MRR:173.0,19024.0] || -> until5(s4)*. % 76.01/76.17 19026[22:MRR:16835.0,19025.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.17 19027[23:Spt:19026.2] || -> xuntil6(s4)*. % 76.01/76.17 19028[23:MRR:172.0,19027.0] || -> until5(s5)*. % 76.01/76.17 19029[23:MRR:16831.0,19028.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.17 19033[24:Spt:19029.2] || -> xuntil6(s5)*. % 76.01/76.17 19034[24:MRR:171.0,19033.0] || -> until5(s6)*. % 76.01/76.17 19035[24:MRR:16827.0,19034.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.17 19036[25:Spt:19035.2] || -> xuntil6(s6)*. % 76.01/76.17 19037[25:MRR:170.0,19036.0] || -> until5(s7)*. % 76.01/76.17 19038[25:MRR:16826.0,19037.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.17 19042[26:Spt:19038.2] || -> xuntil6(s7)*. % 76.01/76.17 19043[26:MRR:169.0,19042.0] || -> until5(s8)*. % 76.01/76.17 19044[26:MRR:16819.0,19043.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.17 19045[27:Spt:19044.2] || -> xuntil6(s8)*. % 76.01/76.17 19046[27:MRR:168.0,19045.0] || -> until5(s9)*. % 76.01/76.17 19047[27:MRR:16815.0,19046.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.17 19051[28:Spt:19047.2] || -> xuntil6(s9)*. % 76.01/76.17 19052[28:MRR:167.0,19051.0] || -> until5(s10)*. % 76.01/76.17 19053[28:MRR:16811.0,19052.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.17 19054[29:Spt:19053.2] || -> xuntil6(s10)*. % 76.01/76.17 19055[29:MRR:166.0,19054.0] || -> until5(s11)*. % 76.01/76.17 19056[29:MRR:16807.0,19055.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.17 19060[30:Spt:19056.2] || -> xuntil6(s11)*. % 76.01/76.17 19061[30:MRR:165.0,19060.0] || -> until5(s12)*. % 76.01/76.17 19062[30:MRR:16806.0,19061.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.17 19063[31:Spt:19062.2] || -> xuntil6(s12)*. % 76.01/76.17 19064[31:MRR:164.0,19063.0] || -> until5(s13)*. % 76.01/76.17 19065[31:MRR:16799.0,19064.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.17 19069[32:Spt:19065.2] || -> xuntil6(s13)*. % 76.01/76.17 19070[32:MRR:163.0,19069.0] || -> until5(s14)*. % 76.01/76.17 19071[32:MRR:16795.0,19070.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.17 19072[33:Spt:19071.2] || -> xuntil6(s14)*. % 76.01/76.17 19073[33:MRR:162.0,19072.0] || -> until5(s15)*. % 76.01/76.17 19074[33:MRR:16791.0,19073.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.17 19078[34:Spt:19074.2] || -> xuntil6(s15)*. % 76.01/76.17 19079[34:MRR:161.0,19078.0] || -> until5(s16)*. % 76.01/76.17 19080[34:MRR:16787.0,19079.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.17 19081[35:Spt:19080.2] || -> xuntil6(s16)*. % 76.01/76.17 19082[35:MRR:160.0,19081.0] || -> until5(s17)*. % 76.01/76.17 19083[35:MRR:16786.0,19082.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.17 19087[36:Spt:19083.2] || -> xuntil6(s17)*. % 76.01/76.17 19088[36:MRR:159.0,19087.0] || -> until5(s18)*. % 76.01/76.17 19089[36:MRR:16779.0,19088.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.17 19090[37:Spt:19089.2] || -> xuntil6(s18)*. % 76.01/76.17 19091[37:MRR:158.0,19090.0] || -> until5(s19)*. % 76.01/76.17 19092[37:MRR:16775.0,19091.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.17 19096[38:Spt:19092.2] || -> xuntil6(s19)*. % 76.01/76.17 19097[38:MRR:157.0,19096.0] || -> until5(s20)*. % 76.01/76.17 19098[38:MRR:16771.0,19097.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.17 19099[39:Spt:19098.2] || -> xuntil6(s20)*. % 76.01/76.17 19100[39:MRR:156.0,19099.0] || -> until5(s21)*. % 76.01/76.17 19101[39:MRR:16767.0,19100.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.17 19105[40:Spt:19101.2] || -> xuntil6(s21)*. % 76.01/76.17 19106[40:MRR:155.0,19105.0] || -> until5(s22)*. % 76.01/76.17 19107[40:MRR:16766.0,19106.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.17 19108[41:Spt:19107.2] || -> xuntil6(s22)*. % 76.01/76.17 19109[41:MRR:154.0,19108.0] || -> until5(s23)*. % 76.01/76.17 19110[41:MRR:16759.0,19109.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.17 19114[42:Spt:19110.2] || -> xuntil6(s23)*. % 76.01/76.17 19115[42:MRR:153.0,19114.0] || -> until5(s24)*. % 76.01/76.17 19116[42:MRR:16755.0,19115.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.17 19117[43:Spt:19116.2] || -> xuntil6(s24)*. % 76.01/76.17 19118[43:MRR:152.0,19117.0] || -> until5(s25)*. % 76.01/76.17 19119[43:MRR:16751.0,19118.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.17 19123[44:Spt:19119.2] || -> xuntil6(s25)*. % 76.01/76.17 19124[44:MRR:151.0,19123.0] || -> until5(s26)*. % 76.01/76.17 19125[44:MRR:16747.0,19124.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.17 19126[45:Spt:19125.2] || -> xuntil6(s26)*. % 76.01/76.17 19127[45:MRR:150.0,19126.0] || -> until5(s27)*. % 76.01/76.17 19128[45:MRR:16746.0,19127.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.17 19132[46:Spt:19128.2] || -> xuntil6(s27)*. % 76.01/76.17 19133[46:MRR:149.0,19132.0] || -> until5(s28)*. % 76.01/76.17 19134[46:MRR:16739.0,19133.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.17 19135[47:Spt:19134.2] || -> xuntil6(s28)*. % 76.01/76.17 19136[47:MRR:148.0,19135.0] || -> until5(s29)*. % 76.01/76.17 19137[47:MRR:16738.0,19136.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.17 19141[48:Spt:19137.2] || -> xuntil6(s29)*. % 76.01/76.17 19142[48:MRR:147.0,19141.0] || -> until5(s30)*. % 76.01/76.17 19143[48:MRR:16737.0,19142.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.17 19144[49:Spt:19143.2] || -> xuntil6(s30)*. % 76.01/76.17 19145[49:MRR:146.0,19144.0] || -> until5(s31)*. % 76.01/76.17 19146[49:MRR:16733.0,19145.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.17 19150[50:Spt:19146.2] || -> xuntil6(s31)*. % 76.01/76.17 19151[50:MRR:145.0,19150.0] || -> until5(s32)*. % 76.01/76.17 19152[50:MRR:16732.0,19151.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.17 19153[51:Spt:19152.2] || -> xuntil6(s32)*. % 76.01/76.17 19154[51:MRR:144.0,19153.0] || -> until5(s33)*. % 76.01/76.17 19155[51:MRR:932.0,19154.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.17 19159[52:Spt:19155.2] || -> xuntil6(s33)*. % 76.01/76.17 19160[52:MRR:143.0,19159.0] || -> until5(s34)*. % 76.01/76.17 19161[52:MRR:16857.0,19160.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.17 19162[53:Spt:19161.1] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.17 19164[53:Res:19162.0,61.1] always3(s35) || -> . % 76.01/76.17 19165[53:SSi:19164.0,724.0] || -> . % 76.01/76.17 19166[53:Spt:19165.0,19161.1,19162.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.01/76.17 19167[53:Spt:19165.0,19161.0,19161.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 76.01/76.17 19169[53:MRR:816.2,19166.0] node4(s34) || m_main_v_state(s34,c_ready)* -> . % 76.01/76.17 19170[53:Res:53.1,19167.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 76.01/76.17 19175[54:Spt:19170.1] || -> xuntil6(s34)*. % 76.01/76.17 19176[54:MRR:142.0,19175.0] || -> until5(s35)*. % 76.01/76.17 19177[54:MRR:930.0,19176.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.17 19179[55:Spt:19177.2] || -> xuntil6(s35)*. % 76.01/76.17 19180[55:MRR:141.0,19179.0] || -> until5(s36)*. % 76.01/76.17 19181[55:MRR:16858.0,19180.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.17 19182[56:Spt:19181.1] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.17 19184[56:Res:19182.0,61.1] always3(s37) || -> . % 76.01/76.17 19185[56:SSi:19184.0,726.0] || -> . % 76.01/76.17 19186[56:Spt:19185.0,19181.1,19182.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.01/76.17 19187[56:Spt:19185.0,19181.0,19181.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 76.01/76.17 19189[56:MRR:810.2,19186.0] node4(s36) || m_main_v_state(s36,c_ready)* -> . % 76.01/76.17 19190[56:Res:53.1,19187.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 76.01/76.17 19192[57:Spt:19190.1] || -> xuntil6(s36)*. % 76.01/76.17 19193[57:MRR:140.0,19192.0] || -> until5(s37)*. % 76.01/76.17 19194[57:MRR:928.0,19193.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.17 19199[58:Spt:19194.2] || -> xuntil6(s37)*. % 76.01/76.17 19200[58:MRR:139.0,19199.0] || -> until5(s38)*. % 76.01/76.17 19201[58:MRR:16862.0,19200.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.17 19202[59:Spt:19201.1] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.17 19204[59:Res:19202.0,61.1] always3(s39) || -> . % 76.01/76.17 19205[59:SSi:19204.0,728.0] || -> . % 76.01/76.17 19206[59:Spt:19205.0,19201.1,19202.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.01/76.17 19207[59:Spt:19205.0,19201.0,19201.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 76.01/76.17 19209[59:MRR:804.2,19206.0] node4(s38) || m_main_v_state(s38,c_ready)* -> . % 76.01/76.17 19210[59:Res:53.1,19207.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 76.01/76.17 19212[60:Spt:19210.1] || -> xuntil6(s38)*. % 76.01/76.17 19213[60:MRR:138.0,19212.0] || -> until5(s39)*. % 76.01/76.17 19214[60:MRR:926.0,19213.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.17 19222[61:Spt:19214.2] || -> xuntil6(s39)*. % 76.01/76.17 19223[61:MRR:137.0,19222.0] || -> until5(s40)*. % 76.01/76.17 19224[61:MRR:16866.0,19223.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.01/76.17 19225[62:Spt:19224.1] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.17 19227[62:Res:19225.0,61.1] always3(s41) || -> . % 76.01/76.17 19228[62:SSi:19227.0,730.0] || -> . % 76.01/76.17 19229[62:Spt:19228.0,19224.1,19225.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.01/76.17 19230[62:Spt:19228.0,19224.0,19224.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 76.01/76.17 19232[62:MRR:798.2,19229.0] node4(s40) || m_main_v_state(s40,c_ready)* -> . % 76.01/76.17 19233[62:Res:53.1,19230.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 76.01/76.17 19238[63:Spt:19233.1] || -> xuntil6(s40)*. % 76.01/76.17 19239[63:MRR:136.0,19238.0] || -> until5(s41)*. % 76.01/76.17 19240[63:MRR:924.0,19239.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.17 19242[64:Spt:19240.2] || -> xuntil6(s41)*. % 76.01/76.17 19243[64:MRR:135.0,19242.0] || -> until5(s42)*. % 76.01/76.17 19244[64:MRR:16870.0,19243.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.01/76.17 19245[65:Spt:19244.1] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.17 19247[65:Res:19245.0,61.1] always3(s43) || -> . % 76.01/76.17 19248[65:SSi:19247.0,732.0] || -> . % 76.01/76.17 19249[65:Spt:19248.0,19244.1,19245.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.01/76.17 19250[65:Spt:19248.0,19244.0,19244.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 76.01/76.17 19252[65:MRR:792.2,19249.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 76.01/76.17 19253[65:Res:53.1,19250.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 76.01/76.17 19255[66:Spt:19253.1] || -> xuntil6(s42)*. % 76.01/76.17 19256[66:MRR:134.0,19255.0] || -> until5(s43)*. % 76.01/76.17 19257[66:MRR:922.0,19256.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.17 19262[67:Spt:19257.2] || -> xuntil6(s43)*. % 76.01/76.17 19263[67:MRR:133.0,19262.0] || -> until5(s44)*. % 76.01/76.17 19264[67:MRR:16877.0,19263.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.01/76.17 19265[68:Spt:19264.1] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.17 19267[68:Res:19265.0,61.1] always3(s45) || -> . % 76.01/76.17 19268[68:SSi:19267.0,734.0] || -> . % 76.01/76.17 19269[68:Spt:19268.0,19264.1,19265.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.01/76.17 19270[68:Spt:19268.0,19264.0,19264.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 76.01/76.17 19272[68:MRR:786.2,19269.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 76.01/76.17 19273[68:Res:53.1,19270.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 76.01/76.17 19275[69:Spt:19273.1] || -> xuntil6(s44)*. % 76.01/76.17 19276[69:MRR:132.0,19275.0] || -> until5(s45)*. % 76.01/76.17 19277[69:MRR:920.0,19276.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.17 19285[70:Spt:19277.2] || -> xuntil6(s45)*. % 76.01/76.17 19286[70:MRR:131.0,19285.0] || -> until5(s46)*. % 76.01/76.17 19287[70:MRR:16878.0,19286.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.01/76.17 19288[71:Spt:19287.1] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.17 19290[71:Res:19288.0,61.1] always3(s47) || -> . % 76.01/76.17 19291[71:SSi:19290.0,736.0] || -> . % 76.01/76.17 19292[71:Spt:19291.0,19287.1,19288.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.01/76.17 19293[71:Spt:19291.0,19287.0,19287.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 76.01/76.17 19295[71:MRR:780.2,19292.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 76.01/76.17 19296[71:Res:53.1,19293.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 76.01/76.17 19301[72:Spt:19296.1] || -> xuntil6(s46)*. % 76.01/76.17 19302[72:MRR:130.0,19301.0] || -> until5(s47)*. % 76.01/76.17 19303[72:MRR:918.0,19302.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.17 19305[73:Spt:19303.2] || -> xuntil6(s47)*. % 76.01/76.17 19306[73:MRR:129.0,19305.0] || -> until5(s48)*. % 76.01/76.17 19307[73:MRR:16882.0,19306.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.01/76.17 19308[74:Spt:19307.1] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.17 19310[74:Res:19308.0,61.1] always3(s49) || -> . % 76.01/76.17 19311[74:SSi:19310.0,50.0,738.0] || -> . % 76.01/76.17 19312[74:Spt:19311.0,19307.1,19308.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.01/76.17 19313[74:Spt:19311.0,19307.0,19307.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 76.01/76.17 19315[74:MRR:774.2,19312.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.01/76.17 19316[74:Res:53.1,19313.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 76.01/76.17 19318[75:Spt:19316.1] || -> xuntil6(s48)*. % 76.01/76.17 19319[75:MRR:128.0,19318.0] || -> until5(s49)*. % 76.01/76.17 19324[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.17 19325[0:SoR:819.0,66.2] until5(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.17 19326[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.17 19330[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.17 19334[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.17 19341[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.17 19342[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.17 19346[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.17 19350[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.17 19354[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.17 19361[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.17 19362[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.17 19366[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.17 19370[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.17 19374[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.17 19381[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.17 19382[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.17 19386[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.17 19390[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.17 19394[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.17 19401[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.17 19402[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.17 19406[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.17 19410[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.17 19414[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.17 19421[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.17 19422[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.17 19426[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.17 19430[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.17 19434[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.17 19441[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.17 19442[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.17 19446[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.17 19450[0:SoR:813.0,66.2] until5(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.17 19454[0:SoR:807.0,66.2] until5(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.17 19461[0:SoR:801.0,66.2] until5(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.17 19462[0:SoR:795.0,66.2] until5(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.17 19466[0:SoR:789.0,66.2] until5(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.17 19470[0:SoR:783.0,66.2] until5(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.17 19474[0:SoR:777.0,66.2] until5(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.17 19476[18:SoR:19011.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.01/76.17 19478[18:SoR:19476.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.01/76.17 19479[75:SSi:19478.0,50.0,738.0,19319.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.01/76.17 19480[76:Spt:19479.1] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.17 19482[76:Res:19480.0,61.1] always3(s33) || -> . % 76.01/76.17 19483[76:SSi:19482.0,722.0,19154.0,19159.0] || -> . % 76.01/76.17 19484[76:Spt:19483.0,19479.1,19480.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.01/76.17 19485[76:Spt:19483.0,19479.0,19479.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.01/76.17 19489[76:MRR:19476.2,19484.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.01/76.17 19490[76:Res:53.1,19485.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.01/76.17 19492[76:MRR:19490.0,19312.0] || -> xuntil6(s49)*. % 76.01/76.17 19493[76:MRR:19010.0,19492.0] || -> until2p7(s33)*. % 76.01/76.17 19494[76:MRR:229.0,19493.0] || -> until2p7(s34)* node4(s33). % 76.01/76.17 19495[77:Spt:19494.0] || -> until2p7(s34)*. % 76.01/76.17 19496[77:MRR:230.0,19495.0] || -> until2p7(s35)* node4(s34). % 76.01/76.17 19497[78:Spt:19496.0] || -> until2p7(s35)*. % 76.01/76.17 19498[78:MRR:231.0,19497.0] || -> until2p7(s36)* node4(s35). % 76.01/76.17 19499[79:Spt:19498.0] || -> until2p7(s36)*. % 76.01/76.17 19500[79:MRR:232.0,19499.0] || -> until2p7(s37)* node4(s36). % 76.01/76.17 19501[80:Spt:19500.0] || -> until2p7(s37)*. % 76.01/76.17 19502[80:MRR:235.0,19501.0] || -> until2p7(s38)* node4(s37). % 76.01/76.17 19503[81:Spt:19502.0] || -> until2p7(s38)*. % 76.01/76.17 19504[81:MRR:236.0,19503.0] || -> until2p7(s39)* node4(s38). % 76.01/76.17 19505[82:Spt:19504.0] || -> until2p7(s39)*. % 76.01/76.17 19506[82:MRR:237.0,19505.0] || -> until2p7(s40)* node4(s39). % 76.01/76.17 19507[83:Spt:19506.0] || -> until2p7(s40)*. % 76.01/76.17 19508[83:MRR:238.0,19507.0] || -> until2p7(s41)* node4(s40). % 76.01/76.17 19509[84:Spt:19508.0] || -> until2p7(s41)*. % 76.01/76.17 19510[84:MRR:239.0,19509.0] || -> until2p7(s42)* node4(s41). % 76.01/76.17 19511[85:Spt:19510.0] || -> until2p7(s42)*. % 76.01/76.17 19512[85:MRR:240.0,19511.0] || -> until2p7(s43)* node4(s42). % 76.01/76.17 19513[86:Spt:19512.0] || -> until2p7(s43)*. % 76.01/76.17 19514[86:MRR:241.0,19513.0] || -> until2p7(s44)* node4(s43). % 76.01/76.17 19515[87:Spt:19514.0] || -> until2p7(s44)*. % 76.01/76.17 19516[87:MRR:539.0,19515.0] || -> until2p7(s45)* node4(s44). % 76.01/76.17 19517[88:Spt:19516.0] || -> until2p7(s45)*. % 76.01/76.17 19518[88:MRR:544.0,19517.0] || -> until2p7(s46)* node4(s45). % 76.01/76.17 19519[89:Spt:19518.0] || -> until2p7(s46)*. % 76.01/76.17 19520[89:MRR:549.0,19519.0] || -> until2p7(s47)* node4(s46). % 76.01/76.17 19521[90:Spt:19520.0] || -> until2p7(s47)*. % 76.01/76.17 19522[90:MRR:554.0,19521.0] || -> until2p7(s48)* node4(s47). % 76.01/76.17 19523[91:Spt:19522.0] || -> until2p7(s48)*. % 76.01/76.17 19524[91:MRR:559.0,19523.0] || -> until2p7(s49)* node4(s48). % 76.01/76.17 19525[92:Spt:19524.0] || -> until2p7(s49)*. % 76.01/76.17 19526[92:MRR:194.0,19525.0] || -> node4(s49)*. % 76.01/76.17 19527[92:MRR:19489.0,19526.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.01/76.17 19528[92:Res:53.1,19527.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.17 19530[92:MRR:19528.0,19312.0] || -> . % 76.01/76.17 19531[92:Spt:19530.0,19524.0,19525.0] || until2p7(s49)*+ -> . % 76.01/76.17 19532[92:Spt:19530.0,19524.1] || -> node4(s48)*. % 76.01/76.17 19533[92:MRR:19315.0,19532.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.01/76.17 19536[92:Res:53.1,19533.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.17 19539[92:Res:19536.0,61.1] always3(s48) || -> . % 76.01/76.17 19540[92:SSi:19539.0,737.0,19306.0,19318.0,19523.0,19532.0] || -> . % 76.01/76.17 19541[91:Spt:19540.0,19522.0,19523.0] || until2p7(s48)*+ -> . % 76.01/76.17 19542[91:Spt:19540.0,19522.1] || -> node4(s47)*. % 76.01/76.17 19544[91:MRR:777.0,19542.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.01/76.17 19559[91:Res:53.1,19544.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.01/76.17 19561[91:MRR:19559.0,19292.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.17 19563[91:Res:19561.0,61.1] always3(s48) || -> . % 76.01/76.17 19564[91:SSi:19563.0,737.0,19306.0,19318.0] || -> . % 76.01/76.17 19565[90:Spt:19564.0,19520.0,19521.0] || until2p7(s47)*+ -> . % 76.01/76.17 19566[90:Spt:19564.0,19520.1] || -> node4(s46)*. % 76.01/76.17 19567[90:MRR:19295.0,19566.0] || m_main_v_state(s46,c_ready)*+ -> . % 76.01/76.17 19570[90:Res:53.1,19567.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.17 19573[90:Res:19570.0,61.1] always3(s46) || -> . % 76.01/76.17 19574[90:SSi:19573.0,735.0,19286.0,19301.0,19519.0,19566.0] || -> . % 76.01/76.17 19575[89:Spt:19574.0,19518.0,19519.0] || until2p7(s46)*+ -> . % 76.01/76.17 19576[89:Spt:19574.0,19518.1] || -> node4(s45)*. % 76.01/76.17 19578[89:MRR:783.0,19576.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.01/76.17 19590[89:Res:53.1,19578.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.01/76.17 19592[89:MRR:19590.0,19269.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.17 19597[89:Res:19592.0,61.1] always3(s46) || -> . % 76.01/76.17 19598[89:SSi:19597.0,735.0,19286.0,19301.0] || -> . % 76.01/76.17 19599[88:Spt:19598.0,19516.0,19517.0] || until2p7(s45)*+ -> . % 76.01/76.17 19600[88:Spt:19598.0,19516.1] || -> node4(s44)*. % 76.01/76.17 19601[88:MRR:19272.0,19600.0] || m_main_v_state(s44,c_ready)*+ -> . % 76.01/76.17 19604[88:Res:53.1,19601.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.17 19608[88:Res:19604.0,61.1] always3(s44) || -> . % 76.01/76.17 19609[88:SSi:19608.0,733.0,19263.0,19275.0,19515.0,19600.0] || -> . % 76.01/76.17 19610[87:Spt:19609.0,19514.0,19515.0] || until2p7(s44)*+ -> . % 76.01/76.17 19611[87:Spt:19609.0,19514.1] || -> node4(s43)*. % 76.01/76.17 19613[87:MRR:789.0,19611.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.01/76.17 19624[87:Res:53.1,19613.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.01/76.17 19626[87:MRR:19624.0,19249.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.17 19628[87:Res:19626.0,61.1] always3(s44) || -> . % 76.01/76.17 19629[87:SSi:19628.0,733.0,19263.0,19275.0] || -> . % 76.01/76.17 19630[86:Spt:19629.0,19512.0,19513.0] || until2p7(s43)*+ -> . % 76.01/76.17 19631[86:Spt:19629.0,19512.1] || -> node4(s42)*. % 76.01/76.17 19632[86:MRR:19252.0,19631.0] || m_main_v_state(s42,c_ready)*+ -> . % 76.01/76.17 19636[86:Res:53.1,19632.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.17 19639[86:Res:19636.0,61.1] always3(s42) || -> . % 76.01/76.17 19640[86:SSi:19639.0,731.0,19243.0,19255.0,19511.0,19631.0] || -> . % 76.01/76.17 19641[85:Spt:19640.0,19510.0,19511.0] || until2p7(s42)*+ -> . % 76.01/76.17 19642[85:Spt:19640.0,19510.1] || -> node4(s41)*. % 76.01/76.17 19644[85:MRR:795.0,19642.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.01/76.17 19655[85:Res:53.1,19644.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.01/76.17 19657[85:MRR:19655.0,19229.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.17 19659[85:Res:19657.0,61.1] always3(s42) || -> . % 76.01/76.17 19660[85:SSi:19659.0,731.0,19243.0,19255.0] || -> . % 76.01/76.17 19661[84:Spt:19660.0,19508.0,19509.0] || until2p7(s41)*+ -> . % 76.01/76.17 19662[84:Spt:19660.0,19508.1] || -> node4(s40)*. % 76.01/76.17 19663[84:MRR:19232.0,19662.0] || m_main_v_state(s40,c_ready)*+ -> . % 76.01/76.17 19666[84:Res:53.1,19663.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.17 19669[84:Res:19666.0,61.1] always3(s40) || -> . % 76.01/76.17 19670[84:SSi:19669.0,729.0,19223.0,19238.0,19507.0,19662.0] || -> . % 76.01/76.17 19671[83:Spt:19670.0,19506.0,19507.0] || until2p7(s40)*+ -> . % 76.01/76.17 19672[83:Spt:19670.0,19506.1] || -> node4(s39)*. % 76.01/76.17 19674[83:MRR:801.0,19672.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.01/76.17 19686[83:Res:53.1,19674.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.01/76.17 19688[83:MRR:19686.0,19206.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.17 19690[83:Res:19688.0,61.1] always3(s40) || -> . % 76.01/76.17 19691[83:SSi:19690.0,729.0,19223.0,19238.0] || -> . % 76.01/76.17 19692[82:Spt:19691.0,19504.0,19505.0] || until2p7(s39)*+ -> . % 76.01/76.17 19693[82:Spt:19691.0,19504.1] || -> node4(s38)*. % 76.01/76.17 19694[82:MRR:19209.0,19693.0] || m_main_v_state(s38,c_ready)*+ -> . % 76.01/76.17 19697[82:Res:53.1,19694.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.17 19700[82:Res:19697.0,61.1] always3(s38) || -> . % 76.01/76.17 19701[82:SSi:19700.0,727.0,19200.0,19212.0,19503.0,19693.0] || -> . % 76.01/76.17 19702[81:Spt:19701.0,19502.0,19503.0] || until2p7(s38)*+ -> . % 76.01/76.17 19703[81:Spt:19701.0,19502.1] || -> node4(s37)*. % 76.01/76.17 19705[81:MRR:807.0,19703.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.01/76.17 19717[81:Res:53.1,19705.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.01/76.17 19719[81:MRR:19717.0,19186.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.17 19724[81:Res:19719.0,61.1] always3(s38) || -> . % 76.01/76.17 19725[81:SSi:19724.0,727.0,19200.0,19212.0] || -> . % 76.01/76.17 19726[80:Spt:19725.0,19500.0,19501.0] || until2p7(s37)*+ -> . % 76.01/76.17 19727[80:Spt:19725.0,19500.1] || -> node4(s36)*. % 76.01/76.17 19728[80:MRR:19189.0,19727.0] || m_main_v_state(s36,c_ready)*+ -> . % 76.01/76.17 19731[80:Res:53.1,19728.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.17 19735[80:Res:19731.0,61.1] always3(s36) || -> . % 76.01/76.17 19736[80:SSi:19735.0,725.0,19180.0,19192.0,19499.0,19727.0] || -> . % 76.01/76.17 19737[79:Spt:19736.0,19498.0,19499.0] || until2p7(s36)*+ -> . % 76.01/76.18 19738[79:Spt:19736.0,19498.1] || -> node4(s35)*. % 76.01/76.18 19740[79:MRR:813.0,19738.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.01/76.18 19751[79:Res:53.1,19740.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.01/76.18 19753[79:MRR:19751.0,19166.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.18 19755[79:Res:19753.0,61.1] always3(s36) || -> . % 76.01/76.18 19756[79:SSi:19755.0,725.0,19180.0,19192.0] || -> . % 76.01/76.18 19757[78:Spt:19756.0,19496.0,19497.0] || until2p7(s35)*+ -> . % 76.01/76.18 19758[78:Spt:19756.0,19496.1] || -> node4(s34)*. % 76.01/76.18 19759[78:MRR:19169.0,19758.0] || m_main_v_state(s34,c_ready)*+ -> . % 76.01/76.18 19763[78:Res:53.1,19759.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.18 19766[78:Res:19763.0,61.1] always3(s34) || -> . % 76.01/76.18 19767[78:SSi:19766.0,723.0,19160.0,19175.0,19495.0,19758.0] || -> . % 76.01/76.18 19768[77:Spt:19767.0,19494.0,19495.0] || until2p7(s34)*+ -> . % 76.01/76.18 19769[77:Spt:19767.0,19494.1] || -> node4(s33)*. % 76.01/76.18 19771[77:MRR:819.0,19769.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.01/76.18 19782[77:Res:53.1,19771.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.01/76.18 19784[77:MRR:19782.0,19484.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.18 19786[77:Res:19784.0,61.1] always3(s34) || -> . % 76.01/76.18 19787[77:SSi:19786.0,723.0,19160.0,19175.0] || -> . % 76.01/76.18 19788[75:Spt:19787.0,19316.1,19318.0] || xuntil6(s48)* -> . % 76.01/76.18 19789[75:Spt:19787.0,19316.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.18 19792[75:Res:19789.0,61.1] always3(s48) || -> . % 76.01/76.18 19793[75:SSi:19792.0,737.0,19306.0] || -> . % 76.01/76.18 19794[73:Spt:19793.0,19303.2,19305.0] || xuntil6(s47)*+ -> . % 76.01/76.18 19795[73:Spt:19793.0,19303.0,19303.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.01/76.18 19796[73:Res:53.1,19795.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.01/76.18 19798[73:MRR:19796.0,19292.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.18 19801[73:Res:19798.0,61.1] always3(s48) || -> . % 76.01/76.18 19802[73:SSi:19801.0,737.0] || -> . % 76.01/76.18 19803[72:Spt:19802.0,19296.1,19301.0] || xuntil6(s46)* -> . % 76.01/76.18 19804[72:Spt:19802.0,19296.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.18 19807[72:Res:19804.0,61.1] always3(s46) || -> . % 76.01/76.18 19808[72:SSi:19807.0,735.0,19286.0] || -> . % 76.01/76.18 19809[70:Spt:19808.0,19277.2,19285.0] || xuntil6(s45)*+ -> . % 76.01/76.18 19810[70:Spt:19808.0,19277.0,19277.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.01/76.18 19811[70:Res:53.1,19810.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.01/76.18 19813[70:MRR:19811.0,19269.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.18 19815[70:Res:19813.0,61.1] always3(s46) || -> . % 76.01/76.18 19816[70:SSi:19815.0,735.0] || -> . % 76.01/76.18 19817[69:Spt:19816.0,19273.1,19275.0] || xuntil6(s44)* -> . % 76.01/76.18 19818[69:Spt:19816.0,19273.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.18 19821[69:Res:19818.0,61.1] always3(s44) || -> . % 76.01/76.18 19822[69:SSi:19821.0,733.0,19263.0] || -> . % 76.01/76.18 19823[67:Spt:19822.0,19257.2,19262.0] || xuntil6(s43)*+ -> . % 76.01/76.18 19824[67:Spt:19822.0,19257.0,19257.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.01/76.18 19825[67:Res:53.1,19824.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.01/76.18 19827[67:MRR:19825.0,19249.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.18 19830[67:Res:19827.0,61.1] always3(s44) || -> . % 76.01/76.18 19831[67:SSi:19830.0,733.0] || -> . % 76.01/76.18 19832[66:Spt:19831.0,19253.1,19255.0] || xuntil6(s42)* -> . % 76.01/76.18 19833[66:Spt:19831.0,19253.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.18 19836[66:Res:19833.0,61.1] always3(s42) || -> . % 76.01/76.18 19837[66:SSi:19836.0,731.0,19243.0] || -> . % 76.01/76.18 19838[64:Spt:19837.0,19240.2,19242.0] || xuntil6(s41)*+ -> . % 76.01/76.18 19839[64:Spt:19837.0,19240.0,19240.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.01/76.18 19840[64:Res:53.1,19839.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.01/76.18 19842[64:MRR:19840.0,19229.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.18 19844[64:Res:19842.0,61.1] always3(s42) || -> . % 76.01/76.18 19845[64:SSi:19844.0,731.0] || -> . % 76.01/76.18 19846[63:Spt:19845.0,19233.1,19238.0] || xuntil6(s40)* -> . % 76.01/76.18 19847[63:Spt:19845.0,19233.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.18 19850[63:Res:19847.0,61.1] always3(s40) || -> . % 76.01/76.18 19851[63:SSi:19850.0,729.0,19223.0] || -> . % 76.01/76.18 19852[61:Spt:19851.0,19214.2,19222.0] || xuntil6(s39)*+ -> . % 76.01/76.18 19853[61:Spt:19851.0,19214.0,19214.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.01/76.18 19854[61:Res:53.1,19853.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.01/76.18 19856[61:MRR:19854.0,19206.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.18 19858[61:Res:19856.0,61.1] always3(s40) || -> . % 76.01/76.18 19859[61:SSi:19858.0,729.0] || -> . % 76.01/76.18 19860[60:Spt:19859.0,19210.1,19212.0] || xuntil6(s38)* -> . % 76.01/76.18 19861[60:Spt:19859.0,19210.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.18 19864[60:Res:19861.0,61.1] always3(s38) || -> . % 76.01/76.18 19865[60:SSi:19864.0,727.0,19200.0] || -> . % 76.01/76.18 19866[58:Spt:19865.0,19194.2,19199.0] || xuntil6(s37)*+ -> . % 76.01/76.18 19867[58:Spt:19865.0,19194.0,19194.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.01/76.18 19868[58:Res:53.1,19867.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.01/76.18 19870[58:MRR:19868.0,19186.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.18 19872[58:Res:19870.0,61.1] always3(s38) || -> . % 76.01/76.18 19873[58:SSi:19872.0,727.0] || -> . % 76.01/76.18 19874[57:Spt:19873.0,19190.1,19192.0] || xuntil6(s36)* -> . % 76.01/76.18 19875[57:Spt:19873.0,19190.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.18 19878[57:Res:19875.0,61.1] always3(s36) || -> . % 76.01/76.18 19879[57:SSi:19878.0,725.0,19180.0] || -> . % 76.01/76.18 19880[55:Spt:19879.0,19177.2,19179.0] || xuntil6(s35)*+ -> . % 76.01/76.18 19881[55:Spt:19879.0,19177.0,19177.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.01/76.18 19882[55:Res:53.1,19881.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.01/76.18 19884[55:MRR:19882.0,19166.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.18 19886[55:Res:19884.0,61.1] always3(s36) || -> . % 76.01/76.18 19887[55:SSi:19886.0,725.0] || -> . % 76.01/76.18 19888[54:Spt:19887.0,19170.1,19175.0] || xuntil6(s34)* -> . % 76.01/76.18 19889[54:Spt:19887.0,19170.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.18 19892[54:Res:19889.0,61.1] always3(s34) || -> . % 76.01/76.18 19893[54:SSi:19892.0,723.0,19160.0] || -> . % 76.01/76.18 19894[52:Spt:19893.0,19155.2,19159.0] || xuntil6(s33)*+ -> . % 76.01/76.18 19895[52:Spt:19893.0,19155.0,19155.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.01/76.18 19896[52:Res:53.1,19895.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.01/76.18 19898[53:Spt:19896.1] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.18 19900[53:Res:19898.0,61.1] always3(s34) || -> . % 76.01/76.18 19901[53:SSi:19900.0,723.0] || -> . % 76.01/76.18 19902[53:Spt:19901.0,19896.1,19898.0] || m_main_v_state(s34,c_busy)* -> . % 76.01/76.18 19903[53:Spt:19901.0,19896.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.18 19906[53:Res:19903.0,61.1] always3(s33) || -> . % 76.01/76.18 19907[53:SSi:19906.0,722.0,19154.0] || -> . % 76.01/76.18 19908[51:Spt:19907.0,19152.2,19153.0] || xuntil6(s32)*+ -> . % 76.01/76.18 19909[51:Spt:19907.0,19152.0,19152.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.01/76.18 19910[51:Res:53.1,19909.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.01/76.18 19912[52:Spt:19910.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.18 19914[52:Res:19912.0,61.1] always3(s32) || -> . % 76.01/76.18 19915[52:SSi:19914.0,721.0,19151.0] || -> . % 76.01/76.18 19916[52:Spt:19915.0,19910.0,19912.0] || m_main_v_state(s32,c_busy)* -> . % 76.01/76.18 19917[52:Spt:19915.0,19910.1] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.18 19921[52:Res:19917.0,61.1] always3(s33) || -> . % 76.01/76.18 19922[52:SSi:19921.0,722.0] || -> . % 76.01/76.18 19923[50:Spt:19922.0,19146.2,19150.0] || xuntil6(s31)*+ -> . % 76.01/76.18 19924[50:Spt:19922.0,19146.0,19146.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.01/76.18 19925[50:Res:53.1,19924.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.01/76.18 19927[51:Spt:19925.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.18 19929[51:Res:19927.0,61.1] always3(s31) || -> . % 76.01/76.18 19930[51:SSi:19929.0,720.0,19145.0] || -> . % 76.01/76.18 19931[51:Spt:19930.0,19925.0,19927.0] || m_main_v_state(s31,c_busy)* -> . % 76.01/76.18 19932[51:Spt:19930.0,19925.1] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.18 19936[51:Res:19932.0,61.1] always3(s32) || -> . % 76.01/76.18 19937[51:SSi:19936.0,721.0] || -> . % 76.01/76.18 19938[49:Spt:19937.0,19143.2,19144.0] || xuntil6(s30)*+ -> . % 76.01/76.18 19939[49:Spt:19937.0,19143.0,19143.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.01/76.18 19940[49:Res:53.1,19939.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.01/76.18 19942[50:Spt:19940.0] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.18 19944[50:Res:19942.0,61.1] always3(s30) || -> . % 76.01/76.18 19945[50:SSi:19944.0,719.0,19142.0] || -> . % 76.01/76.18 19946[50:Spt:19945.0,19940.0,19942.0] || m_main_v_state(s30,c_busy)* -> . % 76.01/76.18 19947[50:Spt:19945.0,19940.1] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.18 19951[50:Res:19947.0,61.1] always3(s31) || -> . % 76.01/76.18 19952[50:SSi:19951.0,720.0] || -> . % 76.01/76.18 19953[48:Spt:19952.0,19137.2,19141.0] || xuntil6(s29)*+ -> . % 76.01/76.18 19954[48:Spt:19952.0,19137.0,19137.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.01/76.18 19955[48:Res:53.1,19954.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.01/76.18 19957[49:Spt:19955.0] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.18 19959[49:Res:19957.0,61.1] always3(s29) || -> . % 76.01/76.18 19960[49:SSi:19959.0,718.0,19136.0] || -> . % 76.01/76.18 19961[49:Spt:19960.0,19955.0,19957.0] || m_main_v_state(s29,c_busy)* -> . % 76.01/76.18 19962[49:Spt:19960.0,19955.1] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.18 19966[49:Res:19962.0,61.1] always3(s30) || -> . % 76.01/76.18 19967[49:SSi:19966.0,719.0] || -> . % 76.01/76.18 19968[47:Spt:19967.0,19134.2,19135.0] || xuntil6(s28)*+ -> . % 76.01/76.18 19969[47:Spt:19967.0,19134.0,19134.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.01/76.18 19970[47:Res:53.1,19969.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.01/76.18 19972[48:Spt:19970.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.18 19974[48:Res:19972.0,61.1] always3(s28) || -> . % 76.01/76.18 19975[48:SSi:19974.0,717.0,19133.0] || -> . % 76.01/76.18 19976[48:Spt:19975.0,19970.0,19972.0] || m_main_v_state(s28,c_busy)* -> . % 76.01/76.18 19977[48:Spt:19975.0,19970.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.18 19981[48:Res:19977.0,61.1] always3(s29) || -> . % 76.01/76.18 19982[48:SSi:19981.0,718.0] || -> . % 76.01/76.18 19983[46:Spt:19982.0,19128.2,19132.0] || xuntil6(s27)*+ -> . % 76.01/76.18 19984[46:Spt:19982.0,19128.0,19128.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.01/76.18 19985[46:Res:53.1,19984.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.01/76.18 19987[47:Spt:19985.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.18 19989[47:Res:19987.0,61.1] always3(s27) || -> . % 76.01/76.18 19990[47:SSi:19989.0,716.0,19127.0] || -> . % 76.01/76.18 19991[47:Spt:19990.0,19985.0,19987.0] || m_main_v_state(s27,c_busy)* -> . % 76.01/76.18 19992[47:Spt:19990.0,19985.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.18 19996[47:Res:19992.0,61.1] always3(s28) || -> . % 76.01/76.18 19997[47:SSi:19996.0,717.0] || -> . % 76.01/76.18 19998[45:Spt:19997.0,19125.2,19126.0] || xuntil6(s26)*+ -> . % 76.01/76.18 19999[45:Spt:19997.0,19125.0,19125.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.01/76.18 20000[45:Res:53.1,19999.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.01/76.18 20002[46:Spt:20000.0] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.18 20004[46:Res:20002.0,61.1] always3(s26) || -> . % 76.01/76.18 20005[46:SSi:20004.0,715.0,19124.0] || -> . % 76.01/76.18 20006[46:Spt:20005.0,20000.0,20002.0] || m_main_v_state(s26,c_busy)* -> . % 76.01/76.18 20007[46:Spt:20005.0,20000.1] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.18 20011[46:Res:20007.0,61.1] always3(s27) || -> . % 76.01/76.18 20012[46:SSi:20011.0,716.0] || -> . % 76.01/76.18 20013[44:Spt:20012.0,19119.2,19123.0] || xuntil6(s25)*+ -> . % 76.01/76.18 20014[44:Spt:20012.0,19119.0,19119.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.01/76.18 20015[44:Res:53.1,20014.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.01/76.18 20017[45:Spt:20015.0] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.18 20019[45:Res:20017.0,61.1] always3(s25) || -> . % 76.01/76.18 20020[45:SSi:20019.0,714.0,19118.0] || -> . % 76.01/76.18 20021[45:Spt:20020.0,20015.0,20017.0] || m_main_v_state(s25,c_busy)* -> . % 76.01/76.18 20022[45:Spt:20020.0,20015.1] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.18 20026[45:Res:20022.0,61.1] always3(s26) || -> . % 76.01/76.18 20027[45:SSi:20026.0,715.0] || -> . % 76.01/76.18 20028[43:Spt:20027.0,19116.2,19117.0] || xuntil6(s24)*+ -> . % 76.01/76.18 20029[43:Spt:20027.0,19116.0,19116.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.01/76.18 20030[43:Res:53.1,20029.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.01/76.18 20032[44:Spt:20030.0] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.18 20034[44:Res:20032.0,61.1] always3(s24) || -> . % 76.01/76.18 20035[44:SSi:20034.0,713.0,19115.0] || -> . % 76.01/76.18 20036[44:Spt:20035.0,20030.0,20032.0] || m_main_v_state(s24,c_busy)* -> . % 76.01/76.18 20037[44:Spt:20035.0,20030.1] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.18 20041[44:Res:20037.0,61.1] always3(s25) || -> . % 76.01/76.18 20042[44:SSi:20041.0,714.0] || -> . % 76.01/76.18 20043[42:Spt:20042.0,19110.2,19114.0] || xuntil6(s23)*+ -> . % 76.01/76.18 20044[42:Spt:20042.0,19110.0,19110.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.01/76.18 20045[42:Res:53.1,20044.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.01/76.18 20050[43:Spt:20045.0] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.18 20052[43:Res:20050.0,61.1] always3(s23) || -> . % 76.01/76.18 20053[43:SSi:20052.0,712.0,19109.0] || -> . % 76.01/76.18 20054[43:Spt:20053.0,20045.0,20050.0] || m_main_v_state(s23,c_busy)* -> . % 76.01/76.18 20055[43:Spt:20053.0,20045.1] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.18 20059[43:Res:20055.0,61.1] always3(s24) || -> . % 76.01/76.18 20060[43:SSi:20059.0,713.0] || -> . % 76.01/76.18 20061[41:Spt:20060.0,19107.2,19108.0] || xuntil6(s22)*+ -> . % 76.01/76.18 20062[41:Spt:20060.0,19107.0,19107.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.01/76.18 20063[41:Res:53.1,20062.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.01/76.18 20065[42:Spt:20063.0] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.18 20067[42:Res:20065.0,61.1] always3(s22) || -> . % 76.01/76.18 20068[42:SSi:20067.0,711.0,19106.0] || -> . % 76.01/76.18 20069[42:Spt:20068.0,20063.0,20065.0] || m_main_v_state(s22,c_busy)* -> . % 76.01/76.18 20070[42:Spt:20068.0,20063.1] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.18 20074[42:Res:20070.0,61.1] always3(s23) || -> . % 76.01/76.18 20075[42:SSi:20074.0,712.0] || -> . % 76.01/76.18 20076[40:Spt:20075.0,19101.2,19105.0] || xuntil6(s21)*+ -> . % 76.01/76.18 20077[40:Spt:20075.0,19101.0,19101.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.01/76.18 20078[40:Res:53.1,20077.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.01/76.18 20080[41:Spt:20078.0] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.18 20082[41:Res:20080.0,61.1] always3(s21) || -> . % 76.01/76.18 20083[41:SSi:20082.0,710.0,19100.0] || -> . % 76.01/76.18 20084[41:Spt:20083.0,20078.0,20080.0] || m_main_v_state(s21,c_busy)* -> . % 76.01/76.18 20085[41:Spt:20083.0,20078.1] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.18 20089[41:Res:20085.0,61.1] always3(s22) || -> . % 76.01/76.18 20090[41:SSi:20089.0,711.0] || -> . % 76.01/76.18 20091[39:Spt:20090.0,19098.2,19099.0] || xuntil6(s20)*+ -> . % 76.01/76.18 20092[39:Spt:20090.0,19098.0,19098.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.01/76.18 20093[39:Res:53.1,20092.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.01/76.18 20098[40:Spt:20093.0] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.18 20100[40:Res:20098.0,61.1] always3(s20) || -> . % 76.01/76.18 20101[40:SSi:20100.0,709.0,19097.0] || -> . % 76.01/76.18 20102[40:Spt:20101.0,20093.0,20098.0] || m_main_v_state(s20,c_busy)* -> . % 76.01/76.18 20103[40:Spt:20101.0,20093.1] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.18 20107[40:Res:20103.0,61.1] always3(s21) || -> . % 76.01/76.18 20108[40:SSi:20107.0,710.0] || -> . % 76.01/76.18 20109[38:Spt:20108.0,19092.2,19096.0] || xuntil6(s19)*+ -> . % 76.01/76.18 20110[38:Spt:20108.0,19092.0,19092.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.01/76.18 20111[38:Res:53.1,20110.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.01/76.18 20113[39:Spt:20111.0] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.18 20115[39:Res:20113.0,61.1] always3(s19) || -> . % 76.01/76.18 20116[39:SSi:20115.0,708.0,19091.0] || -> . % 76.01/76.18 20117[39:Spt:20116.0,20111.0,20113.0] || m_main_v_state(s19,c_busy)* -> . % 76.01/76.18 20118[39:Spt:20116.0,20111.1] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.18 20122[39:Res:20118.0,61.1] always3(s20) || -> . % 76.01/76.18 20123[39:SSi:20122.0,709.0] || -> . % 76.01/76.18 20124[37:Spt:20123.0,19089.2,19090.0] || xuntil6(s18)*+ -> . % 76.01/76.18 20125[37:Spt:20123.0,19089.0,19089.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.01/76.18 20126[37:Res:53.1,20125.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.01/76.18 20128[38:Spt:20126.0] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.18 20130[38:Res:20128.0,61.1] always3(s18) || -> . % 76.01/76.18 20131[38:SSi:20130.0,707.0,19088.0] || -> . % 76.01/76.18 20132[38:Spt:20131.0,20126.0,20128.0] || m_main_v_state(s18,c_busy)* -> . % 76.01/76.18 20133[38:Spt:20131.0,20126.1] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.18 20137[38:Res:20133.0,61.1] always3(s19) || -> . % 76.01/76.18 20138[38:SSi:20137.0,708.0] || -> . % 76.01/76.18 20139[36:Spt:20138.0,19083.2,19087.0] || xuntil6(s17)*+ -> . % 76.01/76.18 20140[36:Spt:20138.0,19083.0,19083.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.01/76.18 20141[36:Res:53.1,20140.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.01/76.18 20146[37:Spt:20141.0] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.18 20148[37:Res:20146.0,61.1] always3(s17) || -> . % 76.01/76.18 20149[37:SSi:20148.0,706.0,19082.0] || -> . % 76.01/76.18 20150[37:Spt:20149.0,20141.0,20146.0] || m_main_v_state(s17,c_busy)* -> . % 76.01/76.18 20151[37:Spt:20149.0,20141.1] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.18 20155[37:Res:20151.0,61.1] always3(s18) || -> . % 76.01/76.18 20156[37:SSi:20155.0,707.0] || -> . % 76.01/76.18 20157[35:Spt:20156.0,19080.2,19081.0] || xuntil6(s16)*+ -> . % 76.01/76.18 20158[35:Spt:20156.0,19080.0,19080.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.01/76.18 20159[35:Res:53.1,20158.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.01/76.18 20161[36:Spt:20159.0] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.18 20163[36:Res:20161.0,61.1] always3(s16) || -> . % 76.01/76.18 20164[36:SSi:20163.0,705.0,19079.0] || -> . % 76.01/76.18 20165[36:Spt:20164.0,20159.0,20161.0] || m_main_v_state(s16,c_busy)* -> . % 76.01/76.18 20166[36:Spt:20164.0,20159.1] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.18 20170[36:Res:20166.0,61.1] always3(s17) || -> . % 76.01/76.18 20171[36:SSi:20170.0,706.0] || -> . % 76.01/76.18 20172[34:Spt:20171.0,19074.2,19078.0] || xuntil6(s15)*+ -> . % 76.01/76.18 20173[34:Spt:20171.0,19074.0,19074.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.01/76.18 20174[34:Res:53.1,20173.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.01/76.18 20176[35:Spt:20174.0] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.18 20178[35:Res:20176.0,61.1] always3(s15) || -> . % 76.01/76.18 20179[35:SSi:20178.0,704.0,19073.0] || -> . % 76.01/76.18 20180[35:Spt:20179.0,20174.0,20176.0] || m_main_v_state(s15,c_busy)* -> . % 76.01/76.18 20181[35:Spt:20179.0,20174.1] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.18 20185[35:Res:20181.0,61.1] always3(s16) || -> . % 76.01/76.18 20186[35:SSi:20185.0,705.0] || -> . % 76.01/76.18 20187[33:Spt:20186.0,19071.2,19072.0] || xuntil6(s14)*+ -> . % 76.01/76.18 20188[33:Spt:20186.0,19071.0,19071.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.01/76.18 20189[33:Res:53.1,20188.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.01/76.18 20194[34:Spt:20189.0] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.18 20196[34:Res:20194.0,61.1] always3(s14) || -> . % 76.01/76.18 20197[34:SSi:20196.0,703.0,19070.0] || -> . % 76.01/76.18 20198[34:Spt:20197.0,20189.0,20194.0] || m_main_v_state(s14,c_busy)* -> . % 76.01/76.18 20199[34:Spt:20197.0,20189.1] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.18 20203[34:Res:20199.0,61.1] always3(s15) || -> . % 76.01/76.18 20204[34:SSi:20203.0,704.0] || -> . % 76.01/76.18 20205[32:Spt:20204.0,19065.2,19069.0] || xuntil6(s13)*+ -> . % 76.01/76.18 20206[32:Spt:20204.0,19065.0,19065.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.01/76.18 20207[32:Res:53.1,20206.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.01/76.18 20209[33:Spt:20207.0] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.18 20211[33:Res:20209.0,61.1] always3(s13) || -> . % 76.01/76.18 20212[33:SSi:20211.0,702.0,19064.0] || -> . % 76.01/76.18 20213[33:Spt:20212.0,20207.0,20209.0] || m_main_v_state(s13,c_busy)* -> . % 76.01/76.18 20214[33:Spt:20212.0,20207.1] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.18 20218[33:Res:20214.0,61.1] always3(s14) || -> . % 76.01/76.18 20219[33:SSi:20218.0,703.0] || -> . % 76.01/76.18 20220[31:Spt:20219.0,19062.2,19063.0] || xuntil6(s12)*+ -> . % 76.01/76.18 20221[31:Spt:20219.0,19062.0,19062.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.01/76.18 20222[31:Res:53.1,20221.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.01/76.18 20224[32:Spt:20222.0] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.18 20226[32:Res:20224.0,61.1] always3(s12) || -> . % 76.01/76.18 20227[32:SSi:20226.0,701.0,19061.0] || -> . % 76.01/76.18 20228[32:Spt:20227.0,20222.0,20224.0] || m_main_v_state(s12,c_busy)* -> . % 76.01/76.18 20229[32:Spt:20227.0,20222.1] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.18 20233[32:Res:20229.0,61.1] always3(s13) || -> . % 76.01/76.18 20234[32:SSi:20233.0,702.0] || -> . % 76.01/76.18 20235[30:Spt:20234.0,19056.2,19060.0] || xuntil6(s11)*+ -> . % 76.01/76.18 20236[30:Spt:20234.0,19056.0,19056.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.01/76.18 20237[30:Res:53.1,20236.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.01/76.18 20242[31:Spt:20237.0] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.18 20244[31:Res:20242.0,61.1] always3(s11) || -> . % 76.01/76.18 20245[31:SSi:20244.0,700.0,19055.0] || -> . % 76.01/76.18 20246[31:Spt:20245.0,20237.0,20242.0] || m_main_v_state(s11,c_busy)* -> . % 76.01/76.18 20247[31:Spt:20245.0,20237.1] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.18 20251[31:Res:20247.0,61.1] always3(s12) || -> . % 76.01/76.18 20252[31:SSi:20251.0,701.0] || -> . % 76.01/76.18 20253[29:Spt:20252.0,19053.2,19054.0] || xuntil6(s10)*+ -> . % 76.01/76.18 20254[29:Spt:20252.0,19053.0,19053.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.01/76.18 20255[29:Res:53.1,20254.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.01/76.18 20257[30:Spt:20255.0] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.18 20259[30:Res:20257.0,61.1] always3(s10) || -> . % 76.01/76.18 20260[30:SSi:20259.0,699.0,19052.0] || -> . % 76.01/76.18 20261[30:Spt:20260.0,20255.0,20257.0] || m_main_v_state(s10,c_busy)* -> . % 76.01/76.18 20262[30:Spt:20260.0,20255.1] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.18 20266[30:Res:20262.0,61.1] always3(s11) || -> . % 76.01/76.18 20267[30:SSi:20266.0,700.0] || -> . % 76.01/76.18 20268[28:Spt:20267.0,19047.2,19051.0] || xuntil6(s9)*+ -> . % 76.01/76.18 20269[28:Spt:20267.0,19047.0,19047.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.01/76.18 20270[28:Res:53.1,20269.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.01/76.18 20272[29:Spt:20270.0] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.18 20274[29:Res:20272.0,61.1] always3(s9) || -> . % 76.01/76.18 20275[29:SSi:20274.0,698.0,19046.0] || -> . % 76.01/76.18 20276[29:Spt:20275.0,20270.0,20272.0] || m_main_v_state(s9,c_busy)* -> . % 76.01/76.18 20277[29:Spt:20275.0,20270.1] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.18 20281[29:Res:20277.0,61.1] always3(s10) || -> . % 76.01/76.18 20282[29:SSi:20281.0,699.0] || -> . % 76.01/76.18 20283[27:Spt:20282.0,19044.2,19045.0] || xuntil6(s8)*+ -> . % 76.01/76.18 20284[27:Spt:20282.0,19044.0,19044.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.01/76.18 20285[27:Res:53.1,20284.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.01/76.18 20290[28:Spt:20285.0] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.18 20292[28:Res:20290.0,61.1] always3(s8) || -> . % 76.01/76.18 20293[28:SSi:20292.0,697.0,19043.0] || -> . % 76.01/76.18 20294[28:Spt:20293.0,20285.0,20290.0] || m_main_v_state(s8,c_busy)* -> . % 76.01/76.18 20295[28:Spt:20293.0,20285.1] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.18 20299[28:Res:20295.0,61.1] always3(s9) || -> . % 76.01/76.18 20300[28:SSi:20299.0,698.0] || -> . % 76.01/76.18 20301[26:Spt:20300.0,19038.2,19042.0] || xuntil6(s7)*+ -> . % 76.01/76.18 20302[26:Spt:20300.0,19038.0,19038.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.01/76.18 20303[26:Res:53.1,20302.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.01/76.18 20305[27:Spt:20303.0] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.18 20307[27:Res:20305.0,61.1] always3(s7) || -> . % 76.01/76.18 20308[27:SSi:20307.0,696.0,19037.0] || -> . % 76.01/76.18 20309[27:Spt:20308.0,20303.0,20305.0] || m_main_v_state(s7,c_busy)* -> . % 76.01/76.18 20310[27:Spt:20308.0,20303.1] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.18 20314[27:Res:20310.0,61.1] always3(s8) || -> . % 76.01/76.18 20315[27:SSi:20314.0,697.0] || -> . % 76.01/76.18 20316[25:Spt:20315.0,19035.2,19036.0] || xuntil6(s6)*+ -> . % 76.01/76.18 20317[25:Spt:20315.0,19035.0,19035.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.01/76.18 20318[25:Res:53.1,20317.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.01/76.18 20320[26:Spt:20318.0] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.18 20322[26:Res:20320.0,61.1] always3(s6) || -> . % 76.01/76.18 20323[26:SSi:20322.0,695.0,19034.0] || -> . % 76.01/76.18 20324[26:Spt:20323.0,20318.0,20320.0] || m_main_v_state(s6,c_busy)* -> . % 76.01/76.18 20325[26:Spt:20323.0,20318.1] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.18 20329[26:Res:20325.0,61.1] always3(s7) || -> . % 76.01/76.18 20330[26:SSi:20329.0,696.0] || -> . % 76.01/76.18 20331[24:Spt:20330.0,19029.2,19033.0] || xuntil6(s5)*+ -> . % 76.01/76.18 20332[24:Spt:20330.0,19029.0,19029.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.01/76.18 20333[24:Res:53.1,20332.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.01/76.18 20338[25:Spt:20333.0] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.18 20340[25:Res:20338.0,61.1] always3(s5) || -> . % 76.01/76.18 20341[25:SSi:20340.0,694.0,19028.0] || -> . % 76.01/76.18 20342[25:Spt:20341.0,20333.0,20338.0] || m_main_v_state(s5,c_busy)* -> . % 76.01/76.18 20343[25:Spt:20341.0,20333.1] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.18 20347[25:Res:20343.0,61.1] always3(s6) || -> . % 76.01/76.18 20348[25:SSi:20347.0,695.0] || -> . % 76.01/76.18 20349[23:Spt:20348.0,19026.2,19027.0] || xuntil6(s4)*+ -> . % 76.01/76.18 20350[23:Spt:20348.0,19026.0,19026.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.01/76.18 20351[23:Res:53.1,20350.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.01/76.18 20353[24:Spt:20351.0] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.18 20355[24:Res:20353.0,61.1] always3(s4) || -> . % 76.01/76.18 20356[24:SSi:20355.0,693.0,19025.0] || -> . % 76.01/76.18 20357[24:Spt:20356.0,20351.0,20353.0] || m_main_v_state(s4,c_busy)* -> . % 76.01/76.18 20358[24:Spt:20356.0,20351.1] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.18 20362[24:Res:20358.0,61.1] always3(s5) || -> . % 76.01/76.18 20363[24:SSi:20362.0,694.0] || -> . % 76.01/76.18 20364[22:Spt:20363.0,19023.2,19024.0] || xuntil6(s3)*+ -> . % 76.01/76.18 20365[22:Spt:20363.0,19023.0,19023.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.01/76.18 20366[22:Res:53.1,20365.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.01/76.18 20368[23:Spt:20366.0] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.18 20370[23:Res:20368.0,61.1] always3(s3) || -> . % 76.01/76.18 20371[23:SSi:20370.0,692.0,19022.0] || -> . % 76.01/76.18 20372[23:Spt:20371.0,20366.0,20368.0] || m_main_v_state(s3,c_busy)* -> . % 76.01/76.18 20373[23:Spt:20371.0,20366.1] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.18 20377[23:Res:20373.0,61.1] always3(s4) || -> . % 76.01/76.18 20378[23:SSi:20377.0,693.0] || -> . % 76.01/76.18 20379[21:Spt:20378.0,19020.2,19021.0] || xuntil6(s2)*+ -> . % 76.01/76.18 20380[21:Spt:20378.0,19020.0,19020.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.01/76.18 20381[21:Res:53.1,20380.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.01/76.18 20386[22:Spt:20381.0] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.18 20388[22:Res:20386.0,61.1] always3(s2) || -> . % 76.01/76.18 20389[22:SSi:20388.0,691.0,19019.0] || -> . % 76.01/76.18 20390[22:Spt:20389.0,20381.0,20386.0] || m_main_v_state(s2,c_busy)* -> . % 76.01/76.18 20391[22:Spt:20389.0,20381.1] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.18 20395[22:Res:20391.0,61.1] always3(s3) || -> . % 76.01/76.18 20396[22:SSi:20395.0,692.0] || -> . % 76.01/76.18 20397[20:Spt:20396.0,19014.2,19018.0] || xuntil6(s1)*+ -> . % 76.01/76.18 20398[20:Spt:20396.0,19014.0,19014.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.01/76.18 20399[20:Res:53.1,20398.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.01/76.18 20401[21:Spt:20399.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.18 20403[21:Res:20401.0,61.1] always3(s1) || -> . % 76.01/76.18 20404[21:SSi:20403.0,690.0,19013.0] || -> . % 76.01/76.18 20405[21:Spt:20404.0,20399.0,20401.0] || m_main_v_state(s1,c_busy)* -> . % 76.01/76.18 20406[21:Spt:20404.0,20399.1] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.18 20411[21:Res:20406.0,61.1] always3(s2) || -> . % 76.01/76.18 20412[21:SSi:20411.0,691.0] || -> . % 76.01/76.18 20413[19:Spt:20412.0,74.0,19012.0] || xuntil6(s0)*+ -> . % 76.01/76.18 20414[19:Spt:20412.0,74.1] || -> node4(s0)*. % 76.01/76.18 20415[19:MRR:758.1,20413.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.18 20417[19:Res:20415.0,61.1] always3(s1) || -> . % 76.01/76.18 20418[19:SSi:20417.0,690.0] || -> . % 76.01/76.18 20419[18:Spt:20418.0,19002.0,19006.0] || trans(s49,s33)*+ -> . % 76.01/76.18 20420[18:Spt:20418.0,19002.1,19002.2,19002.3,19002.4,19002.5,19002.6,19002.7,19002.8,19002.9,19002.10,19002.11,19002.12,19002.13,19002.14,19002.15,19002.16,19002.17,19002.18,19002.19,19002.20,19002.21,19002.22,19002.23,19002.24,19002.25,19002.26,19002.27,19002.28,19002.29,19002.30,19002.31,19002.32,19002.33] || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.01/76.18 20421[18:MRR:19004.0,20419.0] || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.01/76.18 20423[18:MRR:19005.1,20419.0] xuntil6(s49) || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.01/76.18 20424[19:Spt:20420.0] || -> trans(s49,s32)*. % 76.01/76.18 20425[19:Res:20424.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s32)*. % 76.01/76.18 20427[19:Res:20424.0,60.0] || -> node2(s49,s32)*. % 76.01/76.18 20428[19:SSi:20425.1,50.0,738.0] xuntil6(s49) || -> until2p7(s32)*. % 76.01/76.18 20429[19:Res:20427.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)*. % 76.01/76.18 20430[20:Spt:74.0] || -> xuntil6(s0)*. % 76.01/76.18 20431[20:MRR:176.0,20430.0] || -> until5(s1)*. % 76.01/76.18 20432[20:MRR:19446.0,20431.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.18 20439[21:Spt:20432.2] || -> xuntil6(s1)*. % 76.01/76.18 20440[21:MRR:175.0,20439.0] || -> until5(s2)*. % 76.01/76.18 20441[21:MRR:19442.0,20440.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.18 20442[22:Spt:20441.2] || -> xuntil6(s2)*. % 76.01/76.18 20443[22:MRR:174.0,20442.0] || -> until5(s3)*. % 76.01/76.18 20444[22:MRR:19441.0,20443.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.18 20448[23:Spt:20444.2] || -> xuntil6(s3)*. % 76.01/76.18 20449[23:MRR:173.0,20448.0] || -> until5(s4)*. % 76.01/76.18 20450[23:MRR:19434.0,20449.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.18 20451[24:Spt:20450.2] || -> xuntil6(s4)*. % 76.01/76.18 20452[24:MRR:172.0,20451.0] || -> until5(s5)*. % 76.01/76.18 20453[24:MRR:19430.0,20452.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.18 20457[25:Spt:20453.2] || -> xuntil6(s5)*. % 76.01/76.18 20458[25:MRR:171.0,20457.0] || -> until5(s6)*. % 76.01/76.18 20459[25:MRR:19426.0,20458.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.18 20460[26:Spt:20459.2] || -> xuntil6(s6)*. % 76.01/76.18 20461[26:MRR:170.0,20460.0] || -> until5(s7)*. % 76.01/76.18 20462[26:MRR:19422.0,20461.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.18 20466[27:Spt:20462.2] || -> xuntil6(s7)*. % 76.01/76.18 20467[27:MRR:169.0,20466.0] || -> until5(s8)*. % 76.01/76.18 20468[27:MRR:19421.0,20467.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.18 20469[28:Spt:20468.2] || -> xuntil6(s8)*. % 76.01/76.18 20470[28:MRR:168.0,20469.0] || -> until5(s9)*. % 76.01/76.18 20471[28:MRR:19414.0,20470.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.18 20475[29:Spt:20471.2] || -> xuntil6(s9)*. % 76.01/76.18 20476[29:MRR:167.0,20475.0] || -> until5(s10)*. % 76.01/76.18 20477[29:MRR:19410.0,20476.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.18 20478[30:Spt:20477.2] || -> xuntil6(s10)*. % 76.01/76.18 20479[30:MRR:166.0,20478.0] || -> until5(s11)*. % 76.01/76.18 20480[30:MRR:19406.0,20479.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.18 20484[31:Spt:20480.2] || -> xuntil6(s11)*. % 76.01/76.18 20485[31:MRR:165.0,20484.0] || -> until5(s12)*. % 76.01/76.18 20486[31:MRR:19402.0,20485.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.18 20487[32:Spt:20486.2] || -> xuntil6(s12)*. % 76.01/76.18 20488[32:MRR:164.0,20487.0] || -> until5(s13)*. % 76.01/76.18 20489[32:MRR:19401.0,20488.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.18 20493[33:Spt:20489.2] || -> xuntil6(s13)*. % 76.01/76.18 20494[33:MRR:163.0,20493.0] || -> until5(s14)*. % 76.01/76.18 20495[33:MRR:19394.0,20494.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.18 20496[34:Spt:20495.2] || -> xuntil6(s14)*. % 76.01/76.18 20497[34:MRR:162.0,20496.0] || -> until5(s15)*. % 76.01/76.18 20498[34:MRR:19390.0,20497.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.18 20502[35:Spt:20498.2] || -> xuntil6(s15)*. % 76.01/76.18 20503[35:MRR:161.0,20502.0] || -> until5(s16)*. % 76.01/76.18 20504[35:MRR:19386.0,20503.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.18 20505[36:Spt:20504.2] || -> xuntil6(s16)*. % 76.01/76.18 20506[36:MRR:160.0,20505.0] || -> until5(s17)*. % 76.01/76.18 20507[36:MRR:19382.0,20506.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.18 20511[37:Spt:20507.2] || -> xuntil6(s17)*. % 76.01/76.18 20512[37:MRR:159.0,20511.0] || -> until5(s18)*. % 76.01/76.18 20513[37:MRR:19381.0,20512.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.18 20514[38:Spt:20513.2] || -> xuntil6(s18)*. % 76.01/76.18 20515[38:MRR:158.0,20514.0] || -> until5(s19)*. % 76.01/76.18 20516[38:MRR:19374.0,20515.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.18 20520[39:Spt:20516.2] || -> xuntil6(s19)*. % 76.01/76.18 20521[39:MRR:157.0,20520.0] || -> until5(s20)*. % 76.01/76.18 20522[39:MRR:19370.0,20521.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.18 20523[40:Spt:20522.2] || -> xuntil6(s20)*. % 76.01/76.18 20524[40:MRR:156.0,20523.0] || -> until5(s21)*. % 76.01/76.18 20525[40:MRR:19366.0,20524.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.18 20529[41:Spt:20525.2] || -> xuntil6(s21)*. % 76.01/76.18 20530[41:MRR:155.0,20529.0] || -> until5(s22)*. % 76.01/76.18 20531[41:MRR:19362.0,20530.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.18 20532[42:Spt:20531.2] || -> xuntil6(s22)*. % 76.01/76.18 20533[42:MRR:154.0,20532.0] || -> until5(s23)*. % 76.01/76.18 20534[42:MRR:19361.0,20533.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.18 20538[43:Spt:20534.2] || -> xuntil6(s23)*. % 76.01/76.18 20539[43:MRR:153.0,20538.0] || -> until5(s24)*. % 76.01/76.18 20540[43:MRR:19354.0,20539.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.18 20541[44:Spt:20540.2] || -> xuntil6(s24)*. % 76.01/76.18 20542[44:MRR:152.0,20541.0] || -> until5(s25)*. % 76.01/76.18 20543[44:MRR:19350.0,20542.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.18 20547[45:Spt:20543.2] || -> xuntil6(s25)*. % 76.01/76.18 20548[45:MRR:151.0,20547.0] || -> until5(s26)*. % 76.01/76.18 20549[45:MRR:19346.0,20548.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.18 20550[46:Spt:20549.2] || -> xuntil6(s26)*. % 76.01/76.18 20551[46:MRR:150.0,20550.0] || -> until5(s27)*. % 76.01/76.18 20552[46:MRR:19342.0,20551.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.18 20556[47:Spt:20552.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.18 20558[47:Res:20556.0,61.1] always3(s28) || -> . % 76.01/76.18 20559[47:SSi:20558.0,717.0] || -> . % 76.01/76.18 20560[47:Spt:20559.0,20552.1,20556.0] || m_main_v_state(s28,c_busy)*+ -> . % 76.01/76.18 20561[47:Spt:20559.0,20552.0,20552.2] || m_main_v_state(s27,c_ready)*+ -> xuntil6(s27). % 76.01/76.18 20564[47:Res:53.1,20561.0] || -> m_main_v_state(s27,c_busy)* xuntil6(s27). % 76.01/76.18 20566[48:Spt:20564.1] || -> xuntil6(s27)*. % 76.01/76.18 20567[48:MRR:149.0,20566.0] || -> until5(s28)*. % 76.01/76.18 20568[48:MRR:19334.0,20567.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.18 20573[49:Spt:20568.2] || -> xuntil6(s28)*. % 76.01/76.18 20574[49:MRR:148.0,20573.0] || -> until5(s29)*. % 76.01/76.18 20575[49:MRR:19341.0,20574.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.18 20576[50:Spt:20575.1] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.18 20578[50:Res:20576.0,61.1] always3(s30) || -> . % 76.01/76.18 20579[50:SSi:20578.0,719.0] || -> . % 76.01/76.18 20580[50:Spt:20579.0,20575.1,20576.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.01/76.18 20581[50:Spt:20579.0,20575.0,20575.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 76.01/76.18 20584[50:Res:53.1,20581.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 76.01/76.18 20586[51:Spt:20584.1] || -> xuntil6(s29)*. % 76.01/76.18 20587[51:MRR:147.0,20586.0] || -> until5(s30)*. % 76.01/76.18 20588[51:MRR:19326.0,20587.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.18 20596[52:Spt:20588.2] || -> xuntil6(s30)*. % 76.01/76.18 20597[52:MRR:146.0,20596.0] || -> until5(s31)*. % 76.01/76.18 20598[52:MRR:19330.0,20597.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.18 20599[53:Spt:20598.1] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.18 20601[53:Res:20599.0,61.1] always3(s32) || -> . % 76.01/76.18 20602[53:SSi:20601.0,721.0] || -> . % 76.01/76.18 20603[53:Spt:20602.0,20598.1,20599.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.01/76.18 20604[53:Spt:20602.0,20598.0,20598.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.01/76.18 20607[53:MRR:20429.2,20603.0] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> . % 76.01/76.18 20608[53:Res:53.1,20604.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.01/76.18 20613[54:Spt:20608.1] || -> xuntil6(s31)*. % 76.01/76.18 20614[54:MRR:145.0,20613.0] || -> until5(s32)*. % 76.01/76.18 20615[54:MRR:19324.0,20614.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.18 20618[53:SoR:20607.0,64.1] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.01/76.18 20623[53:SoR:20618.0,66.2] until5(s49) || m_main_v_state(s49,c_ready)* -> xuntil6(s49). % 76.01/76.18 20624[55:Spt:20615.2] || -> xuntil6(s32)*. % 76.01/76.18 20625[55:MRR:144.0,20624.0] || -> until5(s33)*. % 76.01/76.18 20626[55:MRR:19325.0,20625.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.18 20630[56:Spt:20626.1] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.18 20632[56:Res:20630.0,61.1] always3(s34) || -> . % 76.01/76.18 20633[56:SSi:20632.0,723.0] || -> . % 76.01/76.18 20634[56:Spt:20633.0,20626.1,20630.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.01/76.18 20635[56:Spt:20633.0,20626.0,20626.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.01/76.18 20637[56:MRR:819.2,20634.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.01/76.18 20638[56:Res:53.1,20635.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.01/76.18 20640[57:Spt:20638.1] || -> xuntil6(s33)*. % 76.01/76.18 20641[57:MRR:143.0,20640.0] || -> until5(s34)*. % 76.01/76.18 20642[57:MRR:16857.0,20641.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.18 20647[58:Spt:20642.2] || -> xuntil6(s34)*. % 76.01/76.18 20648[58:MRR:142.0,20647.0] || -> until5(s35)*. % 76.01/76.18 20649[58:MRR:19450.0,20648.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.18 20650[59:Spt:20649.1] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.18 20652[59:Res:20650.0,61.1] always3(s36) || -> . % 76.01/76.18 20653[59:SSi:20652.0,725.0] || -> . % 76.01/76.18 20654[59:Spt:20653.0,20649.1,20650.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.01/76.18 20655[59:Spt:20653.0,20649.0,20649.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.01/76.18 20657[59:MRR:813.2,20654.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.01/76.18 20658[59:Res:53.1,20655.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.01/76.18 20660[60:Spt:20658.1] || -> xuntil6(s35)*. % 76.01/76.18 20661[60:MRR:141.0,20660.0] || -> until5(s36)*. % 76.01/76.18 20662[60:MRR:16858.0,20661.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.18 20670[61:Spt:20662.2] || -> xuntil6(s36)*. % 76.01/76.18 20671[61:MRR:140.0,20670.0] || -> until5(s37)*. % 76.01/76.18 20672[61:MRR:19454.0,20671.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.18 20673[62:Spt:20672.1] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.18 20675[62:Res:20673.0,61.1] always3(s38) || -> . % 76.01/76.18 20676[62:SSi:20675.0,727.0] || -> . % 76.01/76.18 20677[62:Spt:20676.0,20672.1,20673.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.01/76.18 20678[62:Spt:20676.0,20672.0,20672.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.01/76.18 20680[62:MRR:807.2,20677.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.01/76.18 20681[62:Res:53.1,20678.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.01/76.18 20686[63:Spt:20681.1] || -> xuntil6(s37)*. % 76.01/76.18 20687[63:MRR:139.0,20686.0] || -> until5(s38)*. % 76.01/76.18 20688[63:MRR:16862.0,20687.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.18 20690[64:Spt:20688.2] || -> xuntil6(s38)*. % 76.01/76.18 20691[64:MRR:138.0,20690.0] || -> until5(s39)*. % 76.01/76.18 20692[64:MRR:19461.0,20691.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.18 20693[65:Spt:20692.1] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.18 20695[65:Res:20693.0,61.1] always3(s40) || -> . % 76.01/76.18 20696[65:SSi:20695.0,729.0] || -> . % 76.01/76.18 20697[65:Spt:20696.0,20692.1,20693.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.01/76.18 20698[65:Spt:20696.0,20692.0,20692.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.01/76.18 20700[65:MRR:801.2,20697.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.01/76.18 20701[65:Res:53.1,20698.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.01/76.18 20703[66:Spt:20701.1] || -> xuntil6(s39)*. % 76.01/76.18 20704[66:MRR:137.0,20703.0] || -> until5(s40)*. % 76.01/76.18 20705[66:MRR:16866.0,20704.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.01/76.18 20710[67:Spt:20705.2] || -> xuntil6(s40)*. % 76.01/76.18 20711[67:MRR:136.0,20710.0] || -> until5(s41)*. % 76.01/76.18 20712[67:MRR:19462.0,20711.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.18 20713[68:Spt:20712.1] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.18 20715[68:Res:20713.0,61.1] always3(s42) || -> . % 76.01/76.18 20716[68:SSi:20715.0,731.0] || -> . % 76.01/76.18 20717[68:Spt:20716.0,20712.1,20713.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.01/76.18 20718[68:Spt:20716.0,20712.0,20712.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.01/76.18 20720[68:MRR:795.2,20717.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.01/76.18 20721[68:Res:53.1,20718.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.01/76.18 20723[69:Spt:20721.1] || -> xuntil6(s41)*. % 76.01/76.18 20724[69:MRR:135.0,20723.0] || -> until5(s42)*. % 76.01/76.18 20725[69:MRR:16870.0,20724.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.01/76.18 20733[70:Spt:20725.2] || -> xuntil6(s42)*. % 76.01/76.18 20734[70:MRR:134.0,20733.0] || -> until5(s43)*. % 76.01/76.18 20735[70:MRR:19466.0,20734.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.18 20736[71:Spt:20735.1] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.18 20738[71:Res:20736.0,61.1] always3(s44) || -> . % 76.01/76.18 20739[71:SSi:20738.0,733.0] || -> . % 76.01/76.18 20740[71:Spt:20739.0,20735.1,20736.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.01/76.18 20741[71:Spt:20739.0,20735.0,20735.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.01/76.18 20743[71:MRR:789.2,20740.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.01/76.18 20744[71:Res:53.1,20741.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.01/76.18 20749[72:Spt:20744.1] || -> xuntil6(s43)*. % 76.01/76.18 20750[72:MRR:133.0,20749.0] || -> until5(s44)*. % 76.01/76.18 20751[72:MRR:16877.0,20750.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.01/76.18 20753[73:Spt:20751.2] || -> xuntil6(s44)*. % 76.01/76.18 20754[73:MRR:132.0,20753.0] || -> until5(s45)*. % 76.01/76.18 20755[73:MRR:19470.0,20754.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.18 20756[74:Spt:20755.1] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.18 20758[74:Res:20756.0,61.1] always3(s46) || -> . % 76.01/76.18 20759[74:SSi:20758.0,735.0] || -> . % 76.01/76.18 20760[74:Spt:20759.0,20755.1,20756.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.01/76.18 20761[74:Spt:20759.0,20755.0,20755.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.01/76.18 20763[74:MRR:783.2,20760.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.01/76.18 20764[74:Res:53.1,20761.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.01/76.18 20766[75:Spt:20764.1] || -> xuntil6(s45)*. % 76.01/76.18 20767[75:MRR:131.0,20766.0] || -> until5(s46)*. % 76.01/76.18 20768[75:MRR:16878.0,20767.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.01/76.18 20773[76:Spt:20768.2] || -> xuntil6(s46)*. % 76.01/76.18 20774[76:MRR:130.0,20773.0] || -> until5(s47)*. % 76.01/76.18 20775[76:MRR:19474.0,20774.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.18 20776[77:Spt:20775.1] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.18 20778[77:Res:20776.0,61.1] always3(s48) || -> . % 76.01/76.18 20779[77:SSi:20778.0,737.0] || -> . % 76.01/76.18 20780[77:Spt:20779.0,20775.1,20776.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.01/76.18 20781[77:Spt:20779.0,20775.0,20775.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.01/76.18 20783[77:MRR:777.2,20780.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.01/76.18 20784[77:Res:53.1,20781.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.01/76.18 20786[78:Spt:20784.1] || -> xuntil6(s47)*. % 76.01/76.18 20787[78:MRR:129.0,20786.0] || -> until5(s48)*. % 76.01/76.18 20788[78:MRR:16882.0,20787.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.01/76.18 20796[79:Spt:20788.2] || -> xuntil6(s48)*. % 76.01/76.18 20797[79:MRR:128.0,20796.0] || -> until5(s49)*. % 76.01/76.18 20798[79:MRR:20623.0,20797.0] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.01/76.18 20799[79:Res:53.1,20798.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.01/76.18 20801[80:Spt:20799.1] || -> xuntil6(s49)*. % 76.01/76.18 20802[80:MRR:20428.0,20801.0] || -> until2p7(s32)*. % 76.01/76.18 20803[80:MRR:228.0,20802.0] || -> until2p7(s33)* node4(s32). % 76.01/76.18 20804[81:Spt:20803.0] || -> until2p7(s33)*. % 76.01/76.18 20805[81:MRR:229.0,20804.0] || -> until2p7(s34)* node4(s33). % 76.01/76.18 20806[82:Spt:20805.0] || -> until2p7(s34)*. % 76.01/76.18 20807[82:MRR:230.0,20806.0] || -> until2p7(s35)* node4(s34). % 76.01/76.18 20808[83:Spt:20807.0] || -> until2p7(s35)*. % 76.01/76.18 20809[83:MRR:231.0,20808.0] || -> until2p7(s36)* node4(s35). % 76.01/76.18 20810[84:Spt:20809.0] || -> until2p7(s36)*. % 76.01/76.18 20811[84:MRR:232.0,20810.0] || -> until2p7(s37)* node4(s36). % 76.01/76.18 20812[85:Spt:20811.0] || -> until2p7(s37)*. % 76.01/76.18 20813[85:MRR:235.0,20812.0] || -> until2p7(s38)* node4(s37). % 76.01/76.18 20814[86:Spt:20813.0] || -> until2p7(s38)*. % 76.01/76.18 20815[86:MRR:236.0,20814.0] || -> until2p7(s39)* node4(s38). % 76.01/76.18 20816[87:Spt:20815.0] || -> until2p7(s39)*. % 76.01/76.18 20817[87:MRR:237.0,20816.0] || -> until2p7(s40)* node4(s39). % 76.01/76.18 20818[88:Spt:20817.0] || -> until2p7(s40)*. % 76.01/76.18 20819[88:MRR:238.0,20818.0] || -> until2p7(s41)* node4(s40). % 76.01/76.18 20820[89:Spt:20819.0] || -> until2p7(s41)*. % 76.01/76.18 20821[89:MRR:239.0,20820.0] || -> until2p7(s42)* node4(s41). % 76.01/76.18 20822[90:Spt:20821.0] || -> until2p7(s42)*. % 76.01/76.18 20823[90:MRR:240.0,20822.0] || -> until2p7(s43)* node4(s42). % 76.01/76.18 20824[91:Spt:20823.0] || -> until2p7(s43)*. % 76.01/76.18 20825[91:MRR:241.0,20824.0] || -> until2p7(s44)* node4(s43). % 76.01/76.18 20826[92:Spt:20825.0] || -> until2p7(s44)*. % 76.01/76.18 20827[92:MRR:539.0,20826.0] || -> until2p7(s45)* node4(s44). % 76.01/76.18 20828[93:Spt:20827.0] || -> until2p7(s45)*. % 76.01/76.18 20829[93:MRR:544.0,20828.0] || -> until2p7(s46)* node4(s45). % 76.01/76.18 20830[94:Spt:20829.0] || -> until2p7(s46)*. % 76.01/76.18 20831[94:MRR:549.0,20830.0] || -> until2p7(s47)* node4(s46). % 76.01/76.18 20832[95:Spt:20831.0] || -> until2p7(s47)*. % 76.01/76.18 20833[95:MRR:554.0,20832.0] || -> until2p7(s48)* node4(s47). % 76.01/76.18 20834[96:Spt:20833.0] || -> until2p7(s48)*. % 76.01/76.18 20835[96:MRR:559.0,20834.0] || -> until2p7(s49)* node4(s48). % 76.01/76.18 20836[97:Spt:20835.0] || -> until2p7(s49)*. % 76.01/76.18 20837[97:MRR:194.0,20836.0] || -> node4(s49)*. % 76.01/76.18 20838[97:MRR:20618.0,20837.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.01/76.18 20839[97:Res:53.1,20838.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.18 20845[97:Res:20839.0,61.1] always3(s49) || -> . % 76.01/76.18 20846[97:SSi:20845.0,50.0,738.0,20797.0,20801.0,20836.0,20837.0] || -> . % 76.01/76.18 20847[97:Spt:20846.0,20835.0,20836.0] || until2p7(s49)*+ -> . % 76.01/76.18 20848[97:Spt:20846.0,20835.1] || -> node4(s48)*. % 76.01/76.18 20850[97:MRR:774.0,20848.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.01/76.18 20859[97:Res:53.1,20850.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.01/76.18 20861[97:MRR:20859.0,20780.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.18 20863[97:Res:20861.0,61.1] always3(s49) || -> . % 76.01/76.18 20864[97:SSi:20863.0,50.0,738.0,20797.0,20801.0] || -> . % 76.01/76.18 20865[96:Spt:20864.0,20833.0,20834.0] || until2p7(s48)*+ -> . % 76.01/76.18 20866[96:Spt:20864.0,20833.1] || -> node4(s47)*. % 76.01/76.18 20867[96:MRR:20783.0,20866.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.01/76.18 20870[96:Res:53.1,20867.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.18 20873[96:Res:20870.0,61.1] always3(s47) || -> . % 76.01/76.18 20874[96:SSi:20873.0,736.0,20774.0,20786.0,20832.0,20866.0] || -> . % 76.01/76.18 20875[95:Spt:20874.0,20831.0,20832.0] || until2p7(s47)*+ -> . % 76.01/76.18 20876[95:Spt:20874.0,20831.1] || -> node4(s46)*. % 76.01/76.18 20878[95:MRR:780.0,20876.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.01/76.18 20890[95:Res:53.1,20878.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.01/76.18 20892[95:MRR:20890.0,20760.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.18 20897[95:Res:20892.0,61.1] always3(s47) || -> . % 76.01/76.18 20898[95:SSi:20897.0,736.0,20774.0,20786.0] || -> . % 76.01/76.18 20899[94:Spt:20898.0,20829.0,20830.0] || until2p7(s46)*+ -> . % 76.01/76.18 20900[94:Spt:20898.0,20829.1] || -> node4(s45)*. % 76.01/76.18 20901[94:MRR:20763.0,20900.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.01/76.18 20904[94:Res:53.1,20901.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.18 20908[94:Res:20904.0,61.1] always3(s45) || -> . % 76.01/76.18 20909[94:SSi:20908.0,734.0,20754.0,20766.0,20828.0,20900.0] || -> . % 76.01/76.18 20910[93:Spt:20909.0,20827.0,20828.0] || until2p7(s45)*+ -> . % 76.01/76.18 20911[93:Spt:20909.0,20827.1] || -> node4(s44)*. % 76.01/76.18 20913[93:MRR:786.0,20911.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.01/76.18 20924[93:Res:53.1,20913.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.01/76.18 20926[93:MRR:20924.0,20740.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.18 20928[93:Res:20926.0,61.1] always3(s45) || -> . % 76.01/76.18 20929[93:SSi:20928.0,734.0,20754.0,20766.0] || -> . % 76.01/76.18 20930[92:Spt:20929.0,20825.0,20826.0] || until2p7(s44)*+ -> . % 76.01/76.18 20931[92:Spt:20929.0,20825.1] || -> node4(s43)*. % 76.01/76.18 20932[92:MRR:20743.0,20931.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.01/76.18 20936[92:Res:53.1,20932.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.18 20939[92:Res:20936.0,61.1] always3(s43) || -> . % 76.01/76.18 20940[92:SSi:20939.0,732.0,20734.0,20749.0,20824.0,20931.0] || -> . % 76.01/76.18 20941[91:Spt:20940.0,20823.0,20824.0] || until2p7(s43)*+ -> . % 76.01/76.18 20942[91:Spt:20940.0,20823.1] || -> node4(s42)*. % 76.01/76.18 20944[91:MRR:792.0,20942.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.01/76.18 20955[91:Res:53.1,20944.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.01/76.18 20957[91:MRR:20955.0,20717.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.18 20959[91:Res:20957.0,61.1] always3(s43) || -> . % 76.01/76.18 20960[91:SSi:20959.0,732.0,20734.0,20749.0] || -> . % 76.01/76.18 20961[90:Spt:20960.0,20821.0,20822.0] || until2p7(s42)*+ -> . % 76.01/76.18 20962[90:Spt:20960.0,20821.1] || -> node4(s41)*. % 76.01/76.18 20963[90:MRR:20720.0,20962.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.01/76.18 20966[90:Res:53.1,20963.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.18 20969[90:Res:20966.0,61.1] always3(s41) || -> . % 76.01/76.18 20970[90:SSi:20969.0,730.0,20711.0,20723.0,20820.0,20962.0] || -> . % 76.01/76.18 20971[89:Spt:20970.0,20819.0,20820.0] || until2p7(s41)*+ -> . % 76.01/76.18 20972[89:Spt:20970.0,20819.1] || -> node4(s40)*. % 76.01/76.18 20974[89:MRR:798.0,20972.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.01/76.18 20986[89:Res:53.1,20974.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.01/76.18 20988[89:MRR:20986.0,20697.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.18 20990[89:Res:20988.0,61.1] always3(s41) || -> . % 76.01/76.18 20991[89:SSi:20990.0,730.0,20711.0,20723.0] || -> . % 76.01/76.18 20992[88:Spt:20991.0,20817.0,20818.0] || until2p7(s40)*+ -> . % 76.01/76.18 20993[88:Spt:20991.0,20817.1] || -> node4(s39)*. % 76.01/76.18 20994[88:MRR:20700.0,20993.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.01/76.18 20997[88:Res:53.1,20994.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.18 21000[88:Res:20997.0,61.1] always3(s39) || -> . % 76.01/76.18 21001[88:SSi:21000.0,728.0,20691.0,20703.0,20816.0,20993.0] || -> . % 76.01/76.18 21002[87:Spt:21001.0,20815.0,20816.0] || until2p7(s39)*+ -> . % 76.01/76.18 21003[87:Spt:21001.0,20815.1] || -> node4(s38)*. % 76.01/76.18 21005[87:MRR:804.0,21003.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.01/76.18 21017[87:Res:53.1,21005.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.01/76.18 21019[87:MRR:21017.0,20677.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.18 21024[87:Res:21019.0,61.1] always3(s39) || -> . % 76.01/76.18 21025[87:SSi:21024.0,728.0,20691.0,20703.0] || -> . % 76.01/76.18 21026[86:Spt:21025.0,20813.0,20814.0] || until2p7(s38)*+ -> . % 76.01/76.18 21027[86:Spt:21025.0,20813.1] || -> node4(s37)*. % 76.01/76.18 21028[86:MRR:20680.0,21027.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.01/76.18 21031[86:Res:53.1,21028.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.18 21035[86:Res:21031.0,61.1] always3(s37) || -> . % 76.01/76.18 21036[86:SSi:21035.0,726.0,20671.0,20686.0,20812.0,21027.0] || -> . % 76.01/76.18 21037[85:Spt:21036.0,20811.0,20812.0] || until2p7(s37)*+ -> . % 76.01/76.18 21038[85:Spt:21036.0,20811.1] || -> node4(s36)*. % 76.01/76.18 21040[85:MRR:810.0,21038.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.01/76.18 21051[85:Res:53.1,21040.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.01/76.18 21053[85:MRR:21051.0,20654.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.18 21055[85:Res:21053.0,61.1] always3(s37) || -> . % 76.01/76.18 21056[85:SSi:21055.0,726.0,20671.0,20686.0] || -> . % 76.01/76.18 21057[84:Spt:21056.0,20809.0,20810.0] || until2p7(s36)*+ -> . % 76.01/76.18 21058[84:Spt:21056.0,20809.1] || -> node4(s35)*. % 76.01/76.18 21059[84:MRR:20657.0,21058.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.01/76.18 21063[84:Res:53.1,21059.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.18 21066[84:Res:21063.0,61.1] always3(s35) || -> . % 76.01/76.18 21067[84:SSi:21066.0,724.0,20648.0,20660.0,20808.0,21058.0] || -> . % 76.01/76.18 21068[83:Spt:21067.0,20807.0,20808.0] || until2p7(s35)*+ -> . % 76.01/76.18 21069[83:Spt:21067.0,20807.1] || -> node4(s34)*. % 76.01/76.18 21071[83:MRR:816.0,21069.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.01/76.18 21082[83:Res:53.1,21071.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.01/76.18 21084[83:MRR:21082.0,20634.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.18 21086[83:Res:21084.0,61.1] always3(s35) || -> . % 76.01/76.18 21087[83:SSi:21086.0,724.0,20648.0,20660.0] || -> . % 76.01/76.18 21088[82:Spt:21087.0,20805.0,20806.0] || until2p7(s34)*+ -> . % 76.01/76.18 21089[82:Spt:21087.0,20805.1] || -> node4(s33)*. % 76.01/76.18 21090[82:MRR:20637.0,21089.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.01/76.18 21093[82:Res:53.1,21090.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.18 21096[82:Res:21093.0,61.1] always3(s33) || -> . % 76.01/76.18 21097[82:SSi:21096.0,722.0,20625.0,20640.0,20804.0,21089.0] || -> . % 76.01/76.18 21098[81:Spt:21097.0,20803.0,20804.0] || until2p7(s33)*+ -> . % 76.01/76.18 21099[81:Spt:21097.0,20803.1] || -> node4(s32)*. % 76.01/76.18 21101[81:MRR:822.0,21099.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.01/76.18 21113[81:Res:53.1,21101.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.01/76.18 21115[81:MRR:21113.0,20603.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.18 21117[81:Res:21115.0,61.1] always3(s33) || -> . % 76.01/76.18 21118[81:SSi:21117.0,722.0,20625.0,20640.0] || -> . % 76.01/76.18 21119[80:Spt:21118.0,20799.1,20801.0] || xuntil6(s49)* -> . % 76.01/76.18 21120[80:Spt:21118.0,20799.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.18 21123[80:Res:21120.0,61.1] always3(s49) || -> . % 76.01/76.18 21124[80:SSi:21123.0,50.0,738.0,20797.0] || -> . % 76.01/76.18 21125[79:Spt:21124.0,20788.2,20796.0] || xuntil6(s48)*+ -> . % 76.01/76.18 21126[79:Spt:21124.0,20788.0,20788.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.01/76.18 21127[79:Res:53.1,21126.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.01/76.18 21129[79:MRR:21127.0,20780.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.18 21131[79:Res:21129.0,61.1] always3(s49) || -> . % 76.01/76.18 21132[79:SSi:21131.0,50.0,738.0] || -> . % 76.01/76.18 21133[78:Spt:21132.0,20784.1,20786.0] || xuntil6(s47)* -> . % 76.01/76.18 21134[78:Spt:21132.0,20784.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.18 21137[78:Res:21134.0,61.1] always3(s47) || -> . % 76.01/76.18 21138[78:SSi:21137.0,736.0,20774.0] || -> . % 76.01/76.18 21139[76:Spt:21138.0,20768.2,20773.0] || xuntil6(s46)*+ -> . % 76.01/76.18 21140[76:Spt:21138.0,20768.0,20768.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.01/76.18 21141[76:Res:53.1,21140.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.01/76.18 21143[76:MRR:21141.0,20760.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.18 21145[76:Res:21143.0,61.1] always3(s47) || -> . % 76.01/76.18 21146[76:SSi:21145.0,736.0] || -> . % 76.01/76.18 21147[75:Spt:21146.0,20764.1,20766.0] || xuntil6(s45)* -> . % 76.01/76.18 21148[75:Spt:21146.0,20764.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.18 21151[75:Res:21148.0,61.1] always3(s45) || -> . % 76.01/76.18 21152[75:SSi:21151.0,734.0,20754.0] || -> . % 76.01/76.18 21153[73:Spt:21152.0,20751.2,20753.0] || xuntil6(s44)*+ -> . % 76.01/76.18 21154[73:Spt:21152.0,20751.0,20751.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.01/76.18 21155[73:Res:53.1,21154.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.01/76.18 21157[73:MRR:21155.0,20740.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.18 21160[73:Res:21157.0,61.1] always3(s45) || -> . % 76.01/76.18 21161[73:SSi:21160.0,734.0] || -> . % 76.01/76.18 21162[72:Spt:21161.0,20744.1,20749.0] || xuntil6(s43)* -> . % 76.01/76.18 21163[72:Spt:21161.0,20744.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.18 21166[72:Res:21163.0,61.1] always3(s43) || -> . % 76.01/76.18 21167[72:SSi:21166.0,732.0,20734.0] || -> . % 76.01/76.18 21168[70:Spt:21167.0,20725.2,20733.0] || xuntil6(s42)*+ -> . % 76.01/76.18 21169[70:Spt:21167.0,20725.0,20725.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.01/76.18 21170[70:Res:53.1,21169.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.01/76.18 21172[70:MRR:21170.0,20717.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.18 21174[70:Res:21172.0,61.1] always3(s43) || -> . % 76.01/76.18 21175[70:SSi:21174.0,732.0] || -> . % 76.01/76.18 21176[69:Spt:21175.0,20721.1,20723.0] || xuntil6(s41)* -> . % 76.01/76.18 21177[69:Spt:21175.0,20721.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.18 21180[69:Res:21177.0,61.1] always3(s41) || -> . % 76.01/76.18 21181[69:SSi:21180.0,730.0,20711.0] || -> . % 76.01/76.18 21182[67:Spt:21181.0,20705.2,20710.0] || xuntil6(s40)*+ -> . % 76.01/76.18 21183[67:Spt:21181.0,20705.0,20705.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.01/76.18 21184[67:Res:53.1,21183.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.01/76.18 21186[67:MRR:21184.0,20697.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.18 21189[67:Res:21186.0,61.1] always3(s41) || -> . % 76.01/76.18 21190[67:SSi:21189.0,730.0] || -> . % 76.01/76.18 21191[66:Spt:21190.0,20701.1,20703.0] || xuntil6(s39)* -> . % 76.01/76.18 21192[66:Spt:21190.0,20701.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.18 21195[66:Res:21192.0,61.1] always3(s39) || -> . % 76.01/76.18 21196[66:SSi:21195.0,728.0,20691.0] || -> . % 76.01/76.18 21197[64:Spt:21196.0,20688.2,20690.0] || xuntil6(s38)*+ -> . % 76.01/76.18 21198[64:Spt:21196.0,20688.0,20688.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.01/76.18 21199[64:Res:53.1,21198.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.01/76.18 21201[64:MRR:21199.0,20677.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.18 21203[64:Res:21201.0,61.1] always3(s39) || -> . % 76.01/76.18 21204[64:SSi:21203.0,728.0] || -> . % 76.01/76.18 21205[63:Spt:21204.0,20681.1,20686.0] || xuntil6(s37)* -> . % 76.01/76.18 21206[63:Spt:21204.0,20681.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.18 21209[63:Res:21206.0,61.1] always3(s37) || -> . % 76.01/76.18 21210[63:SSi:21209.0,726.0,20671.0] || -> . % 76.01/76.18 21211[61:Spt:21210.0,20662.2,20670.0] || xuntil6(s36)*+ -> . % 76.01/76.18 21212[61:Spt:21210.0,20662.0,20662.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.01/76.18 21213[61:Res:53.1,21212.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.01/76.18 21215[61:MRR:21213.0,20654.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.18 21217[61:Res:21215.0,61.1] always3(s37) || -> . % 76.01/76.18 21218[61:SSi:21217.0,726.0] || -> . % 76.01/76.18 21219[60:Spt:21218.0,20658.1,20660.0] || xuntil6(s35)* -> . % 76.01/76.18 21220[60:Spt:21218.0,20658.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.18 21223[60:Res:21220.0,61.1] always3(s35) || -> . % 76.01/76.18 21224[60:SSi:21223.0,724.0,20648.0] || -> . % 76.01/76.18 21225[58:Spt:21224.0,20642.2,20647.0] || xuntil6(s34)*+ -> . % 76.01/76.18 21226[58:Spt:21224.0,20642.0,20642.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.01/76.18 21227[58:Res:53.1,21226.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.01/76.18 21229[58:MRR:21227.0,20634.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.18 21231[58:Res:21229.0,61.1] always3(s35) || -> . % 76.01/76.18 21232[58:SSi:21231.0,724.0] || -> . % 76.01/76.18 21233[57:Spt:21232.0,20638.1,20640.0] || xuntil6(s33)* -> . % 76.01/76.18 21234[57:Spt:21232.0,20638.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.18 21237[57:Res:21234.0,61.1] always3(s33) || -> . % 76.01/76.18 21238[57:SSi:21237.0,722.0,20625.0] || -> . % 76.01/76.18 21239[55:Spt:21238.0,20615.2,20624.0] || xuntil6(s32)*+ -> . % 76.01/76.18 21240[55:Spt:21238.0,20615.0,20615.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.01/76.18 21241[55:Res:53.1,21240.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.01/76.18 21243[55:MRR:21241.0,20603.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.18 21245[55:Res:21243.0,61.1] always3(s33) || -> . % 76.01/76.18 21246[55:SSi:21245.0,722.0] || -> . % 76.01/76.18 21247[54:Spt:21246.0,20608.1,20613.0] || xuntil6(s31)* -> . % 76.01/76.18 21248[54:Spt:21246.0,20608.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.18 21251[54:Res:21248.0,61.1] always3(s31) || -> . % 76.01/76.18 21252[54:SSi:21251.0,720.0,20597.0] || -> . % 76.01/76.18 21253[52:Spt:21252.0,20588.2,20596.0] || xuntil6(s30)*+ -> . % 76.01/76.18 21254[52:Spt:21252.0,20588.0,20588.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.01/76.18 21255[52:Res:53.1,21254.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.01/76.18 21257[52:MRR:21255.0,20580.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.18 21259[52:Res:21257.0,61.1] always3(s31) || -> . % 76.01/76.18 21260[52:SSi:21259.0,720.0] || -> . % 76.01/76.18 21261[51:Spt:21260.0,20584.1,20586.0] || xuntil6(s29)* -> . % 76.01/76.18 21262[51:Spt:21260.0,20584.0] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.18 21265[51:Res:21262.0,61.1] always3(s29) || -> . % 76.01/76.18 21266[51:SSi:21265.0,718.0,20574.0] || -> . % 76.01/76.18 21267[49:Spt:21266.0,20568.2,20573.0] || xuntil6(s28)*+ -> . % 76.01/76.18 21268[49:Spt:21266.0,20568.0,20568.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.01/76.18 21269[49:Res:53.1,21268.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.01/76.18 21271[49:MRR:21269.0,20560.0] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.18 21273[49:Res:21271.0,61.1] always3(s29) || -> . % 76.01/76.18 21274[49:SSi:21273.0,718.0] || -> . % 76.01/76.18 21275[48:Spt:21274.0,20564.1,20566.0] || xuntil6(s27)* -> . % 76.01/76.18 21276[48:Spt:21274.0,20564.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.18 21279[48:Res:21276.0,61.1] always3(s27) || -> . % 76.01/76.18 21280[48:SSi:21279.0,716.0,20551.0] || -> . % 76.01/76.18 21281[46:Spt:21280.0,20549.2,20550.0] || xuntil6(s26)*+ -> . % 76.01/76.18 21282[46:Spt:21280.0,20549.0,20549.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.01/76.18 21283[46:Res:53.1,21282.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.01/76.18 21285[47:Spt:21283.0] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.18 21287[47:Res:21285.0,61.1] always3(s26) || -> . % 76.01/76.18 21288[47:SSi:21287.0,715.0,20548.0] || -> . % 76.01/76.18 21289[47:Spt:21288.0,21283.0,21285.0] || m_main_v_state(s26,c_busy)* -> . % 76.01/76.18 21290[47:Spt:21288.0,21283.1] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.18 21294[47:Res:21290.0,61.1] always3(s27) || -> . % 76.01/76.18 21295[47:SSi:21294.0,716.0] || -> . % 76.01/76.18 21296[45:Spt:21295.0,20543.2,20547.0] || xuntil6(s25)*+ -> . % 76.01/76.18 21297[45:Spt:21295.0,20543.0,20543.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.01/76.18 21298[45:Res:53.1,21297.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.01/76.18 21300[46:Spt:21298.0] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.18 21302[46:Res:21300.0,61.1] always3(s25) || -> . % 76.01/76.18 21303[46:SSi:21302.0,714.0,20542.0] || -> . % 76.01/76.18 21304[46:Spt:21303.0,21298.0,21300.0] || m_main_v_state(s25,c_busy)* -> . % 76.01/76.18 21305[46:Spt:21303.0,21298.1] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.18 21309[46:Res:21305.0,61.1] always3(s26) || -> . % 76.01/76.18 21310[46:SSi:21309.0,715.0] || -> . % 76.01/76.18 21311[44:Spt:21310.0,20540.2,20541.0] || xuntil6(s24)*+ -> . % 76.01/76.18 21312[44:Spt:21310.0,20540.0,20540.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.01/76.18 21313[44:Res:53.1,21312.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.01/76.18 21315[45:Spt:21313.0] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.18 21317[45:Res:21315.0,61.1] always3(s24) || -> . % 76.01/76.18 21318[45:SSi:21317.0,713.0,20539.0] || -> . % 76.01/76.18 21319[45:Spt:21318.0,21313.0,21315.0] || m_main_v_state(s24,c_busy)* -> . % 76.01/76.18 21320[45:Spt:21318.0,21313.1] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.18 21324[45:Res:21320.0,61.1] always3(s25) || -> . % 76.01/76.18 21325[45:SSi:21324.0,714.0] || -> . % 76.01/76.18 21326[43:Spt:21325.0,20534.2,20538.0] || xuntil6(s23)*+ -> . % 76.01/76.18 21327[43:Spt:21325.0,20534.0,20534.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.01/76.18 21328[43:Res:53.1,21327.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.01/76.18 21330[44:Spt:21328.0] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.18 21332[44:Res:21330.0,61.1] always3(s23) || -> . % 76.01/76.18 21333[44:SSi:21332.0,712.0,20533.0] || -> . % 76.01/76.18 21334[44:Spt:21333.0,21328.0,21330.0] || m_main_v_state(s23,c_busy)* -> . % 76.01/76.18 21335[44:Spt:21333.0,21328.1] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.18 21339[44:Res:21335.0,61.1] always3(s24) || -> . % 76.01/76.18 21340[44:SSi:21339.0,713.0] || -> . % 76.01/76.18 21341[42:Spt:21340.0,20531.2,20532.0] || xuntil6(s22)*+ -> . % 76.01/76.18 21342[42:Spt:21340.0,20531.0,20531.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.01/76.18 21343[42:Res:53.1,21342.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.01/76.18 21345[43:Spt:21343.0] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.18 21347[43:Res:21345.0,61.1] always3(s22) || -> . % 76.01/76.18 21348[43:SSi:21347.0,711.0,20530.0] || -> . % 76.01/76.18 21349[43:Spt:21348.0,21343.0,21345.0] || m_main_v_state(s22,c_busy)* -> . % 76.01/76.18 21350[43:Spt:21348.0,21343.1] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.18 21354[43:Res:21350.0,61.1] always3(s23) || -> . % 76.01/76.18 21355[43:SSi:21354.0,712.0] || -> . % 76.01/76.18 21356[41:Spt:21355.0,20525.2,20529.0] || xuntil6(s21)*+ -> . % 76.01/76.18 21357[41:Spt:21355.0,20525.0,20525.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.01/76.18 21358[41:Res:53.1,21357.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.01/76.18 21360[42:Spt:21358.0] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.18 21362[42:Res:21360.0,61.1] always3(s21) || -> . % 76.01/76.18 21363[42:SSi:21362.0,710.0,20524.0] || -> . % 76.01/76.18 21364[42:Spt:21363.0,21358.0,21360.0] || m_main_v_state(s21,c_busy)* -> . % 76.01/76.18 21365[42:Spt:21363.0,21358.1] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.18 21369[42:Res:21365.0,61.1] always3(s22) || -> . % 76.01/76.18 21370[42:SSi:21369.0,711.0] || -> . % 76.01/76.18 21371[40:Spt:21370.0,20522.2,20523.0] || xuntil6(s20)*+ -> . % 76.01/76.18 21372[40:Spt:21370.0,20522.0,20522.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.01/76.18 21373[40:Res:53.1,21372.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.01/76.18 21375[41:Spt:21373.0] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.18 21377[41:Res:21375.0,61.1] always3(s20) || -> . % 76.01/76.18 21378[41:SSi:21377.0,709.0,20521.0] || -> . % 76.01/76.18 21379[41:Spt:21378.0,21373.0,21375.0] || m_main_v_state(s20,c_busy)* -> . % 76.01/76.18 21380[41:Spt:21378.0,21373.1] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.18 21384[41:Res:21380.0,61.1] always3(s21) || -> . % 76.01/76.18 21385[41:SSi:21384.0,710.0] || -> . % 76.01/76.18 21386[39:Spt:21385.0,20516.2,20520.0] || xuntil6(s19)*+ -> . % 76.01/76.18 21387[39:Spt:21385.0,20516.0,20516.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.01/76.18 21388[39:Res:53.1,21387.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.01/76.18 21390[40:Spt:21388.0] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.18 21392[40:Res:21390.0,61.1] always3(s19) || -> . % 76.01/76.18 21393[40:SSi:21392.0,708.0,20515.0] || -> . % 76.01/76.18 21394[40:Spt:21393.0,21388.0,21390.0] || m_main_v_state(s19,c_busy)* -> . % 76.01/76.18 21395[40:Spt:21393.0,21388.1] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.18 21399[40:Res:21395.0,61.1] always3(s20) || -> . % 76.01/76.18 21400[40:SSi:21399.0,709.0] || -> . % 76.01/76.18 21401[38:Spt:21400.0,20513.2,20514.0] || xuntil6(s18)*+ -> . % 76.01/76.18 21402[38:Spt:21400.0,20513.0,20513.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.01/76.18 21403[38:Res:53.1,21402.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.01/76.18 21408[39:Spt:21403.0] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.18 21410[39:Res:21408.0,61.1] always3(s18) || -> . % 76.01/76.18 21411[39:SSi:21410.0,707.0,20512.0] || -> . % 76.01/76.18 21412[39:Spt:21411.0,21403.0,21408.0] || m_main_v_state(s18,c_busy)* -> . % 76.01/76.18 21413[39:Spt:21411.0,21403.1] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.18 21417[39:Res:21413.0,61.1] always3(s19) || -> . % 76.01/76.18 21418[39:SSi:21417.0,708.0] || -> . % 76.01/76.18 21419[37:Spt:21418.0,20507.2,20511.0] || xuntil6(s17)*+ -> . % 76.01/76.18 21420[37:Spt:21418.0,20507.0,20507.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.01/76.18 21421[37:Res:53.1,21420.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.01/76.18 21423[38:Spt:21421.0] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.18 21425[38:Res:21423.0,61.1] always3(s17) || -> . % 76.01/76.18 21426[38:SSi:21425.0,706.0,20506.0] || -> . % 76.01/76.18 21427[38:Spt:21426.0,21421.0,21423.0] || m_main_v_state(s17,c_busy)* -> . % 76.01/76.18 21428[38:Spt:21426.0,21421.1] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.18 21432[38:Res:21428.0,61.1] always3(s18) || -> . % 76.01/76.18 21433[38:SSi:21432.0,707.0] || -> . % 76.01/76.18 21434[36:Spt:21433.0,20504.2,20505.0] || xuntil6(s16)*+ -> . % 76.01/76.18 21435[36:Spt:21433.0,20504.0,20504.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.01/76.18 21436[36:Res:53.1,21435.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.01/76.18 21438[37:Spt:21436.1] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.18 21440[37:Res:21438.0,61.1] always3(s17) || -> . % 76.01/76.18 21441[37:SSi:21440.0,706.0] || -> . % 76.01/76.18 21442[37:Spt:21441.0,21436.1,21438.0] || m_main_v_state(s17,c_busy)* -> . % 76.01/76.18 21443[37:Spt:21441.0,21436.0] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.18 21446[37:Res:21443.0,61.1] always3(s16) || -> . % 76.01/76.18 21447[37:SSi:21446.0,705.0,20503.0] || -> . % 76.01/76.18 21448[35:Spt:21447.0,20498.2,20502.0] || xuntil6(s15)*+ -> . % 76.01/76.18 21449[35:Spt:21447.0,20498.0,20498.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.01/76.18 21450[35:Res:53.1,21449.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.01/76.18 21455[36:Spt:21450.0] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.18 21457[36:Res:21455.0,61.1] always3(s15) || -> . % 76.01/76.18 21458[36:SSi:21457.0,704.0,20497.0] || -> . % 76.01/76.18 21459[36:Spt:21458.0,21450.0,21455.0] || m_main_v_state(s15,c_busy)* -> . % 76.01/76.18 21460[36:Spt:21458.0,21450.1] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.18 21464[36:Res:21460.0,61.1] always3(s16) || -> . % 76.01/76.18 21465[36:SSi:21464.0,705.0] || -> . % 76.01/76.18 21466[34:Spt:21465.0,20495.2,20496.0] || xuntil6(s14)*+ -> . % 76.01/76.18 21467[34:Spt:21465.0,20495.0,20495.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.01/76.18 21468[34:Res:53.1,21467.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.01/76.18 21470[35:Spt:21468.1] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.18 21472[35:Res:21470.0,61.1] always3(s15) || -> . % 76.01/76.18 21473[35:SSi:21472.0,704.0] || -> . % 76.01/76.18 21474[35:Spt:21473.0,21468.1,21470.0] || m_main_v_state(s15,c_busy)* -> . % 76.01/76.18 21475[35:Spt:21473.0,21468.0] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.18 21478[35:Res:21475.0,61.1] always3(s14) || -> . % 76.01/76.18 21479[35:SSi:21478.0,703.0,20494.0] || -> . % 76.01/76.18 21480[33:Spt:21479.0,20489.2,20493.0] || xuntil6(s13)*+ -> . % 76.01/76.18 21481[33:Spt:21479.0,20489.0,20489.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.01/76.18 21482[33:Res:53.1,21481.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.01/76.18 21484[34:Spt:21482.1] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.18 21486[34:Res:21484.0,61.1] always3(s14) || -> . % 76.01/76.18 21487[34:SSi:21486.0,703.0] || -> . % 76.01/76.18 21488[34:Spt:21487.0,21482.1,21484.0] || m_main_v_state(s14,c_busy)* -> . % 76.01/76.18 21489[34:Spt:21487.0,21482.0] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.18 21492[34:Res:21489.0,61.1] always3(s13) || -> . % 76.01/76.18 21493[34:SSi:21492.0,702.0,20488.0] || -> . % 76.01/76.18 21494[32:Spt:21493.0,20486.2,20487.0] || xuntil6(s12)*+ -> . % 76.01/76.18 21495[32:Spt:21493.0,20486.0,20486.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.01/76.18 21496[32:Res:53.1,21495.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.01/76.18 21501[33:Spt:21496.0] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.18 21503[33:Res:21501.0,61.1] always3(s12) || -> . % 76.01/76.18 21504[33:SSi:21503.0,701.0,20485.0] || -> . % 76.01/76.18 21505[33:Spt:21504.0,21496.0,21501.0] || m_main_v_state(s12,c_busy)* -> . % 76.01/76.18 21506[33:Spt:21504.0,21496.1] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.18 21510[33:Res:21506.0,61.1] always3(s13) || -> . % 76.01/76.18 21511[33:SSi:21510.0,702.0] || -> . % 76.01/76.18 21512[31:Spt:21511.0,20480.2,20484.0] || xuntil6(s11)*+ -> . % 76.01/76.18 21513[31:Spt:21511.0,20480.0,20480.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.01/76.18 21514[31:Res:53.1,21513.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.01/76.18 21516[32:Spt:21514.1] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.18 21518[32:Res:21516.0,61.1] always3(s12) || -> . % 76.01/76.18 21519[32:SSi:21518.0,701.0] || -> . % 76.01/76.18 21520[32:Spt:21519.0,21514.1,21516.0] || m_main_v_state(s12,c_busy)* -> . % 76.01/76.18 21521[32:Spt:21519.0,21514.0] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.18 21524[32:Res:21521.0,61.1] always3(s11) || -> . % 76.01/76.18 21525[32:SSi:21524.0,700.0,20479.0] || -> . % 76.01/76.18 21526[30:Spt:21525.0,20477.2,20478.0] || xuntil6(s10)*+ -> . % 76.01/76.18 21527[30:Spt:21525.0,20477.0,20477.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.01/76.18 21528[30:Res:53.1,21527.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.01/76.18 21530[31:Spt:21528.1] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.18 21532[31:Res:21530.0,61.1] always3(s11) || -> . % 76.01/76.18 21533[31:SSi:21532.0,700.0] || -> . % 76.01/76.18 21534[31:Spt:21533.0,21528.1,21530.0] || m_main_v_state(s11,c_busy)* -> . % 76.01/76.18 21535[31:Spt:21533.0,21528.0] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.18 21538[31:Res:21535.0,61.1] always3(s10) || -> . % 76.01/76.18 21539[31:SSi:21538.0,699.0,20476.0] || -> . % 76.01/76.18 21540[29:Spt:21539.0,20471.2,20475.0] || xuntil6(s9)*+ -> . % 76.01/76.18 21541[29:Spt:21539.0,20471.0,20471.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.01/76.18 21542[29:Res:53.1,21541.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.01/76.18 21547[30:Spt:21542.0] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.18 21549[30:Res:21547.0,61.1] always3(s9) || -> . % 76.01/76.18 21550[30:SSi:21549.0,698.0,20470.0] || -> . % 76.01/76.18 21551[30:Spt:21550.0,21542.0,21547.0] || m_main_v_state(s9,c_busy)* -> . % 76.01/76.18 21552[30:Spt:21550.0,21542.1] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.18 21556[30:Res:21552.0,61.1] always3(s10) || -> . % 76.01/76.18 21557[30:SSi:21556.0,699.0] || -> . % 76.01/76.18 21558[28:Spt:21557.0,20468.2,20469.0] || xuntil6(s8)*+ -> . % 76.01/76.18 21559[28:Spt:21557.0,20468.0,20468.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.01/76.18 21560[28:Res:53.1,21559.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.01/76.18 21562[29:Spt:21560.1] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.18 21564[29:Res:21562.0,61.1] always3(s9) || -> . % 76.01/76.18 21565[29:SSi:21564.0,698.0] || -> . % 76.01/76.18 21566[29:Spt:21565.0,21560.1,21562.0] || m_main_v_state(s9,c_busy)* -> . % 76.01/76.18 21567[29:Spt:21565.0,21560.0] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.18 21570[29:Res:21567.0,61.1] always3(s8) || -> . % 76.01/76.18 21571[29:SSi:21570.0,697.0,20467.0] || -> . % 76.01/76.18 21572[27:Spt:21571.0,20462.2,20466.0] || xuntil6(s7)*+ -> . % 76.01/76.18 21573[27:Spt:21571.0,20462.0,20462.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.01/76.18 21574[27:Res:53.1,21573.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.01/76.18 21576[28:Spt:21574.1] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.18 21578[28:Res:21576.0,61.1] always3(s8) || -> . % 76.01/76.18 21579[28:SSi:21578.0,697.0] || -> . % 76.01/76.18 21580[28:Spt:21579.0,21574.1,21576.0] || m_main_v_state(s8,c_busy)* -> . % 76.01/76.18 21581[28:Spt:21579.0,21574.0] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.18 21584[28:Res:21581.0,61.1] always3(s7) || -> . % 76.01/76.18 21585[28:SSi:21584.0,696.0,20461.0] || -> . % 76.01/76.18 21586[26:Spt:21585.0,20459.2,20460.0] || xuntil6(s6)*+ -> . % 76.01/76.18 21587[26:Spt:21585.0,20459.0,20459.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.01/76.18 21588[26:Res:53.1,21587.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.01/76.18 21593[27:Spt:21588.0] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.18 21595[27:Res:21593.0,61.1] always3(s6) || -> . % 76.01/76.18 21596[27:SSi:21595.0,695.0,20458.0] || -> . % 76.01/76.18 21597[27:Spt:21596.0,21588.0,21593.0] || m_main_v_state(s6,c_busy)* -> . % 76.01/76.18 21598[27:Spt:21596.0,21588.1] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.18 21602[27:Res:21598.0,61.1] always3(s7) || -> . % 76.01/76.18 21603[27:SSi:21602.0,696.0] || -> . % 76.01/76.18 21604[25:Spt:21603.0,20453.2,20457.0] || xuntil6(s5)*+ -> . % 76.01/76.18 21605[25:Spt:21603.0,20453.0,20453.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.01/76.18 21606[25:Res:53.1,21605.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.01/76.18 21608[26:Spt:21606.1] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.18 21610[26:Res:21608.0,61.1] always3(s6) || -> . % 76.01/76.18 21611[26:SSi:21610.0,695.0] || -> . % 76.01/76.18 21612[26:Spt:21611.0,21606.1,21608.0] || m_main_v_state(s6,c_busy)* -> . % 76.01/76.18 21613[26:Spt:21611.0,21606.0] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.18 21616[26:Res:21613.0,61.1] always3(s5) || -> . % 76.01/76.18 21617[26:SSi:21616.0,694.0,20452.0] || -> . % 76.01/76.18 21618[24:Spt:21617.0,20450.2,20451.0] || xuntil6(s4)*+ -> . % 76.01/76.18 21619[24:Spt:21617.0,20450.0,20450.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.01/76.18 21620[24:Res:53.1,21619.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.01/76.18 21622[25:Spt:21620.1] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.18 21624[25:Res:21622.0,61.1] always3(s5) || -> . % 76.01/76.18 21625[25:SSi:21624.0,694.0] || -> . % 76.01/76.18 21626[25:Spt:21625.0,21620.1,21622.0] || m_main_v_state(s5,c_busy)* -> . % 76.01/76.18 21627[25:Spt:21625.0,21620.0] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.18 21630[25:Res:21627.0,61.1] always3(s4) || -> . % 76.01/76.18 21631[25:SSi:21630.0,693.0,20449.0] || -> . % 76.01/76.18 21632[23:Spt:21631.0,20444.2,20448.0] || xuntil6(s3)*+ -> . % 76.01/76.18 21633[23:Spt:21631.0,20444.0,20444.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.01/76.18 21634[23:Res:53.1,21633.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.01/76.18 21639[24:Spt:21634.0] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.18 21641[24:Res:21639.0,61.1] always3(s3) || -> . % 76.01/76.18 21642[24:SSi:21641.0,692.0,20443.0] || -> . % 76.01/76.18 21643[24:Spt:21642.0,21634.0,21639.0] || m_main_v_state(s3,c_busy)* -> . % 76.01/76.18 21644[24:Spt:21642.0,21634.1] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.18 21648[24:Res:21644.0,61.1] always3(s4) || -> . % 76.01/76.18 21649[24:SSi:21648.0,693.0] || -> . % 76.01/76.18 21650[22:Spt:21649.0,20441.2,20442.0] || xuntil6(s2)*+ -> . % 76.01/76.18 21651[22:Spt:21649.0,20441.0,20441.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.01/76.18 21652[22:Res:53.1,21651.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.01/76.18 21654[23:Spt:21652.1] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.18 21656[23:Res:21654.0,61.1] always3(s3) || -> . % 76.01/76.18 21657[23:SSi:21656.0,692.0] || -> . % 76.01/76.18 21658[23:Spt:21657.0,21652.1,21654.0] || m_main_v_state(s3,c_busy)* -> . % 76.01/76.18 21659[23:Spt:21657.0,21652.0] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.18 21662[23:Res:21659.0,61.1] always3(s2) || -> . % 76.01/76.18 21663[23:SSi:21662.0,691.0,20440.0] || -> . % 76.01/76.18 21664[21:Spt:21663.0,20432.2,20439.0] || xuntil6(s1)*+ -> . % 76.01/76.18 21665[21:Spt:21663.0,20432.0,20432.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.01/76.18 21666[21:Res:53.1,21665.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.01/76.18 21668[22:Spt:21666.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.18 21670[22:Res:21668.0,61.1] always3(s1) || -> . % 76.01/76.18 21671[22:SSi:21670.0,690.0,20431.0] || -> . % 76.01/76.18 21672[22:Spt:21671.0,21666.0,21668.0] || m_main_v_state(s1,c_busy)* -> . % 76.01/76.18 21673[22:Spt:21671.0,21666.1] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.18 21678[22:Res:21673.0,61.1] always3(s2) || -> . % 76.01/76.18 21679[22:SSi:21678.0,691.0] || -> . % 76.01/76.18 21680[20:Spt:21679.0,74.0,20430.0] || xuntil6(s0)*+ -> . % 76.01/76.18 21681[20:Spt:21679.0,74.1] || -> node4(s0)*. % 76.01/76.18 21682[20:MRR:758.1,21680.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.18 21684[20:Res:21682.0,61.1] always3(s1) || -> . % 76.01/76.18 21685[20:SSi:21684.0,690.0] || -> . % 76.01/76.18 21686[19:Spt:21685.0,20420.0,20424.0] || trans(s49,s32)*+ -> . % 76.01/76.18 21687[19:Spt:21685.0,20420.1,20420.2,20420.3,20420.4,20420.5,20420.6,20420.7,20420.8,20420.9,20420.10,20420.11,20420.12,20420.13,20420.14,20420.15,20420.16,20420.17,20420.18,20420.19,20420.20,20420.21,20420.22,20420.23,20420.24,20420.25,20420.26,20420.27,20420.28,20420.29,20420.30,20420.31,20420.32] || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.01/76.18 21689[19:MRR:20421.0,21686.0] || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.01/76.18 21690[19:MRR:20423.1,21686.0] xuntil6(s49) || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.01/76.18 21691[20:Spt:21687.0] || -> trans(s49,s31)*. % 76.01/76.18 21692[20:Res:21691.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s31)*. % 76.01/76.18 21694[20:Res:21691.0,60.0] || -> node2(s49,s31)*. % 76.01/76.18 21695[20:SSi:21692.1,50.0,738.0] xuntil6(s49) || -> until2p7(s31)*. % 76.01/76.18 21696[20:Res:21694.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.01/76.18 21697[21:Spt:74.0] || -> xuntil6(s0)*. % 76.01/76.18 21698[21:MRR:176.0,21697.0] || -> until5(s1)*. % 76.01/76.18 21699[21:MRR:19446.0,21698.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.18 21703[22:Spt:21699.2] || -> xuntil6(s1)*. % 76.01/76.18 21704[22:MRR:175.0,21703.0] || -> until5(s2)*. % 76.01/76.18 21705[22:MRR:19442.0,21704.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.18 21709[23:Spt:21705.2] || -> xuntil6(s2)*. % 76.01/76.18 21710[23:MRR:174.0,21709.0] || -> until5(s3)*. % 76.01/76.18 21711[23:MRR:19441.0,21710.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.18 21712[24:Spt:21711.2] || -> xuntil6(s3)*. % 76.01/76.18 21713[24:MRR:173.0,21712.0] || -> until5(s4)*. % 76.01/76.18 21714[24:MRR:19434.0,21713.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.18 21718[25:Spt:21714.2] || -> xuntil6(s4)*. % 76.01/76.18 21719[25:MRR:172.0,21718.0] || -> until5(s5)*. % 76.01/76.18 21720[25:MRR:19430.0,21719.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.18 21721[26:Spt:21720.2] || -> xuntil6(s5)*. % 76.01/76.18 21722[26:MRR:171.0,21721.0] || -> until5(s6)*. % 76.01/76.18 21723[26:MRR:19426.0,21722.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.18 21727[27:Spt:21723.2] || -> xuntil6(s6)*. % 76.01/76.18 21728[27:MRR:170.0,21727.0] || -> until5(s7)*. % 76.01/76.18 21729[27:MRR:19422.0,21728.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.18 21730[28:Spt:21729.2] || -> xuntil6(s7)*. % 76.01/76.18 21731[28:MRR:169.0,21730.0] || -> until5(s8)*. % 76.01/76.18 21732[28:MRR:19421.0,21731.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.18 21736[29:Spt:21732.2] || -> xuntil6(s8)*. % 76.01/76.18 21737[29:MRR:168.0,21736.0] || -> until5(s9)*. % 76.01/76.18 21738[29:MRR:19414.0,21737.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.18 21739[30:Spt:21738.2] || -> xuntil6(s9)*. % 76.01/76.18 21740[30:MRR:167.0,21739.0] || -> until5(s10)*. % 76.01/76.18 21741[30:MRR:19410.0,21740.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.18 21745[31:Spt:21741.2] || -> xuntil6(s10)*. % 76.01/76.18 21746[31:MRR:166.0,21745.0] || -> until5(s11)*. % 76.01/76.18 21747[31:MRR:19406.0,21746.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.18 21748[32:Spt:21747.2] || -> xuntil6(s11)*. % 76.01/76.18 21749[32:MRR:165.0,21748.0] || -> until5(s12)*. % 76.01/76.18 21750[32:MRR:19402.0,21749.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.18 21754[33:Spt:21750.2] || -> xuntil6(s12)*. % 76.01/76.18 21755[33:MRR:164.0,21754.0] || -> until5(s13)*. % 76.01/76.18 21756[33:MRR:19401.0,21755.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.18 21757[34:Spt:21756.2] || -> xuntil6(s13)*. % 76.01/76.18 21758[34:MRR:163.0,21757.0] || -> until5(s14)*. % 76.01/76.18 21759[34:MRR:19394.0,21758.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.18 21763[35:Spt:21759.2] || -> xuntil6(s14)*. % 76.01/76.18 21764[35:MRR:162.0,21763.0] || -> until5(s15)*. % 76.01/76.18 21765[35:MRR:19390.0,21764.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.18 21766[36:Spt:21765.2] || -> xuntil6(s15)*. % 76.01/76.18 21767[36:MRR:161.0,21766.0] || -> until5(s16)*. % 76.01/76.18 21768[36:MRR:19386.0,21767.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.18 21772[37:Spt:21768.2] || -> xuntil6(s16)*. % 76.01/76.18 21773[37:MRR:160.0,21772.0] || -> until5(s17)*. % 76.01/76.18 21774[37:MRR:19382.0,21773.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.18 21775[38:Spt:21774.2] || -> xuntil6(s17)*. % 76.01/76.18 21776[38:MRR:159.0,21775.0] || -> until5(s18)*. % 76.01/76.18 21777[38:MRR:19381.0,21776.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.18 21781[39:Spt:21777.2] || -> xuntil6(s18)*. % 76.01/76.18 21782[39:MRR:158.0,21781.0] || -> until5(s19)*. % 76.01/76.18 21783[39:MRR:19374.0,21782.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.18 21784[40:Spt:21783.2] || -> xuntil6(s19)*. % 76.01/76.18 21785[40:MRR:157.0,21784.0] || -> until5(s20)*. % 76.01/76.18 21786[40:MRR:19370.0,21785.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.18 21790[41:Spt:21786.2] || -> xuntil6(s20)*. % 76.01/76.18 21791[41:MRR:156.0,21790.0] || -> until5(s21)*. % 76.01/76.18 21792[41:MRR:19366.0,21791.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.18 21793[42:Spt:21792.2] || -> xuntil6(s21)*. % 76.01/76.18 21794[42:MRR:155.0,21793.0] || -> until5(s22)*. % 76.01/76.18 21795[42:MRR:19362.0,21794.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.18 21799[43:Spt:21795.2] || -> xuntil6(s22)*. % 76.01/76.18 21800[43:MRR:154.0,21799.0] || -> until5(s23)*. % 76.01/76.18 21801[43:MRR:19361.0,21800.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.18 21802[44:Spt:21801.2] || -> xuntil6(s23)*. % 76.01/76.18 21803[44:MRR:153.0,21802.0] || -> until5(s24)*. % 76.01/76.18 21804[44:MRR:19354.0,21803.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.18 21808[45:Spt:21804.2] || -> xuntil6(s24)*. % 76.01/76.18 21809[45:MRR:152.0,21808.0] || -> until5(s25)*. % 76.01/76.18 21810[45:MRR:19350.0,21809.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.18 21811[46:Spt:21810.2] || -> xuntil6(s25)*. % 76.01/76.18 21812[46:MRR:151.0,21811.0] || -> until5(s26)*. % 76.01/76.18 21813[46:MRR:19346.0,21812.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.18 21817[47:Spt:21813.2] || -> xuntil6(s26)*. % 76.01/76.18 21818[47:MRR:150.0,21817.0] || -> until5(s27)*. % 76.01/76.18 21819[47:MRR:19342.0,21818.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.18 21820[48:Spt:21819.2] || -> xuntil6(s27)*. % 76.01/76.18 21821[48:MRR:149.0,21820.0] || -> until5(s28)*. % 76.01/76.18 21822[48:MRR:19334.0,21821.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.18 21826[49:Spt:21822.2] || -> xuntil6(s28)*. % 76.01/76.18 21827[49:MRR:148.0,21826.0] || -> until5(s29)*. % 76.01/76.18 21828[49:MRR:19341.0,21827.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.18 21829[50:Spt:21828.2] || -> xuntil6(s29)*. % 76.01/76.18 21830[50:MRR:147.0,21829.0] || -> until5(s30)*. % 76.01/76.18 21831[50:MRR:19326.0,21830.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.18 21835[51:Spt:21831.2] || -> xuntil6(s30)*. % 76.01/76.18 21836[51:MRR:146.0,21835.0] || -> until5(s31)*. % 76.01/76.18 21837[51:MRR:19330.0,21836.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.18 21838[52:Spt:21837.2] || -> xuntil6(s31)*. % 76.01/76.18 21839[52:MRR:145.0,21838.0] || -> until5(s32)*. % 76.01/76.18 21840[52:MRR:19324.0,21839.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.18 21844[53:Spt:21840.1] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.18 21846[53:Res:21844.0,61.1] always3(s33) || -> . % 76.01/76.18 21847[53:SSi:21846.0,722.0] || -> . % 76.01/76.18 21848[53:Spt:21847.0,21840.1,21844.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.01/76.18 21849[53:Spt:21847.0,21840.0,21840.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 76.01/76.18 21851[53:MRR:822.2,21848.0] node4(s32) || m_main_v_state(s32,c_ready)* -> . % 76.01/76.18 21852[53:Res:53.1,21849.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 76.01/76.18 21854[54:Spt:21852.1] || -> xuntil6(s32)*. % 76.01/76.18 21855[54:MRR:144.0,21854.0] || -> until5(s33)*. % 76.01/76.18 21856[54:MRR:19325.0,21855.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.18 21861[55:Spt:21856.2] || -> xuntil6(s33)*. % 76.01/76.18 21862[55:MRR:143.0,21861.0] || -> until5(s34)*. % 76.01/76.18 21863[55:MRR:16857.0,21862.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.18 21864[56:Spt:21863.1] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.18 21866[56:Res:21864.0,61.1] always3(s35) || -> . % 76.01/76.18 21867[56:SSi:21866.0,724.0] || -> . % 76.01/76.18 21868[56:Spt:21867.0,21863.1,21864.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.01/76.18 21869[56:Spt:21867.0,21863.0,21863.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 76.01/76.18 21871[56:MRR:816.2,21868.0] node4(s34) || m_main_v_state(s34,c_ready)* -> . % 76.01/76.18 21872[56:Res:53.1,21869.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 76.01/76.18 21874[57:Spt:21872.1] || -> xuntil6(s34)*. % 76.01/76.18 21875[57:MRR:142.0,21874.0] || -> until5(s35)*. % 76.01/76.18 21876[57:MRR:19450.0,21875.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.18 21884[58:Spt:21876.2] || -> xuntil6(s35)*. % 76.01/76.18 21885[58:MRR:141.0,21884.0] || -> until5(s36)*. % 76.01/76.18 21886[58:MRR:16858.0,21885.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.18 21887[59:Spt:21886.1] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.18 21889[59:Res:21887.0,61.1] always3(s37) || -> . % 76.01/76.18 21890[59:SSi:21889.0,726.0] || -> . % 76.01/76.18 21891[59:Spt:21890.0,21886.1,21887.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.01/76.18 21892[59:Spt:21890.0,21886.0,21886.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 76.01/76.18 21894[59:MRR:810.2,21891.0] node4(s36) || m_main_v_state(s36,c_ready)* -> . % 76.01/76.18 21895[59:Res:53.1,21892.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 76.01/76.18 21900[60:Spt:21895.1] || -> xuntil6(s36)*. % 76.01/76.18 21901[60:MRR:140.0,21900.0] || -> until5(s37)*. % 76.01/76.18 21902[60:MRR:19454.0,21901.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.18 21904[61:Spt:21902.2] || -> xuntil6(s37)*. % 76.01/76.18 21905[61:MRR:139.0,21904.0] || -> until5(s38)*. % 76.01/76.18 21906[61:MRR:16862.0,21905.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.18 21907[62:Spt:21906.1] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.18 21909[62:Res:21907.0,61.1] always3(s39) || -> . % 76.01/76.18 21910[62:SSi:21909.0,728.0] || -> . % 76.01/76.18 21911[62:Spt:21910.0,21906.1,21907.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.01/76.18 21912[62:Spt:21910.0,21906.0,21906.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 76.01/76.18 21914[62:MRR:804.2,21911.0] node4(s38) || m_main_v_state(s38,c_ready)* -> . % 76.01/76.18 21915[62:Res:53.1,21912.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 76.01/76.18 21917[63:Spt:21915.1] || -> xuntil6(s38)*. % 76.01/76.18 21918[63:MRR:138.0,21917.0] || -> until5(s39)*. % 76.01/76.18 21919[63:MRR:19461.0,21918.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.18 21924[64:Spt:21919.2] || -> xuntil6(s39)*. % 76.01/76.18 21925[64:MRR:137.0,21924.0] || -> until5(s40)*. % 76.01/76.18 21926[64:MRR:16866.0,21925.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.01/76.18 21927[65:Spt:21926.1] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.18 21929[65:Res:21927.0,61.1] always3(s41) || -> . % 76.01/76.18 21930[65:SSi:21929.0,730.0] || -> . % 76.01/76.18 21931[65:Spt:21930.0,21926.1,21927.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.01/76.18 21932[65:Spt:21930.0,21926.0,21926.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 76.01/76.18 21934[65:MRR:798.2,21931.0] node4(s40) || m_main_v_state(s40,c_ready)* -> . % 76.01/76.18 21935[65:Res:53.1,21932.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 76.01/76.18 21937[66:Spt:21935.1] || -> xuntil6(s40)*. % 76.01/76.18 21938[66:MRR:136.0,21937.0] || -> until5(s41)*. % 76.01/76.18 21939[66:MRR:19462.0,21938.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.18 21947[67:Spt:21939.2] || -> xuntil6(s41)*. % 76.01/76.18 21948[67:MRR:135.0,21947.0] || -> until5(s42)*. % 76.01/76.18 21949[67:MRR:16870.0,21948.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.01/76.18 21950[68:Spt:21949.1] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.18 21952[68:Res:21950.0,61.1] always3(s43) || -> . % 76.01/76.18 21953[68:SSi:21952.0,732.0] || -> . % 76.01/76.18 21954[68:Spt:21953.0,21949.1,21950.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.01/76.18 21955[68:Spt:21953.0,21949.0,21949.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 76.01/76.18 21957[68:MRR:792.2,21954.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 76.01/76.18 21958[68:Res:53.1,21955.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 76.01/76.18 21963[69:Spt:21958.1] || -> xuntil6(s42)*. % 76.01/76.18 21964[69:MRR:134.0,21963.0] || -> until5(s43)*. % 76.01/76.18 21965[69:MRR:19466.0,21964.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.18 21967[70:Spt:21965.2] || -> xuntil6(s43)*. % 76.01/76.18 21968[70:MRR:133.0,21967.0] || -> until5(s44)*. % 76.01/76.18 21969[70:MRR:16877.0,21968.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.01/76.18 21970[71:Spt:21969.1] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.18 21972[71:Res:21970.0,61.1] always3(s45) || -> . % 76.01/76.18 21973[71:SSi:21972.0,734.0] || -> . % 76.01/76.18 21974[71:Spt:21973.0,21969.1,21970.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.01/76.18 21975[71:Spt:21973.0,21969.0,21969.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 76.01/76.18 21977[71:MRR:786.2,21974.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 76.01/76.18 21978[71:Res:53.1,21975.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 76.01/76.18 21980[72:Spt:21978.1] || -> xuntil6(s44)*. % 76.01/76.18 21981[72:MRR:132.0,21980.0] || -> until5(s45)*. % 76.01/76.18 21982[72:MRR:19470.0,21981.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.18 21987[73:Spt:21982.2] || -> xuntil6(s45)*. % 76.01/76.18 21988[73:MRR:131.0,21987.0] || -> until5(s46)*. % 76.01/76.18 21989[73:MRR:16878.0,21988.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.01/76.18 21990[74:Spt:21989.1] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.18 21992[74:Res:21990.0,61.1] always3(s47) || -> . % 76.01/76.18 21993[74:SSi:21992.0,736.0] || -> . % 76.01/76.18 21994[74:Spt:21993.0,21989.1,21990.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.01/76.18 21995[74:Spt:21993.0,21989.0,21989.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 76.01/76.18 21997[74:MRR:780.2,21994.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 76.01/76.18 21998[74:Res:53.1,21995.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 76.01/76.18 22000[75:Spt:21998.1] || -> xuntil6(s46)*. % 76.01/76.18 22001[75:MRR:130.0,22000.0] || -> until5(s47)*. % 76.01/76.18 22002[75:MRR:19474.0,22001.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.18 22010[76:Spt:22002.2] || -> xuntil6(s47)*. % 76.01/76.18 22011[76:MRR:129.0,22010.0] || -> until5(s48)*. % 76.01/76.18 22012[76:MRR:16882.0,22011.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.01/76.18 22013[77:Spt:22012.1] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.18 22015[77:Res:22013.0,61.1] always3(s49) || -> . % 76.01/76.18 22016[77:SSi:22015.0,50.0,738.0] || -> . % 76.01/76.18 22017[77:Spt:22016.0,22012.1,22013.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.01/76.18 22018[77:Spt:22016.0,22012.0,22012.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 76.01/76.18 22020[77:MRR:774.2,22017.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.01/76.18 22021[77:Res:53.1,22018.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 76.01/76.18 22026[78:Spt:22021.1] || -> xuntil6(s48)*. % 76.01/76.18 22027[78:MRR:128.0,22026.0] || -> until5(s49)*. % 76.01/76.18 22029[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.18 22033[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.18 22034[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.18 22035[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.18 22042[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.18 22043[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.18 22047[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.18 22051[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.18 22055[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.18 22062[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.18 22063[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.18 22067[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.18 22071[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.18 22075[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.18 22082[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.18 22083[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.18 22087[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.18 22091[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.18 22095[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.18 22102[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.18 22103[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.18 22107[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.18 22111[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.18 22115[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.18 22122[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.18 22123[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.18 22127[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.18 22131[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.18 22135[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.18 22142[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.18 22143[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.18 22147[0:SoR:819.0,66.2] until5(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.18 22151[0:SoR:813.0,66.2] until5(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.18 22155[0:SoR:807.0,66.2] until5(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.18 22162[0:SoR:801.0,66.2] until5(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.18 22163[0:SoR:795.0,66.2] until5(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.18 22167[0:SoR:789.0,66.2] until5(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.18 22171[0:SoR:783.0,66.2] until5(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.18 22175[0:SoR:777.0,66.2] until5(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.18 22177[20:SoR:21696.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.01/76.18 22179[20:SoR:22177.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.01/76.18 22180[78:SSi:22179.0,50.0,738.0,22027.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.01/76.18 22181[79:Spt:22180.1] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.18 22183[79:Res:22181.0,61.1] always3(s31) || -> . % 76.01/76.18 22184[79:SSi:22183.0,720.0,21836.0,21838.0] || -> . % 76.01/76.18 22185[79:Spt:22184.0,22180.1,22181.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.01/76.18 22186[79:Spt:22184.0,22180.0,22180.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.01/76.18 22190[79:MRR:22177.2,22185.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.01/76.18 22191[79:Res:53.1,22186.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.01/76.18 22193[79:MRR:22191.0,22017.0] || -> xuntil6(s49)*. % 76.01/76.18 22194[79:MRR:21695.0,22193.0] || -> until2p7(s31)*. % 76.01/76.18 22195[79:MRR:227.0,22194.0] || -> until2p7(s32)* node4(s31). % 76.01/76.18 22196[80:Spt:22195.0] || -> until2p7(s32)*. % 76.01/76.18 22197[80:MRR:228.0,22196.0] || -> until2p7(s33)* node4(s32). % 76.01/76.18 22198[81:Spt:22197.0] || -> until2p7(s33)*. % 76.01/76.18 22199[81:MRR:229.0,22198.0] || -> until2p7(s34)* node4(s33). % 76.01/76.18 22200[82:Spt:22199.0] || -> until2p7(s34)*. % 76.01/76.18 22201[82:MRR:230.0,22200.0] || -> until2p7(s35)* node4(s34). % 76.01/76.18 22202[83:Spt:22201.0] || -> until2p7(s35)*. % 76.01/76.18 22203[83:MRR:231.0,22202.0] || -> until2p7(s36)* node4(s35). % 76.01/76.18 22204[84:Spt:22203.0] || -> until2p7(s36)*. % 76.01/76.18 22205[84:MRR:232.0,22204.0] || -> until2p7(s37)* node4(s36). % 76.01/76.18 22206[85:Spt:22205.0] || -> until2p7(s37)*. % 76.01/76.18 22207[85:MRR:235.0,22206.0] || -> until2p7(s38)* node4(s37). % 76.01/76.18 22208[86:Spt:22207.0] || -> until2p7(s38)*. % 76.01/76.18 22209[86:MRR:236.0,22208.0] || -> until2p7(s39)* node4(s38). % 76.01/76.18 22210[87:Spt:22209.0] || -> until2p7(s39)*. % 76.01/76.18 22211[87:MRR:237.0,22210.0] || -> until2p7(s40)* node4(s39). % 76.01/76.18 22212[88:Spt:22211.0] || -> until2p7(s40)*. % 76.01/76.18 22213[88:MRR:238.0,22212.0] || -> until2p7(s41)* node4(s40). % 76.01/76.18 22214[89:Spt:22213.0] || -> until2p7(s41)*. % 76.01/76.18 22215[89:MRR:239.0,22214.0] || -> until2p7(s42)* node4(s41). % 76.01/76.18 22216[90:Spt:22215.0] || -> until2p7(s42)*. % 76.01/76.18 22217[90:MRR:240.0,22216.0] || -> until2p7(s43)* node4(s42). % 76.01/76.18 22218[91:Spt:22217.0] || -> until2p7(s43)*. % 76.01/76.18 22219[91:MRR:241.0,22218.0] || -> until2p7(s44)* node4(s43). % 76.01/76.18 22220[92:Spt:22219.0] || -> until2p7(s44)*. % 76.01/76.18 22221[92:MRR:539.0,22220.0] || -> until2p7(s45)* node4(s44). % 76.01/76.18 22222[93:Spt:22221.0] || -> until2p7(s45)*. % 76.01/76.18 22223[93:MRR:544.0,22222.0] || -> until2p7(s46)* node4(s45). % 76.01/76.18 22224[94:Spt:22223.0] || -> until2p7(s46)*. % 76.01/76.18 22225[94:MRR:549.0,22224.0] || -> until2p7(s47)* node4(s46). % 76.01/76.18 22226[95:Spt:22225.0] || -> until2p7(s47)*. % 76.01/76.18 22227[95:MRR:554.0,22226.0] || -> until2p7(s48)* node4(s47). % 76.01/76.18 22228[96:Spt:22227.0] || -> until2p7(s48)*. % 76.01/76.18 22229[96:MRR:559.0,22228.0] || -> until2p7(s49)* node4(s48). % 76.01/76.18 22230[97:Spt:22229.0] || -> until2p7(s49)*. % 76.01/76.18 22231[97:MRR:194.0,22230.0] || -> node4(s49)*. % 76.01/76.18 22232[97:MRR:22190.0,22231.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.01/76.18 22233[97:Res:53.1,22232.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.18 22235[97:MRR:22233.0,22017.0] || -> . % 76.01/76.18 22236[97:Spt:22235.0,22229.0,22230.0] || until2p7(s49)*+ -> . % 76.01/76.18 22237[97:Spt:22235.0,22229.1] || -> node4(s48)*. % 76.01/76.18 22238[97:MRR:22020.0,22237.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.01/76.18 22241[97:Res:53.1,22238.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.18 22244[97:Res:22241.0,61.1] always3(s48) || -> . % 76.01/76.18 22245[97:SSi:22244.0,737.0,22011.0,22026.0,22228.0,22237.0] || -> . % 76.01/76.18 22246[96:Spt:22245.0,22227.0,22228.0] || until2p7(s48)*+ -> . % 76.01/76.18 22247[96:Spt:22245.0,22227.1] || -> node4(s47)*. % 76.01/76.18 22249[96:MRR:777.0,22247.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.01/76.18 22267[96:Res:53.1,22249.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.01/76.18 22269[96:MRR:22267.0,21994.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.18 22271[96:Res:22269.0,61.1] always3(s48) || -> . % 76.01/76.18 22272[96:SSi:22271.0,737.0,22011.0,22026.0] || -> . % 76.01/76.18 22273[95:Spt:22272.0,22225.0,22226.0] || until2p7(s47)*+ -> . % 76.01/76.18 22274[95:Spt:22272.0,22225.1] || -> node4(s46)*. % 76.01/76.18 22275[95:MRR:21997.0,22274.0] || m_main_v_state(s46,c_ready)*+ -> . % 76.01/76.18 22279[95:Res:53.1,22275.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.18 22282[95:Res:22279.0,61.1] always3(s46) || -> . % 76.01/76.18 22283[95:SSi:22282.0,735.0,21988.0,22000.0,22224.0,22274.0] || -> . % 76.01/76.18 22284[94:Spt:22283.0,22223.0,22224.0] || until2p7(s46)*+ -> . % 76.01/76.18 22285[94:Spt:22283.0,22223.1] || -> node4(s45)*. % 76.01/76.18 22287[94:MRR:783.0,22285.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.01/76.18 22298[94:Res:53.1,22287.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.01/76.18 22300[94:MRR:22298.0,21974.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.18 22302[94:Res:22300.0,61.1] always3(s46) || -> . % 76.01/76.18 22303[94:SSi:22302.0,735.0,21988.0,22000.0] || -> . % 76.01/76.18 22304[93:Spt:22303.0,22221.0,22222.0] || until2p7(s45)*+ -> . % 76.01/76.18 22305[93:Spt:22303.0,22221.1] || -> node4(s44)*. % 76.01/76.18 22306[93:MRR:21977.0,22305.0] || m_main_v_state(s44,c_ready)*+ -> . % 76.01/76.18 22309[93:Res:53.1,22306.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.18 22312[93:Res:22309.0,61.1] always3(s44) || -> . % 76.01/76.18 22313[93:SSi:22312.0,733.0,21968.0,21980.0,22220.0,22305.0] || -> . % 76.01/76.18 22314[92:Spt:22313.0,22219.0,22220.0] || until2p7(s44)*+ -> . % 76.01/76.18 22315[92:Spt:22313.0,22219.1] || -> node4(s43)*. % 76.01/76.18 22317[92:MRR:789.0,22315.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.01/76.18 22329[92:Res:53.1,22317.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.01/76.18 22331[92:MRR:22329.0,21954.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.18 22333[92:Res:22331.0,61.1] always3(s44) || -> . % 76.01/76.18 22334[92:SSi:22333.0,733.0,21968.0,21980.0] || -> . % 76.01/76.18 22335[91:Spt:22334.0,22217.0,22218.0] || until2p7(s43)*+ -> . % 76.01/76.18 22336[91:Spt:22334.0,22217.1] || -> node4(s42)*. % 76.01/76.18 22337[91:MRR:21957.0,22336.0] || m_main_v_state(s42,c_ready)*+ -> . % 76.01/76.18 22340[91:Res:53.1,22337.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.18 22343[91:Res:22340.0,61.1] always3(s42) || -> . % 76.01/76.18 22344[91:SSi:22343.0,731.0,21948.0,21963.0,22216.0,22336.0] || -> . % 76.01/76.18 22345[90:Spt:22344.0,22215.0,22216.0] || until2p7(s42)*+ -> . % 76.01/76.18 22346[90:Spt:22344.0,22215.1] || -> node4(s41)*. % 76.01/76.18 22348[90:MRR:795.0,22346.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.01/76.18 22360[90:Res:53.1,22348.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.01/76.18 22362[90:MRR:22360.0,21931.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.18 22367[90:Res:22362.0,61.1] always3(s42) || -> . % 76.01/76.18 22368[90:SSi:22367.0,731.0,21948.0,21963.0] || -> . % 76.01/76.18 22369[89:Spt:22368.0,22213.0,22214.0] || until2p7(s41)*+ -> . % 76.01/76.18 22370[89:Spt:22368.0,22213.1] || -> node4(s40)*. % 76.01/76.18 22371[89:MRR:21934.0,22370.0] || m_main_v_state(s40,c_ready)*+ -> . % 76.01/76.18 22374[89:Res:53.1,22371.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.18 22378[89:Res:22374.0,61.1] always3(s40) || -> . % 76.01/76.18 22379[89:SSi:22378.0,729.0,21925.0,21937.0,22212.0,22370.0] || -> . % 76.01/76.18 22380[88:Spt:22379.0,22211.0,22212.0] || until2p7(s40)*+ -> . % 76.01/76.18 22381[88:Spt:22379.0,22211.1] || -> node4(s39)*. % 76.01/76.18 22383[88:MRR:801.0,22381.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.01/76.18 22394[88:Res:53.1,22383.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.01/76.18 22396[88:MRR:22394.0,21911.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.18 22398[88:Res:22396.0,61.1] always3(s40) || -> . % 76.01/76.18 22399[88:SSi:22398.0,729.0,21925.0,21937.0] || -> . % 76.01/76.18 22400[87:Spt:22399.0,22209.0,22210.0] || until2p7(s39)*+ -> . % 76.01/76.18 22401[87:Spt:22399.0,22209.1] || -> node4(s38)*. % 76.01/76.18 22402[87:MRR:21914.0,22401.0] || m_main_v_state(s38,c_ready)*+ -> . % 76.01/76.18 22406[87:Res:53.1,22402.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.18 22409[87:Res:22406.0,61.1] always3(s38) || -> . % 76.01/76.18 22410[87:SSi:22409.0,727.0,21905.0,21917.0,22208.0,22401.0] || -> . % 76.01/76.18 22411[86:Spt:22410.0,22207.0,22208.0] || until2p7(s38)*+ -> . % 76.01/76.18 22412[86:Spt:22410.0,22207.1] || -> node4(s37)*. % 76.01/76.18 22414[86:MRR:807.0,22412.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.01/76.18 22425[86:Res:53.1,22414.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.01/76.18 22427[86:MRR:22425.0,21891.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.18 22429[86:Res:22427.0,61.1] always3(s38) || -> . % 76.01/76.18 22430[86:SSi:22429.0,727.0,21905.0,21917.0] || -> . % 76.01/76.18 22431[85:Spt:22430.0,22205.0,22206.0] || until2p7(s37)*+ -> . % 76.01/76.18 22432[85:Spt:22430.0,22205.1] || -> node4(s36)*. % 76.01/76.18 22433[85:MRR:21894.0,22432.0] || m_main_v_state(s36,c_ready)*+ -> . % 76.01/76.18 22436[85:Res:53.1,22433.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.18 22439[85:Res:22436.0,61.1] always3(s36) || -> . % 76.01/76.18 22440[85:SSi:22439.0,725.0,21885.0,21900.0,22204.0,22432.0] || -> . % 76.01/76.18 22441[84:Spt:22440.0,22203.0,22204.0] || until2p7(s36)*+ -> . % 76.01/76.18 22442[84:Spt:22440.0,22203.1] || -> node4(s35)*. % 76.01/76.18 22444[84:MRR:813.0,22442.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.01/76.18 22456[84:Res:53.1,22444.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.01/76.18 22458[84:MRR:22456.0,21868.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.18 22460[84:Res:22458.0,61.1] always3(s36) || -> . % 76.01/76.18 22461[84:SSi:22460.0,725.0,21885.0,21900.0] || -> . % 76.01/76.18 22462[83:Spt:22461.0,22201.0,22202.0] || until2p7(s35)*+ -> . % 76.01/76.18 22463[83:Spt:22461.0,22201.1] || -> node4(s34)*. % 76.01/76.18 22464[83:MRR:21871.0,22463.0] || m_main_v_state(s34,c_ready)*+ -> . % 76.01/76.18 22467[83:Res:53.1,22464.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.18 22470[83:Res:22467.0,61.1] always3(s34) || -> . % 76.01/76.18 22471[83:SSi:22470.0,723.0,21862.0,21874.0,22200.0,22463.0] || -> . % 76.01/76.18 22472[82:Spt:22471.0,22199.0,22200.0] || until2p7(s34)*+ -> . % 76.01/76.18 22473[82:Spt:22471.0,22199.1] || -> node4(s33)*. % 76.01/76.18 22475[82:MRR:819.0,22473.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.01/76.18 22487[82:Res:53.1,22475.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.01/76.18 22489[82:MRR:22487.0,21848.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.18 22494[82:Res:22489.0,61.1] always3(s34) || -> . % 76.01/76.18 22495[82:SSi:22494.0,723.0,21862.0,21874.0] || -> . % 76.01/76.18 22496[81:Spt:22495.0,22197.0,22198.0] || until2p7(s33)*+ -> . % 76.01/76.18 22497[81:Spt:22495.0,22197.1] || -> node4(s32)*. % 76.01/76.18 22498[81:MRR:21851.0,22497.0] || m_main_v_state(s32,c_ready)*+ -> . % 76.01/76.18 22501[81:Res:53.1,22498.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.18 22505[81:Res:22501.0,61.1] always3(s32) || -> . % 76.01/76.18 22506[81:SSi:22505.0,721.0,21839.0,21854.0,22196.0,22497.0] || -> . % 76.01/76.18 22507[80:Spt:22506.0,22195.0,22196.0] || until2p7(s32)*+ -> . % 76.01/76.18 22508[80:Spt:22506.0,22195.1] || -> node4(s31)*. % 76.01/76.18 22510[80:MRR:825.0,22508.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.01/76.18 22521[80:Res:53.1,22510.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.01/76.18 22523[80:MRR:22521.0,22185.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.18 22525[80:Res:22523.0,61.1] always3(s32) || -> . % 76.01/76.18 22526[80:SSi:22525.0,721.0,21839.0,21854.0] || -> . % 76.01/76.18 22527[78:Spt:22526.0,22021.1,22026.0] || xuntil6(s48)* -> . % 76.01/76.18 22528[78:Spt:22526.0,22021.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.18 22531[78:Res:22528.0,61.1] always3(s48) || -> . % 76.01/76.18 22532[78:SSi:22531.0,737.0,22011.0] || -> . % 76.01/76.18 22533[76:Spt:22532.0,22002.2,22010.0] || xuntil6(s47)*+ -> . % 76.01/76.18 22534[76:Spt:22532.0,22002.0,22002.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.01/76.18 22535[76:Res:53.1,22534.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.01/76.18 22537[76:MRR:22535.0,21994.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.18 22539[76:Res:22537.0,61.1] always3(s48) || -> . % 76.01/76.18 22540[76:SSi:22539.0,737.0] || -> . % 76.01/76.18 22541[75:Spt:22540.0,21998.1,22000.0] || xuntil6(s46)* -> . % 76.01/76.18 22542[75:Spt:22540.0,21998.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.18 22545[75:Res:22542.0,61.1] always3(s46) || -> . % 76.01/76.18 22546[75:SSi:22545.0,735.0,21988.0] || -> . % 76.01/76.18 22547[73:Spt:22546.0,21982.2,21987.0] || xuntil6(s45)*+ -> . % 76.01/76.18 22548[73:Spt:22546.0,21982.0,21982.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.01/76.18 22549[73:Res:53.1,22548.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.01/76.18 22551[73:MRR:22549.0,21974.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.18 22553[73:Res:22551.0,61.1] always3(s46) || -> . % 76.01/76.18 22554[73:SSi:22553.0,735.0] || -> . % 76.01/76.18 22555[72:Spt:22554.0,21978.1,21980.0] || xuntil6(s44)* -> . % 76.01/76.18 22556[72:Spt:22554.0,21978.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.18 22559[72:Res:22556.0,61.1] always3(s44) || -> . % 76.01/76.18 22560[72:SSi:22559.0,733.0,21968.0] || -> . % 76.01/76.18 22561[70:Spt:22560.0,21965.2,21967.0] || xuntil6(s43)*+ -> . % 76.01/76.18 22562[70:Spt:22560.0,21965.0,21965.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.01/76.18 22563[70:Res:53.1,22562.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.01/76.18 22565[70:MRR:22563.0,21954.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.18 22567[70:Res:22565.0,61.1] always3(s44) || -> . % 76.01/76.18 22568[70:SSi:22567.0,733.0] || -> . % 76.01/76.18 22569[69:Spt:22568.0,21958.1,21963.0] || xuntil6(s42)* -> . % 76.01/76.18 22570[69:Spt:22568.0,21958.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.18 22573[69:Res:22570.0,61.1] always3(s42) || -> . % 76.01/76.18 22574[69:SSi:22573.0,731.0,21948.0] || -> . % 76.01/76.18 22575[67:Spt:22574.0,21939.2,21947.0] || xuntil6(s41)*+ -> . % 76.01/76.18 22576[67:Spt:22574.0,21939.0,21939.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.01/76.18 22577[67:Res:53.1,22576.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.01/76.18 22579[67:MRR:22577.0,21931.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.18 22582[67:Res:22579.0,61.1] always3(s42) || -> . % 76.01/76.18 22583[67:SSi:22582.0,731.0] || -> . % 76.01/76.18 22584[66:Spt:22583.0,21935.1,21937.0] || xuntil6(s40)* -> . % 76.01/76.18 22585[66:Spt:22583.0,21935.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.18 22588[66:Res:22585.0,61.1] always3(s40) || -> . % 76.01/76.18 22589[66:SSi:22588.0,729.0,21925.0] || -> . % 76.01/76.18 22590[64:Spt:22589.0,21919.2,21924.0] || xuntil6(s39)*+ -> . % 76.01/76.18 22591[64:Spt:22589.0,21919.0,21919.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.01/76.18 22592[64:Res:53.1,22591.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.01/76.18 22594[64:MRR:22592.0,21911.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.18 22596[64:Res:22594.0,61.1] always3(s40) || -> . % 76.01/76.18 22597[64:SSi:22596.0,729.0] || -> . % 76.01/76.18 22598[63:Spt:22597.0,21915.1,21917.0] || xuntil6(s38)* -> . % 76.01/76.18 22599[63:Spt:22597.0,21915.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.18 22602[63:Res:22599.0,61.1] always3(s38) || -> . % 76.01/76.18 22603[63:SSi:22602.0,727.0,21905.0] || -> . % 76.01/76.18 22604[61:Spt:22603.0,21902.2,21904.0] || xuntil6(s37)*+ -> . % 76.01/76.18 22605[61:Spt:22603.0,21902.0,21902.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.01/76.18 22606[61:Res:53.1,22605.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.01/76.18 22608[61:MRR:22606.0,21891.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.18 22611[61:Res:22608.0,61.1] always3(s38) || -> . % 76.01/76.18 22612[61:SSi:22611.0,727.0] || -> . % 76.01/76.18 22613[60:Spt:22612.0,21895.1,21900.0] || xuntil6(s36)* -> . % 76.01/76.18 22614[60:Spt:22612.0,21895.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.18 22617[60:Res:22614.0,61.1] always3(s36) || -> . % 76.01/76.18 22618[60:SSi:22617.0,725.0,21885.0] || -> . % 76.01/76.18 22619[58:Spt:22618.0,21876.2,21884.0] || xuntil6(s35)*+ -> . % 76.01/76.18 22620[58:Spt:22618.0,21876.0,21876.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.01/76.18 22621[58:Res:53.1,22620.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.01/76.18 22623[58:MRR:22621.0,21868.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.18 22625[58:Res:22623.0,61.1] always3(s36) || -> . % 76.01/76.18 22626[58:SSi:22625.0,725.0] || -> . % 76.01/76.18 22627[57:Spt:22626.0,21872.1,21874.0] || xuntil6(s34)* -> . % 76.01/76.18 22628[57:Spt:22626.0,21872.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.18 22631[57:Res:22628.0,61.1] always3(s34) || -> . % 76.01/76.18 22632[57:SSi:22631.0,723.0,21862.0] || -> . % 76.01/76.18 22633[55:Spt:22632.0,21856.2,21861.0] || xuntil6(s33)*+ -> . % 76.01/76.18 22634[55:Spt:22632.0,21856.0,21856.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.01/76.18 22635[55:Res:53.1,22634.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.01/76.18 22637[55:MRR:22635.0,21848.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.18 22639[55:Res:22637.0,61.1] always3(s34) || -> . % 76.01/76.18 22640[55:SSi:22639.0,723.0] || -> . % 76.01/76.18 22641[54:Spt:22640.0,21852.1,21854.0] || xuntil6(s32)* -> . % 76.01/76.18 22642[54:Spt:22640.0,21852.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.18 22645[54:Res:22642.0,61.1] always3(s32) || -> . % 76.01/76.18 22646[54:SSi:22645.0,721.0,21839.0] || -> . % 76.01/76.18 22647[52:Spt:22646.0,21837.2,21838.0] || xuntil6(s31)*+ -> . % 76.01/76.18 22648[52:Spt:22646.0,21837.0,21837.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.01/76.18 22649[52:Res:53.1,22648.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.01/76.18 22651[53:Spt:22649.1] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.18 22653[53:Res:22651.0,61.1] always3(s32) || -> . % 76.01/76.18 22654[53:SSi:22653.0,721.0] || -> . % 76.01/76.18 22655[53:Spt:22654.0,22649.1,22651.0] || m_main_v_state(s32,c_busy)* -> . % 76.01/76.18 22656[53:Spt:22654.0,22649.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.18 22659[53:Res:22656.0,61.1] always3(s31) || -> . % 76.01/76.18 22660[53:SSi:22659.0,720.0,21836.0] || -> . % 76.01/76.18 22661[51:Spt:22660.0,21831.2,21835.0] || xuntil6(s30)*+ -> . % 76.01/76.18 22662[51:Spt:22660.0,21831.0,21831.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.01/76.18 22663[51:Res:53.1,22662.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.01/76.18 22665[52:Spt:22663.0] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.18 22667[52:Res:22665.0,61.1] always3(s30) || -> . % 76.01/76.18 22668[52:SSi:22667.0,719.0,21830.0] || -> . % 76.01/76.18 22669[52:Spt:22668.0,22663.0,22665.0] || m_main_v_state(s30,c_busy)* -> . % 76.01/76.18 22670[52:Spt:22668.0,22663.1] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.18 22674[52:Res:22670.0,61.1] always3(s31) || -> . % 76.01/76.18 22675[52:SSi:22674.0,720.0] || -> . % 76.01/76.18 22676[50:Spt:22675.0,21828.2,21829.0] || xuntil6(s29)*+ -> . % 76.01/76.18 22677[50:Spt:22675.0,21828.0,21828.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.01/76.18 22678[50:Res:53.1,22677.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.01/76.18 22680[51:Spt:22678.0] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.18 22682[51:Res:22680.0,61.1] always3(s29) || -> . % 76.01/76.18 22683[51:SSi:22682.0,718.0,21827.0] || -> . % 76.01/76.18 22684[51:Spt:22683.0,22678.0,22680.0] || m_main_v_state(s29,c_busy)* -> . % 76.01/76.18 22685[51:Spt:22683.0,22678.1] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.18 22689[51:Res:22685.0,61.1] always3(s30) || -> . % 76.01/76.18 22690[51:SSi:22689.0,719.0] || -> . % 76.01/76.18 22691[49:Spt:22690.0,21822.2,21826.0] || xuntil6(s28)*+ -> . % 76.01/76.18 22692[49:Spt:22690.0,21822.0,21822.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.01/76.18 22693[49:Res:53.1,22692.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.01/76.18 22695[50:Spt:22693.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.18 22697[50:Res:22695.0,61.1] always3(s28) || -> . % 76.01/76.18 22698[50:SSi:22697.0,717.0,21821.0] || -> . % 76.01/76.18 22699[50:Spt:22698.0,22693.0,22695.0] || m_main_v_state(s28,c_busy)* -> . % 76.01/76.18 22700[50:Spt:22698.0,22693.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.18 22704[50:Res:22700.0,61.1] always3(s29) || -> . % 76.01/76.18 22705[50:SSi:22704.0,718.0] || -> . % 76.01/76.18 22706[48:Spt:22705.0,21819.2,21820.0] || xuntil6(s27)*+ -> . % 76.01/76.18 22707[48:Spt:22705.0,21819.0,21819.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.01/76.18 22708[48:Res:53.1,22707.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.01/76.18 22710[49:Spt:22708.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.18 22712[49:Res:22710.0,61.1] always3(s27) || -> . % 76.01/76.18 22713[49:SSi:22712.0,716.0,21818.0] || -> . % 76.01/76.18 22714[49:Spt:22713.0,22708.0,22710.0] || m_main_v_state(s27,c_busy)* -> . % 76.01/76.18 22715[49:Spt:22713.0,22708.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.18 22719[49:Res:22715.0,61.1] always3(s28) || -> . % 76.01/76.18 22720[49:SSi:22719.0,717.0] || -> . % 76.01/76.18 22721[47:Spt:22720.0,21813.2,21817.0] || xuntil6(s26)*+ -> . % 76.01/76.18 22722[47:Spt:22720.0,21813.0,21813.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.01/76.18 22723[47:Res:53.1,22722.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.01/76.18 22725[48:Spt:22723.0] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.18 22727[48:Res:22725.0,61.1] always3(s26) || -> . % 76.01/76.18 22728[48:SSi:22727.0,715.0,21812.0] || -> . % 76.01/76.18 22729[48:Spt:22728.0,22723.0,22725.0] || m_main_v_state(s26,c_busy)* -> . % 76.01/76.18 22730[48:Spt:22728.0,22723.1] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.18 22734[48:Res:22730.0,61.1] always3(s27) || -> . % 76.01/76.18 22735[48:SSi:22734.0,716.0] || -> . % 76.01/76.18 22736[46:Spt:22735.0,21810.2,21811.0] || xuntil6(s25)*+ -> . % 76.01/76.18 22737[46:Spt:22735.0,21810.0,21810.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.01/76.18 22738[46:Res:53.1,22737.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.01/76.18 22740[47:Spt:22738.0] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.18 22742[47:Res:22740.0,61.1] always3(s25) || -> . % 76.01/76.18 22743[47:SSi:22742.0,714.0,21809.0] || -> . % 76.01/76.18 22744[47:Spt:22743.0,22738.0,22740.0] || m_main_v_state(s25,c_busy)* -> . % 76.01/76.18 22745[47:Spt:22743.0,22738.1] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.18 22749[47:Res:22745.0,61.1] always3(s26) || -> . % 76.01/76.18 22750[47:SSi:22749.0,715.0] || -> . % 76.01/76.18 22751[45:Spt:22750.0,21804.2,21808.0] || xuntil6(s24)*+ -> . % 76.01/76.18 22752[45:Spt:22750.0,21804.0,21804.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.01/76.18 22753[45:Res:53.1,22752.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.01/76.18 22755[46:Spt:22753.0] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.18 22757[46:Res:22755.0,61.1] always3(s24) || -> . % 76.01/76.18 22758[46:SSi:22757.0,713.0,21803.0] || -> . % 76.01/76.18 22759[46:Spt:22758.0,22753.0,22755.0] || m_main_v_state(s24,c_busy)* -> . % 76.01/76.18 22760[46:Spt:22758.0,22753.1] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.18 22764[46:Res:22760.0,61.1] always3(s25) || -> . % 76.01/76.18 22765[46:SSi:22764.0,714.0] || -> . % 76.01/76.18 22766[44:Spt:22765.0,21801.2,21802.0] || xuntil6(s23)*+ -> . % 76.01/76.18 22767[44:Spt:22765.0,21801.0,21801.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.01/76.18 22768[44:Res:53.1,22767.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.01/76.18 22770[45:Spt:22768.0] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.18 22772[45:Res:22770.0,61.1] always3(s23) || -> . % 76.01/76.18 22773[45:SSi:22772.0,712.0,21800.0] || -> . % 76.01/76.18 22774[45:Spt:22773.0,22768.0,22770.0] || m_main_v_state(s23,c_busy)* -> . % 76.01/76.18 22775[45:Spt:22773.0,22768.1] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.18 22779[45:Res:22775.0,61.1] always3(s24) || -> . % 76.01/76.18 22780[45:SSi:22779.0,713.0] || -> . % 76.01/76.18 22781[43:Spt:22780.0,21795.2,21799.0] || xuntil6(s22)*+ -> . % 76.01/76.18 22782[43:Spt:22780.0,21795.0,21795.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.01/76.18 22783[43:Res:53.1,22782.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.01/76.18 22788[44:Spt:22783.0] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.18 22790[44:Res:22788.0,61.1] always3(s22) || -> . % 76.01/76.18 22791[44:SSi:22790.0,711.0,21794.0] || -> . % 76.01/76.18 22792[44:Spt:22791.0,22783.0,22788.0] || m_main_v_state(s22,c_busy)* -> . % 76.01/76.18 22793[44:Spt:22791.0,22783.1] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.18 22797[44:Res:22793.0,61.1] always3(s23) || -> . % 76.01/76.18 22798[44:SSi:22797.0,712.0] || -> . % 76.01/76.18 22799[42:Spt:22798.0,21792.2,21793.0] || xuntil6(s21)*+ -> . % 76.01/76.18 22800[42:Spt:22798.0,21792.0,21792.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.01/76.18 22801[42:Res:53.1,22800.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.01/76.18 22803[43:Spt:22801.0] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.18 22805[43:Res:22803.0,61.1] always3(s21) || -> . % 76.01/76.18 22806[43:SSi:22805.0,710.0,21791.0] || -> . % 76.01/76.18 22807[43:Spt:22806.0,22801.0,22803.0] || m_main_v_state(s21,c_busy)* -> . % 76.01/76.18 22808[43:Spt:22806.0,22801.1] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.18 22812[43:Res:22808.0,61.1] always3(s22) || -> . % 76.01/76.18 22813[43:SSi:22812.0,711.0] || -> . % 76.01/76.18 22814[41:Spt:22813.0,21786.2,21790.0] || xuntil6(s20)*+ -> . % 76.01/76.18 22815[41:Spt:22813.0,21786.0,21786.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.01/76.18 22816[41:Res:53.1,22815.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.01/76.18 22818[42:Spt:22816.0] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.18 22820[42:Res:22818.0,61.1] always3(s20) || -> . % 76.01/76.18 22821[42:SSi:22820.0,709.0,21785.0] || -> . % 76.01/76.18 22822[42:Spt:22821.0,22816.0,22818.0] || m_main_v_state(s20,c_busy)* -> . % 76.01/76.18 22823[42:Spt:22821.0,22816.1] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.18 22827[42:Res:22823.0,61.1] always3(s21) || -> . % 76.01/76.18 22828[42:SSi:22827.0,710.0] || -> . % 76.01/76.18 22829[40:Spt:22828.0,21783.2,21784.0] || xuntil6(s19)*+ -> . % 76.01/76.18 22830[40:Spt:22828.0,21783.0,21783.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.01/76.18 22831[40:Res:53.1,22830.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.01/76.18 22836[41:Spt:22831.0] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.18 22838[41:Res:22836.0,61.1] always3(s19) || -> . % 76.01/76.18 22839[41:SSi:22838.0,708.0,21782.0] || -> . % 76.01/76.18 22840[41:Spt:22839.0,22831.0,22836.0] || m_main_v_state(s19,c_busy)* -> . % 76.01/76.18 22841[41:Spt:22839.0,22831.1] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.18 22845[41:Res:22841.0,61.1] always3(s20) || -> . % 76.01/76.18 22846[41:SSi:22845.0,709.0] || -> . % 76.01/76.18 22847[39:Spt:22846.0,21777.2,21781.0] || xuntil6(s18)*+ -> . % 76.01/76.18 22848[39:Spt:22846.0,21777.0,21777.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.01/76.18 22849[39:Res:53.1,22848.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.01/76.18 22851[40:Spt:22849.0] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.18 22853[40:Res:22851.0,61.1] always3(s18) || -> . % 76.01/76.18 22854[40:SSi:22853.0,707.0,21776.0] || -> . % 76.01/76.18 22855[40:Spt:22854.0,22849.0,22851.0] || m_main_v_state(s18,c_busy)* -> . % 76.01/76.18 22856[40:Spt:22854.0,22849.1] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.18 22860[40:Res:22856.0,61.1] always3(s19) || -> . % 76.01/76.18 22861[40:SSi:22860.0,708.0] || -> . % 76.01/76.18 22862[38:Spt:22861.0,21774.2,21775.0] || xuntil6(s17)*+ -> . % 76.01/76.18 22863[38:Spt:22861.0,21774.0,21774.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.01/76.18 22864[38:Res:53.1,22863.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.01/76.18 22866[39:Spt:22864.0] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.18 22868[39:Res:22866.0,61.1] always3(s17) || -> . % 76.01/76.18 22869[39:SSi:22868.0,706.0,21773.0] || -> . % 76.01/76.18 22870[39:Spt:22869.0,22864.0,22866.0] || m_main_v_state(s17,c_busy)* -> . % 76.01/76.18 22871[39:Spt:22869.0,22864.1] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.18 22875[39:Res:22871.0,61.1] always3(s18) || -> . % 76.01/76.18 22876[39:SSi:22875.0,707.0] || -> . % 76.01/76.18 22877[37:Spt:22876.0,21768.2,21772.0] || xuntil6(s16)*+ -> . % 76.01/76.18 22878[37:Spt:22876.0,21768.0,21768.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.01/76.18 22879[37:Res:53.1,22878.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.01/76.18 22884[38:Spt:22879.0] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.18 22886[38:Res:22884.0,61.1] always3(s16) || -> . % 76.01/76.18 22887[38:SSi:22886.0,705.0,21767.0] || -> . % 76.01/76.18 22888[38:Spt:22887.0,22879.0,22884.0] || m_main_v_state(s16,c_busy)* -> . % 76.01/76.18 22889[38:Spt:22887.0,22879.1] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.18 22893[38:Res:22889.0,61.1] always3(s17) || -> . % 76.01/76.18 22894[38:SSi:22893.0,706.0] || -> . % 76.01/76.18 22895[36:Spt:22894.0,21765.2,21766.0] || xuntil6(s15)*+ -> . % 76.01/76.18 22896[36:Spt:22894.0,21765.0,21765.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.01/76.18 22897[36:Res:53.1,22896.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.01/76.18 22899[37:Spt:22897.0] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.18 22901[37:Res:22899.0,61.1] always3(s15) || -> . % 76.01/76.18 22902[37:SSi:22901.0,704.0,21764.0] || -> . % 76.01/76.18 22903[37:Spt:22902.0,22897.0,22899.0] || m_main_v_state(s15,c_busy)* -> . % 76.01/76.18 22904[37:Spt:22902.0,22897.1] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.18 22908[37:Res:22904.0,61.1] always3(s16) || -> . % 76.01/76.18 22909[37:SSi:22908.0,705.0] || -> . % 76.01/76.18 22910[35:Spt:22909.0,21759.2,21763.0] || xuntil6(s14)*+ -> . % 76.01/76.18 22911[35:Spt:22909.0,21759.0,21759.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.01/76.18 22912[35:Res:53.1,22911.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.01/76.18 22914[36:Spt:22912.0] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.18 22916[36:Res:22914.0,61.1] always3(s14) || -> . % 76.01/76.18 22917[36:SSi:22916.0,703.0,21758.0] || -> . % 76.01/76.18 22918[36:Spt:22917.0,22912.0,22914.0] || m_main_v_state(s14,c_busy)* -> . % 76.01/76.18 22919[36:Spt:22917.0,22912.1] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.18 22923[36:Res:22919.0,61.1] always3(s15) || -> . % 76.01/76.18 22924[36:SSi:22923.0,704.0] || -> . % 76.01/76.18 22925[34:Spt:22924.0,21756.2,21757.0] || xuntil6(s13)*+ -> . % 76.01/76.18 22926[34:Spt:22924.0,21756.0,21756.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.01/76.18 22927[34:Res:53.1,22926.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.01/76.18 22932[35:Spt:22927.0] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.18 22934[35:Res:22932.0,61.1] always3(s13) || -> . % 76.01/76.18 22935[35:SSi:22934.0,702.0,21755.0] || -> . % 76.01/76.18 22936[35:Spt:22935.0,22927.0,22932.0] || m_main_v_state(s13,c_busy)* -> . % 76.01/76.18 22937[35:Spt:22935.0,22927.1] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.18 22941[35:Res:22937.0,61.1] always3(s14) || -> . % 76.01/76.18 22942[35:SSi:22941.0,703.0] || -> . % 76.01/76.18 22943[33:Spt:22942.0,21750.2,21754.0] || xuntil6(s12)*+ -> . % 76.01/76.18 22944[33:Spt:22942.0,21750.0,21750.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.01/76.18 22945[33:Res:53.1,22944.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.01/76.18 22947[34:Spt:22945.0] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.18 22949[34:Res:22947.0,61.1] always3(s12) || -> . % 76.01/76.18 22950[34:SSi:22949.0,701.0,21749.0] || -> . % 76.01/76.18 22951[34:Spt:22950.0,22945.0,22947.0] || m_main_v_state(s12,c_busy)* -> . % 76.01/76.18 22952[34:Spt:22950.0,22945.1] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.18 22956[34:Res:22952.0,61.1] always3(s13) || -> . % 76.01/76.18 22957[34:SSi:22956.0,702.0] || -> . % 76.01/76.18 22958[32:Spt:22957.0,21747.2,21748.0] || xuntil6(s11)*+ -> . % 76.01/76.18 22959[32:Spt:22957.0,21747.0,21747.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.01/76.18 22960[32:Res:53.1,22959.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.01/76.18 22962[33:Spt:22960.0] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.18 22964[33:Res:22962.0,61.1] always3(s11) || -> . % 76.01/76.18 22965[33:SSi:22964.0,700.0,21746.0] || -> . % 76.01/76.18 22966[33:Spt:22965.0,22960.0,22962.0] || m_main_v_state(s11,c_busy)* -> . % 76.01/76.18 22967[33:Spt:22965.0,22960.1] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.18 22971[33:Res:22967.0,61.1] always3(s12) || -> . % 76.01/76.18 22972[33:SSi:22971.0,701.0] || -> . % 76.01/76.18 22973[31:Spt:22972.0,21741.2,21745.0] || xuntil6(s10)*+ -> . % 76.01/76.18 22974[31:Spt:22972.0,21741.0,21741.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.01/76.18 22975[31:Res:53.1,22974.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.01/76.18 22980[32:Spt:22975.0] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.18 22982[32:Res:22980.0,61.1] always3(s10) || -> . % 76.01/76.18 22983[32:SSi:22982.0,699.0,21740.0] || -> . % 76.01/76.18 22984[32:Spt:22983.0,22975.0,22980.0] || m_main_v_state(s10,c_busy)* -> . % 76.01/76.18 22985[32:Spt:22983.0,22975.1] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.18 22989[32:Res:22985.0,61.1] always3(s11) || -> . % 76.01/76.18 22990[32:SSi:22989.0,700.0] || -> . % 76.01/76.18 22991[30:Spt:22990.0,21738.2,21739.0] || xuntil6(s9)*+ -> . % 76.01/76.18 22992[30:Spt:22990.0,21738.0,21738.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.01/76.18 22993[30:Res:53.1,22992.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.01/76.18 22995[31:Spt:22993.0] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.18 22997[31:Res:22995.0,61.1] always3(s9) || -> . % 76.01/76.18 22998[31:SSi:22997.0,698.0,21737.0] || -> . % 76.01/76.18 22999[31:Spt:22998.0,22993.0,22995.0] || m_main_v_state(s9,c_busy)* -> . % 76.01/76.18 23000[31:Spt:22998.0,22993.1] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.18 23004[31:Res:23000.0,61.1] always3(s10) || -> . % 76.01/76.18 23005[31:SSi:23004.0,699.0] || -> . % 76.01/76.18 23006[29:Spt:23005.0,21732.2,21736.0] || xuntil6(s8)*+ -> . % 76.01/76.18 23007[29:Spt:23005.0,21732.0,21732.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.01/76.18 23008[29:Res:53.1,23007.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.01/76.18 23010[30:Spt:23008.0] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.18 23012[30:Res:23010.0,61.1] always3(s8) || -> . % 76.01/76.18 23013[30:SSi:23012.0,697.0,21731.0] || -> . % 76.01/76.18 23014[30:Spt:23013.0,23008.0,23010.0] || m_main_v_state(s8,c_busy)* -> . % 76.01/76.18 23015[30:Spt:23013.0,23008.1] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.18 23019[30:Res:23015.0,61.1] always3(s9) || -> . % 76.01/76.18 23020[30:SSi:23019.0,698.0] || -> . % 76.01/76.18 23021[28:Spt:23020.0,21729.2,21730.0] || xuntil6(s7)*+ -> . % 76.01/76.18 23022[28:Spt:23020.0,21729.0,21729.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.01/76.18 23023[28:Res:53.1,23022.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.01/76.18 23028[29:Spt:23023.0] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.18 23030[29:Res:23028.0,61.1] always3(s7) || -> . % 76.01/76.18 23031[29:SSi:23030.0,696.0,21728.0] || -> . % 76.01/76.18 23032[29:Spt:23031.0,23023.0,23028.0] || m_main_v_state(s7,c_busy)* -> . % 76.01/76.18 23033[29:Spt:23031.0,23023.1] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.18 23037[29:Res:23033.0,61.1] always3(s8) || -> . % 76.01/76.18 23038[29:SSi:23037.0,697.0] || -> . % 76.01/76.18 23039[27:Spt:23038.0,21723.2,21727.0] || xuntil6(s6)*+ -> . % 76.01/76.18 23040[27:Spt:23038.0,21723.0,21723.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.01/76.18 23041[27:Res:53.1,23040.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.01/76.18 23043[28:Spt:23041.0] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.18 23045[28:Res:23043.0,61.1] always3(s6) || -> . % 76.01/76.18 23046[28:SSi:23045.0,695.0,21722.0] || -> . % 76.01/76.18 23047[28:Spt:23046.0,23041.0,23043.0] || m_main_v_state(s6,c_busy)* -> . % 76.01/76.18 23048[28:Spt:23046.0,23041.1] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.18 23052[28:Res:23048.0,61.1] always3(s7) || -> . % 76.01/76.18 23053[28:SSi:23052.0,696.0] || -> . % 76.01/76.18 23054[26:Spt:23053.0,21720.2,21721.0] || xuntil6(s5)*+ -> . % 76.01/76.18 23055[26:Spt:23053.0,21720.0,21720.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.01/76.18 23056[26:Res:53.1,23055.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.01/76.18 23058[27:Spt:23056.0] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.18 23060[27:Res:23058.0,61.1] always3(s5) || -> . % 76.01/76.18 23061[27:SSi:23060.0,694.0,21719.0] || -> . % 76.01/76.18 23062[27:Spt:23061.0,23056.0,23058.0] || m_main_v_state(s5,c_busy)* -> . % 76.01/76.18 23063[27:Spt:23061.0,23056.1] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.18 23067[27:Res:23063.0,61.1] always3(s6) || -> . % 76.01/76.18 23068[27:SSi:23067.0,695.0] || -> . % 76.01/76.18 23069[25:Spt:23068.0,21714.2,21718.0] || xuntil6(s4)*+ -> . % 76.01/76.18 23070[25:Spt:23068.0,21714.0,21714.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.01/76.18 23071[25:Res:53.1,23070.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.01/76.18 23076[26:Spt:23071.0] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.18 23078[26:Res:23076.0,61.1] always3(s4) || -> . % 76.01/76.18 23079[26:SSi:23078.0,693.0,21713.0] || -> . % 76.01/76.18 23080[26:Spt:23079.0,23071.0,23076.0] || m_main_v_state(s4,c_busy)* -> . % 76.01/76.18 23081[26:Spt:23079.0,23071.1] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.18 23085[26:Res:23081.0,61.1] always3(s5) || -> . % 76.01/76.18 23086[26:SSi:23085.0,694.0] || -> . % 76.01/76.18 23087[24:Spt:23086.0,21711.2,21712.0] || xuntil6(s3)*+ -> . % 76.01/76.18 23088[24:Spt:23086.0,21711.0,21711.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.01/76.18 23089[24:Res:53.1,23088.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.01/76.18 23091[25:Spt:23089.0] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.18 23093[25:Res:23091.0,61.1] always3(s3) || -> . % 76.01/76.18 23094[25:SSi:23093.0,692.0,21710.0] || -> . % 76.01/76.18 23095[25:Spt:23094.0,23089.0,23091.0] || m_main_v_state(s3,c_busy)* -> . % 76.01/76.18 23096[25:Spt:23094.0,23089.1] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.18 23100[25:Res:23096.0,61.1] always3(s4) || -> . % 76.01/76.18 23101[25:SSi:23100.0,693.0] || -> . % 76.01/76.18 23102[23:Spt:23101.0,21705.2,21709.0] || xuntil6(s2)*+ -> . % 76.01/76.18 23103[23:Spt:23101.0,21705.0,21705.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.01/76.18 23104[23:Res:53.1,23103.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.01/76.18 23106[24:Spt:23104.0] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.18 23108[24:Res:23106.0,61.1] always3(s2) || -> . % 76.01/76.18 23109[24:SSi:23108.0,691.0,21704.0] || -> . % 76.01/76.18 23110[24:Spt:23109.0,23104.0,23106.0] || m_main_v_state(s2,c_busy)* -> . % 76.01/76.18 23111[24:Spt:23109.0,23104.1] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.18 23115[24:Res:23111.0,61.1] always3(s3) || -> . % 76.01/76.18 23116[24:SSi:23115.0,692.0] || -> . % 76.01/76.18 23117[22:Spt:23116.0,21699.2,21703.0] || xuntil6(s1)*+ -> . % 76.01/76.18 23118[22:Spt:23116.0,21699.0,21699.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.01/76.18 23119[22:Res:53.1,23118.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.01/76.18 23124[23:Spt:23119.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.18 23126[23:Res:23124.0,61.1] always3(s1) || -> . % 76.01/76.18 23127[23:SSi:23126.0,690.0,21698.0] || -> . % 76.01/76.18 23128[23:Spt:23127.0,23119.0,23124.0] || m_main_v_state(s1,c_busy)* -> . % 76.01/76.18 23129[23:Spt:23127.0,23119.1] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.18 23134[23:Res:23129.0,61.1] always3(s2) || -> . % 76.01/76.18 23135[23:SSi:23134.0,691.0] || -> . % 76.01/76.18 23136[21:Spt:23135.0,74.0,21697.0] || xuntil6(s0)*+ -> . % 76.01/76.18 23137[21:Spt:23135.0,74.1] || -> node4(s0)*. % 76.01/76.18 23138[21:MRR:758.1,23136.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.18 23140[21:Res:23138.0,61.1] always3(s1) || -> . % 76.01/76.18 23141[21:SSi:23140.0,690.0] || -> . % 76.01/76.18 23142[20:Spt:23141.0,21687.0,21691.0] || trans(s49,s31)*+ -> . % 76.01/76.18 23143[20:Spt:23141.0,21687.1,21687.2,21687.3,21687.4,21687.5,21687.6,21687.7,21687.8,21687.9,21687.10,21687.11,21687.12,21687.13,21687.14,21687.15,21687.16,21687.17,21687.18,21687.19,21687.20,21687.21,21687.22,21687.23,21687.24,21687.25,21687.26,21687.27,21687.28,21687.29,21687.30,21687.31] || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.01/76.18 23144[20:MRR:21689.0,23142.0] || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.01/76.18 23146[20:MRR:21690.1,23142.0] xuntil6(s49) || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.01/76.18 23147[21:Spt:23143.0] || -> trans(s49,s30)*. % 76.01/76.18 23148[21:Res:23147.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s30)*. % 76.01/76.18 23150[21:Res:23147.0,60.0] || -> node2(s49,s30)*. % 76.01/76.18 23151[21:SSi:23148.1,50.0,738.0] xuntil6(s49) || -> until2p7(s30)*. % 76.01/76.18 23152[21:Res:23150.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)*. % 76.01/76.18 23153[22:Spt:74.0] || -> xuntil6(s0)*. % 76.01/76.18 23154[22:MRR:176.0,23153.0] || -> until5(s1)*. % 76.01/76.18 23155[22:MRR:22143.0,23154.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.18 23159[23:Spt:23155.2] || -> xuntil6(s1)*. % 76.01/76.18 23160[23:MRR:175.0,23159.0] || -> until5(s2)*. % 76.01/76.18 23161[23:MRR:22142.0,23160.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.18 23162[24:Spt:23161.2] || -> xuntil6(s2)*. % 76.01/76.18 23163[24:MRR:174.0,23162.0] || -> until5(s3)*. % 76.01/76.18 23164[24:MRR:22135.0,23163.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.18 23165[25:Spt:23164.2] || -> xuntil6(s3)*. % 76.01/76.18 23166[25:MRR:173.0,23165.0] || -> until5(s4)*. % 76.01/76.18 23167[25:MRR:22131.0,23166.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.18 23168[26:Spt:23167.2] || -> xuntil6(s4)*. % 76.01/76.18 23169[26:MRR:172.0,23168.0] || -> until5(s5)*. % 76.01/76.18 23170[26:MRR:22127.0,23169.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.18 23174[27:Spt:23170.2] || -> xuntil6(s5)*. % 76.01/76.18 23175[27:MRR:171.0,23174.0] || -> until5(s6)*. % 76.01/76.18 23176[27:MRR:22123.0,23175.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.18 23177[28:Spt:23176.2] || -> xuntil6(s6)*. % 76.01/76.18 23178[28:MRR:170.0,23177.0] || -> until5(s7)*. % 76.01/76.18 23179[28:MRR:22122.0,23178.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.18 23183[29:Spt:23179.2] || -> xuntil6(s7)*. % 76.01/76.18 23184[29:MRR:169.0,23183.0] || -> until5(s8)*. % 76.01/76.18 23185[29:MRR:22115.0,23184.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.18 23186[30:Spt:23185.2] || -> xuntil6(s8)*. % 76.01/76.18 23187[30:MRR:168.0,23186.0] || -> until5(s9)*. % 76.01/76.18 23188[30:MRR:22111.0,23187.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.18 23192[31:Spt:23188.2] || -> xuntil6(s9)*. % 76.01/76.18 23193[31:MRR:167.0,23192.0] || -> until5(s10)*. % 76.01/76.18 23194[31:MRR:22107.0,23193.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.18 23195[32:Spt:23194.2] || -> xuntil6(s10)*. % 76.01/76.18 23196[32:MRR:166.0,23195.0] || -> until5(s11)*. % 76.01/76.18 23197[32:MRR:22103.0,23196.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.18 23201[33:Spt:23197.2] || -> xuntil6(s11)*. % 76.01/76.18 23202[33:MRR:165.0,23201.0] || -> until5(s12)*. % 76.01/76.18 23203[33:MRR:22102.0,23202.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.18 23204[34:Spt:23203.2] || -> xuntil6(s12)*. % 76.01/76.18 23205[34:MRR:164.0,23204.0] || -> until5(s13)*. % 76.01/76.18 23206[34:MRR:22095.0,23205.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.18 23210[35:Spt:23206.2] || -> xuntil6(s13)*. % 76.01/76.18 23211[35:MRR:163.0,23210.0] || -> until5(s14)*. % 76.01/76.18 23212[35:MRR:22091.0,23211.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.18 23213[36:Spt:23212.2] || -> xuntil6(s14)*. % 76.01/76.18 23214[36:MRR:162.0,23213.0] || -> until5(s15)*. % 76.01/76.18 23215[36:MRR:22087.0,23214.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.18 23219[37:Spt:23215.2] || -> xuntil6(s15)*. % 76.01/76.18 23220[37:MRR:161.0,23219.0] || -> until5(s16)*. % 76.01/76.18 23221[37:MRR:22083.0,23220.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.18 23222[38:Spt:23221.2] || -> xuntil6(s16)*. % 76.01/76.18 23223[38:MRR:160.0,23222.0] || -> until5(s17)*. % 76.01/76.18 23224[38:MRR:22082.0,23223.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.18 23228[39:Spt:23224.2] || -> xuntil6(s17)*. % 76.01/76.18 23229[39:MRR:159.0,23228.0] || -> until5(s18)*. % 76.01/76.18 23230[39:MRR:22075.0,23229.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.18 23231[40:Spt:23230.2] || -> xuntil6(s18)*. % 76.01/76.18 23232[40:MRR:158.0,23231.0] || -> until5(s19)*. % 76.01/76.18 23233[40:MRR:22071.0,23232.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.18 23237[41:Spt:23233.2] || -> xuntil6(s19)*. % 76.01/76.18 23238[41:MRR:157.0,23237.0] || -> until5(s20)*. % 76.01/76.18 23239[41:MRR:22067.0,23238.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.18 23240[42:Spt:23239.2] || -> xuntil6(s20)*. % 76.01/76.18 23241[42:MRR:156.0,23240.0] || -> until5(s21)*. % 76.01/76.18 23242[42:MRR:22063.0,23241.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.18 23246[43:Spt:23242.2] || -> xuntil6(s21)*. % 76.01/76.18 23247[43:MRR:155.0,23246.0] || -> until5(s22)*. % 76.01/76.18 23248[43:MRR:22062.0,23247.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.18 23249[44:Spt:23248.2] || -> xuntil6(s22)*. % 76.01/76.18 23250[44:MRR:154.0,23249.0] || -> until5(s23)*. % 76.01/76.18 23251[44:MRR:22055.0,23250.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.18 23255[45:Spt:23251.2] || -> xuntil6(s23)*. % 76.01/76.18 23256[45:MRR:153.0,23255.0] || -> until5(s24)*. % 76.01/76.18 23257[45:MRR:22051.0,23256.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.18 23258[46:Spt:23257.2] || -> xuntil6(s24)*. % 76.01/76.18 23259[46:MRR:152.0,23258.0] || -> until5(s25)*. % 76.01/76.18 23260[46:MRR:22047.0,23259.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.18 23264[47:Spt:23260.2] || -> xuntil6(s25)*. % 76.01/76.18 23265[47:MRR:151.0,23264.0] || -> until5(s26)*. % 76.01/76.18 23266[47:MRR:22043.0,23265.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.18 23267[48:Spt:23266.2] || -> xuntil6(s26)*. % 76.01/76.18 23268[48:MRR:150.0,23267.0] || -> until5(s27)*. % 76.01/76.18 23269[48:MRR:22042.0,23268.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.18 23273[49:Spt:23269.2] || -> xuntil6(s27)*. % 76.01/76.18 23274[49:MRR:149.0,23273.0] || -> until5(s28)*. % 76.01/76.18 23275[49:MRR:22034.0,23274.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.18 23276[50:Spt:23275.2] || -> xuntil6(s28)*. % 76.01/76.18 23277[50:MRR:148.0,23276.0] || -> until5(s29)*. % 76.01/76.18 23278[50:MRR:22035.0,23277.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.18 23282[51:Spt:23278.1] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.18 23284[51:Res:23282.0,61.1] always3(s30) || -> . % 76.01/76.18 23285[51:SSi:23284.0,719.0] || -> . % 76.01/76.18 23286[51:Spt:23285.0,23278.1,23282.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.01/76.18 23287[51:Spt:23285.0,23278.0,23278.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 76.01/76.18 23290[51:MRR:23152.2,23286.0] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> . % 76.01/76.18 23291[51:Res:53.1,23287.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 76.01/76.18 23293[52:Spt:23291.1] || -> xuntil6(s29)*. % 76.01/76.18 23294[52:MRR:147.0,23293.0] || -> until5(s30)*. % 76.01/76.18 23295[52:MRR:22029.0,23294.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.18 23301[51:SoR:23290.0,64.1] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.01/76.18 23303[51:SoR:23301.0,66.2] until5(s49) || m_main_v_state(s49,c_ready)* -> xuntil6(s49). % 76.01/76.18 23304[53:Spt:23295.2] || -> xuntil6(s30)*. % 76.01/76.18 23305[53:MRR:146.0,23304.0] || -> until5(s31)*. % 76.01/76.18 23306[53:MRR:22033.0,23305.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.18 23307[54:Spt:23306.1] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.18 23309[54:Res:23307.0,61.1] always3(s32) || -> . % 76.01/76.18 23310[54:SSi:23309.0,721.0] || -> . % 76.01/76.18 23311[54:Spt:23310.0,23306.1,23307.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.01/76.18 23312[54:Spt:23310.0,23306.0,23306.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.01/76.18 23314[54:MRR:825.2,23311.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.01/76.18 23315[54:Res:53.1,23312.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.01/76.18 23317[55:Spt:23315.1] || -> xuntil6(s31)*. % 76.01/76.18 23318[55:MRR:145.0,23317.0] || -> until5(s32)*. % 76.01/76.18 23319[55:MRR:19324.0,23318.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.18 23324[56:Spt:23319.2] || -> xuntil6(s32)*. % 76.01/76.18 23325[56:MRR:144.0,23324.0] || -> until5(s33)*. % 76.01/76.18 23326[56:MRR:22147.0,23325.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.18 23330[57:Spt:23326.1] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.18 23332[57:Res:23330.0,61.1] always3(s34) || -> . % 76.01/76.18 23333[57:SSi:23332.0,723.0] || -> . % 76.01/76.18 23334[57:Spt:23333.0,23326.1,23330.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.01/76.18 23335[57:Spt:23333.0,23326.0,23326.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.01/76.18 23337[57:MRR:819.2,23334.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.01/76.18 23338[57:Res:53.1,23335.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.01/76.18 23340[58:Spt:23338.1] || -> xuntil6(s33)*. % 76.01/76.18 23341[58:MRR:143.0,23340.0] || -> until5(s34)*. % 76.01/76.18 23342[58:MRR:16857.0,23341.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.18 23347[59:Spt:23342.2] || -> xuntil6(s34)*. % 76.01/76.18 23348[59:MRR:142.0,23347.0] || -> until5(s35)*. % 76.01/76.18 23349[59:MRR:22151.0,23348.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.18 23350[60:Spt:23349.1] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.18 23352[60:Res:23350.0,61.1] always3(s36) || -> . % 76.01/76.18 23353[60:SSi:23352.0,725.0] || -> . % 76.01/76.18 23354[60:Spt:23353.0,23349.1,23350.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.01/76.18 23355[60:Spt:23353.0,23349.0,23349.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.01/76.18 23357[60:MRR:813.2,23354.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.01/76.18 23358[60:Res:53.1,23355.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.01/76.18 23360[61:Spt:23358.1] || -> xuntil6(s35)*. % 76.01/76.18 23361[61:MRR:141.0,23360.0] || -> until5(s36)*. % 76.01/76.18 23362[61:MRR:16858.0,23361.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.18 23370[62:Spt:23362.2] || -> xuntil6(s36)*. % 76.01/76.18 23371[62:MRR:140.0,23370.0] || -> until5(s37)*. % 76.01/76.18 23372[62:MRR:22155.0,23371.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.18 23373[63:Spt:23372.1] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.18 23375[63:Res:23373.0,61.1] always3(s38) || -> . % 76.01/76.18 23376[63:SSi:23375.0,727.0] || -> . % 76.01/76.18 23377[63:Spt:23376.0,23372.1,23373.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.01/76.18 23378[63:Spt:23376.0,23372.0,23372.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.01/76.18 23380[63:MRR:807.2,23377.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.01/76.18 23381[63:Res:53.1,23378.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.01/76.18 23386[64:Spt:23381.1] || -> xuntil6(s37)*. % 76.01/76.18 23387[64:MRR:139.0,23386.0] || -> until5(s38)*. % 76.01/76.18 23388[64:MRR:16862.0,23387.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.18 23390[65:Spt:23388.2] || -> xuntil6(s38)*. % 76.01/76.18 23391[65:MRR:138.0,23390.0] || -> until5(s39)*. % 76.01/76.18 23392[65:MRR:22162.0,23391.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.18 23393[66:Spt:23392.1] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.18 23395[66:Res:23393.0,61.1] always3(s40) || -> . % 76.01/76.18 23396[66:SSi:23395.0,729.0] || -> . % 76.01/76.18 23397[66:Spt:23396.0,23392.1,23393.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.01/76.18 23398[66:Spt:23396.0,23392.0,23392.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.01/76.18 23400[66:MRR:801.2,23397.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.01/76.18 23401[66:Res:53.1,23398.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.01/76.18 23403[67:Spt:23401.1] || -> xuntil6(s39)*. % 76.01/76.18 23404[67:MRR:137.0,23403.0] || -> until5(s40)*. % 76.01/76.18 23405[67:MRR:16866.0,23404.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.01/76.18 23410[68:Spt:23405.2] || -> xuntil6(s40)*. % 76.01/76.18 23411[68:MRR:136.0,23410.0] || -> until5(s41)*. % 76.01/76.18 23412[68:MRR:22163.0,23411.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.18 23413[69:Spt:23412.1] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.18 23415[69:Res:23413.0,61.1] always3(s42) || -> . % 76.01/76.18 23416[69:SSi:23415.0,731.0] || -> . % 76.01/76.18 23417[69:Spt:23416.0,23412.1,23413.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.01/76.18 23418[69:Spt:23416.0,23412.0,23412.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.01/76.18 23420[69:MRR:795.2,23417.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.01/76.18 23421[69:Res:53.1,23418.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.01/76.18 23423[70:Spt:23421.1] || -> xuntil6(s41)*. % 76.01/76.18 23424[70:MRR:135.0,23423.0] || -> until5(s42)*. % 76.01/76.18 23425[70:MRR:16870.0,23424.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.01/76.18 23433[71:Spt:23425.2] || -> xuntil6(s42)*. % 76.01/76.18 23434[71:MRR:134.0,23433.0] || -> until5(s43)*. % 76.01/76.18 23435[71:MRR:22167.0,23434.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.18 23436[72:Spt:23435.1] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.18 23438[72:Res:23436.0,61.1] always3(s44) || -> . % 76.01/76.18 23439[72:SSi:23438.0,733.0] || -> . % 76.01/76.18 23440[72:Spt:23439.0,23435.1,23436.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.01/76.18 23441[72:Spt:23439.0,23435.0,23435.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.01/76.18 23443[72:MRR:789.2,23440.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.01/76.18 23444[72:Res:53.1,23441.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.01/76.18 23449[73:Spt:23444.1] || -> xuntil6(s43)*. % 76.01/76.18 23450[73:MRR:133.0,23449.0] || -> until5(s44)*. % 76.01/76.18 23451[73:MRR:16877.0,23450.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.01/76.18 23453[74:Spt:23451.2] || -> xuntil6(s44)*. % 76.01/76.18 23454[74:MRR:132.0,23453.0] || -> until5(s45)*. % 76.01/76.18 23455[74:MRR:22171.0,23454.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.18 23456[75:Spt:23455.1] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.18 23458[75:Res:23456.0,61.1] always3(s46) || -> . % 76.01/76.18 23459[75:SSi:23458.0,735.0] || -> . % 76.01/76.18 23460[75:Spt:23459.0,23455.1,23456.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.01/76.18 23461[75:Spt:23459.0,23455.0,23455.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.01/76.18 23463[75:MRR:783.2,23460.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.01/76.18 23464[75:Res:53.1,23461.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.01/76.18 23466[76:Spt:23464.1] || -> xuntil6(s45)*. % 76.01/76.18 23467[76:MRR:131.0,23466.0] || -> until5(s46)*. % 76.01/76.18 23468[76:MRR:16878.0,23467.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.01/76.18 23473[77:Spt:23468.2] || -> xuntil6(s46)*. % 76.01/76.18 23474[77:MRR:130.0,23473.0] || -> until5(s47)*. % 76.01/76.18 23475[77:MRR:22175.0,23474.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.18 23476[78:Spt:23475.1] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.18 23478[78:Res:23476.0,61.1] always3(s48) || -> . % 76.01/76.18 23479[78:SSi:23478.0,737.0] || -> . % 76.01/76.18 23480[78:Spt:23479.0,23475.1,23476.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.01/76.18 23481[78:Spt:23479.0,23475.0,23475.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.01/76.18 23483[78:MRR:777.2,23480.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.01/76.18 23484[78:Res:53.1,23481.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.01/76.18 23486[79:Spt:23484.1] || -> xuntil6(s47)*. % 76.01/76.18 23487[79:MRR:129.0,23486.0] || -> until5(s48)*. % 76.01/76.18 23488[79:MRR:16882.0,23487.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.01/76.18 23496[80:Spt:23488.2] || -> xuntil6(s48)*. % 76.01/76.18 23497[80:MRR:128.0,23496.0] || -> until5(s49)*. % 76.01/76.18 23498[80:MRR:23303.0,23497.0] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.01/76.18 23499[80:Res:53.1,23498.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.01/76.18 23501[81:Spt:23499.1] || -> xuntil6(s49)*. % 76.01/76.18 23502[81:MRR:23151.0,23501.0] || -> until2p7(s30)*. % 76.01/76.18 23503[81:MRR:226.0,23502.0] || -> until2p7(s31)* node4(s30). % 76.01/76.18 23504[82:Spt:23503.0] || -> until2p7(s31)*. % 76.01/76.18 23505[82:MRR:227.0,23504.0] || -> until2p7(s32)* node4(s31). % 76.01/76.18 23506[83:Spt:23505.0] || -> until2p7(s32)*. % 76.01/76.18 23507[83:MRR:228.0,23506.0] || -> until2p7(s33)* node4(s32). % 76.01/76.18 23508[84:Spt:23507.0] || -> until2p7(s33)*. % 76.01/76.18 23509[84:MRR:229.0,23508.0] || -> until2p7(s34)* node4(s33). % 76.01/76.18 23510[85:Spt:23509.0] || -> until2p7(s34)*. % 76.01/76.18 23511[85:MRR:230.0,23510.0] || -> until2p7(s35)* node4(s34). % 76.01/76.18 23512[86:Spt:23511.0] || -> until2p7(s35)*. % 76.01/76.18 23513[86:MRR:231.0,23512.0] || -> until2p7(s36)* node4(s35). % 76.01/76.18 23514[87:Spt:23513.0] || -> until2p7(s36)*. % 76.01/76.18 23515[87:MRR:232.0,23514.0] || -> until2p7(s37)* node4(s36). % 76.01/76.18 23516[88:Spt:23515.0] || -> until2p7(s37)*. % 76.01/76.18 23517[88:MRR:235.0,23516.0] || -> until2p7(s38)* node4(s37). % 76.01/76.18 23518[89:Spt:23517.0] || -> until2p7(s38)*. % 76.01/76.18 23519[89:MRR:236.0,23518.0] || -> until2p7(s39)* node4(s38). % 76.01/76.18 23520[90:Spt:23519.0] || -> until2p7(s39)*. % 76.01/76.18 23521[90:MRR:237.0,23520.0] || -> until2p7(s40)* node4(s39). % 76.01/76.18 23522[91:Spt:23521.0] || -> until2p7(s40)*. % 76.01/76.18 23523[91:MRR:238.0,23522.0] || -> until2p7(s41)* node4(s40). % 76.01/76.18 23524[92:Spt:23523.0] || -> until2p7(s41)*. % 76.01/76.18 23525[92:MRR:239.0,23524.0] || -> until2p7(s42)* node4(s41). % 76.01/76.18 23526[93:Spt:23525.0] || -> until2p7(s42)*. % 76.01/76.18 23527[93:MRR:240.0,23526.0] || -> until2p7(s43)* node4(s42). % 76.01/76.18 23528[94:Spt:23527.0] || -> until2p7(s43)*. % 76.01/76.18 23529[94:MRR:241.0,23528.0] || -> until2p7(s44)* node4(s43). % 76.01/76.18 23530[95:Spt:23529.0] || -> until2p7(s44)*. % 76.01/76.18 23531[95:MRR:539.0,23530.0] || -> until2p7(s45)* node4(s44). % 76.01/76.18 23532[96:Spt:23531.0] || -> until2p7(s45)*. % 76.01/76.18 23533[96:MRR:544.0,23532.0] || -> until2p7(s46)* node4(s45). % 76.01/76.18 23534[97:Spt:23533.0] || -> until2p7(s46)*. % 76.01/76.18 23535[97:MRR:549.0,23534.0] || -> until2p7(s47)* node4(s46). % 76.01/76.18 23536[98:Spt:23535.0] || -> until2p7(s47)*. % 76.01/76.18 23537[98:MRR:554.0,23536.0] || -> until2p7(s48)* node4(s47). % 76.01/76.18 23538[99:Spt:23537.0] || -> until2p7(s48)*. % 76.01/76.18 23539[99:MRR:559.0,23538.0] || -> until2p7(s49)* node4(s48). % 76.01/76.18 23540[100:Spt:23539.0] || -> until2p7(s49)*. % 76.01/76.18 23541[100:MRR:194.0,23540.0] || -> node4(s49)*. % 76.01/76.18 23542[100:MRR:23301.0,23541.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.01/76.18 23543[100:Res:53.1,23542.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.18 23546[100:Res:23543.0,61.1] always3(s49) || -> . % 76.01/76.18 23547[100:SSi:23546.0,50.0,738.0,23497.0,23501.0,23540.0,23541.0] || -> . % 76.01/76.18 23548[100:Spt:23547.0,23539.0,23540.0] || until2p7(s49)*+ -> . % 76.01/76.18 23549[100:Spt:23547.0,23539.1] || -> node4(s48)*. % 76.01/76.18 23551[100:MRR:774.0,23549.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.01/76.18 23557[100:Res:53.1,23551.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.01/76.18 23559[100:MRR:23557.0,23480.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.18 23561[100:Res:23559.0,61.1] always3(s49) || -> . % 76.01/76.18 23562[100:SSi:23561.0,50.0,738.0,23497.0,23501.0] || -> . % 76.01/76.18 23563[99:Spt:23562.0,23537.0,23538.0] || until2p7(s48)*+ -> . % 76.01/76.18 23564[99:Spt:23562.0,23537.1] || -> node4(s47)*. % 76.01/76.18 23565[99:MRR:23483.0,23564.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.01/76.18 23568[99:Res:53.1,23565.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.18 23571[99:Res:23568.0,61.1] always3(s47) || -> . % 76.01/76.18 23572[99:SSi:23571.0,736.0,23474.0,23486.0,23536.0,23564.0] || -> . % 76.01/76.18 23573[98:Spt:23572.0,23535.0,23536.0] || until2p7(s47)*+ -> . % 76.01/76.18 23574[98:Spt:23572.0,23535.1] || -> node4(s46)*. % 76.01/76.18 23576[98:MRR:780.0,23574.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.01/76.18 23588[98:Res:53.1,23576.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.01/76.18 23590[98:MRR:23588.0,23460.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.18 23595[98:Res:23590.0,61.1] always3(s47) || -> . % 76.01/76.18 23596[98:SSi:23595.0,736.0,23474.0,23486.0] || -> . % 76.01/76.18 23597[97:Spt:23596.0,23533.0,23534.0] || until2p7(s46)*+ -> . % 76.01/76.18 23598[97:Spt:23596.0,23533.1] || -> node4(s45)*. % 76.01/76.18 23599[97:MRR:23463.0,23598.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.01/76.18 23602[97:Res:53.1,23599.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.18 23606[97:Res:23602.0,61.1] always3(s45) || -> . % 76.01/76.18 23607[97:SSi:23606.0,734.0,23454.0,23466.0,23532.0,23598.0] || -> . % 76.01/76.18 23608[96:Spt:23607.0,23531.0,23532.0] || until2p7(s45)*+ -> . % 76.01/76.18 23609[96:Spt:23607.0,23531.1] || -> node4(s44)*. % 76.01/76.18 23611[96:MRR:786.0,23609.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.01/76.18 23622[96:Res:53.1,23611.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.01/76.18 23624[96:MRR:23622.0,23440.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.18 23626[96:Res:23624.0,61.1] always3(s45) || -> . % 76.01/76.18 23627[96:SSi:23626.0,734.0,23454.0,23466.0] || -> . % 76.01/76.18 23628[95:Spt:23627.0,23529.0,23530.0] || until2p7(s44)*+ -> . % 76.01/76.18 23629[95:Spt:23627.0,23529.1] || -> node4(s43)*. % 76.01/76.18 23630[95:MRR:23443.0,23629.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.01/76.18 23634[95:Res:53.1,23630.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.18 23637[95:Res:23634.0,61.1] always3(s43) || -> . % 76.01/76.18 23638[95:SSi:23637.0,732.0,23434.0,23449.0,23528.0,23629.0] || -> . % 76.01/76.18 23639[94:Spt:23638.0,23527.0,23528.0] || until2p7(s43)*+ -> . % 76.01/76.18 23640[94:Spt:23638.0,23527.1] || -> node4(s42)*. % 76.01/76.18 23642[94:MRR:792.0,23640.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.01/76.18 23653[94:Res:53.1,23642.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.01/76.18 23655[94:MRR:23653.0,23417.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.18 23657[94:Res:23655.0,61.1] always3(s43) || -> . % 76.01/76.18 23658[94:SSi:23657.0,732.0,23434.0,23449.0] || -> . % 76.01/76.18 23659[93:Spt:23658.0,23525.0,23526.0] || until2p7(s42)*+ -> . % 76.01/76.18 23660[93:Spt:23658.0,23525.1] || -> node4(s41)*. % 76.01/76.18 23661[93:MRR:23420.0,23660.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.01/76.18 23664[93:Res:53.1,23661.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.18 23667[93:Res:23664.0,61.1] always3(s41) || -> . % 76.01/76.18 23668[93:SSi:23667.0,730.0,23411.0,23423.0,23524.0,23660.0] || -> . % 76.01/76.18 23669[92:Spt:23668.0,23523.0,23524.0] || until2p7(s41)*+ -> . % 76.01/76.18 23670[92:Spt:23668.0,23523.1] || -> node4(s40)*. % 76.01/76.18 23672[92:MRR:798.0,23670.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.01/76.18 23684[92:Res:53.1,23672.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.01/76.18 23686[92:MRR:23684.0,23397.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.18 23688[92:Res:23686.0,61.1] always3(s41) || -> . % 76.01/76.18 23689[92:SSi:23688.0,730.0,23411.0,23423.0] || -> . % 76.01/76.18 23690[91:Spt:23689.0,23521.0,23522.0] || until2p7(s40)*+ -> . % 76.01/76.18 23691[91:Spt:23689.0,23521.1] || -> node4(s39)*. % 76.01/76.18 23692[91:MRR:23400.0,23691.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.01/76.18 23695[91:Res:53.1,23692.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.18 23698[91:Res:23695.0,61.1] always3(s39) || -> . % 76.01/76.18 23699[91:SSi:23698.0,728.0,23391.0,23403.0,23520.0,23691.0] || -> . % 76.01/76.18 23700[90:Spt:23699.0,23519.0,23520.0] || until2p7(s39)*+ -> . % 76.01/76.18 23701[90:Spt:23699.0,23519.1] || -> node4(s38)*. % 76.01/76.18 23703[90:MRR:804.0,23701.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.01/76.18 23715[90:Res:53.1,23703.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.01/76.18 23717[90:MRR:23715.0,23377.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.18 23722[90:Res:23717.0,61.1] always3(s39) || -> . % 76.01/76.18 23723[90:SSi:23722.0,728.0,23391.0,23403.0] || -> . % 76.01/76.18 23724[89:Spt:23723.0,23517.0,23518.0] || until2p7(s38)*+ -> . % 76.01/76.18 23725[89:Spt:23723.0,23517.1] || -> node4(s37)*. % 76.01/76.18 23726[89:MRR:23380.0,23725.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.01/76.18 23729[89:Res:53.1,23726.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.18 23733[89:Res:23729.0,61.1] always3(s37) || -> . % 76.01/76.18 23734[89:SSi:23733.0,726.0,23371.0,23386.0,23516.0,23725.0] || -> . % 76.01/76.18 23735[88:Spt:23734.0,23515.0,23516.0] || until2p7(s37)*+ -> . % 76.01/76.18 23736[88:Spt:23734.0,23515.1] || -> node4(s36)*. % 76.01/76.18 23738[88:MRR:810.0,23736.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.01/76.18 23749[88:Res:53.1,23738.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.01/76.18 23751[88:MRR:23749.0,23354.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.18 23753[88:Res:23751.0,61.1] always3(s37) || -> . % 76.01/76.18 23754[88:SSi:23753.0,726.0,23371.0,23386.0] || -> . % 76.01/76.18 23755[87:Spt:23754.0,23513.0,23514.0] || until2p7(s36)*+ -> . % 76.01/76.18 23756[87:Spt:23754.0,23513.1] || -> node4(s35)*. % 76.01/76.18 23757[87:MRR:23357.0,23756.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.01/76.18 23761[87:Res:53.1,23757.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.18 23764[87:Res:23761.0,61.1] always3(s35) || -> . % 76.01/76.18 23765[87:SSi:23764.0,724.0,23348.0,23360.0,23512.0,23756.0] || -> . % 76.01/76.18 23766[86:Spt:23765.0,23511.0,23512.0] || until2p7(s35)*+ -> . % 76.01/76.18 23767[86:Spt:23765.0,23511.1] || -> node4(s34)*. % 76.01/76.18 23769[86:MRR:816.0,23767.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.01/76.18 23780[86:Res:53.1,23769.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.01/76.18 23782[86:MRR:23780.0,23334.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.18 23784[86:Res:23782.0,61.1] always3(s35) || -> . % 76.01/76.18 23785[86:SSi:23784.0,724.0,23348.0,23360.0] || -> . % 76.01/76.18 23786[85:Spt:23785.0,23509.0,23510.0] || until2p7(s34)*+ -> . % 76.01/76.18 23787[85:Spt:23785.0,23509.1] || -> node4(s33)*. % 76.01/76.18 23788[85:MRR:23337.0,23787.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.01/76.18 23791[85:Res:53.1,23788.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.18 23794[85:Res:23791.0,61.1] always3(s33) || -> . % 76.01/76.18 23795[85:SSi:23794.0,722.0,23325.0,23340.0,23508.0,23787.0] || -> . % 76.01/76.18 23796[84:Spt:23795.0,23507.0,23508.0] || until2p7(s33)*+ -> . % 76.01/76.18 23797[84:Spt:23795.0,23507.1] || -> node4(s32)*. % 76.01/76.18 23799[84:MRR:822.0,23797.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.01/76.18 23811[84:Res:53.1,23799.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.01/76.18 23813[84:MRR:23811.0,23311.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.18 23815[84:Res:23813.0,61.1] always3(s33) || -> . % 76.01/76.18 23816[84:SSi:23815.0,722.0,23325.0,23340.0] || -> . % 76.01/76.18 23817[83:Spt:23816.0,23505.0,23506.0] || until2p7(s32)*+ -> . % 76.01/76.18 23818[83:Spt:23816.0,23505.1] || -> node4(s31)*. % 76.01/76.18 23819[83:MRR:23314.0,23818.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.01/76.18 23822[83:Res:53.1,23819.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.18 23825[83:Res:23822.0,61.1] always3(s31) || -> . % 76.01/76.18 23826[83:SSi:23825.0,720.0,23305.0,23317.0,23504.0,23818.0] || -> . % 76.01/76.18 23827[82:Spt:23826.0,23503.0,23504.0] || until2p7(s31)*+ -> . % 76.01/76.18 23828[82:Spt:23826.0,23503.1] || -> node4(s30)*. % 76.01/76.18 23830[82:MRR:828.0,23828.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.01/76.18 23842[82:Res:53.1,23830.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.01/76.18 23844[82:MRR:23842.0,23286.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.18 23849[82:Res:23844.0,61.1] always3(s31) || -> . % 76.01/76.18 23850[82:SSi:23849.0,720.0,23305.0,23317.0] || -> . % 76.01/76.18 23851[81:Spt:23850.0,23499.1,23501.0] || xuntil6(s49)* -> . % 76.01/76.18 23852[81:Spt:23850.0,23499.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.18 23855[81:Res:23852.0,61.1] always3(s49) || -> . % 76.01/76.18 23856[81:SSi:23855.0,50.0,738.0,23497.0] || -> . % 76.01/76.18 23857[80:Spt:23856.0,23488.2,23496.0] || xuntil6(s48)*+ -> . % 76.01/76.18 23858[80:Spt:23856.0,23488.0,23488.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.01/76.18 23859[80:Res:53.1,23858.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.01/76.18 23861[80:MRR:23859.0,23480.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.18 23863[80:Res:23861.0,61.1] always3(s49) || -> . % 76.01/76.18 23864[80:SSi:23863.0,50.0,738.0] || -> . % 76.01/76.18 23865[79:Spt:23864.0,23484.1,23486.0] || xuntil6(s47)* -> . % 76.01/76.18 23866[79:Spt:23864.0,23484.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.18 23869[79:Res:23866.0,61.1] always3(s47) || -> . % 76.01/76.18 23870[79:SSi:23869.0,736.0,23474.0] || -> . % 76.01/76.18 23871[77:Spt:23870.0,23468.2,23473.0] || xuntil6(s46)*+ -> . % 76.01/76.18 23872[77:Spt:23870.0,23468.0,23468.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.01/76.18 23873[77:Res:53.1,23872.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.01/76.18 23875[77:MRR:23873.0,23460.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.18 23878[77:Res:23875.0,61.1] always3(s47) || -> . % 76.01/76.18 23879[77:SSi:23878.0,736.0] || -> . % 76.01/76.18 23880[76:Spt:23879.0,23464.1,23466.0] || xuntil6(s45)* -> . % 76.01/76.18 23881[76:Spt:23879.0,23464.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.18 23884[76:Res:23881.0,61.1] always3(s45) || -> . % 76.01/76.18 23885[76:SSi:23884.0,734.0,23454.0] || -> . % 76.01/76.18 23886[74:Spt:23885.0,23451.2,23453.0] || xuntil6(s44)*+ -> . % 76.01/76.18 23887[74:Spt:23885.0,23451.0,23451.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.01/76.18 23888[74:Res:53.1,23887.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.01/76.18 23890[74:MRR:23888.0,23440.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.18 23892[74:Res:23890.0,61.1] always3(s45) || -> . % 76.01/76.18 23893[74:SSi:23892.0,734.0] || -> . % 76.01/76.18 23894[73:Spt:23893.0,23444.1,23449.0] || xuntil6(s43)* -> . % 76.01/76.18 23895[73:Spt:23893.0,23444.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.18 23898[73:Res:23895.0,61.1] always3(s43) || -> . % 76.01/76.18 23899[73:SSi:23898.0,732.0,23434.0] || -> . % 76.01/76.18 23900[71:Spt:23899.0,23425.2,23433.0] || xuntil6(s42)*+ -> . % 76.01/76.18 23901[71:Spt:23899.0,23425.0,23425.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.01/76.18 23902[71:Res:53.1,23901.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.01/76.18 23904[71:MRR:23902.0,23417.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.18 23907[71:Res:23904.0,61.1] always3(s43) || -> . % 76.01/76.18 23908[71:SSi:23907.0,732.0] || -> . % 76.01/76.18 23909[70:Spt:23908.0,23421.1,23423.0] || xuntil6(s41)* -> . % 76.01/76.18 23910[70:Spt:23908.0,23421.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.18 23913[70:Res:23910.0,61.1] always3(s41) || -> . % 76.01/76.18 23914[70:SSi:23913.0,730.0,23411.0] || -> . % 76.01/76.18 23915[68:Spt:23914.0,23405.2,23410.0] || xuntil6(s40)*+ -> . % 76.01/76.18 23916[68:Spt:23914.0,23405.0,23405.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.01/76.18 23917[68:Res:53.1,23916.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.01/76.18 23919[68:MRR:23917.0,23397.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.18 23921[68:Res:23919.0,61.1] always3(s41) || -> . % 76.01/76.18 23922[68:SSi:23921.0,730.0] || -> . % 76.01/76.18 23923[67:Spt:23922.0,23401.1,23403.0] || xuntil6(s39)* -> . % 76.01/76.18 23924[67:Spt:23922.0,23401.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.18 23927[67:Res:23924.0,61.1] always3(s39) || -> . % 76.01/76.18 23928[67:SSi:23927.0,728.0,23391.0] || -> . % 76.01/76.18 23929[65:Spt:23928.0,23388.2,23390.0] || xuntil6(s38)*+ -> . % 76.01/76.18 23930[65:Spt:23928.0,23388.0,23388.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.01/76.18 23931[65:Res:53.1,23930.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.01/76.18 23933[65:MRR:23931.0,23377.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.18 23935[65:Res:23933.0,61.1] always3(s39) || -> . % 76.01/76.18 23936[65:SSi:23935.0,728.0] || -> . % 76.01/76.18 23937[64:Spt:23936.0,23381.1,23386.0] || xuntil6(s37)* -> . % 76.01/76.18 23938[64:Spt:23936.0,23381.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.18 23941[64:Res:23938.0,61.1] always3(s37) || -> . % 76.01/76.18 23942[64:SSi:23941.0,726.0,23371.0] || -> . % 76.01/76.18 23943[62:Spt:23942.0,23362.2,23370.0] || xuntil6(s36)*+ -> . % 76.01/76.18 23944[62:Spt:23942.0,23362.0,23362.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.01/76.18 23945[62:Res:53.1,23944.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.01/76.18 23947[62:MRR:23945.0,23354.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.18 23949[62:Res:23947.0,61.1] always3(s37) || -> . % 76.01/76.18 23950[62:SSi:23949.0,726.0] || -> . % 76.01/76.18 23951[61:Spt:23950.0,23358.1,23360.0] || xuntil6(s35)* -> . % 76.01/76.18 23952[61:Spt:23950.0,23358.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.18 23955[61:Res:23952.0,61.1] always3(s35) || -> . % 76.01/76.18 23956[61:SSi:23955.0,724.0,23348.0] || -> . % 76.01/76.18 23957[59:Spt:23956.0,23342.2,23347.0] || xuntil6(s34)*+ -> . % 76.01/76.18 23958[59:Spt:23956.0,23342.0,23342.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.01/76.18 23959[59:Res:53.1,23958.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.01/76.18 23961[59:MRR:23959.0,23334.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.18 23963[59:Res:23961.0,61.1] always3(s35) || -> . % 76.01/76.18 23964[59:SSi:23963.0,724.0] || -> . % 76.01/76.18 23965[58:Spt:23964.0,23338.1,23340.0] || xuntil6(s33)* -> . % 76.01/76.18 23966[58:Spt:23964.0,23338.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.18 23969[58:Res:23966.0,61.1] always3(s33) || -> . % 76.01/76.18 23970[58:SSi:23969.0,722.0,23325.0] || -> . % 76.01/76.18 23971[56:Spt:23970.0,23319.2,23324.0] || xuntil6(s32)*+ -> . % 76.01/76.18 23972[56:Spt:23970.0,23319.0,23319.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.01/76.18 23973[56:Res:53.1,23972.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.01/76.18 23975[56:MRR:23973.0,23311.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.18 23977[56:Res:23975.0,61.1] always3(s33) || -> . % 76.01/76.18 23978[56:SSi:23977.0,722.0] || -> . % 76.01/76.18 23979[55:Spt:23978.0,23315.1,23317.0] || xuntil6(s31)* -> . % 76.01/76.18 23980[55:Spt:23978.0,23315.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.18 23983[55:Res:23980.0,61.1] always3(s31) || -> . % 76.01/76.18 23984[55:SSi:23983.0,720.0,23305.0] || -> . % 76.01/76.18 23985[53:Spt:23984.0,23295.2,23304.0] || xuntil6(s30)*+ -> . % 76.01/76.18 23986[53:Spt:23984.0,23295.0,23295.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.01/76.18 23987[53:Res:53.1,23986.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.01/76.18 23989[53:MRR:23987.0,23286.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.18 23991[53:Res:23989.0,61.1] always3(s31) || -> . % 76.01/76.18 23992[53:SSi:23991.0,720.0] || -> . % 76.01/76.18 23993[52:Spt:23992.0,23291.1,23293.0] || xuntil6(s29)* -> . % 76.01/76.18 23994[52:Spt:23992.0,23291.0] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.18 23997[52:Res:23994.0,61.1] always3(s29) || -> . % 76.01/76.18 23998[52:SSi:23997.0,718.0,23277.0] || -> . % 76.01/76.18 23999[50:Spt:23998.0,23275.2,23276.0] || xuntil6(s28)*+ -> . % 76.01/76.18 24000[50:Spt:23998.0,23275.0,23275.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.01/76.18 24001[50:Res:53.1,24000.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.01/76.18 24003[51:Spt:24001.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.18 24005[51:Res:24003.0,61.1] always3(s28) || -> . % 76.01/76.18 24006[51:SSi:24005.0,717.0,23274.0] || -> . % 76.01/76.18 24007[51:Spt:24006.0,24001.0,24003.0] || m_main_v_state(s28,c_busy)* -> . % 76.01/76.18 24008[51:Spt:24006.0,24001.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.18 24012[51:Res:24008.0,61.1] always3(s29) || -> . % 76.01/76.18 24013[51:SSi:24012.0,718.0] || -> . % 76.01/76.18 24014[49:Spt:24013.0,23269.2,23273.0] || xuntil6(s27)*+ -> . % 76.01/76.18 24015[49:Spt:24013.0,23269.0,23269.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.01/76.18 24016[49:Res:53.1,24015.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.01/76.18 24018[50:Spt:24016.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.18 24020[50:Res:24018.0,61.1] always3(s27) || -> . % 76.01/76.18 24021[50:SSi:24020.0,716.0,23268.0] || -> . % 76.01/76.18 24022[50:Spt:24021.0,24016.0,24018.0] || m_main_v_state(s27,c_busy)* -> . % 76.01/76.18 24023[50:Spt:24021.0,24016.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.18 24027[50:Res:24023.0,61.1] always3(s28) || -> . % 76.01/76.18 24028[50:SSi:24027.0,717.0] || -> . % 76.01/76.18 24029[48:Spt:24028.0,23266.2,23267.0] || xuntil6(s26)*+ -> . % 76.01/76.18 24030[48:Spt:24028.0,23266.0,23266.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.01/76.18 24031[48:Res:53.1,24030.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.01/76.18 24033[49:Spt:24031.0] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.18 24035[49:Res:24033.0,61.1] always3(s26) || -> . % 76.01/76.18 24036[49:SSi:24035.0,715.0,23265.0] || -> . % 76.01/76.18 24037[49:Spt:24036.0,24031.0,24033.0] || m_main_v_state(s26,c_busy)* -> . % 76.01/76.18 24038[49:Spt:24036.0,24031.1] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.18 24042[49:Res:24038.0,61.1] always3(s27) || -> . % 76.01/76.18 24043[49:SSi:24042.0,716.0] || -> . % 76.01/76.18 24044[47:Spt:24043.0,23260.2,23264.0] || xuntil6(s25)*+ -> . % 76.01/76.18 24045[47:Spt:24043.0,23260.0,23260.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.01/76.18 24046[47:Res:53.1,24045.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.01/76.18 24048[48:Spt:24046.0] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.18 24050[48:Res:24048.0,61.1] always3(s25) || -> . % 76.01/76.18 24051[48:SSi:24050.0,714.0,23259.0] || -> . % 76.01/76.18 24052[48:Spt:24051.0,24046.0,24048.0] || m_main_v_state(s25,c_busy)* -> . % 76.01/76.18 24053[48:Spt:24051.0,24046.1] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.18 24057[48:Res:24053.0,61.1] always3(s26) || -> . % 76.01/76.18 24058[48:SSi:24057.0,715.0] || -> . % 76.01/76.18 24059[46:Spt:24058.0,23257.2,23258.0] || xuntil6(s24)*+ -> . % 76.01/76.18 24060[46:Spt:24058.0,23257.0,23257.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.01/76.18 24061[46:Res:53.1,24060.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.01/76.18 24063[47:Spt:24061.0] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.18 24065[47:Res:24063.0,61.1] always3(s24) || -> . % 76.01/76.18 24066[47:SSi:24065.0,713.0,23256.0] || -> . % 76.01/76.18 24067[47:Spt:24066.0,24061.0,24063.0] || m_main_v_state(s24,c_busy)* -> . % 76.01/76.18 24068[47:Spt:24066.0,24061.1] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.18 24072[47:Res:24068.0,61.1] always3(s25) || -> . % 76.01/76.18 24073[47:SSi:24072.0,714.0] || -> . % 76.01/76.18 24074[45:Spt:24073.0,23251.2,23255.0] || xuntil6(s23)*+ -> . % 76.01/76.18 24075[45:Spt:24073.0,23251.0,23251.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.01/76.18 24076[45:Res:53.1,24075.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.01/76.18 24078[46:Spt:24076.0] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.18 24080[46:Res:24078.0,61.1] always3(s23) || -> . % 76.01/76.18 24081[46:SSi:24080.0,712.0,23250.0] || -> . % 76.01/76.18 24082[46:Spt:24081.0,24076.0,24078.0] || m_main_v_state(s23,c_busy)* -> . % 76.01/76.18 24083[46:Spt:24081.0,24076.1] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.18 24087[46:Res:24083.0,61.1] always3(s24) || -> . % 76.01/76.18 24088[46:SSi:24087.0,713.0] || -> . % 76.01/76.18 24089[44:Spt:24088.0,23248.2,23249.0] || xuntil6(s22)*+ -> . % 76.01/76.18 24090[44:Spt:24088.0,23248.0,23248.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.01/76.18 24091[44:Res:53.1,24090.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.01/76.18 24093[45:Spt:24091.0] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.18 24095[45:Res:24093.0,61.1] always3(s22) || -> . % 76.01/76.18 24096[45:SSi:24095.0,711.0,23247.0] || -> . % 76.01/76.18 24097[45:Spt:24096.0,24091.0,24093.0] || m_main_v_state(s22,c_busy)* -> . % 76.01/76.18 24098[45:Spt:24096.0,24091.1] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.18 24102[45:Res:24098.0,61.1] always3(s23) || -> . % 76.01/76.18 24103[45:SSi:24102.0,712.0] || -> . % 76.01/76.18 24104[43:Spt:24103.0,23242.2,23246.0] || xuntil6(s21)*+ -> . % 76.01/76.18 24105[43:Spt:24103.0,23242.0,23242.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.01/76.18 24106[43:Res:53.1,24105.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.01/76.18 24111[44:Spt:24106.0] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.18 24113[44:Res:24111.0,61.1] always3(s21) || -> . % 76.01/76.18 24114[44:SSi:24113.0,710.0,23241.0] || -> . % 76.01/76.18 24115[44:Spt:24114.0,24106.0,24111.0] || m_main_v_state(s21,c_busy)* -> . % 76.01/76.18 24116[44:Spt:24114.0,24106.1] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.18 24120[44:Res:24116.0,61.1] always3(s22) || -> . % 76.01/76.18 24121[44:SSi:24120.0,711.0] || -> . % 76.01/76.18 24122[42:Spt:24121.0,23239.2,23240.0] || xuntil6(s20)*+ -> . % 76.01/76.18 24123[42:Spt:24121.0,23239.0,23239.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.01/76.18 24124[42:Res:53.1,24123.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.01/76.18 24126[43:Spt:24124.1] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.18 24128[43:Res:24126.0,61.1] always3(s21) || -> . % 76.01/76.18 24129[43:SSi:24128.0,710.0] || -> . % 76.01/76.18 24130[43:Spt:24129.0,24124.1,24126.0] || m_main_v_state(s21,c_busy)* -> . % 76.01/76.18 24131[43:Spt:24129.0,24124.0] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.18 24134[43:Res:24131.0,61.1] always3(s20) || -> . % 76.01/76.18 24135[43:SSi:24134.0,709.0,23238.0] || -> . % 76.01/76.18 24136[41:Spt:24135.0,23233.2,23237.0] || xuntil6(s19)*+ -> . % 76.01/76.18 24137[41:Spt:24135.0,23233.0,23233.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.01/76.18 24138[41:Res:53.1,24137.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.01/76.18 24140[42:Spt:24138.1] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.18 24142[42:Res:24140.0,61.1] always3(s20) || -> . % 76.01/76.18 24143[42:SSi:24142.0,709.0] || -> . % 76.01/76.18 24144[42:Spt:24143.0,24138.1,24140.0] || m_main_v_state(s20,c_busy)* -> . % 76.01/76.18 24145[42:Spt:24143.0,24138.0] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.18 24148[42:Res:24145.0,61.1] always3(s19) || -> . % 76.01/76.18 24149[42:SSi:24148.0,708.0,23232.0] || -> . % 76.01/76.18 24150[40:Spt:24149.0,23230.2,23231.0] || xuntil6(s18)*+ -> . % 76.01/76.18 24151[40:Spt:24149.0,23230.0,23230.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.01/76.18 24152[40:Res:53.1,24151.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.01/76.18 24157[41:Spt:24152.0] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.18 24159[41:Res:24157.0,61.1] always3(s18) || -> . % 76.01/76.18 24160[41:SSi:24159.0,707.0,23229.0] || -> . % 76.01/76.18 24161[41:Spt:24160.0,24152.0,24157.0] || m_main_v_state(s18,c_busy)* -> . % 76.01/76.18 24162[41:Spt:24160.0,24152.1] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.18 24166[41:Res:24162.0,61.1] always3(s19) || -> . % 76.01/76.18 24167[41:SSi:24166.0,708.0] || -> . % 76.01/76.18 24168[39:Spt:24167.0,23224.2,23228.0] || xuntil6(s17)*+ -> . % 76.01/76.18 24169[39:Spt:24167.0,23224.0,23224.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.01/76.18 24170[39:Res:53.1,24169.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.01/76.18 24172[40:Spt:24170.1] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.18 24174[40:Res:24172.0,61.1] always3(s18) || -> . % 76.01/76.18 24175[40:SSi:24174.0,707.0] || -> . % 76.01/76.18 24176[40:Spt:24175.0,24170.1,24172.0] || m_main_v_state(s18,c_busy)* -> . % 76.01/76.18 24177[40:Spt:24175.0,24170.0] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.18 24180[40:Res:24177.0,61.1] always3(s17) || -> . % 76.01/76.18 24181[40:SSi:24180.0,706.0,23223.0] || -> . % 76.01/76.18 24182[38:Spt:24181.0,23221.2,23222.0] || xuntil6(s16)*+ -> . % 76.01/76.18 24183[38:Spt:24181.0,23221.0,23221.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.01/76.18 24184[38:Res:53.1,24183.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.01/76.18 24186[39:Spt:24184.1] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.18 24188[39:Res:24186.0,61.1] always3(s17) || -> . % 76.01/76.18 24189[39:SSi:24188.0,706.0] || -> . % 76.01/76.18 24190[39:Spt:24189.0,24184.1,24186.0] || m_main_v_state(s17,c_busy)* -> . % 76.01/76.18 24191[39:Spt:24189.0,24184.0] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.18 24194[39:Res:24191.0,61.1] always3(s16) || -> . % 76.01/76.18 24195[39:SSi:24194.0,705.0,23220.0] || -> . % 76.01/76.18 24196[37:Spt:24195.0,23215.2,23219.0] || xuntil6(s15)*+ -> . % 76.01/76.18 24197[37:Spt:24195.0,23215.0,23215.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.01/76.18 24198[37:Res:53.1,24197.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.01/76.18 24203[38:Spt:24198.0] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.18 24205[38:Res:24203.0,61.1] always3(s15) || -> . % 76.01/76.18 24206[38:SSi:24205.0,704.0,23214.0] || -> . % 76.01/76.18 24207[38:Spt:24206.0,24198.0,24203.0] || m_main_v_state(s15,c_busy)* -> . % 76.01/76.18 24208[38:Spt:24206.0,24198.1] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.18 24212[38:Res:24208.0,61.1] always3(s16) || -> . % 76.01/76.18 24213[38:SSi:24212.0,705.0] || -> . % 76.01/76.18 24214[36:Spt:24213.0,23212.2,23213.0] || xuntil6(s14)*+ -> . % 76.01/76.18 24215[36:Spt:24213.0,23212.0,23212.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.01/76.18 24216[36:Res:53.1,24215.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.01/76.18 24218[37:Spt:24216.1] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.18 24220[37:Res:24218.0,61.1] always3(s15) || -> . % 76.01/76.18 24221[37:SSi:24220.0,704.0] || -> . % 76.01/76.18 24222[37:Spt:24221.0,24216.1,24218.0] || m_main_v_state(s15,c_busy)* -> . % 76.01/76.18 24223[37:Spt:24221.0,24216.0] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.18 24226[37:Res:24223.0,61.1] always3(s14) || -> . % 76.01/76.18 24227[37:SSi:24226.0,703.0,23211.0] || -> . % 76.01/76.18 24228[35:Spt:24227.0,23206.2,23210.0] || xuntil6(s13)*+ -> . % 76.01/76.18 24229[35:Spt:24227.0,23206.0,23206.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.01/76.18 24230[35:Res:53.1,24229.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.01/76.18 24232[36:Spt:24230.1] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.18 24234[36:Res:24232.0,61.1] always3(s14) || -> . % 76.01/76.18 24235[36:SSi:24234.0,703.0] || -> . % 76.01/76.18 24236[36:Spt:24235.0,24230.1,24232.0] || m_main_v_state(s14,c_busy)* -> . % 76.01/76.18 24237[36:Spt:24235.0,24230.0] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.18 24240[36:Res:24237.0,61.1] always3(s13) || -> . % 76.01/76.18 24241[36:SSi:24240.0,702.0,23205.0] || -> . % 76.01/76.18 24242[34:Spt:24241.0,23203.2,23204.0] || xuntil6(s12)*+ -> . % 76.01/76.18 24243[34:Spt:24241.0,23203.0,23203.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.01/76.18 24244[34:Res:53.1,24243.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.01/76.18 24249[35:Spt:24244.0] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.18 24251[35:Res:24249.0,61.1] always3(s12) || -> . % 76.01/76.18 24252[35:SSi:24251.0,701.0,23202.0] || -> . % 76.01/76.18 24253[35:Spt:24252.0,24244.0,24249.0] || m_main_v_state(s12,c_busy)* -> . % 76.01/76.18 24254[35:Spt:24252.0,24244.1] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.18 24258[35:Res:24254.0,61.1] always3(s13) || -> . % 76.01/76.18 24259[35:SSi:24258.0,702.0] || -> . % 76.01/76.18 24260[33:Spt:24259.0,23197.2,23201.0] || xuntil6(s11)*+ -> . % 76.01/76.18 24261[33:Spt:24259.0,23197.0,23197.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.01/76.18 24262[33:Res:53.1,24261.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.01/76.18 24264[34:Spt:24262.1] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.18 24266[34:Res:24264.0,61.1] always3(s12) || -> . % 76.01/76.18 24267[34:SSi:24266.0,701.0] || -> . % 76.01/76.18 24268[34:Spt:24267.0,24262.1,24264.0] || m_main_v_state(s12,c_busy)* -> . % 76.01/76.18 24269[34:Spt:24267.0,24262.0] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.18 24272[34:Res:24269.0,61.1] always3(s11) || -> . % 76.01/76.18 24273[34:SSi:24272.0,700.0,23196.0] || -> . % 76.01/76.18 24274[32:Spt:24273.0,23194.2,23195.0] || xuntil6(s10)*+ -> . % 76.01/76.18 24275[32:Spt:24273.0,23194.0,23194.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.01/76.18 24276[32:Res:53.1,24275.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.01/76.18 24278[33:Spt:24276.1] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.18 24280[33:Res:24278.0,61.1] always3(s11) || -> . % 76.01/76.18 24281[33:SSi:24280.0,700.0] || -> . % 76.01/76.18 24282[33:Spt:24281.0,24276.1,24278.0] || m_main_v_state(s11,c_busy)* -> . % 76.01/76.18 24283[33:Spt:24281.0,24276.0] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.18 24286[33:Res:24283.0,61.1] always3(s10) || -> . % 76.01/76.18 24287[33:SSi:24286.0,699.0,23193.0] || -> . % 76.01/76.18 24288[31:Spt:24287.0,23188.2,23192.0] || xuntil6(s9)*+ -> . % 76.01/76.18 24289[31:Spt:24287.0,23188.0,23188.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.01/76.18 24290[31:Res:53.1,24289.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.01/76.18 24295[32:Spt:24290.0] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.18 24297[32:Res:24295.0,61.1] always3(s9) || -> . % 76.01/76.18 24298[32:SSi:24297.0,698.0,23187.0] || -> . % 76.01/76.18 24299[32:Spt:24298.0,24290.0,24295.0] || m_main_v_state(s9,c_busy)* -> . % 76.01/76.18 24300[32:Spt:24298.0,24290.1] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.18 24304[32:Res:24300.0,61.1] always3(s10) || -> . % 76.01/76.18 24305[32:SSi:24304.0,699.0] || -> . % 76.01/76.18 24306[30:Spt:24305.0,23185.2,23186.0] || xuntil6(s8)*+ -> . % 76.01/76.18 24307[30:Spt:24305.0,23185.0,23185.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.01/76.18 24308[30:Res:53.1,24307.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.01/76.18 24310[31:Spt:24308.1] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.18 24312[31:Res:24310.0,61.1] always3(s9) || -> . % 76.01/76.18 24313[31:SSi:24312.0,698.0] || -> . % 76.01/76.18 24314[31:Spt:24313.0,24308.1,24310.0] || m_main_v_state(s9,c_busy)* -> . % 76.01/76.18 24315[31:Spt:24313.0,24308.0] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.18 24318[31:Res:24315.0,61.1] always3(s8) || -> . % 76.01/76.18 24319[31:SSi:24318.0,697.0,23184.0] || -> . % 76.01/76.18 24320[29:Spt:24319.0,23179.2,23183.0] || xuntil6(s7)*+ -> . % 76.01/76.18 24321[29:Spt:24319.0,23179.0,23179.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.01/76.18 24322[29:Res:53.1,24321.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.01/76.18 24324[30:Spt:24322.1] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.18 24326[30:Res:24324.0,61.1] always3(s8) || -> . % 76.01/76.18 24327[30:SSi:24326.0,697.0] || -> . % 76.01/76.18 24328[30:Spt:24327.0,24322.1,24324.0] || m_main_v_state(s8,c_busy)* -> . % 76.01/76.18 24329[30:Spt:24327.0,24322.0] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.18 24332[30:Res:24329.0,61.1] always3(s7) || -> . % 76.01/76.18 24333[30:SSi:24332.0,696.0,23178.0] || -> . % 76.01/76.18 24334[28:Spt:24333.0,23176.2,23177.0] || xuntil6(s6)*+ -> . % 76.01/76.18 24335[28:Spt:24333.0,23176.0,23176.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.01/76.18 24336[28:Res:53.1,24335.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.01/76.18 24341[29:Spt:24336.0] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.18 24343[29:Res:24341.0,61.1] always3(s6) || -> . % 76.01/76.18 24344[29:SSi:24343.0,695.0,23175.0] || -> . % 76.01/76.18 24345[29:Spt:24344.0,24336.0,24341.0] || m_main_v_state(s6,c_busy)* -> . % 76.01/76.18 24346[29:Spt:24344.0,24336.1] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.18 24350[29:Res:24346.0,61.1] always3(s7) || -> . % 76.01/76.18 24351[29:SSi:24350.0,696.0] || -> . % 76.01/76.18 24352[27:Spt:24351.0,23170.2,23174.0] || xuntil6(s5)*+ -> . % 76.01/76.18 24353[27:Spt:24351.0,23170.0,23170.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.01/76.18 24354[27:Res:53.1,24353.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.01/76.18 24356[28:Spt:24354.1] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.18 24358[28:Res:24356.0,61.1] always3(s6) || -> . % 76.01/76.18 24359[28:SSi:24358.0,695.0] || -> . % 76.01/76.18 24360[28:Spt:24359.0,24354.1,24356.0] || m_main_v_state(s6,c_busy)* -> . % 76.01/76.18 24361[28:Spt:24359.0,24354.0] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.18 24364[28:Res:24361.0,61.1] always3(s5) || -> . % 76.01/76.18 24365[28:SSi:24364.0,694.0,23169.0] || -> . % 76.01/76.18 24366[26:Spt:24365.0,23167.2,23168.0] || xuntil6(s4)*+ -> . % 76.01/76.18 24367[26:Spt:24365.0,23167.0,23167.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.01/76.18 24368[26:Res:53.1,24367.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.01/76.18 24370[27:Spt:24368.1] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.18 24372[27:Res:24370.0,61.1] always3(s5) || -> . % 76.01/76.18 24373[27:SSi:24372.0,694.0] || -> . % 76.01/76.18 24374[27:Spt:24373.0,24368.1,24370.0] || m_main_v_state(s5,c_busy)* -> . % 76.01/76.18 24375[27:Spt:24373.0,24368.0] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.18 24378[27:Res:24375.0,61.1] always3(s4) || -> . % 76.01/76.18 24379[27:SSi:24378.0,693.0,23166.0] || -> . % 76.01/76.18 24380[25:Spt:24379.0,23164.2,23165.0] || xuntil6(s3)*+ -> . % 76.01/76.18 24381[25:Spt:24379.0,23164.0,23164.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.01/76.18 24382[25:Res:53.1,24381.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.01/76.18 24387[26:Spt:24382.0] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.18 24389[26:Res:24387.0,61.1] always3(s3) || -> . % 76.01/76.18 24390[26:SSi:24389.0,692.0,23163.0] || -> . % 76.01/76.18 24391[26:Spt:24390.0,24382.0,24387.0] || m_main_v_state(s3,c_busy)* -> . % 76.01/76.18 24392[26:Spt:24390.0,24382.1] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.18 24396[26:Res:24392.0,61.1] always3(s4) || -> . % 76.01/76.18 24397[26:SSi:24396.0,693.0] || -> . % 76.01/76.18 24398[24:Spt:24397.0,23161.2,23162.0] || xuntil6(s2)*+ -> . % 76.01/76.18 24399[24:Spt:24397.0,23161.0,23161.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.01/76.18 24400[24:Res:53.1,24399.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.01/76.18 24402[25:Spt:24400.1] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.18 24404[25:Res:24402.0,61.1] always3(s3) || -> . % 76.01/76.18 24405[25:SSi:24404.0,692.0] || -> . % 76.01/76.18 24406[25:Spt:24405.0,24400.1,24402.0] || m_main_v_state(s3,c_busy)* -> . % 76.01/76.18 24407[25:Spt:24405.0,24400.0] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.18 24410[25:Res:24407.0,61.1] always3(s2) || -> . % 76.01/76.18 24411[25:SSi:24410.0,691.0,23160.0] || -> . % 76.01/76.18 24412[23:Spt:24411.0,23155.2,23159.0] || xuntil6(s1)*+ -> . % 76.01/76.18 24413[23:Spt:24411.0,23155.0,23155.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.01/76.18 24414[23:Res:53.1,24413.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.01/76.18 24416[24:Spt:24414.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.18 24418[24:Res:24416.0,61.1] always3(s1) || -> . % 76.01/76.18 24419[24:SSi:24418.0,690.0,23154.0] || -> . % 76.01/76.18 24420[24:Spt:24419.0,24414.0,24416.0] || m_main_v_state(s1,c_busy)* -> . % 76.01/76.18 24421[24:Spt:24419.0,24414.1] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.18 24426[24:Res:24421.0,61.1] always3(s2) || -> . % 76.01/76.18 24427[24:SSi:24426.0,691.0] || -> . % 76.01/76.18 24428[22:Spt:24427.0,74.0,23153.0] || xuntil6(s0)*+ -> . % 76.01/76.18 24429[22:Spt:24427.0,74.1] || -> node4(s0)*. % 76.01/76.18 24430[22:MRR:758.1,24428.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.18 24432[22:Res:24430.0,61.1] always3(s1) || -> . % 76.01/76.18 24433[22:SSi:24432.0,690.0] || -> . % 76.01/76.18 24434[21:Spt:24433.0,23143.0,23147.0] || trans(s49,s30)*+ -> . % 76.01/76.18 24435[21:Spt:24433.0,23143.1,23143.2,23143.3,23143.4,23143.5,23143.6,23143.7,23143.8,23143.9,23143.10,23143.11,23143.12,23143.13,23143.14,23143.15,23143.16,23143.17,23143.18,23143.19,23143.20,23143.21,23143.22,23143.23,23143.24,23143.25,23143.26,23143.27,23143.28,23143.29,23143.30] || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.01/76.18 24437[21:MRR:23144.0,24434.0] || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.01/76.18 24438[21:MRR:23146.1,24434.0] xuntil6(s49) || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.01/76.18 24439[22:Spt:24435.0] || -> trans(s49,s29)*. % 76.01/76.18 24440[22:Res:24439.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s29)*. % 76.01/76.18 24442[22:Res:24439.0,60.0] || -> node2(s49,s29)*. % 76.01/76.18 24443[22:SSi:24440.1,50.0,738.0] xuntil6(s49) || -> until2p7(s29)*. % 76.01/76.18 24444[22:Res:24442.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.01/76.18 24445[23:Spt:74.0] || -> xuntil6(s0)*. % 76.01/76.18 24446[23:MRR:176.0,24445.0] || -> until5(s1)*. % 76.01/76.18 24447[23:MRR:22143.0,24446.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.18 24451[24:Spt:24447.2] || -> xuntil6(s1)*. % 76.01/76.18 24452[24:MRR:175.0,24451.0] || -> until5(s2)*. % 76.01/76.18 24453[24:MRR:22142.0,24452.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.18 24457[25:Spt:24453.2] || -> xuntil6(s2)*. % 76.01/76.18 24458[25:MRR:174.0,24457.0] || -> until5(s3)*. % 76.01/76.18 24459[25:MRR:22135.0,24458.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.18 24460[26:Spt:24459.2] || -> xuntil6(s3)*. % 76.01/76.18 24461[26:MRR:173.0,24460.0] || -> until5(s4)*. % 76.01/76.18 24462[26:MRR:22131.0,24461.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.18 24466[27:Spt:24462.2] || -> xuntil6(s4)*. % 76.01/76.18 24467[27:MRR:172.0,24466.0] || -> until5(s5)*. % 76.01/76.18 24468[27:MRR:22127.0,24467.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.18 24469[28:Spt:24468.2] || -> xuntil6(s5)*. % 76.01/76.18 24470[28:MRR:171.0,24469.0] || -> until5(s6)*. % 76.01/76.18 24471[28:MRR:22123.0,24470.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.18 24475[29:Spt:24471.2] || -> xuntil6(s6)*. % 76.01/76.18 24476[29:MRR:170.0,24475.0] || -> until5(s7)*. % 76.01/76.18 24477[29:MRR:22122.0,24476.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.18 24478[30:Spt:24477.2] || -> xuntil6(s7)*. % 76.01/76.18 24479[30:MRR:169.0,24478.0] || -> until5(s8)*. % 76.01/76.18 24480[30:MRR:22115.0,24479.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.18 24484[31:Spt:24480.2] || -> xuntil6(s8)*. % 76.01/76.18 24485[31:MRR:168.0,24484.0] || -> until5(s9)*. % 76.01/76.18 24486[31:MRR:22111.0,24485.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.18 24487[32:Spt:24486.2] || -> xuntil6(s9)*. % 76.01/76.18 24488[32:MRR:167.0,24487.0] || -> until5(s10)*. % 76.01/76.18 24489[32:MRR:22107.0,24488.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.18 24493[33:Spt:24489.2] || -> xuntil6(s10)*. % 76.01/76.18 24494[33:MRR:166.0,24493.0] || -> until5(s11)*. % 76.01/76.18 24495[33:MRR:22103.0,24494.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.18 24496[34:Spt:24495.2] || -> xuntil6(s11)*. % 76.01/76.18 24497[34:MRR:165.0,24496.0] || -> until5(s12)*. % 76.01/76.18 24498[34:MRR:22102.0,24497.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.18 24502[35:Spt:24498.2] || -> xuntil6(s12)*. % 76.01/76.18 24503[35:MRR:164.0,24502.0] || -> until5(s13)*. % 76.01/76.18 24504[35:MRR:22095.0,24503.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.18 24505[36:Spt:24504.2] || -> xuntil6(s13)*. % 76.01/76.18 24506[36:MRR:163.0,24505.0] || -> until5(s14)*. % 76.01/76.18 24507[36:MRR:22091.0,24506.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.18 24511[37:Spt:24507.2] || -> xuntil6(s14)*. % 76.01/76.18 24512[37:MRR:162.0,24511.0] || -> until5(s15)*. % 76.01/76.18 24513[37:MRR:22087.0,24512.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.18 24514[38:Spt:24513.2] || -> xuntil6(s15)*. % 76.01/76.18 24515[38:MRR:161.0,24514.0] || -> until5(s16)*. % 76.01/76.18 24516[38:MRR:22083.0,24515.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.18 24520[39:Spt:24516.2] || -> xuntil6(s16)*. % 76.01/76.18 24521[39:MRR:160.0,24520.0] || -> until5(s17)*. % 76.01/76.18 24522[39:MRR:22082.0,24521.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.18 24523[40:Spt:24522.2] || -> xuntil6(s17)*. % 76.01/76.18 24524[40:MRR:159.0,24523.0] || -> until5(s18)*. % 76.01/76.18 24525[40:MRR:22075.0,24524.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.18 24529[41:Spt:24525.2] || -> xuntil6(s18)*. % 76.01/76.18 24530[41:MRR:158.0,24529.0] || -> until5(s19)*. % 76.01/76.18 24531[41:MRR:22071.0,24530.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.18 24532[42:Spt:24531.2] || -> xuntil6(s19)*. % 76.01/76.18 24533[42:MRR:157.0,24532.0] || -> until5(s20)*. % 76.01/76.18 24534[42:MRR:22067.0,24533.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.18 24538[43:Spt:24534.2] || -> xuntil6(s20)*. % 76.01/76.18 24539[43:MRR:156.0,24538.0] || -> until5(s21)*. % 76.01/76.18 24540[43:MRR:22063.0,24539.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.18 24541[44:Spt:24540.2] || -> xuntil6(s21)*. % 76.01/76.18 24542[44:MRR:155.0,24541.0] || -> until5(s22)*. % 76.01/76.18 24543[44:MRR:22062.0,24542.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.18 24547[45:Spt:24543.2] || -> xuntil6(s22)*. % 76.01/76.18 24548[45:MRR:154.0,24547.0] || -> until5(s23)*. % 76.01/76.18 24549[45:MRR:22055.0,24548.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.18 24550[46:Spt:24549.2] || -> xuntil6(s23)*. % 76.01/76.18 24551[46:MRR:153.0,24550.0] || -> until5(s24)*. % 76.01/76.18 24552[46:MRR:22051.0,24551.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.18 24556[47:Spt:24552.2] || -> xuntil6(s24)*. % 76.01/76.18 24557[47:MRR:152.0,24556.0] || -> until5(s25)*. % 76.01/76.18 24558[47:MRR:22047.0,24557.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.18 24559[48:Spt:24558.2] || -> xuntil6(s25)*. % 76.01/76.18 24560[48:MRR:151.0,24559.0] || -> until5(s26)*. % 76.01/76.18 24561[48:MRR:22043.0,24560.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.18 24565[49:Spt:24561.2] || -> xuntil6(s26)*. % 76.01/76.18 24566[49:MRR:150.0,24565.0] || -> until5(s27)*. % 76.01/76.18 24567[49:MRR:22042.0,24566.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.18 24568[50:Spt:24567.2] || -> xuntil6(s27)*. % 76.01/76.18 24569[50:MRR:149.0,24568.0] || -> until5(s28)*. % 76.01/76.18 24570[50:MRR:22034.0,24569.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.18 24574[51:Spt:24570.2] || -> xuntil6(s28)*. % 76.01/76.18 24575[51:MRR:148.0,24574.0] || -> until5(s29)*. % 76.01/76.18 24576[51:MRR:22035.0,24575.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.18 24577[52:Spt:24576.2] || -> xuntil6(s29)*. % 76.01/76.18 24578[52:MRR:147.0,24577.0] || -> until5(s30)*. % 76.01/76.18 24579[52:MRR:22029.0,24578.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.18 24583[53:Spt:24579.2] || -> xuntil6(s30)*. % 76.01/76.18 24584[53:MRR:146.0,24583.0] || -> until5(s31)*. % 76.01/76.18 24585[53:MRR:22033.0,24584.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.18 24586[54:Spt:24585.2] || -> xuntil6(s31)*. % 76.01/76.18 24587[54:MRR:145.0,24586.0] || -> until5(s32)*. % 76.01/76.18 24588[54:MRR:19324.0,24587.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.18 24592[55:Spt:24588.1] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.18 24594[55:Res:24592.0,61.1] always3(s33) || -> . % 76.01/76.18 24595[55:SSi:24594.0,722.0] || -> . % 76.01/76.18 24596[55:Spt:24595.0,24588.1,24592.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.01/76.18 24597[55:Spt:24595.0,24588.0,24588.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 76.01/76.18 24599[55:MRR:822.2,24596.0] node4(s32) || m_main_v_state(s32,c_ready)* -> . % 76.01/76.18 24600[55:Res:53.1,24597.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 76.01/76.18 24602[56:Spt:24600.1] || -> xuntil6(s32)*. % 76.01/76.18 24603[56:MRR:144.0,24602.0] || -> until5(s33)*. % 76.01/76.18 24604[56:MRR:22147.0,24603.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.18 24609[57:Spt:24604.2] || -> xuntil6(s33)*. % 76.01/76.18 24610[57:MRR:143.0,24609.0] || -> until5(s34)*. % 76.01/76.18 24611[57:MRR:16857.0,24610.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.18 24612[58:Spt:24611.1] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.18 24614[58:Res:24612.0,61.1] always3(s35) || -> . % 76.01/76.18 24615[58:SSi:24614.0,724.0] || -> . % 76.01/76.18 24616[58:Spt:24615.0,24611.1,24612.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.01/76.18 24617[58:Spt:24615.0,24611.0,24611.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 76.01/76.18 24619[58:MRR:816.2,24616.0] node4(s34) || m_main_v_state(s34,c_ready)* -> . % 76.01/76.18 24620[58:Res:53.1,24617.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 76.01/76.18 24622[59:Spt:24620.1] || -> xuntil6(s34)*. % 76.01/76.18 24623[59:MRR:142.0,24622.0] || -> until5(s35)*. % 76.01/76.18 24624[59:MRR:22151.0,24623.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.18 24632[60:Spt:24624.2] || -> xuntil6(s35)*. % 76.01/76.18 24633[60:MRR:141.0,24632.0] || -> until5(s36)*. % 76.01/76.18 24634[60:MRR:16858.0,24633.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.18 24635[61:Spt:24634.1] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.18 24637[61:Res:24635.0,61.1] always3(s37) || -> . % 76.01/76.18 24638[61:SSi:24637.0,726.0] || -> . % 76.01/76.18 24639[61:Spt:24638.0,24634.1,24635.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.01/76.18 24640[61:Spt:24638.0,24634.0,24634.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 76.01/76.18 24642[61:MRR:810.2,24639.0] node4(s36) || m_main_v_state(s36,c_ready)* -> . % 76.01/76.18 24643[61:Res:53.1,24640.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 76.01/76.18 24648[62:Spt:24643.1] || -> xuntil6(s36)*. % 76.01/76.18 24649[62:MRR:140.0,24648.0] || -> until5(s37)*. % 76.01/76.18 24650[62:MRR:22155.0,24649.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.18 24652[63:Spt:24650.2] || -> xuntil6(s37)*. % 76.01/76.18 24653[63:MRR:139.0,24652.0] || -> until5(s38)*. % 76.01/76.18 24654[63:MRR:16862.0,24653.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.18 24655[64:Spt:24654.1] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.18 24657[64:Res:24655.0,61.1] always3(s39) || -> . % 76.01/76.18 24658[64:SSi:24657.0,728.0] || -> . % 76.01/76.18 24659[64:Spt:24658.0,24654.1,24655.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.01/76.18 24660[64:Spt:24658.0,24654.0,24654.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 76.01/76.18 24662[64:MRR:804.2,24659.0] node4(s38) || m_main_v_state(s38,c_ready)* -> . % 76.01/76.18 24663[64:Res:53.1,24660.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 76.01/76.18 24665[65:Spt:24663.1] || -> xuntil6(s38)*. % 76.01/76.18 24666[65:MRR:138.0,24665.0] || -> until5(s39)*. % 76.01/76.18 24667[65:MRR:22162.0,24666.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.18 24672[66:Spt:24667.2] || -> xuntil6(s39)*. % 76.01/76.18 24673[66:MRR:137.0,24672.0] || -> until5(s40)*. % 76.01/76.18 24674[66:MRR:16866.0,24673.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.01/76.18 24675[67:Spt:24674.1] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.18 24677[67:Res:24675.0,61.1] always3(s41) || -> . % 76.01/76.18 24678[67:SSi:24677.0,730.0] || -> . % 76.01/76.18 24679[67:Spt:24678.0,24674.1,24675.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.01/76.18 24680[67:Spt:24678.0,24674.0,24674.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 76.01/76.18 24682[67:MRR:798.2,24679.0] node4(s40) || m_main_v_state(s40,c_ready)* -> . % 76.01/76.18 24683[67:Res:53.1,24680.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 76.01/76.18 24685[68:Spt:24683.1] || -> xuntil6(s40)*. % 76.01/76.18 24686[68:MRR:136.0,24685.0] || -> until5(s41)*. % 76.01/76.18 24687[68:MRR:22163.0,24686.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.18 24695[69:Spt:24687.2] || -> xuntil6(s41)*. % 76.01/76.19 24696[69:MRR:135.0,24695.0] || -> until5(s42)*. % 76.01/76.19 24697[69:MRR:16870.0,24696.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.01/76.19 24698[70:Spt:24697.1] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.19 24700[70:Res:24698.0,61.1] always3(s43) || -> . % 76.01/76.19 24701[70:SSi:24700.0,732.0] || -> . % 76.01/76.19 24702[70:Spt:24701.0,24697.1,24698.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.01/76.19 24703[70:Spt:24701.0,24697.0,24697.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 76.01/76.19 24705[70:MRR:792.2,24702.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 76.01/76.19 24706[70:Res:53.1,24703.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 76.01/76.19 24711[71:Spt:24706.1] || -> xuntil6(s42)*. % 76.01/76.19 24712[71:MRR:134.0,24711.0] || -> until5(s43)*. % 76.01/76.19 24713[71:MRR:22167.0,24712.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.19 24715[72:Spt:24713.2] || -> xuntil6(s43)*. % 76.01/76.19 24716[72:MRR:133.0,24715.0] || -> until5(s44)*. % 76.01/76.19 24717[72:MRR:16877.0,24716.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.01/76.19 24718[73:Spt:24717.1] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.19 24720[73:Res:24718.0,61.1] always3(s45) || -> . % 76.01/76.19 24721[73:SSi:24720.0,734.0] || -> . % 76.01/76.19 24722[73:Spt:24721.0,24717.1,24718.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.01/76.19 24723[73:Spt:24721.0,24717.0,24717.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 76.01/76.19 24725[73:MRR:786.2,24722.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 76.01/76.19 24726[73:Res:53.1,24723.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 76.01/76.19 24728[74:Spt:24726.1] || -> xuntil6(s44)*. % 76.01/76.19 24729[74:MRR:132.0,24728.0] || -> until5(s45)*. % 76.01/76.19 24730[74:MRR:22171.0,24729.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.19 24735[75:Spt:24730.2] || -> xuntil6(s45)*. % 76.01/76.19 24736[75:MRR:131.0,24735.0] || -> until5(s46)*. % 76.01/76.19 24737[75:MRR:16878.0,24736.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.01/76.19 24738[76:Spt:24737.1] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.19 24740[76:Res:24738.0,61.1] always3(s47) || -> . % 76.01/76.19 24741[76:SSi:24740.0,736.0] || -> . % 76.01/76.19 24742[76:Spt:24741.0,24737.1,24738.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.01/76.19 24743[76:Spt:24741.0,24737.0,24737.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 76.01/76.19 24745[76:MRR:780.2,24742.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 76.01/76.19 24746[76:Res:53.1,24743.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 76.01/76.19 24748[77:Spt:24746.1] || -> xuntil6(s46)*. % 76.01/76.19 24749[77:MRR:130.0,24748.0] || -> until5(s47)*. % 76.01/76.19 24750[77:MRR:22175.0,24749.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.19 24758[78:Spt:24750.2] || -> xuntil6(s47)*. % 76.01/76.19 24759[78:MRR:129.0,24758.0] || -> until5(s48)*. % 76.01/76.19 24760[78:MRR:16882.0,24759.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.01/76.19 24761[79:Spt:24760.1] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.19 24763[79:Res:24761.0,61.1] always3(s49) || -> . % 76.01/76.19 24764[79:SSi:24763.0,50.0,738.0] || -> . % 76.01/76.19 24765[79:Spt:24764.0,24760.1,24761.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.01/76.19 24766[79:Spt:24764.0,24760.0,24760.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 76.01/76.19 24768[79:MRR:774.2,24765.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.01/76.19 24769[79:Res:53.1,24766.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 76.01/76.19 24774[80:Spt:24769.1] || -> xuntil6(s48)*. % 76.01/76.19 24775[80:MRR:128.0,24774.0] || -> until5(s49)*. % 76.01/76.19 24777[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.19 24781[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.19 24782[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.19 24783[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.19 24790[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.19 24791[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.19 24795[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.19 24799[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.19 24803[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.19 24810[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.19 24811[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.19 24815[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.19 24819[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.19 24823[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.19 24830[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.19 24831[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.19 24835[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.19 24839[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.19 24843[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.19 24850[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.19 24851[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.19 24855[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.19 24859[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.19 24863[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.19 24870[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.19 24871[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.19 24875[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.19 24879[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.19 24883[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.19 24890[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.19 24891[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.19 24895[0:SoR:819.0,66.2] until5(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.19 24899[0:SoR:813.0,66.2] until5(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.19 24903[0:SoR:807.0,66.2] until5(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.19 24910[0:SoR:801.0,66.2] until5(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.19 24911[0:SoR:795.0,66.2] until5(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.19 24915[0:SoR:789.0,66.2] until5(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.19 24919[0:SoR:783.0,66.2] until5(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.19 24923[0:SoR:777.0,66.2] until5(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.19 24925[22:SoR:24444.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.01/76.19 24927[22:SoR:24925.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.01/76.19 24928[80:SSi:24927.0,50.0,738.0,24775.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.01/76.19 24929[81:Spt:24928.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.19 24931[81:Res:24929.0,61.1] always3(s29) || -> . % 76.01/76.19 24932[81:SSi:24931.0,718.0,24575.0,24577.0] || -> . % 76.01/76.19 24933[81:Spt:24932.0,24928.1,24929.0] || m_main_v_state(s29,c_busy)*+ -> . % 76.01/76.19 24934[81:Spt:24932.0,24928.0,24928.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.01/76.19 24938[81:MRR:24925.2,24933.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.01/76.19 24939[81:Res:53.1,24934.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.01/76.19 24941[81:MRR:24939.0,24765.0] || -> xuntil6(s49)*. % 76.01/76.19 24942[81:MRR:24443.0,24941.0] || -> until2p7(s29)*. % 76.01/76.19 24943[81:MRR:225.0,24942.0] || -> until2p7(s30)* node4(s29). % 76.01/76.19 24944[82:Spt:24943.0] || -> until2p7(s30)*. % 76.01/76.19 24945[82:MRR:226.0,24944.0] || -> until2p7(s31)* node4(s30). % 76.01/76.19 24946[83:Spt:24945.0] || -> until2p7(s31)*. % 76.01/76.19 24947[83:MRR:227.0,24946.0] || -> until2p7(s32)* node4(s31). % 76.01/76.19 24948[84:Spt:24947.0] || -> until2p7(s32)*. % 76.01/76.19 24949[84:MRR:228.0,24948.0] || -> until2p7(s33)* node4(s32). % 76.01/76.19 24950[85:Spt:24949.0] || -> until2p7(s33)*. % 76.01/76.19 24951[85:MRR:229.0,24950.0] || -> until2p7(s34)* node4(s33). % 76.01/76.19 24952[86:Spt:24951.0] || -> until2p7(s34)*. % 76.01/76.19 24953[86:MRR:230.0,24952.0] || -> until2p7(s35)* node4(s34). % 76.01/76.19 24954[87:Spt:24953.0] || -> until2p7(s35)*. % 76.01/76.19 24955[87:MRR:231.0,24954.0] || -> until2p7(s36)* node4(s35). % 76.01/76.19 24956[88:Spt:24955.0] || -> until2p7(s36)*. % 76.01/76.19 24957[88:MRR:232.0,24956.0] || -> until2p7(s37)* node4(s36). % 76.01/76.19 24958[89:Spt:24957.0] || -> until2p7(s37)*. % 76.01/76.19 24959[89:MRR:235.0,24958.0] || -> until2p7(s38)* node4(s37). % 76.01/76.19 24960[90:Spt:24959.0] || -> until2p7(s38)*. % 76.01/76.19 24961[90:MRR:236.0,24960.0] || -> until2p7(s39)* node4(s38). % 76.01/76.19 24962[91:Spt:24961.0] || -> until2p7(s39)*. % 76.01/76.19 24963[91:MRR:237.0,24962.0] || -> until2p7(s40)* node4(s39). % 76.01/76.19 24964[92:Spt:24963.0] || -> until2p7(s40)*. % 76.01/76.19 24965[92:MRR:238.0,24964.0] || -> until2p7(s41)* node4(s40). % 76.01/76.19 24966[93:Spt:24965.0] || -> until2p7(s41)*. % 76.01/76.19 24967[93:MRR:239.0,24966.0] || -> until2p7(s42)* node4(s41). % 76.01/76.19 24968[94:Spt:24967.0] || -> until2p7(s42)*. % 76.01/76.19 24969[94:MRR:240.0,24968.0] || -> until2p7(s43)* node4(s42). % 76.01/76.19 24970[95:Spt:24969.0] || -> until2p7(s43)*. % 76.01/76.19 24971[95:MRR:241.0,24970.0] || -> until2p7(s44)* node4(s43). % 76.01/76.19 24972[96:Spt:24971.0] || -> until2p7(s44)*. % 76.01/76.19 24973[96:MRR:539.0,24972.0] || -> until2p7(s45)* node4(s44). % 76.01/76.19 24974[97:Spt:24973.0] || -> until2p7(s45)*. % 76.01/76.19 24975[97:MRR:544.0,24974.0] || -> until2p7(s46)* node4(s45). % 76.01/76.19 24976[98:Spt:24975.0] || -> until2p7(s46)*. % 76.01/76.19 24977[98:MRR:549.0,24976.0] || -> until2p7(s47)* node4(s46). % 76.01/76.19 24978[99:Spt:24977.0] || -> until2p7(s47)*. % 76.01/76.19 24979[99:MRR:554.0,24978.0] || -> until2p7(s48)* node4(s47). % 76.01/76.19 24980[100:Spt:24979.0] || -> until2p7(s48)*. % 76.01/76.19 24981[100:MRR:559.0,24980.0] || -> until2p7(s49)* node4(s48). % 76.01/76.19 24982[101:Spt:24981.0] || -> until2p7(s49)*. % 76.01/76.19 24983[101:MRR:194.0,24982.0] || -> node4(s49)*. % 76.01/76.19 24984[101:MRR:24938.0,24983.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.01/76.19 24985[101:Res:53.1,24984.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.19 24987[101:MRR:24985.0,24765.0] || -> . % 76.01/76.19 24988[101:Spt:24987.0,24981.0,24982.0] || until2p7(s49)*+ -> . % 76.01/76.19 24989[101:Spt:24987.0,24981.1] || -> node4(s48)*. % 76.01/76.19 24990[101:MRR:24768.0,24989.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.01/76.19 24993[101:Res:53.1,24990.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.19 24996[101:Res:24993.0,61.1] always3(s48) || -> . % 76.01/76.19 24997[101:SSi:24996.0,737.0,24759.0,24774.0,24980.0,24989.0] || -> . % 76.01/76.19 24998[100:Spt:24997.0,24979.0,24980.0] || until2p7(s48)*+ -> . % 76.01/76.19 24999[100:Spt:24997.0,24979.1] || -> node4(s47)*. % 76.01/76.19 25001[100:MRR:777.0,24999.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.01/76.19 25016[100:Res:53.1,25001.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.01/76.19 25018[100:MRR:25016.0,24742.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.19 25020[100:Res:25018.0,61.1] always3(s48) || -> . % 76.01/76.19 25021[100:SSi:25020.0,737.0,24759.0,24774.0] || -> . % 76.01/76.19 25022[99:Spt:25021.0,24977.0,24978.0] || until2p7(s47)*+ -> . % 76.01/76.19 25023[99:Spt:25021.0,24977.1] || -> node4(s46)*. % 76.01/76.19 25024[99:MRR:24745.0,25023.0] || m_main_v_state(s46,c_ready)*+ -> . % 76.01/76.19 25027[99:Res:53.1,25024.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.19 25030[99:Res:25027.0,61.1] always3(s46) || -> . % 76.01/76.19 25031[99:SSi:25030.0,735.0,24736.0,24748.0,24976.0,25023.0] || -> . % 76.01/76.19 25032[98:Spt:25031.0,24975.0,24976.0] || until2p7(s46)*+ -> . % 76.01/76.19 25033[98:Spt:25031.0,24975.1] || -> node4(s45)*. % 76.01/76.19 25035[98:MRR:783.0,25033.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.01/76.19 25047[98:Res:53.1,25035.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.01/76.19 25049[98:MRR:25047.0,24722.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.19 25051[98:Res:25049.0,61.1] always3(s46) || -> . % 76.01/76.19 25052[98:SSi:25051.0,735.0,24736.0,24748.0] || -> . % 76.01/76.19 25053[97:Spt:25052.0,24973.0,24974.0] || until2p7(s45)*+ -> . % 76.01/76.19 25054[97:Spt:25052.0,24973.1] || -> node4(s44)*. % 76.01/76.19 25055[97:MRR:24725.0,25054.0] || m_main_v_state(s44,c_ready)*+ -> . % 76.01/76.19 25058[97:Res:53.1,25055.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.19 25061[97:Res:25058.0,61.1] always3(s44) || -> . % 76.01/76.19 25062[97:SSi:25061.0,733.0,24716.0,24728.0,24972.0,25054.0] || -> . % 76.01/76.19 25063[96:Spt:25062.0,24971.0,24972.0] || until2p7(s44)*+ -> . % 76.01/76.19 25064[96:Spt:25062.0,24971.1] || -> node4(s43)*. % 76.01/76.19 25066[96:MRR:789.0,25064.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.01/76.19 25078[96:Res:53.1,25066.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.01/76.19 25080[96:MRR:25078.0,24702.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.19 25085[96:Res:25080.0,61.1] always3(s44) || -> . % 76.01/76.19 25086[96:SSi:25085.0,733.0,24716.0,24728.0] || -> . % 76.01/76.19 25087[95:Spt:25086.0,24969.0,24970.0] || until2p7(s43)*+ -> . % 76.01/76.19 25088[95:Spt:25086.0,24969.1] || -> node4(s42)*. % 76.01/76.19 25089[95:MRR:24705.0,25088.0] || m_main_v_state(s42,c_ready)*+ -> . % 76.01/76.19 25092[95:Res:53.1,25089.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.19 25096[95:Res:25092.0,61.1] always3(s42) || -> . % 76.01/76.19 25097[95:SSi:25096.0,731.0,24696.0,24711.0,24968.0,25088.0] || -> . % 76.01/76.19 25098[94:Spt:25097.0,24967.0,24968.0] || until2p7(s42)*+ -> . % 76.01/76.19 25099[94:Spt:25097.0,24967.1] || -> node4(s41)*. % 76.01/76.19 25101[94:MRR:795.0,25099.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.01/76.19 25112[94:Res:53.1,25101.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.01/76.19 25114[94:MRR:25112.0,24679.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.19 25116[94:Res:25114.0,61.1] always3(s42) || -> . % 76.01/76.19 25117[94:SSi:25116.0,731.0,24696.0,24711.0] || -> . % 76.01/76.19 25118[93:Spt:25117.0,24965.0,24966.0] || until2p7(s41)*+ -> . % 76.01/76.19 25119[93:Spt:25117.0,24965.1] || -> node4(s40)*. % 76.01/76.19 25120[93:MRR:24682.0,25119.0] || m_main_v_state(s40,c_ready)*+ -> . % 76.01/76.19 25124[93:Res:53.1,25120.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.19 25127[93:Res:25124.0,61.1] always3(s40) || -> . % 76.01/76.19 25128[93:SSi:25127.0,729.0,24673.0,24685.0,24964.0,25119.0] || -> . % 76.01/76.19 25129[92:Spt:25128.0,24963.0,24964.0] || until2p7(s40)*+ -> . % 76.01/76.19 25130[92:Spt:25128.0,24963.1] || -> node4(s39)*. % 76.01/76.19 25132[92:MRR:801.0,25130.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.01/76.19 25143[92:Res:53.1,25132.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.01/76.19 25145[92:MRR:25143.0,24659.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.19 25147[92:Res:25145.0,61.1] always3(s40) || -> . % 76.01/76.19 25148[92:SSi:25147.0,729.0,24673.0,24685.0] || -> . % 76.01/76.19 25149[91:Spt:25148.0,24961.0,24962.0] || until2p7(s39)*+ -> . % 76.01/76.19 25150[91:Spt:25148.0,24961.1] || -> node4(s38)*. % 76.01/76.19 25151[91:MRR:24662.0,25150.0] || m_main_v_state(s38,c_ready)*+ -> . % 76.01/76.19 25154[91:Res:53.1,25151.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.19 25157[91:Res:25154.0,61.1] always3(s38) || -> . % 76.01/76.19 25158[91:SSi:25157.0,727.0,24653.0,24665.0,24960.0,25150.0] || -> . % 76.01/76.19 25159[90:Spt:25158.0,24959.0,24960.0] || until2p7(s38)*+ -> . % 76.01/76.19 25160[90:Spt:25158.0,24959.1] || -> node4(s37)*. % 76.01/76.19 25162[90:MRR:807.0,25160.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.01/76.19 25174[90:Res:53.1,25162.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.01/76.19 25176[90:MRR:25174.0,24639.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.19 25178[90:Res:25176.0,61.1] always3(s38) || -> . % 76.01/76.19 25179[90:SSi:25178.0,727.0,24653.0,24665.0] || -> . % 76.01/76.19 25180[89:Spt:25179.0,24957.0,24958.0] || until2p7(s37)*+ -> . % 76.01/76.19 25181[89:Spt:25179.0,24957.1] || -> node4(s36)*. % 76.01/76.19 25182[89:MRR:24642.0,25181.0] || m_main_v_state(s36,c_ready)*+ -> . % 76.01/76.19 25185[89:Res:53.1,25182.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.19 25188[89:Res:25185.0,61.1] always3(s36) || -> . % 76.01/76.19 25189[89:SSi:25188.0,725.0,24633.0,24648.0,24956.0,25181.0] || -> . % 76.01/76.19 25190[88:Spt:25189.0,24955.0,24956.0] || until2p7(s36)*+ -> . % 76.01/76.19 25191[88:Spt:25189.0,24955.1] || -> node4(s35)*. % 76.01/76.19 25193[88:MRR:813.0,25191.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.01/76.19 25205[88:Res:53.1,25193.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.01/76.19 25207[88:MRR:25205.0,24616.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.19 25212[88:Res:25207.0,61.1] always3(s36) || -> . % 76.01/76.19 25213[88:SSi:25212.0,725.0,24633.0,24648.0] || -> . % 76.01/76.19 25214[87:Spt:25213.0,24953.0,24954.0] || until2p7(s35)*+ -> . % 76.01/76.19 25215[87:Spt:25213.0,24953.1] || -> node4(s34)*. % 76.01/76.19 25216[87:MRR:24619.0,25215.0] || m_main_v_state(s34,c_ready)*+ -> . % 76.01/76.19 25219[87:Res:53.1,25216.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.19 25223[87:Res:25219.0,61.1] always3(s34) || -> . % 76.01/76.19 25224[87:SSi:25223.0,723.0,24610.0,24622.0,24952.0,25215.0] || -> . % 76.01/76.19 25225[86:Spt:25224.0,24951.0,24952.0] || until2p7(s34)*+ -> . % 76.01/76.19 25226[86:Spt:25224.0,24951.1] || -> node4(s33)*. % 76.01/76.19 25228[86:MRR:819.0,25226.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.01/76.19 25239[86:Res:53.1,25228.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.01/76.19 25241[86:MRR:25239.0,24596.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.19 25243[86:Res:25241.0,61.1] always3(s34) || -> . % 76.01/76.19 25244[86:SSi:25243.0,723.0,24610.0,24622.0] || -> . % 76.01/76.19 25245[85:Spt:25244.0,24949.0,24950.0] || until2p7(s33)*+ -> . % 76.01/76.19 25246[85:Spt:25244.0,24949.1] || -> node4(s32)*. % 76.01/76.19 25247[85:MRR:24599.0,25246.0] || m_main_v_state(s32,c_ready)*+ -> . % 76.01/76.19 25251[85:Res:53.1,25247.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.19 25254[85:Res:25251.0,61.1] always3(s32) || -> . % 76.01/76.19 25255[85:SSi:25254.0,721.0,24587.0,24602.0,24948.0,25246.0] || -> . % 76.01/76.19 25256[84:Spt:25255.0,24947.0,24948.0] || until2p7(s32)*+ -> . % 76.01/76.19 25257[84:Spt:25255.0,24947.1] || -> node4(s31)*. % 76.01/76.19 25259[84:MRR:825.0,25257.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.01/76.19 25270[84:Res:53.1,25259.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.01/76.19 25272[85:Spt:25270.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.19 25274[85:Res:25272.0,61.1] always3(s31) || -> . % 76.01/76.19 25275[85:SSi:25274.0,720.0,24584.0,24586.0,24946.0,25257.0] || -> . % 76.01/76.19 25276[85:Spt:25275.0,25270.0,25272.0] || m_main_v_state(s31,c_busy)* -> . % 76.01/76.19 25277[85:Spt:25275.0,25270.1] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.19 25281[85:Res:25277.0,61.1] always3(s32) || -> . % 76.01/76.19 25282[85:SSi:25281.0,721.0,24587.0,24602.0] || -> . % 76.01/76.19 25283[83:Spt:25282.0,24945.0,24946.0] || until2p7(s31)*+ -> . % 76.01/76.19 25284[83:Spt:25282.0,24945.1] || -> node4(s30)*. % 76.01/76.19 25286[83:MRR:828.0,25284.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.01/76.19 25296[83:Res:53.1,25286.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.01/76.19 25298[84:Spt:25296.0] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.19 25300[84:Res:25298.0,61.1] always3(s30) || -> . % 76.01/76.19 25301[84:SSi:25300.0,719.0,24578.0,24583.0,24944.0,25284.0] || -> . % 76.01/76.19 25302[84:Spt:25301.0,25296.0,25298.0] || m_main_v_state(s30,c_busy)* -> . % 76.01/76.19 25303[84:Spt:25301.0,25296.1] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.19 25307[84:Res:25303.0,61.1] always3(s31) || -> . % 76.01/76.19 25308[84:SSi:25307.0,720.0,24584.0,24586.0] || -> . % 76.01/76.19 25309[82:Spt:25308.0,24943.0,24944.0] || until2p7(s30)*+ -> . % 76.01/76.19 25310[82:Spt:25308.0,24943.1] || -> node4(s29)*. % 76.01/76.19 25312[82:MRR:831.0,25310.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.01/76.19 25315[82:Res:53.1,25312.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.01/76.19 25317[82:MRR:25315.0,24933.0] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.19 25319[82:Res:25317.0,61.1] always3(s30) || -> . % 76.01/76.19 25320[82:SSi:25319.0,719.0,24578.0,24583.0] || -> . % 76.01/76.19 25321[80:Spt:25320.0,24769.1,24774.0] || xuntil6(s48)* -> . % 76.01/76.19 25322[80:Spt:25320.0,24769.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.19 25325[80:Res:25322.0,61.1] always3(s48) || -> . % 76.01/76.19 25326[80:SSi:25325.0,737.0,24759.0] || -> . % 76.01/76.19 25327[78:Spt:25326.0,24750.2,24758.0] || xuntil6(s47)*+ -> . % 76.01/76.19 25328[78:Spt:25326.0,24750.0,24750.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.01/76.19 25329[78:Res:53.1,25328.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.01/76.19 25331[78:MRR:25329.0,24742.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.19 25334[78:Res:25331.0,61.1] always3(s48) || -> . % 76.01/76.19 25335[78:SSi:25334.0,737.0] || -> . % 76.01/76.19 25336[77:Spt:25335.0,24746.1,24748.0] || xuntil6(s46)* -> . % 76.01/76.19 25337[77:Spt:25335.0,24746.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.19 25340[77:Res:25337.0,61.1] always3(s46) || -> . % 76.01/76.19 25341[77:SSi:25340.0,735.0,24736.0] || -> . % 76.01/76.19 25342[75:Spt:25341.0,24730.2,24735.0] || xuntil6(s45)*+ -> . % 76.01/76.19 25343[75:Spt:25341.0,24730.0,24730.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.01/76.19 25344[75:Res:53.1,25343.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.01/76.19 25346[75:MRR:25344.0,24722.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.19 25348[75:Res:25346.0,61.1] always3(s46) || -> . % 76.01/76.19 25349[75:SSi:25348.0,735.0] || -> . % 76.01/76.19 25350[74:Spt:25349.0,24726.1,24728.0] || xuntil6(s44)* -> . % 76.01/76.19 25351[74:Spt:25349.0,24726.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.19 25354[74:Res:25351.0,61.1] always3(s44) || -> . % 76.01/76.19 25355[74:SSi:25354.0,733.0,24716.0] || -> . % 76.01/76.19 25356[72:Spt:25355.0,24713.2,24715.0] || xuntil6(s43)*+ -> . % 76.01/76.19 25357[72:Spt:25355.0,24713.0,24713.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.01/76.19 25358[72:Res:53.1,25357.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.01/76.19 25360[72:MRR:25358.0,24702.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.19 25363[72:Res:25360.0,61.1] always3(s44) || -> . % 76.01/76.19 25364[72:SSi:25363.0,733.0] || -> . % 76.01/76.19 25365[71:Spt:25364.0,24706.1,24711.0] || xuntil6(s42)* -> . % 76.01/76.19 25366[71:Spt:25364.0,24706.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.19 25369[71:Res:25366.0,61.1] always3(s42) || -> . % 76.01/76.19 25370[71:SSi:25369.0,731.0,24696.0] || -> . % 76.01/76.19 25371[69:Spt:25370.0,24687.2,24695.0] || xuntil6(s41)*+ -> . % 76.01/76.19 25372[69:Spt:25370.0,24687.0,24687.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.01/76.19 25373[69:Res:53.1,25372.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.01/76.19 25375[69:MRR:25373.0,24679.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.19 25377[69:Res:25375.0,61.1] always3(s42) || -> . % 76.01/76.19 25378[69:SSi:25377.0,731.0] || -> . % 76.01/76.19 25379[68:Spt:25378.0,24683.1,24685.0] || xuntil6(s40)* -> . % 76.01/76.19 25380[68:Spt:25378.0,24683.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.19 25383[68:Res:25380.0,61.1] always3(s40) || -> . % 76.01/76.19 25384[68:SSi:25383.0,729.0,24673.0] || -> . % 76.01/76.19 25385[66:Spt:25384.0,24667.2,24672.0] || xuntil6(s39)*+ -> . % 76.01/76.19 25386[66:Spt:25384.0,24667.0,24667.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.01/76.19 25387[66:Res:53.1,25386.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.01/76.19 25389[66:MRR:25387.0,24659.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.19 25391[66:Res:25389.0,61.1] always3(s40) || -> . % 76.01/76.19 25392[66:SSi:25391.0,729.0] || -> . % 76.01/76.19 25393[65:Spt:25392.0,24663.1,24665.0] || xuntil6(s38)* -> . % 76.01/76.19 25394[65:Spt:25392.0,24663.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.19 25397[65:Res:25394.0,61.1] always3(s38) || -> . % 76.01/76.19 25398[65:SSi:25397.0,727.0,24653.0] || -> . % 76.01/76.19 25399[63:Spt:25398.0,24650.2,24652.0] || xuntil6(s37)*+ -> . % 76.01/76.19 25400[63:Spt:25398.0,24650.0,24650.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.01/76.19 25401[63:Res:53.1,25400.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.01/76.19 25403[63:MRR:25401.0,24639.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.19 25405[63:Res:25403.0,61.1] always3(s38) || -> . % 76.01/76.19 25406[63:SSi:25405.0,727.0] || -> . % 76.01/76.19 25407[62:Spt:25406.0,24643.1,24648.0] || xuntil6(s36)* -> . % 76.01/76.19 25408[62:Spt:25406.0,24643.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.19 25411[62:Res:25408.0,61.1] always3(s36) || -> . % 76.01/76.19 25412[62:SSi:25411.0,725.0,24633.0] || -> . % 76.01/76.19 25413[60:Spt:25412.0,24624.2,24632.0] || xuntil6(s35)*+ -> . % 76.01/76.19 25414[60:Spt:25412.0,24624.0,24624.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.01/76.19 25415[60:Res:53.1,25414.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.01/76.19 25417[60:MRR:25415.0,24616.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.19 25419[60:Res:25417.0,61.1] always3(s36) || -> . % 76.01/76.19 25420[60:SSi:25419.0,725.0] || -> . % 76.01/76.19 25421[59:Spt:25420.0,24620.1,24622.0] || xuntil6(s34)* -> . % 76.01/76.19 25422[59:Spt:25420.0,24620.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.19 25425[59:Res:25422.0,61.1] always3(s34) || -> . % 76.01/76.19 25426[59:SSi:25425.0,723.0,24610.0] || -> . % 76.01/76.19 25427[57:Spt:25426.0,24604.2,24609.0] || xuntil6(s33)*+ -> . % 76.01/76.19 25428[57:Spt:25426.0,24604.0,24604.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.01/76.19 25429[57:Res:53.1,25428.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.01/76.19 25431[57:MRR:25429.0,24596.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.19 25433[57:Res:25431.0,61.1] always3(s34) || -> . % 76.01/76.19 25434[57:SSi:25433.0,723.0] || -> . % 76.01/76.19 25435[56:Spt:25434.0,24600.1,24602.0] || xuntil6(s32)* -> . % 76.01/76.19 25436[56:Spt:25434.0,24600.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.19 25439[56:Res:25436.0,61.1] always3(s32) || -> . % 76.01/76.19 25440[56:SSi:25439.0,721.0,24587.0] || -> . % 76.01/76.19 25441[54:Spt:25440.0,24585.2,24586.0] || xuntil6(s31)*+ -> . % 76.01/76.19 25442[54:Spt:25440.0,24585.0,24585.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.01/76.19 25443[54:Res:53.1,25442.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.01/76.19 25445[55:Spt:25443.1] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.19 25447[55:Res:25445.0,61.1] always3(s32) || -> . % 76.01/76.19 25448[55:SSi:25447.0,721.0] || -> . % 76.01/76.19 25449[55:Spt:25448.0,25443.1,25445.0] || m_main_v_state(s32,c_busy)* -> . % 76.01/76.19 25450[55:Spt:25448.0,25443.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.19 25453[55:Res:25450.0,61.1] always3(s31) || -> . % 76.01/76.19 25454[55:SSi:25453.0,720.0,24584.0] || -> . % 76.01/76.19 25455[53:Spt:25454.0,24579.2,24583.0] || xuntil6(s30)*+ -> . % 76.01/76.19 25456[53:Spt:25454.0,24579.0,24579.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.01/76.19 25457[53:Res:53.1,25456.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.01/76.19 25459[54:Spt:25457.1] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.19 25461[54:Res:25459.0,61.1] always3(s31) || -> . % 76.01/76.19 25462[54:SSi:25461.0,720.0] || -> . % 76.01/76.19 25463[54:Spt:25462.0,25457.1,25459.0] || m_main_v_state(s31,c_busy)* -> . % 76.01/76.19 25464[54:Spt:25462.0,25457.0] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.19 25467[54:Res:25464.0,61.1] always3(s30) || -> . % 76.01/76.19 25468[54:SSi:25467.0,719.0,24578.0] || -> . % 76.01/76.19 25469[52:Spt:25468.0,24576.2,24577.0] || xuntil6(s29)*+ -> . % 76.01/76.19 25470[52:Spt:25468.0,24576.0,24576.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.01/76.19 25471[52:Res:53.1,25470.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.01/76.19 25473[53:Spt:25471.1] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.19 25475[53:Res:25473.0,61.1] always3(s30) || -> . % 76.01/76.19 25476[53:SSi:25475.0,719.0] || -> . % 76.01/76.19 25477[53:Spt:25476.0,25471.1,25473.0] || m_main_v_state(s30,c_busy)* -> . % 76.01/76.19 25478[53:Spt:25476.0,25471.0] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.19 25481[53:Res:25478.0,61.1] always3(s29) || -> . % 76.01/76.19 25482[53:SSi:25481.0,718.0,24575.0] || -> . % 76.01/76.19 25483[51:Spt:25482.0,24570.2,24574.0] || xuntil6(s28)*+ -> . % 76.01/76.19 25484[51:Spt:25482.0,24570.0,24570.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.01/76.19 25485[51:Res:53.1,25484.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.01/76.19 25487[52:Spt:25485.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 25489[52:Res:25487.0,61.1] always3(s28) || -> . % 76.01/76.19 25490[52:SSi:25489.0,717.0,24569.0] || -> . % 76.01/76.19 25491[52:Spt:25490.0,25485.0,25487.0] || m_main_v_state(s28,c_busy)* -> . % 76.01/76.19 25492[52:Spt:25490.0,25485.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.19 25496[52:Res:25492.0,61.1] always3(s29) || -> . % 76.01/76.19 25497[52:SSi:25496.0,718.0] || -> . % 76.01/76.19 25498[50:Spt:25497.0,24567.2,24568.0] || xuntil6(s27)*+ -> . % 76.01/76.19 25499[50:Spt:25497.0,24567.0,24567.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.01/76.19 25500[50:Res:53.1,25499.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.01/76.19 25502[51:Spt:25500.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.19 25504[51:Res:25502.0,61.1] always3(s27) || -> . % 76.01/76.19 25505[51:SSi:25504.0,716.0,24566.0] || -> . % 76.01/76.19 25506[51:Spt:25505.0,25500.0,25502.0] || m_main_v_state(s27,c_busy)* -> . % 76.01/76.19 25507[51:Spt:25505.0,25500.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 25511[51:Res:25507.0,61.1] always3(s28) || -> . % 76.01/76.19 25512[51:SSi:25511.0,717.0] || -> . % 76.01/76.19 25513[49:Spt:25512.0,24561.2,24565.0] || xuntil6(s26)*+ -> . % 76.01/76.19 25514[49:Spt:25512.0,24561.0,24561.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.01/76.19 25515[49:Res:53.1,25514.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.01/76.19 25517[50:Spt:25515.0] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.19 25519[50:Res:25517.0,61.1] always3(s26) || -> . % 76.01/76.19 25520[50:SSi:25519.0,715.0,24560.0] || -> . % 76.01/76.19 25521[50:Spt:25520.0,25515.0,25517.0] || m_main_v_state(s26,c_busy)* -> . % 76.01/76.19 25522[50:Spt:25520.0,25515.1] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.19 25526[50:Res:25522.0,61.1] always3(s27) || -> . % 76.01/76.19 25527[50:SSi:25526.0,716.0] || -> . % 76.01/76.19 25528[48:Spt:25527.0,24558.2,24559.0] || xuntil6(s25)*+ -> . % 76.01/76.19 25529[48:Spt:25527.0,24558.0,24558.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.01/76.19 25530[48:Res:53.1,25529.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.01/76.19 25532[49:Spt:25530.0] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.19 25534[49:Res:25532.0,61.1] always3(s25) || -> . % 76.01/76.19 25535[49:SSi:25534.0,714.0,24557.0] || -> . % 76.01/76.19 25536[49:Spt:25535.0,25530.0,25532.0] || m_main_v_state(s25,c_busy)* -> . % 76.01/76.19 25537[49:Spt:25535.0,25530.1] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.19 25541[49:Res:25537.0,61.1] always3(s26) || -> . % 76.01/76.19 25542[49:SSi:25541.0,715.0] || -> . % 76.01/76.19 25543[47:Spt:25542.0,24552.2,24556.0] || xuntil6(s24)*+ -> . % 76.01/76.19 25544[47:Spt:25542.0,24552.0,24552.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.01/76.19 25545[47:Res:53.1,25544.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.01/76.19 25550[48:Spt:25545.0] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.19 25552[48:Res:25550.0,61.1] always3(s24) || -> . % 76.01/76.19 25553[48:SSi:25552.0,713.0,24551.0] || -> . % 76.01/76.19 25554[48:Spt:25553.0,25545.0,25550.0] || m_main_v_state(s24,c_busy)* -> . % 76.01/76.19 25555[48:Spt:25553.0,25545.1] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.19 25559[48:Res:25555.0,61.1] always3(s25) || -> . % 76.01/76.19 25560[48:SSi:25559.0,714.0] || -> . % 76.01/76.19 25561[46:Spt:25560.0,24549.2,24550.0] || xuntil6(s23)*+ -> . % 76.01/76.19 25562[46:Spt:25560.0,24549.0,24549.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.01/76.19 25563[46:Res:53.1,25562.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.01/76.19 25565[47:Spt:25563.0] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.19 25567[47:Res:25565.0,61.1] always3(s23) || -> . % 76.01/76.19 25568[47:SSi:25567.0,712.0,24548.0] || -> . % 76.01/76.19 25569[47:Spt:25568.0,25563.0,25565.0] || m_main_v_state(s23,c_busy)* -> . % 76.01/76.19 25570[47:Spt:25568.0,25563.1] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.19 25574[47:Res:25570.0,61.1] always3(s24) || -> . % 76.01/76.19 25575[47:SSi:25574.0,713.0] || -> . % 76.01/76.19 25576[45:Spt:25575.0,24543.2,24547.0] || xuntil6(s22)*+ -> . % 76.01/76.19 25577[45:Spt:25575.0,24543.0,24543.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.01/76.19 25578[45:Res:53.1,25577.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.01/76.19 25580[46:Spt:25578.0] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.19 25582[46:Res:25580.0,61.1] always3(s22) || -> . % 76.01/76.19 25583[46:SSi:25582.0,711.0,24542.0] || -> . % 76.01/76.19 25584[46:Spt:25583.0,25578.0,25580.0] || m_main_v_state(s22,c_busy)* -> . % 76.01/76.19 25585[46:Spt:25583.0,25578.1] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.19 25589[46:Res:25585.0,61.1] always3(s23) || -> . % 76.01/76.19 25590[46:SSi:25589.0,712.0] || -> . % 76.01/76.19 25591[44:Spt:25590.0,24540.2,24541.0] || xuntil6(s21)*+ -> . % 76.01/76.19 25592[44:Spt:25590.0,24540.0,24540.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.01/76.19 25593[44:Res:53.1,25592.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.01/76.19 25598[45:Spt:25593.0] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.19 25600[45:Res:25598.0,61.1] always3(s21) || -> . % 76.01/76.19 25601[45:SSi:25600.0,710.0,24539.0] || -> . % 76.01/76.19 25602[45:Spt:25601.0,25593.0,25598.0] || m_main_v_state(s21,c_busy)* -> . % 76.01/76.19 25603[45:Spt:25601.0,25593.1] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.19 25607[45:Res:25603.0,61.1] always3(s22) || -> . % 76.01/76.19 25608[45:SSi:25607.0,711.0] || -> . % 76.01/76.19 25609[43:Spt:25608.0,24534.2,24538.0] || xuntil6(s20)*+ -> . % 76.01/76.19 25610[43:Spt:25608.0,24534.0,24534.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.01/76.19 25611[43:Res:53.1,25610.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.01/76.19 25613[44:Spt:25611.0] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.19 25615[44:Res:25613.0,61.1] always3(s20) || -> . % 76.01/76.19 25616[44:SSi:25615.0,709.0,24533.0] || -> . % 76.01/76.19 25617[44:Spt:25616.0,25611.0,25613.0] || m_main_v_state(s20,c_busy)* -> . % 76.01/76.19 25618[44:Spt:25616.0,25611.1] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.19 25622[44:Res:25618.0,61.1] always3(s21) || -> . % 76.01/76.19 25623[44:SSi:25622.0,710.0] || -> . % 76.01/76.19 25624[42:Spt:25623.0,24531.2,24532.0] || xuntil6(s19)*+ -> . % 76.01/76.19 25625[42:Spt:25623.0,24531.0,24531.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.01/76.19 25626[42:Res:53.1,25625.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.01/76.19 25628[43:Spt:25626.0] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.19 25630[43:Res:25628.0,61.1] always3(s19) || -> . % 76.01/76.19 25631[43:SSi:25630.0,708.0,24530.0] || -> . % 76.01/76.19 25632[43:Spt:25631.0,25626.0,25628.0] || m_main_v_state(s19,c_busy)* -> . % 76.01/76.19 25633[43:Spt:25631.0,25626.1] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.19 25637[43:Res:25633.0,61.1] always3(s20) || -> . % 76.01/76.19 25638[43:SSi:25637.0,709.0] || -> . % 76.01/76.19 25639[41:Spt:25638.0,24525.2,24529.0] || xuntil6(s18)*+ -> . % 76.01/76.19 25640[41:Spt:25638.0,24525.0,24525.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.01/76.19 25641[41:Res:53.1,25640.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.01/76.19 25646[42:Spt:25641.0] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.19 25648[42:Res:25646.0,61.1] always3(s18) || -> . % 76.01/76.19 25649[42:SSi:25648.0,707.0,24524.0] || -> . % 76.01/76.19 25650[42:Spt:25649.0,25641.0,25646.0] || m_main_v_state(s18,c_busy)* -> . % 76.01/76.19 25651[42:Spt:25649.0,25641.1] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.19 25655[42:Res:25651.0,61.1] always3(s19) || -> . % 76.01/76.19 25656[42:SSi:25655.0,708.0] || -> . % 76.01/76.19 25657[40:Spt:25656.0,24522.2,24523.0] || xuntil6(s17)*+ -> . % 76.01/76.19 25658[40:Spt:25656.0,24522.0,24522.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.01/76.19 25659[40:Res:53.1,25658.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.01/76.19 25661[41:Spt:25659.0] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.19 25663[41:Res:25661.0,61.1] always3(s17) || -> . % 76.01/76.19 25664[41:SSi:25663.0,706.0,24521.0] || -> . % 76.01/76.19 25665[41:Spt:25664.0,25659.0,25661.0] || m_main_v_state(s17,c_busy)* -> . % 76.01/76.19 25666[41:Spt:25664.0,25659.1] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.19 25670[41:Res:25666.0,61.1] always3(s18) || -> . % 76.01/76.19 25671[41:SSi:25670.0,707.0] || -> . % 76.01/76.19 25672[39:Spt:25671.0,24516.2,24520.0] || xuntil6(s16)*+ -> . % 76.01/76.19 25673[39:Spt:25671.0,24516.0,24516.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.01/76.19 25674[39:Res:53.1,25673.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.01/76.19 25676[40:Spt:25674.0] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.19 25678[40:Res:25676.0,61.1] always3(s16) || -> . % 76.01/76.19 25679[40:SSi:25678.0,705.0,24515.0] || -> . % 76.01/76.19 25680[40:Spt:25679.0,25674.0,25676.0] || m_main_v_state(s16,c_busy)* -> . % 76.01/76.19 25681[40:Spt:25679.0,25674.1] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.19 25685[40:Res:25681.0,61.1] always3(s17) || -> . % 76.01/76.19 25686[40:SSi:25685.0,706.0] || -> . % 76.01/76.19 25687[38:Spt:25686.0,24513.2,24514.0] || xuntil6(s15)*+ -> . % 76.01/76.19 25688[38:Spt:25686.0,24513.0,24513.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.01/76.19 25689[38:Res:53.1,25688.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.01/76.19 25694[39:Spt:25689.0] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.19 25696[39:Res:25694.0,61.1] always3(s15) || -> . % 76.01/76.19 25697[39:SSi:25696.0,704.0,24512.0] || -> . % 76.01/76.19 25698[39:Spt:25697.0,25689.0,25694.0] || m_main_v_state(s15,c_busy)* -> . % 76.01/76.19 25699[39:Spt:25697.0,25689.1] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.19 25703[39:Res:25699.0,61.1] always3(s16) || -> . % 76.01/76.19 25704[39:SSi:25703.0,705.0] || -> . % 76.01/76.19 25705[37:Spt:25704.0,24507.2,24511.0] || xuntil6(s14)*+ -> . % 76.01/76.19 25706[37:Spt:25704.0,24507.0,24507.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.01/76.19 25707[37:Res:53.1,25706.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.01/76.19 25709[38:Spt:25707.0] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.19 25711[38:Res:25709.0,61.1] always3(s14) || -> . % 76.01/76.19 25712[38:SSi:25711.0,703.0,24506.0] || -> . % 76.01/76.19 25713[38:Spt:25712.0,25707.0,25709.0] || m_main_v_state(s14,c_busy)* -> . % 76.01/76.19 25714[38:Spt:25712.0,25707.1] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.19 25718[38:Res:25714.0,61.1] always3(s15) || -> . % 76.01/76.19 25719[38:SSi:25718.0,704.0] || -> . % 76.01/76.19 25720[36:Spt:25719.0,24504.2,24505.0] || xuntil6(s13)*+ -> . % 76.01/76.19 25721[36:Spt:25719.0,24504.0,24504.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.01/76.19 25722[36:Res:53.1,25721.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.01/76.19 25724[37:Spt:25722.0] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.19 25726[37:Res:25724.0,61.1] always3(s13) || -> . % 76.01/76.19 25727[37:SSi:25726.0,702.0,24503.0] || -> . % 76.01/76.19 25728[37:Spt:25727.0,25722.0,25724.0] || m_main_v_state(s13,c_busy)* -> . % 76.01/76.19 25729[37:Spt:25727.0,25722.1] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.19 25733[37:Res:25729.0,61.1] always3(s14) || -> . % 76.01/76.19 25734[37:SSi:25733.0,703.0] || -> . % 76.01/76.19 25735[35:Spt:25734.0,24498.2,24502.0] || xuntil6(s12)*+ -> . % 76.01/76.19 25736[35:Spt:25734.0,24498.0,24498.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.01/76.19 25737[35:Res:53.1,25736.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.01/76.19 25742[36:Spt:25737.0] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.19 25744[36:Res:25742.0,61.1] always3(s12) || -> . % 76.01/76.19 25745[36:SSi:25744.0,701.0,24497.0] || -> . % 76.01/76.19 25746[36:Spt:25745.0,25737.0,25742.0] || m_main_v_state(s12,c_busy)* -> . % 76.01/76.19 25747[36:Spt:25745.0,25737.1] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.19 25751[36:Res:25747.0,61.1] always3(s13) || -> . % 76.01/76.19 25752[36:SSi:25751.0,702.0] || -> . % 76.01/76.19 25753[34:Spt:25752.0,24495.2,24496.0] || xuntil6(s11)*+ -> . % 76.01/76.19 25754[34:Spt:25752.0,24495.0,24495.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.01/76.19 25755[34:Res:53.1,25754.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.01/76.19 25757[35:Spt:25755.0] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.19 25759[35:Res:25757.0,61.1] always3(s11) || -> . % 76.01/76.19 25760[35:SSi:25759.0,700.0,24494.0] || -> . % 76.01/76.19 25761[35:Spt:25760.0,25755.0,25757.0] || m_main_v_state(s11,c_busy)* -> . % 76.01/76.19 25762[35:Spt:25760.0,25755.1] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.19 25766[35:Res:25762.0,61.1] always3(s12) || -> . % 76.01/76.19 25767[35:SSi:25766.0,701.0] || -> . % 76.01/76.19 25768[33:Spt:25767.0,24489.2,24493.0] || xuntil6(s10)*+ -> . % 76.01/76.19 25769[33:Spt:25767.0,24489.0,24489.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.01/76.19 25770[33:Res:53.1,25769.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.01/76.19 25772[34:Spt:25770.0] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.19 25774[34:Res:25772.0,61.1] always3(s10) || -> . % 76.01/76.19 25775[34:SSi:25774.0,699.0,24488.0] || -> . % 76.01/76.19 25776[34:Spt:25775.0,25770.0,25772.0] || m_main_v_state(s10,c_busy)* -> . % 76.01/76.19 25777[34:Spt:25775.0,25770.1] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.19 25781[34:Res:25777.0,61.1] always3(s11) || -> . % 76.01/76.19 25782[34:SSi:25781.0,700.0] || -> . % 76.01/76.19 25783[32:Spt:25782.0,24486.2,24487.0] || xuntil6(s9)*+ -> . % 76.01/76.19 25784[32:Spt:25782.0,24486.0,24486.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.01/76.19 25785[32:Res:53.1,25784.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.01/76.19 25790[33:Spt:25785.0] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.19 25792[33:Res:25790.0,61.1] always3(s9) || -> . % 76.01/76.19 25793[33:SSi:25792.0,698.0,24485.0] || -> . % 76.01/76.19 25794[33:Spt:25793.0,25785.0,25790.0] || m_main_v_state(s9,c_busy)* -> . % 76.01/76.19 25795[33:Spt:25793.0,25785.1] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.19 25799[33:Res:25795.0,61.1] always3(s10) || -> . % 76.01/76.19 25800[33:SSi:25799.0,699.0] || -> . % 76.01/76.19 25801[31:Spt:25800.0,24480.2,24484.0] || xuntil6(s8)*+ -> . % 76.01/76.19 25802[31:Spt:25800.0,24480.0,24480.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.01/76.19 25803[31:Res:53.1,25802.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.01/76.19 25805[32:Spt:25803.0] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.19 25807[32:Res:25805.0,61.1] always3(s8) || -> . % 76.01/76.19 25808[32:SSi:25807.0,697.0,24479.0] || -> . % 76.01/76.19 25809[32:Spt:25808.0,25803.0,25805.0] || m_main_v_state(s8,c_busy)* -> . % 76.01/76.19 25810[32:Spt:25808.0,25803.1] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.19 25814[32:Res:25810.0,61.1] always3(s9) || -> . % 76.01/76.19 25815[32:SSi:25814.0,698.0] || -> . % 76.01/76.19 25816[30:Spt:25815.0,24477.2,24478.0] || xuntil6(s7)*+ -> . % 76.01/76.19 25817[30:Spt:25815.0,24477.0,24477.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.01/76.19 25818[30:Res:53.1,25817.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.01/76.19 25820[31:Spt:25818.0] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.19 25822[31:Res:25820.0,61.1] always3(s7) || -> . % 76.01/76.19 25823[31:SSi:25822.0,696.0,24476.0] || -> . % 76.01/76.19 25824[31:Spt:25823.0,25818.0,25820.0] || m_main_v_state(s7,c_busy)* -> . % 76.01/76.19 25825[31:Spt:25823.0,25818.1] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.19 25829[31:Res:25825.0,61.1] always3(s8) || -> . % 76.01/76.19 25830[31:SSi:25829.0,697.0] || -> . % 76.01/76.19 25831[29:Spt:25830.0,24471.2,24475.0] || xuntil6(s6)*+ -> . % 76.01/76.19 25832[29:Spt:25830.0,24471.0,24471.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.01/76.19 25833[29:Res:53.1,25832.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.01/76.19 25838[30:Spt:25833.0] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.19 25840[30:Res:25838.0,61.1] always3(s6) || -> . % 76.01/76.19 25841[30:SSi:25840.0,695.0,24470.0] || -> . % 76.01/76.19 25842[30:Spt:25841.0,25833.0,25838.0] || m_main_v_state(s6,c_busy)* -> . % 76.01/76.19 25843[30:Spt:25841.0,25833.1] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.19 25847[30:Res:25843.0,61.1] always3(s7) || -> . % 76.01/76.19 25848[30:SSi:25847.0,696.0] || -> . % 76.01/76.19 25849[28:Spt:25848.0,24468.2,24469.0] || xuntil6(s5)*+ -> . % 76.01/76.19 25850[28:Spt:25848.0,24468.0,24468.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.01/76.19 25851[28:Res:53.1,25850.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.01/76.19 25853[29:Spt:25851.0] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.19 25855[29:Res:25853.0,61.1] always3(s5) || -> . % 76.01/76.19 25856[29:SSi:25855.0,694.0,24467.0] || -> . % 76.01/76.19 25857[29:Spt:25856.0,25851.0,25853.0] || m_main_v_state(s5,c_busy)* -> . % 76.01/76.19 25858[29:Spt:25856.0,25851.1] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.19 25862[29:Res:25858.0,61.1] always3(s6) || -> . % 76.01/76.19 25863[29:SSi:25862.0,695.0] || -> . % 76.01/76.19 25864[27:Spt:25863.0,24462.2,24466.0] || xuntil6(s4)*+ -> . % 76.01/76.19 25865[27:Spt:25863.0,24462.0,24462.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.01/76.19 25866[27:Res:53.1,25865.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.01/76.19 25868[28:Spt:25866.0] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.19 25870[28:Res:25868.0,61.1] always3(s4) || -> . % 76.01/76.19 25871[28:SSi:25870.0,693.0,24461.0] || -> . % 76.01/76.19 25872[28:Spt:25871.0,25866.0,25868.0] || m_main_v_state(s4,c_busy)* -> . % 76.01/76.19 25873[28:Spt:25871.0,25866.1] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.19 25877[28:Res:25873.0,61.1] always3(s5) || -> . % 76.01/76.19 25878[28:SSi:25877.0,694.0] || -> . % 76.01/76.19 25879[26:Spt:25878.0,24459.2,24460.0] || xuntil6(s3)*+ -> . % 76.01/76.19 25880[26:Spt:25878.0,24459.0,24459.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.01/76.19 25881[26:Res:53.1,25880.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.01/76.19 25886[27:Spt:25881.0] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.19 25888[27:Res:25886.0,61.1] always3(s3) || -> . % 76.01/76.19 25889[27:SSi:25888.0,692.0,24458.0] || -> . % 76.01/76.19 25890[27:Spt:25889.0,25881.0,25886.0] || m_main_v_state(s3,c_busy)* -> . % 76.01/76.19 25891[27:Spt:25889.0,25881.1] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.19 25895[27:Res:25891.0,61.1] always3(s4) || -> . % 76.01/76.19 25896[27:SSi:25895.0,693.0] || -> . % 76.01/76.19 25897[25:Spt:25896.0,24453.2,24457.0] || xuntil6(s2)*+ -> . % 76.01/76.19 25898[25:Spt:25896.0,24453.0,24453.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.01/76.19 25899[25:Res:53.1,25898.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.01/76.19 25901[26:Spt:25899.0] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.19 25903[26:Res:25901.0,61.1] always3(s2) || -> . % 76.01/76.19 25904[26:SSi:25903.0,691.0,24452.0] || -> . % 76.01/76.19 25905[26:Spt:25904.0,25899.0,25901.0] || m_main_v_state(s2,c_busy)* -> . % 76.01/76.19 25906[26:Spt:25904.0,25899.1] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.19 25910[26:Res:25906.0,61.1] always3(s3) || -> . % 76.01/76.19 25911[26:SSi:25910.0,692.0] || -> . % 76.01/76.19 25912[24:Spt:25911.0,24447.2,24451.0] || xuntil6(s1)*+ -> . % 76.01/76.19 25913[24:Spt:25911.0,24447.0,24447.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.01/76.19 25914[24:Res:53.1,25913.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.01/76.19 25916[25:Spt:25914.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.19 25918[25:Res:25916.0,61.1] always3(s1) || -> . % 76.01/76.19 25919[25:SSi:25918.0,690.0,24446.0] || -> . % 76.01/76.19 25920[25:Spt:25919.0,25914.0,25916.0] || m_main_v_state(s1,c_busy)* -> . % 76.01/76.19 25921[25:Spt:25919.0,25914.1] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.19 25926[25:Res:25921.0,61.1] always3(s2) || -> . % 76.01/76.19 25927[25:SSi:25926.0,691.0] || -> . % 76.01/76.19 25928[23:Spt:25927.0,74.0,24445.0] || xuntil6(s0)*+ -> . % 76.01/76.19 25929[23:Spt:25927.0,74.1] || -> node4(s0)*. % 76.01/76.19 25930[23:MRR:758.1,25928.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.19 25932[23:Res:25930.0,61.1] always3(s1) || -> . % 76.01/76.19 25933[23:SSi:25932.0,690.0] || -> . % 76.01/76.19 25934[22:Spt:25933.0,24435.0,24439.0] || trans(s49,s29)*+ -> . % 76.01/76.19 25935[22:Spt:25933.0,24435.1,24435.2,24435.3,24435.4,24435.5,24435.6,24435.7,24435.8,24435.9,24435.10,24435.11,24435.12,24435.13,24435.14,24435.15,24435.16,24435.17,24435.18,24435.19,24435.20,24435.21,24435.22,24435.23,24435.24,24435.25,24435.26,24435.27,24435.28,24435.29] || -> trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.01/76.19 25936[22:MRR:24437.0,25934.0] || -> trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.01/76.19 25938[22:MRR:24438.1,25934.0] xuntil6(s49) || -> trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.01/76.19 25939[23:Spt:25935.0] || -> trans(s49,s28)*. % 76.01/76.19 25940[23:Res:25939.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s28)*. % 76.01/76.19 25942[23:Res:25939.0,60.0] || -> node2(s49,s28)*. % 76.01/76.19 25943[23:SSi:25940.1,50.0,738.0] xuntil6(s49) || -> until2p7(s28)*. % 76.01/76.19 25944[23:Res:25942.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 25945[24:Spt:74.0] || -> xuntil6(s0)*. % 76.01/76.19 25946[24:MRR:176.0,25945.0] || -> until5(s1)*. % 76.01/76.19 25947[24:MRR:24891.0,25946.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.19 25951[25:Spt:25947.2] || -> xuntil6(s1)*. % 76.01/76.19 25952[25:MRR:175.0,25951.0] || -> until5(s2)*. % 76.01/76.19 25953[25:MRR:24890.0,25952.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.19 25957[26:Spt:25953.2] || -> xuntil6(s2)*. % 76.01/76.19 25958[26:MRR:174.0,25957.0] || -> until5(s3)*. % 76.01/76.19 25959[26:MRR:24883.0,25958.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.19 25960[27:Spt:25959.2] || -> xuntil6(s3)*. % 76.01/76.19 25961[27:MRR:173.0,25960.0] || -> until5(s4)*. % 76.01/76.19 25962[27:MRR:24879.0,25961.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.19 25966[28:Spt:25962.2] || -> xuntil6(s4)*. % 76.01/76.19 25967[28:MRR:172.0,25966.0] || -> until5(s5)*. % 76.01/76.19 25968[28:MRR:24875.0,25967.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.19 25969[29:Spt:25968.2] || -> xuntil6(s5)*. % 76.01/76.19 25970[29:MRR:171.0,25969.0] || -> until5(s6)*. % 76.01/76.19 25971[29:MRR:24871.0,25970.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.19 25975[30:Spt:25971.2] || -> xuntil6(s6)*. % 76.01/76.19 25976[30:MRR:170.0,25975.0] || -> until5(s7)*. % 76.01/76.19 25977[30:MRR:24870.0,25976.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.19 25978[31:Spt:25977.2] || -> xuntil6(s7)*. % 76.01/76.19 25979[31:MRR:169.0,25978.0] || -> until5(s8)*. % 76.01/76.19 25980[31:MRR:24863.0,25979.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.19 25984[32:Spt:25980.2] || -> xuntil6(s8)*. % 76.01/76.19 25985[32:MRR:168.0,25984.0] || -> until5(s9)*. % 76.01/76.19 25986[32:MRR:24859.0,25985.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.19 25987[33:Spt:25986.2] || -> xuntil6(s9)*. % 76.01/76.19 25988[33:MRR:167.0,25987.0] || -> until5(s10)*. % 76.01/76.19 25989[33:MRR:24855.0,25988.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.19 25993[34:Spt:25989.2] || -> xuntil6(s10)*. % 76.01/76.19 25994[34:MRR:166.0,25993.0] || -> until5(s11)*. % 76.01/76.19 25995[34:MRR:24851.0,25994.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.19 25996[35:Spt:25995.2] || -> xuntil6(s11)*. % 76.01/76.19 25997[35:MRR:165.0,25996.0] || -> until5(s12)*. % 76.01/76.19 25998[35:MRR:24850.0,25997.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.19 26002[36:Spt:25998.2] || -> xuntil6(s12)*. % 76.01/76.19 26003[36:MRR:164.0,26002.0] || -> until5(s13)*. % 76.01/76.19 26004[36:MRR:24843.0,26003.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.19 26005[37:Spt:26004.2] || -> xuntil6(s13)*. % 76.01/76.19 26006[37:MRR:163.0,26005.0] || -> until5(s14)*. % 76.01/76.19 26007[37:MRR:24839.0,26006.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.19 26011[38:Spt:26007.2] || -> xuntil6(s14)*. % 76.01/76.19 26012[38:MRR:162.0,26011.0] || -> until5(s15)*. % 76.01/76.19 26013[38:MRR:24835.0,26012.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.19 26014[39:Spt:26013.2] || -> xuntil6(s15)*. % 76.01/76.19 26015[39:MRR:161.0,26014.0] || -> until5(s16)*. % 76.01/76.19 26016[39:MRR:24831.0,26015.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.19 26020[40:Spt:26016.2] || -> xuntil6(s16)*. % 76.01/76.19 26021[40:MRR:160.0,26020.0] || -> until5(s17)*. % 76.01/76.19 26022[40:MRR:24830.0,26021.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.19 26023[41:Spt:26022.2] || -> xuntil6(s17)*. % 76.01/76.19 26024[41:MRR:159.0,26023.0] || -> until5(s18)*. % 76.01/76.19 26025[41:MRR:24823.0,26024.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.19 26029[42:Spt:26025.2] || -> xuntil6(s18)*. % 76.01/76.19 26030[42:MRR:158.0,26029.0] || -> until5(s19)*. % 76.01/76.19 26031[42:MRR:24819.0,26030.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.19 26032[43:Spt:26031.2] || -> xuntil6(s19)*. % 76.01/76.19 26033[43:MRR:157.0,26032.0] || -> until5(s20)*. % 76.01/76.19 26034[43:MRR:24815.0,26033.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.19 26038[44:Spt:26034.2] || -> xuntil6(s20)*. % 76.01/76.19 26039[44:MRR:156.0,26038.0] || -> until5(s21)*. % 76.01/76.19 26040[44:MRR:24811.0,26039.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.19 26041[45:Spt:26040.2] || -> xuntil6(s21)*. % 76.01/76.19 26042[45:MRR:155.0,26041.0] || -> until5(s22)*. % 76.01/76.19 26043[45:MRR:24810.0,26042.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.19 26047[46:Spt:26043.2] || -> xuntil6(s22)*. % 76.01/76.19 26048[46:MRR:154.0,26047.0] || -> until5(s23)*. % 76.01/76.19 26049[46:MRR:24803.0,26048.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.19 26050[47:Spt:26049.2] || -> xuntil6(s23)*. % 76.01/76.19 26051[47:MRR:153.0,26050.0] || -> until5(s24)*. % 76.01/76.19 26052[47:MRR:24799.0,26051.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.19 26056[48:Spt:26052.2] || -> xuntil6(s24)*. % 76.01/76.19 26057[48:MRR:152.0,26056.0] || -> until5(s25)*. % 76.01/76.19 26058[48:MRR:24795.0,26057.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.19 26059[49:Spt:26058.2] || -> xuntil6(s25)*. % 76.01/76.19 26060[49:MRR:151.0,26059.0] || -> until5(s26)*. % 76.01/76.19 26061[49:MRR:24791.0,26060.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.19 26065[50:Spt:26061.2] || -> xuntil6(s26)*. % 76.01/76.19 26066[50:MRR:150.0,26065.0] || -> until5(s27)*. % 76.01/76.19 26067[50:MRR:24790.0,26066.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.19 26068[51:Spt:26067.2] || -> xuntil6(s27)*. % 76.01/76.19 26069[51:MRR:149.0,26068.0] || -> until5(s28)*. % 76.01/76.19 26070[51:MRR:24783.0,26069.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.19 26074[52:Spt:26070.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.19 26076[52:Res:26074.0,61.1] always3(s29) || -> . % 76.01/76.19 26077[52:SSi:26076.0,718.0] || -> . % 76.01/76.19 26078[52:Spt:26077.0,26070.1,26074.0] || m_main_v_state(s29,c_busy)*+ -> . % 76.01/76.19 26079[52:Spt:26077.0,26070.0,26070.2] || m_main_v_state(s28,c_ready)*+ -> xuntil6(s28). % 76.01/76.19 26081[52:MRR:834.2,26078.0] node4(s28) || m_main_v_state(s28,c_ready)* -> . % 76.01/76.19 26082[52:Res:53.1,26079.0] || -> m_main_v_state(s28,c_busy)* xuntil6(s28). % 76.01/76.19 26084[53:Spt:26082.1] || -> xuntil6(s28)*. % 76.01/76.19 26085[53:MRR:148.0,26084.0] || -> until5(s29)*. % 76.01/76.19 26086[53:MRR:24782.0,26085.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.19 26091[54:Spt:26086.2] || -> xuntil6(s29)*. % 76.01/76.19 26092[54:MRR:147.0,26091.0] || -> until5(s30)*. % 76.01/76.19 26093[54:MRR:24777.0,26092.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.19 26094[55:Spt:26093.1] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.19 26096[55:Res:26094.0,61.1] always3(s31) || -> . % 76.01/76.19 26097[55:SSi:26096.0,720.0] || -> . % 76.01/76.19 26098[55:Spt:26097.0,26093.1,26094.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.01/76.19 26099[55:Spt:26097.0,26093.0,26093.2] || m_main_v_state(s30,c_ready)*+ -> xuntil6(s30). % 76.01/76.19 26101[55:MRR:828.2,26098.0] node4(s30) || m_main_v_state(s30,c_ready)* -> . % 76.01/76.19 26102[55:Res:53.1,26099.0] || -> m_main_v_state(s30,c_busy)* xuntil6(s30). % 76.01/76.19 26104[56:Spt:26102.1] || -> xuntil6(s30)*. % 76.01/76.19 26105[56:MRR:146.0,26104.0] || -> until5(s31)*. % 76.01/76.19 26106[56:MRR:24781.0,26105.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.19 26114[57:Spt:26106.2] || -> xuntil6(s31)*. % 76.01/76.19 26115[57:MRR:145.0,26114.0] || -> until5(s32)*. % 76.01/76.19 26116[57:MRR:19324.0,26115.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.19 26117[58:Spt:26116.1] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.19 26119[58:Res:26117.0,61.1] always3(s33) || -> . % 76.01/76.19 26120[58:SSi:26119.0,722.0] || -> . % 76.01/76.19 26121[58:Spt:26120.0,26116.1,26117.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.01/76.19 26122[58:Spt:26120.0,26116.0,26116.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 76.01/76.19 26124[58:MRR:822.2,26121.0] node4(s32) || m_main_v_state(s32,c_ready)* -> . % 76.01/76.19 26125[58:Res:53.1,26122.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 76.01/76.19 26130[59:Spt:26125.1] || -> xuntil6(s32)*. % 76.01/76.19 26131[59:MRR:144.0,26130.0] || -> until5(s33)*. % 76.01/76.19 26132[59:MRR:24895.0,26131.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.19 26134[60:Spt:26132.2] || -> xuntil6(s33)*. % 76.01/76.19 26135[60:MRR:143.0,26134.0] || -> until5(s34)*. % 76.01/76.19 26136[60:MRR:16857.0,26135.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.19 26137[61:Spt:26136.1] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.19 26139[61:Res:26137.0,61.1] always3(s35) || -> . % 76.01/76.19 26140[61:SSi:26139.0,724.0] || -> . % 76.01/76.19 26141[61:Spt:26140.0,26136.1,26137.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.01/76.19 26142[61:Spt:26140.0,26136.0,26136.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 76.01/76.19 26144[61:MRR:816.2,26141.0] node4(s34) || m_main_v_state(s34,c_ready)* -> . % 76.01/76.19 26145[61:Res:53.1,26142.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 76.01/76.19 26147[62:Spt:26145.1] || -> xuntil6(s34)*. % 76.01/76.19 26148[62:MRR:142.0,26147.0] || -> until5(s35)*. % 76.01/76.19 26149[62:MRR:24899.0,26148.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.19 26154[63:Spt:26149.2] || -> xuntil6(s35)*. % 76.01/76.19 26155[63:MRR:141.0,26154.0] || -> until5(s36)*. % 76.01/76.19 26156[63:MRR:16858.0,26155.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.19 26157[64:Spt:26156.1] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.19 26159[64:Res:26157.0,61.1] always3(s37) || -> . % 76.01/76.19 26160[64:SSi:26159.0,726.0] || -> . % 76.01/76.19 26161[64:Spt:26160.0,26156.1,26157.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.01/76.19 26162[64:Spt:26160.0,26156.0,26156.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 76.01/76.19 26164[64:MRR:810.2,26161.0] node4(s36) || m_main_v_state(s36,c_ready)* -> . % 76.01/76.19 26165[64:Res:53.1,26162.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 76.01/76.19 26167[65:Spt:26165.1] || -> xuntil6(s36)*. % 76.01/76.19 26168[65:MRR:140.0,26167.0] || -> until5(s37)*. % 76.01/76.19 26169[65:MRR:24903.0,26168.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.19 26177[66:Spt:26169.2] || -> xuntil6(s37)*. % 76.01/76.19 26178[66:MRR:139.0,26177.0] || -> until5(s38)*. % 76.01/76.19 26179[66:MRR:16862.0,26178.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.19 26180[67:Spt:26179.1] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.19 26182[67:Res:26180.0,61.1] always3(s39) || -> . % 76.01/76.19 26183[67:SSi:26182.0,728.0] || -> . % 76.01/76.19 26184[67:Spt:26183.0,26179.1,26180.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.01/76.19 26185[67:Spt:26183.0,26179.0,26179.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 76.01/76.19 26187[67:MRR:804.2,26184.0] node4(s38) || m_main_v_state(s38,c_ready)* -> . % 76.01/76.19 26188[67:Res:53.1,26185.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 76.01/76.19 26193[68:Spt:26188.1] || -> xuntil6(s38)*. % 76.01/76.19 26194[68:MRR:138.0,26193.0] || -> until5(s39)*. % 76.01/76.19 26195[68:MRR:24910.0,26194.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.19 26197[69:Spt:26195.2] || -> xuntil6(s39)*. % 76.01/76.19 26198[69:MRR:137.0,26197.0] || -> until5(s40)*. % 76.01/76.19 26199[69:MRR:16866.0,26198.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.01/76.19 26200[70:Spt:26199.1] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.19 26202[70:Res:26200.0,61.1] always3(s41) || -> . % 76.01/76.19 26203[70:SSi:26202.0,730.0] || -> . % 76.01/76.19 26204[70:Spt:26203.0,26199.1,26200.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.01/76.19 26205[70:Spt:26203.0,26199.0,26199.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 76.01/76.19 26207[70:MRR:798.2,26204.0] node4(s40) || m_main_v_state(s40,c_ready)* -> . % 76.01/76.19 26208[70:Res:53.1,26205.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 76.01/76.19 26210[71:Spt:26208.1] || -> xuntil6(s40)*. % 76.01/76.19 26211[71:MRR:136.0,26210.0] || -> until5(s41)*. % 76.01/76.19 26212[71:MRR:24911.0,26211.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.19 26217[72:Spt:26212.2] || -> xuntil6(s41)*. % 76.01/76.19 26218[72:MRR:135.0,26217.0] || -> until5(s42)*. % 76.01/76.19 26219[72:MRR:16870.0,26218.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.01/76.19 26220[73:Spt:26219.1] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.19 26222[73:Res:26220.0,61.1] always3(s43) || -> . % 76.01/76.19 26223[73:SSi:26222.0,732.0] || -> . % 76.01/76.19 26224[73:Spt:26223.0,26219.1,26220.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.01/76.19 26225[73:Spt:26223.0,26219.0,26219.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 76.01/76.19 26227[73:MRR:792.2,26224.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 76.01/76.19 26228[73:Res:53.1,26225.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 76.01/76.19 26230[74:Spt:26228.1] || -> xuntil6(s42)*. % 76.01/76.19 26231[74:MRR:134.0,26230.0] || -> until5(s43)*. % 76.01/76.19 26232[74:MRR:24915.0,26231.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.19 26240[75:Spt:26232.2] || -> xuntil6(s43)*. % 76.01/76.19 26241[75:MRR:133.0,26240.0] || -> until5(s44)*. % 76.01/76.19 26242[75:MRR:16877.0,26241.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.01/76.19 26243[76:Spt:26242.1] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.19 26245[76:Res:26243.0,61.1] always3(s45) || -> . % 76.01/76.19 26246[76:SSi:26245.0,734.0] || -> . % 76.01/76.19 26247[76:Spt:26246.0,26242.1,26243.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.01/76.19 26248[76:Spt:26246.0,26242.0,26242.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 76.01/76.19 26250[76:MRR:786.2,26247.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 76.01/76.19 26251[76:Res:53.1,26248.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 76.01/76.19 26256[77:Spt:26251.1] || -> xuntil6(s44)*. % 76.01/76.19 26257[77:MRR:132.0,26256.0] || -> until5(s45)*. % 76.01/76.19 26258[77:MRR:24919.0,26257.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.19 26260[78:Spt:26258.2] || -> xuntil6(s45)*. % 76.01/76.19 26261[78:MRR:131.0,26260.0] || -> until5(s46)*. % 76.01/76.19 26262[78:MRR:16878.0,26261.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.01/76.19 26263[79:Spt:26262.1] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.19 26265[79:Res:26263.0,61.1] always3(s47) || -> . % 76.01/76.19 26266[79:SSi:26265.0,736.0] || -> . % 76.01/76.19 26267[79:Spt:26266.0,26262.1,26263.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.01/76.19 26268[79:Spt:26266.0,26262.0,26262.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 76.01/76.19 26270[79:MRR:780.2,26267.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 76.01/76.19 26271[79:Res:53.1,26268.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 76.01/76.19 26273[80:Spt:26271.1] || -> xuntil6(s46)*. % 76.01/76.19 26274[80:MRR:130.0,26273.0] || -> until5(s47)*. % 76.01/76.19 26275[80:MRR:24923.0,26274.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.19 26280[81:Spt:26275.2] || -> xuntil6(s47)*. % 76.01/76.19 26281[81:MRR:129.0,26280.0] || -> until5(s48)*. % 76.01/76.19 26282[81:MRR:16882.0,26281.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.01/76.19 26283[82:Spt:26282.1] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.19 26285[82:Res:26283.0,61.1] always3(s49) || -> . % 76.01/76.19 26286[82:SSi:26285.0,50.0,738.0] || -> . % 76.01/76.19 26287[82:Spt:26286.0,26282.1,26283.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.01/76.19 26288[82:Spt:26286.0,26282.0,26282.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 76.01/76.19 26290[82:MRR:774.2,26287.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.01/76.19 26291[82:Res:53.1,26288.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 76.01/76.19 26293[83:Spt:26291.1] || -> xuntil6(s48)*. % 76.01/76.19 26294[83:MRR:128.0,26293.0] || -> until5(s49)*. % 76.01/76.19 26302[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.19 26303[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.19 26304[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.19 26305[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.19 26309[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.19 26310[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.19 26314[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.19 26318[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.19 26322[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.19 26329[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.19 26330[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.19 26334[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.19 26338[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.19 26342[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.19 26349[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.19 26350[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.19 26354[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.19 26358[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.19 26362[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.19 26369[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.19 26370[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.19 26374[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.19 26378[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.19 26382[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.19 26389[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.19 26390[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.19 26394[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.19 26398[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.19 26402[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.19 26409[0:SoR:819.0,66.2] until5(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.19 26410[0:SoR:813.0,66.2] until5(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.19 26414[0:SoR:807.0,66.2] until5(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.19 26418[0:SoR:801.0,66.2] until5(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.19 26422[0:SoR:795.0,66.2] until5(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.19 26429[0:SoR:789.0,66.2] until5(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.19 26430[0:SoR:783.0,66.2] until5(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.19 26434[0:SoR:777.0,66.2] until5(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.19 26436[23:SoR:25944.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 26438[23:SoR:26436.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)* xuntil6(s49). % 76.01/76.19 26439[83:SSi:26438.0,50.0,738.0,26294.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s28,c_busy)* xuntil6(s49). % 76.01/76.19 26440[84:Spt:26439.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 26442[84:Res:26440.0,61.1] always3(s28) || -> . % 76.01/76.19 26443[84:SSi:26442.0,717.0,26069.0,26084.0] || -> . % 76.01/76.19 26444[84:Spt:26443.0,26439.1,26440.0] || m_main_v_state(s28,c_busy)*+ -> . % 76.01/76.19 26445[84:Spt:26443.0,26439.0,26439.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.01/76.19 26449[84:MRR:26436.2,26444.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.01/76.19 26450[84:Res:53.1,26445.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.01/76.19 26452[84:MRR:26450.0,26287.0] || -> xuntil6(s49)*. % 76.01/76.19 26453[84:MRR:25943.0,26452.0] || -> until2p7(s28)*. % 76.01/76.19 26454[84:MRR:224.0,26453.0] || -> until2p7(s29)* node4(s28). % 76.01/76.19 26455[85:Spt:26454.0] || -> until2p7(s29)*. % 76.01/76.19 26456[85:MRR:225.0,26455.0] || -> until2p7(s30)* node4(s29). % 76.01/76.19 26457[86:Spt:26456.0] || -> until2p7(s30)*. % 76.01/76.19 26458[86:MRR:226.0,26457.0] || -> until2p7(s31)* node4(s30). % 76.01/76.19 26459[87:Spt:26458.0] || -> until2p7(s31)*. % 76.01/76.19 26460[87:MRR:227.0,26459.0] || -> until2p7(s32)* node4(s31). % 76.01/76.19 26461[88:Spt:26460.0] || -> until2p7(s32)*. % 76.01/76.19 26462[88:MRR:228.0,26461.0] || -> until2p7(s33)* node4(s32). % 76.01/76.19 26463[89:Spt:26462.0] || -> until2p7(s33)*. % 76.01/76.19 26464[89:MRR:229.0,26463.0] || -> until2p7(s34)* node4(s33). % 76.01/76.19 26465[90:Spt:26464.0] || -> until2p7(s34)*. % 76.01/76.19 26466[90:MRR:230.0,26465.0] || -> until2p7(s35)* node4(s34). % 76.01/76.19 26467[91:Spt:26466.0] || -> until2p7(s35)*. % 76.01/76.19 26468[91:MRR:231.0,26467.0] || -> until2p7(s36)* node4(s35). % 76.01/76.19 26469[92:Spt:26468.0] || -> until2p7(s36)*. % 76.01/76.19 26470[92:MRR:232.0,26469.0] || -> until2p7(s37)* node4(s36). % 76.01/76.19 26471[93:Spt:26470.0] || -> until2p7(s37)*. % 76.01/76.19 26472[93:MRR:235.0,26471.0] || -> until2p7(s38)* node4(s37). % 76.01/76.19 26473[94:Spt:26472.0] || -> until2p7(s38)*. % 76.01/76.19 26474[94:MRR:236.0,26473.0] || -> until2p7(s39)* node4(s38). % 76.01/76.19 26475[95:Spt:26474.0] || -> until2p7(s39)*. % 76.01/76.19 26476[95:MRR:237.0,26475.0] || -> until2p7(s40)* node4(s39). % 76.01/76.19 26477[96:Spt:26476.0] || -> until2p7(s40)*. % 76.01/76.19 26478[96:MRR:238.0,26477.0] || -> until2p7(s41)* node4(s40). % 76.01/76.19 26479[97:Spt:26478.0] || -> until2p7(s41)*. % 76.01/76.19 26480[97:MRR:239.0,26479.0] || -> until2p7(s42)* node4(s41). % 76.01/76.19 26481[98:Spt:26480.0] || -> until2p7(s42)*. % 76.01/76.19 26482[98:MRR:240.0,26481.0] || -> until2p7(s43)* node4(s42). % 76.01/76.19 26483[99:Spt:26482.0] || -> until2p7(s43)*. % 76.01/76.19 26484[99:MRR:241.0,26483.0] || -> until2p7(s44)* node4(s43). % 76.01/76.19 26485[100:Spt:26484.0] || -> until2p7(s44)*. % 76.01/76.19 26486[100:MRR:539.0,26485.0] || -> until2p7(s45)* node4(s44). % 76.01/76.19 26487[101:Spt:26486.0] || -> until2p7(s45)*. % 76.01/76.19 26488[101:MRR:544.0,26487.0] || -> until2p7(s46)* node4(s45). % 76.01/76.19 26489[102:Spt:26488.0] || -> until2p7(s46)*. % 76.01/76.19 26490[102:MRR:549.0,26489.0] || -> until2p7(s47)* node4(s46). % 76.01/76.19 26491[103:Spt:26490.0] || -> until2p7(s47)*. % 76.01/76.19 26492[103:MRR:554.0,26491.0] || -> until2p7(s48)* node4(s47). % 76.01/76.19 26493[104:Spt:26492.0] || -> until2p7(s48)*. % 76.01/76.19 26494[104:MRR:559.0,26493.0] || -> until2p7(s49)* node4(s48). % 76.01/76.19 26495[105:Spt:26494.0] || -> until2p7(s49)*. % 76.01/76.19 26496[105:MRR:194.0,26495.0] || -> node4(s49)*. % 76.01/76.19 26497[105:MRR:26449.0,26496.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.01/76.19 26498[105:Res:53.1,26497.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.19 26500[105:MRR:26498.0,26287.0] || -> . % 76.01/76.19 26501[105:Spt:26500.0,26494.0,26495.0] || until2p7(s49)*+ -> . % 76.01/76.19 26502[105:Spt:26500.0,26494.1] || -> node4(s48)*. % 76.01/76.19 26503[105:MRR:26290.0,26502.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.01/76.19 26506[105:Res:53.1,26503.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.19 26509[105:Res:26506.0,61.1] always3(s48) || -> . % 76.01/76.19 26510[105:SSi:26509.0,737.0,26281.0,26293.0,26493.0,26502.0] || -> . % 76.01/76.19 26511[104:Spt:26510.0,26492.0,26493.0] || until2p7(s48)*+ -> . % 76.01/76.19 26512[104:Spt:26510.0,26492.1] || -> node4(s47)*. % 76.01/76.19 26514[104:MRR:777.0,26512.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.01/76.19 26533[104:Res:53.1,26514.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.01/76.19 26535[104:MRR:26533.0,26267.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.19 26537[104:Res:26535.0,61.1] always3(s48) || -> . % 76.01/76.19 26538[104:SSi:26537.0,737.0,26281.0,26293.0] || -> . % 76.01/76.19 26539[103:Spt:26538.0,26490.0,26491.0] || until2p7(s47)*+ -> . % 76.01/76.19 26540[103:Spt:26538.0,26490.1] || -> node4(s46)*. % 76.01/76.19 26541[103:MRR:26270.0,26540.0] || m_main_v_state(s46,c_ready)*+ -> . % 76.01/76.19 26545[103:Res:53.1,26541.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.19 26548[103:Res:26545.0,61.1] always3(s46) || -> . % 76.01/76.19 26549[103:SSi:26548.0,735.0,26261.0,26273.0,26489.0,26540.0] || -> . % 76.01/76.19 26550[102:Spt:26549.0,26488.0,26489.0] || until2p7(s46)*+ -> . % 76.01/76.19 26551[102:Spt:26549.0,26488.1] || -> node4(s45)*. % 76.01/76.19 26553[102:MRR:783.0,26551.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.01/76.19 26564[102:Res:53.1,26553.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.01/76.19 26566[102:MRR:26564.0,26247.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.19 26568[102:Res:26566.0,61.1] always3(s46) || -> . % 76.01/76.19 26569[102:SSi:26568.0,735.0,26261.0,26273.0] || -> . % 76.01/76.19 26570[101:Spt:26569.0,26486.0,26487.0] || until2p7(s45)*+ -> . % 76.01/76.19 26571[101:Spt:26569.0,26486.1] || -> node4(s44)*. % 76.01/76.19 26572[101:MRR:26250.0,26571.0] || m_main_v_state(s44,c_ready)*+ -> . % 76.01/76.19 26575[101:Res:53.1,26572.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.19 26578[101:Res:26575.0,61.1] always3(s44) || -> . % 76.01/76.19 26579[101:SSi:26578.0,733.0,26241.0,26256.0,26485.0,26571.0] || -> . % 76.01/76.19 26580[100:Spt:26579.0,26484.0,26485.0] || until2p7(s44)*+ -> . % 76.01/76.19 26581[100:Spt:26579.0,26484.1] || -> node4(s43)*. % 76.01/76.19 26583[100:MRR:789.0,26581.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.01/76.19 26595[100:Res:53.1,26583.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.01/76.19 26597[100:MRR:26595.0,26224.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.19 26599[100:Res:26597.0,61.1] always3(s44) || -> . % 76.01/76.19 26600[100:SSi:26599.0,733.0,26241.0,26256.0] || -> . % 76.01/76.19 26601[99:Spt:26600.0,26482.0,26483.0] || until2p7(s43)*+ -> . % 76.01/76.19 26602[99:Spt:26600.0,26482.1] || -> node4(s42)*. % 76.01/76.19 26603[99:MRR:26227.0,26602.0] || m_main_v_state(s42,c_ready)*+ -> . % 76.01/76.19 26606[99:Res:53.1,26603.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.19 26609[99:Res:26606.0,61.1] always3(s42) || -> . % 76.01/76.19 26610[99:SSi:26609.0,731.0,26218.0,26230.0,26481.0,26602.0] || -> . % 76.01/76.19 26611[98:Spt:26610.0,26480.0,26481.0] || until2p7(s42)*+ -> . % 76.01/76.19 26612[98:Spt:26610.0,26480.1] || -> node4(s41)*. % 76.01/76.19 26614[98:MRR:795.0,26612.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.01/76.19 26626[98:Res:53.1,26614.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.01/76.19 26628[98:MRR:26626.0,26204.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.19 26633[98:Res:26628.0,61.1] always3(s42) || -> . % 76.01/76.19 26634[98:SSi:26633.0,731.0,26218.0,26230.0] || -> . % 76.01/76.19 26635[97:Spt:26634.0,26478.0,26479.0] || until2p7(s41)*+ -> . % 76.01/76.19 26636[97:Spt:26634.0,26478.1] || -> node4(s40)*. % 76.01/76.19 26637[97:MRR:26207.0,26636.0] || m_main_v_state(s40,c_ready)*+ -> . % 76.01/76.19 26640[97:Res:53.1,26637.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.19 26644[97:Res:26640.0,61.1] always3(s40) || -> . % 76.01/76.19 26645[97:SSi:26644.0,729.0,26198.0,26210.0,26477.0,26636.0] || -> . % 76.01/76.19 26646[96:Spt:26645.0,26476.0,26477.0] || until2p7(s40)*+ -> . % 76.01/76.19 26647[96:Spt:26645.0,26476.1] || -> node4(s39)*. % 76.01/76.19 26649[96:MRR:801.0,26647.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.01/76.19 26660[96:Res:53.1,26649.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.01/76.19 26662[96:MRR:26660.0,26184.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.19 26664[96:Res:26662.0,61.1] always3(s40) || -> . % 76.01/76.19 26665[96:SSi:26664.0,729.0,26198.0,26210.0] || -> . % 76.01/76.19 26666[95:Spt:26665.0,26474.0,26475.0] || until2p7(s39)*+ -> . % 76.01/76.19 26667[95:Spt:26665.0,26474.1] || -> node4(s38)*. % 76.01/76.19 26668[95:MRR:26187.0,26667.0] || m_main_v_state(s38,c_ready)*+ -> . % 76.01/76.19 26672[95:Res:53.1,26668.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.19 26675[95:Res:26672.0,61.1] always3(s38) || -> . % 76.01/76.19 26676[95:SSi:26675.0,727.0,26178.0,26193.0,26473.0,26667.0] || -> . % 76.01/76.19 26677[94:Spt:26676.0,26472.0,26473.0] || until2p7(s38)*+ -> . % 76.01/76.19 26678[94:Spt:26676.0,26472.1] || -> node4(s37)*. % 76.01/76.19 26680[94:MRR:807.0,26678.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.01/76.19 26691[94:Res:53.1,26680.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.01/76.19 26693[94:MRR:26691.0,26161.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.19 26695[94:Res:26693.0,61.1] always3(s38) || -> . % 76.01/76.19 26696[94:SSi:26695.0,727.0,26178.0,26193.0] || -> . % 76.01/76.19 26697[93:Spt:26696.0,26470.0,26471.0] || until2p7(s37)*+ -> . % 76.01/76.19 26698[93:Spt:26696.0,26470.1] || -> node4(s36)*. % 76.01/76.19 26699[93:MRR:26164.0,26698.0] || m_main_v_state(s36,c_ready)*+ -> . % 76.01/76.19 26702[93:Res:53.1,26699.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.19 26705[93:Res:26702.0,61.1] always3(s36) || -> . % 76.01/76.19 26706[93:SSi:26705.0,725.0,26155.0,26167.0,26469.0,26698.0] || -> . % 76.01/76.19 26707[92:Spt:26706.0,26468.0,26469.0] || until2p7(s36)*+ -> . % 76.01/76.19 26708[92:Spt:26706.0,26468.1] || -> node4(s35)*. % 76.01/76.19 26710[92:MRR:813.0,26708.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.01/76.19 26722[92:Res:53.1,26710.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.01/76.19 26724[92:MRR:26722.0,26141.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.19 26726[92:Res:26724.0,61.1] always3(s36) || -> . % 76.01/76.19 26727[92:SSi:26726.0,725.0,26155.0,26167.0] || -> . % 76.01/76.19 26728[91:Spt:26727.0,26466.0,26467.0] || until2p7(s35)*+ -> . % 76.01/76.19 26729[91:Spt:26727.0,26466.1] || -> node4(s34)*. % 76.01/76.19 26730[91:MRR:26144.0,26729.0] || m_main_v_state(s34,c_ready)*+ -> . % 76.01/76.19 26733[91:Res:53.1,26730.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.19 26736[91:Res:26733.0,61.1] always3(s34) || -> . % 76.01/76.19 26737[91:SSi:26736.0,723.0,26135.0,26147.0,26465.0,26729.0] || -> . % 76.01/76.19 26738[90:Spt:26737.0,26464.0,26465.0] || until2p7(s34)*+ -> . % 76.01/76.19 26739[90:Spt:26737.0,26464.1] || -> node4(s33)*. % 76.01/76.19 26741[90:MRR:819.0,26739.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.01/76.19 26753[90:Res:53.1,26741.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.01/76.19 26755[90:MRR:26753.0,26121.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.19 26760[90:Res:26755.0,61.1] always3(s34) || -> . % 76.01/76.19 26761[90:SSi:26760.0,723.0,26135.0,26147.0] || -> . % 76.01/76.19 26762[89:Spt:26761.0,26462.0,26463.0] || until2p7(s33)*+ -> . % 76.01/76.19 26763[89:Spt:26761.0,26462.1] || -> node4(s32)*. % 76.01/76.19 26764[89:MRR:26124.0,26763.0] || m_main_v_state(s32,c_ready)*+ -> . % 76.01/76.19 26767[89:Res:53.1,26764.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.19 26771[89:Res:26767.0,61.1] always3(s32) || -> . % 76.01/76.19 26772[89:SSi:26771.0,721.0,26115.0,26130.0,26461.0,26763.0] || -> . % 76.01/76.19 26773[88:Spt:26772.0,26460.0,26461.0] || until2p7(s32)*+ -> . % 76.01/76.19 26774[88:Spt:26772.0,26460.1] || -> node4(s31)*. % 76.01/76.19 26776[88:MRR:825.0,26774.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.01/76.19 26787[88:Res:53.1,26776.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.01/76.19 26789[88:MRR:26787.0,26098.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.19 26791[88:Res:26789.0,61.1] always3(s32) || -> . % 76.01/76.19 26792[88:SSi:26791.0,721.0,26115.0,26130.0] || -> . % 76.01/76.19 26793[87:Spt:26792.0,26458.0,26459.0] || until2p7(s31)*+ -> . % 76.01/76.19 26794[87:Spt:26792.0,26458.1] || -> node4(s30)*. % 76.01/76.19 26795[87:MRR:26101.0,26794.0] || m_main_v_state(s30,c_ready)*+ -> . % 76.01/76.19 26799[87:Res:53.1,26795.0] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.19 26802[87:Res:26799.0,61.1] always3(s30) || -> . % 76.01/76.19 26803[87:SSi:26802.0,719.0,26092.0,26104.0,26457.0,26794.0] || -> . % 76.01/76.19 26804[86:Spt:26803.0,26456.0,26457.0] || until2p7(s30)*+ -> . % 76.01/76.19 26805[86:Spt:26803.0,26456.1] || -> node4(s29)*. % 76.01/76.19 26807[86:MRR:831.0,26805.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.01/76.19 26818[86:Res:53.1,26807.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.01/76.19 26820[86:MRR:26818.0,26078.0] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.19 26822[86:Res:26820.0,61.1] always3(s30) || -> . % 76.01/76.19 26823[86:SSi:26822.0,719.0,26092.0,26104.0] || -> . % 76.01/76.19 26824[85:Spt:26823.0,26454.0,26455.0] || until2p7(s29)*+ -> . % 76.01/76.19 26825[85:Spt:26823.0,26454.1] || -> node4(s28)*. % 76.01/76.19 26826[85:MRR:26081.0,26825.0] || m_main_v_state(s28,c_ready)*+ -> . % 76.01/76.19 26829[85:Res:53.1,26826.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 26831[85:MRR:26829.0,26444.0] || -> . % 76.01/76.19 26832[83:Spt:26831.0,26291.1,26293.0] || xuntil6(s48)* -> . % 76.01/76.19 26833[83:Spt:26831.0,26291.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.19 26836[83:Res:26833.0,61.1] always3(s48) || -> . % 76.01/76.19 26837[83:SSi:26836.0,737.0,26281.0] || -> . % 76.01/76.19 26838[81:Spt:26837.0,26275.2,26280.0] || xuntil6(s47)*+ -> . % 76.01/76.19 26839[81:Spt:26837.0,26275.0,26275.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.01/76.19 26840[81:Res:53.1,26839.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.01/76.19 26842[81:MRR:26840.0,26267.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.19 26844[81:Res:26842.0,61.1] always3(s48) || -> . % 76.01/76.19 26845[81:SSi:26844.0,737.0] || -> . % 76.01/76.19 26846[80:Spt:26845.0,26271.1,26273.0] || xuntil6(s46)* -> . % 76.01/76.19 26847[80:Spt:26845.0,26271.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.19 26850[80:Res:26847.0,61.1] always3(s46) || -> . % 76.01/76.19 26851[80:SSi:26850.0,735.0,26261.0] || -> . % 76.01/76.19 26852[78:Spt:26851.0,26258.2,26260.0] || xuntil6(s45)*+ -> . % 76.01/76.19 26853[78:Spt:26851.0,26258.0,26258.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.01/76.19 26854[78:Res:53.1,26853.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.01/76.19 26856[78:MRR:26854.0,26247.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.19 26859[78:Res:26856.0,61.1] always3(s46) || -> . % 76.01/76.19 26860[78:SSi:26859.0,735.0] || -> . % 76.01/76.19 26861[77:Spt:26860.0,26251.1,26256.0] || xuntil6(s44)* -> . % 76.01/76.19 26862[77:Spt:26860.0,26251.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.19 26865[77:Res:26862.0,61.1] always3(s44) || -> . % 76.01/76.19 26866[77:SSi:26865.0,733.0,26241.0] || -> . % 76.01/76.19 26867[75:Spt:26866.0,26232.2,26240.0] || xuntil6(s43)*+ -> . % 76.01/76.19 26868[75:Spt:26866.0,26232.0,26232.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.01/76.19 26869[75:Res:53.1,26868.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.01/76.19 26871[75:MRR:26869.0,26224.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.19 26873[75:Res:26871.0,61.1] always3(s44) || -> . % 76.01/76.19 26874[75:SSi:26873.0,733.0] || -> . % 76.01/76.19 26875[74:Spt:26874.0,26228.1,26230.0] || xuntil6(s42)* -> . % 76.01/76.19 26876[74:Spt:26874.0,26228.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.19 26879[74:Res:26876.0,61.1] always3(s42) || -> . % 76.01/76.19 26880[74:SSi:26879.0,731.0,26218.0] || -> . % 76.01/76.19 26881[72:Spt:26880.0,26212.2,26217.0] || xuntil6(s41)*+ -> . % 76.01/76.19 26882[72:Spt:26880.0,26212.0,26212.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.01/76.19 26883[72:Res:53.1,26882.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.01/76.19 26885[72:MRR:26883.0,26204.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.19 26888[72:Res:26885.0,61.1] always3(s42) || -> . % 76.01/76.19 26889[72:SSi:26888.0,731.0] || -> . % 76.01/76.19 26890[71:Spt:26889.0,26208.1,26210.0] || xuntil6(s40)* -> . % 76.01/76.19 26891[71:Spt:26889.0,26208.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.19 26894[71:Res:26891.0,61.1] always3(s40) || -> . % 76.01/76.19 26895[71:SSi:26894.0,729.0,26198.0] || -> . % 76.01/76.19 26896[69:Spt:26895.0,26195.2,26197.0] || xuntil6(s39)*+ -> . % 76.01/76.19 26897[69:Spt:26895.0,26195.0,26195.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.01/76.19 26898[69:Res:53.1,26897.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.01/76.19 26900[69:MRR:26898.0,26184.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.19 26902[69:Res:26900.0,61.1] always3(s40) || -> . % 76.01/76.19 26903[69:SSi:26902.0,729.0] || -> . % 76.01/76.19 26904[68:Spt:26903.0,26188.1,26193.0] || xuntil6(s38)* -> . % 76.01/76.19 26905[68:Spt:26903.0,26188.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.19 26908[68:Res:26905.0,61.1] always3(s38) || -> . % 76.01/76.19 26909[68:SSi:26908.0,727.0,26178.0] || -> . % 76.01/76.19 26910[66:Spt:26909.0,26169.2,26177.0] || xuntil6(s37)*+ -> . % 76.01/76.19 26911[66:Spt:26909.0,26169.0,26169.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.01/76.19 26912[66:Res:53.1,26911.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.01/76.19 26914[66:MRR:26912.0,26161.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.19 26917[66:Res:26914.0,61.1] always3(s38) || -> . % 76.01/76.19 26918[66:SSi:26917.0,727.0] || -> . % 76.01/76.19 26919[65:Spt:26918.0,26165.1,26167.0] || xuntil6(s36)* -> . % 76.01/76.19 26920[65:Spt:26918.0,26165.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.19 26923[65:Res:26920.0,61.1] always3(s36) || -> . % 76.01/76.19 26924[65:SSi:26923.0,725.0,26155.0] || -> . % 76.01/76.19 26925[63:Spt:26924.0,26149.2,26154.0] || xuntil6(s35)*+ -> . % 76.01/76.19 26926[63:Spt:26924.0,26149.0,26149.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.01/76.19 26927[63:Res:53.1,26926.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.01/76.19 26929[63:MRR:26927.0,26141.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.19 26931[63:Res:26929.0,61.1] always3(s36) || -> . % 76.01/76.19 26932[63:SSi:26931.0,725.0] || -> . % 76.01/76.19 26933[62:Spt:26932.0,26145.1,26147.0] || xuntil6(s34)* -> . % 76.01/76.19 26934[62:Spt:26932.0,26145.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.19 26937[62:Res:26934.0,61.1] always3(s34) || -> . % 76.01/76.19 26938[62:SSi:26937.0,723.0,26135.0] || -> . % 76.01/76.19 26939[60:Spt:26938.0,26132.2,26134.0] || xuntil6(s33)*+ -> . % 76.01/76.19 26940[60:Spt:26938.0,26132.0,26132.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.01/76.19 26941[60:Res:53.1,26940.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.01/76.19 26943[60:MRR:26941.0,26121.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.19 26945[60:Res:26943.0,61.1] always3(s34) || -> . % 76.01/76.19 26946[60:SSi:26945.0,723.0] || -> . % 76.01/76.19 26947[59:Spt:26946.0,26125.1,26130.0] || xuntil6(s32)* -> . % 76.01/76.19 26948[59:Spt:26946.0,26125.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.19 26951[59:Res:26948.0,61.1] always3(s32) || -> . % 76.01/76.19 26952[59:SSi:26951.0,721.0,26115.0] || -> . % 76.01/76.19 26953[57:Spt:26952.0,26106.2,26114.0] || xuntil6(s31)*+ -> . % 76.01/76.19 26954[57:Spt:26952.0,26106.0,26106.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.01/76.19 26955[57:Res:53.1,26954.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.01/76.19 26957[57:MRR:26955.0,26098.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.19 26959[57:Res:26957.0,61.1] always3(s32) || -> . % 76.01/76.19 26960[57:SSi:26959.0,721.0] || -> . % 76.01/76.19 26961[56:Spt:26960.0,26102.1,26104.0] || xuntil6(s30)* -> . % 76.01/76.19 26962[56:Spt:26960.0,26102.0] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.19 26965[56:Res:26962.0,61.1] always3(s30) || -> . % 76.01/76.19 26966[56:SSi:26965.0,719.0,26092.0] || -> . % 76.01/76.19 26967[54:Spt:26966.0,26086.2,26091.0] || xuntil6(s29)*+ -> . % 76.01/76.19 26968[54:Spt:26966.0,26086.0,26086.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.01/76.19 26969[54:Res:53.1,26968.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.01/76.19 26971[54:MRR:26969.0,26078.0] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.19 26973[54:Res:26971.0,61.1] always3(s30) || -> . % 76.01/76.19 26974[54:SSi:26973.0,719.0] || -> . % 76.01/76.19 26975[53:Spt:26974.0,26082.1,26084.0] || xuntil6(s28)* -> . % 76.01/76.19 26976[53:Spt:26974.0,26082.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 26979[53:Res:26976.0,61.1] always3(s28) || -> . % 76.01/76.19 26980[53:SSi:26979.0,717.0,26069.0] || -> . % 76.01/76.19 26981[51:Spt:26980.0,26067.2,26068.0] || xuntil6(s27)*+ -> . % 76.01/76.19 26982[51:Spt:26980.0,26067.0,26067.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.01/76.19 26983[51:Res:53.1,26982.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.01/76.19 26985[52:Spt:26983.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.19 26987[52:Res:26985.0,61.1] always3(s27) || -> . % 76.01/76.19 26988[52:SSi:26987.0,716.0,26066.0] || -> . % 76.01/76.19 26989[52:Spt:26988.0,26983.0,26985.0] || m_main_v_state(s27,c_busy)* -> . % 76.01/76.19 26990[52:Spt:26988.0,26983.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 26994[52:Res:26990.0,61.1] always3(s28) || -> . % 76.01/76.19 26995[52:SSi:26994.0,717.0] || -> . % 76.01/76.19 26996[50:Spt:26995.0,26061.2,26065.0] || xuntil6(s26)*+ -> . % 76.01/76.19 26997[50:Spt:26995.0,26061.0,26061.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.01/76.19 26998[50:Res:53.1,26997.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.01/76.19 27000[51:Spt:26998.0] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.19 27002[51:Res:27000.0,61.1] always3(s26) || -> . % 76.01/76.19 27003[51:SSi:27002.0,715.0,26060.0] || -> . % 76.01/76.19 27004[51:Spt:27003.0,26998.0,27000.0] || m_main_v_state(s26,c_busy)* -> . % 76.01/76.19 27005[51:Spt:27003.0,26998.1] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.19 27009[51:Res:27005.0,61.1] always3(s27) || -> . % 76.01/76.19 27010[51:SSi:27009.0,716.0] || -> . % 76.01/76.19 27011[49:Spt:27010.0,26058.2,26059.0] || xuntil6(s25)*+ -> . % 76.01/76.19 27012[49:Spt:27010.0,26058.0,26058.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.01/76.19 27013[49:Res:53.1,27012.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.01/76.19 27015[50:Spt:27013.0] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.19 27017[50:Res:27015.0,61.1] always3(s25) || -> . % 76.01/76.19 27018[50:SSi:27017.0,714.0,26057.0] || -> . % 76.01/76.19 27019[50:Spt:27018.0,27013.0,27015.0] || m_main_v_state(s25,c_busy)* -> . % 76.01/76.19 27020[50:Spt:27018.0,27013.1] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.19 27024[50:Res:27020.0,61.1] always3(s26) || -> . % 76.01/76.19 27025[50:SSi:27024.0,715.0] || -> . % 76.01/76.19 27026[48:Spt:27025.0,26052.2,26056.0] || xuntil6(s24)*+ -> . % 76.01/76.19 27027[48:Spt:27025.0,26052.0,26052.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.01/76.19 27028[48:Res:53.1,27027.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.01/76.19 27030[49:Spt:27028.0] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.19 27032[49:Res:27030.0,61.1] always3(s24) || -> . % 76.01/76.19 27033[49:SSi:27032.0,713.0,26051.0] || -> . % 76.01/76.19 27034[49:Spt:27033.0,27028.0,27030.0] || m_main_v_state(s24,c_busy)* -> . % 76.01/76.19 27035[49:Spt:27033.0,27028.1] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.19 27039[49:Res:27035.0,61.1] always3(s25) || -> . % 76.01/76.19 27040[49:SSi:27039.0,714.0] || -> . % 76.01/76.19 27041[47:Spt:27040.0,26049.2,26050.0] || xuntil6(s23)*+ -> . % 76.01/76.19 27042[47:Spt:27040.0,26049.0,26049.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.01/76.19 27043[47:Res:53.1,27042.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.01/76.19 27045[48:Spt:27043.0] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.19 27047[48:Res:27045.0,61.1] always3(s23) || -> . % 76.01/76.19 27048[48:SSi:27047.0,712.0,26048.0] || -> . % 76.01/76.19 27049[48:Spt:27048.0,27043.0,27045.0] || m_main_v_state(s23,c_busy)* -> . % 76.01/76.19 27050[48:Spt:27048.0,27043.1] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.19 27054[48:Res:27050.0,61.1] always3(s24) || -> . % 76.01/76.19 27055[48:SSi:27054.0,713.0] || -> . % 76.01/76.19 27056[46:Spt:27055.0,26043.2,26047.0] || xuntil6(s22)*+ -> . % 76.01/76.19 27057[46:Spt:27055.0,26043.0,26043.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.01/76.19 27058[46:Res:53.1,27057.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.01/76.19 27060[47:Spt:27058.0] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.19 27062[47:Res:27060.0,61.1] always3(s22) || -> . % 76.01/76.19 27063[47:SSi:27062.0,711.0,26042.0] || -> . % 76.01/76.19 27064[47:Spt:27063.0,27058.0,27060.0] || m_main_v_state(s22,c_busy)* -> . % 76.01/76.19 27065[47:Spt:27063.0,27058.1] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.19 27069[47:Res:27065.0,61.1] always3(s23) || -> . % 76.01/76.19 27070[47:SSi:27069.0,712.0] || -> . % 76.01/76.19 27071[45:Spt:27070.0,26040.2,26041.0] || xuntil6(s21)*+ -> . % 76.01/76.19 27072[45:Spt:27070.0,26040.0,26040.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.01/76.19 27073[45:Res:53.1,27072.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.01/76.19 27075[46:Spt:27073.0] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.19 27077[46:Res:27075.0,61.1] always3(s21) || -> . % 76.01/76.19 27078[46:SSi:27077.0,710.0,26039.0] || -> . % 76.01/76.19 27079[46:Spt:27078.0,27073.0,27075.0] || m_main_v_state(s21,c_busy)* -> . % 76.01/76.19 27080[46:Spt:27078.0,27073.1] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.19 27084[46:Res:27080.0,61.1] always3(s22) || -> . % 76.01/76.19 27085[46:SSi:27084.0,711.0] || -> . % 76.01/76.19 27086[44:Spt:27085.0,26034.2,26038.0] || xuntil6(s20)*+ -> . % 76.01/76.19 27087[44:Spt:27085.0,26034.0,26034.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.01/76.19 27088[44:Res:53.1,27087.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.01/76.19 27090[45:Spt:27088.0] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.19 27092[45:Res:27090.0,61.1] always3(s20) || -> . % 76.01/76.19 27093[45:SSi:27092.0,709.0,26033.0] || -> . % 76.01/76.19 27094[45:Spt:27093.0,27088.0,27090.0] || m_main_v_state(s20,c_busy)* -> . % 76.01/76.19 27095[45:Spt:27093.0,27088.1] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.19 27099[45:Res:27095.0,61.1] always3(s21) || -> . % 76.01/76.19 27100[45:SSi:27099.0,710.0] || -> . % 76.01/76.19 27101[43:Spt:27100.0,26031.2,26032.0] || xuntil6(s19)*+ -> . % 76.01/76.19 27102[43:Spt:27100.0,26031.0,26031.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.01/76.19 27103[43:Res:53.1,27102.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.01/76.19 27105[44:Spt:27103.0] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.19 27107[44:Res:27105.0,61.1] always3(s19) || -> . % 76.01/76.19 27108[44:SSi:27107.0,708.0,26030.0] || -> . % 76.01/76.19 27109[44:Spt:27108.0,27103.0,27105.0] || m_main_v_state(s19,c_busy)* -> . % 76.01/76.19 27110[44:Spt:27108.0,27103.1] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.19 27114[44:Res:27110.0,61.1] always3(s20) || -> . % 76.01/76.19 27115[44:SSi:27114.0,709.0] || -> . % 76.01/76.19 27116[42:Spt:27115.0,26025.2,26029.0] || xuntil6(s18)*+ -> . % 76.01/76.19 27117[42:Spt:27115.0,26025.0,26025.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.01/76.19 27118[42:Res:53.1,27117.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.01/76.19 27120[43:Spt:27118.0] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.19 27122[43:Res:27120.0,61.1] always3(s18) || -> . % 76.01/76.19 27123[43:SSi:27122.0,707.0,26024.0] || -> . % 76.01/76.19 27124[43:Spt:27123.0,27118.0,27120.0] || m_main_v_state(s18,c_busy)* -> . % 76.01/76.19 27125[43:Spt:27123.0,27118.1] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.19 27129[43:Res:27125.0,61.1] always3(s19) || -> . % 76.01/76.19 27130[43:SSi:27129.0,708.0] || -> . % 76.01/76.19 27131[41:Spt:27130.0,26022.2,26023.0] || xuntil6(s17)*+ -> . % 76.01/76.19 27132[41:Spt:27130.0,26022.0,26022.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.01/76.19 27133[41:Res:53.1,27132.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.01/76.19 27135[42:Spt:27133.0] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.19 27137[42:Res:27135.0,61.1] always3(s17) || -> . % 76.01/76.19 27138[42:SSi:27137.0,706.0,26021.0] || -> . % 76.01/76.19 27139[42:Spt:27138.0,27133.0,27135.0] || m_main_v_state(s17,c_busy)* -> . % 76.01/76.19 27140[42:Spt:27138.0,27133.1] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.19 27144[42:Res:27140.0,61.1] always3(s18) || -> . % 76.01/76.19 27145[42:SSi:27144.0,707.0] || -> . % 76.01/76.19 27146[40:Spt:27145.0,26016.2,26020.0] || xuntil6(s16)*+ -> . % 76.01/76.19 27147[40:Spt:27145.0,26016.0,26016.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.01/76.19 27148[40:Res:53.1,27147.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.01/76.19 27153[41:Spt:27148.0] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.19 27155[41:Res:27153.0,61.1] always3(s16) || -> . % 76.01/76.19 27156[41:SSi:27155.0,705.0,26015.0] || -> . % 76.01/76.19 27157[41:Spt:27156.0,27148.0,27153.0] || m_main_v_state(s16,c_busy)* -> . % 76.01/76.19 27158[41:Spt:27156.0,27148.1] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.19 27162[41:Res:27158.0,61.1] always3(s17) || -> . % 76.01/76.19 27163[41:SSi:27162.0,706.0] || -> . % 76.01/76.19 27164[39:Spt:27163.0,26013.2,26014.0] || xuntil6(s15)*+ -> . % 76.01/76.19 27165[39:Spt:27163.0,26013.0,26013.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.01/76.19 27166[39:Res:53.1,27165.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.01/76.19 27168[40:Spt:27166.0] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.19 27170[40:Res:27168.0,61.1] always3(s15) || -> . % 76.01/76.19 27171[40:SSi:27170.0,704.0,26012.0] || -> . % 76.01/76.19 27172[40:Spt:27171.0,27166.0,27168.0] || m_main_v_state(s15,c_busy)* -> . % 76.01/76.19 27173[40:Spt:27171.0,27166.1] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.19 27177[40:Res:27173.0,61.1] always3(s16) || -> . % 76.01/76.19 27178[40:SSi:27177.0,705.0] || -> . % 76.01/76.19 27179[38:Spt:27178.0,26007.2,26011.0] || xuntil6(s14)*+ -> . % 76.01/76.19 27180[38:Spt:27178.0,26007.0,26007.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.01/76.19 27181[38:Res:53.1,27180.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.01/76.19 27183[39:Spt:27181.0] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.19 27185[39:Res:27183.0,61.1] always3(s14) || -> . % 76.01/76.19 27186[39:SSi:27185.0,703.0,26006.0] || -> . % 76.01/76.19 27187[39:Spt:27186.0,27181.0,27183.0] || m_main_v_state(s14,c_busy)* -> . % 76.01/76.19 27188[39:Spt:27186.0,27181.1] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.19 27192[39:Res:27188.0,61.1] always3(s15) || -> . % 76.01/76.19 27193[39:SSi:27192.0,704.0] || -> . % 76.01/76.19 27194[37:Spt:27193.0,26004.2,26005.0] || xuntil6(s13)*+ -> . % 76.01/76.19 27195[37:Spt:27193.0,26004.0,26004.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.01/76.19 27196[37:Res:53.1,27195.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.01/76.19 27201[38:Spt:27196.0] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.19 27203[38:Res:27201.0,61.1] always3(s13) || -> . % 76.01/76.19 27204[38:SSi:27203.0,702.0,26003.0] || -> . % 76.01/76.19 27205[38:Spt:27204.0,27196.0,27201.0] || m_main_v_state(s13,c_busy)* -> . % 76.01/76.19 27206[38:Spt:27204.0,27196.1] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.19 27210[38:Res:27206.0,61.1] always3(s14) || -> . % 76.01/76.19 27211[38:SSi:27210.0,703.0] || -> . % 76.01/76.19 27212[36:Spt:27211.0,25998.2,26002.0] || xuntil6(s12)*+ -> . % 76.01/76.19 27213[36:Spt:27211.0,25998.0,25998.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.01/76.19 27214[36:Res:53.1,27213.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.01/76.19 27216[37:Spt:27214.0] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.19 27218[37:Res:27216.0,61.1] always3(s12) || -> . % 76.01/76.19 27219[37:SSi:27218.0,701.0,25997.0] || -> . % 76.01/76.19 27220[37:Spt:27219.0,27214.0,27216.0] || m_main_v_state(s12,c_busy)* -> . % 76.01/76.19 27221[37:Spt:27219.0,27214.1] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.19 27225[37:Res:27221.0,61.1] always3(s13) || -> . % 76.01/76.19 27226[37:SSi:27225.0,702.0] || -> . % 76.01/76.19 27227[35:Spt:27226.0,25995.2,25996.0] || xuntil6(s11)*+ -> . % 76.01/76.19 27228[35:Spt:27226.0,25995.0,25995.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.01/76.19 27229[35:Res:53.1,27228.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.01/76.19 27231[36:Spt:27229.0] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.19 27233[36:Res:27231.0,61.1] always3(s11) || -> . % 76.01/76.19 27234[36:SSi:27233.0,700.0,25994.0] || -> . % 76.01/76.19 27235[36:Spt:27234.0,27229.0,27231.0] || m_main_v_state(s11,c_busy)* -> . % 76.01/76.19 27236[36:Spt:27234.0,27229.1] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.19 27240[36:Res:27236.0,61.1] always3(s12) || -> . % 76.01/76.19 27241[36:SSi:27240.0,701.0] || -> . % 76.01/76.19 27242[34:Spt:27241.0,25989.2,25993.0] || xuntil6(s10)*+ -> . % 76.01/76.19 27243[34:Spt:27241.0,25989.0,25989.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.01/76.19 27244[34:Res:53.1,27243.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.01/76.19 27249[35:Spt:27244.0] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.19 27251[35:Res:27249.0,61.1] always3(s10) || -> . % 76.01/76.19 27252[35:SSi:27251.0,699.0,25988.0] || -> . % 76.01/76.19 27253[35:Spt:27252.0,27244.0,27249.0] || m_main_v_state(s10,c_busy)* -> . % 76.01/76.19 27254[35:Spt:27252.0,27244.1] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.19 27258[35:Res:27254.0,61.1] always3(s11) || -> . % 76.01/76.19 27259[35:SSi:27258.0,700.0] || -> . % 76.01/76.19 27260[33:Spt:27259.0,25986.2,25987.0] || xuntil6(s9)*+ -> . % 76.01/76.19 27261[33:Spt:27259.0,25986.0,25986.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.01/76.19 27262[33:Res:53.1,27261.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.01/76.19 27264[34:Spt:27262.0] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.19 27266[34:Res:27264.0,61.1] always3(s9) || -> . % 76.01/76.19 27267[34:SSi:27266.0,698.0,25985.0] || -> . % 76.01/76.19 27268[34:Spt:27267.0,27262.0,27264.0] || m_main_v_state(s9,c_busy)* -> . % 76.01/76.19 27269[34:Spt:27267.0,27262.1] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.19 27273[34:Res:27269.0,61.1] always3(s10) || -> . % 76.01/76.19 27274[34:SSi:27273.0,699.0] || -> . % 76.01/76.19 27275[32:Spt:27274.0,25980.2,25984.0] || xuntil6(s8)*+ -> . % 76.01/76.19 27276[32:Spt:27274.0,25980.0,25980.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.01/76.19 27277[32:Res:53.1,27276.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.01/76.19 27279[33:Spt:27277.0] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.19 27281[33:Res:27279.0,61.1] always3(s8) || -> . % 76.01/76.19 27282[33:SSi:27281.0,697.0,25979.0] || -> . % 76.01/76.19 27283[33:Spt:27282.0,27277.0,27279.0] || m_main_v_state(s8,c_busy)* -> . % 76.01/76.19 27284[33:Spt:27282.0,27277.1] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.19 27288[33:Res:27284.0,61.1] always3(s9) || -> . % 76.01/76.19 27289[33:SSi:27288.0,698.0] || -> . % 76.01/76.19 27290[31:Spt:27289.0,25977.2,25978.0] || xuntil6(s7)*+ -> . % 76.01/76.19 27291[31:Spt:27289.0,25977.0,25977.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.01/76.19 27292[31:Res:53.1,27291.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.01/76.19 27297[32:Spt:27292.0] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.19 27299[32:Res:27297.0,61.1] always3(s7) || -> . % 76.01/76.19 27300[32:SSi:27299.0,696.0,25976.0] || -> . % 76.01/76.19 27301[32:Spt:27300.0,27292.0,27297.0] || m_main_v_state(s7,c_busy)* -> . % 76.01/76.19 27302[32:Spt:27300.0,27292.1] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.19 27306[32:Res:27302.0,61.1] always3(s8) || -> . % 76.01/76.19 27307[32:SSi:27306.0,697.0] || -> . % 76.01/76.19 27308[30:Spt:27307.0,25971.2,25975.0] || xuntil6(s6)*+ -> . % 76.01/76.19 27309[30:Spt:27307.0,25971.0,25971.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.01/76.19 27310[30:Res:53.1,27309.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.01/76.19 27312[31:Spt:27310.0] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.19 27314[31:Res:27312.0,61.1] always3(s6) || -> . % 76.01/76.19 27315[31:SSi:27314.0,695.0,25970.0] || -> . % 76.01/76.19 27316[31:Spt:27315.0,27310.0,27312.0] || m_main_v_state(s6,c_busy)* -> . % 76.01/76.19 27317[31:Spt:27315.0,27310.1] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.19 27321[31:Res:27317.0,61.1] always3(s7) || -> . % 76.01/76.19 27322[31:SSi:27321.0,696.0] || -> . % 76.01/76.19 27323[29:Spt:27322.0,25968.2,25969.0] || xuntil6(s5)*+ -> . % 76.01/76.19 27324[29:Spt:27322.0,25968.0,25968.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.01/76.19 27325[29:Res:53.1,27324.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.01/76.19 27327[30:Spt:27325.0] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.19 27329[30:Res:27327.0,61.1] always3(s5) || -> . % 76.01/76.19 27330[30:SSi:27329.0,694.0,25967.0] || -> . % 76.01/76.19 27331[30:Spt:27330.0,27325.0,27327.0] || m_main_v_state(s5,c_busy)* -> . % 76.01/76.19 27332[30:Spt:27330.0,27325.1] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.19 27336[30:Res:27332.0,61.1] always3(s6) || -> . % 76.01/76.19 27337[30:SSi:27336.0,695.0] || -> . % 76.01/76.19 27338[28:Spt:27337.0,25962.2,25966.0] || xuntil6(s4)*+ -> . % 76.01/76.19 27339[28:Spt:27337.0,25962.0,25962.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.01/76.19 27340[28:Res:53.1,27339.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.01/76.19 27345[29:Spt:27340.0] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.19 27347[29:Res:27345.0,61.1] always3(s4) || -> . % 76.01/76.19 27348[29:SSi:27347.0,693.0,25961.0] || -> . % 76.01/76.19 27349[29:Spt:27348.0,27340.0,27345.0] || m_main_v_state(s4,c_busy)* -> . % 76.01/76.19 27350[29:Spt:27348.0,27340.1] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.19 27354[29:Res:27350.0,61.1] always3(s5) || -> . % 76.01/76.19 27355[29:SSi:27354.0,694.0] || -> . % 76.01/76.19 27356[27:Spt:27355.0,25959.2,25960.0] || xuntil6(s3)*+ -> . % 76.01/76.19 27357[27:Spt:27355.0,25959.0,25959.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.01/76.19 27358[27:Res:53.1,27357.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.01/76.19 27360[28:Spt:27358.0] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.19 27362[28:Res:27360.0,61.1] always3(s3) || -> . % 76.01/76.19 27363[28:SSi:27362.0,692.0,25958.0] || -> . % 76.01/76.19 27364[28:Spt:27363.0,27358.0,27360.0] || m_main_v_state(s3,c_busy)* -> . % 76.01/76.19 27365[28:Spt:27363.0,27358.1] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.19 27369[28:Res:27365.0,61.1] always3(s4) || -> . % 76.01/76.19 27370[28:SSi:27369.0,693.0] || -> . % 76.01/76.19 27371[26:Spt:27370.0,25953.2,25957.0] || xuntil6(s2)*+ -> . % 76.01/76.19 27372[26:Spt:27370.0,25953.0,25953.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.01/76.19 27373[26:Res:53.1,27372.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.01/76.19 27375[27:Spt:27373.0] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.19 27377[27:Res:27375.0,61.1] always3(s2) || -> . % 76.01/76.19 27378[27:SSi:27377.0,691.0,25952.0] || -> . % 76.01/76.19 27379[27:Spt:27378.0,27373.0,27375.0] || m_main_v_state(s2,c_busy)* -> . % 76.01/76.19 27380[27:Spt:27378.0,27373.1] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.19 27384[27:Res:27380.0,61.1] always3(s3) || -> . % 76.01/76.19 27385[27:SSi:27384.0,692.0] || -> . % 76.01/76.19 27386[25:Spt:27385.0,25947.2,25951.0] || xuntil6(s1)*+ -> . % 76.01/76.19 27387[25:Spt:27385.0,25947.0,25947.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.01/76.19 27388[25:Res:53.1,27387.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.01/76.19 27393[26:Spt:27388.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.19 27395[26:Res:27393.0,61.1] always3(s1) || -> . % 76.01/76.19 27396[26:SSi:27395.0,690.0,25946.0] || -> . % 76.01/76.19 27397[26:Spt:27396.0,27388.0,27393.0] || m_main_v_state(s1,c_busy)* -> . % 76.01/76.19 27398[26:Spt:27396.0,27388.1] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.19 27403[26:Res:27398.0,61.1] always3(s2) || -> . % 76.01/76.19 27404[26:SSi:27403.0,691.0] || -> . % 76.01/76.19 27405[24:Spt:27404.0,74.0,25945.0] || xuntil6(s0)*+ -> . % 76.01/76.19 27406[24:Spt:27404.0,74.1] || -> node4(s0)*. % 76.01/76.19 27407[24:MRR:758.1,27405.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.19 27409[24:Res:27407.0,61.1] always3(s1) || -> . % 76.01/76.19 27410[24:SSi:27409.0,690.0] || -> . % 76.01/76.19 27411[23:Spt:27410.0,25935.0,25939.0] || trans(s49,s28)*+ -> . % 76.01/76.19 27412[23:Spt:27410.0,25935.1,25935.2,25935.3,25935.4,25935.5,25935.6,25935.7,25935.8,25935.9,25935.10,25935.11,25935.12,25935.13,25935.14,25935.15,25935.16,25935.17,25935.18,25935.19,25935.20,25935.21,25935.22,25935.23,25935.24,25935.25,25935.26,25935.27,25935.28] || -> trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.01/76.19 27414[23:MRR:25936.0,27411.0] || -> trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.01/76.19 27415[23:MRR:25938.1,27411.0] xuntil6(s49) || -> trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.01/76.19 27416[24:Spt:27412.0] || -> trans(s49,s27)*. % 76.01/76.19 27417[24:Res:27416.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s27)*. % 76.01/76.19 27419[24:Res:27416.0,60.0] || -> node2(s49,s27)*. % 76.01/76.19 27420[24:SSi:27417.1,50.0,738.0] xuntil6(s49) || -> until2p7(s27)*. % 76.01/76.19 27421[24:Res:27419.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)*. % 76.01/76.19 27422[25:Spt:74.0] || -> xuntil6(s0)*. % 76.01/76.19 27423[25:MRR:176.0,27422.0] || -> until5(s1)*. % 76.01/76.19 27424[25:MRR:26394.0,27423.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.19 27428[26:Spt:27424.2] || -> xuntil6(s1)*. % 76.01/76.19 27429[26:MRR:175.0,27428.0] || -> until5(s2)*. % 76.01/76.19 27430[26:MRR:26390.0,27429.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.19 27431[27:Spt:27430.2] || -> xuntil6(s2)*. % 76.01/76.19 27432[27:MRR:174.0,27431.0] || -> until5(s3)*. % 76.01/76.19 27433[27:MRR:26389.0,27432.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.19 27434[28:Spt:27433.2] || -> xuntil6(s3)*. % 76.01/76.19 27435[28:MRR:173.0,27434.0] || -> until5(s4)*. % 76.01/76.19 27436[28:MRR:26382.0,27435.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.19 27437[29:Spt:27436.2] || -> xuntil6(s4)*. % 76.01/76.19 27438[29:MRR:172.0,27437.0] || -> until5(s5)*. % 76.01/76.19 27439[29:MRR:26378.0,27438.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.19 27443[30:Spt:27439.2] || -> xuntil6(s5)*. % 76.01/76.19 27444[30:MRR:171.0,27443.0] || -> until5(s6)*. % 76.01/76.19 27445[30:MRR:26374.0,27444.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.19 27446[31:Spt:27445.2] || -> xuntil6(s6)*. % 76.01/76.19 27447[31:MRR:170.0,27446.0] || -> until5(s7)*. % 76.01/76.19 27448[31:MRR:26370.0,27447.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.19 27452[32:Spt:27448.2] || -> xuntil6(s7)*. % 76.01/76.19 27453[32:MRR:169.0,27452.0] || -> until5(s8)*. % 76.01/76.19 27454[32:MRR:26369.0,27453.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.19 27455[33:Spt:27454.2] || -> xuntil6(s8)*. % 76.01/76.19 27456[33:MRR:168.0,27455.0] || -> until5(s9)*. % 76.01/76.19 27457[33:MRR:26362.0,27456.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.19 27461[34:Spt:27457.2] || -> xuntil6(s9)*. % 76.01/76.19 27462[34:MRR:167.0,27461.0] || -> until5(s10)*. % 76.01/76.19 27463[34:MRR:26358.0,27462.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.19 27464[35:Spt:27463.2] || -> xuntil6(s10)*. % 76.01/76.19 27465[35:MRR:166.0,27464.0] || -> until5(s11)*. % 76.01/76.19 27466[35:MRR:26354.0,27465.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.19 27470[36:Spt:27466.2] || -> xuntil6(s11)*. % 76.01/76.19 27471[36:MRR:165.0,27470.0] || -> until5(s12)*. % 76.01/76.19 27472[36:MRR:26350.0,27471.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.19 27473[37:Spt:27472.2] || -> xuntil6(s12)*. % 76.01/76.19 27474[37:MRR:164.0,27473.0] || -> until5(s13)*. % 76.01/76.19 27475[37:MRR:26349.0,27474.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.19 27479[38:Spt:27475.2] || -> xuntil6(s13)*. % 76.01/76.19 27480[38:MRR:163.0,27479.0] || -> until5(s14)*. % 76.01/76.19 27481[38:MRR:26342.0,27480.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.19 27482[39:Spt:27481.2] || -> xuntil6(s14)*. % 76.01/76.19 27483[39:MRR:162.0,27482.0] || -> until5(s15)*. % 76.01/76.19 27484[39:MRR:26338.0,27483.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.19 27488[40:Spt:27484.2] || -> xuntil6(s15)*. % 76.01/76.19 27489[40:MRR:161.0,27488.0] || -> until5(s16)*. % 76.01/76.19 27490[40:MRR:26334.0,27489.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.19 27491[41:Spt:27490.2] || -> xuntil6(s16)*. % 76.01/76.19 27492[41:MRR:160.0,27491.0] || -> until5(s17)*. % 76.01/76.19 27493[41:MRR:26330.0,27492.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.19 27497[42:Spt:27493.2] || -> xuntil6(s17)*. % 76.01/76.19 27498[42:MRR:159.0,27497.0] || -> until5(s18)*. % 76.01/76.19 27499[42:MRR:26329.0,27498.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.19 27500[43:Spt:27499.2] || -> xuntil6(s18)*. % 76.01/76.19 27501[43:MRR:158.0,27500.0] || -> until5(s19)*. % 76.01/76.19 27502[43:MRR:26322.0,27501.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.19 27506[44:Spt:27502.2] || -> xuntil6(s19)*. % 76.01/76.19 27507[44:MRR:157.0,27506.0] || -> until5(s20)*. % 76.01/76.19 27508[44:MRR:26318.0,27507.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.19 27509[45:Spt:27508.2] || -> xuntil6(s20)*. % 76.01/76.19 27510[45:MRR:156.0,27509.0] || -> until5(s21)*. % 76.01/76.19 27511[45:MRR:26314.0,27510.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.19 27515[46:Spt:27511.2] || -> xuntil6(s21)*. % 76.01/76.19 27516[46:MRR:155.0,27515.0] || -> until5(s22)*. % 76.01/76.19 27517[46:MRR:26310.0,27516.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.19 27518[47:Spt:27517.2] || -> xuntil6(s22)*. % 76.01/76.19 27519[47:MRR:154.0,27518.0] || -> until5(s23)*. % 76.01/76.19 27520[47:MRR:26309.0,27519.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.19 27524[48:Spt:27520.2] || -> xuntil6(s23)*. % 76.01/76.19 27525[48:MRR:153.0,27524.0] || -> until5(s24)*. % 76.01/76.19 27526[48:MRR:26305.0,27525.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.19 27527[49:Spt:27526.2] || -> xuntil6(s24)*. % 76.01/76.19 27528[49:MRR:152.0,27527.0] || -> until5(s25)*. % 76.01/76.19 27529[49:MRR:26304.0,27528.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.19 27533[50:Spt:27529.2] || -> xuntil6(s25)*. % 76.01/76.19 27534[50:MRR:151.0,27533.0] || -> until5(s26)*. % 76.01/76.19 27535[50:MRR:26303.0,27534.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.19 27536[51:Spt:27535.2] || -> xuntil6(s26)*. % 76.01/76.19 27537[51:MRR:150.0,27536.0] || -> until5(s27)*. % 76.01/76.19 27538[51:MRR:26302.0,27537.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.19 27542[52:Spt:27538.2] || -> xuntil6(s27)*. % 76.01/76.19 27543[52:MRR:149.0,27542.0] || -> until5(s28)*. % 76.01/76.19 27544[52:MRR:24783.0,27543.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.19 27545[53:Spt:27544.2] || -> xuntil6(s28)*. % 76.01/76.19 27546[53:MRR:148.0,27545.0] || -> until5(s29)*. % 76.01/76.19 27547[53:MRR:26398.0,27546.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.19 27551[54:Spt:27547.1] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.19 27553[54:Res:27551.0,61.1] always3(s30) || -> . % 76.01/76.19 27554[54:SSi:27553.0,719.0] || -> . % 76.01/76.19 27555[54:Spt:27554.0,27547.1,27551.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.01/76.19 27556[54:Spt:27554.0,27547.0,27547.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 76.01/76.19 27558[54:MRR:831.2,27555.0] node4(s29) || m_main_v_state(s29,c_ready)* -> . % 76.01/76.19 27559[54:Res:53.1,27556.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 76.01/76.19 27561[55:Spt:27559.1] || -> xuntil6(s29)*. % 76.01/76.19 27562[55:MRR:147.0,27561.0] || -> until5(s30)*. % 76.01/76.19 27563[55:MRR:24777.0,27562.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.19 27568[56:Spt:27563.2] || -> xuntil6(s30)*. % 76.01/76.19 27569[56:MRR:146.0,27568.0] || -> until5(s31)*. % 76.01/76.19 27570[56:MRR:26402.0,27569.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.19 27571[57:Spt:27570.1] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.19 27573[57:Res:27571.0,61.1] always3(s32) || -> . % 76.01/76.19 27574[57:SSi:27573.0,721.0] || -> . % 76.01/76.19 27575[57:Spt:27574.0,27570.1,27571.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.01/76.19 27576[57:Spt:27574.0,27570.0,27570.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.01/76.19 27578[57:MRR:825.2,27575.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.01/76.19 27579[57:Res:53.1,27576.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.01/76.19 27581[58:Spt:27579.1] || -> xuntil6(s31)*. % 76.01/76.19 27582[58:MRR:145.0,27581.0] || -> until5(s32)*. % 76.01/76.19 27583[58:MRR:19324.0,27582.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.19 27591[59:Spt:27583.2] || -> xuntil6(s32)*. % 76.01/76.19 27592[59:MRR:144.0,27591.0] || -> until5(s33)*. % 76.01/76.19 27593[59:MRR:26409.0,27592.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.19 27594[60:Spt:27593.1] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.19 27596[60:Res:27594.0,61.1] always3(s34) || -> . % 76.01/76.19 27597[60:SSi:27596.0,723.0] || -> . % 76.01/76.19 27598[60:Spt:27597.0,27593.1,27594.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.01/76.19 27599[60:Spt:27597.0,27593.0,27593.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.01/76.19 27601[60:MRR:819.2,27598.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.01/76.19 27602[60:Res:53.1,27599.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.01/76.19 27607[61:Spt:27602.1] || -> xuntil6(s33)*. % 76.01/76.19 27608[61:MRR:143.0,27607.0] || -> until5(s34)*. % 76.01/76.19 27609[61:MRR:16857.0,27608.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.19 27611[62:Spt:27609.2] || -> xuntil6(s34)*. % 76.01/76.19 27612[62:MRR:142.0,27611.0] || -> until5(s35)*. % 76.01/76.19 27613[62:MRR:26410.0,27612.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.19 27614[63:Spt:27613.1] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.19 27616[63:Res:27614.0,61.1] always3(s36) || -> . % 76.01/76.19 27617[63:SSi:27616.0,725.0] || -> . % 76.01/76.19 27618[63:Spt:27617.0,27613.1,27614.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.01/76.19 27619[63:Spt:27617.0,27613.0,27613.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.01/76.19 27621[63:MRR:813.2,27618.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.01/76.19 27622[63:Res:53.1,27619.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.01/76.19 27624[64:Spt:27622.1] || -> xuntil6(s35)*. % 76.01/76.19 27625[64:MRR:141.0,27624.0] || -> until5(s36)*. % 76.01/76.19 27626[64:MRR:16858.0,27625.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.19 27631[65:Spt:27626.2] || -> xuntil6(s36)*. % 76.01/76.19 27632[65:MRR:140.0,27631.0] || -> until5(s37)*. % 76.01/76.19 27633[65:MRR:26414.0,27632.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.19 27634[66:Spt:27633.1] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.19 27636[66:Res:27634.0,61.1] always3(s38) || -> . % 76.01/76.19 27637[66:SSi:27636.0,727.0] || -> . % 76.01/76.19 27638[66:Spt:27637.0,27633.1,27634.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.01/76.19 27639[66:Spt:27637.0,27633.0,27633.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.01/76.19 27641[66:MRR:807.2,27638.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.01/76.19 27642[66:Res:53.1,27639.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.01/76.19 27644[67:Spt:27642.1] || -> xuntil6(s37)*. % 76.01/76.19 27645[67:MRR:139.0,27644.0] || -> until5(s38)*. % 76.01/76.19 27646[67:MRR:16862.0,27645.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.19 27654[68:Spt:27646.2] || -> xuntil6(s38)*. % 76.01/76.19 27655[68:MRR:138.0,27654.0] || -> until5(s39)*. % 76.01/76.19 27656[68:MRR:26418.0,27655.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.19 27657[69:Spt:27656.1] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.19 27659[69:Res:27657.0,61.1] always3(s40) || -> . % 76.01/76.19 27660[69:SSi:27659.0,729.0] || -> . % 76.01/76.19 27661[69:Spt:27660.0,27656.1,27657.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.01/76.19 27662[69:Spt:27660.0,27656.0,27656.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.01/76.19 27664[69:MRR:801.2,27661.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.01/76.19 27665[69:Res:53.1,27662.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.01/76.19 27670[70:Spt:27665.1] || -> xuntil6(s39)*. % 76.01/76.19 27671[70:MRR:137.0,27670.0] || -> until5(s40)*. % 76.01/76.19 27672[70:MRR:16866.0,27671.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.01/76.19 27674[71:Spt:27672.2] || -> xuntil6(s40)*. % 76.01/76.19 27675[71:MRR:136.0,27674.0] || -> until5(s41)*. % 76.01/76.19 27676[71:MRR:26422.0,27675.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.19 27677[72:Spt:27676.1] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.19 27679[72:Res:27677.0,61.1] always3(s42) || -> . % 76.01/76.19 27680[72:SSi:27679.0,731.0] || -> . % 76.01/76.19 27681[72:Spt:27680.0,27676.1,27677.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.01/76.19 27682[72:Spt:27680.0,27676.0,27676.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.01/76.19 27684[72:MRR:795.2,27681.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.01/76.19 27685[72:Res:53.1,27682.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.01/76.19 27687[73:Spt:27685.1] || -> xuntil6(s41)*. % 76.01/76.19 27688[73:MRR:135.0,27687.0] || -> until5(s42)*. % 76.01/76.19 27689[73:MRR:16870.0,27688.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.01/76.19 27694[74:Spt:27689.2] || -> xuntil6(s42)*. % 76.01/76.19 27695[74:MRR:134.0,27694.0] || -> until5(s43)*. % 76.01/76.19 27696[74:MRR:26429.0,27695.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.19 27697[75:Spt:27696.1] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.19 27699[75:Res:27697.0,61.1] always3(s44) || -> . % 76.01/76.19 27700[75:SSi:27699.0,733.0] || -> . % 76.01/76.19 27701[75:Spt:27700.0,27696.1,27697.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.01/76.19 27702[75:Spt:27700.0,27696.0,27696.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.01/76.19 27704[75:MRR:789.2,27701.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.01/76.19 27705[75:Res:53.1,27702.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.01/76.19 27707[76:Spt:27705.1] || -> xuntil6(s43)*. % 76.01/76.19 27708[76:MRR:133.0,27707.0] || -> until5(s44)*. % 76.01/76.19 27709[76:MRR:16877.0,27708.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.01/76.19 27717[77:Spt:27709.2] || -> xuntil6(s44)*. % 76.01/76.19 27718[77:MRR:132.0,27717.0] || -> until5(s45)*. % 76.01/76.19 27719[77:MRR:26430.0,27718.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.19 27720[78:Spt:27719.1] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.19 27722[78:Res:27720.0,61.1] always3(s46) || -> . % 76.01/76.19 27723[78:SSi:27722.0,735.0] || -> . % 76.01/76.19 27724[78:Spt:27723.0,27719.1,27720.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.01/76.19 27725[78:Spt:27723.0,27719.0,27719.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.01/76.19 27727[78:MRR:783.2,27724.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.01/76.19 27728[78:Res:53.1,27725.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.01/76.19 27733[79:Spt:27728.1] || -> xuntil6(s45)*. % 76.01/76.19 27734[79:MRR:131.0,27733.0] || -> until5(s46)*. % 76.01/76.19 27735[79:MRR:16878.0,27734.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.01/76.19 27737[80:Spt:27735.2] || -> xuntil6(s46)*. % 76.01/76.19 27738[80:MRR:130.0,27737.0] || -> until5(s47)*. % 76.01/76.19 27739[80:MRR:26434.0,27738.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.19 27740[81:Spt:27739.1] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.19 27742[81:Res:27740.0,61.1] always3(s48) || -> . % 76.01/76.19 27743[81:SSi:27742.0,737.0] || -> . % 76.01/76.19 27744[81:Spt:27743.0,27739.1,27740.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.01/76.19 27745[81:Spt:27743.0,27739.0,27739.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.01/76.19 27747[81:MRR:777.2,27744.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.01/76.19 27748[81:Res:53.1,27745.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.01/76.19 27750[82:Spt:27748.1] || -> xuntil6(s47)*. % 76.01/76.19 27751[82:MRR:129.0,27750.0] || -> until5(s48)*. % 76.01/76.19 27752[82:MRR:16882.0,27751.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.01/76.19 27757[83:Spt:27752.2] || -> xuntil6(s48)*. % 76.01/76.19 27758[83:MRR:128.0,27757.0] || -> until5(s49)*. % 76.01/76.19 27759[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.19 27763[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.19 27764[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.19 27765[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.19 27772[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.19 27773[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.19 27777[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.19 27781[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.19 27785[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.19 27792[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.19 27793[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.19 27797[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.19 27801[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.19 27805[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.19 27812[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.19 27813[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.19 27817[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.19 27821[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.19 27825[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.19 27832[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.19 27833[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.19 27837[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.19 27841[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.19 27845[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.19 27852[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.19 27853[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.19 27857[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.19 27861[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.19 27863[24:SoR:27421.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)*. % 76.01/76.19 27868[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.19 27872[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.19 27876[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.19 27883[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.19 27884[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.19 27888[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.01/76.19 27892[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.01/76.19 27896[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.01/76.19 27903[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.01/76.19 27904[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.01/76.19 27905[24:SoR:27863.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)* xuntil6(s49). % 76.01/76.19 27906[83:SSi:27905.0,50.0,738.0,27758.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s27,c_busy)* xuntil6(s49). % 76.01/76.19 27907[84:Spt:27906.1] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.19 27909[84:Res:27907.0,61.1] always3(s27) || -> . % 76.01/76.19 27910[84:SSi:27909.0,716.0,27537.0,27542.0] || -> . % 76.01/76.19 27911[84:Spt:27910.0,27906.1,27907.0] || m_main_v_state(s27,c_busy)*+ -> . % 76.01/76.19 27912[84:Spt:27910.0,27906.0,27906.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.01/76.19 27916[84:MRR:27863.2,27911.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.01/76.19 27917[84:Res:53.1,27912.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.01/76.19 27919[85:Spt:27917.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.19 27921[85:Res:27919.0,61.1] always3(s49) || -> . % 76.01/76.19 27922[85:SSi:27921.0,50.0,738.0,27758.0] || -> . % 76.01/76.19 27923[85:Spt:27922.0,27917.0,27919.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.01/76.19 27924[85:Spt:27922.0,27917.1] || -> xuntil6(s49)*. % 76.01/76.19 27925[85:MRR:27420.0,27924.0] || -> until2p7(s27)*. % 76.01/76.19 27926[85:MRR:223.0,27925.0] || -> until2p7(s28)* node4(s27). % 76.01/76.19 27928[85:MRR:774.2,27923.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.01/76.19 27929[86:Spt:27926.0] || -> until2p7(s28)*. % 76.01/76.19 27930[86:MRR:224.0,27929.0] || -> until2p7(s29)* node4(s28). % 76.01/76.19 27931[87:Spt:27930.0] || -> until2p7(s29)*. % 76.01/76.19 27932[87:MRR:225.0,27931.0] || -> until2p7(s30)* node4(s29). % 76.01/76.19 27933[88:Spt:27932.0] || -> until2p7(s30)*. % 76.01/76.19 27934[88:MRR:226.0,27933.0] || -> until2p7(s31)* node4(s30). % 76.01/76.19 27935[89:Spt:27934.0] || -> until2p7(s31)*. % 76.01/76.19 27936[89:MRR:227.0,27935.0] || -> until2p7(s32)* node4(s31). % 76.01/76.19 27937[90:Spt:27936.0] || -> until2p7(s32)*. % 76.01/76.19 27938[90:MRR:228.0,27937.0] || -> until2p7(s33)* node4(s32). % 76.01/76.19 27939[91:Spt:27938.0] || -> until2p7(s33)*. % 76.01/76.19 27940[91:MRR:229.0,27939.0] || -> until2p7(s34)* node4(s33). % 76.01/76.19 27941[92:Spt:27940.0] || -> until2p7(s34)*. % 76.01/76.19 27942[92:MRR:230.0,27941.0] || -> until2p7(s35)* node4(s34). % 76.01/76.19 27943[93:Spt:27942.0] || -> until2p7(s35)*. % 76.01/76.19 27944[93:MRR:231.0,27943.0] || -> until2p7(s36)* node4(s35). % 76.01/76.19 27945[94:Spt:27944.0] || -> until2p7(s36)*. % 76.01/76.19 27946[94:MRR:232.0,27945.0] || -> until2p7(s37)* node4(s36). % 76.01/76.19 27947[95:Spt:27946.0] || -> until2p7(s37)*. % 76.01/76.19 27948[95:MRR:235.0,27947.0] || -> until2p7(s38)* node4(s37). % 76.01/76.19 27949[96:Spt:27948.0] || -> until2p7(s38)*. % 76.01/76.19 27950[96:MRR:236.0,27949.0] || -> until2p7(s39)* node4(s38). % 76.01/76.19 27951[97:Spt:27950.0] || -> until2p7(s39)*. % 76.01/76.19 27952[97:MRR:237.0,27951.0] || -> until2p7(s40)* node4(s39). % 76.01/76.19 27953[98:Spt:27952.0] || -> until2p7(s40)*. % 76.01/76.19 27954[98:MRR:238.0,27953.0] || -> until2p7(s41)* node4(s40). % 76.01/76.19 27955[99:Spt:27954.0] || -> until2p7(s41)*. % 76.01/76.19 27956[99:MRR:239.0,27955.0] || -> until2p7(s42)* node4(s41). % 76.01/76.19 27957[100:Spt:27956.0] || -> until2p7(s42)*. % 76.01/76.19 27958[100:MRR:240.0,27957.0] || -> until2p7(s43)* node4(s42). % 76.01/76.19 27959[101:Spt:27958.0] || -> until2p7(s43)*. % 76.01/76.19 27960[101:MRR:241.0,27959.0] || -> until2p7(s44)* node4(s43). % 76.01/76.19 27961[102:Spt:27960.0] || -> until2p7(s44)*. % 76.01/76.19 27962[102:MRR:539.0,27961.0] || -> until2p7(s45)* node4(s44). % 76.01/76.19 27963[103:Spt:27962.0] || -> until2p7(s45)*. % 76.01/76.19 27964[103:MRR:544.0,27963.0] || -> until2p7(s46)* node4(s45). % 76.01/76.19 27965[104:Spt:27964.0] || -> until2p7(s46)*. % 76.01/76.19 27966[104:MRR:549.0,27965.0] || -> until2p7(s47)* node4(s46). % 76.01/76.19 27967[105:Spt:27966.0] || -> until2p7(s47)*. % 76.01/76.19 27968[105:MRR:554.0,27967.0] || -> until2p7(s48)* node4(s47). % 76.01/76.19 27969[106:Spt:27968.0] || -> until2p7(s48)*. % 76.01/76.19 27970[106:MRR:559.0,27969.0] || -> until2p7(s49)* node4(s48). % 76.01/76.19 27971[107:Spt:27970.0] || -> until2p7(s49)*. % 76.01/76.19 27972[107:MRR:194.0,27971.0] || -> node4(s49)*. % 76.01/76.19 27973[107:MRR:27916.0,27972.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.01/76.19 27974[107:Res:53.1,27973.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.19 27976[107:MRR:27974.0,27923.0] || -> . % 76.01/76.19 27977[107:Spt:27976.0,27970.0,27971.0] || until2p7(s49)*+ -> . % 76.01/76.19 27978[107:Spt:27976.0,27970.1] || -> node4(s48)*. % 76.01/76.19 27979[107:MRR:27928.0,27978.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.01/76.19 27982[107:Res:53.1,27979.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.19 27984[107:MRR:27982.0,27744.0] || -> . % 76.01/76.19 27985[106:Spt:27984.0,27968.0,27969.0] || until2p7(s48)*+ -> . % 76.01/76.19 27986[106:Spt:27984.0,27968.1] || -> node4(s47)*. % 76.01/76.19 27987[106:MRR:27747.0,27986.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.01/76.19 27990[106:Res:53.1,27987.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.19 27994[106:Res:27990.0,61.1] always3(s47) || -> . % 76.01/76.19 27995[106:SSi:27994.0,736.0,27738.0,27750.0,27967.0,27986.0] || -> . % 76.01/76.19 27996[105:Spt:27995.0,27966.0,27967.0] || until2p7(s47)*+ -> . % 76.01/76.19 27997[105:Spt:27995.0,27966.1] || -> node4(s46)*. % 76.01/76.19 27999[105:MRR:780.0,27997.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.01/76.19 28021[105:Res:53.1,27999.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.01/76.19 28023[105:MRR:28021.0,27724.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.19 28025[105:Res:28023.0,61.1] always3(s47) || -> . % 76.01/76.19 28026[105:SSi:28025.0,736.0,27738.0,27750.0] || -> . % 76.01/76.19 28027[104:Spt:28026.0,27964.0,27965.0] || until2p7(s46)*+ -> . % 76.01/76.19 28028[104:Spt:28026.0,27964.1] || -> node4(s45)*. % 76.01/76.19 28029[104:MRR:27727.0,28028.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.01/76.19 28033[104:Res:53.1,28029.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.19 28036[104:Res:28033.0,61.1] always3(s45) || -> . % 76.01/76.19 28037[104:SSi:28036.0,734.0,27718.0,27733.0,27963.0,28028.0] || -> . % 76.01/76.19 28038[103:Spt:28037.0,27962.0,27963.0] || until2p7(s45)*+ -> . % 76.01/76.19 28039[103:Spt:28037.0,27962.1] || -> node4(s44)*. % 76.01/76.19 28041[103:MRR:786.0,28039.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.01/76.19 28052[103:Res:53.1,28041.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.01/76.19 28054[103:MRR:28052.0,27701.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.19 28056[103:Res:28054.0,61.1] always3(s45) || -> . % 76.01/76.19 28057[103:SSi:28056.0,734.0,27718.0,27733.0] || -> . % 76.01/76.19 28058[102:Spt:28057.0,27960.0,27961.0] || until2p7(s44)*+ -> . % 76.01/76.19 28059[102:Spt:28057.0,27960.1] || -> node4(s43)*. % 76.01/76.19 28060[102:MRR:27704.0,28059.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.01/76.19 28063[102:Res:53.1,28060.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.19 28066[102:Res:28063.0,61.1] always3(s43) || -> . % 76.01/76.19 28067[102:SSi:28066.0,732.0,27695.0,27707.0,27959.0,28059.0] || -> . % 76.01/76.19 28068[101:Spt:28067.0,27958.0,27959.0] || until2p7(s43)*+ -> . % 76.01/76.19 28069[101:Spt:28067.0,27958.1] || -> node4(s42)*. % 76.01/76.19 28071[101:MRR:792.0,28069.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.01/76.19 28083[101:Res:53.1,28071.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.01/76.19 28085[101:MRR:28083.0,27681.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.19 28087[101:Res:28085.0,61.1] always3(s43) || -> . % 76.01/76.19 28088[101:SSi:28087.0,732.0,27695.0,27707.0] || -> . % 76.01/76.19 28089[100:Spt:28088.0,27956.0,27957.0] || until2p7(s42)*+ -> . % 76.01/76.19 28090[100:Spt:28088.0,27956.1] || -> node4(s41)*. % 76.01/76.19 28091[100:MRR:27684.0,28090.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.01/76.19 28094[100:Res:53.1,28091.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.19 28097[100:Res:28094.0,61.1] always3(s41) || -> . % 76.01/76.19 28098[100:SSi:28097.0,730.0,27675.0,27687.0,27955.0,28090.0] || -> . % 76.01/76.19 28099[99:Spt:28098.0,27954.0,27955.0] || until2p7(s41)*+ -> . % 76.01/76.19 28100[99:Spt:28098.0,27954.1] || -> node4(s40)*. % 76.01/76.19 28102[99:MRR:798.0,28100.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.01/76.19 28114[99:Res:53.1,28102.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.01/76.19 28116[99:MRR:28114.0,27661.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.19 28121[99:Res:28116.0,61.1] always3(s41) || -> . % 76.01/76.19 28122[99:SSi:28121.0,730.0,27675.0,27687.0] || -> . % 76.01/76.19 28123[98:Spt:28122.0,27952.0,27953.0] || until2p7(s40)*+ -> . % 76.01/76.19 28124[98:Spt:28122.0,27952.1] || -> node4(s39)*. % 76.01/76.19 28125[98:MRR:27664.0,28124.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.01/76.19 28128[98:Res:53.1,28125.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.19 28132[98:Res:28128.0,61.1] always3(s39) || -> . % 76.01/76.19 28133[98:SSi:28132.0,728.0,27655.0,27670.0,27951.0,28124.0] || -> . % 76.01/76.19 28134[97:Spt:28133.0,27950.0,27951.0] || until2p7(s39)*+ -> . % 76.01/76.19 28135[97:Spt:28133.0,27950.1] || -> node4(s38)*. % 76.01/76.19 28137[97:MRR:804.0,28135.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.01/76.19 28148[97:Res:53.1,28137.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.01/76.19 28150[97:MRR:28148.0,27638.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.19 28152[97:Res:28150.0,61.1] always3(s39) || -> . % 76.01/76.19 28153[97:SSi:28152.0,728.0,27655.0,27670.0] || -> . % 76.01/76.19 28154[96:Spt:28153.0,27948.0,27949.0] || until2p7(s38)*+ -> . % 76.01/76.19 28155[96:Spt:28153.0,27948.1] || -> node4(s37)*. % 76.01/76.19 28156[96:MRR:27641.0,28155.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.01/76.19 28160[96:Res:53.1,28156.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.19 28163[96:Res:28160.0,61.1] always3(s37) || -> . % 76.01/76.19 28164[96:SSi:28163.0,726.0,27632.0,27644.0,27947.0,28155.0] || -> . % 76.01/76.19 28165[95:Spt:28164.0,27946.0,27947.0] || until2p7(s37)*+ -> . % 76.01/76.19 28166[95:Spt:28164.0,27946.1] || -> node4(s36)*. % 76.01/76.19 28168[95:MRR:810.0,28166.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.01/76.19 28179[95:Res:53.1,28168.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.01/76.19 28181[95:MRR:28179.0,27618.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.19 28183[95:Res:28181.0,61.1] always3(s37) || -> . % 76.01/76.19 28184[95:SSi:28183.0,726.0,27632.0,27644.0] || -> . % 76.01/76.19 28185[94:Spt:28184.0,27944.0,27945.0] || until2p7(s36)*+ -> . % 76.01/76.19 28186[94:Spt:28184.0,27944.1] || -> node4(s35)*. % 76.01/76.19 28187[94:MRR:27621.0,28186.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.01/76.19 28190[94:Res:53.1,28187.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.19 28193[94:Res:28190.0,61.1] always3(s35) || -> . % 76.01/76.19 28194[94:SSi:28193.0,724.0,27612.0,27624.0,27943.0,28186.0] || -> . % 76.01/76.19 28195[93:Spt:28194.0,27942.0,27943.0] || until2p7(s35)*+ -> . % 76.01/76.19 28196[93:Spt:28194.0,27942.1] || -> node4(s34)*. % 76.01/76.19 28198[93:MRR:816.0,28196.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.01/76.19 28210[93:Res:53.1,28198.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.01/76.19 28212[93:MRR:28210.0,27598.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.19 28214[93:Res:28212.0,61.1] always3(s35) || -> . % 76.01/76.19 28215[93:SSi:28214.0,724.0,27612.0,27624.0] || -> . % 76.01/76.19 28216[92:Spt:28215.0,27940.0,27941.0] || until2p7(s34)*+ -> . % 76.01/76.19 28217[92:Spt:28215.0,27940.1] || -> node4(s33)*. % 76.01/76.19 28218[92:MRR:27601.0,28217.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.01/76.19 28221[92:Res:53.1,28218.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.19 28224[92:Res:28221.0,61.1] always3(s33) || -> . % 76.01/76.19 28225[92:SSi:28224.0,722.0,27592.0,27607.0,27939.0,28217.0] || -> . % 76.01/76.19 28226[91:Spt:28225.0,27938.0,27939.0] || until2p7(s33)*+ -> . % 76.01/76.19 28227[91:Spt:28225.0,27938.1] || -> node4(s32)*. % 76.01/76.19 28229[91:MRR:822.0,28227.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.01/76.19 28241[91:Res:53.1,28229.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.01/76.19 28243[91:MRR:28241.0,27575.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.19 28248[91:Res:28243.0,61.1] always3(s33) || -> . % 76.01/76.19 28249[91:SSi:28248.0,722.0,27592.0,27607.0] || -> . % 76.01/76.19 28250[90:Spt:28249.0,27936.0,27937.0] || until2p7(s32)*+ -> . % 76.01/76.19 28251[90:Spt:28249.0,27936.1] || -> node4(s31)*. % 76.01/76.19 28252[90:MRR:27578.0,28251.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.01/76.19 28255[90:Res:53.1,28252.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.19 28259[90:Res:28255.0,61.1] always3(s31) || -> . % 76.01/76.19 28260[90:SSi:28259.0,720.0,27569.0,27581.0,27935.0,28251.0] || -> . % 76.01/76.19 28261[89:Spt:28260.0,27934.0,27935.0] || until2p7(s31)*+ -> . % 76.01/76.19 28262[89:Spt:28260.0,27934.1] || -> node4(s30)*. % 76.01/76.19 28264[89:MRR:828.0,28262.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.01/76.19 28275[89:Res:53.1,28264.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.01/76.19 28277[89:MRR:28275.0,27555.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.19 28279[89:Res:28277.0,61.1] always3(s31) || -> . % 76.01/76.19 28280[89:SSi:28279.0,720.0,27569.0,27581.0] || -> . % 76.01/76.19 28281[88:Spt:28280.0,27932.0,27933.0] || until2p7(s30)*+ -> . % 76.01/76.19 28282[88:Spt:28280.0,27932.1] || -> node4(s29)*. % 76.01/76.19 28283[88:MRR:27558.0,28282.0] || m_main_v_state(s29,c_ready)*+ -> . % 76.01/76.19 28287[88:Res:53.1,28283.0] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.19 28290[88:Res:28287.0,61.1] always3(s29) || -> . % 76.01/76.19 28291[88:SSi:28290.0,718.0,27546.0,27561.0,27931.0,28282.0] || -> . % 76.01/76.19 28292[87:Spt:28291.0,27930.0,27931.0] || until2p7(s29)*+ -> . % 76.01/76.19 28293[87:Spt:28291.0,27930.1] || -> node4(s28)*. % 76.01/76.19 28295[87:MRR:834.0,28293.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.01/76.19 28306[87:Res:53.1,28295.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.01/76.19 28308[88:Spt:28306.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 28310[88:Res:28308.0,61.1] always3(s28) || -> . % 76.01/76.19 28311[88:SSi:28310.0,717.0,27543.0,27545.0,27929.0,28293.0] || -> . % 76.01/76.19 28312[88:Spt:28311.0,28306.0,28308.0] || m_main_v_state(s28,c_busy)* -> . % 76.01/76.19 28313[88:Spt:28311.0,28306.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.19 28317[88:Res:28313.0,61.1] always3(s29) || -> . % 76.01/76.19 28318[88:SSi:28317.0,718.0,27546.0,27561.0] || -> . % 76.01/76.19 28319[86:Spt:28318.0,27926.0,27929.0] || until2p7(s28)*+ -> . % 76.01/76.19 28320[86:Spt:28318.0,27926.1] || -> node4(s27)*. % 76.01/76.19 28322[86:MRR:837.0,28320.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.01/76.19 28332[86:Res:53.1,28322.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.01/76.19 28334[86:MRR:28332.0,27911.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 28336[86:Res:28334.0,61.1] always3(s28) || -> . % 76.01/76.19 28337[86:SSi:28336.0,717.0,27543.0,27545.0] || -> . % 76.01/76.19 28338[83:Spt:28337.0,27752.2,27757.0] || xuntil6(s48)*+ -> . % 76.01/76.19 28339[83:Spt:28337.0,27752.0,27752.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.01/76.19 28340[83:Res:53.1,28339.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.01/76.19 28342[83:MRR:28340.0,27744.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.19 28344[83:Res:28342.0,61.1] always3(s49) || -> . % 76.01/76.19 28345[83:SSi:28344.0,50.0,738.0] || -> . % 76.01/76.19 28346[82:Spt:28345.0,27748.1,27750.0] || xuntil6(s47)* -> . % 76.01/76.19 28347[82:Spt:28345.0,27748.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.19 28350[82:Res:28347.0,61.1] always3(s47) || -> . % 76.01/76.19 28351[82:SSi:28350.0,736.0,27738.0] || -> . % 76.01/76.19 28352[80:Spt:28351.0,27735.2,27737.0] || xuntil6(s46)*+ -> . % 76.01/76.19 28353[80:Spt:28351.0,27735.0,27735.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.01/76.19 28354[80:Res:53.1,28353.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.01/76.19 28356[80:MRR:28354.0,27724.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.19 28358[80:Res:28356.0,61.1] always3(s47) || -> . % 76.01/76.19 28359[80:SSi:28358.0,736.0] || -> . % 76.01/76.19 28360[79:Spt:28359.0,27728.1,27733.0] || xuntil6(s45)* -> . % 76.01/76.19 28361[79:Spt:28359.0,27728.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.19 28364[79:Res:28361.0,61.1] always3(s45) || -> . % 76.01/76.19 28365[79:SSi:28364.0,734.0,27718.0] || -> . % 76.01/76.19 28366[77:Spt:28365.0,27709.2,27717.0] || xuntil6(s44)*+ -> . % 76.01/76.19 28367[77:Spt:28365.0,27709.0,27709.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.01/76.19 28368[77:Res:53.1,28367.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.01/76.19 28370[77:MRR:28368.0,27701.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.19 28372[77:Res:28370.0,61.1] always3(s45) || -> . % 76.01/76.19 28373[77:SSi:28372.0,734.0] || -> . % 76.01/76.19 28374[76:Spt:28373.0,27705.1,27707.0] || xuntil6(s43)* -> . % 76.01/76.19 28375[76:Spt:28373.0,27705.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.19 28378[76:Res:28375.0,61.1] always3(s43) || -> . % 76.01/76.19 28379[76:SSi:28378.0,732.0,27695.0] || -> . % 76.01/76.19 28380[74:Spt:28379.0,27689.2,27694.0] || xuntil6(s42)*+ -> . % 76.01/76.19 28381[74:Spt:28379.0,27689.0,27689.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.01/76.19 28382[74:Res:53.1,28381.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.01/76.19 28384[74:MRR:28382.0,27681.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.19 28387[74:Res:28384.0,61.1] always3(s43) || -> . % 76.01/76.19 28388[74:SSi:28387.0,732.0] || -> . % 76.01/76.19 28389[73:Spt:28388.0,27685.1,27687.0] || xuntil6(s41)* -> . % 76.01/76.19 28390[73:Spt:28388.0,27685.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.19 28393[73:Res:28390.0,61.1] always3(s41) || -> . % 76.01/76.19 28394[73:SSi:28393.0,730.0,27675.0] || -> . % 76.01/76.19 28395[71:Spt:28394.0,27672.2,27674.0] || xuntil6(s40)*+ -> . % 76.01/76.19 28396[71:Spt:28394.0,27672.0,27672.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.01/76.19 28397[71:Res:53.1,28396.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.01/76.19 28399[71:MRR:28397.0,27661.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.19 28401[71:Res:28399.0,61.1] always3(s41) || -> . % 76.01/76.19 28402[71:SSi:28401.0,730.0] || -> . % 76.01/76.19 28403[70:Spt:28402.0,27665.1,27670.0] || xuntil6(s39)* -> . % 76.01/76.19 28404[70:Spt:28402.0,27665.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.19 28407[70:Res:28404.0,61.1] always3(s39) || -> . % 76.01/76.19 28408[70:SSi:28407.0,728.0,27655.0] || -> . % 76.01/76.19 28409[68:Spt:28408.0,27646.2,27654.0] || xuntil6(s38)*+ -> . % 76.01/76.19 28410[68:Spt:28408.0,27646.0,27646.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.01/76.19 28411[68:Res:53.1,28410.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.01/76.19 28413[68:MRR:28411.0,27638.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.19 28416[68:Res:28413.0,61.1] always3(s39) || -> . % 76.01/76.19 28417[68:SSi:28416.0,728.0] || -> . % 76.01/76.19 28418[67:Spt:28417.0,27642.1,27644.0] || xuntil6(s37)* -> . % 76.01/76.19 28419[67:Spt:28417.0,27642.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.19 28422[67:Res:28419.0,61.1] always3(s37) || -> . % 76.01/76.19 28423[67:SSi:28422.0,726.0,27632.0] || -> . % 76.01/76.19 28424[65:Spt:28423.0,27626.2,27631.0] || xuntil6(s36)*+ -> . % 76.01/76.19 28425[65:Spt:28423.0,27626.0,27626.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.01/76.19 28426[65:Res:53.1,28425.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.01/76.19 28428[65:MRR:28426.0,27618.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.19 28430[65:Res:28428.0,61.1] always3(s37) || -> . % 76.01/76.19 28431[65:SSi:28430.0,726.0] || -> . % 76.01/76.19 28432[64:Spt:28431.0,27622.1,27624.0] || xuntil6(s35)* -> . % 76.01/76.19 28433[64:Spt:28431.0,27622.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.19 28436[64:Res:28433.0,61.1] always3(s35) || -> . % 76.01/76.19 28437[64:SSi:28436.0,724.0,27612.0] || -> . % 76.01/76.19 28438[62:Spt:28437.0,27609.2,27611.0] || xuntil6(s34)*+ -> . % 76.01/76.19 28439[62:Spt:28437.0,27609.0,27609.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.01/76.19 28440[62:Res:53.1,28439.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.01/76.19 28442[62:MRR:28440.0,27598.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.19 28444[62:Res:28442.0,61.1] always3(s35) || -> . % 76.01/76.19 28445[62:SSi:28444.0,724.0] || -> . % 76.01/76.19 28446[61:Spt:28445.0,27602.1,27607.0] || xuntil6(s33)* -> . % 76.01/76.19 28447[61:Spt:28445.0,27602.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.19 28450[61:Res:28447.0,61.1] always3(s33) || -> . % 76.01/76.19 28451[61:SSi:28450.0,722.0,27592.0] || -> . % 76.01/76.19 28452[59:Spt:28451.0,27583.2,27591.0] || xuntil6(s32)*+ -> . % 76.01/76.19 28453[59:Spt:28451.0,27583.0,27583.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.01/76.19 28454[59:Res:53.1,28453.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.01/76.19 28456[59:MRR:28454.0,27575.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.19 28458[59:Res:28456.0,61.1] always3(s33) || -> . % 76.01/76.19 28459[59:SSi:28458.0,722.0] || -> . % 76.01/76.19 28460[58:Spt:28459.0,27579.1,27581.0] || xuntil6(s31)* -> . % 76.01/76.19 28461[58:Spt:28459.0,27579.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.19 28464[58:Res:28461.0,61.1] always3(s31) || -> . % 76.01/76.19 28465[58:SSi:28464.0,720.0,27569.0] || -> . % 76.01/76.19 28466[56:Spt:28465.0,27563.2,27568.0] || xuntil6(s30)*+ -> . % 76.01/76.19 28467[56:Spt:28465.0,27563.0,27563.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.01/76.19 28468[56:Res:53.1,28467.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.01/76.19 28470[56:MRR:28468.0,27555.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.19 28472[56:Res:28470.0,61.1] always3(s31) || -> . % 76.01/76.19 28473[56:SSi:28472.0,720.0] || -> . % 76.01/76.19 28474[55:Spt:28473.0,27559.1,27561.0] || xuntil6(s29)* -> . % 76.01/76.19 28475[55:Spt:28473.0,27559.0] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.19 28478[55:Res:28475.0,61.1] always3(s29) || -> . % 76.01/76.19 28479[55:SSi:28478.0,718.0,27546.0] || -> . % 76.01/76.19 28480[53:Spt:28479.0,27544.2,27545.0] || xuntil6(s28)*+ -> . % 76.01/76.19 28481[53:Spt:28479.0,27544.0,27544.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.01/76.19 28482[53:Res:53.1,28481.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.01/76.19 28484[54:Spt:28482.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.19 28486[54:Res:28484.0,61.1] always3(s29) || -> . % 76.01/76.19 28487[54:SSi:28486.0,718.0] || -> . % 76.01/76.19 28488[54:Spt:28487.0,28482.1,28484.0] || m_main_v_state(s29,c_busy)* -> . % 76.01/76.19 28489[54:Spt:28487.0,28482.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 28492[54:Res:28489.0,61.1] always3(s28) || -> . % 76.01/76.19 28493[54:SSi:28492.0,717.0,27543.0] || -> . % 76.01/76.19 28494[52:Spt:28493.0,27538.2,27542.0] || xuntil6(s27)*+ -> . % 76.01/76.19 28495[52:Spt:28493.0,27538.0,27538.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.01/76.19 28496[52:Res:53.1,28495.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.01/76.19 28498[53:Spt:28496.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 28500[53:Res:28498.0,61.1] always3(s28) || -> . % 76.01/76.19 28501[53:SSi:28500.0,717.0] || -> . % 76.01/76.19 28502[53:Spt:28501.0,28496.1,28498.0] || m_main_v_state(s28,c_busy)* -> . % 76.01/76.19 28503[53:Spt:28501.0,28496.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.19 28506[53:Res:28503.0,61.1] always3(s27) || -> . % 76.01/76.19 28507[53:SSi:28506.0,716.0,27537.0] || -> . % 76.01/76.19 28508[51:Spt:28507.0,27535.2,27536.0] || xuntil6(s26)*+ -> . % 76.01/76.19 28509[51:Spt:28507.0,27535.0,27535.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.01/76.19 28510[51:Res:53.1,28509.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.01/76.19 28512[52:Spt:28510.0] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.19 28514[52:Res:28512.0,61.1] always3(s26) || -> . % 76.01/76.19 28515[52:SSi:28514.0,715.0,27534.0] || -> . % 76.01/76.19 28516[52:Spt:28515.0,28510.0,28512.0] || m_main_v_state(s26,c_busy)* -> . % 76.01/76.19 28517[52:Spt:28515.0,28510.1] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.19 28521[52:Res:28517.0,61.1] always3(s27) || -> . % 76.01/76.19 28522[52:SSi:28521.0,716.0] || -> . % 76.01/76.19 28523[50:Spt:28522.0,27529.2,27533.0] || xuntil6(s25)*+ -> . % 76.01/76.19 28524[50:Spt:28522.0,27529.0,27529.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.01/76.19 28525[50:Res:53.1,28524.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.01/76.19 28527[51:Spt:28525.0] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.19 28529[51:Res:28527.0,61.1] always3(s25) || -> . % 76.01/76.19 28530[51:SSi:28529.0,714.0,27528.0] || -> . % 76.01/76.19 28531[51:Spt:28530.0,28525.0,28527.0] || m_main_v_state(s25,c_busy)* -> . % 76.01/76.19 28532[51:Spt:28530.0,28525.1] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.19 28536[51:Res:28532.0,61.1] always3(s26) || -> . % 76.01/76.19 28537[51:SSi:28536.0,715.0] || -> . % 76.01/76.19 28538[49:Spt:28537.0,27526.2,27527.0] || xuntil6(s24)*+ -> . % 76.01/76.19 28539[49:Spt:28537.0,27526.0,27526.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.01/76.19 28540[49:Res:53.1,28539.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.01/76.19 28542[50:Spt:28540.0] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.19 28544[50:Res:28542.0,61.1] always3(s24) || -> . % 76.01/76.19 28545[50:SSi:28544.0,713.0,27525.0] || -> . % 76.01/76.19 28546[50:Spt:28545.0,28540.0,28542.0] || m_main_v_state(s24,c_busy)* -> . % 76.01/76.19 28547[50:Spt:28545.0,28540.1] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.19 28551[50:Res:28547.0,61.1] always3(s25) || -> . % 76.01/76.19 28552[50:SSi:28551.0,714.0] || -> . % 76.01/76.19 28553[48:Spt:28552.0,27520.2,27524.0] || xuntil6(s23)*+ -> . % 76.01/76.19 28554[48:Spt:28552.0,27520.0,27520.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.01/76.19 28555[48:Res:53.1,28554.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.01/76.19 28557[49:Spt:28555.0] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.19 28559[49:Res:28557.0,61.1] always3(s23) || -> . % 76.01/76.19 28560[49:SSi:28559.0,712.0,27519.0] || -> . % 76.01/76.19 28561[49:Spt:28560.0,28555.0,28557.0] || m_main_v_state(s23,c_busy)* -> . % 76.01/76.19 28562[49:Spt:28560.0,28555.1] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.19 28566[49:Res:28562.0,61.1] always3(s24) || -> . % 76.01/76.19 28567[49:SSi:28566.0,713.0] || -> . % 76.01/76.19 28568[47:Spt:28567.0,27517.2,27518.0] || xuntil6(s22)*+ -> . % 76.01/76.19 28569[47:Spt:28567.0,27517.0,27517.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.01/76.19 28570[47:Res:53.1,28569.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.01/76.19 28572[48:Spt:28570.0] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.19 28574[48:Res:28572.0,61.1] always3(s22) || -> . % 76.01/76.19 28575[48:SSi:28574.0,711.0,27516.0] || -> . % 76.01/76.19 28576[48:Spt:28575.0,28570.0,28572.0] || m_main_v_state(s22,c_busy)* -> . % 76.01/76.19 28577[48:Spt:28575.0,28570.1] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.19 28581[48:Res:28577.0,61.1] always3(s23) || -> . % 76.01/76.19 28582[48:SSi:28581.0,712.0] || -> . % 76.01/76.19 28583[46:Spt:28582.0,27511.2,27515.0] || xuntil6(s21)*+ -> . % 76.01/76.19 28584[46:Spt:28582.0,27511.0,27511.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.01/76.19 28585[46:Res:53.1,28584.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.01/76.19 28587[47:Spt:28585.0] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.19 28589[47:Res:28587.0,61.1] always3(s21) || -> . % 76.01/76.19 28590[47:SSi:28589.0,710.0,27510.0] || -> . % 76.01/76.19 28591[47:Spt:28590.0,28585.0,28587.0] || m_main_v_state(s21,c_busy)* -> . % 76.01/76.19 28592[47:Spt:28590.0,28585.1] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.19 28596[47:Res:28592.0,61.1] always3(s22) || -> . % 76.01/76.19 28597[47:SSi:28596.0,711.0] || -> . % 76.01/76.19 28598[45:Spt:28597.0,27508.2,27509.0] || xuntil6(s20)*+ -> . % 76.01/76.19 28599[45:Spt:28597.0,27508.0,27508.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.01/76.19 28600[45:Res:53.1,28599.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.01/76.19 28602[46:Spt:28600.0] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.19 28604[46:Res:28602.0,61.1] always3(s20) || -> . % 76.01/76.19 28605[46:SSi:28604.0,709.0,27507.0] || -> . % 76.01/76.19 28606[46:Spt:28605.0,28600.0,28602.0] || m_main_v_state(s20,c_busy)* -> . % 76.01/76.19 28607[46:Spt:28605.0,28600.1] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.19 28611[46:Res:28607.0,61.1] always3(s21) || -> . % 76.01/76.19 28612[46:SSi:28611.0,710.0] || -> . % 76.01/76.19 28613[44:Spt:28612.0,27502.2,27506.0] || xuntil6(s19)*+ -> . % 76.01/76.19 28614[44:Spt:28612.0,27502.0,27502.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.01/76.19 28615[44:Res:53.1,28614.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.01/76.19 28617[45:Spt:28615.0] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.19 28619[45:Res:28617.0,61.1] always3(s19) || -> . % 76.01/76.19 28620[45:SSi:28619.0,708.0,27501.0] || -> . % 76.01/76.19 28621[45:Spt:28620.0,28615.0,28617.0] || m_main_v_state(s19,c_busy)* -> . % 76.01/76.19 28622[45:Spt:28620.0,28615.1] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.19 28626[45:Res:28622.0,61.1] always3(s20) || -> . % 76.01/76.19 28627[45:SSi:28626.0,709.0] || -> . % 76.01/76.19 28628[43:Spt:28627.0,27499.2,27500.0] || xuntil6(s18)*+ -> . % 76.01/76.19 28629[43:Spt:28627.0,27499.0,27499.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.01/76.19 28630[43:Res:53.1,28629.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.01/76.19 28635[44:Spt:28630.0] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.19 28637[44:Res:28635.0,61.1] always3(s18) || -> . % 76.01/76.19 28638[44:SSi:28637.0,707.0,27498.0] || -> . % 76.01/76.19 28639[44:Spt:28638.0,28630.0,28635.0] || m_main_v_state(s18,c_busy)* -> . % 76.01/76.19 28640[44:Spt:28638.0,28630.1] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.19 28644[44:Res:28640.0,61.1] always3(s19) || -> . % 76.01/76.19 28645[44:SSi:28644.0,708.0] || -> . % 76.01/76.19 28646[42:Spt:28645.0,27493.2,27497.0] || xuntil6(s17)*+ -> . % 76.01/76.19 28647[42:Spt:28645.0,27493.0,27493.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.01/76.19 28648[42:Res:53.1,28647.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.01/76.19 28650[43:Spt:28648.0] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.19 28652[43:Res:28650.0,61.1] always3(s17) || -> . % 76.01/76.19 28653[43:SSi:28652.0,706.0,27492.0] || -> . % 76.01/76.19 28654[43:Spt:28653.0,28648.0,28650.0] || m_main_v_state(s17,c_busy)* -> . % 76.01/76.19 28655[43:Spt:28653.0,28648.1] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.19 28659[43:Res:28655.0,61.1] always3(s18) || -> . % 76.01/76.19 28660[43:SSi:28659.0,707.0] || -> . % 76.01/76.19 28661[41:Spt:28660.0,27490.2,27491.0] || xuntil6(s16)*+ -> . % 76.01/76.19 28662[41:Spt:28660.0,27490.0,27490.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.01/76.19 28663[41:Res:53.1,28662.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.01/76.19 28665[42:Spt:28663.0] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.19 28667[42:Res:28665.0,61.1] always3(s16) || -> . % 76.01/76.19 28668[42:SSi:28667.0,705.0,27489.0] || -> . % 76.01/76.19 28669[42:Spt:28668.0,28663.0,28665.0] || m_main_v_state(s16,c_busy)* -> . % 76.01/76.19 28670[42:Spt:28668.0,28663.1] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.19 28674[42:Res:28670.0,61.1] always3(s17) || -> . % 76.01/76.19 28675[42:SSi:28674.0,706.0] || -> . % 76.01/76.19 28676[40:Spt:28675.0,27484.2,27488.0] || xuntil6(s15)*+ -> . % 76.01/76.19 28677[40:Spt:28675.0,27484.0,27484.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.01/76.19 28678[40:Res:53.1,28677.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.01/76.19 28683[41:Spt:28678.0] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.19 28685[41:Res:28683.0,61.1] always3(s15) || -> . % 76.01/76.19 28686[41:SSi:28685.0,704.0,27483.0] || -> . % 76.01/76.19 28687[41:Spt:28686.0,28678.0,28683.0] || m_main_v_state(s15,c_busy)* -> . % 76.01/76.19 28688[41:Spt:28686.0,28678.1] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.19 28692[41:Res:28688.0,61.1] always3(s16) || -> . % 76.01/76.19 28693[41:SSi:28692.0,705.0] || -> . % 76.01/76.19 28694[39:Spt:28693.0,27481.2,27482.0] || xuntil6(s14)*+ -> . % 76.01/76.19 28695[39:Spt:28693.0,27481.0,27481.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.01/76.19 28696[39:Res:53.1,28695.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.01/76.19 28698[40:Spt:28696.0] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.19 28700[40:Res:28698.0,61.1] always3(s14) || -> . % 76.01/76.19 28701[40:SSi:28700.0,703.0,27480.0] || -> . % 76.01/76.19 28702[40:Spt:28701.0,28696.0,28698.0] || m_main_v_state(s14,c_busy)* -> . % 76.01/76.19 28703[40:Spt:28701.0,28696.1] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.19 28707[40:Res:28703.0,61.1] always3(s15) || -> . % 76.01/76.19 28708[40:SSi:28707.0,704.0] || -> . % 76.01/76.19 28709[38:Spt:28708.0,27475.2,27479.0] || xuntil6(s13)*+ -> . % 76.01/76.19 28710[38:Spt:28708.0,27475.0,27475.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.01/76.19 28711[38:Res:53.1,28710.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.01/76.19 28713[39:Spt:28711.0] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.19 28715[39:Res:28713.0,61.1] always3(s13) || -> . % 76.01/76.19 28716[39:SSi:28715.0,702.0,27474.0] || -> . % 76.01/76.19 28717[39:Spt:28716.0,28711.0,28713.0] || m_main_v_state(s13,c_busy)* -> . % 76.01/76.19 28718[39:Spt:28716.0,28711.1] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.19 28722[39:Res:28718.0,61.1] always3(s14) || -> . % 76.01/76.19 28723[39:SSi:28722.0,703.0] || -> . % 76.01/76.19 28724[37:Spt:28723.0,27472.2,27473.0] || xuntil6(s12)*+ -> . % 76.01/76.19 28725[37:Spt:28723.0,27472.0,27472.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.01/76.19 28726[37:Res:53.1,28725.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.01/76.19 28731[38:Spt:28726.0] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.19 28733[38:Res:28731.0,61.1] always3(s12) || -> . % 76.01/76.19 28734[38:SSi:28733.0,701.0,27471.0] || -> . % 76.01/76.19 28735[38:Spt:28734.0,28726.0,28731.0] || m_main_v_state(s12,c_busy)* -> . % 76.01/76.19 28736[38:Spt:28734.0,28726.1] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.19 28740[38:Res:28736.0,61.1] always3(s13) || -> . % 76.01/76.19 28741[38:SSi:28740.0,702.0] || -> . % 76.01/76.19 28742[36:Spt:28741.0,27466.2,27470.0] || xuntil6(s11)*+ -> . % 76.01/76.19 28743[36:Spt:28741.0,27466.0,27466.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.01/76.19 28744[36:Res:53.1,28743.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.01/76.19 28746[37:Spt:28744.0] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.19 28748[37:Res:28746.0,61.1] always3(s11) || -> . % 76.01/76.19 28749[37:SSi:28748.0,700.0,27465.0] || -> . % 76.01/76.19 28750[37:Spt:28749.0,28744.0,28746.0] || m_main_v_state(s11,c_busy)* -> . % 76.01/76.19 28751[37:Spt:28749.0,28744.1] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.19 28755[37:Res:28751.0,61.1] always3(s12) || -> . % 76.01/76.19 28756[37:SSi:28755.0,701.0] || -> . % 76.01/76.19 28757[35:Spt:28756.0,27463.2,27464.0] || xuntil6(s10)*+ -> . % 76.01/76.19 28758[35:Spt:28756.0,27463.0,27463.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.01/76.19 28759[35:Res:53.1,28758.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.01/76.19 28761[36:Spt:28759.0] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.19 28763[36:Res:28761.0,61.1] always3(s10) || -> . % 76.01/76.19 28764[36:SSi:28763.0,699.0,27462.0] || -> . % 76.01/76.19 28765[36:Spt:28764.0,28759.0,28761.0] || m_main_v_state(s10,c_busy)* -> . % 76.01/76.19 28766[36:Spt:28764.0,28759.1] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.19 28770[36:Res:28766.0,61.1] always3(s11) || -> . % 76.01/76.19 28771[36:SSi:28770.0,700.0] || -> . % 76.01/76.19 28772[34:Spt:28771.0,27457.2,27461.0] || xuntil6(s9)*+ -> . % 76.01/76.19 28773[34:Spt:28771.0,27457.0,27457.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.01/76.19 28774[34:Res:53.1,28773.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.01/76.19 28779[35:Spt:28774.0] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.19 28781[35:Res:28779.0,61.1] always3(s9) || -> . % 76.01/76.19 28782[35:SSi:28781.0,698.0,27456.0] || -> . % 76.01/76.19 28783[35:Spt:28782.0,28774.0,28779.0] || m_main_v_state(s9,c_busy)* -> . % 76.01/76.19 28784[35:Spt:28782.0,28774.1] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.19 28788[35:Res:28784.0,61.1] always3(s10) || -> . % 76.01/76.19 28789[35:SSi:28788.0,699.0] || -> . % 76.01/76.19 28790[33:Spt:28789.0,27454.2,27455.0] || xuntil6(s8)*+ -> . % 76.01/76.19 28791[33:Spt:28789.0,27454.0,27454.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.01/76.19 28792[33:Res:53.1,28791.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.01/76.19 28794[34:Spt:28792.0] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.19 28796[34:Res:28794.0,61.1] always3(s8) || -> . % 76.01/76.19 28797[34:SSi:28796.0,697.0,27453.0] || -> . % 76.01/76.19 28798[34:Spt:28797.0,28792.0,28794.0] || m_main_v_state(s8,c_busy)* -> . % 76.01/76.19 28799[34:Spt:28797.0,28792.1] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.19 28803[34:Res:28799.0,61.1] always3(s9) || -> . % 76.01/76.19 28804[34:SSi:28803.0,698.0] || -> . % 76.01/76.19 28805[32:Spt:28804.0,27448.2,27452.0] || xuntil6(s7)*+ -> . % 76.01/76.19 28806[32:Spt:28804.0,27448.0,27448.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.01/76.19 28807[32:Res:53.1,28806.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.01/76.19 28809[33:Spt:28807.0] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.19 28811[33:Res:28809.0,61.1] always3(s7) || -> . % 76.01/76.19 28812[33:SSi:28811.0,696.0,27447.0] || -> . % 76.01/76.19 28813[33:Spt:28812.0,28807.0,28809.0] || m_main_v_state(s7,c_busy)* -> . % 76.01/76.19 28814[33:Spt:28812.0,28807.1] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.19 28818[33:Res:28814.0,61.1] always3(s8) || -> . % 76.01/76.19 28819[33:SSi:28818.0,697.0] || -> . % 76.01/76.19 28820[31:Spt:28819.0,27445.2,27446.0] || xuntil6(s6)*+ -> . % 76.01/76.19 28821[31:Spt:28819.0,27445.0,27445.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.01/76.19 28822[31:Res:53.1,28821.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.01/76.19 28827[32:Spt:28822.0] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.19 28829[32:Res:28827.0,61.1] always3(s6) || -> . % 76.01/76.19 28830[32:SSi:28829.0,695.0,27444.0] || -> . % 76.01/76.19 28831[32:Spt:28830.0,28822.0,28827.0] || m_main_v_state(s6,c_busy)* -> . % 76.01/76.19 28832[32:Spt:28830.0,28822.1] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.19 28836[32:Res:28832.0,61.1] always3(s7) || -> . % 76.01/76.19 28837[32:SSi:28836.0,696.0] || -> . % 76.01/76.19 28838[30:Spt:28837.0,27439.2,27443.0] || xuntil6(s5)*+ -> . % 76.01/76.19 28839[30:Spt:28837.0,27439.0,27439.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.01/76.19 28840[30:Res:53.1,28839.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.01/76.19 28842[31:Spt:28840.0] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.19 28844[31:Res:28842.0,61.1] always3(s5) || -> . % 76.01/76.19 28845[31:SSi:28844.0,694.0,27438.0] || -> . % 76.01/76.19 28846[31:Spt:28845.0,28840.0,28842.0] || m_main_v_state(s5,c_busy)* -> . % 76.01/76.19 28847[31:Spt:28845.0,28840.1] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.19 28851[31:Res:28847.0,61.1] always3(s6) || -> . % 76.01/76.19 28852[31:SSi:28851.0,695.0] || -> . % 76.01/76.19 28853[29:Spt:28852.0,27436.2,27437.0] || xuntil6(s4)*+ -> . % 76.01/76.19 28854[29:Spt:28852.0,27436.0,27436.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.01/76.19 28855[29:Res:53.1,28854.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.01/76.19 28857[30:Spt:28855.0] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.19 28859[30:Res:28857.0,61.1] always3(s4) || -> . % 76.01/76.19 28860[30:SSi:28859.0,693.0,27435.0] || -> . % 76.01/76.19 28861[30:Spt:28860.0,28855.0,28857.0] || m_main_v_state(s4,c_busy)* -> . % 76.01/76.19 28862[30:Spt:28860.0,28855.1] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.19 28866[30:Res:28862.0,61.1] always3(s5) || -> . % 76.01/76.19 28867[30:SSi:28866.0,694.0] || -> . % 76.01/76.19 28868[28:Spt:28867.0,27433.2,27434.0] || xuntil6(s3)*+ -> . % 76.01/76.19 28869[28:Spt:28867.0,27433.0,27433.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.01/76.19 28870[28:Res:53.1,28869.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.01/76.19 28875[29:Spt:28870.0] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.19 28877[29:Res:28875.0,61.1] always3(s3) || -> . % 76.01/76.19 28878[29:SSi:28877.0,692.0,27432.0] || -> . % 76.01/76.19 28879[29:Spt:28878.0,28870.0,28875.0] || m_main_v_state(s3,c_busy)* -> . % 76.01/76.19 28880[29:Spt:28878.0,28870.1] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.19 28884[29:Res:28880.0,61.1] always3(s4) || -> . % 76.01/76.19 28885[29:SSi:28884.0,693.0] || -> . % 76.01/76.19 28886[27:Spt:28885.0,27430.2,27431.0] || xuntil6(s2)*+ -> . % 76.01/76.19 28887[27:Spt:28885.0,27430.0,27430.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.01/76.19 28888[27:Res:53.1,28887.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.01/76.19 28890[28:Spt:28888.0] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.19 28892[28:Res:28890.0,61.1] always3(s2) || -> . % 76.01/76.19 28893[28:SSi:28892.0,691.0,27429.0] || -> . % 76.01/76.19 28894[28:Spt:28893.0,28888.0,28890.0] || m_main_v_state(s2,c_busy)* -> . % 76.01/76.19 28895[28:Spt:28893.0,28888.1] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.19 28899[28:Res:28895.0,61.1] always3(s3) || -> . % 76.01/76.19 28900[28:SSi:28899.0,692.0] || -> . % 76.01/76.19 28901[26:Spt:28900.0,27424.2,27428.0] || xuntil6(s1)*+ -> . % 76.01/76.19 28902[26:Spt:28900.0,27424.0,27424.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.01/76.19 28903[26:Res:53.1,28902.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.01/76.19 28905[27:Spt:28903.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.19 28907[27:Res:28905.0,61.1] always3(s1) || -> . % 76.01/76.19 28908[27:SSi:28907.0,690.0,27423.0] || -> . % 76.01/76.19 28909[27:Spt:28908.0,28903.0,28905.0] || m_main_v_state(s1,c_busy)* -> . % 76.01/76.19 28910[27:Spt:28908.0,28903.1] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.19 28915[27:Res:28910.0,61.1] always3(s2) || -> . % 76.01/76.19 28916[27:SSi:28915.0,691.0] || -> . % 76.01/76.19 28917[25:Spt:28916.0,74.0,27422.0] || xuntil6(s0)*+ -> . % 76.01/76.19 28918[25:Spt:28916.0,74.1] || -> node4(s0)*. % 76.01/76.19 28919[25:MRR:758.1,28917.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.19 28921[25:Res:28919.0,61.1] always3(s1) || -> . % 76.01/76.19 28922[25:SSi:28921.0,690.0] || -> . % 76.01/76.19 28923[24:Spt:28922.0,27412.0,27416.0] || trans(s49,s27)*+ -> . % 76.01/76.19 28924[24:Spt:28922.0,27412.1,27412.2,27412.3,27412.4,27412.5,27412.6,27412.7,27412.8,27412.9,27412.10,27412.11,27412.12,27412.13,27412.14,27412.15,27412.16,27412.17,27412.18,27412.19,27412.20,27412.21,27412.22,27412.23,27412.24,27412.25,27412.26,27412.27] || -> trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.01/76.19 28925[24:MRR:27414.0,28923.0] || -> trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.01/76.19 28927[24:MRR:27415.1,28923.0] xuntil6(s49) || -> trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.01/76.19 28928[25:Spt:28924.0] || -> trans(s49,s26)*. % 76.01/76.19 28929[25:Res:28928.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s26)*. % 76.01/76.19 28931[25:Res:28928.0,60.0] || -> node2(s49,s26)*. % 76.01/76.19 28932[25:SSi:28929.1,50.0,738.0] xuntil6(s49) || -> until2p7(s26)*. % 76.01/76.19 28933[25:Res:28931.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)*. % 76.01/76.19 28934[26:Spt:74.0] || -> xuntil6(s0)*. % 76.01/76.19 28935[26:MRR:176.0,28934.0] || -> until5(s1)*. % 76.01/76.19 28936[26:MRR:27861.0,28935.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.19 28940[27:Spt:28936.2] || -> xuntil6(s1)*. % 76.01/76.19 28941[27:MRR:175.0,28940.0] || -> until5(s2)*. % 76.01/76.19 28942[27:MRR:27857.0,28941.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.19 28946[28:Spt:28942.2] || -> xuntil6(s2)*. % 76.01/76.19 28947[28:MRR:174.0,28946.0] || -> until5(s3)*. % 76.01/76.19 28948[28:MRR:27853.0,28947.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.19 28949[29:Spt:28948.2] || -> xuntil6(s3)*. % 76.01/76.19 28950[29:MRR:173.0,28949.0] || -> until5(s4)*. % 76.01/76.19 28951[29:MRR:27852.0,28950.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.19 28955[30:Spt:28951.2] || -> xuntil6(s4)*. % 76.01/76.19 28956[30:MRR:172.0,28955.0] || -> until5(s5)*. % 76.01/76.19 28957[30:MRR:27845.0,28956.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.19 28958[31:Spt:28957.2] || -> xuntil6(s5)*. % 76.01/76.19 28959[31:MRR:171.0,28958.0] || -> until5(s6)*. % 76.01/76.19 28960[31:MRR:27841.0,28959.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.19 28964[32:Spt:28960.2] || -> xuntil6(s6)*. % 76.01/76.19 28965[32:MRR:170.0,28964.0] || -> until5(s7)*. % 76.01/76.19 28966[32:MRR:27837.0,28965.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.19 28967[33:Spt:28966.2] || -> xuntil6(s7)*. % 76.01/76.19 28968[33:MRR:169.0,28967.0] || -> until5(s8)*. % 76.01/76.19 28969[33:MRR:27833.0,28968.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.19 28973[34:Spt:28969.2] || -> xuntil6(s8)*. % 76.01/76.19 28974[34:MRR:168.0,28973.0] || -> until5(s9)*. % 76.01/76.19 28975[34:MRR:27832.0,28974.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.19 28976[35:Spt:28975.2] || -> xuntil6(s9)*. % 76.01/76.19 28977[35:MRR:167.0,28976.0] || -> until5(s10)*. % 76.01/76.19 28978[35:MRR:27825.0,28977.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.19 28982[36:Spt:28978.2] || -> xuntil6(s10)*. % 76.01/76.19 28983[36:MRR:166.0,28982.0] || -> until5(s11)*. % 76.01/76.19 28984[36:MRR:27821.0,28983.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.19 28985[37:Spt:28984.2] || -> xuntil6(s11)*. % 76.01/76.19 28986[37:MRR:165.0,28985.0] || -> until5(s12)*. % 76.01/76.19 28987[37:MRR:27817.0,28986.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.19 28991[38:Spt:28987.2] || -> xuntil6(s12)*. % 76.01/76.19 28992[38:MRR:164.0,28991.0] || -> until5(s13)*. % 76.01/76.19 28993[38:MRR:27813.0,28992.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.19 28994[39:Spt:28993.2] || -> xuntil6(s13)*. % 76.01/76.19 28995[39:MRR:163.0,28994.0] || -> until5(s14)*. % 76.01/76.19 28996[39:MRR:27812.0,28995.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.19 29000[40:Spt:28996.2] || -> xuntil6(s14)*. % 76.01/76.19 29001[40:MRR:162.0,29000.0] || -> until5(s15)*. % 76.01/76.19 29002[40:MRR:27805.0,29001.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.19 29003[41:Spt:29002.2] || -> xuntil6(s15)*. % 76.01/76.19 29004[41:MRR:161.0,29003.0] || -> until5(s16)*. % 76.01/76.19 29005[41:MRR:27801.0,29004.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.19 29009[42:Spt:29005.2] || -> xuntil6(s16)*. % 76.01/76.19 29010[42:MRR:160.0,29009.0] || -> until5(s17)*. % 76.01/76.19 29011[42:MRR:27797.0,29010.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.19 29012[43:Spt:29011.2] || -> xuntil6(s17)*. % 76.01/76.19 29013[43:MRR:159.0,29012.0] || -> until5(s18)*. % 76.01/76.19 29014[43:MRR:27793.0,29013.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.19 29018[44:Spt:29014.2] || -> xuntil6(s18)*. % 76.01/76.19 29019[44:MRR:158.0,29018.0] || -> until5(s19)*. % 76.01/76.19 29020[44:MRR:27792.0,29019.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.19 29021[45:Spt:29020.2] || -> xuntil6(s19)*. % 76.01/76.19 29022[45:MRR:157.0,29021.0] || -> until5(s20)*. % 76.01/76.19 29023[45:MRR:27785.0,29022.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.19 29027[46:Spt:29023.2] || -> xuntil6(s20)*. % 76.01/76.19 29028[46:MRR:156.0,29027.0] || -> until5(s21)*. % 76.01/76.19 29029[46:MRR:27781.0,29028.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.19 29030[47:Spt:29029.2] || -> xuntil6(s21)*. % 76.01/76.19 29031[47:MRR:155.0,29030.0] || -> until5(s22)*. % 76.01/76.19 29032[47:MRR:27777.0,29031.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.19 29036[48:Spt:29032.2] || -> xuntil6(s22)*. % 76.01/76.19 29037[48:MRR:154.0,29036.0] || -> until5(s23)*. % 76.01/76.19 29038[48:MRR:27773.0,29037.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.19 29039[49:Spt:29038.2] || -> xuntil6(s23)*. % 76.01/76.19 29040[49:MRR:153.0,29039.0] || -> until5(s24)*. % 76.01/76.19 29041[49:MRR:27772.0,29040.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.19 29045[50:Spt:29041.2] || -> xuntil6(s24)*. % 76.01/76.19 29046[50:MRR:152.0,29045.0] || -> until5(s25)*. % 76.01/76.19 29047[50:MRR:27765.0,29046.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.19 29048[51:Spt:29047.2] || -> xuntil6(s25)*. % 76.01/76.19 29049[51:MRR:151.0,29048.0] || -> until5(s26)*. % 76.01/76.19 29050[51:MRR:27764.0,29049.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.19 29054[52:Spt:29050.2] || -> xuntil6(s26)*. % 76.01/76.19 29055[52:MRR:150.0,29054.0] || -> until5(s27)*. % 76.01/76.19 29056[52:MRR:27763.0,29055.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.19 29057[53:Spt:29056.2] || -> xuntil6(s27)*. % 76.01/76.19 29058[53:MRR:149.0,29057.0] || -> until5(s28)*. % 76.01/76.19 29059[53:MRR:27759.0,29058.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.19 29063[54:Spt:29059.2] || -> xuntil6(s28)*. % 76.01/76.19 29064[54:MRR:148.0,29063.0] || -> until5(s29)*. % 76.01/76.19 29065[54:MRR:26398.0,29064.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.19 29066[55:Spt:29065.1] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.19 29068[55:Res:29066.0,61.1] always3(s30) || -> . % 76.01/76.19 29069[55:SSi:29068.0,719.0] || -> . % 76.01/76.19 29070[55:Spt:29069.0,29065.1,29066.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.01/76.19 29071[55:Spt:29069.0,29065.0,29065.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 76.01/76.19 29073[55:MRR:831.2,29070.0] node4(s29) || m_main_v_state(s29,c_ready)* -> . % 76.01/76.19 29074[55:Res:53.1,29071.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 76.01/76.19 29079[56:Spt:29074.1] || -> xuntil6(s29)*. % 76.01/76.19 29080[56:MRR:147.0,29079.0] || -> until5(s30)*. % 76.01/76.19 29081[56:MRR:27868.0,29080.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.19 29083[57:Spt:29081.2] || -> xuntil6(s30)*. % 76.01/76.19 29084[57:MRR:146.0,29083.0] || -> until5(s31)*. % 76.01/76.19 29085[57:MRR:26402.0,29084.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.19 29086[58:Spt:29085.1] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.19 29088[58:Res:29086.0,61.1] always3(s32) || -> . % 76.01/76.19 29089[58:SSi:29088.0,721.0] || -> . % 76.01/76.19 29090[58:Spt:29089.0,29085.1,29086.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.01/76.19 29091[58:Spt:29089.0,29085.0,29085.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.01/76.19 29093[58:MRR:825.2,29090.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.01/76.19 29094[58:Res:53.1,29091.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.01/76.19 29096[59:Spt:29094.1] || -> xuntil6(s31)*. % 76.01/76.19 29097[59:MRR:145.0,29096.0] || -> until5(s32)*. % 76.01/76.19 29098[59:MRR:27872.0,29097.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.19 29103[60:Spt:29098.2] || -> xuntil6(s32)*. % 76.01/76.19 29104[60:MRR:144.0,29103.0] || -> until5(s33)*. % 76.01/76.19 29105[60:MRR:26409.0,29104.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.19 29106[61:Spt:29105.1] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.19 29108[61:Res:29106.0,61.1] always3(s34) || -> . % 76.01/76.19 29109[61:SSi:29108.0,723.0] || -> . % 76.01/76.19 29110[61:Spt:29109.0,29105.1,29106.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.01/76.19 29111[61:Spt:29109.0,29105.0,29105.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.01/76.19 29113[61:MRR:819.2,29110.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.01/76.19 29114[61:Res:53.1,29111.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.01/76.19 29116[62:Spt:29114.1] || -> xuntil6(s33)*. % 76.01/76.19 29117[62:MRR:143.0,29116.0] || -> until5(s34)*. % 76.01/76.19 29118[62:MRR:27876.0,29117.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.19 29126[63:Spt:29118.2] || -> xuntil6(s34)*. % 76.01/76.19 29127[63:MRR:142.0,29126.0] || -> until5(s35)*. % 76.01/76.19 29128[63:MRR:26410.0,29127.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.19 29129[64:Spt:29128.1] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.19 29131[64:Res:29129.0,61.1] always3(s36) || -> . % 76.01/76.19 29132[64:SSi:29131.0,725.0] || -> . % 76.01/76.19 29133[64:Spt:29132.0,29128.1,29129.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.01/76.19 29134[64:Spt:29132.0,29128.0,29128.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.01/76.19 29136[64:MRR:813.2,29133.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.01/76.19 29137[64:Res:53.1,29134.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.01/76.19 29142[65:Spt:29137.1] || -> xuntil6(s35)*. % 76.01/76.19 29143[65:MRR:141.0,29142.0] || -> until5(s36)*. % 76.01/76.19 29144[65:MRR:27883.0,29143.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.19 29146[66:Spt:29144.2] || -> xuntil6(s36)*. % 76.01/76.19 29147[66:MRR:140.0,29146.0] || -> until5(s37)*. % 76.01/76.19 29148[66:MRR:26414.0,29147.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.19 29149[67:Spt:29148.1] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.19 29151[67:Res:29149.0,61.1] always3(s38) || -> . % 76.01/76.19 29152[67:SSi:29151.0,727.0] || -> . % 76.01/76.19 29153[67:Spt:29152.0,29148.1,29149.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.01/76.19 29154[67:Spt:29152.0,29148.0,29148.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.01/76.19 29156[67:MRR:807.2,29153.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.01/76.19 29157[67:Res:53.1,29154.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.01/76.19 29159[68:Spt:29157.1] || -> xuntil6(s37)*. % 76.01/76.19 29160[68:MRR:139.0,29159.0] || -> until5(s38)*. % 76.01/76.19 29161[68:MRR:27884.0,29160.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.19 29166[69:Spt:29161.2] || -> xuntil6(s38)*. % 76.01/76.19 29167[69:MRR:138.0,29166.0] || -> until5(s39)*. % 76.01/76.19 29168[69:MRR:26418.0,29167.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.19 29169[70:Spt:29168.1] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.19 29171[70:Res:29169.0,61.1] always3(s40) || -> . % 76.01/76.19 29172[70:SSi:29171.0,729.0] || -> . % 76.01/76.19 29173[70:Spt:29172.0,29168.1,29169.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.01/76.19 29174[70:Spt:29172.0,29168.0,29168.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.01/76.19 29176[70:MRR:801.2,29173.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.01/76.19 29177[70:Res:53.1,29174.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.01/76.19 29179[71:Spt:29177.1] || -> xuntil6(s39)*. % 76.01/76.19 29180[71:MRR:137.0,29179.0] || -> until5(s40)*. % 76.01/76.19 29181[71:MRR:27888.0,29180.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.01/76.19 29189[72:Spt:29181.2] || -> xuntil6(s40)*. % 76.01/76.19 29190[72:MRR:136.0,29189.0] || -> until5(s41)*. % 76.01/76.19 29191[72:MRR:26422.0,29190.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.19 29192[73:Spt:29191.1] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.19 29194[73:Res:29192.0,61.1] always3(s42) || -> . % 76.01/76.19 29195[73:SSi:29194.0,731.0] || -> . % 76.01/76.19 29196[73:Spt:29195.0,29191.1,29192.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.01/76.19 29197[73:Spt:29195.0,29191.0,29191.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.01/76.19 29199[73:MRR:795.2,29196.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.01/76.19 29200[73:Res:53.1,29197.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.01/76.19 29205[74:Spt:29200.1] || -> xuntil6(s41)*. % 76.01/76.19 29206[74:MRR:135.0,29205.0] || -> until5(s42)*. % 76.01/76.19 29207[74:MRR:27892.0,29206.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.01/76.19 29209[75:Spt:29207.2] || -> xuntil6(s42)*. % 76.01/76.19 29210[75:MRR:134.0,29209.0] || -> until5(s43)*. % 76.01/76.19 29211[75:MRR:26429.0,29210.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.19 29212[76:Spt:29211.1] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.19 29214[76:Res:29212.0,61.1] always3(s44) || -> . % 76.01/76.19 29215[76:SSi:29214.0,733.0] || -> . % 76.01/76.19 29216[76:Spt:29215.0,29211.1,29212.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.01/76.19 29217[76:Spt:29215.0,29211.0,29211.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.01/76.19 29219[76:MRR:789.2,29216.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.01/76.19 29220[76:Res:53.1,29217.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.01/76.19 29222[77:Spt:29220.1] || -> xuntil6(s43)*. % 76.01/76.19 29223[77:MRR:133.0,29222.0] || -> until5(s44)*. % 76.01/76.19 29224[77:MRR:27896.0,29223.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.01/76.19 29229[78:Spt:29224.2] || -> xuntil6(s44)*. % 76.01/76.19 29230[78:MRR:132.0,29229.0] || -> until5(s45)*. % 76.01/76.19 29231[78:MRR:26430.0,29230.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.19 29232[79:Spt:29231.1] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.19 29234[79:Res:29232.0,61.1] always3(s46) || -> . % 76.01/76.19 29235[79:SSi:29234.0,735.0] || -> . % 76.01/76.19 29236[79:Spt:29235.0,29231.1,29232.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.01/76.19 29237[79:Spt:29235.0,29231.0,29231.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.01/76.19 29239[79:MRR:783.2,29236.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.01/76.19 29240[79:Res:53.1,29237.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.01/76.19 29242[80:Spt:29240.1] || -> xuntil6(s45)*. % 76.01/76.19 29243[80:MRR:131.0,29242.0] || -> until5(s46)*. % 76.01/76.19 29244[80:MRR:27903.0,29243.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.01/76.19 29252[81:Spt:29244.2] || -> xuntil6(s46)*. % 76.01/76.19 29253[81:MRR:130.0,29252.0] || -> until5(s47)*. % 76.01/76.19 29254[81:MRR:26434.0,29253.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.19 29255[82:Spt:29254.1] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.19 29257[82:Res:29255.0,61.1] always3(s48) || -> . % 76.01/76.19 29258[82:SSi:29257.0,737.0] || -> . % 76.01/76.19 29259[82:Spt:29258.0,29254.1,29255.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.01/76.19 29260[82:Spt:29258.0,29254.0,29254.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.01/76.19 29262[82:MRR:777.2,29259.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.01/76.19 29263[82:Res:53.1,29260.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.01/76.19 29268[83:Spt:29263.1] || -> xuntil6(s47)*. % 76.01/76.19 29269[83:MRR:129.0,29268.0] || -> until5(s48)*. % 76.01/76.19 29270[83:MRR:27904.0,29269.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.01/76.19 29272[84:Spt:29270.2] || -> xuntil6(s48)*. % 76.01/76.19 29273[84:MRR:128.0,29272.0] || -> until5(s49)*. % 76.01/76.19 29274[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.19 29275[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.19 29276[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.19 29283[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.19 29284[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.19 29288[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.19 29292[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.19 29296[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.19 29303[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.19 29304[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.19 29308[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.19 29312[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.19 29316[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.19 29323[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.19 29324[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.19 29328[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.19 29332[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.19 29336[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.19 29343[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.19 29344[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.19 29348[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.19 29352[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.19 29356[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.19 29363[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.19 29364[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.19 29368[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.19 29372[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.19 29376[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.19 29378[25:SoR:28933.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)*. % 76.01/76.19 29383[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.19 29387[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.19 29394[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.19 29395[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.19 29399[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.19 29403[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.01/76.19 29407[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.01/76.19 29414[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.01/76.19 29415[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.01/76.19 29419[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.01/76.19 29420[25:SoR:29378.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)* xuntil6(s49). % 76.01/76.19 29421[84:SSi:29420.0,50.0,738.0,29273.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s26,c_busy)* xuntil6(s49). % 76.01/76.19 29422[85:Spt:29421.1] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.19 29424[85:Res:29422.0,61.1] always3(s26) || -> . % 76.01/76.19 29425[85:SSi:29424.0,715.0,29049.0,29054.0] || -> . % 76.01/76.19 29426[85:Spt:29425.0,29421.1,29422.0] || m_main_v_state(s26,c_busy)*+ -> . % 76.01/76.19 29427[85:Spt:29425.0,29421.0,29421.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.01/76.19 29431[85:MRR:29378.2,29426.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.01/76.19 29432[85:Res:53.1,29427.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.01/76.19 29434[86:Spt:29432.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.19 29436[86:Res:29434.0,61.1] always3(s49) || -> . % 76.01/76.19 29437[86:SSi:29436.0,50.0,738.0,29273.0] || -> . % 76.01/76.19 29438[86:Spt:29437.0,29432.0,29434.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.01/76.19 29439[86:Spt:29437.0,29432.1] || -> xuntil6(s49)*. % 76.01/76.19 29440[86:MRR:28932.0,29439.0] || -> until2p7(s26)*. % 76.01/76.19 29441[86:MRR:222.0,29440.0] || -> until2p7(s27)* node4(s26). % 76.01/76.19 29443[86:MRR:774.2,29438.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.01/76.19 29444[87:Spt:29441.0] || -> until2p7(s27)*. % 76.01/76.19 29445[87:MRR:223.0,29444.0] || -> until2p7(s28)* node4(s27). % 76.01/76.19 29446[88:Spt:29445.0] || -> until2p7(s28)*. % 76.01/76.19 29447[88:MRR:224.0,29446.0] || -> until2p7(s29)* node4(s28). % 76.01/76.19 29448[89:Spt:29447.0] || -> until2p7(s29)*. % 76.01/76.19 29449[89:MRR:225.0,29448.0] || -> until2p7(s30)* node4(s29). % 76.01/76.19 29450[90:Spt:29449.0] || -> until2p7(s30)*. % 76.01/76.19 29451[90:MRR:226.0,29450.0] || -> until2p7(s31)* node4(s30). % 76.01/76.19 29452[91:Spt:29451.0] || -> until2p7(s31)*. % 76.01/76.19 29453[91:MRR:227.0,29452.0] || -> until2p7(s32)* node4(s31). % 76.01/76.19 29454[92:Spt:29453.0] || -> until2p7(s32)*. % 76.01/76.19 29455[92:MRR:228.0,29454.0] || -> until2p7(s33)* node4(s32). % 76.01/76.19 29456[93:Spt:29455.0] || -> until2p7(s33)*. % 76.01/76.19 29457[93:MRR:229.0,29456.0] || -> until2p7(s34)* node4(s33). % 76.01/76.19 29458[94:Spt:29457.0] || -> until2p7(s34)*. % 76.01/76.19 29459[94:MRR:230.0,29458.0] || -> until2p7(s35)* node4(s34). % 76.01/76.19 29460[95:Spt:29459.0] || -> until2p7(s35)*. % 76.01/76.19 29461[95:MRR:231.0,29460.0] || -> until2p7(s36)* node4(s35). % 76.01/76.19 29462[96:Spt:29461.0] || -> until2p7(s36)*. % 76.01/76.19 29463[96:MRR:232.0,29462.0] || -> until2p7(s37)* node4(s36). % 76.01/76.19 29464[97:Spt:29463.0] || -> until2p7(s37)*. % 76.01/76.19 29465[97:MRR:235.0,29464.0] || -> until2p7(s38)* node4(s37). % 76.01/76.19 29466[98:Spt:29465.0] || -> until2p7(s38)*. % 76.01/76.19 29467[98:MRR:236.0,29466.0] || -> until2p7(s39)* node4(s38). % 76.01/76.19 29468[99:Spt:29467.0] || -> until2p7(s39)*. % 76.01/76.19 29469[99:MRR:237.0,29468.0] || -> until2p7(s40)* node4(s39). % 76.01/76.19 29470[100:Spt:29469.0] || -> until2p7(s40)*. % 76.01/76.19 29471[100:MRR:238.0,29470.0] || -> until2p7(s41)* node4(s40). % 76.01/76.19 29472[101:Spt:29471.0] || -> until2p7(s41)*. % 76.01/76.19 29473[101:MRR:239.0,29472.0] || -> until2p7(s42)* node4(s41). % 76.01/76.19 29474[102:Spt:29473.0] || -> until2p7(s42)*. % 76.01/76.19 29475[102:MRR:240.0,29474.0] || -> until2p7(s43)* node4(s42). % 76.01/76.19 29476[103:Spt:29475.0] || -> until2p7(s43)*. % 76.01/76.19 29477[103:MRR:241.0,29476.0] || -> until2p7(s44)* node4(s43). % 76.01/76.19 29478[104:Spt:29477.0] || -> until2p7(s44)*. % 76.01/76.19 29479[104:MRR:539.0,29478.0] || -> until2p7(s45)* node4(s44). % 76.01/76.19 29480[105:Spt:29479.0] || -> until2p7(s45)*. % 76.01/76.19 29481[105:MRR:544.0,29480.0] || -> until2p7(s46)* node4(s45). % 76.01/76.19 29482[106:Spt:29481.0] || -> until2p7(s46)*. % 76.01/76.19 29483[106:MRR:549.0,29482.0] || -> until2p7(s47)* node4(s46). % 76.01/76.19 29484[107:Spt:29483.0] || -> until2p7(s47)*. % 76.01/76.19 29485[107:MRR:554.0,29484.0] || -> until2p7(s48)* node4(s47). % 76.01/76.19 29486[108:Spt:29485.0] || -> until2p7(s48)*. % 76.01/76.19 29487[108:MRR:559.0,29486.0] || -> until2p7(s49)* node4(s48). % 76.01/76.19 29488[109:Spt:29487.0] || -> until2p7(s49)*. % 76.01/76.19 29489[109:MRR:194.0,29488.0] || -> node4(s49)*. % 76.01/76.19 29490[109:MRR:29431.0,29489.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.01/76.19 29494[109:Res:53.1,29490.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.19 29496[109:MRR:29494.0,29438.0] || -> . % 76.01/76.19 29497[109:Spt:29496.0,29487.0,29488.0] || until2p7(s49)*+ -> . % 76.01/76.19 29498[109:Spt:29496.0,29487.1] || -> node4(s48)*. % 76.01/76.19 29499[109:MRR:29443.0,29498.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.01/76.19 29502[109:Res:53.1,29499.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.19 29504[109:MRR:29502.0,29259.0] || -> . % 76.01/76.19 29505[108:Spt:29504.0,29485.0,29486.0] || until2p7(s48)*+ -> . % 76.01/76.19 29506[108:Spt:29504.0,29485.1] || -> node4(s47)*. % 76.01/76.19 29507[108:MRR:29262.0,29506.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.01/76.19 29510[108:Res:53.1,29507.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.19 29513[108:Res:29510.0,61.1] always3(s47) || -> . % 76.01/76.19 29514[108:SSi:29513.0,736.0,29253.0,29268.0,29484.0,29506.0] || -> . % 76.01/76.19 29515[107:Spt:29514.0,29483.0,29484.0] || until2p7(s47)*+ -> . % 76.01/76.19 29516[107:Spt:29514.0,29483.1] || -> node4(s46)*. % 76.01/76.19 29518[107:MRR:780.0,29516.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.01/76.19 29535[107:Res:53.1,29518.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.01/76.19 29537[107:MRR:29535.0,29236.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.19 29539[107:Res:29537.0,61.1] always3(s47) || -> . % 76.01/76.19 29540[107:SSi:29539.0,736.0,29253.0,29268.0] || -> . % 76.01/76.19 29541[106:Spt:29540.0,29481.0,29482.0] || until2p7(s46)*+ -> . % 76.01/76.19 29542[106:Spt:29540.0,29481.1] || -> node4(s45)*. % 76.01/76.19 29543[106:MRR:29239.0,29542.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.01/76.19 29546[106:Res:53.1,29543.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.19 29549[106:Res:29546.0,61.1] always3(s45) || -> . % 76.01/76.19 29550[106:SSi:29549.0,734.0,29230.0,29242.0,29480.0,29542.0] || -> . % 76.01/76.19 29551[105:Spt:29550.0,29479.0,29480.0] || until2p7(s45)*+ -> . % 76.01/76.19 29552[105:Spt:29550.0,29479.1] || -> node4(s44)*. % 76.01/76.19 29554[105:MRR:786.0,29552.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.01/76.19 29566[105:Res:53.1,29554.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.01/76.19 29568[105:MRR:29566.0,29216.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.19 29573[105:Res:29568.0,61.1] always3(s45) || -> . % 76.01/76.19 29574[105:SSi:29573.0,734.0,29230.0,29242.0] || -> . % 76.01/76.19 29575[104:Spt:29574.0,29477.0,29478.0] || until2p7(s44)*+ -> . % 76.01/76.19 29576[104:Spt:29574.0,29477.1] || -> node4(s43)*. % 76.01/76.19 29577[104:MRR:29219.0,29576.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.01/76.19 29580[104:Res:53.1,29577.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.19 29584[104:Res:29580.0,61.1] always3(s43) || -> . % 76.01/76.19 29585[104:SSi:29584.0,732.0,29210.0,29222.0,29476.0,29576.0] || -> . % 76.01/76.19 29586[103:Spt:29585.0,29475.0,29476.0] || until2p7(s43)*+ -> . % 76.01/76.19 29587[103:Spt:29585.0,29475.1] || -> node4(s42)*. % 76.01/76.19 29589[103:MRR:792.0,29587.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.01/76.19 29600[103:Res:53.1,29589.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.01/76.19 29602[103:MRR:29600.0,29196.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.19 29604[103:Res:29602.0,61.1] always3(s43) || -> . % 76.01/76.19 29605[103:SSi:29604.0,732.0,29210.0,29222.0] || -> . % 76.01/76.19 29606[102:Spt:29605.0,29473.0,29474.0] || until2p7(s42)*+ -> . % 76.01/76.19 29607[102:Spt:29605.0,29473.1] || -> node4(s41)*. % 76.01/76.19 29608[102:MRR:29199.0,29607.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.01/76.19 29612[102:Res:53.1,29608.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.19 29615[102:Res:29612.0,61.1] always3(s41) || -> . % 76.01/76.19 29616[102:SSi:29615.0,730.0,29190.0,29205.0,29472.0,29607.0] || -> . % 76.01/76.19 29617[101:Spt:29616.0,29471.0,29472.0] || until2p7(s41)*+ -> . % 76.01/76.19 29618[101:Spt:29616.0,29471.1] || -> node4(s40)*. % 76.01/76.19 29620[101:MRR:798.0,29618.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.01/76.19 29631[101:Res:53.1,29620.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.01/76.19 29633[101:MRR:29631.0,29173.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.19 29635[101:Res:29633.0,61.1] always3(s41) || -> . % 76.01/76.19 29636[101:SSi:29635.0,730.0,29190.0,29205.0] || -> . % 76.01/76.19 29637[100:Spt:29636.0,29469.0,29470.0] || until2p7(s40)*+ -> . % 76.01/76.19 29638[100:Spt:29636.0,29469.1] || -> node4(s39)*. % 76.01/76.19 29639[100:MRR:29176.0,29638.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.01/76.19 29642[100:Res:53.1,29639.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.19 29645[100:Res:29642.0,61.1] always3(s39) || -> . % 76.01/76.19 29646[100:SSi:29645.0,728.0,29167.0,29179.0,29468.0,29638.0] || -> . % 76.01/76.19 29647[99:Spt:29646.0,29467.0,29468.0] || until2p7(s39)*+ -> . % 76.01/76.19 29648[99:Spt:29646.0,29467.1] || -> node4(s38)*. % 76.01/76.19 29650[99:MRR:804.0,29648.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.01/76.19 29662[99:Res:53.1,29650.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.01/76.19 29664[99:MRR:29662.0,29153.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.19 29666[99:Res:29664.0,61.1] always3(s39) || -> . % 76.01/76.19 29667[99:SSi:29666.0,728.0,29167.0,29179.0] || -> . % 76.01/76.19 29668[98:Spt:29667.0,29465.0,29466.0] || until2p7(s38)*+ -> . % 76.01/76.19 29669[98:Spt:29667.0,29465.1] || -> node4(s37)*. % 76.01/76.19 29670[98:MRR:29156.0,29669.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.01/76.19 29673[98:Res:53.1,29670.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.19 29676[98:Res:29673.0,61.1] always3(s37) || -> . % 76.01/76.19 29677[98:SSi:29676.0,726.0,29147.0,29159.0,29464.0,29669.0] || -> . % 76.01/76.19 29678[97:Spt:29677.0,29463.0,29464.0] || until2p7(s37)*+ -> . % 76.01/76.19 29679[97:Spt:29677.0,29463.1] || -> node4(s36)*. % 76.01/76.19 29681[97:MRR:810.0,29679.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.01/76.19 29693[97:Res:53.1,29681.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.01/76.19 29695[97:MRR:29693.0,29133.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.19 29700[97:Res:29695.0,61.1] always3(s37) || -> . % 76.01/76.19 29701[97:SSi:29700.0,726.0,29147.0,29159.0] || -> . % 76.01/76.19 29702[96:Spt:29701.0,29461.0,29462.0] || until2p7(s36)*+ -> . % 76.01/76.19 29703[96:Spt:29701.0,29461.1] || -> node4(s35)*. % 76.01/76.19 29704[96:MRR:29136.0,29703.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.01/76.19 29707[96:Res:53.1,29704.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.19 29711[96:Res:29707.0,61.1] always3(s35) || -> . % 76.01/76.19 29712[96:SSi:29711.0,724.0,29127.0,29142.0,29460.0,29703.0] || -> . % 76.01/76.19 29713[95:Spt:29712.0,29459.0,29460.0] || until2p7(s35)*+ -> . % 76.01/76.19 29714[95:Spt:29712.0,29459.1] || -> node4(s34)*. % 76.01/76.19 29716[95:MRR:816.0,29714.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.01/76.19 29727[95:Res:53.1,29716.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.01/76.19 29729[95:MRR:29727.0,29110.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.19 29731[95:Res:29729.0,61.1] always3(s35) || -> . % 76.01/76.19 29732[95:SSi:29731.0,724.0,29127.0,29142.0] || -> . % 76.01/76.19 29733[94:Spt:29732.0,29457.0,29458.0] || until2p7(s34)*+ -> . % 76.01/76.19 29734[94:Spt:29732.0,29457.1] || -> node4(s33)*. % 76.01/76.19 29735[94:MRR:29113.0,29734.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.01/76.19 29739[94:Res:53.1,29735.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.19 29742[94:Res:29739.0,61.1] always3(s33) || -> . % 76.01/76.19 29743[94:SSi:29742.0,722.0,29104.0,29116.0,29456.0,29734.0] || -> . % 76.01/76.19 29744[93:Spt:29743.0,29455.0,29456.0] || until2p7(s33)*+ -> . % 76.01/76.19 29745[93:Spt:29743.0,29455.1] || -> node4(s32)*. % 76.01/76.19 29747[93:MRR:822.0,29745.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.01/76.19 29758[93:Res:53.1,29747.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.01/76.19 29760[93:MRR:29758.0,29090.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.19 29762[93:Res:29760.0,61.1] always3(s33) || -> . % 76.01/76.19 29763[93:SSi:29762.0,722.0,29104.0,29116.0] || -> . % 76.01/76.19 29764[92:Spt:29763.0,29453.0,29454.0] || until2p7(s32)*+ -> . % 76.01/76.19 29765[92:Spt:29763.0,29453.1] || -> node4(s31)*. % 76.01/76.19 29766[92:MRR:29093.0,29765.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.01/76.19 29769[92:Res:53.1,29766.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.19 29772[92:Res:29769.0,61.1] always3(s31) || -> . % 76.01/76.19 29773[92:SSi:29772.0,720.0,29084.0,29096.0,29452.0,29765.0] || -> . % 76.01/76.19 29774[91:Spt:29773.0,29451.0,29452.0] || until2p7(s31)*+ -> . % 76.01/76.19 29775[91:Spt:29773.0,29451.1] || -> node4(s30)*. % 76.01/76.19 29777[91:MRR:828.0,29775.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.01/76.19 29789[91:Res:53.1,29777.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.01/76.19 29791[91:MRR:29789.0,29070.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.19 29793[91:Res:29791.0,61.1] always3(s31) || -> . % 76.01/76.19 29794[91:SSi:29793.0,720.0,29084.0,29096.0] || -> . % 76.01/76.19 29795[90:Spt:29794.0,29449.0,29450.0] || until2p7(s30)*+ -> . % 76.01/76.19 29796[90:Spt:29794.0,29449.1] || -> node4(s29)*. % 76.01/76.19 29797[90:MRR:29073.0,29796.0] || m_main_v_state(s29,c_ready)*+ -> . % 76.01/76.19 29800[90:Res:53.1,29797.0] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.19 29803[90:Res:29800.0,61.1] always3(s29) || -> . % 76.01/76.19 29804[90:SSi:29803.0,718.0,29064.0,29079.0,29448.0,29796.0] || -> . % 76.01/76.19 29805[89:Spt:29804.0,29447.0,29448.0] || until2p7(s29)*+ -> . % 76.01/76.19 29806[89:Spt:29804.0,29447.1] || -> node4(s28)*. % 76.01/76.19 29808[89:MRR:834.0,29806.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.01/76.19 29820[89:Res:53.1,29808.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.01/76.19 29825[90:Spt:29820.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 29827[90:Res:29825.0,61.1] always3(s28) || -> . % 76.01/76.19 29828[90:SSi:29827.0,717.0,29058.0,29063.0,29446.0,29806.0] || -> . % 76.01/76.19 29829[90:Spt:29828.0,29820.0,29825.0] || m_main_v_state(s28,c_busy)* -> . % 76.01/76.19 29830[90:Spt:29828.0,29820.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.19 29834[90:Res:29830.0,61.1] always3(s29) || -> . % 76.01/76.19 29835[90:SSi:29834.0,718.0,29064.0,29079.0] || -> . % 76.01/76.19 29836[88:Spt:29835.0,29445.0,29446.0] || until2p7(s28)*+ -> . % 76.01/76.19 29837[88:Spt:29835.0,29445.1] || -> node4(s27)*. % 76.01/76.19 29839[88:MRR:837.0,29837.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.01/76.19 29846[88:Res:53.1,29839.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.01/76.19 29848[89:Spt:29846.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.19 29850[89:Res:29848.0,61.1] always3(s27) || -> . % 76.01/76.19 29851[89:SSi:29850.0,716.0,29055.0,29057.0,29444.0,29837.0] || -> . % 76.01/76.19 29852[89:Spt:29851.0,29846.0,29848.0] || m_main_v_state(s27,c_busy)* -> . % 76.01/76.19 29853[89:Spt:29851.0,29846.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.19 29857[89:Res:29853.0,61.1] always3(s28) || -> . % 76.01/76.19 29858[89:SSi:29857.0,717.0,29058.0,29063.0] || -> . % 76.01/76.19 29859[87:Spt:29858.0,29441.0,29444.0] || until2p7(s27)*+ -> . % 76.01/76.19 29860[87:Spt:29858.0,29441.1] || -> node4(s26)*. % 76.01/76.19 29862[87:MRR:840.0,29860.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.01/76.19 29865[87:Res:53.1,29862.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.01/76.19 29867[87:MRR:29865.0,29426.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.19 29872[87:Res:29867.0,61.1] always3(s27) || -> . % 76.01/76.19 29873[87:SSi:29872.0,716.0,29055.0,29057.0] || -> . % 76.01/76.19 29874[84:Spt:29873.0,29270.2,29272.0] || xuntil6(s48)*+ -> . % 76.01/76.19 29875[84:Spt:29873.0,29270.0,29270.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.01/76.19 29876[84:Res:53.1,29875.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.01/76.19 29878[84:MRR:29876.0,29259.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.19 29880[84:Res:29878.0,61.1] always3(s49) || -> . % 76.01/76.19 29881[84:SSi:29880.0,50.0,738.0] || -> . % 76.01/76.19 29882[83:Spt:29881.0,29263.1,29268.0] || xuntil6(s47)* -> . % 76.01/76.19 29883[83:Spt:29881.0,29263.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.19 29886[83:Res:29883.0,61.1] always3(s47) || -> . % 76.01/76.19 29887[83:SSi:29886.0,736.0,29253.0] || -> . % 76.01/76.19 29888[81:Spt:29887.0,29244.2,29252.0] || xuntil6(s46)*+ -> . % 76.01/76.19 29889[81:Spt:29887.0,29244.0,29244.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.01/76.19 29890[81:Res:53.1,29889.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.01/76.19 29892[81:MRR:29890.0,29236.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.19 29895[81:Res:29892.0,61.1] always3(s47) || -> . % 76.01/76.19 29896[81:SSi:29895.0,736.0] || -> . % 76.01/76.19 29897[80:Spt:29896.0,29240.1,29242.0] || xuntil6(s45)* -> . % 76.01/76.19 29898[80:Spt:29896.0,29240.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.19 29901[80:Res:29898.0,61.1] always3(s45) || -> . % 76.01/76.19 29902[80:SSi:29901.0,734.0,29230.0] || -> . % 76.01/76.19 29903[78:Spt:29902.0,29224.2,29229.0] || xuntil6(s44)*+ -> . % 76.01/76.19 29904[78:Spt:29902.0,29224.0,29224.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.01/76.19 29905[78:Res:53.1,29904.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.01/76.19 29907[78:MRR:29905.0,29216.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.19 29909[78:Res:29907.0,61.1] always3(s45) || -> . % 76.01/76.19 29910[78:SSi:29909.0,734.0] || -> . % 76.01/76.19 29911[77:Spt:29910.0,29220.1,29222.0] || xuntil6(s43)* -> . % 76.01/76.19 29912[77:Spt:29910.0,29220.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.19 29915[77:Res:29912.0,61.1] always3(s43) || -> . % 76.01/76.19 29916[77:SSi:29915.0,732.0,29210.0] || -> . % 76.01/76.19 29917[75:Spt:29916.0,29207.2,29209.0] || xuntil6(s42)*+ -> . % 76.01/76.19 29918[75:Spt:29916.0,29207.0,29207.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.01/76.19 29919[75:Res:53.1,29918.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.01/76.19 29921[75:MRR:29919.0,29196.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.19 29924[75:Res:29921.0,61.1] always3(s43) || -> . % 76.01/76.19 29925[75:SSi:29924.0,732.0] || -> . % 76.01/76.19 29926[74:Spt:29925.0,29200.1,29205.0] || xuntil6(s41)* -> . % 76.01/76.19 29927[74:Spt:29925.0,29200.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.19 29930[74:Res:29927.0,61.1] always3(s41) || -> . % 76.01/76.19 29931[74:SSi:29930.0,730.0,29190.0] || -> . % 76.01/76.19 29932[72:Spt:29931.0,29181.2,29189.0] || xuntil6(s40)*+ -> . % 76.01/76.19 29933[72:Spt:29931.0,29181.0,29181.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.01/76.19 29934[72:Res:53.1,29933.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.01/76.19 29936[72:MRR:29934.0,29173.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.19 29938[72:Res:29936.0,61.1] always3(s41) || -> . % 76.01/76.19 29939[72:SSi:29938.0,730.0] || -> . % 76.01/76.19 29940[71:Spt:29939.0,29177.1,29179.0] || xuntil6(s39)* -> . % 76.01/76.19 29941[71:Spt:29939.0,29177.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.19 29944[71:Res:29941.0,61.1] always3(s39) || -> . % 76.01/76.19 29945[71:SSi:29944.0,728.0,29167.0] || -> . % 76.01/76.19 29946[69:Spt:29945.0,29161.2,29166.0] || xuntil6(s38)*+ -> . % 76.01/76.19 29947[69:Spt:29945.0,29161.0,29161.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.01/76.19 29948[69:Res:53.1,29947.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.01/76.19 29950[69:MRR:29948.0,29153.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.19 29952[69:Res:29950.0,61.1] always3(s39) || -> . % 76.01/76.19 29953[69:SSi:29952.0,728.0] || -> . % 76.01/76.19 29954[68:Spt:29953.0,29157.1,29159.0] || xuntil6(s37)* -> . % 76.01/76.19 29955[68:Spt:29953.0,29157.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.19 29958[68:Res:29955.0,61.1] always3(s37) || -> . % 76.01/76.19 29959[68:SSi:29958.0,726.0,29147.0] || -> . % 76.01/76.19 29960[66:Spt:29959.0,29144.2,29146.0] || xuntil6(s36)*+ -> . % 76.01/76.19 29961[66:Spt:29959.0,29144.0,29144.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.01/76.19 29962[66:Res:53.1,29961.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.01/76.19 29964[66:MRR:29962.0,29133.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.19 29966[66:Res:29964.0,61.1] always3(s37) || -> . % 76.01/76.19 29967[66:SSi:29966.0,726.0] || -> . % 76.01/76.19 29968[65:Spt:29967.0,29137.1,29142.0] || xuntil6(s35)* -> . % 76.01/76.19 29969[65:Spt:29967.0,29137.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.19 29972[65:Res:29969.0,61.1] always3(s35) || -> . % 76.01/76.19 29973[65:SSi:29972.0,724.0,29127.0] || -> . % 76.01/76.19 29974[63:Spt:29973.0,29118.2,29126.0] || xuntil6(s34)*+ -> . % 76.01/76.19 29975[63:Spt:29973.0,29118.0,29118.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.01/76.19 29976[63:Res:53.1,29975.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.01/76.19 29978[63:MRR:29976.0,29110.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.19 29980[63:Res:29978.0,61.1] always3(s35) || -> . % 76.01/76.19 29981[63:SSi:29980.0,724.0] || -> . % 76.01/76.19 29982[62:Spt:29981.0,29114.1,29116.0] || xuntil6(s33)* -> . % 76.01/76.19 29983[62:Spt:29981.0,29114.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.19 29986[62:Res:29983.0,61.1] always3(s33) || -> . % 76.01/76.19 29987[62:SSi:29986.0,722.0,29104.0] || -> . % 76.01/76.19 29988[60:Spt:29987.0,29098.2,29103.0] || xuntil6(s32)*+ -> . % 76.01/76.19 29989[60:Spt:29987.0,29098.0,29098.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.01/76.19 29990[60:Res:53.1,29989.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.01/76.19 29992[60:MRR:29990.0,29090.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.19 29994[60:Res:29992.0,61.1] always3(s33) || -> . % 76.01/76.19 29995[60:SSi:29994.0,722.0] || -> . % 76.01/76.19 29996[59:Spt:29995.0,29094.1,29096.0] || xuntil6(s31)* -> . % 76.01/76.19 29997[59:Spt:29995.0,29094.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.20 30000[59:Res:29997.0,61.1] always3(s31) || -> . % 76.01/76.20 30001[59:SSi:30000.0,720.0,29084.0] || -> . % 76.01/76.20 30002[57:Spt:30001.0,29081.2,29083.0] || xuntil6(s30)*+ -> . % 76.01/76.20 30003[57:Spt:30001.0,29081.0,29081.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.01/76.20 30004[57:Res:53.1,30003.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.01/76.20 30006[57:MRR:30004.0,29070.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.20 30008[57:Res:30006.0,61.1] always3(s31) || -> . % 76.01/76.20 30009[57:SSi:30008.0,720.0] || -> . % 76.01/76.20 30010[56:Spt:30009.0,29074.1,29079.0] || xuntil6(s29)* -> . % 76.01/76.20 30011[56:Spt:30009.0,29074.0] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.20 30014[56:Res:30011.0,61.1] always3(s29) || -> . % 76.01/76.20 30015[56:SSi:30014.0,718.0,29064.0] || -> . % 76.01/76.20 30016[54:Spt:30015.0,29059.2,29063.0] || xuntil6(s28)*+ -> . % 76.01/76.20 30017[54:Spt:30015.0,29059.0,29059.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.01/76.20 30018[54:Res:53.1,30017.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.01/76.20 30020[55:Spt:30018.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.20 30022[55:Res:30020.0,61.1] always3(s29) || -> . % 76.01/76.20 30023[55:SSi:30022.0,718.0] || -> . % 76.01/76.20 30024[55:Spt:30023.0,30018.1,30020.0] || m_main_v_state(s29,c_busy)* -> . % 76.01/76.20 30025[55:Spt:30023.0,30018.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.20 30028[55:Res:30025.0,61.1] always3(s28) || -> . % 76.01/76.20 30029[55:SSi:30028.0,717.0,29058.0] || -> . % 76.01/76.20 30030[53:Spt:30029.0,29056.2,29057.0] || xuntil6(s27)*+ -> . % 76.01/76.20 30031[53:Spt:30029.0,29056.0,29056.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.01/76.20 30032[53:Res:53.1,30031.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.01/76.20 30034[54:Spt:30032.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.20 30036[54:Res:30034.0,61.1] always3(s28) || -> . % 76.01/76.20 30037[54:SSi:30036.0,717.0] || -> . % 76.01/76.20 30038[54:Spt:30037.0,30032.1,30034.0] || m_main_v_state(s28,c_busy)* -> . % 76.01/76.20 30039[54:Spt:30037.0,30032.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.20 30042[54:Res:30039.0,61.1] always3(s27) || -> . % 76.01/76.20 30043[54:SSi:30042.0,716.0,29055.0] || -> . % 76.01/76.20 30044[52:Spt:30043.0,29050.2,29054.0] || xuntil6(s26)*+ -> . % 76.01/76.20 30045[52:Spt:30043.0,29050.0,29050.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.01/76.20 30046[52:Res:53.1,30045.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.01/76.20 30048[53:Spt:30046.1] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.20 30050[53:Res:30048.0,61.1] always3(s27) || -> . % 76.01/76.20 30051[53:SSi:30050.0,716.0] || -> . % 76.01/76.20 30052[53:Spt:30051.0,30046.1,30048.0] || m_main_v_state(s27,c_busy)* -> . % 76.01/76.20 30053[53:Spt:30051.0,30046.0] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.20 30056[53:Res:30053.0,61.1] always3(s26) || -> . % 76.01/76.20 30057[53:SSi:30056.0,715.0,29049.0] || -> . % 76.01/76.20 30058[51:Spt:30057.0,29047.2,29048.0] || xuntil6(s25)*+ -> . % 76.01/76.20 30059[51:Spt:30057.0,29047.0,29047.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.01/76.20 30060[51:Res:53.1,30059.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.01/76.20 30062[52:Spt:30060.0] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.20 30064[52:Res:30062.0,61.1] always3(s25) || -> . % 76.01/76.20 30065[52:SSi:30064.0,714.0,29046.0] || -> . % 76.01/76.20 30066[52:Spt:30065.0,30060.0,30062.0] || m_main_v_state(s25,c_busy)* -> . % 76.01/76.20 30067[52:Spt:30065.0,30060.1] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.20 30071[52:Res:30067.0,61.1] always3(s26) || -> . % 76.01/76.20 30072[52:SSi:30071.0,715.0] || -> . % 76.01/76.20 30073[50:Spt:30072.0,29041.2,29045.0] || xuntil6(s24)*+ -> . % 76.01/76.20 30074[50:Spt:30072.0,29041.0,29041.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.01/76.20 30075[50:Res:53.1,30074.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.01/76.20 30077[51:Spt:30075.0] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.20 30079[51:Res:30077.0,61.1] always3(s24) || -> . % 76.01/76.20 30080[51:SSi:30079.0,713.0,29040.0] || -> . % 76.01/76.20 30081[51:Spt:30080.0,30075.0,30077.0] || m_main_v_state(s24,c_busy)* -> . % 76.01/76.20 30082[51:Spt:30080.0,30075.1] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.20 30086[51:Res:30082.0,61.1] always3(s25) || -> . % 76.01/76.20 30087[51:SSi:30086.0,714.0] || -> . % 76.01/76.20 30088[49:Spt:30087.0,29038.2,29039.0] || xuntil6(s23)*+ -> . % 76.01/76.20 30089[49:Spt:30087.0,29038.0,29038.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.01/76.20 30090[49:Res:53.1,30089.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.01/76.20 30092[50:Spt:30090.0] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.20 30094[50:Res:30092.0,61.1] always3(s23) || -> . % 76.01/76.20 30095[50:SSi:30094.0,712.0,29037.0] || -> . % 76.01/76.20 30096[50:Spt:30095.0,30090.0,30092.0] || m_main_v_state(s23,c_busy)* -> . % 76.01/76.20 30097[50:Spt:30095.0,30090.1] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.20 30101[50:Res:30097.0,61.1] always3(s24) || -> . % 76.01/76.20 30102[50:SSi:30101.0,713.0] || -> . % 76.01/76.20 30103[48:Spt:30102.0,29032.2,29036.0] || xuntil6(s22)*+ -> . % 76.01/76.20 30104[48:Spt:30102.0,29032.0,29032.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.01/76.20 30105[48:Res:53.1,30104.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.01/76.20 30107[49:Spt:30105.0] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.20 30109[49:Res:30107.0,61.1] always3(s22) || -> . % 76.01/76.20 30110[49:SSi:30109.0,711.0,29031.0] || -> . % 76.01/76.20 30111[49:Spt:30110.0,30105.0,30107.0] || m_main_v_state(s22,c_busy)* -> . % 76.01/76.20 30112[49:Spt:30110.0,30105.1] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.20 30116[49:Res:30112.0,61.1] always3(s23) || -> . % 76.01/76.20 30117[49:SSi:30116.0,712.0] || -> . % 76.01/76.20 30118[47:Spt:30117.0,29029.2,29030.0] || xuntil6(s21)*+ -> . % 76.01/76.20 30119[47:Spt:30117.0,29029.0,29029.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.01/76.20 30120[47:Res:53.1,30119.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.01/76.20 30125[48:Spt:30120.0] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.20 30127[48:Res:30125.0,61.1] always3(s21) || -> . % 76.01/76.20 30128[48:SSi:30127.0,710.0,29028.0] || -> . % 76.01/76.20 30129[48:Spt:30128.0,30120.0,30125.0] || m_main_v_state(s21,c_busy)* -> . % 76.01/76.20 30130[48:Spt:30128.0,30120.1] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.20 30134[48:Res:30130.0,61.1] always3(s22) || -> . % 76.01/76.20 30135[48:SSi:30134.0,711.0] || -> . % 76.01/76.20 30136[46:Spt:30135.0,29023.2,29027.0] || xuntil6(s20)*+ -> . % 76.01/76.20 30137[46:Spt:30135.0,29023.0,29023.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.01/76.20 30138[46:Res:53.1,30137.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.01/76.20 30140[47:Spt:30138.0] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.20 30142[47:Res:30140.0,61.1] always3(s20) || -> . % 76.01/76.20 30143[47:SSi:30142.0,709.0,29022.0] || -> . % 76.01/76.20 30144[47:Spt:30143.0,30138.0,30140.0] || m_main_v_state(s20,c_busy)* -> . % 76.01/76.20 30145[47:Spt:30143.0,30138.1] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.20 30149[47:Res:30145.0,61.1] always3(s21) || -> . % 76.01/76.20 30150[47:SSi:30149.0,710.0] || -> . % 76.01/76.20 30151[45:Spt:30150.0,29020.2,29021.0] || xuntil6(s19)*+ -> . % 76.01/76.20 30152[45:Spt:30150.0,29020.0,29020.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.01/76.20 30153[45:Res:53.1,30152.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.01/76.20 30155[46:Spt:30153.0] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.20 30157[46:Res:30155.0,61.1] always3(s19) || -> . % 76.01/76.20 30158[46:SSi:30157.0,708.0,29019.0] || -> . % 76.01/76.20 30159[46:Spt:30158.0,30153.0,30155.0] || m_main_v_state(s19,c_busy)* -> . % 76.01/76.20 30160[46:Spt:30158.0,30153.1] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.20 30164[46:Res:30160.0,61.1] always3(s20) || -> . % 76.01/76.20 30165[46:SSi:30164.0,709.0] || -> . % 76.01/76.20 30166[44:Spt:30165.0,29014.2,29018.0] || xuntil6(s18)*+ -> . % 76.01/76.20 30167[44:Spt:30165.0,29014.0,29014.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.01/76.20 30168[44:Res:53.1,30167.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.01/76.20 30173[45:Spt:30168.0] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.20 30175[45:Res:30173.0,61.1] always3(s18) || -> . % 76.01/76.20 30176[45:SSi:30175.0,707.0,29013.0] || -> . % 76.01/76.20 30177[45:Spt:30176.0,30168.0,30173.0] || m_main_v_state(s18,c_busy)* -> . % 76.01/76.20 30178[45:Spt:30176.0,30168.1] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.20 30182[45:Res:30178.0,61.1] always3(s19) || -> . % 76.01/76.20 30183[45:SSi:30182.0,708.0] || -> . % 76.01/76.20 30184[43:Spt:30183.0,29011.2,29012.0] || xuntil6(s17)*+ -> . % 76.01/76.20 30185[43:Spt:30183.0,29011.0,29011.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.01/76.20 30186[43:Res:53.1,30185.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.01/76.20 30188[44:Spt:30186.0] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.20 30190[44:Res:30188.0,61.1] always3(s17) || -> . % 76.01/76.20 30191[44:SSi:30190.0,706.0,29010.0] || -> . % 76.01/76.20 30192[44:Spt:30191.0,30186.0,30188.0] || m_main_v_state(s17,c_busy)* -> . % 76.01/76.20 30193[44:Spt:30191.0,30186.1] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.20 30197[44:Res:30193.0,61.1] always3(s18) || -> . % 76.01/76.20 30198[44:SSi:30197.0,707.0] || -> . % 76.01/76.20 30199[42:Spt:30198.0,29005.2,29009.0] || xuntil6(s16)*+ -> . % 76.01/76.20 30200[42:Spt:30198.0,29005.0,29005.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.01/76.20 30201[42:Res:53.1,30200.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.01/76.20 30203[43:Spt:30201.0] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.20 30205[43:Res:30203.0,61.1] always3(s16) || -> . % 76.01/76.20 30206[43:SSi:30205.0,705.0,29004.0] || -> . % 76.01/76.20 30207[43:Spt:30206.0,30201.0,30203.0] || m_main_v_state(s16,c_busy)* -> . % 76.01/76.20 30208[43:Spt:30206.0,30201.1] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.20 30212[43:Res:30208.0,61.1] always3(s17) || -> . % 76.01/76.20 30213[43:SSi:30212.0,706.0] || -> . % 76.01/76.20 30214[41:Spt:30213.0,29002.2,29003.0] || xuntil6(s15)*+ -> . % 76.01/76.20 30215[41:Spt:30213.0,29002.0,29002.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.01/76.20 30216[41:Res:53.1,30215.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.01/76.20 30221[42:Spt:30216.0] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.20 30223[42:Res:30221.0,61.1] always3(s15) || -> . % 76.01/76.20 30224[42:SSi:30223.0,704.0,29001.0] || -> . % 76.01/76.20 30225[42:Spt:30224.0,30216.0,30221.0] || m_main_v_state(s15,c_busy)* -> . % 76.01/76.20 30226[42:Spt:30224.0,30216.1] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.20 30230[42:Res:30226.0,61.1] always3(s16) || -> . % 76.01/76.20 30231[42:SSi:30230.0,705.0] || -> . % 76.01/76.20 30232[40:Spt:30231.0,28996.2,29000.0] || xuntil6(s14)*+ -> . % 76.01/76.20 30233[40:Spt:30231.0,28996.0,28996.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.01/76.20 30234[40:Res:53.1,30233.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.01/76.20 30236[41:Spt:30234.0] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.20 30238[41:Res:30236.0,61.1] always3(s14) || -> . % 76.01/76.20 30239[41:SSi:30238.0,703.0,28995.0] || -> . % 76.01/76.20 30240[41:Spt:30239.0,30234.0,30236.0] || m_main_v_state(s14,c_busy)* -> . % 76.01/76.20 30241[41:Spt:30239.0,30234.1] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.20 30245[41:Res:30241.0,61.1] always3(s15) || -> . % 76.01/76.20 30246[41:SSi:30245.0,704.0] || -> . % 76.01/76.20 30247[39:Spt:30246.0,28993.2,28994.0] || xuntil6(s13)*+ -> . % 76.01/76.20 30248[39:Spt:30246.0,28993.0,28993.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.01/76.20 30249[39:Res:53.1,30248.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.01/76.20 30251[40:Spt:30249.0] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.20 30253[40:Res:30251.0,61.1] always3(s13) || -> . % 76.01/76.20 30254[40:SSi:30253.0,702.0,28992.0] || -> . % 76.01/76.20 30255[40:Spt:30254.0,30249.0,30251.0] || m_main_v_state(s13,c_busy)* -> . % 76.01/76.20 30256[40:Spt:30254.0,30249.1] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.20 30260[40:Res:30256.0,61.1] always3(s14) || -> . % 76.01/76.20 30261[40:SSi:30260.0,703.0] || -> . % 76.01/76.20 30262[38:Spt:30261.0,28987.2,28991.0] || xuntil6(s12)*+ -> . % 76.01/76.20 30263[38:Spt:30261.0,28987.0,28987.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.01/76.20 30264[38:Res:53.1,30263.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.01/76.20 30269[39:Spt:30264.0] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.20 30271[39:Res:30269.0,61.1] always3(s12) || -> . % 76.01/76.20 30272[39:SSi:30271.0,701.0,28986.0] || -> . % 76.01/76.20 30273[39:Spt:30272.0,30264.0,30269.0] || m_main_v_state(s12,c_busy)* -> . % 76.01/76.20 30274[39:Spt:30272.0,30264.1] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.20 30278[39:Res:30274.0,61.1] always3(s13) || -> . % 76.01/76.20 30279[39:SSi:30278.0,702.0] || -> . % 76.01/76.20 30280[37:Spt:30279.0,28984.2,28985.0] || xuntil6(s11)*+ -> . % 76.01/76.20 30281[37:Spt:30279.0,28984.0,28984.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.01/76.20 30282[37:Res:53.1,30281.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.01/76.20 30284[38:Spt:30282.0] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.20 30286[38:Res:30284.0,61.1] always3(s11) || -> . % 76.01/76.20 30287[38:SSi:30286.0,700.0,28983.0] || -> . % 76.01/76.20 30288[38:Spt:30287.0,30282.0,30284.0] || m_main_v_state(s11,c_busy)* -> . % 76.01/76.20 30289[38:Spt:30287.0,30282.1] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.20 30293[38:Res:30289.0,61.1] always3(s12) || -> . % 76.01/76.20 30294[38:SSi:30293.0,701.0] || -> . % 76.01/76.20 30295[36:Spt:30294.0,28978.2,28982.0] || xuntil6(s10)*+ -> . % 76.01/76.20 30296[36:Spt:30294.0,28978.0,28978.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.01/76.20 30297[36:Res:53.1,30296.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.01/76.20 30299[37:Spt:30297.0] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.20 30301[37:Res:30299.0,61.1] always3(s10) || -> . % 76.01/76.20 30302[37:SSi:30301.0,699.0,28977.0] || -> . % 76.01/76.20 30303[37:Spt:30302.0,30297.0,30299.0] || m_main_v_state(s10,c_busy)* -> . % 76.01/76.20 30304[37:Spt:30302.0,30297.1] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.20 30308[37:Res:30304.0,61.1] always3(s11) || -> . % 76.01/76.20 30309[37:SSi:30308.0,700.0] || -> . % 76.01/76.20 30310[35:Spt:30309.0,28975.2,28976.0] || xuntil6(s9)*+ -> . % 76.01/76.20 30311[35:Spt:30309.0,28975.0,28975.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.01/76.20 30312[35:Res:53.1,30311.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.01/76.20 30317[36:Spt:30312.0] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.20 30319[36:Res:30317.0,61.1] always3(s9) || -> . % 76.01/76.20 30320[36:SSi:30319.0,698.0,28974.0] || -> . % 76.01/76.20 30321[36:Spt:30320.0,30312.0,30317.0] || m_main_v_state(s9,c_busy)* -> . % 76.01/76.20 30322[36:Spt:30320.0,30312.1] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.20 30326[36:Res:30322.0,61.1] always3(s10) || -> . % 76.01/76.20 30327[36:SSi:30326.0,699.0] || -> . % 76.01/76.20 30328[34:Spt:30327.0,28969.2,28973.0] || xuntil6(s8)*+ -> . % 76.01/76.20 30329[34:Spt:30327.0,28969.0,28969.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.01/76.20 30330[34:Res:53.1,30329.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.01/76.20 30332[35:Spt:30330.0] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.20 30334[35:Res:30332.0,61.1] always3(s8) || -> . % 76.01/76.20 30335[35:SSi:30334.0,697.0,28968.0] || -> . % 76.01/76.20 30336[35:Spt:30335.0,30330.0,30332.0] || m_main_v_state(s8,c_busy)* -> . % 76.01/76.20 30337[35:Spt:30335.0,30330.1] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.20 30341[35:Res:30337.0,61.1] always3(s9) || -> . % 76.01/76.20 30342[35:SSi:30341.0,698.0] || -> . % 76.01/76.20 30343[33:Spt:30342.0,28966.2,28967.0] || xuntil6(s7)*+ -> . % 76.01/76.20 30344[33:Spt:30342.0,28966.0,28966.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.01/76.20 30345[33:Res:53.1,30344.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.01/76.20 30347[34:Spt:30345.0] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.20 30349[34:Res:30347.0,61.1] always3(s7) || -> . % 76.01/76.20 30350[34:SSi:30349.0,696.0,28965.0] || -> . % 76.01/76.20 30351[34:Spt:30350.0,30345.0,30347.0] || m_main_v_state(s7,c_busy)* -> . % 76.01/76.20 30352[34:Spt:30350.0,30345.1] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.20 30356[34:Res:30352.0,61.1] always3(s8) || -> . % 76.01/76.20 30357[34:SSi:30356.0,697.0] || -> . % 76.01/76.20 30358[32:Spt:30357.0,28960.2,28964.0] || xuntil6(s6)*+ -> . % 76.01/76.20 30359[32:Spt:30357.0,28960.0,28960.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.01/76.20 30360[32:Res:53.1,30359.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.01/76.20 30365[33:Spt:30360.0] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.20 30367[33:Res:30365.0,61.1] always3(s6) || -> . % 76.01/76.20 30368[33:SSi:30367.0,695.0,28959.0] || -> . % 76.01/76.20 30369[33:Spt:30368.0,30360.0,30365.0] || m_main_v_state(s6,c_busy)* -> . % 76.01/76.20 30370[33:Spt:30368.0,30360.1] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.20 30374[33:Res:30370.0,61.1] always3(s7) || -> . % 76.01/76.20 30375[33:SSi:30374.0,696.0] || -> . % 76.01/76.20 30376[31:Spt:30375.0,28957.2,28958.0] || xuntil6(s5)*+ -> . % 76.01/76.20 30377[31:Spt:30375.0,28957.0,28957.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.01/76.20 30378[31:Res:53.1,30377.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.01/76.20 30380[32:Spt:30378.0] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.20 30382[32:Res:30380.0,61.1] always3(s5) || -> . % 76.01/76.20 30383[32:SSi:30382.0,694.0,28956.0] || -> . % 76.01/76.20 30384[32:Spt:30383.0,30378.0,30380.0] || m_main_v_state(s5,c_busy)* -> . % 76.01/76.20 30385[32:Spt:30383.0,30378.1] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.20 30389[32:Res:30385.0,61.1] always3(s6) || -> . % 76.01/76.20 30390[32:SSi:30389.0,695.0] || -> . % 76.01/76.20 30391[30:Spt:30390.0,28951.2,28955.0] || xuntil6(s4)*+ -> . % 76.01/76.20 30392[30:Spt:30390.0,28951.0,28951.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.01/76.20 30393[30:Res:53.1,30392.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.01/76.20 30395[31:Spt:30393.0] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.20 30397[31:Res:30395.0,61.1] always3(s4) || -> . % 76.01/76.20 30398[31:SSi:30397.0,693.0,28950.0] || -> . % 76.01/76.20 30399[31:Spt:30398.0,30393.0,30395.0] || m_main_v_state(s4,c_busy)* -> . % 76.01/76.20 30400[31:Spt:30398.0,30393.1] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.20 30404[31:Res:30400.0,61.1] always3(s5) || -> . % 76.01/76.20 30405[31:SSi:30404.0,694.0] || -> . % 76.01/76.20 30406[29:Spt:30405.0,28948.2,28949.0] || xuntil6(s3)*+ -> . % 76.01/76.20 30407[29:Spt:30405.0,28948.0,28948.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.01/76.20 30408[29:Res:53.1,30407.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.01/76.20 30413[30:Spt:30408.0] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.20 30415[30:Res:30413.0,61.1] always3(s3) || -> . % 76.01/76.20 30416[30:SSi:30415.0,692.0,28947.0] || -> . % 76.01/76.20 30417[30:Spt:30416.0,30408.0,30413.0] || m_main_v_state(s3,c_busy)* -> . % 76.01/76.20 30418[30:Spt:30416.0,30408.1] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.20 30422[30:Res:30418.0,61.1] always3(s4) || -> . % 76.01/76.20 30423[30:SSi:30422.0,693.0] || -> . % 76.01/76.20 30424[28:Spt:30423.0,28942.2,28946.0] || xuntil6(s2)*+ -> . % 76.01/76.20 30425[28:Spt:30423.0,28942.0,28942.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.01/76.20 30426[28:Res:53.1,30425.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.01/76.20 30428[29:Spt:30426.0] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.20 30430[29:Res:30428.0,61.1] always3(s2) || -> . % 76.01/76.20 30431[29:SSi:30430.0,691.0,28941.0] || -> . % 76.01/76.20 30432[29:Spt:30431.0,30426.0,30428.0] || m_main_v_state(s2,c_busy)* -> . % 76.01/76.20 30433[29:Spt:30431.0,30426.1] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.20 30437[29:Res:30433.0,61.1] always3(s3) || -> . % 76.01/76.20 30438[29:SSi:30437.0,692.0] || -> . % 76.01/76.20 30439[27:Spt:30438.0,28936.2,28940.0] || xuntil6(s1)*+ -> . % 76.01/76.20 30440[27:Spt:30438.0,28936.0,28936.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.01/76.20 30441[27:Res:53.1,30440.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.01/76.20 30443[28:Spt:30441.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.20 30445[28:Res:30443.0,61.1] always3(s1) || -> . % 76.01/76.20 30446[28:SSi:30445.0,690.0,28935.0] || -> . % 76.01/76.20 30447[28:Spt:30446.0,30441.0,30443.0] || m_main_v_state(s1,c_busy)* -> . % 76.01/76.20 30448[28:Spt:30446.0,30441.1] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.20 30453[28:Res:30448.0,61.1] always3(s2) || -> . % 76.01/76.20 30454[28:SSi:30453.0,691.0] || -> . % 76.01/76.20 30455[26:Spt:30454.0,74.0,28934.0] || xuntil6(s0)*+ -> . % 76.01/76.20 30456[26:Spt:30454.0,74.1] || -> node4(s0)*. % 76.01/76.20 30457[26:MRR:758.1,30455.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.20 30459[26:Res:30457.0,61.1] always3(s1) || -> . % 76.01/76.20 30460[26:SSi:30459.0,690.0] || -> . % 76.01/76.20 30461[25:Spt:30460.0,28924.0,28928.0] || trans(s49,s26)*+ -> . % 76.01/76.20 30462[25:Spt:30460.0,28924.1,28924.2,28924.3,28924.4,28924.5,28924.6,28924.7,28924.8,28924.9,28924.10,28924.11,28924.12,28924.13,28924.14,28924.15,28924.16,28924.17,28924.18,28924.19,28924.20,28924.21,28924.22,28924.23,28924.24,28924.25,28924.26] || -> trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.01/76.20 30464[25:MRR:28925.0,30461.0] || -> trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.01/76.20 30465[25:MRR:28927.1,30461.0] xuntil6(s49) || -> trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.01/76.20 30466[26:Spt:30462.0] || -> trans(s49,s25)*. % 76.01/76.20 30467[26:Res:30466.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s25)*. % 76.01/76.20 30469[26:Res:30466.0,60.0] || -> node2(s49,s25)*. % 76.01/76.20 30470[26:SSi:30467.1,50.0,738.0] xuntil6(s49) || -> until2p7(s25)*. % 76.01/76.20 30471[26:Res:30469.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)*. % 76.01/76.20 30472[27:Spt:74.0] || -> xuntil6(s0)*. % 76.01/76.20 30473[27:MRR:176.0,30472.0] || -> until5(s1)*. % 76.01/76.20 30474[27:MRR:29376.0,30473.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.20 30478[28:Spt:30474.2] || -> xuntil6(s1)*. % 76.01/76.20 30479[28:MRR:175.0,30478.0] || -> until5(s2)*. % 76.01/76.20 30480[28:MRR:29372.0,30479.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.20 30484[29:Spt:30480.2] || -> xuntil6(s2)*. % 76.01/76.20 30485[29:MRR:174.0,30484.0] || -> until5(s3)*. % 76.01/76.20 30486[29:MRR:29368.0,30485.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.20 30487[30:Spt:30486.2] || -> xuntil6(s3)*. % 76.01/76.20 30488[30:MRR:173.0,30487.0] || -> until5(s4)*. % 76.01/76.20 30489[30:MRR:29364.0,30488.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.20 30493[31:Spt:30489.2] || -> xuntil6(s4)*. % 76.01/76.20 30494[31:MRR:172.0,30493.0] || -> until5(s5)*. % 76.01/76.20 30495[31:MRR:29363.0,30494.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.20 30496[32:Spt:30495.2] || -> xuntil6(s5)*. % 76.01/76.20 30497[32:MRR:171.0,30496.0] || -> until5(s6)*. % 76.01/76.20 30498[32:MRR:29356.0,30497.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.20 30502[33:Spt:30498.2] || -> xuntil6(s6)*. % 76.01/76.20 30503[33:MRR:170.0,30502.0] || -> until5(s7)*. % 76.01/76.20 30504[33:MRR:29352.0,30503.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.20 30505[34:Spt:30504.2] || -> xuntil6(s7)*. % 76.01/76.20 30506[34:MRR:169.0,30505.0] || -> until5(s8)*. % 76.01/76.20 30507[34:MRR:29348.0,30506.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.20 30511[35:Spt:30507.2] || -> xuntil6(s8)*. % 76.01/76.20 30512[35:MRR:168.0,30511.0] || -> until5(s9)*. % 76.01/76.20 30513[35:MRR:29344.0,30512.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.20 30514[36:Spt:30513.2] || -> xuntil6(s9)*. % 76.01/76.20 30515[36:MRR:167.0,30514.0] || -> until5(s10)*. % 76.01/76.20 30516[36:MRR:29343.0,30515.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.20 30520[37:Spt:30516.2] || -> xuntil6(s10)*. % 76.01/76.20 30521[37:MRR:166.0,30520.0] || -> until5(s11)*. % 76.01/76.20 30522[37:MRR:29336.0,30521.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.20 30523[38:Spt:30522.2] || -> xuntil6(s11)*. % 76.01/76.20 30524[38:MRR:165.0,30523.0] || -> until5(s12)*. % 76.01/76.20 30525[38:MRR:29332.0,30524.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.20 30529[39:Spt:30525.2] || -> xuntil6(s12)*. % 76.01/76.20 30530[39:MRR:164.0,30529.0] || -> until5(s13)*. % 76.01/76.20 30531[39:MRR:29328.0,30530.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.20 30532[40:Spt:30531.2] || -> xuntil6(s13)*. % 76.01/76.20 30533[40:MRR:163.0,30532.0] || -> until5(s14)*. % 76.01/76.20 30534[40:MRR:29324.0,30533.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.20 30538[41:Spt:30534.2] || -> xuntil6(s14)*. % 76.01/76.20 30539[41:MRR:162.0,30538.0] || -> until5(s15)*. % 76.01/76.20 30540[41:MRR:29323.0,30539.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.20 30541[42:Spt:30540.2] || -> xuntil6(s15)*. % 76.01/76.20 30542[42:MRR:161.0,30541.0] || -> until5(s16)*. % 76.01/76.20 30543[42:MRR:29316.0,30542.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.20 30547[43:Spt:30543.2] || -> xuntil6(s16)*. % 76.01/76.20 30548[43:MRR:160.0,30547.0] || -> until5(s17)*. % 76.01/76.20 30549[43:MRR:29312.0,30548.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.20 30550[44:Spt:30549.2] || -> xuntil6(s17)*. % 76.01/76.20 30551[44:MRR:159.0,30550.0] || -> until5(s18)*. % 76.01/76.20 30552[44:MRR:29308.0,30551.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.20 30556[45:Spt:30552.2] || -> xuntil6(s18)*. % 76.01/76.20 30557[45:MRR:158.0,30556.0] || -> until5(s19)*. % 76.01/76.20 30558[45:MRR:29304.0,30557.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.20 30559[46:Spt:30558.2] || -> xuntil6(s19)*. % 76.01/76.20 30560[46:MRR:157.0,30559.0] || -> until5(s20)*. % 76.01/76.20 30561[46:MRR:29303.0,30560.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.20 30565[47:Spt:30561.2] || -> xuntil6(s20)*. % 76.01/76.20 30566[47:MRR:156.0,30565.0] || -> until5(s21)*. % 76.01/76.20 30567[47:MRR:29296.0,30566.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.20 30568[48:Spt:30567.2] || -> xuntil6(s21)*. % 76.01/76.20 30569[48:MRR:155.0,30568.0] || -> until5(s22)*. % 76.01/76.20 30570[48:MRR:29292.0,30569.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.20 30574[49:Spt:30570.2] || -> xuntil6(s22)*. % 76.01/76.20 30575[49:MRR:154.0,30574.0] || -> until5(s23)*. % 76.01/76.20 30576[49:MRR:29288.0,30575.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.20 30577[50:Spt:30576.2] || -> xuntil6(s23)*. % 76.01/76.20 30578[50:MRR:153.0,30577.0] || -> until5(s24)*. % 76.01/76.20 30579[50:MRR:29284.0,30578.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.20 30583[51:Spt:30579.2] || -> xuntil6(s24)*. % 76.01/76.20 30584[51:MRR:152.0,30583.0] || -> until5(s25)*. % 76.01/76.20 30585[51:MRR:29283.0,30584.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.20 30586[52:Spt:30585.2] || -> xuntil6(s25)*. % 76.01/76.20 30587[52:MRR:151.0,30586.0] || -> until5(s26)*. % 76.01/76.20 30588[52:MRR:29276.0,30587.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.20 30592[53:Spt:30588.2] || -> xuntil6(s26)*. % 76.01/76.20 30593[53:MRR:150.0,30592.0] || -> until5(s27)*. % 76.01/76.20 30594[53:MRR:29275.0,30593.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.20 30595[54:Spt:30594.2] || -> xuntil6(s27)*. % 76.01/76.20 30596[54:MRR:149.0,30595.0] || -> until5(s28)*. % 76.01/76.20 30597[54:MRR:29274.0,30596.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.20 30601[55:Spt:30597.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.20 30603[55:Res:30601.0,61.1] always3(s29) || -> . % 76.01/76.20 30604[55:SSi:30603.0,718.0] || -> . % 76.01/76.20 30605[55:Spt:30604.0,30597.1,30601.0] || m_main_v_state(s29,c_busy)*+ -> . % 76.01/76.20 30606[55:Spt:30604.0,30597.0,30597.2] || m_main_v_state(s28,c_ready)*+ -> xuntil6(s28). % 76.01/76.20 30608[55:MRR:834.2,30605.0] node4(s28) || m_main_v_state(s28,c_ready)* -> . % 76.01/76.20 30609[55:Res:53.1,30606.0] || -> m_main_v_state(s28,c_busy)* xuntil6(s28). % 76.01/76.20 30611[56:Spt:30609.1] || -> xuntil6(s28)*. % 76.01/76.20 30612[56:MRR:148.0,30611.0] || -> until5(s29)*. % 76.01/76.20 30613[56:MRR:26398.0,30612.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.20 30618[57:Spt:30613.2] || -> xuntil6(s29)*. % 76.01/76.20 30619[57:MRR:147.0,30618.0] || -> until5(s30)*. % 76.01/76.20 30620[57:MRR:29383.0,30619.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.20 30621[58:Spt:30620.1] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.20 30623[58:Res:30621.0,61.1] always3(s31) || -> . % 76.01/76.20 30624[58:SSi:30623.0,720.0] || -> . % 76.01/76.20 30625[58:Spt:30624.0,30620.1,30621.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.01/76.20 30626[58:Spt:30624.0,30620.0,30620.2] || m_main_v_state(s30,c_ready)*+ -> xuntil6(s30). % 76.01/76.20 30628[58:MRR:828.2,30625.0] node4(s30) || m_main_v_state(s30,c_ready)* -> . % 76.01/76.20 30629[58:Res:53.1,30626.0] || -> m_main_v_state(s30,c_busy)* xuntil6(s30). % 76.01/76.20 30631[59:Spt:30629.1] || -> xuntil6(s30)*. % 76.01/76.20 30632[59:MRR:146.0,30631.0] || -> until5(s31)*. % 76.01/76.20 30633[59:MRR:26402.0,30632.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.20 30641[60:Spt:30633.2] || -> xuntil6(s31)*. % 76.01/76.20 30642[60:MRR:145.0,30641.0] || -> until5(s32)*. % 76.01/76.20 30643[60:MRR:29387.0,30642.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.20 30644[61:Spt:30643.1] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.20 30646[61:Res:30644.0,61.1] always3(s33) || -> . % 76.01/76.20 30647[61:SSi:30646.0,722.0] || -> . % 76.01/76.20 30648[61:Spt:30647.0,30643.1,30644.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.01/76.20 30649[61:Spt:30647.0,30643.0,30643.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 76.01/76.20 30651[61:MRR:822.2,30648.0] node4(s32) || m_main_v_state(s32,c_ready)* -> . % 76.01/76.20 30652[61:Res:53.1,30649.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 76.01/76.20 30657[62:Spt:30652.1] || -> xuntil6(s32)*. % 76.01/76.20 30658[62:MRR:144.0,30657.0] || -> until5(s33)*. % 76.01/76.20 30659[62:MRR:26409.0,30658.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.20 30661[63:Spt:30659.2] || -> xuntil6(s33)*. % 76.01/76.20 30662[63:MRR:143.0,30661.0] || -> until5(s34)*. % 76.01/76.20 30663[63:MRR:29394.0,30662.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.20 30664[64:Spt:30663.1] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.20 30666[64:Res:30664.0,61.1] always3(s35) || -> . % 76.01/76.20 30667[64:SSi:30666.0,724.0] || -> . % 76.01/76.20 30668[64:Spt:30667.0,30663.1,30664.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.01/76.20 30669[64:Spt:30667.0,30663.0,30663.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 76.01/76.20 30671[64:MRR:816.2,30668.0] node4(s34) || m_main_v_state(s34,c_ready)* -> . % 76.01/76.20 30672[64:Res:53.1,30669.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 76.01/76.20 30674[65:Spt:30672.1] || -> xuntil6(s34)*. % 76.01/76.20 30675[65:MRR:142.0,30674.0] || -> until5(s35)*. % 76.01/76.20 30676[65:MRR:26410.0,30675.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.20 30681[66:Spt:30676.2] || -> xuntil6(s35)*. % 76.01/76.20 30682[66:MRR:141.0,30681.0] || -> until5(s36)*. % 76.01/76.20 30683[66:MRR:29395.0,30682.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.20 30684[67:Spt:30683.1] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.20 30686[67:Res:30684.0,61.1] always3(s37) || -> . % 76.01/76.20 30687[67:SSi:30686.0,726.0] || -> . % 76.01/76.20 30688[67:Spt:30687.0,30683.1,30684.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.01/76.20 30689[67:Spt:30687.0,30683.0,30683.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 76.01/76.20 30691[67:MRR:810.2,30688.0] node4(s36) || m_main_v_state(s36,c_ready)* -> . % 76.01/76.20 30692[67:Res:53.1,30689.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 76.01/76.20 30694[68:Spt:30692.1] || -> xuntil6(s36)*. % 76.01/76.20 30695[68:MRR:140.0,30694.0] || -> until5(s37)*. % 76.01/76.20 30696[68:MRR:26414.0,30695.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.20 30704[69:Spt:30696.2] || -> xuntil6(s37)*. % 76.01/76.20 30705[69:MRR:139.0,30704.0] || -> until5(s38)*. % 76.01/76.20 30706[69:MRR:29399.0,30705.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.20 30707[70:Spt:30706.1] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.20 30709[70:Res:30707.0,61.1] always3(s39) || -> . % 76.01/76.20 30710[70:SSi:30709.0,728.0] || -> . % 76.01/76.20 30711[70:Spt:30710.0,30706.1,30707.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.01/76.20 30712[70:Spt:30710.0,30706.0,30706.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 76.01/76.20 30714[70:MRR:804.2,30711.0] node4(s38) || m_main_v_state(s38,c_ready)* -> . % 76.01/76.20 30715[70:Res:53.1,30712.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 76.01/76.20 30720[71:Spt:30715.1] || -> xuntil6(s38)*. % 76.01/76.20 30721[71:MRR:138.0,30720.0] || -> until5(s39)*. % 76.01/76.20 30722[71:MRR:26418.0,30721.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.20 30724[72:Spt:30722.2] || -> xuntil6(s39)*. % 76.01/76.20 30725[72:MRR:137.0,30724.0] || -> until5(s40)*. % 76.01/76.20 30726[72:MRR:29403.0,30725.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.01/76.20 30727[73:Spt:30726.1] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.20 30729[73:Res:30727.0,61.1] always3(s41) || -> . % 76.01/76.20 30730[73:SSi:30729.0,730.0] || -> . % 76.01/76.20 30731[73:Spt:30730.0,30726.1,30727.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.01/76.20 30732[73:Spt:30730.0,30726.0,30726.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 76.01/76.20 30734[73:MRR:798.2,30731.0] node4(s40) || m_main_v_state(s40,c_ready)* -> . % 76.01/76.20 30735[73:Res:53.1,30732.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 76.01/76.20 30737[74:Spt:30735.1] || -> xuntil6(s40)*. % 76.01/76.20 30738[74:MRR:136.0,30737.0] || -> until5(s41)*. % 76.01/76.20 30739[74:MRR:26422.0,30738.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.20 30744[75:Spt:30739.2] || -> xuntil6(s41)*. % 76.01/76.20 30745[75:MRR:135.0,30744.0] || -> until5(s42)*. % 76.01/76.20 30746[75:MRR:29407.0,30745.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.01/76.20 30747[76:Spt:30746.1] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.20 30749[76:Res:30747.0,61.1] always3(s43) || -> . % 76.01/76.20 30750[76:SSi:30749.0,732.0] || -> . % 76.01/76.20 30751[76:Spt:30750.0,30746.1,30747.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.01/76.20 30752[76:Spt:30750.0,30746.0,30746.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 76.01/76.20 30754[76:MRR:792.2,30751.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 76.01/76.20 30755[76:Res:53.1,30752.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 76.01/76.20 30757[77:Spt:30755.1] || -> xuntil6(s42)*. % 76.01/76.20 30758[77:MRR:134.0,30757.0] || -> until5(s43)*. % 76.01/76.20 30759[77:MRR:26429.0,30758.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.20 30767[78:Spt:30759.2] || -> xuntil6(s43)*. % 76.01/76.20 30768[78:MRR:133.0,30767.0] || -> until5(s44)*. % 76.01/76.20 30769[78:MRR:29414.0,30768.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.01/76.20 30770[79:Spt:30769.1] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.20 30772[79:Res:30770.0,61.1] always3(s45) || -> . % 76.01/76.20 30773[79:SSi:30772.0,734.0] || -> . % 76.01/76.20 30774[79:Spt:30773.0,30769.1,30770.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.01/76.20 30775[79:Spt:30773.0,30769.0,30769.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 76.01/76.20 30777[79:MRR:786.2,30774.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 76.01/76.20 30778[79:Res:53.1,30775.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 76.01/76.20 30783[80:Spt:30778.1] || -> xuntil6(s44)*. % 76.01/76.20 30784[80:MRR:132.0,30783.0] || -> until5(s45)*. % 76.01/76.20 30785[80:MRR:26430.0,30784.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.20 30787[81:Spt:30785.2] || -> xuntil6(s45)*. % 76.01/76.20 30788[81:MRR:131.0,30787.0] || -> until5(s46)*. % 76.01/76.20 30789[81:MRR:29415.0,30788.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.01/76.20 30790[82:Spt:30789.1] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.20 30792[82:Res:30790.0,61.1] always3(s47) || -> . % 76.01/76.20 30793[82:SSi:30792.0,736.0] || -> . % 76.01/76.20 30794[82:Spt:30793.0,30789.1,30790.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.01/76.20 30795[82:Spt:30793.0,30789.0,30789.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 76.01/76.20 30797[82:MRR:780.2,30794.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 76.01/76.20 30798[82:Res:53.1,30795.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 76.01/76.20 30800[83:Spt:30798.1] || -> xuntil6(s46)*. % 76.01/76.20 30801[83:MRR:130.0,30800.0] || -> until5(s47)*. % 76.01/76.20 30802[83:MRR:26434.0,30801.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.20 30807[84:Spt:30802.2] || -> xuntil6(s47)*. % 76.01/76.20 30808[84:MRR:129.0,30807.0] || -> until5(s48)*. % 76.01/76.20 30809[84:MRR:29419.0,30808.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.01/76.20 30810[85:Spt:30809.1] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.20 30812[85:Res:30810.0,61.1] always3(s49) || -> . % 76.01/76.20 30813[85:SSi:30812.0,50.0,738.0] || -> . % 76.01/76.20 30814[85:Spt:30813.0,30809.1,30810.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.01/76.20 30815[85:Spt:30813.0,30809.0,30809.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 76.01/76.20 30817[85:MRR:774.2,30814.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.01/76.20 30818[85:Res:53.1,30815.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 76.01/76.20 30820[86:Spt:30818.1] || -> xuntil6(s48)*. % 76.01/76.20 30821[86:MRR:128.0,30820.0] || -> until5(s49)*. % 76.01/76.20 30829[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.20 30830[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.20 30831[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.20 30832[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.20 30836[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.20 30840[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.20 30847[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.20 30848[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.20 30852[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.20 30856[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.20 30860[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.20 30867[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.20 30868[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.20 30872[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.20 30876[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.20 30880[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.20 30887[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.20 30888[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.20 30892[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.20 30896[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.20 30900[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.20 30907[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.20 30908[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.20 30912[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.20 30916[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.20 30920[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.20 30927[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.20 30928[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.20 30932[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.20 30936[0:SoR:819.0,66.2] until5(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.20 30940[0:SoR:813.0,66.2] until5(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.20 30947[0:SoR:807.0,66.2] until5(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.20 30948[0:SoR:801.0,66.2] until5(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.20 30952[0:SoR:795.0,66.2] until5(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.20 30956[0:SoR:789.0,66.2] until5(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.20 30960[0:SoR:783.0,66.2] until5(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.20 30964[0:SoR:777.0,66.2] until5(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.20 30966[26:SoR:30471.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)*. % 76.01/76.20 30968[26:SoR:30966.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)* xuntil6(s49). % 76.01/76.20 30969[86:SSi:30968.0,50.0,738.0,30821.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s25,c_busy)* xuntil6(s49). % 76.01/76.20 30970[87:Spt:30969.1] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.20 30972[87:Res:30970.0,61.1] always3(s25) || -> . % 76.01/76.20 30973[87:SSi:30972.0,714.0,30584.0,30586.0] || -> . % 76.01/76.20 30974[87:Spt:30973.0,30969.1,30970.0] || m_main_v_state(s25,c_busy)*+ -> . % 76.01/76.20 30975[87:Spt:30973.0,30969.0,30969.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.01/76.20 30979[87:MRR:30966.2,30974.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.01/76.20 30980[87:Res:53.1,30975.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.01/76.20 30982[87:MRR:30980.0,30814.0] || -> xuntil6(s49)*. % 76.01/76.20 30983[87:MRR:30470.0,30982.0] || -> until2p7(s25)*. % 76.01/76.20 30984[87:MRR:221.0,30983.0] || -> until2p7(s26)* node4(s25). % 76.01/76.20 30985[88:Spt:30984.0] || -> until2p7(s26)*. % 76.01/76.20 30986[88:MRR:222.0,30985.0] || -> until2p7(s27)* node4(s26). % 76.01/76.20 30987[89:Spt:30986.0] || -> until2p7(s27)*. % 76.01/76.20 30988[89:MRR:223.0,30987.0] || -> until2p7(s28)* node4(s27). % 76.01/76.20 30989[90:Spt:30988.0] || -> until2p7(s28)*. % 76.01/76.20 30990[90:MRR:224.0,30989.0] || -> until2p7(s29)* node4(s28). % 76.01/76.20 30991[91:Spt:30990.0] || -> until2p7(s29)*. % 76.01/76.20 30992[91:MRR:225.0,30991.0] || -> until2p7(s30)* node4(s29). % 76.01/76.20 30993[92:Spt:30992.0] || -> until2p7(s30)*. % 76.01/76.20 30994[92:MRR:226.0,30993.0] || -> until2p7(s31)* node4(s30). % 76.01/76.20 30995[93:Spt:30994.0] || -> until2p7(s31)*. % 76.01/76.20 30996[93:MRR:227.0,30995.0] || -> until2p7(s32)* node4(s31). % 76.01/76.20 30997[94:Spt:30996.0] || -> until2p7(s32)*. % 76.01/76.20 30998[94:MRR:228.0,30997.0] || -> until2p7(s33)* node4(s32). % 76.01/76.20 30999[95:Spt:30998.0] || -> until2p7(s33)*. % 76.01/76.20 31000[95:MRR:229.0,30999.0] || -> until2p7(s34)* node4(s33). % 76.01/76.20 31001[96:Spt:31000.0] || -> until2p7(s34)*. % 76.01/76.20 31002[96:MRR:230.0,31001.0] || -> until2p7(s35)* node4(s34). % 76.01/76.20 31003[97:Spt:31002.0] || -> until2p7(s35)*. % 76.01/76.20 31004[97:MRR:231.0,31003.0] || -> until2p7(s36)* node4(s35). % 76.01/76.20 31005[98:Spt:31004.0] || -> until2p7(s36)*. % 76.01/76.20 31006[98:MRR:232.0,31005.0] || -> until2p7(s37)* node4(s36). % 76.01/76.20 31007[99:Spt:31006.0] || -> until2p7(s37)*. % 76.01/76.20 31008[99:MRR:235.0,31007.0] || -> until2p7(s38)* node4(s37). % 76.01/76.20 31009[100:Spt:31008.0] || -> until2p7(s38)*. % 76.01/76.20 31010[100:MRR:236.0,31009.0] || -> until2p7(s39)* node4(s38). % 76.01/76.20 31011[101:Spt:31010.0] || -> until2p7(s39)*. % 76.01/76.20 31012[101:MRR:237.0,31011.0] || -> until2p7(s40)* node4(s39). % 76.01/76.20 31013[102:Spt:31012.0] || -> until2p7(s40)*. % 76.01/76.20 31014[102:MRR:238.0,31013.0] || -> until2p7(s41)* node4(s40). % 76.01/76.20 31015[103:Spt:31014.0] || -> until2p7(s41)*. % 76.01/76.20 31016[103:MRR:239.0,31015.0] || -> until2p7(s42)* node4(s41). % 76.01/76.20 31017[104:Spt:31016.0] || -> until2p7(s42)*. % 76.01/76.20 31018[104:MRR:240.0,31017.0] || -> until2p7(s43)* node4(s42). % 76.01/76.20 31019[105:Spt:31018.0] || -> until2p7(s43)*. % 76.01/76.20 31020[105:MRR:241.0,31019.0] || -> until2p7(s44)* node4(s43). % 76.01/76.20 31021[106:Spt:31020.0] || -> until2p7(s44)*. % 76.01/76.20 31022[106:MRR:539.0,31021.0] || -> until2p7(s45)* node4(s44). % 76.01/76.20 31023[107:Spt:31022.0] || -> until2p7(s45)*. % 76.01/76.20 31024[107:MRR:544.0,31023.0] || -> until2p7(s46)* node4(s45). % 76.01/76.20 31025[108:Spt:31024.0] || -> until2p7(s46)*. % 76.01/76.20 31026[108:MRR:549.0,31025.0] || -> until2p7(s47)* node4(s46). % 76.01/76.20 31027[109:Spt:31026.0] || -> until2p7(s47)*. % 76.01/76.20 31028[109:MRR:554.0,31027.0] || -> until2p7(s48)* node4(s47). % 76.01/76.20 31029[110:Spt:31028.0] || -> until2p7(s48)*. % 76.01/76.20 31030[110:MRR:559.0,31029.0] || -> until2p7(s49)* node4(s48). % 76.01/76.20 31031[111:Spt:31030.0] || -> until2p7(s49)*. % 76.01/76.20 31032[111:MRR:194.0,31031.0] || -> node4(s49)*. % 76.01/76.20 31033[111:MRR:30979.0,31032.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.01/76.20 31034[111:Res:53.1,31033.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.20 31036[111:MRR:31034.0,30814.0] || -> . % 76.01/76.20 31037[111:Spt:31036.0,31030.0,31031.0] || until2p7(s49)*+ -> . % 76.01/76.20 31038[111:Spt:31036.0,31030.1] || -> node4(s48)*. % 76.01/76.20 31039[111:MRR:30817.0,31038.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.01/76.20 31042[111:Res:53.1,31039.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.20 31045[111:Res:31042.0,61.1] always3(s48) || -> . % 76.01/76.20 31046[111:SSi:31045.0,737.0,30808.0,30820.0,31029.0,31038.0] || -> . % 76.01/76.20 31047[110:Spt:31046.0,31028.0,31029.0] || until2p7(s48)*+ -> . % 76.01/76.20 31048[110:Spt:31046.0,31028.1] || -> node4(s47)*. % 76.01/76.20 31050[110:MRR:777.0,31048.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.01/76.20 31065[110:Res:53.1,31050.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.01/76.20 31067[110:MRR:31065.0,30794.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.20 31069[110:Res:31067.0,61.1] always3(s48) || -> . % 76.01/76.20 31070[110:SSi:31069.0,737.0,30808.0,30820.0] || -> . % 76.01/76.20 31071[109:Spt:31070.0,31026.0,31027.0] || until2p7(s47)*+ -> . % 76.01/76.20 31072[109:Spt:31070.0,31026.1] || -> node4(s46)*. % 76.01/76.20 31073[109:MRR:30797.0,31072.0] || m_main_v_state(s46,c_ready)*+ -> . % 76.01/76.20 31076[109:Res:53.1,31073.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.20 31079[109:Res:31076.0,61.1] always3(s46) || -> . % 76.01/76.20 31080[109:SSi:31079.0,735.0,30788.0,30800.0,31025.0,31072.0] || -> . % 76.01/76.20 31081[108:Spt:31080.0,31024.0,31025.0] || until2p7(s46)*+ -> . % 76.01/76.20 31082[108:Spt:31080.0,31024.1] || -> node4(s45)*. % 76.01/76.20 31084[108:MRR:783.0,31082.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.01/76.20 31096[108:Res:53.1,31084.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.01/76.20 31098[108:MRR:31096.0,30774.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.20 31103[108:Res:31098.0,61.1] always3(s46) || -> . % 76.01/76.20 31104[108:SSi:31103.0,735.0,30788.0,30800.0] || -> . % 76.01/76.20 31105[107:Spt:31104.0,31022.0,31023.0] || until2p7(s45)*+ -> . % 76.01/76.20 31106[107:Spt:31104.0,31022.1] || -> node4(s44)*. % 76.01/76.20 31107[107:MRR:30777.0,31106.0] || m_main_v_state(s44,c_ready)*+ -> . % 76.01/76.20 31110[107:Res:53.1,31107.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.20 31114[107:Res:31110.0,61.1] always3(s44) || -> . % 76.01/76.20 31115[107:SSi:31114.0,733.0,30768.0,30783.0,31021.0,31106.0] || -> . % 76.01/76.20 31116[106:Spt:31115.0,31020.0,31021.0] || until2p7(s44)*+ -> . % 76.01/76.20 31117[106:Spt:31115.0,31020.1] || -> node4(s43)*. % 76.01/76.20 31119[106:MRR:789.0,31117.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.01/76.20 31130[106:Res:53.1,31119.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.01/76.20 31132[106:MRR:31130.0,30751.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.20 31134[106:Res:31132.0,61.1] always3(s44) || -> . % 76.01/76.20 31135[106:SSi:31134.0,733.0,30768.0,30783.0] || -> . % 76.01/76.20 31136[105:Spt:31135.0,31018.0,31019.0] || until2p7(s43)*+ -> . % 76.01/76.20 31137[105:Spt:31135.0,31018.1] || -> node4(s42)*. % 76.01/76.20 31138[105:MRR:30754.0,31137.0] || m_main_v_state(s42,c_ready)*+ -> . % 76.01/76.20 31142[105:Res:53.1,31138.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.20 31145[105:Res:31142.0,61.1] always3(s42) || -> . % 76.01/76.20 31146[105:SSi:31145.0,731.0,30745.0,30757.0,31017.0,31137.0] || -> . % 76.01/76.20 31147[104:Spt:31146.0,31016.0,31017.0] || until2p7(s42)*+ -> . % 76.01/76.20 31148[104:Spt:31146.0,31016.1] || -> node4(s41)*. % 76.01/76.20 31150[104:MRR:795.0,31148.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.01/76.20 31161[104:Res:53.1,31150.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.01/76.20 31163[104:MRR:31161.0,30731.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.20 31165[104:Res:31163.0,61.1] always3(s42) || -> . % 76.01/76.20 31166[104:SSi:31165.0,731.0,30745.0,30757.0] || -> . % 76.01/76.20 31167[103:Spt:31166.0,31014.0,31015.0] || until2p7(s41)*+ -> . % 76.01/76.20 31168[103:Spt:31166.0,31014.1] || -> node4(s40)*. % 76.01/76.20 31169[103:MRR:30734.0,31168.0] || m_main_v_state(s40,c_ready)*+ -> . % 76.01/76.20 31172[103:Res:53.1,31169.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.20 31175[103:Res:31172.0,61.1] always3(s40) || -> . % 76.01/76.20 31176[103:SSi:31175.0,729.0,30725.0,30737.0,31013.0,31168.0] || -> . % 76.01/76.20 31177[102:Spt:31176.0,31012.0,31013.0] || until2p7(s40)*+ -> . % 76.01/76.20 31178[102:Spt:31176.0,31012.1] || -> node4(s39)*. % 76.01/76.20 31180[102:MRR:801.0,31178.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.01/76.20 31192[102:Res:53.1,31180.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.01/76.20 31194[102:MRR:31192.0,30711.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.20 31196[102:Res:31194.0,61.1] always3(s40) || -> . % 76.01/76.20 31197[102:SSi:31196.0,729.0,30725.0,30737.0] || -> . % 76.01/76.20 31198[101:Spt:31197.0,31010.0,31011.0] || until2p7(s39)*+ -> . % 76.01/76.20 31199[101:Spt:31197.0,31010.1] || -> node4(s38)*. % 76.01/76.20 31200[101:MRR:30714.0,31199.0] || m_main_v_state(s38,c_ready)*+ -> . % 76.01/76.20 31203[101:Res:53.1,31200.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.20 31206[101:Res:31203.0,61.1] always3(s38) || -> . % 76.01/76.20 31207[101:SSi:31206.0,727.0,30705.0,30720.0,31009.0,31199.0] || -> . % 76.01/76.20 31208[100:Spt:31207.0,31008.0,31009.0] || until2p7(s38)*+ -> . % 76.01/76.20 31209[100:Spt:31207.0,31008.1] || -> node4(s37)*. % 76.01/76.20 31211[100:MRR:807.0,31209.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.01/76.20 31223[100:Res:53.1,31211.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.01/76.20 31225[100:MRR:31223.0,30688.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.20 31230[100:Res:31225.0,61.1] always3(s38) || -> . % 76.01/76.20 31231[100:SSi:31230.0,727.0,30705.0,30720.0] || -> . % 76.01/76.20 31232[99:Spt:31231.0,31006.0,31007.0] || until2p7(s37)*+ -> . % 76.01/76.20 31233[99:Spt:31231.0,31006.1] || -> node4(s36)*. % 76.01/76.20 31234[99:MRR:30691.0,31233.0] || m_main_v_state(s36,c_ready)*+ -> . % 76.01/76.20 31237[99:Res:53.1,31234.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.20 31241[99:Res:31237.0,61.1] always3(s36) || -> . % 76.01/76.20 31242[99:SSi:31241.0,725.0,30682.0,30694.0,31005.0,31233.0] || -> . % 76.01/76.20 31243[98:Spt:31242.0,31004.0,31005.0] || until2p7(s36)*+ -> . % 76.01/76.20 31244[98:Spt:31242.0,31004.1] || -> node4(s35)*. % 76.01/76.20 31246[98:MRR:813.0,31244.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.01/76.20 31257[98:Res:53.1,31246.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.01/76.20 31259[98:MRR:31257.0,30668.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.20 31261[98:Res:31259.0,61.1] always3(s36) || -> . % 76.01/76.20 31262[98:SSi:31261.0,725.0,30682.0,30694.0] || -> . % 76.01/76.20 31263[97:Spt:31262.0,31002.0,31003.0] || until2p7(s35)*+ -> . % 76.01/76.20 31264[97:Spt:31262.0,31002.1] || -> node4(s34)*. % 76.01/76.20 31265[97:MRR:30671.0,31264.0] || m_main_v_state(s34,c_ready)*+ -> . % 76.01/76.20 31269[97:Res:53.1,31265.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.20 31272[97:Res:31269.0,61.1] always3(s34) || -> . % 76.01/76.20 31273[97:SSi:31272.0,723.0,30662.0,30674.0,31001.0,31264.0] || -> . % 76.01/76.20 31274[96:Spt:31273.0,31000.0,31001.0] || until2p7(s34)*+ -> . % 76.01/76.20 31275[96:Spt:31273.0,31000.1] || -> node4(s33)*. % 76.01/76.20 31277[96:MRR:819.0,31275.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.01/76.20 31288[96:Res:53.1,31277.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.01/76.20 31290[96:MRR:31288.0,30648.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.20 31292[96:Res:31290.0,61.1] always3(s34) || -> . % 76.01/76.20 31293[96:SSi:31292.0,723.0,30662.0,30674.0] || -> . % 76.01/76.20 31294[95:Spt:31293.0,30998.0,30999.0] || until2p7(s33)*+ -> . % 76.01/76.20 31295[95:Spt:31293.0,30998.1] || -> node4(s32)*. % 76.01/76.20 31296[95:MRR:30651.0,31295.0] || m_main_v_state(s32,c_ready)*+ -> . % 76.01/76.20 31299[95:Res:53.1,31296.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.20 31302[95:Res:31299.0,61.1] always3(s32) || -> . % 76.01/76.20 31303[95:SSi:31302.0,721.0,30642.0,30657.0,30997.0,31295.0] || -> . % 76.01/76.20 31304[94:Spt:31303.0,30996.0,30997.0] || until2p7(s32)*+ -> . % 76.01/76.20 31305[94:Spt:31303.0,30996.1] || -> node4(s31)*. % 76.01/76.20 31307[94:MRR:825.0,31305.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.01/76.20 31319[94:Res:53.1,31307.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.01/76.20 31321[94:MRR:31319.0,30625.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.20 31323[94:Res:31321.0,61.1] always3(s32) || -> . % 76.01/76.20 31324[94:SSi:31323.0,721.0,30642.0,30657.0] || -> . % 76.01/76.20 31325[93:Spt:31324.0,30994.0,30995.0] || until2p7(s31)*+ -> . % 76.01/76.20 31326[93:Spt:31324.0,30994.1] || -> node4(s30)*. % 76.01/76.20 31327[93:MRR:30628.0,31326.0] || m_main_v_state(s30,c_ready)*+ -> . % 76.01/76.20 31330[93:Res:53.1,31327.0] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.20 31333[93:Res:31330.0,61.1] always3(s30) || -> . % 76.01/76.20 31334[93:SSi:31333.0,719.0,30619.0,30631.0,30993.0,31326.0] || -> . % 76.01/76.20 31335[92:Spt:31334.0,30992.0,30993.0] || until2p7(s30)*+ -> . % 76.01/76.20 31336[92:Spt:31334.0,30992.1] || -> node4(s29)*. % 76.01/76.20 31338[92:MRR:831.0,31336.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.01/76.20 31350[92:Res:53.1,31338.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.01/76.20 31352[92:MRR:31350.0,30605.0] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.20 31357[92:Res:31352.0,61.1] always3(s30) || -> . % 76.01/76.20 31358[92:SSi:31357.0,719.0,30619.0,30631.0] || -> . % 76.01/76.20 31359[91:Spt:31358.0,30990.0,30991.0] || until2p7(s29)*+ -> . % 76.01/76.20 31360[91:Spt:31358.0,30990.1] || -> node4(s28)*. % 76.01/76.20 31361[91:MRR:30608.0,31360.0] || m_main_v_state(s28,c_ready)*+ -> . % 76.01/76.20 31364[91:Res:53.1,31361.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.20 31368[91:Res:31364.0,61.1] always3(s28) || -> . % 76.01/76.20 31369[91:SSi:31368.0,717.0,30596.0,30611.0,30989.0,31360.0] || -> . % 76.01/76.20 31370[90:Spt:31369.0,30988.0,30989.0] || until2p7(s28)*+ -> . % 76.01/76.20 31371[90:Spt:31369.0,30988.1] || -> node4(s27)*. % 76.01/76.20 31373[90:MRR:837.0,31371.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.01/76.20 31384[90:Res:53.1,31373.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.01/76.20 31386[91:Spt:31384.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.20 31388[91:Res:31386.0,61.1] always3(s27) || -> . % 76.01/76.20 31389[91:SSi:31388.0,716.0,30593.0,30595.0,30987.0,31371.0] || -> . % 76.01/76.20 31390[91:Spt:31389.0,31384.0,31386.0] || m_main_v_state(s27,c_busy)* -> . % 76.01/76.20 31391[91:Spt:31389.0,31384.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.20 31395[91:Res:31391.0,61.1] always3(s28) || -> . % 76.01/76.20 31396[91:SSi:31395.0,717.0,30596.0,30611.0] || -> . % 76.01/76.20 31397[89:Spt:31396.0,30986.0,30987.0] || until2p7(s27)*+ -> . % 76.01/76.20 31398[89:Spt:31396.0,30986.1] || -> node4(s26)*. % 76.01/76.20 31400[89:MRR:840.0,31398.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.01/76.20 31407[89:Res:53.1,31400.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.01/76.20 31412[90:Spt:31407.0] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.20 31414[90:Res:31412.0,61.1] always3(s26) || -> . % 76.01/76.20 31415[90:SSi:31414.0,715.0,30587.0,30592.0,30985.0,31398.0] || -> . % 76.01/76.20 31416[90:Spt:31415.0,31407.0,31412.0] || m_main_v_state(s26,c_busy)* -> . % 76.01/76.20 31417[90:Spt:31415.0,31407.1] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.20 31421[90:Res:31417.0,61.1] always3(s27) || -> . % 76.01/76.20 31422[90:SSi:31421.0,716.0,30593.0,30595.0] || -> . % 76.01/76.20 31423[88:Spt:31422.0,30984.0,30985.0] || until2p7(s26)*+ -> . % 76.01/76.20 31424[88:Spt:31422.0,30984.1] || -> node4(s25)*. % 76.01/76.20 31426[88:MRR:843.0,31424.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.01/76.20 31429[88:Res:53.1,31426.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.01/76.20 31431[88:MRR:31429.0,30974.0] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.20 31433[88:Res:31431.0,61.1] always3(s26) || -> . % 76.01/76.20 31434[88:SSi:31433.0,715.0,30587.0,30592.0] || -> . % 76.01/76.20 31435[86:Spt:31434.0,30818.1,30820.0] || xuntil6(s48)* -> . % 76.01/76.20 31436[86:Spt:31434.0,30818.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.20 31439[86:Res:31436.0,61.1] always3(s48) || -> . % 76.01/76.20 31440[86:SSi:31439.0,737.0,30808.0] || -> . % 76.01/76.20 31441[84:Spt:31440.0,30802.2,30807.0] || xuntil6(s47)*+ -> . % 76.01/76.20 31442[84:Spt:31440.0,30802.0,30802.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.01/76.20 31443[84:Res:53.1,31442.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.01/76.20 31445[84:MRR:31443.0,30794.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.20 31447[84:Res:31445.0,61.1] always3(s48) || -> . % 76.01/76.20 31448[84:SSi:31447.0,737.0] || -> . % 76.01/76.20 31449[83:Spt:31448.0,30798.1,30800.0] || xuntil6(s46)* -> . % 76.01/76.20 31450[83:Spt:31448.0,30798.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.20 31453[83:Res:31450.0,61.1] always3(s46) || -> . % 76.01/76.20 31454[83:SSi:31453.0,735.0,30788.0] || -> . % 76.01/76.20 31455[81:Spt:31454.0,30785.2,30787.0] || xuntil6(s45)*+ -> . % 76.01/76.20 31456[81:Spt:31454.0,30785.0,30785.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.01/76.20 31457[81:Res:53.1,31456.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.01/76.20 31459[81:MRR:31457.0,30774.0] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.20 31461[81:Res:31459.0,61.1] always3(s46) || -> . % 76.01/76.20 31462[81:SSi:31461.0,735.0] || -> . % 76.01/76.20 31463[80:Spt:31462.0,30778.1,30783.0] || xuntil6(s44)* -> . % 76.01/76.20 31464[80:Spt:31462.0,30778.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.20 31467[80:Res:31464.0,61.1] always3(s44) || -> . % 76.01/76.20 31468[80:SSi:31467.0,733.0,30768.0] || -> . % 76.01/76.20 31469[78:Spt:31468.0,30759.2,30767.0] || xuntil6(s43)*+ -> . % 76.01/76.20 31470[78:Spt:31468.0,30759.0,30759.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.01/76.20 31471[78:Res:53.1,31470.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.01/76.20 31473[78:MRR:31471.0,30751.0] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.20 31475[78:Res:31473.0,61.1] always3(s44) || -> . % 76.01/76.20 31476[78:SSi:31475.0,733.0] || -> . % 76.01/76.20 31477[77:Spt:31476.0,30755.1,30757.0] || xuntil6(s42)* -> . % 76.01/76.20 31478[77:Spt:31476.0,30755.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.20 31481[77:Res:31478.0,61.1] always3(s42) || -> . % 76.01/76.20 31482[77:SSi:31481.0,731.0,30745.0] || -> . % 76.01/76.20 31483[75:Spt:31482.0,30739.2,30744.0] || xuntil6(s41)*+ -> . % 76.01/76.20 31484[75:Spt:31482.0,30739.0,30739.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.01/76.20 31485[75:Res:53.1,31484.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.01/76.20 31487[75:MRR:31485.0,30731.0] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.20 31490[75:Res:31487.0,61.1] always3(s42) || -> . % 76.01/76.20 31491[75:SSi:31490.0,731.0] || -> . % 76.01/76.20 31492[74:Spt:31491.0,30735.1,30737.0] || xuntil6(s40)* -> . % 76.01/76.20 31493[74:Spt:31491.0,30735.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.20 31496[74:Res:31493.0,61.1] always3(s40) || -> . % 76.01/76.20 31497[74:SSi:31496.0,729.0,30725.0] || -> . % 76.01/76.20 31498[72:Spt:31497.0,30722.2,30724.0] || xuntil6(s39)*+ -> . % 76.01/76.20 31499[72:Spt:31497.0,30722.0,30722.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.01/76.20 31500[72:Res:53.1,31499.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.01/76.20 31502[72:MRR:31500.0,30711.0] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.20 31504[72:Res:31502.0,61.1] always3(s40) || -> . % 76.01/76.20 31505[72:SSi:31504.0,729.0] || -> . % 76.01/76.20 31506[71:Spt:31505.0,30715.1,30720.0] || xuntil6(s38)* -> . % 76.01/76.20 31507[71:Spt:31505.0,30715.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.20 31510[71:Res:31507.0,61.1] always3(s38) || -> . % 76.01/76.20 31511[71:SSi:31510.0,727.0,30705.0] || -> . % 76.01/76.20 31512[69:Spt:31511.0,30696.2,30704.0] || xuntil6(s37)*+ -> . % 76.01/76.20 31513[69:Spt:31511.0,30696.0,30696.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.01/76.20 31514[69:Res:53.1,31513.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.01/76.20 31516[69:MRR:31514.0,30688.0] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.20 31519[69:Res:31516.0,61.1] always3(s38) || -> . % 76.01/76.20 31520[69:SSi:31519.0,727.0] || -> . % 76.01/76.20 31521[68:Spt:31520.0,30692.1,30694.0] || xuntil6(s36)* -> . % 76.01/76.20 31522[68:Spt:31520.0,30692.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.20 31525[68:Res:31522.0,61.1] always3(s36) || -> . % 76.01/76.20 31526[68:SSi:31525.0,725.0,30682.0] || -> . % 76.01/76.20 31527[66:Spt:31526.0,30676.2,30681.0] || xuntil6(s35)*+ -> . % 76.01/76.20 31528[66:Spt:31526.0,30676.0,30676.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.01/76.20 31529[66:Res:53.1,31528.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.01/76.20 31531[66:MRR:31529.0,30668.0] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.20 31533[66:Res:31531.0,61.1] always3(s36) || -> . % 76.01/76.20 31534[66:SSi:31533.0,725.0] || -> . % 76.01/76.20 31535[65:Spt:31534.0,30672.1,30674.0] || xuntil6(s34)* -> . % 76.01/76.20 31536[65:Spt:31534.0,30672.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.20 31539[65:Res:31536.0,61.1] always3(s34) || -> . % 76.01/76.20 31540[65:SSi:31539.0,723.0,30662.0] || -> . % 76.01/76.20 31541[63:Spt:31540.0,30659.2,30661.0] || xuntil6(s33)*+ -> . % 76.01/76.20 31542[63:Spt:31540.0,30659.0,30659.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.01/76.20 31543[63:Res:53.1,31542.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.01/76.20 31545[63:MRR:31543.0,30648.0] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.20 31547[63:Res:31545.0,61.1] always3(s34) || -> . % 76.01/76.20 31548[63:SSi:31547.0,723.0] || -> . % 76.01/76.20 31549[62:Spt:31548.0,30652.1,30657.0] || xuntil6(s32)* -> . % 76.01/76.20 31550[62:Spt:31548.0,30652.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.20 31553[62:Res:31550.0,61.1] always3(s32) || -> . % 76.01/76.20 31554[62:SSi:31553.0,721.0,30642.0] || -> . % 76.01/76.20 31555[60:Spt:31554.0,30633.2,30641.0] || xuntil6(s31)*+ -> . % 76.01/76.20 31556[60:Spt:31554.0,30633.0,30633.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.01/76.20 31557[60:Res:53.1,31556.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.01/76.20 31559[60:MRR:31557.0,30625.0] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.20 31561[60:Res:31559.0,61.1] always3(s32) || -> . % 76.01/76.20 31562[60:SSi:31561.0,721.0] || -> . % 76.01/76.20 31563[59:Spt:31562.0,30629.1,30631.0] || xuntil6(s30)* -> . % 76.01/76.20 31564[59:Spt:31562.0,30629.0] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.20 31567[59:Res:31564.0,61.1] always3(s30) || -> . % 76.01/76.20 31568[59:SSi:31567.0,719.0,30619.0] || -> . % 76.01/76.20 31569[57:Spt:31568.0,30613.2,30618.0] || xuntil6(s29)*+ -> . % 76.01/76.20 31570[57:Spt:31568.0,30613.0,30613.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.01/76.20 31571[57:Res:53.1,31570.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.01/76.20 31573[57:MRR:31571.0,30605.0] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.20 31575[57:Res:31573.0,61.1] always3(s30) || -> . % 76.01/76.20 31576[57:SSi:31575.0,719.0] || -> . % 76.01/76.20 31577[56:Spt:31576.0,30609.1,30611.0] || xuntil6(s28)* -> . % 76.01/76.20 31578[56:Spt:31576.0,30609.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.20 31581[56:Res:31578.0,61.1] always3(s28) || -> . % 76.01/76.20 31582[56:SSi:31581.0,717.0,30596.0] || -> . % 76.01/76.20 31583[54:Spt:31582.0,30594.2,30595.0] || xuntil6(s27)*+ -> . % 76.01/76.20 31584[54:Spt:31582.0,30594.0,30594.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.01/76.20 31585[54:Res:53.1,31584.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.01/76.20 31587[55:Spt:31585.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.20 31589[55:Res:31587.0,61.1] always3(s28) || -> . % 76.01/76.20 31590[55:SSi:31589.0,717.0] || -> . % 76.01/76.20 31591[55:Spt:31590.0,31585.1,31587.0] || m_main_v_state(s28,c_busy)* -> . % 76.01/76.20 31592[55:Spt:31590.0,31585.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.20 31595[55:Res:31592.0,61.1] always3(s27) || -> . % 76.01/76.20 31596[55:SSi:31595.0,716.0,30593.0] || -> . % 76.01/76.20 31597[53:Spt:31596.0,30588.2,30592.0] || xuntil6(s26)*+ -> . % 76.01/76.20 31598[53:Spt:31596.0,30588.0,30588.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.01/76.20 31599[53:Res:53.1,31598.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.01/76.20 31601[54:Spt:31599.1] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.20 31603[54:Res:31601.0,61.1] always3(s27) || -> . % 76.01/76.20 31604[54:SSi:31603.0,716.0] || -> . % 76.01/76.20 31605[54:Spt:31604.0,31599.1,31601.0] || m_main_v_state(s27,c_busy)* -> . % 76.01/76.20 31606[54:Spt:31604.0,31599.0] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.20 31609[54:Res:31606.0,61.1] always3(s26) || -> . % 76.01/76.20 31610[54:SSi:31609.0,715.0,30587.0] || -> . % 76.01/76.20 31611[52:Spt:31610.0,30585.2,30586.0] || xuntil6(s25)*+ -> . % 76.01/76.20 31612[52:Spt:31610.0,30585.0,30585.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.01/76.20 31613[52:Res:53.1,31612.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.01/76.20 31615[53:Spt:31613.1] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.20 31617[53:Res:31615.0,61.1] always3(s26) || -> . % 76.01/76.20 31618[53:SSi:31617.0,715.0] || -> . % 76.01/76.20 31619[53:Spt:31618.0,31613.1,31615.0] || m_main_v_state(s26,c_busy)* -> . % 76.01/76.20 31620[53:Spt:31618.0,31613.0] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.20 31623[53:Res:31620.0,61.1] always3(s25) || -> . % 76.01/76.20 31624[53:SSi:31623.0,714.0,30584.0] || -> . % 76.01/76.20 31625[51:Spt:31624.0,30579.2,30583.0] || xuntil6(s24)*+ -> . % 76.01/76.20 31626[51:Spt:31624.0,30579.0,30579.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.01/76.20 31627[51:Res:53.1,31626.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.01/76.20 31629[52:Spt:31627.0] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.20 31631[52:Res:31629.0,61.1] always3(s24) || -> . % 76.01/76.20 31632[52:SSi:31631.0,713.0,30578.0] || -> . % 76.01/76.20 31633[52:Spt:31632.0,31627.0,31629.0] || m_main_v_state(s24,c_busy)* -> . % 76.01/76.20 31634[52:Spt:31632.0,31627.1] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.20 31638[52:Res:31634.0,61.1] always3(s25) || -> . % 76.01/76.20 31639[52:SSi:31638.0,714.0] || -> . % 76.01/76.20 31640[50:Spt:31639.0,30576.2,30577.0] || xuntil6(s23)*+ -> . % 76.01/76.20 31641[50:Spt:31639.0,30576.0,30576.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.01/76.20 31642[50:Res:53.1,31641.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.01/76.20 31644[51:Spt:31642.0] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.20 31646[51:Res:31644.0,61.1] always3(s23) || -> . % 76.01/76.20 31647[51:SSi:31646.0,712.0,30575.0] || -> . % 76.01/76.20 31648[51:Spt:31647.0,31642.0,31644.0] || m_main_v_state(s23,c_busy)* -> . % 76.01/76.20 31649[51:Spt:31647.0,31642.1] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.20 31653[51:Res:31649.0,61.1] always3(s24) || -> . % 76.01/76.20 31654[51:SSi:31653.0,713.0] || -> . % 76.01/76.20 31655[49:Spt:31654.0,30570.2,30574.0] || xuntil6(s22)*+ -> . % 76.01/76.20 31656[49:Spt:31654.0,30570.0,30570.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.01/76.20 31657[49:Res:53.1,31656.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.01/76.20 31659[50:Spt:31657.0] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.20 31661[50:Res:31659.0,61.1] always3(s22) || -> . % 76.01/76.20 31662[50:SSi:31661.0,711.0,30569.0] || -> . % 76.01/76.20 31663[50:Spt:31662.0,31657.0,31659.0] || m_main_v_state(s22,c_busy)* -> . % 76.01/76.20 31664[50:Spt:31662.0,31657.1] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.20 31668[50:Res:31664.0,61.1] always3(s23) || -> . % 76.01/76.20 31669[50:SSi:31668.0,712.0] || -> . % 76.01/76.20 31670[48:Spt:31669.0,30567.2,30568.0] || xuntil6(s21)*+ -> . % 76.01/76.20 31671[48:Spt:31669.0,30567.0,30567.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.01/76.20 31672[48:Res:53.1,31671.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.01/76.20 31674[49:Spt:31672.0] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.20 31676[49:Res:31674.0,61.1] always3(s21) || -> . % 76.01/76.20 31677[49:SSi:31676.0,710.0,30566.0] || -> . % 76.01/76.20 31678[49:Spt:31677.0,31672.0,31674.0] || m_main_v_state(s21,c_busy)* -> . % 76.01/76.20 31679[49:Spt:31677.0,31672.1] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.20 31683[49:Res:31679.0,61.1] always3(s22) || -> . % 76.01/76.20 31684[49:SSi:31683.0,711.0] || -> . % 76.01/76.20 31685[47:Spt:31684.0,30561.2,30565.0] || xuntil6(s20)*+ -> . % 76.01/76.20 31686[47:Spt:31684.0,30561.0,30561.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.01/76.20 31687[47:Res:53.1,31686.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.01/76.20 31689[48:Spt:31687.0] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.20 31691[48:Res:31689.0,61.1] always3(s20) || -> . % 76.01/76.20 31692[48:SSi:31691.0,709.0,30560.0] || -> . % 76.01/76.20 31693[48:Spt:31692.0,31687.0,31689.0] || m_main_v_state(s20,c_busy)* -> . % 76.01/76.20 31694[48:Spt:31692.0,31687.1] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.20 31698[48:Res:31694.0,61.1] always3(s21) || -> . % 76.01/76.20 31699[48:SSi:31698.0,710.0] || -> . % 76.01/76.20 31700[46:Spt:31699.0,30558.2,30559.0] || xuntil6(s19)*+ -> . % 76.01/76.20 31701[46:Spt:31699.0,30558.0,30558.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.01/76.20 31702[46:Res:53.1,31701.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.01/76.20 31707[47:Spt:31702.0] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.20 31709[47:Res:31707.0,61.1] always3(s19) || -> . % 76.01/76.20 31710[47:SSi:31709.0,708.0,30557.0] || -> . % 76.01/76.20 31711[47:Spt:31710.0,31702.0,31707.0] || m_main_v_state(s19,c_busy)* -> . % 76.01/76.20 31712[47:Spt:31710.0,31702.1] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.20 31716[47:Res:31712.0,61.1] always3(s20) || -> . % 76.01/76.20 31717[47:SSi:31716.0,709.0] || -> . % 76.01/76.20 31718[45:Spt:31717.0,30552.2,30556.0] || xuntil6(s18)*+ -> . % 76.01/76.20 31719[45:Spt:31717.0,30552.0,30552.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.01/76.20 31720[45:Res:53.1,31719.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.01/76.20 31722[46:Spt:31720.0] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.20 31724[46:Res:31722.0,61.1] always3(s18) || -> . % 76.01/76.20 31725[46:SSi:31724.0,707.0,30551.0] || -> . % 76.01/76.20 31726[46:Spt:31725.0,31720.0,31722.0] || m_main_v_state(s18,c_busy)* -> . % 76.01/76.20 31727[46:Spt:31725.0,31720.1] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.20 31731[46:Res:31727.0,61.1] always3(s19) || -> . % 76.01/76.20 31732[46:SSi:31731.0,708.0] || -> . % 76.01/76.20 31733[44:Spt:31732.0,30549.2,30550.0] || xuntil6(s17)*+ -> . % 76.01/76.20 31734[44:Spt:31732.0,30549.0,30549.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.01/76.20 31735[44:Res:53.1,31734.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.01/76.20 31737[45:Spt:31735.0] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.20 31739[45:Res:31737.0,61.1] always3(s17) || -> . % 76.01/76.20 31740[45:SSi:31739.0,706.0,30548.0] || -> . % 76.01/76.20 31741[45:Spt:31740.0,31735.0,31737.0] || m_main_v_state(s17,c_busy)* -> . % 76.01/76.20 31742[45:Spt:31740.0,31735.1] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.20 31746[45:Res:31742.0,61.1] always3(s18) || -> . % 76.01/76.20 31747[45:SSi:31746.0,707.0] || -> . % 76.01/76.20 31748[43:Spt:31747.0,30543.2,30547.0] || xuntil6(s16)*+ -> . % 76.01/76.20 31749[43:Spt:31747.0,30543.0,30543.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.01/76.20 31750[43:Res:53.1,31749.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.01/76.20 31755[44:Spt:31750.0] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.20 31757[44:Res:31755.0,61.1] always3(s16) || -> . % 76.01/76.20 31758[44:SSi:31757.0,705.0,30542.0] || -> . % 76.01/76.20 31759[44:Spt:31758.0,31750.0,31755.0] || m_main_v_state(s16,c_busy)* -> . % 76.01/76.20 31760[44:Spt:31758.0,31750.1] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.20 31764[44:Res:31760.0,61.1] always3(s17) || -> . % 76.01/76.20 31765[44:SSi:31764.0,706.0] || -> . % 76.01/76.20 31766[42:Spt:31765.0,30540.2,30541.0] || xuntil6(s15)*+ -> . % 76.01/76.20 31767[42:Spt:31765.0,30540.0,30540.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.01/76.20 31768[42:Res:53.1,31767.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.01/76.20 31770[43:Spt:31768.0] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.20 31772[43:Res:31770.0,61.1] always3(s15) || -> . % 76.01/76.20 31773[43:SSi:31772.0,704.0,30539.0] || -> . % 76.01/76.20 31774[43:Spt:31773.0,31768.0,31770.0] || m_main_v_state(s15,c_busy)* -> . % 76.01/76.20 31775[43:Spt:31773.0,31768.1] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.20 31779[43:Res:31775.0,61.1] always3(s16) || -> . % 76.01/76.20 31780[43:SSi:31779.0,705.0] || -> . % 76.01/76.20 31781[41:Spt:31780.0,30534.2,30538.0] || xuntil6(s14)*+ -> . % 76.01/76.20 31782[41:Spt:31780.0,30534.0,30534.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.01/76.20 31783[41:Res:53.1,31782.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.01/76.20 31785[42:Spt:31783.0] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.20 31787[42:Res:31785.0,61.1] always3(s14) || -> . % 76.01/76.20 31788[42:SSi:31787.0,703.0,30533.0] || -> . % 76.01/76.20 31789[42:Spt:31788.0,31783.0,31785.0] || m_main_v_state(s14,c_busy)* -> . % 76.01/76.20 31790[42:Spt:31788.0,31783.1] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.20 31794[42:Res:31790.0,61.1] always3(s15) || -> . % 76.01/76.20 31795[42:SSi:31794.0,704.0] || -> . % 76.01/76.20 31796[40:Spt:31795.0,30531.2,30532.0] || xuntil6(s13)*+ -> . % 76.01/76.20 31797[40:Spt:31795.0,30531.0,30531.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.01/76.20 31798[40:Res:53.1,31797.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.01/76.20 31803[41:Spt:31798.0] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.20 31805[41:Res:31803.0,61.1] always3(s13) || -> . % 76.01/76.20 31806[41:SSi:31805.0,702.0,30530.0] || -> . % 76.01/76.20 31807[41:Spt:31806.0,31798.0,31803.0] || m_main_v_state(s13,c_busy)* -> . % 76.01/76.20 31808[41:Spt:31806.0,31798.1] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.20 31812[41:Res:31808.0,61.1] always3(s14) || -> . % 76.01/76.20 31813[41:SSi:31812.0,703.0] || -> . % 76.01/76.20 31814[39:Spt:31813.0,30525.2,30529.0] || xuntil6(s12)*+ -> . % 76.01/76.20 31815[39:Spt:31813.0,30525.0,30525.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.01/76.20 31816[39:Res:53.1,31815.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.01/76.20 31818[40:Spt:31816.0] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.20 31820[40:Res:31818.0,61.1] always3(s12) || -> . % 76.01/76.20 31821[40:SSi:31820.0,701.0,30524.0] || -> . % 76.01/76.20 31822[40:Spt:31821.0,31816.0,31818.0] || m_main_v_state(s12,c_busy)* -> . % 76.01/76.20 31823[40:Spt:31821.0,31816.1] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.20 31827[40:Res:31823.0,61.1] always3(s13) || -> . % 76.01/76.20 31828[40:SSi:31827.0,702.0] || -> . % 76.01/76.20 31829[38:Spt:31828.0,30522.2,30523.0] || xuntil6(s11)*+ -> . % 76.01/76.20 31830[38:Spt:31828.0,30522.0,30522.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.01/76.20 31831[38:Res:53.1,31830.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.01/76.20 31833[39:Spt:31831.0] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.20 31835[39:Res:31833.0,61.1] always3(s11) || -> . % 76.01/76.20 31836[39:SSi:31835.0,700.0,30521.0] || -> . % 76.01/76.20 31837[39:Spt:31836.0,31831.0,31833.0] || m_main_v_state(s11,c_busy)* -> . % 76.01/76.20 31838[39:Spt:31836.0,31831.1] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.20 31842[39:Res:31838.0,61.1] always3(s12) || -> . % 76.01/76.20 31843[39:SSi:31842.0,701.0] || -> . % 76.01/76.20 31844[37:Spt:31843.0,30516.2,30520.0] || xuntil6(s10)*+ -> . % 76.01/76.20 31845[37:Spt:31843.0,30516.0,30516.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.01/76.20 31846[37:Res:53.1,31845.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.01/76.20 31851[38:Spt:31846.0] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.20 31853[38:Res:31851.0,61.1] always3(s10) || -> . % 76.01/76.20 31854[38:SSi:31853.0,699.0,30515.0] || -> . % 76.01/76.20 31855[38:Spt:31854.0,31846.0,31851.0] || m_main_v_state(s10,c_busy)* -> . % 76.01/76.20 31856[38:Spt:31854.0,31846.1] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.20 31860[38:Res:31856.0,61.1] always3(s11) || -> . % 76.01/76.20 31861[38:SSi:31860.0,700.0] || -> . % 76.01/76.20 31862[36:Spt:31861.0,30513.2,30514.0] || xuntil6(s9)*+ -> . % 76.01/76.20 31863[36:Spt:31861.0,30513.0,30513.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.01/76.20 31864[36:Res:53.1,31863.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.01/76.20 31866[37:Spt:31864.0] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.20 31868[37:Res:31866.0,61.1] always3(s9) || -> . % 76.01/76.20 31869[37:SSi:31868.0,698.0,30512.0] || -> . % 76.01/76.20 31870[37:Spt:31869.0,31864.0,31866.0] || m_main_v_state(s9,c_busy)* -> . % 76.01/76.20 31871[37:Spt:31869.0,31864.1] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.20 31875[37:Res:31871.0,61.1] always3(s10) || -> . % 76.01/76.20 31876[37:SSi:31875.0,699.0] || -> . % 76.01/76.20 31877[35:Spt:31876.0,30507.2,30511.0] || xuntil6(s8)*+ -> . % 76.01/76.20 31878[35:Spt:31876.0,30507.0,30507.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.01/76.20 31879[35:Res:53.1,31878.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.01/76.20 31881[36:Spt:31879.0] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.20 31883[36:Res:31881.0,61.1] always3(s8) || -> . % 76.01/76.20 31884[36:SSi:31883.0,697.0,30506.0] || -> . % 76.01/76.20 31885[36:Spt:31884.0,31879.0,31881.0] || m_main_v_state(s8,c_busy)* -> . % 76.01/76.20 31886[36:Spt:31884.0,31879.1] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.20 31890[36:Res:31886.0,61.1] always3(s9) || -> . % 76.01/76.20 31891[36:SSi:31890.0,698.0] || -> . % 76.01/76.20 31892[34:Spt:31891.0,30504.2,30505.0] || xuntil6(s7)*+ -> . % 76.01/76.20 31893[34:Spt:31891.0,30504.0,30504.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.01/76.20 31894[34:Res:53.1,31893.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.01/76.20 31899[35:Spt:31894.0] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.20 31901[35:Res:31899.0,61.1] always3(s7) || -> . % 76.01/76.20 31902[35:SSi:31901.0,696.0,30503.0] || -> . % 76.01/76.20 31903[35:Spt:31902.0,31894.0,31899.0] || m_main_v_state(s7,c_busy)* -> . % 76.01/76.20 31904[35:Spt:31902.0,31894.1] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.20 31908[35:Res:31904.0,61.1] always3(s8) || -> . % 76.01/76.20 31909[35:SSi:31908.0,697.0] || -> . % 76.01/76.20 31910[33:Spt:31909.0,30498.2,30502.0] || xuntil6(s6)*+ -> . % 76.01/76.20 31911[33:Spt:31909.0,30498.0,30498.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.01/76.20 31912[33:Res:53.1,31911.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.01/76.20 31914[34:Spt:31912.0] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.20 31916[34:Res:31914.0,61.1] always3(s6) || -> . % 76.01/76.20 31917[34:SSi:31916.0,695.0,30497.0] || -> . % 76.01/76.20 31918[34:Spt:31917.0,31912.0,31914.0] || m_main_v_state(s6,c_busy)* -> . % 76.01/76.20 31919[34:Spt:31917.0,31912.1] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.20 31923[34:Res:31919.0,61.1] always3(s7) || -> . % 76.01/76.20 31924[34:SSi:31923.0,696.0] || -> . % 76.01/76.20 31925[32:Spt:31924.0,30495.2,30496.0] || xuntil6(s5)*+ -> . % 76.01/76.20 31926[32:Spt:31924.0,30495.0,30495.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.01/76.20 31927[32:Res:53.1,31926.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.01/76.20 31929[33:Spt:31927.0] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.20 31931[33:Res:31929.0,61.1] always3(s5) || -> . % 76.01/76.20 31932[33:SSi:31931.0,694.0,30494.0] || -> . % 76.01/76.20 31933[33:Spt:31932.0,31927.0,31929.0] || m_main_v_state(s5,c_busy)* -> . % 76.01/76.20 31934[33:Spt:31932.0,31927.1] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.20 31938[33:Res:31934.0,61.1] always3(s6) || -> . % 76.01/76.20 31939[33:SSi:31938.0,695.0] || -> . % 76.01/76.20 31940[31:Spt:31939.0,30489.2,30493.0] || xuntil6(s4)*+ -> . % 76.01/76.20 31941[31:Spt:31939.0,30489.0,30489.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.01/76.20 31942[31:Res:53.1,31941.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.01/76.20 31947[32:Spt:31942.0] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.20 31949[32:Res:31947.0,61.1] always3(s4) || -> . % 76.01/76.20 31950[32:SSi:31949.0,693.0,30488.0] || -> . % 76.01/76.20 31951[32:Spt:31950.0,31942.0,31947.0] || m_main_v_state(s4,c_busy)* -> . % 76.01/76.20 31952[32:Spt:31950.0,31942.1] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.20 31956[32:Res:31952.0,61.1] always3(s5) || -> . % 76.01/76.20 31957[32:SSi:31956.0,694.0] || -> . % 76.01/76.20 31958[30:Spt:31957.0,30486.2,30487.0] || xuntil6(s3)*+ -> . % 76.01/76.20 31959[30:Spt:31957.0,30486.0,30486.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.01/76.20 31960[30:Res:53.1,31959.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.01/76.20 31962[31:Spt:31960.0] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.20 31964[31:Res:31962.0,61.1] always3(s3) || -> . % 76.01/76.20 31965[31:SSi:31964.0,692.0,30485.0] || -> . % 76.01/76.20 31966[31:Spt:31965.0,31960.0,31962.0] || m_main_v_state(s3,c_busy)* -> . % 76.01/76.20 31967[31:Spt:31965.0,31960.1] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.20 31971[31:Res:31967.0,61.1] always3(s4) || -> . % 76.01/76.20 31972[31:SSi:31971.0,693.0] || -> . % 76.01/76.20 31973[29:Spt:31972.0,30480.2,30484.0] || xuntil6(s2)*+ -> . % 76.01/76.20 31974[29:Spt:31972.0,30480.0,30480.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.01/76.20 31975[29:Res:53.1,31974.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.01/76.20 31977[30:Spt:31975.0] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.20 31979[30:Res:31977.0,61.1] always3(s2) || -> . % 76.01/76.20 31980[30:SSi:31979.0,691.0,30479.0] || -> . % 76.01/76.20 31981[30:Spt:31980.0,31975.0,31977.0] || m_main_v_state(s2,c_busy)* -> . % 76.01/76.20 31982[30:Spt:31980.0,31975.1] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.20 31986[30:Res:31982.0,61.1] always3(s3) || -> . % 76.01/76.20 31987[30:SSi:31986.0,692.0] || -> . % 76.01/76.20 31988[28:Spt:31987.0,30474.2,30478.0] || xuntil6(s1)*+ -> . % 76.01/76.20 31989[28:Spt:31987.0,30474.0,30474.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.01/76.20 31990[28:Res:53.1,31989.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.01/76.20 31995[29:Spt:31990.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.20 31997[29:Res:31995.0,61.1] always3(s1) || -> . % 76.01/76.20 31998[29:SSi:31997.0,690.0,30473.0] || -> . % 76.01/76.20 31999[29:Spt:31998.0,31990.0,31995.0] || m_main_v_state(s1,c_busy)* -> . % 76.01/76.20 32000[29:Spt:31998.0,31990.1] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.20 32005[29:Res:32000.0,61.1] always3(s2) || -> . % 76.01/76.20 32006[29:SSi:32005.0,691.0] || -> . % 76.01/76.20 32007[27:Spt:32006.0,74.0,30472.0] || xuntil6(s0)*+ -> . % 76.01/76.20 32008[27:Spt:32006.0,74.1] || -> node4(s0)*. % 76.01/76.20 32009[27:MRR:758.1,32007.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.20 32011[27:Res:32009.0,61.1] always3(s1) || -> . % 76.01/76.20 32012[27:SSi:32011.0,690.0] || -> . % 76.01/76.20 32013[26:Spt:32012.0,30462.0,30466.0] || trans(s49,s25)*+ -> . % 76.01/76.20 32014[26:Spt:32012.0,30462.1,30462.2,30462.3,30462.4,30462.5,30462.6,30462.7,30462.8,30462.9,30462.10,30462.11,30462.12,30462.13,30462.14,30462.15,30462.16,30462.17,30462.18,30462.19,30462.20,30462.21,30462.22,30462.23,30462.24,30462.25] || -> trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.01/76.20 32015[26:MRR:30464.0,32013.0] || -> trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.01/76.20 32017[26:MRR:30465.1,32013.0] xuntil6(s49) || -> trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.01/76.20 32018[27:Spt:32014.0] || -> trans(s49,s24)*. % 76.01/76.20 32019[27:Res:32018.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s24)*. % 76.01/76.20 32021[27:Res:32018.0,60.0] || -> node2(s49,s24)*. % 76.01/76.20 32022[27:SSi:32019.1,50.0,738.0] xuntil6(s49) || -> until2p7(s24)*. % 76.01/76.20 32023[27:Res:32021.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)*. % 76.01/76.20 32024[28:Spt:74.0] || -> xuntil6(s0)*. % 76.01/76.20 32025[28:MRR:176.0,32024.0] || -> until5(s1)*. % 76.01/76.20 32026[28:MRR:30927.0,32025.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.20 32030[29:Spt:32026.2] || -> xuntil6(s1)*. % 76.01/76.20 32031[29:MRR:175.0,32030.0] || -> until5(s2)*. % 76.01/76.20 32032[29:MRR:30920.0,32031.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.20 32033[30:Spt:32032.2] || -> xuntil6(s2)*. % 76.01/76.20 32034[30:MRR:174.0,32033.0] || -> until5(s3)*. % 76.01/76.20 32035[30:MRR:30916.0,32034.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.20 32036[31:Spt:32035.2] || -> xuntil6(s3)*. % 76.01/76.20 32037[31:MRR:173.0,32036.0] || -> until5(s4)*. % 76.01/76.20 32038[31:MRR:30912.0,32037.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.20 32039[32:Spt:32038.2] || -> xuntil6(s4)*. % 76.01/76.20 32040[32:MRR:172.0,32039.0] || -> until5(s5)*. % 76.01/76.20 32041[32:MRR:30908.0,32040.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.20 32045[33:Spt:32041.2] || -> xuntil6(s5)*. % 76.01/76.20 32046[33:MRR:171.0,32045.0] || -> until5(s6)*. % 76.01/76.20 32047[33:MRR:30907.0,32046.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.20 32048[34:Spt:32047.2] || -> xuntil6(s6)*. % 76.01/76.20 32049[34:MRR:170.0,32048.0] || -> until5(s7)*. % 76.01/76.20 32050[34:MRR:30900.0,32049.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.20 32054[35:Spt:32050.2] || -> xuntil6(s7)*. % 76.01/76.20 32055[35:MRR:169.0,32054.0] || -> until5(s8)*. % 76.01/76.20 32056[35:MRR:30896.0,32055.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.20 32057[36:Spt:32056.2] || -> xuntil6(s8)*. % 76.01/76.20 32058[36:MRR:168.0,32057.0] || -> until5(s9)*. % 76.01/76.20 32059[36:MRR:30892.0,32058.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.20 32063[37:Spt:32059.2] || -> xuntil6(s9)*. % 76.01/76.20 32064[37:MRR:167.0,32063.0] || -> until5(s10)*. % 76.01/76.20 32065[37:MRR:30888.0,32064.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.20 32066[38:Spt:32065.2] || -> xuntil6(s10)*. % 76.01/76.20 32067[38:MRR:166.0,32066.0] || -> until5(s11)*. % 76.01/76.20 32068[38:MRR:30887.0,32067.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.20 32072[39:Spt:32068.2] || -> xuntil6(s11)*. % 76.01/76.20 32073[39:MRR:165.0,32072.0] || -> until5(s12)*. % 76.01/76.20 32074[39:MRR:30880.0,32073.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.20 32075[40:Spt:32074.2] || -> xuntil6(s12)*. % 76.01/76.20 32076[40:MRR:164.0,32075.0] || -> until5(s13)*. % 76.01/76.20 32077[40:MRR:30876.0,32076.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.20 32081[41:Spt:32077.2] || -> xuntil6(s13)*. % 76.01/76.20 32082[41:MRR:163.0,32081.0] || -> until5(s14)*. % 76.01/76.20 32083[41:MRR:30872.0,32082.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.20 32084[42:Spt:32083.2] || -> xuntil6(s14)*. % 76.01/76.20 32085[42:MRR:162.0,32084.0] || -> until5(s15)*. % 76.01/76.20 32086[42:MRR:30868.0,32085.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.20 32090[43:Spt:32086.2] || -> xuntil6(s15)*. % 76.01/76.20 32091[43:MRR:161.0,32090.0] || -> until5(s16)*. % 76.01/76.20 32092[43:MRR:30867.0,32091.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.20 32093[44:Spt:32092.2] || -> xuntil6(s16)*. % 76.01/76.20 32094[44:MRR:160.0,32093.0] || -> until5(s17)*. % 76.01/76.20 32095[44:MRR:30860.0,32094.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.20 32099[45:Spt:32095.2] || -> xuntil6(s17)*. % 76.01/76.20 32100[45:MRR:159.0,32099.0] || -> until5(s18)*. % 76.01/76.20 32101[45:MRR:30856.0,32100.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.20 32102[46:Spt:32101.2] || -> xuntil6(s18)*. % 76.01/76.20 32103[46:MRR:158.0,32102.0] || -> until5(s19)*. % 76.01/76.20 32104[46:MRR:30852.0,32103.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.20 32108[47:Spt:32104.2] || -> xuntil6(s19)*. % 76.01/76.20 32109[47:MRR:157.0,32108.0] || -> until5(s20)*. % 76.01/76.20 32110[47:MRR:30848.0,32109.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.20 32111[48:Spt:32110.2] || -> xuntil6(s20)*. % 76.01/76.20 32112[48:MRR:156.0,32111.0] || -> until5(s21)*. % 76.01/76.20 32113[48:MRR:30847.0,32112.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.20 32117[49:Spt:32113.2] || -> xuntil6(s21)*. % 76.01/76.20 32118[49:MRR:155.0,32117.0] || -> until5(s22)*. % 76.01/76.20 32119[49:MRR:30840.0,32118.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.20 32120[50:Spt:32119.2] || -> xuntil6(s22)*. % 76.01/76.20 32121[50:MRR:154.0,32120.0] || -> until5(s23)*. % 76.01/76.20 32122[50:MRR:30836.0,32121.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.20 32126[51:Spt:32122.2] || -> xuntil6(s23)*. % 76.01/76.20 32127[51:MRR:153.0,32126.0] || -> until5(s24)*. % 76.01/76.20 32128[51:MRR:30832.0,32127.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.20 32129[52:Spt:32128.2] || -> xuntil6(s24)*. % 76.01/76.20 32130[52:MRR:152.0,32129.0] || -> until5(s25)*. % 76.01/76.20 32131[52:MRR:30831.0,32130.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.20 32135[53:Spt:32131.2] || -> xuntil6(s25)*. % 76.01/76.20 32136[53:MRR:151.0,32135.0] || -> until5(s26)*. % 76.01/76.20 32137[53:MRR:30830.0,32136.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.20 32138[54:Spt:32137.2] || -> xuntil6(s26)*. % 76.01/76.20 32139[54:MRR:150.0,32138.0] || -> until5(s27)*. % 76.01/76.20 32140[54:MRR:30829.0,32139.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.20 32144[55:Spt:32140.2] || -> xuntil6(s27)*. % 76.01/76.20 32145[55:MRR:149.0,32144.0] || -> until5(s28)*. % 76.01/76.20 32146[55:MRR:29274.0,32145.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.20 32147[56:Spt:32146.2] || -> xuntil6(s28)*. % 76.01/76.20 32148[56:MRR:148.0,32147.0] || -> until5(s29)*. % 76.01/76.20 32149[56:MRR:30928.0,32148.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.20 32153[57:Spt:32149.1] || -> m_main_v_state(s30,c_busy)*. % 76.01/76.20 32155[57:Res:32153.0,61.1] always3(s30) || -> . % 76.01/76.20 32156[57:SSi:32155.0,719.0] || -> . % 76.01/76.20 32157[57:Spt:32156.0,32149.1,32153.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.01/76.20 32158[57:Spt:32156.0,32149.0,32149.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 76.01/76.20 32160[57:MRR:831.2,32157.0] node4(s29) || m_main_v_state(s29,c_ready)* -> . % 76.01/76.20 32161[57:Res:53.1,32158.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 76.01/76.20 32163[58:Spt:32161.1] || -> xuntil6(s29)*. % 76.01/76.20 32164[58:MRR:147.0,32163.0] || -> until5(s30)*. % 76.01/76.20 32165[58:MRR:29383.0,32164.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.20 32170[59:Spt:32165.2] || -> xuntil6(s30)*. % 76.01/76.20 32171[59:MRR:146.0,32170.0] || -> until5(s31)*. % 76.01/76.20 32172[59:MRR:30932.0,32171.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.20 32173[60:Spt:32172.1] || -> m_main_v_state(s32,c_busy)*. % 76.01/76.20 32175[60:Res:32173.0,61.1] always3(s32) || -> . % 76.01/76.20 32176[60:SSi:32175.0,721.0] || -> . % 76.01/76.20 32177[60:Spt:32176.0,32172.1,32173.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.01/76.20 32178[60:Spt:32176.0,32172.0,32172.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.01/76.20 32180[60:MRR:825.2,32177.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.01/76.20 32181[60:Res:53.1,32178.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.01/76.20 32183[61:Spt:32181.1] || -> xuntil6(s31)*. % 76.01/76.20 32184[61:MRR:145.0,32183.0] || -> until5(s32)*. % 76.01/76.20 32185[61:MRR:29387.0,32184.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.20 32193[62:Spt:32185.2] || -> xuntil6(s32)*. % 76.01/76.20 32194[62:MRR:144.0,32193.0] || -> until5(s33)*. % 76.01/76.20 32195[62:MRR:30936.0,32194.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.20 32196[63:Spt:32195.1] || -> m_main_v_state(s34,c_busy)*. % 76.01/76.20 32198[63:Res:32196.0,61.1] always3(s34) || -> . % 76.01/76.20 32199[63:SSi:32198.0,723.0] || -> . % 76.01/76.20 32200[63:Spt:32199.0,32195.1,32196.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.01/76.20 32201[63:Spt:32199.0,32195.0,32195.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.01/76.20 32203[63:MRR:819.2,32200.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.01/76.20 32204[63:Res:53.1,32201.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.01/76.20 32209[64:Spt:32204.1] || -> xuntil6(s33)*. % 76.01/76.20 32210[64:MRR:143.0,32209.0] || -> until5(s34)*. % 76.01/76.20 32211[64:MRR:29394.0,32210.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.20 32213[65:Spt:32211.2] || -> xuntil6(s34)*. % 76.01/76.20 32214[65:MRR:142.0,32213.0] || -> until5(s35)*. % 76.01/76.20 32215[65:MRR:30940.0,32214.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.20 32216[66:Spt:32215.1] || -> m_main_v_state(s36,c_busy)*. % 76.01/76.20 32218[66:Res:32216.0,61.1] always3(s36) || -> . % 76.01/76.20 32219[66:SSi:32218.0,725.0] || -> . % 76.01/76.20 32220[66:Spt:32219.0,32215.1,32216.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.01/76.20 32221[66:Spt:32219.0,32215.0,32215.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.01/76.20 32223[66:MRR:813.2,32220.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.01/76.20 32224[66:Res:53.1,32221.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.01/76.20 32226[67:Spt:32224.1] || -> xuntil6(s35)*. % 76.01/76.20 32227[67:MRR:141.0,32226.0] || -> until5(s36)*. % 76.01/76.20 32228[67:MRR:29395.0,32227.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.20 32233[68:Spt:32228.2] || -> xuntil6(s36)*. % 76.01/76.20 32234[68:MRR:140.0,32233.0] || -> until5(s37)*. % 76.01/76.20 32235[68:MRR:30947.0,32234.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.20 32236[69:Spt:32235.1] || -> m_main_v_state(s38,c_busy)*. % 76.01/76.20 32238[69:Res:32236.0,61.1] always3(s38) || -> . % 76.01/76.20 32239[69:SSi:32238.0,727.0] || -> . % 76.01/76.20 32240[69:Spt:32239.0,32235.1,32236.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.01/76.20 32241[69:Spt:32239.0,32235.0,32235.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.01/76.20 32243[69:MRR:807.2,32240.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.01/76.20 32244[69:Res:53.1,32241.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.01/76.20 32246[70:Spt:32244.1] || -> xuntil6(s37)*. % 76.01/76.20 32247[70:MRR:139.0,32246.0] || -> until5(s38)*. % 76.01/76.20 32248[70:MRR:29399.0,32247.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.20 32256[71:Spt:32248.2] || -> xuntil6(s38)*. % 76.01/76.20 32257[71:MRR:138.0,32256.0] || -> until5(s39)*. % 76.01/76.20 32258[71:MRR:30948.0,32257.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.01/76.20 32259[72:Spt:32258.1] || -> m_main_v_state(s40,c_busy)*. % 76.01/76.20 32261[72:Res:32259.0,61.1] always3(s40) || -> . % 76.01/76.20 32262[72:SSi:32261.0,729.0] || -> . % 76.01/76.20 32263[72:Spt:32262.0,32258.1,32259.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.01/76.20 32264[72:Spt:32262.0,32258.0,32258.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.01/76.20 32266[72:MRR:801.2,32263.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.01/76.20 32267[72:Res:53.1,32264.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.01/76.20 32272[73:Spt:32267.1] || -> xuntil6(s39)*. % 76.01/76.20 32273[73:MRR:137.0,32272.0] || -> until5(s40)*. % 76.01/76.20 32274[73:MRR:29403.0,32273.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.01/76.20 32276[74:Spt:32274.2] || -> xuntil6(s40)*. % 76.01/76.20 32277[74:MRR:136.0,32276.0] || -> until5(s41)*. % 76.01/76.20 32278[74:MRR:30952.0,32277.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.01/76.20 32279[75:Spt:32278.1] || -> m_main_v_state(s42,c_busy)*. % 76.01/76.20 32281[75:Res:32279.0,61.1] always3(s42) || -> . % 76.01/76.20 32282[75:SSi:32281.0,731.0] || -> . % 76.01/76.20 32283[75:Spt:32282.0,32278.1,32279.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.01/76.20 32284[75:Spt:32282.0,32278.0,32278.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.01/76.20 32286[75:MRR:795.2,32283.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.01/76.20 32287[75:Res:53.1,32284.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.01/76.20 32289[76:Spt:32287.1] || -> xuntil6(s41)*. % 76.01/76.20 32290[76:MRR:135.0,32289.0] || -> until5(s42)*. % 76.01/76.20 32291[76:MRR:29407.0,32290.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.01/76.20 32296[77:Spt:32291.2] || -> xuntil6(s42)*. % 76.01/76.20 32297[77:MRR:134.0,32296.0] || -> until5(s43)*. % 76.01/76.20 32298[77:MRR:30956.0,32297.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.01/76.20 32299[78:Spt:32298.1] || -> m_main_v_state(s44,c_busy)*. % 76.01/76.20 32301[78:Res:32299.0,61.1] always3(s44) || -> . % 76.01/76.20 32302[78:SSi:32301.0,733.0] || -> . % 76.01/76.20 32303[78:Spt:32302.0,32298.1,32299.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.01/76.20 32304[78:Spt:32302.0,32298.0,32298.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.01/76.20 32306[78:MRR:789.2,32303.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.01/76.20 32307[78:Res:53.1,32304.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.01/76.20 32309[79:Spt:32307.1] || -> xuntil6(s43)*. % 76.01/76.20 32310[79:MRR:133.0,32309.0] || -> until5(s44)*. % 76.01/76.20 32311[79:MRR:29414.0,32310.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.01/76.20 32319[80:Spt:32311.2] || -> xuntil6(s44)*. % 76.01/76.20 32320[80:MRR:132.0,32319.0] || -> until5(s45)*. % 76.01/76.20 32321[80:MRR:30960.0,32320.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.01/76.20 32322[81:Spt:32321.1] || -> m_main_v_state(s46,c_busy)*. % 76.01/76.20 32324[81:Res:32322.0,61.1] always3(s46) || -> . % 76.01/76.20 32325[81:SSi:32324.0,735.0] || -> . % 76.01/76.20 32326[81:Spt:32325.0,32321.1,32322.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.01/76.20 32327[81:Spt:32325.0,32321.0,32321.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.01/76.20 32329[81:MRR:783.2,32326.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.01/76.20 32330[81:Res:53.1,32327.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.01/76.20 32335[82:Spt:32330.1] || -> xuntil6(s45)*. % 76.01/76.20 32336[82:MRR:131.0,32335.0] || -> until5(s46)*. % 76.01/76.20 32337[82:MRR:29415.0,32336.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.01/76.20 32339[83:Spt:32337.2] || -> xuntil6(s46)*. % 76.01/76.20 32340[83:MRR:130.0,32339.0] || -> until5(s47)*. % 76.01/76.20 32341[83:MRR:30964.0,32340.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.01/76.20 32342[84:Spt:32341.1] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.20 32344[84:Res:32342.0,61.1] always3(s48) || -> . % 76.01/76.20 32345[84:SSi:32344.0,737.0] || -> . % 76.01/76.20 32346[84:Spt:32345.0,32341.1,32342.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.01/76.20 32347[84:Spt:32345.0,32341.0,32341.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.01/76.20 32349[84:MRR:777.2,32346.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.01/76.20 32350[84:Res:53.1,32347.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.01/76.20 32352[85:Spt:32350.1] || -> xuntil6(s47)*. % 76.01/76.20 32353[85:MRR:129.0,32352.0] || -> until5(s48)*. % 76.01/76.20 32354[85:MRR:29419.0,32353.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.01/76.20 32359[86:Spt:32354.2] || -> xuntil6(s48)*. % 76.01/76.20 32360[86:MRR:128.0,32359.0] || -> until5(s49)*. % 76.01/76.20 32361[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.20 32365[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.20 32366[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.20 32367[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.20 32374[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.20 32375[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.20 32379[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.20 32383[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.20 32387[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.20 32394[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.20 32395[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.20 32399[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.20 32403[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.20 32407[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.20 32414[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.20 32415[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.20 32419[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.20 32423[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.20 32427[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.20 32434[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.20 32435[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.20 32439[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.20 32443[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.20 32447[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.20 32454[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.20 32455[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.20 32459[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.20 32463[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.20 32465[27:SoR:32023.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)*. % 76.01/76.20 32470[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.20 32474[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.20 32478[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.20 32485[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.20 32486[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.20 32490[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.01/76.20 32494[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.01/76.20 32498[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.01/76.20 32505[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.01/76.20 32506[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.01/76.20 32507[27:SoR:32465.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)* xuntil6(s49). % 76.01/76.20 32508[86:SSi:32507.0,50.0,738.0,32360.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s24,c_busy)* xuntil6(s49). % 76.01/76.20 32509[87:Spt:32508.1] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.20 32511[87:Res:32509.0,61.1] always3(s24) || -> . % 76.01/76.20 32512[87:SSi:32511.0,713.0,32127.0,32129.0] || -> . % 76.01/76.20 32513[87:Spt:32512.0,32508.1,32509.0] || m_main_v_state(s24,c_busy)*+ -> . % 76.01/76.20 32514[87:Spt:32512.0,32508.0,32508.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.01/76.20 32518[87:MRR:32465.2,32513.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.01/76.20 32519[87:Res:53.1,32514.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.01/76.20 32521[88:Spt:32519.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.20 32523[88:Res:32521.0,61.1] always3(s49) || -> . % 76.01/76.20 32524[88:SSi:32523.0,50.0,738.0,32360.0] || -> . % 76.01/76.20 32525[88:Spt:32524.0,32519.0,32521.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.01/76.20 32526[88:Spt:32524.0,32519.1] || -> xuntil6(s49)*. % 76.01/76.20 32527[88:MRR:32022.0,32526.0] || -> until2p7(s24)*. % 76.01/76.20 32528[88:MRR:220.0,32527.0] || -> until2p7(s25)* node4(s24). % 76.01/76.20 32530[88:MRR:774.2,32525.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.01/76.20 32531[89:Spt:32528.0] || -> until2p7(s25)*. % 76.01/76.20 32532[89:MRR:221.0,32531.0] || -> until2p7(s26)* node4(s25). % 76.01/76.20 32533[90:Spt:32532.0] || -> until2p7(s26)*. % 76.01/76.20 32534[90:MRR:222.0,32533.0] || -> until2p7(s27)* node4(s26). % 76.01/76.20 32535[91:Spt:32534.0] || -> until2p7(s27)*. % 76.01/76.20 32536[91:MRR:223.0,32535.0] || -> until2p7(s28)* node4(s27). % 76.01/76.20 32537[92:Spt:32536.0] || -> until2p7(s28)*. % 76.01/76.20 32538[92:MRR:224.0,32537.0] || -> until2p7(s29)* node4(s28). % 76.01/76.20 32539[93:Spt:32538.0] || -> until2p7(s29)*. % 76.01/76.20 32540[93:MRR:225.0,32539.0] || -> until2p7(s30)* node4(s29). % 76.01/76.20 32541[94:Spt:32540.0] || -> until2p7(s30)*. % 76.01/76.20 32542[94:MRR:226.0,32541.0] || -> until2p7(s31)* node4(s30). % 76.01/76.20 32543[95:Spt:32542.0] || -> until2p7(s31)*. % 76.01/76.20 32544[95:MRR:227.0,32543.0] || -> until2p7(s32)* node4(s31). % 76.01/76.20 32545[96:Spt:32544.0] || -> until2p7(s32)*. % 76.01/76.20 32546[96:MRR:228.0,32545.0] || -> until2p7(s33)* node4(s32). % 76.01/76.20 32547[97:Spt:32546.0] || -> until2p7(s33)*. % 76.01/76.20 32548[97:MRR:229.0,32547.0] || -> until2p7(s34)* node4(s33). % 76.01/76.20 32549[98:Spt:32548.0] || -> until2p7(s34)*. % 76.01/76.20 32550[98:MRR:230.0,32549.0] || -> until2p7(s35)* node4(s34). % 76.01/76.20 32551[99:Spt:32550.0] || -> until2p7(s35)*. % 76.01/76.20 32552[99:MRR:231.0,32551.0] || -> until2p7(s36)* node4(s35). % 76.01/76.20 32553[100:Spt:32552.0] || -> until2p7(s36)*. % 76.01/76.20 32554[100:MRR:232.0,32553.0] || -> until2p7(s37)* node4(s36). % 76.01/76.20 32555[101:Spt:32554.0] || -> until2p7(s37)*. % 76.01/76.20 32556[101:MRR:235.0,32555.0] || -> until2p7(s38)* node4(s37). % 76.01/76.20 32557[102:Spt:32556.0] || -> until2p7(s38)*. % 76.01/76.20 32558[102:MRR:236.0,32557.0] || -> until2p7(s39)* node4(s38). % 76.01/76.20 32559[103:Spt:32558.0] || -> until2p7(s39)*. % 76.01/76.20 32560[103:MRR:237.0,32559.0] || -> until2p7(s40)* node4(s39). % 76.01/76.20 32561[104:Spt:32560.0] || -> until2p7(s40)*. % 76.01/76.20 32562[104:MRR:238.0,32561.0] || -> until2p7(s41)* node4(s40). % 76.01/76.20 32563[105:Spt:32562.0] || -> until2p7(s41)*. % 76.01/76.20 32564[105:MRR:239.0,32563.0] || -> until2p7(s42)* node4(s41). % 76.01/76.20 32565[106:Spt:32564.0] || -> until2p7(s42)*. % 76.01/76.20 32566[106:MRR:240.0,32565.0] || -> until2p7(s43)* node4(s42). % 76.01/76.20 32567[107:Spt:32566.0] || -> until2p7(s43)*. % 76.01/76.20 32568[107:MRR:241.0,32567.0] || -> until2p7(s44)* node4(s43). % 76.01/76.20 32569[108:Spt:32568.0] || -> until2p7(s44)*. % 76.01/76.20 32570[108:MRR:539.0,32569.0] || -> until2p7(s45)* node4(s44). % 76.01/76.20 32571[109:Spt:32570.0] || -> until2p7(s45)*. % 76.01/76.20 32572[109:MRR:544.0,32571.0] || -> until2p7(s46)* node4(s45). % 76.01/76.20 32573[110:Spt:32572.0] || -> until2p7(s46)*. % 76.01/76.20 32574[110:MRR:549.0,32573.0] || -> until2p7(s47)* node4(s46). % 76.01/76.20 32575[111:Spt:32574.0] || -> until2p7(s47)*. % 76.01/76.20 32576[111:MRR:554.0,32575.0] || -> until2p7(s48)* node4(s47). % 76.01/76.20 32577[112:Spt:32576.0] || -> until2p7(s48)*. % 76.01/76.20 32578[112:MRR:559.0,32577.0] || -> until2p7(s49)* node4(s48). % 76.01/76.20 32579[113:Spt:32578.0] || -> until2p7(s49)*. % 76.01/76.20 32580[113:MRR:194.0,32579.0] || -> node4(s49)*. % 76.01/76.20 32581[113:MRR:32518.0,32580.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.01/76.20 32585[113:Res:53.1,32581.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.20 32587[113:MRR:32585.0,32525.0] || -> . % 76.01/76.20 32588[113:Spt:32587.0,32578.0,32579.0] || until2p7(s49)*+ -> . % 76.01/76.20 32589[113:Spt:32587.0,32578.1] || -> node4(s48)*. % 76.01/76.20 32590[113:MRR:32530.0,32589.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.01/76.20 32593[113:Res:53.1,32590.0] || -> m_main_v_state(s48,c_busy)*. % 76.01/76.20 32595[113:MRR:32593.0,32346.0] || -> . % 76.01/76.20 32596[112:Spt:32595.0,32576.0,32577.0] || until2p7(s48)*+ -> . % 76.01/76.20 32597[112:Spt:32595.0,32576.1] || -> node4(s47)*. % 76.01/76.20 32598[112:MRR:32349.0,32597.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.01/76.20 32601[112:Res:53.1,32598.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.20 32604[112:Res:32601.0,61.1] always3(s47) || -> . % 76.01/76.20 32605[112:SSi:32604.0,736.0,32340.0,32352.0,32575.0,32597.0] || -> . % 76.01/76.20 32606[111:Spt:32605.0,32574.0,32575.0] || until2p7(s47)*+ -> . % 76.01/76.20 32607[111:Spt:32605.0,32574.1] || -> node4(s46)*. % 76.01/76.20 32609[111:MRR:780.0,32607.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.01/76.20 32626[111:Res:53.1,32609.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.01/76.20 32628[111:MRR:32626.0,32326.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.20 32630[111:Res:32628.0,61.1] always3(s47) || -> . % 76.01/76.20 32631[111:SSi:32630.0,736.0,32340.0,32352.0] || -> . % 76.01/76.20 32632[110:Spt:32631.0,32572.0,32573.0] || until2p7(s46)*+ -> . % 76.01/76.20 32633[110:Spt:32631.0,32572.1] || -> node4(s45)*. % 76.01/76.20 32634[110:MRR:32329.0,32633.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.01/76.20 32637[110:Res:53.1,32634.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.20 32640[110:Res:32637.0,61.1] always3(s45) || -> . % 76.01/76.20 32641[110:SSi:32640.0,734.0,32320.0,32335.0,32571.0,32633.0] || -> . % 76.01/76.20 32642[109:Spt:32641.0,32570.0,32571.0] || until2p7(s45)*+ -> . % 76.01/76.20 32643[109:Spt:32641.0,32570.1] || -> node4(s44)*. % 76.01/76.20 32645[109:MRR:786.0,32643.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.01/76.20 32657[109:Res:53.1,32645.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.01/76.20 32659[109:MRR:32657.0,32303.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.20 32664[109:Res:32659.0,61.1] always3(s45) || -> . % 76.01/76.20 32665[109:SSi:32664.0,734.0,32320.0,32335.0] || -> . % 76.01/76.20 32666[108:Spt:32665.0,32568.0,32569.0] || until2p7(s44)*+ -> . % 76.01/76.20 32667[108:Spt:32665.0,32568.1] || -> node4(s43)*. % 76.01/76.20 32668[108:MRR:32306.0,32667.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.01/76.20 32671[108:Res:53.1,32668.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.20 32675[108:Res:32671.0,61.1] always3(s43) || -> . % 76.01/76.20 32676[108:SSi:32675.0,732.0,32297.0,32309.0,32567.0,32667.0] || -> . % 76.01/76.20 32677[107:Spt:32676.0,32566.0,32567.0] || until2p7(s43)*+ -> . % 76.01/76.20 32678[107:Spt:32676.0,32566.1] || -> node4(s42)*. % 76.01/76.20 32680[107:MRR:792.0,32678.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.01/76.20 32691[107:Res:53.1,32680.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.01/76.20 32693[107:MRR:32691.0,32283.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.20 32695[107:Res:32693.0,61.1] always3(s43) || -> . % 76.01/76.20 32696[107:SSi:32695.0,732.0,32297.0,32309.0] || -> . % 76.01/76.20 32697[106:Spt:32696.0,32564.0,32565.0] || until2p7(s42)*+ -> . % 76.01/76.20 32698[106:Spt:32696.0,32564.1] || -> node4(s41)*. % 76.01/76.20 32699[106:MRR:32286.0,32698.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.01/76.20 32703[106:Res:53.1,32699.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.20 32706[106:Res:32703.0,61.1] always3(s41) || -> . % 76.01/76.20 32707[106:SSi:32706.0,730.0,32277.0,32289.0,32563.0,32698.0] || -> . % 76.01/76.20 32708[105:Spt:32707.0,32562.0,32563.0] || until2p7(s41)*+ -> . % 76.01/76.20 32709[105:Spt:32707.0,32562.1] || -> node4(s40)*. % 76.01/76.20 32711[105:MRR:798.0,32709.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.01/76.20 32722[105:Res:53.1,32711.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.01/76.20 32724[105:MRR:32722.0,32263.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.20 32726[105:Res:32724.0,61.1] always3(s41) || -> . % 76.01/76.20 32727[105:SSi:32726.0,730.0,32277.0,32289.0] || -> . % 76.01/76.20 32728[104:Spt:32727.0,32560.0,32561.0] || until2p7(s40)*+ -> . % 76.01/76.20 32729[104:Spt:32727.0,32560.1] || -> node4(s39)*. % 76.01/76.20 32730[104:MRR:32266.0,32729.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.01/76.20 32733[104:Res:53.1,32730.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.20 32736[104:Res:32733.0,61.1] always3(s39) || -> . % 76.01/76.20 32737[104:SSi:32736.0,728.0,32257.0,32272.0,32559.0,32729.0] || -> . % 76.01/76.20 32738[103:Spt:32737.0,32558.0,32559.0] || until2p7(s39)*+ -> . % 76.01/76.20 32739[103:Spt:32737.0,32558.1] || -> node4(s38)*. % 76.01/76.20 32741[103:MRR:804.0,32739.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.01/76.20 32753[103:Res:53.1,32741.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.01/76.20 32755[103:MRR:32753.0,32240.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.20 32757[103:Res:32755.0,61.1] always3(s39) || -> . % 76.01/76.20 32758[103:SSi:32757.0,728.0,32257.0,32272.0] || -> . % 76.01/76.20 32759[102:Spt:32758.0,32556.0,32557.0] || until2p7(s38)*+ -> . % 76.01/76.20 32760[102:Spt:32758.0,32556.1] || -> node4(s37)*. % 76.01/76.20 32761[102:MRR:32243.0,32760.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.01/76.20 32764[102:Res:53.1,32761.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.20 32767[102:Res:32764.0,61.1] always3(s37) || -> . % 76.01/76.20 32768[102:SSi:32767.0,726.0,32234.0,32246.0,32555.0,32760.0] || -> . % 76.01/76.20 32769[101:Spt:32768.0,32554.0,32555.0] || until2p7(s37)*+ -> . % 76.01/76.20 32770[101:Spt:32768.0,32554.1] || -> node4(s36)*. % 76.01/76.20 32772[101:MRR:810.0,32770.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.01/76.20 32784[101:Res:53.1,32772.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.01/76.20 32786[101:MRR:32784.0,32220.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.20 32791[101:Res:32786.0,61.1] always3(s37) || -> . % 76.01/76.20 32792[101:SSi:32791.0,726.0,32234.0,32246.0] || -> . % 76.01/76.20 32793[100:Spt:32792.0,32552.0,32553.0] || until2p7(s36)*+ -> . % 76.01/76.20 32794[100:Spt:32792.0,32552.1] || -> node4(s35)*. % 76.01/76.20 32795[100:MRR:32223.0,32794.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.01/76.20 32798[100:Res:53.1,32795.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.20 32802[100:Res:32798.0,61.1] always3(s35) || -> . % 76.01/76.20 32803[100:SSi:32802.0,724.0,32214.0,32226.0,32551.0,32794.0] || -> . % 76.01/76.20 32804[99:Spt:32803.0,32550.0,32551.0] || until2p7(s35)*+ -> . % 76.01/76.20 32805[99:Spt:32803.0,32550.1] || -> node4(s34)*. % 76.01/76.20 32807[99:MRR:816.0,32805.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.01/76.20 32818[99:Res:53.1,32807.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.01/76.20 32820[99:MRR:32818.0,32200.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.20 32822[99:Res:32820.0,61.1] always3(s35) || -> . % 76.01/76.20 32823[99:SSi:32822.0,724.0,32214.0,32226.0] || -> . % 76.01/76.20 32824[98:Spt:32823.0,32548.0,32549.0] || until2p7(s34)*+ -> . % 76.01/76.20 32825[98:Spt:32823.0,32548.1] || -> node4(s33)*. % 76.01/76.20 32826[98:MRR:32203.0,32825.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.01/76.20 32830[98:Res:53.1,32826.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.20 32833[98:Res:32830.0,61.1] always3(s33) || -> . % 76.01/76.20 32834[98:SSi:32833.0,722.0,32194.0,32209.0,32547.0,32825.0] || -> . % 76.01/76.20 32835[97:Spt:32834.0,32546.0,32547.0] || until2p7(s33)*+ -> . % 76.01/76.20 32836[97:Spt:32834.0,32546.1] || -> node4(s32)*. % 76.01/76.20 32838[97:MRR:822.0,32836.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.01/76.20 32849[97:Res:53.1,32838.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.01/76.20 32851[97:MRR:32849.0,32177.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.20 32853[97:Res:32851.0,61.1] always3(s33) || -> . % 76.01/76.20 32854[97:SSi:32853.0,722.0,32194.0,32209.0] || -> . % 76.01/76.20 32855[96:Spt:32854.0,32544.0,32545.0] || until2p7(s32)*+ -> . % 76.01/76.20 32856[96:Spt:32854.0,32544.1] || -> node4(s31)*. % 76.01/76.20 32857[96:MRR:32180.0,32856.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.01/76.20 32860[96:Res:53.1,32857.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.20 32863[96:Res:32860.0,61.1] always3(s31) || -> . % 76.01/76.20 32864[96:SSi:32863.0,720.0,32171.0,32183.0,32543.0,32856.0] || -> . % 76.01/76.20 32865[95:Spt:32864.0,32542.0,32543.0] || until2p7(s31)*+ -> . % 76.01/76.20 32866[95:Spt:32864.0,32542.1] || -> node4(s30)*. % 76.01/76.20 32868[95:MRR:828.0,32866.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.01/76.20 32880[95:Res:53.1,32868.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.01/76.20 32882[95:MRR:32880.0,32157.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.20 32884[95:Res:32882.0,61.1] always3(s31) || -> . % 76.01/76.20 32885[95:SSi:32884.0,720.0,32171.0,32183.0] || -> . % 76.01/76.20 32886[94:Spt:32885.0,32540.0,32541.0] || until2p7(s30)*+ -> . % 76.01/76.20 32887[94:Spt:32885.0,32540.1] || -> node4(s29)*. % 76.01/76.20 32888[94:MRR:32160.0,32887.0] || m_main_v_state(s29,c_ready)*+ -> . % 76.01/76.20 32891[94:Res:53.1,32888.0] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.20 32894[94:Res:32891.0,61.1] always3(s29) || -> . % 76.01/76.20 32895[94:SSi:32894.0,718.0,32148.0,32163.0,32539.0,32887.0] || -> . % 76.01/76.20 32896[93:Spt:32895.0,32538.0,32539.0] || until2p7(s29)*+ -> . % 76.01/76.20 32897[93:Spt:32895.0,32538.1] || -> node4(s28)*. % 76.01/76.20 32899[93:MRR:834.0,32897.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.01/76.20 32911[93:Res:53.1,32899.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.01/76.20 32916[94:Spt:32911.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.20 32918[94:Res:32916.0,61.1] always3(s28) || -> . % 76.01/76.20 32919[94:SSi:32918.0,717.0,32145.0,32147.0,32537.0,32897.0] || -> . % 76.01/76.20 32920[94:Spt:32919.0,32911.0,32916.0] || m_main_v_state(s28,c_busy)* -> . % 76.01/76.20 32921[94:Spt:32919.0,32911.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.20 32925[94:Res:32921.0,61.1] always3(s29) || -> . % 76.01/76.20 32926[94:SSi:32925.0,718.0,32148.0,32163.0] || -> . % 76.01/76.20 32927[92:Spt:32926.0,32536.0,32537.0] || until2p7(s28)*+ -> . % 76.01/76.20 32928[92:Spt:32926.0,32536.1] || -> node4(s27)*. % 76.01/76.20 32930[92:MRR:837.0,32928.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.01/76.20 32937[92:Res:53.1,32930.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.01/76.20 32939[93:Spt:32937.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.20 32941[93:Res:32939.0,61.1] always3(s27) || -> . % 76.01/76.20 32942[93:SSi:32941.0,716.0,32139.0,32144.0,32535.0,32928.0] || -> . % 76.01/76.20 32943[93:Spt:32942.0,32937.0,32939.0] || m_main_v_state(s27,c_busy)* -> . % 76.01/76.20 32944[93:Spt:32942.0,32937.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.20 32948[93:Res:32944.0,61.1] always3(s28) || -> . % 76.01/76.20 32949[93:SSi:32948.0,717.0,32145.0,32147.0] || -> . % 76.01/76.20 32950[91:Spt:32949.0,32534.0,32535.0] || until2p7(s27)*+ -> . % 76.01/76.20 32951[91:Spt:32949.0,32534.1] || -> node4(s26)*. % 76.01/76.20 32953[91:MRR:840.0,32951.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.01/76.20 32956[91:Res:53.1,32953.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.01/76.20 32961[92:Spt:32956.0] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.20 32963[92:Res:32961.0,61.1] always3(s26) || -> . % 76.01/76.20 32964[92:SSi:32963.0,715.0,32136.0,32138.0,32533.0,32951.0] || -> . % 76.01/76.20 32965[92:Spt:32964.0,32956.0,32961.0] || m_main_v_state(s26,c_busy)* -> . % 76.01/76.20 32966[92:Spt:32964.0,32956.1] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.20 32970[92:Res:32966.0,61.1] always3(s27) || -> . % 76.01/76.20 32971[92:SSi:32970.0,716.0,32139.0,32144.0] || -> . % 76.01/76.20 32972[90:Spt:32971.0,32532.0,32533.0] || until2p7(s26)*+ -> . % 76.01/76.20 32973[90:Spt:32971.0,32532.1] || -> node4(s25)*. % 76.01/76.20 32975[90:MRR:843.0,32973.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.01/76.20 32978[90:Res:53.1,32975.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.01/76.20 32980[91:Spt:32978.0] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.20 32982[91:Res:32980.0,61.1] always3(s25) || -> . % 76.01/76.20 32983[91:SSi:32982.0,714.0,32130.0,32135.0,32531.0,32973.0] || -> . % 76.01/76.20 32984[91:Spt:32983.0,32978.0,32980.0] || m_main_v_state(s25,c_busy)* -> . % 76.01/76.20 32985[91:Spt:32983.0,32978.1] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.20 32989[91:Res:32985.0,61.1] always3(s26) || -> . % 76.01/76.20 32990[91:SSi:32989.0,715.0,32136.0,32138.0] || -> . % 76.01/76.20 32991[89:Spt:32990.0,32528.0,32531.0] || until2p7(s25)*+ -> . % 76.01/76.20 32992[89:Spt:32990.0,32528.1] || -> node4(s24)*. % 76.01/76.20 32994[89:MRR:846.0,32992.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.01/76.20 32997[89:Res:53.1,32994.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.01/76.20 32999[89:MRR:32997.0,32513.0] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.20 33001[89:Res:32999.0,61.1] always3(s25) || -> . % 76.01/76.20 33002[89:SSi:33001.0,714.0,32130.0,32135.0] || -> . % 76.01/76.20 33003[86:Spt:33002.0,32354.2,32359.0] || xuntil6(s48)*+ -> . % 76.01/76.20 33004[86:Spt:33002.0,32354.0,32354.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.01/76.20 33005[86:Res:53.1,33004.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.01/76.20 33007[86:MRR:33005.0,32346.0] || -> m_main_v_state(s49,c_busy)*. % 76.01/76.20 33010[86:Res:33007.0,61.1] always3(s49) || -> . % 76.01/76.20 33011[86:SSi:33010.0,50.0,738.0] || -> . % 76.01/76.20 33012[85:Spt:33011.0,32350.1,32352.0] || xuntil6(s47)* -> . % 76.01/76.20 33013[85:Spt:33011.0,32350.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.20 33016[85:Res:33013.0,61.1] always3(s47) || -> . % 76.01/76.20 33017[85:SSi:33016.0,736.0,32340.0] || -> . % 76.01/76.20 33018[83:Spt:33017.0,32337.2,32339.0] || xuntil6(s46)*+ -> . % 76.01/76.20 33019[83:Spt:33017.0,32337.0,32337.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.01/76.20 33020[83:Res:53.1,33019.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.01/76.20 33022[83:MRR:33020.0,32326.0] || -> m_main_v_state(s47,c_busy)*. % 76.01/76.20 33024[83:Res:33022.0,61.1] always3(s47) || -> . % 76.01/76.20 33025[83:SSi:33024.0,736.0] || -> . % 76.01/76.20 33026[82:Spt:33025.0,32330.1,32335.0] || xuntil6(s45)* -> . % 76.01/76.20 33027[82:Spt:33025.0,32330.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.20 33030[82:Res:33027.0,61.1] always3(s45) || -> . % 76.01/76.20 33031[82:SSi:33030.0,734.0,32320.0] || -> . % 76.01/76.20 33032[80:Spt:33031.0,32311.2,32319.0] || xuntil6(s44)*+ -> . % 76.01/76.20 33033[80:Spt:33031.0,32311.0,32311.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.01/76.20 33034[80:Res:53.1,33033.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.01/76.20 33036[80:MRR:33034.0,32303.0] || -> m_main_v_state(s45,c_busy)*. % 76.01/76.20 33039[80:Res:33036.0,61.1] always3(s45) || -> . % 76.01/76.20 33040[80:SSi:33039.0,734.0] || -> . % 76.01/76.20 33041[79:Spt:33040.0,32307.1,32309.0] || xuntil6(s43)* -> . % 76.01/76.20 33042[79:Spt:33040.0,32307.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.20 33045[79:Res:33042.0,61.1] always3(s43) || -> . % 76.01/76.20 33046[79:SSi:33045.0,732.0,32297.0] || -> . % 76.01/76.20 33047[77:Spt:33046.0,32291.2,32296.0] || xuntil6(s42)*+ -> . % 76.01/76.20 33048[77:Spt:33046.0,32291.0,32291.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.01/76.20 33049[77:Res:53.1,33048.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.01/76.20 33051[77:MRR:33049.0,32283.0] || -> m_main_v_state(s43,c_busy)*. % 76.01/76.20 33053[77:Res:33051.0,61.1] always3(s43) || -> . % 76.01/76.20 33054[77:SSi:33053.0,732.0] || -> . % 76.01/76.20 33055[76:Spt:33054.0,32287.1,32289.0] || xuntil6(s41)* -> . % 76.01/76.20 33056[76:Spt:33054.0,32287.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.20 33059[76:Res:33056.0,61.1] always3(s41) || -> . % 76.01/76.20 33060[76:SSi:33059.0,730.0,32277.0] || -> . % 76.01/76.20 33061[74:Spt:33060.0,32274.2,32276.0] || xuntil6(s40)*+ -> . % 76.01/76.20 33062[74:Spt:33060.0,32274.0,32274.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.01/76.20 33063[74:Res:53.1,33062.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.01/76.20 33065[74:MRR:33063.0,32263.0] || -> m_main_v_state(s41,c_busy)*. % 76.01/76.20 33067[74:Res:33065.0,61.1] always3(s41) || -> . % 76.01/76.20 33068[74:SSi:33067.0,730.0] || -> . % 76.01/76.20 33069[73:Spt:33068.0,32267.1,32272.0] || xuntil6(s39)* -> . % 76.01/76.20 33070[73:Spt:33068.0,32267.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.20 33073[73:Res:33070.0,61.1] always3(s39) || -> . % 76.01/76.20 33074[73:SSi:33073.0,728.0,32257.0] || -> . % 76.01/76.20 33075[71:Spt:33074.0,32248.2,32256.0] || xuntil6(s38)*+ -> . % 76.01/76.20 33076[71:Spt:33074.0,32248.0,32248.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.01/76.20 33077[71:Res:53.1,33076.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.01/76.20 33079[71:MRR:33077.0,32240.0] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.20 33081[71:Res:33079.0,61.1] always3(s39) || -> . % 76.01/76.20 33082[71:SSi:33081.0,728.0] || -> . % 76.01/76.20 33083[70:Spt:33082.0,32244.1,32246.0] || xuntil6(s37)* -> . % 76.01/76.20 33084[70:Spt:33082.0,32244.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.20 33087[70:Res:33084.0,61.1] always3(s37) || -> . % 76.01/76.20 33088[70:SSi:33087.0,726.0,32234.0] || -> . % 76.01/76.20 33089[68:Spt:33088.0,32228.2,32233.0] || xuntil6(s36)*+ -> . % 76.01/76.20 33090[68:Spt:33088.0,32228.0,32228.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.01/76.20 33091[68:Res:53.1,33090.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.01/76.20 33093[68:MRR:33091.0,32220.0] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.20 33095[68:Res:33093.0,61.1] always3(s37) || -> . % 76.01/76.20 33096[68:SSi:33095.0,726.0] || -> . % 76.01/76.20 33097[67:Spt:33096.0,32224.1,32226.0] || xuntil6(s35)* -> . % 76.01/76.20 33098[67:Spt:33096.0,32224.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.20 33101[67:Res:33098.0,61.1] always3(s35) || -> . % 76.01/76.20 33102[67:SSi:33101.0,724.0,32214.0] || -> . % 76.01/76.20 33103[65:Spt:33102.0,32211.2,32213.0] || xuntil6(s34)*+ -> . % 76.01/76.20 33104[65:Spt:33102.0,32211.0,32211.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.01/76.20 33105[65:Res:53.1,33104.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.01/76.20 33107[65:MRR:33105.0,32200.0] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.20 33109[65:Res:33107.0,61.1] always3(s35) || -> . % 76.01/76.20 33110[65:SSi:33109.0,724.0] || -> . % 76.01/76.20 33111[64:Spt:33110.0,32204.1,32209.0] || xuntil6(s33)* -> . % 76.01/76.20 33112[64:Spt:33110.0,32204.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.20 33115[64:Res:33112.0,61.1] always3(s33) || -> . % 76.01/76.20 33116[64:SSi:33115.0,722.0,32194.0] || -> . % 76.01/76.20 33117[62:Spt:33116.0,32185.2,32193.0] || xuntil6(s32)*+ -> . % 76.01/76.20 33118[62:Spt:33116.0,32185.0,32185.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.01/76.20 33119[62:Res:53.1,33118.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.01/76.20 33121[62:MRR:33119.0,32177.0] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.20 33123[62:Res:33121.0,61.1] always3(s33) || -> . % 76.01/76.20 33124[62:SSi:33123.0,722.0] || -> . % 76.01/76.20 33125[61:Spt:33124.0,32181.1,32183.0] || xuntil6(s31)* -> . % 76.01/76.20 33126[61:Spt:33124.0,32181.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.20 33129[61:Res:33126.0,61.1] always3(s31) || -> . % 76.01/76.20 33130[61:SSi:33129.0,720.0,32171.0] || -> . % 76.01/76.20 33131[59:Spt:33130.0,32165.2,32170.0] || xuntil6(s30)*+ -> . % 76.01/76.20 33132[59:Spt:33130.0,32165.0,32165.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.01/76.20 33133[59:Res:53.1,33132.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.01/76.20 33135[59:MRR:33133.0,32157.0] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.20 33137[59:Res:33135.0,61.1] always3(s31) || -> . % 76.01/76.20 33138[59:SSi:33137.0,720.0] || -> . % 76.01/76.20 33139[58:Spt:33138.0,32161.1,32163.0] || xuntil6(s29)* -> . % 76.01/76.20 33140[58:Spt:33138.0,32161.0] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.20 33143[58:Res:33140.0,61.1] always3(s29) || -> . % 76.01/76.20 33144[58:SSi:33143.0,718.0,32148.0] || -> . % 76.01/76.20 33145[56:Spt:33144.0,32146.2,32147.0] || xuntil6(s28)*+ -> . % 76.01/76.20 33146[56:Spt:33144.0,32146.0,32146.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.01/76.20 33147[56:Res:53.1,33146.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.01/76.20 33149[57:Spt:33147.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.20 33151[57:Res:33149.0,61.1] always3(s29) || -> . % 76.01/76.20 33152[57:SSi:33151.0,718.0] || -> . % 76.01/76.20 33153[57:Spt:33152.0,33147.1,33149.0] || m_main_v_state(s29,c_busy)* -> . % 76.01/76.20 33154[57:Spt:33152.0,33147.0] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.20 33157[57:Res:33154.0,61.1] always3(s28) || -> . % 76.01/76.20 33158[57:SSi:33157.0,717.0,32145.0] || -> . % 76.01/76.20 33159[55:Spt:33158.0,32140.2,32144.0] || xuntil6(s27)*+ -> . % 76.01/76.20 33160[55:Spt:33158.0,32140.0,32140.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.01/76.20 33161[55:Res:53.1,33160.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.01/76.20 33163[56:Spt:33161.1] || -> m_main_v_state(s28,c_busy)*. % 76.01/76.20 33165[56:Res:33163.0,61.1] always3(s28) || -> . % 76.01/76.20 33166[56:SSi:33165.0,717.0] || -> . % 76.01/76.20 33167[56:Spt:33166.0,33161.1,33163.0] || m_main_v_state(s28,c_busy)* -> . % 76.01/76.20 33168[56:Spt:33166.0,33161.0] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.20 33171[56:Res:33168.0,61.1] always3(s27) || -> . % 76.01/76.20 33172[56:SSi:33171.0,716.0,32139.0] || -> . % 76.01/76.20 33173[54:Spt:33172.0,32137.2,32138.0] || xuntil6(s26)*+ -> . % 76.01/76.20 33174[54:Spt:33172.0,32137.0,32137.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.01/76.20 33175[54:Res:53.1,33174.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.01/76.20 33177[55:Spt:33175.1] || -> m_main_v_state(s27,c_busy)*. % 76.01/76.20 33179[55:Res:33177.0,61.1] always3(s27) || -> . % 76.01/76.20 33180[55:SSi:33179.0,716.0] || -> . % 76.01/76.20 33181[55:Spt:33180.0,33175.1,33177.0] || m_main_v_state(s27,c_busy)* -> . % 76.01/76.20 33182[55:Spt:33180.0,33175.0] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.20 33185[55:Res:33182.0,61.1] always3(s26) || -> . % 76.01/76.20 33186[55:SSi:33185.0,715.0,32136.0] || -> . % 76.01/76.20 33187[53:Spt:33186.0,32131.2,32135.0] || xuntil6(s25)*+ -> . % 76.01/76.20 33188[53:Spt:33186.0,32131.0,32131.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.01/76.20 33189[53:Res:53.1,33188.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.01/76.20 33191[54:Spt:33189.1] || -> m_main_v_state(s26,c_busy)*. % 76.01/76.20 33193[54:Res:33191.0,61.1] always3(s26) || -> . % 76.01/76.20 33194[54:SSi:33193.0,715.0] || -> . % 76.01/76.20 33195[54:Spt:33194.0,33189.1,33191.0] || m_main_v_state(s26,c_busy)* -> . % 76.01/76.20 33196[54:Spt:33194.0,33189.0] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.20 33199[54:Res:33196.0,61.1] always3(s25) || -> . % 76.01/76.20 33200[54:SSi:33199.0,714.0,32130.0] || -> . % 76.01/76.20 33201[52:Spt:33200.0,32128.2,32129.0] || xuntil6(s24)*+ -> . % 76.01/76.20 33202[52:Spt:33200.0,32128.0,32128.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.01/76.20 33203[52:Res:53.1,33202.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.01/76.20 33205[53:Spt:33203.1] || -> m_main_v_state(s25,c_busy)*. % 76.01/76.20 33207[53:Res:33205.0,61.1] always3(s25) || -> . % 76.01/76.20 33208[53:SSi:33207.0,714.0] || -> . % 76.01/76.20 33209[53:Spt:33208.0,33203.1,33205.0] || m_main_v_state(s25,c_busy)* -> . % 76.01/76.20 33210[53:Spt:33208.0,33203.0] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.20 33213[53:Res:33210.0,61.1] always3(s24) || -> . % 76.01/76.20 33214[53:SSi:33213.0,713.0,32127.0] || -> . % 76.01/76.20 33215[51:Spt:33214.0,32122.2,32126.0] || xuntil6(s23)*+ -> . % 76.01/76.20 33216[51:Spt:33214.0,32122.0,32122.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.01/76.20 33217[51:Res:53.1,33216.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.01/76.20 33219[52:Spt:33217.0] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.20 33221[52:Res:33219.0,61.1] always3(s23) || -> . % 76.01/76.20 33222[52:SSi:33221.0,712.0,32121.0] || -> . % 76.01/76.20 33223[52:Spt:33222.0,33217.0,33219.0] || m_main_v_state(s23,c_busy)* -> . % 76.01/76.20 33224[52:Spt:33222.0,33217.1] || -> m_main_v_state(s24,c_busy)*. % 76.01/76.20 33228[52:Res:33224.0,61.1] always3(s24) || -> . % 76.01/76.20 33229[52:SSi:33228.0,713.0] || -> . % 76.01/76.20 33230[50:Spt:33229.0,32119.2,32120.0] || xuntil6(s22)*+ -> . % 76.01/76.20 33231[50:Spt:33229.0,32119.0,32119.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.01/76.20 33232[50:Res:53.1,33231.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.01/76.20 33234[51:Spt:33232.0] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.20 33236[51:Res:33234.0,61.1] always3(s22) || -> . % 76.01/76.20 33237[51:SSi:33236.0,711.0,32118.0] || -> . % 76.01/76.20 33238[51:Spt:33237.0,33232.0,33234.0] || m_main_v_state(s22,c_busy)* -> . % 76.01/76.20 33239[51:Spt:33237.0,33232.1] || -> m_main_v_state(s23,c_busy)*. % 76.01/76.20 33243[51:Res:33239.0,61.1] always3(s23) || -> . % 76.01/76.20 33244[51:SSi:33243.0,712.0] || -> . % 76.01/76.20 33245[49:Spt:33244.0,32113.2,32117.0] || xuntil6(s21)*+ -> . % 76.01/76.20 33246[49:Spt:33244.0,32113.0,32113.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.01/76.20 33247[49:Res:53.1,33246.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.01/76.20 33249[50:Spt:33247.0] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.20 33251[50:Res:33249.0,61.1] always3(s21) || -> . % 76.01/76.20 33252[50:SSi:33251.0,710.0,32112.0] || -> . % 76.01/76.20 33253[50:Spt:33252.0,33247.0,33249.0] || m_main_v_state(s21,c_busy)* -> . % 76.01/76.20 33254[50:Spt:33252.0,33247.1] || -> m_main_v_state(s22,c_busy)*. % 76.01/76.20 33258[50:Res:33254.0,61.1] always3(s22) || -> . % 76.01/76.20 33259[50:SSi:33258.0,711.0] || -> . % 76.01/76.20 33260[48:Spt:33259.0,32110.2,32111.0] || xuntil6(s20)*+ -> . % 76.01/76.20 33261[48:Spt:33259.0,32110.0,32110.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.01/76.20 33262[48:Res:53.1,33261.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.01/76.20 33267[49:Spt:33262.0] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.20 33269[49:Res:33267.0,61.1] always3(s20) || -> . % 76.01/76.20 33270[49:SSi:33269.0,709.0,32109.0] || -> . % 76.01/76.20 33271[49:Spt:33270.0,33262.0,33267.0] || m_main_v_state(s20,c_busy)* -> . % 76.01/76.20 33272[49:Spt:33270.0,33262.1] || -> m_main_v_state(s21,c_busy)*. % 76.01/76.20 33276[49:Res:33272.0,61.1] always3(s21) || -> . % 76.01/76.20 33277[49:SSi:33276.0,710.0] || -> . % 76.01/76.20 33278[47:Spt:33277.0,32104.2,32108.0] || xuntil6(s19)*+ -> . % 76.01/76.20 33279[47:Spt:33277.0,32104.0,32104.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.01/76.20 33280[47:Res:53.1,33279.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.01/76.20 33282[48:Spt:33280.0] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.20 33284[48:Res:33282.0,61.1] always3(s19) || -> . % 76.01/76.20 33285[48:SSi:33284.0,708.0,32103.0] || -> . % 76.01/76.20 33286[48:Spt:33285.0,33280.0,33282.0] || m_main_v_state(s19,c_busy)* -> . % 76.01/76.20 33287[48:Spt:33285.0,33280.1] || -> m_main_v_state(s20,c_busy)*. % 76.01/76.20 33291[48:Res:33287.0,61.1] always3(s20) || -> . % 76.01/76.20 33292[48:SSi:33291.0,709.0] || -> . % 76.01/76.20 33293[46:Spt:33292.0,32101.2,32102.0] || xuntil6(s18)*+ -> . % 76.01/76.20 33294[46:Spt:33292.0,32101.0,32101.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.01/76.20 33295[46:Res:53.1,33294.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.01/76.20 33297[47:Spt:33295.0] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.20 33299[47:Res:33297.0,61.1] always3(s18) || -> . % 76.01/76.20 33300[47:SSi:33299.0,707.0,32100.0] || -> . % 76.01/76.20 33301[47:Spt:33300.0,33295.0,33297.0] || m_main_v_state(s18,c_busy)* -> . % 76.01/76.20 33302[47:Spt:33300.0,33295.1] || -> m_main_v_state(s19,c_busy)*. % 76.01/76.20 33306[47:Res:33302.0,61.1] always3(s19) || -> . % 76.01/76.20 33307[47:SSi:33306.0,708.0] || -> . % 76.01/76.20 33308[45:Spt:33307.0,32095.2,32099.0] || xuntil6(s17)*+ -> . % 76.01/76.20 33309[45:Spt:33307.0,32095.0,32095.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.01/76.20 33310[45:Res:53.1,33309.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.01/76.20 33315[46:Spt:33310.0] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.20 33317[46:Res:33315.0,61.1] always3(s17) || -> . % 76.01/76.20 33318[46:SSi:33317.0,706.0,32094.0] || -> . % 76.01/76.20 33319[46:Spt:33318.0,33310.0,33315.0] || m_main_v_state(s17,c_busy)* -> . % 76.01/76.20 33320[46:Spt:33318.0,33310.1] || -> m_main_v_state(s18,c_busy)*. % 76.01/76.20 33324[46:Res:33320.0,61.1] always3(s18) || -> . % 76.01/76.20 33325[46:SSi:33324.0,707.0] || -> . % 76.01/76.20 33326[44:Spt:33325.0,32092.2,32093.0] || xuntil6(s16)*+ -> . % 76.01/76.20 33327[44:Spt:33325.0,32092.0,32092.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.01/76.20 33328[44:Res:53.1,33327.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.01/76.20 33330[45:Spt:33328.0] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.20 33332[45:Res:33330.0,61.1] always3(s16) || -> . % 76.01/76.20 33333[45:SSi:33332.0,705.0,32091.0] || -> . % 76.01/76.20 33334[45:Spt:33333.0,33328.0,33330.0] || m_main_v_state(s16,c_busy)* -> . % 76.01/76.20 33335[45:Spt:33333.0,33328.1] || -> m_main_v_state(s17,c_busy)*. % 76.01/76.20 33339[45:Res:33335.0,61.1] always3(s17) || -> . % 76.01/76.20 33340[45:SSi:33339.0,706.0] || -> . % 76.01/76.20 33341[43:Spt:33340.0,32086.2,32090.0] || xuntil6(s15)*+ -> . % 76.01/76.20 33342[43:Spt:33340.0,32086.0,32086.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.01/76.20 33343[43:Res:53.1,33342.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.01/76.20 33345[44:Spt:33343.0] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.20 33347[44:Res:33345.0,61.1] always3(s15) || -> . % 76.01/76.20 33348[44:SSi:33347.0,704.0,32085.0] || -> . % 76.01/76.20 33349[44:Spt:33348.0,33343.0,33345.0] || m_main_v_state(s15,c_busy)* -> . % 76.01/76.20 33350[44:Spt:33348.0,33343.1] || -> m_main_v_state(s16,c_busy)*. % 76.01/76.20 33354[44:Res:33350.0,61.1] always3(s16) || -> . % 76.01/76.20 33355[44:SSi:33354.0,705.0] || -> . % 76.01/76.20 33356[42:Spt:33355.0,32083.2,32084.0] || xuntil6(s14)*+ -> . % 76.01/76.20 33357[42:Spt:33355.0,32083.0,32083.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.01/76.20 33358[42:Res:53.1,33357.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.01/76.20 33363[43:Spt:33358.0] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.20 33365[43:Res:33363.0,61.1] always3(s14) || -> . % 76.01/76.20 33366[43:SSi:33365.0,703.0,32082.0] || -> . % 76.01/76.20 33367[43:Spt:33366.0,33358.0,33363.0] || m_main_v_state(s14,c_busy)* -> . % 76.01/76.20 33368[43:Spt:33366.0,33358.1] || -> m_main_v_state(s15,c_busy)*. % 76.01/76.20 33372[43:Res:33368.0,61.1] always3(s15) || -> . % 76.01/76.20 33373[43:SSi:33372.0,704.0] || -> . % 76.01/76.20 33374[41:Spt:33373.0,32077.2,32081.0] || xuntil6(s13)*+ -> . % 76.01/76.20 33375[41:Spt:33373.0,32077.0,32077.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.01/76.20 33376[41:Res:53.1,33375.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.01/76.20 33378[42:Spt:33376.0] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.20 33380[42:Res:33378.0,61.1] always3(s13) || -> . % 76.01/76.20 33381[42:SSi:33380.0,702.0,32076.0] || -> . % 76.01/76.20 33382[42:Spt:33381.0,33376.0,33378.0] || m_main_v_state(s13,c_busy)* -> . % 76.01/76.20 33383[42:Spt:33381.0,33376.1] || -> m_main_v_state(s14,c_busy)*. % 76.01/76.20 33387[42:Res:33383.0,61.1] always3(s14) || -> . % 76.01/76.20 33388[42:SSi:33387.0,703.0] || -> . % 76.01/76.20 33389[40:Spt:33388.0,32074.2,32075.0] || xuntil6(s12)*+ -> . % 76.01/76.20 33390[40:Spt:33388.0,32074.0,32074.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.01/76.20 33391[40:Res:53.1,33390.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.01/76.20 33393[41:Spt:33391.0] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.20 33395[41:Res:33393.0,61.1] always3(s12) || -> . % 76.01/76.20 33396[41:SSi:33395.0,701.0,32073.0] || -> . % 76.01/76.20 33397[41:Spt:33396.0,33391.0,33393.0] || m_main_v_state(s12,c_busy)* -> . % 76.01/76.20 33398[41:Spt:33396.0,33391.1] || -> m_main_v_state(s13,c_busy)*. % 76.01/76.20 33402[41:Res:33398.0,61.1] always3(s13) || -> . % 76.01/76.20 33403[41:SSi:33402.0,702.0] || -> . % 76.01/76.20 33404[39:Spt:33403.0,32068.2,32072.0] || xuntil6(s11)*+ -> . % 76.01/76.20 33405[39:Spt:33403.0,32068.0,32068.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.01/76.20 33406[39:Res:53.1,33405.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.01/76.20 33411[40:Spt:33406.0] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.20 33413[40:Res:33411.0,61.1] always3(s11) || -> . % 76.01/76.20 33414[40:SSi:33413.0,700.0,32067.0] || -> . % 76.01/76.20 33415[40:Spt:33414.0,33406.0,33411.0] || m_main_v_state(s11,c_busy)* -> . % 76.01/76.20 33416[40:Spt:33414.0,33406.1] || -> m_main_v_state(s12,c_busy)*. % 76.01/76.20 33420[40:Res:33416.0,61.1] always3(s12) || -> . % 76.01/76.20 33421[40:SSi:33420.0,701.0] || -> . % 76.01/76.20 33422[38:Spt:33421.0,32065.2,32066.0] || xuntil6(s10)*+ -> . % 76.01/76.20 33423[38:Spt:33421.0,32065.0,32065.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.01/76.20 33424[38:Res:53.1,33423.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.01/76.20 33426[39:Spt:33424.0] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.20 33428[39:Res:33426.0,61.1] always3(s10) || -> . % 76.01/76.20 33429[39:SSi:33428.0,699.0,32064.0] || -> . % 76.01/76.20 33430[39:Spt:33429.0,33424.0,33426.0] || m_main_v_state(s10,c_busy)* -> . % 76.01/76.20 33431[39:Spt:33429.0,33424.1] || -> m_main_v_state(s11,c_busy)*. % 76.01/76.20 33435[39:Res:33431.0,61.1] always3(s11) || -> . % 76.01/76.20 33436[39:SSi:33435.0,700.0] || -> . % 76.01/76.20 33437[37:Spt:33436.0,32059.2,32063.0] || xuntil6(s9)*+ -> . % 76.01/76.20 33438[37:Spt:33436.0,32059.0,32059.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.01/76.20 33439[37:Res:53.1,33438.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.01/76.20 33441[38:Spt:33439.0] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.20 33443[38:Res:33441.0,61.1] always3(s9) || -> . % 76.01/76.20 33444[38:SSi:33443.0,698.0,32058.0] || -> . % 76.01/76.20 33445[38:Spt:33444.0,33439.0,33441.0] || m_main_v_state(s9,c_busy)* -> . % 76.01/76.20 33446[38:Spt:33444.0,33439.1] || -> m_main_v_state(s10,c_busy)*. % 76.01/76.20 33450[38:Res:33446.0,61.1] always3(s10) || -> . % 76.01/76.20 33451[38:SSi:33450.0,699.0] || -> . % 76.01/76.20 33452[36:Spt:33451.0,32056.2,32057.0] || xuntil6(s8)*+ -> . % 76.01/76.20 33453[36:Spt:33451.0,32056.0,32056.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.01/76.20 33454[36:Res:53.1,33453.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.01/76.20 33459[37:Spt:33454.0] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.20 33461[37:Res:33459.0,61.1] always3(s8) || -> . % 76.01/76.20 33462[37:SSi:33461.0,697.0,32055.0] || -> . % 76.01/76.20 33463[37:Spt:33462.0,33454.0,33459.0] || m_main_v_state(s8,c_busy)* -> . % 76.01/76.20 33464[37:Spt:33462.0,33454.1] || -> m_main_v_state(s9,c_busy)*. % 76.01/76.20 33468[37:Res:33464.0,61.1] always3(s9) || -> . % 76.01/76.20 33469[37:SSi:33468.0,698.0] || -> . % 76.01/76.20 33470[35:Spt:33469.0,32050.2,32054.0] || xuntil6(s7)*+ -> . % 76.01/76.20 33471[35:Spt:33469.0,32050.0,32050.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.01/76.20 33472[35:Res:53.1,33471.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.01/76.20 33474[36:Spt:33472.0] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.20 33476[36:Res:33474.0,61.1] always3(s7) || -> . % 76.01/76.20 33477[36:SSi:33476.0,696.0,32049.0] || -> . % 76.01/76.20 33478[36:Spt:33477.0,33472.0,33474.0] || m_main_v_state(s7,c_busy)* -> . % 76.01/76.20 33479[36:Spt:33477.0,33472.1] || -> m_main_v_state(s8,c_busy)*. % 76.01/76.20 33483[36:Res:33479.0,61.1] always3(s8) || -> . % 76.01/76.20 33484[36:SSi:33483.0,697.0] || -> . % 76.01/76.20 33485[34:Spt:33484.0,32047.2,32048.0] || xuntil6(s6)*+ -> . % 76.01/76.20 33486[34:Spt:33484.0,32047.0,32047.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.01/76.20 33487[34:Res:53.1,33486.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.01/76.20 33489[35:Spt:33487.0] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.20 33491[35:Res:33489.0,61.1] always3(s6) || -> . % 76.01/76.20 33492[35:SSi:33491.0,695.0,32046.0] || -> . % 76.01/76.20 33493[35:Spt:33492.0,33487.0,33489.0] || m_main_v_state(s6,c_busy)* -> . % 76.01/76.20 33494[35:Spt:33492.0,33487.1] || -> m_main_v_state(s7,c_busy)*. % 76.01/76.20 33498[35:Res:33494.0,61.1] always3(s7) || -> . % 76.01/76.20 33499[35:SSi:33498.0,696.0] || -> . % 76.01/76.20 33500[33:Spt:33499.0,32041.2,32045.0] || xuntil6(s5)*+ -> . % 76.01/76.20 33501[33:Spt:33499.0,32041.0,32041.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.01/76.20 33502[33:Res:53.1,33501.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.01/76.20 33507[34:Spt:33502.0] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.20 33509[34:Res:33507.0,61.1] always3(s5) || -> . % 76.01/76.20 33510[34:SSi:33509.0,694.0,32040.0] || -> . % 76.01/76.20 33511[34:Spt:33510.0,33502.0,33507.0] || m_main_v_state(s5,c_busy)* -> . % 76.01/76.20 33512[34:Spt:33510.0,33502.1] || -> m_main_v_state(s6,c_busy)*. % 76.01/76.20 33516[34:Res:33512.0,61.1] always3(s6) || -> . % 76.01/76.20 33517[34:SSi:33516.0,695.0] || -> . % 76.01/76.20 33518[32:Spt:33517.0,32038.2,32039.0] || xuntil6(s4)*+ -> . % 76.01/76.20 33519[32:Spt:33517.0,32038.0,32038.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.01/76.20 33520[32:Res:53.1,33519.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.01/76.20 33522[33:Spt:33520.0] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.20 33524[33:Res:33522.0,61.1] always3(s4) || -> . % 76.01/76.20 33525[33:SSi:33524.0,693.0,32037.0] || -> . % 76.01/76.20 33526[33:Spt:33525.0,33520.0,33522.0] || m_main_v_state(s4,c_busy)* -> . % 76.01/76.20 33527[33:Spt:33525.0,33520.1] || -> m_main_v_state(s5,c_busy)*. % 76.01/76.20 33531[33:Res:33527.0,61.1] always3(s5) || -> . % 76.01/76.20 33532[33:SSi:33531.0,694.0] || -> . % 76.01/76.20 33533[31:Spt:33532.0,32035.2,32036.0] || xuntil6(s3)*+ -> . % 76.01/76.20 33534[31:Spt:33532.0,32035.0,32035.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.01/76.20 33535[31:Res:53.1,33534.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.01/76.20 33537[32:Spt:33535.0] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.20 33539[32:Res:33537.0,61.1] always3(s3) || -> . % 76.01/76.20 33540[32:SSi:33539.0,692.0,32034.0] || -> . % 76.01/76.20 33541[32:Spt:33540.0,33535.0,33537.0] || m_main_v_state(s3,c_busy)* -> . % 76.01/76.20 33542[32:Spt:33540.0,33535.1] || -> m_main_v_state(s4,c_busy)*. % 76.01/76.20 33546[32:Res:33542.0,61.1] always3(s4) || -> . % 76.01/76.20 33547[32:SSi:33546.0,693.0] || -> . % 76.01/76.20 33548[30:Spt:33547.0,32032.2,32033.0] || xuntil6(s2)*+ -> . % 76.01/76.20 33549[30:Spt:33547.0,32032.0,32032.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.01/76.20 33550[30:Res:53.1,33549.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.01/76.20 33555[31:Spt:33550.0] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.20 33557[31:Res:33555.0,61.1] always3(s2) || -> . % 76.01/76.20 33558[31:SSi:33557.0,691.0,32031.0] || -> . % 76.01/76.20 33559[31:Spt:33558.0,33550.0,33555.0] || m_main_v_state(s2,c_busy)* -> . % 76.01/76.20 33560[31:Spt:33558.0,33550.1] || -> m_main_v_state(s3,c_busy)*. % 76.01/76.20 33564[31:Res:33560.0,61.1] always3(s3) || -> . % 76.01/76.20 33565[31:SSi:33564.0,692.0] || -> . % 76.01/76.20 33566[29:Spt:33565.0,32026.2,32030.0] || xuntil6(s1)*+ -> . % 76.01/76.20 33567[29:Spt:33565.0,32026.0,32026.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.01/76.20 33568[29:Res:53.1,33567.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.01/76.20 33570[30:Spt:33568.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.20 33572[30:Res:33570.0,61.1] always3(s1) || -> . % 76.01/76.20 33573[30:SSi:33572.0,690.0,32025.0] || -> . % 76.01/76.20 33574[30:Spt:33573.0,33568.0,33570.0] || m_main_v_state(s1,c_busy)* -> . % 76.01/76.20 33575[30:Spt:33573.0,33568.1] || -> m_main_v_state(s2,c_busy)*. % 76.01/76.20 33580[30:Res:33575.0,61.1] always3(s2) || -> . % 76.01/76.20 33581[30:SSi:33580.0,691.0] || -> . % 76.01/76.20 33582[28:Spt:33581.0,74.0,32024.0] || xuntil6(s0)*+ -> . % 76.01/76.20 33583[28:Spt:33581.0,74.1] || -> node4(s0)*. % 76.01/76.20 33584[28:MRR:758.1,33582.0] || -> m_main_v_state(s1,c_busy)*. % 76.01/76.20 33586[28:Res:33584.0,61.1] always3(s1) || -> . % 76.01/76.20 33587[28:SSi:33586.0,690.0] || -> . % 76.01/76.20 33588[27:Spt:33587.0,32014.0,32018.0] || trans(s49,s24)*+ -> . % 76.01/76.20 33589[27:Spt:33587.0,32014.1,32014.2,32014.3,32014.4,32014.5,32014.6,32014.7,32014.8,32014.9,32014.10,32014.11,32014.12,32014.13,32014.14,32014.15,32014.16,32014.17,32014.18,32014.19,32014.20,32014.21,32014.22,32014.23,32014.24] || -> trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.01/76.20 33591[27:MRR:32015.0,33588.0] || -> trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.01/76.20 33592[27:MRR:32017.1,33588.0] xuntil6(s49) || -> trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.01/76.20 33593[28:Spt:33589.0] || -> trans(s49,s23)*. % 76.01/76.20 33594[28:Res:33593.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s23)*. % 76.01/76.20 33596[28:Res:33593.0,60.0] || -> node2(s49,s23)*. % 76.01/76.20 33597[28:SSi:33594.1,50.0,738.0] xuntil6(s49) || -> until2p7(s23)*. % 76.01/76.20 33598[28:Res:33596.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)*. % 76.01/76.20 33599[29:Spt:74.0] || -> xuntil6(s0)*. % 76.01/76.20 33600[29:MRR:176.0,33599.0] || -> until5(s1)*. % 76.01/76.20 33601[29:MRR:32463.0,33600.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.01/76.20 33608[30:Spt:33601.2] || -> xuntil6(s1)*. % 76.01/76.20 33609[30:MRR:175.0,33608.0] || -> until5(s2)*. % 76.01/76.20 33610[30:MRR:32459.0,33609.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.01/76.20 33611[31:Spt:33610.2] || -> xuntil6(s2)*. % 76.01/76.20 33612[31:MRR:174.0,33611.0] || -> until5(s3)*. % 76.01/76.20 33613[31:MRR:32455.0,33612.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.01/76.20 33617[32:Spt:33613.2] || -> xuntil6(s3)*. % 76.01/76.20 33618[32:MRR:173.0,33617.0] || -> until5(s4)*. % 76.01/76.20 33619[32:MRR:32454.0,33618.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.01/76.20 33620[33:Spt:33619.2] || -> xuntil6(s4)*. % 76.01/76.20 33621[33:MRR:172.0,33620.0] || -> until5(s5)*. % 76.01/76.20 33622[33:MRR:32447.0,33621.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.01/76.20 33626[34:Spt:33622.2] || -> xuntil6(s5)*. % 76.01/76.20 33627[34:MRR:171.0,33626.0] || -> until5(s6)*. % 76.01/76.20 33628[34:MRR:32443.0,33627.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.01/76.20 33629[35:Spt:33628.2] || -> xuntil6(s6)*. % 76.01/76.20 33630[35:MRR:170.0,33629.0] || -> until5(s7)*. % 76.01/76.20 33631[35:MRR:32439.0,33630.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.01/76.20 33635[36:Spt:33631.2] || -> xuntil6(s7)*. % 76.01/76.20 33636[36:MRR:169.0,33635.0] || -> until5(s8)*. % 76.01/76.20 33637[36:MRR:32435.0,33636.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.01/76.20 33638[37:Spt:33637.2] || -> xuntil6(s8)*. % 76.01/76.20 33639[37:MRR:168.0,33638.0] || -> until5(s9)*. % 76.01/76.20 33640[37:MRR:32434.0,33639.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.01/76.20 33644[38:Spt:33640.2] || -> xuntil6(s9)*. % 76.01/76.20 33645[38:MRR:167.0,33644.0] || -> until5(s10)*. % 76.01/76.20 33646[38:MRR:32427.0,33645.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.01/76.20 33647[39:Spt:33646.2] || -> xuntil6(s10)*. % 76.01/76.20 33648[39:MRR:166.0,33647.0] || -> until5(s11)*. % 76.01/76.20 33649[39:MRR:32423.0,33648.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.01/76.20 33653[40:Spt:33649.2] || -> xuntil6(s11)*. % 76.01/76.20 33654[40:MRR:165.0,33653.0] || -> until5(s12)*. % 76.01/76.20 33655[40:MRR:32419.0,33654.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.01/76.20 33656[41:Spt:33655.2] || -> xuntil6(s12)*. % 76.01/76.20 33657[41:MRR:164.0,33656.0] || -> until5(s13)*. % 76.01/76.20 33658[41:MRR:32415.0,33657.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.01/76.20 33662[42:Spt:33658.2] || -> xuntil6(s13)*. % 76.01/76.20 33663[42:MRR:163.0,33662.0] || -> until5(s14)*. % 76.01/76.20 33664[42:MRR:32414.0,33663.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.01/76.20 33665[43:Spt:33664.2] || -> xuntil6(s14)*. % 76.01/76.20 33666[43:MRR:162.0,33665.0] || -> until5(s15)*. % 76.01/76.20 33667[43:MRR:32407.0,33666.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.01/76.20 33671[44:Spt:33667.2] || -> xuntil6(s15)*. % 76.01/76.20 33672[44:MRR:161.0,33671.0] || -> until5(s16)*. % 76.01/76.20 33673[44:MRR:32403.0,33672.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.01/76.20 33674[45:Spt:33673.2] || -> xuntil6(s16)*. % 76.01/76.20 33675[45:MRR:160.0,33674.0] || -> until5(s17)*. % 76.01/76.20 33676[45:MRR:32399.0,33675.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.01/76.20 33680[46:Spt:33676.2] || -> xuntil6(s17)*. % 76.01/76.20 33681[46:MRR:159.0,33680.0] || -> until5(s18)*. % 76.01/76.20 33682[46:MRR:32395.0,33681.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.01/76.20 33683[47:Spt:33682.2] || -> xuntil6(s18)*. % 76.01/76.20 33684[47:MRR:158.0,33683.0] || -> until5(s19)*. % 76.01/76.20 33685[47:MRR:32394.0,33684.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.01/76.20 33689[48:Spt:33685.2] || -> xuntil6(s19)*. % 76.01/76.20 33690[48:MRR:157.0,33689.0] || -> until5(s20)*. % 76.01/76.20 33691[48:MRR:32387.0,33690.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.01/76.20 33692[49:Spt:33691.2] || -> xuntil6(s20)*. % 76.01/76.20 33693[49:MRR:156.0,33692.0] || -> until5(s21)*. % 76.01/76.20 33694[49:MRR:32383.0,33693.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.01/76.20 33698[50:Spt:33694.2] || -> xuntil6(s21)*. % 76.01/76.20 33699[50:MRR:155.0,33698.0] || -> until5(s22)*. % 76.01/76.20 33700[50:MRR:32379.0,33699.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.01/76.20 33701[51:Spt:33700.2] || -> xuntil6(s22)*. % 76.01/76.20 33702[51:MRR:154.0,33701.0] || -> until5(s23)*. % 76.01/76.20 33703[51:MRR:32375.0,33702.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.01/76.20 33707[52:Spt:33703.2] || -> xuntil6(s23)*. % 76.01/76.20 33708[52:MRR:153.0,33707.0] || -> until5(s24)*. % 76.01/76.20 33709[52:MRR:32374.0,33708.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.01/76.20 33710[53:Spt:33709.2] || -> xuntil6(s24)*. % 76.01/76.20 33711[53:MRR:152.0,33710.0] || -> until5(s25)*. % 76.01/76.20 33712[53:MRR:32367.0,33711.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.01/76.20 33716[54:Spt:33712.2] || -> xuntil6(s25)*. % 76.01/76.20 33717[54:MRR:151.0,33716.0] || -> until5(s26)*. % 76.01/76.20 33718[54:MRR:32366.0,33717.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.01/76.20 33719[55:Spt:33718.2] || -> xuntil6(s26)*. % 76.01/76.20 33720[55:MRR:150.0,33719.0] || -> until5(s27)*. % 76.01/76.20 33721[55:MRR:32365.0,33720.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.01/76.20 33725[56:Spt:33721.2] || -> xuntil6(s27)*. % 76.01/76.20 33726[56:MRR:149.0,33725.0] || -> until5(s28)*. % 76.01/76.20 33727[56:MRR:32361.0,33726.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.01/76.20 33728[57:Spt:33727.1] || -> m_main_v_state(s29,c_busy)*. % 76.01/76.20 33730[57:Res:33728.0,61.1] always3(s29) || -> . % 76.01/76.20 33731[57:SSi:33730.0,718.0] || -> . % 76.01/76.20 33732[57:Spt:33731.0,33727.1,33728.0] || m_main_v_state(s29,c_busy)*+ -> . % 76.01/76.20 33733[57:Spt:33731.0,33727.0,33727.2] || m_main_v_state(s28,c_ready)*+ -> xuntil6(s28). % 76.01/76.20 33735[57:MRR:834.2,33732.0] node4(s28) || m_main_v_state(s28,c_ready)* -> . % 76.01/76.20 33736[57:Res:53.1,33733.0] || -> m_main_v_state(s28,c_busy)* xuntil6(s28). % 76.01/76.20 33741[58:Spt:33736.1] || -> xuntil6(s28)*. % 76.01/76.20 33742[58:MRR:148.0,33741.0] || -> until5(s29)*. % 76.01/76.20 33743[58:MRR:30928.0,33742.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.01/76.20 33745[59:Spt:33743.2] || -> xuntil6(s29)*. % 76.01/76.20 33746[59:MRR:147.0,33745.0] || -> until5(s30)*. % 76.01/76.20 33747[59:MRR:32470.0,33746.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.01/76.20 33748[60:Spt:33747.1] || -> m_main_v_state(s31,c_busy)*. % 76.01/76.20 33750[60:Res:33748.0,61.1] always3(s31) || -> . % 76.01/76.20 33751[60:SSi:33750.0,720.0] || -> . % 76.01/76.20 33752[60:Spt:33751.0,33747.1,33748.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.01/76.20 33753[60:Spt:33751.0,33747.0,33747.2] || m_main_v_state(s30,c_ready)*+ -> xuntil6(s30). % 76.01/76.20 33755[60:MRR:828.2,33752.0] node4(s30) || m_main_v_state(s30,c_ready)* -> . % 76.01/76.20 33756[60:Res:53.1,33753.0] || -> m_main_v_state(s30,c_busy)* xuntil6(s30). % 76.01/76.20 33758[61:Spt:33756.1] || -> xuntil6(s30)*. % 76.01/76.20 33759[61:MRR:146.0,33758.0] || -> until5(s31)*. % 76.01/76.20 33760[61:MRR:30932.0,33759.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.01/76.20 33765[62:Spt:33760.2] || -> xuntil6(s31)*. % 76.01/76.20 33766[62:MRR:145.0,33765.0] || -> until5(s32)*. % 76.01/76.20 33767[62:MRR:32474.0,33766.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.01/76.20 33768[63:Spt:33767.1] || -> m_main_v_state(s33,c_busy)*. % 76.01/76.20 33770[63:Res:33768.0,61.1] always3(s33) || -> . % 76.01/76.20 33771[63:SSi:33770.0,722.0] || -> . % 76.01/76.20 33772[63:Spt:33771.0,33767.1,33768.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.01/76.20 33773[63:Spt:33771.0,33767.0,33767.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 76.01/76.20 33775[63:MRR:822.2,33772.0] node4(s32) || m_main_v_state(s32,c_ready)* -> . % 76.01/76.20 33776[63:Res:53.1,33773.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 76.01/76.20 33778[64:Spt:33776.1] || -> xuntil6(s32)*. % 76.01/76.20 33779[64:MRR:144.0,33778.0] || -> until5(s33)*. % 76.01/76.20 33780[64:MRR:30936.0,33779.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.01/76.20 33788[65:Spt:33780.2] || -> xuntil6(s33)*. % 76.01/76.20 33789[65:MRR:143.0,33788.0] || -> until5(s34)*. % 76.01/76.20 33790[65:MRR:32478.0,33789.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.01/76.20 33791[66:Spt:33790.1] || -> m_main_v_state(s35,c_busy)*. % 76.01/76.20 33793[66:Res:33791.0,61.1] always3(s35) || -> . % 76.01/76.20 33794[66:SSi:33793.0,724.0] || -> . % 76.01/76.20 33795[66:Spt:33794.0,33790.1,33791.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.01/76.20 33796[66:Spt:33794.0,33790.0,33790.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 76.01/76.20 33798[66:MRR:816.2,33795.0] node4(s34) || m_main_v_state(s34,c_ready)* -> . % 76.01/76.20 33799[66:Res:53.1,33796.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 76.01/76.20 33804[67:Spt:33799.1] || -> xuntil6(s34)*. % 76.01/76.20 33805[67:MRR:142.0,33804.0] || -> until5(s35)*. % 76.01/76.20 33806[67:MRR:30940.0,33805.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.01/76.20 33808[68:Spt:33806.2] || -> xuntil6(s35)*. % 76.01/76.20 33809[68:MRR:141.0,33808.0] || -> until5(s36)*. % 76.01/76.20 33810[68:MRR:32485.0,33809.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.01/76.20 33811[69:Spt:33810.1] || -> m_main_v_state(s37,c_busy)*. % 76.01/76.20 33813[69:Res:33811.0,61.1] always3(s37) || -> . % 76.01/76.20 33814[69:SSi:33813.0,726.0] || -> . % 76.01/76.20 33815[69:Spt:33814.0,33810.1,33811.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.01/76.20 33816[69:Spt:33814.0,33810.0,33810.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 76.01/76.20 33818[69:MRR:810.2,33815.0] node4(s36) || m_main_v_state(s36,c_ready)* -> . % 76.01/76.20 33819[69:Res:53.1,33816.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 76.01/76.20 33821[70:Spt:33819.1] || -> xuntil6(s36)*. % 76.01/76.20 33822[70:MRR:140.0,33821.0] || -> until5(s37)*. % 76.01/76.20 33823[70:MRR:30947.0,33822.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.01/76.20 33828[71:Spt:33823.2] || -> xuntil6(s37)*. % 76.01/76.20 33829[71:MRR:139.0,33828.0] || -> until5(s38)*. % 76.01/76.20 33830[71:MRR:32486.0,33829.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.01/76.20 33831[72:Spt:33830.1] || -> m_main_v_state(s39,c_busy)*. % 76.01/76.20 33833[72:Res:33831.0,61.1] always3(s39) || -> . % 76.01/76.20 33834[72:SSi:33833.0,728.0] || -> . % 76.01/76.20 33835[72:Spt:33834.0,33830.1,33831.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.01/76.20 33836[72:Spt:33834.0,33830.0,33830.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 76.01/76.20 33838[72:MRR:804.2,33835.0] node4(s38) || m_main_v_state(s38,c_ready)* -> . % 76.01/76.20 33839[72:Res:53.1,33836.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 76.01/76.20 33841[73:Spt:33839.1] || -> xuntil6(s38)*. % 76.01/76.20 33842[73:MRR:138.0,33841.0] || -> until5(s39)*. % 76.01/76.20 33843[73:MRR:30948.0,33842.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.03/76.20 33851[74:Spt:33843.2] || -> xuntil6(s39)*. % 76.03/76.20 33852[74:MRR:137.0,33851.0] || -> until5(s40)*. % 76.03/76.20 33853[74:MRR:32490.0,33852.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.03/76.20 33854[75:Spt:33853.1] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.20 33856[75:Res:33854.0,61.1] always3(s41) || -> . % 76.03/76.20 33857[75:SSi:33856.0,730.0] || -> . % 76.03/76.20 33858[75:Spt:33857.0,33853.1,33854.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.03/76.20 33859[75:Spt:33857.0,33853.0,33853.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 76.03/76.20 33861[75:MRR:798.2,33858.0] node4(s40) || m_main_v_state(s40,c_ready)* -> . % 76.03/76.20 33862[75:Res:53.1,33859.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 76.03/76.20 33867[76:Spt:33862.1] || -> xuntil6(s40)*. % 76.03/76.20 33868[76:MRR:136.0,33867.0] || -> until5(s41)*. % 76.03/76.20 33869[76:MRR:30952.0,33868.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.03/76.20 33871[77:Spt:33869.2] || -> xuntil6(s41)*. % 76.03/76.20 33872[77:MRR:135.0,33871.0] || -> until5(s42)*. % 76.03/76.20 33873[77:MRR:32494.0,33872.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.03/76.20 33874[78:Spt:33873.1] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.20 33876[78:Res:33874.0,61.1] always3(s43) || -> . % 76.03/76.20 33877[78:SSi:33876.0,732.0] || -> . % 76.03/76.20 33878[78:Spt:33877.0,33873.1,33874.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.03/76.20 33879[78:Spt:33877.0,33873.0,33873.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 76.03/76.20 33881[78:MRR:792.2,33878.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 76.03/76.20 33882[78:Res:53.1,33879.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 76.03/76.20 33884[79:Spt:33882.1] || -> xuntil6(s42)*. % 76.03/76.20 33885[79:MRR:134.0,33884.0] || -> until5(s43)*. % 76.03/76.20 33886[79:MRR:30956.0,33885.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.03/76.20 33891[80:Spt:33886.2] || -> xuntil6(s43)*. % 76.03/76.20 33892[80:MRR:133.0,33891.0] || -> until5(s44)*. % 76.03/76.20 33893[80:MRR:32498.0,33892.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.03/76.20 33894[81:Spt:33893.1] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.20 33896[81:Res:33894.0,61.1] always3(s45) || -> . % 76.03/76.20 33897[81:SSi:33896.0,734.0] || -> . % 76.03/76.20 33898[81:Spt:33897.0,33893.1,33894.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.03/76.20 33899[81:Spt:33897.0,33893.0,33893.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 76.03/76.20 33901[81:MRR:786.2,33898.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 76.03/76.20 33902[81:Res:53.1,33899.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 76.03/76.20 33904[82:Spt:33902.1] || -> xuntil6(s44)*. % 76.03/76.20 33905[82:MRR:132.0,33904.0] || -> until5(s45)*. % 76.03/76.20 33906[82:MRR:30960.0,33905.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.03/76.20 33914[83:Spt:33906.2] || -> xuntil6(s45)*. % 76.03/76.20 33915[83:MRR:131.0,33914.0] || -> until5(s46)*. % 76.03/76.20 33916[83:MRR:32505.0,33915.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.03/76.20 33917[84:Spt:33916.1] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.20 33919[84:Res:33917.0,61.1] always3(s47) || -> . % 76.03/76.20 33920[84:SSi:33919.0,736.0] || -> . % 76.03/76.20 33921[84:Spt:33920.0,33916.1,33917.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.03/76.20 33922[84:Spt:33920.0,33916.0,33916.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 76.03/76.20 33924[84:MRR:780.2,33921.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 76.03/76.20 33925[84:Res:53.1,33922.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 76.03/76.20 33930[85:Spt:33925.1] || -> xuntil6(s46)*. % 76.03/76.20 33931[85:MRR:130.0,33930.0] || -> until5(s47)*. % 76.03/76.20 33932[85:MRR:30964.0,33931.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.03/76.20 33934[86:Spt:33932.2] || -> xuntil6(s47)*. % 76.03/76.20 33935[86:MRR:129.0,33934.0] || -> until5(s48)*. % 76.03/76.20 33936[86:MRR:32506.0,33935.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.03/76.20 33937[87:Spt:33936.1] || -> m_main_v_state(s49,c_busy)*. % 76.03/76.20 33939[87:Res:33937.0,61.1] always3(s49) || -> . % 76.03/76.20 33940[87:SSi:33939.0,50.0,738.0] || -> . % 76.03/76.20 33941[87:Spt:33940.0,33936.1,33937.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.03/76.20 33942[87:Spt:33940.0,33936.0,33936.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 76.03/76.20 33944[87:MRR:774.2,33941.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.03/76.20 33945[87:Res:53.1,33942.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 76.03/76.20 33947[88:Spt:33945.1] || -> xuntil6(s48)*. % 76.03/76.20 33948[88:MRR:128.0,33947.0] || -> until5(s49)*. % 76.03/76.20 33953[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.03/76.20 33954[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.03/76.20 33955[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.03/76.20 33959[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.03/76.20 33963[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.03/76.20 33970[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.03/76.20 33971[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.03/76.20 33975[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.03/76.20 33979[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.03/76.20 33983[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.03/76.20 33990[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.03/76.20 33991[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.03/76.20 33995[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.03/76.20 33999[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.03/76.20 34003[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.03/76.20 34010[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.03/76.20 34011[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.03/76.20 34015[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.03/76.20 34019[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.03/76.20 34023[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.03/76.20 34030[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.03/76.20 34031[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.03/76.20 34035[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.03/76.20 34039[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.03/76.20 34043[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.03/76.20 34050[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.03/76.20 34051[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.03/76.20 34055[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.03/76.20 34059[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.03/76.20 34063[0:SoR:819.0,66.2] until5(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.03/76.20 34070[0:SoR:813.0,66.2] until5(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.03/76.20 34071[0:SoR:807.0,66.2] until5(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.03/76.20 34075[0:SoR:801.0,66.2] until5(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.03/76.20 34079[0:SoR:795.0,66.2] until5(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.03/76.20 34083[0:SoR:789.0,66.2] until5(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.03/76.20 34090[0:SoR:783.0,66.2] until5(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.03/76.20 34091[0:SoR:777.0,66.2] until5(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.03/76.20 34093[28:SoR:33598.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)*. % 76.03/76.20 34095[28:SoR:34093.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)* xuntil6(s49). % 76.03/76.20 34096[88:SSi:34095.0,50.0,738.0,33948.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s23,c_busy)* xuntil6(s49). % 76.03/76.20 34097[89:Spt:34096.1] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.20 34099[89:Res:34097.0,61.1] always3(s23) || -> . % 76.03/76.20 34100[89:SSi:34099.0,712.0,33702.0,33707.0] || -> . % 76.03/76.20 34101[89:Spt:34100.0,34096.1,34097.0] || m_main_v_state(s23,c_busy)*+ -> . % 76.03/76.20 34102[89:Spt:34100.0,34096.0,34096.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.03/76.20 34106[89:MRR:34093.2,34101.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.03/76.20 34107[89:Res:53.1,34102.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.03/76.20 34109[89:MRR:34107.0,33941.0] || -> xuntil6(s49)*. % 76.03/76.20 34110[89:MRR:33597.0,34109.0] || -> until2p7(s23)*. % 76.03/76.20 34111[89:MRR:219.0,34110.0] || -> until2p7(s24)* node4(s23). % 76.03/76.20 34112[90:Spt:34111.0] || -> until2p7(s24)*. % 76.03/76.20 34113[90:MRR:220.0,34112.0] || -> until2p7(s25)* node4(s24). % 76.03/76.20 34114[91:Spt:34113.0] || -> until2p7(s25)*. % 76.03/76.20 34115[91:MRR:221.0,34114.0] || -> until2p7(s26)* node4(s25). % 76.03/76.20 34116[92:Spt:34115.0] || -> until2p7(s26)*. % 76.03/76.20 34117[92:MRR:222.0,34116.0] || -> until2p7(s27)* node4(s26). % 76.03/76.20 34118[93:Spt:34117.0] || -> until2p7(s27)*. % 76.03/76.20 34119[93:MRR:223.0,34118.0] || -> until2p7(s28)* node4(s27). % 76.03/76.20 34120[94:Spt:34119.0] || -> until2p7(s28)*. % 76.03/76.20 34121[94:MRR:224.0,34120.0] || -> until2p7(s29)* node4(s28). % 76.03/76.20 34122[95:Spt:34121.0] || -> until2p7(s29)*. % 76.03/76.20 34123[95:MRR:225.0,34122.0] || -> until2p7(s30)* node4(s29). % 76.03/76.20 34124[96:Spt:34123.0] || -> until2p7(s30)*. % 76.03/76.20 34125[96:MRR:226.0,34124.0] || -> until2p7(s31)* node4(s30). % 76.03/76.20 34126[97:Spt:34125.0] || -> until2p7(s31)*. % 76.03/76.20 34127[97:MRR:227.0,34126.0] || -> until2p7(s32)* node4(s31). % 76.03/76.20 34128[98:Spt:34127.0] || -> until2p7(s32)*. % 76.03/76.20 34129[98:MRR:228.0,34128.0] || -> until2p7(s33)* node4(s32). % 76.03/76.20 34130[99:Spt:34129.0] || -> until2p7(s33)*. % 76.03/76.20 34131[99:MRR:229.0,34130.0] || -> until2p7(s34)* node4(s33). % 76.03/76.20 34132[100:Spt:34131.0] || -> until2p7(s34)*. % 76.03/76.20 34133[100:MRR:230.0,34132.0] || -> until2p7(s35)* node4(s34). % 76.03/76.20 34134[101:Spt:34133.0] || -> until2p7(s35)*. % 76.03/76.20 34135[101:MRR:231.0,34134.0] || -> until2p7(s36)* node4(s35). % 76.03/76.20 34136[102:Spt:34135.0] || -> until2p7(s36)*. % 76.03/76.20 34137[102:MRR:232.0,34136.0] || -> until2p7(s37)* node4(s36). % 76.03/76.20 34138[103:Spt:34137.0] || -> until2p7(s37)*. % 76.03/76.20 34139[103:MRR:235.0,34138.0] || -> until2p7(s38)* node4(s37). % 76.03/76.20 34140[104:Spt:34139.0] || -> until2p7(s38)*. % 76.03/76.20 34141[104:MRR:236.0,34140.0] || -> until2p7(s39)* node4(s38). % 76.03/76.20 34142[105:Spt:34141.0] || -> until2p7(s39)*. % 76.03/76.20 34143[105:MRR:237.0,34142.0] || -> until2p7(s40)* node4(s39). % 76.03/76.20 34144[106:Spt:34143.0] || -> until2p7(s40)*. % 76.03/76.20 34145[106:MRR:238.0,34144.0] || -> until2p7(s41)* node4(s40). % 76.03/76.20 34146[107:Spt:34145.0] || -> until2p7(s41)*. % 76.03/76.20 34147[107:MRR:239.0,34146.0] || -> until2p7(s42)* node4(s41). % 76.03/76.20 34148[108:Spt:34147.0] || -> until2p7(s42)*. % 76.03/76.20 34149[108:MRR:240.0,34148.0] || -> until2p7(s43)* node4(s42). % 76.03/76.20 34150[109:Spt:34149.0] || -> until2p7(s43)*. % 76.03/76.20 34151[109:MRR:241.0,34150.0] || -> until2p7(s44)* node4(s43). % 76.03/76.20 34152[110:Spt:34151.0] || -> until2p7(s44)*. % 76.03/76.20 34153[110:MRR:539.0,34152.0] || -> until2p7(s45)* node4(s44). % 76.03/76.20 34154[111:Spt:34153.0] || -> until2p7(s45)*. % 76.03/76.20 34155[111:MRR:544.0,34154.0] || -> until2p7(s46)* node4(s45). % 76.03/76.20 34156[112:Spt:34155.0] || -> until2p7(s46)*. % 76.03/76.20 34157[112:MRR:549.0,34156.0] || -> until2p7(s47)* node4(s46). % 76.03/76.20 34158[113:Spt:34157.0] || -> until2p7(s47)*. % 76.03/76.20 34159[113:MRR:554.0,34158.0] || -> until2p7(s48)* node4(s47). % 76.03/76.20 34160[114:Spt:34159.0] || -> until2p7(s48)*. % 76.03/76.20 34161[114:MRR:559.0,34160.0] || -> until2p7(s49)* node4(s48). % 76.03/76.20 34162[115:Spt:34161.0] || -> until2p7(s49)*. % 76.03/76.20 34163[115:MRR:194.0,34162.0] || -> node4(s49)*. % 76.03/76.20 34164[115:MRR:34106.0,34163.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.03/76.20 34165[115:Res:53.1,34164.0] || -> m_main_v_state(s49,c_busy)*. % 76.03/76.20 34167[115:MRR:34165.0,33941.0] || -> . % 76.03/76.20 34168[115:Spt:34167.0,34161.0,34162.0] || until2p7(s49)*+ -> . % 76.03/76.20 34169[115:Spt:34167.0,34161.1] || -> node4(s48)*. % 76.03/76.20 34170[115:MRR:33944.0,34169.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.03/76.20 34173[115:Res:53.1,34170.0] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.20 34176[115:Res:34173.0,61.1] always3(s48) || -> . % 76.03/76.20 34177[115:SSi:34176.0,737.0,33935.0,33947.0,34160.0,34169.0] || -> . % 76.03/76.20 34178[114:Spt:34177.0,34159.0,34160.0] || until2p7(s48)*+ -> . % 76.03/76.20 34179[114:Spt:34177.0,34159.1] || -> node4(s47)*. % 76.03/76.20 34181[114:MRR:777.0,34179.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.03/76.20 34196[114:Res:53.1,34181.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.03/76.20 34198[114:MRR:34196.0,33921.0] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.20 34200[114:Res:34198.0,61.1] always3(s48) || -> . % 76.03/76.20 34201[114:SSi:34200.0,737.0,33935.0,33947.0] || -> . % 76.03/76.20 34202[113:Spt:34201.0,34157.0,34158.0] || until2p7(s47)*+ -> . % 76.03/76.20 34203[113:Spt:34201.0,34157.1] || -> node4(s46)*. % 76.03/76.20 34204[113:MRR:33924.0,34203.0] || m_main_v_state(s46,c_ready)*+ -> . % 76.03/76.20 34207[113:Res:53.1,34204.0] || -> m_main_v_state(s46,c_busy)*. % 76.03/76.20 34210[113:Res:34207.0,61.1] always3(s46) || -> . % 76.03/76.20 34211[113:SSi:34210.0,735.0,33915.0,33930.0,34156.0,34203.0] || -> . % 76.03/76.20 34212[112:Spt:34211.0,34155.0,34156.0] || until2p7(s46)*+ -> . % 76.03/76.20 34213[112:Spt:34211.0,34155.1] || -> node4(s45)*. % 76.03/76.20 34215[112:MRR:783.0,34213.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.03/76.20 34227[112:Res:53.1,34215.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.03/76.20 34229[112:MRR:34227.0,33898.0] || -> m_main_v_state(s46,c_busy)*. % 76.03/76.20 34231[112:Res:34229.0,61.1] always3(s46) || -> . % 76.03/76.20 34232[112:SSi:34231.0,735.0,33915.0,33930.0] || -> . % 76.03/76.20 34233[111:Spt:34232.0,34153.0,34154.0] || until2p7(s45)*+ -> . % 76.03/76.20 34234[111:Spt:34232.0,34153.1] || -> node4(s44)*. % 76.03/76.20 34235[111:MRR:33901.0,34234.0] || m_main_v_state(s44,c_ready)*+ -> . % 76.03/76.20 34238[111:Res:53.1,34235.0] || -> m_main_v_state(s44,c_busy)*. % 76.03/76.20 34241[111:Res:34238.0,61.1] always3(s44) || -> . % 76.03/76.20 34242[111:SSi:34241.0,733.0,33892.0,33904.0,34152.0,34234.0] || -> . % 76.03/76.20 34243[110:Spt:34242.0,34151.0,34152.0] || until2p7(s44)*+ -> . % 76.03/76.20 34244[110:Spt:34242.0,34151.1] || -> node4(s43)*. % 76.03/76.20 34246[110:MRR:789.0,34244.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.03/76.20 34258[110:Res:53.1,34246.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.03/76.20 34260[110:MRR:34258.0,33878.0] || -> m_main_v_state(s44,c_busy)*. % 76.03/76.20 34265[110:Res:34260.0,61.1] always3(s44) || -> . % 76.03/76.20 34266[110:SSi:34265.0,733.0,33892.0,33904.0] || -> . % 76.03/76.20 34267[109:Spt:34266.0,34149.0,34150.0] || until2p7(s43)*+ -> . % 76.03/76.20 34268[109:Spt:34266.0,34149.1] || -> node4(s42)*. % 76.03/76.20 34269[109:MRR:33881.0,34268.0] || m_main_v_state(s42,c_ready)*+ -> . % 76.03/76.20 34272[109:Res:53.1,34269.0] || -> m_main_v_state(s42,c_busy)*. % 76.03/76.20 34276[109:Res:34272.0,61.1] always3(s42) || -> . % 76.03/76.20 34277[109:SSi:34276.0,731.0,33872.0,33884.0,34148.0,34268.0] || -> . % 76.03/76.20 34278[108:Spt:34277.0,34147.0,34148.0] || until2p7(s42)*+ -> . % 76.03/76.20 34279[108:Spt:34277.0,34147.1] || -> node4(s41)*. % 76.03/76.20 34281[108:MRR:795.0,34279.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.03/76.20 34292[108:Res:53.1,34281.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.03/76.20 34294[108:MRR:34292.0,33858.0] || -> m_main_v_state(s42,c_busy)*. % 76.03/76.20 34296[108:Res:34294.0,61.1] always3(s42) || -> . % 76.03/76.20 34297[108:SSi:34296.0,731.0,33872.0,33884.0] || -> . % 76.03/76.20 34298[107:Spt:34297.0,34145.0,34146.0] || until2p7(s41)*+ -> . % 76.03/76.20 34299[107:Spt:34297.0,34145.1] || -> node4(s40)*. % 76.03/76.20 34300[107:MRR:33861.0,34299.0] || m_main_v_state(s40,c_ready)*+ -> . % 76.03/76.20 34304[107:Res:53.1,34300.0] || -> m_main_v_state(s40,c_busy)*. % 76.03/76.20 34307[107:Res:34304.0,61.1] always3(s40) || -> . % 76.03/76.20 34308[107:SSi:34307.0,729.0,33852.0,33867.0,34144.0,34299.0] || -> . % 76.03/76.20 34309[106:Spt:34308.0,34143.0,34144.0] || until2p7(s40)*+ -> . % 76.03/76.20 34310[106:Spt:34308.0,34143.1] || -> node4(s39)*. % 76.03/76.20 34312[106:MRR:801.0,34310.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.03/76.20 34323[106:Res:53.1,34312.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.03/76.20 34325[106:MRR:34323.0,33835.0] || -> m_main_v_state(s40,c_busy)*. % 76.03/76.20 34327[106:Res:34325.0,61.1] always3(s40) || -> . % 76.03/76.20 34328[106:SSi:34327.0,729.0,33852.0,33867.0] || -> . % 76.03/76.20 34329[105:Spt:34328.0,34141.0,34142.0] || until2p7(s39)*+ -> . % 76.03/76.20 34330[105:Spt:34328.0,34141.1] || -> node4(s38)*. % 76.03/76.20 34331[105:MRR:33838.0,34330.0] || m_main_v_state(s38,c_ready)*+ -> . % 76.03/76.20 34334[105:Res:53.1,34331.0] || -> m_main_v_state(s38,c_busy)*. % 76.03/76.20 34337[105:Res:34334.0,61.1] always3(s38) || -> . % 76.03/76.20 34338[105:SSi:34337.0,727.0,33829.0,33841.0,34140.0,34330.0] || -> . % 76.03/76.20 34339[104:Spt:34338.0,34139.0,34140.0] || until2p7(s38)*+ -> . % 76.03/76.20 34340[104:Spt:34338.0,34139.1] || -> node4(s37)*. % 76.03/76.20 34342[104:MRR:807.0,34340.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.03/76.20 34354[104:Res:53.1,34342.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.03/76.20 34356[104:MRR:34354.0,33815.0] || -> m_main_v_state(s38,c_busy)*. % 76.03/76.20 34358[104:Res:34356.0,61.1] always3(s38) || -> . % 76.03/76.20 34359[104:SSi:34358.0,727.0,33829.0,33841.0] || -> . % 76.03/76.20 34360[103:Spt:34359.0,34137.0,34138.0] || until2p7(s37)*+ -> . % 76.03/76.20 34361[103:Spt:34359.0,34137.1] || -> node4(s36)*. % 76.03/76.20 34362[103:MRR:33818.0,34361.0] || m_main_v_state(s36,c_ready)*+ -> . % 76.03/76.20 34365[103:Res:53.1,34362.0] || -> m_main_v_state(s36,c_busy)*. % 76.03/76.20 34368[103:Res:34365.0,61.1] always3(s36) || -> . % 76.03/76.20 34369[103:SSi:34368.0,725.0,33809.0,33821.0,34136.0,34361.0] || -> . % 76.03/76.20 34370[102:Spt:34369.0,34135.0,34136.0] || until2p7(s36)*+ -> . % 76.03/76.20 34371[102:Spt:34369.0,34135.1] || -> node4(s35)*. % 76.03/76.20 34373[102:MRR:813.0,34371.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.03/76.20 34385[102:Res:53.1,34373.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.03/76.20 34387[102:MRR:34385.0,33795.0] || -> m_main_v_state(s36,c_busy)*. % 76.03/76.20 34392[102:Res:34387.0,61.1] always3(s36) || -> . % 76.03/76.20 34393[102:SSi:34392.0,725.0,33809.0,33821.0] || -> . % 76.03/76.20 34394[101:Spt:34393.0,34133.0,34134.0] || until2p7(s35)*+ -> . % 76.03/76.20 34395[101:Spt:34393.0,34133.1] || -> node4(s34)*. % 76.03/76.20 34396[101:MRR:33798.0,34395.0] || m_main_v_state(s34,c_ready)*+ -> . % 76.03/76.20 34399[101:Res:53.1,34396.0] || -> m_main_v_state(s34,c_busy)*. % 76.03/76.20 34403[101:Res:34399.0,61.1] always3(s34) || -> . % 76.03/76.20 34404[101:SSi:34403.0,723.0,33789.0,33804.0,34132.0,34395.0] || -> . % 76.03/76.20 34405[100:Spt:34404.0,34131.0,34132.0] || until2p7(s34)*+ -> . % 76.03/76.20 34406[100:Spt:34404.0,34131.1] || -> node4(s33)*. % 76.03/76.20 34408[100:MRR:819.0,34406.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.03/76.20 34419[100:Res:53.1,34408.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.03/76.20 34421[100:MRR:34419.0,33772.0] || -> m_main_v_state(s34,c_busy)*. % 76.03/76.20 34423[100:Res:34421.0,61.1] always3(s34) || -> . % 76.03/76.20 34424[100:SSi:34423.0,723.0,33789.0,33804.0] || -> . % 76.03/76.20 34425[99:Spt:34424.0,34129.0,34130.0] || until2p7(s33)*+ -> . % 76.03/76.20 34426[99:Spt:34424.0,34129.1] || -> node4(s32)*. % 76.03/76.20 34427[99:MRR:33775.0,34426.0] || m_main_v_state(s32,c_ready)*+ -> . % 76.03/76.20 34431[99:Res:53.1,34427.0] || -> m_main_v_state(s32,c_busy)*. % 76.03/76.20 34434[99:Res:34431.0,61.1] always3(s32) || -> . % 76.03/76.20 34435[99:SSi:34434.0,721.0,33766.0,33778.0,34128.0,34426.0] || -> . % 76.03/76.20 34436[98:Spt:34435.0,34127.0,34128.0] || until2p7(s32)*+ -> . % 76.03/76.20 34437[98:Spt:34435.0,34127.1] || -> node4(s31)*. % 76.03/76.20 34439[98:MRR:825.0,34437.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.03/76.20 34450[98:Res:53.1,34439.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.03/76.20 34452[98:MRR:34450.0,33752.0] || -> m_main_v_state(s32,c_busy)*. % 76.03/76.20 34454[98:Res:34452.0,61.1] always3(s32) || -> . % 76.03/76.20 34455[98:SSi:34454.0,721.0,33766.0,33778.0] || -> . % 76.03/76.20 34456[97:Spt:34455.0,34125.0,34126.0] || until2p7(s31)*+ -> . % 76.03/76.20 34457[97:Spt:34455.0,34125.1] || -> node4(s30)*. % 76.03/76.20 34458[97:MRR:33755.0,34457.0] || m_main_v_state(s30,c_ready)*+ -> . % 76.03/76.20 34461[97:Res:53.1,34458.0] || -> m_main_v_state(s30,c_busy)*. % 76.03/76.20 34464[97:Res:34461.0,61.1] always3(s30) || -> . % 76.03/76.20 34465[97:SSi:34464.0,719.0,33746.0,33758.0,34124.0,34457.0] || -> . % 76.03/76.20 34466[96:Spt:34465.0,34123.0,34124.0] || until2p7(s30)*+ -> . % 76.03/76.20 34467[96:Spt:34465.0,34123.1] || -> node4(s29)*. % 76.03/76.20 34469[96:MRR:831.0,34467.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.03/76.20 34481[96:Res:53.1,34469.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.03/76.20 34483[96:MRR:34481.0,33732.0] || -> m_main_v_state(s30,c_busy)*. % 76.03/76.20 34485[96:Res:34483.0,61.1] always3(s30) || -> . % 76.03/76.20 34486[96:SSi:34485.0,719.0,33746.0,33758.0] || -> . % 76.03/76.20 34487[95:Spt:34486.0,34121.0,34122.0] || until2p7(s29)*+ -> . % 76.03/76.20 34488[95:Spt:34486.0,34121.1] || -> node4(s28)*. % 76.03/76.20 34489[95:MRR:33735.0,34488.0] || m_main_v_state(s28,c_ready)*+ -> . % 76.03/76.20 34492[95:Res:53.1,34489.0] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.20 34495[95:Res:34492.0,61.1] always3(s28) || -> . % 76.03/76.20 34496[95:SSi:34495.0,717.0,33726.0,33741.0,34120.0,34488.0] || -> . % 76.03/76.20 34497[94:Spt:34496.0,34119.0,34120.0] || until2p7(s28)*+ -> . % 76.03/76.20 34498[94:Spt:34496.0,34119.1] || -> node4(s27)*. % 76.03/76.20 34500[94:MRR:837.0,34498.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.03/76.20 34512[94:Res:53.1,34500.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.03/76.20 34517[95:Spt:34512.0] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.20 34519[95:Res:34517.0,61.1] always3(s27) || -> . % 76.03/76.20 34520[95:SSi:34519.0,716.0,33720.0,33725.0,34118.0,34498.0] || -> . % 76.03/76.20 34521[95:Spt:34520.0,34512.0,34517.0] || m_main_v_state(s27,c_busy)* -> . % 76.03/76.20 34522[95:Spt:34520.0,34512.1] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.20 34526[95:Res:34522.0,61.1] always3(s28) || -> . % 76.03/76.20 34527[95:SSi:34526.0,717.0,33726.0,33741.0] || -> . % 76.03/76.20 34528[93:Spt:34527.0,34117.0,34118.0] || until2p7(s27)*+ -> . % 76.03/76.20 34529[93:Spt:34527.0,34117.1] || -> node4(s26)*. % 76.03/76.20 34531[93:MRR:840.0,34529.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.03/76.20 34538[93:Res:53.1,34531.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.03/76.20 34540[94:Spt:34538.0] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.20 34542[94:Res:34540.0,61.1] always3(s26) || -> . % 76.03/76.20 34543[94:SSi:34542.0,715.0,33717.0,33719.0,34116.0,34529.0] || -> . % 76.03/76.20 34544[94:Spt:34543.0,34538.0,34540.0] || m_main_v_state(s26,c_busy)* -> . % 76.03/76.20 34545[94:Spt:34543.0,34538.1] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.20 34549[94:Res:34545.0,61.1] always3(s27) || -> . % 76.03/76.20 34550[94:SSi:34549.0,716.0,33720.0,33725.0] || -> . % 76.03/76.20 34551[92:Spt:34550.0,34115.0,34116.0] || until2p7(s26)*+ -> . % 76.03/76.20 34552[92:Spt:34550.0,34115.1] || -> node4(s25)*. % 76.03/76.20 34554[92:MRR:843.0,34552.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.03/76.20 34557[92:Res:53.1,34554.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.03/76.20 34562[93:Spt:34557.0] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.20 34564[93:Res:34562.0,61.1] always3(s25) || -> . % 76.03/76.20 34565[93:SSi:34564.0,714.0,33711.0,33716.0,34114.0,34552.0] || -> . % 76.03/76.20 34566[93:Spt:34565.0,34557.0,34562.0] || m_main_v_state(s25,c_busy)* -> . % 76.03/76.20 34567[93:Spt:34565.0,34557.1] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.20 34571[93:Res:34567.0,61.1] always3(s26) || -> . % 76.03/76.20 34572[93:SSi:34571.0,715.0,33717.0,33719.0] || -> . % 76.03/76.20 34573[91:Spt:34572.0,34113.0,34114.0] || until2p7(s25)*+ -> . % 76.03/76.20 34574[91:Spt:34572.0,34113.1] || -> node4(s24)*. % 76.03/76.20 34576[91:MRR:846.0,34574.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.03/76.20 34579[91:Res:53.1,34576.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.03/76.20 34581[92:Spt:34579.0] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.20 34583[92:Res:34581.0,61.1] always3(s24) || -> . % 76.03/76.20 34584[92:SSi:34583.0,713.0,33708.0,33710.0,34112.0,34574.0] || -> . % 76.03/76.20 34585[92:Spt:34584.0,34579.0,34581.0] || m_main_v_state(s24,c_busy)* -> . % 76.03/76.20 34586[92:Spt:34584.0,34579.1] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.20 34590[92:Res:34586.0,61.1] always3(s25) || -> . % 76.03/76.20 34591[92:SSi:34590.0,714.0,33711.0,33716.0] || -> . % 76.03/76.20 34592[90:Spt:34591.0,34111.0,34112.0] || until2p7(s24)*+ -> . % 76.03/76.20 34593[90:Spt:34591.0,34111.1] || -> node4(s23)*. % 76.03/76.20 34595[90:MRR:849.0,34593.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.03/76.20 34598[90:Res:53.1,34595.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.03/76.20 34600[90:MRR:34598.0,34101.0] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.20 34602[90:Res:34600.0,61.1] always3(s24) || -> . % 76.03/76.20 34603[90:SSi:34602.0,713.0,33708.0,33710.0] || -> . % 76.03/76.20 34604[88:Spt:34603.0,33945.1,33947.0] || xuntil6(s48)* -> . % 76.03/76.20 34605[88:Spt:34603.0,33945.0] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.20 34608[88:Res:34605.0,61.1] always3(s48) || -> . % 76.03/76.20 34609[88:SSi:34608.0,737.0,33935.0] || -> . % 76.03/76.20 34610[86:Spt:34609.0,33932.2,33934.0] || xuntil6(s47)*+ -> . % 76.03/76.20 34611[86:Spt:34609.0,33932.0,33932.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.03/76.20 34612[86:Res:53.1,34611.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.03/76.20 34614[86:MRR:34612.0,33921.0] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.20 34617[86:Res:34614.0,61.1] always3(s48) || -> . % 76.03/76.20 34618[86:SSi:34617.0,737.0] || -> . % 76.03/76.20 34619[85:Spt:34618.0,33925.1,33930.0] || xuntil6(s46)* -> . % 76.03/76.20 34620[85:Spt:34618.0,33925.0] || -> m_main_v_state(s46,c_busy)*. % 76.03/76.20 34623[85:Res:34620.0,61.1] always3(s46) || -> . % 76.03/76.20 34624[85:SSi:34623.0,735.0,33915.0] || -> . % 76.03/76.20 34625[83:Spt:34624.0,33906.2,33914.0] || xuntil6(s45)*+ -> . % 76.03/76.20 34626[83:Spt:34624.0,33906.0,33906.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.03/76.20 34627[83:Res:53.1,34626.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.03/76.20 34629[83:MRR:34627.0,33898.0] || -> m_main_v_state(s46,c_busy)*. % 76.03/76.20 34631[83:Res:34629.0,61.1] always3(s46) || -> . % 76.03/76.20 34632[83:SSi:34631.0,735.0] || -> . % 76.03/76.20 34633[82:Spt:34632.0,33902.1,33904.0] || xuntil6(s44)* -> . % 76.03/76.20 34634[82:Spt:34632.0,33902.0] || -> m_main_v_state(s44,c_busy)*. % 76.03/76.20 34637[82:Res:34634.0,61.1] always3(s44) || -> . % 76.03/76.20 34638[82:SSi:34637.0,733.0,33892.0] || -> . % 76.03/76.20 34639[80:Spt:34638.0,33886.2,33891.0] || xuntil6(s43)*+ -> . % 76.03/76.20 34640[80:Spt:34638.0,33886.0,33886.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.03/76.20 34641[80:Res:53.1,34640.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.03/76.20 34643[80:MRR:34641.0,33878.0] || -> m_main_v_state(s44,c_busy)*. % 76.03/76.20 34646[80:Res:34643.0,61.1] always3(s44) || -> . % 76.03/76.20 34647[80:SSi:34646.0,733.0] || -> . % 76.03/76.20 34648[79:Spt:34647.0,33882.1,33884.0] || xuntil6(s42)* -> . % 76.03/76.20 34649[79:Spt:34647.0,33882.0] || -> m_main_v_state(s42,c_busy)*. % 76.03/76.20 34652[79:Res:34649.0,61.1] always3(s42) || -> . % 76.03/76.20 34653[79:SSi:34652.0,731.0,33872.0] || -> . % 76.03/76.20 34654[77:Spt:34653.0,33869.2,33871.0] || xuntil6(s41)*+ -> . % 76.03/76.20 34655[77:Spt:34653.0,33869.0,33869.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.03/76.20 34656[77:Res:53.1,34655.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.03/76.20 34658[77:MRR:34656.0,33858.0] || -> m_main_v_state(s42,c_busy)*. % 76.03/76.20 34660[77:Res:34658.0,61.1] always3(s42) || -> . % 76.03/76.20 34661[77:SSi:34660.0,731.0] || -> . % 76.03/76.20 34662[76:Spt:34661.0,33862.1,33867.0] || xuntil6(s40)* -> . % 76.03/76.20 34663[76:Spt:34661.0,33862.0] || -> m_main_v_state(s40,c_busy)*. % 76.03/76.20 34666[76:Res:34663.0,61.1] always3(s40) || -> . % 76.03/76.20 34667[76:SSi:34666.0,729.0,33852.0] || -> . % 76.03/76.20 34668[74:Spt:34667.0,33843.2,33851.0] || xuntil6(s39)*+ -> . % 76.03/76.20 34669[74:Spt:34667.0,33843.0,33843.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.03/76.20 34670[74:Res:53.1,34669.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.03/76.20 34672[74:MRR:34670.0,33835.0] || -> m_main_v_state(s40,c_busy)*. % 76.03/76.20 34674[74:Res:34672.0,61.1] always3(s40) || -> . % 76.03/76.20 34675[74:SSi:34674.0,729.0] || -> . % 76.03/76.20 34676[73:Spt:34675.0,33839.1,33841.0] || xuntil6(s38)* -> . % 76.03/76.20 34677[73:Spt:34675.0,33839.0] || -> m_main_v_state(s38,c_busy)*. % 76.03/76.20 34680[73:Res:34677.0,61.1] always3(s38) || -> . % 76.03/76.20 34681[73:SSi:34680.0,727.0,33829.0] || -> . % 76.03/76.20 34682[71:Spt:34681.0,33823.2,33828.0] || xuntil6(s37)*+ -> . % 76.03/76.20 34683[71:Spt:34681.0,33823.0,33823.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.03/76.20 34684[71:Res:53.1,34683.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.03/76.20 34686[71:MRR:34684.0,33815.0] || -> m_main_v_state(s38,c_busy)*. % 76.03/76.20 34688[71:Res:34686.0,61.1] always3(s38) || -> . % 76.03/76.20 34689[71:SSi:34688.0,727.0] || -> . % 76.03/76.20 34690[70:Spt:34689.0,33819.1,33821.0] || xuntil6(s36)* -> . % 76.03/76.20 34691[70:Spt:34689.0,33819.0] || -> m_main_v_state(s36,c_busy)*. % 76.03/76.20 34694[70:Res:34691.0,61.1] always3(s36) || -> . % 76.03/76.20 34695[70:SSi:34694.0,725.0,33809.0] || -> . % 76.03/76.20 34696[68:Spt:34695.0,33806.2,33808.0] || xuntil6(s35)*+ -> . % 76.03/76.20 34697[68:Spt:34695.0,33806.0,33806.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.03/76.20 34698[68:Res:53.1,34697.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.03/76.20 34700[68:MRR:34698.0,33795.0] || -> m_main_v_state(s36,c_busy)*. % 76.03/76.20 34702[68:Res:34700.0,61.1] always3(s36) || -> . % 76.03/76.20 34703[68:SSi:34702.0,725.0] || -> . % 76.03/76.20 34704[67:Spt:34703.0,33799.1,33804.0] || xuntil6(s34)* -> . % 76.03/76.20 34705[67:Spt:34703.0,33799.0] || -> m_main_v_state(s34,c_busy)*. % 76.03/76.20 34708[67:Res:34705.0,61.1] always3(s34) || -> . % 76.03/76.20 34709[67:SSi:34708.0,723.0,33789.0] || -> . % 76.03/76.20 34710[65:Spt:34709.0,33780.2,33788.0] || xuntil6(s33)*+ -> . % 76.03/76.20 34711[65:Spt:34709.0,33780.0,33780.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.03/76.20 34712[65:Res:53.1,34711.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.03/76.20 34714[65:MRR:34712.0,33772.0] || -> m_main_v_state(s34,c_busy)*. % 76.03/76.20 34716[65:Res:34714.0,61.1] always3(s34) || -> . % 76.03/76.20 34717[65:SSi:34716.0,723.0] || -> . % 76.03/76.20 34718[64:Spt:34717.0,33776.1,33778.0] || xuntil6(s32)* -> . % 76.03/76.20 34719[64:Spt:34717.0,33776.0] || -> m_main_v_state(s32,c_busy)*. % 76.03/76.20 34722[64:Res:34719.0,61.1] always3(s32) || -> . % 76.03/76.20 34723[64:SSi:34722.0,721.0,33766.0] || -> . % 76.03/76.20 34724[62:Spt:34723.0,33760.2,33765.0] || xuntil6(s31)*+ -> . % 76.03/76.20 34725[62:Spt:34723.0,33760.0,33760.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.03/76.20 34726[62:Res:53.1,34725.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.03/76.20 34728[62:MRR:34726.0,33752.0] || -> m_main_v_state(s32,c_busy)*. % 76.03/76.20 34730[62:Res:34728.0,61.1] always3(s32) || -> . % 76.03/76.20 34731[62:SSi:34730.0,721.0] || -> . % 76.03/76.20 34732[61:Spt:34731.0,33756.1,33758.0] || xuntil6(s30)* -> . % 76.03/76.20 34733[61:Spt:34731.0,33756.0] || -> m_main_v_state(s30,c_busy)*. % 76.03/76.20 34736[61:Res:34733.0,61.1] always3(s30) || -> . % 76.03/76.20 34737[61:SSi:34736.0,719.0,33746.0] || -> . % 76.03/76.20 34738[59:Spt:34737.0,33743.2,33745.0] || xuntil6(s29)*+ -> . % 76.03/76.20 34739[59:Spt:34737.0,33743.0,33743.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.03/76.20 34740[59:Res:53.1,34739.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.03/76.20 34742[59:MRR:34740.0,33732.0] || -> m_main_v_state(s30,c_busy)*. % 76.03/76.20 34744[59:Res:34742.0,61.1] always3(s30) || -> . % 76.03/76.20 34745[59:SSi:34744.0,719.0] || -> . % 76.03/76.20 34746[58:Spt:34745.0,33736.1,33741.0] || xuntil6(s28)* -> . % 76.03/76.20 34747[58:Spt:34745.0,33736.0] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.20 34750[58:Res:34747.0,61.1] always3(s28) || -> . % 76.03/76.20 34751[58:SSi:34750.0,717.0,33726.0] || -> . % 76.03/76.20 34752[56:Spt:34751.0,33721.2,33725.0] || xuntil6(s27)*+ -> . % 76.03/76.20 34753[56:Spt:34751.0,33721.0,33721.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.03/76.20 34754[56:Res:53.1,34753.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.03/76.20 34756[57:Spt:34754.1] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.20 34758[57:Res:34756.0,61.1] always3(s28) || -> . % 76.03/76.20 34759[57:SSi:34758.0,717.0] || -> . % 76.03/76.20 34760[57:Spt:34759.0,34754.1,34756.0] || m_main_v_state(s28,c_busy)* -> . % 76.03/76.20 34761[57:Spt:34759.0,34754.0] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.20 34764[57:Res:34761.0,61.1] always3(s27) || -> . % 76.03/76.20 34765[57:SSi:34764.0,716.0,33720.0] || -> . % 76.03/76.20 34766[55:Spt:34765.0,33718.2,33719.0] || xuntil6(s26)*+ -> . % 76.03/76.20 34767[55:Spt:34765.0,33718.0,33718.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.03/76.20 34768[55:Res:53.1,34767.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.03/76.20 34770[56:Spt:34768.1] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.20 34772[56:Res:34770.0,61.1] always3(s27) || -> . % 76.03/76.20 34773[56:SSi:34772.0,716.0] || -> . % 76.03/76.20 34774[56:Spt:34773.0,34768.1,34770.0] || m_main_v_state(s27,c_busy)* -> . % 76.03/76.20 34775[56:Spt:34773.0,34768.0] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.20 34778[56:Res:34775.0,61.1] always3(s26) || -> . % 76.03/76.20 34779[56:SSi:34778.0,715.0,33717.0] || -> . % 76.03/76.20 34780[54:Spt:34779.0,33712.2,33716.0] || xuntil6(s25)*+ -> . % 76.03/76.20 34781[54:Spt:34779.0,33712.0,33712.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.03/76.20 34782[54:Res:53.1,34781.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.03/76.20 34784[55:Spt:34782.1] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.20 34786[55:Res:34784.0,61.1] always3(s26) || -> . % 76.03/76.20 34787[55:SSi:34786.0,715.0] || -> . % 76.03/76.20 34788[55:Spt:34787.0,34782.1,34784.0] || m_main_v_state(s26,c_busy)* -> . % 76.03/76.20 34789[55:Spt:34787.0,34782.0] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.20 34792[55:Res:34789.0,61.1] always3(s25) || -> . % 76.03/76.20 34793[55:SSi:34792.0,714.0,33711.0] || -> . % 76.03/76.20 34794[53:Spt:34793.0,33709.2,33710.0] || xuntil6(s24)*+ -> . % 76.03/76.20 34795[53:Spt:34793.0,33709.0,33709.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.03/76.20 34796[53:Res:53.1,34795.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.03/76.20 34798[54:Spt:34796.1] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.20 34800[54:Res:34798.0,61.1] always3(s25) || -> . % 76.03/76.20 34801[54:SSi:34800.0,714.0] || -> . % 76.03/76.20 34802[54:Spt:34801.0,34796.1,34798.0] || m_main_v_state(s25,c_busy)* -> . % 76.03/76.20 34803[54:Spt:34801.0,34796.0] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.20 34806[54:Res:34803.0,61.1] always3(s24) || -> . % 76.03/76.20 34807[54:SSi:34806.0,713.0,33708.0] || -> . % 76.03/76.20 34808[52:Spt:34807.0,33703.2,33707.0] || xuntil6(s23)*+ -> . % 76.03/76.20 34809[52:Spt:34807.0,33703.0,33703.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.03/76.20 34810[52:Res:53.1,34809.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.03/76.20 34812[53:Spt:34810.1] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.20 34814[53:Res:34812.0,61.1] always3(s24) || -> . % 76.03/76.20 34815[53:SSi:34814.0,713.0] || -> . % 76.03/76.20 34816[53:Spt:34815.0,34810.1,34812.0] || m_main_v_state(s24,c_busy)* -> . % 76.03/76.20 34817[53:Spt:34815.0,34810.0] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.20 34820[53:Res:34817.0,61.1] always3(s23) || -> . % 76.03/76.20 34821[53:SSi:34820.0,712.0,33702.0] || -> . % 76.03/76.20 34822[51:Spt:34821.0,33700.2,33701.0] || xuntil6(s22)*+ -> . % 76.03/76.20 34823[51:Spt:34821.0,33700.0,33700.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.03/76.20 34824[51:Res:53.1,34823.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.03/76.20 34826[52:Spt:34824.0] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.20 34828[52:Res:34826.0,61.1] always3(s22) || -> . % 76.03/76.20 34829[52:SSi:34828.0,711.0,33699.0] || -> . % 76.03/76.20 34830[52:Spt:34829.0,34824.0,34826.0] || m_main_v_state(s22,c_busy)* -> . % 76.03/76.20 34831[52:Spt:34829.0,34824.1] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.20 34835[52:Res:34831.0,61.1] always3(s23) || -> . % 76.03/76.20 34836[52:SSi:34835.0,712.0] || -> . % 76.03/76.20 34837[50:Spt:34836.0,33694.2,33698.0] || xuntil6(s21)*+ -> . % 76.03/76.20 34838[50:Spt:34836.0,33694.0,33694.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.03/76.20 34839[50:Res:53.1,34838.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.03/76.20 34844[51:Spt:34839.0] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.20 34846[51:Res:34844.0,61.1] always3(s21) || -> . % 76.03/76.20 34847[51:SSi:34846.0,710.0,33693.0] || -> . % 76.03/76.20 34848[51:Spt:34847.0,34839.0,34844.0] || m_main_v_state(s21,c_busy)* -> . % 76.03/76.20 34849[51:Spt:34847.0,34839.1] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.20 34853[51:Res:34849.0,61.1] always3(s22) || -> . % 76.03/76.20 34854[51:SSi:34853.0,711.0] || -> . % 76.03/76.20 34855[49:Spt:34854.0,33691.2,33692.0] || xuntil6(s20)*+ -> . % 76.03/76.20 34856[49:Spt:34854.0,33691.0,33691.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.03/76.20 34857[49:Res:53.1,34856.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.03/76.20 34859[50:Spt:34857.0] || -> m_main_v_state(s20,c_busy)*. % 76.03/76.20 34861[50:Res:34859.0,61.1] always3(s20) || -> . % 76.03/76.20 34862[50:SSi:34861.0,709.0,33690.0] || -> . % 76.03/76.20 34863[50:Spt:34862.0,34857.0,34859.0] || m_main_v_state(s20,c_busy)* -> . % 76.03/76.20 34864[50:Spt:34862.0,34857.1] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.20 34868[50:Res:34864.0,61.1] always3(s21) || -> . % 76.03/76.20 34869[50:SSi:34868.0,710.0] || -> . % 76.03/76.20 34870[48:Spt:34869.0,33685.2,33689.0] || xuntil6(s19)*+ -> . % 76.03/76.20 34871[48:Spt:34869.0,33685.0,33685.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.03/76.20 34872[48:Res:53.1,34871.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.03/76.20 34874[49:Spt:34872.0] || -> m_main_v_state(s19,c_busy)*. % 76.03/76.20 34876[49:Res:34874.0,61.1] always3(s19) || -> . % 76.03/76.20 34877[49:SSi:34876.0,708.0,33684.0] || -> . % 76.03/76.20 34878[49:Spt:34877.0,34872.0,34874.0] || m_main_v_state(s19,c_busy)* -> . % 76.03/76.20 34879[49:Spt:34877.0,34872.1] || -> m_main_v_state(s20,c_busy)*. % 76.03/76.20 34883[49:Res:34879.0,61.1] always3(s20) || -> . % 76.03/76.20 34884[49:SSi:34883.0,709.0] || -> . % 76.03/76.20 34885[47:Spt:34884.0,33682.2,33683.0] || xuntil6(s18)*+ -> . % 76.03/76.20 34886[47:Spt:34884.0,33682.0,33682.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.03/76.20 34887[47:Res:53.1,34886.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.03/76.20 34892[48:Spt:34887.0] || -> m_main_v_state(s18,c_busy)*. % 76.03/76.20 34894[48:Res:34892.0,61.1] always3(s18) || -> . % 76.03/76.20 34895[48:SSi:34894.0,707.0,33681.0] || -> . % 76.03/76.20 34896[48:Spt:34895.0,34887.0,34892.0] || m_main_v_state(s18,c_busy)* -> . % 76.03/76.20 34897[48:Spt:34895.0,34887.1] || -> m_main_v_state(s19,c_busy)*. % 76.03/76.20 34901[48:Res:34897.0,61.1] always3(s19) || -> . % 76.03/76.20 34902[48:SSi:34901.0,708.0] || -> . % 76.03/76.20 34903[46:Spt:34902.0,33676.2,33680.0] || xuntil6(s17)*+ -> . % 76.03/76.20 34904[46:Spt:34902.0,33676.0,33676.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.03/76.20 34905[46:Res:53.1,34904.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.03/76.20 34907[47:Spt:34905.0] || -> m_main_v_state(s17,c_busy)*. % 76.03/76.20 34909[47:Res:34907.0,61.1] always3(s17) || -> . % 76.03/76.20 34910[47:SSi:34909.0,706.0,33675.0] || -> . % 76.03/76.20 34911[47:Spt:34910.0,34905.0,34907.0] || m_main_v_state(s17,c_busy)* -> . % 76.03/76.20 34912[47:Spt:34910.0,34905.1] || -> m_main_v_state(s18,c_busy)*. % 76.03/76.20 34916[47:Res:34912.0,61.1] always3(s18) || -> . % 76.03/76.20 34917[47:SSi:34916.0,707.0] || -> . % 76.03/76.20 34918[45:Spt:34917.0,33673.2,33674.0] || xuntil6(s16)*+ -> . % 76.03/76.20 34919[45:Spt:34917.0,33673.0,33673.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.03/76.20 34920[45:Res:53.1,34919.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.03/76.20 34922[46:Spt:34920.0] || -> m_main_v_state(s16,c_busy)*. % 76.03/76.20 34924[46:Res:34922.0,61.1] always3(s16) || -> . % 76.03/76.20 34925[46:SSi:34924.0,705.0,33672.0] || -> . % 76.03/76.20 34926[46:Spt:34925.0,34920.0,34922.0] || m_main_v_state(s16,c_busy)* -> . % 76.03/76.20 34927[46:Spt:34925.0,34920.1] || -> m_main_v_state(s17,c_busy)*. % 76.03/76.20 34931[46:Res:34927.0,61.1] always3(s17) || -> . % 76.03/76.20 34932[46:SSi:34931.0,706.0] || -> . % 76.03/76.20 34933[44:Spt:34932.0,33667.2,33671.0] || xuntil6(s15)*+ -> . % 76.03/76.20 34934[44:Spt:34932.0,33667.0,33667.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.03/76.20 34935[44:Res:53.1,34934.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.03/76.20 34940[45:Spt:34935.0] || -> m_main_v_state(s15,c_busy)*. % 76.03/76.20 34942[45:Res:34940.0,61.1] always3(s15) || -> . % 76.03/76.20 34943[45:SSi:34942.0,704.0,33666.0] || -> . % 76.03/76.20 34944[45:Spt:34943.0,34935.0,34940.0] || m_main_v_state(s15,c_busy)* -> . % 76.03/76.20 34945[45:Spt:34943.0,34935.1] || -> m_main_v_state(s16,c_busy)*. % 76.03/76.20 34949[45:Res:34945.0,61.1] always3(s16) || -> . % 76.03/76.20 34950[45:SSi:34949.0,705.0] || -> . % 76.03/76.20 34951[43:Spt:34950.0,33664.2,33665.0] || xuntil6(s14)*+ -> . % 76.03/76.20 34952[43:Spt:34950.0,33664.0,33664.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.03/76.20 34953[43:Res:53.1,34952.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.03/76.20 34955[44:Spt:34953.0] || -> m_main_v_state(s14,c_busy)*. % 76.03/76.20 34957[44:Res:34955.0,61.1] always3(s14) || -> . % 76.03/76.20 34958[44:SSi:34957.0,703.0,33663.0] || -> . % 76.03/76.20 34959[44:Spt:34958.0,34953.0,34955.0] || m_main_v_state(s14,c_busy)* -> . % 76.03/76.20 34960[44:Spt:34958.0,34953.1] || -> m_main_v_state(s15,c_busy)*. % 76.03/76.20 34964[44:Res:34960.0,61.1] always3(s15) || -> . % 76.03/76.20 34965[44:SSi:34964.0,704.0] || -> . % 76.03/76.20 34966[42:Spt:34965.0,33658.2,33662.0] || xuntil6(s13)*+ -> . % 76.03/76.20 34967[42:Spt:34965.0,33658.0,33658.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.03/76.20 34968[42:Res:53.1,34967.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.03/76.20 34970[43:Spt:34968.0] || -> m_main_v_state(s13,c_busy)*. % 76.03/76.20 34972[43:Res:34970.0,61.1] always3(s13) || -> . % 76.03/76.20 34973[43:SSi:34972.0,702.0,33657.0] || -> . % 76.03/76.20 34974[43:Spt:34973.0,34968.0,34970.0] || m_main_v_state(s13,c_busy)* -> . % 76.03/76.20 34975[43:Spt:34973.0,34968.1] || -> m_main_v_state(s14,c_busy)*. % 76.03/76.20 34979[43:Res:34975.0,61.1] always3(s14) || -> . % 76.03/76.20 34980[43:SSi:34979.0,703.0] || -> . % 76.03/76.20 34981[41:Spt:34980.0,33655.2,33656.0] || xuntil6(s12)*+ -> . % 76.03/76.20 34982[41:Spt:34980.0,33655.0,33655.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.03/76.20 34983[41:Res:53.1,34982.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.03/76.20 34988[42:Spt:34983.0] || -> m_main_v_state(s12,c_busy)*. % 76.03/76.20 34990[42:Res:34988.0,61.1] always3(s12) || -> . % 76.03/76.20 34991[42:SSi:34990.0,701.0,33654.0] || -> . % 76.03/76.20 34992[42:Spt:34991.0,34983.0,34988.0] || m_main_v_state(s12,c_busy)* -> . % 76.03/76.20 34993[42:Spt:34991.0,34983.1] || -> m_main_v_state(s13,c_busy)*. % 76.03/76.20 34997[42:Res:34993.0,61.1] always3(s13) || -> . % 76.03/76.20 34998[42:SSi:34997.0,702.0] || -> . % 76.03/76.20 34999[40:Spt:34998.0,33649.2,33653.0] || xuntil6(s11)*+ -> . % 76.03/76.20 35000[40:Spt:34998.0,33649.0,33649.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.03/76.20 35001[40:Res:53.1,35000.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.03/76.20 35003[41:Spt:35001.0] || -> m_main_v_state(s11,c_busy)*. % 76.03/76.20 35005[41:Res:35003.0,61.1] always3(s11) || -> . % 76.03/76.20 35006[41:SSi:35005.0,700.0,33648.0] || -> . % 76.03/76.20 35007[41:Spt:35006.0,35001.0,35003.0] || m_main_v_state(s11,c_busy)* -> . % 76.03/76.20 35008[41:Spt:35006.0,35001.1] || -> m_main_v_state(s12,c_busy)*. % 76.03/76.20 35012[41:Res:35008.0,61.1] always3(s12) || -> . % 76.03/76.20 35013[41:SSi:35012.0,701.0] || -> . % 76.03/76.20 35014[39:Spt:35013.0,33646.2,33647.0] || xuntil6(s10)*+ -> . % 76.03/76.20 35015[39:Spt:35013.0,33646.0,33646.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.03/76.20 35016[39:Res:53.1,35015.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.03/76.20 35018[40:Spt:35016.0] || -> m_main_v_state(s10,c_busy)*. % 76.03/76.20 35020[40:Res:35018.0,61.1] always3(s10) || -> . % 76.03/76.20 35021[40:SSi:35020.0,699.0,33645.0] || -> . % 76.03/76.20 35022[40:Spt:35021.0,35016.0,35018.0] || m_main_v_state(s10,c_busy)* -> . % 76.03/76.20 35023[40:Spt:35021.0,35016.1] || -> m_main_v_state(s11,c_busy)*. % 76.03/76.20 35027[40:Res:35023.0,61.1] always3(s11) || -> . % 76.03/76.20 35028[40:SSi:35027.0,700.0] || -> . % 76.03/76.20 35029[38:Spt:35028.0,33640.2,33644.0] || xuntil6(s9)*+ -> . % 76.03/76.20 35030[38:Spt:35028.0,33640.0,33640.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.03/76.20 35031[38:Res:53.1,35030.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.03/76.20 35036[39:Spt:35031.0] || -> m_main_v_state(s9,c_busy)*. % 76.03/76.20 35038[39:Res:35036.0,61.1] always3(s9) || -> . % 76.03/76.20 35039[39:SSi:35038.0,698.0,33639.0] || -> . % 76.03/76.20 35040[39:Spt:35039.0,35031.0,35036.0] || m_main_v_state(s9,c_busy)* -> . % 76.03/76.20 35041[39:Spt:35039.0,35031.1] || -> m_main_v_state(s10,c_busy)*. % 76.03/76.20 35045[39:Res:35041.0,61.1] always3(s10) || -> . % 76.03/76.20 35046[39:SSi:35045.0,699.0] || -> . % 76.03/76.20 35047[37:Spt:35046.0,33637.2,33638.0] || xuntil6(s8)*+ -> . % 76.03/76.20 35048[37:Spt:35046.0,33637.0,33637.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.03/76.20 35049[37:Res:53.1,35048.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.03/76.20 35051[38:Spt:35049.0] || -> m_main_v_state(s8,c_busy)*. % 76.03/76.20 35053[38:Res:35051.0,61.1] always3(s8) || -> . % 76.03/76.20 35054[38:SSi:35053.0,697.0,33636.0] || -> . % 76.03/76.20 35055[38:Spt:35054.0,35049.0,35051.0] || m_main_v_state(s8,c_busy)* -> . % 76.03/76.20 35056[38:Spt:35054.0,35049.1] || -> m_main_v_state(s9,c_busy)*. % 76.03/76.20 35060[38:Res:35056.0,61.1] always3(s9) || -> . % 76.03/76.20 35061[38:SSi:35060.0,698.0] || -> . % 76.03/76.20 35062[36:Spt:35061.0,33631.2,33635.0] || xuntil6(s7)*+ -> . % 76.03/76.20 35063[36:Spt:35061.0,33631.0,33631.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.03/76.20 35064[36:Res:53.1,35063.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.03/76.20 35066[37:Spt:35064.0] || -> m_main_v_state(s7,c_busy)*. % 76.03/76.20 35068[37:Res:35066.0,61.1] always3(s7) || -> . % 76.03/76.20 35069[37:SSi:35068.0,696.0,33630.0] || -> . % 76.03/76.20 35070[37:Spt:35069.0,35064.0,35066.0] || m_main_v_state(s7,c_busy)* -> . % 76.03/76.20 35071[37:Spt:35069.0,35064.1] || -> m_main_v_state(s8,c_busy)*. % 76.03/76.20 35075[37:Res:35071.0,61.1] always3(s8) || -> . % 76.03/76.20 35076[37:SSi:35075.0,697.0] || -> . % 76.03/76.20 35077[35:Spt:35076.0,33628.2,33629.0] || xuntil6(s6)*+ -> . % 76.03/76.20 35078[35:Spt:35076.0,33628.0,33628.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.03/76.20 35079[35:Res:53.1,35078.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.03/76.20 35084[36:Spt:35079.0] || -> m_main_v_state(s6,c_busy)*. % 76.03/76.20 35086[36:Res:35084.0,61.1] always3(s6) || -> . % 76.03/76.20 35087[36:SSi:35086.0,695.0,33627.0] || -> . % 76.03/76.20 35088[36:Spt:35087.0,35079.0,35084.0] || m_main_v_state(s6,c_busy)* -> . % 76.03/76.20 35089[36:Spt:35087.0,35079.1] || -> m_main_v_state(s7,c_busy)*. % 76.03/76.20 35093[36:Res:35089.0,61.1] always3(s7) || -> . % 76.03/76.20 35094[36:SSi:35093.0,696.0] || -> . % 76.03/76.20 35095[34:Spt:35094.0,33622.2,33626.0] || xuntil6(s5)*+ -> . % 76.03/76.20 35096[34:Spt:35094.0,33622.0,33622.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.03/76.20 35097[34:Res:53.1,35096.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.03/76.20 35099[35:Spt:35097.0] || -> m_main_v_state(s5,c_busy)*. % 76.03/76.20 35101[35:Res:35099.0,61.1] always3(s5) || -> . % 76.03/76.20 35102[35:SSi:35101.0,694.0,33621.0] || -> . % 76.03/76.20 35103[35:Spt:35102.0,35097.0,35099.0] || m_main_v_state(s5,c_busy)* -> . % 76.03/76.20 35104[35:Spt:35102.0,35097.1] || -> m_main_v_state(s6,c_busy)*. % 76.03/76.20 35108[35:Res:35104.0,61.1] always3(s6) || -> . % 76.03/76.20 35109[35:SSi:35108.0,695.0] || -> . % 76.03/76.20 35110[33:Spt:35109.0,33619.2,33620.0] || xuntil6(s4)*+ -> . % 76.03/76.20 35111[33:Spt:35109.0,33619.0,33619.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.03/76.20 35112[33:Res:53.1,35111.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.03/76.20 35114[34:Spt:35112.0] || -> m_main_v_state(s4,c_busy)*. % 76.03/76.20 35116[34:Res:35114.0,61.1] always3(s4) || -> . % 76.03/76.20 35117[34:SSi:35116.0,693.0,33618.0] || -> . % 76.03/76.20 35118[34:Spt:35117.0,35112.0,35114.0] || m_main_v_state(s4,c_busy)* -> . % 76.03/76.20 35119[34:Spt:35117.0,35112.1] || -> m_main_v_state(s5,c_busy)*. % 76.03/76.20 35123[34:Res:35119.0,61.1] always3(s5) || -> . % 76.03/76.20 35124[34:SSi:35123.0,694.0] || -> . % 76.03/76.20 35125[32:Spt:35124.0,33613.2,33617.0] || xuntil6(s3)*+ -> . % 76.03/76.20 35126[32:Spt:35124.0,33613.0,33613.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.03/76.20 35127[32:Res:53.1,35126.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.03/76.20 35132[33:Spt:35127.0] || -> m_main_v_state(s3,c_busy)*. % 76.03/76.20 35134[33:Res:35132.0,61.1] always3(s3) || -> . % 76.03/76.20 35135[33:SSi:35134.0,692.0,33612.0] || -> . % 76.03/76.20 35136[33:Spt:35135.0,35127.0,35132.0] || m_main_v_state(s3,c_busy)* -> . % 76.03/76.20 35137[33:Spt:35135.0,35127.1] || -> m_main_v_state(s4,c_busy)*. % 76.03/76.20 35141[33:Res:35137.0,61.1] always3(s4) || -> . % 76.03/76.20 35142[33:SSi:35141.0,693.0] || -> . % 76.03/76.20 35143[31:Spt:35142.0,33610.2,33611.0] || xuntil6(s2)*+ -> . % 76.03/76.20 35144[31:Spt:35142.0,33610.0,33610.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.03/76.20 35145[31:Res:53.1,35144.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.03/76.20 35147[32:Spt:35145.0] || -> m_main_v_state(s2,c_busy)*. % 76.03/76.20 35149[32:Res:35147.0,61.1] always3(s2) || -> . % 76.03/76.20 35150[32:SSi:35149.0,691.0,33609.0] || -> . % 76.03/76.20 35151[32:Spt:35150.0,35145.0,35147.0] || m_main_v_state(s2,c_busy)* -> . % 76.03/76.20 35152[32:Spt:35150.0,35145.1] || -> m_main_v_state(s3,c_busy)*. % 76.03/76.20 35156[32:Res:35152.0,61.1] always3(s3) || -> . % 76.03/76.20 35157[32:SSi:35156.0,692.0] || -> . % 76.03/76.20 35158[30:Spt:35157.0,33601.2,33608.0] || xuntil6(s1)*+ -> . % 76.03/76.20 35159[30:Spt:35157.0,33601.0,33601.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.03/76.20 35160[30:Res:53.1,35159.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.03/76.20 35162[31:Spt:35160.0] || -> m_main_v_state(s1,c_busy)*. % 76.03/76.20 35164[31:Res:35162.0,61.1] always3(s1) || -> . % 76.03/76.20 35165[31:SSi:35164.0,690.0,33600.0] || -> . % 76.03/76.20 35166[31:Spt:35165.0,35160.0,35162.0] || m_main_v_state(s1,c_busy)* -> . % 76.03/76.20 35167[31:Spt:35165.0,35160.1] || -> m_main_v_state(s2,c_busy)*. % 76.03/76.20 35172[31:Res:35167.0,61.1] always3(s2) || -> . % 76.03/76.20 35173[31:SSi:35172.0,691.0] || -> . % 76.03/76.20 35174[29:Spt:35173.0,74.0,33599.0] || xuntil6(s0)*+ -> . % 76.03/76.20 35175[29:Spt:35173.0,74.1] || -> node4(s0)*. % 76.03/76.20 35176[29:MRR:758.1,35174.0] || -> m_main_v_state(s1,c_busy)*. % 76.03/76.20 35178[29:Res:35176.0,61.1] always3(s1) || -> . % 76.03/76.20 35179[29:SSi:35178.0,690.0] || -> . % 76.03/76.20 35180[28:Spt:35179.0,33589.0,33593.0] || trans(s49,s23)*+ -> . % 76.03/76.20 35181[28:Spt:35179.0,33589.1,33589.2,33589.3,33589.4,33589.5,33589.6,33589.7,33589.8,33589.9,33589.10,33589.11,33589.12,33589.13,33589.14,33589.15,33589.16,33589.17,33589.18,33589.19,33589.20,33589.21,33589.22,33589.23] || -> trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.03/76.21 35182[28:MRR:33591.0,35180.0] || -> trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.03/76.21 35184[28:MRR:33592.1,35180.0] xuntil6(s49) || -> trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.03/76.21 35185[29:Spt:35181.0] || -> trans(s49,s22)*. % 76.03/76.21 35186[29:Res:35185.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s22)*. % 76.03/76.21 35188[29:Res:35185.0,60.0] || -> node2(s49,s22)*. % 76.03/76.21 35189[29:SSi:35186.1,50.0,738.0] xuntil6(s49) || -> until2p7(s22)*. % 76.03/76.21 35190[29:Res:35188.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)*. % 76.03/76.21 35191[30:Spt:74.0] || -> xuntil6(s0)*. % 76.03/76.21 35192[30:MRR:176.0,35191.0] || -> until5(s1)*. % 76.03/76.21 35193[30:MRR:34051.0,35192.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.03/76.21 35197[31:Spt:35193.2] || -> xuntil6(s1)*. % 76.03/76.21 35198[31:MRR:175.0,35197.0] || -> until5(s2)*. % 76.03/76.21 35199[31:MRR:34050.0,35198.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.03/76.21 35203[32:Spt:35199.2] || -> xuntil6(s2)*. % 76.03/76.21 35204[32:MRR:174.0,35203.0] || -> until5(s3)*. % 76.03/76.21 35205[32:MRR:34043.0,35204.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.03/76.21 35206[33:Spt:35205.2] || -> xuntil6(s3)*. % 76.03/76.21 35207[33:MRR:173.0,35206.0] || -> until5(s4)*. % 76.03/76.21 35208[33:MRR:34039.0,35207.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.03/76.21 35212[34:Spt:35208.2] || -> xuntil6(s4)*. % 76.03/76.21 35213[34:MRR:172.0,35212.0] || -> until5(s5)*. % 76.03/76.21 35214[34:MRR:34035.0,35213.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.03/76.21 35215[35:Spt:35214.2] || -> xuntil6(s5)*. % 76.03/76.21 35216[35:MRR:171.0,35215.0] || -> until5(s6)*. % 76.03/76.21 35217[35:MRR:34031.0,35216.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.03/76.21 35221[36:Spt:35217.2] || -> xuntil6(s6)*. % 76.03/76.21 35222[36:MRR:170.0,35221.0] || -> until5(s7)*. % 76.03/76.21 35223[36:MRR:34030.0,35222.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.03/76.21 35224[37:Spt:35223.2] || -> xuntil6(s7)*. % 76.03/76.21 35225[37:MRR:169.0,35224.0] || -> until5(s8)*. % 76.03/76.21 35226[37:MRR:34023.0,35225.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.03/76.21 35230[38:Spt:35226.2] || -> xuntil6(s8)*. % 76.03/76.21 35231[38:MRR:168.0,35230.0] || -> until5(s9)*. % 76.03/76.21 35232[38:MRR:34019.0,35231.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.03/76.21 35233[39:Spt:35232.2] || -> xuntil6(s9)*. % 76.03/76.21 35234[39:MRR:167.0,35233.0] || -> until5(s10)*. % 76.03/76.21 35235[39:MRR:34015.0,35234.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.03/76.21 35239[40:Spt:35235.2] || -> xuntil6(s10)*. % 76.03/76.21 35240[40:MRR:166.0,35239.0] || -> until5(s11)*. % 76.03/76.21 35241[40:MRR:34011.0,35240.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.03/76.21 35242[41:Spt:35241.2] || -> xuntil6(s11)*. % 76.03/76.21 35243[41:MRR:165.0,35242.0] || -> until5(s12)*. % 76.03/76.21 35244[41:MRR:34010.0,35243.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.03/76.21 35248[42:Spt:35244.2] || -> xuntil6(s12)*. % 76.03/76.21 35249[42:MRR:164.0,35248.0] || -> until5(s13)*. % 76.03/76.21 35250[42:MRR:34003.0,35249.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.03/76.21 35251[43:Spt:35250.2] || -> xuntil6(s13)*. % 76.03/76.21 35252[43:MRR:163.0,35251.0] || -> until5(s14)*. % 76.03/76.21 35253[43:MRR:33999.0,35252.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.03/76.21 35257[44:Spt:35253.2] || -> xuntil6(s14)*. % 76.03/76.21 35258[44:MRR:162.0,35257.0] || -> until5(s15)*. % 76.03/76.21 35259[44:MRR:33995.0,35258.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.03/76.21 35260[45:Spt:35259.2] || -> xuntil6(s15)*. % 76.03/76.21 35261[45:MRR:161.0,35260.0] || -> until5(s16)*. % 76.03/76.21 35262[45:MRR:33991.0,35261.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.03/76.21 35266[46:Spt:35262.2] || -> xuntil6(s16)*. % 76.03/76.21 35267[46:MRR:160.0,35266.0] || -> until5(s17)*. % 76.03/76.21 35268[46:MRR:33990.0,35267.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.03/76.21 35269[47:Spt:35268.2] || -> xuntil6(s17)*. % 76.03/76.21 35270[47:MRR:159.0,35269.0] || -> until5(s18)*. % 76.03/76.21 35271[47:MRR:33983.0,35270.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.03/76.21 35275[48:Spt:35271.2] || -> xuntil6(s18)*. % 76.03/76.21 35276[48:MRR:158.0,35275.0] || -> until5(s19)*. % 76.03/76.21 35277[48:MRR:33979.0,35276.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.03/76.21 35278[49:Spt:35277.2] || -> xuntil6(s19)*. % 76.03/76.21 35279[49:MRR:157.0,35278.0] || -> until5(s20)*. % 76.03/76.21 35280[49:MRR:33975.0,35279.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.03/76.21 35284[50:Spt:35280.2] || -> xuntil6(s20)*. % 76.03/76.21 35285[50:MRR:156.0,35284.0] || -> until5(s21)*. % 76.03/76.21 35286[50:MRR:33971.0,35285.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.03/76.21 35287[51:Spt:35286.2] || -> xuntil6(s21)*. % 76.03/76.21 35288[51:MRR:155.0,35287.0] || -> until5(s22)*. % 76.03/76.21 35289[51:MRR:33970.0,35288.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.03/76.21 35293[52:Spt:35289.2] || -> xuntil6(s22)*. % 76.03/76.21 35294[52:MRR:154.0,35293.0] || -> until5(s23)*. % 76.03/76.21 35295[52:MRR:33963.0,35294.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.03/76.21 35296[53:Spt:35295.2] || -> xuntil6(s23)*. % 76.03/76.21 35297[53:MRR:153.0,35296.0] || -> until5(s24)*. % 76.03/76.21 35298[53:MRR:33959.0,35297.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.03/76.21 35302[54:Spt:35298.2] || -> xuntil6(s24)*. % 76.03/76.21 35303[54:MRR:152.0,35302.0] || -> until5(s25)*. % 76.03/76.21 35304[54:MRR:33955.0,35303.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.03/76.21 35305[55:Spt:35304.2] || -> xuntil6(s25)*. % 76.03/76.21 35306[55:MRR:151.0,35305.0] || -> until5(s26)*. % 76.03/76.21 35307[55:MRR:33954.0,35306.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.03/76.21 35311[56:Spt:35307.2] || -> xuntil6(s26)*. % 76.03/76.21 35312[56:MRR:150.0,35311.0] || -> until5(s27)*. % 76.03/76.21 35313[56:MRR:33953.0,35312.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.03/76.21 35314[57:Spt:35313.2] || -> xuntil6(s27)*. % 76.03/76.21 35315[57:MRR:149.0,35314.0] || -> until5(s28)*. % 76.03/76.21 35316[57:MRR:32361.0,35315.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.03/76.21 35320[58:Spt:35316.1] || -> m_main_v_state(s29,c_busy)*. % 76.03/76.21 35322[58:Res:35320.0,61.1] always3(s29) || -> . % 76.03/76.21 35323[58:SSi:35322.0,718.0] || -> . % 76.03/76.21 35324[58:Spt:35323.0,35316.1,35320.0] || m_main_v_state(s29,c_busy)*+ -> . % 76.03/76.21 35325[58:Spt:35323.0,35316.0,35316.2] || m_main_v_state(s28,c_ready)*+ -> xuntil6(s28). % 76.03/76.21 35327[58:MRR:834.2,35324.0] node4(s28) || m_main_v_state(s28,c_ready)* -> . % 76.03/76.21 35328[58:Res:53.1,35325.0] || -> m_main_v_state(s28,c_busy)* xuntil6(s28). % 76.03/76.21 35330[59:Spt:35328.1] || -> xuntil6(s28)*. % 76.03/76.21 35331[59:MRR:148.0,35330.0] || -> until5(s29)*. % 76.03/76.21 35332[59:MRR:34055.0,35331.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.03/76.21 35337[60:Spt:35332.2] || -> xuntil6(s29)*. % 76.03/76.21 35338[60:MRR:147.0,35337.0] || -> until5(s30)*. % 76.03/76.21 35339[60:MRR:32470.0,35338.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.03/76.21 35340[61:Spt:35339.1] || -> m_main_v_state(s31,c_busy)*. % 76.03/76.21 35342[61:Res:35340.0,61.1] always3(s31) || -> . % 76.03/76.21 35343[61:SSi:35342.0,720.0] || -> . % 76.03/76.21 35344[61:Spt:35343.0,35339.1,35340.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.03/76.21 35345[61:Spt:35343.0,35339.0,35339.2] || m_main_v_state(s30,c_ready)*+ -> xuntil6(s30). % 76.03/76.21 35347[61:MRR:828.2,35344.0] node4(s30) || m_main_v_state(s30,c_ready)* -> . % 76.03/76.21 35348[61:Res:53.1,35345.0] || -> m_main_v_state(s30,c_busy)* xuntil6(s30). % 76.03/76.21 35350[62:Spt:35348.1] || -> xuntil6(s30)*. % 76.03/76.21 35351[62:MRR:146.0,35350.0] || -> until5(s31)*. % 76.03/76.21 35352[62:MRR:34059.0,35351.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.03/76.21 35360[63:Spt:35352.2] || -> xuntil6(s31)*. % 76.03/76.21 35361[63:MRR:145.0,35360.0] || -> until5(s32)*. % 76.03/76.21 35362[63:MRR:32474.0,35361.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.03/76.21 35363[64:Spt:35362.1] || -> m_main_v_state(s33,c_busy)*. % 76.03/76.21 35365[64:Res:35363.0,61.1] always3(s33) || -> . % 76.03/76.21 35366[64:SSi:35365.0,722.0] || -> . % 76.03/76.21 35367[64:Spt:35366.0,35362.1,35363.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.03/76.21 35368[64:Spt:35366.0,35362.0,35362.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 76.03/76.21 35370[64:MRR:822.2,35367.0] node4(s32) || m_main_v_state(s32,c_ready)* -> . % 76.03/76.21 35371[64:Res:53.1,35368.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 76.03/76.21 35376[65:Spt:35371.1] || -> xuntil6(s32)*. % 76.03/76.21 35377[65:MRR:144.0,35376.0] || -> until5(s33)*. % 76.03/76.21 35378[65:MRR:34063.0,35377.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.03/76.21 35380[66:Spt:35378.2] || -> xuntil6(s33)*. % 76.03/76.21 35381[66:MRR:143.0,35380.0] || -> until5(s34)*. % 76.03/76.21 35382[66:MRR:32478.0,35381.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.03/76.21 35383[67:Spt:35382.1] || -> m_main_v_state(s35,c_busy)*. % 76.03/76.21 35385[67:Res:35383.0,61.1] always3(s35) || -> . % 76.03/76.21 35386[67:SSi:35385.0,724.0] || -> . % 76.03/76.21 35387[67:Spt:35386.0,35382.1,35383.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.03/76.21 35388[67:Spt:35386.0,35382.0,35382.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 76.03/76.21 35390[67:MRR:816.2,35387.0] node4(s34) || m_main_v_state(s34,c_ready)* -> . % 76.03/76.21 35391[67:Res:53.1,35388.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 76.03/76.21 35393[68:Spt:35391.1] || -> xuntil6(s34)*. % 76.03/76.21 35394[68:MRR:142.0,35393.0] || -> until5(s35)*. % 76.03/76.21 35395[68:MRR:34070.0,35394.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.03/76.21 35400[69:Spt:35395.2] || -> xuntil6(s35)*. % 76.03/76.21 35401[69:MRR:141.0,35400.0] || -> until5(s36)*. % 76.03/76.21 35402[69:MRR:32485.0,35401.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.03/76.21 35403[70:Spt:35402.1] || -> m_main_v_state(s37,c_busy)*. % 76.03/76.21 35405[70:Res:35403.0,61.1] always3(s37) || -> . % 76.03/76.21 35406[70:SSi:35405.0,726.0] || -> . % 76.03/76.21 35407[70:Spt:35406.0,35402.1,35403.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.03/76.21 35408[70:Spt:35406.0,35402.0,35402.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 76.03/76.21 35410[70:MRR:810.2,35407.0] node4(s36) || m_main_v_state(s36,c_ready)* -> . % 76.03/76.21 35411[70:Res:53.1,35408.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 76.03/76.21 35413[71:Spt:35411.1] || -> xuntil6(s36)*. % 76.03/76.21 35414[71:MRR:140.0,35413.0] || -> until5(s37)*. % 76.03/76.21 35415[71:MRR:34071.0,35414.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.03/76.21 35423[72:Spt:35415.2] || -> xuntil6(s37)*. % 76.03/76.21 35424[72:MRR:139.0,35423.0] || -> until5(s38)*. % 76.03/76.21 35425[72:MRR:32486.0,35424.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.03/76.21 35426[73:Spt:35425.1] || -> m_main_v_state(s39,c_busy)*. % 76.03/76.21 35428[73:Res:35426.0,61.1] always3(s39) || -> . % 76.03/76.21 35429[73:SSi:35428.0,728.0] || -> . % 76.03/76.21 35430[73:Spt:35429.0,35425.1,35426.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.03/76.21 35431[73:Spt:35429.0,35425.0,35425.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 76.03/76.21 35433[73:MRR:804.2,35430.0] node4(s38) || m_main_v_state(s38,c_ready)* -> . % 76.03/76.21 35434[73:Res:53.1,35431.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 76.03/76.21 35439[74:Spt:35434.1] || -> xuntil6(s38)*. % 76.03/76.21 35440[74:MRR:138.0,35439.0] || -> until5(s39)*. % 76.03/76.21 35441[74:MRR:34075.0,35440.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.03/76.21 35443[75:Spt:35441.2] || -> xuntil6(s39)*. % 76.03/76.21 35444[75:MRR:137.0,35443.0] || -> until5(s40)*. % 76.03/76.21 35445[75:MRR:32490.0,35444.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.03/76.21 35446[76:Spt:35445.1] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.21 35448[76:Res:35446.0,61.1] always3(s41) || -> . % 76.03/76.21 35449[76:SSi:35448.0,730.0] || -> . % 76.03/76.21 35450[76:Spt:35449.0,35445.1,35446.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.03/76.21 35451[76:Spt:35449.0,35445.0,35445.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 76.03/76.21 35453[76:MRR:798.2,35450.0] node4(s40) || m_main_v_state(s40,c_ready)* -> . % 76.03/76.21 35454[76:Res:53.1,35451.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 76.03/76.21 35456[77:Spt:35454.1] || -> xuntil6(s40)*. % 76.03/76.21 35457[77:MRR:136.0,35456.0] || -> until5(s41)*. % 76.03/76.21 35458[77:MRR:34079.0,35457.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.03/76.21 35463[78:Spt:35458.2] || -> xuntil6(s41)*. % 76.03/76.21 35464[78:MRR:135.0,35463.0] || -> until5(s42)*. % 76.03/76.21 35465[78:MRR:32494.0,35464.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.03/76.21 35466[79:Spt:35465.1] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.21 35468[79:Res:35466.0,61.1] always3(s43) || -> . % 76.03/76.21 35469[79:SSi:35468.0,732.0] || -> . % 76.03/76.21 35470[79:Spt:35469.0,35465.1,35466.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.03/76.21 35471[79:Spt:35469.0,35465.0,35465.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 76.03/76.21 35473[79:MRR:792.2,35470.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 76.03/76.21 35474[79:Res:53.1,35471.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 76.03/76.21 35476[80:Spt:35474.1] || -> xuntil6(s42)*. % 76.03/76.21 35477[80:MRR:134.0,35476.0] || -> until5(s43)*. % 76.03/76.21 35478[80:MRR:34083.0,35477.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.03/76.21 35486[81:Spt:35478.2] || -> xuntil6(s43)*. % 76.03/76.21 35487[81:MRR:133.0,35486.0] || -> until5(s44)*. % 76.03/76.21 35488[81:MRR:32498.0,35487.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.03/76.21 35489[82:Spt:35488.1] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.21 35491[82:Res:35489.0,61.1] always3(s45) || -> . % 76.03/76.21 35492[82:SSi:35491.0,734.0] || -> . % 76.03/76.21 35493[82:Spt:35492.0,35488.1,35489.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.03/76.21 35494[82:Spt:35492.0,35488.0,35488.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 76.03/76.21 35496[82:MRR:786.2,35493.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 76.03/76.21 35497[82:Res:53.1,35494.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 76.03/76.21 35502[83:Spt:35497.1] || -> xuntil6(s44)*. % 76.03/76.21 35503[83:MRR:132.0,35502.0] || -> until5(s45)*. % 76.03/76.21 35504[83:MRR:34090.0,35503.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.03/76.21 35506[84:Spt:35504.2] || -> xuntil6(s45)*. % 76.03/76.21 35507[84:MRR:131.0,35506.0] || -> until5(s46)*. % 76.03/76.21 35508[84:MRR:32505.0,35507.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.03/76.21 35509[85:Spt:35508.1] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.21 35511[85:Res:35509.0,61.1] always3(s47) || -> . % 76.03/76.21 35512[85:SSi:35511.0,736.0] || -> . % 76.03/76.21 35513[85:Spt:35512.0,35508.1,35509.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.03/76.21 35514[85:Spt:35512.0,35508.0,35508.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 76.03/76.21 35516[85:MRR:780.2,35513.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 76.03/76.21 35517[85:Res:53.1,35514.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 76.03/76.21 35519[86:Spt:35517.1] || -> xuntil6(s46)*. % 76.03/76.21 35520[86:MRR:130.0,35519.0] || -> until5(s47)*. % 76.03/76.21 35521[86:MRR:34091.0,35520.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.03/76.21 35526[87:Spt:35521.2] || -> xuntil6(s47)*. % 76.03/76.21 35527[87:MRR:129.0,35526.0] || -> until5(s48)*. % 76.03/76.21 35528[87:MRR:32506.0,35527.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.03/76.21 35529[88:Spt:35528.1] || -> m_main_v_state(s49,c_busy)*. % 76.03/76.21 35531[88:Res:35529.0,61.1] always3(s49) || -> . % 76.03/76.21 35532[88:SSi:35531.0,50.0,738.0] || -> . % 76.03/76.21 35533[88:Spt:35532.0,35528.1,35529.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.03/76.21 35534[88:Spt:35532.0,35528.0,35528.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 76.03/76.21 35536[88:MRR:774.2,35533.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.03/76.21 35537[88:Res:53.1,35534.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 76.03/76.21 35539[89:Spt:35537.1] || -> xuntil6(s48)*. % 76.03/76.21 35540[89:MRR:128.0,35539.0] || -> until5(s49)*. % 76.03/76.21 35548[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.03/76.21 35549[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.03/76.21 35550[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.03/76.21 35551[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.03/76.21 35555[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.03/76.21 35559[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.03/76.21 35566[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.03/76.21 35567[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.03/76.21 35571[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.03/76.21 35575[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.03/76.21 35579[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.03/76.21 35586[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.03/76.21 35587[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.03/76.21 35591[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.03/76.21 35595[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.03/76.21 35599[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.03/76.21 35606[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.03/76.21 35607[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.03/76.21 35611[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.03/76.21 35615[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.03/76.21 35619[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.03/76.21 35626[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.03/76.21 35627[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.03/76.21 35631[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.03/76.21 35635[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.03/76.21 35639[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.03/76.21 35646[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.03/76.21 35647[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.03/76.21 35651[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.03/76.21 35655[0:SoR:819.0,66.2] until5(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.03/76.21 35659[0:SoR:813.0,66.2] until5(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.03/76.21 35666[0:SoR:807.0,66.2] until5(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.03/76.21 35667[0:SoR:801.0,66.2] until5(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.03/76.21 35671[0:SoR:795.0,66.2] until5(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.03/76.21 35675[0:SoR:789.0,66.2] until5(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.03/76.21 35679[0:SoR:783.0,66.2] until5(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.03/76.21 35683[0:SoR:777.0,66.2] until5(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.03/76.21 35685[29:SoR:35190.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)*. % 76.03/76.21 35687[29:SoR:35685.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)* xuntil6(s49). % 76.03/76.21 35688[89:SSi:35687.0,50.0,738.0,35540.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s22,c_busy)* xuntil6(s49). % 76.03/76.21 35689[90:Spt:35688.1] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.21 35691[90:Res:35689.0,61.1] always3(s22) || -> . % 76.03/76.21 35692[90:SSi:35691.0,711.0,35288.0,35293.0] || -> . % 76.03/76.21 35693[90:Spt:35692.0,35688.1,35689.0] || m_main_v_state(s22,c_busy)*+ -> . % 76.03/76.21 35694[90:Spt:35692.0,35688.0,35688.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.03/76.21 35698[90:MRR:35685.2,35693.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.03/76.21 35699[90:Res:53.1,35694.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.03/76.21 35701[90:MRR:35699.0,35533.0] || -> xuntil6(s49)*. % 76.03/76.21 35702[90:MRR:35189.0,35701.0] || -> until2p7(s22)*. % 76.03/76.21 35703[90:MRR:218.0,35702.0] || -> until2p7(s23)* node4(s22). % 76.03/76.21 35704[91:Spt:35703.0] || -> until2p7(s23)*. % 76.03/76.21 35705[91:MRR:219.0,35704.0] || -> until2p7(s24)* node4(s23). % 76.03/76.21 35706[92:Spt:35705.0] || -> until2p7(s24)*. % 76.03/76.21 35707[92:MRR:220.0,35706.0] || -> until2p7(s25)* node4(s24). % 76.03/76.21 35708[93:Spt:35707.0] || -> until2p7(s25)*. % 76.03/76.21 35709[93:MRR:221.0,35708.0] || -> until2p7(s26)* node4(s25). % 76.03/76.21 35710[94:Spt:35709.0] || -> until2p7(s26)*. % 76.03/76.21 35711[94:MRR:222.0,35710.0] || -> until2p7(s27)* node4(s26). % 76.03/76.21 35712[95:Spt:35711.0] || -> until2p7(s27)*. % 76.03/76.21 35713[95:MRR:223.0,35712.0] || -> until2p7(s28)* node4(s27). % 76.03/76.21 35714[96:Spt:35713.0] || -> until2p7(s28)*. % 76.03/76.21 35715[96:MRR:224.0,35714.0] || -> until2p7(s29)* node4(s28). % 76.03/76.21 35716[97:Spt:35715.0] || -> until2p7(s29)*. % 76.03/76.21 35717[97:MRR:225.0,35716.0] || -> until2p7(s30)* node4(s29). % 76.03/76.21 35718[98:Spt:35717.0] || -> until2p7(s30)*. % 76.03/76.21 35719[98:MRR:226.0,35718.0] || -> until2p7(s31)* node4(s30). % 76.03/76.21 35720[99:Spt:35719.0] || -> until2p7(s31)*. % 76.03/76.21 35721[99:MRR:227.0,35720.0] || -> until2p7(s32)* node4(s31). % 76.03/76.21 35722[100:Spt:35721.0] || -> until2p7(s32)*. % 76.03/76.21 35723[100:MRR:228.0,35722.0] || -> until2p7(s33)* node4(s32). % 76.03/76.21 35724[101:Spt:35723.0] || -> until2p7(s33)*. % 76.03/76.21 35725[101:MRR:229.0,35724.0] || -> until2p7(s34)* node4(s33). % 76.03/76.21 35726[102:Spt:35725.0] || -> until2p7(s34)*. % 76.03/76.21 35727[102:MRR:230.0,35726.0] || -> until2p7(s35)* node4(s34). % 76.03/76.21 35728[103:Spt:35727.0] || -> until2p7(s35)*. % 76.03/76.21 35729[103:MRR:231.0,35728.0] || -> until2p7(s36)* node4(s35). % 76.03/76.21 35730[104:Spt:35729.0] || -> until2p7(s36)*. % 76.03/76.21 35731[104:MRR:232.0,35730.0] || -> until2p7(s37)* node4(s36). % 76.03/76.21 35732[105:Spt:35731.0] || -> until2p7(s37)*. % 76.03/76.21 35733[105:MRR:235.0,35732.0] || -> until2p7(s38)* node4(s37). % 76.03/76.21 35734[106:Spt:35733.0] || -> until2p7(s38)*. % 76.03/76.21 35735[106:MRR:236.0,35734.0] || -> until2p7(s39)* node4(s38). % 76.03/76.21 35736[107:Spt:35735.0] || -> until2p7(s39)*. % 76.03/76.21 35737[107:MRR:237.0,35736.0] || -> until2p7(s40)* node4(s39). % 76.03/76.21 35738[108:Spt:35737.0] || -> until2p7(s40)*. % 76.03/76.21 35739[108:MRR:238.0,35738.0] || -> until2p7(s41)* node4(s40). % 76.03/76.21 35740[109:Spt:35739.0] || -> until2p7(s41)*. % 76.03/76.21 35741[109:MRR:239.0,35740.0] || -> until2p7(s42)* node4(s41). % 76.03/76.21 35742[110:Spt:35741.0] || -> until2p7(s42)*. % 76.03/76.21 35743[110:MRR:240.0,35742.0] || -> until2p7(s43)* node4(s42). % 76.03/76.21 35744[111:Spt:35743.0] || -> until2p7(s43)*. % 76.03/76.21 35745[111:MRR:241.0,35744.0] || -> until2p7(s44)* node4(s43). % 76.03/76.21 35746[112:Spt:35745.0] || -> until2p7(s44)*. % 76.03/76.21 35747[112:MRR:539.0,35746.0] || -> until2p7(s45)* node4(s44). % 76.03/76.21 35748[113:Spt:35747.0] || -> until2p7(s45)*. % 76.03/76.21 35749[113:MRR:544.0,35748.0] || -> until2p7(s46)* node4(s45). % 76.03/76.21 35750[114:Spt:35749.0] || -> until2p7(s46)*. % 76.03/76.21 35751[114:MRR:549.0,35750.0] || -> until2p7(s47)* node4(s46). % 76.03/76.21 35752[115:Spt:35751.0] || -> until2p7(s47)*. % 76.03/76.21 35753[115:MRR:554.0,35752.0] || -> until2p7(s48)* node4(s47). % 76.03/76.21 35754[116:Spt:35753.0] || -> until2p7(s48)*. % 76.03/76.21 35755[116:MRR:559.0,35754.0] || -> until2p7(s49)* node4(s48). % 76.03/76.21 35756[117:Spt:35755.0] || -> until2p7(s49)*. % 76.03/76.21 35757[117:MRR:194.0,35756.0] || -> node4(s49)*. % 76.03/76.21 35758[117:MRR:35698.0,35757.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.03/76.21 35762[117:Res:53.1,35758.0] || -> m_main_v_state(s49,c_busy)*. % 76.03/76.21 35764[117:MRR:35762.0,35533.0] || -> . % 76.03/76.21 35765[117:Spt:35764.0,35755.0,35756.0] || until2p7(s49)*+ -> . % 76.03/76.21 35766[117:Spt:35764.0,35755.1] || -> node4(s48)*. % 76.03/76.21 35767[117:MRR:35536.0,35766.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.03/76.21 35770[117:Res:53.1,35767.0] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.21 35773[117:Res:35770.0,61.1] always3(s48) || -> . % 76.03/76.21 35774[117:SSi:35773.0,737.0,35527.0,35539.0,35754.0,35766.0] || -> . % 76.03/76.21 35775[116:Spt:35774.0,35753.0,35754.0] || until2p7(s48)*+ -> . % 76.03/76.21 35776[116:Spt:35774.0,35753.1] || -> node4(s47)*. % 76.03/76.21 35778[116:MRR:777.0,35776.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.03/76.21 35790[116:Res:53.1,35778.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.03/76.21 35792[116:MRR:35790.0,35513.0] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.21 35794[116:Res:35792.0,61.1] always3(s48) || -> . % 76.03/76.21 35795[116:SSi:35794.0,737.0,35527.0,35539.0] || -> . % 76.03/76.21 35796[115:Spt:35795.0,35751.0,35752.0] || until2p7(s47)*+ -> . % 76.03/76.21 35797[115:Spt:35795.0,35751.1] || -> node4(s46)*. % 76.03/76.21 35798[115:MRR:35516.0,35797.0] || m_main_v_state(s46,c_ready)*+ -> . % 76.03/76.21 35802[115:Res:53.1,35798.0] || -> m_main_v_state(s46,c_busy)*. % 76.03/76.21 35805[115:Res:35802.0,61.1] always3(s46) || -> . % 76.03/76.21 35806[115:SSi:35805.0,735.0,35507.0,35519.0,35750.0,35797.0] || -> . % 76.03/76.21 35807[114:Spt:35806.0,35749.0,35750.0] || until2p7(s46)*+ -> . % 76.03/76.21 35808[114:Spt:35806.0,35749.1] || -> node4(s45)*. % 76.03/76.21 35810[114:MRR:783.0,35808.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.03/76.21 35821[114:Res:53.1,35810.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.03/76.21 35823[114:MRR:35821.0,35493.0] || -> m_main_v_state(s46,c_busy)*. % 76.03/76.21 35825[114:Res:35823.0,61.1] always3(s46) || -> . % 76.03/76.21 35826[114:SSi:35825.0,735.0,35507.0,35519.0] || -> . % 76.03/76.21 35827[113:Spt:35826.0,35747.0,35748.0] || until2p7(s45)*+ -> . % 76.03/76.21 35828[113:Spt:35826.0,35747.1] || -> node4(s44)*. % 76.03/76.21 35829[113:MRR:35496.0,35828.0] || m_main_v_state(s44,c_ready)*+ -> . % 76.03/76.21 35832[113:Res:53.1,35829.0] || -> m_main_v_state(s44,c_busy)*. % 76.03/76.21 35835[113:Res:35832.0,61.1] always3(s44) || -> . % 76.03/76.21 35836[113:SSi:35835.0,733.0,35487.0,35502.0,35746.0,35828.0] || -> . % 76.03/76.21 35837[112:Spt:35836.0,35745.0,35746.0] || until2p7(s44)*+ -> . % 76.03/76.21 35838[112:Spt:35836.0,35745.1] || -> node4(s43)*. % 76.03/76.21 35840[112:MRR:789.0,35838.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.03/76.21 35852[112:Res:53.1,35840.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.03/76.21 35854[112:MRR:35852.0,35470.0] || -> m_main_v_state(s44,c_busy)*. % 76.03/76.21 35856[112:Res:35854.0,61.1] always3(s44) || -> . % 76.03/76.21 35857[112:SSi:35856.0,733.0,35487.0,35502.0] || -> . % 76.03/76.21 35858[111:Spt:35857.0,35743.0,35744.0] || until2p7(s43)*+ -> . % 76.03/76.21 35859[111:Spt:35857.0,35743.1] || -> node4(s42)*. % 76.03/76.21 35860[111:MRR:35473.0,35859.0] || m_main_v_state(s42,c_ready)*+ -> . % 76.03/76.21 35863[111:Res:53.1,35860.0] || -> m_main_v_state(s42,c_busy)*. % 76.03/76.21 35866[111:Res:35863.0,61.1] always3(s42) || -> . % 76.03/76.21 35867[111:SSi:35866.0,731.0,35464.0,35476.0,35742.0,35859.0] || -> . % 76.03/76.21 35868[110:Spt:35867.0,35741.0,35742.0] || until2p7(s42)*+ -> . % 76.03/76.21 35869[110:Spt:35867.0,35741.1] || -> node4(s41)*. % 76.03/76.21 35871[110:MRR:795.0,35869.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.03/76.21 35883[110:Res:53.1,35871.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.03/76.21 35885[110:MRR:35883.0,35450.0] || -> m_main_v_state(s42,c_busy)*. % 76.03/76.21 35890[110:Res:35885.0,61.1] always3(s42) || -> . % 76.03/76.21 35891[110:SSi:35890.0,731.0,35464.0,35476.0] || -> . % 76.03/76.21 35892[109:Spt:35891.0,35739.0,35740.0] || until2p7(s41)*+ -> . % 76.03/76.21 35893[109:Spt:35891.0,35739.1] || -> node4(s40)*. % 76.03/76.21 35894[109:MRR:35453.0,35893.0] || m_main_v_state(s40,c_ready)*+ -> . % 76.03/76.21 35897[109:Res:53.1,35894.0] || -> m_main_v_state(s40,c_busy)*. % 76.03/76.21 35901[109:Res:35897.0,61.1] always3(s40) || -> . % 76.03/76.21 35902[109:SSi:35901.0,729.0,35444.0,35456.0,35738.0,35893.0] || -> . % 76.03/76.21 35903[108:Spt:35902.0,35737.0,35738.0] || until2p7(s40)*+ -> . % 76.03/76.21 35904[108:Spt:35902.0,35737.1] || -> node4(s39)*. % 76.03/76.21 35906[108:MRR:801.0,35904.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.03/76.21 35917[108:Res:53.1,35906.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.03/76.21 35919[108:MRR:35917.0,35430.0] || -> m_main_v_state(s40,c_busy)*. % 76.03/76.21 35921[108:Res:35919.0,61.1] always3(s40) || -> . % 76.03/76.21 35922[108:SSi:35921.0,729.0,35444.0,35456.0] || -> . % 76.03/76.21 35923[107:Spt:35922.0,35735.0,35736.0] || until2p7(s39)*+ -> . % 76.03/76.21 35924[107:Spt:35922.0,35735.1] || -> node4(s38)*. % 76.03/76.21 35925[107:MRR:35433.0,35924.0] || m_main_v_state(s38,c_ready)*+ -> . % 76.03/76.21 35929[107:Res:53.1,35925.0] || -> m_main_v_state(s38,c_busy)*. % 76.03/76.21 35932[107:Res:35929.0,61.1] always3(s38) || -> . % 76.03/76.21 35933[107:SSi:35932.0,727.0,35424.0,35439.0,35734.0,35924.0] || -> . % 76.03/76.21 35934[106:Spt:35933.0,35733.0,35734.0] || until2p7(s38)*+ -> . % 76.03/76.21 35935[106:Spt:35933.0,35733.1] || -> node4(s37)*. % 76.03/76.21 35937[106:MRR:807.0,35935.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.03/76.21 35948[106:Res:53.1,35937.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.03/76.21 35950[106:MRR:35948.0,35407.0] || -> m_main_v_state(s38,c_busy)*. % 76.03/76.21 35952[106:Res:35950.0,61.1] always3(s38) || -> . % 76.03/76.21 35953[106:SSi:35952.0,727.0,35424.0,35439.0] || -> . % 76.03/76.21 35954[105:Spt:35953.0,35731.0,35732.0] || until2p7(s37)*+ -> . % 76.03/76.21 35955[105:Spt:35953.0,35731.1] || -> node4(s36)*. % 76.03/76.21 35956[105:MRR:35410.0,35955.0] || m_main_v_state(s36,c_ready)*+ -> . % 76.03/76.21 35959[105:Res:53.1,35956.0] || -> m_main_v_state(s36,c_busy)*. % 76.03/76.21 35962[105:Res:35959.0,61.1] always3(s36) || -> . % 76.03/76.21 35963[105:SSi:35962.0,725.0,35401.0,35413.0,35730.0,35955.0] || -> . % 76.03/76.21 35964[104:Spt:35963.0,35729.0,35730.0] || until2p7(s36)*+ -> . % 76.03/76.21 35965[104:Spt:35963.0,35729.1] || -> node4(s35)*. % 76.03/76.21 35967[104:MRR:813.0,35965.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.03/76.21 35979[104:Res:53.1,35967.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.03/76.21 35981[104:MRR:35979.0,35387.0] || -> m_main_v_state(s36,c_busy)*. % 76.03/76.21 35983[104:Res:35981.0,61.1] always3(s36) || -> . % 76.03/76.21 35984[104:SSi:35983.0,725.0,35401.0,35413.0] || -> . % 76.03/76.21 35985[103:Spt:35984.0,35727.0,35728.0] || until2p7(s35)*+ -> . % 76.03/76.21 35986[103:Spt:35984.0,35727.1] || -> node4(s34)*. % 76.03/76.21 35987[103:MRR:35390.0,35986.0] || m_main_v_state(s34,c_ready)*+ -> . % 76.03/76.21 35990[103:Res:53.1,35987.0] || -> m_main_v_state(s34,c_busy)*. % 76.03/76.21 35993[103:Res:35990.0,61.1] always3(s34) || -> . % 76.03/76.21 35994[103:SSi:35993.0,723.0,35381.0,35393.0,35726.0,35986.0] || -> . % 76.03/76.21 35995[102:Spt:35994.0,35725.0,35726.0] || until2p7(s34)*+ -> . % 76.03/76.21 35996[102:Spt:35994.0,35725.1] || -> node4(s33)*. % 76.03/76.21 35998[102:MRR:819.0,35996.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.03/76.21 36010[102:Res:53.1,35998.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.03/76.21 36012[102:MRR:36010.0,35367.0] || -> m_main_v_state(s34,c_busy)*. % 76.03/76.21 36017[102:Res:36012.0,61.1] always3(s34) || -> . % 76.03/76.21 36018[102:SSi:36017.0,723.0,35381.0,35393.0] || -> . % 76.03/76.21 36019[101:Spt:36018.0,35723.0,35724.0] || until2p7(s33)*+ -> . % 76.03/76.21 36020[101:Spt:36018.0,35723.1] || -> node4(s32)*. % 76.03/76.21 36021[101:MRR:35370.0,36020.0] || m_main_v_state(s32,c_ready)*+ -> . % 76.03/76.21 36024[101:Res:53.1,36021.0] || -> m_main_v_state(s32,c_busy)*. % 76.03/76.21 36028[101:Res:36024.0,61.1] always3(s32) || -> . % 76.03/76.21 36029[101:SSi:36028.0,721.0,35361.0,35376.0,35722.0,36020.0] || -> . % 76.03/76.21 36030[100:Spt:36029.0,35721.0,35722.0] || until2p7(s32)*+ -> . % 76.03/76.21 36031[100:Spt:36029.0,35721.1] || -> node4(s31)*. % 76.03/76.21 36033[100:MRR:825.0,36031.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.03/76.21 36044[100:Res:53.1,36033.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.03/76.21 36046[100:MRR:36044.0,35344.0] || -> m_main_v_state(s32,c_busy)*. % 76.03/76.21 36048[100:Res:36046.0,61.1] always3(s32) || -> . % 76.03/76.21 36049[100:SSi:36048.0,721.0,35361.0,35376.0] || -> . % 76.03/76.21 36050[99:Spt:36049.0,35719.0,35720.0] || until2p7(s31)*+ -> . % 76.03/76.21 36051[99:Spt:36049.0,35719.1] || -> node4(s30)*. % 76.03/76.21 36052[99:MRR:35347.0,36051.0] || m_main_v_state(s30,c_ready)*+ -> . % 76.03/76.21 36056[99:Res:53.1,36052.0] || -> m_main_v_state(s30,c_busy)*. % 76.03/76.21 36059[99:Res:36056.0,61.1] always3(s30) || -> . % 76.03/76.21 36060[99:SSi:36059.0,719.0,35338.0,35350.0,35718.0,36051.0] || -> . % 76.03/76.21 36061[98:Spt:36060.0,35717.0,35718.0] || until2p7(s30)*+ -> . % 76.03/76.21 36062[98:Spt:36060.0,35717.1] || -> node4(s29)*. % 76.03/76.21 36064[98:MRR:831.0,36062.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.03/76.21 36075[98:Res:53.1,36064.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.03/76.21 36077[98:MRR:36075.0,35324.0] || -> m_main_v_state(s30,c_busy)*. % 76.03/76.21 36079[98:Res:36077.0,61.1] always3(s30) || -> . % 76.03/76.21 36080[98:SSi:36079.0,719.0,35338.0,35350.0] || -> . % 76.03/76.21 36081[97:Spt:36080.0,35715.0,35716.0] || until2p7(s29)*+ -> . % 76.03/76.21 36082[97:Spt:36080.0,35715.1] || -> node4(s28)*. % 76.03/76.21 36083[97:MRR:35327.0,36082.0] || m_main_v_state(s28,c_ready)*+ -> . % 76.03/76.21 36086[97:Res:53.1,36083.0] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.21 36089[97:Res:36086.0,61.1] always3(s28) || -> . % 76.03/76.21 36090[97:SSi:36089.0,717.0,35315.0,35330.0,35714.0,36082.0] || -> . % 76.03/76.21 36091[96:Spt:36090.0,35713.0,35714.0] || until2p7(s28)*+ -> . % 76.03/76.21 36092[96:Spt:36090.0,35713.1] || -> node4(s27)*. % 76.03/76.21 36094[96:MRR:837.0,36092.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.03/76.21 36106[96:Res:53.1,36094.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.03/76.21 36108[97:Spt:36106.0] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.21 36110[97:Res:36108.0,61.1] always3(s27) || -> . % 76.03/76.21 36111[97:SSi:36110.0,716.0,35312.0,35314.0,35712.0,36092.0] || -> . % 76.03/76.21 36112[97:Spt:36111.0,36106.0,36108.0] || m_main_v_state(s27,c_busy)* -> . % 76.03/76.21 36113[97:Spt:36111.0,36106.1] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.21 36117[97:Res:36113.0,61.1] always3(s28) || -> . % 76.03/76.21 36118[97:SSi:36117.0,717.0,35315.0,35330.0] || -> . % 76.03/76.21 36119[95:Spt:36118.0,35711.0,35712.0] || until2p7(s27)*+ -> . % 76.03/76.21 36120[95:Spt:36118.0,35711.1] || -> node4(s26)*. % 76.03/76.21 36122[95:MRR:840.0,36120.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.03/76.21 36129[95:Res:53.1,36122.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.03/76.21 36131[96:Spt:36129.0] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.21 36133[96:Res:36131.0,61.1] always3(s26) || -> . % 76.03/76.21 36134[96:SSi:36133.0,715.0,35306.0,35311.0,35710.0,36120.0] || -> . % 76.03/76.21 36135[96:Spt:36134.0,36129.0,36131.0] || m_main_v_state(s26,c_busy)* -> . % 76.03/76.21 36136[96:Spt:36134.0,36129.1] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.21 36140[96:Res:36136.0,61.1] always3(s27) || -> . % 76.03/76.21 36141[96:SSi:36140.0,716.0,35312.0,35314.0] || -> . % 76.03/76.21 36142[94:Spt:36141.0,35709.0,35710.0] || until2p7(s26)*+ -> . % 76.03/76.21 36143[94:Spt:36141.0,35709.1] || -> node4(s25)*. % 76.03/76.21 36145[94:MRR:843.0,36143.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.03/76.21 36148[94:Res:53.1,36145.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.03/76.21 36150[95:Spt:36148.0] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.21 36152[95:Res:36150.0,61.1] always3(s25) || -> . % 76.03/76.21 36153[95:SSi:36152.0,714.0,35303.0,35305.0,35708.0,36143.0] || -> . % 76.03/76.21 36154[95:Spt:36153.0,36148.0,36150.0] || m_main_v_state(s25,c_busy)* -> . % 76.03/76.21 36155[95:Spt:36153.0,36148.1] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.21 36159[95:Res:36155.0,61.1] always3(s26) || -> . % 76.03/76.21 36160[95:SSi:36159.0,715.0,35306.0,35311.0] || -> . % 76.03/76.21 36161[93:Spt:36160.0,35707.0,35708.0] || until2p7(s25)*+ -> . % 76.03/76.21 36162[93:Spt:36160.0,35707.1] || -> node4(s24)*. % 76.03/76.21 36164[93:MRR:846.0,36162.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.03/76.21 36167[93:Res:53.1,36164.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.03/76.21 36169[94:Spt:36167.0] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.21 36171[94:Res:36169.0,61.1] always3(s24) || -> . % 76.03/76.21 36172[94:SSi:36171.0,713.0,35297.0,35302.0,35706.0,36162.0] || -> . % 76.03/76.21 36173[94:Spt:36172.0,36167.0,36169.0] || m_main_v_state(s24,c_busy)* -> . % 76.03/76.21 36174[94:Spt:36172.0,36167.1] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.21 36178[94:Res:36174.0,61.1] always3(s25) || -> . % 76.03/76.21 36179[94:SSi:36178.0,714.0,35303.0,35305.0] || -> . % 76.03/76.21 36180[92:Spt:36179.0,35705.0,35706.0] || until2p7(s24)*+ -> . % 76.03/76.21 36181[92:Spt:36179.0,35705.1] || -> node4(s23)*. % 76.03/76.21 36183[92:MRR:849.0,36181.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.03/76.21 36186[92:Res:53.1,36183.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.03/76.21 36191[93:Spt:36186.0] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.21 36193[93:Res:36191.0,61.1] always3(s23) || -> . % 76.03/76.21 36194[93:SSi:36193.0,712.0,35294.0,35296.0,35704.0,36181.0] || -> . % 76.03/76.21 36195[93:Spt:36194.0,36186.0,36191.0] || m_main_v_state(s23,c_busy)* -> . % 76.03/76.21 36196[93:Spt:36194.0,36186.1] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.21 36200[93:Res:36196.0,61.1] always3(s24) || -> . % 76.03/76.21 36201[93:SSi:36200.0,713.0,35297.0,35302.0] || -> . % 76.03/76.21 36202[91:Spt:36201.0,35703.0,35704.0] || until2p7(s23)*+ -> . % 76.03/76.21 36203[91:Spt:36201.0,35703.1] || -> node4(s22)*. % 76.03/76.21 36205[91:MRR:852.0,36203.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.03/76.21 36208[91:Res:53.1,36205.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.03/76.21 36210[91:MRR:36208.0,35693.0] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.21 36212[91:Res:36210.0,61.1] always3(s23) || -> . % 76.03/76.21 36213[91:SSi:36212.0,712.0,35294.0,35296.0] || -> . % 76.03/76.21 36214[89:Spt:36213.0,35537.1,35539.0] || xuntil6(s48)* -> . % 76.03/76.21 36215[89:Spt:36213.0,35537.0] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.21 36218[89:Res:36215.0,61.1] always3(s48) || -> . % 76.03/76.21 36219[89:SSi:36218.0,737.0,35527.0] || -> . % 76.03/76.21 36220[87:Spt:36219.0,35521.2,35526.0] || xuntil6(s47)*+ -> . % 76.03/76.21 36221[87:Spt:36219.0,35521.0,35521.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.03/76.21 36222[87:Res:53.1,36221.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.03/76.21 36224[87:MRR:36222.0,35513.0] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.21 36226[87:Res:36224.0,61.1] always3(s48) || -> . % 76.03/76.21 36227[87:SSi:36226.0,737.0] || -> . % 76.03/76.21 36228[86:Spt:36227.0,35517.1,35519.0] || xuntil6(s46)* -> . % 76.03/76.21 36229[86:Spt:36227.0,35517.0] || -> m_main_v_state(s46,c_busy)*. % 76.03/76.21 36232[86:Res:36229.0,61.1] always3(s46) || -> . % 76.03/76.21 36233[86:SSi:36232.0,735.0,35507.0] || -> . % 76.03/76.21 36234[84:Spt:36233.0,35504.2,35506.0] || xuntil6(s45)*+ -> . % 76.03/76.21 36235[84:Spt:36233.0,35504.0,35504.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.03/76.21 36236[84:Res:53.1,36235.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.03/76.21 36238[84:MRR:36236.0,35493.0] || -> m_main_v_state(s46,c_busy)*. % 76.03/76.21 36240[84:Res:36238.0,61.1] always3(s46) || -> . % 76.03/76.21 36241[84:SSi:36240.0,735.0] || -> . % 76.03/76.21 36242[83:Spt:36241.0,35497.1,35502.0] || xuntil6(s44)* -> . % 76.03/76.21 36243[83:Spt:36241.0,35497.0] || -> m_main_v_state(s44,c_busy)*. % 76.03/76.21 36246[83:Res:36243.0,61.1] always3(s44) || -> . % 76.03/76.21 36247[83:SSi:36246.0,733.0,35487.0] || -> . % 76.03/76.21 36248[81:Spt:36247.0,35478.2,35486.0] || xuntil6(s43)*+ -> . % 76.03/76.21 36249[81:Spt:36247.0,35478.0,35478.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.03/76.21 36250[81:Res:53.1,36249.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.03/76.21 36252[81:MRR:36250.0,35470.0] || -> m_main_v_state(s44,c_busy)*. % 76.03/76.21 36254[81:Res:36252.0,61.1] always3(s44) || -> . % 76.03/76.21 36255[81:SSi:36254.0,733.0] || -> . % 76.03/76.21 36256[80:Spt:36255.0,35474.1,35476.0] || xuntil6(s42)* -> . % 76.03/76.21 36257[80:Spt:36255.0,35474.0] || -> m_main_v_state(s42,c_busy)*. % 76.03/76.21 36260[80:Res:36257.0,61.1] always3(s42) || -> . % 76.03/76.21 36261[80:SSi:36260.0,731.0,35464.0] || -> . % 76.03/76.21 36262[78:Spt:36261.0,35458.2,35463.0] || xuntil6(s41)*+ -> . % 76.03/76.21 36263[78:Spt:36261.0,35458.0,35458.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.03/76.21 36264[78:Res:53.1,36263.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.03/76.21 36266[78:MRR:36264.0,35450.0] || -> m_main_v_state(s42,c_busy)*. % 76.03/76.21 36269[78:Res:36266.0,61.1] always3(s42) || -> . % 76.03/76.21 36270[78:SSi:36269.0,731.0] || -> . % 76.03/76.21 36271[77:Spt:36270.0,35454.1,35456.0] || xuntil6(s40)* -> . % 76.03/76.21 36272[77:Spt:36270.0,35454.0] || -> m_main_v_state(s40,c_busy)*. % 76.03/76.21 36275[77:Res:36272.0,61.1] always3(s40) || -> . % 76.03/76.21 36276[77:SSi:36275.0,729.0,35444.0] || -> . % 76.03/76.21 36277[75:Spt:36276.0,35441.2,35443.0] || xuntil6(s39)*+ -> . % 76.03/76.21 36278[75:Spt:36276.0,35441.0,35441.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.03/76.21 36279[75:Res:53.1,36278.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.03/76.21 36281[75:MRR:36279.0,35430.0] || -> m_main_v_state(s40,c_busy)*. % 76.03/76.21 36283[75:Res:36281.0,61.1] always3(s40) || -> . % 76.03/76.21 36284[75:SSi:36283.0,729.0] || -> . % 76.03/76.21 36285[74:Spt:36284.0,35434.1,35439.0] || xuntil6(s38)* -> . % 76.03/76.21 36286[74:Spt:36284.0,35434.0] || -> m_main_v_state(s38,c_busy)*. % 76.03/76.21 36289[74:Res:36286.0,61.1] always3(s38) || -> . % 76.03/76.21 36290[74:SSi:36289.0,727.0,35424.0] || -> . % 76.03/76.21 36291[72:Spt:36290.0,35415.2,35423.0] || xuntil6(s37)*+ -> . % 76.03/76.21 36292[72:Spt:36290.0,35415.0,35415.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.03/76.21 36293[72:Res:53.1,36292.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.03/76.21 36295[72:MRR:36293.0,35407.0] || -> m_main_v_state(s38,c_busy)*. % 76.03/76.21 36298[72:Res:36295.0,61.1] always3(s38) || -> . % 76.03/76.21 36299[72:SSi:36298.0,727.0] || -> . % 76.03/76.21 36300[71:Spt:36299.0,35411.1,35413.0] || xuntil6(s36)* -> . % 76.03/76.21 36301[71:Spt:36299.0,35411.0] || -> m_main_v_state(s36,c_busy)*. % 76.03/76.21 36304[71:Res:36301.0,61.1] always3(s36) || -> . % 76.03/76.21 36305[71:SSi:36304.0,725.0,35401.0] || -> . % 76.03/76.21 36306[69:Spt:36305.0,35395.2,35400.0] || xuntil6(s35)*+ -> . % 76.03/76.21 36307[69:Spt:36305.0,35395.0,35395.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.03/76.21 36308[69:Res:53.1,36307.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.03/76.21 36310[69:MRR:36308.0,35387.0] || -> m_main_v_state(s36,c_busy)*. % 76.03/76.21 36312[69:Res:36310.0,61.1] always3(s36) || -> . % 76.03/76.21 36313[69:SSi:36312.0,725.0] || -> . % 76.03/76.21 36314[68:Spt:36313.0,35391.1,35393.0] || xuntil6(s34)* -> . % 76.03/76.21 36315[68:Spt:36313.0,35391.0] || -> m_main_v_state(s34,c_busy)*. % 76.03/76.21 36318[68:Res:36315.0,61.1] always3(s34) || -> . % 76.03/76.21 36319[68:SSi:36318.0,723.0,35381.0] || -> . % 76.03/76.21 36320[66:Spt:36319.0,35378.2,35380.0] || xuntil6(s33)*+ -> . % 76.03/76.21 36321[66:Spt:36319.0,35378.0,35378.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.03/76.21 36322[66:Res:53.1,36321.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.03/76.21 36324[66:MRR:36322.0,35367.0] || -> m_main_v_state(s34,c_busy)*. % 76.03/76.21 36326[66:Res:36324.0,61.1] always3(s34) || -> . % 76.03/76.21 36327[66:SSi:36326.0,723.0] || -> . % 76.03/76.21 36328[65:Spt:36327.0,35371.1,35376.0] || xuntil6(s32)* -> . % 76.03/76.21 36329[65:Spt:36327.0,35371.0] || -> m_main_v_state(s32,c_busy)*. % 76.03/76.21 36332[65:Res:36329.0,61.1] always3(s32) || -> . % 76.03/76.21 36333[65:SSi:36332.0,721.0,35361.0] || -> . % 76.03/76.21 36334[63:Spt:36333.0,35352.2,35360.0] || xuntil6(s31)*+ -> . % 76.03/76.21 36335[63:Spt:36333.0,35352.0,35352.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.03/76.21 36336[63:Res:53.1,36335.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.03/76.21 36338[63:MRR:36336.0,35344.0] || -> m_main_v_state(s32,c_busy)*. % 76.03/76.21 36340[63:Res:36338.0,61.1] always3(s32) || -> . % 76.03/76.21 36341[63:SSi:36340.0,721.0] || -> . % 76.03/76.21 36342[62:Spt:36341.0,35348.1,35350.0] || xuntil6(s30)* -> . % 76.03/76.21 36343[62:Spt:36341.0,35348.0] || -> m_main_v_state(s30,c_busy)*. % 76.03/76.21 36346[62:Res:36343.0,61.1] always3(s30) || -> . % 76.03/76.21 36347[62:SSi:36346.0,719.0,35338.0] || -> . % 76.03/76.21 36348[60:Spt:36347.0,35332.2,35337.0] || xuntil6(s29)*+ -> . % 76.03/76.21 36349[60:Spt:36347.0,35332.0,35332.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.03/76.21 36350[60:Res:53.1,36349.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.03/76.21 36352[60:MRR:36350.0,35324.0] || -> m_main_v_state(s30,c_busy)*. % 76.03/76.21 36354[60:Res:36352.0,61.1] always3(s30) || -> . % 76.03/76.21 36355[60:SSi:36354.0,719.0] || -> . % 76.03/76.21 36356[59:Spt:36355.0,35328.1,35330.0] || xuntil6(s28)* -> . % 76.03/76.21 36357[59:Spt:36355.0,35328.0] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.21 36360[59:Res:36357.0,61.1] always3(s28) || -> . % 76.03/76.21 36361[59:SSi:36360.0,717.0,35315.0] || -> . % 76.03/76.21 36362[57:Spt:36361.0,35313.2,35314.0] || xuntil6(s27)*+ -> . % 76.03/76.21 36363[57:Spt:36361.0,35313.0,35313.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.03/76.21 36364[57:Res:53.1,36363.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.03/76.21 36366[58:Spt:36364.1] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.21 36368[58:Res:36366.0,61.1] always3(s28) || -> . % 76.03/76.21 36369[58:SSi:36368.0,717.0] || -> . % 76.03/76.21 36370[58:Spt:36369.0,36364.1,36366.0] || m_main_v_state(s28,c_busy)* -> . % 76.03/76.21 36371[58:Spt:36369.0,36364.0] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.21 36374[58:Res:36371.0,61.1] always3(s27) || -> . % 76.03/76.21 36375[58:SSi:36374.0,716.0,35312.0] || -> . % 76.03/76.21 36376[56:Spt:36375.0,35307.2,35311.0] || xuntil6(s26)*+ -> . % 76.03/76.21 36377[56:Spt:36375.0,35307.0,35307.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.03/76.21 36378[56:Res:53.1,36377.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.03/76.21 36380[57:Spt:36378.1] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.21 36382[57:Res:36380.0,61.1] always3(s27) || -> . % 76.03/76.21 36383[57:SSi:36382.0,716.0] || -> . % 76.03/76.21 36384[57:Spt:36383.0,36378.1,36380.0] || m_main_v_state(s27,c_busy)* -> . % 76.03/76.21 36385[57:Spt:36383.0,36378.0] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.21 36388[57:Res:36385.0,61.1] always3(s26) || -> . % 76.03/76.21 36389[57:SSi:36388.0,715.0,35306.0] || -> . % 76.03/76.21 36390[55:Spt:36389.0,35304.2,35305.0] || xuntil6(s25)*+ -> . % 76.03/76.21 36391[55:Spt:36389.0,35304.0,35304.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.03/76.21 36392[55:Res:53.1,36391.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.03/76.21 36394[56:Spt:36392.1] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.21 36396[56:Res:36394.0,61.1] always3(s26) || -> . % 76.03/76.21 36397[56:SSi:36396.0,715.0] || -> . % 76.03/76.21 36398[56:Spt:36397.0,36392.1,36394.0] || m_main_v_state(s26,c_busy)* -> . % 76.03/76.21 36399[56:Spt:36397.0,36392.0] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.21 36402[56:Res:36399.0,61.1] always3(s25) || -> . % 76.03/76.21 36403[56:SSi:36402.0,714.0,35303.0] || -> . % 76.03/76.21 36404[54:Spt:36403.0,35298.2,35302.0] || xuntil6(s24)*+ -> . % 76.03/76.21 36405[54:Spt:36403.0,35298.0,35298.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.03/76.21 36406[54:Res:53.1,36405.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.03/76.21 36408[55:Spt:36406.1] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.21 36410[55:Res:36408.0,61.1] always3(s25) || -> . % 76.03/76.21 36411[55:SSi:36410.0,714.0] || -> . % 76.03/76.21 36412[55:Spt:36411.0,36406.1,36408.0] || m_main_v_state(s25,c_busy)* -> . % 76.03/76.21 36413[55:Spt:36411.0,36406.0] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.21 36416[55:Res:36413.0,61.1] always3(s24) || -> . % 76.03/76.21 36417[55:SSi:36416.0,713.0,35297.0] || -> . % 76.03/76.21 36418[53:Spt:36417.0,35295.2,35296.0] || xuntil6(s23)*+ -> . % 76.03/76.21 36419[53:Spt:36417.0,35295.0,35295.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.03/76.21 36420[53:Res:53.1,36419.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.03/76.21 36422[54:Spt:36420.1] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.21 36424[54:Res:36422.0,61.1] always3(s24) || -> . % 76.03/76.21 36425[54:SSi:36424.0,713.0] || -> . % 76.03/76.21 36426[54:Spt:36425.0,36420.1,36422.0] || m_main_v_state(s24,c_busy)* -> . % 76.03/76.21 36427[54:Spt:36425.0,36420.0] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.21 36430[54:Res:36427.0,61.1] always3(s23) || -> . % 76.03/76.21 36431[54:SSi:36430.0,712.0,35294.0] || -> . % 76.03/76.21 36432[52:Spt:36431.0,35289.2,35293.0] || xuntil6(s22)*+ -> . % 76.03/76.21 36433[52:Spt:36431.0,35289.0,35289.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.03/76.21 36434[52:Res:53.1,36433.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.03/76.21 36436[53:Spt:36434.1] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.21 36438[53:Res:36436.0,61.1] always3(s23) || -> . % 76.03/76.21 36439[53:SSi:36438.0,712.0] || -> . % 76.03/76.21 36440[53:Spt:36439.0,36434.1,36436.0] || m_main_v_state(s23,c_busy)* -> . % 76.03/76.21 36441[53:Spt:36439.0,36434.0] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.21 36444[53:Res:36441.0,61.1] always3(s22) || -> . % 76.03/76.21 36445[53:SSi:36444.0,711.0,35288.0] || -> . % 76.03/76.21 36446[51:Spt:36445.0,35286.2,35287.0] || xuntil6(s21)*+ -> . % 76.03/76.21 36447[51:Spt:36445.0,35286.0,35286.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.03/76.21 36448[51:Res:53.1,36447.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.03/76.21 36450[52:Spt:36448.0] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.21 36452[52:Res:36450.0,61.1] always3(s21) || -> . % 76.03/76.21 36453[52:SSi:36452.0,710.0,35285.0] || -> . % 76.03/76.21 36454[52:Spt:36453.0,36448.0,36450.0] || m_main_v_state(s21,c_busy)* -> . % 76.03/76.21 36455[52:Spt:36453.0,36448.1] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.21 36459[52:Res:36455.0,61.1] always3(s22) || -> . % 76.03/76.21 36460[52:SSi:36459.0,711.0] || -> . % 76.03/76.21 36461[50:Spt:36460.0,35280.2,35284.0] || xuntil6(s20)*+ -> . % 76.03/76.21 36462[50:Spt:36460.0,35280.0,35280.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.03/76.21 36463[50:Res:53.1,36462.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.03/76.21 36465[51:Spt:36463.0] || -> m_main_v_state(s20,c_busy)*. % 76.03/76.21 36467[51:Res:36465.0,61.1] always3(s20) || -> . % 76.03/76.21 36468[51:SSi:36467.0,709.0,35279.0] || -> . % 76.03/76.21 36469[51:Spt:36468.0,36463.0,36465.0] || m_main_v_state(s20,c_busy)* -> . % 76.03/76.21 36470[51:Spt:36468.0,36463.1] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.21 36474[51:Res:36470.0,61.1] always3(s21) || -> . % 76.03/76.21 36475[51:SSi:36474.0,710.0] || -> . % 76.03/76.21 36476[49:Spt:36475.0,35277.2,35278.0] || xuntil6(s19)*+ -> . % 76.03/76.21 36477[49:Spt:36475.0,35277.0,35277.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.03/76.21 36478[49:Res:53.1,36477.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.03/76.21 36483[50:Spt:36478.0] || -> m_main_v_state(s19,c_busy)*. % 76.03/76.21 36485[50:Res:36483.0,61.1] always3(s19) || -> . % 76.03/76.21 36486[50:SSi:36485.0,708.0,35276.0] || -> . % 76.03/76.21 36487[50:Spt:36486.0,36478.0,36483.0] || m_main_v_state(s19,c_busy)* -> . % 76.03/76.21 36488[50:Spt:36486.0,36478.1] || -> m_main_v_state(s20,c_busy)*. % 76.03/76.21 36492[50:Res:36488.0,61.1] always3(s20) || -> . % 76.03/76.21 36493[50:SSi:36492.0,709.0] || -> . % 76.03/76.21 36494[48:Spt:36493.0,35271.2,35275.0] || xuntil6(s18)*+ -> . % 76.03/76.21 36495[48:Spt:36493.0,35271.0,35271.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.03/76.21 36496[48:Res:53.1,36495.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.03/76.21 36498[49:Spt:36496.0] || -> m_main_v_state(s18,c_busy)*. % 76.03/76.21 36500[49:Res:36498.0,61.1] always3(s18) || -> . % 76.03/76.21 36501[49:SSi:36500.0,707.0,35270.0] || -> . % 76.03/76.21 36502[49:Spt:36501.0,36496.0,36498.0] || m_main_v_state(s18,c_busy)* -> . % 76.03/76.21 36503[49:Spt:36501.0,36496.1] || -> m_main_v_state(s19,c_busy)*. % 76.03/76.21 36507[49:Res:36503.0,61.1] always3(s19) || -> . % 76.03/76.21 36508[49:SSi:36507.0,708.0] || -> . % 76.03/76.21 36509[47:Spt:36508.0,35268.2,35269.0] || xuntil6(s17)*+ -> . % 76.03/76.21 36510[47:Spt:36508.0,35268.0,35268.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.03/76.21 36511[47:Res:53.1,36510.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.03/76.21 36513[48:Spt:36511.0] || -> m_main_v_state(s17,c_busy)*. % 76.03/76.21 36515[48:Res:36513.0,61.1] always3(s17) || -> . % 76.03/76.21 36516[48:SSi:36515.0,706.0,35267.0] || -> . % 76.03/76.21 36517[48:Spt:36516.0,36511.0,36513.0] || m_main_v_state(s17,c_busy)* -> . % 76.03/76.21 36518[48:Spt:36516.0,36511.1] || -> m_main_v_state(s18,c_busy)*. % 76.03/76.21 36522[48:Res:36518.0,61.1] always3(s18) || -> . % 76.03/76.21 36523[48:SSi:36522.0,707.0] || -> . % 76.03/76.21 36524[46:Spt:36523.0,35262.2,35266.0] || xuntil6(s16)*+ -> . % 76.03/76.21 36525[46:Spt:36523.0,35262.0,35262.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.03/76.21 36526[46:Res:53.1,36525.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.03/76.21 36531[47:Spt:36526.0] || -> m_main_v_state(s16,c_busy)*. % 76.03/76.21 36533[47:Res:36531.0,61.1] always3(s16) || -> . % 76.03/76.21 36534[47:SSi:36533.0,705.0,35261.0] || -> . % 76.03/76.21 36535[47:Spt:36534.0,36526.0,36531.0] || m_main_v_state(s16,c_busy)* -> . % 76.03/76.21 36536[47:Spt:36534.0,36526.1] || -> m_main_v_state(s17,c_busy)*. % 76.03/76.21 36540[47:Res:36536.0,61.1] always3(s17) || -> . % 76.03/76.21 36541[47:SSi:36540.0,706.0] || -> . % 76.03/76.21 36542[45:Spt:36541.0,35259.2,35260.0] || xuntil6(s15)*+ -> . % 76.03/76.21 36543[45:Spt:36541.0,35259.0,35259.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.03/76.21 36544[45:Res:53.1,36543.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.03/76.21 36546[46:Spt:36544.0] || -> m_main_v_state(s15,c_busy)*. % 76.03/76.21 36548[46:Res:36546.0,61.1] always3(s15) || -> . % 76.03/76.21 36549[46:SSi:36548.0,704.0,35258.0] || -> . % 76.03/76.21 36550[46:Spt:36549.0,36544.0,36546.0] || m_main_v_state(s15,c_busy)* -> . % 76.03/76.21 36551[46:Spt:36549.0,36544.1] || -> m_main_v_state(s16,c_busy)*. % 76.03/76.21 36555[46:Res:36551.0,61.1] always3(s16) || -> . % 76.03/76.21 36556[46:SSi:36555.0,705.0] || -> . % 76.03/76.21 36557[44:Spt:36556.0,35253.2,35257.0] || xuntil6(s14)*+ -> . % 76.03/76.21 36558[44:Spt:36556.0,35253.0,35253.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.03/76.21 36559[44:Res:53.1,36558.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.03/76.21 36561[45:Spt:36559.0] || -> m_main_v_state(s14,c_busy)*. % 76.03/76.21 36563[45:Res:36561.0,61.1] always3(s14) || -> . % 76.03/76.21 36564[45:SSi:36563.0,703.0,35252.0] || -> . % 76.03/76.21 36565[45:Spt:36564.0,36559.0,36561.0] || m_main_v_state(s14,c_busy)* -> . % 76.03/76.21 36566[45:Spt:36564.0,36559.1] || -> m_main_v_state(s15,c_busy)*. % 76.03/76.21 36570[45:Res:36566.0,61.1] always3(s15) || -> . % 76.03/76.21 36571[45:SSi:36570.0,704.0] || -> . % 76.03/76.21 36572[43:Spt:36571.0,35250.2,35251.0] || xuntil6(s13)*+ -> . % 76.03/76.21 36573[43:Spt:36571.0,35250.0,35250.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.03/76.21 36574[43:Res:53.1,36573.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.03/76.21 36579[44:Spt:36574.0] || -> m_main_v_state(s13,c_busy)*. % 76.03/76.21 36581[44:Res:36579.0,61.1] always3(s13) || -> . % 76.03/76.21 36582[44:SSi:36581.0,702.0,35249.0] || -> . % 76.03/76.21 36583[44:Spt:36582.0,36574.0,36579.0] || m_main_v_state(s13,c_busy)* -> . % 76.03/76.21 36584[44:Spt:36582.0,36574.1] || -> m_main_v_state(s14,c_busy)*. % 76.03/76.21 36588[44:Res:36584.0,61.1] always3(s14) || -> . % 76.03/76.21 36589[44:SSi:36588.0,703.0] || -> . % 76.03/76.21 36590[42:Spt:36589.0,35244.2,35248.0] || xuntil6(s12)*+ -> . % 76.03/76.21 36591[42:Spt:36589.0,35244.0,35244.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.03/76.21 36592[42:Res:53.1,36591.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.03/76.21 36594[43:Spt:36592.0] || -> m_main_v_state(s12,c_busy)*. % 76.03/76.21 36596[43:Res:36594.0,61.1] always3(s12) || -> . % 76.03/76.21 36597[43:SSi:36596.0,701.0,35243.0] || -> . % 76.03/76.21 36598[43:Spt:36597.0,36592.0,36594.0] || m_main_v_state(s12,c_busy)* -> . % 76.03/76.21 36599[43:Spt:36597.0,36592.1] || -> m_main_v_state(s13,c_busy)*. % 76.03/76.21 36603[43:Res:36599.0,61.1] always3(s13) || -> . % 76.03/76.21 36604[43:SSi:36603.0,702.0] || -> . % 76.03/76.21 36605[41:Spt:36604.0,35241.2,35242.0] || xuntil6(s11)*+ -> . % 76.03/76.21 36606[41:Spt:36604.0,35241.0,35241.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.03/76.21 36607[41:Res:53.1,36606.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.03/76.21 36609[42:Spt:36607.0] || -> m_main_v_state(s11,c_busy)*. % 76.03/76.21 36611[42:Res:36609.0,61.1] always3(s11) || -> . % 76.03/76.21 36612[42:SSi:36611.0,700.0,35240.0] || -> . % 76.03/76.21 36613[42:Spt:36612.0,36607.0,36609.0] || m_main_v_state(s11,c_busy)* -> . % 76.03/76.21 36614[42:Spt:36612.0,36607.1] || -> m_main_v_state(s12,c_busy)*. % 76.03/76.21 36618[42:Res:36614.0,61.1] always3(s12) || -> . % 76.03/76.21 36619[42:SSi:36618.0,701.0] || -> . % 76.03/76.21 36620[40:Spt:36619.0,35235.2,35239.0] || xuntil6(s10)*+ -> . % 76.03/76.21 36621[40:Spt:36619.0,35235.0,35235.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.03/76.21 36622[40:Res:53.1,36621.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.03/76.21 36627[41:Spt:36622.0] || -> m_main_v_state(s10,c_busy)*. % 76.03/76.21 36629[41:Res:36627.0,61.1] always3(s10) || -> . % 76.03/76.21 36630[41:SSi:36629.0,699.0,35234.0] || -> . % 76.03/76.21 36631[41:Spt:36630.0,36622.0,36627.0] || m_main_v_state(s10,c_busy)* -> . % 76.03/76.21 36632[41:Spt:36630.0,36622.1] || -> m_main_v_state(s11,c_busy)*. % 76.03/76.21 36636[41:Res:36632.0,61.1] always3(s11) || -> . % 76.03/76.21 36637[41:SSi:36636.0,700.0] || -> . % 76.03/76.21 36638[39:Spt:36637.0,35232.2,35233.0] || xuntil6(s9)*+ -> . % 76.03/76.21 36639[39:Spt:36637.0,35232.0,35232.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.03/76.21 36640[39:Res:53.1,36639.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.03/76.21 36642[40:Spt:36640.0] || -> m_main_v_state(s9,c_busy)*. % 76.03/76.21 36644[40:Res:36642.0,61.1] always3(s9) || -> . % 76.03/76.21 36645[40:SSi:36644.0,698.0,35231.0] || -> . % 76.03/76.21 36646[40:Spt:36645.0,36640.0,36642.0] || m_main_v_state(s9,c_busy)* -> . % 76.03/76.21 36647[40:Spt:36645.0,36640.1] || -> m_main_v_state(s10,c_busy)*. % 76.03/76.21 36651[40:Res:36647.0,61.1] always3(s10) || -> . % 76.03/76.21 36652[40:SSi:36651.0,699.0] || -> . % 76.03/76.21 36653[38:Spt:36652.0,35226.2,35230.0] || xuntil6(s8)*+ -> . % 76.03/76.21 36654[38:Spt:36652.0,35226.0,35226.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.03/76.21 36655[38:Res:53.1,36654.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.03/76.21 36657[39:Spt:36655.0] || -> m_main_v_state(s8,c_busy)*. % 76.03/76.21 36659[39:Res:36657.0,61.1] always3(s8) || -> . % 76.03/76.21 36660[39:SSi:36659.0,697.0,35225.0] || -> . % 76.03/76.21 36661[39:Spt:36660.0,36655.0,36657.0] || m_main_v_state(s8,c_busy)* -> . % 76.03/76.21 36662[39:Spt:36660.0,36655.1] || -> m_main_v_state(s9,c_busy)*. % 76.03/76.21 36666[39:Res:36662.0,61.1] always3(s9) || -> . % 76.03/76.21 36667[39:SSi:36666.0,698.0] || -> . % 76.03/76.21 36668[37:Spt:36667.0,35223.2,35224.0] || xuntil6(s7)*+ -> . % 76.03/76.21 36669[37:Spt:36667.0,35223.0,35223.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.03/76.21 36670[37:Res:53.1,36669.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.03/76.21 36675[38:Spt:36670.0] || -> m_main_v_state(s7,c_busy)*. % 76.03/76.21 36677[38:Res:36675.0,61.1] always3(s7) || -> . % 76.03/76.21 36678[38:SSi:36677.0,696.0,35222.0] || -> . % 76.03/76.21 36679[38:Spt:36678.0,36670.0,36675.0] || m_main_v_state(s7,c_busy)* -> . % 76.03/76.21 36680[38:Spt:36678.0,36670.1] || -> m_main_v_state(s8,c_busy)*. % 76.03/76.21 36684[38:Res:36680.0,61.1] always3(s8) || -> . % 76.03/76.21 36685[38:SSi:36684.0,697.0] || -> . % 76.03/76.21 36686[36:Spt:36685.0,35217.2,35221.0] || xuntil6(s6)*+ -> . % 76.03/76.21 36687[36:Spt:36685.0,35217.0,35217.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.03/76.21 36688[36:Res:53.1,36687.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.03/76.21 36690[37:Spt:36688.0] || -> m_main_v_state(s6,c_busy)*. % 76.03/76.21 36692[37:Res:36690.0,61.1] always3(s6) || -> . % 76.03/76.21 36693[37:SSi:36692.0,695.0,35216.0] || -> . % 76.03/76.21 36694[37:Spt:36693.0,36688.0,36690.0] || m_main_v_state(s6,c_busy)* -> . % 76.03/76.21 36695[37:Spt:36693.0,36688.1] || -> m_main_v_state(s7,c_busy)*. % 76.03/76.21 36699[37:Res:36695.0,61.1] always3(s7) || -> . % 76.03/76.21 36700[37:SSi:36699.0,696.0] || -> . % 76.03/76.21 36701[35:Spt:36700.0,35214.2,35215.0] || xuntil6(s5)*+ -> . % 76.03/76.21 36702[35:Spt:36700.0,35214.0,35214.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.03/76.21 36703[35:Res:53.1,36702.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.03/76.21 36705[36:Spt:36703.0] || -> m_main_v_state(s5,c_busy)*. % 76.03/76.21 36707[36:Res:36705.0,61.1] always3(s5) || -> . % 76.03/76.21 36708[36:SSi:36707.0,694.0,35213.0] || -> . % 76.03/76.21 36709[36:Spt:36708.0,36703.0,36705.0] || m_main_v_state(s5,c_busy)* -> . % 76.03/76.21 36710[36:Spt:36708.0,36703.1] || -> m_main_v_state(s6,c_busy)*. % 76.03/76.21 36714[36:Res:36710.0,61.1] always3(s6) || -> . % 76.03/76.21 36715[36:SSi:36714.0,695.0] || -> . % 76.03/76.21 36716[34:Spt:36715.0,35208.2,35212.0] || xuntil6(s4)*+ -> . % 76.03/76.21 36717[34:Spt:36715.0,35208.0,35208.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.03/76.21 36718[34:Res:53.1,36717.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.03/76.21 36723[35:Spt:36718.0] || -> m_main_v_state(s4,c_busy)*. % 76.03/76.21 36725[35:Res:36723.0,61.1] always3(s4) || -> . % 76.03/76.21 36726[35:SSi:36725.0,693.0,35207.0] || -> . % 76.03/76.21 36727[35:Spt:36726.0,36718.0,36723.0] || m_main_v_state(s4,c_busy)* -> . % 76.03/76.21 36728[35:Spt:36726.0,36718.1] || -> m_main_v_state(s5,c_busy)*. % 76.03/76.21 36732[35:Res:36728.0,61.1] always3(s5) || -> . % 76.03/76.21 36733[35:SSi:36732.0,694.0] || -> . % 76.03/76.21 36734[33:Spt:36733.0,35205.2,35206.0] || xuntil6(s3)*+ -> . % 76.03/76.21 36735[33:Spt:36733.0,35205.0,35205.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.03/76.21 36736[33:Res:53.1,36735.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.03/76.21 36738[34:Spt:36736.0] || -> m_main_v_state(s3,c_busy)*. % 76.03/76.21 36740[34:Res:36738.0,61.1] always3(s3) || -> . % 76.03/76.21 36741[34:SSi:36740.0,692.0,35204.0] || -> . % 76.03/76.21 36742[34:Spt:36741.0,36736.0,36738.0] || m_main_v_state(s3,c_busy)* -> . % 76.03/76.21 36743[34:Spt:36741.0,36736.1] || -> m_main_v_state(s4,c_busy)*. % 76.03/76.21 36747[34:Res:36743.0,61.1] always3(s4) || -> . % 76.03/76.21 36748[34:SSi:36747.0,693.0] || -> . % 76.03/76.21 36749[32:Spt:36748.0,35199.2,35203.0] || xuntil6(s2)*+ -> . % 76.03/76.21 36750[32:Spt:36748.0,35199.0,35199.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.03/76.21 36751[32:Res:53.1,36750.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.03/76.21 36753[33:Spt:36751.0] || -> m_main_v_state(s2,c_busy)*. % 76.03/76.21 36755[33:Res:36753.0,61.1] always3(s2) || -> . % 76.03/76.21 36756[33:SSi:36755.0,691.0,35198.0] || -> . % 76.03/76.21 36757[33:Spt:36756.0,36751.0,36753.0] || m_main_v_state(s2,c_busy)* -> . % 76.03/76.21 36758[33:Spt:36756.0,36751.1] || -> m_main_v_state(s3,c_busy)*. % 76.03/76.21 36762[33:Res:36758.0,61.1] always3(s3) || -> . % 76.03/76.21 36763[33:SSi:36762.0,692.0] || -> . % 76.03/76.21 36764[31:Spt:36763.0,35193.2,35197.0] || xuntil6(s1)*+ -> . % 76.03/76.21 36765[31:Spt:36763.0,35193.0,35193.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.03/76.21 36766[31:Res:53.1,36765.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.03/76.21 36771[32:Spt:36766.0] || -> m_main_v_state(s1,c_busy)*. % 76.03/76.21 36773[32:Res:36771.0,61.1] always3(s1) || -> . % 76.03/76.21 36774[32:SSi:36773.0,690.0,35192.0] || -> . % 76.03/76.21 36775[32:Spt:36774.0,36766.0,36771.0] || m_main_v_state(s1,c_busy)* -> . % 76.03/76.21 36776[32:Spt:36774.0,36766.1] || -> m_main_v_state(s2,c_busy)*. % 76.03/76.21 36781[32:Res:36776.0,61.1] always3(s2) || -> . % 76.03/76.21 36782[32:SSi:36781.0,691.0] || -> . % 76.03/76.21 36783[30:Spt:36782.0,74.0,35191.0] || xuntil6(s0)*+ -> . % 76.03/76.21 36784[30:Spt:36782.0,74.1] || -> node4(s0)*. % 76.03/76.21 36785[30:MRR:758.1,36783.0] || -> m_main_v_state(s1,c_busy)*. % 76.03/76.21 36787[30:Res:36785.0,61.1] always3(s1) || -> . % 76.03/76.21 36788[30:SSi:36787.0,690.0] || -> . % 76.03/76.21 36789[29:Spt:36788.0,35181.0,35185.0] || trans(s49,s22)*+ -> . % 76.03/76.21 36790[29:Spt:36788.0,35181.1,35181.2,35181.3,35181.4,35181.5,35181.6,35181.7,35181.8,35181.9,35181.10,35181.11,35181.12,35181.13,35181.14,35181.15,35181.16,35181.17,35181.18,35181.19,35181.20,35181.21,35181.22] || -> trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.03/76.21 36792[29:MRR:35182.0,36789.0] || -> trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.03/76.21 36793[29:MRR:35184.1,36789.0] xuntil6(s49) || -> trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.03/76.21 36794[30:Spt:36790.0] || -> trans(s49,s21)*. % 76.03/76.21 36795[30:Res:36794.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s21)*. % 76.03/76.21 36797[30:Res:36794.0,60.0] || -> node2(s49,s21)*. % 76.03/76.21 36798[30:SSi:36795.1,50.0,738.0] xuntil6(s49) || -> until2p7(s21)*. % 76.03/76.21 36799[30:Res:36797.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)*. % 76.03/76.21 36800[31:Spt:74.0] || -> xuntil6(s0)*. % 76.03/76.21 36801[31:MRR:176.0,36800.0] || -> until5(s1)*. % 76.03/76.21 36802[31:MRR:35646.0,36801.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.03/76.21 36806[32:Spt:36802.2] || -> xuntil6(s1)*. % 76.03/76.21 36807[32:MRR:175.0,36806.0] || -> until5(s2)*. % 76.03/76.21 36808[32:MRR:35639.0,36807.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.03/76.21 36809[33:Spt:36808.2] || -> xuntil6(s2)*. % 76.03/76.21 36810[33:MRR:174.0,36809.0] || -> until5(s3)*. % 76.03/76.21 36811[33:MRR:35635.0,36810.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.03/76.21 36812[34:Spt:36811.2] || -> xuntil6(s3)*. % 76.03/76.21 36813[34:MRR:173.0,36812.0] || -> until5(s4)*. % 76.03/76.21 36814[34:MRR:35631.0,36813.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.03/76.21 36815[35:Spt:36814.2] || -> xuntil6(s4)*. % 76.03/76.21 36816[35:MRR:172.0,36815.0] || -> until5(s5)*. % 76.03/76.21 36817[35:MRR:35627.0,36816.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.03/76.21 36821[36:Spt:36817.2] || -> xuntil6(s5)*. % 76.03/76.21 36822[36:MRR:171.0,36821.0] || -> until5(s6)*. % 76.03/76.21 36823[36:MRR:35626.0,36822.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.03/76.21 36824[37:Spt:36823.2] || -> xuntil6(s6)*. % 76.03/76.21 36825[37:MRR:170.0,36824.0] || -> until5(s7)*. % 76.03/76.21 36826[37:MRR:35619.0,36825.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.03/76.21 36830[38:Spt:36826.2] || -> xuntil6(s7)*. % 76.03/76.21 36831[38:MRR:169.0,36830.0] || -> until5(s8)*. % 76.03/76.21 36832[38:MRR:35615.0,36831.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.03/76.21 36833[39:Spt:36832.2] || -> xuntil6(s8)*. % 76.03/76.21 36834[39:MRR:168.0,36833.0] || -> until5(s9)*. % 76.03/76.21 36835[39:MRR:35611.0,36834.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.03/76.21 36839[40:Spt:36835.2] || -> xuntil6(s9)*. % 76.03/76.21 36840[40:MRR:167.0,36839.0] || -> until5(s10)*. % 76.03/76.21 36841[40:MRR:35607.0,36840.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.03/76.21 36842[41:Spt:36841.2] || -> xuntil6(s10)*. % 76.03/76.21 36843[41:MRR:166.0,36842.0] || -> until5(s11)*. % 76.03/76.21 36844[41:MRR:35606.0,36843.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.03/76.21 36848[42:Spt:36844.2] || -> xuntil6(s11)*. % 76.03/76.21 36849[42:MRR:165.0,36848.0] || -> until5(s12)*. % 76.03/76.21 36850[42:MRR:35599.0,36849.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.03/76.21 36851[43:Spt:36850.2] || -> xuntil6(s12)*. % 76.03/76.21 36852[43:MRR:164.0,36851.0] || -> until5(s13)*. % 76.03/76.21 36853[43:MRR:35595.0,36852.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.03/76.21 36857[44:Spt:36853.2] || -> xuntil6(s13)*. % 76.03/76.21 36858[44:MRR:163.0,36857.0] || -> until5(s14)*. % 76.03/76.21 36859[44:MRR:35591.0,36858.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.03/76.21 36860[45:Spt:36859.2] || -> xuntil6(s14)*. % 76.03/76.21 36861[45:MRR:162.0,36860.0] || -> until5(s15)*. % 76.03/76.21 36862[45:MRR:35587.0,36861.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.03/76.21 36866[46:Spt:36862.2] || -> xuntil6(s15)*. % 76.03/76.21 36867[46:MRR:161.0,36866.0] || -> until5(s16)*. % 76.03/76.21 36868[46:MRR:35586.0,36867.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.03/76.21 36869[47:Spt:36868.2] || -> xuntil6(s16)*. % 76.03/76.21 36870[47:MRR:160.0,36869.0] || -> until5(s17)*. % 76.03/76.21 36871[47:MRR:35579.0,36870.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.03/76.21 36875[48:Spt:36871.2] || -> xuntil6(s17)*. % 76.03/76.21 36876[48:MRR:159.0,36875.0] || -> until5(s18)*. % 76.03/76.21 36877[48:MRR:35575.0,36876.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.03/76.21 36878[49:Spt:36877.2] || -> xuntil6(s18)*. % 76.03/76.21 36879[49:MRR:158.0,36878.0] || -> until5(s19)*. % 76.03/76.21 36880[49:MRR:35571.0,36879.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.03/76.21 36884[50:Spt:36880.2] || -> xuntil6(s19)*. % 76.03/76.21 36885[50:MRR:157.0,36884.0] || -> until5(s20)*. % 76.03/76.21 36886[50:MRR:35567.0,36885.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.03/76.21 36887[51:Spt:36886.2] || -> xuntil6(s20)*. % 76.03/76.21 36888[51:MRR:156.0,36887.0] || -> until5(s21)*. % 76.03/76.21 36889[51:MRR:35566.0,36888.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.03/76.21 36893[52:Spt:36889.2] || -> xuntil6(s21)*. % 76.03/76.21 36894[52:MRR:155.0,36893.0] || -> until5(s22)*. % 76.03/76.21 36895[52:MRR:35559.0,36894.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.03/76.21 36896[53:Spt:36895.2] || -> xuntil6(s22)*. % 76.03/76.21 36897[53:MRR:154.0,36896.0] || -> until5(s23)*. % 76.03/76.21 36898[53:MRR:35555.0,36897.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.03/76.21 36902[54:Spt:36898.2] || -> xuntil6(s23)*. % 76.03/76.21 36903[54:MRR:153.0,36902.0] || -> until5(s24)*. % 76.03/76.21 36904[54:MRR:35551.0,36903.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.03/76.21 36905[55:Spt:36904.2] || -> xuntil6(s24)*. % 76.03/76.21 36906[55:MRR:152.0,36905.0] || -> until5(s25)*. % 76.03/76.21 36907[55:MRR:35550.0,36906.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.03/76.21 36911[56:Spt:36907.2] || -> xuntil6(s25)*. % 76.03/76.21 36912[56:MRR:151.0,36911.0] || -> until5(s26)*. % 76.03/76.21 36913[56:MRR:35549.0,36912.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.03/76.21 36914[57:Spt:36913.2] || -> xuntil6(s26)*. % 76.03/76.21 36915[57:MRR:150.0,36914.0] || -> until5(s27)*. % 76.03/76.21 36916[57:MRR:35548.0,36915.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.03/76.21 36920[58:Spt:36916.2] || -> xuntil6(s27)*. % 76.03/76.21 36921[58:MRR:149.0,36920.0] || -> until5(s28)*. % 76.03/76.21 36922[58:MRR:32361.0,36921.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.03/76.21 36923[59:Spt:36922.2] || -> xuntil6(s28)*. % 76.03/76.21 36924[59:MRR:148.0,36923.0] || -> until5(s29)*. % 76.03/76.21 36925[59:MRR:35647.0,36924.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.03/76.21 36929[60:Spt:36925.1] || -> m_main_v_state(s30,c_busy)*. % 76.03/76.21 36931[60:Res:36929.0,61.1] always3(s30) || -> . % 76.03/76.21 36932[60:SSi:36931.0,719.0] || -> . % 76.03/76.21 36933[60:Spt:36932.0,36925.1,36929.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.03/76.21 36934[60:Spt:36932.0,36925.0,36925.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 76.03/76.21 36936[60:MRR:831.2,36933.0] node4(s29) || m_main_v_state(s29,c_ready)* -> . % 76.03/76.21 36937[60:Res:53.1,36934.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 76.03/76.21 36939[61:Spt:36937.1] || -> xuntil6(s29)*. % 76.03/76.21 36940[61:MRR:147.0,36939.0] || -> until5(s30)*. % 76.03/76.21 36941[61:MRR:32470.0,36940.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.03/76.21 36946[62:Spt:36941.2] || -> xuntil6(s30)*. % 76.03/76.21 36947[62:MRR:146.0,36946.0] || -> until5(s31)*. % 76.03/76.21 36948[62:MRR:35651.0,36947.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.03/76.21 36949[63:Spt:36948.1] || -> m_main_v_state(s32,c_busy)*. % 76.03/76.21 36951[63:Res:36949.0,61.1] always3(s32) || -> . % 76.03/76.21 36952[63:SSi:36951.0,721.0] || -> . % 76.03/76.21 36953[63:Spt:36952.0,36948.1,36949.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.03/76.21 36954[63:Spt:36952.0,36948.0,36948.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.03/76.21 36956[63:MRR:825.2,36953.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.03/76.21 36957[63:Res:53.1,36954.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.03/76.21 36959[64:Spt:36957.1] || -> xuntil6(s31)*. % 76.03/76.21 36960[64:MRR:145.0,36959.0] || -> until5(s32)*. % 76.03/76.21 36961[64:MRR:32474.0,36960.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.03/76.21 36969[65:Spt:36961.2] || -> xuntil6(s32)*. % 76.03/76.21 36970[65:MRR:144.0,36969.0] || -> until5(s33)*. % 76.03/76.21 36971[65:MRR:35655.0,36970.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.03/76.21 36972[66:Spt:36971.1] || -> m_main_v_state(s34,c_busy)*. % 76.03/76.21 36974[66:Res:36972.0,61.1] always3(s34) || -> . % 76.03/76.21 36975[66:SSi:36974.0,723.0] || -> . % 76.03/76.21 36976[66:Spt:36975.0,36971.1,36972.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.03/76.21 36977[66:Spt:36975.0,36971.0,36971.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.03/76.21 36979[66:MRR:819.2,36976.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.03/76.21 36980[66:Res:53.1,36977.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.03/76.21 36985[67:Spt:36980.1] || -> xuntil6(s33)*. % 76.03/76.21 36986[67:MRR:143.0,36985.0] || -> until5(s34)*. % 76.03/76.21 36987[67:MRR:32478.0,36986.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.03/76.21 36989[68:Spt:36987.2] || -> xuntil6(s34)*. % 76.03/76.21 36990[68:MRR:142.0,36989.0] || -> until5(s35)*. % 76.03/76.21 36991[68:MRR:35659.0,36990.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.03/76.21 36992[69:Spt:36991.1] || -> m_main_v_state(s36,c_busy)*. % 76.03/76.21 36994[69:Res:36992.0,61.1] always3(s36) || -> . % 76.03/76.21 36995[69:SSi:36994.0,725.0] || -> . % 76.03/76.21 36996[69:Spt:36995.0,36991.1,36992.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.03/76.21 36997[69:Spt:36995.0,36991.0,36991.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.03/76.21 36999[69:MRR:813.2,36996.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.03/76.21 37000[69:Res:53.1,36997.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.03/76.21 37002[70:Spt:37000.1] || -> xuntil6(s35)*. % 76.03/76.21 37003[70:MRR:141.0,37002.0] || -> until5(s36)*. % 76.03/76.21 37004[70:MRR:32485.0,37003.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.03/76.21 37009[71:Spt:37004.2] || -> xuntil6(s36)*. % 76.03/76.21 37010[71:MRR:140.0,37009.0] || -> until5(s37)*. % 76.03/76.21 37011[71:MRR:35666.0,37010.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.03/76.21 37012[72:Spt:37011.1] || -> m_main_v_state(s38,c_busy)*. % 76.03/76.21 37014[72:Res:37012.0,61.1] always3(s38) || -> . % 76.03/76.21 37015[72:SSi:37014.0,727.0] || -> . % 76.03/76.21 37016[72:Spt:37015.0,37011.1,37012.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.03/76.21 37017[72:Spt:37015.0,37011.0,37011.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.03/76.21 37019[72:MRR:807.2,37016.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.03/76.21 37020[72:Res:53.1,37017.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.03/76.21 37022[73:Spt:37020.1] || -> xuntil6(s37)*. % 76.03/76.21 37023[73:MRR:139.0,37022.0] || -> until5(s38)*. % 76.03/76.21 37024[73:MRR:32486.0,37023.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.03/76.21 37032[74:Spt:37024.2] || -> xuntil6(s38)*. % 76.03/76.21 37033[74:MRR:138.0,37032.0] || -> until5(s39)*. % 76.03/76.21 37034[74:MRR:35667.0,37033.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.03/76.21 37035[75:Spt:37034.1] || -> m_main_v_state(s40,c_busy)*. % 76.03/76.21 37037[75:Res:37035.0,61.1] always3(s40) || -> . % 76.03/76.21 37038[75:SSi:37037.0,729.0] || -> . % 76.03/76.21 37039[75:Spt:37038.0,37034.1,37035.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.03/76.21 37040[75:Spt:37038.0,37034.0,37034.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.03/76.21 37042[75:MRR:801.2,37039.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.03/76.21 37043[75:Res:53.1,37040.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.03/76.21 37048[76:Spt:37043.1] || -> xuntil6(s39)*. % 76.03/76.21 37049[76:MRR:137.0,37048.0] || -> until5(s40)*. % 76.03/76.21 37050[76:MRR:32490.0,37049.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.03/76.21 37052[77:Spt:37050.2] || -> xuntil6(s40)*. % 76.03/76.21 37053[77:MRR:136.0,37052.0] || -> until5(s41)*. % 76.03/76.21 37054[77:MRR:35671.0,37053.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.03/76.21 37055[78:Spt:37054.1] || -> m_main_v_state(s42,c_busy)*. % 76.03/76.21 37057[78:Res:37055.0,61.1] always3(s42) || -> . % 76.03/76.21 37058[78:SSi:37057.0,731.0] || -> . % 76.03/76.21 37059[78:Spt:37058.0,37054.1,37055.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.03/76.21 37060[78:Spt:37058.0,37054.0,37054.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.03/76.21 37062[78:MRR:795.2,37059.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.03/76.21 37063[78:Res:53.1,37060.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.03/76.21 37065[79:Spt:37063.1] || -> xuntil6(s41)*. % 76.03/76.21 37066[79:MRR:135.0,37065.0] || -> until5(s42)*. % 76.03/76.21 37067[79:MRR:32494.0,37066.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.03/76.21 37072[80:Spt:37067.2] || -> xuntil6(s42)*. % 76.03/76.21 37073[80:MRR:134.0,37072.0] || -> until5(s43)*. % 76.03/76.21 37074[80:MRR:35675.0,37073.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.03/76.21 37075[81:Spt:37074.1] || -> m_main_v_state(s44,c_busy)*. % 76.03/76.21 37077[81:Res:37075.0,61.1] always3(s44) || -> . % 76.03/76.21 37078[81:SSi:37077.0,733.0] || -> . % 76.03/76.21 37079[81:Spt:37078.0,37074.1,37075.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.03/76.21 37080[81:Spt:37078.0,37074.0,37074.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.03/76.21 37082[81:MRR:789.2,37079.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.03/76.21 37083[81:Res:53.1,37080.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.03/76.21 37085[82:Spt:37083.1] || -> xuntil6(s43)*. % 76.03/76.21 37086[82:MRR:133.0,37085.0] || -> until5(s44)*. % 76.03/76.21 37087[82:MRR:32498.0,37086.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.03/76.21 37095[83:Spt:37087.2] || -> xuntil6(s44)*. % 76.03/76.21 37096[83:MRR:132.0,37095.0] || -> until5(s45)*. % 76.03/76.21 37097[83:MRR:35679.0,37096.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.03/76.21 37098[84:Spt:37097.1] || -> m_main_v_state(s46,c_busy)*. % 76.03/76.21 37100[84:Res:37098.0,61.1] always3(s46) || -> . % 76.03/76.21 37101[84:SSi:37100.0,735.0] || -> . % 76.03/76.21 37102[84:Spt:37101.0,37097.1,37098.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.03/76.21 37103[84:Spt:37101.0,37097.0,37097.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.03/76.21 37105[84:MRR:783.2,37102.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.03/76.21 37106[84:Res:53.1,37103.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.03/76.21 37111[85:Spt:37106.1] || -> xuntil6(s45)*. % 76.03/76.21 37112[85:MRR:131.0,37111.0] || -> until5(s46)*. % 76.03/76.21 37113[85:MRR:32505.0,37112.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.03/76.21 37115[86:Spt:37113.2] || -> xuntil6(s46)*. % 76.03/76.21 37116[86:MRR:130.0,37115.0] || -> until5(s47)*. % 76.03/76.21 37117[86:MRR:35683.0,37116.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.03/76.21 37118[87:Spt:37117.1] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.21 37120[87:Res:37118.0,61.1] always3(s48) || -> . % 76.03/76.21 37121[87:SSi:37120.0,737.0] || -> . % 76.03/76.21 37122[87:Spt:37121.0,37117.1,37118.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.03/76.21 37123[87:Spt:37121.0,37117.0,37117.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.03/76.21 37125[87:MRR:777.2,37122.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.03/76.21 37126[87:Res:53.1,37123.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.03/76.21 37128[88:Spt:37126.1] || -> xuntil6(s47)*. % 76.03/76.21 37129[88:MRR:129.0,37128.0] || -> until5(s48)*. % 76.03/76.21 37130[88:MRR:32506.0,37129.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.03/76.21 37135[89:Spt:37130.2] || -> xuntil6(s48)*. % 76.03/76.21 37136[89:MRR:128.0,37135.0] || -> until5(s49)*. % 76.03/76.21 37137[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.03/76.21 37141[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.03/76.21 37142[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.03/76.21 37143[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.03/76.21 37144[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.03/76.21 37148[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.03/76.21 37152[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.03/76.21 37159[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.03/76.21 37163[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.03/76.21 37170[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.03/76.21 37171[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.03/76.21 37175[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.03/76.21 37179[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.03/76.21 37183[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.03/76.21 37190[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.03/76.21 37191[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.03/76.21 37195[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.03/76.21 37199[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.03/76.21 37203[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.03/76.21 37210[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.03/76.21 37211[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.03/76.21 37215[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.03/76.21 37219[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.03/76.21 37223[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.03/76.21 37230[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.03/76.21 37231[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.03/76.21 37235[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.03/76.21 37239[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.03/76.21 37241[30:SoR:36799.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)*. % 76.03/76.21 37246[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.03/76.21 37250[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.03/76.21 37254[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.03/76.21 37261[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.03/76.21 37262[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.03/76.21 37266[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.03/76.21 37270[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.03/76.21 37274[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.03/76.21 37281[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.03/76.21 37282[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.03/76.21 37283[30:SoR:37241.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)* xuntil6(s49). % 76.03/76.21 37284[89:SSi:37283.0,50.0,738.0,37136.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s21,c_busy)* xuntil6(s49). % 76.03/76.21 37285[90:Spt:37284.1] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.21 37287[90:Res:37285.0,61.1] always3(s21) || -> . % 76.03/76.21 37288[90:SSi:37287.0,710.0,36888.0,36893.0] || -> . % 76.03/76.21 37289[90:Spt:37288.0,37284.1,37285.0] || m_main_v_state(s21,c_busy)*+ -> . % 76.03/76.21 37290[90:Spt:37288.0,37284.0,37284.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.03/76.21 37294[90:MRR:37241.2,37289.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.03/76.21 37295[90:Res:53.1,37290.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.03/76.21 37297[91:Spt:37295.0] || -> m_main_v_state(s49,c_busy)*. % 76.03/76.21 37299[91:Res:37297.0,61.1] always3(s49) || -> . % 76.03/76.21 37300[91:SSi:37299.0,50.0,738.0,37136.0] || -> . % 76.03/76.21 37301[91:Spt:37300.0,37295.0,37297.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.03/76.21 37302[91:Spt:37300.0,37295.1] || -> xuntil6(s49)*. % 76.03/76.21 37303[91:MRR:36798.0,37302.0] || -> until2p7(s21)*. % 76.03/76.21 37304[91:MRR:217.0,37303.0] || -> until2p7(s22)* node4(s21). % 76.03/76.21 37306[91:MRR:774.2,37301.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.03/76.21 37307[92:Spt:37304.0] || -> until2p7(s22)*. % 76.03/76.21 37308[92:MRR:218.0,37307.0] || -> until2p7(s23)* node4(s22). % 76.03/76.21 37309[93:Spt:37308.0] || -> until2p7(s23)*. % 76.03/76.21 37310[93:MRR:219.0,37309.0] || -> until2p7(s24)* node4(s23). % 76.03/76.21 37311[94:Spt:37310.0] || -> until2p7(s24)*. % 76.03/76.21 37312[94:MRR:220.0,37311.0] || -> until2p7(s25)* node4(s24). % 76.03/76.21 37313[95:Spt:37312.0] || -> until2p7(s25)*. % 76.03/76.21 37314[95:MRR:221.0,37313.0] || -> until2p7(s26)* node4(s25). % 76.03/76.21 37315[96:Spt:37314.0] || -> until2p7(s26)*. % 76.03/76.21 37316[96:MRR:222.0,37315.0] || -> until2p7(s27)* node4(s26). % 76.03/76.21 37317[97:Spt:37316.0] || -> until2p7(s27)*. % 76.03/76.21 37318[97:MRR:223.0,37317.0] || -> until2p7(s28)* node4(s27). % 76.03/76.21 37319[98:Spt:37318.0] || -> until2p7(s28)*. % 76.03/76.21 37320[98:MRR:224.0,37319.0] || -> until2p7(s29)* node4(s28). % 76.03/76.21 37321[99:Spt:37320.0] || -> until2p7(s29)*. % 76.03/76.21 37322[99:MRR:225.0,37321.0] || -> until2p7(s30)* node4(s29). % 76.03/76.21 37323[100:Spt:37322.0] || -> until2p7(s30)*. % 76.03/76.21 37324[100:MRR:226.0,37323.0] || -> until2p7(s31)* node4(s30). % 76.03/76.21 37325[101:Spt:37324.0] || -> until2p7(s31)*. % 76.03/76.21 37326[101:MRR:227.0,37325.0] || -> until2p7(s32)* node4(s31). % 76.03/76.21 37327[102:Spt:37326.0] || -> until2p7(s32)*. % 76.03/76.21 37328[102:MRR:228.0,37327.0] || -> until2p7(s33)* node4(s32). % 76.03/76.21 37329[103:Spt:37328.0] || -> until2p7(s33)*. % 76.03/76.21 37330[103:MRR:229.0,37329.0] || -> until2p7(s34)* node4(s33). % 76.03/76.21 37331[104:Spt:37330.0] || -> until2p7(s34)*. % 76.03/76.21 37332[104:MRR:230.0,37331.0] || -> until2p7(s35)* node4(s34). % 76.03/76.21 37333[105:Spt:37332.0] || -> until2p7(s35)*. % 76.03/76.21 37334[105:MRR:231.0,37333.0] || -> until2p7(s36)* node4(s35). % 76.03/76.21 37335[106:Spt:37334.0] || -> until2p7(s36)*. % 76.03/76.21 37336[106:MRR:232.0,37335.0] || -> until2p7(s37)* node4(s36). % 76.03/76.21 37337[107:Spt:37336.0] || -> until2p7(s37)*. % 76.03/76.21 37338[107:MRR:235.0,37337.0] || -> until2p7(s38)* node4(s37). % 76.03/76.21 37339[108:Spt:37338.0] || -> until2p7(s38)*. % 76.03/76.21 37340[108:MRR:236.0,37339.0] || -> until2p7(s39)* node4(s38). % 76.03/76.21 37341[109:Spt:37340.0] || -> until2p7(s39)*. % 76.03/76.21 37342[109:MRR:237.0,37341.0] || -> until2p7(s40)* node4(s39). % 76.03/76.21 37343[110:Spt:37342.0] || -> until2p7(s40)*. % 76.03/76.21 37344[110:MRR:238.0,37343.0] || -> until2p7(s41)* node4(s40). % 76.03/76.21 37345[111:Spt:37344.0] || -> until2p7(s41)*. % 76.03/76.21 37346[111:MRR:239.0,37345.0] || -> until2p7(s42)* node4(s41). % 76.03/76.21 37347[112:Spt:37346.0] || -> until2p7(s42)*. % 76.03/76.21 37348[112:MRR:240.0,37347.0] || -> until2p7(s43)* node4(s42). % 76.03/76.21 37349[113:Spt:37348.0] || -> until2p7(s43)*. % 76.03/76.21 37350[113:MRR:241.0,37349.0] || -> until2p7(s44)* node4(s43). % 76.03/76.21 37351[114:Spt:37350.0] || -> until2p7(s44)*. % 76.03/76.21 37352[114:MRR:539.0,37351.0] || -> until2p7(s45)* node4(s44). % 76.03/76.21 37353[115:Spt:37352.0] || -> until2p7(s45)*. % 76.03/76.21 37354[115:MRR:544.0,37353.0] || -> until2p7(s46)* node4(s45). % 76.03/76.21 37355[116:Spt:37354.0] || -> until2p7(s46)*. % 76.03/76.21 37356[116:MRR:549.0,37355.0] || -> until2p7(s47)* node4(s46). % 76.03/76.21 37357[117:Spt:37356.0] || -> until2p7(s47)*. % 76.03/76.21 37358[117:MRR:554.0,37357.0] || -> until2p7(s48)* node4(s47). % 76.03/76.21 37359[118:Spt:37358.0] || -> until2p7(s48)*. % 76.03/76.21 37360[118:MRR:559.0,37359.0] || -> until2p7(s49)* node4(s48). % 76.03/76.21 37361[119:Spt:37360.0] || -> until2p7(s49)*. % 76.03/76.21 37362[119:MRR:194.0,37361.0] || -> node4(s49)*. % 76.03/76.21 37363[119:MRR:37294.0,37362.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.03/76.21 37364[119:Res:53.1,37363.0] || -> m_main_v_state(s49,c_busy)*. % 76.03/76.21 37366[119:MRR:37364.0,37301.0] || -> . % 76.03/76.21 37367[119:Spt:37366.0,37360.0,37361.0] || until2p7(s49)*+ -> . % 76.03/76.21 37368[119:Spt:37366.0,37360.1] || -> node4(s48)*. % 76.03/76.21 37369[119:MRR:37306.0,37368.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.03/76.21 37372[119:Res:53.1,37369.0] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.21 37374[119:MRR:37372.0,37122.0] || -> . % 76.03/76.21 37375[118:Spt:37374.0,37358.0,37359.0] || until2p7(s48)*+ -> . % 76.03/76.21 37376[118:Spt:37374.0,37358.1] || -> node4(s47)*. % 76.03/76.21 37377[118:MRR:37125.0,37376.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.03/76.21 37380[118:Res:53.1,37377.0] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.21 37383[118:Res:37380.0,61.1] always3(s47) || -> . % 76.03/76.21 37384[118:SSi:37383.0,736.0,37116.0,37128.0,37357.0,37376.0] || -> . % 76.03/76.21 37385[117:Spt:37384.0,37356.0,37357.0] || until2p7(s47)*+ -> . % 76.03/76.21 37386[117:Spt:37384.0,37356.1] || -> node4(s46)*. % 76.03/76.21 37388[117:MRR:780.0,37386.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.03/76.21 37408[117:Res:53.1,37388.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.03/76.21 37410[117:MRR:37408.0,37102.0] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.21 37412[117:Res:37410.0,61.1] always3(s47) || -> . % 76.03/76.21 37413[117:SSi:37412.0,736.0,37116.0,37128.0] || -> . % 76.03/76.21 37414[116:Spt:37413.0,37354.0,37355.0] || until2p7(s46)*+ -> . % 76.03/76.21 37415[116:Spt:37413.0,37354.1] || -> node4(s45)*. % 76.03/76.21 37416[116:MRR:37105.0,37415.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.03/76.21 37420[116:Res:53.1,37416.0] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.21 37423[116:Res:37420.0,61.1] always3(s45) || -> . % 76.03/76.21 37424[116:SSi:37423.0,734.0,37096.0,37111.0,37353.0,37415.0] || -> . % 76.03/76.21 37425[115:Spt:37424.0,37352.0,37353.0] || until2p7(s45)*+ -> . % 76.03/76.21 37426[115:Spt:37424.0,37352.1] || -> node4(s44)*. % 76.03/76.21 37428[115:MRR:786.0,37426.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.03/76.21 37439[115:Res:53.1,37428.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.03/76.21 37441[115:MRR:37439.0,37079.0] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.21 37443[115:Res:37441.0,61.1] always3(s45) || -> . % 76.03/76.21 37444[115:SSi:37443.0,734.0,37096.0,37111.0] || -> . % 76.03/76.21 37445[114:Spt:37444.0,37350.0,37351.0] || until2p7(s44)*+ -> . % 76.03/76.21 37446[114:Spt:37444.0,37350.1] || -> node4(s43)*. % 76.03/76.21 37447[114:MRR:37082.0,37446.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.03/76.21 37450[114:Res:53.1,37447.0] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.21 37453[114:Res:37450.0,61.1] always3(s43) || -> . % 76.03/76.21 37454[114:SSi:37453.0,732.0,37073.0,37085.0,37349.0,37446.0] || -> . % 76.03/76.21 37455[113:Spt:37454.0,37348.0,37349.0] || until2p7(s43)*+ -> . % 76.03/76.21 37456[113:Spt:37454.0,37348.1] || -> node4(s42)*. % 76.03/76.21 37458[113:MRR:792.0,37456.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.03/76.21 37470[113:Res:53.1,37458.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.03/76.21 37472[113:MRR:37470.0,37059.0] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.21 37474[113:Res:37472.0,61.1] always3(s43) || -> . % 76.03/76.21 37475[113:SSi:37474.0,732.0,37073.0,37085.0] || -> . % 76.03/76.21 37476[112:Spt:37475.0,37346.0,37347.0] || until2p7(s42)*+ -> . % 76.03/76.21 37477[112:Spt:37475.0,37346.1] || -> node4(s41)*. % 76.03/76.21 37478[112:MRR:37062.0,37477.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.03/76.21 37481[112:Res:53.1,37478.0] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.21 37484[112:Res:37481.0,61.1] always3(s41) || -> . % 76.03/76.21 37485[112:SSi:37484.0,730.0,37053.0,37065.0,37345.0,37477.0] || -> . % 76.03/76.21 37486[111:Spt:37485.0,37344.0,37345.0] || until2p7(s41)*+ -> . % 76.03/76.21 37487[111:Spt:37485.0,37344.1] || -> node4(s40)*. % 76.03/76.21 37489[111:MRR:798.0,37487.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.03/76.21 37501[111:Res:53.1,37489.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.03/76.21 37503[111:MRR:37501.0,37039.0] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.21 37508[111:Res:37503.0,61.1] always3(s41) || -> . % 76.03/76.21 37509[111:SSi:37508.0,730.0,37053.0,37065.0] || -> . % 76.03/76.21 37510[110:Spt:37509.0,37342.0,37343.0] || until2p7(s40)*+ -> . % 76.03/76.21 37511[110:Spt:37509.0,37342.1] || -> node4(s39)*. % 76.03/76.21 37512[110:MRR:37042.0,37511.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.03/76.21 37515[110:Res:53.1,37512.0] || -> m_main_v_state(s39,c_busy)*. % 76.03/76.21 37519[110:Res:37515.0,61.1] always3(s39) || -> . % 76.03/76.21 37520[110:SSi:37519.0,728.0,37033.0,37048.0,37341.0,37511.0] || -> . % 76.03/76.21 37521[109:Spt:37520.0,37340.0,37341.0] || until2p7(s39)*+ -> . % 76.03/76.21 37522[109:Spt:37520.0,37340.1] || -> node4(s38)*. % 76.03/76.21 37524[109:MRR:804.0,37522.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.03/76.21 37535[109:Res:53.1,37524.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.03/76.21 37537[109:MRR:37535.0,37016.0] || -> m_main_v_state(s39,c_busy)*. % 76.03/76.21 37539[109:Res:37537.0,61.1] always3(s39) || -> . % 76.03/76.21 37540[109:SSi:37539.0,728.0,37033.0,37048.0] || -> . % 76.03/76.21 37541[108:Spt:37540.0,37338.0,37339.0] || until2p7(s38)*+ -> . % 76.03/76.21 37542[108:Spt:37540.0,37338.1] || -> node4(s37)*. % 76.03/76.21 37543[108:MRR:37019.0,37542.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.03/76.21 37547[108:Res:53.1,37543.0] || -> m_main_v_state(s37,c_busy)*. % 76.03/76.21 37550[108:Res:37547.0,61.1] always3(s37) || -> . % 76.03/76.21 37551[108:SSi:37550.0,726.0,37010.0,37022.0,37337.0,37542.0] || -> . % 76.03/76.21 37552[107:Spt:37551.0,37336.0,37337.0] || until2p7(s37)*+ -> . % 76.03/76.21 37553[107:Spt:37551.0,37336.1] || -> node4(s36)*. % 76.03/76.21 37555[107:MRR:810.0,37553.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.03/76.21 37566[107:Res:53.1,37555.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.03/76.21 37568[107:MRR:37566.0,36996.0] || -> m_main_v_state(s37,c_busy)*. % 76.03/76.21 37570[107:Res:37568.0,61.1] always3(s37) || -> . % 76.03/76.21 37571[107:SSi:37570.0,726.0,37010.0,37022.0] || -> . % 76.03/76.21 37572[106:Spt:37571.0,37334.0,37335.0] || until2p7(s36)*+ -> . % 76.03/76.21 37573[106:Spt:37571.0,37334.1] || -> node4(s35)*. % 76.03/76.21 37574[106:MRR:36999.0,37573.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.03/76.21 37577[106:Res:53.1,37574.0] || -> m_main_v_state(s35,c_busy)*. % 76.03/76.21 37580[106:Res:37577.0,61.1] always3(s35) || -> . % 76.03/76.21 37581[106:SSi:37580.0,724.0,36990.0,37002.0,37333.0,37573.0] || -> . % 76.03/76.21 37582[105:Spt:37581.0,37332.0,37333.0] || until2p7(s35)*+ -> . % 76.03/76.21 37583[105:Spt:37581.0,37332.1] || -> node4(s34)*. % 76.03/76.21 37585[105:MRR:816.0,37583.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.03/76.21 37597[105:Res:53.1,37585.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.03/76.21 37599[105:MRR:37597.0,36976.0] || -> m_main_v_state(s35,c_busy)*. % 76.03/76.21 37601[105:Res:37599.0,61.1] always3(s35) || -> . % 76.03/76.21 37602[105:SSi:37601.0,724.0,36990.0,37002.0] || -> . % 76.03/76.21 37603[104:Spt:37602.0,37330.0,37331.0] || until2p7(s34)*+ -> . % 76.03/76.21 37604[104:Spt:37602.0,37330.1] || -> node4(s33)*. % 76.03/76.21 37605[104:MRR:36979.0,37604.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.03/76.21 37608[104:Res:53.1,37605.0] || -> m_main_v_state(s33,c_busy)*. % 76.03/76.21 37611[104:Res:37608.0,61.1] always3(s33) || -> . % 76.03/76.21 37612[104:SSi:37611.0,722.0,36970.0,36985.0,37329.0,37604.0] || -> . % 76.03/76.21 37613[103:Spt:37612.0,37328.0,37329.0] || until2p7(s33)*+ -> . % 76.03/76.21 37614[103:Spt:37612.0,37328.1] || -> node4(s32)*. % 76.03/76.21 37616[103:MRR:822.0,37614.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.03/76.21 37628[103:Res:53.1,37616.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.03/76.21 37630[103:MRR:37628.0,36953.0] || -> m_main_v_state(s33,c_busy)*. % 76.03/76.21 37635[103:Res:37630.0,61.1] always3(s33) || -> . % 76.03/76.21 37636[103:SSi:37635.0,722.0,36970.0,36985.0] || -> . % 76.03/76.21 37637[102:Spt:37636.0,37326.0,37327.0] || until2p7(s32)*+ -> . % 76.03/76.21 37638[102:Spt:37636.0,37326.1] || -> node4(s31)*. % 76.03/76.21 37639[102:MRR:36956.0,37638.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.03/76.21 37642[102:Res:53.1,37639.0] || -> m_main_v_state(s31,c_busy)*. % 76.03/76.21 37646[102:Res:37642.0,61.1] always3(s31) || -> . % 76.03/76.21 37647[102:SSi:37646.0,720.0,36947.0,36959.0,37325.0,37638.0] || -> . % 76.03/76.21 37648[101:Spt:37647.0,37324.0,37325.0] || until2p7(s31)*+ -> . % 76.03/76.21 37649[101:Spt:37647.0,37324.1] || -> node4(s30)*. % 76.03/76.21 37651[101:MRR:828.0,37649.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.03/76.21 37662[101:Res:53.1,37651.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.03/76.21 37664[101:MRR:37662.0,36933.0] || -> m_main_v_state(s31,c_busy)*. % 76.03/76.21 37666[101:Res:37664.0,61.1] always3(s31) || -> . % 76.03/76.21 37667[101:SSi:37666.0,720.0,36947.0,36959.0] || -> . % 76.03/76.21 37668[100:Spt:37667.0,37322.0,37323.0] || until2p7(s30)*+ -> . % 76.03/76.21 37669[100:Spt:37667.0,37322.1] || -> node4(s29)*. % 76.03/76.21 37670[100:MRR:36936.0,37669.0] || m_main_v_state(s29,c_ready)*+ -> . % 76.03/76.21 37674[100:Res:53.1,37670.0] || -> m_main_v_state(s29,c_busy)*. % 76.03/76.21 37677[100:Res:37674.0,61.1] always3(s29) || -> . % 76.03/76.21 37678[100:SSi:37677.0,718.0,36924.0,36939.0,37321.0,37669.0] || -> . % 76.03/76.21 37679[99:Spt:37678.0,37320.0,37321.0] || until2p7(s29)*+ -> . % 76.03/76.21 37680[99:Spt:37678.0,37320.1] || -> node4(s28)*. % 76.03/76.21 37682[99:MRR:834.0,37680.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.03/76.21 37693[99:Res:53.1,37682.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.03/76.21 37695[100:Spt:37693.0] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.21 37697[100:Res:37695.0,61.1] always3(s28) || -> . % 76.03/76.21 37698[100:SSi:37697.0,717.0,36921.0,36923.0,37319.0,37680.0] || -> . % 76.03/76.21 37699[100:Spt:37698.0,37693.0,37695.0] || m_main_v_state(s28,c_busy)* -> . % 76.03/76.21 37700[100:Spt:37698.0,37693.1] || -> m_main_v_state(s29,c_busy)*. % 76.03/76.21 37704[100:Res:37700.0,61.1] always3(s29) || -> . % 76.03/76.21 37705[100:SSi:37704.0,718.0,36924.0,36939.0] || -> . % 76.03/76.21 37706[98:Spt:37705.0,37318.0,37319.0] || until2p7(s28)*+ -> . % 76.03/76.21 37707[98:Spt:37705.0,37318.1] || -> node4(s27)*. % 76.03/76.21 37709[98:MRR:837.0,37707.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.03/76.21 37719[98:Res:53.1,37709.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.03/76.21 37721[99:Spt:37719.0] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.21 37723[99:Res:37721.0,61.1] always3(s27) || -> . % 76.03/76.21 37724[99:SSi:37723.0,716.0,36915.0,36920.0,37317.0,37707.0] || -> . % 76.03/76.21 37725[99:Spt:37724.0,37719.0,37721.0] || m_main_v_state(s27,c_busy)* -> . % 76.03/76.21 37726[99:Spt:37724.0,37719.1] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.21 37730[99:Res:37726.0,61.1] always3(s28) || -> . % 76.03/76.21 37731[99:SSi:37730.0,717.0,36921.0,36923.0] || -> . % 76.03/76.21 37732[97:Spt:37731.0,37316.0,37317.0] || until2p7(s27)*+ -> . % 76.03/76.21 37733[97:Spt:37731.0,37316.1] || -> node4(s26)*. % 76.03/76.21 37735[97:MRR:840.0,37733.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.03/76.21 37738[97:Res:53.1,37735.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.03/76.21 37740[98:Spt:37738.0] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.21 37742[98:Res:37740.0,61.1] always3(s26) || -> . % 76.03/76.21 37743[98:SSi:37742.0,715.0,36912.0,36914.0,37315.0,37733.0] || -> . % 76.03/76.21 37744[98:Spt:37743.0,37738.0,37740.0] || m_main_v_state(s26,c_busy)* -> . % 76.03/76.21 37745[98:Spt:37743.0,37738.1] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.21 37749[98:Res:37745.0,61.1] always3(s27) || -> . % 76.03/76.21 37750[98:SSi:37749.0,716.0,36915.0,36920.0] || -> . % 76.03/76.21 37751[96:Spt:37750.0,37314.0,37315.0] || until2p7(s26)*+ -> . % 76.03/76.21 37752[96:Spt:37750.0,37314.1] || -> node4(s25)*. % 76.03/76.21 37754[96:MRR:843.0,37752.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.03/76.21 37757[96:Res:53.1,37754.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.03/76.21 37759[97:Spt:37757.0] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.21 37761[97:Res:37759.0,61.1] always3(s25) || -> . % 76.03/76.21 37762[97:SSi:37761.0,714.0,36906.0,36911.0,37313.0,37752.0] || -> . % 76.03/76.21 37763[97:Spt:37762.0,37757.0,37759.0] || m_main_v_state(s25,c_busy)* -> . % 76.03/76.21 37764[97:Spt:37762.0,37757.1] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.21 37768[97:Res:37764.0,61.1] always3(s26) || -> . % 76.03/76.21 37769[97:SSi:37768.0,715.0,36912.0,36914.0] || -> . % 76.03/76.21 37770[95:Spt:37769.0,37312.0,37313.0] || until2p7(s25)*+ -> . % 76.03/76.21 37771[95:Spt:37769.0,37312.1] || -> node4(s24)*. % 76.03/76.21 37773[95:MRR:846.0,37771.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.03/76.21 37776[95:Res:53.1,37773.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.03/76.21 37781[96:Spt:37776.0] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.21 37783[96:Res:37781.0,61.1] always3(s24) || -> . % 76.03/76.21 37784[96:SSi:37783.0,713.0,36903.0,36905.0,37311.0,37771.0] || -> . % 76.03/76.21 37785[96:Spt:37784.0,37776.0,37781.0] || m_main_v_state(s24,c_busy)* -> . % 76.03/76.21 37786[96:Spt:37784.0,37776.1] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.21 37790[96:Res:37786.0,61.1] always3(s25) || -> . % 76.03/76.21 37791[96:SSi:37790.0,714.0,36906.0,36911.0] || -> . % 76.03/76.21 37792[94:Spt:37791.0,37310.0,37311.0] || until2p7(s24)*+ -> . % 76.03/76.21 37793[94:Spt:37791.0,37310.1] || -> node4(s23)*. % 76.03/76.21 37795[94:MRR:849.0,37793.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.03/76.21 37798[94:Res:53.1,37795.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.03/76.21 37800[95:Spt:37798.0] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.21 37802[95:Res:37800.0,61.1] always3(s23) || -> . % 76.03/76.21 37803[95:SSi:37802.0,712.0,36897.0,36902.0,37309.0,37793.0] || -> . % 76.03/76.21 37804[95:Spt:37803.0,37798.0,37800.0] || m_main_v_state(s23,c_busy)* -> . % 76.03/76.21 37805[95:Spt:37803.0,37798.1] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.21 37809[95:Res:37805.0,61.1] always3(s24) || -> . % 76.03/76.21 37810[95:SSi:37809.0,713.0,36903.0,36905.0] || -> . % 76.03/76.21 37811[93:Spt:37810.0,37308.0,37309.0] || until2p7(s23)*+ -> . % 76.03/76.21 37812[93:Spt:37810.0,37308.1] || -> node4(s22)*. % 76.03/76.21 37814[93:MRR:852.0,37812.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.03/76.21 37817[93:Res:53.1,37814.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.03/76.21 37819[94:Spt:37817.0] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.21 37821[94:Res:37819.0,61.1] always3(s22) || -> . % 76.03/76.21 37822[94:SSi:37821.0,711.0,36894.0,36896.0,37307.0,37812.0] || -> . % 76.03/76.21 37823[94:Spt:37822.0,37817.0,37819.0] || m_main_v_state(s22,c_busy)* -> . % 76.03/76.21 37824[94:Spt:37822.0,37817.1] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.21 37828[94:Res:37824.0,61.1] always3(s23) || -> . % 76.03/76.21 37829[94:SSi:37828.0,712.0,36897.0,36902.0] || -> . % 76.03/76.21 37830[92:Spt:37829.0,37304.0,37307.0] || until2p7(s22)*+ -> . % 76.03/76.21 37831[92:Spt:37829.0,37304.1] || -> node4(s21)*. % 76.03/76.21 37833[92:MRR:855.0,37831.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.03/76.21 37836[92:Res:53.1,37833.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.03/76.21 37838[92:MRR:37836.0,37289.0] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.21 37840[92:Res:37838.0,61.1] always3(s22) || -> . % 76.03/76.21 37841[92:SSi:37840.0,711.0,36894.0,36896.0] || -> . % 76.03/76.21 37842[89:Spt:37841.0,37130.2,37135.0] || xuntil6(s48)*+ -> . % 76.03/76.21 37843[89:Spt:37841.0,37130.0,37130.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.03/76.21 37844[89:Res:53.1,37843.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.03/76.21 37846[89:MRR:37844.0,37122.0] || -> m_main_v_state(s49,c_busy)*. % 76.03/76.21 37848[89:Res:37846.0,61.1] always3(s49) || -> . % 76.03/76.21 37849[89:SSi:37848.0,50.0,738.0] || -> . % 76.03/76.21 37850[88:Spt:37849.0,37126.1,37128.0] || xuntil6(s47)* -> . % 76.03/76.21 37851[88:Spt:37849.0,37126.0] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.21 37854[88:Res:37851.0,61.1] always3(s47) || -> . % 76.03/76.21 37855[88:SSi:37854.0,736.0,37116.0] || -> . % 76.03/76.21 37856[86:Spt:37855.0,37113.2,37115.0] || xuntil6(s46)*+ -> . % 76.03/76.21 37857[86:Spt:37855.0,37113.0,37113.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.03/76.21 37858[86:Res:53.1,37857.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.03/76.21 37860[86:MRR:37858.0,37102.0] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.21 37862[86:Res:37860.0,61.1] always3(s47) || -> . % 76.03/76.21 37863[86:SSi:37862.0,736.0] || -> . % 76.03/76.21 37864[85:Spt:37863.0,37106.1,37111.0] || xuntil6(s45)* -> . % 76.03/76.21 37865[85:Spt:37863.0,37106.0] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.21 37868[85:Res:37865.0,61.1] always3(s45) || -> . % 76.03/76.21 37869[85:SSi:37868.0,734.0,37096.0] || -> . % 76.03/76.21 37870[83:Spt:37869.0,37087.2,37095.0] || xuntil6(s44)*+ -> . % 76.03/76.21 37871[83:Spt:37869.0,37087.0,37087.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.03/76.21 37872[83:Res:53.1,37871.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.03/76.21 37874[83:MRR:37872.0,37079.0] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.21 37877[83:Res:37874.0,61.1] always3(s45) || -> . % 76.03/76.21 37878[83:SSi:37877.0,734.0] || -> . % 76.03/76.21 37879[82:Spt:37878.0,37083.1,37085.0] || xuntil6(s43)* -> . % 76.03/76.21 37880[82:Spt:37878.0,37083.0] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.21 37883[82:Res:37880.0,61.1] always3(s43) || -> . % 76.03/76.21 37884[82:SSi:37883.0,732.0,37073.0] || -> . % 76.03/76.21 37885[80:Spt:37884.0,37067.2,37072.0] || xuntil6(s42)*+ -> . % 76.03/76.21 37886[80:Spt:37884.0,37067.0,37067.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.03/76.21 37887[80:Res:53.1,37886.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.03/76.21 37889[80:MRR:37887.0,37059.0] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.21 37891[80:Res:37889.0,61.1] always3(s43) || -> . % 76.03/76.21 37892[80:SSi:37891.0,732.0] || -> . % 76.03/76.21 37893[79:Spt:37892.0,37063.1,37065.0] || xuntil6(s41)* -> . % 76.03/76.21 37894[79:Spt:37892.0,37063.0] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.21 37897[79:Res:37894.0,61.1] always3(s41) || -> . % 76.03/76.21 37898[79:SSi:37897.0,730.0,37053.0] || -> . % 76.03/76.21 37899[77:Spt:37898.0,37050.2,37052.0] || xuntil6(s40)*+ -> . % 76.03/76.21 37900[77:Spt:37898.0,37050.0,37050.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.03/76.21 37901[77:Res:53.1,37900.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.03/76.21 37903[77:MRR:37901.0,37039.0] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.21 37906[77:Res:37903.0,61.1] always3(s41) || -> . % 76.03/76.21 37907[77:SSi:37906.0,730.0] || -> . % 76.03/76.21 37908[76:Spt:37907.0,37043.1,37048.0] || xuntil6(s39)* -> . % 76.03/76.21 37909[76:Spt:37907.0,37043.0] || -> m_main_v_state(s39,c_busy)*. % 76.03/76.21 37912[76:Res:37909.0,61.1] always3(s39) || -> . % 76.03/76.21 37913[76:SSi:37912.0,728.0,37033.0] || -> . % 76.03/76.21 37914[74:Spt:37913.0,37024.2,37032.0] || xuntil6(s38)*+ -> . % 76.03/76.21 37915[74:Spt:37913.0,37024.0,37024.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.03/76.21 37916[74:Res:53.1,37915.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.03/76.21 37918[74:MRR:37916.0,37016.0] || -> m_main_v_state(s39,c_busy)*. % 76.03/76.21 37920[74:Res:37918.0,61.1] always3(s39) || -> . % 76.03/76.21 37921[74:SSi:37920.0,728.0] || -> . % 76.03/76.21 37922[73:Spt:37921.0,37020.1,37022.0] || xuntil6(s37)* -> . % 76.03/76.21 37923[73:Spt:37921.0,37020.0] || -> m_main_v_state(s37,c_busy)*. % 76.03/76.21 37926[73:Res:37923.0,61.1] always3(s37) || -> . % 76.03/76.21 37927[73:SSi:37926.0,726.0,37010.0] || -> . % 76.03/76.21 37928[71:Spt:37927.0,37004.2,37009.0] || xuntil6(s36)*+ -> . % 76.03/76.21 37929[71:Spt:37927.0,37004.0,37004.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.03/76.21 37930[71:Res:53.1,37929.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.03/76.21 37932[71:MRR:37930.0,36996.0] || -> m_main_v_state(s37,c_busy)*. % 76.03/76.21 37934[71:Res:37932.0,61.1] always3(s37) || -> . % 76.03/76.21 37935[71:SSi:37934.0,726.0] || -> . % 76.03/76.21 37936[70:Spt:37935.0,37000.1,37002.0] || xuntil6(s35)* -> . % 76.03/76.21 37937[70:Spt:37935.0,37000.0] || -> m_main_v_state(s35,c_busy)*. % 76.03/76.21 37940[70:Res:37937.0,61.1] always3(s35) || -> . % 76.03/76.21 37941[70:SSi:37940.0,724.0,36990.0] || -> . % 76.03/76.21 37942[68:Spt:37941.0,36987.2,36989.0] || xuntil6(s34)*+ -> . % 76.03/76.21 37943[68:Spt:37941.0,36987.0,36987.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.03/76.21 37944[68:Res:53.1,37943.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.03/76.21 37946[68:MRR:37944.0,36976.0] || -> m_main_v_state(s35,c_busy)*. % 76.03/76.21 37948[68:Res:37946.0,61.1] always3(s35) || -> . % 76.03/76.21 37949[68:SSi:37948.0,724.0] || -> . % 76.03/76.21 37950[67:Spt:37949.0,36980.1,36985.0] || xuntil6(s33)* -> . % 76.03/76.21 37951[67:Spt:37949.0,36980.0] || -> m_main_v_state(s33,c_busy)*. % 76.03/76.21 37954[67:Res:37951.0,61.1] always3(s33) || -> . % 76.03/76.21 37955[67:SSi:37954.0,722.0,36970.0] || -> . % 76.03/76.21 37956[65:Spt:37955.0,36961.2,36969.0] || xuntil6(s32)*+ -> . % 76.03/76.21 37957[65:Spt:37955.0,36961.0,36961.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.03/76.21 37958[65:Res:53.1,37957.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.03/76.21 37960[65:MRR:37958.0,36953.0] || -> m_main_v_state(s33,c_busy)*. % 76.03/76.21 37962[65:Res:37960.0,61.1] always3(s33) || -> . % 76.03/76.21 37963[65:SSi:37962.0,722.0] || -> . % 76.03/76.21 37964[64:Spt:37963.0,36957.1,36959.0] || xuntil6(s31)* -> . % 76.03/76.21 37965[64:Spt:37963.0,36957.0] || -> m_main_v_state(s31,c_busy)*. % 76.03/76.21 37968[64:Res:37965.0,61.1] always3(s31) || -> . % 76.03/76.21 37969[64:SSi:37968.0,720.0,36947.0] || -> . % 76.03/76.21 37970[62:Spt:37969.0,36941.2,36946.0] || xuntil6(s30)*+ -> . % 76.03/76.21 37971[62:Spt:37969.0,36941.0,36941.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.03/76.21 37972[62:Res:53.1,37971.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.03/76.21 37974[62:MRR:37972.0,36933.0] || -> m_main_v_state(s31,c_busy)*. % 76.03/76.21 37976[62:Res:37974.0,61.1] always3(s31) || -> . % 76.03/76.21 37977[62:SSi:37976.0,720.0] || -> . % 76.03/76.21 37978[61:Spt:37977.0,36937.1,36939.0] || xuntil6(s29)* -> . % 76.03/76.21 37979[61:Spt:37977.0,36937.0] || -> m_main_v_state(s29,c_busy)*. % 76.03/76.21 37982[61:Res:37979.0,61.1] always3(s29) || -> . % 76.03/76.21 37983[61:SSi:37982.0,718.0,36924.0] || -> . % 76.03/76.21 37984[59:Spt:37983.0,36922.2,36923.0] || xuntil6(s28)*+ -> . % 76.03/76.21 37985[59:Spt:37983.0,36922.0,36922.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.03/76.21 37986[59:Res:53.1,37985.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.03/76.21 37988[60:Spt:37986.1] || -> m_main_v_state(s29,c_busy)*. % 76.03/76.21 37990[60:Res:37988.0,61.1] always3(s29) || -> . % 76.03/76.21 37991[60:SSi:37990.0,718.0] || -> . % 76.03/76.21 37992[60:Spt:37991.0,37986.1,37988.0] || m_main_v_state(s29,c_busy)* -> . % 76.03/76.21 37993[60:Spt:37991.0,37986.0] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.21 37996[60:Res:37993.0,61.1] always3(s28) || -> . % 76.03/76.21 37997[60:SSi:37996.0,717.0,36921.0] || -> . % 76.03/76.21 37998[58:Spt:37997.0,36916.2,36920.0] || xuntil6(s27)*+ -> . % 76.03/76.21 37999[58:Spt:37997.0,36916.0,36916.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.03/76.21 38000[58:Res:53.1,37999.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.03/76.21 38002[59:Spt:38000.1] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.21 38004[59:Res:38002.0,61.1] always3(s28) || -> . % 76.03/76.21 38005[59:SSi:38004.0,717.0] || -> . % 76.03/76.21 38006[59:Spt:38005.0,38000.1,38002.0] || m_main_v_state(s28,c_busy)* -> . % 76.03/76.21 38007[59:Spt:38005.0,38000.0] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.21 38010[59:Res:38007.0,61.1] always3(s27) || -> . % 76.03/76.21 38011[59:SSi:38010.0,716.0,36915.0] || -> . % 76.03/76.21 38012[57:Spt:38011.0,36913.2,36914.0] || xuntil6(s26)*+ -> . % 76.03/76.21 38013[57:Spt:38011.0,36913.0,36913.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.03/76.21 38014[57:Res:53.1,38013.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.03/76.21 38016[58:Spt:38014.1] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.21 38018[58:Res:38016.0,61.1] always3(s27) || -> . % 76.03/76.21 38019[58:SSi:38018.0,716.0] || -> . % 76.03/76.21 38020[58:Spt:38019.0,38014.1,38016.0] || m_main_v_state(s27,c_busy)* -> . % 76.03/76.21 38021[58:Spt:38019.0,38014.0] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.21 38024[58:Res:38021.0,61.1] always3(s26) || -> . % 76.03/76.21 38025[58:SSi:38024.0,715.0,36912.0] || -> . % 76.03/76.21 38026[56:Spt:38025.0,36907.2,36911.0] || xuntil6(s25)*+ -> . % 76.03/76.21 38027[56:Spt:38025.0,36907.0,36907.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.03/76.21 38028[56:Res:53.1,38027.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.03/76.21 38030[57:Spt:38028.1] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.21 38032[57:Res:38030.0,61.1] always3(s26) || -> . % 76.03/76.21 38033[57:SSi:38032.0,715.0] || -> . % 76.03/76.21 38034[57:Spt:38033.0,38028.1,38030.0] || m_main_v_state(s26,c_busy)* -> . % 76.03/76.21 38035[57:Spt:38033.0,38028.0] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.21 38038[57:Res:38035.0,61.1] always3(s25) || -> . % 76.03/76.21 38039[57:SSi:38038.0,714.0,36906.0] || -> . % 76.03/76.21 38040[55:Spt:38039.0,36904.2,36905.0] || xuntil6(s24)*+ -> . % 76.03/76.21 38041[55:Spt:38039.0,36904.0,36904.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.03/76.21 38042[55:Res:53.1,38041.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.03/76.21 38044[56:Spt:38042.1] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.21 38046[56:Res:38044.0,61.1] always3(s25) || -> . % 76.03/76.21 38047[56:SSi:38046.0,714.0] || -> . % 76.03/76.21 38048[56:Spt:38047.0,38042.1,38044.0] || m_main_v_state(s25,c_busy)* -> . % 76.03/76.21 38049[56:Spt:38047.0,38042.0] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.21 38052[56:Res:38049.0,61.1] always3(s24) || -> . % 76.03/76.21 38053[56:SSi:38052.0,713.0,36903.0] || -> . % 76.03/76.21 38054[54:Spt:38053.0,36898.2,36902.0] || xuntil6(s23)*+ -> . % 76.03/76.21 38055[54:Spt:38053.0,36898.0,36898.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.03/76.21 38056[54:Res:53.1,38055.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.03/76.21 38058[55:Spt:38056.1] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.21 38060[55:Res:38058.0,61.1] always3(s24) || -> . % 76.03/76.21 38061[55:SSi:38060.0,713.0] || -> . % 76.03/76.21 38062[55:Spt:38061.0,38056.1,38058.0] || m_main_v_state(s24,c_busy)* -> . % 76.03/76.21 38063[55:Spt:38061.0,38056.0] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.21 38066[55:Res:38063.0,61.1] always3(s23) || -> . % 76.03/76.21 38067[55:SSi:38066.0,712.0,36897.0] || -> . % 76.03/76.21 38068[53:Spt:38067.0,36895.2,36896.0] || xuntil6(s22)*+ -> . % 76.03/76.21 38069[53:Spt:38067.0,36895.0,36895.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.03/76.21 38070[53:Res:53.1,38069.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.03/76.21 38075[54:Spt:38070.0] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.21 38077[54:Res:38075.0,61.1] always3(s22) || -> . % 76.03/76.21 38078[54:SSi:38077.0,711.0,36894.0] || -> . % 76.03/76.21 38079[54:Spt:38078.0,38070.0,38075.0] || m_main_v_state(s22,c_busy)* -> . % 76.03/76.21 38080[54:Spt:38078.0,38070.1] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.21 38084[54:Res:38080.0,61.1] always3(s23) || -> . % 76.03/76.21 38085[54:SSi:38084.0,712.0] || -> . % 76.03/76.21 38086[52:Spt:38085.0,36889.2,36893.0] || xuntil6(s21)*+ -> . % 76.03/76.21 38087[52:Spt:38085.0,36889.0,36889.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.03/76.21 38088[52:Res:53.1,38087.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.03/76.21 38090[53:Spt:38088.1] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.21 38092[53:Res:38090.0,61.1] always3(s22) || -> . % 76.03/76.21 38093[53:SSi:38092.0,711.0] || -> . % 76.03/76.21 38094[53:Spt:38093.0,38088.1,38090.0] || m_main_v_state(s22,c_busy)* -> . % 76.03/76.21 38095[53:Spt:38093.0,38088.0] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.21 38098[53:Res:38095.0,61.1] always3(s21) || -> . % 76.03/76.21 38099[53:SSi:38098.0,710.0,36888.0] || -> . % 76.03/76.21 38100[51:Spt:38099.0,36886.2,36887.0] || xuntil6(s20)*+ -> . % 76.03/76.21 38101[51:Spt:38099.0,36886.0,36886.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.03/76.21 38102[51:Res:53.1,38101.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.03/76.21 38104[52:Spt:38102.0] || -> m_main_v_state(s20,c_busy)*. % 76.03/76.21 38106[52:Res:38104.0,61.1] always3(s20) || -> . % 76.03/76.21 38107[52:SSi:38106.0,709.0,36885.0] || -> . % 76.03/76.21 38108[52:Spt:38107.0,38102.0,38104.0] || m_main_v_state(s20,c_busy)* -> . % 76.03/76.21 38109[52:Spt:38107.0,38102.1] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.21 38113[52:Res:38109.0,61.1] always3(s21) || -> . % 76.03/76.21 38114[52:SSi:38113.0,710.0] || -> . % 76.03/76.21 38115[50:Spt:38114.0,36880.2,36884.0] || xuntil6(s19)*+ -> . % 76.03/76.21 38116[50:Spt:38114.0,36880.0,36880.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.03/76.21 38117[50:Res:53.1,38116.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.03/76.21 38122[51:Spt:38117.0] || -> m_main_v_state(s19,c_busy)*. % 76.03/76.21 38124[51:Res:38122.0,61.1] always3(s19) || -> . % 76.03/76.21 38125[51:SSi:38124.0,708.0,36879.0] || -> . % 76.03/76.21 38126[51:Spt:38125.0,38117.0,38122.0] || m_main_v_state(s19,c_busy)* -> . % 76.03/76.21 38127[51:Spt:38125.0,38117.1] || -> m_main_v_state(s20,c_busy)*. % 76.03/76.21 38131[51:Res:38127.0,61.1] always3(s20) || -> . % 76.03/76.21 38132[51:SSi:38131.0,709.0] || -> . % 76.03/76.21 38133[49:Spt:38132.0,36877.2,36878.0] || xuntil6(s18)*+ -> . % 76.03/76.21 38134[49:Spt:38132.0,36877.0,36877.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.03/76.21 38135[49:Res:53.1,38134.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.03/76.21 38137[50:Spt:38135.0] || -> m_main_v_state(s18,c_busy)*. % 76.03/76.21 38139[50:Res:38137.0,61.1] always3(s18) || -> . % 76.03/76.21 38140[50:SSi:38139.0,707.0,36876.0] || -> . % 76.03/76.21 38141[50:Spt:38140.0,38135.0,38137.0] || m_main_v_state(s18,c_busy)* -> . % 76.03/76.21 38142[50:Spt:38140.0,38135.1] || -> m_main_v_state(s19,c_busy)*. % 76.03/76.21 38146[50:Res:38142.0,61.1] always3(s19) || -> . % 76.03/76.21 38147[50:SSi:38146.0,708.0] || -> . % 76.03/76.21 38148[48:Spt:38147.0,36871.2,36875.0] || xuntil6(s17)*+ -> . % 76.03/76.21 38149[48:Spt:38147.0,36871.0,36871.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.03/76.21 38150[48:Res:53.1,38149.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.03/76.21 38152[49:Spt:38150.0] || -> m_main_v_state(s17,c_busy)*. % 76.03/76.21 38154[49:Res:38152.0,61.1] always3(s17) || -> . % 76.03/76.21 38155[49:SSi:38154.0,706.0,36870.0] || -> . % 76.03/76.21 38156[49:Spt:38155.0,38150.0,38152.0] || m_main_v_state(s17,c_busy)* -> . % 76.03/76.21 38157[49:Spt:38155.0,38150.1] || -> m_main_v_state(s18,c_busy)*. % 76.03/76.21 38161[49:Res:38157.0,61.1] always3(s18) || -> . % 76.03/76.21 38162[49:SSi:38161.0,707.0] || -> . % 76.03/76.21 38163[47:Spt:38162.0,36868.2,36869.0] || xuntil6(s16)*+ -> . % 76.03/76.21 38164[47:Spt:38162.0,36868.0,36868.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.03/76.21 38165[47:Res:53.1,38164.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.03/76.21 38170[48:Spt:38165.0] || -> m_main_v_state(s16,c_busy)*. % 76.03/76.21 38172[48:Res:38170.0,61.1] always3(s16) || -> . % 76.03/76.21 38173[48:SSi:38172.0,705.0,36867.0] || -> . % 76.03/76.21 38174[48:Spt:38173.0,38165.0,38170.0] || m_main_v_state(s16,c_busy)* -> . % 76.03/76.21 38175[48:Spt:38173.0,38165.1] || -> m_main_v_state(s17,c_busy)*. % 76.03/76.21 38179[48:Res:38175.0,61.1] always3(s17) || -> . % 76.03/76.21 38180[48:SSi:38179.0,706.0] || -> . % 76.03/76.21 38181[46:Spt:38180.0,36862.2,36866.0] || xuntil6(s15)*+ -> . % 76.03/76.21 38182[46:Spt:38180.0,36862.0,36862.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.03/76.21 38183[46:Res:53.1,38182.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.03/76.21 38185[47:Spt:38183.0] || -> m_main_v_state(s15,c_busy)*. % 76.03/76.21 38187[47:Res:38185.0,61.1] always3(s15) || -> . % 76.03/76.21 38188[47:SSi:38187.0,704.0,36861.0] || -> . % 76.03/76.21 38189[47:Spt:38188.0,38183.0,38185.0] || m_main_v_state(s15,c_busy)* -> . % 76.03/76.21 38190[47:Spt:38188.0,38183.1] || -> m_main_v_state(s16,c_busy)*. % 76.03/76.21 38194[47:Res:38190.0,61.1] always3(s16) || -> . % 76.03/76.21 38195[47:SSi:38194.0,705.0] || -> . % 76.03/76.21 38196[45:Spt:38195.0,36859.2,36860.0] || xuntil6(s14)*+ -> . % 76.03/76.21 38197[45:Spt:38195.0,36859.0,36859.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.03/76.21 38198[45:Res:53.1,38197.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.03/76.21 38200[46:Spt:38198.0] || -> m_main_v_state(s14,c_busy)*. % 76.03/76.21 38202[46:Res:38200.0,61.1] always3(s14) || -> . % 76.03/76.21 38203[46:SSi:38202.0,703.0,36858.0] || -> . % 76.03/76.21 38204[46:Spt:38203.0,38198.0,38200.0] || m_main_v_state(s14,c_busy)* -> . % 76.03/76.21 38205[46:Spt:38203.0,38198.1] || -> m_main_v_state(s15,c_busy)*. % 76.03/76.21 38209[46:Res:38205.0,61.1] always3(s15) || -> . % 76.03/76.21 38210[46:SSi:38209.0,704.0] || -> . % 76.03/76.21 38211[44:Spt:38210.0,36853.2,36857.0] || xuntil6(s13)*+ -> . % 76.03/76.21 38212[44:Spt:38210.0,36853.0,36853.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.03/76.21 38213[44:Res:53.1,38212.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.03/76.21 38218[45:Spt:38213.0] || -> m_main_v_state(s13,c_busy)*. % 76.03/76.21 38220[45:Res:38218.0,61.1] always3(s13) || -> . % 76.03/76.21 38221[45:SSi:38220.0,702.0,36852.0] || -> . % 76.03/76.21 38222[45:Spt:38221.0,38213.0,38218.0] || m_main_v_state(s13,c_busy)* -> . % 76.03/76.21 38223[45:Spt:38221.0,38213.1] || -> m_main_v_state(s14,c_busy)*. % 76.03/76.21 38227[45:Res:38223.0,61.1] always3(s14) || -> . % 76.03/76.21 38228[45:SSi:38227.0,703.0] || -> . % 76.03/76.21 38229[43:Spt:38228.0,36850.2,36851.0] || xuntil6(s12)*+ -> . % 76.03/76.21 38230[43:Spt:38228.0,36850.0,36850.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.03/76.21 38231[43:Res:53.1,38230.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.03/76.21 38233[44:Spt:38231.0] || -> m_main_v_state(s12,c_busy)*. % 76.03/76.21 38235[44:Res:38233.0,61.1] always3(s12) || -> . % 76.03/76.21 38236[44:SSi:38235.0,701.0,36849.0] || -> . % 76.03/76.21 38237[44:Spt:38236.0,38231.0,38233.0] || m_main_v_state(s12,c_busy)* -> . % 76.03/76.21 38238[44:Spt:38236.0,38231.1] || -> m_main_v_state(s13,c_busy)*. % 76.03/76.21 38242[44:Res:38238.0,61.1] always3(s13) || -> . % 76.03/76.21 38243[44:SSi:38242.0,702.0] || -> . % 76.03/76.21 38244[42:Spt:38243.0,36844.2,36848.0] || xuntil6(s11)*+ -> . % 76.03/76.21 38245[42:Spt:38243.0,36844.0,36844.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.03/76.21 38246[42:Res:53.1,38245.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.03/76.21 38248[43:Spt:38246.0] || -> m_main_v_state(s11,c_busy)*. % 76.03/76.21 38250[43:Res:38248.0,61.1] always3(s11) || -> . % 76.03/76.21 38251[43:SSi:38250.0,700.0,36843.0] || -> . % 76.03/76.21 38252[43:Spt:38251.0,38246.0,38248.0] || m_main_v_state(s11,c_busy)* -> . % 76.03/76.21 38253[43:Spt:38251.0,38246.1] || -> m_main_v_state(s12,c_busy)*. % 76.03/76.21 38257[43:Res:38253.0,61.1] always3(s12) || -> . % 76.03/76.21 38258[43:SSi:38257.0,701.0] || -> . % 76.03/76.21 38259[41:Spt:38258.0,36841.2,36842.0] || xuntil6(s10)*+ -> . % 76.03/76.21 38260[41:Spt:38258.0,36841.0,36841.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.03/76.21 38261[41:Res:53.1,38260.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.03/76.21 38266[42:Spt:38261.0] || -> m_main_v_state(s10,c_busy)*. % 76.03/76.21 38268[42:Res:38266.0,61.1] always3(s10) || -> . % 76.03/76.21 38269[42:SSi:38268.0,699.0,36840.0] || -> . % 76.03/76.21 38270[42:Spt:38269.0,38261.0,38266.0] || m_main_v_state(s10,c_busy)* -> . % 76.03/76.21 38271[42:Spt:38269.0,38261.1] || -> m_main_v_state(s11,c_busy)*. % 76.03/76.21 38275[42:Res:38271.0,61.1] always3(s11) || -> . % 76.03/76.21 38276[42:SSi:38275.0,700.0] || -> . % 76.03/76.21 38277[40:Spt:38276.0,36835.2,36839.0] || xuntil6(s9)*+ -> . % 76.03/76.21 38278[40:Spt:38276.0,36835.0,36835.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.03/76.21 38279[40:Res:53.1,38278.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.03/76.21 38281[41:Spt:38279.0] || -> m_main_v_state(s9,c_busy)*. % 76.03/76.21 38283[41:Res:38281.0,61.1] always3(s9) || -> . % 76.03/76.21 38284[41:SSi:38283.0,698.0,36834.0] || -> . % 76.03/76.21 38285[41:Spt:38284.0,38279.0,38281.0] || m_main_v_state(s9,c_busy)* -> . % 76.03/76.21 38286[41:Spt:38284.0,38279.1] || -> m_main_v_state(s10,c_busy)*. % 76.03/76.21 38290[41:Res:38286.0,61.1] always3(s10) || -> . % 76.03/76.21 38291[41:SSi:38290.0,699.0] || -> . % 76.03/76.21 38292[39:Spt:38291.0,36832.2,36833.0] || xuntil6(s8)*+ -> . % 76.03/76.21 38293[39:Spt:38291.0,36832.0,36832.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.03/76.21 38294[39:Res:53.1,38293.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.03/76.21 38296[40:Spt:38294.0] || -> m_main_v_state(s8,c_busy)*. % 76.03/76.21 38298[40:Res:38296.0,61.1] always3(s8) || -> . % 76.03/76.21 38299[40:SSi:38298.0,697.0,36831.0] || -> . % 76.03/76.21 38300[40:Spt:38299.0,38294.0,38296.0] || m_main_v_state(s8,c_busy)* -> . % 76.03/76.21 38301[40:Spt:38299.0,38294.1] || -> m_main_v_state(s9,c_busy)*. % 76.03/76.21 38305[40:Res:38301.0,61.1] always3(s9) || -> . % 76.03/76.21 38306[40:SSi:38305.0,698.0] || -> . % 76.03/76.21 38307[38:Spt:38306.0,36826.2,36830.0] || xuntil6(s7)*+ -> . % 76.03/76.21 38308[38:Spt:38306.0,36826.0,36826.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.03/76.21 38309[38:Res:53.1,38308.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.03/76.21 38314[39:Spt:38309.0] || -> m_main_v_state(s7,c_busy)*. % 76.03/76.21 38316[39:Res:38314.0,61.1] always3(s7) || -> . % 76.03/76.21 38317[39:SSi:38316.0,696.0,36825.0] || -> . % 76.03/76.21 38318[39:Spt:38317.0,38309.0,38314.0] || m_main_v_state(s7,c_busy)* -> . % 76.03/76.21 38319[39:Spt:38317.0,38309.1] || -> m_main_v_state(s8,c_busy)*. % 76.03/76.21 38323[39:Res:38319.0,61.1] always3(s8) || -> . % 76.03/76.21 38324[39:SSi:38323.0,697.0] || -> . % 76.03/76.21 38325[37:Spt:38324.0,36823.2,36824.0] || xuntil6(s6)*+ -> . % 76.03/76.21 38326[37:Spt:38324.0,36823.0,36823.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.03/76.21 38327[37:Res:53.1,38326.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.03/76.21 38329[38:Spt:38327.0] || -> m_main_v_state(s6,c_busy)*. % 76.03/76.21 38331[38:Res:38329.0,61.1] always3(s6) || -> . % 76.03/76.21 38332[38:SSi:38331.0,695.0,36822.0] || -> . % 76.03/76.21 38333[38:Spt:38332.0,38327.0,38329.0] || m_main_v_state(s6,c_busy)* -> . % 76.03/76.21 38334[38:Spt:38332.0,38327.1] || -> m_main_v_state(s7,c_busy)*. % 76.03/76.21 38338[38:Res:38334.0,61.1] always3(s7) || -> . % 76.03/76.21 38339[38:SSi:38338.0,696.0] || -> . % 76.03/76.21 38340[36:Spt:38339.0,36817.2,36821.0] || xuntil6(s5)*+ -> . % 76.03/76.21 38341[36:Spt:38339.0,36817.0,36817.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.03/76.21 38342[36:Res:53.1,38341.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.03/76.21 38344[37:Spt:38342.0] || -> m_main_v_state(s5,c_busy)*. % 76.03/76.21 38346[37:Res:38344.0,61.1] always3(s5) || -> . % 76.03/76.21 38347[37:SSi:38346.0,694.0,36816.0] || -> . % 76.03/76.21 38348[37:Spt:38347.0,38342.0,38344.0] || m_main_v_state(s5,c_busy)* -> . % 76.03/76.21 38349[37:Spt:38347.0,38342.1] || -> m_main_v_state(s6,c_busy)*. % 76.03/76.21 38353[37:Res:38349.0,61.1] always3(s6) || -> . % 76.03/76.21 38354[37:SSi:38353.0,695.0] || -> . % 76.03/76.21 38355[35:Spt:38354.0,36814.2,36815.0] || xuntil6(s4)*+ -> . % 76.03/76.21 38356[35:Spt:38354.0,36814.0,36814.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.03/76.21 38357[35:Res:53.1,38356.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.03/76.21 38362[36:Spt:38357.0] || -> m_main_v_state(s4,c_busy)*. % 76.03/76.21 38364[36:Res:38362.0,61.1] always3(s4) || -> . % 76.03/76.21 38365[36:SSi:38364.0,693.0,36813.0] || -> . % 76.03/76.21 38366[36:Spt:38365.0,38357.0,38362.0] || m_main_v_state(s4,c_busy)* -> . % 76.03/76.21 38367[36:Spt:38365.0,38357.1] || -> m_main_v_state(s5,c_busy)*. % 76.03/76.21 38371[36:Res:38367.0,61.1] always3(s5) || -> . % 76.03/76.21 38372[36:SSi:38371.0,694.0] || -> . % 76.03/76.21 38373[34:Spt:38372.0,36811.2,36812.0] || xuntil6(s3)*+ -> . % 76.03/76.21 38374[34:Spt:38372.0,36811.0,36811.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.03/76.21 38375[34:Res:53.1,38374.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.03/76.21 38377[35:Spt:38375.0] || -> m_main_v_state(s3,c_busy)*. % 76.03/76.21 38379[35:Res:38377.0,61.1] always3(s3) || -> . % 76.03/76.21 38380[35:SSi:38379.0,692.0,36810.0] || -> . % 76.03/76.21 38381[35:Spt:38380.0,38375.0,38377.0] || m_main_v_state(s3,c_busy)* -> . % 76.03/76.21 38382[35:Spt:38380.0,38375.1] || -> m_main_v_state(s4,c_busy)*. % 76.03/76.21 38386[35:Res:38382.0,61.1] always3(s4) || -> . % 76.03/76.21 38387[35:SSi:38386.0,693.0] || -> . % 76.03/76.21 38388[33:Spt:38387.0,36808.2,36809.0] || xuntil6(s2)*+ -> . % 76.03/76.21 38389[33:Spt:38387.0,36808.0,36808.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.03/76.21 38390[33:Res:53.1,38389.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.03/76.21 38392[34:Spt:38390.0] || -> m_main_v_state(s2,c_busy)*. % 76.03/76.21 38394[34:Res:38392.0,61.1] always3(s2) || -> . % 76.03/76.21 38395[34:SSi:38394.0,691.0,36807.0] || -> . % 76.03/76.21 38396[34:Spt:38395.0,38390.0,38392.0] || m_main_v_state(s2,c_busy)* -> . % 76.03/76.21 38397[34:Spt:38395.0,38390.1] || -> m_main_v_state(s3,c_busy)*. % 76.03/76.21 38401[34:Res:38397.0,61.1] always3(s3) || -> . % 76.03/76.21 38402[34:SSi:38401.0,692.0] || -> . % 76.03/76.21 38403[32:Spt:38402.0,36802.2,36806.0] || xuntil6(s1)*+ -> . % 76.03/76.21 38404[32:Spt:38402.0,36802.0,36802.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.03/76.21 38405[32:Res:53.1,38404.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.03/76.21 38410[33:Spt:38405.0] || -> m_main_v_state(s1,c_busy)*. % 76.03/76.21 38412[33:Res:38410.0,61.1] always3(s1) || -> . % 76.03/76.21 38413[33:SSi:38412.0,690.0,36801.0] || -> . % 76.03/76.21 38414[33:Spt:38413.0,38405.0,38410.0] || m_main_v_state(s1,c_busy)* -> . % 76.03/76.21 38415[33:Spt:38413.0,38405.1] || -> m_main_v_state(s2,c_busy)*. % 76.03/76.21 38420[33:Res:38415.0,61.1] always3(s2) || -> . % 76.03/76.21 38421[33:SSi:38420.0,691.0] || -> . % 76.03/76.21 38422[31:Spt:38421.0,74.0,36800.0] || xuntil6(s0)*+ -> . % 76.03/76.21 38423[31:Spt:38421.0,74.1] || -> node4(s0)*. % 76.03/76.21 38424[31:MRR:758.1,38422.0] || -> m_main_v_state(s1,c_busy)*. % 76.03/76.21 38426[31:Res:38424.0,61.1] always3(s1) || -> . % 76.03/76.21 38427[31:SSi:38426.0,690.0] || -> . % 76.03/76.21 38428[30:Spt:38427.0,36790.0,36794.0] || trans(s49,s21)*+ -> . % 76.03/76.21 38429[30:Spt:38427.0,36790.1,36790.2,36790.3,36790.4,36790.5,36790.6,36790.7,36790.8,36790.9,36790.10,36790.11,36790.12,36790.13,36790.14,36790.15,36790.16,36790.17,36790.18,36790.19,36790.20,36790.21] || -> trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.03/76.21 38430[30:MRR:36792.0,38428.0] || -> trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.03/76.21 38432[30:MRR:36793.1,38428.0] xuntil6(s49) || -> trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.03/76.21 38433[31:Spt:38429.0] || -> trans(s49,s20)*. % 76.03/76.21 38434[31:Res:38433.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s20)*. % 76.03/76.21 38436[31:Res:38433.0,60.0] || -> node2(s49,s20)*. % 76.03/76.21 38437[31:SSi:38434.1,50.0,738.0] xuntil6(s49) || -> until2p7(s20)*. % 76.03/76.21 38438[31:Res:38436.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)*. % 76.03/76.21 38439[32:Spt:74.0] || -> xuntil6(s0)*. % 76.03/76.21 38440[32:MRR:176.0,38439.0] || -> until5(s1)*. % 76.03/76.21 38441[32:MRR:37239.0,38440.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.03/76.21 38445[33:Spt:38441.2] || -> xuntil6(s1)*. % 76.03/76.21 38446[33:MRR:175.0,38445.0] || -> until5(s2)*. % 76.03/76.21 38447[33:MRR:37235.0,38446.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.03/76.21 38448[34:Spt:38447.2] || -> xuntil6(s2)*. % 76.03/76.21 38449[34:MRR:174.0,38448.0] || -> until5(s3)*. % 76.03/76.21 38450[34:MRR:37231.0,38449.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.03/76.21 38451[35:Spt:38450.2] || -> xuntil6(s3)*. % 76.03/76.21 38452[35:MRR:173.0,38451.0] || -> until5(s4)*. % 76.03/76.21 38453[35:MRR:37230.0,38452.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.03/76.21 38454[36:Spt:38453.2] || -> xuntil6(s4)*. % 76.03/76.21 38455[36:MRR:172.0,38454.0] || -> until5(s5)*. % 76.03/76.21 38456[36:MRR:37223.0,38455.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.03/76.21 38460[37:Spt:38456.2] || -> xuntil6(s5)*. % 76.03/76.21 38461[37:MRR:171.0,38460.0] || -> until5(s6)*. % 76.03/76.21 38462[37:MRR:37219.0,38461.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.03/76.21 38463[38:Spt:38462.2] || -> xuntil6(s6)*. % 76.03/76.21 38464[38:MRR:170.0,38463.0] || -> until5(s7)*. % 76.03/76.21 38465[38:MRR:37215.0,38464.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.03/76.21 38469[39:Spt:38465.2] || -> xuntil6(s7)*. % 76.03/76.21 38470[39:MRR:169.0,38469.0] || -> until5(s8)*. % 76.03/76.21 38471[39:MRR:37211.0,38470.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.03/76.21 38472[40:Spt:38471.2] || -> xuntil6(s8)*. % 76.03/76.21 38473[40:MRR:168.0,38472.0] || -> until5(s9)*. % 76.03/76.21 38474[40:MRR:37210.0,38473.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.03/76.21 38478[41:Spt:38474.2] || -> xuntil6(s9)*. % 76.03/76.21 38479[41:MRR:167.0,38478.0] || -> until5(s10)*. % 76.03/76.21 38480[41:MRR:37203.0,38479.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.03/76.21 38481[42:Spt:38480.2] || -> xuntil6(s10)*. % 76.03/76.21 38482[42:MRR:166.0,38481.0] || -> until5(s11)*. % 76.03/76.21 38483[42:MRR:37199.0,38482.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.03/76.21 38487[43:Spt:38483.2] || -> xuntil6(s11)*. % 76.03/76.21 38488[43:MRR:165.0,38487.0] || -> until5(s12)*. % 76.03/76.21 38489[43:MRR:37195.0,38488.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.03/76.21 38490[44:Spt:38489.2] || -> xuntil6(s12)*. % 76.03/76.21 38491[44:MRR:164.0,38490.0] || -> until5(s13)*. % 76.03/76.21 38492[44:MRR:37191.0,38491.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.03/76.21 38496[45:Spt:38492.2] || -> xuntil6(s13)*. % 76.03/76.21 38497[45:MRR:163.0,38496.0] || -> until5(s14)*. % 76.03/76.21 38498[45:MRR:37190.0,38497.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.03/76.21 38499[46:Spt:38498.2] || -> xuntil6(s14)*. % 76.03/76.21 38500[46:MRR:162.0,38499.0] || -> until5(s15)*. % 76.03/76.21 38501[46:MRR:37183.0,38500.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.03/76.21 38505[47:Spt:38501.2] || -> xuntil6(s15)*. % 76.03/76.21 38506[47:MRR:161.0,38505.0] || -> until5(s16)*. % 76.03/76.21 38507[47:MRR:37179.0,38506.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.03/76.21 38508[48:Spt:38507.2] || -> xuntil6(s16)*. % 76.03/76.21 38509[48:MRR:160.0,38508.0] || -> until5(s17)*. % 76.03/76.21 38510[48:MRR:37175.0,38509.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.03/76.21 38514[49:Spt:38510.2] || -> xuntil6(s17)*. % 76.03/76.21 38515[49:MRR:159.0,38514.0] || -> until5(s18)*. % 76.03/76.21 38516[49:MRR:37171.0,38515.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.03/76.21 38517[50:Spt:38516.2] || -> xuntil6(s18)*. % 76.03/76.21 38518[50:MRR:158.0,38517.0] || -> until5(s19)*. % 76.03/76.21 38519[50:MRR:37170.0,38518.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.03/76.21 38523[51:Spt:38519.2] || -> xuntil6(s19)*. % 76.03/76.21 38524[51:MRR:157.0,38523.0] || -> until5(s20)*. % 76.03/76.21 38525[51:MRR:37163.0,38524.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.03/76.21 38526[52:Spt:38525.2] || -> xuntil6(s20)*. % 76.03/76.21 38527[52:MRR:156.0,38526.0] || -> until5(s21)*. % 76.03/76.21 38528[52:MRR:37159.0,38527.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.03/76.21 38532[53:Spt:38528.2] || -> xuntil6(s21)*. % 76.03/76.21 38533[53:MRR:155.0,38532.0] || -> until5(s22)*. % 76.03/76.21 38534[53:MRR:37152.0,38533.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.03/76.21 38535[54:Spt:38534.2] || -> xuntil6(s22)*. % 76.03/76.21 38536[54:MRR:154.0,38535.0] || -> until5(s23)*. % 76.03/76.21 38537[54:MRR:37148.0,38536.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.03/76.21 38541[55:Spt:38537.2] || -> xuntil6(s23)*. % 76.03/76.21 38542[55:MRR:153.0,38541.0] || -> until5(s24)*. % 76.03/76.21 38543[55:MRR:37144.0,38542.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.03/76.21 38544[56:Spt:38543.2] || -> xuntil6(s24)*. % 76.03/76.21 38545[56:MRR:152.0,38544.0] || -> until5(s25)*. % 76.03/76.21 38546[56:MRR:37143.0,38545.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.03/76.21 38550[57:Spt:38546.2] || -> xuntil6(s25)*. % 76.03/76.21 38551[57:MRR:151.0,38550.0] || -> until5(s26)*. % 76.03/76.21 38552[57:MRR:37142.0,38551.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.03/76.21 38553[58:Spt:38552.2] || -> xuntil6(s26)*. % 76.03/76.21 38554[58:MRR:150.0,38553.0] || -> until5(s27)*. % 76.03/76.21 38555[58:MRR:37141.0,38554.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.03/76.21 38559[59:Spt:38555.2] || -> xuntil6(s27)*. % 76.03/76.21 38560[59:MRR:149.0,38559.0] || -> until5(s28)*. % 76.03/76.21 38561[59:MRR:37137.0,38560.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.03/76.21 38562[60:Spt:38561.2] || -> xuntil6(s28)*. % 76.03/76.21 38563[60:MRR:148.0,38562.0] || -> until5(s29)*. % 76.03/76.21 38564[60:MRR:35647.0,38563.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.03/76.21 38568[61:Spt:38564.1] || -> m_main_v_state(s30,c_busy)*. % 76.03/76.21 38570[61:Res:38568.0,61.1] always3(s30) || -> . % 76.03/76.21 38571[61:SSi:38570.0,719.0] || -> . % 76.03/76.21 38572[61:Spt:38571.0,38564.1,38568.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.03/76.21 38573[61:Spt:38571.0,38564.0,38564.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 76.03/76.21 38575[61:MRR:831.2,38572.0] node4(s29) || m_main_v_state(s29,c_ready)* -> . % 76.03/76.21 38576[61:Res:53.1,38573.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 76.03/76.21 38578[62:Spt:38576.1] || -> xuntil6(s29)*. % 76.03/76.21 38579[62:MRR:147.0,38578.0] || -> until5(s30)*. % 76.03/76.21 38580[62:MRR:37246.0,38579.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.03/76.21 38585[63:Spt:38580.2] || -> xuntil6(s30)*. % 76.03/76.21 38586[63:MRR:146.0,38585.0] || -> until5(s31)*. % 76.03/76.21 38587[63:MRR:35651.0,38586.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.03/76.21 38588[64:Spt:38587.1] || -> m_main_v_state(s32,c_busy)*. % 76.03/76.21 38590[64:Res:38588.0,61.1] always3(s32) || -> . % 76.03/76.21 38591[64:SSi:38590.0,721.0] || -> . % 76.03/76.21 38592[64:Spt:38591.0,38587.1,38588.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.03/76.21 38593[64:Spt:38591.0,38587.0,38587.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.03/76.21 38595[64:MRR:825.2,38592.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.03/76.21 38596[64:Res:53.1,38593.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.03/76.21 38598[65:Spt:38596.1] || -> xuntil6(s31)*. % 76.03/76.21 38599[65:MRR:145.0,38598.0] || -> until5(s32)*. % 76.03/76.21 38600[65:MRR:37250.0,38599.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.03/76.21 38608[66:Spt:38600.2] || -> xuntil6(s32)*. % 76.03/76.21 38609[66:MRR:144.0,38608.0] || -> until5(s33)*. % 76.03/76.21 38610[66:MRR:35655.0,38609.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.03/76.21 38611[67:Spt:38610.1] || -> m_main_v_state(s34,c_busy)*. % 76.03/76.21 38613[67:Res:38611.0,61.1] always3(s34) || -> . % 76.03/76.21 38614[67:SSi:38613.0,723.0] || -> . % 76.03/76.21 38615[67:Spt:38614.0,38610.1,38611.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.03/76.21 38616[67:Spt:38614.0,38610.0,38610.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.03/76.21 38618[67:MRR:819.2,38615.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.03/76.21 38619[67:Res:53.1,38616.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.03/76.21 38624[68:Spt:38619.1] || -> xuntil6(s33)*. % 76.03/76.21 38625[68:MRR:143.0,38624.0] || -> until5(s34)*. % 76.03/76.21 38626[68:MRR:37254.0,38625.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.03/76.21 38628[69:Spt:38626.2] || -> xuntil6(s34)*. % 76.03/76.21 38629[69:MRR:142.0,38628.0] || -> until5(s35)*. % 76.03/76.21 38630[69:MRR:35659.0,38629.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.03/76.21 38631[70:Spt:38630.1] || -> m_main_v_state(s36,c_busy)*. % 76.03/76.21 38633[70:Res:38631.0,61.1] always3(s36) || -> . % 76.03/76.21 38634[70:SSi:38633.0,725.0] || -> . % 76.03/76.21 38635[70:Spt:38634.0,38630.1,38631.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.03/76.21 38636[70:Spt:38634.0,38630.0,38630.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.03/76.21 38638[70:MRR:813.2,38635.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.03/76.21 38639[70:Res:53.1,38636.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.03/76.21 38641[71:Spt:38639.1] || -> xuntil6(s35)*. % 76.03/76.21 38642[71:MRR:141.0,38641.0] || -> until5(s36)*. % 76.03/76.21 38643[71:MRR:37261.0,38642.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.03/76.21 38648[72:Spt:38643.2] || -> xuntil6(s36)*. % 76.03/76.21 38649[72:MRR:140.0,38648.0] || -> until5(s37)*. % 76.03/76.21 38650[72:MRR:35666.0,38649.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.03/76.21 38651[73:Spt:38650.1] || -> m_main_v_state(s38,c_busy)*. % 76.03/76.21 38653[73:Res:38651.0,61.1] always3(s38) || -> . % 76.03/76.21 38654[73:SSi:38653.0,727.0] || -> . % 76.03/76.21 38655[73:Spt:38654.0,38650.1,38651.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.03/76.21 38656[73:Spt:38654.0,38650.0,38650.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.03/76.21 38658[73:MRR:807.2,38655.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.03/76.21 38659[73:Res:53.1,38656.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.03/76.21 38661[74:Spt:38659.1] || -> xuntil6(s37)*. % 76.03/76.21 38662[74:MRR:139.0,38661.0] || -> until5(s38)*. % 76.03/76.21 38663[74:MRR:37262.0,38662.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.03/76.21 38671[75:Spt:38663.2] || -> xuntil6(s38)*. % 76.03/76.21 38672[75:MRR:138.0,38671.0] || -> until5(s39)*. % 76.03/76.21 38673[75:MRR:35667.0,38672.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.03/76.21 38674[76:Spt:38673.1] || -> m_main_v_state(s40,c_busy)*. % 76.03/76.21 38676[76:Res:38674.0,61.1] always3(s40) || -> . % 76.03/76.21 38677[76:SSi:38676.0,729.0] || -> . % 76.03/76.21 38678[76:Spt:38677.0,38673.1,38674.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.03/76.21 38679[76:Spt:38677.0,38673.0,38673.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.03/76.21 38681[76:MRR:801.2,38678.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.03/76.21 38682[76:Res:53.1,38679.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.03/76.21 38687[77:Spt:38682.1] || -> xuntil6(s39)*. % 76.03/76.21 38688[77:MRR:137.0,38687.0] || -> until5(s40)*. % 76.03/76.21 38689[77:MRR:37266.0,38688.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.03/76.21 38691[78:Spt:38689.2] || -> xuntil6(s40)*. % 76.03/76.21 38692[78:MRR:136.0,38691.0] || -> until5(s41)*. % 76.03/76.21 38693[78:MRR:35671.0,38692.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.03/76.21 38694[79:Spt:38693.1] || -> m_main_v_state(s42,c_busy)*. % 76.03/76.21 38696[79:Res:38694.0,61.1] always3(s42) || -> . % 76.03/76.21 38697[79:SSi:38696.0,731.0] || -> . % 76.03/76.21 38698[79:Spt:38697.0,38693.1,38694.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.03/76.21 38699[79:Spt:38697.0,38693.0,38693.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.03/76.21 38701[79:MRR:795.2,38698.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.03/76.21 38702[79:Res:53.1,38699.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.03/76.21 38704[80:Spt:38702.1] || -> xuntil6(s41)*. % 76.03/76.21 38705[80:MRR:135.0,38704.0] || -> until5(s42)*. % 76.03/76.21 38706[80:MRR:37270.0,38705.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.03/76.21 38711[81:Spt:38706.2] || -> xuntil6(s42)*. % 76.03/76.21 38712[81:MRR:134.0,38711.0] || -> until5(s43)*. % 76.03/76.21 38713[81:MRR:35675.0,38712.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.03/76.21 38714[82:Spt:38713.1] || -> m_main_v_state(s44,c_busy)*. % 76.03/76.21 38716[82:Res:38714.0,61.1] always3(s44) || -> . % 76.03/76.21 38717[82:SSi:38716.0,733.0] || -> . % 76.03/76.21 38718[82:Spt:38717.0,38713.1,38714.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.03/76.21 38719[82:Spt:38717.0,38713.0,38713.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.03/76.21 38721[82:MRR:789.2,38718.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.03/76.21 38722[82:Res:53.1,38719.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.03/76.21 38724[83:Spt:38722.1] || -> xuntil6(s43)*. % 76.03/76.21 38725[83:MRR:133.0,38724.0] || -> until5(s44)*. % 76.03/76.21 38726[83:MRR:37274.0,38725.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.03/76.21 38734[84:Spt:38726.2] || -> xuntil6(s44)*. % 76.03/76.21 38735[84:MRR:132.0,38734.0] || -> until5(s45)*. % 76.03/76.21 38736[84:MRR:35679.0,38735.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.03/76.21 38737[85:Spt:38736.1] || -> m_main_v_state(s46,c_busy)*. % 76.03/76.21 38739[85:Res:38737.0,61.1] always3(s46) || -> . % 76.03/76.21 38740[85:SSi:38739.0,735.0] || -> . % 76.03/76.21 38741[85:Spt:38740.0,38736.1,38737.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.03/76.21 38742[85:Spt:38740.0,38736.0,38736.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.03/76.21 38744[85:MRR:783.2,38741.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.03/76.21 38745[85:Res:53.1,38742.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.03/76.21 38750[86:Spt:38745.1] || -> xuntil6(s45)*. % 76.03/76.21 38751[86:MRR:131.0,38750.0] || -> until5(s46)*. % 76.03/76.21 38752[86:MRR:37281.0,38751.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.03/76.21 38754[87:Spt:38752.2] || -> xuntil6(s46)*. % 76.03/76.21 38755[87:MRR:130.0,38754.0] || -> until5(s47)*. % 76.03/76.21 38756[87:MRR:35683.0,38755.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.03/76.21 38757[88:Spt:38756.1] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.21 38759[88:Res:38757.0,61.1] always3(s48) || -> . % 76.03/76.21 38760[88:SSi:38759.0,737.0] || -> . % 76.03/76.21 38761[88:Spt:38760.0,38756.1,38757.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.03/76.21 38762[88:Spt:38760.0,38756.0,38756.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.03/76.21 38764[88:MRR:777.2,38761.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.03/76.21 38765[88:Res:53.1,38762.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.03/76.21 38767[89:Spt:38765.1] || -> xuntil6(s47)*. % 76.03/76.21 38768[89:MRR:129.0,38767.0] || -> until5(s48)*. % 76.03/76.21 38769[89:MRR:37282.0,38768.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.03/76.21 38774[90:Spt:38769.2] || -> xuntil6(s48)*. % 76.03/76.21 38775[90:MRR:128.0,38774.0] || -> until5(s49)*. % 76.03/76.21 38776[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.03/76.21 38780[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.03/76.21 38781[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.03/76.21 38782[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.03/76.21 38783[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.03/76.21 38787[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.03/76.21 38791[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.03/76.21 38798[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.03/76.21 38802[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.03/76.21 38809[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.03/76.21 38810[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.03/76.21 38814[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.03/76.21 38818[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.03/76.21 38822[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.03/76.21 38829[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.03/76.21 38830[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.03/76.21 38834[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.03/76.21 38838[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.03/76.21 38842[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.03/76.21 38849[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.03/76.21 38850[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.03/76.21 38854[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.03/76.21 38858[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.03/76.21 38862[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.03/76.21 38869[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.03/76.21 38870[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.03/76.21 38874[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.03/76.21 38878[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.03/76.21 38880[31:SoR:38438.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)*. % 76.03/76.21 38885[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.03/76.21 38889[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.03/76.21 38893[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.03/76.21 38900[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.03/76.21 38901[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.03/76.21 38905[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.03/76.21 38909[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.03/76.21 38913[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.03/76.21 38920[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.03/76.21 38921[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.03/76.21 38922[31:SoR:38880.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)* xuntil6(s49). % 76.03/76.21 38923[90:SSi:38922.0,50.0,738.0,38775.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s20,c_busy)* xuntil6(s49). % 76.03/76.21 38924[91:Spt:38923.1] || -> m_main_v_state(s20,c_busy)*. % 76.03/76.21 38926[91:Res:38924.0,61.1] always3(s20) || -> . % 76.03/76.21 38927[91:SSi:38926.0,709.0,38524.0,38526.0] || -> . % 76.03/76.21 38928[91:Spt:38927.0,38923.1,38924.0] || m_main_v_state(s20,c_busy)*+ -> . % 76.03/76.21 38929[91:Spt:38927.0,38923.0,38923.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.03/76.21 38933[91:MRR:38880.2,38928.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.03/76.21 38934[91:Res:53.1,38929.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.03/76.21 38936[92:Spt:38934.0] || -> m_main_v_state(s49,c_busy)*. % 76.03/76.21 38938[92:Res:38936.0,61.1] always3(s49) || -> . % 76.03/76.21 38939[92:SSi:38938.0,50.0,738.0,38775.0] || -> . % 76.03/76.21 38940[92:Spt:38939.0,38934.0,38936.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.03/76.21 38941[92:Spt:38939.0,38934.1] || -> xuntil6(s49)*. % 76.03/76.21 38942[92:MRR:38437.0,38941.0] || -> until2p7(s20)*. % 76.03/76.21 38943[92:MRR:216.0,38942.0] || -> until2p7(s21)* node4(s20). % 76.03/76.21 38945[92:MRR:774.2,38940.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.03/76.21 38946[93:Spt:38943.0] || -> until2p7(s21)*. % 76.03/76.21 38947[93:MRR:217.0,38946.0] || -> until2p7(s22)* node4(s21). % 76.03/76.21 38948[94:Spt:38947.0] || -> until2p7(s22)*. % 76.03/76.21 38949[94:MRR:218.0,38948.0] || -> until2p7(s23)* node4(s22). % 76.03/76.21 38950[95:Spt:38949.0] || -> until2p7(s23)*. % 76.03/76.21 38951[95:MRR:219.0,38950.0] || -> until2p7(s24)* node4(s23). % 76.03/76.21 38952[96:Spt:38951.0] || -> until2p7(s24)*. % 76.03/76.21 38953[96:MRR:220.0,38952.0] || -> until2p7(s25)* node4(s24). % 76.03/76.21 38954[97:Spt:38953.0] || -> until2p7(s25)*. % 76.03/76.21 38955[97:MRR:221.0,38954.0] || -> until2p7(s26)* node4(s25). % 76.03/76.21 38956[98:Spt:38955.0] || -> until2p7(s26)*. % 76.03/76.21 38957[98:MRR:222.0,38956.0] || -> until2p7(s27)* node4(s26). % 76.03/76.21 38958[99:Spt:38957.0] || -> until2p7(s27)*. % 76.03/76.21 38959[99:MRR:223.0,38958.0] || -> until2p7(s28)* node4(s27). % 76.03/76.21 38960[100:Spt:38959.0] || -> until2p7(s28)*. % 76.03/76.21 38961[100:MRR:224.0,38960.0] || -> until2p7(s29)* node4(s28). % 76.03/76.21 38962[101:Spt:38961.0] || -> until2p7(s29)*. % 76.03/76.21 38963[101:MRR:225.0,38962.0] || -> until2p7(s30)* node4(s29). % 76.03/76.21 38964[102:Spt:38963.0] || -> until2p7(s30)*. % 76.03/76.21 38965[102:MRR:226.0,38964.0] || -> until2p7(s31)* node4(s30). % 76.03/76.21 38966[103:Spt:38965.0] || -> until2p7(s31)*. % 76.03/76.21 38967[103:MRR:227.0,38966.0] || -> until2p7(s32)* node4(s31). % 76.03/76.21 38968[104:Spt:38967.0] || -> until2p7(s32)*. % 76.03/76.21 38969[104:MRR:228.0,38968.0] || -> until2p7(s33)* node4(s32). % 76.03/76.21 38970[105:Spt:38969.0] || -> until2p7(s33)*. % 76.03/76.21 38971[105:MRR:229.0,38970.0] || -> until2p7(s34)* node4(s33). % 76.03/76.21 38972[106:Spt:38971.0] || -> until2p7(s34)*. % 76.03/76.21 38973[106:MRR:230.0,38972.0] || -> until2p7(s35)* node4(s34). % 76.03/76.21 38974[107:Spt:38973.0] || -> until2p7(s35)*. % 76.03/76.21 38975[107:MRR:231.0,38974.0] || -> until2p7(s36)* node4(s35). % 76.03/76.21 38976[108:Spt:38975.0] || -> until2p7(s36)*. % 76.03/76.21 38977[108:MRR:232.0,38976.0] || -> until2p7(s37)* node4(s36). % 76.03/76.21 38978[109:Spt:38977.0] || -> until2p7(s37)*. % 76.03/76.21 38979[109:MRR:235.0,38978.0] || -> until2p7(s38)* node4(s37). % 76.03/76.21 38980[110:Spt:38979.0] || -> until2p7(s38)*. % 76.03/76.21 38981[110:MRR:236.0,38980.0] || -> until2p7(s39)* node4(s38). % 76.03/76.21 38982[111:Spt:38981.0] || -> until2p7(s39)*. % 76.03/76.21 38983[111:MRR:237.0,38982.0] || -> until2p7(s40)* node4(s39). % 76.03/76.21 38984[112:Spt:38983.0] || -> until2p7(s40)*. % 76.03/76.21 38985[112:MRR:238.0,38984.0] || -> until2p7(s41)* node4(s40). % 76.03/76.21 38986[113:Spt:38985.0] || -> until2p7(s41)*. % 76.03/76.21 38987[113:MRR:239.0,38986.0] || -> until2p7(s42)* node4(s41). % 76.03/76.21 38988[114:Spt:38987.0] || -> until2p7(s42)*. % 76.03/76.21 38989[114:MRR:240.0,38988.0] || -> until2p7(s43)* node4(s42). % 76.03/76.21 38990[115:Spt:38989.0] || -> until2p7(s43)*. % 76.03/76.21 38991[115:MRR:241.0,38990.0] || -> until2p7(s44)* node4(s43). % 76.03/76.21 38992[116:Spt:38991.0] || -> until2p7(s44)*. % 76.03/76.21 38993[116:MRR:539.0,38992.0] || -> until2p7(s45)* node4(s44). % 76.03/76.21 38994[117:Spt:38993.0] || -> until2p7(s45)*. % 76.03/76.21 38995[117:MRR:544.0,38994.0] || -> until2p7(s46)* node4(s45). % 76.03/76.21 38996[118:Spt:38995.0] || -> until2p7(s46)*. % 76.03/76.21 38997[118:MRR:549.0,38996.0] || -> until2p7(s47)* node4(s46). % 76.03/76.21 38998[119:Spt:38997.0] || -> until2p7(s47)*. % 76.03/76.21 38999[119:MRR:554.0,38998.0] || -> until2p7(s48)* node4(s47). % 76.03/76.21 39000[120:Spt:38999.0] || -> until2p7(s48)*. % 76.03/76.21 39001[120:MRR:559.0,39000.0] || -> until2p7(s49)* node4(s48). % 76.03/76.21 39002[121:Spt:39001.0] || -> until2p7(s49)*. % 76.03/76.21 39003[121:MRR:194.0,39002.0] || -> node4(s49)*. % 76.03/76.21 39004[121:MRR:38933.0,39003.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.03/76.21 39005[121:Res:53.1,39004.0] || -> m_main_v_state(s49,c_busy)*. % 76.03/76.21 39007[121:MRR:39005.0,38940.0] || -> . % 76.03/76.21 39008[121:Spt:39007.0,39001.0,39002.0] || until2p7(s49)*+ -> . % 76.03/76.21 39009[121:Spt:39007.0,39001.1] || -> node4(s48)*. % 76.03/76.21 39010[121:MRR:38945.0,39009.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.03/76.21 39013[121:Res:53.1,39010.0] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.21 39015[121:MRR:39013.0,38761.0] || -> . % 76.03/76.21 39016[120:Spt:39015.0,38999.0,39000.0] || until2p7(s48)*+ -> . % 76.03/76.21 39017[120:Spt:39015.0,38999.1] || -> node4(s47)*. % 76.03/76.21 39018[120:MRR:38764.0,39017.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.03/76.21 39021[120:Res:53.1,39018.0] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.21 39024[120:Res:39021.0,61.1] always3(s47) || -> . % 76.03/76.21 39025[120:SSi:39024.0,736.0,38755.0,38767.0,38998.0,39017.0] || -> . % 76.03/76.21 39026[119:Spt:39025.0,38997.0,38998.0] || until2p7(s47)*+ -> . % 76.03/76.21 39027[119:Spt:39025.0,38997.1] || -> node4(s46)*. % 76.03/76.21 39029[119:MRR:780.0,39027.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.03/76.21 39049[119:Res:53.1,39029.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.03/76.21 39051[119:MRR:39049.0,38741.0] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.21 39053[119:Res:39051.0,61.1] always3(s47) || -> . % 76.03/76.21 39054[119:SSi:39053.0,736.0,38755.0,38767.0] || -> . % 76.03/76.21 39055[118:Spt:39054.0,38995.0,38996.0] || until2p7(s46)*+ -> . % 76.03/76.21 39056[118:Spt:39054.0,38995.1] || -> node4(s45)*. % 76.03/76.21 39057[118:MRR:38744.0,39056.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.03/76.21 39060[118:Res:53.1,39057.0] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.21 39063[118:Res:39060.0,61.1] always3(s45) || -> . % 76.03/76.21 39064[118:SSi:39063.0,734.0,38735.0,38750.0,38994.0,39056.0] || -> . % 76.03/76.21 39065[117:Spt:39064.0,38993.0,38994.0] || until2p7(s45)*+ -> . % 76.03/76.21 39066[117:Spt:39064.0,38993.1] || -> node4(s44)*. % 76.03/76.21 39068[117:MRR:786.0,39066.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.03/76.21 39080[117:Res:53.1,39068.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.03/76.21 39082[117:MRR:39080.0,38718.0] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.21 39084[117:Res:39082.0,61.1] always3(s45) || -> . % 76.03/76.21 39085[117:SSi:39084.0,734.0,38735.0,38750.0] || -> . % 76.03/76.21 39086[116:Spt:39085.0,38991.0,38992.0] || until2p7(s44)*+ -> . % 76.03/76.21 39087[116:Spt:39085.0,38991.1] || -> node4(s43)*. % 76.03/76.21 39088[116:MRR:38721.0,39087.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.03/76.21 39091[116:Res:53.1,39088.0] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.21 39094[116:Res:39091.0,61.1] always3(s43) || -> . % 76.03/76.21 39095[116:SSi:39094.0,732.0,38712.0,38724.0,38990.0,39087.0] || -> . % 76.03/76.21 39096[115:Spt:39095.0,38989.0,38990.0] || until2p7(s43)*+ -> . % 76.03/76.21 39097[115:Spt:39095.0,38989.1] || -> node4(s42)*. % 76.03/76.21 39099[115:MRR:792.0,39097.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.03/76.21 39111[115:Res:53.1,39099.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.03/76.21 39113[115:MRR:39111.0,38698.0] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.21 39118[115:Res:39113.0,61.1] always3(s43) || -> . % 76.03/76.21 39119[115:SSi:39118.0,732.0,38712.0,38724.0] || -> . % 76.03/76.21 39120[114:Spt:39119.0,38987.0,38988.0] || until2p7(s42)*+ -> . % 76.03/76.21 39121[114:Spt:39119.0,38987.1] || -> node4(s41)*. % 76.03/76.21 39122[114:MRR:38701.0,39121.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.03/76.21 39125[114:Res:53.1,39122.0] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.21 39129[114:Res:39125.0,61.1] always3(s41) || -> . % 76.03/76.21 39130[114:SSi:39129.0,730.0,38692.0,38704.0,38986.0,39121.0] || -> . % 76.03/76.21 39131[113:Spt:39130.0,38985.0,38986.0] || until2p7(s41)*+ -> . % 76.03/76.21 39132[113:Spt:39130.0,38985.1] || -> node4(s40)*. % 76.03/76.21 39134[113:MRR:798.0,39132.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.03/76.21 39145[113:Res:53.1,39134.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.03/76.21 39147[113:MRR:39145.0,38678.0] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.21 39149[113:Res:39147.0,61.1] always3(s41) || -> . % 76.03/76.21 39150[113:SSi:39149.0,730.0,38692.0,38704.0] || -> . % 76.03/76.21 39151[112:Spt:39150.0,38983.0,38984.0] || until2p7(s40)*+ -> . % 76.03/76.21 39152[112:Spt:39150.0,38983.1] || -> node4(s39)*. % 76.03/76.21 39153[112:MRR:38681.0,39152.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.03/76.21 39157[112:Res:53.1,39153.0] || -> m_main_v_state(s39,c_busy)*. % 76.03/76.21 39160[112:Res:39157.0,61.1] always3(s39) || -> . % 76.03/76.21 39161[112:SSi:39160.0,728.0,38672.0,38687.0,38982.0,39152.0] || -> . % 76.03/76.21 39162[111:Spt:39161.0,38981.0,38982.0] || until2p7(s39)*+ -> . % 76.03/76.21 39163[111:Spt:39161.0,38981.1] || -> node4(s38)*. % 76.03/76.21 39165[111:MRR:804.0,39163.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.03/76.21 39176[111:Res:53.1,39165.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.03/76.21 39178[111:MRR:39176.0,38655.0] || -> m_main_v_state(s39,c_busy)*. % 76.03/76.21 39180[111:Res:39178.0,61.1] always3(s39) || -> . % 76.03/76.21 39181[111:SSi:39180.0,728.0,38672.0,38687.0] || -> . % 76.03/76.21 39182[110:Spt:39181.0,38979.0,38980.0] || until2p7(s38)*+ -> . % 76.03/76.21 39183[110:Spt:39181.0,38979.1] || -> node4(s37)*. % 76.03/76.21 39184[110:MRR:38658.0,39183.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.03/76.21 39187[110:Res:53.1,39184.0] || -> m_main_v_state(s37,c_busy)*. % 76.03/76.21 39190[110:Res:39187.0,61.1] always3(s37) || -> . % 76.03/76.21 39191[110:SSi:39190.0,726.0,38649.0,38661.0,38978.0,39183.0] || -> . % 76.03/76.21 39192[109:Spt:39191.0,38977.0,38978.0] || until2p7(s37)*+ -> . % 76.03/76.21 39193[109:Spt:39191.0,38977.1] || -> node4(s36)*. % 76.03/76.21 39195[109:MRR:810.0,39193.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.03/76.21 39207[109:Res:53.1,39195.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.03/76.21 39209[109:MRR:39207.0,38635.0] || -> m_main_v_state(s37,c_busy)*. % 76.03/76.21 39211[109:Res:39209.0,61.1] always3(s37) || -> . % 76.03/76.21 39212[109:SSi:39211.0,726.0,38649.0,38661.0] || -> . % 76.03/76.21 39213[108:Spt:39212.0,38975.0,38976.0] || until2p7(s36)*+ -> . % 76.03/76.21 39214[108:Spt:39212.0,38975.1] || -> node4(s35)*. % 76.03/76.21 39215[108:MRR:38638.0,39214.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.03/76.21 39218[108:Res:53.1,39215.0] || -> m_main_v_state(s35,c_busy)*. % 76.03/76.21 39221[108:Res:39218.0,61.1] always3(s35) || -> . % 76.03/76.21 39222[108:SSi:39221.0,724.0,38629.0,38641.0,38974.0,39214.0] || -> . % 76.03/76.21 39223[107:Spt:39222.0,38973.0,38974.0] || until2p7(s35)*+ -> . % 76.03/76.21 39224[107:Spt:39222.0,38973.1] || -> node4(s34)*. % 76.03/76.21 39226[107:MRR:816.0,39224.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.03/76.21 39238[107:Res:53.1,39226.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.03/76.21 39240[107:MRR:39238.0,38615.0] || -> m_main_v_state(s35,c_busy)*. % 76.03/76.21 39245[107:Res:39240.0,61.1] always3(s35) || -> . % 76.03/76.21 39246[107:SSi:39245.0,724.0,38629.0,38641.0] || -> . % 76.03/76.21 39247[106:Spt:39246.0,38971.0,38972.0] || until2p7(s34)*+ -> . % 76.03/76.21 39248[106:Spt:39246.0,38971.1] || -> node4(s33)*. % 76.03/76.21 39249[106:MRR:38618.0,39248.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.03/76.21 39252[106:Res:53.1,39249.0] || -> m_main_v_state(s33,c_busy)*. % 76.03/76.21 39256[106:Res:39252.0,61.1] always3(s33) || -> . % 76.03/76.21 39257[106:SSi:39256.0,722.0,38609.0,38624.0,38970.0,39248.0] || -> . % 76.03/76.21 39258[105:Spt:39257.0,38969.0,38970.0] || until2p7(s33)*+ -> . % 76.03/76.21 39259[105:Spt:39257.0,38969.1] || -> node4(s32)*. % 76.03/76.21 39261[105:MRR:822.0,39259.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.03/76.21 39272[105:Res:53.1,39261.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.03/76.21 39274[105:MRR:39272.0,38592.0] || -> m_main_v_state(s33,c_busy)*. % 76.03/76.21 39276[105:Res:39274.0,61.1] always3(s33) || -> . % 76.03/76.21 39277[105:SSi:39276.0,722.0,38609.0,38624.0] || -> . % 76.03/76.21 39278[104:Spt:39277.0,38967.0,38968.0] || until2p7(s32)*+ -> . % 76.03/76.21 39279[104:Spt:39277.0,38967.1] || -> node4(s31)*. % 76.03/76.21 39280[104:MRR:38595.0,39279.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.03/76.21 39284[104:Res:53.1,39280.0] || -> m_main_v_state(s31,c_busy)*. % 76.03/76.21 39287[104:Res:39284.0,61.1] always3(s31) || -> . % 76.03/76.21 39288[104:SSi:39287.0,720.0,38586.0,38598.0,38966.0,39279.0] || -> . % 76.03/76.21 39289[103:Spt:39288.0,38965.0,38966.0] || until2p7(s31)*+ -> . % 76.03/76.21 39290[103:Spt:39288.0,38965.1] || -> node4(s30)*. % 76.03/76.21 39292[103:MRR:828.0,39290.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.03/76.21 39303[103:Res:53.1,39292.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.03/76.21 39305[103:MRR:39303.0,38572.0] || -> m_main_v_state(s31,c_busy)*. % 76.03/76.21 39307[103:Res:39305.0,61.1] always3(s31) || -> . % 76.03/76.21 39308[103:SSi:39307.0,720.0,38586.0,38598.0] || -> . % 76.03/76.21 39309[102:Spt:39308.0,38963.0,38964.0] || until2p7(s30)*+ -> . % 76.03/76.21 39310[102:Spt:39308.0,38963.1] || -> node4(s29)*. % 76.03/76.21 39311[102:MRR:38575.0,39310.0] || m_main_v_state(s29,c_ready)*+ -> . % 76.03/76.21 39314[102:Res:53.1,39311.0] || -> m_main_v_state(s29,c_busy)*. % 76.03/76.21 39317[102:Res:39314.0,61.1] always3(s29) || -> . % 76.03/76.21 39318[102:SSi:39317.0,718.0,38563.0,38578.0,38962.0,39310.0] || -> . % 76.03/76.21 39319[101:Spt:39318.0,38961.0,38962.0] || until2p7(s29)*+ -> . % 76.03/76.21 39320[101:Spt:39318.0,38961.1] || -> node4(s28)*. % 76.03/76.21 39322[101:MRR:834.0,39320.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.03/76.21 39334[101:Res:53.1,39322.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.03/76.21 39336[102:Spt:39334.0] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.21 39338[102:Res:39336.0,61.1] always3(s28) || -> . % 76.03/76.21 39339[102:SSi:39338.0,717.0,38560.0,38562.0,38960.0,39320.0] || -> . % 76.03/76.21 39340[102:Spt:39339.0,39334.0,39336.0] || m_main_v_state(s28,c_busy)* -> . % 76.03/76.21 39341[102:Spt:39339.0,39334.1] || -> m_main_v_state(s29,c_busy)*. % 76.03/76.21 39345[102:Res:39341.0,61.1] always3(s29) || -> . % 76.03/76.21 39346[102:SSi:39345.0,718.0,38563.0,38578.0] || -> . % 76.03/76.21 39347[100:Spt:39346.0,38959.0,38960.0] || until2p7(s28)*+ -> . % 76.03/76.21 39348[100:Spt:39346.0,38959.1] || -> node4(s27)*. % 76.03/76.21 39350[100:MRR:837.0,39348.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.03/76.21 39357[100:Res:53.1,39350.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.03/76.21 39359[101:Spt:39357.0] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.21 39361[101:Res:39359.0,61.1] always3(s27) || -> . % 76.03/76.21 39362[101:SSi:39361.0,716.0,38554.0,38559.0,38958.0,39348.0] || -> . % 76.03/76.21 39363[101:Spt:39362.0,39357.0,39359.0] || m_main_v_state(s27,c_busy)* -> . % 76.03/76.21 39364[101:Spt:39362.0,39357.1] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.21 39368[101:Res:39364.0,61.1] always3(s28) || -> . % 76.03/76.21 39369[101:SSi:39368.0,717.0,38560.0,38562.0] || -> . % 76.03/76.21 39370[99:Spt:39369.0,38957.0,38958.0] || until2p7(s27)*+ -> . % 76.03/76.21 39371[99:Spt:39369.0,38957.1] || -> node4(s26)*. % 76.03/76.21 39373[99:MRR:840.0,39371.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.03/76.21 39376[99:Res:53.1,39373.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.03/76.21 39378[100:Spt:39376.0] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.21 39380[100:Res:39378.0,61.1] always3(s26) || -> . % 76.03/76.21 39381[100:SSi:39380.0,715.0,38551.0,38553.0,38956.0,39371.0] || -> . % 76.03/76.21 39382[100:Spt:39381.0,39376.0,39378.0] || m_main_v_state(s26,c_busy)* -> . % 76.03/76.21 39383[100:Spt:39381.0,39376.1] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.21 39387[100:Res:39383.0,61.1] always3(s27) || -> . % 76.03/76.21 39388[100:SSi:39387.0,716.0,38554.0,38559.0] || -> . % 76.03/76.21 39389[98:Spt:39388.0,38955.0,38956.0] || until2p7(s26)*+ -> . % 76.03/76.21 39390[98:Spt:39388.0,38955.1] || -> node4(s25)*. % 76.03/76.21 39392[98:MRR:843.0,39390.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.03/76.21 39395[98:Res:53.1,39392.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.03/76.21 39397[99:Spt:39395.0] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.21 39399[99:Res:39397.0,61.1] always3(s25) || -> . % 76.03/76.21 39400[99:SSi:39399.0,714.0,38545.0,38550.0,38954.0,39390.0] || -> . % 76.03/76.21 39401[99:Spt:39400.0,39395.0,39397.0] || m_main_v_state(s25,c_busy)* -> . % 76.03/76.21 39402[99:Spt:39400.0,39395.1] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.21 39406[99:Res:39402.0,61.1] always3(s26) || -> . % 76.03/76.21 39407[99:SSi:39406.0,715.0,38551.0,38553.0] || -> . % 76.03/76.21 39408[97:Spt:39407.0,38953.0,38954.0] || until2p7(s25)*+ -> . % 76.03/76.21 39409[97:Spt:39407.0,38953.1] || -> node4(s24)*. % 76.03/76.21 39411[97:MRR:846.0,39409.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.03/76.21 39414[97:Res:53.1,39411.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.03/76.21 39419[98:Spt:39414.0] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.21 39421[98:Res:39419.0,61.1] always3(s24) || -> . % 76.03/76.21 39422[98:SSi:39421.0,713.0,38542.0,38544.0,38952.0,39409.0] || -> . % 76.03/76.21 39423[98:Spt:39422.0,39414.0,39419.0] || m_main_v_state(s24,c_busy)* -> . % 76.03/76.21 39424[98:Spt:39422.0,39414.1] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.21 39428[98:Res:39424.0,61.1] always3(s25) || -> . % 76.03/76.21 39429[98:SSi:39428.0,714.0,38545.0,38550.0] || -> . % 76.03/76.21 39430[96:Spt:39429.0,38951.0,38952.0] || until2p7(s24)*+ -> . % 76.03/76.21 39431[96:Spt:39429.0,38951.1] || -> node4(s23)*. % 76.03/76.21 39433[96:MRR:849.0,39431.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.03/76.21 39436[96:Res:53.1,39433.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.03/76.21 39438[97:Spt:39436.0] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.21 39440[97:Res:39438.0,61.1] always3(s23) || -> . % 76.03/76.21 39441[97:SSi:39440.0,712.0,38536.0,38541.0,38950.0,39431.0] || -> . % 76.03/76.21 39442[97:Spt:39441.0,39436.0,39438.0] || m_main_v_state(s23,c_busy)* -> . % 76.03/76.21 39443[97:Spt:39441.0,39436.1] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.21 39447[97:Res:39443.0,61.1] always3(s24) || -> . % 76.03/76.21 39448[97:SSi:39447.0,713.0,38542.0,38544.0] || -> . % 76.03/76.21 39449[95:Spt:39448.0,38949.0,38950.0] || until2p7(s23)*+ -> . % 76.03/76.21 39450[95:Spt:39448.0,38949.1] || -> node4(s22)*. % 76.03/76.21 39452[95:MRR:852.0,39450.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.03/76.21 39455[95:Res:53.1,39452.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.03/76.21 39457[96:Spt:39455.0] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.21 39459[96:Res:39457.0,61.1] always3(s22) || -> . % 76.03/76.21 39460[96:SSi:39459.0,711.0,38533.0,38535.0,38948.0,39450.0] || -> . % 76.03/76.21 39461[96:Spt:39460.0,39455.0,39457.0] || m_main_v_state(s22,c_busy)* -> . % 76.03/76.21 39462[96:Spt:39460.0,39455.1] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.21 39466[96:Res:39462.0,61.1] always3(s23) || -> . % 76.03/76.21 39467[96:SSi:39466.0,712.0,38536.0,38541.0] || -> . % 76.03/76.21 39468[94:Spt:39467.0,38947.0,38948.0] || until2p7(s22)*+ -> . % 76.03/76.21 39469[94:Spt:39467.0,38947.1] || -> node4(s21)*. % 76.03/76.21 39471[94:MRR:855.0,39469.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.03/76.21 39474[94:Res:53.1,39471.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.03/76.21 39476[95:Spt:39474.0] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.21 39478[95:Res:39476.0,61.1] always3(s21) || -> . % 76.03/76.21 39479[95:SSi:39478.0,710.0,38527.0,38532.0,38946.0,39469.0] || -> . % 76.03/76.21 39480[95:Spt:39479.0,39474.0,39476.0] || m_main_v_state(s21,c_busy)* -> . % 76.03/76.21 39481[95:Spt:39479.0,39474.1] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.21 39485[95:Res:39481.0,61.1] always3(s22) || -> . % 76.03/76.21 39486[95:SSi:39485.0,711.0,38533.0,38535.0] || -> . % 76.03/76.21 39487[93:Spt:39486.0,38943.0,38946.0] || until2p7(s21)*+ -> . % 76.03/76.21 39488[93:Spt:39486.0,38943.1] || -> node4(s20)*. % 76.03/76.21 39490[93:MRR:858.0,39488.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.03/76.21 39493[93:Res:53.1,39490.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.03/76.21 39495[93:MRR:39493.0,38928.0] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.21 39500[93:Res:39495.0,61.1] always3(s21) || -> . % 76.03/76.21 39501[93:SSi:39500.0,710.0,38527.0,38532.0] || -> . % 76.03/76.21 39502[90:Spt:39501.0,38769.2,38774.0] || xuntil6(s48)*+ -> . % 76.03/76.21 39503[90:Spt:39501.0,38769.0,38769.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.03/76.21 39504[90:Res:53.1,39503.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.03/76.21 39506[90:MRR:39504.0,38761.0] || -> m_main_v_state(s49,c_busy)*. % 76.03/76.21 39508[90:Res:39506.0,61.1] always3(s49) || -> . % 76.03/76.21 39509[90:SSi:39508.0,50.0,738.0] || -> . % 76.03/76.21 39510[89:Spt:39509.0,38765.1,38767.0] || xuntil6(s47)* -> . % 76.03/76.21 39511[89:Spt:39509.0,38765.0] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.21 39514[89:Res:39511.0,61.1] always3(s47) || -> . % 76.03/76.21 39515[89:SSi:39514.0,736.0,38755.0] || -> . % 76.03/76.21 39516[87:Spt:39515.0,38752.2,38754.0] || xuntil6(s46)*+ -> . % 76.03/76.21 39517[87:Spt:39515.0,38752.0,38752.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.03/76.21 39518[87:Res:53.1,39517.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.03/76.21 39520[87:MRR:39518.0,38741.0] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.21 39523[87:Res:39520.0,61.1] always3(s47) || -> . % 76.03/76.21 39524[87:SSi:39523.0,736.0] || -> . % 76.03/76.21 39525[86:Spt:39524.0,38745.1,38750.0] || xuntil6(s45)* -> . % 76.03/76.21 39526[86:Spt:39524.0,38745.0] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.21 39529[86:Res:39526.0,61.1] always3(s45) || -> . % 76.03/76.21 39530[86:SSi:39529.0,734.0,38735.0] || -> . % 76.03/76.21 39531[84:Spt:39530.0,38726.2,38734.0] || xuntil6(s44)*+ -> . % 76.03/76.21 39532[84:Spt:39530.0,38726.0,38726.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.03/76.21 39533[84:Res:53.1,39532.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.03/76.21 39535[84:MRR:39533.0,38718.0] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.21 39537[84:Res:39535.0,61.1] always3(s45) || -> . % 76.03/76.21 39538[84:SSi:39537.0,734.0] || -> . % 76.03/76.21 39539[83:Spt:39538.0,38722.1,38724.0] || xuntil6(s43)* -> . % 76.03/76.21 39540[83:Spt:39538.0,38722.0] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.21 39543[83:Res:39540.0,61.1] always3(s43) || -> . % 76.03/76.21 39544[83:SSi:39543.0,732.0,38712.0] || -> . % 76.03/76.21 39545[81:Spt:39544.0,38706.2,38711.0] || xuntil6(s42)*+ -> . % 76.03/76.21 39546[81:Spt:39544.0,38706.0,38706.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.03/76.21 39547[81:Res:53.1,39546.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.03/76.21 39549[81:MRR:39547.0,38698.0] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.21 39552[81:Res:39549.0,61.1] always3(s43) || -> . % 76.03/76.21 39553[81:SSi:39552.0,732.0] || -> . % 76.03/76.21 39554[80:Spt:39553.0,38702.1,38704.0] || xuntil6(s41)* -> . % 76.03/76.21 39555[80:Spt:39553.0,38702.0] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.21 39558[80:Res:39555.0,61.1] always3(s41) || -> . % 76.03/76.21 39559[80:SSi:39558.0,730.0,38692.0] || -> . % 76.03/76.21 39560[78:Spt:39559.0,38689.2,38691.0] || xuntil6(s40)*+ -> . % 76.03/76.21 39561[78:Spt:39559.0,38689.0,38689.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.03/76.21 39562[78:Res:53.1,39561.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.03/76.21 39564[78:MRR:39562.0,38678.0] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.21 39566[78:Res:39564.0,61.1] always3(s41) || -> . % 76.03/76.21 39567[78:SSi:39566.0,730.0] || -> . % 76.03/76.21 39568[77:Spt:39567.0,38682.1,38687.0] || xuntil6(s39)* -> . % 76.03/76.21 39569[77:Spt:39567.0,38682.0] || -> m_main_v_state(s39,c_busy)*. % 76.03/76.21 39572[77:Res:39569.0,61.1] always3(s39) || -> . % 76.03/76.21 39573[77:SSi:39572.0,728.0,38672.0] || -> . % 76.03/76.21 39574[75:Spt:39573.0,38663.2,38671.0] || xuntil6(s38)*+ -> . % 76.03/76.21 39575[75:Spt:39573.0,38663.0,38663.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.03/76.21 39576[75:Res:53.1,39575.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.03/76.21 39578[75:MRR:39576.0,38655.0] || -> m_main_v_state(s39,c_busy)*. % 76.03/76.21 39580[75:Res:39578.0,61.1] always3(s39) || -> . % 76.03/76.21 39581[75:SSi:39580.0,728.0] || -> . % 76.03/76.21 39582[74:Spt:39581.0,38659.1,38661.0] || xuntil6(s37)* -> . % 76.03/76.21 39583[74:Spt:39581.0,38659.0] || -> m_main_v_state(s37,c_busy)*. % 76.03/76.21 39586[74:Res:39583.0,61.1] always3(s37) || -> . % 76.03/76.21 39587[74:SSi:39586.0,726.0,38649.0] || -> . % 76.03/76.21 39588[72:Spt:39587.0,38643.2,38648.0] || xuntil6(s36)*+ -> . % 76.03/76.21 39589[72:Spt:39587.0,38643.0,38643.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.03/76.21 39590[72:Res:53.1,39589.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.03/76.21 39592[72:MRR:39590.0,38635.0] || -> m_main_v_state(s37,c_busy)*. % 76.03/76.21 39594[72:Res:39592.0,61.1] always3(s37) || -> . % 76.03/76.21 39595[72:SSi:39594.0,726.0] || -> . % 76.03/76.21 39596[71:Spt:39595.0,38639.1,38641.0] || xuntil6(s35)* -> . % 76.03/76.21 39597[71:Spt:39595.0,38639.0] || -> m_main_v_state(s35,c_busy)*. % 76.03/76.21 39600[71:Res:39597.0,61.1] always3(s35) || -> . % 76.03/76.21 39601[71:SSi:39600.0,724.0,38629.0] || -> . % 76.03/76.21 39602[69:Spt:39601.0,38626.2,38628.0] || xuntil6(s34)*+ -> . % 76.03/76.21 39603[69:Spt:39601.0,38626.0,38626.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.03/76.21 39604[69:Res:53.1,39603.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.03/76.21 39606[69:MRR:39604.0,38615.0] || -> m_main_v_state(s35,c_busy)*. % 76.03/76.21 39608[69:Res:39606.0,61.1] always3(s35) || -> . % 76.03/76.21 39609[69:SSi:39608.0,724.0] || -> . % 76.03/76.21 39610[68:Spt:39609.0,38619.1,38624.0] || xuntil6(s33)* -> . % 76.03/76.21 39611[68:Spt:39609.0,38619.0] || -> m_main_v_state(s33,c_busy)*. % 76.03/76.21 39614[68:Res:39611.0,61.1] always3(s33) || -> . % 76.03/76.21 39615[68:SSi:39614.0,722.0,38609.0] || -> . % 76.03/76.21 39616[66:Spt:39615.0,38600.2,38608.0] || xuntil6(s32)*+ -> . % 76.03/76.21 39617[66:Spt:39615.0,38600.0,38600.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.03/76.21 39618[66:Res:53.1,39617.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.03/76.21 39620[66:MRR:39618.0,38592.0] || -> m_main_v_state(s33,c_busy)*. % 76.03/76.21 39622[66:Res:39620.0,61.1] always3(s33) || -> . % 76.03/76.21 39623[66:SSi:39622.0,722.0] || -> . % 76.03/76.21 39624[65:Spt:39623.0,38596.1,38598.0] || xuntil6(s31)* -> . % 76.03/76.21 39625[65:Spt:39623.0,38596.0] || -> m_main_v_state(s31,c_busy)*. % 76.03/76.21 39628[65:Res:39625.0,61.1] always3(s31) || -> . % 76.03/76.21 39629[65:SSi:39628.0,720.0,38586.0] || -> . % 76.03/76.21 39630[63:Spt:39629.0,38580.2,38585.0] || xuntil6(s30)*+ -> . % 76.03/76.21 39631[63:Spt:39629.0,38580.0,38580.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.03/76.21 39632[63:Res:53.1,39631.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.03/76.21 39634[63:MRR:39632.0,38572.0] || -> m_main_v_state(s31,c_busy)*. % 76.03/76.21 39636[63:Res:39634.0,61.1] always3(s31) || -> . % 76.03/76.21 39637[63:SSi:39636.0,720.0] || -> . % 76.03/76.21 39638[62:Spt:39637.0,38576.1,38578.0] || xuntil6(s29)* -> . % 76.03/76.21 39639[62:Spt:39637.0,38576.0] || -> m_main_v_state(s29,c_busy)*. % 76.03/76.21 39642[62:Res:39639.0,61.1] always3(s29) || -> . % 76.03/76.21 39643[62:SSi:39642.0,718.0,38563.0] || -> . % 76.03/76.21 39644[60:Spt:39643.0,38561.2,38562.0] || xuntil6(s28)*+ -> . % 76.03/76.21 39645[60:Spt:39643.0,38561.0,38561.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.03/76.21 39646[60:Res:53.1,39645.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.03/76.21 39648[61:Spt:39646.1] || -> m_main_v_state(s29,c_busy)*. % 76.03/76.21 39650[61:Res:39648.0,61.1] always3(s29) || -> . % 76.03/76.21 39651[61:SSi:39650.0,718.0] || -> . % 76.03/76.21 39652[61:Spt:39651.0,39646.1,39648.0] || m_main_v_state(s29,c_busy)* -> . % 76.03/76.21 39653[61:Spt:39651.0,39646.0] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.21 39656[61:Res:39653.0,61.1] always3(s28) || -> . % 76.03/76.21 39657[61:SSi:39656.0,717.0,38560.0] || -> . % 76.03/76.21 39658[59:Spt:39657.0,38555.2,38559.0] || xuntil6(s27)*+ -> . % 76.03/76.21 39659[59:Spt:39657.0,38555.0,38555.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.03/76.21 39660[59:Res:53.1,39659.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.03/76.21 39662[60:Spt:39660.1] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.21 39664[60:Res:39662.0,61.1] always3(s28) || -> . % 76.03/76.21 39665[60:SSi:39664.0,717.0] || -> . % 76.03/76.21 39666[60:Spt:39665.0,39660.1,39662.0] || m_main_v_state(s28,c_busy)* -> . % 76.03/76.21 39667[60:Spt:39665.0,39660.0] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.21 39670[60:Res:39667.0,61.1] always3(s27) || -> . % 76.03/76.21 39671[60:SSi:39670.0,716.0,38554.0] || -> . % 76.03/76.21 39672[58:Spt:39671.0,38552.2,38553.0] || xuntil6(s26)*+ -> . % 76.03/76.21 39673[58:Spt:39671.0,38552.0,38552.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.03/76.21 39674[58:Res:53.1,39673.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.03/76.21 39676[59:Spt:39674.1] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.21 39678[59:Res:39676.0,61.1] always3(s27) || -> . % 76.03/76.21 39679[59:SSi:39678.0,716.0] || -> . % 76.03/76.21 39680[59:Spt:39679.0,39674.1,39676.0] || m_main_v_state(s27,c_busy)* -> . % 76.03/76.21 39681[59:Spt:39679.0,39674.0] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.21 39684[59:Res:39681.0,61.1] always3(s26) || -> . % 76.03/76.21 39685[59:SSi:39684.0,715.0,38551.0] || -> . % 76.03/76.21 39686[57:Spt:39685.0,38546.2,38550.0] || xuntil6(s25)*+ -> . % 76.03/76.21 39687[57:Spt:39685.0,38546.0,38546.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.03/76.21 39688[57:Res:53.1,39687.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.03/76.21 39690[58:Spt:39688.1] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.21 39692[58:Res:39690.0,61.1] always3(s26) || -> . % 76.03/76.21 39693[58:SSi:39692.0,715.0] || -> . % 76.03/76.21 39694[58:Spt:39693.0,39688.1,39690.0] || m_main_v_state(s26,c_busy)* -> . % 76.03/76.21 39695[58:Spt:39693.0,39688.0] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.21 39698[58:Res:39695.0,61.1] always3(s25) || -> . % 76.03/76.21 39699[58:SSi:39698.0,714.0,38545.0] || -> . % 76.03/76.21 39700[56:Spt:39699.0,38543.2,38544.0] || xuntil6(s24)*+ -> . % 76.03/76.21 39701[56:Spt:39699.0,38543.0,38543.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.03/76.21 39702[56:Res:53.1,39701.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.03/76.21 39704[57:Spt:39702.1] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.21 39706[57:Res:39704.0,61.1] always3(s25) || -> . % 76.03/76.21 39707[57:SSi:39706.0,714.0] || -> . % 76.03/76.21 39708[57:Spt:39707.0,39702.1,39704.0] || m_main_v_state(s25,c_busy)* -> . % 76.03/76.21 39709[57:Spt:39707.0,39702.0] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.21 39712[57:Res:39709.0,61.1] always3(s24) || -> . % 76.03/76.21 39713[57:SSi:39712.0,713.0,38542.0] || -> . % 76.03/76.21 39714[55:Spt:39713.0,38537.2,38541.0] || xuntil6(s23)*+ -> . % 76.03/76.21 39715[55:Spt:39713.0,38537.0,38537.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.03/76.21 39716[55:Res:53.1,39715.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.03/76.21 39718[56:Spt:39716.1] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.21 39720[56:Res:39718.0,61.1] always3(s24) || -> . % 76.03/76.21 39721[56:SSi:39720.0,713.0] || -> . % 76.03/76.21 39722[56:Spt:39721.0,39716.1,39718.0] || m_main_v_state(s24,c_busy)* -> . % 76.03/76.21 39723[56:Spt:39721.0,39716.0] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.21 39726[56:Res:39723.0,61.1] always3(s23) || -> . % 76.03/76.21 39727[56:SSi:39726.0,712.0,38536.0] || -> . % 76.03/76.21 39728[54:Spt:39727.0,38534.2,38535.0] || xuntil6(s22)*+ -> . % 76.03/76.21 39729[54:Spt:39727.0,38534.0,38534.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.03/76.21 39730[54:Res:53.1,39729.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.03/76.21 39732[55:Spt:39730.1] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.21 39734[55:Res:39732.0,61.1] always3(s23) || -> . % 76.03/76.21 39735[55:SSi:39734.0,712.0] || -> . % 76.03/76.21 39736[55:Spt:39735.0,39730.1,39732.0] || m_main_v_state(s23,c_busy)* -> . % 76.03/76.21 39737[55:Spt:39735.0,39730.0] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.21 39740[55:Res:39737.0,61.1] always3(s22) || -> . % 76.03/76.21 39741[55:SSi:39740.0,711.0,38533.0] || -> . % 76.03/76.21 39742[53:Spt:39741.0,38528.2,38532.0] || xuntil6(s21)*+ -> . % 76.03/76.21 39743[53:Spt:39741.0,38528.0,38528.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.03/76.21 39744[53:Res:53.1,39743.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.03/76.21 39749[54:Spt:39744.0] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.21 39751[54:Res:39749.0,61.1] always3(s21) || -> . % 76.03/76.21 39752[54:SSi:39751.0,710.0,38527.0] || -> . % 76.03/76.21 39753[54:Spt:39752.0,39744.0,39749.0] || m_main_v_state(s21,c_busy)* -> . % 76.03/76.21 39754[54:Spt:39752.0,39744.1] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.21 39758[54:Res:39754.0,61.1] always3(s22) || -> . % 76.03/76.21 39759[54:SSi:39758.0,711.0] || -> . % 76.03/76.21 39760[52:Spt:39759.0,38525.2,38526.0] || xuntil6(s20)*+ -> . % 76.03/76.21 39761[52:Spt:39759.0,38525.0,38525.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.03/76.21 39762[52:Res:53.1,39761.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.03/76.21 39764[53:Spt:39762.1] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.21 39766[53:Res:39764.0,61.1] always3(s21) || -> . % 76.03/76.21 39767[53:SSi:39766.0,710.0] || -> . % 76.03/76.21 39768[53:Spt:39767.0,39762.1,39764.0] || m_main_v_state(s21,c_busy)* -> . % 76.03/76.21 39769[53:Spt:39767.0,39762.0] || -> m_main_v_state(s20,c_busy)*. % 76.03/76.21 39772[53:Res:39769.0,61.1] always3(s20) || -> . % 76.03/76.21 39773[53:SSi:39772.0,709.0,38524.0] || -> . % 76.03/76.21 39774[51:Spt:39773.0,38519.2,38523.0] || xuntil6(s19)*+ -> . % 76.03/76.21 39775[51:Spt:39773.0,38519.0,38519.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.03/76.21 39776[51:Res:53.1,39775.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.03/76.21 39778[52:Spt:39776.0] || -> m_main_v_state(s19,c_busy)*. % 76.03/76.21 39780[52:Res:39778.0,61.1] always3(s19) || -> . % 76.03/76.21 39781[52:SSi:39780.0,708.0,38518.0] || -> . % 76.03/76.21 39782[52:Spt:39781.0,39776.0,39778.0] || m_main_v_state(s19,c_busy)* -> . % 76.03/76.21 39783[52:Spt:39781.0,39776.1] || -> m_main_v_state(s20,c_busy)*. % 76.03/76.21 39787[52:Res:39783.0,61.1] always3(s20) || -> . % 76.03/76.21 39788[52:SSi:39787.0,709.0] || -> . % 76.03/76.21 39789[50:Spt:39788.0,38516.2,38517.0] || xuntil6(s18)*+ -> . % 76.03/76.21 39790[50:Spt:39788.0,38516.0,38516.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.03/76.21 39791[50:Res:53.1,39790.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.03/76.21 39796[51:Spt:39791.0] || -> m_main_v_state(s18,c_busy)*. % 76.03/76.21 39798[51:Res:39796.0,61.1] always3(s18) || -> . % 76.03/76.21 39799[51:SSi:39798.0,707.0,38515.0] || -> . % 76.03/76.21 39800[51:Spt:39799.0,39791.0,39796.0] || m_main_v_state(s18,c_busy)* -> . % 76.03/76.21 39801[51:Spt:39799.0,39791.1] || -> m_main_v_state(s19,c_busy)*. % 76.03/76.21 39805[51:Res:39801.0,61.1] always3(s19) || -> . % 76.03/76.21 39806[51:SSi:39805.0,708.0] || -> . % 76.03/76.21 39807[49:Spt:39806.0,38510.2,38514.0] || xuntil6(s17)*+ -> . % 76.03/76.21 39808[49:Spt:39806.0,38510.0,38510.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.03/76.21 39809[49:Res:53.1,39808.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.03/76.21 39811[50:Spt:39809.0] || -> m_main_v_state(s17,c_busy)*. % 76.03/76.21 39813[50:Res:39811.0,61.1] always3(s17) || -> . % 76.03/76.21 39814[50:SSi:39813.0,706.0,38509.0] || -> . % 76.03/76.21 39815[50:Spt:39814.0,39809.0,39811.0] || m_main_v_state(s17,c_busy)* -> . % 76.03/76.21 39816[50:Spt:39814.0,39809.1] || -> m_main_v_state(s18,c_busy)*. % 76.03/76.21 39820[50:Res:39816.0,61.1] always3(s18) || -> . % 76.03/76.21 39821[50:SSi:39820.0,707.0] || -> . % 76.03/76.21 39822[48:Spt:39821.0,38507.2,38508.0] || xuntil6(s16)*+ -> . % 76.03/76.21 39823[48:Spt:39821.0,38507.0,38507.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.03/76.21 39824[48:Res:53.1,39823.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.03/76.21 39826[49:Spt:39824.0] || -> m_main_v_state(s16,c_busy)*. % 76.03/76.21 39828[49:Res:39826.0,61.1] always3(s16) || -> . % 76.03/76.21 39829[49:SSi:39828.0,705.0,38506.0] || -> . % 76.03/76.21 39830[49:Spt:39829.0,39824.0,39826.0] || m_main_v_state(s16,c_busy)* -> . % 76.03/76.21 39831[49:Spt:39829.0,39824.1] || -> m_main_v_state(s17,c_busy)*. % 76.03/76.21 39835[49:Res:39831.0,61.1] always3(s17) || -> . % 76.03/76.21 39836[49:SSi:39835.0,706.0] || -> . % 76.03/76.21 39837[47:Spt:39836.0,38501.2,38505.0] || xuntil6(s15)*+ -> . % 76.03/76.21 39838[47:Spt:39836.0,38501.0,38501.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.03/76.21 39839[47:Res:53.1,39838.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.03/76.21 39844[48:Spt:39839.0] || -> m_main_v_state(s15,c_busy)*. % 76.03/76.21 39846[48:Res:39844.0,61.1] always3(s15) || -> . % 76.03/76.21 39847[48:SSi:39846.0,704.0,38500.0] || -> . % 76.03/76.21 39848[48:Spt:39847.0,39839.0,39844.0] || m_main_v_state(s15,c_busy)* -> . % 76.03/76.21 39849[48:Spt:39847.0,39839.1] || -> m_main_v_state(s16,c_busy)*. % 76.03/76.21 39853[48:Res:39849.0,61.1] always3(s16) || -> . % 76.03/76.21 39854[48:SSi:39853.0,705.0] || -> . % 76.03/76.21 39855[46:Spt:39854.0,38498.2,38499.0] || xuntil6(s14)*+ -> . % 76.03/76.21 39856[46:Spt:39854.0,38498.0,38498.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.03/76.21 39857[46:Res:53.1,39856.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.03/76.21 39859[47:Spt:39857.0] || -> m_main_v_state(s14,c_busy)*. % 76.03/76.21 39861[47:Res:39859.0,61.1] always3(s14) || -> . % 76.03/76.21 39862[47:SSi:39861.0,703.0,38497.0] || -> . % 76.03/76.21 39863[47:Spt:39862.0,39857.0,39859.0] || m_main_v_state(s14,c_busy)* -> . % 76.03/76.21 39864[47:Spt:39862.0,39857.1] || -> m_main_v_state(s15,c_busy)*. % 76.03/76.21 39868[47:Res:39864.0,61.1] always3(s15) || -> . % 76.03/76.21 39869[47:SSi:39868.0,704.0] || -> . % 76.03/76.21 39870[45:Spt:39869.0,38492.2,38496.0] || xuntil6(s13)*+ -> . % 76.03/76.21 39871[45:Spt:39869.0,38492.0,38492.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.03/76.21 39872[45:Res:53.1,39871.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.03/76.21 39874[46:Spt:39872.0] || -> m_main_v_state(s13,c_busy)*. % 76.03/76.21 39876[46:Res:39874.0,61.1] always3(s13) || -> . % 76.03/76.21 39877[46:SSi:39876.0,702.0,38491.0] || -> . % 76.03/76.21 39878[46:Spt:39877.0,39872.0,39874.0] || m_main_v_state(s13,c_busy)* -> . % 76.03/76.21 39879[46:Spt:39877.0,39872.1] || -> m_main_v_state(s14,c_busy)*. % 76.03/76.21 39883[46:Res:39879.0,61.1] always3(s14) || -> . % 76.03/76.21 39884[46:SSi:39883.0,703.0] || -> . % 76.03/76.21 39885[44:Spt:39884.0,38489.2,38490.0] || xuntil6(s12)*+ -> . % 76.03/76.21 39886[44:Spt:39884.0,38489.0,38489.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.03/76.21 39887[44:Res:53.1,39886.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.03/76.21 39892[45:Spt:39887.0] || -> m_main_v_state(s12,c_busy)*. % 76.03/76.21 39894[45:Res:39892.0,61.1] always3(s12) || -> . % 76.03/76.21 39895[45:SSi:39894.0,701.0,38488.0] || -> . % 76.03/76.21 39896[45:Spt:39895.0,39887.0,39892.0] || m_main_v_state(s12,c_busy)* -> . % 76.03/76.21 39897[45:Spt:39895.0,39887.1] || -> m_main_v_state(s13,c_busy)*. % 76.03/76.21 39901[45:Res:39897.0,61.1] always3(s13) || -> . % 76.03/76.21 39902[45:SSi:39901.0,702.0] || -> . % 76.03/76.21 39903[43:Spt:39902.0,38483.2,38487.0] || xuntil6(s11)*+ -> . % 76.03/76.21 39904[43:Spt:39902.0,38483.0,38483.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.03/76.21 39905[43:Res:53.1,39904.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.03/76.21 39907[44:Spt:39905.0] || -> m_main_v_state(s11,c_busy)*. % 76.03/76.21 39909[44:Res:39907.0,61.1] always3(s11) || -> . % 76.03/76.21 39910[44:SSi:39909.0,700.0,38482.0] || -> . % 76.03/76.21 39911[44:Spt:39910.0,39905.0,39907.0] || m_main_v_state(s11,c_busy)* -> . % 76.03/76.21 39912[44:Spt:39910.0,39905.1] || -> m_main_v_state(s12,c_busy)*. % 76.03/76.21 39916[44:Res:39912.0,61.1] always3(s12) || -> . % 76.03/76.21 39917[44:SSi:39916.0,701.0] || -> . % 76.03/76.21 39918[42:Spt:39917.0,38480.2,38481.0] || xuntil6(s10)*+ -> . % 76.03/76.21 39919[42:Spt:39917.0,38480.0,38480.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.03/76.21 39920[42:Res:53.1,39919.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.03/76.21 39922[43:Spt:39920.0] || -> m_main_v_state(s10,c_busy)*. % 76.03/76.21 39924[43:Res:39922.0,61.1] always3(s10) || -> . % 76.03/76.21 39925[43:SSi:39924.0,699.0,38479.0] || -> . % 76.03/76.21 39926[43:Spt:39925.0,39920.0,39922.0] || m_main_v_state(s10,c_busy)* -> . % 76.03/76.21 39927[43:Spt:39925.0,39920.1] || -> m_main_v_state(s11,c_busy)*. % 76.03/76.21 39931[43:Res:39927.0,61.1] always3(s11) || -> . % 76.03/76.21 39932[43:SSi:39931.0,700.0] || -> . % 76.03/76.21 39933[41:Spt:39932.0,38474.2,38478.0] || xuntil6(s9)*+ -> . % 76.03/76.21 39934[41:Spt:39932.0,38474.0,38474.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.03/76.21 39935[41:Res:53.1,39934.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.03/76.21 39940[42:Spt:39935.0] || -> m_main_v_state(s9,c_busy)*. % 76.03/76.21 39942[42:Res:39940.0,61.1] always3(s9) || -> . % 76.03/76.21 39943[42:SSi:39942.0,698.0,38473.0] || -> . % 76.03/76.21 39944[42:Spt:39943.0,39935.0,39940.0] || m_main_v_state(s9,c_busy)* -> . % 76.03/76.21 39945[42:Spt:39943.0,39935.1] || -> m_main_v_state(s10,c_busy)*. % 76.03/76.21 39949[42:Res:39945.0,61.1] always3(s10) || -> . % 76.03/76.21 39950[42:SSi:39949.0,699.0] || -> . % 76.03/76.21 39951[40:Spt:39950.0,38471.2,38472.0] || xuntil6(s8)*+ -> . % 76.03/76.21 39952[40:Spt:39950.0,38471.0,38471.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.03/76.21 39953[40:Res:53.1,39952.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.03/76.21 39955[41:Spt:39953.0] || -> m_main_v_state(s8,c_busy)*. % 76.03/76.21 39957[41:Res:39955.0,61.1] always3(s8) || -> . % 76.03/76.21 39958[41:SSi:39957.0,697.0,38470.0] || -> . % 76.03/76.21 39959[41:Spt:39958.0,39953.0,39955.0] || m_main_v_state(s8,c_busy)* -> . % 76.03/76.21 39960[41:Spt:39958.0,39953.1] || -> m_main_v_state(s9,c_busy)*. % 76.03/76.21 39964[41:Res:39960.0,61.1] always3(s9) || -> . % 76.03/76.21 39965[41:SSi:39964.0,698.0] || -> . % 76.03/76.21 39966[39:Spt:39965.0,38465.2,38469.0] || xuntil6(s7)*+ -> . % 76.03/76.21 39967[39:Spt:39965.0,38465.0,38465.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.03/76.21 39968[39:Res:53.1,39967.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.03/76.21 39970[40:Spt:39968.0] || -> m_main_v_state(s7,c_busy)*. % 76.03/76.21 39972[40:Res:39970.0,61.1] always3(s7) || -> . % 76.03/76.21 39973[40:SSi:39972.0,696.0,38464.0] || -> . % 76.03/76.21 39974[40:Spt:39973.0,39968.0,39970.0] || m_main_v_state(s7,c_busy)* -> . % 76.03/76.21 39975[40:Spt:39973.0,39968.1] || -> m_main_v_state(s8,c_busy)*. % 76.03/76.21 39979[40:Res:39975.0,61.1] always3(s8) || -> . % 76.03/76.21 39980[40:SSi:39979.0,697.0] || -> . % 76.03/76.21 39981[38:Spt:39980.0,38462.2,38463.0] || xuntil6(s6)*+ -> . % 76.03/76.21 39982[38:Spt:39980.0,38462.0,38462.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.03/76.21 39983[38:Res:53.1,39982.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.03/76.21 39988[39:Spt:39983.0] || -> m_main_v_state(s6,c_busy)*. % 76.03/76.21 39990[39:Res:39988.0,61.1] always3(s6) || -> . % 76.03/76.21 39991[39:SSi:39990.0,695.0,38461.0] || -> . % 76.03/76.21 39992[39:Spt:39991.0,39983.0,39988.0] || m_main_v_state(s6,c_busy)* -> . % 76.03/76.21 39993[39:Spt:39991.0,39983.1] || -> m_main_v_state(s7,c_busy)*. % 76.03/76.21 39997[39:Res:39993.0,61.1] always3(s7) || -> . % 76.03/76.21 39998[39:SSi:39997.0,696.0] || -> . % 76.03/76.21 39999[37:Spt:39998.0,38456.2,38460.0] || xuntil6(s5)*+ -> . % 76.03/76.21 40000[37:Spt:39998.0,38456.0,38456.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.03/76.21 40001[37:Res:53.1,40000.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.03/76.21 40003[38:Spt:40001.0] || -> m_main_v_state(s5,c_busy)*. % 76.03/76.21 40005[38:Res:40003.0,61.1] always3(s5) || -> . % 76.03/76.21 40006[38:SSi:40005.0,694.0,38455.0] || -> . % 76.03/76.21 40007[38:Spt:40006.0,40001.0,40003.0] || m_main_v_state(s5,c_busy)* -> . % 76.03/76.21 40008[38:Spt:40006.0,40001.1] || -> m_main_v_state(s6,c_busy)*. % 76.03/76.21 40012[38:Res:40008.0,61.1] always3(s6) || -> . % 76.03/76.21 40013[38:SSi:40012.0,695.0] || -> . % 76.03/76.21 40014[36:Spt:40013.0,38453.2,38454.0] || xuntil6(s4)*+ -> . % 76.03/76.21 40015[36:Spt:40013.0,38453.0,38453.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.03/76.21 40016[36:Res:53.1,40015.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.03/76.21 40018[37:Spt:40016.0] || -> m_main_v_state(s4,c_busy)*. % 76.03/76.21 40020[37:Res:40018.0,61.1] always3(s4) || -> . % 76.03/76.21 40021[37:SSi:40020.0,693.0,38452.0] || -> . % 76.03/76.21 40022[37:Spt:40021.0,40016.0,40018.0] || m_main_v_state(s4,c_busy)* -> . % 76.03/76.21 40023[37:Spt:40021.0,40016.1] || -> m_main_v_state(s5,c_busy)*. % 76.03/76.21 40027[37:Res:40023.0,61.1] always3(s5) || -> . % 76.03/76.21 40028[37:SSi:40027.0,694.0] || -> . % 76.03/76.21 40029[35:Spt:40028.0,38450.2,38451.0] || xuntil6(s3)*+ -> . % 76.03/76.21 40030[35:Spt:40028.0,38450.0,38450.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.03/76.21 40031[35:Res:53.1,40030.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.03/76.21 40036[36:Spt:40031.0] || -> m_main_v_state(s3,c_busy)*. % 76.03/76.21 40038[36:Res:40036.0,61.1] always3(s3) || -> . % 76.03/76.21 40039[36:SSi:40038.0,692.0,38449.0] || -> . % 76.03/76.21 40040[36:Spt:40039.0,40031.0,40036.0] || m_main_v_state(s3,c_busy)* -> . % 76.03/76.21 40041[36:Spt:40039.0,40031.1] || -> m_main_v_state(s4,c_busy)*. % 76.03/76.21 40045[36:Res:40041.0,61.1] always3(s4) || -> . % 76.03/76.21 40046[36:SSi:40045.0,693.0] || -> . % 76.03/76.21 40047[34:Spt:40046.0,38447.2,38448.0] || xuntil6(s2)*+ -> . % 76.03/76.21 40048[34:Spt:40046.0,38447.0,38447.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.03/76.21 40049[34:Res:53.1,40048.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.03/76.21 40051[35:Spt:40049.0] || -> m_main_v_state(s2,c_busy)*. % 76.03/76.21 40053[35:Res:40051.0,61.1] always3(s2) || -> . % 76.03/76.21 40054[35:SSi:40053.0,691.0,38446.0] || -> . % 76.03/76.21 40055[35:Spt:40054.0,40049.0,40051.0] || m_main_v_state(s2,c_busy)* -> . % 76.03/76.21 40056[35:Spt:40054.0,40049.1] || -> m_main_v_state(s3,c_busy)*. % 76.03/76.21 40060[35:Res:40056.0,61.1] always3(s3) || -> . % 76.03/76.21 40061[35:SSi:40060.0,692.0] || -> . % 76.03/76.21 40062[33:Spt:40061.0,38441.2,38445.0] || xuntil6(s1)*+ -> . % 76.03/76.21 40063[33:Spt:40061.0,38441.0,38441.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.03/76.21 40064[33:Res:53.1,40063.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.03/76.21 40066[34:Spt:40064.0] || -> m_main_v_state(s1,c_busy)*. % 76.03/76.21 40068[34:Res:40066.0,61.1] always3(s1) || -> . % 76.03/76.21 40069[34:SSi:40068.0,690.0,38440.0] || -> . % 76.03/76.21 40070[34:Spt:40069.0,40064.0,40066.0] || m_main_v_state(s1,c_busy)* -> . % 76.03/76.21 40071[34:Spt:40069.0,40064.1] || -> m_main_v_state(s2,c_busy)*. % 76.03/76.21 40076[34:Res:40071.0,61.1] always3(s2) || -> . % 76.03/76.21 40077[34:SSi:40076.0,691.0] || -> . % 76.03/76.21 40078[32:Spt:40077.0,74.0,38439.0] || xuntil6(s0)*+ -> . % 76.03/76.21 40079[32:Spt:40077.0,74.1] || -> node4(s0)*. % 76.03/76.21 40080[32:MRR:758.1,40078.0] || -> m_main_v_state(s1,c_busy)*. % 76.03/76.21 40082[32:Res:40080.0,61.1] always3(s1) || -> . % 76.03/76.21 40083[32:SSi:40082.0,690.0] || -> . % 76.03/76.21 40084[31:Spt:40083.0,38429.0,38433.0] || trans(s49,s20)*+ -> . % 76.03/76.21 40085[31:Spt:40083.0,38429.1,38429.2,38429.3,38429.4,38429.5,38429.6,38429.7,38429.8,38429.9,38429.10,38429.11,38429.12,38429.13,38429.14,38429.15,38429.16,38429.17,38429.18,38429.19,38429.20] || -> trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.03/76.21 40087[31:MRR:38430.0,40084.0] || -> trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.03/76.21 40088[31:MRR:38432.1,40084.0] xuntil6(s49) || -> trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.03/76.21 40089[32:Spt:40085.0] || -> trans(s49,s19)*. % 76.03/76.21 40090[32:Res:40089.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s19)*. % 76.03/76.21 40092[32:Res:40089.0,60.0] || -> node2(s49,s19)*. % 76.03/76.21 40093[32:SSi:40090.1,50.0,738.0] xuntil6(s49) || -> until2p7(s19)*. % 76.03/76.21 40094[32:Res:40092.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)*. % 76.03/76.21 40095[33:Spt:74.0] || -> xuntil6(s0)*. % 76.03/76.21 40096[33:MRR:176.0,40095.0] || -> until5(s1)*. % 76.03/76.21 40097[33:MRR:38878.0,40096.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.03/76.21 40101[34:Spt:40097.2] || -> xuntil6(s1)*. % 76.03/76.21 40102[34:MRR:175.0,40101.0] || -> until5(s2)*. % 76.03/76.21 40103[34:MRR:38874.0,40102.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.03/76.21 40107[35:Spt:40103.2] || -> xuntil6(s2)*. % 76.03/76.21 40108[35:MRR:174.0,40107.0] || -> until5(s3)*. % 76.03/76.21 40109[35:MRR:38870.0,40108.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.03/76.21 40110[36:Spt:40109.2] || -> xuntil6(s3)*. % 76.03/76.21 40111[36:MRR:173.0,40110.0] || -> until5(s4)*. % 76.03/76.21 40112[36:MRR:38869.0,40111.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.03/76.21 40116[37:Spt:40112.2] || -> xuntil6(s4)*. % 76.03/76.21 40117[37:MRR:172.0,40116.0] || -> until5(s5)*. % 76.03/76.21 40118[37:MRR:38862.0,40117.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.03/76.21 40119[38:Spt:40118.2] || -> xuntil6(s5)*. % 76.03/76.21 40120[38:MRR:171.0,40119.0] || -> until5(s6)*. % 76.03/76.21 40121[38:MRR:38858.0,40120.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.03/76.21 40125[39:Spt:40121.2] || -> xuntil6(s6)*. % 76.03/76.21 40126[39:MRR:170.0,40125.0] || -> until5(s7)*. % 76.03/76.21 40127[39:MRR:38854.0,40126.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.03/76.21 40128[40:Spt:40127.2] || -> xuntil6(s7)*. % 76.03/76.21 40129[40:MRR:169.0,40128.0] || -> until5(s8)*. % 76.03/76.21 40130[40:MRR:38850.0,40129.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.03/76.21 40134[41:Spt:40130.2] || -> xuntil6(s8)*. % 76.03/76.21 40135[41:MRR:168.0,40134.0] || -> until5(s9)*. % 76.03/76.21 40136[41:MRR:38849.0,40135.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.03/76.21 40137[42:Spt:40136.2] || -> xuntil6(s9)*. % 76.03/76.21 40138[42:MRR:167.0,40137.0] || -> until5(s10)*. % 76.03/76.21 40139[42:MRR:38842.0,40138.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.03/76.21 40143[43:Spt:40139.2] || -> xuntil6(s10)*. % 76.03/76.21 40144[43:MRR:166.0,40143.0] || -> until5(s11)*. % 76.03/76.21 40145[43:MRR:38838.0,40144.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.03/76.21 40146[44:Spt:40145.2] || -> xuntil6(s11)*. % 76.03/76.21 40147[44:MRR:165.0,40146.0] || -> until5(s12)*. % 76.03/76.21 40148[44:MRR:38834.0,40147.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.03/76.21 40152[45:Spt:40148.2] || -> xuntil6(s12)*. % 76.03/76.21 40153[45:MRR:164.0,40152.0] || -> until5(s13)*. % 76.03/76.21 40154[45:MRR:38830.0,40153.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.03/76.21 40155[46:Spt:40154.2] || -> xuntil6(s13)*. % 76.03/76.21 40156[46:MRR:163.0,40155.0] || -> until5(s14)*. % 76.03/76.21 40157[46:MRR:38829.0,40156.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.03/76.21 40161[47:Spt:40157.2] || -> xuntil6(s14)*. % 76.03/76.21 40162[47:MRR:162.0,40161.0] || -> until5(s15)*. % 76.03/76.21 40163[47:MRR:38822.0,40162.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.03/76.21 40164[48:Spt:40163.2] || -> xuntil6(s15)*. % 76.03/76.21 40165[48:MRR:161.0,40164.0] || -> until5(s16)*. % 76.03/76.21 40166[48:MRR:38818.0,40165.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.03/76.21 40170[49:Spt:40166.2] || -> xuntil6(s16)*. % 76.03/76.21 40171[49:MRR:160.0,40170.0] || -> until5(s17)*. % 76.03/76.21 40172[49:MRR:38814.0,40171.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.03/76.21 40173[50:Spt:40172.2] || -> xuntil6(s17)*. % 76.03/76.21 40174[50:MRR:159.0,40173.0] || -> until5(s18)*. % 76.03/76.21 40175[50:MRR:38810.0,40174.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.03/76.21 40179[51:Spt:40175.2] || -> xuntil6(s18)*. % 76.03/76.21 40180[51:MRR:158.0,40179.0] || -> until5(s19)*. % 76.03/76.21 40181[51:MRR:38809.0,40180.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.03/76.21 40182[52:Spt:40181.2] || -> xuntil6(s19)*. % 76.03/76.21 40183[52:MRR:157.0,40182.0] || -> until5(s20)*. % 76.03/76.21 40184[52:MRR:38802.0,40183.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.03/76.21 40188[53:Spt:40184.2] || -> xuntil6(s20)*. % 76.03/76.21 40189[53:MRR:156.0,40188.0] || -> until5(s21)*. % 76.03/76.21 40190[53:MRR:38798.0,40189.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.03/76.21 40191[54:Spt:40190.2] || -> xuntil6(s21)*. % 76.03/76.21 40192[54:MRR:155.0,40191.0] || -> until5(s22)*. % 76.03/76.21 40193[54:MRR:38791.0,40192.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.03/76.21 40197[55:Spt:40193.2] || -> xuntil6(s22)*. % 76.03/76.21 40198[55:MRR:154.0,40197.0] || -> until5(s23)*. % 76.03/76.21 40199[55:MRR:38787.0,40198.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.03/76.21 40200[56:Spt:40199.2] || -> xuntil6(s23)*. % 76.03/76.21 40201[56:MRR:153.0,40200.0] || -> until5(s24)*. % 76.03/76.21 40202[56:MRR:38783.0,40201.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.03/76.21 40206[57:Spt:40202.2] || -> xuntil6(s24)*. % 76.03/76.21 40207[57:MRR:152.0,40206.0] || -> until5(s25)*. % 76.03/76.21 40208[57:MRR:38782.0,40207.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.03/76.21 40209[58:Spt:40208.2] || -> xuntil6(s25)*. % 76.03/76.21 40210[58:MRR:151.0,40209.0] || -> until5(s26)*. % 76.03/76.21 40211[58:MRR:38781.0,40210.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.03/76.21 40215[59:Spt:40211.2] || -> xuntil6(s26)*. % 76.03/76.21 40216[59:MRR:150.0,40215.0] || -> until5(s27)*. % 76.03/76.21 40217[59:MRR:38780.0,40216.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.03/76.21 40218[60:Spt:40217.2] || -> xuntil6(s27)*. % 76.03/76.21 40219[60:MRR:149.0,40218.0] || -> until5(s28)*. % 76.03/76.21 40220[60:MRR:38776.0,40219.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.03/76.21 40224[61:Spt:40220.2] || -> xuntil6(s28)*. % 76.03/76.21 40225[61:MRR:148.0,40224.0] || -> until5(s29)*. % 76.03/76.21 40226[61:MRR:35647.0,40225.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.03/76.21 40227[62:Spt:40226.1] || -> m_main_v_state(s30,c_busy)*. % 76.03/76.21 40229[62:Res:40227.0,61.1] always3(s30) || -> . % 76.03/76.21 40230[62:SSi:40229.0,719.0] || -> . % 76.03/76.21 40231[62:Spt:40230.0,40226.1,40227.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.03/76.21 40232[62:Spt:40230.0,40226.0,40226.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 76.03/76.21 40234[62:MRR:831.2,40231.0] node4(s29) || m_main_v_state(s29,c_ready)* -> . % 76.03/76.21 40235[62:Res:53.1,40232.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 76.03/76.21 40240[63:Spt:40235.1] || -> xuntil6(s29)*. % 76.03/76.21 40241[63:MRR:147.0,40240.0] || -> until5(s30)*. % 76.03/76.21 40242[63:MRR:38885.0,40241.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.03/76.21 40244[64:Spt:40242.2] || -> xuntil6(s30)*. % 76.03/76.21 40245[64:MRR:146.0,40244.0] || -> until5(s31)*. % 76.03/76.21 40246[64:MRR:35651.0,40245.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.03/76.21 40247[65:Spt:40246.1] || -> m_main_v_state(s32,c_busy)*. % 76.03/76.21 40249[65:Res:40247.0,61.1] always3(s32) || -> . % 76.03/76.21 40250[65:SSi:40249.0,721.0] || -> . % 76.03/76.21 40251[65:Spt:40250.0,40246.1,40247.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.03/76.21 40252[65:Spt:40250.0,40246.0,40246.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.03/76.21 40254[65:MRR:825.2,40251.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.03/76.21 40255[65:Res:53.1,40252.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.03/76.21 40257[66:Spt:40255.1] || -> xuntil6(s31)*. % 76.03/76.21 40258[66:MRR:145.0,40257.0] || -> until5(s32)*. % 76.03/76.21 40259[66:MRR:38889.0,40258.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.03/76.21 40264[67:Spt:40259.2] || -> xuntil6(s32)*. % 76.03/76.21 40265[67:MRR:144.0,40264.0] || -> until5(s33)*. % 76.03/76.21 40266[67:MRR:35655.0,40265.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.03/76.21 40267[68:Spt:40266.1] || -> m_main_v_state(s34,c_busy)*. % 76.03/76.21 40269[68:Res:40267.0,61.1] always3(s34) || -> . % 76.03/76.21 40270[68:SSi:40269.0,723.0] || -> . % 76.03/76.21 40271[68:Spt:40270.0,40266.1,40267.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.03/76.21 40272[68:Spt:40270.0,40266.0,40266.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.03/76.21 40274[68:MRR:819.2,40271.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.03/76.21 40275[68:Res:53.1,40272.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.03/76.21 40277[69:Spt:40275.1] || -> xuntil6(s33)*. % 76.03/76.21 40278[69:MRR:143.0,40277.0] || -> until5(s34)*. % 76.03/76.21 40279[69:MRR:38893.0,40278.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.03/76.21 40287[70:Spt:40279.2] || -> xuntil6(s34)*. % 76.03/76.21 40288[70:MRR:142.0,40287.0] || -> until5(s35)*. % 76.03/76.21 40289[70:MRR:35659.0,40288.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.03/76.21 40290[71:Spt:40289.1] || -> m_main_v_state(s36,c_busy)*. % 76.03/76.21 40292[71:Res:40290.0,61.1] always3(s36) || -> . % 76.03/76.21 40293[71:SSi:40292.0,725.0] || -> . % 76.03/76.21 40294[71:Spt:40293.0,40289.1,40290.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.03/76.21 40295[71:Spt:40293.0,40289.0,40289.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.03/76.21 40297[71:MRR:813.2,40294.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.03/76.21 40298[71:Res:53.1,40295.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.03/76.21 40303[72:Spt:40298.1] || -> xuntil6(s35)*. % 76.03/76.21 40304[72:MRR:141.0,40303.0] || -> until5(s36)*. % 76.03/76.21 40305[72:MRR:38900.0,40304.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.03/76.21 40307[73:Spt:40305.2] || -> xuntil6(s36)*. % 76.03/76.21 40308[73:MRR:140.0,40307.0] || -> until5(s37)*. % 76.03/76.21 40309[73:MRR:35666.0,40308.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.03/76.21 40310[74:Spt:40309.1] || -> m_main_v_state(s38,c_busy)*. % 76.03/76.21 40312[74:Res:40310.0,61.1] always3(s38) || -> . % 76.03/76.21 40313[74:SSi:40312.0,727.0] || -> . % 76.03/76.21 40314[74:Spt:40313.0,40309.1,40310.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.03/76.21 40315[74:Spt:40313.0,40309.0,40309.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.03/76.21 40317[74:MRR:807.2,40314.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.03/76.21 40318[74:Res:53.1,40315.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.03/76.21 40320[75:Spt:40318.1] || -> xuntil6(s37)*. % 76.03/76.21 40321[75:MRR:139.0,40320.0] || -> until5(s38)*. % 76.03/76.22 40322[75:MRR:38901.0,40321.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.03/76.22 40327[76:Spt:40322.2] || -> xuntil6(s38)*. % 76.03/76.22 40328[76:MRR:138.0,40327.0] || -> until5(s39)*. % 76.03/76.22 40329[76:MRR:35667.0,40328.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.03/76.22 40330[77:Spt:40329.1] || -> m_main_v_state(s40,c_busy)*. % 76.03/76.22 40332[77:Res:40330.0,61.1] always3(s40) || -> . % 76.03/76.22 40333[77:SSi:40332.0,729.0] || -> . % 76.03/76.22 40334[77:Spt:40333.0,40329.1,40330.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.03/76.22 40335[77:Spt:40333.0,40329.0,40329.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.03/76.22 40337[77:MRR:801.2,40334.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.03/76.22 40338[77:Res:53.1,40335.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.03/76.22 40340[78:Spt:40338.1] || -> xuntil6(s39)*. % 76.03/76.22 40341[78:MRR:137.0,40340.0] || -> until5(s40)*. % 76.03/76.22 40342[78:MRR:38905.0,40341.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.03/76.22 40350[79:Spt:40342.2] || -> xuntil6(s40)*. % 76.03/76.22 40351[79:MRR:136.0,40350.0] || -> until5(s41)*. % 76.03/76.22 40352[79:MRR:35671.0,40351.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.03/76.22 40353[80:Spt:40352.1] || -> m_main_v_state(s42,c_busy)*. % 76.03/76.22 40355[80:Res:40353.0,61.1] always3(s42) || -> . % 76.03/76.22 40356[80:SSi:40355.0,731.0] || -> . % 76.03/76.22 40357[80:Spt:40356.0,40352.1,40353.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.03/76.22 40358[80:Spt:40356.0,40352.0,40352.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.03/76.22 40360[80:MRR:795.2,40357.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.03/76.22 40361[80:Res:53.1,40358.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.03/76.22 40366[81:Spt:40361.1] || -> xuntil6(s41)*. % 76.03/76.22 40367[81:MRR:135.0,40366.0] || -> until5(s42)*. % 76.03/76.22 40368[81:MRR:38909.0,40367.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.03/76.22 40370[82:Spt:40368.2] || -> xuntil6(s42)*. % 76.03/76.22 40371[82:MRR:134.0,40370.0] || -> until5(s43)*. % 76.03/76.22 40372[82:MRR:35675.0,40371.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.03/76.22 40373[83:Spt:40372.1] || -> m_main_v_state(s44,c_busy)*. % 76.03/76.22 40375[83:Res:40373.0,61.1] always3(s44) || -> . % 76.03/76.22 40376[83:SSi:40375.0,733.0] || -> . % 76.03/76.22 40377[83:Spt:40376.0,40372.1,40373.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.03/76.22 40378[83:Spt:40376.0,40372.0,40372.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.03/76.22 40380[83:MRR:789.2,40377.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.03/76.22 40381[83:Res:53.1,40378.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.03/76.22 40383[84:Spt:40381.1] || -> xuntil6(s43)*. % 76.03/76.22 40384[84:MRR:133.0,40383.0] || -> until5(s44)*. % 76.03/76.22 40385[84:MRR:38913.0,40384.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.03/76.22 40390[85:Spt:40385.2] || -> xuntil6(s44)*. % 76.03/76.22 40391[85:MRR:132.0,40390.0] || -> until5(s45)*. % 76.03/76.22 40392[85:MRR:35679.0,40391.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.03/76.22 40393[86:Spt:40392.1] || -> m_main_v_state(s46,c_busy)*. % 76.03/76.22 40395[86:Res:40393.0,61.1] always3(s46) || -> . % 76.03/76.22 40396[86:SSi:40395.0,735.0] || -> . % 76.03/76.22 40397[86:Spt:40396.0,40392.1,40393.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.03/76.22 40398[86:Spt:40396.0,40392.0,40392.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.03/76.22 40400[86:MRR:783.2,40397.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.03/76.22 40401[86:Res:53.1,40398.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.03/76.22 40403[87:Spt:40401.1] || -> xuntil6(s45)*. % 76.03/76.22 40404[87:MRR:131.0,40403.0] || -> until5(s46)*. % 76.03/76.22 40405[87:MRR:38920.0,40404.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.03/76.22 40413[88:Spt:40405.2] || -> xuntil6(s46)*. % 76.03/76.22 40414[88:MRR:130.0,40413.0] || -> until5(s47)*. % 76.03/76.22 40415[88:MRR:35683.0,40414.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.03/76.22 40416[89:Spt:40415.1] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.22 40418[89:Res:40416.0,61.1] always3(s48) || -> . % 76.03/76.22 40419[89:SSi:40418.0,737.0] || -> . % 76.03/76.22 40420[89:Spt:40419.0,40415.1,40416.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.03/76.22 40421[89:Spt:40419.0,40415.0,40415.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.03/76.22 40423[89:MRR:777.2,40420.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.03/76.22 40424[89:Res:53.1,40421.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.03/76.22 40429[90:Spt:40424.1] || -> xuntil6(s47)*. % 76.03/76.22 40430[90:MRR:129.0,40429.0] || -> until5(s48)*. % 76.03/76.22 40431[90:MRR:38921.0,40430.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.03/76.22 40433[91:Spt:40431.2] || -> xuntil6(s48)*. % 76.03/76.22 40434[91:MRR:128.0,40433.0] || -> until5(s49)*. % 76.03/76.22 40435[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.03/76.22 40436[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.03/76.22 40437[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.03/76.22 40438[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.03/76.22 40442[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.03/76.22 40446[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.03/76.22 40453[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.03/76.22 40454[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.03/76.22 40464[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.03/76.22 40465[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.03/76.22 40469[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.03/76.22 40473[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.03/76.22 40477[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.03/76.22 40484[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.03/76.22 40485[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.03/76.22 40489[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.03/76.22 40493[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.03/76.22 40497[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.03/76.22 40504[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.03/76.22 40505[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.03/76.22 40509[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.03/76.22 40513[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.03/76.22 40517[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.03/76.22 40524[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.03/76.22 40525[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.03/76.22 40529[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.03/76.22 40533[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.03/76.22 40537[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.03/76.22 40539[32:SoR:40094.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)*. % 76.03/76.22 40544[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.03/76.22 40548[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.03/76.22 40555[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.03/76.22 40556[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.03/76.22 40560[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.03/76.22 40564[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.03/76.22 40568[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.03/76.22 40575[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.03/76.22 40576[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.03/76.22 40580[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.03/76.22 40581[32:SoR:40539.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)* xuntil6(s49). % 76.03/76.22 40582[91:SSi:40581.0,50.0,738.0,40434.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s19,c_busy)* xuntil6(s49). % 76.03/76.22 40583[92:Spt:40582.1] || -> m_main_v_state(s19,c_busy)*. % 76.03/76.22 40585[92:Res:40583.0,61.1] always3(s19) || -> . % 76.03/76.22 40586[92:SSi:40585.0,708.0,40180.0,40182.0] || -> . % 76.03/76.22 40587[92:Spt:40586.0,40582.1,40583.0] || m_main_v_state(s19,c_busy)*+ -> . % 76.03/76.22 40588[92:Spt:40586.0,40582.0,40582.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.03/76.22 40592[92:MRR:40539.2,40587.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.03/76.22 40593[92:Res:53.1,40588.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.03/76.22 40595[93:Spt:40593.0] || -> m_main_v_state(s49,c_busy)*. % 76.03/76.22 40597[93:Res:40595.0,61.1] always3(s49) || -> . % 76.03/76.22 40598[93:SSi:40597.0,50.0,738.0,40434.0] || -> . % 76.03/76.22 40599[93:Spt:40598.0,40593.0,40595.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.03/76.22 40600[93:Spt:40598.0,40593.1] || -> xuntil6(s49)*. % 76.03/76.22 40601[93:MRR:40093.0,40600.0] || -> until2p7(s19)*. % 76.03/76.22 40602[93:MRR:215.0,40601.0] || -> until2p7(s20)* node4(s19). % 76.03/76.22 40604[93:MRR:774.2,40599.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.03/76.22 40605[94:Spt:40602.0] || -> until2p7(s20)*. % 76.03/76.22 40606[94:MRR:216.0,40605.0] || -> until2p7(s21)* node4(s20). % 76.03/76.22 40607[95:Spt:40606.0] || -> until2p7(s21)*. % 76.03/76.22 40608[95:MRR:217.0,40607.0] || -> until2p7(s22)* node4(s21). % 76.03/76.22 40609[96:Spt:40608.0] || -> until2p7(s22)*. % 76.03/76.22 40610[96:MRR:218.0,40609.0] || -> until2p7(s23)* node4(s22). % 76.03/76.22 40611[97:Spt:40610.0] || -> until2p7(s23)*. % 76.03/76.22 40612[97:MRR:219.0,40611.0] || -> until2p7(s24)* node4(s23). % 76.03/76.22 40613[98:Spt:40612.0] || -> until2p7(s24)*. % 76.03/76.22 40614[98:MRR:220.0,40613.0] || -> until2p7(s25)* node4(s24). % 76.03/76.22 40615[99:Spt:40614.0] || -> until2p7(s25)*. % 76.03/76.22 40616[99:MRR:221.0,40615.0] || -> until2p7(s26)* node4(s25). % 76.03/76.22 40617[100:Spt:40616.0] || -> until2p7(s26)*. % 76.03/76.22 40618[100:MRR:222.0,40617.0] || -> until2p7(s27)* node4(s26). % 76.03/76.22 40619[101:Spt:40618.0] || -> until2p7(s27)*. % 76.03/76.22 40620[101:MRR:223.0,40619.0] || -> until2p7(s28)* node4(s27). % 76.03/76.22 40621[102:Spt:40620.0] || -> until2p7(s28)*. % 76.03/76.22 40622[102:MRR:224.0,40621.0] || -> until2p7(s29)* node4(s28). % 76.03/76.22 40623[103:Spt:40622.0] || -> until2p7(s29)*. % 76.03/76.22 40624[103:MRR:225.0,40623.0] || -> until2p7(s30)* node4(s29). % 76.03/76.22 40625[104:Spt:40624.0] || -> until2p7(s30)*. % 76.03/76.22 40626[104:MRR:226.0,40625.0] || -> until2p7(s31)* node4(s30). % 76.03/76.22 40627[105:Spt:40626.0] || -> until2p7(s31)*. % 76.03/76.22 40628[105:MRR:227.0,40627.0] || -> until2p7(s32)* node4(s31). % 76.03/76.22 40629[106:Spt:40628.0] || -> until2p7(s32)*. % 76.03/76.22 40630[106:MRR:228.0,40629.0] || -> until2p7(s33)* node4(s32). % 76.03/76.22 40631[107:Spt:40630.0] || -> until2p7(s33)*. % 76.03/76.22 40632[107:MRR:229.0,40631.0] || -> until2p7(s34)* node4(s33). % 76.03/76.22 40633[108:Spt:40632.0] || -> until2p7(s34)*. % 76.03/76.22 40634[108:MRR:230.0,40633.0] || -> until2p7(s35)* node4(s34). % 76.03/76.22 40635[109:Spt:40634.0] || -> until2p7(s35)*. % 76.03/76.22 40636[109:MRR:231.0,40635.0] || -> until2p7(s36)* node4(s35). % 76.03/76.22 40637[110:Spt:40636.0] || -> until2p7(s36)*. % 76.03/76.22 40638[110:MRR:232.0,40637.0] || -> until2p7(s37)* node4(s36). % 76.03/76.22 40639[111:Spt:40638.0] || -> until2p7(s37)*. % 76.03/76.22 40640[111:MRR:235.0,40639.0] || -> until2p7(s38)* node4(s37). % 76.03/76.22 40641[112:Spt:40640.0] || -> until2p7(s38)*. % 76.03/76.22 40642[112:MRR:236.0,40641.0] || -> until2p7(s39)* node4(s38). % 76.03/76.22 40643[113:Spt:40642.0] || -> until2p7(s39)*. % 76.03/76.22 40644[113:MRR:237.0,40643.0] || -> until2p7(s40)* node4(s39). % 76.03/76.22 40645[114:Spt:40644.0] || -> until2p7(s40)*. % 76.03/76.22 40646[114:MRR:238.0,40645.0] || -> until2p7(s41)* node4(s40). % 76.03/76.22 40647[115:Spt:40646.0] || -> until2p7(s41)*. % 76.03/76.22 40648[115:MRR:239.0,40647.0] || -> until2p7(s42)* node4(s41). % 76.03/76.22 40649[116:Spt:40648.0] || -> until2p7(s42)*. % 76.03/76.22 40650[116:MRR:240.0,40649.0] || -> until2p7(s43)* node4(s42). % 76.03/76.22 40651[117:Spt:40650.0] || -> until2p7(s43)*. % 76.03/76.22 40652[117:MRR:241.0,40651.0] || -> until2p7(s44)* node4(s43). % 76.03/76.22 40653[118:Spt:40652.0] || -> until2p7(s44)*. % 76.03/76.22 40654[118:MRR:539.0,40653.0] || -> until2p7(s45)* node4(s44). % 76.03/76.22 40655[119:Spt:40654.0] || -> until2p7(s45)*. % 76.03/76.22 40656[119:MRR:544.0,40655.0] || -> until2p7(s46)* node4(s45). % 76.03/76.22 40657[120:Spt:40656.0] || -> until2p7(s46)*. % 76.03/76.22 40658[120:MRR:549.0,40657.0] || -> until2p7(s47)* node4(s46). % 76.03/76.22 40659[121:Spt:40658.0] || -> until2p7(s47)*. % 76.03/76.22 40660[121:MRR:554.0,40659.0] || -> until2p7(s48)* node4(s47). % 76.03/76.22 40661[122:Spt:40660.0] || -> until2p7(s48)*. % 76.03/76.22 40662[122:MRR:559.0,40661.0] || -> until2p7(s49)* node4(s48). % 76.03/76.22 40663[123:Spt:40662.0] || -> until2p7(s49)*. % 76.03/76.22 40664[123:MRR:194.0,40663.0] || -> node4(s49)*. % 76.03/76.22 40665[123:MRR:40592.0,40664.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.03/76.22 40666[123:Res:53.1,40665.0] || -> m_main_v_state(s49,c_busy)*. % 76.03/76.22 40668[123:MRR:40666.0,40599.0] || -> . % 76.03/76.22 40669[123:Spt:40668.0,40662.0,40663.0] || until2p7(s49)*+ -> . % 76.03/76.22 40670[123:Spt:40668.0,40662.1] || -> node4(s48)*. % 76.03/76.22 40671[123:MRR:40604.0,40670.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.03/76.22 40674[123:Res:53.1,40671.0] || -> m_main_v_state(s48,c_busy)*. % 76.03/76.22 40676[123:MRR:40674.0,40420.0] || -> . % 76.03/76.22 40677[122:Spt:40676.0,40660.0,40661.0] || until2p7(s48)*+ -> . % 76.03/76.22 40678[122:Spt:40676.0,40660.1] || -> node4(s47)*. % 76.03/76.22 40679[122:MRR:40423.0,40678.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.03/76.22 40682[122:Res:53.1,40679.0] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.22 40686[122:Res:40682.0,61.1] always3(s47) || -> . % 76.03/76.22 40687[122:SSi:40686.0,736.0,40414.0,40429.0,40659.0,40678.0] || -> . % 76.03/76.22 40688[121:Spt:40687.0,40658.0,40659.0] || until2p7(s47)*+ -> . % 76.03/76.22 40689[121:Spt:40687.0,40658.1] || -> node4(s46)*. % 76.03/76.22 40691[121:MRR:780.0,40689.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.03/76.22 40713[121:Res:53.1,40691.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.03/76.22 40715[121:MRR:40713.0,40397.0] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.22 40717[121:Res:40715.0,61.1] always3(s47) || -> . % 76.03/76.22 40718[121:SSi:40717.0,736.0,40414.0,40429.0] || -> . % 76.03/76.22 40719[120:Spt:40718.0,40656.0,40657.0] || until2p7(s46)*+ -> . % 76.03/76.22 40720[120:Spt:40718.0,40656.1] || -> node4(s45)*. % 76.03/76.22 40721[120:MRR:40400.0,40720.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.03/76.22 40725[120:Res:53.1,40721.0] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.22 40728[120:Res:40725.0,61.1] always3(s45) || -> . % 76.03/76.22 40729[120:SSi:40728.0,734.0,40391.0,40403.0,40655.0,40720.0] || -> . % 76.03/76.22 40730[119:Spt:40729.0,40654.0,40655.0] || until2p7(s45)*+ -> . % 76.03/76.22 40731[119:Spt:40729.0,40654.1] || -> node4(s44)*. % 76.03/76.22 40733[119:MRR:786.0,40731.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.03/76.22 40744[119:Res:53.1,40733.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.03/76.22 40746[119:MRR:40744.0,40377.0] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.22 40748[119:Res:40746.0,61.1] always3(s45) || -> . % 76.03/76.22 40749[119:SSi:40748.0,734.0,40391.0,40403.0] || -> . % 76.03/76.22 40750[118:Spt:40749.0,40652.0,40653.0] || until2p7(s44)*+ -> . % 76.03/76.22 40751[118:Spt:40749.0,40652.1] || -> node4(s43)*. % 76.03/76.22 40752[118:MRR:40380.0,40751.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.03/76.22 40755[118:Res:53.1,40752.0] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.22 40758[118:Res:40755.0,61.1] always3(s43) || -> . % 76.03/76.22 40759[118:SSi:40758.0,732.0,40371.0,40383.0,40651.0,40751.0] || -> . % 76.03/76.22 40760[117:Spt:40759.0,40650.0,40651.0] || until2p7(s43)*+ -> . % 76.03/76.22 40761[117:Spt:40759.0,40650.1] || -> node4(s42)*. % 76.03/76.22 40763[117:MRR:792.0,40761.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.03/76.22 40775[117:Res:53.1,40763.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.03/76.22 40777[117:MRR:40775.0,40357.0] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.22 40779[117:Res:40777.0,61.1] always3(s43) || -> . % 76.03/76.22 40780[117:SSi:40779.0,732.0,40371.0,40383.0] || -> . % 76.03/76.22 40781[116:Spt:40780.0,40648.0,40649.0] || until2p7(s42)*+ -> . % 76.03/76.22 40782[116:Spt:40780.0,40648.1] || -> node4(s41)*. % 76.03/76.22 40783[116:MRR:40360.0,40782.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.03/76.22 40786[116:Res:53.1,40783.0] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.22 40789[116:Res:40786.0,61.1] always3(s41) || -> . % 76.03/76.22 40790[116:SSi:40789.0,730.0,40351.0,40366.0,40647.0,40782.0] || -> . % 76.03/76.22 40791[115:Spt:40790.0,40646.0,40647.0] || until2p7(s41)*+ -> . % 76.03/76.22 40792[115:Spt:40790.0,40646.1] || -> node4(s40)*. % 76.03/76.22 40794[115:MRR:798.0,40792.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.03/76.22 40806[115:Res:53.1,40794.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.03/76.22 40808[115:MRR:40806.0,40334.0] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.22 40813[115:Res:40808.0,61.1] always3(s41) || -> . % 76.03/76.22 40814[115:SSi:40813.0,730.0,40351.0,40366.0] || -> . % 76.03/76.22 40815[114:Spt:40814.0,40644.0,40645.0] || until2p7(s40)*+ -> . % 76.03/76.22 40816[114:Spt:40814.0,40644.1] || -> node4(s39)*. % 76.03/76.22 40817[114:MRR:40337.0,40816.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.03/76.22 40820[114:Res:53.1,40817.0] || -> m_main_v_state(s39,c_busy)*. % 76.03/76.22 40824[114:Res:40820.0,61.1] always3(s39) || -> . % 76.03/76.22 40825[114:SSi:40824.0,728.0,40328.0,40340.0,40643.0,40816.0] || -> . % 76.03/76.22 40826[113:Spt:40825.0,40642.0,40643.0] || until2p7(s39)*+ -> . % 76.03/76.22 40827[113:Spt:40825.0,40642.1] || -> node4(s38)*. % 76.03/76.22 40829[113:MRR:804.0,40827.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.03/76.22 40840[113:Res:53.1,40829.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.03/76.22 40842[113:MRR:40840.0,40314.0] || -> m_main_v_state(s39,c_busy)*. % 76.03/76.22 40844[113:Res:40842.0,61.1] always3(s39) || -> . % 76.03/76.22 40845[113:SSi:40844.0,728.0,40328.0,40340.0] || -> . % 76.03/76.22 40846[112:Spt:40845.0,40640.0,40641.0] || until2p7(s38)*+ -> . % 76.03/76.22 40847[112:Spt:40845.0,40640.1] || -> node4(s37)*. % 76.03/76.22 40848[112:MRR:40317.0,40847.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.03/76.22 40852[112:Res:53.1,40848.0] || -> m_main_v_state(s37,c_busy)*. % 76.03/76.22 40855[112:Res:40852.0,61.1] always3(s37) || -> . % 76.03/76.22 40856[112:SSi:40855.0,726.0,40308.0,40320.0,40639.0,40847.0] || -> . % 76.03/76.22 40857[111:Spt:40856.0,40638.0,40639.0] || until2p7(s37)*+ -> . % 76.03/76.22 40858[111:Spt:40856.0,40638.1] || -> node4(s36)*. % 76.03/76.22 40860[111:MRR:810.0,40858.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.03/76.22 40871[111:Res:53.1,40860.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.03/76.22 40873[111:MRR:40871.0,40294.0] || -> m_main_v_state(s37,c_busy)*. % 76.03/76.22 40875[111:Res:40873.0,61.1] always3(s37) || -> . % 76.03/76.22 40876[111:SSi:40875.0,726.0,40308.0,40320.0] || -> . % 76.03/76.22 40877[110:Spt:40876.0,40636.0,40637.0] || until2p7(s36)*+ -> . % 76.03/76.22 40878[110:Spt:40876.0,40636.1] || -> node4(s35)*. % 76.03/76.22 40879[110:MRR:40297.0,40878.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.03/76.22 40882[110:Res:53.1,40879.0] || -> m_main_v_state(s35,c_busy)*. % 76.03/76.22 40885[110:Res:40882.0,61.1] always3(s35) || -> . % 76.03/76.22 40886[110:SSi:40885.0,724.0,40288.0,40303.0,40635.0,40878.0] || -> . % 76.03/76.22 40887[109:Spt:40886.0,40634.0,40635.0] || until2p7(s35)*+ -> . % 76.03/76.22 40888[109:Spt:40886.0,40634.1] || -> node4(s34)*. % 76.03/76.22 40890[109:MRR:816.0,40888.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.03/76.22 40902[109:Res:53.1,40890.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.03/76.22 40904[109:MRR:40902.0,40271.0] || -> m_main_v_state(s35,c_busy)*. % 76.03/76.22 40906[109:Res:40904.0,61.1] always3(s35) || -> . % 76.03/76.22 40907[109:SSi:40906.0,724.0,40288.0,40303.0] || -> . % 76.03/76.22 40908[108:Spt:40907.0,40632.0,40633.0] || until2p7(s34)*+ -> . % 76.03/76.22 40909[108:Spt:40907.0,40632.1] || -> node4(s33)*. % 76.03/76.22 40910[108:MRR:40274.0,40909.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.03/76.22 40913[108:Res:53.1,40910.0] || -> m_main_v_state(s33,c_busy)*. % 76.03/76.22 40916[108:Res:40913.0,61.1] always3(s33) || -> . % 76.03/76.22 40917[108:SSi:40916.0,722.0,40265.0,40277.0,40631.0,40909.0] || -> . % 76.03/76.22 40918[107:Spt:40917.0,40630.0,40631.0] || until2p7(s33)*+ -> . % 76.03/76.22 40919[107:Spt:40917.0,40630.1] || -> node4(s32)*. % 76.03/76.22 40921[107:MRR:822.0,40919.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.03/76.22 40933[107:Res:53.1,40921.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.03/76.22 40935[107:MRR:40933.0,40251.0] || -> m_main_v_state(s33,c_busy)*. % 76.03/76.22 40940[107:Res:40935.0,61.1] always3(s33) || -> . % 76.03/76.22 40941[107:SSi:40940.0,722.0,40265.0,40277.0] || -> . % 76.03/76.22 40942[106:Spt:40941.0,40628.0,40629.0] || until2p7(s32)*+ -> . % 76.03/76.22 40943[106:Spt:40941.0,40628.1] || -> node4(s31)*. % 76.03/76.22 40944[106:MRR:40254.0,40943.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.03/76.22 40947[106:Res:53.1,40944.0] || -> m_main_v_state(s31,c_busy)*. % 76.03/76.22 40951[106:Res:40947.0,61.1] always3(s31) || -> . % 76.03/76.22 40952[106:SSi:40951.0,720.0,40245.0,40257.0,40627.0,40943.0] || -> . % 76.03/76.22 40953[105:Spt:40952.0,40626.0,40627.0] || until2p7(s31)*+ -> . % 76.03/76.22 40954[105:Spt:40952.0,40626.1] || -> node4(s30)*. % 76.03/76.22 40956[105:MRR:828.0,40954.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.03/76.22 40967[105:Res:53.1,40956.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.03/76.22 40969[105:MRR:40967.0,40231.0] || -> m_main_v_state(s31,c_busy)*. % 76.03/76.22 40971[105:Res:40969.0,61.1] always3(s31) || -> . % 76.03/76.22 40972[105:SSi:40971.0,720.0,40245.0,40257.0] || -> . % 76.03/76.22 40973[104:Spt:40972.0,40624.0,40625.0] || until2p7(s30)*+ -> . % 76.03/76.22 40974[104:Spt:40972.0,40624.1] || -> node4(s29)*. % 76.03/76.22 40975[104:MRR:40234.0,40974.0] || m_main_v_state(s29,c_ready)*+ -> . % 76.03/76.22 40979[104:Res:53.1,40975.0] || -> m_main_v_state(s29,c_busy)*. % 76.03/76.22 40982[104:Res:40979.0,61.1] always3(s29) || -> . % 76.03/76.22 40983[104:SSi:40982.0,718.0,40225.0,40240.0,40623.0,40974.0] || -> . % 76.03/76.22 40984[103:Spt:40983.0,40622.0,40623.0] || until2p7(s29)*+ -> . % 76.03/76.22 40985[103:Spt:40983.0,40622.1] || -> node4(s28)*. % 76.03/76.22 40987[103:MRR:834.0,40985.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.03/76.22 40998[103:Res:53.1,40987.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.03/76.22 41000[104:Spt:40998.0] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.22 41002[104:Res:41000.0,61.1] always3(s28) || -> . % 76.03/76.22 41003[104:SSi:41002.0,717.0,40219.0,40224.0,40621.0,40985.0] || -> . % 76.03/76.22 41004[104:Spt:41003.0,40998.0,41000.0] || m_main_v_state(s28,c_busy)* -> . % 76.03/76.22 41005[104:Spt:41003.0,40998.1] || -> m_main_v_state(s29,c_busy)*. % 76.03/76.22 41009[104:Res:41005.0,61.1] always3(s29) || -> . % 76.03/76.22 41010[104:SSi:41009.0,718.0,40225.0,40240.0] || -> . % 76.03/76.22 41011[102:Spt:41010.0,40620.0,40621.0] || until2p7(s28)*+ -> . % 76.03/76.22 41012[102:Spt:41010.0,40620.1] || -> node4(s27)*. % 76.03/76.22 41014[102:MRR:837.0,41012.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.03/76.22 41024[102:Res:53.1,41014.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.03/76.22 41026[103:Spt:41024.0] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.22 41028[103:Res:41026.0,61.1] always3(s27) || -> . % 76.03/76.22 41029[103:SSi:41028.0,716.0,40216.0,40218.0,40619.0,41012.0] || -> . % 76.03/76.22 41030[103:Spt:41029.0,41024.0,41026.0] || m_main_v_state(s27,c_busy)* -> . % 76.03/76.22 41031[103:Spt:41029.0,41024.1] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.22 41035[103:Res:41031.0,61.1] always3(s28) || -> . % 76.03/76.22 41036[103:SSi:41035.0,717.0,40219.0,40224.0] || -> . % 76.03/76.22 41037[101:Spt:41036.0,40618.0,40619.0] || until2p7(s27)*+ -> . % 76.03/76.22 41038[101:Spt:41036.0,40618.1] || -> node4(s26)*. % 76.03/76.22 41040[101:MRR:840.0,41038.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.03/76.22 41043[101:Res:53.1,41040.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.03/76.22 41045[102:Spt:41043.0] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.22 41047[102:Res:41045.0,61.1] always3(s26) || -> . % 76.03/76.22 41048[102:SSi:41047.0,715.0,40210.0,40215.0,40617.0,41038.0] || -> . % 76.03/76.22 41049[102:Spt:41048.0,41043.0,41045.0] || m_main_v_state(s26,c_busy)* -> . % 76.03/76.22 41050[102:Spt:41048.0,41043.1] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.22 41054[102:Res:41050.0,61.1] always3(s27) || -> . % 76.03/76.22 41055[102:SSi:41054.0,716.0,40216.0,40218.0] || -> . % 76.03/76.22 41056[100:Spt:41055.0,40616.0,40617.0] || until2p7(s26)*+ -> . % 76.03/76.22 41057[100:Spt:41055.0,40616.1] || -> node4(s25)*. % 76.03/76.22 41059[100:MRR:843.0,41057.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.03/76.22 41062[100:Res:53.1,41059.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.03/76.22 41064[101:Spt:41062.0] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.22 41066[101:Res:41064.0,61.1] always3(s25) || -> . % 76.03/76.22 41067[101:SSi:41066.0,714.0,40207.0,40209.0,40615.0,41057.0] || -> . % 76.03/76.22 41068[101:Spt:41067.0,41062.0,41064.0] || m_main_v_state(s25,c_busy)* -> . % 76.03/76.22 41069[101:Spt:41067.0,41062.1] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.22 41073[101:Res:41069.0,61.1] always3(s26) || -> . % 76.03/76.22 41074[101:SSi:41073.0,715.0,40210.0,40215.0] || -> . % 76.03/76.22 41075[99:Spt:41074.0,40614.0,40615.0] || until2p7(s25)*+ -> . % 76.03/76.22 41076[99:Spt:41074.0,40614.1] || -> node4(s24)*. % 76.03/76.22 41078[99:MRR:846.0,41076.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.03/76.22 41081[99:Res:53.1,41078.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.03/76.22 41086[100:Spt:41081.0] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.22 41088[100:Res:41086.0,61.1] always3(s24) || -> . % 76.03/76.22 41089[100:SSi:41088.0,713.0,40201.0,40206.0,40613.0,41076.0] || -> . % 76.03/76.22 41090[100:Spt:41089.0,41081.0,41086.0] || m_main_v_state(s24,c_busy)* -> . % 76.03/76.22 41091[100:Spt:41089.0,41081.1] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.22 41095[100:Res:41091.0,61.1] always3(s25) || -> . % 76.03/76.22 41096[100:SSi:41095.0,714.0,40207.0,40209.0] || -> . % 76.03/76.22 41097[98:Spt:41096.0,40612.0,40613.0] || until2p7(s24)*+ -> . % 76.03/76.22 41098[98:Spt:41096.0,40612.1] || -> node4(s23)*. % 76.03/76.22 41100[98:MRR:849.0,41098.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.03/76.22 41103[98:Res:53.1,41100.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.03/76.22 41105[99:Spt:41103.0] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.22 41107[99:Res:41105.0,61.1] always3(s23) || -> . % 76.03/76.22 41108[99:SSi:41107.0,712.0,40198.0,40200.0,40611.0,41098.0] || -> . % 76.03/76.22 41109[99:Spt:41108.0,41103.0,41105.0] || m_main_v_state(s23,c_busy)* -> . % 76.03/76.22 41110[99:Spt:41108.0,41103.1] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.22 41114[99:Res:41110.0,61.1] always3(s24) || -> . % 76.03/76.22 41115[99:SSi:41114.0,713.0,40201.0,40206.0] || -> . % 76.03/76.22 41116[97:Spt:41115.0,40610.0,40611.0] || until2p7(s23)*+ -> . % 76.03/76.22 41117[97:Spt:41115.0,40610.1] || -> node4(s22)*. % 76.03/76.22 41119[97:MRR:852.0,41117.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.03/76.22 41122[97:Res:53.1,41119.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.03/76.22 41124[98:Spt:41122.0] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.22 41126[98:Res:41124.0,61.1] always3(s22) || -> . % 76.03/76.22 41127[98:SSi:41126.0,711.0,40192.0,40197.0,40609.0,41117.0] || -> . % 76.03/76.22 41128[98:Spt:41127.0,41122.0,41124.0] || m_main_v_state(s22,c_busy)* -> . % 76.03/76.22 41129[98:Spt:41127.0,41122.1] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.22 41133[98:Res:41129.0,61.1] always3(s23) || -> . % 76.03/76.22 41134[98:SSi:41133.0,712.0,40198.0,40200.0] || -> . % 76.03/76.22 41135[96:Spt:41134.0,40608.0,40609.0] || until2p7(s22)*+ -> . % 76.03/76.22 41136[96:Spt:41134.0,40608.1] || -> node4(s21)*. % 76.03/76.22 41138[96:MRR:855.0,41136.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.03/76.22 41141[96:Res:53.1,41138.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.03/76.22 41143[97:Spt:41141.0] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.22 41145[97:Res:41143.0,61.1] always3(s21) || -> . % 76.03/76.22 41146[97:SSi:41145.0,710.0,40189.0,40191.0,40607.0,41136.0] || -> . % 76.03/76.22 41147[97:Spt:41146.0,41141.0,41143.0] || m_main_v_state(s21,c_busy)* -> . % 76.03/76.22 41148[97:Spt:41146.0,41141.1] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.22 41152[97:Res:41148.0,61.1] always3(s22) || -> . % 76.03/76.22 41153[97:SSi:41152.0,711.0,40192.0,40197.0] || -> . % 76.03/76.22 41154[95:Spt:41153.0,40606.0,40607.0] || until2p7(s21)*+ -> . % 76.03/76.22 41155[95:Spt:41153.0,40606.1] || -> node4(s20)*. % 76.03/76.22 41157[95:MRR:858.0,41155.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.03/76.22 41160[95:Res:53.1,41157.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.03/76.22 41165[96:Spt:41160.0] || -> m_main_v_state(s20,c_busy)*. % 76.03/76.22 41167[96:Res:41165.0,61.1] always3(s20) || -> . % 76.03/76.22 41168[96:SSi:41167.0,709.0,40183.0,40188.0,40605.0,41155.0] || -> . % 76.03/76.22 41169[96:Spt:41168.0,41160.0,41165.0] || m_main_v_state(s20,c_busy)* -> . % 76.03/76.22 41170[96:Spt:41168.0,41160.1] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.22 41174[96:Res:41170.0,61.1] always3(s21) || -> . % 76.03/76.22 41175[96:SSi:41174.0,710.0,40189.0,40191.0] || -> . % 76.03/76.22 41176[94:Spt:41175.0,40602.0,40605.0] || until2p7(s20)*+ -> . % 76.03/76.22 41177[94:Spt:41175.0,40602.1] || -> node4(s19)*. % 76.03/76.22 41179[94:MRR:861.0,41177.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.03/76.22 41182[94:Res:53.1,41179.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.03/76.22 41184[94:MRR:41182.0,40587.0] || -> m_main_v_state(s20,c_busy)*. % 76.03/76.22 41186[94:Res:41184.0,61.1] always3(s20) || -> . % 76.03/76.22 41187[94:SSi:41186.0,709.0,40183.0,40188.0] || -> . % 76.03/76.22 41188[91:Spt:41187.0,40431.2,40433.0] || xuntil6(s48)*+ -> . % 76.03/76.22 41189[91:Spt:41187.0,40431.0,40431.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.03/76.22 41190[91:Res:53.1,41189.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.03/76.22 41192[91:MRR:41190.0,40420.0] || -> m_main_v_state(s49,c_busy)*. % 76.03/76.22 41194[91:Res:41192.0,61.1] always3(s49) || -> . % 76.03/76.22 41195[91:SSi:41194.0,50.0,738.0] || -> . % 76.03/76.22 41196[90:Spt:41195.0,40424.1,40429.0] || xuntil6(s47)* -> . % 76.03/76.22 41197[90:Spt:41195.0,40424.0] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.22 41200[90:Res:41197.0,61.1] always3(s47) || -> . % 76.03/76.22 41201[90:SSi:41200.0,736.0,40414.0] || -> . % 76.03/76.22 41202[88:Spt:41201.0,40405.2,40413.0] || xuntil6(s46)*+ -> . % 76.03/76.22 41203[88:Spt:41201.0,40405.0,40405.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.03/76.22 41204[88:Res:53.1,41203.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.03/76.22 41206[88:MRR:41204.0,40397.0] || -> m_main_v_state(s47,c_busy)*. % 76.03/76.22 41208[88:Res:41206.0,61.1] always3(s47) || -> . % 76.03/76.22 41209[88:SSi:41208.0,736.0] || -> . % 76.03/76.22 41210[87:Spt:41209.0,40401.1,40403.0] || xuntil6(s45)* -> . % 76.03/76.22 41211[87:Spt:41209.0,40401.0] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.22 41214[87:Res:41211.0,61.1] always3(s45) || -> . % 76.03/76.22 41215[87:SSi:41214.0,734.0,40391.0] || -> . % 76.03/76.22 41216[85:Spt:41215.0,40385.2,40390.0] || xuntil6(s44)*+ -> . % 76.03/76.22 41217[85:Spt:41215.0,40385.0,40385.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.03/76.22 41218[85:Res:53.1,41217.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.03/76.22 41220[85:MRR:41218.0,40377.0] || -> m_main_v_state(s45,c_busy)*. % 76.03/76.22 41222[85:Res:41220.0,61.1] always3(s45) || -> . % 76.03/76.22 41223[85:SSi:41222.0,734.0] || -> . % 76.03/76.22 41224[84:Spt:41223.0,40381.1,40383.0] || xuntil6(s43)* -> . % 76.03/76.22 41225[84:Spt:41223.0,40381.0] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.22 41228[84:Res:41225.0,61.1] always3(s43) || -> . % 76.03/76.22 41229[84:SSi:41228.0,732.0,40371.0] || -> . % 76.03/76.22 41230[82:Spt:41229.0,40368.2,40370.0] || xuntil6(s42)*+ -> . % 76.03/76.22 41231[82:Spt:41229.0,40368.0,40368.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.03/76.22 41232[82:Res:53.1,41231.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.03/76.22 41234[82:MRR:41232.0,40357.0] || -> m_main_v_state(s43,c_busy)*. % 76.03/76.22 41237[82:Res:41234.0,61.1] always3(s43) || -> . % 76.03/76.22 41238[82:SSi:41237.0,732.0] || -> . % 76.03/76.22 41239[81:Spt:41238.0,40361.1,40366.0] || xuntil6(s41)* -> . % 76.03/76.22 41240[81:Spt:41238.0,40361.0] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.22 41243[81:Res:41240.0,61.1] always3(s41) || -> . % 76.03/76.22 41244[81:SSi:41243.0,730.0,40351.0] || -> . % 76.03/76.22 41245[79:Spt:41244.0,40342.2,40350.0] || xuntil6(s40)*+ -> . % 76.03/76.22 41246[79:Spt:41244.0,40342.0,40342.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.03/76.22 41247[79:Res:53.1,41246.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.03/76.22 41249[79:MRR:41247.0,40334.0] || -> m_main_v_state(s41,c_busy)*. % 76.03/76.22 41251[79:Res:41249.0,61.1] always3(s41) || -> . % 76.03/76.22 41252[79:SSi:41251.0,730.0] || -> . % 76.03/76.22 41253[78:Spt:41252.0,40338.1,40340.0] || xuntil6(s39)* -> . % 76.03/76.22 41254[78:Spt:41252.0,40338.0] || -> m_main_v_state(s39,c_busy)*. % 76.03/76.22 41257[78:Res:41254.0,61.1] always3(s39) || -> . % 76.03/76.22 41258[78:SSi:41257.0,728.0,40328.0] || -> . % 76.03/76.22 41259[76:Spt:41258.0,40322.2,40327.0] || xuntil6(s38)*+ -> . % 76.03/76.22 41260[76:Spt:41258.0,40322.0,40322.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.03/76.22 41261[76:Res:53.1,41260.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.03/76.22 41263[76:MRR:41261.0,40314.0] || -> m_main_v_state(s39,c_busy)*. % 76.03/76.22 41266[76:Res:41263.0,61.1] always3(s39) || -> . % 76.03/76.22 41267[76:SSi:41266.0,728.0] || -> . % 76.03/76.22 41268[75:Spt:41267.0,40318.1,40320.0] || xuntil6(s37)* -> . % 76.03/76.22 41269[75:Spt:41267.0,40318.0] || -> m_main_v_state(s37,c_busy)*. % 76.03/76.22 41272[75:Res:41269.0,61.1] always3(s37) || -> . % 76.03/76.22 41273[75:SSi:41272.0,726.0,40308.0] || -> . % 76.03/76.22 41274[73:Spt:41273.0,40305.2,40307.0] || xuntil6(s36)*+ -> . % 76.03/76.22 41275[73:Spt:41273.0,40305.0,40305.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.03/76.22 41276[73:Res:53.1,41275.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.03/76.22 41278[73:MRR:41276.0,40294.0] || -> m_main_v_state(s37,c_busy)*. % 76.03/76.22 41280[73:Res:41278.0,61.1] always3(s37) || -> . % 76.03/76.22 41281[73:SSi:41280.0,726.0] || -> . % 76.03/76.22 41282[72:Spt:41281.0,40298.1,40303.0] || xuntil6(s35)* -> . % 76.03/76.22 41283[72:Spt:41281.0,40298.0] || -> m_main_v_state(s35,c_busy)*. % 76.03/76.22 41286[72:Res:41283.0,61.1] always3(s35) || -> . % 76.03/76.22 41287[72:SSi:41286.0,724.0,40288.0] || -> . % 76.03/76.22 41288[70:Spt:41287.0,40279.2,40287.0] || xuntil6(s34)*+ -> . % 76.03/76.22 41289[70:Spt:41287.0,40279.0,40279.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.03/76.22 41290[70:Res:53.1,41289.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.03/76.22 41292[70:MRR:41290.0,40271.0] || -> m_main_v_state(s35,c_busy)*. % 76.03/76.22 41294[70:Res:41292.0,61.1] always3(s35) || -> . % 76.03/76.22 41295[70:SSi:41294.0,724.0] || -> . % 76.03/76.22 41296[69:Spt:41295.0,40275.1,40277.0] || xuntil6(s33)* -> . % 76.03/76.22 41297[69:Spt:41295.0,40275.0] || -> m_main_v_state(s33,c_busy)*. % 76.03/76.22 41300[69:Res:41297.0,61.1] always3(s33) || -> . % 76.03/76.22 41301[69:SSi:41300.0,722.0,40265.0] || -> . % 76.03/76.22 41302[67:Spt:41301.0,40259.2,40264.0] || xuntil6(s32)*+ -> . % 76.03/76.22 41303[67:Spt:41301.0,40259.0,40259.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.03/76.22 41304[67:Res:53.1,41303.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.03/76.22 41306[67:MRR:41304.0,40251.0] || -> m_main_v_state(s33,c_busy)*. % 76.03/76.22 41308[67:Res:41306.0,61.1] always3(s33) || -> . % 76.03/76.22 41309[67:SSi:41308.0,722.0] || -> . % 76.03/76.22 41310[66:Spt:41309.0,40255.1,40257.0] || xuntil6(s31)* -> . % 76.03/76.22 41311[66:Spt:41309.0,40255.0] || -> m_main_v_state(s31,c_busy)*. % 76.03/76.22 41314[66:Res:41311.0,61.1] always3(s31) || -> . % 76.03/76.22 41315[66:SSi:41314.0,720.0,40245.0] || -> . % 76.03/76.22 41316[64:Spt:41315.0,40242.2,40244.0] || xuntil6(s30)*+ -> . % 76.03/76.22 41317[64:Spt:41315.0,40242.0,40242.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.03/76.22 41318[64:Res:53.1,41317.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.03/76.22 41320[64:MRR:41318.0,40231.0] || -> m_main_v_state(s31,c_busy)*. % 76.03/76.22 41322[64:Res:41320.0,61.1] always3(s31) || -> . % 76.03/76.22 41323[64:SSi:41322.0,720.0] || -> . % 76.03/76.22 41324[63:Spt:41323.0,40235.1,40240.0] || xuntil6(s29)* -> . % 76.03/76.22 41325[63:Spt:41323.0,40235.0] || -> m_main_v_state(s29,c_busy)*. % 76.03/76.22 41328[63:Res:41325.0,61.1] always3(s29) || -> . % 76.03/76.22 41329[63:SSi:41328.0,718.0,40225.0] || -> . % 76.03/76.22 41330[61:Spt:41329.0,40220.2,40224.0] || xuntil6(s28)*+ -> . % 76.03/76.22 41331[61:Spt:41329.0,40220.0,40220.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.03/76.22 41332[61:Res:53.1,41331.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.03/76.22 41334[62:Spt:41332.1] || -> m_main_v_state(s29,c_busy)*. % 76.03/76.22 41336[62:Res:41334.0,61.1] always3(s29) || -> . % 76.03/76.22 41337[62:SSi:41336.0,718.0] || -> . % 76.03/76.22 41338[62:Spt:41337.0,41332.1,41334.0] || m_main_v_state(s29,c_busy)* -> . % 76.03/76.22 41339[62:Spt:41337.0,41332.0] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.22 41342[62:Res:41339.0,61.1] always3(s28) || -> . % 76.03/76.22 41343[62:SSi:41342.0,717.0,40219.0] || -> . % 76.03/76.22 41344[60:Spt:41343.0,40217.2,40218.0] || xuntil6(s27)*+ -> . % 76.03/76.22 41345[60:Spt:41343.0,40217.0,40217.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.03/76.22 41346[60:Res:53.1,41345.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.03/76.22 41348[61:Spt:41346.1] || -> m_main_v_state(s28,c_busy)*. % 76.03/76.22 41350[61:Res:41348.0,61.1] always3(s28) || -> . % 76.03/76.22 41351[61:SSi:41350.0,717.0] || -> . % 76.03/76.22 41352[61:Spt:41351.0,41346.1,41348.0] || m_main_v_state(s28,c_busy)* -> . % 76.03/76.22 41353[61:Spt:41351.0,41346.0] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.22 41356[61:Res:41353.0,61.1] always3(s27) || -> . % 76.03/76.22 41357[61:SSi:41356.0,716.0,40216.0] || -> . % 76.03/76.22 41358[59:Spt:41357.0,40211.2,40215.0] || xuntil6(s26)*+ -> . % 76.03/76.22 41359[59:Spt:41357.0,40211.0,40211.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.03/76.22 41360[59:Res:53.1,41359.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.03/76.22 41362[60:Spt:41360.1] || -> m_main_v_state(s27,c_busy)*. % 76.03/76.22 41364[60:Res:41362.0,61.1] always3(s27) || -> . % 76.03/76.22 41365[60:SSi:41364.0,716.0] || -> . % 76.03/76.22 41366[60:Spt:41365.0,41360.1,41362.0] || m_main_v_state(s27,c_busy)* -> . % 76.03/76.22 41367[60:Spt:41365.0,41360.0] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.22 41370[60:Res:41367.0,61.1] always3(s26) || -> . % 76.03/76.22 41371[60:SSi:41370.0,715.0,40210.0] || -> . % 76.03/76.22 41372[58:Spt:41371.0,40208.2,40209.0] || xuntil6(s25)*+ -> . % 76.03/76.22 41373[58:Spt:41371.0,40208.0,40208.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.03/76.22 41374[58:Res:53.1,41373.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.03/76.22 41376[59:Spt:41374.1] || -> m_main_v_state(s26,c_busy)*. % 76.03/76.22 41378[59:Res:41376.0,61.1] always3(s26) || -> . % 76.03/76.22 41379[59:SSi:41378.0,715.0] || -> . % 76.03/76.22 41380[59:Spt:41379.0,41374.1,41376.0] || m_main_v_state(s26,c_busy)* -> . % 76.03/76.22 41381[59:Spt:41379.0,41374.0] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.22 41384[59:Res:41381.0,61.1] always3(s25) || -> . % 76.03/76.22 41385[59:SSi:41384.0,714.0,40207.0] || -> . % 76.03/76.22 41386[57:Spt:41385.0,40202.2,40206.0] || xuntil6(s24)*+ -> . % 76.03/76.22 41387[57:Spt:41385.0,40202.0,40202.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.03/76.22 41388[57:Res:53.1,41387.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.03/76.22 41390[58:Spt:41388.1] || -> m_main_v_state(s25,c_busy)*. % 76.03/76.22 41392[58:Res:41390.0,61.1] always3(s25) || -> . % 76.03/76.22 41393[58:SSi:41392.0,714.0] || -> . % 76.03/76.22 41394[58:Spt:41393.0,41388.1,41390.0] || m_main_v_state(s25,c_busy)* -> . % 76.03/76.22 41395[58:Spt:41393.0,41388.0] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.22 41398[58:Res:41395.0,61.1] always3(s24) || -> . % 76.03/76.22 41399[58:SSi:41398.0,713.0,40201.0] || -> . % 76.03/76.22 41400[56:Spt:41399.0,40199.2,40200.0] || xuntil6(s23)*+ -> . % 76.03/76.22 41401[56:Spt:41399.0,40199.0,40199.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.03/76.22 41402[56:Res:53.1,41401.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.03/76.22 41404[57:Spt:41402.1] || -> m_main_v_state(s24,c_busy)*. % 76.03/76.22 41406[57:Res:41404.0,61.1] always3(s24) || -> . % 76.03/76.22 41407[57:SSi:41406.0,713.0] || -> . % 76.03/76.22 41408[57:Spt:41407.0,41402.1,41404.0] || m_main_v_state(s24,c_busy)* -> . % 76.03/76.22 41409[57:Spt:41407.0,41402.0] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.22 41412[57:Res:41409.0,61.1] always3(s23) || -> . % 76.03/76.22 41413[57:SSi:41412.0,712.0,40198.0] || -> . % 76.03/76.22 41414[55:Spt:41413.0,40193.2,40197.0] || xuntil6(s22)*+ -> . % 76.03/76.22 41415[55:Spt:41413.0,40193.0,40193.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.03/76.22 41416[55:Res:53.1,41415.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.03/76.22 41418[56:Spt:41416.1] || -> m_main_v_state(s23,c_busy)*. % 76.03/76.22 41420[56:Res:41418.0,61.1] always3(s23) || -> . % 76.03/76.22 41421[56:SSi:41420.0,712.0] || -> . % 76.03/76.22 41422[56:Spt:41421.0,41416.1,41418.0] || m_main_v_state(s23,c_busy)* -> . % 76.03/76.22 41423[56:Spt:41421.0,41416.0] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.22 41426[56:Res:41423.0,61.1] always3(s22) || -> . % 76.03/76.22 41427[56:SSi:41426.0,711.0,40192.0] || -> . % 76.03/76.22 41428[54:Spt:41427.0,40190.2,40191.0] || xuntil6(s21)*+ -> . % 76.03/76.22 41429[54:Spt:41427.0,40190.0,40190.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.03/76.22 41430[54:Res:53.1,41429.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.03/76.22 41432[55:Spt:41430.1] || -> m_main_v_state(s22,c_busy)*. % 76.03/76.22 41434[55:Res:41432.0,61.1] always3(s22) || -> . % 76.03/76.22 41435[55:SSi:41434.0,711.0] || -> . % 76.03/76.22 41436[55:Spt:41435.0,41430.1,41432.0] || m_main_v_state(s22,c_busy)* -> . % 76.03/76.22 41437[55:Spt:41435.0,41430.0] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.22 41440[55:Res:41437.0,61.1] always3(s21) || -> . % 76.03/76.22 41441[55:SSi:41440.0,710.0,40189.0] || -> . % 76.03/76.22 41442[53:Spt:41441.0,40184.2,40188.0] || xuntil6(s20)*+ -> . % 76.03/76.22 41443[53:Spt:41441.0,40184.0,40184.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.03/76.22 41444[53:Res:53.1,41443.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.03/76.22 41446[54:Spt:41444.1] || -> m_main_v_state(s21,c_busy)*. % 76.03/76.22 41448[54:Res:41446.0,61.1] always3(s21) || -> . % 76.03/76.22 41449[54:SSi:41448.0,710.0] || -> . % 76.03/76.22 41450[54:Spt:41449.0,41444.1,41446.0] || m_main_v_state(s21,c_busy)* -> . % 76.03/76.22 41451[54:Spt:41449.0,41444.0] || -> m_main_v_state(s20,c_busy)*. % 76.03/76.22 41454[54:Res:41451.0,61.1] always3(s20) || -> . % 76.03/76.22 41455[54:SSi:41454.0,709.0,40183.0] || -> . % 76.03/76.22 41456[52:Spt:41455.0,40181.2,40182.0] || xuntil6(s19)*+ -> . % 76.03/76.22 41457[52:Spt:41455.0,40181.0,40181.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.03/76.22 41458[52:Res:53.1,41457.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.03/76.22 41460[53:Spt:41458.1] || -> m_main_v_state(s20,c_busy)*. % 76.03/76.22 41462[53:Res:41460.0,61.1] always3(s20) || -> . % 76.03/76.22 41463[53:SSi:41462.0,709.0] || -> . % 76.03/76.22 41464[53:Spt:41463.0,41458.1,41460.0] || m_main_v_state(s20,c_busy)* -> . % 76.03/76.22 41465[53:Spt:41463.0,41458.0] || -> m_main_v_state(s19,c_busy)*. % 76.03/76.22 41468[53:Res:41465.0,61.1] always3(s19) || -> . % 76.03/76.22 41469[53:SSi:41468.0,708.0,40180.0] || -> . % 76.03/76.22 41470[51:Spt:41469.0,40175.2,40179.0] || xuntil6(s18)*+ -> . % 76.03/76.22 41471[51:Spt:41469.0,40175.0,40175.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.03/76.22 41472[51:Res:53.1,41471.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.03/76.22 41477[52:Spt:41472.0] || -> m_main_v_state(s18,c_busy)*. % 76.03/76.22 41479[52:Res:41477.0,61.1] always3(s18) || -> . % 76.03/76.22 41480[52:SSi:41479.0,707.0,40174.0] || -> . % 76.03/76.22 41481[52:Spt:41480.0,41472.0,41477.0] || m_main_v_state(s18,c_busy)* -> . % 76.03/76.22 41482[52:Spt:41480.0,41472.1] || -> m_main_v_state(s19,c_busy)*. % 76.03/76.22 41486[52:Res:41482.0,61.1] always3(s19) || -> . % 76.03/76.22 41487[52:SSi:41486.0,708.0] || -> . % 76.03/76.22 41488[50:Spt:41487.0,40172.2,40173.0] || xuntil6(s17)*+ -> . % 76.03/76.22 41489[50:Spt:41487.0,40172.0,40172.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.03/76.22 41490[50:Res:53.1,41489.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.03/76.22 41492[51:Spt:41490.0] || -> m_main_v_state(s17,c_busy)*. % 76.03/76.22 41494[51:Res:41492.0,61.1] always3(s17) || -> . % 76.03/76.22 41495[51:SSi:41494.0,706.0,40171.0] || -> . % 76.03/76.22 41496[51:Spt:41495.0,41490.0,41492.0] || m_main_v_state(s17,c_busy)* -> . % 76.03/76.22 41497[51:Spt:41495.0,41490.1] || -> m_main_v_state(s18,c_busy)*. % 76.03/76.22 41501[51:Res:41497.0,61.1] always3(s18) || -> . % 76.03/76.22 41502[51:SSi:41501.0,707.0] || -> . % 76.03/76.22 41503[49:Spt:41502.0,40166.2,40170.0] || xuntil6(s16)*+ -> . % 76.03/76.22 41504[49:Spt:41502.0,40166.0,40166.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.03/76.22 41505[49:Res:53.1,41504.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.03/76.22 41507[50:Spt:41505.0] || -> m_main_v_state(s16,c_busy)*. % 76.03/76.22 41509[50:Res:41507.0,61.1] always3(s16) || -> . % 76.03/76.22 41510[50:SSi:41509.0,705.0,40165.0] || -> . % 76.03/76.22 41511[50:Spt:41510.0,41505.0,41507.0] || m_main_v_state(s16,c_busy)* -> . % 76.03/76.22 41512[50:Spt:41510.0,41505.1] || -> m_main_v_state(s17,c_busy)*. % 76.03/76.22 41516[50:Res:41512.0,61.1] always3(s17) || -> . % 76.03/76.22 41517[50:SSi:41516.0,706.0] || -> . % 76.03/76.22 41518[48:Spt:41517.0,40163.2,40164.0] || xuntil6(s15)*+ -> . % 76.03/76.22 41519[48:Spt:41517.0,40163.0,40163.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.03/76.22 41520[48:Res:53.1,41519.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.03/76.22 41525[49:Spt:41520.0] || -> m_main_v_state(s15,c_busy)*. % 76.03/76.22 41527[49:Res:41525.0,61.1] always3(s15) || -> . % 76.03/76.22 41528[49:SSi:41527.0,704.0,40162.0] || -> . % 76.03/76.22 41529[49:Spt:41528.0,41520.0,41525.0] || m_main_v_state(s15,c_busy)* -> . % 76.03/76.22 41530[49:Spt:41528.0,41520.1] || -> m_main_v_state(s16,c_busy)*. % 76.03/76.22 41534[49:Res:41530.0,61.1] always3(s16) || -> . % 76.03/76.22 41535[49:SSi:41534.0,705.0] || -> . % 76.03/76.22 41536[47:Spt:41535.0,40157.2,40161.0] || xuntil6(s14)*+ -> . % 76.03/76.22 41537[47:Spt:41535.0,40157.0,40157.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.03/76.22 41538[47:Res:53.1,41537.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.03/76.22 41540[48:Spt:41538.0] || -> m_main_v_state(s14,c_busy)*. % 76.03/76.22 41542[48:Res:41540.0,61.1] always3(s14) || -> . % 76.03/76.22 41543[48:SSi:41542.0,703.0,40156.0] || -> . % 76.03/76.22 41544[48:Spt:41543.0,41538.0,41540.0] || m_main_v_state(s14,c_busy)* -> . % 76.03/76.22 41545[48:Spt:41543.0,41538.1] || -> m_main_v_state(s15,c_busy)*. % 76.03/76.22 41549[48:Res:41545.0,61.1] always3(s15) || -> . % 76.03/76.22 41550[48:SSi:41549.0,704.0] || -> . % 76.03/76.22 41551[46:Spt:41550.0,40154.2,40155.0] || xuntil6(s13)*+ -> . % 76.03/76.22 41552[46:Spt:41550.0,40154.0,40154.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.03/76.22 41553[46:Res:53.1,41552.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.03/76.22 41555[47:Spt:41553.0] || -> m_main_v_state(s13,c_busy)*. % 76.03/76.22 41557[47:Res:41555.0,61.1] always3(s13) || -> . % 76.03/76.22 41558[47:SSi:41557.0,702.0,40153.0] || -> . % 76.03/76.22 41559[47:Spt:41558.0,41553.0,41555.0] || m_main_v_state(s13,c_busy)* -> . % 76.03/76.22 41560[47:Spt:41558.0,41553.1] || -> m_main_v_state(s14,c_busy)*. % 76.03/76.22 41564[47:Res:41560.0,61.1] always3(s14) || -> . % 76.03/76.22 41565[47:SSi:41564.0,703.0] || -> . % 76.03/76.22 41566[45:Spt:41565.0,40148.2,40152.0] || xuntil6(s12)*+ -> . % 76.03/76.22 41567[45:Spt:41565.0,40148.0,40148.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.03/76.22 41568[45:Res:53.1,41567.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.03/76.22 41573[46:Spt:41568.0] || -> m_main_v_state(s12,c_busy)*. % 76.03/76.22 41575[46:Res:41573.0,61.1] always3(s12) || -> . % 76.03/76.22 41576[46:SSi:41575.0,701.0,40147.0] || -> . % 76.03/76.22 41577[46:Spt:41576.0,41568.0,41573.0] || m_main_v_state(s12,c_busy)* -> . % 76.03/76.22 41578[46:Spt:41576.0,41568.1] || -> m_main_v_state(s13,c_busy)*. % 76.03/76.22 41582[46:Res:41578.0,61.1] always3(s13) || -> . % 76.03/76.22 41583[46:SSi:41582.0,702.0] || -> . % 76.03/76.22 41584[44:Spt:41583.0,40145.2,40146.0] || xuntil6(s11)*+ -> . % 76.03/76.22 41585[44:Spt:41583.0,40145.0,40145.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.03/76.22 41586[44:Res:53.1,41585.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.03/76.22 41588[45:Spt:41586.0] || -> m_main_v_state(s11,c_busy)*. % 76.03/76.22 41590[45:Res:41588.0,61.1] always3(s11) || -> . % 76.03/76.22 41591[45:SSi:41590.0,700.0,40144.0] || -> . % 76.03/76.22 41592[45:Spt:41591.0,41586.0,41588.0] || m_main_v_state(s11,c_busy)* -> . % 76.03/76.22 41593[45:Spt:41591.0,41586.1] || -> m_main_v_state(s12,c_busy)*. % 76.03/76.22 41597[45:Res:41593.0,61.1] always3(s12) || -> . % 76.03/76.22 41598[45:SSi:41597.0,701.0] || -> . % 76.03/76.22 41599[43:Spt:41598.0,40139.2,40143.0] || xuntil6(s10)*+ -> . % 76.03/76.22 41600[43:Spt:41598.0,40139.0,40139.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.03/76.22 41601[43:Res:53.1,41600.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.03/76.22 41603[44:Spt:41601.0] || -> m_main_v_state(s10,c_busy)*. % 76.03/76.22 41605[44:Res:41603.0,61.1] always3(s10) || -> . % 76.03/76.22 41606[44:SSi:41605.0,699.0,40138.0] || -> . % 76.03/76.22 41607[44:Spt:41606.0,41601.0,41603.0] || m_main_v_state(s10,c_busy)* -> . % 76.03/76.22 41608[44:Spt:41606.0,41601.1] || -> m_main_v_state(s11,c_busy)*. % 76.03/76.22 41612[44:Res:41608.0,61.1] always3(s11) || -> . % 76.03/76.22 41613[44:SSi:41612.0,700.0] || -> . % 76.03/76.22 41614[42:Spt:41613.0,40136.2,40137.0] || xuntil6(s9)*+ -> . % 76.03/76.22 41615[42:Spt:41613.0,40136.0,40136.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.03/76.22 41616[42:Res:53.1,41615.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.03/76.22 41621[43:Spt:41616.0] || -> m_main_v_state(s9,c_busy)*. % 76.03/76.22 41623[43:Res:41621.0,61.1] always3(s9) || -> . % 76.03/76.22 41624[43:SSi:41623.0,698.0,40135.0] || -> . % 76.03/76.22 41625[43:Spt:41624.0,41616.0,41621.0] || m_main_v_state(s9,c_busy)* -> . % 76.03/76.22 41626[43:Spt:41624.0,41616.1] || -> m_main_v_state(s10,c_busy)*. % 76.03/76.22 41630[43:Res:41626.0,61.1] always3(s10) || -> . % 76.03/76.22 41631[43:SSi:41630.0,699.0] || -> . % 76.03/76.22 41632[41:Spt:41631.0,40130.2,40134.0] || xuntil6(s8)*+ -> . % 76.03/76.22 41633[41:Spt:41631.0,40130.0,40130.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.03/76.22 41634[41:Res:53.1,41633.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.03/76.22 41636[42:Spt:41634.0] || -> m_main_v_state(s8,c_busy)*. % 76.03/76.22 41638[42:Res:41636.0,61.1] always3(s8) || -> . % 76.03/76.22 41639[42:SSi:41638.0,697.0,40129.0] || -> . % 76.03/76.22 41640[42:Spt:41639.0,41634.0,41636.0] || m_main_v_state(s8,c_busy)* -> . % 76.03/76.22 41641[42:Spt:41639.0,41634.1] || -> m_main_v_state(s9,c_busy)*. % 76.03/76.22 41645[42:Res:41641.0,61.1] always3(s9) || -> . % 76.03/76.22 41646[42:SSi:41645.0,698.0] || -> . % 76.03/76.22 41647[40:Spt:41646.0,40127.2,40128.0] || xuntil6(s7)*+ -> . % 76.03/76.22 41648[40:Spt:41646.0,40127.0,40127.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.03/76.22 41649[40:Res:53.1,41648.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.03/76.22 41651[41:Spt:41649.0] || -> m_main_v_state(s7,c_busy)*. % 76.03/76.22 41653[41:Res:41651.0,61.1] always3(s7) || -> . % 76.03/76.22 41654[41:SSi:41653.0,696.0,40126.0] || -> . % 76.03/76.22 41655[41:Spt:41654.0,41649.0,41651.0] || m_main_v_state(s7,c_busy)* -> . % 76.03/76.22 41656[41:Spt:41654.0,41649.1] || -> m_main_v_state(s8,c_busy)*. % 76.03/76.22 41660[41:Res:41656.0,61.1] always3(s8) || -> . % 76.03/76.22 41661[41:SSi:41660.0,697.0] || -> . % 76.03/76.22 41662[39:Spt:41661.0,40121.2,40125.0] || xuntil6(s6)*+ -> . % 76.03/76.22 41663[39:Spt:41661.0,40121.0,40121.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.03/76.22 41664[39:Res:53.1,41663.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.03/76.22 41669[40:Spt:41664.0] || -> m_main_v_state(s6,c_busy)*. % 76.03/76.22 41671[40:Res:41669.0,61.1] always3(s6) || -> . % 76.03/76.22 41672[40:SSi:41671.0,695.0,40120.0] || -> . % 76.03/76.22 41673[40:Spt:41672.0,41664.0,41669.0] || m_main_v_state(s6,c_busy)* -> . % 76.03/76.22 41674[40:Spt:41672.0,41664.1] || -> m_main_v_state(s7,c_busy)*. % 76.03/76.22 41678[40:Res:41674.0,61.1] always3(s7) || -> . % 76.03/76.22 41679[40:SSi:41678.0,696.0] || -> . % 76.03/76.22 41680[38:Spt:41679.0,40118.2,40119.0] || xuntil6(s5)*+ -> . % 76.03/76.22 41681[38:Spt:41679.0,40118.0,40118.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.03/76.22 41682[38:Res:53.1,41681.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.03/76.22 41684[39:Spt:41682.0] || -> m_main_v_state(s5,c_busy)*. % 76.03/76.22 41686[39:Res:41684.0,61.1] always3(s5) || -> . % 76.03/76.22 41687[39:SSi:41686.0,694.0,40117.0] || -> . % 76.03/76.22 41688[39:Spt:41687.0,41682.0,41684.0] || m_main_v_state(s5,c_busy)* -> . % 76.03/76.22 41689[39:Spt:41687.0,41682.1] || -> m_main_v_state(s6,c_busy)*. % 76.03/76.22 41693[39:Res:41689.0,61.1] always3(s6) || -> . % 76.03/76.22 41694[39:SSi:41693.0,695.0] || -> . % 76.03/76.22 41695[37:Spt:41694.0,40112.2,40116.0] || xuntil6(s4)*+ -> . % 76.03/76.22 41696[37:Spt:41694.0,40112.0,40112.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.03/76.22 41697[37:Res:53.1,41696.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.03/76.22 41699[38:Spt:41697.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.22 41701[38:Res:41699.0,61.1] always3(s4) || -> . % 76.04/76.22 41702[38:SSi:41701.0,693.0,40111.0] || -> . % 76.04/76.22 41703[38:Spt:41702.0,41697.0,41699.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.22 41704[38:Spt:41702.0,41697.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.22 41708[38:Res:41704.0,61.1] always3(s5) || -> . % 76.04/76.22 41709[38:SSi:41708.0,694.0] || -> . % 76.04/76.22 41710[36:Spt:41709.0,40109.2,40110.0] || xuntil6(s3)*+ -> . % 76.04/76.22 41711[36:Spt:41709.0,40109.0,40109.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.22 41712[36:Res:53.1,41711.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.22 41717[37:Spt:41712.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.22 41719[37:Res:41717.0,61.1] always3(s3) || -> . % 76.04/76.22 41720[37:SSi:41719.0,692.0,40108.0] || -> . % 76.04/76.22 41721[37:Spt:41720.0,41712.0,41717.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.22 41722[37:Spt:41720.0,41712.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.22 41726[37:Res:41722.0,61.1] always3(s4) || -> . % 76.04/76.22 41727[37:SSi:41726.0,693.0] || -> . % 76.04/76.22 41728[35:Spt:41727.0,40103.2,40107.0] || xuntil6(s2)*+ -> . % 76.04/76.22 41729[35:Spt:41727.0,40103.0,40103.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.22 41730[35:Res:53.1,41729.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.22 41732[36:Spt:41730.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.22 41734[36:Res:41732.0,61.1] always3(s2) || -> . % 76.04/76.22 41735[36:SSi:41734.0,691.0,40102.0] || -> . % 76.04/76.22 41736[36:Spt:41735.0,41730.0,41732.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.22 41737[36:Spt:41735.0,41730.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.22 41741[36:Res:41737.0,61.1] always3(s3) || -> . % 76.04/76.22 41742[36:SSi:41741.0,692.0] || -> . % 76.04/76.22 41743[34:Spt:41742.0,40097.2,40101.0] || xuntil6(s1)*+ -> . % 76.04/76.22 41744[34:Spt:41742.0,40097.0,40097.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.22 41745[34:Res:53.1,41744.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.22 41747[35:Spt:41745.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.22 41749[35:Res:41747.0,61.1] always3(s1) || -> . % 76.04/76.22 41750[35:SSi:41749.0,690.0,40096.0] || -> . % 76.04/76.22 41751[35:Spt:41750.0,41745.0,41747.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.22 41752[35:Spt:41750.0,41745.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.22 41757[35:Res:41752.0,61.1] always3(s2) || -> . % 76.04/76.22 41758[35:SSi:41757.0,691.0] || -> . % 76.04/76.22 41759[33:Spt:41758.0,74.0,40095.0] || xuntil6(s0)*+ -> . % 76.04/76.22 41760[33:Spt:41758.0,74.1] || -> node4(s0)*. % 76.04/76.22 41761[33:MRR:758.1,41759.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.22 41763[33:Res:41761.0,61.1] always3(s1) || -> . % 76.04/76.22 41764[33:SSi:41763.0,690.0] || -> . % 76.04/76.22 41765[32:Spt:41764.0,40085.0,40089.0] || trans(s49,s19)*+ -> . % 76.04/76.22 41766[32:Spt:41764.0,40085.1,40085.2,40085.3,40085.4,40085.5,40085.6,40085.7,40085.8,40085.9,40085.10,40085.11,40085.12,40085.13,40085.14,40085.15,40085.16,40085.17,40085.18,40085.19] || -> trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.22 41767[32:MRR:40087.0,41765.0] || -> trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.22 41769[32:MRR:40088.1,41765.0] xuntil6(s49) || -> trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.22 41770[33:Spt:41766.0] || -> trans(s49,s18)*. % 76.04/76.22 41771[33:Res:41770.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s18)*. % 76.04/76.22 41773[33:Res:41770.0,60.0] || -> node2(s49,s18)*. % 76.04/76.22 41774[33:SSi:41771.1,50.0,738.0] xuntil6(s49) || -> until2p7(s18)*. % 76.04/76.22 41775[33:Res:41773.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)*. % 76.04/76.22 41776[34:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.22 41777[34:MRR:176.0,41776.0] || -> until5(s1)*. % 76.04/76.22 41778[34:MRR:40537.0,41777.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.22 41782[35:Spt:41778.2] || -> xuntil6(s1)*. % 76.04/76.22 41783[35:MRR:175.0,41782.0] || -> until5(s2)*. % 76.04/76.22 41784[35:MRR:40533.0,41783.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.22 41788[36:Spt:41784.2] || -> xuntil6(s2)*. % 76.04/76.22 41789[36:MRR:174.0,41788.0] || -> until5(s3)*. % 76.04/76.22 41790[36:MRR:40529.0,41789.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.22 41791[37:Spt:41790.2] || -> xuntil6(s3)*. % 76.04/76.22 41792[37:MRR:173.0,41791.0] || -> until5(s4)*. % 76.04/76.22 41793[37:MRR:40525.0,41792.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.22 41797[38:Spt:41793.2] || -> xuntil6(s4)*. % 76.04/76.22 41798[38:MRR:172.0,41797.0] || -> until5(s5)*. % 76.04/76.22 41799[38:MRR:40524.0,41798.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.22 41800[39:Spt:41799.2] || -> xuntil6(s5)*. % 76.04/76.22 41801[39:MRR:171.0,41800.0] || -> until5(s6)*. % 76.04/76.22 41802[39:MRR:40517.0,41801.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.22 41806[40:Spt:41802.2] || -> xuntil6(s6)*. % 76.04/76.22 41807[40:MRR:170.0,41806.0] || -> until5(s7)*. % 76.04/76.22 41808[40:MRR:40513.0,41807.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.22 41809[41:Spt:41808.2] || -> xuntil6(s7)*. % 76.04/76.22 41810[41:MRR:169.0,41809.0] || -> until5(s8)*. % 76.04/76.22 41811[41:MRR:40509.0,41810.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.22 41815[42:Spt:41811.2] || -> xuntil6(s8)*. % 76.04/76.22 41816[42:MRR:168.0,41815.0] || -> until5(s9)*. % 76.04/76.22 41817[42:MRR:40505.0,41816.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.22 41818[43:Spt:41817.2] || -> xuntil6(s9)*. % 76.04/76.22 41819[43:MRR:167.0,41818.0] || -> until5(s10)*. % 76.04/76.22 41820[43:MRR:40504.0,41819.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.22 41824[44:Spt:41820.2] || -> xuntil6(s10)*. % 76.04/76.22 41825[44:MRR:166.0,41824.0] || -> until5(s11)*. % 76.04/76.22 41826[44:MRR:40497.0,41825.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.22 41827[45:Spt:41826.2] || -> xuntil6(s11)*. % 76.04/76.22 41828[45:MRR:165.0,41827.0] || -> until5(s12)*. % 76.04/76.22 41829[45:MRR:40493.0,41828.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.22 41833[46:Spt:41829.2] || -> xuntil6(s12)*. % 76.04/76.22 41834[46:MRR:164.0,41833.0] || -> until5(s13)*. % 76.04/76.22 41835[46:MRR:40489.0,41834.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.22 41836[47:Spt:41835.2] || -> xuntil6(s13)*. % 76.04/76.22 41837[47:MRR:163.0,41836.0] || -> until5(s14)*. % 76.04/76.22 41838[47:MRR:40485.0,41837.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.22 41842[48:Spt:41838.2] || -> xuntil6(s14)*. % 76.04/76.22 41843[48:MRR:162.0,41842.0] || -> until5(s15)*. % 76.04/76.22 41844[48:MRR:40484.0,41843.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.22 41845[49:Spt:41844.2] || -> xuntil6(s15)*. % 76.04/76.22 41846[49:MRR:161.0,41845.0] || -> until5(s16)*. % 76.04/76.22 41847[49:MRR:40477.0,41846.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.22 41851[50:Spt:41847.2] || -> xuntil6(s16)*. % 76.04/76.22 41852[50:MRR:160.0,41851.0] || -> until5(s17)*. % 76.04/76.22 41853[50:MRR:40473.0,41852.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.22 41854[51:Spt:41853.2] || -> xuntil6(s17)*. % 76.04/76.22 41855[51:MRR:159.0,41854.0] || -> until5(s18)*. % 76.04/76.22 41856[51:MRR:40469.0,41855.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.22 41860[52:Spt:41856.2] || -> xuntil6(s18)*. % 76.04/76.22 41861[52:MRR:158.0,41860.0] || -> until5(s19)*. % 76.04/76.22 41862[52:MRR:40465.0,41861.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.22 41863[53:Spt:41862.2] || -> xuntil6(s19)*. % 76.04/76.22 41864[53:MRR:157.0,41863.0] || -> until5(s20)*. % 76.04/76.22 41865[53:MRR:40464.0,41864.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.22 41869[54:Spt:41865.2] || -> xuntil6(s20)*. % 76.04/76.22 41870[54:MRR:156.0,41869.0] || -> until5(s21)*. % 76.04/76.22 41871[54:MRR:40454.0,41870.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.22 41872[55:Spt:41871.2] || -> xuntil6(s21)*. % 76.04/76.22 41873[55:MRR:155.0,41872.0] || -> until5(s22)*. % 76.04/76.22 41874[55:MRR:40453.0,41873.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.22 41878[56:Spt:41874.2] || -> xuntil6(s22)*. % 76.04/76.22 41879[56:MRR:154.0,41878.0] || -> until5(s23)*. % 76.04/76.22 41880[56:MRR:40446.0,41879.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.22 41881[57:Spt:41880.2] || -> xuntil6(s23)*. % 76.04/76.22 41882[57:MRR:153.0,41881.0] || -> until5(s24)*. % 76.04/76.22 41883[57:MRR:40442.0,41882.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.22 41887[58:Spt:41883.2] || -> xuntil6(s24)*. % 76.04/76.22 41888[58:MRR:152.0,41887.0] || -> until5(s25)*. % 76.04/76.22 41889[58:MRR:40438.0,41888.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.22 41890[59:Spt:41889.2] || -> xuntil6(s25)*. % 76.04/76.22 41891[59:MRR:151.0,41890.0] || -> until5(s26)*. % 76.04/76.22 41892[59:MRR:40437.0,41891.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.22 41896[60:Spt:41892.2] || -> xuntil6(s26)*. % 76.04/76.22 41897[60:MRR:150.0,41896.0] || -> until5(s27)*. % 76.04/76.22 41898[60:MRR:40436.0,41897.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.22 41899[61:Spt:41898.2] || -> xuntil6(s27)*. % 76.04/76.22 41900[61:MRR:149.0,41899.0] || -> until5(s28)*. % 76.04/76.22 41901[61:MRR:40435.0,41900.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.22 41905[62:Spt:41901.2] || -> xuntil6(s28)*. % 76.04/76.22 41906[62:MRR:148.0,41905.0] || -> until5(s29)*. % 76.04/76.22 41907[62:MRR:35647.0,41906.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.22 41908[63:Spt:41907.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.22 41910[63:Res:41908.0,61.1] always3(s30) || -> . % 76.04/76.22 41911[63:SSi:41910.0,719.0] || -> . % 76.04/76.22 41912[63:Spt:41911.0,41907.1,41908.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.04/76.22 41913[63:Spt:41911.0,41907.0,41907.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 76.04/76.22 41915[63:MRR:831.2,41912.0] node4(s29) || m_main_v_state(s29,c_ready)* -> . % 76.04/76.22 41916[63:Res:53.1,41913.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 76.04/76.22 41921[64:Spt:41916.1] || -> xuntil6(s29)*. % 76.04/76.22 41922[64:MRR:147.0,41921.0] || -> until5(s30)*. % 76.04/76.22 41923[64:MRR:40544.0,41922.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.22 41925[65:Spt:41923.2] || -> xuntil6(s30)*. % 76.04/76.22 41926[65:MRR:146.0,41925.0] || -> until5(s31)*. % 76.04/76.22 41927[65:MRR:35651.0,41926.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.22 41928[66:Spt:41927.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.22 41930[66:Res:41928.0,61.1] always3(s32) || -> . % 76.04/76.22 41931[66:SSi:41930.0,721.0] || -> . % 76.04/76.22 41932[66:Spt:41931.0,41927.1,41928.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.04/76.22 41933[66:Spt:41931.0,41927.0,41927.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.04/76.22 41935[66:MRR:825.2,41932.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.04/76.22 41936[66:Res:53.1,41933.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.04/76.22 41938[67:Spt:41936.1] || -> xuntil6(s31)*. % 76.04/76.22 41939[67:MRR:145.0,41938.0] || -> until5(s32)*. % 76.04/76.22 41940[67:MRR:40548.0,41939.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.22 41945[68:Spt:41940.2] || -> xuntil6(s32)*. % 76.04/76.22 41946[68:MRR:144.0,41945.0] || -> until5(s33)*. % 76.04/76.22 41947[68:MRR:35655.0,41946.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.22 41948[69:Spt:41947.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.22 41950[69:Res:41948.0,61.1] always3(s34) || -> . % 76.04/76.22 41951[69:SSi:41950.0,723.0] || -> . % 76.04/76.22 41952[69:Spt:41951.0,41947.1,41948.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.22 41953[69:Spt:41951.0,41947.0,41947.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.22 41955[69:MRR:819.2,41952.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.22 41956[69:Res:53.1,41953.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.22 41958[70:Spt:41956.1] || -> xuntil6(s33)*. % 76.04/76.22 41959[70:MRR:143.0,41958.0] || -> until5(s34)*. % 76.04/76.22 41960[70:MRR:40555.0,41959.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.22 41968[71:Spt:41960.2] || -> xuntil6(s34)*. % 76.04/76.22 41969[71:MRR:142.0,41968.0] || -> until5(s35)*. % 76.04/76.22 41970[71:MRR:35659.0,41969.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.22 41971[72:Spt:41970.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.22 41973[72:Res:41971.0,61.1] always3(s36) || -> . % 76.04/76.22 41974[72:SSi:41973.0,725.0] || -> . % 76.04/76.22 41975[72:Spt:41974.0,41970.1,41971.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.22 41976[72:Spt:41974.0,41970.0,41970.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.22 41978[72:MRR:813.2,41975.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.22 41979[72:Res:53.1,41976.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.22 41984[73:Spt:41979.1] || -> xuntil6(s35)*. % 76.04/76.22 41985[73:MRR:141.0,41984.0] || -> until5(s36)*. % 76.04/76.22 41986[73:MRR:40556.0,41985.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.22 41988[74:Spt:41986.2] || -> xuntil6(s36)*. % 76.04/76.22 41989[74:MRR:140.0,41988.0] || -> until5(s37)*. % 76.04/76.22 41990[74:MRR:35666.0,41989.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.22 41991[75:Spt:41990.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.22 41993[75:Res:41991.0,61.1] always3(s38) || -> . % 76.04/76.22 41994[75:SSi:41993.0,727.0] || -> . % 76.04/76.22 41995[75:Spt:41994.0,41990.1,41991.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.22 41996[75:Spt:41994.0,41990.0,41990.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.22 41998[75:MRR:807.2,41995.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.22 41999[75:Res:53.1,41996.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.22 42001[76:Spt:41999.1] || -> xuntil6(s37)*. % 76.04/76.22 42002[76:MRR:139.0,42001.0] || -> until5(s38)*. % 76.04/76.22 42003[76:MRR:40560.0,42002.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.22 42008[77:Spt:42003.2] || -> xuntil6(s38)*. % 76.04/76.22 42009[77:MRR:138.0,42008.0] || -> until5(s39)*. % 76.04/76.22 42010[77:MRR:35667.0,42009.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.22 42011[78:Spt:42010.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.22 42013[78:Res:42011.0,61.1] always3(s40) || -> . % 76.04/76.22 42014[78:SSi:42013.0,729.0] || -> . % 76.04/76.22 42015[78:Spt:42014.0,42010.1,42011.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.22 42016[78:Spt:42014.0,42010.0,42010.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.22 42018[78:MRR:801.2,42015.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.22 42019[78:Res:53.1,42016.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.22 42021[79:Spt:42019.1] || -> xuntil6(s39)*. % 76.04/76.22 42022[79:MRR:137.0,42021.0] || -> until5(s40)*. % 76.04/76.22 42023[79:MRR:40564.0,42022.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.22 42031[80:Spt:42023.2] || -> xuntil6(s40)*. % 76.04/76.22 42032[80:MRR:136.0,42031.0] || -> until5(s41)*. % 76.04/76.22 42033[80:MRR:35671.0,42032.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.22 42034[81:Spt:42033.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.22 42036[81:Res:42034.0,61.1] always3(s42) || -> . % 76.04/76.22 42037[81:SSi:42036.0,731.0] || -> . % 76.04/76.22 42038[81:Spt:42037.0,42033.1,42034.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.22 42039[81:Spt:42037.0,42033.0,42033.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.22 42041[81:MRR:795.2,42038.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.22 42042[81:Res:53.1,42039.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.22 42047[82:Spt:42042.1] || -> xuntil6(s41)*. % 76.04/76.22 42048[82:MRR:135.0,42047.0] || -> until5(s42)*. % 76.04/76.22 42049[82:MRR:40568.0,42048.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.22 42051[83:Spt:42049.2] || -> xuntil6(s42)*. % 76.04/76.22 42052[83:MRR:134.0,42051.0] || -> until5(s43)*. % 76.04/76.22 42053[83:MRR:35675.0,42052.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.22 42054[84:Spt:42053.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.22 42056[84:Res:42054.0,61.1] always3(s44) || -> . % 76.04/76.22 42057[84:SSi:42056.0,733.0] || -> . % 76.04/76.22 42058[84:Spt:42057.0,42053.1,42054.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.22 42059[84:Spt:42057.0,42053.0,42053.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.22 42061[84:MRR:789.2,42058.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.22 42062[84:Res:53.1,42059.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.22 42064[85:Spt:42062.1] || -> xuntil6(s43)*. % 76.04/76.22 42065[85:MRR:133.0,42064.0] || -> until5(s44)*. % 76.04/76.22 42066[85:MRR:40575.0,42065.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.22 42071[86:Spt:42066.2] || -> xuntil6(s44)*. % 76.04/76.22 42072[86:MRR:132.0,42071.0] || -> until5(s45)*. % 76.04/76.22 42073[86:MRR:35679.0,42072.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.22 42074[87:Spt:42073.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.22 42076[87:Res:42074.0,61.1] always3(s46) || -> . % 76.04/76.22 42077[87:SSi:42076.0,735.0] || -> . % 76.04/76.22 42078[87:Spt:42077.0,42073.1,42074.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.22 42079[87:Spt:42077.0,42073.0,42073.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.22 42081[87:MRR:783.2,42078.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.22 42082[87:Res:53.1,42079.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.22 42084[88:Spt:42082.1] || -> xuntil6(s45)*. % 76.04/76.22 42085[88:MRR:131.0,42084.0] || -> until5(s46)*. % 76.04/76.22 42086[88:MRR:40576.0,42085.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.22 42094[89:Spt:42086.2] || -> xuntil6(s46)*. % 76.04/76.22 42095[89:MRR:130.0,42094.0] || -> until5(s47)*. % 76.04/76.22 42096[89:MRR:35683.0,42095.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.22 42097[90:Spt:42096.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.22 42099[90:Res:42097.0,61.1] always3(s48) || -> . % 76.04/76.22 42100[90:SSi:42099.0,737.0] || -> . % 76.04/76.22 42101[90:Spt:42100.0,42096.1,42097.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.22 42102[90:Spt:42100.0,42096.0,42096.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.22 42104[90:MRR:777.2,42101.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.22 42105[90:Res:53.1,42102.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.22 42110[91:Spt:42105.1] || -> xuntil6(s47)*. % 76.04/76.22 42111[91:MRR:129.0,42110.0] || -> until5(s48)*. % 76.04/76.22 42112[91:MRR:40580.0,42111.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.22 42114[92:Spt:42112.2] || -> xuntil6(s48)*. % 76.04/76.22 42115[92:MRR:128.0,42114.0] || -> until5(s49)*. % 76.04/76.22 42116[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.22 42117[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.22 42118[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.22 42119[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.22 42123[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.22 42127[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.22 42134[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.22 42135[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.22 42139[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.22 42143[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.22 42150[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.22 42154[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.22 42158[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.22 42165[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.22 42166[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.22 42170[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.22 42174[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.22 42178[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.22 42185[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.22 42186[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.22 42190[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.22 42194[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.22 42198[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.22 42205[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.22 42206[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.22 42210[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.22 42214[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.22 42218[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.22 42220[33:SoR:41775.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)*. % 76.04/76.22 42225[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.22 42229[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.22 42236[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.22 42237[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.22 42241[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.22 42245[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.22 42249[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.22 42256[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.22 42257[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.22 42261[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.22 42262[33:SoR:42220.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)* xuntil6(s49). % 76.04/76.22 42263[92:SSi:42262.0,50.0,738.0,42115.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s18,c_busy)* xuntil6(s49). % 76.04/76.22 42264[93:Spt:42263.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.22 42266[93:Res:42264.0,61.1] always3(s18) || -> . % 76.04/76.22 42267[93:SSi:42266.0,707.0,41855.0,41860.0] || -> . % 76.04/76.22 42268[93:Spt:42267.0,42263.1,42264.0] || m_main_v_state(s18,c_busy)*+ -> . % 76.04/76.22 42269[93:Spt:42267.0,42263.0,42263.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.22 42273[93:MRR:42220.2,42268.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.22 42274[93:Res:53.1,42269.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.22 42276[94:Spt:42274.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.22 42278[94:Res:42276.0,61.1] always3(s49) || -> . % 76.04/76.22 42279[94:SSi:42278.0,50.0,738.0,42115.0] || -> . % 76.04/76.22 42280[94:Spt:42279.0,42274.0,42276.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.22 42281[94:Spt:42279.0,42274.1] || -> xuntil6(s49)*. % 76.04/76.22 42282[94:MRR:41774.0,42281.0] || -> until2p7(s18)*. % 76.04/76.22 42283[94:MRR:214.0,42282.0] || -> until2p7(s19)* node4(s18). % 76.04/76.22 42285[94:MRR:774.2,42280.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.22 42286[95:Spt:42283.0] || -> until2p7(s19)*. % 76.04/76.22 42287[95:MRR:215.0,42286.0] || -> until2p7(s20)* node4(s19). % 76.04/76.22 42288[96:Spt:42287.0] || -> until2p7(s20)*. % 76.04/76.22 42289[96:MRR:216.0,42288.0] || -> until2p7(s21)* node4(s20). % 76.04/76.22 42290[97:Spt:42289.0] || -> until2p7(s21)*. % 76.04/76.22 42291[97:MRR:217.0,42290.0] || -> until2p7(s22)* node4(s21). % 76.04/76.22 42292[98:Spt:42291.0] || -> until2p7(s22)*. % 76.04/76.22 42293[98:MRR:218.0,42292.0] || -> until2p7(s23)* node4(s22). % 76.04/76.22 42294[99:Spt:42293.0] || -> until2p7(s23)*. % 76.04/76.22 42295[99:MRR:219.0,42294.0] || -> until2p7(s24)* node4(s23). % 76.04/76.22 42296[100:Spt:42295.0] || -> until2p7(s24)*. % 76.04/76.22 42297[100:MRR:220.0,42296.0] || -> until2p7(s25)* node4(s24). % 76.04/76.22 42298[101:Spt:42297.0] || -> until2p7(s25)*. % 76.04/76.22 42299[101:MRR:221.0,42298.0] || -> until2p7(s26)* node4(s25). % 76.04/76.22 42300[102:Spt:42299.0] || -> until2p7(s26)*. % 76.04/76.22 42301[102:MRR:222.0,42300.0] || -> until2p7(s27)* node4(s26). % 76.04/76.22 42302[103:Spt:42301.0] || -> until2p7(s27)*. % 76.04/76.22 42303[103:MRR:223.0,42302.0] || -> until2p7(s28)* node4(s27). % 76.04/76.22 42304[104:Spt:42303.0] || -> until2p7(s28)*. % 76.04/76.22 42305[104:MRR:224.0,42304.0] || -> until2p7(s29)* node4(s28). % 76.04/76.22 42306[105:Spt:42305.0] || -> until2p7(s29)*. % 76.04/76.22 42307[105:MRR:225.0,42306.0] || -> until2p7(s30)* node4(s29). % 76.04/76.22 42308[106:Spt:42307.0] || -> until2p7(s30)*. % 76.04/76.22 42309[106:MRR:226.0,42308.0] || -> until2p7(s31)* node4(s30). % 76.04/76.22 42310[107:Spt:42309.0] || -> until2p7(s31)*. % 76.04/76.22 42311[107:MRR:227.0,42310.0] || -> until2p7(s32)* node4(s31). % 76.04/76.22 42312[108:Spt:42311.0] || -> until2p7(s32)*. % 76.04/76.22 42313[108:MRR:228.0,42312.0] || -> until2p7(s33)* node4(s32). % 76.04/76.22 42314[109:Spt:42313.0] || -> until2p7(s33)*. % 76.04/76.22 42315[109:MRR:229.0,42314.0] || -> until2p7(s34)* node4(s33). % 76.04/76.22 42316[110:Spt:42315.0] || -> until2p7(s34)*. % 76.04/76.22 42317[110:MRR:230.0,42316.0] || -> until2p7(s35)* node4(s34). % 76.04/76.22 42318[111:Spt:42317.0] || -> until2p7(s35)*. % 76.04/76.22 42319[111:MRR:231.0,42318.0] || -> until2p7(s36)* node4(s35). % 76.04/76.22 42320[112:Spt:42319.0] || -> until2p7(s36)*. % 76.04/76.22 42321[112:MRR:232.0,42320.0] || -> until2p7(s37)* node4(s36). % 76.04/76.22 42322[113:Spt:42321.0] || -> until2p7(s37)*. % 76.04/76.22 42323[113:MRR:235.0,42322.0] || -> until2p7(s38)* node4(s37). % 76.04/76.22 42324[114:Spt:42323.0] || -> until2p7(s38)*. % 76.04/76.22 42325[114:MRR:236.0,42324.0] || -> until2p7(s39)* node4(s38). % 76.04/76.22 42326[115:Spt:42325.0] || -> until2p7(s39)*. % 76.04/76.22 42327[115:MRR:237.0,42326.0] || -> until2p7(s40)* node4(s39). % 76.04/76.22 42328[116:Spt:42327.0] || -> until2p7(s40)*. % 76.04/76.22 42329[116:MRR:238.0,42328.0] || -> until2p7(s41)* node4(s40). % 76.04/76.22 42330[117:Spt:42329.0] || -> until2p7(s41)*. % 76.04/76.22 42331[117:MRR:239.0,42330.0] || -> until2p7(s42)* node4(s41). % 76.04/76.22 42332[118:Spt:42331.0] || -> until2p7(s42)*. % 76.04/76.22 42333[118:MRR:240.0,42332.0] || -> until2p7(s43)* node4(s42). % 76.04/76.22 42334[119:Spt:42333.0] || -> until2p7(s43)*. % 76.04/76.22 42335[119:MRR:241.0,42334.0] || -> until2p7(s44)* node4(s43). % 76.04/76.22 42336[120:Spt:42335.0] || -> until2p7(s44)*. % 76.04/76.22 42337[120:MRR:539.0,42336.0] || -> until2p7(s45)* node4(s44). % 76.04/76.22 42338[121:Spt:42337.0] || -> until2p7(s45)*. % 76.04/76.22 42339[121:MRR:544.0,42338.0] || -> until2p7(s46)* node4(s45). % 76.04/76.22 42340[122:Spt:42339.0] || -> until2p7(s46)*. % 76.04/76.22 42341[122:MRR:549.0,42340.0] || -> until2p7(s47)* node4(s46). % 76.04/76.22 42342[123:Spt:42341.0] || -> until2p7(s47)*. % 76.04/76.22 42343[123:MRR:554.0,42342.0] || -> until2p7(s48)* node4(s47). % 76.04/76.22 42344[124:Spt:42343.0] || -> until2p7(s48)*. % 76.04/76.22 42345[124:MRR:559.0,42344.0] || -> until2p7(s49)* node4(s48). % 76.04/76.22 42346[125:Spt:42345.0] || -> until2p7(s49)*. % 76.04/76.22 42347[125:MRR:194.0,42346.0] || -> node4(s49)*. % 76.04/76.22 42348[125:MRR:42273.0,42347.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.22 42349[125:Res:53.1,42348.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.22 42351[125:MRR:42349.0,42280.0] || -> . % 76.04/76.22 42352[125:Spt:42351.0,42345.0,42346.0] || until2p7(s49)*+ -> . % 76.04/76.22 42353[125:Spt:42351.0,42345.1] || -> node4(s48)*. % 76.04/76.22 42354[125:MRR:42285.0,42353.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.22 42357[125:Res:53.1,42354.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.22 42359[125:MRR:42357.0,42101.0] || -> . % 76.04/76.22 42360[124:Spt:42359.0,42343.0,42344.0] || until2p7(s48)*+ -> . % 76.04/76.22 42361[124:Spt:42359.0,42343.1] || -> node4(s47)*. % 76.04/76.22 42362[124:MRR:42104.0,42361.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.22 42365[124:Res:53.1,42362.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.22 42368[124:Res:42365.0,61.1] always3(s47) || -> . % 76.04/76.22 42369[124:SSi:42368.0,736.0,42095.0,42110.0,42342.0,42361.0] || -> . % 76.04/76.22 42370[123:Spt:42369.0,42341.0,42342.0] || until2p7(s47)*+ -> . % 76.04/76.22 42371[123:Spt:42369.0,42341.1] || -> node4(s46)*. % 76.04/76.22 42373[123:MRR:780.0,42371.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.22 42393[123:Res:53.1,42373.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.22 42395[123:MRR:42393.0,42078.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.22 42397[123:Res:42395.0,61.1] always3(s47) || -> . % 76.04/76.22 42398[123:SSi:42397.0,736.0,42095.0,42110.0] || -> . % 76.04/76.22 42399[122:Spt:42398.0,42339.0,42340.0] || until2p7(s46)*+ -> . % 76.04/76.22 42400[122:Spt:42398.0,42339.1] || -> node4(s45)*. % 76.04/76.22 42401[122:MRR:42081.0,42400.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.22 42405[122:Res:53.1,42401.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.22 42408[122:Res:42405.0,61.1] always3(s45) || -> . % 76.04/76.22 42409[122:SSi:42408.0,734.0,42072.0,42084.0,42338.0,42400.0] || -> . % 76.04/76.22 42410[121:Spt:42409.0,42337.0,42338.0] || until2p7(s45)*+ -> . % 76.04/76.22 42411[121:Spt:42409.0,42337.1] || -> node4(s44)*. % 76.04/76.22 42413[121:MRR:786.0,42411.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.22 42424[121:Res:53.1,42413.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.22 42426[121:MRR:42424.0,42058.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.22 42428[121:Res:42426.0,61.1] always3(s45) || -> . % 76.04/76.22 42429[121:SSi:42428.0,734.0,42072.0,42084.0] || -> . % 76.04/76.22 42430[120:Spt:42429.0,42335.0,42336.0] || until2p7(s44)*+ -> . % 76.04/76.22 42431[120:Spt:42429.0,42335.1] || -> node4(s43)*. % 76.04/76.22 42432[120:MRR:42061.0,42431.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.22 42435[120:Res:53.1,42432.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.22 42438[120:Res:42435.0,61.1] always3(s43) || -> . % 76.04/76.22 42439[120:SSi:42438.0,732.0,42052.0,42064.0,42334.0,42431.0] || -> . % 76.04/76.22 42440[119:Spt:42439.0,42333.0,42334.0] || until2p7(s43)*+ -> . % 76.04/76.22 42441[119:Spt:42439.0,42333.1] || -> node4(s42)*. % 76.04/76.22 42443[119:MRR:792.0,42441.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.22 42455[119:Res:53.1,42443.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.22 42457[119:MRR:42455.0,42038.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.22 42459[119:Res:42457.0,61.1] always3(s43) || -> . % 76.04/76.22 42460[119:SSi:42459.0,732.0,42052.0,42064.0] || -> . % 76.04/76.22 42461[118:Spt:42460.0,42331.0,42332.0] || until2p7(s42)*+ -> . % 76.04/76.22 42462[118:Spt:42460.0,42331.1] || -> node4(s41)*. % 76.04/76.22 42463[118:MRR:42041.0,42462.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.22 42466[118:Res:53.1,42463.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.22 42469[118:Res:42466.0,61.1] always3(s41) || -> . % 76.04/76.22 42470[118:SSi:42469.0,730.0,42032.0,42047.0,42330.0,42462.0] || -> . % 76.04/76.22 42471[117:Spt:42470.0,42329.0,42330.0] || until2p7(s41)*+ -> . % 76.04/76.22 42472[117:Spt:42470.0,42329.1] || -> node4(s40)*. % 76.04/76.22 42474[117:MRR:798.0,42472.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.22 42486[117:Res:53.1,42474.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.22 42488[117:MRR:42486.0,42015.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.22 42493[117:Res:42488.0,61.1] always3(s41) || -> . % 76.04/76.22 42494[117:SSi:42493.0,730.0,42032.0,42047.0] || -> . % 76.04/76.22 42495[116:Spt:42494.0,42327.0,42328.0] || until2p7(s40)*+ -> . % 76.04/76.22 42496[116:Spt:42494.0,42327.1] || -> node4(s39)*. % 76.04/76.22 42497[116:MRR:42018.0,42496.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.22 42500[116:Res:53.1,42497.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.22 42504[116:Res:42500.0,61.1] always3(s39) || -> . % 76.04/76.22 42505[116:SSi:42504.0,728.0,42009.0,42021.0,42326.0,42496.0] || -> . % 76.04/76.22 42506[115:Spt:42505.0,42325.0,42326.0] || until2p7(s39)*+ -> . % 76.04/76.22 42507[115:Spt:42505.0,42325.1] || -> node4(s38)*. % 76.04/76.22 42509[115:MRR:804.0,42507.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.22 42520[115:Res:53.1,42509.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.22 42522[115:MRR:42520.0,41995.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.22 42524[115:Res:42522.0,61.1] always3(s39) || -> . % 76.04/76.22 42525[115:SSi:42524.0,728.0,42009.0,42021.0] || -> . % 76.04/76.22 42526[114:Spt:42525.0,42323.0,42324.0] || until2p7(s38)*+ -> . % 76.04/76.22 42527[114:Spt:42525.0,42323.1] || -> node4(s37)*. % 76.04/76.22 42528[114:MRR:41998.0,42527.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.22 42532[114:Res:53.1,42528.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.22 42535[114:Res:42532.0,61.1] always3(s37) || -> . % 76.04/76.22 42536[114:SSi:42535.0,726.0,41989.0,42001.0,42322.0,42527.0] || -> . % 76.04/76.22 42537[113:Spt:42536.0,42321.0,42322.0] || until2p7(s37)*+ -> . % 76.04/76.22 42538[113:Spt:42536.0,42321.1] || -> node4(s36)*. % 76.04/76.22 42540[113:MRR:810.0,42538.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.22 42551[113:Res:53.1,42540.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.22 42553[113:MRR:42551.0,41975.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.22 42555[113:Res:42553.0,61.1] always3(s37) || -> . % 76.04/76.22 42556[113:SSi:42555.0,726.0,41989.0,42001.0] || -> . % 76.04/76.22 42557[112:Spt:42556.0,42319.0,42320.0] || until2p7(s36)*+ -> . % 76.04/76.22 42558[112:Spt:42556.0,42319.1] || -> node4(s35)*. % 76.04/76.22 42559[112:MRR:41978.0,42558.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.22 42562[112:Res:53.1,42559.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.22 42565[112:Res:42562.0,61.1] always3(s35) || -> . % 76.04/76.22 42566[112:SSi:42565.0,724.0,41969.0,41984.0,42318.0,42558.0] || -> . % 76.04/76.22 42567[111:Spt:42566.0,42317.0,42318.0] || until2p7(s35)*+ -> . % 76.04/76.22 42568[111:Spt:42566.0,42317.1] || -> node4(s34)*. % 76.04/76.22 42570[111:MRR:816.0,42568.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.22 42582[111:Res:53.1,42570.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.22 42584[111:MRR:42582.0,41952.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.22 42586[111:Res:42584.0,61.1] always3(s35) || -> . % 76.04/76.22 42587[111:SSi:42586.0,724.0,41969.0,41984.0] || -> . % 76.04/76.22 42588[110:Spt:42587.0,42315.0,42316.0] || until2p7(s34)*+ -> . % 76.04/76.22 42589[110:Spt:42587.0,42315.1] || -> node4(s33)*. % 76.04/76.22 42590[110:MRR:41955.0,42589.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.22 42593[110:Res:53.1,42590.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.22 42596[110:Res:42593.0,61.1] always3(s33) || -> . % 76.04/76.22 42597[110:SSi:42596.0,722.0,41946.0,41958.0,42314.0,42589.0] || -> . % 76.04/76.22 42598[109:Spt:42597.0,42313.0,42314.0] || until2p7(s33)*+ -> . % 76.04/76.22 42599[109:Spt:42597.0,42313.1] || -> node4(s32)*. % 76.04/76.22 42601[109:MRR:822.0,42599.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.22 42613[109:Res:53.1,42601.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.22 42615[109:MRR:42613.0,41932.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.22 42620[109:Res:42615.0,61.1] always3(s33) || -> . % 76.04/76.22 42621[109:SSi:42620.0,722.0,41946.0,41958.0] || -> . % 76.04/76.22 42622[108:Spt:42621.0,42311.0,42312.0] || until2p7(s32)*+ -> . % 76.04/76.22 42623[108:Spt:42621.0,42311.1] || -> node4(s31)*. % 76.04/76.22 42624[108:MRR:41935.0,42623.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.04/76.22 42627[108:Res:53.1,42624.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.22 42631[108:Res:42627.0,61.1] always3(s31) || -> . % 76.04/76.22 42632[108:SSi:42631.0,720.0,41926.0,41938.0,42310.0,42623.0] || -> . % 76.04/76.22 42633[107:Spt:42632.0,42309.0,42310.0] || until2p7(s31)*+ -> . % 76.04/76.22 42634[107:Spt:42632.0,42309.1] || -> node4(s30)*. % 76.04/76.22 42636[107:MRR:828.0,42634.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.22 42647[107:Res:53.1,42636.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.22 42649[107:MRR:42647.0,41912.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.22 42651[107:Res:42649.0,61.1] always3(s31) || -> . % 76.04/76.22 42652[107:SSi:42651.0,720.0,41926.0,41938.0] || -> . % 76.04/76.22 42653[106:Spt:42652.0,42307.0,42308.0] || until2p7(s30)*+ -> . % 76.04/76.22 42654[106:Spt:42652.0,42307.1] || -> node4(s29)*. % 76.04/76.22 42655[106:MRR:41915.0,42654.0] || m_main_v_state(s29,c_ready)*+ -> . % 76.04/76.22 42659[106:Res:53.1,42655.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.22 42662[106:Res:42659.0,61.1] always3(s29) || -> . % 76.04/76.22 42663[106:SSi:42662.0,718.0,41906.0,41921.0,42306.0,42654.0] || -> . % 76.04/76.22 42664[105:Spt:42663.0,42305.0,42306.0] || until2p7(s29)*+ -> . % 76.04/76.22 42665[105:Spt:42663.0,42305.1] || -> node4(s28)*. % 76.04/76.22 42667[105:MRR:834.0,42665.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.22 42678[105:Res:53.1,42667.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.22 42680[106:Spt:42678.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.22 42682[106:Res:42680.0,61.1] always3(s28) || -> . % 76.04/76.22 42683[106:SSi:42682.0,717.0,41900.0,41905.0,42304.0,42665.0] || -> . % 76.04/76.22 42684[106:Spt:42683.0,42678.0,42680.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.22 42685[106:Spt:42683.0,42678.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.22 42689[106:Res:42685.0,61.1] always3(s29) || -> . % 76.04/76.22 42690[106:SSi:42689.0,718.0,41906.0,41921.0] || -> . % 76.04/76.22 42691[104:Spt:42690.0,42303.0,42304.0] || until2p7(s28)*+ -> . % 76.04/76.22 42692[104:Spt:42690.0,42303.1] || -> node4(s27)*. % 76.04/76.22 42694[104:MRR:837.0,42692.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.22 42704[104:Res:53.1,42694.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.22 42706[105:Spt:42704.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.22 42708[105:Res:42706.0,61.1] always3(s27) || -> . % 76.04/76.22 42709[105:SSi:42708.0,716.0,41897.0,41899.0,42302.0,42692.0] || -> . % 76.04/76.22 42710[105:Spt:42709.0,42704.0,42706.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.22 42711[105:Spt:42709.0,42704.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.22 42715[105:Res:42711.0,61.1] always3(s28) || -> . % 76.04/76.22 42716[105:SSi:42715.0,717.0,41900.0,41905.0] || -> . % 76.04/76.22 42717[103:Spt:42716.0,42301.0,42302.0] || until2p7(s27)*+ -> . % 76.04/76.22 42718[103:Spt:42716.0,42301.1] || -> node4(s26)*. % 76.04/76.22 42720[103:MRR:840.0,42718.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.22 42723[103:Res:53.1,42720.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.22 42725[104:Spt:42723.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.22 42727[104:Res:42725.0,61.1] always3(s26) || -> . % 76.04/76.22 42728[104:SSi:42727.0,715.0,41891.0,41896.0,42300.0,42718.0] || -> . % 76.04/76.22 42729[104:Spt:42728.0,42723.0,42725.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.22 42730[104:Spt:42728.0,42723.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.22 42734[104:Res:42730.0,61.1] always3(s27) || -> . % 76.04/76.22 42735[104:SSi:42734.0,716.0,41897.0,41899.0] || -> . % 76.04/76.22 42736[102:Spt:42735.0,42299.0,42300.0] || until2p7(s26)*+ -> . % 76.04/76.22 42737[102:Spt:42735.0,42299.1] || -> node4(s25)*. % 76.04/76.22 42739[102:MRR:843.0,42737.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.22 42742[102:Res:53.1,42739.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.22 42744[103:Spt:42742.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.22 42746[103:Res:42744.0,61.1] always3(s25) || -> . % 76.04/76.22 42747[103:SSi:42746.0,714.0,41888.0,41890.0,42298.0,42737.0] || -> . % 76.04/76.22 42748[103:Spt:42747.0,42742.0,42744.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.22 42749[103:Spt:42747.0,42742.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.22 42753[103:Res:42749.0,61.1] always3(s26) || -> . % 76.04/76.22 42754[103:SSi:42753.0,715.0,41891.0,41896.0] || -> . % 76.04/76.22 42755[101:Spt:42754.0,42297.0,42298.0] || until2p7(s25)*+ -> . % 76.04/76.22 42756[101:Spt:42754.0,42297.1] || -> node4(s24)*. % 76.04/76.22 42758[101:MRR:846.0,42756.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.22 42761[101:Res:53.1,42758.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.22 42766[102:Spt:42761.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.22 42768[102:Res:42766.0,61.1] always3(s24) || -> . % 76.04/76.22 42769[102:SSi:42768.0,713.0,41882.0,41887.0,42296.0,42756.0] || -> . % 76.04/76.22 42770[102:Spt:42769.0,42761.0,42766.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.22 42771[102:Spt:42769.0,42761.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.22 42775[102:Res:42771.0,61.1] always3(s25) || -> . % 76.04/76.22 42776[102:SSi:42775.0,714.0,41888.0,41890.0] || -> . % 76.04/76.22 42777[100:Spt:42776.0,42295.0,42296.0] || until2p7(s24)*+ -> . % 76.04/76.22 42778[100:Spt:42776.0,42295.1] || -> node4(s23)*. % 76.04/76.22 42780[100:MRR:849.0,42778.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.22 42783[100:Res:53.1,42780.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.22 42785[101:Spt:42783.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.22 42787[101:Res:42785.0,61.1] always3(s23) || -> . % 76.04/76.22 42788[101:SSi:42787.0,712.0,41879.0,41881.0,42294.0,42778.0] || -> . % 76.04/76.22 42789[101:Spt:42788.0,42783.0,42785.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.22 42790[101:Spt:42788.0,42783.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.22 42794[101:Res:42790.0,61.1] always3(s24) || -> . % 76.04/76.22 42795[101:SSi:42794.0,713.0,41882.0,41887.0] || -> . % 76.04/76.22 42796[99:Spt:42795.0,42293.0,42294.0] || until2p7(s23)*+ -> . % 76.04/76.22 42797[99:Spt:42795.0,42293.1] || -> node4(s22)*. % 76.04/76.22 42799[99:MRR:852.0,42797.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.22 42802[99:Res:53.1,42799.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.22 42804[100:Spt:42802.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.22 42806[100:Res:42804.0,61.1] always3(s22) || -> . % 76.04/76.22 42807[100:SSi:42806.0,711.0,41873.0,41878.0,42292.0,42797.0] || -> . % 76.04/76.22 42808[100:Spt:42807.0,42802.0,42804.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.22 42809[100:Spt:42807.0,42802.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.22 42813[100:Res:42809.0,61.1] always3(s23) || -> . % 76.04/76.22 42814[100:SSi:42813.0,712.0,41879.0,41881.0] || -> . % 76.04/76.22 42815[98:Spt:42814.0,42291.0,42292.0] || until2p7(s22)*+ -> . % 76.04/76.22 42816[98:Spt:42814.0,42291.1] || -> node4(s21)*. % 76.04/76.22 42818[98:MRR:855.0,42816.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.22 42821[98:Res:53.1,42818.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.22 42823[99:Spt:42821.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.22 42825[99:Res:42823.0,61.1] always3(s21) || -> . % 76.04/76.22 42826[99:SSi:42825.0,710.0,41870.0,41872.0,42290.0,42816.0] || -> . % 76.04/76.22 42827[99:Spt:42826.0,42821.0,42823.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.22 42828[99:Spt:42826.0,42821.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.22 42832[99:Res:42828.0,61.1] always3(s22) || -> . % 76.04/76.22 42833[99:SSi:42832.0,711.0,41873.0,41878.0] || -> . % 76.04/76.22 42834[97:Spt:42833.0,42289.0,42290.0] || until2p7(s21)*+ -> . % 76.04/76.22 42835[97:Spt:42833.0,42289.1] || -> node4(s20)*. % 76.04/76.22 42837[97:MRR:858.0,42835.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.22 42840[97:Res:53.1,42837.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.22 42845[98:Spt:42840.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.22 42847[98:Res:42845.0,61.1] always3(s20) || -> . % 76.04/76.22 42848[98:SSi:42847.0,709.0,41864.0,41869.0,42288.0,42835.0] || -> . % 76.04/76.22 42849[98:Spt:42848.0,42840.0,42845.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.22 42850[98:Spt:42848.0,42840.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.22 42854[98:Res:42850.0,61.1] always3(s21) || -> . % 76.04/76.22 42855[98:SSi:42854.0,710.0,41870.0,41872.0] || -> . % 76.04/76.22 42856[96:Spt:42855.0,42287.0,42288.0] || until2p7(s20)*+ -> . % 76.04/76.22 42857[96:Spt:42855.0,42287.1] || -> node4(s19)*. % 76.04/76.22 42859[96:MRR:861.0,42857.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.22 42862[96:Res:53.1,42859.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.22 42864[97:Spt:42862.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.22 42866[97:Res:42864.0,61.1] always3(s19) || -> . % 76.04/76.22 42867[97:SSi:42866.0,708.0,41861.0,41863.0,42286.0,42857.0] || -> . % 76.04/76.22 42868[97:Spt:42867.0,42862.0,42864.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.22 42869[97:Spt:42867.0,42862.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.22 42873[97:Res:42869.0,61.1] always3(s20) || -> . % 76.04/76.22 42874[97:SSi:42873.0,709.0,41864.0,41869.0] || -> . % 76.04/76.22 42875[95:Spt:42874.0,42283.0,42286.0] || until2p7(s19)*+ -> . % 76.04/76.22 42876[95:Spt:42874.0,42283.1] || -> node4(s18)*. % 76.04/76.22 42878[95:MRR:864.0,42876.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.22 42881[95:Res:53.1,42878.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.22 42883[95:MRR:42881.0,42268.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.22 42885[95:Res:42883.0,61.1] always3(s19) || -> . % 76.04/76.22 42886[95:SSi:42885.0,708.0,41861.0,41863.0] || -> . % 76.04/76.22 42887[92:Spt:42886.0,42112.2,42114.0] || xuntil6(s48)*+ -> . % 76.04/76.22 42888[92:Spt:42886.0,42112.0,42112.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.22 42889[92:Res:53.1,42888.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.22 42891[92:MRR:42889.0,42101.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.22 42894[92:Res:42891.0,61.1] always3(s49) || -> . % 76.04/76.22 42895[92:SSi:42894.0,50.0,738.0] || -> . % 76.04/76.22 42896[91:Spt:42895.0,42105.1,42110.0] || xuntil6(s47)* -> . % 76.04/76.22 42897[91:Spt:42895.0,42105.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.22 42900[91:Res:42897.0,61.1] always3(s47) || -> . % 76.04/76.22 42901[91:SSi:42900.0,736.0,42095.0] || -> . % 76.04/76.22 42902[89:Spt:42901.0,42086.2,42094.0] || xuntil6(s46)*+ -> . % 76.04/76.22 42903[89:Spt:42901.0,42086.0,42086.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.22 42904[89:Res:53.1,42903.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.22 42906[89:MRR:42904.0,42078.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.22 42908[89:Res:42906.0,61.1] always3(s47) || -> . % 76.04/76.22 42909[89:SSi:42908.0,736.0] || -> . % 76.04/76.22 42910[88:Spt:42909.0,42082.1,42084.0] || xuntil6(s45)* -> . % 76.04/76.22 42911[88:Spt:42909.0,42082.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.22 42914[88:Res:42911.0,61.1] always3(s45) || -> . % 76.04/76.22 42915[88:SSi:42914.0,734.0,42072.0] || -> . % 76.04/76.22 42916[86:Spt:42915.0,42066.2,42071.0] || xuntil6(s44)*+ -> . % 76.04/76.22 42917[86:Spt:42915.0,42066.0,42066.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.22 42918[86:Res:53.1,42917.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.22 42920[86:MRR:42918.0,42058.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.22 42923[86:Res:42920.0,61.1] always3(s45) || -> . % 76.04/76.22 42924[86:SSi:42923.0,734.0] || -> . % 76.04/76.22 42925[85:Spt:42924.0,42062.1,42064.0] || xuntil6(s43)* -> . % 76.04/76.22 42926[85:Spt:42924.0,42062.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.22 42929[85:Res:42926.0,61.1] always3(s43) || -> . % 76.04/76.22 42930[85:SSi:42929.0,732.0,42052.0] || -> . % 76.04/76.22 42931[83:Spt:42930.0,42049.2,42051.0] || xuntil6(s42)*+ -> . % 76.04/76.22 42932[83:Spt:42930.0,42049.0,42049.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.22 42933[83:Res:53.1,42932.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.22 42935[83:MRR:42933.0,42038.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.22 42937[83:Res:42935.0,61.1] always3(s43) || -> . % 76.04/76.22 42938[83:SSi:42937.0,732.0] || -> . % 76.04/76.22 42939[82:Spt:42938.0,42042.1,42047.0] || xuntil6(s41)* -> . % 76.04/76.22 42940[82:Spt:42938.0,42042.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.22 42943[82:Res:42940.0,61.1] always3(s41) || -> . % 76.04/76.22 42944[82:SSi:42943.0,730.0,42032.0] || -> . % 76.04/76.22 42945[80:Spt:42944.0,42023.2,42031.0] || xuntil6(s40)*+ -> . % 76.04/76.22 42946[80:Spt:42944.0,42023.0,42023.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.22 42947[80:Res:53.1,42946.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.22 42949[80:MRR:42947.0,42015.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.22 42951[80:Res:42949.0,61.1] always3(s41) || -> . % 76.04/76.22 42952[80:SSi:42951.0,730.0] || -> . % 76.04/76.22 42953[79:Spt:42952.0,42019.1,42021.0] || xuntil6(s39)* -> . % 76.04/76.22 42954[79:Spt:42952.0,42019.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.22 42957[79:Res:42954.0,61.1] always3(s39) || -> . % 76.04/76.22 42958[79:SSi:42957.0,728.0,42009.0] || -> . % 76.04/76.22 42959[77:Spt:42958.0,42003.2,42008.0] || xuntil6(s38)*+ -> . % 76.04/76.22 42960[77:Spt:42958.0,42003.0,42003.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.22 42961[77:Res:53.1,42960.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.22 42963[77:MRR:42961.0,41995.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.22 42965[77:Res:42963.0,61.1] always3(s39) || -> . % 76.04/76.22 42966[77:SSi:42965.0,728.0] || -> . % 76.04/76.22 42967[76:Spt:42966.0,41999.1,42001.0] || xuntil6(s37)* -> . % 76.04/76.22 42968[76:Spt:42966.0,41999.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.22 42971[76:Res:42968.0,61.1] always3(s37) || -> . % 76.04/76.22 42972[76:SSi:42971.0,726.0,41989.0] || -> . % 76.04/76.22 42973[74:Spt:42972.0,41986.2,41988.0] || xuntil6(s36)*+ -> . % 76.04/76.22 42974[74:Spt:42972.0,41986.0,41986.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.22 42975[74:Res:53.1,42974.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.22 42977[74:MRR:42975.0,41975.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.22 42979[74:Res:42977.0,61.1] always3(s37) || -> . % 76.04/76.22 42980[74:SSi:42979.0,726.0] || -> . % 76.04/76.22 42981[73:Spt:42980.0,41979.1,41984.0] || xuntil6(s35)* -> . % 76.04/76.22 42982[73:Spt:42980.0,41979.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.22 42985[73:Res:42982.0,61.1] always3(s35) || -> . % 76.04/76.22 42986[73:SSi:42985.0,724.0,41969.0] || -> . % 76.04/76.22 42987[71:Spt:42986.0,41960.2,41968.0] || xuntil6(s34)*+ -> . % 76.04/76.22 42988[71:Spt:42986.0,41960.0,41960.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.22 42989[71:Res:53.1,42988.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.22 42991[71:MRR:42989.0,41952.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.22 42993[71:Res:42991.0,61.1] always3(s35) || -> . % 76.04/76.22 42994[71:SSi:42993.0,724.0] || -> . % 76.04/76.22 42995[70:Spt:42994.0,41956.1,41958.0] || xuntil6(s33)* -> . % 76.04/76.22 42996[70:Spt:42994.0,41956.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.22 42999[70:Res:42996.0,61.1] always3(s33) || -> . % 76.04/76.22 43000[70:SSi:42999.0,722.0,41946.0] || -> . % 76.04/76.22 43001[68:Spt:43000.0,41940.2,41945.0] || xuntil6(s32)*+ -> . % 76.04/76.22 43002[68:Spt:43000.0,41940.0,41940.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.22 43003[68:Res:53.1,43002.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.22 43005[68:MRR:43003.0,41932.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.22 43007[68:Res:43005.0,61.1] always3(s33) || -> . % 76.04/76.22 43008[68:SSi:43007.0,722.0] || -> . % 76.04/76.22 43009[67:Spt:43008.0,41936.1,41938.0] || xuntil6(s31)* -> . % 76.04/76.22 43010[67:Spt:43008.0,41936.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.22 43013[67:Res:43010.0,61.1] always3(s31) || -> . % 76.04/76.22 43014[67:SSi:43013.0,720.0,41926.0] || -> . % 76.04/76.22 43015[65:Spt:43014.0,41923.2,41925.0] || xuntil6(s30)*+ -> . % 76.04/76.22 43016[65:Spt:43014.0,41923.0,41923.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.22 43017[65:Res:53.1,43016.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.22 43019[65:MRR:43017.0,41912.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.22 43021[65:Res:43019.0,61.1] always3(s31) || -> . % 76.04/76.22 43022[65:SSi:43021.0,720.0] || -> . % 76.04/76.22 43023[64:Spt:43022.0,41916.1,41921.0] || xuntil6(s29)* -> . % 76.04/76.22 43024[64:Spt:43022.0,41916.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.22 43027[64:Res:43024.0,61.1] always3(s29) || -> . % 76.04/76.22 43028[64:SSi:43027.0,718.0,41906.0] || -> . % 76.04/76.22 43029[62:Spt:43028.0,41901.2,41905.0] || xuntil6(s28)*+ -> . % 76.04/76.22 43030[62:Spt:43028.0,41901.0,41901.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.22 43031[62:Res:53.1,43030.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.22 43033[63:Spt:43031.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.22 43035[63:Res:43033.0,61.1] always3(s29) || -> . % 76.04/76.22 43036[63:SSi:43035.0,718.0] || -> . % 76.04/76.22 43037[63:Spt:43036.0,43031.1,43033.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.22 43038[63:Spt:43036.0,43031.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.22 43041[63:Res:43038.0,61.1] always3(s28) || -> . % 76.04/76.22 43042[63:SSi:43041.0,717.0,41900.0] || -> . % 76.04/76.22 43043[61:Spt:43042.0,41898.2,41899.0] || xuntil6(s27)*+ -> . % 76.04/76.22 43044[61:Spt:43042.0,41898.0,41898.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.22 43045[61:Res:53.1,43044.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.22 43047[62:Spt:43045.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.22 43049[62:Res:43047.0,61.1] always3(s28) || -> . % 76.04/76.22 43050[62:SSi:43049.0,717.0] || -> . % 76.04/76.22 43051[62:Spt:43050.0,43045.1,43047.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.22 43052[62:Spt:43050.0,43045.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.22 43055[62:Res:43052.0,61.1] always3(s27) || -> . % 76.04/76.22 43056[62:SSi:43055.0,716.0,41897.0] || -> . % 76.04/76.22 43057[60:Spt:43056.0,41892.2,41896.0] || xuntil6(s26)*+ -> . % 76.04/76.22 43058[60:Spt:43056.0,41892.0,41892.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.22 43059[60:Res:53.1,43058.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.22 43061[61:Spt:43059.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.22 43063[61:Res:43061.0,61.1] always3(s27) || -> . % 76.04/76.22 43064[61:SSi:43063.0,716.0] || -> . % 76.04/76.22 43065[61:Spt:43064.0,43059.1,43061.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.22 43066[61:Spt:43064.0,43059.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.22 43069[61:Res:43066.0,61.1] always3(s26) || -> . % 76.04/76.22 43070[61:SSi:43069.0,715.0,41891.0] || -> . % 76.04/76.22 43071[59:Spt:43070.0,41889.2,41890.0] || xuntil6(s25)*+ -> . % 76.04/76.22 43072[59:Spt:43070.0,41889.0,41889.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.22 43073[59:Res:53.1,43072.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.22 43075[60:Spt:43073.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.22 43077[60:Res:43075.0,61.1] always3(s26) || -> . % 76.04/76.22 43078[60:SSi:43077.0,715.0] || -> . % 76.04/76.22 43079[60:Spt:43078.0,43073.1,43075.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.22 43080[60:Spt:43078.0,43073.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.22 43083[60:Res:43080.0,61.1] always3(s25) || -> . % 76.04/76.22 43084[60:SSi:43083.0,714.0,41888.0] || -> . % 76.04/76.22 43085[58:Spt:43084.0,41883.2,41887.0] || xuntil6(s24)*+ -> . % 76.04/76.22 43086[58:Spt:43084.0,41883.0,41883.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.22 43087[58:Res:53.1,43086.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.22 43089[59:Spt:43087.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.22 43091[59:Res:43089.0,61.1] always3(s25) || -> . % 76.04/76.22 43092[59:SSi:43091.0,714.0] || -> . % 76.04/76.22 43093[59:Spt:43092.0,43087.1,43089.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.22 43094[59:Spt:43092.0,43087.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.22 43097[59:Res:43094.0,61.1] always3(s24) || -> . % 76.04/76.22 43098[59:SSi:43097.0,713.0,41882.0] || -> . % 76.04/76.22 43099[57:Spt:43098.0,41880.2,41881.0] || xuntil6(s23)*+ -> . % 76.04/76.22 43100[57:Spt:43098.0,41880.0,41880.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.22 43101[57:Res:53.1,43100.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.22 43103[58:Spt:43101.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.22 43105[58:Res:43103.0,61.1] always3(s24) || -> . % 76.04/76.22 43106[58:SSi:43105.0,713.0] || -> . % 76.04/76.22 43107[58:Spt:43106.0,43101.1,43103.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.22 43108[58:Spt:43106.0,43101.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.22 43111[58:Res:43108.0,61.1] always3(s23) || -> . % 76.04/76.22 43112[58:SSi:43111.0,712.0,41879.0] || -> . % 76.04/76.22 43113[56:Spt:43112.0,41874.2,41878.0] || xuntil6(s22)*+ -> . % 76.04/76.22 43114[56:Spt:43112.0,41874.0,41874.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.22 43115[56:Res:53.1,43114.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.22 43117[57:Spt:43115.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.22 43119[57:Res:43117.0,61.1] always3(s23) || -> . % 76.04/76.22 43120[57:SSi:43119.0,712.0] || -> . % 76.04/76.22 43121[57:Spt:43120.0,43115.1,43117.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.22 43122[57:Spt:43120.0,43115.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.22 43125[57:Res:43122.0,61.1] always3(s22) || -> . % 76.04/76.22 43126[57:SSi:43125.0,711.0,41873.0] || -> . % 76.04/76.22 43127[55:Spt:43126.0,41871.2,41872.0] || xuntil6(s21)*+ -> . % 76.04/76.22 43128[55:Spt:43126.0,41871.0,41871.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.22 43129[55:Res:53.1,43128.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.22 43131[56:Spt:43129.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.22 43133[56:Res:43131.0,61.1] always3(s22) || -> . % 76.04/76.22 43134[56:SSi:43133.0,711.0] || -> . % 76.04/76.22 43135[56:Spt:43134.0,43129.1,43131.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.22 43136[56:Spt:43134.0,43129.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.22 43139[56:Res:43136.0,61.1] always3(s21) || -> . % 76.04/76.22 43140[56:SSi:43139.0,710.0,41870.0] || -> . % 76.04/76.22 43141[54:Spt:43140.0,41865.2,41869.0] || xuntil6(s20)*+ -> . % 76.04/76.22 43142[54:Spt:43140.0,41865.0,41865.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.22 43143[54:Res:53.1,43142.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.22 43148[55:Spt:43143.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.22 43150[55:Res:43148.0,61.1] always3(s21) || -> . % 76.04/76.22 43151[55:SSi:43150.0,710.0] || -> . % 76.04/76.22 43152[55:Spt:43151.0,43143.1,43148.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.22 43153[55:Spt:43151.0,43143.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.22 43156[55:Res:43153.0,61.1] always3(s20) || -> . % 76.04/76.22 43157[55:SSi:43156.0,709.0,41864.0] || -> . % 76.04/76.22 43158[53:Spt:43157.0,41862.2,41863.0] || xuntil6(s19)*+ -> . % 76.04/76.22 43159[53:Spt:43157.0,41862.0,41862.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.22 43160[53:Res:53.1,43159.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.22 43162[54:Spt:43160.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.22 43164[54:Res:43162.0,61.1] always3(s19) || -> . % 76.04/76.22 43165[54:SSi:43164.0,708.0,41861.0] || -> . % 76.04/76.22 43166[54:Spt:43165.0,43160.0,43162.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.22 43167[54:Spt:43165.0,43160.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.22 43171[54:Res:43167.0,61.1] always3(s20) || -> . % 76.04/76.22 43172[54:SSi:43171.0,709.0] || -> . % 76.04/76.22 43173[52:Spt:43172.0,41856.2,41860.0] || xuntil6(s18)*+ -> . % 76.04/76.22 43174[52:Spt:43172.0,41856.0,41856.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.22 43175[52:Res:53.1,43174.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.22 43177[53:Spt:43175.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.22 43179[53:Res:43177.0,61.1] always3(s19) || -> . % 76.04/76.22 43180[53:SSi:43179.0,708.0] || -> . % 76.04/76.22 43181[53:Spt:43180.0,43175.1,43177.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.22 43182[53:Spt:43180.0,43175.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.22 43185[53:Res:43182.0,61.1] always3(s18) || -> . % 76.04/76.22 43186[53:SSi:43185.0,707.0,41855.0] || -> . % 76.04/76.22 43187[51:Spt:43186.0,41853.2,41854.0] || xuntil6(s17)*+ -> . % 76.04/76.22 43188[51:Spt:43186.0,41853.0,41853.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.22 43189[51:Res:53.1,43188.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.22 43194[52:Spt:43189.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.22 43196[52:Res:43194.0,61.1] always3(s17) || -> . % 76.04/76.22 43197[52:SSi:43196.0,706.0,41852.0] || -> . % 76.04/76.22 43198[52:Spt:43197.0,43189.0,43194.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.22 43199[52:Spt:43197.0,43189.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.22 43203[52:Res:43199.0,61.1] always3(s18) || -> . % 76.04/76.22 43204[52:SSi:43203.0,707.0] || -> . % 76.04/76.22 43205[50:Spt:43204.0,41847.2,41851.0] || xuntil6(s16)*+ -> . % 76.04/76.22 43206[50:Spt:43204.0,41847.0,41847.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.22 43207[50:Res:53.1,43206.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.22 43209[51:Spt:43207.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.22 43211[51:Res:43209.0,61.1] always3(s16) || -> . % 76.04/76.22 43212[51:SSi:43211.0,705.0,41846.0] || -> . % 76.04/76.22 43213[51:Spt:43212.0,43207.0,43209.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.22 43214[51:Spt:43212.0,43207.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.22 43218[51:Res:43214.0,61.1] always3(s17) || -> . % 76.04/76.22 43219[51:SSi:43218.0,706.0] || -> . % 76.04/76.22 43220[49:Spt:43219.0,41844.2,41845.0] || xuntil6(s15)*+ -> . % 76.04/76.22 43221[49:Spt:43219.0,41844.0,41844.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.22 43222[49:Res:53.1,43221.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.22 43224[50:Spt:43222.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.22 43226[50:Res:43224.0,61.1] always3(s15) || -> . % 76.04/76.22 43227[50:SSi:43226.0,704.0,41843.0] || -> . % 76.04/76.22 43228[50:Spt:43227.0,43222.0,43224.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.22 43229[50:Spt:43227.0,43222.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.22 43233[50:Res:43229.0,61.1] always3(s16) || -> . % 76.04/76.22 43234[50:SSi:43233.0,705.0] || -> . % 76.04/76.22 43235[48:Spt:43234.0,41838.2,41842.0] || xuntil6(s14)*+ -> . % 76.04/76.22 43236[48:Spt:43234.0,41838.0,41838.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.22 43237[48:Res:53.1,43236.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.22 43242[49:Spt:43237.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.22 43244[49:Res:43242.0,61.1] always3(s14) || -> . % 76.04/76.22 43245[49:SSi:43244.0,703.0,41837.0] || -> . % 76.04/76.22 43246[49:Spt:43245.0,43237.0,43242.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.22 43247[49:Spt:43245.0,43237.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.22 43251[49:Res:43247.0,61.1] always3(s15) || -> . % 76.04/76.22 43252[49:SSi:43251.0,704.0] || -> . % 76.04/76.22 43253[47:Spt:43252.0,41835.2,41836.0] || xuntil6(s13)*+ -> . % 76.04/76.22 43254[47:Spt:43252.0,41835.0,41835.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.22 43255[47:Res:53.1,43254.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.22 43257[48:Spt:43255.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.22 43259[48:Res:43257.0,61.1] always3(s13) || -> . % 76.04/76.22 43260[48:SSi:43259.0,702.0,41834.0] || -> . % 76.04/76.22 43261[48:Spt:43260.0,43255.0,43257.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.22 43262[48:Spt:43260.0,43255.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.22 43266[48:Res:43262.0,61.1] always3(s14) || -> . % 76.04/76.22 43267[48:SSi:43266.0,703.0] || -> . % 76.04/76.22 43268[46:Spt:43267.0,41829.2,41833.0] || xuntil6(s12)*+ -> . % 76.04/76.22 43269[46:Spt:43267.0,41829.0,41829.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.22 43270[46:Res:53.1,43269.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.22 43272[47:Spt:43270.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.22 43274[47:Res:43272.0,61.1] always3(s12) || -> . % 76.04/76.22 43275[47:SSi:43274.0,701.0,41828.0] || -> . % 76.04/76.22 43276[47:Spt:43275.0,43270.0,43272.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.22 43277[47:Spt:43275.0,43270.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.22 43281[47:Res:43277.0,61.1] always3(s13) || -> . % 76.04/76.22 43282[47:SSi:43281.0,702.0] || -> . % 76.04/76.22 43283[45:Spt:43282.0,41826.2,41827.0] || xuntil6(s11)*+ -> . % 76.04/76.22 43284[45:Spt:43282.0,41826.0,41826.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.22 43285[45:Res:53.1,43284.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.22 43290[46:Spt:43285.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.22 43292[46:Res:43290.0,61.1] always3(s11) || -> . % 76.04/76.22 43293[46:SSi:43292.0,700.0,41825.0] || -> . % 76.04/76.22 43294[46:Spt:43293.0,43285.0,43290.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.22 43295[46:Spt:43293.0,43285.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.22 43299[46:Res:43295.0,61.1] always3(s12) || -> . % 76.04/76.22 43300[46:SSi:43299.0,701.0] || -> . % 76.04/76.22 43301[44:Spt:43300.0,41820.2,41824.0] || xuntil6(s10)*+ -> . % 76.04/76.22 43302[44:Spt:43300.0,41820.0,41820.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.22 43303[44:Res:53.1,43302.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.22 43305[45:Spt:43303.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.22 43307[45:Res:43305.0,61.1] always3(s10) || -> . % 76.04/76.22 43308[45:SSi:43307.0,699.0,41819.0] || -> . % 76.04/76.22 43309[45:Spt:43308.0,43303.0,43305.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.22 43310[45:Spt:43308.0,43303.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.22 43314[45:Res:43310.0,61.1] always3(s11) || -> . % 76.04/76.22 43315[45:SSi:43314.0,700.0] || -> . % 76.04/76.22 43316[43:Spt:43315.0,41817.2,41818.0] || xuntil6(s9)*+ -> . % 76.04/76.22 43317[43:Spt:43315.0,41817.0,41817.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.22 43318[43:Res:53.1,43317.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.22 43320[44:Spt:43318.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.22 43322[44:Res:43320.0,61.1] always3(s9) || -> . % 76.04/76.22 43323[44:SSi:43322.0,698.0,41816.0] || -> . % 76.04/76.22 43324[44:Spt:43323.0,43318.0,43320.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.22 43325[44:Spt:43323.0,43318.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.22 43329[44:Res:43325.0,61.1] always3(s10) || -> . % 76.04/76.22 43330[44:SSi:43329.0,699.0] || -> . % 76.04/76.22 43331[42:Spt:43330.0,41811.2,41815.0] || xuntil6(s8)*+ -> . % 76.04/76.22 43332[42:Spt:43330.0,41811.0,41811.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.22 43333[42:Res:53.1,43332.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.22 43338[43:Spt:43333.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.22 43340[43:Res:43338.0,61.1] always3(s8) || -> . % 76.04/76.22 43341[43:SSi:43340.0,697.0,41810.0] || -> . % 76.04/76.22 43342[43:Spt:43341.0,43333.0,43338.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.22 43343[43:Spt:43341.0,43333.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.22 43347[43:Res:43343.0,61.1] always3(s9) || -> . % 76.04/76.22 43348[43:SSi:43347.0,698.0] || -> . % 76.04/76.22 43349[41:Spt:43348.0,41808.2,41809.0] || xuntil6(s7)*+ -> . % 76.04/76.22 43350[41:Spt:43348.0,41808.0,41808.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.22 43351[41:Res:53.1,43350.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.22 43353[42:Spt:43351.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.22 43355[42:Res:43353.0,61.1] always3(s7) || -> . % 76.04/76.22 43356[42:SSi:43355.0,696.0,41807.0] || -> . % 76.04/76.22 43357[42:Spt:43356.0,43351.0,43353.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.22 43358[42:Spt:43356.0,43351.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.22 43362[42:Res:43358.0,61.1] always3(s8) || -> . % 76.04/76.22 43363[42:SSi:43362.0,697.0] || -> . % 76.04/76.22 43364[40:Spt:43363.0,41802.2,41806.0] || xuntil6(s6)*+ -> . % 76.04/76.22 43365[40:Spt:43363.0,41802.0,41802.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.22 43366[40:Res:53.1,43365.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.22 43368[41:Spt:43366.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.22 43370[41:Res:43368.0,61.1] always3(s6) || -> . % 76.04/76.22 43371[41:SSi:43370.0,695.0,41801.0] || -> . % 76.04/76.22 43372[41:Spt:43371.0,43366.0,43368.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.22 43373[41:Spt:43371.0,43366.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.22 43377[41:Res:43373.0,61.1] always3(s7) || -> . % 76.04/76.22 43378[41:SSi:43377.0,696.0] || -> . % 76.04/76.22 43379[39:Spt:43378.0,41799.2,41800.0] || xuntil6(s5)*+ -> . % 76.04/76.22 43380[39:Spt:43378.0,41799.0,41799.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.22 43381[39:Res:53.1,43380.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.22 43386[40:Spt:43381.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.22 43388[40:Res:43386.0,61.1] always3(s5) || -> . % 76.04/76.22 43389[40:SSi:43388.0,694.0,41798.0] || -> . % 76.04/76.22 43390[40:Spt:43389.0,43381.0,43386.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.22 43391[40:Spt:43389.0,43381.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.22 43395[40:Res:43391.0,61.1] always3(s6) || -> . % 76.04/76.22 43396[40:SSi:43395.0,695.0] || -> . % 76.04/76.22 43397[38:Spt:43396.0,41793.2,41797.0] || xuntil6(s4)*+ -> . % 76.04/76.22 43398[38:Spt:43396.0,41793.0,41793.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.22 43399[38:Res:53.1,43398.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.22 43401[39:Spt:43399.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.22 43403[39:Res:43401.0,61.1] always3(s4) || -> . % 76.04/76.22 43404[39:SSi:43403.0,693.0,41792.0] || -> . % 76.04/76.22 43405[39:Spt:43404.0,43399.0,43401.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.22 43406[39:Spt:43404.0,43399.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.22 43410[39:Res:43406.0,61.1] always3(s5) || -> . % 76.04/76.22 43411[39:SSi:43410.0,694.0] || -> . % 76.04/76.22 43412[37:Spt:43411.0,41790.2,41791.0] || xuntil6(s3)*+ -> . % 76.04/76.22 43413[37:Spt:43411.0,41790.0,41790.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.22 43414[37:Res:53.1,43413.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.22 43416[38:Spt:43414.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.22 43418[38:Res:43416.0,61.1] always3(s3) || -> . % 76.04/76.22 43419[38:SSi:43418.0,692.0,41789.0] || -> . % 76.04/76.22 43420[38:Spt:43419.0,43414.0,43416.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.22 43421[38:Spt:43419.0,43414.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.22 43425[38:Res:43421.0,61.1] always3(s4) || -> . % 76.04/76.22 43426[38:SSi:43425.0,693.0] || -> . % 76.04/76.22 43427[36:Spt:43426.0,41784.2,41788.0] || xuntil6(s2)*+ -> . % 76.04/76.22 43428[36:Spt:43426.0,41784.0,41784.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.22 43429[36:Res:53.1,43428.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.22 43434[37:Spt:43429.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.22 43436[37:Res:43434.0,61.1] always3(s2) || -> . % 76.04/76.22 43437[37:SSi:43436.0,691.0,41783.0] || -> . % 76.04/76.22 43438[37:Spt:43437.0,43429.0,43434.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.22 43439[37:Spt:43437.0,43429.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.22 43443[37:Res:43439.0,61.1] always3(s3) || -> . % 76.04/76.22 43444[37:SSi:43443.0,692.0] || -> . % 76.04/76.22 43445[35:Spt:43444.0,41778.2,41782.0] || xuntil6(s1)*+ -> . % 76.04/76.22 43446[35:Spt:43444.0,41778.0,41778.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.22 43447[35:Res:53.1,43446.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.22 43449[36:Spt:43447.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.22 43451[36:Res:43449.0,61.1] always3(s1) || -> . % 76.04/76.22 43452[36:SSi:43451.0,690.0,41777.0] || -> . % 76.04/76.22 43453[36:Spt:43452.0,43447.0,43449.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.22 43454[36:Spt:43452.0,43447.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.22 43459[36:Res:43454.0,61.1] always3(s2) || -> . % 76.04/76.22 43460[36:SSi:43459.0,691.0] || -> . % 76.04/76.22 43461[34:Spt:43460.0,74.0,41776.0] || xuntil6(s0)*+ -> . % 76.04/76.22 43462[34:Spt:43460.0,74.1] || -> node4(s0)*. % 76.04/76.22 43463[34:MRR:758.1,43461.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.22 43465[34:Res:43463.0,61.1] always3(s1) || -> . % 76.04/76.22 43466[34:SSi:43465.0,690.0] || -> . % 76.04/76.22 43467[33:Spt:43466.0,41766.0,41770.0] || trans(s49,s18)*+ -> . % 76.04/76.22 43468[33:Spt:43466.0,41766.1,41766.2,41766.3,41766.4,41766.5,41766.6,41766.7,41766.8,41766.9,41766.10,41766.11,41766.12,41766.13,41766.14,41766.15,41766.16,41766.17,41766.18] || -> trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.22 43470[33:MRR:41767.0,43467.0] || -> trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.22 43471[33:MRR:41769.1,43467.0] xuntil6(s49) || -> trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.22 43472[34:Spt:43468.0] || -> trans(s49,s17)*. % 76.04/76.22 43473[34:Res:43472.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s17)*. % 76.04/76.22 43475[34:Res:43472.0,60.0] || -> node2(s49,s17)*. % 76.04/76.22 43476[34:SSi:43473.1,50.0,738.0] xuntil6(s49) || -> until2p7(s17)*. % 76.04/76.22 43477[34:Res:43475.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)*. % 76.04/76.22 43478[35:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.22 43479[35:MRR:176.0,43478.0] || -> until5(s1)*. % 76.04/76.22 43480[35:MRR:42218.0,43479.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.22 43487[36:Spt:43480.2] || -> xuntil6(s1)*. % 76.04/76.22 43488[36:MRR:175.0,43487.0] || -> until5(s2)*. % 76.04/76.22 43489[36:MRR:42214.0,43488.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.22 43490[37:Spt:43489.2] || -> xuntil6(s2)*. % 76.04/76.22 43491[37:MRR:174.0,43490.0] || -> until5(s3)*. % 76.04/76.22 43492[37:MRR:42210.0,43491.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.22 43496[38:Spt:43492.2] || -> xuntil6(s3)*. % 76.04/76.22 43497[38:MRR:173.0,43496.0] || -> until5(s4)*. % 76.04/76.22 43498[38:MRR:42206.0,43497.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.22 43499[39:Spt:43498.2] || -> xuntil6(s4)*. % 76.04/76.22 43500[39:MRR:172.0,43499.0] || -> until5(s5)*. % 76.04/76.22 43501[39:MRR:42205.0,43500.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.22 43505[40:Spt:43501.2] || -> xuntil6(s5)*. % 76.04/76.22 43506[40:MRR:171.0,43505.0] || -> until5(s6)*. % 76.04/76.22 43507[40:MRR:42198.0,43506.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.22 43508[41:Spt:43507.2] || -> xuntil6(s6)*. % 76.04/76.22 43509[41:MRR:170.0,43508.0] || -> until5(s7)*. % 76.04/76.22 43510[41:MRR:42194.0,43509.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.22 43514[42:Spt:43510.2] || -> xuntil6(s7)*. % 76.04/76.22 43515[42:MRR:169.0,43514.0] || -> until5(s8)*. % 76.04/76.22 43516[42:MRR:42190.0,43515.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.22 43517[43:Spt:43516.2] || -> xuntil6(s8)*. % 76.04/76.22 43518[43:MRR:168.0,43517.0] || -> until5(s9)*. % 76.04/76.22 43519[43:MRR:42186.0,43518.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.22 43523[44:Spt:43519.2] || -> xuntil6(s9)*. % 76.04/76.22 43524[44:MRR:167.0,43523.0] || -> until5(s10)*. % 76.04/76.22 43525[44:MRR:42185.0,43524.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.22 43526[45:Spt:43525.2] || -> xuntil6(s10)*. % 76.04/76.22 43527[45:MRR:166.0,43526.0] || -> until5(s11)*. % 76.04/76.22 43528[45:MRR:42178.0,43527.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.22 43532[46:Spt:43528.2] || -> xuntil6(s11)*. % 76.04/76.22 43533[46:MRR:165.0,43532.0] || -> until5(s12)*. % 76.04/76.22 43534[46:MRR:42174.0,43533.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.22 43535[47:Spt:43534.2] || -> xuntil6(s12)*. % 76.04/76.22 43536[47:MRR:164.0,43535.0] || -> until5(s13)*. % 76.04/76.22 43537[47:MRR:42170.0,43536.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.22 43541[48:Spt:43537.2] || -> xuntil6(s13)*. % 76.04/76.22 43542[48:MRR:163.0,43541.0] || -> until5(s14)*. % 76.04/76.22 43543[48:MRR:42166.0,43542.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.22 43544[49:Spt:43543.2] || -> xuntil6(s14)*. % 76.04/76.22 43545[49:MRR:162.0,43544.0] || -> until5(s15)*. % 76.04/76.22 43546[49:MRR:42165.0,43545.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.22 43550[50:Spt:43546.2] || -> xuntil6(s15)*. % 76.04/76.22 43551[50:MRR:161.0,43550.0] || -> until5(s16)*. % 76.04/76.22 43552[50:MRR:42158.0,43551.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.22 43553[51:Spt:43552.2] || -> xuntil6(s16)*. % 76.04/76.22 43554[51:MRR:160.0,43553.0] || -> until5(s17)*. % 76.04/76.22 43555[51:MRR:42154.0,43554.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.22 43559[52:Spt:43555.2] || -> xuntil6(s17)*. % 76.04/76.22 43560[52:MRR:159.0,43559.0] || -> until5(s18)*. % 76.04/76.22 43561[52:MRR:42150.0,43560.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.22 43562[53:Spt:43561.2] || -> xuntil6(s18)*. % 76.04/76.22 43563[53:MRR:158.0,43562.0] || -> until5(s19)*. % 76.04/76.22 43564[53:MRR:42143.0,43563.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.22 43568[54:Spt:43564.2] || -> xuntil6(s19)*. % 76.04/76.22 43569[54:MRR:157.0,43568.0] || -> until5(s20)*. % 76.04/76.22 43570[54:MRR:42139.0,43569.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.22 43571[55:Spt:43570.2] || -> xuntil6(s20)*. % 76.04/76.22 43572[55:MRR:156.0,43571.0] || -> until5(s21)*. % 76.04/76.22 43573[55:MRR:42135.0,43572.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.22 43577[56:Spt:43573.2] || -> xuntil6(s21)*. % 76.04/76.22 43578[56:MRR:155.0,43577.0] || -> until5(s22)*. % 76.04/76.22 43579[56:MRR:42134.0,43578.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.22 43580[57:Spt:43579.2] || -> xuntil6(s22)*. % 76.04/76.22 43581[57:MRR:154.0,43580.0] || -> until5(s23)*. % 76.04/76.22 43582[57:MRR:42127.0,43581.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.22 43586[58:Spt:43582.2] || -> xuntil6(s23)*. % 76.04/76.22 43587[58:MRR:153.0,43586.0] || -> until5(s24)*. % 76.04/76.22 43588[58:MRR:42123.0,43587.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.22 43589[59:Spt:43588.2] || -> xuntil6(s24)*. % 76.04/76.22 43590[59:MRR:152.0,43589.0] || -> until5(s25)*. % 76.04/76.22 43591[59:MRR:42119.0,43590.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.22 43595[60:Spt:43591.2] || -> xuntil6(s25)*. % 76.04/76.22 43596[60:MRR:151.0,43595.0] || -> until5(s26)*. % 76.04/76.22 43597[60:MRR:42118.0,43596.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.22 43598[61:Spt:43597.2] || -> xuntil6(s26)*. % 76.04/76.22 43599[61:MRR:150.0,43598.0] || -> until5(s27)*. % 76.04/76.22 43600[61:MRR:42117.0,43599.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.22 43604[62:Spt:43600.2] || -> xuntil6(s27)*. % 76.04/76.22 43605[62:MRR:149.0,43604.0] || -> until5(s28)*. % 76.04/76.22 43606[62:MRR:42116.0,43605.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.22 43607[63:Spt:43606.2] || -> xuntil6(s28)*. % 76.04/76.22 43608[63:MRR:148.0,43607.0] || -> until5(s29)*. % 76.04/76.22 43609[63:MRR:35647.0,43608.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.22 43613[64:Spt:43609.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.22 43615[64:Res:43613.0,61.1] always3(s30) || -> . % 76.04/76.22 43616[64:SSi:43615.0,719.0] || -> . % 76.04/76.22 43617[64:Spt:43616.0,43609.1,43613.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.04/76.22 43618[64:Spt:43616.0,43609.0,43609.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 76.04/76.22 43620[64:MRR:831.2,43617.0] node4(s29) || m_main_v_state(s29,c_ready)* -> . % 76.04/76.22 43621[64:Res:53.1,43618.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 76.04/76.22 43623[65:Spt:43621.1] || -> xuntil6(s29)*. % 76.04/76.22 43624[65:MRR:147.0,43623.0] || -> until5(s30)*. % 76.04/76.22 43625[65:MRR:42225.0,43624.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.22 43630[66:Spt:43625.2] || -> xuntil6(s30)*. % 76.04/76.22 43631[66:MRR:146.0,43630.0] || -> until5(s31)*. % 76.04/76.22 43632[66:MRR:35651.0,43631.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.22 43633[67:Spt:43632.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.22 43635[67:Res:43633.0,61.1] always3(s32) || -> . % 76.04/76.22 43636[67:SSi:43635.0,721.0] || -> . % 76.04/76.22 43637[67:Spt:43636.0,43632.1,43633.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.04/76.22 43638[67:Spt:43636.0,43632.0,43632.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.04/76.22 43640[67:MRR:825.2,43637.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.04/76.22 43641[67:Res:53.1,43638.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.04/76.22 43643[68:Spt:43641.1] || -> xuntil6(s31)*. % 76.04/76.22 43644[68:MRR:145.0,43643.0] || -> until5(s32)*. % 76.04/76.22 43645[68:MRR:42229.0,43644.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.22 43653[69:Spt:43645.2] || -> xuntil6(s32)*. % 76.04/76.22 43654[69:MRR:144.0,43653.0] || -> until5(s33)*. % 76.04/76.22 43655[69:MRR:35655.0,43654.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.22 43656[70:Spt:43655.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.22 43658[70:Res:43656.0,61.1] always3(s34) || -> . % 76.04/76.22 43659[70:SSi:43658.0,723.0] || -> . % 76.04/76.22 43660[70:Spt:43659.0,43655.1,43656.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.22 43661[70:Spt:43659.0,43655.0,43655.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.22 43663[70:MRR:819.2,43660.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.22 43664[70:Res:53.1,43661.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.22 43669[71:Spt:43664.1] || -> xuntil6(s33)*. % 76.04/76.22 43670[71:MRR:143.0,43669.0] || -> until5(s34)*. % 76.04/76.22 43671[71:MRR:42236.0,43670.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.22 43673[72:Spt:43671.2] || -> xuntil6(s34)*. % 76.04/76.22 43674[72:MRR:142.0,43673.0] || -> until5(s35)*. % 76.04/76.22 43675[72:MRR:35659.0,43674.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.22 43676[73:Spt:43675.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.22 43678[73:Res:43676.0,61.1] always3(s36) || -> . % 76.04/76.22 43679[73:SSi:43678.0,725.0] || -> . % 76.04/76.22 43680[73:Spt:43679.0,43675.1,43676.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.22 43681[73:Spt:43679.0,43675.0,43675.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.22 43683[73:MRR:813.2,43680.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.22 43684[73:Res:53.1,43681.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.22 43686[74:Spt:43684.1] || -> xuntil6(s35)*. % 76.04/76.22 43687[74:MRR:141.0,43686.0] || -> until5(s36)*. % 76.04/76.22 43688[74:MRR:42237.0,43687.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.22 43693[75:Spt:43688.2] || -> xuntil6(s36)*. % 76.04/76.22 43694[75:MRR:140.0,43693.0] || -> until5(s37)*. % 76.04/76.22 43695[75:MRR:35666.0,43694.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.22 43696[76:Spt:43695.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.22 43698[76:Res:43696.0,61.1] always3(s38) || -> . % 76.04/76.22 43699[76:SSi:43698.0,727.0] || -> . % 76.04/76.22 43700[76:Spt:43699.0,43695.1,43696.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.22 43701[76:Spt:43699.0,43695.0,43695.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.22 43703[76:MRR:807.2,43700.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.22 43704[76:Res:53.1,43701.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.22 43706[77:Spt:43704.1] || -> xuntil6(s37)*. % 76.04/76.22 43707[77:MRR:139.0,43706.0] || -> until5(s38)*. % 76.04/76.22 43708[77:MRR:42241.0,43707.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.22 43716[78:Spt:43708.2] || -> xuntil6(s38)*. % 76.04/76.22 43717[78:MRR:138.0,43716.0] || -> until5(s39)*. % 76.04/76.22 43718[78:MRR:35667.0,43717.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.22 43719[79:Spt:43718.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.22 43721[79:Res:43719.0,61.1] always3(s40) || -> . % 76.04/76.22 43722[79:SSi:43721.0,729.0] || -> . % 76.04/76.22 43723[79:Spt:43722.0,43718.1,43719.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.22 43724[79:Spt:43722.0,43718.0,43718.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.22 43726[79:MRR:801.2,43723.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.22 43727[79:Res:53.1,43724.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.22 43732[80:Spt:43727.1] || -> xuntil6(s39)*. % 76.04/76.22 43733[80:MRR:137.0,43732.0] || -> until5(s40)*. % 76.04/76.22 43734[80:MRR:42245.0,43733.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.22 43736[81:Spt:43734.2] || -> xuntil6(s40)*. % 76.04/76.22 43737[81:MRR:136.0,43736.0] || -> until5(s41)*. % 76.04/76.22 43738[81:MRR:35671.0,43737.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.22 43739[82:Spt:43738.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.22 43741[82:Res:43739.0,61.1] always3(s42) || -> . % 76.04/76.22 43742[82:SSi:43741.0,731.0] || -> . % 76.04/76.22 43743[82:Spt:43742.0,43738.1,43739.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.22 43744[82:Spt:43742.0,43738.0,43738.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.22 43746[82:MRR:795.2,43743.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.22 43747[82:Res:53.1,43744.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.22 43749[83:Spt:43747.1] || -> xuntil6(s41)*. % 76.04/76.22 43750[83:MRR:135.0,43749.0] || -> until5(s42)*. % 76.04/76.22 43751[83:MRR:42249.0,43750.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.22 43756[84:Spt:43751.2] || -> xuntil6(s42)*. % 76.04/76.22 43757[84:MRR:134.0,43756.0] || -> until5(s43)*. % 76.04/76.22 43758[84:MRR:35675.0,43757.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.22 43759[85:Spt:43758.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.22 43761[85:Res:43759.0,61.1] always3(s44) || -> . % 76.04/76.22 43762[85:SSi:43761.0,733.0] || -> . % 76.04/76.22 43763[85:Spt:43762.0,43758.1,43759.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.22 43764[85:Spt:43762.0,43758.0,43758.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.22 43766[85:MRR:789.2,43763.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.22 43767[85:Res:53.1,43764.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.22 43769[86:Spt:43767.1] || -> xuntil6(s43)*. % 76.04/76.22 43770[86:MRR:133.0,43769.0] || -> until5(s44)*. % 76.04/76.22 43771[86:MRR:42256.0,43770.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.22 43779[87:Spt:43771.2] || -> xuntil6(s44)*. % 76.04/76.22 43780[87:MRR:132.0,43779.0] || -> until5(s45)*. % 76.04/76.22 43781[87:MRR:35679.0,43780.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.22 43782[88:Spt:43781.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.22 43784[88:Res:43782.0,61.1] always3(s46) || -> . % 76.04/76.22 43785[88:SSi:43784.0,735.0] || -> . % 76.04/76.22 43786[88:Spt:43785.0,43781.1,43782.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.22 43787[88:Spt:43785.0,43781.0,43781.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.22 43789[88:MRR:783.2,43786.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.22 43790[88:Res:53.1,43787.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.22 43795[89:Spt:43790.1] || -> xuntil6(s45)*. % 76.04/76.22 43796[89:MRR:131.0,43795.0] || -> until5(s46)*. % 76.04/76.22 43797[89:MRR:42257.0,43796.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.22 43799[90:Spt:43797.2] || -> xuntil6(s46)*. % 76.04/76.22 43800[90:MRR:130.0,43799.0] || -> until5(s47)*. % 76.04/76.22 43801[90:MRR:35683.0,43800.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.22 43802[91:Spt:43801.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.22 43804[91:Res:43802.0,61.1] always3(s48) || -> . % 76.04/76.22 43805[91:SSi:43804.0,737.0] || -> . % 76.04/76.22 43806[91:Spt:43805.0,43801.1,43802.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.22 43807[91:Spt:43805.0,43801.0,43801.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.22 43809[91:MRR:777.2,43806.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.22 43810[91:Res:53.1,43807.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.22 43812[92:Spt:43810.1] || -> xuntil6(s47)*. % 76.04/76.22 43813[92:MRR:129.0,43812.0] || -> until5(s48)*. % 76.04/76.22 43814[92:MRR:42261.0,43813.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.22 43819[93:Spt:43814.2] || -> xuntil6(s48)*. % 76.04/76.22 43820[93:MRR:128.0,43819.0] || -> until5(s49)*. % 76.04/76.22 43821[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.22 43825[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.22 43826[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.22 43827[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.22 43828[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.22 43832[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.22 43833[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.22 43837[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.22 43841[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.22 43845[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.22 43852[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.22 43856[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.22 43863[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.22 43864[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.22 43868[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.22 43872[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.22 43876[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.22 43883[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.22 43884[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.22 43888[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.22 43892[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.22 43896[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.22 43903[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.22 43904[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.22 43908[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.22 43912[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.22 43916[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.22 43923[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.22 43925[34:SoR:43477.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)*. % 76.04/76.22 43927[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.22 43934[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.22 43935[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.22 43939[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.22 43943[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.22 43947[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.22 43954[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.22 43955[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.22 43959[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.22 43963[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.22 43964[34:SoR:43925.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)* xuntil6(s49). % 76.04/76.22 43965[93:SSi:43964.0,50.0,738.0,43820.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s17,c_busy)* xuntil6(s49). % 76.04/76.22 43966[94:Spt:43965.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.22 43968[94:Res:43966.0,61.1] always3(s17) || -> . % 76.04/76.22 43969[94:SSi:43968.0,706.0,43554.0,43559.0] || -> . % 76.04/76.22 43970[94:Spt:43969.0,43965.1,43966.0] || m_main_v_state(s17,c_busy)*+ -> . % 76.04/76.22 43971[94:Spt:43969.0,43965.0,43965.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.22 43975[94:MRR:43925.2,43970.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.22 43976[94:Res:53.1,43971.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.22 43981[95:Spt:43976.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.22 43983[95:Res:43981.0,61.1] always3(s49) || -> . % 76.04/76.22 43984[95:SSi:43983.0,50.0,738.0,43820.0] || -> . % 76.04/76.22 43985[95:Spt:43984.0,43976.0,43981.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.22 43986[95:Spt:43984.0,43976.1] || -> xuntil6(s49)*. % 76.04/76.22 43987[95:MRR:43476.0,43986.0] || -> until2p7(s17)*. % 76.04/76.22 43988[95:MRR:213.0,43987.0] || -> until2p7(s18)* node4(s17). % 76.04/76.22 43990[95:MRR:774.2,43985.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.22 43991[96:Spt:43988.0] || -> until2p7(s18)*. % 76.04/76.22 43992[96:MRR:214.0,43991.0] || -> until2p7(s19)* node4(s18). % 76.04/76.22 43993[97:Spt:43992.0] || -> until2p7(s19)*. % 76.04/76.22 43994[97:MRR:215.0,43993.0] || -> until2p7(s20)* node4(s19). % 76.04/76.22 43995[98:Spt:43994.0] || -> until2p7(s20)*. % 76.04/76.22 43996[98:MRR:216.0,43995.0] || -> until2p7(s21)* node4(s20). % 76.04/76.22 43997[99:Spt:43996.0] || -> until2p7(s21)*. % 76.04/76.22 43998[99:MRR:217.0,43997.0] || -> until2p7(s22)* node4(s21). % 76.04/76.22 43999[100:Spt:43998.0] || -> until2p7(s22)*. % 76.04/76.22 44000[100:MRR:218.0,43999.0] || -> until2p7(s23)* node4(s22). % 76.04/76.22 44001[101:Spt:44000.0] || -> until2p7(s23)*. % 76.04/76.22 44002[101:MRR:219.0,44001.0] || -> until2p7(s24)* node4(s23). % 76.04/76.22 44003[102:Spt:44002.0] || -> until2p7(s24)*. % 76.04/76.22 44004[102:MRR:220.0,44003.0] || -> until2p7(s25)* node4(s24). % 76.04/76.22 44005[103:Spt:44004.0] || -> until2p7(s25)*. % 76.04/76.22 44006[103:MRR:221.0,44005.0] || -> until2p7(s26)* node4(s25). % 76.04/76.22 44007[104:Spt:44006.0] || -> until2p7(s26)*. % 76.04/76.22 44008[104:MRR:222.0,44007.0] || -> until2p7(s27)* node4(s26). % 76.04/76.22 44009[105:Spt:44008.0] || -> until2p7(s27)*. % 76.04/76.22 44010[105:MRR:223.0,44009.0] || -> until2p7(s28)* node4(s27). % 76.04/76.22 44011[106:Spt:44010.0] || -> until2p7(s28)*. % 76.04/76.22 44012[106:MRR:224.0,44011.0] || -> until2p7(s29)* node4(s28). % 76.04/76.22 44013[107:Spt:44012.0] || -> until2p7(s29)*. % 76.04/76.22 44014[107:MRR:225.0,44013.0] || -> until2p7(s30)* node4(s29). % 76.04/76.22 44015[108:Spt:44014.0] || -> until2p7(s30)*. % 76.04/76.22 44016[108:MRR:226.0,44015.0] || -> until2p7(s31)* node4(s30). % 76.04/76.22 44017[109:Spt:44016.0] || -> until2p7(s31)*. % 76.04/76.22 44018[109:MRR:227.0,44017.0] || -> until2p7(s32)* node4(s31). % 76.04/76.22 44019[110:Spt:44018.0] || -> until2p7(s32)*. % 76.04/76.22 44020[110:MRR:228.0,44019.0] || -> until2p7(s33)* node4(s32). % 76.04/76.22 44021[111:Spt:44020.0] || -> until2p7(s33)*. % 76.04/76.22 44022[111:MRR:229.0,44021.0] || -> until2p7(s34)* node4(s33). % 76.04/76.22 44023[112:Spt:44022.0] || -> until2p7(s34)*. % 76.04/76.22 44024[112:MRR:230.0,44023.0] || -> until2p7(s35)* node4(s34). % 76.04/76.22 44025[113:Spt:44024.0] || -> until2p7(s35)*. % 76.04/76.22 44026[113:MRR:231.0,44025.0] || -> until2p7(s36)* node4(s35). % 76.04/76.22 44027[114:Spt:44026.0] || -> until2p7(s36)*. % 76.04/76.22 44028[114:MRR:232.0,44027.0] || -> until2p7(s37)* node4(s36). % 76.04/76.22 44029[115:Spt:44028.0] || -> until2p7(s37)*. % 76.04/76.22 44030[115:MRR:235.0,44029.0] || -> until2p7(s38)* node4(s37). % 76.04/76.22 44031[116:Spt:44030.0] || -> until2p7(s38)*. % 76.04/76.22 44032[116:MRR:236.0,44031.0] || -> until2p7(s39)* node4(s38). % 76.04/76.22 44033[117:Spt:44032.0] || -> until2p7(s39)*. % 76.04/76.22 44034[117:MRR:237.0,44033.0] || -> until2p7(s40)* node4(s39). % 76.04/76.22 44035[118:Spt:44034.0] || -> until2p7(s40)*. % 76.04/76.22 44036[118:MRR:238.0,44035.0] || -> until2p7(s41)* node4(s40). % 76.04/76.22 44037[119:Spt:44036.0] || -> until2p7(s41)*. % 76.04/76.22 44038[119:MRR:239.0,44037.0] || -> until2p7(s42)* node4(s41). % 76.04/76.22 44039[120:Spt:44038.0] || -> until2p7(s42)*. % 76.04/76.22 44040[120:MRR:240.0,44039.0] || -> until2p7(s43)* node4(s42). % 76.04/76.22 44041[121:Spt:44040.0] || -> until2p7(s43)*. % 76.04/76.22 44042[121:MRR:241.0,44041.0] || -> until2p7(s44)* node4(s43). % 76.04/76.22 44043[122:Spt:44042.0] || -> until2p7(s44)*. % 76.04/76.22 44044[122:MRR:539.0,44043.0] || -> until2p7(s45)* node4(s44). % 76.04/76.22 44045[123:Spt:44044.0] || -> until2p7(s45)*. % 76.04/76.22 44046[123:MRR:544.0,44045.0] || -> until2p7(s46)* node4(s45). % 76.04/76.22 44047[124:Spt:44046.0] || -> until2p7(s46)*. % 76.04/76.22 44048[124:MRR:549.0,44047.0] || -> until2p7(s47)* node4(s46). % 76.04/76.22 44049[125:Spt:44048.0] || -> until2p7(s47)*. % 76.04/76.22 44050[125:MRR:554.0,44049.0] || -> until2p7(s48)* node4(s47). % 76.04/76.22 44051[126:Spt:44050.0] || -> until2p7(s48)*. % 76.04/76.22 44052[126:MRR:559.0,44051.0] || -> until2p7(s49)* node4(s48). % 76.04/76.22 44053[127:Spt:44052.0] || -> until2p7(s49)*. % 76.04/76.22 44054[127:MRR:194.0,44053.0] || -> node4(s49)*. % 76.04/76.22 44055[127:MRR:43975.0,44054.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.22 44056[127:Res:53.1,44055.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.22 44058[127:MRR:44056.0,43985.0] || -> . % 76.04/76.22 44059[127:Spt:44058.0,44052.0,44053.0] || until2p7(s49)*+ -> . % 76.04/76.22 44060[127:Spt:44058.0,44052.1] || -> node4(s48)*. % 76.04/76.22 44061[127:MRR:43990.0,44060.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.22 44064[127:Res:53.1,44061.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.22 44066[127:MRR:44064.0,43806.0] || -> . % 76.04/76.22 44067[126:Spt:44066.0,44050.0,44051.0] || until2p7(s48)*+ -> . % 76.04/76.22 44068[126:Spt:44066.0,44050.1] || -> node4(s47)*. % 76.04/76.22 44069[126:MRR:43809.0,44068.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.22 44072[126:Res:53.1,44069.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.22 44076[126:Res:44072.0,61.1] always3(s47) || -> . % 76.04/76.22 44077[126:SSi:44076.0,736.0,43800.0,43812.0,44049.0,44068.0] || -> . % 76.04/76.22 44078[125:Spt:44077.0,44048.0,44049.0] || until2p7(s47)*+ -> . % 76.04/76.22 44079[125:Spt:44077.0,44048.1] || -> node4(s46)*. % 76.04/76.22 44081[125:MRR:780.0,44079.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.22 44097[125:Res:53.1,44081.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.22 44099[125:MRR:44097.0,43786.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.22 44104[125:Res:44099.0,61.1] always3(s47) || -> . % 76.04/76.22 44105[125:SSi:44104.0,736.0,43800.0,43812.0] || -> . % 76.04/76.22 44106[124:Spt:44105.0,44046.0,44047.0] || until2p7(s46)*+ -> . % 76.04/76.22 44107[124:Spt:44105.0,44046.1] || -> node4(s45)*. % 76.04/76.22 44108[124:MRR:43789.0,44107.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.22 44111[124:Res:53.1,44108.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.22 44115[124:Res:44111.0,61.1] always3(s45) || -> . % 76.04/76.22 44116[124:SSi:44115.0,734.0,43780.0,43795.0,44045.0,44107.0] || -> . % 76.04/76.22 44117[123:Spt:44116.0,44044.0,44045.0] || until2p7(s45)*+ -> . % 76.04/76.22 44118[123:Spt:44116.0,44044.1] || -> node4(s44)*. % 76.04/76.22 44120[123:MRR:786.0,44118.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.22 44131[123:Res:53.1,44120.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.22 44133[123:MRR:44131.0,43763.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.22 44135[123:Res:44133.0,61.1] always3(s45) || -> . % 76.04/76.22 44136[123:SSi:44135.0,734.0,43780.0,43795.0] || -> . % 76.04/76.22 44137[122:Spt:44136.0,44042.0,44043.0] || until2p7(s44)*+ -> . % 76.04/76.22 44138[122:Spt:44136.0,44042.1] || -> node4(s43)*. % 76.04/76.22 44139[122:MRR:43766.0,44138.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.22 44143[122:Res:53.1,44139.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.22 44146[122:Res:44143.0,61.1] always3(s43) || -> . % 76.04/76.22 44147[122:SSi:44146.0,732.0,43757.0,43769.0,44041.0,44138.0] || -> . % 76.04/76.22 44148[121:Spt:44147.0,44040.0,44041.0] || until2p7(s43)*+ -> . % 76.04/76.22 44149[121:Spt:44147.0,44040.1] || -> node4(s42)*. % 76.04/76.22 44151[121:MRR:792.0,44149.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.22 44162[121:Res:53.1,44151.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.22 44164[121:MRR:44162.0,43743.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.22 44166[121:Res:44164.0,61.1] always3(s43) || -> . % 76.04/76.22 44167[121:SSi:44166.0,732.0,43757.0,43769.0] || -> . % 76.04/76.22 44168[120:Spt:44167.0,44038.0,44039.0] || until2p7(s42)*+ -> . % 76.04/76.22 44169[120:Spt:44167.0,44038.1] || -> node4(s41)*. % 76.04/76.22 44170[120:MRR:43746.0,44169.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.22 44173[120:Res:53.1,44170.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.22 44176[120:Res:44173.0,61.1] always3(s41) || -> . % 76.04/76.22 44177[120:SSi:44176.0,730.0,43737.0,43749.0,44037.0,44169.0] || -> . % 76.04/76.22 44178[119:Spt:44177.0,44036.0,44037.0] || until2p7(s41)*+ -> . % 76.04/76.22 44179[119:Spt:44177.0,44036.1] || -> node4(s40)*. % 76.04/76.22 44181[119:MRR:798.0,44179.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.22 44193[119:Res:53.1,44181.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.22 44195[119:MRR:44193.0,43723.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.22 44197[119:Res:44195.0,61.1] always3(s41) || -> . % 76.04/76.22 44198[119:SSi:44197.0,730.0,43737.0,43749.0] || -> . % 76.04/76.22 44199[118:Spt:44198.0,44034.0,44035.0] || until2p7(s40)*+ -> . % 76.04/76.22 44200[118:Spt:44198.0,44034.1] || -> node4(s39)*. % 76.04/76.22 44201[118:MRR:43726.0,44200.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.22 44204[118:Res:53.1,44201.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.22 44207[118:Res:44204.0,61.1] always3(s39) || -> . % 76.04/76.22 44208[118:SSi:44207.0,728.0,43717.0,43732.0,44033.0,44200.0] || -> . % 76.04/76.22 44209[117:Spt:44208.0,44032.0,44033.0] || until2p7(s39)*+ -> . % 76.04/76.22 44210[117:Spt:44208.0,44032.1] || -> node4(s38)*. % 76.04/76.22 44212[117:MRR:804.0,44210.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.22 44224[117:Res:53.1,44212.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.22 44226[117:MRR:44224.0,43700.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.22 44231[117:Res:44226.0,61.1] always3(s39) || -> . % 76.04/76.22 44232[117:SSi:44231.0,728.0,43717.0,43732.0] || -> . % 76.04/76.22 44233[116:Spt:44232.0,44030.0,44031.0] || until2p7(s38)*+ -> . % 76.04/76.22 44234[116:Spt:44232.0,44030.1] || -> node4(s37)*. % 76.04/76.22 44235[116:MRR:43703.0,44234.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.22 44238[116:Res:53.1,44235.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.22 44242[116:Res:44238.0,61.1] always3(s37) || -> . % 76.04/76.22 44243[116:SSi:44242.0,726.0,43694.0,43706.0,44029.0,44234.0] || -> . % 76.04/76.22 44244[115:Spt:44243.0,44028.0,44029.0] || until2p7(s37)*+ -> . % 76.04/76.22 44245[115:Spt:44243.0,44028.1] || -> node4(s36)*. % 76.04/76.22 44247[115:MRR:810.0,44245.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.22 44258[115:Res:53.1,44247.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.22 44260[115:MRR:44258.0,43680.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.22 44262[115:Res:44260.0,61.1] always3(s37) || -> . % 76.04/76.22 44263[115:SSi:44262.0,726.0,43694.0,43706.0] || -> . % 76.04/76.22 44264[114:Spt:44263.0,44026.0,44027.0] || until2p7(s36)*+ -> . % 76.04/76.22 44265[114:Spt:44263.0,44026.1] || -> node4(s35)*. % 76.04/76.22 44266[114:MRR:43683.0,44265.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.22 44270[114:Res:53.1,44266.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.22 44273[114:Res:44270.0,61.1] always3(s35) || -> . % 76.04/76.22 44274[114:SSi:44273.0,724.0,43674.0,43686.0,44025.0,44265.0] || -> . % 76.04/76.22 44275[113:Spt:44274.0,44024.0,44025.0] || until2p7(s35)*+ -> . % 76.04/76.22 44276[113:Spt:44274.0,44024.1] || -> node4(s34)*. % 76.04/76.22 44278[113:MRR:816.0,44276.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.22 44289[113:Res:53.1,44278.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.22 44291[113:MRR:44289.0,43660.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.22 44293[113:Res:44291.0,61.1] always3(s35) || -> . % 76.04/76.22 44294[113:SSi:44293.0,724.0,43674.0,43686.0] || -> . % 76.04/76.22 44295[112:Spt:44294.0,44022.0,44023.0] || until2p7(s34)*+ -> . % 76.04/76.22 44296[112:Spt:44294.0,44022.1] || -> node4(s33)*. % 76.04/76.22 44297[112:MRR:43663.0,44296.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.22 44300[112:Res:53.1,44297.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.22 44303[112:Res:44300.0,61.1] always3(s33) || -> . % 76.04/76.22 44304[112:SSi:44303.0,722.0,43654.0,43669.0,44021.0,44296.0] || -> . % 76.04/76.22 44305[111:Spt:44304.0,44020.0,44021.0] || until2p7(s33)*+ -> . % 76.04/76.22 44306[111:Spt:44304.0,44020.1] || -> node4(s32)*. % 76.04/76.22 44308[111:MRR:822.0,44306.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.22 44320[111:Res:53.1,44308.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.22 44322[111:MRR:44320.0,43637.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.22 44324[111:Res:44322.0,61.1] always3(s33) || -> . % 76.04/76.22 44325[111:SSi:44324.0,722.0,43654.0,43669.0] || -> . % 76.04/76.22 44326[110:Spt:44325.0,44018.0,44019.0] || until2p7(s32)*+ -> . % 76.04/76.22 44327[110:Spt:44325.0,44018.1] || -> node4(s31)*. % 76.04/76.22 44328[110:MRR:43640.0,44327.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.04/76.22 44331[110:Res:53.1,44328.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.22 44334[110:Res:44331.0,61.1] always3(s31) || -> . % 76.04/76.22 44335[110:SSi:44334.0,720.0,43631.0,43643.0,44017.0,44327.0] || -> . % 76.04/76.22 44336[109:Spt:44335.0,44016.0,44017.0] || until2p7(s31)*+ -> . % 76.04/76.22 44337[109:Spt:44335.0,44016.1] || -> node4(s30)*. % 76.04/76.22 44339[109:MRR:828.0,44337.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.22 44351[109:Res:53.1,44339.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.22 44353[109:MRR:44351.0,43617.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.22 44358[109:Res:44353.0,61.1] always3(s31) || -> . % 76.04/76.22 44359[109:SSi:44358.0,720.0,43631.0,43643.0] || -> . % 76.04/76.22 44360[108:Spt:44359.0,44014.0,44015.0] || until2p7(s30)*+ -> . % 76.04/76.22 44361[108:Spt:44359.0,44014.1] || -> node4(s29)*. % 76.04/76.22 44362[108:MRR:43620.0,44361.0] || m_main_v_state(s29,c_ready)*+ -> . % 76.04/76.22 44365[108:Res:53.1,44362.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.22 44369[108:Res:44365.0,61.1] always3(s29) || -> . % 76.04/76.22 44370[108:SSi:44369.0,718.0,43608.0,43623.0,44013.0,44361.0] || -> . % 76.04/76.22 44371[107:Spt:44370.0,44012.0,44013.0] || until2p7(s29)*+ -> . % 76.04/76.22 44372[107:Spt:44370.0,44012.1] || -> node4(s28)*. % 76.04/76.22 44374[107:MRR:834.0,44372.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.22 44385[107:Res:53.1,44374.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.22 44387[108:Spt:44385.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.22 44389[108:Res:44387.0,61.1] always3(s28) || -> . % 76.04/76.22 44390[108:SSi:44389.0,717.0,43605.0,43607.0,44011.0,44372.0] || -> . % 76.04/76.22 44391[108:Spt:44390.0,44385.0,44387.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.22 44392[108:Spt:44390.0,44385.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.22 44396[108:Res:44392.0,61.1] always3(s29) || -> . % 76.04/76.22 44397[108:SSi:44396.0,718.0,43608.0,43623.0] || -> . % 76.04/76.22 44398[106:Spt:44397.0,44010.0,44011.0] || until2p7(s28)*+ -> . % 76.04/76.22 44399[106:Spt:44397.0,44010.1] || -> node4(s27)*. % 76.04/76.22 44401[106:MRR:837.0,44399.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.22 44408[106:Res:53.1,44401.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.22 44413[107:Spt:44408.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.22 44415[107:Res:44413.0,61.1] always3(s27) || -> . % 76.04/76.22 44416[107:SSi:44415.0,716.0,43599.0,43604.0,44009.0,44399.0] || -> . % 76.04/76.22 44417[107:Spt:44416.0,44408.0,44413.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.22 44418[107:Spt:44416.0,44408.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.22 44422[107:Res:44418.0,61.1] always3(s28) || -> . % 76.04/76.22 44423[107:SSi:44422.0,717.0,43605.0,43607.0] || -> . % 76.04/76.22 44424[105:Spt:44423.0,44008.0,44009.0] || until2p7(s27)*+ -> . % 76.04/76.22 44425[105:Spt:44423.0,44008.1] || -> node4(s26)*. % 76.04/76.22 44427[105:MRR:840.0,44425.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.22 44430[105:Res:53.1,44427.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.22 44432[106:Spt:44430.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.22 44434[106:Res:44432.0,61.1] always3(s26) || -> . % 76.04/76.22 44435[106:SSi:44434.0,715.0,43596.0,43598.0,44007.0,44425.0] || -> . % 76.04/76.22 44436[106:Spt:44435.0,44430.0,44432.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.22 44437[106:Spt:44435.0,44430.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.22 44441[106:Res:44437.0,61.1] always3(s27) || -> . % 76.04/76.22 44442[106:SSi:44441.0,716.0,43599.0,43604.0] || -> . % 76.04/76.22 44443[104:Spt:44442.0,44006.0,44007.0] || until2p7(s26)*+ -> . % 76.04/76.22 44444[104:Spt:44442.0,44006.1] || -> node4(s25)*. % 76.04/76.22 44446[104:MRR:843.0,44444.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.22 44449[104:Res:53.1,44446.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.22 44451[105:Spt:44449.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.22 44453[105:Res:44451.0,61.1] always3(s25) || -> . % 76.04/76.22 44454[105:SSi:44453.0,714.0,43590.0,43595.0,44005.0,44444.0] || -> . % 76.04/76.22 44455[105:Spt:44454.0,44449.0,44451.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.22 44456[105:Spt:44454.0,44449.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.22 44460[105:Res:44456.0,61.1] always3(s26) || -> . % 76.04/76.22 44461[105:SSi:44460.0,715.0,43596.0,43598.0] || -> . % 76.04/76.22 44462[103:Spt:44461.0,44004.0,44005.0] || until2p7(s25)*+ -> . % 76.04/76.22 44463[103:Spt:44461.0,44004.1] || -> node4(s24)*. % 76.04/76.22 44465[103:MRR:846.0,44463.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.22 44468[103:Res:53.1,44465.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.22 44470[104:Spt:44468.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.22 44472[104:Res:44470.0,61.1] always3(s24) || -> . % 76.04/76.22 44473[104:SSi:44472.0,713.0,43587.0,43589.0,44003.0,44463.0] || -> . % 76.04/76.22 44474[104:Spt:44473.0,44468.0,44470.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.22 44475[104:Spt:44473.0,44468.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.22 44479[104:Res:44475.0,61.1] always3(s25) || -> . % 76.04/76.22 44480[104:SSi:44479.0,714.0,43590.0,43595.0] || -> . % 76.04/76.22 44481[102:Spt:44480.0,44002.0,44003.0] || until2p7(s24)*+ -> . % 76.04/76.22 44482[102:Spt:44480.0,44002.1] || -> node4(s23)*. % 76.04/76.22 44484[102:MRR:849.0,44482.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.22 44487[102:Res:53.1,44484.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.22 44492[103:Spt:44487.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.22 44494[103:Res:44492.0,61.1] always3(s23) || -> . % 76.04/76.22 44495[103:SSi:44494.0,712.0,43581.0,43586.0,44001.0,44482.0] || -> . % 76.04/76.22 44496[103:Spt:44495.0,44487.0,44492.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.22 44497[103:Spt:44495.0,44487.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.22 44501[103:Res:44497.0,61.1] always3(s24) || -> . % 76.04/76.22 44502[103:SSi:44501.0,713.0,43587.0,43589.0] || -> . % 76.04/76.22 44503[101:Spt:44502.0,44000.0,44001.0] || until2p7(s23)*+ -> . % 76.04/76.22 44504[101:Spt:44502.0,44000.1] || -> node4(s22)*. % 76.04/76.22 44506[101:MRR:852.0,44504.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.22 44509[101:Res:53.1,44506.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.22 44511[102:Spt:44509.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.22 44513[102:Res:44511.0,61.1] always3(s22) || -> . % 76.04/76.22 44514[102:SSi:44513.0,711.0,43578.0,43580.0,43999.0,44504.0] || -> . % 76.04/76.22 44515[102:Spt:44514.0,44509.0,44511.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.22 44516[102:Spt:44514.0,44509.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.22 44520[102:Res:44516.0,61.1] always3(s23) || -> . % 76.04/76.22 44521[102:SSi:44520.0,712.0,43581.0,43586.0] || -> . % 76.04/76.22 44522[100:Spt:44521.0,43998.0,43999.0] || until2p7(s22)*+ -> . % 76.04/76.22 44523[100:Spt:44521.0,43998.1] || -> node4(s21)*. % 76.04/76.22 44525[100:MRR:855.0,44523.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.22 44528[100:Res:53.1,44525.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.22 44530[101:Spt:44528.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.22 44532[101:Res:44530.0,61.1] always3(s21) || -> . % 76.04/76.22 44533[101:SSi:44532.0,710.0,43572.0,43577.0,43997.0,44523.0] || -> . % 76.04/76.22 44534[101:Spt:44533.0,44528.0,44530.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.22 44535[101:Spt:44533.0,44528.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.22 44539[101:Res:44535.0,61.1] always3(s22) || -> . % 76.04/76.22 44540[101:SSi:44539.0,711.0,43578.0,43580.0] || -> . % 76.04/76.22 44541[99:Spt:44540.0,43996.0,43997.0] || until2p7(s21)*+ -> . % 76.04/76.22 44542[99:Spt:44540.0,43996.1] || -> node4(s20)*. % 76.04/76.22 44544[99:MRR:858.0,44542.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.22 44547[99:Res:53.1,44544.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.22 44549[100:Spt:44547.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.22 44551[100:Res:44549.0,61.1] always3(s20) || -> . % 76.04/76.22 44552[100:SSi:44551.0,709.0,43569.0,43571.0,43995.0,44542.0] || -> . % 76.04/76.22 44553[100:Spt:44552.0,44547.0,44549.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.22 44554[100:Spt:44552.0,44547.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.22 44558[100:Res:44554.0,61.1] always3(s21) || -> . % 76.04/76.22 44559[100:SSi:44558.0,710.0,43572.0,43577.0] || -> . % 76.04/76.22 44560[98:Spt:44559.0,43994.0,43995.0] || until2p7(s20)*+ -> . % 76.04/76.22 44561[98:Spt:44559.0,43994.1] || -> node4(s19)*. % 76.04/76.22 44563[98:MRR:861.0,44561.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.22 44566[98:Res:53.1,44563.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.22 44571[99:Spt:44566.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.22 44573[99:Res:44571.0,61.1] always3(s19) || -> . % 76.04/76.22 44574[99:SSi:44573.0,708.0,43563.0,43568.0,43993.0,44561.0] || -> . % 76.04/76.22 44575[99:Spt:44574.0,44566.0,44571.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.22 44576[99:Spt:44574.0,44566.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.22 44580[99:Res:44576.0,61.1] always3(s20) || -> . % 76.04/76.22 44581[99:SSi:44580.0,709.0,43569.0,43571.0] || -> . % 76.04/76.22 44582[97:Spt:44581.0,43992.0,43993.0] || until2p7(s19)*+ -> . % 76.04/76.22 44583[97:Spt:44581.0,43992.1] || -> node4(s18)*. % 76.04/76.22 44585[97:MRR:864.0,44583.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.22 44588[97:Res:53.1,44585.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.22 44590[98:Spt:44588.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.22 44592[98:Res:44590.0,61.1] always3(s18) || -> . % 76.04/76.22 44593[98:SSi:44592.0,707.0,43560.0,43562.0,43991.0,44583.0] || -> . % 76.04/76.22 44594[98:Spt:44593.0,44588.0,44590.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.22 44595[98:Spt:44593.0,44588.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.22 44599[98:Res:44595.0,61.1] always3(s19) || -> . % 76.04/76.22 44600[98:SSi:44599.0,708.0,43563.0,43568.0] || -> . % 76.04/76.22 44601[96:Spt:44600.0,43988.0,43991.0] || until2p7(s18)*+ -> . % 76.04/76.22 44602[96:Spt:44600.0,43988.1] || -> node4(s17)*. % 76.04/76.22 44604[96:MRR:867.0,44602.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.22 44607[96:Res:53.1,44604.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.22 44609[96:MRR:44607.0,43970.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.22 44611[96:Res:44609.0,61.1] always3(s18) || -> . % 76.04/76.22 44612[96:SSi:44611.0,707.0,43560.0,43562.0] || -> . % 76.04/76.22 44613[93:Spt:44612.0,43814.2,43819.0] || xuntil6(s48)*+ -> . % 76.04/76.22 44614[93:Spt:44612.0,43814.0,43814.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.22 44615[93:Res:53.1,44614.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.22 44617[93:MRR:44615.0,43806.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.22 44620[93:Res:44617.0,61.1] always3(s49) || -> . % 76.04/76.22 44621[93:SSi:44620.0,50.0,738.0] || -> . % 76.04/76.22 44622[92:Spt:44621.0,43810.1,43812.0] || xuntil6(s47)* -> . % 76.04/76.22 44623[92:Spt:44621.0,43810.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.22 44626[92:Res:44623.0,61.1] always3(s47) || -> . % 76.04/76.22 44627[92:SSi:44626.0,736.0,43800.0] || -> . % 76.04/76.22 44628[90:Spt:44627.0,43797.2,43799.0] || xuntil6(s46)*+ -> . % 76.04/76.22 44629[90:Spt:44627.0,43797.0,43797.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.22 44630[90:Res:53.1,44629.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.22 44632[90:MRR:44630.0,43786.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.22 44634[90:Res:44632.0,61.1] always3(s47) || -> . % 76.04/76.22 44635[90:SSi:44634.0,736.0] || -> . % 76.04/76.22 44636[89:Spt:44635.0,43790.1,43795.0] || xuntil6(s45)* -> . % 76.04/76.22 44637[89:Spt:44635.0,43790.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.22 44640[89:Res:44637.0,61.1] always3(s45) || -> . % 76.04/76.22 44641[89:SSi:44640.0,734.0,43780.0] || -> . % 76.04/76.22 44642[87:Spt:44641.0,43771.2,43779.0] || xuntil6(s44)*+ -> . % 76.04/76.22 44643[87:Spt:44641.0,43771.0,43771.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.22 44644[87:Res:53.1,44643.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.22 44646[87:MRR:44644.0,43763.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.22 44649[87:Res:44646.0,61.1] always3(s45) || -> . % 76.04/76.22 44650[87:SSi:44649.0,734.0] || -> . % 76.04/76.22 44651[86:Spt:44650.0,43767.1,43769.0] || xuntil6(s43)* -> . % 76.04/76.22 44652[86:Spt:44650.0,43767.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.22 44655[86:Res:44652.0,61.1] always3(s43) || -> . % 76.04/76.22 44656[86:SSi:44655.0,732.0,43757.0] || -> . % 76.04/76.22 44657[84:Spt:44656.0,43751.2,43756.0] || xuntil6(s42)*+ -> . % 76.04/76.22 44658[84:Spt:44656.0,43751.0,43751.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.22 44659[84:Res:53.1,44658.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.22 44661[84:MRR:44659.0,43743.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.22 44663[84:Res:44661.0,61.1] always3(s43) || -> . % 76.04/76.22 44664[84:SSi:44663.0,732.0] || -> . % 76.04/76.22 44665[83:Spt:44664.0,43747.1,43749.0] || xuntil6(s41)* -> . % 76.04/76.22 44666[83:Spt:44664.0,43747.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.22 44669[83:Res:44666.0,61.1] always3(s41) || -> . % 76.04/76.22 44670[83:SSi:44669.0,730.0,43737.0] || -> . % 76.04/76.22 44671[81:Spt:44670.0,43734.2,43736.0] || xuntil6(s40)*+ -> . % 76.04/76.22 44672[81:Spt:44670.0,43734.0,43734.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.22 44673[81:Res:53.1,44672.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.22 44675[81:MRR:44673.0,43723.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.22 44677[81:Res:44675.0,61.1] always3(s41) || -> . % 76.04/76.22 44678[81:SSi:44677.0,730.0] || -> . % 76.04/76.22 44679[80:Spt:44678.0,43727.1,43732.0] || xuntil6(s39)* -> . % 76.04/76.22 44680[80:Spt:44678.0,43727.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.22 44683[80:Res:44680.0,61.1] always3(s39) || -> . % 76.04/76.22 44684[80:SSi:44683.0,728.0,43717.0] || -> . % 76.04/76.22 44685[78:Spt:44684.0,43708.2,43716.0] || xuntil6(s38)*+ -> . % 76.04/76.22 44686[78:Spt:44684.0,43708.0,43708.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.22 44687[78:Res:53.1,44686.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.22 44689[78:MRR:44687.0,43700.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.22 44691[78:Res:44689.0,61.1] always3(s39) || -> . % 76.04/76.22 44692[78:SSi:44691.0,728.0] || -> . % 76.04/76.22 44693[77:Spt:44692.0,43704.1,43706.0] || xuntil6(s37)* -> . % 76.04/76.22 44694[77:Spt:44692.0,43704.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.22 44697[77:Res:44694.0,61.1] always3(s37) || -> . % 76.04/76.22 44698[77:SSi:44697.0,726.0,43694.0] || -> . % 76.04/76.22 44699[75:Spt:44698.0,43688.2,43693.0] || xuntil6(s36)*+ -> . % 76.04/76.22 44700[75:Spt:44698.0,43688.0,43688.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.22 44701[75:Res:53.1,44700.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.22 44703[75:MRR:44701.0,43680.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.22 44705[75:Res:44703.0,61.1] always3(s37) || -> . % 76.04/76.22 44706[75:SSi:44705.0,726.0] || -> . % 76.04/76.22 44707[74:Spt:44706.0,43684.1,43686.0] || xuntil6(s35)* -> . % 76.04/76.22 44708[74:Spt:44706.0,43684.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.22 44711[74:Res:44708.0,61.1] always3(s35) || -> . % 76.04/76.22 44712[74:SSi:44711.0,724.0,43674.0] || -> . % 76.04/76.22 44713[72:Spt:44712.0,43671.2,43673.0] || xuntil6(s34)*+ -> . % 76.04/76.22 44714[72:Spt:44712.0,43671.0,43671.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.22 44715[72:Res:53.1,44714.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.22 44717[72:MRR:44715.0,43660.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.22 44719[72:Res:44717.0,61.1] always3(s35) || -> . % 76.04/76.22 44720[72:SSi:44719.0,724.0] || -> . % 76.04/76.22 44721[71:Spt:44720.0,43664.1,43669.0] || xuntil6(s33)* -> . % 76.04/76.22 44722[71:Spt:44720.0,43664.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.22 44725[71:Res:44722.0,61.1] always3(s33) || -> . % 76.04/76.22 44726[71:SSi:44725.0,722.0,43654.0] || -> . % 76.04/76.22 44727[69:Spt:44726.0,43645.2,43653.0] || xuntil6(s32)*+ -> . % 76.04/76.22 44728[69:Spt:44726.0,43645.0,43645.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.22 44729[69:Res:53.1,44728.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.22 44731[69:MRR:44729.0,43637.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.22 44733[69:Res:44731.0,61.1] always3(s33) || -> . % 76.04/76.22 44734[69:SSi:44733.0,722.0] || -> . % 76.04/76.22 44735[68:Spt:44734.0,43641.1,43643.0] || xuntil6(s31)* -> . % 76.04/76.22 44736[68:Spt:44734.0,43641.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.22 44739[68:Res:44736.0,61.1] always3(s31) || -> . % 76.04/76.22 44740[68:SSi:44739.0,720.0,43631.0] || -> . % 76.04/76.22 44741[66:Spt:44740.0,43625.2,43630.0] || xuntil6(s30)*+ -> . % 76.04/76.22 44742[66:Spt:44740.0,43625.0,43625.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.22 44743[66:Res:53.1,44742.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.22 44745[66:MRR:44743.0,43617.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.22 44747[66:Res:44745.0,61.1] always3(s31) || -> . % 76.04/76.22 44748[66:SSi:44747.0,720.0] || -> . % 76.04/76.22 44749[65:Spt:44748.0,43621.1,43623.0] || xuntil6(s29)* -> . % 76.04/76.22 44750[65:Spt:44748.0,43621.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.22 44753[65:Res:44750.0,61.1] always3(s29) || -> . % 76.04/76.22 44754[65:SSi:44753.0,718.0,43608.0] || -> . % 76.04/76.22 44755[63:Spt:44754.0,43606.2,43607.0] || xuntil6(s28)*+ -> . % 76.04/76.22 44756[63:Spt:44754.0,43606.0,43606.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.22 44757[63:Res:53.1,44756.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.22 44759[64:Spt:44757.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.22 44761[64:Res:44759.0,61.1] always3(s29) || -> . % 76.04/76.22 44762[64:SSi:44761.0,718.0] || -> . % 76.04/76.22 44763[64:Spt:44762.0,44757.1,44759.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.22 44764[64:Spt:44762.0,44757.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.22 44767[64:Res:44764.0,61.1] always3(s28) || -> . % 76.04/76.22 44768[64:SSi:44767.0,717.0,43605.0] || -> . % 76.04/76.22 44769[62:Spt:44768.0,43600.2,43604.0] || xuntil6(s27)*+ -> . % 76.04/76.22 44770[62:Spt:44768.0,43600.0,43600.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.22 44771[62:Res:53.1,44770.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.22 44773[63:Spt:44771.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.22 44775[63:Res:44773.0,61.1] always3(s28) || -> . % 76.04/76.22 44776[63:SSi:44775.0,717.0] || -> . % 76.04/76.22 44777[63:Spt:44776.0,44771.1,44773.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.22 44778[63:Spt:44776.0,44771.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.22 44781[63:Res:44778.0,61.1] always3(s27) || -> . % 76.04/76.22 44782[63:SSi:44781.0,716.0,43599.0] || -> . % 76.04/76.22 44783[61:Spt:44782.0,43597.2,43598.0] || xuntil6(s26)*+ -> . % 76.04/76.22 44784[61:Spt:44782.0,43597.0,43597.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.22 44785[61:Res:53.1,44784.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.22 44787[62:Spt:44785.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.22 44789[62:Res:44787.0,61.1] always3(s27) || -> . % 76.04/76.22 44790[62:SSi:44789.0,716.0] || -> . % 76.04/76.22 44791[62:Spt:44790.0,44785.1,44787.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.22 44792[62:Spt:44790.0,44785.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.22 44795[62:Res:44792.0,61.1] always3(s26) || -> . % 76.04/76.22 44796[62:SSi:44795.0,715.0,43596.0] || -> . % 76.04/76.22 44797[60:Spt:44796.0,43591.2,43595.0] || xuntil6(s25)*+ -> . % 76.04/76.22 44798[60:Spt:44796.0,43591.0,43591.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.22 44799[60:Res:53.1,44798.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.22 44801[61:Spt:44799.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.22 44803[61:Res:44801.0,61.1] always3(s26) || -> . % 76.04/76.22 44804[61:SSi:44803.0,715.0] || -> . % 76.04/76.22 44805[61:Spt:44804.0,44799.1,44801.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.22 44806[61:Spt:44804.0,44799.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.22 44809[61:Res:44806.0,61.1] always3(s25) || -> . % 76.04/76.22 44810[61:SSi:44809.0,714.0,43590.0] || -> . % 76.04/76.22 44811[59:Spt:44810.0,43588.2,43589.0] || xuntil6(s24)*+ -> . % 76.04/76.22 44812[59:Spt:44810.0,43588.0,43588.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.22 44813[59:Res:53.1,44812.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.22 44815[60:Spt:44813.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.22 44817[60:Res:44815.0,61.1] always3(s25) || -> . % 76.04/76.22 44818[60:SSi:44817.0,714.0] || -> . % 76.04/76.22 44819[60:Spt:44818.0,44813.1,44815.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.22 44820[60:Spt:44818.0,44813.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.22 44823[60:Res:44820.0,61.1] always3(s24) || -> . % 76.04/76.22 44824[60:SSi:44823.0,713.0,43587.0] || -> . % 76.04/76.22 44825[58:Spt:44824.0,43582.2,43586.0] || xuntil6(s23)*+ -> . % 76.04/76.22 44826[58:Spt:44824.0,43582.0,43582.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.22 44827[58:Res:53.1,44826.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.22 44829[59:Spt:44827.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.22 44831[59:Res:44829.0,61.1] always3(s24) || -> . % 76.04/76.22 44832[59:SSi:44831.0,713.0] || -> . % 76.04/76.22 44833[59:Spt:44832.0,44827.1,44829.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.22 44834[59:Spt:44832.0,44827.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.22 44837[59:Res:44834.0,61.1] always3(s23) || -> . % 76.04/76.22 44838[59:SSi:44837.0,712.0,43581.0] || -> . % 76.04/76.22 44839[57:Spt:44838.0,43579.2,43580.0] || xuntil6(s22)*+ -> . % 76.04/76.22 44840[57:Spt:44838.0,43579.0,43579.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.22 44841[57:Res:53.1,44840.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.22 44843[58:Spt:44841.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.22 44845[58:Res:44843.0,61.1] always3(s23) || -> . % 76.04/76.22 44846[58:SSi:44845.0,712.0] || -> . % 76.04/76.22 44847[58:Spt:44846.0,44841.1,44843.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.22 44848[58:Spt:44846.0,44841.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.22 44851[58:Res:44848.0,61.1] always3(s22) || -> . % 76.04/76.22 44852[58:SSi:44851.0,711.0,43578.0] || -> . % 76.04/76.22 44853[56:Spt:44852.0,43573.2,43577.0] || xuntil6(s21)*+ -> . % 76.04/76.22 44854[56:Spt:44852.0,43573.0,43573.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.22 44855[56:Res:53.1,44854.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.22 44857[57:Spt:44855.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.22 44859[57:Res:44857.0,61.1] always3(s22) || -> . % 76.04/76.22 44860[57:SSi:44859.0,711.0] || -> . % 76.04/76.22 44861[57:Spt:44860.0,44855.1,44857.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.22 44862[57:Spt:44860.0,44855.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.22 44865[57:Res:44862.0,61.1] always3(s21) || -> . % 76.04/76.22 44866[57:SSi:44865.0,710.0,43572.0] || -> . % 76.04/76.22 44867[55:Spt:44866.0,43570.2,43571.0] || xuntil6(s20)*+ -> . % 76.04/76.22 44868[55:Spt:44866.0,43570.0,43570.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.22 44869[55:Res:53.1,44868.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.22 44874[56:Spt:44869.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.22 44876[56:Res:44874.0,61.1] always3(s20) || -> . % 76.04/76.22 44877[56:SSi:44876.0,709.0,43569.0] || -> . % 76.04/76.22 44878[56:Spt:44877.0,44869.0,44874.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.22 44879[56:Spt:44877.0,44869.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.22 44883[56:Res:44879.0,61.1] always3(s21) || -> . % 76.04/76.22 44884[56:SSi:44883.0,710.0] || -> . % 76.04/76.22 44885[54:Spt:44884.0,43564.2,43568.0] || xuntil6(s19)*+ -> . % 76.04/76.22 44886[54:Spt:44884.0,43564.0,43564.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.22 44887[54:Res:53.1,44886.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.22 44889[55:Spt:44887.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.22 44891[55:Res:44889.0,61.1] always3(s20) || -> . % 76.04/76.22 44892[55:SSi:44891.0,709.0] || -> . % 76.04/76.22 44893[55:Spt:44892.0,44887.1,44889.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.22 44894[55:Spt:44892.0,44887.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.22 44897[55:Res:44894.0,61.1] always3(s19) || -> . % 76.04/76.22 44898[55:SSi:44897.0,708.0,43563.0] || -> . % 76.04/76.22 44899[53:Spt:44898.0,43561.2,43562.0] || xuntil6(s18)*+ -> . % 76.04/76.22 44900[53:Spt:44898.0,43561.0,43561.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.22 44901[53:Res:53.1,44900.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.22 44903[54:Spt:44901.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.22 44905[54:Res:44903.0,61.1] always3(s19) || -> . % 76.04/76.22 44906[54:SSi:44905.0,708.0] || -> . % 76.04/76.22 44907[54:Spt:44906.0,44901.1,44903.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.22 44908[54:Spt:44906.0,44901.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.22 44911[54:Res:44908.0,61.1] always3(s18) || -> . % 76.04/76.22 44912[54:SSi:44911.0,707.0,43560.0] || -> . % 76.04/76.22 44913[52:Spt:44912.0,43555.2,43559.0] || xuntil6(s17)*+ -> . % 76.04/76.22 44914[52:Spt:44912.0,43555.0,43555.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.22 44915[52:Res:53.1,44914.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.22 44920[53:Spt:44915.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.22 44922[53:Res:44920.0,61.1] always3(s17) || -> . % 76.04/76.22 44923[53:SSi:44922.0,706.0,43554.0] || -> . % 76.04/76.22 44924[53:Spt:44923.0,44915.0,44920.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.22 44925[53:Spt:44923.0,44915.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.22 44932[53:Res:44925.0,61.1] always3(s18) || -> . % 76.04/76.22 44933[53:SSi:44932.0,707.0] || -> . % 76.04/76.22 44934[51:Spt:44933.0,43552.2,43553.0] || xuntil6(s16)*+ -> . % 76.04/76.22 44935[51:Spt:44933.0,43552.0,43552.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.22 44936[51:Res:53.1,44935.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.22 44938[52:Spt:44936.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.22 44940[52:Res:44938.0,61.1] always3(s16) || -> . % 76.04/76.22 44941[52:SSi:44940.0,705.0,43551.0] || -> . % 76.04/76.22 44942[52:Spt:44941.0,44936.0,44938.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.22 44943[52:Spt:44941.0,44936.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.22 44947[52:Res:44943.0,61.1] always3(s17) || -> . % 76.04/76.22 44948[52:SSi:44947.0,706.0] || -> . % 76.04/76.22 44949[50:Spt:44948.0,43546.2,43550.0] || xuntil6(s15)*+ -> . % 76.04/76.22 44950[50:Spt:44948.0,43546.0,43546.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.22 44951[50:Res:53.1,44950.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.22 44953[51:Spt:44951.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.22 44955[51:Res:44953.0,61.1] always3(s15) || -> . % 76.04/76.22 44956[51:SSi:44955.0,704.0,43545.0] || -> . % 76.04/76.22 44957[51:Spt:44956.0,44951.0,44953.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.22 44958[51:Spt:44956.0,44951.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.22 44962[51:Res:44958.0,61.1] always3(s16) || -> . % 76.04/76.22 44963[51:SSi:44962.0,705.0] || -> . % 76.04/76.22 44964[49:Spt:44963.0,43543.2,43544.0] || xuntil6(s14)*+ -> . % 76.04/76.22 44965[49:Spt:44963.0,43543.0,43543.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.22 44966[49:Res:53.1,44965.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.22 44971[50:Spt:44966.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.22 44973[50:Res:44971.0,61.1] always3(s14) || -> . % 76.04/76.22 44974[50:SSi:44973.0,703.0,43542.0] || -> . % 76.04/76.22 44975[50:Spt:44974.0,44966.0,44971.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.22 44976[50:Spt:44974.0,44966.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.22 44980[50:Res:44976.0,61.1] always3(s15) || -> . % 76.04/76.22 44981[50:SSi:44980.0,704.0] || -> . % 76.04/76.22 44982[48:Spt:44981.0,43537.2,43541.0] || xuntil6(s13)*+ -> . % 76.04/76.22 44983[48:Spt:44981.0,43537.0,43537.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.22 44984[48:Res:53.1,44983.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.22 44986[49:Spt:44984.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.22 44988[49:Res:44986.0,61.1] always3(s13) || -> . % 76.04/76.22 44989[49:SSi:44988.0,702.0,43536.0] || -> . % 76.04/76.22 44990[49:Spt:44989.0,44984.0,44986.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.22 44991[49:Spt:44989.0,44984.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.22 44995[49:Res:44991.0,61.1] always3(s14) || -> . % 76.04/76.22 44996[49:SSi:44995.0,703.0] || -> . % 76.04/76.22 44997[47:Spt:44996.0,43534.2,43535.0] || xuntil6(s12)*+ -> . % 76.04/76.22 44998[47:Spt:44996.0,43534.0,43534.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.22 44999[47:Res:53.1,44998.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.22 45001[48:Spt:44999.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.22 45003[48:Res:45001.0,61.1] always3(s12) || -> . % 76.04/76.22 45004[48:SSi:45003.0,701.0,43533.0] || -> . % 76.04/76.22 45005[48:Spt:45004.0,44999.0,45001.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.22 45006[48:Spt:45004.0,44999.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.22 45010[48:Res:45006.0,61.1] always3(s13) || -> . % 76.04/76.22 45011[48:SSi:45010.0,702.0] || -> . % 76.04/76.22 45012[46:Spt:45011.0,43528.2,43532.0] || xuntil6(s11)*+ -> . % 76.04/76.22 45013[46:Spt:45011.0,43528.0,43528.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.22 45014[46:Res:53.1,45013.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.22 45019[47:Spt:45014.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.22 45021[47:Res:45019.0,61.1] always3(s11) || -> . % 76.04/76.22 45022[47:SSi:45021.0,700.0,43527.0] || -> . % 76.04/76.22 45023[47:Spt:45022.0,45014.0,45019.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.22 45024[47:Spt:45022.0,45014.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.22 45028[47:Res:45024.0,61.1] always3(s12) || -> . % 76.04/76.22 45029[47:SSi:45028.0,701.0] || -> . % 76.04/76.22 45030[45:Spt:45029.0,43525.2,43526.0] || xuntil6(s10)*+ -> . % 76.04/76.22 45031[45:Spt:45029.0,43525.0,43525.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.22 45032[45:Res:53.1,45031.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.22 45034[46:Spt:45032.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.22 45036[46:Res:45034.0,61.1] always3(s10) || -> . % 76.04/76.22 45037[46:SSi:45036.0,699.0,43524.0] || -> . % 76.04/76.22 45038[46:Spt:45037.0,45032.0,45034.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.22 45039[46:Spt:45037.0,45032.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.22 45043[46:Res:45039.0,61.1] always3(s11) || -> . % 76.04/76.22 45044[46:SSi:45043.0,700.0] || -> . % 76.04/76.22 45045[44:Spt:45044.0,43519.2,43523.0] || xuntil6(s9)*+ -> . % 76.04/76.22 45046[44:Spt:45044.0,43519.0,43519.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.22 45047[44:Res:53.1,45046.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.22 45049[45:Spt:45047.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.22 45051[45:Res:45049.0,61.1] always3(s9) || -> . % 76.04/76.22 45052[45:SSi:45051.0,698.0,43518.0] || -> . % 76.04/76.22 45053[45:Spt:45052.0,45047.0,45049.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.22 45054[45:Spt:45052.0,45047.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.22 45058[45:Res:45054.0,61.1] always3(s10) || -> . % 76.04/76.22 45059[45:SSi:45058.0,699.0] || -> . % 76.04/76.22 45060[43:Spt:45059.0,43516.2,43517.0] || xuntil6(s8)*+ -> . % 76.04/76.22 45061[43:Spt:45059.0,43516.0,43516.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.22 45062[43:Res:53.1,45061.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.22 45067[44:Spt:45062.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.22 45069[44:Res:45067.0,61.1] always3(s8) || -> . % 76.04/76.22 45070[44:SSi:45069.0,697.0,43515.0] || -> . % 76.04/76.22 45071[44:Spt:45070.0,45062.0,45067.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.22 45072[44:Spt:45070.0,45062.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.22 45076[44:Res:45072.0,61.1] always3(s9) || -> . % 76.04/76.22 45077[44:SSi:45076.0,698.0] || -> . % 76.04/76.22 45078[42:Spt:45077.0,43510.2,43514.0] || xuntil6(s7)*+ -> . % 76.04/76.22 45079[42:Spt:45077.0,43510.0,43510.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.22 45080[42:Res:53.1,45079.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.22 45082[43:Spt:45080.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.22 45084[43:Res:45082.0,61.1] always3(s7) || -> . % 76.04/76.22 45085[43:SSi:45084.0,696.0,43509.0] || -> . % 76.04/76.22 45086[43:Spt:45085.0,45080.0,45082.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.22 45087[43:Spt:45085.0,45080.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.22 45091[43:Res:45087.0,61.1] always3(s8) || -> . % 76.04/76.22 45092[43:SSi:45091.0,697.0] || -> . % 76.04/76.22 45093[41:Spt:45092.0,43507.2,43508.0] || xuntil6(s6)*+ -> . % 76.04/76.22 45094[41:Spt:45092.0,43507.0,43507.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.22 45095[41:Res:53.1,45094.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.22 45097[42:Spt:45095.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.22 45099[42:Res:45097.0,61.1] always3(s6) || -> . % 76.04/76.22 45100[42:SSi:45099.0,695.0,43506.0] || -> . % 76.04/76.22 45101[42:Spt:45100.0,45095.0,45097.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.22 45102[42:Spt:45100.0,45095.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.22 45106[42:Res:45102.0,61.1] always3(s7) || -> . % 76.04/76.22 45107[42:SSi:45106.0,696.0] || -> . % 76.04/76.22 45108[40:Spt:45107.0,43501.2,43505.0] || xuntil6(s5)*+ -> . % 76.04/76.22 45109[40:Spt:45107.0,43501.0,43501.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.22 45110[40:Res:53.1,45109.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.22 45115[41:Spt:45110.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.22 45117[41:Res:45115.0,61.1] always3(s5) || -> . % 76.04/76.22 45118[41:SSi:45117.0,694.0,43500.0] || -> . % 76.04/76.22 45119[41:Spt:45118.0,45110.0,45115.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.22 45120[41:Spt:45118.0,45110.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.22 45124[41:Res:45120.0,61.1] always3(s6) || -> . % 76.04/76.22 45125[41:SSi:45124.0,695.0] || -> . % 76.04/76.22 45126[39:Spt:45125.0,43498.2,43499.0] || xuntil6(s4)*+ -> . % 76.04/76.22 45127[39:Spt:45125.0,43498.0,43498.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.22 45128[39:Res:53.1,45127.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.22 45130[40:Spt:45128.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.22 45132[40:Res:45130.0,61.1] always3(s4) || -> . % 76.04/76.22 45133[40:SSi:45132.0,693.0,43497.0] || -> . % 76.04/76.22 45134[40:Spt:45133.0,45128.0,45130.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.22 45135[40:Spt:45133.0,45128.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.22 45139[40:Res:45135.0,61.1] always3(s5) || -> . % 76.04/76.22 45140[40:SSi:45139.0,694.0] || -> . % 76.04/76.22 45141[38:Spt:45140.0,43492.2,43496.0] || xuntil6(s3)*+ -> . % 76.04/76.22 45142[38:Spt:45140.0,43492.0,43492.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.22 45143[38:Res:53.1,45142.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.22 45145[39:Spt:45143.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.22 45147[39:Res:45145.0,61.1] always3(s3) || -> . % 76.04/76.22 45148[39:SSi:45147.0,692.0,43491.0] || -> . % 76.04/76.22 45149[39:Spt:45148.0,45143.0,45145.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.22 45150[39:Spt:45148.0,45143.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.22 45154[39:Res:45150.0,61.1] always3(s4) || -> . % 76.04/76.22 45155[39:SSi:45154.0,693.0] || -> . % 76.04/76.22 45156[37:Spt:45155.0,43489.2,43490.0] || xuntil6(s2)*+ -> . % 76.04/76.22 45157[37:Spt:45155.0,43489.0,43489.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.22 45158[37:Res:53.1,45157.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.22 45163[38:Spt:45158.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.22 45165[38:Res:45163.0,61.1] always3(s2) || -> . % 76.04/76.22 45166[38:SSi:45165.0,691.0,43488.0] || -> . % 76.04/76.22 45167[38:Spt:45166.0,45158.0,45163.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.22 45168[38:Spt:45166.0,45158.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.22 45172[38:Res:45168.0,61.1] always3(s3) || -> . % 76.04/76.22 45173[38:SSi:45172.0,692.0] || -> . % 76.04/76.22 45174[36:Spt:45173.0,43480.2,43487.0] || xuntil6(s1)*+ -> . % 76.04/76.22 45175[36:Spt:45173.0,43480.0,43480.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.22 45176[36:Res:53.1,45175.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.22 45178[37:Spt:45176.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.22 45180[37:Res:45178.0,61.1] always3(s1) || -> . % 76.04/76.22 45181[37:SSi:45180.0,690.0,43479.0] || -> . % 76.04/76.22 45182[37:Spt:45181.0,45176.0,45178.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.22 45183[37:Spt:45181.0,45176.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.22 45188[37:Res:45183.0,61.1] always3(s2) || -> . % 76.04/76.22 45189[37:SSi:45188.0,691.0] || -> . % 76.04/76.22 45190[35:Spt:45189.0,74.0,43478.0] || xuntil6(s0)*+ -> . % 76.04/76.22 45191[35:Spt:45189.0,74.1] || -> node4(s0)*. % 76.04/76.22 45192[35:MRR:758.1,45190.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.22 45194[35:Res:45192.0,61.1] always3(s1) || -> . % 76.04/76.22 45195[35:SSi:45194.0,690.0] || -> . % 76.04/76.22 45196[34:Spt:45195.0,43468.0,43472.0] || trans(s49,s17)*+ -> . % 76.04/76.22 45197[34:Spt:45195.0,43468.1,43468.2,43468.3,43468.4,43468.5,43468.6,43468.7,43468.8,43468.9,43468.10,43468.11,43468.12,43468.13,43468.14,43468.15,43468.16,43468.17] || -> trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.22 45198[34:MRR:43470.0,45196.0] || -> trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.22 45200[34:MRR:43471.1,45196.0] xuntil6(s49) || -> trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.22 45201[35:Spt:45197.0] || -> trans(s49,s16)*. % 76.04/76.22 45202[35:Res:45201.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s16)*. % 76.04/76.22 45204[35:Res:45201.0,60.0] || -> node2(s49,s16)*. % 76.04/76.22 45205[35:SSi:45202.1,50.0,738.0] xuntil6(s49) || -> until2p7(s16)*. % 76.04/76.22 45206[35:Res:45204.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)*. % 76.04/76.22 45207[36:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.22 45208[36:MRR:176.0,45207.0] || -> until5(s1)*. % 76.04/76.22 45209[36:MRR:43923.0,45208.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.22 45216[37:Spt:45209.2] || -> xuntil6(s1)*. % 76.04/76.22 45217[37:MRR:175.0,45216.0] || -> until5(s2)*. % 76.04/76.22 45218[37:MRR:43916.0,45217.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.22 45219[38:Spt:45218.2] || -> xuntil6(s2)*. % 76.04/76.22 45220[38:MRR:174.0,45219.0] || -> until5(s3)*. % 76.04/76.22 45221[38:MRR:43912.0,45220.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.22 45225[39:Spt:45221.2] || -> xuntil6(s3)*. % 76.04/76.22 45226[39:MRR:173.0,45225.0] || -> until5(s4)*. % 76.04/76.22 45227[39:MRR:43908.0,45226.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.22 45228[40:Spt:45227.2] || -> xuntil6(s4)*. % 76.04/76.22 45229[40:MRR:172.0,45228.0] || -> until5(s5)*. % 76.04/76.22 45230[40:MRR:43904.0,45229.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.22 45234[41:Spt:45230.2] || -> xuntil6(s5)*. % 76.04/76.22 45235[41:MRR:171.0,45234.0] || -> until5(s6)*. % 76.04/76.22 45236[41:MRR:43903.0,45235.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.22 45237[42:Spt:45236.2] || -> xuntil6(s6)*. % 76.04/76.22 45238[42:MRR:170.0,45237.0] || -> until5(s7)*. % 76.04/76.22 45239[42:MRR:43896.0,45238.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.22 45243[43:Spt:45239.2] || -> xuntil6(s7)*. % 76.04/76.22 45244[43:MRR:169.0,45243.0] || -> until5(s8)*. % 76.04/76.22 45245[43:MRR:43892.0,45244.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.22 45246[44:Spt:45245.2] || -> xuntil6(s8)*. % 76.04/76.22 45247[44:MRR:168.0,45246.0] || -> until5(s9)*. % 76.04/76.22 45248[44:MRR:43888.0,45247.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.22 45252[45:Spt:45248.2] || -> xuntil6(s9)*. % 76.04/76.22 45253[45:MRR:167.0,45252.0] || -> until5(s10)*. % 76.04/76.22 45254[45:MRR:43884.0,45253.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.22 45255[46:Spt:45254.2] || -> xuntil6(s10)*. % 76.04/76.22 45256[46:MRR:166.0,45255.0] || -> until5(s11)*. % 76.04/76.22 45257[46:MRR:43883.0,45256.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.22 45261[47:Spt:45257.2] || -> xuntil6(s11)*. % 76.04/76.22 45262[47:MRR:165.0,45261.0] || -> until5(s12)*. % 76.04/76.22 45263[47:MRR:43876.0,45262.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.22 45264[48:Spt:45263.2] || -> xuntil6(s12)*. % 76.04/76.22 45265[48:MRR:164.0,45264.0] || -> until5(s13)*. % 76.04/76.22 45266[48:MRR:43872.0,45265.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.22 45270[49:Spt:45266.2] || -> xuntil6(s13)*. % 76.04/76.22 45271[49:MRR:163.0,45270.0] || -> until5(s14)*. % 76.04/76.22 45272[49:MRR:43868.0,45271.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.22 45273[50:Spt:45272.2] || -> xuntil6(s14)*. % 76.04/76.22 45274[50:MRR:162.0,45273.0] || -> until5(s15)*. % 76.04/76.22 45275[50:MRR:43864.0,45274.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.22 45279[51:Spt:45275.2] || -> xuntil6(s15)*. % 76.04/76.22 45280[51:MRR:161.0,45279.0] || -> until5(s16)*. % 76.04/76.22 45281[51:MRR:43863.0,45280.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.22 45282[52:Spt:45281.2] || -> xuntil6(s16)*. % 76.04/76.22 45283[52:MRR:160.0,45282.0] || -> until5(s17)*. % 76.04/76.22 45284[52:MRR:43856.0,45283.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.22 45288[53:Spt:45284.2] || -> xuntil6(s17)*. % 76.04/76.22 45289[53:MRR:159.0,45288.0] || -> until5(s18)*. % 76.04/76.22 45290[53:MRR:43852.0,45289.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.22 45291[54:Spt:45290.2] || -> xuntil6(s18)*. % 76.04/76.22 45292[54:MRR:158.0,45291.0] || -> until5(s19)*. % 76.04/76.22 45293[54:MRR:43845.0,45292.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.22 45297[55:Spt:45293.2] || -> xuntil6(s19)*. % 76.04/76.22 45298[55:MRR:157.0,45297.0] || -> until5(s20)*. % 76.04/76.22 45299[55:MRR:43841.0,45298.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.22 45300[56:Spt:45299.2] || -> xuntil6(s20)*. % 76.04/76.22 45301[56:MRR:156.0,45300.0] || -> until5(s21)*. % 76.04/76.22 45302[56:MRR:43837.0,45301.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.22 45306[57:Spt:45302.2] || -> xuntil6(s21)*. % 76.04/76.22 45307[57:MRR:155.0,45306.0] || -> until5(s22)*. % 76.04/76.22 45308[57:MRR:43833.0,45307.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.22 45309[58:Spt:45308.2] || -> xuntil6(s22)*. % 76.04/76.22 45310[58:MRR:154.0,45309.0] || -> until5(s23)*. % 76.04/76.22 45311[58:MRR:43832.0,45310.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.22 45315[59:Spt:45311.2] || -> xuntil6(s23)*. % 76.04/76.22 45316[59:MRR:153.0,45315.0] || -> until5(s24)*. % 76.04/76.22 45317[59:MRR:43828.0,45316.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.22 45318[60:Spt:45317.2] || -> xuntil6(s24)*. % 76.04/76.22 45319[60:MRR:152.0,45318.0] || -> until5(s25)*. % 76.04/76.22 45320[60:MRR:43827.0,45319.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.22 45324[61:Spt:45320.2] || -> xuntil6(s25)*. % 76.04/76.22 45325[61:MRR:151.0,45324.0] || -> until5(s26)*. % 76.04/76.22 45326[61:MRR:43826.0,45325.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.22 45327[62:Spt:45326.2] || -> xuntil6(s26)*. % 76.04/76.22 45328[62:MRR:150.0,45327.0] || -> until5(s27)*. % 76.04/76.22 45329[62:MRR:43825.0,45328.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.22 45333[63:Spt:45329.2] || -> xuntil6(s27)*. % 76.04/76.22 45334[63:MRR:149.0,45333.0] || -> until5(s28)*. % 76.04/76.22 45335[63:MRR:43821.0,45334.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.22 45336[64:Spt:45335.2] || -> xuntil6(s28)*. % 76.04/76.22 45337[64:MRR:148.0,45336.0] || -> until5(s29)*. % 76.04/76.22 45338[64:MRR:35647.0,45337.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.22 45342[65:Spt:45338.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.22 45344[65:Res:45342.0,61.1] always3(s30) || -> . % 76.04/76.22 45345[65:SSi:45344.0,719.0] || -> . % 76.04/76.22 45346[65:Spt:45345.0,45338.1,45342.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.04/76.22 45347[65:Spt:45345.0,45338.0,45338.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 76.04/76.22 45349[65:MRR:831.2,45346.0] node4(s29) || m_main_v_state(s29,c_ready)* -> . % 76.04/76.22 45350[65:Res:53.1,45347.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 76.04/76.22 45352[66:Spt:45350.1] || -> xuntil6(s29)*. % 76.04/76.22 45353[66:MRR:147.0,45352.0] || -> until5(s30)*. % 76.04/76.22 45354[66:MRR:43927.0,45353.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.22 45359[67:Spt:45354.2] || -> xuntil6(s30)*. % 76.04/76.22 45360[67:MRR:146.0,45359.0] || -> until5(s31)*. % 76.04/76.22 45361[67:MRR:35651.0,45360.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.22 45362[68:Spt:45361.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.22 45364[68:Res:45362.0,61.1] always3(s32) || -> . % 76.04/76.22 45365[68:SSi:45364.0,721.0] || -> . % 76.04/76.22 45366[68:Spt:45365.0,45361.1,45362.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.04/76.22 45367[68:Spt:45365.0,45361.0,45361.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.04/76.22 45369[68:MRR:825.2,45366.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.04/76.22 45370[68:Res:53.1,45367.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.04/76.22 45372[69:Spt:45370.1] || -> xuntil6(s31)*. % 76.04/76.22 45373[69:MRR:145.0,45372.0] || -> until5(s32)*. % 76.04/76.22 45374[69:MRR:43934.0,45373.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.22 45382[70:Spt:45374.2] || -> xuntil6(s32)*. % 76.04/76.22 45383[70:MRR:144.0,45382.0] || -> until5(s33)*. % 76.04/76.22 45384[70:MRR:35655.0,45383.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.22 45385[71:Spt:45384.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.22 45387[71:Res:45385.0,61.1] always3(s34) || -> . % 76.04/76.22 45388[71:SSi:45387.0,723.0] || -> . % 76.04/76.22 45389[71:Spt:45388.0,45384.1,45385.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.22 45390[71:Spt:45388.0,45384.0,45384.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.22 45392[71:MRR:819.2,45389.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.22 45393[71:Res:53.1,45390.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.22 45398[72:Spt:45393.1] || -> xuntil6(s33)*. % 76.04/76.22 45399[72:MRR:143.0,45398.0] || -> until5(s34)*. % 76.04/76.22 45400[72:MRR:43935.0,45399.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.22 45402[73:Spt:45400.2] || -> xuntil6(s34)*. % 76.04/76.22 45403[73:MRR:142.0,45402.0] || -> until5(s35)*. % 76.04/76.22 45404[73:MRR:35659.0,45403.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.22 45405[74:Spt:45404.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.22 45407[74:Res:45405.0,61.1] always3(s36) || -> . % 76.04/76.22 45408[74:SSi:45407.0,725.0] || -> . % 76.04/76.22 45409[74:Spt:45408.0,45404.1,45405.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.22 45410[74:Spt:45408.0,45404.0,45404.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.22 45412[74:MRR:813.2,45409.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.22 45413[74:Res:53.1,45410.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.22 45415[75:Spt:45413.1] || -> xuntil6(s35)*. % 76.04/76.22 45416[75:MRR:141.0,45415.0] || -> until5(s36)*. % 76.04/76.22 45417[75:MRR:43939.0,45416.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.22 45422[76:Spt:45417.2] || -> xuntil6(s36)*. % 76.04/76.22 45423[76:MRR:140.0,45422.0] || -> until5(s37)*. % 76.04/76.22 45424[76:MRR:35666.0,45423.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.22 45425[77:Spt:45424.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.22 45427[77:Res:45425.0,61.1] always3(s38) || -> . % 76.04/76.22 45428[77:SSi:45427.0,727.0] || -> . % 76.04/76.22 45429[77:Spt:45428.0,45424.1,45425.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.22 45430[77:Spt:45428.0,45424.0,45424.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.22 45432[77:MRR:807.2,45429.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.22 45433[77:Res:53.1,45430.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.22 45435[78:Spt:45433.1] || -> xuntil6(s37)*. % 76.04/76.22 45436[78:MRR:139.0,45435.0] || -> until5(s38)*. % 76.04/76.22 45437[78:MRR:43943.0,45436.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.22 45445[79:Spt:45437.2] || -> xuntil6(s38)*. % 76.04/76.22 45446[79:MRR:138.0,45445.0] || -> until5(s39)*. % 76.04/76.22 45447[79:MRR:35667.0,45446.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.22 45448[80:Spt:45447.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.22 45450[80:Res:45448.0,61.1] always3(s40) || -> . % 76.04/76.22 45451[80:SSi:45450.0,729.0] || -> . % 76.04/76.22 45452[80:Spt:45451.0,45447.1,45448.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.22 45453[80:Spt:45451.0,45447.0,45447.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.22 45455[80:MRR:801.2,45452.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.22 45456[80:Res:53.1,45453.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.22 45461[81:Spt:45456.1] || -> xuntil6(s39)*. % 76.04/76.22 45462[81:MRR:137.0,45461.0] || -> until5(s40)*. % 76.04/76.22 45463[81:MRR:43947.0,45462.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.22 45465[82:Spt:45463.2] || -> xuntil6(s40)*. % 76.04/76.22 45466[82:MRR:136.0,45465.0] || -> until5(s41)*. % 76.04/76.22 45467[82:MRR:35671.0,45466.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.22 45468[83:Spt:45467.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.22 45470[83:Res:45468.0,61.1] always3(s42) || -> . % 76.04/76.22 45471[83:SSi:45470.0,731.0] || -> . % 76.04/76.22 45472[83:Spt:45471.0,45467.1,45468.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.22 45473[83:Spt:45471.0,45467.0,45467.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.22 45475[83:MRR:795.2,45472.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.22 45476[83:Res:53.1,45473.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.22 45478[84:Spt:45476.1] || -> xuntil6(s41)*. % 76.04/76.22 45479[84:MRR:135.0,45478.0] || -> until5(s42)*. % 76.04/76.22 45480[84:MRR:43954.0,45479.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.22 45485[85:Spt:45480.2] || -> xuntil6(s42)*. % 76.04/76.22 45486[85:MRR:134.0,45485.0] || -> until5(s43)*. % 76.04/76.22 45487[85:MRR:35675.0,45486.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.22 45488[86:Spt:45487.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.22 45490[86:Res:45488.0,61.1] always3(s44) || -> . % 76.04/76.22 45491[86:SSi:45490.0,733.0] || -> . % 76.04/76.22 45492[86:Spt:45491.0,45487.1,45488.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.22 45493[86:Spt:45491.0,45487.0,45487.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.22 45495[86:MRR:789.2,45492.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.22 45496[86:Res:53.1,45493.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.22 45498[87:Spt:45496.1] || -> xuntil6(s43)*. % 76.04/76.22 45499[87:MRR:133.0,45498.0] || -> until5(s44)*. % 76.04/76.22 45500[87:MRR:43955.0,45499.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.22 45508[88:Spt:45500.2] || -> xuntil6(s44)*. % 76.04/76.22 45509[88:MRR:132.0,45508.0] || -> until5(s45)*. % 76.04/76.22 45510[88:MRR:35679.0,45509.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.22 45511[89:Spt:45510.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.22 45513[89:Res:45511.0,61.1] always3(s46) || -> . % 76.04/76.22 45514[89:SSi:45513.0,735.0] || -> . % 76.04/76.22 45515[89:Spt:45514.0,45510.1,45511.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.22 45516[89:Spt:45514.0,45510.0,45510.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.22 45518[89:MRR:783.2,45515.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.22 45519[89:Res:53.1,45516.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.22 45524[90:Spt:45519.1] || -> xuntil6(s45)*. % 76.04/76.22 45525[90:MRR:131.0,45524.0] || -> until5(s46)*. % 76.04/76.22 45526[90:MRR:43959.0,45525.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.22 45528[91:Spt:45526.2] || -> xuntil6(s46)*. % 76.04/76.22 45529[91:MRR:130.0,45528.0] || -> until5(s47)*. % 76.04/76.22 45530[91:MRR:35683.0,45529.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.23 45531[92:Spt:45530.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.23 45533[92:Res:45531.0,61.1] always3(s48) || -> . % 76.04/76.23 45534[92:SSi:45533.0,737.0] || -> . % 76.04/76.23 45535[92:Spt:45534.0,45530.1,45531.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.23 45536[92:Spt:45534.0,45530.0,45530.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.23 45538[92:MRR:777.2,45535.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.23 45539[92:Res:53.1,45536.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.23 45541[93:Spt:45539.1] || -> xuntil6(s47)*. % 76.04/76.23 45542[93:MRR:129.0,45541.0] || -> until5(s48)*. % 76.04/76.23 45543[93:MRR:43963.0,45542.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.23 45548[94:Spt:45543.2] || -> xuntil6(s48)*. % 76.04/76.23 45549[94:MRR:128.0,45548.0] || -> until5(s49)*. % 76.04/76.23 45550[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.23 45554[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.23 45555[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.23 45556[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.23 45557[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.23 45561[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.23 45565[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.23 45572[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.23 45573[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.23 45583[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.23 45584[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.23 45585[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.23 45592[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.23 45596[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.23 45603[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.23 45604[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.23 45608[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.23 45612[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.23 45616[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.23 45623[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.23 45624[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.23 45628[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.23 45632[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.23 45636[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.23 45643[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.23 45644[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.23 45648[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.23 45652[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.23 45654[35:SoR:45206.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)*. % 76.04/76.23 45659[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.23 45663[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.23 45667[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.23 45674[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.23 45675[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.23 45679[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.23 45683[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.23 45687[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.23 45694[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.23 45695[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.23 45696[35:SoR:45654.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)* xuntil6(s49). % 76.04/76.23 45697[94:SSi:45696.0,50.0,738.0,45549.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s16,c_busy)* xuntil6(s49). % 76.04/76.23 45698[95:Spt:45697.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.23 45700[95:Res:45698.0,61.1] always3(s16) || -> . % 76.04/76.23 45701[95:SSi:45700.0,705.0,45280.0,45282.0] || -> . % 76.04/76.23 45702[95:Spt:45701.0,45697.1,45698.0] || m_main_v_state(s16,c_busy)*+ -> . % 76.04/76.23 45703[95:Spt:45701.0,45697.0,45697.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.23 45707[95:MRR:45654.2,45702.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.23 45708[95:Res:53.1,45703.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.23 45710[96:Spt:45708.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.23 45712[96:Res:45710.0,61.1] always3(s49) || -> . % 76.04/76.23 45713[96:SSi:45712.0,50.0,738.0,45549.0] || -> . % 76.04/76.23 45714[96:Spt:45713.0,45708.0,45710.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.23 45715[96:Spt:45713.0,45708.1] || -> xuntil6(s49)*. % 76.04/76.23 45716[96:MRR:45205.0,45715.0] || -> until2p7(s16)*. % 76.04/76.23 45717[96:MRR:212.0,45716.0] || -> until2p7(s17)* node4(s16). % 76.04/76.23 45719[96:MRR:774.2,45714.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.23 45720[97:Spt:45717.0] || -> until2p7(s17)*. % 76.04/76.23 45721[97:MRR:213.0,45720.0] || -> until2p7(s18)* node4(s17). % 76.04/76.23 45722[98:Spt:45721.0] || -> until2p7(s18)*. % 76.04/76.23 45723[98:MRR:214.0,45722.0] || -> until2p7(s19)* node4(s18). % 76.04/76.23 45724[99:Spt:45723.0] || -> until2p7(s19)*. % 76.04/76.23 45725[99:MRR:215.0,45724.0] || -> until2p7(s20)* node4(s19). % 76.04/76.23 45726[100:Spt:45725.0] || -> until2p7(s20)*. % 76.04/76.23 45727[100:MRR:216.0,45726.0] || -> until2p7(s21)* node4(s20). % 76.04/76.23 45728[101:Spt:45727.0] || -> until2p7(s21)*. % 76.04/76.23 45729[101:MRR:217.0,45728.0] || -> until2p7(s22)* node4(s21). % 76.04/76.23 45730[102:Spt:45729.0] || -> until2p7(s22)*. % 76.04/76.23 45731[102:MRR:218.0,45730.0] || -> until2p7(s23)* node4(s22). % 76.04/76.23 45732[103:Spt:45731.0] || -> until2p7(s23)*. % 76.04/76.23 45733[103:MRR:219.0,45732.0] || -> until2p7(s24)* node4(s23). % 76.04/76.23 45734[104:Spt:45733.0] || -> until2p7(s24)*. % 76.04/76.23 45735[104:MRR:220.0,45734.0] || -> until2p7(s25)* node4(s24). % 76.04/76.23 45736[105:Spt:45735.0] || -> until2p7(s25)*. % 76.04/76.23 45737[105:MRR:221.0,45736.0] || -> until2p7(s26)* node4(s25). % 76.04/76.23 45738[106:Spt:45737.0] || -> until2p7(s26)*. % 76.04/76.23 45739[106:MRR:222.0,45738.0] || -> until2p7(s27)* node4(s26). % 76.04/76.23 45740[107:Spt:45739.0] || -> until2p7(s27)*. % 76.04/76.23 45741[107:MRR:223.0,45740.0] || -> until2p7(s28)* node4(s27). % 76.04/76.23 45742[108:Spt:45741.0] || -> until2p7(s28)*. % 76.04/76.23 45743[108:MRR:224.0,45742.0] || -> until2p7(s29)* node4(s28). % 76.04/76.23 45744[109:Spt:45743.0] || -> until2p7(s29)*. % 76.04/76.23 45745[109:MRR:225.0,45744.0] || -> until2p7(s30)* node4(s29). % 76.04/76.23 45746[110:Spt:45745.0] || -> until2p7(s30)*. % 76.04/76.23 45747[110:MRR:226.0,45746.0] || -> until2p7(s31)* node4(s30). % 76.04/76.23 45748[111:Spt:45747.0] || -> until2p7(s31)*. % 76.04/76.23 45749[111:MRR:227.0,45748.0] || -> until2p7(s32)* node4(s31). % 76.04/76.23 45750[112:Spt:45749.0] || -> until2p7(s32)*. % 76.04/76.23 45751[112:MRR:228.0,45750.0] || -> until2p7(s33)* node4(s32). % 76.04/76.23 45752[113:Spt:45751.0] || -> until2p7(s33)*. % 76.04/76.23 45753[113:MRR:229.0,45752.0] || -> until2p7(s34)* node4(s33). % 76.04/76.23 45754[114:Spt:45753.0] || -> until2p7(s34)*. % 76.04/76.23 45755[114:MRR:230.0,45754.0] || -> until2p7(s35)* node4(s34). % 76.04/76.23 45756[115:Spt:45755.0] || -> until2p7(s35)*. % 76.04/76.23 45757[115:MRR:231.0,45756.0] || -> until2p7(s36)* node4(s35). % 76.04/76.23 45758[116:Spt:45757.0] || -> until2p7(s36)*. % 76.04/76.23 45759[116:MRR:232.0,45758.0] || -> until2p7(s37)* node4(s36). % 76.04/76.23 45760[117:Spt:45759.0] || -> until2p7(s37)*. % 76.04/76.23 45761[117:MRR:235.0,45760.0] || -> until2p7(s38)* node4(s37). % 76.04/76.23 45762[118:Spt:45761.0] || -> until2p7(s38)*. % 76.04/76.23 45763[118:MRR:236.0,45762.0] || -> until2p7(s39)* node4(s38). % 76.04/76.23 45764[119:Spt:45763.0] || -> until2p7(s39)*. % 76.04/76.23 45765[119:MRR:237.0,45764.0] || -> until2p7(s40)* node4(s39). % 76.04/76.23 45766[120:Spt:45765.0] || -> until2p7(s40)*. % 76.04/76.23 45767[120:MRR:238.0,45766.0] || -> until2p7(s41)* node4(s40). % 76.04/76.23 45768[121:Spt:45767.0] || -> until2p7(s41)*. % 76.04/76.23 45769[121:MRR:239.0,45768.0] || -> until2p7(s42)* node4(s41). % 76.04/76.23 45770[122:Spt:45769.0] || -> until2p7(s42)*. % 76.04/76.23 45771[122:MRR:240.0,45770.0] || -> until2p7(s43)* node4(s42). % 76.04/76.23 45772[123:Spt:45771.0] || -> until2p7(s43)*. % 76.04/76.23 45773[123:MRR:241.0,45772.0] || -> until2p7(s44)* node4(s43). % 76.04/76.23 45774[124:Spt:45773.0] || -> until2p7(s44)*. % 76.04/76.23 45775[124:MRR:539.0,45774.0] || -> until2p7(s45)* node4(s44). % 76.04/76.23 45776[125:Spt:45775.0] || -> until2p7(s45)*. % 76.04/76.23 45777[125:MRR:544.0,45776.0] || -> until2p7(s46)* node4(s45). % 76.04/76.23 45778[126:Spt:45777.0] || -> until2p7(s46)*. % 76.04/76.23 45779[126:MRR:549.0,45778.0] || -> until2p7(s47)* node4(s46). % 76.04/76.23 45780[127:Spt:45779.0] || -> until2p7(s47)*. % 76.04/76.23 45781[127:MRR:554.0,45780.0] || -> until2p7(s48)* node4(s47). % 76.04/76.23 45782[128:Spt:45781.0] || -> until2p7(s48)*. % 76.04/76.23 45783[128:MRR:559.0,45782.0] || -> until2p7(s49)* node4(s48). % 76.04/76.23 45784[129:Spt:45783.0] || -> until2p7(s49)*. % 76.04/76.23 45785[129:MRR:194.0,45784.0] || -> node4(s49)*. % 76.04/76.23 45786[129:MRR:45707.0,45785.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.23 45787[129:Res:53.1,45786.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.23 45789[129:MRR:45787.0,45714.0] || -> . % 76.04/76.23 45790[129:Spt:45789.0,45783.0,45784.0] || until2p7(s49)*+ -> . % 76.04/76.23 45791[129:Spt:45789.0,45783.1] || -> node4(s48)*. % 76.04/76.23 45792[129:MRR:45719.0,45791.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.23 45795[129:Res:53.1,45792.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.23 45797[129:MRR:45795.0,45535.0] || -> . % 76.04/76.23 45798[128:Spt:45797.0,45781.0,45782.0] || until2p7(s48)*+ -> . % 76.04/76.23 45799[128:Spt:45797.0,45781.1] || -> node4(s47)*. % 76.04/76.23 45800[128:MRR:45538.0,45799.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.23 45803[128:Res:53.1,45800.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.23 45806[128:Res:45803.0,61.1] always3(s47) || -> . % 76.04/76.23 45807[128:SSi:45806.0,736.0,45529.0,45541.0,45780.0,45799.0] || -> . % 76.04/76.23 45808[127:Spt:45807.0,45779.0,45780.0] || until2p7(s47)*+ -> . % 76.04/76.23 45809[127:Spt:45807.0,45779.1] || -> node4(s46)*. % 76.04/76.23 45811[127:MRR:780.0,45809.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.23 45831[127:Res:53.1,45811.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.23 45833[127:MRR:45831.0,45515.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.23 45835[127:Res:45833.0,61.1] always3(s47) || -> . % 76.04/76.23 45836[127:SSi:45835.0,736.0,45529.0,45541.0] || -> . % 76.04/76.23 45837[126:Spt:45836.0,45777.0,45778.0] || until2p7(s46)*+ -> . % 76.04/76.23 45838[126:Spt:45836.0,45777.1] || -> node4(s45)*. % 76.04/76.23 45839[126:MRR:45518.0,45838.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.23 45843[126:Res:53.1,45839.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.23 45846[126:Res:45843.0,61.1] always3(s45) || -> . % 76.04/76.23 45847[126:SSi:45846.0,734.0,45509.0,45524.0,45776.0,45838.0] || -> . % 76.04/76.23 45848[125:Spt:45847.0,45775.0,45776.0] || until2p7(s45)*+ -> . % 76.04/76.23 45849[125:Spt:45847.0,45775.1] || -> node4(s44)*. % 76.04/76.23 45851[125:MRR:786.0,45849.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.23 45862[125:Res:53.1,45851.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.23 45864[125:MRR:45862.0,45492.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.23 45866[125:Res:45864.0,61.1] always3(s45) || -> . % 76.04/76.23 45867[125:SSi:45866.0,734.0,45509.0,45524.0] || -> . % 76.04/76.23 45868[124:Spt:45867.0,45773.0,45774.0] || until2p7(s44)*+ -> . % 76.04/76.23 45869[124:Spt:45867.0,45773.1] || -> node4(s43)*. % 76.04/76.23 45870[124:MRR:45495.0,45869.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.23 45873[124:Res:53.1,45870.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.23 45876[124:Res:45873.0,61.1] always3(s43) || -> . % 76.04/76.23 45877[124:SSi:45876.0,732.0,45486.0,45498.0,45772.0,45869.0] || -> . % 76.04/76.23 45878[123:Spt:45877.0,45771.0,45772.0] || until2p7(s43)*+ -> . % 76.04/76.23 45879[123:Spt:45877.0,45771.1] || -> node4(s42)*. % 76.04/76.23 45881[123:MRR:792.0,45879.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.23 45893[123:Res:53.1,45881.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.23 45895[123:MRR:45893.0,45472.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.23 45897[123:Res:45895.0,61.1] always3(s43) || -> . % 76.04/76.23 45898[123:SSi:45897.0,732.0,45486.0,45498.0] || -> . % 76.04/76.23 45899[122:Spt:45898.0,45769.0,45770.0] || until2p7(s42)*+ -> . % 76.04/76.23 45900[122:Spt:45898.0,45769.1] || -> node4(s41)*. % 76.04/76.23 45901[122:MRR:45475.0,45900.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.23 45904[122:Res:53.1,45901.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.23 45907[122:Res:45904.0,61.1] always3(s41) || -> . % 76.04/76.23 45908[122:SSi:45907.0,730.0,45466.0,45478.0,45768.0,45900.0] || -> . % 76.04/76.23 45909[121:Spt:45908.0,45767.0,45768.0] || until2p7(s41)*+ -> . % 76.04/76.23 45910[121:Spt:45908.0,45767.1] || -> node4(s40)*. % 76.04/76.23 45912[121:MRR:798.0,45910.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.23 45924[121:Res:53.1,45912.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.23 45926[121:MRR:45924.0,45452.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.23 45931[121:Res:45926.0,61.1] always3(s41) || -> . % 76.04/76.23 45932[121:SSi:45931.0,730.0,45466.0,45478.0] || -> . % 76.04/76.23 45933[120:Spt:45932.0,45765.0,45766.0] || until2p7(s40)*+ -> . % 76.04/76.23 45934[120:Spt:45932.0,45765.1] || -> node4(s39)*. % 76.04/76.23 45935[120:MRR:45455.0,45934.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.23 45938[120:Res:53.1,45935.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.23 45942[120:Res:45938.0,61.1] always3(s39) || -> . % 76.04/76.23 45943[120:SSi:45942.0,728.0,45446.0,45461.0,45764.0,45934.0] || -> . % 76.04/76.23 45944[119:Spt:45943.0,45763.0,45764.0] || until2p7(s39)*+ -> . % 76.04/76.23 45945[119:Spt:45943.0,45763.1] || -> node4(s38)*. % 76.04/76.23 45947[119:MRR:804.0,45945.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.23 45958[119:Res:53.1,45947.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.23 45960[119:MRR:45958.0,45429.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.23 45962[119:Res:45960.0,61.1] always3(s39) || -> . % 76.04/76.23 45963[119:SSi:45962.0,728.0,45446.0,45461.0] || -> . % 76.04/76.23 45964[118:Spt:45963.0,45761.0,45762.0] || until2p7(s38)*+ -> . % 76.04/76.23 45965[118:Spt:45963.0,45761.1] || -> node4(s37)*. % 76.04/76.23 45966[118:MRR:45432.0,45965.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.23 45970[118:Res:53.1,45966.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.23 45973[118:Res:45970.0,61.1] always3(s37) || -> . % 76.04/76.23 45974[118:SSi:45973.0,726.0,45423.0,45435.0,45760.0,45965.0] || -> . % 76.04/76.23 45975[117:Spt:45974.0,45759.0,45760.0] || until2p7(s37)*+ -> . % 76.04/76.23 45976[117:Spt:45974.0,45759.1] || -> node4(s36)*. % 76.04/76.23 45978[117:MRR:810.0,45976.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.23 45989[117:Res:53.1,45978.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.23 45991[117:MRR:45989.0,45409.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.23 45993[117:Res:45991.0,61.1] always3(s37) || -> . % 76.04/76.23 45994[117:SSi:45993.0,726.0,45423.0,45435.0] || -> . % 76.04/76.23 45995[116:Spt:45994.0,45757.0,45758.0] || until2p7(s36)*+ -> . % 76.04/76.23 45996[116:Spt:45994.0,45757.1] || -> node4(s35)*. % 76.04/76.23 45997[116:MRR:45412.0,45996.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.23 46000[116:Res:53.1,45997.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.23 46003[116:Res:46000.0,61.1] always3(s35) || -> . % 76.04/76.23 46004[116:SSi:46003.0,724.0,45403.0,45415.0,45756.0,45996.0] || -> . % 76.04/76.23 46005[115:Spt:46004.0,45755.0,45756.0] || until2p7(s35)*+ -> . % 76.04/76.23 46006[115:Spt:46004.0,45755.1] || -> node4(s34)*. % 76.04/76.23 46008[115:MRR:816.0,46006.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.23 46020[115:Res:53.1,46008.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.23 46022[115:MRR:46020.0,45389.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.23 46024[115:Res:46022.0,61.1] always3(s35) || -> . % 76.04/76.23 46025[115:SSi:46024.0,724.0,45403.0,45415.0] || -> . % 76.04/76.23 46026[114:Spt:46025.0,45753.0,45754.0] || until2p7(s34)*+ -> . % 76.04/76.23 46027[114:Spt:46025.0,45753.1] || -> node4(s33)*. % 76.04/76.23 46028[114:MRR:45392.0,46027.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.23 46031[114:Res:53.1,46028.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.23 46034[114:Res:46031.0,61.1] always3(s33) || -> . % 76.04/76.23 46035[114:SSi:46034.0,722.0,45383.0,45398.0,45752.0,46027.0] || -> . % 76.04/76.23 46036[113:Spt:46035.0,45751.0,45752.0] || until2p7(s33)*+ -> . % 76.04/76.23 46037[113:Spt:46035.0,45751.1] || -> node4(s32)*. % 76.04/76.23 46039[113:MRR:822.0,46037.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.23 46051[113:Res:53.1,46039.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.23 46053[113:MRR:46051.0,45366.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.23 46058[113:Res:46053.0,61.1] always3(s33) || -> . % 76.04/76.23 46059[113:SSi:46058.0,722.0,45383.0,45398.0] || -> . % 76.04/76.23 46060[112:Spt:46059.0,45749.0,45750.0] || until2p7(s32)*+ -> . % 76.04/76.23 46061[112:Spt:46059.0,45749.1] || -> node4(s31)*. % 76.04/76.23 46062[112:MRR:45369.0,46061.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.04/76.23 46065[112:Res:53.1,46062.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.23 46069[112:Res:46065.0,61.1] always3(s31) || -> . % 76.04/76.23 46070[112:SSi:46069.0,720.0,45360.0,45372.0,45748.0,46061.0] || -> . % 76.04/76.23 46071[111:Spt:46070.0,45747.0,45748.0] || until2p7(s31)*+ -> . % 76.04/76.23 46072[111:Spt:46070.0,45747.1] || -> node4(s30)*. % 76.04/76.23 46074[111:MRR:828.0,46072.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.23 46085[111:Res:53.1,46074.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.23 46087[111:MRR:46085.0,45346.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.23 46089[111:Res:46087.0,61.1] always3(s31) || -> . % 76.04/76.23 46090[111:SSi:46089.0,720.0,45360.0,45372.0] || -> . % 76.04/76.23 46091[110:Spt:46090.0,45745.0,45746.0] || until2p7(s30)*+ -> . % 76.04/76.23 46092[110:Spt:46090.0,45745.1] || -> node4(s29)*. % 76.04/76.23 46093[110:MRR:45349.0,46092.0] || m_main_v_state(s29,c_ready)*+ -> . % 76.04/76.23 46097[110:Res:53.1,46093.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.23 46100[110:Res:46097.0,61.1] always3(s29) || -> . % 76.04/76.23 46101[110:SSi:46100.0,718.0,45337.0,45352.0,45744.0,46092.0] || -> . % 76.04/76.23 46102[109:Spt:46101.0,45743.0,45744.0] || until2p7(s29)*+ -> . % 76.04/76.23 46103[109:Spt:46101.0,45743.1] || -> node4(s28)*. % 76.04/76.23 46105[109:MRR:834.0,46103.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.23 46116[109:Res:53.1,46105.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.23 46118[110:Spt:46116.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.23 46120[110:Res:46118.0,61.1] always3(s28) || -> . % 76.04/76.23 46121[110:SSi:46120.0,717.0,45334.0,45336.0,45742.0,46103.0] || -> . % 76.04/76.23 46122[110:Spt:46121.0,46116.0,46118.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.23 46123[110:Spt:46121.0,46116.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.23 46127[110:Res:46123.0,61.1] always3(s29) || -> . % 76.04/76.23 46128[110:SSi:46127.0,718.0,45337.0,45352.0] || -> . % 76.04/76.23 46129[108:Spt:46128.0,45741.0,45742.0] || until2p7(s28)*+ -> . % 76.04/76.23 46130[108:Spt:46128.0,45741.1] || -> node4(s27)*. % 76.04/76.23 46132[108:MRR:837.0,46130.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.23 46142[108:Res:53.1,46132.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.23 46144[109:Spt:46142.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.23 46146[109:Res:46144.0,61.1] always3(s27) || -> . % 76.04/76.23 46147[109:SSi:46146.0,716.0,45328.0,45333.0,45740.0,46130.0] || -> . % 76.04/76.23 46148[109:Spt:46147.0,46142.0,46144.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.23 46149[109:Spt:46147.0,46142.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.23 46153[109:Res:46149.0,61.1] always3(s28) || -> . % 76.04/76.23 46154[109:SSi:46153.0,717.0,45334.0,45336.0] || -> . % 76.04/76.23 46155[107:Spt:46154.0,45739.0,45740.0] || until2p7(s27)*+ -> . % 76.04/76.23 46156[107:Spt:46154.0,45739.1] || -> node4(s26)*. % 76.04/76.23 46158[107:MRR:840.0,46156.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.23 46161[107:Res:53.1,46158.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.23 46163[108:Spt:46161.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.23 46165[108:Res:46163.0,61.1] always3(s26) || -> . % 76.04/76.23 46166[108:SSi:46165.0,715.0,45325.0,45327.0,45738.0,46156.0] || -> . % 76.04/76.23 46167[108:Spt:46166.0,46161.0,46163.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.23 46168[108:Spt:46166.0,46161.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.23 46172[108:Res:46168.0,61.1] always3(s27) || -> . % 76.04/76.23 46173[108:SSi:46172.0,716.0,45328.0,45333.0] || -> . % 76.04/76.23 46174[106:Spt:46173.0,45737.0,45738.0] || until2p7(s26)*+ -> . % 76.04/76.23 46175[106:Spt:46173.0,45737.1] || -> node4(s25)*. % 76.04/76.23 46177[106:MRR:843.0,46175.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.23 46180[106:Res:53.1,46177.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.23 46182[107:Spt:46180.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.23 46184[107:Res:46182.0,61.1] always3(s25) || -> . % 76.04/76.23 46185[107:SSi:46184.0,714.0,45319.0,45324.0,45736.0,46175.0] || -> . % 76.04/76.23 46186[107:Spt:46185.0,46180.0,46182.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.23 46187[107:Spt:46185.0,46180.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.23 46191[107:Res:46187.0,61.1] always3(s26) || -> . % 76.04/76.23 46192[107:SSi:46191.0,715.0,45325.0,45327.0] || -> . % 76.04/76.23 46193[105:Spt:46192.0,45735.0,45736.0] || until2p7(s25)*+ -> . % 76.04/76.23 46194[105:Spt:46192.0,45735.1] || -> node4(s24)*. % 76.04/76.23 46196[105:MRR:846.0,46194.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.23 46199[105:Res:53.1,46196.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.23 46204[106:Spt:46199.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.23 46206[106:Res:46204.0,61.1] always3(s24) || -> . % 76.04/76.23 46207[106:SSi:46206.0,713.0,45316.0,45318.0,45734.0,46194.0] || -> . % 76.04/76.23 46208[106:Spt:46207.0,46199.0,46204.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.23 46209[106:Spt:46207.0,46199.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.23 46213[106:Res:46209.0,61.1] always3(s25) || -> . % 76.04/76.23 46214[106:SSi:46213.0,714.0,45319.0,45324.0] || -> . % 76.04/76.23 46215[104:Spt:46214.0,45733.0,45734.0] || until2p7(s24)*+ -> . % 76.04/76.23 46216[104:Spt:46214.0,45733.1] || -> node4(s23)*. % 76.04/76.23 46218[104:MRR:849.0,46216.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.23 46221[104:Res:53.1,46218.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.23 46223[105:Spt:46221.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.23 46225[105:Res:46223.0,61.1] always3(s23) || -> . % 76.04/76.23 46226[105:SSi:46225.0,712.0,45310.0,45315.0,45732.0,46216.0] || -> . % 76.04/76.23 46227[105:Spt:46226.0,46221.0,46223.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.23 46228[105:Spt:46226.0,46221.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.23 46232[105:Res:46228.0,61.1] always3(s24) || -> . % 76.04/76.23 46233[105:SSi:46232.0,713.0,45316.0,45318.0] || -> . % 76.04/76.23 46234[103:Spt:46233.0,45731.0,45732.0] || until2p7(s23)*+ -> . % 76.04/76.23 46235[103:Spt:46233.0,45731.1] || -> node4(s22)*. % 76.04/76.23 46237[103:MRR:852.0,46235.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.23 46240[103:Res:53.1,46237.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.23 46242[104:Spt:46240.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.23 46244[104:Res:46242.0,61.1] always3(s22) || -> . % 76.04/76.23 46245[104:SSi:46244.0,711.0,45307.0,45309.0,45730.0,46235.0] || -> . % 76.04/76.23 46246[104:Spt:46245.0,46240.0,46242.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.23 46247[104:Spt:46245.0,46240.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.23 46251[104:Res:46247.0,61.1] always3(s23) || -> . % 76.04/76.23 46252[104:SSi:46251.0,712.0,45310.0,45315.0] || -> . % 76.04/76.23 46253[102:Spt:46252.0,45729.0,45730.0] || until2p7(s22)*+ -> . % 76.04/76.23 46254[102:Spt:46252.0,45729.1] || -> node4(s21)*. % 76.04/76.23 46256[102:MRR:855.0,46254.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.23 46259[102:Res:53.1,46256.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.23 46261[103:Spt:46259.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.23 46263[103:Res:46261.0,61.1] always3(s21) || -> . % 76.04/76.23 46264[103:SSi:46263.0,710.0,45301.0,45306.0,45728.0,46254.0] || -> . % 76.04/76.23 46265[103:Spt:46264.0,46259.0,46261.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.23 46266[103:Spt:46264.0,46259.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.23 46270[103:Res:46266.0,61.1] always3(s22) || -> . % 76.04/76.23 46271[103:SSi:46270.0,711.0,45307.0,45309.0] || -> . % 76.04/76.23 46272[101:Spt:46271.0,45727.0,45728.0] || until2p7(s21)*+ -> . % 76.04/76.23 46273[101:Spt:46271.0,45727.1] || -> node4(s20)*. % 76.04/76.23 46275[101:MRR:858.0,46273.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.23 46278[101:Res:53.1,46275.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.23 46283[102:Spt:46278.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.23 46285[102:Res:46283.0,61.1] always3(s20) || -> . % 76.04/76.23 46286[102:SSi:46285.0,709.0,45298.0,45300.0,45726.0,46273.0] || -> . % 76.04/76.23 46287[102:Spt:46286.0,46278.0,46283.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.23 46288[102:Spt:46286.0,46278.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.23 46292[102:Res:46288.0,61.1] always3(s21) || -> . % 76.04/76.23 46293[102:SSi:46292.0,710.0,45301.0,45306.0] || -> . % 76.04/76.23 46294[100:Spt:46293.0,45725.0,45726.0] || until2p7(s20)*+ -> . % 76.04/76.23 46295[100:Spt:46293.0,45725.1] || -> node4(s19)*. % 76.04/76.23 46297[100:MRR:861.0,46295.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.23 46300[100:Res:53.1,46297.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.23 46302[101:Spt:46300.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.23 46304[101:Res:46302.0,61.1] always3(s19) || -> . % 76.04/76.23 46305[101:SSi:46304.0,708.0,45292.0,45297.0,45724.0,46295.0] || -> . % 76.04/76.23 46306[101:Spt:46305.0,46300.0,46302.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.23 46307[101:Spt:46305.0,46300.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.23 46311[101:Res:46307.0,61.1] always3(s20) || -> . % 76.04/76.23 46312[101:SSi:46311.0,709.0,45298.0,45300.0] || -> . % 76.04/76.23 46313[99:Spt:46312.0,45723.0,45724.0] || until2p7(s19)*+ -> . % 76.04/76.23 46314[99:Spt:46312.0,45723.1] || -> node4(s18)*. % 76.04/76.23 46316[99:MRR:864.0,46314.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.23 46319[99:Res:53.1,46316.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.23 46321[100:Spt:46319.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.23 46323[100:Res:46321.0,61.1] always3(s18) || -> . % 76.04/76.23 46324[100:SSi:46323.0,707.0,45289.0,45291.0,45722.0,46314.0] || -> . % 76.04/76.23 46325[100:Spt:46324.0,46319.0,46321.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.23 46326[100:Spt:46324.0,46319.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.23 46330[100:Res:46326.0,61.1] always3(s19) || -> . % 76.04/76.23 46331[100:SSi:46330.0,708.0,45292.0,45297.0] || -> . % 76.04/76.23 46332[98:Spt:46331.0,45721.0,45722.0] || until2p7(s18)*+ -> . % 76.04/76.23 46333[98:Spt:46331.0,45721.1] || -> node4(s17)*. % 76.04/76.23 46335[98:MRR:867.0,46333.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.23 46338[98:Res:53.1,46335.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.23 46340[99:Spt:46338.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.23 46342[99:Res:46340.0,61.1] always3(s17) || -> . % 76.04/76.23 46343[99:SSi:46342.0,706.0,45283.0,45288.0,45720.0,46333.0] || -> . % 76.04/76.23 46344[99:Spt:46343.0,46338.0,46340.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.23 46345[99:Spt:46343.0,46338.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.23 46349[99:Res:46345.0,61.1] always3(s18) || -> . % 76.04/76.23 46350[99:SSi:46349.0,707.0,45289.0,45291.0] || -> . % 76.04/76.23 46351[97:Spt:46350.0,45717.0,45720.0] || until2p7(s17)*+ -> . % 76.04/76.23 46352[97:Spt:46350.0,45717.1] || -> node4(s16)*. % 76.04/76.23 46354[97:MRR:870.0,46352.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.23 46357[97:Res:53.1,46354.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.23 46359[97:MRR:46357.0,45702.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.23 46364[97:Res:46359.0,61.1] always3(s17) || -> . % 76.04/76.23 46365[97:SSi:46364.0,706.0,45283.0,45288.0] || -> . % 76.04/76.23 46366[94:Spt:46365.0,45543.2,45548.0] || xuntil6(s48)*+ -> . % 76.04/76.23 46367[94:Spt:46365.0,45543.0,45543.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.23 46368[94:Res:53.1,46367.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.23 46370[94:MRR:46368.0,45535.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.23 46372[94:Res:46370.0,61.1] always3(s49) || -> . % 76.04/76.23 46373[94:SSi:46372.0,50.0,738.0] || -> . % 76.04/76.23 46374[93:Spt:46373.0,45539.1,45541.0] || xuntil6(s47)* -> . % 76.04/76.23 46375[93:Spt:46373.0,45539.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.23 46378[93:Res:46375.0,61.1] always3(s47) || -> . % 76.04/76.23 46379[93:SSi:46378.0,736.0,45529.0] || -> . % 76.04/76.23 46380[91:Spt:46379.0,45526.2,45528.0] || xuntil6(s46)*+ -> . % 76.04/76.23 46381[91:Spt:46379.0,45526.0,45526.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.23 46382[91:Res:53.1,46381.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.23 46384[91:MRR:46382.0,45515.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.23 46387[91:Res:46384.0,61.1] always3(s47) || -> . % 76.04/76.23 46388[91:SSi:46387.0,736.0] || -> . % 76.04/76.23 46389[90:Spt:46388.0,45519.1,45524.0] || xuntil6(s45)* -> . % 76.04/76.23 46390[90:Spt:46388.0,45519.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.23 46393[90:Res:46390.0,61.1] always3(s45) || -> . % 76.04/76.23 46394[90:SSi:46393.0,734.0,45509.0] || -> . % 76.04/76.23 46395[88:Spt:46394.0,45500.2,45508.0] || xuntil6(s44)*+ -> . % 76.04/76.23 46396[88:Spt:46394.0,45500.0,45500.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.23 46397[88:Res:53.1,46396.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.23 46399[88:MRR:46397.0,45492.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.23 46401[88:Res:46399.0,61.1] always3(s45) || -> . % 76.04/76.23 46402[88:SSi:46401.0,734.0] || -> . % 76.04/76.23 46403[87:Spt:46402.0,45496.1,45498.0] || xuntil6(s43)* -> . % 76.04/76.23 46404[87:Spt:46402.0,45496.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.23 46407[87:Res:46404.0,61.1] always3(s43) || -> . % 76.04/76.23 46408[87:SSi:46407.0,732.0,45486.0] || -> . % 76.04/76.23 46409[85:Spt:46408.0,45480.2,45485.0] || xuntil6(s42)*+ -> . % 76.04/76.23 46410[85:Spt:46408.0,45480.0,45480.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.23 46411[85:Res:53.1,46410.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.23 46413[85:MRR:46411.0,45472.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.23 46416[85:Res:46413.0,61.1] always3(s43) || -> . % 76.04/76.23 46417[85:SSi:46416.0,732.0] || -> . % 76.04/76.23 46418[84:Spt:46417.0,45476.1,45478.0] || xuntil6(s41)* -> . % 76.04/76.23 46419[84:Spt:46417.0,45476.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.23 46422[84:Res:46419.0,61.1] always3(s41) || -> . % 76.04/76.23 46423[84:SSi:46422.0,730.0,45466.0] || -> . % 76.04/76.23 46424[82:Spt:46423.0,45463.2,45465.0] || xuntil6(s40)*+ -> . % 76.04/76.23 46425[82:Spt:46423.0,45463.0,45463.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.23 46426[82:Res:53.1,46425.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.23 46428[82:MRR:46426.0,45452.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.23 46430[82:Res:46428.0,61.1] always3(s41) || -> . % 76.04/76.23 46431[82:SSi:46430.0,730.0] || -> . % 76.04/76.23 46432[81:Spt:46431.0,45456.1,45461.0] || xuntil6(s39)* -> . % 76.04/76.23 46433[81:Spt:46431.0,45456.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.23 46436[81:Res:46433.0,61.1] always3(s39) || -> . % 76.04/76.23 46437[81:SSi:46436.0,728.0,45446.0] || -> . % 76.04/76.23 46438[79:Spt:46437.0,45437.2,45445.0] || xuntil6(s38)*+ -> . % 76.04/76.23 46439[79:Spt:46437.0,45437.0,45437.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.23 46440[79:Res:53.1,46439.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.23 46442[79:MRR:46440.0,45429.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.23 46444[79:Res:46442.0,61.1] always3(s39) || -> . % 76.04/76.23 46445[79:SSi:46444.0,728.0] || -> . % 76.04/76.23 46446[78:Spt:46445.0,45433.1,45435.0] || xuntil6(s37)* -> . % 76.04/76.23 46447[78:Spt:46445.0,45433.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.23 46450[78:Res:46447.0,61.1] always3(s37) || -> . % 76.04/76.23 46451[78:SSi:46450.0,726.0,45423.0] || -> . % 76.04/76.23 46452[76:Spt:46451.0,45417.2,45422.0] || xuntil6(s36)*+ -> . % 76.04/76.23 46453[76:Spt:46451.0,45417.0,45417.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.23 46454[76:Res:53.1,46453.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.23 46456[76:MRR:46454.0,45409.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.23 46458[76:Res:46456.0,61.1] always3(s37) || -> . % 76.04/76.23 46459[76:SSi:46458.0,726.0] || -> . % 76.04/76.23 46460[75:Spt:46459.0,45413.1,45415.0] || xuntil6(s35)* -> . % 76.04/76.23 46461[75:Spt:46459.0,45413.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.23 46464[75:Res:46461.0,61.1] always3(s35) || -> . % 76.04/76.23 46465[75:SSi:46464.0,724.0,45403.0] || -> . % 76.04/76.23 46466[73:Spt:46465.0,45400.2,45402.0] || xuntil6(s34)*+ -> . % 76.04/76.23 46467[73:Spt:46465.0,45400.0,45400.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.23 46468[73:Res:53.1,46467.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.23 46470[73:MRR:46468.0,45389.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.23 46472[73:Res:46470.0,61.1] always3(s35) || -> . % 76.04/76.23 46473[73:SSi:46472.0,724.0] || -> . % 76.04/76.23 46474[72:Spt:46473.0,45393.1,45398.0] || xuntil6(s33)* -> . % 76.04/76.23 46475[72:Spt:46473.0,45393.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.23 46478[72:Res:46475.0,61.1] always3(s33) || -> . % 76.04/76.23 46479[72:SSi:46478.0,722.0,45383.0] || -> . % 76.04/76.23 46480[70:Spt:46479.0,45374.2,45382.0] || xuntil6(s32)*+ -> . % 76.04/76.23 46481[70:Spt:46479.0,45374.0,45374.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.23 46482[70:Res:53.1,46481.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.23 46484[70:MRR:46482.0,45366.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.23 46486[70:Res:46484.0,61.1] always3(s33) || -> . % 76.04/76.23 46487[70:SSi:46486.0,722.0] || -> . % 76.04/76.23 46488[69:Spt:46487.0,45370.1,45372.0] || xuntil6(s31)* -> . % 76.04/76.23 46489[69:Spt:46487.0,45370.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.23 46492[69:Res:46489.0,61.1] always3(s31) || -> . % 76.04/76.23 46493[69:SSi:46492.0,720.0,45360.0] || -> . % 76.04/76.23 46494[67:Spt:46493.0,45354.2,45359.0] || xuntil6(s30)*+ -> . % 76.04/76.23 46495[67:Spt:46493.0,45354.0,45354.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.23 46496[67:Res:53.1,46495.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.23 46498[67:MRR:46496.0,45346.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.23 46500[67:Res:46498.0,61.1] always3(s31) || -> . % 76.04/76.23 46501[67:SSi:46500.0,720.0] || -> . % 76.04/76.23 46502[66:Spt:46501.0,45350.1,45352.0] || xuntil6(s29)* -> . % 76.04/76.23 46503[66:Spt:46501.0,45350.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.23 46506[66:Res:46503.0,61.1] always3(s29) || -> . % 76.04/76.23 46507[66:SSi:46506.0,718.0,45337.0] || -> . % 76.04/76.23 46508[64:Spt:46507.0,45335.2,45336.0] || xuntil6(s28)*+ -> . % 76.04/76.23 46509[64:Spt:46507.0,45335.0,45335.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.23 46510[64:Res:53.1,46509.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.23 46512[65:Spt:46510.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.23 46514[65:Res:46512.0,61.1] always3(s29) || -> . % 76.04/76.23 46515[65:SSi:46514.0,718.0] || -> . % 76.04/76.23 46516[65:Spt:46515.0,46510.1,46512.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.23 46517[65:Spt:46515.0,46510.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.23 46520[65:Res:46517.0,61.1] always3(s28) || -> . % 76.04/76.23 46521[65:SSi:46520.0,717.0,45334.0] || -> . % 76.04/76.23 46522[63:Spt:46521.0,45329.2,45333.0] || xuntil6(s27)*+ -> . % 76.04/76.23 46523[63:Spt:46521.0,45329.0,45329.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.23 46524[63:Res:53.1,46523.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.23 46526[64:Spt:46524.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.23 46528[64:Res:46526.0,61.1] always3(s28) || -> . % 76.04/76.23 46529[64:SSi:46528.0,717.0] || -> . % 76.04/76.23 46530[64:Spt:46529.0,46524.1,46526.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.23 46531[64:Spt:46529.0,46524.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.23 46534[64:Res:46531.0,61.1] always3(s27) || -> . % 76.04/76.23 46535[64:SSi:46534.0,716.0,45328.0] || -> . % 76.04/76.23 46536[62:Spt:46535.0,45326.2,45327.0] || xuntil6(s26)*+ -> . % 76.04/76.23 46537[62:Spt:46535.0,45326.0,45326.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.23 46538[62:Res:53.1,46537.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.23 46540[63:Spt:46538.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.23 46542[63:Res:46540.0,61.1] always3(s27) || -> . % 76.04/76.23 46543[63:SSi:46542.0,716.0] || -> . % 76.04/76.23 46544[63:Spt:46543.0,46538.1,46540.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.23 46545[63:Spt:46543.0,46538.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.23 46548[63:Res:46545.0,61.1] always3(s26) || -> . % 76.04/76.23 46549[63:SSi:46548.0,715.0,45325.0] || -> . % 76.04/76.23 46550[61:Spt:46549.0,45320.2,45324.0] || xuntil6(s25)*+ -> . % 76.04/76.23 46551[61:Spt:46549.0,45320.0,45320.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.23 46552[61:Res:53.1,46551.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.23 46554[62:Spt:46552.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.23 46556[62:Res:46554.0,61.1] always3(s26) || -> . % 76.04/76.23 46557[62:SSi:46556.0,715.0] || -> . % 76.04/76.23 46558[62:Spt:46557.0,46552.1,46554.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.23 46559[62:Spt:46557.0,46552.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.23 46562[62:Res:46559.0,61.1] always3(s25) || -> . % 76.04/76.23 46563[62:SSi:46562.0,714.0,45319.0] || -> . % 76.04/76.23 46564[60:Spt:46563.0,45317.2,45318.0] || xuntil6(s24)*+ -> . % 76.04/76.23 46565[60:Spt:46563.0,45317.0,45317.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.23 46566[60:Res:53.1,46565.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.23 46568[61:Spt:46566.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.23 46570[61:Res:46568.0,61.1] always3(s25) || -> . % 76.04/76.23 46571[61:SSi:46570.0,714.0] || -> . % 76.04/76.23 46572[61:Spt:46571.0,46566.1,46568.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.23 46573[61:Spt:46571.0,46566.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.23 46576[61:Res:46573.0,61.1] always3(s24) || -> . % 76.04/76.23 46577[61:SSi:46576.0,713.0,45316.0] || -> . % 76.04/76.23 46578[59:Spt:46577.0,45311.2,45315.0] || xuntil6(s23)*+ -> . % 76.04/76.23 46579[59:Spt:46577.0,45311.0,45311.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.23 46580[59:Res:53.1,46579.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.23 46582[60:Spt:46580.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.23 46584[60:Res:46582.0,61.1] always3(s24) || -> . % 76.04/76.23 46585[60:SSi:46584.0,713.0] || -> . % 76.04/76.23 46586[60:Spt:46585.0,46580.1,46582.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.23 46587[60:Spt:46585.0,46580.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.23 46590[60:Res:46587.0,61.1] always3(s23) || -> . % 76.04/76.23 46591[60:SSi:46590.0,712.0,45310.0] || -> . % 76.04/76.23 46592[58:Spt:46591.0,45308.2,45309.0] || xuntil6(s22)*+ -> . % 76.04/76.23 46593[58:Spt:46591.0,45308.0,45308.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.23 46594[58:Res:53.1,46593.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.23 46596[59:Spt:46594.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.23 46598[59:Res:46596.0,61.1] always3(s23) || -> . % 76.04/76.23 46599[59:SSi:46598.0,712.0] || -> . % 76.04/76.23 46600[59:Spt:46599.0,46594.1,46596.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.23 46601[59:Spt:46599.0,46594.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.23 46604[59:Res:46601.0,61.1] always3(s22) || -> . % 76.04/76.23 46605[59:SSi:46604.0,711.0,45307.0] || -> . % 76.04/76.23 46606[57:Spt:46605.0,45302.2,45306.0] || xuntil6(s21)*+ -> . % 76.04/76.23 46607[57:Spt:46605.0,45302.0,45302.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.23 46608[57:Res:53.1,46607.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.23 46613[58:Spt:46608.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.23 46615[58:Res:46613.0,61.1] always3(s21) || -> . % 76.04/76.23 46616[58:SSi:46615.0,710.0,45301.0] || -> . % 76.04/76.23 46617[58:Spt:46616.0,46608.0,46613.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.23 46618[58:Spt:46616.0,46608.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.23 46622[58:Res:46618.0,61.1] always3(s22) || -> . % 76.04/76.23 46623[58:SSi:46622.0,711.0] || -> . % 76.04/76.23 46624[56:Spt:46623.0,45299.2,45300.0] || xuntil6(s20)*+ -> . % 76.04/76.23 46625[56:Spt:46623.0,45299.0,45299.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.23 46626[56:Res:53.1,46625.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.23 46628[57:Spt:46626.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.23 46630[57:Res:46628.0,61.1] always3(s21) || -> . % 76.04/76.23 46631[57:SSi:46630.0,710.0] || -> . % 76.04/76.23 46632[57:Spt:46631.0,46626.1,46628.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.23 46633[57:Spt:46631.0,46626.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.23 46636[57:Res:46633.0,61.1] always3(s20) || -> . % 76.04/76.23 46637[57:SSi:46636.0,709.0,45298.0] || -> . % 76.04/76.23 46638[55:Spt:46637.0,45293.2,45297.0] || xuntil6(s19)*+ -> . % 76.04/76.23 46639[55:Spt:46637.0,45293.0,45293.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.23 46640[55:Res:53.1,46639.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.23 46642[56:Spt:46640.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.23 46644[56:Res:46642.0,61.1] always3(s20) || -> . % 76.04/76.23 46645[56:SSi:46644.0,709.0] || -> . % 76.04/76.23 46646[56:Spt:46645.0,46640.1,46642.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.23 46647[56:Spt:46645.0,46640.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.23 46650[56:Res:46647.0,61.1] always3(s19) || -> . % 76.04/76.23 46651[56:SSi:46650.0,708.0,45292.0] || -> . % 76.04/76.23 46652[54:Spt:46651.0,45290.2,45291.0] || xuntil6(s18)*+ -> . % 76.04/76.23 46653[54:Spt:46651.0,45290.0,45290.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.23 46654[54:Res:53.1,46653.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.23 46659[55:Spt:46654.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.23 46661[55:Res:46659.0,61.1] always3(s19) || -> . % 76.04/76.23 46662[55:SSi:46661.0,708.0] || -> . % 76.04/76.23 46663[55:Spt:46662.0,46654.1,46659.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.23 46664[55:Spt:46662.0,46654.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.23 46667[55:Res:46664.0,61.1] always3(s18) || -> . % 76.04/76.23 46668[55:SSi:46667.0,707.0,45289.0] || -> . % 76.04/76.23 46669[53:Spt:46668.0,45284.2,45288.0] || xuntil6(s17)*+ -> . % 76.04/76.23 46670[53:Spt:46668.0,45284.0,45284.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.23 46671[53:Res:53.1,46670.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.23 46673[54:Spt:46671.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.23 46675[54:Res:46673.0,61.1] always3(s17) || -> . % 76.04/76.23 46676[54:SSi:46675.0,706.0,45283.0] || -> . % 76.04/76.23 46677[54:Spt:46676.0,46671.0,46673.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.23 46678[54:Spt:46676.0,46671.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.23 46682[54:Res:46678.0,61.1] always3(s18) || -> . % 76.04/76.23 46683[54:SSi:46682.0,707.0] || -> . % 76.04/76.23 46684[52:Spt:46683.0,45281.2,45282.0] || xuntil6(s16)*+ -> . % 76.04/76.23 46685[52:Spt:46683.0,45281.0,45281.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.23 46686[52:Res:53.1,46685.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.23 46688[53:Spt:46686.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.23 46690[53:Res:46688.0,61.1] always3(s17) || -> . % 76.04/76.23 46691[53:SSi:46690.0,706.0] || -> . % 76.04/76.23 46692[53:Spt:46691.0,46686.1,46688.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.23 46693[53:Spt:46691.0,46686.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.23 46696[53:Res:46693.0,61.1] always3(s16) || -> . % 76.04/76.23 46697[53:SSi:46696.0,705.0,45280.0] || -> . % 76.04/76.23 46698[51:Spt:46697.0,45275.2,45279.0] || xuntil6(s15)*+ -> . % 76.04/76.23 46699[51:Spt:46697.0,45275.0,45275.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.23 46700[51:Res:53.1,46699.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.23 46705[52:Spt:46700.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.23 46707[52:Res:46705.0,61.1] always3(s15) || -> . % 76.04/76.23 46708[52:SSi:46707.0,704.0,45274.0] || -> . % 76.04/76.23 46709[52:Spt:46708.0,46700.0,46705.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.23 46710[52:Spt:46708.0,46700.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.23 46714[52:Res:46710.0,61.1] always3(s16) || -> . % 76.04/76.23 46715[52:SSi:46714.0,705.0] || -> . % 76.04/76.23 46716[50:Spt:46715.0,45272.2,45273.0] || xuntil6(s14)*+ -> . % 76.04/76.23 46717[50:Spt:46715.0,45272.0,45272.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.23 46718[50:Res:53.1,46717.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.23 46720[51:Spt:46718.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.23 46722[51:Res:46720.0,61.1] always3(s14) || -> . % 76.04/76.23 46723[51:SSi:46722.0,703.0,45271.0] || -> . % 76.04/76.23 46724[51:Spt:46723.0,46718.0,46720.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.23 46725[51:Spt:46723.0,46718.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.23 46729[51:Res:46725.0,61.1] always3(s15) || -> . % 76.04/76.23 46730[51:SSi:46729.0,704.0] || -> . % 76.04/76.23 46731[49:Spt:46730.0,45266.2,45270.0] || xuntil6(s13)*+ -> . % 76.04/76.23 46732[49:Spt:46730.0,45266.0,45266.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.23 46733[49:Res:53.1,46732.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.23 46735[50:Spt:46733.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.23 46737[50:Res:46735.0,61.1] always3(s13) || -> . % 76.04/76.23 46738[50:SSi:46737.0,702.0,45265.0] || -> . % 76.04/76.23 46739[50:Spt:46738.0,46733.0,46735.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.23 46740[50:Spt:46738.0,46733.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.23 46744[50:Res:46740.0,61.1] always3(s14) || -> . % 76.04/76.23 46745[50:SSi:46744.0,703.0] || -> . % 76.04/76.23 46746[48:Spt:46745.0,45263.2,45264.0] || xuntil6(s12)*+ -> . % 76.04/76.23 46747[48:Spt:46745.0,45263.0,45263.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.23 46748[48:Res:53.1,46747.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.23 46753[49:Spt:46748.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.23 46755[49:Res:46753.0,61.1] always3(s12) || -> . % 76.04/76.23 46756[49:SSi:46755.0,701.0,45262.0] || -> . % 76.04/76.23 46757[49:Spt:46756.0,46748.0,46753.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.23 46758[49:Spt:46756.0,46748.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.23 46762[49:Res:46758.0,61.1] always3(s13) || -> . % 76.04/76.23 46763[49:SSi:46762.0,702.0] || -> . % 76.04/76.23 46764[47:Spt:46763.0,45257.2,45261.0] || xuntil6(s11)*+ -> . % 76.04/76.23 46765[47:Spt:46763.0,45257.0,45257.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.23 46766[47:Res:53.1,46765.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.23 46768[48:Spt:46766.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.23 46770[48:Res:46768.0,61.1] always3(s11) || -> . % 76.04/76.23 46771[48:SSi:46770.0,700.0,45256.0] || -> . % 76.04/76.23 46772[48:Spt:46771.0,46766.0,46768.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.23 46773[48:Spt:46771.0,46766.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.23 46777[48:Res:46773.0,61.1] always3(s12) || -> . % 76.04/76.23 46778[48:SSi:46777.0,701.0] || -> . % 76.04/76.23 46779[46:Spt:46778.0,45254.2,45255.0] || xuntil6(s10)*+ -> . % 76.04/76.23 46780[46:Spt:46778.0,45254.0,45254.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.23 46781[46:Res:53.1,46780.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.23 46783[47:Spt:46781.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.23 46785[47:Res:46783.0,61.1] always3(s10) || -> . % 76.04/76.23 46786[47:SSi:46785.0,699.0,45253.0] || -> . % 76.04/76.23 46787[47:Spt:46786.0,46781.0,46783.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.23 46788[47:Spt:46786.0,46781.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.23 46792[47:Res:46788.0,61.1] always3(s11) || -> . % 76.04/76.23 46793[47:SSi:46792.0,700.0] || -> . % 76.04/76.23 46794[45:Spt:46793.0,45248.2,45252.0] || xuntil6(s9)*+ -> . % 76.04/76.23 46795[45:Spt:46793.0,45248.0,45248.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.23 46796[45:Res:53.1,46795.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.23 46801[46:Spt:46796.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.23 46803[46:Res:46801.0,61.1] always3(s9) || -> . % 76.04/76.23 46804[46:SSi:46803.0,698.0,45247.0] || -> . % 76.04/76.23 46805[46:Spt:46804.0,46796.0,46801.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.23 46806[46:Spt:46804.0,46796.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.23 46810[46:Res:46806.0,61.1] always3(s10) || -> . % 76.04/76.23 46811[46:SSi:46810.0,699.0] || -> . % 76.04/76.23 46812[44:Spt:46811.0,45245.2,45246.0] || xuntil6(s8)*+ -> . % 76.04/76.23 46813[44:Spt:46811.0,45245.0,45245.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.23 46814[44:Res:53.1,46813.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.23 46816[45:Spt:46814.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.23 46818[45:Res:46816.0,61.1] always3(s8) || -> . % 76.04/76.23 46819[45:SSi:46818.0,697.0,45244.0] || -> . % 76.04/76.23 46820[45:Spt:46819.0,46814.0,46816.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.23 46821[45:Spt:46819.0,46814.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.23 46825[45:Res:46821.0,61.1] always3(s9) || -> . % 76.04/76.23 46826[45:SSi:46825.0,698.0] || -> . % 76.04/76.23 46827[43:Spt:46826.0,45239.2,45243.0] || xuntil6(s7)*+ -> . % 76.04/76.23 46828[43:Spt:46826.0,45239.0,45239.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.23 46829[43:Res:53.1,46828.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.23 46831[44:Spt:46829.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.23 46833[44:Res:46831.0,61.1] always3(s7) || -> . % 76.04/76.23 46834[44:SSi:46833.0,696.0,45238.0] || -> . % 76.04/76.23 46835[44:Spt:46834.0,46829.0,46831.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.23 46836[44:Spt:46834.0,46829.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.23 46840[44:Res:46836.0,61.1] always3(s8) || -> . % 76.04/76.23 46841[44:SSi:46840.0,697.0] || -> . % 76.04/76.23 46842[42:Spt:46841.0,45236.2,45237.0] || xuntil6(s6)*+ -> . % 76.04/76.23 46843[42:Spt:46841.0,45236.0,45236.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.23 46844[42:Res:53.1,46843.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.23 46849[43:Spt:46844.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.23 46851[43:Res:46849.0,61.1] always3(s6) || -> . % 76.04/76.23 46852[43:SSi:46851.0,695.0,45235.0] || -> . % 76.04/76.23 46853[43:Spt:46852.0,46844.0,46849.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.23 46854[43:Spt:46852.0,46844.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.23 46858[43:Res:46854.0,61.1] always3(s7) || -> . % 76.04/76.23 46859[43:SSi:46858.0,696.0] || -> . % 76.04/76.23 46860[41:Spt:46859.0,45230.2,45234.0] || xuntil6(s5)*+ -> . % 76.04/76.23 46861[41:Spt:46859.0,45230.0,45230.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.23 46862[41:Res:53.1,46861.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.23 46864[42:Spt:46862.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.23 46866[42:Res:46864.0,61.1] always3(s5) || -> . % 76.04/76.23 46867[42:SSi:46866.0,694.0,45229.0] || -> . % 76.04/76.23 46868[42:Spt:46867.0,46862.0,46864.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.23 46869[42:Spt:46867.0,46862.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.23 46873[42:Res:46869.0,61.1] always3(s6) || -> . % 76.04/76.23 46874[42:SSi:46873.0,695.0] || -> . % 76.04/76.23 46875[40:Spt:46874.0,45227.2,45228.0] || xuntil6(s4)*+ -> . % 76.04/76.23 46876[40:Spt:46874.0,45227.0,45227.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.23 46877[40:Res:53.1,46876.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.23 46879[41:Spt:46877.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.23 46881[41:Res:46879.0,61.1] always3(s4) || -> . % 76.04/76.23 46882[41:SSi:46881.0,693.0,45226.0] || -> . % 76.04/76.23 46883[41:Spt:46882.0,46877.0,46879.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.23 46884[41:Spt:46882.0,46877.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.23 46888[41:Res:46884.0,61.1] always3(s5) || -> . % 76.04/76.23 46889[41:SSi:46888.0,694.0] || -> . % 76.04/76.23 46890[39:Spt:46889.0,45221.2,45225.0] || xuntil6(s3)*+ -> . % 76.04/76.23 46891[39:Spt:46889.0,45221.0,45221.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.23 46892[39:Res:53.1,46891.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.23 46897[40:Spt:46892.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.23 46899[40:Res:46897.0,61.1] always3(s3) || -> . % 76.04/76.23 46900[40:SSi:46899.0,692.0,45220.0] || -> . % 76.04/76.23 46901[40:Spt:46900.0,46892.0,46897.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.23 46902[40:Spt:46900.0,46892.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.23 46906[40:Res:46902.0,61.1] always3(s4) || -> . % 76.04/76.23 46907[40:SSi:46906.0,693.0] || -> . % 76.04/76.23 46908[38:Spt:46907.0,45218.2,45219.0] || xuntil6(s2)*+ -> . % 76.04/76.23 46909[38:Spt:46907.0,45218.0,45218.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.23 46910[38:Res:53.1,46909.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.23 46912[39:Spt:46910.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.23 46914[39:Res:46912.0,61.1] always3(s2) || -> . % 76.04/76.23 46915[39:SSi:46914.0,691.0,45217.0] || -> . % 76.04/76.23 46916[39:Spt:46915.0,46910.0,46912.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.23 46917[39:Spt:46915.0,46910.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.23 46921[39:Res:46917.0,61.1] always3(s3) || -> . % 76.04/76.23 46922[39:SSi:46921.0,692.0] || -> . % 76.04/76.23 46923[37:Spt:46922.0,45209.2,45216.0] || xuntil6(s1)*+ -> . % 76.04/76.23 46924[37:Spt:46922.0,45209.0,45209.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.23 46925[37:Res:53.1,46924.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.23 46927[38:Spt:46925.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.23 46929[38:Res:46927.0,61.1] always3(s1) || -> . % 76.04/76.23 46930[38:SSi:46929.0,690.0,45208.0] || -> . % 76.04/76.23 46931[38:Spt:46930.0,46925.0,46927.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.23 46932[38:Spt:46930.0,46925.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.23 46937[38:Res:46932.0,61.1] always3(s2) || -> . % 76.04/76.23 46938[38:SSi:46937.0,691.0] || -> . % 76.04/76.23 46939[36:Spt:46938.0,74.0,45207.0] || xuntil6(s0)*+ -> . % 76.04/76.23 46940[36:Spt:46938.0,74.1] || -> node4(s0)*. % 76.04/76.23 46941[36:MRR:758.1,46939.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.23 46943[36:Res:46941.0,61.1] always3(s1) || -> . % 76.04/76.23 46944[36:SSi:46943.0,690.0] || -> . % 76.04/76.23 46945[35:Spt:46944.0,45197.0,45201.0] || trans(s49,s16)*+ -> . % 76.04/76.23 46946[35:Spt:46944.0,45197.1,45197.2,45197.3,45197.4,45197.5,45197.6,45197.7,45197.8,45197.9,45197.10,45197.11,45197.12,45197.13,45197.14,45197.15,45197.16] || -> trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.23 46948[35:MRR:45198.0,46945.0] || -> trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.23 46949[35:MRR:45200.1,46945.0] xuntil6(s49) || -> trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.23 46950[36:Spt:46946.0] || -> trans(s49,s15)*. % 76.04/76.23 46951[36:Res:46950.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s15)*. % 76.04/76.23 46953[36:Res:46950.0,60.0] || -> node2(s49,s15)*. % 76.04/76.23 46954[36:SSi:46951.1,50.0,738.0] xuntil6(s49) || -> until2p7(s15)*. % 76.04/76.23 46955[36:Res:46953.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)*. % 76.04/76.23 46956[37:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.23 46957[37:MRR:176.0,46956.0] || -> until5(s1)*. % 76.04/76.23 46958[37:MRR:45652.0,46957.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.23 46962[38:Spt:46958.2] || -> xuntil6(s1)*. % 76.04/76.23 46963[38:MRR:175.0,46962.0] || -> until5(s2)*. % 76.04/76.23 46964[38:MRR:45648.0,46963.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.23 46968[39:Spt:46964.2] || -> xuntil6(s2)*. % 76.04/76.23 46969[39:MRR:174.0,46968.0] || -> until5(s3)*. % 76.04/76.23 46970[39:MRR:45644.0,46969.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.23 46971[40:Spt:46970.2] || -> xuntil6(s3)*. % 76.04/76.23 46972[40:MRR:173.0,46971.0] || -> until5(s4)*. % 76.04/76.23 46973[40:MRR:45643.0,46972.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.23 46977[41:Spt:46973.2] || -> xuntil6(s4)*. % 76.04/76.23 46978[41:MRR:172.0,46977.0] || -> until5(s5)*. % 76.04/76.23 46979[41:MRR:45636.0,46978.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.23 46980[42:Spt:46979.2] || -> xuntil6(s5)*. % 76.04/76.23 46981[42:MRR:171.0,46980.0] || -> until5(s6)*. % 76.04/76.23 46982[42:MRR:45632.0,46981.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.23 46986[43:Spt:46982.2] || -> xuntil6(s6)*. % 76.04/76.23 46987[43:MRR:170.0,46986.0] || -> until5(s7)*. % 76.04/76.23 46988[43:MRR:45628.0,46987.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.23 46989[44:Spt:46988.2] || -> xuntil6(s7)*. % 76.04/76.23 46990[44:MRR:169.0,46989.0] || -> until5(s8)*. % 76.04/76.23 46991[44:MRR:45624.0,46990.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.23 46995[45:Spt:46991.2] || -> xuntil6(s8)*. % 76.04/76.23 46996[45:MRR:168.0,46995.0] || -> until5(s9)*. % 76.04/76.23 46997[45:MRR:45623.0,46996.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.23 46998[46:Spt:46997.2] || -> xuntil6(s9)*. % 76.04/76.23 46999[46:MRR:167.0,46998.0] || -> until5(s10)*. % 76.04/76.23 47000[46:MRR:45616.0,46999.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.23 47004[47:Spt:47000.2] || -> xuntil6(s10)*. % 76.04/76.23 47005[47:MRR:166.0,47004.0] || -> until5(s11)*. % 76.04/76.23 47006[47:MRR:45612.0,47005.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.23 47007[48:Spt:47006.2] || -> xuntil6(s11)*. % 76.04/76.23 47008[48:MRR:165.0,47007.0] || -> until5(s12)*. % 76.04/76.23 47009[48:MRR:45608.0,47008.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.23 47013[49:Spt:47009.2] || -> xuntil6(s12)*. % 76.04/76.23 47014[49:MRR:164.0,47013.0] || -> until5(s13)*. % 76.04/76.23 47015[49:MRR:45604.0,47014.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.23 47016[50:Spt:47015.2] || -> xuntil6(s13)*. % 76.04/76.23 47017[50:MRR:163.0,47016.0] || -> until5(s14)*. % 76.04/76.23 47018[50:MRR:45603.0,47017.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.23 47022[51:Spt:47018.2] || -> xuntil6(s14)*. % 76.04/76.23 47023[51:MRR:162.0,47022.0] || -> until5(s15)*. % 76.04/76.23 47024[51:MRR:45596.0,47023.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.23 47025[52:Spt:47024.2] || -> xuntil6(s15)*. % 76.04/76.23 47026[52:MRR:161.0,47025.0] || -> until5(s16)*. % 76.04/76.23 47027[52:MRR:45592.0,47026.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.23 47031[53:Spt:47027.2] || -> xuntil6(s16)*. % 76.04/76.23 47032[53:MRR:160.0,47031.0] || -> until5(s17)*. % 76.04/76.23 47033[53:MRR:45585.0,47032.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.23 47034[54:Spt:47033.2] || -> xuntil6(s17)*. % 76.04/76.23 47035[54:MRR:159.0,47034.0] || -> until5(s18)*. % 76.04/76.23 47036[54:MRR:45584.0,47035.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.23 47040[55:Spt:47036.2] || -> xuntil6(s18)*. % 76.04/76.23 47041[55:MRR:158.0,47040.0] || -> until5(s19)*. % 76.04/76.23 47042[55:MRR:45583.0,47041.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.23 47043[56:Spt:47042.2] || -> xuntil6(s19)*. % 76.04/76.23 47044[56:MRR:157.0,47043.0] || -> until5(s20)*. % 76.04/76.23 47045[56:MRR:45573.0,47044.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.23 47049[57:Spt:47045.2] || -> xuntil6(s20)*. % 76.04/76.23 47050[57:MRR:156.0,47049.0] || -> until5(s21)*. % 76.04/76.23 47051[57:MRR:45572.0,47050.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.23 47052[58:Spt:47051.2] || -> xuntil6(s21)*. % 76.04/76.23 47053[58:MRR:155.0,47052.0] || -> until5(s22)*. % 76.04/76.23 47054[58:MRR:45565.0,47053.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.23 47058[59:Spt:47054.2] || -> xuntil6(s22)*. % 76.04/76.23 47059[59:MRR:154.0,47058.0] || -> until5(s23)*. % 76.04/76.23 47060[59:MRR:45561.0,47059.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.23 47061[60:Spt:47060.2] || -> xuntil6(s23)*. % 76.04/76.23 47062[60:MRR:153.0,47061.0] || -> until5(s24)*. % 76.04/76.23 47063[60:MRR:45557.0,47062.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.23 47067[61:Spt:47063.2] || -> xuntil6(s24)*. % 76.04/76.23 47068[61:MRR:152.0,47067.0] || -> until5(s25)*. % 76.04/76.23 47069[61:MRR:45556.0,47068.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.23 47070[62:Spt:47069.2] || -> xuntil6(s25)*. % 76.04/76.23 47071[62:MRR:151.0,47070.0] || -> until5(s26)*. % 76.04/76.23 47072[62:MRR:45555.0,47071.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.23 47076[63:Spt:47072.2] || -> xuntil6(s26)*. % 76.04/76.23 47077[63:MRR:150.0,47076.0] || -> until5(s27)*. % 76.04/76.23 47078[63:MRR:45554.0,47077.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.23 47079[64:Spt:47078.2] || -> xuntil6(s27)*. % 76.04/76.23 47080[64:MRR:149.0,47079.0] || -> until5(s28)*. % 76.04/76.23 47081[64:MRR:45550.0,47080.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.23 47085[65:Spt:47081.2] || -> xuntil6(s28)*. % 76.04/76.23 47086[65:MRR:148.0,47085.0] || -> until5(s29)*. % 76.04/76.23 47087[65:MRR:35647.0,47086.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.23 47088[66:Spt:47087.2] || -> xuntil6(s29)*. % 76.04/76.23 47089[66:MRR:147.0,47088.0] || -> until5(s30)*. % 76.04/76.23 47090[66:MRR:45659.0,47089.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.23 47094[67:Spt:47090.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.23 47096[67:Res:47094.0,61.1] always3(s31) || -> . % 76.04/76.23 47097[67:SSi:47096.0,720.0] || -> . % 76.04/76.23 47098[67:Spt:47097.0,47090.1,47094.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.04/76.23 47099[67:Spt:47097.0,47090.0,47090.2] || m_main_v_state(s30,c_ready)*+ -> xuntil6(s30). % 76.04/76.23 47101[67:MRR:828.2,47098.0] node4(s30) || m_main_v_state(s30,c_ready)* -> . % 76.04/76.23 47102[67:Res:53.1,47099.0] || -> m_main_v_state(s30,c_busy)* xuntil6(s30). % 76.04/76.23 47104[68:Spt:47102.1] || -> xuntil6(s30)*. % 76.04/76.23 47105[68:MRR:146.0,47104.0] || -> until5(s31)*. % 76.04/76.23 47106[68:MRR:35651.0,47105.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.23 47111[69:Spt:47106.2] || -> xuntil6(s31)*. % 76.04/76.23 47112[69:MRR:145.0,47111.0] || -> until5(s32)*. % 76.04/76.23 47113[69:MRR:45663.0,47112.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.23 47114[70:Spt:47113.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.23 47116[70:Res:47114.0,61.1] always3(s33) || -> . % 76.04/76.23 47117[70:SSi:47116.0,722.0] || -> . % 76.04/76.23 47118[70:Spt:47117.0,47113.1,47114.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.04/76.23 47119[70:Spt:47117.0,47113.0,47113.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 76.04/76.23 47121[70:MRR:822.2,47118.0] node4(s32) || m_main_v_state(s32,c_ready)* -> . % 76.04/76.23 47122[70:Res:53.1,47119.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 76.04/76.23 47124[71:Spt:47122.1] || -> xuntil6(s32)*. % 76.04/76.23 47125[71:MRR:144.0,47124.0] || -> until5(s33)*. % 76.04/76.23 47126[71:MRR:35655.0,47125.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.23 47134[72:Spt:47126.2] || -> xuntil6(s33)*. % 76.04/76.23 47135[72:MRR:143.0,47134.0] || -> until5(s34)*. % 76.04/76.23 47136[72:MRR:45667.0,47135.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.23 47137[73:Spt:47136.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.23 47139[73:Res:47137.0,61.1] always3(s35) || -> . % 76.04/76.23 47140[73:SSi:47139.0,724.0] || -> . % 76.04/76.23 47141[73:Spt:47140.0,47136.1,47137.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.04/76.23 47142[73:Spt:47140.0,47136.0,47136.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 76.04/76.23 47144[73:MRR:816.2,47141.0] node4(s34) || m_main_v_state(s34,c_ready)* -> . % 76.04/76.23 47145[73:Res:53.1,47142.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 76.04/76.23 47150[74:Spt:47145.1] || -> xuntil6(s34)*. % 76.04/76.23 47151[74:MRR:142.0,47150.0] || -> until5(s35)*. % 76.04/76.23 47152[74:MRR:35659.0,47151.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.23 47154[75:Spt:47152.2] || -> xuntil6(s35)*. % 76.04/76.23 47155[75:MRR:141.0,47154.0] || -> until5(s36)*. % 76.04/76.23 47156[75:MRR:45674.0,47155.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.23 47157[76:Spt:47156.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.23 47159[76:Res:47157.0,61.1] always3(s37) || -> . % 76.04/76.23 47160[76:SSi:47159.0,726.0] || -> . % 76.04/76.23 47161[76:Spt:47160.0,47156.1,47157.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.04/76.23 47162[76:Spt:47160.0,47156.0,47156.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 76.04/76.23 47164[76:MRR:810.2,47161.0] node4(s36) || m_main_v_state(s36,c_ready)* -> . % 76.04/76.23 47165[76:Res:53.1,47162.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 76.04/76.23 47167[77:Spt:47165.1] || -> xuntil6(s36)*. % 76.04/76.23 47168[77:MRR:140.0,47167.0] || -> until5(s37)*. % 76.04/76.23 47169[77:MRR:35666.0,47168.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.23 47174[78:Spt:47169.2] || -> xuntil6(s37)*. % 76.04/76.23 47175[78:MRR:139.0,47174.0] || -> until5(s38)*. % 76.04/76.23 47176[78:MRR:45675.0,47175.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.23 47177[79:Spt:47176.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.23 47179[79:Res:47177.0,61.1] always3(s39) || -> . % 76.04/76.23 47180[79:SSi:47179.0,728.0] || -> . % 76.04/76.23 47181[79:Spt:47180.0,47176.1,47177.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.04/76.23 47182[79:Spt:47180.0,47176.0,47176.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 76.04/76.23 47184[79:MRR:804.2,47181.0] node4(s38) || m_main_v_state(s38,c_ready)* -> . % 76.04/76.23 47185[79:Res:53.1,47182.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 76.04/76.23 47187[80:Spt:47185.1] || -> xuntil6(s38)*. % 76.04/76.23 47188[80:MRR:138.0,47187.0] || -> until5(s39)*. % 76.04/76.23 47189[80:MRR:35667.0,47188.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.23 47197[81:Spt:47189.2] || -> xuntil6(s39)*. % 76.04/76.23 47198[81:MRR:137.0,47197.0] || -> until5(s40)*. % 76.04/76.23 47199[81:MRR:45679.0,47198.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.23 47200[82:Spt:47199.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.23 47202[82:Res:47200.0,61.1] always3(s41) || -> . % 76.04/76.23 47203[82:SSi:47202.0,730.0] || -> . % 76.04/76.23 47204[82:Spt:47203.0,47199.1,47200.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.04/76.23 47205[82:Spt:47203.0,47199.0,47199.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 76.04/76.23 47207[82:MRR:798.2,47204.0] node4(s40) || m_main_v_state(s40,c_ready)* -> . % 76.04/76.23 47208[82:Res:53.1,47205.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 76.04/76.23 47213[83:Spt:47208.1] || -> xuntil6(s40)*. % 76.04/76.23 47214[83:MRR:136.0,47213.0] || -> until5(s41)*. % 76.04/76.23 47215[83:MRR:35671.0,47214.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.23 47217[84:Spt:47215.2] || -> xuntil6(s41)*. % 76.04/76.23 47218[84:MRR:135.0,47217.0] || -> until5(s42)*. % 76.04/76.23 47219[84:MRR:45683.0,47218.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.23 47220[85:Spt:47219.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.23 47222[85:Res:47220.0,61.1] always3(s43) || -> . % 76.04/76.23 47223[85:SSi:47222.0,732.0] || -> . % 76.04/76.23 47224[85:Spt:47223.0,47219.1,47220.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.04/76.23 47225[85:Spt:47223.0,47219.0,47219.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 76.04/76.23 47227[85:MRR:792.2,47224.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 76.04/76.23 47228[85:Res:53.1,47225.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 76.04/76.23 47230[86:Spt:47228.1] || -> xuntil6(s42)*. % 76.04/76.23 47231[86:MRR:134.0,47230.0] || -> until5(s43)*. % 76.04/76.23 47232[86:MRR:35675.0,47231.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.23 47237[87:Spt:47232.2] || -> xuntil6(s43)*. % 76.04/76.23 47238[87:MRR:133.0,47237.0] || -> until5(s44)*. % 76.04/76.23 47239[87:MRR:45687.0,47238.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.23 47240[88:Spt:47239.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.23 47242[88:Res:47240.0,61.1] always3(s45) || -> . % 76.04/76.23 47243[88:SSi:47242.0,734.0] || -> . % 76.04/76.23 47244[88:Spt:47243.0,47239.1,47240.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.04/76.23 47245[88:Spt:47243.0,47239.0,47239.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 76.04/76.23 47247[88:MRR:786.2,47244.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 76.04/76.23 47248[88:Res:53.1,47245.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 76.04/76.23 47250[89:Spt:47248.1] || -> xuntil6(s44)*. % 76.04/76.23 47251[89:MRR:132.0,47250.0] || -> until5(s45)*. % 76.04/76.23 47252[89:MRR:35679.0,47251.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.23 47260[90:Spt:47252.2] || -> xuntil6(s45)*. % 76.04/76.23 47261[90:MRR:131.0,47260.0] || -> until5(s46)*. % 76.04/76.23 47262[90:MRR:45694.0,47261.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.23 47263[91:Spt:47262.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.23 47265[91:Res:47263.0,61.1] always3(s47) || -> . % 76.04/76.23 47266[91:SSi:47265.0,736.0] || -> . % 76.04/76.23 47267[91:Spt:47266.0,47262.1,47263.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.04/76.23 47268[91:Spt:47266.0,47262.0,47262.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 76.04/76.23 47270[91:MRR:780.2,47267.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 76.04/76.23 47271[91:Res:53.1,47268.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 76.04/76.23 47276[92:Spt:47271.1] || -> xuntil6(s46)*. % 76.04/76.23 47277[92:MRR:130.0,47276.0] || -> until5(s47)*. % 76.04/76.23 47278[92:MRR:35683.0,47277.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.23 47280[93:Spt:47278.2] || -> xuntil6(s47)*. % 76.04/76.23 47281[93:MRR:129.0,47280.0] || -> until5(s48)*. % 76.04/76.23 47282[93:MRR:45695.0,47281.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.23 47283[94:Spt:47282.1] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.23 47285[94:Res:47283.0,61.1] always3(s49) || -> . % 76.04/76.23 47286[94:SSi:47285.0,50.0,738.0] || -> . % 76.04/76.23 47287[94:Spt:47286.0,47282.1,47283.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.23 47288[94:Spt:47286.0,47282.0,47282.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 76.04/76.23 47290[94:MRR:774.2,47287.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.23 47291[94:Res:53.1,47288.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 76.04/76.23 47293[95:Spt:47291.1] || -> xuntil6(s48)*. % 76.04/76.23 47294[95:MRR:128.0,47293.0] || -> until5(s49)*. % 76.04/76.23 47299[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.23 47300[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.23 47301[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.23 47305[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.23 47306[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.23 47307[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.23 47314[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.23 47315[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.23 47319[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.23 47326[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.23 47327[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.23 47334[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.23 47335[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.23 47345[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.23 47346[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.23 47350[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.23 47354[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.23 47358[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.23 47365[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.23 47366[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.23 47370[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.23 47374[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.23 47378[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.23 47385[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.23 47386[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.23 47390[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.23 47394[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.23 47398[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.23 47405[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.23 47406[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.23 47410[0:SoR:819.0,66.2] until5(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.23 47414[0:SoR:813.0,66.2] until5(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.23 47418[0:SoR:807.0,66.2] until5(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.23 47425[0:SoR:801.0,66.2] until5(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.23 47426[0:SoR:795.0,66.2] until5(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.23 47430[0:SoR:789.0,66.2] until5(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.23 47434[0:SoR:783.0,66.2] until5(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.23 47438[0:SoR:777.0,66.2] until5(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.23 47440[36:SoR:46955.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)*. % 76.04/76.23 47442[36:SoR:47440.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)* xuntil6(s49). % 76.04/76.23 47443[95:SSi:47442.0,50.0,738.0,47294.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s15,c_busy)* xuntil6(s49). % 76.04/76.23 47444[96:Spt:47443.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.23 47446[96:Res:47444.0,61.1] always3(s15) || -> . % 76.04/76.23 47447[96:SSi:47446.0,704.0,47023.0,47025.0] || -> . % 76.04/76.23 47448[96:Spt:47447.0,47443.1,47444.0] || m_main_v_state(s15,c_busy)*+ -> . % 76.04/76.23 47449[96:Spt:47447.0,47443.0,47443.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.23 47453[96:MRR:47440.2,47448.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.23 47454[96:Res:53.1,47449.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.23 47456[96:MRR:47454.0,47287.0] || -> xuntil6(s49)*. % 76.04/76.23 47457[96:MRR:46954.0,47456.0] || -> until2p7(s15)*. % 76.04/76.23 47458[96:MRR:211.0,47457.0] || -> until2p7(s16)* node4(s15). % 76.04/76.23 47459[97:Spt:47458.0] || -> until2p7(s16)*. % 76.04/76.23 47460[97:MRR:212.0,47459.0] || -> until2p7(s17)* node4(s16). % 76.04/76.23 47461[98:Spt:47460.0] || -> until2p7(s17)*. % 76.04/76.23 47462[98:MRR:213.0,47461.0] || -> until2p7(s18)* node4(s17). % 76.04/76.23 47463[99:Spt:47462.0] || -> until2p7(s18)*. % 76.04/76.23 47464[99:MRR:214.0,47463.0] || -> until2p7(s19)* node4(s18). % 76.04/76.23 47465[100:Spt:47464.0] || -> until2p7(s19)*. % 76.04/76.23 47466[100:MRR:215.0,47465.0] || -> until2p7(s20)* node4(s19). % 76.04/76.23 47467[101:Spt:47466.0] || -> until2p7(s20)*. % 76.04/76.23 47468[101:MRR:216.0,47467.0] || -> until2p7(s21)* node4(s20). % 76.04/76.23 47469[102:Spt:47468.0] || -> until2p7(s21)*. % 76.04/76.23 47470[102:MRR:217.0,47469.0] || -> until2p7(s22)* node4(s21). % 76.04/76.23 47471[103:Spt:47470.0] || -> until2p7(s22)*. % 76.04/76.23 47472[103:MRR:218.0,47471.0] || -> until2p7(s23)* node4(s22). % 76.04/76.23 47473[104:Spt:47472.0] || -> until2p7(s23)*. % 76.04/76.23 47474[104:MRR:219.0,47473.0] || -> until2p7(s24)* node4(s23). % 76.04/76.23 47475[105:Spt:47474.0] || -> until2p7(s24)*. % 76.04/76.23 47476[105:MRR:220.0,47475.0] || -> until2p7(s25)* node4(s24). % 76.04/76.23 47477[106:Spt:47476.0] || -> until2p7(s25)*. % 76.04/76.23 47478[106:MRR:221.0,47477.0] || -> until2p7(s26)* node4(s25). % 76.04/76.23 47479[107:Spt:47478.0] || -> until2p7(s26)*. % 76.04/76.23 47480[107:MRR:222.0,47479.0] || -> until2p7(s27)* node4(s26). % 76.04/76.23 47481[108:Spt:47480.0] || -> until2p7(s27)*. % 76.04/76.23 47482[108:MRR:223.0,47481.0] || -> until2p7(s28)* node4(s27). % 76.04/76.23 47483[109:Spt:47482.0] || -> until2p7(s28)*. % 76.04/76.23 47484[109:MRR:224.0,47483.0] || -> until2p7(s29)* node4(s28). % 76.04/76.23 47485[110:Spt:47484.0] || -> until2p7(s29)*. % 76.04/76.23 47486[110:MRR:225.0,47485.0] || -> until2p7(s30)* node4(s29). % 76.04/76.23 47487[111:Spt:47486.0] || -> until2p7(s30)*. % 76.04/76.23 47488[111:MRR:226.0,47487.0] || -> until2p7(s31)* node4(s30). % 76.04/76.23 47489[112:Spt:47488.0] || -> until2p7(s31)*. % 76.04/76.23 47490[112:MRR:227.0,47489.0] || -> until2p7(s32)* node4(s31). % 76.04/76.23 47491[113:Spt:47490.0] || -> until2p7(s32)*. % 76.04/76.23 47492[113:MRR:228.0,47491.0] || -> until2p7(s33)* node4(s32). % 76.04/76.23 47493[114:Spt:47492.0] || -> until2p7(s33)*. % 76.04/76.23 47494[114:MRR:229.0,47493.0] || -> until2p7(s34)* node4(s33). % 76.04/76.23 47495[115:Spt:47494.0] || -> until2p7(s34)*. % 76.04/76.23 47496[115:MRR:230.0,47495.0] || -> until2p7(s35)* node4(s34). % 76.04/76.23 47497[116:Spt:47496.0] || -> until2p7(s35)*. % 76.04/76.23 47498[116:MRR:231.0,47497.0] || -> until2p7(s36)* node4(s35). % 76.04/76.23 47499[117:Spt:47498.0] || -> until2p7(s36)*. % 76.04/76.23 47500[117:MRR:232.0,47499.0] || -> until2p7(s37)* node4(s36). % 76.04/76.23 47501[118:Spt:47500.0] || -> until2p7(s37)*. % 76.04/76.23 47502[118:MRR:235.0,47501.0] || -> until2p7(s38)* node4(s37). % 76.04/76.23 47503[119:Spt:47502.0] || -> until2p7(s38)*. % 76.04/76.23 47504[119:MRR:236.0,47503.0] || -> until2p7(s39)* node4(s38). % 76.04/76.23 47505[120:Spt:47504.0] || -> until2p7(s39)*. % 76.04/76.23 47506[120:MRR:237.0,47505.0] || -> until2p7(s40)* node4(s39). % 76.04/76.23 47507[121:Spt:47506.0] || -> until2p7(s40)*. % 76.04/76.23 47508[121:MRR:238.0,47507.0] || -> until2p7(s41)* node4(s40). % 76.04/76.23 47509[122:Spt:47508.0] || -> until2p7(s41)*. % 76.04/76.23 47510[122:MRR:239.0,47509.0] || -> until2p7(s42)* node4(s41). % 76.04/76.23 47511[123:Spt:47510.0] || -> until2p7(s42)*. % 76.04/76.23 47512[123:MRR:240.0,47511.0] || -> until2p7(s43)* node4(s42). % 76.04/76.23 47513[124:Spt:47512.0] || -> until2p7(s43)*. % 76.04/76.23 47514[124:MRR:241.0,47513.0] || -> until2p7(s44)* node4(s43). % 76.04/76.23 47515[125:Spt:47514.0] || -> until2p7(s44)*. % 76.04/76.23 47516[125:MRR:539.0,47515.0] || -> until2p7(s45)* node4(s44). % 76.04/76.23 47517[126:Spt:47516.0] || -> until2p7(s45)*. % 76.04/76.23 47518[126:MRR:544.0,47517.0] || -> until2p7(s46)* node4(s45). % 76.04/76.23 47519[127:Spt:47518.0] || -> until2p7(s46)*. % 76.04/76.23 47520[127:MRR:549.0,47519.0] || -> until2p7(s47)* node4(s46). % 76.04/76.23 47521[128:Spt:47520.0] || -> until2p7(s47)*. % 76.04/76.23 47522[128:MRR:554.0,47521.0] || -> until2p7(s48)* node4(s47). % 76.04/76.23 47523[129:Spt:47522.0] || -> until2p7(s48)*. % 76.04/76.23 47524[129:MRR:559.0,47523.0] || -> until2p7(s49)* node4(s48). % 76.04/76.23 47525[130:Spt:47524.0] || -> until2p7(s49)*. % 76.04/76.23 47526[130:MRR:194.0,47525.0] || -> node4(s49)*. % 76.04/76.23 47527[130:MRR:47453.0,47526.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.23 47531[130:Res:53.1,47527.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.23 47533[130:MRR:47531.0,47287.0] || -> . % 76.04/76.23 47534[130:Spt:47533.0,47524.0,47525.0] || until2p7(s49)*+ -> . % 76.04/76.23 47535[130:Spt:47533.0,47524.1] || -> node4(s48)*. % 76.04/76.23 47536[130:MRR:47290.0,47535.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.23 47539[130:Res:53.1,47536.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.23 47542[130:Res:47539.0,61.1] always3(s48) || -> . % 76.04/76.23 47543[130:SSi:47542.0,737.0,47281.0,47293.0,47523.0,47535.0] || -> . % 76.04/76.23 47544[129:Spt:47543.0,47522.0,47523.0] || until2p7(s48)*+ -> . % 76.04/76.23 47545[129:Spt:47543.0,47522.1] || -> node4(s47)*. % 76.04/76.23 47547[129:MRR:777.0,47545.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.23 47559[129:Res:53.1,47547.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.23 47561[129:MRR:47559.0,47267.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.23 47563[129:Res:47561.0,61.1] always3(s48) || -> . % 76.04/76.23 47564[129:SSi:47563.0,737.0,47281.0,47293.0] || -> . % 76.04/76.23 47565[128:Spt:47564.0,47520.0,47521.0] || until2p7(s47)*+ -> . % 76.04/76.23 47566[128:Spt:47564.0,47520.1] || -> node4(s46)*. % 76.04/76.23 47567[128:MRR:47270.0,47566.0] || m_main_v_state(s46,c_ready)*+ -> . % 76.04/76.23 47571[128:Res:53.1,47567.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.23 47574[128:Res:47571.0,61.1] always3(s46) || -> . % 76.04/76.23 47575[128:SSi:47574.0,735.0,47261.0,47276.0,47519.0,47566.0] || -> . % 76.04/76.23 47576[127:Spt:47575.0,47518.0,47519.0] || until2p7(s46)*+ -> . % 76.04/76.23 47577[127:Spt:47575.0,47518.1] || -> node4(s45)*. % 76.04/76.23 47579[127:MRR:783.0,47577.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.23 47590[127:Res:53.1,47579.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.23 47592[127:MRR:47590.0,47244.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.23 47594[127:Res:47592.0,61.1] always3(s46) || -> . % 76.04/76.23 47595[127:SSi:47594.0,735.0,47261.0,47276.0] || -> . % 76.04/76.23 47596[126:Spt:47595.0,47516.0,47517.0] || until2p7(s45)*+ -> . % 76.04/76.23 47597[126:Spt:47595.0,47516.1] || -> node4(s44)*. % 76.04/76.23 47598[126:MRR:47247.0,47597.0] || m_main_v_state(s44,c_ready)*+ -> . % 76.04/76.23 47601[126:Res:53.1,47598.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.23 47604[126:Res:47601.0,61.1] always3(s44) || -> . % 76.04/76.23 47605[126:SSi:47604.0,733.0,47238.0,47250.0,47515.0,47597.0] || -> . % 76.04/76.23 47606[125:Spt:47605.0,47514.0,47515.0] || until2p7(s44)*+ -> . % 76.04/76.23 47607[125:Spt:47605.0,47514.1] || -> node4(s43)*. % 76.04/76.23 47609[125:MRR:789.0,47607.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.23 47621[125:Res:53.1,47609.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.23 47623[125:MRR:47621.0,47224.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.23 47625[125:Res:47623.0,61.1] always3(s44) || -> . % 76.04/76.23 47626[125:SSi:47625.0,733.0,47238.0,47250.0] || -> . % 76.04/76.23 47627[124:Spt:47626.0,47512.0,47513.0] || until2p7(s43)*+ -> . % 76.04/76.23 47628[124:Spt:47626.0,47512.1] || -> node4(s42)*. % 76.04/76.23 47629[124:MRR:47227.0,47628.0] || m_main_v_state(s42,c_ready)*+ -> . % 76.04/76.23 47632[124:Res:53.1,47629.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.23 47635[124:Res:47632.0,61.1] always3(s42) || -> . % 76.04/76.23 47636[124:SSi:47635.0,731.0,47218.0,47230.0,47511.0,47628.0] || -> . % 76.04/76.23 47637[123:Spt:47636.0,47510.0,47511.0] || until2p7(s42)*+ -> . % 76.04/76.23 47638[123:Spt:47636.0,47510.1] || -> node4(s41)*. % 76.04/76.23 47640[123:MRR:795.0,47638.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.23 47652[123:Res:53.1,47640.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.23 47654[123:MRR:47652.0,47204.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.23 47659[123:Res:47654.0,61.1] always3(s42) || -> . % 76.04/76.23 47660[123:SSi:47659.0,731.0,47218.0,47230.0] || -> . % 76.04/76.23 47661[122:Spt:47660.0,47508.0,47509.0] || until2p7(s41)*+ -> . % 76.04/76.23 47662[122:Spt:47660.0,47508.1] || -> node4(s40)*. % 76.04/76.23 47663[122:MRR:47207.0,47662.0] || m_main_v_state(s40,c_ready)*+ -> . % 76.04/76.23 47666[122:Res:53.1,47663.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.23 47670[122:Res:47666.0,61.1] always3(s40) || -> . % 76.04/76.23 47671[122:SSi:47670.0,729.0,47198.0,47213.0,47507.0,47662.0] || -> . % 76.04/76.23 47672[121:Spt:47671.0,47506.0,47507.0] || until2p7(s40)*+ -> . % 76.04/76.23 47673[121:Spt:47671.0,47506.1] || -> node4(s39)*. % 76.04/76.23 47675[121:MRR:801.0,47673.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.23 47686[121:Res:53.1,47675.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.23 47688[121:MRR:47686.0,47181.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.23 47690[121:Res:47688.0,61.1] always3(s40) || -> . % 76.04/76.23 47691[121:SSi:47690.0,729.0,47198.0,47213.0] || -> . % 76.04/76.23 47692[120:Spt:47691.0,47504.0,47505.0] || until2p7(s39)*+ -> . % 76.04/76.23 47693[120:Spt:47691.0,47504.1] || -> node4(s38)*. % 76.04/76.23 47694[120:MRR:47184.0,47693.0] || m_main_v_state(s38,c_ready)*+ -> . % 76.04/76.23 47698[120:Res:53.1,47694.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.23 47701[120:Res:47698.0,61.1] always3(s38) || -> . % 76.04/76.23 47702[120:SSi:47701.0,727.0,47175.0,47187.0,47503.0,47693.0] || -> . % 76.04/76.23 47703[119:Spt:47702.0,47502.0,47503.0] || until2p7(s38)*+ -> . % 76.04/76.23 47704[119:Spt:47702.0,47502.1] || -> node4(s37)*. % 76.04/76.23 47706[119:MRR:807.0,47704.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.23 47717[119:Res:53.1,47706.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.23 47719[119:MRR:47717.0,47161.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.23 47721[119:Res:47719.0,61.1] always3(s38) || -> . % 76.04/76.23 47722[119:SSi:47721.0,727.0,47175.0,47187.0] || -> . % 76.04/76.23 47723[118:Spt:47722.0,47500.0,47501.0] || until2p7(s37)*+ -> . % 76.04/76.23 47724[118:Spt:47722.0,47500.1] || -> node4(s36)*. % 76.04/76.23 47725[118:MRR:47164.0,47724.0] || m_main_v_state(s36,c_ready)*+ -> . % 76.04/76.23 47728[118:Res:53.1,47725.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.23 47731[118:Res:47728.0,61.1] always3(s36) || -> . % 76.04/76.23 47732[118:SSi:47731.0,725.0,47155.0,47167.0,47499.0,47724.0] || -> . % 76.04/76.23 47733[117:Spt:47732.0,47498.0,47499.0] || until2p7(s36)*+ -> . % 76.04/76.23 47734[117:Spt:47732.0,47498.1] || -> node4(s35)*. % 76.04/76.23 47736[117:MRR:813.0,47734.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.23 47748[117:Res:53.1,47736.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.23 47750[117:MRR:47748.0,47141.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.23 47752[117:Res:47750.0,61.1] always3(s36) || -> . % 76.04/76.23 47753[117:SSi:47752.0,725.0,47155.0,47167.0] || -> . % 76.04/76.23 47754[116:Spt:47753.0,47496.0,47497.0] || until2p7(s35)*+ -> . % 76.04/76.23 47755[116:Spt:47753.0,47496.1] || -> node4(s34)*. % 76.04/76.23 47756[116:MRR:47144.0,47755.0] || m_main_v_state(s34,c_ready)*+ -> . % 76.04/76.23 47759[116:Res:53.1,47756.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.23 47762[116:Res:47759.0,61.1] always3(s34) || -> . % 76.04/76.23 47763[116:SSi:47762.0,723.0,47135.0,47150.0,47495.0,47755.0] || -> . % 76.04/76.23 47764[115:Spt:47763.0,47494.0,47495.0] || until2p7(s34)*+ -> . % 76.04/76.23 47765[115:Spt:47763.0,47494.1] || -> node4(s33)*. % 76.04/76.23 47767[115:MRR:819.0,47765.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.23 47779[115:Res:53.1,47767.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.23 47781[115:MRR:47779.0,47118.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.23 47786[115:Res:47781.0,61.1] always3(s34) || -> . % 76.04/76.23 47787[115:SSi:47786.0,723.0,47135.0,47150.0] || -> . % 76.04/76.23 47788[114:Spt:47787.0,47492.0,47493.0] || until2p7(s33)*+ -> . % 76.04/76.23 47789[114:Spt:47787.0,47492.1] || -> node4(s32)*. % 76.04/76.23 47790[114:MRR:47121.0,47789.0] || m_main_v_state(s32,c_ready)*+ -> . % 76.04/76.23 47793[114:Res:53.1,47790.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.23 47797[114:Res:47793.0,61.1] always3(s32) || -> . % 76.04/76.23 47798[114:SSi:47797.0,721.0,47112.0,47124.0,47491.0,47789.0] || -> . % 76.04/76.23 47799[113:Spt:47798.0,47490.0,47491.0] || until2p7(s32)*+ -> . % 76.04/76.23 47800[113:Spt:47798.0,47490.1] || -> node4(s31)*. % 76.04/76.23 47802[113:MRR:825.0,47800.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.23 47813[113:Res:53.1,47802.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.23 47815[113:MRR:47813.0,47098.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.23 47817[113:Res:47815.0,61.1] always3(s32) || -> . % 76.04/76.23 47818[113:SSi:47817.0,721.0,47112.0,47124.0] || -> . % 76.04/76.23 47819[112:Spt:47818.0,47488.0,47489.0] || until2p7(s31)*+ -> . % 76.04/76.23 47820[112:Spt:47818.0,47488.1] || -> node4(s30)*. % 76.04/76.23 47821[112:MRR:47101.0,47820.0] || m_main_v_state(s30,c_ready)*+ -> . % 76.04/76.23 47825[112:Res:53.1,47821.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.23 47828[112:Res:47825.0,61.1] always3(s30) || -> . % 76.04/76.23 47829[112:SSi:47828.0,719.0,47089.0,47104.0,47487.0,47820.0] || -> . % 76.04/76.23 47830[111:Spt:47829.0,47486.0,47487.0] || until2p7(s30)*+ -> . % 76.04/76.23 47831[111:Spt:47829.0,47486.1] || -> node4(s29)*. % 76.04/76.23 47833[111:MRR:831.0,47831.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.23 47844[111:Res:53.1,47833.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.23 47846[112:Spt:47844.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.23 47848[112:Res:47846.0,61.1] always3(s29) || -> . % 76.04/76.23 47849[112:SSi:47848.0,718.0,47086.0,47088.0,47485.0,47831.0] || -> . % 76.04/76.23 47850[112:Spt:47849.0,47844.0,47846.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.23 47851[112:Spt:47849.0,47844.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.23 47855[112:Res:47851.0,61.1] always3(s30) || -> . % 76.04/76.23 47856[112:SSi:47855.0,719.0,47089.0,47104.0] || -> . % 76.04/76.23 47857[110:Spt:47856.0,47484.0,47485.0] || until2p7(s29)*+ -> . % 76.04/76.23 47858[110:Spt:47856.0,47484.1] || -> node4(s28)*. % 76.04/76.23 47860[110:MRR:834.0,47858.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.23 47870[110:Res:53.1,47860.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.23 47872[111:Spt:47870.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.23 47874[111:Res:47872.0,61.1] always3(s28) || -> . % 76.04/76.23 47875[111:SSi:47874.0,717.0,47080.0,47085.0,47483.0,47858.0] || -> . % 76.04/76.23 47876[111:Spt:47875.0,47870.0,47872.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.23 47877[111:Spt:47875.0,47870.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.23 47881[111:Res:47877.0,61.1] always3(s29) || -> . % 76.04/76.23 47882[111:SSi:47881.0,718.0,47086.0,47088.0] || -> . % 76.04/76.23 47883[109:Spt:47882.0,47482.0,47483.0] || until2p7(s28)*+ -> . % 76.04/76.23 47884[109:Spt:47882.0,47482.1] || -> node4(s27)*. % 76.04/76.23 47886[109:MRR:837.0,47884.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.23 47889[109:Res:53.1,47886.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.23 47891[110:Spt:47889.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.23 47893[110:Res:47891.0,61.1] always3(s27) || -> . % 76.04/76.23 47894[110:SSi:47893.0,716.0,47077.0,47079.0,47481.0,47884.0] || -> . % 76.04/76.23 47895[110:Spt:47894.0,47889.0,47891.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.23 47896[110:Spt:47894.0,47889.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.23 47900[110:Res:47896.0,61.1] always3(s28) || -> . % 76.04/76.23 47901[110:SSi:47900.0,717.0,47080.0,47085.0] || -> . % 76.04/76.23 47902[108:Spt:47901.0,47480.0,47481.0] || until2p7(s27)*+ -> . % 76.04/76.23 47903[108:Spt:47901.0,47480.1] || -> node4(s26)*. % 76.04/76.23 47905[108:MRR:840.0,47903.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.23 47908[108:Res:53.1,47905.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.23 47910[109:Spt:47908.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.23 47912[109:Res:47910.0,61.1] always3(s26) || -> . % 76.04/76.23 47913[109:SSi:47912.0,715.0,47071.0,47076.0,47479.0,47903.0] || -> . % 76.04/76.23 47914[109:Spt:47913.0,47908.0,47910.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.23 47915[109:Spt:47913.0,47908.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.23 47919[109:Res:47915.0,61.1] always3(s27) || -> . % 76.04/76.23 47920[109:SSi:47919.0,716.0,47077.0,47079.0] || -> . % 76.04/76.23 47921[107:Spt:47920.0,47478.0,47479.0] || until2p7(s26)*+ -> . % 76.04/76.23 47922[107:Spt:47920.0,47478.1] || -> node4(s25)*. % 76.04/76.23 47924[107:MRR:843.0,47922.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.23 47927[107:Res:53.1,47924.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.23 47932[108:Spt:47927.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.23 47934[108:Res:47932.0,61.1] always3(s25) || -> . % 76.04/76.23 47935[108:SSi:47934.0,714.0,47068.0,47070.0,47477.0,47922.0] || -> . % 76.04/76.23 47936[108:Spt:47935.0,47927.0,47932.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.23 47937[108:Spt:47935.0,47927.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.23 47941[108:Res:47937.0,61.1] always3(s26) || -> . % 76.04/76.23 47942[108:SSi:47941.0,715.0,47071.0,47076.0] || -> . % 76.04/76.23 47943[106:Spt:47942.0,47476.0,47477.0] || until2p7(s25)*+ -> . % 76.04/76.23 47944[106:Spt:47942.0,47476.1] || -> node4(s24)*. % 76.04/76.23 47946[106:MRR:846.0,47944.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.23 47949[106:Res:53.1,47946.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.23 47951[107:Spt:47949.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.23 47953[107:Res:47951.0,61.1] always3(s24) || -> . % 76.04/76.23 47954[107:SSi:47953.0,713.0,47062.0,47067.0,47475.0,47944.0] || -> . % 76.04/76.23 47955[107:Spt:47954.0,47949.0,47951.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.23 47956[107:Spt:47954.0,47949.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.23 47960[107:Res:47956.0,61.1] always3(s25) || -> . % 76.04/76.23 47961[107:SSi:47960.0,714.0,47068.0,47070.0] || -> . % 76.04/76.23 47962[105:Spt:47961.0,47474.0,47475.0] || until2p7(s24)*+ -> . % 76.04/76.23 47963[105:Spt:47961.0,47474.1] || -> node4(s23)*. % 76.04/76.23 47965[105:MRR:849.0,47963.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.23 47968[105:Res:53.1,47965.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.23 47970[106:Spt:47968.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.23 47972[106:Res:47970.0,61.1] always3(s23) || -> . % 76.04/76.23 47973[106:SSi:47972.0,712.0,47059.0,47061.0,47473.0,47963.0] || -> . % 76.04/76.23 47974[106:Spt:47973.0,47968.0,47970.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.23 47975[106:Spt:47973.0,47968.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.23 47979[106:Res:47975.0,61.1] always3(s24) || -> . % 76.04/76.23 47980[106:SSi:47979.0,713.0,47062.0,47067.0] || -> . % 76.04/76.23 47981[104:Spt:47980.0,47472.0,47473.0] || until2p7(s23)*+ -> . % 76.04/76.23 47982[104:Spt:47980.0,47472.1] || -> node4(s22)*. % 76.04/76.23 47984[104:MRR:852.0,47982.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.23 47987[104:Res:53.1,47984.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.23 47989[105:Spt:47987.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.23 47991[105:Res:47989.0,61.1] always3(s22) || -> . % 76.04/76.23 47992[105:SSi:47991.0,711.0,47053.0,47058.0,47471.0,47982.0] || -> . % 76.04/76.23 47993[105:Spt:47992.0,47987.0,47989.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.23 47994[105:Spt:47992.0,47987.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.23 47998[105:Res:47994.0,61.1] always3(s23) || -> . % 76.04/76.23 47999[105:SSi:47998.0,712.0,47059.0,47061.0] || -> . % 76.04/76.23 48000[103:Spt:47999.0,47470.0,47471.0] || until2p7(s22)*+ -> . % 76.04/76.23 48001[103:Spt:47999.0,47470.1] || -> node4(s21)*. % 76.04/76.23 48003[103:MRR:855.0,48001.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.23 48006[103:Res:53.1,48003.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.23 48011[104:Spt:48006.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.23 48013[104:Res:48011.0,61.1] always3(s21) || -> . % 76.04/76.23 48014[104:SSi:48013.0,710.0,47050.0,47052.0,47469.0,48001.0] || -> . % 76.04/76.23 48015[104:Spt:48014.0,48006.0,48011.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.23 48016[104:Spt:48014.0,48006.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.23 48020[104:Res:48016.0,61.1] always3(s22) || -> . % 76.04/76.23 48021[104:SSi:48020.0,711.0,47053.0,47058.0] || -> . % 76.04/76.23 48022[102:Spt:48021.0,47468.0,47469.0] || until2p7(s21)*+ -> . % 76.04/76.23 48023[102:Spt:48021.0,47468.1] || -> node4(s20)*. % 76.04/76.23 48025[102:MRR:858.0,48023.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.23 48028[102:Res:53.1,48025.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.23 48030[103:Spt:48028.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.23 48032[103:Res:48030.0,61.1] always3(s20) || -> . % 76.04/76.23 48033[103:SSi:48032.0,709.0,47044.0,47049.0,47467.0,48023.0] || -> . % 76.04/76.23 48034[103:Spt:48033.0,48028.0,48030.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.23 48035[103:Spt:48033.0,48028.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.23 48039[103:Res:48035.0,61.1] always3(s21) || -> . % 76.04/76.23 48040[103:SSi:48039.0,710.0,47050.0,47052.0] || -> . % 76.04/76.23 48041[101:Spt:48040.0,47466.0,47467.0] || until2p7(s20)*+ -> . % 76.04/76.23 48042[101:Spt:48040.0,47466.1] || -> node4(s19)*. % 76.04/76.23 48044[101:MRR:861.0,48042.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.23 48047[101:Res:53.1,48044.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.23 48049[102:Spt:48047.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.23 48051[102:Res:48049.0,61.1] always3(s19) || -> . % 76.04/76.23 48052[102:SSi:48051.0,708.0,47041.0,47043.0,47465.0,48042.0] || -> . % 76.04/76.23 48053[102:Spt:48052.0,48047.0,48049.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.23 48054[102:Spt:48052.0,48047.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.23 48058[102:Res:48054.0,61.1] always3(s20) || -> . % 76.04/76.23 48059[102:SSi:48058.0,709.0,47044.0,47049.0] || -> . % 76.04/76.23 48060[100:Spt:48059.0,47464.0,47465.0] || until2p7(s19)*+ -> . % 76.04/76.23 48061[100:Spt:48059.0,47464.1] || -> node4(s18)*. % 76.04/76.23 48063[100:MRR:864.0,48061.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.23 48066[100:Res:53.1,48063.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.23 48068[101:Spt:48066.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.23 48070[101:Res:48068.0,61.1] always3(s18) || -> . % 76.04/76.23 48071[101:SSi:48070.0,707.0,47035.0,47040.0,47463.0,48061.0] || -> . % 76.04/76.23 48072[101:Spt:48071.0,48066.0,48068.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.23 48073[101:Spt:48071.0,48066.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.23 48077[101:Res:48073.0,61.1] always3(s19) || -> . % 76.04/76.23 48078[101:SSi:48077.0,708.0,47041.0,47043.0] || -> . % 76.04/76.23 48079[99:Spt:48078.0,47462.0,47463.0] || until2p7(s18)*+ -> . % 76.04/76.23 48080[99:Spt:48078.0,47462.1] || -> node4(s17)*. % 76.04/76.23 48082[99:MRR:867.0,48080.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.23 48085[99:Res:53.1,48082.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.23 48090[100:Spt:48085.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.23 48092[100:Res:48090.0,61.1] always3(s17) || -> . % 76.04/76.23 48093[100:SSi:48092.0,706.0,47032.0,47034.0,47461.0,48080.0] || -> . % 76.04/76.23 48094[100:Spt:48093.0,48085.0,48090.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.23 48095[100:Spt:48093.0,48085.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.23 48099[100:Res:48095.0,61.1] always3(s18) || -> . % 76.04/76.23 48100[100:SSi:48099.0,707.0,47035.0,47040.0] || -> . % 76.04/76.23 48101[98:Spt:48100.0,47460.0,47461.0] || until2p7(s17)*+ -> . % 76.04/76.23 48102[98:Spt:48100.0,47460.1] || -> node4(s16)*. % 76.04/76.23 48104[98:MRR:870.0,48102.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.23 48107[98:Res:53.1,48104.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.23 48109[99:Spt:48107.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.23 48111[99:Res:48109.0,61.1] always3(s16) || -> . % 76.04/76.23 48112[99:SSi:48111.0,705.0,47026.0,47031.0,47459.0,48102.0] || -> . % 76.04/76.23 48113[99:Spt:48112.0,48107.0,48109.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.23 48114[99:Spt:48112.0,48107.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.23 48118[99:Res:48114.0,61.1] always3(s17) || -> . % 76.04/76.23 48119[99:SSi:48118.0,706.0,47032.0,47034.0] || -> . % 76.04/76.23 48120[97:Spt:48119.0,47458.0,47459.0] || until2p7(s16)*+ -> . % 76.04/76.23 48121[97:Spt:48119.0,47458.1] || -> node4(s15)*. % 76.04/76.23 48123[97:MRR:873.0,48121.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.23 48126[97:Res:53.1,48123.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.23 48128[97:MRR:48126.0,47448.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.23 48130[97:Res:48128.0,61.1] always3(s16) || -> . % 76.04/76.23 48131[97:SSi:48130.0,705.0,47026.0,47031.0] || -> . % 76.04/76.23 48132[95:Spt:48131.0,47291.1,47293.0] || xuntil6(s48)* -> . % 76.04/76.23 48133[95:Spt:48131.0,47291.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.23 48136[95:Res:48133.0,61.1] always3(s48) || -> . % 76.04/76.23 48137[95:SSi:48136.0,737.0,47281.0] || -> . % 76.04/76.23 48138[93:Spt:48137.0,47278.2,47280.0] || xuntil6(s47)*+ -> . % 76.04/76.23 48139[93:Spt:48137.0,47278.0,47278.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.23 48140[93:Res:53.1,48139.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.23 48142[93:MRR:48140.0,47267.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.23 48145[93:Res:48142.0,61.1] always3(s48) || -> . % 76.04/76.23 48146[93:SSi:48145.0,737.0] || -> . % 76.04/76.23 48147[92:Spt:48146.0,47271.1,47276.0] || xuntil6(s46)* -> . % 76.04/76.23 48148[92:Spt:48146.0,47271.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.23 48151[92:Res:48148.0,61.1] always3(s46) || -> . % 76.04/76.23 48152[92:SSi:48151.0,735.0,47261.0] || -> . % 76.04/76.23 48153[90:Spt:48152.0,47252.2,47260.0] || xuntil6(s45)*+ -> . % 76.04/76.23 48154[90:Spt:48152.0,47252.0,47252.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.23 48155[90:Res:53.1,48154.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.23 48157[90:MRR:48155.0,47244.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.23 48159[90:Res:48157.0,61.1] always3(s46) || -> . % 76.04/76.23 48160[90:SSi:48159.0,735.0] || -> . % 76.04/76.23 48161[89:Spt:48160.0,47248.1,47250.0] || xuntil6(s44)* -> . % 76.04/76.23 48162[89:Spt:48160.0,47248.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.23 48165[89:Res:48162.0,61.1] always3(s44) || -> . % 76.04/76.23 48166[89:SSi:48165.0,733.0,47238.0] || -> . % 76.04/76.23 48167[87:Spt:48166.0,47232.2,47237.0] || xuntil6(s43)*+ -> . % 76.04/76.23 48168[87:Spt:48166.0,47232.0,47232.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.23 48169[87:Res:53.1,48168.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.23 48171[87:MRR:48169.0,47224.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.23 48174[87:Res:48171.0,61.1] always3(s44) || -> . % 76.04/76.23 48175[87:SSi:48174.0,733.0] || -> . % 76.04/76.23 48176[86:Spt:48175.0,47228.1,47230.0] || xuntil6(s42)* -> . % 76.04/76.23 48177[86:Spt:48175.0,47228.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.23 48180[86:Res:48177.0,61.1] always3(s42) || -> . % 76.04/76.23 48181[86:SSi:48180.0,731.0,47218.0] || -> . % 76.04/76.23 48182[84:Spt:48181.0,47215.2,47217.0] || xuntil6(s41)*+ -> . % 76.04/76.23 48183[84:Spt:48181.0,47215.0,47215.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.23 48184[84:Res:53.1,48183.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.23 48186[84:MRR:48184.0,47204.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.23 48188[84:Res:48186.0,61.1] always3(s42) || -> . % 76.04/76.23 48189[84:SSi:48188.0,731.0] || -> . % 76.04/76.23 48190[83:Spt:48189.0,47208.1,47213.0] || xuntil6(s40)* -> . % 76.04/76.23 48191[83:Spt:48189.0,47208.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.23 48194[83:Res:48191.0,61.1] always3(s40) || -> . % 76.04/76.23 48195[83:SSi:48194.0,729.0,47198.0] || -> . % 76.04/76.23 48196[81:Spt:48195.0,47189.2,47197.0] || xuntil6(s39)*+ -> . % 76.04/76.23 48197[81:Spt:48195.0,47189.0,47189.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.23 48198[81:Res:53.1,48197.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.23 48200[81:MRR:48198.0,47181.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.23 48202[81:Res:48200.0,61.1] always3(s40) || -> . % 76.04/76.23 48203[81:SSi:48202.0,729.0] || -> . % 76.04/76.23 48204[80:Spt:48203.0,47185.1,47187.0] || xuntil6(s38)* -> . % 76.04/76.23 48205[80:Spt:48203.0,47185.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.23 48208[80:Res:48205.0,61.1] always3(s38) || -> . % 76.04/76.23 48209[80:SSi:48208.0,727.0,47175.0] || -> . % 76.04/76.23 48210[78:Spt:48209.0,47169.2,47174.0] || xuntil6(s37)*+ -> . % 76.04/76.23 48211[78:Spt:48209.0,47169.0,47169.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.23 48212[78:Res:53.1,48211.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.23 48214[78:MRR:48212.0,47161.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.23 48216[78:Res:48214.0,61.1] always3(s38) || -> . % 76.04/76.23 48217[78:SSi:48216.0,727.0] || -> . % 76.04/76.23 48218[77:Spt:48217.0,47165.1,47167.0] || xuntil6(s36)* -> . % 76.04/76.23 48219[77:Spt:48217.0,47165.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.23 48222[77:Res:48219.0,61.1] always3(s36) || -> . % 76.04/76.23 48223[77:SSi:48222.0,725.0,47155.0] || -> . % 76.04/76.23 48224[75:Spt:48223.0,47152.2,47154.0] || xuntil6(s35)*+ -> . % 76.04/76.23 48225[75:Spt:48223.0,47152.0,47152.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.23 48226[75:Res:53.1,48225.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.23 48228[75:MRR:48226.0,47141.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.23 48230[75:Res:48228.0,61.1] always3(s36) || -> . % 76.04/76.23 48231[75:SSi:48230.0,725.0] || -> . % 76.04/76.23 48232[74:Spt:48231.0,47145.1,47150.0] || xuntil6(s34)* -> . % 76.04/76.23 48233[74:Spt:48231.0,47145.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.23 48236[74:Res:48233.0,61.1] always3(s34) || -> . % 76.04/76.23 48237[74:SSi:48236.0,723.0,47135.0] || -> . % 76.04/76.23 48238[72:Spt:48237.0,47126.2,47134.0] || xuntil6(s33)*+ -> . % 76.04/76.23 48239[72:Spt:48237.0,47126.0,47126.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.23 48240[72:Res:53.1,48239.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.23 48242[72:MRR:48240.0,47118.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.23 48244[72:Res:48242.0,61.1] always3(s34) || -> . % 76.04/76.23 48245[72:SSi:48244.0,723.0] || -> . % 76.04/76.23 48246[71:Spt:48245.0,47122.1,47124.0] || xuntil6(s32)* -> . % 76.04/76.23 48247[71:Spt:48245.0,47122.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.23 48250[71:Res:48247.0,61.1] always3(s32) || -> . % 76.04/76.23 48251[71:SSi:48250.0,721.0,47112.0] || -> . % 76.04/76.23 48252[69:Spt:48251.0,47106.2,47111.0] || xuntil6(s31)*+ -> . % 76.04/76.23 48253[69:Spt:48251.0,47106.0,47106.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.23 48254[69:Res:53.1,48253.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.23 48256[69:MRR:48254.0,47098.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.23 48258[69:Res:48256.0,61.1] always3(s32) || -> . % 76.04/76.23 48259[69:SSi:48258.0,721.0] || -> . % 76.04/76.23 48260[68:Spt:48259.0,47102.1,47104.0] || xuntil6(s30)* -> . % 76.04/76.23 48261[68:Spt:48259.0,47102.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.23 48264[68:Res:48261.0,61.1] always3(s30) || -> . % 76.04/76.23 48265[68:SSi:48264.0,719.0,47089.0] || -> . % 76.04/76.23 48266[66:Spt:48265.0,47087.2,47088.0] || xuntil6(s29)*+ -> . % 76.04/76.23 48267[66:Spt:48265.0,47087.0,47087.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.23 48268[66:Res:53.1,48267.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.23 48270[67:Spt:48268.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.23 48272[67:Res:48270.0,61.1] always3(s30) || -> . % 76.04/76.23 48273[67:SSi:48272.0,719.0] || -> . % 76.04/76.23 48274[67:Spt:48273.0,48268.1,48270.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.23 48275[67:Spt:48273.0,48268.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.23 48278[67:Res:48275.0,61.1] always3(s29) || -> . % 76.04/76.23 48279[67:SSi:48278.0,718.0,47086.0] || -> . % 76.04/76.23 48280[65:Spt:48279.0,47081.2,47085.0] || xuntil6(s28)*+ -> . % 76.04/76.23 48281[65:Spt:48279.0,47081.0,47081.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.23 48282[65:Res:53.1,48281.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.23 48284[66:Spt:48282.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.23 48286[66:Res:48284.0,61.1] always3(s29) || -> . % 76.04/76.23 48287[66:SSi:48286.0,718.0] || -> . % 76.04/76.23 48288[66:Spt:48287.0,48282.1,48284.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.23 48289[66:Spt:48287.0,48282.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.23 48292[66:Res:48289.0,61.1] always3(s28) || -> . % 76.04/76.23 48293[66:SSi:48292.0,717.0,47080.0] || -> . % 76.04/76.23 48294[64:Spt:48293.0,47078.2,47079.0] || xuntil6(s27)*+ -> . % 76.04/76.23 48295[64:Spt:48293.0,47078.0,47078.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.23 48296[64:Res:53.1,48295.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.23 48298[65:Spt:48296.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.23 48300[65:Res:48298.0,61.1] always3(s28) || -> . % 76.04/76.23 48301[65:SSi:48300.0,717.0] || -> . % 76.04/76.23 48302[65:Spt:48301.0,48296.1,48298.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.23 48303[65:Spt:48301.0,48296.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.23 48306[65:Res:48303.0,61.1] always3(s27) || -> . % 76.04/76.23 48307[65:SSi:48306.0,716.0,47077.0] || -> . % 76.04/76.23 48308[63:Spt:48307.0,47072.2,47076.0] || xuntil6(s26)*+ -> . % 76.04/76.23 48309[63:Spt:48307.0,47072.0,47072.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.23 48310[63:Res:53.1,48309.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.23 48312[64:Spt:48310.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.23 48314[64:Res:48312.0,61.1] always3(s27) || -> . % 76.04/76.23 48315[64:SSi:48314.0,716.0] || -> . % 76.04/76.23 48316[64:Spt:48315.0,48310.1,48312.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.23 48317[64:Spt:48315.0,48310.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.23 48320[64:Res:48317.0,61.1] always3(s26) || -> . % 76.04/76.23 48321[64:SSi:48320.0,715.0,47071.0] || -> . % 76.04/76.23 48322[62:Spt:48321.0,47069.2,47070.0] || xuntil6(s25)*+ -> . % 76.04/76.23 48323[62:Spt:48321.0,47069.0,47069.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.23 48324[62:Res:53.1,48323.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.23 48326[63:Spt:48324.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.23 48328[63:Res:48326.0,61.1] always3(s26) || -> . % 76.04/76.23 48329[63:SSi:48328.0,715.0] || -> . % 76.04/76.23 48330[63:Spt:48329.0,48324.1,48326.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.23 48331[63:Spt:48329.0,48324.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.23 48334[63:Res:48331.0,61.1] always3(s25) || -> . % 76.04/76.23 48335[63:SSi:48334.0,714.0,47068.0] || -> . % 76.04/76.23 48336[61:Spt:48335.0,47063.2,47067.0] || xuntil6(s24)*+ -> . % 76.04/76.23 48337[61:Spt:48335.0,47063.0,47063.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.23 48338[61:Res:53.1,48337.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.23 48340[62:Spt:48338.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.23 48342[62:Res:48340.0,61.1] always3(s25) || -> . % 76.04/76.23 48343[62:SSi:48342.0,714.0] || -> . % 76.04/76.23 48344[62:Spt:48343.0,48338.1,48340.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.23 48345[62:Spt:48343.0,48338.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.23 48348[62:Res:48345.0,61.1] always3(s24) || -> . % 76.04/76.23 48349[62:SSi:48348.0,713.0,47062.0] || -> . % 76.04/76.23 48350[60:Spt:48349.0,47060.2,47061.0] || xuntil6(s23)*+ -> . % 76.04/76.23 48351[60:Spt:48349.0,47060.0,47060.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.23 48352[60:Res:53.1,48351.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.23 48354[61:Spt:48352.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.23 48356[61:Res:48354.0,61.1] always3(s24) || -> . % 76.04/76.23 48357[61:SSi:48356.0,713.0] || -> . % 76.04/76.23 48358[61:Spt:48357.0,48352.1,48354.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.23 48359[61:Spt:48357.0,48352.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.23 48362[61:Res:48359.0,61.1] always3(s23) || -> . % 76.04/76.23 48363[61:SSi:48362.0,712.0,47059.0] || -> . % 76.04/76.23 48364[59:Spt:48363.0,47054.2,47058.0] || xuntil6(s22)*+ -> . % 76.04/76.23 48365[59:Spt:48363.0,47054.0,47054.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.23 48366[59:Res:53.1,48365.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.23 48368[60:Spt:48366.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.23 48370[60:Res:48368.0,61.1] always3(s23) || -> . % 76.04/76.23 48371[60:SSi:48370.0,712.0] || -> . % 76.04/76.23 48372[60:Spt:48371.0,48366.1,48368.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.23 48373[60:Spt:48371.0,48366.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.23 48376[60:Res:48373.0,61.1] always3(s22) || -> . % 76.04/76.23 48377[60:SSi:48376.0,711.0,47053.0] || -> . % 76.04/76.23 48378[58:Spt:48377.0,47051.2,47052.0] || xuntil6(s21)*+ -> . % 76.04/76.23 48379[58:Spt:48377.0,47051.0,47051.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.23 48380[58:Res:53.1,48379.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.23 48382[59:Spt:48380.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.23 48384[59:Res:48382.0,61.1] always3(s22) || -> . % 76.04/76.23 48385[59:SSi:48384.0,711.0] || -> . % 76.04/76.23 48386[59:Spt:48385.0,48380.1,48382.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.23 48387[59:Spt:48385.0,48380.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.23 48390[59:Res:48387.0,61.1] always3(s21) || -> . % 76.04/76.23 48391[59:SSi:48390.0,710.0,47050.0] || -> . % 76.04/76.23 48392[57:Spt:48391.0,47045.2,47049.0] || xuntil6(s20)*+ -> . % 76.04/76.23 48393[57:Spt:48391.0,47045.0,47045.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.23 48394[57:Res:53.1,48393.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.23 48399[58:Spt:48394.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.23 48401[58:Res:48399.0,61.1] always3(s20) || -> . % 76.04/76.23 48402[58:SSi:48401.0,709.0,47044.0] || -> . % 76.04/76.23 48403[58:Spt:48402.0,48394.0,48399.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.23 48404[58:Spt:48402.0,48394.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.23 48408[58:Res:48404.0,61.1] always3(s21) || -> . % 76.04/76.23 48409[58:SSi:48408.0,710.0] || -> . % 76.04/76.23 48410[56:Spt:48409.0,47042.2,47043.0] || xuntil6(s19)*+ -> . % 76.04/76.23 48411[56:Spt:48409.0,47042.0,47042.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.23 48412[56:Res:53.1,48411.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.23 48414[57:Spt:48412.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.23 48416[57:Res:48414.0,61.1] always3(s20) || -> . % 76.04/76.23 48417[57:SSi:48416.0,709.0] || -> . % 76.04/76.23 48418[57:Spt:48417.0,48412.1,48414.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.23 48419[57:Spt:48417.0,48412.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.23 48422[57:Res:48419.0,61.1] always3(s19) || -> . % 76.04/76.23 48423[57:SSi:48422.0,708.0,47041.0] || -> . % 76.04/76.23 48424[55:Spt:48423.0,47036.2,47040.0] || xuntil6(s18)*+ -> . % 76.04/76.23 48425[55:Spt:48423.0,47036.0,47036.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.23 48426[55:Res:53.1,48425.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.23 48428[56:Spt:48426.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.23 48430[56:Res:48428.0,61.1] always3(s19) || -> . % 76.04/76.23 48431[56:SSi:48430.0,708.0] || -> . % 76.04/76.23 48432[56:Spt:48431.0,48426.1,48428.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.23 48433[56:Spt:48431.0,48426.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.23 48436[56:Res:48433.0,61.1] always3(s18) || -> . % 76.04/76.23 48437[56:SSi:48436.0,707.0,47035.0] || -> . % 76.04/76.23 48438[54:Spt:48437.0,47033.2,47034.0] || xuntil6(s17)*+ -> . % 76.04/76.23 48439[54:Spt:48437.0,47033.0,47033.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.23 48440[54:Res:53.1,48439.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.23 48445[55:Spt:48440.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.23 48447[55:Res:48445.0,61.1] always3(s18) || -> . % 76.04/76.23 48448[55:SSi:48447.0,707.0] || -> . % 76.04/76.23 48449[55:Spt:48448.0,48440.1,48445.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.23 48450[55:Spt:48448.0,48440.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.23 48453[55:Res:48450.0,61.1] always3(s17) || -> . % 76.04/76.23 48454[55:SSi:48453.0,706.0,47032.0] || -> . % 76.04/76.23 48455[53:Spt:48454.0,47027.2,47031.0] || xuntil6(s16)*+ -> . % 76.04/76.23 48456[53:Spt:48454.0,47027.0,47027.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.23 48457[53:Res:53.1,48456.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.23 48459[54:Spt:48457.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.23 48461[54:Res:48459.0,61.1] always3(s16) || -> . % 76.04/76.23 48462[54:SSi:48461.0,705.0,47026.0] || -> . % 76.04/76.23 48463[54:Spt:48462.0,48457.0,48459.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.23 48464[54:Spt:48462.0,48457.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.23 48468[54:Res:48464.0,61.1] always3(s17) || -> . % 76.04/76.23 48469[54:SSi:48468.0,706.0] || -> . % 76.04/76.23 48470[52:Spt:48469.0,47024.2,47025.0] || xuntil6(s15)*+ -> . % 76.04/76.23 48471[52:Spt:48469.0,47024.0,47024.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.23 48472[52:Res:53.1,48471.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.23 48474[53:Spt:48472.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.23 48476[53:Res:48474.0,61.1] always3(s16) || -> . % 76.04/76.23 48477[53:SSi:48476.0,705.0] || -> . % 76.04/76.23 48478[53:Spt:48477.0,48472.1,48474.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.23 48479[53:Spt:48477.0,48472.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.23 48482[53:Res:48479.0,61.1] always3(s15) || -> . % 76.04/76.23 48483[53:SSi:48482.0,704.0,47023.0] || -> . % 76.04/76.23 48484[51:Spt:48483.0,47018.2,47022.0] || xuntil6(s14)*+ -> . % 76.04/76.23 48485[51:Spt:48483.0,47018.0,47018.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.23 48486[51:Res:53.1,48485.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.23 48491[52:Spt:48486.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.23 48493[52:Res:48491.0,61.1] always3(s14) || -> . % 76.04/76.23 48494[52:SSi:48493.0,703.0,47017.0] || -> . % 76.04/76.23 48495[52:Spt:48494.0,48486.0,48491.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.23 48496[52:Spt:48494.0,48486.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.23 48500[52:Res:48496.0,61.1] always3(s15) || -> . % 76.04/76.23 48501[52:SSi:48500.0,704.0] || -> . % 76.04/76.23 48502[50:Spt:48501.0,47015.2,47016.0] || xuntil6(s13)*+ -> . % 76.04/76.23 48503[50:Spt:48501.0,47015.0,47015.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.23 48504[50:Res:53.1,48503.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.23 48506[51:Spt:48504.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.23 48508[51:Res:48506.0,61.1] always3(s13) || -> . % 76.04/76.23 48509[51:SSi:48508.0,702.0,47014.0] || -> . % 76.04/76.23 48510[51:Spt:48509.0,48504.0,48506.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.23 48511[51:Spt:48509.0,48504.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.23 48515[51:Res:48511.0,61.1] always3(s14) || -> . % 76.04/76.23 48516[51:SSi:48515.0,703.0] || -> . % 76.04/76.23 48517[49:Spt:48516.0,47009.2,47013.0] || xuntil6(s12)*+ -> . % 76.04/76.23 48518[49:Spt:48516.0,47009.0,47009.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.23 48519[49:Res:53.1,48518.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.23 48521[50:Spt:48519.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.23 48523[50:Res:48521.0,61.1] always3(s12) || -> . % 76.04/76.23 48524[50:SSi:48523.0,701.0,47008.0] || -> . % 76.04/76.23 48525[50:Spt:48524.0,48519.0,48521.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.23 48526[50:Spt:48524.0,48519.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.23 48530[50:Res:48526.0,61.1] always3(s13) || -> . % 76.04/76.23 48531[50:SSi:48530.0,702.0] || -> . % 76.04/76.23 48532[48:Spt:48531.0,47006.2,47007.0] || xuntil6(s11)*+ -> . % 76.04/76.23 48533[48:Spt:48531.0,47006.0,47006.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.23 48534[48:Res:53.1,48533.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.23 48539[49:Spt:48534.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.23 48541[49:Res:48539.0,61.1] always3(s11) || -> . % 76.04/76.23 48542[49:SSi:48541.0,700.0,47005.0] || -> . % 76.04/76.23 48543[49:Spt:48542.0,48534.0,48539.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.23 48544[49:Spt:48542.0,48534.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.23 48548[49:Res:48544.0,61.1] always3(s12) || -> . % 76.04/76.23 48549[49:SSi:48548.0,701.0] || -> . % 76.04/76.23 48550[47:Spt:48549.0,47000.2,47004.0] || xuntil6(s10)*+ -> . % 76.04/76.23 48551[47:Spt:48549.0,47000.0,47000.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.23 48552[47:Res:53.1,48551.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.23 48554[48:Spt:48552.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.23 48556[48:Res:48554.0,61.1] always3(s10) || -> . % 76.04/76.23 48557[48:SSi:48556.0,699.0,46999.0] || -> . % 76.04/76.23 48558[48:Spt:48557.0,48552.0,48554.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.23 48559[48:Spt:48557.0,48552.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.23 48563[48:Res:48559.0,61.1] always3(s11) || -> . % 76.04/76.23 48564[48:SSi:48563.0,700.0] || -> . % 76.04/76.23 48565[46:Spt:48564.0,46997.2,46998.0] || xuntil6(s9)*+ -> . % 76.04/76.23 48566[46:Spt:48564.0,46997.0,46997.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.23 48567[46:Res:53.1,48566.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.23 48569[47:Spt:48567.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.23 48571[47:Res:48569.0,61.1] always3(s9) || -> . % 76.04/76.23 48572[47:SSi:48571.0,698.0,46996.0] || -> . % 76.04/76.23 48573[47:Spt:48572.0,48567.0,48569.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.23 48574[47:Spt:48572.0,48567.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.23 48578[47:Res:48574.0,61.1] always3(s10) || -> . % 76.04/76.23 48579[47:SSi:48578.0,699.0] || -> . % 76.04/76.23 48580[45:Spt:48579.0,46991.2,46995.0] || xuntil6(s8)*+ -> . % 76.04/76.23 48581[45:Spt:48579.0,46991.0,46991.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.23 48582[45:Res:53.1,48581.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.23 48587[46:Spt:48582.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.23 48589[46:Res:48587.0,61.1] always3(s8) || -> . % 76.04/76.23 48590[46:SSi:48589.0,697.0,46990.0] || -> . % 76.04/76.23 48591[46:Spt:48590.0,48582.0,48587.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.23 48592[46:Spt:48590.0,48582.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.23 48596[46:Res:48592.0,61.1] always3(s9) || -> . % 76.04/76.23 48597[46:SSi:48596.0,698.0] || -> . % 76.04/76.23 48598[44:Spt:48597.0,46988.2,46989.0] || xuntil6(s7)*+ -> . % 76.04/76.23 48599[44:Spt:48597.0,46988.0,46988.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.23 48600[44:Res:53.1,48599.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.23 48602[45:Spt:48600.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.23 48604[45:Res:48602.0,61.1] always3(s7) || -> . % 76.04/76.23 48605[45:SSi:48604.0,696.0,46987.0] || -> . % 76.04/76.23 48606[45:Spt:48605.0,48600.0,48602.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.23 48607[45:Spt:48605.0,48600.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.23 48611[45:Res:48607.0,61.1] always3(s8) || -> . % 76.04/76.23 48612[45:SSi:48611.0,697.0] || -> . % 76.04/76.23 48613[43:Spt:48612.0,46982.2,46986.0] || xuntil6(s6)*+ -> . % 76.04/76.23 48614[43:Spt:48612.0,46982.0,46982.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.23 48615[43:Res:53.1,48614.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.23 48617[44:Spt:48615.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.23 48619[44:Res:48617.0,61.1] always3(s6) || -> . % 76.04/76.23 48620[44:SSi:48619.0,695.0,46981.0] || -> . % 76.04/76.23 48621[44:Spt:48620.0,48615.0,48617.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.23 48622[44:Spt:48620.0,48615.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.23 48626[44:Res:48622.0,61.1] always3(s7) || -> . % 76.04/76.23 48627[44:SSi:48626.0,696.0] || -> . % 76.04/76.23 48628[42:Spt:48627.0,46979.2,46980.0] || xuntil6(s5)*+ -> . % 76.04/76.23 48629[42:Spt:48627.0,46979.0,46979.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.23 48630[42:Res:53.1,48629.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.23 48635[43:Spt:48630.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.23 48637[43:Res:48635.0,61.1] always3(s5) || -> . % 76.04/76.23 48638[43:SSi:48637.0,694.0,46978.0] || -> . % 76.04/76.23 48639[43:Spt:48638.0,48630.0,48635.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.23 48640[43:Spt:48638.0,48630.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.23 48644[43:Res:48640.0,61.1] always3(s6) || -> . % 76.04/76.23 48645[43:SSi:48644.0,695.0] || -> . % 76.04/76.23 48646[41:Spt:48645.0,46973.2,46977.0] || xuntil6(s4)*+ -> . % 76.04/76.23 48647[41:Spt:48645.0,46973.0,46973.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.23 48648[41:Res:53.1,48647.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.23 48650[42:Spt:48648.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.23 48652[42:Res:48650.0,61.1] always3(s4) || -> . % 76.04/76.23 48653[42:SSi:48652.0,693.0,46972.0] || -> . % 76.04/76.23 48654[42:Spt:48653.0,48648.0,48650.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.23 48655[42:Spt:48653.0,48648.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.23 48659[42:Res:48655.0,61.1] always3(s5) || -> . % 76.04/76.23 48660[42:SSi:48659.0,694.0] || -> . % 76.04/76.23 48661[40:Spt:48660.0,46970.2,46971.0] || xuntil6(s3)*+ -> . % 76.04/76.23 48662[40:Spt:48660.0,46970.0,46970.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.23 48663[40:Res:53.1,48662.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.23 48665[41:Spt:48663.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.23 48667[41:Res:48665.0,61.1] always3(s3) || -> . % 76.04/76.23 48668[41:SSi:48667.0,692.0,46969.0] || -> . % 76.04/76.23 48669[41:Spt:48668.0,48663.0,48665.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.23 48670[41:Spt:48668.0,48663.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.23 48674[41:Res:48670.0,61.1] always3(s4) || -> . % 76.04/76.23 48675[41:SSi:48674.0,693.0] || -> . % 76.04/76.23 48676[39:Spt:48675.0,46964.2,46968.0] || xuntil6(s2)*+ -> . % 76.04/76.23 48677[39:Spt:48675.0,46964.0,46964.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.23 48678[39:Res:53.1,48677.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.23 48683[40:Spt:48678.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.23 48685[40:Res:48683.0,61.1] always3(s2) || -> . % 76.04/76.23 48686[40:SSi:48685.0,691.0,46963.0] || -> . % 76.04/76.23 48687[40:Spt:48686.0,48678.0,48683.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.23 48688[40:Spt:48686.0,48678.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.23 48692[40:Res:48688.0,61.1] always3(s3) || -> . % 76.04/76.23 48693[40:SSi:48692.0,692.0] || -> . % 76.04/76.23 48694[38:Spt:48693.0,46958.2,46962.0] || xuntil6(s1)*+ -> . % 76.04/76.23 48695[38:Spt:48693.0,46958.0,46958.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.23 48696[38:Res:53.1,48695.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.23 48698[39:Spt:48696.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.23 48700[39:Res:48698.0,61.1] always3(s1) || -> . % 76.04/76.23 48701[39:SSi:48700.0,690.0,46957.0] || -> . % 76.04/76.23 48702[39:Spt:48701.0,48696.0,48698.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.23 48703[39:Spt:48701.0,48696.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.23 48708[39:Res:48703.0,61.1] always3(s2) || -> . % 76.04/76.23 48709[39:SSi:48708.0,691.0] || -> . % 76.04/76.23 48710[37:Spt:48709.0,74.0,46956.0] || xuntil6(s0)*+ -> . % 76.04/76.23 48711[37:Spt:48709.0,74.1] || -> node4(s0)*. % 76.04/76.23 48712[37:MRR:758.1,48710.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.23 48714[37:Res:48712.0,61.1] always3(s1) || -> . % 76.04/76.23 48715[37:SSi:48714.0,690.0] || -> . % 76.04/76.23 48716[36:Spt:48715.0,46946.0,46950.0] || trans(s49,s15)*+ -> . % 76.04/76.23 48717[36:Spt:48715.0,46946.1,46946.2,46946.3,46946.4,46946.5,46946.6,46946.7,46946.8,46946.9,46946.10,46946.11,46946.12,46946.13,46946.14,46946.15] || -> trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.23 48718[36:MRR:46948.0,48716.0] || -> trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.23 48720[36:MRR:46949.1,48716.0] xuntil6(s49) || -> trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.23 48721[37:Spt:48717.0] || -> trans(s49,s14)*. % 76.04/76.23 48722[37:Res:48721.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s14)*. % 76.04/76.23 48724[37:Res:48721.0,60.0] || -> node2(s49,s14)*. % 76.04/76.23 48725[37:SSi:48722.1,50.0,738.0] xuntil6(s49) || -> until2p7(s14)*. % 76.04/76.23 48726[37:Res:48724.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)*. % 76.04/76.23 48727[38:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.23 48728[38:MRR:176.0,48727.0] || -> until5(s1)*. % 76.04/76.23 48729[38:MRR:47405.0,48728.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.23 48736[39:Spt:48729.2] || -> xuntil6(s1)*. % 76.04/76.23 48737[39:MRR:175.0,48736.0] || -> until5(s2)*. % 76.04/76.23 48738[39:MRR:47398.0,48737.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.23 48739[40:Spt:48738.2] || -> xuntil6(s2)*. % 76.04/76.23 48740[40:MRR:174.0,48739.0] || -> until5(s3)*. % 76.04/76.23 48741[40:MRR:47394.0,48740.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.23 48745[41:Spt:48741.2] || -> xuntil6(s3)*. % 76.04/76.23 48746[41:MRR:173.0,48745.0] || -> until5(s4)*. % 76.04/76.23 48747[41:MRR:47390.0,48746.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.23 48748[42:Spt:48747.2] || -> xuntil6(s4)*. % 76.04/76.23 48749[42:MRR:172.0,48748.0] || -> until5(s5)*. % 76.04/76.23 48750[42:MRR:47386.0,48749.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.23 48754[43:Spt:48750.2] || -> xuntil6(s5)*. % 76.04/76.23 48755[43:MRR:171.0,48754.0] || -> until5(s6)*. % 76.04/76.23 48756[43:MRR:47385.0,48755.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.23 48757[44:Spt:48756.2] || -> xuntil6(s6)*. % 76.04/76.23 48758[44:MRR:170.0,48757.0] || -> until5(s7)*. % 76.04/76.23 48759[44:MRR:47378.0,48758.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.23 48763[45:Spt:48759.2] || -> xuntil6(s7)*. % 76.04/76.23 48764[45:MRR:169.0,48763.0] || -> until5(s8)*. % 76.04/76.23 48765[45:MRR:47374.0,48764.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.23 48766[46:Spt:48765.2] || -> xuntil6(s8)*. % 76.04/76.23 48767[46:MRR:168.0,48766.0] || -> until5(s9)*. % 76.04/76.23 48768[46:MRR:47370.0,48767.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.23 48772[47:Spt:48768.2] || -> xuntil6(s9)*. % 76.04/76.23 48773[47:MRR:167.0,48772.0] || -> until5(s10)*. % 76.04/76.23 48774[47:MRR:47366.0,48773.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.23 48775[48:Spt:48774.2] || -> xuntil6(s10)*. % 76.04/76.23 48776[48:MRR:166.0,48775.0] || -> until5(s11)*. % 76.04/76.23 48777[48:MRR:47365.0,48776.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.23 48781[49:Spt:48777.2] || -> xuntil6(s11)*. % 76.04/76.23 48782[49:MRR:165.0,48781.0] || -> until5(s12)*. % 76.04/76.23 48783[49:MRR:47358.0,48782.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.23 48784[50:Spt:48783.2] || -> xuntil6(s12)*. % 76.04/76.23 48785[50:MRR:164.0,48784.0] || -> until5(s13)*. % 76.04/76.23 48786[50:MRR:47354.0,48785.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.23 48790[51:Spt:48786.2] || -> xuntil6(s13)*. % 76.04/76.23 48791[51:MRR:163.0,48790.0] || -> until5(s14)*. % 76.04/76.23 48792[51:MRR:47350.0,48791.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.23 48793[52:Spt:48792.2] || -> xuntil6(s14)*. % 76.04/76.23 48794[52:MRR:162.0,48793.0] || -> until5(s15)*. % 76.04/76.23 48795[52:MRR:47346.0,48794.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.23 48799[53:Spt:48795.2] || -> xuntil6(s15)*. % 76.04/76.23 48800[53:MRR:161.0,48799.0] || -> until5(s16)*. % 76.04/76.23 48801[53:MRR:47345.0,48800.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.23 48802[54:Spt:48801.2] || -> xuntil6(s16)*. % 76.04/76.23 48803[54:MRR:160.0,48802.0] || -> until5(s17)*. % 76.04/76.23 48804[54:MRR:47335.0,48803.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.23 48808[55:Spt:48804.2] || -> xuntil6(s17)*. % 76.04/76.23 48809[55:MRR:159.0,48808.0] || -> until5(s18)*. % 76.04/76.23 48810[55:MRR:47334.0,48809.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.23 48811[56:Spt:48810.2] || -> xuntil6(s18)*. % 76.04/76.23 48812[56:MRR:158.0,48811.0] || -> until5(s19)*. % 76.04/76.23 48813[56:MRR:47327.0,48812.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.23 48817[57:Spt:48813.2] || -> xuntil6(s19)*. % 76.04/76.23 48818[57:MRR:157.0,48817.0] || -> until5(s20)*. % 76.04/76.23 48819[57:MRR:47326.0,48818.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.23 48820[58:Spt:48819.2] || -> xuntil6(s20)*. % 76.04/76.23 48821[58:MRR:156.0,48820.0] || -> until5(s21)*. % 76.04/76.23 48822[58:MRR:47319.0,48821.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.23 48826[59:Spt:48822.2] || -> xuntil6(s21)*. % 76.04/76.23 48827[59:MRR:155.0,48826.0] || -> until5(s22)*. % 76.04/76.23 48828[59:MRR:47315.0,48827.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.23 48829[60:Spt:48828.2] || -> xuntil6(s22)*. % 76.04/76.23 48830[60:MRR:154.0,48829.0] || -> until5(s23)*. % 76.04/76.23 48831[60:MRR:47314.0,48830.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.23 48835[61:Spt:48831.2] || -> xuntil6(s23)*. % 76.04/76.23 48836[61:MRR:153.0,48835.0] || -> until5(s24)*. % 76.04/76.23 48837[61:MRR:47307.0,48836.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.23 48838[62:Spt:48837.2] || -> xuntil6(s24)*. % 76.04/76.23 48839[62:MRR:152.0,48838.0] || -> until5(s25)*. % 76.04/76.23 48840[62:MRR:47306.0,48839.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.23 48844[63:Spt:48840.2] || -> xuntil6(s25)*. % 76.04/76.23 48845[63:MRR:151.0,48844.0] || -> until5(s26)*. % 76.04/76.23 48846[63:MRR:47305.0,48845.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.23 48847[64:Spt:48846.2] || -> xuntil6(s26)*. % 76.04/76.23 48848[64:MRR:150.0,48847.0] || -> until5(s27)*. % 76.04/76.23 48849[64:MRR:47301.0,48848.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.23 48853[65:Spt:48849.2] || -> xuntil6(s27)*. % 76.04/76.23 48854[65:MRR:149.0,48853.0] || -> until5(s28)*. % 76.04/76.23 48855[65:MRR:47300.0,48854.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.23 48856[66:Spt:48855.2] || -> xuntil6(s28)*. % 76.04/76.23 48857[66:MRR:148.0,48856.0] || -> until5(s29)*. % 76.04/76.23 48858[66:MRR:47299.0,48857.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.23 48862[67:Spt:48858.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.23 48864[67:Res:48862.0,61.1] always3(s30) || -> . % 76.04/76.23 48865[67:SSi:48864.0,719.0] || -> . % 76.04/76.23 48866[67:Spt:48865.0,48858.1,48862.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.04/76.23 48867[67:Spt:48865.0,48858.0,48858.2] || m_main_v_state(s29,c_ready)*+ -> xuntil6(s29). % 76.04/76.23 48869[67:MRR:831.2,48866.0] node4(s29) || m_main_v_state(s29,c_ready)* -> . % 76.04/76.23 48870[67:Res:53.1,48867.0] || -> m_main_v_state(s29,c_busy)* xuntil6(s29). % 76.04/76.23 48872[68:Spt:48870.1] || -> xuntil6(s29)*. % 76.04/76.23 48873[68:MRR:147.0,48872.0] || -> until5(s30)*. % 76.04/76.23 48874[68:MRR:45659.0,48873.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.23 48879[69:Spt:48874.2] || -> xuntil6(s30)*. % 76.04/76.23 48880[69:MRR:146.0,48879.0] || -> until5(s31)*. % 76.04/76.23 48881[69:MRR:47406.0,48880.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.23 48882[70:Spt:48881.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.23 48884[70:Res:48882.0,61.1] always3(s32) || -> . % 76.04/76.23 48885[70:SSi:48884.0,721.0] || -> . % 76.04/76.23 48886[70:Spt:48885.0,48881.1,48882.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.04/76.23 48887[70:Spt:48885.0,48881.0,48881.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.04/76.23 48889[70:MRR:825.2,48886.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.04/76.23 48890[70:Res:53.1,48887.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.04/76.23 48892[71:Spt:48890.1] || -> xuntil6(s31)*. % 76.04/76.23 48893[71:MRR:145.0,48892.0] || -> until5(s32)*. % 76.04/76.23 48894[71:MRR:45663.0,48893.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.23 48902[72:Spt:48894.2] || -> xuntil6(s32)*. % 76.04/76.23 48903[72:MRR:144.0,48902.0] || -> until5(s33)*. % 76.04/76.23 48904[72:MRR:47410.0,48903.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.23 48905[73:Spt:48904.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.23 48907[73:Res:48905.0,61.1] always3(s34) || -> . % 76.04/76.23 48908[73:SSi:48907.0,723.0] || -> . % 76.04/76.23 48909[73:Spt:48908.0,48904.1,48905.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.23 48910[73:Spt:48908.0,48904.0,48904.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.23 48912[73:MRR:819.2,48909.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.23 48913[73:Res:53.1,48910.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.23 48918[74:Spt:48913.1] || -> xuntil6(s33)*. % 76.04/76.23 48919[74:MRR:143.0,48918.0] || -> until5(s34)*. % 76.04/76.23 48920[74:MRR:45667.0,48919.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.23 48922[75:Spt:48920.2] || -> xuntil6(s34)*. % 76.04/76.23 48923[75:MRR:142.0,48922.0] || -> until5(s35)*. % 76.04/76.23 48924[75:MRR:47414.0,48923.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.23 48925[76:Spt:48924.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.23 48927[76:Res:48925.0,61.1] always3(s36) || -> . % 76.04/76.23 48928[76:SSi:48927.0,725.0] || -> . % 76.04/76.23 48929[76:Spt:48928.0,48924.1,48925.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.23 48930[76:Spt:48928.0,48924.0,48924.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.23 48932[76:MRR:813.2,48929.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.23 48933[76:Res:53.1,48930.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.23 48935[77:Spt:48933.1] || -> xuntil6(s35)*. % 76.04/76.23 48936[77:MRR:141.0,48935.0] || -> until5(s36)*. % 76.04/76.23 48937[77:MRR:45674.0,48936.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.23 48942[78:Spt:48937.2] || -> xuntil6(s36)*. % 76.04/76.23 48943[78:MRR:140.0,48942.0] || -> until5(s37)*. % 76.04/76.23 48944[78:MRR:47418.0,48943.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.23 48945[79:Spt:48944.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.23 48947[79:Res:48945.0,61.1] always3(s38) || -> . % 76.04/76.23 48948[79:SSi:48947.0,727.0] || -> . % 76.04/76.23 48949[79:Spt:48948.0,48944.1,48945.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.23 48950[79:Spt:48948.0,48944.0,48944.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.23 48952[79:MRR:807.2,48949.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.23 48953[79:Res:53.1,48950.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.23 48955[80:Spt:48953.1] || -> xuntil6(s37)*. % 76.04/76.23 48956[80:MRR:139.0,48955.0] || -> until5(s38)*. % 76.04/76.23 48957[80:MRR:45675.0,48956.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.23 48965[81:Spt:48957.2] || -> xuntil6(s38)*. % 76.04/76.23 48966[81:MRR:138.0,48965.0] || -> until5(s39)*. % 76.04/76.23 48967[81:MRR:47425.0,48966.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.23 48968[82:Spt:48967.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.23 48970[82:Res:48968.0,61.1] always3(s40) || -> . % 76.04/76.23 48971[82:SSi:48970.0,729.0] || -> . % 76.04/76.23 48972[82:Spt:48971.0,48967.1,48968.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.23 48973[82:Spt:48971.0,48967.0,48967.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.23 48975[82:MRR:801.2,48972.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.23 48976[82:Res:53.1,48973.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.23 48981[83:Spt:48976.1] || -> xuntil6(s39)*. % 76.04/76.23 48982[83:MRR:137.0,48981.0] || -> until5(s40)*. % 76.04/76.23 48983[83:MRR:45679.0,48982.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.23 48985[84:Spt:48983.2] || -> xuntil6(s40)*. % 76.04/76.23 48986[84:MRR:136.0,48985.0] || -> until5(s41)*. % 76.04/76.23 48987[84:MRR:47426.0,48986.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.23 48988[85:Spt:48987.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.23 48990[85:Res:48988.0,61.1] always3(s42) || -> . % 76.04/76.23 48991[85:SSi:48990.0,731.0] || -> . % 76.04/76.23 48992[85:Spt:48991.0,48987.1,48988.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.23 48993[85:Spt:48991.0,48987.0,48987.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.23 48995[85:MRR:795.2,48992.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.23 48996[85:Res:53.1,48993.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.23 48998[86:Spt:48996.1] || -> xuntil6(s41)*. % 76.04/76.23 48999[86:MRR:135.0,48998.0] || -> until5(s42)*. % 76.04/76.23 49000[86:MRR:45683.0,48999.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.23 49005[87:Spt:49000.2] || -> xuntil6(s42)*. % 76.04/76.23 49006[87:MRR:134.0,49005.0] || -> until5(s43)*. % 76.04/76.23 49007[87:MRR:47430.0,49006.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.23 49008[88:Spt:49007.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.23 49010[88:Res:49008.0,61.1] always3(s44) || -> . % 76.04/76.23 49011[88:SSi:49010.0,733.0] || -> . % 76.04/76.23 49012[88:Spt:49011.0,49007.1,49008.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.23 49013[88:Spt:49011.0,49007.0,49007.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.23 49015[88:MRR:789.2,49012.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.23 49016[88:Res:53.1,49013.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.23 49018[89:Spt:49016.1] || -> xuntil6(s43)*. % 76.04/76.23 49019[89:MRR:133.0,49018.0] || -> until5(s44)*. % 76.04/76.23 49020[89:MRR:45687.0,49019.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.23 49028[90:Spt:49020.2] || -> xuntil6(s44)*. % 76.04/76.23 49029[90:MRR:132.0,49028.0] || -> until5(s45)*. % 76.04/76.23 49030[90:MRR:47434.0,49029.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.23 49031[91:Spt:49030.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.23 49033[91:Res:49031.0,61.1] always3(s46) || -> . % 76.04/76.23 49034[91:SSi:49033.0,735.0] || -> . % 76.04/76.23 49035[91:Spt:49034.0,49030.1,49031.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.23 49036[91:Spt:49034.0,49030.0,49030.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.23 49038[91:MRR:783.2,49035.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.23 49039[91:Res:53.1,49036.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.23 49044[92:Spt:49039.1] || -> xuntil6(s45)*. % 76.04/76.23 49045[92:MRR:131.0,49044.0] || -> until5(s46)*. % 76.04/76.23 49046[92:MRR:45694.0,49045.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.23 49048[93:Spt:49046.2] || -> xuntil6(s46)*. % 76.04/76.23 49049[93:MRR:130.0,49048.0] || -> until5(s47)*. % 76.04/76.23 49050[93:MRR:47438.0,49049.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.23 49051[94:Spt:49050.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.23 49053[94:Res:49051.0,61.1] always3(s48) || -> . % 76.04/76.23 49054[94:SSi:49053.0,737.0] || -> . % 76.04/76.23 49055[94:Spt:49054.0,49050.1,49051.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.23 49056[94:Spt:49054.0,49050.0,49050.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.23 49058[94:MRR:777.2,49055.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.23 49059[94:Res:53.1,49056.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.23 49061[95:Spt:49059.1] || -> xuntil6(s47)*. % 76.04/76.23 49062[95:MRR:129.0,49061.0] || -> until5(s48)*. % 76.04/76.23 49063[95:MRR:45695.0,49062.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.23 49068[96:Spt:49063.2] || -> xuntil6(s48)*. % 76.04/76.23 49069[96:MRR:128.0,49068.0] || -> until5(s49)*. % 76.04/76.23 49070[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.23 49074[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.23 49075[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.23 49076[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.23 49077[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.23 49081[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.23 49085[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.23 49092[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.23 49093[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.23 49103[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.23 49104[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.23 49105[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.23 49112[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.23 49116[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.23 49123[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.23 49124[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.23 49128[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.23 49132[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.23 49136[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.23 49143[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.23 49144[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.23 49148[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.23 49152[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.23 49156[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.23 49163[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.23 49164[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.23 49168[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.23 49172[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.23 49174[37:SoR:48726.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)*. % 76.04/76.23 49179[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.23 49183[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.23 49187[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.23 49194[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.23 49195[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.23 49199[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.23 49203[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.23 49207[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.23 49214[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.23 49215[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.23 49216[37:SoR:49174.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)* xuntil6(s49). % 76.04/76.23 49217[96:SSi:49216.0,50.0,738.0,49069.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s14,c_busy)* xuntil6(s49). % 76.04/76.23 49218[97:Spt:49217.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.23 49220[97:Res:49218.0,61.1] always3(s14) || -> . % 76.04/76.23 49221[97:SSi:49220.0,703.0,48791.0,48793.0] || -> . % 76.04/76.23 49222[97:Spt:49221.0,49217.1,49218.0] || m_main_v_state(s14,c_busy)*+ -> . % 76.04/76.23 49223[97:Spt:49221.0,49217.0,49217.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.23 49227[97:MRR:49174.2,49222.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.23 49228[97:Res:53.1,49223.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.23 49230[98:Spt:49228.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.23 49232[98:Res:49230.0,61.1] always3(s49) || -> . % 76.04/76.23 49233[98:SSi:49232.0,50.0,738.0,49069.0] || -> . % 76.04/76.23 49234[98:Spt:49233.0,49228.0,49230.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.23 49235[98:Spt:49233.0,49228.1] || -> xuntil6(s49)*. % 76.04/76.23 49236[98:MRR:48725.0,49235.0] || -> until2p7(s14)*. % 76.04/76.23 49237[98:MRR:210.0,49236.0] || -> until2p7(s15)* node4(s14). % 76.04/76.23 49239[98:MRR:774.2,49234.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.23 49240[99:Spt:49237.0] || -> until2p7(s15)*. % 76.04/76.23 49241[99:MRR:211.0,49240.0] || -> until2p7(s16)* node4(s15). % 76.04/76.23 49242[100:Spt:49241.0] || -> until2p7(s16)*. % 76.04/76.23 49243[100:MRR:212.0,49242.0] || -> until2p7(s17)* node4(s16). % 76.04/76.23 49244[101:Spt:49243.0] || -> until2p7(s17)*. % 76.04/76.23 49245[101:MRR:213.0,49244.0] || -> until2p7(s18)* node4(s17). % 76.04/76.23 49246[102:Spt:49245.0] || -> until2p7(s18)*. % 76.04/76.23 49247[102:MRR:214.0,49246.0] || -> until2p7(s19)* node4(s18). % 76.04/76.23 49248[103:Spt:49247.0] || -> until2p7(s19)*. % 76.04/76.23 49249[103:MRR:215.0,49248.0] || -> until2p7(s20)* node4(s19). % 76.04/76.23 49250[104:Spt:49249.0] || -> until2p7(s20)*. % 76.04/76.23 49251[104:MRR:216.0,49250.0] || -> until2p7(s21)* node4(s20). % 76.04/76.23 49252[105:Spt:49251.0] || -> until2p7(s21)*. % 76.04/76.23 49253[105:MRR:217.0,49252.0] || -> until2p7(s22)* node4(s21). % 76.04/76.23 49254[106:Spt:49253.0] || -> until2p7(s22)*. % 76.04/76.23 49255[106:MRR:218.0,49254.0] || -> until2p7(s23)* node4(s22). % 76.04/76.23 49256[107:Spt:49255.0] || -> until2p7(s23)*. % 76.04/76.23 49257[107:MRR:219.0,49256.0] || -> until2p7(s24)* node4(s23). % 76.04/76.23 49258[108:Spt:49257.0] || -> until2p7(s24)*. % 76.04/76.23 49259[108:MRR:220.0,49258.0] || -> until2p7(s25)* node4(s24). % 76.04/76.23 49260[109:Spt:49259.0] || -> until2p7(s25)*. % 76.04/76.23 49261[109:MRR:221.0,49260.0] || -> until2p7(s26)* node4(s25). % 76.04/76.23 49262[110:Spt:49261.0] || -> until2p7(s26)*. % 76.04/76.23 49263[110:MRR:222.0,49262.0] || -> until2p7(s27)* node4(s26). % 76.04/76.23 49264[111:Spt:49263.0] || -> until2p7(s27)*. % 76.04/76.23 49265[111:MRR:223.0,49264.0] || -> until2p7(s28)* node4(s27). % 76.04/76.23 49266[112:Spt:49265.0] || -> until2p7(s28)*. % 76.04/76.23 49267[112:MRR:224.0,49266.0] || -> until2p7(s29)* node4(s28). % 76.04/76.23 49268[113:Spt:49267.0] || -> until2p7(s29)*. % 76.04/76.23 49269[113:MRR:225.0,49268.0] || -> until2p7(s30)* node4(s29). % 76.04/76.23 49270[114:Spt:49269.0] || -> until2p7(s30)*. % 76.04/76.23 49271[114:MRR:226.0,49270.0] || -> until2p7(s31)* node4(s30). % 76.04/76.23 49272[115:Spt:49271.0] || -> until2p7(s31)*. % 76.04/76.23 49273[115:MRR:227.0,49272.0] || -> until2p7(s32)* node4(s31). % 76.04/76.23 49274[116:Spt:49273.0] || -> until2p7(s32)*. % 76.04/76.23 49275[116:MRR:228.0,49274.0] || -> until2p7(s33)* node4(s32). % 76.04/76.23 49276[117:Spt:49275.0] || -> until2p7(s33)*. % 76.04/76.23 49277[117:MRR:229.0,49276.0] || -> until2p7(s34)* node4(s33). % 76.04/76.23 49278[118:Spt:49277.0] || -> until2p7(s34)*. % 76.04/76.23 49279[118:MRR:230.0,49278.0] || -> until2p7(s35)* node4(s34). % 76.04/76.23 49280[119:Spt:49279.0] || -> until2p7(s35)*. % 76.04/76.23 49281[119:MRR:231.0,49280.0] || -> until2p7(s36)* node4(s35). % 76.04/76.23 49282[120:Spt:49281.0] || -> until2p7(s36)*. % 76.04/76.23 49283[120:MRR:232.0,49282.0] || -> until2p7(s37)* node4(s36). % 76.04/76.23 49284[121:Spt:49283.0] || -> until2p7(s37)*. % 76.04/76.23 49285[121:MRR:235.0,49284.0] || -> until2p7(s38)* node4(s37). % 76.04/76.23 49286[122:Spt:49285.0] || -> until2p7(s38)*. % 76.04/76.23 49287[122:MRR:236.0,49286.0] || -> until2p7(s39)* node4(s38). % 76.04/76.23 49288[123:Spt:49287.0] || -> until2p7(s39)*. % 76.04/76.23 49289[123:MRR:237.0,49288.0] || -> until2p7(s40)* node4(s39). % 76.04/76.23 49290[124:Spt:49289.0] || -> until2p7(s40)*. % 76.04/76.23 49291[124:MRR:238.0,49290.0] || -> until2p7(s41)* node4(s40). % 76.04/76.23 49292[125:Spt:49291.0] || -> until2p7(s41)*. % 76.04/76.23 49293[125:MRR:239.0,49292.0] || -> until2p7(s42)* node4(s41). % 76.04/76.23 49294[126:Spt:49293.0] || -> until2p7(s42)*. % 76.04/76.23 49295[126:MRR:240.0,49294.0] || -> until2p7(s43)* node4(s42). % 76.04/76.23 49296[127:Spt:49295.0] || -> until2p7(s43)*. % 76.04/76.23 49297[127:MRR:241.0,49296.0] || -> until2p7(s44)* node4(s43). % 76.04/76.23 49298[128:Spt:49297.0] || -> until2p7(s44)*. % 76.04/76.23 49299[128:MRR:539.0,49298.0] || -> until2p7(s45)* node4(s44). % 76.04/76.23 49300[129:Spt:49299.0] || -> until2p7(s45)*. % 76.04/76.23 49301[129:MRR:544.0,49300.0] || -> until2p7(s46)* node4(s45). % 76.04/76.23 49302[130:Spt:49301.0] || -> until2p7(s46)*. % 76.04/76.23 49303[130:MRR:549.0,49302.0] || -> until2p7(s47)* node4(s46). % 76.04/76.23 49304[131:Spt:49303.0] || -> until2p7(s47)*. % 76.04/76.23 49305[131:MRR:554.0,49304.0] || -> until2p7(s48)* node4(s47). % 76.04/76.23 49306[132:Spt:49305.0] || -> until2p7(s48)*. % 76.04/76.23 49307[132:MRR:559.0,49306.0] || -> until2p7(s49)* node4(s48). % 76.04/76.23 49308[133:Spt:49307.0] || -> until2p7(s49)*. % 76.04/76.23 49309[133:MRR:194.0,49308.0] || -> node4(s49)*. % 76.04/76.23 49310[133:MRR:49227.0,49309.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.23 49314[133:Res:53.1,49310.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.23 49316[133:MRR:49314.0,49234.0] || -> . % 76.04/76.23 49317[133:Spt:49316.0,49307.0,49308.0] || until2p7(s49)*+ -> . % 76.04/76.23 49318[133:Spt:49316.0,49307.1] || -> node4(s48)*. % 76.04/76.23 49319[133:MRR:49239.0,49318.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.23 49322[133:Res:53.1,49319.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.23 49324[133:MRR:49322.0,49055.0] || -> . % 76.04/76.23 49325[132:Spt:49324.0,49305.0,49306.0] || until2p7(s48)*+ -> . % 76.04/76.23 49326[132:Spt:49324.0,49305.1] || -> node4(s47)*. % 76.04/76.23 49327[132:MRR:49058.0,49326.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.23 49330[132:Res:53.1,49327.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.23 49333[132:Res:49330.0,61.1] always3(s47) || -> . % 76.04/76.23 49334[132:SSi:49333.0,736.0,49049.0,49061.0,49304.0,49326.0] || -> . % 76.04/76.23 49335[131:Spt:49334.0,49303.0,49304.0] || until2p7(s47)*+ -> . % 76.04/76.23 49336[131:Spt:49334.0,49303.1] || -> node4(s46)*. % 76.04/76.23 49338[131:MRR:780.0,49336.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.23 49355[131:Res:53.1,49338.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.23 49357[131:MRR:49355.0,49035.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.23 49359[131:Res:49357.0,61.1] always3(s47) || -> . % 76.04/76.23 49360[131:SSi:49359.0,736.0,49049.0,49061.0] || -> . % 76.04/76.23 49361[130:Spt:49360.0,49301.0,49302.0] || until2p7(s46)*+ -> . % 76.04/76.23 49362[130:Spt:49360.0,49301.1] || -> node4(s45)*. % 76.04/76.23 49363[130:MRR:49038.0,49362.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.23 49366[130:Res:53.1,49363.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.23 49369[130:Res:49366.0,61.1] always3(s45) || -> . % 76.04/76.23 49370[130:SSi:49369.0,734.0,49029.0,49044.0,49300.0,49362.0] || -> . % 76.04/76.23 49371[129:Spt:49370.0,49299.0,49300.0] || until2p7(s45)*+ -> . % 76.04/76.23 49372[129:Spt:49370.0,49299.1] || -> node4(s44)*. % 76.04/76.23 49374[129:MRR:786.0,49372.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.23 49386[129:Res:53.1,49374.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.23 49388[129:MRR:49386.0,49012.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.23 49393[129:Res:49388.0,61.1] always3(s45) || -> . % 76.04/76.23 49394[129:SSi:49393.0,734.0,49029.0,49044.0] || -> . % 76.04/76.23 49395[128:Spt:49394.0,49297.0,49298.0] || until2p7(s44)*+ -> . % 76.04/76.23 49396[128:Spt:49394.0,49297.1] || -> node4(s43)*. % 76.04/76.23 49397[128:MRR:49015.0,49396.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.23 49400[128:Res:53.1,49397.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.23 49404[128:Res:49400.0,61.1] always3(s43) || -> . % 76.04/76.23 49405[128:SSi:49404.0,732.0,49006.0,49018.0,49296.0,49396.0] || -> . % 76.04/76.23 49406[127:Spt:49405.0,49295.0,49296.0] || until2p7(s43)*+ -> . % 76.04/76.23 49407[127:Spt:49405.0,49295.1] || -> node4(s42)*. % 76.04/76.23 49409[127:MRR:792.0,49407.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.23 49420[127:Res:53.1,49409.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.23 49422[127:MRR:49420.0,48992.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.23 49424[127:Res:49422.0,61.1] always3(s43) || -> . % 76.04/76.23 49425[127:SSi:49424.0,732.0,49006.0,49018.0] || -> . % 76.04/76.23 49426[126:Spt:49425.0,49293.0,49294.0] || until2p7(s42)*+ -> . % 76.04/76.23 49427[126:Spt:49425.0,49293.1] || -> node4(s41)*. % 76.04/76.23 49428[126:MRR:48995.0,49427.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.23 49432[126:Res:53.1,49428.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.23 49435[126:Res:49432.0,61.1] always3(s41) || -> . % 76.04/76.23 49436[126:SSi:49435.0,730.0,48986.0,48998.0,49292.0,49427.0] || -> . % 76.04/76.23 49437[125:Spt:49436.0,49291.0,49292.0] || until2p7(s41)*+ -> . % 76.04/76.23 49438[125:Spt:49436.0,49291.1] || -> node4(s40)*. % 76.04/76.23 49440[125:MRR:798.0,49438.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.23 49451[125:Res:53.1,49440.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.23 49453[125:MRR:49451.0,48972.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.23 49455[125:Res:49453.0,61.1] always3(s41) || -> . % 76.04/76.23 49456[125:SSi:49455.0,730.0,48986.0,48998.0] || -> . % 76.04/76.23 49457[124:Spt:49456.0,49289.0,49290.0] || until2p7(s40)*+ -> . % 76.04/76.23 49458[124:Spt:49456.0,49289.1] || -> node4(s39)*. % 76.04/76.23 49459[124:MRR:48975.0,49458.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.23 49462[124:Res:53.1,49459.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.23 49465[124:Res:49462.0,61.1] always3(s39) || -> . % 76.04/76.23 49466[124:SSi:49465.0,728.0,48966.0,48981.0,49288.0,49458.0] || -> . % 76.04/76.23 49467[123:Spt:49466.0,49287.0,49288.0] || until2p7(s39)*+ -> . % 76.04/76.23 49468[123:Spt:49466.0,49287.1] || -> node4(s38)*. % 76.04/76.23 49470[123:MRR:804.0,49468.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.23 49482[123:Res:53.1,49470.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.23 49484[123:MRR:49482.0,48949.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.23 49486[123:Res:49484.0,61.1] always3(s39) || -> . % 76.04/76.23 49487[123:SSi:49486.0,728.0,48966.0,48981.0] || -> . % 76.04/76.23 49488[122:Spt:49487.0,49285.0,49286.0] || until2p7(s38)*+ -> . % 76.04/76.23 49489[122:Spt:49487.0,49285.1] || -> node4(s37)*. % 76.04/76.23 49490[122:MRR:48952.0,49489.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.23 49493[122:Res:53.1,49490.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.23 49496[122:Res:49493.0,61.1] always3(s37) || -> . % 76.04/76.23 49497[122:SSi:49496.0,726.0,48943.0,48955.0,49284.0,49489.0] || -> . % 76.04/76.23 49498[121:Spt:49497.0,49283.0,49284.0] || until2p7(s37)*+ -> . % 76.04/76.23 49499[121:Spt:49497.0,49283.1] || -> node4(s36)*. % 76.04/76.23 49501[121:MRR:810.0,49499.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.23 49513[121:Res:53.1,49501.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.23 49515[121:MRR:49513.0,48929.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.23 49520[121:Res:49515.0,61.1] always3(s37) || -> . % 76.04/76.23 49521[121:SSi:49520.0,726.0,48943.0,48955.0] || -> . % 76.04/76.23 49522[120:Spt:49521.0,49281.0,49282.0] || until2p7(s36)*+ -> . % 76.04/76.23 49523[120:Spt:49521.0,49281.1] || -> node4(s35)*. % 76.04/76.23 49524[120:MRR:48932.0,49523.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.23 49527[120:Res:53.1,49524.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.23 49531[120:Res:49527.0,61.1] always3(s35) || -> . % 76.04/76.23 49532[120:SSi:49531.0,724.0,48923.0,48935.0,49280.0,49523.0] || -> . % 76.04/76.23 49533[119:Spt:49532.0,49279.0,49280.0] || until2p7(s35)*+ -> . % 76.04/76.23 49534[119:Spt:49532.0,49279.1] || -> node4(s34)*. % 76.04/76.23 49536[119:MRR:816.0,49534.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.23 49547[119:Res:53.1,49536.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.23 49549[119:MRR:49547.0,48909.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.23 49551[119:Res:49549.0,61.1] always3(s35) || -> . % 76.04/76.23 49552[119:SSi:49551.0,724.0,48923.0,48935.0] || -> . % 76.04/76.23 49553[118:Spt:49552.0,49277.0,49278.0] || until2p7(s34)*+ -> . % 76.04/76.23 49554[118:Spt:49552.0,49277.1] || -> node4(s33)*. % 76.04/76.23 49555[118:MRR:48912.0,49554.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.23 49559[118:Res:53.1,49555.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.23 49562[118:Res:49559.0,61.1] always3(s33) || -> . % 76.04/76.23 49563[118:SSi:49562.0,722.0,48903.0,48918.0,49276.0,49554.0] || -> . % 76.04/76.23 49564[117:Spt:49563.0,49275.0,49276.0] || until2p7(s33)*+ -> . % 76.04/76.23 49565[117:Spt:49563.0,49275.1] || -> node4(s32)*. % 76.04/76.23 49567[117:MRR:822.0,49565.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.23 49578[117:Res:53.1,49567.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.23 49580[117:MRR:49578.0,48886.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.23 49582[117:Res:49580.0,61.1] always3(s33) || -> . % 76.04/76.23 49583[117:SSi:49582.0,722.0,48903.0,48918.0] || -> . % 76.04/76.23 49584[116:Spt:49583.0,49273.0,49274.0] || until2p7(s32)*+ -> . % 76.04/76.23 49585[116:Spt:49583.0,49273.1] || -> node4(s31)*. % 76.04/76.23 49586[116:MRR:48889.0,49585.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.04/76.23 49589[116:Res:53.1,49586.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.23 49592[116:Res:49589.0,61.1] always3(s31) || -> . % 76.04/76.23 49593[116:SSi:49592.0,720.0,48880.0,48892.0,49272.0,49585.0] || -> . % 76.04/76.23 49594[115:Spt:49593.0,49271.0,49272.0] || until2p7(s31)*+ -> . % 76.04/76.23 49595[115:Spt:49593.0,49271.1] || -> node4(s30)*. % 76.04/76.23 49597[115:MRR:828.0,49595.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.23 49609[115:Res:53.1,49597.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.23 49611[115:MRR:49609.0,48866.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.23 49613[115:Res:49611.0,61.1] always3(s31) || -> . % 76.04/76.23 49614[115:SSi:49613.0,720.0,48880.0,48892.0] || -> . % 76.04/76.23 49615[114:Spt:49614.0,49269.0,49270.0] || until2p7(s30)*+ -> . % 76.04/76.23 49616[114:Spt:49614.0,49269.1] || -> node4(s29)*. % 76.04/76.23 49617[114:MRR:48869.0,49616.0] || m_main_v_state(s29,c_ready)*+ -> . % 76.04/76.23 49620[114:Res:53.1,49617.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.23 49623[114:Res:49620.0,61.1] always3(s29) || -> . % 76.04/76.23 49624[114:SSi:49623.0,718.0,48857.0,48872.0,49268.0,49616.0] || -> . % 76.04/76.23 49625[113:Spt:49624.0,49267.0,49268.0] || until2p7(s29)*+ -> . % 76.04/76.23 49626[113:Spt:49624.0,49267.1] || -> node4(s28)*. % 76.04/76.23 49628[113:MRR:834.0,49626.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.23 49640[113:Res:53.1,49628.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.23 49645[114:Spt:49640.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.23 49647[114:Res:49645.0,61.1] always3(s28) || -> . % 76.04/76.23 49648[114:SSi:49647.0,717.0,48854.0,48856.0,49266.0,49626.0] || -> . % 76.04/76.23 49649[114:Spt:49648.0,49640.0,49645.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.23 49650[114:Spt:49648.0,49640.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.23 49654[114:Res:49650.0,61.1] always3(s29) || -> . % 76.04/76.23 49655[114:SSi:49654.0,718.0,48857.0,48872.0] || -> . % 76.04/76.23 49656[112:Spt:49655.0,49265.0,49266.0] || until2p7(s28)*+ -> . % 76.04/76.23 49657[112:Spt:49655.0,49265.1] || -> node4(s27)*. % 76.04/76.23 49659[112:MRR:837.0,49657.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.23 49666[112:Res:53.1,49659.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.23 49668[113:Spt:49666.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.23 49670[113:Res:49668.0,61.1] always3(s27) || -> . % 76.04/76.23 49671[113:SSi:49670.0,716.0,48848.0,48853.0,49264.0,49657.0] || -> . % 76.04/76.23 49672[113:Spt:49671.0,49666.0,49668.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.23 49673[113:Spt:49671.0,49666.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.23 49677[113:Res:49673.0,61.1] always3(s28) || -> . % 76.04/76.23 49678[113:SSi:49677.0,717.0,48854.0,48856.0] || -> . % 76.04/76.23 49679[111:Spt:49678.0,49263.0,49264.0] || until2p7(s27)*+ -> . % 76.04/76.23 49680[111:Spt:49678.0,49263.1] || -> node4(s26)*. % 76.04/76.23 49682[111:MRR:840.0,49680.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.23 49685[111:Res:53.1,49682.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.23 49690[112:Spt:49685.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.23 49692[112:Res:49690.0,61.1] always3(s26) || -> . % 76.04/76.23 49693[112:SSi:49692.0,715.0,48845.0,48847.0,49262.0,49680.0] || -> . % 76.04/76.23 49694[112:Spt:49693.0,49685.0,49690.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.23 49695[112:Spt:49693.0,49685.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.23 49699[112:Res:49695.0,61.1] always3(s27) || -> . % 76.04/76.23 49700[112:SSi:49699.0,716.0,48848.0,48853.0] || -> . % 76.04/76.23 49701[110:Spt:49700.0,49261.0,49262.0] || until2p7(s26)*+ -> . % 76.04/76.23 49702[110:Spt:49700.0,49261.1] || -> node4(s25)*. % 76.04/76.23 49704[110:MRR:843.0,49702.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.23 49707[110:Res:53.1,49704.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.23 49709[111:Spt:49707.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.23 49711[111:Res:49709.0,61.1] always3(s25) || -> . % 76.04/76.23 49712[111:SSi:49711.0,714.0,48839.0,48844.0,49260.0,49702.0] || -> . % 76.04/76.23 49713[111:Spt:49712.0,49707.0,49709.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.23 49714[111:Spt:49712.0,49707.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.23 49718[111:Res:49714.0,61.1] always3(s26) || -> . % 76.04/76.23 49719[111:SSi:49718.0,715.0,48845.0,48847.0] || -> . % 76.04/76.23 49720[109:Spt:49719.0,49259.0,49260.0] || until2p7(s25)*+ -> . % 76.04/76.23 49721[109:Spt:49719.0,49259.1] || -> node4(s24)*. % 76.04/76.23 49723[109:MRR:846.0,49721.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.23 49726[109:Res:53.1,49723.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.23 49728[110:Spt:49726.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.23 49730[110:Res:49728.0,61.1] always3(s24) || -> . % 76.04/76.23 49731[110:SSi:49730.0,713.0,48836.0,48838.0,49258.0,49721.0] || -> . % 76.04/76.23 49732[110:Spt:49731.0,49726.0,49728.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.23 49733[110:Spt:49731.0,49726.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.23 49737[110:Res:49733.0,61.1] always3(s25) || -> . % 76.04/76.23 49738[110:SSi:49737.0,714.0,48839.0,48844.0] || -> . % 76.04/76.23 49739[108:Spt:49738.0,49257.0,49258.0] || until2p7(s24)*+ -> . % 76.04/76.23 49740[108:Spt:49738.0,49257.1] || -> node4(s23)*. % 76.04/76.23 49742[108:MRR:849.0,49740.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.23 49745[108:Res:53.1,49742.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.23 49747[109:Spt:49745.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.23 49749[109:Res:49747.0,61.1] always3(s23) || -> . % 76.04/76.23 49750[109:SSi:49749.0,712.0,48830.0,48835.0,49256.0,49740.0] || -> . % 76.04/76.23 49751[109:Spt:49750.0,49745.0,49747.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.23 49752[109:Spt:49750.0,49745.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.23 49756[109:Res:49752.0,61.1] always3(s24) || -> . % 76.04/76.23 49757[109:SSi:49756.0,713.0,48836.0,48838.0] || -> . % 76.04/76.23 49758[107:Spt:49757.0,49255.0,49256.0] || until2p7(s23)*+ -> . % 76.04/76.23 49759[107:Spt:49757.0,49255.1] || -> node4(s22)*. % 76.04/76.23 49761[107:MRR:852.0,49759.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.23 49764[107:Res:53.1,49761.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.23 49769[108:Spt:49764.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.23 49771[108:Res:49769.0,61.1] always3(s22) || -> . % 76.04/76.23 49772[108:SSi:49771.0,711.0,48827.0,48829.0,49254.0,49759.0] || -> . % 76.04/76.23 49773[108:Spt:49772.0,49764.0,49769.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.23 49774[108:Spt:49772.0,49764.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.23 49778[108:Res:49774.0,61.1] always3(s23) || -> . % 76.04/76.23 49779[108:SSi:49778.0,712.0,48830.0,48835.0] || -> . % 76.04/76.23 49780[106:Spt:49779.0,49253.0,49254.0] || until2p7(s22)*+ -> . % 76.04/76.23 49781[106:Spt:49779.0,49253.1] || -> node4(s21)*. % 76.04/76.23 49783[106:MRR:855.0,49781.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.23 49786[106:Res:53.1,49783.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.23 49788[107:Spt:49786.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.23 49790[107:Res:49788.0,61.1] always3(s21) || -> . % 76.04/76.23 49791[107:SSi:49790.0,710.0,48821.0,48826.0,49252.0,49781.0] || -> . % 76.04/76.23 49792[107:Spt:49791.0,49786.0,49788.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.23 49793[107:Spt:49791.0,49786.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.23 49797[107:Res:49793.0,61.1] always3(s22) || -> . % 76.04/76.23 49798[107:SSi:49797.0,711.0,48827.0,48829.0] || -> . % 76.04/76.23 49799[105:Spt:49798.0,49251.0,49252.0] || until2p7(s21)*+ -> . % 76.04/76.23 49800[105:Spt:49798.0,49251.1] || -> node4(s20)*. % 76.04/76.23 49802[105:MRR:858.0,49800.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.23 49805[105:Res:53.1,49802.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.23 49807[106:Spt:49805.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.23 49809[106:Res:49807.0,61.1] always3(s20) || -> . % 76.04/76.23 49810[106:SSi:49809.0,709.0,48818.0,48820.0,49250.0,49800.0] || -> . % 76.04/76.23 49811[106:Spt:49810.0,49805.0,49807.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.23 49812[106:Spt:49810.0,49805.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.23 49816[106:Res:49812.0,61.1] always3(s21) || -> . % 76.04/76.23 49817[106:SSi:49816.0,710.0,48821.0,48826.0] || -> . % 76.04/76.23 49818[104:Spt:49817.0,49249.0,49250.0] || until2p7(s20)*+ -> . % 76.04/76.23 49819[104:Spt:49817.0,49249.1] || -> node4(s19)*. % 76.04/76.23 49821[104:MRR:861.0,49819.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.23 49824[104:Res:53.1,49821.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.23 49826[105:Spt:49824.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.23 49828[105:Res:49826.0,61.1] always3(s19) || -> . % 76.04/76.23 49829[105:SSi:49828.0,708.0,48812.0,48817.0,49248.0,49819.0] || -> . % 76.04/76.23 49830[105:Spt:49829.0,49824.0,49826.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.23 49831[105:Spt:49829.0,49824.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.23 49835[105:Res:49831.0,61.1] always3(s20) || -> . % 76.04/76.23 49836[105:SSi:49835.0,709.0,48818.0,48820.0] || -> . % 76.04/76.23 49837[103:Spt:49836.0,49247.0,49248.0] || until2p7(s19)*+ -> . % 76.04/76.23 49838[103:Spt:49836.0,49247.1] || -> node4(s18)*. % 76.04/76.23 49840[103:MRR:864.0,49838.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.23 49843[103:Res:53.1,49840.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.23 49848[104:Spt:49843.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.23 49850[104:Res:49848.0,61.1] always3(s18) || -> . % 76.04/76.23 49851[104:SSi:49850.0,707.0,48809.0,48811.0,49246.0,49838.0] || -> . % 76.04/76.23 49852[104:Spt:49851.0,49843.0,49848.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.23 49853[104:Spt:49851.0,49843.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.23 49857[104:Res:49853.0,61.1] always3(s19) || -> . % 76.04/76.23 49858[104:SSi:49857.0,708.0,48812.0,48817.0] || -> . % 76.04/76.23 49859[102:Spt:49858.0,49245.0,49246.0] || until2p7(s18)*+ -> . % 76.04/76.23 49860[102:Spt:49858.0,49245.1] || -> node4(s17)*. % 76.04/76.23 49862[102:MRR:867.0,49860.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.23 49865[102:Res:53.1,49862.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.23 49867[103:Spt:49865.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.23 49869[103:Res:49867.0,61.1] always3(s17) || -> . % 76.04/76.23 49870[103:SSi:49869.0,706.0,48803.0,48808.0,49244.0,49860.0] || -> . % 76.04/76.23 49871[103:Spt:49870.0,49865.0,49867.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.23 49872[103:Spt:49870.0,49865.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.23 49876[103:Res:49872.0,61.1] always3(s18) || -> . % 76.04/76.23 49877[103:SSi:49876.0,707.0,48809.0,48811.0] || -> . % 76.04/76.23 49878[101:Spt:49877.0,49243.0,49244.0] || until2p7(s17)*+ -> . % 76.04/76.23 49879[101:Spt:49877.0,49243.1] || -> node4(s16)*. % 76.04/76.23 49881[101:MRR:870.0,49879.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.23 49884[101:Res:53.1,49881.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.23 49886[102:Spt:49884.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.23 49888[102:Res:49886.0,61.1] always3(s16) || -> . % 76.04/76.23 49889[102:SSi:49888.0,705.0,48800.0,48802.0,49242.0,49879.0] || -> . % 76.04/76.23 49890[102:Spt:49889.0,49884.0,49886.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.23 49891[102:Spt:49889.0,49884.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.23 49895[102:Res:49891.0,61.1] always3(s17) || -> . % 76.04/76.23 49896[102:SSi:49895.0,706.0,48803.0,48808.0] || -> . % 76.04/76.23 49897[100:Spt:49896.0,49241.0,49242.0] || until2p7(s16)*+ -> . % 76.04/76.23 49898[100:Spt:49896.0,49241.1] || -> node4(s15)*. % 76.04/76.23 49900[100:MRR:873.0,49898.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.23 49903[100:Res:53.1,49900.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.23 49905[101:Spt:49903.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.23 49907[101:Res:49905.0,61.1] always3(s15) || -> . % 76.04/76.23 49908[101:SSi:49907.0,704.0,48794.0,48799.0,49240.0,49898.0] || -> . % 76.04/76.23 49909[101:Spt:49908.0,49903.0,49905.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.23 49910[101:Spt:49908.0,49903.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.23 49914[101:Res:49910.0,61.1] always3(s16) || -> . % 76.04/76.23 49915[101:SSi:49914.0,705.0,48800.0,48802.0] || -> . % 76.04/76.23 49916[99:Spt:49915.0,49237.0,49240.0] || until2p7(s15)*+ -> . % 76.04/76.23 49917[99:Spt:49915.0,49237.1] || -> node4(s14)*. % 76.04/76.23 49919[99:MRR:876.0,49917.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.23 49922[99:Res:53.1,49919.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.23 49924[99:MRR:49922.0,49222.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.23 49929[99:Res:49924.0,61.1] always3(s15) || -> . % 76.04/76.23 49930[99:SSi:49929.0,704.0,48794.0,48799.0] || -> . % 76.04/76.23 49931[96:Spt:49930.0,49063.2,49068.0] || xuntil6(s48)*+ -> . % 76.04/76.23 49932[96:Spt:49930.0,49063.0,49063.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.23 49933[96:Res:53.1,49932.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.23 49935[96:MRR:49933.0,49055.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.23 49937[96:Res:49935.0,61.1] always3(s49) || -> . % 76.04/76.23 49938[96:SSi:49937.0,50.0,738.0] || -> . % 76.04/76.23 49939[95:Spt:49938.0,49059.1,49061.0] || xuntil6(s47)* -> . % 76.04/76.23 49940[95:Spt:49938.0,49059.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.23 49943[95:Res:49940.0,61.1] always3(s47) || -> . % 76.04/76.23 49944[95:SSi:49943.0,736.0,49049.0] || -> . % 76.04/76.23 49945[93:Spt:49944.0,49046.2,49048.0] || xuntil6(s46)*+ -> . % 76.04/76.23 49946[93:Spt:49944.0,49046.0,49046.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.23 49947[93:Res:53.1,49946.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.23 49949[93:MRR:49947.0,49035.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.23 49952[93:Res:49949.0,61.1] always3(s47) || -> . % 76.04/76.23 49953[93:SSi:49952.0,736.0] || -> . % 76.04/76.23 49954[92:Spt:49953.0,49039.1,49044.0] || xuntil6(s45)* -> . % 76.04/76.23 49955[92:Spt:49953.0,49039.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.23 49958[92:Res:49955.0,61.1] always3(s45) || -> . % 76.04/76.23 49959[92:SSi:49958.0,734.0,49029.0] || -> . % 76.04/76.23 49960[90:Spt:49959.0,49020.2,49028.0] || xuntil6(s44)*+ -> . % 76.04/76.23 49961[90:Spt:49959.0,49020.0,49020.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.23 49962[90:Res:53.1,49961.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.23 49964[90:MRR:49962.0,49012.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.23 49966[90:Res:49964.0,61.1] always3(s45) || -> . % 76.04/76.23 49967[90:SSi:49966.0,734.0] || -> . % 76.04/76.23 49968[89:Spt:49967.0,49016.1,49018.0] || xuntil6(s43)* -> . % 76.04/76.23 49969[89:Spt:49967.0,49016.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.23 49972[89:Res:49969.0,61.1] always3(s43) || -> . % 76.04/76.23 49973[89:SSi:49972.0,732.0,49006.0] || -> . % 76.04/76.23 49974[87:Spt:49973.0,49000.2,49005.0] || xuntil6(s42)*+ -> . % 76.04/76.23 49975[87:Spt:49973.0,49000.0,49000.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.23 49976[87:Res:53.1,49975.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.23 49978[87:MRR:49976.0,48992.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.23 49981[87:Res:49978.0,61.1] always3(s43) || -> . % 76.04/76.23 49982[87:SSi:49981.0,732.0] || -> . % 76.04/76.23 49983[86:Spt:49982.0,48996.1,48998.0] || xuntil6(s41)* -> . % 76.04/76.23 49984[86:Spt:49982.0,48996.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.23 49987[86:Res:49984.0,61.1] always3(s41) || -> . % 76.04/76.23 49988[86:SSi:49987.0,730.0,48986.0] || -> . % 76.04/76.23 49989[84:Spt:49988.0,48983.2,48985.0] || xuntil6(s40)*+ -> . % 76.04/76.23 49990[84:Spt:49988.0,48983.0,48983.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.23 49991[84:Res:53.1,49990.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.23 49993[84:MRR:49991.0,48972.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.23 49995[84:Res:49993.0,61.1] always3(s41) || -> . % 76.04/76.23 49996[84:SSi:49995.0,730.0] || -> . % 76.04/76.23 49997[83:Spt:49996.0,48976.1,48981.0] || xuntil6(s39)* -> . % 76.04/76.23 49998[83:Spt:49996.0,48976.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.23 50001[83:Res:49998.0,61.1] always3(s39) || -> . % 76.04/76.23 50002[83:SSi:50001.0,728.0,48966.0] || -> . % 76.04/76.23 50003[81:Spt:50002.0,48957.2,48965.0] || xuntil6(s38)*+ -> . % 76.04/76.23 50004[81:Spt:50002.0,48957.0,48957.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.23 50005[81:Res:53.1,50004.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.23 50007[81:MRR:50005.0,48949.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.23 50009[81:Res:50007.0,61.1] always3(s39) || -> . % 76.04/76.23 50010[81:SSi:50009.0,728.0] || -> . % 76.04/76.23 50011[80:Spt:50010.0,48953.1,48955.0] || xuntil6(s37)* -> . % 76.04/76.23 50012[80:Spt:50010.0,48953.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.23 50015[80:Res:50012.0,61.1] always3(s37) || -> . % 76.04/76.23 50016[80:SSi:50015.0,726.0,48943.0] || -> . % 76.04/76.23 50017[78:Spt:50016.0,48937.2,48942.0] || xuntil6(s36)*+ -> . % 76.04/76.23 50018[78:Spt:50016.0,48937.0,48937.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.23 50019[78:Res:53.1,50018.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.23 50021[78:MRR:50019.0,48929.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.23 50023[78:Res:50021.0,61.1] always3(s37) || -> . % 76.04/76.23 50024[78:SSi:50023.0,726.0] || -> . % 76.04/76.23 50025[77:Spt:50024.0,48933.1,48935.0] || xuntil6(s35)* -> . % 76.04/76.23 50026[77:Spt:50024.0,48933.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.23 50029[77:Res:50026.0,61.1] always3(s35) || -> . % 76.04/76.23 50030[77:SSi:50029.0,724.0,48923.0] || -> . % 76.04/76.23 50031[75:Spt:50030.0,48920.2,48922.0] || xuntil6(s34)*+ -> . % 76.04/76.23 50032[75:Spt:50030.0,48920.0,48920.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.23 50033[75:Res:53.1,50032.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.23 50035[75:MRR:50033.0,48909.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.23 50037[75:Res:50035.0,61.1] always3(s35) || -> . % 76.04/76.23 50038[75:SSi:50037.0,724.0] || -> . % 76.04/76.23 50039[74:Spt:50038.0,48913.1,48918.0] || xuntil6(s33)* -> . % 76.04/76.23 50040[74:Spt:50038.0,48913.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.23 50043[74:Res:50040.0,61.1] always3(s33) || -> . % 76.04/76.23 50044[74:SSi:50043.0,722.0,48903.0] || -> . % 76.04/76.23 50045[72:Spt:50044.0,48894.2,48902.0] || xuntil6(s32)*+ -> . % 76.04/76.23 50046[72:Spt:50044.0,48894.0,48894.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.23 50047[72:Res:53.1,50046.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.23 50049[72:MRR:50047.0,48886.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.23 50051[72:Res:50049.0,61.1] always3(s33) || -> . % 76.04/76.23 50052[72:SSi:50051.0,722.0] || -> . % 76.04/76.23 50053[71:Spt:50052.0,48890.1,48892.0] || xuntil6(s31)* -> . % 76.04/76.23 50054[71:Spt:50052.0,48890.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.23 50057[71:Res:50054.0,61.1] always3(s31) || -> . % 76.04/76.23 50058[71:SSi:50057.0,720.0,48880.0] || -> . % 76.04/76.23 50059[69:Spt:50058.0,48874.2,48879.0] || xuntil6(s30)*+ -> . % 76.04/76.23 50060[69:Spt:50058.0,48874.0,48874.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.23 50061[69:Res:53.1,50060.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.23 50063[69:MRR:50061.0,48866.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.23 50065[69:Res:50063.0,61.1] always3(s31) || -> . % 76.04/76.23 50066[69:SSi:50065.0,720.0] || -> . % 76.04/76.23 50067[68:Spt:50066.0,48870.1,48872.0] || xuntil6(s29)* -> . % 76.04/76.23 50068[68:Spt:50066.0,48870.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.23 50071[68:Res:50068.0,61.1] always3(s29) || -> . % 76.04/76.23 50072[68:SSi:50071.0,718.0,48857.0] || -> . % 76.04/76.23 50073[66:Spt:50072.0,48855.2,48856.0] || xuntil6(s28)*+ -> . % 76.04/76.23 50074[66:Spt:50072.0,48855.0,48855.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.23 50075[66:Res:53.1,50074.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.23 50077[67:Spt:50075.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.23 50079[67:Res:50077.0,61.1] always3(s29) || -> . % 76.04/76.23 50080[67:SSi:50079.0,718.0] || -> . % 76.04/76.23 50081[67:Spt:50080.0,50075.1,50077.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.23 50082[67:Spt:50080.0,50075.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.23 50085[67:Res:50082.0,61.1] always3(s28) || -> . % 76.04/76.23 50086[67:SSi:50085.0,717.0,48854.0] || -> . % 76.04/76.23 50087[65:Spt:50086.0,48849.2,48853.0] || xuntil6(s27)*+ -> . % 76.04/76.23 50088[65:Spt:50086.0,48849.0,48849.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.23 50089[65:Res:53.1,50088.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.23 50091[66:Spt:50089.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.23 50093[66:Res:50091.0,61.1] always3(s28) || -> . % 76.04/76.23 50094[66:SSi:50093.0,717.0] || -> . % 76.04/76.23 50095[66:Spt:50094.0,50089.1,50091.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.23 50096[66:Spt:50094.0,50089.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.23 50099[66:Res:50096.0,61.1] always3(s27) || -> . % 76.04/76.23 50100[66:SSi:50099.0,716.0,48848.0] || -> . % 76.04/76.23 50101[64:Spt:50100.0,48846.2,48847.0] || xuntil6(s26)*+ -> . % 76.04/76.23 50102[64:Spt:50100.0,48846.0,48846.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.23 50103[64:Res:53.1,50102.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.23 50105[65:Spt:50103.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.23 50107[65:Res:50105.0,61.1] always3(s27) || -> . % 76.04/76.23 50108[65:SSi:50107.0,716.0] || -> . % 76.04/76.23 50109[65:Spt:50108.0,50103.1,50105.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.23 50110[65:Spt:50108.0,50103.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.23 50113[65:Res:50110.0,61.1] always3(s26) || -> . % 76.04/76.23 50114[65:SSi:50113.0,715.0,48845.0] || -> . % 76.04/76.23 50115[63:Spt:50114.0,48840.2,48844.0] || xuntil6(s25)*+ -> . % 76.04/76.23 50116[63:Spt:50114.0,48840.0,48840.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.23 50117[63:Res:53.1,50116.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.23 50119[64:Spt:50117.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.23 50121[64:Res:50119.0,61.1] always3(s26) || -> . % 76.04/76.23 50122[64:SSi:50121.0,715.0] || -> . % 76.04/76.23 50123[64:Spt:50122.0,50117.1,50119.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.23 50124[64:Spt:50122.0,50117.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.23 50127[64:Res:50124.0,61.1] always3(s25) || -> . % 76.04/76.23 50128[64:SSi:50127.0,714.0,48839.0] || -> . % 76.04/76.23 50129[62:Spt:50128.0,48837.2,48838.0] || xuntil6(s24)*+ -> . % 76.04/76.23 50130[62:Spt:50128.0,48837.0,48837.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.23 50131[62:Res:53.1,50130.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.23 50133[63:Spt:50131.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.23 50135[63:Res:50133.0,61.1] always3(s25) || -> . % 76.04/76.23 50136[63:SSi:50135.0,714.0] || -> . % 76.04/76.23 50137[63:Spt:50136.0,50131.1,50133.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.23 50138[63:Spt:50136.0,50131.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.23 50141[63:Res:50138.0,61.1] always3(s24) || -> . % 76.04/76.23 50142[63:SSi:50141.0,713.0,48836.0] || -> . % 76.04/76.23 50143[61:Spt:50142.0,48831.2,48835.0] || xuntil6(s23)*+ -> . % 76.04/76.23 50144[61:Spt:50142.0,48831.0,48831.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.23 50145[61:Res:53.1,50144.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.23 50147[62:Spt:50145.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.23 50149[62:Res:50147.0,61.1] always3(s24) || -> . % 76.04/76.23 50150[62:SSi:50149.0,713.0] || -> . % 76.04/76.23 50151[62:Spt:50150.0,50145.1,50147.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.23 50152[62:Spt:50150.0,50145.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.23 50155[62:Res:50152.0,61.1] always3(s23) || -> . % 76.04/76.23 50156[62:SSi:50155.0,712.0,48830.0] || -> . % 76.04/76.23 50157[60:Spt:50156.0,48828.2,48829.0] || xuntil6(s22)*+ -> . % 76.04/76.23 50158[60:Spt:50156.0,48828.0,48828.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.23 50159[60:Res:53.1,50158.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.23 50161[61:Spt:50159.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.23 50163[61:Res:50161.0,61.1] always3(s23) || -> . % 76.04/76.23 50164[61:SSi:50163.0,712.0] || -> . % 76.04/76.23 50165[61:Spt:50164.0,50159.1,50161.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.23 50166[61:Spt:50164.0,50159.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.23 50169[61:Res:50166.0,61.1] always3(s22) || -> . % 76.04/76.23 50170[61:SSi:50169.0,711.0,48827.0] || -> . % 76.04/76.23 50171[59:Spt:50170.0,48822.2,48826.0] || xuntil6(s21)*+ -> . % 76.04/76.23 50172[59:Spt:50170.0,48822.0,48822.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.23 50173[59:Res:53.1,50172.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.23 50178[60:Spt:50173.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.23 50180[60:Res:50178.0,61.1] always3(s21) || -> . % 76.04/76.23 50181[60:SSi:50180.0,710.0,48821.0] || -> . % 76.04/76.23 50182[60:Spt:50181.0,50173.0,50178.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.23 50183[60:Spt:50181.0,50173.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.23 50187[60:Res:50183.0,61.1] always3(s22) || -> . % 76.04/76.23 50188[60:SSi:50187.0,711.0] || -> . % 76.04/76.23 50189[58:Spt:50188.0,48819.2,48820.0] || xuntil6(s20)*+ -> . % 76.04/76.23 50190[58:Spt:50188.0,48819.0,48819.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.23 50191[58:Res:53.1,50190.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.23 50193[59:Spt:50191.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.23 50195[59:Res:50193.0,61.1] always3(s21) || -> . % 76.04/76.23 50196[59:SSi:50195.0,710.0] || -> . % 76.04/76.23 50197[59:Spt:50196.0,50191.1,50193.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.23 50198[59:Spt:50196.0,50191.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.23 50201[59:Res:50198.0,61.1] always3(s20) || -> . % 76.04/76.23 50202[59:SSi:50201.0,709.0,48818.0] || -> . % 76.04/76.23 50203[57:Spt:50202.0,48813.2,48817.0] || xuntil6(s19)*+ -> . % 76.04/76.23 50204[57:Spt:50202.0,48813.0,48813.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.23 50205[57:Res:53.1,50204.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.23 50207[58:Spt:50205.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.23 50209[58:Res:50207.0,61.1] always3(s20) || -> . % 76.04/76.23 50210[58:SSi:50209.0,709.0] || -> . % 76.04/76.23 50211[58:Spt:50210.0,50205.1,50207.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.23 50212[58:Spt:50210.0,50205.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.23 50215[58:Res:50212.0,61.1] always3(s19) || -> . % 76.04/76.23 50216[58:SSi:50215.0,708.0,48812.0] || -> . % 76.04/76.23 50217[56:Spt:50216.0,48810.2,48811.0] || xuntil6(s18)*+ -> . % 76.04/76.23 50218[56:Spt:50216.0,48810.0,48810.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.23 50219[56:Res:53.1,50218.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.23 50224[57:Spt:50219.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.23 50226[57:Res:50224.0,61.1] always3(s18) || -> . % 76.04/76.23 50227[57:SSi:50226.0,707.0,48809.0] || -> . % 76.04/76.23 50228[57:Spt:50227.0,50219.0,50224.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.23 50229[57:Spt:50227.0,50219.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.23 50233[57:Res:50229.0,61.1] always3(s19) || -> . % 76.04/76.23 50234[57:SSi:50233.0,708.0] || -> . % 76.04/76.23 50235[55:Spt:50234.0,48804.2,48808.0] || xuntil6(s17)*+ -> . % 76.04/76.23 50236[55:Spt:50234.0,48804.0,48804.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.23 50237[55:Res:53.1,50236.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.23 50239[56:Spt:50237.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.23 50241[56:Res:50239.0,61.1] always3(s18) || -> . % 76.04/76.23 50242[56:SSi:50241.0,707.0] || -> . % 76.04/76.23 50243[56:Spt:50242.0,50237.1,50239.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.23 50244[56:Spt:50242.0,50237.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.23 50247[56:Res:50244.0,61.1] always3(s17) || -> . % 76.04/76.23 50248[56:SSi:50247.0,706.0,48803.0] || -> . % 76.04/76.23 50249[54:Spt:50248.0,48801.2,48802.0] || xuntil6(s16)*+ -> . % 76.04/76.23 50250[54:Spt:50248.0,48801.0,48801.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.23 50251[54:Res:53.1,50250.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.23 50253[55:Spt:50251.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.23 50255[55:Res:50253.0,61.1] always3(s17) || -> . % 76.04/76.23 50256[55:SSi:50255.0,706.0] || -> . % 76.04/76.23 50257[55:Spt:50256.0,50251.1,50253.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.23 50258[55:Spt:50256.0,50251.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.23 50261[55:Res:50258.0,61.1] always3(s16) || -> . % 76.04/76.23 50262[55:SSi:50261.0,705.0,48800.0] || -> . % 76.04/76.23 50263[53:Spt:50262.0,48795.2,48799.0] || xuntil6(s15)*+ -> . % 76.04/76.23 50264[53:Spt:50262.0,48795.0,48795.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.23 50265[53:Res:53.1,50264.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.23 50270[54:Spt:50265.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.23 50272[54:Res:50270.0,61.1] always3(s15) || -> . % 76.04/76.23 50273[54:SSi:50272.0,704.0,48794.0] || -> . % 76.04/76.23 50274[54:Spt:50273.0,50265.0,50270.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.23 50275[54:Spt:50273.0,50265.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.23 50279[54:Res:50275.0,61.1] always3(s16) || -> . % 76.04/76.23 50280[54:SSi:50279.0,705.0] || -> . % 76.04/76.23 50281[52:Spt:50280.0,48792.2,48793.0] || xuntil6(s14)*+ -> . % 76.04/76.23 50282[52:Spt:50280.0,48792.0,48792.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.23 50283[52:Res:53.1,50282.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.23 50285[53:Spt:50283.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.23 50287[53:Res:50285.0,61.1] always3(s15) || -> . % 76.04/76.23 50288[53:SSi:50287.0,704.0] || -> . % 76.04/76.23 50289[53:Spt:50288.0,50283.1,50285.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.23 50290[53:Spt:50288.0,50283.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.23 50293[53:Res:50290.0,61.1] always3(s14) || -> . % 76.04/76.23 50294[53:SSi:50293.0,703.0,48791.0] || -> . % 76.04/76.23 50295[51:Spt:50294.0,48786.2,48790.0] || xuntil6(s13)*+ -> . % 76.04/76.23 50296[51:Spt:50294.0,48786.0,48786.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.23 50297[51:Res:53.1,50296.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.23 50299[52:Spt:50297.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.23 50301[52:Res:50299.0,61.1] always3(s13) || -> . % 76.04/76.23 50302[52:SSi:50301.0,702.0,48785.0] || -> . % 76.04/76.23 50303[52:Spt:50302.0,50297.0,50299.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.23 50304[52:Spt:50302.0,50297.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.23 50308[52:Res:50304.0,61.1] always3(s14) || -> . % 76.04/76.23 50309[52:SSi:50308.0,703.0] || -> . % 76.04/76.23 50310[50:Spt:50309.0,48783.2,48784.0] || xuntil6(s12)*+ -> . % 76.04/76.23 50311[50:Spt:50309.0,48783.0,48783.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.23 50312[50:Res:53.1,50311.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.23 50317[51:Spt:50312.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.23 50319[51:Res:50317.0,61.1] always3(s12) || -> . % 76.04/76.23 50320[51:SSi:50319.0,701.0,48782.0] || -> . % 76.04/76.23 50321[51:Spt:50320.0,50312.0,50317.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.23 50322[51:Spt:50320.0,50312.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.23 50326[51:Res:50322.0,61.1] always3(s13) || -> . % 76.04/76.23 50327[51:SSi:50326.0,702.0] || -> . % 76.04/76.23 50328[49:Spt:50327.0,48777.2,48781.0] || xuntil6(s11)*+ -> . % 76.04/76.23 50329[49:Spt:50327.0,48777.0,48777.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.23 50330[49:Res:53.1,50329.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.23 50332[50:Spt:50330.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.23 50334[50:Res:50332.0,61.1] always3(s11) || -> . % 76.04/76.23 50335[50:SSi:50334.0,700.0,48776.0] || -> . % 76.04/76.23 50336[50:Spt:50335.0,50330.0,50332.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.23 50337[50:Spt:50335.0,50330.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.23 50341[50:Res:50337.0,61.1] always3(s12) || -> . % 76.04/76.23 50342[50:SSi:50341.0,701.0] || -> . % 76.04/76.23 50343[48:Spt:50342.0,48774.2,48775.0] || xuntil6(s10)*+ -> . % 76.04/76.23 50344[48:Spt:50342.0,48774.0,48774.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.23 50345[48:Res:53.1,50344.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.23 50347[49:Spt:50345.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.23 50349[49:Res:50347.0,61.1] always3(s10) || -> . % 76.04/76.23 50350[49:SSi:50349.0,699.0,48773.0] || -> . % 76.04/76.23 50351[49:Spt:50350.0,50345.0,50347.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.23 50352[49:Spt:50350.0,50345.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.23 50356[49:Res:50352.0,61.1] always3(s11) || -> . % 76.04/76.23 50357[49:SSi:50356.0,700.0] || -> . % 76.04/76.23 50358[47:Spt:50357.0,48768.2,48772.0] || xuntil6(s9)*+ -> . % 76.04/76.23 50359[47:Spt:50357.0,48768.0,48768.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.23 50360[47:Res:53.1,50359.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.23 50365[48:Spt:50360.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.23 50367[48:Res:50365.0,61.1] always3(s9) || -> . % 76.04/76.23 50368[48:SSi:50367.0,698.0,48767.0] || -> . % 76.04/76.23 50369[48:Spt:50368.0,50360.0,50365.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.23 50370[48:Spt:50368.0,50360.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.23 50374[48:Res:50370.0,61.1] always3(s10) || -> . % 76.04/76.23 50375[48:SSi:50374.0,699.0] || -> . % 76.04/76.23 50376[46:Spt:50375.0,48765.2,48766.0] || xuntil6(s8)*+ -> . % 76.04/76.23 50377[46:Spt:50375.0,48765.0,48765.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.23 50378[46:Res:53.1,50377.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.23 50380[47:Spt:50378.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.23 50382[47:Res:50380.0,61.1] always3(s8) || -> . % 76.04/76.23 50383[47:SSi:50382.0,697.0,48764.0] || -> . % 76.04/76.23 50384[47:Spt:50383.0,50378.0,50380.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.23 50385[47:Spt:50383.0,50378.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.23 50389[47:Res:50385.0,61.1] always3(s9) || -> . % 76.04/76.23 50390[47:SSi:50389.0,698.0] || -> . % 76.04/76.23 50391[45:Spt:50390.0,48759.2,48763.0] || xuntil6(s7)*+ -> . % 76.04/76.23 50392[45:Spt:50390.0,48759.0,48759.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.23 50393[45:Res:53.1,50392.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.23 50395[46:Spt:50393.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.23 50397[46:Res:50395.0,61.1] always3(s7) || -> . % 76.04/76.23 50398[46:SSi:50397.0,696.0,48758.0] || -> . % 76.04/76.23 50399[46:Spt:50398.0,50393.0,50395.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.23 50400[46:Spt:50398.0,50393.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.23 50404[46:Res:50400.0,61.1] always3(s8) || -> . % 76.04/76.23 50405[46:SSi:50404.0,697.0] || -> . % 76.04/76.23 50406[44:Spt:50405.0,48756.2,48757.0] || xuntil6(s6)*+ -> . % 76.04/76.23 50407[44:Spt:50405.0,48756.0,48756.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.23 50408[44:Res:53.1,50407.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.23 50413[45:Spt:50408.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.23 50415[45:Res:50413.0,61.1] always3(s6) || -> . % 76.04/76.23 50416[45:SSi:50415.0,695.0,48755.0] || -> . % 76.04/76.23 50417[45:Spt:50416.0,50408.0,50413.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.23 50418[45:Spt:50416.0,50408.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.23 50422[45:Res:50418.0,61.1] always3(s7) || -> . % 76.04/76.23 50423[45:SSi:50422.0,696.0] || -> . % 76.04/76.23 50424[43:Spt:50423.0,48750.2,48754.0] || xuntil6(s5)*+ -> . % 76.04/76.23 50425[43:Spt:50423.0,48750.0,48750.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.23 50426[43:Res:53.1,50425.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.23 50428[44:Spt:50426.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.23 50430[44:Res:50428.0,61.1] always3(s5) || -> . % 76.04/76.23 50431[44:SSi:50430.0,694.0,48749.0] || -> . % 76.04/76.23 50432[44:Spt:50431.0,50426.0,50428.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.23 50433[44:Spt:50431.0,50426.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.23 50437[44:Res:50433.0,61.1] always3(s6) || -> . % 76.04/76.23 50438[44:SSi:50437.0,695.0] || -> . % 76.04/76.23 50439[42:Spt:50438.0,48747.2,48748.0] || xuntil6(s4)*+ -> . % 76.04/76.23 50440[42:Spt:50438.0,48747.0,48747.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.23 50441[42:Res:53.1,50440.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.23 50443[43:Spt:50441.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.23 50445[43:Res:50443.0,61.1] always3(s4) || -> . % 76.04/76.23 50446[43:SSi:50445.0,693.0,48746.0] || -> . % 76.04/76.23 50447[43:Spt:50446.0,50441.0,50443.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.23 50448[43:Spt:50446.0,50441.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.23 50452[43:Res:50448.0,61.1] always3(s5) || -> . % 76.04/76.23 50453[43:SSi:50452.0,694.0] || -> . % 76.04/76.23 50454[41:Spt:50453.0,48741.2,48745.0] || xuntil6(s3)*+ -> . % 76.04/76.23 50455[41:Spt:50453.0,48741.0,48741.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.23 50456[41:Res:53.1,50455.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.23 50461[42:Spt:50456.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.23 50463[42:Res:50461.0,61.1] always3(s3) || -> . % 76.04/76.23 50464[42:SSi:50463.0,692.0,48740.0] || -> . % 76.04/76.23 50465[42:Spt:50464.0,50456.0,50461.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.23 50466[42:Spt:50464.0,50456.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.23 50470[42:Res:50466.0,61.1] always3(s4) || -> . % 76.04/76.23 50471[42:SSi:50470.0,693.0] || -> . % 76.04/76.23 50472[40:Spt:50471.0,48738.2,48739.0] || xuntil6(s2)*+ -> . % 76.04/76.23 50473[40:Spt:50471.0,48738.0,48738.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.23 50474[40:Res:53.1,50473.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.23 50476[41:Spt:50474.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.23 50478[41:Res:50476.0,61.1] always3(s2) || -> . % 76.04/76.23 50479[41:SSi:50478.0,691.0,48737.0] || -> . % 76.04/76.23 50480[41:Spt:50479.0,50474.0,50476.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.23 50481[41:Spt:50479.0,50474.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.23 50485[41:Res:50481.0,61.1] always3(s3) || -> . % 76.04/76.23 50486[41:SSi:50485.0,692.0] || -> . % 76.04/76.23 50487[39:Spt:50486.0,48729.2,48736.0] || xuntil6(s1)*+ -> . % 76.04/76.23 50488[39:Spt:50486.0,48729.0,48729.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.23 50489[39:Res:53.1,50488.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.23 50491[40:Spt:50489.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.23 50493[40:Res:50491.0,61.1] always3(s1) || -> . % 76.04/76.23 50494[40:SSi:50493.0,690.0,48728.0] || -> . % 76.04/76.23 50495[40:Spt:50494.0,50489.0,50491.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.23 50496[40:Spt:50494.0,50489.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.23 50501[40:Res:50496.0,61.1] always3(s2) || -> . % 76.04/76.23 50502[40:SSi:50501.0,691.0] || -> . % 76.04/76.23 50503[38:Spt:50502.0,74.0,48727.0] || xuntil6(s0)*+ -> . % 76.04/76.23 50504[38:Spt:50502.0,74.1] || -> node4(s0)*. % 76.04/76.23 50505[38:MRR:758.1,50503.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.23 50507[38:Res:50505.0,61.1] always3(s1) || -> . % 76.04/76.23 50508[38:SSi:50507.0,690.0] || -> . % 76.04/76.23 50509[37:Spt:50508.0,48717.0,48721.0] || trans(s49,s14)*+ -> . % 76.04/76.23 50510[37:Spt:50508.0,48717.1,48717.2,48717.3,48717.4,48717.5,48717.6,48717.7,48717.8,48717.9,48717.10,48717.11,48717.12,48717.13,48717.14] || -> trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.23 50512[37:MRR:48718.0,50509.0] || -> trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.23 50513[37:MRR:48720.1,50509.0] xuntil6(s49) || -> trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.23 50514[38:Spt:50510.0] || -> trans(s49,s13)*. % 76.04/76.23 50515[38:Res:50514.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s13)*. % 76.04/76.23 50517[38:Res:50514.0,60.0] || -> node2(s49,s13)*. % 76.04/76.23 50518[38:SSi:50515.1,50.0,738.0] xuntil6(s49) || -> until2p7(s13)*. % 76.04/76.23 50519[38:Res:50517.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)*. % 76.04/76.23 50520[39:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.23 50521[39:MRR:176.0,50520.0] || -> until5(s1)*. % 76.04/76.23 50522[39:MRR:49172.0,50521.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.23 50526[40:Spt:50522.2] || -> xuntil6(s1)*. % 76.04/76.23 50527[40:MRR:175.0,50526.0] || -> until5(s2)*. % 76.04/76.23 50528[40:MRR:49168.0,50527.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.23 50532[41:Spt:50528.2] || -> xuntil6(s2)*. % 76.04/76.23 50533[41:MRR:174.0,50532.0] || -> until5(s3)*. % 76.04/76.23 50534[41:MRR:49164.0,50533.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.23 50535[42:Spt:50534.2] || -> xuntil6(s3)*. % 76.04/76.23 50536[42:MRR:173.0,50535.0] || -> until5(s4)*. % 76.04/76.23 50537[42:MRR:49163.0,50536.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.23 50541[43:Spt:50537.2] || -> xuntil6(s4)*. % 76.04/76.23 50542[43:MRR:172.0,50541.0] || -> until5(s5)*. % 76.04/76.23 50543[43:MRR:49156.0,50542.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.23 50544[44:Spt:50543.2] || -> xuntil6(s5)*. % 76.04/76.23 50545[44:MRR:171.0,50544.0] || -> until5(s6)*. % 76.04/76.23 50546[44:MRR:49152.0,50545.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.23 50550[45:Spt:50546.2] || -> xuntil6(s6)*. % 76.04/76.23 50551[45:MRR:170.0,50550.0] || -> until5(s7)*. % 76.04/76.23 50552[45:MRR:49148.0,50551.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.23 50553[46:Spt:50552.2] || -> xuntil6(s7)*. % 76.04/76.23 50554[46:MRR:169.0,50553.0] || -> until5(s8)*. % 76.04/76.23 50555[46:MRR:49144.0,50554.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.23 50559[47:Spt:50555.2] || -> xuntil6(s8)*. % 76.04/76.23 50560[47:MRR:168.0,50559.0] || -> until5(s9)*. % 76.04/76.23 50561[47:MRR:49143.0,50560.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.23 50562[48:Spt:50561.2] || -> xuntil6(s9)*. % 76.04/76.23 50563[48:MRR:167.0,50562.0] || -> until5(s10)*. % 76.04/76.23 50564[48:MRR:49136.0,50563.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.23 50568[49:Spt:50564.2] || -> xuntil6(s10)*. % 76.04/76.23 50569[49:MRR:166.0,50568.0] || -> until5(s11)*. % 76.04/76.23 50570[49:MRR:49132.0,50569.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.23 50571[50:Spt:50570.2] || -> xuntil6(s11)*. % 76.04/76.23 50572[50:MRR:165.0,50571.0] || -> until5(s12)*. % 76.04/76.23 50573[50:MRR:49128.0,50572.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.23 50577[51:Spt:50573.2] || -> xuntil6(s12)*. % 76.04/76.23 50578[51:MRR:164.0,50577.0] || -> until5(s13)*. % 76.04/76.23 50579[51:MRR:49124.0,50578.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.23 50580[52:Spt:50579.2] || -> xuntil6(s13)*. % 76.04/76.23 50581[52:MRR:163.0,50580.0] || -> until5(s14)*. % 76.04/76.23 50582[52:MRR:49123.0,50581.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.23 50586[53:Spt:50582.2] || -> xuntil6(s14)*. % 76.04/76.23 50587[53:MRR:162.0,50586.0] || -> until5(s15)*. % 76.04/76.23 50588[53:MRR:49116.0,50587.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.23 50589[54:Spt:50588.2] || -> xuntil6(s15)*. % 76.04/76.23 50590[54:MRR:161.0,50589.0] || -> until5(s16)*. % 76.04/76.23 50591[54:MRR:49112.0,50590.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.23 50595[55:Spt:50591.2] || -> xuntil6(s16)*. % 76.04/76.23 50596[55:MRR:160.0,50595.0] || -> until5(s17)*. % 76.04/76.23 50597[55:MRR:49105.0,50596.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.23 50598[56:Spt:50597.2] || -> xuntil6(s17)*. % 76.04/76.23 50599[56:MRR:159.0,50598.0] || -> until5(s18)*. % 76.04/76.23 50600[56:MRR:49104.0,50599.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.23 50604[57:Spt:50600.2] || -> xuntil6(s18)*. % 76.04/76.23 50605[57:MRR:158.0,50604.0] || -> until5(s19)*. % 76.04/76.23 50606[57:MRR:49103.0,50605.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.23 50607[58:Spt:50606.2] || -> xuntil6(s19)*. % 76.04/76.23 50608[58:MRR:157.0,50607.0] || -> until5(s20)*. % 76.04/76.23 50609[58:MRR:49093.0,50608.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.23 50613[59:Spt:50609.2] || -> xuntil6(s20)*. % 76.04/76.23 50614[59:MRR:156.0,50613.0] || -> until5(s21)*. % 76.04/76.23 50615[59:MRR:49092.0,50614.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.23 50616[60:Spt:50615.2] || -> xuntil6(s21)*. % 76.04/76.23 50617[60:MRR:155.0,50616.0] || -> until5(s22)*. % 76.04/76.23 50618[60:MRR:49085.0,50617.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.23 50622[61:Spt:50618.2] || -> xuntil6(s22)*. % 76.04/76.23 50623[61:MRR:154.0,50622.0] || -> until5(s23)*. % 76.04/76.23 50624[61:MRR:49081.0,50623.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.23 50625[62:Spt:50624.2] || -> xuntil6(s23)*. % 76.04/76.23 50626[62:MRR:153.0,50625.0] || -> until5(s24)*. % 76.04/76.23 50627[62:MRR:49077.0,50626.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.23 50631[63:Spt:50627.2] || -> xuntil6(s24)*. % 76.04/76.23 50632[63:MRR:152.0,50631.0] || -> until5(s25)*. % 76.04/76.23 50633[63:MRR:49076.0,50632.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.23 50634[64:Spt:50633.2] || -> xuntil6(s25)*. % 76.04/76.23 50635[64:MRR:151.0,50634.0] || -> until5(s26)*. % 76.04/76.23 50636[64:MRR:49075.0,50635.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.23 50640[65:Spt:50636.2] || -> xuntil6(s26)*. % 76.04/76.23 50641[65:MRR:150.0,50640.0] || -> until5(s27)*. % 76.04/76.23 50642[65:MRR:49074.0,50641.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.23 50643[66:Spt:50642.2] || -> xuntil6(s27)*. % 76.04/76.23 50644[66:MRR:149.0,50643.0] || -> until5(s28)*. % 76.04/76.23 50645[66:MRR:49070.0,50644.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.23 50649[67:Spt:50645.2] || -> xuntil6(s28)*. % 76.04/76.23 50650[67:MRR:148.0,50649.0] || -> until5(s29)*. % 76.04/76.23 50651[67:MRR:47299.0,50650.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.23 50652[68:Spt:50651.2] || -> xuntil6(s29)*. % 76.04/76.23 50653[68:MRR:147.0,50652.0] || -> until5(s30)*. % 76.04/76.23 50654[68:MRR:49179.0,50653.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.23 50658[69:Spt:50654.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.23 50660[69:Res:50658.0,61.1] always3(s31) || -> . % 76.04/76.23 50661[69:SSi:50660.0,720.0] || -> . % 76.04/76.23 50662[69:Spt:50661.0,50654.1,50658.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.04/76.23 50663[69:Spt:50661.0,50654.0,50654.2] || m_main_v_state(s30,c_ready)*+ -> xuntil6(s30). % 76.04/76.23 50665[69:MRR:828.2,50662.0] node4(s30) || m_main_v_state(s30,c_ready)* -> . % 76.04/76.23 50666[69:Res:53.1,50663.0] || -> m_main_v_state(s30,c_busy)* xuntil6(s30). % 76.04/76.23 50668[70:Spt:50666.1] || -> xuntil6(s30)*. % 76.04/76.23 50669[70:MRR:146.0,50668.0] || -> until5(s31)*. % 76.04/76.23 50670[70:MRR:47406.0,50669.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.23 50675[71:Spt:50670.2] || -> xuntil6(s31)*. % 76.04/76.23 50676[71:MRR:145.0,50675.0] || -> until5(s32)*. % 76.04/76.23 50677[71:MRR:49183.0,50676.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.23 50678[72:Spt:50677.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.23 50680[72:Res:50678.0,61.1] always3(s33) || -> . % 76.04/76.23 50681[72:SSi:50680.0,722.0] || -> . % 76.04/76.23 50682[72:Spt:50681.0,50677.1,50678.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.04/76.23 50683[72:Spt:50681.0,50677.0,50677.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 76.04/76.23 50685[72:MRR:822.2,50682.0] node4(s32) || m_main_v_state(s32,c_ready)* -> . % 76.04/76.23 50686[72:Res:53.1,50683.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 76.04/76.23 50688[73:Spt:50686.1] || -> xuntil6(s32)*. % 76.04/76.23 50689[73:MRR:144.0,50688.0] || -> until5(s33)*. % 76.04/76.23 50690[73:MRR:47410.0,50689.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.23 50698[74:Spt:50690.2] || -> xuntil6(s33)*. % 76.04/76.23 50699[74:MRR:143.0,50698.0] || -> until5(s34)*. % 76.04/76.23 50700[74:MRR:49187.0,50699.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.23 50701[75:Spt:50700.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.23 50703[75:Res:50701.0,61.1] always3(s35) || -> . % 76.04/76.23 50704[75:SSi:50703.0,724.0] || -> . % 76.04/76.23 50705[75:Spt:50704.0,50700.1,50701.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.04/76.23 50706[75:Spt:50704.0,50700.0,50700.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 76.04/76.23 50708[75:MRR:816.2,50705.0] node4(s34) || m_main_v_state(s34,c_ready)* -> . % 76.04/76.23 50709[75:Res:53.1,50706.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 76.04/76.23 50714[76:Spt:50709.1] || -> xuntil6(s34)*. % 76.04/76.23 50715[76:MRR:142.0,50714.0] || -> until5(s35)*. % 76.04/76.23 50716[76:MRR:47414.0,50715.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.23 50718[77:Spt:50716.2] || -> xuntil6(s35)*. % 76.04/76.23 50719[77:MRR:141.0,50718.0] || -> until5(s36)*. % 76.04/76.23 50720[77:MRR:49194.0,50719.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.23 50721[78:Spt:50720.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.23 50723[78:Res:50721.0,61.1] always3(s37) || -> . % 76.04/76.23 50724[78:SSi:50723.0,726.0] || -> . % 76.04/76.23 50725[78:Spt:50724.0,50720.1,50721.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.04/76.23 50726[78:Spt:50724.0,50720.0,50720.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 76.04/76.23 50728[78:MRR:810.2,50725.0] node4(s36) || m_main_v_state(s36,c_ready)* -> . % 76.04/76.23 50729[78:Res:53.1,50726.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 76.04/76.23 50731[79:Spt:50729.1] || -> xuntil6(s36)*. % 76.04/76.23 50732[79:MRR:140.0,50731.0] || -> until5(s37)*. % 76.04/76.23 50733[79:MRR:47418.0,50732.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.23 50738[80:Spt:50733.2] || -> xuntil6(s37)*. % 76.04/76.23 50739[80:MRR:139.0,50738.0] || -> until5(s38)*. % 76.04/76.23 50740[80:MRR:49195.0,50739.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.23 50741[81:Spt:50740.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.23 50743[81:Res:50741.0,61.1] always3(s39) || -> . % 76.04/76.23 50744[81:SSi:50743.0,728.0] || -> . % 76.04/76.23 50745[81:Spt:50744.0,50740.1,50741.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.04/76.23 50746[81:Spt:50744.0,50740.0,50740.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 76.04/76.24 50748[81:MRR:804.2,50745.0] node4(s38) || m_main_v_state(s38,c_ready)* -> . % 76.04/76.24 50749[81:Res:53.1,50746.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 76.04/76.24 50751[82:Spt:50749.1] || -> xuntil6(s38)*. % 76.04/76.24 50752[82:MRR:138.0,50751.0] || -> until5(s39)*. % 76.04/76.24 50753[82:MRR:47425.0,50752.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.24 50761[83:Spt:50753.2] || -> xuntil6(s39)*. % 76.04/76.24 50762[83:MRR:137.0,50761.0] || -> until5(s40)*. % 76.04/76.24 50763[83:MRR:49199.0,50762.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.24 50764[84:Spt:50763.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.24 50766[84:Res:50764.0,61.1] always3(s41) || -> . % 76.04/76.24 50767[84:SSi:50766.0,730.0] || -> . % 76.04/76.24 50768[84:Spt:50767.0,50763.1,50764.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.04/76.24 50769[84:Spt:50767.0,50763.0,50763.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 76.04/76.24 50771[84:MRR:798.2,50768.0] node4(s40) || m_main_v_state(s40,c_ready)* -> . % 76.04/76.24 50772[84:Res:53.1,50769.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 76.04/76.24 50777[85:Spt:50772.1] || -> xuntil6(s40)*. % 76.04/76.24 50778[85:MRR:136.0,50777.0] || -> until5(s41)*. % 76.04/76.24 50779[85:MRR:47426.0,50778.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.24 50781[86:Spt:50779.2] || -> xuntil6(s41)*. % 76.04/76.24 50782[86:MRR:135.0,50781.0] || -> until5(s42)*. % 76.04/76.24 50783[86:MRR:49203.0,50782.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.24 50784[87:Spt:50783.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.24 50786[87:Res:50784.0,61.1] always3(s43) || -> . % 76.04/76.24 50787[87:SSi:50786.0,732.0] || -> . % 76.04/76.24 50788[87:Spt:50787.0,50783.1,50784.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.04/76.24 50789[87:Spt:50787.0,50783.0,50783.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 76.04/76.24 50791[87:MRR:792.2,50788.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 76.04/76.24 50792[87:Res:53.1,50789.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 76.04/76.24 50794[88:Spt:50792.1] || -> xuntil6(s42)*. % 76.04/76.24 50795[88:MRR:134.0,50794.0] || -> until5(s43)*. % 76.04/76.24 50796[88:MRR:47430.0,50795.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.24 50801[89:Spt:50796.2] || -> xuntil6(s43)*. % 76.04/76.24 50802[89:MRR:133.0,50801.0] || -> until5(s44)*. % 76.04/76.24 50803[89:MRR:49207.0,50802.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.24 50804[90:Spt:50803.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.24 50806[90:Res:50804.0,61.1] always3(s45) || -> . % 76.04/76.24 50807[90:SSi:50806.0,734.0] || -> . % 76.04/76.24 50808[90:Spt:50807.0,50803.1,50804.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.04/76.24 50809[90:Spt:50807.0,50803.0,50803.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 76.04/76.24 50811[90:MRR:786.2,50808.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 76.04/76.24 50812[90:Res:53.1,50809.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 76.04/76.24 50814[91:Spt:50812.1] || -> xuntil6(s44)*. % 76.04/76.24 50815[91:MRR:132.0,50814.0] || -> until5(s45)*. % 76.04/76.24 50816[91:MRR:47434.0,50815.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.24 50824[92:Spt:50816.2] || -> xuntil6(s45)*. % 76.04/76.24 50825[92:MRR:131.0,50824.0] || -> until5(s46)*. % 76.04/76.24 50826[92:MRR:49214.0,50825.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.24 50827[93:Spt:50826.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.24 50829[93:Res:50827.0,61.1] always3(s47) || -> . % 76.04/76.24 50830[93:SSi:50829.0,736.0] || -> . % 76.04/76.24 50831[93:Spt:50830.0,50826.1,50827.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.04/76.24 50832[93:Spt:50830.0,50826.0,50826.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 76.04/76.24 50834[93:MRR:780.2,50831.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 76.04/76.24 50835[93:Res:53.1,50832.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 76.04/76.24 50840[94:Spt:50835.1] || -> xuntil6(s46)*. % 76.04/76.24 50841[94:MRR:130.0,50840.0] || -> until5(s47)*. % 76.04/76.24 50842[94:MRR:47438.0,50841.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.24 50844[95:Spt:50842.2] || -> xuntil6(s47)*. % 76.04/76.24 50845[95:MRR:129.0,50844.0] || -> until5(s48)*. % 76.04/76.24 50846[95:MRR:49215.0,50845.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.24 50847[96:Spt:50846.1] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.24 50849[96:Res:50847.0,61.1] always3(s49) || -> . % 76.04/76.24 50850[96:SSi:50849.0,50.0,738.0] || -> . % 76.04/76.24 50851[96:Spt:50850.0,50846.1,50847.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.24 50852[96:Spt:50850.0,50846.0,50846.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 76.04/76.24 50854[96:MRR:774.2,50851.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.24 50855[96:Res:53.1,50852.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 76.04/76.24 50857[97:Spt:50855.1] || -> xuntil6(s48)*. % 76.04/76.24 50858[97:MRR:128.0,50857.0] || -> until5(s49)*. % 76.04/76.24 50863[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.24 50864[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.24 50865[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.24 50869[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.24 50870[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.24 50874[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.24 50878[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.24 50882[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.24 50889[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.24 50893[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.24 50894[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.24 50898[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.24 50905[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.24 50909[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.24 50910[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.24 50920[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.24 50921[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.24 50925[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.24 50929[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.24 50933[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.24 50940[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.24 50941[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.24 50945[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.24 50949[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.24 50953[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.24 50960[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.24 50961[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.24 50965[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.24 50969[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.24 50973[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.24 50980[0:SoR:819.0,66.2] until5(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.24 50981[0:SoR:813.0,66.2] until5(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.24 50985[0:SoR:807.0,66.2] until5(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.24 50989[0:SoR:801.0,66.2] until5(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.24 50993[0:SoR:795.0,66.2] until5(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.24 51000[0:SoR:789.0,66.2] until5(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.24 51001[0:SoR:783.0,66.2] until5(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.24 51005[0:SoR:777.0,66.2] until5(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.24 51007[38:SoR:50519.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)*. % 76.04/76.24 51009[38:SoR:51007.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)* xuntil6(s49). % 76.04/76.24 51010[97:SSi:51009.0,50.0,738.0,50858.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s13,c_busy)* xuntil6(s49). % 76.04/76.24 51011[98:Spt:51010.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.24 51013[98:Res:51011.0,61.1] always3(s13) || -> . % 76.04/76.24 51014[98:SSi:51013.0,702.0,50578.0,50580.0] || -> . % 76.04/76.24 51015[98:Spt:51014.0,51010.1,51011.0] || m_main_v_state(s13,c_busy)*+ -> . % 76.04/76.24 51016[98:Spt:51014.0,51010.0,51010.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.24 51020[98:MRR:51007.2,51015.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.24 51021[98:Res:53.1,51016.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.24 51023[98:MRR:51021.0,50851.0] || -> xuntil6(s49)*. % 76.04/76.24 51024[98:MRR:50518.0,51023.0] || -> until2p7(s13)*. % 76.04/76.24 51025[98:MRR:209.0,51024.0] || -> until2p7(s14)* node4(s13). % 76.04/76.24 51026[99:Spt:51025.0] || -> until2p7(s14)*. % 76.04/76.24 51027[99:MRR:210.0,51026.0] || -> until2p7(s15)* node4(s14). % 76.04/76.24 51028[100:Spt:51027.0] || -> until2p7(s15)*. % 76.04/76.24 51029[100:MRR:211.0,51028.0] || -> until2p7(s16)* node4(s15). % 76.04/76.24 51030[101:Spt:51029.0] || -> until2p7(s16)*. % 76.04/76.24 51031[101:MRR:212.0,51030.0] || -> until2p7(s17)* node4(s16). % 76.04/76.24 51032[102:Spt:51031.0] || -> until2p7(s17)*. % 76.04/76.24 51033[102:MRR:213.0,51032.0] || -> until2p7(s18)* node4(s17). % 76.04/76.24 51034[103:Spt:51033.0] || -> until2p7(s18)*. % 76.04/76.24 51035[103:MRR:214.0,51034.0] || -> until2p7(s19)* node4(s18). % 76.04/76.24 51036[104:Spt:51035.0] || -> until2p7(s19)*. % 76.04/76.24 51037[104:MRR:215.0,51036.0] || -> until2p7(s20)* node4(s19). % 76.04/76.24 51038[105:Spt:51037.0] || -> until2p7(s20)*. % 76.04/76.24 51039[105:MRR:216.0,51038.0] || -> until2p7(s21)* node4(s20). % 76.04/76.24 51040[106:Spt:51039.0] || -> until2p7(s21)*. % 76.04/76.24 51041[106:MRR:217.0,51040.0] || -> until2p7(s22)* node4(s21). % 76.04/76.24 51042[107:Spt:51041.0] || -> until2p7(s22)*. % 76.04/76.24 51043[107:MRR:218.0,51042.0] || -> until2p7(s23)* node4(s22). % 76.04/76.24 51044[108:Spt:51043.0] || -> until2p7(s23)*. % 76.04/76.24 51045[108:MRR:219.0,51044.0] || -> until2p7(s24)* node4(s23). % 76.04/76.24 51046[109:Spt:51045.0] || -> until2p7(s24)*. % 76.04/76.24 51047[109:MRR:220.0,51046.0] || -> until2p7(s25)* node4(s24). % 76.04/76.24 51048[110:Spt:51047.0] || -> until2p7(s25)*. % 76.04/76.24 51049[110:MRR:221.0,51048.0] || -> until2p7(s26)* node4(s25). % 76.04/76.24 51050[111:Spt:51049.0] || -> until2p7(s26)*. % 76.04/76.24 51051[111:MRR:222.0,51050.0] || -> until2p7(s27)* node4(s26). % 76.04/76.24 51052[112:Spt:51051.0] || -> until2p7(s27)*. % 76.04/76.24 51053[112:MRR:223.0,51052.0] || -> until2p7(s28)* node4(s27). % 76.04/76.24 51054[113:Spt:51053.0] || -> until2p7(s28)*. % 76.04/76.24 51055[113:MRR:224.0,51054.0] || -> until2p7(s29)* node4(s28). % 76.04/76.24 51056[114:Spt:51055.0] || -> until2p7(s29)*. % 76.04/76.24 51057[114:MRR:225.0,51056.0] || -> until2p7(s30)* node4(s29). % 76.04/76.24 51058[115:Spt:51057.0] || -> until2p7(s30)*. % 76.04/76.24 51059[115:MRR:226.0,51058.0] || -> until2p7(s31)* node4(s30). % 76.04/76.24 51060[116:Spt:51059.0] || -> until2p7(s31)*. % 76.04/76.24 51061[116:MRR:227.0,51060.0] || -> until2p7(s32)* node4(s31). % 76.04/76.24 51062[117:Spt:51061.0] || -> until2p7(s32)*. % 76.04/76.24 51063[117:MRR:228.0,51062.0] || -> until2p7(s33)* node4(s32). % 76.04/76.24 51064[118:Spt:51063.0] || -> until2p7(s33)*. % 76.04/76.24 51065[118:MRR:229.0,51064.0] || -> until2p7(s34)* node4(s33). % 76.04/76.24 51066[119:Spt:51065.0] || -> until2p7(s34)*. % 76.04/76.24 51067[119:MRR:230.0,51066.0] || -> until2p7(s35)* node4(s34). % 76.04/76.24 51068[120:Spt:51067.0] || -> until2p7(s35)*. % 76.04/76.24 51069[120:MRR:231.0,51068.0] || -> until2p7(s36)* node4(s35). % 76.04/76.24 51070[121:Spt:51069.0] || -> until2p7(s36)*. % 76.04/76.24 51071[121:MRR:232.0,51070.0] || -> until2p7(s37)* node4(s36). % 76.04/76.24 51072[122:Spt:51071.0] || -> until2p7(s37)*. % 76.04/76.24 51073[122:MRR:235.0,51072.0] || -> until2p7(s38)* node4(s37). % 76.04/76.24 51074[123:Spt:51073.0] || -> until2p7(s38)*. % 76.04/76.24 51075[123:MRR:236.0,51074.0] || -> until2p7(s39)* node4(s38). % 76.04/76.24 51076[124:Spt:51075.0] || -> until2p7(s39)*. % 76.04/76.24 51077[124:MRR:237.0,51076.0] || -> until2p7(s40)* node4(s39). % 76.04/76.24 51078[125:Spt:51077.0] || -> until2p7(s40)*. % 76.04/76.24 51079[125:MRR:238.0,51078.0] || -> until2p7(s41)* node4(s40). % 76.04/76.24 51080[126:Spt:51079.0] || -> until2p7(s41)*. % 76.04/76.24 51081[126:MRR:239.0,51080.0] || -> until2p7(s42)* node4(s41). % 76.04/76.24 51082[127:Spt:51081.0] || -> until2p7(s42)*. % 76.04/76.24 51083[127:MRR:240.0,51082.0] || -> until2p7(s43)* node4(s42). % 76.04/76.24 51084[128:Spt:51083.0] || -> until2p7(s43)*. % 76.04/76.24 51085[128:MRR:241.0,51084.0] || -> until2p7(s44)* node4(s43). % 76.04/76.24 51086[129:Spt:51085.0] || -> until2p7(s44)*. % 76.04/76.24 51087[129:MRR:539.0,51086.0] || -> until2p7(s45)* node4(s44). % 76.04/76.24 51088[130:Spt:51087.0] || -> until2p7(s45)*. % 76.04/76.24 51089[130:MRR:544.0,51088.0] || -> until2p7(s46)* node4(s45). % 76.04/76.24 51090[131:Spt:51089.0] || -> until2p7(s46)*. % 76.04/76.24 51091[131:MRR:549.0,51090.0] || -> until2p7(s47)* node4(s46). % 76.04/76.24 51092[132:Spt:51091.0] || -> until2p7(s47)*. % 76.04/76.24 51093[132:MRR:554.0,51092.0] || -> until2p7(s48)* node4(s47). % 76.04/76.24 51094[133:Spt:51093.0] || -> until2p7(s48)*. % 76.04/76.24 51095[133:MRR:559.0,51094.0] || -> until2p7(s49)* node4(s48). % 76.04/76.24 51096[134:Spt:51095.0] || -> until2p7(s49)*. % 76.04/76.24 51097[134:MRR:194.0,51096.0] || -> node4(s49)*. % 76.04/76.24 51098[134:MRR:51020.0,51097.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.24 51099[134:Res:53.1,51098.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.24 51101[134:MRR:51099.0,50851.0] || -> . % 76.04/76.24 51102[134:Spt:51101.0,51095.0,51096.0] || until2p7(s49)*+ -> . % 76.04/76.24 51103[134:Spt:51101.0,51095.1] || -> node4(s48)*. % 76.04/76.24 51104[134:MRR:50854.0,51103.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.24 51107[134:Res:53.1,51104.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.24 51110[134:Res:51107.0,61.1] always3(s48) || -> . % 76.04/76.24 51111[134:SSi:51110.0,737.0,50845.0,50857.0,51094.0,51103.0] || -> . % 76.04/76.24 51112[133:Spt:51111.0,51093.0,51094.0] || until2p7(s48)*+ -> . % 76.04/76.24 51113[133:Spt:51111.0,51093.1] || -> node4(s47)*. % 76.04/76.24 51115[133:MRR:777.0,51113.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.24 51130[133:Res:53.1,51115.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.24 51132[133:MRR:51130.0,50831.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.24 51137[133:Res:51132.0,61.1] always3(s48) || -> . % 76.04/76.24 51138[133:SSi:51137.0,737.0,50845.0,50857.0] || -> . % 76.04/76.24 51139[132:Spt:51138.0,51091.0,51092.0] || until2p7(s47)*+ -> . % 76.04/76.24 51140[132:Spt:51138.0,51091.1] || -> node4(s46)*. % 76.04/76.24 51141[132:MRR:50834.0,51140.0] || m_main_v_state(s46,c_ready)*+ -> . % 76.04/76.24 51144[132:Res:53.1,51141.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.24 51148[132:Res:51144.0,61.1] always3(s46) || -> . % 76.04/76.24 51149[132:SSi:51148.0,735.0,50825.0,50840.0,51090.0,51140.0] || -> . % 76.04/76.24 51150[131:Spt:51149.0,51089.0,51090.0] || until2p7(s46)*+ -> . % 76.04/76.24 51151[131:Spt:51149.0,51089.1] || -> node4(s45)*. % 76.04/76.24 51153[131:MRR:783.0,51151.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.24 51164[131:Res:53.1,51153.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.24 51166[131:MRR:51164.0,50808.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.24 51168[131:Res:51166.0,61.1] always3(s46) || -> . % 76.04/76.24 51169[131:SSi:51168.0,735.0,50825.0,50840.0] || -> . % 76.04/76.24 51170[130:Spt:51169.0,51087.0,51088.0] || until2p7(s45)*+ -> . % 76.04/76.24 51171[130:Spt:51169.0,51087.1] || -> node4(s44)*. % 76.04/76.24 51172[130:MRR:50811.0,51171.0] || m_main_v_state(s44,c_ready)*+ -> . % 76.04/76.24 51176[130:Res:53.1,51172.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.24 51179[130:Res:51176.0,61.1] always3(s44) || -> . % 76.04/76.24 51180[130:SSi:51179.0,733.0,50802.0,50814.0,51086.0,51171.0] || -> . % 76.04/76.24 51181[129:Spt:51180.0,51085.0,51086.0] || until2p7(s44)*+ -> . % 76.04/76.24 51182[129:Spt:51180.0,51085.1] || -> node4(s43)*. % 76.04/76.24 51184[129:MRR:789.0,51182.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.24 51195[129:Res:53.1,51184.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.24 51197[129:MRR:51195.0,50788.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.24 51199[129:Res:51197.0,61.1] always3(s44) || -> . % 76.04/76.24 51200[129:SSi:51199.0,733.0,50802.0,50814.0] || -> . % 76.04/76.24 51201[128:Spt:51200.0,51083.0,51084.0] || until2p7(s43)*+ -> . % 76.04/76.24 51202[128:Spt:51200.0,51083.1] || -> node4(s42)*. % 76.04/76.24 51203[128:MRR:50791.0,51202.0] || m_main_v_state(s42,c_ready)*+ -> . % 76.04/76.24 51206[128:Res:53.1,51203.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.24 51209[128:Res:51206.0,61.1] always3(s42) || -> . % 76.04/76.24 51210[128:SSi:51209.0,731.0,50782.0,50794.0,51082.0,51202.0] || -> . % 76.04/76.24 51211[127:Spt:51210.0,51081.0,51082.0] || until2p7(s42)*+ -> . % 76.04/76.24 51212[127:Spt:51210.0,51081.1] || -> node4(s41)*. % 76.04/76.24 51214[127:MRR:795.0,51212.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.24 51226[127:Res:53.1,51214.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.24 51228[127:MRR:51226.0,50768.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.24 51230[127:Res:51228.0,61.1] always3(s42) || -> . % 76.04/76.24 51231[127:SSi:51230.0,731.0,50782.0,50794.0] || -> . % 76.04/76.24 51232[126:Spt:51231.0,51079.0,51080.0] || until2p7(s41)*+ -> . % 76.04/76.24 51233[126:Spt:51231.0,51079.1] || -> node4(s40)*. % 76.04/76.24 51234[126:MRR:50771.0,51233.0] || m_main_v_state(s40,c_ready)*+ -> . % 76.04/76.24 51237[126:Res:53.1,51234.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.24 51240[126:Res:51237.0,61.1] always3(s40) || -> . % 76.04/76.24 51241[126:SSi:51240.0,729.0,50762.0,50777.0,51078.0,51233.0] || -> . % 76.04/76.24 51242[125:Spt:51241.0,51077.0,51078.0] || until2p7(s40)*+ -> . % 76.04/76.24 51243[125:Spt:51241.0,51077.1] || -> node4(s39)*. % 76.04/76.24 51245[125:MRR:801.0,51243.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.24 51257[125:Res:53.1,51245.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.24 51259[125:MRR:51257.0,50745.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.24 51264[125:Res:51259.0,61.1] always3(s40) || -> . % 76.04/76.24 51265[125:SSi:51264.0,729.0,50762.0,50777.0] || -> . % 76.04/76.24 51266[124:Spt:51265.0,51075.0,51076.0] || until2p7(s39)*+ -> . % 76.04/76.24 51267[124:Spt:51265.0,51075.1] || -> node4(s38)*. % 76.04/76.24 51268[124:MRR:50748.0,51267.0] || m_main_v_state(s38,c_ready)*+ -> . % 76.04/76.24 51271[124:Res:53.1,51268.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.24 51275[124:Res:51271.0,61.1] always3(s38) || -> . % 76.04/76.24 51276[124:SSi:51275.0,727.0,50739.0,50751.0,51074.0,51267.0] || -> . % 76.04/76.24 51277[123:Spt:51276.0,51073.0,51074.0] || until2p7(s38)*+ -> . % 76.04/76.24 51278[123:Spt:51276.0,51073.1] || -> node4(s37)*. % 76.04/76.24 51280[123:MRR:807.0,51278.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.24 51291[123:Res:53.1,51280.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.24 51293[123:MRR:51291.0,50725.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.24 51295[123:Res:51293.0,61.1] always3(s38) || -> . % 76.04/76.24 51296[123:SSi:51295.0,727.0,50739.0,50751.0] || -> . % 76.04/76.24 51297[122:Spt:51296.0,51071.0,51072.0] || until2p7(s37)*+ -> . % 76.04/76.24 51298[122:Spt:51296.0,51071.1] || -> node4(s36)*. % 76.04/76.24 51299[122:MRR:50728.0,51298.0] || m_main_v_state(s36,c_ready)*+ -> . % 76.04/76.24 51303[122:Res:53.1,51299.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.24 51306[122:Res:51303.0,61.1] always3(s36) || -> . % 76.04/76.24 51307[122:SSi:51306.0,725.0,50719.0,50731.0,51070.0,51298.0] || -> . % 76.04/76.24 51308[121:Spt:51307.0,51069.0,51070.0] || until2p7(s36)*+ -> . % 76.04/76.24 51309[121:Spt:51307.0,51069.1] || -> node4(s35)*. % 76.04/76.24 51311[121:MRR:813.0,51309.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.24 51322[121:Res:53.1,51311.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.24 51324[121:MRR:51322.0,50705.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.24 51326[121:Res:51324.0,61.1] always3(s36) || -> . % 76.04/76.24 51327[121:SSi:51326.0,725.0,50719.0,50731.0] || -> . % 76.04/76.24 51328[120:Spt:51327.0,51067.0,51068.0] || until2p7(s35)*+ -> . % 76.04/76.24 51329[120:Spt:51327.0,51067.1] || -> node4(s34)*. % 76.04/76.24 51330[120:MRR:50708.0,51329.0] || m_main_v_state(s34,c_ready)*+ -> . % 76.04/76.24 51333[120:Res:53.1,51330.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.24 51336[120:Res:51333.0,61.1] always3(s34) || -> . % 76.04/76.24 51337[120:SSi:51336.0,723.0,50699.0,50714.0,51066.0,51329.0] || -> . % 76.04/76.24 51338[119:Spt:51337.0,51065.0,51066.0] || until2p7(s34)*+ -> . % 76.04/76.24 51339[119:Spt:51337.0,51065.1] || -> node4(s33)*. % 76.04/76.24 51341[119:MRR:819.0,51339.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.24 51353[119:Res:53.1,51341.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.24 51355[119:MRR:51353.0,50682.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.24 51357[119:Res:51355.0,61.1] always3(s34) || -> . % 76.04/76.24 51358[119:SSi:51357.0,723.0,50699.0,50714.0] || -> . % 76.04/76.24 51359[118:Spt:51358.0,51063.0,51064.0] || until2p7(s33)*+ -> . % 76.04/76.24 51360[118:Spt:51358.0,51063.1] || -> node4(s32)*. % 76.04/76.24 51361[118:MRR:50685.0,51360.0] || m_main_v_state(s32,c_ready)*+ -> . % 76.04/76.24 51364[118:Res:53.1,51361.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.24 51367[118:Res:51364.0,61.1] always3(s32) || -> . % 76.04/76.24 51368[118:SSi:51367.0,721.0,50676.0,50688.0,51062.0,51360.0] || -> . % 76.04/76.24 51369[117:Spt:51368.0,51061.0,51062.0] || until2p7(s32)*+ -> . % 76.04/76.24 51370[117:Spt:51368.0,51061.1] || -> node4(s31)*. % 76.04/76.24 51372[117:MRR:825.0,51370.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.24 51384[117:Res:53.1,51372.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.24 51386[117:MRR:51384.0,50662.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.24 51391[117:Res:51386.0,61.1] always3(s32) || -> . % 76.04/76.24 51392[117:SSi:51391.0,721.0,50676.0,50688.0] || -> . % 76.04/76.24 51393[116:Spt:51392.0,51059.0,51060.0] || until2p7(s31)*+ -> . % 76.04/76.24 51394[116:Spt:51392.0,51059.1] || -> node4(s30)*. % 76.04/76.24 51395[116:MRR:50665.0,51394.0] || m_main_v_state(s30,c_ready)*+ -> . % 76.04/76.24 51398[116:Res:53.1,51395.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.24 51402[116:Res:51398.0,61.1] always3(s30) || -> . % 76.04/76.24 51403[116:SSi:51402.0,719.0,50653.0,50668.0,51058.0,51394.0] || -> . % 76.04/76.24 51404[115:Spt:51403.0,51057.0,51058.0] || until2p7(s30)*+ -> . % 76.04/76.24 51405[115:Spt:51403.0,51057.1] || -> node4(s29)*. % 76.04/76.24 51407[115:MRR:831.0,51405.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.24 51418[115:Res:53.1,51407.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.24 51420[116:Spt:51418.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.24 51422[116:Res:51420.0,61.1] always3(s29) || -> . % 76.04/76.24 51423[116:SSi:51422.0,718.0,50650.0,50652.0,51056.0,51405.0] || -> . % 76.04/76.24 51424[116:Spt:51423.0,51418.0,51420.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.24 51425[116:Spt:51423.0,51418.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.24 51429[116:Res:51425.0,61.1] always3(s30) || -> . % 76.04/76.24 51430[116:SSi:51429.0,719.0,50653.0,50668.0] || -> . % 76.04/76.24 51431[114:Spt:51430.0,51055.0,51056.0] || until2p7(s29)*+ -> . % 76.04/76.24 51432[114:Spt:51430.0,51055.1] || -> node4(s28)*. % 76.04/76.24 51434[114:MRR:834.0,51432.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.24 51441[114:Res:53.1,51434.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.24 51446[115:Spt:51441.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.24 51448[115:Res:51446.0,61.1] always3(s28) || -> . % 76.04/76.24 51449[115:SSi:51448.0,717.0,50644.0,50649.0,51054.0,51432.0] || -> . % 76.04/76.24 51450[115:Spt:51449.0,51441.0,51446.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.24 51451[115:Spt:51449.0,51441.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.24 51455[115:Res:51451.0,61.1] always3(s29) || -> . % 76.04/76.24 51456[115:SSi:51455.0,718.0,50650.0,50652.0] || -> . % 76.04/76.24 51457[113:Spt:51456.0,51053.0,51054.0] || until2p7(s28)*+ -> . % 76.04/76.24 51458[113:Spt:51456.0,51053.1] || -> node4(s27)*. % 76.04/76.24 51460[113:MRR:837.0,51458.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.24 51463[113:Res:53.1,51460.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.24 51465[114:Spt:51463.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.24 51467[114:Res:51465.0,61.1] always3(s27) || -> . % 76.04/76.24 51468[114:SSi:51467.0,716.0,50641.0,50643.0,51052.0,51458.0] || -> . % 76.04/76.24 51469[114:Spt:51468.0,51463.0,51465.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.24 51470[114:Spt:51468.0,51463.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.24 51474[114:Res:51470.0,61.1] always3(s28) || -> . % 76.04/76.24 51475[114:SSi:51474.0,717.0,50644.0,50649.0] || -> . % 76.04/76.24 51476[112:Spt:51475.0,51051.0,51052.0] || until2p7(s27)*+ -> . % 76.04/76.24 51477[112:Spt:51475.0,51051.1] || -> node4(s26)*. % 76.04/76.24 51479[112:MRR:840.0,51477.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.24 51482[112:Res:53.1,51479.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.24 51484[113:Spt:51482.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.24 51486[113:Res:51484.0,61.1] always3(s26) || -> . % 76.04/76.24 51487[113:SSi:51486.0,715.0,50635.0,50640.0,51050.0,51477.0] || -> . % 76.04/76.24 51488[113:Spt:51487.0,51482.0,51484.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.24 51489[113:Spt:51487.0,51482.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.24 51493[113:Res:51489.0,61.1] always3(s27) || -> . % 76.04/76.24 51494[113:SSi:51493.0,716.0,50641.0,50643.0] || -> . % 76.04/76.24 51495[111:Spt:51494.0,51049.0,51050.0] || until2p7(s26)*+ -> . % 76.04/76.24 51496[111:Spt:51494.0,51049.1] || -> node4(s25)*. % 76.04/76.24 51498[111:MRR:843.0,51496.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.24 51501[111:Res:53.1,51498.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.24 51503[112:Spt:51501.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.24 51505[112:Res:51503.0,61.1] always3(s25) || -> . % 76.04/76.24 51506[112:SSi:51505.0,714.0,50632.0,50634.0,51048.0,51496.0] || -> . % 76.04/76.24 51507[112:Spt:51506.0,51501.0,51503.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.24 51508[112:Spt:51506.0,51501.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.24 51512[112:Res:51508.0,61.1] always3(s26) || -> . % 76.04/76.24 51513[112:SSi:51512.0,715.0,50635.0,50640.0] || -> . % 76.04/76.24 51514[110:Spt:51513.0,51047.0,51048.0] || until2p7(s25)*+ -> . % 76.04/76.24 51515[110:Spt:51513.0,51047.1] || -> node4(s24)*. % 76.04/76.24 51517[110:MRR:846.0,51515.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.24 51520[110:Res:53.1,51517.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.24 51525[111:Spt:51520.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.24 51527[111:Res:51525.0,61.1] always3(s24) || -> . % 76.04/76.24 51528[111:SSi:51527.0,713.0,50626.0,50631.0,51046.0,51515.0] || -> . % 76.04/76.24 51529[111:Spt:51528.0,51520.0,51525.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.24 51530[111:Spt:51528.0,51520.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.24 51534[111:Res:51530.0,61.1] always3(s25) || -> . % 76.04/76.24 51535[111:SSi:51534.0,714.0,50632.0,50634.0] || -> . % 76.04/76.24 51536[109:Spt:51535.0,51045.0,51046.0] || until2p7(s24)*+ -> . % 76.04/76.24 51537[109:Spt:51535.0,51045.1] || -> node4(s23)*. % 76.04/76.24 51539[109:MRR:849.0,51537.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.24 51542[109:Res:53.1,51539.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.24 51544[110:Spt:51542.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.24 51546[110:Res:51544.0,61.1] always3(s23) || -> . % 76.04/76.24 51547[110:SSi:51546.0,712.0,50623.0,50625.0,51044.0,51537.0] || -> . % 76.04/76.24 51548[110:Spt:51547.0,51542.0,51544.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.24 51549[110:Spt:51547.0,51542.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.24 51553[110:Res:51549.0,61.1] always3(s24) || -> . % 76.04/76.24 51554[110:SSi:51553.0,713.0,50626.0,50631.0] || -> . % 76.04/76.24 51555[108:Spt:51554.0,51043.0,51044.0] || until2p7(s23)*+ -> . % 76.04/76.24 51556[108:Spt:51554.0,51043.1] || -> node4(s22)*. % 76.04/76.24 51558[108:MRR:852.0,51556.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.24 51561[108:Res:53.1,51558.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.24 51563[109:Spt:51561.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.24 51565[109:Res:51563.0,61.1] always3(s22) || -> . % 76.04/76.24 51566[109:SSi:51565.0,711.0,50617.0,50622.0,51042.0,51556.0] || -> . % 76.04/76.24 51567[109:Spt:51566.0,51561.0,51563.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.24 51568[109:Spt:51566.0,51561.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.24 51572[109:Res:51568.0,61.1] always3(s23) || -> . % 76.04/76.24 51573[109:SSi:51572.0,712.0,50623.0,50625.0] || -> . % 76.04/76.24 51574[107:Spt:51573.0,51041.0,51042.0] || until2p7(s22)*+ -> . % 76.04/76.24 51575[107:Spt:51573.0,51041.1] || -> node4(s21)*. % 76.04/76.24 51577[107:MRR:855.0,51575.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.24 51580[107:Res:53.1,51577.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.24 51582[108:Spt:51580.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.24 51584[108:Res:51582.0,61.1] always3(s21) || -> . % 76.04/76.24 51585[108:SSi:51584.0,710.0,50614.0,50616.0,51040.0,51575.0] || -> . % 76.04/76.24 51586[108:Spt:51585.0,51580.0,51582.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.24 51587[108:Spt:51585.0,51580.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.24 51591[108:Res:51587.0,61.1] always3(s22) || -> . % 76.04/76.24 51592[108:SSi:51591.0,711.0,50617.0,50622.0] || -> . % 76.04/76.24 51593[106:Spt:51592.0,51039.0,51040.0] || until2p7(s21)*+ -> . % 76.04/76.24 51594[106:Spt:51592.0,51039.1] || -> node4(s20)*. % 76.04/76.24 51596[106:MRR:858.0,51594.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.24 51599[106:Res:53.1,51596.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.24 51604[107:Spt:51599.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.24 51606[107:Res:51604.0,61.1] always3(s20) || -> . % 76.04/76.24 51607[107:SSi:51606.0,709.0,50608.0,50613.0,51038.0,51594.0] || -> . % 76.04/76.24 51608[107:Spt:51607.0,51599.0,51604.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.24 51609[107:Spt:51607.0,51599.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.24 51613[107:Res:51609.0,61.1] always3(s21) || -> . % 76.04/76.24 51614[107:SSi:51613.0,710.0,50614.0,50616.0] || -> . % 76.04/76.24 51615[105:Spt:51614.0,51037.0,51038.0] || until2p7(s20)*+ -> . % 76.04/76.24 51616[105:Spt:51614.0,51037.1] || -> node4(s19)*. % 76.04/76.24 51618[105:MRR:861.0,51616.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.24 51621[105:Res:53.1,51618.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.24 51623[106:Spt:51621.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.24 51625[106:Res:51623.0,61.1] always3(s19) || -> . % 76.04/76.24 51626[106:SSi:51625.0,708.0,50605.0,50607.0,51036.0,51616.0] || -> . % 76.04/76.24 51627[106:Spt:51626.0,51621.0,51623.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.24 51628[106:Spt:51626.0,51621.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.24 51632[106:Res:51628.0,61.1] always3(s20) || -> . % 76.04/76.24 51633[106:SSi:51632.0,709.0,50608.0,50613.0] || -> . % 76.04/76.24 51634[104:Spt:51633.0,51035.0,51036.0] || until2p7(s19)*+ -> . % 76.04/76.24 51635[104:Spt:51633.0,51035.1] || -> node4(s18)*. % 76.04/76.24 51637[104:MRR:864.0,51635.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.24 51640[104:Res:53.1,51637.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.24 51642[105:Spt:51640.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.24 51644[105:Res:51642.0,61.1] always3(s18) || -> . % 76.04/76.24 51645[105:SSi:51644.0,707.0,50599.0,50604.0,51034.0,51635.0] || -> . % 76.04/76.24 51646[105:Spt:51645.0,51640.0,51642.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.24 51647[105:Spt:51645.0,51640.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.24 51651[105:Res:51647.0,61.1] always3(s19) || -> . % 76.04/76.24 51652[105:SSi:51651.0,708.0,50605.0,50607.0] || -> . % 76.04/76.24 51653[103:Spt:51652.0,51033.0,51034.0] || until2p7(s18)*+ -> . % 76.04/76.24 51654[103:Spt:51652.0,51033.1] || -> node4(s17)*. % 76.04/76.24 51656[103:MRR:867.0,51654.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.24 51659[103:Res:53.1,51656.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.24 51661[104:Spt:51659.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.24 51663[104:Res:51661.0,61.1] always3(s17) || -> . % 76.04/76.24 51664[104:SSi:51663.0,706.0,50596.0,50598.0,51032.0,51654.0] || -> . % 76.04/76.24 51665[104:Spt:51664.0,51659.0,51661.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.24 51666[104:Spt:51664.0,51659.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.24 51670[104:Res:51666.0,61.1] always3(s18) || -> . % 76.04/76.24 51671[104:SSi:51670.0,707.0,50599.0,50604.0] || -> . % 76.04/76.24 51672[102:Spt:51671.0,51031.0,51032.0] || until2p7(s17)*+ -> . % 76.04/76.24 51673[102:Spt:51671.0,51031.1] || -> node4(s16)*. % 76.04/76.24 51675[102:MRR:870.0,51673.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.24 51678[102:Res:53.1,51675.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.24 51683[103:Spt:51678.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.24 51685[103:Res:51683.0,61.1] always3(s16) || -> . % 76.04/76.24 51686[103:SSi:51685.0,705.0,50590.0,50595.0,51030.0,51673.0] || -> . % 76.04/76.24 51687[103:Spt:51686.0,51678.0,51683.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.24 51688[103:Spt:51686.0,51678.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.24 51692[103:Res:51688.0,61.1] always3(s17) || -> . % 76.04/76.24 51693[103:SSi:51692.0,706.0,50596.0,50598.0] || -> . % 76.04/76.24 51694[101:Spt:51693.0,51029.0,51030.0] || until2p7(s16)*+ -> . % 76.04/76.24 51695[101:Spt:51693.0,51029.1] || -> node4(s15)*. % 76.04/76.24 51697[101:MRR:873.0,51695.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.24 51700[101:Res:53.1,51697.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.24 51702[102:Spt:51700.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.24 51704[102:Res:51702.0,61.1] always3(s15) || -> . % 76.04/76.24 51705[102:SSi:51704.0,704.0,50587.0,50589.0,51028.0,51695.0] || -> . % 76.04/76.24 51706[102:Spt:51705.0,51700.0,51702.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.24 51707[102:Spt:51705.0,51700.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.24 51711[102:Res:51707.0,61.1] always3(s16) || -> . % 76.04/76.24 51712[102:SSi:51711.0,705.0,50590.0,50595.0] || -> . % 76.04/76.24 51713[100:Spt:51712.0,51027.0,51028.0] || until2p7(s15)*+ -> . % 76.04/76.24 51714[100:Spt:51712.0,51027.1] || -> node4(s14)*. % 76.04/76.24 51716[100:MRR:876.0,51714.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.24 51719[100:Res:53.1,51716.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.24 51721[101:Spt:51719.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.24 51723[101:Res:51721.0,61.1] always3(s14) || -> . % 76.04/76.24 51724[101:SSi:51723.0,703.0,50581.0,50586.0,51026.0,51714.0] || -> . % 76.04/76.24 51725[101:Spt:51724.0,51719.0,51721.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.24 51726[101:Spt:51724.0,51719.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.24 51730[101:Res:51726.0,61.1] always3(s15) || -> . % 76.04/76.24 51731[101:SSi:51730.0,704.0,50587.0,50589.0] || -> . % 76.04/76.24 51732[99:Spt:51731.0,51025.0,51026.0] || until2p7(s14)*+ -> . % 76.04/76.24 51733[99:Spt:51731.0,51025.1] || -> node4(s13)*. % 76.04/76.24 51735[99:MRR:879.0,51733.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.24 51738[99:Res:53.1,51735.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.24 51740[99:MRR:51738.0,51015.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.24 51742[99:Res:51740.0,61.1] always3(s14) || -> . % 76.04/76.24 51743[99:SSi:51742.0,703.0,50581.0,50586.0] || -> . % 76.04/76.24 51744[97:Spt:51743.0,50855.1,50857.0] || xuntil6(s48)* -> . % 76.04/76.24 51745[97:Spt:51743.0,50855.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.24 51748[97:Res:51745.0,61.1] always3(s48) || -> . % 76.04/76.24 51749[97:SSi:51748.0,737.0,50845.0] || -> . % 76.04/76.24 51750[95:Spt:51749.0,50842.2,50844.0] || xuntil6(s47)*+ -> . % 76.04/76.24 51751[95:Spt:51749.0,50842.0,50842.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.24 51752[95:Res:53.1,51751.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.24 51754[95:MRR:51752.0,50831.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.24 51756[95:Res:51754.0,61.1] always3(s48) || -> . % 76.04/76.24 51757[95:SSi:51756.0,737.0] || -> . % 76.04/76.24 51758[94:Spt:51757.0,50835.1,50840.0] || xuntil6(s46)* -> . % 76.04/76.24 51759[94:Spt:51757.0,50835.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.24 51762[94:Res:51759.0,61.1] always3(s46) || -> . % 76.04/76.24 51763[94:SSi:51762.0,735.0,50825.0] || -> . % 76.04/76.24 51764[92:Spt:51763.0,50816.2,50824.0] || xuntil6(s45)*+ -> . % 76.04/76.24 51765[92:Spt:51763.0,50816.0,50816.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.24 51766[92:Res:53.1,51765.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.24 51768[92:MRR:51766.0,50808.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.24 51770[92:Res:51768.0,61.1] always3(s46) || -> . % 76.04/76.24 51771[92:SSi:51770.0,735.0] || -> . % 76.04/76.24 51772[91:Spt:51771.0,50812.1,50814.0] || xuntil6(s44)* -> . % 76.04/76.24 51773[91:Spt:51771.0,50812.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.24 51776[91:Res:51773.0,61.1] always3(s44) || -> . % 76.04/76.24 51777[91:SSi:51776.0,733.0,50802.0] || -> . % 76.04/76.24 51778[89:Spt:51777.0,50796.2,50801.0] || xuntil6(s43)*+ -> . % 76.04/76.24 51779[89:Spt:51777.0,50796.0,50796.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.24 51780[89:Res:53.1,51779.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.24 51782[89:MRR:51780.0,50788.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.24 51785[89:Res:51782.0,61.1] always3(s44) || -> . % 76.04/76.24 51786[89:SSi:51785.0,733.0] || -> . % 76.04/76.24 51787[88:Spt:51786.0,50792.1,50794.0] || xuntil6(s42)* -> . % 76.04/76.24 51788[88:Spt:51786.0,50792.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.24 51791[88:Res:51788.0,61.1] always3(s42) || -> . % 76.04/76.24 51792[88:SSi:51791.0,731.0,50782.0] || -> . % 76.04/76.24 51793[86:Spt:51792.0,50779.2,50781.0] || xuntil6(s41)*+ -> . % 76.04/76.24 51794[86:Spt:51792.0,50779.0,50779.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.24 51795[86:Res:53.1,51794.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.24 51797[86:MRR:51795.0,50768.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.24 51799[86:Res:51797.0,61.1] always3(s42) || -> . % 76.04/76.24 51800[86:SSi:51799.0,731.0] || -> . % 76.04/76.24 51801[85:Spt:51800.0,50772.1,50777.0] || xuntil6(s40)* -> . % 76.04/76.24 51802[85:Spt:51800.0,50772.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.24 51805[85:Res:51802.0,61.1] always3(s40) || -> . % 76.04/76.24 51806[85:SSi:51805.0,729.0,50762.0] || -> . % 76.04/76.24 51807[83:Spt:51806.0,50753.2,50761.0] || xuntil6(s39)*+ -> . % 76.04/76.24 51808[83:Spt:51806.0,50753.0,50753.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.24 51809[83:Res:53.1,51808.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.24 51811[83:MRR:51809.0,50745.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.24 51814[83:Res:51811.0,61.1] always3(s40) || -> . % 76.04/76.24 51815[83:SSi:51814.0,729.0] || -> . % 76.04/76.24 51816[82:Spt:51815.0,50749.1,50751.0] || xuntil6(s38)* -> . % 76.04/76.24 51817[82:Spt:51815.0,50749.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.24 51820[82:Res:51817.0,61.1] always3(s38) || -> . % 76.04/76.24 51821[82:SSi:51820.0,727.0,50739.0] || -> . % 76.04/76.24 51822[80:Spt:51821.0,50733.2,50738.0] || xuntil6(s37)*+ -> . % 76.04/76.24 51823[80:Spt:51821.0,50733.0,50733.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.24 51824[80:Res:53.1,51823.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.24 51826[80:MRR:51824.0,50725.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.24 51828[80:Res:51826.0,61.1] always3(s38) || -> . % 76.04/76.24 51829[80:SSi:51828.0,727.0] || -> . % 76.04/76.24 51830[79:Spt:51829.0,50729.1,50731.0] || xuntil6(s36)* -> . % 76.04/76.24 51831[79:Spt:51829.0,50729.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.24 51834[79:Res:51831.0,61.1] always3(s36) || -> . % 76.04/76.24 51835[79:SSi:51834.0,725.0,50719.0] || -> . % 76.04/76.24 51836[77:Spt:51835.0,50716.2,50718.0] || xuntil6(s35)*+ -> . % 76.04/76.24 51837[77:Spt:51835.0,50716.0,50716.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.24 51838[77:Res:53.1,51837.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.24 51840[77:MRR:51838.0,50705.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.24 51842[77:Res:51840.0,61.1] always3(s36) || -> . % 76.04/76.24 51843[77:SSi:51842.0,725.0] || -> . % 76.04/76.24 51844[76:Spt:51843.0,50709.1,50714.0] || xuntil6(s34)* -> . % 76.04/76.24 51845[76:Spt:51843.0,50709.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.24 51848[76:Res:51845.0,61.1] always3(s34) || -> . % 76.04/76.24 51849[76:SSi:51848.0,723.0,50699.0] || -> . % 76.04/76.24 51850[74:Spt:51849.0,50690.2,50698.0] || xuntil6(s33)*+ -> . % 76.04/76.24 51851[74:Spt:51849.0,50690.0,50690.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.24 51852[74:Res:53.1,51851.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.24 51854[74:MRR:51852.0,50682.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.24 51856[74:Res:51854.0,61.1] always3(s34) || -> . % 76.04/76.24 51857[74:SSi:51856.0,723.0] || -> . % 76.04/76.24 51858[73:Spt:51857.0,50686.1,50688.0] || xuntil6(s32)* -> . % 76.04/76.24 51859[73:Spt:51857.0,50686.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.24 51862[73:Res:51859.0,61.1] always3(s32) || -> . % 76.04/76.24 51863[73:SSi:51862.0,721.0,50676.0] || -> . % 76.04/76.24 51864[71:Spt:51863.0,50670.2,50675.0] || xuntil6(s31)*+ -> . % 76.04/76.24 51865[71:Spt:51863.0,50670.0,50670.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.24 51866[71:Res:53.1,51865.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.24 51868[71:MRR:51866.0,50662.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.24 51870[71:Res:51868.0,61.1] always3(s32) || -> . % 76.04/76.24 51871[71:SSi:51870.0,721.0] || -> . % 76.04/76.24 51872[70:Spt:51871.0,50666.1,50668.0] || xuntil6(s30)* -> . % 76.04/76.24 51873[70:Spt:51871.0,50666.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.24 51876[70:Res:51873.0,61.1] always3(s30) || -> . % 76.04/76.24 51877[70:SSi:51876.0,719.0,50653.0] || -> . % 76.04/76.24 51878[68:Spt:51877.0,50651.2,50652.0] || xuntil6(s29)*+ -> . % 76.04/76.24 51879[68:Spt:51877.0,50651.0,50651.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.24 51880[68:Res:53.1,51879.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.24 51882[69:Spt:51880.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.24 51884[69:Res:51882.0,61.1] always3(s30) || -> . % 76.04/76.24 51885[69:SSi:51884.0,719.0] || -> . % 76.04/76.24 51886[69:Spt:51885.0,51880.1,51882.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.24 51887[69:Spt:51885.0,51880.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.24 51890[69:Res:51887.0,61.1] always3(s29) || -> . % 76.04/76.24 51891[69:SSi:51890.0,718.0,50650.0] || -> . % 76.04/76.24 51892[67:Spt:51891.0,50645.2,50649.0] || xuntil6(s28)*+ -> . % 76.04/76.24 51893[67:Spt:51891.0,50645.0,50645.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.24 51894[67:Res:53.1,51893.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.24 51896[68:Spt:51894.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.24 51898[68:Res:51896.0,61.1] always3(s29) || -> . % 76.04/76.24 51899[68:SSi:51898.0,718.0] || -> . % 76.04/76.24 51900[68:Spt:51899.0,51894.1,51896.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.24 51901[68:Spt:51899.0,51894.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.24 51904[68:Res:51901.0,61.1] always3(s28) || -> . % 76.04/76.24 51905[68:SSi:51904.0,717.0,50644.0] || -> . % 76.04/76.24 51906[66:Spt:51905.0,50642.2,50643.0] || xuntil6(s27)*+ -> . % 76.04/76.24 51907[66:Spt:51905.0,50642.0,50642.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.24 51908[66:Res:53.1,51907.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.24 51910[67:Spt:51908.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.24 51912[67:Res:51910.0,61.1] always3(s28) || -> . % 76.04/76.24 51913[67:SSi:51912.0,717.0] || -> . % 76.04/76.24 51914[67:Spt:51913.0,51908.1,51910.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.24 51915[67:Spt:51913.0,51908.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.24 51918[67:Res:51915.0,61.1] always3(s27) || -> . % 76.04/76.24 51919[67:SSi:51918.0,716.0,50641.0] || -> . % 76.04/76.24 51920[65:Spt:51919.0,50636.2,50640.0] || xuntil6(s26)*+ -> . % 76.04/76.24 51921[65:Spt:51919.0,50636.0,50636.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.24 51922[65:Res:53.1,51921.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.24 51924[66:Spt:51922.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.24 51926[66:Res:51924.0,61.1] always3(s27) || -> . % 76.04/76.24 51927[66:SSi:51926.0,716.0] || -> . % 76.04/76.24 51928[66:Spt:51927.0,51922.1,51924.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.24 51929[66:Spt:51927.0,51922.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.24 51932[66:Res:51929.0,61.1] always3(s26) || -> . % 76.04/76.24 51933[66:SSi:51932.0,715.0,50635.0] || -> . % 76.04/76.24 51934[64:Spt:51933.0,50633.2,50634.0] || xuntil6(s25)*+ -> . % 76.04/76.24 51935[64:Spt:51933.0,50633.0,50633.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.24 51936[64:Res:53.1,51935.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.24 51938[65:Spt:51936.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.24 51940[65:Res:51938.0,61.1] always3(s26) || -> . % 76.04/76.24 51941[65:SSi:51940.0,715.0] || -> . % 76.04/76.24 51942[65:Spt:51941.0,51936.1,51938.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.24 51943[65:Spt:51941.0,51936.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.24 51946[65:Res:51943.0,61.1] always3(s25) || -> . % 76.04/76.24 51947[65:SSi:51946.0,714.0,50632.0] || -> . % 76.04/76.24 51948[63:Spt:51947.0,50627.2,50631.0] || xuntil6(s24)*+ -> . % 76.04/76.24 51949[63:Spt:51947.0,50627.0,50627.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.24 51950[63:Res:53.1,51949.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.24 51952[64:Spt:51950.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.24 51954[64:Res:51952.0,61.1] always3(s25) || -> . % 76.04/76.24 51955[64:SSi:51954.0,714.0] || -> . % 76.04/76.24 51956[64:Spt:51955.0,51950.1,51952.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.24 51957[64:Spt:51955.0,51950.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.24 51960[64:Res:51957.0,61.1] always3(s24) || -> . % 76.04/76.24 51961[64:SSi:51960.0,713.0,50626.0] || -> . % 76.04/76.24 51962[62:Spt:51961.0,50624.2,50625.0] || xuntil6(s23)*+ -> . % 76.04/76.24 51963[62:Spt:51961.0,50624.0,50624.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.24 51964[62:Res:53.1,51963.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.24 51966[63:Spt:51964.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.24 51968[63:Res:51966.0,61.1] always3(s24) || -> . % 76.04/76.24 51969[63:SSi:51968.0,713.0] || -> . % 76.04/76.24 51970[63:Spt:51969.0,51964.1,51966.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.24 51971[63:Spt:51969.0,51964.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.24 51974[63:Res:51971.0,61.1] always3(s23) || -> . % 76.04/76.24 51975[63:SSi:51974.0,712.0,50623.0] || -> . % 76.04/76.24 51976[61:Spt:51975.0,50618.2,50622.0] || xuntil6(s22)*+ -> . % 76.04/76.24 51977[61:Spt:51975.0,50618.0,50618.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.24 51978[61:Res:53.1,51977.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.24 51983[62:Spt:51978.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.24 51985[62:Res:51983.0,61.1] always3(s22) || -> . % 76.04/76.24 51986[62:SSi:51985.0,711.0,50617.0] || -> . % 76.04/76.24 51987[62:Spt:51986.0,51978.0,51983.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.24 51988[62:Spt:51986.0,51978.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.24 51992[62:Res:51988.0,61.1] always3(s23) || -> . % 76.04/76.24 51993[62:SSi:51992.0,712.0] || -> . % 76.04/76.24 51994[60:Spt:51993.0,50615.2,50616.0] || xuntil6(s21)*+ -> . % 76.04/76.24 51995[60:Spt:51993.0,50615.0,50615.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.24 51996[60:Res:53.1,51995.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.24 51998[61:Spt:51996.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.24 52000[61:Res:51998.0,61.1] always3(s22) || -> . % 76.04/76.24 52001[61:SSi:52000.0,711.0] || -> . % 76.04/76.24 52002[61:Spt:52001.0,51996.1,51998.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.24 52003[61:Spt:52001.0,51996.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.24 52006[61:Res:52003.0,61.1] always3(s21) || -> . % 76.04/76.24 52007[61:SSi:52006.0,710.0,50614.0] || -> . % 76.04/76.24 52008[59:Spt:52007.0,50609.2,50613.0] || xuntil6(s20)*+ -> . % 76.04/76.24 52009[59:Spt:52007.0,50609.0,50609.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.24 52010[59:Res:53.1,52009.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.24 52012[60:Spt:52010.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.24 52014[60:Res:52012.0,61.1] always3(s21) || -> . % 76.04/76.24 52015[60:SSi:52014.0,710.0] || -> . % 76.04/76.24 52016[60:Spt:52015.0,52010.1,52012.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.24 52017[60:Spt:52015.0,52010.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.24 52020[60:Res:52017.0,61.1] always3(s20) || -> . % 76.04/76.24 52021[60:SSi:52020.0,709.0,50608.0] || -> . % 76.04/76.24 52022[58:Spt:52021.0,50606.2,50607.0] || xuntil6(s19)*+ -> . % 76.04/76.24 52023[58:Spt:52021.0,50606.0,50606.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.24 52024[58:Res:53.1,52023.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.24 52029[59:Spt:52024.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.24 52031[59:Res:52029.0,61.1] always3(s19) || -> . % 76.04/76.24 52032[59:SSi:52031.0,708.0,50605.0] || -> . % 76.04/76.24 52033[59:Spt:52032.0,52024.0,52029.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.24 52034[59:Spt:52032.0,52024.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.24 52038[59:Res:52034.0,61.1] always3(s20) || -> . % 76.04/76.24 52039[59:SSi:52038.0,709.0] || -> . % 76.04/76.24 52040[57:Spt:52039.0,50600.2,50604.0] || xuntil6(s18)*+ -> . % 76.04/76.24 52041[57:Spt:52039.0,50600.0,50600.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.24 52042[57:Res:53.1,52041.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.24 52044[58:Spt:52042.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.24 52046[58:Res:52044.0,61.1] always3(s19) || -> . % 76.04/76.24 52047[58:SSi:52046.0,708.0] || -> . % 76.04/76.24 52048[58:Spt:52047.0,52042.1,52044.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.24 52049[58:Spt:52047.0,52042.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.24 52052[58:Res:52049.0,61.1] always3(s18) || -> . % 76.04/76.24 52053[58:SSi:52052.0,707.0,50599.0] || -> . % 76.04/76.24 52054[56:Spt:52053.0,50597.2,50598.0] || xuntil6(s17)*+ -> . % 76.04/76.24 52055[56:Spt:52053.0,50597.0,50597.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.24 52056[56:Res:53.1,52055.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.24 52058[57:Spt:52056.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.24 52060[57:Res:52058.0,61.1] always3(s18) || -> . % 76.04/76.24 52061[57:SSi:52060.0,707.0] || -> . % 76.04/76.24 52062[57:Spt:52061.0,52056.1,52058.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.24 52063[57:Spt:52061.0,52056.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.24 52066[57:Res:52063.0,61.1] always3(s17) || -> . % 76.04/76.24 52067[57:SSi:52066.0,706.0,50596.0] || -> . % 76.04/76.24 52068[55:Spt:52067.0,50591.2,50595.0] || xuntil6(s16)*+ -> . % 76.04/76.24 52069[55:Spt:52067.0,50591.0,50591.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.24 52070[55:Res:53.1,52069.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.24 52075[56:Spt:52070.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.24 52077[56:Res:52075.0,61.1] always3(s16) || -> . % 76.04/76.24 52078[56:SSi:52077.0,705.0,50590.0] || -> . % 76.04/76.24 52079[56:Spt:52078.0,52070.0,52075.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.24 52080[56:Spt:52078.0,52070.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.24 52084[56:Res:52080.0,61.1] always3(s17) || -> . % 76.04/76.24 52085[56:SSi:52084.0,706.0] || -> . % 76.04/76.24 52086[54:Spt:52085.0,50588.2,50589.0] || xuntil6(s15)*+ -> . % 76.04/76.24 52087[54:Spt:52085.0,50588.0,50588.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.24 52088[54:Res:53.1,52087.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.24 52090[55:Spt:52088.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.24 52092[55:Res:52090.0,61.1] always3(s16) || -> . % 76.04/76.24 52093[55:SSi:52092.0,705.0] || -> . % 76.04/76.24 52094[55:Spt:52093.0,52088.1,52090.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.24 52095[55:Spt:52093.0,52088.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.24 52098[55:Res:52095.0,61.1] always3(s15) || -> . % 76.04/76.24 52099[55:SSi:52098.0,704.0,50587.0] || -> . % 76.04/76.24 52100[53:Spt:52099.0,50582.2,50586.0] || xuntil6(s14)*+ -> . % 76.04/76.24 52101[53:Spt:52099.0,50582.0,50582.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.24 52102[53:Res:53.1,52101.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.24 52104[54:Spt:52102.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.24 52106[54:Res:52104.0,61.1] always3(s15) || -> . % 76.04/76.24 52107[54:SSi:52106.0,704.0] || -> . % 76.04/76.24 52108[54:Spt:52107.0,52102.1,52104.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.24 52109[54:Spt:52107.0,52102.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.24 52112[54:Res:52109.0,61.1] always3(s14) || -> . % 76.04/76.24 52113[54:SSi:52112.0,703.0,50581.0] || -> . % 76.04/76.24 52114[52:Spt:52113.0,50579.2,50580.0] || xuntil6(s13)*+ -> . % 76.04/76.24 52115[52:Spt:52113.0,50579.0,50579.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.24 52116[52:Res:53.1,52115.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.24 52121[53:Spt:52116.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.24 52123[53:Res:52121.0,61.1] always3(s13) || -> . % 76.04/76.24 52124[53:SSi:52123.0,702.0,50578.0] || -> . % 76.04/76.24 52125[53:Spt:52124.0,52116.0,52121.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.24 52126[53:Spt:52124.0,52116.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.24 52133[53:Res:52126.0,61.1] always3(s14) || -> . % 76.04/76.24 52134[53:SSi:52133.0,703.0] || -> . % 76.04/76.24 52135[51:Spt:52134.0,50573.2,50577.0] || xuntil6(s12)*+ -> . % 76.04/76.24 52136[51:Spt:52134.0,50573.0,50573.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.24 52137[51:Res:53.1,52136.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.24 52139[52:Spt:52137.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.24 52141[52:Res:52139.0,61.1] always3(s12) || -> . % 76.04/76.24 52142[52:SSi:52141.0,701.0,50572.0] || -> . % 76.04/76.24 52143[52:Spt:52142.0,52137.0,52139.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.24 52144[52:Spt:52142.0,52137.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.24 52148[52:Res:52144.0,61.1] always3(s13) || -> . % 76.04/76.24 52149[52:SSi:52148.0,702.0] || -> . % 76.04/76.24 52150[50:Spt:52149.0,50570.2,50571.0] || xuntil6(s11)*+ -> . % 76.04/76.24 52151[50:Spt:52149.0,50570.0,50570.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.24 52152[50:Res:53.1,52151.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.24 52154[51:Spt:52152.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.24 52156[51:Res:52154.0,61.1] always3(s11) || -> . % 76.04/76.24 52157[51:SSi:52156.0,700.0,50569.0] || -> . % 76.04/76.24 52158[51:Spt:52157.0,52152.0,52154.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.24 52159[51:Spt:52157.0,52152.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.24 52163[51:Res:52159.0,61.1] always3(s12) || -> . % 76.04/76.24 52164[51:SSi:52163.0,701.0] || -> . % 76.04/76.24 52165[49:Spt:52164.0,50564.2,50568.0] || xuntil6(s10)*+ -> . % 76.04/76.24 52166[49:Spt:52164.0,50564.0,50564.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.24 52167[49:Res:53.1,52166.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.24 52172[50:Spt:52167.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.24 52174[50:Res:52172.0,61.1] always3(s10) || -> . % 76.04/76.24 52175[50:SSi:52174.0,699.0,50563.0] || -> . % 76.04/76.24 52176[50:Spt:52175.0,52167.0,52172.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.24 52177[50:Spt:52175.0,52167.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.24 52181[50:Res:52177.0,61.1] always3(s11) || -> . % 76.04/76.24 52182[50:SSi:52181.0,700.0] || -> . % 76.04/76.24 52183[48:Spt:52182.0,50561.2,50562.0] || xuntil6(s9)*+ -> . % 76.04/76.24 52184[48:Spt:52182.0,50561.0,50561.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.24 52185[48:Res:53.1,52184.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.24 52187[49:Spt:52185.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.24 52189[49:Res:52187.0,61.1] always3(s9) || -> . % 76.04/76.24 52190[49:SSi:52189.0,698.0,50560.0] || -> . % 76.04/76.24 52191[49:Spt:52190.0,52185.0,52187.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.24 52192[49:Spt:52190.0,52185.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.24 52196[49:Res:52192.0,61.1] always3(s10) || -> . % 76.04/76.24 52197[49:SSi:52196.0,699.0] || -> . % 76.04/76.24 52198[47:Spt:52197.0,50555.2,50559.0] || xuntil6(s8)*+ -> . % 76.04/76.24 52199[47:Spt:52197.0,50555.0,50555.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.24 52200[47:Res:53.1,52199.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.24 52202[48:Spt:52200.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.24 52204[48:Res:52202.0,61.1] always3(s8) || -> . % 76.04/76.24 52205[48:SSi:52204.0,697.0,50554.0] || -> . % 76.04/76.24 52206[48:Spt:52205.0,52200.0,52202.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.24 52207[48:Spt:52205.0,52200.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.24 52211[48:Res:52207.0,61.1] always3(s9) || -> . % 76.04/76.24 52212[48:SSi:52211.0,698.0] || -> . % 76.04/76.24 52213[46:Spt:52212.0,50552.2,50553.0] || xuntil6(s7)*+ -> . % 76.04/76.24 52214[46:Spt:52212.0,50552.0,50552.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.24 52215[46:Res:53.1,52214.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.24 52220[47:Spt:52215.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.24 52222[47:Res:52220.0,61.1] always3(s7) || -> . % 76.04/76.24 52223[47:SSi:52222.0,696.0,50551.0] || -> . % 76.04/76.24 52224[47:Spt:52223.0,52215.0,52220.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.24 52225[47:Spt:52223.0,52215.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.24 52229[47:Res:52225.0,61.1] always3(s8) || -> . % 76.04/76.24 52230[47:SSi:52229.0,697.0] || -> . % 76.04/76.24 52231[45:Spt:52230.0,50546.2,50550.0] || xuntil6(s6)*+ -> . % 76.04/76.24 52232[45:Spt:52230.0,50546.0,50546.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.24 52233[45:Res:53.1,52232.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.24 52235[46:Spt:52233.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.24 52237[46:Res:52235.0,61.1] always3(s6) || -> . % 76.04/76.24 52238[46:SSi:52237.0,695.0,50545.0] || -> . % 76.04/76.24 52239[46:Spt:52238.0,52233.0,52235.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.24 52240[46:Spt:52238.0,52233.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.24 52244[46:Res:52240.0,61.1] always3(s7) || -> . % 76.04/76.24 52245[46:SSi:52244.0,696.0] || -> . % 76.04/76.24 52246[44:Spt:52245.0,50543.2,50544.0] || xuntil6(s5)*+ -> . % 76.04/76.24 52247[44:Spt:52245.0,50543.0,50543.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.24 52248[44:Res:53.1,52247.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.24 52250[45:Spt:52248.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.24 52252[45:Res:52250.0,61.1] always3(s5) || -> . % 76.04/76.24 52253[45:SSi:52252.0,694.0,50542.0] || -> . % 76.04/76.24 52254[45:Spt:52253.0,52248.0,52250.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.24 52255[45:Spt:52253.0,52248.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.24 52259[45:Res:52255.0,61.1] always3(s6) || -> . % 76.04/76.24 52260[45:SSi:52259.0,695.0] || -> . % 76.04/76.24 52261[43:Spt:52260.0,50537.2,50541.0] || xuntil6(s4)*+ -> . % 76.04/76.24 52262[43:Spt:52260.0,50537.0,50537.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.24 52263[43:Res:53.1,52262.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.24 52268[44:Spt:52263.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.24 52270[44:Res:52268.0,61.1] always3(s4) || -> . % 76.04/76.24 52271[44:SSi:52270.0,693.0,50536.0] || -> . % 76.04/76.24 52272[44:Spt:52271.0,52263.0,52268.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.24 52273[44:Spt:52271.0,52263.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.24 52277[44:Res:52273.0,61.1] always3(s5) || -> . % 76.04/76.24 52278[44:SSi:52277.0,694.0] || -> . % 76.04/76.24 52279[42:Spt:52278.0,50534.2,50535.0] || xuntil6(s3)*+ -> . % 76.04/76.24 52280[42:Spt:52278.0,50534.0,50534.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.24 52281[42:Res:53.1,52280.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.24 52283[43:Spt:52281.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.24 52285[43:Res:52283.0,61.1] always3(s3) || -> . % 76.04/76.24 52286[43:SSi:52285.0,692.0,50533.0] || -> . % 76.04/76.24 52287[43:Spt:52286.0,52281.0,52283.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.24 52288[43:Spt:52286.0,52281.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.24 52292[43:Res:52288.0,61.1] always3(s4) || -> . % 76.04/76.24 52293[43:SSi:52292.0,693.0] || -> . % 76.04/76.24 52294[41:Spt:52293.0,50528.2,50532.0] || xuntil6(s2)*+ -> . % 76.04/76.24 52295[41:Spt:52293.0,50528.0,50528.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.24 52296[41:Res:53.1,52295.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.24 52298[42:Spt:52296.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.24 52300[42:Res:52298.0,61.1] always3(s2) || -> . % 76.04/76.24 52301[42:SSi:52300.0,691.0,50527.0] || -> . % 76.04/76.24 52302[42:Spt:52301.0,52296.0,52298.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.24 52303[42:Spt:52301.0,52296.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.24 52307[42:Res:52303.0,61.1] always3(s3) || -> . % 76.04/76.24 52308[42:SSi:52307.0,692.0] || -> . % 76.04/76.24 52309[40:Spt:52308.0,50522.2,50526.0] || xuntil6(s1)*+ -> . % 76.04/76.24 52310[40:Spt:52308.0,50522.0,50522.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.24 52311[40:Res:53.1,52310.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.24 52316[41:Spt:52311.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.24 52318[41:Res:52316.0,61.1] always3(s1) || -> . % 76.04/76.24 52319[41:SSi:52318.0,690.0,50521.0] || -> . % 76.04/76.24 52320[41:Spt:52319.0,52311.0,52316.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.24 52321[41:Spt:52319.0,52311.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.24 52326[41:Res:52321.0,61.1] always3(s2) || -> . % 76.04/76.24 52327[41:SSi:52326.0,691.0] || -> . % 76.04/76.24 52328[39:Spt:52327.0,74.0,50520.0] || xuntil6(s0)*+ -> . % 76.04/76.24 52329[39:Spt:52327.0,74.1] || -> node4(s0)*. % 76.04/76.24 52330[39:MRR:758.1,52328.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.24 52332[39:Res:52330.0,61.1] always3(s1) || -> . % 76.04/76.24 52333[39:SSi:52332.0,690.0] || -> . % 76.04/76.24 52334[38:Spt:52333.0,50510.0,50514.0] || trans(s49,s13)*+ -> . % 76.04/76.24 52335[38:Spt:52333.0,50510.1,50510.2,50510.3,50510.4,50510.5,50510.6,50510.7,50510.8,50510.9,50510.10,50510.11,50510.12,50510.13] || -> trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.24 52336[38:MRR:50512.0,52334.0] || -> trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.24 52338[38:MRR:50513.1,52334.0] xuntil6(s49) || -> trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.24 52339[39:Spt:52335.0] || -> trans(s49,s12)*. % 76.04/76.24 52340[39:Res:52339.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s12)*. % 76.04/76.24 52342[39:Res:52339.0,60.0] || -> node2(s49,s12)*. % 76.04/76.24 52343[39:SSi:52340.1,50.0,738.0] xuntil6(s49) || -> until2p7(s12)*. % 76.04/76.24 52344[39:Res:52342.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)*. % 76.04/76.24 52345[40:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.24 52346[40:MRR:176.0,52345.0] || -> until5(s1)*. % 76.04/76.24 52347[40:MRR:50969.0,52346.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.24 52351[41:Spt:52347.2] || -> xuntil6(s1)*. % 76.04/76.24 52352[41:MRR:175.0,52351.0] || -> until5(s2)*. % 76.04/76.24 52353[41:MRR:50965.0,52352.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.24 52354[42:Spt:52353.2] || -> xuntil6(s2)*. % 76.04/76.24 52355[42:MRR:174.0,52354.0] || -> until5(s3)*. % 76.04/76.24 52356[42:MRR:50961.0,52355.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.24 52357[43:Spt:52356.2] || -> xuntil6(s3)*. % 76.04/76.24 52358[43:MRR:173.0,52357.0] || -> until5(s4)*. % 76.04/76.24 52359[43:MRR:50960.0,52358.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.24 52360[44:Spt:52359.2] || -> xuntil6(s4)*. % 76.04/76.24 52361[44:MRR:172.0,52360.0] || -> until5(s5)*. % 76.04/76.24 52362[44:MRR:50953.0,52361.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.24 52366[45:Spt:52362.2] || -> xuntil6(s5)*. % 76.04/76.24 52367[45:MRR:171.0,52366.0] || -> until5(s6)*. % 76.04/76.24 52368[45:MRR:50949.0,52367.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.24 52369[46:Spt:52368.2] || -> xuntil6(s6)*. % 76.04/76.24 52370[46:MRR:170.0,52369.0] || -> until5(s7)*. % 76.04/76.24 52371[46:MRR:50945.0,52370.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.24 52375[47:Spt:52371.2] || -> xuntil6(s7)*. % 76.04/76.24 52376[47:MRR:169.0,52375.0] || -> until5(s8)*. % 76.04/76.24 52377[47:MRR:50941.0,52376.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.24 52378[48:Spt:52377.2] || -> xuntil6(s8)*. % 76.04/76.24 52379[48:MRR:168.0,52378.0] || -> until5(s9)*. % 76.04/76.24 52380[48:MRR:50940.0,52379.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.24 52384[49:Spt:52380.2] || -> xuntil6(s9)*. % 76.04/76.24 52385[49:MRR:167.0,52384.0] || -> until5(s10)*. % 76.04/76.24 52386[49:MRR:50933.0,52385.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.24 52387[50:Spt:52386.2] || -> xuntil6(s10)*. % 76.04/76.24 52388[50:MRR:166.0,52387.0] || -> until5(s11)*. % 76.04/76.24 52389[50:MRR:50929.0,52388.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.24 52393[51:Spt:52389.2] || -> xuntil6(s11)*. % 76.04/76.24 52394[51:MRR:165.0,52393.0] || -> until5(s12)*. % 76.04/76.24 52395[51:MRR:50925.0,52394.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.24 52396[52:Spt:52395.2] || -> xuntil6(s12)*. % 76.04/76.24 52397[52:MRR:164.0,52396.0] || -> until5(s13)*. % 76.04/76.24 52398[52:MRR:50921.0,52397.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.24 52402[53:Spt:52398.2] || -> xuntil6(s13)*. % 76.04/76.24 52403[53:MRR:163.0,52402.0] || -> until5(s14)*. % 76.04/76.24 52404[53:MRR:50920.0,52403.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.24 52405[54:Spt:52404.2] || -> xuntil6(s14)*. % 76.04/76.24 52406[54:MRR:162.0,52405.0] || -> until5(s15)*. % 76.04/76.24 52407[54:MRR:50910.0,52406.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.24 52411[55:Spt:52407.2] || -> xuntil6(s15)*. % 76.04/76.24 52412[55:MRR:161.0,52411.0] || -> until5(s16)*. % 76.04/76.24 52413[55:MRR:50909.0,52412.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.24 52414[56:Spt:52413.2] || -> xuntil6(s16)*. % 76.04/76.24 52415[56:MRR:160.0,52414.0] || -> until5(s17)*. % 76.04/76.24 52416[56:MRR:50905.0,52415.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.24 52420[57:Spt:52416.2] || -> xuntil6(s17)*. % 76.04/76.24 52421[57:MRR:159.0,52420.0] || -> until5(s18)*. % 76.04/76.24 52422[57:MRR:50898.0,52421.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.24 52423[58:Spt:52422.2] || -> xuntil6(s18)*. % 76.04/76.24 52424[58:MRR:158.0,52423.0] || -> until5(s19)*. % 76.04/76.24 52425[58:MRR:50894.0,52424.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.24 52429[59:Spt:52425.2] || -> xuntil6(s19)*. % 76.04/76.24 52430[59:MRR:157.0,52429.0] || -> until5(s20)*. % 76.04/76.24 52431[59:MRR:50893.0,52430.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.24 52432[60:Spt:52431.2] || -> xuntil6(s20)*. % 76.04/76.24 52433[60:MRR:156.0,52432.0] || -> until5(s21)*. % 76.04/76.24 52434[60:MRR:50889.0,52433.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.24 52438[61:Spt:52434.2] || -> xuntil6(s21)*. % 76.04/76.24 52439[61:MRR:155.0,52438.0] || -> until5(s22)*. % 76.04/76.24 52440[61:MRR:50882.0,52439.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.24 52441[62:Spt:52440.2] || -> xuntil6(s22)*. % 76.04/76.24 52442[62:MRR:154.0,52441.0] || -> until5(s23)*. % 76.04/76.24 52443[62:MRR:50878.0,52442.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.24 52447[63:Spt:52443.2] || -> xuntil6(s23)*. % 76.04/76.24 52448[63:MRR:153.0,52447.0] || -> until5(s24)*. % 76.04/76.24 52449[63:MRR:50874.0,52448.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.24 52450[64:Spt:52449.2] || -> xuntil6(s24)*. % 76.04/76.24 52451[64:MRR:152.0,52450.0] || -> until5(s25)*. % 76.04/76.24 52452[64:MRR:50870.0,52451.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.24 52456[65:Spt:52452.2] || -> xuntil6(s25)*. % 76.04/76.24 52457[65:MRR:151.0,52456.0] || -> until5(s26)*. % 76.04/76.24 52458[65:MRR:50869.0,52457.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.24 52459[66:Spt:52458.2] || -> xuntil6(s26)*. % 76.04/76.24 52460[66:MRR:150.0,52459.0] || -> until5(s27)*. % 76.04/76.24 52461[66:MRR:50865.0,52460.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.24 52465[67:Spt:52461.2] || -> xuntil6(s27)*. % 76.04/76.24 52466[67:MRR:149.0,52465.0] || -> until5(s28)*. % 76.04/76.24 52467[67:MRR:50864.0,52466.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.24 52468[68:Spt:52467.2] || -> xuntil6(s28)*. % 76.04/76.24 52469[68:MRR:148.0,52468.0] || -> until5(s29)*. % 76.04/76.24 52470[68:MRR:50863.0,52469.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.24 52474[69:Spt:52470.2] || -> xuntil6(s29)*. % 76.04/76.24 52475[69:MRR:147.0,52474.0] || -> until5(s30)*. % 76.04/76.24 52476[69:MRR:49179.0,52475.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.24 52477[70:Spt:52476.2] || -> xuntil6(s30)*. % 76.04/76.24 52478[70:MRR:146.0,52477.0] || -> until5(s31)*. % 76.04/76.24 52479[70:MRR:50973.0,52478.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.24 52483[71:Spt:52479.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.24 52485[71:Res:52483.0,61.1] always3(s32) || -> . % 76.04/76.24 52486[71:SSi:52485.0,721.0] || -> . % 76.04/76.24 52487[71:Spt:52486.0,52479.1,52483.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.04/76.24 52488[71:Spt:52486.0,52479.0,52479.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.04/76.24 52490[71:MRR:825.2,52487.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.04/76.24 52491[71:Res:53.1,52488.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.04/76.24 52493[72:Spt:52491.1] || -> xuntil6(s31)*. % 76.04/76.24 52494[72:MRR:145.0,52493.0] || -> until5(s32)*. % 76.04/76.24 52495[72:MRR:49183.0,52494.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.24 52500[73:Spt:52495.2] || -> xuntil6(s32)*. % 76.04/76.24 52501[73:MRR:144.0,52500.0] || -> until5(s33)*. % 76.04/76.24 52502[73:MRR:50980.0,52501.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.24 52503[74:Spt:52502.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.24 52505[74:Res:52503.0,61.1] always3(s34) || -> . % 76.04/76.24 52506[74:SSi:52505.0,723.0] || -> . % 76.04/76.24 52507[74:Spt:52506.0,52502.1,52503.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.24 52508[74:Spt:52506.0,52502.0,52502.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.24 52510[74:MRR:819.2,52507.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.24 52511[74:Res:53.1,52508.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.24 52513[75:Spt:52511.1] || -> xuntil6(s33)*. % 76.04/76.24 52514[75:MRR:143.0,52513.0] || -> until5(s34)*. % 76.04/76.24 52515[75:MRR:49187.0,52514.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.24 52523[76:Spt:52515.2] || -> xuntil6(s34)*. % 76.04/76.24 52524[76:MRR:142.0,52523.0] || -> until5(s35)*. % 76.04/76.24 52525[76:MRR:50981.0,52524.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.24 52526[77:Spt:52525.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.24 52528[77:Res:52526.0,61.1] always3(s36) || -> . % 76.04/76.24 52529[77:SSi:52528.0,725.0] || -> . % 76.04/76.24 52530[77:Spt:52529.0,52525.1,52526.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.24 52531[77:Spt:52529.0,52525.0,52525.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.24 52533[77:MRR:813.2,52530.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.24 52534[77:Res:53.1,52531.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.24 52539[78:Spt:52534.1] || -> xuntil6(s35)*. % 76.04/76.24 52540[78:MRR:141.0,52539.0] || -> until5(s36)*. % 76.04/76.24 52541[78:MRR:49194.0,52540.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.24 52543[79:Spt:52541.2] || -> xuntil6(s36)*. % 76.04/76.24 52544[79:MRR:140.0,52543.0] || -> until5(s37)*. % 76.04/76.24 52545[79:MRR:50985.0,52544.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.24 52546[80:Spt:52545.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.24 52548[80:Res:52546.0,61.1] always3(s38) || -> . % 76.04/76.24 52549[80:SSi:52548.0,727.0] || -> . % 76.04/76.24 52550[80:Spt:52549.0,52545.1,52546.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.24 52551[80:Spt:52549.0,52545.0,52545.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.24 52553[80:MRR:807.2,52550.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.24 52554[80:Res:53.1,52551.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.24 52556[81:Spt:52554.1] || -> xuntil6(s37)*. % 76.04/76.24 52557[81:MRR:139.0,52556.0] || -> until5(s38)*. % 76.04/76.24 52558[81:MRR:49195.0,52557.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.24 52563[82:Spt:52558.2] || -> xuntil6(s38)*. % 76.04/76.24 52564[82:MRR:138.0,52563.0] || -> until5(s39)*. % 76.04/76.24 52565[82:MRR:50989.0,52564.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.24 52566[83:Spt:52565.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.24 52568[83:Res:52566.0,61.1] always3(s40) || -> . % 76.04/76.24 52569[83:SSi:52568.0,729.0] || -> . % 76.04/76.24 52570[83:Spt:52569.0,52565.1,52566.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.24 52571[83:Spt:52569.0,52565.0,52565.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.24 52573[83:MRR:801.2,52570.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.24 52574[83:Res:53.1,52571.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.24 52576[84:Spt:52574.1] || -> xuntil6(s39)*. % 76.04/76.24 52577[84:MRR:137.0,52576.0] || -> until5(s40)*. % 76.04/76.24 52578[84:MRR:49199.0,52577.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.24 52586[85:Spt:52578.2] || -> xuntil6(s40)*. % 76.04/76.24 52587[85:MRR:136.0,52586.0] || -> until5(s41)*. % 76.04/76.24 52588[85:MRR:50993.0,52587.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.24 52589[86:Spt:52588.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.24 52591[86:Res:52589.0,61.1] always3(s42) || -> . % 76.04/76.24 52592[86:SSi:52591.0,731.0] || -> . % 76.04/76.24 52593[86:Spt:52592.0,52588.1,52589.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.24 52594[86:Spt:52592.0,52588.0,52588.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.24 52596[86:MRR:795.2,52593.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.24 52597[86:Res:53.1,52594.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.24 52602[87:Spt:52597.1] || -> xuntil6(s41)*. % 76.04/76.24 52603[87:MRR:135.0,52602.0] || -> until5(s42)*. % 76.04/76.24 52604[87:MRR:49203.0,52603.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.24 52606[88:Spt:52604.2] || -> xuntil6(s42)*. % 76.04/76.24 52607[88:MRR:134.0,52606.0] || -> until5(s43)*. % 76.04/76.24 52608[88:MRR:51000.0,52607.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.24 52609[89:Spt:52608.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.24 52611[89:Res:52609.0,61.1] always3(s44) || -> . % 76.04/76.24 52612[89:SSi:52611.0,733.0] || -> . % 76.04/76.24 52613[89:Spt:52612.0,52608.1,52609.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.24 52614[89:Spt:52612.0,52608.0,52608.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.24 52616[89:MRR:789.2,52613.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.24 52617[89:Res:53.1,52614.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.24 52619[90:Spt:52617.1] || -> xuntil6(s43)*. % 76.04/76.24 52620[90:MRR:133.0,52619.0] || -> until5(s44)*. % 76.04/76.24 52621[90:MRR:49207.0,52620.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.24 52626[91:Spt:52621.2] || -> xuntil6(s44)*. % 76.04/76.24 52627[91:MRR:132.0,52626.0] || -> until5(s45)*. % 76.04/76.24 52628[91:MRR:51001.0,52627.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.24 52629[92:Spt:52628.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.24 52631[92:Res:52629.0,61.1] always3(s46) || -> . % 76.04/76.24 52632[92:SSi:52631.0,735.0] || -> . % 76.04/76.24 52633[92:Spt:52632.0,52628.1,52629.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.24 52634[92:Spt:52632.0,52628.0,52628.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.24 52636[92:MRR:783.2,52633.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.24 52637[92:Res:53.1,52634.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.24 52639[93:Spt:52637.1] || -> xuntil6(s45)*. % 76.04/76.24 52640[93:MRR:131.0,52639.0] || -> until5(s46)*. % 76.04/76.24 52641[93:MRR:49214.0,52640.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.24 52649[94:Spt:52641.2] || -> xuntil6(s46)*. % 76.04/76.24 52650[94:MRR:130.0,52649.0] || -> until5(s47)*. % 76.04/76.24 52651[94:MRR:51005.0,52650.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.24 52652[95:Spt:52651.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.24 52654[95:Res:52652.0,61.1] always3(s48) || -> . % 76.04/76.24 52655[95:SSi:52654.0,737.0] || -> . % 76.04/76.24 52656[95:Spt:52655.0,52651.1,52652.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.24 52657[95:Spt:52655.0,52651.0,52651.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.24 52659[95:MRR:777.2,52656.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.24 52660[95:Res:53.1,52657.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.24 52665[96:Spt:52660.1] || -> xuntil6(s47)*. % 76.04/76.24 52666[96:MRR:129.0,52665.0] || -> until5(s48)*. % 76.04/76.24 52667[96:MRR:49215.0,52666.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.24 52669[97:Spt:52667.2] || -> xuntil6(s48)*. % 76.04/76.24 52670[97:MRR:128.0,52669.0] || -> until5(s49)*. % 76.04/76.24 52671[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.24 52672[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.24 52673[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.24 52674[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.24 52678[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.24 52682[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.24 52689[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.24 52690[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.24 52694[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.24 52701[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.24 52702[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.24 52709[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.24 52713[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.24 52714[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.24 52718[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.24 52725[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.24 52729[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.24 52730[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.24 52740[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.24 52741[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.24 52745[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.24 52749[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.24 52753[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.24 52760[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.24 52761[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.24 52765[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.24 52769[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.24 52773[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.24 52780[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.24 52781[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.24 52783[39:SoR:52344.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)*. % 76.04/76.24 52791[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.24 52792[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.24 52796[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.24 52800[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.24 52804[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.24 52811[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.24 52812[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.24 52816[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.24 52820[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.24 52821[39:SoR:52783.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)* xuntil6(s49). % 76.04/76.24 52822[97:SSi:52821.0,50.0,738.0,52670.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s12,c_busy)* xuntil6(s49). % 76.04/76.24 52823[98:Spt:52822.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.24 52825[98:Res:52823.0,61.1] always3(s12) || -> . % 76.04/76.24 52826[98:SSi:52825.0,701.0,52394.0,52396.0] || -> . % 76.04/76.24 52827[98:Spt:52826.0,52822.1,52823.0] || m_main_v_state(s12,c_busy)*+ -> . % 76.04/76.24 52828[98:Spt:52826.0,52822.0,52822.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.24 52832[98:MRR:52783.2,52827.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.24 52833[98:Res:53.1,52828.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.24 52838[99:Spt:52833.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.24 52840[99:Res:52838.0,61.1] always3(s49) || -> . % 76.04/76.24 52841[99:SSi:52840.0,50.0,738.0,52670.0] || -> . % 76.04/76.24 52842[99:Spt:52841.0,52833.0,52838.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.24 52843[99:Spt:52841.0,52833.1] || -> xuntil6(s49)*. % 76.04/76.24 52844[99:MRR:52343.0,52843.0] || -> until2p7(s12)*. % 76.04/76.24 52845[99:MRR:208.0,52844.0] || -> until2p7(s13)* node4(s12). % 76.04/76.24 52847[99:MRR:774.2,52842.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.24 52848[100:Spt:52845.0] || -> until2p7(s13)*. % 76.04/76.24 52849[100:MRR:209.0,52848.0] || -> until2p7(s14)* node4(s13). % 76.04/76.24 52850[101:Spt:52849.0] || -> until2p7(s14)*. % 76.04/76.24 52851[101:MRR:210.0,52850.0] || -> until2p7(s15)* node4(s14). % 76.04/76.24 52852[102:Spt:52851.0] || -> until2p7(s15)*. % 76.04/76.24 52853[102:MRR:211.0,52852.0] || -> until2p7(s16)* node4(s15). % 76.04/76.24 52854[103:Spt:52853.0] || -> until2p7(s16)*. % 76.04/76.24 52855[103:MRR:212.0,52854.0] || -> until2p7(s17)* node4(s16). % 76.04/76.24 52856[104:Spt:52855.0] || -> until2p7(s17)*. % 76.04/76.24 52857[104:MRR:213.0,52856.0] || -> until2p7(s18)* node4(s17). % 76.04/76.24 52858[105:Spt:52857.0] || -> until2p7(s18)*. % 76.04/76.24 52859[105:MRR:214.0,52858.0] || -> until2p7(s19)* node4(s18). % 76.04/76.24 52860[106:Spt:52859.0] || -> until2p7(s19)*. % 76.04/76.24 52861[106:MRR:215.0,52860.0] || -> until2p7(s20)* node4(s19). % 76.04/76.24 52862[107:Spt:52861.0] || -> until2p7(s20)*. % 76.04/76.24 52863[107:MRR:216.0,52862.0] || -> until2p7(s21)* node4(s20). % 76.04/76.24 52864[108:Spt:52863.0] || -> until2p7(s21)*. % 76.04/76.24 52865[108:MRR:217.0,52864.0] || -> until2p7(s22)* node4(s21). % 76.04/76.24 52866[109:Spt:52865.0] || -> until2p7(s22)*. % 76.04/76.24 52867[109:MRR:218.0,52866.0] || -> until2p7(s23)* node4(s22). % 76.04/76.24 52868[110:Spt:52867.0] || -> until2p7(s23)*. % 76.04/76.24 52869[110:MRR:219.0,52868.0] || -> until2p7(s24)* node4(s23). % 76.04/76.24 52870[111:Spt:52869.0] || -> until2p7(s24)*. % 76.04/76.24 52871[111:MRR:220.0,52870.0] || -> until2p7(s25)* node4(s24). % 76.04/76.24 52872[112:Spt:52871.0] || -> until2p7(s25)*. % 76.04/76.24 52873[112:MRR:221.0,52872.0] || -> until2p7(s26)* node4(s25). % 76.04/76.24 52874[113:Spt:52873.0] || -> until2p7(s26)*. % 76.04/76.24 52875[113:MRR:222.0,52874.0] || -> until2p7(s27)* node4(s26). % 76.04/76.24 52876[114:Spt:52875.0] || -> until2p7(s27)*. % 76.04/76.24 52877[114:MRR:223.0,52876.0] || -> until2p7(s28)* node4(s27). % 76.04/76.24 52878[115:Spt:52877.0] || -> until2p7(s28)*. % 76.04/76.24 52879[115:MRR:224.0,52878.0] || -> until2p7(s29)* node4(s28). % 76.04/76.24 52880[116:Spt:52879.0] || -> until2p7(s29)*. % 76.04/76.24 52881[116:MRR:225.0,52880.0] || -> until2p7(s30)* node4(s29). % 76.04/76.24 52882[117:Spt:52881.0] || -> until2p7(s30)*. % 76.04/76.24 52883[117:MRR:226.0,52882.0] || -> until2p7(s31)* node4(s30). % 76.04/76.24 52884[118:Spt:52883.0] || -> until2p7(s31)*. % 76.04/76.24 52885[118:MRR:227.0,52884.0] || -> until2p7(s32)* node4(s31). % 76.04/76.24 52886[119:Spt:52885.0] || -> until2p7(s32)*. % 76.04/76.24 52887[119:MRR:228.0,52886.0] || -> until2p7(s33)* node4(s32). % 76.04/76.24 52888[120:Spt:52887.0] || -> until2p7(s33)*. % 76.04/76.24 52889[120:MRR:229.0,52888.0] || -> until2p7(s34)* node4(s33). % 76.04/76.24 52890[121:Spt:52889.0] || -> until2p7(s34)*. % 76.04/76.24 52891[121:MRR:230.0,52890.0] || -> until2p7(s35)* node4(s34). % 76.04/76.24 52892[122:Spt:52891.0] || -> until2p7(s35)*. % 76.04/76.24 52893[122:MRR:231.0,52892.0] || -> until2p7(s36)* node4(s35). % 76.04/76.24 52894[123:Spt:52893.0] || -> until2p7(s36)*. % 76.04/76.24 52895[123:MRR:232.0,52894.0] || -> until2p7(s37)* node4(s36). % 76.04/76.24 52896[124:Spt:52895.0] || -> until2p7(s37)*. % 76.04/76.24 52897[124:MRR:235.0,52896.0] || -> until2p7(s38)* node4(s37). % 76.04/76.24 52898[125:Spt:52897.0] || -> until2p7(s38)*. % 76.04/76.24 52899[125:MRR:236.0,52898.0] || -> until2p7(s39)* node4(s38). % 76.04/76.24 52900[126:Spt:52899.0] || -> until2p7(s39)*. % 76.04/76.24 52901[126:MRR:237.0,52900.0] || -> until2p7(s40)* node4(s39). % 76.04/76.24 52902[127:Spt:52901.0] || -> until2p7(s40)*. % 76.04/76.24 52903[127:MRR:238.0,52902.0] || -> until2p7(s41)* node4(s40). % 76.04/76.24 52904[128:Spt:52903.0] || -> until2p7(s41)*. % 76.04/76.24 52905[128:MRR:239.0,52904.0] || -> until2p7(s42)* node4(s41). % 76.04/76.24 52906[129:Spt:52905.0] || -> until2p7(s42)*. % 76.04/76.24 52907[129:MRR:240.0,52906.0] || -> until2p7(s43)* node4(s42). % 76.04/76.24 52908[130:Spt:52907.0] || -> until2p7(s43)*. % 76.04/76.24 52909[130:MRR:241.0,52908.0] || -> until2p7(s44)* node4(s43). % 76.04/76.24 52910[131:Spt:52909.0] || -> until2p7(s44)*. % 76.04/76.24 52911[131:MRR:539.0,52910.0] || -> until2p7(s45)* node4(s44). % 76.04/76.24 52912[132:Spt:52911.0] || -> until2p7(s45)*. % 76.04/76.24 52913[132:MRR:544.0,52912.0] || -> until2p7(s46)* node4(s45). % 76.04/76.24 52914[133:Spt:52913.0] || -> until2p7(s46)*. % 76.04/76.24 52915[133:MRR:549.0,52914.0] || -> until2p7(s47)* node4(s46). % 76.04/76.24 52916[134:Spt:52915.0] || -> until2p7(s47)*. % 76.04/76.24 52917[134:MRR:554.0,52916.0] || -> until2p7(s48)* node4(s47). % 76.04/76.24 52918[135:Spt:52917.0] || -> until2p7(s48)*. % 76.04/76.24 52919[135:MRR:559.0,52918.0] || -> until2p7(s49)* node4(s48). % 76.04/76.24 52920[136:Spt:52919.0] || -> until2p7(s49)*. % 76.04/76.24 52921[136:MRR:194.0,52920.0] || -> node4(s49)*. % 76.04/76.24 52922[136:MRR:52832.0,52921.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.24 52923[136:Res:53.1,52922.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.24 52925[136:MRR:52923.0,52842.0] || -> . % 76.04/76.24 52926[136:Spt:52925.0,52919.0,52920.0] || until2p7(s49)*+ -> . % 76.04/76.24 52927[136:Spt:52925.0,52919.1] || -> node4(s48)*. % 76.04/76.24 52928[136:MRR:52847.0,52927.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.24 52931[136:Res:53.1,52928.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.24 52933[136:MRR:52931.0,52656.0] || -> . % 76.04/76.24 52934[135:Spt:52933.0,52917.0,52918.0] || until2p7(s48)*+ -> . % 76.04/76.24 52935[135:Spt:52933.0,52917.1] || -> node4(s47)*. % 76.04/76.24 52936[135:MRR:52659.0,52935.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.24 52939[135:Res:53.1,52936.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.24 52943[135:Res:52939.0,61.1] always3(s47) || -> . % 76.04/76.24 52944[135:SSi:52943.0,736.0,52650.0,52665.0,52916.0,52935.0] || -> . % 76.04/76.24 52945[134:Spt:52944.0,52915.0,52916.0] || until2p7(s47)*+ -> . % 76.04/76.24 52946[134:Spt:52944.0,52915.1] || -> node4(s46)*. % 76.04/76.24 52948[134:MRR:780.0,52946.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.24 52964[134:Res:53.1,52948.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.24 52966[134:MRR:52964.0,52633.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.24 52971[134:Res:52966.0,61.1] always3(s47) || -> . % 76.04/76.24 52972[134:SSi:52971.0,736.0,52650.0,52665.0] || -> . % 76.04/76.24 52973[133:Spt:52972.0,52913.0,52914.0] || until2p7(s46)*+ -> . % 76.04/76.24 52974[133:Spt:52972.0,52913.1] || -> node4(s45)*. % 76.04/76.24 52975[133:MRR:52636.0,52974.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.24 52978[133:Res:53.1,52975.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.24 52982[133:Res:52978.0,61.1] always3(s45) || -> . % 76.04/76.24 52983[133:SSi:52982.0,734.0,52627.0,52639.0,52912.0,52974.0] || -> . % 76.04/76.24 52984[132:Spt:52983.0,52911.0,52912.0] || until2p7(s45)*+ -> . % 76.04/76.24 52985[132:Spt:52983.0,52911.1] || -> node4(s44)*. % 76.04/76.24 52987[132:MRR:786.0,52985.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.24 52998[132:Res:53.1,52987.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.24 53000[132:MRR:52998.0,52613.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.24 53002[132:Res:53000.0,61.1] always3(s45) || -> . % 76.04/76.24 53003[132:SSi:53002.0,734.0,52627.0,52639.0] || -> . % 76.04/76.24 53004[131:Spt:53003.0,52909.0,52910.0] || until2p7(s44)*+ -> . % 76.04/76.24 53005[131:Spt:53003.0,52909.1] || -> node4(s43)*. % 76.04/76.24 53006[131:MRR:52616.0,53005.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.24 53010[131:Res:53.1,53006.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.24 53013[131:Res:53010.0,61.1] always3(s43) || -> . % 76.04/76.24 53014[131:SSi:53013.0,732.0,52607.0,52619.0,52908.0,53005.0] || -> . % 76.04/76.24 53015[130:Spt:53014.0,52907.0,52908.0] || until2p7(s43)*+ -> . % 76.04/76.24 53016[130:Spt:53014.0,52907.1] || -> node4(s42)*. % 76.04/76.24 53018[130:MRR:792.0,53016.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.24 53029[130:Res:53.1,53018.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.24 53031[130:MRR:53029.0,52593.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.24 53033[130:Res:53031.0,61.1] always3(s43) || -> . % 76.04/76.24 53034[130:SSi:53033.0,732.0,52607.0,52619.0] || -> . % 76.04/76.24 53035[129:Spt:53034.0,52905.0,52906.0] || until2p7(s42)*+ -> . % 76.04/76.24 53036[129:Spt:53034.0,52905.1] || -> node4(s41)*. % 76.04/76.24 53037[129:MRR:52596.0,53036.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.24 53040[129:Res:53.1,53037.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.24 53043[129:Res:53040.0,61.1] always3(s41) || -> . % 76.04/76.24 53044[129:SSi:53043.0,730.0,52587.0,52602.0,52904.0,53036.0] || -> . % 76.04/76.24 53045[128:Spt:53044.0,52903.0,52904.0] || until2p7(s41)*+ -> . % 76.04/76.24 53046[128:Spt:53044.0,52903.1] || -> node4(s40)*. % 76.04/76.24 53048[128:MRR:798.0,53046.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.24 53060[128:Res:53.1,53048.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.24 53062[128:MRR:53060.0,52570.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.24 53064[128:Res:53062.0,61.1] always3(s41) || -> . % 76.04/76.24 53065[128:SSi:53064.0,730.0,52587.0,52602.0] || -> . % 76.04/76.24 53066[127:Spt:53065.0,52901.0,52902.0] || until2p7(s40)*+ -> . % 76.04/76.24 53067[127:Spt:53065.0,52901.1] || -> node4(s39)*. % 76.04/76.24 53068[127:MRR:52573.0,53067.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.24 53071[127:Res:53.1,53068.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.24 53074[127:Res:53071.0,61.1] always3(s39) || -> . % 76.04/76.24 53075[127:SSi:53074.0,728.0,52564.0,52576.0,52900.0,53067.0] || -> . % 76.04/76.24 53076[126:Spt:53075.0,52899.0,52900.0] || until2p7(s39)*+ -> . % 76.04/76.24 53077[126:Spt:53075.0,52899.1] || -> node4(s38)*. % 76.04/76.24 53079[126:MRR:804.0,53077.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.24 53091[126:Res:53.1,53079.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.24 53093[126:MRR:53091.0,52550.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.24 53098[126:Res:53093.0,61.1] always3(s39) || -> . % 76.04/76.24 53099[126:SSi:53098.0,728.0,52564.0,52576.0] || -> . % 76.04/76.24 53100[125:Spt:53099.0,52897.0,52898.0] || until2p7(s38)*+ -> . % 76.04/76.24 53101[125:Spt:53099.0,52897.1] || -> node4(s37)*. % 76.04/76.24 53102[125:MRR:52553.0,53101.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.24 53105[125:Res:53.1,53102.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.24 53109[125:Res:53105.0,61.1] always3(s37) || -> . % 76.04/76.24 53110[125:SSi:53109.0,726.0,52544.0,52556.0,52896.0,53101.0] || -> . % 76.04/76.24 53111[124:Spt:53110.0,52895.0,52896.0] || until2p7(s37)*+ -> . % 76.04/76.24 53112[124:Spt:53110.0,52895.1] || -> node4(s36)*. % 76.04/76.24 53114[124:MRR:810.0,53112.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.24 53125[124:Res:53.1,53114.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.24 53127[124:MRR:53125.0,52530.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.24 53129[124:Res:53127.0,61.1] always3(s37) || -> . % 76.04/76.24 53130[124:SSi:53129.0,726.0,52544.0,52556.0] || -> . % 76.04/76.24 53131[123:Spt:53130.0,52893.0,52894.0] || until2p7(s36)*+ -> . % 76.04/76.24 53132[123:Spt:53130.0,52893.1] || -> node4(s35)*. % 76.04/76.24 53133[123:MRR:52533.0,53132.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.24 53137[123:Res:53.1,53133.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.24 53140[123:Res:53137.0,61.1] always3(s35) || -> . % 76.04/76.24 53141[123:SSi:53140.0,724.0,52524.0,52539.0,52892.0,53132.0] || -> . % 76.04/76.24 53142[122:Spt:53141.0,52891.0,52892.0] || until2p7(s35)*+ -> . % 76.04/76.24 53143[122:Spt:53141.0,52891.1] || -> node4(s34)*. % 76.04/76.24 53145[122:MRR:816.0,53143.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.24 53156[122:Res:53.1,53145.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.24 53158[122:MRR:53156.0,52507.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.24 53160[122:Res:53158.0,61.1] always3(s35) || -> . % 76.04/76.24 53161[122:SSi:53160.0,724.0,52524.0,52539.0] || -> . % 76.04/76.24 53162[121:Spt:53161.0,52889.0,52890.0] || until2p7(s34)*+ -> . % 76.04/76.24 53163[121:Spt:53161.0,52889.1] || -> node4(s33)*. % 76.04/76.24 53164[121:MRR:52510.0,53163.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.24 53167[121:Res:53.1,53164.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.24 53170[121:Res:53167.0,61.1] always3(s33) || -> . % 76.04/76.24 53171[121:SSi:53170.0,722.0,52501.0,52513.0,52888.0,53163.0] || -> . % 76.04/76.24 53172[120:Spt:53171.0,52887.0,52888.0] || until2p7(s33)*+ -> . % 76.04/76.24 53173[120:Spt:53171.0,52887.1] || -> node4(s32)*. % 76.04/76.24 53175[120:MRR:822.0,53173.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.24 53187[120:Res:53.1,53175.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.24 53189[120:MRR:53187.0,52487.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.24 53191[120:Res:53189.0,61.1] always3(s33) || -> . % 76.04/76.24 53192[120:SSi:53191.0,722.0,52501.0,52513.0] || -> . % 76.04/76.24 53193[119:Spt:53192.0,52885.0,52886.0] || until2p7(s32)*+ -> . % 76.04/76.24 53194[119:Spt:53192.0,52885.1] || -> node4(s31)*. % 76.04/76.24 53195[119:MRR:52490.0,53194.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.04/76.24 53198[119:Res:53.1,53195.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.24 53201[119:Res:53198.0,61.1] always3(s31) || -> . % 76.04/76.24 53202[119:SSi:53201.0,720.0,52478.0,52493.0,52884.0,53194.0] || -> . % 76.04/76.24 53203[118:Spt:53202.0,52883.0,52884.0] || until2p7(s31)*+ -> . % 76.04/76.24 53204[118:Spt:53202.0,52883.1] || -> node4(s30)*. % 76.04/76.24 53206[118:MRR:828.0,53204.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.24 53218[118:Res:53.1,53206.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.24 53223[119:Spt:53218.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.24 53225[119:Res:53223.0,61.1] always3(s30) || -> . % 76.04/76.24 53226[119:SSi:53225.0,719.0,52475.0,52477.0,52882.0,53204.0] || -> . % 76.04/76.24 53227[119:Spt:53226.0,53218.0,53223.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.24 53228[119:Spt:53226.0,53218.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.24 53232[119:Res:53228.0,61.1] always3(s31) || -> . % 76.04/76.24 53233[119:SSi:53232.0,720.0,52478.0,52493.0] || -> . % 76.04/76.24 53234[117:Spt:53233.0,52881.0,52882.0] || until2p7(s30)*+ -> . % 76.04/76.24 53235[117:Spt:53233.0,52881.1] || -> node4(s29)*. % 76.04/76.24 53237[117:MRR:831.0,53235.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.24 53244[117:Res:53.1,53237.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.24 53246[118:Spt:53244.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.24 53248[118:Res:53246.0,61.1] always3(s29) || -> . % 76.04/76.24 53249[118:SSi:53248.0,718.0,52469.0,52474.0,52880.0,53235.0] || -> . % 76.04/76.24 53250[118:Spt:53249.0,53244.0,53246.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.24 53251[118:Spt:53249.0,53244.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.24 53255[118:Res:53251.0,61.1] always3(s30) || -> . % 76.04/76.24 53256[118:SSi:53255.0,719.0,52475.0,52477.0] || -> . % 76.04/76.24 53257[116:Spt:53256.0,52879.0,52880.0] || until2p7(s29)*+ -> . % 76.04/76.24 53258[116:Spt:53256.0,52879.1] || -> node4(s28)*. % 76.04/76.24 53260[116:MRR:834.0,53258.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.24 53263[116:Res:53.1,53260.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.24 53268[117:Spt:53263.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.24 53270[117:Res:53268.0,61.1] always3(s28) || -> . % 76.04/76.24 53271[117:SSi:53270.0,717.0,52466.0,52468.0,52878.0,53258.0] || -> . % 76.04/76.24 53272[117:Spt:53271.0,53263.0,53268.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.24 53273[117:Spt:53271.0,53263.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.24 53277[117:Res:53273.0,61.1] always3(s29) || -> . % 76.04/76.24 53278[117:SSi:53277.0,718.0,52469.0,52474.0] || -> . % 76.04/76.24 53279[115:Spt:53278.0,52877.0,52878.0] || until2p7(s28)*+ -> . % 76.04/76.24 53280[115:Spt:53278.0,52877.1] || -> node4(s27)*. % 76.04/76.24 53282[115:MRR:837.0,53280.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.24 53285[115:Res:53.1,53282.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.24 53287[116:Spt:53285.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.24 53289[116:Res:53287.0,61.1] always3(s27) || -> . % 76.04/76.24 53290[116:SSi:53289.0,716.0,52460.0,52465.0,52876.0,53280.0] || -> . % 76.04/76.24 53291[116:Spt:53290.0,53285.0,53287.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.24 53292[116:Spt:53290.0,53285.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.24 53296[116:Res:53292.0,61.1] always3(s28) || -> . % 76.04/76.24 53297[116:SSi:53296.0,717.0,52466.0,52468.0] || -> . % 76.04/76.24 53298[114:Spt:53297.0,52875.0,52876.0] || until2p7(s27)*+ -> . % 76.04/76.24 53299[114:Spt:53297.0,52875.1] || -> node4(s26)*. % 76.04/76.24 53301[114:MRR:840.0,53299.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.24 53304[114:Res:53.1,53301.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.24 53306[115:Spt:53304.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.24 53308[115:Res:53306.0,61.1] always3(s26) || -> . % 76.04/76.24 53309[115:SSi:53308.0,715.0,52457.0,52459.0,52874.0,53299.0] || -> . % 76.04/76.24 53310[115:Spt:53309.0,53304.0,53306.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.24 53311[115:Spt:53309.0,53304.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.24 53315[115:Res:53311.0,61.1] always3(s27) || -> . % 76.04/76.24 53316[115:SSi:53315.0,716.0,52460.0,52465.0] || -> . % 76.04/76.24 53317[113:Spt:53316.0,52873.0,52874.0] || until2p7(s26)*+ -> . % 76.04/76.24 53318[113:Spt:53316.0,52873.1] || -> node4(s25)*. % 76.04/76.24 53320[113:MRR:843.0,53318.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.24 53323[113:Res:53.1,53320.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.24 53325[114:Spt:53323.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.24 53327[114:Res:53325.0,61.1] always3(s25) || -> . % 76.04/76.24 53328[114:SSi:53327.0,714.0,52451.0,52456.0,52872.0,53318.0] || -> . % 76.04/76.24 53329[114:Spt:53328.0,53323.0,53325.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.24 53330[114:Spt:53328.0,53323.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.24 53334[114:Res:53330.0,61.1] always3(s26) || -> . % 76.04/76.24 53335[114:SSi:53334.0,715.0,52457.0,52459.0] || -> . % 76.04/76.24 53336[112:Spt:53335.0,52871.0,52872.0] || until2p7(s25)*+ -> . % 76.04/76.24 53337[112:Spt:53335.0,52871.1] || -> node4(s24)*. % 76.04/76.24 53339[112:MRR:846.0,53337.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.24 53342[112:Res:53.1,53339.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.24 53347[113:Spt:53342.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.24 53349[113:Res:53347.0,61.1] always3(s24) || -> . % 76.04/76.24 53350[113:SSi:53349.0,713.0,52448.0,52450.0,52870.0,53337.0] || -> . % 76.04/76.24 53351[113:Spt:53350.0,53342.0,53347.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.24 53352[113:Spt:53350.0,53342.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.24 53356[113:Res:53352.0,61.1] always3(s25) || -> . % 76.04/76.24 53357[113:SSi:53356.0,714.0,52451.0,52456.0] || -> . % 76.04/76.24 53358[111:Spt:53357.0,52869.0,52870.0] || until2p7(s24)*+ -> . % 76.04/76.24 53359[111:Spt:53357.0,52869.1] || -> node4(s23)*. % 76.04/76.24 53361[111:MRR:849.0,53359.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.24 53364[111:Res:53.1,53361.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.24 53366[112:Spt:53364.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.24 53368[112:Res:53366.0,61.1] always3(s23) || -> . % 76.04/76.24 53369[112:SSi:53368.0,712.0,52442.0,52447.0,52868.0,53359.0] || -> . % 76.04/76.24 53370[112:Spt:53369.0,53364.0,53366.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.24 53371[112:Spt:53369.0,53364.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.24 53375[112:Res:53371.0,61.1] always3(s24) || -> . % 76.04/76.24 53376[112:SSi:53375.0,713.0,52448.0,52450.0] || -> . % 76.04/76.24 53377[110:Spt:53376.0,52867.0,52868.0] || until2p7(s23)*+ -> . % 76.04/76.24 53378[110:Spt:53376.0,52867.1] || -> node4(s22)*. % 76.04/76.24 53380[110:MRR:852.0,53378.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.24 53383[110:Res:53.1,53380.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.24 53385[111:Spt:53383.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.24 53387[111:Res:53385.0,61.1] always3(s22) || -> . % 76.04/76.24 53388[111:SSi:53387.0,711.0,52439.0,52441.0,52866.0,53378.0] || -> . % 76.04/76.24 53389[111:Spt:53388.0,53383.0,53385.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.24 53390[111:Spt:53388.0,53383.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.24 53394[111:Res:53390.0,61.1] always3(s23) || -> . % 76.04/76.24 53395[111:SSi:53394.0,712.0,52442.0,52447.0] || -> . % 76.04/76.24 53396[109:Spt:53395.0,52865.0,52866.0] || until2p7(s22)*+ -> . % 76.04/76.24 53397[109:Spt:53395.0,52865.1] || -> node4(s21)*. % 76.04/76.24 53399[109:MRR:855.0,53397.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.24 53402[109:Res:53.1,53399.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.24 53404[110:Spt:53402.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.24 53406[110:Res:53404.0,61.1] always3(s21) || -> . % 76.04/76.24 53407[110:SSi:53406.0,710.0,52433.0,52438.0,52864.0,53397.0] || -> . % 76.04/76.24 53408[110:Spt:53407.0,53402.0,53404.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.24 53409[110:Spt:53407.0,53402.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.24 53413[110:Res:53409.0,61.1] always3(s22) || -> . % 76.04/76.24 53414[110:SSi:53413.0,711.0,52439.0,52441.0] || -> . % 76.04/76.24 53415[108:Spt:53414.0,52863.0,52864.0] || until2p7(s21)*+ -> . % 76.04/76.24 53416[108:Spt:53414.0,52863.1] || -> node4(s20)*. % 76.04/76.24 53418[108:MRR:858.0,53416.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.24 53421[108:Res:53.1,53418.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.24 53426[109:Spt:53421.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.24 53428[109:Res:53426.0,61.1] always3(s20) || -> . % 76.04/76.24 53429[109:SSi:53428.0,709.0,52430.0,52432.0,52862.0,53416.0] || -> . % 76.04/76.24 53430[109:Spt:53429.0,53421.0,53426.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.24 53431[109:Spt:53429.0,53421.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.24 53435[109:Res:53431.0,61.1] always3(s21) || -> . % 76.04/76.24 53436[109:SSi:53435.0,710.0,52433.0,52438.0] || -> . % 76.04/76.24 53437[107:Spt:53436.0,52861.0,52862.0] || until2p7(s20)*+ -> . % 76.04/76.24 53438[107:Spt:53436.0,52861.1] || -> node4(s19)*. % 76.04/76.24 53440[107:MRR:861.0,53438.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.24 53443[107:Res:53.1,53440.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.24 53445[108:Spt:53443.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.24 53447[108:Res:53445.0,61.1] always3(s19) || -> . % 76.04/76.24 53448[108:SSi:53447.0,708.0,52424.0,52429.0,52860.0,53438.0] || -> . % 76.04/76.24 53449[108:Spt:53448.0,53443.0,53445.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.24 53450[108:Spt:53448.0,53443.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.24 53454[108:Res:53450.0,61.1] always3(s20) || -> . % 76.04/76.24 53455[108:SSi:53454.0,709.0,52430.0,52432.0] || -> . % 76.04/76.24 53456[106:Spt:53455.0,52859.0,52860.0] || until2p7(s19)*+ -> . % 76.04/76.24 53457[106:Spt:53455.0,52859.1] || -> node4(s18)*. % 76.04/76.24 53459[106:MRR:864.0,53457.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.24 53462[106:Res:53.1,53459.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.24 53464[107:Spt:53462.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.24 53466[107:Res:53464.0,61.1] always3(s18) || -> . % 76.04/76.24 53467[107:SSi:53466.0,707.0,52421.0,52423.0,52858.0,53457.0] || -> . % 76.04/76.24 53468[107:Spt:53467.0,53462.0,53464.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.24 53469[107:Spt:53467.0,53462.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.24 53473[107:Res:53469.0,61.1] always3(s19) || -> . % 76.04/76.24 53474[107:SSi:53473.0,708.0,52424.0,52429.0] || -> . % 76.04/76.24 53475[105:Spt:53474.0,52857.0,52858.0] || until2p7(s18)*+ -> . % 76.04/76.24 53476[105:Spt:53474.0,52857.1] || -> node4(s17)*. % 76.04/76.24 53478[105:MRR:867.0,53476.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.24 53481[105:Res:53.1,53478.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.24 53483[106:Spt:53481.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.24 53485[106:Res:53483.0,61.1] always3(s17) || -> . % 76.04/76.24 53486[106:SSi:53485.0,706.0,52415.0,52420.0,52856.0,53476.0] || -> . % 76.04/76.24 53487[106:Spt:53486.0,53481.0,53483.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.24 53488[106:Spt:53486.0,53481.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.24 53492[106:Res:53488.0,61.1] always3(s18) || -> . % 76.04/76.24 53493[106:SSi:53492.0,707.0,52421.0,52423.0] || -> . % 76.04/76.24 53494[104:Spt:53493.0,52855.0,52856.0] || until2p7(s17)*+ -> . % 76.04/76.24 53495[104:Spt:53493.0,52855.1] || -> node4(s16)*. % 76.04/76.24 53497[104:MRR:870.0,53495.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.24 53500[104:Res:53.1,53497.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.24 53505[105:Spt:53500.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.24 53507[105:Res:53505.0,61.1] always3(s16) || -> . % 76.04/76.24 53508[105:SSi:53507.0,705.0,52412.0,52414.0,52854.0,53495.0] || -> . % 76.04/76.24 53509[105:Spt:53508.0,53500.0,53505.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.24 53510[105:Spt:53508.0,53500.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.24 53514[105:Res:53510.0,61.1] always3(s17) || -> . % 76.04/76.24 53515[105:SSi:53514.0,706.0,52415.0,52420.0] || -> . % 76.04/76.24 53516[103:Spt:53515.0,52853.0,52854.0] || until2p7(s16)*+ -> . % 76.04/76.24 53517[103:Spt:53515.0,52853.1] || -> node4(s15)*. % 76.04/76.24 53519[103:MRR:873.0,53517.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.24 53522[103:Res:53.1,53519.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.24 53524[104:Spt:53522.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.24 53526[104:Res:53524.0,61.1] always3(s15) || -> . % 76.04/76.24 53527[104:SSi:53526.0,704.0,52406.0,52411.0,52852.0,53517.0] || -> . % 76.04/76.24 53528[104:Spt:53527.0,53522.0,53524.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.24 53529[104:Spt:53527.0,53522.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.24 53533[104:Res:53529.0,61.1] always3(s16) || -> . % 76.04/76.24 53534[104:SSi:53533.0,705.0,52412.0,52414.0] || -> . % 76.04/76.24 53535[102:Spt:53534.0,52851.0,52852.0] || until2p7(s15)*+ -> . % 76.04/76.24 53536[102:Spt:53534.0,52851.1] || -> node4(s14)*. % 76.04/76.24 53538[102:MRR:876.0,53536.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.24 53541[102:Res:53.1,53538.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.24 53543[103:Spt:53541.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.24 53545[103:Res:53543.0,61.1] always3(s14) || -> . % 76.04/76.24 53546[103:SSi:53545.0,703.0,52403.0,52405.0,52850.0,53536.0] || -> . % 76.04/76.24 53547[103:Spt:53546.0,53541.0,53543.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.24 53548[103:Spt:53546.0,53541.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.24 53552[103:Res:53548.0,61.1] always3(s15) || -> . % 76.04/76.24 53553[103:SSi:53552.0,704.0,52406.0,52411.0] || -> . % 76.04/76.24 53554[101:Spt:53553.0,52849.0,52850.0] || until2p7(s14)*+ -> . % 76.04/76.24 53555[101:Spt:53553.0,52849.1] || -> node4(s13)*. % 76.04/76.24 53557[101:MRR:879.0,53555.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.24 53560[101:Res:53.1,53557.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.24 53562[102:Spt:53560.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.24 53564[102:Res:53562.0,61.1] always3(s13) || -> . % 76.04/76.24 53565[102:SSi:53564.0,702.0,52397.0,52402.0,52848.0,53555.0] || -> . % 76.04/76.24 53566[102:Spt:53565.0,53560.0,53562.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.24 53567[102:Spt:53565.0,53560.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.24 53571[102:Res:53567.0,61.1] always3(s14) || -> . % 76.04/76.24 53572[102:SSi:53571.0,703.0,52403.0,52405.0] || -> . % 76.04/76.24 53573[100:Spt:53572.0,52845.0,52848.0] || until2p7(s13)*+ -> . % 76.04/76.24 53574[100:Spt:53572.0,52845.1] || -> node4(s12)*. % 76.04/76.24 53576[100:MRR:882.0,53574.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.24 53579[100:Res:53.1,53576.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.24 53581[100:MRR:53579.0,52827.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.24 53586[100:Res:53581.0,61.1] always3(s13) || -> . % 76.04/76.24 53587[100:SSi:53586.0,702.0,52397.0,52402.0] || -> . % 76.04/76.24 53588[97:Spt:53587.0,52667.2,52669.0] || xuntil6(s48)*+ -> . % 76.04/76.24 53589[97:Spt:53587.0,52667.0,52667.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.24 53590[97:Res:53.1,53589.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.24 53592[97:MRR:53590.0,52656.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.24 53594[97:Res:53592.0,61.1] always3(s49) || -> . % 76.04/76.24 53595[97:SSi:53594.0,50.0,738.0] || -> . % 76.04/76.24 53596[96:Spt:53595.0,52660.1,52665.0] || xuntil6(s47)* -> . % 76.04/76.24 53597[96:Spt:53595.0,52660.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.24 53600[96:Res:53597.0,61.1] always3(s47) || -> . % 76.04/76.24 53601[96:SSi:53600.0,736.0,52650.0] || -> . % 76.04/76.24 53602[94:Spt:53601.0,52641.2,52649.0] || xuntil6(s46)*+ -> . % 76.04/76.24 53603[94:Spt:53601.0,52641.0,52641.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.24 53604[94:Res:53.1,53603.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.24 53606[94:MRR:53604.0,52633.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.24 53609[94:Res:53606.0,61.1] always3(s47) || -> . % 76.04/76.24 53610[94:SSi:53609.0,736.0] || -> . % 76.04/76.24 53611[93:Spt:53610.0,52637.1,52639.0] || xuntil6(s45)* -> . % 76.04/76.24 53612[93:Spt:53610.0,52637.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.24 53615[93:Res:53612.0,61.1] always3(s45) || -> . % 76.04/76.24 53616[93:SSi:53615.0,734.0,52627.0] || -> . % 76.04/76.24 53617[91:Spt:53616.0,52621.2,52626.0] || xuntil6(s44)*+ -> . % 76.04/76.24 53618[91:Spt:53616.0,52621.0,52621.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.24 53619[91:Res:53.1,53618.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.24 53621[91:MRR:53619.0,52613.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.24 53623[91:Res:53621.0,61.1] always3(s45) || -> . % 76.04/76.24 53624[91:SSi:53623.0,734.0] || -> . % 76.04/76.24 53625[90:Spt:53624.0,52617.1,52619.0] || xuntil6(s43)* -> . % 76.04/76.24 53626[90:Spt:53624.0,52617.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.24 53629[90:Res:53626.0,61.1] always3(s43) || -> . % 76.04/76.24 53630[90:SSi:53629.0,732.0,52607.0] || -> . % 76.04/76.24 53631[88:Spt:53630.0,52604.2,52606.0] || xuntil6(s42)*+ -> . % 76.04/76.24 53632[88:Spt:53630.0,52604.0,52604.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.24 53633[88:Res:53.1,53632.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.24 53635[88:MRR:53633.0,52593.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.24 53638[88:Res:53635.0,61.1] always3(s43) || -> . % 76.04/76.24 53639[88:SSi:53638.0,732.0] || -> . % 76.04/76.24 53640[87:Spt:53639.0,52597.1,52602.0] || xuntil6(s41)* -> . % 76.04/76.24 53641[87:Spt:53639.0,52597.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.24 53644[87:Res:53641.0,61.1] always3(s41) || -> . % 76.04/76.24 53645[87:SSi:53644.0,730.0,52587.0] || -> . % 76.04/76.24 53646[85:Spt:53645.0,52578.2,52586.0] || xuntil6(s40)*+ -> . % 76.04/76.24 53647[85:Spt:53645.0,52578.0,52578.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.24 53648[85:Res:53.1,53647.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.24 53650[85:MRR:53648.0,52570.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.24 53652[85:Res:53650.0,61.1] always3(s41) || -> . % 76.04/76.24 53653[85:SSi:53652.0,730.0] || -> . % 76.04/76.24 53654[84:Spt:53653.0,52574.1,52576.0] || xuntil6(s39)* -> . % 76.04/76.24 53655[84:Spt:53653.0,52574.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.24 53658[84:Res:53655.0,61.1] always3(s39) || -> . % 76.04/76.24 53659[84:SSi:53658.0,728.0,52564.0] || -> . % 76.04/76.24 53660[82:Spt:53659.0,52558.2,52563.0] || xuntil6(s38)*+ -> . % 76.04/76.24 53661[82:Spt:53659.0,52558.0,52558.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.24 53662[82:Res:53.1,53661.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.24 53664[82:MRR:53662.0,52550.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.24 53666[82:Res:53664.0,61.1] always3(s39) || -> . % 76.04/76.24 53667[82:SSi:53666.0,728.0] || -> . % 76.04/76.24 53668[81:Spt:53667.0,52554.1,52556.0] || xuntil6(s37)* -> . % 76.04/76.24 53669[81:Spt:53667.0,52554.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.24 53672[81:Res:53669.0,61.1] always3(s37) || -> . % 76.04/76.24 53673[81:SSi:53672.0,726.0,52544.0] || -> . % 76.04/76.24 53674[79:Spt:53673.0,52541.2,52543.0] || xuntil6(s36)*+ -> . % 76.04/76.24 53675[79:Spt:53673.0,52541.0,52541.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.24 53676[79:Res:53.1,53675.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.24 53678[79:MRR:53676.0,52530.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.24 53680[79:Res:53678.0,61.1] always3(s37) || -> . % 76.04/76.24 53681[79:SSi:53680.0,726.0] || -> . % 76.04/76.24 53682[78:Spt:53681.0,52534.1,52539.0] || xuntil6(s35)* -> . % 76.04/76.24 53683[78:Spt:53681.0,52534.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.24 53686[78:Res:53683.0,61.1] always3(s35) || -> . % 76.04/76.24 53687[78:SSi:53686.0,724.0,52524.0] || -> . % 76.04/76.24 53688[76:Spt:53687.0,52515.2,52523.0] || xuntil6(s34)*+ -> . % 76.04/76.24 53689[76:Spt:53687.0,52515.0,52515.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.24 53690[76:Res:53.1,53689.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.24 53692[76:MRR:53690.0,52507.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.24 53694[76:Res:53692.0,61.1] always3(s35) || -> . % 76.04/76.24 53695[76:SSi:53694.0,724.0] || -> . % 76.04/76.24 53696[75:Spt:53695.0,52511.1,52513.0] || xuntil6(s33)* -> . % 76.04/76.24 53697[75:Spt:53695.0,52511.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.24 53700[75:Res:53697.0,61.1] always3(s33) || -> . % 76.04/76.24 53701[75:SSi:53700.0,722.0,52501.0] || -> . % 76.04/76.24 53702[73:Spt:53701.0,52495.2,52500.0] || xuntil6(s32)*+ -> . % 76.04/76.24 53703[73:Spt:53701.0,52495.0,52495.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.24 53704[73:Res:53.1,53703.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.24 53706[73:MRR:53704.0,52487.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.24 53708[73:Res:53706.0,61.1] always3(s33) || -> . % 76.04/76.24 53709[73:SSi:53708.0,722.0] || -> . % 76.04/76.24 53710[72:Spt:53709.0,52491.1,52493.0] || xuntil6(s31)* -> . % 76.04/76.24 53711[72:Spt:53709.0,52491.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.24 53714[72:Res:53711.0,61.1] always3(s31) || -> . % 76.04/76.24 53715[72:SSi:53714.0,720.0,52478.0] || -> . % 76.04/76.24 53716[70:Spt:53715.0,52476.2,52477.0] || xuntil6(s30)*+ -> . % 76.04/76.24 53717[70:Spt:53715.0,52476.0,52476.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.24 53718[70:Res:53.1,53717.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.24 53720[71:Spt:53718.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.24 53722[71:Res:53720.0,61.1] always3(s31) || -> . % 76.04/76.24 53723[71:SSi:53722.0,720.0] || -> . % 76.04/76.24 53724[71:Spt:53723.0,53718.1,53720.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.24 53725[71:Spt:53723.0,53718.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.24 53728[71:Res:53725.0,61.1] always3(s30) || -> . % 76.04/76.24 53729[71:SSi:53728.0,719.0,52475.0] || -> . % 76.04/76.24 53730[69:Spt:53729.0,52470.2,52474.0] || xuntil6(s29)*+ -> . % 76.04/76.24 53731[69:Spt:53729.0,52470.0,52470.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.24 53732[69:Res:53.1,53731.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.24 53734[70:Spt:53732.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.24 53736[70:Res:53734.0,61.1] always3(s30) || -> . % 76.04/76.24 53737[70:SSi:53736.0,719.0] || -> . % 76.04/76.24 53738[70:Spt:53737.0,53732.1,53734.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.24 53739[70:Spt:53737.0,53732.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.24 53742[70:Res:53739.0,61.1] always3(s29) || -> . % 76.04/76.24 53743[70:SSi:53742.0,718.0,52469.0] || -> . % 76.04/76.24 53744[68:Spt:53743.0,52467.2,52468.0] || xuntil6(s28)*+ -> . % 76.04/76.24 53745[68:Spt:53743.0,52467.0,52467.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.24 53746[68:Res:53.1,53745.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.24 53748[69:Spt:53746.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.24 53750[69:Res:53748.0,61.1] always3(s29) || -> . % 76.04/76.24 53751[69:SSi:53750.0,718.0] || -> . % 76.04/76.24 53752[69:Spt:53751.0,53746.1,53748.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.24 53753[69:Spt:53751.0,53746.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.24 53756[69:Res:53753.0,61.1] always3(s28) || -> . % 76.04/76.24 53757[69:SSi:53756.0,717.0,52466.0] || -> . % 76.04/76.24 53758[67:Spt:53757.0,52461.2,52465.0] || xuntil6(s27)*+ -> . % 76.04/76.24 53759[67:Spt:53757.0,52461.0,52461.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.24 53760[67:Res:53.1,53759.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.24 53762[68:Spt:53760.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.24 53764[68:Res:53762.0,61.1] always3(s28) || -> . % 76.04/76.24 53765[68:SSi:53764.0,717.0] || -> . % 76.04/76.24 53766[68:Spt:53765.0,53760.1,53762.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.24 53767[68:Spt:53765.0,53760.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.24 53770[68:Res:53767.0,61.1] always3(s27) || -> . % 76.04/76.24 53771[68:SSi:53770.0,716.0,52460.0] || -> . % 76.04/76.24 53772[66:Spt:53771.0,52458.2,52459.0] || xuntil6(s26)*+ -> . % 76.04/76.24 53773[66:Spt:53771.0,52458.0,52458.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.24 53774[66:Res:53.1,53773.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.24 53776[67:Spt:53774.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.24 53778[67:Res:53776.0,61.1] always3(s27) || -> . % 76.04/76.24 53779[67:SSi:53778.0,716.0] || -> . % 76.04/76.24 53780[67:Spt:53779.0,53774.1,53776.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.24 53781[67:Spt:53779.0,53774.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.24 53784[67:Res:53781.0,61.1] always3(s26) || -> . % 76.04/76.24 53785[67:SSi:53784.0,715.0,52457.0] || -> . % 76.04/76.24 53786[65:Spt:53785.0,52452.2,52456.0] || xuntil6(s25)*+ -> . % 76.04/76.24 53787[65:Spt:53785.0,52452.0,52452.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.24 53788[65:Res:53.1,53787.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.24 53790[66:Spt:53788.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.24 53792[66:Res:53790.0,61.1] always3(s26) || -> . % 76.04/76.24 53793[66:SSi:53792.0,715.0] || -> . % 76.04/76.24 53794[66:Spt:53793.0,53788.1,53790.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.24 53795[66:Spt:53793.0,53788.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.24 53798[66:Res:53795.0,61.1] always3(s25) || -> . % 76.04/76.24 53799[66:SSi:53798.0,714.0,52451.0] || -> . % 76.04/76.24 53800[64:Spt:53799.0,52449.2,52450.0] || xuntil6(s24)*+ -> . % 76.04/76.24 53801[64:Spt:53799.0,52449.0,52449.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.24 53802[64:Res:53.1,53801.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.24 53804[65:Spt:53802.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.24 53806[65:Res:53804.0,61.1] always3(s25) || -> . % 76.04/76.24 53807[65:SSi:53806.0,714.0] || -> . % 76.04/76.24 53808[65:Spt:53807.0,53802.1,53804.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.24 53809[65:Spt:53807.0,53802.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.24 53812[65:Res:53809.0,61.1] always3(s24) || -> . % 76.04/76.24 53813[65:SSi:53812.0,713.0,52448.0] || -> . % 76.04/76.24 53814[63:Spt:53813.0,52443.2,52447.0] || xuntil6(s23)*+ -> . % 76.04/76.24 53815[63:Spt:53813.0,52443.0,52443.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.24 53816[63:Res:53.1,53815.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.24 53818[64:Spt:53816.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.24 53820[64:Res:53818.0,61.1] always3(s24) || -> . % 76.04/76.24 53821[64:SSi:53820.0,713.0] || -> . % 76.04/76.24 53822[64:Spt:53821.0,53816.1,53818.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.24 53823[64:Spt:53821.0,53816.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.24 53826[64:Res:53823.0,61.1] always3(s23) || -> . % 76.04/76.24 53827[64:SSi:53826.0,712.0,52442.0] || -> . % 76.04/76.24 53828[62:Spt:53827.0,52440.2,52441.0] || xuntil6(s22)*+ -> . % 76.04/76.24 53829[62:Spt:53827.0,52440.0,52440.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.24 53830[62:Res:53.1,53829.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.24 53832[63:Spt:53830.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.24 53834[63:Res:53832.0,61.1] always3(s23) || -> . % 76.04/76.24 53835[63:SSi:53834.0,712.0] || -> . % 76.04/76.24 53836[63:Spt:53835.0,53830.1,53832.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.24 53837[63:Spt:53835.0,53830.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.24 53840[63:Res:53837.0,61.1] always3(s22) || -> . % 76.04/76.24 53841[63:SSi:53840.0,711.0,52439.0] || -> . % 76.04/76.24 53842[61:Spt:53841.0,52434.2,52438.0] || xuntil6(s21)*+ -> . % 76.04/76.24 53843[61:Spt:53841.0,52434.0,52434.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.24 53844[61:Res:53.1,53843.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.24 53846[62:Spt:53844.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.24 53848[62:Res:53846.0,61.1] always3(s22) || -> . % 76.04/76.24 53849[62:SSi:53848.0,711.0] || -> . % 76.04/76.24 53850[62:Spt:53849.0,53844.1,53846.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.24 53851[62:Spt:53849.0,53844.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.24 53854[62:Res:53851.0,61.1] always3(s21) || -> . % 76.04/76.24 53855[62:SSi:53854.0,710.0,52433.0] || -> . % 76.04/76.24 53856[60:Spt:53855.0,52431.2,52432.0] || xuntil6(s20)*+ -> . % 76.04/76.24 53857[60:Spt:53855.0,52431.0,52431.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.24 53858[60:Res:53.1,53857.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.24 53863[61:Spt:53858.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.24 53865[61:Res:53863.0,61.1] always3(s20) || -> . % 76.04/76.24 53866[61:SSi:53865.0,709.0,52430.0] || -> . % 76.04/76.24 53867[61:Spt:53866.0,53858.0,53863.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.24 53868[61:Spt:53866.0,53858.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.24 53872[61:Res:53868.0,61.1] always3(s21) || -> . % 76.04/76.24 53873[61:SSi:53872.0,710.0] || -> . % 76.04/76.24 53874[59:Spt:53873.0,52425.2,52429.0] || xuntil6(s19)*+ -> . % 76.04/76.24 53875[59:Spt:53873.0,52425.0,52425.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.24 53876[59:Res:53.1,53875.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.24 53878[60:Spt:53876.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.24 53880[60:Res:53878.0,61.1] always3(s20) || -> . % 76.04/76.24 53881[60:SSi:53880.0,709.0] || -> . % 76.04/76.24 53882[60:Spt:53881.0,53876.1,53878.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.24 53883[60:Spt:53881.0,53876.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.24 53886[60:Res:53883.0,61.1] always3(s19) || -> . % 76.04/76.24 53887[60:SSi:53886.0,708.0,52424.0] || -> . % 76.04/76.24 53888[58:Spt:53887.0,52422.2,52423.0] || xuntil6(s18)*+ -> . % 76.04/76.24 53889[58:Spt:53887.0,52422.0,52422.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.24 53890[58:Res:53.1,53889.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.24 53892[59:Spt:53890.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.24 53894[59:Res:53892.0,61.1] always3(s19) || -> . % 76.04/76.24 53895[59:SSi:53894.0,708.0] || -> . % 76.04/76.24 53896[59:Spt:53895.0,53890.1,53892.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.24 53897[59:Spt:53895.0,53890.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.24 53900[59:Res:53897.0,61.1] always3(s18) || -> . % 76.04/76.24 53901[59:SSi:53900.0,707.0,52421.0] || -> . % 76.04/76.24 53902[57:Spt:53901.0,52416.2,52420.0] || xuntil6(s17)*+ -> . % 76.04/76.24 53903[57:Spt:53901.0,52416.0,52416.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.24 53904[57:Res:53.1,53903.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.24 53909[58:Spt:53904.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.24 53911[58:Res:53909.0,61.1] always3(s17) || -> . % 76.04/76.24 53912[58:SSi:53911.0,706.0,52415.0] || -> . % 76.04/76.24 53913[58:Spt:53912.0,53904.0,53909.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.24 53914[58:Spt:53912.0,53904.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.24 53918[58:Res:53914.0,61.1] always3(s18) || -> . % 76.04/76.24 53919[58:SSi:53918.0,707.0] || -> . % 76.04/76.24 53920[56:Spt:53919.0,52413.2,52414.0] || xuntil6(s16)*+ -> . % 76.04/76.24 53921[56:Spt:53919.0,52413.0,52413.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.24 53922[56:Res:53.1,53921.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.24 53924[57:Spt:53922.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.24 53926[57:Res:53924.0,61.1] always3(s17) || -> . % 76.04/76.24 53927[57:SSi:53926.0,706.0] || -> . % 76.04/76.24 53928[57:Spt:53927.0,53922.1,53924.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.24 53929[57:Spt:53927.0,53922.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.24 53932[57:Res:53929.0,61.1] always3(s16) || -> . % 76.04/76.24 53933[57:SSi:53932.0,705.0,52412.0] || -> . % 76.04/76.24 53934[55:Spt:53933.0,52407.2,52411.0] || xuntil6(s15)*+ -> . % 76.04/76.24 53935[55:Spt:53933.0,52407.0,52407.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.24 53936[55:Res:53.1,53935.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.24 53938[56:Spt:53936.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.24 53940[56:Res:53938.0,61.1] always3(s16) || -> . % 76.04/76.24 53941[56:SSi:53940.0,705.0] || -> . % 76.04/76.24 53942[56:Spt:53941.0,53936.1,53938.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.24 53943[56:Spt:53941.0,53936.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.24 53946[56:Res:53943.0,61.1] always3(s15) || -> . % 76.04/76.24 53947[56:SSi:53946.0,704.0,52406.0] || -> . % 76.04/76.24 53948[54:Spt:53947.0,52404.2,52405.0] || xuntil6(s14)*+ -> . % 76.04/76.24 53949[54:Spt:53947.0,52404.0,52404.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.24 53950[54:Res:53.1,53949.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.24 53955[55:Spt:53950.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.24 53957[55:Res:53955.0,61.1] always3(s15) || -> . % 76.04/76.24 53958[55:SSi:53957.0,704.0] || -> . % 76.04/76.24 53959[55:Spt:53958.0,53950.1,53955.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.24 53960[55:Spt:53958.0,53950.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.24 53963[55:Res:53960.0,61.1] always3(s14) || -> . % 76.04/76.24 53964[55:SSi:53963.0,703.0,52403.0] || -> . % 76.04/76.24 53965[53:Spt:53964.0,52398.2,52402.0] || xuntil6(s13)*+ -> . % 76.04/76.24 53966[53:Spt:53964.0,52398.0,52398.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.24 53967[53:Res:53.1,53966.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.24 53969[54:Spt:53967.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.24 53971[54:Res:53969.0,61.1] always3(s13) || -> . % 76.04/76.24 53972[54:SSi:53971.0,702.0,52397.0] || -> . % 76.04/76.24 53973[54:Spt:53972.0,53967.0,53969.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.24 53974[54:Spt:53972.0,53967.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.24 53978[54:Res:53974.0,61.1] always3(s14) || -> . % 76.04/76.24 53979[54:SSi:53978.0,703.0] || -> . % 76.04/76.24 53980[52:Spt:53979.0,52395.2,52396.0] || xuntil6(s12)*+ -> . % 76.04/76.24 53981[52:Spt:53979.0,52395.0,52395.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.24 53982[52:Res:53.1,53981.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.24 53984[53:Spt:53982.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.24 53986[53:Res:53984.0,61.1] always3(s13) || -> . % 76.04/76.24 53987[53:SSi:53986.0,702.0] || -> . % 76.04/76.24 53988[53:Spt:53987.0,53982.1,53984.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.24 53989[53:Spt:53987.0,53982.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.24 53992[53:Res:53989.0,61.1] always3(s12) || -> . % 76.04/76.24 53993[53:SSi:53992.0,701.0,52394.0] || -> . % 76.04/76.24 53994[51:Spt:53993.0,52389.2,52393.0] || xuntil6(s11)*+ -> . % 76.04/76.24 53995[51:Spt:53993.0,52389.0,52389.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.24 53996[51:Res:53.1,53995.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.24 54001[52:Spt:53996.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.24 54003[52:Res:54001.0,61.1] always3(s11) || -> . % 76.04/76.24 54004[52:SSi:54003.0,700.0,52388.0] || -> . % 76.04/76.24 54005[52:Spt:54004.0,53996.0,54001.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.24 54006[52:Spt:54004.0,53996.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.24 54010[52:Res:54006.0,61.1] always3(s12) || -> . % 76.04/76.24 54011[52:SSi:54010.0,701.0] || -> . % 76.04/76.24 54012[50:Spt:54011.0,52386.2,52387.0] || xuntil6(s10)*+ -> . % 76.04/76.24 54013[50:Spt:54011.0,52386.0,52386.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.24 54014[50:Res:53.1,54013.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.24 54016[51:Spt:54014.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.24 54018[51:Res:54016.0,61.1] always3(s10) || -> . % 76.04/76.24 54019[51:SSi:54018.0,699.0,52385.0] || -> . % 76.04/76.24 54020[51:Spt:54019.0,54014.0,54016.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.24 54021[51:Spt:54019.0,54014.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.24 54025[51:Res:54021.0,61.1] always3(s11) || -> . % 76.04/76.24 54026[51:SSi:54025.0,700.0] || -> . % 76.04/76.24 54027[49:Spt:54026.0,52380.2,52384.0] || xuntil6(s9)*+ -> . % 76.04/76.24 54028[49:Spt:54026.0,52380.0,52380.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.24 54029[49:Res:53.1,54028.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.24 54031[50:Spt:54029.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.24 54033[50:Res:54031.0,61.1] always3(s9) || -> . % 76.04/76.24 54034[50:SSi:54033.0,698.0,52379.0] || -> . % 76.04/76.24 54035[50:Spt:54034.0,54029.0,54031.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.24 54036[50:Spt:54034.0,54029.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.24 54040[50:Res:54036.0,61.1] always3(s10) || -> . % 76.04/76.24 54041[50:SSi:54040.0,699.0] || -> . % 76.04/76.24 54042[48:Spt:54041.0,52377.2,52378.0] || xuntil6(s8)*+ -> . % 76.04/76.24 54043[48:Spt:54041.0,52377.0,52377.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.24 54044[48:Res:53.1,54043.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.24 54049[49:Spt:54044.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.24 54051[49:Res:54049.0,61.1] always3(s8) || -> . % 76.04/76.24 54052[49:SSi:54051.0,697.0,52376.0] || -> . % 76.04/76.24 54053[49:Spt:54052.0,54044.0,54049.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.24 54054[49:Spt:54052.0,54044.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.24 54058[49:Res:54054.0,61.1] always3(s9) || -> . % 76.04/76.24 54059[49:SSi:54058.0,698.0] || -> . % 76.04/76.24 54060[47:Spt:54059.0,52371.2,52375.0] || xuntil6(s7)*+ -> . % 76.04/76.24 54061[47:Spt:54059.0,52371.0,52371.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.24 54062[47:Res:53.1,54061.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.24 54064[48:Spt:54062.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.24 54066[48:Res:54064.0,61.1] always3(s7) || -> . % 76.04/76.24 54067[48:SSi:54066.0,696.0,52370.0] || -> . % 76.04/76.24 54068[48:Spt:54067.0,54062.0,54064.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.24 54069[48:Spt:54067.0,54062.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.24 54073[48:Res:54069.0,61.1] always3(s8) || -> . % 76.04/76.24 54074[48:SSi:54073.0,697.0] || -> . % 76.04/76.24 54075[46:Spt:54074.0,52368.2,52369.0] || xuntil6(s6)*+ -> . % 76.04/76.24 54076[46:Spt:54074.0,52368.0,52368.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.24 54077[46:Res:53.1,54076.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.24 54079[47:Spt:54077.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.24 54081[47:Res:54079.0,61.1] always3(s6) || -> . % 76.04/76.24 54082[47:SSi:54081.0,695.0,52367.0] || -> . % 76.04/76.24 54083[47:Spt:54082.0,54077.0,54079.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.24 54084[47:Spt:54082.0,54077.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.24 54088[47:Res:54084.0,61.1] always3(s7) || -> . % 76.04/76.24 54089[47:SSi:54088.0,696.0] || -> . % 76.04/76.24 54090[45:Spt:54089.0,52362.2,52366.0] || xuntil6(s5)*+ -> . % 76.04/76.24 54091[45:Spt:54089.0,52362.0,52362.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.24 54092[45:Res:53.1,54091.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.24 54097[46:Spt:54092.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.24 54099[46:Res:54097.0,61.1] always3(s5) || -> . % 76.04/76.24 54100[46:SSi:54099.0,694.0,52361.0] || -> . % 76.04/76.24 54101[46:Spt:54100.0,54092.0,54097.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.24 54102[46:Spt:54100.0,54092.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.24 54106[46:Res:54102.0,61.1] always3(s6) || -> . % 76.04/76.24 54107[46:SSi:54106.0,695.0] || -> . % 76.04/76.24 54108[44:Spt:54107.0,52359.2,52360.0] || xuntil6(s4)*+ -> . % 76.04/76.24 54109[44:Spt:54107.0,52359.0,52359.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.24 54110[44:Res:53.1,54109.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.24 54112[45:Spt:54110.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.24 54114[45:Res:54112.0,61.1] always3(s4) || -> . % 76.04/76.24 54115[45:SSi:54114.0,693.0,52358.0] || -> . % 76.04/76.24 54116[45:Spt:54115.0,54110.0,54112.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.24 54117[45:Spt:54115.0,54110.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.24 54121[45:Res:54117.0,61.1] always3(s5) || -> . % 76.04/76.24 54122[45:SSi:54121.0,694.0] || -> . % 76.04/76.24 54123[43:Spt:54122.0,52356.2,52357.0] || xuntil6(s3)*+ -> . % 76.04/76.24 54124[43:Spt:54122.0,52356.0,52356.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.24 54125[43:Res:53.1,54124.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.24 54127[44:Spt:54125.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.24 54129[44:Res:54127.0,61.1] always3(s3) || -> . % 76.04/76.24 54130[44:SSi:54129.0,692.0,52355.0] || -> . % 76.04/76.24 54131[44:Spt:54130.0,54125.0,54127.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.24 54132[44:Spt:54130.0,54125.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.24 54136[44:Res:54132.0,61.1] always3(s4) || -> . % 76.04/76.24 54137[44:SSi:54136.0,693.0] || -> . % 76.04/76.24 54138[42:Spt:54137.0,52353.2,52354.0] || xuntil6(s2)*+ -> . % 76.04/76.24 54139[42:Spt:54137.0,52353.0,52353.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.24 54140[42:Res:53.1,54139.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.24 54145[43:Spt:54140.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.24 54147[43:Res:54145.0,61.1] always3(s2) || -> . % 76.04/76.24 54148[43:SSi:54147.0,691.0,52352.0] || -> . % 76.04/76.24 54149[43:Spt:54148.0,54140.0,54145.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.24 54150[43:Spt:54148.0,54140.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.24 54154[43:Res:54150.0,61.1] always3(s3) || -> . % 76.04/76.24 54155[43:SSi:54154.0,692.0] || -> . % 76.04/76.24 54156[41:Spt:54155.0,52347.2,52351.0] || xuntil6(s1)*+ -> . % 76.04/76.24 54157[41:Spt:54155.0,52347.0,52347.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.24 54158[41:Res:53.1,54157.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.24 54160[42:Spt:54158.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.24 54162[42:Res:54160.0,61.1] always3(s1) || -> . % 76.04/76.24 54163[42:SSi:54162.0,690.0,52346.0] || -> . % 76.04/76.24 54164[42:Spt:54163.0,54158.0,54160.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.24 54165[42:Spt:54163.0,54158.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.24 54170[42:Res:54165.0,61.1] always3(s2) || -> . % 76.04/76.24 54171[42:SSi:54170.0,691.0] || -> . % 76.04/76.24 54172[40:Spt:54171.0,74.0,52345.0] || xuntil6(s0)*+ -> . % 76.04/76.24 54173[40:Spt:54171.0,74.1] || -> node4(s0)*. % 76.04/76.24 54174[40:MRR:758.1,54172.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.24 54176[40:Res:54174.0,61.1] always3(s1) || -> . % 76.04/76.24 54177[40:SSi:54176.0,690.0] || -> . % 76.04/76.24 54178[39:Spt:54177.0,52335.0,52339.0] || trans(s49,s12)*+ -> . % 76.04/76.24 54179[39:Spt:54177.0,52335.1,52335.2,52335.3,52335.4,52335.5,52335.6,52335.7,52335.8,52335.9,52335.10,52335.11,52335.12] || -> trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.24 54181[39:MRR:52336.0,54178.0] || -> trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.24 54182[39:MRR:52338.1,54178.0] xuntil6(s49) || -> trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.24 54183[40:Spt:54179.0] || -> trans(s49,s11)*. % 76.04/76.24 54184[40:Res:54183.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s11)*. % 76.04/76.24 54186[40:Res:54183.0,60.0] || -> node2(s49,s11)*. % 76.04/76.24 54187[40:SSi:54184.1,50.0,738.0] xuntil6(s49) || -> until2p7(s11)*. % 76.04/76.24 54188[40:Res:54186.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)*. % 76.04/76.24 54189[41:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.24 54190[41:MRR:176.0,54189.0] || -> until5(s1)*. % 76.04/76.24 54191[41:MRR:52781.0,54190.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.24 54198[42:Spt:54191.2] || -> xuntil6(s1)*. % 76.04/76.24 54199[42:MRR:175.0,54198.0] || -> until5(s2)*. % 76.04/76.24 54200[42:MRR:52780.0,54199.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.24 54201[43:Spt:54200.2] || -> xuntil6(s2)*. % 76.04/76.24 54202[43:MRR:174.0,54201.0] || -> until5(s3)*. % 76.04/76.24 54203[43:MRR:52773.0,54202.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.24 54207[44:Spt:54203.2] || -> xuntil6(s3)*. % 76.04/76.24 54208[44:MRR:173.0,54207.0] || -> until5(s4)*. % 76.04/76.24 54209[44:MRR:52769.0,54208.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.24 54210[45:Spt:54209.2] || -> xuntil6(s4)*. % 76.04/76.24 54211[45:MRR:172.0,54210.0] || -> until5(s5)*. % 76.04/76.24 54212[45:MRR:52765.0,54211.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.24 54216[46:Spt:54212.2] || -> xuntil6(s5)*. % 76.04/76.24 54217[46:MRR:171.0,54216.0] || -> until5(s6)*. % 76.04/76.24 54218[46:MRR:52761.0,54217.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.24 54219[47:Spt:54218.2] || -> xuntil6(s6)*. % 76.04/76.24 54220[47:MRR:170.0,54219.0] || -> until5(s7)*. % 76.04/76.24 54221[47:MRR:52760.0,54220.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.24 54225[48:Spt:54221.2] || -> xuntil6(s7)*. % 76.04/76.24 54226[48:MRR:169.0,54225.0] || -> until5(s8)*. % 76.04/76.24 54227[48:MRR:52753.0,54226.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.24 54228[49:Spt:54227.2] || -> xuntil6(s8)*. % 76.04/76.24 54229[49:MRR:168.0,54228.0] || -> until5(s9)*. % 76.04/76.24 54230[49:MRR:52749.0,54229.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.24 54234[50:Spt:54230.2] || -> xuntil6(s9)*. % 76.04/76.24 54235[50:MRR:167.0,54234.0] || -> until5(s10)*. % 76.04/76.24 54236[50:MRR:52745.0,54235.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.24 54237[51:Spt:54236.2] || -> xuntil6(s10)*. % 76.04/76.24 54238[51:MRR:166.0,54237.0] || -> until5(s11)*. % 76.04/76.24 54239[51:MRR:52741.0,54238.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.24 54243[52:Spt:54239.2] || -> xuntil6(s11)*. % 76.04/76.24 54244[52:MRR:165.0,54243.0] || -> until5(s12)*. % 76.04/76.24 54245[52:MRR:52740.0,54244.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.24 54246[53:Spt:54245.2] || -> xuntil6(s12)*. % 76.04/76.24 54247[53:MRR:164.0,54246.0] || -> until5(s13)*. % 76.04/76.24 54248[53:MRR:52730.0,54247.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.24 54252[54:Spt:54248.2] || -> xuntil6(s13)*. % 76.04/76.24 54253[54:MRR:163.0,54252.0] || -> until5(s14)*. % 76.04/76.24 54254[54:MRR:52729.0,54253.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.24 54255[55:Spt:54254.2] || -> xuntil6(s14)*. % 76.04/76.24 54256[55:MRR:162.0,54255.0] || -> until5(s15)*. % 76.04/76.24 54257[55:MRR:52725.0,54256.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.24 54261[56:Spt:54257.2] || -> xuntil6(s15)*. % 76.04/76.24 54262[56:MRR:161.0,54261.0] || -> until5(s16)*. % 76.04/76.24 54263[56:MRR:52718.0,54262.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.24 54264[57:Spt:54263.2] || -> xuntil6(s16)*. % 76.04/76.24 54265[57:MRR:160.0,54264.0] || -> until5(s17)*. % 76.04/76.24 54266[57:MRR:52714.0,54265.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.24 54270[58:Spt:54266.2] || -> xuntil6(s17)*. % 76.04/76.24 54271[58:MRR:159.0,54270.0] || -> until5(s18)*. % 76.04/76.24 54272[58:MRR:52713.0,54271.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.24 54273[59:Spt:54272.2] || -> xuntil6(s18)*. % 76.04/76.24 54274[59:MRR:158.0,54273.0] || -> until5(s19)*. % 76.04/76.24 54275[59:MRR:52709.0,54274.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.24 54279[60:Spt:54275.2] || -> xuntil6(s19)*. % 76.04/76.24 54280[60:MRR:157.0,54279.0] || -> until5(s20)*. % 76.04/76.24 54281[60:MRR:52702.0,54280.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.24 54282[61:Spt:54281.2] || -> xuntil6(s20)*. % 76.04/76.24 54283[61:MRR:156.0,54282.0] || -> until5(s21)*. % 76.04/76.24 54284[61:MRR:52701.0,54283.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.24 54288[62:Spt:54284.2] || -> xuntil6(s21)*. % 76.04/76.24 54289[62:MRR:155.0,54288.0] || -> until5(s22)*. % 76.04/76.24 54290[62:MRR:52694.0,54289.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.24 54291[63:Spt:54290.2] || -> xuntil6(s22)*. % 76.04/76.24 54292[63:MRR:154.0,54291.0] || -> until5(s23)*. % 76.04/76.24 54293[63:MRR:52690.0,54292.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.24 54297[64:Spt:54293.2] || -> xuntil6(s23)*. % 76.04/76.24 54298[64:MRR:153.0,54297.0] || -> until5(s24)*. % 76.04/76.24 54299[64:MRR:52689.0,54298.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.24 54300[65:Spt:54299.2] || -> xuntil6(s24)*. % 76.04/76.24 54301[65:MRR:152.0,54300.0] || -> until5(s25)*. % 76.04/76.24 54302[65:MRR:52682.0,54301.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.24 54306[66:Spt:54302.2] || -> xuntil6(s25)*. % 76.04/76.24 54307[66:MRR:151.0,54306.0] || -> until5(s26)*. % 76.04/76.24 54308[66:MRR:52678.0,54307.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.24 54309[67:Spt:54308.2] || -> xuntil6(s26)*. % 76.04/76.24 54310[67:MRR:150.0,54309.0] || -> until5(s27)*. % 76.04/76.24 54311[67:MRR:52674.0,54310.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.24 54315[68:Spt:54311.2] || -> xuntil6(s27)*. % 76.04/76.24 54316[68:MRR:149.0,54315.0] || -> until5(s28)*. % 76.04/76.24 54317[68:MRR:52673.0,54316.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.24 54318[69:Spt:54317.2] || -> xuntil6(s28)*. % 76.04/76.24 54319[69:MRR:148.0,54318.0] || -> until5(s29)*. % 76.04/76.24 54320[69:MRR:52672.0,54319.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.24 54324[70:Spt:54320.2] || -> xuntil6(s29)*. % 76.04/76.24 54325[70:MRR:147.0,54324.0] || -> until5(s30)*. % 76.04/76.24 54326[70:MRR:52671.0,54325.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.24 54327[71:Spt:54326.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.24 54329[71:Res:54327.0,61.1] always3(s31) || -> . % 76.04/76.24 54330[71:SSi:54329.0,720.0] || -> . % 76.04/76.24 54331[71:Spt:54330.0,54326.1,54327.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.04/76.24 54332[71:Spt:54330.0,54326.0,54326.2] || m_main_v_state(s30,c_ready)*+ -> xuntil6(s30). % 76.04/76.24 54334[71:MRR:828.2,54331.0] node4(s30) || m_main_v_state(s30,c_ready)* -> . % 76.04/76.24 54335[71:Res:53.1,54332.0] || -> m_main_v_state(s30,c_busy)* xuntil6(s30). % 76.04/76.24 54340[72:Spt:54335.1] || -> xuntil6(s30)*. % 76.04/76.24 54341[72:MRR:146.0,54340.0] || -> until5(s31)*. % 76.04/76.24 54342[72:MRR:50973.0,54341.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.24 54344[73:Spt:54342.2] || -> xuntil6(s31)*. % 76.04/76.24 54345[73:MRR:145.0,54344.0] || -> until5(s32)*. % 76.04/76.24 54346[73:MRR:52791.0,54345.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.24 54347[74:Spt:54346.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.24 54349[74:Res:54347.0,61.1] always3(s33) || -> . % 76.04/76.24 54350[74:SSi:54349.0,722.0] || -> . % 76.04/76.24 54351[74:Spt:54350.0,54346.1,54347.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.04/76.24 54352[74:Spt:54350.0,54346.0,54346.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 76.04/76.24 54354[74:MRR:822.2,54351.0] node4(s32) || m_main_v_state(s32,c_ready)* -> . % 76.04/76.24 54355[74:Res:53.1,54352.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 76.04/76.24 54357[75:Spt:54355.1] || -> xuntil6(s32)*. % 76.04/76.24 54358[75:MRR:144.0,54357.0] || -> until5(s33)*. % 76.04/76.24 54359[75:MRR:50980.0,54358.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.24 54364[76:Spt:54359.2] || -> xuntil6(s33)*. % 76.04/76.24 54365[76:MRR:143.0,54364.0] || -> until5(s34)*. % 76.04/76.24 54366[76:MRR:52792.0,54365.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.24 54367[77:Spt:54366.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.24 54369[77:Res:54367.0,61.1] always3(s35) || -> . % 76.04/76.24 54370[77:SSi:54369.0,724.0] || -> . % 76.04/76.24 54371[77:Spt:54370.0,54366.1,54367.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.04/76.24 54372[77:Spt:54370.0,54366.0,54366.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 76.04/76.24 54374[77:MRR:816.2,54371.0] node4(s34) || m_main_v_state(s34,c_ready)* -> . % 76.04/76.24 54375[77:Res:53.1,54372.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 76.04/76.24 54377[78:Spt:54375.1] || -> xuntil6(s34)*. % 76.04/76.24 54378[78:MRR:142.0,54377.0] || -> until5(s35)*. % 76.04/76.24 54379[78:MRR:50981.0,54378.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.24 54387[79:Spt:54379.2] || -> xuntil6(s35)*. % 76.04/76.24 54388[79:MRR:141.0,54387.0] || -> until5(s36)*. % 76.04/76.24 54389[79:MRR:52796.0,54388.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.24 54390[80:Spt:54389.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.24 54392[80:Res:54390.0,61.1] always3(s37) || -> . % 76.04/76.24 54393[80:SSi:54392.0,726.0] || -> . % 76.04/76.24 54394[80:Spt:54393.0,54389.1,54390.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.04/76.24 54395[80:Spt:54393.0,54389.0,54389.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 76.04/76.24 54397[80:MRR:810.2,54394.0] node4(s36) || m_main_v_state(s36,c_ready)* -> . % 76.04/76.24 54398[80:Res:53.1,54395.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 76.04/76.24 54403[81:Spt:54398.1] || -> xuntil6(s36)*. % 76.04/76.24 54404[81:MRR:140.0,54403.0] || -> until5(s37)*. % 76.04/76.24 54405[81:MRR:50985.0,54404.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.24 54407[82:Spt:54405.2] || -> xuntil6(s37)*. % 76.04/76.24 54408[82:MRR:139.0,54407.0] || -> until5(s38)*. % 76.04/76.24 54409[82:MRR:52800.0,54408.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.24 54410[83:Spt:54409.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.24 54412[83:Res:54410.0,61.1] always3(s39) || -> . % 76.04/76.24 54413[83:SSi:54412.0,728.0] || -> . % 76.04/76.24 54414[83:Spt:54413.0,54409.1,54410.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.04/76.24 54415[83:Spt:54413.0,54409.0,54409.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 76.04/76.24 54417[83:MRR:804.2,54414.0] node4(s38) || m_main_v_state(s38,c_ready)* -> . % 76.04/76.24 54418[83:Res:53.1,54415.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 76.04/76.24 54420[84:Spt:54418.1] || -> xuntil6(s38)*. % 76.04/76.24 54421[84:MRR:138.0,54420.0] || -> until5(s39)*. % 76.04/76.24 54422[84:MRR:50989.0,54421.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.24 54427[85:Spt:54422.2] || -> xuntil6(s39)*. % 76.04/76.24 54428[85:MRR:137.0,54427.0] || -> until5(s40)*. % 76.04/76.24 54429[85:MRR:52804.0,54428.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.24 54430[86:Spt:54429.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.24 54432[86:Res:54430.0,61.1] always3(s41) || -> . % 76.04/76.24 54433[86:SSi:54432.0,730.0] || -> . % 76.04/76.24 54434[86:Spt:54433.0,54429.1,54430.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.04/76.24 54435[86:Spt:54433.0,54429.0,54429.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 76.04/76.24 54437[86:MRR:798.2,54434.0] node4(s40) || m_main_v_state(s40,c_ready)* -> . % 76.04/76.24 54438[86:Res:53.1,54435.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 76.04/76.24 54440[87:Spt:54438.1] || -> xuntil6(s40)*. % 76.04/76.24 54441[87:MRR:136.0,54440.0] || -> until5(s41)*. % 76.04/76.24 54442[87:MRR:50993.0,54441.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.24 54450[88:Spt:54442.2] || -> xuntil6(s41)*. % 76.04/76.24 54451[88:MRR:135.0,54450.0] || -> until5(s42)*. % 76.04/76.24 54452[88:MRR:52811.0,54451.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.24 54453[89:Spt:54452.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.24 54455[89:Res:54453.0,61.1] always3(s43) || -> . % 76.04/76.24 54456[89:SSi:54455.0,732.0] || -> . % 76.04/76.24 54457[89:Spt:54456.0,54452.1,54453.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.04/76.24 54458[89:Spt:54456.0,54452.0,54452.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 76.04/76.24 54460[89:MRR:792.2,54457.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 76.04/76.24 54461[89:Res:53.1,54458.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 76.04/76.24 54466[90:Spt:54461.1] || -> xuntil6(s42)*. % 76.04/76.24 54467[90:MRR:134.0,54466.0] || -> until5(s43)*. % 76.04/76.24 54468[90:MRR:51000.0,54467.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.24 54470[91:Spt:54468.2] || -> xuntil6(s43)*. % 76.04/76.24 54471[91:MRR:133.0,54470.0] || -> until5(s44)*. % 76.04/76.24 54472[91:MRR:52812.0,54471.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.24 54473[92:Spt:54472.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.24 54475[92:Res:54473.0,61.1] always3(s45) || -> . % 76.04/76.24 54476[92:SSi:54475.0,734.0] || -> . % 76.04/76.24 54477[92:Spt:54476.0,54472.1,54473.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.04/76.24 54478[92:Spt:54476.0,54472.0,54472.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 76.04/76.24 54480[92:MRR:786.2,54477.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 76.04/76.24 54481[92:Res:53.1,54478.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 76.04/76.24 54483[93:Spt:54481.1] || -> xuntil6(s44)*. % 76.04/76.24 54484[93:MRR:132.0,54483.0] || -> until5(s45)*. % 76.04/76.24 54485[93:MRR:51001.0,54484.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.24 54490[94:Spt:54485.2] || -> xuntil6(s45)*. % 76.04/76.24 54491[94:MRR:131.0,54490.0] || -> until5(s46)*. % 76.04/76.24 54492[94:MRR:52816.0,54491.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.24 54493[95:Spt:54492.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.24 54495[95:Res:54493.0,61.1] always3(s47) || -> . % 76.04/76.24 54496[95:SSi:54495.0,736.0] || -> . % 76.04/76.24 54497[95:Spt:54496.0,54492.1,54493.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.04/76.24 54498[95:Spt:54496.0,54492.0,54492.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 76.04/76.24 54500[95:MRR:780.2,54497.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 76.04/76.24 54501[95:Res:53.1,54498.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 76.04/76.24 54503[96:Spt:54501.1] || -> xuntil6(s46)*. % 76.04/76.24 54504[96:MRR:130.0,54503.0] || -> until5(s47)*. % 76.04/76.24 54505[96:MRR:51005.0,54504.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.24 54513[97:Spt:54505.2] || -> xuntil6(s47)*. % 76.04/76.24 54514[97:MRR:129.0,54513.0] || -> until5(s48)*. % 76.04/76.24 54515[97:MRR:52820.0,54514.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.24 54516[98:Spt:54515.1] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.24 54518[98:Res:54516.0,61.1] always3(s49) || -> . % 76.04/76.24 54519[98:SSi:54518.0,50.0,738.0] || -> . % 76.04/76.24 54520[98:Spt:54519.0,54515.1,54516.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.24 54521[98:Spt:54519.0,54515.0,54515.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 76.04/76.24 54523[98:MRR:774.2,54520.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.24 54524[98:Res:53.1,54521.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 76.04/76.24 54529[99:Spt:54524.1] || -> xuntil6(s48)*. % 76.04/76.24 54530[99:MRR:128.0,54529.0] || -> until5(s49)*. % 76.04/76.24 54532[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.24 54536[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.24 54537[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.24 54538[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.24 54539[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.24 54543[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.24 54547[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.24 54554[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.24 54555[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.24 54559[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.24 54566[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.24 54567[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.24 54574[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.24 54578[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.24 54579[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.24 54583[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.24 54587[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.24 54594[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.24 54598[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.24 54605[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.24 54606[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.24 54610[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.24 54614[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.24 54618[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.24 54625[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.24 54626[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.24 54630[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.24 54634[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.24 54638[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.24 54645[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.24 54646[0:SoR:819.0,66.2] until5(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.24 54650[0:SoR:813.0,66.2] until5(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.24 54654[0:SoR:807.0,66.2] until5(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.24 54658[0:SoR:801.0,66.2] until5(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.24 54665[0:SoR:795.0,66.2] until5(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.24 54666[0:SoR:789.0,66.2] until5(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.24 54670[0:SoR:783.0,66.2] until5(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.24 54674[0:SoR:777.0,66.2] until5(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.24 54676[40:SoR:54188.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)*. % 76.04/76.24 54678[40:SoR:54676.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)* xuntil6(s49). % 76.04/76.24 54679[99:SSi:54678.0,50.0,738.0,54530.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s11,c_busy)* xuntil6(s49). % 76.04/76.24 54680[100:Spt:54679.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.24 54682[100:Res:54680.0,61.1] always3(s11) || -> . % 76.04/76.24 54683[100:SSi:54682.0,700.0,54238.0,54243.0] || -> . % 76.04/76.24 54684[100:Spt:54683.0,54679.1,54680.0] || m_main_v_state(s11,c_busy)*+ -> . % 76.04/76.24 54685[100:Spt:54683.0,54679.0,54679.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.24 54689[100:MRR:54676.2,54684.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.24 54690[100:Res:53.1,54685.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.24 54692[100:MRR:54690.0,54520.0] || -> xuntil6(s49)*. % 76.04/76.24 54693[100:MRR:54187.0,54692.0] || -> until2p7(s11)*. % 76.04/76.24 54694[100:MRR:207.0,54693.0] || -> until2p7(s12)* node4(s11). % 76.04/76.24 54695[101:Spt:54694.0] || -> until2p7(s12)*. % 76.04/76.24 54696[101:MRR:208.0,54695.0] || -> until2p7(s13)* node4(s12). % 76.04/76.24 54697[102:Spt:54696.0] || -> until2p7(s13)*. % 76.04/76.24 54698[102:MRR:209.0,54697.0] || -> until2p7(s14)* node4(s13). % 76.04/76.24 54699[103:Spt:54698.0] || -> until2p7(s14)*. % 76.04/76.24 54700[103:MRR:210.0,54699.0] || -> until2p7(s15)* node4(s14). % 76.04/76.24 54701[104:Spt:54700.0] || -> until2p7(s15)*. % 76.04/76.24 54702[104:MRR:211.0,54701.0] || -> until2p7(s16)* node4(s15). % 76.04/76.24 54703[105:Spt:54702.0] || -> until2p7(s16)*. % 76.04/76.24 54704[105:MRR:212.0,54703.0] || -> until2p7(s17)* node4(s16). % 76.04/76.24 54705[106:Spt:54704.0] || -> until2p7(s17)*. % 76.04/76.24 54706[106:MRR:213.0,54705.0] || -> until2p7(s18)* node4(s17). % 76.04/76.24 54707[107:Spt:54706.0] || -> until2p7(s18)*. % 76.04/76.24 54708[107:MRR:214.0,54707.0] || -> until2p7(s19)* node4(s18). % 76.04/76.24 54709[108:Spt:54708.0] || -> until2p7(s19)*. % 76.04/76.24 54710[108:MRR:215.0,54709.0] || -> until2p7(s20)* node4(s19). % 76.04/76.24 54711[109:Spt:54710.0] || -> until2p7(s20)*. % 76.04/76.24 54712[109:MRR:216.0,54711.0] || -> until2p7(s21)* node4(s20). % 76.04/76.24 54713[110:Spt:54712.0] || -> until2p7(s21)*. % 76.04/76.24 54714[110:MRR:217.0,54713.0] || -> until2p7(s22)* node4(s21). % 76.04/76.24 54715[111:Spt:54714.0] || -> until2p7(s22)*. % 76.04/76.24 54716[111:MRR:218.0,54715.0] || -> until2p7(s23)* node4(s22). % 76.04/76.24 54717[112:Spt:54716.0] || -> until2p7(s23)*. % 76.04/76.24 54718[112:MRR:219.0,54717.0] || -> until2p7(s24)* node4(s23). % 76.04/76.24 54719[113:Spt:54718.0] || -> until2p7(s24)*. % 76.04/76.24 54720[113:MRR:220.0,54719.0] || -> until2p7(s25)* node4(s24). % 76.04/76.24 54721[114:Spt:54720.0] || -> until2p7(s25)*. % 76.04/76.24 54722[114:MRR:221.0,54721.0] || -> until2p7(s26)* node4(s25). % 76.04/76.24 54723[115:Spt:54722.0] || -> until2p7(s26)*. % 76.04/76.24 54724[115:MRR:222.0,54723.0] || -> until2p7(s27)* node4(s26). % 76.04/76.24 54725[116:Spt:54724.0] || -> until2p7(s27)*. % 76.04/76.24 54726[116:MRR:223.0,54725.0] || -> until2p7(s28)* node4(s27). % 76.04/76.24 54727[117:Spt:54726.0] || -> until2p7(s28)*. % 76.04/76.24 54728[117:MRR:224.0,54727.0] || -> until2p7(s29)* node4(s28). % 76.04/76.24 54729[118:Spt:54728.0] || -> until2p7(s29)*. % 76.04/76.24 54730[118:MRR:225.0,54729.0] || -> until2p7(s30)* node4(s29). % 76.04/76.24 54731[119:Spt:54730.0] || -> until2p7(s30)*. % 76.04/76.24 54732[119:MRR:226.0,54731.0] || -> until2p7(s31)* node4(s30). % 76.04/76.24 54733[120:Spt:54732.0] || -> until2p7(s31)*. % 76.04/76.24 54734[120:MRR:227.0,54733.0] || -> until2p7(s32)* node4(s31). % 76.04/76.24 54735[121:Spt:54734.0] || -> until2p7(s32)*. % 76.04/76.24 54736[121:MRR:228.0,54735.0] || -> until2p7(s33)* node4(s32). % 76.04/76.24 54737[122:Spt:54736.0] || -> until2p7(s33)*. % 76.04/76.24 54738[122:MRR:229.0,54737.0] || -> until2p7(s34)* node4(s33). % 76.04/76.24 54739[123:Spt:54738.0] || -> until2p7(s34)*. % 76.04/76.24 54740[123:MRR:230.0,54739.0] || -> until2p7(s35)* node4(s34). % 76.04/76.24 54741[124:Spt:54740.0] || -> until2p7(s35)*. % 76.04/76.24 54742[124:MRR:231.0,54741.0] || -> until2p7(s36)* node4(s35). % 76.04/76.24 54743[125:Spt:54742.0] || -> until2p7(s36)*. % 76.04/76.24 54744[125:MRR:232.0,54743.0] || -> until2p7(s37)* node4(s36). % 76.04/76.24 54745[126:Spt:54744.0] || -> until2p7(s37)*. % 76.04/76.24 54746[126:MRR:235.0,54745.0] || -> until2p7(s38)* node4(s37). % 76.04/76.24 54747[127:Spt:54746.0] || -> until2p7(s38)*. % 76.04/76.24 54748[127:MRR:236.0,54747.0] || -> until2p7(s39)* node4(s38). % 76.04/76.24 54749[128:Spt:54748.0] || -> until2p7(s39)*. % 76.04/76.24 54750[128:MRR:237.0,54749.0] || -> until2p7(s40)* node4(s39). % 76.04/76.24 54751[129:Spt:54750.0] || -> until2p7(s40)*. % 76.04/76.24 54752[129:MRR:238.0,54751.0] || -> until2p7(s41)* node4(s40). % 76.04/76.24 54753[130:Spt:54752.0] || -> until2p7(s41)*. % 76.04/76.24 54754[130:MRR:239.0,54753.0] || -> until2p7(s42)* node4(s41). % 76.04/76.24 54755[131:Spt:54754.0] || -> until2p7(s42)*. % 76.04/76.24 54756[131:MRR:240.0,54755.0] || -> until2p7(s43)* node4(s42). % 76.04/76.24 54757[132:Spt:54756.0] || -> until2p7(s43)*. % 76.04/76.24 54758[132:MRR:241.0,54757.0] || -> until2p7(s44)* node4(s43). % 76.04/76.24 54759[133:Spt:54758.0] || -> until2p7(s44)*. % 76.04/76.24 54760[133:MRR:539.0,54759.0] || -> until2p7(s45)* node4(s44). % 76.04/76.24 54761[134:Spt:54760.0] || -> until2p7(s45)*. % 76.04/76.24 54762[134:MRR:544.0,54761.0] || -> until2p7(s46)* node4(s45). % 76.04/76.24 54763[135:Spt:54762.0] || -> until2p7(s46)*. % 76.04/76.24 54764[135:MRR:549.0,54763.0] || -> until2p7(s47)* node4(s46). % 76.04/76.24 54765[136:Spt:54764.0] || -> until2p7(s47)*. % 76.04/76.24 54766[136:MRR:554.0,54765.0] || -> until2p7(s48)* node4(s47). % 76.04/76.24 54767[137:Spt:54766.0] || -> until2p7(s48)*. % 76.04/76.24 54768[137:MRR:559.0,54767.0] || -> until2p7(s49)* node4(s48). % 76.04/76.24 54769[138:Spt:54768.0] || -> until2p7(s49)*. % 76.04/76.24 54770[138:MRR:194.0,54769.0] || -> node4(s49)*. % 76.04/76.24 54771[138:MRR:54689.0,54770.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.24 54772[138:Res:53.1,54771.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.24 54774[138:MRR:54772.0,54520.0] || -> . % 76.04/76.24 54775[138:Spt:54774.0,54768.0,54769.0] || until2p7(s49)*+ -> . % 76.04/76.24 54776[138:Spt:54774.0,54768.1] || -> node4(s48)*. % 76.04/76.24 54777[138:MRR:54523.0,54776.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.24 54780[138:Res:53.1,54777.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.24 54783[138:Res:54780.0,61.1] always3(s48) || -> . % 76.04/76.24 54784[138:SSi:54783.0,737.0,54514.0,54529.0,54767.0,54776.0] || -> . % 76.04/76.24 54785[137:Spt:54784.0,54766.0,54767.0] || until2p7(s48)*+ -> . % 76.04/76.24 54786[137:Spt:54784.0,54766.1] || -> node4(s47)*. % 76.04/76.24 54788[137:MRR:777.0,54786.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.24 54803[137:Res:53.1,54788.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.24 54805[137:MRR:54803.0,54497.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.24 54807[137:Res:54805.0,61.1] always3(s48) || -> . % 76.04/76.24 54808[137:SSi:54807.0,737.0,54514.0,54529.0] || -> . % 76.04/76.24 54809[136:Spt:54808.0,54764.0,54765.0] || until2p7(s47)*+ -> . % 76.04/76.24 54810[136:Spt:54808.0,54764.1] || -> node4(s46)*. % 76.04/76.24 54811[136:MRR:54500.0,54810.0] || m_main_v_state(s46,c_ready)*+ -> . % 76.04/76.24 54814[136:Res:53.1,54811.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.24 54817[136:Res:54814.0,61.1] always3(s46) || -> . % 76.04/76.24 54818[136:SSi:54817.0,735.0,54491.0,54503.0,54763.0,54810.0] || -> . % 76.04/76.24 54819[135:Spt:54818.0,54762.0,54763.0] || until2p7(s46)*+ -> . % 76.04/76.24 54820[135:Spt:54818.0,54762.1] || -> node4(s45)*. % 76.04/76.24 54822[135:MRR:783.0,54820.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.24 54834[135:Res:53.1,54822.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.24 54836[135:MRR:54834.0,54477.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.24 54841[135:Res:54836.0,61.1] always3(s46) || -> . % 76.04/76.24 54842[135:SSi:54841.0,735.0,54491.0,54503.0] || -> . % 76.04/76.24 54843[134:Spt:54842.0,54760.0,54761.0] || until2p7(s45)*+ -> . % 76.04/76.24 54844[134:Spt:54842.0,54760.1] || -> node4(s44)*. % 76.04/76.24 54845[134:MRR:54480.0,54844.0] || m_main_v_state(s44,c_ready)*+ -> . % 76.04/76.24 54848[134:Res:53.1,54845.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.24 54852[134:Res:54848.0,61.1] always3(s44) || -> . % 76.04/76.24 54853[134:SSi:54852.0,733.0,54471.0,54483.0,54759.0,54844.0] || -> . % 76.04/76.24 54854[133:Spt:54853.0,54758.0,54759.0] || until2p7(s44)*+ -> . % 76.04/76.24 54855[133:Spt:54853.0,54758.1] || -> node4(s43)*. % 76.04/76.24 54857[133:MRR:789.0,54855.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.24 54868[133:Res:53.1,54857.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.24 54870[133:MRR:54868.0,54457.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.24 54872[133:Res:54870.0,61.1] always3(s44) || -> . % 76.04/76.24 54873[133:SSi:54872.0,733.0,54471.0,54483.0] || -> . % 76.04/76.24 54874[132:Spt:54873.0,54756.0,54757.0] || until2p7(s43)*+ -> . % 76.04/76.24 54875[132:Spt:54873.0,54756.1] || -> node4(s42)*. % 76.04/76.24 54876[132:MRR:54460.0,54875.0] || m_main_v_state(s42,c_ready)*+ -> . % 76.04/76.24 54880[132:Res:53.1,54876.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.24 54883[132:Res:54880.0,61.1] always3(s42) || -> . % 76.04/76.24 54884[132:SSi:54883.0,731.0,54451.0,54466.0,54755.0,54875.0] || -> . % 76.04/76.24 54885[131:Spt:54884.0,54754.0,54755.0] || until2p7(s42)*+ -> . % 76.04/76.24 54886[131:Spt:54884.0,54754.1] || -> node4(s41)*. % 76.04/76.24 54888[131:MRR:795.0,54886.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.24 54899[131:Res:53.1,54888.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.24 54901[131:MRR:54899.0,54434.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.24 54903[131:Res:54901.0,61.1] always3(s42) || -> . % 76.04/76.24 54904[131:SSi:54903.0,731.0,54451.0,54466.0] || -> . % 76.04/76.24 54905[130:Spt:54904.0,54752.0,54753.0] || until2p7(s41)*+ -> . % 76.04/76.24 54906[130:Spt:54904.0,54752.1] || -> node4(s40)*. % 76.04/76.24 54907[130:MRR:54437.0,54906.0] || m_main_v_state(s40,c_ready)*+ -> . % 76.04/76.24 54910[130:Res:53.1,54907.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.24 54913[130:Res:54910.0,61.1] always3(s40) || -> . % 76.04/76.24 54914[130:SSi:54913.0,729.0,54428.0,54440.0,54751.0,54906.0] || -> . % 76.04/76.24 54915[129:Spt:54914.0,54750.0,54751.0] || until2p7(s40)*+ -> . % 76.04/76.24 54916[129:Spt:54914.0,54750.1] || -> node4(s39)*. % 76.04/76.24 54918[129:MRR:801.0,54916.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.24 54930[129:Res:53.1,54918.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.24 54932[129:MRR:54930.0,54414.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.24 54934[129:Res:54932.0,61.1] always3(s40) || -> . % 76.04/76.24 54935[129:SSi:54934.0,729.0,54428.0,54440.0] || -> . % 76.04/76.24 54936[128:Spt:54935.0,54748.0,54749.0] || until2p7(s39)*+ -> . % 76.04/76.24 54937[128:Spt:54935.0,54748.1] || -> node4(s38)*. % 76.04/76.24 54938[128:MRR:54417.0,54937.0] || m_main_v_state(s38,c_ready)*+ -> . % 76.04/76.24 54941[128:Res:53.1,54938.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.24 54944[128:Res:54941.0,61.1] always3(s38) || -> . % 76.04/76.24 54945[128:SSi:54944.0,727.0,54408.0,54420.0,54747.0,54937.0] || -> . % 76.04/76.24 54946[127:Spt:54945.0,54746.0,54747.0] || until2p7(s38)*+ -> . % 76.04/76.24 54947[127:Spt:54945.0,54746.1] || -> node4(s37)*. % 76.04/76.24 54949[127:MRR:807.0,54947.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.24 54961[127:Res:53.1,54949.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.24 54963[127:MRR:54961.0,54394.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.24 54968[127:Res:54963.0,61.1] always3(s38) || -> . % 76.04/76.24 54969[127:SSi:54968.0,727.0,54408.0,54420.0] || -> . % 76.04/76.24 54970[126:Spt:54969.0,54744.0,54745.0] || until2p7(s37)*+ -> . % 76.04/76.24 54971[126:Spt:54969.0,54744.1] || -> node4(s36)*. % 76.04/76.24 54972[126:MRR:54397.0,54971.0] || m_main_v_state(s36,c_ready)*+ -> . % 76.04/76.24 54975[126:Res:53.1,54972.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.24 54979[126:Res:54975.0,61.1] always3(s36) || -> . % 76.04/76.24 54980[126:SSi:54979.0,725.0,54388.0,54403.0,54743.0,54971.0] || -> . % 76.04/76.24 54981[125:Spt:54980.0,54742.0,54743.0] || until2p7(s36)*+ -> . % 76.04/76.24 54982[125:Spt:54980.0,54742.1] || -> node4(s35)*. % 76.04/76.24 54984[125:MRR:813.0,54982.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.24 54995[125:Res:53.1,54984.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.24 54997[125:MRR:54995.0,54371.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.24 54999[125:Res:54997.0,61.1] always3(s36) || -> . % 76.04/76.24 55000[125:SSi:54999.0,725.0,54388.0,54403.0] || -> . % 76.04/76.24 55001[124:Spt:55000.0,54740.0,54741.0] || until2p7(s35)*+ -> . % 76.04/76.24 55002[124:Spt:55000.0,54740.1] || -> node4(s34)*. % 76.04/76.24 55003[124:MRR:54374.0,55002.0] || m_main_v_state(s34,c_ready)*+ -> . % 76.04/76.24 55007[124:Res:53.1,55003.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.24 55010[124:Res:55007.0,61.1] always3(s34) || -> . % 76.04/76.24 55011[124:SSi:55010.0,723.0,54365.0,54377.0,54739.0,55002.0] || -> . % 76.04/76.24 55012[123:Spt:55011.0,54738.0,54739.0] || until2p7(s34)*+ -> . % 76.04/76.24 55013[123:Spt:55011.0,54738.1] || -> node4(s33)*. % 76.04/76.24 55015[123:MRR:819.0,55013.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.24 55026[123:Res:53.1,55015.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.24 55028[123:MRR:55026.0,54351.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.24 55030[123:Res:55028.0,61.1] always3(s34) || -> . % 76.04/76.24 55031[123:SSi:55030.0,723.0,54365.0,54377.0] || -> . % 76.04/76.24 55032[122:Spt:55031.0,54736.0,54737.0] || until2p7(s33)*+ -> . % 76.04/76.24 55033[122:Spt:55031.0,54736.1] || -> node4(s32)*. % 76.04/76.24 55034[122:MRR:54354.0,55033.0] || m_main_v_state(s32,c_ready)*+ -> . % 76.04/76.24 55037[122:Res:53.1,55034.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.24 55040[122:Res:55037.0,61.1] always3(s32) || -> . % 76.04/76.24 55041[122:SSi:55040.0,721.0,54345.0,54357.0,54735.0,55033.0] || -> . % 76.04/76.24 55042[121:Spt:55041.0,54734.0,54735.0] || until2p7(s32)*+ -> . % 76.04/76.24 55043[121:Spt:55041.0,54734.1] || -> node4(s31)*. % 76.04/76.24 55045[121:MRR:825.0,55043.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.24 55057[121:Res:53.1,55045.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.24 55059[121:MRR:55057.0,54331.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.24 55061[121:Res:55059.0,61.1] always3(s32) || -> . % 76.04/76.24 55062[121:SSi:55061.0,721.0,54345.0,54357.0] || -> . % 76.04/76.24 55063[120:Spt:55062.0,54732.0,54733.0] || until2p7(s31)*+ -> . % 76.04/76.24 55064[120:Spt:55062.0,54732.1] || -> node4(s30)*. % 76.04/76.24 55065[120:MRR:54334.0,55064.0] || m_main_v_state(s30,c_ready)*+ -> . % 76.04/76.24 55068[120:Res:53.1,55065.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.24 55071[120:Res:55068.0,61.1] always3(s30) || -> . % 76.04/76.24 55072[120:SSi:55071.0,719.0,54325.0,54340.0,54731.0,55064.0] || -> . % 76.04/76.24 55073[119:Spt:55072.0,54730.0,54731.0] || until2p7(s30)*+ -> . % 76.04/76.24 55074[119:Spt:55072.0,54730.1] || -> node4(s29)*. % 76.04/76.24 55076[119:MRR:831.0,55074.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.24 55088[119:Res:53.1,55076.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.24 55093[120:Spt:55088.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.24 55095[120:Res:55093.0,61.1] always3(s29) || -> . % 76.04/76.24 55096[120:SSi:55095.0,718.0,54319.0,54324.0,54729.0,55074.0] || -> . % 76.04/76.24 55097[120:Spt:55096.0,55088.0,55093.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.24 55098[120:Spt:55096.0,55088.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.24 55102[120:Res:55098.0,61.1] always3(s30) || -> . % 76.04/76.24 55103[120:SSi:55102.0,719.0,54325.0,54340.0] || -> . % 76.04/76.24 55104[118:Spt:55103.0,54728.0,54729.0] || until2p7(s29)*+ -> . % 76.04/76.24 55105[118:Spt:55103.0,54728.1] || -> node4(s28)*. % 76.04/76.24 55107[118:MRR:834.0,55105.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.24 55114[118:Res:53.1,55107.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.24 55116[119:Spt:55114.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.24 55118[119:Res:55116.0,61.1] always3(s28) || -> . % 76.04/76.24 55119[119:SSi:55118.0,717.0,54316.0,54318.0,54727.0,55105.0] || -> . % 76.04/76.24 55120[119:Spt:55119.0,55114.0,55116.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.24 55121[119:Spt:55119.0,55114.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.24 55125[119:Res:55121.0,61.1] always3(s29) || -> . % 76.04/76.24 55126[119:SSi:55125.0,718.0,54319.0,54324.0] || -> . % 76.04/76.24 55127[117:Spt:55126.0,54726.0,54727.0] || until2p7(s28)*+ -> . % 76.04/76.24 55128[117:Spt:55126.0,54726.1] || -> node4(s27)*. % 76.04/76.24 55130[117:MRR:837.0,55128.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.24 55133[117:Res:53.1,55130.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.24 55138[118:Spt:55133.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.24 55140[118:Res:55138.0,61.1] always3(s27) || -> . % 76.04/76.24 55141[118:SSi:55140.0,716.0,54310.0,54315.0,54725.0,55128.0] || -> . % 76.04/76.24 55142[118:Spt:55141.0,55133.0,55138.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.24 55143[118:Spt:55141.0,55133.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.24 55147[118:Res:55143.0,61.1] always3(s28) || -> . % 76.04/76.24 55148[118:SSi:55147.0,717.0,54316.0,54318.0] || -> . % 76.04/76.24 55149[116:Spt:55148.0,54724.0,54725.0] || until2p7(s27)*+ -> . % 76.04/76.24 55150[116:Spt:55148.0,54724.1] || -> node4(s26)*. % 76.04/76.24 55152[116:MRR:840.0,55150.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.24 55155[116:Res:53.1,55152.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.24 55157[117:Spt:55155.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.24 55159[117:Res:55157.0,61.1] always3(s26) || -> . % 76.04/76.24 55160[117:SSi:55159.0,715.0,54307.0,54309.0,54723.0,55150.0] || -> . % 76.04/76.24 55161[117:Spt:55160.0,55155.0,55157.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.24 55162[117:Spt:55160.0,55155.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.24 55166[117:Res:55162.0,61.1] always3(s27) || -> . % 76.04/76.24 55167[117:SSi:55166.0,716.0,54310.0,54315.0] || -> . % 76.04/76.24 55168[115:Spt:55167.0,54722.0,54723.0] || until2p7(s26)*+ -> . % 76.04/76.24 55169[115:Spt:55167.0,54722.1] || -> node4(s25)*. % 76.04/76.24 55171[115:MRR:843.0,55169.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.24 55174[115:Res:53.1,55171.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.24 55176[116:Spt:55174.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.24 55178[116:Res:55176.0,61.1] always3(s25) || -> . % 76.04/76.24 55179[116:SSi:55178.0,714.0,54301.0,54306.0,54721.0,55169.0] || -> . % 76.04/76.24 55180[116:Spt:55179.0,55174.0,55176.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.24 55181[116:Spt:55179.0,55174.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.24 55185[116:Res:55181.0,61.1] always3(s26) || -> . % 76.04/76.24 55186[116:SSi:55185.0,715.0,54307.0,54309.0] || -> . % 76.04/76.24 55187[114:Spt:55186.0,54720.0,54721.0] || until2p7(s25)*+ -> . % 76.04/76.24 55188[114:Spt:55186.0,54720.1] || -> node4(s24)*. % 76.04/76.24 55190[114:MRR:846.0,55188.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.24 55193[114:Res:53.1,55190.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.24 55195[115:Spt:55193.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.24 55197[115:Res:55195.0,61.1] always3(s24) || -> . % 76.04/76.24 55198[115:SSi:55197.0,713.0,54298.0,54300.0,54719.0,55188.0] || -> . % 76.04/76.24 55199[115:Spt:55198.0,55193.0,55195.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.24 55200[115:Spt:55198.0,55193.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.24 55204[115:Res:55200.0,61.1] always3(s25) || -> . % 76.04/76.24 55205[115:SSi:55204.0,714.0,54301.0,54306.0] || -> . % 76.04/76.24 55206[113:Spt:55205.0,54718.0,54719.0] || until2p7(s24)*+ -> . % 76.04/76.24 55207[113:Spt:55205.0,54718.1] || -> node4(s23)*. % 76.04/76.24 55209[113:MRR:849.0,55207.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.24 55212[113:Res:53.1,55209.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.24 55217[114:Spt:55212.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.24 55219[114:Res:55217.0,61.1] always3(s23) || -> . % 76.04/76.24 55220[114:SSi:55219.0,712.0,54292.0,54297.0,54717.0,55207.0] || -> . % 76.04/76.24 55221[114:Spt:55220.0,55212.0,55217.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.24 55222[114:Spt:55220.0,55212.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.24 55226[114:Res:55222.0,61.1] always3(s24) || -> . % 76.04/76.24 55227[114:SSi:55226.0,713.0,54298.0,54300.0] || -> . % 76.04/76.24 55228[112:Spt:55227.0,54716.0,54717.0] || until2p7(s23)*+ -> . % 76.04/76.24 55229[112:Spt:55227.0,54716.1] || -> node4(s22)*. % 76.04/76.24 55231[112:MRR:852.0,55229.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.24 55234[112:Res:53.1,55231.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.24 55236[113:Spt:55234.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.24 55238[113:Res:55236.0,61.1] always3(s22) || -> . % 76.04/76.24 55239[113:SSi:55238.0,711.0,54289.0,54291.0,54715.0,55229.0] || -> . % 76.04/76.24 55240[113:Spt:55239.0,55234.0,55236.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.24 55241[113:Spt:55239.0,55234.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.24 55245[113:Res:55241.0,61.1] always3(s23) || -> . % 76.04/76.24 55246[113:SSi:55245.0,712.0,54292.0,54297.0] || -> . % 76.04/76.24 55247[111:Spt:55246.0,54714.0,54715.0] || until2p7(s22)*+ -> . % 76.04/76.24 55248[111:Spt:55246.0,54714.1] || -> node4(s21)*. % 76.04/76.24 55250[111:MRR:855.0,55248.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.24 55253[111:Res:53.1,55250.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.24 55255[112:Spt:55253.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.24 55257[112:Res:55255.0,61.1] always3(s21) || -> . % 76.04/76.24 55258[112:SSi:55257.0,710.0,54283.0,54288.0,54713.0,55248.0] || -> . % 76.04/76.24 55259[112:Spt:55258.0,55253.0,55255.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.24 55260[112:Spt:55258.0,55253.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.24 55264[112:Res:55260.0,61.1] always3(s22) || -> . % 76.04/76.24 55265[112:SSi:55264.0,711.0,54289.0,54291.0] || -> . % 76.04/76.24 55266[110:Spt:55265.0,54712.0,54713.0] || until2p7(s21)*+ -> . % 76.04/76.24 55267[110:Spt:55265.0,54712.1] || -> node4(s20)*. % 76.04/76.24 55269[110:MRR:858.0,55267.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.24 55272[110:Res:53.1,55269.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.24 55274[111:Spt:55272.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.24 55276[111:Res:55274.0,61.1] always3(s20) || -> . % 76.04/76.24 55277[111:SSi:55276.0,709.0,54280.0,54282.0,54711.0,55267.0] || -> . % 76.04/76.24 55278[111:Spt:55277.0,55272.0,55274.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.24 55279[111:Spt:55277.0,55272.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.24 55283[111:Res:55279.0,61.1] always3(s21) || -> . % 76.04/76.24 55284[111:SSi:55283.0,710.0,54283.0,54288.0] || -> . % 76.04/76.24 55285[109:Spt:55284.0,54710.0,54711.0] || until2p7(s20)*+ -> . % 76.04/76.24 55286[109:Spt:55284.0,54710.1] || -> node4(s19)*. % 76.04/76.24 55288[109:MRR:861.0,55286.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.24 55291[109:Res:53.1,55288.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.24 55296[110:Spt:55291.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.24 55298[110:Res:55296.0,61.1] always3(s19) || -> . % 76.04/76.24 55299[110:SSi:55298.0,708.0,54274.0,54279.0,54709.0,55286.0] || -> . % 76.04/76.24 55300[110:Spt:55299.0,55291.0,55296.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.24 55301[110:Spt:55299.0,55291.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.24 55305[110:Res:55301.0,61.1] always3(s20) || -> . % 76.04/76.24 55306[110:SSi:55305.0,709.0,54280.0,54282.0] || -> . % 76.04/76.24 55307[108:Spt:55306.0,54708.0,54709.0] || until2p7(s19)*+ -> . % 76.04/76.24 55308[108:Spt:55306.0,54708.1] || -> node4(s18)*. % 76.04/76.24 55310[108:MRR:864.0,55308.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.24 55313[108:Res:53.1,55310.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.24 55315[109:Spt:55313.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.24 55317[109:Res:55315.0,61.1] always3(s18) || -> . % 76.04/76.24 55318[109:SSi:55317.0,707.0,54271.0,54273.0,54707.0,55308.0] || -> . % 76.04/76.24 55319[109:Spt:55318.0,55313.0,55315.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.24 55320[109:Spt:55318.0,55313.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.24 55324[109:Res:55320.0,61.1] always3(s19) || -> . % 76.04/76.24 55325[109:SSi:55324.0,708.0,54274.0,54279.0] || -> . % 76.04/76.24 55326[107:Spt:55325.0,54706.0,54707.0] || until2p7(s18)*+ -> . % 76.04/76.24 55327[107:Spt:55325.0,54706.1] || -> node4(s17)*. % 76.04/76.24 55329[107:MRR:867.0,55327.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.24 55332[107:Res:53.1,55329.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.24 55334[108:Spt:55332.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.24 55336[108:Res:55334.0,61.1] always3(s17) || -> . % 76.04/76.24 55337[108:SSi:55336.0,706.0,54265.0,54270.0,54705.0,55327.0] || -> . % 76.04/76.24 55338[108:Spt:55337.0,55332.0,55334.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.24 55339[108:Spt:55337.0,55332.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.24 55343[108:Res:55339.0,61.1] always3(s18) || -> . % 76.04/76.24 55344[108:SSi:55343.0,707.0,54271.0,54273.0] || -> . % 76.04/76.24 55345[106:Spt:55344.0,54704.0,54705.0] || until2p7(s17)*+ -> . % 76.04/76.24 55346[106:Spt:55344.0,54704.1] || -> node4(s16)*. % 76.04/76.24 55348[106:MRR:870.0,55346.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.24 55351[106:Res:53.1,55348.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.24 55353[107:Spt:55351.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.24 55355[107:Res:55353.0,61.1] always3(s16) || -> . % 76.04/76.24 55356[107:SSi:55355.0,705.0,54262.0,54264.0,54703.0,55346.0] || -> . % 76.04/76.24 55357[107:Spt:55356.0,55351.0,55353.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.24 55358[107:Spt:55356.0,55351.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.24 55362[107:Res:55358.0,61.1] always3(s17) || -> . % 76.04/76.24 55363[107:SSi:55362.0,706.0,54265.0,54270.0] || -> . % 76.04/76.24 55364[105:Spt:55363.0,54702.0,54703.0] || until2p7(s16)*+ -> . % 76.04/76.24 55365[105:Spt:55363.0,54702.1] || -> node4(s15)*. % 76.04/76.24 55367[105:MRR:873.0,55365.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.24 55370[105:Res:53.1,55367.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.24 55375[106:Spt:55370.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.24 55377[106:Res:55375.0,61.1] always3(s15) || -> . % 76.04/76.24 55378[106:SSi:55377.0,704.0,54256.0,54261.0,54701.0,55365.0] || -> . % 76.04/76.24 55379[106:Spt:55378.0,55370.0,55375.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.24 55380[106:Spt:55378.0,55370.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.24 55384[106:Res:55380.0,61.1] always3(s16) || -> . % 76.04/76.24 55385[106:SSi:55384.0,705.0,54262.0,54264.0] || -> . % 76.04/76.24 55386[104:Spt:55385.0,54700.0,54701.0] || until2p7(s15)*+ -> . % 76.04/76.24 55387[104:Spt:55385.0,54700.1] || -> node4(s14)*. % 76.04/76.24 55389[104:MRR:876.0,55387.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.24 55392[104:Res:53.1,55389.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.24 55394[105:Spt:55392.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.24 55396[105:Res:55394.0,61.1] always3(s14) || -> . % 76.04/76.24 55397[105:SSi:55396.0,703.0,54253.0,54255.0,54699.0,55387.0] || -> . % 76.04/76.24 55398[105:Spt:55397.0,55392.0,55394.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.24 55399[105:Spt:55397.0,55392.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.24 55403[105:Res:55399.0,61.1] always3(s15) || -> . % 76.04/76.24 55404[105:SSi:55403.0,704.0,54256.0,54261.0] || -> . % 76.04/76.24 55405[103:Spt:55404.0,54698.0,54699.0] || until2p7(s14)*+ -> . % 76.04/76.24 55406[103:Spt:55404.0,54698.1] || -> node4(s13)*. % 76.04/76.24 55408[103:MRR:879.0,55406.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.24 55411[103:Res:53.1,55408.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.24 55413[104:Spt:55411.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.24 55415[104:Res:55413.0,61.1] always3(s13) || -> . % 76.04/76.24 55416[104:SSi:55415.0,702.0,54247.0,54252.0,54697.0,55406.0] || -> . % 76.04/76.24 55417[104:Spt:55416.0,55411.0,55413.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.24 55418[104:Spt:55416.0,55411.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.24 55422[104:Res:55418.0,61.1] always3(s14) || -> . % 76.04/76.24 55423[104:SSi:55422.0,703.0,54253.0,54255.0] || -> . % 76.04/76.24 55424[102:Spt:55423.0,54696.0,54697.0] || until2p7(s13)*+ -> . % 76.04/76.24 55425[102:Spt:55423.0,54696.1] || -> node4(s12)*. % 76.04/76.24 55427[102:MRR:882.0,55425.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.24 55430[102:Res:53.1,55427.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.24 55432[103:Spt:55430.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.24 55434[103:Res:55432.0,61.1] always3(s12) || -> . % 76.04/76.24 55435[103:SSi:55434.0,701.0,54244.0,54246.0,54695.0,55425.0] || -> . % 76.04/76.24 55436[103:Spt:55435.0,55430.0,55432.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.24 55437[103:Spt:55435.0,55430.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.24 55441[103:Res:55437.0,61.1] always3(s13) || -> . % 76.04/76.24 55442[103:SSi:55441.0,702.0,54247.0,54252.0] || -> . % 76.04/76.24 55443[101:Spt:55442.0,54694.0,54695.0] || until2p7(s12)*+ -> . % 76.04/76.24 55444[101:Spt:55442.0,54694.1] || -> node4(s11)*. % 76.04/76.24 55446[101:MRR:885.0,55444.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.24 55449[101:Res:53.1,55446.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.24 55451[101:MRR:55449.0,54684.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.24 55456[101:Res:55451.0,61.1] always3(s12) || -> . % 76.04/76.24 55457[101:SSi:55456.0,701.0,54244.0,54246.0] || -> . % 76.04/76.24 55458[99:Spt:55457.0,54524.1,54529.0] || xuntil6(s48)* -> . % 76.04/76.24 55459[99:Spt:55457.0,54524.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.24 55462[99:Res:55459.0,61.1] always3(s48) || -> . % 76.04/76.24 55463[99:SSi:55462.0,737.0,54514.0] || -> . % 76.04/76.24 55464[97:Spt:55463.0,54505.2,54513.0] || xuntil6(s47)*+ -> . % 76.04/76.24 55465[97:Spt:55463.0,54505.0,54505.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.24 55466[97:Res:53.1,55465.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.24 55468[97:MRR:55466.0,54497.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.24 55470[97:Res:55468.0,61.1] always3(s48) || -> . % 76.04/76.24 55471[97:SSi:55470.0,737.0] || -> . % 76.04/76.24 55472[96:Spt:55471.0,54501.1,54503.0] || xuntil6(s46)* -> . % 76.04/76.24 55473[96:Spt:55471.0,54501.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.24 55476[96:Res:55473.0,61.1] always3(s46) || -> . % 76.04/76.24 55477[96:SSi:55476.0,735.0,54491.0] || -> . % 76.04/76.24 55478[94:Spt:55477.0,54485.2,54490.0] || xuntil6(s45)*+ -> . % 76.04/76.24 55479[94:Spt:55477.0,54485.0,54485.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.24 55480[94:Res:53.1,55479.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.24 55482[94:MRR:55480.0,54477.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.24 55485[94:Res:55482.0,61.1] always3(s46) || -> . % 76.04/76.24 55486[94:SSi:55485.0,735.0] || -> . % 76.04/76.24 55487[93:Spt:55486.0,54481.1,54483.0] || xuntil6(s44)* -> . % 76.04/76.24 55488[93:Spt:55486.0,54481.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.24 55491[93:Res:55488.0,61.1] always3(s44) || -> . % 76.04/76.24 55492[93:SSi:55491.0,733.0,54471.0] || -> . % 76.04/76.24 55493[91:Spt:55492.0,54468.2,54470.0] || xuntil6(s43)*+ -> . % 76.04/76.24 55494[91:Spt:55492.0,54468.0,54468.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.24 55495[91:Res:53.1,55494.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.24 55497[91:MRR:55495.0,54457.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.24 55499[91:Res:55497.0,61.1] always3(s44) || -> . % 76.04/76.24 55500[91:SSi:55499.0,733.0] || -> . % 76.04/76.24 55501[90:Spt:55500.0,54461.1,54466.0] || xuntil6(s42)* -> . % 76.04/76.24 55502[90:Spt:55500.0,54461.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.24 55505[90:Res:55502.0,61.1] always3(s42) || -> . % 76.04/76.24 55506[90:SSi:55505.0,731.0,54451.0] || -> . % 76.04/76.24 55507[88:Spt:55506.0,54442.2,54450.0] || xuntil6(s41)*+ -> . % 76.04/76.24 55508[88:Spt:55506.0,54442.0,54442.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.24 55509[88:Res:53.1,55508.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.24 55511[88:MRR:55509.0,54434.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.24 55514[88:Res:55511.0,61.1] always3(s42) || -> . % 76.04/76.24 55515[88:SSi:55514.0,731.0] || -> . % 76.04/76.24 55516[87:Spt:55515.0,54438.1,54440.0] || xuntil6(s40)* -> . % 76.04/76.24 55517[87:Spt:55515.0,54438.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.24 55520[87:Res:55517.0,61.1] always3(s40) || -> . % 76.04/76.24 55521[87:SSi:55520.0,729.0,54428.0] || -> . % 76.04/76.24 55522[85:Spt:55521.0,54422.2,54427.0] || xuntil6(s39)*+ -> . % 76.04/76.24 55523[85:Spt:55521.0,54422.0,54422.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.24 55524[85:Res:53.1,55523.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.24 55526[85:MRR:55524.0,54414.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.24 55528[85:Res:55526.0,61.1] always3(s40) || -> . % 76.04/76.24 55529[85:SSi:55528.0,729.0] || -> . % 76.04/76.24 55530[84:Spt:55529.0,54418.1,54420.0] || xuntil6(s38)* -> . % 76.04/76.24 55531[84:Spt:55529.0,54418.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.24 55534[84:Res:55531.0,61.1] always3(s38) || -> . % 76.04/76.24 55535[84:SSi:55534.0,727.0,54408.0] || -> . % 76.04/76.24 55536[82:Spt:55535.0,54405.2,54407.0] || xuntil6(s37)*+ -> . % 76.04/76.24 55537[82:Spt:55535.0,54405.0,54405.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.24 55538[82:Res:53.1,55537.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.24 55540[82:MRR:55538.0,54394.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.24 55542[82:Res:55540.0,61.1] always3(s38) || -> . % 76.04/76.24 55543[82:SSi:55542.0,727.0] || -> . % 76.04/76.24 55544[81:Spt:55543.0,54398.1,54403.0] || xuntil6(s36)* -> . % 76.04/76.24 55545[81:Spt:55543.0,54398.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.24 55548[81:Res:55545.0,61.1] always3(s36) || -> . % 76.04/76.24 55549[81:SSi:55548.0,725.0,54388.0] || -> . % 76.04/76.24 55550[79:Spt:55549.0,54379.2,54387.0] || xuntil6(s35)*+ -> . % 76.04/76.24 55551[79:Spt:55549.0,54379.0,54379.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.24 55552[79:Res:53.1,55551.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.24 55554[79:MRR:55552.0,54371.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.24 55556[79:Res:55554.0,61.1] always3(s36) || -> . % 76.04/76.24 55557[79:SSi:55556.0,725.0] || -> . % 76.04/76.24 55558[78:Spt:55557.0,54375.1,54377.0] || xuntil6(s34)* -> . % 76.04/76.24 55559[78:Spt:55557.0,54375.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.24 55562[78:Res:55559.0,61.1] always3(s34) || -> . % 76.04/76.24 55563[78:SSi:55562.0,723.0,54365.0] || -> . % 76.04/76.24 55564[76:Spt:55563.0,54359.2,54364.0] || xuntil6(s33)*+ -> . % 76.04/76.24 55565[76:Spt:55563.0,54359.0,54359.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.24 55566[76:Res:53.1,55565.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.24 55568[76:MRR:55566.0,54351.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.24 55570[76:Res:55568.0,61.1] always3(s34) || -> . % 76.04/76.24 55571[76:SSi:55570.0,723.0] || -> . % 76.04/76.24 55572[75:Spt:55571.0,54355.1,54357.0] || xuntil6(s32)* -> . % 76.04/76.24 55573[75:Spt:55571.0,54355.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.24 55576[75:Res:55573.0,61.1] always3(s32) || -> . % 76.04/76.24 55577[75:SSi:55576.0,721.0,54345.0] || -> . % 76.04/76.24 55578[73:Spt:55577.0,54342.2,54344.0] || xuntil6(s31)*+ -> . % 76.04/76.24 55579[73:Spt:55577.0,54342.0,54342.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.24 55580[73:Res:53.1,55579.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.24 55582[73:MRR:55580.0,54331.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.24 55584[73:Res:55582.0,61.1] always3(s32) || -> . % 76.04/76.24 55585[73:SSi:55584.0,721.0] || -> . % 76.04/76.24 55586[72:Spt:55585.0,54335.1,54340.0] || xuntil6(s30)* -> . % 76.04/76.24 55587[72:Spt:55585.0,54335.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.24 55590[72:Res:55587.0,61.1] always3(s30) || -> . % 76.04/76.24 55591[72:SSi:55590.0,719.0,54325.0] || -> . % 76.04/76.24 55592[70:Spt:55591.0,54320.2,54324.0] || xuntil6(s29)*+ -> . % 76.04/76.24 55593[70:Spt:55591.0,54320.0,54320.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.24 55594[70:Res:53.1,55593.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.24 55596[71:Spt:55594.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.24 55598[71:Res:55596.0,61.1] always3(s30) || -> . % 76.04/76.24 55599[71:SSi:55598.0,719.0] || -> . % 76.04/76.24 55600[71:Spt:55599.0,55594.1,55596.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.24 55601[71:Spt:55599.0,55594.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.24 55604[71:Res:55601.0,61.1] always3(s29) || -> . % 76.04/76.24 55605[71:SSi:55604.0,718.0,54319.0] || -> . % 76.04/76.24 55606[69:Spt:55605.0,54317.2,54318.0] || xuntil6(s28)*+ -> . % 76.04/76.24 55607[69:Spt:55605.0,54317.0,54317.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.24 55608[69:Res:53.1,55607.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.24 55610[70:Spt:55608.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.24 55612[70:Res:55610.0,61.1] always3(s29) || -> . % 76.04/76.24 55613[70:SSi:55612.0,718.0] || -> . % 76.04/76.24 55614[70:Spt:55613.0,55608.1,55610.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.24 55615[70:Spt:55613.0,55608.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.24 55618[70:Res:55615.0,61.1] always3(s28) || -> . % 76.04/76.24 55619[70:SSi:55618.0,717.0,54316.0] || -> . % 76.04/76.24 55620[68:Spt:55619.0,54311.2,54315.0] || xuntil6(s27)*+ -> . % 76.04/76.24 55621[68:Spt:55619.0,54311.0,54311.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.24 55622[68:Res:53.1,55621.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.24 55624[69:Spt:55622.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.24 55626[69:Res:55624.0,61.1] always3(s28) || -> . % 76.04/76.24 55627[69:SSi:55626.0,717.0] || -> . % 76.04/76.24 55628[69:Spt:55627.0,55622.1,55624.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.24 55629[69:Spt:55627.0,55622.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.24 55632[69:Res:55629.0,61.1] always3(s27) || -> . % 76.04/76.24 55633[69:SSi:55632.0,716.0,54310.0] || -> . % 76.04/76.24 55634[67:Spt:55633.0,54308.2,54309.0] || xuntil6(s26)*+ -> . % 76.04/76.24 55635[67:Spt:55633.0,54308.0,54308.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.24 55636[67:Res:53.1,55635.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.24 55638[68:Spt:55636.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.24 55640[68:Res:55638.0,61.1] always3(s27) || -> . % 76.04/76.24 55641[68:SSi:55640.0,716.0] || -> . % 76.04/76.24 55642[68:Spt:55641.0,55636.1,55638.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.24 55643[68:Spt:55641.0,55636.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.24 55646[68:Res:55643.0,61.1] always3(s26) || -> . % 76.04/76.24 55647[68:SSi:55646.0,715.0,54307.0] || -> . % 76.04/76.24 55648[66:Spt:55647.0,54302.2,54306.0] || xuntil6(s25)*+ -> . % 76.04/76.24 55649[66:Spt:55647.0,54302.0,54302.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.24 55650[66:Res:53.1,55649.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.24 55652[67:Spt:55650.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.24 55654[67:Res:55652.0,61.1] always3(s26) || -> . % 76.04/76.24 55655[67:SSi:55654.0,715.0] || -> . % 76.04/76.24 55656[67:Spt:55655.0,55650.1,55652.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.24 55657[67:Spt:55655.0,55650.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.24 55660[67:Res:55657.0,61.1] always3(s25) || -> . % 76.04/76.24 55661[67:SSi:55660.0,714.0,54301.0] || -> . % 76.04/76.24 55662[65:Spt:55661.0,54299.2,54300.0] || xuntil6(s24)*+ -> . % 76.04/76.24 55663[65:Spt:55661.0,54299.0,54299.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.24 55664[65:Res:53.1,55663.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.24 55666[66:Spt:55664.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.24 55668[66:Res:55666.0,61.1] always3(s25) || -> . % 76.04/76.24 55669[66:SSi:55668.0,714.0] || -> . % 76.04/76.24 55670[66:Spt:55669.0,55664.1,55666.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.24 55671[66:Spt:55669.0,55664.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.24 55674[66:Res:55671.0,61.1] always3(s24) || -> . % 76.04/76.24 55675[66:SSi:55674.0,713.0,54298.0] || -> . % 76.04/76.24 55676[64:Spt:55675.0,54293.2,54297.0] || xuntil6(s23)*+ -> . % 76.04/76.24 55677[64:Spt:55675.0,54293.0,54293.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.24 55678[64:Res:53.1,55677.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.24 55680[65:Spt:55678.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.24 55682[65:Res:55680.0,61.1] always3(s24) || -> . % 76.04/76.24 55683[65:SSi:55682.0,713.0] || -> . % 76.04/76.24 55684[65:Spt:55683.0,55678.1,55680.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.24 55685[65:Spt:55683.0,55678.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.24 55688[65:Res:55685.0,61.1] always3(s23) || -> . % 76.04/76.24 55689[65:SSi:55688.0,712.0,54292.0] || -> . % 76.04/76.24 55690[63:Spt:55689.0,54290.2,54291.0] || xuntil6(s22)*+ -> . % 76.04/76.24 55691[63:Spt:55689.0,54290.0,54290.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.24 55692[63:Res:53.1,55691.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.24 55694[64:Spt:55692.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.24 55696[64:Res:55694.0,61.1] always3(s23) || -> . % 76.04/76.24 55697[64:SSi:55696.0,712.0] || -> . % 76.04/76.24 55698[64:Spt:55697.0,55692.1,55694.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.24 55699[64:Spt:55697.0,55692.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.24 55702[64:Res:55699.0,61.1] always3(s22) || -> . % 76.04/76.24 55703[64:SSi:55702.0,711.0,54289.0] || -> . % 76.04/76.24 55704[62:Spt:55703.0,54284.2,54288.0] || xuntil6(s21)*+ -> . % 76.04/76.24 55705[62:Spt:55703.0,54284.0,54284.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.24 55706[62:Res:53.1,55705.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.24 55711[63:Spt:55706.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.24 55713[63:Res:55711.0,61.1] always3(s21) || -> . % 76.04/76.24 55714[63:SSi:55713.0,710.0,54283.0] || -> . % 76.04/76.24 55715[63:Spt:55714.0,55706.0,55711.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.24 55716[63:Spt:55714.0,55706.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.24 55720[63:Res:55716.0,61.1] always3(s22) || -> . % 76.04/76.24 55721[63:SSi:55720.0,711.0] || -> . % 76.04/76.24 55722[61:Spt:55721.0,54281.2,54282.0] || xuntil6(s20)*+ -> . % 76.04/76.24 55723[61:Spt:55721.0,54281.0,54281.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.24 55724[61:Res:53.1,55723.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.24 55726[62:Spt:55724.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.24 55728[62:Res:55726.0,61.1] always3(s21) || -> . % 76.04/76.24 55729[62:SSi:55728.0,710.0] || -> . % 76.04/76.24 55730[62:Spt:55729.0,55724.1,55726.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.24 55731[62:Spt:55729.0,55724.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.24 55734[62:Res:55731.0,61.1] always3(s20) || -> . % 76.04/76.24 55735[62:SSi:55734.0,709.0,54280.0] || -> . % 76.04/76.24 55736[60:Spt:55735.0,54275.2,54279.0] || xuntil6(s19)*+ -> . % 76.04/76.24 55737[60:Spt:55735.0,54275.0,54275.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.24 55738[60:Res:53.1,55737.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.24 55740[61:Spt:55738.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.24 55742[61:Res:55740.0,61.1] always3(s20) || -> . % 76.04/76.24 55743[61:SSi:55742.0,709.0] || -> . % 76.04/76.24 55744[61:Spt:55743.0,55738.1,55740.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.24 55745[61:Spt:55743.0,55738.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.24 55748[61:Res:55745.0,61.1] always3(s19) || -> . % 76.04/76.24 55749[61:SSi:55748.0,708.0,54274.0] || -> . % 76.04/76.24 55750[59:Spt:55749.0,54272.2,54273.0] || xuntil6(s18)*+ -> . % 76.04/76.24 55751[59:Spt:55749.0,54272.0,54272.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.24 55752[59:Res:53.1,55751.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.24 55757[60:Spt:55752.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.24 55759[60:Res:55757.0,61.1] always3(s18) || -> . % 76.04/76.24 55760[60:SSi:55759.0,707.0,54271.0] || -> . % 76.04/76.24 55761[60:Spt:55760.0,55752.0,55757.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.24 55762[60:Spt:55760.0,55752.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.24 55766[60:Res:55762.0,61.1] always3(s19) || -> . % 76.04/76.24 55767[60:SSi:55766.0,708.0] || -> . % 76.04/76.24 55768[58:Spt:55767.0,54266.2,54270.0] || xuntil6(s17)*+ -> . % 76.04/76.24 55769[58:Spt:55767.0,54266.0,54266.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.24 55770[58:Res:53.1,55769.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.24 55772[59:Spt:55770.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.24 55774[59:Res:55772.0,61.1] always3(s18) || -> . % 76.04/76.24 55775[59:SSi:55774.0,707.0] || -> . % 76.04/76.24 55776[59:Spt:55775.0,55770.1,55772.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.24 55777[59:Spt:55775.0,55770.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.24 55780[59:Res:55777.0,61.1] always3(s17) || -> . % 76.04/76.24 55781[59:SSi:55780.0,706.0,54265.0] || -> . % 76.04/76.24 55782[57:Spt:55781.0,54263.2,54264.0] || xuntil6(s16)*+ -> . % 76.04/76.24 55783[57:Spt:55781.0,54263.0,54263.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.24 55784[57:Res:53.1,55783.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.24 55786[58:Spt:55784.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.24 55788[58:Res:55786.0,61.1] always3(s17) || -> . % 76.04/76.24 55789[58:SSi:55788.0,706.0] || -> . % 76.04/76.24 55790[58:Spt:55789.0,55784.1,55786.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.24 55791[58:Spt:55789.0,55784.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.24 55794[58:Res:55791.0,61.1] always3(s16) || -> . % 76.04/76.24 55795[58:SSi:55794.0,705.0,54262.0] || -> . % 76.04/76.24 55796[56:Spt:55795.0,54257.2,54261.0] || xuntil6(s15)*+ -> . % 76.04/76.24 55797[56:Spt:55795.0,54257.0,54257.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.24 55798[56:Res:53.1,55797.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.24 55803[57:Spt:55798.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.24 55805[57:Res:55803.0,61.1] always3(s15) || -> . % 76.04/76.24 55806[57:SSi:55805.0,704.0,54256.0] || -> . % 76.04/76.24 55807[57:Spt:55806.0,55798.0,55803.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.24 55808[57:Spt:55806.0,55798.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.24 55812[57:Res:55808.0,61.1] always3(s16) || -> . % 76.04/76.24 55813[57:SSi:55812.0,705.0] || -> . % 76.04/76.24 55814[55:Spt:55813.0,54254.2,54255.0] || xuntil6(s14)*+ -> . % 76.04/76.24 55815[55:Spt:55813.0,54254.0,54254.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.24 55816[55:Res:53.1,55815.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.24 55818[56:Spt:55816.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.24 55820[56:Res:55818.0,61.1] always3(s15) || -> . % 76.04/76.24 55821[56:SSi:55820.0,704.0] || -> . % 76.04/76.24 55822[56:Spt:55821.0,55816.1,55818.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.24 55823[56:Spt:55821.0,55816.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.24 55826[56:Res:55823.0,61.1] always3(s14) || -> . % 76.04/76.24 55827[56:SSi:55826.0,703.0,54253.0] || -> . % 76.04/76.24 55828[54:Spt:55827.0,54248.2,54252.0] || xuntil6(s13)*+ -> . % 76.04/76.24 55829[54:Spt:55827.0,54248.0,54248.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.24 55830[54:Res:53.1,55829.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.24 55832[55:Spt:55830.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.24 55834[55:Res:55832.0,61.1] always3(s14) || -> . % 76.04/76.24 55835[55:SSi:55834.0,703.0] || -> . % 76.04/76.24 55836[55:Spt:55835.0,55830.1,55832.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.24 55837[55:Spt:55835.0,55830.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.24 55840[55:Res:55837.0,61.1] always3(s13) || -> . % 76.04/76.24 55841[55:SSi:55840.0,702.0,54247.0] || -> . % 76.04/76.24 55842[53:Spt:55841.0,54245.2,54246.0] || xuntil6(s12)*+ -> . % 76.04/76.24 55843[53:Spt:55841.0,54245.0,54245.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.24 55844[53:Res:53.1,55843.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.24 55849[54:Spt:55844.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.24 55851[54:Res:55849.0,61.1] always3(s12) || -> . % 76.04/76.24 55852[54:SSi:55851.0,701.0,54244.0] || -> . % 76.04/76.24 55853[54:Spt:55852.0,55844.0,55849.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.24 55854[54:Spt:55852.0,55844.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.24 55858[54:Res:55854.0,61.1] always3(s13) || -> . % 76.04/76.24 55859[54:SSi:55858.0,702.0] || -> . % 76.04/76.24 55860[52:Spt:55859.0,54239.2,54243.0] || xuntil6(s11)*+ -> . % 76.04/76.24 55861[52:Spt:55859.0,54239.0,54239.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.24 55862[52:Res:53.1,55861.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.24 55864[53:Spt:55862.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.24 55866[53:Res:55864.0,61.1] always3(s12) || -> . % 76.04/76.24 55867[53:SSi:55866.0,701.0] || -> . % 76.04/76.24 55868[53:Spt:55867.0,55862.1,55864.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.24 55869[53:Spt:55867.0,55862.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.24 55872[53:Res:55869.0,61.1] always3(s11) || -> . % 76.04/76.24 55873[53:SSi:55872.0,700.0,54238.0] || -> . % 76.04/76.24 55874[51:Spt:55873.0,54236.2,54237.0] || xuntil6(s10)*+ -> . % 76.04/76.24 55875[51:Spt:55873.0,54236.0,54236.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.24 55876[51:Res:53.1,55875.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.24 55878[52:Spt:55876.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.24 55880[52:Res:55878.0,61.1] always3(s10) || -> . % 76.04/76.24 55881[52:SSi:55880.0,699.0,54235.0] || -> . % 76.04/76.24 55882[52:Spt:55881.0,55876.0,55878.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.24 55883[52:Spt:55881.0,55876.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.24 55887[52:Res:55883.0,61.1] always3(s11) || -> . % 76.04/76.24 55888[52:SSi:55887.0,700.0] || -> . % 76.04/76.24 55889[50:Spt:55888.0,54230.2,54234.0] || xuntil6(s9)*+ -> . % 76.04/76.24 55890[50:Spt:55888.0,54230.0,54230.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.24 55891[50:Res:53.1,55890.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.24 55896[51:Spt:55891.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.24 55898[51:Res:55896.0,61.1] always3(s9) || -> . % 76.04/76.24 55899[51:SSi:55898.0,698.0,54229.0] || -> . % 76.04/76.24 55900[51:Spt:55899.0,55891.0,55896.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.24 55901[51:Spt:55899.0,55891.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.24 55905[51:Res:55901.0,61.1] always3(s10) || -> . % 76.04/76.24 55906[51:SSi:55905.0,699.0] || -> . % 76.04/76.24 55907[49:Spt:55906.0,54227.2,54228.0] || xuntil6(s8)*+ -> . % 76.04/76.24 55908[49:Spt:55906.0,54227.0,54227.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.24 55909[49:Res:53.1,55908.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.24 55911[50:Spt:55909.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.24 55913[50:Res:55911.0,61.1] always3(s8) || -> . % 76.04/76.24 55914[50:SSi:55913.0,697.0,54226.0] || -> . % 76.04/76.24 55915[50:Spt:55914.0,55909.0,55911.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.24 55916[50:Spt:55914.0,55909.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.24 55920[50:Res:55916.0,61.1] always3(s9) || -> . % 76.04/76.24 55921[50:SSi:55920.0,698.0] || -> . % 76.04/76.24 55922[48:Spt:55921.0,54221.2,54225.0] || xuntil6(s7)*+ -> . % 76.04/76.24 55923[48:Spt:55921.0,54221.0,54221.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.24 55924[48:Res:53.1,55923.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.24 55926[49:Spt:55924.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.24 55928[49:Res:55926.0,61.1] always3(s7) || -> . % 76.04/76.24 55929[49:SSi:55928.0,696.0,54220.0] || -> . % 76.04/76.24 55930[49:Spt:55929.0,55924.0,55926.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.24 55931[49:Spt:55929.0,55924.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.24 55935[49:Res:55931.0,61.1] always3(s8) || -> . % 76.04/76.24 55936[49:SSi:55935.0,697.0] || -> . % 76.04/76.24 55937[47:Spt:55936.0,54218.2,54219.0] || xuntil6(s6)*+ -> . % 76.04/76.24 55938[47:Spt:55936.0,54218.0,54218.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.24 55939[47:Res:53.1,55938.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.24 55944[48:Spt:55939.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.24 55946[48:Res:55944.0,61.1] always3(s6) || -> . % 76.04/76.24 55947[48:SSi:55946.0,695.0,54217.0] || -> . % 76.04/76.24 55948[48:Spt:55947.0,55939.0,55944.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.24 55949[48:Spt:55947.0,55939.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.24 55953[48:Res:55949.0,61.1] always3(s7) || -> . % 76.04/76.24 55954[48:SSi:55953.0,696.0] || -> . % 76.04/76.24 55955[46:Spt:55954.0,54212.2,54216.0] || xuntil6(s5)*+ -> . % 76.04/76.24 55956[46:Spt:55954.0,54212.0,54212.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.24 55957[46:Res:53.1,55956.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.24 55959[47:Spt:55957.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.24 55961[47:Res:55959.0,61.1] always3(s5) || -> . % 76.04/76.24 55962[47:SSi:55961.0,694.0,54211.0] || -> . % 76.04/76.24 55963[47:Spt:55962.0,55957.0,55959.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.24 55964[47:Spt:55962.0,55957.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.24 55968[47:Res:55964.0,61.1] always3(s6) || -> . % 76.04/76.24 55969[47:SSi:55968.0,695.0] || -> . % 76.04/76.24 55970[45:Spt:55969.0,54209.2,54210.0] || xuntil6(s4)*+ -> . % 76.04/76.24 55971[45:Spt:55969.0,54209.0,54209.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.24 55972[45:Res:53.1,55971.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.24 55974[46:Spt:55972.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.24 55976[46:Res:55974.0,61.1] always3(s4) || -> . % 76.04/76.24 55977[46:SSi:55976.0,693.0,54208.0] || -> . % 76.04/76.24 55978[46:Spt:55977.0,55972.0,55974.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.24 55979[46:Spt:55977.0,55972.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.24 55983[46:Res:55979.0,61.1] always3(s5) || -> . % 76.04/76.24 55984[46:SSi:55983.0,694.0] || -> . % 76.04/76.24 55985[44:Spt:55984.0,54203.2,54207.0] || xuntil6(s3)*+ -> . % 76.04/76.24 55986[44:Spt:55984.0,54203.0,54203.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.24 55987[44:Res:53.1,55986.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.24 55992[45:Spt:55987.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.24 55994[45:Res:55992.0,61.1] always3(s3) || -> . % 76.04/76.24 55995[45:SSi:55994.0,692.0,54202.0] || -> . % 76.04/76.24 55996[45:Spt:55995.0,55987.0,55992.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.24 55997[45:Spt:55995.0,55987.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.24 56001[45:Res:55997.0,61.1] always3(s4) || -> . % 76.04/76.24 56002[45:SSi:56001.0,693.0] || -> . % 76.04/76.24 56003[43:Spt:56002.0,54200.2,54201.0] || xuntil6(s2)*+ -> . % 76.04/76.24 56004[43:Spt:56002.0,54200.0,54200.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.24 56005[43:Res:53.1,56004.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.24 56007[44:Spt:56005.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.24 56009[44:Res:56007.0,61.1] always3(s2) || -> . % 76.04/76.24 56010[44:SSi:56009.0,691.0,54199.0] || -> . % 76.04/76.24 56011[44:Spt:56010.0,56005.0,56007.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.24 56012[44:Spt:56010.0,56005.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.24 56016[44:Res:56012.0,61.1] always3(s3) || -> . % 76.04/76.24 56017[44:SSi:56016.0,692.0] || -> . % 76.04/76.24 56018[42:Spt:56017.0,54191.2,54198.0] || xuntil6(s1)*+ -> . % 76.04/76.24 56019[42:Spt:56017.0,54191.0,54191.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.24 56020[42:Res:53.1,56019.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.24 56022[43:Spt:56020.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.24 56024[43:Res:56022.0,61.1] always3(s1) || -> . % 76.04/76.24 56025[43:SSi:56024.0,690.0,54190.0] || -> . % 76.04/76.24 56026[43:Spt:56025.0,56020.0,56022.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.24 56027[43:Spt:56025.0,56020.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.24 56032[43:Res:56027.0,61.1] always3(s2) || -> . % 76.04/76.24 56033[43:SSi:56032.0,691.0] || -> . % 76.04/76.24 56034[41:Spt:56033.0,74.0,54189.0] || xuntil6(s0)*+ -> . % 76.04/76.24 56035[41:Spt:56033.0,74.1] || -> node4(s0)*. % 76.04/76.24 56036[41:MRR:758.1,56034.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.24 56038[41:Res:56036.0,61.1] always3(s1) || -> . % 76.04/76.24 56039[41:SSi:56038.0,690.0] || -> . % 76.04/76.24 56040[40:Spt:56039.0,54179.0,54183.0] || trans(s49,s11)*+ -> . % 76.04/76.24 56041[40:Spt:56039.0,54179.1,54179.2,54179.3,54179.4,54179.5,54179.6,54179.7,54179.8,54179.9,54179.10,54179.11] || -> trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.24 56042[40:MRR:54181.0,56040.0] || -> trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.24 56044[40:MRR:54182.1,56040.0] xuntil6(s49) || -> trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.24 56045[41:Spt:56041.0] || -> trans(s49,s10)*. % 76.04/76.24 56046[41:Res:56045.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s10)*. % 76.04/76.24 56048[41:Res:56045.0,60.0] || -> node2(s49,s10)*. % 76.04/76.24 56049[41:SSi:56046.1,50.0,738.0] xuntil6(s49) || -> until2p7(s10)*. % 76.04/76.24 56050[41:Res:56048.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)*. % 76.04/76.24 56051[42:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.24 56052[42:MRR:176.0,56051.0] || -> until5(s1)*. % 76.04/76.24 56053[42:MRR:54638.0,56052.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.24 56057[43:Spt:56053.2] || -> xuntil6(s1)*. % 76.04/76.24 56058[43:MRR:175.0,56057.0] || -> until5(s2)*. % 76.04/76.24 56059[43:MRR:54634.0,56058.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.24 56063[44:Spt:56059.2] || -> xuntil6(s2)*. % 76.04/76.24 56064[44:MRR:174.0,56063.0] || -> until5(s3)*. % 76.04/76.24 56065[44:MRR:54630.0,56064.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.24 56066[45:Spt:56065.2] || -> xuntil6(s3)*. % 76.04/76.24 56067[45:MRR:173.0,56066.0] || -> until5(s4)*. % 76.04/76.24 56068[45:MRR:54626.0,56067.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.24 56072[46:Spt:56068.2] || -> xuntil6(s4)*. % 76.04/76.24 56073[46:MRR:172.0,56072.0] || -> until5(s5)*. % 76.04/76.24 56074[46:MRR:54625.0,56073.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.24 56075[47:Spt:56074.2] || -> xuntil6(s5)*. % 76.04/76.24 56076[47:MRR:171.0,56075.0] || -> until5(s6)*. % 76.04/76.24 56077[47:MRR:54618.0,56076.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.24 56081[48:Spt:56077.2] || -> xuntil6(s6)*. % 76.04/76.24 56082[48:MRR:170.0,56081.0] || -> until5(s7)*. % 76.04/76.24 56083[48:MRR:54614.0,56082.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.24 56084[49:Spt:56083.2] || -> xuntil6(s7)*. % 76.04/76.24 56085[49:MRR:169.0,56084.0] || -> until5(s8)*. % 76.04/76.24 56086[49:MRR:54610.0,56085.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.24 56090[50:Spt:56086.2] || -> xuntil6(s8)*. % 76.04/76.24 56091[50:MRR:168.0,56090.0] || -> until5(s9)*. % 76.04/76.24 56092[50:MRR:54606.0,56091.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.24 56093[51:Spt:56092.2] || -> xuntil6(s9)*. % 76.04/76.24 56094[51:MRR:167.0,56093.0] || -> until5(s10)*. % 76.04/76.24 56095[51:MRR:54605.0,56094.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.24 56099[52:Spt:56095.2] || -> xuntil6(s10)*. % 76.04/76.24 56100[52:MRR:166.0,56099.0] || -> until5(s11)*. % 76.04/76.24 56101[52:MRR:54598.0,56100.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.24 56102[53:Spt:56101.2] || -> xuntil6(s11)*. % 76.04/76.24 56103[53:MRR:165.0,56102.0] || -> until5(s12)*. % 76.04/76.24 56104[53:MRR:54594.0,56103.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.24 56108[54:Spt:56104.2] || -> xuntil6(s12)*. % 76.04/76.24 56109[54:MRR:164.0,56108.0] || -> until5(s13)*. % 76.04/76.24 56110[54:MRR:54587.0,56109.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.24 56111[55:Spt:56110.2] || -> xuntil6(s13)*. % 76.04/76.24 56112[55:MRR:163.0,56111.0] || -> until5(s14)*. % 76.04/76.24 56113[55:MRR:54583.0,56112.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.24 56117[56:Spt:56113.2] || -> xuntil6(s14)*. % 76.04/76.24 56118[56:MRR:162.0,56117.0] || -> until5(s15)*. % 76.04/76.24 56119[56:MRR:54579.0,56118.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.24 56120[57:Spt:56119.2] || -> xuntil6(s15)*. % 76.04/76.24 56121[57:MRR:161.0,56120.0] || -> until5(s16)*. % 76.04/76.24 56122[57:MRR:54578.0,56121.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.24 56126[58:Spt:56122.2] || -> xuntil6(s16)*. % 76.04/76.24 56127[58:MRR:160.0,56126.0] || -> until5(s17)*. % 76.04/76.24 56128[58:MRR:54574.0,56127.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.24 56129[59:Spt:56128.2] || -> xuntil6(s17)*. % 76.04/76.24 56130[59:MRR:159.0,56129.0] || -> until5(s18)*. % 76.04/76.24 56131[59:MRR:54567.0,56130.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.24 56135[60:Spt:56131.2] || -> xuntil6(s18)*. % 76.04/76.24 56136[60:MRR:158.0,56135.0] || -> until5(s19)*. % 76.04/76.25 56137[60:MRR:54566.0,56136.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.25 56138[61:Spt:56137.2] || -> xuntil6(s19)*. % 76.04/76.25 56139[61:MRR:157.0,56138.0] || -> until5(s20)*. % 76.04/76.25 56140[61:MRR:54559.0,56139.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.25 56144[62:Spt:56140.2] || -> xuntil6(s20)*. % 76.04/76.25 56145[62:MRR:156.0,56144.0] || -> until5(s21)*. % 76.04/76.25 56146[62:MRR:54555.0,56145.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.25 56147[63:Spt:56146.2] || -> xuntil6(s21)*. % 76.04/76.25 56148[63:MRR:155.0,56147.0] || -> until5(s22)*. % 76.04/76.25 56149[63:MRR:54554.0,56148.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.25 56153[64:Spt:56149.2] || -> xuntil6(s22)*. % 76.04/76.25 56154[64:MRR:154.0,56153.0] || -> until5(s23)*. % 76.04/76.25 56155[64:MRR:54547.0,56154.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.25 56156[65:Spt:56155.2] || -> xuntil6(s23)*. % 76.04/76.25 56157[65:MRR:153.0,56156.0] || -> until5(s24)*. % 76.04/76.25 56158[65:MRR:54543.0,56157.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.25 56162[66:Spt:56158.2] || -> xuntil6(s24)*. % 76.04/76.25 56163[66:MRR:152.0,56162.0] || -> until5(s25)*. % 76.04/76.25 56164[66:MRR:54539.0,56163.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.25 56165[67:Spt:56164.2] || -> xuntil6(s25)*. % 76.04/76.25 56166[67:MRR:151.0,56165.0] || -> until5(s26)*. % 76.04/76.25 56167[67:MRR:54538.0,56166.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.25 56171[68:Spt:56167.2] || -> xuntil6(s26)*. % 76.04/76.25 56172[68:MRR:150.0,56171.0] || -> until5(s27)*. % 76.04/76.25 56173[68:MRR:54537.0,56172.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.25 56174[69:Spt:56173.2] || -> xuntil6(s27)*. % 76.04/76.25 56175[69:MRR:149.0,56174.0] || -> until5(s28)*. % 76.04/76.25 56176[69:MRR:54536.0,56175.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.25 56180[70:Spt:56176.2] || -> xuntil6(s28)*. % 76.04/76.25 56181[70:MRR:148.0,56180.0] || -> until5(s29)*. % 76.04/76.25 56182[70:MRR:54532.0,56181.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.25 56183[71:Spt:56182.2] || -> xuntil6(s29)*. % 76.04/76.25 56184[71:MRR:147.0,56183.0] || -> until5(s30)*. % 76.04/76.25 56185[71:MRR:52671.0,56184.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.25 56189[72:Spt:56185.2] || -> xuntil6(s30)*. % 76.04/76.25 56190[72:MRR:146.0,56189.0] || -> until5(s31)*. % 76.04/76.25 56191[72:MRR:54645.0,56190.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.25 56192[73:Spt:56191.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.25 56194[73:Res:56192.0,61.1] always3(s32) || -> . % 76.04/76.25 56195[73:SSi:56194.0,721.0] || -> . % 76.04/76.25 56196[73:Spt:56195.0,56191.1,56192.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.04/76.25 56197[73:Spt:56195.0,56191.0,56191.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.04/76.25 56199[73:MRR:825.2,56196.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.04/76.25 56200[73:Res:53.1,56197.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.04/76.25 56205[74:Spt:56200.1] || -> xuntil6(s31)*. % 76.04/76.25 56206[74:MRR:145.0,56205.0] || -> until5(s32)*. % 76.04/76.25 56207[74:MRR:52791.0,56206.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.25 56209[75:Spt:56207.2] || -> xuntil6(s32)*. % 76.04/76.25 56210[75:MRR:144.0,56209.0] || -> until5(s33)*. % 76.04/76.25 56211[75:MRR:54646.0,56210.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.25 56212[76:Spt:56211.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.25 56214[76:Res:56212.0,61.1] always3(s34) || -> . % 76.04/76.25 56215[76:SSi:56214.0,723.0] || -> . % 76.04/76.25 56216[76:Spt:56215.0,56211.1,56212.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.25 56217[76:Spt:56215.0,56211.0,56211.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.25 56219[76:MRR:819.2,56216.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.25 56220[76:Res:53.1,56217.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.25 56222[77:Spt:56220.1] || -> xuntil6(s33)*. % 76.04/76.25 56223[77:MRR:143.0,56222.0] || -> until5(s34)*. % 76.04/76.25 56224[77:MRR:52792.0,56223.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.25 56229[78:Spt:56224.2] || -> xuntil6(s34)*. % 76.04/76.25 56230[78:MRR:142.0,56229.0] || -> until5(s35)*. % 76.04/76.25 56231[78:MRR:54650.0,56230.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.25 56232[79:Spt:56231.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.25 56234[79:Res:56232.0,61.1] always3(s36) || -> . % 76.04/76.25 56235[79:SSi:56234.0,725.0] || -> . % 76.04/76.25 56236[79:Spt:56235.0,56231.1,56232.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.25 56237[79:Spt:56235.0,56231.0,56231.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.25 56239[79:MRR:813.2,56236.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.25 56240[79:Res:53.1,56237.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.25 56242[80:Spt:56240.1] || -> xuntil6(s35)*. % 76.04/76.25 56243[80:MRR:141.0,56242.0] || -> until5(s36)*. % 76.04/76.25 56244[80:MRR:52796.0,56243.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.25 56252[81:Spt:56244.2] || -> xuntil6(s36)*. % 76.04/76.25 56253[81:MRR:140.0,56252.0] || -> until5(s37)*. % 76.04/76.25 56254[81:MRR:54654.0,56253.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.25 56255[82:Spt:56254.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.25 56257[82:Res:56255.0,61.1] always3(s38) || -> . % 76.04/76.25 56258[82:SSi:56257.0,727.0] || -> . % 76.04/76.25 56259[82:Spt:56258.0,56254.1,56255.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.25 56260[82:Spt:56258.0,56254.0,56254.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.25 56262[82:MRR:807.2,56259.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.25 56263[82:Res:53.1,56260.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.25 56268[83:Spt:56263.1] || -> xuntil6(s37)*. % 76.04/76.25 56269[83:MRR:139.0,56268.0] || -> until5(s38)*. % 76.04/76.25 56270[83:MRR:52800.0,56269.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.25 56272[84:Spt:56270.2] || -> xuntil6(s38)*. % 76.04/76.25 56273[84:MRR:138.0,56272.0] || -> until5(s39)*. % 76.04/76.25 56274[84:MRR:54658.0,56273.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.25 56275[85:Spt:56274.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.25 56277[85:Res:56275.0,61.1] always3(s40) || -> . % 76.04/76.25 56278[85:SSi:56277.0,729.0] || -> . % 76.04/76.25 56279[85:Spt:56278.0,56274.1,56275.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.25 56280[85:Spt:56278.0,56274.0,56274.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.25 56282[85:MRR:801.2,56279.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.25 56283[85:Res:53.1,56280.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.25 56285[86:Spt:56283.1] || -> xuntil6(s39)*. % 76.04/76.25 56286[86:MRR:137.0,56285.0] || -> until5(s40)*. % 76.04/76.25 56287[86:MRR:52804.0,56286.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.25 56292[87:Spt:56287.2] || -> xuntil6(s40)*. % 76.04/76.25 56293[87:MRR:136.0,56292.0] || -> until5(s41)*. % 76.04/76.25 56294[87:MRR:54665.0,56293.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.25 56295[88:Spt:56294.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.25 56297[88:Res:56295.0,61.1] always3(s42) || -> . % 76.04/76.25 56298[88:SSi:56297.0,731.0] || -> . % 76.04/76.25 56299[88:Spt:56298.0,56294.1,56295.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.25 56300[88:Spt:56298.0,56294.0,56294.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.25 56302[88:MRR:795.2,56299.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.25 56303[88:Res:53.1,56300.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.25 56305[89:Spt:56303.1] || -> xuntil6(s41)*. % 76.04/76.25 56306[89:MRR:135.0,56305.0] || -> until5(s42)*. % 76.04/76.25 56307[89:MRR:52811.0,56306.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.25 56315[90:Spt:56307.2] || -> xuntil6(s42)*. % 76.04/76.25 56316[90:MRR:134.0,56315.0] || -> until5(s43)*. % 76.04/76.25 56317[90:MRR:54666.0,56316.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.25 56318[91:Spt:56317.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.25 56320[91:Res:56318.0,61.1] always3(s44) || -> . % 76.04/76.25 56321[91:SSi:56320.0,733.0] || -> . % 76.04/76.25 56322[91:Spt:56321.0,56317.1,56318.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.25 56323[91:Spt:56321.0,56317.0,56317.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.25 56325[91:MRR:789.2,56322.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.25 56326[91:Res:53.1,56323.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.25 56331[92:Spt:56326.1] || -> xuntil6(s43)*. % 76.04/76.25 56332[92:MRR:133.0,56331.0] || -> until5(s44)*. % 76.04/76.25 56333[92:MRR:52812.0,56332.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.25 56335[93:Spt:56333.2] || -> xuntil6(s44)*. % 76.04/76.25 56336[93:MRR:132.0,56335.0] || -> until5(s45)*. % 76.04/76.25 56337[93:MRR:54670.0,56336.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.25 56338[94:Spt:56337.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.25 56340[94:Res:56338.0,61.1] always3(s46) || -> . % 76.04/76.25 56341[94:SSi:56340.0,735.0] || -> . % 76.04/76.25 56342[94:Spt:56341.0,56337.1,56338.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.25 56343[94:Spt:56341.0,56337.0,56337.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.25 56345[94:MRR:783.2,56342.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.25 56346[94:Res:53.1,56343.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.25 56348[95:Spt:56346.1] || -> xuntil6(s45)*. % 76.04/76.25 56349[95:MRR:131.0,56348.0] || -> until5(s46)*. % 76.04/76.25 56350[95:MRR:52816.0,56349.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.25 56355[96:Spt:56350.2] || -> xuntil6(s46)*. % 76.04/76.25 56356[96:MRR:130.0,56355.0] || -> until5(s47)*. % 76.04/76.25 56357[96:MRR:54674.0,56356.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.25 56358[97:Spt:56357.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.25 56360[97:Res:56358.0,61.1] always3(s48) || -> . % 76.04/76.25 56361[97:SSi:56360.0,737.0] || -> . % 76.04/76.25 56362[97:Spt:56361.0,56357.1,56358.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.25 56363[97:Spt:56361.0,56357.0,56357.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.25 56365[97:MRR:777.2,56362.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.25 56366[97:Res:53.1,56363.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.25 56368[98:Spt:56366.1] || -> xuntil6(s47)*. % 76.04/76.25 56369[98:MRR:129.0,56368.0] || -> until5(s48)*. % 76.04/76.25 56370[98:MRR:52820.0,56369.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.25 56378[99:Spt:56370.2] || -> xuntil6(s48)*. % 76.04/76.25 56379[99:MRR:128.0,56378.0] || -> until5(s49)*. % 76.04/76.25 56380[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.25 56381[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.25 56385[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.25 56386[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.25 56387[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.25 56394[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.25 56395[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.25 56399[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.25 56403[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.25 56407[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.25 56414[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.25 56415[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.25 56419[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.25 56426[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.25 56427[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.25 56434[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.25 56438[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.25 56439[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.25 56443[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.25 56450[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.25 56454[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.25 56458[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.25 56465[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.25 56466[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.25 56470[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.25 56474[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.25 56478[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.25 56485[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.25 56486[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.25 56490[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.25 56495[41:SoR:56050.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)*. % 76.04/76.25 56497[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.25 56501[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.25 56505[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.25 56509[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.25 56516[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.25 56517[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.25 56521[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.25 56525[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.25 56529[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.25 56530[41:SoR:56495.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)* xuntil6(s49). % 76.04/76.25 56531[99:SSi:56530.0,50.0,738.0,56379.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s10,c_busy)* xuntil6(s49). % 76.04/76.25 56532[100:Spt:56531.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.25 56534[100:Res:56532.0,61.1] always3(s10) || -> . % 76.04/76.25 56535[100:SSi:56534.0,699.0,56094.0,56099.0] || -> . % 76.04/76.25 56536[100:Spt:56535.0,56531.1,56532.0] || m_main_v_state(s10,c_busy)*+ -> . % 76.04/76.25 56537[100:Spt:56535.0,56531.0,56531.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.25 56541[100:MRR:56495.2,56536.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.25 56542[100:Res:53.1,56537.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.25 56544[101:Spt:56542.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.25 56546[101:Res:56544.0,61.1] always3(s49) || -> . % 76.04/76.25 56547[101:SSi:56546.0,50.0,738.0,56379.0] || -> . % 76.04/76.25 56548[101:Spt:56547.0,56542.0,56544.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.25 56549[101:Spt:56547.0,56542.1] || -> xuntil6(s49)*. % 76.04/76.25 56550[101:MRR:56049.0,56549.0] || -> until2p7(s10)*. % 76.04/76.25 56551[101:MRR:206.0,56550.0] || -> until2p7(s11)* node4(s10). % 76.04/76.25 56553[101:MRR:774.2,56548.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.25 56554[102:Spt:56551.0] || -> until2p7(s11)*. % 76.04/76.25 56555[102:MRR:207.0,56554.0] || -> until2p7(s12)* node4(s11). % 76.04/76.25 56556[103:Spt:56555.0] || -> until2p7(s12)*. % 76.04/76.25 56557[103:MRR:208.0,56556.0] || -> until2p7(s13)* node4(s12). % 76.04/76.25 56558[104:Spt:56557.0] || -> until2p7(s13)*. % 76.04/76.25 56559[104:MRR:209.0,56558.0] || -> until2p7(s14)* node4(s13). % 76.04/76.25 56560[105:Spt:56559.0] || -> until2p7(s14)*. % 76.04/76.25 56561[105:MRR:210.0,56560.0] || -> until2p7(s15)* node4(s14). % 76.04/76.25 56562[106:Spt:56561.0] || -> until2p7(s15)*. % 76.04/76.25 56563[106:MRR:211.0,56562.0] || -> until2p7(s16)* node4(s15). % 76.04/76.25 56564[107:Spt:56563.0] || -> until2p7(s16)*. % 76.04/76.25 56565[107:MRR:212.0,56564.0] || -> until2p7(s17)* node4(s16). % 76.04/76.25 56566[108:Spt:56565.0] || -> until2p7(s17)*. % 76.04/76.25 56567[108:MRR:213.0,56566.0] || -> until2p7(s18)* node4(s17). % 76.04/76.25 56568[109:Spt:56567.0] || -> until2p7(s18)*. % 76.04/76.25 56569[109:MRR:214.0,56568.0] || -> until2p7(s19)* node4(s18). % 76.04/76.25 56570[110:Spt:56569.0] || -> until2p7(s19)*. % 76.04/76.25 56571[110:MRR:215.0,56570.0] || -> until2p7(s20)* node4(s19). % 76.04/76.25 56572[111:Spt:56571.0] || -> until2p7(s20)*. % 76.04/76.25 56573[111:MRR:216.0,56572.0] || -> until2p7(s21)* node4(s20). % 76.04/76.25 56574[112:Spt:56573.0] || -> until2p7(s21)*. % 76.04/76.25 56575[112:MRR:217.0,56574.0] || -> until2p7(s22)* node4(s21). % 76.04/76.25 56576[113:Spt:56575.0] || -> until2p7(s22)*. % 76.04/76.25 56577[113:MRR:218.0,56576.0] || -> until2p7(s23)* node4(s22). % 76.04/76.25 56578[114:Spt:56577.0] || -> until2p7(s23)*. % 76.04/76.25 56579[114:MRR:219.0,56578.0] || -> until2p7(s24)* node4(s23). % 76.04/76.25 56580[115:Spt:56579.0] || -> until2p7(s24)*. % 76.04/76.25 56581[115:MRR:220.0,56580.0] || -> until2p7(s25)* node4(s24). % 76.04/76.25 56582[116:Spt:56581.0] || -> until2p7(s25)*. % 76.04/76.25 56583[116:MRR:221.0,56582.0] || -> until2p7(s26)* node4(s25). % 76.04/76.25 56584[117:Spt:56583.0] || -> until2p7(s26)*. % 76.04/76.25 56585[117:MRR:222.0,56584.0] || -> until2p7(s27)* node4(s26). % 76.04/76.25 56586[118:Spt:56585.0] || -> until2p7(s27)*. % 76.04/76.25 56587[118:MRR:223.0,56586.0] || -> until2p7(s28)* node4(s27). % 76.04/76.25 56588[119:Spt:56587.0] || -> until2p7(s28)*. % 76.04/76.25 56589[119:MRR:224.0,56588.0] || -> until2p7(s29)* node4(s28). % 76.04/76.25 56590[120:Spt:56589.0] || -> until2p7(s29)*. % 76.04/76.25 56591[120:MRR:225.0,56590.0] || -> until2p7(s30)* node4(s29). % 76.04/76.25 56592[121:Spt:56591.0] || -> until2p7(s30)*. % 76.04/76.25 56593[121:MRR:226.0,56592.0] || -> until2p7(s31)* node4(s30). % 76.04/76.25 56594[122:Spt:56593.0] || -> until2p7(s31)*. % 76.04/76.25 56595[122:MRR:227.0,56594.0] || -> until2p7(s32)* node4(s31). % 76.04/76.25 56596[123:Spt:56595.0] || -> until2p7(s32)*. % 76.04/76.25 56597[123:MRR:228.0,56596.0] || -> until2p7(s33)* node4(s32). % 76.04/76.25 56598[124:Spt:56597.0] || -> until2p7(s33)*. % 76.04/76.25 56599[124:MRR:229.0,56598.0] || -> until2p7(s34)* node4(s33). % 76.04/76.25 56600[125:Spt:56599.0] || -> until2p7(s34)*. % 76.04/76.25 56601[125:MRR:230.0,56600.0] || -> until2p7(s35)* node4(s34). % 76.04/76.25 56602[126:Spt:56601.0] || -> until2p7(s35)*. % 76.04/76.25 56603[126:MRR:231.0,56602.0] || -> until2p7(s36)* node4(s35). % 76.04/76.25 56604[127:Spt:56603.0] || -> until2p7(s36)*. % 76.04/76.25 56605[127:MRR:232.0,56604.0] || -> until2p7(s37)* node4(s36). % 76.04/76.25 56606[128:Spt:56605.0] || -> until2p7(s37)*. % 76.04/76.25 56607[128:MRR:235.0,56606.0] || -> until2p7(s38)* node4(s37). % 76.04/76.25 56608[129:Spt:56607.0] || -> until2p7(s38)*. % 76.04/76.25 56609[129:MRR:236.0,56608.0] || -> until2p7(s39)* node4(s38). % 76.04/76.25 56610[130:Spt:56609.0] || -> until2p7(s39)*. % 76.04/76.25 56611[130:MRR:237.0,56610.0] || -> until2p7(s40)* node4(s39). % 76.04/76.25 56612[131:Spt:56611.0] || -> until2p7(s40)*. % 76.04/76.25 56613[131:MRR:238.0,56612.0] || -> until2p7(s41)* node4(s40). % 76.04/76.25 56614[132:Spt:56613.0] || -> until2p7(s41)*. % 76.04/76.25 56615[132:MRR:239.0,56614.0] || -> until2p7(s42)* node4(s41). % 76.04/76.25 56616[133:Spt:56615.0] || -> until2p7(s42)*. % 76.04/76.25 56617[133:MRR:240.0,56616.0] || -> until2p7(s43)* node4(s42). % 76.04/76.25 56618[134:Spt:56617.0] || -> until2p7(s43)*. % 76.04/76.25 56619[134:MRR:241.0,56618.0] || -> until2p7(s44)* node4(s43). % 76.04/76.25 56620[135:Spt:56619.0] || -> until2p7(s44)*. % 76.04/76.25 56621[135:MRR:539.0,56620.0] || -> until2p7(s45)* node4(s44). % 76.04/76.25 56622[136:Spt:56621.0] || -> until2p7(s45)*. % 76.04/76.25 56623[136:MRR:544.0,56622.0] || -> until2p7(s46)* node4(s45). % 76.04/76.25 56624[137:Spt:56623.0] || -> until2p7(s46)*. % 76.04/76.25 56625[137:MRR:549.0,56624.0] || -> until2p7(s47)* node4(s46). % 76.04/76.25 56626[138:Spt:56625.0] || -> until2p7(s47)*. % 76.04/76.25 56627[138:MRR:554.0,56626.0] || -> until2p7(s48)* node4(s47). % 76.04/76.25 56628[139:Spt:56627.0] || -> until2p7(s48)*. % 76.04/76.25 56629[139:MRR:559.0,56628.0] || -> until2p7(s49)* node4(s48). % 76.04/76.25 56630[140:Spt:56629.0] || -> until2p7(s49)*. % 76.04/76.25 56631[140:MRR:194.0,56630.0] || -> node4(s49)*. % 76.04/76.25 56632[140:MRR:56541.0,56631.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.25 56636[140:Res:53.1,56632.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.25 56638[140:MRR:56636.0,56548.0] || -> . % 76.04/76.25 56639[140:Spt:56638.0,56629.0,56630.0] || until2p7(s49)*+ -> . % 76.04/76.25 56640[140:Spt:56638.0,56629.1] || -> node4(s48)*. % 76.04/76.25 56641[140:MRR:56553.0,56640.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.25 56644[140:Res:53.1,56641.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.25 56646[140:MRR:56644.0,56362.0] || -> . % 76.04/76.25 56647[139:Spt:56646.0,56627.0,56628.0] || until2p7(s48)*+ -> . % 76.04/76.25 56648[139:Spt:56646.0,56627.1] || -> node4(s47)*. % 76.04/76.25 56649[139:MRR:56365.0,56648.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.25 56652[139:Res:53.1,56649.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.25 56655[139:Res:56652.0,61.1] always3(s47) || -> . % 76.04/76.25 56656[139:SSi:56655.0,736.0,56356.0,56368.0,56626.0,56648.0] || -> . % 76.04/76.25 56657[138:Spt:56656.0,56625.0,56626.0] || until2p7(s47)*+ -> . % 76.04/76.25 56658[138:Spt:56656.0,56625.1] || -> node4(s46)*. % 76.04/76.25 56660[138:MRR:780.0,56658.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.25 56677[138:Res:53.1,56660.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.25 56679[138:MRR:56677.0,56342.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.25 56681[138:Res:56679.0,61.1] always3(s47) || -> . % 76.04/76.25 56682[138:SSi:56681.0,736.0,56356.0,56368.0] || -> . % 76.04/76.25 56683[137:Spt:56682.0,56623.0,56624.0] || until2p7(s46)*+ -> . % 76.04/76.25 56684[137:Spt:56682.0,56623.1] || -> node4(s45)*. % 76.04/76.25 56685[137:MRR:56345.0,56684.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.25 56688[137:Res:53.1,56685.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.25 56691[137:Res:56688.0,61.1] always3(s45) || -> . % 76.04/76.25 56692[137:SSi:56691.0,734.0,56336.0,56348.0,56622.0,56684.0] || -> . % 76.04/76.25 56693[136:Spt:56692.0,56621.0,56622.0] || until2p7(s45)*+ -> . % 76.04/76.25 56694[136:Spt:56692.0,56621.1] || -> node4(s44)*. % 76.04/76.25 56696[136:MRR:786.0,56694.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.25 56708[136:Res:53.1,56696.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.25 56710[136:MRR:56708.0,56322.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.25 56715[136:Res:56710.0,61.1] always3(s45) || -> . % 76.04/76.25 56716[136:SSi:56715.0,734.0,56336.0,56348.0] || -> . % 76.04/76.25 56717[135:Spt:56716.0,56619.0,56620.0] || until2p7(s44)*+ -> . % 76.04/76.25 56718[135:Spt:56716.0,56619.1] || -> node4(s43)*. % 76.04/76.25 56719[135:MRR:56325.0,56718.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.25 56722[135:Res:53.1,56719.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.25 56726[135:Res:56722.0,61.1] always3(s43) || -> . % 76.04/76.25 56727[135:SSi:56726.0,732.0,56316.0,56331.0,56618.0,56718.0] || -> . % 76.04/76.25 56728[134:Spt:56727.0,56617.0,56618.0] || until2p7(s43)*+ -> . % 76.04/76.25 56729[134:Spt:56727.0,56617.1] || -> node4(s42)*. % 76.04/76.25 56731[134:MRR:792.0,56729.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.25 56742[134:Res:53.1,56731.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.25 56744[134:MRR:56742.0,56299.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.25 56746[134:Res:56744.0,61.1] always3(s43) || -> . % 76.04/76.25 56747[134:SSi:56746.0,732.0,56316.0,56331.0] || -> . % 76.04/76.25 56748[133:Spt:56747.0,56615.0,56616.0] || until2p7(s42)*+ -> . % 76.04/76.25 56749[133:Spt:56747.0,56615.1] || -> node4(s41)*. % 76.04/76.25 56750[133:MRR:56302.0,56749.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.25 56754[133:Res:53.1,56750.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.25 56757[133:Res:56754.0,61.1] always3(s41) || -> . % 76.04/76.25 56758[133:SSi:56757.0,730.0,56293.0,56305.0,56614.0,56749.0] || -> . % 76.04/76.25 56759[132:Spt:56758.0,56613.0,56614.0] || until2p7(s41)*+ -> . % 76.04/76.25 56760[132:Spt:56758.0,56613.1] || -> node4(s40)*. % 76.04/76.25 56762[132:MRR:798.0,56760.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.25 56773[132:Res:53.1,56762.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.25 56775[132:MRR:56773.0,56279.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.25 56777[132:Res:56775.0,61.1] always3(s41) || -> . % 76.04/76.25 56778[132:SSi:56777.0,730.0,56293.0,56305.0] || -> . % 76.04/76.25 56779[131:Spt:56778.0,56611.0,56612.0] || until2p7(s40)*+ -> . % 76.04/76.25 56780[131:Spt:56778.0,56611.1] || -> node4(s39)*. % 76.04/76.25 56781[131:MRR:56282.0,56780.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.25 56784[131:Res:53.1,56781.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.25 56787[131:Res:56784.0,61.1] always3(s39) || -> . % 76.04/76.25 56788[131:SSi:56787.0,728.0,56273.0,56285.0,56610.0,56780.0] || -> . % 76.04/76.25 56789[130:Spt:56788.0,56609.0,56610.0] || until2p7(s39)*+ -> . % 76.04/76.25 56790[130:Spt:56788.0,56609.1] || -> node4(s38)*. % 76.04/76.25 56792[130:MRR:804.0,56790.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.25 56804[130:Res:53.1,56792.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.25 56806[130:MRR:56804.0,56259.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.25 56808[130:Res:56806.0,61.1] always3(s39) || -> . % 76.04/76.25 56809[130:SSi:56808.0,728.0,56273.0,56285.0] || -> . % 76.04/76.25 56810[129:Spt:56809.0,56607.0,56608.0] || until2p7(s38)*+ -> . % 76.04/76.25 56811[129:Spt:56809.0,56607.1] || -> node4(s37)*. % 76.04/76.25 56812[129:MRR:56262.0,56811.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.25 56815[129:Res:53.1,56812.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.25 56818[129:Res:56815.0,61.1] always3(s37) || -> . % 76.04/76.25 56819[129:SSi:56818.0,726.0,56253.0,56268.0,56606.0,56811.0] || -> . % 76.04/76.25 56820[128:Spt:56819.0,56605.0,56606.0] || until2p7(s37)*+ -> . % 76.04/76.25 56821[128:Spt:56819.0,56605.1] || -> node4(s36)*. % 76.04/76.25 56823[128:MRR:810.0,56821.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.25 56835[128:Res:53.1,56823.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.25 56837[128:MRR:56835.0,56236.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.25 56842[128:Res:56837.0,61.1] always3(s37) || -> . % 76.04/76.25 56843[128:SSi:56842.0,726.0,56253.0,56268.0] || -> . % 76.04/76.25 56844[127:Spt:56843.0,56603.0,56604.0] || until2p7(s36)*+ -> . % 76.04/76.25 56845[127:Spt:56843.0,56603.1] || -> node4(s35)*. % 76.04/76.25 56846[127:MRR:56239.0,56845.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.25 56849[127:Res:53.1,56846.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.25 56853[127:Res:56849.0,61.1] always3(s35) || -> . % 76.04/76.25 56854[127:SSi:56853.0,724.0,56230.0,56242.0,56602.0,56845.0] || -> . % 76.04/76.25 56855[126:Spt:56854.0,56601.0,56602.0] || until2p7(s35)*+ -> . % 76.04/76.25 56856[126:Spt:56854.0,56601.1] || -> node4(s34)*. % 76.04/76.25 56858[126:MRR:816.0,56856.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.25 56869[126:Res:53.1,56858.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.25 56871[126:MRR:56869.0,56216.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.25 56873[126:Res:56871.0,61.1] always3(s35) || -> . % 76.04/76.25 56874[126:SSi:56873.0,724.0,56230.0,56242.0] || -> . % 76.04/76.25 56875[125:Spt:56874.0,56599.0,56600.0] || until2p7(s34)*+ -> . % 76.04/76.25 56876[125:Spt:56874.0,56599.1] || -> node4(s33)*. % 76.04/76.25 56877[125:MRR:56219.0,56876.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.25 56881[125:Res:53.1,56877.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.25 56884[125:Res:56881.0,61.1] always3(s33) || -> . % 76.04/76.25 56885[125:SSi:56884.0,722.0,56210.0,56222.0,56598.0,56876.0] || -> . % 76.04/76.25 56886[124:Spt:56885.0,56597.0,56598.0] || until2p7(s33)*+ -> . % 76.04/76.25 56887[124:Spt:56885.0,56597.1] || -> node4(s32)*. % 76.04/76.25 56889[124:MRR:822.0,56887.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.25 56900[124:Res:53.1,56889.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.25 56902[124:MRR:56900.0,56196.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.25 56904[124:Res:56902.0,61.1] always3(s33) || -> . % 76.04/76.25 56905[124:SSi:56904.0,722.0,56210.0,56222.0] || -> . % 76.04/76.25 56906[123:Spt:56905.0,56595.0,56596.0] || until2p7(s32)*+ -> . % 76.04/76.25 56907[123:Spt:56905.0,56595.1] || -> node4(s31)*. % 76.04/76.25 56908[123:MRR:56199.0,56907.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.04/76.25 56911[123:Res:53.1,56908.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.25 56914[123:Res:56911.0,61.1] always3(s31) || -> . % 76.04/76.25 56915[123:SSi:56914.0,720.0,56190.0,56205.0,56594.0,56907.0] || -> . % 76.04/76.25 56916[122:Spt:56915.0,56593.0,56594.0] || until2p7(s31)*+ -> . % 76.04/76.25 56917[122:Spt:56915.0,56593.1] || -> node4(s30)*. % 76.04/76.25 56919[122:MRR:828.0,56917.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.25 56931[122:Res:53.1,56919.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.25 56933[123:Spt:56931.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.25 56935[123:Res:56933.0,61.1] always3(s30) || -> . % 76.04/76.25 56936[123:SSi:56935.0,719.0,56184.0,56189.0,56592.0,56917.0] || -> . % 76.04/76.25 56937[123:Spt:56936.0,56931.0,56933.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.25 56938[123:Spt:56936.0,56931.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.25 56942[123:Res:56938.0,61.1] always3(s31) || -> . % 76.04/76.25 56943[123:SSi:56942.0,720.0,56190.0,56205.0] || -> . % 76.04/76.25 56944[121:Spt:56943.0,56591.0,56592.0] || until2p7(s30)*+ -> . % 76.04/76.25 56945[121:Spt:56943.0,56591.1] || -> node4(s29)*. % 76.04/76.25 56947[121:MRR:831.0,56945.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.25 56954[121:Res:53.1,56947.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.25 56956[122:Spt:56954.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.25 56958[122:Res:56956.0,61.1] always3(s29) || -> . % 76.04/76.25 56959[122:SSi:56958.0,718.0,56181.0,56183.0,56590.0,56945.0] || -> . % 76.04/76.25 56960[122:Spt:56959.0,56954.0,56956.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.25 56961[122:Spt:56959.0,56954.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.25 56965[122:Res:56961.0,61.1] always3(s30) || -> . % 76.04/76.25 56966[122:SSi:56965.0,719.0,56184.0,56189.0] || -> . % 76.04/76.25 56967[120:Spt:56966.0,56589.0,56590.0] || until2p7(s29)*+ -> . % 76.04/76.25 56968[120:Spt:56966.0,56589.1] || -> node4(s28)*. % 76.04/76.25 56970[120:MRR:834.0,56968.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.25 56973[120:Res:53.1,56970.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.25 56975[121:Spt:56973.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.25 56977[121:Res:56975.0,61.1] always3(s28) || -> . % 76.04/76.25 56978[121:SSi:56977.0,717.0,56175.0,56180.0,56588.0,56968.0] || -> . % 76.04/76.25 56979[121:Spt:56978.0,56973.0,56975.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.25 56980[121:Spt:56978.0,56973.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.25 56984[121:Res:56980.0,61.1] always3(s29) || -> . % 76.04/76.25 56985[121:SSi:56984.0,718.0,56181.0,56183.0] || -> . % 76.04/76.25 56986[119:Spt:56985.0,56587.0,56588.0] || until2p7(s28)*+ -> . % 76.04/76.25 56987[119:Spt:56985.0,56587.1] || -> node4(s27)*. % 76.04/76.25 56989[119:MRR:837.0,56987.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.25 56992[119:Res:53.1,56989.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.25 56994[120:Spt:56992.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.25 56996[120:Res:56994.0,61.1] always3(s27) || -> . % 76.04/76.25 56997[120:SSi:56996.0,716.0,56172.0,56174.0,56586.0,56987.0] || -> . % 76.04/76.25 56998[120:Spt:56997.0,56992.0,56994.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.25 56999[120:Spt:56997.0,56992.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.25 57003[120:Res:56999.0,61.1] always3(s28) || -> . % 76.04/76.25 57004[120:SSi:57003.0,717.0,56175.0,56180.0] || -> . % 76.04/76.25 57005[118:Spt:57004.0,56585.0,56586.0] || until2p7(s27)*+ -> . % 76.04/76.25 57006[118:Spt:57004.0,56585.1] || -> node4(s26)*. % 76.04/76.25 57008[118:MRR:840.0,57006.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.25 57011[118:Res:53.1,57008.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.25 57016[119:Spt:57011.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.25 57018[119:Res:57016.0,61.1] always3(s26) || -> . % 76.04/76.25 57019[119:SSi:57018.0,715.0,56166.0,56171.0,56584.0,57006.0] || -> . % 76.04/76.25 57020[119:Spt:57019.0,57011.0,57016.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.25 57021[119:Spt:57019.0,57011.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.25 57025[119:Res:57021.0,61.1] always3(s27) || -> . % 76.04/76.25 57026[119:SSi:57025.0,716.0,56172.0,56174.0] || -> . % 76.04/76.25 57027[117:Spt:57026.0,56583.0,56584.0] || until2p7(s26)*+ -> . % 76.04/76.25 57028[117:Spt:57026.0,56583.1] || -> node4(s25)*. % 76.04/76.25 57030[117:MRR:843.0,57028.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.25 57033[117:Res:53.1,57030.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.25 57035[118:Spt:57033.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.25 57037[118:Res:57035.0,61.1] always3(s25) || -> . % 76.04/76.25 57038[118:SSi:57037.0,714.0,56163.0,56165.0,56582.0,57028.0] || -> . % 76.04/76.25 57039[118:Spt:57038.0,57033.0,57035.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.25 57040[118:Spt:57038.0,57033.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.25 57044[118:Res:57040.0,61.1] always3(s26) || -> . % 76.04/76.25 57045[118:SSi:57044.0,715.0,56166.0,56171.0] || -> . % 76.04/76.25 57046[116:Spt:57045.0,56581.0,56582.0] || until2p7(s25)*+ -> . % 76.04/76.25 57047[116:Spt:57045.0,56581.1] || -> node4(s24)*. % 76.04/76.25 57049[116:MRR:846.0,57047.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.25 57052[116:Res:53.1,57049.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.25 57054[117:Spt:57052.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.25 57056[117:Res:57054.0,61.1] always3(s24) || -> . % 76.04/76.25 57057[117:SSi:57056.0,713.0,56157.0,56162.0,56580.0,57047.0] || -> . % 76.04/76.25 57058[117:Spt:57057.0,57052.0,57054.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.25 57059[117:Spt:57057.0,57052.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.25 57063[117:Res:57059.0,61.1] always3(s25) || -> . % 76.04/76.25 57064[117:SSi:57063.0,714.0,56163.0,56165.0] || -> . % 76.04/76.25 57065[115:Spt:57064.0,56579.0,56580.0] || until2p7(s24)*+ -> . % 76.04/76.25 57066[115:Spt:57064.0,56579.1] || -> node4(s23)*. % 76.04/76.25 57068[115:MRR:849.0,57066.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.25 57071[115:Res:53.1,57068.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.25 57073[116:Spt:57071.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.25 57075[116:Res:57073.0,61.1] always3(s23) || -> . % 76.04/76.25 57076[116:SSi:57075.0,712.0,56154.0,56156.0,56578.0,57066.0] || -> . % 76.04/76.25 57077[116:Spt:57076.0,57071.0,57073.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.25 57078[116:Spt:57076.0,57071.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.25 57082[116:Res:57078.0,61.1] always3(s24) || -> . % 76.04/76.25 57083[116:SSi:57082.0,713.0,56157.0,56162.0] || -> . % 76.04/76.25 57084[114:Spt:57083.0,56577.0,56578.0] || until2p7(s23)*+ -> . % 76.04/76.25 57085[114:Spt:57083.0,56577.1] || -> node4(s22)*. % 76.04/76.25 57087[114:MRR:852.0,57085.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.25 57090[114:Res:53.1,57087.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.25 57095[115:Spt:57090.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.25 57097[115:Res:57095.0,61.1] always3(s22) || -> . % 76.04/76.25 57098[115:SSi:57097.0,711.0,56148.0,56153.0,56576.0,57085.0] || -> . % 76.04/76.25 57099[115:Spt:57098.0,57090.0,57095.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.25 57100[115:Spt:57098.0,57090.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.25 57104[115:Res:57100.0,61.1] always3(s23) || -> . % 76.04/76.25 57105[115:SSi:57104.0,712.0,56154.0,56156.0] || -> . % 76.04/76.25 57106[113:Spt:57105.0,56575.0,56576.0] || until2p7(s22)*+ -> . % 76.04/76.25 57107[113:Spt:57105.0,56575.1] || -> node4(s21)*. % 76.04/76.25 57109[113:MRR:855.0,57107.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.25 57112[113:Res:53.1,57109.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.25 57114[114:Spt:57112.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.25 57116[114:Res:57114.0,61.1] always3(s21) || -> . % 76.04/76.25 57117[114:SSi:57116.0,710.0,56145.0,56147.0,56574.0,57107.0] || -> . % 76.04/76.25 57118[114:Spt:57117.0,57112.0,57114.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.25 57119[114:Spt:57117.0,57112.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.25 57123[114:Res:57119.0,61.1] always3(s22) || -> . % 76.04/76.25 57124[114:SSi:57123.0,711.0,56148.0,56153.0] || -> . % 76.04/76.25 57125[112:Spt:57124.0,56573.0,56574.0] || until2p7(s21)*+ -> . % 76.04/76.25 57126[112:Spt:57124.0,56573.1] || -> node4(s20)*. % 76.04/76.25 57128[112:MRR:858.0,57126.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.25 57131[112:Res:53.1,57128.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.25 57133[113:Spt:57131.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.25 57135[113:Res:57133.0,61.1] always3(s20) || -> . % 76.04/76.25 57136[113:SSi:57135.0,709.0,56139.0,56144.0,56572.0,57126.0] || -> . % 76.04/76.25 57137[113:Spt:57136.0,57131.0,57133.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.25 57138[113:Spt:57136.0,57131.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.25 57142[113:Res:57138.0,61.1] always3(s21) || -> . % 76.04/76.25 57143[113:SSi:57142.0,710.0,56145.0,56147.0] || -> . % 76.04/76.25 57144[111:Spt:57143.0,56571.0,56572.0] || until2p7(s20)*+ -> . % 76.04/76.25 57145[111:Spt:57143.0,56571.1] || -> node4(s19)*. % 76.04/76.25 57147[111:MRR:861.0,57145.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.25 57150[111:Res:53.1,57147.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.25 57152[112:Spt:57150.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.25 57154[112:Res:57152.0,61.1] always3(s19) || -> . % 76.04/76.25 57155[112:SSi:57154.0,708.0,56136.0,56138.0,56570.0,57145.0] || -> . % 76.04/76.25 57156[112:Spt:57155.0,57150.0,57152.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.25 57157[112:Spt:57155.0,57150.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.25 57161[112:Res:57157.0,61.1] always3(s20) || -> . % 76.04/76.25 57162[112:SSi:57161.0,709.0,56139.0,56144.0] || -> . % 76.04/76.25 57163[110:Spt:57162.0,56569.0,56570.0] || until2p7(s19)*+ -> . % 76.04/76.25 57164[110:Spt:57162.0,56569.1] || -> node4(s18)*. % 76.04/76.25 57166[110:MRR:864.0,57164.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.25 57169[110:Res:53.1,57166.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.25 57174[111:Spt:57169.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.25 57176[111:Res:57174.0,61.1] always3(s18) || -> . % 76.04/76.25 57177[111:SSi:57176.0,707.0,56130.0,56135.0,56568.0,57164.0] || -> . % 76.04/76.25 57178[111:Spt:57177.0,57169.0,57174.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.25 57179[111:Spt:57177.0,57169.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.25 57183[111:Res:57179.0,61.1] always3(s19) || -> . % 76.04/76.25 57184[111:SSi:57183.0,708.0,56136.0,56138.0] || -> . % 76.04/76.25 57185[109:Spt:57184.0,56567.0,56568.0] || until2p7(s18)*+ -> . % 76.04/76.25 57186[109:Spt:57184.0,56567.1] || -> node4(s17)*. % 76.04/76.25 57188[109:MRR:867.0,57186.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.25 57191[109:Res:53.1,57188.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.25 57193[110:Spt:57191.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.25 57195[110:Res:57193.0,61.1] always3(s17) || -> . % 76.04/76.25 57196[110:SSi:57195.0,706.0,56127.0,56129.0,56566.0,57186.0] || -> . % 76.04/76.25 57197[110:Spt:57196.0,57191.0,57193.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.25 57198[110:Spt:57196.0,57191.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.25 57202[110:Res:57198.0,61.1] always3(s18) || -> . % 76.04/76.25 57203[110:SSi:57202.0,707.0,56130.0,56135.0] || -> . % 76.04/76.25 57204[108:Spt:57203.0,56565.0,56566.0] || until2p7(s17)*+ -> . % 76.04/76.25 57205[108:Spt:57203.0,56565.1] || -> node4(s16)*. % 76.04/76.25 57207[108:MRR:870.0,57205.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.25 57210[108:Res:53.1,57207.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.25 57212[109:Spt:57210.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.25 57214[109:Res:57212.0,61.1] always3(s16) || -> . % 76.04/76.25 57215[109:SSi:57214.0,705.0,56121.0,56126.0,56564.0,57205.0] || -> . % 76.04/76.25 57216[109:Spt:57215.0,57210.0,57212.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.25 57217[109:Spt:57215.0,57210.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.25 57221[109:Res:57217.0,61.1] always3(s17) || -> . % 76.04/76.25 57222[109:SSi:57221.0,706.0,56127.0,56129.0] || -> . % 76.04/76.25 57223[107:Spt:57222.0,56563.0,56564.0] || until2p7(s16)*+ -> . % 76.04/76.25 57224[107:Spt:57222.0,56563.1] || -> node4(s15)*. % 76.04/76.25 57226[107:MRR:873.0,57224.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.25 57229[107:Res:53.1,57226.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.25 57231[108:Spt:57229.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.25 57233[108:Res:57231.0,61.1] always3(s15) || -> . % 76.04/76.25 57234[108:SSi:57233.0,704.0,56118.0,56120.0,56562.0,57224.0] || -> . % 76.04/76.25 57235[108:Spt:57234.0,57229.0,57231.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.25 57236[108:Spt:57234.0,57229.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.25 57240[108:Res:57236.0,61.1] always3(s16) || -> . % 76.04/76.25 57241[108:SSi:57240.0,705.0,56121.0,56126.0] || -> . % 76.04/76.25 57242[106:Spt:57241.0,56561.0,56562.0] || until2p7(s15)*+ -> . % 76.04/76.25 57243[106:Spt:57241.0,56561.1] || -> node4(s14)*. % 76.04/76.25 57245[106:MRR:876.0,57243.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.25 57248[106:Res:53.1,57245.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.25 57253[107:Spt:57248.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.25 57255[107:Res:57253.0,61.1] always3(s14) || -> . % 76.04/76.25 57256[107:SSi:57255.0,703.0,56112.0,56117.0,56560.0,57243.0] || -> . % 76.04/76.25 57257[107:Spt:57256.0,57248.0,57253.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.25 57258[107:Spt:57256.0,57248.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.25 57262[107:Res:57258.0,61.1] always3(s15) || -> . % 76.04/76.25 57263[107:SSi:57262.0,704.0,56118.0,56120.0] || -> . % 76.04/76.25 57264[105:Spt:57263.0,56559.0,56560.0] || until2p7(s14)*+ -> . % 76.04/76.25 57265[105:Spt:57263.0,56559.1] || -> node4(s13)*. % 76.04/76.25 57267[105:MRR:879.0,57265.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.25 57270[105:Res:53.1,57267.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.25 57272[106:Spt:57270.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.25 57274[106:Res:57272.0,61.1] always3(s13) || -> . % 76.04/76.25 57275[106:SSi:57274.0,702.0,56109.0,56111.0,56558.0,57265.0] || -> . % 76.04/76.25 57276[106:Spt:57275.0,57270.0,57272.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.25 57277[106:Spt:57275.0,57270.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.25 57281[106:Res:57277.0,61.1] always3(s14) || -> . % 76.04/76.25 57282[106:SSi:57281.0,703.0,56112.0,56117.0] || -> . % 76.04/76.25 57283[104:Spt:57282.0,56557.0,56558.0] || until2p7(s13)*+ -> . % 76.04/76.25 57284[104:Spt:57282.0,56557.1] || -> node4(s12)*. % 76.04/76.25 57286[104:MRR:882.0,57284.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.25 57289[104:Res:53.1,57286.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.25 57291[105:Spt:57289.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.25 57293[105:Res:57291.0,61.1] always3(s12) || -> . % 76.04/76.25 57294[105:SSi:57293.0,701.0,56103.0,56108.0,56556.0,57284.0] || -> . % 76.04/76.25 57295[105:Spt:57294.0,57289.0,57291.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.25 57296[105:Spt:57294.0,57289.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.25 57300[105:Res:57296.0,61.1] always3(s13) || -> . % 76.04/76.25 57301[105:SSi:57300.0,702.0,56109.0,56111.0] || -> . % 76.04/76.25 57302[103:Spt:57301.0,56555.0,56556.0] || until2p7(s12)*+ -> . % 76.04/76.25 57303[103:Spt:57301.0,56555.1] || -> node4(s11)*. % 76.04/76.25 57305[103:MRR:885.0,57303.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.25 57308[103:Res:53.1,57305.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.25 57310[104:Spt:57308.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.25 57312[104:Res:57310.0,61.1] always3(s11) || -> . % 76.04/76.25 57313[104:SSi:57312.0,700.0,56100.0,56102.0,56554.0,57303.0] || -> . % 76.04/76.25 57314[104:Spt:57313.0,57308.0,57310.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.25 57315[104:Spt:57313.0,57308.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.25 57319[104:Res:57315.0,61.1] always3(s12) || -> . % 76.04/76.25 57320[104:SSi:57319.0,701.0,56103.0,56108.0] || -> . % 76.04/76.25 57321[102:Spt:57320.0,56551.0,56554.0] || until2p7(s11)*+ -> . % 76.04/76.25 57322[102:Spt:57320.0,56551.1] || -> node4(s10)*. % 76.04/76.25 57324[102:MRR:888.0,57322.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.25 57327[102:Res:53.1,57324.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.25 57329[102:MRR:57327.0,56536.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.25 57334[102:Res:57329.0,61.1] always3(s11) || -> . % 76.04/76.25 57335[102:SSi:57334.0,700.0,56100.0,56102.0] || -> . % 76.04/76.25 57336[99:Spt:57335.0,56370.2,56378.0] || xuntil6(s48)*+ -> . % 76.04/76.25 57337[99:Spt:57335.0,56370.0,56370.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.25 57338[99:Res:53.1,57337.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.25 57340[99:MRR:57338.0,56362.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.25 57342[99:Res:57340.0,61.1] always3(s49) || -> . % 76.04/76.25 57343[99:SSi:57342.0,50.0,738.0] || -> . % 76.04/76.25 57344[98:Spt:57343.0,56366.1,56368.0] || xuntil6(s47)* -> . % 76.04/76.25 57345[98:Spt:57343.0,56366.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.25 57348[98:Res:57345.0,61.1] always3(s47) || -> . % 76.04/76.25 57349[98:SSi:57348.0,736.0,56356.0] || -> . % 76.04/76.25 57350[96:Spt:57349.0,56350.2,56355.0] || xuntil6(s46)*+ -> . % 76.04/76.25 57351[96:Spt:57349.0,56350.0,56350.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.25 57352[96:Res:53.1,57351.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.25 57354[96:MRR:57352.0,56342.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.25 57357[96:Res:57354.0,61.1] always3(s47) || -> . % 76.04/76.25 57358[96:SSi:57357.0,736.0] || -> . % 76.04/76.25 57359[95:Spt:57358.0,56346.1,56348.0] || xuntil6(s45)* -> . % 76.04/76.25 57360[95:Spt:57358.0,56346.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.25 57363[95:Res:57360.0,61.1] always3(s45) || -> . % 76.04/76.25 57364[95:SSi:57363.0,734.0,56336.0] || -> . % 76.04/76.25 57365[93:Spt:57364.0,56333.2,56335.0] || xuntil6(s44)*+ -> . % 76.04/76.25 57366[93:Spt:57364.0,56333.0,56333.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.25 57367[93:Res:53.1,57366.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.25 57369[93:MRR:57367.0,56322.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.25 57371[93:Res:57369.0,61.1] always3(s45) || -> . % 76.04/76.25 57372[93:SSi:57371.0,734.0] || -> . % 76.04/76.25 57373[92:Spt:57372.0,56326.1,56331.0] || xuntil6(s43)* -> . % 76.04/76.25 57374[92:Spt:57372.0,56326.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.25 57377[92:Res:57374.0,61.1] always3(s43) || -> . % 76.04/76.25 57378[92:SSi:57377.0,732.0,56316.0] || -> . % 76.04/76.25 57379[90:Spt:57378.0,56307.2,56315.0] || xuntil6(s42)*+ -> . % 76.04/76.25 57380[90:Spt:57378.0,56307.0,56307.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.25 57381[90:Res:53.1,57380.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.25 57383[90:MRR:57381.0,56299.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.25 57386[90:Res:57383.0,61.1] always3(s43) || -> . % 76.04/76.25 57387[90:SSi:57386.0,732.0] || -> . % 76.04/76.25 57388[89:Spt:57387.0,56303.1,56305.0] || xuntil6(s41)* -> . % 76.04/76.25 57389[89:Spt:57387.0,56303.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.25 57392[89:Res:57389.0,61.1] always3(s41) || -> . % 76.04/76.25 57393[89:SSi:57392.0,730.0,56293.0] || -> . % 76.04/76.25 57394[87:Spt:57393.0,56287.2,56292.0] || xuntil6(s40)*+ -> . % 76.04/76.25 57395[87:Spt:57393.0,56287.0,56287.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.25 57396[87:Res:53.1,57395.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.25 57398[87:MRR:57396.0,56279.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.25 57400[87:Res:57398.0,61.1] always3(s41) || -> . % 76.04/76.25 57401[87:SSi:57400.0,730.0] || -> . % 76.04/76.25 57402[86:Spt:57401.0,56283.1,56285.0] || xuntil6(s39)* -> . % 76.04/76.25 57403[86:Spt:57401.0,56283.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.25 57406[86:Res:57403.0,61.1] always3(s39) || -> . % 76.04/76.25 57407[86:SSi:57406.0,728.0,56273.0] || -> . % 76.04/76.25 57408[84:Spt:57407.0,56270.2,56272.0] || xuntil6(s38)*+ -> . % 76.04/76.25 57409[84:Spt:57407.0,56270.0,56270.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.25 57410[84:Res:53.1,57409.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.25 57412[84:MRR:57410.0,56259.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.25 57414[84:Res:57412.0,61.1] always3(s39) || -> . % 76.04/76.25 57415[84:SSi:57414.0,728.0] || -> . % 76.04/76.25 57416[83:Spt:57415.0,56263.1,56268.0] || xuntil6(s37)* -> . % 76.04/76.25 57417[83:Spt:57415.0,56263.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.25 57420[83:Res:57417.0,61.1] always3(s37) || -> . % 76.04/76.25 57421[83:SSi:57420.0,726.0,56253.0] || -> . % 76.04/76.25 57422[81:Spt:57421.0,56244.2,56252.0] || xuntil6(s36)*+ -> . % 76.04/76.25 57423[81:Spt:57421.0,56244.0,56244.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.25 57424[81:Res:53.1,57423.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.25 57426[81:MRR:57424.0,56236.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.25 57428[81:Res:57426.0,61.1] always3(s37) || -> . % 76.04/76.25 57429[81:SSi:57428.0,726.0] || -> . % 76.04/76.25 57430[80:Spt:57429.0,56240.1,56242.0] || xuntil6(s35)* -> . % 76.04/76.25 57431[80:Spt:57429.0,56240.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.25 57434[80:Res:57431.0,61.1] always3(s35) || -> . % 76.04/76.25 57435[80:SSi:57434.0,724.0,56230.0] || -> . % 76.04/76.25 57436[78:Spt:57435.0,56224.2,56229.0] || xuntil6(s34)*+ -> . % 76.04/76.25 57437[78:Spt:57435.0,56224.0,56224.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.25 57438[78:Res:53.1,57437.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.25 57440[78:MRR:57438.0,56216.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.25 57442[78:Res:57440.0,61.1] always3(s35) || -> . % 76.04/76.25 57443[78:SSi:57442.0,724.0] || -> . % 76.04/76.25 57444[77:Spt:57443.0,56220.1,56222.0] || xuntil6(s33)* -> . % 76.04/76.25 57445[77:Spt:57443.0,56220.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.25 57448[77:Res:57445.0,61.1] always3(s33) || -> . % 76.04/76.25 57449[77:SSi:57448.0,722.0,56210.0] || -> . % 76.04/76.25 57450[75:Spt:57449.0,56207.2,56209.0] || xuntil6(s32)*+ -> . % 76.04/76.25 57451[75:Spt:57449.0,56207.0,56207.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.25 57452[75:Res:53.1,57451.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.25 57454[75:MRR:57452.0,56196.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.25 57456[75:Res:57454.0,61.1] always3(s33) || -> . % 76.04/76.25 57457[75:SSi:57456.0,722.0] || -> . % 76.04/76.25 57458[74:Spt:57457.0,56200.1,56205.0] || xuntil6(s31)* -> . % 76.04/76.25 57459[74:Spt:57457.0,56200.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.25 57462[74:Res:57459.0,61.1] always3(s31) || -> . % 76.04/76.25 57463[74:SSi:57462.0,720.0,56190.0] || -> . % 76.04/76.25 57464[72:Spt:57463.0,56185.2,56189.0] || xuntil6(s30)*+ -> . % 76.04/76.25 57465[72:Spt:57463.0,56185.0,56185.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.25 57466[72:Res:53.1,57465.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.25 57468[73:Spt:57466.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.25 57470[73:Res:57468.0,61.1] always3(s31) || -> . % 76.04/76.25 57471[73:SSi:57470.0,720.0] || -> . % 76.04/76.25 57472[73:Spt:57471.0,57466.1,57468.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.25 57473[73:Spt:57471.0,57466.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.25 57476[73:Res:57473.0,61.1] always3(s30) || -> . % 76.04/76.25 57477[73:SSi:57476.0,719.0,56184.0] || -> . % 76.04/76.25 57478[71:Spt:57477.0,56182.2,56183.0] || xuntil6(s29)*+ -> . % 76.04/76.25 57479[71:Spt:57477.0,56182.0,56182.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.25 57480[71:Res:53.1,57479.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.25 57482[72:Spt:57480.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.25 57484[72:Res:57482.0,61.1] always3(s30) || -> . % 76.04/76.25 57485[72:SSi:57484.0,719.0] || -> . % 76.04/76.25 57486[72:Spt:57485.0,57480.1,57482.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.25 57487[72:Spt:57485.0,57480.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.25 57490[72:Res:57487.0,61.1] always3(s29) || -> . % 76.04/76.25 57491[72:SSi:57490.0,718.0,56181.0] || -> . % 76.04/76.25 57492[70:Spt:57491.0,56176.2,56180.0] || xuntil6(s28)*+ -> . % 76.04/76.25 57493[70:Spt:57491.0,56176.0,56176.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.25 57494[70:Res:53.1,57493.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.25 57496[71:Spt:57494.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.25 57498[71:Res:57496.0,61.1] always3(s29) || -> . % 76.04/76.25 57499[71:SSi:57498.0,718.0] || -> . % 76.04/76.25 57500[71:Spt:57499.0,57494.1,57496.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.25 57501[71:Spt:57499.0,57494.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.25 57504[71:Res:57501.0,61.1] always3(s28) || -> . % 76.04/76.25 57505[71:SSi:57504.0,717.0,56175.0] || -> . % 76.04/76.25 57506[69:Spt:57505.0,56173.2,56174.0] || xuntil6(s27)*+ -> . % 76.04/76.25 57507[69:Spt:57505.0,56173.0,56173.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.25 57508[69:Res:53.1,57507.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.25 57510[70:Spt:57508.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.25 57512[70:Res:57510.0,61.1] always3(s28) || -> . % 76.04/76.25 57513[70:SSi:57512.0,717.0] || -> . % 76.04/76.25 57514[70:Spt:57513.0,57508.1,57510.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.25 57515[70:Spt:57513.0,57508.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.25 57518[70:Res:57515.0,61.1] always3(s27) || -> . % 76.04/76.25 57519[70:SSi:57518.0,716.0,56172.0] || -> . % 76.04/76.25 57520[68:Spt:57519.0,56167.2,56171.0] || xuntil6(s26)*+ -> . % 76.04/76.25 57521[68:Spt:57519.0,56167.0,56167.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.25 57522[68:Res:53.1,57521.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.25 57524[69:Spt:57522.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.25 57526[69:Res:57524.0,61.1] always3(s27) || -> . % 76.04/76.25 57527[69:SSi:57526.0,716.0] || -> . % 76.04/76.25 57528[69:Spt:57527.0,57522.1,57524.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.25 57529[69:Spt:57527.0,57522.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.25 57532[69:Res:57529.0,61.1] always3(s26) || -> . % 76.04/76.25 57533[69:SSi:57532.0,715.0,56166.0] || -> . % 76.04/76.25 57534[67:Spt:57533.0,56164.2,56165.0] || xuntil6(s25)*+ -> . % 76.04/76.25 57535[67:Spt:57533.0,56164.0,56164.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.25 57536[67:Res:53.1,57535.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.25 57538[68:Spt:57536.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.25 57540[68:Res:57538.0,61.1] always3(s26) || -> . % 76.04/76.25 57541[68:SSi:57540.0,715.0] || -> . % 76.04/76.25 57542[68:Spt:57541.0,57536.1,57538.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.25 57543[68:Spt:57541.0,57536.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.25 57546[68:Res:57543.0,61.1] always3(s25) || -> . % 76.04/76.25 57547[68:SSi:57546.0,714.0,56163.0] || -> . % 76.04/76.25 57548[66:Spt:57547.0,56158.2,56162.0] || xuntil6(s24)*+ -> . % 76.04/76.25 57549[66:Spt:57547.0,56158.0,56158.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.25 57550[66:Res:53.1,57549.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.25 57552[67:Spt:57550.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.25 57554[67:Res:57552.0,61.1] always3(s25) || -> . % 76.04/76.25 57555[67:SSi:57554.0,714.0] || -> . % 76.04/76.25 57556[67:Spt:57555.0,57550.1,57552.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.25 57557[67:Spt:57555.0,57550.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.25 57560[67:Res:57557.0,61.1] always3(s24) || -> . % 76.04/76.25 57561[67:SSi:57560.0,713.0,56157.0] || -> . % 76.04/76.25 57562[65:Spt:57561.0,56155.2,56156.0] || xuntil6(s23)*+ -> . % 76.04/76.25 57563[65:Spt:57561.0,56155.0,56155.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.25 57564[65:Res:53.1,57563.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.25 57566[66:Spt:57564.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.25 57568[66:Res:57566.0,61.1] always3(s24) || -> . % 76.04/76.25 57569[66:SSi:57568.0,713.0] || -> . % 76.04/76.25 57570[66:Spt:57569.0,57564.1,57566.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.25 57571[66:Spt:57569.0,57564.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.25 57574[66:Res:57571.0,61.1] always3(s23) || -> . % 76.04/76.25 57575[66:SSi:57574.0,712.0,56154.0] || -> . % 76.04/76.25 57576[64:Spt:57575.0,56149.2,56153.0] || xuntil6(s22)*+ -> . % 76.04/76.25 57577[64:Spt:57575.0,56149.0,56149.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.25 57578[64:Res:53.1,57577.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.25 57580[65:Spt:57578.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.25 57582[65:Res:57580.0,61.1] always3(s23) || -> . % 76.04/76.25 57583[65:SSi:57582.0,712.0] || -> . % 76.04/76.25 57584[65:Spt:57583.0,57578.1,57580.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.25 57585[65:Spt:57583.0,57578.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.25 57588[65:Res:57585.0,61.1] always3(s22) || -> . % 76.04/76.25 57589[65:SSi:57588.0,711.0,56148.0] || -> . % 76.04/76.25 57590[63:Spt:57589.0,56146.2,56147.0] || xuntil6(s21)*+ -> . % 76.04/76.25 57591[63:Spt:57589.0,56146.0,56146.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.25 57592[63:Res:53.1,57591.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.25 57594[64:Spt:57592.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.25 57596[64:Res:57594.0,61.1] always3(s22) || -> . % 76.04/76.25 57597[64:SSi:57596.0,711.0] || -> . % 76.04/76.25 57598[64:Spt:57597.0,57592.1,57594.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.25 57599[64:Spt:57597.0,57592.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.25 57602[64:Res:57599.0,61.1] always3(s21) || -> . % 76.04/76.25 57603[64:SSi:57602.0,710.0,56145.0] || -> . % 76.04/76.25 57604[62:Spt:57603.0,56140.2,56144.0] || xuntil6(s20)*+ -> . % 76.04/76.25 57605[62:Spt:57603.0,56140.0,56140.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.25 57606[62:Res:53.1,57605.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.25 57611[63:Spt:57606.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.25 57613[63:Res:57611.0,61.1] always3(s20) || -> . % 76.04/76.25 57614[63:SSi:57613.0,709.0,56139.0] || -> . % 76.04/76.25 57615[63:Spt:57614.0,57606.0,57611.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.25 57616[63:Spt:57614.0,57606.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.25 57620[63:Res:57616.0,61.1] always3(s21) || -> . % 76.04/76.25 57621[63:SSi:57620.0,710.0] || -> . % 76.04/76.25 57622[61:Spt:57621.0,56137.2,56138.0] || xuntil6(s19)*+ -> . % 76.04/76.25 57623[61:Spt:57621.0,56137.0,56137.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.25 57624[61:Res:53.1,57623.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.25 57626[62:Spt:57624.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.25 57628[62:Res:57626.0,61.1] always3(s20) || -> . % 76.04/76.25 57629[62:SSi:57628.0,709.0] || -> . % 76.04/76.25 57630[62:Spt:57629.0,57624.1,57626.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.25 57631[62:Spt:57629.0,57624.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.25 57634[62:Res:57631.0,61.1] always3(s19) || -> . % 76.04/76.25 57635[62:SSi:57634.0,708.0,56136.0] || -> . % 76.04/76.25 57636[60:Spt:57635.0,56131.2,56135.0] || xuntil6(s18)*+ -> . % 76.04/76.25 57637[60:Spt:57635.0,56131.0,56131.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.25 57638[60:Res:53.1,57637.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.25 57640[61:Spt:57638.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.25 57642[61:Res:57640.0,61.1] always3(s19) || -> . % 76.04/76.25 57643[61:SSi:57642.0,708.0] || -> . % 76.04/76.25 57644[61:Spt:57643.0,57638.1,57640.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.25 57645[61:Spt:57643.0,57638.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.25 57648[61:Res:57645.0,61.1] always3(s18) || -> . % 76.04/76.25 57649[61:SSi:57648.0,707.0,56130.0] || -> . % 76.04/76.25 57650[59:Spt:57649.0,56128.2,56129.0] || xuntil6(s17)*+ -> . % 76.04/76.25 57651[59:Spt:57649.0,56128.0,56128.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.25 57652[59:Res:53.1,57651.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.25 57657[60:Spt:57652.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.25 57659[60:Res:57657.0,61.1] always3(s17) || -> . % 76.04/76.25 57660[60:SSi:57659.0,706.0,56127.0] || -> . % 76.04/76.25 57661[60:Spt:57660.0,57652.0,57657.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.25 57662[60:Spt:57660.0,57652.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.25 57666[60:Res:57662.0,61.1] always3(s18) || -> . % 76.04/76.25 57667[60:SSi:57666.0,707.0] || -> . % 76.04/76.25 57668[58:Spt:57667.0,56122.2,56126.0] || xuntil6(s16)*+ -> . % 76.04/76.25 57669[58:Spt:57667.0,56122.0,56122.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.25 57670[58:Res:53.1,57669.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.25 57672[59:Spt:57670.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.25 57674[59:Res:57672.0,61.1] always3(s17) || -> . % 76.04/76.25 57675[59:SSi:57674.0,706.0] || -> . % 76.04/76.25 57676[59:Spt:57675.0,57670.1,57672.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.25 57677[59:Spt:57675.0,57670.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.25 57680[59:Res:57677.0,61.1] always3(s16) || -> . % 76.04/76.25 57681[59:SSi:57680.0,705.0,56121.0] || -> . % 76.04/76.25 57682[57:Spt:57681.0,56119.2,56120.0] || xuntil6(s15)*+ -> . % 76.04/76.25 57683[57:Spt:57681.0,56119.0,56119.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.25 57684[57:Res:53.1,57683.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.25 57686[58:Spt:57684.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.25 57688[58:Res:57686.0,61.1] always3(s16) || -> . % 76.04/76.25 57689[58:SSi:57688.0,705.0] || -> . % 76.04/76.25 57690[58:Spt:57689.0,57684.1,57686.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.25 57691[58:Spt:57689.0,57684.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.25 57694[58:Res:57691.0,61.1] always3(s15) || -> . % 76.04/76.25 57695[58:SSi:57694.0,704.0,56118.0] || -> . % 76.04/76.25 57696[56:Spt:57695.0,56113.2,56117.0] || xuntil6(s14)*+ -> . % 76.04/76.25 57697[56:Spt:57695.0,56113.0,56113.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.25 57698[56:Res:53.1,57697.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.25 57703[57:Spt:57698.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.25 57705[57:Res:57703.0,61.1] always3(s14) || -> . % 76.04/76.25 57706[57:SSi:57705.0,703.0,56112.0] || -> . % 76.04/76.25 57707[57:Spt:57706.0,57698.0,57703.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.25 57708[57:Spt:57706.0,57698.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.25 57712[57:Res:57708.0,61.1] always3(s15) || -> . % 76.04/76.25 57713[57:SSi:57712.0,704.0] || -> . % 76.04/76.25 57714[55:Spt:57713.0,56110.2,56111.0] || xuntil6(s13)*+ -> . % 76.04/76.25 57715[55:Spt:57713.0,56110.0,56110.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.25 57716[55:Res:53.1,57715.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.25 57718[56:Spt:57716.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.25 57720[56:Res:57718.0,61.1] always3(s14) || -> . % 76.04/76.25 57721[56:SSi:57720.0,703.0] || -> . % 76.04/76.25 57722[56:Spt:57721.0,57716.1,57718.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.25 57723[56:Spt:57721.0,57716.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.25 57726[56:Res:57723.0,61.1] always3(s13) || -> . % 76.04/76.25 57727[56:SSi:57726.0,702.0,56109.0] || -> . % 76.04/76.25 57728[54:Spt:57727.0,56104.2,56108.0] || xuntil6(s12)*+ -> . % 76.04/76.25 57729[54:Spt:57727.0,56104.0,56104.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.25 57730[54:Res:53.1,57729.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.25 57732[55:Spt:57730.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.25 57734[55:Res:57732.0,61.1] always3(s13) || -> . % 76.04/76.25 57735[55:SSi:57734.0,702.0] || -> . % 76.04/76.25 57736[55:Spt:57735.0,57730.1,57732.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.25 57737[55:Spt:57735.0,57730.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.25 57740[55:Res:57737.0,61.1] always3(s12) || -> . % 76.04/76.25 57741[55:SSi:57740.0,701.0,56103.0] || -> . % 76.04/76.25 57742[53:Spt:57741.0,56101.2,56102.0] || xuntil6(s11)*+ -> . % 76.04/76.25 57743[53:Spt:57741.0,56101.0,56101.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.25 57744[53:Res:53.1,57743.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.25 57749[54:Spt:57744.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.25 57751[54:Res:57749.0,61.1] always3(s11) || -> . % 76.04/76.25 57752[54:SSi:57751.0,700.0,56100.0] || -> . % 76.04/76.25 57753[54:Spt:57752.0,57744.0,57749.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.25 57754[54:Spt:57752.0,57744.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.25 57758[54:Res:57754.0,61.1] always3(s12) || -> . % 76.04/76.25 57759[54:SSi:57758.0,701.0] || -> . % 76.04/76.25 57760[52:Spt:57759.0,56095.2,56099.0] || xuntil6(s10)*+ -> . % 76.04/76.25 57761[52:Spt:57759.0,56095.0,56095.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.25 57762[52:Res:53.1,57761.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.25 57764[53:Spt:57762.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.25 57766[53:Res:57764.0,61.1] always3(s11) || -> . % 76.04/76.25 57767[53:SSi:57766.0,700.0] || -> . % 76.04/76.25 57768[53:Spt:57767.0,57762.1,57764.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.25 57769[53:Spt:57767.0,57762.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.25 57772[53:Res:57769.0,61.1] always3(s10) || -> . % 76.04/76.25 57773[53:SSi:57772.0,699.0,56094.0] || -> . % 76.04/76.25 57774[51:Spt:57773.0,56092.2,56093.0] || xuntil6(s9)*+ -> . % 76.04/76.25 57775[51:Spt:57773.0,56092.0,56092.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.25 57776[51:Res:53.1,57775.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.25 57778[52:Spt:57776.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.25 57780[52:Res:57778.0,61.1] always3(s9) || -> . % 76.04/76.25 57781[52:SSi:57780.0,698.0,56091.0] || -> . % 76.04/76.25 57782[52:Spt:57781.0,57776.0,57778.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.25 57783[52:Spt:57781.0,57776.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.25 57787[52:Res:57783.0,61.1] always3(s10) || -> . % 76.04/76.25 57788[52:SSi:57787.0,699.0] || -> . % 76.04/76.25 57789[50:Spt:57788.0,56086.2,56090.0] || xuntil6(s8)*+ -> . % 76.04/76.25 57790[50:Spt:57788.0,56086.0,56086.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.25 57791[50:Res:53.1,57790.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.25 57796[51:Spt:57791.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.25 57798[51:Res:57796.0,61.1] always3(s8) || -> . % 76.04/76.25 57799[51:SSi:57798.0,697.0,56085.0] || -> . % 76.04/76.25 57800[51:Spt:57799.0,57791.0,57796.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.25 57801[51:Spt:57799.0,57791.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.25 57805[51:Res:57801.0,61.1] always3(s9) || -> . % 76.04/76.25 57806[51:SSi:57805.0,698.0] || -> . % 76.04/76.25 57807[49:Spt:57806.0,56083.2,56084.0] || xuntil6(s7)*+ -> . % 76.04/76.25 57808[49:Spt:57806.0,56083.0,56083.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.25 57809[49:Res:53.1,57808.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.25 57811[50:Spt:57809.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.25 57813[50:Res:57811.0,61.1] always3(s7) || -> . % 76.04/76.25 57814[50:SSi:57813.0,696.0,56082.0] || -> . % 76.04/76.25 57815[50:Spt:57814.0,57809.0,57811.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.25 57816[50:Spt:57814.0,57809.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.25 57820[50:Res:57816.0,61.1] always3(s8) || -> . % 76.04/76.25 57821[50:SSi:57820.0,697.0] || -> . % 76.04/76.25 57822[48:Spt:57821.0,56077.2,56081.0] || xuntil6(s6)*+ -> . % 76.04/76.25 57823[48:Spt:57821.0,56077.0,56077.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.25 57824[48:Res:53.1,57823.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.25 57826[49:Spt:57824.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.25 57828[49:Res:57826.0,61.1] always3(s6) || -> . % 76.04/76.25 57829[49:SSi:57828.0,695.0,56076.0] || -> . % 76.04/76.25 57830[49:Spt:57829.0,57824.0,57826.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.25 57831[49:Spt:57829.0,57824.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.25 57835[49:Res:57831.0,61.1] always3(s7) || -> . % 76.04/76.25 57836[49:SSi:57835.0,696.0] || -> . % 76.04/76.25 57837[47:Spt:57836.0,56074.2,56075.0] || xuntil6(s5)*+ -> . % 76.04/76.25 57838[47:Spt:57836.0,56074.0,56074.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.25 57839[47:Res:53.1,57838.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.25 57844[48:Spt:57839.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.25 57846[48:Res:57844.0,61.1] always3(s5) || -> . % 76.04/76.25 57847[48:SSi:57846.0,694.0,56073.0] || -> . % 76.04/76.25 57848[48:Spt:57847.0,57839.0,57844.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.25 57849[48:Spt:57847.0,57839.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.25 57853[48:Res:57849.0,61.1] always3(s6) || -> . % 76.04/76.25 57854[48:SSi:57853.0,695.0] || -> . % 76.04/76.25 57855[46:Spt:57854.0,56068.2,56072.0] || xuntil6(s4)*+ -> . % 76.04/76.25 57856[46:Spt:57854.0,56068.0,56068.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.25 57857[46:Res:53.1,57856.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.25 57859[47:Spt:57857.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.25 57861[47:Res:57859.0,61.1] always3(s4) || -> . % 76.04/76.25 57862[47:SSi:57861.0,693.0,56067.0] || -> . % 76.04/76.25 57863[47:Spt:57862.0,57857.0,57859.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.25 57864[47:Spt:57862.0,57857.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.25 57868[47:Res:57864.0,61.1] always3(s5) || -> . % 76.04/76.25 57869[47:SSi:57868.0,694.0] || -> . % 76.04/76.25 57870[45:Spt:57869.0,56065.2,56066.0] || xuntil6(s3)*+ -> . % 76.04/76.25 57871[45:Spt:57869.0,56065.0,56065.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.25 57872[45:Res:53.1,57871.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.25 57874[46:Spt:57872.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.25 57876[46:Res:57874.0,61.1] always3(s3) || -> . % 76.04/76.25 57877[46:SSi:57876.0,692.0,56064.0] || -> . % 76.04/76.25 57878[46:Spt:57877.0,57872.0,57874.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.25 57879[46:Spt:57877.0,57872.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.25 57883[46:Res:57879.0,61.1] always3(s4) || -> . % 76.04/76.25 57884[46:SSi:57883.0,693.0] || -> . % 76.04/76.25 57885[44:Spt:57884.0,56059.2,56063.0] || xuntil6(s2)*+ -> . % 76.04/76.25 57886[44:Spt:57884.0,56059.0,56059.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.25 57887[44:Res:53.1,57886.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.25 57892[45:Spt:57887.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.25 57894[45:Res:57892.0,61.1] always3(s2) || -> . % 76.04/76.25 57895[45:SSi:57894.0,691.0,56058.0] || -> . % 76.04/76.25 57896[45:Spt:57895.0,57887.0,57892.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.25 57897[45:Spt:57895.0,57887.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.25 57901[45:Res:57897.0,61.1] always3(s3) || -> . % 76.04/76.25 57902[45:SSi:57901.0,692.0] || -> . % 76.04/76.25 57903[43:Spt:57902.0,56053.2,56057.0] || xuntil6(s1)*+ -> . % 76.04/76.25 57904[43:Spt:57902.0,56053.0,56053.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.25 57905[43:Res:53.1,57904.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.25 57907[44:Spt:57905.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.25 57909[44:Res:57907.0,61.1] always3(s1) || -> . % 76.04/76.25 57910[44:SSi:57909.0,690.0,56052.0] || -> . % 76.04/76.25 57911[44:Spt:57910.0,57905.0,57907.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.25 57912[44:Spt:57910.0,57905.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.25 57917[44:Res:57912.0,61.1] always3(s2) || -> . % 76.04/76.25 57918[44:SSi:57917.0,691.0] || -> . % 76.04/76.25 57919[42:Spt:57918.0,74.0,56051.0] || xuntil6(s0)*+ -> . % 76.04/76.25 57920[42:Spt:57918.0,74.1] || -> node4(s0)*. % 76.04/76.25 57921[42:MRR:758.1,57919.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.25 57923[42:Res:57921.0,61.1] always3(s1) || -> . % 76.04/76.25 57924[42:SSi:57923.0,690.0] || -> . % 76.04/76.25 57925[41:Spt:57924.0,56041.0,56045.0] || trans(s49,s10)*+ -> . % 76.04/76.25 57926[41:Spt:57924.0,56041.1,56041.2,56041.3,56041.4,56041.5,56041.6,56041.7,56041.8,56041.9,56041.10] || -> trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.25 57928[41:MRR:56042.0,57925.0] || -> trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.25 57929[41:MRR:56044.1,57925.0] xuntil6(s49) || -> trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.25 57930[42:Spt:57926.0] || -> trans(s49,s9)*. % 76.04/76.25 57931[42:Res:57930.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s9)*. % 76.04/76.25 57933[42:Res:57930.0,60.0] || -> node2(s49,s9)*. % 76.04/76.25 57934[42:SSi:57931.1,50.0,738.0] xuntil6(s49) || -> until2p7(s9)*. % 76.04/76.25 57935[42:Res:57933.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)*. % 76.04/76.25 57936[43:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.25 57937[43:MRR:176.0,57936.0] || -> until5(s1)*. % 76.04/76.25 57938[43:MRR:56490.0,57937.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.25 57945[44:Spt:57938.2] || -> xuntil6(s1)*. % 76.04/76.25 57946[44:MRR:175.0,57945.0] || -> until5(s2)*. % 76.04/76.25 57947[44:MRR:56486.0,57946.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.25 57948[45:Spt:57947.2] || -> xuntil6(s2)*. % 76.04/76.25 57949[45:MRR:174.0,57948.0] || -> until5(s3)*. % 76.04/76.25 57950[45:MRR:56485.0,57949.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.25 57954[46:Spt:57950.2] || -> xuntil6(s3)*. % 76.04/76.25 57955[46:MRR:173.0,57954.0] || -> until5(s4)*. % 76.04/76.25 57956[46:MRR:56478.0,57955.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.25 57957[47:Spt:57956.2] || -> xuntil6(s4)*. % 76.04/76.25 57958[47:MRR:172.0,57957.0] || -> until5(s5)*. % 76.04/76.25 57959[47:MRR:56474.0,57958.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.25 57963[48:Spt:57959.2] || -> xuntil6(s5)*. % 76.04/76.25 57964[48:MRR:171.0,57963.0] || -> until5(s6)*. % 76.04/76.25 57965[48:MRR:56470.0,57964.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.25 57966[49:Spt:57965.2] || -> xuntil6(s6)*. % 76.04/76.25 57967[49:MRR:170.0,57966.0] || -> until5(s7)*. % 76.04/76.25 57968[49:MRR:56466.0,57967.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.25 57972[50:Spt:57968.2] || -> xuntil6(s7)*. % 76.04/76.25 57973[50:MRR:169.0,57972.0] || -> until5(s8)*. % 76.04/76.25 57974[50:MRR:56465.0,57973.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.25 57975[51:Spt:57974.2] || -> xuntil6(s8)*. % 76.04/76.25 57976[51:MRR:168.0,57975.0] || -> until5(s9)*. % 76.04/76.25 57977[51:MRR:56458.0,57976.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.25 57981[52:Spt:57977.2] || -> xuntil6(s9)*. % 76.04/76.25 57982[52:MRR:167.0,57981.0] || -> until5(s10)*. % 76.04/76.25 57983[52:MRR:56454.0,57982.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.25 57984[53:Spt:57983.2] || -> xuntil6(s10)*. % 76.04/76.25 57985[53:MRR:166.0,57984.0] || -> until5(s11)*. % 76.04/76.25 57986[53:MRR:56450.0,57985.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.25 57990[54:Spt:57986.2] || -> xuntil6(s11)*. % 76.04/76.25 57991[54:MRR:165.0,57990.0] || -> until5(s12)*. % 76.04/76.25 57992[54:MRR:56443.0,57991.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.25 57993[55:Spt:57992.2] || -> xuntil6(s12)*. % 76.04/76.25 57994[55:MRR:164.0,57993.0] || -> until5(s13)*. % 76.04/76.25 57995[55:MRR:56439.0,57994.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.25 57999[56:Spt:57995.2] || -> xuntil6(s13)*. % 76.04/76.25 58000[56:MRR:163.0,57999.0] || -> until5(s14)*. % 76.04/76.25 58001[56:MRR:56438.0,58000.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.25 58002[57:Spt:58001.2] || -> xuntil6(s14)*. % 76.04/76.25 58003[57:MRR:162.0,58002.0] || -> until5(s15)*. % 76.04/76.25 58004[57:MRR:56434.0,58003.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.25 58008[58:Spt:58004.2] || -> xuntil6(s15)*. % 76.04/76.25 58009[58:MRR:161.0,58008.0] || -> until5(s16)*. % 76.04/76.25 58010[58:MRR:56427.0,58009.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.25 58011[59:Spt:58010.2] || -> xuntil6(s16)*. % 76.04/76.25 58012[59:MRR:160.0,58011.0] || -> until5(s17)*. % 76.04/76.25 58013[59:MRR:56426.0,58012.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.25 58017[60:Spt:58013.2] || -> xuntil6(s17)*. % 76.04/76.25 58018[60:MRR:159.0,58017.0] || -> until5(s18)*. % 76.04/76.25 58019[60:MRR:56419.0,58018.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.25 58020[61:Spt:58019.2] || -> xuntil6(s18)*. % 76.04/76.25 58021[61:MRR:158.0,58020.0] || -> until5(s19)*. % 76.04/76.25 58022[61:MRR:56415.0,58021.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.25 58026[62:Spt:58022.2] || -> xuntil6(s19)*. % 76.04/76.25 58027[62:MRR:157.0,58026.0] || -> until5(s20)*. % 76.04/76.25 58028[62:MRR:56414.0,58027.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.25 58029[63:Spt:58028.2] || -> xuntil6(s20)*. % 76.04/76.25 58030[63:MRR:156.0,58029.0] || -> until5(s21)*. % 76.04/76.25 58031[63:MRR:56407.0,58030.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.25 58035[64:Spt:58031.2] || -> xuntil6(s21)*. % 76.04/76.25 58036[64:MRR:155.0,58035.0] || -> until5(s22)*. % 76.04/76.25 58037[64:MRR:56403.0,58036.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.25 58038[65:Spt:58037.2] || -> xuntil6(s22)*. % 76.04/76.25 58039[65:MRR:154.0,58038.0] || -> until5(s23)*. % 76.04/76.25 58040[65:MRR:56399.0,58039.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.25 58044[66:Spt:58040.2] || -> xuntil6(s23)*. % 76.04/76.25 58045[66:MRR:153.0,58044.0] || -> until5(s24)*. % 76.04/76.25 58046[66:MRR:56395.0,58045.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.25 58047[67:Spt:58046.2] || -> xuntil6(s24)*. % 76.04/76.25 58048[67:MRR:152.0,58047.0] || -> until5(s25)*. % 76.04/76.25 58049[67:MRR:56394.0,58048.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.25 58053[68:Spt:58049.2] || -> xuntil6(s25)*. % 76.04/76.25 58054[68:MRR:151.0,58053.0] || -> until5(s26)*. % 76.04/76.25 58055[68:MRR:56387.0,58054.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.25 58056[69:Spt:58055.2] || -> xuntil6(s26)*. % 76.04/76.25 58057[69:MRR:150.0,58056.0] || -> until5(s27)*. % 76.04/76.25 58058[69:MRR:56386.0,58057.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.25 58062[70:Spt:58058.2] || -> xuntil6(s27)*. % 76.04/76.25 58063[70:MRR:149.0,58062.0] || -> until5(s28)*. % 76.04/76.25 58064[70:MRR:56385.0,58063.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.25 58065[71:Spt:58064.2] || -> xuntil6(s28)*. % 76.04/76.25 58066[71:MRR:148.0,58065.0] || -> until5(s29)*. % 76.04/76.25 58067[71:MRR:56381.0,58066.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.25 58071[72:Spt:58067.2] || -> xuntil6(s29)*. % 76.04/76.25 58072[72:MRR:147.0,58071.0] || -> until5(s30)*. % 76.04/76.25 58073[72:MRR:56380.0,58072.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.25 58074[73:Spt:58073.2] || -> xuntil6(s30)*. % 76.04/76.25 58075[73:MRR:146.0,58074.0] || -> until5(s31)*. % 76.04/76.25 58076[73:MRR:54645.0,58075.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.25 58080[74:Spt:58076.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.25 58082[74:Res:58080.0,61.1] always3(s32) || -> . % 76.04/76.25 58083[74:SSi:58082.0,721.0] || -> . % 76.04/76.25 58084[74:Spt:58083.0,58076.1,58080.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.04/76.25 58085[74:Spt:58083.0,58076.0,58076.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.04/76.25 58087[74:MRR:825.2,58084.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.04/76.25 58088[74:Res:53.1,58085.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.04/76.25 58090[75:Spt:58088.1] || -> xuntil6(s31)*. % 76.04/76.25 58091[75:MRR:145.0,58090.0] || -> until5(s32)*. % 76.04/76.25 58092[75:MRR:56497.0,58091.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.25 58097[76:Spt:58092.2] || -> xuntil6(s32)*. % 76.04/76.25 58098[76:MRR:144.0,58097.0] || -> until5(s33)*. % 76.04/76.25 58099[76:MRR:54646.0,58098.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.25 58100[77:Spt:58099.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.25 58102[77:Res:58100.0,61.1] always3(s34) || -> . % 76.04/76.25 58103[77:SSi:58102.0,723.0] || -> . % 76.04/76.25 58104[77:Spt:58103.0,58099.1,58100.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.25 58105[77:Spt:58103.0,58099.0,58099.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.25 58107[77:MRR:819.2,58104.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.25 58108[77:Res:53.1,58105.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.25 58110[78:Spt:58108.1] || -> xuntil6(s33)*. % 76.04/76.25 58111[78:MRR:143.0,58110.0] || -> until5(s34)*. % 76.04/76.25 58112[78:MRR:56501.0,58111.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.25 58120[79:Spt:58112.2] || -> xuntil6(s34)*. % 76.04/76.25 58121[79:MRR:142.0,58120.0] || -> until5(s35)*. % 76.04/76.25 58122[79:MRR:54650.0,58121.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.25 58123[80:Spt:58122.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.25 58125[80:Res:58123.0,61.1] always3(s36) || -> . % 76.04/76.25 58126[80:SSi:58125.0,725.0] || -> . % 76.04/76.25 58127[80:Spt:58126.0,58122.1,58123.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.25 58128[80:Spt:58126.0,58122.0,58122.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.25 58130[80:MRR:813.2,58127.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.25 58131[80:Res:53.1,58128.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.25 58136[81:Spt:58131.1] || -> xuntil6(s35)*. % 76.04/76.25 58137[81:MRR:141.0,58136.0] || -> until5(s36)*. % 76.04/76.25 58138[81:MRR:56505.0,58137.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.25 58140[82:Spt:58138.2] || -> xuntil6(s36)*. % 76.04/76.25 58141[82:MRR:140.0,58140.0] || -> until5(s37)*. % 76.04/76.25 58142[82:MRR:54654.0,58141.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.25 58143[83:Spt:58142.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.25 58145[83:Res:58143.0,61.1] always3(s38) || -> . % 76.04/76.25 58146[83:SSi:58145.0,727.0] || -> . % 76.04/76.25 58147[83:Spt:58146.0,58142.1,58143.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.25 58148[83:Spt:58146.0,58142.0,58142.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.25 58150[83:MRR:807.2,58147.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.25 58151[83:Res:53.1,58148.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.25 58153[84:Spt:58151.1] || -> xuntil6(s37)*. % 76.04/76.25 58154[84:MRR:139.0,58153.0] || -> until5(s38)*. % 76.04/76.25 58155[84:MRR:56509.0,58154.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.25 58160[85:Spt:58155.2] || -> xuntil6(s38)*. % 76.04/76.25 58161[85:MRR:138.0,58160.0] || -> until5(s39)*. % 76.04/76.25 58162[85:MRR:54658.0,58161.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.25 58163[86:Spt:58162.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.25 58165[86:Res:58163.0,61.1] always3(s40) || -> . % 76.04/76.25 58166[86:SSi:58165.0,729.0] || -> . % 76.04/76.25 58167[86:Spt:58166.0,58162.1,58163.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.25 58168[86:Spt:58166.0,58162.0,58162.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.25 58170[86:MRR:801.2,58167.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.25 58171[86:Res:53.1,58168.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.25 58173[87:Spt:58171.1] || -> xuntil6(s39)*. % 76.04/76.25 58174[87:MRR:137.0,58173.0] || -> until5(s40)*. % 76.04/76.25 58175[87:MRR:56516.0,58174.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.25 58183[88:Spt:58175.2] || -> xuntil6(s40)*. % 76.04/76.25 58184[88:MRR:136.0,58183.0] || -> until5(s41)*. % 76.04/76.25 58185[88:MRR:54665.0,58184.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.25 58186[89:Spt:58185.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.25 58188[89:Res:58186.0,61.1] always3(s42) || -> . % 76.04/76.25 58189[89:SSi:58188.0,731.0] || -> . % 76.04/76.25 58190[89:Spt:58189.0,58185.1,58186.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.25 58191[89:Spt:58189.0,58185.0,58185.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.25 58193[89:MRR:795.2,58190.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.25 58194[89:Res:53.1,58191.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.25 58199[90:Spt:58194.1] || -> xuntil6(s41)*. % 76.04/76.25 58200[90:MRR:135.0,58199.0] || -> until5(s42)*. % 76.04/76.25 58201[90:MRR:56517.0,58200.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.25 58203[91:Spt:58201.2] || -> xuntil6(s42)*. % 76.04/76.25 58204[91:MRR:134.0,58203.0] || -> until5(s43)*. % 76.04/76.25 58205[91:MRR:54666.0,58204.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.25 58206[92:Spt:58205.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.25 58208[92:Res:58206.0,61.1] always3(s44) || -> . % 76.04/76.25 58209[92:SSi:58208.0,733.0] || -> . % 76.04/76.25 58210[92:Spt:58209.0,58205.1,58206.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.25 58211[92:Spt:58209.0,58205.0,58205.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.25 58213[92:MRR:789.2,58210.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.25 58214[92:Res:53.1,58211.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.25 58216[93:Spt:58214.1] || -> xuntil6(s43)*. % 76.04/76.25 58217[93:MRR:133.0,58216.0] || -> until5(s44)*. % 76.04/76.25 58218[93:MRR:56521.0,58217.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.25 58223[94:Spt:58218.2] || -> xuntil6(s44)*. % 76.04/76.25 58224[94:MRR:132.0,58223.0] || -> until5(s45)*. % 76.04/76.25 58225[94:MRR:54670.0,58224.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.25 58226[95:Spt:58225.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.25 58228[95:Res:58226.0,61.1] always3(s46) || -> . % 76.04/76.25 58229[95:SSi:58228.0,735.0] || -> . % 76.04/76.25 58230[95:Spt:58229.0,58225.1,58226.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.25 58231[95:Spt:58229.0,58225.0,58225.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.25 58233[95:MRR:783.2,58230.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.25 58234[95:Res:53.1,58231.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.25 58236[96:Spt:58234.1] || -> xuntil6(s45)*. % 76.04/76.25 58237[96:MRR:131.0,58236.0] || -> until5(s46)*. % 76.04/76.25 58238[96:MRR:56525.0,58237.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.25 58246[97:Spt:58238.2] || -> xuntil6(s46)*. % 76.04/76.25 58247[97:MRR:130.0,58246.0] || -> until5(s47)*. % 76.04/76.25 58248[97:MRR:54674.0,58247.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.25 58249[98:Spt:58248.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.25 58251[98:Res:58249.0,61.1] always3(s48) || -> . % 76.04/76.25 58252[98:SSi:58251.0,737.0] || -> . % 76.04/76.25 58253[98:Spt:58252.0,58248.1,58249.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.25 58254[98:Spt:58252.0,58248.0,58248.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.25 58256[98:MRR:777.2,58253.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.25 58257[98:Res:53.1,58254.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.25 58262[99:Spt:58257.1] || -> xuntil6(s47)*. % 76.04/76.25 58263[99:MRR:129.0,58262.0] || -> until5(s48)*. % 76.04/76.25 58264[99:MRR:56529.0,58263.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.25 58266[100:Spt:58264.2] || -> xuntil6(s48)*. % 76.04/76.25 58267[100:MRR:128.0,58266.0] || -> until5(s49)*. % 76.04/76.25 58268[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.25 58269[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.25 58270[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.25 58271[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.25 58275[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.25 58276[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.25 58280[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.25 58284[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.25 58288[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.25 58295[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.25 58296[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.25 58306[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.25 58307[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.25 58308[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.25 58315[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.25 58316[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.25 58320[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.25 58327[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.25 58328[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.25 58335[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.25 58339[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.25 58346[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.25 58347[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.25 58351[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.25 58355[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.25 58359[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.25 58366[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.25 58367[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.25 58371[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.25 58375[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.25 58377[42:SoR:57935.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)*. % 76.04/76.25 58382[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.25 58386[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.25 58390[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.25 58397[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.25 58398[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.25 58402[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.25 58406[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.25 58410[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.25 58414[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.25 58415[42:SoR:58377.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)* xuntil6(s49). % 76.04/76.25 58416[100:SSi:58415.0,50.0,738.0,58267.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s9,c_busy)* xuntil6(s49). % 76.04/76.25 58417[101:Spt:58416.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.25 58419[101:Res:58417.0,61.1] always3(s9) || -> . % 76.04/76.25 58420[101:SSi:58419.0,698.0,57976.0,57981.0] || -> . % 76.04/76.25 58421[101:Spt:58420.0,58416.1,58417.0] || m_main_v_state(s9,c_busy)*+ -> . % 76.04/76.25 58422[101:Spt:58420.0,58416.0,58416.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.25 58426[101:MRR:58377.2,58421.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.25 58427[101:Res:53.1,58422.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.25 58429[102:Spt:58427.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.25 58431[102:Res:58429.0,61.1] always3(s49) || -> . % 76.04/76.25 58432[102:SSi:58431.0,50.0,738.0,58267.0] || -> . % 76.04/76.25 58433[102:Spt:58432.0,58427.0,58429.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.25 58434[102:Spt:58432.0,58427.1] || -> xuntil6(s49)*. % 76.04/76.25 58435[102:MRR:57934.0,58434.0] || -> until2p7(s9)*. % 76.04/76.25 58436[102:MRR:205.0,58435.0] || -> until2p7(s10)* node4(s9). % 76.04/76.25 58438[102:MRR:774.2,58433.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.25 58439[103:Spt:58436.0] || -> until2p7(s10)*. % 76.04/76.25 58440[103:MRR:206.0,58439.0] || -> until2p7(s11)* node4(s10). % 76.04/76.25 58441[104:Spt:58440.0] || -> until2p7(s11)*. % 76.04/76.25 58442[104:MRR:207.0,58441.0] || -> until2p7(s12)* node4(s11). % 76.04/76.25 58443[105:Spt:58442.0] || -> until2p7(s12)*. % 76.04/76.25 58444[105:MRR:208.0,58443.0] || -> until2p7(s13)* node4(s12). % 76.04/76.25 58445[106:Spt:58444.0] || -> until2p7(s13)*. % 76.04/76.25 58446[106:MRR:209.0,58445.0] || -> until2p7(s14)* node4(s13). % 76.04/76.25 58447[107:Spt:58446.0] || -> until2p7(s14)*. % 76.04/76.25 58448[107:MRR:210.0,58447.0] || -> until2p7(s15)* node4(s14). % 76.04/76.25 58449[108:Spt:58448.0] || -> until2p7(s15)*. % 76.04/76.25 58450[108:MRR:211.0,58449.0] || -> until2p7(s16)* node4(s15). % 76.04/76.25 58451[109:Spt:58450.0] || -> until2p7(s16)*. % 76.04/76.25 58452[109:MRR:212.0,58451.0] || -> until2p7(s17)* node4(s16). % 76.04/76.25 58453[110:Spt:58452.0] || -> until2p7(s17)*. % 76.04/76.25 58454[110:MRR:213.0,58453.0] || -> until2p7(s18)* node4(s17). % 76.04/76.25 58455[111:Spt:58454.0] || -> until2p7(s18)*. % 76.04/76.25 58456[111:MRR:214.0,58455.0] || -> until2p7(s19)* node4(s18). % 76.04/76.25 58457[112:Spt:58456.0] || -> until2p7(s19)*. % 76.04/76.25 58458[112:MRR:215.0,58457.0] || -> until2p7(s20)* node4(s19). % 76.04/76.25 58459[113:Spt:58458.0] || -> until2p7(s20)*. % 76.04/76.25 58460[113:MRR:216.0,58459.0] || -> until2p7(s21)* node4(s20). % 76.04/76.25 58461[114:Spt:58460.0] || -> until2p7(s21)*. % 76.04/76.25 58462[114:MRR:217.0,58461.0] || -> until2p7(s22)* node4(s21). % 76.04/76.25 58463[115:Spt:58462.0] || -> until2p7(s22)*. % 76.04/76.25 58464[115:MRR:218.0,58463.0] || -> until2p7(s23)* node4(s22). % 76.04/76.25 58465[116:Spt:58464.0] || -> until2p7(s23)*. % 76.04/76.25 58466[116:MRR:219.0,58465.0] || -> until2p7(s24)* node4(s23). % 76.04/76.25 58467[117:Spt:58466.0] || -> until2p7(s24)*. % 76.04/76.25 58468[117:MRR:220.0,58467.0] || -> until2p7(s25)* node4(s24). % 76.04/76.25 58469[118:Spt:58468.0] || -> until2p7(s25)*. % 76.04/76.25 58470[118:MRR:221.0,58469.0] || -> until2p7(s26)* node4(s25). % 76.04/76.25 58471[119:Spt:58470.0] || -> until2p7(s26)*. % 76.04/76.25 58472[119:MRR:222.0,58471.0] || -> until2p7(s27)* node4(s26). % 76.04/76.25 58473[120:Spt:58472.0] || -> until2p7(s27)*. % 76.04/76.25 58474[120:MRR:223.0,58473.0] || -> until2p7(s28)* node4(s27). % 76.04/76.25 58475[121:Spt:58474.0] || -> until2p7(s28)*. % 76.04/76.25 58476[121:MRR:224.0,58475.0] || -> until2p7(s29)* node4(s28). % 76.04/76.25 58477[122:Spt:58476.0] || -> until2p7(s29)*. % 76.04/76.25 58478[122:MRR:225.0,58477.0] || -> until2p7(s30)* node4(s29). % 76.04/76.25 58479[123:Spt:58478.0] || -> until2p7(s30)*. % 76.04/76.25 58480[123:MRR:226.0,58479.0] || -> until2p7(s31)* node4(s30). % 76.04/76.25 58481[124:Spt:58480.0] || -> until2p7(s31)*. % 76.04/76.25 58482[124:MRR:227.0,58481.0] || -> until2p7(s32)* node4(s31). % 76.04/76.25 58483[125:Spt:58482.0] || -> until2p7(s32)*. % 76.04/76.25 58484[125:MRR:228.0,58483.0] || -> until2p7(s33)* node4(s32). % 76.04/76.25 58485[126:Spt:58484.0] || -> until2p7(s33)*. % 76.04/76.25 58486[126:MRR:229.0,58485.0] || -> until2p7(s34)* node4(s33). % 76.04/76.25 58487[127:Spt:58486.0] || -> until2p7(s34)*. % 76.04/76.25 58488[127:MRR:230.0,58487.0] || -> until2p7(s35)* node4(s34). % 76.04/76.25 58489[128:Spt:58488.0] || -> until2p7(s35)*. % 76.04/76.25 58490[128:MRR:231.0,58489.0] || -> until2p7(s36)* node4(s35). % 76.04/76.25 58491[129:Spt:58490.0] || -> until2p7(s36)*. % 76.04/76.25 58492[129:MRR:232.0,58491.0] || -> until2p7(s37)* node4(s36). % 76.04/76.25 58493[130:Spt:58492.0] || -> until2p7(s37)*. % 76.04/76.25 58494[130:MRR:235.0,58493.0] || -> until2p7(s38)* node4(s37). % 76.04/76.25 58495[131:Spt:58494.0] || -> until2p7(s38)*. % 76.04/76.25 58496[131:MRR:236.0,58495.0] || -> until2p7(s39)* node4(s38). % 76.04/76.25 58497[132:Spt:58496.0] || -> until2p7(s39)*. % 76.04/76.25 58498[132:MRR:237.0,58497.0] || -> until2p7(s40)* node4(s39). % 76.04/76.25 58499[133:Spt:58498.0] || -> until2p7(s40)*. % 76.04/76.25 58500[133:MRR:238.0,58499.0] || -> until2p7(s41)* node4(s40). % 76.04/76.25 58501[134:Spt:58500.0] || -> until2p7(s41)*. % 76.04/76.25 58502[134:MRR:239.0,58501.0] || -> until2p7(s42)* node4(s41). % 76.04/76.25 58503[135:Spt:58502.0] || -> until2p7(s42)*. % 76.04/76.25 58504[135:MRR:240.0,58503.0] || -> until2p7(s43)* node4(s42). % 76.04/76.25 58505[136:Spt:58504.0] || -> until2p7(s43)*. % 76.04/76.25 58506[136:MRR:241.0,58505.0] || -> until2p7(s44)* node4(s43). % 76.04/76.25 58507[137:Spt:58506.0] || -> until2p7(s44)*. % 76.04/76.25 58508[137:MRR:539.0,58507.0] || -> until2p7(s45)* node4(s44). % 76.04/76.25 58509[138:Spt:58508.0] || -> until2p7(s45)*. % 76.04/76.25 58510[138:MRR:544.0,58509.0] || -> until2p7(s46)* node4(s45). % 76.04/76.25 58511[139:Spt:58510.0] || -> until2p7(s46)*. % 76.04/76.25 58512[139:MRR:549.0,58511.0] || -> until2p7(s47)* node4(s46). % 76.04/76.25 58513[140:Spt:58512.0] || -> until2p7(s47)*. % 76.04/76.25 58514[140:MRR:554.0,58513.0] || -> until2p7(s48)* node4(s47). % 76.04/76.25 58515[141:Spt:58514.0] || -> until2p7(s48)*. % 76.04/76.25 58516[141:MRR:559.0,58515.0] || -> until2p7(s49)* node4(s48). % 76.04/76.25 58517[142:Spt:58516.0] || -> until2p7(s49)*. % 76.04/76.25 58518[142:MRR:194.0,58517.0] || -> node4(s49)*. % 76.04/76.25 58519[142:MRR:58426.0,58518.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.25 58520[142:Res:53.1,58519.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.25 58522[142:MRR:58520.0,58433.0] || -> . % 76.04/76.25 58523[142:Spt:58522.0,58516.0,58517.0] || until2p7(s49)*+ -> . % 76.04/76.25 58524[142:Spt:58522.0,58516.1] || -> node4(s48)*. % 76.04/76.25 58525[142:MRR:58438.0,58524.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.25 58528[142:Res:53.1,58525.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.25 58530[142:MRR:58528.0,58253.0] || -> . % 76.04/76.25 58531[141:Spt:58530.0,58514.0,58515.0] || until2p7(s48)*+ -> . % 76.04/76.25 58532[141:Spt:58530.0,58514.1] || -> node4(s47)*. % 76.04/76.25 58533[141:MRR:58256.0,58532.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.25 58536[141:Res:53.1,58533.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.25 58539[141:Res:58536.0,61.1] always3(s47) || -> . % 76.04/76.25 58540[141:SSi:58539.0,736.0,58247.0,58262.0,58513.0,58532.0] || -> . % 76.04/76.25 58541[140:Spt:58540.0,58512.0,58513.0] || until2p7(s47)*+ -> . % 76.04/76.25 58542[140:Spt:58540.0,58512.1] || -> node4(s46)*. % 76.04/76.25 58544[140:MRR:780.0,58542.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.25 58564[140:Res:53.1,58544.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.25 58566[140:MRR:58564.0,58230.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.25 58568[140:Res:58566.0,61.1] always3(s47) || -> . % 76.04/76.25 58569[140:SSi:58568.0,736.0,58247.0,58262.0] || -> . % 76.04/76.25 58570[139:Spt:58569.0,58510.0,58511.0] || until2p7(s46)*+ -> . % 76.04/76.25 58571[139:Spt:58569.0,58510.1] || -> node4(s45)*. % 76.04/76.25 58572[139:MRR:58233.0,58571.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.25 58576[139:Res:53.1,58572.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.25 58579[139:Res:58576.0,61.1] always3(s45) || -> . % 76.04/76.25 58580[139:SSi:58579.0,734.0,58224.0,58236.0,58509.0,58571.0] || -> . % 76.04/76.25 58581[138:Spt:58580.0,58508.0,58509.0] || until2p7(s45)*+ -> . % 76.04/76.25 58582[138:Spt:58580.0,58508.1] || -> node4(s44)*. % 76.04/76.25 58584[138:MRR:786.0,58582.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.25 58595[138:Res:53.1,58584.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.25 58597[138:MRR:58595.0,58210.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.25 58599[138:Res:58597.0,61.1] always3(s45) || -> . % 76.04/76.25 58600[138:SSi:58599.0,734.0,58224.0,58236.0] || -> . % 76.04/76.25 58601[137:Spt:58600.0,58506.0,58507.0] || until2p7(s44)*+ -> . % 76.04/76.25 58602[137:Spt:58600.0,58506.1] || -> node4(s43)*. % 76.04/76.25 58603[137:MRR:58213.0,58602.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.25 58606[137:Res:53.1,58603.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.25 58609[137:Res:58606.0,61.1] always3(s43) || -> . % 76.04/76.25 58610[137:SSi:58609.0,732.0,58204.0,58216.0,58505.0,58602.0] || -> . % 76.04/76.25 58611[136:Spt:58610.0,58504.0,58505.0] || until2p7(s43)*+ -> . % 76.04/76.25 58612[136:Spt:58610.0,58504.1] || -> node4(s42)*. % 76.04/76.25 58614[136:MRR:792.0,58612.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.25 58626[136:Res:53.1,58614.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.25 58628[136:MRR:58626.0,58190.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.25 58630[136:Res:58628.0,61.1] always3(s43) || -> . % 76.04/76.25 58631[136:SSi:58630.0,732.0,58204.0,58216.0] || -> . % 76.04/76.25 58632[135:Spt:58631.0,58502.0,58503.0] || until2p7(s42)*+ -> . % 76.04/76.25 58633[135:Spt:58631.0,58502.1] || -> node4(s41)*. % 76.04/76.25 58634[135:MRR:58193.0,58633.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.25 58637[135:Res:53.1,58634.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.25 58640[135:Res:58637.0,61.1] always3(s41) || -> . % 76.04/76.25 58641[135:SSi:58640.0,730.0,58184.0,58199.0,58501.0,58633.0] || -> . % 76.04/76.25 58642[134:Spt:58641.0,58500.0,58501.0] || until2p7(s41)*+ -> . % 76.04/76.25 58643[134:Spt:58641.0,58500.1] || -> node4(s40)*. % 76.04/76.25 58645[134:MRR:798.0,58643.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.25 58657[134:Res:53.1,58645.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.25 58659[134:MRR:58657.0,58167.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.25 58664[134:Res:58659.0,61.1] always3(s41) || -> . % 76.04/76.25 58665[134:SSi:58664.0,730.0,58184.0,58199.0] || -> . % 76.04/76.25 58666[133:Spt:58665.0,58498.0,58499.0] || until2p7(s40)*+ -> . % 76.04/76.25 58667[133:Spt:58665.0,58498.1] || -> node4(s39)*. % 76.04/76.25 58668[133:MRR:58170.0,58667.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.25 58671[133:Res:53.1,58668.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.25 58675[133:Res:58671.0,61.1] always3(s39) || -> . % 76.04/76.25 58676[133:SSi:58675.0,728.0,58161.0,58173.0,58497.0,58667.0] || -> . % 76.04/76.25 58677[132:Spt:58676.0,58496.0,58497.0] || until2p7(s39)*+ -> . % 76.04/76.25 58678[132:Spt:58676.0,58496.1] || -> node4(s38)*. % 76.04/76.25 58680[132:MRR:804.0,58678.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.25 58691[132:Res:53.1,58680.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.25 58693[132:MRR:58691.0,58147.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.25 58695[132:Res:58693.0,61.1] always3(s39) || -> . % 76.04/76.25 58696[132:SSi:58695.0,728.0,58161.0,58173.0] || -> . % 76.04/76.25 58697[131:Spt:58696.0,58494.0,58495.0] || until2p7(s38)*+ -> . % 76.04/76.25 58698[131:Spt:58696.0,58494.1] || -> node4(s37)*. % 76.04/76.25 58699[131:MRR:58150.0,58698.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.25 58703[131:Res:53.1,58699.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.25 58706[131:Res:58703.0,61.1] always3(s37) || -> . % 76.04/76.25 58707[131:SSi:58706.0,726.0,58141.0,58153.0,58493.0,58698.0] || -> . % 76.04/76.25 58708[130:Spt:58707.0,58492.0,58493.0] || until2p7(s37)*+ -> . % 76.04/76.25 58709[130:Spt:58707.0,58492.1] || -> node4(s36)*. % 76.04/76.25 58711[130:MRR:810.0,58709.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.25 58722[130:Res:53.1,58711.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.25 58724[130:MRR:58722.0,58127.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.25 58726[130:Res:58724.0,61.1] always3(s37) || -> . % 76.04/76.25 58727[130:SSi:58726.0,726.0,58141.0,58153.0] || -> . % 76.04/76.25 58728[129:Spt:58727.0,58490.0,58491.0] || until2p7(s36)*+ -> . % 76.04/76.25 58729[129:Spt:58727.0,58490.1] || -> node4(s35)*. % 76.04/76.25 58730[129:MRR:58130.0,58729.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.25 58733[129:Res:53.1,58730.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.25 58736[129:Res:58733.0,61.1] always3(s35) || -> . % 76.04/76.25 58737[129:SSi:58736.0,724.0,58121.0,58136.0,58489.0,58729.0] || -> . % 76.04/76.25 58738[128:Spt:58737.0,58488.0,58489.0] || until2p7(s35)*+ -> . % 76.04/76.25 58739[128:Spt:58737.0,58488.1] || -> node4(s34)*. % 76.04/76.25 58741[128:MRR:816.0,58739.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.25 58753[128:Res:53.1,58741.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.25 58755[128:MRR:58753.0,58104.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.25 58757[128:Res:58755.0,61.1] always3(s35) || -> . % 76.04/76.25 58758[128:SSi:58757.0,724.0,58121.0,58136.0] || -> . % 76.04/76.25 58759[127:Spt:58758.0,58486.0,58487.0] || until2p7(s34)*+ -> . % 76.04/76.25 58760[127:Spt:58758.0,58486.1] || -> node4(s33)*. % 76.04/76.25 58761[127:MRR:58107.0,58760.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.25 58764[127:Res:53.1,58761.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.25 58767[127:Res:58764.0,61.1] always3(s33) || -> . % 76.04/76.25 58768[127:SSi:58767.0,722.0,58098.0,58110.0,58485.0,58760.0] || -> . % 76.04/76.25 58769[126:Spt:58768.0,58484.0,58485.0] || until2p7(s33)*+ -> . % 76.04/76.25 58770[126:Spt:58768.0,58484.1] || -> node4(s32)*. % 76.04/76.25 58772[126:MRR:822.0,58770.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.25 58784[126:Res:53.1,58772.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.25 58786[126:MRR:58784.0,58084.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.25 58791[126:Res:58786.0,61.1] always3(s33) || -> . % 76.04/76.25 58792[126:SSi:58791.0,722.0,58098.0,58110.0] || -> . % 76.04/76.25 58793[125:Spt:58792.0,58482.0,58483.0] || until2p7(s32)*+ -> . % 76.04/76.25 58794[125:Spt:58792.0,58482.1] || -> node4(s31)*. % 76.04/76.25 58795[125:MRR:58087.0,58794.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.04/76.25 58798[125:Res:53.1,58795.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.25 58802[125:Res:58798.0,61.1] always3(s31) || -> . % 76.04/76.25 58803[125:SSi:58802.0,720.0,58075.0,58090.0,58481.0,58794.0] || -> . % 76.04/76.25 58804[124:Spt:58803.0,58480.0,58481.0] || until2p7(s31)*+ -> . % 76.04/76.25 58805[124:Spt:58803.0,58480.1] || -> node4(s30)*. % 76.04/76.25 58807[124:MRR:828.0,58805.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.25 58818[124:Res:53.1,58807.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.25 58820[125:Spt:58818.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.25 58822[125:Res:58820.0,61.1] always3(s30) || -> . % 76.04/76.25 58823[125:SSi:58822.0,719.0,58072.0,58074.0,58479.0,58805.0] || -> . % 76.04/76.25 58824[125:Spt:58823.0,58818.0,58820.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.25 58825[125:Spt:58823.0,58818.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.25 58829[125:Res:58825.0,61.1] always3(s31) || -> . % 76.04/76.25 58830[125:SSi:58829.0,720.0,58075.0,58090.0] || -> . % 76.04/76.25 58831[123:Spt:58830.0,58478.0,58479.0] || until2p7(s30)*+ -> . % 76.04/76.25 58832[123:Spt:58830.0,58478.1] || -> node4(s29)*. % 76.04/76.25 58834[123:MRR:831.0,58832.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.25 58841[123:Res:53.1,58834.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.25 58846[124:Spt:58841.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.25 58848[124:Res:58846.0,61.1] always3(s29) || -> . % 76.04/76.25 58849[124:SSi:58848.0,718.0,58066.0,58071.0,58477.0,58832.0] || -> . % 76.04/76.25 58850[124:Spt:58849.0,58841.0,58846.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.25 58851[124:Spt:58849.0,58841.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.25 58855[124:Res:58851.0,61.1] always3(s30) || -> . % 76.04/76.25 58856[124:SSi:58855.0,719.0,58072.0,58074.0] || -> . % 76.04/76.25 58857[122:Spt:58856.0,58476.0,58477.0] || until2p7(s29)*+ -> . % 76.04/76.25 58858[122:Spt:58856.0,58476.1] || -> node4(s28)*. % 76.04/76.25 58860[122:MRR:834.0,58858.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.25 58863[122:Res:53.1,58860.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.25 58865[123:Spt:58863.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.25 58867[123:Res:58865.0,61.1] always3(s28) || -> . % 76.04/76.25 58868[123:SSi:58867.0,717.0,58063.0,58065.0,58475.0,58858.0] || -> . % 76.04/76.25 58869[123:Spt:58868.0,58863.0,58865.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.25 58870[123:Spt:58868.0,58863.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.25 58874[123:Res:58870.0,61.1] always3(s29) || -> . % 76.04/76.25 58875[123:SSi:58874.0,718.0,58066.0,58071.0] || -> . % 76.04/76.25 58876[121:Spt:58875.0,58474.0,58475.0] || until2p7(s28)*+ -> . % 76.04/76.25 58877[121:Spt:58875.0,58474.1] || -> node4(s27)*. % 76.04/76.25 58879[121:MRR:837.0,58877.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.25 58882[121:Res:53.1,58879.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.25 58884[122:Spt:58882.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.25 58886[122:Res:58884.0,61.1] always3(s27) || -> . % 76.04/76.25 58887[122:SSi:58886.0,716.0,58057.0,58062.0,58473.0,58877.0] || -> . % 76.04/76.25 58888[122:Spt:58887.0,58882.0,58884.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.25 58889[122:Spt:58887.0,58882.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.25 58893[122:Res:58889.0,61.1] always3(s28) || -> . % 76.04/76.25 58894[122:SSi:58893.0,717.0,58063.0,58065.0] || -> . % 76.04/76.25 58895[120:Spt:58894.0,58472.0,58473.0] || until2p7(s27)*+ -> . % 76.04/76.25 58896[120:Spt:58894.0,58472.1] || -> node4(s26)*. % 76.04/76.25 58898[120:MRR:840.0,58896.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.25 58901[120:Res:53.1,58898.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.25 58903[121:Spt:58901.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.25 58905[121:Res:58903.0,61.1] always3(s26) || -> . % 76.04/76.25 58906[121:SSi:58905.0,715.0,58054.0,58056.0,58471.0,58896.0] || -> . % 76.04/76.25 58907[121:Spt:58906.0,58901.0,58903.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.25 58908[121:Spt:58906.0,58901.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.25 58912[121:Res:58908.0,61.1] always3(s27) || -> . % 76.04/76.25 58913[121:SSi:58912.0,716.0,58057.0,58062.0] || -> . % 76.04/76.25 58914[119:Spt:58913.0,58470.0,58471.0] || until2p7(s26)*+ -> . % 76.04/76.25 58915[119:Spt:58913.0,58470.1] || -> node4(s25)*. % 76.04/76.25 58917[119:MRR:843.0,58915.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.25 58920[119:Res:53.1,58917.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.25 58925[120:Spt:58920.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.25 58927[120:Res:58925.0,61.1] always3(s25) || -> . % 76.04/76.25 58928[120:SSi:58927.0,714.0,58048.0,58053.0,58469.0,58915.0] || -> . % 76.04/76.25 58929[120:Spt:58928.0,58920.0,58925.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.25 58930[120:Spt:58928.0,58920.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.25 58934[120:Res:58930.0,61.1] always3(s26) || -> . % 76.04/76.25 58935[120:SSi:58934.0,715.0,58054.0,58056.0] || -> . % 76.04/76.25 58936[118:Spt:58935.0,58468.0,58469.0] || until2p7(s25)*+ -> . % 76.04/76.25 58937[118:Spt:58935.0,58468.1] || -> node4(s24)*. % 76.04/76.25 58939[118:MRR:846.0,58937.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.25 58942[118:Res:53.1,58939.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.25 58944[119:Spt:58942.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.25 58946[119:Res:58944.0,61.1] always3(s24) || -> . % 76.04/76.25 58947[119:SSi:58946.0,713.0,58045.0,58047.0,58467.0,58937.0] || -> . % 76.04/76.25 58948[119:Spt:58947.0,58942.0,58944.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.25 58949[119:Spt:58947.0,58942.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.25 58953[119:Res:58949.0,61.1] always3(s25) || -> . % 76.04/76.25 58954[119:SSi:58953.0,714.0,58048.0,58053.0] || -> . % 76.04/76.25 58955[117:Spt:58954.0,58466.0,58467.0] || until2p7(s24)*+ -> . % 76.04/76.25 58956[117:Spt:58954.0,58466.1] || -> node4(s23)*. % 76.04/76.25 58958[117:MRR:849.0,58956.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.25 58961[117:Res:53.1,58958.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.25 58963[118:Spt:58961.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.25 58965[118:Res:58963.0,61.1] always3(s23) || -> . % 76.04/76.25 58966[118:SSi:58965.0,712.0,58039.0,58044.0,58465.0,58956.0] || -> . % 76.04/76.25 58967[118:Spt:58966.0,58961.0,58963.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.25 58968[118:Spt:58966.0,58961.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.25 58972[118:Res:58968.0,61.1] always3(s24) || -> . % 76.04/76.25 58973[118:SSi:58972.0,713.0,58045.0,58047.0] || -> . % 76.04/76.25 58974[116:Spt:58973.0,58464.0,58465.0] || until2p7(s23)*+ -> . % 76.04/76.25 58975[116:Spt:58973.0,58464.1] || -> node4(s22)*. % 76.04/76.25 58977[116:MRR:852.0,58975.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.25 58980[116:Res:53.1,58977.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.25 58982[117:Spt:58980.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.25 58984[117:Res:58982.0,61.1] always3(s22) || -> . % 76.04/76.25 58985[117:SSi:58984.0,711.0,58036.0,58038.0,58463.0,58975.0] || -> . % 76.04/76.25 58986[117:Spt:58985.0,58980.0,58982.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.25 58987[117:Spt:58985.0,58980.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.25 58991[117:Res:58987.0,61.1] always3(s23) || -> . % 76.04/76.25 58992[117:SSi:58991.0,712.0,58039.0,58044.0] || -> . % 76.04/76.25 58993[115:Spt:58992.0,58462.0,58463.0] || until2p7(s22)*+ -> . % 76.04/76.25 58994[115:Spt:58992.0,58462.1] || -> node4(s21)*. % 76.04/76.25 58996[115:MRR:855.0,58994.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.25 58999[115:Res:53.1,58996.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.25 59004[116:Spt:58999.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.25 59006[116:Res:59004.0,61.1] always3(s21) || -> . % 76.04/76.25 59007[116:SSi:59006.0,710.0,58030.0,58035.0,58461.0,58994.0] || -> . % 76.04/76.25 59008[116:Spt:59007.0,58999.0,59004.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.25 59009[116:Spt:59007.0,58999.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.25 59013[116:Res:59009.0,61.1] always3(s22) || -> . % 76.04/76.25 59014[116:SSi:59013.0,711.0,58036.0,58038.0] || -> . % 76.04/76.25 59015[114:Spt:59014.0,58460.0,58461.0] || until2p7(s21)*+ -> . % 76.04/76.25 59016[114:Spt:59014.0,58460.1] || -> node4(s20)*. % 76.04/76.25 59018[114:MRR:858.0,59016.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.25 59021[114:Res:53.1,59018.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.25 59023[115:Spt:59021.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.25 59025[115:Res:59023.0,61.1] always3(s20) || -> . % 76.04/76.25 59026[115:SSi:59025.0,709.0,58027.0,58029.0,58459.0,59016.0] || -> . % 76.04/76.25 59027[115:Spt:59026.0,59021.0,59023.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.25 59028[115:Spt:59026.0,59021.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.25 59032[115:Res:59028.0,61.1] always3(s21) || -> . % 76.04/76.25 59033[115:SSi:59032.0,710.0,58030.0,58035.0] || -> . % 76.04/76.25 59034[113:Spt:59033.0,58458.0,58459.0] || until2p7(s20)*+ -> . % 76.04/76.25 59035[113:Spt:59033.0,58458.1] || -> node4(s19)*. % 76.04/76.25 59037[113:MRR:861.0,59035.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.25 59040[113:Res:53.1,59037.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.25 59042[114:Spt:59040.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.25 59044[114:Res:59042.0,61.1] always3(s19) || -> . % 76.04/76.25 59045[114:SSi:59044.0,708.0,58021.0,58026.0,58457.0,59035.0] || -> . % 76.04/76.25 59046[114:Spt:59045.0,59040.0,59042.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.25 59047[114:Spt:59045.0,59040.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.25 59051[114:Res:59047.0,61.1] always3(s20) || -> . % 76.04/76.25 59052[114:SSi:59051.0,709.0,58027.0,58029.0] || -> . % 76.04/76.25 59053[112:Spt:59052.0,58456.0,58457.0] || until2p7(s19)*+ -> . % 76.04/76.25 59054[112:Spt:59052.0,58456.1] || -> node4(s18)*. % 76.04/76.25 59056[112:MRR:864.0,59054.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.25 59059[112:Res:53.1,59056.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.25 59061[113:Spt:59059.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.25 59063[113:Res:59061.0,61.1] always3(s18) || -> . % 76.04/76.25 59064[113:SSi:59063.0,707.0,58018.0,58020.0,58455.0,59054.0] || -> . % 76.04/76.25 59065[113:Spt:59064.0,59059.0,59061.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.25 59066[113:Spt:59064.0,59059.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.25 59070[113:Res:59066.0,61.1] always3(s19) || -> . % 76.04/76.25 59071[113:SSi:59070.0,708.0,58021.0,58026.0] || -> . % 76.04/76.25 59072[111:Spt:59071.0,58454.0,58455.0] || until2p7(s18)*+ -> . % 76.04/76.25 59073[111:Spt:59071.0,58454.1] || -> node4(s17)*. % 76.04/76.25 59075[111:MRR:867.0,59073.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.25 59078[111:Res:53.1,59075.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.25 59083[112:Spt:59078.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.25 59085[112:Res:59083.0,61.1] always3(s17) || -> . % 76.04/76.25 59086[112:SSi:59085.0,706.0,58012.0,58017.0,58453.0,59073.0] || -> . % 76.04/76.25 59087[112:Spt:59086.0,59078.0,59083.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.25 59088[112:Spt:59086.0,59078.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.25 59092[112:Res:59088.0,61.1] always3(s18) || -> . % 76.04/76.25 59093[112:SSi:59092.0,707.0,58018.0,58020.0] || -> . % 76.04/76.25 59094[110:Spt:59093.0,58452.0,58453.0] || until2p7(s17)*+ -> . % 76.04/76.25 59095[110:Spt:59093.0,58452.1] || -> node4(s16)*. % 76.04/76.25 59097[110:MRR:870.0,59095.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.25 59100[110:Res:53.1,59097.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.25 59102[111:Spt:59100.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.25 59104[111:Res:59102.0,61.1] always3(s16) || -> . % 76.04/76.25 59105[111:SSi:59104.0,705.0,58009.0,58011.0,58451.0,59095.0] || -> . % 76.04/76.25 59106[111:Spt:59105.0,59100.0,59102.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.25 59107[111:Spt:59105.0,59100.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.25 59111[111:Res:59107.0,61.1] always3(s17) || -> . % 76.04/76.25 59112[111:SSi:59111.0,706.0,58012.0,58017.0] || -> . % 76.04/76.25 59113[109:Spt:59112.0,58450.0,58451.0] || until2p7(s16)*+ -> . % 76.04/76.25 59114[109:Spt:59112.0,58450.1] || -> node4(s15)*. % 76.04/76.25 59116[109:MRR:873.0,59114.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.25 59119[109:Res:53.1,59116.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.25 59121[110:Spt:59119.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.25 59123[110:Res:59121.0,61.1] always3(s15) || -> . % 76.04/76.25 59124[110:SSi:59123.0,704.0,58003.0,58008.0,58449.0,59114.0] || -> . % 76.04/76.25 59125[110:Spt:59124.0,59119.0,59121.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.25 59126[110:Spt:59124.0,59119.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.25 59130[110:Res:59126.0,61.1] always3(s16) || -> . % 76.04/76.25 59131[110:SSi:59130.0,705.0,58009.0,58011.0] || -> . % 76.04/76.25 59132[108:Spt:59131.0,58448.0,58449.0] || until2p7(s15)*+ -> . % 76.04/76.25 59133[108:Spt:59131.0,58448.1] || -> node4(s14)*. % 76.04/76.25 59135[108:MRR:876.0,59133.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.25 59138[108:Res:53.1,59135.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.25 59140[109:Spt:59138.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.25 59142[109:Res:59140.0,61.1] always3(s14) || -> . % 76.04/76.25 59143[109:SSi:59142.0,703.0,58000.0,58002.0,58447.0,59133.0] || -> . % 76.04/76.25 59144[109:Spt:59143.0,59138.0,59140.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.25 59145[109:Spt:59143.0,59138.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.25 59149[109:Res:59145.0,61.1] always3(s15) || -> . % 76.04/76.25 59150[109:SSi:59149.0,704.0,58003.0,58008.0] || -> . % 76.04/76.25 59151[107:Spt:59150.0,58446.0,58447.0] || until2p7(s14)*+ -> . % 76.04/76.25 59152[107:Spt:59150.0,58446.1] || -> node4(s13)*. % 76.04/76.25 59154[107:MRR:879.0,59152.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.25 59157[107:Res:53.1,59154.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.25 59162[108:Spt:59157.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.25 59164[108:Res:59162.0,61.1] always3(s13) || -> . % 76.04/76.25 59165[108:SSi:59164.0,702.0,57994.0,57999.0,58445.0,59152.0] || -> . % 76.04/76.25 59166[108:Spt:59165.0,59157.0,59162.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.25 59167[108:Spt:59165.0,59157.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.25 59171[108:Res:59167.0,61.1] always3(s14) || -> . % 76.04/76.25 59172[108:SSi:59171.0,703.0,58000.0,58002.0] || -> . % 76.04/76.25 59173[106:Spt:59172.0,58444.0,58445.0] || until2p7(s13)*+ -> . % 76.04/76.25 59174[106:Spt:59172.0,58444.1] || -> node4(s12)*. % 76.04/76.25 59176[106:MRR:882.0,59174.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.25 59179[106:Res:53.1,59176.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.25 59181[107:Spt:59179.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.25 59183[107:Res:59181.0,61.1] always3(s12) || -> . % 76.04/76.25 59184[107:SSi:59183.0,701.0,57991.0,57993.0,58443.0,59174.0] || -> . % 76.04/76.25 59185[107:Spt:59184.0,59179.0,59181.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.25 59186[107:Spt:59184.0,59179.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.25 59190[107:Res:59186.0,61.1] always3(s13) || -> . % 76.04/76.25 59191[107:SSi:59190.0,702.0,57994.0,57999.0] || -> . % 76.04/76.25 59192[105:Spt:59191.0,58442.0,58443.0] || until2p7(s12)*+ -> . % 76.04/76.25 59193[105:Spt:59191.0,58442.1] || -> node4(s11)*. % 76.04/76.25 59195[105:MRR:885.0,59193.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.25 59198[105:Res:53.1,59195.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.25 59200[106:Spt:59198.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.25 59202[106:Res:59200.0,61.1] always3(s11) || -> . % 76.04/76.25 59203[106:SSi:59202.0,700.0,57985.0,57990.0,58441.0,59193.0] || -> . % 76.04/76.25 59204[106:Spt:59203.0,59198.0,59200.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.25 59205[106:Spt:59203.0,59198.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.25 59209[106:Res:59205.0,61.1] always3(s12) || -> . % 76.04/76.25 59210[106:SSi:59209.0,701.0,57991.0,57993.0] || -> . % 76.04/76.25 59211[104:Spt:59210.0,58440.0,58441.0] || until2p7(s11)*+ -> . % 76.04/76.25 59212[104:Spt:59210.0,58440.1] || -> node4(s10)*. % 76.04/76.25 59214[104:MRR:888.0,59212.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.25 59217[104:Res:53.1,59214.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.25 59219[105:Spt:59217.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.25 59221[105:Res:59219.0,61.1] always3(s10) || -> . % 76.04/76.25 59222[105:SSi:59221.0,699.0,57982.0,57984.0,58439.0,59212.0] || -> . % 76.04/76.25 59223[105:Spt:59222.0,59217.0,59219.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.25 59224[105:Spt:59222.0,59217.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.25 59228[105:Res:59224.0,61.1] always3(s11) || -> . % 76.04/76.25 59229[105:SSi:59228.0,700.0,57985.0,57990.0] || -> . % 76.04/76.25 59230[103:Spt:59229.0,58436.0,58439.0] || until2p7(s10)*+ -> . % 76.04/76.25 59231[103:Spt:59229.0,58436.1] || -> node4(s9)*. % 76.04/76.25 59233[103:MRR:891.0,59231.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.25 59236[103:Res:53.1,59233.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.25 59238[103:MRR:59236.0,58421.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.25 59243[103:Res:59238.0,61.1] always3(s10) || -> . % 76.04/76.25 59244[103:SSi:59243.0,699.0,57982.0,57984.0] || -> . % 76.04/76.25 59245[100:Spt:59244.0,58264.2,58266.0] || xuntil6(s48)*+ -> . % 76.04/76.25 59246[100:Spt:59244.0,58264.0,58264.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.25 59247[100:Res:53.1,59246.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.25 59249[100:MRR:59247.0,58253.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.25 59251[100:Res:59249.0,61.1] always3(s49) || -> . % 76.04/76.25 59252[100:SSi:59251.0,50.0,738.0] || -> . % 76.04/76.25 59253[99:Spt:59252.0,58257.1,58262.0] || xuntil6(s47)* -> . % 76.04/76.25 59254[99:Spt:59252.0,58257.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.25 59257[99:Res:59254.0,61.1] always3(s47) || -> . % 76.04/76.25 59258[99:SSi:59257.0,736.0,58247.0] || -> . % 76.04/76.25 59259[97:Spt:59258.0,58238.2,58246.0] || xuntil6(s46)*+ -> . % 76.04/76.25 59260[97:Spt:59258.0,58238.0,58238.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.25 59261[97:Res:53.1,59260.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.25 59263[97:MRR:59261.0,58230.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.25 59266[97:Res:59263.0,61.1] always3(s47) || -> . % 76.04/76.25 59267[97:SSi:59266.0,736.0] || -> . % 76.04/76.25 59268[96:Spt:59267.0,58234.1,58236.0] || xuntil6(s45)* -> . % 76.04/76.25 59269[96:Spt:59267.0,58234.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.25 59272[96:Res:59269.0,61.1] always3(s45) || -> . % 76.04/76.25 59273[96:SSi:59272.0,734.0,58224.0] || -> . % 76.04/76.25 59274[94:Spt:59273.0,58218.2,58223.0] || xuntil6(s44)*+ -> . % 76.04/76.25 59275[94:Spt:59273.0,58218.0,58218.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.25 59276[94:Res:53.1,59275.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.25 59278[94:MRR:59276.0,58210.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.25 59280[94:Res:59278.0,61.1] always3(s45) || -> . % 76.04/76.25 59281[94:SSi:59280.0,734.0] || -> . % 76.04/76.25 59282[93:Spt:59281.0,58214.1,58216.0] || xuntil6(s43)* -> . % 76.04/76.25 59283[93:Spt:59281.0,58214.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.25 59286[93:Res:59283.0,61.1] always3(s43) || -> . % 76.04/76.25 59287[93:SSi:59286.0,732.0,58204.0] || -> . % 76.04/76.25 59288[91:Spt:59287.0,58201.2,58203.0] || xuntil6(s42)*+ -> . % 76.04/76.25 59289[91:Spt:59287.0,58201.0,58201.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.25 59290[91:Res:53.1,59289.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.25 59292[91:MRR:59290.0,58190.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.25 59295[91:Res:59292.0,61.1] always3(s43) || -> . % 76.04/76.25 59296[91:SSi:59295.0,732.0] || -> . % 76.04/76.25 59297[90:Spt:59296.0,58194.1,58199.0] || xuntil6(s41)* -> . % 76.04/76.25 59298[90:Spt:59296.0,58194.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.25 59301[90:Res:59298.0,61.1] always3(s41) || -> . % 76.04/76.25 59302[90:SSi:59301.0,730.0,58184.0] || -> . % 76.04/76.25 59303[88:Spt:59302.0,58175.2,58183.0] || xuntil6(s40)*+ -> . % 76.04/76.25 59304[88:Spt:59302.0,58175.0,58175.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.25 59305[88:Res:53.1,59304.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.25 59307[88:MRR:59305.0,58167.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.25 59309[88:Res:59307.0,61.1] always3(s41) || -> . % 76.04/76.25 59310[88:SSi:59309.0,730.0] || -> . % 76.04/76.25 59311[87:Spt:59310.0,58171.1,58173.0] || xuntil6(s39)* -> . % 76.04/76.25 59312[87:Spt:59310.0,58171.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.25 59315[87:Res:59312.0,61.1] always3(s39) || -> . % 76.04/76.25 59316[87:SSi:59315.0,728.0,58161.0] || -> . % 76.04/76.25 59317[85:Spt:59316.0,58155.2,58160.0] || xuntil6(s38)*+ -> . % 76.04/76.25 59318[85:Spt:59316.0,58155.0,58155.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.25 59319[85:Res:53.1,59318.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.25 59321[85:MRR:59319.0,58147.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.25 59323[85:Res:59321.0,61.1] always3(s39) || -> . % 76.04/76.25 59324[85:SSi:59323.0,728.0] || -> . % 76.04/76.25 59325[84:Spt:59324.0,58151.1,58153.0] || xuntil6(s37)* -> . % 76.04/76.25 59326[84:Spt:59324.0,58151.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.25 59329[84:Res:59326.0,61.1] always3(s37) || -> . % 76.04/76.25 59330[84:SSi:59329.0,726.0,58141.0] || -> . % 76.04/76.25 59331[82:Spt:59330.0,58138.2,58140.0] || xuntil6(s36)*+ -> . % 76.04/76.25 59332[82:Spt:59330.0,58138.0,58138.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.25 59333[82:Res:53.1,59332.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.25 59335[82:MRR:59333.0,58127.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.25 59337[82:Res:59335.0,61.1] always3(s37) || -> . % 76.04/76.25 59338[82:SSi:59337.0,726.0] || -> . % 76.04/76.25 59339[81:Spt:59338.0,58131.1,58136.0] || xuntil6(s35)* -> . % 76.04/76.25 59340[81:Spt:59338.0,58131.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.25 59343[81:Res:59340.0,61.1] always3(s35) || -> . % 76.04/76.25 59344[81:SSi:59343.0,724.0,58121.0] || -> . % 76.04/76.25 59345[79:Spt:59344.0,58112.2,58120.0] || xuntil6(s34)*+ -> . % 76.04/76.25 59346[79:Spt:59344.0,58112.0,58112.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.25 59347[79:Res:53.1,59346.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.25 59349[79:MRR:59347.0,58104.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.25 59351[79:Res:59349.0,61.1] always3(s35) || -> . % 76.04/76.25 59352[79:SSi:59351.0,724.0] || -> . % 76.04/76.25 59353[78:Spt:59352.0,58108.1,58110.0] || xuntil6(s33)* -> . % 76.04/76.25 59354[78:Spt:59352.0,58108.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.25 59357[78:Res:59354.0,61.1] always3(s33) || -> . % 76.04/76.25 59358[78:SSi:59357.0,722.0,58098.0] || -> . % 76.04/76.25 59359[76:Spt:59358.0,58092.2,58097.0] || xuntil6(s32)*+ -> . % 76.04/76.25 59360[76:Spt:59358.0,58092.0,58092.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.25 59361[76:Res:53.1,59360.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.25 59363[76:MRR:59361.0,58084.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.25 59365[76:Res:59363.0,61.1] always3(s33) || -> . % 76.04/76.25 59366[76:SSi:59365.0,722.0] || -> . % 76.04/76.25 59367[75:Spt:59366.0,58088.1,58090.0] || xuntil6(s31)* -> . % 76.04/76.25 59368[75:Spt:59366.0,58088.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.25 59371[75:Res:59368.0,61.1] always3(s31) || -> . % 76.04/76.25 59372[75:SSi:59371.0,720.0,58075.0] || -> . % 76.04/76.25 59373[73:Spt:59372.0,58073.2,58074.0] || xuntil6(s30)*+ -> . % 76.04/76.25 59374[73:Spt:59372.0,58073.0,58073.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.25 59375[73:Res:53.1,59374.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.25 59377[74:Spt:59375.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.25 59379[74:Res:59377.0,61.1] always3(s31) || -> . % 76.04/76.25 59380[74:SSi:59379.0,720.0] || -> . % 76.04/76.25 59381[74:Spt:59380.0,59375.1,59377.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.25 59382[74:Spt:59380.0,59375.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.25 59385[74:Res:59382.0,61.1] always3(s30) || -> . % 76.04/76.25 59386[74:SSi:59385.0,719.0,58072.0] || -> . % 76.04/76.25 59387[72:Spt:59386.0,58067.2,58071.0] || xuntil6(s29)*+ -> . % 76.04/76.25 59388[72:Spt:59386.0,58067.0,58067.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.25 59389[72:Res:53.1,59388.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.25 59391[73:Spt:59389.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.25 59393[73:Res:59391.0,61.1] always3(s30) || -> . % 76.04/76.25 59394[73:SSi:59393.0,719.0] || -> . % 76.04/76.25 59395[73:Spt:59394.0,59389.1,59391.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.25 59396[73:Spt:59394.0,59389.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.25 59399[73:Res:59396.0,61.1] always3(s29) || -> . % 76.04/76.25 59400[73:SSi:59399.0,718.0,58066.0] || -> . % 76.04/76.25 59401[71:Spt:59400.0,58064.2,58065.0] || xuntil6(s28)*+ -> . % 76.04/76.25 59402[71:Spt:59400.0,58064.0,58064.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.25 59403[71:Res:53.1,59402.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.25 59405[72:Spt:59403.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.25 59407[72:Res:59405.0,61.1] always3(s29) || -> . % 76.04/76.25 59408[72:SSi:59407.0,718.0] || -> . % 76.04/76.25 59409[72:Spt:59408.0,59403.1,59405.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.25 59410[72:Spt:59408.0,59403.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.25 59413[72:Res:59410.0,61.1] always3(s28) || -> . % 76.04/76.25 59414[72:SSi:59413.0,717.0,58063.0] || -> . % 76.04/76.25 59415[70:Spt:59414.0,58058.2,58062.0] || xuntil6(s27)*+ -> . % 76.04/76.25 59416[70:Spt:59414.0,58058.0,58058.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.25 59417[70:Res:53.1,59416.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.25 59419[71:Spt:59417.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.25 59421[71:Res:59419.0,61.1] always3(s28) || -> . % 76.04/76.25 59422[71:SSi:59421.0,717.0] || -> . % 76.04/76.25 59423[71:Spt:59422.0,59417.1,59419.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.25 59424[71:Spt:59422.0,59417.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.25 59427[71:Res:59424.0,61.1] always3(s27) || -> . % 76.04/76.25 59428[71:SSi:59427.0,716.0,58057.0] || -> . % 76.04/76.25 59429[69:Spt:59428.0,58055.2,58056.0] || xuntil6(s26)*+ -> . % 76.04/76.25 59430[69:Spt:59428.0,58055.0,58055.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.25 59431[69:Res:53.1,59430.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.25 59433[70:Spt:59431.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.25 59435[70:Res:59433.0,61.1] always3(s27) || -> . % 76.04/76.25 59436[70:SSi:59435.0,716.0] || -> . % 76.04/76.25 59437[70:Spt:59436.0,59431.1,59433.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.25 59438[70:Spt:59436.0,59431.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.25 59441[70:Res:59438.0,61.1] always3(s26) || -> . % 76.04/76.25 59442[70:SSi:59441.0,715.0,58054.0] || -> . % 76.04/76.25 59443[68:Spt:59442.0,58049.2,58053.0] || xuntil6(s25)*+ -> . % 76.04/76.25 59444[68:Spt:59442.0,58049.0,58049.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.25 59445[68:Res:53.1,59444.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.25 59447[69:Spt:59445.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.25 59449[69:Res:59447.0,61.1] always3(s26) || -> . % 76.04/76.25 59450[69:SSi:59449.0,715.0] || -> . % 76.04/76.25 59451[69:Spt:59450.0,59445.1,59447.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.25 59452[69:Spt:59450.0,59445.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.25 59455[69:Res:59452.0,61.1] always3(s25) || -> . % 76.04/76.25 59456[69:SSi:59455.0,714.0,58048.0] || -> . % 76.04/76.25 59457[67:Spt:59456.0,58046.2,58047.0] || xuntil6(s24)*+ -> . % 76.04/76.25 59458[67:Spt:59456.0,58046.0,58046.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.25 59459[67:Res:53.1,59458.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.25 59461[68:Spt:59459.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.25 59463[68:Res:59461.0,61.1] always3(s25) || -> . % 76.04/76.25 59464[68:SSi:59463.0,714.0] || -> . % 76.04/76.25 59465[68:Spt:59464.0,59459.1,59461.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.25 59466[68:Spt:59464.0,59459.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.25 59469[68:Res:59466.0,61.1] always3(s24) || -> . % 76.04/76.25 59470[68:SSi:59469.0,713.0,58045.0] || -> . % 76.04/76.25 59471[66:Spt:59470.0,58040.2,58044.0] || xuntil6(s23)*+ -> . % 76.04/76.25 59472[66:Spt:59470.0,58040.0,58040.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.25 59473[66:Res:53.1,59472.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.25 59475[67:Spt:59473.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.25 59477[67:Res:59475.0,61.1] always3(s24) || -> . % 76.04/76.25 59478[67:SSi:59477.0,713.0] || -> . % 76.04/76.25 59479[67:Spt:59478.0,59473.1,59475.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.25 59480[67:Spt:59478.0,59473.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.25 59483[67:Res:59480.0,61.1] always3(s23) || -> . % 76.04/76.25 59484[67:SSi:59483.0,712.0,58039.0] || -> . % 76.04/76.25 59485[65:Spt:59484.0,58037.2,58038.0] || xuntil6(s22)*+ -> . % 76.04/76.25 59486[65:Spt:59484.0,58037.0,58037.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.25 59487[65:Res:53.1,59486.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.25 59489[66:Spt:59487.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.25 59491[66:Res:59489.0,61.1] always3(s23) || -> . % 76.04/76.25 59492[66:SSi:59491.0,712.0] || -> . % 76.04/76.25 59493[66:Spt:59492.0,59487.1,59489.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.25 59494[66:Spt:59492.0,59487.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.25 59497[66:Res:59494.0,61.1] always3(s22) || -> . % 76.04/76.25 59498[66:SSi:59497.0,711.0,58036.0] || -> . % 76.04/76.25 59499[64:Spt:59498.0,58031.2,58035.0] || xuntil6(s21)*+ -> . % 76.04/76.25 59500[64:Spt:59498.0,58031.0,58031.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.25 59501[64:Res:53.1,59500.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.25 59503[65:Spt:59501.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.25 59505[65:Res:59503.0,61.1] always3(s22) || -> . % 76.04/76.25 59506[65:SSi:59505.0,711.0] || -> . % 76.04/76.25 59507[65:Spt:59506.0,59501.1,59503.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.25 59508[65:Spt:59506.0,59501.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.25 59511[65:Res:59508.0,61.1] always3(s21) || -> . % 76.04/76.25 59512[65:SSi:59511.0,710.0,58030.0] || -> . % 76.04/76.25 59513[63:Spt:59512.0,58028.2,58029.0] || xuntil6(s20)*+ -> . % 76.04/76.25 59514[63:Spt:59512.0,58028.0,58028.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.25 59515[63:Res:53.1,59514.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.25 59520[64:Spt:59515.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.25 59522[64:Res:59520.0,61.1] always3(s20) || -> . % 76.04/76.25 59523[64:SSi:59522.0,709.0,58027.0] || -> . % 76.04/76.25 59524[64:Spt:59523.0,59515.0,59520.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.25 59525[64:Spt:59523.0,59515.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.25 59529[64:Res:59525.0,61.1] always3(s21) || -> . % 76.04/76.25 59530[64:SSi:59529.0,710.0] || -> . % 76.04/76.25 59531[62:Spt:59530.0,58022.2,58026.0] || xuntil6(s19)*+ -> . % 76.04/76.25 59532[62:Spt:59530.0,58022.0,58022.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.25 59533[62:Res:53.1,59532.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.25 59535[63:Spt:59533.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.25 59537[63:Res:59535.0,61.1] always3(s20) || -> . % 76.04/76.25 59538[63:SSi:59537.0,709.0] || -> . % 76.04/76.25 59539[63:Spt:59538.0,59533.1,59535.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.25 59540[63:Spt:59538.0,59533.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.25 59543[63:Res:59540.0,61.1] always3(s19) || -> . % 76.04/76.25 59544[63:SSi:59543.0,708.0,58021.0] || -> . % 76.04/76.25 59545[61:Spt:59544.0,58019.2,58020.0] || xuntil6(s18)*+ -> . % 76.04/76.25 59546[61:Spt:59544.0,58019.0,58019.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.25 59547[61:Res:53.1,59546.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.25 59549[62:Spt:59547.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.25 59551[62:Res:59549.0,61.1] always3(s19) || -> . % 76.04/76.25 59552[62:SSi:59551.0,708.0] || -> . % 76.04/76.25 59553[62:Spt:59552.0,59547.1,59549.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.25 59554[62:Spt:59552.0,59547.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.25 59557[62:Res:59554.0,61.1] always3(s18) || -> . % 76.04/76.25 59558[62:SSi:59557.0,707.0,58018.0] || -> . % 76.04/76.25 59559[60:Spt:59558.0,58013.2,58017.0] || xuntil6(s17)*+ -> . % 76.04/76.25 59560[60:Spt:59558.0,58013.0,58013.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.25 59561[60:Res:53.1,59560.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.25 59566[61:Spt:59561.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.25 59568[61:Res:59566.0,61.1] always3(s17) || -> . % 76.04/76.25 59569[61:SSi:59568.0,706.0,58012.0] || -> . % 76.04/76.25 59570[61:Spt:59569.0,59561.0,59566.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.25 59571[61:Spt:59569.0,59561.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.25 59575[61:Res:59571.0,61.1] always3(s18) || -> . % 76.04/76.25 59576[61:SSi:59575.0,707.0] || -> . % 76.04/76.25 59577[59:Spt:59576.0,58010.2,58011.0] || xuntil6(s16)*+ -> . % 76.04/76.25 59578[59:Spt:59576.0,58010.0,58010.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.25 59579[59:Res:53.1,59578.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.25 59581[60:Spt:59579.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.25 59583[60:Res:59581.0,61.1] always3(s17) || -> . % 76.04/76.25 59584[60:SSi:59583.0,706.0] || -> . % 76.04/76.25 59585[60:Spt:59584.0,59579.1,59581.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.25 59586[60:Spt:59584.0,59579.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.25 59589[60:Res:59586.0,61.1] always3(s16) || -> . % 76.04/76.25 59590[60:SSi:59589.0,705.0,58009.0] || -> . % 76.04/76.25 59591[58:Spt:59590.0,58004.2,58008.0] || xuntil6(s15)*+ -> . % 76.04/76.25 59592[58:Spt:59590.0,58004.0,58004.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.25 59593[58:Res:53.1,59592.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.25 59595[59:Spt:59593.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.25 59597[59:Res:59595.0,61.1] always3(s16) || -> . % 76.04/76.25 59598[59:SSi:59597.0,705.0] || -> . % 76.04/76.25 59599[59:Spt:59598.0,59593.1,59595.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.25 59600[59:Spt:59598.0,59593.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.25 59603[59:Res:59600.0,61.1] always3(s15) || -> . % 76.04/76.25 59604[59:SSi:59603.0,704.0,58003.0] || -> . % 76.04/76.25 59605[57:Spt:59604.0,58001.2,58002.0] || xuntil6(s14)*+ -> . % 76.04/76.25 59606[57:Spt:59604.0,58001.0,58001.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.25 59607[57:Res:53.1,59606.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.25 59612[58:Spt:59607.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.25 59614[58:Res:59612.0,61.1] always3(s14) || -> . % 76.04/76.25 59615[58:SSi:59614.0,703.0,58000.0] || -> . % 76.04/76.25 59616[58:Spt:59615.0,59607.0,59612.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.25 59617[58:Spt:59615.0,59607.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.25 59621[58:Res:59617.0,61.1] always3(s15) || -> . % 76.04/76.25 59622[58:SSi:59621.0,704.0] || -> . % 76.04/76.25 59623[56:Spt:59622.0,57995.2,57999.0] || xuntil6(s13)*+ -> . % 76.04/76.25 59624[56:Spt:59622.0,57995.0,57995.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.25 59625[56:Res:53.1,59624.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.25 59627[57:Spt:59625.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.25 59629[57:Res:59627.0,61.1] always3(s14) || -> . % 76.04/76.25 59630[57:SSi:59629.0,703.0] || -> . % 76.04/76.25 59631[57:Spt:59630.0,59625.1,59627.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.25 59632[57:Spt:59630.0,59625.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.25 59635[57:Res:59632.0,61.1] always3(s13) || -> . % 76.04/76.25 59636[57:SSi:59635.0,702.0,57994.0] || -> . % 76.04/76.25 59637[55:Spt:59636.0,57992.2,57993.0] || xuntil6(s12)*+ -> . % 76.04/76.25 59638[55:Spt:59636.0,57992.0,57992.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.25 59639[55:Res:53.1,59638.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.25 59641[56:Spt:59639.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.25 59643[56:Res:59641.0,61.1] always3(s13) || -> . % 76.04/76.25 59644[56:SSi:59643.0,702.0] || -> . % 76.04/76.25 59645[56:Spt:59644.0,59639.1,59641.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.25 59646[56:Spt:59644.0,59639.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.25 59649[56:Res:59646.0,61.1] always3(s12) || -> . % 76.04/76.25 59650[56:SSi:59649.0,701.0,57991.0] || -> . % 76.04/76.25 59651[54:Spt:59650.0,57986.2,57990.0] || xuntil6(s11)*+ -> . % 76.04/76.25 59652[54:Spt:59650.0,57986.0,57986.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.25 59653[54:Res:53.1,59652.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.25 59658[55:Spt:59653.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.25 59660[55:Res:59658.0,61.1] always3(s12) || -> . % 76.04/76.25 59661[55:SSi:59660.0,701.0] || -> . % 76.04/76.25 59662[55:Spt:59661.0,59653.1,59658.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.25 59663[55:Spt:59661.0,59653.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.25 59666[55:Res:59663.0,61.1] always3(s11) || -> . % 76.04/76.25 59667[55:SSi:59666.0,700.0,57985.0] || -> . % 76.04/76.25 59668[53:Spt:59667.0,57983.2,57984.0] || xuntil6(s10)*+ -> . % 76.04/76.25 59669[53:Spt:59667.0,57983.0,57983.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.25 59670[53:Res:53.1,59669.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.25 59672[54:Spt:59670.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.25 59674[54:Res:59672.0,61.1] always3(s10) || -> . % 76.04/76.25 59675[54:SSi:59674.0,699.0,57982.0] || -> . % 76.04/76.25 59676[54:Spt:59675.0,59670.0,59672.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.25 59677[54:Spt:59675.0,59670.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.25 59681[54:Res:59677.0,61.1] always3(s11) || -> . % 76.04/76.25 59682[54:SSi:59681.0,700.0] || -> . % 76.04/76.25 59683[52:Spt:59682.0,57977.2,57981.0] || xuntil6(s9)*+ -> . % 76.04/76.25 59684[52:Spt:59682.0,57977.0,57977.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.25 59685[52:Res:53.1,59684.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.25 59687[53:Spt:59685.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.25 59689[53:Res:59687.0,61.1] always3(s10) || -> . % 76.04/76.25 59690[53:SSi:59689.0,699.0] || -> . % 76.04/76.25 59691[53:Spt:59690.0,59685.1,59687.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.25 59692[53:Spt:59690.0,59685.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.25 59695[53:Res:59692.0,61.1] always3(s9) || -> . % 76.04/76.25 59696[53:SSi:59695.0,698.0,57976.0] || -> . % 76.04/76.25 59697[51:Spt:59696.0,57974.2,57975.0] || xuntil6(s8)*+ -> . % 76.04/76.25 59698[51:Spt:59696.0,57974.0,57974.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.25 59699[51:Res:53.1,59698.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.25 59704[52:Spt:59699.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.25 59706[52:Res:59704.0,61.1] always3(s8) || -> . % 76.04/76.25 59707[52:SSi:59706.0,697.0,57973.0] || -> . % 76.04/76.25 59708[52:Spt:59707.0,59699.0,59704.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.25 59709[52:Spt:59707.0,59699.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.25 59713[52:Res:59709.0,61.1] always3(s9) || -> . % 76.04/76.25 59714[52:SSi:59713.0,698.0] || -> . % 76.04/76.25 59715[50:Spt:59714.0,57968.2,57972.0] || xuntil6(s7)*+ -> . % 76.04/76.25 59716[50:Spt:59714.0,57968.0,57968.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.25 59717[50:Res:53.1,59716.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.25 59719[51:Spt:59717.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.25 59721[51:Res:59719.0,61.1] always3(s7) || -> . % 76.04/76.25 59722[51:SSi:59721.0,696.0,57967.0] || -> . % 76.04/76.25 59723[51:Spt:59722.0,59717.0,59719.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.25 59724[51:Spt:59722.0,59717.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.25 59728[51:Res:59724.0,61.1] always3(s8) || -> . % 76.04/76.25 59729[51:SSi:59728.0,697.0] || -> . % 76.04/76.25 59730[49:Spt:59729.0,57965.2,57966.0] || xuntil6(s6)*+ -> . % 76.04/76.25 59731[49:Spt:59729.0,57965.0,57965.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.25 59732[49:Res:53.1,59731.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.25 59734[50:Spt:59732.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.25 59736[50:Res:59734.0,61.1] always3(s6) || -> . % 76.04/76.25 59737[50:SSi:59736.0,695.0,57964.0] || -> . % 76.04/76.25 59738[50:Spt:59737.0,59732.0,59734.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.25 59739[50:Spt:59737.0,59732.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.25 59743[50:Res:59739.0,61.1] always3(s7) || -> . % 76.04/76.25 59744[50:SSi:59743.0,696.0] || -> . % 76.04/76.25 59745[48:Spt:59744.0,57959.2,57963.0] || xuntil6(s5)*+ -> . % 76.04/76.25 59746[48:Spt:59744.0,57959.0,57959.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.25 59747[48:Res:53.1,59746.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.25 59752[49:Spt:59747.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.25 59754[49:Res:59752.0,61.1] always3(s5) || -> . % 76.04/76.25 59755[49:SSi:59754.0,694.0,57958.0] || -> . % 76.04/76.25 59756[49:Spt:59755.0,59747.0,59752.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.25 59757[49:Spt:59755.0,59747.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.25 59761[49:Res:59757.0,61.1] always3(s6) || -> . % 76.04/76.25 59762[49:SSi:59761.0,695.0] || -> . % 76.04/76.25 59763[47:Spt:59762.0,57956.2,57957.0] || xuntil6(s4)*+ -> . % 76.04/76.25 59764[47:Spt:59762.0,57956.0,57956.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.25 59765[47:Res:53.1,59764.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.25 59767[48:Spt:59765.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.25 59769[48:Res:59767.0,61.1] always3(s4) || -> . % 76.04/76.25 59770[48:SSi:59769.0,693.0,57955.0] || -> . % 76.04/76.25 59771[48:Spt:59770.0,59765.0,59767.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.25 59772[48:Spt:59770.0,59765.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.25 59776[48:Res:59772.0,61.1] always3(s5) || -> . % 76.04/76.25 59777[48:SSi:59776.0,694.0] || -> . % 76.04/76.25 59778[46:Spt:59777.0,57950.2,57954.0] || xuntil6(s3)*+ -> . % 76.04/76.25 59779[46:Spt:59777.0,57950.0,57950.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.25 59780[46:Res:53.1,59779.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.25 59782[47:Spt:59780.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.25 59784[47:Res:59782.0,61.1] always3(s3) || -> . % 76.04/76.25 59785[47:SSi:59784.0,692.0,57949.0] || -> . % 76.04/76.25 59786[47:Spt:59785.0,59780.0,59782.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.25 59787[47:Spt:59785.0,59780.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.25 59791[47:Res:59787.0,61.1] always3(s4) || -> . % 76.04/76.25 59792[47:SSi:59791.0,693.0] || -> . % 76.04/76.25 59793[45:Spt:59792.0,57947.2,57948.0] || xuntil6(s2)*+ -> . % 76.04/76.25 59794[45:Spt:59792.0,57947.0,57947.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.25 59795[45:Res:53.1,59794.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.25 59800[46:Spt:59795.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.25 59802[46:Res:59800.0,61.1] always3(s2) || -> . % 76.04/76.25 59803[46:SSi:59802.0,691.0,57946.0] || -> . % 76.04/76.25 59804[46:Spt:59803.0,59795.0,59800.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.25 59805[46:Spt:59803.0,59795.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.25 59809[46:Res:59805.0,61.1] always3(s3) || -> . % 76.04/76.25 59810[46:SSi:59809.0,692.0] || -> . % 76.04/76.25 59811[44:Spt:59810.0,57938.2,57945.0] || xuntil6(s1)*+ -> . % 76.04/76.25 59812[44:Spt:59810.0,57938.0,57938.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.25 59813[44:Res:53.1,59812.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.25 59815[45:Spt:59813.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.25 59817[45:Res:59815.0,61.1] always3(s1) || -> . % 76.04/76.25 59818[45:SSi:59817.0,690.0,57937.0] || -> . % 76.04/76.25 59819[45:Spt:59818.0,59813.0,59815.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.25 59820[45:Spt:59818.0,59813.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.25 59825[45:Res:59820.0,61.1] always3(s2) || -> . % 76.04/76.25 59826[45:SSi:59825.0,691.0] || -> . % 76.04/76.25 59827[43:Spt:59826.0,74.0,57936.0] || xuntil6(s0)*+ -> . % 76.04/76.25 59828[43:Spt:59826.0,74.1] || -> node4(s0)*. % 76.04/76.25 59829[43:MRR:758.1,59827.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.25 59831[43:Res:59829.0,61.1] always3(s1) || -> . % 76.04/76.25 59832[43:SSi:59831.0,690.0] || -> . % 76.04/76.25 59833[42:Spt:59832.0,57926.0,57930.0] || trans(s49,s9)*+ -> . % 76.04/76.25 59834[42:Spt:59832.0,57926.1,57926.2,57926.3,57926.4,57926.5,57926.6,57926.7,57926.8,57926.9] || -> trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.25 59835[42:MRR:57928.0,59833.0] || -> trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.25 59837[42:MRR:57929.1,59833.0] xuntil6(s49) || -> trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.25 59838[43:Spt:59834.0] || -> trans(s49,s8)*. % 76.04/76.25 59839[43:Res:59838.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s8)*. % 76.04/76.25 59841[43:Res:59838.0,60.0] || -> node2(s49,s8)*. % 76.04/76.25 59842[43:SSi:59839.1,50.0,738.0] xuntil6(s49) || -> until2p7(s8)*. % 76.04/76.25 59843[43:Res:59841.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)*. % 76.04/76.25 59844[44:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.25 59845[44:MRR:176.0,59844.0] || -> until5(s1)*. % 76.04/76.25 59846[44:MRR:58375.0,59845.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.25 59853[45:Spt:59846.2] || -> xuntil6(s1)*. % 76.04/76.25 59854[45:MRR:175.0,59853.0] || -> until5(s2)*. % 76.04/76.25 59855[45:MRR:58371.0,59854.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.25 59856[46:Spt:59855.2] || -> xuntil6(s2)*. % 76.04/76.25 59857[46:MRR:174.0,59856.0] || -> until5(s3)*. % 76.04/76.25 59858[46:MRR:58367.0,59857.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.25 59862[47:Spt:59858.2] || -> xuntil6(s3)*. % 76.04/76.25 59863[47:MRR:173.0,59862.0] || -> until5(s4)*. % 76.04/76.25 59864[47:MRR:58366.0,59863.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.25 59865[48:Spt:59864.2] || -> xuntil6(s4)*. % 76.04/76.25 59866[48:MRR:172.0,59865.0] || -> until5(s5)*. % 76.04/76.25 59867[48:MRR:58359.0,59866.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.25 59871[49:Spt:59867.2] || -> xuntil6(s5)*. % 76.04/76.25 59872[49:MRR:171.0,59871.0] || -> until5(s6)*. % 76.04/76.25 59873[49:MRR:58355.0,59872.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.25 59874[50:Spt:59873.2] || -> xuntil6(s6)*. % 76.04/76.25 59875[50:MRR:170.0,59874.0] || -> until5(s7)*. % 76.04/76.25 59876[50:MRR:58351.0,59875.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.25 59880[51:Spt:59876.2] || -> xuntil6(s7)*. % 76.04/76.25 59881[51:MRR:169.0,59880.0] || -> until5(s8)*. % 76.04/76.25 59882[51:MRR:58347.0,59881.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.25 59883[52:Spt:59882.2] || -> xuntil6(s8)*. % 76.04/76.25 59884[52:MRR:168.0,59883.0] || -> until5(s9)*. % 76.04/76.25 59885[52:MRR:58346.0,59884.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.25 59889[53:Spt:59885.2] || -> xuntil6(s9)*. % 76.04/76.25 59890[53:MRR:167.0,59889.0] || -> until5(s10)*. % 76.04/76.25 59891[53:MRR:58339.0,59890.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.25 59892[54:Spt:59891.2] || -> xuntil6(s10)*. % 76.04/76.25 59893[54:MRR:166.0,59892.0] || -> until5(s11)*. % 76.04/76.25 59894[54:MRR:58335.0,59893.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.25 59898[55:Spt:59894.2] || -> xuntil6(s11)*. % 76.04/76.25 59899[55:MRR:165.0,59898.0] || -> until5(s12)*. % 76.04/76.25 59900[55:MRR:58328.0,59899.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.25 59901[56:Spt:59900.2] || -> xuntil6(s12)*. % 76.04/76.25 59902[56:MRR:164.0,59901.0] || -> until5(s13)*. % 76.04/76.25 59903[56:MRR:58327.0,59902.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.25 59907[57:Spt:59903.2] || -> xuntil6(s13)*. % 76.04/76.25 59908[57:MRR:163.0,59907.0] || -> until5(s14)*. % 76.04/76.25 59909[57:MRR:58320.0,59908.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.25 59910[58:Spt:59909.2] || -> xuntil6(s14)*. % 76.04/76.25 59911[58:MRR:162.0,59910.0] || -> until5(s15)*. % 76.04/76.25 59912[58:MRR:58316.0,59911.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.25 59916[59:Spt:59912.2] || -> xuntil6(s15)*. % 76.04/76.25 59917[59:MRR:161.0,59916.0] || -> until5(s16)*. % 76.04/76.25 59918[59:MRR:58315.0,59917.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.25 59919[60:Spt:59918.2] || -> xuntil6(s16)*. % 76.04/76.25 59920[60:MRR:160.0,59919.0] || -> until5(s17)*. % 76.04/76.25 59921[60:MRR:58308.0,59920.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.25 59925[61:Spt:59921.2] || -> xuntil6(s17)*. % 76.04/76.25 59926[61:MRR:159.0,59925.0] || -> until5(s18)*. % 76.04/76.25 59927[61:MRR:58307.0,59926.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.25 59928[62:Spt:59927.2] || -> xuntil6(s18)*. % 76.04/76.25 59929[62:MRR:158.0,59928.0] || -> until5(s19)*. % 76.04/76.25 59930[62:MRR:58306.0,59929.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.25 59934[63:Spt:59930.2] || -> xuntil6(s19)*. % 76.04/76.25 59935[63:MRR:157.0,59934.0] || -> until5(s20)*. % 76.04/76.25 59936[63:MRR:58296.0,59935.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.25 59937[64:Spt:59936.2] || -> xuntil6(s20)*. % 76.04/76.25 59938[64:MRR:156.0,59937.0] || -> until5(s21)*. % 76.04/76.25 59939[64:MRR:58295.0,59938.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.25 59943[65:Spt:59939.2] || -> xuntil6(s21)*. % 76.04/76.25 59944[65:MRR:155.0,59943.0] || -> until5(s22)*. % 76.04/76.25 59945[65:MRR:58288.0,59944.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.25 59946[66:Spt:59945.2] || -> xuntil6(s22)*. % 76.04/76.25 59947[66:MRR:154.0,59946.0] || -> until5(s23)*. % 76.04/76.25 59948[66:MRR:58284.0,59947.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.25 59952[67:Spt:59948.2] || -> xuntil6(s23)*. % 76.04/76.25 59953[67:MRR:153.0,59952.0] || -> until5(s24)*. % 76.04/76.25 59954[67:MRR:58280.0,59953.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.25 59955[68:Spt:59954.2] || -> xuntil6(s24)*. % 76.04/76.25 59956[68:MRR:152.0,59955.0] || -> until5(s25)*. % 76.04/76.25 59957[68:MRR:58276.0,59956.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.25 59961[69:Spt:59957.2] || -> xuntil6(s25)*. % 76.04/76.25 59962[69:MRR:151.0,59961.0] || -> until5(s26)*. % 76.04/76.25 59963[69:MRR:58275.0,59962.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.25 59964[70:Spt:59963.2] || -> xuntil6(s26)*. % 76.04/76.25 59965[70:MRR:150.0,59964.0] || -> until5(s27)*. % 76.04/76.25 59966[70:MRR:58271.0,59965.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.25 59970[71:Spt:59966.2] || -> xuntil6(s27)*. % 76.04/76.25 59971[71:MRR:149.0,59970.0] || -> until5(s28)*. % 76.04/76.25 59972[71:MRR:58270.0,59971.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.25 59973[72:Spt:59972.2] || -> xuntil6(s28)*. % 76.04/76.25 59974[72:MRR:148.0,59973.0] || -> until5(s29)*. % 76.04/76.25 59975[72:MRR:58269.0,59974.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.25 59979[73:Spt:59975.2] || -> xuntil6(s29)*. % 76.04/76.25 59980[73:MRR:147.0,59979.0] || -> until5(s30)*. % 76.04/76.25 59981[73:MRR:58268.0,59980.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.25 59982[74:Spt:59981.2] || -> xuntil6(s30)*. % 76.04/76.25 59983[74:MRR:146.0,59982.0] || -> until5(s31)*. % 76.04/76.25 59984[74:MRR:54645.0,59983.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.25 59988[75:Spt:59984.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.25 59990[75:Res:59988.0,61.1] always3(s32) || -> . % 76.04/76.25 59991[75:SSi:59990.0,721.0] || -> . % 76.04/76.25 59992[75:Spt:59991.0,59984.1,59988.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.04/76.25 59993[75:Spt:59991.0,59984.0,59984.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.04/76.25 59995[75:MRR:825.2,59992.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.04/76.25 59996[75:Res:53.1,59993.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.04/76.25 59998[76:Spt:59996.1] || -> xuntil6(s31)*. % 76.04/76.25 59999[76:MRR:145.0,59998.0] || -> until5(s32)*. % 76.04/76.25 60000[76:MRR:58382.0,59999.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.25 60005[77:Spt:60000.2] || -> xuntil6(s32)*. % 76.04/76.25 60006[77:MRR:144.0,60005.0] || -> until5(s33)*. % 76.04/76.25 60007[77:MRR:54646.0,60006.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.25 60008[78:Spt:60007.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.25 60010[78:Res:60008.0,61.1] always3(s34) || -> . % 76.04/76.25 60011[78:SSi:60010.0,723.0] || -> . % 76.04/76.25 60012[78:Spt:60011.0,60007.1,60008.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.25 60013[78:Spt:60011.0,60007.0,60007.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.25 60015[78:MRR:819.2,60012.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.25 60016[78:Res:53.1,60013.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.25 60018[79:Spt:60016.1] || -> xuntil6(s33)*. % 76.04/76.25 60019[79:MRR:143.0,60018.0] || -> until5(s34)*. % 76.04/76.25 60020[79:MRR:58386.0,60019.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.25 60028[80:Spt:60020.2] || -> xuntil6(s34)*. % 76.04/76.25 60029[80:MRR:142.0,60028.0] || -> until5(s35)*. % 76.04/76.25 60030[80:MRR:54650.0,60029.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.25 60031[81:Spt:60030.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.25 60033[81:Res:60031.0,61.1] always3(s36) || -> . % 76.04/76.25 60034[81:SSi:60033.0,725.0] || -> . % 76.04/76.25 60035[81:Spt:60034.0,60030.1,60031.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.25 60036[81:Spt:60034.0,60030.0,60030.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.25 60038[81:MRR:813.2,60035.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.25 60039[81:Res:53.1,60036.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.25 60044[82:Spt:60039.1] || -> xuntil6(s35)*. % 76.04/76.25 60045[82:MRR:141.0,60044.0] || -> until5(s36)*. % 76.04/76.25 60046[82:MRR:58390.0,60045.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.25 60048[83:Spt:60046.2] || -> xuntil6(s36)*. % 76.04/76.25 60049[83:MRR:140.0,60048.0] || -> until5(s37)*. % 76.04/76.25 60050[83:MRR:54654.0,60049.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.25 60051[84:Spt:60050.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.25 60053[84:Res:60051.0,61.1] always3(s38) || -> . % 76.04/76.25 60054[84:SSi:60053.0,727.0] || -> . % 76.04/76.25 60055[84:Spt:60054.0,60050.1,60051.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.25 60056[84:Spt:60054.0,60050.0,60050.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.25 60058[84:MRR:807.2,60055.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.25 60059[84:Res:53.1,60056.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.25 60061[85:Spt:60059.1] || -> xuntil6(s37)*. % 76.04/76.25 60062[85:MRR:139.0,60061.0] || -> until5(s38)*. % 76.04/76.25 60063[85:MRR:58397.0,60062.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.25 60068[86:Spt:60063.2] || -> xuntil6(s38)*. % 76.04/76.25 60069[86:MRR:138.0,60068.0] || -> until5(s39)*. % 76.04/76.25 60070[86:MRR:54658.0,60069.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.25 60071[87:Spt:60070.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.25 60073[87:Res:60071.0,61.1] always3(s40) || -> . % 76.04/76.25 60074[87:SSi:60073.0,729.0] || -> . % 76.04/76.25 60075[87:Spt:60074.0,60070.1,60071.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.25 60076[87:Spt:60074.0,60070.0,60070.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.25 60078[87:MRR:801.2,60075.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.25 60079[87:Res:53.1,60076.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.25 60081[88:Spt:60079.1] || -> xuntil6(s39)*. % 76.04/76.25 60082[88:MRR:137.0,60081.0] || -> until5(s40)*. % 76.04/76.25 60083[88:MRR:58398.0,60082.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.25 60091[89:Spt:60083.2] || -> xuntil6(s40)*. % 76.04/76.25 60092[89:MRR:136.0,60091.0] || -> until5(s41)*. % 76.04/76.25 60093[89:MRR:54665.0,60092.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.25 60094[90:Spt:60093.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.25 60096[90:Res:60094.0,61.1] always3(s42) || -> . % 76.04/76.25 60097[90:SSi:60096.0,731.0] || -> . % 76.04/76.25 60098[90:Spt:60097.0,60093.1,60094.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.25 60099[90:Spt:60097.0,60093.0,60093.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.25 60101[90:MRR:795.2,60098.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.25 60102[90:Res:53.1,60099.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.25 60107[91:Spt:60102.1] || -> xuntil6(s41)*. % 76.04/76.25 60108[91:MRR:135.0,60107.0] || -> until5(s42)*. % 76.04/76.25 60109[91:MRR:58402.0,60108.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.25 60111[92:Spt:60109.2] || -> xuntil6(s42)*. % 76.04/76.25 60112[92:MRR:134.0,60111.0] || -> until5(s43)*. % 76.04/76.25 60113[92:MRR:54666.0,60112.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.25 60114[93:Spt:60113.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.25 60116[93:Res:60114.0,61.1] always3(s44) || -> . % 76.04/76.25 60117[93:SSi:60116.0,733.0] || -> . % 76.04/76.25 60118[93:Spt:60117.0,60113.1,60114.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.25 60119[93:Spt:60117.0,60113.0,60113.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.25 60121[93:MRR:789.2,60118.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.25 60122[93:Res:53.1,60119.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.25 60124[94:Spt:60122.1] || -> xuntil6(s43)*. % 76.04/76.25 60125[94:MRR:133.0,60124.0] || -> until5(s44)*. % 76.04/76.25 60126[94:MRR:58406.0,60125.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.25 60131[95:Spt:60126.2] || -> xuntil6(s44)*. % 76.04/76.25 60132[95:MRR:132.0,60131.0] || -> until5(s45)*. % 76.04/76.25 60133[95:MRR:54670.0,60132.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.25 60134[96:Spt:60133.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.25 60136[96:Res:60134.0,61.1] always3(s46) || -> . % 76.04/76.25 60137[96:SSi:60136.0,735.0] || -> . % 76.04/76.25 60138[96:Spt:60137.0,60133.1,60134.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.25 60139[96:Spt:60137.0,60133.0,60133.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.25 60141[96:MRR:783.2,60138.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.25 60142[96:Res:53.1,60139.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.25 60144[97:Spt:60142.1] || -> xuntil6(s45)*. % 76.04/76.25 60145[97:MRR:131.0,60144.0] || -> until5(s46)*. % 76.04/76.25 60146[97:MRR:58410.0,60145.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.25 60154[98:Spt:60146.2] || -> xuntil6(s46)*. % 76.04/76.25 60155[98:MRR:130.0,60154.0] || -> until5(s47)*. % 76.04/76.25 60156[98:MRR:54674.0,60155.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.25 60157[99:Spt:60156.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.25 60159[99:Res:60157.0,61.1] always3(s48) || -> . % 76.04/76.25 60160[99:SSi:60159.0,737.0] || -> . % 76.04/76.25 60161[99:Spt:60160.0,60156.1,60157.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.25 60162[99:Spt:60160.0,60156.0,60156.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.25 60164[99:MRR:777.2,60161.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.25 60165[99:Res:53.1,60162.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.25 60170[100:Spt:60165.1] || -> xuntil6(s47)*. % 76.04/76.25 60171[100:MRR:129.0,60170.0] || -> until5(s48)*. % 76.04/76.25 60172[100:MRR:58414.0,60171.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.25 60174[101:Spt:60172.2] || -> xuntil6(s48)*. % 76.04/76.25 60175[101:MRR:128.0,60174.0] || -> until5(s49)*. % 76.04/76.25 60176[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.25 60177[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.25 60178[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.25 60179[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.25 60183[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.25 60184[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.25 60188[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.25 60192[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.25 60196[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.25 60203[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.25 60204[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.25 60214[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.25 60215[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.25 60216[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.25 60223[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.25 60224[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.25 60228[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.25 60235[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.25 60236[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.25 60243[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.25 60244[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.25 60254[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.25 60255[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.25 60259[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.25 60263[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.25 60267[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.25 60274[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.25 60275[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.25 60279[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.25 60283[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.25 60285[43:SoR:59843.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)*. % 76.04/76.25 60290[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.25 60294[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.25 60298[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.25 60305[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.25 60306[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.25 60310[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.25 60314[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.25 60318[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.25 60322[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.25 60323[43:SoR:60285.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)* xuntil6(s49). % 76.04/76.25 60324[101:SSi:60323.0,50.0,738.0,60175.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s8,c_busy)* xuntil6(s49). % 76.04/76.25 60325[102:Spt:60324.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.25 60327[102:Res:60325.0,61.1] always3(s8) || -> . % 76.04/76.25 60328[102:SSi:60327.0,697.0,59881.0,59883.0] || -> . % 76.04/76.25 60329[102:Spt:60328.0,60324.1,60325.0] || m_main_v_state(s8,c_busy)*+ -> . % 76.04/76.25 60330[102:Spt:60328.0,60324.0,60324.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.25 60334[102:MRR:60285.2,60329.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.25 60335[102:Res:53.1,60330.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.25 60337[103:Spt:60335.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.25 60339[103:Res:60337.0,61.1] always3(s49) || -> . % 76.04/76.25 60340[103:SSi:60339.0,50.0,738.0,60175.0] || -> . % 76.04/76.25 60341[103:Spt:60340.0,60335.0,60337.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.25 60342[103:Spt:60340.0,60335.1] || -> xuntil6(s49)*. % 76.04/76.25 60343[103:MRR:59842.0,60342.0] || -> until2p7(s8)*. % 76.04/76.25 60344[103:MRR:204.0,60343.0] || -> until2p7(s9)* node4(s8). % 76.04/76.25 60346[103:MRR:774.2,60341.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.25 60347[104:Spt:60344.0] || -> until2p7(s9)*. % 76.04/76.25 60348[104:MRR:205.0,60347.0] || -> until2p7(s10)* node4(s9). % 76.04/76.25 60349[105:Spt:60348.0] || -> until2p7(s10)*. % 76.04/76.25 60350[105:MRR:206.0,60349.0] || -> until2p7(s11)* node4(s10). % 76.04/76.25 60351[106:Spt:60350.0] || -> until2p7(s11)*. % 76.04/76.25 60352[106:MRR:207.0,60351.0] || -> until2p7(s12)* node4(s11). % 76.04/76.25 60353[107:Spt:60352.0] || -> until2p7(s12)*. % 76.04/76.25 60354[107:MRR:208.0,60353.0] || -> until2p7(s13)* node4(s12). % 76.04/76.25 60355[108:Spt:60354.0] || -> until2p7(s13)*. % 76.04/76.25 60356[108:MRR:209.0,60355.0] || -> until2p7(s14)* node4(s13). % 76.04/76.25 60357[109:Spt:60356.0] || -> until2p7(s14)*. % 76.04/76.25 60358[109:MRR:210.0,60357.0] || -> until2p7(s15)* node4(s14). % 76.04/76.25 60359[110:Spt:60358.0] || -> until2p7(s15)*. % 76.04/76.25 60360[110:MRR:211.0,60359.0] || -> until2p7(s16)* node4(s15). % 76.04/76.25 60361[111:Spt:60360.0] || -> until2p7(s16)*. % 76.04/76.25 60362[111:MRR:212.0,60361.0] || -> until2p7(s17)* node4(s16). % 76.04/76.25 60363[112:Spt:60362.0] || -> until2p7(s17)*. % 76.04/76.25 60364[112:MRR:213.0,60363.0] || -> until2p7(s18)* node4(s17). % 76.04/76.25 60365[113:Spt:60364.0] || -> until2p7(s18)*. % 76.04/76.25 60366[113:MRR:214.0,60365.0] || -> until2p7(s19)* node4(s18). % 76.04/76.25 60367[114:Spt:60366.0] || -> until2p7(s19)*. % 76.04/76.25 60368[114:MRR:215.0,60367.0] || -> until2p7(s20)* node4(s19). % 76.04/76.25 60369[115:Spt:60368.0] || -> until2p7(s20)*. % 76.04/76.25 60370[115:MRR:216.0,60369.0] || -> until2p7(s21)* node4(s20). % 76.04/76.25 60371[116:Spt:60370.0] || -> until2p7(s21)*. % 76.04/76.25 60372[116:MRR:217.0,60371.0] || -> until2p7(s22)* node4(s21). % 76.04/76.25 60373[117:Spt:60372.0] || -> until2p7(s22)*. % 76.04/76.25 60374[117:MRR:218.0,60373.0] || -> until2p7(s23)* node4(s22). % 76.04/76.25 60375[118:Spt:60374.0] || -> until2p7(s23)*. % 76.04/76.25 60376[118:MRR:219.0,60375.0] || -> until2p7(s24)* node4(s23). % 76.04/76.25 60377[119:Spt:60376.0] || -> until2p7(s24)*. % 76.04/76.25 60378[119:MRR:220.0,60377.0] || -> until2p7(s25)* node4(s24). % 76.04/76.25 60379[120:Spt:60378.0] || -> until2p7(s25)*. % 76.04/76.25 60380[120:MRR:221.0,60379.0] || -> until2p7(s26)* node4(s25). % 76.04/76.25 60381[121:Spt:60380.0] || -> until2p7(s26)*. % 76.04/76.25 60382[121:MRR:222.0,60381.0] || -> until2p7(s27)* node4(s26). % 76.04/76.25 60383[122:Spt:60382.0] || -> until2p7(s27)*. % 76.04/76.25 60384[122:MRR:223.0,60383.0] || -> until2p7(s28)* node4(s27). % 76.04/76.25 60385[123:Spt:60384.0] || -> until2p7(s28)*. % 76.04/76.25 60386[123:MRR:224.0,60385.0] || -> until2p7(s29)* node4(s28). % 76.04/76.25 60387[124:Spt:60386.0] || -> until2p7(s29)*. % 76.04/76.25 60388[124:MRR:225.0,60387.0] || -> until2p7(s30)* node4(s29). % 76.04/76.25 60389[125:Spt:60388.0] || -> until2p7(s30)*. % 76.04/76.25 60390[125:MRR:226.0,60389.0] || -> until2p7(s31)* node4(s30). % 76.04/76.25 60391[126:Spt:60390.0] || -> until2p7(s31)*. % 76.04/76.25 60392[126:MRR:227.0,60391.0] || -> until2p7(s32)* node4(s31). % 76.04/76.25 60393[127:Spt:60392.0] || -> until2p7(s32)*. % 76.04/76.25 60394[127:MRR:228.0,60393.0] || -> until2p7(s33)* node4(s32). % 76.04/76.25 60395[128:Spt:60394.0] || -> until2p7(s33)*. % 76.04/76.25 60396[128:MRR:229.0,60395.0] || -> until2p7(s34)* node4(s33). % 76.04/76.25 60397[129:Spt:60396.0] || -> until2p7(s34)*. % 76.04/76.25 60398[129:MRR:230.0,60397.0] || -> until2p7(s35)* node4(s34). % 76.04/76.25 60399[130:Spt:60398.0] || -> until2p7(s35)*. % 76.04/76.25 60400[130:MRR:231.0,60399.0] || -> until2p7(s36)* node4(s35). % 76.04/76.25 60401[131:Spt:60400.0] || -> until2p7(s36)*. % 76.04/76.25 60402[131:MRR:232.0,60401.0] || -> until2p7(s37)* node4(s36). % 76.04/76.25 60403[132:Spt:60402.0] || -> until2p7(s37)*. % 76.04/76.25 60404[132:MRR:235.0,60403.0] || -> until2p7(s38)* node4(s37). % 76.04/76.25 60405[133:Spt:60404.0] || -> until2p7(s38)*. % 76.04/76.25 60406[133:MRR:236.0,60405.0] || -> until2p7(s39)* node4(s38). % 76.04/76.25 60407[134:Spt:60406.0] || -> until2p7(s39)*. % 76.04/76.25 60408[134:MRR:237.0,60407.0] || -> until2p7(s40)* node4(s39). % 76.04/76.25 60409[135:Spt:60408.0] || -> until2p7(s40)*. % 76.04/76.25 60410[135:MRR:238.0,60409.0] || -> until2p7(s41)* node4(s40). % 76.04/76.25 60411[136:Spt:60410.0] || -> until2p7(s41)*. % 76.04/76.25 60412[136:MRR:239.0,60411.0] || -> until2p7(s42)* node4(s41). % 76.04/76.25 60413[137:Spt:60412.0] || -> until2p7(s42)*. % 76.04/76.25 60414[137:MRR:240.0,60413.0] || -> until2p7(s43)* node4(s42). % 76.04/76.25 60415[138:Spt:60414.0] || -> until2p7(s43)*. % 76.04/76.25 60416[138:MRR:241.0,60415.0] || -> until2p7(s44)* node4(s43). % 76.04/76.25 60417[139:Spt:60416.0] || -> until2p7(s44)*. % 76.04/76.25 60418[139:MRR:539.0,60417.0] || -> until2p7(s45)* node4(s44). % 76.04/76.25 60419[140:Spt:60418.0] || -> until2p7(s45)*. % 76.04/76.25 60420[140:MRR:544.0,60419.0] || -> until2p7(s46)* node4(s45). % 76.04/76.25 60421[141:Spt:60420.0] || -> until2p7(s46)*. % 76.04/76.25 60422[141:MRR:549.0,60421.0] || -> until2p7(s47)* node4(s46). % 76.04/76.25 60423[142:Spt:60422.0] || -> until2p7(s47)*. % 76.04/76.25 60424[142:MRR:554.0,60423.0] || -> until2p7(s48)* node4(s47). % 76.04/76.25 60425[143:Spt:60424.0] || -> until2p7(s48)*. % 76.04/76.25 60426[143:MRR:559.0,60425.0] || -> until2p7(s49)* node4(s48). % 76.04/76.25 60427[144:Spt:60426.0] || -> until2p7(s49)*. % 76.04/76.25 60428[144:MRR:194.0,60427.0] || -> node4(s49)*. % 76.04/76.25 60429[144:MRR:60334.0,60428.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.25 60430[144:Res:53.1,60429.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.25 60432[144:MRR:60430.0,60341.0] || -> . % 76.04/76.25 60433[144:Spt:60432.0,60426.0,60427.0] || until2p7(s49)*+ -> . % 76.04/76.25 60434[144:Spt:60432.0,60426.1] || -> node4(s48)*. % 76.04/76.25 60435[144:MRR:60346.0,60434.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.25 60438[144:Res:53.1,60435.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.25 60440[144:MRR:60438.0,60161.0] || -> . % 76.04/76.25 60441[143:Spt:60440.0,60424.0,60425.0] || until2p7(s48)*+ -> . % 76.04/76.25 60442[143:Spt:60440.0,60424.1] || -> node4(s47)*. % 76.04/76.25 60443[143:MRR:60164.0,60442.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.25 60446[143:Res:53.1,60443.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.25 60449[143:Res:60446.0,61.1] always3(s47) || -> . % 76.04/76.25 60450[143:SSi:60449.0,736.0,60155.0,60170.0,60423.0,60442.0] || -> . % 76.04/76.25 60451[142:Spt:60450.0,60422.0,60423.0] || until2p7(s47)*+ -> . % 76.04/76.25 60452[142:Spt:60450.0,60422.1] || -> node4(s46)*. % 76.04/76.25 60454[142:MRR:780.0,60452.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.25 60474[142:Res:53.1,60454.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.25 60476[142:MRR:60474.0,60138.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.25 60478[142:Res:60476.0,61.1] always3(s47) || -> . % 76.04/76.25 60479[142:SSi:60478.0,736.0,60155.0,60170.0] || -> . % 76.04/76.25 60480[141:Spt:60479.0,60420.0,60421.0] || until2p7(s46)*+ -> . % 76.04/76.25 60481[141:Spt:60479.0,60420.1] || -> node4(s45)*. % 76.04/76.25 60482[141:MRR:60141.0,60481.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.25 60485[141:Res:53.1,60482.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.25 60488[141:Res:60485.0,61.1] always3(s45) || -> . % 76.04/76.25 60489[141:SSi:60488.0,734.0,60132.0,60144.0,60419.0,60481.0] || -> . % 76.04/76.25 60490[140:Spt:60489.0,60418.0,60419.0] || until2p7(s45)*+ -> . % 76.04/76.25 60491[140:Spt:60489.0,60418.1] || -> node4(s44)*. % 76.04/76.25 60493[140:MRR:786.0,60491.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.25 60505[140:Res:53.1,60493.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.25 60507[140:MRR:60505.0,60118.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.25 60509[140:Res:60507.0,61.1] always3(s45) || -> . % 76.04/76.25 60510[140:SSi:60509.0,734.0,60132.0,60144.0] || -> . % 76.04/76.25 60511[139:Spt:60510.0,60416.0,60417.0] || until2p7(s44)*+ -> . % 76.04/76.25 60512[139:Spt:60510.0,60416.1] || -> node4(s43)*. % 76.04/76.25 60513[139:MRR:60121.0,60512.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.25 60516[139:Res:53.1,60513.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.25 60519[139:Res:60516.0,61.1] always3(s43) || -> . % 76.04/76.25 60520[139:SSi:60519.0,732.0,60112.0,60124.0,60415.0,60512.0] || -> . % 76.04/76.25 60521[138:Spt:60520.0,60414.0,60415.0] || until2p7(s43)*+ -> . % 76.04/76.25 60522[138:Spt:60520.0,60414.1] || -> node4(s42)*. % 76.04/76.25 60524[138:MRR:792.0,60522.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.25 60536[138:Res:53.1,60524.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.25 60538[138:MRR:60536.0,60098.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.25 60543[138:Res:60538.0,61.1] always3(s43) || -> . % 76.04/76.25 60544[138:SSi:60543.0,732.0,60112.0,60124.0] || -> . % 76.04/76.25 60545[137:Spt:60544.0,60412.0,60413.0] || until2p7(s42)*+ -> . % 76.04/76.25 60546[137:Spt:60544.0,60412.1] || -> node4(s41)*. % 76.04/76.25 60547[137:MRR:60101.0,60546.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.25 60550[137:Res:53.1,60547.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.25 60554[137:Res:60550.0,61.1] always3(s41) || -> . % 76.04/76.25 60555[137:SSi:60554.0,730.0,60092.0,60107.0,60411.0,60546.0] || -> . % 76.04/76.25 60556[136:Spt:60555.0,60410.0,60411.0] || until2p7(s41)*+ -> . % 76.04/76.25 60557[136:Spt:60555.0,60410.1] || -> node4(s40)*. % 76.04/76.25 60559[136:MRR:798.0,60557.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.25 60570[136:Res:53.1,60559.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.25 60572[136:MRR:60570.0,60075.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.25 60574[136:Res:60572.0,61.1] always3(s41) || -> . % 76.04/76.25 60575[136:SSi:60574.0,730.0,60092.0,60107.0] || -> . % 76.04/76.25 60576[135:Spt:60575.0,60408.0,60409.0] || until2p7(s40)*+ -> . % 76.04/76.25 60577[135:Spt:60575.0,60408.1] || -> node4(s39)*. % 76.04/76.25 60578[135:MRR:60078.0,60577.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.25 60582[135:Res:53.1,60578.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.25 60585[135:Res:60582.0,61.1] always3(s39) || -> . % 76.04/76.25 60586[135:SSi:60585.0,728.0,60069.0,60081.0,60407.0,60577.0] || -> . % 76.04/76.25 60587[134:Spt:60586.0,60406.0,60407.0] || until2p7(s39)*+ -> . % 76.04/76.25 60588[134:Spt:60586.0,60406.1] || -> node4(s38)*. % 76.04/76.25 60590[134:MRR:804.0,60588.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.25 60601[134:Res:53.1,60590.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.25 60603[134:MRR:60601.0,60055.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.25 60605[134:Res:60603.0,61.1] always3(s39) || -> . % 76.04/76.25 60606[134:SSi:60605.0,728.0,60069.0,60081.0] || -> . % 76.04/76.25 60607[133:Spt:60606.0,60404.0,60405.0] || until2p7(s38)*+ -> . % 76.04/76.25 60608[133:Spt:60606.0,60404.1] || -> node4(s37)*. % 76.04/76.25 60609[133:MRR:60058.0,60608.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.25 60612[133:Res:53.1,60609.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.25 60615[133:Res:60612.0,61.1] always3(s37) || -> . % 76.04/76.25 60616[133:SSi:60615.0,726.0,60049.0,60061.0,60403.0,60608.0] || -> . % 76.04/76.25 60617[132:Spt:60616.0,60402.0,60403.0] || until2p7(s37)*+ -> . % 76.04/76.25 60618[132:Spt:60616.0,60402.1] || -> node4(s36)*. % 76.04/76.25 60620[132:MRR:810.0,60618.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.25 60632[132:Res:53.1,60620.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.25 60634[132:MRR:60632.0,60035.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.25 60636[132:Res:60634.0,61.1] always3(s37) || -> . % 76.04/76.25 60637[132:SSi:60636.0,726.0,60049.0,60061.0] || -> . % 76.04/76.25 60638[131:Spt:60637.0,60400.0,60401.0] || until2p7(s36)*+ -> . % 76.04/76.25 60639[131:Spt:60637.0,60400.1] || -> node4(s35)*. % 76.04/76.25 60640[131:MRR:60038.0,60639.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.25 60643[131:Res:53.1,60640.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.25 60646[131:Res:60643.0,61.1] always3(s35) || -> . % 76.04/76.25 60647[131:SSi:60646.0,724.0,60029.0,60044.0,60399.0,60639.0] || -> . % 76.04/76.25 60648[130:Spt:60647.0,60398.0,60399.0] || until2p7(s35)*+ -> . % 76.04/76.25 60649[130:Spt:60647.0,60398.1] || -> node4(s34)*. % 76.04/76.25 60651[130:MRR:816.0,60649.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.25 60663[130:Res:53.1,60651.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.25 60665[130:MRR:60663.0,60012.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.25 60670[130:Res:60665.0,61.1] always3(s35) || -> . % 76.04/76.25 60671[130:SSi:60670.0,724.0,60029.0,60044.0] || -> . % 76.04/76.25 60672[129:Spt:60671.0,60396.0,60397.0] || until2p7(s34)*+ -> . % 76.04/76.25 60673[129:Spt:60671.0,60396.1] || -> node4(s33)*. % 76.04/76.25 60674[129:MRR:60015.0,60673.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.25 60677[129:Res:53.1,60674.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.25 60681[129:Res:60677.0,61.1] always3(s33) || -> . % 76.04/76.25 60682[129:SSi:60681.0,722.0,60006.0,60018.0,60395.0,60673.0] || -> . % 76.04/76.25 60683[128:Spt:60682.0,60394.0,60395.0] || until2p7(s33)*+ -> . % 76.04/76.25 60684[128:Spt:60682.0,60394.1] || -> node4(s32)*. % 76.04/76.25 60686[128:MRR:822.0,60684.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.25 60697[128:Res:53.1,60686.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.25 60699[128:MRR:60697.0,59992.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.25 60701[128:Res:60699.0,61.1] always3(s33) || -> . % 76.04/76.25 60702[128:SSi:60701.0,722.0,60006.0,60018.0] || -> . % 76.04/76.25 60703[127:Spt:60702.0,60392.0,60393.0] || until2p7(s32)*+ -> . % 76.04/76.25 60704[127:Spt:60702.0,60392.1] || -> node4(s31)*. % 76.04/76.25 60705[127:MRR:59995.0,60704.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.04/76.25 60709[127:Res:53.1,60705.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.25 60712[127:Res:60709.0,61.1] always3(s31) || -> . % 76.04/76.25 60713[127:SSi:60712.0,720.0,59983.0,59998.0,60391.0,60704.0] || -> . % 76.04/76.25 60714[126:Spt:60713.0,60390.0,60391.0] || until2p7(s31)*+ -> . % 76.04/76.25 60715[126:Spt:60713.0,60390.1] || -> node4(s30)*. % 76.04/76.25 60717[126:MRR:828.0,60715.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.25 60728[126:Res:53.1,60717.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.25 60730[127:Spt:60728.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.25 60732[127:Res:60730.0,61.1] always3(s30) || -> . % 76.04/76.25 60733[127:SSi:60732.0,719.0,59980.0,59982.0,60389.0,60715.0] || -> . % 76.04/76.25 60734[127:Spt:60733.0,60728.0,60730.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.25 60735[127:Spt:60733.0,60728.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.25 60739[127:Res:60735.0,61.1] always3(s31) || -> . % 76.04/76.25 60740[127:SSi:60739.0,720.0,59983.0,59998.0] || -> . % 76.04/76.25 60741[125:Spt:60740.0,60388.0,60389.0] || until2p7(s30)*+ -> . % 76.04/76.25 60742[125:Spt:60740.0,60388.1] || -> node4(s29)*. % 76.04/76.25 60744[125:MRR:831.0,60742.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.25 60754[125:Res:53.1,60744.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.25 60756[126:Spt:60754.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.25 60758[126:Res:60756.0,61.1] always3(s29) || -> . % 76.04/76.25 60759[126:SSi:60758.0,718.0,59974.0,59979.0,60387.0,60742.0] || -> . % 76.04/76.25 60760[126:Spt:60759.0,60754.0,60756.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.25 60761[126:Spt:60759.0,60754.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.25 60765[126:Res:60761.0,61.1] always3(s30) || -> . % 76.04/76.25 60766[126:SSi:60765.0,719.0,59980.0,59982.0] || -> . % 76.04/76.25 60767[124:Spt:60766.0,60386.0,60387.0] || until2p7(s29)*+ -> . % 76.04/76.25 60768[124:Spt:60766.0,60386.1] || -> node4(s28)*. % 76.04/76.25 60770[124:MRR:834.0,60768.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.25 60773[124:Res:53.1,60770.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.25 60775[125:Spt:60773.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.25 60777[125:Res:60775.0,61.1] always3(s28) || -> . % 76.04/76.25 60778[125:SSi:60777.0,717.0,59971.0,59973.0,60385.0,60768.0] || -> . % 76.04/76.25 60779[125:Spt:60778.0,60773.0,60775.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.25 60780[125:Spt:60778.0,60773.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.25 60784[125:Res:60780.0,61.1] always3(s29) || -> . % 76.04/76.25 60785[125:SSi:60784.0,718.0,59974.0,59979.0] || -> . % 76.04/76.25 60786[123:Spt:60785.0,60384.0,60385.0] || until2p7(s28)*+ -> . % 76.04/76.25 60787[123:Spt:60785.0,60384.1] || -> node4(s27)*. % 76.04/76.25 60789[123:MRR:837.0,60787.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.25 60792[123:Res:53.1,60789.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.25 60794[124:Spt:60792.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.25 60796[124:Res:60794.0,61.1] always3(s27) || -> . % 76.04/76.25 60797[124:SSi:60796.0,716.0,59965.0,59970.0,60383.0,60787.0] || -> . % 76.04/76.25 60798[124:Spt:60797.0,60792.0,60794.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.25 60799[124:Spt:60797.0,60792.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.25 60803[124:Res:60799.0,61.1] always3(s28) || -> . % 76.04/76.25 60804[124:SSi:60803.0,717.0,59971.0,59973.0] || -> . % 76.04/76.25 60805[122:Spt:60804.0,60382.0,60383.0] || until2p7(s27)*+ -> . % 76.04/76.25 60806[122:Spt:60804.0,60382.1] || -> node4(s26)*. % 76.04/76.25 60808[122:MRR:840.0,60806.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.25 60811[122:Res:53.1,60808.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.25 60816[123:Spt:60811.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.25 60818[123:Res:60816.0,61.1] always3(s26) || -> . % 76.04/76.25 60819[123:SSi:60818.0,715.0,59962.0,59964.0,60381.0,60806.0] || -> . % 76.04/76.25 60820[123:Spt:60819.0,60811.0,60816.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.25 60821[123:Spt:60819.0,60811.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.25 60825[123:Res:60821.0,61.1] always3(s27) || -> . % 76.04/76.25 60826[123:SSi:60825.0,716.0,59965.0,59970.0] || -> . % 76.04/76.25 60827[121:Spt:60826.0,60380.0,60381.0] || until2p7(s26)*+ -> . % 76.04/76.25 60828[121:Spt:60826.0,60380.1] || -> node4(s25)*. % 76.04/76.25 60830[121:MRR:843.0,60828.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.25 60833[121:Res:53.1,60830.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.25 60835[122:Spt:60833.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.25 60837[122:Res:60835.0,61.1] always3(s25) || -> . % 76.04/76.25 60838[122:SSi:60837.0,714.0,59956.0,59961.0,60379.0,60828.0] || -> . % 76.04/76.25 60839[122:Spt:60838.0,60833.0,60835.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.25 60840[122:Spt:60838.0,60833.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.25 60844[122:Res:60840.0,61.1] always3(s26) || -> . % 76.04/76.25 60845[122:SSi:60844.0,715.0,59962.0,59964.0] || -> . % 76.04/76.25 60846[120:Spt:60845.0,60378.0,60379.0] || until2p7(s25)*+ -> . % 76.04/76.25 60847[120:Spt:60845.0,60378.1] || -> node4(s24)*. % 76.04/76.25 60849[120:MRR:846.0,60847.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.25 60852[120:Res:53.1,60849.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.25 60854[121:Spt:60852.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.25 60856[121:Res:60854.0,61.1] always3(s24) || -> . % 76.04/76.25 60857[121:SSi:60856.0,713.0,59953.0,59955.0,60377.0,60847.0] || -> . % 76.04/76.25 60858[121:Spt:60857.0,60852.0,60854.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.25 60859[121:Spt:60857.0,60852.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.25 60863[121:Res:60859.0,61.1] always3(s25) || -> . % 76.04/76.25 60864[121:SSi:60863.0,714.0,59956.0,59961.0] || -> . % 76.04/76.25 60865[119:Spt:60864.0,60376.0,60377.0] || until2p7(s24)*+ -> . % 76.04/76.25 60866[119:Spt:60864.0,60376.1] || -> node4(s23)*. % 76.04/76.25 60868[119:MRR:849.0,60866.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.25 60871[119:Res:53.1,60868.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.25 60873[120:Spt:60871.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.25 60875[120:Res:60873.0,61.1] always3(s23) || -> . % 76.04/76.25 60876[120:SSi:60875.0,712.0,59947.0,59952.0,60375.0,60866.0] || -> . % 76.04/76.25 60877[120:Spt:60876.0,60871.0,60873.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.25 60878[120:Spt:60876.0,60871.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.25 60882[120:Res:60878.0,61.1] always3(s24) || -> . % 76.04/76.25 60883[120:SSi:60882.0,713.0,59953.0,59955.0] || -> . % 76.04/76.25 60884[118:Spt:60883.0,60374.0,60375.0] || until2p7(s23)*+ -> . % 76.04/76.25 60885[118:Spt:60883.0,60374.1] || -> node4(s22)*. % 76.04/76.25 60887[118:MRR:852.0,60885.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.25 60890[118:Res:53.1,60887.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.25 60895[119:Spt:60890.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.25 60897[119:Res:60895.0,61.1] always3(s22) || -> . % 76.04/76.25 60898[119:SSi:60897.0,711.0,59944.0,59946.0,60373.0,60885.0] || -> . % 76.04/76.25 60899[119:Spt:60898.0,60890.0,60895.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.25 60900[119:Spt:60898.0,60890.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.25 60904[119:Res:60900.0,61.1] always3(s23) || -> . % 76.04/76.25 60905[119:SSi:60904.0,712.0,59947.0,59952.0] || -> . % 76.04/76.25 60906[117:Spt:60905.0,60372.0,60373.0] || until2p7(s22)*+ -> . % 76.04/76.25 60907[117:Spt:60905.0,60372.1] || -> node4(s21)*. % 76.04/76.25 60909[117:MRR:855.0,60907.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.25 60912[117:Res:53.1,60909.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.25 60914[118:Spt:60912.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.25 60916[118:Res:60914.0,61.1] always3(s21) || -> . % 76.04/76.25 60917[118:SSi:60916.0,710.0,59938.0,59943.0,60371.0,60907.0] || -> . % 76.04/76.25 60918[118:Spt:60917.0,60912.0,60914.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.25 60919[118:Spt:60917.0,60912.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.25 60923[118:Res:60919.0,61.1] always3(s22) || -> . % 76.04/76.25 60924[118:SSi:60923.0,711.0,59944.0,59946.0] || -> . % 76.04/76.25 60925[116:Spt:60924.0,60370.0,60371.0] || until2p7(s21)*+ -> . % 76.04/76.25 60926[116:Spt:60924.0,60370.1] || -> node4(s20)*. % 76.04/76.25 60928[116:MRR:858.0,60926.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.25 60931[116:Res:53.1,60928.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.25 60933[117:Spt:60931.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.25 60935[117:Res:60933.0,61.1] always3(s20) || -> . % 76.04/76.25 60936[117:SSi:60935.0,709.0,59935.0,59937.0,60369.0,60926.0] || -> . % 76.04/76.25 60937[117:Spt:60936.0,60931.0,60933.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.25 60938[117:Spt:60936.0,60931.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.25 60942[117:Res:60938.0,61.1] always3(s21) || -> . % 76.04/76.25 60943[117:SSi:60942.0,710.0,59938.0,59943.0] || -> . % 76.04/76.25 60944[115:Spt:60943.0,60368.0,60369.0] || until2p7(s20)*+ -> . % 76.04/76.25 60945[115:Spt:60943.0,60368.1] || -> node4(s19)*. % 76.04/76.25 60947[115:MRR:861.0,60945.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.25 60950[115:Res:53.1,60947.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.25 60952[116:Spt:60950.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.25 60954[116:Res:60952.0,61.1] always3(s19) || -> . % 76.04/76.25 60955[116:SSi:60954.0,708.0,59929.0,59934.0,60367.0,60945.0] || -> . % 76.04/76.25 60956[116:Spt:60955.0,60950.0,60952.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.25 60957[116:Spt:60955.0,60950.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.25 60961[116:Res:60957.0,61.1] always3(s20) || -> . % 76.04/76.25 60962[116:SSi:60961.0,709.0,59935.0,59937.0] || -> . % 76.04/76.25 60963[114:Spt:60962.0,60366.0,60367.0] || until2p7(s19)*+ -> . % 76.04/76.25 60964[114:Spt:60962.0,60366.1] || -> node4(s18)*. % 76.04/76.25 60966[114:MRR:864.0,60964.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.25 60969[114:Res:53.1,60966.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.25 60974[115:Spt:60969.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.25 60976[115:Res:60974.0,61.1] always3(s18) || -> . % 76.04/76.25 60977[115:SSi:60976.0,707.0,59926.0,59928.0,60365.0,60964.0] || -> . % 76.04/76.25 60978[115:Spt:60977.0,60969.0,60974.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.25 60979[115:Spt:60977.0,60969.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.25 60983[115:Res:60979.0,61.1] always3(s19) || -> . % 76.04/76.25 60984[115:SSi:60983.0,708.0,59929.0,59934.0] || -> . % 76.04/76.25 60985[113:Spt:60984.0,60364.0,60365.0] || until2p7(s18)*+ -> . % 76.04/76.25 60986[113:Spt:60984.0,60364.1] || -> node4(s17)*. % 76.04/76.25 60988[113:MRR:867.0,60986.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.25 60991[113:Res:53.1,60988.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.25 60993[114:Spt:60991.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.25 60995[114:Res:60993.0,61.1] always3(s17) || -> . % 76.04/76.25 60996[114:SSi:60995.0,706.0,59920.0,59925.0,60363.0,60986.0] || -> . % 76.04/76.25 60997[114:Spt:60996.0,60991.0,60993.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.25 60998[114:Spt:60996.0,60991.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.25 61002[114:Res:60998.0,61.1] always3(s18) || -> . % 76.04/76.25 61003[114:SSi:61002.0,707.0,59926.0,59928.0] || -> . % 76.04/76.25 61004[112:Spt:61003.0,60362.0,60363.0] || until2p7(s17)*+ -> . % 76.04/76.25 61005[112:Spt:61003.0,60362.1] || -> node4(s16)*. % 76.04/76.25 61007[112:MRR:870.0,61005.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.25 61010[112:Res:53.1,61007.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.25 61012[113:Spt:61010.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.25 61014[113:Res:61012.0,61.1] always3(s16) || -> . % 76.04/76.25 61015[113:SSi:61014.0,705.0,59917.0,59919.0,60361.0,61005.0] || -> . % 76.04/76.25 61016[113:Spt:61015.0,61010.0,61012.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.25 61017[113:Spt:61015.0,61010.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.25 61021[113:Res:61017.0,61.1] always3(s17) || -> . % 76.04/76.25 61022[113:SSi:61021.0,706.0,59920.0,59925.0] || -> . % 76.04/76.25 61023[111:Spt:61022.0,60360.0,60361.0] || until2p7(s16)*+ -> . % 76.04/76.25 61024[111:Spt:61022.0,60360.1] || -> node4(s15)*. % 76.04/76.25 61026[111:MRR:873.0,61024.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.25 61029[111:Res:53.1,61026.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.25 61031[112:Spt:61029.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.25 61033[112:Res:61031.0,61.1] always3(s15) || -> . % 76.04/76.25 61034[112:SSi:61033.0,704.0,59911.0,59916.0,60359.0,61024.0] || -> . % 76.04/76.25 61035[112:Spt:61034.0,61029.0,61031.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.25 61036[112:Spt:61034.0,61029.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.25 61040[112:Res:61036.0,61.1] always3(s16) || -> . % 76.04/76.25 61041[112:SSi:61040.0,705.0,59917.0,59919.0] || -> . % 76.04/76.25 61042[110:Spt:61041.0,60358.0,60359.0] || until2p7(s15)*+ -> . % 76.04/76.25 61043[110:Spt:61041.0,60358.1] || -> node4(s14)*. % 76.04/76.25 61045[110:MRR:876.0,61043.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.25 61048[110:Res:53.1,61045.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.25 61053[111:Spt:61048.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.25 61055[111:Res:61053.0,61.1] always3(s14) || -> . % 76.04/76.25 61056[111:SSi:61055.0,703.0,59908.0,59910.0,60357.0,61043.0] || -> . % 76.04/76.25 61057[111:Spt:61056.0,61048.0,61053.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.25 61058[111:Spt:61056.0,61048.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.25 61062[111:Res:61058.0,61.1] always3(s15) || -> . % 76.04/76.25 61063[111:SSi:61062.0,704.0,59911.0,59916.0] || -> . % 76.04/76.25 61064[109:Spt:61063.0,60356.0,60357.0] || until2p7(s14)*+ -> . % 76.04/76.25 61065[109:Spt:61063.0,60356.1] || -> node4(s13)*. % 76.04/76.25 61067[109:MRR:879.0,61065.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.25 61070[109:Res:53.1,61067.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.25 61072[110:Spt:61070.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.25 61074[110:Res:61072.0,61.1] always3(s13) || -> . % 76.04/76.25 61075[110:SSi:61074.0,702.0,59902.0,59907.0,60355.0,61065.0] || -> . % 76.04/76.25 61076[110:Spt:61075.0,61070.0,61072.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.25 61077[110:Spt:61075.0,61070.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.25 61081[110:Res:61077.0,61.1] always3(s14) || -> . % 76.04/76.25 61082[110:SSi:61081.0,703.0,59908.0,59910.0] || -> . % 76.04/76.25 61083[108:Spt:61082.0,60354.0,60355.0] || until2p7(s13)*+ -> . % 76.04/76.25 61084[108:Spt:61082.0,60354.1] || -> node4(s12)*. % 76.04/76.25 61086[108:MRR:882.0,61084.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.25 61089[108:Res:53.1,61086.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.25 61091[109:Spt:61089.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.25 61093[109:Res:61091.0,61.1] always3(s12) || -> . % 76.04/76.25 61094[109:SSi:61093.0,701.0,59899.0,59901.0,60353.0,61084.0] || -> . % 76.04/76.25 61095[109:Spt:61094.0,61089.0,61091.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.25 61096[109:Spt:61094.0,61089.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.25 61100[109:Res:61096.0,61.1] always3(s13) || -> . % 76.04/76.25 61101[109:SSi:61100.0,702.0,59902.0,59907.0] || -> . % 76.04/76.25 61102[107:Spt:61101.0,60352.0,60353.0] || until2p7(s12)*+ -> . % 76.04/76.25 61103[107:Spt:61101.0,60352.1] || -> node4(s11)*. % 76.04/76.25 61105[107:MRR:885.0,61103.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.25 61108[107:Res:53.1,61105.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.25 61110[108:Spt:61108.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.25 61112[108:Res:61110.0,61.1] always3(s11) || -> . % 76.04/76.25 61113[108:SSi:61112.0,700.0,59893.0,59898.0,60351.0,61103.0] || -> . % 76.04/76.25 61114[108:Spt:61113.0,61108.0,61110.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.25 61115[108:Spt:61113.0,61108.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.25 61119[108:Res:61115.0,61.1] always3(s12) || -> . % 76.04/76.25 61120[108:SSi:61119.0,701.0,59899.0,59901.0] || -> . % 76.04/76.25 61121[106:Spt:61120.0,60350.0,60351.0] || until2p7(s11)*+ -> . % 76.04/76.25 61122[106:Spt:61120.0,60350.1] || -> node4(s10)*. % 76.04/76.25 61124[106:MRR:888.0,61122.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.25 61127[106:Res:53.1,61124.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.25 61132[107:Spt:61127.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.25 61134[107:Res:61132.0,61.1] always3(s10) || -> . % 76.04/76.25 61135[107:SSi:61134.0,699.0,59890.0,59892.0,60349.0,61122.0] || -> . % 76.04/76.25 61136[107:Spt:61135.0,61127.0,61132.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.25 61137[107:Spt:61135.0,61127.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.25 61141[107:Res:61137.0,61.1] always3(s11) || -> . % 76.04/76.25 61142[107:SSi:61141.0,700.0,59893.0,59898.0] || -> . % 76.04/76.25 61143[105:Spt:61142.0,60348.0,60349.0] || until2p7(s10)*+ -> . % 76.04/76.25 61144[105:Spt:61142.0,60348.1] || -> node4(s9)*. % 76.04/76.25 61146[105:MRR:891.0,61144.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.25 61149[105:Res:53.1,61146.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.25 61151[106:Spt:61149.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.25 61153[106:Res:61151.0,61.1] always3(s9) || -> . % 76.04/76.25 61154[106:SSi:61153.0,698.0,59884.0,59889.0,60347.0,61144.0] || -> . % 76.04/76.25 61155[106:Spt:61154.0,61149.0,61151.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.25 61156[106:Spt:61154.0,61149.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.25 61160[106:Res:61156.0,61.1] always3(s10) || -> . % 76.04/76.25 61161[106:SSi:61160.0,699.0,59890.0,59892.0] || -> . % 76.04/76.25 61162[104:Spt:61161.0,60344.0,60347.0] || until2p7(s9)*+ -> . % 76.04/76.25 61163[104:Spt:61161.0,60344.1] || -> node4(s8)*. % 76.04/76.25 61165[104:MRR:894.0,61163.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.25 61168[104:Res:53.1,61165.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.25 61170[104:MRR:61168.0,60329.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.25 61172[104:Res:61170.0,61.1] always3(s9) || -> . % 76.04/76.25 61173[104:SSi:61172.0,698.0,59884.0,59889.0] || -> . % 76.04/76.25 61174[101:Spt:61173.0,60172.2,60174.0] || xuntil6(s48)*+ -> . % 76.04/76.25 61175[101:Spt:61173.0,60172.0,60172.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.25 61176[101:Res:53.1,61175.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.25 61178[101:MRR:61176.0,60161.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.25 61181[101:Res:61178.0,61.1] always3(s49) || -> . % 76.04/76.25 61182[101:SSi:61181.0,50.0,738.0] || -> . % 76.04/76.25 61183[100:Spt:61182.0,60165.1,60170.0] || xuntil6(s47)* -> . % 76.04/76.25 61184[100:Spt:61182.0,60165.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.25 61187[100:Res:61184.0,61.1] always3(s47) || -> . % 76.04/76.25 61188[100:SSi:61187.0,736.0,60155.0] || -> . % 76.04/76.25 61189[98:Spt:61188.0,60146.2,60154.0] || xuntil6(s46)*+ -> . % 76.04/76.25 61190[98:Spt:61188.0,60146.0,60146.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.25 61191[98:Res:53.1,61190.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.25 61193[98:MRR:61191.0,60138.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.25 61195[98:Res:61193.0,61.1] always3(s47) || -> . % 76.04/76.25 61196[98:SSi:61195.0,736.0] || -> . % 76.04/76.25 61197[97:Spt:61196.0,60142.1,60144.0] || xuntil6(s45)* -> . % 76.04/76.25 61198[97:Spt:61196.0,60142.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.25 61201[97:Res:61198.0,61.1] always3(s45) || -> . % 76.04/76.25 61202[97:SSi:61201.0,734.0,60132.0] || -> . % 76.04/76.25 61203[95:Spt:61202.0,60126.2,60131.0] || xuntil6(s44)*+ -> . % 76.04/76.25 61204[95:Spt:61202.0,60126.0,60126.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.25 61205[95:Res:53.1,61204.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.25 61207[95:MRR:61205.0,60118.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.25 61210[95:Res:61207.0,61.1] always3(s45) || -> . % 76.04/76.25 61211[95:SSi:61210.0,734.0] || -> . % 76.04/76.25 61212[94:Spt:61211.0,60122.1,60124.0] || xuntil6(s43)* -> . % 76.04/76.25 61213[94:Spt:61211.0,60122.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.25 61216[94:Res:61213.0,61.1] always3(s43) || -> . % 76.04/76.25 61217[94:SSi:61216.0,732.0,60112.0] || -> . % 76.04/76.25 61218[92:Spt:61217.0,60109.2,60111.0] || xuntil6(s42)*+ -> . % 76.04/76.25 61219[92:Spt:61217.0,60109.0,60109.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.25 61220[92:Res:53.1,61219.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.25 61222[92:MRR:61220.0,60098.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.25 61224[92:Res:61222.0,61.1] always3(s43) || -> . % 76.04/76.25 61225[92:SSi:61224.0,732.0] || -> . % 76.04/76.25 61226[91:Spt:61225.0,60102.1,60107.0] || xuntil6(s41)* -> . % 76.04/76.25 61227[91:Spt:61225.0,60102.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.25 61230[91:Res:61227.0,61.1] always3(s41) || -> . % 76.04/76.25 61231[91:SSi:61230.0,730.0,60092.0] || -> . % 76.04/76.25 61232[89:Spt:61231.0,60083.2,60091.0] || xuntil6(s40)*+ -> . % 76.04/76.25 61233[89:Spt:61231.0,60083.0,60083.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.25 61234[89:Res:53.1,61233.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.25 61236[89:MRR:61234.0,60075.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.25 61238[89:Res:61236.0,61.1] always3(s41) || -> . % 76.04/76.25 61239[89:SSi:61238.0,730.0] || -> . % 76.04/76.25 61240[88:Spt:61239.0,60079.1,60081.0] || xuntil6(s39)* -> . % 76.04/76.25 61241[88:Spt:61239.0,60079.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.25 61244[88:Res:61241.0,61.1] always3(s39) || -> . % 76.04/76.25 61245[88:SSi:61244.0,728.0,60069.0] || -> . % 76.04/76.25 61246[86:Spt:61245.0,60063.2,60068.0] || xuntil6(s38)*+ -> . % 76.04/76.25 61247[86:Spt:61245.0,60063.0,60063.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.25 61248[86:Res:53.1,61247.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.25 61250[86:MRR:61248.0,60055.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.25 61252[86:Res:61250.0,61.1] always3(s39) || -> . % 76.04/76.25 61253[86:SSi:61252.0,728.0] || -> . % 76.04/76.25 61254[85:Spt:61253.0,60059.1,60061.0] || xuntil6(s37)* -> . % 76.04/76.25 61255[85:Spt:61253.0,60059.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.25 61258[85:Res:61255.0,61.1] always3(s37) || -> . % 76.04/76.25 61259[85:SSi:61258.0,726.0,60049.0] || -> . % 76.04/76.25 61260[83:Spt:61259.0,60046.2,60048.0] || xuntil6(s36)*+ -> . % 76.04/76.25 61261[83:Spt:61259.0,60046.0,60046.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.25 61262[83:Res:53.1,61261.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.25 61264[83:MRR:61262.0,60035.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.25 61266[83:Res:61264.0,61.1] always3(s37) || -> . % 76.04/76.25 61267[83:SSi:61266.0,726.0] || -> . % 76.04/76.25 61268[82:Spt:61267.0,60039.1,60044.0] || xuntil6(s35)* -> . % 76.04/76.25 61269[82:Spt:61267.0,60039.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.25 61272[82:Res:61269.0,61.1] always3(s35) || -> . % 76.04/76.25 61273[82:SSi:61272.0,724.0,60029.0] || -> . % 76.04/76.25 61274[80:Spt:61273.0,60020.2,60028.0] || xuntil6(s34)*+ -> . % 76.04/76.25 61275[80:Spt:61273.0,60020.0,60020.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.25 61276[80:Res:53.1,61275.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.25 61278[80:MRR:61276.0,60012.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.25 61280[80:Res:61278.0,61.1] always3(s35) || -> . % 76.04/76.25 61281[80:SSi:61280.0,724.0] || -> . % 76.04/76.25 61282[79:Spt:61281.0,60016.1,60018.0] || xuntil6(s33)* -> . % 76.04/76.25 61283[79:Spt:61281.0,60016.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.25 61286[79:Res:61283.0,61.1] always3(s33) || -> . % 76.04/76.25 61287[79:SSi:61286.0,722.0,60006.0] || -> . % 76.04/76.25 61288[77:Spt:61287.0,60000.2,60005.0] || xuntil6(s32)*+ -> . % 76.04/76.25 61289[77:Spt:61287.0,60000.0,60000.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.25 61290[77:Res:53.1,61289.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.25 61292[77:MRR:61290.0,59992.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.25 61294[77:Res:61292.0,61.1] always3(s33) || -> . % 76.04/76.25 61295[77:SSi:61294.0,722.0] || -> . % 76.04/76.25 61296[76:Spt:61295.0,59996.1,59998.0] || xuntil6(s31)* -> . % 76.04/76.25 61297[76:Spt:61295.0,59996.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.25 61300[76:Res:61297.0,61.1] always3(s31) || -> . % 76.04/76.25 61301[76:SSi:61300.0,720.0,59983.0] || -> . % 76.04/76.25 61302[74:Spt:61301.0,59981.2,59982.0] || xuntil6(s30)*+ -> . % 76.04/76.25 61303[74:Spt:61301.0,59981.0,59981.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.25 61304[74:Res:53.1,61303.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.25 61306[75:Spt:61304.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.25 61308[75:Res:61306.0,61.1] always3(s31) || -> . % 76.04/76.25 61309[75:SSi:61308.0,720.0] || -> . % 76.04/76.25 61310[75:Spt:61309.0,61304.1,61306.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.25 61311[75:Spt:61309.0,61304.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.25 61314[75:Res:61311.0,61.1] always3(s30) || -> . % 76.04/76.25 61315[75:SSi:61314.0,719.0,59980.0] || -> . % 76.04/76.25 61316[73:Spt:61315.0,59975.2,59979.0] || xuntil6(s29)*+ -> . % 76.04/76.25 61317[73:Spt:61315.0,59975.0,59975.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.25 61318[73:Res:53.1,61317.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.25 61320[74:Spt:61318.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.25 61322[74:Res:61320.0,61.1] always3(s30) || -> . % 76.04/76.25 61323[74:SSi:61322.0,719.0] || -> . % 76.04/76.25 61324[74:Spt:61323.0,61318.1,61320.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.25 61325[74:Spt:61323.0,61318.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.25 61328[74:Res:61325.0,61.1] always3(s29) || -> . % 76.04/76.25 61329[74:SSi:61328.0,718.0,59974.0] || -> . % 76.04/76.25 61330[72:Spt:61329.0,59972.2,59973.0] || xuntil6(s28)*+ -> . % 76.04/76.25 61331[72:Spt:61329.0,59972.0,59972.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.25 61332[72:Res:53.1,61331.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.25 61334[73:Spt:61332.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.25 61336[73:Res:61334.0,61.1] always3(s29) || -> . % 76.04/76.25 61337[73:SSi:61336.0,718.0] || -> . % 76.04/76.25 61338[73:Spt:61337.0,61332.1,61334.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.25 61339[73:Spt:61337.0,61332.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.25 61342[73:Res:61339.0,61.1] always3(s28) || -> . % 76.04/76.25 61343[73:SSi:61342.0,717.0,59971.0] || -> . % 76.04/76.25 61344[71:Spt:61343.0,59966.2,59970.0] || xuntil6(s27)*+ -> . % 76.04/76.25 61345[71:Spt:61343.0,59966.0,59966.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.25 61346[71:Res:53.1,61345.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.25 61348[72:Spt:61346.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.25 61350[72:Res:61348.0,61.1] always3(s28) || -> . % 76.04/76.25 61351[72:SSi:61350.0,717.0] || -> . % 76.04/76.25 61352[72:Spt:61351.0,61346.1,61348.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.25 61353[72:Spt:61351.0,61346.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.25 61356[72:Res:61353.0,61.1] always3(s27) || -> . % 76.04/76.25 61357[72:SSi:61356.0,716.0,59965.0] || -> . % 76.04/76.25 61358[70:Spt:61357.0,59963.2,59964.0] || xuntil6(s26)*+ -> . % 76.04/76.25 61359[70:Spt:61357.0,59963.0,59963.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.25 61360[70:Res:53.1,61359.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.25 61362[71:Spt:61360.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.25 61364[71:Res:61362.0,61.1] always3(s27) || -> . % 76.04/76.25 61365[71:SSi:61364.0,716.0] || -> . % 76.04/76.25 61366[71:Spt:61365.0,61360.1,61362.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.25 61367[71:Spt:61365.0,61360.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.25 61370[71:Res:61367.0,61.1] always3(s26) || -> . % 76.04/76.25 61371[71:SSi:61370.0,715.0,59962.0] || -> . % 76.04/76.25 61372[69:Spt:61371.0,59957.2,59961.0] || xuntil6(s25)*+ -> . % 76.04/76.25 61373[69:Spt:61371.0,59957.0,59957.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.25 61374[69:Res:53.1,61373.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.25 61376[70:Spt:61374.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.25 61378[70:Res:61376.0,61.1] always3(s26) || -> . % 76.04/76.25 61379[70:SSi:61378.0,715.0] || -> . % 76.04/76.25 61380[70:Spt:61379.0,61374.1,61376.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.25 61381[70:Spt:61379.0,61374.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.25 61384[70:Res:61381.0,61.1] always3(s25) || -> . % 76.04/76.25 61385[70:SSi:61384.0,714.0,59956.0] || -> . % 76.04/76.25 61386[68:Spt:61385.0,59954.2,59955.0] || xuntil6(s24)*+ -> . % 76.04/76.25 61387[68:Spt:61385.0,59954.0,59954.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.25 61388[68:Res:53.1,61387.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.25 61393[69:Spt:61388.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.25 61395[69:Res:61393.0,61.1] always3(s24) || -> . % 76.04/76.25 61396[69:SSi:61395.0,713.0,59953.0] || -> . % 76.04/76.25 61397[69:Spt:61396.0,61388.0,61393.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.25 61398[69:Spt:61396.0,61388.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.25 61402[69:Res:61398.0,61.1] always3(s25) || -> . % 76.04/76.25 61403[69:SSi:61402.0,714.0] || -> . % 76.04/76.25 61404[67:Spt:61403.0,59948.2,59952.0] || xuntil6(s23)*+ -> . % 76.04/76.25 61405[67:Spt:61403.0,59948.0,59948.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.25 61406[67:Res:53.1,61405.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.25 61408[68:Spt:61406.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.25 61410[68:Res:61408.0,61.1] always3(s24) || -> . % 76.04/76.25 61411[68:SSi:61410.0,713.0] || -> . % 76.04/76.25 61412[68:Spt:61411.0,61406.1,61408.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.25 61413[68:Spt:61411.0,61406.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.25 61416[68:Res:61413.0,61.1] always3(s23) || -> . % 76.04/76.25 61417[68:SSi:61416.0,712.0,59947.0] || -> . % 76.04/76.25 61418[66:Spt:61417.0,59945.2,59946.0] || xuntil6(s22)*+ -> . % 76.04/76.25 61419[66:Spt:61417.0,59945.0,59945.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.25 61420[66:Res:53.1,61419.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.25 61422[67:Spt:61420.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.25 61424[67:Res:61422.0,61.1] always3(s23) || -> . % 76.04/76.25 61425[67:SSi:61424.0,712.0] || -> . % 76.04/76.25 61426[67:Spt:61425.0,61420.1,61422.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.25 61427[67:Spt:61425.0,61420.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.25 61430[67:Res:61427.0,61.1] always3(s22) || -> . % 76.04/76.25 61431[67:SSi:61430.0,711.0,59944.0] || -> . % 76.04/76.25 61432[65:Spt:61431.0,59939.2,59943.0] || xuntil6(s21)*+ -> . % 76.04/76.25 61433[65:Spt:61431.0,59939.0,59939.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.25 61434[65:Res:53.1,61433.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.25 61439[66:Spt:61434.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.25 61441[66:Res:61439.0,61.1] always3(s21) || -> . % 76.04/76.25 61442[66:SSi:61441.0,710.0,59938.0] || -> . % 76.04/76.25 61443[66:Spt:61442.0,61434.0,61439.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.25 61444[66:Spt:61442.0,61434.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.25 61448[66:Res:61444.0,61.1] always3(s22) || -> . % 76.04/76.25 61449[66:SSi:61448.0,711.0] || -> . % 76.04/76.25 61450[64:Spt:61449.0,59936.2,59937.0] || xuntil6(s20)*+ -> . % 76.04/76.25 61451[64:Spt:61449.0,59936.0,59936.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.25 61452[64:Res:53.1,61451.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.25 61454[65:Spt:61452.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.25 61456[65:Res:61454.0,61.1] always3(s21) || -> . % 76.04/76.25 61457[65:SSi:61456.0,710.0] || -> . % 76.04/76.25 61458[65:Spt:61457.0,61452.1,61454.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.25 61459[65:Spt:61457.0,61452.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.25 61462[65:Res:61459.0,61.1] always3(s20) || -> . % 76.04/76.25 61463[65:SSi:61462.0,709.0,59935.0] || -> . % 76.04/76.25 61464[63:Spt:61463.0,59930.2,59934.0] || xuntil6(s19)*+ -> . % 76.04/76.25 61465[63:Spt:61463.0,59930.0,59930.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.25 61466[63:Res:53.1,61465.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.25 61468[64:Spt:61466.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.25 61470[64:Res:61468.0,61.1] always3(s20) || -> . % 76.04/76.25 61471[64:SSi:61470.0,709.0] || -> . % 76.04/76.25 61472[64:Spt:61471.0,61466.1,61468.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.25 61473[64:Spt:61471.0,61466.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.25 61476[64:Res:61473.0,61.1] always3(s19) || -> . % 76.04/76.25 61477[64:SSi:61476.0,708.0,59929.0] || -> . % 76.04/76.25 61478[62:Spt:61477.0,59927.2,59928.0] || xuntil6(s18)*+ -> . % 76.04/76.25 61479[62:Spt:61477.0,59927.0,59927.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.25 61480[62:Res:53.1,61479.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.25 61485[63:Spt:61480.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.25 61487[63:Res:61485.0,61.1] always3(s18) || -> . % 76.04/76.25 61488[63:SSi:61487.0,707.0,59926.0] || -> . % 76.04/76.25 61489[63:Spt:61488.0,61480.0,61485.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.25 61490[63:Spt:61488.0,61480.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.25 61494[63:Res:61490.0,61.1] always3(s19) || -> . % 76.04/76.25 61495[63:SSi:61494.0,708.0] || -> . % 76.04/76.25 61496[61:Spt:61495.0,59921.2,59925.0] || xuntil6(s17)*+ -> . % 76.04/76.25 61497[61:Spt:61495.0,59921.0,59921.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.25 61498[61:Res:53.1,61497.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.25 61500[62:Spt:61498.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.25 61502[62:Res:61500.0,61.1] always3(s18) || -> . % 76.04/76.25 61503[62:SSi:61502.0,707.0] || -> . % 76.04/76.25 61504[62:Spt:61503.0,61498.1,61500.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.25 61505[62:Spt:61503.0,61498.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.25 61508[62:Res:61505.0,61.1] always3(s17) || -> . % 76.04/76.25 61509[62:SSi:61508.0,706.0,59920.0] || -> . % 76.04/76.25 61510[60:Spt:61509.0,59918.2,59919.0] || xuntil6(s16)*+ -> . % 76.04/76.25 61511[60:Spt:61509.0,59918.0,59918.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.25 61512[60:Res:53.1,61511.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.25 61514[61:Spt:61512.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.25 61516[61:Res:61514.0,61.1] always3(s17) || -> . % 76.04/76.25 61517[61:SSi:61516.0,706.0] || -> . % 76.04/76.25 61518[61:Spt:61517.0,61512.1,61514.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.25 61519[61:Spt:61517.0,61512.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.25 61522[61:Res:61519.0,61.1] always3(s16) || -> . % 76.04/76.25 61523[61:SSi:61522.0,705.0,59917.0] || -> . % 76.04/76.25 61524[59:Spt:61523.0,59912.2,59916.0] || xuntil6(s15)*+ -> . % 76.04/76.25 61525[59:Spt:61523.0,59912.0,59912.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.25 61526[59:Res:53.1,61525.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.25 61531[60:Spt:61526.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.25 61533[60:Res:61531.0,61.1] always3(s15) || -> . % 76.04/76.25 61534[60:SSi:61533.0,704.0,59911.0] || -> . % 76.04/76.25 61535[60:Spt:61534.0,61526.0,61531.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.25 61536[60:Spt:61534.0,61526.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.25 61540[60:Res:61536.0,61.1] always3(s16) || -> . % 76.04/76.25 61541[60:SSi:61540.0,705.0] || -> . % 76.04/76.25 61542[58:Spt:61541.0,59909.2,59910.0] || xuntil6(s14)*+ -> . % 76.04/76.25 61543[58:Spt:61541.0,59909.0,59909.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.25 61544[58:Res:53.1,61543.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.25 61546[59:Spt:61544.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.25 61548[59:Res:61546.0,61.1] always3(s15) || -> . % 76.04/76.25 61549[59:SSi:61548.0,704.0] || -> . % 76.04/76.25 61550[59:Spt:61549.0,61544.1,61546.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.25 61551[59:Spt:61549.0,61544.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.25 61554[59:Res:61551.0,61.1] always3(s14) || -> . % 76.04/76.25 61555[59:SSi:61554.0,703.0,59908.0] || -> . % 76.04/76.25 61556[57:Spt:61555.0,59903.2,59907.0] || xuntil6(s13)*+ -> . % 76.04/76.25 61557[57:Spt:61555.0,59903.0,59903.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.25 61558[57:Res:53.1,61557.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.25 61560[58:Spt:61558.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.25 61562[58:Res:61560.0,61.1] always3(s14) || -> . % 76.04/76.25 61563[58:SSi:61562.0,703.0] || -> . % 76.04/76.25 61564[58:Spt:61563.0,61558.1,61560.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.25 61565[58:Spt:61563.0,61558.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.25 61568[58:Res:61565.0,61.1] always3(s13) || -> . % 76.04/76.25 61569[58:SSi:61568.0,702.0,59902.0] || -> . % 76.04/76.25 61570[56:Spt:61569.0,59900.2,59901.0] || xuntil6(s12)*+ -> . % 76.04/76.25 61571[56:Spt:61569.0,59900.0,59900.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.25 61572[56:Res:53.1,61571.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.25 61577[57:Spt:61572.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.25 61579[57:Res:61577.0,61.1] always3(s12) || -> . % 76.04/76.25 61580[57:SSi:61579.0,701.0,59899.0] || -> . % 76.04/76.25 61581[57:Spt:61580.0,61572.0,61577.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.25 61582[57:Spt:61580.0,61572.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.25 61586[57:Res:61582.0,61.1] always3(s13) || -> . % 76.04/76.25 61587[57:SSi:61586.0,702.0] || -> . % 76.04/76.25 61588[55:Spt:61587.0,59894.2,59898.0] || xuntil6(s11)*+ -> . % 76.04/76.25 61589[55:Spt:61587.0,59894.0,59894.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.25 61590[55:Res:53.1,61589.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.25 61592[56:Spt:61590.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.25 61594[56:Res:61592.0,61.1] always3(s12) || -> . % 76.04/76.25 61595[56:SSi:61594.0,701.0] || -> . % 76.04/76.25 61596[56:Spt:61595.0,61590.1,61592.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.25 61597[56:Spt:61595.0,61590.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.25 61600[56:Res:61597.0,61.1] always3(s11) || -> . % 76.04/76.25 61601[56:SSi:61600.0,700.0,59893.0] || -> . % 76.04/76.25 61602[54:Spt:61601.0,59891.2,59892.0] || xuntil6(s10)*+ -> . % 76.04/76.25 61603[54:Spt:61601.0,59891.0,59891.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.25 61604[54:Res:53.1,61603.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.25 61606[55:Spt:61604.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.25 61608[55:Res:61606.0,61.1] always3(s11) || -> . % 76.04/76.25 61609[55:SSi:61608.0,700.0] || -> . % 76.04/76.25 61610[55:Spt:61609.0,61604.1,61606.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.25 61611[55:Spt:61609.0,61604.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.25 61614[55:Res:61611.0,61.1] always3(s10) || -> . % 76.04/76.25 61615[55:SSi:61614.0,699.0,59890.0] || -> . % 76.04/76.25 61616[53:Spt:61615.0,59885.2,59889.0] || xuntil6(s9)*+ -> . % 76.04/76.25 61617[53:Spt:61615.0,59885.0,59885.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.25 61618[53:Res:53.1,61617.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.25 61623[54:Spt:61618.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.25 61625[54:Res:61623.0,61.1] always3(s9) || -> . % 76.04/76.25 61626[54:SSi:61625.0,698.0,59884.0] || -> . % 76.04/76.25 61627[54:Spt:61626.0,61618.0,61623.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.25 61628[54:Spt:61626.0,61618.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.25 61632[54:Res:61628.0,61.1] always3(s10) || -> . % 76.04/76.25 61633[54:SSi:61632.0,699.0] || -> . % 76.04/76.25 61634[52:Spt:61633.0,59882.2,59883.0] || xuntil6(s8)*+ -> . % 76.04/76.25 61635[52:Spt:61633.0,59882.0,59882.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.25 61636[52:Res:53.1,61635.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.25 61638[53:Spt:61636.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.25 61640[53:Res:61638.0,61.1] always3(s9) || -> . % 76.04/76.25 61641[53:SSi:61640.0,698.0] || -> . % 76.04/76.25 61642[53:Spt:61641.0,61636.1,61638.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.25 61643[53:Spt:61641.0,61636.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.25 61646[53:Res:61643.0,61.1] always3(s8) || -> . % 76.04/76.25 61647[53:SSi:61646.0,697.0,59881.0] || -> . % 76.04/76.25 61648[51:Spt:61647.0,59876.2,59880.0] || xuntil6(s7)*+ -> . % 76.04/76.25 61649[51:Spt:61647.0,59876.0,59876.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.25 61650[51:Res:53.1,61649.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.25 61652[52:Spt:61650.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.25 61654[52:Res:61652.0,61.1] always3(s7) || -> . % 76.04/76.25 61655[52:SSi:61654.0,696.0,59875.0] || -> . % 76.04/76.25 61656[52:Spt:61655.0,61650.0,61652.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.25 61657[52:Spt:61655.0,61650.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.25 61661[52:Res:61657.0,61.1] always3(s8) || -> . % 76.04/76.25 61662[52:SSi:61661.0,697.0] || -> . % 76.04/76.25 61663[50:Spt:61662.0,59873.2,59874.0] || xuntil6(s6)*+ -> . % 76.04/76.25 61664[50:Spt:61662.0,59873.0,59873.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.25 61665[50:Res:53.1,61664.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.25 61670[51:Spt:61665.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.25 61672[51:Res:61670.0,61.1] always3(s6) || -> . % 76.04/76.25 61673[51:SSi:61672.0,695.0,59872.0] || -> . % 76.04/76.25 61674[51:Spt:61673.0,61665.0,61670.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.25 61675[51:Spt:61673.0,61665.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.25 61679[51:Res:61675.0,61.1] always3(s7) || -> . % 76.04/76.25 61680[51:SSi:61679.0,696.0] || -> . % 76.04/76.25 61681[49:Spt:61680.0,59867.2,59871.0] || xuntil6(s5)*+ -> . % 76.04/76.25 61682[49:Spt:61680.0,59867.0,59867.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.25 61683[49:Res:53.1,61682.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.25 61685[50:Spt:61683.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.25 61687[50:Res:61685.0,61.1] always3(s5) || -> . % 76.04/76.25 61688[50:SSi:61687.0,694.0,59866.0] || -> . % 76.04/76.25 61689[50:Spt:61688.0,61683.0,61685.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.25 61690[50:Spt:61688.0,61683.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.25 61694[50:Res:61690.0,61.1] always3(s6) || -> . % 76.04/76.25 61695[50:SSi:61694.0,695.0] || -> . % 76.04/76.25 61696[48:Spt:61695.0,59864.2,59865.0] || xuntil6(s4)*+ -> . % 76.04/76.25 61697[48:Spt:61695.0,59864.0,59864.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.25 61698[48:Res:53.1,61697.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.25 61700[49:Spt:61698.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.25 61702[49:Res:61700.0,61.1] always3(s4) || -> . % 76.04/76.25 61703[49:SSi:61702.0,693.0,59863.0] || -> . % 76.04/76.25 61704[49:Spt:61703.0,61698.0,61700.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.25 61705[49:Spt:61703.0,61698.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.25 61709[49:Res:61705.0,61.1] always3(s5) || -> . % 76.04/76.25 61710[49:SSi:61709.0,694.0] || -> . % 76.04/76.25 61711[47:Spt:61710.0,59858.2,59862.0] || xuntil6(s3)*+ -> . % 76.04/76.25 61712[47:Spt:61710.0,59858.0,59858.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.25 61713[47:Res:53.1,61712.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.25 61718[48:Spt:61713.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.25 61720[48:Res:61718.0,61.1] always3(s3) || -> . % 76.04/76.25 61721[48:SSi:61720.0,692.0,59857.0] || -> . % 76.04/76.25 61722[48:Spt:61721.0,61713.0,61718.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.25 61723[48:Spt:61721.0,61713.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.25 61727[48:Res:61723.0,61.1] always3(s4) || -> . % 76.04/76.25 61728[48:SSi:61727.0,693.0] || -> . % 76.04/76.25 61729[46:Spt:61728.0,59855.2,59856.0] || xuntil6(s2)*+ -> . % 76.04/76.25 61730[46:Spt:61728.0,59855.0,59855.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.25 61731[46:Res:53.1,61730.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.25 61733[47:Spt:61731.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.25 61735[47:Res:61733.0,61.1] always3(s2) || -> . % 76.04/76.25 61736[47:SSi:61735.0,691.0,59854.0] || -> . % 76.04/76.25 61737[47:Spt:61736.0,61731.0,61733.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.25 61738[47:Spt:61736.0,61731.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.25 61742[47:Res:61738.0,61.1] always3(s3) || -> . % 76.04/76.25 61743[47:SSi:61742.0,692.0] || -> . % 76.04/76.25 61744[45:Spt:61743.0,59846.2,59853.0] || xuntil6(s1)*+ -> . % 76.04/76.25 61745[45:Spt:61743.0,59846.0,59846.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.25 61746[45:Res:53.1,61745.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.25 61748[46:Spt:61746.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.25 61750[46:Res:61748.0,61.1] always3(s1) || -> . % 76.04/76.25 61751[46:SSi:61750.0,690.0,59845.0] || -> . % 76.04/76.25 61752[46:Spt:61751.0,61746.0,61748.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.25 61753[46:Spt:61751.0,61746.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.25 61758[46:Res:61753.0,61.1] always3(s2) || -> . % 76.04/76.25 61759[46:SSi:61758.0,691.0] || -> . % 76.04/76.25 61760[44:Spt:61759.0,74.0,59844.0] || xuntil6(s0)*+ -> . % 76.04/76.25 61761[44:Spt:61759.0,74.1] || -> node4(s0)*. % 76.04/76.25 61762[44:MRR:758.1,61760.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.25 61764[44:Res:61762.0,61.1] always3(s1) || -> . % 76.04/76.25 61765[44:SSi:61764.0,690.0] || -> . % 76.04/76.25 61766[43:Spt:61765.0,59834.0,59838.0] || trans(s49,s8)*+ -> . % 76.04/76.25 61767[43:Spt:61765.0,59834.1,59834.2,59834.3,59834.4,59834.5,59834.6,59834.7,59834.8] || -> trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.25 61769[43:MRR:59835.0,61766.0] || -> trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.25 61770[43:MRR:59837.1,61766.0] xuntil6(s49) || -> trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.25 61771[44:Spt:61767.0] || -> trans(s49,s7)*. % 76.04/76.25 61772[44:Res:61771.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s7)*. % 76.04/76.25 61774[44:Res:61771.0,60.0] || -> node2(s49,s7)*. % 76.04/76.25 61775[44:SSi:61772.1,50.0,738.0] xuntil6(s49) || -> until2p7(s7)*. % 76.04/76.25 61776[44:Res:61774.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)*. % 76.04/76.25 61777[45:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.25 61778[45:MRR:176.0,61777.0] || -> until5(s1)*. % 76.04/76.25 61779[45:MRR:60283.0,61778.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.25 61783[46:Spt:61779.2] || -> xuntil6(s1)*. % 76.04/76.25 61784[46:MRR:175.0,61783.0] || -> until5(s2)*. % 76.04/76.25 61785[46:MRR:60279.0,61784.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.25 61789[47:Spt:61785.2] || -> xuntil6(s2)*. % 76.04/76.25 61790[47:MRR:174.0,61789.0] || -> until5(s3)*. % 76.04/76.25 61791[47:MRR:60275.0,61790.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.25 61792[48:Spt:61791.2] || -> xuntil6(s3)*. % 76.04/76.25 61793[48:MRR:173.0,61792.0] || -> until5(s4)*. % 76.04/76.25 61794[48:MRR:60274.0,61793.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.25 61798[49:Spt:61794.2] || -> xuntil6(s4)*. % 76.04/76.25 61799[49:MRR:172.0,61798.0] || -> until5(s5)*. % 76.04/76.25 61800[49:MRR:60267.0,61799.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.25 61801[50:Spt:61800.2] || -> xuntil6(s5)*. % 76.04/76.25 61802[50:MRR:171.0,61801.0] || -> until5(s6)*. % 76.04/76.25 61803[50:MRR:60263.0,61802.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.25 61807[51:Spt:61803.2] || -> xuntil6(s6)*. % 76.04/76.25 61808[51:MRR:170.0,61807.0] || -> until5(s7)*. % 76.04/76.25 61809[51:MRR:60259.0,61808.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.25 61810[52:Spt:61809.2] || -> xuntil6(s7)*. % 76.04/76.25 61811[52:MRR:169.0,61810.0] || -> until5(s8)*. % 76.04/76.25 61812[52:MRR:60255.0,61811.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.25 61816[53:Spt:61812.2] || -> xuntil6(s8)*. % 76.04/76.25 61817[53:MRR:168.0,61816.0] || -> until5(s9)*. % 76.04/76.25 61818[53:MRR:60254.0,61817.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.25 61819[54:Spt:61818.2] || -> xuntil6(s9)*. % 76.04/76.25 61820[54:MRR:167.0,61819.0] || -> until5(s10)*. % 76.04/76.25 61821[54:MRR:60244.0,61820.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.25 61825[55:Spt:61821.2] || -> xuntil6(s10)*. % 76.04/76.25 61826[55:MRR:166.0,61825.0] || -> until5(s11)*. % 76.04/76.25 61827[55:MRR:60243.0,61826.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.25 61828[56:Spt:61827.2] || -> xuntil6(s11)*. % 76.04/76.25 61829[56:MRR:165.0,61828.0] || -> until5(s12)*. % 76.04/76.25 61830[56:MRR:60236.0,61829.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.25 61834[57:Spt:61830.2] || -> xuntil6(s12)*. % 76.04/76.25 61835[57:MRR:164.0,61834.0] || -> until5(s13)*. % 76.04/76.25 61836[57:MRR:60235.0,61835.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.25 61837[58:Spt:61836.2] || -> xuntil6(s13)*. % 76.04/76.25 61838[58:MRR:163.0,61837.0] || -> until5(s14)*. % 76.04/76.25 61839[58:MRR:60228.0,61838.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.25 61843[59:Spt:61839.2] || -> xuntil6(s14)*. % 76.04/76.25 61844[59:MRR:162.0,61843.0] || -> until5(s15)*. % 76.04/76.25 61845[59:MRR:60224.0,61844.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.25 61846[60:Spt:61845.2] || -> xuntil6(s15)*. % 76.04/76.25 61847[60:MRR:161.0,61846.0] || -> until5(s16)*. % 76.04/76.25 61848[60:MRR:60223.0,61847.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.25 61852[61:Spt:61848.2] || -> xuntil6(s16)*. % 76.04/76.25 61853[61:MRR:160.0,61852.0] || -> until5(s17)*. % 76.04/76.25 61854[61:MRR:60216.0,61853.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.25 61855[62:Spt:61854.2] || -> xuntil6(s17)*. % 76.04/76.25 61856[62:MRR:159.0,61855.0] || -> until5(s18)*. % 76.04/76.25 61857[62:MRR:60215.0,61856.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.25 61861[63:Spt:61857.2] || -> xuntil6(s18)*. % 76.04/76.25 61862[63:MRR:158.0,61861.0] || -> until5(s19)*. % 76.04/76.25 61863[63:MRR:60214.0,61862.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.25 61864[64:Spt:61863.2] || -> xuntil6(s19)*. % 76.04/76.25 61865[64:MRR:157.0,61864.0] || -> until5(s20)*. % 76.04/76.25 61866[64:MRR:60204.0,61865.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.25 61870[65:Spt:61866.2] || -> xuntil6(s20)*. % 76.04/76.25 61871[65:MRR:156.0,61870.0] || -> until5(s21)*. % 76.04/76.25 61872[65:MRR:60203.0,61871.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.25 61873[66:Spt:61872.2] || -> xuntil6(s21)*. % 76.04/76.25 61874[66:MRR:155.0,61873.0] || -> until5(s22)*. % 76.04/76.25 61875[66:MRR:60196.0,61874.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.25 61879[67:Spt:61875.2] || -> xuntil6(s22)*. % 76.04/76.25 61880[67:MRR:154.0,61879.0] || -> until5(s23)*. % 76.04/76.25 61881[67:MRR:60192.0,61880.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.25 61882[68:Spt:61881.2] || -> xuntil6(s23)*. % 76.04/76.25 61883[68:MRR:153.0,61882.0] || -> until5(s24)*. % 76.04/76.25 61884[68:MRR:60188.0,61883.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.25 61888[69:Spt:61884.2] || -> xuntil6(s24)*. % 76.04/76.25 61889[69:MRR:152.0,61888.0] || -> until5(s25)*. % 76.04/76.25 61890[69:MRR:60184.0,61889.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.25 61891[70:Spt:61890.2] || -> xuntil6(s25)*. % 76.04/76.25 61892[70:MRR:151.0,61891.0] || -> until5(s26)*. % 76.04/76.25 61893[70:MRR:60183.0,61892.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.25 61897[71:Spt:61893.2] || -> xuntil6(s26)*. % 76.04/76.25 61898[71:MRR:150.0,61897.0] || -> until5(s27)*. % 76.04/76.25 61899[71:MRR:60179.0,61898.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.25 61900[72:Spt:61899.2] || -> xuntil6(s27)*. % 76.04/76.25 61901[72:MRR:149.0,61900.0] || -> until5(s28)*. % 76.04/76.25 61902[72:MRR:60178.0,61901.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.25 61906[73:Spt:61902.2] || -> xuntil6(s28)*. % 76.04/76.25 61907[73:MRR:148.0,61906.0] || -> until5(s29)*. % 76.04/76.25 61908[73:MRR:60177.0,61907.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.25 61909[74:Spt:61908.2] || -> xuntil6(s29)*. % 76.04/76.25 61910[74:MRR:147.0,61909.0] || -> until5(s30)*. % 76.04/76.25 61911[74:MRR:60176.0,61910.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.25 61915[75:Spt:61911.2] || -> xuntil6(s30)*. % 76.04/76.25 61916[75:MRR:146.0,61915.0] || -> until5(s31)*. % 76.04/76.25 61917[75:MRR:54645.0,61916.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.25 61918[76:Spt:61917.2] || -> xuntil6(s31)*. % 76.04/76.25 61919[76:MRR:145.0,61918.0] || -> until5(s32)*. % 76.04/76.25 61920[76:MRR:60290.0,61919.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.25 61924[77:Spt:61920.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.25 61926[77:Res:61924.0,61.1] always3(s33) || -> . % 76.04/76.25 61927[77:SSi:61926.0,722.0] || -> . % 76.04/76.25 61928[77:Spt:61927.0,61920.1,61924.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.04/76.25 61929[77:Spt:61927.0,61920.0,61920.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 76.04/76.25 61931[77:MRR:822.2,61928.0] node4(s32) || m_main_v_state(s32,c_ready)* -> . % 76.04/76.25 61932[77:Res:53.1,61929.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 76.04/76.25 61934[78:Spt:61932.1] || -> xuntil6(s32)*. % 76.04/76.25 61935[78:MRR:144.0,61934.0] || -> until5(s33)*. % 76.04/76.25 61936[78:MRR:54646.0,61935.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.25 61941[79:Spt:61936.2] || -> xuntil6(s33)*. % 76.04/76.25 61942[79:MRR:143.0,61941.0] || -> until5(s34)*. % 76.04/76.25 61943[79:MRR:60294.0,61942.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.25 61944[80:Spt:61943.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.25 61946[80:Res:61944.0,61.1] always3(s35) || -> . % 76.04/76.25 61947[80:SSi:61946.0,724.0] || -> . % 76.04/76.25 61948[80:Spt:61947.0,61943.1,61944.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.04/76.25 61949[80:Spt:61947.0,61943.0,61943.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 76.04/76.25 61951[80:MRR:816.2,61948.0] node4(s34) || m_main_v_state(s34,c_ready)* -> . % 76.04/76.25 61952[80:Res:53.1,61949.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 76.04/76.25 61954[81:Spt:61952.1] || -> xuntil6(s34)*. % 76.04/76.25 61955[81:MRR:142.0,61954.0] || -> until5(s35)*. % 76.04/76.25 61956[81:MRR:54650.0,61955.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.25 61964[82:Spt:61956.2] || -> xuntil6(s35)*. % 76.04/76.25 61965[82:MRR:141.0,61964.0] || -> until5(s36)*. % 76.04/76.25 61966[82:MRR:60298.0,61965.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.25 61967[83:Spt:61966.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.25 61969[83:Res:61967.0,61.1] always3(s37) || -> . % 76.04/76.25 61970[83:SSi:61969.0,726.0] || -> . % 76.04/76.25 61971[83:Spt:61970.0,61966.1,61967.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.04/76.25 61972[83:Spt:61970.0,61966.0,61966.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 76.04/76.25 61974[83:MRR:810.2,61971.0] node4(s36) || m_main_v_state(s36,c_ready)* -> . % 76.04/76.25 61975[83:Res:53.1,61972.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 76.04/76.25 61980[84:Spt:61975.1] || -> xuntil6(s36)*. % 76.04/76.25 61981[84:MRR:140.0,61980.0] || -> until5(s37)*. % 76.04/76.25 61982[84:MRR:54654.0,61981.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.25 61984[85:Spt:61982.2] || -> xuntil6(s37)*. % 76.04/76.25 61985[85:MRR:139.0,61984.0] || -> until5(s38)*. % 76.04/76.25 61986[85:MRR:60305.0,61985.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.25 61987[86:Spt:61986.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.25 61989[86:Res:61987.0,61.1] always3(s39) || -> . % 76.04/76.25 61990[86:SSi:61989.0,728.0] || -> . % 76.04/76.25 61991[86:Spt:61990.0,61986.1,61987.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.04/76.25 61992[86:Spt:61990.0,61986.0,61986.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 76.04/76.25 61994[86:MRR:804.2,61991.0] node4(s38) || m_main_v_state(s38,c_ready)* -> . % 76.04/76.25 61995[86:Res:53.1,61992.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 76.04/76.25 61997[87:Spt:61995.1] || -> xuntil6(s38)*. % 76.04/76.25 61998[87:MRR:138.0,61997.0] || -> until5(s39)*. % 76.04/76.25 61999[87:MRR:54658.0,61998.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.25 62004[88:Spt:61999.2] || -> xuntil6(s39)*. % 76.04/76.25 62005[88:MRR:137.0,62004.0] || -> until5(s40)*. % 76.04/76.25 62006[88:MRR:60306.0,62005.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.25 62007[89:Spt:62006.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.25 62009[89:Res:62007.0,61.1] always3(s41) || -> . % 76.04/76.25 62010[89:SSi:62009.0,730.0] || -> . % 76.04/76.25 62011[89:Spt:62010.0,62006.1,62007.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.04/76.25 62012[89:Spt:62010.0,62006.0,62006.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 76.04/76.25 62014[89:MRR:798.2,62011.0] node4(s40) || m_main_v_state(s40,c_ready)* -> . % 76.04/76.25 62015[89:Res:53.1,62012.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 76.04/76.25 62017[90:Spt:62015.1] || -> xuntil6(s40)*. % 76.04/76.25 62018[90:MRR:136.0,62017.0] || -> until5(s41)*. % 76.04/76.25 62019[90:MRR:54665.0,62018.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.25 62027[91:Spt:62019.2] || -> xuntil6(s41)*. % 76.04/76.25 62028[91:MRR:135.0,62027.0] || -> until5(s42)*. % 76.04/76.25 62029[91:MRR:60310.0,62028.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.25 62030[92:Spt:62029.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.25 62032[92:Res:62030.0,61.1] always3(s43) || -> . % 76.04/76.25 62033[92:SSi:62032.0,732.0] || -> . % 76.04/76.25 62034[92:Spt:62033.0,62029.1,62030.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.04/76.25 62035[92:Spt:62033.0,62029.0,62029.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 76.04/76.25 62037[92:MRR:792.2,62034.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 76.04/76.25 62038[92:Res:53.1,62035.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 76.04/76.25 62043[93:Spt:62038.1] || -> xuntil6(s42)*. % 76.04/76.25 62044[93:MRR:134.0,62043.0] || -> until5(s43)*. % 76.04/76.25 62045[93:MRR:54666.0,62044.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.25 62047[94:Spt:62045.2] || -> xuntil6(s43)*. % 76.04/76.25 62048[94:MRR:133.0,62047.0] || -> until5(s44)*. % 76.04/76.25 62049[94:MRR:60314.0,62048.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.25 62050[95:Spt:62049.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.25 62052[95:Res:62050.0,61.1] always3(s45) || -> . % 76.04/76.25 62053[95:SSi:62052.0,734.0] || -> . % 76.04/76.25 62054[95:Spt:62053.0,62049.1,62050.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.04/76.25 62055[95:Spt:62053.0,62049.0,62049.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 76.04/76.25 62057[95:MRR:786.2,62054.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 76.04/76.25 62058[95:Res:53.1,62055.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 76.04/76.25 62060[96:Spt:62058.1] || -> xuntil6(s44)*. % 76.04/76.25 62061[96:MRR:132.0,62060.0] || -> until5(s45)*. % 76.04/76.25 62062[96:MRR:54670.0,62061.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.25 62067[97:Spt:62062.2] || -> xuntil6(s45)*. % 76.04/76.25 62068[97:MRR:131.0,62067.0] || -> until5(s46)*. % 76.04/76.25 62069[97:MRR:60318.0,62068.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.25 62070[98:Spt:62069.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.25 62072[98:Res:62070.0,61.1] always3(s47) || -> . % 76.04/76.25 62073[98:SSi:62072.0,736.0] || -> . % 76.04/76.25 62074[98:Spt:62073.0,62069.1,62070.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.04/76.25 62075[98:Spt:62073.0,62069.0,62069.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 76.04/76.25 62077[98:MRR:780.2,62074.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 76.04/76.25 62078[98:Res:53.1,62075.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 76.04/76.25 62080[99:Spt:62078.1] || -> xuntil6(s46)*. % 76.04/76.25 62081[99:MRR:130.0,62080.0] || -> until5(s47)*. % 76.04/76.25 62082[99:MRR:54674.0,62081.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.25 62090[100:Spt:62082.2] || -> xuntil6(s47)*. % 76.04/76.25 62091[100:MRR:129.0,62090.0] || -> until5(s48)*. % 76.04/76.25 62092[100:MRR:60322.0,62091.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.25 62093[101:Spt:62092.1] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.25 62095[101:Res:62093.0,61.1] always3(s49) || -> . % 76.04/76.25 62096[101:SSi:62095.0,50.0,738.0] || -> . % 76.04/76.25 62097[101:Spt:62096.0,62092.1,62093.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.25 62098[101:Spt:62096.0,62092.0,62092.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 76.04/76.25 62100[101:MRR:774.2,62097.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.25 62101[101:Res:53.1,62098.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 76.04/76.25 62106[102:Spt:62101.1] || -> xuntil6(s48)*. % 76.04/76.25 62107[102:MRR:128.0,62106.0] || -> until5(s49)*. % 76.04/76.25 62109[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.25 62113[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.25 62114[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.26 62115[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.26 62116[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.26 62120[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.26 62121[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.26 62125[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.26 62132[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.26 62133[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.26 62140[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.26 62144[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.26 62145[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.26 62149[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.26 62156[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.26 62160[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.26 62161[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.26 62171[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.26 62172[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.26 62173[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.26 62180[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.26 62181[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.26 62185[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.26 62192[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.26 62196[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.26 62200[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.26 62204[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.26 62211[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.26 62212[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.26 62216[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.26 62220[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.26 62224[0:SoR:819.0,66.2] until5(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.26 62231[0:SoR:813.0,66.2] until5(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.26 62232[0:SoR:807.0,66.2] until5(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.26 62236[0:SoR:801.0,66.2] until5(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.26 62240[0:SoR:795.0,66.2] until5(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.26 62244[0:SoR:789.0,66.2] until5(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.26 62251[0:SoR:783.0,66.2] until5(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.26 62252[0:SoR:777.0,66.2] until5(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.26 62254[44:SoR:61776.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 62256[44:SoR:62254.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)* xuntil6(s49). % 76.04/76.26 62257[102:SSi:62256.0,50.0,738.0,62107.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s7,c_busy)* xuntil6(s49). % 76.04/76.26 62258[103:Spt:62257.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 62260[103:Res:62258.0,61.1] always3(s7) || -> . % 76.04/76.26 62261[103:SSi:62260.0,696.0,61808.0,61810.0] || -> . % 76.04/76.26 62262[103:Spt:62261.0,62257.1,62258.0] || m_main_v_state(s7,c_busy)*+ -> . % 76.04/76.26 62263[103:Spt:62261.0,62257.0,62257.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.26 62267[103:MRR:62254.2,62262.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.26 62268[103:Res:53.1,62263.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.26 62270[103:MRR:62268.0,62097.0] || -> xuntil6(s49)*. % 76.04/76.26 62271[103:MRR:61775.0,62270.0] || -> until2p7(s7)*. % 76.04/76.26 62272[103:MRR:203.0,62271.0] || -> until2p7(s8)* node4(s7). % 76.04/76.26 62273[104:Spt:62272.0] || -> until2p7(s8)*. % 76.04/76.26 62274[104:MRR:204.0,62273.0] || -> until2p7(s9)* node4(s8). % 76.04/76.26 62275[105:Spt:62274.0] || -> until2p7(s9)*. % 76.04/76.26 62276[105:MRR:205.0,62275.0] || -> until2p7(s10)* node4(s9). % 76.04/76.26 62277[106:Spt:62276.0] || -> until2p7(s10)*. % 76.04/76.26 62278[106:MRR:206.0,62277.0] || -> until2p7(s11)* node4(s10). % 76.04/76.26 62279[107:Spt:62278.0] || -> until2p7(s11)*. % 76.04/76.26 62280[107:MRR:207.0,62279.0] || -> until2p7(s12)* node4(s11). % 76.04/76.26 62281[108:Spt:62280.0] || -> until2p7(s12)*. % 76.04/76.26 62282[108:MRR:208.0,62281.0] || -> until2p7(s13)* node4(s12). % 76.04/76.26 62283[109:Spt:62282.0] || -> until2p7(s13)*. % 76.04/76.26 62284[109:MRR:209.0,62283.0] || -> until2p7(s14)* node4(s13). % 76.04/76.26 62285[110:Spt:62284.0] || -> until2p7(s14)*. % 76.04/76.26 62286[110:MRR:210.0,62285.0] || -> until2p7(s15)* node4(s14). % 76.04/76.26 62287[111:Spt:62286.0] || -> until2p7(s15)*. % 76.04/76.26 62288[111:MRR:211.0,62287.0] || -> until2p7(s16)* node4(s15). % 76.04/76.26 62289[112:Spt:62288.0] || -> until2p7(s16)*. % 76.04/76.26 62290[112:MRR:212.0,62289.0] || -> until2p7(s17)* node4(s16). % 76.04/76.26 62291[113:Spt:62290.0] || -> until2p7(s17)*. % 76.04/76.26 62292[113:MRR:213.0,62291.0] || -> until2p7(s18)* node4(s17). % 76.04/76.26 62293[114:Spt:62292.0] || -> until2p7(s18)*. % 76.04/76.26 62294[114:MRR:214.0,62293.0] || -> until2p7(s19)* node4(s18). % 76.04/76.26 62295[115:Spt:62294.0] || -> until2p7(s19)*. % 76.04/76.26 62296[115:MRR:215.0,62295.0] || -> until2p7(s20)* node4(s19). % 76.04/76.26 62297[116:Spt:62296.0] || -> until2p7(s20)*. % 76.04/76.26 62298[116:MRR:216.0,62297.0] || -> until2p7(s21)* node4(s20). % 76.04/76.26 62299[117:Spt:62298.0] || -> until2p7(s21)*. % 76.04/76.26 62300[117:MRR:217.0,62299.0] || -> until2p7(s22)* node4(s21). % 76.04/76.26 62301[118:Spt:62300.0] || -> until2p7(s22)*. % 76.04/76.26 62302[118:MRR:218.0,62301.0] || -> until2p7(s23)* node4(s22). % 76.04/76.26 62303[119:Spt:62302.0] || -> until2p7(s23)*. % 76.04/76.26 62304[119:MRR:219.0,62303.0] || -> until2p7(s24)* node4(s23). % 76.04/76.26 62305[120:Spt:62304.0] || -> until2p7(s24)*. % 76.04/76.26 62306[120:MRR:220.0,62305.0] || -> until2p7(s25)* node4(s24). % 76.04/76.26 62307[121:Spt:62306.0] || -> until2p7(s25)*. % 76.04/76.26 62308[121:MRR:221.0,62307.0] || -> until2p7(s26)* node4(s25). % 76.04/76.26 62309[122:Spt:62308.0] || -> until2p7(s26)*. % 76.04/76.26 62310[122:MRR:222.0,62309.0] || -> until2p7(s27)* node4(s26). % 76.04/76.26 62311[123:Spt:62310.0] || -> until2p7(s27)*. % 76.04/76.26 62312[123:MRR:223.0,62311.0] || -> until2p7(s28)* node4(s27). % 76.04/76.26 62313[124:Spt:62312.0] || -> until2p7(s28)*. % 76.04/76.26 62314[124:MRR:224.0,62313.0] || -> until2p7(s29)* node4(s28). % 76.04/76.26 62315[125:Spt:62314.0] || -> until2p7(s29)*. % 76.04/76.26 62316[125:MRR:225.0,62315.0] || -> until2p7(s30)* node4(s29). % 76.04/76.26 62317[126:Spt:62316.0] || -> until2p7(s30)*. % 76.04/76.26 62318[126:MRR:226.0,62317.0] || -> until2p7(s31)* node4(s30). % 76.04/76.26 62319[127:Spt:62318.0] || -> until2p7(s31)*. % 76.04/76.26 62320[127:MRR:227.0,62319.0] || -> until2p7(s32)* node4(s31). % 76.04/76.26 62321[128:Spt:62320.0] || -> until2p7(s32)*. % 76.04/76.26 62322[128:MRR:228.0,62321.0] || -> until2p7(s33)* node4(s32). % 76.04/76.26 62323[129:Spt:62322.0] || -> until2p7(s33)*. % 76.04/76.26 62324[129:MRR:229.0,62323.0] || -> until2p7(s34)* node4(s33). % 76.04/76.26 62325[130:Spt:62324.0] || -> until2p7(s34)*. % 76.04/76.26 62326[130:MRR:230.0,62325.0] || -> until2p7(s35)* node4(s34). % 76.04/76.26 62327[131:Spt:62326.0] || -> until2p7(s35)*. % 76.04/76.26 62328[131:MRR:231.0,62327.0] || -> until2p7(s36)* node4(s35). % 76.04/76.26 62329[132:Spt:62328.0] || -> until2p7(s36)*. % 76.04/76.26 62330[132:MRR:232.0,62329.0] || -> until2p7(s37)* node4(s36). % 76.04/76.26 62331[133:Spt:62330.0] || -> until2p7(s37)*. % 76.04/76.26 62332[133:MRR:235.0,62331.0] || -> until2p7(s38)* node4(s37). % 76.04/76.26 62333[134:Spt:62332.0] || -> until2p7(s38)*. % 76.04/76.26 62334[134:MRR:236.0,62333.0] || -> until2p7(s39)* node4(s38). % 76.04/76.26 62335[135:Spt:62334.0] || -> until2p7(s39)*. % 76.04/76.26 62336[135:MRR:237.0,62335.0] || -> until2p7(s40)* node4(s39). % 76.04/76.26 62337[136:Spt:62336.0] || -> until2p7(s40)*. % 76.04/76.26 62338[136:MRR:238.0,62337.0] || -> until2p7(s41)* node4(s40). % 76.04/76.26 62339[137:Spt:62338.0] || -> until2p7(s41)*. % 76.04/76.26 62340[137:MRR:239.0,62339.0] || -> until2p7(s42)* node4(s41). % 76.04/76.26 62341[138:Spt:62340.0] || -> until2p7(s42)*. % 76.04/76.26 62342[138:MRR:240.0,62341.0] || -> until2p7(s43)* node4(s42). % 76.04/76.26 62343[139:Spt:62342.0] || -> until2p7(s43)*. % 76.04/76.26 62344[139:MRR:241.0,62343.0] || -> until2p7(s44)* node4(s43). % 76.04/76.26 62345[140:Spt:62344.0] || -> until2p7(s44)*. % 76.04/76.26 62346[140:MRR:539.0,62345.0] || -> until2p7(s45)* node4(s44). % 76.04/76.26 62347[141:Spt:62346.0] || -> until2p7(s45)*. % 76.04/76.26 62348[141:MRR:544.0,62347.0] || -> until2p7(s46)* node4(s45). % 76.04/76.26 62349[142:Spt:62348.0] || -> until2p7(s46)*. % 76.04/76.26 62350[142:MRR:549.0,62349.0] || -> until2p7(s47)* node4(s46). % 76.04/76.26 62351[143:Spt:62350.0] || -> until2p7(s47)*. % 76.04/76.26 62352[143:MRR:554.0,62351.0] || -> until2p7(s48)* node4(s47). % 76.04/76.26 62353[144:Spt:62352.0] || -> until2p7(s48)*. % 76.04/76.26 62354[144:MRR:559.0,62353.0] || -> until2p7(s49)* node4(s48). % 76.04/76.26 62355[145:Spt:62354.0] || -> until2p7(s49)*. % 76.04/76.26 62356[145:MRR:194.0,62355.0] || -> node4(s49)*. % 76.04/76.26 62357[145:MRR:62267.0,62356.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.26 62358[145:Res:53.1,62357.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.26 62360[145:MRR:62358.0,62097.0] || -> . % 76.04/76.26 62361[145:Spt:62360.0,62354.0,62355.0] || until2p7(s49)*+ -> . % 76.04/76.26 62362[145:Spt:62360.0,62354.1] || -> node4(s48)*. % 76.04/76.26 62363[145:MRR:62100.0,62362.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.26 62366[145:Res:53.1,62363.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.26 62369[145:Res:62366.0,61.1] always3(s48) || -> . % 76.04/76.26 62370[145:SSi:62369.0,737.0,62091.0,62106.0,62353.0,62362.0] || -> . % 76.04/76.26 62371[144:Spt:62370.0,62352.0,62353.0] || until2p7(s48)*+ -> . % 76.04/76.26 62372[144:Spt:62370.0,62352.1] || -> node4(s47)*. % 76.04/76.26 62374[144:MRR:777.0,62372.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.26 62389[144:Res:53.1,62374.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.26 62391[144:MRR:62389.0,62074.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.26 62393[144:Res:62391.0,61.1] always3(s48) || -> . % 76.04/76.26 62394[144:SSi:62393.0,737.0,62091.0,62106.0] || -> . % 76.04/76.26 62395[143:Spt:62394.0,62350.0,62351.0] || until2p7(s47)*+ -> . % 76.04/76.26 62396[143:Spt:62394.0,62350.1] || -> node4(s46)*. % 76.04/76.26 62397[143:MRR:62077.0,62396.0] || m_main_v_state(s46,c_ready)*+ -> . % 76.04/76.26 62400[143:Res:53.1,62397.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.26 62403[143:Res:62400.0,61.1] always3(s46) || -> . % 76.04/76.26 62404[143:SSi:62403.0,735.0,62068.0,62080.0,62349.0,62396.0] || -> . % 76.04/76.26 62405[142:Spt:62404.0,62348.0,62349.0] || until2p7(s46)*+ -> . % 76.04/76.26 62406[142:Spt:62404.0,62348.1] || -> node4(s45)*. % 76.04/76.26 62408[142:MRR:783.0,62406.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.26 62420[142:Res:53.1,62408.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.26 62422[142:MRR:62420.0,62054.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.26 62427[142:Res:62422.0,61.1] always3(s46) || -> . % 76.04/76.26 62428[142:SSi:62427.0,735.0,62068.0,62080.0] || -> . % 76.04/76.26 62429[141:Spt:62428.0,62346.0,62347.0] || until2p7(s45)*+ -> . % 76.04/76.26 62430[141:Spt:62428.0,62346.1] || -> node4(s44)*. % 76.04/76.26 62431[141:MRR:62057.0,62430.0] || m_main_v_state(s44,c_ready)*+ -> . % 76.04/76.26 62434[141:Res:53.1,62431.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.26 62438[141:Res:62434.0,61.1] always3(s44) || -> . % 76.04/76.26 62439[141:SSi:62438.0,733.0,62048.0,62060.0,62345.0,62430.0] || -> . % 76.04/76.26 62440[140:Spt:62439.0,62344.0,62345.0] || until2p7(s44)*+ -> . % 76.04/76.26 62441[140:Spt:62439.0,62344.1] || -> node4(s43)*. % 76.04/76.26 62443[140:MRR:789.0,62441.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.26 62454[140:Res:53.1,62443.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.26 62456[140:MRR:62454.0,62034.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.26 62458[140:Res:62456.0,61.1] always3(s44) || -> . % 76.04/76.26 62459[140:SSi:62458.0,733.0,62048.0,62060.0] || -> . % 76.04/76.26 62460[139:Spt:62459.0,62342.0,62343.0] || until2p7(s43)*+ -> . % 76.04/76.26 62461[139:Spt:62459.0,62342.1] || -> node4(s42)*. % 76.04/76.26 62462[139:MRR:62037.0,62461.0] || m_main_v_state(s42,c_ready)*+ -> . % 76.04/76.26 62466[139:Res:53.1,62462.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.26 62469[139:Res:62466.0,61.1] always3(s42) || -> . % 76.04/76.26 62470[139:SSi:62469.0,731.0,62028.0,62043.0,62341.0,62461.0] || -> . % 76.04/76.26 62471[138:Spt:62470.0,62340.0,62341.0] || until2p7(s42)*+ -> . % 76.04/76.26 62472[138:Spt:62470.0,62340.1] || -> node4(s41)*. % 76.04/76.26 62474[138:MRR:795.0,62472.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.26 62485[138:Res:53.1,62474.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.26 62487[138:MRR:62485.0,62011.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.26 62489[138:Res:62487.0,61.1] always3(s42) || -> . % 76.04/76.26 62490[138:SSi:62489.0,731.0,62028.0,62043.0] || -> . % 76.04/76.26 62491[137:Spt:62490.0,62338.0,62339.0] || until2p7(s41)*+ -> . % 76.04/76.26 62492[137:Spt:62490.0,62338.1] || -> node4(s40)*. % 76.04/76.26 62493[137:MRR:62014.0,62492.0] || m_main_v_state(s40,c_ready)*+ -> . % 76.04/76.26 62496[137:Res:53.1,62493.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.26 62499[137:Res:62496.0,61.1] always3(s40) || -> . % 76.04/76.26 62500[137:SSi:62499.0,729.0,62005.0,62017.0,62337.0,62492.0] || -> . % 76.04/76.26 62501[136:Spt:62500.0,62336.0,62337.0] || until2p7(s40)*+ -> . % 76.04/76.26 62502[136:Spt:62500.0,62336.1] || -> node4(s39)*. % 76.04/76.26 62504[136:MRR:801.0,62502.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.26 62516[136:Res:53.1,62504.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.26 62518[136:MRR:62516.0,61991.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.26 62520[136:Res:62518.0,61.1] always3(s40) || -> . % 76.04/76.26 62521[136:SSi:62520.0,729.0,62005.0,62017.0] || -> . % 76.04/76.26 62522[135:Spt:62521.0,62334.0,62335.0] || until2p7(s39)*+ -> . % 76.04/76.26 62523[135:Spt:62521.0,62334.1] || -> node4(s38)*. % 76.04/76.26 62524[135:MRR:61994.0,62523.0] || m_main_v_state(s38,c_ready)*+ -> . % 76.04/76.26 62527[135:Res:53.1,62524.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.26 62530[135:Res:62527.0,61.1] always3(s38) || -> . % 76.04/76.26 62531[135:SSi:62530.0,727.0,61985.0,61997.0,62333.0,62523.0] || -> . % 76.04/76.26 62532[134:Spt:62531.0,62332.0,62333.0] || until2p7(s38)*+ -> . % 76.04/76.26 62533[134:Spt:62531.0,62332.1] || -> node4(s37)*. % 76.04/76.26 62535[134:MRR:807.0,62533.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.26 62547[134:Res:53.1,62535.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.26 62549[134:MRR:62547.0,61971.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.26 62554[134:Res:62549.0,61.1] always3(s38) || -> . % 76.04/76.26 62555[134:SSi:62554.0,727.0,61985.0,61997.0] || -> . % 76.04/76.26 62556[133:Spt:62555.0,62330.0,62331.0] || until2p7(s37)*+ -> . % 76.04/76.26 62557[133:Spt:62555.0,62330.1] || -> node4(s36)*. % 76.04/76.26 62558[133:MRR:61974.0,62557.0] || m_main_v_state(s36,c_ready)*+ -> . % 76.04/76.26 62561[133:Res:53.1,62558.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.26 62565[133:Res:62561.0,61.1] always3(s36) || -> . % 76.04/76.26 62566[133:SSi:62565.0,725.0,61965.0,61980.0,62329.0,62557.0] || -> . % 76.04/76.26 62567[132:Spt:62566.0,62328.0,62329.0] || until2p7(s36)*+ -> . % 76.04/76.26 62568[132:Spt:62566.0,62328.1] || -> node4(s35)*. % 76.04/76.26 62570[132:MRR:813.0,62568.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.26 62581[132:Res:53.1,62570.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.26 62583[132:MRR:62581.0,61948.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.26 62585[132:Res:62583.0,61.1] always3(s36) || -> . % 76.04/76.26 62586[132:SSi:62585.0,725.0,61965.0,61980.0] || -> . % 76.04/76.26 62587[131:Spt:62586.0,62326.0,62327.0] || until2p7(s35)*+ -> . % 76.04/76.26 62588[131:Spt:62586.0,62326.1] || -> node4(s34)*. % 76.04/76.26 62589[131:MRR:61951.0,62588.0] || m_main_v_state(s34,c_ready)*+ -> . % 76.04/76.26 62593[131:Res:53.1,62589.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.26 62596[131:Res:62593.0,61.1] always3(s34) || -> . % 76.04/76.26 62597[131:SSi:62596.0,723.0,61942.0,61954.0,62325.0,62588.0] || -> . % 76.04/76.26 62598[130:Spt:62597.0,62324.0,62325.0] || until2p7(s34)*+ -> . % 76.04/76.26 62599[130:Spt:62597.0,62324.1] || -> node4(s33)*. % 76.04/76.26 62601[130:MRR:819.0,62599.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.26 62612[130:Res:53.1,62601.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.26 62614[130:MRR:62612.0,61928.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.26 62616[130:Res:62614.0,61.1] always3(s34) || -> . % 76.04/76.26 62617[130:SSi:62616.0,723.0,61942.0,61954.0] || -> . % 76.04/76.26 62618[129:Spt:62617.0,62322.0,62323.0] || until2p7(s33)*+ -> . % 76.04/76.26 62619[129:Spt:62617.0,62322.1] || -> node4(s32)*. % 76.04/76.26 62620[129:MRR:61931.0,62619.0] || m_main_v_state(s32,c_ready)*+ -> . % 76.04/76.26 62623[129:Res:53.1,62620.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.26 62626[129:Res:62623.0,61.1] always3(s32) || -> . % 76.04/76.26 62627[129:SSi:62626.0,721.0,61919.0,61934.0,62321.0,62619.0] || -> . % 76.04/76.26 62628[128:Spt:62627.0,62320.0,62321.0] || until2p7(s32)*+ -> . % 76.04/76.26 62629[128:Spt:62627.0,62320.1] || -> node4(s31)*. % 76.04/76.26 62631[128:MRR:825.0,62629.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.26 62643[128:Res:53.1,62631.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.26 62645[129:Spt:62643.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 62647[129:Res:62645.0,61.1] always3(s31) || -> . % 76.04/76.26 62648[129:SSi:62647.0,720.0,61916.0,61918.0,62319.0,62629.0] || -> . % 76.04/76.26 62649[129:Spt:62648.0,62643.0,62645.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.26 62650[129:Spt:62648.0,62643.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.26 62654[129:Res:62650.0,61.1] always3(s32) || -> . % 76.04/76.26 62655[129:SSi:62654.0,721.0,61919.0,61934.0] || -> . % 76.04/76.26 62656[127:Spt:62655.0,62318.0,62319.0] || until2p7(s31)*+ -> . % 76.04/76.26 62657[127:Spt:62655.0,62318.1] || -> node4(s30)*. % 76.04/76.26 62659[127:MRR:828.0,62657.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.26 62666[127:Res:53.1,62659.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.26 62668[128:Spt:62666.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 62670[128:Res:62668.0,61.1] always3(s30) || -> . % 76.04/76.26 62671[128:SSi:62670.0,719.0,61910.0,61915.0,62317.0,62657.0] || -> . % 76.04/76.26 62672[128:Spt:62671.0,62666.0,62668.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.26 62673[128:Spt:62671.0,62666.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 62677[128:Res:62673.0,61.1] always3(s31) || -> . % 76.04/76.26 62678[128:SSi:62677.0,720.0,61916.0,61918.0] || -> . % 76.04/76.26 62679[126:Spt:62678.0,62316.0,62317.0] || until2p7(s30)*+ -> . % 76.04/76.26 62680[126:Spt:62678.0,62316.1] || -> node4(s29)*. % 76.04/76.26 62682[126:MRR:831.0,62680.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.26 62685[126:Res:53.1,62682.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.26 62687[127:Spt:62685.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 62689[127:Res:62687.0,61.1] always3(s29) || -> . % 76.04/76.26 62690[127:SSi:62689.0,718.0,61907.0,61909.0,62315.0,62680.0] || -> . % 76.04/76.26 62691[127:Spt:62690.0,62685.0,62687.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.26 62692[127:Spt:62690.0,62685.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 62696[127:Res:62692.0,61.1] always3(s30) || -> . % 76.04/76.26 62697[127:SSi:62696.0,719.0,61910.0,61915.0] || -> . % 76.04/76.26 62698[125:Spt:62697.0,62314.0,62315.0] || until2p7(s29)*+ -> . % 76.04/76.26 62699[125:Spt:62697.0,62314.1] || -> node4(s28)*. % 76.04/76.26 62701[125:MRR:834.0,62699.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.26 62704[125:Res:53.1,62701.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.26 62706[126:Spt:62704.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 62708[126:Res:62706.0,61.1] always3(s28) || -> . % 76.04/76.26 62709[126:SSi:62708.0,717.0,61901.0,61906.0,62313.0,62699.0] || -> . % 76.04/76.26 62710[126:Spt:62709.0,62704.0,62706.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.26 62711[126:Spt:62709.0,62704.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 62715[126:Res:62711.0,61.1] always3(s29) || -> . % 76.04/76.26 62716[126:SSi:62715.0,718.0,61907.0,61909.0] || -> . % 76.04/76.26 62717[124:Spt:62716.0,62312.0,62313.0] || until2p7(s28)*+ -> . % 76.04/76.26 62718[124:Spt:62716.0,62312.1] || -> node4(s27)*. % 76.04/76.26 62720[124:MRR:837.0,62718.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.26 62723[124:Res:53.1,62720.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.26 62728[125:Spt:62723.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 62730[125:Res:62728.0,61.1] always3(s27) || -> . % 76.04/76.26 62731[125:SSi:62730.0,716.0,61898.0,61900.0,62311.0,62718.0] || -> . % 76.04/76.26 62732[125:Spt:62731.0,62723.0,62728.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.26 62733[125:Spt:62731.0,62723.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 62737[125:Res:62733.0,61.1] always3(s28) || -> . % 76.04/76.26 62738[125:SSi:62737.0,717.0,61901.0,61906.0] || -> . % 76.04/76.26 62739[123:Spt:62738.0,62310.0,62311.0] || until2p7(s27)*+ -> . % 76.04/76.26 62740[123:Spt:62738.0,62310.1] || -> node4(s26)*. % 76.04/76.26 62742[123:MRR:840.0,62740.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.26 62745[123:Res:53.1,62742.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.26 62747[124:Spt:62745.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 62749[124:Res:62747.0,61.1] always3(s26) || -> . % 76.04/76.26 62750[124:SSi:62749.0,715.0,61892.0,61897.0,62309.0,62740.0] || -> . % 76.04/76.26 62751[124:Spt:62750.0,62745.0,62747.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.26 62752[124:Spt:62750.0,62745.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 62756[124:Res:62752.0,61.1] always3(s27) || -> . % 76.04/76.26 62757[124:SSi:62756.0,716.0,61898.0,61900.0] || -> . % 76.04/76.26 62758[122:Spt:62757.0,62308.0,62309.0] || until2p7(s26)*+ -> . % 76.04/76.26 62759[122:Spt:62757.0,62308.1] || -> node4(s25)*. % 76.04/76.26 62761[122:MRR:843.0,62759.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.26 62764[122:Res:53.1,62761.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.26 62766[123:Spt:62764.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 62768[123:Res:62766.0,61.1] always3(s25) || -> . % 76.04/76.26 62769[123:SSi:62768.0,714.0,61889.0,61891.0,62307.0,62759.0] || -> . % 76.04/76.26 62770[123:Spt:62769.0,62764.0,62766.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.26 62771[123:Spt:62769.0,62764.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 62775[123:Res:62771.0,61.1] always3(s26) || -> . % 76.04/76.26 62776[123:SSi:62775.0,715.0,61892.0,61897.0] || -> . % 76.04/76.26 62777[121:Spt:62776.0,62306.0,62307.0] || until2p7(s25)*+ -> . % 76.04/76.26 62778[121:Spt:62776.0,62306.1] || -> node4(s24)*. % 76.04/76.26 62780[121:MRR:846.0,62778.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.26 62783[121:Res:53.1,62780.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.26 62785[122:Spt:62783.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 62787[122:Res:62785.0,61.1] always3(s24) || -> . % 76.04/76.26 62788[122:SSi:62787.0,713.0,61883.0,61888.0,62305.0,62778.0] || -> . % 76.04/76.26 62789[122:Spt:62788.0,62783.0,62785.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.26 62790[122:Spt:62788.0,62783.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 62794[122:Res:62790.0,61.1] always3(s25) || -> . % 76.04/76.26 62795[122:SSi:62794.0,714.0,61889.0,61891.0] || -> . % 76.04/76.26 62796[120:Spt:62795.0,62304.0,62305.0] || until2p7(s24)*+ -> . % 76.04/76.26 62797[120:Spt:62795.0,62304.1] || -> node4(s23)*. % 76.04/76.26 62799[120:MRR:849.0,62797.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.26 62802[120:Res:53.1,62799.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.26 62807[121:Spt:62802.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 62809[121:Res:62807.0,61.1] always3(s23) || -> . % 76.04/76.26 62810[121:SSi:62809.0,712.0,61880.0,61882.0,62303.0,62797.0] || -> . % 76.04/76.26 62811[121:Spt:62810.0,62802.0,62807.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.26 62812[121:Spt:62810.0,62802.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 62816[121:Res:62812.0,61.1] always3(s24) || -> . % 76.04/76.26 62817[121:SSi:62816.0,713.0,61883.0,61888.0] || -> . % 76.04/76.26 62818[119:Spt:62817.0,62302.0,62303.0] || until2p7(s23)*+ -> . % 76.04/76.26 62819[119:Spt:62817.0,62302.1] || -> node4(s22)*. % 76.04/76.26 62821[119:MRR:852.0,62819.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.26 62824[119:Res:53.1,62821.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.26 62826[120:Spt:62824.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 62828[120:Res:62826.0,61.1] always3(s22) || -> . % 76.04/76.26 62829[120:SSi:62828.0,711.0,61874.0,61879.0,62301.0,62819.0] || -> . % 76.04/76.26 62830[120:Spt:62829.0,62824.0,62826.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.26 62831[120:Spt:62829.0,62824.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 62835[120:Res:62831.0,61.1] always3(s23) || -> . % 76.04/76.26 62836[120:SSi:62835.0,712.0,61880.0,61882.0] || -> . % 76.04/76.26 62837[118:Spt:62836.0,62300.0,62301.0] || until2p7(s22)*+ -> . % 76.04/76.26 62838[118:Spt:62836.0,62300.1] || -> node4(s21)*. % 76.04/76.26 62840[118:MRR:855.0,62838.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.26 62843[118:Res:53.1,62840.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.26 62845[119:Spt:62843.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 62847[119:Res:62845.0,61.1] always3(s21) || -> . % 76.04/76.26 62848[119:SSi:62847.0,710.0,61871.0,61873.0,62299.0,62838.0] || -> . % 76.04/76.26 62849[119:Spt:62848.0,62843.0,62845.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.26 62850[119:Spt:62848.0,62843.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 62854[119:Res:62850.0,61.1] always3(s22) || -> . % 76.04/76.26 62855[119:SSi:62854.0,711.0,61874.0,61879.0] || -> . % 76.04/76.26 62856[117:Spt:62855.0,62298.0,62299.0] || until2p7(s21)*+ -> . % 76.04/76.26 62857[117:Spt:62855.0,62298.1] || -> node4(s20)*. % 76.04/76.26 62859[117:MRR:858.0,62857.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.26 62862[117:Res:53.1,62859.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.26 62864[118:Spt:62862.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 62866[118:Res:62864.0,61.1] always3(s20) || -> . % 76.04/76.26 62867[118:SSi:62866.0,709.0,61865.0,61870.0,62297.0,62857.0] || -> . % 76.04/76.26 62868[118:Spt:62867.0,62862.0,62864.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.26 62869[118:Spt:62867.0,62862.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 62873[118:Res:62869.0,61.1] always3(s21) || -> . % 76.04/76.26 62874[118:SSi:62873.0,710.0,61871.0,61873.0] || -> . % 76.04/76.26 62875[116:Spt:62874.0,62296.0,62297.0] || until2p7(s20)*+ -> . % 76.04/76.26 62876[116:Spt:62874.0,62296.1] || -> node4(s19)*. % 76.04/76.26 62878[116:MRR:861.0,62876.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.26 62881[116:Res:53.1,62878.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.26 62886[117:Spt:62881.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 62888[117:Res:62886.0,61.1] always3(s19) || -> . % 76.04/76.26 62889[117:SSi:62888.0,708.0,61862.0,61864.0,62295.0,62876.0] || -> . % 76.04/76.26 62890[117:Spt:62889.0,62881.0,62886.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.26 62891[117:Spt:62889.0,62881.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 62895[117:Res:62891.0,61.1] always3(s20) || -> . % 76.04/76.26 62896[117:SSi:62895.0,709.0,61865.0,61870.0] || -> . % 76.04/76.26 62897[115:Spt:62896.0,62294.0,62295.0] || until2p7(s19)*+ -> . % 76.04/76.26 62898[115:Spt:62896.0,62294.1] || -> node4(s18)*. % 76.04/76.26 62900[115:MRR:864.0,62898.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.26 62903[115:Res:53.1,62900.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.26 62905[116:Spt:62903.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 62907[116:Res:62905.0,61.1] always3(s18) || -> . % 76.04/76.26 62908[116:SSi:62907.0,707.0,61856.0,61861.0,62293.0,62898.0] || -> . % 76.04/76.26 62909[116:Spt:62908.0,62903.0,62905.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.26 62910[116:Spt:62908.0,62903.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 62914[116:Res:62910.0,61.1] always3(s19) || -> . % 76.04/76.26 62915[116:SSi:62914.0,708.0,61862.0,61864.0] || -> . % 76.04/76.26 62916[114:Spt:62915.0,62292.0,62293.0] || until2p7(s18)*+ -> . % 76.04/76.26 62917[114:Spt:62915.0,62292.1] || -> node4(s17)*. % 76.04/76.26 62919[114:MRR:867.0,62917.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.26 62922[114:Res:53.1,62919.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.26 62924[115:Spt:62922.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 62926[115:Res:62924.0,61.1] always3(s17) || -> . % 76.04/76.26 62927[115:SSi:62926.0,706.0,61853.0,61855.0,62291.0,62917.0] || -> . % 76.04/76.26 62928[115:Spt:62927.0,62922.0,62924.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.26 62929[115:Spt:62927.0,62922.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 62933[115:Res:62929.0,61.1] always3(s18) || -> . % 76.04/76.26 62934[115:SSi:62933.0,707.0,61856.0,61861.0] || -> . % 76.04/76.26 62935[113:Spt:62934.0,62290.0,62291.0] || until2p7(s17)*+ -> . % 76.04/76.26 62936[113:Spt:62934.0,62290.1] || -> node4(s16)*. % 76.04/76.26 62938[113:MRR:870.0,62936.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.26 62941[113:Res:53.1,62938.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.26 62943[114:Spt:62941.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 62945[114:Res:62943.0,61.1] always3(s16) || -> . % 76.04/76.26 62946[114:SSi:62945.0,705.0,61847.0,61852.0,62289.0,62936.0] || -> . % 76.04/76.26 62947[114:Spt:62946.0,62941.0,62943.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.26 62948[114:Spt:62946.0,62941.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 62952[114:Res:62948.0,61.1] always3(s17) || -> . % 76.04/76.26 62953[114:SSi:62952.0,706.0,61853.0,61855.0] || -> . % 76.04/76.26 62954[112:Spt:62953.0,62288.0,62289.0] || until2p7(s16)*+ -> . % 76.04/76.26 62955[112:Spt:62953.0,62288.1] || -> node4(s15)*. % 76.04/76.26 62957[112:MRR:873.0,62955.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.26 62960[112:Res:53.1,62957.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.26 62965[113:Spt:62960.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 62967[113:Res:62965.0,61.1] always3(s15) || -> . % 76.04/76.26 62968[113:SSi:62967.0,704.0,61844.0,61846.0,62287.0,62955.0] || -> . % 76.04/76.26 62969[113:Spt:62968.0,62960.0,62965.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.26 62970[113:Spt:62968.0,62960.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 62974[113:Res:62970.0,61.1] always3(s16) || -> . % 76.04/76.26 62975[113:SSi:62974.0,705.0,61847.0,61852.0] || -> . % 76.04/76.26 62976[111:Spt:62975.0,62286.0,62287.0] || until2p7(s15)*+ -> . % 76.04/76.26 62977[111:Spt:62975.0,62286.1] || -> node4(s14)*. % 76.04/76.26 62979[111:MRR:876.0,62977.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.26 62982[111:Res:53.1,62979.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.26 62984[112:Spt:62982.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 62986[112:Res:62984.0,61.1] always3(s14) || -> . % 76.04/76.26 62987[112:SSi:62986.0,703.0,61838.0,61843.0,62285.0,62977.0] || -> . % 76.04/76.26 62988[112:Spt:62987.0,62982.0,62984.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.26 62989[112:Spt:62987.0,62982.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 62993[112:Res:62989.0,61.1] always3(s15) || -> . % 76.04/76.26 62994[112:SSi:62993.0,704.0,61844.0,61846.0] || -> . % 76.04/76.26 62995[110:Spt:62994.0,62284.0,62285.0] || until2p7(s14)*+ -> . % 76.04/76.26 62996[110:Spt:62994.0,62284.1] || -> node4(s13)*. % 76.04/76.26 62998[110:MRR:879.0,62996.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.26 63001[110:Res:53.1,62998.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.26 63003[111:Spt:63001.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 63005[111:Res:63003.0,61.1] always3(s13) || -> . % 76.04/76.26 63006[111:SSi:63005.0,702.0,61835.0,61837.0,62283.0,62996.0] || -> . % 76.04/76.26 63007[111:Spt:63006.0,63001.0,63003.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.26 63008[111:Spt:63006.0,63001.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 63012[111:Res:63008.0,61.1] always3(s14) || -> . % 76.04/76.26 63013[111:SSi:63012.0,703.0,61838.0,61843.0] || -> . % 76.04/76.26 63014[109:Spt:63013.0,62282.0,62283.0] || until2p7(s13)*+ -> . % 76.04/76.26 63015[109:Spt:63013.0,62282.1] || -> node4(s12)*. % 76.04/76.26 63017[109:MRR:882.0,63015.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.26 63020[109:Res:53.1,63017.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.26 63022[110:Spt:63020.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 63024[110:Res:63022.0,61.1] always3(s12) || -> . % 76.04/76.26 63025[110:SSi:63024.0,701.0,61829.0,61834.0,62281.0,63015.0] || -> . % 76.04/76.26 63026[110:Spt:63025.0,63020.0,63022.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.26 63027[110:Spt:63025.0,63020.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 63031[110:Res:63027.0,61.1] always3(s13) || -> . % 76.04/76.26 63032[110:SSi:63031.0,702.0,61835.0,61837.0] || -> . % 76.04/76.26 63033[108:Spt:63032.0,62280.0,62281.0] || until2p7(s12)*+ -> . % 76.04/76.26 63034[108:Spt:63032.0,62280.1] || -> node4(s11)*. % 76.04/76.26 63036[108:MRR:885.0,63034.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.26 63039[108:Res:53.1,63036.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.26 63044[109:Spt:63039.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 63046[109:Res:63044.0,61.1] always3(s11) || -> . % 76.04/76.26 63047[109:SSi:63046.0,700.0,61826.0,61828.0,62279.0,63034.0] || -> . % 76.04/76.26 63048[109:Spt:63047.0,63039.0,63044.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.26 63049[109:Spt:63047.0,63039.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 63053[109:Res:63049.0,61.1] always3(s12) || -> . % 76.04/76.26 63054[109:SSi:63053.0,701.0,61829.0,61834.0] || -> . % 76.04/76.26 63055[107:Spt:63054.0,62278.0,62279.0] || until2p7(s11)*+ -> . % 76.04/76.26 63056[107:Spt:63054.0,62278.1] || -> node4(s10)*. % 76.04/76.26 63058[107:MRR:888.0,63056.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.26 63061[107:Res:53.1,63058.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.26 63063[108:Spt:63061.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 63065[108:Res:63063.0,61.1] always3(s10) || -> . % 76.04/76.26 63066[108:SSi:63065.0,699.0,61820.0,61825.0,62277.0,63056.0] || -> . % 76.04/76.26 63067[108:Spt:63066.0,63061.0,63063.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.26 63068[108:Spt:63066.0,63061.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 63072[108:Res:63068.0,61.1] always3(s11) || -> . % 76.04/76.26 63073[108:SSi:63072.0,700.0,61826.0,61828.0] || -> . % 76.04/76.26 63074[106:Spt:63073.0,62276.0,62277.0] || until2p7(s10)*+ -> . % 76.04/76.26 63075[106:Spt:63073.0,62276.1] || -> node4(s9)*. % 76.04/76.26 63077[106:MRR:891.0,63075.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.26 63080[106:Res:53.1,63077.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.26 63082[107:Spt:63080.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 63084[107:Res:63082.0,61.1] always3(s9) || -> . % 76.04/76.26 63085[107:SSi:63084.0,698.0,61817.0,61819.0,62275.0,63075.0] || -> . % 76.04/76.26 63086[107:Spt:63085.0,63080.0,63082.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.26 63087[107:Spt:63085.0,63080.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 63091[107:Res:63087.0,61.1] always3(s10) || -> . % 76.04/76.26 63092[107:SSi:63091.0,699.0,61820.0,61825.0] || -> . % 76.04/76.26 63093[105:Spt:63092.0,62274.0,62275.0] || until2p7(s9)*+ -> . % 76.04/76.26 63094[105:Spt:63092.0,62274.1] || -> node4(s8)*. % 76.04/76.26 63096[105:MRR:894.0,63094.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.26 63099[105:Res:53.1,63096.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.26 63101[106:Spt:63099.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 63103[106:Res:63101.0,61.1] always3(s8) || -> . % 76.04/76.26 63104[106:SSi:63103.0,697.0,61811.0,61816.0,62273.0,63094.0] || -> . % 76.04/76.26 63105[106:Spt:63104.0,63099.0,63101.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.26 63106[106:Spt:63104.0,63099.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 63110[106:Res:63106.0,61.1] always3(s9) || -> . % 76.04/76.26 63111[106:SSi:63110.0,698.0,61817.0,61819.0] || -> . % 76.04/76.26 63112[104:Spt:63111.0,62272.0,62273.0] || until2p7(s8)*+ -> . % 76.04/76.26 63113[104:Spt:63111.0,62272.1] || -> node4(s7)*. % 76.04/76.26 63115[104:MRR:897.0,63113.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.26 63118[104:Res:53.1,63115.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.26 63120[104:MRR:63118.0,62262.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 63125[104:Res:63120.0,61.1] always3(s8) || -> . % 76.04/76.26 63126[104:SSi:63125.0,697.0,61811.0,61816.0] || -> . % 76.04/76.26 63127[102:Spt:63126.0,62101.1,62106.0] || xuntil6(s48)* -> . % 76.04/76.26 63128[102:Spt:63126.0,62101.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.26 63131[102:Res:63128.0,61.1] always3(s48) || -> . % 76.04/76.26 63132[102:SSi:63131.0,737.0,62091.0] || -> . % 76.04/76.26 63133[100:Spt:63132.0,62082.2,62090.0] || xuntil6(s47)*+ -> . % 76.04/76.26 63134[100:Spt:63132.0,62082.0,62082.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.26 63135[100:Res:53.1,63134.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.26 63137[100:MRR:63135.0,62074.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.26 63139[100:Res:63137.0,61.1] always3(s48) || -> . % 76.04/76.26 63140[100:SSi:63139.0,737.0] || -> . % 76.04/76.26 63141[99:Spt:63140.0,62078.1,62080.0] || xuntil6(s46)* -> . % 76.04/76.26 63142[99:Spt:63140.0,62078.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.26 63145[99:Res:63142.0,61.1] always3(s46) || -> . % 76.04/76.26 63146[99:SSi:63145.0,735.0,62068.0] || -> . % 76.04/76.26 63147[97:Spt:63146.0,62062.2,62067.0] || xuntil6(s45)*+ -> . % 76.04/76.26 63148[97:Spt:63146.0,62062.0,62062.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.26 63149[97:Res:53.1,63148.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.26 63151[97:MRR:63149.0,62054.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.26 63154[97:Res:63151.0,61.1] always3(s46) || -> . % 76.04/76.26 63155[97:SSi:63154.0,735.0] || -> . % 76.04/76.26 63156[96:Spt:63155.0,62058.1,62060.0] || xuntil6(s44)* -> . % 76.04/76.26 63157[96:Spt:63155.0,62058.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.26 63160[96:Res:63157.0,61.1] always3(s44) || -> . % 76.04/76.26 63161[96:SSi:63160.0,733.0,62048.0] || -> . % 76.04/76.26 63162[94:Spt:63161.0,62045.2,62047.0] || xuntil6(s43)*+ -> . % 76.04/76.26 63163[94:Spt:63161.0,62045.0,62045.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.26 63164[94:Res:53.1,63163.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.26 63166[94:MRR:63164.0,62034.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.26 63168[94:Res:63166.0,61.1] always3(s44) || -> . % 76.04/76.26 63169[94:SSi:63168.0,733.0] || -> . % 76.04/76.26 63170[93:Spt:63169.0,62038.1,62043.0] || xuntil6(s42)* -> . % 76.04/76.26 63171[93:Spt:63169.0,62038.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.26 63174[93:Res:63171.0,61.1] always3(s42) || -> . % 76.04/76.26 63175[93:SSi:63174.0,731.0,62028.0] || -> . % 76.04/76.26 63176[91:Spt:63175.0,62019.2,62027.0] || xuntil6(s41)*+ -> . % 76.04/76.26 63177[91:Spt:63175.0,62019.0,62019.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.26 63178[91:Res:53.1,63177.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.26 63180[91:MRR:63178.0,62011.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.26 63183[91:Res:63180.0,61.1] always3(s42) || -> . % 76.04/76.26 63184[91:SSi:63183.0,731.0] || -> . % 76.04/76.26 63185[90:Spt:63184.0,62015.1,62017.0] || xuntil6(s40)* -> . % 76.04/76.26 63186[90:Spt:63184.0,62015.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.26 63189[90:Res:63186.0,61.1] always3(s40) || -> . % 76.04/76.26 63190[90:SSi:63189.0,729.0,62005.0] || -> . % 76.04/76.26 63191[88:Spt:63190.0,61999.2,62004.0] || xuntil6(s39)*+ -> . % 76.04/76.26 63192[88:Spt:63190.0,61999.0,61999.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.26 63193[88:Res:53.1,63192.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.26 63195[88:MRR:63193.0,61991.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.26 63197[88:Res:63195.0,61.1] always3(s40) || -> . % 76.04/76.26 63198[88:SSi:63197.0,729.0] || -> . % 76.04/76.26 63199[87:Spt:63198.0,61995.1,61997.0] || xuntil6(s38)* -> . % 76.04/76.26 63200[87:Spt:63198.0,61995.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.26 63203[87:Res:63200.0,61.1] always3(s38) || -> . % 76.04/76.26 63204[87:SSi:63203.0,727.0,61985.0] || -> . % 76.04/76.26 63205[85:Spt:63204.0,61982.2,61984.0] || xuntil6(s37)*+ -> . % 76.04/76.26 63206[85:Spt:63204.0,61982.0,61982.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.26 63207[85:Res:53.1,63206.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.26 63209[85:MRR:63207.0,61971.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.26 63211[85:Res:63209.0,61.1] always3(s38) || -> . % 76.04/76.26 63212[85:SSi:63211.0,727.0] || -> . % 76.04/76.26 63213[84:Spt:63212.0,61975.1,61980.0] || xuntil6(s36)* -> . % 76.04/76.26 63214[84:Spt:63212.0,61975.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.26 63217[84:Res:63214.0,61.1] always3(s36) || -> . % 76.04/76.26 63218[84:SSi:63217.0,725.0,61965.0] || -> . % 76.04/76.26 63219[82:Spt:63218.0,61956.2,61964.0] || xuntil6(s35)*+ -> . % 76.04/76.26 63220[82:Spt:63218.0,61956.0,61956.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.26 63221[82:Res:53.1,63220.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.26 63223[82:MRR:63221.0,61948.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.26 63225[82:Res:63223.0,61.1] always3(s36) || -> . % 76.04/76.26 63226[82:SSi:63225.0,725.0] || -> . % 76.04/76.26 63227[81:Spt:63226.0,61952.1,61954.0] || xuntil6(s34)* -> . % 76.04/76.26 63228[81:Spt:63226.0,61952.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.26 63231[81:Res:63228.0,61.1] always3(s34) || -> . % 76.04/76.26 63232[81:SSi:63231.0,723.0,61942.0] || -> . % 76.04/76.26 63233[79:Spt:63232.0,61936.2,61941.0] || xuntil6(s33)*+ -> . % 76.04/76.26 63234[79:Spt:63232.0,61936.0,61936.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.26 63235[79:Res:53.1,63234.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.26 63237[79:MRR:63235.0,61928.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.26 63239[79:Res:63237.0,61.1] always3(s34) || -> . % 76.04/76.26 63240[79:SSi:63239.0,723.0] || -> . % 76.04/76.26 63241[78:Spt:63240.0,61932.1,61934.0] || xuntil6(s32)* -> . % 76.04/76.26 63242[78:Spt:63240.0,61932.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.26 63245[78:Res:63242.0,61.1] always3(s32) || -> . % 76.04/76.26 63246[78:SSi:63245.0,721.0,61919.0] || -> . % 76.04/76.26 63247[76:Spt:63246.0,61917.2,61918.0] || xuntil6(s31)*+ -> . % 76.04/76.26 63248[76:Spt:63246.0,61917.0,61917.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.26 63249[76:Res:53.1,63248.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.26 63251[77:Spt:63249.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.26 63253[77:Res:63251.0,61.1] always3(s32) || -> . % 76.04/76.26 63254[77:SSi:63253.0,721.0] || -> . % 76.04/76.26 63255[77:Spt:63254.0,63249.1,63251.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.26 63256[77:Spt:63254.0,63249.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 63259[77:Res:63256.0,61.1] always3(s31) || -> . % 76.04/76.26 63260[77:SSi:63259.0,720.0,61916.0] || -> . % 76.04/76.26 63261[75:Spt:63260.0,61911.2,61915.0] || xuntil6(s30)*+ -> . % 76.04/76.26 63262[75:Spt:63260.0,61911.0,61911.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.26 63263[75:Res:53.1,63262.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.26 63265[76:Spt:63263.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 63267[76:Res:63265.0,61.1] always3(s31) || -> . % 76.04/76.26 63268[76:SSi:63267.0,720.0] || -> . % 76.04/76.26 63269[76:Spt:63268.0,63263.1,63265.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.26 63270[76:Spt:63268.0,63263.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 63273[76:Res:63270.0,61.1] always3(s30) || -> . % 76.04/76.26 63274[76:SSi:63273.0,719.0,61910.0] || -> . % 76.04/76.26 63275[74:Spt:63274.0,61908.2,61909.0] || xuntil6(s29)*+ -> . % 76.04/76.26 63276[74:Spt:63274.0,61908.0,61908.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.26 63277[74:Res:53.1,63276.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.26 63279[75:Spt:63277.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 63281[75:Res:63279.0,61.1] always3(s30) || -> . % 76.04/76.26 63282[75:SSi:63281.0,719.0] || -> . % 76.04/76.26 63283[75:Spt:63282.0,63277.1,63279.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.26 63284[75:Spt:63282.0,63277.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 63287[75:Res:63284.0,61.1] always3(s29) || -> . % 76.04/76.26 63288[75:SSi:63287.0,718.0,61907.0] || -> . % 76.04/76.26 63289[73:Spt:63288.0,61902.2,61906.0] || xuntil6(s28)*+ -> . % 76.04/76.26 63290[73:Spt:63288.0,61902.0,61902.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.26 63291[73:Res:53.1,63290.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.26 63293[74:Spt:63291.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 63295[74:Res:63293.0,61.1] always3(s29) || -> . % 76.04/76.26 63296[74:SSi:63295.0,718.0] || -> . % 76.04/76.26 63297[74:Spt:63296.0,63291.1,63293.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.26 63298[74:Spt:63296.0,63291.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 63301[74:Res:63298.0,61.1] always3(s28) || -> . % 76.04/76.26 63302[74:SSi:63301.0,717.0,61901.0] || -> . % 76.04/76.26 63303[72:Spt:63302.0,61899.2,61900.0] || xuntil6(s27)*+ -> . % 76.04/76.26 63304[72:Spt:63302.0,61899.0,61899.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.26 63305[72:Res:53.1,63304.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.26 63307[73:Spt:63305.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 63309[73:Res:63307.0,61.1] always3(s28) || -> . % 76.04/76.26 63310[73:SSi:63309.0,717.0] || -> . % 76.04/76.26 63311[73:Spt:63310.0,63305.1,63307.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.26 63312[73:Spt:63310.0,63305.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 63315[73:Res:63312.0,61.1] always3(s27) || -> . % 76.04/76.26 63316[73:SSi:63315.0,716.0,61898.0] || -> . % 76.04/76.26 63317[71:Spt:63316.0,61893.2,61897.0] || xuntil6(s26)*+ -> . % 76.04/76.26 63318[71:Spt:63316.0,61893.0,61893.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.26 63319[71:Res:53.1,63318.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.26 63321[72:Spt:63319.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 63323[72:Res:63321.0,61.1] always3(s27) || -> . % 76.04/76.26 63324[72:SSi:63323.0,716.0] || -> . % 76.04/76.26 63325[72:Spt:63324.0,63319.1,63321.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.26 63326[72:Spt:63324.0,63319.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 63329[72:Res:63326.0,61.1] always3(s26) || -> . % 76.04/76.26 63330[72:SSi:63329.0,715.0,61892.0] || -> . % 76.04/76.26 63331[70:Spt:63330.0,61890.2,61891.0] || xuntil6(s25)*+ -> . % 76.04/76.26 63332[70:Spt:63330.0,61890.0,61890.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.26 63333[70:Res:53.1,63332.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.26 63338[71:Spt:63333.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 63340[71:Res:63338.0,61.1] always3(s25) || -> . % 76.04/76.26 63341[71:SSi:63340.0,714.0,61889.0] || -> . % 76.04/76.26 63342[71:Spt:63341.0,63333.0,63338.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.26 63343[71:Spt:63341.0,63333.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 63347[71:Res:63343.0,61.1] always3(s26) || -> . % 76.04/76.26 63348[71:SSi:63347.0,715.0] || -> . % 76.04/76.26 63349[69:Spt:63348.0,61884.2,61888.0] || xuntil6(s24)*+ -> . % 76.04/76.26 63350[69:Spt:63348.0,61884.0,61884.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.26 63351[69:Res:53.1,63350.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.26 63353[70:Spt:63351.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 63355[70:Res:63353.0,61.1] always3(s25) || -> . % 76.04/76.26 63356[70:SSi:63355.0,714.0] || -> . % 76.04/76.26 63357[70:Spt:63356.0,63351.1,63353.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.26 63358[70:Spt:63356.0,63351.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 63361[70:Res:63358.0,61.1] always3(s24) || -> . % 76.04/76.26 63362[70:SSi:63361.0,713.0,61883.0] || -> . % 76.04/76.26 63363[68:Spt:63362.0,61881.2,61882.0] || xuntil6(s23)*+ -> . % 76.04/76.26 63364[68:Spt:63362.0,61881.0,61881.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.26 63365[68:Res:53.1,63364.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.26 63367[69:Spt:63365.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 63369[69:Res:63367.0,61.1] always3(s24) || -> . % 76.04/76.26 63370[69:SSi:63369.0,713.0] || -> . % 76.04/76.26 63371[69:Spt:63370.0,63365.1,63367.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.26 63372[69:Spt:63370.0,63365.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 63375[69:Res:63372.0,61.1] always3(s23) || -> . % 76.04/76.26 63376[69:SSi:63375.0,712.0,61880.0] || -> . % 76.04/76.26 63377[67:Spt:63376.0,61875.2,61879.0] || xuntil6(s22)*+ -> . % 76.04/76.26 63378[67:Spt:63376.0,61875.0,61875.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.26 63379[67:Res:53.1,63378.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.26 63384[68:Spt:63379.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 63386[68:Res:63384.0,61.1] always3(s22) || -> . % 76.04/76.26 63387[68:SSi:63386.0,711.0,61874.0] || -> . % 76.04/76.26 63388[68:Spt:63387.0,63379.0,63384.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.26 63389[68:Spt:63387.0,63379.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 63393[68:Res:63389.0,61.1] always3(s23) || -> . % 76.04/76.26 63394[68:SSi:63393.0,712.0] || -> . % 76.04/76.26 63395[66:Spt:63394.0,61872.2,61873.0] || xuntil6(s21)*+ -> . % 76.04/76.26 63396[66:Spt:63394.0,61872.0,61872.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.26 63397[66:Res:53.1,63396.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.26 63399[67:Spt:63397.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 63401[67:Res:63399.0,61.1] always3(s22) || -> . % 76.04/76.26 63402[67:SSi:63401.0,711.0] || -> . % 76.04/76.26 63403[67:Spt:63402.0,63397.1,63399.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.26 63404[67:Spt:63402.0,63397.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 63407[67:Res:63404.0,61.1] always3(s21) || -> . % 76.04/76.26 63408[67:SSi:63407.0,710.0,61871.0] || -> . % 76.04/76.26 63409[65:Spt:63408.0,61866.2,61870.0] || xuntil6(s20)*+ -> . % 76.04/76.26 63410[65:Spt:63408.0,61866.0,61866.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.26 63411[65:Res:53.1,63410.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.26 63413[66:Spt:63411.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 63415[66:Res:63413.0,61.1] always3(s21) || -> . % 76.04/76.26 63416[66:SSi:63415.0,710.0] || -> . % 76.04/76.26 63417[66:Spt:63416.0,63411.1,63413.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.26 63418[66:Spt:63416.0,63411.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 63421[66:Res:63418.0,61.1] always3(s20) || -> . % 76.04/76.26 63422[66:SSi:63421.0,709.0,61865.0] || -> . % 76.04/76.26 63423[64:Spt:63422.0,61863.2,61864.0] || xuntil6(s19)*+ -> . % 76.04/76.26 63424[64:Spt:63422.0,61863.0,61863.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.26 63425[64:Res:53.1,63424.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.26 63430[65:Spt:63425.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 63432[65:Res:63430.0,61.1] always3(s19) || -> . % 76.04/76.26 63433[65:SSi:63432.0,708.0,61862.0] || -> . % 76.04/76.26 63434[65:Spt:63433.0,63425.0,63430.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.26 63435[65:Spt:63433.0,63425.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 63439[65:Res:63435.0,61.1] always3(s20) || -> . % 76.04/76.26 63440[65:SSi:63439.0,709.0] || -> . % 76.04/76.26 63441[63:Spt:63440.0,61857.2,61861.0] || xuntil6(s18)*+ -> . % 76.04/76.26 63442[63:Spt:63440.0,61857.0,61857.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.26 63443[63:Res:53.1,63442.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.26 63445[64:Spt:63443.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 63447[64:Res:63445.0,61.1] always3(s19) || -> . % 76.04/76.26 63448[64:SSi:63447.0,708.0] || -> . % 76.04/76.26 63449[64:Spt:63448.0,63443.1,63445.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.26 63450[64:Spt:63448.0,63443.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 63453[64:Res:63450.0,61.1] always3(s18) || -> . % 76.04/76.26 63454[64:SSi:63453.0,707.0,61856.0] || -> . % 76.04/76.26 63455[62:Spt:63454.0,61854.2,61855.0] || xuntil6(s17)*+ -> . % 76.04/76.26 63456[62:Spt:63454.0,61854.0,61854.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.26 63457[62:Res:53.1,63456.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.26 63459[63:Spt:63457.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 63461[63:Res:63459.0,61.1] always3(s18) || -> . % 76.04/76.26 63462[63:SSi:63461.0,707.0] || -> . % 76.04/76.26 63463[63:Spt:63462.0,63457.1,63459.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.26 63464[63:Spt:63462.0,63457.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 63467[63:Res:63464.0,61.1] always3(s17) || -> . % 76.04/76.26 63468[63:SSi:63467.0,706.0,61853.0] || -> . % 76.04/76.26 63469[61:Spt:63468.0,61848.2,61852.0] || xuntil6(s16)*+ -> . % 76.04/76.26 63470[61:Spt:63468.0,61848.0,61848.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.26 63471[61:Res:53.1,63470.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.26 63476[62:Spt:63471.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 63478[62:Res:63476.0,61.1] always3(s16) || -> . % 76.04/76.26 63479[62:SSi:63478.0,705.0,61847.0] || -> . % 76.04/76.26 63480[62:Spt:63479.0,63471.0,63476.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.26 63481[62:Spt:63479.0,63471.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 63485[62:Res:63481.0,61.1] always3(s17) || -> . % 76.04/76.26 63486[62:SSi:63485.0,706.0] || -> . % 76.04/76.26 63487[60:Spt:63486.0,61845.2,61846.0] || xuntil6(s15)*+ -> . % 76.04/76.26 63488[60:Spt:63486.0,61845.0,61845.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.26 63489[60:Res:53.1,63488.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.26 63491[61:Spt:63489.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 63493[61:Res:63491.0,61.1] always3(s16) || -> . % 76.04/76.26 63494[61:SSi:63493.0,705.0] || -> . % 76.04/76.26 63495[61:Spt:63494.0,63489.1,63491.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.26 63496[61:Spt:63494.0,63489.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 63499[61:Res:63496.0,61.1] always3(s15) || -> . % 76.04/76.26 63500[61:SSi:63499.0,704.0,61844.0] || -> . % 76.04/76.26 63501[59:Spt:63500.0,61839.2,61843.0] || xuntil6(s14)*+ -> . % 76.04/76.26 63502[59:Spt:63500.0,61839.0,61839.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.26 63503[59:Res:53.1,63502.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.26 63505[60:Spt:63503.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 63507[60:Res:63505.0,61.1] always3(s15) || -> . % 76.04/76.26 63508[60:SSi:63507.0,704.0] || -> . % 76.04/76.26 63509[60:Spt:63508.0,63503.1,63505.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.26 63510[60:Spt:63508.0,63503.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 63513[60:Res:63510.0,61.1] always3(s14) || -> . % 76.04/76.26 63514[60:SSi:63513.0,703.0,61838.0] || -> . % 76.04/76.26 63515[58:Spt:63514.0,61836.2,61837.0] || xuntil6(s13)*+ -> . % 76.04/76.26 63516[58:Spt:63514.0,61836.0,61836.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.26 63517[58:Res:53.1,63516.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.26 63522[59:Spt:63517.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 63524[59:Res:63522.0,61.1] always3(s13) || -> . % 76.04/76.26 63525[59:SSi:63524.0,702.0,61835.0] || -> . % 76.04/76.26 63526[59:Spt:63525.0,63517.0,63522.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.26 63527[59:Spt:63525.0,63517.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 63531[59:Res:63527.0,61.1] always3(s14) || -> . % 76.04/76.26 63532[59:SSi:63531.0,703.0] || -> . % 76.04/76.26 63533[57:Spt:63532.0,61830.2,61834.0] || xuntil6(s12)*+ -> . % 76.04/76.26 63534[57:Spt:63532.0,61830.0,61830.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.26 63535[57:Res:53.1,63534.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.26 63537[58:Spt:63535.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 63539[58:Res:63537.0,61.1] always3(s13) || -> . % 76.04/76.26 63540[58:SSi:63539.0,702.0] || -> . % 76.04/76.26 63541[58:Spt:63540.0,63535.1,63537.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.26 63542[58:Spt:63540.0,63535.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 63545[58:Res:63542.0,61.1] always3(s12) || -> . % 76.04/76.26 63546[58:SSi:63545.0,701.0,61829.0] || -> . % 76.04/76.26 63547[56:Spt:63546.0,61827.2,61828.0] || xuntil6(s11)*+ -> . % 76.04/76.26 63548[56:Spt:63546.0,61827.0,61827.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.26 63549[56:Res:53.1,63548.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.26 63551[57:Spt:63549.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 63553[57:Res:63551.0,61.1] always3(s12) || -> . % 76.04/76.26 63554[57:SSi:63553.0,701.0] || -> . % 76.04/76.26 63555[57:Spt:63554.0,63549.1,63551.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.26 63556[57:Spt:63554.0,63549.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 63559[57:Res:63556.0,61.1] always3(s11) || -> . % 76.04/76.26 63560[57:SSi:63559.0,700.0,61826.0] || -> . % 76.04/76.26 63561[55:Spt:63560.0,61821.2,61825.0] || xuntil6(s10)*+ -> . % 76.04/76.26 63562[55:Spt:63560.0,61821.0,61821.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.26 63563[55:Res:53.1,63562.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.26 63568[56:Spt:63563.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 63570[56:Res:63568.0,61.1] always3(s10) || -> . % 76.04/76.26 63571[56:SSi:63570.0,699.0,61820.0] || -> . % 76.04/76.26 63572[56:Spt:63571.0,63563.0,63568.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.26 63573[56:Spt:63571.0,63563.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 63577[56:Res:63573.0,61.1] always3(s11) || -> . % 76.04/76.26 63578[56:SSi:63577.0,700.0] || -> . % 76.04/76.26 63579[54:Spt:63578.0,61818.2,61819.0] || xuntil6(s9)*+ -> . % 76.04/76.26 63580[54:Spt:63578.0,61818.0,61818.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.26 63581[54:Res:53.1,63580.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.26 63583[55:Spt:63581.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 63585[55:Res:63583.0,61.1] always3(s10) || -> . % 76.04/76.26 63586[55:SSi:63585.0,699.0] || -> . % 76.04/76.26 63587[55:Spt:63586.0,63581.1,63583.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.26 63588[55:Spt:63586.0,63581.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 63591[55:Res:63588.0,61.1] always3(s9) || -> . % 76.04/76.26 63592[55:SSi:63591.0,698.0,61817.0] || -> . % 76.04/76.26 63593[53:Spt:63592.0,61812.2,61816.0] || xuntil6(s8)*+ -> . % 76.04/76.26 63594[53:Spt:63592.0,61812.0,61812.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.26 63595[53:Res:53.1,63594.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.26 63597[54:Spt:63595.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 63599[54:Res:63597.0,61.1] always3(s9) || -> . % 76.04/76.26 63600[54:SSi:63599.0,698.0] || -> . % 76.04/76.26 63601[54:Spt:63600.0,63595.1,63597.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.26 63602[54:Spt:63600.0,63595.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 63605[54:Res:63602.0,61.1] always3(s8) || -> . % 76.04/76.26 63606[54:SSi:63605.0,697.0,61811.0] || -> . % 76.04/76.26 63607[52:Spt:63606.0,61809.2,61810.0] || xuntil6(s7)*+ -> . % 76.04/76.26 63608[52:Spt:63606.0,61809.0,61809.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.26 63609[52:Res:53.1,63608.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.26 63614[53:Spt:63609.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 63616[53:Res:63614.0,61.1] always3(s7) || -> . % 76.04/76.26 63617[53:SSi:63616.0,696.0,61808.0] || -> . % 76.04/76.26 63618[53:Spt:63617.0,63609.0,63614.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.26 63619[53:Spt:63617.0,63609.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 63626[53:Res:63619.0,61.1] always3(s8) || -> . % 76.04/76.26 63627[53:SSi:63626.0,697.0] || -> . % 76.04/76.26 63628[51:Spt:63627.0,61803.2,61807.0] || xuntil6(s6)*+ -> . % 76.04/76.26 63629[51:Spt:63627.0,61803.0,61803.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.26 63630[51:Res:53.1,63629.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.26 63632[52:Spt:63630.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 63634[52:Res:63632.0,61.1] always3(s6) || -> . % 76.04/76.26 63635[52:SSi:63634.0,695.0,61802.0] || -> . % 76.04/76.26 63636[52:Spt:63635.0,63630.0,63632.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.26 63637[52:Spt:63635.0,63630.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 63641[52:Res:63637.0,61.1] always3(s7) || -> . % 76.04/76.26 63642[52:SSi:63641.0,696.0] || -> . % 76.04/76.26 63643[50:Spt:63642.0,61800.2,61801.0] || xuntil6(s5)*+ -> . % 76.04/76.26 63644[50:Spt:63642.0,61800.0,61800.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.26 63645[50:Res:53.1,63644.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.26 63647[51:Spt:63645.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.26 63649[51:Res:63647.0,61.1] always3(s5) || -> . % 76.04/76.26 63650[51:SSi:63649.0,694.0,61799.0] || -> . % 76.04/76.26 63651[51:Spt:63650.0,63645.0,63647.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.26 63652[51:Spt:63650.0,63645.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 63656[51:Res:63652.0,61.1] always3(s6) || -> . % 76.04/76.26 63657[51:SSi:63656.0,695.0] || -> . % 76.04/76.26 63658[49:Spt:63657.0,61794.2,61798.0] || xuntil6(s4)*+ -> . % 76.04/76.26 63659[49:Spt:63657.0,61794.0,61794.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.26 63660[49:Res:53.1,63659.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.26 63665[50:Spt:63660.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.26 63667[50:Res:63665.0,61.1] always3(s4) || -> . % 76.04/76.26 63668[50:SSi:63667.0,693.0,61793.0] || -> . % 76.04/76.26 63669[50:Spt:63668.0,63660.0,63665.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.26 63670[50:Spt:63668.0,63660.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.26 63674[50:Res:63670.0,61.1] always3(s5) || -> . % 76.04/76.26 63675[50:SSi:63674.0,694.0] || -> . % 76.04/76.26 63676[48:Spt:63675.0,61791.2,61792.0] || xuntil6(s3)*+ -> . % 76.04/76.26 63677[48:Spt:63675.0,61791.0,61791.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.26 63678[48:Res:53.1,63677.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.26 63680[49:Spt:63678.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.26 63682[49:Res:63680.0,61.1] always3(s3) || -> . % 76.04/76.26 63683[49:SSi:63682.0,692.0,61790.0] || -> . % 76.04/76.26 63684[49:Spt:63683.0,63678.0,63680.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.26 63685[49:Spt:63683.0,63678.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.26 63689[49:Res:63685.0,61.1] always3(s4) || -> . % 76.04/76.26 63690[49:SSi:63689.0,693.0] || -> . % 76.04/76.26 63691[47:Spt:63690.0,61785.2,61789.0] || xuntil6(s2)*+ -> . % 76.04/76.26 63692[47:Spt:63690.0,61785.0,61785.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.26 63693[47:Res:53.1,63692.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.26 63695[48:Spt:63693.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.26 63697[48:Res:63695.0,61.1] always3(s2) || -> . % 76.04/76.26 63698[48:SSi:63697.0,691.0,61784.0] || -> . % 76.04/76.26 63699[48:Spt:63698.0,63693.0,63695.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.26 63700[48:Spt:63698.0,63693.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.26 63704[48:Res:63700.0,61.1] always3(s3) || -> . % 76.04/76.26 63705[48:SSi:63704.0,692.0] || -> . % 76.04/76.26 63706[46:Spt:63705.0,61779.2,61783.0] || xuntil6(s1)*+ -> . % 76.04/76.26 63707[46:Spt:63705.0,61779.0,61779.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.26 63708[46:Res:53.1,63707.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.26 63713[47:Spt:63708.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.26 63715[47:Res:63713.0,61.1] always3(s1) || -> . % 76.04/76.26 63716[47:SSi:63715.0,690.0,61778.0] || -> . % 76.04/76.26 63717[47:Spt:63716.0,63708.0,63713.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.26 63718[47:Spt:63716.0,63708.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.26 63723[47:Res:63718.0,61.1] always3(s2) || -> . % 76.04/76.26 63724[47:SSi:63723.0,691.0] || -> . % 76.04/76.26 63725[45:Spt:63724.0,74.0,61777.0] || xuntil6(s0)*+ -> . % 76.04/76.26 63726[45:Spt:63724.0,74.1] || -> node4(s0)*. % 76.04/76.26 63727[45:MRR:758.1,63725.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.26 63729[45:Res:63727.0,61.1] always3(s1) || -> . % 76.04/76.26 63730[45:SSi:63729.0,690.0] || -> . % 76.04/76.26 63731[44:Spt:63730.0,61767.0,61771.0] || trans(s49,s7)*+ -> . % 76.04/76.26 63732[44:Spt:63730.0,61767.1,61767.2,61767.3,61767.4,61767.5,61767.6,61767.7] || -> trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.26 63733[44:MRR:61769.0,63731.0] || -> trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.26 63735[44:MRR:61770.1,63731.0] xuntil6(s49) || -> trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.26 63736[45:Spt:63732.0] || -> trans(s49,s6)*. % 76.04/76.26 63737[45:Res:63736.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s6)*. % 76.04/76.26 63739[45:Res:63736.0,60.0] || -> node2(s49,s6)*. % 76.04/76.26 63740[45:SSi:63737.1,50.0,738.0] xuntil6(s49) || -> until2p7(s6)*. % 76.04/76.26 63741[45:Res:63739.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 63742[46:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.26 63743[46:MRR:176.0,63742.0] || -> until5(s1)*. % 76.04/76.26 63744[46:MRR:62220.0,63743.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.26 63748[47:Spt:63744.2] || -> xuntil6(s1)*. % 76.04/76.26 63749[47:MRR:175.0,63748.0] || -> until5(s2)*. % 76.04/76.26 63750[47:MRR:62216.0,63749.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.26 63751[48:Spt:63750.2] || -> xuntil6(s2)*. % 76.04/76.26 63752[48:MRR:174.0,63751.0] || -> until5(s3)*. % 76.04/76.26 63753[48:MRR:62212.0,63752.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.26 63754[49:Spt:63753.2] || -> xuntil6(s3)*. % 76.04/76.26 63755[49:MRR:173.0,63754.0] || -> until5(s4)*. % 76.04/76.26 63756[49:MRR:62211.0,63755.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.26 63757[50:Spt:63756.2] || -> xuntil6(s4)*. % 76.04/76.26 63758[50:MRR:172.0,63757.0] || -> until5(s5)*. % 76.04/76.26 63759[50:MRR:62204.0,63758.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.26 63763[51:Spt:63759.2] || -> xuntil6(s5)*. % 76.04/76.26 63764[51:MRR:171.0,63763.0] || -> until5(s6)*. % 76.04/76.26 63765[51:MRR:62200.0,63764.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.26 63766[52:Spt:63765.2] || -> xuntil6(s6)*. % 76.04/76.26 63767[52:MRR:170.0,63766.0] || -> until5(s7)*. % 76.04/76.26 63768[52:MRR:62196.0,63767.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.26 63772[53:Spt:63768.2] || -> xuntil6(s7)*. % 76.04/76.26 63773[53:MRR:169.0,63772.0] || -> until5(s8)*. % 76.04/76.26 63774[53:MRR:62192.0,63773.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.26 63775[54:Spt:63774.2] || -> xuntil6(s8)*. % 76.04/76.26 63776[54:MRR:168.0,63775.0] || -> until5(s9)*. % 76.04/76.26 63777[54:MRR:62185.0,63776.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.26 63781[55:Spt:63777.2] || -> xuntil6(s9)*. % 76.04/76.26 63782[55:MRR:167.0,63781.0] || -> until5(s10)*. % 76.04/76.26 63783[55:MRR:62181.0,63782.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.26 63784[56:Spt:63783.2] || -> xuntil6(s10)*. % 76.04/76.26 63785[56:MRR:166.0,63784.0] || -> until5(s11)*. % 76.04/76.26 63786[56:MRR:62180.0,63785.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.26 63790[57:Spt:63786.2] || -> xuntil6(s11)*. % 76.04/76.26 63791[57:MRR:165.0,63790.0] || -> until5(s12)*. % 76.04/76.26 63792[57:MRR:62173.0,63791.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.26 63793[58:Spt:63792.2] || -> xuntil6(s12)*. % 76.04/76.26 63794[58:MRR:164.0,63793.0] || -> until5(s13)*. % 76.04/76.26 63795[58:MRR:62172.0,63794.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.26 63799[59:Spt:63795.2] || -> xuntil6(s13)*. % 76.04/76.26 63800[59:MRR:163.0,63799.0] || -> until5(s14)*. % 76.04/76.26 63801[59:MRR:62171.0,63800.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.26 63802[60:Spt:63801.2] || -> xuntil6(s14)*. % 76.04/76.26 63803[60:MRR:162.0,63802.0] || -> until5(s15)*. % 76.04/76.26 63804[60:MRR:62161.0,63803.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.26 63808[61:Spt:63804.2] || -> xuntil6(s15)*. % 76.04/76.26 63809[61:MRR:161.0,63808.0] || -> until5(s16)*. % 76.04/76.26 63810[61:MRR:62160.0,63809.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.26 63811[62:Spt:63810.2] || -> xuntil6(s16)*. % 76.04/76.26 63812[62:MRR:160.0,63811.0] || -> until5(s17)*. % 76.04/76.26 63813[62:MRR:62156.0,63812.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.26 63817[63:Spt:63813.2] || -> xuntil6(s17)*. % 76.04/76.26 63818[63:MRR:159.0,63817.0] || -> until5(s18)*. % 76.04/76.26 63819[63:MRR:62149.0,63818.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.26 63820[64:Spt:63819.2] || -> xuntil6(s18)*. % 76.04/76.26 63821[64:MRR:158.0,63820.0] || -> until5(s19)*. % 76.04/76.26 63822[64:MRR:62145.0,63821.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.26 63826[65:Spt:63822.2] || -> xuntil6(s19)*. % 76.04/76.26 63827[65:MRR:157.0,63826.0] || -> until5(s20)*. % 76.04/76.26 63828[65:MRR:62144.0,63827.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.26 63829[66:Spt:63828.2] || -> xuntil6(s20)*. % 76.04/76.26 63830[66:MRR:156.0,63829.0] || -> until5(s21)*. % 76.04/76.26 63831[66:MRR:62140.0,63830.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.26 63835[67:Spt:63831.2] || -> xuntil6(s21)*. % 76.04/76.26 63836[67:MRR:155.0,63835.0] || -> until5(s22)*. % 76.04/76.26 63837[67:MRR:62133.0,63836.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.26 63838[68:Spt:63837.2] || -> xuntil6(s22)*. % 76.04/76.26 63839[68:MRR:154.0,63838.0] || -> until5(s23)*. % 76.04/76.26 63840[68:MRR:62132.0,63839.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.26 63844[69:Spt:63840.2] || -> xuntil6(s23)*. % 76.04/76.26 63845[69:MRR:153.0,63844.0] || -> until5(s24)*. % 76.04/76.26 63846[69:MRR:62125.0,63845.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.26 63847[70:Spt:63846.2] || -> xuntil6(s24)*. % 76.04/76.26 63848[70:MRR:152.0,63847.0] || -> until5(s25)*. % 76.04/76.26 63849[70:MRR:62121.0,63848.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.26 63853[71:Spt:63849.2] || -> xuntil6(s25)*. % 76.04/76.26 63854[71:MRR:151.0,63853.0] || -> until5(s26)*. % 76.04/76.26 63855[71:MRR:62120.0,63854.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.26 63856[72:Spt:63855.2] || -> xuntil6(s26)*. % 76.04/76.26 63857[72:MRR:150.0,63856.0] || -> until5(s27)*. % 76.04/76.26 63858[72:MRR:62116.0,63857.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.26 63862[73:Spt:63858.2] || -> xuntil6(s27)*. % 76.04/76.26 63863[73:MRR:149.0,63862.0] || -> until5(s28)*. % 76.04/76.26 63864[73:MRR:62115.0,63863.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.26 63865[74:Spt:63864.2] || -> xuntil6(s28)*. % 76.04/76.26 63866[74:MRR:148.0,63865.0] || -> until5(s29)*. % 76.04/76.26 63867[74:MRR:62114.0,63866.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.26 63871[75:Spt:63867.2] || -> xuntil6(s29)*. % 76.04/76.26 63872[75:MRR:147.0,63871.0] || -> until5(s30)*. % 76.04/76.26 63873[75:MRR:62113.0,63872.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.26 63874[76:Spt:63873.2] || -> xuntil6(s30)*. % 76.04/76.26 63875[76:MRR:146.0,63874.0] || -> until5(s31)*. % 76.04/76.26 63876[76:MRR:62109.0,63875.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.26 63880[77:Spt:63876.2] || -> xuntil6(s31)*. % 76.04/76.26 63881[77:MRR:145.0,63880.0] || -> until5(s32)*. % 76.04/76.26 63882[77:MRR:60290.0,63881.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.26 63883[78:Spt:63882.2] || -> xuntil6(s32)*. % 76.04/76.26 63884[78:MRR:144.0,63883.0] || -> until5(s33)*. % 76.04/76.26 63885[78:MRR:62224.0,63884.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.26 63889[79:Spt:63885.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.26 63891[79:Res:63889.0,61.1] always3(s34) || -> . % 76.04/76.26 63892[79:SSi:63891.0,723.0] || -> . % 76.04/76.26 63893[79:Spt:63892.0,63885.1,63889.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.26 63894[79:Spt:63892.0,63885.0,63885.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.26 63896[79:MRR:819.2,63893.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.26 63897[79:Res:53.1,63894.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.26 63899[80:Spt:63897.1] || -> xuntil6(s33)*. % 76.04/76.26 63900[80:MRR:143.0,63899.0] || -> until5(s34)*. % 76.04/76.26 63901[80:MRR:60294.0,63900.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.26 63906[81:Spt:63901.2] || -> xuntil6(s34)*. % 76.04/76.26 63907[81:MRR:142.0,63906.0] || -> until5(s35)*. % 76.04/76.26 63908[81:MRR:62231.0,63907.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.26 63909[82:Spt:63908.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.26 63911[82:Res:63909.0,61.1] always3(s36) || -> . % 76.04/76.26 63912[82:SSi:63911.0,725.0] || -> . % 76.04/76.26 63913[82:Spt:63912.0,63908.1,63909.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.26 63914[82:Spt:63912.0,63908.0,63908.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.26 63916[82:MRR:813.2,63913.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.26 63917[82:Res:53.1,63914.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.26 63919[83:Spt:63917.1] || -> xuntil6(s35)*. % 76.04/76.26 63920[83:MRR:141.0,63919.0] || -> until5(s36)*. % 76.04/76.26 63921[83:MRR:60298.0,63920.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.26 63929[84:Spt:63921.2] || -> xuntil6(s36)*. % 76.04/76.26 63930[84:MRR:140.0,63929.0] || -> until5(s37)*. % 76.04/76.26 63931[84:MRR:62232.0,63930.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.26 63932[85:Spt:63931.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.26 63934[85:Res:63932.0,61.1] always3(s38) || -> . % 76.04/76.26 63935[85:SSi:63934.0,727.0] || -> . % 76.04/76.26 63936[85:Spt:63935.0,63931.1,63932.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.26 63937[85:Spt:63935.0,63931.0,63931.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.26 63939[85:MRR:807.2,63936.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.26 63940[85:Res:53.1,63937.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.26 63945[86:Spt:63940.1] || -> xuntil6(s37)*. % 76.04/76.26 63946[86:MRR:139.0,63945.0] || -> until5(s38)*. % 76.04/76.26 63947[86:MRR:60305.0,63946.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.26 63949[87:Spt:63947.2] || -> xuntil6(s38)*. % 76.04/76.26 63950[87:MRR:138.0,63949.0] || -> until5(s39)*. % 76.04/76.26 63951[87:MRR:62236.0,63950.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.26 63952[88:Spt:63951.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.26 63954[88:Res:63952.0,61.1] always3(s40) || -> . % 76.04/76.26 63955[88:SSi:63954.0,729.0] || -> . % 76.04/76.26 63956[88:Spt:63955.0,63951.1,63952.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.26 63957[88:Spt:63955.0,63951.0,63951.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.26 63959[88:MRR:801.2,63956.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.26 63960[88:Res:53.1,63957.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.26 63962[89:Spt:63960.1] || -> xuntil6(s39)*. % 76.04/76.26 63963[89:MRR:137.0,63962.0] || -> until5(s40)*. % 76.04/76.26 63964[89:MRR:60306.0,63963.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.26 63969[90:Spt:63964.2] || -> xuntil6(s40)*. % 76.04/76.26 63970[90:MRR:136.0,63969.0] || -> until5(s41)*. % 76.04/76.26 63971[90:MRR:62240.0,63970.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.26 63972[91:Spt:63971.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.26 63974[91:Res:63972.0,61.1] always3(s42) || -> . % 76.04/76.26 63975[91:SSi:63974.0,731.0] || -> . % 76.04/76.26 63976[91:Spt:63975.0,63971.1,63972.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.26 63977[91:Spt:63975.0,63971.0,63971.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.26 63979[91:MRR:795.2,63976.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.26 63980[91:Res:53.1,63977.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.26 63982[92:Spt:63980.1] || -> xuntil6(s41)*. % 76.04/76.26 63983[92:MRR:135.0,63982.0] || -> until5(s42)*. % 76.04/76.26 63984[92:MRR:60310.0,63983.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.26 63992[93:Spt:63984.2] || -> xuntil6(s42)*. % 76.04/76.26 63993[93:MRR:134.0,63992.0] || -> until5(s43)*. % 76.04/76.26 63994[93:MRR:62244.0,63993.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.26 63995[94:Spt:63994.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.26 63997[94:Res:63995.0,61.1] always3(s44) || -> . % 76.04/76.26 63998[94:SSi:63997.0,733.0] || -> . % 76.04/76.26 63999[94:Spt:63998.0,63994.1,63995.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.26 64000[94:Spt:63998.0,63994.0,63994.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.26 64002[94:MRR:789.2,63999.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.26 64003[94:Res:53.1,64000.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.26 64008[95:Spt:64003.1] || -> xuntil6(s43)*. % 76.04/76.26 64009[95:MRR:133.0,64008.0] || -> until5(s44)*. % 76.04/76.26 64010[95:MRR:60314.0,64009.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.26 64012[96:Spt:64010.2] || -> xuntil6(s44)*. % 76.04/76.26 64013[96:MRR:132.0,64012.0] || -> until5(s45)*. % 76.04/76.26 64014[96:MRR:62251.0,64013.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.26 64015[97:Spt:64014.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.26 64017[97:Res:64015.0,61.1] always3(s46) || -> . % 76.04/76.26 64018[97:SSi:64017.0,735.0] || -> . % 76.04/76.26 64019[97:Spt:64018.0,64014.1,64015.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.26 64020[97:Spt:64018.0,64014.0,64014.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.26 64022[97:MRR:783.2,64019.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.26 64023[97:Res:53.1,64020.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.26 64025[98:Spt:64023.1] || -> xuntil6(s45)*. % 76.04/76.26 64026[98:MRR:131.0,64025.0] || -> until5(s46)*. % 76.04/76.26 64027[98:MRR:60318.0,64026.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.26 64032[99:Spt:64027.2] || -> xuntil6(s46)*. % 76.04/76.26 64033[99:MRR:130.0,64032.0] || -> until5(s47)*. % 76.04/76.26 64034[99:MRR:62252.0,64033.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.26 64035[100:Spt:64034.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.26 64037[100:Res:64035.0,61.1] always3(s48) || -> . % 76.04/76.26 64038[100:SSi:64037.0,737.0] || -> . % 76.04/76.26 64039[100:Spt:64038.0,64034.1,64035.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.26 64040[100:Spt:64038.0,64034.0,64034.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.26 64042[100:MRR:777.2,64039.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.26 64043[100:Res:53.1,64040.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.26 64045[101:Spt:64043.1] || -> xuntil6(s47)*. % 76.04/76.26 64046[101:MRR:129.0,64045.0] || -> until5(s48)*. % 76.04/76.26 64047[101:MRR:60322.0,64046.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.26 64055[102:Spt:64047.2] || -> xuntil6(s48)*. % 76.04/76.26 64056[102:MRR:128.0,64055.0] || -> until5(s49)*. % 76.04/76.26 64057[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.26 64058[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.26 64062[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.26 64063[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.26 64064[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.26 64065[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.26 64069[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.26 64073[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.26 64080[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.26 64081[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.26 64085[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.26 64092[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.26 64093[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.26 64100[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.26 64104[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.26 64105[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.26 64109[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.26 64116[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.26 64120[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.26 64121[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.26 64131[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.26 64132[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.26 64133[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.26 64140[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.26 64141[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.26 64145[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.26 64152[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.26 64156[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.26 64160[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.26 64164[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.26 64171[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.26 64172[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.26 64174[45:SoR:63741.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 64182[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.26 64183[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.26 64187[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.26 64191[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.26 64195[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.26 64202[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.26 64203[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.26 64207[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.26 64208[45:SoR:64174.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)* xuntil6(s49). % 76.04/76.26 64209[102:SSi:64208.0,50.0,738.0,64056.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s6,c_busy)* xuntil6(s49). % 76.04/76.26 64210[103:Spt:64209.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 64212[103:Res:64210.0,61.1] always3(s6) || -> . % 76.04/76.26 64213[103:SSi:64212.0,695.0,63764.0,63766.0] || -> . % 76.04/76.26 64214[103:Spt:64213.0,64209.1,64210.0] || m_main_v_state(s6,c_busy)*+ -> . % 76.04/76.26 64215[103:Spt:64213.0,64209.0,64209.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.26 64219[103:MRR:64174.2,64214.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.26 64220[103:Res:53.1,64215.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.26 64222[104:Spt:64220.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.26 64224[104:Res:64222.0,61.1] always3(s49) || -> . % 76.04/76.26 64225[104:SSi:64224.0,50.0,738.0,64056.0] || -> . % 76.04/76.26 64226[104:Spt:64225.0,64220.0,64222.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.26 64227[104:Spt:64225.0,64220.1] || -> xuntil6(s49)*. % 76.04/76.26 64228[104:MRR:63740.0,64227.0] || -> until2p7(s6)*. % 76.04/76.26 64229[104:MRR:202.0,64228.0] || -> until2p7(s7)* node4(s6). % 76.04/76.26 64231[104:MRR:774.2,64226.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.26 64232[105:Spt:64229.0] || -> until2p7(s7)*. % 76.04/76.26 64233[105:MRR:203.0,64232.0] || -> until2p7(s8)* node4(s7). % 76.04/76.26 64234[106:Spt:64233.0] || -> until2p7(s8)*. % 76.04/76.26 64235[106:MRR:204.0,64234.0] || -> until2p7(s9)* node4(s8). % 76.04/76.26 64236[107:Spt:64235.0] || -> until2p7(s9)*. % 76.04/76.26 64237[107:MRR:205.0,64236.0] || -> until2p7(s10)* node4(s9). % 76.04/76.26 64238[108:Spt:64237.0] || -> until2p7(s10)*. % 76.04/76.26 64239[108:MRR:206.0,64238.0] || -> until2p7(s11)* node4(s10). % 76.04/76.26 64240[109:Spt:64239.0] || -> until2p7(s11)*. % 76.04/76.26 64241[109:MRR:207.0,64240.0] || -> until2p7(s12)* node4(s11). % 76.04/76.26 64242[110:Spt:64241.0] || -> until2p7(s12)*. % 76.04/76.26 64243[110:MRR:208.0,64242.0] || -> until2p7(s13)* node4(s12). % 76.04/76.26 64244[111:Spt:64243.0] || -> until2p7(s13)*. % 76.04/76.26 64245[111:MRR:209.0,64244.0] || -> until2p7(s14)* node4(s13). % 76.04/76.26 64246[112:Spt:64245.0] || -> until2p7(s14)*. % 76.04/76.26 64247[112:MRR:210.0,64246.0] || -> until2p7(s15)* node4(s14). % 76.04/76.26 64248[113:Spt:64247.0] || -> until2p7(s15)*. % 76.04/76.26 64249[113:MRR:211.0,64248.0] || -> until2p7(s16)* node4(s15). % 76.04/76.26 64250[114:Spt:64249.0] || -> until2p7(s16)*. % 76.04/76.26 64251[114:MRR:212.0,64250.0] || -> until2p7(s17)* node4(s16). % 76.04/76.26 64252[115:Spt:64251.0] || -> until2p7(s17)*. % 76.04/76.26 64253[115:MRR:213.0,64252.0] || -> until2p7(s18)* node4(s17). % 76.04/76.26 64254[116:Spt:64253.0] || -> until2p7(s18)*. % 76.04/76.26 64255[116:MRR:214.0,64254.0] || -> until2p7(s19)* node4(s18). % 76.04/76.26 64256[117:Spt:64255.0] || -> until2p7(s19)*. % 76.04/76.26 64257[117:MRR:215.0,64256.0] || -> until2p7(s20)* node4(s19). % 76.04/76.26 64258[118:Spt:64257.0] || -> until2p7(s20)*. % 76.04/76.26 64259[118:MRR:216.0,64258.0] || -> until2p7(s21)* node4(s20). % 76.04/76.26 64260[119:Spt:64259.0] || -> until2p7(s21)*. % 76.04/76.26 64261[119:MRR:217.0,64260.0] || -> until2p7(s22)* node4(s21). % 76.04/76.26 64262[120:Spt:64261.0] || -> until2p7(s22)*. % 76.04/76.26 64263[120:MRR:218.0,64262.0] || -> until2p7(s23)* node4(s22). % 76.04/76.26 64264[121:Spt:64263.0] || -> until2p7(s23)*. % 76.04/76.26 64265[121:MRR:219.0,64264.0] || -> until2p7(s24)* node4(s23). % 76.04/76.26 64266[122:Spt:64265.0] || -> until2p7(s24)*. % 76.04/76.26 64267[122:MRR:220.0,64266.0] || -> until2p7(s25)* node4(s24). % 76.04/76.26 64268[123:Spt:64267.0] || -> until2p7(s25)*. % 76.04/76.26 64269[123:MRR:221.0,64268.0] || -> until2p7(s26)* node4(s25). % 76.04/76.26 64270[124:Spt:64269.0] || -> until2p7(s26)*. % 76.04/76.26 64271[124:MRR:222.0,64270.0] || -> until2p7(s27)* node4(s26). % 76.04/76.26 64272[125:Spt:64271.0] || -> until2p7(s27)*. % 76.04/76.26 64273[125:MRR:223.0,64272.0] || -> until2p7(s28)* node4(s27). % 76.04/76.26 64274[126:Spt:64273.0] || -> until2p7(s28)*. % 76.04/76.26 64275[126:MRR:224.0,64274.0] || -> until2p7(s29)* node4(s28). % 76.04/76.26 64276[127:Spt:64275.0] || -> until2p7(s29)*. % 76.04/76.26 64277[127:MRR:225.0,64276.0] || -> until2p7(s30)* node4(s29). % 76.04/76.26 64278[128:Spt:64277.0] || -> until2p7(s30)*. % 76.04/76.26 64279[128:MRR:226.0,64278.0] || -> until2p7(s31)* node4(s30). % 76.04/76.26 64280[129:Spt:64279.0] || -> until2p7(s31)*. % 76.04/76.26 64281[129:MRR:227.0,64280.0] || -> until2p7(s32)* node4(s31). % 76.04/76.26 64282[130:Spt:64281.0] || -> until2p7(s32)*. % 76.04/76.26 64283[130:MRR:228.0,64282.0] || -> until2p7(s33)* node4(s32). % 76.04/76.26 64284[131:Spt:64283.0] || -> until2p7(s33)*. % 76.04/76.26 64285[131:MRR:229.0,64284.0] || -> until2p7(s34)* node4(s33). % 76.04/76.26 64286[132:Spt:64285.0] || -> until2p7(s34)*. % 76.04/76.26 64287[132:MRR:230.0,64286.0] || -> until2p7(s35)* node4(s34). % 76.04/76.26 64288[133:Spt:64287.0] || -> until2p7(s35)*. % 76.04/76.26 64289[133:MRR:231.0,64288.0] || -> until2p7(s36)* node4(s35). % 76.04/76.26 64290[134:Spt:64289.0] || -> until2p7(s36)*. % 76.04/76.26 64291[134:MRR:232.0,64290.0] || -> until2p7(s37)* node4(s36). % 76.04/76.26 64292[135:Spt:64291.0] || -> until2p7(s37)*. % 76.04/76.26 64293[135:MRR:235.0,64292.0] || -> until2p7(s38)* node4(s37). % 76.04/76.26 64294[136:Spt:64293.0] || -> until2p7(s38)*. % 76.04/76.26 64295[136:MRR:236.0,64294.0] || -> until2p7(s39)* node4(s38). % 76.04/76.26 64296[137:Spt:64295.0] || -> until2p7(s39)*. % 76.04/76.26 64297[137:MRR:237.0,64296.0] || -> until2p7(s40)* node4(s39). % 76.04/76.26 64298[138:Spt:64297.0] || -> until2p7(s40)*. % 76.04/76.26 64299[138:MRR:238.0,64298.0] || -> until2p7(s41)* node4(s40). % 76.04/76.26 64300[139:Spt:64299.0] || -> until2p7(s41)*. % 76.04/76.26 64301[139:MRR:239.0,64300.0] || -> until2p7(s42)* node4(s41). % 76.04/76.26 64302[140:Spt:64301.0] || -> until2p7(s42)*. % 76.04/76.26 64303[140:MRR:240.0,64302.0] || -> until2p7(s43)* node4(s42). % 76.04/76.26 64304[141:Spt:64303.0] || -> until2p7(s43)*. % 76.04/76.26 64305[141:MRR:241.0,64304.0] || -> until2p7(s44)* node4(s43). % 76.04/76.26 64306[142:Spt:64305.0] || -> until2p7(s44)*. % 76.04/76.26 64307[142:MRR:539.0,64306.0] || -> until2p7(s45)* node4(s44). % 76.04/76.26 64308[143:Spt:64307.0] || -> until2p7(s45)*. % 76.04/76.26 64309[143:MRR:544.0,64308.0] || -> until2p7(s46)* node4(s45). % 76.04/76.26 64310[144:Spt:64309.0] || -> until2p7(s46)*. % 76.04/76.26 64311[144:MRR:549.0,64310.0] || -> until2p7(s47)* node4(s46). % 76.04/76.26 64312[145:Spt:64311.0] || -> until2p7(s47)*. % 76.04/76.26 64313[145:MRR:554.0,64312.0] || -> until2p7(s48)* node4(s47). % 76.04/76.26 64314[146:Spt:64313.0] || -> until2p7(s48)*. % 76.04/76.26 64315[146:MRR:559.0,64314.0] || -> until2p7(s49)* node4(s48). % 76.04/76.26 64316[147:Spt:64315.0] || -> until2p7(s49)*. % 76.04/76.26 64317[147:MRR:194.0,64316.0] || -> node4(s49)*. % 76.04/76.26 64318[147:MRR:64219.0,64317.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.26 64322[147:Res:53.1,64318.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.26 64324[147:MRR:64322.0,64226.0] || -> . % 76.04/76.26 64325[147:Spt:64324.0,64315.0,64316.0] || until2p7(s49)*+ -> . % 76.04/76.26 64326[147:Spt:64324.0,64315.1] || -> node4(s48)*. % 76.04/76.26 64327[147:MRR:64231.0,64326.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.26 64330[147:Res:53.1,64327.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.26 64332[147:MRR:64330.0,64039.0] || -> . % 76.04/76.26 64333[146:Spt:64332.0,64313.0,64314.0] || until2p7(s48)*+ -> . % 76.04/76.26 64334[146:Spt:64332.0,64313.1] || -> node4(s47)*. % 76.04/76.26 64335[146:MRR:64042.0,64334.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.26 64338[146:Res:53.1,64335.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.26 64341[146:Res:64338.0,61.1] always3(s47) || -> . % 76.04/76.26 64342[146:SSi:64341.0,736.0,64033.0,64045.0,64312.0,64334.0] || -> . % 76.04/76.26 64343[145:Spt:64342.0,64311.0,64312.0] || until2p7(s47)*+ -> . % 76.04/76.26 64344[145:Spt:64342.0,64311.1] || -> node4(s46)*. % 76.04/76.26 64346[145:MRR:780.0,64344.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.26 64363[145:Res:53.1,64346.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.26 64365[145:MRR:64363.0,64019.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.26 64367[145:Res:64365.0,61.1] always3(s47) || -> . % 76.04/76.26 64368[145:SSi:64367.0,736.0,64033.0,64045.0] || -> . % 76.04/76.26 64369[144:Spt:64368.0,64309.0,64310.0] || until2p7(s46)*+ -> . % 76.04/76.26 64370[144:Spt:64368.0,64309.1] || -> node4(s45)*. % 76.04/76.26 64371[144:MRR:64022.0,64370.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.26 64374[144:Res:53.1,64371.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.26 64377[144:Res:64374.0,61.1] always3(s45) || -> . % 76.04/76.26 64378[144:SSi:64377.0,734.0,64013.0,64025.0,64308.0,64370.0] || -> . % 76.04/76.26 64379[143:Spt:64378.0,64307.0,64308.0] || until2p7(s45)*+ -> . % 76.04/76.26 64380[143:Spt:64378.0,64307.1] || -> node4(s44)*. % 76.04/76.26 64382[143:MRR:786.0,64380.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.26 64394[143:Res:53.1,64382.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.26 64396[143:MRR:64394.0,63999.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.26 64401[143:Res:64396.0,61.1] always3(s45) || -> . % 76.04/76.26 64402[143:SSi:64401.0,734.0,64013.0,64025.0] || -> . % 76.04/76.26 64403[142:Spt:64402.0,64305.0,64306.0] || until2p7(s44)*+ -> . % 76.04/76.26 64404[142:Spt:64402.0,64305.1] || -> node4(s43)*. % 76.04/76.26 64405[142:MRR:64002.0,64404.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.26 64408[142:Res:53.1,64405.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.26 64412[142:Res:64408.0,61.1] always3(s43) || -> . % 76.04/76.26 64413[142:SSi:64412.0,732.0,63993.0,64008.0,64304.0,64404.0] || -> . % 76.04/76.26 64414[141:Spt:64413.0,64303.0,64304.0] || until2p7(s43)*+ -> . % 76.04/76.26 64415[141:Spt:64413.0,64303.1] || -> node4(s42)*. % 76.04/76.26 64417[141:MRR:792.0,64415.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.26 64428[141:Res:53.1,64417.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.26 64430[141:MRR:64428.0,63976.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.26 64432[141:Res:64430.0,61.1] always3(s43) || -> . % 76.04/76.26 64433[141:SSi:64432.0,732.0,63993.0,64008.0] || -> . % 76.04/76.26 64434[140:Spt:64433.0,64301.0,64302.0] || until2p7(s42)*+ -> . % 76.04/76.26 64435[140:Spt:64433.0,64301.1] || -> node4(s41)*. % 76.04/76.26 64436[140:MRR:63979.0,64435.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.26 64440[140:Res:53.1,64436.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.26 64443[140:Res:64440.0,61.1] always3(s41) || -> . % 76.04/76.26 64444[140:SSi:64443.0,730.0,63970.0,63982.0,64300.0,64435.0] || -> . % 76.04/76.26 64445[139:Spt:64444.0,64299.0,64300.0] || until2p7(s41)*+ -> . % 76.04/76.26 64446[139:Spt:64444.0,64299.1] || -> node4(s40)*. % 76.04/76.26 64448[139:MRR:798.0,64446.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.26 64459[139:Res:53.1,64448.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.26 64461[139:MRR:64459.0,63956.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.26 64463[139:Res:64461.0,61.1] always3(s41) || -> . % 76.04/76.26 64464[139:SSi:64463.0,730.0,63970.0,63982.0] || -> . % 76.04/76.26 64465[138:Spt:64464.0,64297.0,64298.0] || until2p7(s40)*+ -> . % 76.04/76.26 64466[138:Spt:64464.0,64297.1] || -> node4(s39)*. % 76.04/76.26 64467[138:MRR:63959.0,64466.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.26 64470[138:Res:53.1,64467.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.26 64473[138:Res:64470.0,61.1] always3(s39) || -> . % 76.04/76.26 64474[138:SSi:64473.0,728.0,63950.0,63962.0,64296.0,64466.0] || -> . % 76.04/76.26 64475[137:Spt:64474.0,64295.0,64296.0] || until2p7(s39)*+ -> . % 76.04/76.26 64476[137:Spt:64474.0,64295.1] || -> node4(s38)*. % 76.04/76.26 64478[137:MRR:804.0,64476.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.26 64490[137:Res:53.1,64478.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.26 64492[137:MRR:64490.0,63936.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.26 64494[137:Res:64492.0,61.1] always3(s39) || -> . % 76.04/76.26 64495[137:SSi:64494.0,728.0,63950.0,63962.0] || -> . % 76.04/76.26 64496[136:Spt:64495.0,64293.0,64294.0] || until2p7(s38)*+ -> . % 76.04/76.26 64497[136:Spt:64495.0,64293.1] || -> node4(s37)*. % 76.04/76.26 64498[136:MRR:63939.0,64497.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.26 64501[136:Res:53.1,64498.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.26 64504[136:Res:64501.0,61.1] always3(s37) || -> . % 76.04/76.26 64505[136:SSi:64504.0,726.0,63930.0,63945.0,64292.0,64497.0] || -> . % 76.04/76.26 64506[135:Spt:64505.0,64291.0,64292.0] || until2p7(s37)*+ -> . % 76.04/76.26 64507[135:Spt:64505.0,64291.1] || -> node4(s36)*. % 76.04/76.26 64509[135:MRR:810.0,64507.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.26 64521[135:Res:53.1,64509.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.26 64523[135:MRR:64521.0,63913.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.26 64528[135:Res:64523.0,61.1] always3(s37) || -> . % 76.04/76.26 64529[135:SSi:64528.0,726.0,63930.0,63945.0] || -> . % 76.04/76.26 64530[134:Spt:64529.0,64289.0,64290.0] || until2p7(s36)*+ -> . % 76.04/76.26 64531[134:Spt:64529.0,64289.1] || -> node4(s35)*. % 76.04/76.26 64532[134:MRR:63916.0,64531.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.26 64535[134:Res:53.1,64532.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.26 64539[134:Res:64535.0,61.1] always3(s35) || -> . % 76.04/76.26 64540[134:SSi:64539.0,724.0,63907.0,63919.0,64288.0,64531.0] || -> . % 76.04/76.26 64541[133:Spt:64540.0,64287.0,64288.0] || until2p7(s35)*+ -> . % 76.04/76.26 64542[133:Spt:64540.0,64287.1] || -> node4(s34)*. % 76.04/76.26 64544[133:MRR:816.0,64542.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.26 64555[133:Res:53.1,64544.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.26 64557[133:MRR:64555.0,63893.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.26 64559[133:Res:64557.0,61.1] always3(s35) || -> . % 76.04/76.26 64560[133:SSi:64559.0,724.0,63907.0,63919.0] || -> . % 76.04/76.26 64561[132:Spt:64560.0,64285.0,64286.0] || until2p7(s34)*+ -> . % 76.04/76.26 64562[132:Spt:64560.0,64285.1] || -> node4(s33)*. % 76.04/76.26 64563[132:MRR:63896.0,64562.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.26 64567[132:Res:53.1,64563.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.26 64570[132:Res:64567.0,61.1] always3(s33) || -> . % 76.04/76.26 64571[132:SSi:64570.0,722.0,63884.0,63899.0,64284.0,64562.0] || -> . % 76.04/76.26 64572[131:Spt:64571.0,64283.0,64284.0] || until2p7(s33)*+ -> . % 76.04/76.26 64573[131:Spt:64571.0,64283.1] || -> node4(s32)*. % 76.04/76.26 64575[131:MRR:822.0,64573.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.26 64586[131:Res:53.1,64575.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.26 64588[132:Spt:64586.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.26 64590[132:Res:64588.0,61.1] always3(s32) || -> . % 76.04/76.26 64591[132:SSi:64590.0,721.0,63881.0,63883.0,64282.0,64573.0] || -> . % 76.04/76.26 64592[132:Spt:64591.0,64586.0,64588.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.26 64593[132:Spt:64591.0,64586.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.26 64597[132:Res:64593.0,61.1] always3(s33) || -> . % 76.04/76.26 64598[132:SSi:64597.0,722.0,63884.0,63899.0] || -> . % 76.04/76.26 64599[130:Spt:64598.0,64281.0,64282.0] || until2p7(s32)*+ -> . % 76.04/76.26 64600[130:Spt:64598.0,64281.1] || -> node4(s31)*. % 76.04/76.26 64602[130:MRR:825.0,64600.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.26 64612[130:Res:53.1,64602.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.26 64614[131:Spt:64612.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 64616[131:Res:64614.0,61.1] always3(s31) || -> . % 76.04/76.26 64617[131:SSi:64616.0,720.0,63875.0,63880.0,64280.0,64600.0] || -> . % 76.04/76.26 64618[131:Spt:64617.0,64612.0,64614.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.26 64619[131:Spt:64617.0,64612.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.26 64623[131:Res:64619.0,61.1] always3(s32) || -> . % 76.04/76.26 64624[131:SSi:64623.0,721.0,63881.0,63883.0] || -> . % 76.04/76.26 64625[129:Spt:64624.0,64279.0,64280.0] || until2p7(s31)*+ -> . % 76.04/76.26 64626[129:Spt:64624.0,64279.1] || -> node4(s30)*. % 76.04/76.26 64628[129:MRR:828.0,64626.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.26 64631[129:Res:53.1,64628.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.26 64633[130:Spt:64631.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 64635[130:Res:64633.0,61.1] always3(s30) || -> . % 76.04/76.26 64636[130:SSi:64635.0,719.0,63872.0,63874.0,64278.0,64626.0] || -> . % 76.04/76.26 64637[130:Spt:64636.0,64631.0,64633.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.26 64638[130:Spt:64636.0,64631.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 64642[130:Res:64638.0,61.1] always3(s31) || -> . % 76.04/76.26 64643[130:SSi:64642.0,720.0,63875.0,63880.0] || -> . % 76.04/76.26 64644[128:Spt:64643.0,64277.0,64278.0] || until2p7(s30)*+ -> . % 76.04/76.26 64645[128:Spt:64643.0,64277.1] || -> node4(s29)*. % 76.04/76.26 64647[128:MRR:831.0,64645.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.26 64650[128:Res:53.1,64647.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.26 64652[129:Spt:64650.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 64654[129:Res:64652.0,61.1] always3(s29) || -> . % 76.04/76.26 64655[129:SSi:64654.0,718.0,63866.0,63871.0,64276.0,64645.0] || -> . % 76.04/76.26 64656[129:Spt:64655.0,64650.0,64652.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.26 64657[129:Spt:64655.0,64650.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 64661[129:Res:64657.0,61.1] always3(s30) || -> . % 76.04/76.26 64662[129:SSi:64661.0,719.0,63872.0,63874.0] || -> . % 76.04/76.26 64663[127:Spt:64662.0,64275.0,64276.0] || until2p7(s29)*+ -> . % 76.04/76.26 64664[127:Spt:64662.0,64275.1] || -> node4(s28)*. % 76.04/76.26 64666[127:MRR:834.0,64664.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.26 64669[127:Res:53.1,64666.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.26 64674[128:Spt:64669.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 64676[128:Res:64674.0,61.1] always3(s28) || -> . % 76.04/76.26 64677[128:SSi:64676.0,717.0,63863.0,63865.0,64274.0,64664.0] || -> . % 76.04/76.26 64678[128:Spt:64677.0,64669.0,64674.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.26 64679[128:Spt:64677.0,64669.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 64683[128:Res:64679.0,61.1] always3(s29) || -> . % 76.04/76.26 64684[128:SSi:64683.0,718.0,63866.0,63871.0] || -> . % 76.04/76.26 64685[126:Spt:64684.0,64273.0,64274.0] || until2p7(s28)*+ -> . % 76.04/76.26 64686[126:Spt:64684.0,64273.1] || -> node4(s27)*. % 76.04/76.26 64688[126:MRR:837.0,64686.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.26 64691[126:Res:53.1,64688.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.26 64693[127:Spt:64691.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 64695[127:Res:64693.0,61.1] always3(s27) || -> . % 76.04/76.26 64696[127:SSi:64695.0,716.0,63857.0,63862.0,64272.0,64686.0] || -> . % 76.04/76.26 64697[127:Spt:64696.0,64691.0,64693.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.26 64698[127:Spt:64696.0,64691.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 64702[127:Res:64698.0,61.1] always3(s28) || -> . % 76.04/76.26 64703[127:SSi:64702.0,717.0,63863.0,63865.0] || -> . % 76.04/76.26 64704[125:Spt:64703.0,64271.0,64272.0] || until2p7(s27)*+ -> . % 76.04/76.26 64705[125:Spt:64703.0,64271.1] || -> node4(s26)*. % 76.04/76.26 64707[125:MRR:840.0,64705.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.26 64710[125:Res:53.1,64707.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.26 64712[126:Spt:64710.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 64714[126:Res:64712.0,61.1] always3(s26) || -> . % 76.04/76.26 64715[126:SSi:64714.0,715.0,63854.0,63856.0,64270.0,64705.0] || -> . % 76.04/76.26 64716[126:Spt:64715.0,64710.0,64712.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.26 64717[126:Spt:64715.0,64710.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 64721[126:Res:64717.0,61.1] always3(s27) || -> . % 76.04/76.26 64722[126:SSi:64721.0,716.0,63857.0,63862.0] || -> . % 76.04/76.26 64723[124:Spt:64722.0,64269.0,64270.0] || until2p7(s26)*+ -> . % 76.04/76.26 64724[124:Spt:64722.0,64269.1] || -> node4(s25)*. % 76.04/76.26 64726[124:MRR:843.0,64724.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.26 64729[124:Res:53.1,64726.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.26 64731[125:Spt:64729.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 64733[125:Res:64731.0,61.1] always3(s25) || -> . % 76.04/76.26 64734[125:SSi:64733.0,714.0,63848.0,63853.0,64268.0,64724.0] || -> . % 76.04/76.26 64735[125:Spt:64734.0,64729.0,64731.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.26 64736[125:Spt:64734.0,64729.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 64740[125:Res:64736.0,61.1] always3(s26) || -> . % 76.04/76.26 64741[125:SSi:64740.0,715.0,63854.0,63856.0] || -> . % 76.04/76.26 64742[123:Spt:64741.0,64267.0,64268.0] || until2p7(s25)*+ -> . % 76.04/76.26 64743[123:Spt:64741.0,64267.1] || -> node4(s24)*. % 76.04/76.26 64745[123:MRR:846.0,64743.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.26 64748[123:Res:53.1,64745.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.26 64753[124:Spt:64748.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 64755[124:Res:64753.0,61.1] always3(s24) || -> . % 76.04/76.26 64756[124:SSi:64755.0,713.0,63845.0,63847.0,64266.0,64743.0] || -> . % 76.04/76.26 64757[124:Spt:64756.0,64748.0,64753.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.26 64758[124:Spt:64756.0,64748.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 64762[124:Res:64758.0,61.1] always3(s25) || -> . % 76.04/76.26 64763[124:SSi:64762.0,714.0,63848.0,63853.0] || -> . % 76.04/76.26 64764[122:Spt:64763.0,64265.0,64266.0] || until2p7(s24)*+ -> . % 76.04/76.26 64765[122:Spt:64763.0,64265.1] || -> node4(s23)*. % 76.04/76.26 64767[122:MRR:849.0,64765.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.26 64770[122:Res:53.1,64767.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.26 64772[123:Spt:64770.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 64774[123:Res:64772.0,61.1] always3(s23) || -> . % 76.04/76.26 64775[123:SSi:64774.0,712.0,63839.0,63844.0,64264.0,64765.0] || -> . % 76.04/76.26 64776[123:Spt:64775.0,64770.0,64772.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.26 64777[123:Spt:64775.0,64770.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 64781[123:Res:64777.0,61.1] always3(s24) || -> . % 76.04/76.26 64782[123:SSi:64781.0,713.0,63845.0,63847.0] || -> . % 76.04/76.26 64783[121:Spt:64782.0,64263.0,64264.0] || until2p7(s23)*+ -> . % 76.04/76.26 64784[121:Spt:64782.0,64263.1] || -> node4(s22)*. % 76.04/76.26 64786[121:MRR:852.0,64784.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.26 64789[121:Res:53.1,64786.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.26 64791[122:Spt:64789.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 64793[122:Res:64791.0,61.1] always3(s22) || -> . % 76.04/76.26 64794[122:SSi:64793.0,711.0,63836.0,63838.0,64262.0,64784.0] || -> . % 76.04/76.26 64795[122:Spt:64794.0,64789.0,64791.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.26 64796[122:Spt:64794.0,64789.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 64800[122:Res:64796.0,61.1] always3(s23) || -> . % 76.04/76.26 64801[122:SSi:64800.0,712.0,63839.0,63844.0] || -> . % 76.04/76.26 64802[120:Spt:64801.0,64261.0,64262.0] || until2p7(s22)*+ -> . % 76.04/76.26 64803[120:Spt:64801.0,64261.1] || -> node4(s21)*. % 76.04/76.26 64805[120:MRR:855.0,64803.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.26 64808[120:Res:53.1,64805.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.26 64810[121:Spt:64808.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 64812[121:Res:64810.0,61.1] always3(s21) || -> . % 76.04/76.26 64813[121:SSi:64812.0,710.0,63830.0,63835.0,64260.0,64803.0] || -> . % 76.04/76.26 64814[121:Spt:64813.0,64808.0,64810.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.26 64815[121:Spt:64813.0,64808.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 64819[121:Res:64815.0,61.1] always3(s22) || -> . % 76.04/76.26 64820[121:SSi:64819.0,711.0,63836.0,63838.0] || -> . % 76.04/76.26 64821[119:Spt:64820.0,64259.0,64260.0] || until2p7(s21)*+ -> . % 76.04/76.26 64822[119:Spt:64820.0,64259.1] || -> node4(s20)*. % 76.04/76.26 64824[119:MRR:858.0,64822.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.26 64827[119:Res:53.1,64824.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.26 64832[120:Spt:64827.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 64834[120:Res:64832.0,61.1] always3(s20) || -> . % 76.04/76.26 64835[120:SSi:64834.0,709.0,63827.0,63829.0,64258.0,64822.0] || -> . % 76.04/76.26 64836[120:Spt:64835.0,64827.0,64832.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.26 64837[120:Spt:64835.0,64827.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 64841[120:Res:64837.0,61.1] always3(s21) || -> . % 76.04/76.26 64842[120:SSi:64841.0,710.0,63830.0,63835.0] || -> . % 76.04/76.26 64843[118:Spt:64842.0,64257.0,64258.0] || until2p7(s20)*+ -> . % 76.04/76.26 64844[118:Spt:64842.0,64257.1] || -> node4(s19)*. % 76.04/76.26 64846[118:MRR:861.0,64844.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.26 64849[118:Res:53.1,64846.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.26 64851[119:Spt:64849.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 64853[119:Res:64851.0,61.1] always3(s19) || -> . % 76.04/76.26 64854[119:SSi:64853.0,708.0,63821.0,63826.0,64256.0,64844.0] || -> . % 76.04/76.26 64855[119:Spt:64854.0,64849.0,64851.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.26 64856[119:Spt:64854.0,64849.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 64860[119:Res:64856.0,61.1] always3(s20) || -> . % 76.04/76.26 64861[119:SSi:64860.0,709.0,63827.0,63829.0] || -> . % 76.04/76.26 64862[117:Spt:64861.0,64255.0,64256.0] || until2p7(s19)*+ -> . % 76.04/76.26 64863[117:Spt:64861.0,64255.1] || -> node4(s18)*. % 76.04/76.26 64865[117:MRR:864.0,64863.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.26 64868[117:Res:53.1,64865.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.26 64870[118:Spt:64868.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 64872[118:Res:64870.0,61.1] always3(s18) || -> . % 76.04/76.26 64873[118:SSi:64872.0,707.0,63818.0,63820.0,64254.0,64863.0] || -> . % 76.04/76.26 64874[118:Spt:64873.0,64868.0,64870.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.26 64875[118:Spt:64873.0,64868.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 64879[118:Res:64875.0,61.1] always3(s19) || -> . % 76.04/76.26 64880[118:SSi:64879.0,708.0,63821.0,63826.0] || -> . % 76.04/76.26 64881[116:Spt:64880.0,64253.0,64254.0] || until2p7(s18)*+ -> . % 76.04/76.26 64882[116:Spt:64880.0,64253.1] || -> node4(s17)*. % 76.04/76.26 64884[116:MRR:867.0,64882.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.26 64887[116:Res:53.1,64884.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.26 64889[117:Spt:64887.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 64891[117:Res:64889.0,61.1] always3(s17) || -> . % 76.04/76.26 64892[117:SSi:64891.0,706.0,63812.0,63817.0,64252.0,64882.0] || -> . % 76.04/76.26 64893[117:Spt:64892.0,64887.0,64889.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.26 64894[117:Spt:64892.0,64887.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 64898[117:Res:64894.0,61.1] always3(s18) || -> . % 76.04/76.26 64899[117:SSi:64898.0,707.0,63818.0,63820.0] || -> . % 76.04/76.26 64900[115:Spt:64899.0,64251.0,64252.0] || until2p7(s17)*+ -> . % 76.04/76.26 64901[115:Spt:64899.0,64251.1] || -> node4(s16)*. % 76.04/76.26 64903[115:MRR:870.0,64901.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.26 64906[115:Res:53.1,64903.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.26 64911[116:Spt:64906.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 64913[116:Res:64911.0,61.1] always3(s16) || -> . % 76.04/76.26 64914[116:SSi:64913.0,705.0,63809.0,63811.0,64250.0,64901.0] || -> . % 76.04/76.26 64915[116:Spt:64914.0,64906.0,64911.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.26 64916[116:Spt:64914.0,64906.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 64920[116:Res:64916.0,61.1] always3(s17) || -> . % 76.04/76.26 64921[116:SSi:64920.0,706.0,63812.0,63817.0] || -> . % 76.04/76.26 64922[114:Spt:64921.0,64249.0,64250.0] || until2p7(s16)*+ -> . % 76.04/76.26 64923[114:Spt:64921.0,64249.1] || -> node4(s15)*. % 76.04/76.26 64925[114:MRR:873.0,64923.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.26 64928[114:Res:53.1,64925.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.26 64930[115:Spt:64928.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 64932[115:Res:64930.0,61.1] always3(s15) || -> . % 76.04/76.26 64933[115:SSi:64932.0,704.0,63803.0,63808.0,64248.0,64923.0] || -> . % 76.04/76.26 64934[115:Spt:64933.0,64928.0,64930.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.26 64935[115:Spt:64933.0,64928.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 64939[115:Res:64935.0,61.1] always3(s16) || -> . % 76.04/76.26 64940[115:SSi:64939.0,705.0,63809.0,63811.0] || -> . % 76.04/76.26 64941[113:Spt:64940.0,64247.0,64248.0] || until2p7(s15)*+ -> . % 76.04/76.26 64942[113:Spt:64940.0,64247.1] || -> node4(s14)*. % 76.04/76.26 64944[113:MRR:876.0,64942.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.26 64947[113:Res:53.1,64944.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.26 64949[114:Spt:64947.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 64951[114:Res:64949.0,61.1] always3(s14) || -> . % 76.04/76.26 64952[114:SSi:64951.0,703.0,63800.0,63802.0,64246.0,64942.0] || -> . % 76.04/76.26 64953[114:Spt:64952.0,64947.0,64949.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.26 64954[114:Spt:64952.0,64947.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 64958[114:Res:64954.0,61.1] always3(s15) || -> . % 76.04/76.26 64959[114:SSi:64958.0,704.0,63803.0,63808.0] || -> . % 76.04/76.26 64960[112:Spt:64959.0,64245.0,64246.0] || until2p7(s14)*+ -> . % 76.04/76.26 64961[112:Spt:64959.0,64245.1] || -> node4(s13)*. % 76.04/76.26 64963[112:MRR:879.0,64961.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.26 64966[112:Res:53.1,64963.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.26 64968[113:Spt:64966.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 64970[113:Res:64968.0,61.1] always3(s13) || -> . % 76.04/76.26 64971[113:SSi:64970.0,702.0,63794.0,63799.0,64244.0,64961.0] || -> . % 76.04/76.26 64972[113:Spt:64971.0,64966.0,64968.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.26 64973[113:Spt:64971.0,64966.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 64977[113:Res:64973.0,61.1] always3(s14) || -> . % 76.04/76.26 64978[113:SSi:64977.0,703.0,63800.0,63802.0] || -> . % 76.04/76.26 64979[111:Spt:64978.0,64243.0,64244.0] || until2p7(s13)*+ -> . % 76.04/76.26 64980[111:Spt:64978.0,64243.1] || -> node4(s12)*. % 76.04/76.26 64982[111:MRR:882.0,64980.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.26 64985[111:Res:53.1,64982.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.26 64990[112:Spt:64985.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 64992[112:Res:64990.0,61.1] always3(s12) || -> . % 76.04/76.26 64993[112:SSi:64992.0,701.0,63791.0,63793.0,64242.0,64980.0] || -> . % 76.04/76.26 64994[112:Spt:64993.0,64985.0,64990.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.26 64995[112:Spt:64993.0,64985.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 64999[112:Res:64995.0,61.1] always3(s13) || -> . % 76.04/76.26 65000[112:SSi:64999.0,702.0,63794.0,63799.0] || -> . % 76.04/76.26 65001[110:Spt:65000.0,64241.0,64242.0] || until2p7(s12)*+ -> . % 76.04/76.26 65002[110:Spt:65000.0,64241.1] || -> node4(s11)*. % 76.04/76.26 65004[110:MRR:885.0,65002.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.26 65007[110:Res:53.1,65004.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.26 65009[111:Spt:65007.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 65011[111:Res:65009.0,61.1] always3(s11) || -> . % 76.04/76.26 65012[111:SSi:65011.0,700.0,63785.0,63790.0,64240.0,65002.0] || -> . % 76.04/76.26 65013[111:Spt:65012.0,65007.0,65009.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.26 65014[111:Spt:65012.0,65007.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 65018[111:Res:65014.0,61.1] always3(s12) || -> . % 76.04/76.26 65019[111:SSi:65018.0,701.0,63791.0,63793.0] || -> . % 76.04/76.26 65020[109:Spt:65019.0,64239.0,64240.0] || until2p7(s11)*+ -> . % 76.04/76.26 65021[109:Spt:65019.0,64239.1] || -> node4(s10)*. % 76.04/76.26 65023[109:MRR:888.0,65021.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.26 65026[109:Res:53.1,65023.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.26 65028[110:Spt:65026.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 65030[110:Res:65028.0,61.1] always3(s10) || -> . % 76.04/76.26 65031[110:SSi:65030.0,699.0,63782.0,63784.0,64238.0,65021.0] || -> . % 76.04/76.26 65032[110:Spt:65031.0,65026.0,65028.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.26 65033[110:Spt:65031.0,65026.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 65037[110:Res:65033.0,61.1] always3(s11) || -> . % 76.04/76.26 65038[110:SSi:65037.0,700.0,63785.0,63790.0] || -> . % 76.04/76.26 65039[108:Spt:65038.0,64237.0,64238.0] || until2p7(s10)*+ -> . % 76.04/76.26 65040[108:Spt:65038.0,64237.1] || -> node4(s9)*. % 76.04/76.26 65042[108:MRR:891.0,65040.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.26 65045[108:Res:53.1,65042.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.26 65047[109:Spt:65045.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 65049[109:Res:65047.0,61.1] always3(s9) || -> . % 76.04/76.26 65050[109:SSi:65049.0,698.0,63776.0,63781.0,64236.0,65040.0] || -> . % 76.04/76.26 65051[109:Spt:65050.0,65045.0,65047.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.26 65052[109:Spt:65050.0,65045.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 65056[109:Res:65052.0,61.1] always3(s10) || -> . % 76.04/76.26 65057[109:SSi:65056.0,699.0,63782.0,63784.0] || -> . % 76.04/76.26 65058[107:Spt:65057.0,64235.0,64236.0] || until2p7(s9)*+ -> . % 76.04/76.26 65059[107:Spt:65057.0,64235.1] || -> node4(s8)*. % 76.04/76.26 65061[107:MRR:894.0,65059.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.26 65064[107:Res:53.1,65061.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.26 65069[108:Spt:65064.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 65071[108:Res:65069.0,61.1] always3(s8) || -> . % 76.04/76.26 65072[108:SSi:65071.0,697.0,63773.0,63775.0,64234.0,65059.0] || -> . % 76.04/76.26 65073[108:Spt:65072.0,65064.0,65069.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.26 65074[108:Spt:65072.0,65064.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 65078[108:Res:65074.0,61.1] always3(s9) || -> . % 76.04/76.26 65079[108:SSi:65078.0,698.0,63776.0,63781.0] || -> . % 76.04/76.26 65080[106:Spt:65079.0,64233.0,64234.0] || until2p7(s8)*+ -> . % 76.04/76.26 65081[106:Spt:65079.0,64233.1] || -> node4(s7)*. % 76.04/76.26 65083[106:MRR:897.0,65081.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.26 65086[106:Res:53.1,65083.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.26 65088[107:Spt:65086.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 65090[107:Res:65088.0,61.1] always3(s7) || -> . % 76.04/76.26 65091[107:SSi:65090.0,696.0,63767.0,63772.0,64232.0,65081.0] || -> . % 76.04/76.26 65092[107:Spt:65091.0,65086.0,65088.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.26 65093[107:Spt:65091.0,65086.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 65097[107:Res:65093.0,61.1] always3(s8) || -> . % 76.04/76.26 65098[107:SSi:65097.0,697.0,63773.0,63775.0] || -> . % 76.04/76.26 65099[105:Spt:65098.0,64229.0,64232.0] || until2p7(s7)*+ -> . % 76.04/76.26 65100[105:Spt:65098.0,64229.1] || -> node4(s6)*. % 76.04/76.26 65102[105:MRR:900.0,65100.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.26 65105[105:Res:53.1,65102.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.26 65107[105:MRR:65105.0,64214.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 65109[105:Res:65107.0,61.1] always3(s7) || -> . % 76.04/76.26 65110[105:SSi:65109.0,696.0,63767.0,63772.0] || -> . % 76.04/76.26 65111[102:Spt:65110.0,64047.2,64055.0] || xuntil6(s48)*+ -> . % 76.04/76.26 65112[102:Spt:65110.0,64047.0,64047.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.26 65113[102:Res:53.1,65112.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.26 65115[102:MRR:65113.0,64039.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.26 65118[102:Res:65115.0,61.1] always3(s49) || -> . % 76.04/76.26 65119[102:SSi:65118.0,50.0,738.0] || -> . % 76.04/76.26 65120[101:Spt:65119.0,64043.1,64045.0] || xuntil6(s47)* -> . % 76.04/76.26 65121[101:Spt:65119.0,64043.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.26 65124[101:Res:65121.0,61.1] always3(s47) || -> . % 76.04/76.26 65125[101:SSi:65124.0,736.0,64033.0] || -> . % 76.04/76.26 65126[99:Spt:65125.0,64027.2,64032.0] || xuntil6(s46)*+ -> . % 76.04/76.26 65127[99:Spt:65125.0,64027.0,64027.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.26 65128[99:Res:53.1,65127.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.26 65130[99:MRR:65128.0,64019.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.26 65132[99:Res:65130.0,61.1] always3(s47) || -> . % 76.04/76.26 65133[99:SSi:65132.0,736.0] || -> . % 76.04/76.26 65134[98:Spt:65133.0,64023.1,64025.0] || xuntil6(s45)* -> . % 76.04/76.26 65135[98:Spt:65133.0,64023.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.26 65138[98:Res:65135.0,61.1] always3(s45) || -> . % 76.04/76.26 65139[98:SSi:65138.0,734.0,64013.0] || -> . % 76.04/76.26 65140[96:Spt:65139.0,64010.2,64012.0] || xuntil6(s44)*+ -> . % 76.04/76.26 65141[96:Spt:65139.0,64010.0,64010.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.26 65142[96:Res:53.1,65141.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.26 65144[96:MRR:65142.0,63999.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.26 65147[96:Res:65144.0,61.1] always3(s45) || -> . % 76.04/76.26 65148[96:SSi:65147.0,734.0] || -> . % 76.04/76.26 65149[95:Spt:65148.0,64003.1,64008.0] || xuntil6(s43)* -> . % 76.04/76.26 65150[95:Spt:65148.0,64003.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.26 65153[95:Res:65150.0,61.1] always3(s43) || -> . % 76.04/76.26 65154[95:SSi:65153.0,732.0,63993.0] || -> . % 76.04/76.26 65155[93:Spt:65154.0,63984.2,63992.0] || xuntil6(s42)*+ -> . % 76.04/76.26 65156[93:Spt:65154.0,63984.0,63984.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.26 65157[93:Res:53.1,65156.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.26 65159[93:MRR:65157.0,63976.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.26 65161[93:Res:65159.0,61.1] always3(s43) || -> . % 76.04/76.26 65162[93:SSi:65161.0,732.0] || -> . % 76.04/76.26 65163[92:Spt:65162.0,63980.1,63982.0] || xuntil6(s41)* -> . % 76.04/76.26 65164[92:Spt:65162.0,63980.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.26 65167[92:Res:65164.0,61.1] always3(s41) || -> . % 76.04/76.26 65168[92:SSi:65167.0,730.0,63970.0] || -> . % 76.04/76.26 65169[90:Spt:65168.0,63964.2,63969.0] || xuntil6(s40)*+ -> . % 76.04/76.26 65170[90:Spt:65168.0,63964.0,63964.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.26 65171[90:Res:53.1,65170.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.26 65173[90:MRR:65171.0,63956.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.26 65175[90:Res:65173.0,61.1] always3(s41) || -> . % 76.04/76.26 65176[90:SSi:65175.0,730.0] || -> . % 76.04/76.26 65177[89:Spt:65176.0,63960.1,63962.0] || xuntil6(s39)* -> . % 76.04/76.26 65178[89:Spt:65176.0,63960.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.26 65181[89:Res:65178.0,61.1] always3(s39) || -> . % 76.04/76.26 65182[89:SSi:65181.0,728.0,63950.0] || -> . % 76.04/76.26 65183[87:Spt:65182.0,63947.2,63949.0] || xuntil6(s38)*+ -> . % 76.04/76.26 65184[87:Spt:65182.0,63947.0,63947.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.26 65185[87:Res:53.1,65184.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.26 65187[87:MRR:65185.0,63936.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.26 65189[87:Res:65187.0,61.1] always3(s39) || -> . % 76.04/76.26 65190[87:SSi:65189.0,728.0] || -> . % 76.04/76.26 65191[86:Spt:65190.0,63940.1,63945.0] || xuntil6(s37)* -> . % 76.04/76.26 65192[86:Spt:65190.0,63940.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.26 65195[86:Res:65192.0,61.1] always3(s37) || -> . % 76.04/76.26 65196[86:SSi:65195.0,726.0,63930.0] || -> . % 76.04/76.26 65197[84:Spt:65196.0,63921.2,63929.0] || xuntil6(s36)*+ -> . % 76.04/76.26 65198[84:Spt:65196.0,63921.0,63921.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.26 65199[84:Res:53.1,65198.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.26 65201[84:MRR:65199.0,63913.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.26 65203[84:Res:65201.0,61.1] always3(s37) || -> . % 76.04/76.26 65204[84:SSi:65203.0,726.0] || -> . % 76.04/76.26 65205[83:Spt:65204.0,63917.1,63919.0] || xuntil6(s35)* -> . % 76.04/76.26 65206[83:Spt:65204.0,63917.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.26 65209[83:Res:65206.0,61.1] always3(s35) || -> . % 76.04/76.26 65210[83:SSi:65209.0,724.0,63907.0] || -> . % 76.04/76.26 65211[81:Spt:65210.0,63901.2,63906.0] || xuntil6(s34)*+ -> . % 76.04/76.26 65212[81:Spt:65210.0,63901.0,63901.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.26 65213[81:Res:53.1,65212.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.26 65215[81:MRR:65213.0,63893.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.26 65217[81:Res:65215.0,61.1] always3(s35) || -> . % 76.04/76.26 65218[81:SSi:65217.0,724.0] || -> . % 76.04/76.26 65219[80:Spt:65218.0,63897.1,63899.0] || xuntil6(s33)* -> . % 76.04/76.26 65220[80:Spt:65218.0,63897.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.26 65223[80:Res:65220.0,61.1] always3(s33) || -> . % 76.04/76.26 65224[80:SSi:65223.0,722.0,63884.0] || -> . % 76.04/76.26 65225[78:Spt:65224.0,63882.2,63883.0] || xuntil6(s32)*+ -> . % 76.04/76.26 65226[78:Spt:65224.0,63882.0,63882.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.26 65227[78:Res:53.1,65226.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.26 65229[79:Spt:65227.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.26 65231[79:Res:65229.0,61.1] always3(s33) || -> . % 76.04/76.26 65232[79:SSi:65231.0,722.0] || -> . % 76.04/76.26 65233[79:Spt:65232.0,65227.1,65229.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.26 65234[79:Spt:65232.0,65227.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.26 65237[79:Res:65234.0,61.1] always3(s32) || -> . % 76.04/76.26 65238[79:SSi:65237.0,721.0,63881.0] || -> . % 76.04/76.26 65239[77:Spt:65238.0,63876.2,63880.0] || xuntil6(s31)*+ -> . % 76.04/76.26 65240[77:Spt:65238.0,63876.0,63876.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.26 65241[77:Res:53.1,65240.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.26 65243[78:Spt:65241.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.26 65245[78:Res:65243.0,61.1] always3(s32) || -> . % 76.04/76.26 65246[78:SSi:65245.0,721.0] || -> . % 76.04/76.26 65247[78:Spt:65246.0,65241.1,65243.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.26 65248[78:Spt:65246.0,65241.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 65251[78:Res:65248.0,61.1] always3(s31) || -> . % 76.04/76.26 65252[78:SSi:65251.0,720.0,63875.0] || -> . % 76.04/76.26 65253[76:Spt:65252.0,63873.2,63874.0] || xuntil6(s30)*+ -> . % 76.04/76.26 65254[76:Spt:65252.0,63873.0,63873.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.26 65255[76:Res:53.1,65254.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.26 65257[77:Spt:65255.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 65259[77:Res:65257.0,61.1] always3(s31) || -> . % 76.04/76.26 65260[77:SSi:65259.0,720.0] || -> . % 76.04/76.26 65261[77:Spt:65260.0,65255.1,65257.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.26 65262[77:Spt:65260.0,65255.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 65265[77:Res:65262.0,61.1] always3(s30) || -> . % 76.04/76.26 65266[77:SSi:65265.0,719.0,63872.0] || -> . % 76.04/76.26 65267[75:Spt:65266.0,63867.2,63871.0] || xuntil6(s29)*+ -> . % 76.04/76.26 65268[75:Spt:65266.0,63867.0,63867.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.26 65269[75:Res:53.1,65268.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.26 65271[76:Spt:65269.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 65273[76:Res:65271.0,61.1] always3(s30) || -> . % 76.04/76.26 65274[76:SSi:65273.0,719.0] || -> . % 76.04/76.26 65275[76:Spt:65274.0,65269.1,65271.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.26 65276[76:Spt:65274.0,65269.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 65279[76:Res:65276.0,61.1] always3(s29) || -> . % 76.04/76.26 65280[76:SSi:65279.0,718.0,63866.0] || -> . % 76.04/76.26 65281[74:Spt:65280.0,63864.2,63865.0] || xuntil6(s28)*+ -> . % 76.04/76.26 65282[74:Spt:65280.0,63864.0,63864.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.26 65283[74:Res:53.1,65282.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.26 65285[75:Spt:65283.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 65287[75:Res:65285.0,61.1] always3(s29) || -> . % 76.04/76.26 65288[75:SSi:65287.0,718.0] || -> . % 76.04/76.26 65289[75:Spt:65288.0,65283.1,65285.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.26 65290[75:Spt:65288.0,65283.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 65293[75:Res:65290.0,61.1] always3(s28) || -> . % 76.04/76.26 65294[75:SSi:65293.0,717.0,63863.0] || -> . % 76.04/76.26 65295[73:Spt:65294.0,63858.2,63862.0] || xuntil6(s27)*+ -> . % 76.04/76.26 65296[73:Spt:65294.0,63858.0,63858.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.26 65297[73:Res:53.1,65296.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.26 65299[74:Spt:65297.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 65301[74:Res:65299.0,61.1] always3(s28) || -> . % 76.04/76.26 65302[74:SSi:65301.0,717.0] || -> . % 76.04/76.26 65303[74:Spt:65302.0,65297.1,65299.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.26 65304[74:Spt:65302.0,65297.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 65307[74:Res:65304.0,61.1] always3(s27) || -> . % 76.04/76.26 65308[74:SSi:65307.0,716.0,63857.0] || -> . % 76.04/76.26 65309[72:Spt:65308.0,63855.2,63856.0] || xuntil6(s26)*+ -> . % 76.04/76.26 65310[72:Spt:65308.0,63855.0,63855.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.26 65311[72:Res:53.1,65310.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.26 65313[73:Spt:65311.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 65315[73:Res:65313.0,61.1] always3(s27) || -> . % 76.04/76.26 65316[73:SSi:65315.0,716.0] || -> . % 76.04/76.26 65317[73:Spt:65316.0,65311.1,65313.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.26 65318[73:Spt:65316.0,65311.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 65321[73:Res:65318.0,61.1] always3(s26) || -> . % 76.04/76.26 65322[73:SSi:65321.0,715.0,63854.0] || -> . % 76.04/76.26 65323[71:Spt:65322.0,63849.2,63853.0] || xuntil6(s25)*+ -> . % 76.04/76.26 65324[71:Spt:65322.0,63849.0,63849.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.26 65325[71:Res:53.1,65324.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.26 65327[72:Spt:65325.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 65329[72:Res:65327.0,61.1] always3(s26) || -> . % 76.04/76.26 65330[72:SSi:65329.0,715.0] || -> . % 76.04/76.26 65331[72:Spt:65330.0,65325.1,65327.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.26 65332[72:Spt:65330.0,65325.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 65335[72:Res:65332.0,61.1] always3(s25) || -> . % 76.04/76.26 65336[72:SSi:65335.0,714.0,63848.0] || -> . % 76.04/76.26 65337[70:Spt:65336.0,63846.2,63847.0] || xuntil6(s24)*+ -> . % 76.04/76.26 65338[70:Spt:65336.0,63846.0,63846.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.26 65339[70:Res:53.1,65338.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.26 65341[71:Spt:65339.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 65343[71:Res:65341.0,61.1] always3(s25) || -> . % 76.04/76.26 65344[71:SSi:65343.0,714.0] || -> . % 76.04/76.26 65345[71:Spt:65344.0,65339.1,65341.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.26 65346[71:Spt:65344.0,65339.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 65349[71:Res:65346.0,61.1] always3(s24) || -> . % 76.04/76.26 65350[71:SSi:65349.0,713.0,63845.0] || -> . % 76.04/76.26 65351[69:Spt:65350.0,63840.2,63844.0] || xuntil6(s23)*+ -> . % 76.04/76.26 65352[69:Spt:65350.0,63840.0,63840.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.26 65353[69:Res:53.1,65352.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.26 65358[70:Spt:65353.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 65360[70:Res:65358.0,61.1] always3(s23) || -> . % 76.04/76.26 65361[70:SSi:65360.0,712.0,63839.0] || -> . % 76.04/76.26 65362[70:Spt:65361.0,65353.0,65358.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.26 65363[70:Spt:65361.0,65353.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 65367[70:Res:65363.0,61.1] always3(s24) || -> . % 76.04/76.26 65368[70:SSi:65367.0,713.0] || -> . % 76.04/76.26 65369[68:Spt:65368.0,63837.2,63838.0] || xuntil6(s22)*+ -> . % 76.04/76.26 65370[68:Spt:65368.0,63837.0,63837.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.26 65371[68:Res:53.1,65370.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.26 65373[69:Spt:65371.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 65375[69:Res:65373.0,61.1] always3(s23) || -> . % 76.04/76.26 65376[69:SSi:65375.0,712.0] || -> . % 76.04/76.26 65377[69:Spt:65376.0,65371.1,65373.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.26 65378[69:Spt:65376.0,65371.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 65381[69:Res:65378.0,61.1] always3(s22) || -> . % 76.04/76.26 65382[69:SSi:65381.0,711.0,63836.0] || -> . % 76.04/76.26 65383[67:Spt:65382.0,63831.2,63835.0] || xuntil6(s21)*+ -> . % 76.04/76.26 65384[67:Spt:65382.0,63831.0,63831.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.26 65385[67:Res:53.1,65384.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.26 65387[68:Spt:65385.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 65389[68:Res:65387.0,61.1] always3(s22) || -> . % 76.04/76.26 65390[68:SSi:65389.0,711.0] || -> . % 76.04/76.26 65391[68:Spt:65390.0,65385.1,65387.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.26 65392[68:Spt:65390.0,65385.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 65395[68:Res:65392.0,61.1] always3(s21) || -> . % 76.04/76.26 65396[68:SSi:65395.0,710.0,63830.0] || -> . % 76.04/76.26 65397[66:Spt:65396.0,63828.2,63829.0] || xuntil6(s20)*+ -> . % 76.04/76.26 65398[66:Spt:65396.0,63828.0,63828.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.26 65399[66:Res:53.1,65398.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.26 65404[67:Spt:65399.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 65406[67:Res:65404.0,61.1] always3(s20) || -> . % 76.04/76.26 65407[67:SSi:65406.0,709.0,63827.0] || -> . % 76.04/76.26 65408[67:Spt:65407.0,65399.0,65404.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.26 65409[67:Spt:65407.0,65399.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 65413[67:Res:65409.0,61.1] always3(s21) || -> . % 76.04/76.26 65414[67:SSi:65413.0,710.0] || -> . % 76.04/76.26 65415[65:Spt:65414.0,63822.2,63826.0] || xuntil6(s19)*+ -> . % 76.04/76.26 65416[65:Spt:65414.0,63822.0,63822.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.26 65417[65:Res:53.1,65416.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.26 65419[66:Spt:65417.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 65421[66:Res:65419.0,61.1] always3(s20) || -> . % 76.04/76.26 65422[66:SSi:65421.0,709.0] || -> . % 76.04/76.26 65423[66:Spt:65422.0,65417.1,65419.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.26 65424[66:Spt:65422.0,65417.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 65427[66:Res:65424.0,61.1] always3(s19) || -> . % 76.04/76.26 65428[66:SSi:65427.0,708.0,63821.0] || -> . % 76.04/76.26 65429[64:Spt:65428.0,63819.2,63820.0] || xuntil6(s18)*+ -> . % 76.04/76.26 65430[64:Spt:65428.0,63819.0,63819.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.26 65431[64:Res:53.1,65430.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.26 65433[65:Spt:65431.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 65435[65:Res:65433.0,61.1] always3(s19) || -> . % 76.04/76.26 65436[65:SSi:65435.0,708.0] || -> . % 76.04/76.26 65437[65:Spt:65436.0,65431.1,65433.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.26 65438[65:Spt:65436.0,65431.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 65441[65:Res:65438.0,61.1] always3(s18) || -> . % 76.04/76.26 65442[65:SSi:65441.0,707.0,63818.0] || -> . % 76.04/76.26 65443[63:Spt:65442.0,63813.2,63817.0] || xuntil6(s17)*+ -> . % 76.04/76.26 65444[63:Spt:65442.0,63813.0,63813.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.26 65445[63:Res:53.1,65444.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.26 65450[64:Spt:65445.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 65452[64:Res:65450.0,61.1] always3(s17) || -> . % 76.04/76.26 65453[64:SSi:65452.0,706.0,63812.0] || -> . % 76.04/76.26 65454[64:Spt:65453.0,65445.0,65450.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.26 65455[64:Spt:65453.0,65445.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 65459[64:Res:65455.0,61.1] always3(s18) || -> . % 76.04/76.26 65460[64:SSi:65459.0,707.0] || -> . % 76.04/76.26 65461[62:Spt:65460.0,63810.2,63811.0] || xuntil6(s16)*+ -> . % 76.04/76.26 65462[62:Spt:65460.0,63810.0,63810.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.26 65463[62:Res:53.1,65462.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.26 65465[63:Spt:65463.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 65467[63:Res:65465.0,61.1] always3(s17) || -> . % 76.04/76.26 65468[63:SSi:65467.0,706.0] || -> . % 76.04/76.26 65469[63:Spt:65468.0,65463.1,65465.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.26 65470[63:Spt:65468.0,65463.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 65473[63:Res:65470.0,61.1] always3(s16) || -> . % 76.04/76.26 65474[63:SSi:65473.0,705.0,63809.0] || -> . % 76.04/76.26 65475[61:Spt:65474.0,63804.2,63808.0] || xuntil6(s15)*+ -> . % 76.04/76.26 65476[61:Spt:65474.0,63804.0,63804.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.26 65477[61:Res:53.1,65476.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.26 65479[62:Spt:65477.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 65481[62:Res:65479.0,61.1] always3(s16) || -> . % 76.04/76.26 65482[62:SSi:65481.0,705.0] || -> . % 76.04/76.26 65483[62:Spt:65482.0,65477.1,65479.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.26 65484[62:Spt:65482.0,65477.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 65487[62:Res:65484.0,61.1] always3(s15) || -> . % 76.04/76.26 65488[62:SSi:65487.0,704.0,63803.0] || -> . % 76.04/76.26 65489[60:Spt:65488.0,63801.2,63802.0] || xuntil6(s14)*+ -> . % 76.04/76.26 65490[60:Spt:65488.0,63801.0,63801.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.26 65491[60:Res:53.1,65490.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.26 65496[61:Spt:65491.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 65498[61:Res:65496.0,61.1] always3(s14) || -> . % 76.04/76.26 65499[61:SSi:65498.0,703.0,63800.0] || -> . % 76.04/76.26 65500[61:Spt:65499.0,65491.0,65496.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.26 65501[61:Spt:65499.0,65491.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 65505[61:Res:65501.0,61.1] always3(s15) || -> . % 76.04/76.26 65506[61:SSi:65505.0,704.0] || -> . % 76.04/76.26 65507[59:Spt:65506.0,63795.2,63799.0] || xuntil6(s13)*+ -> . % 76.04/76.26 65508[59:Spt:65506.0,63795.0,63795.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.26 65509[59:Res:53.1,65508.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.26 65511[60:Spt:65509.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 65513[60:Res:65511.0,61.1] always3(s14) || -> . % 76.04/76.26 65514[60:SSi:65513.0,703.0] || -> . % 76.04/76.26 65515[60:Spt:65514.0,65509.1,65511.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.26 65516[60:Spt:65514.0,65509.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 65519[60:Res:65516.0,61.1] always3(s13) || -> . % 76.04/76.26 65520[60:SSi:65519.0,702.0,63794.0] || -> . % 76.04/76.26 65521[58:Spt:65520.0,63792.2,63793.0] || xuntil6(s12)*+ -> . % 76.04/76.26 65522[58:Spt:65520.0,63792.0,63792.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.26 65523[58:Res:53.1,65522.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.26 65525[59:Spt:65523.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 65527[59:Res:65525.0,61.1] always3(s13) || -> . % 76.04/76.26 65528[59:SSi:65527.0,702.0] || -> . % 76.04/76.26 65529[59:Spt:65528.0,65523.1,65525.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.26 65530[59:Spt:65528.0,65523.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 65533[59:Res:65530.0,61.1] always3(s12) || -> . % 76.04/76.26 65534[59:SSi:65533.0,701.0,63791.0] || -> . % 76.04/76.26 65535[57:Spt:65534.0,63786.2,63790.0] || xuntil6(s11)*+ -> . % 76.04/76.26 65536[57:Spt:65534.0,63786.0,63786.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.26 65537[57:Res:53.1,65536.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.26 65542[58:Spt:65537.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 65544[58:Res:65542.0,61.1] always3(s11) || -> . % 76.04/76.26 65545[58:SSi:65544.0,700.0,63785.0] || -> . % 76.04/76.26 65546[58:Spt:65545.0,65537.0,65542.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.26 65547[58:Spt:65545.0,65537.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 65551[58:Res:65547.0,61.1] always3(s12) || -> . % 76.04/76.26 65552[58:SSi:65551.0,701.0] || -> . % 76.04/76.26 65553[56:Spt:65552.0,63783.2,63784.0] || xuntil6(s10)*+ -> . % 76.04/76.26 65554[56:Spt:65552.0,63783.0,63783.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.26 65555[56:Res:53.1,65554.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.26 65557[57:Spt:65555.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 65559[57:Res:65557.0,61.1] always3(s11) || -> . % 76.04/76.26 65560[57:SSi:65559.0,700.0] || -> . % 76.04/76.26 65561[57:Spt:65560.0,65555.1,65557.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.26 65562[57:Spt:65560.0,65555.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 65565[57:Res:65562.0,61.1] always3(s10) || -> . % 76.04/76.26 65566[57:SSi:65565.0,699.0,63782.0] || -> . % 76.04/76.26 65567[55:Spt:65566.0,63777.2,63781.0] || xuntil6(s9)*+ -> . % 76.04/76.26 65568[55:Spt:65566.0,63777.0,63777.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.26 65569[55:Res:53.1,65568.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.26 65571[56:Spt:65569.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 65573[56:Res:65571.0,61.1] always3(s10) || -> . % 76.04/76.26 65574[56:SSi:65573.0,699.0] || -> . % 76.04/76.26 65575[56:Spt:65574.0,65569.1,65571.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.26 65576[56:Spt:65574.0,65569.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 65579[56:Res:65576.0,61.1] always3(s9) || -> . % 76.04/76.26 65580[56:SSi:65579.0,698.0,63776.0] || -> . % 76.04/76.26 65581[54:Spt:65580.0,63774.2,63775.0] || xuntil6(s8)*+ -> . % 76.04/76.26 65582[54:Spt:65580.0,63774.0,63774.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.26 65583[54:Res:53.1,65582.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.26 65588[55:Spt:65583.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 65590[55:Res:65588.0,61.1] always3(s9) || -> . % 76.04/76.26 65591[55:SSi:65590.0,698.0] || -> . % 76.04/76.26 65592[55:Spt:65591.0,65583.1,65588.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.26 65593[55:Spt:65591.0,65583.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 65596[55:Res:65593.0,61.1] always3(s8) || -> . % 76.04/76.26 65597[55:SSi:65596.0,697.0,63773.0] || -> . % 76.04/76.26 65598[53:Spt:65597.0,63768.2,63772.0] || xuntil6(s7)*+ -> . % 76.04/76.26 65599[53:Spt:65597.0,63768.0,63768.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.26 65600[53:Res:53.1,65599.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.26 65602[54:Spt:65600.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 65604[54:Res:65602.0,61.1] always3(s7) || -> . % 76.04/76.26 65605[54:SSi:65604.0,696.0,63767.0] || -> . % 76.04/76.26 65606[54:Spt:65605.0,65600.0,65602.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.26 65607[54:Spt:65605.0,65600.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 65611[54:Res:65607.0,61.1] always3(s8) || -> . % 76.04/76.26 65612[54:SSi:65611.0,697.0] || -> . % 76.04/76.26 65613[52:Spt:65612.0,63765.2,63766.0] || xuntil6(s6)*+ -> . % 76.04/76.26 65614[52:Spt:65612.0,63765.0,63765.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.26 65615[52:Res:53.1,65614.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.26 65617[53:Spt:65615.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 65619[53:Res:65617.0,61.1] always3(s7) || -> . % 76.04/76.26 65620[53:SSi:65619.0,696.0] || -> . % 76.04/76.26 65621[53:Spt:65620.0,65615.1,65617.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.26 65622[53:Spt:65620.0,65615.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 65625[53:Res:65622.0,61.1] always3(s6) || -> . % 76.04/76.26 65626[53:SSi:65625.0,695.0,63764.0] || -> . % 76.04/76.26 65627[51:Spt:65626.0,63759.2,63763.0] || xuntil6(s5)*+ -> . % 76.04/76.26 65628[51:Spt:65626.0,63759.0,63759.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.26 65629[51:Res:53.1,65628.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.26 65634[52:Spt:65629.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.26 65636[52:Res:65634.0,61.1] always3(s5) || -> . % 76.04/76.26 65637[52:SSi:65636.0,694.0,63758.0] || -> . % 76.04/76.26 65638[52:Spt:65637.0,65629.0,65634.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.26 65639[52:Spt:65637.0,65629.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 65643[52:Res:65639.0,61.1] always3(s6) || -> . % 76.04/76.26 65644[52:SSi:65643.0,695.0] || -> . % 76.04/76.26 65645[50:Spt:65644.0,63756.2,63757.0] || xuntil6(s4)*+ -> . % 76.04/76.26 65646[50:Spt:65644.0,63756.0,63756.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.26 65647[50:Res:53.1,65646.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.26 65649[51:Spt:65647.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.26 65651[51:Res:65649.0,61.1] always3(s4) || -> . % 76.04/76.26 65652[51:SSi:65651.0,693.0,63755.0] || -> . % 76.04/76.26 65653[51:Spt:65652.0,65647.0,65649.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.26 65654[51:Spt:65652.0,65647.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.26 65658[51:Res:65654.0,61.1] always3(s5) || -> . % 76.04/76.26 65659[51:SSi:65658.0,694.0] || -> . % 76.04/76.26 65660[49:Spt:65659.0,63753.2,63754.0] || xuntil6(s3)*+ -> . % 76.04/76.26 65661[49:Spt:65659.0,63753.0,63753.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.26 65662[49:Res:53.1,65661.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.26 65664[50:Spt:65662.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.26 65666[50:Res:65664.0,61.1] always3(s3) || -> . % 76.04/76.26 65667[50:SSi:65666.0,692.0,63752.0] || -> . % 76.04/76.26 65668[50:Spt:65667.0,65662.0,65664.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.26 65669[50:Spt:65667.0,65662.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.26 65673[50:Res:65669.0,61.1] always3(s4) || -> . % 76.04/76.26 65674[50:SSi:65673.0,693.0] || -> . % 76.04/76.26 65675[48:Spt:65674.0,63750.2,63751.0] || xuntil6(s2)*+ -> . % 76.04/76.26 65676[48:Spt:65674.0,63750.0,63750.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.26 65677[48:Res:53.1,65676.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.26 65682[49:Spt:65677.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.26 65684[49:Res:65682.0,61.1] always3(s2) || -> . % 76.04/76.26 65685[49:SSi:65684.0,691.0,63749.0] || -> . % 76.04/76.26 65686[49:Spt:65685.0,65677.0,65682.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.26 65687[49:Spt:65685.0,65677.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.26 65691[49:Res:65687.0,61.1] always3(s3) || -> . % 76.04/76.26 65692[49:SSi:65691.0,692.0] || -> . % 76.04/76.26 65693[47:Spt:65692.0,63744.2,63748.0] || xuntil6(s1)*+ -> . % 76.04/76.26 65694[47:Spt:65692.0,63744.0,63744.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.26 65695[47:Res:53.1,65694.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.26 65697[48:Spt:65695.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.26 65699[48:Res:65697.0,61.1] always3(s1) || -> . % 76.04/76.26 65700[48:SSi:65699.0,690.0,63743.0] || -> . % 76.04/76.26 65701[48:Spt:65700.0,65695.0,65697.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.26 65702[48:Spt:65700.0,65695.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.26 65707[48:Res:65702.0,61.1] always3(s2) || -> . % 76.04/76.26 65708[48:SSi:65707.0,691.0] || -> . % 76.04/76.26 65709[46:Spt:65708.0,74.0,63742.0] || xuntil6(s0)*+ -> . % 76.04/76.26 65710[46:Spt:65708.0,74.1] || -> node4(s0)*. % 76.04/76.26 65711[46:MRR:758.1,65709.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.26 65713[46:Res:65711.0,61.1] always3(s1) || -> . % 76.04/76.26 65714[46:SSi:65713.0,690.0] || -> . % 76.04/76.26 65715[45:Spt:65714.0,63732.0,63736.0] || trans(s49,s6)*+ -> . % 76.04/76.26 65716[45:Spt:65714.0,63732.1,63732.2,63732.3,63732.4,63732.5,63732.6] || -> trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.26 65718[45:MRR:63733.0,65715.0] || -> trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.26 65719[45:MRR:63735.1,65715.0] xuntil6(s49) || -> trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.26 65720[46:Spt:65716.0] || -> trans(s49,s5)*. % 76.04/76.26 65721[46:Res:65720.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s5)*. % 76.04/76.26 65723[46:Res:65720.0,60.0] || -> node2(s49,s5)*. % 76.04/76.26 65724[46:SSi:65721.1,50.0,738.0] xuntil6(s49) || -> until2p7(s5)*. % 76.04/76.26 65725[46:Res:65723.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)*. % 76.04/76.26 65726[47:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.26 65727[47:MRR:176.0,65726.0] || -> until5(s1)*. % 76.04/76.26 65728[47:MRR:64172.0,65727.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.26 65735[48:Spt:65728.2] || -> xuntil6(s1)*. % 76.04/76.26 65736[48:MRR:175.0,65735.0] || -> until5(s2)*. % 76.04/76.26 65737[48:MRR:64171.0,65736.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.26 65738[49:Spt:65737.2] || -> xuntil6(s2)*. % 76.04/76.26 65739[49:MRR:174.0,65738.0] || -> until5(s3)*. % 76.04/76.26 65740[49:MRR:64164.0,65739.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.26 65744[50:Spt:65740.2] || -> xuntil6(s3)*. % 76.04/76.26 65745[50:MRR:173.0,65744.0] || -> until5(s4)*. % 76.04/76.26 65746[50:MRR:64160.0,65745.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.26 65747[51:Spt:65746.2] || -> xuntil6(s4)*. % 76.04/76.26 65748[51:MRR:172.0,65747.0] || -> until5(s5)*. % 76.04/76.26 65749[51:MRR:64156.0,65748.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.26 65753[52:Spt:65749.2] || -> xuntil6(s5)*. % 76.04/76.26 65754[52:MRR:171.0,65753.0] || -> until5(s6)*. % 76.04/76.26 65755[52:MRR:64152.0,65754.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.26 65756[53:Spt:65755.2] || -> xuntil6(s6)*. % 76.04/76.26 65757[53:MRR:170.0,65756.0] || -> until5(s7)*. % 76.04/76.26 65758[53:MRR:64145.0,65757.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.26 65762[54:Spt:65758.2] || -> xuntil6(s7)*. % 76.04/76.26 65763[54:MRR:169.0,65762.0] || -> until5(s8)*. % 76.04/76.26 65764[54:MRR:64141.0,65763.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.26 65765[55:Spt:65764.2] || -> xuntil6(s8)*. % 76.04/76.26 65766[55:MRR:168.0,65765.0] || -> until5(s9)*. % 76.04/76.26 65767[55:MRR:64140.0,65766.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.26 65771[56:Spt:65767.2] || -> xuntil6(s9)*. % 76.04/76.26 65772[56:MRR:167.0,65771.0] || -> until5(s10)*. % 76.04/76.26 65773[56:MRR:64133.0,65772.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.26 65774[57:Spt:65773.2] || -> xuntil6(s10)*. % 76.04/76.26 65775[57:MRR:166.0,65774.0] || -> until5(s11)*. % 76.04/76.26 65776[57:MRR:64132.0,65775.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.26 65780[58:Spt:65776.2] || -> xuntil6(s11)*. % 76.04/76.26 65781[58:MRR:165.0,65780.0] || -> until5(s12)*. % 76.04/76.26 65782[58:MRR:64131.0,65781.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.26 65783[59:Spt:65782.2] || -> xuntil6(s12)*. % 76.04/76.26 65784[59:MRR:164.0,65783.0] || -> until5(s13)*. % 76.04/76.26 65785[59:MRR:64121.0,65784.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.26 65789[60:Spt:65785.2] || -> xuntil6(s13)*. % 76.04/76.26 65790[60:MRR:163.0,65789.0] || -> until5(s14)*. % 76.04/76.26 65791[60:MRR:64120.0,65790.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.26 65792[61:Spt:65791.2] || -> xuntil6(s14)*. % 76.04/76.26 65793[61:MRR:162.0,65792.0] || -> until5(s15)*. % 76.04/76.26 65794[61:MRR:64116.0,65793.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.26 65798[62:Spt:65794.2] || -> xuntil6(s15)*. % 76.04/76.26 65799[62:MRR:161.0,65798.0] || -> until5(s16)*. % 76.04/76.26 65800[62:MRR:64109.0,65799.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.26 65801[63:Spt:65800.2] || -> xuntil6(s16)*. % 76.04/76.26 65802[63:MRR:160.0,65801.0] || -> until5(s17)*. % 76.04/76.26 65803[63:MRR:64105.0,65802.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.26 65807[64:Spt:65803.2] || -> xuntil6(s17)*. % 76.04/76.26 65808[64:MRR:159.0,65807.0] || -> until5(s18)*. % 76.04/76.26 65809[64:MRR:64104.0,65808.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.26 65810[65:Spt:65809.2] || -> xuntil6(s18)*. % 76.04/76.26 65811[65:MRR:158.0,65810.0] || -> until5(s19)*. % 76.04/76.26 65812[65:MRR:64100.0,65811.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.26 65816[66:Spt:65812.2] || -> xuntil6(s19)*. % 76.04/76.26 65817[66:MRR:157.0,65816.0] || -> until5(s20)*. % 76.04/76.26 65818[66:MRR:64093.0,65817.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.26 65819[67:Spt:65818.2] || -> xuntil6(s20)*. % 76.04/76.26 65820[67:MRR:156.0,65819.0] || -> until5(s21)*. % 76.04/76.26 65821[67:MRR:64092.0,65820.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.26 65825[68:Spt:65821.2] || -> xuntil6(s21)*. % 76.04/76.26 65826[68:MRR:155.0,65825.0] || -> until5(s22)*. % 76.04/76.26 65827[68:MRR:64085.0,65826.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.26 65828[69:Spt:65827.2] || -> xuntil6(s22)*. % 76.04/76.26 65829[69:MRR:154.0,65828.0] || -> until5(s23)*. % 76.04/76.26 65830[69:MRR:64081.0,65829.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.26 65834[70:Spt:65830.2] || -> xuntil6(s23)*. % 76.04/76.26 65835[70:MRR:153.0,65834.0] || -> until5(s24)*. % 76.04/76.26 65836[70:MRR:64080.0,65835.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.26 65837[71:Spt:65836.2] || -> xuntil6(s24)*. % 76.04/76.26 65838[71:MRR:152.0,65837.0] || -> until5(s25)*. % 76.04/76.26 65839[71:MRR:64073.0,65838.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.26 65843[72:Spt:65839.2] || -> xuntil6(s25)*. % 76.04/76.26 65844[72:MRR:151.0,65843.0] || -> until5(s26)*. % 76.04/76.26 65845[72:MRR:64069.0,65844.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.26 65846[73:Spt:65845.2] || -> xuntil6(s26)*. % 76.04/76.26 65847[73:MRR:150.0,65846.0] || -> until5(s27)*. % 76.04/76.26 65848[73:MRR:64065.0,65847.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.26 65852[74:Spt:65848.2] || -> xuntil6(s27)*. % 76.04/76.26 65853[74:MRR:149.0,65852.0] || -> until5(s28)*. % 76.04/76.26 65854[74:MRR:64064.0,65853.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.26 65855[75:Spt:65854.2] || -> xuntil6(s28)*. % 76.04/76.26 65856[75:MRR:148.0,65855.0] || -> until5(s29)*. % 76.04/76.26 65857[75:MRR:64063.0,65856.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.26 65861[76:Spt:65857.2] || -> xuntil6(s29)*. % 76.04/76.26 65862[76:MRR:147.0,65861.0] || -> until5(s30)*. % 76.04/76.26 65863[76:MRR:64062.0,65862.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.26 65864[77:Spt:65863.2] || -> xuntil6(s30)*. % 76.04/76.26 65865[77:MRR:146.0,65864.0] || -> until5(s31)*. % 76.04/76.26 65866[77:MRR:64058.0,65865.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.26 65870[78:Spt:65866.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.26 65872[78:Res:65870.0,61.1] always3(s32) || -> . % 76.04/76.26 65873[78:SSi:65872.0,721.0] || -> . % 76.04/76.26 65874[78:Spt:65873.0,65866.1,65870.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.04/76.26 65875[78:Spt:65873.0,65866.0,65866.2] || m_main_v_state(s31,c_ready)*+ -> xuntil6(s31). % 76.04/76.26 65877[78:MRR:825.2,65874.0] node4(s31) || m_main_v_state(s31,c_ready)* -> . % 76.04/76.26 65878[78:Res:53.1,65875.0] || -> m_main_v_state(s31,c_busy)* xuntil6(s31). % 76.04/76.26 65880[79:Spt:65878.1] || -> xuntil6(s31)*. % 76.04/76.26 65881[79:MRR:145.0,65880.0] || -> until5(s32)*. % 76.04/76.26 65882[79:MRR:64057.0,65881.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.26 65887[80:Spt:65882.2] || -> xuntil6(s32)*. % 76.04/76.26 65888[80:MRR:144.0,65887.0] || -> until5(s33)*. % 76.04/76.26 65889[80:MRR:62224.0,65888.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.26 65890[81:Spt:65889.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.26 65892[81:Res:65890.0,61.1] always3(s34) || -> . % 76.04/76.26 65893[81:SSi:65892.0,723.0] || -> . % 76.04/76.26 65894[81:Spt:65893.0,65889.1,65890.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.26 65895[81:Spt:65893.0,65889.0,65889.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.26 65897[81:MRR:819.2,65894.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.26 65898[81:Res:53.1,65895.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.26 65900[82:Spt:65898.1] || -> xuntil6(s33)*. % 76.04/76.26 65901[82:MRR:143.0,65900.0] || -> until5(s34)*. % 76.04/76.26 65902[82:MRR:64182.0,65901.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.26 65910[83:Spt:65902.2] || -> xuntil6(s34)*. % 76.04/76.26 65911[83:MRR:142.0,65910.0] || -> until5(s35)*. % 76.04/76.26 65912[83:MRR:62231.0,65911.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.26 65913[84:Spt:65912.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.26 65915[84:Res:65913.0,61.1] always3(s36) || -> . % 76.04/76.26 65916[84:SSi:65915.0,725.0] || -> . % 76.04/76.26 65917[84:Spt:65916.0,65912.1,65913.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.26 65918[84:Spt:65916.0,65912.0,65912.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.26 65920[84:MRR:813.2,65917.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.26 65921[84:Res:53.1,65918.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.26 65926[85:Spt:65921.1] || -> xuntil6(s35)*. % 76.04/76.26 65927[85:MRR:141.0,65926.0] || -> until5(s36)*. % 76.04/76.26 65928[85:MRR:64183.0,65927.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.26 65930[86:Spt:65928.2] || -> xuntil6(s36)*. % 76.04/76.26 65931[86:MRR:140.0,65930.0] || -> until5(s37)*. % 76.04/76.26 65932[86:MRR:62232.0,65931.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.26 65933[87:Spt:65932.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.26 65935[87:Res:65933.0,61.1] always3(s38) || -> . % 76.04/76.26 65936[87:SSi:65935.0,727.0] || -> . % 76.04/76.26 65937[87:Spt:65936.0,65932.1,65933.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.26 65938[87:Spt:65936.0,65932.0,65932.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.26 65940[87:MRR:807.2,65937.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.26 65941[87:Res:53.1,65938.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.26 65943[88:Spt:65941.1] || -> xuntil6(s37)*. % 76.04/76.26 65944[88:MRR:139.0,65943.0] || -> until5(s38)*. % 76.04/76.26 65945[88:MRR:64187.0,65944.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.26 65950[89:Spt:65945.2] || -> xuntil6(s38)*. % 76.04/76.26 65951[89:MRR:138.0,65950.0] || -> until5(s39)*. % 76.04/76.26 65952[89:MRR:62236.0,65951.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.26 65953[90:Spt:65952.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.26 65955[90:Res:65953.0,61.1] always3(s40) || -> . % 76.04/76.26 65956[90:SSi:65955.0,729.0] || -> . % 76.04/76.26 65957[90:Spt:65956.0,65952.1,65953.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.26 65958[90:Spt:65956.0,65952.0,65952.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.26 65960[90:MRR:801.2,65957.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.26 65961[90:Res:53.1,65958.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.26 65963[91:Spt:65961.1] || -> xuntil6(s39)*. % 76.04/76.26 65964[91:MRR:137.0,65963.0] || -> until5(s40)*. % 76.04/76.26 65965[91:MRR:64191.0,65964.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.26 65973[92:Spt:65965.2] || -> xuntil6(s40)*. % 76.04/76.26 65974[92:MRR:136.0,65973.0] || -> until5(s41)*. % 76.04/76.26 65975[92:MRR:62240.0,65974.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.26 65976[93:Spt:65975.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.26 65978[93:Res:65976.0,61.1] always3(s42) || -> . % 76.04/76.26 65979[93:SSi:65978.0,731.0] || -> . % 76.04/76.26 65980[93:Spt:65979.0,65975.1,65976.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.26 65981[93:Spt:65979.0,65975.0,65975.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.26 65983[93:MRR:795.2,65980.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.26 65984[93:Res:53.1,65981.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.26 65989[94:Spt:65984.1] || -> xuntil6(s41)*. % 76.04/76.26 65990[94:MRR:135.0,65989.0] || -> until5(s42)*. % 76.04/76.26 65991[94:MRR:64195.0,65990.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.26 65993[95:Spt:65991.2] || -> xuntil6(s42)*. % 76.04/76.26 65994[95:MRR:134.0,65993.0] || -> until5(s43)*. % 76.04/76.26 65995[95:MRR:62244.0,65994.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.26 65996[96:Spt:65995.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.26 65998[96:Res:65996.0,61.1] always3(s44) || -> . % 76.04/76.26 65999[96:SSi:65998.0,733.0] || -> . % 76.04/76.26 66000[96:Spt:65999.0,65995.1,65996.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.26 66001[96:Spt:65999.0,65995.0,65995.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.26 66003[96:MRR:789.2,66000.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.26 66004[96:Res:53.1,66001.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.26 66006[97:Spt:66004.1] || -> xuntil6(s43)*. % 76.04/76.26 66007[97:MRR:133.0,66006.0] || -> until5(s44)*. % 76.04/76.26 66008[97:MRR:64202.0,66007.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.26 66013[98:Spt:66008.2] || -> xuntil6(s44)*. % 76.04/76.26 66014[98:MRR:132.0,66013.0] || -> until5(s45)*. % 76.04/76.26 66015[98:MRR:62251.0,66014.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.26 66016[99:Spt:66015.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.26 66018[99:Res:66016.0,61.1] always3(s46) || -> . % 76.04/76.26 66019[99:SSi:66018.0,735.0] || -> . % 76.04/76.26 66020[99:Spt:66019.0,66015.1,66016.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.26 66021[99:Spt:66019.0,66015.0,66015.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.26 66023[99:MRR:783.2,66020.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.26 66024[99:Res:53.1,66021.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.26 66026[100:Spt:66024.1] || -> xuntil6(s45)*. % 76.04/76.26 66027[100:MRR:131.0,66026.0] || -> until5(s46)*. % 76.04/76.26 66028[100:MRR:64203.0,66027.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.26 66036[101:Spt:66028.2] || -> xuntil6(s46)*. % 76.04/76.26 66037[101:MRR:130.0,66036.0] || -> until5(s47)*. % 76.04/76.26 66038[101:MRR:62252.0,66037.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.26 66039[102:Spt:66038.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.26 66041[102:Res:66039.0,61.1] always3(s48) || -> . % 76.04/76.26 66042[102:SSi:66041.0,737.0] || -> . % 76.04/76.26 66043[102:Spt:66042.0,66038.1,66039.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.26 66044[102:Spt:66042.0,66038.0,66038.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.26 66046[102:MRR:777.2,66043.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.26 66047[102:Res:53.1,66044.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.26 66052[103:Spt:66047.1] || -> xuntil6(s47)*. % 76.04/76.26 66053[103:MRR:129.0,66052.0] || -> until5(s48)*. % 76.04/76.26 66054[103:MRR:64207.0,66053.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.26 66056[104:Spt:66054.2] || -> xuntil6(s48)*. % 76.04/76.26 66057[104:MRR:128.0,66056.0] || -> until5(s49)*. % 76.04/76.26 66058[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.26 66059[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.26 66060[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.26 66061[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.26 66065[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.26 66069[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.26 66076[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.26 66077[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.26 66087[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.26 66088[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.26 66089[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.26 66096[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.26 66097[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.26 66101[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.26 66108[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.26 66109[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.26 66116[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.26 66120[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.26 66121[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.26 66125[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.26 66132[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.26 66136[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.26 66137[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.26 66141[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.26 66148[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.26 66152[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.26 66156[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.26 66160[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.26 66167[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.26 66168[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.26 66170[46:SoR:65725.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)*. % 76.04/76.26 66178[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.26 66179[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.26 66183[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.26 66187[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.26 66191[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.26 66198[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.26 66199[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.26 66203[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.26 66207[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.26 66208[46:SoR:66170.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)* xuntil6(s49). % 76.04/76.26 66209[104:SSi:66208.0,50.0,738.0,66057.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s5,c_busy)* xuntil6(s49). % 76.04/76.26 66210[105:Spt:66209.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.26 66212[105:Res:66210.0,61.1] always3(s5) || -> . % 76.04/76.26 66213[105:SSi:66212.0,694.0,65748.0,65753.0] || -> . % 76.04/76.26 66214[105:Spt:66213.0,66209.1,66210.0] || m_main_v_state(s5,c_busy)*+ -> . % 76.04/76.26 66215[105:Spt:66213.0,66209.0,66209.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.26 66219[105:MRR:66170.2,66214.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.26 66220[105:Res:53.1,66215.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.26 66225[106:Spt:66220.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.26 66227[106:Res:66225.0,61.1] always3(s49) || -> . % 76.04/76.26 66228[106:SSi:66227.0,50.0,738.0,66057.0] || -> . % 76.04/76.26 66229[106:Spt:66228.0,66220.0,66225.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.26 66230[106:Spt:66228.0,66220.1] || -> xuntil6(s49)*. % 76.04/76.26 66231[106:MRR:65724.0,66230.0] || -> until2p7(s5)*. % 76.04/76.26 66232[106:MRR:201.0,66231.0] || -> until2p7(s6)* node4(s5). % 76.04/76.26 66234[106:MRR:774.2,66229.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.26 66235[107:Spt:66232.0] || -> until2p7(s6)*. % 76.04/76.26 66236[107:MRR:202.0,66235.0] || -> until2p7(s7)* node4(s6). % 76.04/76.26 66237[108:Spt:66236.0] || -> until2p7(s7)*. % 76.04/76.26 66238[108:MRR:203.0,66237.0] || -> until2p7(s8)* node4(s7). % 76.04/76.26 66239[109:Spt:66238.0] || -> until2p7(s8)*. % 76.04/76.26 66240[109:MRR:204.0,66239.0] || -> until2p7(s9)* node4(s8). % 76.04/76.26 66241[110:Spt:66240.0] || -> until2p7(s9)*. % 76.04/76.26 66242[110:MRR:205.0,66241.0] || -> until2p7(s10)* node4(s9). % 76.04/76.26 66243[111:Spt:66242.0] || -> until2p7(s10)*. % 76.04/76.26 66244[111:MRR:206.0,66243.0] || -> until2p7(s11)* node4(s10). % 76.04/76.26 66245[112:Spt:66244.0] || -> until2p7(s11)*. % 76.04/76.26 66246[112:MRR:207.0,66245.0] || -> until2p7(s12)* node4(s11). % 76.04/76.26 66247[113:Spt:66246.0] || -> until2p7(s12)*. % 76.04/76.26 66248[113:MRR:208.0,66247.0] || -> until2p7(s13)* node4(s12). % 76.04/76.26 66249[114:Spt:66248.0] || -> until2p7(s13)*. % 76.04/76.26 66250[114:MRR:209.0,66249.0] || -> until2p7(s14)* node4(s13). % 76.04/76.26 66251[115:Spt:66250.0] || -> until2p7(s14)*. % 76.04/76.26 66252[115:MRR:210.0,66251.0] || -> until2p7(s15)* node4(s14). % 76.04/76.26 66253[116:Spt:66252.0] || -> until2p7(s15)*. % 76.04/76.26 66254[116:MRR:211.0,66253.0] || -> until2p7(s16)* node4(s15). % 76.04/76.26 66255[117:Spt:66254.0] || -> until2p7(s16)*. % 76.04/76.26 66256[117:MRR:212.0,66255.0] || -> until2p7(s17)* node4(s16). % 76.04/76.26 66257[118:Spt:66256.0] || -> until2p7(s17)*. % 76.04/76.26 66258[118:MRR:213.0,66257.0] || -> until2p7(s18)* node4(s17). % 76.04/76.26 66259[119:Spt:66258.0] || -> until2p7(s18)*. % 76.04/76.26 66260[119:MRR:214.0,66259.0] || -> until2p7(s19)* node4(s18). % 76.04/76.26 66261[120:Spt:66260.0] || -> until2p7(s19)*. % 76.04/76.26 66262[120:MRR:215.0,66261.0] || -> until2p7(s20)* node4(s19). % 76.04/76.26 66263[121:Spt:66262.0] || -> until2p7(s20)*. % 76.04/76.26 66264[121:MRR:216.0,66263.0] || -> until2p7(s21)* node4(s20). % 76.04/76.26 66265[122:Spt:66264.0] || -> until2p7(s21)*. % 76.04/76.26 66266[122:MRR:217.0,66265.0] || -> until2p7(s22)* node4(s21). % 76.04/76.26 66267[123:Spt:66266.0] || -> until2p7(s22)*. % 76.04/76.26 66268[123:MRR:218.0,66267.0] || -> until2p7(s23)* node4(s22). % 76.04/76.26 66269[124:Spt:66268.0] || -> until2p7(s23)*. % 76.04/76.26 66270[124:MRR:219.0,66269.0] || -> until2p7(s24)* node4(s23). % 76.04/76.26 66271[125:Spt:66270.0] || -> until2p7(s24)*. % 76.04/76.26 66272[125:MRR:220.0,66271.0] || -> until2p7(s25)* node4(s24). % 76.04/76.26 66273[126:Spt:66272.0] || -> until2p7(s25)*. % 76.04/76.26 66274[126:MRR:221.0,66273.0] || -> until2p7(s26)* node4(s25). % 76.04/76.26 66275[127:Spt:66274.0] || -> until2p7(s26)*. % 76.04/76.26 66276[127:MRR:222.0,66275.0] || -> until2p7(s27)* node4(s26). % 76.04/76.26 66277[128:Spt:66276.0] || -> until2p7(s27)*. % 76.04/76.26 66278[128:MRR:223.0,66277.0] || -> until2p7(s28)* node4(s27). % 76.04/76.26 66279[129:Spt:66278.0] || -> until2p7(s28)*. % 76.04/76.26 66280[129:MRR:224.0,66279.0] || -> until2p7(s29)* node4(s28). % 76.04/76.26 66281[130:Spt:66280.0] || -> until2p7(s29)*. % 76.04/76.26 66282[130:MRR:225.0,66281.0] || -> until2p7(s30)* node4(s29). % 76.04/76.26 66283[131:Spt:66282.0] || -> until2p7(s30)*. % 76.04/76.26 66284[131:MRR:226.0,66283.0] || -> until2p7(s31)* node4(s30). % 76.04/76.26 66285[132:Spt:66284.0] || -> until2p7(s31)*. % 76.04/76.26 66286[132:MRR:227.0,66285.0] || -> until2p7(s32)* node4(s31). % 76.04/76.26 66287[133:Spt:66286.0] || -> until2p7(s32)*. % 76.04/76.26 66288[133:MRR:228.0,66287.0] || -> until2p7(s33)* node4(s32). % 76.04/76.26 66289[134:Spt:66288.0] || -> until2p7(s33)*. % 76.04/76.26 66290[134:MRR:229.0,66289.0] || -> until2p7(s34)* node4(s33). % 76.04/76.26 66291[135:Spt:66290.0] || -> until2p7(s34)*. % 76.04/76.26 66292[135:MRR:230.0,66291.0] || -> until2p7(s35)* node4(s34). % 76.04/76.26 66293[136:Spt:66292.0] || -> until2p7(s35)*. % 76.04/76.26 66294[136:MRR:231.0,66293.0] || -> until2p7(s36)* node4(s35). % 76.04/76.26 66295[137:Spt:66294.0] || -> until2p7(s36)*. % 76.04/76.26 66296[137:MRR:232.0,66295.0] || -> until2p7(s37)* node4(s36). % 76.04/76.26 66297[138:Spt:66296.0] || -> until2p7(s37)*. % 76.04/76.26 66298[138:MRR:235.0,66297.0] || -> until2p7(s38)* node4(s37). % 76.04/76.26 66299[139:Spt:66298.0] || -> until2p7(s38)*. % 76.04/76.26 66300[139:MRR:236.0,66299.0] || -> until2p7(s39)* node4(s38). % 76.04/76.26 66301[140:Spt:66300.0] || -> until2p7(s39)*. % 76.04/76.26 66302[140:MRR:237.0,66301.0] || -> until2p7(s40)* node4(s39). % 76.04/76.26 66303[141:Spt:66302.0] || -> until2p7(s40)*. % 76.04/76.26 66304[141:MRR:238.0,66303.0] || -> until2p7(s41)* node4(s40). % 76.04/76.26 66305[142:Spt:66304.0] || -> until2p7(s41)*. % 76.04/76.26 66306[142:MRR:239.0,66305.0] || -> until2p7(s42)* node4(s41). % 76.04/76.26 66307[143:Spt:66306.0] || -> until2p7(s42)*. % 76.04/76.26 66308[143:MRR:240.0,66307.0] || -> until2p7(s43)* node4(s42). % 76.04/76.26 66309[144:Spt:66308.0] || -> until2p7(s43)*. % 76.04/76.26 66310[144:MRR:241.0,66309.0] || -> until2p7(s44)* node4(s43). % 76.04/76.26 66311[145:Spt:66310.0] || -> until2p7(s44)*. % 76.04/76.26 66312[145:MRR:539.0,66311.0] || -> until2p7(s45)* node4(s44). % 76.04/76.26 66313[146:Spt:66312.0] || -> until2p7(s45)*. % 76.04/76.26 66314[146:MRR:544.0,66313.0] || -> until2p7(s46)* node4(s45). % 76.04/76.26 66315[147:Spt:66314.0] || -> until2p7(s46)*. % 76.04/76.26 66316[147:MRR:549.0,66315.0] || -> until2p7(s47)* node4(s46). % 76.04/76.26 66317[148:Spt:66316.0] || -> until2p7(s47)*. % 76.04/76.26 66318[148:MRR:554.0,66317.0] || -> until2p7(s48)* node4(s47). % 76.04/76.26 66319[149:Spt:66318.0] || -> until2p7(s48)*. % 76.04/76.26 66320[149:MRR:559.0,66319.0] || -> until2p7(s49)* node4(s48). % 76.04/76.26 66321[150:Spt:66320.0] || -> until2p7(s49)*. % 76.04/76.26 66322[150:MRR:194.0,66321.0] || -> node4(s49)*. % 76.04/76.26 66323[150:MRR:66219.0,66322.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.26 66324[150:Res:53.1,66323.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.26 66326[150:MRR:66324.0,66229.0] || -> . % 76.04/76.26 66327[150:Spt:66326.0,66320.0,66321.0] || until2p7(s49)*+ -> . % 76.04/76.26 66328[150:Spt:66326.0,66320.1] || -> node4(s48)*. % 76.04/76.26 66329[150:MRR:66234.0,66328.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.26 66332[150:Res:53.1,66329.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.26 66334[150:MRR:66332.0,66043.0] || -> . % 76.04/76.26 66335[149:Spt:66334.0,66318.0,66319.0] || until2p7(s48)*+ -> . % 76.04/76.26 66336[149:Spt:66334.0,66318.1] || -> node4(s47)*. % 76.04/76.26 66337[149:MRR:66046.0,66336.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.26 66340[149:Res:53.1,66337.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.26 66343[149:Res:66340.0,61.1] always3(s47) || -> . % 76.04/76.26 66344[149:SSi:66343.0,736.0,66037.0,66052.0,66317.0,66336.0] || -> . % 76.04/76.26 66345[148:Spt:66344.0,66316.0,66317.0] || until2p7(s47)*+ -> . % 76.04/76.26 66346[148:Spt:66344.0,66316.1] || -> node4(s46)*. % 76.04/76.26 66348[148:MRR:780.0,66346.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.26 66365[148:Res:53.1,66348.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.26 66367[148:MRR:66365.0,66020.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.26 66369[148:Res:66367.0,61.1] always3(s47) || -> . % 76.04/76.26 66370[148:SSi:66369.0,736.0,66037.0,66052.0] || -> . % 76.04/76.26 66371[147:Spt:66370.0,66314.0,66315.0] || until2p7(s46)*+ -> . % 76.04/76.26 66372[147:Spt:66370.0,66314.1] || -> node4(s45)*. % 76.04/76.26 66373[147:MRR:66023.0,66372.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.26 66377[147:Res:53.1,66373.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.26 66380[147:Res:66377.0,61.1] always3(s45) || -> . % 76.04/76.26 66381[147:SSi:66380.0,734.0,66014.0,66026.0,66313.0,66372.0] || -> . % 76.04/76.26 66382[146:Spt:66381.0,66312.0,66313.0] || until2p7(s45)*+ -> . % 76.04/76.26 66383[146:Spt:66381.0,66312.1] || -> node4(s44)*. % 76.04/76.26 66385[146:MRR:786.0,66383.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.26 66396[146:Res:53.1,66385.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.26 66398[146:MRR:66396.0,66000.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.26 66400[146:Res:66398.0,61.1] always3(s45) || -> . % 76.04/76.26 66401[146:SSi:66400.0,734.0,66014.0,66026.0] || -> . % 76.04/76.26 66402[145:Spt:66401.0,66310.0,66311.0] || until2p7(s44)*+ -> . % 76.04/76.26 66403[145:Spt:66401.0,66310.1] || -> node4(s43)*. % 76.04/76.26 66404[145:MRR:66003.0,66403.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.26 66407[145:Res:53.1,66404.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.26 66410[145:Res:66407.0,61.1] always3(s43) || -> . % 76.04/76.26 66411[145:SSi:66410.0,732.0,65994.0,66006.0,66309.0,66403.0] || -> . % 76.04/76.26 66412[144:Spt:66411.0,66308.0,66309.0] || until2p7(s43)*+ -> . % 76.04/76.26 66413[144:Spt:66411.0,66308.1] || -> node4(s42)*. % 76.04/76.26 66415[144:MRR:792.0,66413.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.26 66427[144:Res:53.1,66415.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.26 66429[144:MRR:66427.0,65980.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.26 66431[144:Res:66429.0,61.1] always3(s43) || -> . % 76.04/76.26 66432[144:SSi:66431.0,732.0,65994.0,66006.0] || -> . % 76.04/76.26 66433[143:Spt:66432.0,66306.0,66307.0] || until2p7(s42)*+ -> . % 76.04/76.26 66434[143:Spt:66432.0,66306.1] || -> node4(s41)*. % 76.04/76.26 66435[143:MRR:65983.0,66434.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.26 66438[143:Res:53.1,66435.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.26 66441[143:Res:66438.0,61.1] always3(s41) || -> . % 76.04/76.26 66442[143:SSi:66441.0,730.0,65974.0,65989.0,66305.0,66434.0] || -> . % 76.04/76.26 66443[142:Spt:66442.0,66304.0,66305.0] || until2p7(s41)*+ -> . % 76.04/76.26 66444[142:Spt:66442.0,66304.1] || -> node4(s40)*. % 76.04/76.26 66446[142:MRR:798.0,66444.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.26 66458[142:Res:53.1,66446.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.26 66460[142:MRR:66458.0,65957.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.26 66465[142:Res:66460.0,61.1] always3(s41) || -> . % 76.04/76.26 66466[142:SSi:66465.0,730.0,65974.0,65989.0] || -> . % 76.04/76.26 66467[141:Spt:66466.0,66302.0,66303.0] || until2p7(s40)*+ -> . % 76.04/76.26 66468[141:Spt:66466.0,66302.1] || -> node4(s39)*. % 76.04/76.26 66469[141:MRR:65960.0,66468.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.26 66472[141:Res:53.1,66469.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.26 66476[141:Res:66472.0,61.1] always3(s39) || -> . % 76.04/76.26 66477[141:SSi:66476.0,728.0,65951.0,65963.0,66301.0,66468.0] || -> . % 76.04/76.26 66478[140:Spt:66477.0,66300.0,66301.0] || until2p7(s39)*+ -> . % 76.04/76.26 66479[140:Spt:66477.0,66300.1] || -> node4(s38)*. % 76.04/76.26 66481[140:MRR:804.0,66479.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.26 66492[140:Res:53.1,66481.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.26 66494[140:MRR:66492.0,65937.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.26 66496[140:Res:66494.0,61.1] always3(s39) || -> . % 76.04/76.26 66497[140:SSi:66496.0,728.0,65951.0,65963.0] || -> . % 76.04/76.26 66498[139:Spt:66497.0,66298.0,66299.0] || until2p7(s38)*+ -> . % 76.04/76.26 66499[139:Spt:66497.0,66298.1] || -> node4(s37)*. % 76.04/76.26 66500[139:MRR:65940.0,66499.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.26 66504[139:Res:53.1,66500.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.26 66507[139:Res:66504.0,61.1] always3(s37) || -> . % 76.04/76.26 66508[139:SSi:66507.0,726.0,65931.0,65943.0,66297.0,66499.0] || -> . % 76.04/76.26 66509[138:Spt:66508.0,66296.0,66297.0] || until2p7(s37)*+ -> . % 76.04/76.26 66510[138:Spt:66508.0,66296.1] || -> node4(s36)*. % 76.04/76.26 66512[138:MRR:810.0,66510.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.26 66523[138:Res:53.1,66512.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.26 66525[138:MRR:66523.0,65917.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.26 66527[138:Res:66525.0,61.1] always3(s37) || -> . % 76.04/76.26 66528[138:SSi:66527.0,726.0,65931.0,65943.0] || -> . % 76.04/76.26 66529[137:Spt:66528.0,66294.0,66295.0] || until2p7(s36)*+ -> . % 76.04/76.26 66530[137:Spt:66528.0,66294.1] || -> node4(s35)*. % 76.04/76.26 66531[137:MRR:65920.0,66530.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.26 66534[137:Res:53.1,66531.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.26 66537[137:Res:66534.0,61.1] always3(s35) || -> . % 76.04/76.26 66538[137:SSi:66537.0,724.0,65911.0,65926.0,66293.0,66530.0] || -> . % 76.04/76.26 66539[136:Spt:66538.0,66292.0,66293.0] || until2p7(s35)*+ -> . % 76.04/76.26 66540[136:Spt:66538.0,66292.1] || -> node4(s34)*. % 76.04/76.26 66542[136:MRR:816.0,66540.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.26 66554[136:Res:53.1,66542.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.26 66556[136:MRR:66554.0,65894.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.26 66558[136:Res:66556.0,61.1] always3(s35) || -> . % 76.04/76.26 66559[136:SSi:66558.0,724.0,65911.0,65926.0] || -> . % 76.04/76.26 66560[135:Spt:66559.0,66290.0,66291.0] || until2p7(s34)*+ -> . % 76.04/76.26 66561[135:Spt:66559.0,66290.1] || -> node4(s33)*. % 76.04/76.26 66562[135:MRR:65897.0,66561.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.26 66565[135:Res:53.1,66562.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.26 66568[135:Res:66565.0,61.1] always3(s33) || -> . % 76.04/76.26 66569[135:SSi:66568.0,722.0,65888.0,65900.0,66289.0,66561.0] || -> . % 76.04/76.26 66570[134:Spt:66569.0,66288.0,66289.0] || until2p7(s33)*+ -> . % 76.04/76.26 66571[134:Spt:66569.0,66288.1] || -> node4(s32)*. % 76.04/76.26 66573[134:MRR:822.0,66571.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.26 66585[134:Res:53.1,66573.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.26 66587[134:MRR:66585.0,65874.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.26 66592[134:Res:66587.0,61.1] always3(s33) || -> . % 76.04/76.26 66593[134:SSi:66592.0,722.0,65888.0,65900.0] || -> . % 76.04/76.26 66594[133:Spt:66593.0,66286.0,66287.0] || until2p7(s32)*+ -> . % 76.04/76.26 66595[133:Spt:66593.0,66286.1] || -> node4(s31)*. % 76.04/76.26 66596[133:MRR:65877.0,66595.0] || m_main_v_state(s31,c_ready)*+ -> . % 76.04/76.26 66599[133:Res:53.1,66596.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 66603[133:Res:66599.0,61.1] always3(s31) || -> . % 76.04/76.26 66604[133:SSi:66603.0,720.0,65865.0,65880.0,66285.0,66595.0] || -> . % 76.04/76.26 66605[132:Spt:66604.0,66284.0,66285.0] || until2p7(s31)*+ -> . % 76.04/76.26 66606[132:Spt:66604.0,66284.1] || -> node4(s30)*. % 76.04/76.26 66608[132:MRR:828.0,66606.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.26 66619[132:Res:53.1,66608.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.26 66621[133:Spt:66619.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 66623[133:Res:66621.0,61.1] always3(s30) || -> . % 76.04/76.26 66624[133:SSi:66623.0,719.0,65862.0,65864.0,66283.0,66606.0] || -> . % 76.04/76.26 66625[133:Spt:66624.0,66619.0,66621.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.26 66626[133:Spt:66624.0,66619.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 66630[133:Res:66626.0,61.1] always3(s31) || -> . % 76.04/76.26 66631[133:SSi:66630.0,720.0,65865.0,65880.0] || -> . % 76.04/76.26 66632[131:Spt:66631.0,66282.0,66283.0] || until2p7(s30)*+ -> . % 76.04/76.26 66633[131:Spt:66631.0,66282.1] || -> node4(s29)*. % 76.04/76.26 66635[131:MRR:831.0,66633.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.26 66642[131:Res:53.1,66635.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.26 66647[132:Spt:66642.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 66649[132:Res:66647.0,61.1] always3(s29) || -> . % 76.04/76.26 66650[132:SSi:66649.0,718.0,65856.0,65861.0,66281.0,66633.0] || -> . % 76.04/76.26 66651[132:Spt:66650.0,66642.0,66647.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.26 66652[132:Spt:66650.0,66642.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 66656[132:Res:66652.0,61.1] always3(s30) || -> . % 76.04/76.26 66657[132:SSi:66656.0,719.0,65862.0,65864.0] || -> . % 76.04/76.26 66658[130:Spt:66657.0,66280.0,66281.0] || until2p7(s29)*+ -> . % 76.04/76.26 66659[130:Spt:66657.0,66280.1] || -> node4(s28)*. % 76.04/76.26 66661[130:MRR:834.0,66659.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.26 66664[130:Res:53.1,66661.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.26 66666[131:Spt:66664.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 66668[131:Res:66666.0,61.1] always3(s28) || -> . % 76.04/76.26 66669[131:SSi:66668.0,717.0,65853.0,65855.0,66279.0,66659.0] || -> . % 76.04/76.26 66670[131:Spt:66669.0,66664.0,66666.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.26 66671[131:Spt:66669.0,66664.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 66675[131:Res:66671.0,61.1] always3(s29) || -> . % 76.04/76.26 66676[131:SSi:66675.0,718.0,65856.0,65861.0] || -> . % 76.04/76.26 66677[129:Spt:66676.0,66278.0,66279.0] || until2p7(s28)*+ -> . % 76.04/76.26 66678[129:Spt:66676.0,66278.1] || -> node4(s27)*. % 76.04/76.26 66680[129:MRR:837.0,66678.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.26 66683[129:Res:53.1,66680.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.26 66685[130:Spt:66683.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 66687[130:Res:66685.0,61.1] always3(s27) || -> . % 76.04/76.26 66688[130:SSi:66687.0,716.0,65847.0,65852.0,66277.0,66678.0] || -> . % 76.04/76.26 66689[130:Spt:66688.0,66683.0,66685.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.26 66690[130:Spt:66688.0,66683.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 66694[130:Res:66690.0,61.1] always3(s28) || -> . % 76.04/76.26 66695[130:SSi:66694.0,717.0,65853.0,65855.0] || -> . % 76.04/76.26 66696[128:Spt:66695.0,66276.0,66277.0] || until2p7(s27)*+ -> . % 76.04/76.26 66697[128:Spt:66695.0,66276.1] || -> node4(s26)*. % 76.04/76.26 66699[128:MRR:840.0,66697.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.26 66702[128:Res:53.1,66699.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.26 66704[129:Spt:66702.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 66706[129:Res:66704.0,61.1] always3(s26) || -> . % 76.04/76.26 66707[129:SSi:66706.0,715.0,65844.0,65846.0,66275.0,66697.0] || -> . % 76.04/76.26 66708[129:Spt:66707.0,66702.0,66704.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.26 66709[129:Spt:66707.0,66702.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 66713[129:Res:66709.0,61.1] always3(s27) || -> . % 76.04/76.26 66714[129:SSi:66713.0,716.0,65847.0,65852.0] || -> . % 76.04/76.26 66715[127:Spt:66714.0,66274.0,66275.0] || until2p7(s26)*+ -> . % 76.04/76.26 66716[127:Spt:66714.0,66274.1] || -> node4(s25)*. % 76.04/76.26 66718[127:MRR:843.0,66716.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.26 66721[127:Res:53.1,66718.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.26 66726[128:Spt:66721.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 66728[128:Res:66726.0,61.1] always3(s25) || -> . % 76.04/76.26 66729[128:SSi:66728.0,714.0,65838.0,65843.0,66273.0,66716.0] || -> . % 76.04/76.26 66730[128:Spt:66729.0,66721.0,66726.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.26 66731[128:Spt:66729.0,66721.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 66735[128:Res:66731.0,61.1] always3(s26) || -> . % 76.04/76.26 66736[128:SSi:66735.0,715.0,65844.0,65846.0] || -> . % 76.04/76.26 66737[126:Spt:66736.0,66272.0,66273.0] || until2p7(s25)*+ -> . % 76.04/76.26 66738[126:Spt:66736.0,66272.1] || -> node4(s24)*. % 76.04/76.26 66740[126:MRR:846.0,66738.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.26 66743[126:Res:53.1,66740.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.26 66745[127:Spt:66743.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 66747[127:Res:66745.0,61.1] always3(s24) || -> . % 76.04/76.26 66748[127:SSi:66747.0,713.0,65835.0,65837.0,66271.0,66738.0] || -> . % 76.04/76.26 66749[127:Spt:66748.0,66743.0,66745.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.26 66750[127:Spt:66748.0,66743.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 66754[127:Res:66750.0,61.1] always3(s25) || -> . % 76.04/76.26 66755[127:SSi:66754.0,714.0,65838.0,65843.0] || -> . % 76.04/76.26 66756[125:Spt:66755.0,66270.0,66271.0] || until2p7(s24)*+ -> . % 76.04/76.26 66757[125:Spt:66755.0,66270.1] || -> node4(s23)*. % 76.04/76.26 66759[125:MRR:849.0,66757.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.26 66762[125:Res:53.1,66759.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.26 66764[126:Spt:66762.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 66766[126:Res:66764.0,61.1] always3(s23) || -> . % 76.04/76.26 66767[126:SSi:66766.0,712.0,65829.0,65834.0,66269.0,66757.0] || -> . % 76.04/76.26 66768[126:Spt:66767.0,66762.0,66764.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.26 66769[126:Spt:66767.0,66762.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 66773[126:Res:66769.0,61.1] always3(s24) || -> . % 76.04/76.26 66774[126:SSi:66773.0,713.0,65835.0,65837.0] || -> . % 76.04/76.26 66775[124:Spt:66774.0,66268.0,66269.0] || until2p7(s23)*+ -> . % 76.04/76.26 66776[124:Spt:66774.0,66268.1] || -> node4(s22)*. % 76.04/76.26 66778[124:MRR:852.0,66776.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.26 66781[124:Res:53.1,66778.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.26 66783[125:Spt:66781.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 66785[125:Res:66783.0,61.1] always3(s22) || -> . % 76.04/76.26 66786[125:SSi:66785.0,711.0,65826.0,65828.0,66267.0,66776.0] || -> . % 76.04/76.26 66787[125:Spt:66786.0,66781.0,66783.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.26 66788[125:Spt:66786.0,66781.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 66792[125:Res:66788.0,61.1] always3(s23) || -> . % 76.04/76.26 66793[125:SSi:66792.0,712.0,65829.0,65834.0] || -> . % 76.04/76.26 66794[123:Spt:66793.0,66266.0,66267.0] || until2p7(s22)*+ -> . % 76.04/76.26 66795[123:Spt:66793.0,66266.1] || -> node4(s21)*. % 76.04/76.26 66797[123:MRR:855.0,66795.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.26 66800[123:Res:53.1,66797.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.26 66805[124:Spt:66800.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 66807[124:Res:66805.0,61.1] always3(s21) || -> . % 76.04/76.26 66808[124:SSi:66807.0,710.0,65820.0,65825.0,66265.0,66795.0] || -> . % 76.04/76.26 66809[124:Spt:66808.0,66800.0,66805.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.26 66810[124:Spt:66808.0,66800.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 66814[124:Res:66810.0,61.1] always3(s22) || -> . % 76.04/76.26 66815[124:SSi:66814.0,711.0,65826.0,65828.0] || -> . % 76.04/76.26 66816[122:Spt:66815.0,66264.0,66265.0] || until2p7(s21)*+ -> . % 76.04/76.26 66817[122:Spt:66815.0,66264.1] || -> node4(s20)*. % 76.04/76.26 66819[122:MRR:858.0,66817.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.26 66822[122:Res:53.1,66819.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.26 66824[123:Spt:66822.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 66826[123:Res:66824.0,61.1] always3(s20) || -> . % 76.04/76.26 66827[123:SSi:66826.0,709.0,65817.0,65819.0,66263.0,66817.0] || -> . % 76.04/76.26 66828[123:Spt:66827.0,66822.0,66824.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.26 66829[123:Spt:66827.0,66822.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 66833[123:Res:66829.0,61.1] always3(s21) || -> . % 76.04/76.26 66834[123:SSi:66833.0,710.0,65820.0,65825.0] || -> . % 76.04/76.26 66835[121:Spt:66834.0,66262.0,66263.0] || until2p7(s20)*+ -> . % 76.04/76.26 66836[121:Spt:66834.0,66262.1] || -> node4(s19)*. % 76.04/76.26 66838[121:MRR:861.0,66836.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.26 66841[121:Res:53.1,66838.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.26 66843[122:Spt:66841.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 66845[122:Res:66843.0,61.1] always3(s19) || -> . % 76.04/76.26 66846[122:SSi:66845.0,708.0,65811.0,65816.0,66261.0,66836.0] || -> . % 76.04/76.26 66847[122:Spt:66846.0,66841.0,66843.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.26 66848[122:Spt:66846.0,66841.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 66852[122:Res:66848.0,61.1] always3(s20) || -> . % 76.04/76.26 66853[122:SSi:66852.0,709.0,65817.0,65819.0] || -> . % 76.04/76.26 66854[120:Spt:66853.0,66260.0,66261.0] || until2p7(s19)*+ -> . % 76.04/76.26 66855[120:Spt:66853.0,66260.1] || -> node4(s18)*. % 76.04/76.26 66857[120:MRR:864.0,66855.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.26 66860[120:Res:53.1,66857.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.26 66862[121:Spt:66860.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 66864[121:Res:66862.0,61.1] always3(s18) || -> . % 76.04/76.26 66865[121:SSi:66864.0,707.0,65808.0,65810.0,66259.0,66855.0] || -> . % 76.04/76.26 66866[121:Spt:66865.0,66860.0,66862.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.26 66867[121:Spt:66865.0,66860.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 66871[121:Res:66867.0,61.1] always3(s19) || -> . % 76.04/76.26 66872[121:SSi:66871.0,708.0,65811.0,65816.0] || -> . % 76.04/76.26 66873[119:Spt:66872.0,66258.0,66259.0] || until2p7(s18)*+ -> . % 76.04/76.26 66874[119:Spt:66872.0,66258.1] || -> node4(s17)*. % 76.04/76.26 66876[119:MRR:867.0,66874.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.26 66879[119:Res:53.1,66876.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.26 66884[120:Spt:66879.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 66886[120:Res:66884.0,61.1] always3(s17) || -> . % 76.04/76.26 66887[120:SSi:66886.0,706.0,65802.0,65807.0,66257.0,66874.0] || -> . % 76.04/76.26 66888[120:Spt:66887.0,66879.0,66884.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.26 66889[120:Spt:66887.0,66879.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 66893[120:Res:66889.0,61.1] always3(s18) || -> . % 76.04/76.26 66894[120:SSi:66893.0,707.0,65808.0,65810.0] || -> . % 76.04/76.26 66895[118:Spt:66894.0,66256.0,66257.0] || until2p7(s17)*+ -> . % 76.04/76.26 66896[118:Spt:66894.0,66256.1] || -> node4(s16)*. % 76.04/76.26 66898[118:MRR:870.0,66896.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.26 66901[118:Res:53.1,66898.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.26 66903[119:Spt:66901.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 66905[119:Res:66903.0,61.1] always3(s16) || -> . % 76.04/76.26 66906[119:SSi:66905.0,705.0,65799.0,65801.0,66255.0,66896.0] || -> . % 76.04/76.26 66907[119:Spt:66906.0,66901.0,66903.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.26 66908[119:Spt:66906.0,66901.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 66912[119:Res:66908.0,61.1] always3(s17) || -> . % 76.04/76.26 66913[119:SSi:66912.0,706.0,65802.0,65807.0] || -> . % 76.04/76.26 66914[117:Spt:66913.0,66254.0,66255.0] || until2p7(s16)*+ -> . % 76.04/76.26 66915[117:Spt:66913.0,66254.1] || -> node4(s15)*. % 76.04/76.26 66917[117:MRR:873.0,66915.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.26 66920[117:Res:53.1,66917.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.26 66922[118:Spt:66920.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 66924[118:Res:66922.0,61.1] always3(s15) || -> . % 76.04/76.26 66925[118:SSi:66924.0,704.0,65793.0,65798.0,66253.0,66915.0] || -> . % 76.04/76.26 66926[118:Spt:66925.0,66920.0,66922.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.26 66927[118:Spt:66925.0,66920.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 66931[118:Res:66927.0,61.1] always3(s16) || -> . % 76.04/76.26 66932[118:SSi:66931.0,705.0,65799.0,65801.0] || -> . % 76.04/76.26 66933[116:Spt:66932.0,66252.0,66253.0] || until2p7(s15)*+ -> . % 76.04/76.26 66934[116:Spt:66932.0,66252.1] || -> node4(s14)*. % 76.04/76.26 66936[116:MRR:876.0,66934.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.26 66939[116:Res:53.1,66936.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.26 66941[117:Spt:66939.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 66943[117:Res:66941.0,61.1] always3(s14) || -> . % 76.04/76.26 66944[117:SSi:66943.0,703.0,65790.0,65792.0,66251.0,66934.0] || -> . % 76.04/76.26 66945[117:Spt:66944.0,66939.0,66941.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.26 66946[117:Spt:66944.0,66939.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 66950[117:Res:66946.0,61.1] always3(s15) || -> . % 76.04/76.26 66951[117:SSi:66950.0,704.0,65793.0,65798.0] || -> . % 76.04/76.26 66952[115:Spt:66951.0,66250.0,66251.0] || until2p7(s14)*+ -> . % 76.04/76.26 66953[115:Spt:66951.0,66250.1] || -> node4(s13)*. % 76.04/76.26 66955[115:MRR:879.0,66953.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.26 66958[115:Res:53.1,66955.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.26 66963[116:Spt:66958.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 66965[116:Res:66963.0,61.1] always3(s13) || -> . % 76.04/76.26 66966[116:SSi:66965.0,702.0,65784.0,65789.0,66249.0,66953.0] || -> . % 76.04/76.26 66967[116:Spt:66966.0,66958.0,66963.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.26 66968[116:Spt:66966.0,66958.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 66972[116:Res:66968.0,61.1] always3(s14) || -> . % 76.04/76.26 66973[116:SSi:66972.0,703.0,65790.0,65792.0] || -> . % 76.04/76.26 66974[114:Spt:66973.0,66248.0,66249.0] || until2p7(s13)*+ -> . % 76.04/76.26 66975[114:Spt:66973.0,66248.1] || -> node4(s12)*. % 76.04/76.26 66977[114:MRR:882.0,66975.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.26 66980[114:Res:53.1,66977.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.26 66982[115:Spt:66980.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 66984[115:Res:66982.0,61.1] always3(s12) || -> . % 76.04/76.26 66985[115:SSi:66984.0,701.0,65781.0,65783.0,66247.0,66975.0] || -> . % 76.04/76.26 66986[115:Spt:66985.0,66980.0,66982.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.26 66987[115:Spt:66985.0,66980.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 66991[115:Res:66987.0,61.1] always3(s13) || -> . % 76.04/76.26 66992[115:SSi:66991.0,702.0,65784.0,65789.0] || -> . % 76.04/76.26 66993[113:Spt:66992.0,66246.0,66247.0] || until2p7(s12)*+ -> . % 76.04/76.26 66994[113:Spt:66992.0,66246.1] || -> node4(s11)*. % 76.04/76.26 66996[113:MRR:885.0,66994.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.26 66999[113:Res:53.1,66996.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.26 67001[114:Spt:66999.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 67003[114:Res:67001.0,61.1] always3(s11) || -> . % 76.04/76.26 67004[114:SSi:67003.0,700.0,65775.0,65780.0,66245.0,66994.0] || -> . % 76.04/76.26 67005[114:Spt:67004.0,66999.0,67001.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.26 67006[114:Spt:67004.0,66999.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 67010[114:Res:67006.0,61.1] always3(s12) || -> . % 76.04/76.26 67011[114:SSi:67010.0,701.0,65781.0,65783.0] || -> . % 76.04/76.26 67012[112:Spt:67011.0,66244.0,66245.0] || until2p7(s11)*+ -> . % 76.04/76.26 67013[112:Spt:67011.0,66244.1] || -> node4(s10)*. % 76.04/76.26 67015[112:MRR:888.0,67013.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.26 67018[112:Res:53.1,67015.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.26 67020[113:Spt:67018.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 67022[113:Res:67020.0,61.1] always3(s10) || -> . % 76.04/76.26 67023[113:SSi:67022.0,699.0,65772.0,65774.0,66243.0,67013.0] || -> . % 76.04/76.26 67024[113:Spt:67023.0,67018.0,67020.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.26 67025[113:Spt:67023.0,67018.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 67029[113:Res:67025.0,61.1] always3(s11) || -> . % 76.04/76.26 67030[113:SSi:67029.0,700.0,65775.0,65780.0] || -> . % 76.04/76.26 67031[111:Spt:67030.0,66242.0,66243.0] || until2p7(s10)*+ -> . % 76.04/76.26 67032[111:Spt:67030.0,66242.1] || -> node4(s9)*. % 76.04/76.26 67034[111:MRR:891.0,67032.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.26 67037[111:Res:53.1,67034.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.26 67042[112:Spt:67037.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 67044[112:Res:67042.0,61.1] always3(s9) || -> . % 76.04/76.26 67045[112:SSi:67044.0,698.0,65766.0,65771.0,66241.0,67032.0] || -> . % 76.04/76.26 67046[112:Spt:67045.0,67037.0,67042.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.26 67047[112:Spt:67045.0,67037.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 67051[112:Res:67047.0,61.1] always3(s10) || -> . % 76.04/76.26 67052[112:SSi:67051.0,699.0,65772.0,65774.0] || -> . % 76.04/76.26 67053[110:Spt:67052.0,66240.0,66241.0] || until2p7(s9)*+ -> . % 76.04/76.26 67054[110:Spt:67052.0,66240.1] || -> node4(s8)*. % 76.04/76.26 67056[110:MRR:894.0,67054.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.26 67059[110:Res:53.1,67056.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.26 67061[111:Spt:67059.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 67063[111:Res:67061.0,61.1] always3(s8) || -> . % 76.04/76.26 67064[111:SSi:67063.0,697.0,65763.0,65765.0,66239.0,67054.0] || -> . % 76.04/76.26 67065[111:Spt:67064.0,67059.0,67061.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.26 67066[111:Spt:67064.0,67059.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 67070[111:Res:67066.0,61.1] always3(s9) || -> . % 76.04/76.26 67071[111:SSi:67070.0,698.0,65766.0,65771.0] || -> . % 76.04/76.26 67072[109:Spt:67071.0,66238.0,66239.0] || until2p7(s8)*+ -> . % 76.04/76.26 67073[109:Spt:67071.0,66238.1] || -> node4(s7)*. % 76.04/76.26 67075[109:MRR:897.0,67073.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.26 67078[109:Res:53.1,67075.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.26 67080[110:Spt:67078.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 67082[110:Res:67080.0,61.1] always3(s7) || -> . % 76.04/76.26 67083[110:SSi:67082.0,696.0,65757.0,65762.0,66237.0,67073.0] || -> . % 76.04/76.26 67084[110:Spt:67083.0,67078.0,67080.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.26 67085[110:Spt:67083.0,67078.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 67089[110:Res:67085.0,61.1] always3(s8) || -> . % 76.04/76.26 67090[110:SSi:67089.0,697.0,65763.0,65765.0] || -> . % 76.04/76.26 67091[108:Spt:67090.0,66236.0,66237.0] || until2p7(s7)*+ -> . % 76.04/76.26 67092[108:Spt:67090.0,66236.1] || -> node4(s6)*. % 76.04/76.26 67094[108:MRR:900.0,67092.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.26 67097[108:Res:53.1,67094.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.26 67099[109:Spt:67097.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 67101[109:Res:67099.0,61.1] always3(s6) || -> . % 76.04/76.26 67102[109:SSi:67101.0,695.0,65754.0,65756.0,66235.0,67092.0] || -> . % 76.04/76.26 67103[109:Spt:67102.0,67097.0,67099.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.26 67104[109:Spt:67102.0,67097.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 67108[109:Res:67104.0,61.1] always3(s7) || -> . % 76.04/76.26 67109[109:SSi:67108.0,696.0,65757.0,65762.0] || -> . % 76.04/76.26 67110[107:Spt:67109.0,66232.0,66235.0] || until2p7(s6)*+ -> . % 76.04/76.26 67111[107:Spt:67109.0,66232.1] || -> node4(s5)*. % 76.04/76.26 67113[107:MRR:903.0,67111.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.26 67116[107:Res:53.1,67113.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.26 67118[107:MRR:67116.0,66214.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 67123[107:Res:67118.0,61.1] always3(s6) || -> . % 76.04/76.26 67124[107:SSi:67123.0,695.0,65754.0,65756.0] || -> . % 76.04/76.26 67125[104:Spt:67124.0,66054.2,66056.0] || xuntil6(s48)*+ -> . % 76.04/76.26 67126[104:Spt:67124.0,66054.0,66054.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.26 67127[104:Res:53.1,67126.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.26 67129[104:MRR:67127.0,66043.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.26 67131[104:Res:67129.0,61.1] always3(s49) || -> . % 76.04/76.26 67132[104:SSi:67131.0,50.0,738.0] || -> . % 76.04/76.26 67133[103:Spt:67132.0,66047.1,66052.0] || xuntil6(s47)* -> . % 76.04/76.26 67134[103:Spt:67132.0,66047.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.26 67137[103:Res:67134.0,61.1] always3(s47) || -> . % 76.04/76.26 67138[103:SSi:67137.0,736.0,66037.0] || -> . % 76.04/76.26 67139[101:Spt:67138.0,66028.2,66036.0] || xuntil6(s46)*+ -> . % 76.04/76.26 67140[101:Spt:67138.0,66028.0,66028.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.26 67141[101:Res:53.1,67140.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.26 67143[101:MRR:67141.0,66020.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.26 67146[101:Res:67143.0,61.1] always3(s47) || -> . % 76.04/76.26 67147[101:SSi:67146.0,736.0] || -> . % 76.04/76.26 67148[100:Spt:67147.0,66024.1,66026.0] || xuntil6(s45)* -> . % 76.04/76.26 67149[100:Spt:67147.0,66024.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.26 67152[100:Res:67149.0,61.1] always3(s45) || -> . % 76.04/76.26 67153[100:SSi:67152.0,734.0,66014.0] || -> . % 76.04/76.26 67154[98:Spt:67153.0,66008.2,66013.0] || xuntil6(s44)*+ -> . % 76.04/76.26 67155[98:Spt:67153.0,66008.0,66008.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.26 67156[98:Res:53.1,67155.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.26 67158[98:MRR:67156.0,66000.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.26 67160[98:Res:67158.0,61.1] always3(s45) || -> . % 76.04/76.26 67161[98:SSi:67160.0,734.0] || -> . % 76.04/76.26 67162[97:Spt:67161.0,66004.1,66006.0] || xuntil6(s43)* -> . % 76.04/76.26 67163[97:Spt:67161.0,66004.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.26 67166[97:Res:67163.0,61.1] always3(s43) || -> . % 76.04/76.26 67167[97:SSi:67166.0,732.0,65994.0] || -> . % 76.04/76.26 67168[95:Spt:67167.0,65991.2,65993.0] || xuntil6(s42)*+ -> . % 76.04/76.26 67169[95:Spt:67167.0,65991.0,65991.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.26 67170[95:Res:53.1,67169.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.26 67172[95:MRR:67170.0,65980.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.26 67175[95:Res:67172.0,61.1] always3(s43) || -> . % 76.04/76.26 67176[95:SSi:67175.0,732.0] || -> . % 76.04/76.26 67177[94:Spt:67176.0,65984.1,65989.0] || xuntil6(s41)* -> . % 76.04/76.26 67178[94:Spt:67176.0,65984.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.26 67181[94:Res:67178.0,61.1] always3(s41) || -> . % 76.04/76.26 67182[94:SSi:67181.0,730.0,65974.0] || -> . % 76.04/76.26 67183[92:Spt:67182.0,65965.2,65973.0] || xuntil6(s40)*+ -> . % 76.04/76.26 67184[92:Spt:67182.0,65965.0,65965.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.26 67185[92:Res:53.1,67184.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.26 67187[92:MRR:67185.0,65957.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.26 67189[92:Res:67187.0,61.1] always3(s41) || -> . % 76.04/76.26 67190[92:SSi:67189.0,730.0] || -> . % 76.04/76.26 67191[91:Spt:67190.0,65961.1,65963.0] || xuntil6(s39)* -> . % 76.04/76.26 67192[91:Spt:67190.0,65961.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.26 67195[91:Res:67192.0,61.1] always3(s39) || -> . % 76.04/76.26 67196[91:SSi:67195.0,728.0,65951.0] || -> . % 76.04/76.26 67197[89:Spt:67196.0,65945.2,65950.0] || xuntil6(s38)*+ -> . % 76.04/76.26 67198[89:Spt:67196.0,65945.0,65945.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.26 67199[89:Res:53.1,67198.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.26 67201[89:MRR:67199.0,65937.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.26 67203[89:Res:67201.0,61.1] always3(s39) || -> . % 76.04/76.26 67204[89:SSi:67203.0,728.0] || -> . % 76.04/76.26 67205[88:Spt:67204.0,65941.1,65943.0] || xuntil6(s37)* -> . % 76.04/76.26 67206[88:Spt:67204.0,65941.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.26 67209[88:Res:67206.0,61.1] always3(s37) || -> . % 76.04/76.26 67210[88:SSi:67209.0,726.0,65931.0] || -> . % 76.04/76.26 67211[86:Spt:67210.0,65928.2,65930.0] || xuntil6(s36)*+ -> . % 76.04/76.26 67212[86:Spt:67210.0,65928.0,65928.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.26 67213[86:Res:53.1,67212.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.26 67215[86:MRR:67213.0,65917.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.26 67217[86:Res:67215.0,61.1] always3(s37) || -> . % 76.04/76.26 67218[86:SSi:67217.0,726.0] || -> . % 76.04/76.26 67219[85:Spt:67218.0,65921.1,65926.0] || xuntil6(s35)* -> . % 76.04/76.26 67220[85:Spt:67218.0,65921.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.26 67223[85:Res:67220.0,61.1] always3(s35) || -> . % 76.04/76.26 67224[85:SSi:67223.0,724.0,65911.0] || -> . % 76.04/76.26 67225[83:Spt:67224.0,65902.2,65910.0] || xuntil6(s34)*+ -> . % 76.04/76.26 67226[83:Spt:67224.0,65902.0,65902.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.26 67227[83:Res:53.1,67226.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.26 67229[83:MRR:67227.0,65894.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.26 67231[83:Res:67229.0,61.1] always3(s35) || -> . % 76.04/76.26 67232[83:SSi:67231.0,724.0] || -> . % 76.04/76.26 67233[82:Spt:67232.0,65898.1,65900.0] || xuntil6(s33)* -> . % 76.04/76.26 67234[82:Spt:67232.0,65898.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.26 67237[82:Res:67234.0,61.1] always3(s33) || -> . % 76.04/76.26 67238[82:SSi:67237.0,722.0,65888.0] || -> . % 76.04/76.26 67239[80:Spt:67238.0,65882.2,65887.0] || xuntil6(s32)*+ -> . % 76.04/76.26 67240[80:Spt:67238.0,65882.0,65882.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.26 67241[80:Res:53.1,67240.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.26 67243[80:MRR:67241.0,65874.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.26 67245[80:Res:67243.0,61.1] always3(s33) || -> . % 76.04/76.26 67246[80:SSi:67245.0,722.0] || -> . % 76.04/76.26 67247[79:Spt:67246.0,65878.1,65880.0] || xuntil6(s31)* -> . % 76.04/76.26 67248[79:Spt:67246.0,65878.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 67251[79:Res:67248.0,61.1] always3(s31) || -> . % 76.04/76.26 67252[79:SSi:67251.0,720.0,65865.0] || -> . % 76.04/76.26 67253[77:Spt:67252.0,65863.2,65864.0] || xuntil6(s30)*+ -> . % 76.04/76.26 67254[77:Spt:67252.0,65863.0,65863.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.26 67255[77:Res:53.1,67254.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.26 67257[78:Spt:67255.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 67259[78:Res:67257.0,61.1] always3(s31) || -> . % 76.04/76.26 67260[78:SSi:67259.0,720.0] || -> . % 76.04/76.26 67261[78:Spt:67260.0,67255.1,67257.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.26 67262[78:Spt:67260.0,67255.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 67265[78:Res:67262.0,61.1] always3(s30) || -> . % 76.04/76.26 67266[78:SSi:67265.0,719.0,65862.0] || -> . % 76.04/76.26 67267[76:Spt:67266.0,65857.2,65861.0] || xuntil6(s29)*+ -> . % 76.04/76.26 67268[76:Spt:67266.0,65857.0,65857.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.26 67269[76:Res:53.1,67268.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.26 67271[77:Spt:67269.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 67273[77:Res:67271.0,61.1] always3(s30) || -> . % 76.04/76.26 67274[77:SSi:67273.0,719.0] || -> . % 76.04/76.26 67275[77:Spt:67274.0,67269.1,67271.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.26 67276[77:Spt:67274.0,67269.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 67279[77:Res:67276.0,61.1] always3(s29) || -> . % 76.04/76.26 67280[77:SSi:67279.0,718.0,65856.0] || -> . % 76.04/76.26 67281[75:Spt:67280.0,65854.2,65855.0] || xuntil6(s28)*+ -> . % 76.04/76.26 67282[75:Spt:67280.0,65854.0,65854.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.26 67283[75:Res:53.1,67282.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.26 67285[76:Spt:67283.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 67287[76:Res:67285.0,61.1] always3(s29) || -> . % 76.04/76.26 67288[76:SSi:67287.0,718.0] || -> . % 76.04/76.26 67289[76:Spt:67288.0,67283.1,67285.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.26 67290[76:Spt:67288.0,67283.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 67293[76:Res:67290.0,61.1] always3(s28) || -> . % 76.04/76.26 67294[76:SSi:67293.0,717.0,65853.0] || -> . % 76.04/76.26 67295[74:Spt:67294.0,65848.2,65852.0] || xuntil6(s27)*+ -> . % 76.04/76.26 67296[74:Spt:67294.0,65848.0,65848.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.26 67297[74:Res:53.1,67296.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.26 67299[75:Spt:67297.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 67301[75:Res:67299.0,61.1] always3(s28) || -> . % 76.04/76.26 67302[75:SSi:67301.0,717.0] || -> . % 76.04/76.26 67303[75:Spt:67302.0,67297.1,67299.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.26 67304[75:Spt:67302.0,67297.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 67307[75:Res:67304.0,61.1] always3(s27) || -> . % 76.04/76.26 67308[75:SSi:67307.0,716.0,65847.0] || -> . % 76.04/76.26 67309[73:Spt:67308.0,65845.2,65846.0] || xuntil6(s26)*+ -> . % 76.04/76.26 67310[73:Spt:67308.0,65845.0,65845.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.26 67311[73:Res:53.1,67310.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.26 67313[74:Spt:67311.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 67315[74:Res:67313.0,61.1] always3(s27) || -> . % 76.04/76.26 67316[74:SSi:67315.0,716.0] || -> . % 76.04/76.26 67317[74:Spt:67316.0,67311.1,67313.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.26 67318[74:Spt:67316.0,67311.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 67321[74:Res:67318.0,61.1] always3(s26) || -> . % 76.04/76.26 67322[74:SSi:67321.0,715.0,65844.0] || -> . % 76.04/76.26 67323[72:Spt:67322.0,65839.2,65843.0] || xuntil6(s25)*+ -> . % 76.04/76.26 67324[72:Spt:67322.0,65839.0,65839.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.26 67325[72:Res:53.1,67324.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.26 67327[73:Spt:67325.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 67329[73:Res:67327.0,61.1] always3(s26) || -> . % 76.04/76.26 67330[73:SSi:67329.0,715.0] || -> . % 76.04/76.26 67331[73:Spt:67330.0,67325.1,67327.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.26 67332[73:Spt:67330.0,67325.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 67335[73:Res:67332.0,61.1] always3(s25) || -> . % 76.04/76.26 67336[73:SSi:67335.0,714.0,65838.0] || -> . % 76.04/76.26 67337[71:Spt:67336.0,65836.2,65837.0] || xuntil6(s24)*+ -> . % 76.04/76.26 67338[71:Spt:67336.0,65836.0,65836.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.26 67339[71:Res:53.1,67338.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.26 67341[72:Spt:67339.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 67343[72:Res:67341.0,61.1] always3(s25) || -> . % 76.04/76.26 67344[72:SSi:67343.0,714.0] || -> . % 76.04/76.26 67345[72:Spt:67344.0,67339.1,67341.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.26 67346[72:Spt:67344.0,67339.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 67349[72:Res:67346.0,61.1] always3(s24) || -> . % 76.04/76.26 67350[72:SSi:67349.0,713.0,65835.0] || -> . % 76.04/76.26 67351[70:Spt:67350.0,65830.2,65834.0] || xuntil6(s23)*+ -> . % 76.04/76.26 67352[70:Spt:67350.0,65830.0,65830.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.26 67353[70:Res:53.1,67352.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.26 67355[71:Spt:67353.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 67357[71:Res:67355.0,61.1] always3(s24) || -> . % 76.04/76.26 67358[71:SSi:67357.0,713.0] || -> . % 76.04/76.26 67359[71:Spt:67358.0,67353.1,67355.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.26 67360[71:Spt:67358.0,67353.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 67363[71:Res:67360.0,61.1] always3(s23) || -> . % 76.04/76.26 67364[71:SSi:67363.0,712.0,65829.0] || -> . % 76.04/76.26 67365[69:Spt:67364.0,65827.2,65828.0] || xuntil6(s22)*+ -> . % 76.04/76.26 67366[69:Spt:67364.0,65827.0,65827.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.26 67367[69:Res:53.1,67366.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.26 67369[70:Spt:67367.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 67371[70:Res:67369.0,61.1] always3(s23) || -> . % 76.04/76.26 67372[70:SSi:67371.0,712.0] || -> . % 76.04/76.26 67373[70:Spt:67372.0,67367.1,67369.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.26 67374[70:Spt:67372.0,67367.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 67377[70:Res:67374.0,61.1] always3(s22) || -> . % 76.04/76.26 67378[70:SSi:67377.0,711.0,65826.0] || -> . % 76.04/76.26 67379[68:Spt:67378.0,65821.2,65825.0] || xuntil6(s21)*+ -> . % 76.04/76.26 67380[68:Spt:67378.0,65821.0,65821.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.26 67381[68:Res:53.1,67380.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.26 67383[69:Spt:67381.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 67385[69:Res:67383.0,61.1] always3(s22) || -> . % 76.04/76.26 67386[69:SSi:67385.0,711.0] || -> . % 76.04/76.26 67387[69:Spt:67386.0,67381.1,67383.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.26 67388[69:Spt:67386.0,67381.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 67391[69:Res:67388.0,61.1] always3(s21) || -> . % 76.04/76.26 67392[69:SSi:67391.0,710.0,65820.0] || -> . % 76.04/76.26 67393[67:Spt:67392.0,65818.2,65819.0] || xuntil6(s20)*+ -> . % 76.04/76.26 67394[67:Spt:67392.0,65818.0,65818.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.26 67395[67:Res:53.1,67394.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.26 67400[68:Spt:67395.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 67402[68:Res:67400.0,61.1] always3(s20) || -> . % 76.04/76.26 67403[68:SSi:67402.0,709.0,65817.0] || -> . % 76.04/76.26 67404[68:Spt:67403.0,67395.0,67400.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.26 67405[68:Spt:67403.0,67395.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 67409[68:Res:67405.0,61.1] always3(s21) || -> . % 76.04/76.26 67410[68:SSi:67409.0,710.0] || -> . % 76.04/76.26 67411[66:Spt:67410.0,65812.2,65816.0] || xuntil6(s19)*+ -> . % 76.04/76.26 67412[66:Spt:67410.0,65812.0,65812.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.26 67413[66:Res:53.1,67412.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.26 67415[67:Spt:67413.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 67417[67:Res:67415.0,61.1] always3(s20) || -> . % 76.04/76.26 67418[67:SSi:67417.0,709.0] || -> . % 76.04/76.26 67419[67:Spt:67418.0,67413.1,67415.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.26 67420[67:Spt:67418.0,67413.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 67423[67:Res:67420.0,61.1] always3(s19) || -> . % 76.04/76.26 67424[67:SSi:67423.0,708.0,65811.0] || -> . % 76.04/76.26 67425[65:Spt:67424.0,65809.2,65810.0] || xuntil6(s18)*+ -> . % 76.04/76.26 67426[65:Spt:67424.0,65809.0,65809.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.26 67427[65:Res:53.1,67426.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.26 67429[66:Spt:67427.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 67431[66:Res:67429.0,61.1] always3(s19) || -> . % 76.04/76.26 67432[66:SSi:67431.0,708.0] || -> . % 76.04/76.26 67433[66:Spt:67432.0,67427.1,67429.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.26 67434[66:Spt:67432.0,67427.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 67437[66:Res:67434.0,61.1] always3(s18) || -> . % 76.04/76.26 67438[66:SSi:67437.0,707.0,65808.0] || -> . % 76.04/76.26 67439[64:Spt:67438.0,65803.2,65807.0] || xuntil6(s17)*+ -> . % 76.04/76.26 67440[64:Spt:67438.0,65803.0,65803.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.26 67441[64:Res:53.1,67440.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.26 67446[65:Spt:67441.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 67448[65:Res:67446.0,61.1] always3(s17) || -> . % 76.04/76.26 67449[65:SSi:67448.0,706.0,65802.0] || -> . % 76.04/76.26 67450[65:Spt:67449.0,67441.0,67446.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.26 67451[65:Spt:67449.0,67441.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 67455[65:Res:67451.0,61.1] always3(s18) || -> . % 76.04/76.26 67456[65:SSi:67455.0,707.0] || -> . % 76.04/76.26 67457[63:Spt:67456.0,65800.2,65801.0] || xuntil6(s16)*+ -> . % 76.04/76.26 67458[63:Spt:67456.0,65800.0,65800.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.26 67459[63:Res:53.1,67458.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.26 67461[64:Spt:67459.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 67463[64:Res:67461.0,61.1] always3(s17) || -> . % 76.04/76.26 67464[64:SSi:67463.0,706.0] || -> . % 76.04/76.26 67465[64:Spt:67464.0,67459.1,67461.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.26 67466[64:Spt:67464.0,67459.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 67469[64:Res:67466.0,61.1] always3(s16) || -> . % 76.04/76.26 67470[64:SSi:67469.0,705.0,65799.0] || -> . % 76.04/76.26 67471[62:Spt:67470.0,65794.2,65798.0] || xuntil6(s15)*+ -> . % 76.04/76.26 67472[62:Spt:67470.0,65794.0,65794.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.26 67473[62:Res:53.1,67472.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.26 67475[63:Spt:67473.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 67477[63:Res:67475.0,61.1] always3(s16) || -> . % 76.04/76.26 67478[63:SSi:67477.0,705.0] || -> . % 76.04/76.26 67479[63:Spt:67478.0,67473.1,67475.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.26 67480[63:Spt:67478.0,67473.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 67483[63:Res:67480.0,61.1] always3(s15) || -> . % 76.04/76.26 67484[63:SSi:67483.0,704.0,65793.0] || -> . % 76.04/76.26 67485[61:Spt:67484.0,65791.2,65792.0] || xuntil6(s14)*+ -> . % 76.04/76.26 67486[61:Spt:67484.0,65791.0,65791.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.26 67487[61:Res:53.1,67486.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.26 67492[62:Spt:67487.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 67494[62:Res:67492.0,61.1] always3(s14) || -> . % 76.04/76.26 67495[62:SSi:67494.0,703.0,65790.0] || -> . % 76.04/76.26 67496[62:Spt:67495.0,67487.0,67492.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.26 67497[62:Spt:67495.0,67487.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 67501[62:Res:67497.0,61.1] always3(s15) || -> . % 76.04/76.26 67502[62:SSi:67501.0,704.0] || -> . % 76.04/76.26 67503[60:Spt:67502.0,65785.2,65789.0] || xuntil6(s13)*+ -> . % 76.04/76.26 67504[60:Spt:67502.0,65785.0,65785.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.26 67505[60:Res:53.1,67504.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.26 67507[61:Spt:67505.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 67509[61:Res:67507.0,61.1] always3(s14) || -> . % 76.04/76.26 67510[61:SSi:67509.0,703.0] || -> . % 76.04/76.26 67511[61:Spt:67510.0,67505.1,67507.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.26 67512[61:Spt:67510.0,67505.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 67515[61:Res:67512.0,61.1] always3(s13) || -> . % 76.04/76.26 67516[61:SSi:67515.0,702.0,65784.0] || -> . % 76.04/76.26 67517[59:Spt:67516.0,65782.2,65783.0] || xuntil6(s12)*+ -> . % 76.04/76.26 67518[59:Spt:67516.0,65782.0,65782.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.26 67519[59:Res:53.1,67518.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.26 67521[60:Spt:67519.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 67523[60:Res:67521.0,61.1] always3(s13) || -> . % 76.04/76.26 67524[60:SSi:67523.0,702.0] || -> . % 76.04/76.26 67525[60:Spt:67524.0,67519.1,67521.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.26 67526[60:Spt:67524.0,67519.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 67529[60:Res:67526.0,61.1] always3(s12) || -> . % 76.04/76.26 67530[60:SSi:67529.0,701.0,65781.0] || -> . % 76.04/76.26 67531[58:Spt:67530.0,65776.2,65780.0] || xuntil6(s11)*+ -> . % 76.04/76.26 67532[58:Spt:67530.0,65776.0,65776.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.26 67533[58:Res:53.1,67532.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.26 67538[59:Spt:67533.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 67540[59:Res:67538.0,61.1] always3(s11) || -> . % 76.04/76.26 67541[59:SSi:67540.0,700.0,65775.0] || -> . % 76.04/76.26 67542[59:Spt:67541.0,67533.0,67538.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.26 67543[59:Spt:67541.0,67533.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 67547[59:Res:67543.0,61.1] always3(s12) || -> . % 76.04/76.26 67548[59:SSi:67547.0,701.0] || -> . % 76.04/76.26 67549[57:Spt:67548.0,65773.2,65774.0] || xuntil6(s10)*+ -> . % 76.04/76.26 67550[57:Spt:67548.0,65773.0,65773.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.26 67551[57:Res:53.1,67550.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.26 67553[58:Spt:67551.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 67555[58:Res:67553.0,61.1] always3(s11) || -> . % 76.04/76.26 67556[58:SSi:67555.0,700.0] || -> . % 76.04/76.26 67557[58:Spt:67556.0,67551.1,67553.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.26 67558[58:Spt:67556.0,67551.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 67561[58:Res:67558.0,61.1] always3(s10) || -> . % 76.04/76.26 67562[58:SSi:67561.0,699.0,65772.0] || -> . % 76.04/76.26 67563[56:Spt:67562.0,65767.2,65771.0] || xuntil6(s9)*+ -> . % 76.04/76.26 67564[56:Spt:67562.0,65767.0,65767.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.26 67565[56:Res:53.1,67564.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.26 67567[57:Spt:67565.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 67569[57:Res:67567.0,61.1] always3(s10) || -> . % 76.04/76.26 67570[57:SSi:67569.0,699.0] || -> . % 76.04/76.26 67571[57:Spt:67570.0,67565.1,67567.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.26 67572[57:Spt:67570.0,67565.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 67575[57:Res:67572.0,61.1] always3(s9) || -> . % 76.04/76.26 67576[57:SSi:67575.0,698.0,65766.0] || -> . % 76.04/76.26 67577[55:Spt:67576.0,65764.2,65765.0] || xuntil6(s8)*+ -> . % 76.04/76.26 67578[55:Spt:67576.0,65764.0,65764.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.26 67579[55:Res:53.1,67578.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.26 67584[56:Spt:67579.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 67586[56:Res:67584.0,61.1] always3(s8) || -> . % 76.04/76.26 67587[56:SSi:67586.0,697.0,65763.0] || -> . % 76.04/76.26 67588[56:Spt:67587.0,67579.0,67584.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.26 67589[56:Spt:67587.0,67579.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 67593[56:Res:67589.0,61.1] always3(s9) || -> . % 76.04/76.26 67594[56:SSi:67593.0,698.0] || -> . % 76.04/76.26 67595[54:Spt:67594.0,65758.2,65762.0] || xuntil6(s7)*+ -> . % 76.04/76.26 67596[54:Spt:67594.0,65758.0,65758.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.26 67597[54:Res:53.1,67596.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.26 67599[55:Spt:67597.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 67601[55:Res:67599.0,61.1] always3(s8) || -> . % 76.04/76.26 67602[55:SSi:67601.0,697.0] || -> . % 76.04/76.26 67603[55:Spt:67602.0,67597.1,67599.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.26 67604[55:Spt:67602.0,67597.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 67607[55:Res:67604.0,61.1] always3(s7) || -> . % 76.04/76.26 67608[55:SSi:67607.0,696.0,65757.0] || -> . % 76.04/76.26 67609[53:Spt:67608.0,65755.2,65756.0] || xuntil6(s6)*+ -> . % 76.04/76.26 67610[53:Spt:67608.0,65755.0,65755.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.26 67611[53:Res:53.1,67610.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.26 67613[54:Spt:67611.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 67615[54:Res:67613.0,61.1] always3(s7) || -> . % 76.04/76.26 67616[54:SSi:67615.0,696.0] || -> . % 76.04/76.26 67617[54:Spt:67616.0,67611.1,67613.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.26 67618[54:Spt:67616.0,67611.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 67621[54:Res:67618.0,61.1] always3(s6) || -> . % 76.04/76.26 67622[54:SSi:67621.0,695.0,65754.0] || -> . % 76.04/76.26 67623[52:Spt:67622.0,65749.2,65753.0] || xuntil6(s5)*+ -> . % 76.04/76.26 67624[52:Spt:67622.0,65749.0,65749.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.26 67625[52:Res:53.1,67624.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.26 67630[53:Spt:67625.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.26 67632[53:Res:67630.0,61.1] always3(s5) || -> . % 76.04/76.26 67633[53:SSi:67632.0,694.0,65748.0] || -> . % 76.04/76.26 67634[53:Spt:67633.0,67625.0,67630.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.26 67635[53:Spt:67633.0,67625.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 67642[53:Res:67635.0,61.1] always3(s6) || -> . % 76.04/76.26 67643[53:SSi:67642.0,695.0] || -> . % 76.04/76.26 67644[51:Spt:67643.0,65746.2,65747.0] || xuntil6(s4)*+ -> . % 76.04/76.26 67645[51:Spt:67643.0,65746.0,65746.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.26 67646[51:Res:53.1,67645.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.26 67648[52:Spt:67646.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.26 67650[52:Res:67648.0,61.1] always3(s4) || -> . % 76.04/76.26 67651[52:SSi:67650.0,693.0,65745.0] || -> . % 76.04/76.26 67652[52:Spt:67651.0,67646.0,67648.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.26 67653[52:Spt:67651.0,67646.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.26 67657[52:Res:67653.0,61.1] always3(s5) || -> . % 76.04/76.26 67658[52:SSi:67657.0,694.0] || -> . % 76.04/76.26 67659[50:Spt:67658.0,65740.2,65744.0] || xuntil6(s3)*+ -> . % 76.04/76.26 67660[50:Spt:67658.0,65740.0,65740.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.26 67661[50:Res:53.1,67660.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.26 67663[51:Spt:67661.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.26 67665[51:Res:67663.0,61.1] always3(s3) || -> . % 76.04/76.26 67666[51:SSi:67665.0,692.0,65739.0] || -> . % 76.04/76.26 67667[51:Spt:67666.0,67661.0,67663.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.26 67668[51:Spt:67666.0,67661.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.26 67672[51:Res:67668.0,61.1] always3(s4) || -> . % 76.04/76.26 67673[51:SSi:67672.0,693.0] || -> . % 76.04/76.26 67674[49:Spt:67673.0,65737.2,65738.0] || xuntil6(s2)*+ -> . % 76.04/76.26 67675[49:Spt:67673.0,65737.0,65737.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.26 67676[49:Res:53.1,67675.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.26 67681[50:Spt:67676.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.26 67683[50:Res:67681.0,61.1] always3(s2) || -> . % 76.04/76.26 67684[50:SSi:67683.0,691.0,65736.0] || -> . % 76.04/76.26 67685[50:Spt:67684.0,67676.0,67681.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.26 67686[50:Spt:67684.0,67676.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.26 67690[50:Res:67686.0,61.1] always3(s3) || -> . % 76.04/76.26 67691[50:SSi:67690.0,692.0] || -> . % 76.04/76.26 67692[48:Spt:67691.0,65728.2,65735.0] || xuntil6(s1)*+ -> . % 76.04/76.26 67693[48:Spt:67691.0,65728.0,65728.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.26 67694[48:Res:53.1,67693.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.26 67696[49:Spt:67694.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.26 67698[49:Res:67696.0,61.1] always3(s1) || -> . % 76.04/76.26 67699[49:SSi:67698.0,690.0,65727.0] || -> . % 76.04/76.26 67700[49:Spt:67699.0,67694.0,67696.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.26 67701[49:Spt:67699.0,67694.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.26 67706[49:Res:67701.0,61.1] always3(s2) || -> . % 76.04/76.26 67707[49:SSi:67706.0,691.0] || -> . % 76.04/76.26 67708[47:Spt:67707.0,74.0,65726.0] || xuntil6(s0)*+ -> . % 76.04/76.26 67709[47:Spt:67707.0,74.1] || -> node4(s0)*. % 76.04/76.26 67710[47:MRR:758.1,67708.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.26 67712[47:Res:67710.0,61.1] always3(s1) || -> . % 76.04/76.26 67713[47:SSi:67712.0,690.0] || -> . % 76.04/76.26 67714[46:Spt:67713.0,65716.0,65720.0] || trans(s49,s5)*+ -> . % 76.04/76.26 67715[46:Spt:67713.0,65716.1,65716.2,65716.3,65716.4,65716.5] || -> trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.26 67717[46:MRR:65718.0,67714.0] || -> trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.26 67718[46:MRR:65719.1,67714.0] xuntil6(s49) || -> trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.26 67719[47:Spt:67715.0] || -> trans(s49,s4)*. % 76.04/76.26 67720[47:Res:67719.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s4)*. % 76.04/76.26 67722[47:Res:67719.0,60.0] || -> node2(s49,s4)*. % 76.04/76.26 67723[47:SSi:67720.1,50.0,738.0] xuntil6(s49) || -> until2p7(s4)*. % 76.04/76.26 67724[47:Res:67722.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s4,c_busy)*. % 76.04/76.26 67725[48:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.26 67726[48:MRR:176.0,67725.0] || -> until5(s1)*. % 76.04/76.26 67727[48:MRR:66168.0,67726.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.26 67734[49:Spt:67727.2] || -> xuntil6(s1)*. % 76.04/76.26 67735[49:MRR:175.0,67734.0] || -> until5(s2)*. % 76.04/76.26 67736[49:MRR:66167.0,67735.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.26 67737[50:Spt:67736.2] || -> xuntil6(s2)*. % 76.04/76.26 67738[50:MRR:174.0,67737.0] || -> until5(s3)*. % 76.04/76.26 67739[50:MRR:66160.0,67738.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.26 67743[51:Spt:67739.2] || -> xuntil6(s3)*. % 76.04/76.26 67744[51:MRR:173.0,67743.0] || -> until5(s4)*. % 76.04/76.26 67745[51:MRR:66156.0,67744.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.26 67746[52:Spt:67745.2] || -> xuntil6(s4)*. % 76.04/76.26 67747[52:MRR:172.0,67746.0] || -> until5(s5)*. % 76.04/76.26 67748[52:MRR:66152.0,67747.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.26 67752[53:Spt:67748.2] || -> xuntil6(s5)*. % 76.04/76.26 67753[53:MRR:171.0,67752.0] || -> until5(s6)*. % 76.04/76.26 67754[53:MRR:66148.0,67753.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.26 67755[54:Spt:67754.2] || -> xuntil6(s6)*. % 76.04/76.26 67756[54:MRR:170.0,67755.0] || -> until5(s7)*. % 76.04/76.26 67757[54:MRR:66141.0,67756.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.26 67761[55:Spt:67757.2] || -> xuntil6(s7)*. % 76.04/76.26 67762[55:MRR:169.0,67761.0] || -> until5(s8)*. % 76.04/76.26 67763[55:MRR:66137.0,67762.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.26 67764[56:Spt:67763.2] || -> xuntil6(s8)*. % 76.04/76.26 67765[56:MRR:168.0,67764.0] || -> until5(s9)*. % 76.04/76.26 67766[56:MRR:66136.0,67765.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.26 67770[57:Spt:67766.2] || -> xuntil6(s9)*. % 76.04/76.26 67771[57:MRR:167.0,67770.0] || -> until5(s10)*. % 76.04/76.26 67772[57:MRR:66132.0,67771.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.26 67773[58:Spt:67772.2] || -> xuntil6(s10)*. % 76.04/76.26 67774[58:MRR:166.0,67773.0] || -> until5(s11)*. % 76.04/76.26 67775[58:MRR:66125.0,67774.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.26 67779[59:Spt:67775.2] || -> xuntil6(s11)*. % 76.04/76.26 67780[59:MRR:165.0,67779.0] || -> until5(s12)*. % 76.04/76.26 67781[59:MRR:66121.0,67780.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.26 67782[60:Spt:67781.2] || -> xuntil6(s12)*. % 76.04/76.26 67783[60:MRR:164.0,67782.0] || -> until5(s13)*. % 76.04/76.26 67784[60:MRR:66120.0,67783.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.26 67788[61:Spt:67784.2] || -> xuntil6(s13)*. % 76.04/76.26 67789[61:MRR:163.0,67788.0] || -> until5(s14)*. % 76.04/76.26 67790[61:MRR:66116.0,67789.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.26 67791[62:Spt:67790.2] || -> xuntil6(s14)*. % 76.04/76.26 67792[62:MRR:162.0,67791.0] || -> until5(s15)*. % 76.04/76.26 67793[62:MRR:66109.0,67792.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.26 67797[63:Spt:67793.2] || -> xuntil6(s15)*. % 76.04/76.26 67798[63:MRR:161.0,67797.0] || -> until5(s16)*. % 76.04/76.26 67799[63:MRR:66108.0,67798.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.26 67800[64:Spt:67799.2] || -> xuntil6(s16)*. % 76.04/76.26 67801[64:MRR:160.0,67800.0] || -> until5(s17)*. % 76.04/76.26 67802[64:MRR:66101.0,67801.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.26 67806[65:Spt:67802.2] || -> xuntil6(s17)*. % 76.04/76.26 67807[65:MRR:159.0,67806.0] || -> until5(s18)*. % 76.04/76.26 67808[65:MRR:66097.0,67807.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.26 67809[66:Spt:67808.2] || -> xuntil6(s18)*. % 76.04/76.26 67810[66:MRR:158.0,67809.0] || -> until5(s19)*. % 76.04/76.26 67811[66:MRR:66096.0,67810.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.26 67815[67:Spt:67811.2] || -> xuntil6(s19)*. % 76.04/76.26 67816[67:MRR:157.0,67815.0] || -> until5(s20)*. % 76.04/76.26 67817[67:MRR:66089.0,67816.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.26 67818[68:Spt:67817.2] || -> xuntil6(s20)*. % 76.04/76.26 67819[68:MRR:156.0,67818.0] || -> until5(s21)*. % 76.04/76.26 67820[68:MRR:66088.0,67819.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.26 67824[69:Spt:67820.2] || -> xuntil6(s21)*. % 76.04/76.26 67825[69:MRR:155.0,67824.0] || -> until5(s22)*. % 76.04/76.26 67826[69:MRR:66087.0,67825.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.26 67827[70:Spt:67826.2] || -> xuntil6(s22)*. % 76.04/76.26 67828[70:MRR:154.0,67827.0] || -> until5(s23)*. % 76.04/76.26 67829[70:MRR:66077.0,67828.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.26 67833[71:Spt:67829.2] || -> xuntil6(s23)*. % 76.04/76.26 67834[71:MRR:153.0,67833.0] || -> until5(s24)*. % 76.04/76.26 67835[71:MRR:66076.0,67834.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.26 67836[72:Spt:67835.2] || -> xuntil6(s24)*. % 76.04/76.26 67837[72:MRR:152.0,67836.0] || -> until5(s25)*. % 76.04/76.26 67838[72:MRR:66069.0,67837.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.26 67842[73:Spt:67838.2] || -> xuntil6(s25)*. % 76.04/76.26 67843[73:MRR:151.0,67842.0] || -> until5(s26)*. % 76.04/76.26 67844[73:MRR:66065.0,67843.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.26 67845[74:Spt:67844.2] || -> xuntil6(s26)*. % 76.04/76.26 67846[74:MRR:150.0,67845.0] || -> until5(s27)*. % 76.04/76.26 67847[74:MRR:66061.0,67846.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.26 67851[75:Spt:67847.2] || -> xuntil6(s27)*. % 76.04/76.26 67852[75:MRR:149.0,67851.0] || -> until5(s28)*. % 76.04/76.26 67853[75:MRR:66060.0,67852.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.26 67854[76:Spt:67853.2] || -> xuntil6(s28)*. % 76.04/76.26 67855[76:MRR:148.0,67854.0] || -> until5(s29)*. % 76.04/76.26 67856[76:MRR:66059.0,67855.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.26 67860[77:Spt:67856.2] || -> xuntil6(s29)*. % 76.04/76.26 67861[77:MRR:147.0,67860.0] || -> until5(s30)*. % 76.04/76.26 67862[77:MRR:66058.0,67861.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.26 67863[78:Spt:67862.2] || -> xuntil6(s30)*. % 76.04/76.26 67864[78:MRR:146.0,67863.0] || -> until5(s31)*. % 76.04/76.26 67865[78:MRR:64058.0,67864.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.26 67869[79:Spt:67865.2] || -> xuntil6(s31)*. % 76.04/76.26 67870[79:MRR:145.0,67869.0] || -> until5(s32)*. % 76.04/76.26 67871[79:MRR:66178.0,67870.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.26 67872[80:Spt:67871.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.26 67874[80:Res:67872.0,61.1] always3(s33) || -> . % 76.04/76.26 67875[80:SSi:67874.0,722.0] || -> . % 76.04/76.26 67876[80:Spt:67875.0,67871.1,67872.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.04/76.26 67877[80:Spt:67875.0,67871.0,67871.2] || m_main_v_state(s32,c_ready)*+ -> xuntil6(s32). % 76.04/76.26 67879[80:MRR:822.2,67876.0] node4(s32) || m_main_v_state(s32,c_ready)* -> . % 76.04/76.26 67880[80:Res:53.1,67877.0] || -> m_main_v_state(s32,c_busy)* xuntil6(s32). % 76.04/76.26 67885[81:Spt:67880.1] || -> xuntil6(s32)*. % 76.04/76.26 67886[81:MRR:144.0,67885.0] || -> until5(s33)*. % 76.04/76.26 67887[81:MRR:62224.0,67886.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.26 67889[82:Spt:67887.2] || -> xuntil6(s33)*. % 76.04/76.26 67890[82:MRR:143.0,67889.0] || -> until5(s34)*. % 76.04/76.26 67891[82:MRR:66179.0,67890.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.26 67892[83:Spt:67891.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.26 67894[83:Res:67892.0,61.1] always3(s35) || -> . % 76.04/76.26 67895[83:SSi:67894.0,724.0] || -> . % 76.04/76.26 67896[83:Spt:67895.0,67891.1,67892.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.04/76.26 67897[83:Spt:67895.0,67891.0,67891.2] || m_main_v_state(s34,c_ready)*+ -> xuntil6(s34). % 76.04/76.26 67899[83:MRR:816.2,67896.0] node4(s34) || m_main_v_state(s34,c_ready)* -> . % 76.04/76.26 67900[83:Res:53.1,67897.0] || -> m_main_v_state(s34,c_busy)* xuntil6(s34). % 76.04/76.26 67902[84:Spt:67900.1] || -> xuntil6(s34)*. % 76.04/76.26 67903[84:MRR:142.0,67902.0] || -> until5(s35)*. % 76.04/76.26 67904[84:MRR:62231.0,67903.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.26 67909[85:Spt:67904.2] || -> xuntil6(s35)*. % 76.04/76.26 67910[85:MRR:141.0,67909.0] || -> until5(s36)*. % 76.04/76.26 67911[85:MRR:66183.0,67910.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.26 67912[86:Spt:67911.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.26 67914[86:Res:67912.0,61.1] always3(s37) || -> . % 76.04/76.26 67915[86:SSi:67914.0,726.0] || -> . % 76.04/76.26 67916[86:Spt:67915.0,67911.1,67912.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.04/76.26 67917[86:Spt:67915.0,67911.0,67911.2] || m_main_v_state(s36,c_ready)*+ -> xuntil6(s36). % 76.04/76.26 67919[86:MRR:810.2,67916.0] node4(s36) || m_main_v_state(s36,c_ready)* -> . % 76.04/76.26 67920[86:Res:53.1,67917.0] || -> m_main_v_state(s36,c_busy)* xuntil6(s36). % 76.04/76.26 67922[87:Spt:67920.1] || -> xuntil6(s36)*. % 76.04/76.26 67923[87:MRR:140.0,67922.0] || -> until5(s37)*. % 76.04/76.26 67924[87:MRR:62232.0,67923.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.26 67932[88:Spt:67924.2] || -> xuntil6(s37)*. % 76.04/76.26 67933[88:MRR:139.0,67932.0] || -> until5(s38)*. % 76.04/76.26 67934[88:MRR:66187.0,67933.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.26 67935[89:Spt:67934.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.26 67937[89:Res:67935.0,61.1] always3(s39) || -> . % 76.04/76.26 67938[89:SSi:67937.0,728.0] || -> . % 76.04/76.26 67939[89:Spt:67938.0,67934.1,67935.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.04/76.26 67940[89:Spt:67938.0,67934.0,67934.2] || m_main_v_state(s38,c_ready)*+ -> xuntil6(s38). % 76.04/76.26 67942[89:MRR:804.2,67939.0] node4(s38) || m_main_v_state(s38,c_ready)* -> . % 76.04/76.26 67943[89:Res:53.1,67940.0] || -> m_main_v_state(s38,c_busy)* xuntil6(s38). % 76.04/76.26 67948[90:Spt:67943.1] || -> xuntil6(s38)*. % 76.04/76.26 67949[90:MRR:138.0,67948.0] || -> until5(s39)*. % 76.04/76.26 67950[90:MRR:62236.0,67949.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.26 67952[91:Spt:67950.2] || -> xuntil6(s39)*. % 76.04/76.26 67953[91:MRR:137.0,67952.0] || -> until5(s40)*. % 76.04/76.26 67954[91:MRR:66191.0,67953.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.26 67955[92:Spt:67954.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.26 67957[92:Res:67955.0,61.1] always3(s41) || -> . % 76.04/76.26 67958[92:SSi:67957.0,730.0] || -> . % 76.04/76.26 67959[92:Spt:67958.0,67954.1,67955.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.04/76.26 67960[92:Spt:67958.0,67954.0,67954.2] || m_main_v_state(s40,c_ready)*+ -> xuntil6(s40). % 76.04/76.26 67962[92:MRR:798.2,67959.0] node4(s40) || m_main_v_state(s40,c_ready)* -> . % 76.04/76.26 67963[92:Res:53.1,67960.0] || -> m_main_v_state(s40,c_busy)* xuntil6(s40). % 76.04/76.26 67965[93:Spt:67963.1] || -> xuntil6(s40)*. % 76.04/76.26 67966[93:MRR:136.0,67965.0] || -> until5(s41)*. % 76.04/76.26 67967[93:MRR:62240.0,67966.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.26 67972[94:Spt:67967.2] || -> xuntil6(s41)*. % 76.04/76.26 67973[94:MRR:135.0,67972.0] || -> until5(s42)*. % 76.04/76.26 67974[94:MRR:66198.0,67973.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.26 67975[95:Spt:67974.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.26 67977[95:Res:67975.0,61.1] always3(s43) || -> . % 76.04/76.26 67978[95:SSi:67977.0,732.0] || -> . % 76.04/76.26 67979[95:Spt:67978.0,67974.1,67975.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.04/76.26 67980[95:Spt:67978.0,67974.0,67974.2] || m_main_v_state(s42,c_ready)*+ -> xuntil6(s42). % 76.04/76.26 67982[95:MRR:792.2,67979.0] node4(s42) || m_main_v_state(s42,c_ready)* -> . % 76.04/76.26 67983[95:Res:53.1,67980.0] || -> m_main_v_state(s42,c_busy)* xuntil6(s42). % 76.04/76.26 67985[96:Spt:67983.1] || -> xuntil6(s42)*. % 76.04/76.26 67986[96:MRR:134.0,67985.0] || -> until5(s43)*. % 76.04/76.26 67987[96:MRR:62244.0,67986.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.26 67995[97:Spt:67987.2] || -> xuntil6(s43)*. % 76.04/76.26 67996[97:MRR:133.0,67995.0] || -> until5(s44)*. % 76.04/76.26 67997[97:MRR:66199.0,67996.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.26 67998[98:Spt:67997.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.26 68000[98:Res:67998.0,61.1] always3(s45) || -> . % 76.04/76.26 68001[98:SSi:68000.0,734.0] || -> . % 76.04/76.26 68002[98:Spt:68001.0,67997.1,67998.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.04/76.26 68003[98:Spt:68001.0,67997.0,67997.2] || m_main_v_state(s44,c_ready)*+ -> xuntil6(s44). % 76.04/76.26 68005[98:MRR:786.2,68002.0] node4(s44) || m_main_v_state(s44,c_ready)* -> . % 76.04/76.26 68006[98:Res:53.1,68003.0] || -> m_main_v_state(s44,c_busy)* xuntil6(s44). % 76.04/76.26 68011[99:Spt:68006.1] || -> xuntil6(s44)*. % 76.04/76.26 68012[99:MRR:132.0,68011.0] || -> until5(s45)*. % 76.04/76.26 68013[99:MRR:62251.0,68012.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.26 68015[100:Spt:68013.2] || -> xuntil6(s45)*. % 76.04/76.26 68016[100:MRR:131.0,68015.0] || -> until5(s46)*. % 76.04/76.26 68017[100:MRR:66203.0,68016.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.26 68018[101:Spt:68017.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.26 68020[101:Res:68018.0,61.1] always3(s47) || -> . % 76.04/76.26 68021[101:SSi:68020.0,736.0] || -> . % 76.04/76.26 68022[101:Spt:68021.0,68017.1,68018.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.04/76.26 68023[101:Spt:68021.0,68017.0,68017.2] || m_main_v_state(s46,c_ready)*+ -> xuntil6(s46). % 76.04/76.26 68025[101:MRR:780.2,68022.0] node4(s46) || m_main_v_state(s46,c_ready)* -> . % 76.04/76.26 68026[101:Res:53.1,68023.0] || -> m_main_v_state(s46,c_busy)* xuntil6(s46). % 76.04/76.26 68028[102:Spt:68026.1] || -> xuntil6(s46)*. % 76.04/76.26 68029[102:MRR:130.0,68028.0] || -> until5(s47)*. % 76.04/76.26 68030[102:MRR:62252.0,68029.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.26 68035[103:Spt:68030.2] || -> xuntil6(s47)*. % 76.04/76.26 68036[103:MRR:129.0,68035.0] || -> until5(s48)*. % 76.04/76.26 68037[103:MRR:66207.0,68036.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.26 68038[104:Spt:68037.1] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.26 68040[104:Res:68038.0,61.1] always3(s49) || -> . % 76.04/76.26 68041[104:SSi:68040.0,50.0,738.0] || -> . % 76.04/76.26 68042[104:Spt:68041.0,68037.1,68038.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.26 68043[104:Spt:68041.0,68037.0,68037.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 76.04/76.26 68045[104:MRR:774.2,68042.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.26 68046[104:Res:53.1,68043.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 76.04/76.26 68048[105:Spt:68046.1] || -> xuntil6(s48)*. % 76.04/76.26 68049[105:MRR:128.0,68048.0] || -> until5(s49)*. % 76.04/76.26 68057[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.26 68058[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.26 68059[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.26 68060[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.26 68064[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.26 68068[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.26 68075[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.26 68076[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.26 68080[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.26 68084[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.26 68088[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.26 68095[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.26 68099[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.26 68100[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.26 68104[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.26 68111[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.26 68115[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.26 68116[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.26 68126[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.26 68127[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.26 68128[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.26 68135[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.26 68136[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.26 68140[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.26 68147[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.26 68148[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.26 68155[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.26 68159[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.26 68166[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.26 68167[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.26 68171[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.26 68175[0:SoR:819.0,66.2] until5(s33) || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.26 68179[0:SoR:813.0,66.2] until5(s35) || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.26 68186[0:SoR:807.0,66.2] until5(s37) || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.26 68187[0:SoR:801.0,66.2] until5(s39) || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.26 68191[0:SoR:795.0,66.2] until5(s41) || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.26 68195[0:SoR:789.0,66.2] until5(s43) || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.26 68199[0:SoR:783.0,66.2] until5(s45) || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.26 68203[0:SoR:777.0,66.2] until5(s47) || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.26 68205[47:SoR:67724.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s4,c_busy)*. % 76.04/76.26 68207[47:SoR:68205.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s4,c_busy)* xuntil6(s49). % 76.04/76.26 68208[105:SSi:68207.0,50.0,738.0,68049.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s4,c_busy)* xuntil6(s49). % 76.04/76.26 68209[106:Spt:68208.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.26 68211[106:Res:68209.0,61.1] always3(s4) || -> . % 76.04/76.26 68212[106:SSi:68211.0,693.0,67744.0,67746.0] || -> . % 76.04/76.26 68213[106:Spt:68212.0,68208.1,68209.0] || m_main_v_state(s4,c_busy)*+ -> . % 76.04/76.26 68214[106:Spt:68212.0,68208.0,68208.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.26 68218[106:MRR:68205.2,68213.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.26 68219[106:Res:53.1,68214.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.26 68221[106:MRR:68219.0,68042.0] || -> xuntil6(s49)*. % 76.04/76.26 68222[106:MRR:67723.0,68221.0] || -> until2p7(s4)*. % 76.04/76.26 68223[106:MRR:200.0,68222.0] || -> until2p7(s5)* node4(s4). % 76.04/76.26 68224[107:Spt:68223.0] || -> until2p7(s5)*. % 76.04/76.26 68225[107:MRR:201.0,68224.0] || -> until2p7(s6)* node4(s5). % 76.04/76.26 68226[108:Spt:68225.0] || -> until2p7(s6)*. % 76.04/76.26 68227[108:MRR:202.0,68226.0] || -> until2p7(s7)* node4(s6). % 76.04/76.26 68228[109:Spt:68227.0] || -> until2p7(s7)*. % 76.04/76.26 68229[109:MRR:203.0,68228.0] || -> until2p7(s8)* node4(s7). % 76.04/76.26 68230[110:Spt:68229.0] || -> until2p7(s8)*. % 76.04/76.26 68231[110:MRR:204.0,68230.0] || -> until2p7(s9)* node4(s8). % 76.04/76.26 68232[111:Spt:68231.0] || -> until2p7(s9)*. % 76.04/76.26 68233[111:MRR:205.0,68232.0] || -> until2p7(s10)* node4(s9). % 76.04/76.26 68234[112:Spt:68233.0] || -> until2p7(s10)*. % 76.04/76.26 68235[112:MRR:206.0,68234.0] || -> until2p7(s11)* node4(s10). % 76.04/76.26 68236[113:Spt:68235.0] || -> until2p7(s11)*. % 76.04/76.26 68237[113:MRR:207.0,68236.0] || -> until2p7(s12)* node4(s11). % 76.04/76.26 68238[114:Spt:68237.0] || -> until2p7(s12)*. % 76.04/76.26 68239[114:MRR:208.0,68238.0] || -> until2p7(s13)* node4(s12). % 76.04/76.26 68240[115:Spt:68239.0] || -> until2p7(s13)*. % 76.04/76.26 68241[115:MRR:209.0,68240.0] || -> until2p7(s14)* node4(s13). % 76.04/76.26 68242[116:Spt:68241.0] || -> until2p7(s14)*. % 76.04/76.26 68243[116:MRR:210.0,68242.0] || -> until2p7(s15)* node4(s14). % 76.04/76.26 68244[117:Spt:68243.0] || -> until2p7(s15)*. % 76.04/76.26 68245[117:MRR:211.0,68244.0] || -> until2p7(s16)* node4(s15). % 76.04/76.26 68246[118:Spt:68245.0] || -> until2p7(s16)*. % 76.04/76.26 68247[118:MRR:212.0,68246.0] || -> until2p7(s17)* node4(s16). % 76.04/76.26 68248[119:Spt:68247.0] || -> until2p7(s17)*. % 76.04/76.26 68249[119:MRR:213.0,68248.0] || -> until2p7(s18)* node4(s17). % 76.04/76.26 68250[120:Spt:68249.0] || -> until2p7(s18)*. % 76.04/76.26 68251[120:MRR:214.0,68250.0] || -> until2p7(s19)* node4(s18). % 76.04/76.26 68252[121:Spt:68251.0] || -> until2p7(s19)*. % 76.04/76.26 68253[121:MRR:215.0,68252.0] || -> until2p7(s20)* node4(s19). % 76.04/76.26 68254[122:Spt:68253.0] || -> until2p7(s20)*. % 76.04/76.26 68255[122:MRR:216.0,68254.0] || -> until2p7(s21)* node4(s20). % 76.04/76.26 68256[123:Spt:68255.0] || -> until2p7(s21)*. % 76.04/76.26 68257[123:MRR:217.0,68256.0] || -> until2p7(s22)* node4(s21). % 76.04/76.26 68258[124:Spt:68257.0] || -> until2p7(s22)*. % 76.04/76.26 68259[124:MRR:218.0,68258.0] || -> until2p7(s23)* node4(s22). % 76.04/76.26 68260[125:Spt:68259.0] || -> until2p7(s23)*. % 76.04/76.26 68261[125:MRR:219.0,68260.0] || -> until2p7(s24)* node4(s23). % 76.04/76.26 68262[126:Spt:68261.0] || -> until2p7(s24)*. % 76.04/76.26 68263[126:MRR:220.0,68262.0] || -> until2p7(s25)* node4(s24). % 76.04/76.26 68264[127:Spt:68263.0] || -> until2p7(s25)*. % 76.04/76.26 68265[127:MRR:221.0,68264.0] || -> until2p7(s26)* node4(s25). % 76.04/76.26 68266[128:Spt:68265.0] || -> until2p7(s26)*. % 76.04/76.26 68267[128:MRR:222.0,68266.0] || -> until2p7(s27)* node4(s26). % 76.04/76.26 68268[129:Spt:68267.0] || -> until2p7(s27)*. % 76.04/76.26 68269[129:MRR:223.0,68268.0] || -> until2p7(s28)* node4(s27). % 76.04/76.26 68270[130:Spt:68269.0] || -> until2p7(s28)*. % 76.04/76.26 68271[130:MRR:224.0,68270.0] || -> until2p7(s29)* node4(s28). % 76.04/76.26 68272[131:Spt:68271.0] || -> until2p7(s29)*. % 76.04/76.26 68273[131:MRR:225.0,68272.0] || -> until2p7(s30)* node4(s29). % 76.04/76.26 68274[132:Spt:68273.0] || -> until2p7(s30)*. % 76.04/76.26 68275[132:MRR:226.0,68274.0] || -> until2p7(s31)* node4(s30). % 76.04/76.26 68276[133:Spt:68275.0] || -> until2p7(s31)*. % 76.04/76.26 68277[133:MRR:227.0,68276.0] || -> until2p7(s32)* node4(s31). % 76.04/76.26 68278[134:Spt:68277.0] || -> until2p7(s32)*. % 76.04/76.26 68279[134:MRR:228.0,68278.0] || -> until2p7(s33)* node4(s32). % 76.04/76.26 68280[135:Spt:68279.0] || -> until2p7(s33)*. % 76.04/76.26 68281[135:MRR:229.0,68280.0] || -> until2p7(s34)* node4(s33). % 76.04/76.26 68282[136:Spt:68281.0] || -> until2p7(s34)*. % 76.04/76.26 68283[136:MRR:230.0,68282.0] || -> until2p7(s35)* node4(s34). % 76.04/76.26 68284[137:Spt:68283.0] || -> until2p7(s35)*. % 76.04/76.26 68285[137:MRR:231.0,68284.0] || -> until2p7(s36)* node4(s35). % 76.04/76.26 68286[138:Spt:68285.0] || -> until2p7(s36)*. % 76.04/76.26 68287[138:MRR:232.0,68286.0] || -> until2p7(s37)* node4(s36). % 76.04/76.26 68288[139:Spt:68287.0] || -> until2p7(s37)*. % 76.04/76.26 68289[139:MRR:235.0,68288.0] || -> until2p7(s38)* node4(s37). % 76.04/76.26 68290[140:Spt:68289.0] || -> until2p7(s38)*. % 76.04/76.26 68291[140:MRR:236.0,68290.0] || -> until2p7(s39)* node4(s38). % 76.04/76.26 68292[141:Spt:68291.0] || -> until2p7(s39)*. % 76.04/76.26 68293[141:MRR:237.0,68292.0] || -> until2p7(s40)* node4(s39). % 76.04/76.26 68294[142:Spt:68293.0] || -> until2p7(s40)*. % 76.04/76.26 68295[142:MRR:238.0,68294.0] || -> until2p7(s41)* node4(s40). % 76.04/76.26 68296[143:Spt:68295.0] || -> until2p7(s41)*. % 76.04/76.26 68297[143:MRR:239.0,68296.0] || -> until2p7(s42)* node4(s41). % 76.04/76.26 68298[144:Spt:68297.0] || -> until2p7(s42)*. % 76.04/76.26 68299[144:MRR:240.0,68298.0] || -> until2p7(s43)* node4(s42). % 76.04/76.26 68300[145:Spt:68299.0] || -> until2p7(s43)*. % 76.04/76.26 68301[145:MRR:241.0,68300.0] || -> until2p7(s44)* node4(s43). % 76.04/76.26 68302[146:Spt:68301.0] || -> until2p7(s44)*. % 76.04/76.26 68303[146:MRR:539.0,68302.0] || -> until2p7(s45)* node4(s44). % 76.04/76.26 68304[147:Spt:68303.0] || -> until2p7(s45)*. % 76.04/76.26 68305[147:MRR:544.0,68304.0] || -> until2p7(s46)* node4(s45). % 76.04/76.26 68306[148:Spt:68305.0] || -> until2p7(s46)*. % 76.04/76.26 68307[148:MRR:549.0,68306.0] || -> until2p7(s47)* node4(s46). % 76.04/76.26 68308[149:Spt:68307.0] || -> until2p7(s47)*. % 76.04/76.26 68309[149:MRR:554.0,68308.0] || -> until2p7(s48)* node4(s47). % 76.04/76.26 68310[150:Spt:68309.0] || -> until2p7(s48)*. % 76.04/76.26 68311[150:MRR:559.0,68310.0] || -> until2p7(s49)* node4(s48). % 76.04/76.26 68312[151:Spt:68311.0] || -> until2p7(s49)*. % 76.04/76.26 68313[151:MRR:194.0,68312.0] || -> node4(s49)*. % 76.04/76.26 68314[151:MRR:68218.0,68313.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.26 68315[151:Res:53.1,68314.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.26 68317[151:MRR:68315.0,68042.0] || -> . % 76.04/76.26 68318[151:Spt:68317.0,68311.0,68312.0] || until2p7(s49)*+ -> . % 76.04/76.26 68319[151:Spt:68317.0,68311.1] || -> node4(s48)*. % 76.04/76.26 68320[151:MRR:68045.0,68319.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.26 68323[151:Res:53.1,68320.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.26 68326[151:Res:68323.0,61.1] always3(s48) || -> . % 76.04/76.26 68327[151:SSi:68326.0,737.0,68036.0,68048.0,68310.0,68319.0] || -> . % 76.04/76.26 68328[150:Spt:68327.0,68309.0,68310.0] || until2p7(s48)*+ -> . % 76.04/76.26 68329[150:Spt:68327.0,68309.1] || -> node4(s47)*. % 76.04/76.26 68331[150:MRR:777.0,68329.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.26 68346[150:Res:53.1,68331.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.26 68348[150:MRR:68346.0,68022.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.26 68353[150:Res:68348.0,61.1] always3(s48) || -> . % 76.04/76.26 68354[150:SSi:68353.0,737.0,68036.0,68048.0] || -> . % 76.04/76.26 68355[149:Spt:68354.0,68307.0,68308.0] || until2p7(s47)*+ -> . % 76.04/76.26 68356[149:Spt:68354.0,68307.1] || -> node4(s46)*. % 76.04/76.26 68357[149:MRR:68025.0,68356.0] || m_main_v_state(s46,c_ready)*+ -> . % 76.04/76.26 68360[149:Res:53.1,68357.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.26 68364[149:Res:68360.0,61.1] always3(s46) || -> . % 76.04/76.26 68365[149:SSi:68364.0,735.0,68016.0,68028.0,68306.0,68356.0] || -> . % 76.04/76.26 68366[148:Spt:68365.0,68305.0,68306.0] || until2p7(s46)*+ -> . % 76.04/76.26 68367[148:Spt:68365.0,68305.1] || -> node4(s45)*. % 76.04/76.26 68369[148:MRR:783.0,68367.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.26 68380[148:Res:53.1,68369.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.26 68382[148:MRR:68380.0,68002.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.26 68384[148:Res:68382.0,61.1] always3(s46) || -> . % 76.04/76.26 68385[148:SSi:68384.0,735.0,68016.0,68028.0] || -> . % 76.04/76.26 68386[147:Spt:68385.0,68303.0,68304.0] || until2p7(s45)*+ -> . % 76.04/76.26 68387[147:Spt:68385.0,68303.1] || -> node4(s44)*. % 76.04/76.26 68388[147:MRR:68005.0,68387.0] || m_main_v_state(s44,c_ready)*+ -> . % 76.04/76.26 68392[147:Res:53.1,68388.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.26 68395[147:Res:68392.0,61.1] always3(s44) || -> . % 76.04/76.26 68396[147:SSi:68395.0,733.0,67996.0,68011.0,68302.0,68387.0] || -> . % 76.04/76.26 68397[146:Spt:68396.0,68301.0,68302.0] || until2p7(s44)*+ -> . % 76.04/76.26 68398[146:Spt:68396.0,68301.1] || -> node4(s43)*. % 76.04/76.26 68400[146:MRR:789.0,68398.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.26 68411[146:Res:53.1,68400.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.26 68413[146:MRR:68411.0,67979.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.26 68415[146:Res:68413.0,61.1] always3(s44) || -> . % 76.04/76.26 68416[146:SSi:68415.0,733.0,67996.0,68011.0] || -> . % 76.04/76.26 68417[145:Spt:68416.0,68299.0,68300.0] || until2p7(s43)*+ -> . % 76.04/76.26 68418[145:Spt:68416.0,68299.1] || -> node4(s42)*. % 76.04/76.26 68419[145:MRR:67982.0,68418.0] || m_main_v_state(s42,c_ready)*+ -> . % 76.04/76.26 68422[145:Res:53.1,68419.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.26 68425[145:Res:68422.0,61.1] always3(s42) || -> . % 76.04/76.26 68426[145:SSi:68425.0,731.0,67973.0,67985.0,68298.0,68418.0] || -> . % 76.04/76.26 68427[144:Spt:68426.0,68297.0,68298.0] || until2p7(s42)*+ -> . % 76.04/76.26 68428[144:Spt:68426.0,68297.1] || -> node4(s41)*. % 76.04/76.26 68430[144:MRR:795.0,68428.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.26 68442[144:Res:53.1,68430.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.26 68444[144:MRR:68442.0,67959.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.26 68446[144:Res:68444.0,61.1] always3(s42) || -> . % 76.04/76.26 68447[144:SSi:68446.0,731.0,67973.0,67985.0] || -> . % 76.04/76.26 68448[143:Spt:68447.0,68295.0,68296.0] || until2p7(s41)*+ -> . % 76.04/76.26 68449[143:Spt:68447.0,68295.1] || -> node4(s40)*. % 76.04/76.26 68450[143:MRR:67962.0,68449.0] || m_main_v_state(s40,c_ready)*+ -> . % 76.04/76.26 68453[143:Res:53.1,68450.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.26 68456[143:Res:68453.0,61.1] always3(s40) || -> . % 76.04/76.26 68457[143:SSi:68456.0,729.0,67953.0,67965.0,68294.0,68449.0] || -> . % 76.04/76.26 68458[142:Spt:68457.0,68293.0,68294.0] || until2p7(s40)*+ -> . % 76.04/76.26 68459[142:Spt:68457.0,68293.1] || -> node4(s39)*. % 76.04/76.26 68461[142:MRR:801.0,68459.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.26 68473[142:Res:53.1,68461.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.26 68475[142:MRR:68473.0,67939.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.26 68480[142:Res:68475.0,61.1] always3(s40) || -> . % 76.04/76.26 68481[142:SSi:68480.0,729.0,67953.0,67965.0] || -> . % 76.04/76.26 68482[141:Spt:68481.0,68291.0,68292.0] || until2p7(s39)*+ -> . % 76.04/76.26 68483[141:Spt:68481.0,68291.1] || -> node4(s38)*. % 76.04/76.26 68484[141:MRR:67942.0,68483.0] || m_main_v_state(s38,c_ready)*+ -> . % 76.04/76.26 68487[141:Res:53.1,68484.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.26 68491[141:Res:68487.0,61.1] always3(s38) || -> . % 76.04/76.26 68492[141:SSi:68491.0,727.0,67933.0,67948.0,68290.0,68483.0] || -> . % 76.04/76.26 68493[140:Spt:68492.0,68289.0,68290.0] || until2p7(s38)*+ -> . % 76.04/76.26 68494[140:Spt:68492.0,68289.1] || -> node4(s37)*. % 76.04/76.26 68496[140:MRR:807.0,68494.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.26 68507[140:Res:53.1,68496.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.26 68509[140:MRR:68507.0,67916.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.26 68511[140:Res:68509.0,61.1] always3(s38) || -> . % 76.04/76.26 68512[140:SSi:68511.0,727.0,67933.0,67948.0] || -> . % 76.04/76.26 68513[139:Spt:68512.0,68287.0,68288.0] || until2p7(s37)*+ -> . % 76.04/76.26 68514[139:Spt:68512.0,68287.1] || -> node4(s36)*. % 76.04/76.26 68515[139:MRR:67919.0,68514.0] || m_main_v_state(s36,c_ready)*+ -> . % 76.04/76.26 68519[139:Res:53.1,68515.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.26 68522[139:Res:68519.0,61.1] always3(s36) || -> . % 76.04/76.26 68523[139:SSi:68522.0,725.0,67910.0,67922.0,68286.0,68514.0] || -> . % 76.04/76.26 68524[138:Spt:68523.0,68285.0,68286.0] || until2p7(s36)*+ -> . % 76.04/76.26 68525[138:Spt:68523.0,68285.1] || -> node4(s35)*. % 76.04/76.26 68527[138:MRR:813.0,68525.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.26 68538[138:Res:53.1,68527.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.26 68540[138:MRR:68538.0,67896.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.26 68542[138:Res:68540.0,61.1] always3(s36) || -> . % 76.04/76.26 68543[138:SSi:68542.0,725.0,67910.0,67922.0] || -> . % 76.04/76.26 68544[137:Spt:68543.0,68283.0,68284.0] || until2p7(s35)*+ -> . % 76.04/76.26 68545[137:Spt:68543.0,68283.1] || -> node4(s34)*. % 76.04/76.26 68546[137:MRR:67899.0,68545.0] || m_main_v_state(s34,c_ready)*+ -> . % 76.04/76.26 68549[137:Res:53.1,68546.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.26 68552[137:Res:68549.0,61.1] always3(s34) || -> . % 76.04/76.26 68553[137:SSi:68552.0,723.0,67890.0,67902.0,68282.0,68545.0] || -> . % 76.04/76.26 68554[136:Spt:68553.0,68281.0,68282.0] || until2p7(s34)*+ -> . % 76.04/76.26 68555[136:Spt:68553.0,68281.1] || -> node4(s33)*. % 76.04/76.26 68557[136:MRR:819.0,68555.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.26 68569[136:Res:53.1,68557.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.26 68571[136:MRR:68569.0,67876.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.26 68573[136:Res:68571.0,61.1] always3(s34) || -> . % 76.04/76.26 68574[136:SSi:68573.0,723.0,67890.0,67902.0] || -> . % 76.04/76.26 68575[135:Spt:68574.0,68279.0,68280.0] || until2p7(s33)*+ -> . % 76.04/76.26 68576[135:Spt:68574.0,68279.1] || -> node4(s32)*. % 76.04/76.26 68577[135:MRR:67879.0,68576.0] || m_main_v_state(s32,c_ready)*+ -> . % 76.04/76.26 68580[135:Res:53.1,68577.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.26 68583[135:Res:68580.0,61.1] always3(s32) || -> . % 76.04/76.26 68584[135:SSi:68583.0,721.0,67870.0,67885.0,68278.0,68576.0] || -> . % 76.04/76.26 68585[134:Spt:68584.0,68277.0,68278.0] || until2p7(s32)*+ -> . % 76.04/76.26 68586[134:Spt:68584.0,68277.1] || -> node4(s31)*. % 76.04/76.26 68588[134:MRR:825.0,68586.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.26 68600[134:Res:53.1,68588.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.26 68605[135:Spt:68600.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 68607[135:Res:68605.0,61.1] always3(s31) || -> . % 76.04/76.26 68608[135:SSi:68607.0,720.0,67864.0,67869.0,68276.0,68586.0] || -> . % 76.04/76.26 68609[135:Spt:68608.0,68600.0,68605.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.26 68610[135:Spt:68608.0,68600.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.26 68614[135:Res:68610.0,61.1] always3(s32) || -> . % 76.04/76.26 68615[135:SSi:68614.0,721.0,67870.0,67885.0] || -> . % 76.04/76.26 68616[133:Spt:68615.0,68275.0,68276.0] || until2p7(s31)*+ -> . % 76.04/76.26 68617[133:Spt:68615.0,68275.1] || -> node4(s30)*. % 76.04/76.26 68619[133:MRR:828.0,68617.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.26 68626[133:Res:53.1,68619.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.26 68628[134:Spt:68626.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 68630[134:Res:68628.0,61.1] always3(s30) || -> . % 76.04/76.26 68631[134:SSi:68630.0,719.0,67861.0,67863.0,68274.0,68617.0] || -> . % 76.04/76.26 68632[134:Spt:68631.0,68626.0,68628.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.26 68633[134:Spt:68631.0,68626.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 68637[134:Res:68633.0,61.1] always3(s31) || -> . % 76.04/76.26 68638[134:SSi:68637.0,720.0,67864.0,67869.0] || -> . % 76.04/76.26 68639[132:Spt:68638.0,68273.0,68274.0] || until2p7(s30)*+ -> . % 76.04/76.26 68640[132:Spt:68638.0,68273.1] || -> node4(s29)*. % 76.04/76.26 68642[132:MRR:831.0,68640.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.26 68645[132:Res:53.1,68642.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.26 68650[133:Spt:68645.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 68652[133:Res:68650.0,61.1] always3(s29) || -> . % 76.04/76.26 68653[133:SSi:68652.0,718.0,67855.0,67860.0,68272.0,68640.0] || -> . % 76.04/76.26 68654[133:Spt:68653.0,68645.0,68650.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.26 68655[133:Spt:68653.0,68645.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 68659[133:Res:68655.0,61.1] always3(s30) || -> . % 76.04/76.26 68660[133:SSi:68659.0,719.0,67861.0,67863.0] || -> . % 76.04/76.26 68661[131:Spt:68660.0,68271.0,68272.0] || until2p7(s29)*+ -> . % 76.04/76.26 68662[131:Spt:68660.0,68271.1] || -> node4(s28)*. % 76.04/76.26 68664[131:MRR:834.0,68662.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.26 68667[131:Res:53.1,68664.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.26 68669[132:Spt:68667.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 68671[132:Res:68669.0,61.1] always3(s28) || -> . % 76.04/76.26 68672[132:SSi:68671.0,717.0,67852.0,67854.0,68270.0,68662.0] || -> . % 76.04/76.26 68673[132:Spt:68672.0,68667.0,68669.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.26 68674[132:Spt:68672.0,68667.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 68678[132:Res:68674.0,61.1] always3(s29) || -> . % 76.04/76.26 68679[132:SSi:68678.0,718.0,67855.0,67860.0] || -> . % 76.04/76.26 68680[130:Spt:68679.0,68269.0,68270.0] || until2p7(s28)*+ -> . % 76.04/76.26 68681[130:Spt:68679.0,68269.1] || -> node4(s27)*. % 76.04/76.26 68683[130:MRR:837.0,68681.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.26 68686[130:Res:53.1,68683.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.26 68688[131:Spt:68686.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 68690[131:Res:68688.0,61.1] always3(s27) || -> . % 76.04/76.26 68691[131:SSi:68690.0,716.0,67846.0,67851.0,68268.0,68681.0] || -> . % 76.04/76.26 68692[131:Spt:68691.0,68686.0,68688.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.26 68693[131:Spt:68691.0,68686.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 68697[131:Res:68693.0,61.1] always3(s28) || -> . % 76.04/76.26 68698[131:SSi:68697.0,717.0,67852.0,67854.0] || -> . % 76.04/76.26 68699[129:Spt:68698.0,68267.0,68268.0] || until2p7(s27)*+ -> . % 76.04/76.26 68700[129:Spt:68698.0,68267.1] || -> node4(s26)*. % 76.04/76.26 68702[129:MRR:840.0,68700.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.26 68705[129:Res:53.1,68702.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.26 68707[130:Spt:68705.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 68709[130:Res:68707.0,61.1] always3(s26) || -> . % 76.04/76.26 68710[130:SSi:68709.0,715.0,67843.0,67845.0,68266.0,68700.0] || -> . % 76.04/76.26 68711[130:Spt:68710.0,68705.0,68707.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.26 68712[130:Spt:68710.0,68705.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 68716[130:Res:68712.0,61.1] always3(s27) || -> . % 76.04/76.26 68717[130:SSi:68716.0,716.0,67846.0,67851.0] || -> . % 76.04/76.26 68718[128:Spt:68717.0,68265.0,68266.0] || until2p7(s26)*+ -> . % 76.04/76.26 68719[128:Spt:68717.0,68265.1] || -> node4(s25)*. % 76.04/76.26 68721[128:MRR:843.0,68719.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.26 68724[128:Res:53.1,68721.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.26 68729[129:Spt:68724.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 68731[129:Res:68729.0,61.1] always3(s25) || -> . % 76.04/76.26 68732[129:SSi:68731.0,714.0,67837.0,67842.0,68264.0,68719.0] || -> . % 76.04/76.26 68733[129:Spt:68732.0,68724.0,68729.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.26 68734[129:Spt:68732.0,68724.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 68738[129:Res:68734.0,61.1] always3(s26) || -> . % 76.04/76.26 68739[129:SSi:68738.0,715.0,67843.0,67845.0] || -> . % 76.04/76.26 68740[127:Spt:68739.0,68263.0,68264.0] || until2p7(s25)*+ -> . % 76.04/76.26 68741[127:Spt:68739.0,68263.1] || -> node4(s24)*. % 76.04/76.26 68743[127:MRR:846.0,68741.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.26 68746[127:Res:53.1,68743.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.26 68748[128:Spt:68746.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 68750[128:Res:68748.0,61.1] always3(s24) || -> . % 76.04/76.26 68751[128:SSi:68750.0,713.0,67834.0,67836.0,68262.0,68741.0] || -> . % 76.04/76.26 68752[128:Spt:68751.0,68746.0,68748.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.26 68753[128:Spt:68751.0,68746.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 68757[128:Res:68753.0,61.1] always3(s25) || -> . % 76.04/76.26 68758[128:SSi:68757.0,714.0,67837.0,67842.0] || -> . % 76.04/76.26 68759[126:Spt:68758.0,68261.0,68262.0] || until2p7(s24)*+ -> . % 76.04/76.26 68760[126:Spt:68758.0,68261.1] || -> node4(s23)*. % 76.04/76.26 68762[126:MRR:849.0,68760.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.26 68765[126:Res:53.1,68762.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.26 68767[127:Spt:68765.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 68769[127:Res:68767.0,61.1] always3(s23) || -> . % 76.04/76.26 68770[127:SSi:68769.0,712.0,67828.0,67833.0,68260.0,68760.0] || -> . % 76.04/76.26 68771[127:Spt:68770.0,68765.0,68767.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.26 68772[127:Spt:68770.0,68765.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 68776[127:Res:68772.0,61.1] always3(s24) || -> . % 76.04/76.26 68777[127:SSi:68776.0,713.0,67834.0,67836.0] || -> . % 76.04/76.26 68778[125:Spt:68777.0,68259.0,68260.0] || until2p7(s23)*+ -> . % 76.04/76.26 68779[125:Spt:68777.0,68259.1] || -> node4(s22)*. % 76.04/76.26 68781[125:MRR:852.0,68779.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.26 68784[125:Res:53.1,68781.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.26 68786[126:Spt:68784.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 68788[126:Res:68786.0,61.1] always3(s22) || -> . % 76.04/76.26 68789[126:SSi:68788.0,711.0,67825.0,67827.0,68258.0,68779.0] || -> . % 76.04/76.26 68790[126:Spt:68789.0,68784.0,68786.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.26 68791[126:Spt:68789.0,68784.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 68795[126:Res:68791.0,61.1] always3(s23) || -> . % 76.04/76.26 68796[126:SSi:68795.0,712.0,67828.0,67833.0] || -> . % 76.04/76.26 68797[124:Spt:68796.0,68257.0,68258.0] || until2p7(s22)*+ -> . % 76.04/76.26 68798[124:Spt:68796.0,68257.1] || -> node4(s21)*. % 76.04/76.26 68800[124:MRR:855.0,68798.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.26 68803[124:Res:53.1,68800.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.26 68808[125:Spt:68803.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 68810[125:Res:68808.0,61.1] always3(s21) || -> . % 76.04/76.26 68811[125:SSi:68810.0,710.0,67819.0,67824.0,68256.0,68798.0] || -> . % 76.04/76.26 68812[125:Spt:68811.0,68803.0,68808.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.26 68813[125:Spt:68811.0,68803.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 68817[125:Res:68813.0,61.1] always3(s22) || -> . % 76.04/76.26 68818[125:SSi:68817.0,711.0,67825.0,67827.0] || -> . % 76.04/76.26 68819[123:Spt:68818.0,68255.0,68256.0] || until2p7(s21)*+ -> . % 76.04/76.26 68820[123:Spt:68818.0,68255.1] || -> node4(s20)*. % 76.04/76.26 68822[123:MRR:858.0,68820.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.26 68825[123:Res:53.1,68822.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.26 68827[124:Spt:68825.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 68829[124:Res:68827.0,61.1] always3(s20) || -> . % 76.04/76.26 68830[124:SSi:68829.0,709.0,67816.0,67818.0,68254.0,68820.0] || -> . % 76.04/76.26 68831[124:Spt:68830.0,68825.0,68827.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.26 68832[124:Spt:68830.0,68825.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 68836[124:Res:68832.0,61.1] always3(s21) || -> . % 76.04/76.26 68837[124:SSi:68836.0,710.0,67819.0,67824.0] || -> . % 76.04/76.26 68838[122:Spt:68837.0,68253.0,68254.0] || until2p7(s20)*+ -> . % 76.04/76.26 68839[122:Spt:68837.0,68253.1] || -> node4(s19)*. % 76.04/76.26 68841[122:MRR:861.0,68839.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.26 68844[122:Res:53.1,68841.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.26 68846[123:Spt:68844.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 68848[123:Res:68846.0,61.1] always3(s19) || -> . % 76.04/76.26 68849[123:SSi:68848.0,708.0,67810.0,67815.0,68252.0,68839.0] || -> . % 76.04/76.26 68850[123:Spt:68849.0,68844.0,68846.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.26 68851[123:Spt:68849.0,68844.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 68855[123:Res:68851.0,61.1] always3(s20) || -> . % 76.04/76.26 68856[123:SSi:68855.0,709.0,67816.0,67818.0] || -> . % 76.04/76.26 68857[121:Spt:68856.0,68251.0,68252.0] || until2p7(s19)*+ -> . % 76.04/76.26 68858[121:Spt:68856.0,68251.1] || -> node4(s18)*. % 76.04/76.26 68860[121:MRR:864.0,68858.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.26 68863[121:Res:53.1,68860.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.26 68865[122:Spt:68863.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 68867[122:Res:68865.0,61.1] always3(s18) || -> . % 76.04/76.26 68868[122:SSi:68867.0,707.0,67807.0,67809.0,68250.0,68858.0] || -> . % 76.04/76.26 68869[122:Spt:68868.0,68863.0,68865.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.26 68870[122:Spt:68868.0,68863.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 68874[122:Res:68870.0,61.1] always3(s19) || -> . % 76.04/76.26 68875[122:SSi:68874.0,708.0,67810.0,67815.0] || -> . % 76.04/76.26 68876[120:Spt:68875.0,68249.0,68250.0] || until2p7(s18)*+ -> . % 76.04/76.26 68877[120:Spt:68875.0,68249.1] || -> node4(s17)*. % 76.04/76.26 68879[120:MRR:867.0,68877.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.26 68882[120:Res:53.1,68879.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.26 68887[121:Spt:68882.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 68889[121:Res:68887.0,61.1] always3(s17) || -> . % 76.04/76.26 68890[121:SSi:68889.0,706.0,67801.0,67806.0,68248.0,68877.0] || -> . % 76.04/76.26 68891[121:Spt:68890.0,68882.0,68887.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.26 68892[121:Spt:68890.0,68882.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 68896[121:Res:68892.0,61.1] always3(s18) || -> . % 76.04/76.26 68897[121:SSi:68896.0,707.0,67807.0,67809.0] || -> . % 76.04/76.26 68898[119:Spt:68897.0,68247.0,68248.0] || until2p7(s17)*+ -> . % 76.04/76.26 68899[119:Spt:68897.0,68247.1] || -> node4(s16)*. % 76.04/76.26 68901[119:MRR:870.0,68899.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.26 68904[119:Res:53.1,68901.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.26 68906[120:Spt:68904.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 68908[120:Res:68906.0,61.1] always3(s16) || -> . % 76.04/76.26 68909[120:SSi:68908.0,705.0,67798.0,67800.0,68246.0,68899.0] || -> . % 76.04/76.26 68910[120:Spt:68909.0,68904.0,68906.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.26 68911[120:Spt:68909.0,68904.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 68915[120:Res:68911.0,61.1] always3(s17) || -> . % 76.04/76.26 68916[120:SSi:68915.0,706.0,67801.0,67806.0] || -> . % 76.04/76.26 68917[118:Spt:68916.0,68245.0,68246.0] || until2p7(s16)*+ -> . % 76.04/76.26 68918[118:Spt:68916.0,68245.1] || -> node4(s15)*. % 76.04/76.26 68920[118:MRR:873.0,68918.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.26 68923[118:Res:53.1,68920.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.26 68925[119:Spt:68923.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 68927[119:Res:68925.0,61.1] always3(s15) || -> . % 76.04/76.26 68928[119:SSi:68927.0,704.0,67792.0,67797.0,68244.0,68918.0] || -> . % 76.04/76.26 68929[119:Spt:68928.0,68923.0,68925.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.26 68930[119:Spt:68928.0,68923.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 68934[119:Res:68930.0,61.1] always3(s16) || -> . % 76.04/76.26 68935[119:SSi:68934.0,705.0,67798.0,67800.0] || -> . % 76.04/76.26 68936[117:Spt:68935.0,68243.0,68244.0] || until2p7(s15)*+ -> . % 76.04/76.26 68937[117:Spt:68935.0,68243.1] || -> node4(s14)*. % 76.04/76.26 68939[117:MRR:876.0,68937.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.26 68942[117:Res:53.1,68939.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.26 68944[118:Spt:68942.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 68946[118:Res:68944.0,61.1] always3(s14) || -> . % 76.04/76.26 68947[118:SSi:68946.0,703.0,67789.0,67791.0,68242.0,68937.0] || -> . % 76.04/76.26 68948[118:Spt:68947.0,68942.0,68944.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.26 68949[118:Spt:68947.0,68942.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 68953[118:Res:68949.0,61.1] always3(s15) || -> . % 76.04/76.26 68954[118:SSi:68953.0,704.0,67792.0,67797.0] || -> . % 76.04/76.26 68955[116:Spt:68954.0,68241.0,68242.0] || until2p7(s14)*+ -> . % 76.04/76.26 68956[116:Spt:68954.0,68241.1] || -> node4(s13)*. % 76.04/76.26 68958[116:MRR:879.0,68956.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.26 68961[116:Res:53.1,68958.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.26 68966[117:Spt:68961.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 68968[117:Res:68966.0,61.1] always3(s13) || -> . % 76.04/76.26 68969[117:SSi:68968.0,702.0,67783.0,67788.0,68240.0,68956.0] || -> . % 76.04/76.26 68970[117:Spt:68969.0,68961.0,68966.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.26 68971[117:Spt:68969.0,68961.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 68975[117:Res:68971.0,61.1] always3(s14) || -> . % 76.04/76.26 68976[117:SSi:68975.0,703.0,67789.0,67791.0] || -> . % 76.04/76.26 68977[115:Spt:68976.0,68239.0,68240.0] || until2p7(s13)*+ -> . % 76.04/76.26 68978[115:Spt:68976.0,68239.1] || -> node4(s12)*. % 76.04/76.26 68980[115:MRR:882.0,68978.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.26 68983[115:Res:53.1,68980.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.26 68985[116:Spt:68983.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 68987[116:Res:68985.0,61.1] always3(s12) || -> . % 76.04/76.26 68988[116:SSi:68987.0,701.0,67780.0,67782.0,68238.0,68978.0] || -> . % 76.04/76.26 68989[116:Spt:68988.0,68983.0,68985.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.26 68990[116:Spt:68988.0,68983.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 68994[116:Res:68990.0,61.1] always3(s13) || -> . % 76.04/76.26 68995[116:SSi:68994.0,702.0,67783.0,67788.0] || -> . % 76.04/76.26 68996[114:Spt:68995.0,68237.0,68238.0] || until2p7(s12)*+ -> . % 76.04/76.26 68997[114:Spt:68995.0,68237.1] || -> node4(s11)*. % 76.04/76.26 68999[114:MRR:885.0,68997.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.26 69002[114:Res:53.1,68999.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.26 69004[115:Spt:69002.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 69006[115:Res:69004.0,61.1] always3(s11) || -> . % 76.04/76.26 69007[115:SSi:69006.0,700.0,67774.0,67779.0,68236.0,68997.0] || -> . % 76.04/76.26 69008[115:Spt:69007.0,69002.0,69004.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.26 69009[115:Spt:69007.0,69002.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 69013[115:Res:69009.0,61.1] always3(s12) || -> . % 76.04/76.26 69014[115:SSi:69013.0,701.0,67780.0,67782.0] || -> . % 76.04/76.26 69015[113:Spt:69014.0,68235.0,68236.0] || until2p7(s11)*+ -> . % 76.04/76.26 69016[113:Spt:69014.0,68235.1] || -> node4(s10)*. % 76.04/76.26 69018[113:MRR:888.0,69016.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.26 69021[113:Res:53.1,69018.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.26 69023[114:Spt:69021.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 69025[114:Res:69023.0,61.1] always3(s10) || -> . % 76.04/76.26 69026[114:SSi:69025.0,699.0,67771.0,67773.0,68234.0,69016.0] || -> . % 76.04/76.26 69027[114:Spt:69026.0,69021.0,69023.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.26 69028[114:Spt:69026.0,69021.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 69032[114:Res:69028.0,61.1] always3(s11) || -> . % 76.04/76.26 69033[114:SSi:69032.0,700.0,67774.0,67779.0] || -> . % 76.04/76.26 69034[112:Spt:69033.0,68233.0,68234.0] || until2p7(s10)*+ -> . % 76.04/76.26 69035[112:Spt:69033.0,68233.1] || -> node4(s9)*. % 76.04/76.26 69037[112:MRR:891.0,69035.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.26 69040[112:Res:53.1,69037.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.26 69045[113:Spt:69040.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 69047[113:Res:69045.0,61.1] always3(s9) || -> . % 76.04/76.26 69048[113:SSi:69047.0,698.0,67765.0,67770.0,68232.0,69035.0] || -> . % 76.04/76.26 69049[113:Spt:69048.0,69040.0,69045.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.26 69050[113:Spt:69048.0,69040.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 69054[113:Res:69050.0,61.1] always3(s10) || -> . % 76.04/76.26 69055[113:SSi:69054.0,699.0,67771.0,67773.0] || -> . % 76.04/76.26 69056[111:Spt:69055.0,68231.0,68232.0] || until2p7(s9)*+ -> . % 76.04/76.26 69057[111:Spt:69055.0,68231.1] || -> node4(s8)*. % 76.04/76.26 69059[111:MRR:894.0,69057.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.26 69062[111:Res:53.1,69059.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.26 69064[112:Spt:69062.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 69066[112:Res:69064.0,61.1] always3(s8) || -> . % 76.04/76.26 69067[112:SSi:69066.0,697.0,67762.0,67764.0,68230.0,69057.0] || -> . % 76.04/76.26 69068[112:Spt:69067.0,69062.0,69064.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.26 69069[112:Spt:69067.0,69062.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 69073[112:Res:69069.0,61.1] always3(s9) || -> . % 76.04/76.26 69074[112:SSi:69073.0,698.0,67765.0,67770.0] || -> . % 76.04/76.26 69075[110:Spt:69074.0,68229.0,68230.0] || until2p7(s8)*+ -> . % 76.04/76.26 69076[110:Spt:69074.0,68229.1] || -> node4(s7)*. % 76.04/76.26 69078[110:MRR:897.0,69076.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.26 69081[110:Res:53.1,69078.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.26 69083[111:Spt:69081.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 69085[111:Res:69083.0,61.1] always3(s7) || -> . % 76.04/76.26 69086[111:SSi:69085.0,696.0,67756.0,67761.0,68228.0,69076.0] || -> . % 76.04/76.26 69087[111:Spt:69086.0,69081.0,69083.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.26 69088[111:Spt:69086.0,69081.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 69092[111:Res:69088.0,61.1] always3(s8) || -> . % 76.04/76.26 69093[111:SSi:69092.0,697.0,67762.0,67764.0] || -> . % 76.04/76.26 69094[109:Spt:69093.0,68227.0,68228.0] || until2p7(s7)*+ -> . % 76.04/76.26 69095[109:Spt:69093.0,68227.1] || -> node4(s6)*. % 76.04/76.26 69097[109:MRR:900.0,69095.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.26 69100[109:Res:53.1,69097.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.26 69102[110:Spt:69100.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 69104[110:Res:69102.0,61.1] always3(s6) || -> . % 76.04/76.26 69105[110:SSi:69104.0,695.0,67753.0,67755.0,68226.0,69095.0] || -> . % 76.04/76.26 69106[110:Spt:69105.0,69100.0,69102.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.26 69107[110:Spt:69105.0,69100.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 69111[110:Res:69107.0,61.1] always3(s7) || -> . % 76.04/76.26 69112[110:SSi:69111.0,696.0,67756.0,67761.0] || -> . % 76.04/76.26 69113[108:Spt:69112.0,68225.0,68226.0] || until2p7(s6)*+ -> . % 76.04/76.26 69114[108:Spt:69112.0,68225.1] || -> node4(s5)*. % 76.04/76.26 69116[108:MRR:903.0,69114.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.26 69119[108:Res:53.1,69116.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.26 69124[109:Spt:69119.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.26 69126[109:Res:69124.0,61.1] always3(s5) || -> . % 76.04/76.26 69127[109:SSi:69126.0,694.0,67747.0,67752.0,68224.0,69114.0] || -> . % 76.04/76.26 69128[109:Spt:69127.0,69119.0,69124.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.26 69129[109:Spt:69127.0,69119.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 69133[109:Res:69129.0,61.1] always3(s6) || -> . % 76.04/76.26 69134[109:SSi:69133.0,695.0,67753.0,67755.0] || -> . % 76.04/76.26 69135[107:Spt:69134.0,68223.0,68224.0] || until2p7(s5)*+ -> . % 76.04/76.26 69136[107:Spt:69134.0,68223.1] || -> node4(s4)*. % 76.04/76.26 69138[107:MRR:906.0,69136.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.26 69141[107:Res:53.1,69138.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.26 69143[107:MRR:69141.0,68213.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.26 69145[107:Res:69143.0,61.1] always3(s5) || -> . % 76.04/76.26 69146[107:SSi:69145.0,694.0,67747.0,67752.0] || -> . % 76.04/76.26 69147[105:Spt:69146.0,68046.1,68048.0] || xuntil6(s48)* -> . % 76.04/76.26 69148[105:Spt:69146.0,68046.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.26 69151[105:Res:69148.0,61.1] always3(s48) || -> . % 76.04/76.26 69152[105:SSi:69151.0,737.0,68036.0] || -> . % 76.04/76.26 69153[103:Spt:69152.0,68030.2,68035.0] || xuntil6(s47)*+ -> . % 76.04/76.26 69154[103:Spt:69152.0,68030.0,68030.1] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.26 69155[103:Res:53.1,69154.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.26 69157[103:MRR:69155.0,68022.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.26 69159[103:Res:69157.0,61.1] always3(s48) || -> . % 76.04/76.26 69160[103:SSi:69159.0,737.0] || -> . % 76.04/76.26 69161[102:Spt:69160.0,68026.1,68028.0] || xuntil6(s46)* -> . % 76.04/76.26 69162[102:Spt:69160.0,68026.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.26 69165[102:Res:69162.0,61.1] always3(s46) || -> . % 76.04/76.26 69166[102:SSi:69165.0,735.0,68016.0] || -> . % 76.04/76.26 69167[100:Spt:69166.0,68013.2,68015.0] || xuntil6(s45)*+ -> . % 76.04/76.26 69168[100:Spt:69166.0,68013.0,68013.1] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.26 69169[100:Res:53.1,69168.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.26 69171[100:MRR:69169.0,68002.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.26 69173[100:Res:69171.0,61.1] always3(s46) || -> . % 76.04/76.26 69174[100:SSi:69173.0,735.0] || -> . % 76.04/76.26 69175[99:Spt:69174.0,68006.1,68011.0] || xuntil6(s44)* -> . % 76.04/76.26 69176[99:Spt:69174.0,68006.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.26 69179[99:Res:69176.0,61.1] always3(s44) || -> . % 76.04/76.26 69180[99:SSi:69179.0,733.0,67996.0] || -> . % 76.04/76.26 69181[97:Spt:69180.0,67987.2,67995.0] || xuntil6(s43)*+ -> . % 76.04/76.26 69182[97:Spt:69180.0,67987.0,67987.1] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.26 69183[97:Res:53.1,69182.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.26 69185[97:MRR:69183.0,67979.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.26 69187[97:Res:69185.0,61.1] always3(s44) || -> . % 76.04/76.26 69188[97:SSi:69187.0,733.0] || -> . % 76.04/76.26 69189[96:Spt:69188.0,67983.1,67985.0] || xuntil6(s42)* -> . % 76.04/76.26 69190[96:Spt:69188.0,67983.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.26 69193[96:Res:69190.0,61.1] always3(s42) || -> . % 76.04/76.26 69194[96:SSi:69193.0,731.0,67973.0] || -> . % 76.04/76.26 69195[94:Spt:69194.0,67967.2,67972.0] || xuntil6(s41)*+ -> . % 76.04/76.26 69196[94:Spt:69194.0,67967.0,67967.1] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.26 69197[94:Res:53.1,69196.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.26 69199[94:MRR:69197.0,67959.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.26 69202[94:Res:69199.0,61.1] always3(s42) || -> . % 76.04/76.26 69203[94:SSi:69202.0,731.0] || -> . % 76.04/76.26 69204[93:Spt:69203.0,67963.1,67965.0] || xuntil6(s40)* -> . % 76.04/76.26 69205[93:Spt:69203.0,67963.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.26 69208[93:Res:69205.0,61.1] always3(s40) || -> . % 76.04/76.26 69209[93:SSi:69208.0,729.0,67953.0] || -> . % 76.04/76.26 69210[91:Spt:69209.0,67950.2,67952.0] || xuntil6(s39)*+ -> . % 76.04/76.26 69211[91:Spt:69209.0,67950.0,67950.1] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.26 69212[91:Res:53.1,69211.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.26 69214[91:MRR:69212.0,67939.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.26 69216[91:Res:69214.0,61.1] always3(s40) || -> . % 76.04/76.26 69217[91:SSi:69216.0,729.0] || -> . % 76.04/76.26 69218[90:Spt:69217.0,67943.1,67948.0] || xuntil6(s38)* -> . % 76.04/76.26 69219[90:Spt:69217.0,67943.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.26 69222[90:Res:69219.0,61.1] always3(s38) || -> . % 76.04/76.26 69223[90:SSi:69222.0,727.0,67933.0] || -> . % 76.04/76.26 69224[88:Spt:69223.0,67924.2,67932.0] || xuntil6(s37)*+ -> . % 76.04/76.26 69225[88:Spt:69223.0,67924.0,67924.1] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.26 69226[88:Res:53.1,69225.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.26 69228[88:MRR:69226.0,67916.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.26 69231[88:Res:69228.0,61.1] always3(s38) || -> . % 76.04/76.26 69232[88:SSi:69231.0,727.0] || -> . % 76.04/76.26 69233[87:Spt:69232.0,67920.1,67922.0] || xuntil6(s36)* -> . % 76.04/76.26 69234[87:Spt:69232.0,67920.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.26 69237[87:Res:69234.0,61.1] always3(s36) || -> . % 76.04/76.26 69238[87:SSi:69237.0,725.0,67910.0] || -> . % 76.04/76.26 69239[85:Spt:69238.0,67904.2,67909.0] || xuntil6(s35)*+ -> . % 76.04/76.26 69240[85:Spt:69238.0,67904.0,67904.1] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.26 69241[85:Res:53.1,69240.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.26 69243[85:MRR:69241.0,67896.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.26 69245[85:Res:69243.0,61.1] always3(s36) || -> . % 76.04/76.26 69246[85:SSi:69245.0,725.0] || -> . % 76.04/76.26 69247[84:Spt:69246.0,67900.1,67902.0] || xuntil6(s34)* -> . % 76.04/76.26 69248[84:Spt:69246.0,67900.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.26 69251[84:Res:69248.0,61.1] always3(s34) || -> . % 76.04/76.26 69252[84:SSi:69251.0,723.0,67890.0] || -> . % 76.04/76.26 69253[82:Spt:69252.0,67887.2,67889.0] || xuntil6(s33)*+ -> . % 76.04/76.26 69254[82:Spt:69252.0,67887.0,67887.1] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.26 69255[82:Res:53.1,69254.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.26 69257[82:MRR:69255.0,67876.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.26 69259[82:Res:69257.0,61.1] always3(s34) || -> . % 76.04/76.26 69260[82:SSi:69259.0,723.0] || -> . % 76.04/76.26 69261[81:Spt:69260.0,67880.1,67885.0] || xuntil6(s32)* -> . % 76.04/76.26 69262[81:Spt:69260.0,67880.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.26 69265[81:Res:69262.0,61.1] always3(s32) || -> . % 76.04/76.26 69266[81:SSi:69265.0,721.0,67870.0] || -> . % 76.04/76.26 69267[79:Spt:69266.0,67865.2,67869.0] || xuntil6(s31)*+ -> . % 76.04/76.26 69268[79:Spt:69266.0,67865.0,67865.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.26 69269[79:Res:53.1,69268.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.26 69271[80:Spt:69269.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.26 69273[80:Res:69271.0,61.1] always3(s32) || -> . % 76.04/76.26 69274[80:SSi:69273.0,721.0] || -> . % 76.04/76.26 69275[80:Spt:69274.0,69269.1,69271.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.26 69276[80:Spt:69274.0,69269.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 69279[80:Res:69276.0,61.1] always3(s31) || -> . % 76.04/76.26 69280[80:SSi:69279.0,720.0,67864.0] || -> . % 76.04/76.26 69281[78:Spt:69280.0,67862.2,67863.0] || xuntil6(s30)*+ -> . % 76.04/76.26 69282[78:Spt:69280.0,67862.0,67862.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.26 69283[78:Res:53.1,69282.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.26 69285[79:Spt:69283.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.26 69287[79:Res:69285.0,61.1] always3(s31) || -> . % 76.04/76.26 69288[79:SSi:69287.0,720.0] || -> . % 76.04/76.26 69289[79:Spt:69288.0,69283.1,69285.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.26 69290[79:Spt:69288.0,69283.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 69293[79:Res:69290.0,61.1] always3(s30) || -> . % 76.04/76.26 69294[79:SSi:69293.0,719.0,67861.0] || -> . % 76.04/76.26 69295[77:Spt:69294.0,67856.2,67860.0] || xuntil6(s29)*+ -> . % 76.04/76.26 69296[77:Spt:69294.0,67856.0,67856.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.26 69297[77:Res:53.1,69296.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.26 69299[78:Spt:69297.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.26 69301[78:Res:69299.0,61.1] always3(s30) || -> . % 76.04/76.26 69302[78:SSi:69301.0,719.0] || -> . % 76.04/76.26 69303[78:Spt:69302.0,69297.1,69299.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.26 69304[78:Spt:69302.0,69297.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 69307[78:Res:69304.0,61.1] always3(s29) || -> . % 76.04/76.26 69308[78:SSi:69307.0,718.0,67855.0] || -> . % 76.04/76.26 69309[76:Spt:69308.0,67853.2,67854.0] || xuntil6(s28)*+ -> . % 76.04/76.26 69310[76:Spt:69308.0,67853.0,67853.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.26 69311[76:Res:53.1,69310.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.26 69313[77:Spt:69311.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.26 69315[77:Res:69313.0,61.1] always3(s29) || -> . % 76.04/76.26 69316[77:SSi:69315.0,718.0] || -> . % 76.04/76.26 69317[77:Spt:69316.0,69311.1,69313.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.26 69318[77:Spt:69316.0,69311.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 69321[77:Res:69318.0,61.1] always3(s28) || -> . % 76.04/76.26 69322[77:SSi:69321.0,717.0,67852.0] || -> . % 76.04/76.26 69323[75:Spt:69322.0,67847.2,67851.0] || xuntil6(s27)*+ -> . % 76.04/76.26 69324[75:Spt:69322.0,67847.0,67847.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.26 69325[75:Res:53.1,69324.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.26 69327[76:Spt:69325.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.26 69329[76:Res:69327.0,61.1] always3(s28) || -> . % 76.04/76.26 69330[76:SSi:69329.0,717.0] || -> . % 76.04/76.26 69331[76:Spt:69330.0,69325.1,69327.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.26 69332[76:Spt:69330.0,69325.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 69335[76:Res:69332.0,61.1] always3(s27) || -> . % 76.04/76.26 69336[76:SSi:69335.0,716.0,67846.0] || -> . % 76.04/76.26 69337[74:Spt:69336.0,67844.2,67845.0] || xuntil6(s26)*+ -> . % 76.04/76.26 69338[74:Spt:69336.0,67844.0,67844.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.26 69339[74:Res:53.1,69338.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.26 69341[75:Spt:69339.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.26 69343[75:Res:69341.0,61.1] always3(s27) || -> . % 76.04/76.26 69344[75:SSi:69343.0,716.0] || -> . % 76.04/76.26 69345[75:Spt:69344.0,69339.1,69341.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.26 69346[75:Spt:69344.0,69339.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 69349[75:Res:69346.0,61.1] always3(s26) || -> . % 76.04/76.26 69350[75:SSi:69349.0,715.0,67843.0] || -> . % 76.04/76.26 69351[73:Spt:69350.0,67838.2,67842.0] || xuntil6(s25)*+ -> . % 76.04/76.26 69352[73:Spt:69350.0,67838.0,67838.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.26 69353[73:Res:53.1,69352.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.26 69355[74:Spt:69353.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.26 69357[74:Res:69355.0,61.1] always3(s26) || -> . % 76.04/76.26 69358[74:SSi:69357.0,715.0] || -> . % 76.04/76.26 69359[74:Spt:69358.0,69353.1,69355.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.26 69360[74:Spt:69358.0,69353.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 69363[74:Res:69360.0,61.1] always3(s25) || -> . % 76.04/76.26 69364[74:SSi:69363.0,714.0,67837.0] || -> . % 76.04/76.26 69365[72:Spt:69364.0,67835.2,67836.0] || xuntil6(s24)*+ -> . % 76.04/76.26 69366[72:Spt:69364.0,67835.0,67835.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.26 69367[72:Res:53.1,69366.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.26 69369[73:Spt:69367.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.26 69371[73:Res:69369.0,61.1] always3(s25) || -> . % 76.04/76.26 69372[73:SSi:69371.0,714.0] || -> . % 76.04/76.26 69373[73:Spt:69372.0,69367.1,69369.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.26 69374[73:Spt:69372.0,69367.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 69377[73:Res:69374.0,61.1] always3(s24) || -> . % 76.04/76.26 69378[73:SSi:69377.0,713.0,67834.0] || -> . % 76.04/76.26 69379[71:Spt:69378.0,67829.2,67833.0] || xuntil6(s23)*+ -> . % 76.04/76.26 69380[71:Spt:69378.0,67829.0,67829.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.26 69381[71:Res:53.1,69380.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.26 69383[72:Spt:69381.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.26 69385[72:Res:69383.0,61.1] always3(s24) || -> . % 76.04/76.26 69386[72:SSi:69385.0,713.0] || -> . % 76.04/76.26 69387[72:Spt:69386.0,69381.1,69383.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.26 69388[72:Spt:69386.0,69381.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 69391[72:Res:69388.0,61.1] always3(s23) || -> . % 76.04/76.26 69392[72:SSi:69391.0,712.0,67828.0] || -> . % 76.04/76.26 69393[70:Spt:69392.0,67826.2,67827.0] || xuntil6(s22)*+ -> . % 76.04/76.26 69394[70:Spt:69392.0,67826.0,67826.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.26 69395[70:Res:53.1,69394.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.26 69400[71:Spt:69395.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 69402[71:Res:69400.0,61.1] always3(s22) || -> . % 76.04/76.26 69403[71:SSi:69402.0,711.0,67825.0] || -> . % 76.04/76.26 69404[71:Spt:69403.0,69395.0,69400.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.26 69405[71:Spt:69403.0,69395.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.26 69409[71:Res:69405.0,61.1] always3(s23) || -> . % 76.04/76.26 69410[71:SSi:69409.0,712.0] || -> . % 76.04/76.26 69411[69:Spt:69410.0,67820.2,67824.0] || xuntil6(s21)*+ -> . % 76.04/76.26 69412[69:Spt:69410.0,67820.0,67820.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.26 69413[69:Res:53.1,69412.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.26 69415[70:Spt:69413.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.26 69417[70:Res:69415.0,61.1] always3(s22) || -> . % 76.04/76.26 69418[70:SSi:69417.0,711.0] || -> . % 76.04/76.26 69419[70:Spt:69418.0,69413.1,69415.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.26 69420[70:Spt:69418.0,69413.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 69423[70:Res:69420.0,61.1] always3(s21) || -> . % 76.04/76.26 69424[70:SSi:69423.0,710.0,67819.0] || -> . % 76.04/76.26 69425[68:Spt:69424.0,67817.2,67818.0] || xuntil6(s20)*+ -> . % 76.04/76.26 69426[68:Spt:69424.0,67817.0,67817.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.26 69427[68:Res:53.1,69426.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.26 69429[69:Spt:69427.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.26 69431[69:Res:69429.0,61.1] always3(s21) || -> . % 76.04/76.26 69432[69:SSi:69431.0,710.0] || -> . % 76.04/76.26 69433[69:Spt:69432.0,69427.1,69429.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.26 69434[69:Spt:69432.0,69427.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 69437[69:Res:69434.0,61.1] always3(s20) || -> . % 76.04/76.26 69438[69:SSi:69437.0,709.0,67816.0] || -> . % 76.04/76.26 69439[67:Spt:69438.0,67811.2,67815.0] || xuntil6(s19)*+ -> . % 76.04/76.26 69440[67:Spt:69438.0,67811.0,67811.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.26 69441[67:Res:53.1,69440.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.26 69446[68:Spt:69441.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 69448[68:Res:69446.0,61.1] always3(s19) || -> . % 76.04/76.26 69449[68:SSi:69448.0,708.0,67810.0] || -> . % 76.04/76.26 69450[68:Spt:69449.0,69441.0,69446.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.26 69451[68:Spt:69449.0,69441.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.26 69455[68:Res:69451.0,61.1] always3(s20) || -> . % 76.04/76.26 69456[68:SSi:69455.0,709.0] || -> . % 76.04/76.26 69457[66:Spt:69456.0,67808.2,67809.0] || xuntil6(s18)*+ -> . % 76.04/76.26 69458[66:Spt:69456.0,67808.0,67808.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.26 69459[66:Res:53.1,69458.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.26 69461[67:Spt:69459.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.26 69463[67:Res:69461.0,61.1] always3(s19) || -> . % 76.04/76.26 69464[67:SSi:69463.0,708.0] || -> . % 76.04/76.26 69465[67:Spt:69464.0,69459.1,69461.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.26 69466[67:Spt:69464.0,69459.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 69469[67:Res:69466.0,61.1] always3(s18) || -> . % 76.04/76.26 69470[67:SSi:69469.0,707.0,67807.0] || -> . % 76.04/76.26 69471[65:Spt:69470.0,67802.2,67806.0] || xuntil6(s17)*+ -> . % 76.04/76.26 69472[65:Spt:69470.0,67802.0,67802.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.26 69473[65:Res:53.1,69472.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.26 69475[66:Spt:69473.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.26 69477[66:Res:69475.0,61.1] always3(s18) || -> . % 76.04/76.26 69478[66:SSi:69477.0,707.0] || -> . % 76.04/76.26 69479[66:Spt:69478.0,69473.1,69475.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.26 69480[66:Spt:69478.0,69473.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 69483[66:Res:69480.0,61.1] always3(s17) || -> . % 76.04/76.26 69484[66:SSi:69483.0,706.0,67801.0] || -> . % 76.04/76.26 69485[64:Spt:69484.0,67799.2,67800.0] || xuntil6(s16)*+ -> . % 76.04/76.26 69486[64:Spt:69484.0,67799.0,67799.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.26 69487[64:Res:53.1,69486.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.26 69492[65:Spt:69487.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 69494[65:Res:69492.0,61.1] always3(s16) || -> . % 76.04/76.26 69495[65:SSi:69494.0,705.0,67798.0] || -> . % 76.04/76.26 69496[65:Spt:69495.0,69487.0,69492.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.26 69497[65:Spt:69495.0,69487.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.26 69501[65:Res:69497.0,61.1] always3(s17) || -> . % 76.04/76.26 69502[65:SSi:69501.0,706.0] || -> . % 76.04/76.26 69503[63:Spt:69502.0,67793.2,67797.0] || xuntil6(s15)*+ -> . % 76.04/76.26 69504[63:Spt:69502.0,67793.0,67793.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.26 69505[63:Res:53.1,69504.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.26 69507[64:Spt:69505.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.26 69509[64:Res:69507.0,61.1] always3(s16) || -> . % 76.04/76.26 69510[64:SSi:69509.0,705.0] || -> . % 76.04/76.26 69511[64:Spt:69510.0,69505.1,69507.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.26 69512[64:Spt:69510.0,69505.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 69515[64:Res:69512.0,61.1] always3(s15) || -> . % 76.04/76.26 69516[64:SSi:69515.0,704.0,67792.0] || -> . % 76.04/76.26 69517[62:Spt:69516.0,67790.2,67791.0] || xuntil6(s14)*+ -> . % 76.04/76.26 69518[62:Spt:69516.0,67790.0,67790.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.26 69519[62:Res:53.1,69518.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.26 69521[63:Spt:69519.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.26 69523[63:Res:69521.0,61.1] always3(s15) || -> . % 76.04/76.26 69524[63:SSi:69523.0,704.0] || -> . % 76.04/76.26 69525[63:Spt:69524.0,69519.1,69521.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.26 69526[63:Spt:69524.0,69519.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 69529[63:Res:69526.0,61.1] always3(s14) || -> . % 76.04/76.26 69530[63:SSi:69529.0,703.0,67789.0] || -> . % 76.04/76.26 69531[61:Spt:69530.0,67784.2,67788.0] || xuntil6(s13)*+ -> . % 76.04/76.26 69532[61:Spt:69530.0,67784.0,67784.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.26 69533[61:Res:53.1,69532.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.26 69538[62:Spt:69533.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 69540[62:Res:69538.0,61.1] always3(s13) || -> . % 76.04/76.26 69541[62:SSi:69540.0,702.0,67783.0] || -> . % 76.04/76.26 69542[62:Spt:69541.0,69533.0,69538.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.26 69543[62:Spt:69541.0,69533.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.26 69547[62:Res:69543.0,61.1] always3(s14) || -> . % 76.04/76.26 69548[62:SSi:69547.0,703.0] || -> . % 76.04/76.26 69549[60:Spt:69548.0,67781.2,67782.0] || xuntil6(s12)*+ -> . % 76.04/76.26 69550[60:Spt:69548.0,67781.0,67781.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.26 69551[60:Res:53.1,69550.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.26 69553[61:Spt:69551.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.26 69555[61:Res:69553.0,61.1] always3(s13) || -> . % 76.04/76.26 69556[61:SSi:69555.0,702.0] || -> . % 76.04/76.26 69557[61:Spt:69556.0,69551.1,69553.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.26 69558[61:Spt:69556.0,69551.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 69561[61:Res:69558.0,61.1] always3(s12) || -> . % 76.04/76.26 69562[61:SSi:69561.0,701.0,67780.0] || -> . % 76.04/76.26 69563[59:Spt:69562.0,67775.2,67779.0] || xuntil6(s11)*+ -> . % 76.04/76.26 69564[59:Spt:69562.0,67775.0,67775.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.26 69565[59:Res:53.1,69564.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.26 69567[60:Spt:69565.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.26 69569[60:Res:69567.0,61.1] always3(s12) || -> . % 76.04/76.26 69570[60:SSi:69569.0,701.0] || -> . % 76.04/76.26 69571[60:Spt:69570.0,69565.1,69567.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.26 69572[60:Spt:69570.0,69565.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 69575[60:Res:69572.0,61.1] always3(s11) || -> . % 76.04/76.26 69576[60:SSi:69575.0,700.0,67774.0] || -> . % 76.04/76.26 69577[58:Spt:69576.0,67772.2,67773.0] || xuntil6(s10)*+ -> . % 76.04/76.26 69578[58:Spt:69576.0,67772.0,67772.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.26 69579[58:Res:53.1,69578.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.26 69584[59:Spt:69579.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 69586[59:Res:69584.0,61.1] always3(s10) || -> . % 76.04/76.26 69587[59:SSi:69586.0,699.0,67771.0] || -> . % 76.04/76.26 69588[59:Spt:69587.0,69579.0,69584.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.26 69589[59:Spt:69587.0,69579.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.26 69593[59:Res:69589.0,61.1] always3(s11) || -> . % 76.04/76.26 69594[59:SSi:69593.0,700.0] || -> . % 76.04/76.26 69595[57:Spt:69594.0,67766.2,67770.0] || xuntil6(s9)*+ -> . % 76.04/76.26 69596[57:Spt:69594.0,67766.0,67766.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.26 69597[57:Res:53.1,69596.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.26 69599[58:Spt:69597.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.26 69601[58:Res:69599.0,61.1] always3(s10) || -> . % 76.04/76.26 69602[58:SSi:69601.0,699.0] || -> . % 76.04/76.26 69603[58:Spt:69602.0,69597.1,69599.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.26 69604[58:Spt:69602.0,69597.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 69607[58:Res:69604.0,61.1] always3(s9) || -> . % 76.04/76.26 69608[58:SSi:69607.0,698.0,67765.0] || -> . % 76.04/76.26 69609[56:Spt:69608.0,67763.2,67764.0] || xuntil6(s8)*+ -> . % 76.04/76.26 69610[56:Spt:69608.0,67763.0,67763.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.26 69611[56:Res:53.1,69610.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.26 69613[57:Spt:69611.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.26 69615[57:Res:69613.0,61.1] always3(s9) || -> . % 76.04/76.26 69616[57:SSi:69615.0,698.0] || -> . % 76.04/76.26 69617[57:Spt:69616.0,69611.1,69613.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.26 69618[57:Spt:69616.0,69611.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 69621[57:Res:69618.0,61.1] always3(s8) || -> . % 76.04/76.26 69622[57:SSi:69621.0,697.0,67762.0] || -> . % 76.04/76.26 69623[55:Spt:69622.0,67757.2,67761.0] || xuntil6(s7)*+ -> . % 76.04/76.26 69624[55:Spt:69622.0,67757.0,67757.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.26 69625[55:Res:53.1,69624.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.26 69630[56:Spt:69625.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 69632[56:Res:69630.0,61.1] always3(s7) || -> . % 76.04/76.26 69633[56:SSi:69632.0,696.0,67756.0] || -> . % 76.04/76.26 69634[56:Spt:69633.0,69625.0,69630.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.26 69635[56:Spt:69633.0,69625.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.26 69639[56:Res:69635.0,61.1] always3(s8) || -> . % 76.04/76.26 69640[56:SSi:69639.0,697.0] || -> . % 76.04/76.26 69641[54:Spt:69640.0,67754.2,67755.0] || xuntil6(s6)*+ -> . % 76.04/76.26 69642[54:Spt:69640.0,67754.0,67754.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.26 69643[54:Res:53.1,69642.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.26 69645[55:Spt:69643.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.26 69647[55:Res:69645.0,61.1] always3(s7) || -> . % 76.04/76.26 69648[55:SSi:69647.0,696.0] || -> . % 76.04/76.26 69649[55:Spt:69648.0,69643.1,69645.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.26 69650[55:Spt:69648.0,69643.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 69653[55:Res:69650.0,61.1] always3(s6) || -> . % 76.04/76.26 69654[55:SSi:69653.0,695.0,67753.0] || -> . % 76.04/76.26 69655[53:Spt:69654.0,67748.2,67752.0] || xuntil6(s5)*+ -> . % 76.04/76.26 69656[53:Spt:69654.0,67748.0,67748.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.26 69657[53:Res:53.1,69656.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.26 69659[54:Spt:69657.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.26 69661[54:Res:69659.0,61.1] always3(s6) || -> . % 76.04/76.26 69662[54:SSi:69661.0,695.0] || -> . % 76.04/76.26 69663[54:Spt:69662.0,69657.1,69659.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.26 69664[54:Spt:69662.0,69657.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.26 69667[54:Res:69664.0,61.1] always3(s5) || -> . % 76.04/76.26 69668[54:SSi:69667.0,694.0,67747.0] || -> . % 76.04/76.26 69669[52:Spt:69668.0,67745.2,67746.0] || xuntil6(s4)*+ -> . % 76.04/76.26 69670[52:Spt:69668.0,67745.0,67745.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.26 69671[52:Res:53.1,69670.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.26 69676[53:Spt:69671.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.26 69678[53:Res:69676.0,61.1] always3(s4) || -> . % 76.04/76.26 69679[53:SSi:69678.0,693.0,67744.0] || -> . % 76.04/76.26 69680[53:Spt:69679.0,69671.0,69676.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.26 69681[53:Spt:69679.0,69671.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.26 69688[53:Res:69681.0,61.1] always3(s5) || -> . % 76.04/76.26 69689[53:SSi:69688.0,694.0] || -> . % 76.04/76.26 69690[51:Spt:69689.0,67739.2,67743.0] || xuntil6(s3)*+ -> . % 76.04/76.26 69691[51:Spt:69689.0,67739.0,67739.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.26 69692[51:Res:53.1,69691.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.26 69694[52:Spt:69692.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.26 69696[52:Res:69694.0,61.1] always3(s3) || -> . % 76.04/76.26 69697[52:SSi:69696.0,692.0,67738.0] || -> . % 76.04/76.26 69698[52:Spt:69697.0,69692.0,69694.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.26 69699[52:Spt:69697.0,69692.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.26 69703[52:Res:69699.0,61.1] always3(s4) || -> . % 76.04/76.26 69704[52:SSi:69703.0,693.0] || -> . % 76.04/76.26 69705[50:Spt:69704.0,67736.2,67737.0] || xuntil6(s2)*+ -> . % 76.04/76.26 69706[50:Spt:69704.0,67736.0,67736.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.27 69707[50:Res:53.1,69706.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.27 69709[51:Spt:69707.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 69711[51:Res:69709.0,61.1] always3(s2) || -> . % 76.04/76.27 69712[51:SSi:69711.0,691.0,67735.0] || -> . % 76.04/76.27 69713[51:Spt:69712.0,69707.0,69709.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.27 69714[51:Spt:69712.0,69707.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 69718[51:Res:69714.0,61.1] always3(s3) || -> . % 76.04/76.27 69719[51:SSi:69718.0,692.0] || -> . % 76.04/76.27 69720[49:Spt:69719.0,67727.2,67734.0] || xuntil6(s1)*+ -> . % 76.04/76.27 69721[49:Spt:69719.0,67727.0,67727.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.27 69722[49:Res:53.1,69721.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.27 69727[50:Spt:69722.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 69729[50:Res:69727.0,61.1] always3(s1) || -> . % 76.04/76.27 69730[50:SSi:69729.0,690.0,67726.0] || -> . % 76.04/76.27 69731[50:Spt:69730.0,69722.0,69727.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.27 69732[50:Spt:69730.0,69722.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 69737[50:Res:69732.0,61.1] always3(s2) || -> . % 76.04/76.27 69738[50:SSi:69737.0,691.0] || -> . % 76.04/76.27 69739[48:Spt:69738.0,74.0,67725.0] || xuntil6(s0)*+ -> . % 76.04/76.27 69740[48:Spt:69738.0,74.1] || -> node4(s0)*. % 76.04/76.27 69741[48:MRR:758.1,69739.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 69743[48:Res:69741.0,61.1] always3(s1) || -> . % 76.04/76.27 69744[48:SSi:69743.0,690.0] || -> . % 76.04/76.27 69745[47:Spt:69744.0,67715.0,67719.0] || trans(s49,s4)*+ -> . % 76.04/76.27 69746[47:Spt:69744.0,67715.1,67715.2,67715.3,67715.4] || -> trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.27 69748[47:MRR:67717.0,69745.0] || -> trans(s49,s3) trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.27 69749[47:MRR:67718.1,69745.0] xuntil6(s49) || -> trans(s49,s3) trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.27 69750[48:Spt:69746.0] || -> trans(s49,s3)*. % 76.04/76.27 69751[48:Res:69750.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s3)*. % 76.04/76.27 69753[48:Res:69750.0,60.0] || -> node2(s49,s3)*. % 76.04/76.27 69754[48:SSi:69751.1,50.0,738.0] xuntil6(s49) || -> until2p7(s3)*. % 76.04/76.27 69755[48:Res:69753.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 69756[49:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.27 69757[49:MRR:176.0,69756.0] || -> until5(s1)*. % 76.04/76.27 69758[49:MRR:68171.0,69757.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.27 69762[50:Spt:69758.2] || -> xuntil6(s1)*. % 76.04/76.27 69763[50:MRR:175.0,69762.0] || -> until5(s2)*. % 76.04/76.27 69764[50:MRR:68167.0,69763.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.27 69765[51:Spt:69764.2] || -> xuntil6(s2)*. % 76.04/76.27 69766[51:MRR:174.0,69765.0] || -> until5(s3)*. % 76.04/76.27 69767[51:MRR:68166.0,69766.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.27 69768[52:Spt:69767.2] || -> xuntil6(s3)*. % 76.04/76.27 69769[52:MRR:173.0,69768.0] || -> until5(s4)*. % 76.04/76.27 69770[52:MRR:68159.0,69769.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.27 69771[53:Spt:69770.2] || -> xuntil6(s4)*. % 76.04/76.27 69772[53:MRR:172.0,69771.0] || -> until5(s5)*. % 76.04/76.27 69773[53:MRR:68155.0,69772.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.27 69777[54:Spt:69773.2] || -> xuntil6(s5)*. % 76.04/76.27 69778[54:MRR:171.0,69777.0] || -> until5(s6)*. % 76.04/76.27 69779[54:MRR:68148.0,69778.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.27 69780[55:Spt:69779.2] || -> xuntil6(s6)*. % 76.04/76.27 69781[55:MRR:170.0,69780.0] || -> until5(s7)*. % 76.04/76.27 69782[55:MRR:68147.0,69781.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.27 69786[56:Spt:69782.2] || -> xuntil6(s7)*. % 76.04/76.27 69787[56:MRR:169.0,69786.0] || -> until5(s8)*. % 76.04/76.27 69788[56:MRR:68140.0,69787.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.27 69789[57:Spt:69788.2] || -> xuntil6(s8)*. % 76.04/76.27 69790[57:MRR:168.0,69789.0] || -> until5(s9)*. % 76.04/76.27 69791[57:MRR:68136.0,69790.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.27 69795[58:Spt:69791.2] || -> xuntil6(s9)*. % 76.04/76.27 69796[58:MRR:167.0,69795.0] || -> until5(s10)*. % 76.04/76.27 69797[58:MRR:68135.0,69796.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.27 69798[59:Spt:69797.2] || -> xuntil6(s10)*. % 76.04/76.27 69799[59:MRR:166.0,69798.0] || -> until5(s11)*. % 76.04/76.27 69800[59:MRR:68128.0,69799.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.27 69804[60:Spt:69800.2] || -> xuntil6(s11)*. % 76.04/76.27 69805[60:MRR:165.0,69804.0] || -> until5(s12)*. % 76.04/76.27 69806[60:MRR:68127.0,69805.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.27 69807[61:Spt:69806.2] || -> xuntil6(s12)*. % 76.04/76.27 69808[61:MRR:164.0,69807.0] || -> until5(s13)*. % 76.04/76.27 69809[61:MRR:68126.0,69808.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.27 69813[62:Spt:69809.2] || -> xuntil6(s13)*. % 76.04/76.27 69814[62:MRR:163.0,69813.0] || -> until5(s14)*. % 76.04/76.27 69815[62:MRR:68116.0,69814.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.27 69816[63:Spt:69815.2] || -> xuntil6(s14)*. % 76.04/76.27 69817[63:MRR:162.0,69816.0] || -> until5(s15)*. % 76.04/76.27 69818[63:MRR:68115.0,69817.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.27 69822[64:Spt:69818.2] || -> xuntil6(s15)*. % 76.04/76.27 69823[64:MRR:161.0,69822.0] || -> until5(s16)*. % 76.04/76.27 69824[64:MRR:68111.0,69823.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.27 69825[65:Spt:69824.2] || -> xuntil6(s16)*. % 76.04/76.27 69826[65:MRR:160.0,69825.0] || -> until5(s17)*. % 76.04/76.27 69827[65:MRR:68104.0,69826.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.27 69831[66:Spt:69827.2] || -> xuntil6(s17)*. % 76.04/76.27 69832[66:MRR:159.0,69831.0] || -> until5(s18)*. % 76.04/76.27 69833[66:MRR:68100.0,69832.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.27 69834[67:Spt:69833.2] || -> xuntil6(s18)*. % 76.04/76.27 69835[67:MRR:158.0,69834.0] || -> until5(s19)*. % 76.04/76.27 69836[67:MRR:68099.0,69835.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.27 69840[68:Spt:69836.2] || -> xuntil6(s19)*. % 76.04/76.27 69841[68:MRR:157.0,69840.0] || -> until5(s20)*. % 76.04/76.27 69842[68:MRR:68095.0,69841.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.27 69843[69:Spt:69842.2] || -> xuntil6(s20)*. % 76.04/76.27 69844[69:MRR:156.0,69843.0] || -> until5(s21)*. % 76.04/76.27 69845[69:MRR:68088.0,69844.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.27 69849[70:Spt:69845.2] || -> xuntil6(s21)*. % 76.04/76.27 69850[70:MRR:155.0,69849.0] || -> until5(s22)*. % 76.04/76.27 69851[70:MRR:68084.0,69850.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.27 69852[71:Spt:69851.2] || -> xuntil6(s22)*. % 76.04/76.27 69853[71:MRR:154.0,69852.0] || -> until5(s23)*. % 76.04/76.27 69854[71:MRR:68080.0,69853.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.27 69858[72:Spt:69854.2] || -> xuntil6(s23)*. % 76.04/76.27 69859[72:MRR:153.0,69858.0] || -> until5(s24)*. % 76.04/76.27 69860[72:MRR:68076.0,69859.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.27 69861[73:Spt:69860.2] || -> xuntil6(s24)*. % 76.04/76.27 69862[73:MRR:152.0,69861.0] || -> until5(s25)*. % 76.04/76.27 69863[73:MRR:68075.0,69862.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.27 69867[74:Spt:69863.2] || -> xuntil6(s25)*. % 76.04/76.27 69868[74:MRR:151.0,69867.0] || -> until5(s26)*. % 76.04/76.27 69869[74:MRR:68068.0,69868.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.27 69870[75:Spt:69869.2] || -> xuntil6(s26)*. % 76.04/76.27 69871[75:MRR:150.0,69870.0] || -> until5(s27)*. % 76.04/76.27 69872[75:MRR:68064.0,69871.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.27 69876[76:Spt:69872.2] || -> xuntil6(s27)*. % 76.04/76.27 69877[76:MRR:149.0,69876.0] || -> until5(s28)*. % 76.04/76.27 69878[76:MRR:68060.0,69877.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.27 69879[77:Spt:69878.2] || -> xuntil6(s28)*. % 76.04/76.27 69880[77:MRR:148.0,69879.0] || -> until5(s29)*. % 76.04/76.27 69881[77:MRR:68059.0,69880.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.27 69885[78:Spt:69881.2] || -> xuntil6(s29)*. % 76.04/76.27 69886[78:MRR:147.0,69885.0] || -> until5(s30)*. % 76.04/76.27 69887[78:MRR:68058.0,69886.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.27 69888[79:Spt:69887.2] || -> xuntil6(s30)*. % 76.04/76.27 69889[79:MRR:146.0,69888.0] || -> until5(s31)*. % 76.04/76.27 69890[79:MRR:68057.0,69889.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.27 69894[80:Spt:69890.2] || -> xuntil6(s31)*. % 76.04/76.27 69895[80:MRR:145.0,69894.0] || -> until5(s32)*. % 76.04/76.27 69896[80:MRR:66178.0,69895.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.27 69897[81:Spt:69896.2] || -> xuntil6(s32)*. % 76.04/76.27 69898[81:MRR:144.0,69897.0] || -> until5(s33)*. % 76.04/76.27 69899[81:MRR:68175.0,69898.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.27 69903[82:Spt:69899.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.27 69905[82:Res:69903.0,61.1] always3(s34) || -> . % 76.04/76.27 69906[82:SSi:69905.0,723.0] || -> . % 76.04/76.27 69907[82:Spt:69906.0,69899.1,69903.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.27 69908[82:Spt:69906.0,69899.0,69899.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.27 69910[82:MRR:819.2,69907.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.27 69911[82:Res:53.1,69908.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.27 69913[83:Spt:69911.1] || -> xuntil6(s33)*. % 76.04/76.27 69914[83:MRR:143.0,69913.0] || -> until5(s34)*. % 76.04/76.27 69915[83:MRR:66179.0,69914.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.27 69920[84:Spt:69915.2] || -> xuntil6(s34)*. % 76.04/76.27 69921[84:MRR:142.0,69920.0] || -> until5(s35)*. % 76.04/76.27 69922[84:MRR:68179.0,69921.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.27 69923[85:Spt:69922.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.27 69925[85:Res:69923.0,61.1] always3(s36) || -> . % 76.04/76.27 69926[85:SSi:69925.0,725.0] || -> . % 76.04/76.27 69927[85:Spt:69926.0,69922.1,69923.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.27 69928[85:Spt:69926.0,69922.0,69922.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.27 69930[85:MRR:813.2,69927.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.27 69931[85:Res:53.1,69928.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.27 69933[86:Spt:69931.1] || -> xuntil6(s35)*. % 76.04/76.27 69934[86:MRR:141.0,69933.0] || -> until5(s36)*. % 76.04/76.27 69935[86:MRR:66183.0,69934.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.27 69943[87:Spt:69935.2] || -> xuntil6(s36)*. % 76.04/76.27 69944[87:MRR:140.0,69943.0] || -> until5(s37)*. % 76.04/76.27 69945[87:MRR:68186.0,69944.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.27 69946[88:Spt:69945.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.27 69948[88:Res:69946.0,61.1] always3(s38) || -> . % 76.04/76.27 69949[88:SSi:69948.0,727.0] || -> . % 76.04/76.27 69950[88:Spt:69949.0,69945.1,69946.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.27 69951[88:Spt:69949.0,69945.0,69945.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.27 69953[88:MRR:807.2,69950.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.27 69954[88:Res:53.1,69951.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.27 69959[89:Spt:69954.1] || -> xuntil6(s37)*. % 76.04/76.27 69960[89:MRR:139.0,69959.0] || -> until5(s38)*. % 76.04/76.27 69961[89:MRR:66187.0,69960.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.27 69963[90:Spt:69961.2] || -> xuntil6(s38)*. % 76.04/76.27 69964[90:MRR:138.0,69963.0] || -> until5(s39)*. % 76.04/76.27 69965[90:MRR:68187.0,69964.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.27 69966[91:Spt:69965.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.27 69968[91:Res:69966.0,61.1] always3(s40) || -> . % 76.04/76.27 69969[91:SSi:69968.0,729.0] || -> . % 76.04/76.27 69970[91:Spt:69969.0,69965.1,69966.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.27 69971[91:Spt:69969.0,69965.0,69965.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.27 69973[91:MRR:801.2,69970.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.27 69974[91:Res:53.1,69971.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.27 69976[92:Spt:69974.1] || -> xuntil6(s39)*. % 76.04/76.27 69977[92:MRR:137.0,69976.0] || -> until5(s40)*. % 76.04/76.27 69978[92:MRR:66191.0,69977.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.27 69983[93:Spt:69978.2] || -> xuntil6(s40)*. % 76.04/76.27 69984[93:MRR:136.0,69983.0] || -> until5(s41)*. % 76.04/76.27 69985[93:MRR:68191.0,69984.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.27 69986[94:Spt:69985.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.27 69988[94:Res:69986.0,61.1] always3(s42) || -> . % 76.04/76.27 69989[94:SSi:69988.0,731.0] || -> . % 76.04/76.27 69990[94:Spt:69989.0,69985.1,69986.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.27 69991[94:Spt:69989.0,69985.0,69985.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.27 69993[94:MRR:795.2,69990.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.27 69994[94:Res:53.1,69991.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.27 69996[95:Spt:69994.1] || -> xuntil6(s41)*. % 76.04/76.27 69997[95:MRR:135.0,69996.0] || -> until5(s42)*. % 76.04/76.27 69998[95:MRR:66198.0,69997.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.27 70006[96:Spt:69998.2] || -> xuntil6(s42)*. % 76.04/76.27 70007[96:MRR:134.0,70006.0] || -> until5(s43)*. % 76.04/76.27 70008[96:MRR:68195.0,70007.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.27 70009[97:Spt:70008.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.27 70011[97:Res:70009.0,61.1] always3(s44) || -> . % 76.04/76.27 70012[97:SSi:70011.0,733.0] || -> . % 76.04/76.27 70013[97:Spt:70012.0,70008.1,70009.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.27 70014[97:Spt:70012.0,70008.0,70008.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.27 70016[97:MRR:789.2,70013.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.27 70017[97:Res:53.1,70014.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.27 70022[98:Spt:70017.1] || -> xuntil6(s43)*. % 76.04/76.27 70023[98:MRR:133.0,70022.0] || -> until5(s44)*. % 76.04/76.27 70024[98:MRR:66199.0,70023.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.27 70026[99:Spt:70024.2] || -> xuntil6(s44)*. % 76.04/76.27 70027[99:MRR:132.0,70026.0] || -> until5(s45)*. % 76.04/76.27 70028[99:MRR:68199.0,70027.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.27 70029[100:Spt:70028.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.27 70031[100:Res:70029.0,61.1] always3(s46) || -> . % 76.04/76.27 70032[100:SSi:70031.0,735.0] || -> . % 76.04/76.27 70033[100:Spt:70032.0,70028.1,70029.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.27 70034[100:Spt:70032.0,70028.0,70028.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.27 70036[100:MRR:783.2,70033.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.27 70037[100:Res:53.1,70034.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.27 70039[101:Spt:70037.1] || -> xuntil6(s45)*. % 76.04/76.27 70040[101:MRR:131.0,70039.0] || -> until5(s46)*. % 76.04/76.27 70041[101:MRR:66203.0,70040.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.27 70046[102:Spt:70041.2] || -> xuntil6(s46)*. % 76.04/76.27 70047[102:MRR:130.0,70046.0] || -> until5(s47)*. % 76.04/76.27 70048[102:MRR:68203.0,70047.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.27 70049[103:Spt:70048.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.27 70051[103:Res:70049.0,61.1] always3(s48) || -> . % 76.04/76.27 70052[103:SSi:70051.0,737.0] || -> . % 76.04/76.27 70053[103:Spt:70052.0,70048.1,70049.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.27 70054[103:Spt:70052.0,70048.0,70048.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.27 70056[103:MRR:777.2,70053.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.27 70057[103:Res:53.1,70054.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.27 70059[104:Spt:70057.1] || -> xuntil6(s47)*. % 76.04/76.27 70060[104:MRR:129.0,70059.0] || -> until5(s48)*. % 76.04/76.27 70061[104:MRR:66207.0,70060.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.27 70069[105:Spt:70061.2] || -> xuntil6(s48)*. % 76.04/76.27 70070[105:MRR:128.0,70069.0] || -> until5(s49)*. % 76.04/76.27 70071[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.27 70072[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.27 70076[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.27 70077[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.27 70078[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.27 70085[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.27 70086[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.27 70090[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.27 70094[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.27 70098[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.27 70105[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.27 70109[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.27 70110[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.27 70114[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.27 70121[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.27 70125[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.27 70126[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.27 70136[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.27 70137[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.27 70138[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.27 70145[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.27 70146[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.27 70150[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.27 70157[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.27 70158[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.27 70165[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.27 70169[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.27 70170[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.27 70174[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.27 70181[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.27 70185[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.27 70189[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.27 70191[48:SoR:69755.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 70196[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.27 70200[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.27 70207[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.27 70208[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.27 70212[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.27 70216[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.27 70220[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.27 70224[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.27 70225[48:SoR:70191.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s3,c_busy)* xuntil6(s49). % 76.04/76.27 70226[105:SSi:70225.0,50.0,738.0,70070.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s3,c_busy)* xuntil6(s49). % 76.04/76.27 70227[106:Spt:70226.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 70229[106:Res:70227.0,61.1] always3(s3) || -> . % 76.04/76.27 70230[106:SSi:70229.0,692.0,69766.0,69768.0] || -> . % 76.04/76.27 70231[106:Spt:70230.0,70226.1,70227.0] || m_main_v_state(s3,c_busy)*+ -> . % 76.04/76.27 70232[106:Spt:70230.0,70226.0,70226.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.27 70236[106:MRR:70191.2,70231.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.27 70237[106:Res:53.1,70232.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.27 70239[107:Spt:70237.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 70241[107:Res:70239.0,61.1] always3(s49) || -> . % 76.04/76.27 70242[107:SSi:70241.0,50.0,738.0,70070.0] || -> . % 76.04/76.27 70243[107:Spt:70242.0,70237.0,70239.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.27 70244[107:Spt:70242.0,70237.1] || -> xuntil6(s49)*. % 76.04/76.27 70245[107:MRR:69754.0,70244.0] || -> until2p7(s3)*. % 76.04/76.27 70246[107:MRR:199.0,70245.0] || -> until2p7(s4)* node4(s3). % 76.04/76.27 70248[107:MRR:774.2,70243.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.27 70249[108:Spt:70246.0] || -> until2p7(s4)*. % 76.04/76.27 70250[108:MRR:200.0,70249.0] || -> until2p7(s5)* node4(s4). % 76.04/76.27 70251[109:Spt:70250.0] || -> until2p7(s5)*. % 76.04/76.27 70252[109:MRR:201.0,70251.0] || -> until2p7(s6)* node4(s5). % 76.04/76.27 70253[110:Spt:70252.0] || -> until2p7(s6)*. % 76.04/76.27 70254[110:MRR:202.0,70253.0] || -> until2p7(s7)* node4(s6). % 76.04/76.27 70255[111:Spt:70254.0] || -> until2p7(s7)*. % 76.04/76.27 70256[111:MRR:203.0,70255.0] || -> until2p7(s8)* node4(s7). % 76.04/76.27 70257[112:Spt:70256.0] || -> until2p7(s8)*. % 76.04/76.27 70258[112:MRR:204.0,70257.0] || -> until2p7(s9)* node4(s8). % 76.04/76.27 70259[113:Spt:70258.0] || -> until2p7(s9)*. % 76.04/76.27 70260[113:MRR:205.0,70259.0] || -> until2p7(s10)* node4(s9). % 76.04/76.27 70261[114:Spt:70260.0] || -> until2p7(s10)*. % 76.04/76.27 70262[114:MRR:206.0,70261.0] || -> until2p7(s11)* node4(s10). % 76.04/76.27 70263[115:Spt:70262.0] || -> until2p7(s11)*. % 76.04/76.27 70264[115:MRR:207.0,70263.0] || -> until2p7(s12)* node4(s11). % 76.04/76.27 70265[116:Spt:70264.0] || -> until2p7(s12)*. % 76.04/76.27 70266[116:MRR:208.0,70265.0] || -> until2p7(s13)* node4(s12). % 76.04/76.27 70267[117:Spt:70266.0] || -> until2p7(s13)*. % 76.04/76.27 70268[117:MRR:209.0,70267.0] || -> until2p7(s14)* node4(s13). % 76.04/76.27 70269[118:Spt:70268.0] || -> until2p7(s14)*. % 76.04/76.27 70270[118:MRR:210.0,70269.0] || -> until2p7(s15)* node4(s14). % 76.04/76.27 70271[119:Spt:70270.0] || -> until2p7(s15)*. % 76.04/76.27 70272[119:MRR:211.0,70271.0] || -> until2p7(s16)* node4(s15). % 76.04/76.27 70273[120:Spt:70272.0] || -> until2p7(s16)*. % 76.04/76.27 70274[120:MRR:212.0,70273.0] || -> until2p7(s17)* node4(s16). % 76.04/76.27 70275[121:Spt:70274.0] || -> until2p7(s17)*. % 76.04/76.27 70276[121:MRR:213.0,70275.0] || -> until2p7(s18)* node4(s17). % 76.04/76.27 70277[122:Spt:70276.0] || -> until2p7(s18)*. % 76.04/76.27 70278[122:MRR:214.0,70277.0] || -> until2p7(s19)* node4(s18). % 76.04/76.27 70279[123:Spt:70278.0] || -> until2p7(s19)*. % 76.04/76.27 70280[123:MRR:215.0,70279.0] || -> until2p7(s20)* node4(s19). % 76.04/76.27 70281[124:Spt:70280.0] || -> until2p7(s20)*. % 76.04/76.27 70282[124:MRR:216.0,70281.0] || -> until2p7(s21)* node4(s20). % 76.04/76.27 70283[125:Spt:70282.0] || -> until2p7(s21)*. % 76.04/76.27 70284[125:MRR:217.0,70283.0] || -> until2p7(s22)* node4(s21). % 76.04/76.27 70285[126:Spt:70284.0] || -> until2p7(s22)*. % 76.04/76.27 70286[126:MRR:218.0,70285.0] || -> until2p7(s23)* node4(s22). % 76.04/76.27 70287[127:Spt:70286.0] || -> until2p7(s23)*. % 76.04/76.27 70288[127:MRR:219.0,70287.0] || -> until2p7(s24)* node4(s23). % 76.04/76.27 70289[128:Spt:70288.0] || -> until2p7(s24)*. % 76.04/76.27 70290[128:MRR:220.0,70289.0] || -> until2p7(s25)* node4(s24). % 76.04/76.27 70291[129:Spt:70290.0] || -> until2p7(s25)*. % 76.04/76.27 70292[129:MRR:221.0,70291.0] || -> until2p7(s26)* node4(s25). % 76.04/76.27 70293[130:Spt:70292.0] || -> until2p7(s26)*. % 76.04/76.27 70294[130:MRR:222.0,70293.0] || -> until2p7(s27)* node4(s26). % 76.04/76.27 70295[131:Spt:70294.0] || -> until2p7(s27)*. % 76.04/76.27 70296[131:MRR:223.0,70295.0] || -> until2p7(s28)* node4(s27). % 76.04/76.27 70297[132:Spt:70296.0] || -> until2p7(s28)*. % 76.04/76.27 70298[132:MRR:224.0,70297.0] || -> until2p7(s29)* node4(s28). % 76.04/76.27 70299[133:Spt:70298.0] || -> until2p7(s29)*. % 76.04/76.27 70300[133:MRR:225.0,70299.0] || -> until2p7(s30)* node4(s29). % 76.04/76.27 70301[134:Spt:70300.0] || -> until2p7(s30)*. % 76.04/76.27 70302[134:MRR:226.0,70301.0] || -> until2p7(s31)* node4(s30). % 76.04/76.27 70303[135:Spt:70302.0] || -> until2p7(s31)*. % 76.04/76.27 70304[135:MRR:227.0,70303.0] || -> until2p7(s32)* node4(s31). % 76.04/76.27 70305[136:Spt:70304.0] || -> until2p7(s32)*. % 76.04/76.27 70306[136:MRR:228.0,70305.0] || -> until2p7(s33)* node4(s32). % 76.04/76.27 70307[137:Spt:70306.0] || -> until2p7(s33)*. % 76.04/76.27 70308[137:MRR:229.0,70307.0] || -> until2p7(s34)* node4(s33). % 76.04/76.27 70309[138:Spt:70308.0] || -> until2p7(s34)*. % 76.04/76.27 70310[138:MRR:230.0,70309.0] || -> until2p7(s35)* node4(s34). % 76.04/76.27 70311[139:Spt:70310.0] || -> until2p7(s35)*. % 76.04/76.27 70312[139:MRR:231.0,70311.0] || -> until2p7(s36)* node4(s35). % 76.04/76.27 70313[140:Spt:70312.0] || -> until2p7(s36)*. % 76.04/76.27 70314[140:MRR:232.0,70313.0] || -> until2p7(s37)* node4(s36). % 76.04/76.27 70315[141:Spt:70314.0] || -> until2p7(s37)*. % 76.04/76.27 70316[141:MRR:235.0,70315.0] || -> until2p7(s38)* node4(s37). % 76.04/76.27 70317[142:Spt:70316.0] || -> until2p7(s38)*. % 76.04/76.27 70318[142:MRR:236.0,70317.0] || -> until2p7(s39)* node4(s38). % 76.04/76.27 70319[143:Spt:70318.0] || -> until2p7(s39)*. % 76.04/76.27 70320[143:MRR:237.0,70319.0] || -> until2p7(s40)* node4(s39). % 76.04/76.27 70321[144:Spt:70320.0] || -> until2p7(s40)*. % 76.04/76.27 70322[144:MRR:238.0,70321.0] || -> until2p7(s41)* node4(s40). % 76.04/76.27 70323[145:Spt:70322.0] || -> until2p7(s41)*. % 76.04/76.27 70324[145:MRR:239.0,70323.0] || -> until2p7(s42)* node4(s41). % 76.04/76.27 70325[146:Spt:70324.0] || -> until2p7(s42)*. % 76.04/76.27 70326[146:MRR:240.0,70325.0] || -> until2p7(s43)* node4(s42). % 76.04/76.27 70327[147:Spt:70326.0] || -> until2p7(s43)*. % 76.04/76.27 70328[147:MRR:241.0,70327.0] || -> until2p7(s44)* node4(s43). % 76.04/76.27 70329[148:Spt:70328.0] || -> until2p7(s44)*. % 76.04/76.27 70330[148:MRR:539.0,70329.0] || -> until2p7(s45)* node4(s44). % 76.04/76.27 70331[149:Spt:70330.0] || -> until2p7(s45)*. % 76.04/76.27 70332[149:MRR:544.0,70331.0] || -> until2p7(s46)* node4(s45). % 76.04/76.27 70333[150:Spt:70332.0] || -> until2p7(s46)*. % 76.04/76.27 70334[150:MRR:549.0,70333.0] || -> until2p7(s47)* node4(s46). % 76.04/76.27 70335[151:Spt:70334.0] || -> until2p7(s47)*. % 76.04/76.27 70336[151:MRR:554.0,70335.0] || -> until2p7(s48)* node4(s47). % 76.04/76.27 70337[152:Spt:70336.0] || -> until2p7(s48)*. % 76.04/76.27 70338[152:MRR:559.0,70337.0] || -> until2p7(s49)* node4(s48). % 76.04/76.27 70339[153:Spt:70338.0] || -> until2p7(s49)*. % 76.04/76.27 70340[153:MRR:194.0,70339.0] || -> node4(s49)*. % 76.04/76.27 70341[153:MRR:70236.0,70340.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.27 70342[153:Res:53.1,70341.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 70344[153:MRR:70342.0,70243.0] || -> . % 76.04/76.27 70345[153:Spt:70344.0,70338.0,70339.0] || until2p7(s49)*+ -> . % 76.04/76.27 70346[153:Spt:70344.0,70338.1] || -> node4(s48)*. % 76.04/76.27 70347[153:MRR:70248.0,70346.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.27 70350[153:Res:53.1,70347.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.27 70352[153:MRR:70350.0,70053.0] || -> . % 76.04/76.27 70353[152:Spt:70352.0,70336.0,70337.0] || until2p7(s48)*+ -> . % 76.04/76.27 70354[152:Spt:70352.0,70336.1] || -> node4(s47)*. % 76.04/76.27 70355[152:MRR:70056.0,70354.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.27 70358[152:Res:53.1,70355.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 70361[152:Res:70358.0,61.1] always3(s47) || -> . % 76.04/76.27 70362[152:SSi:70361.0,736.0,70047.0,70059.0,70335.0,70354.0] || -> . % 76.04/76.27 70363[151:Spt:70362.0,70334.0,70335.0] || until2p7(s47)*+ -> . % 76.04/76.27 70364[151:Spt:70362.0,70334.1] || -> node4(s46)*. % 76.04/76.27 70366[151:MRR:780.0,70364.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.27 70386[151:Res:53.1,70366.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.27 70388[151:MRR:70386.0,70033.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 70390[151:Res:70388.0,61.1] always3(s47) || -> . % 76.04/76.27 70391[151:SSi:70390.0,736.0,70047.0,70059.0] || -> . % 76.04/76.27 70392[150:Spt:70391.0,70332.0,70333.0] || until2p7(s46)*+ -> . % 76.04/76.27 70393[150:Spt:70391.0,70332.1] || -> node4(s45)*. % 76.04/76.27 70394[150:MRR:70036.0,70393.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.27 70397[150:Res:53.1,70394.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 70400[150:Res:70397.0,61.1] always3(s45) || -> . % 76.04/76.27 70401[150:SSi:70400.0,734.0,70027.0,70039.0,70331.0,70393.0] || -> . % 76.04/76.27 70402[149:Spt:70401.0,70330.0,70331.0] || until2p7(s45)*+ -> . % 76.04/76.27 70403[149:Spt:70401.0,70330.1] || -> node4(s44)*. % 76.04/76.27 70405[149:MRR:786.0,70403.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.27 70417[149:Res:53.1,70405.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.27 70419[149:MRR:70417.0,70013.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 70421[149:Res:70419.0,61.1] always3(s45) || -> . % 76.04/76.27 70422[149:SSi:70421.0,734.0,70027.0,70039.0] || -> . % 76.04/76.27 70423[148:Spt:70422.0,70328.0,70329.0] || until2p7(s44)*+ -> . % 76.04/76.27 70424[148:Spt:70422.0,70328.1] || -> node4(s43)*. % 76.04/76.27 70425[148:MRR:70016.0,70424.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.27 70428[148:Res:53.1,70425.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 70431[148:Res:70428.0,61.1] always3(s43) || -> . % 76.04/76.27 70432[148:SSi:70431.0,732.0,70007.0,70022.0,70327.0,70424.0] || -> . % 76.04/76.27 70433[147:Spt:70432.0,70326.0,70327.0] || until2p7(s43)*+ -> . % 76.04/76.27 70434[147:Spt:70432.0,70326.1] || -> node4(s42)*. % 76.04/76.27 70436[147:MRR:792.0,70434.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.27 70448[147:Res:53.1,70436.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.27 70450[147:MRR:70448.0,69990.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 70455[147:Res:70450.0,61.1] always3(s43) || -> . % 76.04/76.27 70456[147:SSi:70455.0,732.0,70007.0,70022.0] || -> . % 76.04/76.27 70457[146:Spt:70456.0,70324.0,70325.0] || until2p7(s42)*+ -> . % 76.04/76.27 70458[146:Spt:70456.0,70324.1] || -> node4(s41)*. % 76.04/76.27 70459[146:MRR:69993.0,70458.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.27 70462[146:Res:53.1,70459.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 70466[146:Res:70462.0,61.1] always3(s41) || -> . % 76.04/76.27 70467[146:SSi:70466.0,730.0,69984.0,69996.0,70323.0,70458.0] || -> . % 76.04/76.27 70468[145:Spt:70467.0,70322.0,70323.0] || until2p7(s41)*+ -> . % 76.04/76.27 70469[145:Spt:70467.0,70322.1] || -> node4(s40)*. % 76.04/76.27 70471[145:MRR:798.0,70469.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.27 70482[145:Res:53.1,70471.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.27 70484[145:MRR:70482.0,69970.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 70486[145:Res:70484.0,61.1] always3(s41) || -> . % 76.04/76.27 70487[145:SSi:70486.0,730.0,69984.0,69996.0] || -> . % 76.04/76.27 70488[144:Spt:70487.0,70320.0,70321.0] || until2p7(s40)*+ -> . % 76.04/76.27 70489[144:Spt:70487.0,70320.1] || -> node4(s39)*. % 76.04/76.27 70490[144:MRR:69973.0,70489.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.27 70494[144:Res:53.1,70490.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 70497[144:Res:70494.0,61.1] always3(s39) || -> . % 76.04/76.27 70498[144:SSi:70497.0,728.0,69964.0,69976.0,70319.0,70489.0] || -> . % 76.04/76.27 70499[143:Spt:70498.0,70318.0,70319.0] || until2p7(s39)*+ -> . % 76.04/76.27 70500[143:Spt:70498.0,70318.1] || -> node4(s38)*. % 76.04/76.27 70502[143:MRR:804.0,70500.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.27 70513[143:Res:53.1,70502.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.27 70515[143:MRR:70513.0,69950.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 70517[143:Res:70515.0,61.1] always3(s39) || -> . % 76.04/76.27 70518[143:SSi:70517.0,728.0,69964.0,69976.0] || -> . % 76.04/76.27 70519[142:Spt:70518.0,70316.0,70317.0] || until2p7(s38)*+ -> . % 76.04/76.27 70520[142:Spt:70518.0,70316.1] || -> node4(s37)*. % 76.04/76.27 70521[142:MRR:69953.0,70520.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.27 70524[142:Res:53.1,70521.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 70527[142:Res:70524.0,61.1] always3(s37) || -> . % 76.04/76.27 70528[142:SSi:70527.0,726.0,69944.0,69959.0,70315.0,70520.0] || -> . % 76.04/76.27 70529[141:Spt:70528.0,70314.0,70315.0] || until2p7(s37)*+ -> . % 76.04/76.27 70530[141:Spt:70528.0,70314.1] || -> node4(s36)*. % 76.04/76.27 70532[141:MRR:810.0,70530.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.27 70544[141:Res:53.1,70532.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.27 70546[141:MRR:70544.0,69927.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 70548[141:Res:70546.0,61.1] always3(s37) || -> . % 76.04/76.27 70549[141:SSi:70548.0,726.0,69944.0,69959.0] || -> . % 76.04/76.27 70550[140:Spt:70549.0,70312.0,70313.0] || until2p7(s36)*+ -> . % 76.04/76.27 70551[140:Spt:70549.0,70312.1] || -> node4(s35)*. % 76.04/76.27 70552[140:MRR:69930.0,70551.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.27 70555[140:Res:53.1,70552.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 70558[140:Res:70555.0,61.1] always3(s35) || -> . % 76.04/76.27 70559[140:SSi:70558.0,724.0,69921.0,69933.0,70311.0,70551.0] || -> . % 76.04/76.27 70560[139:Spt:70559.0,70310.0,70311.0] || until2p7(s35)*+ -> . % 76.04/76.27 70561[139:Spt:70559.0,70310.1] || -> node4(s34)*. % 76.04/76.27 70563[139:MRR:816.0,70561.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.27 70575[139:Res:53.1,70563.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.27 70577[139:MRR:70575.0,69907.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 70582[139:Res:70577.0,61.1] always3(s35) || -> . % 76.04/76.27 70583[139:SSi:70582.0,724.0,69921.0,69933.0] || -> . % 76.04/76.27 70584[138:Spt:70583.0,70308.0,70309.0] || until2p7(s34)*+ -> . % 76.04/76.27 70585[138:Spt:70583.0,70308.1] || -> node4(s33)*. % 76.04/76.27 70586[138:MRR:69910.0,70585.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.27 70589[138:Res:53.1,70586.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 70593[138:Res:70589.0,61.1] always3(s33) || -> . % 76.04/76.27 70594[138:SSi:70593.0,722.0,69898.0,69913.0,70307.0,70585.0] || -> . % 76.04/76.27 70595[137:Spt:70594.0,70306.0,70307.0] || until2p7(s33)*+ -> . % 76.04/76.27 70596[137:Spt:70594.0,70306.1] || -> node4(s32)*. % 76.04/76.27 70598[137:MRR:822.0,70596.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.27 70609[137:Res:53.1,70598.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.27 70611[138:Spt:70609.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 70613[138:Res:70611.0,61.1] always3(s32) || -> . % 76.04/76.27 70614[138:SSi:70613.0,721.0,69895.0,69897.0,70305.0,70596.0] || -> . % 76.04/76.27 70615[138:Spt:70614.0,70609.0,70611.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.27 70616[138:Spt:70614.0,70609.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 70620[138:Res:70616.0,61.1] always3(s33) || -> . % 76.04/76.27 70621[138:SSi:70620.0,722.0,69898.0,69913.0] || -> . % 76.04/76.27 70622[136:Spt:70621.0,70304.0,70305.0] || until2p7(s32)*+ -> . % 76.04/76.27 70623[136:Spt:70621.0,70304.1] || -> node4(s31)*. % 76.04/76.27 70625[136:MRR:825.0,70623.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.27 70632[136:Res:53.1,70625.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.27 70637[137:Spt:70632.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 70639[137:Res:70637.0,61.1] always3(s31) || -> . % 76.04/76.27 70640[137:SSi:70639.0,720.0,69889.0,69894.0,70303.0,70623.0] || -> . % 76.04/76.27 70641[137:Spt:70640.0,70632.0,70637.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.27 70642[137:Spt:70640.0,70632.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 70646[137:Res:70642.0,61.1] always3(s32) || -> . % 76.04/76.27 70647[137:SSi:70646.0,721.0,69895.0,69897.0] || -> . % 76.04/76.27 70648[135:Spt:70647.0,70302.0,70303.0] || until2p7(s31)*+ -> . % 76.04/76.27 70649[135:Spt:70647.0,70302.1] || -> node4(s30)*. % 76.04/76.27 70651[135:MRR:828.0,70649.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.27 70654[135:Res:53.1,70651.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.27 70656[136:Spt:70654.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 70658[136:Res:70656.0,61.1] always3(s30) || -> . % 76.04/76.27 70659[136:SSi:70658.0,719.0,69886.0,69888.0,70301.0,70649.0] || -> . % 76.04/76.27 70660[136:Spt:70659.0,70654.0,70656.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.27 70661[136:Spt:70659.0,70654.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 70665[136:Res:70661.0,61.1] always3(s31) || -> . % 76.04/76.27 70666[136:SSi:70665.0,720.0,69889.0,69894.0] || -> . % 76.04/76.27 70667[134:Spt:70666.0,70300.0,70301.0] || until2p7(s30)*+ -> . % 76.04/76.27 70668[134:Spt:70666.0,70300.1] || -> node4(s29)*. % 76.04/76.27 70670[134:MRR:831.0,70668.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.27 70673[134:Res:53.1,70670.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.27 70675[135:Spt:70673.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 70677[135:Res:70675.0,61.1] always3(s29) || -> . % 76.04/76.27 70678[135:SSi:70677.0,718.0,69880.0,69885.0,70299.0,70668.0] || -> . % 76.04/76.27 70679[135:Spt:70678.0,70673.0,70675.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.27 70680[135:Spt:70678.0,70673.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 70684[135:Res:70680.0,61.1] always3(s30) || -> . % 76.04/76.27 70685[135:SSi:70684.0,719.0,69886.0,69888.0] || -> . % 76.04/76.27 70686[133:Spt:70685.0,70298.0,70299.0] || until2p7(s29)*+ -> . % 76.04/76.27 70687[133:Spt:70685.0,70298.1] || -> node4(s28)*. % 76.04/76.27 70689[133:MRR:834.0,70687.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.27 70692[133:Res:53.1,70689.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.27 70694[134:Spt:70692.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 70696[134:Res:70694.0,61.1] always3(s28) || -> . % 76.04/76.27 70697[134:SSi:70696.0,717.0,69877.0,69879.0,70297.0,70687.0] || -> . % 76.04/76.27 70698[134:Spt:70697.0,70692.0,70694.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.27 70699[134:Spt:70697.0,70692.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 70703[134:Res:70699.0,61.1] always3(s29) || -> . % 76.04/76.27 70704[134:SSi:70703.0,718.0,69880.0,69885.0] || -> . % 76.04/76.27 70705[132:Spt:70704.0,70296.0,70297.0] || until2p7(s28)*+ -> . % 76.04/76.27 70706[132:Spt:70704.0,70296.1] || -> node4(s27)*. % 76.04/76.27 70708[132:MRR:837.0,70706.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.27 70711[132:Res:53.1,70708.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.27 70716[133:Spt:70711.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 70718[133:Res:70716.0,61.1] always3(s27) || -> . % 76.04/76.27 70719[133:SSi:70718.0,716.0,69871.0,69876.0,70295.0,70706.0] || -> . % 76.04/76.27 70720[133:Spt:70719.0,70711.0,70716.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.27 70721[133:Spt:70719.0,70711.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 70725[133:Res:70721.0,61.1] always3(s28) || -> . % 76.04/76.27 70726[133:SSi:70725.0,717.0,69877.0,69879.0] || -> . % 76.04/76.27 70727[131:Spt:70726.0,70294.0,70295.0] || until2p7(s27)*+ -> . % 76.04/76.27 70728[131:Spt:70726.0,70294.1] || -> node4(s26)*. % 76.04/76.27 70730[131:MRR:840.0,70728.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.27 70733[131:Res:53.1,70730.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.27 70735[132:Spt:70733.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 70737[132:Res:70735.0,61.1] always3(s26) || -> . % 76.04/76.27 70738[132:SSi:70737.0,715.0,69868.0,69870.0,70293.0,70728.0] || -> . % 76.04/76.27 70739[132:Spt:70738.0,70733.0,70735.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.27 70740[132:Spt:70738.0,70733.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 70744[132:Res:70740.0,61.1] always3(s27) || -> . % 76.04/76.27 70745[132:SSi:70744.0,716.0,69871.0,69876.0] || -> . % 76.04/76.27 70746[130:Spt:70745.0,70292.0,70293.0] || until2p7(s26)*+ -> . % 76.04/76.27 70747[130:Spt:70745.0,70292.1] || -> node4(s25)*. % 76.04/76.27 70749[130:MRR:843.0,70747.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.27 70752[130:Res:53.1,70749.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.27 70754[131:Spt:70752.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 70756[131:Res:70754.0,61.1] always3(s25) || -> . % 76.04/76.27 70757[131:SSi:70756.0,714.0,69862.0,69867.0,70291.0,70747.0] || -> . % 76.04/76.27 70758[131:Spt:70757.0,70752.0,70754.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.27 70759[131:Spt:70757.0,70752.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 70763[131:Res:70759.0,61.1] always3(s26) || -> . % 76.04/76.27 70764[131:SSi:70763.0,715.0,69868.0,69870.0] || -> . % 76.04/76.27 70765[129:Spt:70764.0,70290.0,70291.0] || until2p7(s25)*+ -> . % 76.04/76.27 70766[129:Spt:70764.0,70290.1] || -> node4(s24)*. % 76.04/76.27 70768[129:MRR:846.0,70766.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.27 70771[129:Res:53.1,70768.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.27 70773[130:Spt:70771.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 70775[130:Res:70773.0,61.1] always3(s24) || -> . % 76.04/76.27 70776[130:SSi:70775.0,713.0,69859.0,69861.0,70289.0,70766.0] || -> . % 76.04/76.27 70777[130:Spt:70776.0,70771.0,70773.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.27 70778[130:Spt:70776.0,70771.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 70782[130:Res:70778.0,61.1] always3(s25) || -> . % 76.04/76.27 70783[130:SSi:70782.0,714.0,69862.0,69867.0] || -> . % 76.04/76.27 70784[128:Spt:70783.0,70288.0,70289.0] || until2p7(s24)*+ -> . % 76.04/76.27 70785[128:Spt:70783.0,70288.1] || -> node4(s23)*. % 76.04/76.27 70787[128:MRR:849.0,70785.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.27 70790[128:Res:53.1,70787.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.27 70795[129:Spt:70790.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 70797[129:Res:70795.0,61.1] always3(s23) || -> . % 76.04/76.27 70798[129:SSi:70797.0,712.0,69853.0,69858.0,70287.0,70785.0] || -> . % 76.04/76.27 70799[129:Spt:70798.0,70790.0,70795.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.27 70800[129:Spt:70798.0,70790.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 70804[129:Res:70800.0,61.1] always3(s24) || -> . % 76.04/76.27 70805[129:SSi:70804.0,713.0,69859.0,69861.0] || -> . % 76.04/76.27 70806[127:Spt:70805.0,70286.0,70287.0] || until2p7(s23)*+ -> . % 76.04/76.27 70807[127:Spt:70805.0,70286.1] || -> node4(s22)*. % 76.04/76.27 70809[127:MRR:852.0,70807.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.27 70812[127:Res:53.1,70809.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.27 70814[128:Spt:70812.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 70816[128:Res:70814.0,61.1] always3(s22) || -> . % 76.04/76.27 70817[128:SSi:70816.0,711.0,69850.0,69852.0,70285.0,70807.0] || -> . % 76.04/76.27 70818[128:Spt:70817.0,70812.0,70814.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.27 70819[128:Spt:70817.0,70812.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 70823[128:Res:70819.0,61.1] always3(s23) || -> . % 76.04/76.27 70824[128:SSi:70823.0,712.0,69853.0,69858.0] || -> . % 76.04/76.27 70825[126:Spt:70824.0,70284.0,70285.0] || until2p7(s22)*+ -> . % 76.04/76.27 70826[126:Spt:70824.0,70284.1] || -> node4(s21)*. % 76.04/76.27 70828[126:MRR:855.0,70826.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.27 70831[126:Res:53.1,70828.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.27 70833[127:Spt:70831.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 70835[127:Res:70833.0,61.1] always3(s21) || -> . % 76.04/76.27 70836[127:SSi:70835.0,710.0,69844.0,69849.0,70283.0,70826.0] || -> . % 76.04/76.27 70837[127:Spt:70836.0,70831.0,70833.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.27 70838[127:Spt:70836.0,70831.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 70842[127:Res:70838.0,61.1] always3(s22) || -> . % 76.04/76.27 70843[127:SSi:70842.0,711.0,69850.0,69852.0] || -> . % 76.04/76.27 70844[125:Spt:70843.0,70282.0,70283.0] || until2p7(s21)*+ -> . % 76.04/76.27 70845[125:Spt:70843.0,70282.1] || -> node4(s20)*. % 76.04/76.27 70847[125:MRR:858.0,70845.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.27 70850[125:Res:53.1,70847.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.27 70852[126:Spt:70850.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 70854[126:Res:70852.0,61.1] always3(s20) || -> . % 76.04/76.27 70855[126:SSi:70854.0,709.0,69841.0,69843.0,70281.0,70845.0] || -> . % 76.04/76.27 70856[126:Spt:70855.0,70850.0,70852.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.27 70857[126:Spt:70855.0,70850.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 70861[126:Res:70857.0,61.1] always3(s21) || -> . % 76.04/76.27 70862[126:SSi:70861.0,710.0,69844.0,69849.0] || -> . % 76.04/76.27 70863[124:Spt:70862.0,70280.0,70281.0] || until2p7(s20)*+ -> . % 76.04/76.27 70864[124:Spt:70862.0,70280.1] || -> node4(s19)*. % 76.04/76.27 70866[124:MRR:861.0,70864.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.27 70869[124:Res:53.1,70866.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.27 70874[125:Spt:70869.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 70876[125:Res:70874.0,61.1] always3(s19) || -> . % 76.04/76.27 70877[125:SSi:70876.0,708.0,69835.0,69840.0,70279.0,70864.0] || -> . % 76.04/76.27 70878[125:Spt:70877.0,70869.0,70874.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.27 70879[125:Spt:70877.0,70869.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 70883[125:Res:70879.0,61.1] always3(s20) || -> . % 76.04/76.27 70884[125:SSi:70883.0,709.0,69841.0,69843.0] || -> . % 76.04/76.27 70885[123:Spt:70884.0,70278.0,70279.0] || until2p7(s19)*+ -> . % 76.04/76.27 70886[123:Spt:70884.0,70278.1] || -> node4(s18)*. % 76.04/76.27 70888[123:MRR:864.0,70886.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.27 70891[123:Res:53.1,70888.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.27 70893[124:Spt:70891.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 70895[124:Res:70893.0,61.1] always3(s18) || -> . % 76.04/76.27 70896[124:SSi:70895.0,707.0,69832.0,69834.0,70277.0,70886.0] || -> . % 76.04/76.27 70897[124:Spt:70896.0,70891.0,70893.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.27 70898[124:Spt:70896.0,70891.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 70902[124:Res:70898.0,61.1] always3(s19) || -> . % 76.04/76.27 70903[124:SSi:70902.0,708.0,69835.0,69840.0] || -> . % 76.04/76.27 70904[122:Spt:70903.0,70276.0,70277.0] || until2p7(s18)*+ -> . % 76.04/76.27 70905[122:Spt:70903.0,70276.1] || -> node4(s17)*. % 76.04/76.27 70907[122:MRR:867.0,70905.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.27 70910[122:Res:53.1,70907.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.27 70912[123:Spt:70910.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 70914[123:Res:70912.0,61.1] always3(s17) || -> . % 76.04/76.27 70915[123:SSi:70914.0,706.0,69826.0,69831.0,70275.0,70905.0] || -> . % 76.04/76.27 70916[123:Spt:70915.0,70910.0,70912.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.27 70917[123:Spt:70915.0,70910.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 70921[123:Res:70917.0,61.1] always3(s18) || -> . % 76.04/76.27 70922[123:SSi:70921.0,707.0,69832.0,69834.0] || -> . % 76.04/76.27 70923[121:Spt:70922.0,70274.0,70275.0] || until2p7(s17)*+ -> . % 76.04/76.27 70924[121:Spt:70922.0,70274.1] || -> node4(s16)*. % 76.04/76.27 70926[121:MRR:870.0,70924.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.27 70929[121:Res:53.1,70926.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.27 70931[122:Spt:70929.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 70933[122:Res:70931.0,61.1] always3(s16) || -> . % 76.04/76.27 70934[122:SSi:70933.0,705.0,69823.0,69825.0,70273.0,70924.0] || -> . % 76.04/76.27 70935[122:Spt:70934.0,70929.0,70931.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.27 70936[122:Spt:70934.0,70929.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 70940[122:Res:70936.0,61.1] always3(s17) || -> . % 76.04/76.27 70941[122:SSi:70940.0,706.0,69826.0,69831.0] || -> . % 76.04/76.27 70942[120:Spt:70941.0,70272.0,70273.0] || until2p7(s16)*+ -> . % 76.04/76.27 70943[120:Spt:70941.0,70272.1] || -> node4(s15)*. % 76.04/76.27 70945[120:MRR:873.0,70943.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.27 70948[120:Res:53.1,70945.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.27 70953[121:Spt:70948.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 70955[121:Res:70953.0,61.1] always3(s15) || -> . % 76.04/76.27 70956[121:SSi:70955.0,704.0,69817.0,69822.0,70271.0,70943.0] || -> . % 76.04/76.27 70957[121:Spt:70956.0,70948.0,70953.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.27 70958[121:Spt:70956.0,70948.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 70962[121:Res:70958.0,61.1] always3(s16) || -> . % 76.04/76.27 70963[121:SSi:70962.0,705.0,69823.0,69825.0] || -> . % 76.04/76.27 70964[119:Spt:70963.0,70270.0,70271.0] || until2p7(s15)*+ -> . % 76.04/76.27 70965[119:Spt:70963.0,70270.1] || -> node4(s14)*. % 76.04/76.27 70967[119:MRR:876.0,70965.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.27 70970[119:Res:53.1,70967.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.27 70972[120:Spt:70970.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 70974[120:Res:70972.0,61.1] always3(s14) || -> . % 76.04/76.27 70975[120:SSi:70974.0,703.0,69814.0,69816.0,70269.0,70965.0] || -> . % 76.04/76.27 70976[120:Spt:70975.0,70970.0,70972.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.27 70977[120:Spt:70975.0,70970.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 70981[120:Res:70977.0,61.1] always3(s15) || -> . % 76.04/76.27 70982[120:SSi:70981.0,704.0,69817.0,69822.0] || -> . % 76.04/76.27 70983[118:Spt:70982.0,70268.0,70269.0] || until2p7(s14)*+ -> . % 76.04/76.27 70984[118:Spt:70982.0,70268.1] || -> node4(s13)*. % 76.04/76.27 70986[118:MRR:879.0,70984.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.27 70989[118:Res:53.1,70986.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.27 70991[119:Spt:70989.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 70993[119:Res:70991.0,61.1] always3(s13) || -> . % 76.04/76.27 70994[119:SSi:70993.0,702.0,69808.0,69813.0,70267.0,70984.0] || -> . % 76.04/76.27 70995[119:Spt:70994.0,70989.0,70991.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.27 70996[119:Spt:70994.0,70989.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 71000[119:Res:70996.0,61.1] always3(s14) || -> . % 76.04/76.27 71001[119:SSi:71000.0,703.0,69814.0,69816.0] || -> . % 76.04/76.27 71002[117:Spt:71001.0,70266.0,70267.0] || until2p7(s13)*+ -> . % 76.04/76.27 71003[117:Spt:71001.0,70266.1] || -> node4(s12)*. % 76.04/76.27 71005[117:MRR:882.0,71003.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.27 71008[117:Res:53.1,71005.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.27 71010[118:Spt:71008.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 71012[118:Res:71010.0,61.1] always3(s12) || -> . % 76.04/76.27 71013[118:SSi:71012.0,701.0,69805.0,69807.0,70265.0,71003.0] || -> . % 76.04/76.27 71014[118:Spt:71013.0,71008.0,71010.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.27 71015[118:Spt:71013.0,71008.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 71019[118:Res:71015.0,61.1] always3(s13) || -> . % 76.04/76.27 71020[118:SSi:71019.0,702.0,69808.0,69813.0] || -> . % 76.04/76.27 71021[116:Spt:71020.0,70264.0,70265.0] || until2p7(s12)*+ -> . % 76.04/76.27 71022[116:Spt:71020.0,70264.1] || -> node4(s11)*. % 76.04/76.27 71024[116:MRR:885.0,71022.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.27 71027[116:Res:53.1,71024.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.27 71032[117:Spt:71027.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 71034[117:Res:71032.0,61.1] always3(s11) || -> . % 76.04/76.27 71035[117:SSi:71034.0,700.0,69799.0,69804.0,70263.0,71022.0] || -> . % 76.04/76.27 71036[117:Spt:71035.0,71027.0,71032.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.27 71037[117:Spt:71035.0,71027.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 71041[117:Res:71037.0,61.1] always3(s12) || -> . % 76.04/76.27 71042[117:SSi:71041.0,701.0,69805.0,69807.0] || -> . % 76.04/76.27 71043[115:Spt:71042.0,70262.0,70263.0] || until2p7(s11)*+ -> . % 76.04/76.27 71044[115:Spt:71042.0,70262.1] || -> node4(s10)*. % 76.04/76.27 71046[115:MRR:888.0,71044.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.27 71049[115:Res:53.1,71046.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.27 71051[116:Spt:71049.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 71053[116:Res:71051.0,61.1] always3(s10) || -> . % 76.04/76.27 71054[116:SSi:71053.0,699.0,69796.0,69798.0,70261.0,71044.0] || -> . % 76.04/76.27 71055[116:Spt:71054.0,71049.0,71051.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.27 71056[116:Spt:71054.0,71049.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 71060[116:Res:71056.0,61.1] always3(s11) || -> . % 76.04/76.27 71061[116:SSi:71060.0,700.0,69799.0,69804.0] || -> . % 76.04/76.27 71062[114:Spt:71061.0,70260.0,70261.0] || until2p7(s10)*+ -> . % 76.04/76.27 71063[114:Spt:71061.0,70260.1] || -> node4(s9)*. % 76.04/76.27 71065[114:MRR:891.0,71063.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.27 71068[114:Res:53.1,71065.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.27 71070[115:Spt:71068.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 71072[115:Res:71070.0,61.1] always3(s9) || -> . % 76.04/76.27 71073[115:SSi:71072.0,698.0,69790.0,69795.0,70259.0,71063.0] || -> . % 76.04/76.27 71074[115:Spt:71073.0,71068.0,71070.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.27 71075[115:Spt:71073.0,71068.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 71079[115:Res:71075.0,61.1] always3(s10) || -> . % 76.04/76.27 71080[115:SSi:71079.0,699.0,69796.0,69798.0] || -> . % 76.04/76.27 71081[113:Spt:71080.0,70258.0,70259.0] || until2p7(s9)*+ -> . % 76.04/76.27 71082[113:Spt:71080.0,70258.1] || -> node4(s8)*. % 76.04/76.27 71084[113:MRR:894.0,71082.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.27 71087[113:Res:53.1,71084.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.27 71089[114:Spt:71087.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 71091[114:Res:71089.0,61.1] always3(s8) || -> . % 76.04/76.27 71092[114:SSi:71091.0,697.0,69787.0,69789.0,70257.0,71082.0] || -> . % 76.04/76.27 71093[114:Spt:71092.0,71087.0,71089.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.27 71094[114:Spt:71092.0,71087.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 71098[114:Res:71094.0,61.1] always3(s9) || -> . % 76.04/76.27 71099[114:SSi:71098.0,698.0,69790.0,69795.0] || -> . % 76.04/76.27 71100[112:Spt:71099.0,70256.0,70257.0] || until2p7(s8)*+ -> . % 76.04/76.27 71101[112:Spt:71099.0,70256.1] || -> node4(s7)*. % 76.04/76.27 71103[112:MRR:897.0,71101.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.27 71106[112:Res:53.1,71103.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.27 71111[113:Spt:71106.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 71113[113:Res:71111.0,61.1] always3(s7) || -> . % 76.04/76.27 71114[113:SSi:71113.0,696.0,69781.0,69786.0,70255.0,71101.0] || -> . % 76.04/76.27 71115[113:Spt:71114.0,71106.0,71111.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.27 71116[113:Spt:71114.0,71106.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 71120[113:Res:71116.0,61.1] always3(s8) || -> . % 76.04/76.27 71121[113:SSi:71120.0,697.0,69787.0,69789.0] || -> . % 76.04/76.27 71122[111:Spt:71121.0,70254.0,70255.0] || until2p7(s7)*+ -> . % 76.04/76.27 71123[111:Spt:71121.0,70254.1] || -> node4(s6)*. % 76.04/76.27 71125[111:MRR:900.0,71123.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.27 71128[111:Res:53.1,71125.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.27 71130[112:Spt:71128.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 71132[112:Res:71130.0,61.1] always3(s6) || -> . % 76.04/76.27 71133[112:SSi:71132.0,695.0,69778.0,69780.0,70253.0,71123.0] || -> . % 76.04/76.27 71134[112:Spt:71133.0,71128.0,71130.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.27 71135[112:Spt:71133.0,71128.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 71139[112:Res:71135.0,61.1] always3(s7) || -> . % 76.04/76.27 71140[112:SSi:71139.0,696.0,69781.0,69786.0] || -> . % 76.04/76.27 71141[110:Spt:71140.0,70252.0,70253.0] || until2p7(s6)*+ -> . % 76.04/76.27 71142[110:Spt:71140.0,70252.1] || -> node4(s5)*. % 76.04/76.27 71144[110:MRR:903.0,71142.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.27 71147[110:Res:53.1,71144.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.27 71149[111:Spt:71147.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 71151[111:Res:71149.0,61.1] always3(s5) || -> . % 76.04/76.27 71152[111:SSi:71151.0,694.0,69772.0,69777.0,70251.0,71142.0] || -> . % 76.04/76.27 71153[111:Spt:71152.0,71147.0,71149.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.27 71154[111:Spt:71152.0,71147.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 71158[111:Res:71154.0,61.1] always3(s6) || -> . % 76.04/76.27 71159[111:SSi:71158.0,695.0,69778.0,69780.0] || -> . % 76.04/76.27 71160[109:Spt:71159.0,70250.0,70251.0] || until2p7(s5)*+ -> . % 76.04/76.27 71161[109:Spt:71159.0,70250.1] || -> node4(s4)*. % 76.04/76.27 71163[109:MRR:906.0,71161.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.27 71166[109:Res:53.1,71163.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.27 71168[110:Spt:71166.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 71170[110:Res:71168.0,61.1] always3(s4) || -> . % 76.04/76.27 71171[110:SSi:71170.0,693.0,69769.0,69771.0,70249.0,71161.0] || -> . % 76.04/76.27 71172[110:Spt:71171.0,71166.0,71168.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.27 71173[110:Spt:71171.0,71166.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 71177[110:Res:71173.0,61.1] always3(s5) || -> . % 76.04/76.27 71178[110:SSi:71177.0,694.0,69772.0,69777.0] || -> . % 76.04/76.27 71179[108:Spt:71178.0,70246.0,70249.0] || until2p7(s4)*+ -> . % 76.04/76.27 71180[108:Spt:71178.0,70246.1] || -> node4(s3)*. % 76.04/76.27 71182[108:MRR:909.0,71180.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.27 71185[108:Res:53.1,71182.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.27 71187[108:MRR:71185.0,70231.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 71192[108:Res:71187.0,61.1] always3(s4) || -> . % 76.04/76.27 71193[108:SSi:71192.0,693.0,69769.0,69771.0] || -> . % 76.04/76.27 71194[105:Spt:71193.0,70061.2,70069.0] || xuntil6(s48)*+ -> . % 76.04/76.27 71195[105:Spt:71193.0,70061.0,70061.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.27 71196[105:Res:53.1,71195.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.27 71198[105:MRR:71196.0,70053.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 71200[105:Res:71198.0,61.1] always3(s49) || -> . % 76.04/76.27 71201[105:SSi:71200.0,50.0,738.0] || -> . % 76.04/76.27 71202[104:Spt:71201.0,70057.1,70059.0] || xuntil6(s47)* -> . % 76.04/76.27 71203[104:Spt:71201.0,70057.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 71206[104:Res:71203.0,61.1] always3(s47) || -> . % 76.04/76.27 71207[104:SSi:71206.0,736.0,70047.0] || -> . % 76.04/76.27 71208[102:Spt:71207.0,70041.2,70046.0] || xuntil6(s46)*+ -> . % 76.04/76.27 71209[102:Spt:71207.0,70041.0,70041.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.27 71210[102:Res:53.1,71209.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.27 71212[102:MRR:71210.0,70033.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 71215[102:Res:71212.0,61.1] always3(s47) || -> . % 76.04/76.27 71216[102:SSi:71215.0,736.0] || -> . % 76.04/76.27 71217[101:Spt:71216.0,70037.1,70039.0] || xuntil6(s45)* -> . % 76.04/76.27 71218[101:Spt:71216.0,70037.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 71221[101:Res:71218.0,61.1] always3(s45) || -> . % 76.04/76.27 71222[101:SSi:71221.0,734.0,70027.0] || -> . % 76.04/76.27 71223[99:Spt:71222.0,70024.2,70026.0] || xuntil6(s44)*+ -> . % 76.04/76.27 71224[99:Spt:71222.0,70024.0,70024.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.27 71225[99:Res:53.1,71224.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.27 71227[99:MRR:71225.0,70013.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 71229[99:Res:71227.0,61.1] always3(s45) || -> . % 76.04/76.27 71230[99:SSi:71229.0,734.0] || -> . % 76.04/76.27 71231[98:Spt:71230.0,70017.1,70022.0] || xuntil6(s43)* -> . % 76.04/76.27 71232[98:Spt:71230.0,70017.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 71235[98:Res:71232.0,61.1] always3(s43) || -> . % 76.04/76.27 71236[98:SSi:71235.0,732.0,70007.0] || -> . % 76.04/76.27 71237[96:Spt:71236.0,69998.2,70006.0] || xuntil6(s42)*+ -> . % 76.04/76.27 71238[96:Spt:71236.0,69998.0,69998.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.27 71239[96:Res:53.1,71238.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.27 71241[96:MRR:71239.0,69990.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 71244[96:Res:71241.0,61.1] always3(s43) || -> . % 76.04/76.27 71245[96:SSi:71244.0,732.0] || -> . % 76.04/76.27 71246[95:Spt:71245.0,69994.1,69996.0] || xuntil6(s41)* -> . % 76.04/76.27 71247[95:Spt:71245.0,69994.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 71250[95:Res:71247.0,61.1] always3(s41) || -> . % 76.04/76.27 71251[95:SSi:71250.0,730.0,69984.0] || -> . % 76.04/76.27 71252[93:Spt:71251.0,69978.2,69983.0] || xuntil6(s40)*+ -> . % 76.04/76.27 71253[93:Spt:71251.0,69978.0,69978.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.27 71254[93:Res:53.1,71253.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.27 71256[93:MRR:71254.0,69970.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 71258[93:Res:71256.0,61.1] always3(s41) || -> . % 76.04/76.27 71259[93:SSi:71258.0,730.0] || -> . % 76.04/76.27 71260[92:Spt:71259.0,69974.1,69976.0] || xuntil6(s39)* -> . % 76.04/76.27 71261[92:Spt:71259.0,69974.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 71264[92:Res:71261.0,61.1] always3(s39) || -> . % 76.04/76.27 71265[92:SSi:71264.0,728.0,69964.0] || -> . % 76.04/76.27 71266[90:Spt:71265.0,69961.2,69963.0] || xuntil6(s38)*+ -> . % 76.04/76.27 71267[90:Spt:71265.0,69961.0,69961.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.27 71268[90:Res:53.1,71267.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.27 71270[90:MRR:71268.0,69950.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 71272[90:Res:71270.0,61.1] always3(s39) || -> . % 76.04/76.27 71273[90:SSi:71272.0,728.0] || -> . % 76.04/76.27 71274[89:Spt:71273.0,69954.1,69959.0] || xuntil6(s37)* -> . % 76.04/76.27 71275[89:Spt:71273.0,69954.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 71278[89:Res:71275.0,61.1] always3(s37) || -> . % 76.04/76.27 71279[89:SSi:71278.0,726.0,69944.0] || -> . % 76.04/76.27 71280[87:Spt:71279.0,69935.2,69943.0] || xuntil6(s36)*+ -> . % 76.04/76.27 71281[87:Spt:71279.0,69935.0,69935.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.27 71282[87:Res:53.1,71281.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.27 71284[87:MRR:71282.0,69927.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 71286[87:Res:71284.0,61.1] always3(s37) || -> . % 76.04/76.27 71287[87:SSi:71286.0,726.0] || -> . % 76.04/76.27 71288[86:Spt:71287.0,69931.1,69933.0] || xuntil6(s35)* -> . % 76.04/76.27 71289[86:Spt:71287.0,69931.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 71292[86:Res:71289.0,61.1] always3(s35) || -> . % 76.04/76.27 71293[86:SSi:71292.0,724.0,69921.0] || -> . % 76.04/76.27 71294[84:Spt:71293.0,69915.2,69920.0] || xuntil6(s34)*+ -> . % 76.04/76.27 71295[84:Spt:71293.0,69915.0,69915.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.27 71296[84:Res:53.1,71295.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.27 71298[84:MRR:71296.0,69907.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 71300[84:Res:71298.0,61.1] always3(s35) || -> . % 76.04/76.27 71301[84:SSi:71300.0,724.0] || -> . % 76.04/76.27 71302[83:Spt:71301.0,69911.1,69913.0] || xuntil6(s33)* -> . % 76.04/76.27 71303[83:Spt:71301.0,69911.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 71306[83:Res:71303.0,61.1] always3(s33) || -> . % 76.04/76.27 71307[83:SSi:71306.0,722.0,69898.0] || -> . % 76.04/76.27 71308[81:Spt:71307.0,69896.2,69897.0] || xuntil6(s32)*+ -> . % 76.04/76.27 71309[81:Spt:71307.0,69896.0,69896.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.27 71310[81:Res:53.1,71309.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.27 71312[82:Spt:71310.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 71314[82:Res:71312.0,61.1] always3(s32) || -> . % 76.04/76.27 71315[82:SSi:71314.0,721.0,69895.0] || -> . % 76.04/76.27 71316[82:Spt:71315.0,71310.0,71312.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.27 71317[82:Spt:71315.0,71310.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 71321[82:Res:71317.0,61.1] always3(s33) || -> . % 76.04/76.27 71322[82:SSi:71321.0,722.0] || -> . % 76.04/76.27 71323[80:Spt:71322.0,69890.2,69894.0] || xuntil6(s31)*+ -> . % 76.04/76.27 71324[80:Spt:71322.0,69890.0,69890.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.27 71325[80:Res:53.1,71324.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.27 71327[81:Spt:71325.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 71329[81:Res:71327.0,61.1] always3(s32) || -> . % 76.04/76.27 71330[81:SSi:71329.0,721.0] || -> . % 76.04/76.27 71331[81:Spt:71330.0,71325.1,71327.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.27 71332[81:Spt:71330.0,71325.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 71335[81:Res:71332.0,61.1] always3(s31) || -> . % 76.04/76.27 71336[81:SSi:71335.0,720.0,69889.0] || -> . % 76.04/76.27 71337[79:Spt:71336.0,69887.2,69888.0] || xuntil6(s30)*+ -> . % 76.04/76.27 71338[79:Spt:71336.0,69887.0,69887.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.27 71339[79:Res:53.1,71338.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.27 71341[80:Spt:71339.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 71343[80:Res:71341.0,61.1] always3(s31) || -> . % 76.04/76.27 71344[80:SSi:71343.0,720.0] || -> . % 76.04/76.27 71345[80:Spt:71344.0,71339.1,71341.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.27 71346[80:Spt:71344.0,71339.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 71349[80:Res:71346.0,61.1] always3(s30) || -> . % 76.04/76.27 71350[80:SSi:71349.0,719.0,69886.0] || -> . % 76.04/76.27 71351[78:Spt:71350.0,69881.2,69885.0] || xuntil6(s29)*+ -> . % 76.04/76.27 71352[78:Spt:71350.0,69881.0,69881.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.27 71353[78:Res:53.1,71352.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.27 71355[79:Spt:71353.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 71357[79:Res:71355.0,61.1] always3(s30) || -> . % 76.04/76.27 71358[79:SSi:71357.0,719.0] || -> . % 76.04/76.27 71359[79:Spt:71358.0,71353.1,71355.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.27 71360[79:Spt:71358.0,71353.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 71363[79:Res:71360.0,61.1] always3(s29) || -> . % 76.04/76.27 71364[79:SSi:71363.0,718.0,69880.0] || -> . % 76.04/76.27 71365[77:Spt:71364.0,69878.2,69879.0] || xuntil6(s28)*+ -> . % 76.04/76.27 71366[77:Spt:71364.0,69878.0,69878.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.27 71367[77:Res:53.1,71366.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.27 71369[78:Spt:71367.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 71371[78:Res:71369.0,61.1] always3(s29) || -> . % 76.04/76.27 71372[78:SSi:71371.0,718.0] || -> . % 76.04/76.27 71373[78:Spt:71372.0,71367.1,71369.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.27 71374[78:Spt:71372.0,71367.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 71377[78:Res:71374.0,61.1] always3(s28) || -> . % 76.04/76.27 71378[78:SSi:71377.0,717.0,69877.0] || -> . % 76.04/76.27 71379[76:Spt:71378.0,69872.2,69876.0] || xuntil6(s27)*+ -> . % 76.04/76.27 71380[76:Spt:71378.0,69872.0,69872.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.27 71381[76:Res:53.1,71380.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.27 71383[77:Spt:71381.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 71385[77:Res:71383.0,61.1] always3(s28) || -> . % 76.04/76.27 71386[77:SSi:71385.0,717.0] || -> . % 76.04/76.27 71387[77:Spt:71386.0,71381.1,71383.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.27 71388[77:Spt:71386.0,71381.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 71391[77:Res:71388.0,61.1] always3(s27) || -> . % 76.04/76.27 71392[77:SSi:71391.0,716.0,69871.0] || -> . % 76.04/76.27 71393[75:Spt:71392.0,69869.2,69870.0] || xuntil6(s26)*+ -> . % 76.04/76.27 71394[75:Spt:71392.0,69869.0,69869.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.27 71395[75:Res:53.1,71394.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.27 71397[76:Spt:71395.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 71399[76:Res:71397.0,61.1] always3(s27) || -> . % 76.04/76.27 71400[76:SSi:71399.0,716.0] || -> . % 76.04/76.27 71401[76:Spt:71400.0,71395.1,71397.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.27 71402[76:Spt:71400.0,71395.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 71405[76:Res:71402.0,61.1] always3(s26) || -> . % 76.04/76.27 71406[76:SSi:71405.0,715.0,69868.0] || -> . % 76.04/76.27 71407[74:Spt:71406.0,69863.2,69867.0] || xuntil6(s25)*+ -> . % 76.04/76.27 71408[74:Spt:71406.0,69863.0,69863.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.27 71409[74:Res:53.1,71408.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.27 71411[75:Spt:71409.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 71413[75:Res:71411.0,61.1] always3(s26) || -> . % 76.04/76.27 71414[75:SSi:71413.0,715.0] || -> . % 76.04/76.27 71415[75:Spt:71414.0,71409.1,71411.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.27 71416[75:Spt:71414.0,71409.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 71419[75:Res:71416.0,61.1] always3(s25) || -> . % 76.04/76.27 71420[75:SSi:71419.0,714.0,69862.0] || -> . % 76.04/76.27 71421[73:Spt:71420.0,69860.2,69861.0] || xuntil6(s24)*+ -> . % 76.04/76.27 71422[73:Spt:71420.0,69860.0,69860.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.27 71423[73:Res:53.1,71422.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.27 71428[74:Spt:71423.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 71430[74:Res:71428.0,61.1] always3(s24) || -> . % 76.04/76.27 71431[74:SSi:71430.0,713.0,69859.0] || -> . % 76.04/76.27 71432[74:Spt:71431.0,71423.0,71428.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.27 71433[74:Spt:71431.0,71423.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 71437[74:Res:71433.0,61.1] always3(s25) || -> . % 76.04/76.27 71438[74:SSi:71437.0,714.0] || -> . % 76.04/76.27 71439[72:Spt:71438.0,69854.2,69858.0] || xuntil6(s23)*+ -> . % 76.04/76.27 71440[72:Spt:71438.0,69854.0,69854.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.27 71441[72:Res:53.1,71440.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.27 71443[73:Spt:71441.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 71445[73:Res:71443.0,61.1] always3(s24) || -> . % 76.04/76.27 71446[73:SSi:71445.0,713.0] || -> . % 76.04/76.27 71447[73:Spt:71446.0,71441.1,71443.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.27 71448[73:Spt:71446.0,71441.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 71451[73:Res:71448.0,61.1] always3(s23) || -> . % 76.04/76.27 71452[73:SSi:71451.0,712.0,69853.0] || -> . % 76.04/76.27 71453[71:Spt:71452.0,69851.2,69852.0] || xuntil6(s22)*+ -> . % 76.04/76.27 71454[71:Spt:71452.0,69851.0,69851.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.27 71455[71:Res:53.1,71454.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.27 71457[72:Spt:71455.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 71459[72:Res:71457.0,61.1] always3(s23) || -> . % 76.04/76.27 71460[72:SSi:71459.0,712.0] || -> . % 76.04/76.27 71461[72:Spt:71460.0,71455.1,71457.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.27 71462[72:Spt:71460.0,71455.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 71465[72:Res:71462.0,61.1] always3(s22) || -> . % 76.04/76.27 71466[72:SSi:71465.0,711.0,69850.0] || -> . % 76.04/76.27 71467[70:Spt:71466.0,69845.2,69849.0] || xuntil6(s21)*+ -> . % 76.04/76.27 71468[70:Spt:71466.0,69845.0,69845.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.27 71469[70:Res:53.1,71468.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.27 71474[71:Spt:71469.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 71476[71:Res:71474.0,61.1] always3(s21) || -> . % 76.04/76.27 71477[71:SSi:71476.0,710.0,69844.0] || -> . % 76.04/76.27 71478[71:Spt:71477.0,71469.0,71474.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.27 71479[71:Spt:71477.0,71469.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 71483[71:Res:71479.0,61.1] always3(s22) || -> . % 76.04/76.27 71484[71:SSi:71483.0,711.0] || -> . % 76.04/76.27 71485[69:Spt:71484.0,69842.2,69843.0] || xuntil6(s20)*+ -> . % 76.04/76.27 71486[69:Spt:71484.0,69842.0,69842.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.27 71487[69:Res:53.1,71486.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.27 71489[70:Spt:71487.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 71491[70:Res:71489.0,61.1] always3(s21) || -> . % 76.04/76.27 71492[70:SSi:71491.0,710.0] || -> . % 76.04/76.27 71493[70:Spt:71492.0,71487.1,71489.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.27 71494[70:Spt:71492.0,71487.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 71497[70:Res:71494.0,61.1] always3(s20) || -> . % 76.04/76.27 71498[70:SSi:71497.0,709.0,69841.0] || -> . % 76.04/76.27 71499[68:Spt:71498.0,69836.2,69840.0] || xuntil6(s19)*+ -> . % 76.04/76.27 71500[68:Spt:71498.0,69836.0,69836.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.27 71501[68:Res:53.1,71500.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.27 71503[69:Spt:71501.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 71505[69:Res:71503.0,61.1] always3(s20) || -> . % 76.04/76.27 71506[69:SSi:71505.0,709.0] || -> . % 76.04/76.27 71507[69:Spt:71506.0,71501.1,71503.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.27 71508[69:Spt:71506.0,71501.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 71511[69:Res:71508.0,61.1] always3(s19) || -> . % 76.04/76.27 71512[69:SSi:71511.0,708.0,69835.0] || -> . % 76.04/76.27 71513[67:Spt:71512.0,69833.2,69834.0] || xuntil6(s18)*+ -> . % 76.04/76.27 71514[67:Spt:71512.0,69833.0,69833.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.27 71515[67:Res:53.1,71514.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.27 71520[68:Spt:71515.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 71522[68:Res:71520.0,61.1] always3(s18) || -> . % 76.04/76.27 71523[68:SSi:71522.0,707.0,69832.0] || -> . % 76.04/76.27 71524[68:Spt:71523.0,71515.0,71520.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.27 71525[68:Spt:71523.0,71515.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 71529[68:Res:71525.0,61.1] always3(s19) || -> . % 76.04/76.27 71530[68:SSi:71529.0,708.0] || -> . % 76.04/76.27 71531[66:Spt:71530.0,69827.2,69831.0] || xuntil6(s17)*+ -> . % 76.04/76.27 71532[66:Spt:71530.0,69827.0,69827.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.27 71533[66:Res:53.1,71532.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.27 71535[67:Spt:71533.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 71537[67:Res:71535.0,61.1] always3(s18) || -> . % 76.04/76.27 71538[67:SSi:71537.0,707.0] || -> . % 76.04/76.27 71539[67:Spt:71538.0,71533.1,71535.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.27 71540[67:Spt:71538.0,71533.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 71543[67:Res:71540.0,61.1] always3(s17) || -> . % 76.04/76.27 71544[67:SSi:71543.0,706.0,69826.0] || -> . % 76.04/76.27 71545[65:Spt:71544.0,69824.2,69825.0] || xuntil6(s16)*+ -> . % 76.04/76.27 71546[65:Spt:71544.0,69824.0,69824.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.27 71547[65:Res:53.1,71546.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.27 71549[66:Spt:71547.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 71551[66:Res:71549.0,61.1] always3(s17) || -> . % 76.04/76.27 71552[66:SSi:71551.0,706.0] || -> . % 76.04/76.27 71553[66:Spt:71552.0,71547.1,71549.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.27 71554[66:Spt:71552.0,71547.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 71557[66:Res:71554.0,61.1] always3(s16) || -> . % 76.04/76.27 71558[66:SSi:71557.0,705.0,69823.0] || -> . % 76.04/76.27 71559[64:Spt:71558.0,69818.2,69822.0] || xuntil6(s15)*+ -> . % 76.04/76.27 71560[64:Spt:71558.0,69818.0,69818.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.27 71561[64:Res:53.1,71560.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.27 71566[65:Spt:71561.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 71568[65:Res:71566.0,61.1] always3(s15) || -> . % 76.04/76.27 71569[65:SSi:71568.0,704.0,69817.0] || -> . % 76.04/76.27 71570[65:Spt:71569.0,71561.0,71566.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.27 71571[65:Spt:71569.0,71561.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 71575[65:Res:71571.0,61.1] always3(s16) || -> . % 76.04/76.27 71576[65:SSi:71575.0,705.0] || -> . % 76.04/76.27 71577[63:Spt:71576.0,69815.2,69816.0] || xuntil6(s14)*+ -> . % 76.04/76.27 71578[63:Spt:71576.0,69815.0,69815.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.27 71579[63:Res:53.1,71578.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.27 71581[64:Spt:71579.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 71583[64:Res:71581.0,61.1] always3(s15) || -> . % 76.04/76.27 71584[64:SSi:71583.0,704.0] || -> . % 76.04/76.27 71585[64:Spt:71584.0,71579.1,71581.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.27 71586[64:Spt:71584.0,71579.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 71589[64:Res:71586.0,61.1] always3(s14) || -> . % 76.04/76.27 71590[64:SSi:71589.0,703.0,69814.0] || -> . % 76.04/76.27 71591[62:Spt:71590.0,69809.2,69813.0] || xuntil6(s13)*+ -> . % 76.04/76.27 71592[62:Spt:71590.0,69809.0,69809.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.27 71593[62:Res:53.1,71592.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.27 71595[63:Spt:71593.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 71597[63:Res:71595.0,61.1] always3(s14) || -> . % 76.04/76.27 71598[63:SSi:71597.0,703.0] || -> . % 76.04/76.27 71599[63:Spt:71598.0,71593.1,71595.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.27 71600[63:Spt:71598.0,71593.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 71603[63:Res:71600.0,61.1] always3(s13) || -> . % 76.04/76.27 71604[63:SSi:71603.0,702.0,69808.0] || -> . % 76.04/76.27 71605[61:Spt:71604.0,69806.2,69807.0] || xuntil6(s12)*+ -> . % 76.04/76.27 71606[61:Spt:71604.0,69806.0,69806.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.27 71607[61:Res:53.1,71606.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.27 71612[62:Spt:71607.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 71614[62:Res:71612.0,61.1] always3(s12) || -> . % 76.04/76.27 71615[62:SSi:71614.0,701.0,69805.0] || -> . % 76.04/76.27 71616[62:Spt:71615.0,71607.0,71612.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.27 71617[62:Spt:71615.0,71607.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 71621[62:Res:71617.0,61.1] always3(s13) || -> . % 76.04/76.27 71622[62:SSi:71621.0,702.0] || -> . % 76.04/76.27 71623[60:Spt:71622.0,69800.2,69804.0] || xuntil6(s11)*+ -> . % 76.04/76.27 71624[60:Spt:71622.0,69800.0,69800.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.27 71625[60:Res:53.1,71624.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.27 71627[61:Spt:71625.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 71629[61:Res:71627.0,61.1] always3(s12) || -> . % 76.04/76.27 71630[61:SSi:71629.0,701.0] || -> . % 76.04/76.27 71631[61:Spt:71630.0,71625.1,71627.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.27 71632[61:Spt:71630.0,71625.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 71635[61:Res:71632.0,61.1] always3(s11) || -> . % 76.04/76.27 71636[61:SSi:71635.0,700.0,69799.0] || -> . % 76.04/76.27 71637[59:Spt:71636.0,69797.2,69798.0] || xuntil6(s10)*+ -> . % 76.04/76.27 71638[59:Spt:71636.0,69797.0,69797.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.27 71639[59:Res:53.1,71638.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.27 71641[60:Spt:71639.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 71643[60:Res:71641.0,61.1] always3(s11) || -> . % 76.04/76.27 71644[60:SSi:71643.0,700.0] || -> . % 76.04/76.27 71645[60:Spt:71644.0,71639.1,71641.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.27 71646[60:Spt:71644.0,71639.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 71649[60:Res:71646.0,61.1] always3(s10) || -> . % 76.04/76.27 71650[60:SSi:71649.0,699.0,69796.0] || -> . % 76.04/76.27 71651[58:Spt:71650.0,69791.2,69795.0] || xuntil6(s9)*+ -> . % 76.04/76.27 71652[58:Spt:71650.0,69791.0,69791.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.27 71653[58:Res:53.1,71652.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.27 71658[59:Spt:71653.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 71660[59:Res:71658.0,61.1] always3(s9) || -> . % 76.04/76.27 71661[59:SSi:71660.0,698.0,69790.0] || -> . % 76.04/76.27 71662[59:Spt:71661.0,71653.0,71658.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.27 71663[59:Spt:71661.0,71653.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 71667[59:Res:71663.0,61.1] always3(s10) || -> . % 76.04/76.27 71668[59:SSi:71667.0,699.0] || -> . % 76.04/76.27 71669[57:Spt:71668.0,69788.2,69789.0] || xuntil6(s8)*+ -> . % 76.04/76.27 71670[57:Spt:71668.0,69788.0,69788.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.27 71671[57:Res:53.1,71670.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.27 71673[58:Spt:71671.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 71675[58:Res:71673.0,61.1] always3(s9) || -> . % 76.04/76.27 71676[58:SSi:71675.0,698.0] || -> . % 76.04/76.27 71677[58:Spt:71676.0,71671.1,71673.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.27 71678[58:Spt:71676.0,71671.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 71681[58:Res:71678.0,61.1] always3(s8) || -> . % 76.04/76.27 71682[58:SSi:71681.0,697.0,69787.0] || -> . % 76.04/76.27 71683[56:Spt:71682.0,69782.2,69786.0] || xuntil6(s7)*+ -> . % 76.04/76.27 71684[56:Spt:71682.0,69782.0,69782.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.27 71685[56:Res:53.1,71684.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.27 71687[57:Spt:71685.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 71689[57:Res:71687.0,61.1] always3(s8) || -> . % 76.04/76.27 71690[57:SSi:71689.0,697.0] || -> . % 76.04/76.27 71691[57:Spt:71690.0,71685.1,71687.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.27 71692[57:Spt:71690.0,71685.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 71695[57:Res:71692.0,61.1] always3(s7) || -> . % 76.04/76.27 71696[57:SSi:71695.0,696.0,69781.0] || -> . % 76.04/76.27 71697[55:Spt:71696.0,69779.2,69780.0] || xuntil6(s6)*+ -> . % 76.04/76.27 71698[55:Spt:71696.0,69779.0,69779.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.27 71699[55:Res:53.1,71698.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.27 71704[56:Spt:71699.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 71706[56:Res:71704.0,61.1] always3(s6) || -> . % 76.04/76.27 71707[56:SSi:71706.0,695.0,69778.0] || -> . % 76.04/76.27 71708[56:Spt:71707.0,71699.0,71704.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.27 71709[56:Spt:71707.0,71699.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 71713[56:Res:71709.0,61.1] always3(s7) || -> . % 76.04/76.27 71714[56:SSi:71713.0,696.0] || -> . % 76.04/76.27 71715[54:Spt:71714.0,69773.2,69777.0] || xuntil6(s5)*+ -> . % 76.04/76.27 71716[54:Spt:71714.0,69773.0,69773.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.27 71717[54:Res:53.1,71716.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.27 71719[55:Spt:71717.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 71721[55:Res:71719.0,61.1] always3(s6) || -> . % 76.04/76.27 71722[55:SSi:71721.0,695.0] || -> . % 76.04/76.27 71723[55:Spt:71722.0,71717.1,71719.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.27 71724[55:Spt:71722.0,71717.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 71727[55:Res:71724.0,61.1] always3(s5) || -> . % 76.04/76.27 71728[55:SSi:71727.0,694.0,69772.0] || -> . % 76.04/76.27 71729[53:Spt:71728.0,69770.2,69771.0] || xuntil6(s4)*+ -> . % 76.04/76.27 71730[53:Spt:71728.0,69770.0,69770.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.27 71731[53:Res:53.1,71730.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.27 71733[54:Spt:71731.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 71735[54:Res:71733.0,61.1] always3(s5) || -> . % 76.04/76.27 71736[54:SSi:71735.0,694.0] || -> . % 76.04/76.27 71737[54:Spt:71736.0,71731.1,71733.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.27 71738[54:Spt:71736.0,71731.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 71741[54:Res:71738.0,61.1] always3(s4) || -> . % 76.04/76.27 71742[54:SSi:71741.0,693.0,69769.0] || -> . % 76.04/76.27 71743[52:Spt:71742.0,69767.2,69768.0] || xuntil6(s3)*+ -> . % 76.04/76.27 71744[52:Spt:71742.0,69767.0,69767.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.27 71745[52:Res:53.1,71744.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.27 71750[53:Spt:71745.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 71752[53:Res:71750.0,61.1] always3(s3) || -> . % 76.04/76.27 71753[53:SSi:71752.0,692.0,69766.0] || -> . % 76.04/76.27 71754[53:Spt:71753.0,71745.0,71750.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.27 71755[53:Spt:71753.0,71745.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 71762[53:Res:71755.0,61.1] always3(s4) || -> . % 76.04/76.27 71763[53:SSi:71762.0,693.0] || -> . % 76.04/76.27 71764[51:Spt:71763.0,69764.2,69765.0] || xuntil6(s2)*+ -> . % 76.04/76.27 71765[51:Spt:71763.0,69764.0,69764.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.27 71766[51:Res:53.1,71765.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.27 71768[52:Spt:71766.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 71770[52:Res:71768.0,61.1] always3(s2) || -> . % 76.04/76.27 71771[52:SSi:71770.0,691.0,69763.0] || -> . % 76.04/76.27 71772[52:Spt:71771.0,71766.0,71768.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.27 71773[52:Spt:71771.0,71766.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 71777[52:Res:71773.0,61.1] always3(s3) || -> . % 76.04/76.27 71778[52:SSi:71777.0,692.0] || -> . % 76.04/76.27 71779[50:Spt:71778.0,69758.2,69762.0] || xuntil6(s1)*+ -> . % 76.04/76.27 71780[50:Spt:71778.0,69758.0,69758.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.27 71781[50:Res:53.1,71780.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.27 71783[51:Spt:71781.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 71785[51:Res:71783.0,61.1] always3(s1) || -> . % 76.04/76.27 71786[51:SSi:71785.0,690.0,69757.0] || -> . % 76.04/76.27 71787[51:Spt:71786.0,71781.0,71783.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.27 71788[51:Spt:71786.0,71781.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 71793[51:Res:71788.0,61.1] always3(s2) || -> . % 76.04/76.27 71794[51:SSi:71793.0,691.0] || -> . % 76.04/76.27 71795[49:Spt:71794.0,74.0,69756.0] || xuntil6(s0)*+ -> . % 76.04/76.27 71796[49:Spt:71794.0,74.1] || -> node4(s0)*. % 76.04/76.27 71797[49:MRR:758.1,71795.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 71799[49:Res:71797.0,61.1] always3(s1) || -> . % 76.04/76.27 71800[49:SSi:71799.0,690.0] || -> . % 76.04/76.27 71801[48:Spt:71800.0,69746.0,69750.0] || trans(s49,s3)*+ -> . % 76.04/76.27 71802[48:Spt:71800.0,69746.1,69746.2,69746.3] || -> trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.27 71804[48:MRR:69748.0,71801.0] || -> trans(s49,s2) trans(s49,s1) node2(s49,s0)*. % 76.04/76.27 71805[48:MRR:69749.1,71801.0] xuntil6(s49) || -> trans(s49,s2) trans(s49,s1)* until2p7(s0). % 76.04/76.27 71806[49:Spt:71802.0] || -> trans(s49,s2)*. % 76.04/76.27 71807[49:Res:71806.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s2)*. % 76.04/76.27 71809[49:Res:71806.0,60.0] || -> node2(s49,s2)*. % 76.04/76.27 71810[49:SSi:71807.1,50.0,738.0] xuntil6(s49) || -> until2p7(s2)*. % 76.04/76.27 71811[49:Res:71809.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 71812[50:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.27 71813[50:MRR:176.0,71812.0] || -> until5(s1)*. % 76.04/76.27 71814[50:MRR:70189.0,71813.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.27 71818[51:Spt:71814.2] || -> xuntil6(s1)*. % 76.04/76.27 71819[51:MRR:175.0,71818.0] || -> until5(s2)*. % 76.04/76.27 71820[51:MRR:70185.0,71819.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.27 71824[52:Spt:71820.2] || -> xuntil6(s2)*. % 76.04/76.27 71825[52:MRR:174.0,71824.0] || -> until5(s3)*. % 76.04/76.27 71826[52:MRR:70181.0,71825.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.27 71827[53:Spt:71826.2] || -> xuntil6(s3)*. % 76.04/76.27 71828[53:MRR:173.0,71827.0] || -> until5(s4)*. % 76.04/76.27 71829[53:MRR:70174.0,71828.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.27 71833[54:Spt:71829.2] || -> xuntil6(s4)*. % 76.04/76.27 71834[54:MRR:172.0,71833.0] || -> until5(s5)*. % 76.04/76.27 71835[54:MRR:70170.0,71834.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.27 71836[55:Spt:71835.2] || -> xuntil6(s5)*. % 76.04/76.27 71837[55:MRR:171.0,71836.0] || -> until5(s6)*. % 76.04/76.27 71838[55:MRR:70169.0,71837.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.27 71842[56:Spt:71838.2] || -> xuntil6(s6)*. % 76.04/76.27 71843[56:MRR:170.0,71842.0] || -> until5(s7)*. % 76.04/76.27 71844[56:MRR:70165.0,71843.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.27 71845[57:Spt:71844.2] || -> xuntil6(s7)*. % 76.04/76.27 71846[57:MRR:169.0,71845.0] || -> until5(s8)*. % 76.04/76.27 71847[57:MRR:70158.0,71846.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.27 71851[58:Spt:71847.2] || -> xuntil6(s8)*. % 76.04/76.27 71852[58:MRR:168.0,71851.0] || -> until5(s9)*. % 76.04/76.27 71853[58:MRR:70157.0,71852.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.27 71854[59:Spt:71853.2] || -> xuntil6(s9)*. % 76.04/76.27 71855[59:MRR:167.0,71854.0] || -> until5(s10)*. % 76.04/76.27 71856[59:MRR:70150.0,71855.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.27 71860[60:Spt:71856.2] || -> xuntil6(s10)*. % 76.04/76.27 71861[60:MRR:166.0,71860.0] || -> until5(s11)*. % 76.04/76.27 71862[60:MRR:70146.0,71861.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.27 71863[61:Spt:71862.2] || -> xuntil6(s11)*. % 76.04/76.27 71864[61:MRR:165.0,71863.0] || -> until5(s12)*. % 76.04/76.27 71865[61:MRR:70145.0,71864.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.27 71869[62:Spt:71865.2] || -> xuntil6(s12)*. % 76.04/76.27 71870[62:MRR:164.0,71869.0] || -> until5(s13)*. % 76.04/76.27 71871[62:MRR:70138.0,71870.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.27 71872[63:Spt:71871.2] || -> xuntil6(s13)*. % 76.04/76.27 71873[63:MRR:163.0,71872.0] || -> until5(s14)*. % 76.04/76.27 71874[63:MRR:70137.0,71873.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.27 71878[64:Spt:71874.2] || -> xuntil6(s14)*. % 76.04/76.27 71879[64:MRR:162.0,71878.0] || -> until5(s15)*. % 76.04/76.27 71880[64:MRR:70136.0,71879.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.27 71881[65:Spt:71880.2] || -> xuntil6(s15)*. % 76.04/76.27 71882[65:MRR:161.0,71881.0] || -> until5(s16)*. % 76.04/76.27 71883[65:MRR:70126.0,71882.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.27 71887[66:Spt:71883.2] || -> xuntil6(s16)*. % 76.04/76.27 71888[66:MRR:160.0,71887.0] || -> until5(s17)*. % 76.04/76.27 71889[66:MRR:70125.0,71888.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.27 71890[67:Spt:71889.2] || -> xuntil6(s17)*. % 76.04/76.27 71891[67:MRR:159.0,71890.0] || -> until5(s18)*. % 76.04/76.27 71892[67:MRR:70121.0,71891.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.27 71896[68:Spt:71892.2] || -> xuntil6(s18)*. % 76.04/76.27 71897[68:MRR:158.0,71896.0] || -> until5(s19)*. % 76.04/76.27 71898[68:MRR:70114.0,71897.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.27 71899[69:Spt:71898.2] || -> xuntil6(s19)*. % 76.04/76.27 71900[69:MRR:157.0,71899.0] || -> until5(s20)*. % 76.04/76.27 71901[69:MRR:70110.0,71900.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.27 71905[70:Spt:71901.2] || -> xuntil6(s20)*. % 76.04/76.27 71906[70:MRR:156.0,71905.0] || -> until5(s21)*. % 76.04/76.27 71907[70:MRR:70109.0,71906.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.27 71908[71:Spt:71907.2] || -> xuntil6(s21)*. % 76.04/76.27 71909[71:MRR:155.0,71908.0] || -> until5(s22)*. % 76.04/76.27 71910[71:MRR:70105.0,71909.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.27 71914[72:Spt:71910.2] || -> xuntil6(s22)*. % 76.04/76.27 71915[72:MRR:154.0,71914.0] || -> until5(s23)*. % 76.04/76.27 71916[72:MRR:70098.0,71915.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.27 71917[73:Spt:71916.2] || -> xuntil6(s23)*. % 76.04/76.27 71918[73:MRR:153.0,71917.0] || -> until5(s24)*. % 76.04/76.27 71919[73:MRR:70094.0,71918.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.27 71923[74:Spt:71919.2] || -> xuntil6(s24)*. % 76.04/76.27 71924[74:MRR:152.0,71923.0] || -> until5(s25)*. % 76.04/76.27 71925[74:MRR:70090.0,71924.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.27 71926[75:Spt:71925.2] || -> xuntil6(s25)*. % 76.04/76.27 71927[75:MRR:151.0,71926.0] || -> until5(s26)*. % 76.04/76.27 71928[75:MRR:70086.0,71927.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.27 71932[76:Spt:71928.2] || -> xuntil6(s26)*. % 76.04/76.27 71933[76:MRR:150.0,71932.0] || -> until5(s27)*. % 76.04/76.27 71934[76:MRR:70085.0,71933.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.27 71935[77:Spt:71934.2] || -> xuntil6(s27)*. % 76.04/76.27 71936[77:MRR:149.0,71935.0] || -> until5(s28)*. % 76.04/76.27 71937[77:MRR:70078.0,71936.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.27 71941[78:Spt:71937.2] || -> xuntil6(s28)*. % 76.04/76.27 71942[78:MRR:148.0,71941.0] || -> until5(s29)*. % 76.04/76.27 71943[78:MRR:70077.0,71942.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.27 71944[79:Spt:71943.2] || -> xuntil6(s29)*. % 76.04/76.27 71945[79:MRR:147.0,71944.0] || -> until5(s30)*. % 76.04/76.27 71946[79:MRR:70076.0,71945.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.27 71950[80:Spt:71946.2] || -> xuntil6(s30)*. % 76.04/76.27 71951[80:MRR:146.0,71950.0] || -> until5(s31)*. % 76.04/76.27 71952[80:MRR:70072.0,71951.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.27 71953[81:Spt:71952.2] || -> xuntil6(s31)*. % 76.04/76.27 71954[81:MRR:145.0,71953.0] || -> until5(s32)*. % 76.04/76.27 71955[81:MRR:70071.0,71954.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.27 71959[82:Spt:71955.2] || -> xuntil6(s32)*. % 76.04/76.27 71960[82:MRR:144.0,71959.0] || -> until5(s33)*. % 76.04/76.27 71961[82:MRR:68175.0,71960.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.27 71962[83:Spt:71961.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.27 71964[83:Res:71962.0,61.1] always3(s34) || -> . % 76.04/76.27 71965[83:SSi:71964.0,723.0] || -> . % 76.04/76.27 71966[83:Spt:71965.0,71961.1,71962.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.27 71967[83:Spt:71965.0,71961.0,71961.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.27 71969[83:MRR:819.2,71966.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.27 71970[83:Res:53.1,71967.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.27 71975[84:Spt:71970.1] || -> xuntil6(s33)*. % 76.04/76.27 71976[84:MRR:143.0,71975.0] || -> until5(s34)*. % 76.04/76.27 71977[84:MRR:70196.0,71976.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.27 71979[85:Spt:71977.2] || -> xuntil6(s34)*. % 76.04/76.27 71980[85:MRR:142.0,71979.0] || -> until5(s35)*. % 76.04/76.27 71981[85:MRR:68179.0,71980.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.27 71982[86:Spt:71981.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.27 71984[86:Res:71982.0,61.1] always3(s36) || -> . % 76.04/76.27 71985[86:SSi:71984.0,725.0] || -> . % 76.04/76.27 71986[86:Spt:71985.0,71981.1,71982.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.27 71987[86:Spt:71985.0,71981.0,71981.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.27 71989[86:MRR:813.2,71986.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.27 71990[86:Res:53.1,71987.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.27 71992[87:Spt:71990.1] || -> xuntil6(s35)*. % 76.04/76.27 71993[87:MRR:141.0,71992.0] || -> until5(s36)*. % 76.04/76.27 71994[87:MRR:70200.0,71993.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.27 71999[88:Spt:71994.2] || -> xuntil6(s36)*. % 76.04/76.27 72000[88:MRR:140.0,71999.0] || -> until5(s37)*. % 76.04/76.27 72001[88:MRR:68186.0,72000.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.27 72002[89:Spt:72001.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.27 72004[89:Res:72002.0,61.1] always3(s38) || -> . % 76.04/76.27 72005[89:SSi:72004.0,727.0] || -> . % 76.04/76.27 72006[89:Spt:72005.0,72001.1,72002.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.27 72007[89:Spt:72005.0,72001.0,72001.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.27 72009[89:MRR:807.2,72006.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.27 72010[89:Res:53.1,72007.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.27 72012[90:Spt:72010.1] || -> xuntil6(s37)*. % 76.04/76.27 72013[90:MRR:139.0,72012.0] || -> until5(s38)*. % 76.04/76.27 72014[90:MRR:70207.0,72013.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.27 72022[91:Spt:72014.2] || -> xuntil6(s38)*. % 76.04/76.27 72023[91:MRR:138.0,72022.0] || -> until5(s39)*. % 76.04/76.27 72024[91:MRR:68187.0,72023.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.27 72025[92:Spt:72024.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.27 72027[92:Res:72025.0,61.1] always3(s40) || -> . % 76.04/76.27 72028[92:SSi:72027.0,729.0] || -> . % 76.04/76.27 72029[92:Spt:72028.0,72024.1,72025.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.27 72030[92:Spt:72028.0,72024.0,72024.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.27 72032[92:MRR:801.2,72029.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.27 72033[92:Res:53.1,72030.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.27 72038[93:Spt:72033.1] || -> xuntil6(s39)*. % 76.04/76.27 72039[93:MRR:137.0,72038.0] || -> until5(s40)*. % 76.04/76.27 72040[93:MRR:70208.0,72039.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.27 72042[94:Spt:72040.2] || -> xuntil6(s40)*. % 76.04/76.27 72043[94:MRR:136.0,72042.0] || -> until5(s41)*. % 76.04/76.27 72044[94:MRR:68191.0,72043.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.27 72045[95:Spt:72044.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.27 72047[95:Res:72045.0,61.1] always3(s42) || -> . % 76.04/76.27 72048[95:SSi:72047.0,731.0] || -> . % 76.04/76.27 72049[95:Spt:72048.0,72044.1,72045.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.27 72050[95:Spt:72048.0,72044.0,72044.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.27 72052[95:MRR:795.2,72049.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.27 72053[95:Res:53.1,72050.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.27 72055[96:Spt:72053.1] || -> xuntil6(s41)*. % 76.04/76.27 72056[96:MRR:135.0,72055.0] || -> until5(s42)*. % 76.04/76.27 72057[96:MRR:70212.0,72056.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.27 72062[97:Spt:72057.2] || -> xuntil6(s42)*. % 76.04/76.27 72063[97:MRR:134.0,72062.0] || -> until5(s43)*. % 76.04/76.27 72064[97:MRR:68195.0,72063.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.27 72065[98:Spt:72064.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.27 72067[98:Res:72065.0,61.1] always3(s44) || -> . % 76.04/76.27 72068[98:SSi:72067.0,733.0] || -> . % 76.04/76.27 72069[98:Spt:72068.0,72064.1,72065.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.27 72070[98:Spt:72068.0,72064.0,72064.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.27 72072[98:MRR:789.2,72069.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.27 72073[98:Res:53.1,72070.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.27 72075[99:Spt:72073.1] || -> xuntil6(s43)*. % 76.04/76.27 72076[99:MRR:133.0,72075.0] || -> until5(s44)*. % 76.04/76.27 72077[99:MRR:70216.0,72076.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.27 72085[100:Spt:72077.2] || -> xuntil6(s44)*. % 76.04/76.27 72086[100:MRR:132.0,72085.0] || -> until5(s45)*. % 76.04/76.27 72087[100:MRR:68199.0,72086.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.27 72088[101:Spt:72087.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.27 72090[101:Res:72088.0,61.1] always3(s46) || -> . % 76.04/76.27 72091[101:SSi:72090.0,735.0] || -> . % 76.04/76.27 72092[101:Spt:72091.0,72087.1,72088.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.27 72093[101:Spt:72091.0,72087.0,72087.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.27 72095[101:MRR:783.2,72092.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.27 72096[101:Res:53.1,72093.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.27 72101[102:Spt:72096.1] || -> xuntil6(s45)*. % 76.04/76.27 72102[102:MRR:131.0,72101.0] || -> until5(s46)*. % 76.04/76.27 72103[102:MRR:70220.0,72102.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.27 72105[103:Spt:72103.2] || -> xuntil6(s46)*. % 76.04/76.27 72106[103:MRR:130.0,72105.0] || -> until5(s47)*. % 76.04/76.27 72107[103:MRR:68203.0,72106.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.27 72108[104:Spt:72107.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.27 72110[104:Res:72108.0,61.1] always3(s48) || -> . % 76.04/76.27 72111[104:SSi:72110.0,737.0] || -> . % 76.04/76.27 72112[104:Spt:72111.0,72107.1,72108.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.27 72113[104:Spt:72111.0,72107.0,72107.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.27 72115[104:MRR:777.2,72112.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.27 72116[104:Res:53.1,72113.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.27 72118[105:Spt:72116.1] || -> xuntil6(s47)*. % 76.04/76.27 72119[105:MRR:129.0,72118.0] || -> until5(s48)*. % 76.04/76.27 72120[105:MRR:70224.0,72119.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.27 72125[106:Spt:72120.2] || -> xuntil6(s48)*. % 76.04/76.27 72126[106:MRR:128.0,72125.0] || -> until5(s49)*. % 76.04/76.27 72127[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.27 72131[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.27 72132[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.27 72133[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.27 72140[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.27 72141[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.27 72145[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.27 72149[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.27 72153[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.27 72160[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.27 72161[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.27 72165[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.27 72172[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.27 72173[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.27 72180[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.27 72184[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.27 72185[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.27 72189[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.27 72196[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.27 72200[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.27 72201[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.27 72211[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.27 72212[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.27 72213[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.27 72220[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.27 72221[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.27 72225[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.27 72232[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.27 72233[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.27 72240[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.27 72244[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.27 72251[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.27 72253[49:SoR:71811.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 72255[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.27 72262[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.27 72263[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.27 72267[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.27 72271[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.27 72275[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.27 72282[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.27 72283[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.27 72284[49:SoR:72253.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s2,c_busy)* xuntil6(s49). % 76.04/76.27 72285[106:SSi:72284.0,50.0,738.0,72126.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s2,c_busy)* xuntil6(s49). % 76.04/76.27 72286[107:Spt:72285.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 72288[107:Res:72286.0,61.1] always3(s2) || -> . % 76.04/76.27 72289[107:SSi:72288.0,691.0,71819.0,71824.0] || -> . % 76.04/76.27 72290[107:Spt:72289.0,72285.1,72286.0] || m_main_v_state(s2,c_busy)*+ -> . % 76.04/76.27 72291[107:Spt:72289.0,72285.0,72285.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.27 72295[107:MRR:72253.2,72290.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.27 72296[107:Res:53.1,72291.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.27 72298[108:Spt:72296.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 72300[108:Res:72298.0,61.1] always3(s49) || -> . % 76.04/76.27 72301[108:SSi:72300.0,50.0,738.0,72126.0] || -> . % 76.04/76.27 72302[108:Spt:72301.0,72296.0,72298.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.27 72303[108:Spt:72301.0,72296.1] || -> xuntil6(s49)*. % 76.04/76.27 72304[108:MRR:71810.0,72303.0] || -> until2p7(s2)*. % 76.04/76.27 72305[108:MRR:198.0,72304.0] || -> until2p7(s3)* node4(s2). % 76.04/76.27 72307[108:MRR:774.2,72302.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.27 72308[109:Spt:72305.0] || -> until2p7(s3)*. % 76.04/76.27 72309[109:MRR:199.0,72308.0] || -> until2p7(s4)* node4(s3). % 76.04/76.27 72310[110:Spt:72309.0] || -> until2p7(s4)*. % 76.04/76.27 72311[110:MRR:200.0,72310.0] || -> until2p7(s5)* node4(s4). % 76.04/76.27 72312[111:Spt:72311.0] || -> until2p7(s5)*. % 76.04/76.27 72313[111:MRR:201.0,72312.0] || -> until2p7(s6)* node4(s5). % 76.04/76.27 72314[112:Spt:72313.0] || -> until2p7(s6)*. % 76.04/76.27 72315[112:MRR:202.0,72314.0] || -> until2p7(s7)* node4(s6). % 76.04/76.27 72316[113:Spt:72315.0] || -> until2p7(s7)*. % 76.04/76.27 72317[113:MRR:203.0,72316.0] || -> until2p7(s8)* node4(s7). % 76.04/76.27 72318[114:Spt:72317.0] || -> until2p7(s8)*. % 76.04/76.27 72319[114:MRR:204.0,72318.0] || -> until2p7(s9)* node4(s8). % 76.04/76.27 72320[115:Spt:72319.0] || -> until2p7(s9)*. % 76.04/76.27 72321[115:MRR:205.0,72320.0] || -> until2p7(s10)* node4(s9). % 76.04/76.27 72322[116:Spt:72321.0] || -> until2p7(s10)*. % 76.04/76.27 72323[116:MRR:206.0,72322.0] || -> until2p7(s11)* node4(s10). % 76.04/76.27 72324[117:Spt:72323.0] || -> until2p7(s11)*. % 76.04/76.27 72325[117:MRR:207.0,72324.0] || -> until2p7(s12)* node4(s11). % 76.04/76.27 72326[118:Spt:72325.0] || -> until2p7(s12)*. % 76.04/76.27 72327[118:MRR:208.0,72326.0] || -> until2p7(s13)* node4(s12). % 76.04/76.27 72328[119:Spt:72327.0] || -> until2p7(s13)*. % 76.04/76.27 72329[119:MRR:209.0,72328.0] || -> until2p7(s14)* node4(s13). % 76.04/76.27 72330[120:Spt:72329.0] || -> until2p7(s14)*. % 76.04/76.27 72331[120:MRR:210.0,72330.0] || -> until2p7(s15)* node4(s14). % 76.04/76.27 72332[121:Spt:72331.0] || -> until2p7(s15)*. % 76.04/76.27 72333[121:MRR:211.0,72332.0] || -> until2p7(s16)* node4(s15). % 76.04/76.27 72334[122:Spt:72333.0] || -> until2p7(s16)*. % 76.04/76.27 72335[122:MRR:212.0,72334.0] || -> until2p7(s17)* node4(s16). % 76.04/76.27 72336[123:Spt:72335.0] || -> until2p7(s17)*. % 76.04/76.27 72337[123:MRR:213.0,72336.0] || -> until2p7(s18)* node4(s17). % 76.04/76.27 72338[124:Spt:72337.0] || -> until2p7(s18)*. % 76.04/76.27 72339[124:MRR:214.0,72338.0] || -> until2p7(s19)* node4(s18). % 76.04/76.27 72340[125:Spt:72339.0] || -> until2p7(s19)*. % 76.04/76.27 72341[125:MRR:215.0,72340.0] || -> until2p7(s20)* node4(s19). % 76.04/76.27 72342[126:Spt:72341.0] || -> until2p7(s20)*. % 76.04/76.27 72343[126:MRR:216.0,72342.0] || -> until2p7(s21)* node4(s20). % 76.04/76.27 72344[127:Spt:72343.0] || -> until2p7(s21)*. % 76.04/76.27 72345[127:MRR:217.0,72344.0] || -> until2p7(s22)* node4(s21). % 76.04/76.27 72346[128:Spt:72345.0] || -> until2p7(s22)*. % 76.04/76.27 72347[128:MRR:218.0,72346.0] || -> until2p7(s23)* node4(s22). % 76.04/76.27 72348[129:Spt:72347.0] || -> until2p7(s23)*. % 76.04/76.27 72349[129:MRR:219.0,72348.0] || -> until2p7(s24)* node4(s23). % 76.04/76.27 72350[130:Spt:72349.0] || -> until2p7(s24)*. % 76.04/76.27 72351[130:MRR:220.0,72350.0] || -> until2p7(s25)* node4(s24). % 76.04/76.27 72352[131:Spt:72351.0] || -> until2p7(s25)*. % 76.04/76.27 72353[131:MRR:221.0,72352.0] || -> until2p7(s26)* node4(s25). % 76.04/76.27 72354[132:Spt:72353.0] || -> until2p7(s26)*. % 76.04/76.27 72355[132:MRR:222.0,72354.0] || -> until2p7(s27)* node4(s26). % 76.04/76.27 72356[133:Spt:72355.0] || -> until2p7(s27)*. % 76.04/76.27 72357[133:MRR:223.0,72356.0] || -> until2p7(s28)* node4(s27). % 76.04/76.27 72358[134:Spt:72357.0] || -> until2p7(s28)*. % 76.04/76.27 72359[134:MRR:224.0,72358.0] || -> until2p7(s29)* node4(s28). % 76.04/76.27 72360[135:Spt:72359.0] || -> until2p7(s29)*. % 76.04/76.27 72361[135:MRR:225.0,72360.0] || -> until2p7(s30)* node4(s29). % 76.04/76.27 72362[136:Spt:72361.0] || -> until2p7(s30)*. % 76.04/76.27 72363[136:MRR:226.0,72362.0] || -> until2p7(s31)* node4(s30). % 76.04/76.27 72364[137:Spt:72363.0] || -> until2p7(s31)*. % 76.04/76.27 72365[137:MRR:227.0,72364.0] || -> until2p7(s32)* node4(s31). % 76.04/76.27 72366[138:Spt:72365.0] || -> until2p7(s32)*. % 76.04/76.27 72367[138:MRR:228.0,72366.0] || -> until2p7(s33)* node4(s32). % 76.04/76.27 72368[139:Spt:72367.0] || -> until2p7(s33)*. % 76.04/76.27 72369[139:MRR:229.0,72368.0] || -> until2p7(s34)* node4(s33). % 76.04/76.27 72370[140:Spt:72369.0] || -> until2p7(s34)*. % 76.04/76.27 72371[140:MRR:230.0,72370.0] || -> until2p7(s35)* node4(s34). % 76.04/76.27 72372[141:Spt:72371.0] || -> until2p7(s35)*. % 76.04/76.27 72373[141:MRR:231.0,72372.0] || -> until2p7(s36)* node4(s35). % 76.04/76.27 72374[142:Spt:72373.0] || -> until2p7(s36)*. % 76.04/76.27 72375[142:MRR:232.0,72374.0] || -> until2p7(s37)* node4(s36). % 76.04/76.27 72376[143:Spt:72375.0] || -> until2p7(s37)*. % 76.04/76.27 72377[143:MRR:235.0,72376.0] || -> until2p7(s38)* node4(s37). % 76.04/76.27 72378[144:Spt:72377.0] || -> until2p7(s38)*. % 76.04/76.27 72379[144:MRR:236.0,72378.0] || -> until2p7(s39)* node4(s38). % 76.04/76.27 72380[145:Spt:72379.0] || -> until2p7(s39)*. % 76.04/76.27 72381[145:MRR:237.0,72380.0] || -> until2p7(s40)* node4(s39). % 76.04/76.27 72382[146:Spt:72381.0] || -> until2p7(s40)*. % 76.04/76.27 72383[146:MRR:238.0,72382.0] || -> until2p7(s41)* node4(s40). % 76.04/76.27 72384[147:Spt:72383.0] || -> until2p7(s41)*. % 76.04/76.27 72385[147:MRR:239.0,72384.0] || -> until2p7(s42)* node4(s41). % 76.04/76.27 72386[148:Spt:72385.0] || -> until2p7(s42)*. % 76.04/76.27 72387[148:MRR:240.0,72386.0] || -> until2p7(s43)* node4(s42). % 76.04/76.27 72388[149:Spt:72387.0] || -> until2p7(s43)*. % 76.04/76.27 72389[149:MRR:241.0,72388.0] || -> until2p7(s44)* node4(s43). % 76.04/76.27 72390[150:Spt:72389.0] || -> until2p7(s44)*. % 76.04/76.27 72391[150:MRR:539.0,72390.0] || -> until2p7(s45)* node4(s44). % 76.04/76.27 72392[151:Spt:72391.0] || -> until2p7(s45)*. % 76.04/76.27 72393[151:MRR:544.0,72392.0] || -> until2p7(s46)* node4(s45). % 76.04/76.27 72394[152:Spt:72393.0] || -> until2p7(s46)*. % 76.04/76.27 72395[152:MRR:549.0,72394.0] || -> until2p7(s47)* node4(s46). % 76.04/76.27 72396[153:Spt:72395.0] || -> until2p7(s47)*. % 76.04/76.27 72397[153:MRR:554.0,72396.0] || -> until2p7(s48)* node4(s47). % 76.04/76.27 72398[154:Spt:72397.0] || -> until2p7(s48)*. % 76.04/76.27 72399[154:MRR:559.0,72398.0] || -> until2p7(s49)* node4(s48). % 76.04/76.27 72400[155:Spt:72399.0] || -> until2p7(s49)*. % 76.04/76.27 72401[155:MRR:194.0,72400.0] || -> node4(s49)*. % 76.04/76.27 72402[155:MRR:72295.0,72401.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.27 72403[155:Res:53.1,72402.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 72405[155:MRR:72403.0,72302.0] || -> . % 76.04/76.27 72406[155:Spt:72405.0,72399.0,72400.0] || until2p7(s49)*+ -> . % 76.04/76.27 72407[155:Spt:72405.0,72399.1] || -> node4(s48)*. % 76.04/76.27 72408[155:MRR:72307.0,72407.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.27 72411[155:Res:53.1,72408.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.27 72413[155:MRR:72411.0,72112.0] || -> . % 76.04/76.27 72414[154:Spt:72413.0,72397.0,72398.0] || until2p7(s48)*+ -> . % 76.04/76.27 72415[154:Spt:72413.0,72397.1] || -> node4(s47)*. % 76.04/76.27 72416[154:MRR:72115.0,72415.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.27 72419[154:Res:53.1,72416.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 72423[154:Res:72419.0,61.1] always3(s47) || -> . % 76.04/76.27 72424[154:SSi:72423.0,736.0,72106.0,72118.0,72396.0,72415.0] || -> . % 76.04/76.27 72425[153:Spt:72424.0,72395.0,72396.0] || until2p7(s47)*+ -> . % 76.04/76.27 72426[153:Spt:72424.0,72395.1] || -> node4(s46)*. % 76.04/76.27 72428[153:MRR:780.0,72426.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.27 72450[153:Res:53.1,72428.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.27 72452[153:MRR:72450.0,72092.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 72454[153:Res:72452.0,61.1] always3(s47) || -> . % 76.04/76.27 72455[153:SSi:72454.0,736.0,72106.0,72118.0] || -> . % 76.04/76.27 72456[152:Spt:72455.0,72393.0,72394.0] || until2p7(s46)*+ -> . % 76.04/76.27 72457[152:Spt:72455.0,72393.1] || -> node4(s45)*. % 76.04/76.27 72458[152:MRR:72095.0,72457.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.27 72462[152:Res:53.1,72458.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 72465[152:Res:72462.0,61.1] always3(s45) || -> . % 76.04/76.27 72466[152:SSi:72465.0,734.0,72086.0,72101.0,72392.0,72457.0] || -> . % 76.04/76.27 72467[151:Spt:72466.0,72391.0,72392.0] || until2p7(s45)*+ -> . % 76.04/76.27 72468[151:Spt:72466.0,72391.1] || -> node4(s44)*. % 76.04/76.27 72470[151:MRR:786.0,72468.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.27 72481[151:Res:53.1,72470.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.27 72483[151:MRR:72481.0,72069.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 72485[151:Res:72483.0,61.1] always3(s45) || -> . % 76.04/76.27 72486[151:SSi:72485.0,734.0,72086.0,72101.0] || -> . % 76.04/76.27 72487[150:Spt:72486.0,72389.0,72390.0] || until2p7(s44)*+ -> . % 76.04/76.27 72488[150:Spt:72486.0,72389.1] || -> node4(s43)*. % 76.04/76.27 72489[150:MRR:72072.0,72488.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.27 72492[150:Res:53.1,72489.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 72495[150:Res:72492.0,61.1] always3(s43) || -> . % 76.04/76.27 72496[150:SSi:72495.0,732.0,72063.0,72075.0,72388.0,72488.0] || -> . % 76.04/76.27 72497[149:Spt:72496.0,72387.0,72388.0] || until2p7(s43)*+ -> . % 76.04/76.27 72498[149:Spt:72496.0,72387.1] || -> node4(s42)*. % 76.04/76.27 72500[149:MRR:792.0,72498.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.27 72512[149:Res:53.1,72500.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.27 72514[149:MRR:72512.0,72049.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 72516[149:Res:72514.0,61.1] always3(s43) || -> . % 76.04/76.27 72517[149:SSi:72516.0,732.0,72063.0,72075.0] || -> . % 76.04/76.27 72518[148:Spt:72517.0,72385.0,72386.0] || until2p7(s42)*+ -> . % 76.04/76.27 72519[148:Spt:72517.0,72385.1] || -> node4(s41)*. % 76.04/76.27 72520[148:MRR:72052.0,72519.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.27 72523[148:Res:53.1,72520.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 72526[148:Res:72523.0,61.1] always3(s41) || -> . % 76.04/76.27 72527[148:SSi:72526.0,730.0,72043.0,72055.0,72384.0,72519.0] || -> . % 76.04/76.27 72528[147:Spt:72527.0,72383.0,72384.0] || until2p7(s41)*+ -> . % 76.04/76.27 72529[147:Spt:72527.0,72383.1] || -> node4(s40)*. % 76.04/76.27 72531[147:MRR:798.0,72529.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.27 72543[147:Res:53.1,72531.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.27 72545[147:MRR:72543.0,72029.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 72550[147:Res:72545.0,61.1] always3(s41) || -> . % 76.04/76.27 72551[147:SSi:72550.0,730.0,72043.0,72055.0] || -> . % 76.04/76.27 72552[146:Spt:72551.0,72381.0,72382.0] || until2p7(s40)*+ -> . % 76.04/76.27 72553[146:Spt:72551.0,72381.1] || -> node4(s39)*. % 76.04/76.27 72554[146:MRR:72032.0,72553.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.27 72557[146:Res:53.1,72554.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 72561[146:Res:72557.0,61.1] always3(s39) || -> . % 76.04/76.27 72562[146:SSi:72561.0,728.0,72023.0,72038.0,72380.0,72553.0] || -> . % 76.04/76.27 72563[145:Spt:72562.0,72379.0,72380.0] || until2p7(s39)*+ -> . % 76.04/76.27 72564[145:Spt:72562.0,72379.1] || -> node4(s38)*. % 76.04/76.27 72566[145:MRR:804.0,72564.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.27 72577[145:Res:53.1,72566.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.27 72579[145:MRR:72577.0,72006.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 72581[145:Res:72579.0,61.1] always3(s39) || -> . % 76.04/76.27 72582[145:SSi:72581.0,728.0,72023.0,72038.0] || -> . % 76.04/76.27 72583[144:Spt:72582.0,72377.0,72378.0] || until2p7(s38)*+ -> . % 76.04/76.27 72584[144:Spt:72582.0,72377.1] || -> node4(s37)*. % 76.04/76.27 72585[144:MRR:72009.0,72584.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.27 72589[144:Res:53.1,72585.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 72592[144:Res:72589.0,61.1] always3(s37) || -> . % 76.04/76.27 72593[144:SSi:72592.0,726.0,72000.0,72012.0,72376.0,72584.0] || -> . % 76.04/76.27 72594[143:Spt:72593.0,72375.0,72376.0] || until2p7(s37)*+ -> . % 76.04/76.27 72595[143:Spt:72593.0,72375.1] || -> node4(s36)*. % 76.04/76.27 72597[143:MRR:810.0,72595.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.27 72608[143:Res:53.1,72597.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.27 72610[143:MRR:72608.0,71986.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 72612[143:Res:72610.0,61.1] always3(s37) || -> . % 76.04/76.27 72613[143:SSi:72612.0,726.0,72000.0,72012.0] || -> . % 76.04/76.27 72614[142:Spt:72613.0,72373.0,72374.0] || until2p7(s36)*+ -> . % 76.04/76.27 72615[142:Spt:72613.0,72373.1] || -> node4(s35)*. % 76.04/76.27 72616[142:MRR:71989.0,72615.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.27 72619[142:Res:53.1,72616.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 72622[142:Res:72619.0,61.1] always3(s35) || -> . % 76.04/76.27 72623[142:SSi:72622.0,724.0,71980.0,71992.0,72372.0,72615.0] || -> . % 76.04/76.27 72624[141:Spt:72623.0,72371.0,72372.0] || until2p7(s35)*+ -> . % 76.04/76.27 72625[141:Spt:72623.0,72371.1] || -> node4(s34)*. % 76.04/76.27 72627[141:MRR:816.0,72625.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.27 72639[141:Res:53.1,72627.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.27 72641[141:MRR:72639.0,71966.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 72643[141:Res:72641.0,61.1] always3(s35) || -> . % 76.04/76.27 72644[141:SSi:72643.0,724.0,71980.0,71992.0] || -> . % 76.04/76.27 72645[140:Spt:72644.0,72369.0,72370.0] || until2p7(s34)*+ -> . % 76.04/76.27 72646[140:Spt:72644.0,72369.1] || -> node4(s33)*. % 76.04/76.27 72647[140:MRR:71969.0,72646.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.27 72650[140:Res:53.1,72647.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 72653[140:Res:72650.0,61.1] always3(s33) || -> . % 76.04/76.27 72654[140:SSi:72653.0,722.0,71960.0,71975.0,72368.0,72646.0] || -> . % 76.04/76.27 72655[139:Spt:72654.0,72367.0,72368.0] || until2p7(s33)*+ -> . % 76.04/76.27 72656[139:Spt:72654.0,72367.1] || -> node4(s32)*. % 76.04/76.27 72658[139:MRR:822.0,72656.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.27 72670[139:Res:53.1,72658.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.27 72675[140:Spt:72670.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 72677[140:Res:72675.0,61.1] always3(s32) || -> . % 76.04/76.27 72678[140:SSi:72677.0,721.0,71954.0,71959.0,72366.0,72656.0] || -> . % 76.04/76.27 72679[140:Spt:72678.0,72670.0,72675.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.27 72680[140:Spt:72678.0,72670.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 72684[140:Res:72680.0,61.1] always3(s33) || -> . % 76.04/76.27 72685[140:SSi:72684.0,722.0,71960.0,71975.0] || -> . % 76.04/76.27 72686[138:Spt:72685.0,72365.0,72366.0] || until2p7(s32)*+ -> . % 76.04/76.27 72687[138:Spt:72685.0,72365.1] || -> node4(s31)*. % 76.04/76.27 72689[138:MRR:825.0,72687.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.27 72696[138:Res:53.1,72689.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.27 72698[139:Spt:72696.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 72700[139:Res:72698.0,61.1] always3(s31) || -> . % 76.04/76.27 72701[139:SSi:72700.0,720.0,71951.0,71953.0,72364.0,72687.0] || -> . % 76.04/76.27 72702[139:Spt:72701.0,72696.0,72698.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.27 72703[139:Spt:72701.0,72696.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 72707[139:Res:72703.0,61.1] always3(s32) || -> . % 76.04/76.27 72708[139:SSi:72707.0,721.0,71954.0,71959.0] || -> . % 76.04/76.27 72709[137:Spt:72708.0,72363.0,72364.0] || until2p7(s31)*+ -> . % 76.04/76.27 72710[137:Spt:72708.0,72363.1] || -> node4(s30)*. % 76.04/76.27 72712[137:MRR:828.0,72710.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.27 72715[137:Res:53.1,72712.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.27 72720[138:Spt:72715.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 72722[138:Res:72720.0,61.1] always3(s30) || -> . % 76.04/76.27 72723[138:SSi:72722.0,719.0,71945.0,71950.0,72362.0,72710.0] || -> . % 76.04/76.27 72724[138:Spt:72723.0,72715.0,72720.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.27 72725[138:Spt:72723.0,72715.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 72729[138:Res:72725.0,61.1] always3(s31) || -> . % 76.04/76.27 72730[138:SSi:72729.0,720.0,71951.0,71953.0] || -> . % 76.04/76.27 72731[136:Spt:72730.0,72361.0,72362.0] || until2p7(s30)*+ -> . % 76.04/76.27 72732[136:Spt:72730.0,72361.1] || -> node4(s29)*. % 76.04/76.27 72734[136:MRR:831.0,72732.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.27 72737[136:Res:53.1,72734.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.27 72739[137:Spt:72737.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 72741[137:Res:72739.0,61.1] always3(s29) || -> . % 76.04/76.27 72742[137:SSi:72741.0,718.0,71942.0,71944.0,72360.0,72732.0] || -> . % 76.04/76.27 72743[137:Spt:72742.0,72737.0,72739.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.27 72744[137:Spt:72742.0,72737.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 72748[137:Res:72744.0,61.1] always3(s30) || -> . % 76.04/76.27 72749[137:SSi:72748.0,719.0,71945.0,71950.0] || -> . % 76.04/76.27 72750[135:Spt:72749.0,72359.0,72360.0] || until2p7(s29)*+ -> . % 76.04/76.27 72751[135:Spt:72749.0,72359.1] || -> node4(s28)*. % 76.04/76.27 72753[135:MRR:834.0,72751.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.27 72756[135:Res:53.1,72753.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.27 72758[136:Spt:72756.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 72760[136:Res:72758.0,61.1] always3(s28) || -> . % 76.04/76.27 72761[136:SSi:72760.0,717.0,71936.0,71941.0,72358.0,72751.0] || -> . % 76.04/76.27 72762[136:Spt:72761.0,72756.0,72758.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.27 72763[136:Spt:72761.0,72756.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 72767[136:Res:72763.0,61.1] always3(s29) || -> . % 76.04/76.27 72768[136:SSi:72767.0,718.0,71942.0,71944.0] || -> . % 76.04/76.27 72769[134:Spt:72768.0,72357.0,72358.0] || until2p7(s28)*+ -> . % 76.04/76.27 72770[134:Spt:72768.0,72357.1] || -> node4(s27)*. % 76.04/76.27 72772[134:MRR:837.0,72770.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.27 72775[134:Res:53.1,72772.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.27 72777[135:Spt:72775.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 72779[135:Res:72777.0,61.1] always3(s27) || -> . % 76.04/76.27 72780[135:SSi:72779.0,716.0,71933.0,71935.0,72356.0,72770.0] || -> . % 76.04/76.27 72781[135:Spt:72780.0,72775.0,72777.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.27 72782[135:Spt:72780.0,72775.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 72786[135:Res:72782.0,61.1] always3(s28) || -> . % 76.04/76.27 72787[135:SSi:72786.0,717.0,71936.0,71941.0] || -> . % 76.04/76.27 72788[133:Spt:72787.0,72355.0,72356.0] || until2p7(s27)*+ -> . % 76.04/76.27 72789[133:Spt:72787.0,72355.1] || -> node4(s26)*. % 76.04/76.27 72791[133:MRR:840.0,72789.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.27 72794[133:Res:53.1,72791.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.27 72799[134:Spt:72794.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 72801[134:Res:72799.0,61.1] always3(s26) || -> . % 76.04/76.27 72802[134:SSi:72801.0,715.0,71927.0,71932.0,72354.0,72789.0] || -> . % 76.04/76.27 72803[134:Spt:72802.0,72794.0,72799.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.27 72804[134:Spt:72802.0,72794.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 72808[134:Res:72804.0,61.1] always3(s27) || -> . % 76.04/76.27 72809[134:SSi:72808.0,716.0,71933.0,71935.0] || -> . % 76.04/76.27 72810[132:Spt:72809.0,72353.0,72354.0] || until2p7(s26)*+ -> . % 76.04/76.27 72811[132:Spt:72809.0,72353.1] || -> node4(s25)*. % 76.04/76.27 72813[132:MRR:843.0,72811.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.27 72816[132:Res:53.1,72813.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.27 72818[133:Spt:72816.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 72820[133:Res:72818.0,61.1] always3(s25) || -> . % 76.04/76.27 72821[133:SSi:72820.0,714.0,71924.0,71926.0,72352.0,72811.0] || -> . % 76.04/76.27 72822[133:Spt:72821.0,72816.0,72818.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.27 72823[133:Spt:72821.0,72816.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 72827[133:Res:72823.0,61.1] always3(s26) || -> . % 76.04/76.27 72828[133:SSi:72827.0,715.0,71927.0,71932.0] || -> . % 76.04/76.27 72829[131:Spt:72828.0,72351.0,72352.0] || until2p7(s25)*+ -> . % 76.04/76.27 72830[131:Spt:72828.0,72351.1] || -> node4(s24)*. % 76.04/76.27 72832[131:MRR:846.0,72830.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.27 72835[131:Res:53.1,72832.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.27 72837[132:Spt:72835.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 72839[132:Res:72837.0,61.1] always3(s24) || -> . % 76.04/76.27 72840[132:SSi:72839.0,713.0,71918.0,71923.0,72350.0,72830.0] || -> . % 76.04/76.27 72841[132:Spt:72840.0,72835.0,72837.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.27 72842[132:Spt:72840.0,72835.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 72846[132:Res:72842.0,61.1] always3(s25) || -> . % 76.04/76.27 72847[132:SSi:72846.0,714.0,71924.0,71926.0] || -> . % 76.04/76.27 72848[130:Spt:72847.0,72349.0,72350.0] || until2p7(s24)*+ -> . % 76.04/76.27 72849[130:Spt:72847.0,72349.1] || -> node4(s23)*. % 76.04/76.27 72851[130:MRR:849.0,72849.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.27 72854[130:Res:53.1,72851.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.27 72856[131:Spt:72854.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 72858[131:Res:72856.0,61.1] always3(s23) || -> . % 76.04/76.27 72859[131:SSi:72858.0,712.0,71915.0,71917.0,72348.0,72849.0] || -> . % 76.04/76.27 72860[131:Spt:72859.0,72854.0,72856.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.27 72861[131:Spt:72859.0,72854.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 72865[131:Res:72861.0,61.1] always3(s24) || -> . % 76.04/76.27 72866[131:SSi:72865.0,713.0,71918.0,71923.0] || -> . % 76.04/76.27 72867[129:Spt:72866.0,72347.0,72348.0] || until2p7(s23)*+ -> . % 76.04/76.27 72868[129:Spt:72866.0,72347.1] || -> node4(s22)*. % 76.04/76.27 72870[129:MRR:852.0,72868.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.27 72873[129:Res:53.1,72870.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.27 72878[130:Spt:72873.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 72880[130:Res:72878.0,61.1] always3(s22) || -> . % 76.04/76.27 72881[130:SSi:72880.0,711.0,71909.0,71914.0,72346.0,72868.0] || -> . % 76.04/76.27 72882[130:Spt:72881.0,72873.0,72878.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.27 72883[130:Spt:72881.0,72873.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 72887[130:Res:72883.0,61.1] always3(s23) || -> . % 76.04/76.27 72888[130:SSi:72887.0,712.0,71915.0,71917.0] || -> . % 76.04/76.27 72889[128:Spt:72888.0,72345.0,72346.0] || until2p7(s22)*+ -> . % 76.04/76.27 72890[128:Spt:72888.0,72345.1] || -> node4(s21)*. % 76.04/76.27 72892[128:MRR:855.0,72890.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.27 72895[128:Res:53.1,72892.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.27 72897[129:Spt:72895.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 72899[129:Res:72897.0,61.1] always3(s21) || -> . % 76.04/76.27 72900[129:SSi:72899.0,710.0,71906.0,71908.0,72344.0,72890.0] || -> . % 76.04/76.27 72901[129:Spt:72900.0,72895.0,72897.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.27 72902[129:Spt:72900.0,72895.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 72906[129:Res:72902.0,61.1] always3(s22) || -> . % 76.04/76.27 72907[129:SSi:72906.0,711.0,71909.0,71914.0] || -> . % 76.04/76.27 72908[127:Spt:72907.0,72343.0,72344.0] || until2p7(s21)*+ -> . % 76.04/76.27 72909[127:Spt:72907.0,72343.1] || -> node4(s20)*. % 76.04/76.27 72911[127:MRR:858.0,72909.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.27 72914[127:Res:53.1,72911.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.27 72916[128:Spt:72914.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 72918[128:Res:72916.0,61.1] always3(s20) || -> . % 76.04/76.27 72919[128:SSi:72918.0,709.0,71900.0,71905.0,72342.0,72909.0] || -> . % 76.04/76.27 72920[128:Spt:72919.0,72914.0,72916.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.27 72921[128:Spt:72919.0,72914.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 72925[128:Res:72921.0,61.1] always3(s21) || -> . % 76.04/76.27 72926[128:SSi:72925.0,710.0,71906.0,71908.0] || -> . % 76.04/76.27 72927[126:Spt:72926.0,72341.0,72342.0] || until2p7(s20)*+ -> . % 76.04/76.27 72928[126:Spt:72926.0,72341.1] || -> node4(s19)*. % 76.04/76.27 72930[126:MRR:861.0,72928.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.27 72933[126:Res:53.1,72930.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.27 72935[127:Spt:72933.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 72937[127:Res:72935.0,61.1] always3(s19) || -> . % 76.04/76.27 72938[127:SSi:72937.0,708.0,71897.0,71899.0,72340.0,72928.0] || -> . % 76.04/76.27 72939[127:Spt:72938.0,72933.0,72935.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.27 72940[127:Spt:72938.0,72933.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 72944[127:Res:72940.0,61.1] always3(s20) || -> . % 76.04/76.27 72945[127:SSi:72944.0,709.0,71900.0,71905.0] || -> . % 76.04/76.27 72946[125:Spt:72945.0,72339.0,72340.0] || until2p7(s19)*+ -> . % 76.04/76.27 72947[125:Spt:72945.0,72339.1] || -> node4(s18)*. % 76.04/76.27 72949[125:MRR:864.0,72947.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.27 72952[125:Res:53.1,72949.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.27 72957[126:Spt:72952.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 72959[126:Res:72957.0,61.1] always3(s18) || -> . % 76.04/76.27 72960[126:SSi:72959.0,707.0,71891.0,71896.0,72338.0,72947.0] || -> . % 76.04/76.27 72961[126:Spt:72960.0,72952.0,72957.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.27 72962[126:Spt:72960.0,72952.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 72966[126:Res:72962.0,61.1] always3(s19) || -> . % 76.04/76.27 72967[126:SSi:72966.0,708.0,71897.0,71899.0] || -> . % 76.04/76.27 72968[124:Spt:72967.0,72337.0,72338.0] || until2p7(s18)*+ -> . % 76.04/76.27 72969[124:Spt:72967.0,72337.1] || -> node4(s17)*. % 76.04/76.27 72971[124:MRR:867.0,72969.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.27 72974[124:Res:53.1,72971.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.27 72976[125:Spt:72974.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 72978[125:Res:72976.0,61.1] always3(s17) || -> . % 76.04/76.27 72979[125:SSi:72978.0,706.0,71888.0,71890.0,72336.0,72969.0] || -> . % 76.04/76.27 72980[125:Spt:72979.0,72974.0,72976.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.27 72981[125:Spt:72979.0,72974.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 72985[125:Res:72981.0,61.1] always3(s18) || -> . % 76.04/76.27 72986[125:SSi:72985.0,707.0,71891.0,71896.0] || -> . % 76.04/76.27 72987[123:Spt:72986.0,72335.0,72336.0] || until2p7(s17)*+ -> . % 76.04/76.27 72988[123:Spt:72986.0,72335.1] || -> node4(s16)*. % 76.04/76.27 72990[123:MRR:870.0,72988.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.27 72993[123:Res:53.1,72990.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.27 72995[124:Spt:72993.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 72997[124:Res:72995.0,61.1] always3(s16) || -> . % 76.04/76.27 72998[124:SSi:72997.0,705.0,71882.0,71887.0,72334.0,72988.0] || -> . % 76.04/76.27 72999[124:Spt:72998.0,72993.0,72995.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.27 73000[124:Spt:72998.0,72993.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 73004[124:Res:73000.0,61.1] always3(s17) || -> . % 76.04/76.27 73005[124:SSi:73004.0,706.0,71888.0,71890.0] || -> . % 76.04/76.27 73006[122:Spt:73005.0,72333.0,72334.0] || until2p7(s16)*+ -> . % 76.04/76.27 73007[122:Spt:73005.0,72333.1] || -> node4(s15)*. % 76.04/76.27 73009[122:MRR:873.0,73007.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.27 73012[122:Res:53.1,73009.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.27 73014[123:Spt:73012.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 73016[123:Res:73014.0,61.1] always3(s15) || -> . % 76.04/76.27 73017[123:SSi:73016.0,704.0,71879.0,71881.0,72332.0,73007.0] || -> . % 76.04/76.27 73018[123:Spt:73017.0,73012.0,73014.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.27 73019[123:Spt:73017.0,73012.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 73023[123:Res:73019.0,61.1] always3(s16) || -> . % 76.04/76.27 73024[123:SSi:73023.0,705.0,71882.0,71887.0] || -> . % 76.04/76.27 73025[121:Spt:73024.0,72331.0,72332.0] || until2p7(s15)*+ -> . % 76.04/76.27 73026[121:Spt:73024.0,72331.1] || -> node4(s14)*. % 76.04/76.27 73028[121:MRR:876.0,73026.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.27 73031[121:Res:53.1,73028.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.27 73036[122:Spt:73031.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 73038[122:Res:73036.0,61.1] always3(s14) || -> . % 76.04/76.27 73039[122:SSi:73038.0,703.0,71873.0,71878.0,72330.0,73026.0] || -> . % 76.04/76.27 73040[122:Spt:73039.0,73031.0,73036.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.27 73041[122:Spt:73039.0,73031.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 73045[122:Res:73041.0,61.1] always3(s15) || -> . % 76.04/76.27 73046[122:SSi:73045.0,704.0,71879.0,71881.0] || -> . % 76.04/76.27 73047[120:Spt:73046.0,72329.0,72330.0] || until2p7(s14)*+ -> . % 76.04/76.27 73048[120:Spt:73046.0,72329.1] || -> node4(s13)*. % 76.04/76.27 73050[120:MRR:879.0,73048.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.27 73053[120:Res:53.1,73050.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.27 73055[121:Spt:73053.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 73057[121:Res:73055.0,61.1] always3(s13) || -> . % 76.04/76.27 73058[121:SSi:73057.0,702.0,71870.0,71872.0,72328.0,73048.0] || -> . % 76.04/76.27 73059[121:Spt:73058.0,73053.0,73055.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.27 73060[121:Spt:73058.0,73053.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 73064[121:Res:73060.0,61.1] always3(s14) || -> . % 76.04/76.27 73065[121:SSi:73064.0,703.0,71873.0,71878.0] || -> . % 76.04/76.27 73066[119:Spt:73065.0,72327.0,72328.0] || until2p7(s13)*+ -> . % 76.04/76.27 73067[119:Spt:73065.0,72327.1] || -> node4(s12)*. % 76.04/76.27 73069[119:MRR:882.0,73067.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.27 73072[119:Res:53.1,73069.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.27 73074[120:Spt:73072.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 73076[120:Res:73074.0,61.1] always3(s12) || -> . % 76.04/76.27 73077[120:SSi:73076.0,701.0,71864.0,71869.0,72326.0,73067.0] || -> . % 76.04/76.27 73078[120:Spt:73077.0,73072.0,73074.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.27 73079[120:Spt:73077.0,73072.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 73083[120:Res:73079.0,61.1] always3(s13) || -> . % 76.04/76.27 73084[120:SSi:73083.0,702.0,71870.0,71872.0] || -> . % 76.04/76.27 73085[118:Spt:73084.0,72325.0,72326.0] || until2p7(s12)*+ -> . % 76.04/76.27 73086[118:Spt:73084.0,72325.1] || -> node4(s11)*. % 76.04/76.27 73088[118:MRR:885.0,73086.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.27 73091[118:Res:53.1,73088.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.27 73093[119:Spt:73091.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 73095[119:Res:73093.0,61.1] always3(s11) || -> . % 76.04/76.27 73096[119:SSi:73095.0,700.0,71861.0,71863.0,72324.0,73086.0] || -> . % 76.04/76.27 73097[119:Spt:73096.0,73091.0,73093.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.27 73098[119:Spt:73096.0,73091.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 73102[119:Res:73098.0,61.1] always3(s12) || -> . % 76.04/76.27 73103[119:SSi:73102.0,701.0,71864.0,71869.0] || -> . % 76.04/76.27 73104[117:Spt:73103.0,72323.0,72324.0] || until2p7(s11)*+ -> . % 76.04/76.27 73105[117:Spt:73103.0,72323.1] || -> node4(s10)*. % 76.04/76.27 73107[117:MRR:888.0,73105.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.27 73110[117:Res:53.1,73107.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.27 73115[118:Spt:73110.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 73117[118:Res:73115.0,61.1] always3(s10) || -> . % 76.04/76.27 73118[118:SSi:73117.0,699.0,71855.0,71860.0,72322.0,73105.0] || -> . % 76.04/76.27 73119[118:Spt:73118.0,73110.0,73115.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.27 73120[118:Spt:73118.0,73110.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 73124[118:Res:73120.0,61.1] always3(s11) || -> . % 76.04/76.27 73125[118:SSi:73124.0,700.0,71861.0,71863.0] || -> . % 76.04/76.27 73126[116:Spt:73125.0,72321.0,72322.0] || until2p7(s10)*+ -> . % 76.04/76.27 73127[116:Spt:73125.0,72321.1] || -> node4(s9)*. % 76.04/76.27 73129[116:MRR:891.0,73127.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.27 73132[116:Res:53.1,73129.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.27 73134[117:Spt:73132.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 73136[117:Res:73134.0,61.1] always3(s9) || -> . % 76.04/76.27 73137[117:SSi:73136.0,698.0,71852.0,71854.0,72320.0,73127.0] || -> . % 76.04/76.27 73138[117:Spt:73137.0,73132.0,73134.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.27 73139[117:Spt:73137.0,73132.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 73143[117:Res:73139.0,61.1] always3(s10) || -> . % 76.04/76.27 73144[117:SSi:73143.0,699.0,71855.0,71860.0] || -> . % 76.04/76.27 73145[115:Spt:73144.0,72319.0,72320.0] || until2p7(s9)*+ -> . % 76.04/76.27 73146[115:Spt:73144.0,72319.1] || -> node4(s8)*. % 76.04/76.27 73148[115:MRR:894.0,73146.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.27 73151[115:Res:53.1,73148.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.27 73153[116:Spt:73151.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 73155[116:Res:73153.0,61.1] always3(s8) || -> . % 76.04/76.27 73156[116:SSi:73155.0,697.0,71846.0,71851.0,72318.0,73146.0] || -> . % 76.04/76.27 73157[116:Spt:73156.0,73151.0,73153.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.27 73158[116:Spt:73156.0,73151.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 73162[116:Res:73158.0,61.1] always3(s9) || -> . % 76.04/76.27 73163[116:SSi:73162.0,698.0,71852.0,71854.0] || -> . % 76.04/76.27 73164[114:Spt:73163.0,72317.0,72318.0] || until2p7(s8)*+ -> . % 76.04/76.27 73165[114:Spt:73163.0,72317.1] || -> node4(s7)*. % 76.04/76.27 73167[114:MRR:897.0,73165.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.27 73170[114:Res:53.1,73167.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.27 73172[115:Spt:73170.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 73174[115:Res:73172.0,61.1] always3(s7) || -> . % 76.04/76.27 73175[115:SSi:73174.0,696.0,71843.0,71845.0,72316.0,73165.0] || -> . % 76.04/76.27 73176[115:Spt:73175.0,73170.0,73172.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.27 73177[115:Spt:73175.0,73170.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 73181[115:Res:73177.0,61.1] always3(s8) || -> . % 76.04/76.27 73182[115:SSi:73181.0,697.0,71846.0,71851.0] || -> . % 76.04/76.27 73183[113:Spt:73182.0,72315.0,72316.0] || until2p7(s7)*+ -> . % 76.04/76.27 73184[113:Spt:73182.0,72315.1] || -> node4(s6)*. % 76.04/76.27 73186[113:MRR:900.0,73184.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.27 73189[113:Res:53.1,73186.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.27 73194[114:Spt:73189.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 73196[114:Res:73194.0,61.1] always3(s6) || -> . % 76.04/76.27 73197[114:SSi:73196.0,695.0,71837.0,71842.0,72314.0,73184.0] || -> . % 76.04/76.27 73198[114:Spt:73197.0,73189.0,73194.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.27 73199[114:Spt:73197.0,73189.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 73203[114:Res:73199.0,61.1] always3(s7) || -> . % 76.04/76.27 73204[114:SSi:73203.0,696.0,71843.0,71845.0] || -> . % 76.04/76.27 73205[112:Spt:73204.0,72313.0,72314.0] || until2p7(s6)*+ -> . % 76.04/76.27 73206[112:Spt:73204.0,72313.1] || -> node4(s5)*. % 76.04/76.27 73208[112:MRR:903.0,73206.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.27 73211[112:Res:53.1,73208.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.27 73213[113:Spt:73211.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 73215[113:Res:73213.0,61.1] always3(s5) || -> . % 76.04/76.27 73216[113:SSi:73215.0,694.0,71834.0,71836.0,72312.0,73206.0] || -> . % 76.04/76.27 73217[113:Spt:73216.0,73211.0,73213.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.27 73218[113:Spt:73216.0,73211.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 73222[113:Res:73218.0,61.1] always3(s6) || -> . % 76.04/76.27 73223[113:SSi:73222.0,695.0,71837.0,71842.0] || -> . % 76.04/76.27 73224[111:Spt:73223.0,72311.0,72312.0] || until2p7(s5)*+ -> . % 76.04/76.27 73225[111:Spt:73223.0,72311.1] || -> node4(s4)*. % 76.04/76.27 73227[111:MRR:906.0,73225.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.27 73230[111:Res:53.1,73227.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.27 73232[112:Spt:73230.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 73234[112:Res:73232.0,61.1] always3(s4) || -> . % 76.04/76.27 73235[112:SSi:73234.0,693.0,71828.0,71833.0,72310.0,73225.0] || -> . % 76.04/76.27 73236[112:Spt:73235.0,73230.0,73232.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.27 73237[112:Spt:73235.0,73230.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 73241[112:Res:73237.0,61.1] always3(s5) || -> . % 76.04/76.27 73242[112:SSi:73241.0,694.0,71834.0,71836.0] || -> . % 76.04/76.27 73243[110:Spt:73242.0,72309.0,72310.0] || until2p7(s4)*+ -> . % 76.04/76.27 73244[110:Spt:73242.0,72309.1] || -> node4(s3)*. % 76.04/76.27 73246[110:MRR:909.0,73244.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.27 73249[110:Res:53.1,73246.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.27 73251[111:Spt:73249.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 73253[111:Res:73251.0,61.1] always3(s3) || -> . % 76.04/76.27 73254[111:SSi:73253.0,692.0,71825.0,71827.0,72308.0,73244.0] || -> . % 76.04/76.27 73255[111:Spt:73254.0,73249.0,73251.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.27 73256[111:Spt:73254.0,73249.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 73260[111:Res:73256.0,61.1] always3(s4) || -> . % 76.04/76.27 73261[111:SSi:73260.0,693.0,71828.0,71833.0] || -> . % 76.04/76.27 73262[109:Spt:73261.0,72305.0,72308.0] || until2p7(s3)*+ -> . % 76.04/76.27 73263[109:Spt:73261.0,72305.1] || -> node4(s2)*. % 76.04/76.27 73265[109:MRR:912.0,73263.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.27 73268[109:Res:53.1,73265.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.27 73270[109:MRR:73268.0,72290.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 73275[109:Res:73270.0,61.1] always3(s3) || -> . % 76.04/76.27 73276[109:SSi:73275.0,692.0,71825.0,71827.0] || -> . % 76.04/76.27 73277[106:Spt:73276.0,72120.2,72125.0] || xuntil6(s48)*+ -> . % 76.04/76.27 73278[106:Spt:73276.0,72120.0,72120.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.27 73279[106:Res:53.1,73278.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.27 73281[106:MRR:73279.0,72112.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 73283[106:Res:73281.0,61.1] always3(s49) || -> . % 76.04/76.27 73284[106:SSi:73283.0,50.0,738.0] || -> . % 76.04/76.27 73285[105:Spt:73284.0,72116.1,72118.0] || xuntil6(s47)* -> . % 76.04/76.27 73286[105:Spt:73284.0,72116.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 73289[105:Res:73286.0,61.1] always3(s47) || -> . % 76.04/76.27 73290[105:SSi:73289.0,736.0,72106.0] || -> . % 76.04/76.27 73291[103:Spt:73290.0,72103.2,72105.0] || xuntil6(s46)*+ -> . % 76.04/76.27 73292[103:Spt:73290.0,72103.0,72103.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.27 73293[103:Res:53.1,73292.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.27 73295[103:MRR:73293.0,72092.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 73298[103:Res:73295.0,61.1] always3(s47) || -> . % 76.04/76.27 73299[103:SSi:73298.0,736.0] || -> . % 76.04/76.27 73300[102:Spt:73299.0,72096.1,72101.0] || xuntil6(s45)* -> . % 76.04/76.27 73301[102:Spt:73299.0,72096.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 73304[102:Res:73301.0,61.1] always3(s45) || -> . % 76.04/76.27 73305[102:SSi:73304.0,734.0,72086.0] || -> . % 76.04/76.27 73306[100:Spt:73305.0,72077.2,72085.0] || xuntil6(s44)*+ -> . % 76.04/76.27 73307[100:Spt:73305.0,72077.0,72077.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.27 73308[100:Res:53.1,73307.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.27 73310[100:MRR:73308.0,72069.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 73312[100:Res:73310.0,61.1] always3(s45) || -> . % 76.04/76.27 73313[100:SSi:73312.0,734.0] || -> . % 76.04/76.27 73314[99:Spt:73313.0,72073.1,72075.0] || xuntil6(s43)* -> . % 76.04/76.27 73315[99:Spt:73313.0,72073.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 73318[99:Res:73315.0,61.1] always3(s43) || -> . % 76.04/76.27 73319[99:SSi:73318.0,732.0,72063.0] || -> . % 76.04/76.27 73320[97:Spt:73319.0,72057.2,72062.0] || xuntil6(s42)*+ -> . % 76.04/76.27 73321[97:Spt:73319.0,72057.0,72057.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.27 73322[97:Res:53.1,73321.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.27 73324[97:MRR:73322.0,72049.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 73327[97:Res:73324.0,61.1] always3(s43) || -> . % 76.04/76.27 73328[97:SSi:73327.0,732.0] || -> . % 76.04/76.27 73329[96:Spt:73328.0,72053.1,72055.0] || xuntil6(s41)* -> . % 76.04/76.27 73330[96:Spt:73328.0,72053.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 73333[96:Res:73330.0,61.1] always3(s41) || -> . % 76.04/76.27 73334[96:SSi:73333.0,730.0,72043.0] || -> . % 76.04/76.27 73335[94:Spt:73334.0,72040.2,72042.0] || xuntil6(s40)*+ -> . % 76.04/76.27 73336[94:Spt:73334.0,72040.0,72040.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.27 73337[94:Res:53.1,73336.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.27 73339[94:MRR:73337.0,72029.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 73341[94:Res:73339.0,61.1] always3(s41) || -> . % 76.04/76.27 73342[94:SSi:73341.0,730.0] || -> . % 76.04/76.27 73343[93:Spt:73342.0,72033.1,72038.0] || xuntil6(s39)* -> . % 76.04/76.27 73344[93:Spt:73342.0,72033.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 73347[93:Res:73344.0,61.1] always3(s39) || -> . % 76.04/76.27 73348[93:SSi:73347.0,728.0,72023.0] || -> . % 76.04/76.27 73349[91:Spt:73348.0,72014.2,72022.0] || xuntil6(s38)*+ -> . % 76.04/76.27 73350[91:Spt:73348.0,72014.0,72014.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.27 73351[91:Res:53.1,73350.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.27 73353[91:MRR:73351.0,72006.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 73355[91:Res:73353.0,61.1] always3(s39) || -> . % 76.04/76.27 73356[91:SSi:73355.0,728.0] || -> . % 76.04/76.27 73357[90:Spt:73356.0,72010.1,72012.0] || xuntil6(s37)* -> . % 76.04/76.27 73358[90:Spt:73356.0,72010.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 73361[90:Res:73358.0,61.1] always3(s37) || -> . % 76.04/76.27 73362[90:SSi:73361.0,726.0,72000.0] || -> . % 76.04/76.27 73363[88:Spt:73362.0,71994.2,71999.0] || xuntil6(s36)*+ -> . % 76.04/76.27 73364[88:Spt:73362.0,71994.0,71994.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.27 73365[88:Res:53.1,73364.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.27 73367[88:MRR:73365.0,71986.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 73369[88:Res:73367.0,61.1] always3(s37) || -> . % 76.04/76.27 73370[88:SSi:73369.0,726.0] || -> . % 76.04/76.27 73371[87:Spt:73370.0,71990.1,71992.0] || xuntil6(s35)* -> . % 76.04/76.27 73372[87:Spt:73370.0,71990.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 73375[87:Res:73372.0,61.1] always3(s35) || -> . % 76.04/76.27 73376[87:SSi:73375.0,724.0,71980.0] || -> . % 76.04/76.27 73377[85:Spt:73376.0,71977.2,71979.0] || xuntil6(s34)*+ -> . % 76.04/76.27 73378[85:Spt:73376.0,71977.0,71977.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.27 73379[85:Res:53.1,73378.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.27 73381[85:MRR:73379.0,71966.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 73383[85:Res:73381.0,61.1] always3(s35) || -> . % 76.04/76.27 73384[85:SSi:73383.0,724.0] || -> . % 76.04/76.27 73385[84:Spt:73384.0,71970.1,71975.0] || xuntil6(s33)* -> . % 76.04/76.27 73386[84:Spt:73384.0,71970.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 73389[84:Res:73386.0,61.1] always3(s33) || -> . % 76.04/76.27 73390[84:SSi:73389.0,722.0,71960.0] || -> . % 76.04/76.27 73391[82:Spt:73390.0,71955.2,71959.0] || xuntil6(s32)*+ -> . % 76.04/76.27 73392[82:Spt:73390.0,71955.0,71955.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.27 73393[82:Res:53.1,73392.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.27 73395[83:Spt:73393.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 73397[83:Res:73395.0,61.1] always3(s32) || -> . % 76.04/76.27 73398[83:SSi:73397.0,721.0,71954.0] || -> . % 76.04/76.27 73399[83:Spt:73398.0,73393.0,73395.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.27 73400[83:Spt:73398.0,73393.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 73404[83:Res:73400.0,61.1] always3(s33) || -> . % 76.04/76.27 73405[83:SSi:73404.0,722.0] || -> . % 76.04/76.27 73406[81:Spt:73405.0,71952.2,71953.0] || xuntil6(s31)*+ -> . % 76.04/76.27 73407[81:Spt:73405.0,71952.0,71952.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.27 73408[81:Res:53.1,73407.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.27 73410[82:Spt:73408.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 73412[82:Res:73410.0,61.1] always3(s31) || -> . % 76.04/76.27 73413[82:SSi:73412.0,720.0,71951.0] || -> . % 76.04/76.27 73414[82:Spt:73413.0,73408.0,73410.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.27 73415[82:Spt:73413.0,73408.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 73419[82:Res:73415.0,61.1] always3(s32) || -> . % 76.04/76.27 73420[82:SSi:73419.0,721.0] || -> . % 76.04/76.27 73421[80:Spt:73420.0,71946.2,71950.0] || xuntil6(s30)*+ -> . % 76.04/76.27 73422[80:Spt:73420.0,71946.0,71946.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.27 73423[80:Res:53.1,73422.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.27 73425[81:Spt:73423.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 73427[81:Res:73425.0,61.1] always3(s31) || -> . % 76.04/76.27 73428[81:SSi:73427.0,720.0] || -> . % 76.04/76.27 73429[81:Spt:73428.0,73423.1,73425.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.27 73430[81:Spt:73428.0,73423.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 73433[81:Res:73430.0,61.1] always3(s30) || -> . % 76.04/76.27 73434[81:SSi:73433.0,719.0,71945.0] || -> . % 76.04/76.27 73435[79:Spt:73434.0,71943.2,71944.0] || xuntil6(s29)*+ -> . % 76.04/76.27 73436[79:Spt:73434.0,71943.0,71943.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.27 73437[79:Res:53.1,73436.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.27 73439[80:Spt:73437.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 73441[80:Res:73439.0,61.1] always3(s30) || -> . % 76.04/76.27 73442[80:SSi:73441.0,719.0] || -> . % 76.04/76.27 73443[80:Spt:73442.0,73437.1,73439.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.27 73444[80:Spt:73442.0,73437.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 73447[80:Res:73444.0,61.1] always3(s29) || -> . % 76.04/76.27 73448[80:SSi:73447.0,718.0,71942.0] || -> . % 76.04/76.27 73449[78:Spt:73448.0,71937.2,71941.0] || xuntil6(s28)*+ -> . % 76.04/76.27 73450[78:Spt:73448.0,71937.0,71937.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.27 73451[78:Res:53.1,73450.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.27 73453[79:Spt:73451.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 73455[79:Res:73453.0,61.1] always3(s29) || -> . % 76.04/76.27 73456[79:SSi:73455.0,718.0] || -> . % 76.04/76.27 73457[79:Spt:73456.0,73451.1,73453.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.27 73458[79:Spt:73456.0,73451.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 73461[79:Res:73458.0,61.1] always3(s28) || -> . % 76.04/76.27 73462[79:SSi:73461.0,717.0,71936.0] || -> . % 76.04/76.27 73463[77:Spt:73462.0,71934.2,71935.0] || xuntil6(s27)*+ -> . % 76.04/76.27 73464[77:Spt:73462.0,71934.0,71934.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.27 73465[77:Res:53.1,73464.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.27 73467[78:Spt:73465.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 73469[78:Res:73467.0,61.1] always3(s28) || -> . % 76.04/76.27 73470[78:SSi:73469.0,717.0] || -> . % 76.04/76.27 73471[78:Spt:73470.0,73465.1,73467.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.27 73472[78:Spt:73470.0,73465.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 73475[78:Res:73472.0,61.1] always3(s27) || -> . % 76.04/76.27 73476[78:SSi:73475.0,716.0,71933.0] || -> . % 76.04/76.27 73477[76:Spt:73476.0,71928.2,71932.0] || xuntil6(s26)*+ -> . % 76.04/76.27 73478[76:Spt:73476.0,71928.0,71928.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.27 73479[76:Res:53.1,73478.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.27 73481[77:Spt:73479.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 73483[77:Res:73481.0,61.1] always3(s27) || -> . % 76.04/76.27 73484[77:SSi:73483.0,716.0] || -> . % 76.04/76.27 73485[77:Spt:73484.0,73479.1,73481.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.27 73486[77:Spt:73484.0,73479.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 73489[77:Res:73486.0,61.1] always3(s26) || -> . % 76.04/76.27 73490[77:SSi:73489.0,715.0,71927.0] || -> . % 76.04/76.27 73491[75:Spt:73490.0,71925.2,71926.0] || xuntil6(s25)*+ -> . % 76.04/76.27 73492[75:Spt:73490.0,71925.0,71925.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.27 73493[75:Res:53.1,73492.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.27 73495[76:Spt:73493.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 73497[76:Res:73495.0,61.1] always3(s26) || -> . % 76.04/76.27 73498[76:SSi:73497.0,715.0] || -> . % 76.04/76.27 73499[76:Spt:73498.0,73493.1,73495.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.27 73500[76:Spt:73498.0,73493.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 73503[76:Res:73500.0,61.1] always3(s25) || -> . % 76.04/76.27 73504[76:SSi:73503.0,714.0,71924.0] || -> . % 76.04/76.27 73505[74:Spt:73504.0,71919.2,71923.0] || xuntil6(s24)*+ -> . % 76.04/76.27 73506[74:Spt:73504.0,71919.0,71919.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.27 73507[74:Res:53.1,73506.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.27 73512[75:Spt:73507.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 73514[75:Res:73512.0,61.1] always3(s24) || -> . % 76.04/76.27 73515[75:SSi:73514.0,713.0,71918.0] || -> . % 76.04/76.27 73516[75:Spt:73515.0,73507.0,73512.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.27 73517[75:Spt:73515.0,73507.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 73521[75:Res:73517.0,61.1] always3(s25) || -> . % 76.04/76.27 73522[75:SSi:73521.0,714.0] || -> . % 76.04/76.27 73523[73:Spt:73522.0,71916.2,71917.0] || xuntil6(s23)*+ -> . % 76.04/76.27 73524[73:Spt:73522.0,71916.0,71916.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.27 73525[73:Res:53.1,73524.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.27 73527[74:Spt:73525.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 73529[74:Res:73527.0,61.1] always3(s24) || -> . % 76.04/76.27 73530[74:SSi:73529.0,713.0] || -> . % 76.04/76.27 73531[74:Spt:73530.0,73525.1,73527.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.27 73532[74:Spt:73530.0,73525.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 73535[74:Res:73532.0,61.1] always3(s23) || -> . % 76.04/76.27 73536[74:SSi:73535.0,712.0,71915.0] || -> . % 76.04/76.27 73537[72:Spt:73536.0,71910.2,71914.0] || xuntil6(s22)*+ -> . % 76.04/76.27 73538[72:Spt:73536.0,71910.0,71910.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.27 73539[72:Res:53.1,73538.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.27 73541[73:Spt:73539.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 73543[73:Res:73541.0,61.1] always3(s23) || -> . % 76.04/76.27 73544[73:SSi:73543.0,712.0] || -> . % 76.04/76.27 73545[73:Spt:73544.0,73539.1,73541.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.27 73546[73:Spt:73544.0,73539.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 73549[73:Res:73546.0,61.1] always3(s22) || -> . % 76.04/76.27 73550[73:SSi:73549.0,711.0,71909.0] || -> . % 76.04/76.27 73551[71:Spt:73550.0,71907.2,71908.0] || xuntil6(s21)*+ -> . % 76.04/76.27 73552[71:Spt:73550.0,71907.0,71907.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.27 73553[71:Res:53.1,73552.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.27 73558[72:Spt:73553.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 73560[72:Res:73558.0,61.1] always3(s21) || -> . % 76.04/76.27 73561[72:SSi:73560.0,710.0,71906.0] || -> . % 76.04/76.27 73562[72:Spt:73561.0,73553.0,73558.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.27 73563[72:Spt:73561.0,73553.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 73567[72:Res:73563.0,61.1] always3(s22) || -> . % 76.04/76.27 73568[72:SSi:73567.0,711.0] || -> . % 76.04/76.27 73569[70:Spt:73568.0,71901.2,71905.0] || xuntil6(s20)*+ -> . % 76.04/76.27 73570[70:Spt:73568.0,71901.0,71901.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.27 73571[70:Res:53.1,73570.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.27 73573[71:Spt:73571.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 73575[71:Res:73573.0,61.1] always3(s21) || -> . % 76.04/76.27 73576[71:SSi:73575.0,710.0] || -> . % 76.04/76.27 73577[71:Spt:73576.0,73571.1,73573.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.27 73578[71:Spt:73576.0,73571.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 73581[71:Res:73578.0,61.1] always3(s20) || -> . % 76.04/76.27 73582[71:SSi:73581.0,709.0,71900.0] || -> . % 76.04/76.27 73583[69:Spt:73582.0,71898.2,71899.0] || xuntil6(s19)*+ -> . % 76.04/76.27 73584[69:Spt:73582.0,71898.0,71898.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.27 73585[69:Res:53.1,73584.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.27 73587[70:Spt:73585.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 73589[70:Res:73587.0,61.1] always3(s20) || -> . % 76.04/76.27 73590[70:SSi:73589.0,709.0] || -> . % 76.04/76.27 73591[70:Spt:73590.0,73585.1,73587.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.27 73592[70:Spt:73590.0,73585.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 73595[70:Res:73592.0,61.1] always3(s19) || -> . % 76.04/76.27 73596[70:SSi:73595.0,708.0,71897.0] || -> . % 76.04/76.27 73597[68:Spt:73596.0,71892.2,71896.0] || xuntil6(s18)*+ -> . % 76.04/76.27 73598[68:Spt:73596.0,71892.0,71892.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.27 73599[68:Res:53.1,73598.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.27 73604[69:Spt:73599.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 73606[69:Res:73604.0,61.1] always3(s18) || -> . % 76.04/76.27 73607[69:SSi:73606.0,707.0,71891.0] || -> . % 76.04/76.27 73608[69:Spt:73607.0,73599.0,73604.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.27 73609[69:Spt:73607.0,73599.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 73613[69:Res:73609.0,61.1] always3(s19) || -> . % 76.04/76.27 73614[69:SSi:73613.0,708.0] || -> . % 76.04/76.27 73615[67:Spt:73614.0,71889.2,71890.0] || xuntil6(s17)*+ -> . % 76.04/76.27 73616[67:Spt:73614.0,71889.0,71889.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.27 73617[67:Res:53.1,73616.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.27 73619[68:Spt:73617.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 73621[68:Res:73619.0,61.1] always3(s18) || -> . % 76.04/76.27 73622[68:SSi:73621.0,707.0] || -> . % 76.04/76.27 73623[68:Spt:73622.0,73617.1,73619.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.27 73624[68:Spt:73622.0,73617.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 73627[68:Res:73624.0,61.1] always3(s17) || -> . % 76.04/76.27 73628[68:SSi:73627.0,706.0,71888.0] || -> . % 76.04/76.27 73629[66:Spt:73628.0,71883.2,71887.0] || xuntil6(s16)*+ -> . % 76.04/76.27 73630[66:Spt:73628.0,71883.0,71883.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.27 73631[66:Res:53.1,73630.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.27 73633[67:Spt:73631.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 73635[67:Res:73633.0,61.1] always3(s17) || -> . % 76.04/76.27 73636[67:SSi:73635.0,706.0] || -> . % 76.04/76.27 73637[67:Spt:73636.0,73631.1,73633.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.27 73638[67:Spt:73636.0,73631.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 73641[67:Res:73638.0,61.1] always3(s16) || -> . % 76.04/76.27 73642[67:SSi:73641.0,705.0,71882.0] || -> . % 76.04/76.27 73643[65:Spt:73642.0,71880.2,71881.0] || xuntil6(s15)*+ -> . % 76.04/76.27 73644[65:Spt:73642.0,71880.0,71880.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.27 73645[65:Res:53.1,73644.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.27 73650[66:Spt:73645.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 73652[66:Res:73650.0,61.1] always3(s15) || -> . % 76.04/76.27 73653[66:SSi:73652.0,704.0,71879.0] || -> . % 76.04/76.27 73654[66:Spt:73653.0,73645.0,73650.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.27 73655[66:Spt:73653.0,73645.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 73659[66:Res:73655.0,61.1] always3(s16) || -> . % 76.04/76.27 73660[66:SSi:73659.0,705.0] || -> . % 76.04/76.27 73661[64:Spt:73660.0,71874.2,71878.0] || xuntil6(s14)*+ -> . % 76.04/76.27 73662[64:Spt:73660.0,71874.0,71874.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.27 73663[64:Res:53.1,73662.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.27 73665[65:Spt:73663.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 73667[65:Res:73665.0,61.1] always3(s15) || -> . % 76.04/76.27 73668[65:SSi:73667.0,704.0] || -> . % 76.04/76.27 73669[65:Spt:73668.0,73663.1,73665.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.27 73670[65:Spt:73668.0,73663.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 73673[65:Res:73670.0,61.1] always3(s14) || -> . % 76.04/76.27 73674[65:SSi:73673.0,703.0,71873.0] || -> . % 76.04/76.27 73675[63:Spt:73674.0,71871.2,71872.0] || xuntil6(s13)*+ -> . % 76.04/76.27 73676[63:Spt:73674.0,71871.0,71871.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.27 73677[63:Res:53.1,73676.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.27 73679[64:Spt:73677.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 73681[64:Res:73679.0,61.1] always3(s14) || -> . % 76.04/76.27 73682[64:SSi:73681.0,703.0] || -> . % 76.04/76.27 73683[64:Spt:73682.0,73677.1,73679.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.27 73684[64:Spt:73682.0,73677.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 73687[64:Res:73684.0,61.1] always3(s13) || -> . % 76.04/76.27 73688[64:SSi:73687.0,702.0,71870.0] || -> . % 76.04/76.27 73689[62:Spt:73688.0,71865.2,71869.0] || xuntil6(s12)*+ -> . % 76.04/76.27 73690[62:Spt:73688.0,71865.0,71865.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.27 73691[62:Res:53.1,73690.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.27 73696[63:Spt:73691.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 73698[63:Res:73696.0,61.1] always3(s12) || -> . % 76.04/76.27 73699[63:SSi:73698.0,701.0,71864.0] || -> . % 76.04/76.27 73700[63:Spt:73699.0,73691.0,73696.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.27 73701[63:Spt:73699.0,73691.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 73705[63:Res:73701.0,61.1] always3(s13) || -> . % 76.04/76.27 73706[63:SSi:73705.0,702.0] || -> . % 76.04/76.27 73707[61:Spt:73706.0,71862.2,71863.0] || xuntil6(s11)*+ -> . % 76.04/76.27 73708[61:Spt:73706.0,71862.0,71862.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.27 73709[61:Res:53.1,73708.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.27 73711[62:Spt:73709.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 73713[62:Res:73711.0,61.1] always3(s12) || -> . % 76.04/76.27 73714[62:SSi:73713.0,701.0] || -> . % 76.04/76.27 73715[62:Spt:73714.0,73709.1,73711.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.27 73716[62:Spt:73714.0,73709.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 73719[62:Res:73716.0,61.1] always3(s11) || -> . % 76.04/76.27 73720[62:SSi:73719.0,700.0,71861.0] || -> . % 76.04/76.27 73721[60:Spt:73720.0,71856.2,71860.0] || xuntil6(s10)*+ -> . % 76.04/76.27 73722[60:Spt:73720.0,71856.0,71856.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.27 73723[60:Res:53.1,73722.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.27 73725[61:Spt:73723.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 73727[61:Res:73725.0,61.1] always3(s11) || -> . % 76.04/76.27 73728[61:SSi:73727.0,700.0] || -> . % 76.04/76.27 73729[61:Spt:73728.0,73723.1,73725.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.27 73730[61:Spt:73728.0,73723.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 73733[61:Res:73730.0,61.1] always3(s10) || -> . % 76.04/76.27 73734[61:SSi:73733.0,699.0,71855.0] || -> . % 76.04/76.27 73735[59:Spt:73734.0,71853.2,71854.0] || xuntil6(s9)*+ -> . % 76.04/76.27 73736[59:Spt:73734.0,71853.0,71853.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.27 73737[59:Res:53.1,73736.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.27 73742[60:Spt:73737.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 73744[60:Res:73742.0,61.1] always3(s9) || -> . % 76.04/76.27 73745[60:SSi:73744.0,698.0,71852.0] || -> . % 76.04/76.27 73746[60:Spt:73745.0,73737.0,73742.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.27 73747[60:Spt:73745.0,73737.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 73751[60:Res:73747.0,61.1] always3(s10) || -> . % 76.04/76.27 73752[60:SSi:73751.0,699.0] || -> . % 76.04/76.27 73753[58:Spt:73752.0,71847.2,71851.0] || xuntil6(s8)*+ -> . % 76.04/76.27 73754[58:Spt:73752.0,71847.0,71847.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.27 73755[58:Res:53.1,73754.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.27 73757[59:Spt:73755.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 73759[59:Res:73757.0,61.1] always3(s9) || -> . % 76.04/76.27 73760[59:SSi:73759.0,698.0] || -> . % 76.04/76.27 73761[59:Spt:73760.0,73755.1,73757.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.27 73762[59:Spt:73760.0,73755.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 73765[59:Res:73762.0,61.1] always3(s8) || -> . % 76.04/76.27 73766[59:SSi:73765.0,697.0,71846.0] || -> . % 76.04/76.27 73767[57:Spt:73766.0,71844.2,71845.0] || xuntil6(s7)*+ -> . % 76.04/76.27 73768[57:Spt:73766.0,71844.0,71844.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.27 73769[57:Res:53.1,73768.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.27 73771[58:Spt:73769.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 73773[58:Res:73771.0,61.1] always3(s8) || -> . % 76.04/76.27 73774[58:SSi:73773.0,697.0] || -> . % 76.04/76.27 73775[58:Spt:73774.0,73769.1,73771.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.27 73776[58:Spt:73774.0,73769.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 73779[58:Res:73776.0,61.1] always3(s7) || -> . % 76.04/76.27 73780[58:SSi:73779.0,696.0,71843.0] || -> . % 76.04/76.27 73781[56:Spt:73780.0,71838.2,71842.0] || xuntil6(s6)*+ -> . % 76.04/76.27 73782[56:Spt:73780.0,71838.0,71838.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.27 73783[56:Res:53.1,73782.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.27 73788[57:Spt:73783.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 73790[57:Res:73788.0,61.1] always3(s6) || -> . % 76.04/76.27 73791[57:SSi:73790.0,695.0,71837.0] || -> . % 76.04/76.27 73792[57:Spt:73791.0,73783.0,73788.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.27 73793[57:Spt:73791.0,73783.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 73797[57:Res:73793.0,61.1] always3(s7) || -> . % 76.04/76.27 73798[57:SSi:73797.0,696.0] || -> . % 76.04/76.27 73799[55:Spt:73798.0,71835.2,71836.0] || xuntil6(s5)*+ -> . % 76.04/76.27 73800[55:Spt:73798.0,71835.0,71835.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.27 73801[55:Res:53.1,73800.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.27 73803[56:Spt:73801.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 73805[56:Res:73803.0,61.1] always3(s6) || -> . % 76.04/76.27 73806[56:SSi:73805.0,695.0] || -> . % 76.04/76.27 73807[56:Spt:73806.0,73801.1,73803.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.27 73808[56:Spt:73806.0,73801.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 73811[56:Res:73808.0,61.1] always3(s5) || -> . % 76.04/76.27 73812[56:SSi:73811.0,694.0,71834.0] || -> . % 76.04/76.27 73813[54:Spt:73812.0,71829.2,71833.0] || xuntil6(s4)*+ -> . % 76.04/76.27 73814[54:Spt:73812.0,71829.0,71829.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.27 73815[54:Res:53.1,73814.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.27 73817[55:Spt:73815.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 73819[55:Res:73817.0,61.1] always3(s5) || -> . % 76.04/76.27 73820[55:SSi:73819.0,694.0] || -> . % 76.04/76.27 73821[55:Spt:73820.0,73815.1,73817.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.27 73822[55:Spt:73820.0,73815.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 73825[55:Res:73822.0,61.1] always3(s4) || -> . % 76.04/76.27 73826[55:SSi:73825.0,693.0,71828.0] || -> . % 76.04/76.27 73827[53:Spt:73826.0,71826.2,71827.0] || xuntil6(s3)*+ -> . % 76.04/76.27 73828[53:Spt:73826.0,71826.0,71826.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.27 73829[53:Res:53.1,73828.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.27 73834[54:Spt:73829.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 73836[54:Res:73834.0,61.1] always3(s3) || -> . % 76.04/76.27 73837[54:SSi:73836.0,692.0,71825.0] || -> . % 76.04/76.27 73838[54:Spt:73837.0,73829.0,73834.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.27 73839[54:Spt:73837.0,73829.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 73843[54:Res:73839.0,61.1] always3(s4) || -> . % 76.04/76.27 73844[54:SSi:73843.0,693.0] || -> . % 76.04/76.27 73845[52:Spt:73844.0,71820.2,71824.0] || xuntil6(s2)*+ -> . % 76.04/76.27 73846[52:Spt:73844.0,71820.0,71820.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.27 73847[52:Res:53.1,73846.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.27 73849[53:Spt:73847.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 73851[53:Res:73849.0,61.1] always3(s3) || -> . % 76.04/76.27 73852[53:SSi:73851.0,692.0] || -> . % 76.04/76.27 73853[53:Spt:73852.0,73847.1,73849.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.27 73854[53:Spt:73852.0,73847.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 73857[53:Res:73854.0,61.1] always3(s2) || -> . % 76.04/76.27 73858[53:SSi:73857.0,691.0,71819.0] || -> . % 76.04/76.27 73859[51:Spt:73858.0,71814.2,71818.0] || xuntil6(s1)*+ -> . % 76.04/76.27 73860[51:Spt:73858.0,71814.0,71814.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.27 73861[51:Res:53.1,73860.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.27 73863[52:Spt:73861.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 73865[52:Res:73863.0,61.1] always3(s1) || -> . % 76.04/76.27 73866[52:SSi:73865.0,690.0,71813.0] || -> . % 76.04/76.27 73867[52:Spt:73866.0,73861.0,73863.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.27 73868[52:Spt:73866.0,73861.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 73873[52:Res:73868.0,61.1] always3(s2) || -> . % 76.04/76.27 73874[52:SSi:73873.0,691.0] || -> . % 76.04/76.27 73875[50:Spt:73874.0,74.0,71812.0] || xuntil6(s0)*+ -> . % 76.04/76.27 73876[50:Spt:73874.0,74.1] || -> node4(s0)*. % 76.04/76.27 73877[50:MRR:758.1,73875.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 73879[50:Res:73877.0,61.1] always3(s1) || -> . % 76.04/76.27 73880[50:SSi:73879.0,690.0] || -> . % 76.04/76.27 73881[49:Spt:73880.0,71802.0,71806.0] || trans(s49,s2)*+ -> . % 76.04/76.27 73882[49:Spt:73880.0,71802.1,71802.2] || -> trans(s49,s1)* always3(s0). % 76.04/76.27 73884[49:MRR:71804.0,73881.0] || -> trans(s49,s1) node2(s49,s0)*. % 76.04/76.27 73885[49:MRR:71805.1,73881.0] xuntil6(s49) || -> trans(s49,s1)* until2p7(s0). % 76.04/76.27 73886[50:Spt:73882.0] || -> trans(s49,s1)*. % 76.04/76.27 73887[50:Res:73886.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s1)*. % 76.04/76.27 73889[50:Res:73886.0,60.0] || -> node2(s49,s1)*. % 76.04/76.27 73890[50:SSi:73887.1,50.0,738.0] xuntil6(s49) || -> until2p7(s1)*. % 76.04/76.27 73891[50:Res:73889.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 73892[51:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.27 73893[51:MRR:176.0,73892.0] || -> until5(s1)*. % 76.04/76.27 73894[51:MRR:72251.0,73893.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.27 73898[52:Spt:73894.2] || -> xuntil6(s1)*. % 76.04/76.27 73899[52:MRR:175.0,73898.0] || -> until5(s2)*. % 76.04/76.27 73900[52:MRR:72244.0,73899.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.27 73904[53:Spt:73900.2] || -> xuntil6(s2)*. % 76.04/76.27 73905[53:MRR:174.0,73904.0] || -> until5(s3)*. % 76.04/76.27 73906[53:MRR:72240.0,73905.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.27 73907[54:Spt:73906.2] || -> xuntil6(s3)*. % 76.04/76.27 73908[54:MRR:173.0,73907.0] || -> until5(s4)*. % 76.04/76.27 73909[54:MRR:72233.0,73908.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.27 73913[55:Spt:73909.2] || -> xuntil6(s4)*. % 76.04/76.27 73914[55:MRR:172.0,73913.0] || -> until5(s5)*. % 76.04/76.27 73915[55:MRR:72232.0,73914.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.27 73916[56:Spt:73915.2] || -> xuntil6(s5)*. % 76.04/76.27 73917[56:MRR:171.0,73916.0] || -> until5(s6)*. % 76.04/76.27 73918[56:MRR:72225.0,73917.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.27 73922[57:Spt:73918.2] || -> xuntil6(s6)*. % 76.04/76.27 73923[57:MRR:170.0,73922.0] || -> until5(s7)*. % 76.04/76.27 73924[57:MRR:72221.0,73923.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.27 73925[58:Spt:73924.2] || -> xuntil6(s7)*. % 76.04/76.27 73926[58:MRR:169.0,73925.0] || -> until5(s8)*. % 76.04/76.27 73927[58:MRR:72220.0,73926.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.27 73931[59:Spt:73927.2] || -> xuntil6(s8)*. % 76.04/76.27 73932[59:MRR:168.0,73931.0] || -> until5(s9)*. % 76.04/76.27 73933[59:MRR:72213.0,73932.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.27 73934[60:Spt:73933.2] || -> xuntil6(s9)*. % 76.04/76.27 73935[60:MRR:167.0,73934.0] || -> until5(s10)*. % 76.04/76.27 73936[60:MRR:72212.0,73935.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.27 73940[61:Spt:73936.2] || -> xuntil6(s10)*. % 76.04/76.27 73941[61:MRR:166.0,73940.0] || -> until5(s11)*. % 76.04/76.27 73942[61:MRR:72211.0,73941.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.27 73943[62:Spt:73942.2] || -> xuntil6(s11)*. % 76.04/76.27 73944[62:MRR:165.0,73943.0] || -> until5(s12)*. % 76.04/76.27 73945[62:MRR:72201.0,73944.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.27 73949[63:Spt:73945.2] || -> xuntil6(s12)*. % 76.04/76.27 73950[63:MRR:164.0,73949.0] || -> until5(s13)*. % 76.04/76.27 73951[63:MRR:72200.0,73950.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.27 73952[64:Spt:73951.2] || -> xuntil6(s13)*. % 76.04/76.27 73953[64:MRR:163.0,73952.0] || -> until5(s14)*. % 76.04/76.27 73954[64:MRR:72196.0,73953.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.27 73958[65:Spt:73954.2] || -> xuntil6(s14)*. % 76.04/76.27 73959[65:MRR:162.0,73958.0] || -> until5(s15)*. % 76.04/76.27 73960[65:MRR:72189.0,73959.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.27 73961[66:Spt:73960.2] || -> xuntil6(s15)*. % 76.04/76.27 73962[66:MRR:161.0,73961.0] || -> until5(s16)*. % 76.04/76.27 73963[66:MRR:72185.0,73962.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.27 73967[67:Spt:73963.2] || -> xuntil6(s16)*. % 76.04/76.27 73968[67:MRR:160.0,73967.0] || -> until5(s17)*. % 76.04/76.27 73969[67:MRR:72184.0,73968.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.27 73970[68:Spt:73969.2] || -> xuntil6(s17)*. % 76.04/76.27 73971[68:MRR:159.0,73970.0] || -> until5(s18)*. % 76.04/76.27 73972[68:MRR:72180.0,73971.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.27 73976[69:Spt:73972.2] || -> xuntil6(s18)*. % 76.04/76.27 73977[69:MRR:158.0,73976.0] || -> until5(s19)*. % 76.04/76.27 73978[69:MRR:72173.0,73977.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.27 73979[70:Spt:73978.2] || -> xuntil6(s19)*. % 76.04/76.27 73980[70:MRR:157.0,73979.0] || -> until5(s20)*. % 76.04/76.27 73981[70:MRR:72172.0,73980.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.27 73985[71:Spt:73981.2] || -> xuntil6(s20)*. % 76.04/76.27 73986[71:MRR:156.0,73985.0] || -> until5(s21)*. % 76.04/76.27 73987[71:MRR:72165.0,73986.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.27 73988[72:Spt:73987.2] || -> xuntil6(s21)*. % 76.04/76.27 73989[72:MRR:155.0,73988.0] || -> until5(s22)*. % 76.04/76.27 73990[72:MRR:72161.0,73989.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.27 73994[73:Spt:73990.2] || -> xuntil6(s22)*. % 76.04/76.27 73995[73:MRR:154.0,73994.0] || -> until5(s23)*. % 76.04/76.27 73996[73:MRR:72160.0,73995.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.27 73997[74:Spt:73996.2] || -> xuntil6(s23)*. % 76.04/76.27 73998[74:MRR:153.0,73997.0] || -> until5(s24)*. % 76.04/76.27 73999[74:MRR:72153.0,73998.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.27 74003[75:Spt:73999.2] || -> xuntil6(s24)*. % 76.04/76.27 74004[75:MRR:152.0,74003.0] || -> until5(s25)*. % 76.04/76.27 74005[75:MRR:72149.0,74004.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.27 74006[76:Spt:74005.2] || -> xuntil6(s25)*. % 76.04/76.27 74007[76:MRR:151.0,74006.0] || -> until5(s26)*. % 76.04/76.27 74008[76:MRR:72145.0,74007.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.27 74012[77:Spt:74008.2] || -> xuntil6(s26)*. % 76.04/76.27 74013[77:MRR:150.0,74012.0] || -> until5(s27)*. % 76.04/76.27 74014[77:MRR:72141.0,74013.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.27 74015[78:Spt:74014.2] || -> xuntil6(s27)*. % 76.04/76.27 74016[78:MRR:149.0,74015.0] || -> until5(s28)*. % 76.04/76.27 74017[78:MRR:72140.0,74016.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.27 74021[79:Spt:74017.2] || -> xuntil6(s28)*. % 76.04/76.27 74022[79:MRR:148.0,74021.0] || -> until5(s29)*. % 76.04/76.27 74023[79:MRR:72133.0,74022.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.27 74024[80:Spt:74023.2] || -> xuntil6(s29)*. % 76.04/76.27 74025[80:MRR:147.0,74024.0] || -> until5(s30)*. % 76.04/76.27 74026[80:MRR:72132.0,74025.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.27 74030[81:Spt:74026.2] || -> xuntil6(s30)*. % 76.04/76.27 74031[81:MRR:146.0,74030.0] || -> until5(s31)*. % 76.04/76.27 74032[81:MRR:72131.0,74031.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.27 74033[82:Spt:74032.2] || -> xuntil6(s31)*. % 76.04/76.27 74034[82:MRR:145.0,74033.0] || -> until5(s32)*. % 76.04/76.27 74035[82:MRR:72127.0,74034.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.27 74039[83:Spt:74035.2] || -> xuntil6(s32)*. % 76.04/76.27 74040[83:MRR:144.0,74039.0] || -> until5(s33)*. % 76.04/76.27 74041[83:MRR:68175.0,74040.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.27 74042[84:Spt:74041.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.27 74044[84:Res:74042.0,61.1] always3(s34) || -> . % 76.04/76.27 74045[84:SSi:74044.0,723.0] || -> . % 76.04/76.27 74046[84:Spt:74045.0,74041.1,74042.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.27 74047[84:Spt:74045.0,74041.0,74041.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.27 74049[84:MRR:819.2,74046.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.27 74050[84:Res:53.1,74047.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.27 74055[85:Spt:74050.1] || -> xuntil6(s33)*. % 76.04/76.27 74056[85:MRR:143.0,74055.0] || -> until5(s34)*. % 76.04/76.27 74057[85:MRR:72255.0,74056.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.27 74059[86:Spt:74057.2] || -> xuntil6(s34)*. % 76.04/76.27 74060[86:MRR:142.0,74059.0] || -> until5(s35)*. % 76.04/76.27 74061[86:MRR:68179.0,74060.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.27 74062[87:Spt:74061.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.27 74064[87:Res:74062.0,61.1] always3(s36) || -> . % 76.04/76.27 74065[87:SSi:74064.0,725.0] || -> . % 76.04/76.27 74066[87:Spt:74065.0,74061.1,74062.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.27 74067[87:Spt:74065.0,74061.0,74061.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.27 74069[87:MRR:813.2,74066.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.27 74070[87:Res:53.1,74067.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.27 74072[88:Spt:74070.1] || -> xuntil6(s35)*. % 76.04/76.27 74073[88:MRR:141.0,74072.0] || -> until5(s36)*. % 76.04/76.27 74074[88:MRR:72262.0,74073.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.27 74079[89:Spt:74074.2] || -> xuntil6(s36)*. % 76.04/76.27 74080[89:MRR:140.0,74079.0] || -> until5(s37)*. % 76.04/76.27 74081[89:MRR:68186.0,74080.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.27 74082[90:Spt:74081.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.27 74084[90:Res:74082.0,61.1] always3(s38) || -> . % 76.04/76.27 74085[90:SSi:74084.0,727.0] || -> . % 76.04/76.27 74086[90:Spt:74085.0,74081.1,74082.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.27 74087[90:Spt:74085.0,74081.0,74081.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.27 74089[90:MRR:807.2,74086.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.27 74090[90:Res:53.1,74087.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.27 74092[91:Spt:74090.1] || -> xuntil6(s37)*. % 76.04/76.27 74093[91:MRR:139.0,74092.0] || -> until5(s38)*. % 76.04/76.27 74094[91:MRR:72263.0,74093.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.27 74102[92:Spt:74094.2] || -> xuntil6(s38)*. % 76.04/76.27 74103[92:MRR:138.0,74102.0] || -> until5(s39)*. % 76.04/76.27 74104[92:MRR:68187.0,74103.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.27 74105[93:Spt:74104.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.27 74107[93:Res:74105.0,61.1] always3(s40) || -> . % 76.04/76.27 74108[93:SSi:74107.0,729.0] || -> . % 76.04/76.27 74109[93:Spt:74108.0,74104.1,74105.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.27 74110[93:Spt:74108.0,74104.0,74104.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.27 74112[93:MRR:801.2,74109.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.27 74113[93:Res:53.1,74110.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.27 74118[94:Spt:74113.1] || -> xuntil6(s39)*. % 76.04/76.27 74119[94:MRR:137.0,74118.0] || -> until5(s40)*. % 76.04/76.27 74120[94:MRR:72267.0,74119.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.27 74122[95:Spt:74120.2] || -> xuntil6(s40)*. % 76.04/76.27 74123[95:MRR:136.0,74122.0] || -> until5(s41)*. % 76.04/76.27 74124[95:MRR:68191.0,74123.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.27 74125[96:Spt:74124.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.27 74127[96:Res:74125.0,61.1] always3(s42) || -> . % 76.04/76.27 74128[96:SSi:74127.0,731.0] || -> . % 76.04/76.27 74129[96:Spt:74128.0,74124.1,74125.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.27 74130[96:Spt:74128.0,74124.0,74124.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.27 74132[96:MRR:795.2,74129.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.27 74133[96:Res:53.1,74130.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.27 74135[97:Spt:74133.1] || -> xuntil6(s41)*. % 76.04/76.27 74136[97:MRR:135.0,74135.0] || -> until5(s42)*. % 76.04/76.27 74137[97:MRR:72271.0,74136.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.27 74142[98:Spt:74137.2] || -> xuntil6(s42)*. % 76.04/76.27 74143[98:MRR:134.0,74142.0] || -> until5(s43)*. % 76.04/76.27 74144[98:MRR:68195.0,74143.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.27 74145[99:Spt:74144.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.27 74147[99:Res:74145.0,61.1] always3(s44) || -> . % 76.04/76.27 74148[99:SSi:74147.0,733.0] || -> . % 76.04/76.27 74149[99:Spt:74148.0,74144.1,74145.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.27 74150[99:Spt:74148.0,74144.0,74144.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.27 74152[99:MRR:789.2,74149.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.27 74153[99:Res:53.1,74150.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.27 74155[100:Spt:74153.1] || -> xuntil6(s43)*. % 76.04/76.27 74156[100:MRR:133.0,74155.0] || -> until5(s44)*. % 76.04/76.27 74157[100:MRR:72275.0,74156.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.27 74165[101:Spt:74157.2] || -> xuntil6(s44)*. % 76.04/76.27 74166[101:MRR:132.0,74165.0] || -> until5(s45)*. % 76.04/76.27 74167[101:MRR:68199.0,74166.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.27 74168[102:Spt:74167.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.27 74170[102:Res:74168.0,61.1] always3(s46) || -> . % 76.04/76.27 74171[102:SSi:74170.0,735.0] || -> . % 76.04/76.27 74172[102:Spt:74171.0,74167.1,74168.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.27 74173[102:Spt:74171.0,74167.0,74167.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.27 74175[102:MRR:783.2,74172.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.27 74176[102:Res:53.1,74173.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.27 74181[103:Spt:74176.1] || -> xuntil6(s45)*. % 76.04/76.27 74182[103:MRR:131.0,74181.0] || -> until5(s46)*. % 76.04/76.27 74183[103:MRR:72282.0,74182.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.27 74185[104:Spt:74183.2] || -> xuntil6(s46)*. % 76.04/76.27 74186[104:MRR:130.0,74185.0] || -> until5(s47)*. % 76.04/76.27 74187[104:MRR:68203.0,74186.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.27 74188[105:Spt:74187.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.27 74190[105:Res:74188.0,61.1] always3(s48) || -> . % 76.04/76.27 74191[105:SSi:74190.0,737.0] || -> . % 76.04/76.27 74192[105:Spt:74191.0,74187.1,74188.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.27 74193[105:Spt:74191.0,74187.0,74187.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.27 74195[105:MRR:777.2,74192.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.27 74196[105:Res:53.1,74193.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.27 74198[106:Spt:74196.1] || -> xuntil6(s47)*. % 76.04/76.27 74199[106:MRR:129.0,74198.0] || -> until5(s48)*. % 76.04/76.27 74200[106:MRR:72283.0,74199.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.27 74205[107:Spt:74200.2] || -> xuntil6(s48)*. % 76.04/76.27 74206[107:MRR:128.0,74205.0] || -> until5(s49)*. % 76.04/76.27 74207[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.27 74211[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.27 74212[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.27 74213[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.27 74220[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.27 74221[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.27 74225[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.27 74229[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.27 74233[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.27 74240[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.27 74241[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.27 74245[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.27 74252[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.27 74253[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.27 74260[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.27 74264[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.27 74265[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.27 74269[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.27 74276[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.27 74280[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.27 74281[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.27 74291[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.27 74292[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.27 74293[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.27 74300[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.27 74301[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.27 74305[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.27 74312[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.27 74313[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.27 74320[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.27 74324[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.27 74331[0:SoR:915.0,66.2] until5(s1) || m_main_v_state(s1,c_ready)* -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.27 74333[50:SoR:73891.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 74335[0:SoR:816.0,66.2] until5(s34) || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.27 74342[0:SoR:810.0,66.2] until5(s36) || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.27 74343[0:SoR:804.0,66.2] until5(s38) || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.27 74347[0:SoR:798.0,66.2] until5(s40) || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.27 74351[0:SoR:792.0,66.2] until5(s42) || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.27 74355[0:SoR:786.0,66.2] until5(s44) || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.27 74362[0:SoR:780.0,66.2] until5(s46) || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.27 74363[0:SoR:774.0,66.2] until5(s48) || m_main_v_state(s48,c_ready)* -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.27 74364[50:SoR:74333.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s1,c_busy)* xuntil6(s49). % 76.04/76.27 74365[107:SSi:74364.0,50.0,738.0,74206.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s1,c_busy)* xuntil6(s49). % 76.04/76.27 74366[108:Spt:74365.1] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 74368[108:Res:74366.0,61.1] always3(s1) || -> . % 76.04/76.27 74369[108:SSi:74368.0,690.0,73893.0,73898.0] || -> . % 76.04/76.27 74370[108:Spt:74369.0,74365.1,74366.0] || m_main_v_state(s1,c_busy)*+ -> . % 76.04/76.27 74371[108:Spt:74369.0,74365.0,74365.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.27 74376[108:MRR:74333.2,74370.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.27 74377[108:Res:53.1,74371.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.27 74382[109:Spt:74377.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 74384[109:Res:74382.0,61.1] always3(s49) || -> . % 76.04/76.27 74385[109:SSi:74384.0,50.0,738.0,74206.0] || -> . % 76.04/76.27 74386[109:Spt:74385.0,74377.0,74382.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.27 74387[109:Spt:74385.0,74377.1] || -> xuntil6(s49)*. % 76.04/76.27 74388[109:MRR:73890.0,74387.0] || -> until2p7(s1)*. % 76.04/76.27 74389[109:MRR:197.0,74388.0] || -> until2p7(s2)* node4(s1). % 76.04/76.27 74391[109:MRR:774.2,74386.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.27 74392[110:Spt:74389.0] || -> until2p7(s2)*. % 76.04/76.27 74393[110:MRR:198.0,74392.0] || -> until2p7(s3)* node4(s2). % 76.04/76.27 74394[111:Spt:74393.0] || -> until2p7(s3)*. % 76.04/76.27 74395[111:MRR:199.0,74394.0] || -> until2p7(s4)* node4(s3). % 76.04/76.27 74396[112:Spt:74395.0] || -> until2p7(s4)*. % 76.04/76.27 74397[112:MRR:200.0,74396.0] || -> until2p7(s5)* node4(s4). % 76.04/76.27 74398[113:Spt:74397.0] || -> until2p7(s5)*. % 76.04/76.27 74399[113:MRR:201.0,74398.0] || -> until2p7(s6)* node4(s5). % 76.04/76.27 74400[114:Spt:74399.0] || -> until2p7(s6)*. % 76.04/76.27 74401[114:MRR:202.0,74400.0] || -> until2p7(s7)* node4(s6). % 76.04/76.27 74402[115:Spt:74401.0] || -> until2p7(s7)*. % 76.04/76.27 74403[115:MRR:203.0,74402.0] || -> until2p7(s8)* node4(s7). % 76.04/76.27 74404[116:Spt:74403.0] || -> until2p7(s8)*. % 76.04/76.27 74405[116:MRR:204.0,74404.0] || -> until2p7(s9)* node4(s8). % 76.04/76.27 74406[117:Spt:74405.0] || -> until2p7(s9)*. % 76.04/76.27 74407[117:MRR:205.0,74406.0] || -> until2p7(s10)* node4(s9). % 76.04/76.27 74408[118:Spt:74407.0] || -> until2p7(s10)*. % 76.04/76.27 74409[118:MRR:206.0,74408.0] || -> until2p7(s11)* node4(s10). % 76.04/76.27 74410[119:Spt:74409.0] || -> until2p7(s11)*. % 76.04/76.27 74411[119:MRR:207.0,74410.0] || -> until2p7(s12)* node4(s11). % 76.04/76.27 74412[120:Spt:74411.0] || -> until2p7(s12)*. % 76.04/76.27 74413[120:MRR:208.0,74412.0] || -> until2p7(s13)* node4(s12). % 76.04/76.27 74414[121:Spt:74413.0] || -> until2p7(s13)*. % 76.04/76.27 74415[121:MRR:209.0,74414.0] || -> until2p7(s14)* node4(s13). % 76.04/76.27 74416[122:Spt:74415.0] || -> until2p7(s14)*. % 76.04/76.27 74417[122:MRR:210.0,74416.0] || -> until2p7(s15)* node4(s14). % 76.04/76.27 74418[123:Spt:74417.0] || -> until2p7(s15)*. % 76.04/76.27 74419[123:MRR:211.0,74418.0] || -> until2p7(s16)* node4(s15). % 76.04/76.27 74420[124:Spt:74419.0] || -> until2p7(s16)*. % 76.04/76.27 74421[124:MRR:212.0,74420.0] || -> until2p7(s17)* node4(s16). % 76.04/76.27 74422[125:Spt:74421.0] || -> until2p7(s17)*. % 76.04/76.27 74423[125:MRR:213.0,74422.0] || -> until2p7(s18)* node4(s17). % 76.04/76.27 74424[126:Spt:74423.0] || -> until2p7(s18)*. % 76.04/76.27 74425[126:MRR:214.0,74424.0] || -> until2p7(s19)* node4(s18). % 76.04/76.27 74426[127:Spt:74425.0] || -> until2p7(s19)*. % 76.04/76.27 74427[127:MRR:215.0,74426.0] || -> until2p7(s20)* node4(s19). % 76.04/76.27 74428[128:Spt:74427.0] || -> until2p7(s20)*. % 76.04/76.27 74429[128:MRR:216.0,74428.0] || -> until2p7(s21)* node4(s20). % 76.04/76.27 74430[129:Spt:74429.0] || -> until2p7(s21)*. % 76.04/76.27 74431[129:MRR:217.0,74430.0] || -> until2p7(s22)* node4(s21). % 76.04/76.27 74432[130:Spt:74431.0] || -> until2p7(s22)*. % 76.04/76.27 74433[130:MRR:218.0,74432.0] || -> until2p7(s23)* node4(s22). % 76.04/76.27 74434[131:Spt:74433.0] || -> until2p7(s23)*. % 76.04/76.27 74435[131:MRR:219.0,74434.0] || -> until2p7(s24)* node4(s23). % 76.04/76.27 74436[132:Spt:74435.0] || -> until2p7(s24)*. % 76.04/76.27 74437[132:MRR:220.0,74436.0] || -> until2p7(s25)* node4(s24). % 76.04/76.27 74438[133:Spt:74437.0] || -> until2p7(s25)*. % 76.04/76.27 74439[133:MRR:221.0,74438.0] || -> until2p7(s26)* node4(s25). % 76.04/76.27 74440[134:Spt:74439.0] || -> until2p7(s26)*. % 76.04/76.27 74441[134:MRR:222.0,74440.0] || -> until2p7(s27)* node4(s26). % 76.04/76.27 74442[135:Spt:74441.0] || -> until2p7(s27)*. % 76.04/76.27 74443[135:MRR:223.0,74442.0] || -> until2p7(s28)* node4(s27). % 76.04/76.27 74444[136:Spt:74443.0] || -> until2p7(s28)*. % 76.04/76.27 74445[136:MRR:224.0,74444.0] || -> until2p7(s29)* node4(s28). % 76.04/76.27 74446[137:Spt:74445.0] || -> until2p7(s29)*. % 76.04/76.27 74447[137:MRR:225.0,74446.0] || -> until2p7(s30)* node4(s29). % 76.04/76.27 74448[138:Spt:74447.0] || -> until2p7(s30)*. % 76.04/76.27 74449[138:MRR:226.0,74448.0] || -> until2p7(s31)* node4(s30). % 76.04/76.27 74450[139:Spt:74449.0] || -> until2p7(s31)*. % 76.04/76.27 74451[139:MRR:227.0,74450.0] || -> until2p7(s32)* node4(s31). % 76.04/76.27 74452[140:Spt:74451.0] || -> until2p7(s32)*. % 76.04/76.27 74453[140:MRR:228.0,74452.0] || -> until2p7(s33)* node4(s32). % 76.04/76.27 74454[141:Spt:74453.0] || -> until2p7(s33)*. % 76.04/76.27 74455[141:MRR:229.0,74454.0] || -> until2p7(s34)* node4(s33). % 76.04/76.27 74456[142:Spt:74455.0] || -> until2p7(s34)*. % 76.04/76.27 74457[142:MRR:230.0,74456.0] || -> until2p7(s35)* node4(s34). % 76.04/76.27 74458[143:Spt:74457.0] || -> until2p7(s35)*. % 76.04/76.27 74459[143:MRR:231.0,74458.0] || -> until2p7(s36)* node4(s35). % 76.04/76.27 74460[144:Spt:74459.0] || -> until2p7(s36)*. % 76.04/76.27 74461[144:MRR:232.0,74460.0] || -> until2p7(s37)* node4(s36). % 76.04/76.27 74462[145:Spt:74461.0] || -> until2p7(s37)*. % 76.04/76.27 74463[145:MRR:235.0,74462.0] || -> until2p7(s38)* node4(s37). % 76.04/76.27 74464[146:Spt:74463.0] || -> until2p7(s38)*. % 76.04/76.27 74465[146:MRR:236.0,74464.0] || -> until2p7(s39)* node4(s38). % 76.04/76.27 74466[147:Spt:74465.0] || -> until2p7(s39)*. % 76.04/76.27 74467[147:MRR:237.0,74466.0] || -> until2p7(s40)* node4(s39). % 76.04/76.27 74468[148:Spt:74467.0] || -> until2p7(s40)*. % 76.04/76.27 74469[148:MRR:238.0,74468.0] || -> until2p7(s41)* node4(s40). % 76.04/76.27 74470[149:Spt:74469.0] || -> until2p7(s41)*. % 76.04/76.27 74471[149:MRR:239.0,74470.0] || -> until2p7(s42)* node4(s41). % 76.04/76.27 74472[150:Spt:74471.0] || -> until2p7(s42)*. % 76.04/76.27 74473[150:MRR:240.0,74472.0] || -> until2p7(s43)* node4(s42). % 76.04/76.27 74474[151:Spt:74473.0] || -> until2p7(s43)*. % 76.04/76.27 74475[151:MRR:241.0,74474.0] || -> until2p7(s44)* node4(s43). % 76.04/76.27 74476[152:Spt:74475.0] || -> until2p7(s44)*. % 76.04/76.27 74477[152:MRR:539.0,74476.0] || -> until2p7(s45)* node4(s44). % 76.04/76.27 74478[153:Spt:74477.0] || -> until2p7(s45)*. % 76.04/76.27 74479[153:MRR:544.0,74478.0] || -> until2p7(s46)* node4(s45). % 76.04/76.27 74480[154:Spt:74479.0] || -> until2p7(s46)*. % 76.04/76.27 74481[154:MRR:549.0,74480.0] || -> until2p7(s47)* node4(s46). % 76.04/76.27 74482[155:Spt:74481.0] || -> until2p7(s47)*. % 76.04/76.27 74483[155:MRR:554.0,74482.0] || -> until2p7(s48)* node4(s47). % 76.04/76.27 74484[156:Spt:74483.0] || -> until2p7(s48)*. % 76.04/76.27 74485[156:MRR:559.0,74484.0] || -> until2p7(s49)* node4(s48). % 76.04/76.27 74486[157:Spt:74485.0] || -> until2p7(s49)*. % 76.04/76.27 74487[157:MRR:194.0,74486.0] || -> node4(s49)*. % 76.04/76.27 74488[157:MRR:74376.0,74487.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.27 74489[157:Res:53.1,74488.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 74491[157:MRR:74489.0,74386.0] || -> . % 76.04/76.27 74492[157:Spt:74491.0,74485.0,74486.0] || until2p7(s49)*+ -> . % 76.04/76.27 74493[157:Spt:74491.0,74485.1] || -> node4(s48)*. % 76.04/76.27 74494[157:MRR:74391.0,74493.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.27 74497[157:Res:53.1,74494.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.27 74499[157:MRR:74497.0,74192.0] || -> . % 76.04/76.27 74500[156:Spt:74499.0,74483.0,74484.0] || until2p7(s48)*+ -> . % 76.04/76.27 74501[156:Spt:74499.0,74483.1] || -> node4(s47)*. % 76.04/76.27 74502[156:MRR:74195.0,74501.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.27 74505[156:Res:53.1,74502.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 74508[156:Res:74505.0,61.1] always3(s47) || -> . % 76.04/76.27 74509[156:SSi:74508.0,736.0,74186.0,74198.0,74482.0,74501.0] || -> . % 76.04/76.27 74510[155:Spt:74509.0,74481.0,74482.0] || until2p7(s47)*+ -> . % 76.04/76.27 74511[155:Spt:74509.0,74481.1] || -> node4(s46)*. % 76.04/76.27 74513[155:MRR:780.0,74511.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.27 74529[155:Res:53.1,74513.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.27 74531[155:MRR:74529.0,74172.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 74533[155:Res:74531.0,61.1] always3(s47) || -> . % 76.04/76.27 74534[155:SSi:74533.0,736.0,74186.0,74198.0] || -> . % 76.04/76.27 74535[154:Spt:74534.0,74479.0,74480.0] || until2p7(s46)*+ -> . % 76.04/76.27 74536[154:Spt:74534.0,74479.1] || -> node4(s45)*. % 76.04/76.27 74537[154:MRR:74175.0,74536.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.27 74540[154:Res:53.1,74537.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 74543[154:Res:74540.0,61.1] always3(s45) || -> . % 76.04/76.27 74544[154:SSi:74543.0,734.0,74166.0,74181.0,74478.0,74536.0] || -> . % 76.04/76.27 74545[153:Spt:74544.0,74477.0,74478.0] || until2p7(s45)*+ -> . % 76.04/76.27 74546[153:Spt:74544.0,74477.1] || -> node4(s44)*. % 76.04/76.27 74548[153:MRR:786.0,74546.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.27 74560[153:Res:53.1,74548.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.27 74562[153:MRR:74560.0,74149.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 74564[153:Res:74562.0,61.1] always3(s45) || -> . % 76.04/76.27 74565[153:SSi:74564.0,734.0,74166.0,74181.0] || -> . % 76.04/76.27 74566[152:Spt:74565.0,74475.0,74476.0] || until2p7(s44)*+ -> . % 76.04/76.27 74567[152:Spt:74565.0,74475.1] || -> node4(s43)*. % 76.04/76.27 74568[152:MRR:74152.0,74567.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.27 74571[152:Res:53.1,74568.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 74574[152:Res:74571.0,61.1] always3(s43) || -> . % 76.04/76.27 74575[152:SSi:74574.0,732.0,74143.0,74155.0,74474.0,74567.0] || -> . % 76.04/76.27 74576[151:Spt:74575.0,74473.0,74474.0] || until2p7(s43)*+ -> . % 76.04/76.27 74577[151:Spt:74575.0,74473.1] || -> node4(s42)*. % 76.04/76.27 74579[151:MRR:792.0,74577.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.27 74591[151:Res:53.1,74579.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.27 74593[151:MRR:74591.0,74129.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 74598[151:Res:74593.0,61.1] always3(s43) || -> . % 76.04/76.27 74599[151:SSi:74598.0,732.0,74143.0,74155.0] || -> . % 76.04/76.27 74600[150:Spt:74599.0,74471.0,74472.0] || until2p7(s42)*+ -> . % 76.04/76.27 74601[150:Spt:74599.0,74471.1] || -> node4(s41)*. % 76.04/76.27 74602[150:MRR:74132.0,74601.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.27 74605[150:Res:53.1,74602.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 74609[150:Res:74605.0,61.1] always3(s41) || -> . % 76.04/76.27 74610[150:SSi:74609.0,730.0,74123.0,74135.0,74470.0,74601.0] || -> . % 76.04/76.27 74611[149:Spt:74610.0,74469.0,74470.0] || until2p7(s41)*+ -> . % 76.04/76.27 74612[149:Spt:74610.0,74469.1] || -> node4(s40)*. % 76.04/76.27 74614[149:MRR:798.0,74612.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.27 74625[149:Res:53.1,74614.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.27 74627[149:MRR:74625.0,74109.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 74629[149:Res:74627.0,61.1] always3(s41) || -> . % 76.04/76.27 74630[149:SSi:74629.0,730.0,74123.0,74135.0] || -> . % 76.04/76.27 74631[148:Spt:74630.0,74467.0,74468.0] || until2p7(s40)*+ -> . % 76.04/76.27 74632[148:Spt:74630.0,74467.1] || -> node4(s39)*. % 76.04/76.27 74633[148:MRR:74112.0,74632.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.27 74637[148:Res:53.1,74633.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 74640[148:Res:74637.0,61.1] always3(s39) || -> . % 76.04/76.27 74641[148:SSi:74640.0,728.0,74103.0,74118.0,74466.0,74632.0] || -> . % 76.04/76.27 74642[147:Spt:74641.0,74465.0,74466.0] || until2p7(s39)*+ -> . % 76.04/76.27 74643[147:Spt:74641.0,74465.1] || -> node4(s38)*. % 76.04/76.27 74645[147:MRR:804.0,74643.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.27 74656[147:Res:53.1,74645.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.27 74658[147:MRR:74656.0,74086.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 74660[147:Res:74658.0,61.1] always3(s39) || -> . % 76.04/76.27 74661[147:SSi:74660.0,728.0,74103.0,74118.0] || -> . % 76.04/76.27 74662[146:Spt:74661.0,74463.0,74464.0] || until2p7(s38)*+ -> . % 76.04/76.27 74663[146:Spt:74661.0,74463.1] || -> node4(s37)*. % 76.04/76.27 74664[146:MRR:74089.0,74663.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.27 74667[146:Res:53.1,74664.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 74670[146:Res:74667.0,61.1] always3(s37) || -> . % 76.04/76.27 74671[146:SSi:74670.0,726.0,74080.0,74092.0,74462.0,74663.0] || -> . % 76.04/76.27 74672[145:Spt:74671.0,74461.0,74462.0] || until2p7(s37)*+ -> . % 76.04/76.27 74673[145:Spt:74671.0,74461.1] || -> node4(s36)*. % 76.04/76.27 74675[145:MRR:810.0,74673.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.27 74687[145:Res:53.1,74675.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.27 74689[145:MRR:74687.0,74066.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 74691[145:Res:74689.0,61.1] always3(s37) || -> . % 76.04/76.27 74692[145:SSi:74691.0,726.0,74080.0,74092.0] || -> . % 76.04/76.27 74693[144:Spt:74692.0,74459.0,74460.0] || until2p7(s36)*+ -> . % 76.04/76.27 74694[144:Spt:74692.0,74459.1] || -> node4(s35)*. % 76.04/76.27 74695[144:MRR:74069.0,74694.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.27 74698[144:Res:53.1,74695.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 74701[144:Res:74698.0,61.1] always3(s35) || -> . % 76.04/76.27 74702[144:SSi:74701.0,724.0,74060.0,74072.0,74458.0,74694.0] || -> . % 76.04/76.27 74703[143:Spt:74702.0,74457.0,74458.0] || until2p7(s35)*+ -> . % 76.04/76.27 74704[143:Spt:74702.0,74457.1] || -> node4(s34)*. % 76.04/76.27 74706[143:MRR:816.0,74704.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.27 74718[143:Res:53.1,74706.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.27 74720[143:MRR:74718.0,74046.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 74725[143:Res:74720.0,61.1] always3(s35) || -> . % 76.04/76.27 74726[143:SSi:74725.0,724.0,74060.0,74072.0] || -> . % 76.04/76.27 74727[142:Spt:74726.0,74455.0,74456.0] || until2p7(s34)*+ -> . % 76.04/76.27 74728[142:Spt:74726.0,74455.1] || -> node4(s33)*. % 76.04/76.27 74729[142:MRR:74049.0,74728.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.27 74732[142:Res:53.1,74729.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 74736[142:Res:74732.0,61.1] always3(s33) || -> . % 76.04/76.27 74737[142:SSi:74736.0,722.0,74040.0,74055.0,74454.0,74728.0] || -> . % 76.04/76.27 74738[141:Spt:74737.0,74453.0,74454.0] || until2p7(s33)*+ -> . % 76.04/76.27 74739[141:Spt:74737.0,74453.1] || -> node4(s32)*. % 76.04/76.27 74741[141:MRR:822.0,74739.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.27 74752[141:Res:53.1,74741.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.27 74754[142:Spt:74752.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 74756[142:Res:74754.0,61.1] always3(s32) || -> . % 76.04/76.27 74757[142:SSi:74756.0,721.0,74034.0,74039.0,74452.0,74739.0] || -> . % 76.04/76.27 74758[142:Spt:74757.0,74752.0,74754.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.27 74759[142:Spt:74757.0,74752.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 74763[142:Res:74759.0,61.1] always3(s33) || -> . % 76.04/76.27 74764[142:SSi:74763.0,722.0,74040.0,74055.0] || -> . % 76.04/76.27 74765[140:Spt:74764.0,74451.0,74452.0] || until2p7(s32)*+ -> . % 76.04/76.27 74766[140:Spt:74764.0,74451.1] || -> node4(s31)*. % 76.04/76.27 74768[140:MRR:825.0,74766.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.27 74775[140:Res:53.1,74768.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.27 74780[141:Spt:74775.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 74782[141:Res:74780.0,61.1] always3(s31) || -> . % 76.04/76.27 74783[141:SSi:74782.0,720.0,74031.0,74033.0,74450.0,74766.0] || -> . % 76.04/76.27 74784[141:Spt:74783.0,74775.0,74780.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.27 74785[141:Spt:74783.0,74775.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 74789[141:Res:74785.0,61.1] always3(s32) || -> . % 76.04/76.27 74790[141:SSi:74789.0,721.0,74034.0,74039.0] || -> . % 76.04/76.27 74791[139:Spt:74790.0,74449.0,74450.0] || until2p7(s31)*+ -> . % 76.04/76.27 74792[139:Spt:74790.0,74449.1] || -> node4(s30)*. % 76.04/76.27 74794[139:MRR:828.0,74792.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.27 74797[139:Res:53.1,74794.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.27 74799[140:Spt:74797.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 74801[140:Res:74799.0,61.1] always3(s30) || -> . % 76.04/76.27 74802[140:SSi:74801.0,719.0,74025.0,74030.0,74448.0,74792.0] || -> . % 76.04/76.27 74803[140:Spt:74802.0,74797.0,74799.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.27 74804[140:Spt:74802.0,74797.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 74808[140:Res:74804.0,61.1] always3(s31) || -> . % 76.04/76.27 74809[140:SSi:74808.0,720.0,74031.0,74033.0] || -> . % 76.04/76.27 74810[138:Spt:74809.0,74447.0,74448.0] || until2p7(s30)*+ -> . % 76.04/76.27 74811[138:Spt:74809.0,74447.1] || -> node4(s29)*. % 76.04/76.27 74813[138:MRR:831.0,74811.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.27 74816[138:Res:53.1,74813.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.27 74818[139:Spt:74816.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 74820[139:Res:74818.0,61.1] always3(s29) || -> . % 76.04/76.27 74821[139:SSi:74820.0,718.0,74022.0,74024.0,74446.0,74811.0] || -> . % 76.04/76.27 74822[139:Spt:74821.0,74816.0,74818.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.27 74823[139:Spt:74821.0,74816.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 74827[139:Res:74823.0,61.1] always3(s30) || -> . % 76.04/76.27 74828[139:SSi:74827.0,719.0,74025.0,74030.0] || -> . % 76.04/76.27 74829[137:Spt:74828.0,74445.0,74446.0] || until2p7(s29)*+ -> . % 76.04/76.27 74830[137:Spt:74828.0,74445.1] || -> node4(s28)*. % 76.04/76.27 74832[137:MRR:834.0,74830.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.27 74835[137:Res:53.1,74832.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.27 74837[138:Spt:74835.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 74839[138:Res:74837.0,61.1] always3(s28) || -> . % 76.04/76.27 74840[138:SSi:74839.0,717.0,74016.0,74021.0,74444.0,74830.0] || -> . % 76.04/76.27 74841[138:Spt:74840.0,74835.0,74837.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.27 74842[138:Spt:74840.0,74835.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 74846[138:Res:74842.0,61.1] always3(s29) || -> . % 76.04/76.27 74847[138:SSi:74846.0,718.0,74022.0,74024.0] || -> . % 76.04/76.27 74848[136:Spt:74847.0,74443.0,74444.0] || until2p7(s28)*+ -> . % 76.04/76.27 74849[136:Spt:74847.0,74443.1] || -> node4(s27)*. % 76.04/76.27 74851[136:MRR:837.0,74849.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.27 74854[136:Res:53.1,74851.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.27 74859[137:Spt:74854.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 74861[137:Res:74859.0,61.1] always3(s27) || -> . % 76.04/76.27 74862[137:SSi:74861.0,716.0,74013.0,74015.0,74442.0,74849.0] || -> . % 76.04/76.27 74863[137:Spt:74862.0,74854.0,74859.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.27 74864[137:Spt:74862.0,74854.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 74868[137:Res:74864.0,61.1] always3(s28) || -> . % 76.04/76.27 74869[137:SSi:74868.0,717.0,74016.0,74021.0] || -> . % 76.04/76.27 74870[135:Spt:74869.0,74441.0,74442.0] || until2p7(s27)*+ -> . % 76.04/76.27 74871[135:Spt:74869.0,74441.1] || -> node4(s26)*. % 76.04/76.27 74873[135:MRR:840.0,74871.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.27 74876[135:Res:53.1,74873.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.27 74878[136:Spt:74876.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 74880[136:Res:74878.0,61.1] always3(s26) || -> . % 76.04/76.27 74881[136:SSi:74880.0,715.0,74007.0,74012.0,74440.0,74871.0] || -> . % 76.04/76.27 74882[136:Spt:74881.0,74876.0,74878.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.27 74883[136:Spt:74881.0,74876.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 74887[136:Res:74883.0,61.1] always3(s27) || -> . % 76.04/76.27 74888[136:SSi:74887.0,716.0,74013.0,74015.0] || -> . % 76.04/76.27 74889[134:Spt:74888.0,74439.0,74440.0] || until2p7(s26)*+ -> . % 76.04/76.27 74890[134:Spt:74888.0,74439.1] || -> node4(s25)*. % 76.04/76.27 74892[134:MRR:843.0,74890.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.27 74895[134:Res:53.1,74892.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.27 74897[135:Spt:74895.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 74899[135:Res:74897.0,61.1] always3(s25) || -> . % 76.04/76.27 74900[135:SSi:74899.0,714.0,74004.0,74006.0,74438.0,74890.0] || -> . % 76.04/76.27 74901[135:Spt:74900.0,74895.0,74897.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.27 74902[135:Spt:74900.0,74895.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 74906[135:Res:74902.0,61.1] always3(s26) || -> . % 76.04/76.27 74907[135:SSi:74906.0,715.0,74007.0,74012.0] || -> . % 76.04/76.27 74908[133:Spt:74907.0,74437.0,74438.0] || until2p7(s25)*+ -> . % 76.04/76.27 74909[133:Spt:74907.0,74437.1] || -> node4(s24)*. % 76.04/76.27 74911[133:MRR:846.0,74909.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.27 74914[133:Res:53.1,74911.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.27 74916[134:Spt:74914.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 74918[134:Res:74916.0,61.1] always3(s24) || -> . % 76.04/76.27 74919[134:SSi:74918.0,713.0,73998.0,74003.0,74436.0,74909.0] || -> . % 76.04/76.27 74920[134:Spt:74919.0,74914.0,74916.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.27 74921[134:Spt:74919.0,74914.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 74925[134:Res:74921.0,61.1] always3(s25) || -> . % 76.04/76.27 74926[134:SSi:74925.0,714.0,74004.0,74006.0] || -> . % 76.04/76.27 74927[132:Spt:74926.0,74435.0,74436.0] || until2p7(s24)*+ -> . % 76.04/76.27 74928[132:Spt:74926.0,74435.1] || -> node4(s23)*. % 76.04/76.27 74930[132:MRR:849.0,74928.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.27 74933[132:Res:53.1,74930.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.27 74938[133:Spt:74933.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 74940[133:Res:74938.0,61.1] always3(s23) || -> . % 76.04/76.27 74941[133:SSi:74940.0,712.0,73995.0,73997.0,74434.0,74928.0] || -> . % 76.04/76.27 74942[133:Spt:74941.0,74933.0,74938.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.27 74943[133:Spt:74941.0,74933.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 74947[133:Res:74943.0,61.1] always3(s24) || -> . % 76.04/76.27 74948[133:SSi:74947.0,713.0,73998.0,74003.0] || -> . % 76.04/76.27 74949[131:Spt:74948.0,74433.0,74434.0] || until2p7(s23)*+ -> . % 76.04/76.27 74950[131:Spt:74948.0,74433.1] || -> node4(s22)*. % 76.04/76.27 74952[131:MRR:852.0,74950.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.27 74955[131:Res:53.1,74952.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.27 74957[132:Spt:74955.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 74959[132:Res:74957.0,61.1] always3(s22) || -> . % 76.04/76.27 74960[132:SSi:74959.0,711.0,73989.0,73994.0,74432.0,74950.0] || -> . % 76.04/76.27 74961[132:Spt:74960.0,74955.0,74957.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.27 74962[132:Spt:74960.0,74955.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 74966[132:Res:74962.0,61.1] always3(s23) || -> . % 76.04/76.27 74967[132:SSi:74966.0,712.0,73995.0,73997.0] || -> . % 76.04/76.27 74968[130:Spt:74967.0,74431.0,74432.0] || until2p7(s22)*+ -> . % 76.04/76.27 74969[130:Spt:74967.0,74431.1] || -> node4(s21)*. % 76.04/76.27 74971[130:MRR:855.0,74969.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.27 74974[130:Res:53.1,74971.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.27 74976[131:Spt:74974.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 74978[131:Res:74976.0,61.1] always3(s21) || -> . % 76.04/76.27 74979[131:SSi:74978.0,710.0,73986.0,73988.0,74430.0,74969.0] || -> . % 76.04/76.27 74980[131:Spt:74979.0,74974.0,74976.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.27 74981[131:Spt:74979.0,74974.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 74985[131:Res:74981.0,61.1] always3(s22) || -> . % 76.04/76.27 74986[131:SSi:74985.0,711.0,73989.0,73994.0] || -> . % 76.04/76.27 74987[129:Spt:74986.0,74429.0,74430.0] || until2p7(s21)*+ -> . % 76.04/76.27 74988[129:Spt:74986.0,74429.1] || -> node4(s20)*. % 76.04/76.27 74990[129:MRR:858.0,74988.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.27 74993[129:Res:53.1,74990.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.27 74995[130:Spt:74993.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 74997[130:Res:74995.0,61.1] always3(s20) || -> . % 76.04/76.27 74998[130:SSi:74997.0,709.0,73980.0,73985.0,74428.0,74988.0] || -> . % 76.04/76.27 74999[130:Spt:74998.0,74993.0,74995.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.27 75000[130:Spt:74998.0,74993.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 75004[130:Res:75000.0,61.1] always3(s21) || -> . % 76.04/76.27 75005[130:SSi:75004.0,710.0,73986.0,73988.0] || -> . % 76.04/76.27 75006[128:Spt:75005.0,74427.0,74428.0] || until2p7(s20)*+ -> . % 76.04/76.27 75007[128:Spt:75005.0,74427.1] || -> node4(s19)*. % 76.04/76.27 75009[128:MRR:861.0,75007.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.27 75012[128:Res:53.1,75009.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.27 75017[129:Spt:75012.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 75019[129:Res:75017.0,61.1] always3(s19) || -> . % 76.04/76.27 75020[129:SSi:75019.0,708.0,73977.0,73979.0,74426.0,75007.0] || -> . % 76.04/76.27 75021[129:Spt:75020.0,75012.0,75017.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.27 75022[129:Spt:75020.0,75012.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 75026[129:Res:75022.0,61.1] always3(s20) || -> . % 76.04/76.27 75027[129:SSi:75026.0,709.0,73980.0,73985.0] || -> . % 76.04/76.27 75028[127:Spt:75027.0,74425.0,74426.0] || until2p7(s19)*+ -> . % 76.04/76.27 75029[127:Spt:75027.0,74425.1] || -> node4(s18)*. % 76.04/76.27 75031[127:MRR:864.0,75029.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.27 75034[127:Res:53.1,75031.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.27 75036[128:Spt:75034.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 75038[128:Res:75036.0,61.1] always3(s18) || -> . % 76.04/76.27 75039[128:SSi:75038.0,707.0,73971.0,73976.0,74424.0,75029.0] || -> . % 76.04/76.27 75040[128:Spt:75039.0,75034.0,75036.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.27 75041[128:Spt:75039.0,75034.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 75045[128:Res:75041.0,61.1] always3(s19) || -> . % 76.04/76.27 75046[128:SSi:75045.0,708.0,73977.0,73979.0] || -> . % 76.04/76.27 75047[126:Spt:75046.0,74423.0,74424.0] || until2p7(s18)*+ -> . % 76.04/76.27 75048[126:Spt:75046.0,74423.1] || -> node4(s17)*. % 76.04/76.27 75050[126:MRR:867.0,75048.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.27 75053[126:Res:53.1,75050.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.27 75055[127:Spt:75053.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 75057[127:Res:75055.0,61.1] always3(s17) || -> . % 76.04/76.27 75058[127:SSi:75057.0,706.0,73968.0,73970.0,74422.0,75048.0] || -> . % 76.04/76.27 75059[127:Spt:75058.0,75053.0,75055.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.27 75060[127:Spt:75058.0,75053.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 75064[127:Res:75060.0,61.1] always3(s18) || -> . % 76.04/76.27 75065[127:SSi:75064.0,707.0,73971.0,73976.0] || -> . % 76.04/76.27 75066[125:Spt:75065.0,74421.0,74422.0] || until2p7(s17)*+ -> . % 76.04/76.27 75067[125:Spt:75065.0,74421.1] || -> node4(s16)*. % 76.04/76.27 75069[125:MRR:870.0,75067.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.27 75072[125:Res:53.1,75069.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.27 75074[126:Spt:75072.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 75076[126:Res:75074.0,61.1] always3(s16) || -> . % 76.04/76.27 75077[126:SSi:75076.0,705.0,73962.0,73967.0,74420.0,75067.0] || -> . % 76.04/76.27 75078[126:Spt:75077.0,75072.0,75074.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.27 75079[126:Spt:75077.0,75072.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 75083[126:Res:75079.0,61.1] always3(s17) || -> . % 76.04/76.27 75084[126:SSi:75083.0,706.0,73968.0,73970.0] || -> . % 76.04/76.27 75085[124:Spt:75084.0,74419.0,74420.0] || until2p7(s16)*+ -> . % 76.04/76.27 75086[124:Spt:75084.0,74419.1] || -> node4(s15)*. % 76.04/76.27 75088[124:MRR:873.0,75086.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.27 75091[124:Res:53.1,75088.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.27 75096[125:Spt:75091.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 75098[125:Res:75096.0,61.1] always3(s15) || -> . % 76.04/76.27 75099[125:SSi:75098.0,704.0,73959.0,73961.0,74418.0,75086.0] || -> . % 76.04/76.27 75100[125:Spt:75099.0,75091.0,75096.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.27 75101[125:Spt:75099.0,75091.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 75105[125:Res:75101.0,61.1] always3(s16) || -> . % 76.04/76.27 75106[125:SSi:75105.0,705.0,73962.0,73967.0] || -> . % 76.04/76.27 75107[123:Spt:75106.0,74417.0,74418.0] || until2p7(s15)*+ -> . % 76.04/76.27 75108[123:Spt:75106.0,74417.1] || -> node4(s14)*. % 76.04/76.27 75110[123:MRR:876.0,75108.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.27 75113[123:Res:53.1,75110.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.27 75115[124:Spt:75113.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 75117[124:Res:75115.0,61.1] always3(s14) || -> . % 76.04/76.27 75118[124:SSi:75117.0,703.0,73953.0,73958.0,74416.0,75108.0] || -> . % 76.04/76.27 75119[124:Spt:75118.0,75113.0,75115.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.27 75120[124:Spt:75118.0,75113.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 75124[124:Res:75120.0,61.1] always3(s15) || -> . % 76.04/76.27 75125[124:SSi:75124.0,704.0,73959.0,73961.0] || -> . % 76.04/76.27 75126[122:Spt:75125.0,74415.0,74416.0] || until2p7(s14)*+ -> . % 76.04/76.27 75127[122:Spt:75125.0,74415.1] || -> node4(s13)*. % 76.04/76.27 75129[122:MRR:879.0,75127.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.27 75132[122:Res:53.1,75129.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.27 75134[123:Spt:75132.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 75136[123:Res:75134.0,61.1] always3(s13) || -> . % 76.04/76.27 75137[123:SSi:75136.0,702.0,73950.0,73952.0,74414.0,75127.0] || -> . % 76.04/76.27 75138[123:Spt:75137.0,75132.0,75134.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.27 75139[123:Spt:75137.0,75132.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 75143[123:Res:75139.0,61.1] always3(s14) || -> . % 76.04/76.27 75144[123:SSi:75143.0,703.0,73953.0,73958.0] || -> . % 76.04/76.27 75145[121:Spt:75144.0,74413.0,74414.0] || until2p7(s13)*+ -> . % 76.04/76.27 75146[121:Spt:75144.0,74413.1] || -> node4(s12)*. % 76.04/76.27 75148[121:MRR:882.0,75146.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.27 75151[121:Res:53.1,75148.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.27 75153[122:Spt:75151.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 75155[122:Res:75153.0,61.1] always3(s12) || -> . % 76.04/76.27 75156[122:SSi:75155.0,701.0,73944.0,73949.0,74412.0,75146.0] || -> . % 76.04/76.27 75157[122:Spt:75156.0,75151.0,75153.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.27 75158[122:Spt:75156.0,75151.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 75162[122:Res:75158.0,61.1] always3(s13) || -> . % 76.04/76.27 75163[122:SSi:75162.0,702.0,73950.0,73952.0] || -> . % 76.04/76.27 75164[120:Spt:75163.0,74411.0,74412.0] || until2p7(s12)*+ -> . % 76.04/76.27 75165[120:Spt:75163.0,74411.1] || -> node4(s11)*. % 76.04/76.27 75167[120:MRR:885.0,75165.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.27 75170[120:Res:53.1,75167.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.27 75175[121:Spt:75170.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 75177[121:Res:75175.0,61.1] always3(s11) || -> . % 76.04/76.27 75178[121:SSi:75177.0,700.0,73941.0,73943.0,74410.0,75165.0] || -> . % 76.04/76.27 75179[121:Spt:75178.0,75170.0,75175.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.27 75180[121:Spt:75178.0,75170.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 75184[121:Res:75180.0,61.1] always3(s12) || -> . % 76.04/76.27 75185[121:SSi:75184.0,701.0,73944.0,73949.0] || -> . % 76.04/76.27 75186[119:Spt:75185.0,74409.0,74410.0] || until2p7(s11)*+ -> . % 76.04/76.27 75187[119:Spt:75185.0,74409.1] || -> node4(s10)*. % 76.04/76.27 75189[119:MRR:888.0,75187.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.27 75192[119:Res:53.1,75189.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.27 75194[120:Spt:75192.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 75196[120:Res:75194.0,61.1] always3(s10) || -> . % 76.04/76.27 75197[120:SSi:75196.0,699.0,73935.0,73940.0,74408.0,75187.0] || -> . % 76.04/76.27 75198[120:Spt:75197.0,75192.0,75194.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.27 75199[120:Spt:75197.0,75192.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 75203[120:Res:75199.0,61.1] always3(s11) || -> . % 76.04/76.27 75204[120:SSi:75203.0,700.0,73941.0,73943.0] || -> . % 76.04/76.27 75205[118:Spt:75204.0,74407.0,74408.0] || until2p7(s10)*+ -> . % 76.04/76.27 75206[118:Spt:75204.0,74407.1] || -> node4(s9)*. % 76.04/76.27 75208[118:MRR:891.0,75206.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.27 75211[118:Res:53.1,75208.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.27 75213[119:Spt:75211.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 75215[119:Res:75213.0,61.1] always3(s9) || -> . % 76.04/76.27 75216[119:SSi:75215.0,698.0,73932.0,73934.0,74406.0,75206.0] || -> . % 76.04/76.27 75217[119:Spt:75216.0,75211.0,75213.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.27 75218[119:Spt:75216.0,75211.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 75222[119:Res:75218.0,61.1] always3(s10) || -> . % 76.04/76.27 75223[119:SSi:75222.0,699.0,73935.0,73940.0] || -> . % 76.04/76.27 75224[117:Spt:75223.0,74405.0,74406.0] || until2p7(s9)*+ -> . % 76.04/76.27 75225[117:Spt:75223.0,74405.1] || -> node4(s8)*. % 76.04/76.27 75227[117:MRR:894.0,75225.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.27 75230[117:Res:53.1,75227.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.27 75232[118:Spt:75230.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 75234[118:Res:75232.0,61.1] always3(s8) || -> . % 76.04/76.27 75235[118:SSi:75234.0,697.0,73926.0,73931.0,74404.0,75225.0] || -> . % 76.04/76.27 75236[118:Spt:75235.0,75230.0,75232.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.27 75237[118:Spt:75235.0,75230.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 75241[118:Res:75237.0,61.1] always3(s9) || -> . % 76.04/76.27 75242[118:SSi:75241.0,698.0,73932.0,73934.0] || -> . % 76.04/76.27 75243[116:Spt:75242.0,74403.0,74404.0] || until2p7(s8)*+ -> . % 76.04/76.27 75244[116:Spt:75242.0,74403.1] || -> node4(s7)*. % 76.04/76.27 75246[116:MRR:897.0,75244.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.27 75249[116:Res:53.1,75246.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.27 75254[117:Spt:75249.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 75256[117:Res:75254.0,61.1] always3(s7) || -> . % 76.04/76.27 75257[117:SSi:75256.0,696.0,73923.0,73925.0,74402.0,75244.0] || -> . % 76.04/76.27 75258[117:Spt:75257.0,75249.0,75254.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.27 75259[117:Spt:75257.0,75249.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 75263[117:Res:75259.0,61.1] always3(s8) || -> . % 76.04/76.27 75264[117:SSi:75263.0,697.0,73926.0,73931.0] || -> . % 76.04/76.27 75265[115:Spt:75264.0,74401.0,74402.0] || until2p7(s7)*+ -> . % 76.04/76.27 75266[115:Spt:75264.0,74401.1] || -> node4(s6)*. % 76.04/76.27 75268[115:MRR:900.0,75266.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.27 75271[115:Res:53.1,75268.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.27 75273[116:Spt:75271.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 75275[116:Res:75273.0,61.1] always3(s6) || -> . % 76.04/76.27 75276[116:SSi:75275.0,695.0,73917.0,73922.0,74400.0,75266.0] || -> . % 76.04/76.27 75277[116:Spt:75276.0,75271.0,75273.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.27 75278[116:Spt:75276.0,75271.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 75282[116:Res:75278.0,61.1] always3(s7) || -> . % 76.04/76.27 75283[116:SSi:75282.0,696.0,73923.0,73925.0] || -> . % 76.04/76.27 75284[114:Spt:75283.0,74399.0,74400.0] || until2p7(s6)*+ -> . % 76.04/76.27 75285[114:Spt:75283.0,74399.1] || -> node4(s5)*. % 76.04/76.27 75287[114:MRR:903.0,75285.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.27 75290[114:Res:53.1,75287.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.27 75292[115:Spt:75290.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 75294[115:Res:75292.0,61.1] always3(s5) || -> . % 76.04/76.27 75295[115:SSi:75294.0,694.0,73914.0,73916.0,74398.0,75285.0] || -> . % 76.04/76.27 75296[115:Spt:75295.0,75290.0,75292.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.27 75297[115:Spt:75295.0,75290.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 75301[115:Res:75297.0,61.1] always3(s6) || -> . % 76.04/76.27 75302[115:SSi:75301.0,695.0,73917.0,73922.0] || -> . % 76.04/76.27 75303[113:Spt:75302.0,74397.0,74398.0] || until2p7(s5)*+ -> . % 76.04/76.27 75304[113:Spt:75302.0,74397.1] || -> node4(s4)*. % 76.04/76.27 75306[113:MRR:906.0,75304.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.27 75309[113:Res:53.1,75306.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.27 75311[114:Spt:75309.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 75313[114:Res:75311.0,61.1] always3(s4) || -> . % 76.04/76.27 75314[114:SSi:75313.0,693.0,73908.0,73913.0,74396.0,75304.0] || -> . % 76.04/76.27 75315[114:Spt:75314.0,75309.0,75311.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.27 75316[114:Spt:75314.0,75309.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 75320[114:Res:75316.0,61.1] always3(s5) || -> . % 76.04/76.27 75321[114:SSi:75320.0,694.0,73914.0,73916.0] || -> . % 76.04/76.27 75322[112:Spt:75321.0,74395.0,74396.0] || until2p7(s4)*+ -> . % 76.04/76.27 75323[112:Spt:75321.0,74395.1] || -> node4(s3)*. % 76.04/76.27 75325[112:MRR:909.0,75323.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.27 75328[112:Res:53.1,75325.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.27 75333[113:Spt:75328.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 75335[113:Res:75333.0,61.1] always3(s3) || -> . % 76.04/76.27 75336[113:SSi:75335.0,692.0,73905.0,73907.0,74394.0,75323.0] || -> . % 76.04/76.27 75337[113:Spt:75336.0,75328.0,75333.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.27 75338[113:Spt:75336.0,75328.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 75342[113:Res:75338.0,61.1] always3(s4) || -> . % 76.04/76.27 75343[113:SSi:75342.0,693.0,73908.0,73913.0] || -> . % 76.04/76.27 75344[111:Spt:75343.0,74393.0,74394.0] || until2p7(s3)*+ -> . % 76.04/76.27 75345[111:Spt:75343.0,74393.1] || -> node4(s2)*. % 76.04/76.27 75347[111:MRR:912.0,75345.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.27 75350[111:Res:53.1,75347.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.27 75352[112:Spt:75350.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 75354[112:Res:75352.0,61.1] always3(s2) || -> . % 76.04/76.27 75355[112:SSi:75354.0,691.0,73899.0,73904.0,74392.0,75345.0] || -> . % 76.04/76.27 75356[112:Spt:75355.0,75350.0,75352.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.27 75357[112:Spt:75355.0,75350.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 75361[112:Res:75357.0,61.1] always3(s3) || -> . % 76.04/76.27 75362[112:SSi:75361.0,692.0,73905.0,73907.0] || -> . % 76.04/76.27 75363[110:Spt:75362.0,74389.0,74392.0] || until2p7(s2)*+ -> . % 76.04/76.27 75364[110:Spt:75362.0,74389.1] || -> node4(s1)*. % 76.04/76.27 75366[110:MRR:915.0,75364.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.27 75369[110:Res:53.1,75366.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.27 75371[110:MRR:75369.0,74370.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 75373[110:Res:75371.0,61.1] always3(s2) || -> . % 76.04/76.27 75374[110:SSi:75373.0,691.0,73899.0,73904.0] || -> . % 76.04/76.27 75375[107:Spt:75374.0,74200.2,74205.0] || xuntil6(s48)*+ -> . % 76.04/76.27 75376[107:Spt:75374.0,74200.0,74200.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.27 75377[107:Res:53.1,75376.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.27 75379[107:MRR:75377.0,74192.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 75382[107:Res:75379.0,61.1] always3(s49) || -> . % 76.04/76.27 75383[107:SSi:75382.0,50.0,738.0] || -> . % 76.04/76.27 75384[106:Spt:75383.0,74196.1,74198.0] || xuntil6(s47)* -> . % 76.04/76.27 75385[106:Spt:75383.0,74196.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 75388[106:Res:75385.0,61.1] always3(s47) || -> . % 76.04/76.27 75389[106:SSi:75388.0,736.0,74186.0] || -> . % 76.04/76.27 75390[104:Spt:75389.0,74183.2,74185.0] || xuntil6(s46)*+ -> . % 76.04/76.27 75391[104:Spt:75389.0,74183.0,74183.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.27 75392[104:Res:53.1,75391.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.27 75394[104:MRR:75392.0,74172.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 75396[104:Res:75394.0,61.1] always3(s47) || -> . % 76.04/76.27 75397[104:SSi:75396.0,736.0] || -> . % 76.04/76.27 75398[103:Spt:75397.0,74176.1,74181.0] || xuntil6(s45)* -> . % 76.04/76.27 75399[103:Spt:75397.0,74176.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 75402[103:Res:75399.0,61.1] always3(s45) || -> . % 76.04/76.27 75403[103:SSi:75402.0,734.0,74166.0] || -> . % 76.04/76.27 75404[101:Spt:75403.0,74157.2,74165.0] || xuntil6(s44)*+ -> . % 76.04/76.27 75405[101:Spt:75403.0,74157.0,74157.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.27 75406[101:Res:53.1,75405.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.27 75408[101:MRR:75406.0,74149.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 75411[101:Res:75408.0,61.1] always3(s45) || -> . % 76.04/76.27 75412[101:SSi:75411.0,734.0] || -> . % 76.04/76.27 75413[100:Spt:75412.0,74153.1,74155.0] || xuntil6(s43)* -> . % 76.04/76.27 75414[100:Spt:75412.0,74153.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 75417[100:Res:75414.0,61.1] always3(s43) || -> . % 76.04/76.27 75418[100:SSi:75417.0,732.0,74143.0] || -> . % 76.04/76.27 75419[98:Spt:75418.0,74137.2,74142.0] || xuntil6(s42)*+ -> . % 76.04/76.27 75420[98:Spt:75418.0,74137.0,74137.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.27 75421[98:Res:53.1,75420.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.27 75423[98:MRR:75421.0,74129.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 75425[98:Res:75423.0,61.1] always3(s43) || -> . % 76.04/76.27 75426[98:SSi:75425.0,732.0] || -> . % 76.04/76.27 75427[97:Spt:75426.0,74133.1,74135.0] || xuntil6(s41)* -> . % 76.04/76.27 75428[97:Spt:75426.0,74133.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 75431[97:Res:75428.0,61.1] always3(s41) || -> . % 76.04/76.27 75432[97:SSi:75431.0,730.0,74123.0] || -> . % 76.04/76.27 75433[95:Spt:75432.0,74120.2,74122.0] || xuntil6(s40)*+ -> . % 76.04/76.27 75434[95:Spt:75432.0,74120.0,74120.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.27 75435[95:Res:53.1,75434.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.27 75437[95:MRR:75435.0,74109.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 75439[95:Res:75437.0,61.1] always3(s41) || -> . % 76.04/76.27 75440[95:SSi:75439.0,730.0] || -> . % 76.04/76.27 75441[94:Spt:75440.0,74113.1,74118.0] || xuntil6(s39)* -> . % 76.04/76.27 75442[94:Spt:75440.0,74113.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 75445[94:Res:75442.0,61.1] always3(s39) || -> . % 76.04/76.27 75446[94:SSi:75445.0,728.0,74103.0] || -> . % 76.04/76.27 75447[92:Spt:75446.0,74094.2,74102.0] || xuntil6(s38)*+ -> . % 76.04/76.27 75448[92:Spt:75446.0,74094.0,74094.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.27 75449[92:Res:53.1,75448.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.27 75451[92:MRR:75449.0,74086.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 75453[92:Res:75451.0,61.1] always3(s39) || -> . % 76.04/76.27 75454[92:SSi:75453.0,728.0] || -> . % 76.04/76.27 75455[91:Spt:75454.0,74090.1,74092.0] || xuntil6(s37)* -> . % 76.04/76.27 75456[91:Spt:75454.0,74090.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 75459[91:Res:75456.0,61.1] always3(s37) || -> . % 76.04/76.27 75460[91:SSi:75459.0,726.0,74080.0] || -> . % 76.04/76.27 75461[89:Spt:75460.0,74074.2,74079.0] || xuntil6(s36)*+ -> . % 76.04/76.27 75462[89:Spt:75460.0,74074.0,74074.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.27 75463[89:Res:53.1,75462.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.27 75465[89:MRR:75463.0,74066.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 75467[89:Res:75465.0,61.1] always3(s37) || -> . % 76.04/76.27 75468[89:SSi:75467.0,726.0] || -> . % 76.04/76.27 75469[88:Spt:75468.0,74070.1,74072.0] || xuntil6(s35)* -> . % 76.04/76.27 75470[88:Spt:75468.0,74070.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 75473[88:Res:75470.0,61.1] always3(s35) || -> . % 76.04/76.27 75474[88:SSi:75473.0,724.0,74060.0] || -> . % 76.04/76.27 75475[86:Spt:75474.0,74057.2,74059.0] || xuntil6(s34)*+ -> . % 76.04/76.27 75476[86:Spt:75474.0,74057.0,74057.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.27 75477[86:Res:53.1,75476.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.27 75479[86:MRR:75477.0,74046.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 75481[86:Res:75479.0,61.1] always3(s35) || -> . % 76.04/76.27 75482[86:SSi:75481.0,724.0] || -> . % 76.04/76.27 75483[85:Spt:75482.0,74050.1,74055.0] || xuntil6(s33)* -> . % 76.04/76.27 75484[85:Spt:75482.0,74050.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 75487[85:Res:75484.0,61.1] always3(s33) || -> . % 76.04/76.27 75488[85:SSi:75487.0,722.0,74040.0] || -> . % 76.04/76.27 75489[83:Spt:75488.0,74035.2,74039.0] || xuntil6(s32)*+ -> . % 76.04/76.27 75490[83:Spt:75488.0,74035.0,74035.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.27 75491[83:Res:53.1,75490.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.27 75496[84:Spt:75491.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 75498[84:Res:75496.0,61.1] always3(s32) || -> . % 76.04/76.27 75499[84:SSi:75498.0,721.0,74034.0] || -> . % 76.04/76.27 75500[84:Spt:75499.0,75491.0,75496.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.27 75501[84:Spt:75499.0,75491.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 75505[84:Res:75501.0,61.1] always3(s33) || -> . % 76.04/76.27 75506[84:SSi:75505.0,722.0] || -> . % 76.04/76.27 75507[82:Spt:75506.0,74032.2,74033.0] || xuntil6(s31)*+ -> . % 76.04/76.27 75508[82:Spt:75506.0,74032.0,74032.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.27 75509[82:Res:53.1,75508.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.27 75511[83:Spt:75509.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 75513[83:Res:75511.0,61.1] always3(s32) || -> . % 76.04/76.27 75514[83:SSi:75513.0,721.0] || -> . % 76.04/76.27 75515[83:Spt:75514.0,75509.1,75511.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.27 75516[83:Spt:75514.0,75509.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 75519[83:Res:75516.0,61.1] always3(s31) || -> . % 76.04/76.27 75520[83:SSi:75519.0,720.0,74031.0] || -> . % 76.04/76.27 75521[81:Spt:75520.0,74026.2,74030.0] || xuntil6(s30)*+ -> . % 76.04/76.27 75522[81:Spt:75520.0,74026.0,74026.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.27 75523[81:Res:53.1,75522.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.27 75525[82:Spt:75523.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 75527[82:Res:75525.0,61.1] always3(s31) || -> . % 76.04/76.27 75528[82:SSi:75527.0,720.0] || -> . % 76.04/76.27 75529[82:Spt:75528.0,75523.1,75525.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.27 75530[82:Spt:75528.0,75523.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 75533[82:Res:75530.0,61.1] always3(s30) || -> . % 76.04/76.27 75534[82:SSi:75533.0,719.0,74025.0] || -> . % 76.04/76.27 75535[80:Spt:75534.0,74023.2,74024.0] || xuntil6(s29)*+ -> . % 76.04/76.27 75536[80:Spt:75534.0,74023.0,74023.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.27 75537[80:Res:53.1,75536.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.27 75539[81:Spt:75537.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 75541[81:Res:75539.0,61.1] always3(s30) || -> . % 76.04/76.27 75542[81:SSi:75541.0,719.0] || -> . % 76.04/76.27 75543[81:Spt:75542.0,75537.1,75539.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.27 75544[81:Spt:75542.0,75537.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 75547[81:Res:75544.0,61.1] always3(s29) || -> . % 76.04/76.27 75548[81:SSi:75547.0,718.0,74022.0] || -> . % 76.04/76.27 75549[79:Spt:75548.0,74017.2,74021.0] || xuntil6(s28)*+ -> . % 76.04/76.27 75550[79:Spt:75548.0,74017.0,74017.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.27 75551[79:Res:53.1,75550.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.27 75553[80:Spt:75551.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 75555[80:Res:75553.0,61.1] always3(s29) || -> . % 76.04/76.27 75556[80:SSi:75555.0,718.0] || -> . % 76.04/76.27 75557[80:Spt:75556.0,75551.1,75553.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.27 75558[80:Spt:75556.0,75551.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 75561[80:Res:75558.0,61.1] always3(s28) || -> . % 76.04/76.27 75562[80:SSi:75561.0,717.0,74016.0] || -> . % 76.04/76.27 75563[78:Spt:75562.0,74014.2,74015.0] || xuntil6(s27)*+ -> . % 76.04/76.27 75564[78:Spt:75562.0,74014.0,74014.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.27 75565[78:Res:53.1,75564.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.27 75567[79:Spt:75565.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 75569[79:Res:75567.0,61.1] always3(s28) || -> . % 76.04/76.27 75570[79:SSi:75569.0,717.0] || -> . % 76.04/76.27 75571[79:Spt:75570.0,75565.1,75567.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.27 75572[79:Spt:75570.0,75565.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 75575[79:Res:75572.0,61.1] always3(s27) || -> . % 76.04/76.27 75576[79:SSi:75575.0,716.0,74013.0] || -> . % 76.04/76.27 75577[77:Spt:75576.0,74008.2,74012.0] || xuntil6(s26)*+ -> . % 76.04/76.27 75578[77:Spt:75576.0,74008.0,74008.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.27 75579[77:Res:53.1,75578.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.27 75581[78:Spt:75579.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 75583[78:Res:75581.0,61.1] always3(s27) || -> . % 76.04/76.27 75584[78:SSi:75583.0,716.0] || -> . % 76.04/76.27 75585[78:Spt:75584.0,75579.1,75581.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.27 75586[78:Spt:75584.0,75579.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 75589[78:Res:75586.0,61.1] always3(s26) || -> . % 76.04/76.27 75590[78:SSi:75589.0,715.0,74007.0] || -> . % 76.04/76.27 75591[76:Spt:75590.0,74005.2,74006.0] || xuntil6(s25)*+ -> . % 76.04/76.27 75592[76:Spt:75590.0,74005.0,74005.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.27 75593[76:Res:53.1,75592.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.27 75595[77:Spt:75593.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 75597[77:Res:75595.0,61.1] always3(s26) || -> . % 76.04/76.27 75598[77:SSi:75597.0,715.0] || -> . % 76.04/76.27 75599[77:Spt:75598.0,75593.1,75595.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.27 75600[77:Spt:75598.0,75593.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 75603[77:Res:75600.0,61.1] always3(s25) || -> . % 76.04/76.27 75604[77:SSi:75603.0,714.0,74004.0] || -> . % 76.04/76.27 75605[75:Spt:75604.0,73999.2,74003.0] || xuntil6(s24)*+ -> . % 76.04/76.27 75606[75:Spt:75604.0,73999.0,73999.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.27 75607[75:Res:53.1,75606.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.27 75609[76:Spt:75607.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 75611[76:Res:75609.0,61.1] always3(s25) || -> . % 76.04/76.27 75612[76:SSi:75611.0,714.0] || -> . % 76.04/76.27 75613[76:Spt:75612.0,75607.1,75609.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.27 75614[76:Spt:75612.0,75607.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 75617[76:Res:75614.0,61.1] always3(s24) || -> . % 76.04/76.27 75618[76:SSi:75617.0,713.0,73998.0] || -> . % 76.04/76.27 75619[74:Spt:75618.0,73996.2,73997.0] || xuntil6(s23)*+ -> . % 76.04/76.27 75620[74:Spt:75618.0,73996.0,73996.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.27 75621[74:Res:53.1,75620.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.27 75623[75:Spt:75621.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 75625[75:Res:75623.0,61.1] always3(s24) || -> . % 76.04/76.27 75626[75:SSi:75625.0,713.0] || -> . % 76.04/76.27 75627[75:Spt:75626.0,75621.1,75623.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.27 75628[75:Spt:75626.0,75621.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 75631[75:Res:75628.0,61.1] always3(s23) || -> . % 76.04/76.27 75632[75:SSi:75631.0,712.0,73995.0] || -> . % 76.04/76.27 75633[73:Spt:75632.0,73990.2,73994.0] || xuntil6(s22)*+ -> . % 76.04/76.27 75634[73:Spt:75632.0,73990.0,73990.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.27 75635[73:Res:53.1,75634.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.27 75640[74:Spt:75635.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 75642[74:Res:75640.0,61.1] always3(s22) || -> . % 76.04/76.27 75643[74:SSi:75642.0,711.0,73989.0] || -> . % 76.04/76.27 75644[74:Spt:75643.0,75635.0,75640.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.27 75645[74:Spt:75643.0,75635.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 75649[74:Res:75645.0,61.1] always3(s23) || -> . % 76.04/76.27 75650[74:SSi:75649.0,712.0] || -> . % 76.04/76.27 75651[72:Spt:75650.0,73987.2,73988.0] || xuntil6(s21)*+ -> . % 76.04/76.27 75652[72:Spt:75650.0,73987.0,73987.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.27 75653[72:Res:53.1,75652.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.27 75655[73:Spt:75653.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 75657[73:Res:75655.0,61.1] always3(s22) || -> . % 76.04/76.27 75658[73:SSi:75657.0,711.0] || -> . % 76.04/76.27 75659[73:Spt:75658.0,75653.1,75655.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.27 75660[73:Spt:75658.0,75653.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 75663[73:Res:75660.0,61.1] always3(s21) || -> . % 76.04/76.27 75664[73:SSi:75663.0,710.0,73986.0] || -> . % 76.04/76.27 75665[71:Spt:75664.0,73981.2,73985.0] || xuntil6(s20)*+ -> . % 76.04/76.27 75666[71:Spt:75664.0,73981.0,73981.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.27 75667[71:Res:53.1,75666.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.27 75669[72:Spt:75667.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 75671[72:Res:75669.0,61.1] always3(s21) || -> . % 76.04/76.27 75672[72:SSi:75671.0,710.0] || -> . % 76.04/76.27 75673[72:Spt:75672.0,75667.1,75669.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.27 75674[72:Spt:75672.0,75667.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 75677[72:Res:75674.0,61.1] always3(s20) || -> . % 76.04/76.27 75678[72:SSi:75677.0,709.0,73980.0] || -> . % 76.04/76.27 75679[70:Spt:75678.0,73978.2,73979.0] || xuntil6(s19)*+ -> . % 76.04/76.27 75680[70:Spt:75678.0,73978.0,73978.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.27 75681[70:Res:53.1,75680.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.27 75686[71:Spt:75681.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 75688[71:Res:75686.0,61.1] always3(s19) || -> . % 76.04/76.27 75689[71:SSi:75688.0,708.0,73977.0] || -> . % 76.04/76.27 75690[71:Spt:75689.0,75681.0,75686.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.27 75691[71:Spt:75689.0,75681.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 75695[71:Res:75691.0,61.1] always3(s20) || -> . % 76.04/76.27 75696[71:SSi:75695.0,709.0] || -> . % 76.04/76.27 75697[69:Spt:75696.0,73972.2,73976.0] || xuntil6(s18)*+ -> . % 76.04/76.27 75698[69:Spt:75696.0,73972.0,73972.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.27 75699[69:Res:53.1,75698.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.27 75701[70:Spt:75699.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 75703[70:Res:75701.0,61.1] always3(s19) || -> . % 76.04/76.27 75704[70:SSi:75703.0,708.0] || -> . % 76.04/76.27 75705[70:Spt:75704.0,75699.1,75701.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.27 75706[70:Spt:75704.0,75699.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 75709[70:Res:75706.0,61.1] always3(s18) || -> . % 76.04/76.27 75710[70:SSi:75709.0,707.0,73971.0] || -> . % 76.04/76.27 75711[68:Spt:75710.0,73969.2,73970.0] || xuntil6(s17)*+ -> . % 76.04/76.27 75712[68:Spt:75710.0,73969.0,73969.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.27 75713[68:Res:53.1,75712.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.27 75715[69:Spt:75713.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 75717[69:Res:75715.0,61.1] always3(s18) || -> . % 76.04/76.27 75718[69:SSi:75717.0,707.0] || -> . % 76.04/76.27 75719[69:Spt:75718.0,75713.1,75715.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.27 75720[69:Spt:75718.0,75713.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 75723[69:Res:75720.0,61.1] always3(s17) || -> . % 76.04/76.27 75724[69:SSi:75723.0,706.0,73968.0] || -> . % 76.04/76.27 75725[67:Spt:75724.0,73963.2,73967.0] || xuntil6(s16)*+ -> . % 76.04/76.27 75726[67:Spt:75724.0,73963.0,73963.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.27 75727[67:Res:53.1,75726.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.27 75732[68:Spt:75727.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 75734[68:Res:75732.0,61.1] always3(s16) || -> . % 76.04/76.27 75735[68:SSi:75734.0,705.0,73962.0] || -> . % 76.04/76.27 75736[68:Spt:75735.0,75727.0,75732.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.27 75737[68:Spt:75735.0,75727.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 75741[68:Res:75737.0,61.1] always3(s17) || -> . % 76.04/76.27 75742[68:SSi:75741.0,706.0] || -> . % 76.04/76.27 75743[66:Spt:75742.0,73960.2,73961.0] || xuntil6(s15)*+ -> . % 76.04/76.27 75744[66:Spt:75742.0,73960.0,73960.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.27 75745[66:Res:53.1,75744.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.27 75747[67:Spt:75745.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 75749[67:Res:75747.0,61.1] always3(s16) || -> . % 76.04/76.27 75750[67:SSi:75749.0,705.0] || -> . % 76.04/76.27 75751[67:Spt:75750.0,75745.1,75747.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.27 75752[67:Spt:75750.0,75745.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 75755[67:Res:75752.0,61.1] always3(s15) || -> . % 76.04/76.27 75756[67:SSi:75755.0,704.0,73959.0] || -> . % 76.04/76.27 75757[65:Spt:75756.0,73954.2,73958.0] || xuntil6(s14)*+ -> . % 76.04/76.27 75758[65:Spt:75756.0,73954.0,73954.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.27 75759[65:Res:53.1,75758.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.27 75761[66:Spt:75759.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 75763[66:Res:75761.0,61.1] always3(s15) || -> . % 76.04/76.27 75764[66:SSi:75763.0,704.0] || -> . % 76.04/76.27 75765[66:Spt:75764.0,75759.1,75761.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.27 75766[66:Spt:75764.0,75759.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 75769[66:Res:75766.0,61.1] always3(s14) || -> . % 76.04/76.27 75770[66:SSi:75769.0,703.0,73953.0] || -> . % 76.04/76.27 75771[64:Spt:75770.0,73951.2,73952.0] || xuntil6(s13)*+ -> . % 76.04/76.27 75772[64:Spt:75770.0,73951.0,73951.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.27 75773[64:Res:53.1,75772.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.27 75778[65:Spt:75773.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 75780[65:Res:75778.0,61.1] always3(s13) || -> . % 76.04/76.27 75781[65:SSi:75780.0,702.0,73950.0] || -> . % 76.04/76.27 75782[65:Spt:75781.0,75773.0,75778.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.27 75783[65:Spt:75781.0,75773.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 75787[65:Res:75783.0,61.1] always3(s14) || -> . % 76.04/76.27 75788[65:SSi:75787.0,703.0] || -> . % 76.04/76.27 75789[63:Spt:75788.0,73945.2,73949.0] || xuntil6(s12)*+ -> . % 76.04/76.27 75790[63:Spt:75788.0,73945.0,73945.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.27 75791[63:Res:53.1,75790.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.27 75793[64:Spt:75791.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 75795[64:Res:75793.0,61.1] always3(s13) || -> . % 76.04/76.27 75796[64:SSi:75795.0,702.0] || -> . % 76.04/76.27 75797[64:Spt:75796.0,75791.1,75793.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.27 75798[64:Spt:75796.0,75791.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 75801[64:Res:75798.0,61.1] always3(s12) || -> . % 76.04/76.27 75802[64:SSi:75801.0,701.0,73944.0] || -> . % 76.04/76.27 75803[62:Spt:75802.0,73942.2,73943.0] || xuntil6(s11)*+ -> . % 76.04/76.27 75804[62:Spt:75802.0,73942.0,73942.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.27 75805[62:Res:53.1,75804.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.27 75807[63:Spt:75805.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 75809[63:Res:75807.0,61.1] always3(s12) || -> . % 76.04/76.27 75810[63:SSi:75809.0,701.0] || -> . % 76.04/76.27 75811[63:Spt:75810.0,75805.1,75807.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.27 75812[63:Spt:75810.0,75805.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 75815[63:Res:75812.0,61.1] always3(s11) || -> . % 76.04/76.27 75816[63:SSi:75815.0,700.0,73941.0] || -> . % 76.04/76.27 75817[61:Spt:75816.0,73936.2,73940.0] || xuntil6(s10)*+ -> . % 76.04/76.27 75818[61:Spt:75816.0,73936.0,73936.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.27 75819[61:Res:53.1,75818.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.27 75824[62:Spt:75819.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 75826[62:Res:75824.0,61.1] always3(s10) || -> . % 76.04/76.27 75827[62:SSi:75826.0,699.0,73935.0] || -> . % 76.04/76.27 75828[62:Spt:75827.0,75819.0,75824.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.27 75829[62:Spt:75827.0,75819.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 75833[62:Res:75829.0,61.1] always3(s11) || -> . % 76.04/76.27 75834[62:SSi:75833.0,700.0] || -> . % 76.04/76.27 75835[60:Spt:75834.0,73933.2,73934.0] || xuntil6(s9)*+ -> . % 76.04/76.27 75836[60:Spt:75834.0,73933.0,73933.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.27 75837[60:Res:53.1,75836.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.27 75839[61:Spt:75837.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 75841[61:Res:75839.0,61.1] always3(s10) || -> . % 76.04/76.27 75842[61:SSi:75841.0,699.0] || -> . % 76.04/76.27 75843[61:Spt:75842.0,75837.1,75839.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.27 75844[61:Spt:75842.0,75837.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 75847[61:Res:75844.0,61.1] always3(s9) || -> . % 76.04/76.27 75848[61:SSi:75847.0,698.0,73932.0] || -> . % 76.04/76.27 75849[59:Spt:75848.0,73927.2,73931.0] || xuntil6(s8)*+ -> . % 76.04/76.27 75850[59:Spt:75848.0,73927.0,73927.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.27 75851[59:Res:53.1,75850.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.27 75853[60:Spt:75851.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 75855[60:Res:75853.0,61.1] always3(s9) || -> . % 76.04/76.27 75856[60:SSi:75855.0,698.0] || -> . % 76.04/76.27 75857[60:Spt:75856.0,75851.1,75853.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.27 75858[60:Spt:75856.0,75851.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 75861[60:Res:75858.0,61.1] always3(s8) || -> . % 76.04/76.27 75862[60:SSi:75861.0,697.0,73926.0] || -> . % 76.04/76.27 75863[58:Spt:75862.0,73924.2,73925.0] || xuntil6(s7)*+ -> . % 76.04/76.27 75864[58:Spt:75862.0,73924.0,73924.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.27 75865[58:Res:53.1,75864.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.27 75870[59:Spt:75865.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 75872[59:Res:75870.0,61.1] always3(s7) || -> . % 76.04/76.27 75873[59:SSi:75872.0,696.0,73923.0] || -> . % 76.04/76.27 75874[59:Spt:75873.0,75865.0,75870.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.27 75875[59:Spt:75873.0,75865.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 75879[59:Res:75875.0,61.1] always3(s8) || -> . % 76.04/76.27 75880[59:SSi:75879.0,697.0] || -> . % 76.04/76.27 75881[57:Spt:75880.0,73918.2,73922.0] || xuntil6(s6)*+ -> . % 76.04/76.27 75882[57:Spt:75880.0,73918.0,73918.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.27 75883[57:Res:53.1,75882.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.27 75885[58:Spt:75883.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 75887[58:Res:75885.0,61.1] always3(s7) || -> . % 76.04/76.27 75888[58:SSi:75887.0,696.0] || -> . % 76.04/76.27 75889[58:Spt:75888.0,75883.1,75885.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.27 75890[58:Spt:75888.0,75883.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 75893[58:Res:75890.0,61.1] always3(s6) || -> . % 76.04/76.27 75894[58:SSi:75893.0,695.0,73917.0] || -> . % 76.04/76.27 75895[56:Spt:75894.0,73915.2,73916.0] || xuntil6(s5)*+ -> . % 76.04/76.27 75896[56:Spt:75894.0,73915.0,73915.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.27 75897[56:Res:53.1,75896.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.27 75899[57:Spt:75897.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 75901[57:Res:75899.0,61.1] always3(s6) || -> . % 76.04/76.27 75902[57:SSi:75901.0,695.0] || -> . % 76.04/76.27 75903[57:Spt:75902.0,75897.1,75899.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.27 75904[57:Spt:75902.0,75897.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 75907[57:Res:75904.0,61.1] always3(s5) || -> . % 76.04/76.27 75908[57:SSi:75907.0,694.0,73914.0] || -> . % 76.04/76.27 75909[55:Spt:75908.0,73909.2,73913.0] || xuntil6(s4)*+ -> . % 76.04/76.27 75910[55:Spt:75908.0,73909.0,73909.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.27 75911[55:Res:53.1,75910.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.27 75916[56:Spt:75911.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 75918[56:Res:75916.0,61.1] always3(s4) || -> . % 76.04/76.27 75919[56:SSi:75918.0,693.0,73908.0] || -> . % 76.04/76.27 75920[56:Spt:75919.0,75911.0,75916.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.27 75921[56:Spt:75919.0,75911.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 75925[56:Res:75921.0,61.1] always3(s5) || -> . % 76.04/76.27 75926[56:SSi:75925.0,694.0] || -> . % 76.04/76.27 75927[54:Spt:75926.0,73906.2,73907.0] || xuntil6(s3)*+ -> . % 76.04/76.27 75928[54:Spt:75926.0,73906.0,73906.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.27 75929[54:Res:53.1,75928.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.27 75931[55:Spt:75929.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 75933[55:Res:75931.0,61.1] always3(s4) || -> . % 76.04/76.27 75934[55:SSi:75933.0,693.0] || -> . % 76.04/76.27 75935[55:Spt:75934.0,75929.1,75931.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.27 75936[55:Spt:75934.0,75929.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 75939[55:Res:75936.0,61.1] always3(s3) || -> . % 76.04/76.27 75940[55:SSi:75939.0,692.0,73905.0] || -> . % 76.04/76.27 75941[53:Spt:75940.0,73900.2,73904.0] || xuntil6(s2)*+ -> . % 76.04/76.27 75942[53:Spt:75940.0,73900.0,73900.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.27 75943[53:Res:53.1,75942.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.27 75945[54:Spt:75943.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 75947[54:Res:75945.0,61.1] always3(s3) || -> . % 76.04/76.27 75948[54:SSi:75947.0,692.0] || -> . % 76.04/76.27 75949[54:Spt:75948.0,75943.1,75945.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.27 75950[54:Spt:75948.0,75943.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 75953[54:Res:75950.0,61.1] always3(s2) || -> . % 76.04/76.27 75954[54:SSi:75953.0,691.0,73899.0] || -> . % 76.04/76.27 75955[52:Spt:75954.0,73894.2,73898.0] || xuntil6(s1)*+ -> . % 76.04/76.27 75956[52:Spt:75954.0,73894.0,73894.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.27 75957[52:Res:53.1,75956.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.27 75962[53:Spt:75957.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 75964[53:Res:75962.0,61.1] always3(s1) || -> . % 76.04/76.27 75965[53:SSi:75964.0,690.0,73893.0] || -> . % 76.04/76.27 75966[53:Spt:75965.0,75957.0,75962.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.27 75967[53:Spt:75965.0,75957.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 75975[53:Res:75967.0,61.1] always3(s2) || -> . % 76.04/76.27 75976[53:SSi:75975.0,691.0] || -> . % 76.04/76.27 75977[51:Spt:75976.0,74.0,73892.0] || xuntil6(s0)*+ -> . % 76.04/76.27 75978[51:Spt:75976.0,74.1] || -> node4(s0)*. % 76.04/76.27 75979[51:MRR:758.1,75977.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 75981[51:Res:75979.0,61.1] always3(s1) || -> . % 76.04/76.27 75982[51:SSi:75981.0,690.0] || -> . % 76.04/76.27 75983[50:Spt:75982.0,73882.0,73886.0] || trans(s49,s1)*+ -> . % 76.04/76.27 75984[50:Spt:75982.0,73882.1] || -> always3(s0)*. % 76.04/76.27 75986[50:MRR:73884.0,75983.0] || -> node2(s49,s0)*. % 76.04/76.27 75987[50:MRR:73885.1,75983.0] xuntil6(s49) || -> until2p7(s0)*. % 76.04/76.27 75991[50:Res:75986.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s0,c_busy)*. % 76.04/76.27 75992[51:Spt:74.0] || -> xuntil6(s0)*. % 76.04/76.27 75993[51:MRR:176.0,75992.0] || -> until5(s1)*. % 76.04/76.27 75994[51:MRR:74331.0,75993.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy) xuntil6(s1). % 76.04/76.27 75998[52:Spt:75994.2] || -> xuntil6(s1)*. % 76.04/76.27 75999[52:MRR:175.0,75998.0] || -> until5(s2)*. % 76.04/76.27 76000[52:MRR:74324.0,75999.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.27 76002[50:SoR:75991.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s0,c_busy)*. % 76.04/76.27 76004[53:Spt:76000.2] || -> xuntil6(s2)*. % 76.04/76.27 76005[53:MRR:174.0,76004.0] || -> until5(s3)*. % 76.04/76.27 76006[53:MRR:74320.0,76005.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.27 76007[54:Spt:76006.2] || -> xuntil6(s3)*. % 76.04/76.27 76008[54:MRR:173.0,76007.0] || -> until5(s4)*. % 76.04/76.27 76009[54:MRR:74313.0,76008.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.27 76013[55:Spt:76009.2] || -> xuntil6(s4)*. % 76.04/76.27 76014[55:MRR:172.0,76013.0] || -> until5(s5)*. % 76.04/76.27 76015[55:MRR:74312.0,76014.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.27 76016[56:Spt:76015.2] || -> xuntil6(s5)*. % 76.04/76.27 76017[56:MRR:171.0,76016.0] || -> until5(s6)*. % 76.04/76.27 76018[56:MRR:74305.0,76017.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.27 76022[57:Spt:76018.2] || -> xuntil6(s6)*. % 76.04/76.27 76023[57:MRR:170.0,76022.0] || -> until5(s7)*. % 76.04/76.27 76024[57:MRR:74301.0,76023.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.27 76025[58:Spt:76024.2] || -> xuntil6(s7)*. % 76.04/76.27 76026[58:MRR:169.0,76025.0] || -> until5(s8)*. % 76.04/76.27 76027[58:MRR:74300.0,76026.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.27 76031[59:Spt:76027.2] || -> xuntil6(s8)*. % 76.04/76.27 76032[59:MRR:168.0,76031.0] || -> until5(s9)*. % 76.04/76.27 76033[59:MRR:74293.0,76032.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.27 76034[60:Spt:76033.2] || -> xuntil6(s9)*. % 76.04/76.27 76035[60:MRR:167.0,76034.0] || -> until5(s10)*. % 76.04/76.27 76036[60:MRR:74292.0,76035.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.27 76040[61:Spt:76036.2] || -> xuntil6(s10)*. % 76.04/76.27 76041[61:MRR:166.0,76040.0] || -> until5(s11)*. % 76.04/76.27 76042[61:MRR:74291.0,76041.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.27 76043[62:Spt:76042.2] || -> xuntil6(s11)*. % 76.04/76.27 76044[62:MRR:165.0,76043.0] || -> until5(s12)*. % 76.04/76.27 76045[62:MRR:74281.0,76044.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.27 76049[63:Spt:76045.2] || -> xuntil6(s12)*. % 76.04/76.27 76050[63:MRR:164.0,76049.0] || -> until5(s13)*. % 76.04/76.27 76051[63:MRR:74280.0,76050.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.27 76052[64:Spt:76051.2] || -> xuntil6(s13)*. % 76.04/76.27 76053[64:MRR:163.0,76052.0] || -> until5(s14)*. % 76.04/76.27 76054[64:MRR:74276.0,76053.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.27 76058[65:Spt:76054.2] || -> xuntil6(s14)*. % 76.04/76.27 76059[65:MRR:162.0,76058.0] || -> until5(s15)*. % 76.04/76.27 76060[65:MRR:74269.0,76059.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.27 76061[66:Spt:76060.2] || -> xuntil6(s15)*. % 76.04/76.27 76062[66:MRR:161.0,76061.0] || -> until5(s16)*. % 76.04/76.27 76063[66:MRR:74265.0,76062.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.27 76067[67:Spt:76063.2] || -> xuntil6(s16)*. % 76.04/76.27 76068[67:MRR:160.0,76067.0] || -> until5(s17)*. % 76.04/76.27 76069[67:MRR:74264.0,76068.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.27 76070[68:Spt:76069.2] || -> xuntil6(s17)*. % 76.04/76.27 76071[68:MRR:159.0,76070.0] || -> until5(s18)*. % 76.04/76.27 76072[68:MRR:74260.0,76071.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.27 76076[69:Spt:76072.2] || -> xuntil6(s18)*. % 76.04/76.27 76077[69:MRR:158.0,76076.0] || -> until5(s19)*. % 76.04/76.27 76078[69:MRR:74253.0,76077.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.27 76079[70:Spt:76078.2] || -> xuntil6(s19)*. % 76.04/76.27 76080[70:MRR:157.0,76079.0] || -> until5(s20)*. % 76.04/76.27 76081[70:MRR:74252.0,76080.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.27 76085[71:Spt:76081.2] || -> xuntil6(s20)*. % 76.04/76.27 76086[71:MRR:156.0,76085.0] || -> until5(s21)*. % 76.04/76.27 76087[71:MRR:74245.0,76086.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.27 76088[72:Spt:76087.2] || -> xuntil6(s21)*. % 76.04/76.27 76089[72:MRR:155.0,76088.0] || -> until5(s22)*. % 76.04/76.27 76090[72:MRR:74241.0,76089.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.27 76094[73:Spt:76090.2] || -> xuntil6(s22)*. % 76.04/76.27 76095[73:MRR:154.0,76094.0] || -> until5(s23)*. % 76.04/76.27 76096[73:MRR:74240.0,76095.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.27 76097[74:Spt:76096.2] || -> xuntil6(s23)*. % 76.04/76.27 76098[74:MRR:153.0,76097.0] || -> until5(s24)*. % 76.04/76.27 76099[74:MRR:74233.0,76098.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.27 76103[75:Spt:76099.2] || -> xuntil6(s24)*. % 76.04/76.27 76104[75:MRR:152.0,76103.0] || -> until5(s25)*. % 76.04/76.27 76105[75:MRR:74229.0,76104.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.27 76106[76:Spt:76105.2] || -> xuntil6(s25)*. % 76.04/76.27 76107[76:MRR:151.0,76106.0] || -> until5(s26)*. % 76.04/76.27 76108[76:MRR:74225.0,76107.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.27 76112[77:Spt:76108.2] || -> xuntil6(s26)*. % 76.04/76.27 76113[77:MRR:150.0,76112.0] || -> until5(s27)*. % 76.04/76.27 76114[77:MRR:74221.0,76113.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.27 76115[78:Spt:76114.2] || -> xuntil6(s27)*. % 76.04/76.27 76116[78:MRR:149.0,76115.0] || -> until5(s28)*. % 76.04/76.27 76117[78:MRR:74220.0,76116.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.27 76121[79:Spt:76117.2] || -> xuntil6(s28)*. % 76.04/76.27 76122[79:MRR:148.0,76121.0] || -> until5(s29)*. % 76.04/76.27 76123[79:MRR:74213.0,76122.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.27 76124[80:Spt:76123.2] || -> xuntil6(s29)*. % 76.04/76.27 76125[80:MRR:147.0,76124.0] || -> until5(s30)*. % 76.04/76.27 76126[80:MRR:74212.0,76125.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.27 76130[81:Spt:76126.2] || -> xuntil6(s30)*. % 76.04/76.27 76131[81:MRR:146.0,76130.0] || -> until5(s31)*. % 76.04/76.27 76132[81:MRR:74211.0,76131.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.27 76133[82:Spt:76132.2] || -> xuntil6(s31)*. % 76.04/76.27 76134[82:MRR:145.0,76133.0] || -> until5(s32)*. % 76.04/76.27 76135[82:MRR:74207.0,76134.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.27 76139[83:Spt:76135.2] || -> xuntil6(s32)*. % 76.04/76.27 76140[83:MRR:144.0,76139.0] || -> until5(s33)*. % 76.04/76.27 76141[83:MRR:68175.0,76140.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.27 76142[84:Spt:76141.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.27 76144[84:Res:76142.0,61.1] always3(s34) || -> . % 76.04/76.27 76145[84:SSi:76144.0,723.0] || -> . % 76.04/76.27 76146[84:Spt:76145.0,76141.1,76142.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.27 76147[84:Spt:76145.0,76141.0,76141.2] || m_main_v_state(s33,c_ready)*+ -> xuntil6(s33). % 76.04/76.27 76149[84:MRR:819.2,76146.0] node4(s33) || m_main_v_state(s33,c_ready)* -> . % 76.04/76.27 76150[84:Res:53.1,76147.0] || -> m_main_v_state(s33,c_busy)* xuntil6(s33). % 76.04/76.27 76155[85:Spt:76150.1] || -> xuntil6(s33)*. % 76.04/76.27 76156[85:MRR:143.0,76155.0] || -> until5(s34)*. % 76.04/76.27 76157[85:MRR:74335.0,76156.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.27 76159[86:Spt:76157.2] || -> xuntil6(s34)*. % 76.04/76.27 76160[86:MRR:142.0,76159.0] || -> until5(s35)*. % 76.04/76.27 76161[86:MRR:68179.0,76160.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.27 76162[87:Spt:76161.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.27 76164[87:Res:76162.0,61.1] always3(s36) || -> . % 76.04/76.27 76165[87:SSi:76164.0,725.0] || -> . % 76.04/76.27 76166[87:Spt:76165.0,76161.1,76162.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.27 76167[87:Spt:76165.0,76161.0,76161.2] || m_main_v_state(s35,c_ready)*+ -> xuntil6(s35). % 76.04/76.27 76169[87:MRR:813.2,76166.0] node4(s35) || m_main_v_state(s35,c_ready)* -> . % 76.04/76.27 76170[87:Res:53.1,76167.0] || -> m_main_v_state(s35,c_busy)* xuntil6(s35). % 76.04/76.27 76172[88:Spt:76170.1] || -> xuntil6(s35)*. % 76.04/76.27 76173[88:MRR:141.0,76172.0] || -> until5(s36)*. % 76.04/76.27 76174[88:MRR:74342.0,76173.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.27 76179[89:Spt:76174.2] || -> xuntil6(s36)*. % 76.04/76.27 76180[89:MRR:140.0,76179.0] || -> until5(s37)*. % 76.04/76.27 76181[89:MRR:68186.0,76180.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.27 76182[90:Spt:76181.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.27 76184[90:Res:76182.0,61.1] always3(s38) || -> . % 76.04/76.27 76185[90:SSi:76184.0,727.0] || -> . % 76.04/76.27 76186[90:Spt:76185.0,76181.1,76182.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.27 76187[90:Spt:76185.0,76181.0,76181.2] || m_main_v_state(s37,c_ready)*+ -> xuntil6(s37). % 76.04/76.27 76189[90:MRR:807.2,76186.0] node4(s37) || m_main_v_state(s37,c_ready)* -> . % 76.04/76.27 76190[90:Res:53.1,76187.0] || -> m_main_v_state(s37,c_busy)* xuntil6(s37). % 76.04/76.27 76192[91:Spt:76190.1] || -> xuntil6(s37)*. % 76.04/76.27 76193[91:MRR:139.0,76192.0] || -> until5(s38)*. % 76.04/76.27 76194[91:MRR:74343.0,76193.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.27 76202[92:Spt:76194.2] || -> xuntil6(s38)*. % 76.04/76.27 76203[92:MRR:138.0,76202.0] || -> until5(s39)*. % 76.04/76.27 76204[92:MRR:68187.0,76203.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.27 76205[93:Spt:76204.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.27 76207[93:Res:76205.0,61.1] always3(s40) || -> . % 76.04/76.27 76208[93:SSi:76207.0,729.0] || -> . % 76.04/76.27 76209[93:Spt:76208.0,76204.1,76205.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.27 76210[93:Spt:76208.0,76204.0,76204.2] || m_main_v_state(s39,c_ready)*+ -> xuntil6(s39). % 76.04/76.27 76212[93:MRR:801.2,76209.0] node4(s39) || m_main_v_state(s39,c_ready)* -> . % 76.04/76.27 76213[93:Res:53.1,76210.0] || -> m_main_v_state(s39,c_busy)* xuntil6(s39). % 76.04/76.27 76218[94:Spt:76213.1] || -> xuntil6(s39)*. % 76.04/76.27 76219[94:MRR:137.0,76218.0] || -> until5(s40)*. % 76.04/76.27 76220[94:MRR:74347.0,76219.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.27 76222[95:Spt:76220.2] || -> xuntil6(s40)*. % 76.04/76.27 76223[95:MRR:136.0,76222.0] || -> until5(s41)*. % 76.04/76.27 76224[95:MRR:68191.0,76223.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.27 76225[96:Spt:76224.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.27 76227[96:Res:76225.0,61.1] always3(s42) || -> . % 76.04/76.27 76228[96:SSi:76227.0,731.0] || -> . % 76.04/76.27 76229[96:Spt:76228.0,76224.1,76225.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.27 76230[96:Spt:76228.0,76224.0,76224.2] || m_main_v_state(s41,c_ready)*+ -> xuntil6(s41). % 76.04/76.27 76232[96:MRR:795.2,76229.0] node4(s41) || m_main_v_state(s41,c_ready)* -> . % 76.04/76.27 76233[96:Res:53.1,76230.0] || -> m_main_v_state(s41,c_busy)* xuntil6(s41). % 76.04/76.27 76235[97:Spt:76233.1] || -> xuntil6(s41)*. % 76.04/76.27 76236[97:MRR:135.0,76235.0] || -> until5(s42)*. % 76.04/76.27 76237[97:MRR:74351.0,76236.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.27 76242[98:Spt:76237.2] || -> xuntil6(s42)*. % 76.04/76.27 76243[98:MRR:134.0,76242.0] || -> until5(s43)*. % 76.04/76.27 76244[98:MRR:68195.0,76243.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.27 76245[99:Spt:76244.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.27 76247[99:Res:76245.0,61.1] always3(s44) || -> . % 76.04/76.27 76248[99:SSi:76247.0,733.0] || -> . % 76.04/76.27 76249[99:Spt:76248.0,76244.1,76245.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.27 76250[99:Spt:76248.0,76244.0,76244.2] || m_main_v_state(s43,c_ready)*+ -> xuntil6(s43). % 76.04/76.27 76252[99:MRR:789.2,76249.0] node4(s43) || m_main_v_state(s43,c_ready)* -> . % 76.04/76.27 76253[99:Res:53.1,76250.0] || -> m_main_v_state(s43,c_busy)* xuntil6(s43). % 76.04/76.27 76255[100:Spt:76253.1] || -> xuntil6(s43)*. % 76.04/76.27 76256[100:MRR:133.0,76255.0] || -> until5(s44)*. % 76.04/76.27 76257[100:MRR:74355.0,76256.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.27 76265[101:Spt:76257.2] || -> xuntil6(s44)*. % 76.04/76.27 76266[101:MRR:132.0,76265.0] || -> until5(s45)*. % 76.04/76.27 76267[101:MRR:68199.0,76266.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.27 76268[102:Spt:76267.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.27 76270[102:Res:76268.0,61.1] always3(s46) || -> . % 76.04/76.27 76271[102:SSi:76270.0,735.0] || -> . % 76.04/76.27 76272[102:Spt:76271.0,76267.1,76268.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.27 76273[102:Spt:76271.0,76267.0,76267.2] || m_main_v_state(s45,c_ready)*+ -> xuntil6(s45). % 76.04/76.27 76275[102:MRR:783.2,76272.0] node4(s45) || m_main_v_state(s45,c_ready)* -> . % 76.04/76.27 76276[102:Res:53.1,76273.0] || -> m_main_v_state(s45,c_busy)* xuntil6(s45). % 76.04/76.27 76281[103:Spt:76276.1] || -> xuntil6(s45)*. % 76.04/76.27 76282[103:MRR:131.0,76281.0] || -> until5(s46)*. % 76.04/76.27 76283[103:MRR:74362.0,76282.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.27 76285[104:Spt:76283.2] || -> xuntil6(s46)*. % 76.04/76.27 76286[104:MRR:130.0,76285.0] || -> until5(s47)*. % 76.04/76.27 76287[104:MRR:68203.0,76286.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.27 76288[105:Spt:76287.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.27 76290[105:Res:76288.0,61.1] always3(s48) || -> . % 76.04/76.27 76291[105:SSi:76290.0,737.0] || -> . % 76.04/76.27 76292[105:Spt:76291.0,76287.1,76288.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.27 76293[105:Spt:76291.0,76287.0,76287.2] || m_main_v_state(s47,c_ready)*+ -> xuntil6(s47). % 76.04/76.27 76295[105:MRR:777.2,76292.0] node4(s47) || m_main_v_state(s47,c_ready)* -> . % 76.04/76.27 76296[105:Res:53.1,76293.0] || -> m_main_v_state(s47,c_busy)* xuntil6(s47). % 76.04/76.27 76298[106:Spt:76296.1] || -> xuntil6(s47)*. % 76.04/76.27 76299[106:MRR:129.0,76298.0] || -> until5(s48)*. % 76.04/76.27 76300[106:MRR:74363.0,76299.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.27 76305[107:Spt:76300.2] || -> xuntil6(s48)*. % 76.04/76.27 76306[107:MRR:128.0,76305.0] || -> until5(s49)*. % 76.04/76.27 76307[0:SoR:822.0,66.2] until5(s32) || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.27 76311[0:SoR:825.0,66.2] until5(s31) || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.27 76312[0:SoR:828.0,66.2] until5(s30) || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.27 76313[0:SoR:831.0,66.2] until5(s29) || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.27 76320[0:SoR:834.0,66.2] until5(s28) || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.27 76321[0:SoR:837.0,66.2] until5(s27) || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.27 76325[0:SoR:840.0,66.2] until5(s26) || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.27 76329[0:SoR:843.0,66.2] until5(s25) || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.27 76333[0:SoR:846.0,66.2] until5(s24) || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.27 76340[0:SoR:849.0,66.2] until5(s23) || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.27 76341[0:SoR:852.0,66.2] until5(s22) || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.27 76351[0:SoR:855.0,66.2] until5(s21) || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.27 76352[0:SoR:858.0,66.2] until5(s20) || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.27 76353[0:SoR:861.0,66.2] until5(s19) || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.27 76360[0:SoR:864.0,66.2] until5(s18) || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.27 76361[0:SoR:867.0,66.2] until5(s17) || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.27 76365[0:SoR:870.0,66.2] until5(s16) || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.27 76372[0:SoR:873.0,66.2] until5(s15) || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.27 76373[0:SoR:876.0,66.2] until5(s14) || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.27 76380[0:SoR:879.0,66.2] until5(s13) || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.27 76384[0:SoR:882.0,66.2] until5(s12) || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.27 76385[0:SoR:885.0,66.2] until5(s11) || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.27 76389[0:SoR:888.0,66.2] until5(s10) || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.27 76396[0:SoR:891.0,66.2] until5(s9) || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.27 76400[0:SoR:894.0,66.2] until5(s8) || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.27 76401[0:SoR:897.0,66.2] until5(s7) || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.27 76411[0:SoR:900.0,66.2] until5(s6) || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.27 76412[0:SoR:903.0,66.2] until5(s5) || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.27 76413[0:SoR:906.0,66.2] until5(s4) || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.27 76420[0:SoR:909.0,66.2] until5(s3) || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.27 76421[0:SoR:912.0,66.2] until5(s2) || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.27 76429[50:SoR:76002.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s0,c_busy)* xuntil6(s49). % 76.04/76.27 76430[107:SSi:76429.0,50.0,738.0,76306.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s0,c_busy)* xuntil6(s49). % 76.04/76.27 76431[108:Spt:76430.1] || -> m_main_v_state(s0,c_busy)*. % 76.04/76.27 76432[108:Res:76431.0,54.0] || m_main_v_state(s0,c_ready)* -> . % 76.04/76.27 76435[108:MRR:76432.0,55.0] || -> . % 76.04/76.27 76436[108:Spt:76435.0,76430.1,76431.0] || m_main_v_state(s0,c_busy)*+ -> . % 76.04/76.27 76437[108:Spt:76435.0,76430.0,76430.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.27 76439[108:MRR:76002.2,76436.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.27 76440[108:Res:53.1,76437.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.27 76442[109:Spt:76440.1] || -> xuntil6(s49)*. % 76.04/76.27 76443[109:MRR:75987.0,76442.0] || -> until2p7(s0)*. % 76.04/76.27 76444[109:MRR:196.0,76443.0] || -> until2p7(s1)* node4(s0). % 76.04/76.27 76445[110:Spt:76444.0] || -> until2p7(s1)*. % 76.04/76.27 76446[110:MRR:197.0,76445.0] || -> until2p7(s2)* node4(s1). % 76.04/76.27 76447[111:Spt:76446.0] || -> until2p7(s2)*. % 76.04/76.27 76448[111:MRR:198.0,76447.0] || -> until2p7(s3)* node4(s2). % 76.04/76.27 76449[112:Spt:76448.0] || -> until2p7(s3)*. % 76.04/76.27 76450[112:MRR:199.0,76449.0] || -> until2p7(s4)* node4(s3). % 76.04/76.27 76451[113:Spt:76450.0] || -> until2p7(s4)*. % 76.04/76.27 76452[113:MRR:200.0,76451.0] || -> until2p7(s5)* node4(s4). % 76.04/76.27 76453[114:Spt:76452.0] || -> until2p7(s5)*. % 76.04/76.27 76454[114:MRR:201.0,76453.0] || -> until2p7(s6)* node4(s5). % 76.04/76.27 76455[115:Spt:76454.0] || -> until2p7(s6)*. % 76.04/76.27 76456[115:MRR:202.0,76455.0] || -> until2p7(s7)* node4(s6). % 76.04/76.27 76457[116:Spt:76456.0] || -> until2p7(s7)*. % 76.04/76.27 76458[116:MRR:203.0,76457.0] || -> until2p7(s8)* node4(s7). % 76.04/76.27 76459[117:Spt:76458.0] || -> until2p7(s8)*. % 76.04/76.27 76460[117:MRR:204.0,76459.0] || -> until2p7(s9)* node4(s8). % 76.04/76.27 76461[118:Spt:76460.0] || -> until2p7(s9)*. % 76.04/76.27 76462[118:MRR:205.0,76461.0] || -> until2p7(s10)* node4(s9). % 76.04/76.27 76463[119:Spt:76462.0] || -> until2p7(s10)*. % 76.04/76.27 76464[119:MRR:206.0,76463.0] || -> until2p7(s11)* node4(s10). % 76.04/76.27 76465[120:Spt:76464.0] || -> until2p7(s11)*. % 76.04/76.27 76466[120:MRR:207.0,76465.0] || -> until2p7(s12)* node4(s11). % 76.04/76.27 76467[121:Spt:76466.0] || -> until2p7(s12)*. % 76.04/76.27 76468[121:MRR:208.0,76467.0] || -> until2p7(s13)* node4(s12). % 76.04/76.27 76469[122:Spt:76468.0] || -> until2p7(s13)*. % 76.04/76.27 76470[122:MRR:209.0,76469.0] || -> until2p7(s14)* node4(s13). % 76.04/76.27 76471[123:Spt:76470.0] || -> until2p7(s14)*. % 76.04/76.27 76472[123:MRR:210.0,76471.0] || -> until2p7(s15)* node4(s14). % 76.04/76.27 76473[124:Spt:76472.0] || -> until2p7(s15)*. % 76.04/76.27 76474[124:MRR:211.0,76473.0] || -> until2p7(s16)* node4(s15). % 76.04/76.27 76475[125:Spt:76474.0] || -> until2p7(s16)*. % 76.04/76.27 76476[125:MRR:212.0,76475.0] || -> until2p7(s17)* node4(s16). % 76.04/76.27 76477[126:Spt:76476.0] || -> until2p7(s17)*. % 76.04/76.27 76478[126:MRR:213.0,76477.0] || -> until2p7(s18)* node4(s17). % 76.04/76.27 76479[127:Spt:76478.0] || -> until2p7(s18)*. % 76.04/76.27 76480[127:MRR:214.0,76479.0] || -> until2p7(s19)* node4(s18). % 76.04/76.27 76481[128:Spt:76480.0] || -> until2p7(s19)*. % 76.04/76.27 76482[128:MRR:215.0,76481.0] || -> until2p7(s20)* node4(s19). % 76.04/76.27 76483[129:Spt:76482.0] || -> until2p7(s20)*. % 76.04/76.27 76484[129:MRR:216.0,76483.0] || -> until2p7(s21)* node4(s20). % 76.04/76.27 76485[130:Spt:76484.0] || -> until2p7(s21)*. % 76.04/76.27 76486[130:MRR:217.0,76485.0] || -> until2p7(s22)* node4(s21). % 76.04/76.27 76487[131:Spt:76486.0] || -> until2p7(s22)*. % 76.04/76.27 76488[131:MRR:218.0,76487.0] || -> until2p7(s23)* node4(s22). % 76.04/76.27 76489[132:Spt:76488.0] || -> until2p7(s23)*. % 76.04/76.27 76490[132:MRR:219.0,76489.0] || -> until2p7(s24)* node4(s23). % 76.04/76.27 76491[133:Spt:76490.0] || -> until2p7(s24)*. % 76.04/76.27 76492[133:MRR:220.0,76491.0] || -> until2p7(s25)* node4(s24). % 76.04/76.27 76493[134:Spt:76492.0] || -> until2p7(s25)*. % 76.04/76.27 76494[134:MRR:221.0,76493.0] || -> until2p7(s26)* node4(s25). % 76.04/76.27 76495[135:Spt:76494.0] || -> until2p7(s26)*. % 76.04/76.27 76496[135:MRR:222.0,76495.0] || -> until2p7(s27)* node4(s26). % 76.04/76.27 76497[136:Spt:76496.0] || -> until2p7(s27)*. % 76.04/76.27 76498[136:MRR:223.0,76497.0] || -> until2p7(s28)* node4(s27). % 76.04/76.27 76499[137:Spt:76498.0] || -> until2p7(s28)*. % 76.04/76.27 76500[137:MRR:224.0,76499.0] || -> until2p7(s29)* node4(s28). % 76.04/76.27 76501[138:Spt:76500.0] || -> until2p7(s29)*. % 76.04/76.27 76502[138:MRR:225.0,76501.0] || -> until2p7(s30)* node4(s29). % 76.04/76.27 76503[139:Spt:76502.0] || -> until2p7(s30)*. % 76.04/76.27 76504[139:MRR:226.0,76503.0] || -> until2p7(s31)* node4(s30). % 76.04/76.27 76505[140:Spt:76504.0] || -> until2p7(s31)*. % 76.04/76.27 76506[140:MRR:227.0,76505.0] || -> until2p7(s32)* node4(s31). % 76.04/76.27 76507[141:Spt:76506.0] || -> until2p7(s32)*. % 76.04/76.27 76508[141:MRR:228.0,76507.0] || -> until2p7(s33)* node4(s32). % 76.04/76.27 76509[142:Spt:76508.0] || -> until2p7(s33)*. % 76.04/76.27 76510[142:MRR:229.0,76509.0] || -> until2p7(s34)* node4(s33). % 76.04/76.27 76511[143:Spt:76510.0] || -> until2p7(s34)*. % 76.04/76.27 76512[143:MRR:230.0,76511.0] || -> until2p7(s35)* node4(s34). % 76.04/76.27 76513[144:Spt:76512.0] || -> until2p7(s35)*. % 76.04/76.27 76514[144:MRR:231.0,76513.0] || -> until2p7(s36)* node4(s35). % 76.04/76.27 76515[145:Spt:76514.0] || -> until2p7(s36)*. % 76.04/76.27 76516[145:MRR:232.0,76515.0] || -> until2p7(s37)* node4(s36). % 76.04/76.27 76517[146:Spt:76516.0] || -> until2p7(s37)*. % 76.04/76.27 76518[146:MRR:235.0,76517.0] || -> until2p7(s38)* node4(s37). % 76.04/76.27 76519[147:Spt:76518.0] || -> until2p7(s38)*. % 76.04/76.27 76520[147:MRR:236.0,76519.0] || -> until2p7(s39)* node4(s38). % 76.04/76.27 76521[148:Spt:76520.0] || -> until2p7(s39)*. % 76.04/76.27 76522[148:MRR:237.0,76521.0] || -> until2p7(s40)* node4(s39). % 76.04/76.27 76523[149:Spt:76522.0] || -> until2p7(s40)*. % 76.04/76.27 76524[149:MRR:238.0,76523.0] || -> until2p7(s41)* node4(s40). % 76.04/76.27 76525[150:Spt:76524.0] || -> until2p7(s41)*. % 76.04/76.27 76526[150:MRR:239.0,76525.0] || -> until2p7(s42)* node4(s41). % 76.04/76.27 76527[151:Spt:76526.0] || -> until2p7(s42)*. % 76.04/76.27 76528[151:MRR:240.0,76527.0] || -> until2p7(s43)* node4(s42). % 76.04/76.27 76529[152:Spt:76528.0] || -> until2p7(s43)*. % 76.04/76.27 76530[152:MRR:241.0,76529.0] || -> until2p7(s44)* node4(s43). % 76.04/76.27 76531[153:Spt:76530.0] || -> until2p7(s44)*. % 76.04/76.27 76532[153:MRR:539.0,76531.0] || -> until2p7(s45)* node4(s44). % 76.04/76.27 76533[154:Spt:76532.0] || -> until2p7(s45)*. % 76.04/76.27 76534[154:MRR:544.0,76533.0] || -> until2p7(s46)* node4(s45). % 76.04/76.27 76535[155:Spt:76534.0] || -> until2p7(s46)*. % 76.04/76.27 76536[155:MRR:549.0,76535.0] || -> until2p7(s47)* node4(s46). % 76.04/76.27 76537[156:Spt:76536.0] || -> until2p7(s47)*. % 76.04/76.27 76538[156:MRR:554.0,76537.0] || -> until2p7(s48)* node4(s47). % 76.04/76.27 76539[157:Spt:76538.0] || -> until2p7(s48)*. % 76.04/76.27 76540[157:MRR:559.0,76539.0] || -> until2p7(s49)* node4(s48). % 76.04/76.27 76541[158:Spt:76540.0] || -> until2p7(s49)*. % 76.04/76.27 76542[158:MRR:194.0,76541.0] || -> node4(s49)*. % 76.04/76.27 76543[158:MRR:76439.0,76542.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.27 76544[158:Res:53.1,76543.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 76547[158:Res:76544.0,61.1] always3(s49) || -> . % 76.04/76.27 76548[158:SSi:76547.0,50.0,738.0,76306.0,76442.0,76541.0,76542.0] || -> . % 76.04/76.27 76549[158:Spt:76548.0,76540.0,76541.0] || until2p7(s49)*+ -> . % 76.04/76.27 76550[158:Spt:76548.0,76540.1] || -> node4(s48)*. % 76.04/76.27 76552[158:MRR:774.0,76550.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.27 76558[158:Res:53.1,76552.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.27 76560[158:MRR:76558.0,76292.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 76562[158:Res:76560.0,61.1] always3(s49) || -> . % 76.04/76.27 76563[158:SSi:76562.0,50.0,738.0,76306.0,76442.0] || -> . % 76.04/76.27 76564[157:Spt:76563.0,76538.0,76539.0] || until2p7(s48)*+ -> . % 76.04/76.27 76565[157:Spt:76563.0,76538.1] || -> node4(s47)*. % 76.04/76.27 76566[157:MRR:76295.0,76565.0] || m_main_v_state(s47,c_ready)*+ -> . % 76.04/76.27 76569[157:Res:53.1,76566.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 76572[157:Res:76569.0,61.1] always3(s47) || -> . % 76.04/76.27 76573[157:SSi:76572.0,736.0,76286.0,76298.0,76537.0,76565.0] || -> . % 76.04/76.27 76574[156:Spt:76573.0,76536.0,76537.0] || until2p7(s47)*+ -> . % 76.04/76.27 76575[156:Spt:76573.0,76536.1] || -> node4(s46)*. % 76.04/76.27 76577[156:MRR:780.0,76575.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.27 76589[156:Res:53.1,76577.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.27 76591[156:MRR:76589.0,76272.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 76596[156:Res:76591.0,61.1] always3(s47) || -> . % 76.04/76.27 76597[156:SSi:76596.0,736.0,76286.0,76298.0] || -> . % 76.04/76.27 76598[155:Spt:76597.0,76534.0,76535.0] || until2p7(s46)*+ -> . % 76.04/76.27 76599[155:Spt:76597.0,76534.1] || -> node4(s45)*. % 76.04/76.27 76600[155:MRR:76275.0,76599.0] || m_main_v_state(s45,c_ready)*+ -> . % 76.04/76.27 76603[155:Res:53.1,76600.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 76607[155:Res:76603.0,61.1] always3(s45) || -> . % 76.04/76.27 76608[155:SSi:76607.0,734.0,76266.0,76281.0,76533.0,76599.0] || -> . % 76.04/76.27 76609[154:Spt:76608.0,76532.0,76533.0] || until2p7(s45)*+ -> . % 76.04/76.27 76610[154:Spt:76608.0,76532.1] || -> node4(s44)*. % 76.04/76.27 76612[154:MRR:786.0,76610.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.27 76623[154:Res:53.1,76612.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.27 76625[154:MRR:76623.0,76249.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 76627[154:Res:76625.0,61.1] always3(s45) || -> . % 76.04/76.27 76628[154:SSi:76627.0,734.0,76266.0,76281.0] || -> . % 76.04/76.27 76629[153:Spt:76628.0,76530.0,76531.0] || until2p7(s44)*+ -> . % 76.04/76.27 76630[153:Spt:76628.0,76530.1] || -> node4(s43)*. % 76.04/76.27 76631[153:MRR:76252.0,76630.0] || m_main_v_state(s43,c_ready)*+ -> . % 76.04/76.27 76635[153:Res:53.1,76631.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 76638[153:Res:76635.0,61.1] always3(s43) || -> . % 76.04/76.27 76639[153:SSi:76638.0,732.0,76243.0,76255.0,76529.0,76630.0] || -> . % 76.04/76.27 76640[152:Spt:76639.0,76528.0,76529.0] || until2p7(s43)*+ -> . % 76.04/76.27 76641[152:Spt:76639.0,76528.1] || -> node4(s42)*. % 76.04/76.27 76643[152:MRR:792.0,76641.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.27 76654[152:Res:53.1,76643.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.27 76656[152:MRR:76654.0,76229.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 76658[152:Res:76656.0,61.1] always3(s43) || -> . % 76.04/76.27 76659[152:SSi:76658.0,732.0,76243.0,76255.0] || -> . % 76.04/76.27 76660[151:Spt:76659.0,76526.0,76527.0] || until2p7(s42)*+ -> . % 76.04/76.27 76661[151:Spt:76659.0,76526.1] || -> node4(s41)*. % 76.04/76.27 76662[151:MRR:76232.0,76661.0] || m_main_v_state(s41,c_ready)*+ -> . % 76.04/76.27 76665[151:Res:53.1,76662.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 76668[151:Res:76665.0,61.1] always3(s41) || -> . % 76.04/76.27 76669[151:SSi:76668.0,730.0,76223.0,76235.0,76525.0,76661.0] || -> . % 76.04/76.27 76670[150:Spt:76669.0,76524.0,76525.0] || until2p7(s41)*+ -> . % 76.04/76.27 76671[150:Spt:76669.0,76524.1] || -> node4(s40)*. % 76.04/76.27 76673[150:MRR:798.0,76671.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.27 76685[150:Res:53.1,76673.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.27 76687[150:MRR:76685.0,76209.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 76689[150:Res:76687.0,61.1] always3(s41) || -> . % 76.04/76.27 76690[150:SSi:76689.0,730.0,76223.0,76235.0] || -> . % 76.04/76.27 76691[149:Spt:76690.0,76522.0,76523.0] || until2p7(s40)*+ -> . % 76.04/76.27 76692[149:Spt:76690.0,76522.1] || -> node4(s39)*. % 76.04/76.27 76693[149:MRR:76212.0,76692.0] || m_main_v_state(s39,c_ready)*+ -> . % 76.04/76.27 76696[149:Res:53.1,76693.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 76699[149:Res:76696.0,61.1] always3(s39) || -> . % 76.04/76.27 76700[149:SSi:76699.0,728.0,76203.0,76218.0,76521.0,76692.0] || -> . % 76.04/76.27 76701[148:Spt:76700.0,76520.0,76521.0] || until2p7(s39)*+ -> . % 76.04/76.27 76702[148:Spt:76700.0,76520.1] || -> node4(s38)*. % 76.04/76.27 76704[148:MRR:804.0,76702.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.27 76716[148:Res:53.1,76704.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.27 76718[148:MRR:76716.0,76186.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 76723[148:Res:76718.0,61.1] always3(s39) || -> . % 76.04/76.27 76724[148:SSi:76723.0,728.0,76203.0,76218.0] || -> . % 76.04/76.27 76725[147:Spt:76724.0,76518.0,76519.0] || until2p7(s38)*+ -> . % 76.04/76.27 76726[147:Spt:76724.0,76518.1] || -> node4(s37)*. % 76.04/76.27 76727[147:MRR:76189.0,76726.0] || m_main_v_state(s37,c_ready)*+ -> . % 76.04/76.27 76730[147:Res:53.1,76727.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 76734[147:Res:76730.0,61.1] always3(s37) || -> . % 76.04/76.27 76735[147:SSi:76734.0,726.0,76180.0,76192.0,76517.0,76726.0] || -> . % 76.04/76.27 76736[146:Spt:76735.0,76516.0,76517.0] || until2p7(s37)*+ -> . % 76.04/76.27 76737[146:Spt:76735.0,76516.1] || -> node4(s36)*. % 76.04/76.27 76739[146:MRR:810.0,76737.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.27 76750[146:Res:53.1,76739.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.27 76752[146:MRR:76750.0,76166.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 76754[146:Res:76752.0,61.1] always3(s37) || -> . % 76.04/76.27 76755[146:SSi:76754.0,726.0,76180.0,76192.0] || -> . % 76.04/76.27 76756[145:Spt:76755.0,76514.0,76515.0] || until2p7(s36)*+ -> . % 76.04/76.27 76757[145:Spt:76755.0,76514.1] || -> node4(s35)*. % 76.04/76.27 76758[145:MRR:76169.0,76757.0] || m_main_v_state(s35,c_ready)*+ -> . % 76.04/76.27 76762[145:Res:53.1,76758.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 76765[145:Res:76762.0,61.1] always3(s35) || -> . % 76.04/76.27 76766[145:SSi:76765.0,724.0,76160.0,76172.0,76513.0,76757.0] || -> . % 76.04/76.27 76767[144:Spt:76766.0,76512.0,76513.0] || until2p7(s35)*+ -> . % 76.04/76.27 76768[144:Spt:76766.0,76512.1] || -> node4(s34)*. % 76.04/76.27 76770[144:MRR:816.0,76768.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.27 76781[144:Res:53.1,76770.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.27 76783[144:MRR:76781.0,76146.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 76785[144:Res:76783.0,61.1] always3(s35) || -> . % 76.04/76.27 76786[144:SSi:76785.0,724.0,76160.0,76172.0] || -> . % 76.04/76.27 76787[143:Spt:76786.0,76510.0,76511.0] || until2p7(s34)*+ -> . % 76.04/76.27 76788[143:Spt:76786.0,76510.1] || -> node4(s33)*. % 76.04/76.27 76789[143:MRR:76149.0,76788.0] || m_main_v_state(s33,c_ready)*+ -> . % 76.04/76.27 76792[143:Res:53.1,76789.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 76795[143:Res:76792.0,61.1] always3(s33) || -> . % 76.04/76.27 76796[143:SSi:76795.0,722.0,76140.0,76155.0,76509.0,76788.0] || -> . % 76.04/76.27 76797[142:Spt:76796.0,76508.0,76509.0] || until2p7(s33)*+ -> . % 76.04/76.27 76798[142:Spt:76796.0,76508.1] || -> node4(s32)*. % 76.04/76.27 76800[142:MRR:822.0,76798.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.27 76812[142:Res:53.1,76800.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.27 76814[143:Spt:76812.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 76816[143:Res:76814.0,61.1] always3(s32) || -> . % 76.04/76.27 76817[143:SSi:76816.0,721.0,76134.0,76139.0,76507.0,76798.0] || -> . % 76.04/76.27 76818[143:Spt:76817.0,76812.0,76814.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.27 76819[143:Spt:76817.0,76812.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 76823[143:Res:76819.0,61.1] always3(s33) || -> . % 76.04/76.27 76824[143:SSi:76823.0,722.0,76140.0,76155.0] || -> . % 76.04/76.27 76825[141:Spt:76824.0,76506.0,76507.0] || until2p7(s32)*+ -> . % 76.04/76.27 76826[141:Spt:76824.0,76506.1] || -> node4(s31)*. % 76.04/76.27 76828[141:MRR:825.0,76826.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.27 76835[141:Res:53.1,76828.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.27 76837[142:Spt:76835.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 76839[142:Res:76837.0,61.1] always3(s31) || -> . % 76.04/76.27 76840[142:SSi:76839.0,720.0,76131.0,76133.0,76505.0,76826.0] || -> . % 76.04/76.27 76841[142:Spt:76840.0,76835.0,76837.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.27 76842[142:Spt:76840.0,76835.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 76846[142:Res:76842.0,61.1] always3(s32) || -> . % 76.04/76.27 76847[142:SSi:76846.0,721.0,76134.0,76139.0] || -> . % 76.04/76.27 76848[140:Spt:76847.0,76504.0,76505.0] || until2p7(s31)*+ -> . % 76.04/76.27 76849[140:Spt:76847.0,76504.1] || -> node4(s30)*. % 76.04/76.27 76851[140:MRR:828.0,76849.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.27 76854[140:Res:53.1,76851.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.27 76856[141:Spt:76854.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 76858[141:Res:76856.0,61.1] always3(s30) || -> . % 76.04/76.27 76859[141:SSi:76858.0,719.0,76125.0,76130.0,76503.0,76849.0] || -> . % 76.04/76.27 76860[141:Spt:76859.0,76854.0,76856.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.27 76861[141:Spt:76859.0,76854.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 76865[141:Res:76861.0,61.1] always3(s31) || -> . % 76.04/76.27 76866[141:SSi:76865.0,720.0,76131.0,76133.0] || -> . % 76.04/76.27 76867[139:Spt:76866.0,76502.0,76503.0] || until2p7(s30)*+ -> . % 76.04/76.27 76868[139:Spt:76866.0,76502.1] || -> node4(s29)*. % 76.04/76.27 76870[139:MRR:831.0,76868.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.27 76873[139:Res:53.1,76870.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.27 76875[140:Spt:76873.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 76877[140:Res:76875.0,61.1] always3(s29) || -> . % 76.04/76.27 76878[140:SSi:76877.0,718.0,76122.0,76124.0,76501.0,76868.0] || -> . % 76.04/76.27 76879[140:Spt:76878.0,76873.0,76875.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.27 76880[140:Spt:76878.0,76873.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 76884[140:Res:76880.0,61.1] always3(s30) || -> . % 76.04/76.27 76885[140:SSi:76884.0,719.0,76125.0,76130.0] || -> . % 76.04/76.27 76886[138:Spt:76885.0,76500.0,76501.0] || until2p7(s29)*+ -> . % 76.04/76.27 76887[138:Spt:76885.0,76500.1] || -> node4(s28)*. % 76.04/76.27 76889[138:MRR:834.0,76887.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.27 76892[138:Res:53.1,76889.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.27 76897[139:Spt:76892.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 76899[139:Res:76897.0,61.1] always3(s28) || -> . % 76.04/76.27 76900[139:SSi:76899.0,717.0,76116.0,76121.0,76499.0,76887.0] || -> . % 76.04/76.27 76901[139:Spt:76900.0,76892.0,76897.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.27 76902[139:Spt:76900.0,76892.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 76906[139:Res:76902.0,61.1] always3(s29) || -> . % 76.04/76.27 76907[139:SSi:76906.0,718.0,76122.0,76124.0] || -> . % 76.04/76.27 76908[137:Spt:76907.0,76498.0,76499.0] || until2p7(s28)*+ -> . % 76.04/76.27 76909[137:Spt:76907.0,76498.1] || -> node4(s27)*. % 76.04/76.27 76911[137:MRR:837.0,76909.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.27 76914[137:Res:53.1,76911.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.27 76916[138:Spt:76914.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 76918[138:Res:76916.0,61.1] always3(s27) || -> . % 76.04/76.27 76919[138:SSi:76918.0,716.0,76113.0,76115.0,76497.0,76909.0] || -> . % 76.04/76.27 76920[138:Spt:76919.0,76914.0,76916.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.27 76921[138:Spt:76919.0,76914.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 76925[138:Res:76921.0,61.1] always3(s28) || -> . % 76.04/76.27 76926[138:SSi:76925.0,717.0,76116.0,76121.0] || -> . % 76.04/76.27 76927[136:Spt:76926.0,76496.0,76497.0] || until2p7(s27)*+ -> . % 76.04/76.27 76928[136:Spt:76926.0,76496.1] || -> node4(s26)*. % 76.04/76.27 76930[136:MRR:840.0,76928.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.27 76933[136:Res:53.1,76930.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.27 76935[137:Spt:76933.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 76937[137:Res:76935.0,61.1] always3(s26) || -> . % 76.04/76.27 76938[137:SSi:76937.0,715.0,76107.0,76112.0,76495.0,76928.0] || -> . % 76.04/76.27 76939[137:Spt:76938.0,76933.0,76935.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.27 76940[137:Spt:76938.0,76933.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 76944[137:Res:76940.0,61.1] always3(s27) || -> . % 76.04/76.27 76945[137:SSi:76944.0,716.0,76113.0,76115.0] || -> . % 76.04/76.27 76946[135:Spt:76945.0,76494.0,76495.0] || until2p7(s26)*+ -> . % 76.04/76.27 76947[135:Spt:76945.0,76494.1] || -> node4(s25)*. % 76.04/76.27 76949[135:MRR:843.0,76947.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.27 76952[135:Res:53.1,76949.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.27 76954[136:Spt:76952.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 76956[136:Res:76954.0,61.1] always3(s25) || -> . % 76.04/76.27 76957[136:SSi:76956.0,714.0,76104.0,76106.0,76493.0,76947.0] || -> . % 76.04/76.27 76958[136:Spt:76957.0,76952.0,76954.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.27 76959[136:Spt:76957.0,76952.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 76963[136:Res:76959.0,61.1] always3(s26) || -> . % 76.04/76.27 76964[136:SSi:76963.0,715.0,76107.0,76112.0] || -> . % 76.04/76.27 76965[134:Spt:76964.0,76492.0,76493.0] || until2p7(s25)*+ -> . % 76.04/76.27 76966[134:Spt:76964.0,76492.1] || -> node4(s24)*. % 76.04/76.27 76968[134:MRR:846.0,76966.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.27 76971[134:Res:53.1,76968.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.27 76976[135:Spt:76971.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 76978[135:Res:76976.0,61.1] always3(s24) || -> . % 76.04/76.27 76979[135:SSi:76978.0,713.0,76098.0,76103.0,76491.0,76966.0] || -> . % 76.04/76.27 76980[135:Spt:76979.0,76971.0,76976.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.27 76981[135:Spt:76979.0,76971.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 76985[135:Res:76981.0,61.1] always3(s25) || -> . % 76.04/76.27 76986[135:SSi:76985.0,714.0,76104.0,76106.0] || -> . % 76.04/76.27 76987[133:Spt:76986.0,76490.0,76491.0] || until2p7(s24)*+ -> . % 76.04/76.27 76988[133:Spt:76986.0,76490.1] || -> node4(s23)*. % 76.04/76.27 76990[133:MRR:849.0,76988.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.27 76993[133:Res:53.1,76990.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.27 76995[134:Spt:76993.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 76997[134:Res:76995.0,61.1] always3(s23) || -> . % 76.04/76.27 76998[134:SSi:76997.0,712.0,76095.0,76097.0,76489.0,76988.0] || -> . % 76.04/76.27 76999[134:Spt:76998.0,76993.0,76995.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.27 77000[134:Spt:76998.0,76993.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 77004[134:Res:77000.0,61.1] always3(s24) || -> . % 76.04/76.27 77005[134:SSi:77004.0,713.0,76098.0,76103.0] || -> . % 76.04/76.27 77006[132:Spt:77005.0,76488.0,76489.0] || until2p7(s23)*+ -> . % 76.04/76.27 77007[132:Spt:77005.0,76488.1] || -> node4(s22)*. % 76.04/76.27 77009[132:MRR:852.0,77007.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.27 77012[132:Res:53.1,77009.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.27 77014[133:Spt:77012.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 77016[133:Res:77014.0,61.1] always3(s22) || -> . % 76.04/76.27 77017[133:SSi:77016.0,711.0,76089.0,76094.0,76487.0,77007.0] || -> . % 76.04/76.27 77018[133:Spt:77017.0,77012.0,77014.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.27 77019[133:Spt:77017.0,77012.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 77023[133:Res:77019.0,61.1] always3(s23) || -> . % 76.04/76.27 77024[133:SSi:77023.0,712.0,76095.0,76097.0] || -> . % 76.04/76.27 77025[131:Spt:77024.0,76486.0,76487.0] || until2p7(s22)*+ -> . % 76.04/76.27 77026[131:Spt:77024.0,76486.1] || -> node4(s21)*. % 76.04/76.27 77028[131:MRR:855.0,77026.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.27 77031[131:Res:53.1,77028.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.27 77033[132:Spt:77031.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 77035[132:Res:77033.0,61.1] always3(s21) || -> . % 76.04/76.27 77036[132:SSi:77035.0,710.0,76086.0,76088.0,76485.0,77026.0] || -> . % 76.04/76.27 77037[132:Spt:77036.0,77031.0,77033.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.27 77038[132:Spt:77036.0,77031.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 77042[132:Res:77038.0,61.1] always3(s22) || -> . % 76.04/76.27 77043[132:SSi:77042.0,711.0,76089.0,76094.0] || -> . % 76.04/76.27 77044[130:Spt:77043.0,76484.0,76485.0] || until2p7(s21)*+ -> . % 76.04/76.27 77045[130:Spt:77043.0,76484.1] || -> node4(s20)*. % 76.04/76.27 77047[130:MRR:858.0,77045.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.27 77050[130:Res:53.1,77047.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.27 77055[131:Spt:77050.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 77057[131:Res:77055.0,61.1] always3(s20) || -> . % 76.04/76.27 77058[131:SSi:77057.0,709.0,76080.0,76085.0,76483.0,77045.0] || -> . % 76.04/76.27 77059[131:Spt:77058.0,77050.0,77055.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.27 77060[131:Spt:77058.0,77050.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 77064[131:Res:77060.0,61.1] always3(s21) || -> . % 76.04/76.27 77065[131:SSi:77064.0,710.0,76086.0,76088.0] || -> . % 76.04/76.27 77066[129:Spt:77065.0,76482.0,76483.0] || until2p7(s20)*+ -> . % 76.04/76.27 77067[129:Spt:77065.0,76482.1] || -> node4(s19)*. % 76.04/76.27 77069[129:MRR:861.0,77067.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.27 77072[129:Res:53.1,77069.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.27 77074[130:Spt:77072.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 77076[130:Res:77074.0,61.1] always3(s19) || -> . % 76.04/76.27 77077[130:SSi:77076.0,708.0,76077.0,76079.0,76481.0,77067.0] || -> . % 76.04/76.27 77078[130:Spt:77077.0,77072.0,77074.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.27 77079[130:Spt:77077.0,77072.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 77083[130:Res:77079.0,61.1] always3(s20) || -> . % 76.04/76.27 77084[130:SSi:77083.0,709.0,76080.0,76085.0] || -> . % 76.04/76.27 77085[128:Spt:77084.0,76480.0,76481.0] || until2p7(s19)*+ -> . % 76.04/76.27 77086[128:Spt:77084.0,76480.1] || -> node4(s18)*. % 76.04/76.27 77088[128:MRR:864.0,77086.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.27 77091[128:Res:53.1,77088.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.27 77093[129:Spt:77091.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 77095[129:Res:77093.0,61.1] always3(s18) || -> . % 76.04/76.27 77096[129:SSi:77095.0,707.0,76071.0,76076.0,76479.0,77086.0] || -> . % 76.04/76.27 77097[129:Spt:77096.0,77091.0,77093.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.27 77098[129:Spt:77096.0,77091.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 77102[129:Res:77098.0,61.1] always3(s19) || -> . % 76.04/76.27 77103[129:SSi:77102.0,708.0,76077.0,76079.0] || -> . % 76.04/76.27 77104[127:Spt:77103.0,76478.0,76479.0] || until2p7(s18)*+ -> . % 76.04/76.27 77105[127:Spt:77103.0,76478.1] || -> node4(s17)*. % 76.04/76.27 77107[127:MRR:867.0,77105.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.27 77110[127:Res:53.1,77107.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.27 77112[128:Spt:77110.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 77114[128:Res:77112.0,61.1] always3(s17) || -> . % 76.04/76.27 77115[128:SSi:77114.0,706.0,76068.0,76070.0,76477.0,77105.0] || -> . % 76.04/76.27 77116[128:Spt:77115.0,77110.0,77112.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.27 77117[128:Spt:77115.0,77110.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 77121[128:Res:77117.0,61.1] always3(s18) || -> . % 76.04/76.27 77122[128:SSi:77121.0,707.0,76071.0,76076.0] || -> . % 76.04/76.27 77123[126:Spt:77122.0,76476.0,76477.0] || until2p7(s17)*+ -> . % 76.04/76.27 77124[126:Spt:77122.0,76476.1] || -> node4(s16)*. % 76.04/76.27 77126[126:MRR:870.0,77124.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.27 77129[126:Res:53.1,77126.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.27 77134[127:Spt:77129.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 77136[127:Res:77134.0,61.1] always3(s16) || -> . % 76.04/76.27 77137[127:SSi:77136.0,705.0,76062.0,76067.0,76475.0,77124.0] || -> . % 76.04/76.27 77138[127:Spt:77137.0,77129.0,77134.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.27 77139[127:Spt:77137.0,77129.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 77143[127:Res:77139.0,61.1] always3(s17) || -> . % 76.04/76.27 77144[127:SSi:77143.0,706.0,76068.0,76070.0] || -> . % 76.04/76.27 77145[125:Spt:77144.0,76474.0,76475.0] || until2p7(s16)*+ -> . % 76.04/76.27 77146[125:Spt:77144.0,76474.1] || -> node4(s15)*. % 76.04/76.27 77148[125:MRR:873.0,77146.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.27 77151[125:Res:53.1,77148.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.27 77153[126:Spt:77151.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 77155[126:Res:77153.0,61.1] always3(s15) || -> . % 76.04/76.27 77156[126:SSi:77155.0,704.0,76059.0,76061.0,76473.0,77146.0] || -> . % 76.04/76.27 77157[126:Spt:77156.0,77151.0,77153.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.27 77158[126:Spt:77156.0,77151.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 77162[126:Res:77158.0,61.1] always3(s16) || -> . % 76.04/76.27 77163[126:SSi:77162.0,705.0,76062.0,76067.0] || -> . % 76.04/76.27 77164[124:Spt:77163.0,76472.0,76473.0] || until2p7(s15)*+ -> . % 76.04/76.27 77165[124:Spt:77163.0,76472.1] || -> node4(s14)*. % 76.04/76.27 77167[124:MRR:876.0,77165.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.27 77170[124:Res:53.1,77167.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.27 77172[125:Spt:77170.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 77174[125:Res:77172.0,61.1] always3(s14) || -> . % 76.04/76.27 77175[125:SSi:77174.0,703.0,76053.0,76058.0,76471.0,77165.0] || -> . % 76.04/76.27 77176[125:Spt:77175.0,77170.0,77172.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.27 77177[125:Spt:77175.0,77170.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 77181[125:Res:77177.0,61.1] always3(s15) || -> . % 76.04/76.27 77182[125:SSi:77181.0,704.0,76059.0,76061.0] || -> . % 76.04/76.27 77183[123:Spt:77182.0,76470.0,76471.0] || until2p7(s14)*+ -> . % 76.04/76.27 77184[123:Spt:77182.0,76470.1] || -> node4(s13)*. % 76.04/76.27 77186[123:MRR:879.0,77184.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.27 77189[123:Res:53.1,77186.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.27 77191[124:Spt:77189.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 77193[124:Res:77191.0,61.1] always3(s13) || -> . % 76.04/76.27 77194[124:SSi:77193.0,702.0,76050.0,76052.0,76469.0,77184.0] || -> . % 76.04/76.27 77195[124:Spt:77194.0,77189.0,77191.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.27 77196[124:Spt:77194.0,77189.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 77200[124:Res:77196.0,61.1] always3(s14) || -> . % 76.04/76.27 77201[124:SSi:77200.0,703.0,76053.0,76058.0] || -> . % 76.04/76.27 77202[122:Spt:77201.0,76468.0,76469.0] || until2p7(s13)*+ -> . % 76.04/76.27 77203[122:Spt:77201.0,76468.1] || -> node4(s12)*. % 76.04/76.27 77205[122:MRR:882.0,77203.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.27 77208[122:Res:53.1,77205.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.27 77213[123:Spt:77208.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 77215[123:Res:77213.0,61.1] always3(s12) || -> . % 76.04/76.27 77216[123:SSi:77215.0,701.0,76044.0,76049.0,76467.0,77203.0] || -> . % 76.04/76.27 77217[123:Spt:77216.0,77208.0,77213.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.27 77218[123:Spt:77216.0,77208.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 77222[123:Res:77218.0,61.1] always3(s13) || -> . % 76.04/76.27 77223[123:SSi:77222.0,702.0,76050.0,76052.0] || -> . % 76.04/76.27 77224[121:Spt:77223.0,76466.0,76467.0] || until2p7(s12)*+ -> . % 76.04/76.27 77225[121:Spt:77223.0,76466.1] || -> node4(s11)*. % 76.04/76.27 77227[121:MRR:885.0,77225.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.27 77230[121:Res:53.1,77227.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.27 77232[122:Spt:77230.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 77234[122:Res:77232.0,61.1] always3(s11) || -> . % 76.04/76.27 77235[122:SSi:77234.0,700.0,76041.0,76043.0,76465.0,77225.0] || -> . % 76.04/76.27 77236[122:Spt:77235.0,77230.0,77232.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.27 77237[122:Spt:77235.0,77230.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 77241[122:Res:77237.0,61.1] always3(s12) || -> . % 76.04/76.27 77242[122:SSi:77241.0,701.0,76044.0,76049.0] || -> . % 76.04/76.27 77243[120:Spt:77242.0,76464.0,76465.0] || until2p7(s11)*+ -> . % 76.04/76.27 77244[120:Spt:77242.0,76464.1] || -> node4(s10)*. % 76.04/76.27 77246[120:MRR:888.0,77244.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.27 77249[120:Res:53.1,77246.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.27 77251[121:Spt:77249.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 77253[121:Res:77251.0,61.1] always3(s10) || -> . % 76.04/76.27 77254[121:SSi:77253.0,699.0,76035.0,76040.0,76463.0,77244.0] || -> . % 76.04/76.27 77255[121:Spt:77254.0,77249.0,77251.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.27 77256[121:Spt:77254.0,77249.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 77260[121:Res:77256.0,61.1] always3(s11) || -> . % 76.04/76.27 77261[121:SSi:77260.0,700.0,76041.0,76043.0] || -> . % 76.04/76.27 77262[119:Spt:77261.0,76462.0,76463.0] || until2p7(s10)*+ -> . % 76.04/76.27 77263[119:Spt:77261.0,76462.1] || -> node4(s9)*. % 76.04/76.27 77265[119:MRR:891.0,77263.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.27 77268[119:Res:53.1,77265.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.27 77270[120:Spt:77268.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 77272[120:Res:77270.0,61.1] always3(s9) || -> . % 76.04/76.27 77273[120:SSi:77272.0,698.0,76032.0,76034.0,76461.0,77263.0] || -> . % 76.04/76.27 77274[120:Spt:77273.0,77268.0,77270.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.27 77275[120:Spt:77273.0,77268.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 77279[120:Res:77275.0,61.1] always3(s10) || -> . % 76.04/76.27 77280[120:SSi:77279.0,699.0,76035.0,76040.0] || -> . % 76.04/76.27 77281[118:Spt:77280.0,76460.0,76461.0] || until2p7(s9)*+ -> . % 76.04/76.27 77282[118:Spt:77280.0,76460.1] || -> node4(s8)*. % 76.04/76.27 77284[118:MRR:894.0,77282.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.27 77287[118:Res:53.1,77284.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.27 77292[119:Spt:77287.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 77294[119:Res:77292.0,61.1] always3(s8) || -> . % 76.04/76.27 77295[119:SSi:77294.0,697.0,76026.0,76031.0,76459.0,77282.0] || -> . % 76.04/76.27 77296[119:Spt:77295.0,77287.0,77292.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.27 77297[119:Spt:77295.0,77287.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 77301[119:Res:77297.0,61.1] always3(s9) || -> . % 76.04/76.27 77302[119:SSi:77301.0,698.0,76032.0,76034.0] || -> . % 76.04/76.27 77303[117:Spt:77302.0,76458.0,76459.0] || until2p7(s8)*+ -> . % 76.04/76.27 77304[117:Spt:77302.0,76458.1] || -> node4(s7)*. % 76.04/76.27 77306[117:MRR:897.0,77304.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.27 77309[117:Res:53.1,77306.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.27 77311[118:Spt:77309.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 77313[118:Res:77311.0,61.1] always3(s7) || -> . % 76.04/76.27 77314[118:SSi:77313.0,696.0,76023.0,76025.0,76457.0,77304.0] || -> . % 76.04/76.27 77315[118:Spt:77314.0,77309.0,77311.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.27 77316[118:Spt:77314.0,77309.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 77320[118:Res:77316.0,61.1] always3(s8) || -> . % 76.04/76.27 77321[118:SSi:77320.0,697.0,76026.0,76031.0] || -> . % 76.04/76.27 77322[116:Spt:77321.0,76456.0,76457.0] || until2p7(s7)*+ -> . % 76.04/76.27 77323[116:Spt:77321.0,76456.1] || -> node4(s6)*. % 76.04/76.27 77325[116:MRR:900.0,77323.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.27 77328[116:Res:53.1,77325.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.27 77330[117:Spt:77328.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 77332[117:Res:77330.0,61.1] always3(s6) || -> . % 76.04/76.27 77333[117:SSi:77332.0,695.0,76017.0,76022.0,76455.0,77323.0] || -> . % 76.04/76.27 77334[117:Spt:77333.0,77328.0,77330.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.27 77335[117:Spt:77333.0,77328.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 77339[117:Res:77335.0,61.1] always3(s7) || -> . % 76.04/76.27 77340[117:SSi:77339.0,696.0,76023.0,76025.0] || -> . % 76.04/76.27 77341[115:Spt:77340.0,76454.0,76455.0] || until2p7(s6)*+ -> . % 76.04/76.27 77342[115:Spt:77340.0,76454.1] || -> node4(s5)*. % 76.04/76.27 77344[115:MRR:903.0,77342.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.27 77347[115:Res:53.1,77344.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.27 77349[116:Spt:77347.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 77351[116:Res:77349.0,61.1] always3(s5) || -> . % 76.04/76.27 77352[116:SSi:77351.0,694.0,76014.0,76016.0,76453.0,77342.0] || -> . % 76.04/76.27 77353[116:Spt:77352.0,77347.0,77349.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.27 77354[116:Spt:77352.0,77347.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 77358[116:Res:77354.0,61.1] always3(s6) || -> . % 76.04/76.27 77359[116:SSi:77358.0,695.0,76017.0,76022.0] || -> . % 76.04/76.27 77360[114:Spt:77359.0,76452.0,76453.0] || until2p7(s5)*+ -> . % 76.04/76.27 77361[114:Spt:77359.0,76452.1] || -> node4(s4)*. % 76.04/76.27 77363[114:MRR:906.0,77361.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.27 77366[114:Res:53.1,77363.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.27 77371[115:Spt:77366.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 77373[115:Res:77371.0,61.1] always3(s4) || -> . % 76.04/76.27 77374[115:SSi:77373.0,693.0,76008.0,76013.0,76451.0,77361.0] || -> . % 76.04/76.27 77375[115:Spt:77374.0,77366.0,77371.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.27 77376[115:Spt:77374.0,77366.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 77380[115:Res:77376.0,61.1] always3(s5) || -> . % 76.04/76.27 77381[115:SSi:77380.0,694.0,76014.0,76016.0] || -> . % 76.04/76.27 77382[113:Spt:77381.0,76450.0,76451.0] || until2p7(s4)*+ -> . % 76.04/76.27 77383[113:Spt:77381.0,76450.1] || -> node4(s3)*. % 76.04/76.27 77385[113:MRR:909.0,77383.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.27 77388[113:Res:53.1,77385.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.27 77390[114:Spt:77388.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 77392[114:Res:77390.0,61.1] always3(s3) || -> . % 76.04/76.27 77393[114:SSi:77392.0,692.0,76005.0,76007.0,76449.0,77383.0] || -> . % 76.04/76.27 77394[114:Spt:77393.0,77388.0,77390.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.27 77395[114:Spt:77393.0,77388.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 77399[114:Res:77395.0,61.1] always3(s4) || -> . % 76.04/76.27 77400[114:SSi:77399.0,693.0,76008.0,76013.0] || -> . % 76.04/76.27 77401[112:Spt:77400.0,76448.0,76449.0] || until2p7(s3)*+ -> . % 76.04/76.27 77402[112:Spt:77400.0,76448.1] || -> node4(s2)*. % 76.04/76.27 77404[112:MRR:912.0,77402.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.27 77407[112:Res:53.1,77404.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.27 77409[113:Spt:77407.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 77411[113:Res:77409.0,61.1] always3(s2) || -> . % 76.04/76.27 77412[113:SSi:77411.0,691.0,75999.0,76004.0,76447.0,77402.0] || -> . % 76.04/76.27 77413[113:Spt:77412.0,77407.0,77409.0] || m_main_v_state(s2,c_busy)* -> . % 76.04/76.27 77414[113:Spt:77412.0,77407.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 77418[113:Res:77414.0,61.1] always3(s3) || -> . % 76.04/76.27 77419[113:SSi:77418.0,692.0,76005.0,76007.0] || -> . % 76.04/76.27 77420[111:Spt:77419.0,76446.0,76447.0] || until2p7(s2)*+ -> . % 76.04/76.27 77421[111:Spt:77419.0,76446.1] || -> node4(s1)*. % 76.04/76.27 77423[111:MRR:915.0,77421.0] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.27 77426[111:Res:53.1,77423.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.27 77428[112:Spt:77426.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 77430[112:Res:77428.0,61.1] always3(s1) || -> . % 76.04/76.27 77431[112:SSi:77430.0,690.0,75993.0,75998.0,76445.0,77421.0] || -> . % 76.04/76.27 77432[112:Spt:77431.0,77426.0,77428.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.27 77433[112:Spt:77431.0,77426.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 77437[112:Res:77433.0,61.1] always3(s2) || -> . % 76.04/76.27 77438[112:SSi:77437.0,691.0,75999.0,76004.0] || -> . % 76.04/76.27 77439[110:Spt:77438.0,76444.0,76445.0] || until2p7(s1)*+ -> . % 76.04/76.27 77440[110:Spt:77438.0,76444.1] || -> node4(s0)*. % 76.04/76.27 77442[110:MRR:754.0,77440.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 77445[110:Res:77442.0,61.1] always3(s1) || -> . % 76.04/76.27 77446[110:SSi:77445.0,690.0,75993.0,75998.0] || -> . % 76.04/76.27 77447[109:Spt:77446.0,76440.1,76442.0] || xuntil6(s49)* -> . % 76.04/76.27 77448[109:Spt:77446.0,76440.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 77451[109:Res:77448.0,61.1] always3(s49) || -> . % 76.04/76.27 77452[109:SSi:77451.0,50.0,738.0,76306.0] || -> . % 76.04/76.27 77453[107:Spt:77452.0,76300.2,76305.0] || xuntil6(s48)*+ -> . % 76.04/76.27 77454[107:Spt:77452.0,76300.0,76300.1] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy). % 76.04/76.27 77455[107:Res:53.1,77454.0] || -> m_main_v_state(s48,c_busy)* m_main_v_state(s49,c_busy). % 76.04/76.27 77457[107:MRR:77455.0,76292.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 77459[107:Res:77457.0,61.1] always3(s49) || -> . % 76.04/76.27 77460[107:SSi:77459.0,50.0,738.0] || -> . % 76.04/76.27 77461[106:Spt:77460.0,76296.1,76298.0] || xuntil6(s47)* -> . % 76.04/76.27 77462[106:Spt:77460.0,76296.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 77465[106:Res:77462.0,61.1] always3(s47) || -> . % 76.04/76.27 77466[106:SSi:77465.0,736.0,76286.0] || -> . % 76.04/76.27 77467[104:Spt:77466.0,76283.2,76285.0] || xuntil6(s46)*+ -> . % 76.04/76.27 77468[104:Spt:77466.0,76283.0,76283.1] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.27 77469[104:Res:53.1,77468.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.27 77471[104:MRR:77469.0,76272.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 77473[104:Res:77471.0,61.1] always3(s47) || -> . % 76.04/76.27 77474[104:SSi:77473.0,736.0] || -> . % 76.04/76.27 77475[103:Spt:77474.0,76276.1,76281.0] || xuntil6(s45)* -> . % 76.04/76.27 77476[103:Spt:77474.0,76276.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 77479[103:Res:77476.0,61.1] always3(s45) || -> . % 76.04/76.27 77480[103:SSi:77479.0,734.0,76266.0] || -> . % 76.04/76.27 77481[101:Spt:77480.0,76257.2,76265.0] || xuntil6(s44)*+ -> . % 76.04/76.27 77482[101:Spt:77480.0,76257.0,76257.1] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.27 77483[101:Res:53.1,77482.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.27 77485[101:MRR:77483.0,76249.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.27 77487[101:Res:77485.0,61.1] always3(s45) || -> . % 76.04/76.27 77488[101:SSi:77487.0,734.0] || -> . % 76.04/76.27 77489[100:Spt:77488.0,76253.1,76255.0] || xuntil6(s43)* -> . % 76.04/76.27 77490[100:Spt:77488.0,76253.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 77493[100:Res:77490.0,61.1] always3(s43) || -> . % 76.04/76.27 77494[100:SSi:77493.0,732.0,76243.0] || -> . % 76.04/76.27 77495[98:Spt:77494.0,76237.2,76242.0] || xuntil6(s42)*+ -> . % 76.04/76.27 77496[98:Spt:77494.0,76237.0,76237.1] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.27 77497[98:Res:53.1,77496.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.27 77499[98:MRR:77497.0,76229.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.27 77502[98:Res:77499.0,61.1] always3(s43) || -> . % 76.04/76.27 77503[98:SSi:77502.0,732.0] || -> . % 76.04/76.27 77504[97:Spt:77503.0,76233.1,76235.0] || xuntil6(s41)* -> . % 76.04/76.27 77505[97:Spt:77503.0,76233.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 77508[97:Res:77505.0,61.1] always3(s41) || -> . % 76.04/76.27 77509[97:SSi:77508.0,730.0,76223.0] || -> . % 76.04/76.27 77510[95:Spt:77509.0,76220.2,76222.0] || xuntil6(s40)*+ -> . % 76.04/76.27 77511[95:Spt:77509.0,76220.0,76220.1] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.27 77512[95:Res:53.1,77511.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.27 77514[95:MRR:77512.0,76209.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.27 77516[95:Res:77514.0,61.1] always3(s41) || -> . % 76.04/76.27 77517[95:SSi:77516.0,730.0] || -> . % 76.04/76.27 77518[94:Spt:77517.0,76213.1,76218.0] || xuntil6(s39)* -> . % 76.04/76.27 77519[94:Spt:77517.0,76213.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 77522[94:Res:77519.0,61.1] always3(s39) || -> . % 76.04/76.27 77523[94:SSi:77522.0,728.0,76203.0] || -> . % 76.04/76.27 77524[92:Spt:77523.0,76194.2,76202.0] || xuntil6(s38)*+ -> . % 76.04/76.27 77525[92:Spt:77523.0,76194.0,76194.1] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.27 77526[92:Res:53.1,77525.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.27 77528[92:MRR:77526.0,76186.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.27 77531[92:Res:77528.0,61.1] always3(s39) || -> . % 76.04/76.27 77532[92:SSi:77531.0,728.0] || -> . % 76.04/76.27 77533[91:Spt:77532.0,76190.1,76192.0] || xuntil6(s37)* -> . % 76.04/76.27 77534[91:Spt:77532.0,76190.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 77537[91:Res:77534.0,61.1] always3(s37) || -> . % 76.04/76.27 77538[91:SSi:77537.0,726.0,76180.0] || -> . % 76.04/76.27 77539[89:Spt:77538.0,76174.2,76179.0] || xuntil6(s36)*+ -> . % 76.04/76.27 77540[89:Spt:77538.0,76174.0,76174.1] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.27 77541[89:Res:53.1,77540.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.27 77543[89:MRR:77541.0,76166.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.27 77545[89:Res:77543.0,61.1] always3(s37) || -> . % 76.04/76.27 77546[89:SSi:77545.0,726.0] || -> . % 76.04/76.27 77547[88:Spt:77546.0,76170.1,76172.0] || xuntil6(s35)* -> . % 76.04/76.27 77548[88:Spt:77546.0,76170.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 77551[88:Res:77548.0,61.1] always3(s35) || -> . % 76.04/76.27 77552[88:SSi:77551.0,724.0,76160.0] || -> . % 76.04/76.27 77553[86:Spt:77552.0,76157.2,76159.0] || xuntil6(s34)*+ -> . % 76.04/76.27 77554[86:Spt:77552.0,76157.0,76157.1] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.27 77555[86:Res:53.1,77554.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.27 77557[86:MRR:77555.0,76146.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.27 77559[86:Res:77557.0,61.1] always3(s35) || -> . % 76.04/76.27 77560[86:SSi:77559.0,724.0] || -> . % 76.04/76.27 77561[85:Spt:77560.0,76150.1,76155.0] || xuntil6(s33)* -> . % 76.04/76.27 77562[85:Spt:77560.0,76150.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 77565[85:Res:77562.0,61.1] always3(s33) || -> . % 76.04/76.27 77566[85:SSi:77565.0,722.0,76140.0] || -> . % 76.04/76.27 77567[83:Spt:77566.0,76135.2,76139.0] || xuntil6(s32)*+ -> . % 76.04/76.27 77568[83:Spt:77566.0,76135.0,76135.1] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.27 77569[83:Res:53.1,77568.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.27 77574[84:Spt:77569.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.27 77576[84:Res:77574.0,61.1] always3(s33) || -> . % 76.04/76.27 77577[84:SSi:77576.0,722.0] || -> . % 76.04/76.27 77578[84:Spt:77577.0,77569.1,77574.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.27 77579[84:Spt:77577.0,77569.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 77582[84:Res:77579.0,61.1] always3(s32) || -> . % 76.04/76.27 77583[84:SSi:77582.0,721.0,76134.0] || -> . % 76.04/76.27 77584[82:Spt:77583.0,76132.2,76133.0] || xuntil6(s31)*+ -> . % 76.04/76.27 77585[82:Spt:77583.0,76132.0,76132.1] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.27 77586[82:Res:53.1,77585.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.27 77588[83:Spt:77586.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.27 77590[83:Res:77588.0,61.1] always3(s32) || -> . % 76.04/76.27 77591[83:SSi:77590.0,721.0] || -> . % 76.04/76.27 77592[83:Spt:77591.0,77586.1,77588.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.27 77593[83:Spt:77591.0,77586.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 77596[83:Res:77593.0,61.1] always3(s31) || -> . % 76.04/76.27 77597[83:SSi:77596.0,720.0,76131.0] || -> . % 76.04/76.27 77598[81:Spt:77597.0,76126.2,76130.0] || xuntil6(s30)*+ -> . % 76.04/76.27 77599[81:Spt:77597.0,76126.0,76126.1] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.27 77600[81:Res:53.1,77599.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.27 77602[82:Spt:77600.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.27 77604[82:Res:77602.0,61.1] always3(s31) || -> . % 76.04/76.27 77605[82:SSi:77604.0,720.0] || -> . % 76.04/76.27 77606[82:Spt:77605.0,77600.1,77602.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.27 77607[82:Spt:77605.0,77600.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 77610[82:Res:77607.0,61.1] always3(s30) || -> . % 76.04/76.27 77611[82:SSi:77610.0,719.0,76125.0] || -> . % 76.04/76.27 77612[80:Spt:77611.0,76123.2,76124.0] || xuntil6(s29)*+ -> . % 76.04/76.27 77613[80:Spt:77611.0,76123.0,76123.1] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.27 77614[80:Res:53.1,77613.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.27 77616[81:Spt:77614.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.27 77618[81:Res:77616.0,61.1] always3(s30) || -> . % 76.04/76.27 77619[81:SSi:77618.0,719.0] || -> . % 76.04/76.27 77620[81:Spt:77619.0,77614.1,77616.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.27 77621[81:Spt:77619.0,77614.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 77624[81:Res:77621.0,61.1] always3(s29) || -> . % 76.04/76.27 77625[81:SSi:77624.0,718.0,76122.0] || -> . % 76.04/76.27 77626[79:Spt:77625.0,76117.2,76121.0] || xuntil6(s28)*+ -> . % 76.04/76.27 77627[79:Spt:77625.0,76117.0,76117.1] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.27 77628[79:Res:53.1,77627.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.27 77630[80:Spt:77628.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.27 77632[80:Res:77630.0,61.1] always3(s29) || -> . % 76.04/76.27 77633[80:SSi:77632.0,718.0] || -> . % 76.04/76.27 77634[80:Spt:77633.0,77628.1,77630.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.27 77635[80:Spt:77633.0,77628.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 77638[80:Res:77635.0,61.1] always3(s28) || -> . % 76.04/76.27 77639[80:SSi:77638.0,717.0,76116.0] || -> . % 76.04/76.27 77640[78:Spt:77639.0,76114.2,76115.0] || xuntil6(s27)*+ -> . % 76.04/76.27 77641[78:Spt:77639.0,76114.0,76114.1] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.27 77642[78:Res:53.1,77641.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.27 77644[79:Spt:77642.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.27 77646[79:Res:77644.0,61.1] always3(s28) || -> . % 76.04/76.27 77647[79:SSi:77646.0,717.0] || -> . % 76.04/76.27 77648[79:Spt:77647.0,77642.1,77644.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.27 77649[79:Spt:77647.0,77642.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 77652[79:Res:77649.0,61.1] always3(s27) || -> . % 76.04/76.27 77653[79:SSi:77652.0,716.0,76113.0] || -> . % 76.04/76.27 77654[77:Spt:77653.0,76108.2,76112.0] || xuntil6(s26)*+ -> . % 76.04/76.27 77655[77:Spt:77653.0,76108.0,76108.1] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.27 77656[77:Res:53.1,77655.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.27 77658[78:Spt:77656.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.27 77660[78:Res:77658.0,61.1] always3(s27) || -> . % 76.04/76.27 77661[78:SSi:77660.0,716.0] || -> . % 76.04/76.27 77662[78:Spt:77661.0,77656.1,77658.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.27 77663[78:Spt:77661.0,77656.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 77666[78:Res:77663.0,61.1] always3(s26) || -> . % 76.04/76.27 77667[78:SSi:77666.0,715.0,76107.0] || -> . % 76.04/76.27 77668[76:Spt:77667.0,76105.2,76106.0] || xuntil6(s25)*+ -> . % 76.04/76.27 77669[76:Spt:77667.0,76105.0,76105.1] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.27 77670[76:Res:53.1,77669.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.27 77675[77:Spt:77670.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.27 77677[77:Res:77675.0,61.1] always3(s26) || -> . % 76.04/76.27 77678[77:SSi:77677.0,715.0] || -> . % 76.04/76.27 77679[77:Spt:77678.0,77670.1,77675.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.27 77680[77:Spt:77678.0,77670.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 77683[77:Res:77680.0,61.1] always3(s25) || -> . % 76.04/76.27 77684[77:SSi:77683.0,714.0,76104.0] || -> . % 76.04/76.27 77685[75:Spt:77684.0,76099.2,76103.0] || xuntil6(s24)*+ -> . % 76.04/76.27 77686[75:Spt:77684.0,76099.0,76099.1] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.27 77687[75:Res:53.1,77686.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.27 77689[76:Spt:77687.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.27 77691[76:Res:77689.0,61.1] always3(s25) || -> . % 76.04/76.27 77692[76:SSi:77691.0,714.0] || -> . % 76.04/76.27 77693[76:Spt:77692.0,77687.1,77689.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.27 77694[76:Spt:77692.0,77687.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 77697[76:Res:77694.0,61.1] always3(s24) || -> . % 76.04/76.27 77698[76:SSi:77697.0,713.0,76098.0] || -> . % 76.04/76.27 77699[74:Spt:77698.0,76096.2,76097.0] || xuntil6(s23)*+ -> . % 76.04/76.27 77700[74:Spt:77698.0,76096.0,76096.1] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.27 77701[74:Res:53.1,77700.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.27 77703[75:Spt:77701.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.27 77705[75:Res:77703.0,61.1] always3(s24) || -> . % 76.04/76.27 77706[75:SSi:77705.0,713.0] || -> . % 76.04/76.27 77707[75:Spt:77706.0,77701.1,77703.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.27 77708[75:Spt:77706.0,77701.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 77711[75:Res:77708.0,61.1] always3(s23) || -> . % 76.04/76.27 77712[75:SSi:77711.0,712.0,76095.0] || -> . % 76.04/76.27 77713[73:Spt:77712.0,76090.2,76094.0] || xuntil6(s22)*+ -> . % 76.04/76.27 77714[73:Spt:77712.0,76090.0,76090.1] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.27 77715[73:Res:53.1,77714.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.27 77720[74:Spt:77715.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 77722[74:Res:77720.0,61.1] always3(s22) || -> . % 76.04/76.27 77723[74:SSi:77722.0,711.0,76089.0] || -> . % 76.04/76.27 77724[74:Spt:77723.0,77715.0,77720.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.27 77725[74:Spt:77723.0,77715.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.27 77729[74:Res:77725.0,61.1] always3(s23) || -> . % 76.04/76.27 77730[74:SSi:77729.0,712.0] || -> . % 76.04/76.27 77731[72:Spt:77730.0,76087.2,76088.0] || xuntil6(s21)*+ -> . % 76.04/76.27 77732[72:Spt:77730.0,76087.0,76087.1] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.27 77733[72:Res:53.1,77732.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.27 77735[73:Spt:77733.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.27 77737[73:Res:77735.0,61.1] always3(s22) || -> . % 76.04/76.27 77738[73:SSi:77737.0,711.0] || -> . % 76.04/76.27 77739[73:Spt:77738.0,77733.1,77735.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.27 77740[73:Spt:77738.0,77733.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 77743[73:Res:77740.0,61.1] always3(s21) || -> . % 76.04/76.27 77744[73:SSi:77743.0,710.0,76086.0] || -> . % 76.04/76.27 77745[71:Spt:77744.0,76081.2,76085.0] || xuntil6(s20)*+ -> . % 76.04/76.27 77746[71:Spt:77744.0,76081.0,76081.1] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.27 77747[71:Res:53.1,77746.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.27 77749[72:Spt:77747.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.27 77751[72:Res:77749.0,61.1] always3(s21) || -> . % 76.04/76.27 77752[72:SSi:77751.0,710.0] || -> . % 76.04/76.27 77753[72:Spt:77752.0,77747.1,77749.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.27 77754[72:Spt:77752.0,77747.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 77757[72:Res:77754.0,61.1] always3(s20) || -> . % 76.04/76.27 77758[72:SSi:77757.0,709.0,76080.0] || -> . % 76.04/76.27 77759[70:Spt:77758.0,76078.2,76079.0] || xuntil6(s19)*+ -> . % 76.04/76.27 77760[70:Spt:77758.0,76078.0,76078.1] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.27 77761[70:Res:53.1,77760.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.27 77766[71:Spt:77761.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 77768[71:Res:77766.0,61.1] always3(s19) || -> . % 76.04/76.27 77769[71:SSi:77768.0,708.0,76077.0] || -> . % 76.04/76.27 77770[71:Spt:77769.0,77761.0,77766.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.27 77771[71:Spt:77769.0,77761.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.27 77775[71:Res:77771.0,61.1] always3(s20) || -> . % 76.04/76.27 77776[71:SSi:77775.0,709.0] || -> . % 76.04/76.27 77777[69:Spt:77776.0,76072.2,76076.0] || xuntil6(s18)*+ -> . % 76.04/76.27 77778[69:Spt:77776.0,76072.0,76072.1] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.27 77779[69:Res:53.1,77778.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.27 77781[70:Spt:77779.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.27 77783[70:Res:77781.0,61.1] always3(s19) || -> . % 76.04/76.27 77784[70:SSi:77783.0,708.0] || -> . % 76.04/76.27 77785[70:Spt:77784.0,77779.1,77781.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.27 77786[70:Spt:77784.0,77779.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 77789[70:Res:77786.0,61.1] always3(s18) || -> . % 76.04/76.27 77790[70:SSi:77789.0,707.0,76071.0] || -> . % 76.04/76.27 77791[68:Spt:77790.0,76069.2,76070.0] || xuntil6(s17)*+ -> . % 76.04/76.27 77792[68:Spt:77790.0,76069.0,76069.1] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.27 77793[68:Res:53.1,77792.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.27 77795[69:Spt:77793.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.27 77797[69:Res:77795.0,61.1] always3(s18) || -> . % 76.04/76.27 77798[69:SSi:77797.0,707.0] || -> . % 76.04/76.27 77799[69:Spt:77798.0,77793.1,77795.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.27 77800[69:Spt:77798.0,77793.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 77803[69:Res:77800.0,61.1] always3(s17) || -> . % 76.04/76.27 77804[69:SSi:77803.0,706.0,76068.0] || -> . % 76.04/76.27 77805[67:Spt:77804.0,76063.2,76067.0] || xuntil6(s16)*+ -> . % 76.04/76.27 77806[67:Spt:77804.0,76063.0,76063.1] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.27 77807[67:Res:53.1,77806.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.27 77812[68:Spt:77807.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 77814[68:Res:77812.0,61.1] always3(s16) || -> . % 76.04/76.27 77815[68:SSi:77814.0,705.0,76062.0] || -> . % 76.04/76.27 77816[68:Spt:77815.0,77807.0,77812.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.27 77817[68:Spt:77815.0,77807.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.27 77821[68:Res:77817.0,61.1] always3(s17) || -> . % 76.04/76.27 77822[68:SSi:77821.0,706.0] || -> . % 76.04/76.27 77823[66:Spt:77822.0,76060.2,76061.0] || xuntil6(s15)*+ -> . % 76.04/76.27 77824[66:Spt:77822.0,76060.0,76060.1] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.27 77825[66:Res:53.1,77824.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.27 77827[67:Spt:77825.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.27 77829[67:Res:77827.0,61.1] always3(s16) || -> . % 76.04/76.27 77830[67:SSi:77829.0,705.0] || -> . % 76.04/76.27 77831[67:Spt:77830.0,77825.1,77827.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.27 77832[67:Spt:77830.0,77825.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 77835[67:Res:77832.0,61.1] always3(s15) || -> . % 76.04/76.27 77836[67:SSi:77835.0,704.0,76059.0] || -> . % 76.04/76.27 77837[65:Spt:77836.0,76054.2,76058.0] || xuntil6(s14)*+ -> . % 76.04/76.27 77838[65:Spt:77836.0,76054.0,76054.1] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.27 77839[65:Res:53.1,77838.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.27 77841[66:Spt:77839.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.27 77843[66:Res:77841.0,61.1] always3(s15) || -> . % 76.04/76.27 77844[66:SSi:77843.0,704.0] || -> . % 76.04/76.27 77845[66:Spt:77844.0,77839.1,77841.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.27 77846[66:Spt:77844.0,77839.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 77849[66:Res:77846.0,61.1] always3(s14) || -> . % 76.04/76.27 77850[66:SSi:77849.0,703.0,76053.0] || -> . % 76.04/76.27 77851[64:Spt:77850.0,76051.2,76052.0] || xuntil6(s13)*+ -> . % 76.04/76.27 77852[64:Spt:77850.0,76051.0,76051.1] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.27 77853[64:Res:53.1,77852.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.27 77858[65:Spt:77853.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 77860[65:Res:77858.0,61.1] always3(s13) || -> . % 76.04/76.27 77861[65:SSi:77860.0,702.0,76050.0] || -> . % 76.04/76.27 77862[65:Spt:77861.0,77853.0,77858.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.27 77863[65:Spt:77861.0,77853.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.27 77867[65:Res:77863.0,61.1] always3(s14) || -> . % 76.04/76.27 77868[65:SSi:77867.0,703.0] || -> . % 76.04/76.27 77869[63:Spt:77868.0,76045.2,76049.0] || xuntil6(s12)*+ -> . % 76.04/76.27 77870[63:Spt:77868.0,76045.0,76045.1] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.27 77871[63:Res:53.1,77870.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.27 77873[64:Spt:77871.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.27 77875[64:Res:77873.0,61.1] always3(s13) || -> . % 76.04/76.27 77876[64:SSi:77875.0,702.0] || -> . % 76.04/76.27 77877[64:Spt:77876.0,77871.1,77873.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.27 77878[64:Spt:77876.0,77871.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 77881[64:Res:77878.0,61.1] always3(s12) || -> . % 76.04/76.27 77882[64:SSi:77881.0,701.0,76044.0] || -> . % 76.04/76.27 77883[62:Spt:77882.0,76042.2,76043.0] || xuntil6(s11)*+ -> . % 76.04/76.27 77884[62:Spt:77882.0,76042.0,76042.1] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.27 77885[62:Res:53.1,77884.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.27 77887[63:Spt:77885.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.27 77889[63:Res:77887.0,61.1] always3(s12) || -> . % 76.04/76.27 77890[63:SSi:77889.0,701.0] || -> . % 76.04/76.27 77891[63:Spt:77890.0,77885.1,77887.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.27 77892[63:Spt:77890.0,77885.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 77895[63:Res:77892.0,61.1] always3(s11) || -> . % 76.04/76.27 77896[63:SSi:77895.0,700.0,76041.0] || -> . % 76.04/76.27 77897[61:Spt:77896.0,76036.2,76040.0] || xuntil6(s10)*+ -> . % 76.04/76.27 77898[61:Spt:77896.0,76036.0,76036.1] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.27 77899[61:Res:53.1,77898.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.27 77904[62:Spt:77899.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 77906[62:Res:77904.0,61.1] always3(s10) || -> . % 76.04/76.27 77907[62:SSi:77906.0,699.0,76035.0] || -> . % 76.04/76.27 77908[62:Spt:77907.0,77899.0,77904.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.27 77909[62:Spt:77907.0,77899.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.27 77913[62:Res:77909.0,61.1] always3(s11) || -> . % 76.04/76.27 77914[62:SSi:77913.0,700.0] || -> . % 76.04/76.27 77915[60:Spt:77914.0,76033.2,76034.0] || xuntil6(s9)*+ -> . % 76.04/76.27 77916[60:Spt:77914.0,76033.0,76033.1] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.27 77917[60:Res:53.1,77916.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.27 77919[61:Spt:77917.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.27 77921[61:Res:77919.0,61.1] always3(s10) || -> . % 76.04/76.27 77922[61:SSi:77921.0,699.0] || -> . % 76.04/76.27 77923[61:Spt:77922.0,77917.1,77919.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.27 77924[61:Spt:77922.0,77917.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 77927[61:Res:77924.0,61.1] always3(s9) || -> . % 76.04/76.27 77928[61:SSi:77927.0,698.0,76032.0] || -> . % 76.04/76.27 77929[59:Spt:77928.0,76027.2,76031.0] || xuntil6(s8)*+ -> . % 76.04/76.27 77930[59:Spt:77928.0,76027.0,76027.1] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.27 77931[59:Res:53.1,77930.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.27 77933[60:Spt:77931.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.27 77935[60:Res:77933.0,61.1] always3(s9) || -> . % 76.04/76.27 77936[60:SSi:77935.0,698.0] || -> . % 76.04/76.27 77937[60:Spt:77936.0,77931.1,77933.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.27 77938[60:Spt:77936.0,77931.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 77941[60:Res:77938.0,61.1] always3(s8) || -> . % 76.04/76.27 77942[60:SSi:77941.0,697.0,76026.0] || -> . % 76.04/76.27 77943[58:Spt:77942.0,76024.2,76025.0] || xuntil6(s7)*+ -> . % 76.04/76.27 77944[58:Spt:77942.0,76024.0,76024.1] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.27 77945[58:Res:53.1,77944.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.27 77950[59:Spt:77945.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 77952[59:Res:77950.0,61.1] always3(s7) || -> . % 76.04/76.27 77953[59:SSi:77952.0,696.0,76023.0] || -> . % 76.04/76.27 77954[59:Spt:77953.0,77945.0,77950.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.27 77955[59:Spt:77953.0,77945.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.27 77959[59:Res:77955.0,61.1] always3(s8) || -> . % 76.04/76.27 77960[59:SSi:77959.0,697.0] || -> . % 76.04/76.27 77961[57:Spt:77960.0,76018.2,76022.0] || xuntil6(s6)*+ -> . % 76.04/76.27 77962[57:Spt:77960.0,76018.0,76018.1] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.27 77963[57:Res:53.1,77962.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.27 77965[58:Spt:77963.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.27 77967[58:Res:77965.0,61.1] always3(s7) || -> . % 76.04/76.27 77968[58:SSi:77967.0,696.0] || -> . % 76.04/76.27 77969[58:Spt:77968.0,77963.1,77965.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.27 77970[58:Spt:77968.0,77963.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 77973[58:Res:77970.0,61.1] always3(s6) || -> . % 76.04/76.27 77974[58:SSi:77973.0,695.0,76017.0] || -> . % 76.04/76.27 77975[56:Spt:77974.0,76015.2,76016.0] || xuntil6(s5)*+ -> . % 76.04/76.27 77976[56:Spt:77974.0,76015.0,76015.1] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.27 77977[56:Res:53.1,77976.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.27 77979[57:Spt:77977.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.27 77981[57:Res:77979.0,61.1] always3(s6) || -> . % 76.04/76.27 77982[57:SSi:77981.0,695.0] || -> . % 76.04/76.27 77983[57:Spt:77982.0,77977.1,77979.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.27 77984[57:Spt:77982.0,77977.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 77987[57:Res:77984.0,61.1] always3(s5) || -> . % 76.04/76.27 77988[57:SSi:77987.0,694.0,76014.0] || -> . % 76.04/76.27 77989[55:Spt:77988.0,76009.2,76013.0] || xuntil6(s4)*+ -> . % 76.04/76.27 77990[55:Spt:77988.0,76009.0,76009.1] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.27 77991[55:Res:53.1,77990.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.27 77996[56:Spt:77991.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 77998[56:Res:77996.0,61.1] always3(s4) || -> . % 76.04/76.27 77999[56:SSi:77998.0,693.0,76008.0] || -> . % 76.04/76.27 78000[56:Spt:77999.0,77991.0,77996.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.27 78001[56:Spt:77999.0,77991.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.27 78005[56:Res:78001.0,61.1] always3(s5) || -> . % 76.04/76.27 78006[56:SSi:78005.0,694.0] || -> . % 76.04/76.27 78007[54:Spt:78006.0,76006.2,76007.0] || xuntil6(s3)*+ -> . % 76.04/76.27 78008[54:Spt:78006.0,76006.0,76006.1] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.27 78009[54:Res:53.1,78008.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.27 78011[55:Spt:78009.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.27 78013[55:Res:78011.0,61.1] always3(s4) || -> . % 76.04/76.27 78014[55:SSi:78013.0,693.0] || -> . % 76.04/76.27 78015[55:Spt:78014.0,78009.1,78011.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.27 78016[55:Spt:78014.0,78009.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 78019[55:Res:78016.0,61.1] always3(s3) || -> . % 76.04/76.27 78020[55:SSi:78019.0,692.0,76005.0] || -> . % 76.04/76.27 78021[53:Spt:78020.0,76000.2,76004.0] || xuntil6(s2)*+ -> . % 76.04/76.27 78022[53:Spt:78020.0,76000.0,76000.1] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.27 78023[53:Res:53.1,78022.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.27 78025[54:Spt:78023.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.27 78027[54:Res:78025.0,61.1] always3(s3) || -> . % 76.04/76.27 78028[54:SSi:78027.0,692.0] || -> . % 76.04/76.27 78029[54:Spt:78028.0,78023.1,78025.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.27 78030[54:Spt:78028.0,78023.0] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 78033[54:Res:78030.0,61.1] always3(s2) || -> . % 76.04/76.27 78034[54:SSi:78033.0,691.0,75999.0] || -> . % 76.04/76.27 78035[52:Spt:78034.0,75994.2,75998.0] || xuntil6(s1)*+ -> . % 76.04/76.27 78036[52:Spt:78034.0,75994.0,75994.1] || m_main_v_state(s1,c_ready)*+ -> m_main_v_state(s2,c_busy). % 76.04/76.27 78037[52:Res:53.1,78036.0] || -> m_main_v_state(s1,c_busy)* m_main_v_state(s2,c_busy). % 76.04/76.27 78042[53:Spt:78037.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 78044[53:Res:78042.0,61.1] always3(s1) || -> . % 76.04/76.27 78045[53:SSi:78044.0,690.0,75993.0] || -> . % 76.04/76.27 78046[53:Spt:78045.0,78037.0,78042.0] || m_main_v_state(s1,c_busy)* -> . % 76.04/76.27 78047[53:Spt:78045.0,78037.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.27 78052[53:Res:78047.0,61.1] always3(s2) || -> . % 76.04/76.27 78053[53:SSi:78052.0,691.0] || -> . % 76.04/76.27 78054[51:Spt:78053.0,74.0,75992.0] || xuntil6(s0)*+ -> . % 76.04/76.27 78055[51:Spt:78053.0,74.1] || -> node4(s0)*. % 76.04/76.27 78056[51:MRR:758.1,78054.0] || -> m_main_v_state(s1,c_busy)*. % 76.04/76.27 78058[51:Res:78056.0,61.1] always3(s1) || -> . % 76.04/76.27 78059[51:SSi:78058.0,690.0] || -> . % 76.04/76.27 78060[1:Spt:78059.0,689.0,690.0] || always3(s1)*+ -> . % 76.04/76.27 78061[1:Spt:78059.0,689.1] || -> xuntil6(s0)*. % 76.04/76.27 78062[1:MRR:176.0,78061.0] || -> until5(s1)*. % 76.04/76.27 78063[1:MRR:534.1,78060.0] always3(s0) || -> . % 76.04/76.27 78064[1:MRR:639.1,78060.0] node4(s0) || -> . % 76.04/76.27 78065[1:MRR:196.2,78064.0] until2p7(s0) || -> until2p7(s1)*. % 76.04/76.27 78068[1:Res:65.1,78060.0] node4(s1) || -> . % 76.04/76.27 78069[1:MRR:197.2,78068.0] until2p7(s1) || -> until2p7(s2)*. % 76.04/76.27 78072[1:SoR:78068.0,66.2] until5(s1) || -> xuntil6(s1)*. % 76.04/76.27 78073[1:SSi:78072.0,78062.0] || -> xuntil6(s1)*. % 76.04/76.27 78074[1:MRR:175.0,78073.0] || -> until5(s2)*. % 76.04/76.27 78075[1:MRR:76421.0,78074.0] || m_main_v_state(s2,c_ready)* -> m_main_v_state(s3,c_busy) xuntil6(s2). % 76.04/76.27 78076[1:MRR:686.0,78074.0] || -> always3(s3)* xuntil6(s2). % 76.04/76.27 78080[2:Spt:78076.1] || -> xuntil6(s2)*. % 76.04/76.27 78081[2:MRR:174.0,78080.0] || -> until5(s3)*. % 76.04/76.27 78082[2:MRR:76420.0,78081.0] || m_main_v_state(s3,c_ready)* -> m_main_v_state(s4,c_busy) xuntil6(s3). % 76.04/76.27 78083[2:MRR:685.0,78081.0] || -> always3(s4)* xuntil6(s3). % 76.04/76.27 78084[3:Spt:78083.1] || -> xuntil6(s3)*. % 76.04/76.27 78085[3:MRR:173.0,78084.0] || -> until5(s4)*. % 76.04/76.27 78086[3:MRR:76413.0,78085.0] || m_main_v_state(s4,c_ready)* -> m_main_v_state(s5,c_busy) xuntil6(s4). % 76.04/76.27 78087[3:MRR:684.0,78085.0] || -> always3(s5)* xuntil6(s4). % 76.04/76.27 78088[4:Spt:78087.1] || -> xuntil6(s4)*. % 76.04/76.27 78089[4:MRR:172.0,78088.0] || -> until5(s5)*. % 76.04/76.27 78090[4:MRR:76412.0,78089.0] || m_main_v_state(s5,c_ready)* -> m_main_v_state(s6,c_busy) xuntil6(s5). % 76.04/76.27 78091[4:MRR:683.0,78089.0] || -> always3(s6)* xuntil6(s5). % 76.04/76.27 78092[5:Spt:78091.1] || -> xuntil6(s5)*. % 76.04/76.27 78093[5:MRR:171.0,78092.0] || -> until5(s6)*. % 76.04/76.27 78094[5:MRR:76411.0,78093.0] || m_main_v_state(s6,c_ready)* -> m_main_v_state(s7,c_busy) xuntil6(s6). % 76.04/76.27 78095[5:MRR:682.0,78093.0] || -> always3(s7)* xuntil6(s6). % 76.04/76.27 78096[6:Spt:78095.1] || -> xuntil6(s6)*. % 76.04/76.27 78097[6:MRR:170.0,78096.0] || -> until5(s7)*. % 76.04/76.27 78098[6:MRR:76401.0,78097.0] || m_main_v_state(s7,c_ready)* -> m_main_v_state(s8,c_busy) xuntil6(s7). % 76.04/76.27 78099[6:MRR:681.0,78097.0] || -> always3(s8)* xuntil6(s7). % 76.04/76.27 78100[7:Spt:78099.1] || -> xuntil6(s7)*. % 76.04/76.27 78101[7:MRR:169.0,78100.0] || -> until5(s8)*. % 76.04/76.27 78102[7:MRR:76400.0,78101.0] || m_main_v_state(s8,c_ready)* -> m_main_v_state(s9,c_busy) xuntil6(s8). % 76.04/76.27 78103[7:MRR:680.0,78101.0] || -> always3(s9)* xuntil6(s8). % 76.04/76.27 78105[8:Spt:78103.1] || -> xuntil6(s8)*. % 76.04/76.27 78106[8:MRR:168.0,78105.0] || -> until5(s9)*. % 76.04/76.27 78107[8:MRR:76396.0,78106.0] || m_main_v_state(s9,c_ready)* -> m_main_v_state(s10,c_busy) xuntil6(s9). % 76.04/76.27 78108[8:MRR:679.0,78106.0] || -> always3(s10)* xuntil6(s9). % 76.04/76.27 78109[9:Spt:78108.1] || -> xuntil6(s9)*. % 76.04/76.27 78110[9:MRR:167.0,78109.0] || -> until5(s10)*. % 76.04/76.27 78111[9:MRR:76389.0,78110.0] || m_main_v_state(s10,c_ready)* -> m_main_v_state(s11,c_busy) xuntil6(s10). % 76.04/76.27 78112[9:MRR:678.0,78110.0] || -> always3(s11)* xuntil6(s10). % 76.04/76.27 78114[10:Spt:78112.1] || -> xuntil6(s10)*. % 76.04/76.27 78115[10:MRR:166.0,78114.0] || -> until5(s11)*. % 76.04/76.27 78116[10:MRR:76385.0,78115.0] || m_main_v_state(s11,c_ready)* -> m_main_v_state(s12,c_busy) xuntil6(s11). % 76.04/76.27 78117[10:MRR:677.0,78115.0] || -> always3(s12)* xuntil6(s11). % 76.04/76.27 78118[11:Spt:78117.1] || -> xuntil6(s11)*. % 76.04/76.27 78119[11:MRR:165.0,78118.0] || -> until5(s12)*. % 76.04/76.27 78120[11:MRR:76384.0,78119.0] || m_main_v_state(s12,c_ready)* -> m_main_v_state(s13,c_busy) xuntil6(s12). % 76.04/76.27 78121[11:MRR:676.0,78119.0] || -> always3(s13)* xuntil6(s12). % 76.04/76.27 78123[12:Spt:78121.1] || -> xuntil6(s12)*. % 76.04/76.27 78124[12:MRR:164.0,78123.0] || -> until5(s13)*. % 76.04/76.27 78125[12:MRR:76380.0,78124.0] || m_main_v_state(s13,c_ready)* -> m_main_v_state(s14,c_busy) xuntil6(s13). % 76.04/76.27 78126[12:MRR:675.0,78124.0] || -> always3(s14)* xuntil6(s13). % 76.04/76.27 78127[13:Spt:78126.1] || -> xuntil6(s13)*. % 76.04/76.27 78128[13:MRR:163.0,78127.0] || -> until5(s14)*. % 76.04/76.27 78129[13:MRR:76373.0,78128.0] || m_main_v_state(s14,c_ready)* -> m_main_v_state(s15,c_busy) xuntil6(s14). % 76.04/76.27 78130[13:MRR:674.0,78128.0] || -> always3(s15)* xuntil6(s14). % 76.04/76.27 78132[14:Spt:78130.1] || -> xuntil6(s14)*. % 76.04/76.27 78133[14:MRR:162.0,78132.0] || -> until5(s15)*. % 76.04/76.27 78134[14:MRR:76372.0,78133.0] || m_main_v_state(s15,c_ready)* -> m_main_v_state(s16,c_busy) xuntil6(s15). % 76.04/76.27 78135[14:MRR:673.0,78133.0] || -> always3(s16)* xuntil6(s15). % 76.04/76.27 78136[15:Spt:78135.1] || -> xuntil6(s15)*. % 76.04/76.27 78137[15:MRR:161.0,78136.0] || -> until5(s16)*. % 76.04/76.27 78138[15:MRR:76365.0,78137.0] || m_main_v_state(s16,c_ready)* -> m_main_v_state(s17,c_busy) xuntil6(s16). % 76.04/76.27 78139[15:MRR:672.0,78137.0] || -> always3(s17)* xuntil6(s16). % 76.04/76.27 78141[16:Spt:78139.1] || -> xuntil6(s16)*. % 76.04/76.27 78142[16:MRR:160.0,78141.0] || -> until5(s17)*. % 76.04/76.27 78143[16:MRR:76361.0,78142.0] || m_main_v_state(s17,c_ready)* -> m_main_v_state(s18,c_busy) xuntil6(s17). % 76.04/76.27 78144[16:MRR:671.0,78142.0] || -> always3(s18)* xuntil6(s17). % 76.04/76.27 78145[17:Spt:78144.1] || -> xuntil6(s17)*. % 76.04/76.27 78146[17:MRR:159.0,78145.0] || -> until5(s18)*. % 76.04/76.27 78147[17:MRR:76360.0,78146.0] || m_main_v_state(s18,c_ready)* -> m_main_v_state(s19,c_busy) xuntil6(s18). % 76.04/76.27 78148[17:MRR:670.0,78146.0] || -> always3(s19)* xuntil6(s18). % 76.04/76.27 78150[18:Spt:78148.1] || -> xuntil6(s18)*. % 76.04/76.27 78151[18:MRR:158.0,78150.0] || -> until5(s19)*. % 76.04/76.27 78152[18:MRR:76353.0,78151.0] || m_main_v_state(s19,c_ready)* -> m_main_v_state(s20,c_busy) xuntil6(s19). % 76.04/76.27 78153[18:MRR:669.0,78151.0] || -> always3(s20)* xuntil6(s19). % 76.04/76.27 78154[19:Spt:78153.1] || -> xuntil6(s19)*. % 76.04/76.27 78155[19:MRR:157.0,78154.0] || -> until5(s20)*. % 76.04/76.27 78156[19:MRR:76352.0,78155.0] || m_main_v_state(s20,c_ready)* -> m_main_v_state(s21,c_busy) xuntil6(s20). % 76.04/76.27 78157[19:MRR:668.0,78155.0] || -> always3(s21)* xuntil6(s20). % 76.04/76.27 78159[20:Spt:78157.1] || -> xuntil6(s20)*. % 76.04/76.27 78160[20:MRR:156.0,78159.0] || -> until5(s21)*. % 76.04/76.27 78161[20:MRR:76351.0,78160.0] || m_main_v_state(s21,c_ready)* -> m_main_v_state(s22,c_busy) xuntil6(s21). % 76.04/76.27 78162[20:MRR:667.0,78160.0] || -> always3(s22)* xuntil6(s21). % 76.04/76.27 78163[21:Spt:78162.1] || -> xuntil6(s21)*. % 76.04/76.27 78164[21:MRR:155.0,78163.0] || -> until5(s22)*. % 76.04/76.27 78165[21:MRR:76341.0,78164.0] || m_main_v_state(s22,c_ready)* -> m_main_v_state(s23,c_busy) xuntil6(s22). % 76.04/76.27 78166[21:MRR:666.0,78164.0] || -> always3(s23)* xuntil6(s22). % 76.04/76.27 78168[22:Spt:78166.1] || -> xuntil6(s22)*. % 76.04/76.27 78169[22:MRR:154.0,78168.0] || -> until5(s23)*. % 76.04/76.27 78170[22:MRR:76340.0,78169.0] || m_main_v_state(s23,c_ready)* -> m_main_v_state(s24,c_busy) xuntil6(s23). % 76.04/76.27 78171[22:MRR:665.0,78169.0] || -> always3(s24)* xuntil6(s23). % 76.04/76.27 78172[23:Spt:78171.1] || -> xuntil6(s23)*. % 76.04/76.27 78173[23:MRR:153.0,78172.0] || -> until5(s24)*. % 76.04/76.27 78174[23:MRR:76333.0,78173.0] || m_main_v_state(s24,c_ready)* -> m_main_v_state(s25,c_busy) xuntil6(s24). % 76.04/76.27 78175[23:MRR:664.0,78173.0] || -> always3(s25)* xuntil6(s24). % 76.04/76.27 78177[24:Spt:78175.1] || -> xuntil6(s24)*. % 76.04/76.27 78178[24:MRR:152.0,78177.0] || -> until5(s25)*. % 76.04/76.27 78179[24:MRR:76329.0,78178.0] || m_main_v_state(s25,c_ready)* -> m_main_v_state(s26,c_busy) xuntil6(s25). % 76.04/76.27 78180[24:MRR:663.0,78178.0] || -> always3(s26)* xuntil6(s25). % 76.04/76.27 78181[25:Spt:78180.1] || -> xuntil6(s25)*. % 76.04/76.27 78182[25:MRR:151.0,78181.0] || -> until5(s26)*. % 76.04/76.27 78183[25:MRR:76325.0,78182.0] || m_main_v_state(s26,c_ready)* -> m_main_v_state(s27,c_busy) xuntil6(s26). % 76.04/76.27 78184[25:MRR:662.0,78182.0] || -> always3(s27)* xuntil6(s26). % 76.04/76.27 78186[26:Spt:78184.1] || -> xuntil6(s26)*. % 76.04/76.27 78187[26:MRR:150.0,78186.0] || -> until5(s27)*. % 76.04/76.27 78188[26:MRR:76321.0,78187.0] || m_main_v_state(s27,c_ready)* -> m_main_v_state(s28,c_busy) xuntil6(s27). % 76.04/76.27 78189[26:MRR:661.0,78187.0] || -> always3(s28)* xuntil6(s27). % 76.04/76.27 78190[27:Spt:78189.1] || -> xuntil6(s27)*. % 76.04/76.27 78191[27:MRR:149.0,78190.0] || -> until5(s28)*. % 76.04/76.27 78192[27:MRR:76320.0,78191.0] || m_main_v_state(s28,c_ready)* -> m_main_v_state(s29,c_busy) xuntil6(s28). % 76.04/76.27 78193[27:MRR:660.0,78191.0] || -> always3(s29)* xuntil6(s28). % 76.04/76.27 78195[28:Spt:78193.1] || -> xuntil6(s28)*. % 76.04/76.27 78196[28:MRR:148.0,78195.0] || -> until5(s29)*. % 76.04/76.27 78197[28:MRR:76313.0,78196.0] || m_main_v_state(s29,c_ready)* -> m_main_v_state(s30,c_busy) xuntil6(s29). % 76.04/76.27 78198[28:MRR:659.0,78196.0] || -> always3(s30)* xuntil6(s29). % 76.04/76.27 78199[29:Spt:78198.1] || -> xuntil6(s29)*. % 76.04/76.27 78200[29:MRR:147.0,78199.0] || -> until5(s30)*. % 76.04/76.27 78201[29:MRR:76312.0,78200.0] || m_main_v_state(s30,c_ready)* -> m_main_v_state(s31,c_busy) xuntil6(s30). % 76.04/76.27 78202[29:MRR:658.0,78200.0] || -> always3(s31)* xuntil6(s30). % 76.04/76.27 78204[30:Spt:78202.1] || -> xuntil6(s30)*. % 76.04/76.27 78205[30:MRR:146.0,78204.0] || -> until5(s31)*. % 76.04/76.27 78206[30:MRR:76311.0,78205.0] || m_main_v_state(s31,c_ready)* -> m_main_v_state(s32,c_busy) xuntil6(s31). % 76.04/76.27 78207[30:MRR:657.0,78205.0] || -> always3(s32)* xuntil6(s31). % 76.04/76.27 78208[31:Spt:78207.1] || -> xuntil6(s31)*. % 76.04/76.27 78209[31:MRR:145.0,78208.0] || -> until5(s32)*. % 76.04/76.27 78210[31:MRR:76307.0,78209.0] || m_main_v_state(s32,c_ready)* -> m_main_v_state(s33,c_busy) xuntil6(s32). % 76.04/76.27 78211[31:MRR:656.0,78209.0] || -> always3(s33)* xuntil6(s32). % 76.04/76.27 78213[32:Spt:78211.1] || -> xuntil6(s32)*. % 76.04/76.27 78214[32:MRR:144.0,78213.0] || -> until5(s33)*. % 76.04/76.27 78215[32:MRR:68175.0,78214.0] || m_main_v_state(s33,c_ready)* -> m_main_v_state(s34,c_busy) xuntil6(s33). % 76.04/76.27 78216[32:MRR:655.0,78214.0] || -> always3(s34)* xuntil6(s33). % 76.04/76.27 78217[33:Spt:78216.1] || -> xuntil6(s33)*. % 76.04/76.27 78218[33:MRR:143.0,78217.0] || -> until5(s34)*. % 76.04/76.27 78219[33:MRR:74335.0,78218.0] || m_main_v_state(s34,c_ready)* -> m_main_v_state(s35,c_busy) xuntil6(s34). % 76.04/76.27 78220[33:MRR:654.0,78218.0] || -> always3(s35)* xuntil6(s34). % 76.04/76.27 78222[34:Spt:78220.1] || -> xuntil6(s34)*. % 76.04/76.27 78223[34:MRR:142.0,78222.0] || -> until5(s35)*. % 76.04/76.27 78224[34:MRR:68179.0,78223.0] || m_main_v_state(s35,c_ready)* -> m_main_v_state(s36,c_busy) xuntil6(s35). % 76.04/76.27 78225[34:MRR:653.0,78223.0] || -> always3(s36)* xuntil6(s35). % 76.04/76.27 78226[35:Spt:78225.1] || -> xuntil6(s35)*. % 76.04/76.27 78227[35:MRR:141.0,78226.0] || -> until5(s36)*. % 76.04/76.27 78228[35:MRR:74342.0,78227.0] || m_main_v_state(s36,c_ready)* -> m_main_v_state(s37,c_busy) xuntil6(s36). % 76.04/76.27 78229[35:MRR:652.0,78227.0] || -> always3(s37)* xuntil6(s36). % 76.04/76.27 78231[36:Spt:78229.1] || -> xuntil6(s36)*. % 76.04/76.27 78232[36:MRR:140.0,78231.0] || -> until5(s37)*. % 76.04/76.27 78233[36:MRR:68186.0,78232.0] || m_main_v_state(s37,c_ready)* -> m_main_v_state(s38,c_busy) xuntil6(s37). % 76.04/76.27 78234[36:MRR:651.0,78232.0] || -> always3(s38)* xuntil6(s37). % 76.04/76.27 78235[37:Spt:78234.1] || -> xuntil6(s37)*. % 76.04/76.27 78236[37:MRR:139.0,78235.0] || -> until5(s38)*. % 76.04/76.27 78237[37:MRR:74343.0,78236.0] || m_main_v_state(s38,c_ready)* -> m_main_v_state(s39,c_busy) xuntil6(s38). % 76.04/76.27 78238[37:MRR:650.0,78236.0] || -> always3(s39)* xuntil6(s38). % 76.04/76.27 78240[38:Spt:78238.1] || -> xuntil6(s38)*. % 76.04/76.27 78241[38:MRR:138.0,78240.0] || -> until5(s39)*. % 76.04/76.27 78242[38:MRR:68187.0,78241.0] || m_main_v_state(s39,c_ready)* -> m_main_v_state(s40,c_busy) xuntil6(s39). % 76.04/76.27 78243[38:MRR:649.0,78241.0] || -> always3(s40)* xuntil6(s39). % 76.04/76.27 78244[39:Spt:78243.1] || -> xuntil6(s39)*. % 76.04/76.27 78245[39:MRR:137.0,78244.0] || -> until5(s40)*. % 76.04/76.27 78246[39:MRR:74347.0,78245.0] || m_main_v_state(s40,c_ready)* -> m_main_v_state(s41,c_busy) xuntil6(s40). % 76.04/76.27 78247[39:MRR:648.0,78245.0] || -> always3(s41)* xuntil6(s40). % 76.04/76.27 78249[40:Spt:78247.1] || -> xuntil6(s40)*. % 76.04/76.27 78250[40:MRR:136.0,78249.0] || -> until5(s41)*. % 76.04/76.27 78251[40:MRR:68191.0,78250.0] || m_main_v_state(s41,c_ready)* -> m_main_v_state(s42,c_busy) xuntil6(s41). % 76.04/76.27 78252[40:MRR:647.0,78250.0] || -> always3(s42)* xuntil6(s41). % 76.04/76.27 78253[41:Spt:78252.1] || -> xuntil6(s41)*. % 76.04/76.27 78254[41:MRR:135.0,78253.0] || -> until5(s42)*. % 76.04/76.27 78255[41:MRR:74351.0,78254.0] || m_main_v_state(s42,c_ready)* -> m_main_v_state(s43,c_busy) xuntil6(s42). % 76.04/76.27 78256[41:MRR:646.0,78254.0] || -> always3(s43)* xuntil6(s42). % 76.04/76.27 78258[42:Spt:78256.1] || -> xuntil6(s42)*. % 76.04/76.27 78259[42:MRR:134.0,78258.0] || -> until5(s43)*. % 76.04/76.27 78260[42:MRR:68195.0,78259.0] || m_main_v_state(s43,c_ready)* -> m_main_v_state(s44,c_busy) xuntil6(s43). % 76.04/76.27 78261[42:MRR:645.0,78259.0] || -> always3(s44)* xuntil6(s43). % 76.04/76.27 78262[43:Spt:78261.1] || -> xuntil6(s43)*. % 76.04/76.27 78263[43:MRR:133.0,78262.0] || -> until5(s44)*. % 76.04/76.27 78264[43:MRR:74355.0,78263.0] || m_main_v_state(s44,c_ready)* -> m_main_v_state(s45,c_busy) xuntil6(s44). % 76.04/76.27 78265[43:MRR:644.0,78263.0] || -> always3(s45)* xuntil6(s44). % 76.04/76.27 78267[44:Spt:78265.1] || -> xuntil6(s44)*. % 76.04/76.27 78268[44:MRR:132.0,78267.0] || -> until5(s45)*. % 76.04/76.27 78269[44:MRR:68199.0,78268.0] || m_main_v_state(s45,c_ready)* -> m_main_v_state(s46,c_busy) xuntil6(s45). % 76.04/76.27 78270[44:MRR:643.0,78268.0] || -> always3(s46)* xuntil6(s45). % 76.04/76.27 78271[45:Spt:78270.1] || -> xuntil6(s45)*. % 76.04/76.27 78272[45:MRR:131.0,78271.0] || -> until5(s46)*. % 76.04/76.27 78273[45:MRR:74362.0,78272.0] || m_main_v_state(s46,c_ready)* -> m_main_v_state(s47,c_busy) xuntil6(s46). % 76.04/76.27 78274[45:MRR:642.0,78272.0] || -> always3(s47)* xuntil6(s46). % 76.04/76.27 78276[46:Spt:78274.1] || -> xuntil6(s46)*. % 76.04/76.27 78277[46:MRR:130.0,78276.0] || -> until5(s47)*. % 76.04/76.27 78278[46:MRR:68203.0,78277.0] || m_main_v_state(s47,c_ready)* -> m_main_v_state(s48,c_busy) xuntil6(s47). % 76.04/76.27 78279[46:MRR:641.0,78277.0] || -> always3(s48)* xuntil6(s47). % 76.04/76.27 78280[47:Spt:78279.1] || -> xuntil6(s47)*. % 76.04/76.27 78281[47:MRR:129.0,78280.0] || -> until5(s48)*. % 76.04/76.27 78282[47:MRR:74363.0,78281.0] || m_main_v_state(s48,c_ready)*+ -> m_main_v_state(s49,c_busy) xuntil6(s48). % 76.04/76.27 78283[47:MRR:640.0,78281.0] || -> always3(s49)* xuntil6(s48). % 76.04/76.27 78285[48:Spt:78283.0] || -> always3(s49)*. % 76.04/76.27 78286[48:MRR:78.0,78285.0] || -> loop*. % 76.04/76.27 78287[48:MRR:52.0,78286.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1) trans(s49,s0)*. % 76.04/76.27 78291[48:Res:78287.49,62.1] always3(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.27 78293[48:SSi:78291.0,50.0,78285.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)* always3(s0). % 76.04/76.27 78294[48:MRR:78293.49,78063.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2) trans(s49,s1)*. % 76.04/76.27 78300[48:Res:78294.48,62.1] always3(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2)* always3(s1). % 76.04/76.27 78302[48:SSi:78300.0,50.0,78285.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2)* always3(s1). % 76.04/76.27 78303[48:MRR:78302.48,78060.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) trans(s49,s2)*. % 76.04/76.27 78372[48:Res:78303.47,69.2] xuntil6(s49) last(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.27 78373[48:Res:78303.47,62.1] always3(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* always3(s2). % 76.04/76.27 78374[48:Res:78303.47,60.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.27 78375[48:SSi:78373.0,50.0,78285.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* always3(s2). % 76.04/76.27 78376[48:SSi:78372.1,50.0,78285.0] xuntil6(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.27 78377[49:Spt:78282.1] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 78379[49:Res:78377.0,61.1] always3(s49) || -> . % 76.04/76.27 78380[49:SSi:78379.0,50.0,78285.0] || -> . % 76.04/76.27 78381[49:Spt:78380.0,78282.1,78377.0] || m_main_v_state(s49,c_busy)*+ -> . % 76.04/76.27 78382[49:Spt:78380.0,78282.0,78282.2] || m_main_v_state(s48,c_ready)*+ -> xuntil6(s48). % 76.04/76.27 78384[49:MRR:774.2,78381.0] node4(s48) || m_main_v_state(s48,c_ready)* -> . % 76.04/76.27 78385[49:Res:53.1,78382.0] || -> m_main_v_state(s48,c_busy)* xuntil6(s48). % 76.04/76.27 78387[50:Spt:78385.1] || -> xuntil6(s48)*. % 76.04/76.27 78388[50:MRR:128.0,78387.0] || -> until5(s49)*. % 76.04/76.27 78580[51:Spt:78375.47] || -> always3(s2)*. % 76.04/76.27 78581[51:MRR:528.0,78580.0] || -> always3(s3)*. % 76.04/76.27 78582[51:MRR:525.0,78581.0] || -> always3(s4)*. % 76.04/76.27 78583[51:MRR:522.0,78582.0] || -> always3(s5)*. % 76.04/76.27 78584[51:MRR:519.0,78583.0] || -> always3(s6)*. % 76.04/76.27 78585[51:MRR:516.0,78584.0] || -> always3(s7)*. % 76.04/76.27 78586[51:MRR:513.0,78585.0] || -> always3(s8)*. % 76.04/76.27 78587[51:MRR:510.0,78586.0] || -> always3(s9)*. % 76.04/76.27 78588[51:MRR:507.0,78587.0] || -> always3(s10)*. % 76.04/76.27 78589[51:MRR:504.0,78588.0] || -> always3(s11)*. % 76.04/76.27 78590[51:MRR:501.0,78589.0] || -> always3(s12)*. % 76.04/76.27 78591[51:MRR:498.0,78590.0] || -> always3(s13)*. % 76.04/76.27 78592[51:MRR:495.0,78591.0] || -> always3(s14)*. % 76.04/76.27 78593[51:MRR:492.0,78592.0] || -> always3(s15)*. % 76.04/76.27 78594[51:MRR:489.0,78593.0] || -> always3(s16)*. % 76.04/76.27 78595[51:MRR:486.0,78594.0] || -> always3(s17)*. % 76.04/76.27 78596[51:MRR:483.0,78595.0] || -> always3(s18)*. % 76.04/76.27 78597[51:MRR:480.0,78596.0] || -> always3(s19)*. % 76.04/76.27 78598[51:MRR:477.0,78597.0] || -> always3(s20)*. % 76.04/76.27 78599[51:MRR:474.0,78598.0] || -> always3(s21)*. % 76.04/76.27 78600[51:MRR:471.0,78599.0] || -> always3(s22)*. % 76.04/76.27 78601[51:MRR:468.0,78600.0] || -> always3(s23)*. % 76.04/76.27 78602[51:MRR:465.0,78601.0] || -> always3(s24)*. % 76.04/76.27 78603[51:MRR:462.0,78602.0] || -> always3(s25)*. % 76.04/76.27 78604[51:MRR:459.0,78603.0] || -> always3(s26)*. % 76.04/76.27 78605[51:MRR:456.0,78604.0] || -> always3(s27)*. % 76.04/76.27 78606[51:MRR:453.0,78605.0] || -> always3(s28)*. % 76.04/76.27 78607[51:MRR:450.0,78606.0] || -> always3(s29)*. % 76.04/76.27 78608[51:MRR:427.0,78607.0] || -> always3(s30)*. % 76.04/76.27 78609[51:MRR:425.0,78608.0] || -> always3(s31)*. % 76.04/76.27 78610[51:MRR:423.0,78609.0] || -> always3(s32)*. % 76.04/76.27 78611[51:MRR:421.0,78610.0] || -> always3(s33)*. % 76.04/76.27 78612[51:MRR:370.0,78611.0] || -> always3(s34)*. % 76.04/76.27 78613[51:MRR:368.0,78612.0] || -> always3(s35)*. % 76.04/76.27 78614[51:MRR:366.0,78613.0] || -> always3(s36)*. % 76.04/76.27 78615[51:MRR:364.0,78614.0] || -> always3(s37)*. % 76.04/76.27 78616[51:MRR:313.0,78615.0] || -> always3(s38)*. % 76.04/76.27 78617[51:MRR:311.0,78616.0] || -> always3(s39)*. % 76.04/76.27 78618[51:MRR:309.0,78617.0] || -> always3(s40)*. % 76.04/76.27 78619[51:MRR:307.0,78618.0] || -> always3(s41)*. % 76.04/76.27 78620[51:MRR:306.0,78619.0] || -> always3(s42)*. % 76.04/76.27 78621[51:MRR:305.0,78620.0] || -> always3(s43)*. % 76.04/76.27 78622[51:MRR:304.0,78621.0] || -> always3(s44)*. % 76.04/76.27 78623[51:MRR:303.0,78622.0] || -> always3(s45)*. % 76.04/76.27 78624[51:MRR:302.0,78623.0] || -> always3(s46)*. % 76.04/76.27 78625[51:MRR:301.0,78624.0] || -> always3(s47)*. % 76.04/76.27 78626[51:MRR:300.0,78625.0] || -> always3(s48)*. % 76.04/76.27 78627[52:Spt:78374.0] || -> trans(s49,s49)*. % 76.04/76.27 78628[52:Res:78627.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s49)*. % 76.04/76.27 78630[52:Res:78627.0,60.0] || -> node2(s49,s49)*. % 76.04/76.27 78631[52:SSi:78628.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s49)*. % 76.04/76.27 78632[52:Res:78630.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> m_main_v_state(s49,c_busy). % 76.04/76.27 78633[52:MRR:78632.1,78632.2,53.1,78381.0] m_main_v_request(s49) || -> . % 76.04/76.27 78635[52:SoR:78633.0,64.1] node4(s49) || -> . % 76.04/76.27 78636[52:MRR:194.1,78635.0] until2p7(s49) || -> . % 76.04/76.27 78639[52:MRR:78631.1,78636.0] xuntil6(s49) || -> . % 76.04/76.27 78640[52:SoR:78635.0,66.2] until5(s49) || -> xuntil6(s49)*. % 76.04/76.27 78641[52:SSi:78640.0,50.0,78285.0,78388.0] || -> xuntil6(s49)*. % 76.04/76.27 78642[52:MRR:78641.0,78639.0] || -> . % 76.04/76.27 78643[52:Spt:78642.0,78374.0,78627.0] || trans(s49,s49)*+ -> . % 76.04/76.27 78644[52:Spt:78642.0,78374.1,78374.2,78374.3,78374.4,78374.5,78374.6,78374.7,78374.8,78374.9,78374.10,78374.11,78374.12,78374.13,78374.14,78374.15,78374.16,78374.17,78374.18,78374.19,78374.20,78374.21,78374.22,78374.23,78374.24,78374.25,78374.26,78374.27,78374.28,78374.29,78374.30,78374.31,78374.32,78374.33,78374.34,78374.35,78374.36,78374.37,78374.38,78374.39,78374.40,78374.41,78374.42,78374.43,78374.44,78374.45,78374.46,78374.47] || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.27 78646[52:MRR:78376.1,78643.0] xuntil6(s49) || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.27 78647[53:Spt:78644.0] || -> trans(s49,s48)*. % 76.04/76.27 78648[53:Res:78647.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s48)*. % 76.04/76.27 78650[53:Res:78647.0,60.0] || -> node2(s49,s48)*. % 76.04/76.27 78651[53:SSi:78648.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s48)*. % 76.04/76.27 78652[53:Res:78650.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)*. % 76.04/76.27 78655[53:SoR:78652.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)*. % 76.04/76.27 78657[53:SoR:78655.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)* xuntil6(s49). % 76.04/76.27 78658[53:SSi:78657.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s48,c_busy)* xuntil6(s49). % 76.04/76.27 78659[54:Spt:78658.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.27 78661[54:Res:78659.0,61.1] always3(s48) || -> . % 76.04/76.27 78662[54:SSi:78661.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.27 78663[54:Spt:78662.0,78658.1,78659.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.27 78664[54:Spt:78662.0,78658.0,78658.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.27 78668[54:MRR:78655.2,78663.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.27 78669[54:Res:53.1,78664.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.27 78671[54:MRR:78669.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.27 78672[54:MRR:78651.0,78671.0] || -> until2p7(s48)*. % 76.04/76.27 78673[54:MRR:559.0,78672.0] || -> until2p7(s49)* node4(s48). % 76.04/76.27 78674[55:Spt:78673.0] || -> until2p7(s49)*. % 76.04/76.27 78675[55:MRR:194.0,78674.0] || -> node4(s49)*. % 76.04/76.27 78676[55:MRR:78668.0,78675.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.27 78677[55:Res:53.1,78676.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 78679[55:MRR:78677.0,78381.0] || -> . % 76.04/76.27 78680[55:Spt:78679.0,78673.0,78674.0] || until2p7(s49)*+ -> . % 76.04/76.27 78681[55:Spt:78679.0,78673.1] || -> node4(s48)*. % 76.04/76.27 78682[55:MRR:78384.0,78681.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.27 78685[55:Res:53.1,78682.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.27 78687[55:MRR:78685.0,78663.0] || -> . % 76.04/76.27 78688[53:Spt:78687.0,78644.0,78647.0] || trans(s49,s48)*+ -> . % 76.04/76.27 78689[53:Spt:78687.0,78644.1,78644.2,78644.3,78644.4,78644.5,78644.6,78644.7,78644.8,78644.9,78644.10,78644.11,78644.12,78644.13,78644.14,78644.15,78644.16,78644.17,78644.18,78644.19,78644.20,78644.21,78644.22,78644.23,78644.24,78644.25,78644.26,78644.27,78644.28,78644.29,78644.30,78644.31,78644.32,78644.33,78644.34,78644.35,78644.36,78644.37,78644.38,78644.39,78644.40,78644.41,78644.42,78644.43,78644.44,78644.45,78644.46] || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.27 78691[53:MRR:78646.1,78688.0] xuntil6(s49) || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.27 78692[54:Spt:78689.0] || -> trans(s49,s47)*. % 76.04/76.27 78693[54:Res:78692.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s47)*. % 76.04/76.27 78695[54:Res:78692.0,60.0] || -> node2(s49,s47)*. % 76.04/76.27 78696[54:SSi:78693.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s47)*. % 76.04/76.27 78697[54:Res:78695.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 78709[54:SoR:78697.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 78711[54:SoR:78709.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 76.04/76.27 78712[54:SSi:78711.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 76.04/76.27 78713[55:Spt:78712.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.27 78715[55:Res:78713.0,61.1] always3(s47) || -> . % 76.04/76.27 78716[55:SSi:78715.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.27 78717[55:Spt:78716.0,78712.1,78713.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.04/76.27 78718[55:Spt:78716.0,78712.0,78712.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.27 78722[55:MRR:78709.2,78717.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.27 78723[55:Res:53.1,78718.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.27 78725[55:MRR:78723.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.27 78726[55:MRR:78696.0,78725.0] || -> until2p7(s47)*. % 76.04/76.27 78727[55:MRR:554.0,78726.0] || -> until2p7(s48)* node4(s47). % 76.04/76.27 78728[56:Spt:78727.0] || -> until2p7(s48)*. % 76.04/76.27 78729[56:MRR:559.0,78728.0] || -> until2p7(s49)* node4(s48). % 76.04/76.27 78730[57:Spt:78729.0] || -> until2p7(s49)*. % 76.04/76.27 78731[57:MRR:194.0,78730.0] || -> node4(s49)*. % 76.04/76.27 78732[57:MRR:78722.0,78731.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.27 78733[57:Res:53.1,78732.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.27 78735[57:MRR:78733.0,78381.0] || -> . % 76.04/76.27 78736[57:Spt:78735.0,78729.0,78730.0] || until2p7(s49)*+ -> . % 76.04/76.27 78737[57:Spt:78735.0,78729.1] || -> node4(s48)*. % 76.04/76.27 78738[57:MRR:78384.0,78737.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.27 78741[57:Res:53.1,78738.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.27 78744[57:Res:78741.0,61.1] always3(s48) || -> . % 76.04/76.27 78745[57:SSi:78744.0,78281.0,78387.0,78626.0,78728.0,78737.0] || -> . % 76.04/76.27 78746[56:Spt:78745.0,78727.0,78728.0] || until2p7(s48)*+ -> . % 76.04/76.27 78747[56:Spt:78745.0,78727.1] || -> node4(s47)*. % 76.04/76.27 78749[56:MRR:777.0,78747.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.27 78764[56:Res:53.1,78749.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.27 78766[56:MRR:78764.0,78717.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.27 78768[56:Res:78766.0,61.1] always3(s48) || -> . % 76.04/76.27 78769[56:SSi:78768.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.27 78770[54:Spt:78769.0,78689.0,78692.0] || trans(s49,s47)*+ -> . % 76.04/76.27 78771[54:Spt:78769.0,78689.1,78689.2,78689.3,78689.4,78689.5,78689.6,78689.7,78689.8,78689.9,78689.10,78689.11,78689.12,78689.13,78689.14,78689.15,78689.16,78689.17,78689.18,78689.19,78689.20,78689.21,78689.22,78689.23,78689.24,78689.25,78689.26,78689.27,78689.28,78689.29,78689.30,78689.31,78689.32,78689.33,78689.34,78689.35,78689.36,78689.37,78689.38,78689.39,78689.40,78689.41,78689.42,78689.43,78689.44,78689.45] || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.27 78773[54:MRR:78691.1,78770.0] xuntil6(s49) || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.27 78774[55:Spt:78771.0] || -> trans(s49,s46)*. % 76.04/76.27 78775[55:Res:78774.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s46)*. % 76.04/76.27 78777[55:Res:78774.0,60.0] || -> node2(s49,s46)*. % 76.04/76.27 78778[55:SSi:78775.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s46)*. % 76.04/76.27 78779[55:Res:78777.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)*. % 76.04/76.27 78795[55:SoR:78779.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)*. % 76.04/76.27 78797[55:SoR:78795.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)* xuntil6(s49). % 76.04/76.27 78798[55:SSi:78797.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s46,c_busy)* xuntil6(s49). % 76.04/76.27 78799[56:Spt:78798.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.27 78801[56:Res:78799.0,61.1] always3(s46) || -> . % 76.04/76.27 78802[56:SSi:78801.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 78803[56:Spt:78802.0,78798.1,78799.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.28 78804[56:Spt:78802.0,78798.0,78798.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 78808[56:MRR:78795.2,78803.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 78809[56:Res:53.1,78804.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 78811[56:MRR:78809.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 78812[56:MRR:78778.0,78811.0] || -> until2p7(s46)*. % 76.04/76.28 78813[56:MRR:549.0,78812.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 78814[57:Spt:78813.0] || -> until2p7(s47)*. % 76.04/76.28 78815[57:MRR:554.0,78814.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 78816[58:Spt:78815.0] || -> until2p7(s48)*. % 76.04/76.28 78817[58:MRR:559.0,78816.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 78818[59:Spt:78817.0] || -> until2p7(s49)*. % 76.04/76.28 78819[59:MRR:194.0,78818.0] || -> node4(s49)*. % 76.04/76.28 78820[59:MRR:78808.0,78819.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 78821[59:Res:53.1,78820.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 78823[59:MRR:78821.0,78381.0] || -> . % 76.04/76.28 78824[59:Spt:78823.0,78817.0,78818.0] || until2p7(s49)*+ -> . % 76.04/76.28 78825[59:Spt:78823.0,78817.1] || -> node4(s48)*. % 76.04/76.28 78826[59:MRR:78384.0,78825.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 78829[59:Res:53.1,78826.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 78832[59:Res:78829.0,61.1] always3(s48) || -> . % 76.04/76.28 78833[59:SSi:78832.0,78281.0,78387.0,78626.0,78816.0,78825.0] || -> . % 76.04/76.28 78834[58:Spt:78833.0,78815.0,78816.0] || until2p7(s48)*+ -> . % 76.04/76.28 78835[58:Spt:78833.0,78815.1] || -> node4(s47)*. % 76.04/76.28 78837[58:MRR:777.0,78835.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 78852[58:Res:53.1,78837.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 78854[59:Spt:78852.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 78856[59:Res:78854.0,61.1] always3(s48) || -> . % 76.04/76.28 78857[59:SSi:78856.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 78858[59:Spt:78857.0,78852.1,78854.0] || m_main_v_state(s48,c_busy)* -> . % 76.04/76.28 78859[59:Spt:78857.0,78852.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 78862[59:Res:78859.0,61.1] always3(s47) || -> . % 76.04/76.28 78863[59:SSi:78862.0,78277.0,78280.0,78625.0,78814.0,78835.0] || -> . % 76.04/76.28 78864[57:Spt:78863.0,78813.0,78814.0] || until2p7(s47)*+ -> . % 76.04/76.28 78865[57:Spt:78863.0,78813.1] || -> node4(s46)*. % 76.04/76.28 78867[57:MRR:780.0,78865.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 78874[57:Res:53.1,78867.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 78876[57:MRR:78874.0,78803.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 78878[57:Res:78876.0,61.1] always3(s47) || -> . % 76.04/76.28 78879[57:SSi:78878.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 78880[55:Spt:78879.0,78771.0,78774.0] || trans(s49,s46)*+ -> . % 76.04/76.28 78881[55:Spt:78879.0,78771.1,78771.2,78771.3,78771.4,78771.5,78771.6,78771.7,78771.8,78771.9,78771.10,78771.11,78771.12,78771.13,78771.14,78771.15,78771.16,78771.17,78771.18,78771.19,78771.20,78771.21,78771.22,78771.23,78771.24,78771.25,78771.26,78771.27,78771.28,78771.29,78771.30,78771.31,78771.32,78771.33,78771.34,78771.35,78771.36,78771.37,78771.38,78771.39,78771.40,78771.41,78771.42,78771.43,78771.44] || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 78883[55:MRR:78773.1,78880.0] xuntil6(s49) || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 78884[56:Spt:78881.0] || -> trans(s49,s45)*. % 76.04/76.28 78885[56:Res:78884.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s45)*. % 76.04/76.28 78887[56:Res:78884.0,60.0] || -> node2(s49,s45)*. % 76.04/76.28 78888[56:SSi:78885.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s45)*. % 76.04/76.28 78889[56:Res:78887.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 78905[56:SoR:78889.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 78907[56:SoR:78905.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)* xuntil6(s49). % 76.04/76.28 78908[56:SSi:78907.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s45,c_busy)* xuntil6(s49). % 76.04/76.28 78909[57:Spt:78908.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 78911[57:Res:78909.0,61.1] always3(s45) || -> . % 76.04/76.28 78912[57:SSi:78911.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 78913[57:Spt:78912.0,78908.1,78909.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.04/76.28 78914[57:Spt:78912.0,78908.0,78908.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 78918[57:MRR:78905.2,78913.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 78919[57:Res:53.1,78914.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 78921[57:MRR:78919.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 78922[57:MRR:78888.0,78921.0] || -> until2p7(s45)*. % 76.04/76.28 78923[57:MRR:544.0,78922.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 78924[58:Spt:78923.0] || -> until2p7(s46)*. % 76.04/76.28 78925[58:MRR:549.0,78924.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 78926[59:Spt:78925.0] || -> until2p7(s47)*. % 76.04/76.28 78927[59:MRR:554.0,78926.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 78928[60:Spt:78927.0] || -> until2p7(s48)*. % 76.04/76.28 78929[60:MRR:559.0,78928.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 78930[61:Spt:78929.0] || -> until2p7(s49)*. % 76.04/76.28 78931[61:MRR:194.0,78930.0] || -> node4(s49)*. % 76.04/76.28 78932[61:MRR:78918.0,78931.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 78933[61:Res:53.1,78932.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 78935[61:MRR:78933.0,78381.0] || -> . % 76.04/76.28 78936[61:Spt:78935.0,78929.0,78930.0] || until2p7(s49)*+ -> . % 76.04/76.28 78937[61:Spt:78935.0,78929.1] || -> node4(s48)*. % 76.04/76.28 78938[61:MRR:78384.0,78937.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 78941[61:Res:53.1,78938.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 78944[61:Res:78941.0,61.1] always3(s48) || -> . % 76.04/76.28 78945[61:SSi:78944.0,78281.0,78387.0,78626.0,78928.0,78937.0] || -> . % 76.04/76.28 78946[60:Spt:78945.0,78927.0,78928.0] || until2p7(s48)*+ -> . % 76.04/76.28 78947[60:Spt:78945.0,78927.1] || -> node4(s47)*. % 76.04/76.28 78949[60:MRR:777.0,78947.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 78964[60:Res:53.1,78949.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 78966[61:Spt:78964.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 78968[61:Res:78966.0,61.1] always3(s47) || -> . % 76.04/76.28 78969[61:SSi:78968.0,78277.0,78280.0,78625.0,78926.0,78947.0] || -> . % 76.04/76.28 78970[61:Spt:78969.0,78964.0,78966.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 78971[61:Spt:78969.0,78964.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 78975[61:Res:78971.0,61.1] always3(s48) || -> . % 76.04/76.28 78976[61:SSi:78975.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 78977[59:Spt:78976.0,78925.0,78926.0] || until2p7(s47)*+ -> . % 76.04/76.28 78978[59:Spt:78976.0,78925.1] || -> node4(s46)*. % 76.04/76.28 78980[59:MRR:780.0,78978.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 78987[59:Res:53.1,78980.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 78989[60:Spt:78987.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 78991[60:Res:78989.0,61.1] always3(s47) || -> . % 76.04/76.28 78992[60:SSi:78991.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 78993[60:Spt:78992.0,78987.1,78989.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 78994[60:Spt:78992.0,78987.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 78997[60:Res:78994.0,61.1] always3(s46) || -> . % 76.04/76.28 78998[60:SSi:78997.0,78272.0,78276.0,78624.0,78924.0,78978.0] || -> . % 76.04/76.28 78999[58:Spt:78998.0,78923.0,78924.0] || until2p7(s46)*+ -> . % 76.04/76.28 79000[58:Spt:78998.0,78923.1] || -> node4(s45)*. % 76.04/76.28 79002[58:MRR:783.0,79000.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 79005[58:Res:53.1,79002.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 79007[58:MRR:79005.0,78913.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 79009[58:Res:79007.0,61.1] always3(s46) || -> . % 76.04/76.28 79010[58:SSi:79009.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 79011[56:Spt:79010.0,78881.0,78884.0] || trans(s49,s45)*+ -> . % 76.04/76.28 79012[56:Spt:79010.0,78881.1,78881.2,78881.3,78881.4,78881.5,78881.6,78881.7,78881.8,78881.9,78881.10,78881.11,78881.12,78881.13,78881.14,78881.15,78881.16,78881.17,78881.18,78881.19,78881.20,78881.21,78881.22,78881.23,78881.24,78881.25,78881.26,78881.27,78881.28,78881.29,78881.30,78881.31,78881.32,78881.33,78881.34,78881.35,78881.36,78881.37,78881.38,78881.39,78881.40,78881.41,78881.42,78881.43] || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 79014[56:MRR:78883.1,79011.0] xuntil6(s49) || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 79015[57:Spt:79012.0] || -> trans(s49,s44)*. % 76.04/76.28 79016[57:Res:79015.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s44)*. % 76.04/76.28 79018[57:Res:79015.0,60.0] || -> node2(s49,s44)*. % 76.04/76.28 79019[57:SSi:79016.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s44)*. % 76.04/76.28 79020[57:Res:79018.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 79040[57:SoR:79020.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 79042[57:SoR:79040.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)* xuntil6(s49). % 76.04/76.28 79043[57:SSi:79042.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s44,c_busy)* xuntil6(s49). % 76.04/76.28 79044[58:Spt:79043.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 79046[58:Res:79044.0,61.1] always3(s44) || -> . % 76.04/76.28 79047[58:SSi:79046.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 79048[58:Spt:79047.0,79043.1,79044.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.28 79049[58:Spt:79047.0,79043.0,79043.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 79053[58:MRR:79040.2,79048.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 79054[58:Res:53.1,79049.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 79056[58:MRR:79054.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 79057[58:MRR:79019.0,79056.0] || -> until2p7(s44)*. % 76.04/76.28 79058[58:MRR:539.0,79057.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 79059[59:Spt:79058.0] || -> until2p7(s45)*. % 76.04/76.28 79060[59:MRR:544.0,79059.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 79061[60:Spt:79060.0] || -> until2p7(s46)*. % 76.04/76.28 79062[60:MRR:549.0,79061.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 79063[61:Spt:79062.0] || -> until2p7(s47)*. % 76.04/76.28 79064[61:MRR:554.0,79063.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 79065[62:Spt:79064.0] || -> until2p7(s48)*. % 76.04/76.28 79066[62:MRR:559.0,79065.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 79067[63:Spt:79066.0] || -> until2p7(s49)*. % 76.04/76.28 79068[63:MRR:194.0,79067.0] || -> node4(s49)*. % 76.04/76.28 79069[63:MRR:79053.0,79068.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 79070[63:Res:53.1,79069.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 79072[63:MRR:79070.0,78381.0] || -> . % 76.04/76.28 79073[63:Spt:79072.0,79066.0,79067.0] || until2p7(s49)*+ -> . % 76.04/76.28 79074[63:Spt:79072.0,79066.1] || -> node4(s48)*. % 76.04/76.28 79075[63:MRR:78384.0,79074.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 79078[63:Res:53.1,79075.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 79081[63:Res:79078.0,61.1] always3(s48) || -> . % 76.04/76.28 79082[63:SSi:79081.0,78281.0,78387.0,78626.0,79065.0,79074.0] || -> . % 76.04/76.28 79083[62:Spt:79082.0,79064.0,79065.0] || until2p7(s48)*+ -> . % 76.04/76.28 79084[62:Spt:79082.0,79064.1] || -> node4(s47)*. % 76.04/76.28 79086[62:MRR:777.0,79084.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 79101[62:Res:53.1,79086.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 79103[63:Spt:79101.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 79105[63:Res:79103.0,61.1] always3(s47) || -> . % 76.04/76.28 79106[63:SSi:79105.0,78277.0,78280.0,78625.0,79063.0,79084.0] || -> . % 76.04/76.28 79107[63:Spt:79106.0,79101.0,79103.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 79108[63:Spt:79106.0,79101.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 79112[63:Res:79108.0,61.1] always3(s48) || -> . % 76.04/76.28 79113[63:SSi:79112.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 79114[61:Spt:79113.0,79062.0,79063.0] || until2p7(s47)*+ -> . % 76.04/76.28 79115[61:Spt:79113.0,79062.1] || -> node4(s46)*. % 76.04/76.28 79117[61:MRR:780.0,79115.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 79127[61:Res:53.1,79117.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 79129[62:Spt:79127.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 79131[62:Res:79129.0,61.1] always3(s46) || -> . % 76.04/76.28 79132[62:SSi:79131.0,78272.0,78276.0,78624.0,79061.0,79115.0] || -> . % 76.04/76.28 79133[62:Spt:79132.0,79127.0,79129.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 79134[62:Spt:79132.0,79127.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 79138[62:Res:79134.0,61.1] always3(s47) || -> . % 76.04/76.28 79139[62:SSi:79138.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 79140[60:Spt:79139.0,79060.0,79061.0] || until2p7(s46)*+ -> . % 76.04/76.28 79141[60:Spt:79139.0,79060.1] || -> node4(s45)*. % 76.04/76.28 79143[60:MRR:783.0,79141.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 79146[60:Res:53.1,79143.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 79148[61:Spt:79146.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 79150[61:Res:79148.0,61.1] always3(s45) || -> . % 76.04/76.28 79151[61:SSi:79150.0,78268.0,78271.0,78623.0,79059.0,79141.0] || -> . % 76.04/76.28 79152[61:Spt:79151.0,79146.0,79148.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 79153[61:Spt:79151.0,79146.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 79157[61:Res:79153.0,61.1] always3(s46) || -> . % 76.04/76.28 79158[61:SSi:79157.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 79159[59:Spt:79158.0,79058.0,79059.0] || until2p7(s45)*+ -> . % 76.04/76.28 79160[59:Spt:79158.0,79058.1] || -> node4(s44)*. % 76.04/76.28 79162[59:MRR:786.0,79160.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 79165[59:Res:53.1,79162.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 79167[59:MRR:79165.0,79048.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 79169[59:Res:79167.0,61.1] always3(s45) || -> . % 76.04/76.28 79170[59:SSi:79169.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 79171[57:Spt:79170.0,79012.0,79015.0] || trans(s49,s44)*+ -> . % 76.04/76.28 79172[57:Spt:79170.0,79012.1,79012.2,79012.3,79012.4,79012.5,79012.6,79012.7,79012.8,79012.9,79012.10,79012.11,79012.12,79012.13,79012.14,79012.15,79012.16,79012.17,79012.18,79012.19,79012.20,79012.21,79012.22,79012.23,79012.24,79012.25,79012.26,79012.27,79012.28,79012.29,79012.30,79012.31,79012.32,79012.33,79012.34,79012.35,79012.36,79012.37,79012.38,79012.39,79012.40,79012.41,79012.42] || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 79174[57:MRR:79014.1,79171.0] xuntil6(s49) || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 79175[58:Spt:79172.0] || -> trans(s49,s43)*. % 76.04/76.28 79176[58:Res:79175.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s43)*. % 76.04/76.28 79178[58:Res:79175.0,60.0] || -> node2(s49,s43)*. % 76.04/76.28 79179[58:SSi:79176.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s43)*. % 76.04/76.28 79180[58:Res:79178.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 79204[58:SoR:79180.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 79206[58:SoR:79204.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 76.04/76.28 79207[58:SSi:79206.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 76.04/76.28 79208[59:Spt:79207.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 79210[59:Res:79208.0,61.1] always3(s43) || -> . % 76.04/76.28 79211[59:SSi:79210.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 79212[59:Spt:79211.0,79207.1,79208.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.04/76.28 79213[59:Spt:79211.0,79207.0,79207.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 79217[59:MRR:79204.2,79212.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 79218[59:Res:53.1,79213.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 79220[59:MRR:79218.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 79221[59:MRR:79179.0,79220.0] || -> until2p7(s43)*. % 76.04/76.28 79222[59:MRR:241.0,79221.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 79223[60:Spt:79222.0] || -> until2p7(s44)*. % 76.04/76.28 79224[60:MRR:539.0,79223.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 79225[61:Spt:79224.0] || -> until2p7(s45)*. % 76.04/76.28 79226[61:MRR:544.0,79225.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 79227[62:Spt:79226.0] || -> until2p7(s46)*. % 76.04/76.28 79228[62:MRR:549.0,79227.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 79229[63:Spt:79228.0] || -> until2p7(s47)*. % 76.04/76.28 79230[63:MRR:554.0,79229.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 79231[64:Spt:79230.0] || -> until2p7(s48)*. % 76.04/76.28 79232[64:MRR:559.0,79231.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 79233[65:Spt:79232.0] || -> until2p7(s49)*. % 76.04/76.28 79234[65:MRR:194.0,79233.0] || -> node4(s49)*. % 76.04/76.28 79235[65:MRR:79217.0,79234.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 79239[65:Res:53.1,79235.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 79241[65:MRR:79239.0,78381.0] || -> . % 76.04/76.28 79242[65:Spt:79241.0,79232.0,79233.0] || until2p7(s49)*+ -> . % 76.04/76.28 79243[65:Spt:79241.0,79232.1] || -> node4(s48)*. % 76.04/76.28 79244[65:MRR:78384.0,79243.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 79247[65:Res:53.1,79244.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 79250[65:Res:79247.0,61.1] always3(s48) || -> . % 76.04/76.28 79251[65:SSi:79250.0,78281.0,78387.0,78626.0,79231.0,79243.0] || -> . % 76.04/76.28 79252[64:Spt:79251.0,79230.0,79231.0] || until2p7(s48)*+ -> . % 76.04/76.28 79253[64:Spt:79251.0,79230.1] || -> node4(s47)*. % 76.04/76.28 79255[64:MRR:777.0,79253.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 79267[64:Res:53.1,79255.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 79269[65:Spt:79267.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 79271[65:Res:79269.0,61.1] always3(s47) || -> . % 76.04/76.28 79272[65:SSi:79271.0,78277.0,78280.0,78625.0,79229.0,79253.0] || -> . % 76.04/76.28 79273[65:Spt:79272.0,79267.0,79269.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 79274[65:Spt:79272.0,79267.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 79278[65:Res:79274.0,61.1] always3(s48) || -> . % 76.04/76.28 79279[65:SSi:79278.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 79280[63:Spt:79279.0,79228.0,79229.0] || until2p7(s47)*+ -> . % 76.04/76.28 79281[63:Spt:79279.0,79228.1] || -> node4(s46)*. % 76.04/76.28 79283[63:MRR:780.0,79281.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 79290[63:Res:53.1,79283.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 79295[64:Spt:79290.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 79297[64:Res:79295.0,61.1] always3(s46) || -> . % 76.04/76.28 79298[64:SSi:79297.0,78272.0,78276.0,78624.0,79227.0,79281.0] || -> . % 76.04/76.28 79299[64:Spt:79298.0,79290.0,79295.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 79300[64:Spt:79298.0,79290.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 79304[64:Res:79300.0,61.1] always3(s47) || -> . % 76.04/76.28 79305[64:SSi:79304.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 79306[62:Spt:79305.0,79226.0,79227.0] || until2p7(s46)*+ -> . % 76.04/76.28 79307[62:Spt:79305.0,79226.1] || -> node4(s45)*. % 76.04/76.28 79309[62:MRR:783.0,79307.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 79312[62:Res:53.1,79309.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 79314[63:Spt:79312.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 79316[63:Res:79314.0,61.1] always3(s45) || -> . % 76.04/76.28 79317[63:SSi:79316.0,78268.0,78271.0,78623.0,79225.0,79307.0] || -> . % 76.04/76.28 79318[63:Spt:79317.0,79312.0,79314.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 79319[63:Spt:79317.0,79312.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 79323[63:Res:79319.0,61.1] always3(s46) || -> . % 76.04/76.28 79324[63:SSi:79323.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 79325[61:Spt:79324.0,79224.0,79225.0] || until2p7(s45)*+ -> . % 76.04/76.28 79326[61:Spt:79324.0,79224.1] || -> node4(s44)*. % 76.04/76.28 79328[61:MRR:786.0,79326.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 79331[61:Res:53.1,79328.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 79333[62:Spt:79331.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 79335[62:Res:79333.0,61.1] always3(s44) || -> . % 76.04/76.28 79336[62:SSi:79335.0,78263.0,78267.0,78622.0,79223.0,79326.0] || -> . % 76.04/76.28 79337[62:Spt:79336.0,79331.0,79333.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 79338[62:Spt:79336.0,79331.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 79342[62:Res:79338.0,61.1] always3(s45) || -> . % 76.04/76.28 79343[62:SSi:79342.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 79344[60:Spt:79343.0,79222.0,79223.0] || until2p7(s44)*+ -> . % 76.04/76.28 79345[60:Spt:79343.0,79222.1] || -> node4(s43)*. % 76.04/76.28 79347[60:MRR:789.0,79345.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 79350[60:Res:53.1,79347.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 79352[60:MRR:79350.0,79212.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 79354[60:Res:79352.0,61.1] always3(s44) || -> . % 76.04/76.28 79355[60:SSi:79354.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 79356[58:Spt:79355.0,79172.0,79175.0] || trans(s49,s43)*+ -> . % 76.04/76.28 79357[58:Spt:79355.0,79172.1,79172.2,79172.3,79172.4,79172.5,79172.6,79172.7,79172.8,79172.9,79172.10,79172.11,79172.12,79172.13,79172.14,79172.15,79172.16,79172.17,79172.18,79172.19,79172.20,79172.21,79172.22,79172.23,79172.24,79172.25,79172.26,79172.27,79172.28,79172.29,79172.30,79172.31,79172.32,79172.33,79172.34,79172.35,79172.36,79172.37,79172.38,79172.39,79172.40,79172.41] || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 79359[58:MRR:79174.1,79356.0] xuntil6(s49) || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 79360[59:Spt:79357.0] || -> trans(s49,s42)*. % 76.04/76.28 79361[59:Res:79360.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s42)*. % 76.04/76.28 79363[59:Res:79360.0,60.0] || -> node2(s49,s42)*. % 76.04/76.28 79364[59:SSi:79361.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s42)*. % 76.04/76.28 79365[59:Res:79363.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 79393[59:SoR:79365.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 79395[59:SoR:79393.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)* xuntil6(s49). % 76.04/76.28 79396[59:SSi:79395.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s42,c_busy)* xuntil6(s49). % 76.04/76.28 79397[60:Spt:79396.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 79399[60:Res:79397.0,61.1] always3(s42) || -> . % 76.04/76.28 79400[60:SSi:79399.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 79401[60:Spt:79400.0,79396.1,79397.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.28 79402[60:Spt:79400.0,79396.0,79396.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 79406[60:MRR:79393.2,79401.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 79407[60:Res:53.1,79402.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 79409[60:MRR:79407.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 79410[60:MRR:79364.0,79409.0] || -> until2p7(s42)*. % 76.04/76.28 79411[60:MRR:240.0,79410.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 79412[61:Spt:79411.0] || -> until2p7(s43)*. % 76.04/76.28 79413[61:MRR:241.0,79412.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 79414[62:Spt:79413.0] || -> until2p7(s44)*. % 76.04/76.28 79415[62:MRR:539.0,79414.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 79416[63:Spt:79415.0] || -> until2p7(s45)*. % 76.04/76.28 79417[63:MRR:544.0,79416.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 79418[64:Spt:79417.0] || -> until2p7(s46)*. % 76.04/76.28 79419[64:MRR:549.0,79418.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 79420[65:Spt:79419.0] || -> until2p7(s47)*. % 76.04/76.28 79421[65:MRR:554.0,79420.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 79422[66:Spt:79421.0] || -> until2p7(s48)*. % 76.04/76.28 79423[66:MRR:559.0,79422.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 79424[67:Spt:79423.0] || -> until2p7(s49)*. % 76.04/76.28 79425[67:MRR:194.0,79424.0] || -> node4(s49)*. % 76.04/76.28 79426[67:MRR:79406.0,79425.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 79427[67:Res:53.1,79426.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 79429[67:MRR:79427.0,78381.0] || -> . % 76.04/76.28 79430[67:Spt:79429.0,79423.0,79424.0] || until2p7(s49)*+ -> . % 76.04/76.28 79431[67:Spt:79429.0,79423.1] || -> node4(s48)*. % 76.04/76.28 79432[67:MRR:78384.0,79431.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 79435[67:Res:53.1,79432.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 79438[67:Res:79435.0,61.1] always3(s48) || -> . % 76.04/76.28 79439[67:SSi:79438.0,78281.0,78387.0,78626.0,79422.0,79431.0] || -> . % 76.04/76.28 79440[66:Spt:79439.0,79421.0,79422.0] || until2p7(s48)*+ -> . % 76.04/76.28 79441[66:Spt:79439.0,79421.1] || -> node4(s47)*. % 76.04/76.28 79443[66:MRR:777.0,79441.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 79458[66:Res:53.1,79443.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 79463[67:Spt:79458.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 79465[67:Res:79463.0,61.1] always3(s47) || -> . % 76.04/76.28 79466[67:SSi:79465.0,78277.0,78280.0,78625.0,79420.0,79441.0] || -> . % 76.04/76.28 79467[67:Spt:79466.0,79458.0,79463.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 79468[67:Spt:79466.0,79458.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 79472[67:Res:79468.0,61.1] always3(s48) || -> . % 76.04/76.28 79473[67:SSi:79472.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 79474[65:Spt:79473.0,79419.0,79420.0] || until2p7(s47)*+ -> . % 76.04/76.28 79475[65:Spt:79473.0,79419.1] || -> node4(s46)*. % 76.04/76.28 79477[65:MRR:780.0,79475.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 79484[65:Res:53.1,79477.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 79486[66:Spt:79484.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 79488[66:Res:79486.0,61.1] always3(s46) || -> . % 76.04/76.28 79489[66:SSi:79488.0,78272.0,78276.0,78624.0,79418.0,79475.0] || -> . % 76.04/76.28 79490[66:Spt:79489.0,79484.0,79486.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 79491[66:Spt:79489.0,79484.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 79495[66:Res:79491.0,61.1] always3(s47) || -> . % 76.04/76.28 79496[66:SSi:79495.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 79497[64:Spt:79496.0,79417.0,79418.0] || until2p7(s46)*+ -> . % 76.04/76.28 79498[64:Spt:79496.0,79417.1] || -> node4(s45)*. % 76.04/76.28 79500[64:MRR:783.0,79498.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 79503[64:Res:53.1,79500.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 79508[65:Spt:79503.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 79510[65:Res:79508.0,61.1] always3(s45) || -> . % 76.04/76.28 79511[65:SSi:79510.0,78268.0,78271.0,78623.0,79416.0,79498.0] || -> . % 76.04/76.28 79512[65:Spt:79511.0,79503.0,79508.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 79513[65:Spt:79511.0,79503.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 79517[65:Res:79513.0,61.1] always3(s46) || -> . % 76.04/76.28 79518[65:SSi:79517.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 79519[63:Spt:79518.0,79415.0,79416.0] || until2p7(s45)*+ -> . % 76.04/76.28 79520[63:Spt:79518.0,79415.1] || -> node4(s44)*. % 76.04/76.28 79522[63:MRR:786.0,79520.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 79525[63:Res:53.1,79522.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 79527[64:Spt:79525.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 79529[64:Res:79527.0,61.1] always3(s44) || -> . % 76.04/76.28 79530[64:SSi:79529.0,78263.0,78267.0,78622.0,79414.0,79520.0] || -> . % 76.04/76.28 79531[64:Spt:79530.0,79525.0,79527.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 79532[64:Spt:79530.0,79525.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 79536[64:Res:79532.0,61.1] always3(s45) || -> . % 76.04/76.28 79537[64:SSi:79536.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 79538[62:Spt:79537.0,79413.0,79414.0] || until2p7(s44)*+ -> . % 76.04/76.28 79539[62:Spt:79537.0,79413.1] || -> node4(s43)*. % 76.04/76.28 79541[62:MRR:789.0,79539.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 79544[62:Res:53.1,79541.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 79546[63:Spt:79544.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 79548[63:Res:79546.0,61.1] always3(s43) || -> . % 76.04/76.28 79549[63:SSi:79548.0,78259.0,78262.0,78621.0,79412.0,79539.0] || -> . % 76.04/76.28 79550[63:Spt:79549.0,79544.0,79546.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 79551[63:Spt:79549.0,79544.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 79555[63:Res:79551.0,61.1] always3(s44) || -> . % 76.04/76.28 79556[63:SSi:79555.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 79557[61:Spt:79556.0,79411.0,79412.0] || until2p7(s43)*+ -> . % 76.04/76.28 79558[61:Spt:79556.0,79411.1] || -> node4(s42)*. % 76.04/76.28 79560[61:MRR:792.0,79558.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 79563[61:Res:53.1,79560.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 79565[61:MRR:79563.0,79401.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 79567[61:Res:79565.0,61.1] always3(s43) || -> . % 76.04/76.28 79568[61:SSi:79567.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 79569[59:Spt:79568.0,79357.0,79360.0] || trans(s49,s42)*+ -> . % 76.04/76.28 79570[59:Spt:79568.0,79357.1,79357.2,79357.3,79357.4,79357.5,79357.6,79357.7,79357.8,79357.9,79357.10,79357.11,79357.12,79357.13,79357.14,79357.15,79357.16,79357.17,79357.18,79357.19,79357.20,79357.21,79357.22,79357.23,79357.24,79357.25,79357.26,79357.27,79357.28,79357.29,79357.30,79357.31,79357.32,79357.33,79357.34,79357.35,79357.36,79357.37,79357.38,79357.39,79357.40] || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 79572[59:MRR:79359.1,79569.0] xuntil6(s49) || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 79573[60:Spt:79570.0] || -> trans(s49,s41)*. % 76.04/76.28 79574[60:Res:79573.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s41)*. % 76.04/76.28 79576[60:Res:79573.0,60.0] || -> node2(s49,s41)*. % 76.04/76.28 79577[60:SSi:79574.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s41)*. % 76.04/76.28 79578[60:Res:79576.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 79607[60:SoR:79578.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 79609[60:SoR:79607.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)* xuntil6(s49). % 76.04/76.28 79610[60:SSi:79609.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s41,c_busy)* xuntil6(s49). % 76.04/76.28 79611[61:Spt:79610.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 79613[61:Res:79611.0,61.1] always3(s41) || -> . % 76.04/76.28 79614[61:SSi:79613.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 79615[61:Spt:79614.0,79610.1,79611.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.04/76.28 79616[61:Spt:79614.0,79610.0,79610.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 79620[61:MRR:79607.2,79615.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 79621[61:Res:53.1,79616.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 79623[61:MRR:79621.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 79624[61:MRR:79577.0,79623.0] || -> until2p7(s41)*. % 76.04/76.28 79625[61:MRR:239.0,79624.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 79626[62:Spt:79625.0] || -> until2p7(s42)*. % 76.04/76.28 79627[62:MRR:240.0,79626.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 79628[63:Spt:79627.0] || -> until2p7(s43)*. % 76.04/76.28 79629[63:MRR:241.0,79628.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 79630[64:Spt:79629.0] || -> until2p7(s44)*. % 76.04/76.28 79631[64:MRR:539.0,79630.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 79632[65:Spt:79631.0] || -> until2p7(s45)*. % 76.04/76.28 79633[65:MRR:544.0,79632.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 79634[66:Spt:79633.0] || -> until2p7(s46)*. % 76.04/76.28 79635[66:MRR:549.0,79634.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 79636[67:Spt:79635.0] || -> until2p7(s47)*. % 76.04/76.28 79637[67:MRR:554.0,79636.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 79638[68:Spt:79637.0] || -> until2p7(s48)*. % 76.04/76.28 79639[68:MRR:559.0,79638.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 79640[69:Spt:79639.0] || -> until2p7(s49)*. % 76.04/76.28 79641[69:MRR:194.0,79640.0] || -> node4(s49)*. % 76.04/76.28 79642[69:MRR:79620.0,79641.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 79646[69:Res:53.1,79642.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 79648[69:MRR:79646.0,78381.0] || -> . % 76.04/76.28 79649[69:Spt:79648.0,79639.0,79640.0] || until2p7(s49)*+ -> . % 76.04/76.28 79650[69:Spt:79648.0,79639.1] || -> node4(s48)*. % 76.04/76.28 79651[69:MRR:78384.0,79650.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 79654[69:Res:53.1,79651.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 79657[69:Res:79654.0,61.1] always3(s48) || -> . % 76.04/76.28 79658[69:SSi:79657.0,78281.0,78387.0,78626.0,79638.0,79650.0] || -> . % 76.04/76.28 79659[68:Spt:79658.0,79637.0,79638.0] || until2p7(s48)*+ -> . % 76.04/76.28 79660[68:Spt:79658.0,79637.1] || -> node4(s47)*. % 76.04/76.28 79662[68:MRR:777.0,79660.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 79674[68:Res:53.1,79662.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 79676[69:Spt:79674.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 79678[69:Res:79676.0,61.1] always3(s47) || -> . % 76.04/76.28 79679[69:SSi:79678.0,78277.0,78280.0,78625.0,79636.0,79660.0] || -> . % 76.04/76.28 79680[69:Spt:79679.0,79674.0,79676.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 79681[69:Spt:79679.0,79674.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 79685[69:Res:79681.0,61.1] always3(s48) || -> . % 76.04/76.28 79686[69:SSi:79685.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 79687[67:Spt:79686.0,79635.0,79636.0] || until2p7(s47)*+ -> . % 76.04/76.28 79688[67:Spt:79686.0,79635.1] || -> node4(s46)*. % 76.04/76.28 79690[67:MRR:780.0,79688.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 79697[67:Res:53.1,79690.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 79702[68:Spt:79697.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 79704[68:Res:79702.0,61.1] always3(s46) || -> . % 76.04/76.28 79705[68:SSi:79704.0,78272.0,78276.0,78624.0,79634.0,79688.0] || -> . % 76.04/76.28 79706[68:Spt:79705.0,79697.0,79702.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 79707[68:Spt:79705.0,79697.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 79711[68:Res:79707.0,61.1] always3(s47) || -> . % 76.04/76.28 79712[68:SSi:79711.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 79713[66:Spt:79712.0,79633.0,79634.0] || until2p7(s46)*+ -> . % 76.04/76.28 79714[66:Spt:79712.0,79633.1] || -> node4(s45)*. % 76.04/76.28 79716[66:MRR:783.0,79714.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 79719[66:Res:53.1,79716.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 79721[67:Spt:79719.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 79723[67:Res:79721.0,61.1] always3(s45) || -> . % 76.04/76.28 79724[67:SSi:79723.0,78268.0,78271.0,78623.0,79632.0,79714.0] || -> . % 76.04/76.28 79725[67:Spt:79724.0,79719.0,79721.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 79726[67:Spt:79724.0,79719.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 79730[67:Res:79726.0,61.1] always3(s46) || -> . % 76.04/76.28 79731[67:SSi:79730.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 79732[65:Spt:79731.0,79631.0,79632.0] || until2p7(s45)*+ -> . % 76.04/76.28 79733[65:Spt:79731.0,79631.1] || -> node4(s44)*. % 76.04/76.28 79735[65:MRR:786.0,79733.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 79738[65:Res:53.1,79735.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 79740[66:Spt:79738.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 79742[66:Res:79740.0,61.1] always3(s44) || -> . % 76.04/76.28 79743[66:SSi:79742.0,78263.0,78267.0,78622.0,79630.0,79733.0] || -> . % 76.04/76.28 79744[66:Spt:79743.0,79738.0,79740.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 79745[66:Spt:79743.0,79738.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 79749[66:Res:79745.0,61.1] always3(s45) || -> . % 76.04/76.28 79750[66:SSi:79749.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 79751[64:Spt:79750.0,79629.0,79630.0] || until2p7(s44)*+ -> . % 76.04/76.28 79752[64:Spt:79750.0,79629.1] || -> node4(s43)*. % 76.04/76.28 79754[64:MRR:789.0,79752.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 79757[64:Res:53.1,79754.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 79759[65:Spt:79757.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 79761[65:Res:79759.0,61.1] always3(s43) || -> . % 76.04/76.28 79762[65:SSi:79761.0,78259.0,78262.0,78621.0,79628.0,79752.0] || -> . % 76.04/76.28 79763[65:Spt:79762.0,79757.0,79759.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 79764[65:Spt:79762.0,79757.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 79768[65:Res:79764.0,61.1] always3(s44) || -> . % 76.04/76.28 79769[65:SSi:79768.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 79770[63:Spt:79769.0,79627.0,79628.0] || until2p7(s43)*+ -> . % 76.04/76.28 79771[63:Spt:79769.0,79627.1] || -> node4(s42)*. % 76.04/76.28 79773[63:MRR:792.0,79771.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 79776[63:Res:53.1,79773.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 79781[64:Spt:79776.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 79783[64:Res:79781.0,61.1] always3(s42) || -> . % 76.04/76.28 79784[64:SSi:79783.0,78254.0,78258.0,78620.0,79626.0,79771.0] || -> . % 76.04/76.28 79785[64:Spt:79784.0,79776.0,79781.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 79786[64:Spt:79784.0,79776.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 79790[64:Res:79786.0,61.1] always3(s43) || -> . % 76.04/76.28 79791[64:SSi:79790.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 79792[62:Spt:79791.0,79625.0,79626.0] || until2p7(s42)*+ -> . % 76.04/76.28 79793[62:Spt:79791.0,79625.1] || -> node4(s41)*. % 76.04/76.28 79795[62:MRR:795.0,79793.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 79798[62:Res:53.1,79795.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 79800[62:MRR:79798.0,79615.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 79802[62:Res:79800.0,61.1] always3(s42) || -> . % 76.04/76.28 79803[62:SSi:79802.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 79804[60:Spt:79803.0,79570.0,79573.0] || trans(s49,s41)*+ -> . % 76.04/76.28 79805[60:Spt:79803.0,79570.1,79570.2,79570.3,79570.4,79570.5,79570.6,79570.7,79570.8,79570.9,79570.10,79570.11,79570.12,79570.13,79570.14,79570.15,79570.16,79570.17,79570.18,79570.19,79570.20,79570.21,79570.22,79570.23,79570.24,79570.25,79570.26,79570.27,79570.28,79570.29,79570.30,79570.31,79570.32,79570.33,79570.34,79570.35,79570.36,79570.37,79570.38,79570.39] || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 79807[60:MRR:79572.1,79804.0] xuntil6(s49) || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 79808[61:Spt:79805.0] || -> trans(s49,s40)*. % 76.04/76.28 79809[61:Res:79808.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s40)*. % 76.04/76.28 79811[61:Res:79808.0,60.0] || -> node2(s49,s40)*. % 76.04/76.28 79812[61:SSi:79809.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s40)*. % 76.04/76.28 79813[61:Res:79811.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 79846[61:SoR:79813.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 79848[61:SoR:79846.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)* xuntil6(s49). % 76.04/76.28 79849[61:SSi:79848.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s40,c_busy)* xuntil6(s49). % 76.04/76.28 79850[62:Spt:79849.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 79852[62:Res:79850.0,61.1] always3(s40) || -> . % 76.04/76.28 79853[62:SSi:79852.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 79854[62:Spt:79853.0,79849.1,79850.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.28 79855[62:Spt:79853.0,79849.0,79849.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 79859[62:MRR:79846.2,79854.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 79860[62:Res:53.1,79855.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 79862[62:MRR:79860.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 79863[62:MRR:79812.0,79862.0] || -> until2p7(s40)*. % 76.04/76.28 79864[62:MRR:238.0,79863.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 79865[63:Spt:79864.0] || -> until2p7(s41)*. % 76.04/76.28 79866[63:MRR:239.0,79865.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 79867[64:Spt:79866.0] || -> until2p7(s42)*. % 76.04/76.28 79868[64:MRR:240.0,79867.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 79869[65:Spt:79868.0] || -> until2p7(s43)*. % 76.04/76.28 79870[65:MRR:241.0,79869.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 79871[66:Spt:79870.0] || -> until2p7(s44)*. % 76.04/76.28 79872[66:MRR:539.0,79871.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 79873[67:Spt:79872.0] || -> until2p7(s45)*. % 76.04/76.28 79874[67:MRR:544.0,79873.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 79875[68:Spt:79874.0] || -> until2p7(s46)*. % 76.04/76.28 79876[68:MRR:549.0,79875.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 79877[69:Spt:79876.0] || -> until2p7(s47)*. % 76.04/76.28 79878[69:MRR:554.0,79877.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 79879[70:Spt:79878.0] || -> until2p7(s48)*. % 76.04/76.28 79880[70:MRR:559.0,79879.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 79881[71:Spt:79880.0] || -> until2p7(s49)*. % 76.04/76.28 79882[71:MRR:194.0,79881.0] || -> node4(s49)*. % 76.04/76.28 79883[71:MRR:79859.0,79882.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 79884[71:Res:53.1,79883.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 79886[71:MRR:79884.0,78381.0] || -> . % 76.04/76.28 79887[71:Spt:79886.0,79880.0,79881.0] || until2p7(s49)*+ -> . % 76.04/76.28 79888[71:Spt:79886.0,79880.1] || -> node4(s48)*. % 76.04/76.28 79889[71:MRR:78384.0,79888.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 79892[71:Res:53.1,79889.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 79895[71:Res:79892.0,61.1] always3(s48) || -> . % 76.04/76.28 79896[71:SSi:79895.0,78281.0,78387.0,78626.0,79879.0,79888.0] || -> . % 76.04/76.28 79897[70:Spt:79896.0,79878.0,79879.0] || until2p7(s48)*+ -> . % 76.04/76.28 79898[70:Spt:79896.0,79878.1] || -> node4(s47)*. % 76.04/76.28 79900[70:MRR:777.0,79898.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 79915[70:Res:53.1,79900.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 79917[71:Spt:79915.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 79919[71:Res:79917.0,61.1] always3(s47) || -> . % 76.04/76.28 79920[71:SSi:79919.0,78277.0,78280.0,78625.0,79877.0,79898.0] || -> . % 76.04/76.28 79921[71:Spt:79920.0,79915.0,79917.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 79922[71:Spt:79920.0,79915.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 79926[71:Res:79922.0,61.1] always3(s48) || -> . % 76.04/76.28 79927[71:SSi:79926.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 79928[69:Spt:79927.0,79876.0,79877.0] || until2p7(s47)*+ -> . % 76.04/76.28 79929[69:Spt:79927.0,79876.1] || -> node4(s46)*. % 76.04/76.28 79931[69:MRR:780.0,79929.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 79941[69:Res:53.1,79931.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 79943[70:Spt:79941.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 79945[70:Res:79943.0,61.1] always3(s46) || -> . % 76.04/76.28 79946[70:SSi:79945.0,78272.0,78276.0,78624.0,79875.0,79929.0] || -> . % 76.04/76.28 79947[70:Spt:79946.0,79941.0,79943.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 79948[70:Spt:79946.0,79941.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 79952[70:Res:79948.0,61.1] always3(s47) || -> . % 76.04/76.28 79953[70:SSi:79952.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 79954[68:Spt:79953.0,79874.0,79875.0] || until2p7(s46)*+ -> . % 76.04/76.28 79955[68:Spt:79953.0,79874.1] || -> node4(s45)*. % 76.04/76.28 79957[68:MRR:783.0,79955.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 79960[68:Res:53.1,79957.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 79962[69:Spt:79960.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 79964[69:Res:79962.0,61.1] always3(s45) || -> . % 76.04/76.28 79965[69:SSi:79964.0,78268.0,78271.0,78623.0,79873.0,79955.0] || -> . % 76.04/76.28 79966[69:Spt:79965.0,79960.0,79962.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 79967[69:Spt:79965.0,79960.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 79971[69:Res:79967.0,61.1] always3(s46) || -> . % 76.04/76.28 79972[69:SSi:79971.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 79973[67:Spt:79972.0,79872.0,79873.0] || until2p7(s45)*+ -> . % 76.04/76.28 79974[67:Spt:79972.0,79872.1] || -> node4(s44)*. % 76.04/76.28 79976[67:MRR:786.0,79974.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 79979[67:Res:53.1,79976.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 79981[68:Spt:79979.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 79983[68:Res:79981.0,61.1] always3(s44) || -> . % 76.04/76.28 79984[68:SSi:79983.0,78263.0,78267.0,78622.0,79871.0,79974.0] || -> . % 76.04/76.28 79985[68:Spt:79984.0,79979.0,79981.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 79986[68:Spt:79984.0,79979.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 79990[68:Res:79986.0,61.1] always3(s45) || -> . % 76.04/76.28 79991[68:SSi:79990.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 79992[66:Spt:79991.0,79870.0,79871.0] || until2p7(s44)*+ -> . % 76.04/76.28 79993[66:Spt:79991.0,79870.1] || -> node4(s43)*. % 76.04/76.28 79995[66:MRR:789.0,79993.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 79998[66:Res:53.1,79995.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 80003[67:Spt:79998.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 80005[67:Res:80003.0,61.1] always3(s43) || -> . % 76.04/76.28 80006[67:SSi:80005.0,78259.0,78262.0,78621.0,79869.0,79993.0] || -> . % 76.04/76.28 80007[67:Spt:80006.0,79998.0,80003.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 80008[67:Spt:80006.0,79998.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 80012[67:Res:80008.0,61.1] always3(s44) || -> . % 76.04/76.28 80013[67:SSi:80012.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 80014[65:Spt:80013.0,79868.0,79869.0] || until2p7(s43)*+ -> . % 76.04/76.28 80015[65:Spt:80013.0,79868.1] || -> node4(s42)*. % 76.04/76.28 80017[65:MRR:792.0,80015.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 80020[65:Res:53.1,80017.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 80022[66:Spt:80020.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 80024[66:Res:80022.0,61.1] always3(s42) || -> . % 76.04/76.28 80025[66:SSi:80024.0,78254.0,78258.0,78620.0,79867.0,80015.0] || -> . % 76.04/76.28 80026[66:Spt:80025.0,80020.0,80022.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 80027[66:Spt:80025.0,80020.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 80031[66:Res:80027.0,61.1] always3(s43) || -> . % 76.04/76.28 80032[66:SSi:80031.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 80033[64:Spt:80032.0,79866.0,79867.0] || until2p7(s42)*+ -> . % 76.04/76.28 80034[64:Spt:80032.0,79866.1] || -> node4(s41)*. % 76.04/76.28 80036[64:MRR:795.0,80034.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 80039[64:Res:53.1,80036.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 80041[65:Spt:80039.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 80043[65:Res:80041.0,61.1] always3(s41) || -> . % 76.04/76.28 80044[65:SSi:80043.0,78250.0,78253.0,78619.0,79865.0,80034.0] || -> . % 76.04/76.28 80045[65:Spt:80044.0,80039.0,80041.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 80046[65:Spt:80044.0,80039.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 80050[65:Res:80046.0,61.1] always3(s42) || -> . % 76.04/76.28 80051[65:SSi:80050.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 80052[63:Spt:80051.0,79864.0,79865.0] || until2p7(s41)*+ -> . % 76.04/76.28 80053[63:Spt:80051.0,79864.1] || -> node4(s40)*. % 76.04/76.28 80055[63:MRR:798.0,80053.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 80058[63:Res:53.1,80055.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 80060[63:MRR:80058.0,79854.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 80062[63:Res:80060.0,61.1] always3(s41) || -> . % 76.04/76.28 80063[63:SSi:80062.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 80064[61:Spt:80063.0,79805.0,79808.0] || trans(s49,s40)*+ -> . % 76.04/76.28 80065[61:Spt:80063.0,79805.1,79805.2,79805.3,79805.4,79805.5,79805.6,79805.7,79805.8,79805.9,79805.10,79805.11,79805.12,79805.13,79805.14,79805.15,79805.16,79805.17,79805.18,79805.19,79805.20,79805.21,79805.22,79805.23,79805.24,79805.25,79805.26,79805.27,79805.28,79805.29,79805.30,79805.31,79805.32,79805.33,79805.34,79805.35,79805.36,79805.37,79805.38] || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 80067[61:MRR:79807.1,80064.0] xuntil6(s49) || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 80068[62:Spt:80065.0] || -> trans(s49,s39)*. % 76.04/76.28 80069[62:Res:80068.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s39)*. % 76.04/76.28 80071[62:Res:80068.0,60.0] || -> node2(s49,s39)*. % 76.04/76.28 80072[62:SSi:80069.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s39)*. % 76.04/76.28 80073[62:Res:80071.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 80110[62:SoR:80073.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 80112[62:SoR:80110.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 76.04/76.28 80113[62:SSi:80112.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 76.04/76.28 80114[63:Spt:80113.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 80116[63:Res:80114.0,61.1] always3(s39) || -> . % 76.04/76.28 80117[63:SSi:80116.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 80118[63:Spt:80117.0,80113.1,80114.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.04/76.28 80119[63:Spt:80117.0,80113.0,80113.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 80123[63:MRR:80110.2,80118.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 80124[63:Res:53.1,80119.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 80126[63:MRR:80124.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 80127[63:MRR:80072.0,80126.0] || -> until2p7(s39)*. % 76.04/76.28 80128[63:MRR:237.0,80127.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 80129[64:Spt:80128.0] || -> until2p7(s40)*. % 76.04/76.28 80130[64:MRR:238.0,80129.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 80131[65:Spt:80130.0] || -> until2p7(s41)*. % 76.04/76.28 80132[65:MRR:239.0,80131.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 80133[66:Spt:80132.0] || -> until2p7(s42)*. % 76.04/76.28 80134[66:MRR:240.0,80133.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 80135[67:Spt:80134.0] || -> until2p7(s43)*. % 76.04/76.28 80136[67:MRR:241.0,80135.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 80137[68:Spt:80136.0] || -> until2p7(s44)*. % 76.04/76.28 80138[68:MRR:539.0,80137.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 80139[69:Spt:80138.0] || -> until2p7(s45)*. % 76.04/76.28 80140[69:MRR:544.0,80139.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 80141[70:Spt:80140.0] || -> until2p7(s46)*. % 76.04/76.28 80142[70:MRR:549.0,80141.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 80143[71:Spt:80142.0] || -> until2p7(s47)*. % 76.04/76.28 80144[71:MRR:554.0,80143.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 80145[72:Spt:80144.0] || -> until2p7(s48)*. % 76.04/76.28 80146[72:MRR:559.0,80145.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 80147[73:Spt:80146.0] || -> until2p7(s49)*. % 76.04/76.28 80148[73:MRR:194.0,80147.0] || -> node4(s49)*. % 76.04/76.28 80149[73:MRR:80123.0,80148.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 80150[73:Res:53.1,80149.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 80152[73:MRR:80150.0,78381.0] || -> . % 76.04/76.28 80153[73:Spt:80152.0,80146.0,80147.0] || until2p7(s49)*+ -> . % 76.04/76.28 80154[73:Spt:80152.0,80146.1] || -> node4(s48)*. % 76.04/76.28 80155[73:MRR:78384.0,80154.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 80158[73:Res:53.1,80155.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 80161[73:Res:80158.0,61.1] always3(s48) || -> . % 76.04/76.28 80162[73:SSi:80161.0,78281.0,78387.0,78626.0,80145.0,80154.0] || -> . % 76.04/76.28 80163[72:Spt:80162.0,80144.0,80145.0] || until2p7(s48)*+ -> . % 76.04/76.28 80164[72:Spt:80162.0,80144.1] || -> node4(s47)*. % 76.04/76.28 80166[72:MRR:777.0,80164.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 80181[72:Res:53.1,80166.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 80183[73:Spt:80181.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 80185[73:Res:80183.0,61.1] always3(s47) || -> . % 76.04/76.28 80186[73:SSi:80185.0,78277.0,78280.0,78625.0,80143.0,80164.0] || -> . % 76.04/76.28 80187[73:Spt:80186.0,80181.0,80183.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 80188[73:Spt:80186.0,80181.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 80192[73:Res:80188.0,61.1] always3(s48) || -> . % 76.04/76.28 80193[73:SSi:80192.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 80194[71:Spt:80193.0,80142.0,80143.0] || until2p7(s47)*+ -> . % 76.04/76.28 80195[71:Spt:80193.0,80142.1] || -> node4(s46)*. % 76.04/76.28 80197[71:MRR:780.0,80195.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 80207[71:Res:53.1,80197.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 80209[72:Spt:80207.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 80211[72:Res:80209.0,61.1] always3(s46) || -> . % 76.04/76.28 80212[72:SSi:80211.0,78272.0,78276.0,78624.0,80141.0,80195.0] || -> . % 76.04/76.28 80213[72:Spt:80212.0,80207.0,80209.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 80214[72:Spt:80212.0,80207.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 80218[72:Res:80214.0,61.1] always3(s47) || -> . % 76.04/76.28 80219[72:SSi:80218.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 80220[70:Spt:80219.0,80140.0,80141.0] || until2p7(s46)*+ -> . % 76.04/76.28 80221[70:Spt:80219.0,80140.1] || -> node4(s45)*. % 76.04/76.28 80223[70:MRR:783.0,80221.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 80226[70:Res:53.1,80223.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 80228[71:Spt:80226.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 80230[71:Res:80228.0,61.1] always3(s45) || -> . % 76.04/76.28 80231[71:SSi:80230.0,78268.0,78271.0,78623.0,80139.0,80221.0] || -> . % 76.04/76.28 80232[71:Spt:80231.0,80226.0,80228.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 80233[71:Spt:80231.0,80226.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 80237[71:Res:80233.0,61.1] always3(s46) || -> . % 76.04/76.28 80238[71:SSi:80237.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 80239[69:Spt:80238.0,80138.0,80139.0] || until2p7(s45)*+ -> . % 76.04/76.28 80240[69:Spt:80238.0,80138.1] || -> node4(s44)*. % 76.04/76.28 80242[69:MRR:786.0,80240.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 80245[69:Res:53.1,80242.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 80247[70:Spt:80245.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 80249[70:Res:80247.0,61.1] always3(s44) || -> . % 76.04/76.28 80250[70:SSi:80249.0,78263.0,78267.0,78622.0,80137.0,80240.0] || -> . % 76.04/76.28 80251[70:Spt:80250.0,80245.0,80247.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 80252[70:Spt:80250.0,80245.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 80256[70:Res:80252.0,61.1] always3(s45) || -> . % 76.04/76.28 80257[70:SSi:80256.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 80258[68:Spt:80257.0,80136.0,80137.0] || until2p7(s44)*+ -> . % 76.04/76.28 80259[68:Spt:80257.0,80136.1] || -> node4(s43)*. % 76.04/76.28 80261[68:MRR:789.0,80259.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 80264[68:Res:53.1,80261.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 80269[69:Spt:80264.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 80271[69:Res:80269.0,61.1] always3(s43) || -> . % 76.04/76.28 80272[69:SSi:80271.0,78259.0,78262.0,78621.0,80135.0,80259.0] || -> . % 76.04/76.28 80273[69:Spt:80272.0,80264.0,80269.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 80274[69:Spt:80272.0,80264.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 80278[69:Res:80274.0,61.1] always3(s44) || -> . % 76.04/76.28 80279[69:SSi:80278.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 80280[67:Spt:80279.0,80134.0,80135.0] || until2p7(s43)*+ -> . % 76.04/76.28 80281[67:Spt:80279.0,80134.1] || -> node4(s42)*. % 76.04/76.28 80283[67:MRR:792.0,80281.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 80286[67:Res:53.1,80283.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 80288[68:Spt:80286.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 80290[68:Res:80288.0,61.1] always3(s42) || -> . % 76.04/76.28 80291[68:SSi:80290.0,78254.0,78258.0,78620.0,80133.0,80281.0] || -> . % 76.04/76.28 80292[68:Spt:80291.0,80286.0,80288.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 80293[68:Spt:80291.0,80286.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 80297[68:Res:80293.0,61.1] always3(s43) || -> . % 76.04/76.28 80298[68:SSi:80297.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 80299[66:Spt:80298.0,80132.0,80133.0] || until2p7(s42)*+ -> . % 76.04/76.28 80300[66:Spt:80298.0,80132.1] || -> node4(s41)*. % 76.04/76.28 80302[66:MRR:795.0,80300.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 80305[66:Res:53.1,80302.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 80307[67:Spt:80305.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 80309[67:Res:80307.0,61.1] always3(s41) || -> . % 76.04/76.28 80310[67:SSi:80309.0,78250.0,78253.0,78619.0,80131.0,80300.0] || -> . % 76.04/76.28 80311[67:Spt:80310.0,80305.0,80307.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 80312[67:Spt:80310.0,80305.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 80316[67:Res:80312.0,61.1] always3(s42) || -> . % 76.04/76.28 80317[67:SSi:80316.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 80318[65:Spt:80317.0,80130.0,80131.0] || until2p7(s41)*+ -> . % 76.04/76.28 80319[65:Spt:80317.0,80130.1] || -> node4(s40)*. % 76.04/76.28 80321[65:MRR:798.0,80319.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 80324[65:Res:53.1,80321.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 80326[66:Spt:80324.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 80328[66:Res:80326.0,61.1] always3(s40) || -> . % 76.04/76.28 80329[66:SSi:80328.0,78245.0,78249.0,78618.0,80129.0,80319.0] || -> . % 76.04/76.28 80330[66:Spt:80329.0,80324.0,80326.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 80331[66:Spt:80329.0,80324.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 80335[66:Res:80331.0,61.1] always3(s41) || -> . % 76.04/76.28 80336[66:SSi:80335.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 80337[64:Spt:80336.0,80128.0,80129.0] || until2p7(s40)*+ -> . % 76.04/76.28 80338[64:Spt:80336.0,80128.1] || -> node4(s39)*. % 76.04/76.28 80340[64:MRR:801.0,80338.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 80343[64:Res:53.1,80340.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 80345[64:MRR:80343.0,80118.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 80350[64:Res:80345.0,61.1] always3(s40) || -> . % 76.04/76.28 80351[64:SSi:80350.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 80352[62:Spt:80351.0,80065.0,80068.0] || trans(s49,s39)*+ -> . % 76.04/76.28 80353[62:Spt:80351.0,80065.1,80065.2,80065.3,80065.4,80065.5,80065.6,80065.7,80065.8,80065.9,80065.10,80065.11,80065.12,80065.13,80065.14,80065.15,80065.16,80065.17,80065.18,80065.19,80065.20,80065.21,80065.22,80065.23,80065.24,80065.25,80065.26,80065.27,80065.28,80065.29,80065.30,80065.31,80065.32,80065.33,80065.34,80065.35,80065.36,80065.37] || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 80355[62:MRR:80067.1,80352.0] xuntil6(s49) || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 80356[63:Spt:80353.0] || -> trans(s49,s38)*. % 76.04/76.28 80357[63:Res:80356.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s38)*. % 76.04/76.28 80359[63:Res:80356.0,60.0] || -> node2(s49,s38)*. % 76.04/76.28 80360[63:SSi:80357.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s38)*. % 76.04/76.28 80361[63:Res:80359.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 80399[63:SoR:80361.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 80401[63:SoR:80399.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)* xuntil6(s49). % 76.04/76.28 80402[63:SSi:80401.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s38,c_busy)* xuntil6(s49). % 76.04/76.28 80403[64:Spt:80402.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 80405[64:Res:80403.0,61.1] always3(s38) || -> . % 76.04/76.28 80406[64:SSi:80405.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 80407[64:Spt:80406.0,80402.1,80403.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.28 80408[64:Spt:80406.0,80402.0,80402.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 80412[64:MRR:80399.2,80407.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 80413[64:Res:53.1,80408.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 80415[64:MRR:80413.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 80416[64:MRR:80360.0,80415.0] || -> until2p7(s38)*. % 76.04/76.28 80417[64:MRR:236.0,80416.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 80418[65:Spt:80417.0] || -> until2p7(s39)*. % 76.04/76.28 80419[65:MRR:237.0,80418.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 80420[66:Spt:80419.0] || -> until2p7(s40)*. % 76.04/76.28 80421[66:MRR:238.0,80420.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 80422[67:Spt:80421.0] || -> until2p7(s41)*. % 76.04/76.28 80423[67:MRR:239.0,80422.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 80424[68:Spt:80423.0] || -> until2p7(s42)*. % 76.04/76.28 80425[68:MRR:240.0,80424.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 80426[69:Spt:80425.0] || -> until2p7(s43)*. % 76.04/76.28 80427[69:MRR:241.0,80426.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 80428[70:Spt:80427.0] || -> until2p7(s44)*. % 76.04/76.28 80429[70:MRR:539.0,80428.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 80430[71:Spt:80429.0] || -> until2p7(s45)*. % 76.04/76.28 80431[71:MRR:544.0,80430.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 80432[72:Spt:80431.0] || -> until2p7(s46)*. % 76.04/76.28 80433[72:MRR:549.0,80432.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 80434[73:Spt:80433.0] || -> until2p7(s47)*. % 76.04/76.28 80435[73:MRR:554.0,80434.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 80436[74:Spt:80435.0] || -> until2p7(s48)*. % 76.04/76.28 80437[74:MRR:559.0,80436.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 80438[75:Spt:80437.0] || -> until2p7(s49)*. % 76.04/76.28 80439[75:MRR:194.0,80438.0] || -> node4(s49)*. % 76.04/76.28 80440[75:MRR:80412.0,80439.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 80444[75:Res:53.1,80440.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 80446[75:MRR:80444.0,78381.0] || -> . % 76.04/76.28 80447[75:Spt:80446.0,80437.0,80438.0] || until2p7(s49)*+ -> . % 76.04/76.28 80448[75:Spt:80446.0,80437.1] || -> node4(s48)*. % 76.04/76.28 80449[75:MRR:78384.0,80448.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 80452[75:Res:53.1,80449.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 80455[75:Res:80452.0,61.1] always3(s48) || -> . % 76.04/76.28 80456[75:SSi:80455.0,78281.0,78387.0,78626.0,80436.0,80448.0] || -> . % 76.04/76.28 80457[74:Spt:80456.0,80435.0,80436.0] || until2p7(s48)*+ -> . % 76.04/76.28 80458[74:Spt:80456.0,80435.1] || -> node4(s47)*. % 76.04/76.28 80460[74:MRR:777.0,80458.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 80472[74:Res:53.1,80460.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 80474[75:Spt:80472.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 80476[75:Res:80474.0,61.1] always3(s47) || -> . % 76.04/76.28 80477[75:SSi:80476.0,78277.0,78280.0,78625.0,80434.0,80458.0] || -> . % 76.04/76.28 80478[75:Spt:80477.0,80472.0,80474.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 80479[75:Spt:80477.0,80472.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 80483[75:Res:80479.0,61.1] always3(s48) || -> . % 76.04/76.28 80484[75:SSi:80483.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 80485[73:Spt:80484.0,80433.0,80434.0] || until2p7(s47)*+ -> . % 76.04/76.28 80486[73:Spt:80484.0,80433.1] || -> node4(s46)*. % 76.04/76.28 80488[73:MRR:780.0,80486.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 80495[73:Res:53.1,80488.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 80500[74:Spt:80495.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 80502[74:Res:80500.0,61.1] always3(s46) || -> . % 76.04/76.28 80503[74:SSi:80502.0,78272.0,78276.0,78624.0,80432.0,80486.0] || -> . % 76.04/76.28 80504[74:Spt:80503.0,80495.0,80500.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 80505[74:Spt:80503.0,80495.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 80509[74:Res:80505.0,61.1] always3(s47) || -> . % 76.04/76.28 80510[74:SSi:80509.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 80511[72:Spt:80510.0,80431.0,80432.0] || until2p7(s46)*+ -> . % 76.04/76.28 80512[72:Spt:80510.0,80431.1] || -> node4(s45)*. % 76.04/76.28 80514[72:MRR:783.0,80512.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 80517[72:Res:53.1,80514.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 80519[73:Spt:80517.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 80521[73:Res:80519.0,61.1] always3(s45) || -> . % 76.04/76.28 80522[73:SSi:80521.0,78268.0,78271.0,78623.0,80430.0,80512.0] || -> . % 76.04/76.28 80523[73:Spt:80522.0,80517.0,80519.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 80524[73:Spt:80522.0,80517.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 80528[73:Res:80524.0,61.1] always3(s46) || -> . % 76.04/76.28 80529[73:SSi:80528.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 80530[71:Spt:80529.0,80429.0,80430.0] || until2p7(s45)*+ -> . % 76.04/76.28 80531[71:Spt:80529.0,80429.1] || -> node4(s44)*. % 76.04/76.28 80533[71:MRR:786.0,80531.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 80536[71:Res:53.1,80533.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 80538[72:Spt:80536.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 80540[72:Res:80538.0,61.1] always3(s44) || -> . % 76.04/76.28 80541[72:SSi:80540.0,78263.0,78267.0,78622.0,80428.0,80531.0] || -> . % 76.04/76.28 80542[72:Spt:80541.0,80536.0,80538.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 80543[72:Spt:80541.0,80536.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 80547[72:Res:80543.0,61.1] always3(s45) || -> . % 76.04/76.28 80548[72:SSi:80547.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 80549[70:Spt:80548.0,80427.0,80428.0] || until2p7(s44)*+ -> . % 76.04/76.28 80550[70:Spt:80548.0,80427.1] || -> node4(s43)*. % 76.04/76.28 80552[70:MRR:789.0,80550.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 80555[70:Res:53.1,80552.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 80557[71:Spt:80555.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 80559[71:Res:80557.0,61.1] always3(s43) || -> . % 76.04/76.28 80560[71:SSi:80559.0,78259.0,78262.0,78621.0,80426.0,80550.0] || -> . % 76.04/76.28 80561[71:Spt:80560.0,80555.0,80557.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 80562[71:Spt:80560.0,80555.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 80566[71:Res:80562.0,61.1] always3(s44) || -> . % 76.04/76.28 80567[71:SSi:80566.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 80568[69:Spt:80567.0,80425.0,80426.0] || until2p7(s43)*+ -> . % 76.04/76.28 80569[69:Spt:80567.0,80425.1] || -> node4(s42)*. % 76.04/76.28 80571[69:MRR:792.0,80569.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 80574[69:Res:53.1,80571.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 80579[70:Spt:80574.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 80581[70:Res:80579.0,61.1] always3(s42) || -> . % 76.04/76.28 80582[70:SSi:80581.0,78254.0,78258.0,78620.0,80424.0,80569.0] || -> . % 76.04/76.28 80583[70:Spt:80582.0,80574.0,80579.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 80584[70:Spt:80582.0,80574.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 80588[70:Res:80584.0,61.1] always3(s43) || -> . % 76.04/76.28 80589[70:SSi:80588.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 80590[68:Spt:80589.0,80423.0,80424.0] || until2p7(s42)*+ -> . % 76.04/76.28 80591[68:Spt:80589.0,80423.1] || -> node4(s41)*. % 76.04/76.28 80593[68:MRR:795.0,80591.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 80596[68:Res:53.1,80593.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 80598[69:Spt:80596.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 80600[69:Res:80598.0,61.1] always3(s41) || -> . % 76.04/76.28 80601[69:SSi:80600.0,78250.0,78253.0,78619.0,80422.0,80591.0] || -> . % 76.04/76.28 80602[69:Spt:80601.0,80596.0,80598.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 80603[69:Spt:80601.0,80596.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 80607[69:Res:80603.0,61.1] always3(s42) || -> . % 76.04/76.28 80608[69:SSi:80607.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 80609[67:Spt:80608.0,80421.0,80422.0] || until2p7(s41)*+ -> . % 76.04/76.28 80610[67:Spt:80608.0,80421.1] || -> node4(s40)*. % 76.04/76.28 80612[67:MRR:798.0,80610.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 80615[67:Res:53.1,80612.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 80617[68:Spt:80615.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 80619[68:Res:80617.0,61.1] always3(s40) || -> . % 76.04/76.28 80620[68:SSi:80619.0,78245.0,78249.0,78618.0,80420.0,80610.0] || -> . % 76.04/76.28 80621[68:Spt:80620.0,80615.0,80617.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 80622[68:Spt:80620.0,80615.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 80626[68:Res:80622.0,61.1] always3(s41) || -> . % 76.04/76.28 80627[68:SSi:80626.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 80628[66:Spt:80627.0,80419.0,80420.0] || until2p7(s40)*+ -> . % 76.04/76.28 80629[66:Spt:80627.0,80419.1] || -> node4(s39)*. % 76.04/76.28 80631[66:MRR:801.0,80629.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 80634[66:Res:53.1,80631.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 80636[67:Spt:80634.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 80638[67:Res:80636.0,61.1] always3(s39) || -> . % 76.04/76.28 80639[67:SSi:80638.0,78241.0,78244.0,78617.0,80418.0,80629.0] || -> . % 76.04/76.28 80640[67:Spt:80639.0,80634.0,80636.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 80641[67:Spt:80639.0,80634.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 80645[67:Res:80641.0,61.1] always3(s40) || -> . % 76.04/76.28 80646[67:SSi:80645.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 80647[65:Spt:80646.0,80417.0,80418.0] || until2p7(s39)*+ -> . % 76.04/76.28 80648[65:Spt:80646.0,80417.1] || -> node4(s38)*. % 76.04/76.28 80650[65:MRR:804.0,80648.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 80653[65:Res:53.1,80650.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 80655[65:MRR:80653.0,80407.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 80660[65:Res:80655.0,61.1] always3(s39) || -> . % 76.04/76.28 80661[65:SSi:80660.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 80662[63:Spt:80661.0,80353.0,80356.0] || trans(s49,s38)*+ -> . % 76.04/76.28 80663[63:Spt:80661.0,80353.1,80353.2,80353.3,80353.4,80353.5,80353.6,80353.7,80353.8,80353.9,80353.10,80353.11,80353.12,80353.13,80353.14,80353.15,80353.16,80353.17,80353.18,80353.19,80353.20,80353.21,80353.22,80353.23,80353.24,80353.25,80353.26,80353.27,80353.28,80353.29,80353.30,80353.31,80353.32,80353.33,80353.34,80353.35,80353.36] || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 80665[63:MRR:80355.1,80662.0] xuntil6(s49) || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 80666[64:Spt:80663.0] || -> trans(s49,s37)*. % 76.04/76.28 80667[64:Res:80666.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s37)*. % 76.04/76.28 80669[64:Res:80666.0,60.0] || -> node2(s49,s37)*. % 76.04/76.28 80670[64:SSi:80667.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s37)*. % 76.04/76.28 80671[64:Res:80669.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 80713[64:SoR:80671.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 80715[64:SoR:80713.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)* xuntil6(s49). % 76.04/76.28 80716[64:SSi:80715.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s37,c_busy)* xuntil6(s49). % 76.04/76.28 80717[65:Spt:80716.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 80719[65:Res:80717.0,61.1] always3(s37) || -> . % 76.04/76.28 80720[65:SSi:80719.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 80721[65:Spt:80720.0,80716.1,80717.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.04/76.28 80722[65:Spt:80720.0,80716.0,80716.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 80726[65:MRR:80713.2,80721.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 80727[65:Res:53.1,80722.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 80729[65:MRR:80727.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 80730[65:MRR:80670.0,80729.0] || -> until2p7(s37)*. % 76.04/76.28 80731[65:MRR:235.0,80730.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 80732[66:Spt:80731.0] || -> until2p7(s38)*. % 76.04/76.28 80733[66:MRR:236.0,80732.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 80734[67:Spt:80733.0] || -> until2p7(s39)*. % 76.04/76.28 80735[67:MRR:237.0,80734.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 80736[68:Spt:80735.0] || -> until2p7(s40)*. % 76.04/76.28 80737[68:MRR:238.0,80736.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 80738[69:Spt:80737.0] || -> until2p7(s41)*. % 76.04/76.28 80739[69:MRR:239.0,80738.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 80740[70:Spt:80739.0] || -> until2p7(s42)*. % 76.04/76.28 80741[70:MRR:240.0,80740.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 80742[71:Spt:80741.0] || -> until2p7(s43)*. % 76.04/76.28 80743[71:MRR:241.0,80742.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 80744[72:Spt:80743.0] || -> until2p7(s44)*. % 76.04/76.28 80745[72:MRR:539.0,80744.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 80746[73:Spt:80745.0] || -> until2p7(s45)*. % 76.04/76.28 80747[73:MRR:544.0,80746.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 80748[74:Spt:80747.0] || -> until2p7(s46)*. % 76.04/76.28 80749[74:MRR:549.0,80748.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 80750[75:Spt:80749.0] || -> until2p7(s47)*. % 76.04/76.28 80751[75:MRR:554.0,80750.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 80752[76:Spt:80751.0] || -> until2p7(s48)*. % 76.04/76.28 80753[76:MRR:559.0,80752.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 80754[77:Spt:80753.0] || -> until2p7(s49)*. % 76.04/76.28 80755[77:MRR:194.0,80754.0] || -> node4(s49)*. % 76.04/76.28 80756[77:MRR:80726.0,80755.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 80757[77:Res:53.1,80756.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 80759[77:MRR:80757.0,78381.0] || -> . % 76.04/76.28 80760[77:Spt:80759.0,80753.0,80754.0] || until2p7(s49)*+ -> . % 76.04/76.28 80761[77:Spt:80759.0,80753.1] || -> node4(s48)*. % 76.04/76.28 80762[77:MRR:78384.0,80761.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 80765[77:Res:53.1,80762.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 80768[77:Res:80765.0,61.1] always3(s48) || -> . % 76.04/76.28 80769[77:SSi:80768.0,78281.0,78387.0,78626.0,80752.0,80761.0] || -> . % 76.04/76.28 80770[76:Spt:80769.0,80751.0,80752.0] || until2p7(s48)*+ -> . % 76.04/76.28 80771[76:Spt:80769.0,80751.1] || -> node4(s47)*. % 76.04/76.28 80773[76:MRR:777.0,80771.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 80788[76:Res:53.1,80773.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 80793[77:Spt:80788.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 80795[77:Res:80793.0,61.1] always3(s47) || -> . % 76.04/76.28 80796[77:SSi:80795.0,78277.0,78280.0,78625.0,80750.0,80771.0] || -> . % 76.04/76.28 80797[77:Spt:80796.0,80788.0,80793.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 80798[77:Spt:80796.0,80788.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 80802[77:Res:80798.0,61.1] always3(s48) || -> . % 76.04/76.28 80803[77:SSi:80802.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 80804[75:Spt:80803.0,80749.0,80750.0] || until2p7(s47)*+ -> . % 76.04/76.28 80805[75:Spt:80803.0,80749.1] || -> node4(s46)*. % 76.04/76.28 80807[75:MRR:780.0,80805.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 80814[75:Res:53.1,80807.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 80816[76:Spt:80814.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 80818[76:Res:80816.0,61.1] always3(s46) || -> . % 76.04/76.28 80819[76:SSi:80818.0,78272.0,78276.0,78624.0,80748.0,80805.0] || -> . % 76.04/76.28 80820[76:Spt:80819.0,80814.0,80816.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 80821[76:Spt:80819.0,80814.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 80825[76:Res:80821.0,61.1] always3(s47) || -> . % 76.04/76.28 80826[76:SSi:80825.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 80827[74:Spt:80826.0,80747.0,80748.0] || until2p7(s46)*+ -> . % 76.04/76.28 80828[74:Spt:80826.0,80747.1] || -> node4(s45)*. % 76.04/76.28 80830[74:MRR:783.0,80828.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 80833[74:Res:53.1,80830.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 80838[75:Spt:80833.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 80840[75:Res:80838.0,61.1] always3(s45) || -> . % 76.04/76.28 80841[75:SSi:80840.0,78268.0,78271.0,78623.0,80746.0,80828.0] || -> . % 76.04/76.28 80842[75:Spt:80841.0,80833.0,80838.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 80843[75:Spt:80841.0,80833.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 80847[75:Res:80843.0,61.1] always3(s46) || -> . % 76.04/76.28 80848[75:SSi:80847.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 80849[73:Spt:80848.0,80745.0,80746.0] || until2p7(s45)*+ -> . % 76.04/76.28 80850[73:Spt:80848.0,80745.1] || -> node4(s44)*. % 76.04/76.28 80852[73:MRR:786.0,80850.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 80855[73:Res:53.1,80852.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 80857[74:Spt:80855.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 80859[74:Res:80857.0,61.1] always3(s44) || -> . % 76.04/76.28 80860[74:SSi:80859.0,78263.0,78267.0,78622.0,80744.0,80850.0] || -> . % 76.04/76.28 80861[74:Spt:80860.0,80855.0,80857.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 80862[74:Spt:80860.0,80855.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 80866[74:Res:80862.0,61.1] always3(s45) || -> . % 76.04/76.28 80867[74:SSi:80866.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 80868[72:Spt:80867.0,80743.0,80744.0] || until2p7(s44)*+ -> . % 76.04/76.28 80869[72:Spt:80867.0,80743.1] || -> node4(s43)*. % 76.04/76.28 80871[72:MRR:789.0,80869.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 80874[72:Res:53.1,80871.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 80876[73:Spt:80874.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 80878[73:Res:80876.0,61.1] always3(s43) || -> . % 76.04/76.28 80879[73:SSi:80878.0,78259.0,78262.0,78621.0,80742.0,80869.0] || -> . % 76.04/76.28 80880[73:Spt:80879.0,80874.0,80876.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 80881[73:Spt:80879.0,80874.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 80885[73:Res:80881.0,61.1] always3(s44) || -> . % 76.04/76.28 80886[73:SSi:80885.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 80887[71:Spt:80886.0,80741.0,80742.0] || until2p7(s43)*+ -> . % 76.04/76.28 80888[71:Spt:80886.0,80741.1] || -> node4(s42)*. % 76.04/76.28 80890[71:MRR:792.0,80888.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 80893[71:Res:53.1,80890.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 80895[72:Spt:80893.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 80897[72:Res:80895.0,61.1] always3(s42) || -> . % 76.04/76.28 80898[72:SSi:80897.0,78254.0,78258.0,78620.0,80740.0,80888.0] || -> . % 76.04/76.28 80899[72:Spt:80898.0,80893.0,80895.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 80900[72:Spt:80898.0,80893.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 80904[72:Res:80900.0,61.1] always3(s43) || -> . % 76.04/76.28 80905[72:SSi:80904.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 80906[70:Spt:80905.0,80739.0,80740.0] || until2p7(s42)*+ -> . % 76.04/76.28 80907[70:Spt:80905.0,80739.1] || -> node4(s41)*. % 76.04/76.28 80909[70:MRR:795.0,80907.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 80912[70:Res:53.1,80909.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 80917[71:Spt:80912.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 80919[71:Res:80917.0,61.1] always3(s41) || -> . % 76.04/76.28 80920[71:SSi:80919.0,78250.0,78253.0,78619.0,80738.0,80907.0] || -> . % 76.04/76.28 80921[71:Spt:80920.0,80912.0,80917.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 80922[71:Spt:80920.0,80912.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 80926[71:Res:80922.0,61.1] always3(s42) || -> . % 76.04/76.28 80927[71:SSi:80926.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 80928[69:Spt:80927.0,80737.0,80738.0] || until2p7(s41)*+ -> . % 76.04/76.28 80929[69:Spt:80927.0,80737.1] || -> node4(s40)*. % 76.04/76.28 80931[69:MRR:798.0,80929.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 80934[69:Res:53.1,80931.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 80936[70:Spt:80934.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 80938[70:Res:80936.0,61.1] always3(s40) || -> . % 76.04/76.28 80939[70:SSi:80938.0,78245.0,78249.0,78618.0,80736.0,80929.0] || -> . % 76.04/76.28 80940[70:Spt:80939.0,80934.0,80936.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 80941[70:Spt:80939.0,80934.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 80945[70:Res:80941.0,61.1] always3(s41) || -> . % 76.04/76.28 80946[70:SSi:80945.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 80947[68:Spt:80946.0,80735.0,80736.0] || until2p7(s40)*+ -> . % 76.04/76.28 80948[68:Spt:80946.0,80735.1] || -> node4(s39)*. % 76.04/76.28 80950[68:MRR:801.0,80948.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 80953[68:Res:53.1,80950.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 80955[69:Spt:80953.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 80957[69:Res:80955.0,61.1] always3(s39) || -> . % 76.04/76.28 80958[69:SSi:80957.0,78241.0,78244.0,78617.0,80734.0,80948.0] || -> . % 76.04/76.28 80959[69:Spt:80958.0,80953.0,80955.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 80960[69:Spt:80958.0,80953.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 80964[69:Res:80960.0,61.1] always3(s40) || -> . % 76.04/76.28 80965[69:SSi:80964.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 80966[67:Spt:80965.0,80733.0,80734.0] || until2p7(s39)*+ -> . % 76.04/76.28 80967[67:Spt:80965.0,80733.1] || -> node4(s38)*. % 76.04/76.28 80969[67:MRR:804.0,80967.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 80972[67:Res:53.1,80969.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 80974[68:Spt:80972.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 80976[68:Res:80974.0,61.1] always3(s38) || -> . % 76.04/76.28 80977[68:SSi:80976.0,78236.0,78240.0,78616.0,80732.0,80967.0] || -> . % 76.04/76.28 80978[68:Spt:80977.0,80972.0,80974.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 80979[68:Spt:80977.0,80972.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 80983[68:Res:80979.0,61.1] always3(s39) || -> . % 76.04/76.28 80984[68:SSi:80983.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 80985[66:Spt:80984.0,80731.0,80732.0] || until2p7(s38)*+ -> . % 76.04/76.28 80986[66:Spt:80984.0,80731.1] || -> node4(s37)*. % 76.04/76.28 80988[66:MRR:807.0,80986.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 80991[66:Res:53.1,80988.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 80993[66:MRR:80991.0,80721.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 80998[66:Res:80993.0,61.1] always3(s38) || -> . % 76.04/76.28 80999[66:SSi:80998.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 81000[64:Spt:80999.0,80663.0,80666.0] || trans(s49,s37)*+ -> . % 76.04/76.28 81001[64:Spt:80999.0,80663.1,80663.2,80663.3,80663.4,80663.5,80663.6,80663.7,80663.8,80663.9,80663.10,80663.11,80663.12,80663.13,80663.14,80663.15,80663.16,80663.17,80663.18,80663.19,80663.20,80663.21,80663.22,80663.23,80663.24,80663.25,80663.26,80663.27,80663.28,80663.29,80663.30,80663.31,80663.32,80663.33,80663.34,80663.35] || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 81003[64:MRR:80665.1,81000.0] xuntil6(s49) || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 81004[65:Spt:81001.0] || -> trans(s49,s36)*. % 76.04/76.28 81005[65:Res:81004.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s36)*. % 76.04/76.28 81007[65:Res:81004.0,60.0] || -> node2(s49,s36)*. % 76.04/76.28 81008[65:SSi:81005.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s36)*. % 76.04/76.28 81009[65:Res:81007.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 81052[65:SoR:81009.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 81054[65:SoR:81052.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)* xuntil6(s49). % 76.04/76.28 81055[65:SSi:81054.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s36,c_busy)* xuntil6(s49). % 76.04/76.28 81056[66:Spt:81055.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 81058[66:Res:81056.0,61.1] always3(s36) || -> . % 76.04/76.28 81059[66:SSi:81058.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 81060[66:Spt:81059.0,81055.1,81056.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.28 81061[66:Spt:81059.0,81055.0,81055.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 81065[66:MRR:81052.2,81060.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 81066[66:Res:53.1,81061.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 81068[66:MRR:81066.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 81069[66:MRR:81008.0,81068.0] || -> until2p7(s36)*. % 76.04/76.28 81070[66:MRR:232.0,81069.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 81071[67:Spt:81070.0] || -> until2p7(s37)*. % 76.04/76.28 81072[67:MRR:235.0,81071.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 81073[68:Spt:81072.0] || -> until2p7(s38)*. % 76.04/76.28 81074[68:MRR:236.0,81073.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 81075[69:Spt:81074.0] || -> until2p7(s39)*. % 76.04/76.28 81076[69:MRR:237.0,81075.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 81077[70:Spt:81076.0] || -> until2p7(s40)*. % 76.04/76.28 81078[70:MRR:238.0,81077.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 81079[71:Spt:81078.0] || -> until2p7(s41)*. % 76.04/76.28 81080[71:MRR:239.0,81079.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 81081[72:Spt:81080.0] || -> until2p7(s42)*. % 76.04/76.28 81082[72:MRR:240.0,81081.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 81083[73:Spt:81082.0] || -> until2p7(s43)*. % 76.04/76.28 81084[73:MRR:241.0,81083.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 81085[74:Spt:81084.0] || -> until2p7(s44)*. % 76.04/76.28 81086[74:MRR:539.0,81085.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 81087[75:Spt:81086.0] || -> until2p7(s45)*. % 76.04/76.28 81088[75:MRR:544.0,81087.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 81089[76:Spt:81088.0] || -> until2p7(s46)*. % 76.04/76.28 81090[76:MRR:549.0,81089.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 81091[77:Spt:81090.0] || -> until2p7(s47)*. % 76.04/76.28 81092[77:MRR:554.0,81091.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 81093[78:Spt:81092.0] || -> until2p7(s48)*. % 76.04/76.28 81094[78:MRR:559.0,81093.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 81095[79:Spt:81094.0] || -> until2p7(s49)*. % 76.04/76.28 81096[79:MRR:194.0,81095.0] || -> node4(s49)*. % 76.04/76.28 81097[79:MRR:81065.0,81096.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 81101[79:Res:53.1,81097.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 81103[79:MRR:81101.0,78381.0] || -> . % 76.04/76.28 81104[79:Spt:81103.0,81094.0,81095.0] || until2p7(s49)*+ -> . % 76.04/76.28 81105[79:Spt:81103.0,81094.1] || -> node4(s48)*. % 76.04/76.28 81106[79:MRR:78384.0,81105.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 81109[79:Res:53.1,81106.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 81112[79:Res:81109.0,61.1] always3(s48) || -> . % 76.04/76.28 81113[79:SSi:81112.0,78281.0,78387.0,78626.0,81093.0,81105.0] || -> . % 76.04/76.28 81114[78:Spt:81113.0,81092.0,81093.0] || until2p7(s48)*+ -> . % 76.04/76.28 81115[78:Spt:81113.0,81092.1] || -> node4(s47)*. % 76.04/76.28 81117[78:MRR:777.0,81115.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 81129[78:Res:53.1,81117.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 81131[79:Spt:81129.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 81133[79:Res:81131.0,61.1] always3(s47) || -> . % 76.04/76.28 81134[79:SSi:81133.0,78277.0,78280.0,78625.0,81091.0,81115.0] || -> . % 76.04/76.28 81135[79:Spt:81134.0,81129.0,81131.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 81136[79:Spt:81134.0,81129.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 81140[79:Res:81136.0,61.1] always3(s48) || -> . % 76.04/76.28 81141[79:SSi:81140.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 81142[77:Spt:81141.0,81090.0,81091.0] || until2p7(s47)*+ -> . % 76.04/76.28 81143[77:Spt:81141.0,81090.1] || -> node4(s46)*. % 76.04/76.28 81145[77:MRR:780.0,81143.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 81152[77:Res:53.1,81145.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 81157[78:Spt:81152.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 81159[78:Res:81157.0,61.1] always3(s46) || -> . % 76.04/76.28 81160[78:SSi:81159.0,78272.0,78276.0,78624.0,81089.0,81143.0] || -> . % 76.04/76.28 81161[78:Spt:81160.0,81152.0,81157.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 81162[78:Spt:81160.0,81152.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 81166[78:Res:81162.0,61.1] always3(s47) || -> . % 76.04/76.28 81167[78:SSi:81166.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 81168[76:Spt:81167.0,81088.0,81089.0] || until2p7(s46)*+ -> . % 76.04/76.28 81169[76:Spt:81167.0,81088.1] || -> node4(s45)*. % 76.04/76.28 81171[76:MRR:783.0,81169.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 81174[76:Res:53.1,81171.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 81176[77:Spt:81174.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 81178[77:Res:81176.0,61.1] always3(s45) || -> . % 76.04/76.28 81179[77:SSi:81178.0,78268.0,78271.0,78623.0,81087.0,81169.0] || -> . % 76.04/76.28 81180[77:Spt:81179.0,81174.0,81176.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 81181[77:Spt:81179.0,81174.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 81185[77:Res:81181.0,61.1] always3(s46) || -> . % 76.04/76.28 81186[77:SSi:81185.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 81187[75:Spt:81186.0,81086.0,81087.0] || until2p7(s45)*+ -> . % 76.04/76.28 81188[75:Spt:81186.0,81086.1] || -> node4(s44)*. % 76.04/76.28 81190[75:MRR:786.0,81188.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 81193[75:Res:53.1,81190.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 81195[76:Spt:81193.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 81197[76:Res:81195.0,61.1] always3(s44) || -> . % 76.04/76.28 81198[76:SSi:81197.0,78263.0,78267.0,78622.0,81085.0,81188.0] || -> . % 76.04/76.28 81199[76:Spt:81198.0,81193.0,81195.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 81200[76:Spt:81198.0,81193.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 81204[76:Res:81200.0,61.1] always3(s45) || -> . % 76.04/76.28 81205[76:SSi:81204.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 81206[74:Spt:81205.0,81084.0,81085.0] || until2p7(s44)*+ -> . % 76.04/76.28 81207[74:Spt:81205.0,81084.1] || -> node4(s43)*. % 76.04/76.28 81209[74:MRR:789.0,81207.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 81212[74:Res:53.1,81209.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 81214[75:Spt:81212.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 81216[75:Res:81214.0,61.1] always3(s43) || -> . % 76.04/76.28 81217[75:SSi:81216.0,78259.0,78262.0,78621.0,81083.0,81207.0] || -> . % 76.04/76.28 81218[75:Spt:81217.0,81212.0,81214.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 81219[75:Spt:81217.0,81212.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 81223[75:Res:81219.0,61.1] always3(s44) || -> . % 76.04/76.28 81224[75:SSi:81223.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 81225[73:Spt:81224.0,81082.0,81083.0] || until2p7(s43)*+ -> . % 76.04/76.28 81226[73:Spt:81224.0,81082.1] || -> node4(s42)*. % 76.04/76.28 81228[73:MRR:792.0,81226.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 81231[73:Res:53.1,81228.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 81236[74:Spt:81231.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 81238[74:Res:81236.0,61.1] always3(s42) || -> . % 76.04/76.28 81239[74:SSi:81238.0,78254.0,78258.0,78620.0,81081.0,81226.0] || -> . % 76.04/76.28 81240[74:Spt:81239.0,81231.0,81236.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 81241[74:Spt:81239.0,81231.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 81245[74:Res:81241.0,61.1] always3(s43) || -> . % 76.04/76.28 81246[74:SSi:81245.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 81247[72:Spt:81246.0,81080.0,81081.0] || until2p7(s42)*+ -> . % 76.04/76.28 81248[72:Spt:81246.0,81080.1] || -> node4(s41)*. % 76.04/76.28 81250[72:MRR:795.0,81248.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 81253[72:Res:53.1,81250.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 81255[73:Spt:81253.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 81257[73:Res:81255.0,61.1] always3(s41) || -> . % 76.04/76.28 81258[73:SSi:81257.0,78250.0,78253.0,78619.0,81079.0,81248.0] || -> . % 76.04/76.28 81259[73:Spt:81258.0,81253.0,81255.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 81260[73:Spt:81258.0,81253.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 81264[73:Res:81260.0,61.1] always3(s42) || -> . % 76.04/76.28 81265[73:SSi:81264.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 81266[71:Spt:81265.0,81078.0,81079.0] || until2p7(s41)*+ -> . % 76.04/76.28 81267[71:Spt:81265.0,81078.1] || -> node4(s40)*. % 76.04/76.28 81269[71:MRR:798.0,81267.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 81272[71:Res:53.1,81269.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 81274[72:Spt:81272.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 81276[72:Res:81274.0,61.1] always3(s40) || -> . % 76.04/76.28 81277[72:SSi:81276.0,78245.0,78249.0,78618.0,81077.0,81267.0] || -> . % 76.04/76.28 81278[72:Spt:81277.0,81272.0,81274.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 81279[72:Spt:81277.0,81272.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 81283[72:Res:81279.0,61.1] always3(s41) || -> . % 76.04/76.28 81284[72:SSi:81283.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 81285[70:Spt:81284.0,81076.0,81077.0] || until2p7(s40)*+ -> . % 76.04/76.28 81286[70:Spt:81284.0,81076.1] || -> node4(s39)*. % 76.04/76.28 81288[70:MRR:801.0,81286.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 81291[70:Res:53.1,81288.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 81293[71:Spt:81291.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 81295[71:Res:81293.0,61.1] always3(s39) || -> . % 76.04/76.28 81296[71:SSi:81295.0,78241.0,78244.0,78617.0,81075.0,81286.0] || -> . % 76.04/76.28 81297[71:Spt:81296.0,81291.0,81293.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 81298[71:Spt:81296.0,81291.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 81302[71:Res:81298.0,61.1] always3(s40) || -> . % 76.04/76.28 81303[71:SSi:81302.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 81304[69:Spt:81303.0,81074.0,81075.0] || until2p7(s39)*+ -> . % 76.04/76.28 81305[69:Spt:81303.0,81074.1] || -> node4(s38)*. % 76.04/76.28 81307[69:MRR:804.0,81305.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 81310[69:Res:53.1,81307.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 81315[70:Spt:81310.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 81317[70:Res:81315.0,61.1] always3(s38) || -> . % 76.04/76.28 81318[70:SSi:81317.0,78236.0,78240.0,78616.0,81073.0,81305.0] || -> . % 76.04/76.28 81319[70:Spt:81318.0,81310.0,81315.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 81320[70:Spt:81318.0,81310.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 81324[70:Res:81320.0,61.1] always3(s39) || -> . % 76.04/76.28 81325[70:SSi:81324.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 81326[68:Spt:81325.0,81072.0,81073.0] || until2p7(s38)*+ -> . % 76.04/76.28 81327[68:Spt:81325.0,81072.1] || -> node4(s37)*. % 76.04/76.28 81329[68:MRR:807.0,81327.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 81332[68:Res:53.1,81329.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 81334[69:Spt:81332.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 81336[69:Res:81334.0,61.1] always3(s37) || -> . % 76.04/76.28 81337[69:SSi:81336.0,78232.0,78235.0,78615.0,81071.0,81327.0] || -> . % 76.04/76.28 81338[69:Spt:81337.0,81332.0,81334.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 81339[69:Spt:81337.0,81332.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 81343[69:Res:81339.0,61.1] always3(s38) || -> . % 76.04/76.28 81344[69:SSi:81343.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 81345[67:Spt:81344.0,81070.0,81071.0] || until2p7(s37)*+ -> . % 76.04/76.28 81346[67:Spt:81344.0,81070.1] || -> node4(s36)*. % 76.04/76.28 81348[67:MRR:810.0,81346.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 81351[67:Res:53.1,81348.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 81353[67:MRR:81351.0,81060.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 81355[67:Res:81353.0,61.1] always3(s37) || -> . % 76.04/76.28 81356[67:SSi:81355.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 81357[65:Spt:81356.0,81001.0,81004.0] || trans(s49,s36)*+ -> . % 76.04/76.28 81358[65:Spt:81356.0,81001.1,81001.2,81001.3,81001.4,81001.5,81001.6,81001.7,81001.8,81001.9,81001.10,81001.11,81001.12,81001.13,81001.14,81001.15,81001.16,81001.17,81001.18,81001.19,81001.20,81001.21,81001.22,81001.23,81001.24,81001.25,81001.26,81001.27,81001.28,81001.29,81001.30,81001.31,81001.32,81001.33,81001.34] || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 81360[65:MRR:81003.1,81357.0] xuntil6(s49) || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 81361[66:Spt:81358.0] || -> trans(s49,s35)*. % 76.04/76.28 81362[66:Res:81361.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s35)*. % 76.04/76.28 81364[66:Res:81361.0,60.0] || -> node2(s49,s35)*. % 76.04/76.28 81365[66:SSi:81362.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s35)*. % 76.04/76.28 81366[66:Res:81364.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 81416[66:SoR:81366.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 81418[66:SoR:81416.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 76.04/76.28 81419[66:SSi:81418.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 76.04/76.28 81420[67:Spt:81419.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 81422[67:Res:81420.0,61.1] always3(s35) || -> . % 76.04/76.28 81423[67:SSi:81422.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 81424[67:Spt:81423.0,81419.1,81420.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.04/76.28 81425[67:Spt:81423.0,81419.0,81419.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 81429[67:MRR:81416.2,81424.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 81430[67:Res:53.1,81425.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 81432[67:MRR:81430.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 81433[67:MRR:81365.0,81432.0] || -> until2p7(s35)*. % 76.04/76.28 81434[67:MRR:231.0,81433.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 81435[68:Spt:81434.0] || -> until2p7(s36)*. % 76.04/76.28 81436[68:MRR:232.0,81435.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 81437[69:Spt:81436.0] || -> until2p7(s37)*. % 76.04/76.28 81438[69:MRR:235.0,81437.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 81439[70:Spt:81438.0] || -> until2p7(s38)*. % 76.04/76.28 81440[70:MRR:236.0,81439.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 81441[71:Spt:81440.0] || -> until2p7(s39)*. % 76.04/76.28 81442[71:MRR:237.0,81441.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 81443[72:Spt:81442.0] || -> until2p7(s40)*. % 76.04/76.28 81444[72:MRR:238.0,81443.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 81445[73:Spt:81444.0] || -> until2p7(s41)*. % 76.04/76.28 81446[73:MRR:239.0,81445.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 81447[74:Spt:81446.0] || -> until2p7(s42)*. % 76.04/76.28 81448[74:MRR:240.0,81447.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 81449[75:Spt:81448.0] || -> until2p7(s43)*. % 76.04/76.28 81450[75:MRR:241.0,81449.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 81451[76:Spt:81450.0] || -> until2p7(s44)*. % 76.04/76.28 81452[76:MRR:539.0,81451.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 81453[77:Spt:81452.0] || -> until2p7(s45)*. % 76.04/76.28 81454[77:MRR:544.0,81453.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 81455[78:Spt:81454.0] || -> until2p7(s46)*. % 76.04/76.28 81456[78:MRR:549.0,81455.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 81457[79:Spt:81456.0] || -> until2p7(s47)*. % 76.04/76.28 81458[79:MRR:554.0,81457.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 81459[80:Spt:81458.0] || -> until2p7(s48)*. % 76.04/76.28 81460[80:MRR:559.0,81459.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 81461[81:Spt:81460.0] || -> until2p7(s49)*. % 76.04/76.28 81462[81:MRR:194.0,81461.0] || -> node4(s49)*. % 76.04/76.28 81463[81:MRR:81429.0,81462.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 81464[81:Res:53.1,81463.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 81466[81:MRR:81464.0,78381.0] || -> . % 76.04/76.28 81467[81:Spt:81466.0,81460.0,81461.0] || until2p7(s49)*+ -> . % 76.04/76.28 81468[81:Spt:81466.0,81460.1] || -> node4(s48)*. % 76.04/76.28 81469[81:MRR:78384.0,81468.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 81472[81:Res:53.1,81469.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 81475[81:Res:81472.0,61.1] always3(s48) || -> . % 76.04/76.28 81476[81:SSi:81475.0,78281.0,78387.0,78626.0,81459.0,81468.0] || -> . % 76.04/76.28 81477[80:Spt:81476.0,81458.0,81459.0] || until2p7(s48)*+ -> . % 76.04/76.28 81478[80:Spt:81476.0,81458.1] || -> node4(s47)*. % 76.04/76.28 81480[80:MRR:777.0,81478.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 81495[80:Res:53.1,81480.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 81497[81:Spt:81495.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 81499[81:Res:81497.0,61.1] always3(s47) || -> . % 76.04/76.28 81500[81:SSi:81499.0,78277.0,78280.0,78625.0,81457.0,81478.0] || -> . % 76.04/76.28 81501[81:Spt:81500.0,81495.0,81497.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 81502[81:Spt:81500.0,81495.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 81506[81:Res:81502.0,61.1] always3(s48) || -> . % 76.04/76.28 81507[81:SSi:81506.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 81508[79:Spt:81507.0,81456.0,81457.0] || until2p7(s47)*+ -> . % 76.04/76.28 81509[79:Spt:81507.0,81456.1] || -> node4(s46)*. % 76.04/76.28 81511[79:MRR:780.0,81509.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 81521[79:Res:53.1,81511.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 81523[80:Spt:81521.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 81525[80:Res:81523.0,61.1] always3(s46) || -> . % 76.04/76.28 81526[80:SSi:81525.0,78272.0,78276.0,78624.0,81455.0,81509.0] || -> . % 76.04/76.28 81527[80:Spt:81526.0,81521.0,81523.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 81528[80:Spt:81526.0,81521.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 81532[80:Res:81528.0,61.1] always3(s47) || -> . % 76.04/76.28 81533[80:SSi:81532.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 81534[78:Spt:81533.0,81454.0,81455.0] || until2p7(s46)*+ -> . % 76.04/76.28 81535[78:Spt:81533.0,81454.1] || -> node4(s45)*. % 76.04/76.28 81537[78:MRR:783.0,81535.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 81540[78:Res:53.1,81537.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 81542[79:Spt:81540.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 81544[79:Res:81542.0,61.1] always3(s45) || -> . % 76.04/76.28 81545[79:SSi:81544.0,78268.0,78271.0,78623.0,81453.0,81535.0] || -> . % 76.04/76.28 81546[79:Spt:81545.0,81540.0,81542.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 81547[79:Spt:81545.0,81540.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 81551[79:Res:81547.0,61.1] always3(s46) || -> . % 76.04/76.28 81552[79:SSi:81551.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 81553[77:Spt:81552.0,81452.0,81453.0] || until2p7(s45)*+ -> . % 76.04/76.28 81554[77:Spt:81552.0,81452.1] || -> node4(s44)*. % 76.04/76.28 81556[77:MRR:786.0,81554.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 81559[77:Res:53.1,81556.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 81561[78:Spt:81559.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 81563[78:Res:81561.0,61.1] always3(s44) || -> . % 76.04/76.28 81564[78:SSi:81563.0,78263.0,78267.0,78622.0,81451.0,81554.0] || -> . % 76.04/76.28 81565[78:Spt:81564.0,81559.0,81561.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 81566[78:Spt:81564.0,81559.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 81570[78:Res:81566.0,61.1] always3(s45) || -> . % 76.04/76.28 81571[78:SSi:81570.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 81572[76:Spt:81571.0,81450.0,81451.0] || until2p7(s44)*+ -> . % 76.04/76.28 81573[76:Spt:81571.0,81450.1] || -> node4(s43)*. % 76.04/76.28 81575[76:MRR:789.0,81573.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 81578[76:Res:53.1,81575.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 81583[77:Spt:81578.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 81585[77:Res:81583.0,61.1] always3(s43) || -> . % 76.04/76.28 81586[77:SSi:81585.0,78259.0,78262.0,78621.0,81449.0,81573.0] || -> . % 76.04/76.28 81587[77:Spt:81586.0,81578.0,81583.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 81588[77:Spt:81586.0,81578.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 81592[77:Res:81588.0,61.1] always3(s44) || -> . % 76.04/76.28 81593[77:SSi:81592.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 81594[75:Spt:81593.0,81448.0,81449.0] || until2p7(s43)*+ -> . % 76.04/76.28 81595[75:Spt:81593.0,81448.1] || -> node4(s42)*. % 76.04/76.28 81597[75:MRR:792.0,81595.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 81600[75:Res:53.1,81597.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 81602[76:Spt:81600.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 81604[76:Res:81602.0,61.1] always3(s42) || -> . % 76.04/76.28 81605[76:SSi:81604.0,78254.0,78258.0,78620.0,81447.0,81595.0] || -> . % 76.04/76.28 81606[76:Spt:81605.0,81600.0,81602.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 81607[76:Spt:81605.0,81600.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 81611[76:Res:81607.0,61.1] always3(s43) || -> . % 76.04/76.28 81612[76:SSi:81611.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 81613[74:Spt:81612.0,81446.0,81447.0] || until2p7(s42)*+ -> . % 76.04/76.28 81614[74:Spt:81612.0,81446.1] || -> node4(s41)*. % 76.04/76.28 81616[74:MRR:795.0,81614.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 81619[74:Res:53.1,81616.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 81621[75:Spt:81619.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 81623[75:Res:81621.0,61.1] always3(s41) || -> . % 76.04/76.28 81624[75:SSi:81623.0,78250.0,78253.0,78619.0,81445.0,81614.0] || -> . % 76.04/76.28 81625[75:Spt:81624.0,81619.0,81621.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 81626[75:Spt:81624.0,81619.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 81630[75:Res:81626.0,61.1] always3(s42) || -> . % 76.04/76.28 81631[75:SSi:81630.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 81632[73:Spt:81631.0,81444.0,81445.0] || until2p7(s41)*+ -> . % 76.04/76.28 81633[73:Spt:81631.0,81444.1] || -> node4(s40)*. % 76.04/76.28 81635[73:MRR:798.0,81633.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 81638[73:Res:53.1,81635.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 81640[74:Spt:81638.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 81642[74:Res:81640.0,61.1] always3(s40) || -> . % 76.04/76.28 81643[74:SSi:81642.0,78245.0,78249.0,78618.0,81443.0,81633.0] || -> . % 76.04/76.28 81644[74:Spt:81643.0,81638.0,81640.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 81645[74:Spt:81643.0,81638.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 81649[74:Res:81645.0,61.1] always3(s41) || -> . % 76.04/76.28 81650[74:SSi:81649.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 81651[72:Spt:81650.0,81442.0,81443.0] || until2p7(s40)*+ -> . % 76.04/76.28 81652[72:Spt:81650.0,81442.1] || -> node4(s39)*. % 76.04/76.28 81654[72:MRR:801.0,81652.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 81657[72:Res:53.1,81654.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 81662[73:Spt:81657.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 81664[73:Res:81662.0,61.1] always3(s39) || -> . % 76.04/76.28 81665[73:SSi:81664.0,78241.0,78244.0,78617.0,81441.0,81652.0] || -> . % 76.04/76.28 81666[73:Spt:81665.0,81657.0,81662.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 81667[73:Spt:81665.0,81657.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 81671[73:Res:81667.0,61.1] always3(s40) || -> . % 76.04/76.28 81672[73:SSi:81671.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 81673[71:Spt:81672.0,81440.0,81441.0] || until2p7(s39)*+ -> . % 76.04/76.28 81674[71:Spt:81672.0,81440.1] || -> node4(s38)*. % 76.04/76.28 81676[71:MRR:804.0,81674.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 81679[71:Res:53.1,81676.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 81681[72:Spt:81679.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 81683[72:Res:81681.0,61.1] always3(s38) || -> . % 76.04/76.28 81684[72:SSi:81683.0,78236.0,78240.0,78616.0,81439.0,81674.0] || -> . % 76.04/76.28 81685[72:Spt:81684.0,81679.0,81681.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 81686[72:Spt:81684.0,81679.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 81690[72:Res:81686.0,61.1] always3(s39) || -> . % 76.04/76.28 81691[72:SSi:81690.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 81692[70:Spt:81691.0,81438.0,81439.0] || until2p7(s38)*+ -> . % 76.04/76.28 81693[70:Spt:81691.0,81438.1] || -> node4(s37)*. % 76.04/76.28 81695[70:MRR:807.0,81693.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 81698[70:Res:53.1,81695.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 81700[71:Spt:81698.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 81702[71:Res:81700.0,61.1] always3(s37) || -> . % 76.04/76.28 81703[71:SSi:81702.0,78232.0,78235.0,78615.0,81437.0,81693.0] || -> . % 76.04/76.28 81704[71:Spt:81703.0,81698.0,81700.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 81705[71:Spt:81703.0,81698.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 81709[71:Res:81705.0,61.1] always3(s38) || -> . % 76.04/76.28 81710[71:SSi:81709.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 81711[69:Spt:81710.0,81436.0,81437.0] || until2p7(s37)*+ -> . % 76.04/76.28 81712[69:Spt:81710.0,81436.1] || -> node4(s36)*. % 76.04/76.28 81714[69:MRR:810.0,81712.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 81717[69:Res:53.1,81714.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 81719[70:Spt:81717.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 81721[70:Res:81719.0,61.1] always3(s36) || -> . % 76.04/76.28 81722[70:SSi:81721.0,78227.0,78231.0,78614.0,81435.0,81712.0] || -> . % 76.04/76.28 81723[70:Spt:81722.0,81717.0,81719.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 81724[70:Spt:81722.0,81717.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 81728[70:Res:81724.0,61.1] always3(s37) || -> . % 76.04/76.28 81729[70:SSi:81728.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 81730[68:Spt:81729.0,81434.0,81435.0] || until2p7(s36)*+ -> . % 76.04/76.28 81731[68:Spt:81729.0,81434.1] || -> node4(s35)*. % 76.04/76.28 81733[68:MRR:813.0,81731.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 81736[68:Res:53.1,81733.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 81738[68:MRR:81736.0,81424.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 81743[68:Res:81738.0,61.1] always3(s36) || -> . % 76.04/76.28 81744[68:SSi:81743.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 81745[66:Spt:81744.0,81358.0,81361.0] || trans(s49,s35)*+ -> . % 76.04/76.28 81746[66:Spt:81744.0,81358.1,81358.2,81358.3,81358.4,81358.5,81358.6,81358.7,81358.8,81358.9,81358.10,81358.11,81358.12,81358.13,81358.14,81358.15,81358.16,81358.17,81358.18,81358.19,81358.20,81358.21,81358.22,81358.23,81358.24,81358.25,81358.26,81358.27,81358.28,81358.29,81358.30,81358.31,81358.32,81358.33] || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 81748[66:MRR:81360.1,81745.0] xuntil6(s49) || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 81749[67:Spt:81746.0] || -> trans(s49,s34)*. % 76.04/76.28 81750[67:Res:81749.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s34)*. % 76.04/76.28 81752[67:Res:81749.0,60.0] || -> node2(s49,s34)*. % 76.04/76.28 81753[67:SSi:81750.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s34)*. % 76.04/76.28 81754[67:Res:81752.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 81805[67:SoR:81754.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 81807[67:SoR:81805.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)* xuntil6(s49). % 76.04/76.28 81808[67:SSi:81807.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s34,c_busy)* xuntil6(s49). % 76.04/76.28 81809[68:Spt:81808.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 81811[68:Res:81809.0,61.1] always3(s34) || -> . % 76.04/76.28 81812[68:SSi:81811.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.28 81813[68:Spt:81812.0,81808.1,81809.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.28 81814[68:Spt:81812.0,81808.0,81808.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 81818[68:MRR:81805.2,81813.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 81819[68:Res:53.1,81814.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 81821[68:MRR:81819.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 81822[68:MRR:81753.0,81821.0] || -> until2p7(s34)*. % 76.04/76.28 81823[68:MRR:230.0,81822.0] || -> until2p7(s35)* node4(s34). % 76.04/76.28 81824[69:Spt:81823.0] || -> until2p7(s35)*. % 76.04/76.28 81825[69:MRR:231.0,81824.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 81826[70:Spt:81825.0] || -> until2p7(s36)*. % 76.04/76.28 81827[70:MRR:232.0,81826.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 81828[71:Spt:81827.0] || -> until2p7(s37)*. % 76.04/76.28 81829[71:MRR:235.0,81828.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 81830[72:Spt:81829.0] || -> until2p7(s38)*. % 76.04/76.28 81831[72:MRR:236.0,81830.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 81832[73:Spt:81831.0] || -> until2p7(s39)*. % 76.04/76.28 81833[73:MRR:237.0,81832.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 81834[74:Spt:81833.0] || -> until2p7(s40)*. % 76.04/76.28 81835[74:MRR:238.0,81834.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 81836[75:Spt:81835.0] || -> until2p7(s41)*. % 76.04/76.28 81837[75:MRR:239.0,81836.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 81838[76:Spt:81837.0] || -> until2p7(s42)*. % 76.04/76.28 81839[76:MRR:240.0,81838.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 81840[77:Spt:81839.0] || -> until2p7(s43)*. % 76.04/76.28 81841[77:MRR:241.0,81840.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 81842[78:Spt:81841.0] || -> until2p7(s44)*. % 76.04/76.28 81843[78:MRR:539.0,81842.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 81844[79:Spt:81843.0] || -> until2p7(s45)*. % 76.04/76.28 81845[79:MRR:544.0,81844.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 81846[80:Spt:81845.0] || -> until2p7(s46)*. % 76.04/76.28 81847[80:MRR:549.0,81846.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 81848[81:Spt:81847.0] || -> until2p7(s47)*. % 76.04/76.28 81849[81:MRR:554.0,81848.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 81850[82:Spt:81849.0] || -> until2p7(s48)*. % 76.04/76.28 81851[82:MRR:559.0,81850.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 81852[83:Spt:81851.0] || -> until2p7(s49)*. % 76.04/76.28 81853[83:MRR:194.0,81852.0] || -> node4(s49)*. % 76.04/76.28 81854[83:MRR:81818.0,81853.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 81855[83:Res:53.1,81854.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 81857[83:MRR:81855.0,78381.0] || -> . % 76.04/76.28 81858[83:Spt:81857.0,81851.0,81852.0] || until2p7(s49)*+ -> . % 76.04/76.28 81859[83:Spt:81857.0,81851.1] || -> node4(s48)*. % 76.04/76.28 81860[83:MRR:78384.0,81859.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 81863[83:Res:53.1,81860.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 81866[83:Res:81863.0,61.1] always3(s48) || -> . % 76.04/76.28 81867[83:SSi:81866.0,78281.0,78387.0,78626.0,81850.0,81859.0] || -> . % 76.04/76.28 81868[82:Spt:81867.0,81849.0,81850.0] || until2p7(s48)*+ -> . % 76.04/76.28 81869[82:Spt:81867.0,81849.1] || -> node4(s47)*. % 76.04/76.28 81871[82:MRR:777.0,81869.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 81886[82:Res:53.1,81871.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 81888[83:Spt:81886.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 81890[83:Res:81888.0,61.1] always3(s47) || -> . % 76.04/76.28 81891[83:SSi:81890.0,78277.0,78280.0,78625.0,81848.0,81869.0] || -> . % 76.04/76.28 81892[83:Spt:81891.0,81886.0,81888.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 81893[83:Spt:81891.0,81886.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 81897[83:Res:81893.0,61.1] always3(s48) || -> . % 76.04/76.28 81898[83:SSi:81897.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 81899[81:Spt:81898.0,81847.0,81848.0] || until2p7(s47)*+ -> . % 76.04/76.28 81900[81:Spt:81898.0,81847.1] || -> node4(s46)*. % 76.04/76.28 81902[81:MRR:780.0,81900.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 81912[81:Res:53.1,81902.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 81914[82:Spt:81912.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 81916[82:Res:81914.0,61.1] always3(s46) || -> . % 76.04/76.28 81917[82:SSi:81916.0,78272.0,78276.0,78624.0,81846.0,81900.0] || -> . % 76.04/76.28 81918[82:Spt:81917.0,81912.0,81914.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 81919[82:Spt:81917.0,81912.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 81923[82:Res:81919.0,61.1] always3(s47) || -> . % 76.04/76.28 81924[82:SSi:81923.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 81925[80:Spt:81924.0,81845.0,81846.0] || until2p7(s46)*+ -> . % 76.04/76.28 81926[80:Spt:81924.0,81845.1] || -> node4(s45)*. % 76.04/76.28 81928[80:MRR:783.0,81926.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 81931[80:Res:53.1,81928.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 81933[81:Spt:81931.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 81935[81:Res:81933.0,61.1] always3(s45) || -> . % 76.04/76.28 81936[81:SSi:81935.0,78268.0,78271.0,78623.0,81844.0,81926.0] || -> . % 76.04/76.28 81937[81:Spt:81936.0,81931.0,81933.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 81938[81:Spt:81936.0,81931.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 81942[81:Res:81938.0,61.1] always3(s46) || -> . % 76.04/76.28 81943[81:SSi:81942.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 81944[79:Spt:81943.0,81843.0,81844.0] || until2p7(s45)*+ -> . % 76.04/76.28 81945[79:Spt:81943.0,81843.1] || -> node4(s44)*. % 76.04/76.28 81947[79:MRR:786.0,81945.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 81950[79:Res:53.1,81947.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 81952[80:Spt:81950.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 81954[80:Res:81952.0,61.1] always3(s44) || -> . % 76.04/76.28 81955[80:SSi:81954.0,78263.0,78267.0,78622.0,81842.0,81945.0] || -> . % 76.04/76.28 81956[80:Spt:81955.0,81950.0,81952.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 81957[80:Spt:81955.0,81950.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 81961[80:Res:81957.0,61.1] always3(s45) || -> . % 76.04/76.28 81962[80:SSi:81961.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 81963[78:Spt:81962.0,81841.0,81842.0] || until2p7(s44)*+ -> . % 76.04/76.28 81964[78:Spt:81962.0,81841.1] || -> node4(s43)*. % 76.04/76.28 81966[78:MRR:789.0,81964.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 81969[78:Res:53.1,81966.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 81974[79:Spt:81969.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 81976[79:Res:81974.0,61.1] always3(s43) || -> . % 76.04/76.28 81977[79:SSi:81976.0,78259.0,78262.0,78621.0,81840.0,81964.0] || -> . % 76.04/76.28 81978[79:Spt:81977.0,81969.0,81974.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 81979[79:Spt:81977.0,81969.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 81983[79:Res:81979.0,61.1] always3(s44) || -> . % 76.04/76.28 81984[79:SSi:81983.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 81985[77:Spt:81984.0,81839.0,81840.0] || until2p7(s43)*+ -> . % 76.04/76.28 81986[77:Spt:81984.0,81839.1] || -> node4(s42)*. % 76.04/76.28 81988[77:MRR:792.0,81986.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 81991[77:Res:53.1,81988.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 81993[78:Spt:81991.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 81995[78:Res:81993.0,61.1] always3(s42) || -> . % 76.04/76.28 81996[78:SSi:81995.0,78254.0,78258.0,78620.0,81838.0,81986.0] || -> . % 76.04/76.28 81997[78:Spt:81996.0,81991.0,81993.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 81998[78:Spt:81996.0,81991.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 82002[78:Res:81998.0,61.1] always3(s43) || -> . % 76.04/76.28 82003[78:SSi:82002.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 82004[76:Spt:82003.0,81837.0,81838.0] || until2p7(s42)*+ -> . % 76.04/76.28 82005[76:Spt:82003.0,81837.1] || -> node4(s41)*. % 76.04/76.28 82007[76:MRR:795.0,82005.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 82010[76:Res:53.1,82007.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 82012[77:Spt:82010.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 82014[77:Res:82012.0,61.1] always3(s41) || -> . % 76.04/76.28 82015[77:SSi:82014.0,78250.0,78253.0,78619.0,81836.0,82005.0] || -> . % 76.04/76.28 82016[77:Spt:82015.0,82010.0,82012.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 82017[77:Spt:82015.0,82010.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 82021[77:Res:82017.0,61.1] always3(s42) || -> . % 76.04/76.28 82022[77:SSi:82021.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 82023[75:Spt:82022.0,81835.0,81836.0] || until2p7(s41)*+ -> . % 76.04/76.28 82024[75:Spt:82022.0,81835.1] || -> node4(s40)*. % 76.04/76.28 82026[75:MRR:798.0,82024.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 82029[75:Res:53.1,82026.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 82031[76:Spt:82029.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 82033[76:Res:82031.0,61.1] always3(s40) || -> . % 76.04/76.28 82034[76:SSi:82033.0,78245.0,78249.0,78618.0,81834.0,82024.0] || -> . % 76.04/76.28 82035[76:Spt:82034.0,82029.0,82031.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 82036[76:Spt:82034.0,82029.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 82040[76:Res:82036.0,61.1] always3(s41) || -> . % 76.04/76.28 82041[76:SSi:82040.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 82042[74:Spt:82041.0,81833.0,81834.0] || until2p7(s40)*+ -> . % 76.04/76.28 82043[74:Spt:82041.0,81833.1] || -> node4(s39)*. % 76.04/76.28 82045[74:MRR:801.0,82043.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 82048[74:Res:53.1,82045.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 82053[75:Spt:82048.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 82055[75:Res:82053.0,61.1] always3(s39) || -> . % 76.04/76.28 82056[75:SSi:82055.0,78241.0,78244.0,78617.0,81832.0,82043.0] || -> . % 76.04/76.28 82057[75:Spt:82056.0,82048.0,82053.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 82058[75:Spt:82056.0,82048.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 82062[75:Res:82058.0,61.1] always3(s40) || -> . % 76.04/76.28 82063[75:SSi:82062.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 82064[73:Spt:82063.0,81831.0,81832.0] || until2p7(s39)*+ -> . % 76.04/76.28 82065[73:Spt:82063.0,81831.1] || -> node4(s38)*. % 76.04/76.28 82067[73:MRR:804.0,82065.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 82070[73:Res:53.1,82067.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 82072[74:Spt:82070.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 82074[74:Res:82072.0,61.1] always3(s38) || -> . % 76.04/76.28 82075[74:SSi:82074.0,78236.0,78240.0,78616.0,81830.0,82065.0] || -> . % 76.04/76.28 82076[74:Spt:82075.0,82070.0,82072.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 82077[74:Spt:82075.0,82070.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 82081[74:Res:82077.0,61.1] always3(s39) || -> . % 76.04/76.28 82082[74:SSi:82081.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 82083[72:Spt:82082.0,81829.0,81830.0] || until2p7(s38)*+ -> . % 76.04/76.28 82084[72:Spt:82082.0,81829.1] || -> node4(s37)*. % 76.04/76.28 82086[72:MRR:807.0,82084.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 82089[72:Res:53.1,82086.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 82091[73:Spt:82089.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 82093[73:Res:82091.0,61.1] always3(s37) || -> . % 76.04/76.28 82094[73:SSi:82093.0,78232.0,78235.0,78615.0,81828.0,82084.0] || -> . % 76.04/76.28 82095[73:Spt:82094.0,82089.0,82091.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 82096[73:Spt:82094.0,82089.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 82100[73:Res:82096.0,61.1] always3(s38) || -> . % 76.04/76.28 82101[73:SSi:82100.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 82102[71:Spt:82101.0,81827.0,81828.0] || until2p7(s37)*+ -> . % 76.04/76.28 82103[71:Spt:82101.0,81827.1] || -> node4(s36)*. % 76.04/76.28 82105[71:MRR:810.0,82103.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 82108[71:Res:53.1,82105.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 82110[72:Spt:82108.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 82112[72:Res:82110.0,61.1] always3(s36) || -> . % 76.04/76.28 82113[72:SSi:82112.0,78227.0,78231.0,78614.0,81826.0,82103.0] || -> . % 76.04/76.28 82114[72:Spt:82113.0,82108.0,82110.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 82115[72:Spt:82113.0,82108.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 82119[72:Res:82115.0,61.1] always3(s37) || -> . % 76.04/76.28 82120[72:SSi:82119.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 82121[70:Spt:82120.0,81825.0,81826.0] || until2p7(s36)*+ -> . % 76.04/76.28 82122[70:Spt:82120.0,81825.1] || -> node4(s35)*. % 76.04/76.28 82124[70:MRR:813.0,82122.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 82127[70:Res:53.1,82124.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 82132[71:Spt:82127.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 82134[71:Res:82132.0,61.1] always3(s35) || -> . % 76.04/76.28 82135[71:SSi:82134.0,78223.0,78226.0,78613.0,81824.0,82122.0] || -> . % 76.04/76.28 82136[71:Spt:82135.0,82127.0,82132.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.28 82137[71:Spt:82135.0,82127.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 82141[71:Res:82137.0,61.1] always3(s36) || -> . % 76.04/76.28 82142[71:SSi:82141.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 82143[69:Spt:82142.0,81823.0,81824.0] || until2p7(s35)*+ -> . % 76.04/76.28 82144[69:Spt:82142.0,81823.1] || -> node4(s34)*. % 76.04/76.28 82146[69:MRR:816.0,82144.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.28 82149[69:Res:53.1,82146.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.28 82151[69:MRR:82149.0,81813.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 82153[69:Res:82151.0,61.1] always3(s35) || -> . % 76.04/76.28 82154[69:SSi:82153.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 82155[67:Spt:82154.0,81746.0,81749.0] || trans(s49,s34)*+ -> . % 76.04/76.28 82156[67:Spt:82154.0,81746.1,81746.2,81746.3,81746.4,81746.5,81746.6,81746.7,81746.8,81746.9,81746.10,81746.11,81746.12,81746.13,81746.14,81746.15,81746.16,81746.17,81746.18,81746.19,81746.20,81746.21,81746.22,81746.23,81746.24,81746.25,81746.26,81746.27,81746.28,81746.29,81746.30,81746.31,81746.32] || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 82158[67:MRR:81748.1,82155.0] xuntil6(s49) || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 82159[68:Spt:82156.0] || -> trans(s49,s33)*. % 76.04/76.28 82160[68:Res:82159.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s33)*. % 76.04/76.28 82162[68:Res:82159.0,60.0] || -> node2(s49,s33)*. % 76.04/76.28 82163[68:SSi:82160.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s33)*. % 76.04/76.28 82164[68:Res:82162.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 82219[68:SoR:82164.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 82221[68:SoR:82219.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.04/76.28 82222[68:SSi:82221.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.04/76.28 82223[69:Spt:82222.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 82225[69:Res:82223.0,61.1] always3(s33) || -> . % 76.04/76.28 82226[69:SSi:82225.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.28 82227[69:Spt:82226.0,82222.1,82223.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.04/76.28 82228[69:Spt:82226.0,82222.0,82222.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 82232[69:MRR:82219.2,82227.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 82233[69:Res:53.1,82228.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 82235[69:MRR:82233.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 82236[69:MRR:82163.0,82235.0] || -> until2p7(s33)*. % 76.04/76.28 82237[69:MRR:229.0,82236.0] || -> until2p7(s34)* node4(s33). % 76.04/76.28 82238[70:Spt:82237.0] || -> until2p7(s34)*. % 76.04/76.28 82239[70:MRR:230.0,82238.0] || -> until2p7(s35)* node4(s34). % 76.04/76.28 82240[71:Spt:82239.0] || -> until2p7(s35)*. % 76.04/76.28 82241[71:MRR:231.0,82240.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 82242[72:Spt:82241.0] || -> until2p7(s36)*. % 76.04/76.28 82243[72:MRR:232.0,82242.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 82244[73:Spt:82243.0] || -> until2p7(s37)*. % 76.04/76.28 82245[73:MRR:235.0,82244.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 82246[74:Spt:82245.0] || -> until2p7(s38)*. % 76.04/76.28 82247[74:MRR:236.0,82246.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 82248[75:Spt:82247.0] || -> until2p7(s39)*. % 76.04/76.28 82249[75:MRR:237.0,82248.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 82250[76:Spt:82249.0] || -> until2p7(s40)*. % 76.04/76.28 82251[76:MRR:238.0,82250.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 82252[77:Spt:82251.0] || -> until2p7(s41)*. % 76.04/76.28 82253[77:MRR:239.0,82252.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 82254[78:Spt:82253.0] || -> until2p7(s42)*. % 76.04/76.28 82255[78:MRR:240.0,82254.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 82256[79:Spt:82255.0] || -> until2p7(s43)*. % 76.04/76.28 82257[79:MRR:241.0,82256.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 82258[80:Spt:82257.0] || -> until2p7(s44)*. % 76.04/76.28 82259[80:MRR:539.0,82258.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 82260[81:Spt:82259.0] || -> until2p7(s45)*. % 76.04/76.28 82261[81:MRR:544.0,82260.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 82262[82:Spt:82261.0] || -> until2p7(s46)*. % 76.04/76.28 82263[82:MRR:549.0,82262.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 82264[83:Spt:82263.0] || -> until2p7(s47)*. % 76.04/76.28 82265[83:MRR:554.0,82264.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 82266[84:Spt:82265.0] || -> until2p7(s48)*. % 76.04/76.28 82267[84:MRR:559.0,82266.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 82268[85:Spt:82267.0] || -> until2p7(s49)*. % 76.04/76.28 82269[85:MRR:194.0,82268.0] || -> node4(s49)*. % 76.04/76.28 82270[85:MRR:82232.0,82269.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 82274[85:Res:53.1,82270.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 82276[85:MRR:82274.0,78381.0] || -> . % 76.04/76.28 82277[85:Spt:82276.0,82267.0,82268.0] || until2p7(s49)*+ -> . % 76.04/76.28 82278[85:Spt:82276.0,82267.1] || -> node4(s48)*. % 76.04/76.28 82279[85:MRR:78384.0,82278.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 82282[85:Res:53.1,82279.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 82285[85:Res:82282.0,61.1] always3(s48) || -> . % 76.04/76.28 82286[85:SSi:82285.0,78281.0,78387.0,78626.0,82266.0,82278.0] || -> . % 76.04/76.28 82287[84:Spt:82286.0,82265.0,82266.0] || until2p7(s48)*+ -> . % 76.04/76.28 82288[84:Spt:82286.0,82265.1] || -> node4(s47)*. % 76.04/76.28 82290[84:MRR:777.0,82288.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 82302[84:Res:53.1,82290.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 82304[85:Spt:82302.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 82306[85:Res:82304.0,61.1] always3(s47) || -> . % 76.04/76.28 82307[85:SSi:82306.0,78277.0,78280.0,78625.0,82264.0,82288.0] || -> . % 76.04/76.28 82308[85:Spt:82307.0,82302.0,82304.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 82309[85:Spt:82307.0,82302.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 82313[85:Res:82309.0,61.1] always3(s48) || -> . % 76.04/76.28 82314[85:SSi:82313.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 82315[83:Spt:82314.0,82263.0,82264.0] || until2p7(s47)*+ -> . % 76.04/76.28 82316[83:Spt:82314.0,82263.1] || -> node4(s46)*. % 76.04/76.28 82318[83:MRR:780.0,82316.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 82325[83:Res:53.1,82318.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 82330[84:Spt:82325.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 82332[84:Res:82330.0,61.1] always3(s46) || -> . % 76.04/76.28 82333[84:SSi:82332.0,78272.0,78276.0,78624.0,82262.0,82316.0] || -> . % 76.04/76.28 82334[84:Spt:82333.0,82325.0,82330.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 82335[84:Spt:82333.0,82325.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 82339[84:Res:82335.0,61.1] always3(s47) || -> . % 76.04/76.28 82340[84:SSi:82339.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 82341[82:Spt:82340.0,82261.0,82262.0] || until2p7(s46)*+ -> . % 76.04/76.28 82342[82:Spt:82340.0,82261.1] || -> node4(s45)*. % 76.04/76.28 82344[82:MRR:783.0,82342.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 82347[82:Res:53.1,82344.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 82349[83:Spt:82347.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 82351[83:Res:82349.0,61.1] always3(s45) || -> . % 76.04/76.28 82352[83:SSi:82351.0,78268.0,78271.0,78623.0,82260.0,82342.0] || -> . % 76.04/76.28 82353[83:Spt:82352.0,82347.0,82349.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 82354[83:Spt:82352.0,82347.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 82358[83:Res:82354.0,61.1] always3(s46) || -> . % 76.04/76.28 82359[83:SSi:82358.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 82360[81:Spt:82359.0,82259.0,82260.0] || until2p7(s45)*+ -> . % 76.04/76.28 82361[81:Spt:82359.0,82259.1] || -> node4(s44)*. % 76.04/76.28 82363[81:MRR:786.0,82361.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 82366[81:Res:53.1,82363.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 82368[82:Spt:82366.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 82370[82:Res:82368.0,61.1] always3(s44) || -> . % 76.04/76.28 82371[82:SSi:82370.0,78263.0,78267.0,78622.0,82258.0,82361.0] || -> . % 76.04/76.28 82372[82:Spt:82371.0,82366.0,82368.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 82373[82:Spt:82371.0,82366.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 82377[82:Res:82373.0,61.1] always3(s45) || -> . % 76.04/76.28 82378[82:SSi:82377.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 82379[80:Spt:82378.0,82257.0,82258.0] || until2p7(s44)*+ -> . % 76.04/76.28 82380[80:Spt:82378.0,82257.1] || -> node4(s43)*. % 76.04/76.28 82382[80:MRR:789.0,82380.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 82385[80:Res:53.1,82382.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 82387[81:Spt:82385.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 82389[81:Res:82387.0,61.1] always3(s43) || -> . % 76.04/76.28 82390[81:SSi:82389.0,78259.0,78262.0,78621.0,82256.0,82380.0] || -> . % 76.04/76.28 82391[81:Spt:82390.0,82385.0,82387.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 82392[81:Spt:82390.0,82385.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 82396[81:Res:82392.0,61.1] always3(s44) || -> . % 76.04/76.28 82397[81:SSi:82396.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 82398[79:Spt:82397.0,82255.0,82256.0] || until2p7(s43)*+ -> . % 76.04/76.28 82399[79:Spt:82397.0,82255.1] || -> node4(s42)*. % 76.04/76.28 82401[79:MRR:792.0,82399.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 82404[79:Res:53.1,82401.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 82409[80:Spt:82404.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 82411[80:Res:82409.0,61.1] always3(s42) || -> . % 76.04/76.28 82412[80:SSi:82411.0,78254.0,78258.0,78620.0,82254.0,82399.0] || -> . % 76.04/76.28 82413[80:Spt:82412.0,82404.0,82409.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 82414[80:Spt:82412.0,82404.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 82418[80:Res:82414.0,61.1] always3(s43) || -> . % 76.04/76.28 82419[80:SSi:82418.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 82420[78:Spt:82419.0,82253.0,82254.0] || until2p7(s42)*+ -> . % 76.04/76.28 82421[78:Spt:82419.0,82253.1] || -> node4(s41)*. % 76.04/76.28 82423[78:MRR:795.0,82421.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 82426[78:Res:53.1,82423.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 82428[79:Spt:82426.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 82430[79:Res:82428.0,61.1] always3(s41) || -> . % 76.04/76.28 82431[79:SSi:82430.0,78250.0,78253.0,78619.0,82252.0,82421.0] || -> . % 76.04/76.28 82432[79:Spt:82431.0,82426.0,82428.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 82433[79:Spt:82431.0,82426.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 82437[79:Res:82433.0,61.1] always3(s42) || -> . % 76.04/76.28 82438[79:SSi:82437.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 82439[77:Spt:82438.0,82251.0,82252.0] || until2p7(s41)*+ -> . % 76.04/76.28 82440[77:Spt:82438.0,82251.1] || -> node4(s40)*. % 76.04/76.28 82442[77:MRR:798.0,82440.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 82445[77:Res:53.1,82442.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 82447[78:Spt:82445.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 82449[78:Res:82447.0,61.1] always3(s40) || -> . % 76.04/76.28 82450[78:SSi:82449.0,78245.0,78249.0,78618.0,82250.0,82440.0] || -> . % 76.04/76.28 82451[78:Spt:82450.0,82445.0,82447.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 82452[78:Spt:82450.0,82445.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 82456[78:Res:82452.0,61.1] always3(s41) || -> . % 76.04/76.28 82457[78:SSi:82456.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 82458[76:Spt:82457.0,82249.0,82250.0] || until2p7(s40)*+ -> . % 76.04/76.28 82459[76:Spt:82457.0,82249.1] || -> node4(s39)*. % 76.04/76.28 82461[76:MRR:801.0,82459.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 82464[76:Res:53.1,82461.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 82466[77:Spt:82464.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 82468[77:Res:82466.0,61.1] always3(s39) || -> . % 76.04/76.28 82469[77:SSi:82468.0,78241.0,78244.0,78617.0,82248.0,82459.0] || -> . % 76.04/76.28 82470[77:Spt:82469.0,82464.0,82466.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 82471[77:Spt:82469.0,82464.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 82475[77:Res:82471.0,61.1] always3(s40) || -> . % 76.04/76.28 82476[77:SSi:82475.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 82477[75:Spt:82476.0,82247.0,82248.0] || until2p7(s39)*+ -> . % 76.04/76.28 82478[75:Spt:82476.0,82247.1] || -> node4(s38)*. % 76.04/76.28 82480[75:MRR:804.0,82478.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 82483[75:Res:53.1,82480.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 82488[76:Spt:82483.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 82490[76:Res:82488.0,61.1] always3(s38) || -> . % 76.04/76.28 82491[76:SSi:82490.0,78236.0,78240.0,78616.0,82246.0,82478.0] || -> . % 76.04/76.28 82492[76:Spt:82491.0,82483.0,82488.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 82493[76:Spt:82491.0,82483.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 82497[76:Res:82493.0,61.1] always3(s39) || -> . % 76.04/76.28 82498[76:SSi:82497.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 82499[74:Spt:82498.0,82245.0,82246.0] || until2p7(s38)*+ -> . % 76.04/76.28 82500[74:Spt:82498.0,82245.1] || -> node4(s37)*. % 76.04/76.28 82502[74:MRR:807.0,82500.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 82505[74:Res:53.1,82502.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 82507[75:Spt:82505.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 82509[75:Res:82507.0,61.1] always3(s37) || -> . % 76.04/76.28 82510[75:SSi:82509.0,78232.0,78235.0,78615.0,82244.0,82500.0] || -> . % 76.04/76.28 82511[75:Spt:82510.0,82505.0,82507.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 82512[75:Spt:82510.0,82505.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 82516[75:Res:82512.0,61.1] always3(s38) || -> . % 76.04/76.28 82517[75:SSi:82516.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 82518[73:Spt:82517.0,82243.0,82244.0] || until2p7(s37)*+ -> . % 76.04/76.28 82519[73:Spt:82517.0,82243.1] || -> node4(s36)*. % 76.04/76.28 82521[73:MRR:810.0,82519.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 82524[73:Res:53.1,82521.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 82526[74:Spt:82524.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 82528[74:Res:82526.0,61.1] always3(s36) || -> . % 76.04/76.28 82529[74:SSi:82528.0,78227.0,78231.0,78614.0,82242.0,82519.0] || -> . % 76.04/76.28 82530[74:Spt:82529.0,82524.0,82526.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 82531[74:Spt:82529.0,82524.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 82535[74:Res:82531.0,61.1] always3(s37) || -> . % 76.04/76.28 82536[74:SSi:82535.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 82537[72:Spt:82536.0,82241.0,82242.0] || until2p7(s36)*+ -> . % 76.04/76.28 82538[72:Spt:82536.0,82241.1] || -> node4(s35)*. % 76.04/76.28 82540[72:MRR:813.0,82538.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 82543[72:Res:53.1,82540.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 82545[73:Spt:82543.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 82547[73:Res:82545.0,61.1] always3(s35) || -> . % 76.04/76.28 82548[73:SSi:82547.0,78223.0,78226.0,78613.0,82240.0,82538.0] || -> . % 76.04/76.28 82549[73:Spt:82548.0,82543.0,82545.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.28 82550[73:Spt:82548.0,82543.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 82554[73:Res:82550.0,61.1] always3(s36) || -> . % 76.04/76.28 82555[73:SSi:82554.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 82556[71:Spt:82555.0,82239.0,82240.0] || until2p7(s35)*+ -> . % 76.04/76.28 82557[71:Spt:82555.0,82239.1] || -> node4(s34)*. % 76.04/76.28 82559[71:MRR:816.0,82557.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.28 82562[71:Res:53.1,82559.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.28 82567[72:Spt:82562.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 82569[72:Res:82567.0,61.1] always3(s34) || -> . % 76.04/76.28 82570[72:SSi:82569.0,78218.0,78222.0,78612.0,82238.0,82557.0] || -> . % 76.04/76.28 82571[72:Spt:82570.0,82562.0,82567.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.28 82572[72:Spt:82570.0,82562.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 82576[72:Res:82572.0,61.1] always3(s35) || -> . % 76.04/76.28 82577[72:SSi:82576.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 82578[70:Spt:82577.0,82237.0,82238.0] || until2p7(s34)*+ -> . % 76.04/76.28 82579[70:Spt:82577.0,82237.1] || -> node4(s33)*. % 76.04/76.28 82581[70:MRR:819.0,82579.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.28 82584[70:Res:53.1,82581.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.28 82586[70:MRR:82584.0,82227.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 82588[70:Res:82586.0,61.1] always3(s34) || -> . % 76.04/76.28 82589[70:SSi:82588.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.28 82590[68:Spt:82589.0,82156.0,82159.0] || trans(s49,s33)*+ -> . % 76.04/76.28 82591[68:Spt:82589.0,82156.1,82156.2,82156.3,82156.4,82156.5,82156.6,82156.7,82156.8,82156.9,82156.10,82156.11,82156.12,82156.13,82156.14,82156.15,82156.16,82156.17,82156.18,82156.19,82156.20,82156.21,82156.22,82156.23,82156.24,82156.25,82156.26,82156.27,82156.28,82156.29,82156.30,82156.31] || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 82593[68:MRR:82158.1,82590.0] xuntil6(s49) || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 82594[69:Spt:82591.0] || -> trans(s49,s32)*. % 76.04/76.28 82595[69:Res:82594.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s32)*. % 76.04/76.28 82597[69:Res:82594.0,60.0] || -> node2(s49,s32)*. % 76.04/76.28 82598[69:SSi:82595.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s32)*. % 76.04/76.28 82599[69:Res:82597.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 82658[69:SoR:82599.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 82660[69:SoR:82658.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)* xuntil6(s49). % 76.04/76.28 82661[69:SSi:82660.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s32,c_busy)* xuntil6(s49). % 76.04/76.28 82662[70:Spt:82661.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 82664[70:Res:82662.0,61.1] always3(s32) || -> . % 76.04/76.28 82665[70:SSi:82664.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.28 82666[70:Spt:82665.0,82661.1,82662.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.04/76.28 82667[70:Spt:82665.0,82661.0,82661.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 82671[70:MRR:82658.2,82666.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 82672[70:Res:53.1,82667.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 82674[70:MRR:82672.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 82675[70:MRR:82598.0,82674.0] || -> until2p7(s32)*. % 76.04/76.28 82676[70:MRR:228.0,82675.0] || -> until2p7(s33)* node4(s32). % 76.04/76.28 82677[71:Spt:82676.0] || -> until2p7(s33)*. % 76.04/76.28 82678[71:MRR:229.0,82677.0] || -> until2p7(s34)* node4(s33). % 76.04/76.28 82679[72:Spt:82678.0] || -> until2p7(s34)*. % 76.04/76.28 82680[72:MRR:230.0,82679.0] || -> until2p7(s35)* node4(s34). % 76.04/76.28 82681[73:Spt:82680.0] || -> until2p7(s35)*. % 76.04/76.28 82682[73:MRR:231.0,82681.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 82683[74:Spt:82682.0] || -> until2p7(s36)*. % 76.04/76.28 82684[74:MRR:232.0,82683.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 82685[75:Spt:82684.0] || -> until2p7(s37)*. % 76.04/76.28 82686[75:MRR:235.0,82685.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 82687[76:Spt:82686.0] || -> until2p7(s38)*. % 76.04/76.28 82688[76:MRR:236.0,82687.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 82689[77:Spt:82688.0] || -> until2p7(s39)*. % 76.04/76.28 82690[77:MRR:237.0,82689.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 82691[78:Spt:82690.0] || -> until2p7(s40)*. % 76.04/76.28 82692[78:MRR:238.0,82691.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 82693[79:Spt:82692.0] || -> until2p7(s41)*. % 76.04/76.28 82694[79:MRR:239.0,82693.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 82695[80:Spt:82694.0] || -> until2p7(s42)*. % 76.04/76.28 82696[80:MRR:240.0,82695.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 82697[81:Spt:82696.0] || -> until2p7(s43)*. % 76.04/76.28 82698[81:MRR:241.0,82697.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 82699[82:Spt:82698.0] || -> until2p7(s44)*. % 76.04/76.28 82700[82:MRR:539.0,82699.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 82701[83:Spt:82700.0] || -> until2p7(s45)*. % 76.04/76.28 82702[83:MRR:544.0,82701.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 82703[84:Spt:82702.0] || -> until2p7(s46)*. % 76.04/76.28 82704[84:MRR:549.0,82703.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 82705[85:Spt:82704.0] || -> until2p7(s47)*. % 76.04/76.28 82706[85:MRR:554.0,82705.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 82707[86:Spt:82706.0] || -> until2p7(s48)*. % 76.04/76.28 82708[86:MRR:559.0,82707.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 82709[87:Spt:82708.0] || -> until2p7(s49)*. % 76.04/76.28 82710[87:MRR:194.0,82709.0] || -> node4(s49)*. % 76.04/76.28 82711[87:MRR:82671.0,82710.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 82712[87:Res:53.1,82711.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 82714[87:MRR:82712.0,78381.0] || -> . % 76.04/76.28 82715[87:Spt:82714.0,82708.0,82709.0] || until2p7(s49)*+ -> . % 76.04/76.28 82716[87:Spt:82714.0,82708.1] || -> node4(s48)*. % 76.04/76.28 82717[87:MRR:78384.0,82716.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 82720[87:Res:53.1,82717.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 82723[87:Res:82720.0,61.1] always3(s48) || -> . % 76.04/76.28 82724[87:SSi:82723.0,78281.0,78387.0,78626.0,82707.0,82716.0] || -> . % 76.04/76.28 82725[86:Spt:82724.0,82706.0,82707.0] || until2p7(s48)*+ -> . % 76.04/76.28 82726[86:Spt:82724.0,82706.1] || -> node4(s47)*. % 76.04/76.28 82728[86:MRR:777.0,82726.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 82743[86:Res:53.1,82728.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 82748[87:Spt:82743.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 82750[87:Res:82748.0,61.1] always3(s47) || -> . % 76.04/76.28 82751[87:SSi:82750.0,78277.0,78280.0,78625.0,82705.0,82726.0] || -> . % 76.04/76.28 82752[87:Spt:82751.0,82743.0,82748.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 82753[87:Spt:82751.0,82743.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 82757[87:Res:82753.0,61.1] always3(s48) || -> . % 76.04/76.28 82758[87:SSi:82757.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 82759[85:Spt:82758.0,82704.0,82705.0] || until2p7(s47)*+ -> . % 76.04/76.28 82760[85:Spt:82758.0,82704.1] || -> node4(s46)*. % 76.04/76.28 82762[85:MRR:780.0,82760.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 82769[85:Res:53.1,82762.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 82771[86:Spt:82769.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 82773[86:Res:82771.0,61.1] always3(s46) || -> . % 76.04/76.28 82774[86:SSi:82773.0,78272.0,78276.0,78624.0,82703.0,82760.0] || -> . % 76.04/76.28 82775[86:Spt:82774.0,82769.0,82771.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 82776[86:Spt:82774.0,82769.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 82780[86:Res:82776.0,61.1] always3(s47) || -> . % 76.04/76.28 82781[86:SSi:82780.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 82782[84:Spt:82781.0,82702.0,82703.0] || until2p7(s46)*+ -> . % 76.04/76.28 82783[84:Spt:82781.0,82702.1] || -> node4(s45)*. % 76.04/76.28 82785[84:MRR:783.0,82783.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 82788[84:Res:53.1,82785.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 82793[85:Spt:82788.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 82795[85:Res:82793.0,61.1] always3(s45) || -> . % 76.04/76.28 82796[85:SSi:82795.0,78268.0,78271.0,78623.0,82701.0,82783.0] || -> . % 76.04/76.28 82797[85:Spt:82796.0,82788.0,82793.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 82798[85:Spt:82796.0,82788.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 82802[85:Res:82798.0,61.1] always3(s46) || -> . % 76.04/76.28 82803[85:SSi:82802.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 82804[83:Spt:82803.0,82700.0,82701.0] || until2p7(s45)*+ -> . % 76.04/76.28 82805[83:Spt:82803.0,82700.1] || -> node4(s44)*. % 76.04/76.28 82807[83:MRR:786.0,82805.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 82810[83:Res:53.1,82807.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 82812[84:Spt:82810.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 82814[84:Res:82812.0,61.1] always3(s44) || -> . % 76.04/76.28 82815[84:SSi:82814.0,78263.0,78267.0,78622.0,82699.0,82805.0] || -> . % 76.04/76.28 82816[84:Spt:82815.0,82810.0,82812.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 82817[84:Spt:82815.0,82810.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 82821[84:Res:82817.0,61.1] always3(s45) || -> . % 76.04/76.28 82822[84:SSi:82821.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 82823[82:Spt:82822.0,82698.0,82699.0] || until2p7(s44)*+ -> . % 76.04/76.28 82824[82:Spt:82822.0,82698.1] || -> node4(s43)*. % 76.04/76.28 82826[82:MRR:789.0,82824.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 82829[82:Res:53.1,82826.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 82831[83:Spt:82829.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 82833[83:Res:82831.0,61.1] always3(s43) || -> . % 76.04/76.28 82834[83:SSi:82833.0,78259.0,78262.0,78621.0,82697.0,82824.0] || -> . % 76.04/76.28 82835[83:Spt:82834.0,82829.0,82831.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 82836[83:Spt:82834.0,82829.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 82840[83:Res:82836.0,61.1] always3(s44) || -> . % 76.04/76.28 82841[83:SSi:82840.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 82842[81:Spt:82841.0,82696.0,82697.0] || until2p7(s43)*+ -> . % 76.04/76.28 82843[81:Spt:82841.0,82696.1] || -> node4(s42)*. % 76.04/76.28 82845[81:MRR:792.0,82843.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 82848[81:Res:53.1,82845.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 82850[82:Spt:82848.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 82852[82:Res:82850.0,61.1] always3(s42) || -> . % 76.04/76.28 82853[82:SSi:82852.0,78254.0,78258.0,78620.0,82695.0,82843.0] || -> . % 76.04/76.28 82854[82:Spt:82853.0,82848.0,82850.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 82855[82:Spt:82853.0,82848.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 82859[82:Res:82855.0,61.1] always3(s43) || -> . % 76.04/76.28 82860[82:SSi:82859.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 82861[80:Spt:82860.0,82694.0,82695.0] || until2p7(s42)*+ -> . % 76.04/76.28 82862[80:Spt:82860.0,82694.1] || -> node4(s41)*. % 76.04/76.28 82864[80:MRR:795.0,82862.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 82867[80:Res:53.1,82864.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 82872[81:Spt:82867.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 82874[81:Res:82872.0,61.1] always3(s41) || -> . % 76.04/76.28 82875[81:SSi:82874.0,78250.0,78253.0,78619.0,82693.0,82862.0] || -> . % 76.04/76.28 82876[81:Spt:82875.0,82867.0,82872.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 82877[81:Spt:82875.0,82867.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 82881[81:Res:82877.0,61.1] always3(s42) || -> . % 76.04/76.28 82882[81:SSi:82881.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 82883[79:Spt:82882.0,82692.0,82693.0] || until2p7(s41)*+ -> . % 76.04/76.28 82884[79:Spt:82882.0,82692.1] || -> node4(s40)*. % 76.04/76.28 82886[79:MRR:798.0,82884.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 82889[79:Res:53.1,82886.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 82891[80:Spt:82889.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 82893[80:Res:82891.0,61.1] always3(s40) || -> . % 76.04/76.28 82894[80:SSi:82893.0,78245.0,78249.0,78618.0,82691.0,82884.0] || -> . % 76.04/76.28 82895[80:Spt:82894.0,82889.0,82891.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 82896[80:Spt:82894.0,82889.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 82900[80:Res:82896.0,61.1] always3(s41) || -> . % 76.04/76.28 82901[80:SSi:82900.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 82902[78:Spt:82901.0,82690.0,82691.0] || until2p7(s40)*+ -> . % 76.04/76.28 82903[78:Spt:82901.0,82690.1] || -> node4(s39)*. % 76.04/76.28 82905[78:MRR:801.0,82903.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 82908[78:Res:53.1,82905.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 82910[79:Spt:82908.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 82912[79:Res:82910.0,61.1] always3(s39) || -> . % 76.04/76.28 82913[79:SSi:82912.0,78241.0,78244.0,78617.0,82689.0,82903.0] || -> . % 76.04/76.28 82914[79:Spt:82913.0,82908.0,82910.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 82915[79:Spt:82913.0,82908.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 82919[79:Res:82915.0,61.1] always3(s40) || -> . % 76.04/76.28 82920[79:SSi:82919.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 82921[77:Spt:82920.0,82688.0,82689.0] || until2p7(s39)*+ -> . % 76.04/76.28 82922[77:Spt:82920.0,82688.1] || -> node4(s38)*. % 76.04/76.28 82924[77:MRR:804.0,82922.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 82927[77:Res:53.1,82924.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 82929[78:Spt:82927.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 82931[78:Res:82929.0,61.1] always3(s38) || -> . % 76.04/76.28 82932[78:SSi:82931.0,78236.0,78240.0,78616.0,82687.0,82922.0] || -> . % 76.04/76.28 82933[78:Spt:82932.0,82927.0,82929.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 82934[78:Spt:82932.0,82927.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 82938[78:Res:82934.0,61.1] always3(s39) || -> . % 76.04/76.28 82939[78:SSi:82938.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 82940[76:Spt:82939.0,82686.0,82687.0] || until2p7(s38)*+ -> . % 76.04/76.28 82941[76:Spt:82939.0,82686.1] || -> node4(s37)*. % 76.04/76.28 82943[76:MRR:807.0,82941.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 82946[76:Res:53.1,82943.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 82951[77:Spt:82946.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 82953[77:Res:82951.0,61.1] always3(s37) || -> . % 76.04/76.28 82954[77:SSi:82953.0,78232.0,78235.0,78615.0,82685.0,82941.0] || -> . % 76.04/76.28 82955[77:Spt:82954.0,82946.0,82951.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 82956[77:Spt:82954.0,82946.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 82960[77:Res:82956.0,61.1] always3(s38) || -> . % 76.04/76.28 82961[77:SSi:82960.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 82962[75:Spt:82961.0,82684.0,82685.0] || until2p7(s37)*+ -> . % 76.04/76.28 82963[75:Spt:82961.0,82684.1] || -> node4(s36)*. % 76.04/76.28 82965[75:MRR:810.0,82963.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 82968[75:Res:53.1,82965.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 82970[76:Spt:82968.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 82972[76:Res:82970.0,61.1] always3(s36) || -> . % 76.04/76.28 82973[76:SSi:82972.0,78227.0,78231.0,78614.0,82683.0,82963.0] || -> . % 76.04/76.28 82974[76:Spt:82973.0,82968.0,82970.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 82975[76:Spt:82973.0,82968.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 82979[76:Res:82975.0,61.1] always3(s37) || -> . % 76.04/76.28 82980[76:SSi:82979.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 82981[74:Spt:82980.0,82682.0,82683.0] || until2p7(s36)*+ -> . % 76.04/76.28 82982[74:Spt:82980.0,82682.1] || -> node4(s35)*. % 76.04/76.28 82984[74:MRR:813.0,82982.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 82987[74:Res:53.1,82984.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 82989[75:Spt:82987.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 82991[75:Res:82989.0,61.1] always3(s35) || -> . % 76.04/76.28 82992[75:SSi:82991.0,78223.0,78226.0,78613.0,82681.0,82982.0] || -> . % 76.04/76.28 82993[75:Spt:82992.0,82987.0,82989.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.28 82994[75:Spt:82992.0,82987.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 82998[75:Res:82994.0,61.1] always3(s36) || -> . % 76.04/76.28 82999[75:SSi:82998.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 83000[73:Spt:82999.0,82680.0,82681.0] || until2p7(s35)*+ -> . % 76.04/76.28 83001[73:Spt:82999.0,82680.1] || -> node4(s34)*. % 76.04/76.28 83003[73:MRR:816.0,83001.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.28 83006[73:Res:53.1,83003.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.28 83008[74:Spt:83006.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 83010[74:Res:83008.0,61.1] always3(s34) || -> . % 76.04/76.28 83011[74:SSi:83010.0,78218.0,78222.0,78612.0,82679.0,83001.0] || -> . % 76.04/76.28 83012[74:Spt:83011.0,83006.0,83008.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.28 83013[74:Spt:83011.0,83006.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 83017[74:Res:83013.0,61.1] always3(s35) || -> . % 76.04/76.28 83018[74:SSi:83017.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 83019[72:Spt:83018.0,82678.0,82679.0] || until2p7(s34)*+ -> . % 76.04/76.28 83020[72:Spt:83018.0,82678.1] || -> node4(s33)*. % 76.04/76.28 83022[72:MRR:819.0,83020.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.28 83025[72:Res:53.1,83022.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.28 83030[73:Spt:83025.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 83032[73:Res:83030.0,61.1] always3(s33) || -> . % 76.04/76.28 83033[73:SSi:83032.0,78214.0,78217.0,78611.0,82677.0,83020.0] || -> . % 76.04/76.28 83034[73:Spt:83033.0,83025.0,83030.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.28 83035[73:Spt:83033.0,83025.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 83039[73:Res:83035.0,61.1] always3(s34) || -> . % 76.04/76.28 83040[73:SSi:83039.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.28 83041[71:Spt:83040.0,82676.0,82677.0] || until2p7(s33)*+ -> . % 76.04/76.28 83042[71:Spt:83040.0,82676.1] || -> node4(s32)*. % 76.04/76.28 83044[71:MRR:822.0,83042.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.28 83047[71:Res:53.1,83044.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.28 83049[71:MRR:83047.0,82666.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 83051[71:Res:83049.0,61.1] always3(s33) || -> . % 76.04/76.28 83052[71:SSi:83051.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.28 83053[69:Spt:83052.0,82591.0,82594.0] || trans(s49,s32)*+ -> . % 76.04/76.28 83054[69:Spt:83052.0,82591.1,82591.2,82591.3,82591.4,82591.5,82591.6,82591.7,82591.8,82591.9,82591.10,82591.11,82591.12,82591.13,82591.14,82591.15,82591.16,82591.17,82591.18,82591.19,82591.20,82591.21,82591.22,82591.23,82591.24,82591.25,82591.26,82591.27,82591.28,82591.29,82591.30] || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 83056[69:MRR:82593.1,83053.0] xuntil6(s49) || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 83057[70:Spt:83054.0] || -> trans(s49,s31)*. % 76.04/76.28 83058[70:Res:83057.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s31)*. % 76.04/76.28 83060[70:Res:83057.0,60.0] || -> node2(s49,s31)*. % 76.04/76.28 83061[70:SSi:83058.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s31)*. % 76.04/76.28 83062[70:Res:83060.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 83122[70:SoR:83062.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 83124[70:SoR:83122.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.04/76.28 83125[70:SSi:83124.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.04/76.28 83126[71:Spt:83125.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 83128[71:Res:83126.0,61.1] always3(s31) || -> . % 76.04/76.28 83129[71:SSi:83128.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.28 83130[71:Spt:83129.0,83125.1,83126.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.04/76.28 83131[71:Spt:83129.0,83125.0,83125.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 83135[71:MRR:83122.2,83130.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 83136[71:Res:53.1,83131.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 83138[71:MRR:83136.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 83139[71:MRR:83061.0,83138.0] || -> until2p7(s31)*. % 76.04/76.28 83140[71:MRR:227.0,83139.0] || -> until2p7(s32)* node4(s31). % 76.04/76.28 83141[72:Spt:83140.0] || -> until2p7(s32)*. % 76.04/76.28 83142[72:MRR:228.0,83141.0] || -> until2p7(s33)* node4(s32). % 76.04/76.28 83143[73:Spt:83142.0] || -> until2p7(s33)*. % 76.04/76.28 83144[73:MRR:229.0,83143.0] || -> until2p7(s34)* node4(s33). % 76.04/76.28 83145[74:Spt:83144.0] || -> until2p7(s34)*. % 76.04/76.28 83146[74:MRR:230.0,83145.0] || -> until2p7(s35)* node4(s34). % 76.04/76.28 83147[75:Spt:83146.0] || -> until2p7(s35)*. % 76.04/76.28 83148[75:MRR:231.0,83147.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 83149[76:Spt:83148.0] || -> until2p7(s36)*. % 76.04/76.28 83150[76:MRR:232.0,83149.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 83151[77:Spt:83150.0] || -> until2p7(s37)*. % 76.04/76.28 83152[77:MRR:235.0,83151.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 83153[78:Spt:83152.0] || -> until2p7(s38)*. % 76.04/76.28 83154[78:MRR:236.0,83153.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 83155[79:Spt:83154.0] || -> until2p7(s39)*. % 76.04/76.28 83156[79:MRR:237.0,83155.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 83157[80:Spt:83156.0] || -> until2p7(s40)*. % 76.04/76.28 83158[80:MRR:238.0,83157.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 83159[81:Spt:83158.0] || -> until2p7(s41)*. % 76.04/76.28 83160[81:MRR:239.0,83159.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 83161[82:Spt:83160.0] || -> until2p7(s42)*. % 76.04/76.28 83162[82:MRR:240.0,83161.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 83163[83:Spt:83162.0] || -> until2p7(s43)*. % 76.04/76.28 83164[83:MRR:241.0,83163.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 83165[84:Spt:83164.0] || -> until2p7(s44)*. % 76.04/76.28 83166[84:MRR:539.0,83165.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 83167[85:Spt:83166.0] || -> until2p7(s45)*. % 76.04/76.28 83168[85:MRR:544.0,83167.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 83169[86:Spt:83168.0] || -> until2p7(s46)*. % 76.04/76.28 83170[86:MRR:549.0,83169.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 83171[87:Spt:83170.0] || -> until2p7(s47)*. % 76.04/76.28 83172[87:MRR:554.0,83171.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 83173[88:Spt:83172.0] || -> until2p7(s48)*. % 76.04/76.28 83174[88:MRR:559.0,83173.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 83175[89:Spt:83174.0] || -> until2p7(s49)*. % 76.04/76.28 83176[89:MRR:194.0,83175.0] || -> node4(s49)*. % 76.04/76.28 83177[89:MRR:83135.0,83176.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 83181[89:Res:53.1,83177.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 83183[89:MRR:83181.0,78381.0] || -> . % 76.04/76.28 83184[89:Spt:83183.0,83174.0,83175.0] || until2p7(s49)*+ -> . % 76.04/76.28 83185[89:Spt:83183.0,83174.1] || -> node4(s48)*. % 76.04/76.28 83186[89:MRR:78384.0,83185.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 83189[89:Res:53.1,83186.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 83192[89:Res:83189.0,61.1] always3(s48) || -> . % 76.04/76.28 83193[89:SSi:83192.0,78281.0,78387.0,78626.0,83173.0,83185.0] || -> . % 76.04/76.28 83194[88:Spt:83193.0,83172.0,83173.0] || until2p7(s48)*+ -> . % 76.04/76.28 83195[88:Spt:83193.0,83172.1] || -> node4(s47)*. % 76.04/76.28 83197[88:MRR:777.0,83195.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 83209[88:Res:53.1,83197.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 83211[89:Spt:83209.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 83213[89:Res:83211.0,61.1] always3(s47) || -> . % 76.04/76.28 83214[89:SSi:83213.0,78277.0,78280.0,78625.0,83171.0,83195.0] || -> . % 76.04/76.28 83215[89:Spt:83214.0,83209.0,83211.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 83216[89:Spt:83214.0,83209.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 83220[89:Res:83216.0,61.1] always3(s48) || -> . % 76.04/76.28 83221[89:SSi:83220.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 83222[87:Spt:83221.0,83170.0,83171.0] || until2p7(s47)*+ -> . % 76.04/76.28 83223[87:Spt:83221.0,83170.1] || -> node4(s46)*. % 76.04/76.28 83225[87:MRR:780.0,83223.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 83232[87:Res:53.1,83225.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 83237[88:Spt:83232.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 83239[88:Res:83237.0,61.1] always3(s46) || -> . % 76.04/76.28 83240[88:SSi:83239.0,78272.0,78276.0,78624.0,83169.0,83223.0] || -> . % 76.04/76.28 83241[88:Spt:83240.0,83232.0,83237.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 83242[88:Spt:83240.0,83232.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 83246[88:Res:83242.0,61.1] always3(s47) || -> . % 76.04/76.28 83247[88:SSi:83246.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 83248[86:Spt:83247.0,83168.0,83169.0] || until2p7(s46)*+ -> . % 76.04/76.28 83249[86:Spt:83247.0,83168.1] || -> node4(s45)*. % 76.04/76.28 83251[86:MRR:783.0,83249.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 83254[86:Res:53.1,83251.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 83256[87:Spt:83254.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 83258[87:Res:83256.0,61.1] always3(s45) || -> . % 76.04/76.28 83259[87:SSi:83258.0,78268.0,78271.0,78623.0,83167.0,83249.0] || -> . % 76.04/76.28 83260[87:Spt:83259.0,83254.0,83256.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 83261[87:Spt:83259.0,83254.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 83265[87:Res:83261.0,61.1] always3(s46) || -> . % 76.04/76.28 83266[87:SSi:83265.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 83267[85:Spt:83266.0,83166.0,83167.0] || until2p7(s45)*+ -> . % 76.04/76.28 83268[85:Spt:83266.0,83166.1] || -> node4(s44)*. % 76.04/76.28 83270[85:MRR:786.0,83268.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 83273[85:Res:53.1,83270.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 83275[86:Spt:83273.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 83277[86:Res:83275.0,61.1] always3(s44) || -> . % 76.04/76.28 83278[86:SSi:83277.0,78263.0,78267.0,78622.0,83165.0,83268.0] || -> . % 76.04/76.28 83279[86:Spt:83278.0,83273.0,83275.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 83280[86:Spt:83278.0,83273.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 83284[86:Res:83280.0,61.1] always3(s45) || -> . % 76.04/76.28 83285[86:SSi:83284.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 83286[84:Spt:83285.0,83164.0,83165.0] || until2p7(s44)*+ -> . % 76.04/76.28 83287[84:Spt:83285.0,83164.1] || -> node4(s43)*. % 76.04/76.28 83289[84:MRR:789.0,83287.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 83292[84:Res:53.1,83289.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 83294[85:Spt:83292.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 83296[85:Res:83294.0,61.1] always3(s43) || -> . % 76.04/76.28 83297[85:SSi:83296.0,78259.0,78262.0,78621.0,83163.0,83287.0] || -> . % 76.04/76.28 83298[85:Spt:83297.0,83292.0,83294.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 83299[85:Spt:83297.0,83292.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 83303[85:Res:83299.0,61.1] always3(s44) || -> . % 76.04/76.28 83304[85:SSi:83303.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 83305[83:Spt:83304.0,83162.0,83163.0] || until2p7(s43)*+ -> . % 76.04/76.28 83306[83:Spt:83304.0,83162.1] || -> node4(s42)*. % 76.04/76.28 83308[83:MRR:792.0,83306.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 83311[83:Res:53.1,83308.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 83316[84:Spt:83311.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 83318[84:Res:83316.0,61.1] always3(s42) || -> . % 76.04/76.28 83319[84:SSi:83318.0,78254.0,78258.0,78620.0,83161.0,83306.0] || -> . % 76.04/76.28 83320[84:Spt:83319.0,83311.0,83316.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 83321[84:Spt:83319.0,83311.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 83325[84:Res:83321.0,61.1] always3(s43) || -> . % 76.04/76.28 83326[84:SSi:83325.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 83327[82:Spt:83326.0,83160.0,83161.0] || until2p7(s42)*+ -> . % 76.04/76.28 83328[82:Spt:83326.0,83160.1] || -> node4(s41)*. % 76.04/76.28 83330[82:MRR:795.0,83328.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 83333[82:Res:53.1,83330.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 83335[83:Spt:83333.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 83337[83:Res:83335.0,61.1] always3(s41) || -> . % 76.04/76.28 83338[83:SSi:83337.0,78250.0,78253.0,78619.0,83159.0,83328.0] || -> . % 76.04/76.28 83339[83:Spt:83338.0,83333.0,83335.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 83340[83:Spt:83338.0,83333.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 83344[83:Res:83340.0,61.1] always3(s42) || -> . % 76.04/76.28 83345[83:SSi:83344.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 83346[81:Spt:83345.0,83158.0,83159.0] || until2p7(s41)*+ -> . % 76.04/76.28 83347[81:Spt:83345.0,83158.1] || -> node4(s40)*. % 76.04/76.28 83349[81:MRR:798.0,83347.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 83352[81:Res:53.1,83349.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 83354[82:Spt:83352.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 83356[82:Res:83354.0,61.1] always3(s40) || -> . % 76.04/76.28 83357[82:SSi:83356.0,78245.0,78249.0,78618.0,83157.0,83347.0] || -> . % 76.04/76.28 83358[82:Spt:83357.0,83352.0,83354.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 83359[82:Spt:83357.0,83352.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 83363[82:Res:83359.0,61.1] always3(s41) || -> . % 76.04/76.28 83364[82:SSi:83363.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 83365[80:Spt:83364.0,83156.0,83157.0] || until2p7(s40)*+ -> . % 76.04/76.28 83366[80:Spt:83364.0,83156.1] || -> node4(s39)*. % 76.04/76.28 83368[80:MRR:801.0,83366.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 83371[80:Res:53.1,83368.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 83373[81:Spt:83371.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 83375[81:Res:83373.0,61.1] always3(s39) || -> . % 76.04/76.28 83376[81:SSi:83375.0,78241.0,78244.0,78617.0,83155.0,83366.0] || -> . % 76.04/76.28 83377[81:Spt:83376.0,83371.0,83373.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 83378[81:Spt:83376.0,83371.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 83382[81:Res:83378.0,61.1] always3(s40) || -> . % 76.04/76.28 83383[81:SSi:83382.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 83384[79:Spt:83383.0,83154.0,83155.0] || until2p7(s39)*+ -> . % 76.04/76.28 83385[79:Spt:83383.0,83154.1] || -> node4(s38)*. % 76.04/76.28 83387[79:MRR:804.0,83385.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 83390[79:Res:53.1,83387.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 83395[80:Spt:83390.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 83397[80:Res:83395.0,61.1] always3(s38) || -> . % 76.04/76.28 83398[80:SSi:83397.0,78236.0,78240.0,78616.0,83153.0,83385.0] || -> . % 76.04/76.28 83399[80:Spt:83398.0,83390.0,83395.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 83400[80:Spt:83398.0,83390.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 83404[80:Res:83400.0,61.1] always3(s39) || -> . % 76.04/76.28 83405[80:SSi:83404.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 83406[78:Spt:83405.0,83152.0,83153.0] || until2p7(s38)*+ -> . % 76.04/76.28 83407[78:Spt:83405.0,83152.1] || -> node4(s37)*. % 76.04/76.28 83409[78:MRR:807.0,83407.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 83412[78:Res:53.1,83409.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 83414[79:Spt:83412.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 83416[79:Res:83414.0,61.1] always3(s37) || -> . % 76.04/76.28 83417[79:SSi:83416.0,78232.0,78235.0,78615.0,83151.0,83407.0] || -> . % 76.04/76.28 83418[79:Spt:83417.0,83412.0,83414.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 83419[79:Spt:83417.0,83412.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 83423[79:Res:83419.0,61.1] always3(s38) || -> . % 76.04/76.28 83424[79:SSi:83423.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 83425[77:Spt:83424.0,83150.0,83151.0] || until2p7(s37)*+ -> . % 76.04/76.28 83426[77:Spt:83424.0,83150.1] || -> node4(s36)*. % 76.04/76.28 83428[77:MRR:810.0,83426.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 83431[77:Res:53.1,83428.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 83433[78:Spt:83431.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 83435[78:Res:83433.0,61.1] always3(s36) || -> . % 76.04/76.28 83436[78:SSi:83435.0,78227.0,78231.0,78614.0,83149.0,83426.0] || -> . % 76.04/76.28 83437[78:Spt:83436.0,83431.0,83433.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 83438[78:Spt:83436.0,83431.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 83442[78:Res:83438.0,61.1] always3(s37) || -> . % 76.04/76.28 83443[78:SSi:83442.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 83444[76:Spt:83443.0,83148.0,83149.0] || until2p7(s36)*+ -> . % 76.04/76.28 83445[76:Spt:83443.0,83148.1] || -> node4(s35)*. % 76.04/76.28 83447[76:MRR:813.0,83445.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 83450[76:Res:53.1,83447.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 83452[77:Spt:83450.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 83454[77:Res:83452.0,61.1] always3(s35) || -> . % 76.04/76.28 83455[77:SSi:83454.0,78223.0,78226.0,78613.0,83147.0,83445.0] || -> . % 76.04/76.28 83456[77:Spt:83455.0,83450.0,83452.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.28 83457[77:Spt:83455.0,83450.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 83461[77:Res:83457.0,61.1] always3(s36) || -> . % 76.04/76.28 83462[77:SSi:83461.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 83463[75:Spt:83462.0,83146.0,83147.0] || until2p7(s35)*+ -> . % 76.04/76.28 83464[75:Spt:83462.0,83146.1] || -> node4(s34)*. % 76.04/76.28 83466[75:MRR:816.0,83464.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.28 83469[75:Res:53.1,83466.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.28 83474[76:Spt:83469.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 83476[76:Res:83474.0,61.1] always3(s34) || -> . % 76.04/76.28 83477[76:SSi:83476.0,78218.0,78222.0,78612.0,83145.0,83464.0] || -> . % 76.04/76.28 83478[76:Spt:83477.0,83469.0,83474.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.28 83479[76:Spt:83477.0,83469.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 83483[76:Res:83479.0,61.1] always3(s35) || -> . % 76.04/76.28 83484[76:SSi:83483.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 83485[74:Spt:83484.0,83144.0,83145.0] || until2p7(s34)*+ -> . % 76.04/76.28 83486[74:Spt:83484.0,83144.1] || -> node4(s33)*. % 76.04/76.28 83488[74:MRR:819.0,83486.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.28 83491[74:Res:53.1,83488.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.28 83493[75:Spt:83491.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 83495[75:Res:83493.0,61.1] always3(s33) || -> . % 76.04/76.28 83496[75:SSi:83495.0,78214.0,78217.0,78611.0,83143.0,83486.0] || -> . % 76.04/76.28 83497[75:Spt:83496.0,83491.0,83493.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.28 83498[75:Spt:83496.0,83491.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 83502[75:Res:83498.0,61.1] always3(s34) || -> . % 76.04/76.28 83503[75:SSi:83502.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.28 83504[73:Spt:83503.0,83142.0,83143.0] || until2p7(s33)*+ -> . % 76.04/76.28 83505[73:Spt:83503.0,83142.1] || -> node4(s32)*. % 76.04/76.28 83507[73:MRR:822.0,83505.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.28 83510[73:Res:53.1,83507.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.28 83512[74:Spt:83510.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 83514[74:Res:83512.0,61.1] always3(s32) || -> . % 76.04/76.28 83515[74:SSi:83514.0,78209.0,78213.0,78610.0,83141.0,83505.0] || -> . % 76.04/76.28 83516[74:Spt:83515.0,83510.0,83512.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.28 83517[74:Spt:83515.0,83510.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 83521[74:Res:83517.0,61.1] always3(s33) || -> . % 76.04/76.28 83522[74:SSi:83521.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.28 83523[72:Spt:83522.0,83140.0,83141.0] || until2p7(s32)*+ -> . % 76.04/76.28 83524[72:Spt:83522.0,83140.1] || -> node4(s31)*. % 76.04/76.28 83526[72:MRR:825.0,83524.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.28 83529[72:Res:53.1,83526.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.28 83531[72:MRR:83529.0,83130.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 83533[72:Res:83531.0,61.1] always3(s32) || -> . % 76.04/76.28 83534[72:SSi:83533.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.28 83535[70:Spt:83534.0,83054.0,83057.0] || trans(s49,s31)*+ -> . % 76.04/76.28 83536[70:Spt:83534.0,83054.1,83054.2,83054.3,83054.4,83054.5,83054.6,83054.7,83054.8,83054.9,83054.10,83054.11,83054.12,83054.13,83054.14,83054.15,83054.16,83054.17,83054.18,83054.19,83054.20,83054.21,83054.22,83054.23,83054.24,83054.25,83054.26,83054.27,83054.28,83054.29] || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 83538[70:MRR:83056.1,83535.0] xuntil6(s49) || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 83539[71:Spt:83536.0] || -> trans(s49,s30)*. % 76.04/76.28 83540[71:Res:83539.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s30)*. % 76.04/76.28 83542[71:Res:83539.0,60.0] || -> node2(s49,s30)*. % 76.04/76.28 83543[71:SSi:83540.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s30)*. % 76.04/76.28 83544[71:Res:83542.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 83611[71:SoR:83544.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 83613[71:SoR:83611.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)* xuntil6(s49). % 76.04/76.28 83614[71:SSi:83613.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s30,c_busy)* xuntil6(s49). % 76.04/76.28 83615[72:Spt:83614.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 83617[72:Res:83615.0,61.1] always3(s30) || -> . % 76.04/76.28 83618[72:SSi:83617.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.28 83619[72:Spt:83618.0,83614.1,83615.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.04/76.28 83620[72:Spt:83618.0,83614.0,83614.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 83624[72:MRR:83611.2,83619.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 83625[72:Res:53.1,83620.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 83627[72:MRR:83625.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 83628[72:MRR:83543.0,83627.0] || -> until2p7(s30)*. % 76.04/76.28 83629[72:MRR:226.0,83628.0] || -> until2p7(s31)* node4(s30). % 76.04/76.28 83630[73:Spt:83629.0] || -> until2p7(s31)*. % 76.04/76.28 83631[73:MRR:227.0,83630.0] || -> until2p7(s32)* node4(s31). % 76.04/76.28 83632[74:Spt:83631.0] || -> until2p7(s32)*. % 76.04/76.28 83633[74:MRR:228.0,83632.0] || -> until2p7(s33)* node4(s32). % 76.04/76.28 83634[75:Spt:83633.0] || -> until2p7(s33)*. % 76.04/76.28 83635[75:MRR:229.0,83634.0] || -> until2p7(s34)* node4(s33). % 76.04/76.28 83636[76:Spt:83635.0] || -> until2p7(s34)*. % 76.04/76.28 83637[76:MRR:230.0,83636.0] || -> until2p7(s35)* node4(s34). % 76.04/76.28 83638[77:Spt:83637.0] || -> until2p7(s35)*. % 76.04/76.28 83639[77:MRR:231.0,83638.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 83640[78:Spt:83639.0] || -> until2p7(s36)*. % 76.04/76.28 83641[78:MRR:232.0,83640.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 83642[79:Spt:83641.0] || -> until2p7(s37)*. % 76.04/76.28 83643[79:MRR:235.0,83642.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 83644[80:Spt:83643.0] || -> until2p7(s38)*. % 76.04/76.28 83645[80:MRR:236.0,83644.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 83646[81:Spt:83645.0] || -> until2p7(s39)*. % 76.04/76.28 83647[81:MRR:237.0,83646.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 83648[82:Spt:83647.0] || -> until2p7(s40)*. % 76.04/76.28 83649[82:MRR:238.0,83648.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 83650[83:Spt:83649.0] || -> until2p7(s41)*. % 76.04/76.28 83651[83:MRR:239.0,83650.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 83652[84:Spt:83651.0] || -> until2p7(s42)*. % 76.04/76.28 83653[84:MRR:240.0,83652.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 83654[85:Spt:83653.0] || -> until2p7(s43)*. % 76.04/76.28 83655[85:MRR:241.0,83654.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 83656[86:Spt:83655.0] || -> until2p7(s44)*. % 76.04/76.28 83657[86:MRR:539.0,83656.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 83658[87:Spt:83657.0] || -> until2p7(s45)*. % 76.04/76.28 83659[87:MRR:544.0,83658.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 83660[88:Spt:83659.0] || -> until2p7(s46)*. % 76.04/76.28 83661[88:MRR:549.0,83660.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 83662[89:Spt:83661.0] || -> until2p7(s47)*. % 76.04/76.28 83663[89:MRR:554.0,83662.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 83664[90:Spt:83663.0] || -> until2p7(s48)*. % 76.04/76.28 83665[90:MRR:559.0,83664.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 83666[91:Spt:83665.0] || -> until2p7(s49)*. % 76.04/76.28 83667[91:MRR:194.0,83666.0] || -> node4(s49)*. % 76.04/76.28 83668[91:MRR:83624.0,83667.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 83669[91:Res:53.1,83668.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 83671[91:MRR:83669.0,78381.0] || -> . % 76.04/76.28 83672[91:Spt:83671.0,83665.0,83666.0] || until2p7(s49)*+ -> . % 76.04/76.28 83673[91:Spt:83671.0,83665.1] || -> node4(s48)*. % 76.04/76.28 83674[91:MRR:78384.0,83673.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 83677[91:Res:53.1,83674.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 83680[91:Res:83677.0,61.1] always3(s48) || -> . % 76.04/76.28 83681[91:SSi:83680.0,78281.0,78387.0,78626.0,83664.0,83673.0] || -> . % 76.04/76.28 83682[90:Spt:83681.0,83663.0,83664.0] || until2p7(s48)*+ -> . % 76.04/76.28 83683[90:Spt:83681.0,83663.1] || -> node4(s47)*. % 76.04/76.28 83685[90:MRR:777.0,83683.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 83700[90:Res:53.1,83685.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 83702[91:Spt:83700.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 83704[91:Res:83702.0,61.1] always3(s47) || -> . % 76.04/76.28 83705[91:SSi:83704.0,78277.0,78280.0,78625.0,83662.0,83683.0] || -> . % 76.04/76.28 83706[91:Spt:83705.0,83700.0,83702.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 83707[91:Spt:83705.0,83700.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 83711[91:Res:83707.0,61.1] always3(s48) || -> . % 76.04/76.28 83712[91:SSi:83711.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 83713[89:Spt:83712.0,83661.0,83662.0] || until2p7(s47)*+ -> . % 76.04/76.28 83714[89:Spt:83712.0,83661.1] || -> node4(s46)*. % 76.04/76.28 83716[89:MRR:780.0,83714.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 83726[89:Res:53.1,83716.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 83728[90:Spt:83726.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 83730[90:Res:83728.0,61.1] always3(s46) || -> . % 76.04/76.28 83731[90:SSi:83730.0,78272.0,78276.0,78624.0,83660.0,83714.0] || -> . % 76.04/76.28 83732[90:Spt:83731.0,83726.0,83728.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 83733[90:Spt:83731.0,83726.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 83737[90:Res:83733.0,61.1] always3(s47) || -> . % 76.04/76.28 83738[90:SSi:83737.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 83739[88:Spt:83738.0,83659.0,83660.0] || until2p7(s46)*+ -> . % 76.04/76.28 83740[88:Spt:83738.0,83659.1] || -> node4(s45)*. % 76.04/76.28 83742[88:MRR:783.0,83740.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 83745[88:Res:53.1,83742.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 83747[89:Spt:83745.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 83749[89:Res:83747.0,61.1] always3(s45) || -> . % 76.04/76.28 83750[89:SSi:83749.0,78268.0,78271.0,78623.0,83658.0,83740.0] || -> . % 76.04/76.28 83751[89:Spt:83750.0,83745.0,83747.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 83752[89:Spt:83750.0,83745.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 83756[89:Res:83752.0,61.1] always3(s46) || -> . % 76.04/76.28 83757[89:SSi:83756.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 83758[87:Spt:83757.0,83657.0,83658.0] || until2p7(s45)*+ -> . % 76.04/76.28 83759[87:Spt:83757.0,83657.1] || -> node4(s44)*. % 76.04/76.28 83761[87:MRR:786.0,83759.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 83764[87:Res:53.1,83761.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 83766[88:Spt:83764.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 83768[88:Res:83766.0,61.1] always3(s44) || -> . % 76.04/76.28 83769[88:SSi:83768.0,78263.0,78267.0,78622.0,83656.0,83759.0] || -> . % 76.04/76.28 83770[88:Spt:83769.0,83764.0,83766.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 83771[88:Spt:83769.0,83764.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 83775[88:Res:83771.0,61.1] always3(s45) || -> . % 76.04/76.28 83776[88:SSi:83775.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 83777[86:Spt:83776.0,83655.0,83656.0] || until2p7(s44)*+ -> . % 76.04/76.28 83778[86:Spt:83776.0,83655.1] || -> node4(s43)*. % 76.04/76.28 83780[86:MRR:789.0,83778.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 83783[86:Res:53.1,83780.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 83788[87:Spt:83783.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 83790[87:Res:83788.0,61.1] always3(s43) || -> . % 76.04/76.28 83791[87:SSi:83790.0,78259.0,78262.0,78621.0,83654.0,83778.0] || -> . % 76.04/76.28 83792[87:Spt:83791.0,83783.0,83788.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 83793[87:Spt:83791.0,83783.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 83797[87:Res:83793.0,61.1] always3(s44) || -> . % 76.04/76.28 83798[87:SSi:83797.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 83799[85:Spt:83798.0,83653.0,83654.0] || until2p7(s43)*+ -> . % 76.04/76.28 83800[85:Spt:83798.0,83653.1] || -> node4(s42)*. % 76.04/76.28 83802[85:MRR:792.0,83800.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 83805[85:Res:53.1,83802.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 83807[86:Spt:83805.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 83809[86:Res:83807.0,61.1] always3(s42) || -> . % 76.04/76.28 83810[86:SSi:83809.0,78254.0,78258.0,78620.0,83652.0,83800.0] || -> . % 76.04/76.28 83811[86:Spt:83810.0,83805.0,83807.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 83812[86:Spt:83810.0,83805.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 83816[86:Res:83812.0,61.1] always3(s43) || -> . % 76.04/76.28 83817[86:SSi:83816.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 83818[84:Spt:83817.0,83651.0,83652.0] || until2p7(s42)*+ -> . % 76.04/76.28 83819[84:Spt:83817.0,83651.1] || -> node4(s41)*. % 76.04/76.28 83821[84:MRR:795.0,83819.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 83824[84:Res:53.1,83821.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 83826[85:Spt:83824.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 83828[85:Res:83826.0,61.1] always3(s41) || -> . % 76.04/76.28 83829[85:SSi:83828.0,78250.0,78253.0,78619.0,83650.0,83819.0] || -> . % 76.04/76.28 83830[85:Spt:83829.0,83824.0,83826.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 83831[85:Spt:83829.0,83824.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 83835[85:Res:83831.0,61.1] always3(s42) || -> . % 76.04/76.28 83836[85:SSi:83835.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 83837[83:Spt:83836.0,83649.0,83650.0] || until2p7(s41)*+ -> . % 76.04/76.28 83838[83:Spt:83836.0,83649.1] || -> node4(s40)*. % 76.04/76.28 83840[83:MRR:798.0,83838.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 83843[83:Res:53.1,83840.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 83845[84:Spt:83843.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 83847[84:Res:83845.0,61.1] always3(s40) || -> . % 76.04/76.28 83848[84:SSi:83847.0,78245.0,78249.0,78618.0,83648.0,83838.0] || -> . % 76.04/76.28 83849[84:Spt:83848.0,83843.0,83845.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 83850[84:Spt:83848.0,83843.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 83854[84:Res:83850.0,61.1] always3(s41) || -> . % 76.04/76.28 83855[84:SSi:83854.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 83856[82:Spt:83855.0,83647.0,83648.0] || until2p7(s40)*+ -> . % 76.04/76.28 83857[82:Spt:83855.0,83647.1] || -> node4(s39)*. % 76.04/76.28 83859[82:MRR:801.0,83857.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 83862[82:Res:53.1,83859.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 83867[83:Spt:83862.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 83869[83:Res:83867.0,61.1] always3(s39) || -> . % 76.04/76.28 83870[83:SSi:83869.0,78241.0,78244.0,78617.0,83646.0,83857.0] || -> . % 76.04/76.28 83871[83:Spt:83870.0,83862.0,83867.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 83872[83:Spt:83870.0,83862.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 83876[83:Res:83872.0,61.1] always3(s40) || -> . % 76.04/76.28 83877[83:SSi:83876.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 83878[81:Spt:83877.0,83645.0,83646.0] || until2p7(s39)*+ -> . % 76.04/76.28 83879[81:Spt:83877.0,83645.1] || -> node4(s38)*. % 76.04/76.28 83881[81:MRR:804.0,83879.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 83884[81:Res:53.1,83881.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 83886[82:Spt:83884.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 83888[82:Res:83886.0,61.1] always3(s38) || -> . % 76.04/76.28 83889[82:SSi:83888.0,78236.0,78240.0,78616.0,83644.0,83879.0] || -> . % 76.04/76.28 83890[82:Spt:83889.0,83884.0,83886.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 83891[82:Spt:83889.0,83884.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 83895[82:Res:83891.0,61.1] always3(s39) || -> . % 76.04/76.28 83896[82:SSi:83895.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 83897[80:Spt:83896.0,83643.0,83644.0] || until2p7(s38)*+ -> . % 76.04/76.28 83898[80:Spt:83896.0,83643.1] || -> node4(s37)*. % 76.04/76.28 83900[80:MRR:807.0,83898.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 83903[80:Res:53.1,83900.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 83905[81:Spt:83903.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 83907[81:Res:83905.0,61.1] always3(s37) || -> . % 76.04/76.28 83908[81:SSi:83907.0,78232.0,78235.0,78615.0,83642.0,83898.0] || -> . % 76.04/76.28 83909[81:Spt:83908.0,83903.0,83905.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 83910[81:Spt:83908.0,83903.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 83914[81:Res:83910.0,61.1] always3(s38) || -> . % 76.04/76.28 83915[81:SSi:83914.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 83916[79:Spt:83915.0,83641.0,83642.0] || until2p7(s37)*+ -> . % 76.04/76.28 83917[79:Spt:83915.0,83641.1] || -> node4(s36)*. % 76.04/76.28 83919[79:MRR:810.0,83917.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 83922[79:Res:53.1,83919.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 83924[80:Spt:83922.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 83926[80:Res:83924.0,61.1] always3(s36) || -> . % 76.04/76.28 83927[80:SSi:83926.0,78227.0,78231.0,78614.0,83640.0,83917.0] || -> . % 76.04/76.28 83928[80:Spt:83927.0,83922.0,83924.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 83929[80:Spt:83927.0,83922.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 83933[80:Res:83929.0,61.1] always3(s37) || -> . % 76.04/76.28 83934[80:SSi:83933.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 83935[78:Spt:83934.0,83639.0,83640.0] || until2p7(s36)*+ -> . % 76.04/76.28 83936[78:Spt:83934.0,83639.1] || -> node4(s35)*. % 76.04/76.28 83938[78:MRR:813.0,83936.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 83941[78:Res:53.1,83938.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 83946[79:Spt:83941.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 83948[79:Res:83946.0,61.1] always3(s35) || -> . % 76.04/76.28 83949[79:SSi:83948.0,78223.0,78226.0,78613.0,83638.0,83936.0] || -> . % 76.04/76.28 83950[79:Spt:83949.0,83941.0,83946.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.28 83951[79:Spt:83949.0,83941.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 83955[79:Res:83951.0,61.1] always3(s36) || -> . % 76.04/76.28 83956[79:SSi:83955.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 83957[77:Spt:83956.0,83637.0,83638.0] || until2p7(s35)*+ -> . % 76.04/76.28 83958[77:Spt:83956.0,83637.1] || -> node4(s34)*. % 76.04/76.28 83960[77:MRR:816.0,83958.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.28 83963[77:Res:53.1,83960.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.28 83965[78:Spt:83963.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 83967[78:Res:83965.0,61.1] always3(s34) || -> . % 76.04/76.28 83968[78:SSi:83967.0,78218.0,78222.0,78612.0,83636.0,83958.0] || -> . % 76.04/76.28 83969[78:Spt:83968.0,83963.0,83965.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.28 83970[78:Spt:83968.0,83963.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 83974[78:Res:83970.0,61.1] always3(s35) || -> . % 76.04/76.28 83975[78:SSi:83974.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 83976[76:Spt:83975.0,83635.0,83636.0] || until2p7(s34)*+ -> . % 76.04/76.28 83977[76:Spt:83975.0,83635.1] || -> node4(s33)*. % 76.04/76.28 83979[76:MRR:819.0,83977.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.28 83982[76:Res:53.1,83979.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.28 83984[77:Spt:83982.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 83986[77:Res:83984.0,61.1] always3(s33) || -> . % 76.04/76.28 83987[77:SSi:83986.0,78214.0,78217.0,78611.0,83634.0,83977.0] || -> . % 76.04/76.28 83988[77:Spt:83987.0,83982.0,83984.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.28 83989[77:Spt:83987.0,83982.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 83993[77:Res:83989.0,61.1] always3(s34) || -> . % 76.04/76.28 83994[77:SSi:83993.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.28 83995[75:Spt:83994.0,83633.0,83634.0] || until2p7(s33)*+ -> . % 76.04/76.28 83996[75:Spt:83994.0,83633.1] || -> node4(s32)*. % 76.04/76.28 83998[75:MRR:822.0,83996.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.28 84001[75:Res:53.1,83998.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.28 84003[76:Spt:84001.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 84005[76:Res:84003.0,61.1] always3(s32) || -> . % 76.04/76.28 84006[76:SSi:84005.0,78209.0,78213.0,78610.0,83632.0,83996.0] || -> . % 76.04/76.28 84007[76:Spt:84006.0,84001.0,84003.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.28 84008[76:Spt:84006.0,84001.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 84012[76:Res:84008.0,61.1] always3(s33) || -> . % 76.04/76.28 84013[76:SSi:84012.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.28 84014[74:Spt:84013.0,83631.0,83632.0] || until2p7(s32)*+ -> . % 76.04/76.28 84015[74:Spt:84013.0,83631.1] || -> node4(s31)*. % 76.04/76.28 84017[74:MRR:825.0,84015.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.28 84020[74:Res:53.1,84017.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.28 84025[75:Spt:84020.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 84027[75:Res:84025.0,61.1] always3(s31) || -> . % 76.04/76.28 84028[75:SSi:84027.0,78205.0,78208.0,78609.0,83630.0,84015.0] || -> . % 76.04/76.28 84029[75:Spt:84028.0,84020.0,84025.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.28 84030[75:Spt:84028.0,84020.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 84034[75:Res:84030.0,61.1] always3(s32) || -> . % 76.04/76.28 84035[75:SSi:84034.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.28 84036[73:Spt:84035.0,83629.0,83630.0] || until2p7(s31)*+ -> . % 76.04/76.28 84037[73:Spt:84035.0,83629.1] || -> node4(s30)*. % 76.04/76.28 84039[73:MRR:828.0,84037.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.28 84042[73:Res:53.1,84039.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.28 84044[73:MRR:84042.0,83619.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 84046[73:Res:84044.0,61.1] always3(s31) || -> . % 76.04/76.28 84047[73:SSi:84046.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.28 84048[71:Spt:84047.0,83536.0,83539.0] || trans(s49,s30)*+ -> . % 76.04/76.28 84049[71:Spt:84047.0,83536.1,83536.2,83536.3,83536.4,83536.5,83536.6,83536.7,83536.8,83536.9,83536.10,83536.11,83536.12,83536.13,83536.14,83536.15,83536.16,83536.17,83536.18,83536.19,83536.20,83536.21,83536.22,83536.23,83536.24,83536.25,83536.26,83536.27,83536.28] || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 84051[71:MRR:83538.1,84048.0] xuntil6(s49) || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 84052[72:Spt:84049.0] || -> trans(s49,s29)*. % 76.04/76.28 84053[72:Res:84052.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s29)*. % 76.04/76.28 84055[72:Res:84052.0,60.0] || -> node2(s49,s29)*. % 76.04/76.28 84056[72:SSi:84053.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s29)*. % 76.04/76.28 84057[72:Res:84055.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 84125[72:SoR:84057.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 84127[72:SoR:84125.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.04/76.28 84128[72:SSi:84127.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.04/76.28 84129[73:Spt:84128.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 84131[73:Res:84129.0,61.1] always3(s29) || -> . % 76.04/76.28 84132[73:SSi:84131.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.28 84133[73:Spt:84132.0,84128.1,84129.0] || m_main_v_state(s29,c_busy)*+ -> . % 76.04/76.28 84134[73:Spt:84132.0,84128.0,84128.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 84138[73:MRR:84125.2,84133.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 84139[73:Res:53.1,84134.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 84141[73:MRR:84139.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 84142[73:MRR:84056.0,84141.0] || -> until2p7(s29)*. % 76.04/76.28 84143[73:MRR:225.0,84142.0] || -> until2p7(s30)* node4(s29). % 76.04/76.28 84144[74:Spt:84143.0] || -> until2p7(s30)*. % 76.04/76.28 84145[74:MRR:226.0,84144.0] || -> until2p7(s31)* node4(s30). % 76.04/76.28 84146[75:Spt:84145.0] || -> until2p7(s31)*. % 76.04/76.28 84147[75:MRR:227.0,84146.0] || -> until2p7(s32)* node4(s31). % 76.04/76.28 84148[76:Spt:84147.0] || -> until2p7(s32)*. % 76.04/76.28 84149[76:MRR:228.0,84148.0] || -> until2p7(s33)* node4(s32). % 76.04/76.28 84150[77:Spt:84149.0] || -> until2p7(s33)*. % 76.04/76.28 84151[77:MRR:229.0,84150.0] || -> until2p7(s34)* node4(s33). % 76.04/76.28 84152[78:Spt:84151.0] || -> until2p7(s34)*. % 76.04/76.28 84153[78:MRR:230.0,84152.0] || -> until2p7(s35)* node4(s34). % 76.04/76.28 84154[79:Spt:84153.0] || -> until2p7(s35)*. % 76.04/76.28 84155[79:MRR:231.0,84154.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 84156[80:Spt:84155.0] || -> until2p7(s36)*. % 76.04/76.28 84157[80:MRR:232.0,84156.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 84158[81:Spt:84157.0] || -> until2p7(s37)*. % 76.04/76.28 84159[81:MRR:235.0,84158.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 84160[82:Spt:84159.0] || -> until2p7(s38)*. % 76.04/76.28 84161[82:MRR:236.0,84160.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 84162[83:Spt:84161.0] || -> until2p7(s39)*. % 76.04/76.28 84163[83:MRR:237.0,84162.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 84164[84:Spt:84163.0] || -> until2p7(s40)*. % 76.04/76.28 84165[84:MRR:238.0,84164.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 84166[85:Spt:84165.0] || -> until2p7(s41)*. % 76.04/76.28 84167[85:MRR:239.0,84166.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 84168[86:Spt:84167.0] || -> until2p7(s42)*. % 76.04/76.28 84169[86:MRR:240.0,84168.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 84170[87:Spt:84169.0] || -> until2p7(s43)*. % 76.04/76.28 84171[87:MRR:241.0,84170.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 84172[88:Spt:84171.0] || -> until2p7(s44)*. % 76.04/76.28 84173[88:MRR:539.0,84172.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 84174[89:Spt:84173.0] || -> until2p7(s45)*. % 76.04/76.28 84175[89:MRR:544.0,84174.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 84176[90:Spt:84175.0] || -> until2p7(s46)*. % 76.04/76.28 84177[90:MRR:549.0,84176.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 84178[91:Spt:84177.0] || -> until2p7(s47)*. % 76.04/76.28 84179[91:MRR:554.0,84178.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 84180[92:Spt:84179.0] || -> until2p7(s48)*. % 76.04/76.28 84181[92:MRR:559.0,84180.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 84182[93:Spt:84181.0] || -> until2p7(s49)*. % 76.04/76.28 84183[93:MRR:194.0,84182.0] || -> node4(s49)*. % 76.04/76.28 84184[93:MRR:84138.0,84183.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 84185[93:Res:53.1,84184.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 84187[93:MRR:84185.0,78381.0] || -> . % 76.04/76.28 84188[93:Spt:84187.0,84181.0,84182.0] || until2p7(s49)*+ -> . % 76.04/76.28 84189[93:Spt:84187.0,84181.1] || -> node4(s48)*. % 76.04/76.28 84190[93:MRR:78384.0,84189.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 84193[93:Res:53.1,84190.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 84196[93:Res:84193.0,61.1] always3(s48) || -> . % 76.04/76.28 84197[93:SSi:84196.0,78281.0,78387.0,78626.0,84180.0,84189.0] || -> . % 76.04/76.28 84198[92:Spt:84197.0,84179.0,84180.0] || until2p7(s48)*+ -> . % 76.04/76.28 84199[92:Spt:84197.0,84179.1] || -> node4(s47)*. % 76.04/76.28 84201[92:MRR:777.0,84199.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 84216[92:Res:53.1,84201.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 84218[93:Spt:84216.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 84220[93:Res:84218.0,61.1] always3(s47) || -> . % 76.04/76.28 84221[93:SSi:84220.0,78277.0,78280.0,78625.0,84178.0,84199.0] || -> . % 76.04/76.28 84222[93:Spt:84221.0,84216.0,84218.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 84223[93:Spt:84221.0,84216.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 84227[93:Res:84223.0,61.1] always3(s48) || -> . % 76.04/76.28 84228[93:SSi:84227.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 84229[91:Spt:84228.0,84177.0,84178.0] || until2p7(s47)*+ -> . % 76.04/76.28 84230[91:Spt:84228.0,84177.1] || -> node4(s46)*. % 76.04/76.28 84232[91:MRR:780.0,84230.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 84242[91:Res:53.1,84232.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 84244[92:Spt:84242.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 84246[92:Res:84244.0,61.1] always3(s46) || -> . % 76.04/76.28 84247[92:SSi:84246.0,78272.0,78276.0,78624.0,84176.0,84230.0] || -> . % 76.04/76.28 84248[92:Spt:84247.0,84242.0,84244.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 84249[92:Spt:84247.0,84242.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 84253[92:Res:84249.0,61.1] always3(s47) || -> . % 76.04/76.28 84254[92:SSi:84253.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 84255[90:Spt:84254.0,84175.0,84176.0] || until2p7(s46)*+ -> . % 76.04/76.28 84256[90:Spt:84254.0,84175.1] || -> node4(s45)*. % 76.04/76.28 84258[90:MRR:783.0,84256.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 84261[90:Res:53.1,84258.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 84263[91:Spt:84261.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 84265[91:Res:84263.0,61.1] always3(s45) || -> . % 76.04/76.28 84266[91:SSi:84265.0,78268.0,78271.0,78623.0,84174.0,84256.0] || -> . % 76.04/76.28 84267[91:Spt:84266.0,84261.0,84263.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 84268[91:Spt:84266.0,84261.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 84272[91:Res:84268.0,61.1] always3(s46) || -> . % 76.04/76.28 84273[91:SSi:84272.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 84274[89:Spt:84273.0,84173.0,84174.0] || until2p7(s45)*+ -> . % 76.04/76.28 84275[89:Spt:84273.0,84173.1] || -> node4(s44)*. % 76.04/76.28 84277[89:MRR:786.0,84275.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 84280[89:Res:53.1,84277.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 84282[90:Spt:84280.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 84284[90:Res:84282.0,61.1] always3(s44) || -> . % 76.04/76.28 84285[90:SSi:84284.0,78263.0,78267.0,78622.0,84172.0,84275.0] || -> . % 76.04/76.28 84286[90:Spt:84285.0,84280.0,84282.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 84287[90:Spt:84285.0,84280.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 84291[90:Res:84287.0,61.1] always3(s45) || -> . % 76.04/76.28 84292[90:SSi:84291.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 84293[88:Spt:84292.0,84171.0,84172.0] || until2p7(s44)*+ -> . % 76.04/76.28 84294[88:Spt:84292.0,84171.1] || -> node4(s43)*. % 76.04/76.28 84296[88:MRR:789.0,84294.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 84299[88:Res:53.1,84296.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 84304[89:Spt:84299.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 84306[89:Res:84304.0,61.1] always3(s43) || -> . % 76.04/76.28 84307[89:SSi:84306.0,78259.0,78262.0,78621.0,84170.0,84294.0] || -> . % 76.04/76.28 84308[89:Spt:84307.0,84299.0,84304.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 84309[89:Spt:84307.0,84299.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 84313[89:Res:84309.0,61.1] always3(s44) || -> . % 76.04/76.28 84314[89:SSi:84313.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 84315[87:Spt:84314.0,84169.0,84170.0] || until2p7(s43)*+ -> . % 76.04/76.28 84316[87:Spt:84314.0,84169.1] || -> node4(s42)*. % 76.04/76.28 84318[87:MRR:792.0,84316.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 84321[87:Res:53.1,84318.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 84323[88:Spt:84321.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 84325[88:Res:84323.0,61.1] always3(s42) || -> . % 76.04/76.28 84326[88:SSi:84325.0,78254.0,78258.0,78620.0,84168.0,84316.0] || -> . % 76.04/76.28 84327[88:Spt:84326.0,84321.0,84323.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 84328[88:Spt:84326.0,84321.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 84332[88:Res:84328.0,61.1] always3(s43) || -> . % 76.04/76.28 84333[88:SSi:84332.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 84334[86:Spt:84333.0,84167.0,84168.0] || until2p7(s42)*+ -> . % 76.04/76.28 84335[86:Spt:84333.0,84167.1] || -> node4(s41)*. % 76.04/76.28 84337[86:MRR:795.0,84335.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 84340[86:Res:53.1,84337.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 84342[87:Spt:84340.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 84344[87:Res:84342.0,61.1] always3(s41) || -> . % 76.04/76.28 84345[87:SSi:84344.0,78250.0,78253.0,78619.0,84166.0,84335.0] || -> . % 76.04/76.28 84346[87:Spt:84345.0,84340.0,84342.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 84347[87:Spt:84345.0,84340.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 84351[87:Res:84347.0,61.1] always3(s42) || -> . % 76.04/76.28 84352[87:SSi:84351.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 84353[85:Spt:84352.0,84165.0,84166.0] || until2p7(s41)*+ -> . % 76.04/76.28 84354[85:Spt:84352.0,84165.1] || -> node4(s40)*. % 76.04/76.28 84356[85:MRR:798.0,84354.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 84359[85:Res:53.1,84356.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 84361[86:Spt:84359.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 84363[86:Res:84361.0,61.1] always3(s40) || -> . % 76.04/76.28 84364[86:SSi:84363.0,78245.0,78249.0,78618.0,84164.0,84354.0] || -> . % 76.04/76.28 84365[86:Spt:84364.0,84359.0,84361.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 84366[86:Spt:84364.0,84359.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 84370[86:Res:84366.0,61.1] always3(s41) || -> . % 76.04/76.28 84371[86:SSi:84370.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 84372[84:Spt:84371.0,84163.0,84164.0] || until2p7(s40)*+ -> . % 76.04/76.28 84373[84:Spt:84371.0,84163.1] || -> node4(s39)*. % 76.04/76.28 84375[84:MRR:801.0,84373.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 84378[84:Res:53.1,84375.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 84383[85:Spt:84378.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 84385[85:Res:84383.0,61.1] always3(s39) || -> . % 76.04/76.28 84386[85:SSi:84385.0,78241.0,78244.0,78617.0,84162.0,84373.0] || -> . % 76.04/76.28 84387[85:Spt:84386.0,84378.0,84383.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 84388[85:Spt:84386.0,84378.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 84392[85:Res:84388.0,61.1] always3(s40) || -> . % 76.04/76.28 84393[85:SSi:84392.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 84394[83:Spt:84393.0,84161.0,84162.0] || until2p7(s39)*+ -> . % 76.04/76.28 84395[83:Spt:84393.0,84161.1] || -> node4(s38)*. % 76.04/76.28 84397[83:MRR:804.0,84395.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 84400[83:Res:53.1,84397.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 84402[84:Spt:84400.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 84404[84:Res:84402.0,61.1] always3(s38) || -> . % 76.04/76.28 84405[84:SSi:84404.0,78236.0,78240.0,78616.0,84160.0,84395.0] || -> . % 76.04/76.28 84406[84:Spt:84405.0,84400.0,84402.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 84407[84:Spt:84405.0,84400.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 84411[84:Res:84407.0,61.1] always3(s39) || -> . % 76.04/76.28 84412[84:SSi:84411.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 84413[82:Spt:84412.0,84159.0,84160.0] || until2p7(s38)*+ -> . % 76.04/76.28 84414[82:Spt:84412.0,84159.1] || -> node4(s37)*. % 76.04/76.28 84416[82:MRR:807.0,84414.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 84419[82:Res:53.1,84416.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 84421[83:Spt:84419.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 84423[83:Res:84421.0,61.1] always3(s37) || -> . % 76.04/76.28 84424[83:SSi:84423.0,78232.0,78235.0,78615.0,84158.0,84414.0] || -> . % 76.04/76.28 84425[83:Spt:84424.0,84419.0,84421.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 84426[83:Spt:84424.0,84419.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 84430[83:Res:84426.0,61.1] always3(s38) || -> . % 76.04/76.28 84431[83:SSi:84430.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 84432[81:Spt:84431.0,84157.0,84158.0] || until2p7(s37)*+ -> . % 76.04/76.28 84433[81:Spt:84431.0,84157.1] || -> node4(s36)*. % 76.04/76.28 84435[81:MRR:810.0,84433.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 84438[81:Res:53.1,84435.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 84440[82:Spt:84438.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 84442[82:Res:84440.0,61.1] always3(s36) || -> . % 76.04/76.28 84443[82:SSi:84442.0,78227.0,78231.0,78614.0,84156.0,84433.0] || -> . % 76.04/76.28 84444[82:Spt:84443.0,84438.0,84440.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 84445[82:Spt:84443.0,84438.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 84449[82:Res:84445.0,61.1] always3(s37) || -> . % 76.04/76.28 84450[82:SSi:84449.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 84451[80:Spt:84450.0,84155.0,84156.0] || until2p7(s36)*+ -> . % 76.04/76.28 84452[80:Spt:84450.0,84155.1] || -> node4(s35)*. % 76.04/76.28 84454[80:MRR:813.0,84452.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 84457[80:Res:53.1,84454.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 84462[81:Spt:84457.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 84464[81:Res:84462.0,61.1] always3(s35) || -> . % 76.04/76.28 84465[81:SSi:84464.0,78223.0,78226.0,78613.0,84154.0,84452.0] || -> . % 76.04/76.28 84466[81:Spt:84465.0,84457.0,84462.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.28 84467[81:Spt:84465.0,84457.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 84471[81:Res:84467.0,61.1] always3(s36) || -> . % 76.04/76.28 84472[81:SSi:84471.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 84473[79:Spt:84472.0,84153.0,84154.0] || until2p7(s35)*+ -> . % 76.04/76.28 84474[79:Spt:84472.0,84153.1] || -> node4(s34)*. % 76.04/76.28 84476[79:MRR:816.0,84474.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.28 84479[79:Res:53.1,84476.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.28 84481[80:Spt:84479.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 84483[80:Res:84481.0,61.1] always3(s34) || -> . % 76.04/76.28 84484[80:SSi:84483.0,78218.0,78222.0,78612.0,84152.0,84474.0] || -> . % 76.04/76.28 84485[80:Spt:84484.0,84479.0,84481.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.28 84486[80:Spt:84484.0,84479.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 84490[80:Res:84486.0,61.1] always3(s35) || -> . % 76.04/76.28 84491[80:SSi:84490.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 84492[78:Spt:84491.0,84151.0,84152.0] || until2p7(s34)*+ -> . % 76.04/76.28 84493[78:Spt:84491.0,84151.1] || -> node4(s33)*. % 76.04/76.28 84495[78:MRR:819.0,84493.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.28 84498[78:Res:53.1,84495.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.28 84500[79:Spt:84498.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 84502[79:Res:84500.0,61.1] always3(s33) || -> . % 76.04/76.28 84503[79:SSi:84502.0,78214.0,78217.0,78611.0,84150.0,84493.0] || -> . % 76.04/76.28 84504[79:Spt:84503.0,84498.0,84500.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.28 84505[79:Spt:84503.0,84498.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 84509[79:Res:84505.0,61.1] always3(s34) || -> . % 76.04/76.28 84510[79:SSi:84509.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.28 84511[77:Spt:84510.0,84149.0,84150.0] || until2p7(s33)*+ -> . % 76.04/76.28 84512[77:Spt:84510.0,84149.1] || -> node4(s32)*. % 76.04/76.28 84514[77:MRR:822.0,84512.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.28 84517[77:Res:53.1,84514.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.28 84519[78:Spt:84517.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 84521[78:Res:84519.0,61.1] always3(s32) || -> . % 76.04/76.28 84522[78:SSi:84521.0,78209.0,78213.0,78610.0,84148.0,84512.0] || -> . % 76.04/76.28 84523[78:Spt:84522.0,84517.0,84519.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.28 84524[78:Spt:84522.0,84517.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 84528[78:Res:84524.0,61.1] always3(s33) || -> . % 76.04/76.28 84529[78:SSi:84528.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.28 84530[76:Spt:84529.0,84147.0,84148.0] || until2p7(s32)*+ -> . % 76.04/76.28 84531[76:Spt:84529.0,84147.1] || -> node4(s31)*. % 76.04/76.28 84533[76:MRR:825.0,84531.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.28 84536[76:Res:53.1,84533.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.28 84541[77:Spt:84536.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 84543[77:Res:84541.0,61.1] always3(s31) || -> . % 76.04/76.28 84544[77:SSi:84543.0,78205.0,78208.0,78609.0,84146.0,84531.0] || -> . % 76.04/76.28 84545[77:Spt:84544.0,84536.0,84541.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.28 84546[77:Spt:84544.0,84536.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 84550[77:Res:84546.0,61.1] always3(s32) || -> . % 76.04/76.28 84551[77:SSi:84550.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.28 84552[75:Spt:84551.0,84145.0,84146.0] || until2p7(s31)*+ -> . % 76.04/76.28 84553[75:Spt:84551.0,84145.1] || -> node4(s30)*. % 76.04/76.28 84555[75:MRR:828.0,84553.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.28 84558[75:Res:53.1,84555.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.28 84560[76:Spt:84558.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 84562[76:Res:84560.0,61.1] always3(s30) || -> . % 76.04/76.28 84563[76:SSi:84562.0,78200.0,78204.0,78608.0,84144.0,84553.0] || -> . % 76.04/76.28 84564[76:Spt:84563.0,84558.0,84560.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.28 84565[76:Spt:84563.0,84558.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 84569[76:Res:84565.0,61.1] always3(s31) || -> . % 76.04/76.28 84570[76:SSi:84569.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.28 84571[74:Spt:84570.0,84143.0,84144.0] || until2p7(s30)*+ -> . % 76.04/76.28 84572[74:Spt:84570.0,84143.1] || -> node4(s29)*. % 76.04/76.28 84574[74:MRR:831.0,84572.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.28 84577[74:Res:53.1,84574.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.28 84579[74:MRR:84577.0,84133.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 84581[74:Res:84579.0,61.1] always3(s30) || -> . % 76.04/76.28 84582[74:SSi:84581.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.28 84583[72:Spt:84582.0,84049.0,84052.0] || trans(s49,s29)*+ -> . % 76.04/76.28 84584[72:Spt:84582.0,84049.1,84049.2,84049.3,84049.4,84049.5,84049.6,84049.7,84049.8,84049.9,84049.10,84049.11,84049.12,84049.13,84049.14,84049.15,84049.16,84049.17,84049.18,84049.19,84049.20,84049.21,84049.22,84049.23,84049.24,84049.25,84049.26,84049.27] || -> trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 84586[72:MRR:84051.1,84583.0] xuntil6(s49) || -> trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 84587[73:Spt:84584.0] || -> trans(s49,s28)*. % 76.04/76.28 84588[73:Res:84587.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s28)*. % 76.04/76.28 84590[73:Res:84587.0,60.0] || -> node2(s49,s28)*. % 76.04/76.28 84591[73:SSi:84588.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s28)*. % 76.04/76.28 84592[73:Res:84590.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 84664[73:SoR:84592.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 84666[73:SoR:84664.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)* xuntil6(s49). % 76.04/76.28 84667[73:SSi:84666.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s28,c_busy)* xuntil6(s49). % 76.04/76.28 84668[74:Spt:84667.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 84670[74:Res:84668.0,61.1] always3(s28) || -> . % 76.04/76.28 84671[74:SSi:84670.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.28 84672[74:Spt:84671.0,84667.1,84668.0] || m_main_v_state(s28,c_busy)*+ -> . % 76.04/76.28 84673[74:Spt:84671.0,84667.0,84667.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 84677[74:MRR:84664.2,84672.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 84678[74:Res:53.1,84673.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 84680[74:MRR:84678.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 84681[74:MRR:84591.0,84680.0] || -> until2p7(s28)*. % 76.04/76.28 84682[74:MRR:224.0,84681.0] || -> until2p7(s29)* node4(s28). % 76.04/76.28 84683[75:Spt:84682.0] || -> until2p7(s29)*. % 76.04/76.28 84684[75:MRR:225.0,84683.0] || -> until2p7(s30)* node4(s29). % 76.04/76.28 84685[76:Spt:84684.0] || -> until2p7(s30)*. % 76.04/76.28 84686[76:MRR:226.0,84685.0] || -> until2p7(s31)* node4(s30). % 76.04/76.28 84687[77:Spt:84686.0] || -> until2p7(s31)*. % 76.04/76.28 84688[77:MRR:227.0,84687.0] || -> until2p7(s32)* node4(s31). % 76.04/76.28 84689[78:Spt:84688.0] || -> until2p7(s32)*. % 76.04/76.28 84690[78:MRR:228.0,84689.0] || -> until2p7(s33)* node4(s32). % 76.04/76.28 84691[79:Spt:84690.0] || -> until2p7(s33)*. % 76.04/76.28 84692[79:MRR:229.0,84691.0] || -> until2p7(s34)* node4(s33). % 76.04/76.28 84693[80:Spt:84692.0] || -> until2p7(s34)*. % 76.04/76.28 84694[80:MRR:230.0,84693.0] || -> until2p7(s35)* node4(s34). % 76.04/76.28 84695[81:Spt:84694.0] || -> until2p7(s35)*. % 76.04/76.28 84696[81:MRR:231.0,84695.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 84697[82:Spt:84696.0] || -> until2p7(s36)*. % 76.04/76.28 84698[82:MRR:232.0,84697.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 84699[83:Spt:84698.0] || -> until2p7(s37)*. % 76.04/76.28 84700[83:MRR:235.0,84699.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 84701[84:Spt:84700.0] || -> until2p7(s38)*. % 76.04/76.28 84702[84:MRR:236.0,84701.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 84703[85:Spt:84702.0] || -> until2p7(s39)*. % 76.04/76.28 84704[85:MRR:237.0,84703.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 84705[86:Spt:84704.0] || -> until2p7(s40)*. % 76.04/76.28 84706[86:MRR:238.0,84705.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 84707[87:Spt:84706.0] || -> until2p7(s41)*. % 76.04/76.28 84708[87:MRR:239.0,84707.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 84709[88:Spt:84708.0] || -> until2p7(s42)*. % 76.04/76.28 84710[88:MRR:240.0,84709.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 84711[89:Spt:84710.0] || -> until2p7(s43)*. % 76.04/76.28 84712[89:MRR:241.0,84711.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 84713[90:Spt:84712.0] || -> until2p7(s44)*. % 76.04/76.28 84714[90:MRR:539.0,84713.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 84715[91:Spt:84714.0] || -> until2p7(s45)*. % 76.04/76.28 84716[91:MRR:544.0,84715.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 84717[92:Spt:84716.0] || -> until2p7(s46)*. % 76.04/76.28 84718[92:MRR:549.0,84717.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 84719[93:Spt:84718.0] || -> until2p7(s47)*. % 76.04/76.28 84720[93:MRR:554.0,84719.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 84721[94:Spt:84720.0] || -> until2p7(s48)*. % 76.04/76.28 84722[94:MRR:559.0,84721.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 84723[95:Spt:84722.0] || -> until2p7(s49)*. % 76.04/76.28 84724[95:MRR:194.0,84723.0] || -> node4(s49)*. % 76.04/76.28 84725[95:MRR:84677.0,84724.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 84729[95:Res:53.1,84725.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 84731[95:MRR:84729.0,78381.0] || -> . % 76.04/76.28 84732[95:Spt:84731.0,84722.0,84723.0] || until2p7(s49)*+ -> . % 76.04/76.28 84733[95:Spt:84731.0,84722.1] || -> node4(s48)*. % 76.04/76.28 84734[95:MRR:78384.0,84733.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 84737[95:Res:53.1,84734.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 84740[95:Res:84737.0,61.1] always3(s48) || -> . % 76.04/76.28 84741[95:SSi:84740.0,78281.0,78387.0,78626.0,84721.0,84733.0] || -> . % 76.04/76.28 84742[94:Spt:84741.0,84720.0,84721.0] || until2p7(s48)*+ -> . % 76.04/76.28 84743[94:Spt:84741.0,84720.1] || -> node4(s47)*. % 76.04/76.28 84745[94:MRR:777.0,84743.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 84757[94:Res:53.1,84745.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 84759[95:Spt:84757.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 84761[95:Res:84759.0,61.1] always3(s47) || -> . % 76.04/76.28 84762[95:SSi:84761.0,78277.0,78280.0,78625.0,84719.0,84743.0] || -> . % 76.04/76.28 84763[95:Spt:84762.0,84757.0,84759.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 84764[95:Spt:84762.0,84757.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 84768[95:Res:84764.0,61.1] always3(s48) || -> . % 76.04/76.28 84769[95:SSi:84768.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 84770[93:Spt:84769.0,84718.0,84719.0] || until2p7(s47)*+ -> . % 76.04/76.28 84771[93:Spt:84769.0,84718.1] || -> node4(s46)*. % 76.04/76.28 84773[93:MRR:780.0,84771.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 84780[93:Res:53.1,84773.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 84785[94:Spt:84780.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 84787[94:Res:84785.0,61.1] always3(s46) || -> . % 76.04/76.28 84788[94:SSi:84787.0,78272.0,78276.0,78624.0,84717.0,84771.0] || -> . % 76.04/76.28 84789[94:Spt:84788.0,84780.0,84785.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 84790[94:Spt:84788.0,84780.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 84794[94:Res:84790.0,61.1] always3(s47) || -> . % 76.04/76.28 84795[94:SSi:84794.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 84796[92:Spt:84795.0,84716.0,84717.0] || until2p7(s46)*+ -> . % 76.04/76.28 84797[92:Spt:84795.0,84716.1] || -> node4(s45)*. % 76.04/76.28 84799[92:MRR:783.0,84797.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 84802[92:Res:53.1,84799.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 84804[93:Spt:84802.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 84806[93:Res:84804.0,61.1] always3(s45) || -> . % 76.04/76.28 84807[93:SSi:84806.0,78268.0,78271.0,78623.0,84715.0,84797.0] || -> . % 76.04/76.28 84808[93:Spt:84807.0,84802.0,84804.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 84809[93:Spt:84807.0,84802.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 84813[93:Res:84809.0,61.1] always3(s46) || -> . % 76.04/76.28 84814[93:SSi:84813.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 84815[91:Spt:84814.0,84714.0,84715.0] || until2p7(s45)*+ -> . % 76.04/76.28 84816[91:Spt:84814.0,84714.1] || -> node4(s44)*. % 76.04/76.28 84818[91:MRR:786.0,84816.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 84821[91:Res:53.1,84818.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 84823[92:Spt:84821.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 84825[92:Res:84823.0,61.1] always3(s44) || -> . % 76.04/76.28 84826[92:SSi:84825.0,78263.0,78267.0,78622.0,84713.0,84816.0] || -> . % 76.04/76.28 84827[92:Spt:84826.0,84821.0,84823.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 84828[92:Spt:84826.0,84821.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 84832[92:Res:84828.0,61.1] always3(s45) || -> . % 76.04/76.28 84833[92:SSi:84832.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 84834[90:Spt:84833.0,84712.0,84713.0] || until2p7(s44)*+ -> . % 76.04/76.28 84835[90:Spt:84833.0,84712.1] || -> node4(s43)*. % 76.04/76.28 84837[90:MRR:789.0,84835.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 84840[90:Res:53.1,84837.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 84842[91:Spt:84840.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 84844[91:Res:84842.0,61.1] always3(s43) || -> . % 76.04/76.28 84845[91:SSi:84844.0,78259.0,78262.0,78621.0,84711.0,84835.0] || -> . % 76.04/76.28 84846[91:Spt:84845.0,84840.0,84842.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 84847[91:Spt:84845.0,84840.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 84851[91:Res:84847.0,61.1] always3(s44) || -> . % 76.04/76.28 84852[91:SSi:84851.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 84853[89:Spt:84852.0,84710.0,84711.0] || until2p7(s43)*+ -> . % 76.04/76.28 84854[89:Spt:84852.0,84710.1] || -> node4(s42)*. % 76.04/76.28 84856[89:MRR:792.0,84854.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 84859[89:Res:53.1,84856.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 84864[90:Spt:84859.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 84866[90:Res:84864.0,61.1] always3(s42) || -> . % 76.04/76.28 84867[90:SSi:84866.0,78254.0,78258.0,78620.0,84709.0,84854.0] || -> . % 76.04/76.28 84868[90:Spt:84867.0,84859.0,84864.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 84869[90:Spt:84867.0,84859.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 84873[90:Res:84869.0,61.1] always3(s43) || -> . % 76.04/76.28 84874[90:SSi:84873.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 84875[88:Spt:84874.0,84708.0,84709.0] || until2p7(s42)*+ -> . % 76.04/76.28 84876[88:Spt:84874.0,84708.1] || -> node4(s41)*. % 76.04/76.28 84878[88:MRR:795.0,84876.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 84881[88:Res:53.1,84878.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 84883[89:Spt:84881.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 84885[89:Res:84883.0,61.1] always3(s41) || -> . % 76.04/76.28 84886[89:SSi:84885.0,78250.0,78253.0,78619.0,84707.0,84876.0] || -> . % 76.04/76.28 84887[89:Spt:84886.0,84881.0,84883.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 84888[89:Spt:84886.0,84881.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 84892[89:Res:84888.0,61.1] always3(s42) || -> . % 76.04/76.28 84893[89:SSi:84892.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 84894[87:Spt:84893.0,84706.0,84707.0] || until2p7(s41)*+ -> . % 76.04/76.28 84895[87:Spt:84893.0,84706.1] || -> node4(s40)*. % 76.04/76.28 84897[87:MRR:798.0,84895.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 84900[87:Res:53.1,84897.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 84902[88:Spt:84900.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 84904[88:Res:84902.0,61.1] always3(s40) || -> . % 76.04/76.28 84905[88:SSi:84904.0,78245.0,78249.0,78618.0,84705.0,84895.0] || -> . % 76.04/76.28 84906[88:Spt:84905.0,84900.0,84902.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 84907[88:Spt:84905.0,84900.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 84911[88:Res:84907.0,61.1] always3(s41) || -> . % 76.04/76.28 84912[88:SSi:84911.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 84913[86:Spt:84912.0,84704.0,84705.0] || until2p7(s40)*+ -> . % 76.04/76.28 84914[86:Spt:84912.0,84704.1] || -> node4(s39)*. % 76.04/76.28 84916[86:MRR:801.0,84914.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 84919[86:Res:53.1,84916.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 84921[87:Spt:84919.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 84923[87:Res:84921.0,61.1] always3(s39) || -> . % 76.04/76.28 84924[87:SSi:84923.0,78241.0,78244.0,78617.0,84703.0,84914.0] || -> . % 76.04/76.28 84925[87:Spt:84924.0,84919.0,84921.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 84926[87:Spt:84924.0,84919.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 84930[87:Res:84926.0,61.1] always3(s40) || -> . % 76.04/76.28 84931[87:SSi:84930.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 84932[85:Spt:84931.0,84702.0,84703.0] || until2p7(s39)*+ -> . % 76.04/76.28 84933[85:Spt:84931.0,84702.1] || -> node4(s38)*. % 76.04/76.28 84935[85:MRR:804.0,84933.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 84938[85:Res:53.1,84935.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 84943[86:Spt:84938.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 84945[86:Res:84943.0,61.1] always3(s38) || -> . % 76.04/76.28 84946[86:SSi:84945.0,78236.0,78240.0,78616.0,84701.0,84933.0] || -> . % 76.04/76.28 84947[86:Spt:84946.0,84938.0,84943.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 84948[86:Spt:84946.0,84938.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 84952[86:Res:84948.0,61.1] always3(s39) || -> . % 76.04/76.28 84953[86:SSi:84952.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 84954[84:Spt:84953.0,84700.0,84701.0] || until2p7(s38)*+ -> . % 76.04/76.28 84955[84:Spt:84953.0,84700.1] || -> node4(s37)*. % 76.04/76.28 84957[84:MRR:807.0,84955.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 84960[84:Res:53.1,84957.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 84962[85:Spt:84960.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 84964[85:Res:84962.0,61.1] always3(s37) || -> . % 76.04/76.28 84965[85:SSi:84964.0,78232.0,78235.0,78615.0,84699.0,84955.0] || -> . % 76.04/76.28 84966[85:Spt:84965.0,84960.0,84962.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 84967[85:Spt:84965.0,84960.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 84971[85:Res:84967.0,61.1] always3(s38) || -> . % 76.04/76.28 84972[85:SSi:84971.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 84973[83:Spt:84972.0,84698.0,84699.0] || until2p7(s37)*+ -> . % 76.04/76.28 84974[83:Spt:84972.0,84698.1] || -> node4(s36)*. % 76.04/76.28 84976[83:MRR:810.0,84974.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 84979[83:Res:53.1,84976.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 84981[84:Spt:84979.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 84983[84:Res:84981.0,61.1] always3(s36) || -> . % 76.04/76.28 84984[84:SSi:84983.0,78227.0,78231.0,78614.0,84697.0,84974.0] || -> . % 76.04/76.28 84985[84:Spt:84984.0,84979.0,84981.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 84986[84:Spt:84984.0,84979.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 84990[84:Res:84986.0,61.1] always3(s37) || -> . % 76.04/76.28 84991[84:SSi:84990.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 84992[82:Spt:84991.0,84696.0,84697.0] || until2p7(s36)*+ -> . % 76.04/76.28 84993[82:Spt:84991.0,84696.1] || -> node4(s35)*. % 76.04/76.28 84995[82:MRR:813.0,84993.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 84998[82:Res:53.1,84995.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 85000[83:Spt:84998.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 85002[83:Res:85000.0,61.1] always3(s35) || -> . % 76.04/76.28 85003[83:SSi:85002.0,78223.0,78226.0,78613.0,84695.0,84993.0] || -> . % 76.04/76.28 85004[83:Spt:85003.0,84998.0,85000.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.28 85005[83:Spt:85003.0,84998.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 85009[83:Res:85005.0,61.1] always3(s36) || -> . % 76.04/76.28 85010[83:SSi:85009.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 85011[81:Spt:85010.0,84694.0,84695.0] || until2p7(s35)*+ -> . % 76.04/76.28 85012[81:Spt:85010.0,84694.1] || -> node4(s34)*. % 76.04/76.28 85014[81:MRR:816.0,85012.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.28 85017[81:Res:53.1,85014.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.28 85022[82:Spt:85017.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 85024[82:Res:85022.0,61.1] always3(s34) || -> . % 76.04/76.28 85025[82:SSi:85024.0,78218.0,78222.0,78612.0,84693.0,85012.0] || -> . % 76.04/76.28 85026[82:Spt:85025.0,85017.0,85022.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.28 85027[82:Spt:85025.0,85017.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 85031[82:Res:85027.0,61.1] always3(s35) || -> . % 76.04/76.28 85032[82:SSi:85031.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 85033[80:Spt:85032.0,84692.0,84693.0] || until2p7(s34)*+ -> . % 76.04/76.28 85034[80:Spt:85032.0,84692.1] || -> node4(s33)*. % 76.04/76.28 85036[80:MRR:819.0,85034.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.28 85039[80:Res:53.1,85036.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.28 85041[81:Spt:85039.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 85043[81:Res:85041.0,61.1] always3(s33) || -> . % 76.04/76.28 85044[81:SSi:85043.0,78214.0,78217.0,78611.0,84691.0,85034.0] || -> . % 76.04/76.28 85045[81:Spt:85044.0,85039.0,85041.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.28 85046[81:Spt:85044.0,85039.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 85050[81:Res:85046.0,61.1] always3(s34) || -> . % 76.04/76.28 85051[81:SSi:85050.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.28 85052[79:Spt:85051.0,84690.0,84691.0] || until2p7(s33)*+ -> . % 76.04/76.28 85053[79:Spt:85051.0,84690.1] || -> node4(s32)*. % 76.04/76.28 85055[79:MRR:822.0,85053.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.28 85058[79:Res:53.1,85055.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.28 85060[80:Spt:85058.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 85062[80:Res:85060.0,61.1] always3(s32) || -> . % 76.04/76.28 85063[80:SSi:85062.0,78209.0,78213.0,78610.0,84689.0,85053.0] || -> . % 76.04/76.28 85064[80:Spt:85063.0,85058.0,85060.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.28 85065[80:Spt:85063.0,85058.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 85069[80:Res:85065.0,61.1] always3(s33) || -> . % 76.04/76.28 85070[80:SSi:85069.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.28 85071[78:Spt:85070.0,84688.0,84689.0] || until2p7(s32)*+ -> . % 76.04/76.28 85072[78:Spt:85070.0,84688.1] || -> node4(s31)*. % 76.04/76.28 85074[78:MRR:825.0,85072.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.28 85077[78:Res:53.1,85074.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.28 85079[79:Spt:85077.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 85081[79:Res:85079.0,61.1] always3(s31) || -> . % 76.04/76.28 85082[79:SSi:85081.0,78205.0,78208.0,78609.0,84687.0,85072.0] || -> . % 76.04/76.28 85083[79:Spt:85082.0,85077.0,85079.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.28 85084[79:Spt:85082.0,85077.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 85088[79:Res:85084.0,61.1] always3(s32) || -> . % 76.04/76.28 85089[79:SSi:85088.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.28 85090[77:Spt:85089.0,84686.0,84687.0] || until2p7(s31)*+ -> . % 76.04/76.28 85091[77:Spt:85089.0,84686.1] || -> node4(s30)*. % 76.04/76.28 85093[77:MRR:828.0,85091.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.28 85096[77:Res:53.1,85093.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.28 85101[78:Spt:85096.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 85103[78:Res:85101.0,61.1] always3(s30) || -> . % 76.04/76.28 85104[78:SSi:85103.0,78200.0,78204.0,78608.0,84685.0,85091.0] || -> . % 76.04/76.28 85105[78:Spt:85104.0,85096.0,85101.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.28 85106[78:Spt:85104.0,85096.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 85110[78:Res:85106.0,61.1] always3(s31) || -> . % 76.04/76.28 85111[78:SSi:85110.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.28 85112[76:Spt:85111.0,84684.0,84685.0] || until2p7(s30)*+ -> . % 76.04/76.28 85113[76:Spt:85111.0,84684.1] || -> node4(s29)*. % 76.04/76.28 85115[76:MRR:831.0,85113.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.28 85118[76:Res:53.1,85115.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.28 85120[77:Spt:85118.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 85122[77:Res:85120.0,61.1] always3(s29) || -> . % 76.04/76.28 85123[77:SSi:85122.0,78196.0,78199.0,78607.0,84683.0,85113.0] || -> . % 76.04/76.28 85124[77:Spt:85123.0,85118.0,85120.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.28 85125[77:Spt:85123.0,85118.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 85129[77:Res:85125.0,61.1] always3(s30) || -> . % 76.04/76.28 85130[77:SSi:85129.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.28 85131[75:Spt:85130.0,84682.0,84683.0] || until2p7(s29)*+ -> . % 76.04/76.28 85132[75:Spt:85130.0,84682.1] || -> node4(s28)*. % 76.04/76.28 85134[75:MRR:834.0,85132.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.28 85137[75:Res:53.1,85134.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.28 85139[75:MRR:85137.0,84672.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 85141[75:Res:85139.0,61.1] always3(s29) || -> . % 76.04/76.28 85142[75:SSi:85141.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.28 85143[73:Spt:85142.0,84584.0,84587.0] || trans(s49,s28)*+ -> . % 76.04/76.28 85144[73:Spt:85142.0,84584.1,84584.2,84584.3,84584.4,84584.5,84584.6,84584.7,84584.8,84584.9,84584.10,84584.11,84584.12,84584.13,84584.14,84584.15,84584.16,84584.17,84584.18,84584.19,84584.20,84584.21,84584.22,84584.23,84584.24,84584.25,84584.26] || -> trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 85146[73:MRR:84586.1,85143.0] xuntil6(s49) || -> trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 85147[74:Spt:85144.0] || -> trans(s49,s27)*. % 76.04/76.28 85148[74:Res:85147.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s27)*. % 76.04/76.28 85150[74:Res:85147.0,60.0] || -> node2(s49,s27)*. % 76.04/76.28 85151[74:SSi:85148.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s27)*. % 76.04/76.28 85152[74:Res:85150.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)*. % 76.04/76.28 85228[74:SoR:85152.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)*. % 76.04/76.28 85230[74:SoR:85228.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)* xuntil6(s49). % 76.04/76.28 85231[74:SSi:85230.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s27,c_busy)* xuntil6(s49). % 76.04/76.28 85232[75:Spt:85231.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.28 85234[75:Res:85232.0,61.1] always3(s27) || -> . % 76.04/76.28 85235[75:SSi:85234.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.28 85236[75:Spt:85235.0,85231.1,85232.0] || m_main_v_state(s27,c_busy)*+ -> . % 76.04/76.28 85237[75:Spt:85235.0,85231.0,85231.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 85241[75:MRR:85228.2,85236.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 85242[75:Res:53.1,85237.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 85244[75:MRR:85242.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 85245[75:MRR:85151.0,85244.0] || -> until2p7(s27)*. % 76.04/76.28 85246[75:MRR:223.0,85245.0] || -> until2p7(s28)* node4(s27). % 76.04/76.28 85247[76:Spt:85246.0] || -> until2p7(s28)*. % 76.04/76.28 85248[76:MRR:224.0,85247.0] || -> until2p7(s29)* node4(s28). % 76.04/76.28 85249[77:Spt:85248.0] || -> until2p7(s29)*. % 76.04/76.28 85250[77:MRR:225.0,85249.0] || -> until2p7(s30)* node4(s29). % 76.04/76.28 85251[78:Spt:85250.0] || -> until2p7(s30)*. % 76.04/76.28 85252[78:MRR:226.0,85251.0] || -> until2p7(s31)* node4(s30). % 76.04/76.28 85253[79:Spt:85252.0] || -> until2p7(s31)*. % 76.04/76.28 85254[79:MRR:227.0,85253.0] || -> until2p7(s32)* node4(s31). % 76.04/76.28 85255[80:Spt:85254.0] || -> until2p7(s32)*. % 76.04/76.28 85256[80:MRR:228.0,85255.0] || -> until2p7(s33)* node4(s32). % 76.04/76.28 85257[81:Spt:85256.0] || -> until2p7(s33)*. % 76.04/76.28 85258[81:MRR:229.0,85257.0] || -> until2p7(s34)* node4(s33). % 76.04/76.28 85259[82:Spt:85258.0] || -> until2p7(s34)*. % 76.04/76.28 85260[82:MRR:230.0,85259.0] || -> until2p7(s35)* node4(s34). % 76.04/76.28 85261[83:Spt:85260.0] || -> until2p7(s35)*. % 76.04/76.28 85262[83:MRR:231.0,85261.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 85263[84:Spt:85262.0] || -> until2p7(s36)*. % 76.04/76.28 85264[84:MRR:232.0,85263.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 85265[85:Spt:85264.0] || -> until2p7(s37)*. % 76.04/76.28 85266[85:MRR:235.0,85265.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 85267[86:Spt:85266.0] || -> until2p7(s38)*. % 76.04/76.28 85268[86:MRR:236.0,85267.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 85269[87:Spt:85268.0] || -> until2p7(s39)*. % 76.04/76.28 85270[87:MRR:237.0,85269.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 85271[88:Spt:85270.0] || -> until2p7(s40)*. % 76.04/76.28 85272[88:MRR:238.0,85271.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 85273[89:Spt:85272.0] || -> until2p7(s41)*. % 76.04/76.28 85274[89:MRR:239.0,85273.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 85275[90:Spt:85274.0] || -> until2p7(s42)*. % 76.04/76.28 85276[90:MRR:240.0,85275.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 85277[91:Spt:85276.0] || -> until2p7(s43)*. % 76.04/76.28 85278[91:MRR:241.0,85277.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 85279[92:Spt:85278.0] || -> until2p7(s44)*. % 76.04/76.28 85280[92:MRR:539.0,85279.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 85281[93:Spt:85280.0] || -> until2p7(s45)*. % 76.04/76.28 85282[93:MRR:544.0,85281.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 85283[94:Spt:85282.0] || -> until2p7(s46)*. % 76.04/76.28 85284[94:MRR:549.0,85283.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 85285[95:Spt:85284.0] || -> until2p7(s47)*. % 76.04/76.28 85286[95:MRR:554.0,85285.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 85287[96:Spt:85286.0] || -> until2p7(s48)*. % 76.04/76.28 85288[96:MRR:559.0,85287.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 85289[97:Spt:85288.0] || -> until2p7(s49)*. % 76.04/76.28 85290[97:MRR:194.0,85289.0] || -> node4(s49)*. % 76.04/76.28 85291[97:MRR:85241.0,85290.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 85292[97:Res:53.1,85291.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 85294[97:MRR:85292.0,78381.0] || -> . % 76.04/76.28 85295[97:Spt:85294.0,85288.0,85289.0] || until2p7(s49)*+ -> . % 76.04/76.28 85296[97:Spt:85294.0,85288.1] || -> node4(s48)*. % 76.04/76.28 85297[97:MRR:78384.0,85296.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 85300[97:Res:53.1,85297.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 85303[97:Res:85300.0,61.1] always3(s48) || -> . % 76.04/76.28 85304[97:SSi:85303.0,78281.0,78387.0,78626.0,85287.0,85296.0] || -> . % 76.04/76.28 85305[96:Spt:85304.0,85286.0,85287.0] || until2p7(s48)*+ -> . % 76.04/76.28 85306[96:Spt:85304.0,85286.1] || -> node4(s47)*. % 76.04/76.28 85308[96:MRR:777.0,85306.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 85323[96:Res:53.1,85308.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 85328[97:Spt:85323.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 85330[97:Res:85328.0,61.1] always3(s47) || -> . % 76.04/76.28 85331[97:SSi:85330.0,78277.0,78280.0,78625.0,85285.0,85306.0] || -> . % 76.04/76.28 85332[97:Spt:85331.0,85323.0,85328.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 85333[97:Spt:85331.0,85323.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 85337[97:Res:85333.0,61.1] always3(s48) || -> . % 76.04/76.28 85338[97:SSi:85337.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 85339[95:Spt:85338.0,85284.0,85285.0] || until2p7(s47)*+ -> . % 76.04/76.28 85340[95:Spt:85338.0,85284.1] || -> node4(s46)*. % 76.04/76.28 85342[95:MRR:780.0,85340.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 85349[95:Res:53.1,85342.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 85351[96:Spt:85349.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 85353[96:Res:85351.0,61.1] always3(s46) || -> . % 76.04/76.28 85354[96:SSi:85353.0,78272.0,78276.0,78624.0,85283.0,85340.0] || -> . % 76.04/76.28 85355[96:Spt:85354.0,85349.0,85351.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 85356[96:Spt:85354.0,85349.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 85360[96:Res:85356.0,61.1] always3(s47) || -> . % 76.04/76.28 85361[96:SSi:85360.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 85362[94:Spt:85361.0,85282.0,85283.0] || until2p7(s46)*+ -> . % 76.04/76.28 85363[94:Spt:85361.0,85282.1] || -> node4(s45)*. % 76.04/76.28 85365[94:MRR:783.0,85363.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 85368[94:Res:53.1,85365.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 85373[95:Spt:85368.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 85375[95:Res:85373.0,61.1] always3(s45) || -> . % 76.04/76.28 85376[95:SSi:85375.0,78268.0,78271.0,78623.0,85281.0,85363.0] || -> . % 76.04/76.28 85377[95:Spt:85376.0,85368.0,85373.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 85378[95:Spt:85376.0,85368.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 85382[95:Res:85378.0,61.1] always3(s46) || -> . % 76.04/76.28 85383[95:SSi:85382.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 85384[93:Spt:85383.0,85280.0,85281.0] || until2p7(s45)*+ -> . % 76.04/76.28 85385[93:Spt:85383.0,85280.1] || -> node4(s44)*. % 76.04/76.28 85387[93:MRR:786.0,85385.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 85390[93:Res:53.1,85387.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 85392[94:Spt:85390.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 85394[94:Res:85392.0,61.1] always3(s44) || -> . % 76.04/76.28 85395[94:SSi:85394.0,78263.0,78267.0,78622.0,85279.0,85385.0] || -> . % 76.04/76.28 85396[94:Spt:85395.0,85390.0,85392.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 85397[94:Spt:85395.0,85390.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 85401[94:Res:85397.0,61.1] always3(s45) || -> . % 76.04/76.28 85402[94:SSi:85401.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 85403[92:Spt:85402.0,85278.0,85279.0] || until2p7(s44)*+ -> . % 76.04/76.28 85404[92:Spt:85402.0,85278.1] || -> node4(s43)*. % 76.04/76.28 85406[92:MRR:789.0,85404.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 85409[92:Res:53.1,85406.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 85411[93:Spt:85409.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 85413[93:Res:85411.0,61.1] always3(s43) || -> . % 76.04/76.28 85414[93:SSi:85413.0,78259.0,78262.0,78621.0,85277.0,85404.0] || -> . % 76.04/76.28 85415[93:Spt:85414.0,85409.0,85411.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 85416[93:Spt:85414.0,85409.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 85420[93:Res:85416.0,61.1] always3(s44) || -> . % 76.04/76.28 85421[93:SSi:85420.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 85422[91:Spt:85421.0,85276.0,85277.0] || until2p7(s43)*+ -> . % 76.04/76.28 85423[91:Spt:85421.0,85276.1] || -> node4(s42)*. % 76.04/76.28 85425[91:MRR:792.0,85423.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 85428[91:Res:53.1,85425.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 85430[92:Spt:85428.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 85432[92:Res:85430.0,61.1] always3(s42) || -> . % 76.04/76.28 85433[92:SSi:85432.0,78254.0,78258.0,78620.0,85275.0,85423.0] || -> . % 76.04/76.28 85434[92:Spt:85433.0,85428.0,85430.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 85435[92:Spt:85433.0,85428.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 85439[92:Res:85435.0,61.1] always3(s43) || -> . % 76.04/76.28 85440[92:SSi:85439.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 85441[90:Spt:85440.0,85274.0,85275.0] || until2p7(s42)*+ -> . % 76.04/76.28 85442[90:Spt:85440.0,85274.1] || -> node4(s41)*. % 76.04/76.28 85444[90:MRR:795.0,85442.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 85447[90:Res:53.1,85444.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 85452[91:Spt:85447.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 85454[91:Res:85452.0,61.1] always3(s41) || -> . % 76.04/76.28 85455[91:SSi:85454.0,78250.0,78253.0,78619.0,85273.0,85442.0] || -> . % 76.04/76.28 85456[91:Spt:85455.0,85447.0,85452.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 85457[91:Spt:85455.0,85447.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 85461[91:Res:85457.0,61.1] always3(s42) || -> . % 76.04/76.28 85462[91:SSi:85461.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 85463[89:Spt:85462.0,85272.0,85273.0] || until2p7(s41)*+ -> . % 76.04/76.28 85464[89:Spt:85462.0,85272.1] || -> node4(s40)*. % 76.04/76.28 85466[89:MRR:798.0,85464.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 85469[89:Res:53.1,85466.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 85471[90:Spt:85469.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 85473[90:Res:85471.0,61.1] always3(s40) || -> . % 76.04/76.28 85474[90:SSi:85473.0,78245.0,78249.0,78618.0,85271.0,85464.0] || -> . % 76.04/76.28 85475[90:Spt:85474.0,85469.0,85471.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 85476[90:Spt:85474.0,85469.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 85480[90:Res:85476.0,61.1] always3(s41) || -> . % 76.04/76.28 85481[90:SSi:85480.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 85482[88:Spt:85481.0,85270.0,85271.0] || until2p7(s40)*+ -> . % 76.04/76.28 85483[88:Spt:85481.0,85270.1] || -> node4(s39)*. % 76.04/76.28 85485[88:MRR:801.0,85483.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 85488[88:Res:53.1,85485.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 85490[89:Spt:85488.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 85492[89:Res:85490.0,61.1] always3(s39) || -> . % 76.04/76.28 85493[89:SSi:85492.0,78241.0,78244.0,78617.0,85269.0,85483.0] || -> . % 76.04/76.28 85494[89:Spt:85493.0,85488.0,85490.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 85495[89:Spt:85493.0,85488.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 85499[89:Res:85495.0,61.1] always3(s40) || -> . % 76.04/76.28 85500[89:SSi:85499.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 85501[87:Spt:85500.0,85268.0,85269.0] || until2p7(s39)*+ -> . % 76.04/76.28 85502[87:Spt:85500.0,85268.1] || -> node4(s38)*. % 76.04/76.28 85504[87:MRR:804.0,85502.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 85507[87:Res:53.1,85504.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 85509[88:Spt:85507.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 85511[88:Res:85509.0,61.1] always3(s38) || -> . % 76.04/76.28 85512[88:SSi:85511.0,78236.0,78240.0,78616.0,85267.0,85502.0] || -> . % 76.04/76.28 85513[88:Spt:85512.0,85507.0,85509.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 85514[88:Spt:85512.0,85507.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 85518[88:Res:85514.0,61.1] always3(s39) || -> . % 76.04/76.28 85519[88:SSi:85518.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 85520[86:Spt:85519.0,85266.0,85267.0] || until2p7(s38)*+ -> . % 76.04/76.28 85521[86:Spt:85519.0,85266.1] || -> node4(s37)*. % 76.04/76.28 85523[86:MRR:807.0,85521.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 85526[86:Res:53.1,85523.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 85531[87:Spt:85526.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 85533[87:Res:85531.0,61.1] always3(s37) || -> . % 76.04/76.28 85534[87:SSi:85533.0,78232.0,78235.0,78615.0,85265.0,85521.0] || -> . % 76.04/76.28 85535[87:Spt:85534.0,85526.0,85531.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 85536[87:Spt:85534.0,85526.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 85540[87:Res:85536.0,61.1] always3(s38) || -> . % 76.04/76.28 85541[87:SSi:85540.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 85542[85:Spt:85541.0,85264.0,85265.0] || until2p7(s37)*+ -> . % 76.04/76.28 85543[85:Spt:85541.0,85264.1] || -> node4(s36)*. % 76.04/76.28 85545[85:MRR:810.0,85543.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 85548[85:Res:53.1,85545.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 85550[86:Spt:85548.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 85552[86:Res:85550.0,61.1] always3(s36) || -> . % 76.04/76.28 85553[86:SSi:85552.0,78227.0,78231.0,78614.0,85263.0,85543.0] || -> . % 76.04/76.28 85554[86:Spt:85553.0,85548.0,85550.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 85555[86:Spt:85553.0,85548.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 85559[86:Res:85555.0,61.1] always3(s37) || -> . % 76.04/76.28 85560[86:SSi:85559.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 85561[84:Spt:85560.0,85262.0,85263.0] || until2p7(s36)*+ -> . % 76.04/76.28 85562[84:Spt:85560.0,85262.1] || -> node4(s35)*. % 76.04/76.28 85564[84:MRR:813.0,85562.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 85567[84:Res:53.1,85564.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 85569[85:Spt:85567.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 85571[85:Res:85569.0,61.1] always3(s35) || -> . % 76.04/76.28 85572[85:SSi:85571.0,78223.0,78226.0,78613.0,85261.0,85562.0] || -> . % 76.04/76.28 85573[85:Spt:85572.0,85567.0,85569.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.28 85574[85:Spt:85572.0,85567.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 85578[85:Res:85574.0,61.1] always3(s36) || -> . % 76.04/76.28 85579[85:SSi:85578.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 85580[83:Spt:85579.0,85260.0,85261.0] || until2p7(s35)*+ -> . % 76.04/76.28 85581[83:Spt:85579.0,85260.1] || -> node4(s34)*. % 76.04/76.28 85583[83:MRR:816.0,85581.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.28 85586[83:Res:53.1,85583.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.28 85588[84:Spt:85586.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 85590[84:Res:85588.0,61.1] always3(s34) || -> . % 76.04/76.28 85591[84:SSi:85590.0,78218.0,78222.0,78612.0,85259.0,85581.0] || -> . % 76.04/76.28 85592[84:Spt:85591.0,85586.0,85588.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.28 85593[84:Spt:85591.0,85586.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 85597[84:Res:85593.0,61.1] always3(s35) || -> . % 76.04/76.28 85598[84:SSi:85597.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 85599[82:Spt:85598.0,85258.0,85259.0] || until2p7(s34)*+ -> . % 76.04/76.28 85600[82:Spt:85598.0,85258.1] || -> node4(s33)*. % 76.04/76.28 85602[82:MRR:819.0,85600.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.28 85605[82:Res:53.1,85602.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.28 85610[83:Spt:85605.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 85612[83:Res:85610.0,61.1] always3(s33) || -> . % 76.04/76.28 85613[83:SSi:85612.0,78214.0,78217.0,78611.0,85257.0,85600.0] || -> . % 76.04/76.28 85614[83:Spt:85613.0,85605.0,85610.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.28 85615[83:Spt:85613.0,85605.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 85619[83:Res:85615.0,61.1] always3(s34) || -> . % 76.04/76.28 85620[83:SSi:85619.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.28 85621[81:Spt:85620.0,85256.0,85257.0] || until2p7(s33)*+ -> . % 76.04/76.28 85622[81:Spt:85620.0,85256.1] || -> node4(s32)*. % 76.04/76.28 85624[81:MRR:822.0,85622.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.28 85627[81:Res:53.1,85624.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.28 85629[82:Spt:85627.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 85631[82:Res:85629.0,61.1] always3(s32) || -> . % 76.04/76.28 85632[82:SSi:85631.0,78209.0,78213.0,78610.0,85255.0,85622.0] || -> . % 76.04/76.28 85633[82:Spt:85632.0,85627.0,85629.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.28 85634[82:Spt:85632.0,85627.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 85638[82:Res:85634.0,61.1] always3(s33) || -> . % 76.04/76.28 85639[82:SSi:85638.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.28 85640[80:Spt:85639.0,85254.0,85255.0] || until2p7(s32)*+ -> . % 76.04/76.28 85641[80:Spt:85639.0,85254.1] || -> node4(s31)*. % 76.04/76.28 85643[80:MRR:825.0,85641.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.28 85646[80:Res:53.1,85643.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.28 85648[81:Spt:85646.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 85650[81:Res:85648.0,61.1] always3(s31) || -> . % 76.04/76.28 85651[81:SSi:85650.0,78205.0,78208.0,78609.0,85253.0,85641.0] || -> . % 76.04/76.28 85652[81:Spt:85651.0,85646.0,85648.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.28 85653[81:Spt:85651.0,85646.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 85657[81:Res:85653.0,61.1] always3(s32) || -> . % 76.04/76.28 85658[81:SSi:85657.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.28 85659[79:Spt:85658.0,85252.0,85253.0] || until2p7(s31)*+ -> . % 76.04/76.28 85660[79:Spt:85658.0,85252.1] || -> node4(s30)*. % 76.04/76.28 85662[79:MRR:828.0,85660.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.28 85665[79:Res:53.1,85662.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.28 85667[80:Spt:85665.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 85669[80:Res:85667.0,61.1] always3(s30) || -> . % 76.04/76.28 85670[80:SSi:85669.0,78200.0,78204.0,78608.0,85251.0,85660.0] || -> . % 76.04/76.28 85671[80:Spt:85670.0,85665.0,85667.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.28 85672[80:Spt:85670.0,85665.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 85676[80:Res:85672.0,61.1] always3(s31) || -> . % 76.04/76.28 85677[80:SSi:85676.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.28 85678[78:Spt:85677.0,85250.0,85251.0] || until2p7(s30)*+ -> . % 76.04/76.28 85679[78:Spt:85677.0,85250.1] || -> node4(s29)*. % 76.04/76.28 85681[78:MRR:831.0,85679.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.28 85684[78:Res:53.1,85681.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.28 85689[79:Spt:85684.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 85691[79:Res:85689.0,61.1] always3(s29) || -> . % 76.04/76.28 85692[79:SSi:85691.0,78196.0,78199.0,78607.0,85249.0,85679.0] || -> . % 76.04/76.28 85693[79:Spt:85692.0,85684.0,85689.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.28 85694[79:Spt:85692.0,85684.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 85698[79:Res:85694.0,61.1] always3(s30) || -> . % 76.04/76.28 85699[79:SSi:85698.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.28 85700[77:Spt:85699.0,85248.0,85249.0] || until2p7(s29)*+ -> . % 76.04/76.28 85701[77:Spt:85699.0,85248.1] || -> node4(s28)*. % 76.04/76.28 85703[77:MRR:834.0,85701.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.28 85706[77:Res:53.1,85703.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.28 85708[78:Spt:85706.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 85710[78:Res:85708.0,61.1] always3(s28) || -> . % 76.04/76.28 85711[78:SSi:85710.0,78191.0,78195.0,78606.0,85247.0,85701.0] || -> . % 76.04/76.28 85712[78:Spt:85711.0,85706.0,85708.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.28 85713[78:Spt:85711.0,85706.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 85717[78:Res:85713.0,61.1] always3(s29) || -> . % 76.04/76.28 85718[78:SSi:85717.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.28 85719[76:Spt:85718.0,85246.0,85247.0] || until2p7(s28)*+ -> . % 76.04/76.28 85720[76:Spt:85718.0,85246.1] || -> node4(s27)*. % 76.04/76.28 85722[76:MRR:837.0,85720.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.28 85725[76:Res:53.1,85722.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.28 85727[76:MRR:85725.0,85236.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 85729[76:Res:85727.0,61.1] always3(s28) || -> . % 76.04/76.28 85730[76:SSi:85729.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.28 85731[74:Spt:85730.0,85144.0,85147.0] || trans(s49,s27)*+ -> . % 76.04/76.28 85732[74:Spt:85730.0,85144.1,85144.2,85144.3,85144.4,85144.5,85144.6,85144.7,85144.8,85144.9,85144.10,85144.11,85144.12,85144.13,85144.14,85144.15,85144.16,85144.17,85144.18,85144.19,85144.20,85144.21,85144.22,85144.23,85144.24,85144.25] || -> trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 85734[74:MRR:85146.1,85731.0] xuntil6(s49) || -> trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 85735[75:Spt:85732.0] || -> trans(s49,s26)*. % 76.04/76.28 85736[75:Res:85735.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s26)*. % 76.04/76.28 85738[75:Res:85735.0,60.0] || -> node2(s49,s26)*. % 76.04/76.28 85739[75:SSi:85736.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s26)*. % 76.04/76.28 85740[75:Res:85738.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)*. % 76.04/76.28 85817[75:SoR:85740.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)*. % 76.04/76.28 85819[75:SoR:85817.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)* xuntil6(s49). % 76.04/76.28 85820[75:SSi:85819.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s26,c_busy)* xuntil6(s49). % 76.04/76.28 85821[76:Spt:85820.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.28 85823[76:Res:85821.0,61.1] always3(s26) || -> . % 76.04/76.28 85824[76:SSi:85823.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.28 85825[76:Spt:85824.0,85820.1,85821.0] || m_main_v_state(s26,c_busy)*+ -> . % 76.04/76.28 85826[76:Spt:85824.0,85820.0,85820.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 85830[76:MRR:85817.2,85825.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 85831[76:Res:53.1,85826.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 85833[76:MRR:85831.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 85834[76:MRR:85739.0,85833.0] || -> until2p7(s26)*. % 76.04/76.28 85835[76:MRR:222.0,85834.0] || -> until2p7(s27)* node4(s26). % 76.04/76.28 85836[77:Spt:85835.0] || -> until2p7(s27)*. % 76.04/76.28 85837[77:MRR:223.0,85836.0] || -> until2p7(s28)* node4(s27). % 76.04/76.28 85838[78:Spt:85837.0] || -> until2p7(s28)*. % 76.04/76.28 85839[78:MRR:224.0,85838.0] || -> until2p7(s29)* node4(s28). % 76.04/76.28 85840[79:Spt:85839.0] || -> until2p7(s29)*. % 76.04/76.28 85841[79:MRR:225.0,85840.0] || -> until2p7(s30)* node4(s29). % 76.04/76.28 85842[80:Spt:85841.0] || -> until2p7(s30)*. % 76.04/76.28 85843[80:MRR:226.0,85842.0] || -> until2p7(s31)* node4(s30). % 76.04/76.28 85844[81:Spt:85843.0] || -> until2p7(s31)*. % 76.04/76.28 85845[81:MRR:227.0,85844.0] || -> until2p7(s32)* node4(s31). % 76.04/76.28 85846[82:Spt:85845.0] || -> until2p7(s32)*. % 76.04/76.28 85847[82:MRR:228.0,85846.0] || -> until2p7(s33)* node4(s32). % 76.04/76.28 85848[83:Spt:85847.0] || -> until2p7(s33)*. % 76.04/76.28 85849[83:MRR:229.0,85848.0] || -> until2p7(s34)* node4(s33). % 76.04/76.28 85850[84:Spt:85849.0] || -> until2p7(s34)*. % 76.04/76.28 85851[84:MRR:230.0,85850.0] || -> until2p7(s35)* node4(s34). % 76.04/76.28 85852[85:Spt:85851.0] || -> until2p7(s35)*. % 76.04/76.28 85853[85:MRR:231.0,85852.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 85854[86:Spt:85853.0] || -> until2p7(s36)*. % 76.04/76.28 85855[86:MRR:232.0,85854.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 85856[87:Spt:85855.0] || -> until2p7(s37)*. % 76.04/76.28 85857[87:MRR:235.0,85856.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 85858[88:Spt:85857.0] || -> until2p7(s38)*. % 76.04/76.28 85859[88:MRR:236.0,85858.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 85860[89:Spt:85859.0] || -> until2p7(s39)*. % 76.04/76.28 85861[89:MRR:237.0,85860.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 85862[90:Spt:85861.0] || -> until2p7(s40)*. % 76.04/76.28 85863[90:MRR:238.0,85862.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 85864[91:Spt:85863.0] || -> until2p7(s41)*. % 76.04/76.28 85865[91:MRR:239.0,85864.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 85866[92:Spt:85865.0] || -> until2p7(s42)*. % 76.04/76.28 85867[92:MRR:240.0,85866.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 85868[93:Spt:85867.0] || -> until2p7(s43)*. % 76.04/76.28 85869[93:MRR:241.0,85868.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 85870[94:Spt:85869.0] || -> until2p7(s44)*. % 76.04/76.28 85871[94:MRR:539.0,85870.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 85872[95:Spt:85871.0] || -> until2p7(s45)*. % 76.04/76.28 85873[95:MRR:544.0,85872.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 85874[96:Spt:85873.0] || -> until2p7(s46)*. % 76.04/76.28 85875[96:MRR:549.0,85874.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 85876[97:Spt:85875.0] || -> until2p7(s47)*. % 76.04/76.28 85877[97:MRR:554.0,85876.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 85878[98:Spt:85877.0] || -> until2p7(s48)*. % 76.04/76.28 85879[98:MRR:559.0,85878.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 85880[99:Spt:85879.0] || -> until2p7(s49)*. % 76.04/76.28 85881[99:MRR:194.0,85880.0] || -> node4(s49)*. % 76.04/76.28 85882[99:MRR:85830.0,85881.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 85886[99:Res:53.1,85882.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 85888[99:MRR:85886.0,78381.0] || -> . % 76.04/76.28 85889[99:Spt:85888.0,85879.0,85880.0] || until2p7(s49)*+ -> . % 76.04/76.28 85890[99:Spt:85888.0,85879.1] || -> node4(s48)*. % 76.04/76.28 85891[99:MRR:78384.0,85890.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 85894[99:Res:53.1,85891.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 85897[99:Res:85894.0,61.1] always3(s48) || -> . % 76.04/76.28 85898[99:SSi:85897.0,78281.0,78387.0,78626.0,85878.0,85890.0] || -> . % 76.04/76.28 85899[98:Spt:85898.0,85877.0,85878.0] || until2p7(s48)*+ -> . % 76.04/76.28 85900[98:Spt:85898.0,85877.1] || -> node4(s47)*. % 76.04/76.28 85902[98:MRR:777.0,85900.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 85914[98:Res:53.1,85902.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 85916[99:Spt:85914.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 85918[99:Res:85916.0,61.1] always3(s47) || -> . % 76.04/76.28 85919[99:SSi:85918.0,78277.0,78280.0,78625.0,85876.0,85900.0] || -> . % 76.04/76.28 85920[99:Spt:85919.0,85914.0,85916.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 85921[99:Spt:85919.0,85914.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 85925[99:Res:85921.0,61.1] always3(s48) || -> . % 76.04/76.28 85926[99:SSi:85925.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 85927[97:Spt:85926.0,85875.0,85876.0] || until2p7(s47)*+ -> . % 76.04/76.28 85928[97:Spt:85926.0,85875.1] || -> node4(s46)*. % 76.04/76.28 85930[97:MRR:780.0,85928.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 85937[97:Res:53.1,85930.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 85942[98:Spt:85937.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 85944[98:Res:85942.0,61.1] always3(s46) || -> . % 76.04/76.28 85945[98:SSi:85944.0,78272.0,78276.0,78624.0,85874.0,85928.0] || -> . % 76.04/76.28 85946[98:Spt:85945.0,85937.0,85942.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 85947[98:Spt:85945.0,85937.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 85951[98:Res:85947.0,61.1] always3(s47) || -> . % 76.04/76.28 85952[98:SSi:85951.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 85953[96:Spt:85952.0,85873.0,85874.0] || until2p7(s46)*+ -> . % 76.04/76.28 85954[96:Spt:85952.0,85873.1] || -> node4(s45)*. % 76.04/76.28 85956[96:MRR:783.0,85954.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 85959[96:Res:53.1,85956.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 85961[97:Spt:85959.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 85963[97:Res:85961.0,61.1] always3(s45) || -> . % 76.04/76.28 85964[97:SSi:85963.0,78268.0,78271.0,78623.0,85872.0,85954.0] || -> . % 76.04/76.28 85965[97:Spt:85964.0,85959.0,85961.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 85966[97:Spt:85964.0,85959.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 85970[97:Res:85966.0,61.1] always3(s46) || -> . % 76.04/76.28 85971[97:SSi:85970.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 85972[95:Spt:85971.0,85871.0,85872.0] || until2p7(s45)*+ -> . % 76.04/76.28 85973[95:Spt:85971.0,85871.1] || -> node4(s44)*. % 76.04/76.28 85975[95:MRR:786.0,85973.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 85978[95:Res:53.1,85975.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 85980[96:Spt:85978.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 85982[96:Res:85980.0,61.1] always3(s44) || -> . % 76.04/76.28 85983[96:SSi:85982.0,78263.0,78267.0,78622.0,85870.0,85973.0] || -> . % 76.04/76.28 85984[96:Spt:85983.0,85978.0,85980.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 85985[96:Spt:85983.0,85978.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 85989[96:Res:85985.0,61.1] always3(s45) || -> . % 76.04/76.28 85990[96:SSi:85989.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 85991[94:Spt:85990.0,85869.0,85870.0] || until2p7(s44)*+ -> . % 76.04/76.28 85992[94:Spt:85990.0,85869.1] || -> node4(s43)*. % 76.04/76.28 85994[94:MRR:789.0,85992.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 85997[94:Res:53.1,85994.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 85999[95:Spt:85997.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 86001[95:Res:85999.0,61.1] always3(s43) || -> . % 76.04/76.28 86002[95:SSi:86001.0,78259.0,78262.0,78621.0,85868.0,85992.0] || -> . % 76.04/76.28 86003[95:Spt:86002.0,85997.0,85999.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 86004[95:Spt:86002.0,85997.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 86008[95:Res:86004.0,61.1] always3(s44) || -> . % 76.04/76.28 86009[95:SSi:86008.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 86010[93:Spt:86009.0,85867.0,85868.0] || until2p7(s43)*+ -> . % 76.04/76.28 86011[93:Spt:86009.0,85867.1] || -> node4(s42)*. % 76.04/76.28 86013[93:MRR:792.0,86011.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 86016[93:Res:53.1,86013.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 86021[94:Spt:86016.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 86023[94:Res:86021.0,61.1] always3(s42) || -> . % 76.04/76.28 86024[94:SSi:86023.0,78254.0,78258.0,78620.0,85866.0,86011.0] || -> . % 76.04/76.28 86025[94:Spt:86024.0,86016.0,86021.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 86026[94:Spt:86024.0,86016.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 86030[94:Res:86026.0,61.1] always3(s43) || -> . % 76.04/76.28 86031[94:SSi:86030.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 86032[92:Spt:86031.0,85865.0,85866.0] || until2p7(s42)*+ -> . % 76.04/76.28 86033[92:Spt:86031.0,85865.1] || -> node4(s41)*. % 76.04/76.28 86035[92:MRR:795.0,86033.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 86038[92:Res:53.1,86035.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 86040[93:Spt:86038.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 86042[93:Res:86040.0,61.1] always3(s41) || -> . % 76.04/76.28 86043[93:SSi:86042.0,78250.0,78253.0,78619.0,85864.0,86033.0] || -> . % 76.04/76.28 86044[93:Spt:86043.0,86038.0,86040.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 86045[93:Spt:86043.0,86038.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 86049[93:Res:86045.0,61.1] always3(s42) || -> . % 76.04/76.28 86050[93:SSi:86049.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 86051[91:Spt:86050.0,85863.0,85864.0] || until2p7(s41)*+ -> . % 76.04/76.28 86052[91:Spt:86050.0,85863.1] || -> node4(s40)*. % 76.04/76.28 86054[91:MRR:798.0,86052.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 86057[91:Res:53.1,86054.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 86059[92:Spt:86057.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 86061[92:Res:86059.0,61.1] always3(s40) || -> . % 76.04/76.28 86062[92:SSi:86061.0,78245.0,78249.0,78618.0,85862.0,86052.0] || -> . % 76.04/76.28 86063[92:Spt:86062.0,86057.0,86059.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 86064[92:Spt:86062.0,86057.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 86068[92:Res:86064.0,61.1] always3(s41) || -> . % 76.04/76.28 86069[92:SSi:86068.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 86070[90:Spt:86069.0,85861.0,85862.0] || until2p7(s40)*+ -> . % 76.04/76.28 86071[90:Spt:86069.0,85861.1] || -> node4(s39)*. % 76.04/76.28 86073[90:MRR:801.0,86071.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 86076[90:Res:53.1,86073.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 86078[91:Spt:86076.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 86080[91:Res:86078.0,61.1] always3(s39) || -> . % 76.04/76.28 86081[91:SSi:86080.0,78241.0,78244.0,78617.0,85860.0,86071.0] || -> . % 76.04/76.28 86082[91:Spt:86081.0,86076.0,86078.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 86083[91:Spt:86081.0,86076.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 86087[91:Res:86083.0,61.1] always3(s40) || -> . % 76.04/76.28 86088[91:SSi:86087.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 86089[89:Spt:86088.0,85859.0,85860.0] || until2p7(s39)*+ -> . % 76.04/76.28 86090[89:Spt:86088.0,85859.1] || -> node4(s38)*. % 76.04/76.28 86092[89:MRR:804.0,86090.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 86095[89:Res:53.1,86092.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 86100[90:Spt:86095.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 86102[90:Res:86100.0,61.1] always3(s38) || -> . % 76.04/76.28 86103[90:SSi:86102.0,78236.0,78240.0,78616.0,85858.0,86090.0] || -> . % 76.04/76.28 86104[90:Spt:86103.0,86095.0,86100.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 86105[90:Spt:86103.0,86095.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 86109[90:Res:86105.0,61.1] always3(s39) || -> . % 76.04/76.28 86110[90:SSi:86109.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 86111[88:Spt:86110.0,85857.0,85858.0] || until2p7(s38)*+ -> . % 76.04/76.28 86112[88:Spt:86110.0,85857.1] || -> node4(s37)*. % 76.04/76.28 86114[88:MRR:807.0,86112.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 86117[88:Res:53.1,86114.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 86119[89:Spt:86117.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 86121[89:Res:86119.0,61.1] always3(s37) || -> . % 76.04/76.28 86122[89:SSi:86121.0,78232.0,78235.0,78615.0,85856.0,86112.0] || -> . % 76.04/76.28 86123[89:Spt:86122.0,86117.0,86119.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 86124[89:Spt:86122.0,86117.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 86128[89:Res:86124.0,61.1] always3(s38) || -> . % 76.04/76.28 86129[89:SSi:86128.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 86130[87:Spt:86129.0,85855.0,85856.0] || until2p7(s37)*+ -> . % 76.04/76.28 86131[87:Spt:86129.0,85855.1] || -> node4(s36)*. % 76.04/76.28 86133[87:MRR:810.0,86131.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 86136[87:Res:53.1,86133.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 86138[88:Spt:86136.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 86140[88:Res:86138.0,61.1] always3(s36) || -> . % 76.04/76.28 86141[88:SSi:86140.0,78227.0,78231.0,78614.0,85854.0,86131.0] || -> . % 76.04/76.28 86142[88:Spt:86141.0,86136.0,86138.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 86143[88:Spt:86141.0,86136.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 86147[88:Res:86143.0,61.1] always3(s37) || -> . % 76.04/76.28 86148[88:SSi:86147.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 86149[86:Spt:86148.0,85853.0,85854.0] || until2p7(s36)*+ -> . % 76.04/76.28 86150[86:Spt:86148.0,85853.1] || -> node4(s35)*. % 76.04/76.28 86152[86:MRR:813.0,86150.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 86155[86:Res:53.1,86152.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 86157[87:Spt:86155.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 86159[87:Res:86157.0,61.1] always3(s35) || -> . % 76.04/76.28 86160[87:SSi:86159.0,78223.0,78226.0,78613.0,85852.0,86150.0] || -> . % 76.04/76.28 86161[87:Spt:86160.0,86155.0,86157.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.28 86162[87:Spt:86160.0,86155.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 86166[87:Res:86162.0,61.1] always3(s36) || -> . % 76.04/76.28 86167[87:SSi:86166.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 86168[85:Spt:86167.0,85851.0,85852.0] || until2p7(s35)*+ -> . % 76.04/76.28 86169[85:Spt:86167.0,85851.1] || -> node4(s34)*. % 76.04/76.28 86171[85:MRR:816.0,86169.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.28 86174[85:Res:53.1,86171.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.28 86179[86:Spt:86174.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 86181[86:Res:86179.0,61.1] always3(s34) || -> . % 76.04/76.28 86182[86:SSi:86181.0,78218.0,78222.0,78612.0,85850.0,86169.0] || -> . % 76.04/76.28 86183[86:Spt:86182.0,86174.0,86179.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.28 86184[86:Spt:86182.0,86174.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 86188[86:Res:86184.0,61.1] always3(s35) || -> . % 76.04/76.28 86189[86:SSi:86188.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 86190[84:Spt:86189.0,85849.0,85850.0] || until2p7(s34)*+ -> . % 76.04/76.28 86191[84:Spt:86189.0,85849.1] || -> node4(s33)*. % 76.04/76.28 86193[84:MRR:819.0,86191.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.28 86196[84:Res:53.1,86193.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.28 86198[85:Spt:86196.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 86200[85:Res:86198.0,61.1] always3(s33) || -> . % 76.04/76.28 86201[85:SSi:86200.0,78214.0,78217.0,78611.0,85848.0,86191.0] || -> . % 76.04/76.28 86202[85:Spt:86201.0,86196.0,86198.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.28 86203[85:Spt:86201.0,86196.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 86207[85:Res:86203.0,61.1] always3(s34) || -> . % 76.04/76.28 86208[85:SSi:86207.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.28 86209[83:Spt:86208.0,85847.0,85848.0] || until2p7(s33)*+ -> . % 76.04/76.28 86210[83:Spt:86208.0,85847.1] || -> node4(s32)*. % 76.04/76.28 86212[83:MRR:822.0,86210.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.28 86215[83:Res:53.1,86212.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.28 86217[84:Spt:86215.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 86219[84:Res:86217.0,61.1] always3(s32) || -> . % 76.04/76.28 86220[84:SSi:86219.0,78209.0,78213.0,78610.0,85846.0,86210.0] || -> . % 76.04/76.28 86221[84:Spt:86220.0,86215.0,86217.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.28 86222[84:Spt:86220.0,86215.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 86226[84:Res:86222.0,61.1] always3(s33) || -> . % 76.04/76.28 86227[84:SSi:86226.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.28 86228[82:Spt:86227.0,85845.0,85846.0] || until2p7(s32)*+ -> . % 76.04/76.28 86229[82:Spt:86227.0,85845.1] || -> node4(s31)*. % 76.04/76.28 86231[82:MRR:825.0,86229.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.28 86234[82:Res:53.1,86231.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.28 86236[83:Spt:86234.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 86238[83:Res:86236.0,61.1] always3(s31) || -> . % 76.04/76.28 86239[83:SSi:86238.0,78205.0,78208.0,78609.0,85844.0,86229.0] || -> . % 76.04/76.28 86240[83:Spt:86239.0,86234.0,86236.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.28 86241[83:Spt:86239.0,86234.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 86245[83:Res:86241.0,61.1] always3(s32) || -> . % 76.04/76.28 86246[83:SSi:86245.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.28 86247[81:Spt:86246.0,85843.0,85844.0] || until2p7(s31)*+ -> . % 76.04/76.28 86248[81:Spt:86246.0,85843.1] || -> node4(s30)*. % 76.04/76.28 86250[81:MRR:828.0,86248.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.28 86253[81:Res:53.1,86250.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.28 86258[82:Spt:86253.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 86260[82:Res:86258.0,61.1] always3(s30) || -> . % 76.04/76.28 86261[82:SSi:86260.0,78200.0,78204.0,78608.0,85842.0,86248.0] || -> . % 76.04/76.28 86262[82:Spt:86261.0,86253.0,86258.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.28 86263[82:Spt:86261.0,86253.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 86267[82:Res:86263.0,61.1] always3(s31) || -> . % 76.04/76.28 86268[82:SSi:86267.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.28 86269[80:Spt:86268.0,85841.0,85842.0] || until2p7(s30)*+ -> . % 76.04/76.28 86270[80:Spt:86268.0,85841.1] || -> node4(s29)*. % 76.04/76.28 86272[80:MRR:831.0,86270.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.28 86275[80:Res:53.1,86272.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.28 86277[81:Spt:86275.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 86279[81:Res:86277.0,61.1] always3(s29) || -> . % 76.04/76.28 86280[81:SSi:86279.0,78196.0,78199.0,78607.0,85840.0,86270.0] || -> . % 76.04/76.28 86281[81:Spt:86280.0,86275.0,86277.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.28 86282[81:Spt:86280.0,86275.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 86286[81:Res:86282.0,61.1] always3(s30) || -> . % 76.04/76.28 86287[81:SSi:86286.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.28 86288[79:Spt:86287.0,85839.0,85840.0] || until2p7(s29)*+ -> . % 76.04/76.28 86289[79:Spt:86287.0,85839.1] || -> node4(s28)*. % 76.04/76.28 86291[79:MRR:834.0,86289.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.28 86294[79:Res:53.1,86291.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.28 86296[80:Spt:86294.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 86298[80:Res:86296.0,61.1] always3(s28) || -> . % 76.04/76.28 86299[80:SSi:86298.0,78191.0,78195.0,78606.0,85838.0,86289.0] || -> . % 76.04/76.28 86300[80:Spt:86299.0,86294.0,86296.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.28 86301[80:Spt:86299.0,86294.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 86305[80:Res:86301.0,61.1] always3(s29) || -> . % 76.04/76.28 86306[80:SSi:86305.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.28 86307[78:Spt:86306.0,85837.0,85838.0] || until2p7(s28)*+ -> . % 76.04/76.28 86308[78:Spt:86306.0,85837.1] || -> node4(s27)*. % 76.04/76.28 86310[78:MRR:837.0,86308.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.28 86313[78:Res:53.1,86310.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.28 86315[79:Spt:86313.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.28 86317[79:Res:86315.0,61.1] always3(s27) || -> . % 76.04/76.28 86318[79:SSi:86317.0,78187.0,78190.0,78605.0,85836.0,86308.0] || -> . % 76.04/76.28 86319[79:Spt:86318.0,86313.0,86315.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.28 86320[79:Spt:86318.0,86313.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 86324[79:Res:86320.0,61.1] always3(s28) || -> . % 76.04/76.28 86325[79:SSi:86324.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.28 86326[77:Spt:86325.0,85835.0,85836.0] || until2p7(s27)*+ -> . % 76.04/76.28 86327[77:Spt:86325.0,85835.1] || -> node4(s26)*. % 76.04/76.28 86329[77:MRR:840.0,86327.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.28 86332[77:Res:53.1,86329.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.28 86334[77:MRR:86332.0,85825.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.28 86339[77:Res:86334.0,61.1] always3(s27) || -> . % 76.04/76.28 86340[77:SSi:86339.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.28 86341[75:Spt:86340.0,85732.0,85735.0] || trans(s49,s26)*+ -> . % 76.04/76.28 86342[75:Spt:86340.0,85732.1,85732.2,85732.3,85732.4,85732.5,85732.6,85732.7,85732.8,85732.9,85732.10,85732.11,85732.12,85732.13,85732.14,85732.15,85732.16,85732.17,85732.18,85732.19,85732.20,85732.21,85732.22,85732.23,85732.24] || -> trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 86344[75:MRR:85734.1,86341.0] xuntil6(s49) || -> trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 86345[76:Spt:86342.0] || -> trans(s49,s25)*. % 76.04/76.28 86346[76:Res:86345.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s25)*. % 76.04/76.28 86348[76:Res:86345.0,60.0] || -> node2(s49,s25)*. % 76.04/76.28 86349[76:SSi:86346.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s25)*. % 76.04/76.28 86350[76:Res:86348.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)*. % 76.04/76.28 86431[76:SoR:86350.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)*. % 76.04/76.28 86433[76:SoR:86431.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)* xuntil6(s49). % 76.04/76.28 86434[76:SSi:86433.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s25,c_busy)* xuntil6(s49). % 76.04/76.28 86435[77:Spt:86434.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.28 86437[77:Res:86435.0,61.1] always3(s25) || -> . % 76.04/76.28 86438[77:SSi:86437.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.28 86439[77:Spt:86438.0,86434.1,86435.0] || m_main_v_state(s25,c_busy)*+ -> . % 76.04/76.28 86440[77:Spt:86438.0,86434.0,86434.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 86444[77:MRR:86431.2,86439.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 86445[77:Res:53.1,86440.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 86447[77:MRR:86445.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 86448[77:MRR:86349.0,86447.0] || -> until2p7(s25)*. % 76.04/76.28 86449[77:MRR:221.0,86448.0] || -> until2p7(s26)* node4(s25). % 76.04/76.28 86450[78:Spt:86449.0] || -> until2p7(s26)*. % 76.04/76.28 86451[78:MRR:222.0,86450.0] || -> until2p7(s27)* node4(s26). % 76.04/76.28 86452[79:Spt:86451.0] || -> until2p7(s27)*. % 76.04/76.28 86453[79:MRR:223.0,86452.0] || -> until2p7(s28)* node4(s27). % 76.04/76.28 86454[80:Spt:86453.0] || -> until2p7(s28)*. % 76.04/76.28 86455[80:MRR:224.0,86454.0] || -> until2p7(s29)* node4(s28). % 76.04/76.28 86456[81:Spt:86455.0] || -> until2p7(s29)*. % 76.04/76.28 86457[81:MRR:225.0,86456.0] || -> until2p7(s30)* node4(s29). % 76.04/76.28 86458[82:Spt:86457.0] || -> until2p7(s30)*. % 76.04/76.28 86459[82:MRR:226.0,86458.0] || -> until2p7(s31)* node4(s30). % 76.04/76.28 86460[83:Spt:86459.0] || -> until2p7(s31)*. % 76.04/76.28 86461[83:MRR:227.0,86460.0] || -> until2p7(s32)* node4(s31). % 76.04/76.28 86462[84:Spt:86461.0] || -> until2p7(s32)*. % 76.04/76.28 86463[84:MRR:228.0,86462.0] || -> until2p7(s33)* node4(s32). % 76.04/76.28 86464[85:Spt:86463.0] || -> until2p7(s33)*. % 76.04/76.28 86465[85:MRR:229.0,86464.0] || -> until2p7(s34)* node4(s33). % 76.04/76.28 86466[86:Spt:86465.0] || -> until2p7(s34)*. % 76.04/76.28 86467[86:MRR:230.0,86466.0] || -> until2p7(s35)* node4(s34). % 76.04/76.28 86468[87:Spt:86467.0] || -> until2p7(s35)*. % 76.04/76.28 86469[87:MRR:231.0,86468.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 86470[88:Spt:86469.0] || -> until2p7(s36)*. % 76.04/76.28 86471[88:MRR:232.0,86470.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 86472[89:Spt:86471.0] || -> until2p7(s37)*. % 76.04/76.28 86473[89:MRR:235.0,86472.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 86474[90:Spt:86473.0] || -> until2p7(s38)*. % 76.04/76.28 86475[90:MRR:236.0,86474.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 86476[91:Spt:86475.0] || -> until2p7(s39)*. % 76.04/76.28 86477[91:MRR:237.0,86476.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 86478[92:Spt:86477.0] || -> until2p7(s40)*. % 76.04/76.28 86479[92:MRR:238.0,86478.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 86480[93:Spt:86479.0] || -> until2p7(s41)*. % 76.04/76.28 86481[93:MRR:239.0,86480.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 86482[94:Spt:86481.0] || -> until2p7(s42)*. % 76.04/76.28 86483[94:MRR:240.0,86482.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 86484[95:Spt:86483.0] || -> until2p7(s43)*. % 76.04/76.28 86485[95:MRR:241.0,86484.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 86486[96:Spt:86485.0] || -> until2p7(s44)*. % 76.04/76.28 86487[96:MRR:539.0,86486.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 86488[97:Spt:86487.0] || -> until2p7(s45)*. % 76.04/76.28 86489[97:MRR:544.0,86488.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 86490[98:Spt:86489.0] || -> until2p7(s46)*. % 76.04/76.28 86491[98:MRR:549.0,86490.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 86492[99:Spt:86491.0] || -> until2p7(s47)*. % 76.04/76.28 86493[99:MRR:554.0,86492.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 86494[100:Spt:86493.0] || -> until2p7(s48)*. % 76.04/76.28 86495[100:MRR:559.0,86494.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 86496[101:Spt:86495.0] || -> until2p7(s49)*. % 76.04/76.28 86497[101:MRR:194.0,86496.0] || -> node4(s49)*. % 76.04/76.28 86498[101:MRR:86444.0,86497.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 86499[101:Res:53.1,86498.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 86501[101:MRR:86499.0,78381.0] || -> . % 76.04/76.28 86502[101:Spt:86501.0,86495.0,86496.0] || until2p7(s49)*+ -> . % 76.04/76.28 86503[101:Spt:86501.0,86495.1] || -> node4(s48)*. % 76.04/76.28 86504[101:MRR:78384.0,86503.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 86507[101:Res:53.1,86504.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 86510[101:Res:86507.0,61.1] always3(s48) || -> . % 76.04/76.28 86511[101:SSi:86510.0,78281.0,78387.0,78626.0,86494.0,86503.0] || -> . % 76.04/76.28 86512[100:Spt:86511.0,86493.0,86494.0] || until2p7(s48)*+ -> . % 76.04/76.28 86513[100:Spt:86511.0,86493.1] || -> node4(s47)*. % 76.04/76.28 86515[100:MRR:777.0,86513.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 86530[100:Res:53.1,86515.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 86532[101:Spt:86530.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 86534[101:Res:86532.0,61.1] always3(s47) || -> . % 76.04/76.28 86535[101:SSi:86534.0,78277.0,78280.0,78625.0,86492.0,86513.0] || -> . % 76.04/76.28 86536[101:Spt:86535.0,86530.0,86532.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 86537[101:Spt:86535.0,86530.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 86541[101:Res:86537.0,61.1] always3(s48) || -> . % 76.04/76.28 86542[101:SSi:86541.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 86543[99:Spt:86542.0,86491.0,86492.0] || until2p7(s47)*+ -> . % 76.04/76.28 86544[99:Spt:86542.0,86491.1] || -> node4(s46)*. % 76.04/76.28 86546[99:MRR:780.0,86544.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 86556[99:Res:53.1,86546.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 86558[100:Spt:86556.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 86560[100:Res:86558.0,61.1] always3(s46) || -> . % 76.04/76.28 86561[100:SSi:86560.0,78272.0,78276.0,78624.0,86490.0,86544.0] || -> . % 76.04/76.28 86562[100:Spt:86561.0,86556.0,86558.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 86563[100:Spt:86561.0,86556.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 86567[100:Res:86563.0,61.1] always3(s47) || -> . % 76.04/76.28 86568[100:SSi:86567.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 86569[98:Spt:86568.0,86489.0,86490.0] || until2p7(s46)*+ -> . % 76.04/76.28 86570[98:Spt:86568.0,86489.1] || -> node4(s45)*. % 76.04/76.28 86572[98:MRR:783.0,86570.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 86575[98:Res:53.1,86572.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 86577[99:Spt:86575.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 86579[99:Res:86577.0,61.1] always3(s45) || -> . % 76.04/76.28 86580[99:SSi:86579.0,78268.0,78271.0,78623.0,86488.0,86570.0] || -> . % 76.04/76.28 86581[99:Spt:86580.0,86575.0,86577.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 86582[99:Spt:86580.0,86575.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 86586[99:Res:86582.0,61.1] always3(s46) || -> . % 76.04/76.28 86587[99:SSi:86586.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 86588[97:Spt:86587.0,86487.0,86488.0] || until2p7(s45)*+ -> . % 76.04/76.28 86589[97:Spt:86587.0,86487.1] || -> node4(s44)*. % 76.04/76.28 86591[97:MRR:786.0,86589.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 86594[97:Res:53.1,86591.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 86596[98:Spt:86594.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 86598[98:Res:86596.0,61.1] always3(s44) || -> . % 76.04/76.28 86599[98:SSi:86598.0,78263.0,78267.0,78622.0,86486.0,86589.0] || -> . % 76.04/76.28 86600[98:Spt:86599.0,86594.0,86596.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 86601[98:Spt:86599.0,86594.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 86605[98:Res:86601.0,61.1] always3(s45) || -> . % 76.04/76.28 86606[98:SSi:86605.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 86607[96:Spt:86606.0,86485.0,86486.0] || until2p7(s44)*+ -> . % 76.04/76.28 86608[96:Spt:86606.0,86485.1] || -> node4(s43)*. % 76.04/76.28 86610[96:MRR:789.0,86608.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 86613[96:Res:53.1,86610.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 86618[97:Spt:86613.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 86620[97:Res:86618.0,61.1] always3(s43) || -> . % 76.04/76.28 86621[97:SSi:86620.0,78259.0,78262.0,78621.0,86484.0,86608.0] || -> . % 76.04/76.28 86622[97:Spt:86621.0,86613.0,86618.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 86623[97:Spt:86621.0,86613.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 86627[97:Res:86623.0,61.1] always3(s44) || -> . % 76.04/76.28 86628[97:SSi:86627.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 86629[95:Spt:86628.0,86483.0,86484.0] || until2p7(s43)*+ -> . % 76.04/76.28 86630[95:Spt:86628.0,86483.1] || -> node4(s42)*. % 76.04/76.28 86632[95:MRR:792.0,86630.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 86635[95:Res:53.1,86632.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 86637[96:Spt:86635.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 86639[96:Res:86637.0,61.1] always3(s42) || -> . % 76.04/76.28 86640[96:SSi:86639.0,78254.0,78258.0,78620.0,86482.0,86630.0] || -> . % 76.04/76.28 86641[96:Spt:86640.0,86635.0,86637.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 86642[96:Spt:86640.0,86635.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 86646[96:Res:86642.0,61.1] always3(s43) || -> . % 76.04/76.28 86647[96:SSi:86646.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 86648[94:Spt:86647.0,86481.0,86482.0] || until2p7(s42)*+ -> . % 76.04/76.28 86649[94:Spt:86647.0,86481.1] || -> node4(s41)*. % 76.04/76.28 86651[94:MRR:795.0,86649.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 86654[94:Res:53.1,86651.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 86656[95:Spt:86654.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 86658[95:Res:86656.0,61.1] always3(s41) || -> . % 76.04/76.28 86659[95:SSi:86658.0,78250.0,78253.0,78619.0,86480.0,86649.0] || -> . % 76.04/76.28 86660[95:Spt:86659.0,86654.0,86656.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 86661[95:Spt:86659.0,86654.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 86665[95:Res:86661.0,61.1] always3(s42) || -> . % 76.04/76.28 86666[95:SSi:86665.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 86667[93:Spt:86666.0,86479.0,86480.0] || until2p7(s41)*+ -> . % 76.04/76.28 86668[93:Spt:86666.0,86479.1] || -> node4(s40)*. % 76.04/76.28 86670[93:MRR:798.0,86668.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 86673[93:Res:53.1,86670.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 86675[94:Spt:86673.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 86677[94:Res:86675.0,61.1] always3(s40) || -> . % 76.04/76.28 86678[94:SSi:86677.0,78245.0,78249.0,78618.0,86478.0,86668.0] || -> . % 76.04/76.28 86679[94:Spt:86678.0,86673.0,86675.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 86680[94:Spt:86678.0,86673.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 86684[94:Res:86680.0,61.1] always3(s41) || -> . % 76.04/76.28 86685[94:SSi:86684.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 86686[92:Spt:86685.0,86477.0,86478.0] || until2p7(s40)*+ -> . % 76.04/76.28 86687[92:Spt:86685.0,86477.1] || -> node4(s39)*. % 76.04/76.28 86689[92:MRR:801.0,86687.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 86692[92:Res:53.1,86689.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 86697[93:Spt:86692.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 86699[93:Res:86697.0,61.1] always3(s39) || -> . % 76.04/76.28 86700[93:SSi:86699.0,78241.0,78244.0,78617.0,86476.0,86687.0] || -> . % 76.04/76.28 86701[93:Spt:86700.0,86692.0,86697.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 86702[93:Spt:86700.0,86692.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 86706[93:Res:86702.0,61.1] always3(s40) || -> . % 76.04/76.28 86707[93:SSi:86706.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 86708[91:Spt:86707.0,86475.0,86476.0] || until2p7(s39)*+ -> . % 76.04/76.28 86709[91:Spt:86707.0,86475.1] || -> node4(s38)*. % 76.04/76.28 86711[91:MRR:804.0,86709.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 86714[91:Res:53.1,86711.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 86716[92:Spt:86714.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 86718[92:Res:86716.0,61.1] always3(s38) || -> . % 76.04/76.28 86719[92:SSi:86718.0,78236.0,78240.0,78616.0,86474.0,86709.0] || -> . % 76.04/76.28 86720[92:Spt:86719.0,86714.0,86716.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 86721[92:Spt:86719.0,86714.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 86725[92:Res:86721.0,61.1] always3(s39) || -> . % 76.04/76.28 86726[92:SSi:86725.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 86727[90:Spt:86726.0,86473.0,86474.0] || until2p7(s38)*+ -> . % 76.04/76.28 86728[90:Spt:86726.0,86473.1] || -> node4(s37)*. % 76.04/76.28 86730[90:MRR:807.0,86728.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 86733[90:Res:53.1,86730.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 86735[91:Spt:86733.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 86737[91:Res:86735.0,61.1] always3(s37) || -> . % 76.04/76.28 86738[91:SSi:86737.0,78232.0,78235.0,78615.0,86472.0,86728.0] || -> . % 76.04/76.28 86739[91:Spt:86738.0,86733.0,86735.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 86740[91:Spt:86738.0,86733.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 86744[91:Res:86740.0,61.1] always3(s38) || -> . % 76.04/76.28 86745[91:SSi:86744.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 86746[89:Spt:86745.0,86471.0,86472.0] || until2p7(s37)*+ -> . % 76.04/76.28 86747[89:Spt:86745.0,86471.1] || -> node4(s36)*. % 76.04/76.28 86749[89:MRR:810.0,86747.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 86752[89:Res:53.1,86749.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 86754[90:Spt:86752.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 86756[90:Res:86754.0,61.1] always3(s36) || -> . % 76.04/76.28 86757[90:SSi:86756.0,78227.0,78231.0,78614.0,86470.0,86747.0] || -> . % 76.04/76.28 86758[90:Spt:86757.0,86752.0,86754.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 86759[90:Spt:86757.0,86752.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 86763[90:Res:86759.0,61.1] always3(s37) || -> . % 76.04/76.28 86764[90:SSi:86763.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 86765[88:Spt:86764.0,86469.0,86470.0] || until2p7(s36)*+ -> . % 76.04/76.28 86766[88:Spt:86764.0,86469.1] || -> node4(s35)*. % 76.04/76.28 86768[88:MRR:813.0,86766.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 86771[88:Res:53.1,86768.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 86776[89:Spt:86771.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 86778[89:Res:86776.0,61.1] always3(s35) || -> . % 76.04/76.28 86779[89:SSi:86778.0,78223.0,78226.0,78613.0,86468.0,86766.0] || -> . % 76.04/76.28 86780[89:Spt:86779.0,86771.0,86776.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.28 86781[89:Spt:86779.0,86771.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 86785[89:Res:86781.0,61.1] always3(s36) || -> . % 76.04/76.28 86786[89:SSi:86785.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 86787[87:Spt:86786.0,86467.0,86468.0] || until2p7(s35)*+ -> . % 76.04/76.28 86788[87:Spt:86786.0,86467.1] || -> node4(s34)*. % 76.04/76.28 86790[87:MRR:816.0,86788.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.28 86793[87:Res:53.1,86790.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.28 86795[88:Spt:86793.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 86797[88:Res:86795.0,61.1] always3(s34) || -> . % 76.04/76.28 86798[88:SSi:86797.0,78218.0,78222.0,78612.0,86466.0,86788.0] || -> . % 76.04/76.28 86799[88:Spt:86798.0,86793.0,86795.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.28 86800[88:Spt:86798.0,86793.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 86804[88:Res:86800.0,61.1] always3(s35) || -> . % 76.04/76.28 86805[88:SSi:86804.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 86806[86:Spt:86805.0,86465.0,86466.0] || until2p7(s34)*+ -> . % 76.04/76.28 86807[86:Spt:86805.0,86465.1] || -> node4(s33)*. % 76.04/76.28 86809[86:MRR:819.0,86807.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.28 86812[86:Res:53.1,86809.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.28 86814[87:Spt:86812.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 86816[87:Res:86814.0,61.1] always3(s33) || -> . % 76.04/76.28 86817[87:SSi:86816.0,78214.0,78217.0,78611.0,86464.0,86807.0] || -> . % 76.04/76.28 86818[87:Spt:86817.0,86812.0,86814.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.28 86819[87:Spt:86817.0,86812.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 86823[87:Res:86819.0,61.1] always3(s34) || -> . % 76.04/76.28 86824[87:SSi:86823.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.28 86825[85:Spt:86824.0,86463.0,86464.0] || until2p7(s33)*+ -> . % 76.04/76.28 86826[85:Spt:86824.0,86463.1] || -> node4(s32)*. % 76.04/76.28 86828[85:MRR:822.0,86826.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.28 86831[85:Res:53.1,86828.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.28 86833[86:Spt:86831.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 86835[86:Res:86833.0,61.1] always3(s32) || -> . % 76.04/76.28 86836[86:SSi:86835.0,78209.0,78213.0,78610.0,86462.0,86826.0] || -> . % 76.04/76.28 86837[86:Spt:86836.0,86831.0,86833.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.28 86838[86:Spt:86836.0,86831.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 86842[86:Res:86838.0,61.1] always3(s33) || -> . % 76.04/76.28 86843[86:SSi:86842.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.28 86844[84:Spt:86843.0,86461.0,86462.0] || until2p7(s32)*+ -> . % 76.04/76.28 86845[84:Spt:86843.0,86461.1] || -> node4(s31)*. % 76.04/76.28 86847[84:MRR:825.0,86845.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.28 86850[84:Res:53.1,86847.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.28 86855[85:Spt:86850.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 86857[85:Res:86855.0,61.1] always3(s31) || -> . % 76.04/76.28 86858[85:SSi:86857.0,78205.0,78208.0,78609.0,86460.0,86845.0] || -> . % 76.04/76.28 86859[85:Spt:86858.0,86850.0,86855.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.28 86860[85:Spt:86858.0,86850.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 86864[85:Res:86860.0,61.1] always3(s32) || -> . % 76.04/76.28 86865[85:SSi:86864.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.28 86866[83:Spt:86865.0,86459.0,86460.0] || until2p7(s31)*+ -> . % 76.04/76.28 86867[83:Spt:86865.0,86459.1] || -> node4(s30)*. % 76.04/76.28 86869[83:MRR:828.0,86867.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.28 86872[83:Res:53.1,86869.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.28 86874[84:Spt:86872.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 86876[84:Res:86874.0,61.1] always3(s30) || -> . % 76.04/76.28 86877[84:SSi:86876.0,78200.0,78204.0,78608.0,86458.0,86867.0] || -> . % 76.04/76.28 86878[84:Spt:86877.0,86872.0,86874.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.28 86879[84:Spt:86877.0,86872.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 86883[84:Res:86879.0,61.1] always3(s31) || -> . % 76.04/76.28 86884[84:SSi:86883.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.28 86885[82:Spt:86884.0,86457.0,86458.0] || until2p7(s30)*+ -> . % 76.04/76.28 86886[82:Spt:86884.0,86457.1] || -> node4(s29)*. % 76.04/76.28 86888[82:MRR:831.0,86886.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.28 86891[82:Res:53.1,86888.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.28 86893[83:Spt:86891.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 86895[83:Res:86893.0,61.1] always3(s29) || -> . % 76.04/76.28 86896[83:SSi:86895.0,78196.0,78199.0,78607.0,86456.0,86886.0] || -> . % 76.04/76.28 86897[83:Spt:86896.0,86891.0,86893.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.28 86898[83:Spt:86896.0,86891.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 86902[83:Res:86898.0,61.1] always3(s30) || -> . % 76.04/76.28 86903[83:SSi:86902.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.28 86904[81:Spt:86903.0,86455.0,86456.0] || until2p7(s29)*+ -> . % 76.04/76.28 86905[81:Spt:86903.0,86455.1] || -> node4(s28)*. % 76.04/76.28 86907[81:MRR:834.0,86905.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.28 86910[81:Res:53.1,86907.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.28 86912[82:Spt:86910.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 86914[82:Res:86912.0,61.1] always3(s28) || -> . % 76.04/76.28 86915[82:SSi:86914.0,78191.0,78195.0,78606.0,86454.0,86905.0] || -> . % 76.04/76.28 86916[82:Spt:86915.0,86910.0,86912.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.28 86917[82:Spt:86915.0,86910.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 86921[82:Res:86917.0,61.1] always3(s29) || -> . % 76.04/76.28 86922[82:SSi:86921.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.28 86923[80:Spt:86922.0,86453.0,86454.0] || until2p7(s28)*+ -> . % 76.04/76.28 86924[80:Spt:86922.0,86453.1] || -> node4(s27)*. % 76.04/76.28 86926[80:MRR:837.0,86924.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.28 86929[80:Res:53.1,86926.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.28 86934[81:Spt:86929.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.28 86936[81:Res:86934.0,61.1] always3(s27) || -> . % 76.04/76.28 86937[81:SSi:86936.0,78187.0,78190.0,78605.0,86452.0,86924.0] || -> . % 76.04/76.28 86938[81:Spt:86937.0,86929.0,86934.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.28 86939[81:Spt:86937.0,86929.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 86943[81:Res:86939.0,61.1] always3(s28) || -> . % 76.04/76.28 86944[81:SSi:86943.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.28 86945[79:Spt:86944.0,86451.0,86452.0] || until2p7(s27)*+ -> . % 76.04/76.28 86946[79:Spt:86944.0,86451.1] || -> node4(s26)*. % 76.04/76.28 86948[79:MRR:840.0,86946.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.28 86951[79:Res:53.1,86948.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.28 86953[80:Spt:86951.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.28 86955[80:Res:86953.0,61.1] always3(s26) || -> . % 76.04/76.28 86956[80:SSi:86955.0,78182.0,78186.0,78604.0,86450.0,86946.0] || -> . % 76.04/76.28 86957[80:Spt:86956.0,86951.0,86953.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.28 86958[80:Spt:86956.0,86951.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.28 86962[80:Res:86958.0,61.1] always3(s27) || -> . % 76.04/76.28 86963[80:SSi:86962.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.28 86964[78:Spt:86963.0,86449.0,86450.0] || until2p7(s26)*+ -> . % 76.04/76.28 86965[78:Spt:86963.0,86449.1] || -> node4(s25)*. % 76.04/76.28 86967[78:MRR:843.0,86965.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.28 86970[78:Res:53.1,86967.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.28 86972[78:MRR:86970.0,86439.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.28 86974[78:Res:86972.0,61.1] always3(s26) || -> . % 76.04/76.28 86975[78:SSi:86974.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.28 86976[76:Spt:86975.0,86342.0,86345.0] || trans(s49,s25)*+ -> . % 76.04/76.28 86977[76:Spt:86975.0,86342.1,86342.2,86342.3,86342.4,86342.5,86342.6,86342.7,86342.8,86342.9,86342.10,86342.11,86342.12,86342.13,86342.14,86342.15,86342.16,86342.17,86342.18,86342.19,86342.20,86342.21,86342.22,86342.23] || -> trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 86979[76:MRR:86344.1,86976.0] xuntil6(s49) || -> trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 86980[77:Spt:86977.0] || -> trans(s49,s24)*. % 76.04/76.28 86981[77:Res:86980.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s24)*. % 76.04/76.28 86983[77:Res:86980.0,60.0] || -> node2(s49,s24)*. % 76.04/76.28 86984[77:SSi:86981.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s24)*. % 76.04/76.28 86985[77:Res:86983.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)*. % 76.04/76.28 87070[77:SoR:86985.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)*. % 76.04/76.28 87072[77:SoR:87070.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)* xuntil6(s49). % 76.04/76.28 87073[77:SSi:87072.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s24,c_busy)* xuntil6(s49). % 76.04/76.28 87074[78:Spt:87073.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.28 87076[78:Res:87074.0,61.1] always3(s24) || -> . % 76.04/76.28 87077[78:SSi:87076.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.28 87078[78:Spt:87077.0,87073.1,87074.0] || m_main_v_state(s24,c_busy)*+ -> . % 76.04/76.28 87079[78:Spt:87077.0,87073.0,87073.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 87083[78:MRR:87070.2,87078.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 87084[78:Res:53.1,87079.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 87086[78:MRR:87084.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 87087[78:MRR:86984.0,87086.0] || -> until2p7(s24)*. % 76.04/76.28 87088[78:MRR:220.0,87087.0] || -> until2p7(s25)* node4(s24). % 76.04/76.28 87089[79:Spt:87088.0] || -> until2p7(s25)*. % 76.04/76.28 87090[79:MRR:221.0,87089.0] || -> until2p7(s26)* node4(s25). % 76.04/76.28 87091[80:Spt:87090.0] || -> until2p7(s26)*. % 76.04/76.28 87092[80:MRR:222.0,87091.0] || -> until2p7(s27)* node4(s26). % 76.04/76.28 87093[81:Spt:87092.0] || -> until2p7(s27)*. % 76.04/76.28 87094[81:MRR:223.0,87093.0] || -> until2p7(s28)* node4(s27). % 76.04/76.28 87095[82:Spt:87094.0] || -> until2p7(s28)*. % 76.04/76.28 87096[82:MRR:224.0,87095.0] || -> until2p7(s29)* node4(s28). % 76.04/76.28 87097[83:Spt:87096.0] || -> until2p7(s29)*. % 76.04/76.28 87098[83:MRR:225.0,87097.0] || -> until2p7(s30)* node4(s29). % 76.04/76.28 87099[84:Spt:87098.0] || -> until2p7(s30)*. % 76.04/76.28 87100[84:MRR:226.0,87099.0] || -> until2p7(s31)* node4(s30). % 76.04/76.28 87101[85:Spt:87100.0] || -> until2p7(s31)*. % 76.04/76.28 87102[85:MRR:227.0,87101.0] || -> until2p7(s32)* node4(s31). % 76.04/76.28 87103[86:Spt:87102.0] || -> until2p7(s32)*. % 76.04/76.28 87104[86:MRR:228.0,87103.0] || -> until2p7(s33)* node4(s32). % 76.04/76.28 87105[87:Spt:87104.0] || -> until2p7(s33)*. % 76.04/76.28 87106[87:MRR:229.0,87105.0] || -> until2p7(s34)* node4(s33). % 76.04/76.28 87107[88:Spt:87106.0] || -> until2p7(s34)*. % 76.04/76.28 87108[88:MRR:230.0,87107.0] || -> until2p7(s35)* node4(s34). % 76.04/76.28 87109[89:Spt:87108.0] || -> until2p7(s35)*. % 76.04/76.28 87110[89:MRR:231.0,87109.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 87111[90:Spt:87110.0] || -> until2p7(s36)*. % 76.04/76.28 87112[90:MRR:232.0,87111.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 87113[91:Spt:87112.0] || -> until2p7(s37)*. % 76.04/76.28 87114[91:MRR:235.0,87113.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 87115[92:Spt:87114.0] || -> until2p7(s38)*. % 76.04/76.28 87116[92:MRR:236.0,87115.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 87117[93:Spt:87116.0] || -> until2p7(s39)*. % 76.04/76.28 87118[93:MRR:237.0,87117.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 87119[94:Spt:87118.0] || -> until2p7(s40)*. % 76.04/76.28 87120[94:MRR:238.0,87119.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 87121[95:Spt:87120.0] || -> until2p7(s41)*. % 76.04/76.28 87122[95:MRR:239.0,87121.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 87123[96:Spt:87122.0] || -> until2p7(s42)*. % 76.04/76.28 87124[96:MRR:240.0,87123.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 87125[97:Spt:87124.0] || -> until2p7(s43)*. % 76.04/76.28 87126[97:MRR:241.0,87125.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 87127[98:Spt:87126.0] || -> until2p7(s44)*. % 76.04/76.28 87128[98:MRR:539.0,87127.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 87129[99:Spt:87128.0] || -> until2p7(s45)*. % 76.04/76.28 87130[99:MRR:544.0,87129.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 87131[100:Spt:87130.0] || -> until2p7(s46)*. % 76.04/76.28 87132[100:MRR:549.0,87131.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 87133[101:Spt:87132.0] || -> until2p7(s47)*. % 76.04/76.28 87134[101:MRR:554.0,87133.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 87135[102:Spt:87134.0] || -> until2p7(s48)*. % 76.04/76.28 87136[102:MRR:559.0,87135.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 87137[103:Spt:87136.0] || -> until2p7(s49)*. % 76.04/76.28 87138[103:MRR:194.0,87137.0] || -> node4(s49)*. % 76.04/76.28 87139[103:MRR:87083.0,87138.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 87140[103:Res:53.1,87139.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 87142[103:MRR:87140.0,78381.0] || -> . % 76.04/76.28 87143[103:Spt:87142.0,87136.0,87137.0] || until2p7(s49)*+ -> . % 76.04/76.28 87144[103:Spt:87142.0,87136.1] || -> node4(s48)*. % 76.04/76.28 87145[103:MRR:78384.0,87144.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 87148[103:Res:53.1,87145.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 87151[103:Res:87148.0,61.1] always3(s48) || -> . % 76.04/76.28 87152[103:SSi:87151.0,78281.0,78387.0,78626.0,87135.0,87144.0] || -> . % 76.04/76.28 87153[102:Spt:87152.0,87134.0,87135.0] || until2p7(s48)*+ -> . % 76.04/76.28 87154[102:Spt:87152.0,87134.1] || -> node4(s47)*. % 76.04/76.28 87156[102:MRR:777.0,87154.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 87171[102:Res:53.1,87156.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 87173[103:Spt:87171.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 87175[103:Res:87173.0,61.1] always3(s47) || -> . % 76.04/76.28 87176[103:SSi:87175.0,78277.0,78280.0,78625.0,87133.0,87154.0] || -> . % 76.04/76.28 87177[103:Spt:87176.0,87171.0,87173.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 87178[103:Spt:87176.0,87171.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 87182[103:Res:87178.0,61.1] always3(s48) || -> . % 76.04/76.28 87183[103:SSi:87182.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 87184[101:Spt:87183.0,87132.0,87133.0] || until2p7(s47)*+ -> . % 76.04/76.28 87185[101:Spt:87183.0,87132.1] || -> node4(s46)*. % 76.04/76.28 87187[101:MRR:780.0,87185.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 87197[101:Res:53.1,87187.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 87199[102:Spt:87197.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 87201[102:Res:87199.0,61.1] always3(s46) || -> . % 76.04/76.28 87202[102:SSi:87201.0,78272.0,78276.0,78624.0,87131.0,87185.0] || -> . % 76.04/76.28 87203[102:Spt:87202.0,87197.0,87199.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 87204[102:Spt:87202.0,87197.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 87208[102:Res:87204.0,61.1] always3(s47) || -> . % 76.04/76.28 87209[102:SSi:87208.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 87210[100:Spt:87209.0,87130.0,87131.0] || until2p7(s46)*+ -> . % 76.04/76.28 87211[100:Spt:87209.0,87130.1] || -> node4(s45)*. % 76.04/76.28 87213[100:MRR:783.0,87211.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 87216[100:Res:53.1,87213.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 87218[101:Spt:87216.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 87220[101:Res:87218.0,61.1] always3(s45) || -> . % 76.04/76.28 87221[101:SSi:87220.0,78268.0,78271.0,78623.0,87129.0,87211.0] || -> . % 76.04/76.28 87222[101:Spt:87221.0,87216.0,87218.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 87223[101:Spt:87221.0,87216.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 87227[101:Res:87223.0,61.1] always3(s46) || -> . % 76.04/76.28 87228[101:SSi:87227.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 87229[99:Spt:87228.0,87128.0,87129.0] || until2p7(s45)*+ -> . % 76.04/76.28 87230[99:Spt:87228.0,87128.1] || -> node4(s44)*. % 76.04/76.28 87232[99:MRR:786.0,87230.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 87235[99:Res:53.1,87232.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 87237[100:Spt:87235.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 87239[100:Res:87237.0,61.1] always3(s44) || -> . % 76.04/76.28 87240[100:SSi:87239.0,78263.0,78267.0,78622.0,87127.0,87230.0] || -> . % 76.04/76.28 87241[100:Spt:87240.0,87235.0,87237.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 87242[100:Spt:87240.0,87235.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 87246[100:Res:87242.0,61.1] always3(s45) || -> . % 76.04/76.28 87247[100:SSi:87246.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 87248[98:Spt:87247.0,87126.0,87127.0] || until2p7(s44)*+ -> . % 76.04/76.28 87249[98:Spt:87247.0,87126.1] || -> node4(s43)*. % 76.04/76.28 87251[98:MRR:789.0,87249.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 87254[98:Res:53.1,87251.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 87259[99:Spt:87254.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 87261[99:Res:87259.0,61.1] always3(s43) || -> . % 76.04/76.28 87262[99:SSi:87261.0,78259.0,78262.0,78621.0,87125.0,87249.0] || -> . % 76.04/76.28 87263[99:Spt:87262.0,87254.0,87259.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 87264[99:Spt:87262.0,87254.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 87268[99:Res:87264.0,61.1] always3(s44) || -> . % 76.04/76.28 87269[99:SSi:87268.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 87270[97:Spt:87269.0,87124.0,87125.0] || until2p7(s43)*+ -> . % 76.04/76.28 87271[97:Spt:87269.0,87124.1] || -> node4(s42)*. % 76.04/76.28 87273[97:MRR:792.0,87271.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 87276[97:Res:53.1,87273.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 87278[98:Spt:87276.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 87280[98:Res:87278.0,61.1] always3(s42) || -> . % 76.04/76.28 87281[98:SSi:87280.0,78254.0,78258.0,78620.0,87123.0,87271.0] || -> . % 76.04/76.28 87282[98:Spt:87281.0,87276.0,87278.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 87283[98:Spt:87281.0,87276.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 87287[98:Res:87283.0,61.1] always3(s43) || -> . % 76.04/76.28 87288[98:SSi:87287.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 87289[96:Spt:87288.0,87122.0,87123.0] || until2p7(s42)*+ -> . % 76.04/76.28 87290[96:Spt:87288.0,87122.1] || -> node4(s41)*. % 76.04/76.28 87292[96:MRR:795.0,87290.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 87295[96:Res:53.1,87292.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 87297[97:Spt:87295.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 87299[97:Res:87297.0,61.1] always3(s41) || -> . % 76.04/76.28 87300[97:SSi:87299.0,78250.0,78253.0,78619.0,87121.0,87290.0] || -> . % 76.04/76.28 87301[97:Spt:87300.0,87295.0,87297.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 87302[97:Spt:87300.0,87295.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 87306[97:Res:87302.0,61.1] always3(s42) || -> . % 76.04/76.28 87307[97:SSi:87306.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 87308[95:Spt:87307.0,87120.0,87121.0] || until2p7(s41)*+ -> . % 76.04/76.28 87309[95:Spt:87307.0,87120.1] || -> node4(s40)*. % 76.04/76.28 87311[95:MRR:798.0,87309.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 87314[95:Res:53.1,87311.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 87316[96:Spt:87314.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 87318[96:Res:87316.0,61.1] always3(s40) || -> . % 76.04/76.28 87319[96:SSi:87318.0,78245.0,78249.0,78618.0,87119.0,87309.0] || -> . % 76.04/76.28 87320[96:Spt:87319.0,87314.0,87316.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 87321[96:Spt:87319.0,87314.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 87325[96:Res:87321.0,61.1] always3(s41) || -> . % 76.04/76.28 87326[96:SSi:87325.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 87327[94:Spt:87326.0,87118.0,87119.0] || until2p7(s40)*+ -> . % 76.04/76.28 87328[94:Spt:87326.0,87118.1] || -> node4(s39)*. % 76.04/76.28 87330[94:MRR:801.0,87328.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 87333[94:Res:53.1,87330.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 87338[95:Spt:87333.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 87340[95:Res:87338.0,61.1] always3(s39) || -> . % 76.04/76.28 87341[95:SSi:87340.0,78241.0,78244.0,78617.0,87117.0,87328.0] || -> . % 76.04/76.28 87342[95:Spt:87341.0,87333.0,87338.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 87343[95:Spt:87341.0,87333.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 87347[95:Res:87343.0,61.1] always3(s40) || -> . % 76.04/76.28 87348[95:SSi:87347.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 87349[93:Spt:87348.0,87116.0,87117.0] || until2p7(s39)*+ -> . % 76.04/76.28 87350[93:Spt:87348.0,87116.1] || -> node4(s38)*. % 76.04/76.28 87352[93:MRR:804.0,87350.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 87355[93:Res:53.1,87352.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 87357[94:Spt:87355.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 87359[94:Res:87357.0,61.1] always3(s38) || -> . % 76.04/76.28 87360[94:SSi:87359.0,78236.0,78240.0,78616.0,87115.0,87350.0] || -> . % 76.04/76.28 87361[94:Spt:87360.0,87355.0,87357.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 87362[94:Spt:87360.0,87355.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 87366[94:Res:87362.0,61.1] always3(s39) || -> . % 76.04/76.28 87367[94:SSi:87366.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 87368[92:Spt:87367.0,87114.0,87115.0] || until2p7(s38)*+ -> . % 76.04/76.28 87369[92:Spt:87367.0,87114.1] || -> node4(s37)*. % 76.04/76.28 87371[92:MRR:807.0,87369.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 87374[92:Res:53.1,87371.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 87376[93:Spt:87374.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 87378[93:Res:87376.0,61.1] always3(s37) || -> . % 76.04/76.28 87379[93:SSi:87378.0,78232.0,78235.0,78615.0,87113.0,87369.0] || -> . % 76.04/76.28 87380[93:Spt:87379.0,87374.0,87376.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 87381[93:Spt:87379.0,87374.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 87385[93:Res:87381.0,61.1] always3(s38) || -> . % 76.04/76.28 87386[93:SSi:87385.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 87387[91:Spt:87386.0,87112.0,87113.0] || until2p7(s37)*+ -> . % 76.04/76.28 87388[91:Spt:87386.0,87112.1] || -> node4(s36)*. % 76.04/76.28 87390[91:MRR:810.0,87388.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 87393[91:Res:53.1,87390.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 87395[92:Spt:87393.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 87397[92:Res:87395.0,61.1] always3(s36) || -> . % 76.04/76.28 87398[92:SSi:87397.0,78227.0,78231.0,78614.0,87111.0,87388.0] || -> . % 76.04/76.28 87399[92:Spt:87398.0,87393.0,87395.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 87400[92:Spt:87398.0,87393.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 87404[92:Res:87400.0,61.1] always3(s37) || -> . % 76.04/76.28 87405[92:SSi:87404.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 87406[90:Spt:87405.0,87110.0,87111.0] || until2p7(s36)*+ -> . % 76.04/76.28 87407[90:Spt:87405.0,87110.1] || -> node4(s35)*. % 76.04/76.28 87409[90:MRR:813.0,87407.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 87412[90:Res:53.1,87409.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 87417[91:Spt:87412.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 87419[91:Res:87417.0,61.1] always3(s35) || -> . % 76.04/76.28 87420[91:SSi:87419.0,78223.0,78226.0,78613.0,87109.0,87407.0] || -> . % 76.04/76.28 87421[91:Spt:87420.0,87412.0,87417.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.28 87422[91:Spt:87420.0,87412.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 87426[91:Res:87422.0,61.1] always3(s36) || -> . % 76.04/76.28 87427[91:SSi:87426.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 87428[89:Spt:87427.0,87108.0,87109.0] || until2p7(s35)*+ -> . % 76.04/76.28 87429[89:Spt:87427.0,87108.1] || -> node4(s34)*. % 76.04/76.28 87431[89:MRR:816.0,87429.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.28 87434[89:Res:53.1,87431.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.28 87436[90:Spt:87434.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 87438[90:Res:87436.0,61.1] always3(s34) || -> . % 76.04/76.28 87439[90:SSi:87438.0,78218.0,78222.0,78612.0,87107.0,87429.0] || -> . % 76.04/76.28 87440[90:Spt:87439.0,87434.0,87436.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.28 87441[90:Spt:87439.0,87434.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 87445[90:Res:87441.0,61.1] always3(s35) || -> . % 76.04/76.28 87446[90:SSi:87445.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 87447[88:Spt:87446.0,87106.0,87107.0] || until2p7(s34)*+ -> . % 76.04/76.28 87448[88:Spt:87446.0,87106.1] || -> node4(s33)*. % 76.04/76.28 87450[88:MRR:819.0,87448.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.28 87453[88:Res:53.1,87450.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.28 87455[89:Spt:87453.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 87457[89:Res:87455.0,61.1] always3(s33) || -> . % 76.04/76.28 87458[89:SSi:87457.0,78214.0,78217.0,78611.0,87105.0,87448.0] || -> . % 76.04/76.28 87459[89:Spt:87458.0,87453.0,87455.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.28 87460[89:Spt:87458.0,87453.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 87464[89:Res:87460.0,61.1] always3(s34) || -> . % 76.04/76.28 87465[89:SSi:87464.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.28 87466[87:Spt:87465.0,87104.0,87105.0] || until2p7(s33)*+ -> . % 76.04/76.28 87467[87:Spt:87465.0,87104.1] || -> node4(s32)*. % 76.04/76.28 87469[87:MRR:822.0,87467.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.28 87472[87:Res:53.1,87469.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.28 87474[88:Spt:87472.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 87476[88:Res:87474.0,61.1] always3(s32) || -> . % 76.04/76.28 87477[88:SSi:87476.0,78209.0,78213.0,78610.0,87103.0,87467.0] || -> . % 76.04/76.28 87478[88:Spt:87477.0,87472.0,87474.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.28 87479[88:Spt:87477.0,87472.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 87483[88:Res:87479.0,61.1] always3(s33) || -> . % 76.04/76.28 87484[88:SSi:87483.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.28 87485[86:Spt:87484.0,87102.0,87103.0] || until2p7(s32)*+ -> . % 76.04/76.28 87486[86:Spt:87484.0,87102.1] || -> node4(s31)*. % 76.04/76.28 87488[86:MRR:825.0,87486.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.28 87491[86:Res:53.1,87488.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.28 87496[87:Spt:87491.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 87498[87:Res:87496.0,61.1] always3(s31) || -> . % 76.04/76.28 87499[87:SSi:87498.0,78205.0,78208.0,78609.0,87101.0,87486.0] || -> . % 76.04/76.28 87500[87:Spt:87499.0,87491.0,87496.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.28 87501[87:Spt:87499.0,87491.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 87505[87:Res:87501.0,61.1] always3(s32) || -> . % 76.04/76.28 87506[87:SSi:87505.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.28 87507[85:Spt:87506.0,87100.0,87101.0] || until2p7(s31)*+ -> . % 76.04/76.28 87508[85:Spt:87506.0,87100.1] || -> node4(s30)*. % 76.04/76.28 87510[85:MRR:828.0,87508.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.28 87513[85:Res:53.1,87510.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.28 87515[86:Spt:87513.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 87517[86:Res:87515.0,61.1] always3(s30) || -> . % 76.04/76.28 87518[86:SSi:87517.0,78200.0,78204.0,78608.0,87099.0,87508.0] || -> . % 76.04/76.28 87519[86:Spt:87518.0,87513.0,87515.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.28 87520[86:Spt:87518.0,87513.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 87524[86:Res:87520.0,61.1] always3(s31) || -> . % 76.04/76.28 87525[86:SSi:87524.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.28 87526[84:Spt:87525.0,87098.0,87099.0] || until2p7(s30)*+ -> . % 76.04/76.28 87527[84:Spt:87525.0,87098.1] || -> node4(s29)*. % 76.04/76.28 87529[84:MRR:831.0,87527.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.28 87532[84:Res:53.1,87529.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.28 87534[85:Spt:87532.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 87536[85:Res:87534.0,61.1] always3(s29) || -> . % 76.04/76.28 87537[85:SSi:87536.0,78196.0,78199.0,78607.0,87097.0,87527.0] || -> . % 76.04/76.28 87538[85:Spt:87537.0,87532.0,87534.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.28 87539[85:Spt:87537.0,87532.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 87543[85:Res:87539.0,61.1] always3(s30) || -> . % 76.04/76.28 87544[85:SSi:87543.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.28 87545[83:Spt:87544.0,87096.0,87097.0] || until2p7(s29)*+ -> . % 76.04/76.28 87546[83:Spt:87544.0,87096.1] || -> node4(s28)*. % 76.04/76.28 87548[83:MRR:834.0,87546.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.28 87551[83:Res:53.1,87548.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.28 87553[84:Spt:87551.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 87555[84:Res:87553.0,61.1] always3(s28) || -> . % 76.04/76.28 87556[84:SSi:87555.0,78191.0,78195.0,78606.0,87095.0,87546.0] || -> . % 76.04/76.28 87557[84:Spt:87556.0,87551.0,87553.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.28 87558[84:Spt:87556.0,87551.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 87562[84:Res:87558.0,61.1] always3(s29) || -> . % 76.04/76.28 87563[84:SSi:87562.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.28 87564[82:Spt:87563.0,87094.0,87095.0] || until2p7(s28)*+ -> . % 76.04/76.28 87565[82:Spt:87563.0,87094.1] || -> node4(s27)*. % 76.04/76.28 87567[82:MRR:837.0,87565.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.28 87570[82:Res:53.1,87567.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.28 87575[83:Spt:87570.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.28 87577[83:Res:87575.0,61.1] always3(s27) || -> . % 76.04/76.28 87578[83:SSi:87577.0,78187.0,78190.0,78605.0,87093.0,87565.0] || -> . % 76.04/76.28 87579[83:Spt:87578.0,87570.0,87575.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.28 87580[83:Spt:87578.0,87570.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 87584[83:Res:87580.0,61.1] always3(s28) || -> . % 76.04/76.28 87585[83:SSi:87584.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.28 87586[81:Spt:87585.0,87092.0,87093.0] || until2p7(s27)*+ -> . % 76.04/76.28 87587[81:Spt:87585.0,87092.1] || -> node4(s26)*. % 76.04/76.28 87589[81:MRR:840.0,87587.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.28 87592[81:Res:53.1,87589.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.28 87594[82:Spt:87592.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.28 87596[82:Res:87594.0,61.1] always3(s26) || -> . % 76.04/76.28 87597[82:SSi:87596.0,78182.0,78186.0,78604.0,87091.0,87587.0] || -> . % 76.04/76.28 87598[82:Spt:87597.0,87592.0,87594.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.28 87599[82:Spt:87597.0,87592.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.28 87603[82:Res:87599.0,61.1] always3(s27) || -> . % 76.04/76.28 87604[82:SSi:87603.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.28 87605[80:Spt:87604.0,87090.0,87091.0] || until2p7(s26)*+ -> . % 76.04/76.28 87606[80:Spt:87604.0,87090.1] || -> node4(s25)*. % 76.04/76.28 87608[80:MRR:843.0,87606.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.28 87611[80:Res:53.1,87608.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.28 87613[81:Spt:87611.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.28 87615[81:Res:87613.0,61.1] always3(s25) || -> . % 76.04/76.28 87616[81:SSi:87615.0,78178.0,78181.0,78603.0,87089.0,87606.0] || -> . % 76.04/76.28 87617[81:Spt:87616.0,87611.0,87613.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.28 87618[81:Spt:87616.0,87611.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.28 87622[81:Res:87618.0,61.1] always3(s26) || -> . % 76.04/76.28 87623[81:SSi:87622.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.28 87624[79:Spt:87623.0,87088.0,87089.0] || until2p7(s25)*+ -> . % 76.04/76.28 87625[79:Spt:87623.0,87088.1] || -> node4(s24)*. % 76.04/76.28 87627[79:MRR:846.0,87625.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.28 87630[79:Res:53.1,87627.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.28 87632[79:MRR:87630.0,87078.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.28 87634[79:Res:87632.0,61.1] always3(s25) || -> . % 76.04/76.28 87635[79:SSi:87634.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.28 87636[77:Spt:87635.0,86977.0,86980.0] || trans(s49,s24)*+ -> . % 76.04/76.28 87637[77:Spt:87635.0,86977.1,86977.2,86977.3,86977.4,86977.5,86977.6,86977.7,86977.8,86977.9,86977.10,86977.11,86977.12,86977.13,86977.14,86977.15,86977.16,86977.17,86977.18,86977.19,86977.20,86977.21,86977.22] || -> trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 87639[77:MRR:86979.1,87636.0] xuntil6(s49) || -> trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 87640[78:Spt:87637.0] || -> trans(s49,s23)*. % 76.04/76.28 87641[78:Res:87640.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s23)*. % 76.04/76.28 87643[78:Res:87640.0,60.0] || -> node2(s49,s23)*. % 76.04/76.28 87644[78:SSi:87641.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s23)*. % 76.04/76.28 87645[78:Res:87643.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)*. % 76.04/76.28 87734[78:SoR:87645.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)*. % 76.04/76.28 87736[78:SoR:87734.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)* xuntil6(s49). % 76.04/76.28 87737[78:SSi:87736.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s23,c_busy)* xuntil6(s49). % 76.04/76.28 87738[79:Spt:87737.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.28 87740[79:Res:87738.0,61.1] always3(s23) || -> . % 76.04/76.28 87741[79:SSi:87740.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.28 87742[79:Spt:87741.0,87737.1,87738.0] || m_main_v_state(s23,c_busy)*+ -> . % 76.04/76.28 87743[79:Spt:87741.0,87737.0,87737.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 87747[79:MRR:87734.2,87742.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 87748[79:Res:53.1,87743.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 87750[79:MRR:87748.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 87751[79:MRR:87644.0,87750.0] || -> until2p7(s23)*. % 76.04/76.28 87752[79:MRR:219.0,87751.0] || -> until2p7(s24)* node4(s23). % 76.04/76.28 87753[80:Spt:87752.0] || -> until2p7(s24)*. % 76.04/76.28 87754[80:MRR:220.0,87753.0] || -> until2p7(s25)* node4(s24). % 76.04/76.28 87755[81:Spt:87754.0] || -> until2p7(s25)*. % 76.04/76.28 87756[81:MRR:221.0,87755.0] || -> until2p7(s26)* node4(s25). % 76.04/76.28 87757[82:Spt:87756.0] || -> until2p7(s26)*. % 76.04/76.28 87758[82:MRR:222.0,87757.0] || -> until2p7(s27)* node4(s26). % 76.04/76.28 87759[83:Spt:87758.0] || -> until2p7(s27)*. % 76.04/76.28 87760[83:MRR:223.0,87759.0] || -> until2p7(s28)* node4(s27). % 76.04/76.28 87761[84:Spt:87760.0] || -> until2p7(s28)*. % 76.04/76.28 87762[84:MRR:224.0,87761.0] || -> until2p7(s29)* node4(s28). % 76.04/76.28 87763[85:Spt:87762.0] || -> until2p7(s29)*. % 76.04/76.28 87764[85:MRR:225.0,87763.0] || -> until2p7(s30)* node4(s29). % 76.04/76.28 87765[86:Spt:87764.0] || -> until2p7(s30)*. % 76.04/76.28 87766[86:MRR:226.0,87765.0] || -> until2p7(s31)* node4(s30). % 76.04/76.28 87767[87:Spt:87766.0] || -> until2p7(s31)*. % 76.04/76.28 87768[87:MRR:227.0,87767.0] || -> until2p7(s32)* node4(s31). % 76.04/76.28 87769[88:Spt:87768.0] || -> until2p7(s32)*. % 76.04/76.28 87770[88:MRR:228.0,87769.0] || -> until2p7(s33)* node4(s32). % 76.04/76.28 87771[89:Spt:87770.0] || -> until2p7(s33)*. % 76.04/76.28 87772[89:MRR:229.0,87771.0] || -> until2p7(s34)* node4(s33). % 76.04/76.28 87773[90:Spt:87772.0] || -> until2p7(s34)*. % 76.04/76.28 87774[90:MRR:230.0,87773.0] || -> until2p7(s35)* node4(s34). % 76.04/76.28 87775[91:Spt:87774.0] || -> until2p7(s35)*. % 76.04/76.28 87776[91:MRR:231.0,87775.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 87777[92:Spt:87776.0] || -> until2p7(s36)*. % 76.04/76.28 87778[92:MRR:232.0,87777.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 87779[93:Spt:87778.0] || -> until2p7(s37)*. % 76.04/76.28 87780[93:MRR:235.0,87779.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 87781[94:Spt:87780.0] || -> until2p7(s38)*. % 76.04/76.28 87782[94:MRR:236.0,87781.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 87783[95:Spt:87782.0] || -> until2p7(s39)*. % 76.04/76.28 87784[95:MRR:237.0,87783.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 87785[96:Spt:87784.0] || -> until2p7(s40)*. % 76.04/76.28 87786[96:MRR:238.0,87785.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 87787[97:Spt:87786.0] || -> until2p7(s41)*. % 76.04/76.28 87788[97:MRR:239.0,87787.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 87789[98:Spt:87788.0] || -> until2p7(s42)*. % 76.04/76.28 87790[98:MRR:240.0,87789.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 87791[99:Spt:87790.0] || -> until2p7(s43)*. % 76.04/76.28 87792[99:MRR:241.0,87791.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 87793[100:Spt:87792.0] || -> until2p7(s44)*. % 76.04/76.28 87794[100:MRR:539.0,87793.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 87795[101:Spt:87794.0] || -> until2p7(s45)*. % 76.04/76.28 87796[101:MRR:544.0,87795.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 87797[102:Spt:87796.0] || -> until2p7(s46)*. % 76.04/76.28 87798[102:MRR:549.0,87797.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 87799[103:Spt:87798.0] || -> until2p7(s47)*. % 76.04/76.28 87800[103:MRR:554.0,87799.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 87801[104:Spt:87800.0] || -> until2p7(s48)*. % 76.04/76.28 87802[104:MRR:559.0,87801.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 87803[105:Spt:87802.0] || -> until2p7(s49)*. % 76.04/76.28 87804[105:MRR:194.0,87803.0] || -> node4(s49)*. % 76.04/76.28 87805[105:MRR:87747.0,87804.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 87809[105:Res:53.1,87805.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 87811[105:MRR:87809.0,78381.0] || -> . % 76.04/76.28 87812[105:Spt:87811.0,87802.0,87803.0] || until2p7(s49)*+ -> . % 76.04/76.28 87813[105:Spt:87811.0,87802.1] || -> node4(s48)*. % 76.04/76.28 87814[105:MRR:78384.0,87813.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 87817[105:Res:53.1,87814.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 87820[105:Res:87817.0,61.1] always3(s48) || -> . % 76.04/76.28 87821[105:SSi:87820.0,78281.0,78387.0,78626.0,87801.0,87813.0] || -> . % 76.04/76.28 87822[104:Spt:87821.0,87800.0,87801.0] || until2p7(s48)*+ -> . % 76.04/76.28 87823[104:Spt:87821.0,87800.1] || -> node4(s47)*. % 76.04/76.28 87825[104:MRR:777.0,87823.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 87837[104:Res:53.1,87825.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 87839[105:Spt:87837.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 87841[105:Res:87839.0,61.1] always3(s47) || -> . % 76.04/76.28 87842[105:SSi:87841.0,78277.0,78280.0,78625.0,87799.0,87823.0] || -> . % 76.04/76.28 87843[105:Spt:87842.0,87837.0,87839.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 87844[105:Spt:87842.0,87837.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 87848[105:Res:87844.0,61.1] always3(s48) || -> . % 76.04/76.28 87849[105:SSi:87848.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 87850[103:Spt:87849.0,87798.0,87799.0] || until2p7(s47)*+ -> . % 76.04/76.28 87851[103:Spt:87849.0,87798.1] || -> node4(s46)*. % 76.04/76.28 87853[103:MRR:780.0,87851.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 87860[103:Res:53.1,87853.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 87865[104:Spt:87860.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 87867[104:Res:87865.0,61.1] always3(s46) || -> . % 76.04/76.28 87868[104:SSi:87867.0,78272.0,78276.0,78624.0,87797.0,87851.0] || -> . % 76.04/76.28 87869[104:Spt:87868.0,87860.0,87865.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 87870[104:Spt:87868.0,87860.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 87874[104:Res:87870.0,61.1] always3(s47) || -> . % 76.04/76.28 87875[104:SSi:87874.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 87876[102:Spt:87875.0,87796.0,87797.0] || until2p7(s46)*+ -> . % 76.04/76.28 87877[102:Spt:87875.0,87796.1] || -> node4(s45)*. % 76.04/76.28 87879[102:MRR:783.0,87877.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 87882[102:Res:53.1,87879.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 87884[103:Spt:87882.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 87886[103:Res:87884.0,61.1] always3(s45) || -> . % 76.04/76.28 87887[103:SSi:87886.0,78268.0,78271.0,78623.0,87795.0,87877.0] || -> . % 76.04/76.28 87888[103:Spt:87887.0,87882.0,87884.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 87889[103:Spt:87887.0,87882.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 87893[103:Res:87889.0,61.1] always3(s46) || -> . % 76.04/76.28 87894[103:SSi:87893.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 87895[101:Spt:87894.0,87794.0,87795.0] || until2p7(s45)*+ -> . % 76.04/76.28 87896[101:Spt:87894.0,87794.1] || -> node4(s44)*. % 76.04/76.28 87898[101:MRR:786.0,87896.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 87901[101:Res:53.1,87898.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 87903[102:Spt:87901.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 87905[102:Res:87903.0,61.1] always3(s44) || -> . % 76.04/76.28 87906[102:SSi:87905.0,78263.0,78267.0,78622.0,87793.0,87896.0] || -> . % 76.04/76.28 87907[102:Spt:87906.0,87901.0,87903.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 87908[102:Spt:87906.0,87901.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 87912[102:Res:87908.0,61.1] always3(s45) || -> . % 76.04/76.28 87913[102:SSi:87912.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 87914[100:Spt:87913.0,87792.0,87793.0] || until2p7(s44)*+ -> . % 76.04/76.28 87915[100:Spt:87913.0,87792.1] || -> node4(s43)*. % 76.04/76.28 87917[100:MRR:789.0,87915.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 87920[100:Res:53.1,87917.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 87922[101:Spt:87920.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 87924[101:Res:87922.0,61.1] always3(s43) || -> . % 76.04/76.28 87925[101:SSi:87924.0,78259.0,78262.0,78621.0,87791.0,87915.0] || -> . % 76.04/76.28 87926[101:Spt:87925.0,87920.0,87922.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 87927[101:Spt:87925.0,87920.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 87931[101:Res:87927.0,61.1] always3(s44) || -> . % 76.04/76.28 87932[101:SSi:87931.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 87933[99:Spt:87932.0,87790.0,87791.0] || until2p7(s43)*+ -> . % 76.04/76.28 87934[99:Spt:87932.0,87790.1] || -> node4(s42)*. % 76.04/76.28 87936[99:MRR:792.0,87934.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 87939[99:Res:53.1,87936.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 87944[100:Spt:87939.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 87946[100:Res:87944.0,61.1] always3(s42) || -> . % 76.04/76.28 87947[100:SSi:87946.0,78254.0,78258.0,78620.0,87789.0,87934.0] || -> . % 76.04/76.28 87948[100:Spt:87947.0,87939.0,87944.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 87949[100:Spt:87947.0,87939.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 87953[100:Res:87949.0,61.1] always3(s43) || -> . % 76.04/76.28 87954[100:SSi:87953.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 87955[98:Spt:87954.0,87788.0,87789.0] || until2p7(s42)*+ -> . % 76.04/76.28 87956[98:Spt:87954.0,87788.1] || -> node4(s41)*. % 76.04/76.28 87958[98:MRR:795.0,87956.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 87961[98:Res:53.1,87958.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 87963[99:Spt:87961.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 87965[99:Res:87963.0,61.1] always3(s41) || -> . % 76.04/76.28 87966[99:SSi:87965.0,78250.0,78253.0,78619.0,87787.0,87956.0] || -> . % 76.04/76.28 87967[99:Spt:87966.0,87961.0,87963.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 87968[99:Spt:87966.0,87961.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 87972[99:Res:87968.0,61.1] always3(s42) || -> . % 76.04/76.28 87973[99:SSi:87972.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 87974[97:Spt:87973.0,87786.0,87787.0] || until2p7(s41)*+ -> . % 76.04/76.28 87975[97:Spt:87973.0,87786.1] || -> node4(s40)*. % 76.04/76.28 87977[97:MRR:798.0,87975.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 87980[97:Res:53.1,87977.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 87982[98:Spt:87980.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 87984[98:Res:87982.0,61.1] always3(s40) || -> . % 76.04/76.28 87985[98:SSi:87984.0,78245.0,78249.0,78618.0,87785.0,87975.0] || -> . % 76.04/76.28 87986[98:Spt:87985.0,87980.0,87982.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 87987[98:Spt:87985.0,87980.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 87991[98:Res:87987.0,61.1] always3(s41) || -> . % 76.04/76.28 87992[98:SSi:87991.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 87993[96:Spt:87992.0,87784.0,87785.0] || until2p7(s40)*+ -> . % 76.04/76.28 87994[96:Spt:87992.0,87784.1] || -> node4(s39)*. % 76.04/76.28 87996[96:MRR:801.0,87994.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 87999[96:Res:53.1,87996.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 88001[97:Spt:87999.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 88003[97:Res:88001.0,61.1] always3(s39) || -> . % 76.04/76.28 88004[97:SSi:88003.0,78241.0,78244.0,78617.0,87783.0,87994.0] || -> . % 76.04/76.28 88005[97:Spt:88004.0,87999.0,88001.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 88006[97:Spt:88004.0,87999.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 88010[97:Res:88006.0,61.1] always3(s40) || -> . % 76.04/76.28 88011[97:SSi:88010.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 88012[95:Spt:88011.0,87782.0,87783.0] || until2p7(s39)*+ -> . % 76.04/76.28 88013[95:Spt:88011.0,87782.1] || -> node4(s38)*. % 76.04/76.28 88015[95:MRR:804.0,88013.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 88018[95:Res:53.1,88015.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 88023[96:Spt:88018.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 88025[96:Res:88023.0,61.1] always3(s38) || -> . % 76.04/76.28 88026[96:SSi:88025.0,78236.0,78240.0,78616.0,87781.0,88013.0] || -> . % 76.04/76.28 88027[96:Spt:88026.0,88018.0,88023.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 88028[96:Spt:88026.0,88018.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 88032[96:Res:88028.0,61.1] always3(s39) || -> . % 76.04/76.28 88033[96:SSi:88032.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 88034[94:Spt:88033.0,87780.0,87781.0] || until2p7(s38)*+ -> . % 76.04/76.28 88035[94:Spt:88033.0,87780.1] || -> node4(s37)*. % 76.04/76.28 88037[94:MRR:807.0,88035.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 88040[94:Res:53.1,88037.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 88042[95:Spt:88040.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 88044[95:Res:88042.0,61.1] always3(s37) || -> . % 76.04/76.28 88045[95:SSi:88044.0,78232.0,78235.0,78615.0,87779.0,88035.0] || -> . % 76.04/76.28 88046[95:Spt:88045.0,88040.0,88042.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 88047[95:Spt:88045.0,88040.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 88051[95:Res:88047.0,61.1] always3(s38) || -> . % 76.04/76.28 88052[95:SSi:88051.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 88053[93:Spt:88052.0,87778.0,87779.0] || until2p7(s37)*+ -> . % 76.04/76.28 88054[93:Spt:88052.0,87778.1] || -> node4(s36)*. % 76.04/76.28 88056[93:MRR:810.0,88054.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 88059[93:Res:53.1,88056.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 88061[94:Spt:88059.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 88063[94:Res:88061.0,61.1] always3(s36) || -> . % 76.04/76.28 88064[94:SSi:88063.0,78227.0,78231.0,78614.0,87777.0,88054.0] || -> . % 76.04/76.28 88065[94:Spt:88064.0,88059.0,88061.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 88066[94:Spt:88064.0,88059.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 88070[94:Res:88066.0,61.1] always3(s37) || -> . % 76.04/76.28 88071[94:SSi:88070.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 88072[92:Spt:88071.0,87776.0,87777.0] || until2p7(s36)*+ -> . % 76.04/76.28 88073[92:Spt:88071.0,87776.1] || -> node4(s35)*. % 76.04/76.28 88075[92:MRR:813.0,88073.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 88078[92:Res:53.1,88075.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 88080[93:Spt:88078.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 88082[93:Res:88080.0,61.1] always3(s35) || -> . % 76.04/76.28 88083[93:SSi:88082.0,78223.0,78226.0,78613.0,87775.0,88073.0] || -> . % 76.04/76.28 88084[93:Spt:88083.0,88078.0,88080.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.28 88085[93:Spt:88083.0,88078.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 88089[93:Res:88085.0,61.1] always3(s36) || -> . % 76.04/76.28 88090[93:SSi:88089.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 88091[91:Spt:88090.0,87774.0,87775.0] || until2p7(s35)*+ -> . % 76.04/76.28 88092[91:Spt:88090.0,87774.1] || -> node4(s34)*. % 76.04/76.28 88094[91:MRR:816.0,88092.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.28 88097[91:Res:53.1,88094.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.28 88102[92:Spt:88097.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 88104[92:Res:88102.0,61.1] always3(s34) || -> . % 76.04/76.28 88105[92:SSi:88104.0,78218.0,78222.0,78612.0,87773.0,88092.0] || -> . % 76.04/76.28 88106[92:Spt:88105.0,88097.0,88102.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.28 88107[92:Spt:88105.0,88097.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 88111[92:Res:88107.0,61.1] always3(s35) || -> . % 76.04/76.28 88112[92:SSi:88111.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 88113[90:Spt:88112.0,87772.0,87773.0] || until2p7(s34)*+ -> . % 76.04/76.28 88114[90:Spt:88112.0,87772.1] || -> node4(s33)*. % 76.04/76.28 88116[90:MRR:819.0,88114.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.28 88119[90:Res:53.1,88116.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.28 88121[91:Spt:88119.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 88123[91:Res:88121.0,61.1] always3(s33) || -> . % 76.04/76.28 88124[91:SSi:88123.0,78214.0,78217.0,78611.0,87771.0,88114.0] || -> . % 76.04/76.28 88125[91:Spt:88124.0,88119.0,88121.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.28 88126[91:Spt:88124.0,88119.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 88130[91:Res:88126.0,61.1] always3(s34) || -> . % 76.04/76.28 88131[91:SSi:88130.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.28 88132[89:Spt:88131.0,87770.0,87771.0] || until2p7(s33)*+ -> . % 76.04/76.28 88133[89:Spt:88131.0,87770.1] || -> node4(s32)*. % 76.04/76.28 88135[89:MRR:822.0,88133.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.28 88138[89:Res:53.1,88135.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.28 88140[90:Spt:88138.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 88142[90:Res:88140.0,61.1] always3(s32) || -> . % 76.04/76.28 88143[90:SSi:88142.0,78209.0,78213.0,78610.0,87769.0,88133.0] || -> . % 76.04/76.28 88144[90:Spt:88143.0,88138.0,88140.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.28 88145[90:Spt:88143.0,88138.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 88149[90:Res:88145.0,61.1] always3(s33) || -> . % 76.04/76.28 88150[90:SSi:88149.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.28 88151[88:Spt:88150.0,87768.0,87769.0] || until2p7(s32)*+ -> . % 76.04/76.28 88152[88:Spt:88150.0,87768.1] || -> node4(s31)*. % 76.04/76.28 88154[88:MRR:825.0,88152.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.28 88157[88:Res:53.1,88154.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.28 88159[89:Spt:88157.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 88161[89:Res:88159.0,61.1] always3(s31) || -> . % 76.04/76.28 88162[89:SSi:88161.0,78205.0,78208.0,78609.0,87767.0,88152.0] || -> . % 76.04/76.28 88163[89:Spt:88162.0,88157.0,88159.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.28 88164[89:Spt:88162.0,88157.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 88168[89:Res:88164.0,61.1] always3(s32) || -> . % 76.04/76.28 88169[89:SSi:88168.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.28 88170[87:Spt:88169.0,87766.0,87767.0] || until2p7(s31)*+ -> . % 76.04/76.28 88171[87:Spt:88169.0,87766.1] || -> node4(s30)*. % 76.04/76.28 88173[87:MRR:828.0,88171.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.28 88176[87:Res:53.1,88173.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.28 88181[88:Spt:88176.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 88183[88:Res:88181.0,61.1] always3(s30) || -> . % 76.04/76.28 88184[88:SSi:88183.0,78200.0,78204.0,78608.0,87765.0,88171.0] || -> . % 76.04/76.28 88185[88:Spt:88184.0,88176.0,88181.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.28 88186[88:Spt:88184.0,88176.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 88190[88:Res:88186.0,61.1] always3(s31) || -> . % 76.04/76.28 88191[88:SSi:88190.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.28 88192[86:Spt:88191.0,87764.0,87765.0] || until2p7(s30)*+ -> . % 76.04/76.28 88193[86:Spt:88191.0,87764.1] || -> node4(s29)*. % 76.04/76.28 88195[86:MRR:831.0,88193.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.28 88198[86:Res:53.1,88195.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.28 88200[87:Spt:88198.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 88202[87:Res:88200.0,61.1] always3(s29) || -> . % 76.04/76.28 88203[87:SSi:88202.0,78196.0,78199.0,78607.0,87763.0,88193.0] || -> . % 76.04/76.28 88204[87:Spt:88203.0,88198.0,88200.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.28 88205[87:Spt:88203.0,88198.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 88209[87:Res:88205.0,61.1] always3(s30) || -> . % 76.04/76.28 88210[87:SSi:88209.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.28 88211[85:Spt:88210.0,87762.0,87763.0] || until2p7(s29)*+ -> . % 76.04/76.28 88212[85:Spt:88210.0,87762.1] || -> node4(s28)*. % 76.04/76.28 88214[85:MRR:834.0,88212.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.28 88217[85:Res:53.1,88214.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.28 88219[86:Spt:88217.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 88221[86:Res:88219.0,61.1] always3(s28) || -> . % 76.04/76.28 88222[86:SSi:88221.0,78191.0,78195.0,78606.0,87761.0,88212.0] || -> . % 76.04/76.28 88223[86:Spt:88222.0,88217.0,88219.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.28 88224[86:Spt:88222.0,88217.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 88228[86:Res:88224.0,61.1] always3(s29) || -> . % 76.04/76.28 88229[86:SSi:88228.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.28 88230[84:Spt:88229.0,87760.0,87761.0] || until2p7(s28)*+ -> . % 76.04/76.28 88231[84:Spt:88229.0,87760.1] || -> node4(s27)*. % 76.04/76.28 88233[84:MRR:837.0,88231.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.28 88236[84:Res:53.1,88233.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.28 88238[85:Spt:88236.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.28 88240[85:Res:88238.0,61.1] always3(s27) || -> . % 76.04/76.28 88241[85:SSi:88240.0,78187.0,78190.0,78605.0,87759.0,88231.0] || -> . % 76.04/76.28 88242[85:Spt:88241.0,88236.0,88238.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.28 88243[85:Spt:88241.0,88236.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 88247[85:Res:88243.0,61.1] always3(s28) || -> . % 76.04/76.28 88248[85:SSi:88247.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.28 88249[83:Spt:88248.0,87758.0,87759.0] || until2p7(s27)*+ -> . % 76.04/76.28 88250[83:Spt:88248.0,87758.1] || -> node4(s26)*. % 76.04/76.28 88252[83:MRR:840.0,88250.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.28 88255[83:Res:53.1,88252.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.28 88260[84:Spt:88255.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.28 88262[84:Res:88260.0,61.1] always3(s26) || -> . % 76.04/76.28 88263[84:SSi:88262.0,78182.0,78186.0,78604.0,87757.0,88250.0] || -> . % 76.04/76.28 88264[84:Spt:88263.0,88255.0,88260.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.28 88265[84:Spt:88263.0,88255.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.28 88269[84:Res:88265.0,61.1] always3(s27) || -> . % 76.04/76.28 88270[84:SSi:88269.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.28 88271[82:Spt:88270.0,87756.0,87757.0] || until2p7(s26)*+ -> . % 76.04/76.28 88272[82:Spt:88270.0,87756.1] || -> node4(s25)*. % 76.04/76.28 88274[82:MRR:843.0,88272.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.28 88277[82:Res:53.1,88274.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.28 88279[83:Spt:88277.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.28 88281[83:Res:88279.0,61.1] always3(s25) || -> . % 76.04/76.28 88282[83:SSi:88281.0,78178.0,78181.0,78603.0,87755.0,88272.0] || -> . % 76.04/76.28 88283[83:Spt:88282.0,88277.0,88279.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.28 88284[83:Spt:88282.0,88277.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.28 88288[83:Res:88284.0,61.1] always3(s26) || -> . % 76.04/76.28 88289[83:SSi:88288.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.28 88290[81:Spt:88289.0,87754.0,87755.0] || until2p7(s25)*+ -> . % 76.04/76.28 88291[81:Spt:88289.0,87754.1] || -> node4(s24)*. % 76.04/76.28 88293[81:MRR:846.0,88291.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.28 88296[81:Res:53.1,88293.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.28 88298[82:Spt:88296.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.28 88300[82:Res:88298.0,61.1] always3(s24) || -> . % 76.04/76.28 88301[82:SSi:88300.0,78173.0,78177.0,78602.0,87753.0,88291.0] || -> . % 76.04/76.28 88302[82:Spt:88301.0,88296.0,88298.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.28 88303[82:Spt:88301.0,88296.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.28 88307[82:Res:88303.0,61.1] always3(s25) || -> . % 76.04/76.28 88308[82:SSi:88307.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.28 88309[80:Spt:88308.0,87752.0,87753.0] || until2p7(s24)*+ -> . % 76.04/76.28 88310[80:Spt:88308.0,87752.1] || -> node4(s23)*. % 76.04/76.28 88312[80:MRR:849.0,88310.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.28 88315[80:Res:53.1,88312.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.28 88317[80:MRR:88315.0,87742.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.28 88319[80:Res:88317.0,61.1] always3(s24) || -> . % 76.04/76.28 88320[80:SSi:88319.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.28 88321[78:Spt:88320.0,87637.0,87640.0] || trans(s49,s23)*+ -> . % 76.04/76.28 88322[78:Spt:88320.0,87637.1,87637.2,87637.3,87637.4,87637.5,87637.6,87637.7,87637.8,87637.9,87637.10,87637.11,87637.12,87637.13,87637.14,87637.15,87637.16,87637.17,87637.18,87637.19,87637.20,87637.21] || -> trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.28 88324[78:MRR:87639.1,88321.0] xuntil6(s49) || -> trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.28 88325[79:Spt:88322.0] || -> trans(s49,s22)*. % 76.04/76.28 88326[79:Res:88325.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s22)*. % 76.04/76.28 88328[79:Res:88325.0,60.0] || -> node2(s49,s22)*. % 76.04/76.28 88329[79:SSi:88326.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s22)*. % 76.04/76.28 88330[79:Res:88328.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)*. % 76.04/76.28 88423[79:SoR:88330.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)*. % 76.04/76.28 88425[79:SoR:88423.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)* xuntil6(s49). % 76.04/76.28 88426[79:SSi:88425.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s22,c_busy)* xuntil6(s49). % 76.04/76.28 88427[80:Spt:88426.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.28 88429[80:Res:88427.0,61.1] always3(s22) || -> . % 76.04/76.28 88430[80:SSi:88429.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.28 88431[80:Spt:88430.0,88426.1,88427.0] || m_main_v_state(s22,c_busy)*+ -> . % 76.04/76.28 88432[80:Spt:88430.0,88426.0,88426.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.28 88436[80:MRR:88423.2,88431.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.28 88437[80:Res:53.1,88432.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.28 88439[80:MRR:88437.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.28 88440[80:MRR:88329.0,88439.0] || -> until2p7(s22)*. % 76.04/76.28 88441[80:MRR:218.0,88440.0] || -> until2p7(s23)* node4(s22). % 76.04/76.28 88442[81:Spt:88441.0] || -> until2p7(s23)*. % 76.04/76.28 88443[81:MRR:219.0,88442.0] || -> until2p7(s24)* node4(s23). % 76.04/76.28 88444[82:Spt:88443.0] || -> until2p7(s24)*. % 76.04/76.28 88445[82:MRR:220.0,88444.0] || -> until2p7(s25)* node4(s24). % 76.04/76.28 88446[83:Spt:88445.0] || -> until2p7(s25)*. % 76.04/76.28 88447[83:MRR:221.0,88446.0] || -> until2p7(s26)* node4(s25). % 76.04/76.28 88448[84:Spt:88447.0] || -> until2p7(s26)*. % 76.04/76.28 88449[84:MRR:222.0,88448.0] || -> until2p7(s27)* node4(s26). % 76.04/76.28 88450[85:Spt:88449.0] || -> until2p7(s27)*. % 76.04/76.28 88451[85:MRR:223.0,88450.0] || -> until2p7(s28)* node4(s27). % 76.04/76.28 88452[86:Spt:88451.0] || -> until2p7(s28)*. % 76.04/76.28 88453[86:MRR:224.0,88452.0] || -> until2p7(s29)* node4(s28). % 76.04/76.28 88454[87:Spt:88453.0] || -> until2p7(s29)*. % 76.04/76.28 88455[87:MRR:225.0,88454.0] || -> until2p7(s30)* node4(s29). % 76.04/76.28 88456[88:Spt:88455.0] || -> until2p7(s30)*. % 76.04/76.28 88457[88:MRR:226.0,88456.0] || -> until2p7(s31)* node4(s30). % 76.04/76.28 88458[89:Spt:88457.0] || -> until2p7(s31)*. % 76.04/76.28 88459[89:MRR:227.0,88458.0] || -> until2p7(s32)* node4(s31). % 76.04/76.28 88460[90:Spt:88459.0] || -> until2p7(s32)*. % 76.04/76.28 88461[90:MRR:228.0,88460.0] || -> until2p7(s33)* node4(s32). % 76.04/76.28 88462[91:Spt:88461.0] || -> until2p7(s33)*. % 76.04/76.28 88463[91:MRR:229.0,88462.0] || -> until2p7(s34)* node4(s33). % 76.04/76.28 88464[92:Spt:88463.0] || -> until2p7(s34)*. % 76.04/76.28 88465[92:MRR:230.0,88464.0] || -> until2p7(s35)* node4(s34). % 76.04/76.28 88466[93:Spt:88465.0] || -> until2p7(s35)*. % 76.04/76.28 88467[93:MRR:231.0,88466.0] || -> until2p7(s36)* node4(s35). % 76.04/76.28 88468[94:Spt:88467.0] || -> until2p7(s36)*. % 76.04/76.28 88469[94:MRR:232.0,88468.0] || -> until2p7(s37)* node4(s36). % 76.04/76.28 88470[95:Spt:88469.0] || -> until2p7(s37)*. % 76.04/76.28 88471[95:MRR:235.0,88470.0] || -> until2p7(s38)* node4(s37). % 76.04/76.28 88472[96:Spt:88471.0] || -> until2p7(s38)*. % 76.04/76.28 88473[96:MRR:236.0,88472.0] || -> until2p7(s39)* node4(s38). % 76.04/76.28 88474[97:Spt:88473.0] || -> until2p7(s39)*. % 76.04/76.28 88475[97:MRR:237.0,88474.0] || -> until2p7(s40)* node4(s39). % 76.04/76.28 88476[98:Spt:88475.0] || -> until2p7(s40)*. % 76.04/76.28 88477[98:MRR:238.0,88476.0] || -> until2p7(s41)* node4(s40). % 76.04/76.28 88478[99:Spt:88477.0] || -> until2p7(s41)*. % 76.04/76.28 88479[99:MRR:239.0,88478.0] || -> until2p7(s42)* node4(s41). % 76.04/76.28 88480[100:Spt:88479.0] || -> until2p7(s42)*. % 76.04/76.28 88481[100:MRR:240.0,88480.0] || -> until2p7(s43)* node4(s42). % 76.04/76.28 88482[101:Spt:88481.0] || -> until2p7(s43)*. % 76.04/76.28 88483[101:MRR:241.0,88482.0] || -> until2p7(s44)* node4(s43). % 76.04/76.28 88484[102:Spt:88483.0] || -> until2p7(s44)*. % 76.04/76.28 88485[102:MRR:539.0,88484.0] || -> until2p7(s45)* node4(s44). % 76.04/76.28 88486[103:Spt:88485.0] || -> until2p7(s45)*. % 76.04/76.28 88487[103:MRR:544.0,88486.0] || -> until2p7(s46)* node4(s45). % 76.04/76.28 88488[104:Spt:88487.0] || -> until2p7(s46)*. % 76.04/76.28 88489[104:MRR:549.0,88488.0] || -> until2p7(s47)* node4(s46). % 76.04/76.28 88490[105:Spt:88489.0] || -> until2p7(s47)*. % 76.04/76.28 88491[105:MRR:554.0,88490.0] || -> until2p7(s48)* node4(s47). % 76.04/76.28 88492[106:Spt:88491.0] || -> until2p7(s48)*. % 76.04/76.28 88493[106:MRR:559.0,88492.0] || -> until2p7(s49)* node4(s48). % 76.04/76.28 88494[107:Spt:88493.0] || -> until2p7(s49)*. % 76.04/76.28 88495[107:MRR:194.0,88494.0] || -> node4(s49)*. % 76.04/76.28 88496[107:MRR:88436.0,88495.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.28 88497[107:Res:53.1,88496.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.28 88499[107:MRR:88497.0,78381.0] || -> . % 76.04/76.28 88500[107:Spt:88499.0,88493.0,88494.0] || until2p7(s49)*+ -> . % 76.04/76.28 88501[107:Spt:88499.0,88493.1] || -> node4(s48)*. % 76.04/76.28 88502[107:MRR:78384.0,88501.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.28 88505[107:Res:53.1,88502.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 88508[107:Res:88505.0,61.1] always3(s48) || -> . % 76.04/76.28 88509[107:SSi:88508.0,78281.0,78387.0,78626.0,88492.0,88501.0] || -> . % 76.04/76.28 88510[106:Spt:88509.0,88491.0,88492.0] || until2p7(s48)*+ -> . % 76.04/76.28 88511[106:Spt:88509.0,88491.1] || -> node4(s47)*. % 76.04/76.28 88513[106:MRR:777.0,88511.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.28 88528[106:Res:53.1,88513.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.28 88533[107:Spt:88528.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 88535[107:Res:88533.0,61.1] always3(s47) || -> . % 76.04/76.28 88536[107:SSi:88535.0,78277.0,78280.0,78625.0,88490.0,88511.0] || -> . % 76.04/76.28 88537[107:Spt:88536.0,88528.0,88533.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.28 88538[107:Spt:88536.0,88528.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.28 88542[107:Res:88538.0,61.1] always3(s48) || -> . % 76.04/76.28 88543[107:SSi:88542.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.28 88544[105:Spt:88543.0,88489.0,88490.0] || until2p7(s47)*+ -> . % 76.04/76.28 88545[105:Spt:88543.0,88489.1] || -> node4(s46)*. % 76.04/76.28 88547[105:MRR:780.0,88545.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.28 88554[105:Res:53.1,88547.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.28 88556[106:Spt:88554.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 88558[106:Res:88556.0,61.1] always3(s46) || -> . % 76.04/76.28 88559[106:SSi:88558.0,78272.0,78276.0,78624.0,88488.0,88545.0] || -> . % 76.04/76.28 88560[106:Spt:88559.0,88554.0,88556.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.28 88561[106:Spt:88559.0,88554.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.28 88565[106:Res:88561.0,61.1] always3(s47) || -> . % 76.04/76.28 88566[106:SSi:88565.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.28 88567[104:Spt:88566.0,88487.0,88488.0] || until2p7(s46)*+ -> . % 76.04/76.28 88568[104:Spt:88566.0,88487.1] || -> node4(s45)*. % 76.04/76.28 88570[104:MRR:783.0,88568.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.28 88573[104:Res:53.1,88570.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.28 88578[105:Spt:88573.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 88580[105:Res:88578.0,61.1] always3(s45) || -> . % 76.04/76.28 88581[105:SSi:88580.0,78268.0,78271.0,78623.0,88486.0,88568.0] || -> . % 76.04/76.28 88582[105:Spt:88581.0,88573.0,88578.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.28 88583[105:Spt:88581.0,88573.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.28 88587[105:Res:88583.0,61.1] always3(s46) || -> . % 76.04/76.28 88588[105:SSi:88587.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.28 88589[103:Spt:88588.0,88485.0,88486.0] || until2p7(s45)*+ -> . % 76.04/76.28 88590[103:Spt:88588.0,88485.1] || -> node4(s44)*. % 76.04/76.28 88592[103:MRR:786.0,88590.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.28 88595[103:Res:53.1,88592.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.28 88597[104:Spt:88595.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 88599[104:Res:88597.0,61.1] always3(s44) || -> . % 76.04/76.28 88600[104:SSi:88599.0,78263.0,78267.0,78622.0,88484.0,88590.0] || -> . % 76.04/76.28 88601[104:Spt:88600.0,88595.0,88597.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.28 88602[104:Spt:88600.0,88595.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.28 88606[104:Res:88602.0,61.1] always3(s45) || -> . % 76.04/76.28 88607[104:SSi:88606.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.28 88608[102:Spt:88607.0,88483.0,88484.0] || until2p7(s44)*+ -> . % 76.04/76.28 88609[102:Spt:88607.0,88483.1] || -> node4(s43)*. % 76.04/76.28 88611[102:MRR:789.0,88609.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.28 88614[102:Res:53.1,88611.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.28 88616[103:Spt:88614.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 88618[103:Res:88616.0,61.1] always3(s43) || -> . % 76.04/76.28 88619[103:SSi:88618.0,78259.0,78262.0,78621.0,88482.0,88609.0] || -> . % 76.04/76.28 88620[103:Spt:88619.0,88614.0,88616.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.28 88621[103:Spt:88619.0,88614.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.28 88625[103:Res:88621.0,61.1] always3(s44) || -> . % 76.04/76.28 88626[103:SSi:88625.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.28 88627[101:Spt:88626.0,88481.0,88482.0] || until2p7(s43)*+ -> . % 76.04/76.28 88628[101:Spt:88626.0,88481.1] || -> node4(s42)*. % 76.04/76.28 88630[101:MRR:792.0,88628.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.28 88633[101:Res:53.1,88630.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.28 88635[102:Spt:88633.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 88637[102:Res:88635.0,61.1] always3(s42) || -> . % 76.04/76.28 88638[102:SSi:88637.0,78254.0,78258.0,78620.0,88480.0,88628.0] || -> . % 76.04/76.28 88639[102:Spt:88638.0,88633.0,88635.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.28 88640[102:Spt:88638.0,88633.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.28 88644[102:Res:88640.0,61.1] always3(s43) || -> . % 76.04/76.28 88645[102:SSi:88644.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.28 88646[100:Spt:88645.0,88479.0,88480.0] || until2p7(s42)*+ -> . % 76.04/76.28 88647[100:Spt:88645.0,88479.1] || -> node4(s41)*. % 76.04/76.28 88649[100:MRR:795.0,88647.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.28 88652[100:Res:53.1,88649.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.28 88657[101:Spt:88652.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 88659[101:Res:88657.0,61.1] always3(s41) || -> . % 76.04/76.28 88660[101:SSi:88659.0,78250.0,78253.0,78619.0,88478.0,88647.0] || -> . % 76.04/76.28 88661[101:Spt:88660.0,88652.0,88657.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.28 88662[101:Spt:88660.0,88652.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.28 88666[101:Res:88662.0,61.1] always3(s42) || -> . % 76.04/76.28 88667[101:SSi:88666.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.28 88668[99:Spt:88667.0,88477.0,88478.0] || until2p7(s41)*+ -> . % 76.04/76.28 88669[99:Spt:88667.0,88477.1] || -> node4(s40)*. % 76.04/76.28 88671[99:MRR:798.0,88669.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.28 88674[99:Res:53.1,88671.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.28 88676[100:Spt:88674.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 88678[100:Res:88676.0,61.1] always3(s40) || -> . % 76.04/76.28 88679[100:SSi:88678.0,78245.0,78249.0,78618.0,88476.0,88669.0] || -> . % 76.04/76.28 88680[100:Spt:88679.0,88674.0,88676.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.28 88681[100:Spt:88679.0,88674.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.28 88685[100:Res:88681.0,61.1] always3(s41) || -> . % 76.04/76.28 88686[100:SSi:88685.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.28 88687[98:Spt:88686.0,88475.0,88476.0] || until2p7(s40)*+ -> . % 76.04/76.28 88688[98:Spt:88686.0,88475.1] || -> node4(s39)*. % 76.04/76.28 88690[98:MRR:801.0,88688.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.28 88693[98:Res:53.1,88690.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.28 88695[99:Spt:88693.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 88697[99:Res:88695.0,61.1] always3(s39) || -> . % 76.04/76.28 88698[99:SSi:88697.0,78241.0,78244.0,78617.0,88474.0,88688.0] || -> . % 76.04/76.28 88699[99:Spt:88698.0,88693.0,88695.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.28 88700[99:Spt:88698.0,88693.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.28 88704[99:Res:88700.0,61.1] always3(s40) || -> . % 76.04/76.28 88705[99:SSi:88704.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.28 88706[97:Spt:88705.0,88473.0,88474.0] || until2p7(s39)*+ -> . % 76.04/76.28 88707[97:Spt:88705.0,88473.1] || -> node4(s38)*. % 76.04/76.28 88709[97:MRR:804.0,88707.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.28 88712[97:Res:53.1,88709.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.28 88714[98:Spt:88712.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 88716[98:Res:88714.0,61.1] always3(s38) || -> . % 76.04/76.28 88717[98:SSi:88716.0,78236.0,78240.0,78616.0,88472.0,88707.0] || -> . % 76.04/76.28 88718[98:Spt:88717.0,88712.0,88714.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.28 88719[98:Spt:88717.0,88712.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.28 88723[98:Res:88719.0,61.1] always3(s39) || -> . % 76.04/76.28 88724[98:SSi:88723.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.28 88725[96:Spt:88724.0,88471.0,88472.0] || until2p7(s38)*+ -> . % 76.04/76.28 88726[96:Spt:88724.0,88471.1] || -> node4(s37)*. % 76.04/76.28 88728[96:MRR:807.0,88726.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.28 88731[96:Res:53.1,88728.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.28 88736[97:Spt:88731.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 88738[97:Res:88736.0,61.1] always3(s37) || -> . % 76.04/76.28 88739[97:SSi:88738.0,78232.0,78235.0,78615.0,88470.0,88726.0] || -> . % 76.04/76.28 88740[97:Spt:88739.0,88731.0,88736.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.28 88741[97:Spt:88739.0,88731.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.28 88745[97:Res:88741.0,61.1] always3(s38) || -> . % 76.04/76.28 88746[97:SSi:88745.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.28 88747[95:Spt:88746.0,88469.0,88470.0] || until2p7(s37)*+ -> . % 76.04/76.28 88748[95:Spt:88746.0,88469.1] || -> node4(s36)*. % 76.04/76.28 88750[95:MRR:810.0,88748.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.28 88753[95:Res:53.1,88750.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.28 88755[96:Spt:88753.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 88757[96:Res:88755.0,61.1] always3(s36) || -> . % 76.04/76.28 88758[96:SSi:88757.0,78227.0,78231.0,78614.0,88468.0,88748.0] || -> . % 76.04/76.28 88759[96:Spt:88758.0,88753.0,88755.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.28 88760[96:Spt:88758.0,88753.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.28 88764[96:Res:88760.0,61.1] always3(s37) || -> . % 76.04/76.28 88765[96:SSi:88764.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.28 88766[94:Spt:88765.0,88467.0,88468.0] || until2p7(s36)*+ -> . % 76.04/76.28 88767[94:Spt:88765.0,88467.1] || -> node4(s35)*. % 76.04/76.28 88769[94:MRR:813.0,88767.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.28 88772[94:Res:53.1,88769.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.28 88774[95:Spt:88772.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 88776[95:Res:88774.0,61.1] always3(s35) || -> . % 76.04/76.28 88777[95:SSi:88776.0,78223.0,78226.0,78613.0,88466.0,88767.0] || -> . % 76.04/76.28 88778[95:Spt:88777.0,88772.0,88774.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.28 88779[95:Spt:88777.0,88772.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.28 88783[95:Res:88779.0,61.1] always3(s36) || -> . % 76.04/76.28 88784[95:SSi:88783.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.28 88785[93:Spt:88784.0,88465.0,88466.0] || until2p7(s35)*+ -> . % 76.04/76.28 88786[93:Spt:88784.0,88465.1] || -> node4(s34)*. % 76.04/76.28 88788[93:MRR:816.0,88786.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.28 88791[93:Res:53.1,88788.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.28 88793[94:Spt:88791.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 88795[94:Res:88793.0,61.1] always3(s34) || -> . % 76.04/76.28 88796[94:SSi:88795.0,78218.0,78222.0,78612.0,88464.0,88786.0] || -> . % 76.04/76.28 88797[94:Spt:88796.0,88791.0,88793.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.28 88798[94:Spt:88796.0,88791.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.28 88802[94:Res:88798.0,61.1] always3(s35) || -> . % 76.04/76.28 88803[94:SSi:88802.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.28 88804[92:Spt:88803.0,88463.0,88464.0] || until2p7(s34)*+ -> . % 76.04/76.28 88805[92:Spt:88803.0,88463.1] || -> node4(s33)*. % 76.04/76.28 88807[92:MRR:819.0,88805.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.28 88810[92:Res:53.1,88807.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.28 88815[93:Spt:88810.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 88817[93:Res:88815.0,61.1] always3(s33) || -> . % 76.04/76.28 88818[93:SSi:88817.0,78214.0,78217.0,78611.0,88462.0,88805.0] || -> . % 76.04/76.28 88819[93:Spt:88818.0,88810.0,88815.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.28 88820[93:Spt:88818.0,88810.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.28 88824[93:Res:88820.0,61.1] always3(s34) || -> . % 76.04/76.28 88825[93:SSi:88824.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.28 88826[91:Spt:88825.0,88461.0,88462.0] || until2p7(s33)*+ -> . % 76.04/76.28 88827[91:Spt:88825.0,88461.1] || -> node4(s32)*. % 76.04/76.28 88829[91:MRR:822.0,88827.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.28 88832[91:Res:53.1,88829.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.28 88834[92:Spt:88832.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 88836[92:Res:88834.0,61.1] always3(s32) || -> . % 76.04/76.28 88837[92:SSi:88836.0,78209.0,78213.0,78610.0,88460.0,88827.0] || -> . % 76.04/76.28 88838[92:Spt:88837.0,88832.0,88834.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.28 88839[92:Spt:88837.0,88832.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.28 88843[92:Res:88839.0,61.1] always3(s33) || -> . % 76.04/76.28 88844[92:SSi:88843.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.28 88845[90:Spt:88844.0,88459.0,88460.0] || until2p7(s32)*+ -> . % 76.04/76.28 88846[90:Spt:88844.0,88459.1] || -> node4(s31)*. % 76.04/76.28 88848[90:MRR:825.0,88846.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.28 88851[90:Res:53.1,88848.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.28 88853[91:Spt:88851.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 88855[91:Res:88853.0,61.1] always3(s31) || -> . % 76.04/76.28 88856[91:SSi:88855.0,78205.0,78208.0,78609.0,88458.0,88846.0] || -> . % 76.04/76.28 88857[91:Spt:88856.0,88851.0,88853.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.28 88858[91:Spt:88856.0,88851.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.28 88862[91:Res:88858.0,61.1] always3(s32) || -> . % 76.04/76.28 88863[91:SSi:88862.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.28 88864[89:Spt:88863.0,88457.0,88458.0] || until2p7(s31)*+ -> . % 76.04/76.28 88865[89:Spt:88863.0,88457.1] || -> node4(s30)*. % 76.04/76.28 88867[89:MRR:828.0,88865.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.28 88870[89:Res:53.1,88867.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.28 88872[90:Spt:88870.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 88874[90:Res:88872.0,61.1] always3(s30) || -> . % 76.04/76.28 88875[90:SSi:88874.0,78200.0,78204.0,78608.0,88456.0,88865.0] || -> . % 76.04/76.28 88876[90:Spt:88875.0,88870.0,88872.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.28 88877[90:Spt:88875.0,88870.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.28 88881[90:Res:88877.0,61.1] always3(s31) || -> . % 76.04/76.28 88882[90:SSi:88881.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.28 88883[88:Spt:88882.0,88455.0,88456.0] || until2p7(s30)*+ -> . % 76.04/76.28 88884[88:Spt:88882.0,88455.1] || -> node4(s29)*. % 76.04/76.28 88886[88:MRR:831.0,88884.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.28 88889[88:Res:53.1,88886.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.28 88894[89:Spt:88889.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 88896[89:Res:88894.0,61.1] always3(s29) || -> . % 76.04/76.28 88897[89:SSi:88896.0,78196.0,78199.0,78607.0,88454.0,88884.0] || -> . % 76.04/76.28 88898[89:Spt:88897.0,88889.0,88894.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.28 88899[89:Spt:88897.0,88889.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.28 88903[89:Res:88899.0,61.1] always3(s30) || -> . % 76.04/76.28 88904[89:SSi:88903.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.28 88905[87:Spt:88904.0,88453.0,88454.0] || until2p7(s29)*+ -> . % 76.04/76.28 88906[87:Spt:88904.0,88453.1] || -> node4(s28)*. % 76.04/76.28 88908[87:MRR:834.0,88906.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.28 88911[87:Res:53.1,88908.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.28 88913[88:Spt:88911.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 88915[88:Res:88913.0,61.1] always3(s28) || -> . % 76.04/76.28 88916[88:SSi:88915.0,78191.0,78195.0,78606.0,88452.0,88906.0] || -> . % 76.04/76.28 88917[88:Spt:88916.0,88911.0,88913.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.28 88918[88:Spt:88916.0,88911.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.28 88922[88:Res:88918.0,61.1] always3(s29) || -> . % 76.04/76.28 88923[88:SSi:88922.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.28 88924[86:Spt:88923.0,88451.0,88452.0] || until2p7(s28)*+ -> . % 76.04/76.28 88925[86:Spt:88923.0,88451.1] || -> node4(s27)*. % 76.04/76.28 88927[86:MRR:837.0,88925.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.28 88930[86:Res:53.1,88927.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.28 88932[87:Spt:88930.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.28 88934[87:Res:88932.0,61.1] always3(s27) || -> . % 76.04/76.28 88935[87:SSi:88934.0,78187.0,78190.0,78605.0,88450.0,88925.0] || -> . % 76.04/76.28 88936[87:Spt:88935.0,88930.0,88932.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.28 88937[87:Spt:88935.0,88930.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.28 88941[87:Res:88937.0,61.1] always3(s28) || -> . % 76.04/76.28 88942[87:SSi:88941.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.28 88943[85:Spt:88942.0,88449.0,88450.0] || until2p7(s27)*+ -> . % 76.04/76.28 88944[85:Spt:88942.0,88449.1] || -> node4(s26)*. % 76.04/76.28 88946[85:MRR:840.0,88944.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.28 88949[85:Res:53.1,88946.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.28 88951[86:Spt:88949.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.28 88953[86:Res:88951.0,61.1] always3(s26) || -> . % 76.04/76.28 88954[86:SSi:88953.0,78182.0,78186.0,78604.0,88448.0,88944.0] || -> . % 76.04/76.28 88955[86:Spt:88954.0,88949.0,88951.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.28 88956[86:Spt:88954.0,88949.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.28 88960[86:Res:88956.0,61.1] always3(s27) || -> . % 76.04/76.28 88961[86:SSi:88960.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.28 88962[84:Spt:88961.0,88447.0,88448.0] || until2p7(s26)*+ -> . % 76.04/76.28 88963[84:Spt:88961.0,88447.1] || -> node4(s25)*. % 76.04/76.28 88965[84:MRR:843.0,88963.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.28 88968[84:Res:53.1,88965.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.28 88973[85:Spt:88968.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.28 88975[85:Res:88973.0,61.1] always3(s25) || -> . % 76.04/76.28 88976[85:SSi:88975.0,78178.0,78181.0,78603.0,88446.0,88963.0] || -> . % 76.04/76.28 88977[85:Spt:88976.0,88968.0,88973.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.28 88978[85:Spt:88976.0,88968.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.28 88982[85:Res:88978.0,61.1] always3(s26) || -> . % 76.04/76.28 88983[85:SSi:88982.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.28 88984[83:Spt:88983.0,88445.0,88446.0] || until2p7(s25)*+ -> . % 76.04/76.28 88985[83:Spt:88983.0,88445.1] || -> node4(s24)*. % 76.04/76.28 88987[83:MRR:846.0,88985.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.28 88990[83:Res:53.1,88987.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.28 88992[84:Spt:88990.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.28 88994[84:Res:88992.0,61.1] always3(s24) || -> . % 76.04/76.28 88995[84:SSi:88994.0,78173.0,78177.0,78602.0,88444.0,88985.0] || -> . % 76.04/76.28 88996[84:Spt:88995.0,88990.0,88992.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.28 88997[84:Spt:88995.0,88990.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.28 89001[84:Res:88997.0,61.1] always3(s25) || -> . % 76.04/76.28 89002[84:SSi:89001.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.29 89003[82:Spt:89002.0,88443.0,88444.0] || until2p7(s24)*+ -> . % 76.04/76.29 89004[82:Spt:89002.0,88443.1] || -> node4(s23)*. % 76.04/76.29 89006[82:MRR:849.0,89004.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.29 89009[82:Res:53.1,89006.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.29 89011[83:Spt:89009.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 89013[83:Res:89011.0,61.1] always3(s23) || -> . % 76.04/76.29 89014[83:SSi:89013.0,78169.0,78172.0,78601.0,88442.0,89004.0] || -> . % 76.04/76.29 89015[83:Spt:89014.0,89009.0,89011.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.29 89016[83:Spt:89014.0,89009.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 89020[83:Res:89016.0,61.1] always3(s24) || -> . % 76.04/76.29 89021[83:SSi:89020.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.29 89022[81:Spt:89021.0,88441.0,88442.0] || until2p7(s23)*+ -> . % 76.04/76.29 89023[81:Spt:89021.0,88441.1] || -> node4(s22)*. % 76.04/76.29 89025[81:MRR:852.0,89023.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.29 89028[81:Res:53.1,89025.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.29 89030[81:MRR:89028.0,88431.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 89032[81:Res:89030.0,61.1] always3(s23) || -> . % 76.04/76.29 89033[81:SSi:89032.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.29 89034[79:Spt:89033.0,88322.0,88325.0] || trans(s49,s22)*+ -> . % 76.04/76.29 89035[79:Spt:89033.0,88322.1,88322.2,88322.3,88322.4,88322.5,88322.6,88322.7,88322.8,88322.9,88322.10,88322.11,88322.12,88322.13,88322.14,88322.15,88322.16,88322.17,88322.18,88322.19,88322.20] || -> trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.29 89037[79:MRR:88324.1,89034.0] xuntil6(s49) || -> trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.29 89038[80:Spt:89035.0] || -> trans(s49,s21)*. % 76.04/76.29 89039[80:Res:89038.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s21)*. % 76.04/76.29 89041[80:Res:89038.0,60.0] || -> node2(s49,s21)*. % 76.04/76.29 89042[80:SSi:89039.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s21)*. % 76.04/76.29 89043[80:Res:89041.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 89137[80:SoR:89043.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 89139[80:SoR:89137.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)* xuntil6(s49). % 76.04/76.29 89140[80:SSi:89139.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s21,c_busy)* xuntil6(s49). % 76.04/76.29 89141[81:Spt:89140.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 89143[81:Res:89141.0,61.1] always3(s21) || -> . % 76.04/76.29 89144[81:SSi:89143.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.29 89145[81:Spt:89144.0,89140.1,89141.0] || m_main_v_state(s21,c_busy)*+ -> . % 76.04/76.29 89146[81:Spt:89144.0,89140.0,89140.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.29 89150[81:MRR:89137.2,89145.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.29 89151[81:Res:53.1,89146.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.29 89153[81:MRR:89151.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.29 89154[81:MRR:89042.0,89153.0] || -> until2p7(s21)*. % 76.04/76.29 89155[81:MRR:217.0,89154.0] || -> until2p7(s22)* node4(s21). % 76.04/76.29 89156[82:Spt:89155.0] || -> until2p7(s22)*. % 76.04/76.29 89157[82:MRR:218.0,89156.0] || -> until2p7(s23)* node4(s22). % 76.04/76.29 89158[83:Spt:89157.0] || -> until2p7(s23)*. % 76.04/76.29 89159[83:MRR:219.0,89158.0] || -> until2p7(s24)* node4(s23). % 76.04/76.29 89160[84:Spt:89159.0] || -> until2p7(s24)*. % 76.04/76.29 89161[84:MRR:220.0,89160.0] || -> until2p7(s25)* node4(s24). % 76.04/76.29 89162[85:Spt:89161.0] || -> until2p7(s25)*. % 76.04/76.29 89163[85:MRR:221.0,89162.0] || -> until2p7(s26)* node4(s25). % 76.04/76.29 89164[86:Spt:89163.0] || -> until2p7(s26)*. % 76.04/76.29 89165[86:MRR:222.0,89164.0] || -> until2p7(s27)* node4(s26). % 76.04/76.29 89166[87:Spt:89165.0] || -> until2p7(s27)*. % 76.04/76.29 89167[87:MRR:223.0,89166.0] || -> until2p7(s28)* node4(s27). % 76.04/76.29 89168[88:Spt:89167.0] || -> until2p7(s28)*. % 76.04/76.29 89169[88:MRR:224.0,89168.0] || -> until2p7(s29)* node4(s28). % 76.04/76.29 89170[89:Spt:89169.0] || -> until2p7(s29)*. % 76.04/76.29 89171[89:MRR:225.0,89170.0] || -> until2p7(s30)* node4(s29). % 76.04/76.29 89172[90:Spt:89171.0] || -> until2p7(s30)*. % 76.04/76.29 89173[90:MRR:226.0,89172.0] || -> until2p7(s31)* node4(s30). % 76.04/76.29 89174[91:Spt:89173.0] || -> until2p7(s31)*. % 76.04/76.29 89175[91:MRR:227.0,89174.0] || -> until2p7(s32)* node4(s31). % 76.04/76.29 89176[92:Spt:89175.0] || -> until2p7(s32)*. % 76.04/76.29 89177[92:MRR:228.0,89176.0] || -> until2p7(s33)* node4(s32). % 76.04/76.29 89178[93:Spt:89177.0] || -> until2p7(s33)*. % 76.04/76.29 89179[93:MRR:229.0,89178.0] || -> until2p7(s34)* node4(s33). % 76.04/76.29 89180[94:Spt:89179.0] || -> until2p7(s34)*. % 76.04/76.29 89181[94:MRR:230.0,89180.0] || -> until2p7(s35)* node4(s34). % 76.04/76.29 89182[95:Spt:89181.0] || -> until2p7(s35)*. % 76.04/76.29 89183[95:MRR:231.0,89182.0] || -> until2p7(s36)* node4(s35). % 76.04/76.29 89184[96:Spt:89183.0] || -> until2p7(s36)*. % 76.04/76.29 89185[96:MRR:232.0,89184.0] || -> until2p7(s37)* node4(s36). % 76.04/76.29 89186[97:Spt:89185.0] || -> until2p7(s37)*. % 76.04/76.29 89187[97:MRR:235.0,89186.0] || -> until2p7(s38)* node4(s37). % 76.04/76.29 89188[98:Spt:89187.0] || -> until2p7(s38)*. % 76.04/76.29 89189[98:MRR:236.0,89188.0] || -> until2p7(s39)* node4(s38). % 76.04/76.29 89190[99:Spt:89189.0] || -> until2p7(s39)*. % 76.04/76.29 89191[99:MRR:237.0,89190.0] || -> until2p7(s40)* node4(s39). % 76.04/76.29 89192[100:Spt:89191.0] || -> until2p7(s40)*. % 76.04/76.29 89193[100:MRR:238.0,89192.0] || -> until2p7(s41)* node4(s40). % 76.04/76.29 89194[101:Spt:89193.0] || -> until2p7(s41)*. % 76.04/76.29 89195[101:MRR:239.0,89194.0] || -> until2p7(s42)* node4(s41). % 76.04/76.29 89196[102:Spt:89195.0] || -> until2p7(s42)*. % 76.04/76.29 89197[102:MRR:240.0,89196.0] || -> until2p7(s43)* node4(s42). % 76.04/76.29 89198[103:Spt:89197.0] || -> until2p7(s43)*. % 76.04/76.29 89199[103:MRR:241.0,89198.0] || -> until2p7(s44)* node4(s43). % 76.04/76.29 89200[104:Spt:89199.0] || -> until2p7(s44)*. % 76.04/76.29 89201[104:MRR:539.0,89200.0] || -> until2p7(s45)* node4(s44). % 76.04/76.29 89202[105:Spt:89201.0] || -> until2p7(s45)*. % 76.04/76.29 89203[105:MRR:544.0,89202.0] || -> until2p7(s46)* node4(s45). % 76.04/76.29 89204[106:Spt:89203.0] || -> until2p7(s46)*. % 76.04/76.29 89205[106:MRR:549.0,89204.0] || -> until2p7(s47)* node4(s46). % 76.04/76.29 89206[107:Spt:89205.0] || -> until2p7(s47)*. % 76.04/76.29 89207[107:MRR:554.0,89206.0] || -> until2p7(s48)* node4(s47). % 76.04/76.29 89208[108:Spt:89207.0] || -> until2p7(s48)*. % 76.04/76.29 89209[108:MRR:559.0,89208.0] || -> until2p7(s49)* node4(s48). % 76.04/76.29 89210[109:Spt:89209.0] || -> until2p7(s49)*. % 76.04/76.29 89211[109:MRR:194.0,89210.0] || -> node4(s49)*. % 76.04/76.29 89212[109:MRR:89150.0,89211.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.29 89216[109:Res:53.1,89212.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.29 89218[109:MRR:89216.0,78381.0] || -> . % 76.04/76.29 89219[109:Spt:89218.0,89209.0,89210.0] || until2p7(s49)*+ -> . % 76.04/76.29 89220[109:Spt:89218.0,89209.1] || -> node4(s48)*. % 76.04/76.29 89221[109:MRR:78384.0,89220.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.29 89224[109:Res:53.1,89221.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 89227[109:Res:89224.0,61.1] always3(s48) || -> . % 76.04/76.29 89228[109:SSi:89227.0,78281.0,78387.0,78626.0,89208.0,89220.0] || -> . % 76.04/76.29 89229[108:Spt:89228.0,89207.0,89208.0] || until2p7(s48)*+ -> . % 76.04/76.29 89230[108:Spt:89228.0,89207.1] || -> node4(s47)*. % 76.04/76.29 89232[108:MRR:777.0,89230.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.29 89244[108:Res:53.1,89232.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.29 89246[109:Spt:89244.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 89248[109:Res:89246.0,61.1] always3(s47) || -> . % 76.04/76.29 89249[109:SSi:89248.0,78277.0,78280.0,78625.0,89206.0,89230.0] || -> . % 76.04/76.29 89250[109:Spt:89249.0,89244.0,89246.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.29 89251[109:Spt:89249.0,89244.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 89255[109:Res:89251.0,61.1] always3(s48) || -> . % 76.04/76.29 89256[109:SSi:89255.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.29 89257[107:Spt:89256.0,89205.0,89206.0] || until2p7(s47)*+ -> . % 76.04/76.29 89258[107:Spt:89256.0,89205.1] || -> node4(s46)*. % 76.04/76.29 89260[107:MRR:780.0,89258.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.29 89267[107:Res:53.1,89260.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.29 89272[108:Spt:89267.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 89274[108:Res:89272.0,61.1] always3(s46) || -> . % 76.04/76.29 89275[108:SSi:89274.0,78272.0,78276.0,78624.0,89204.0,89258.0] || -> . % 76.04/76.29 89276[108:Spt:89275.0,89267.0,89272.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.29 89277[108:Spt:89275.0,89267.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 89281[108:Res:89277.0,61.1] always3(s47) || -> . % 76.04/76.29 89282[108:SSi:89281.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.29 89283[106:Spt:89282.0,89203.0,89204.0] || until2p7(s46)*+ -> . % 76.04/76.29 89284[106:Spt:89282.0,89203.1] || -> node4(s45)*. % 76.04/76.29 89286[106:MRR:783.0,89284.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.29 89289[106:Res:53.1,89286.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.29 89291[107:Spt:89289.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 89293[107:Res:89291.0,61.1] always3(s45) || -> . % 76.04/76.29 89294[107:SSi:89293.0,78268.0,78271.0,78623.0,89202.0,89284.0] || -> . % 76.04/76.29 89295[107:Spt:89294.0,89289.0,89291.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.29 89296[107:Spt:89294.0,89289.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 89300[107:Res:89296.0,61.1] always3(s46) || -> . % 76.04/76.29 89301[107:SSi:89300.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.29 89302[105:Spt:89301.0,89201.0,89202.0] || until2p7(s45)*+ -> . % 76.04/76.29 89303[105:Spt:89301.0,89201.1] || -> node4(s44)*. % 76.04/76.29 89305[105:MRR:786.0,89303.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.29 89308[105:Res:53.1,89305.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.29 89310[106:Spt:89308.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 89312[106:Res:89310.0,61.1] always3(s44) || -> . % 76.04/76.29 89313[106:SSi:89312.0,78263.0,78267.0,78622.0,89200.0,89303.0] || -> . % 76.04/76.29 89314[106:Spt:89313.0,89308.0,89310.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.29 89315[106:Spt:89313.0,89308.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 89319[106:Res:89315.0,61.1] always3(s45) || -> . % 76.04/76.29 89320[106:SSi:89319.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.29 89321[104:Spt:89320.0,89199.0,89200.0] || until2p7(s44)*+ -> . % 76.04/76.29 89322[104:Spt:89320.0,89199.1] || -> node4(s43)*. % 76.04/76.29 89324[104:MRR:789.0,89322.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.29 89327[104:Res:53.1,89324.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.29 89329[105:Spt:89327.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 89331[105:Res:89329.0,61.1] always3(s43) || -> . % 76.04/76.29 89332[105:SSi:89331.0,78259.0,78262.0,78621.0,89198.0,89322.0] || -> . % 76.04/76.29 89333[105:Spt:89332.0,89327.0,89329.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.29 89334[105:Spt:89332.0,89327.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 89338[105:Res:89334.0,61.1] always3(s44) || -> . % 76.04/76.29 89339[105:SSi:89338.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.29 89340[103:Spt:89339.0,89197.0,89198.0] || until2p7(s43)*+ -> . % 76.04/76.29 89341[103:Spt:89339.0,89197.1] || -> node4(s42)*. % 76.04/76.29 89343[103:MRR:792.0,89341.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.29 89346[103:Res:53.1,89343.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.29 89351[104:Spt:89346.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 89353[104:Res:89351.0,61.1] always3(s42) || -> . % 76.04/76.29 89354[104:SSi:89353.0,78254.0,78258.0,78620.0,89196.0,89341.0] || -> . % 76.04/76.29 89355[104:Spt:89354.0,89346.0,89351.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.29 89356[104:Spt:89354.0,89346.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 89360[104:Res:89356.0,61.1] always3(s43) || -> . % 76.04/76.29 89361[104:SSi:89360.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.29 89362[102:Spt:89361.0,89195.0,89196.0] || until2p7(s42)*+ -> . % 76.04/76.29 89363[102:Spt:89361.0,89195.1] || -> node4(s41)*. % 76.04/76.29 89365[102:MRR:795.0,89363.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.29 89368[102:Res:53.1,89365.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.29 89370[103:Spt:89368.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 89372[103:Res:89370.0,61.1] always3(s41) || -> . % 76.04/76.29 89373[103:SSi:89372.0,78250.0,78253.0,78619.0,89194.0,89363.0] || -> . % 76.04/76.29 89374[103:Spt:89373.0,89368.0,89370.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.29 89375[103:Spt:89373.0,89368.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 89379[103:Res:89375.0,61.1] always3(s42) || -> . % 76.04/76.29 89380[103:SSi:89379.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.29 89381[101:Spt:89380.0,89193.0,89194.0] || until2p7(s41)*+ -> . % 76.04/76.29 89382[101:Spt:89380.0,89193.1] || -> node4(s40)*. % 76.04/76.29 89384[101:MRR:798.0,89382.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.29 89387[101:Res:53.1,89384.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.29 89389[102:Spt:89387.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 89391[102:Res:89389.0,61.1] always3(s40) || -> . % 76.04/76.29 89392[102:SSi:89391.0,78245.0,78249.0,78618.0,89192.0,89382.0] || -> . % 76.04/76.29 89393[102:Spt:89392.0,89387.0,89389.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.29 89394[102:Spt:89392.0,89387.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 89398[102:Res:89394.0,61.1] always3(s41) || -> . % 76.04/76.29 89399[102:SSi:89398.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.29 89400[100:Spt:89399.0,89191.0,89192.0] || until2p7(s40)*+ -> . % 76.04/76.29 89401[100:Spt:89399.0,89191.1] || -> node4(s39)*. % 76.04/76.29 89403[100:MRR:801.0,89401.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.29 89406[100:Res:53.1,89403.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.29 89408[101:Spt:89406.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 89410[101:Res:89408.0,61.1] always3(s39) || -> . % 76.04/76.29 89411[101:SSi:89410.0,78241.0,78244.0,78617.0,89190.0,89401.0] || -> . % 76.04/76.29 89412[101:Spt:89411.0,89406.0,89408.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.29 89413[101:Spt:89411.0,89406.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 89417[101:Res:89413.0,61.1] always3(s40) || -> . % 76.04/76.29 89418[101:SSi:89417.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.29 89419[99:Spt:89418.0,89189.0,89190.0] || until2p7(s39)*+ -> . % 76.04/76.29 89420[99:Spt:89418.0,89189.1] || -> node4(s38)*. % 76.04/76.29 89422[99:MRR:804.0,89420.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.29 89425[99:Res:53.1,89422.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.29 89430[100:Spt:89425.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 89432[100:Res:89430.0,61.1] always3(s38) || -> . % 76.04/76.29 89433[100:SSi:89432.0,78236.0,78240.0,78616.0,89188.0,89420.0] || -> . % 76.04/76.29 89434[100:Spt:89433.0,89425.0,89430.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.29 89435[100:Spt:89433.0,89425.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 89439[100:Res:89435.0,61.1] always3(s39) || -> . % 76.04/76.29 89440[100:SSi:89439.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.29 89441[98:Spt:89440.0,89187.0,89188.0] || until2p7(s38)*+ -> . % 76.04/76.29 89442[98:Spt:89440.0,89187.1] || -> node4(s37)*. % 76.04/76.29 89444[98:MRR:807.0,89442.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.29 89447[98:Res:53.1,89444.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.29 89449[99:Spt:89447.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 89451[99:Res:89449.0,61.1] always3(s37) || -> . % 76.04/76.29 89452[99:SSi:89451.0,78232.0,78235.0,78615.0,89186.0,89442.0] || -> . % 76.04/76.29 89453[99:Spt:89452.0,89447.0,89449.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.29 89454[99:Spt:89452.0,89447.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 89458[99:Res:89454.0,61.1] always3(s38) || -> . % 76.04/76.29 89459[99:SSi:89458.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.29 89460[97:Spt:89459.0,89185.0,89186.0] || until2p7(s37)*+ -> . % 76.04/76.29 89461[97:Spt:89459.0,89185.1] || -> node4(s36)*. % 76.04/76.29 89463[97:MRR:810.0,89461.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.29 89466[97:Res:53.1,89463.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.29 89468[98:Spt:89466.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 89470[98:Res:89468.0,61.1] always3(s36) || -> . % 76.04/76.29 89471[98:SSi:89470.0,78227.0,78231.0,78614.0,89184.0,89461.0] || -> . % 76.04/76.29 89472[98:Spt:89471.0,89466.0,89468.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.29 89473[98:Spt:89471.0,89466.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 89477[98:Res:89473.0,61.1] always3(s37) || -> . % 76.04/76.29 89478[98:SSi:89477.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.29 89479[96:Spt:89478.0,89183.0,89184.0] || until2p7(s36)*+ -> . % 76.04/76.29 89480[96:Spt:89478.0,89183.1] || -> node4(s35)*. % 76.04/76.29 89482[96:MRR:813.0,89480.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.29 89485[96:Res:53.1,89482.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.29 89487[97:Spt:89485.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 89489[97:Res:89487.0,61.1] always3(s35) || -> . % 76.04/76.29 89490[97:SSi:89489.0,78223.0,78226.0,78613.0,89182.0,89480.0] || -> . % 76.04/76.29 89491[97:Spt:89490.0,89485.0,89487.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.29 89492[97:Spt:89490.0,89485.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 89496[97:Res:89492.0,61.1] always3(s36) || -> . % 76.04/76.29 89497[97:SSi:89496.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.29 89498[95:Spt:89497.0,89181.0,89182.0] || until2p7(s35)*+ -> . % 76.04/76.29 89499[95:Spt:89497.0,89181.1] || -> node4(s34)*. % 76.04/76.29 89501[95:MRR:816.0,89499.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.29 89504[95:Res:53.1,89501.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.29 89509[96:Spt:89504.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 89511[96:Res:89509.0,61.1] always3(s34) || -> . % 76.04/76.29 89512[96:SSi:89511.0,78218.0,78222.0,78612.0,89180.0,89499.0] || -> . % 76.04/76.29 89513[96:Spt:89512.0,89504.0,89509.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.29 89514[96:Spt:89512.0,89504.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 89518[96:Res:89514.0,61.1] always3(s35) || -> . % 76.04/76.29 89519[96:SSi:89518.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.29 89520[94:Spt:89519.0,89179.0,89180.0] || until2p7(s34)*+ -> . % 76.04/76.29 89521[94:Spt:89519.0,89179.1] || -> node4(s33)*. % 76.04/76.29 89523[94:MRR:819.0,89521.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.29 89526[94:Res:53.1,89523.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.29 89528[95:Spt:89526.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 89530[95:Res:89528.0,61.1] always3(s33) || -> . % 76.04/76.29 89531[95:SSi:89530.0,78214.0,78217.0,78611.0,89178.0,89521.0] || -> . % 76.04/76.29 89532[95:Spt:89531.0,89526.0,89528.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.29 89533[95:Spt:89531.0,89526.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 89537[95:Res:89533.0,61.1] always3(s34) || -> . % 76.04/76.29 89538[95:SSi:89537.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.29 89539[93:Spt:89538.0,89177.0,89178.0] || until2p7(s33)*+ -> . % 76.04/76.29 89540[93:Spt:89538.0,89177.1] || -> node4(s32)*. % 76.04/76.29 89542[93:MRR:822.0,89540.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.29 89545[93:Res:53.1,89542.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.29 89547[94:Spt:89545.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 89549[94:Res:89547.0,61.1] always3(s32) || -> . % 76.04/76.29 89550[94:SSi:89549.0,78209.0,78213.0,78610.0,89176.0,89540.0] || -> . % 76.04/76.29 89551[94:Spt:89550.0,89545.0,89547.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.29 89552[94:Spt:89550.0,89545.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 89556[94:Res:89552.0,61.1] always3(s33) || -> . % 76.04/76.29 89557[94:SSi:89556.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.29 89558[92:Spt:89557.0,89175.0,89176.0] || until2p7(s32)*+ -> . % 76.04/76.29 89559[92:Spt:89557.0,89175.1] || -> node4(s31)*. % 76.04/76.29 89561[92:MRR:825.0,89559.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.29 89564[92:Res:53.1,89561.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.29 89566[93:Spt:89564.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 89568[93:Res:89566.0,61.1] always3(s31) || -> . % 76.04/76.29 89569[93:SSi:89568.0,78205.0,78208.0,78609.0,89174.0,89559.0] || -> . % 76.04/76.29 89570[93:Spt:89569.0,89564.0,89566.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.29 89571[93:Spt:89569.0,89564.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 89575[93:Res:89571.0,61.1] always3(s32) || -> . % 76.04/76.29 89576[93:SSi:89575.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.29 89577[91:Spt:89576.0,89173.0,89174.0] || until2p7(s31)*+ -> . % 76.04/76.29 89578[91:Spt:89576.0,89173.1] || -> node4(s30)*. % 76.04/76.29 89580[91:MRR:828.0,89578.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.29 89583[91:Res:53.1,89580.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.29 89588[92:Spt:89583.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 89590[92:Res:89588.0,61.1] always3(s30) || -> . % 76.04/76.29 89591[92:SSi:89590.0,78200.0,78204.0,78608.0,89172.0,89578.0] || -> . % 76.04/76.29 89592[92:Spt:89591.0,89583.0,89588.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.29 89593[92:Spt:89591.0,89583.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 89597[92:Res:89593.0,61.1] always3(s31) || -> . % 76.04/76.29 89598[92:SSi:89597.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.29 89599[90:Spt:89598.0,89171.0,89172.0] || until2p7(s30)*+ -> . % 76.04/76.29 89600[90:Spt:89598.0,89171.1] || -> node4(s29)*. % 76.04/76.29 89602[90:MRR:831.0,89600.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.29 89605[90:Res:53.1,89602.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.29 89607[91:Spt:89605.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 89609[91:Res:89607.0,61.1] always3(s29) || -> . % 76.04/76.29 89610[91:SSi:89609.0,78196.0,78199.0,78607.0,89170.0,89600.0] || -> . % 76.04/76.29 89611[91:Spt:89610.0,89605.0,89607.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.29 89612[91:Spt:89610.0,89605.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 89616[91:Res:89612.0,61.1] always3(s30) || -> . % 76.04/76.29 89617[91:SSi:89616.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.29 89618[89:Spt:89617.0,89169.0,89170.0] || until2p7(s29)*+ -> . % 76.04/76.29 89619[89:Spt:89617.0,89169.1] || -> node4(s28)*. % 76.04/76.29 89621[89:MRR:834.0,89619.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.29 89624[89:Res:53.1,89621.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.29 89626[90:Spt:89624.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 89628[90:Res:89626.0,61.1] always3(s28) || -> . % 76.04/76.29 89629[90:SSi:89628.0,78191.0,78195.0,78606.0,89168.0,89619.0] || -> . % 76.04/76.29 89630[90:Spt:89629.0,89624.0,89626.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.29 89631[90:Spt:89629.0,89624.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 89635[90:Res:89631.0,61.1] always3(s29) || -> . % 76.04/76.29 89636[90:SSi:89635.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.29 89637[88:Spt:89636.0,89167.0,89168.0] || until2p7(s28)*+ -> . % 76.04/76.29 89638[88:Spt:89636.0,89167.1] || -> node4(s27)*. % 76.04/76.29 89640[88:MRR:837.0,89638.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.29 89643[88:Res:53.1,89640.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.29 89645[89:Spt:89643.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 89647[89:Res:89645.0,61.1] always3(s27) || -> . % 76.04/76.29 89648[89:SSi:89647.0,78187.0,78190.0,78605.0,89166.0,89638.0] || -> . % 76.04/76.29 89649[89:Spt:89648.0,89643.0,89645.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.29 89650[89:Spt:89648.0,89643.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 89654[89:Res:89650.0,61.1] always3(s28) || -> . % 76.04/76.29 89655[89:SSi:89654.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.29 89656[87:Spt:89655.0,89165.0,89166.0] || until2p7(s27)*+ -> . % 76.04/76.29 89657[87:Spt:89655.0,89165.1] || -> node4(s26)*. % 76.04/76.29 89659[87:MRR:840.0,89657.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.29 89662[87:Res:53.1,89659.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.29 89667[88:Spt:89662.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 89669[88:Res:89667.0,61.1] always3(s26) || -> . % 76.04/76.29 89670[88:SSi:89669.0,78182.0,78186.0,78604.0,89164.0,89657.0] || -> . % 76.04/76.29 89671[88:Spt:89670.0,89662.0,89667.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.29 89672[88:Spt:89670.0,89662.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 89676[88:Res:89672.0,61.1] always3(s27) || -> . % 76.04/76.29 89677[88:SSi:89676.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.29 89678[86:Spt:89677.0,89163.0,89164.0] || until2p7(s26)*+ -> . % 76.04/76.29 89679[86:Spt:89677.0,89163.1] || -> node4(s25)*. % 76.04/76.29 89681[86:MRR:843.0,89679.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.29 89684[86:Res:53.1,89681.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.29 89686[87:Spt:89684.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 89688[87:Res:89686.0,61.1] always3(s25) || -> . % 76.04/76.29 89689[87:SSi:89688.0,78178.0,78181.0,78603.0,89162.0,89679.0] || -> . % 76.04/76.29 89690[87:Spt:89689.0,89684.0,89686.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.29 89691[87:Spt:89689.0,89684.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 89695[87:Res:89691.0,61.1] always3(s26) || -> . % 76.04/76.29 89696[87:SSi:89695.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.29 89697[85:Spt:89696.0,89161.0,89162.0] || until2p7(s25)*+ -> . % 76.04/76.29 89698[85:Spt:89696.0,89161.1] || -> node4(s24)*. % 76.04/76.29 89700[85:MRR:846.0,89698.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.29 89703[85:Res:53.1,89700.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.29 89705[86:Spt:89703.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 89707[86:Res:89705.0,61.1] always3(s24) || -> . % 76.04/76.29 89708[86:SSi:89707.0,78173.0,78177.0,78602.0,89160.0,89698.0] || -> . % 76.04/76.29 89709[86:Spt:89708.0,89703.0,89705.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.29 89710[86:Spt:89708.0,89703.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 89714[86:Res:89710.0,61.1] always3(s25) || -> . % 76.04/76.29 89715[86:SSi:89714.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.29 89716[84:Spt:89715.0,89159.0,89160.0] || until2p7(s24)*+ -> . % 76.04/76.29 89717[84:Spt:89715.0,89159.1] || -> node4(s23)*. % 76.04/76.29 89719[84:MRR:849.0,89717.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.29 89722[84:Res:53.1,89719.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.29 89724[85:Spt:89722.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 89726[85:Res:89724.0,61.1] always3(s23) || -> . % 76.04/76.29 89727[85:SSi:89726.0,78169.0,78172.0,78601.0,89158.0,89717.0] || -> . % 76.04/76.29 89728[85:Spt:89727.0,89722.0,89724.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.29 89729[85:Spt:89727.0,89722.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 89733[85:Res:89729.0,61.1] always3(s24) || -> . % 76.04/76.29 89734[85:SSi:89733.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.29 89735[83:Spt:89734.0,89157.0,89158.0] || until2p7(s23)*+ -> . % 76.04/76.29 89736[83:Spt:89734.0,89157.1] || -> node4(s22)*. % 76.04/76.29 89738[83:MRR:852.0,89736.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.29 89741[83:Res:53.1,89738.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.29 89746[84:Spt:89741.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 89748[84:Res:89746.0,61.1] always3(s22) || -> . % 76.04/76.29 89749[84:SSi:89748.0,78164.0,78168.0,78600.0,89156.0,89736.0] || -> . % 76.04/76.29 89750[84:Spt:89749.0,89741.0,89746.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.29 89751[84:Spt:89749.0,89741.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 89755[84:Res:89751.0,61.1] always3(s23) || -> . % 76.04/76.29 89756[84:SSi:89755.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.29 89757[82:Spt:89756.0,89155.0,89156.0] || until2p7(s22)*+ -> . % 76.04/76.29 89758[82:Spt:89756.0,89155.1] || -> node4(s21)*. % 76.04/76.29 89760[82:MRR:855.0,89758.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.29 89763[82:Res:53.1,89760.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.29 89765[82:MRR:89763.0,89145.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 89767[82:Res:89765.0,61.1] always3(s22) || -> . % 76.04/76.29 89768[82:SSi:89767.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.29 89769[80:Spt:89768.0,89035.0,89038.0] || trans(s49,s21)*+ -> . % 76.04/76.29 89770[80:Spt:89768.0,89035.1,89035.2,89035.3,89035.4,89035.5,89035.6,89035.7,89035.8,89035.9,89035.10,89035.11,89035.12,89035.13,89035.14,89035.15,89035.16,89035.17,89035.18,89035.19] || -> trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.29 89772[80:MRR:89037.1,89769.0] xuntil6(s49) || -> trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.29 89773[81:Spt:89770.0] || -> trans(s49,s20)*. % 76.04/76.29 89774[81:Res:89773.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s20)*. % 76.04/76.29 89776[81:Res:89773.0,60.0] || -> node2(s49,s20)*. % 76.04/76.29 89777[81:SSi:89774.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s20)*. % 76.04/76.29 89778[81:Res:89776.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 89876[81:SoR:89778.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 89878[81:SoR:89876.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)* xuntil6(s49). % 76.04/76.29 89879[81:SSi:89878.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s20,c_busy)* xuntil6(s49). % 76.04/76.29 89880[82:Spt:89879.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 89882[82:Res:89880.0,61.1] always3(s20) || -> . % 76.04/76.29 89883[82:SSi:89882.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.29 89884[82:Spt:89883.0,89879.1,89880.0] || m_main_v_state(s20,c_busy)*+ -> . % 76.04/76.29 89885[82:Spt:89883.0,89879.0,89879.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.29 89889[82:MRR:89876.2,89884.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.29 89890[82:Res:53.1,89885.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.29 89892[82:MRR:89890.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.29 89893[82:MRR:89777.0,89892.0] || -> until2p7(s20)*. % 76.04/76.29 89894[82:MRR:216.0,89893.0] || -> until2p7(s21)* node4(s20). % 76.04/76.29 89895[83:Spt:89894.0] || -> until2p7(s21)*. % 76.04/76.29 89896[83:MRR:217.0,89895.0] || -> until2p7(s22)* node4(s21). % 76.04/76.29 89897[84:Spt:89896.0] || -> until2p7(s22)*. % 76.04/76.29 89898[84:MRR:218.0,89897.0] || -> until2p7(s23)* node4(s22). % 76.04/76.29 89899[85:Spt:89898.0] || -> until2p7(s23)*. % 76.04/76.29 89900[85:MRR:219.0,89899.0] || -> until2p7(s24)* node4(s23). % 76.04/76.29 89901[86:Spt:89900.0] || -> until2p7(s24)*. % 76.04/76.29 89902[86:MRR:220.0,89901.0] || -> until2p7(s25)* node4(s24). % 76.04/76.29 89903[87:Spt:89902.0] || -> until2p7(s25)*. % 76.04/76.29 89904[87:MRR:221.0,89903.0] || -> until2p7(s26)* node4(s25). % 76.04/76.29 89905[88:Spt:89904.0] || -> until2p7(s26)*. % 76.04/76.29 89906[88:MRR:222.0,89905.0] || -> until2p7(s27)* node4(s26). % 76.04/76.29 89907[89:Spt:89906.0] || -> until2p7(s27)*. % 76.04/76.29 89908[89:MRR:223.0,89907.0] || -> until2p7(s28)* node4(s27). % 76.04/76.29 89909[90:Spt:89908.0] || -> until2p7(s28)*. % 76.04/76.29 89910[90:MRR:224.0,89909.0] || -> until2p7(s29)* node4(s28). % 76.04/76.29 89911[91:Spt:89910.0] || -> until2p7(s29)*. % 76.04/76.29 89912[91:MRR:225.0,89911.0] || -> until2p7(s30)* node4(s29). % 76.04/76.29 89913[92:Spt:89912.0] || -> until2p7(s30)*. % 76.04/76.29 89914[92:MRR:226.0,89913.0] || -> until2p7(s31)* node4(s30). % 76.04/76.29 89915[93:Spt:89914.0] || -> until2p7(s31)*. % 76.04/76.29 89916[93:MRR:227.0,89915.0] || -> until2p7(s32)* node4(s31). % 76.04/76.29 89917[94:Spt:89916.0] || -> until2p7(s32)*. % 76.04/76.29 89918[94:MRR:228.0,89917.0] || -> until2p7(s33)* node4(s32). % 76.04/76.29 89919[95:Spt:89918.0] || -> until2p7(s33)*. % 76.04/76.29 89920[95:MRR:229.0,89919.0] || -> until2p7(s34)* node4(s33). % 76.04/76.29 89921[96:Spt:89920.0] || -> until2p7(s34)*. % 76.04/76.29 89922[96:MRR:230.0,89921.0] || -> until2p7(s35)* node4(s34). % 76.04/76.29 89923[97:Spt:89922.0] || -> until2p7(s35)*. % 76.04/76.29 89924[97:MRR:231.0,89923.0] || -> until2p7(s36)* node4(s35). % 76.04/76.29 89925[98:Spt:89924.0] || -> until2p7(s36)*. % 76.04/76.29 89926[98:MRR:232.0,89925.0] || -> until2p7(s37)* node4(s36). % 76.04/76.29 89927[99:Spt:89926.0] || -> until2p7(s37)*. % 76.04/76.29 89928[99:MRR:235.0,89927.0] || -> until2p7(s38)* node4(s37). % 76.04/76.29 89929[100:Spt:89928.0] || -> until2p7(s38)*. % 76.04/76.29 89930[100:MRR:236.0,89929.0] || -> until2p7(s39)* node4(s38). % 76.04/76.29 89931[101:Spt:89930.0] || -> until2p7(s39)*. % 76.04/76.29 89932[101:MRR:237.0,89931.0] || -> until2p7(s40)* node4(s39). % 76.04/76.29 89933[102:Spt:89932.0] || -> until2p7(s40)*. % 76.04/76.29 89934[102:MRR:238.0,89933.0] || -> until2p7(s41)* node4(s40). % 76.04/76.29 89935[103:Spt:89934.0] || -> until2p7(s41)*. % 76.04/76.29 89936[103:MRR:239.0,89935.0] || -> until2p7(s42)* node4(s41). % 76.04/76.29 89937[104:Spt:89936.0] || -> until2p7(s42)*. % 76.04/76.29 89938[104:MRR:240.0,89937.0] || -> until2p7(s43)* node4(s42). % 76.04/76.29 89939[105:Spt:89938.0] || -> until2p7(s43)*. % 76.04/76.29 89940[105:MRR:241.0,89939.0] || -> until2p7(s44)* node4(s43). % 76.04/76.29 89941[106:Spt:89940.0] || -> until2p7(s44)*. % 76.04/76.29 89942[106:MRR:539.0,89941.0] || -> until2p7(s45)* node4(s44). % 76.04/76.29 89943[107:Spt:89942.0] || -> until2p7(s45)*. % 76.04/76.29 89944[107:MRR:544.0,89943.0] || -> until2p7(s46)* node4(s45). % 76.04/76.29 89945[108:Spt:89944.0] || -> until2p7(s46)*. % 76.04/76.29 89946[108:MRR:549.0,89945.0] || -> until2p7(s47)* node4(s46). % 76.04/76.29 89947[109:Spt:89946.0] || -> until2p7(s47)*. % 76.04/76.29 89948[109:MRR:554.0,89947.0] || -> until2p7(s48)* node4(s47). % 76.04/76.29 89949[110:Spt:89948.0] || -> until2p7(s48)*. % 76.04/76.29 89950[110:MRR:559.0,89949.0] || -> until2p7(s49)* node4(s48). % 76.04/76.29 89951[111:Spt:89950.0] || -> until2p7(s49)*. % 76.04/76.29 89952[111:MRR:194.0,89951.0] || -> node4(s49)*. % 76.04/76.29 89953[111:MRR:89889.0,89952.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.29 89954[111:Res:53.1,89953.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.29 89956[111:MRR:89954.0,78381.0] || -> . % 76.04/76.29 89957[111:Spt:89956.0,89950.0,89951.0] || until2p7(s49)*+ -> . % 76.04/76.29 89958[111:Spt:89956.0,89950.1] || -> node4(s48)*. % 76.04/76.29 89959[111:MRR:78384.0,89958.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.29 89962[111:Res:53.1,89959.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 89965[111:Res:89962.0,61.1] always3(s48) || -> . % 76.04/76.29 89966[111:SSi:89965.0,78281.0,78387.0,78626.0,89949.0,89958.0] || -> . % 76.04/76.29 89967[110:Spt:89966.0,89948.0,89949.0] || until2p7(s48)*+ -> . % 76.04/76.29 89968[110:Spt:89966.0,89948.1] || -> node4(s47)*. % 76.04/76.29 89970[110:MRR:777.0,89968.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.29 89985[110:Res:53.1,89970.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.29 89987[111:Spt:89985.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 89989[111:Res:89987.0,61.1] always3(s47) || -> . % 76.04/76.29 89990[111:SSi:89989.0,78277.0,78280.0,78625.0,89947.0,89968.0] || -> . % 76.04/76.29 89991[111:Spt:89990.0,89985.0,89987.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.29 89992[111:Spt:89990.0,89985.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 89996[111:Res:89992.0,61.1] always3(s48) || -> . % 76.04/76.29 89997[111:SSi:89996.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.29 89998[109:Spt:89997.0,89946.0,89947.0] || until2p7(s47)*+ -> . % 76.04/76.29 89999[109:Spt:89997.0,89946.1] || -> node4(s46)*. % 76.04/76.29 90001[109:MRR:780.0,89999.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.29 90011[109:Res:53.1,90001.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.29 90013[110:Spt:90011.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 90015[110:Res:90013.0,61.1] always3(s46) || -> . % 76.04/76.29 90016[110:SSi:90015.0,78272.0,78276.0,78624.0,89945.0,89999.0] || -> . % 76.04/76.29 90017[110:Spt:90016.0,90011.0,90013.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.29 90018[110:Spt:90016.0,90011.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 90022[110:Res:90018.0,61.1] always3(s47) || -> . % 76.04/76.29 90023[110:SSi:90022.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.29 90024[108:Spt:90023.0,89944.0,89945.0] || until2p7(s46)*+ -> . % 76.04/76.29 90025[108:Spt:90023.0,89944.1] || -> node4(s45)*. % 76.04/76.29 90027[108:MRR:783.0,90025.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.29 90030[108:Res:53.1,90027.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.29 90032[109:Spt:90030.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 90034[109:Res:90032.0,61.1] always3(s45) || -> . % 76.04/76.29 90035[109:SSi:90034.0,78268.0,78271.0,78623.0,89943.0,90025.0] || -> . % 76.04/76.29 90036[109:Spt:90035.0,90030.0,90032.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.29 90037[109:Spt:90035.0,90030.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 90041[109:Res:90037.0,61.1] always3(s46) || -> . % 76.04/76.29 90042[109:SSi:90041.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.29 90043[107:Spt:90042.0,89942.0,89943.0] || until2p7(s45)*+ -> . % 76.04/76.29 90044[107:Spt:90042.0,89942.1] || -> node4(s44)*. % 76.04/76.29 90046[107:MRR:786.0,90044.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.29 90049[107:Res:53.1,90046.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.29 90051[108:Spt:90049.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 90053[108:Res:90051.0,61.1] always3(s44) || -> . % 76.04/76.29 90054[108:SSi:90053.0,78263.0,78267.0,78622.0,89941.0,90044.0] || -> . % 76.04/76.29 90055[108:Spt:90054.0,90049.0,90051.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.29 90056[108:Spt:90054.0,90049.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 90060[108:Res:90056.0,61.1] always3(s45) || -> . % 76.04/76.29 90061[108:SSi:90060.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.29 90062[106:Spt:90061.0,89940.0,89941.0] || until2p7(s44)*+ -> . % 76.04/76.29 90063[106:Spt:90061.0,89940.1] || -> node4(s43)*. % 76.04/76.29 90065[106:MRR:789.0,90063.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.29 90068[106:Res:53.1,90065.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.29 90073[107:Spt:90068.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 90075[107:Res:90073.0,61.1] always3(s43) || -> . % 76.04/76.29 90076[107:SSi:90075.0,78259.0,78262.0,78621.0,89939.0,90063.0] || -> . % 76.04/76.29 90077[107:Spt:90076.0,90068.0,90073.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.29 90078[107:Spt:90076.0,90068.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 90082[107:Res:90078.0,61.1] always3(s44) || -> . % 76.04/76.29 90083[107:SSi:90082.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.29 90084[105:Spt:90083.0,89938.0,89939.0] || until2p7(s43)*+ -> . % 76.04/76.29 90085[105:Spt:90083.0,89938.1] || -> node4(s42)*. % 76.04/76.29 90087[105:MRR:792.0,90085.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.29 90090[105:Res:53.1,90087.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.29 90092[106:Spt:90090.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 90094[106:Res:90092.0,61.1] always3(s42) || -> . % 76.04/76.29 90095[106:SSi:90094.0,78254.0,78258.0,78620.0,89937.0,90085.0] || -> . % 76.04/76.29 90096[106:Spt:90095.0,90090.0,90092.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.29 90097[106:Spt:90095.0,90090.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 90101[106:Res:90097.0,61.1] always3(s43) || -> . % 76.04/76.29 90102[106:SSi:90101.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.29 90103[104:Spt:90102.0,89936.0,89937.0] || until2p7(s42)*+ -> . % 76.04/76.29 90104[104:Spt:90102.0,89936.1] || -> node4(s41)*. % 76.04/76.29 90106[104:MRR:795.0,90104.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.29 90109[104:Res:53.1,90106.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.29 90111[105:Spt:90109.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 90113[105:Res:90111.0,61.1] always3(s41) || -> . % 76.04/76.29 90114[105:SSi:90113.0,78250.0,78253.0,78619.0,89935.0,90104.0] || -> . % 76.04/76.29 90115[105:Spt:90114.0,90109.0,90111.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.29 90116[105:Spt:90114.0,90109.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 90120[105:Res:90116.0,61.1] always3(s42) || -> . % 76.04/76.29 90121[105:SSi:90120.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.29 90122[103:Spt:90121.0,89934.0,89935.0] || until2p7(s41)*+ -> . % 76.04/76.29 90123[103:Spt:90121.0,89934.1] || -> node4(s40)*. % 76.04/76.29 90125[103:MRR:798.0,90123.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.29 90128[103:Res:53.1,90125.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.29 90130[104:Spt:90128.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 90132[104:Res:90130.0,61.1] always3(s40) || -> . % 76.04/76.29 90133[104:SSi:90132.0,78245.0,78249.0,78618.0,89933.0,90123.0] || -> . % 76.04/76.29 90134[104:Spt:90133.0,90128.0,90130.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.29 90135[104:Spt:90133.0,90128.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 90139[104:Res:90135.0,61.1] always3(s41) || -> . % 76.04/76.29 90140[104:SSi:90139.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.29 90141[102:Spt:90140.0,89932.0,89933.0] || until2p7(s40)*+ -> . % 76.04/76.29 90142[102:Spt:90140.0,89932.1] || -> node4(s39)*. % 76.04/76.29 90144[102:MRR:801.0,90142.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.29 90147[102:Res:53.1,90144.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.29 90152[103:Spt:90147.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 90154[103:Res:90152.0,61.1] always3(s39) || -> . % 76.04/76.29 90155[103:SSi:90154.0,78241.0,78244.0,78617.0,89931.0,90142.0] || -> . % 76.04/76.29 90156[103:Spt:90155.0,90147.0,90152.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.29 90157[103:Spt:90155.0,90147.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 90161[103:Res:90157.0,61.1] always3(s40) || -> . % 76.04/76.29 90162[103:SSi:90161.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.29 90163[101:Spt:90162.0,89930.0,89931.0] || until2p7(s39)*+ -> . % 76.04/76.29 90164[101:Spt:90162.0,89930.1] || -> node4(s38)*. % 76.04/76.29 90166[101:MRR:804.0,90164.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.29 90169[101:Res:53.1,90166.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.29 90171[102:Spt:90169.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 90173[102:Res:90171.0,61.1] always3(s38) || -> . % 76.04/76.29 90174[102:SSi:90173.0,78236.0,78240.0,78616.0,89929.0,90164.0] || -> . % 76.04/76.29 90175[102:Spt:90174.0,90169.0,90171.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.29 90176[102:Spt:90174.0,90169.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 90180[102:Res:90176.0,61.1] always3(s39) || -> . % 76.04/76.29 90181[102:SSi:90180.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.29 90182[100:Spt:90181.0,89928.0,89929.0] || until2p7(s38)*+ -> . % 76.04/76.29 90183[100:Spt:90181.0,89928.1] || -> node4(s37)*. % 76.04/76.29 90185[100:MRR:807.0,90183.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.29 90188[100:Res:53.1,90185.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.29 90190[101:Spt:90188.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 90192[101:Res:90190.0,61.1] always3(s37) || -> . % 76.04/76.29 90193[101:SSi:90192.0,78232.0,78235.0,78615.0,89927.0,90183.0] || -> . % 76.04/76.29 90194[101:Spt:90193.0,90188.0,90190.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.29 90195[101:Spt:90193.0,90188.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 90199[101:Res:90195.0,61.1] always3(s38) || -> . % 76.04/76.29 90200[101:SSi:90199.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.29 90201[99:Spt:90200.0,89926.0,89927.0] || until2p7(s37)*+ -> . % 76.04/76.29 90202[99:Spt:90200.0,89926.1] || -> node4(s36)*. % 76.04/76.29 90204[99:MRR:810.0,90202.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.29 90207[99:Res:53.1,90204.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.29 90209[100:Spt:90207.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 90211[100:Res:90209.0,61.1] always3(s36) || -> . % 76.04/76.29 90212[100:SSi:90211.0,78227.0,78231.0,78614.0,89925.0,90202.0] || -> . % 76.04/76.29 90213[100:Spt:90212.0,90207.0,90209.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.29 90214[100:Spt:90212.0,90207.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 90218[100:Res:90214.0,61.1] always3(s37) || -> . % 76.04/76.29 90219[100:SSi:90218.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.29 90220[98:Spt:90219.0,89924.0,89925.0] || until2p7(s36)*+ -> . % 76.04/76.29 90221[98:Spt:90219.0,89924.1] || -> node4(s35)*. % 76.04/76.29 90223[98:MRR:813.0,90221.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.29 90226[98:Res:53.1,90223.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.29 90231[99:Spt:90226.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 90233[99:Res:90231.0,61.1] always3(s35) || -> . % 76.04/76.29 90234[99:SSi:90233.0,78223.0,78226.0,78613.0,89923.0,90221.0] || -> . % 76.04/76.29 90235[99:Spt:90234.0,90226.0,90231.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.29 90236[99:Spt:90234.0,90226.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 90240[99:Res:90236.0,61.1] always3(s36) || -> . % 76.04/76.29 90241[99:SSi:90240.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.29 90242[97:Spt:90241.0,89922.0,89923.0] || until2p7(s35)*+ -> . % 76.04/76.29 90243[97:Spt:90241.0,89922.1] || -> node4(s34)*. % 76.04/76.29 90245[97:MRR:816.0,90243.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.29 90248[97:Res:53.1,90245.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.29 90250[98:Spt:90248.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 90252[98:Res:90250.0,61.1] always3(s34) || -> . % 76.04/76.29 90253[98:SSi:90252.0,78218.0,78222.0,78612.0,89921.0,90243.0] || -> . % 76.04/76.29 90254[98:Spt:90253.0,90248.0,90250.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.29 90255[98:Spt:90253.0,90248.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 90259[98:Res:90255.0,61.1] always3(s35) || -> . % 76.04/76.29 90260[98:SSi:90259.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.29 90261[96:Spt:90260.0,89920.0,89921.0] || until2p7(s34)*+ -> . % 76.04/76.29 90262[96:Spt:90260.0,89920.1] || -> node4(s33)*. % 76.04/76.29 90264[96:MRR:819.0,90262.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.29 90267[96:Res:53.1,90264.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.29 90269[97:Spt:90267.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 90271[97:Res:90269.0,61.1] always3(s33) || -> . % 76.04/76.29 90272[97:SSi:90271.0,78214.0,78217.0,78611.0,89919.0,90262.0] || -> . % 76.04/76.29 90273[97:Spt:90272.0,90267.0,90269.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.29 90274[97:Spt:90272.0,90267.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 90278[97:Res:90274.0,61.1] always3(s34) || -> . % 76.04/76.29 90279[97:SSi:90278.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.29 90280[95:Spt:90279.0,89918.0,89919.0] || until2p7(s33)*+ -> . % 76.04/76.29 90281[95:Spt:90279.0,89918.1] || -> node4(s32)*. % 76.04/76.29 90283[95:MRR:822.0,90281.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.29 90286[95:Res:53.1,90283.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.29 90288[96:Spt:90286.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 90290[96:Res:90288.0,61.1] always3(s32) || -> . % 76.04/76.29 90291[96:SSi:90290.0,78209.0,78213.0,78610.0,89917.0,90281.0] || -> . % 76.04/76.29 90292[96:Spt:90291.0,90286.0,90288.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.29 90293[96:Spt:90291.0,90286.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 90297[96:Res:90293.0,61.1] always3(s33) || -> . % 76.04/76.29 90298[96:SSi:90297.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.29 90299[94:Spt:90298.0,89916.0,89917.0] || until2p7(s32)*+ -> . % 76.04/76.29 90300[94:Spt:90298.0,89916.1] || -> node4(s31)*. % 76.04/76.29 90302[94:MRR:825.0,90300.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.29 90305[94:Res:53.1,90302.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.29 90310[95:Spt:90305.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 90312[95:Res:90310.0,61.1] always3(s31) || -> . % 76.04/76.29 90313[95:SSi:90312.0,78205.0,78208.0,78609.0,89915.0,90300.0] || -> . % 76.04/76.29 90314[95:Spt:90313.0,90305.0,90310.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.29 90315[95:Spt:90313.0,90305.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 90319[95:Res:90315.0,61.1] always3(s32) || -> . % 76.04/76.29 90320[95:SSi:90319.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.29 90321[93:Spt:90320.0,89914.0,89915.0] || until2p7(s31)*+ -> . % 76.04/76.29 90322[93:Spt:90320.0,89914.1] || -> node4(s30)*. % 76.04/76.29 90324[93:MRR:828.0,90322.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.29 90327[93:Res:53.1,90324.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.29 90329[94:Spt:90327.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 90331[94:Res:90329.0,61.1] always3(s30) || -> . % 76.04/76.29 90332[94:SSi:90331.0,78200.0,78204.0,78608.0,89913.0,90322.0] || -> . % 76.04/76.29 90333[94:Spt:90332.0,90327.0,90329.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.29 90334[94:Spt:90332.0,90327.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 90338[94:Res:90334.0,61.1] always3(s31) || -> . % 76.04/76.29 90339[94:SSi:90338.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.29 90340[92:Spt:90339.0,89912.0,89913.0] || until2p7(s30)*+ -> . % 76.04/76.29 90341[92:Spt:90339.0,89912.1] || -> node4(s29)*. % 76.04/76.29 90343[92:MRR:831.0,90341.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.29 90346[92:Res:53.1,90343.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.29 90348[93:Spt:90346.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 90350[93:Res:90348.0,61.1] always3(s29) || -> . % 76.04/76.29 90351[93:SSi:90350.0,78196.0,78199.0,78607.0,89911.0,90341.0] || -> . % 76.04/76.29 90352[93:Spt:90351.0,90346.0,90348.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.29 90353[93:Spt:90351.0,90346.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 90357[93:Res:90353.0,61.1] always3(s30) || -> . % 76.04/76.29 90358[93:SSi:90357.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.29 90359[91:Spt:90358.0,89910.0,89911.0] || until2p7(s29)*+ -> . % 76.04/76.29 90360[91:Spt:90358.0,89910.1] || -> node4(s28)*. % 76.04/76.29 90362[91:MRR:834.0,90360.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.29 90365[91:Res:53.1,90362.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.29 90367[92:Spt:90365.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 90369[92:Res:90367.0,61.1] always3(s28) || -> . % 76.04/76.29 90370[92:SSi:90369.0,78191.0,78195.0,78606.0,89909.0,90360.0] || -> . % 76.04/76.29 90371[92:Spt:90370.0,90365.0,90367.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.29 90372[92:Spt:90370.0,90365.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 90376[92:Res:90372.0,61.1] always3(s29) || -> . % 76.04/76.29 90377[92:SSi:90376.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.29 90378[90:Spt:90377.0,89908.0,89909.0] || until2p7(s28)*+ -> . % 76.04/76.29 90379[90:Spt:90377.0,89908.1] || -> node4(s27)*. % 76.04/76.29 90381[90:MRR:837.0,90379.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.29 90384[90:Res:53.1,90381.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.29 90389[91:Spt:90384.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 90391[91:Res:90389.0,61.1] always3(s27) || -> . % 76.04/76.29 90392[91:SSi:90391.0,78187.0,78190.0,78605.0,89907.0,90379.0] || -> . % 76.04/76.29 90393[91:Spt:90392.0,90384.0,90389.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.29 90394[91:Spt:90392.0,90384.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 90398[91:Res:90394.0,61.1] always3(s28) || -> . % 76.04/76.29 90399[91:SSi:90398.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.29 90400[89:Spt:90399.0,89906.0,89907.0] || until2p7(s27)*+ -> . % 76.04/76.29 90401[89:Spt:90399.0,89906.1] || -> node4(s26)*. % 76.04/76.29 90403[89:MRR:840.0,90401.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.29 90406[89:Res:53.1,90403.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.29 90408[90:Spt:90406.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 90410[90:Res:90408.0,61.1] always3(s26) || -> . % 76.04/76.29 90411[90:SSi:90410.0,78182.0,78186.0,78604.0,89905.0,90401.0] || -> . % 76.04/76.29 90412[90:Spt:90411.0,90406.0,90408.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.29 90413[90:Spt:90411.0,90406.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 90417[90:Res:90413.0,61.1] always3(s27) || -> . % 76.04/76.29 90418[90:SSi:90417.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.29 90419[88:Spt:90418.0,89904.0,89905.0] || until2p7(s26)*+ -> . % 76.04/76.29 90420[88:Spt:90418.0,89904.1] || -> node4(s25)*. % 76.04/76.29 90422[88:MRR:843.0,90420.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.29 90425[88:Res:53.1,90422.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.29 90427[89:Spt:90425.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 90429[89:Res:90427.0,61.1] always3(s25) || -> . % 76.04/76.29 90430[89:SSi:90429.0,78178.0,78181.0,78603.0,89903.0,90420.0] || -> . % 76.04/76.29 90431[89:Spt:90430.0,90425.0,90427.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.29 90432[89:Spt:90430.0,90425.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 90436[89:Res:90432.0,61.1] always3(s26) || -> . % 76.04/76.29 90437[89:SSi:90436.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.29 90438[87:Spt:90437.0,89902.0,89903.0] || until2p7(s25)*+ -> . % 76.04/76.29 90439[87:Spt:90437.0,89902.1] || -> node4(s24)*. % 76.04/76.29 90441[87:MRR:846.0,90439.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.29 90444[87:Res:53.1,90441.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.29 90446[88:Spt:90444.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 90448[88:Res:90446.0,61.1] always3(s24) || -> . % 76.04/76.29 90449[88:SSi:90448.0,78173.0,78177.0,78602.0,89901.0,90439.0] || -> . % 76.04/76.29 90450[88:Spt:90449.0,90444.0,90446.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.29 90451[88:Spt:90449.0,90444.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 90455[88:Res:90451.0,61.1] always3(s25) || -> . % 76.04/76.29 90456[88:SSi:90455.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.29 90457[86:Spt:90456.0,89900.0,89901.0] || until2p7(s24)*+ -> . % 76.04/76.29 90458[86:Spt:90456.0,89900.1] || -> node4(s23)*. % 76.04/76.29 90460[86:MRR:849.0,90458.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.29 90463[86:Res:53.1,90460.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.29 90468[87:Spt:90463.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 90470[87:Res:90468.0,61.1] always3(s23) || -> . % 76.04/76.29 90471[87:SSi:90470.0,78169.0,78172.0,78601.0,89899.0,90458.0] || -> . % 76.04/76.29 90472[87:Spt:90471.0,90463.0,90468.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.29 90473[87:Spt:90471.0,90463.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 90477[87:Res:90473.0,61.1] always3(s24) || -> . % 76.04/76.29 90478[87:SSi:90477.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.29 90479[85:Spt:90478.0,89898.0,89899.0] || until2p7(s23)*+ -> . % 76.04/76.29 90480[85:Spt:90478.0,89898.1] || -> node4(s22)*. % 76.04/76.29 90482[85:MRR:852.0,90480.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.29 90485[85:Res:53.1,90482.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.29 90487[86:Spt:90485.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 90489[86:Res:90487.0,61.1] always3(s22) || -> . % 76.04/76.29 90490[86:SSi:90489.0,78164.0,78168.0,78600.0,89897.0,90480.0] || -> . % 76.04/76.29 90491[86:Spt:90490.0,90485.0,90487.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.29 90492[86:Spt:90490.0,90485.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 90496[86:Res:90492.0,61.1] always3(s23) || -> . % 76.04/76.29 90497[86:SSi:90496.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.29 90498[84:Spt:90497.0,89896.0,89897.0] || until2p7(s22)*+ -> . % 76.04/76.29 90499[84:Spt:90497.0,89896.1] || -> node4(s21)*. % 76.04/76.29 90501[84:MRR:855.0,90499.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.29 90504[84:Res:53.1,90501.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.29 90506[85:Spt:90504.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 90508[85:Res:90506.0,61.1] always3(s21) || -> . % 76.04/76.29 90509[85:SSi:90508.0,78160.0,78163.0,78599.0,89895.0,90499.0] || -> . % 76.04/76.29 90510[85:Spt:90509.0,90504.0,90506.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.29 90511[85:Spt:90509.0,90504.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 90515[85:Res:90511.0,61.1] always3(s22) || -> . % 76.04/76.29 90516[85:SSi:90515.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.29 90517[83:Spt:90516.0,89894.0,89895.0] || until2p7(s21)*+ -> . % 76.04/76.29 90518[83:Spt:90516.0,89894.1] || -> node4(s20)*. % 76.04/76.29 90520[83:MRR:858.0,90518.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.29 90523[83:Res:53.1,90520.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.29 90525[83:MRR:90523.0,89884.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 90527[83:Res:90525.0,61.1] always3(s21) || -> . % 76.04/76.29 90528[83:SSi:90527.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.29 90529[81:Spt:90528.0,89770.0,89773.0] || trans(s49,s20)*+ -> . % 76.04/76.29 90530[81:Spt:90528.0,89770.1,89770.2,89770.3,89770.4,89770.5,89770.6,89770.7,89770.8,89770.9,89770.10,89770.11,89770.12,89770.13,89770.14,89770.15,89770.16,89770.17,89770.18] || -> trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.29 90532[81:MRR:89772.1,90529.0] xuntil6(s49) || -> trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.29 90533[82:Spt:90530.0] || -> trans(s49,s19)*. % 76.04/76.29 90534[82:Res:90533.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s19)*. % 76.04/76.29 90536[82:Res:90533.0,60.0] || -> node2(s49,s19)*. % 76.04/76.29 90537[82:SSi:90534.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s19)*. % 76.04/76.29 90538[82:Res:90536.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 90640[82:SoR:90538.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 90642[82:SoR:90640.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)* xuntil6(s49). % 76.04/76.29 90643[82:SSi:90642.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s19,c_busy)* xuntil6(s49). % 76.04/76.29 90644[83:Spt:90643.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 90646[83:Res:90644.0,61.1] always3(s19) || -> . % 76.04/76.29 90647[83:SSi:90646.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.29 90648[83:Spt:90647.0,90643.1,90644.0] || m_main_v_state(s19,c_busy)*+ -> . % 76.04/76.29 90649[83:Spt:90647.0,90643.0,90643.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.29 90653[83:MRR:90640.2,90648.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.29 90654[83:Res:53.1,90649.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.29 90656[83:MRR:90654.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.29 90657[83:MRR:90537.0,90656.0] || -> until2p7(s19)*. % 76.04/76.29 90658[83:MRR:215.0,90657.0] || -> until2p7(s20)* node4(s19). % 76.04/76.29 90659[84:Spt:90658.0] || -> until2p7(s20)*. % 76.04/76.29 90660[84:MRR:216.0,90659.0] || -> until2p7(s21)* node4(s20). % 76.04/76.29 90661[85:Spt:90660.0] || -> until2p7(s21)*. % 76.04/76.29 90662[85:MRR:217.0,90661.0] || -> until2p7(s22)* node4(s21). % 76.04/76.29 90663[86:Spt:90662.0] || -> until2p7(s22)*. % 76.04/76.29 90664[86:MRR:218.0,90663.0] || -> until2p7(s23)* node4(s22). % 76.04/76.29 90665[87:Spt:90664.0] || -> until2p7(s23)*. % 76.04/76.29 90666[87:MRR:219.0,90665.0] || -> until2p7(s24)* node4(s23). % 76.04/76.29 90667[88:Spt:90666.0] || -> until2p7(s24)*. % 76.04/76.29 90668[88:MRR:220.0,90667.0] || -> until2p7(s25)* node4(s24). % 76.04/76.29 90669[89:Spt:90668.0] || -> until2p7(s25)*. % 76.04/76.29 90670[89:MRR:221.0,90669.0] || -> until2p7(s26)* node4(s25). % 76.04/76.29 90671[90:Spt:90670.0] || -> until2p7(s26)*. % 76.04/76.29 90672[90:MRR:222.0,90671.0] || -> until2p7(s27)* node4(s26). % 76.04/76.29 90673[91:Spt:90672.0] || -> until2p7(s27)*. % 76.04/76.29 90674[91:MRR:223.0,90673.0] || -> until2p7(s28)* node4(s27). % 76.04/76.29 90675[92:Spt:90674.0] || -> until2p7(s28)*. % 76.04/76.29 90676[92:MRR:224.0,90675.0] || -> until2p7(s29)* node4(s28). % 76.04/76.29 90677[93:Spt:90676.0] || -> until2p7(s29)*. % 76.04/76.29 90678[93:MRR:225.0,90677.0] || -> until2p7(s30)* node4(s29). % 76.04/76.29 90679[94:Spt:90678.0] || -> until2p7(s30)*. % 76.04/76.29 90680[94:MRR:226.0,90679.0] || -> until2p7(s31)* node4(s30). % 76.04/76.29 90681[95:Spt:90680.0] || -> until2p7(s31)*. % 76.04/76.29 90682[95:MRR:227.0,90681.0] || -> until2p7(s32)* node4(s31). % 76.04/76.29 90683[96:Spt:90682.0] || -> until2p7(s32)*. % 76.04/76.29 90684[96:MRR:228.0,90683.0] || -> until2p7(s33)* node4(s32). % 76.04/76.29 90685[97:Spt:90684.0] || -> until2p7(s33)*. % 76.04/76.29 90686[97:MRR:229.0,90685.0] || -> until2p7(s34)* node4(s33). % 76.04/76.29 90687[98:Spt:90686.0] || -> until2p7(s34)*. % 76.04/76.29 90688[98:MRR:230.0,90687.0] || -> until2p7(s35)* node4(s34). % 76.04/76.29 90689[99:Spt:90688.0] || -> until2p7(s35)*. % 76.04/76.29 90690[99:MRR:231.0,90689.0] || -> until2p7(s36)* node4(s35). % 76.04/76.29 90691[100:Spt:90690.0] || -> until2p7(s36)*. % 76.04/76.29 90692[100:MRR:232.0,90691.0] || -> until2p7(s37)* node4(s36). % 76.04/76.29 90693[101:Spt:90692.0] || -> until2p7(s37)*. % 76.04/76.29 90694[101:MRR:235.0,90693.0] || -> until2p7(s38)* node4(s37). % 76.04/76.29 90695[102:Spt:90694.0] || -> until2p7(s38)*. % 76.04/76.29 90696[102:MRR:236.0,90695.0] || -> until2p7(s39)* node4(s38). % 76.04/76.29 90697[103:Spt:90696.0] || -> until2p7(s39)*. % 76.04/76.29 90698[103:MRR:237.0,90697.0] || -> until2p7(s40)* node4(s39). % 76.04/76.29 90699[104:Spt:90698.0] || -> until2p7(s40)*. % 76.04/76.29 90700[104:MRR:238.0,90699.0] || -> until2p7(s41)* node4(s40). % 76.04/76.29 90701[105:Spt:90700.0] || -> until2p7(s41)*. % 76.04/76.29 90702[105:MRR:239.0,90701.0] || -> until2p7(s42)* node4(s41). % 76.04/76.29 90703[106:Spt:90702.0] || -> until2p7(s42)*. % 76.04/76.29 90704[106:MRR:240.0,90703.0] || -> until2p7(s43)* node4(s42). % 76.04/76.29 90705[107:Spt:90704.0] || -> until2p7(s43)*. % 76.04/76.29 90706[107:MRR:241.0,90705.0] || -> until2p7(s44)* node4(s43). % 76.04/76.29 90707[108:Spt:90706.0] || -> until2p7(s44)*. % 76.04/76.29 90708[108:MRR:539.0,90707.0] || -> until2p7(s45)* node4(s44). % 76.04/76.29 90709[109:Spt:90708.0] || -> until2p7(s45)*. % 76.04/76.29 90710[109:MRR:544.0,90709.0] || -> until2p7(s46)* node4(s45). % 76.04/76.29 90711[110:Spt:90710.0] || -> until2p7(s46)*. % 76.04/76.29 90712[110:MRR:549.0,90711.0] || -> until2p7(s47)* node4(s46). % 76.04/76.29 90713[111:Spt:90712.0] || -> until2p7(s47)*. % 76.04/76.29 90714[111:MRR:554.0,90713.0] || -> until2p7(s48)* node4(s47). % 76.04/76.29 90715[112:Spt:90714.0] || -> until2p7(s48)*. % 76.04/76.29 90716[112:MRR:559.0,90715.0] || -> until2p7(s49)* node4(s48). % 76.04/76.29 90717[113:Spt:90716.0] || -> until2p7(s49)*. % 76.04/76.29 90718[113:MRR:194.0,90717.0] || -> node4(s49)*. % 76.04/76.29 90719[113:MRR:90653.0,90718.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.29 90720[113:Res:53.1,90719.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.29 90722[113:MRR:90720.0,78381.0] || -> . % 76.04/76.29 90723[113:Spt:90722.0,90716.0,90717.0] || until2p7(s49)*+ -> . % 76.04/76.29 90724[113:Spt:90722.0,90716.1] || -> node4(s48)*. % 76.04/76.29 90725[113:MRR:78384.0,90724.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.29 90728[113:Res:53.1,90725.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 90731[113:Res:90728.0,61.1] always3(s48) || -> . % 76.04/76.29 90732[113:SSi:90731.0,78281.0,78387.0,78626.0,90715.0,90724.0] || -> . % 76.04/76.29 90733[112:Spt:90732.0,90714.0,90715.0] || until2p7(s48)*+ -> . % 76.04/76.29 90734[112:Spt:90732.0,90714.1] || -> node4(s47)*. % 76.04/76.29 90736[112:MRR:777.0,90734.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.29 90751[112:Res:53.1,90736.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.29 90753[113:Spt:90751.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 90755[113:Res:90753.0,61.1] always3(s47) || -> . % 76.04/76.29 90756[113:SSi:90755.0,78277.0,78280.0,78625.0,90713.0,90734.0] || -> . % 76.04/76.29 90757[113:Spt:90756.0,90751.0,90753.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.29 90758[113:Spt:90756.0,90751.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 90762[113:Res:90758.0,61.1] always3(s48) || -> . % 76.04/76.29 90763[113:SSi:90762.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.29 90764[111:Spt:90763.0,90712.0,90713.0] || until2p7(s47)*+ -> . % 76.04/76.29 90765[111:Spt:90763.0,90712.1] || -> node4(s46)*. % 76.04/76.29 90767[111:MRR:780.0,90765.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.29 90777[111:Res:53.1,90767.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.29 90779[112:Spt:90777.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 90781[112:Res:90779.0,61.1] always3(s46) || -> . % 76.04/76.29 90782[112:SSi:90781.0,78272.0,78276.0,78624.0,90711.0,90765.0] || -> . % 76.04/76.29 90783[112:Spt:90782.0,90777.0,90779.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.29 90784[112:Spt:90782.0,90777.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 90788[112:Res:90784.0,61.1] always3(s47) || -> . % 76.04/76.29 90789[112:SSi:90788.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.29 90790[110:Spt:90789.0,90710.0,90711.0] || until2p7(s46)*+ -> . % 76.04/76.29 90791[110:Spt:90789.0,90710.1] || -> node4(s45)*. % 76.04/76.29 90793[110:MRR:783.0,90791.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.29 90796[110:Res:53.1,90793.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.29 90798[111:Spt:90796.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 90800[111:Res:90798.0,61.1] always3(s45) || -> . % 76.04/76.29 90801[111:SSi:90800.0,78268.0,78271.0,78623.0,90709.0,90791.0] || -> . % 76.04/76.29 90802[111:Spt:90801.0,90796.0,90798.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.29 90803[111:Spt:90801.0,90796.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 90807[111:Res:90803.0,61.1] always3(s46) || -> . % 76.04/76.29 90808[111:SSi:90807.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.29 90809[109:Spt:90808.0,90708.0,90709.0] || until2p7(s45)*+ -> . % 76.04/76.29 90810[109:Spt:90808.0,90708.1] || -> node4(s44)*. % 76.04/76.29 90812[109:MRR:786.0,90810.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.29 90815[109:Res:53.1,90812.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.29 90817[110:Spt:90815.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 90819[110:Res:90817.0,61.1] always3(s44) || -> . % 76.04/76.29 90820[110:SSi:90819.0,78263.0,78267.0,78622.0,90707.0,90810.0] || -> . % 76.04/76.29 90821[110:Spt:90820.0,90815.0,90817.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.29 90822[110:Spt:90820.0,90815.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 90826[110:Res:90822.0,61.1] always3(s45) || -> . % 76.04/76.29 90827[110:SSi:90826.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.29 90828[108:Spt:90827.0,90706.0,90707.0] || until2p7(s44)*+ -> . % 76.04/76.29 90829[108:Spt:90827.0,90706.1] || -> node4(s43)*. % 76.04/76.29 90831[108:MRR:789.0,90829.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.29 90834[108:Res:53.1,90831.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.29 90839[109:Spt:90834.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 90841[109:Res:90839.0,61.1] always3(s43) || -> . % 76.04/76.29 90842[109:SSi:90841.0,78259.0,78262.0,78621.0,90705.0,90829.0] || -> . % 76.04/76.29 90843[109:Spt:90842.0,90834.0,90839.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.29 90844[109:Spt:90842.0,90834.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 90848[109:Res:90844.0,61.1] always3(s44) || -> . % 76.04/76.29 90849[109:SSi:90848.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.29 90850[107:Spt:90849.0,90704.0,90705.0] || until2p7(s43)*+ -> . % 76.04/76.29 90851[107:Spt:90849.0,90704.1] || -> node4(s42)*. % 76.04/76.29 90853[107:MRR:792.0,90851.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.29 90856[107:Res:53.1,90853.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.29 90858[108:Spt:90856.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 90860[108:Res:90858.0,61.1] always3(s42) || -> . % 76.04/76.29 90861[108:SSi:90860.0,78254.0,78258.0,78620.0,90703.0,90851.0] || -> . % 76.04/76.29 90862[108:Spt:90861.0,90856.0,90858.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.29 90863[108:Spt:90861.0,90856.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 90867[108:Res:90863.0,61.1] always3(s43) || -> . % 76.04/76.29 90868[108:SSi:90867.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.29 90869[106:Spt:90868.0,90702.0,90703.0] || until2p7(s42)*+ -> . % 76.04/76.29 90870[106:Spt:90868.0,90702.1] || -> node4(s41)*. % 76.04/76.29 90872[106:MRR:795.0,90870.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.29 90875[106:Res:53.1,90872.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.29 90877[107:Spt:90875.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 90879[107:Res:90877.0,61.1] always3(s41) || -> . % 76.04/76.29 90880[107:SSi:90879.0,78250.0,78253.0,78619.0,90701.0,90870.0] || -> . % 76.04/76.29 90881[107:Spt:90880.0,90875.0,90877.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.29 90882[107:Spt:90880.0,90875.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 90886[107:Res:90882.0,61.1] always3(s42) || -> . % 76.04/76.29 90887[107:SSi:90886.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.29 90888[105:Spt:90887.0,90700.0,90701.0] || until2p7(s41)*+ -> . % 76.04/76.29 90889[105:Spt:90887.0,90700.1] || -> node4(s40)*. % 76.04/76.29 90891[105:MRR:798.0,90889.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.29 90894[105:Res:53.1,90891.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.29 90896[106:Spt:90894.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 90898[106:Res:90896.0,61.1] always3(s40) || -> . % 76.04/76.29 90899[106:SSi:90898.0,78245.0,78249.0,78618.0,90699.0,90889.0] || -> . % 76.04/76.29 90900[106:Spt:90899.0,90894.0,90896.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.29 90901[106:Spt:90899.0,90894.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 90905[106:Res:90901.0,61.1] always3(s41) || -> . % 76.04/76.29 90906[106:SSi:90905.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.29 90907[104:Spt:90906.0,90698.0,90699.0] || until2p7(s40)*+ -> . % 76.04/76.29 90908[104:Spt:90906.0,90698.1] || -> node4(s39)*. % 76.04/76.29 90910[104:MRR:801.0,90908.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.29 90913[104:Res:53.1,90910.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.29 90918[105:Spt:90913.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 90920[105:Res:90918.0,61.1] always3(s39) || -> . % 76.04/76.29 90921[105:SSi:90920.0,78241.0,78244.0,78617.0,90697.0,90908.0] || -> . % 76.04/76.29 90922[105:Spt:90921.0,90913.0,90918.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.29 90923[105:Spt:90921.0,90913.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 90927[105:Res:90923.0,61.1] always3(s40) || -> . % 76.04/76.29 90928[105:SSi:90927.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.29 90929[103:Spt:90928.0,90696.0,90697.0] || until2p7(s39)*+ -> . % 76.04/76.29 90930[103:Spt:90928.0,90696.1] || -> node4(s38)*. % 76.04/76.29 90932[103:MRR:804.0,90930.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.29 90935[103:Res:53.1,90932.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.29 90937[104:Spt:90935.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 90939[104:Res:90937.0,61.1] always3(s38) || -> . % 76.04/76.29 90940[104:SSi:90939.0,78236.0,78240.0,78616.0,90695.0,90930.0] || -> . % 76.04/76.29 90941[104:Spt:90940.0,90935.0,90937.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.29 90942[104:Spt:90940.0,90935.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 90946[104:Res:90942.0,61.1] always3(s39) || -> . % 76.04/76.29 90947[104:SSi:90946.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.29 90948[102:Spt:90947.0,90694.0,90695.0] || until2p7(s38)*+ -> . % 76.04/76.29 90949[102:Spt:90947.0,90694.1] || -> node4(s37)*. % 76.04/76.29 90951[102:MRR:807.0,90949.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.29 90954[102:Res:53.1,90951.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.29 90956[103:Spt:90954.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 90958[103:Res:90956.0,61.1] always3(s37) || -> . % 76.04/76.29 90959[103:SSi:90958.0,78232.0,78235.0,78615.0,90693.0,90949.0] || -> . % 76.04/76.29 90960[103:Spt:90959.0,90954.0,90956.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.29 90961[103:Spt:90959.0,90954.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 90965[103:Res:90961.0,61.1] always3(s38) || -> . % 76.04/76.29 90966[103:SSi:90965.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.29 90967[101:Spt:90966.0,90692.0,90693.0] || until2p7(s37)*+ -> . % 76.04/76.29 90968[101:Spt:90966.0,90692.1] || -> node4(s36)*. % 76.04/76.29 90970[101:MRR:810.0,90968.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.29 90973[101:Res:53.1,90970.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.29 90975[102:Spt:90973.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 90977[102:Res:90975.0,61.1] always3(s36) || -> . % 76.04/76.29 90978[102:SSi:90977.0,78227.0,78231.0,78614.0,90691.0,90968.0] || -> . % 76.04/76.29 90979[102:Spt:90978.0,90973.0,90975.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.29 90980[102:Spt:90978.0,90973.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 90984[102:Res:90980.0,61.1] always3(s37) || -> . % 76.04/76.29 90985[102:SSi:90984.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.29 90986[100:Spt:90985.0,90690.0,90691.0] || until2p7(s36)*+ -> . % 76.04/76.29 90987[100:Spt:90985.0,90690.1] || -> node4(s35)*. % 76.04/76.29 90989[100:MRR:813.0,90987.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.29 90992[100:Res:53.1,90989.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.29 90997[101:Spt:90992.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 90999[101:Res:90997.0,61.1] always3(s35) || -> . % 76.04/76.29 91000[101:SSi:90999.0,78223.0,78226.0,78613.0,90689.0,90987.0] || -> . % 76.04/76.29 91001[101:Spt:91000.0,90992.0,90997.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.29 91002[101:Spt:91000.0,90992.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 91006[101:Res:91002.0,61.1] always3(s36) || -> . % 76.04/76.29 91007[101:SSi:91006.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.29 91008[99:Spt:91007.0,90688.0,90689.0] || until2p7(s35)*+ -> . % 76.04/76.29 91009[99:Spt:91007.0,90688.1] || -> node4(s34)*. % 76.04/76.29 91011[99:MRR:816.0,91009.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.29 91014[99:Res:53.1,91011.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.29 91016[100:Spt:91014.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 91018[100:Res:91016.0,61.1] always3(s34) || -> . % 76.04/76.29 91019[100:SSi:91018.0,78218.0,78222.0,78612.0,90687.0,91009.0] || -> . % 76.04/76.29 91020[100:Spt:91019.0,91014.0,91016.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.29 91021[100:Spt:91019.0,91014.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 91025[100:Res:91021.0,61.1] always3(s35) || -> . % 76.04/76.29 91026[100:SSi:91025.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.29 91027[98:Spt:91026.0,90686.0,90687.0] || until2p7(s34)*+ -> . % 76.04/76.29 91028[98:Spt:91026.0,90686.1] || -> node4(s33)*. % 76.04/76.29 91030[98:MRR:819.0,91028.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.29 91033[98:Res:53.1,91030.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.29 91035[99:Spt:91033.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 91037[99:Res:91035.0,61.1] always3(s33) || -> . % 76.04/76.29 91038[99:SSi:91037.0,78214.0,78217.0,78611.0,90685.0,91028.0] || -> . % 76.04/76.29 91039[99:Spt:91038.0,91033.0,91035.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.29 91040[99:Spt:91038.0,91033.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 91044[99:Res:91040.0,61.1] always3(s34) || -> . % 76.04/76.29 91045[99:SSi:91044.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.29 91046[97:Spt:91045.0,90684.0,90685.0] || until2p7(s33)*+ -> . % 76.04/76.29 91047[97:Spt:91045.0,90684.1] || -> node4(s32)*. % 76.04/76.29 91049[97:MRR:822.0,91047.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.29 91052[97:Res:53.1,91049.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.29 91054[98:Spt:91052.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 91056[98:Res:91054.0,61.1] always3(s32) || -> . % 76.04/76.29 91057[98:SSi:91056.0,78209.0,78213.0,78610.0,90683.0,91047.0] || -> . % 76.04/76.29 91058[98:Spt:91057.0,91052.0,91054.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.29 91059[98:Spt:91057.0,91052.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 91063[98:Res:91059.0,61.1] always3(s33) || -> . % 76.04/76.29 91064[98:SSi:91063.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.29 91065[96:Spt:91064.0,90682.0,90683.0] || until2p7(s32)*+ -> . % 76.04/76.29 91066[96:Spt:91064.0,90682.1] || -> node4(s31)*. % 76.04/76.29 91068[96:MRR:825.0,91066.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.29 91071[96:Res:53.1,91068.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.29 91076[97:Spt:91071.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 91078[97:Res:91076.0,61.1] always3(s31) || -> . % 76.04/76.29 91079[97:SSi:91078.0,78205.0,78208.0,78609.0,90681.0,91066.0] || -> . % 76.04/76.29 91080[97:Spt:91079.0,91071.0,91076.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.29 91081[97:Spt:91079.0,91071.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 91085[97:Res:91081.0,61.1] always3(s32) || -> . % 76.04/76.29 91086[97:SSi:91085.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.29 91087[95:Spt:91086.0,90680.0,90681.0] || until2p7(s31)*+ -> . % 76.04/76.29 91088[95:Spt:91086.0,90680.1] || -> node4(s30)*. % 76.04/76.29 91090[95:MRR:828.0,91088.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.29 91093[95:Res:53.1,91090.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.29 91095[96:Spt:91093.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 91097[96:Res:91095.0,61.1] always3(s30) || -> . % 76.04/76.29 91098[96:SSi:91097.0,78200.0,78204.0,78608.0,90679.0,91088.0] || -> . % 76.04/76.29 91099[96:Spt:91098.0,91093.0,91095.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.29 91100[96:Spt:91098.0,91093.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 91104[96:Res:91100.0,61.1] always3(s31) || -> . % 76.04/76.29 91105[96:SSi:91104.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.29 91106[94:Spt:91105.0,90678.0,90679.0] || until2p7(s30)*+ -> . % 76.04/76.29 91107[94:Spt:91105.0,90678.1] || -> node4(s29)*. % 76.04/76.29 91109[94:MRR:831.0,91107.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.29 91112[94:Res:53.1,91109.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.29 91114[95:Spt:91112.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 91116[95:Res:91114.0,61.1] always3(s29) || -> . % 76.04/76.29 91117[95:SSi:91116.0,78196.0,78199.0,78607.0,90677.0,91107.0] || -> . % 76.04/76.29 91118[95:Spt:91117.0,91112.0,91114.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.29 91119[95:Spt:91117.0,91112.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 91123[95:Res:91119.0,61.1] always3(s30) || -> . % 76.04/76.29 91124[95:SSi:91123.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.29 91125[93:Spt:91124.0,90676.0,90677.0] || until2p7(s29)*+ -> . % 76.04/76.29 91126[93:Spt:91124.0,90676.1] || -> node4(s28)*. % 76.04/76.29 91128[93:MRR:834.0,91126.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.29 91131[93:Res:53.1,91128.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.29 91133[94:Spt:91131.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 91135[94:Res:91133.0,61.1] always3(s28) || -> . % 76.04/76.29 91136[94:SSi:91135.0,78191.0,78195.0,78606.0,90675.0,91126.0] || -> . % 76.04/76.29 91137[94:Spt:91136.0,91131.0,91133.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.29 91138[94:Spt:91136.0,91131.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 91142[94:Res:91138.0,61.1] always3(s29) || -> . % 76.04/76.29 91143[94:SSi:91142.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.29 91144[92:Spt:91143.0,90674.0,90675.0] || until2p7(s28)*+ -> . % 76.04/76.29 91145[92:Spt:91143.0,90674.1] || -> node4(s27)*. % 76.04/76.29 91147[92:MRR:837.0,91145.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.29 91150[92:Res:53.1,91147.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.29 91155[93:Spt:91150.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 91157[93:Res:91155.0,61.1] always3(s27) || -> . % 76.04/76.29 91158[93:SSi:91157.0,78187.0,78190.0,78605.0,90673.0,91145.0] || -> . % 76.04/76.29 91159[93:Spt:91158.0,91150.0,91155.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.29 91160[93:Spt:91158.0,91150.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 91164[93:Res:91160.0,61.1] always3(s28) || -> . % 76.04/76.29 91165[93:SSi:91164.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.29 91166[91:Spt:91165.0,90672.0,90673.0] || until2p7(s27)*+ -> . % 76.04/76.29 91167[91:Spt:91165.0,90672.1] || -> node4(s26)*. % 76.04/76.29 91169[91:MRR:840.0,91167.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.29 91172[91:Res:53.1,91169.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.29 91174[92:Spt:91172.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 91176[92:Res:91174.0,61.1] always3(s26) || -> . % 76.04/76.29 91177[92:SSi:91176.0,78182.0,78186.0,78604.0,90671.0,91167.0] || -> . % 76.04/76.29 91178[92:Spt:91177.0,91172.0,91174.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.29 91179[92:Spt:91177.0,91172.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 91183[92:Res:91179.0,61.1] always3(s27) || -> . % 76.04/76.29 91184[92:SSi:91183.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.29 91185[90:Spt:91184.0,90670.0,90671.0] || until2p7(s26)*+ -> . % 76.04/76.29 91186[90:Spt:91184.0,90670.1] || -> node4(s25)*. % 76.04/76.29 91188[90:MRR:843.0,91186.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.29 91191[90:Res:53.1,91188.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.29 91193[91:Spt:91191.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 91195[91:Res:91193.0,61.1] always3(s25) || -> . % 76.04/76.29 91196[91:SSi:91195.0,78178.0,78181.0,78603.0,90669.0,91186.0] || -> . % 76.04/76.29 91197[91:Spt:91196.0,91191.0,91193.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.29 91198[91:Spt:91196.0,91191.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 91202[91:Res:91198.0,61.1] always3(s26) || -> . % 76.04/76.29 91203[91:SSi:91202.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.29 91204[89:Spt:91203.0,90668.0,90669.0] || until2p7(s25)*+ -> . % 76.04/76.29 91205[89:Spt:91203.0,90668.1] || -> node4(s24)*. % 76.04/76.29 91207[89:MRR:846.0,91205.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.29 91210[89:Res:53.1,91207.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.29 91212[90:Spt:91210.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 91214[90:Res:91212.0,61.1] always3(s24) || -> . % 76.04/76.29 91215[90:SSi:91214.0,78173.0,78177.0,78602.0,90667.0,91205.0] || -> . % 76.04/76.29 91216[90:Spt:91215.0,91210.0,91212.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.29 91217[90:Spt:91215.0,91210.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 91221[90:Res:91217.0,61.1] always3(s25) || -> . % 76.04/76.29 91222[90:SSi:91221.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.29 91223[88:Spt:91222.0,90666.0,90667.0] || until2p7(s24)*+ -> . % 76.04/76.29 91224[88:Spt:91222.0,90666.1] || -> node4(s23)*. % 76.04/76.29 91226[88:MRR:849.0,91224.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.29 91229[88:Res:53.1,91226.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.29 91234[89:Spt:91229.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 91236[89:Res:91234.0,61.1] always3(s23) || -> . % 76.04/76.29 91237[89:SSi:91236.0,78169.0,78172.0,78601.0,90665.0,91224.0] || -> . % 76.04/76.29 91238[89:Spt:91237.0,91229.0,91234.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.29 91239[89:Spt:91237.0,91229.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 91243[89:Res:91239.0,61.1] always3(s24) || -> . % 76.04/76.29 91244[89:SSi:91243.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.29 91245[87:Spt:91244.0,90664.0,90665.0] || until2p7(s23)*+ -> . % 76.04/76.29 91246[87:Spt:91244.0,90664.1] || -> node4(s22)*. % 76.04/76.29 91248[87:MRR:852.0,91246.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.29 91251[87:Res:53.1,91248.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.29 91253[88:Spt:91251.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 91255[88:Res:91253.0,61.1] always3(s22) || -> . % 76.04/76.29 91256[88:SSi:91255.0,78164.0,78168.0,78600.0,90663.0,91246.0] || -> . % 76.04/76.29 91257[88:Spt:91256.0,91251.0,91253.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.29 91258[88:Spt:91256.0,91251.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 91262[88:Res:91258.0,61.1] always3(s23) || -> . % 76.04/76.29 91263[88:SSi:91262.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.29 91264[86:Spt:91263.0,90662.0,90663.0] || until2p7(s22)*+ -> . % 76.04/76.29 91265[86:Spt:91263.0,90662.1] || -> node4(s21)*. % 76.04/76.29 91267[86:MRR:855.0,91265.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.29 91270[86:Res:53.1,91267.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.29 91272[87:Spt:91270.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 91274[87:Res:91272.0,61.1] always3(s21) || -> . % 76.04/76.29 91275[87:SSi:91274.0,78160.0,78163.0,78599.0,90661.0,91265.0] || -> . % 76.04/76.29 91276[87:Spt:91275.0,91270.0,91272.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.29 91277[87:Spt:91275.0,91270.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 91281[87:Res:91277.0,61.1] always3(s22) || -> . % 76.04/76.29 91282[87:SSi:91281.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.29 91283[85:Spt:91282.0,90660.0,90661.0] || until2p7(s21)*+ -> . % 76.04/76.29 91284[85:Spt:91282.0,90660.1] || -> node4(s20)*. % 76.04/76.29 91286[85:MRR:858.0,91284.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.29 91289[85:Res:53.1,91286.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.29 91291[86:Spt:91289.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 91293[86:Res:91291.0,61.1] always3(s20) || -> . % 76.04/76.29 91294[86:SSi:91293.0,78155.0,78159.0,78598.0,90659.0,91284.0] || -> . % 76.04/76.29 91295[86:Spt:91294.0,91289.0,91291.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.29 91296[86:Spt:91294.0,91289.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 91300[86:Res:91296.0,61.1] always3(s21) || -> . % 76.04/76.29 91301[86:SSi:91300.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.29 91302[84:Spt:91301.0,90658.0,90659.0] || until2p7(s20)*+ -> . % 76.04/76.29 91303[84:Spt:91301.0,90658.1] || -> node4(s19)*. % 76.04/76.29 91305[84:MRR:861.0,91303.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.29 91308[84:Res:53.1,91305.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.29 91310[84:MRR:91308.0,90648.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 91315[84:Res:91310.0,61.1] always3(s20) || -> . % 76.04/76.29 91316[84:SSi:91315.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.29 91317[82:Spt:91316.0,90530.0,90533.0] || trans(s49,s19)*+ -> . % 76.04/76.29 91318[82:Spt:91316.0,90530.1,90530.2,90530.3,90530.4,90530.5,90530.6,90530.7,90530.8,90530.9,90530.10,90530.11,90530.12,90530.13,90530.14,90530.15,90530.16,90530.17] || -> trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.29 91320[82:MRR:90532.1,91317.0] xuntil6(s49) || -> trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.29 91321[83:Spt:91318.0] || -> trans(s49,s18)*. % 76.04/76.29 91322[83:Res:91321.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s18)*. % 76.04/76.29 91324[83:Res:91321.0,60.0] || -> node2(s49,s18)*. % 76.04/76.29 91325[83:SSi:91322.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s18)*. % 76.04/76.29 91326[83:Res:91324.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 91429[83:SoR:91326.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 91431[83:SoR:91429.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)* xuntil6(s49). % 76.04/76.29 91432[83:SSi:91431.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s18,c_busy)* xuntil6(s49). % 76.04/76.29 91433[84:Spt:91432.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 91435[84:Res:91433.0,61.1] always3(s18) || -> . % 76.04/76.29 91436[84:SSi:91435.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.29 91437[84:Spt:91436.0,91432.1,91433.0] || m_main_v_state(s18,c_busy)*+ -> . % 76.04/76.29 91438[84:Spt:91436.0,91432.0,91432.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.29 91442[84:MRR:91429.2,91437.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.29 91443[84:Res:53.1,91438.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.29 91445[84:MRR:91443.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.29 91446[84:MRR:91325.0,91445.0] || -> until2p7(s18)*. % 76.04/76.29 91447[84:MRR:214.0,91446.0] || -> until2p7(s19)* node4(s18). % 76.04/76.29 91448[85:Spt:91447.0] || -> until2p7(s19)*. % 76.04/76.29 91449[85:MRR:215.0,91448.0] || -> until2p7(s20)* node4(s19). % 76.04/76.29 91450[86:Spt:91449.0] || -> until2p7(s20)*. % 76.04/76.29 91451[86:MRR:216.0,91450.0] || -> until2p7(s21)* node4(s20). % 76.04/76.29 91452[87:Spt:91451.0] || -> until2p7(s21)*. % 76.04/76.29 91453[87:MRR:217.0,91452.0] || -> until2p7(s22)* node4(s21). % 76.04/76.29 91454[88:Spt:91453.0] || -> until2p7(s22)*. % 76.04/76.29 91455[88:MRR:218.0,91454.0] || -> until2p7(s23)* node4(s22). % 76.04/76.29 91456[89:Spt:91455.0] || -> until2p7(s23)*. % 76.04/76.29 91457[89:MRR:219.0,91456.0] || -> until2p7(s24)* node4(s23). % 76.04/76.29 91458[90:Spt:91457.0] || -> until2p7(s24)*. % 76.04/76.29 91459[90:MRR:220.0,91458.0] || -> until2p7(s25)* node4(s24). % 76.04/76.29 91460[91:Spt:91459.0] || -> until2p7(s25)*. % 76.04/76.29 91461[91:MRR:221.0,91460.0] || -> until2p7(s26)* node4(s25). % 76.04/76.29 91462[92:Spt:91461.0] || -> until2p7(s26)*. % 76.04/76.29 91463[92:MRR:222.0,91462.0] || -> until2p7(s27)* node4(s26). % 76.04/76.29 91464[93:Spt:91463.0] || -> until2p7(s27)*. % 76.04/76.29 91465[93:MRR:223.0,91464.0] || -> until2p7(s28)* node4(s27). % 76.04/76.29 91466[94:Spt:91465.0] || -> until2p7(s28)*. % 76.04/76.29 91467[94:MRR:224.0,91466.0] || -> until2p7(s29)* node4(s28). % 76.04/76.29 91468[95:Spt:91467.0] || -> until2p7(s29)*. % 76.04/76.29 91469[95:MRR:225.0,91468.0] || -> until2p7(s30)* node4(s29). % 76.04/76.29 91470[96:Spt:91469.0] || -> until2p7(s30)*. % 76.04/76.29 91471[96:MRR:226.0,91470.0] || -> until2p7(s31)* node4(s30). % 76.04/76.29 91472[97:Spt:91471.0] || -> until2p7(s31)*. % 76.04/76.29 91473[97:MRR:227.0,91472.0] || -> until2p7(s32)* node4(s31). % 76.04/76.29 91474[98:Spt:91473.0] || -> until2p7(s32)*. % 76.04/76.29 91475[98:MRR:228.0,91474.0] || -> until2p7(s33)* node4(s32). % 76.04/76.29 91476[99:Spt:91475.0] || -> until2p7(s33)*. % 76.04/76.29 91477[99:MRR:229.0,91476.0] || -> until2p7(s34)* node4(s33). % 76.04/76.29 91478[100:Spt:91477.0] || -> until2p7(s34)*. % 76.04/76.29 91479[100:MRR:230.0,91478.0] || -> until2p7(s35)* node4(s34). % 76.04/76.29 91480[101:Spt:91479.0] || -> until2p7(s35)*. % 76.04/76.29 91481[101:MRR:231.0,91480.0] || -> until2p7(s36)* node4(s35). % 76.04/76.29 91482[102:Spt:91481.0] || -> until2p7(s36)*. % 76.04/76.29 91483[102:MRR:232.0,91482.0] || -> until2p7(s37)* node4(s36). % 76.04/76.29 91484[103:Spt:91483.0] || -> until2p7(s37)*. % 76.04/76.29 91485[103:MRR:235.0,91484.0] || -> until2p7(s38)* node4(s37). % 76.04/76.29 91486[104:Spt:91485.0] || -> until2p7(s38)*. % 76.04/76.29 91487[104:MRR:236.0,91486.0] || -> until2p7(s39)* node4(s38). % 76.04/76.29 91488[105:Spt:91487.0] || -> until2p7(s39)*. % 76.04/76.29 91489[105:MRR:237.0,91488.0] || -> until2p7(s40)* node4(s39). % 76.04/76.29 91490[106:Spt:91489.0] || -> until2p7(s40)*. % 76.04/76.29 91491[106:MRR:238.0,91490.0] || -> until2p7(s41)* node4(s40). % 76.04/76.29 91492[107:Spt:91491.0] || -> until2p7(s41)*. % 76.04/76.29 91493[107:MRR:239.0,91492.0] || -> until2p7(s42)* node4(s41). % 76.04/76.29 91494[108:Spt:91493.0] || -> until2p7(s42)*. % 76.04/76.29 91495[108:MRR:240.0,91494.0] || -> until2p7(s43)* node4(s42). % 76.04/76.29 91496[109:Spt:91495.0] || -> until2p7(s43)*. % 76.04/76.29 91497[109:MRR:241.0,91496.0] || -> until2p7(s44)* node4(s43). % 76.04/76.29 91498[110:Spt:91497.0] || -> until2p7(s44)*. % 76.04/76.29 91499[110:MRR:539.0,91498.0] || -> until2p7(s45)* node4(s44). % 76.04/76.29 91500[111:Spt:91499.0] || -> until2p7(s45)*. % 76.04/76.29 91501[111:MRR:544.0,91500.0] || -> until2p7(s46)* node4(s45). % 76.04/76.29 91502[112:Spt:91501.0] || -> until2p7(s46)*. % 76.04/76.29 91503[112:MRR:549.0,91502.0] || -> until2p7(s47)* node4(s46). % 76.04/76.29 91504[113:Spt:91503.0] || -> until2p7(s47)*. % 76.04/76.29 91505[113:MRR:554.0,91504.0] || -> until2p7(s48)* node4(s47). % 76.04/76.29 91506[114:Spt:91505.0] || -> until2p7(s48)*. % 76.04/76.29 91507[114:MRR:559.0,91506.0] || -> until2p7(s49)* node4(s48). % 76.04/76.29 91508[115:Spt:91507.0] || -> until2p7(s49)*. % 76.04/76.29 91509[115:MRR:194.0,91508.0] || -> node4(s49)*. % 76.04/76.29 91510[115:MRR:91442.0,91509.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.29 91514[115:Res:53.1,91510.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.29 91516[115:MRR:91514.0,78381.0] || -> . % 76.04/76.29 91517[115:Spt:91516.0,91507.0,91508.0] || until2p7(s49)*+ -> . % 76.04/76.29 91518[115:Spt:91516.0,91507.1] || -> node4(s48)*. % 76.04/76.29 91519[115:MRR:78384.0,91518.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.29 91522[115:Res:53.1,91519.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 91525[115:Res:91522.0,61.1] always3(s48) || -> . % 76.04/76.29 91526[115:SSi:91525.0,78281.0,78387.0,78626.0,91506.0,91518.0] || -> . % 76.04/76.29 91527[114:Spt:91526.0,91505.0,91506.0] || until2p7(s48)*+ -> . % 76.04/76.29 91528[114:Spt:91526.0,91505.1] || -> node4(s47)*. % 76.04/76.29 91530[114:MRR:777.0,91528.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.29 91542[114:Res:53.1,91530.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.29 91544[115:Spt:91542.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 91546[115:Res:91544.0,61.1] always3(s47) || -> . % 76.04/76.29 91547[115:SSi:91546.0,78277.0,78280.0,78625.0,91504.0,91528.0] || -> . % 76.04/76.29 91548[115:Spt:91547.0,91542.0,91544.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.29 91549[115:Spt:91547.0,91542.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 91553[115:Res:91549.0,61.1] always3(s48) || -> . % 76.04/76.29 91554[115:SSi:91553.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.29 91555[113:Spt:91554.0,91503.0,91504.0] || until2p7(s47)*+ -> . % 76.04/76.29 91556[113:Spt:91554.0,91503.1] || -> node4(s46)*. % 76.04/76.29 91558[113:MRR:780.0,91556.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.29 91565[113:Res:53.1,91558.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.29 91570[114:Spt:91565.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 91572[114:Res:91570.0,61.1] always3(s46) || -> . % 76.04/76.29 91573[114:SSi:91572.0,78272.0,78276.0,78624.0,91502.0,91556.0] || -> . % 76.04/76.29 91574[114:Spt:91573.0,91565.0,91570.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.29 91575[114:Spt:91573.0,91565.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 91579[114:Res:91575.0,61.1] always3(s47) || -> . % 76.04/76.29 91580[114:SSi:91579.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.29 91581[112:Spt:91580.0,91501.0,91502.0] || until2p7(s46)*+ -> . % 76.04/76.29 91582[112:Spt:91580.0,91501.1] || -> node4(s45)*. % 76.04/76.29 91584[112:MRR:783.0,91582.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.29 91587[112:Res:53.1,91584.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.29 91589[113:Spt:91587.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 91591[113:Res:91589.0,61.1] always3(s45) || -> . % 76.04/76.29 91592[113:SSi:91591.0,78268.0,78271.0,78623.0,91500.0,91582.0] || -> . % 76.04/76.29 91593[113:Spt:91592.0,91587.0,91589.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.29 91594[113:Spt:91592.0,91587.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 91598[113:Res:91594.0,61.1] always3(s46) || -> . % 76.04/76.29 91599[113:SSi:91598.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.29 91600[111:Spt:91599.0,91499.0,91500.0] || until2p7(s45)*+ -> . % 76.04/76.29 91601[111:Spt:91599.0,91499.1] || -> node4(s44)*. % 76.04/76.29 91603[111:MRR:786.0,91601.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.29 91606[111:Res:53.1,91603.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.29 91608[112:Spt:91606.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 91610[112:Res:91608.0,61.1] always3(s44) || -> . % 76.04/76.29 91611[112:SSi:91610.0,78263.0,78267.0,78622.0,91498.0,91601.0] || -> . % 76.04/76.29 91612[112:Spt:91611.0,91606.0,91608.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.29 91613[112:Spt:91611.0,91606.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 91617[112:Res:91613.0,61.1] always3(s45) || -> . % 76.04/76.29 91618[112:SSi:91617.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.29 91619[110:Spt:91618.0,91497.0,91498.0] || until2p7(s44)*+ -> . % 76.04/76.29 91620[110:Spt:91618.0,91497.1] || -> node4(s43)*. % 76.04/76.29 91622[110:MRR:789.0,91620.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.29 91625[110:Res:53.1,91622.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.29 91627[111:Spt:91625.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 91629[111:Res:91627.0,61.1] always3(s43) || -> . % 76.04/76.29 91630[111:SSi:91629.0,78259.0,78262.0,78621.0,91496.0,91620.0] || -> . % 76.04/76.29 91631[111:Spt:91630.0,91625.0,91627.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.29 91632[111:Spt:91630.0,91625.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 91636[111:Res:91632.0,61.1] always3(s44) || -> . % 76.04/76.29 91637[111:SSi:91636.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.29 91638[109:Spt:91637.0,91495.0,91496.0] || until2p7(s43)*+ -> . % 76.04/76.29 91639[109:Spt:91637.0,91495.1] || -> node4(s42)*. % 76.04/76.29 91641[109:MRR:792.0,91639.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.29 91644[109:Res:53.1,91641.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.29 91649[110:Spt:91644.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 91651[110:Res:91649.0,61.1] always3(s42) || -> . % 76.04/76.29 91652[110:SSi:91651.0,78254.0,78258.0,78620.0,91494.0,91639.0] || -> . % 76.04/76.29 91653[110:Spt:91652.0,91644.0,91649.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.29 91654[110:Spt:91652.0,91644.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 91658[110:Res:91654.0,61.1] always3(s43) || -> . % 76.04/76.29 91659[110:SSi:91658.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.29 91660[108:Spt:91659.0,91493.0,91494.0] || until2p7(s42)*+ -> . % 76.04/76.29 91661[108:Spt:91659.0,91493.1] || -> node4(s41)*. % 76.04/76.29 91663[108:MRR:795.0,91661.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.29 91666[108:Res:53.1,91663.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.29 91668[109:Spt:91666.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 91670[109:Res:91668.0,61.1] always3(s41) || -> . % 76.04/76.29 91671[109:SSi:91670.0,78250.0,78253.0,78619.0,91492.0,91661.0] || -> . % 76.04/76.29 91672[109:Spt:91671.0,91666.0,91668.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.29 91673[109:Spt:91671.0,91666.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 91677[109:Res:91673.0,61.1] always3(s42) || -> . % 76.04/76.29 91678[109:SSi:91677.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.29 91679[107:Spt:91678.0,91491.0,91492.0] || until2p7(s41)*+ -> . % 76.04/76.29 91680[107:Spt:91678.0,91491.1] || -> node4(s40)*. % 76.04/76.29 91682[107:MRR:798.0,91680.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.29 91685[107:Res:53.1,91682.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.29 91687[108:Spt:91685.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 91689[108:Res:91687.0,61.1] always3(s40) || -> . % 76.04/76.29 91690[108:SSi:91689.0,78245.0,78249.0,78618.0,91490.0,91680.0] || -> . % 76.04/76.29 91691[108:Spt:91690.0,91685.0,91687.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.29 91692[108:Spt:91690.0,91685.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 91696[108:Res:91692.0,61.1] always3(s41) || -> . % 76.04/76.29 91697[108:SSi:91696.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.29 91698[106:Spt:91697.0,91489.0,91490.0] || until2p7(s40)*+ -> . % 76.04/76.29 91699[106:Spt:91697.0,91489.1] || -> node4(s39)*. % 76.04/76.29 91701[106:MRR:801.0,91699.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.29 91704[106:Res:53.1,91701.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.29 91706[107:Spt:91704.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 91708[107:Res:91706.0,61.1] always3(s39) || -> . % 76.04/76.29 91709[107:SSi:91708.0,78241.0,78244.0,78617.0,91488.0,91699.0] || -> . % 76.04/76.29 91710[107:Spt:91709.0,91704.0,91706.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.29 91711[107:Spt:91709.0,91704.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 91715[107:Res:91711.0,61.1] always3(s40) || -> . % 76.04/76.29 91716[107:SSi:91715.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.29 91717[105:Spt:91716.0,91487.0,91488.0] || until2p7(s39)*+ -> . % 76.04/76.29 91718[105:Spt:91716.0,91487.1] || -> node4(s38)*. % 76.04/76.29 91720[105:MRR:804.0,91718.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.29 91723[105:Res:53.1,91720.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.29 91728[106:Spt:91723.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 91730[106:Res:91728.0,61.1] always3(s38) || -> . % 76.04/76.29 91731[106:SSi:91730.0,78236.0,78240.0,78616.0,91486.0,91718.0] || -> . % 76.04/76.29 91732[106:Spt:91731.0,91723.0,91728.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.29 91733[106:Spt:91731.0,91723.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 91737[106:Res:91733.0,61.1] always3(s39) || -> . % 76.04/76.29 91738[106:SSi:91737.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.29 91739[104:Spt:91738.0,91485.0,91486.0] || until2p7(s38)*+ -> . % 76.04/76.29 91740[104:Spt:91738.0,91485.1] || -> node4(s37)*. % 76.04/76.29 91742[104:MRR:807.0,91740.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.29 91745[104:Res:53.1,91742.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.29 91747[105:Spt:91745.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 91749[105:Res:91747.0,61.1] always3(s37) || -> . % 76.04/76.29 91750[105:SSi:91749.0,78232.0,78235.0,78615.0,91484.0,91740.0] || -> . % 76.04/76.29 91751[105:Spt:91750.0,91745.0,91747.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.29 91752[105:Spt:91750.0,91745.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 91756[105:Res:91752.0,61.1] always3(s38) || -> . % 76.04/76.29 91757[105:SSi:91756.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.29 91758[103:Spt:91757.0,91483.0,91484.0] || until2p7(s37)*+ -> . % 76.04/76.29 91759[103:Spt:91757.0,91483.1] || -> node4(s36)*. % 76.04/76.29 91761[103:MRR:810.0,91759.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.29 91764[103:Res:53.1,91761.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.29 91766[104:Spt:91764.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 91768[104:Res:91766.0,61.1] always3(s36) || -> . % 76.04/76.29 91769[104:SSi:91768.0,78227.0,78231.0,78614.0,91482.0,91759.0] || -> . % 76.04/76.29 91770[104:Spt:91769.0,91764.0,91766.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.29 91771[104:Spt:91769.0,91764.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 91775[104:Res:91771.0,61.1] always3(s37) || -> . % 76.04/76.29 91776[104:SSi:91775.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.29 91777[102:Spt:91776.0,91481.0,91482.0] || until2p7(s36)*+ -> . % 76.04/76.29 91778[102:Spt:91776.0,91481.1] || -> node4(s35)*. % 76.04/76.29 91780[102:MRR:813.0,91778.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.29 91783[102:Res:53.1,91780.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.29 91785[103:Spt:91783.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 91787[103:Res:91785.0,61.1] always3(s35) || -> . % 76.04/76.29 91788[103:SSi:91787.0,78223.0,78226.0,78613.0,91480.0,91778.0] || -> . % 76.04/76.29 91789[103:Spt:91788.0,91783.0,91785.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.29 91790[103:Spt:91788.0,91783.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 91794[103:Res:91790.0,61.1] always3(s36) || -> . % 76.04/76.29 91795[103:SSi:91794.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.29 91796[101:Spt:91795.0,91479.0,91480.0] || until2p7(s35)*+ -> . % 76.04/76.29 91797[101:Spt:91795.0,91479.1] || -> node4(s34)*. % 76.04/76.29 91799[101:MRR:816.0,91797.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.29 91802[101:Res:53.1,91799.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.29 91807[102:Spt:91802.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 91809[102:Res:91807.0,61.1] always3(s34) || -> . % 76.04/76.29 91810[102:SSi:91809.0,78218.0,78222.0,78612.0,91478.0,91797.0] || -> . % 76.04/76.29 91811[102:Spt:91810.0,91802.0,91807.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.29 91812[102:Spt:91810.0,91802.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 91816[102:Res:91812.0,61.1] always3(s35) || -> . % 76.04/76.29 91817[102:SSi:91816.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.29 91818[100:Spt:91817.0,91477.0,91478.0] || until2p7(s34)*+ -> . % 76.04/76.29 91819[100:Spt:91817.0,91477.1] || -> node4(s33)*. % 76.04/76.29 91821[100:MRR:819.0,91819.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.29 91824[100:Res:53.1,91821.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.29 91826[101:Spt:91824.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 91828[101:Res:91826.0,61.1] always3(s33) || -> . % 76.04/76.29 91829[101:SSi:91828.0,78214.0,78217.0,78611.0,91476.0,91819.0] || -> . % 76.04/76.29 91830[101:Spt:91829.0,91824.0,91826.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.29 91831[101:Spt:91829.0,91824.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 91835[101:Res:91831.0,61.1] always3(s34) || -> . % 76.04/76.29 91836[101:SSi:91835.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.29 91837[99:Spt:91836.0,91475.0,91476.0] || until2p7(s33)*+ -> . % 76.04/76.29 91838[99:Spt:91836.0,91475.1] || -> node4(s32)*. % 76.04/76.29 91840[99:MRR:822.0,91838.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.29 91843[99:Res:53.1,91840.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.29 91845[100:Spt:91843.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 91847[100:Res:91845.0,61.1] always3(s32) || -> . % 76.04/76.29 91848[100:SSi:91847.0,78209.0,78213.0,78610.0,91474.0,91838.0] || -> . % 76.04/76.29 91849[100:Spt:91848.0,91843.0,91845.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.29 91850[100:Spt:91848.0,91843.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 91854[100:Res:91850.0,61.1] always3(s33) || -> . % 76.04/76.29 91855[100:SSi:91854.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.29 91856[98:Spt:91855.0,91473.0,91474.0] || until2p7(s32)*+ -> . % 76.04/76.29 91857[98:Spt:91855.0,91473.1] || -> node4(s31)*. % 76.04/76.29 91859[98:MRR:825.0,91857.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.29 91862[98:Res:53.1,91859.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.29 91864[99:Spt:91862.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 91866[99:Res:91864.0,61.1] always3(s31) || -> . % 76.04/76.29 91867[99:SSi:91866.0,78205.0,78208.0,78609.0,91472.0,91857.0] || -> . % 76.04/76.29 91868[99:Spt:91867.0,91862.0,91864.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.29 91869[99:Spt:91867.0,91862.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 91873[99:Res:91869.0,61.1] always3(s32) || -> . % 76.04/76.29 91874[99:SSi:91873.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.29 91875[97:Spt:91874.0,91471.0,91472.0] || until2p7(s31)*+ -> . % 76.04/76.29 91876[97:Spt:91874.0,91471.1] || -> node4(s30)*. % 76.04/76.29 91878[97:MRR:828.0,91876.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.29 91881[97:Res:53.1,91878.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.29 91886[98:Spt:91881.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 91888[98:Res:91886.0,61.1] always3(s30) || -> . % 76.04/76.29 91889[98:SSi:91888.0,78200.0,78204.0,78608.0,91470.0,91876.0] || -> . % 76.04/76.29 91890[98:Spt:91889.0,91881.0,91886.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.29 91891[98:Spt:91889.0,91881.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 91895[98:Res:91891.0,61.1] always3(s31) || -> . % 76.04/76.29 91896[98:SSi:91895.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.29 91897[96:Spt:91896.0,91469.0,91470.0] || until2p7(s30)*+ -> . % 76.04/76.29 91898[96:Spt:91896.0,91469.1] || -> node4(s29)*. % 76.04/76.29 91900[96:MRR:831.0,91898.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.29 91903[96:Res:53.1,91900.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.29 91905[97:Spt:91903.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 91907[97:Res:91905.0,61.1] always3(s29) || -> . % 76.04/76.29 91908[97:SSi:91907.0,78196.0,78199.0,78607.0,91468.0,91898.0] || -> . % 76.04/76.29 91909[97:Spt:91908.0,91903.0,91905.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.29 91910[97:Spt:91908.0,91903.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 91914[97:Res:91910.0,61.1] always3(s30) || -> . % 76.04/76.29 91915[97:SSi:91914.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.29 91916[95:Spt:91915.0,91467.0,91468.0] || until2p7(s29)*+ -> . % 76.04/76.29 91917[95:Spt:91915.0,91467.1] || -> node4(s28)*. % 76.04/76.29 91919[95:MRR:834.0,91917.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.29 91922[95:Res:53.1,91919.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.29 91924[96:Spt:91922.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 91926[96:Res:91924.0,61.1] always3(s28) || -> . % 76.04/76.29 91927[96:SSi:91926.0,78191.0,78195.0,78606.0,91466.0,91917.0] || -> . % 76.04/76.29 91928[96:Spt:91927.0,91922.0,91924.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.29 91929[96:Spt:91927.0,91922.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 91933[96:Res:91929.0,61.1] always3(s29) || -> . % 76.04/76.29 91934[96:SSi:91933.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.29 91935[94:Spt:91934.0,91465.0,91466.0] || until2p7(s28)*+ -> . % 76.04/76.29 91936[94:Spt:91934.0,91465.1] || -> node4(s27)*. % 76.04/76.29 91938[94:MRR:837.0,91936.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.29 91941[94:Res:53.1,91938.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.29 91943[95:Spt:91941.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 91945[95:Res:91943.0,61.1] always3(s27) || -> . % 76.04/76.29 91946[95:SSi:91945.0,78187.0,78190.0,78605.0,91464.0,91936.0] || -> . % 76.04/76.29 91947[95:Spt:91946.0,91941.0,91943.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.29 91948[95:Spt:91946.0,91941.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 91952[95:Res:91948.0,61.1] always3(s28) || -> . % 76.04/76.29 91953[95:SSi:91952.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.29 91954[93:Spt:91953.0,91463.0,91464.0] || until2p7(s27)*+ -> . % 76.04/76.29 91955[93:Spt:91953.0,91463.1] || -> node4(s26)*. % 76.04/76.29 91957[93:MRR:840.0,91955.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.29 91960[93:Res:53.1,91957.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.29 91965[94:Spt:91960.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 91967[94:Res:91965.0,61.1] always3(s26) || -> . % 76.04/76.29 91968[94:SSi:91967.0,78182.0,78186.0,78604.0,91462.0,91955.0] || -> . % 76.04/76.29 91969[94:Spt:91968.0,91960.0,91965.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.29 91970[94:Spt:91968.0,91960.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 91974[94:Res:91970.0,61.1] always3(s27) || -> . % 76.04/76.29 91975[94:SSi:91974.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.29 91976[92:Spt:91975.0,91461.0,91462.0] || until2p7(s26)*+ -> . % 76.04/76.29 91977[92:Spt:91975.0,91461.1] || -> node4(s25)*. % 76.04/76.29 91979[92:MRR:843.0,91977.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.29 91982[92:Res:53.1,91979.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.29 91984[93:Spt:91982.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 91986[93:Res:91984.0,61.1] always3(s25) || -> . % 76.04/76.29 91987[93:SSi:91986.0,78178.0,78181.0,78603.0,91460.0,91977.0] || -> . % 76.04/76.29 91988[93:Spt:91987.0,91982.0,91984.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.29 91989[93:Spt:91987.0,91982.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 91993[93:Res:91989.0,61.1] always3(s26) || -> . % 76.04/76.29 91994[93:SSi:91993.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.29 91995[91:Spt:91994.0,91459.0,91460.0] || until2p7(s25)*+ -> . % 76.04/76.29 91996[91:Spt:91994.0,91459.1] || -> node4(s24)*. % 76.04/76.29 91998[91:MRR:846.0,91996.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.29 92001[91:Res:53.1,91998.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.29 92003[92:Spt:92001.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 92005[92:Res:92003.0,61.1] always3(s24) || -> . % 76.04/76.29 92006[92:SSi:92005.0,78173.0,78177.0,78602.0,91458.0,91996.0] || -> . % 76.04/76.29 92007[92:Spt:92006.0,92001.0,92003.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.29 92008[92:Spt:92006.0,92001.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 92012[92:Res:92008.0,61.1] always3(s25) || -> . % 76.04/76.29 92013[92:SSi:92012.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.29 92014[90:Spt:92013.0,91457.0,91458.0] || until2p7(s24)*+ -> . % 76.04/76.29 92015[90:Spt:92013.0,91457.1] || -> node4(s23)*. % 76.04/76.29 92017[90:MRR:849.0,92015.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.29 92020[90:Res:53.1,92017.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.29 92022[91:Spt:92020.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 92024[91:Res:92022.0,61.1] always3(s23) || -> . % 76.04/76.29 92025[91:SSi:92024.0,78169.0,78172.0,78601.0,91456.0,92015.0] || -> . % 76.04/76.29 92026[91:Spt:92025.0,92020.0,92022.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.29 92027[91:Spt:92025.0,92020.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 92031[91:Res:92027.0,61.1] always3(s24) || -> . % 76.04/76.29 92032[91:SSi:92031.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.29 92033[89:Spt:92032.0,91455.0,91456.0] || until2p7(s23)*+ -> . % 76.04/76.29 92034[89:Spt:92032.0,91455.1] || -> node4(s22)*. % 76.04/76.29 92036[89:MRR:852.0,92034.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.29 92039[89:Res:53.1,92036.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.29 92044[90:Spt:92039.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 92046[90:Res:92044.0,61.1] always3(s22) || -> . % 76.04/76.29 92047[90:SSi:92046.0,78164.0,78168.0,78600.0,91454.0,92034.0] || -> . % 76.04/76.29 92048[90:Spt:92047.0,92039.0,92044.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.29 92049[90:Spt:92047.0,92039.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 92053[90:Res:92049.0,61.1] always3(s23) || -> . % 76.04/76.29 92054[90:SSi:92053.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.29 92055[88:Spt:92054.0,91453.0,91454.0] || until2p7(s22)*+ -> . % 76.04/76.29 92056[88:Spt:92054.0,91453.1] || -> node4(s21)*. % 76.04/76.29 92058[88:MRR:855.0,92056.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.29 92061[88:Res:53.1,92058.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.29 92063[89:Spt:92061.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 92065[89:Res:92063.0,61.1] always3(s21) || -> . % 76.04/76.29 92066[89:SSi:92065.0,78160.0,78163.0,78599.0,91452.0,92056.0] || -> . % 76.04/76.29 92067[89:Spt:92066.0,92061.0,92063.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.29 92068[89:Spt:92066.0,92061.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 92072[89:Res:92068.0,61.1] always3(s22) || -> . % 76.04/76.29 92073[89:SSi:92072.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.29 92074[87:Spt:92073.0,91451.0,91452.0] || until2p7(s21)*+ -> . % 76.04/76.29 92075[87:Spt:92073.0,91451.1] || -> node4(s20)*. % 76.04/76.29 92077[87:MRR:858.0,92075.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.29 92080[87:Res:53.1,92077.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.29 92082[88:Spt:92080.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 92084[88:Res:92082.0,61.1] always3(s20) || -> . % 76.04/76.29 92085[88:SSi:92084.0,78155.0,78159.0,78598.0,91450.0,92075.0] || -> . % 76.04/76.29 92086[88:Spt:92085.0,92080.0,92082.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.29 92087[88:Spt:92085.0,92080.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 92091[88:Res:92087.0,61.1] always3(s21) || -> . % 76.04/76.29 92092[88:SSi:92091.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.29 92093[86:Spt:92092.0,91449.0,91450.0] || until2p7(s20)*+ -> . % 76.04/76.29 92094[86:Spt:92092.0,91449.1] || -> node4(s19)*. % 76.04/76.29 92096[86:MRR:861.0,92094.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.29 92099[86:Res:53.1,92096.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.29 92101[87:Spt:92099.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 92103[87:Res:92101.0,61.1] always3(s19) || -> . % 76.04/76.29 92104[87:SSi:92103.0,78151.0,78154.0,78597.0,91448.0,92094.0] || -> . % 76.04/76.29 92105[87:Spt:92104.0,92099.0,92101.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.29 92106[87:Spt:92104.0,92099.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 92110[87:Res:92106.0,61.1] always3(s20) || -> . % 76.04/76.29 92111[87:SSi:92110.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.29 92112[85:Spt:92111.0,91447.0,91448.0] || until2p7(s19)*+ -> . % 76.04/76.29 92113[85:Spt:92111.0,91447.1] || -> node4(s18)*. % 76.04/76.29 92115[85:MRR:864.0,92113.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.29 92118[85:Res:53.1,92115.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.29 92120[85:MRR:92118.0,91437.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 92125[85:Res:92120.0,61.1] always3(s19) || -> . % 76.04/76.29 92126[85:SSi:92125.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.29 92127[83:Spt:92126.0,91318.0,91321.0] || trans(s49,s18)*+ -> . % 76.04/76.29 92128[83:Spt:92126.0,91318.1,91318.2,91318.3,91318.4,91318.5,91318.6,91318.7,91318.8,91318.9,91318.10,91318.11,91318.12,91318.13,91318.14,91318.15,91318.16] || -> trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.29 92130[83:MRR:91320.1,92127.0] xuntil6(s49) || -> trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.29 92131[84:Spt:92128.0] || -> trans(s49,s17)*. % 76.04/76.29 92132[84:Res:92131.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s17)*. % 76.04/76.29 92134[84:Res:92131.0,60.0] || -> node2(s49,s17)*. % 76.04/76.29 92135[84:SSi:92132.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s17)*. % 76.04/76.29 92136[84:Res:92134.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 92243[84:SoR:92136.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 92245[84:SoR:92243.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)* xuntil6(s49). % 76.04/76.29 92246[84:SSi:92245.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s17,c_busy)* xuntil6(s49). % 76.04/76.29 92247[85:Spt:92246.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 92249[85:Res:92247.0,61.1] always3(s17) || -> . % 76.04/76.29 92250[85:SSi:92249.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.29 92251[85:Spt:92250.0,92246.1,92247.0] || m_main_v_state(s17,c_busy)*+ -> . % 76.04/76.29 92252[85:Spt:92250.0,92246.0,92246.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.29 92256[85:MRR:92243.2,92251.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.29 92257[85:Res:53.1,92252.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.29 92259[85:MRR:92257.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.29 92260[85:MRR:92135.0,92259.0] || -> until2p7(s17)*. % 76.04/76.29 92261[85:MRR:213.0,92260.0] || -> until2p7(s18)* node4(s17). % 76.04/76.29 92262[86:Spt:92261.0] || -> until2p7(s18)*. % 76.04/76.29 92263[86:MRR:214.0,92262.0] || -> until2p7(s19)* node4(s18). % 76.04/76.29 92264[87:Spt:92263.0] || -> until2p7(s19)*. % 76.04/76.29 92265[87:MRR:215.0,92264.0] || -> until2p7(s20)* node4(s19). % 76.04/76.29 92266[88:Spt:92265.0] || -> until2p7(s20)*. % 76.04/76.29 92267[88:MRR:216.0,92266.0] || -> until2p7(s21)* node4(s20). % 76.04/76.29 92268[89:Spt:92267.0] || -> until2p7(s21)*. % 76.04/76.29 92269[89:MRR:217.0,92268.0] || -> until2p7(s22)* node4(s21). % 76.04/76.29 92270[90:Spt:92269.0] || -> until2p7(s22)*. % 76.04/76.29 92271[90:MRR:218.0,92270.0] || -> until2p7(s23)* node4(s22). % 76.04/76.29 92272[91:Spt:92271.0] || -> until2p7(s23)*. % 76.04/76.29 92273[91:MRR:219.0,92272.0] || -> until2p7(s24)* node4(s23). % 76.04/76.29 92274[92:Spt:92273.0] || -> until2p7(s24)*. % 76.04/76.29 92275[92:MRR:220.0,92274.0] || -> until2p7(s25)* node4(s24). % 76.04/76.29 92276[93:Spt:92275.0] || -> until2p7(s25)*. % 76.04/76.29 92277[93:MRR:221.0,92276.0] || -> until2p7(s26)* node4(s25). % 76.04/76.29 92278[94:Spt:92277.0] || -> until2p7(s26)*. % 76.04/76.29 92279[94:MRR:222.0,92278.0] || -> until2p7(s27)* node4(s26). % 76.04/76.29 92280[95:Spt:92279.0] || -> until2p7(s27)*. % 76.04/76.29 92281[95:MRR:223.0,92280.0] || -> until2p7(s28)* node4(s27). % 76.04/76.29 92282[96:Spt:92281.0] || -> until2p7(s28)*. % 76.04/76.29 92283[96:MRR:224.0,92282.0] || -> until2p7(s29)* node4(s28). % 76.04/76.29 92284[97:Spt:92283.0] || -> until2p7(s29)*. % 76.04/76.29 92285[97:MRR:225.0,92284.0] || -> until2p7(s30)* node4(s29). % 76.04/76.29 92286[98:Spt:92285.0] || -> until2p7(s30)*. % 76.04/76.29 92287[98:MRR:226.0,92286.0] || -> until2p7(s31)* node4(s30). % 76.04/76.29 92288[99:Spt:92287.0] || -> until2p7(s31)*. % 76.04/76.29 92289[99:MRR:227.0,92288.0] || -> until2p7(s32)* node4(s31). % 76.04/76.29 92290[100:Spt:92289.0] || -> until2p7(s32)*. % 76.04/76.29 92291[100:MRR:228.0,92290.0] || -> until2p7(s33)* node4(s32). % 76.04/76.29 92292[101:Spt:92291.0] || -> until2p7(s33)*. % 76.04/76.29 92293[101:MRR:229.0,92292.0] || -> until2p7(s34)* node4(s33). % 76.04/76.29 92294[102:Spt:92293.0] || -> until2p7(s34)*. % 76.04/76.29 92295[102:MRR:230.0,92294.0] || -> until2p7(s35)* node4(s34). % 76.04/76.29 92296[103:Spt:92295.0] || -> until2p7(s35)*. % 76.04/76.29 92297[103:MRR:231.0,92296.0] || -> until2p7(s36)* node4(s35). % 76.04/76.29 92298[104:Spt:92297.0] || -> until2p7(s36)*. % 76.04/76.29 92299[104:MRR:232.0,92298.0] || -> until2p7(s37)* node4(s36). % 76.04/76.29 92300[105:Spt:92299.0] || -> until2p7(s37)*. % 76.04/76.29 92301[105:MRR:235.0,92300.0] || -> until2p7(s38)* node4(s37). % 76.04/76.29 92302[106:Spt:92301.0] || -> until2p7(s38)*. % 76.04/76.29 92303[106:MRR:236.0,92302.0] || -> until2p7(s39)* node4(s38). % 76.04/76.29 92304[107:Spt:92303.0] || -> until2p7(s39)*. % 76.04/76.29 92305[107:MRR:237.0,92304.0] || -> until2p7(s40)* node4(s39). % 76.04/76.29 92306[108:Spt:92305.0] || -> until2p7(s40)*. % 76.04/76.29 92307[108:MRR:238.0,92306.0] || -> until2p7(s41)* node4(s40). % 76.04/76.29 92308[109:Spt:92307.0] || -> until2p7(s41)*. % 76.04/76.29 92309[109:MRR:239.0,92308.0] || -> until2p7(s42)* node4(s41). % 76.04/76.29 92310[110:Spt:92309.0] || -> until2p7(s42)*. % 76.04/76.29 92311[110:MRR:240.0,92310.0] || -> until2p7(s43)* node4(s42). % 76.04/76.29 92312[111:Spt:92311.0] || -> until2p7(s43)*. % 76.04/76.29 92313[111:MRR:241.0,92312.0] || -> until2p7(s44)* node4(s43). % 76.04/76.29 92314[112:Spt:92313.0] || -> until2p7(s44)*. % 76.04/76.29 92315[112:MRR:539.0,92314.0] || -> until2p7(s45)* node4(s44). % 76.04/76.29 92316[113:Spt:92315.0] || -> until2p7(s45)*. % 76.04/76.29 92317[113:MRR:544.0,92316.0] || -> until2p7(s46)* node4(s45). % 76.04/76.29 92318[114:Spt:92317.0] || -> until2p7(s46)*. % 76.04/76.29 92319[114:MRR:549.0,92318.0] || -> until2p7(s47)* node4(s46). % 76.04/76.29 92320[115:Spt:92319.0] || -> until2p7(s47)*. % 76.04/76.29 92321[115:MRR:554.0,92320.0] || -> until2p7(s48)* node4(s47). % 76.04/76.29 92322[116:Spt:92321.0] || -> until2p7(s48)*. % 76.04/76.29 92323[116:MRR:559.0,92322.0] || -> until2p7(s49)* node4(s48). % 76.04/76.29 92324[117:Spt:92323.0] || -> until2p7(s49)*. % 76.04/76.29 92325[117:MRR:194.0,92324.0] || -> node4(s49)*. % 76.04/76.29 92326[117:MRR:92256.0,92325.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.29 92327[117:Res:53.1,92326.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.29 92329[117:MRR:92327.0,78381.0] || -> . % 76.04/76.29 92330[117:Spt:92329.0,92323.0,92324.0] || until2p7(s49)*+ -> . % 76.04/76.29 92331[117:Spt:92329.0,92323.1] || -> node4(s48)*. % 76.04/76.29 92332[117:MRR:78384.0,92331.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.29 92335[117:Res:53.1,92332.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 92338[117:Res:92335.0,61.1] always3(s48) || -> . % 76.04/76.29 92339[117:SSi:92338.0,78281.0,78387.0,78626.0,92322.0,92331.0] || -> . % 76.04/76.29 92340[116:Spt:92339.0,92321.0,92322.0] || until2p7(s48)*+ -> . % 76.04/76.29 92341[116:Spt:92339.0,92321.1] || -> node4(s47)*. % 76.04/76.29 92343[116:MRR:777.0,92341.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.29 92358[116:Res:53.1,92343.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.29 92363[117:Spt:92358.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 92365[117:Res:92363.0,61.1] always3(s47) || -> . % 76.04/76.29 92366[117:SSi:92365.0,78277.0,78280.0,78625.0,92320.0,92341.0] || -> . % 76.04/76.29 92367[117:Spt:92366.0,92358.0,92363.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.29 92368[117:Spt:92366.0,92358.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 92372[117:Res:92368.0,61.1] always3(s48) || -> . % 76.04/76.29 92373[117:SSi:92372.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.29 92374[115:Spt:92373.0,92319.0,92320.0] || until2p7(s47)*+ -> . % 76.04/76.29 92375[115:Spt:92373.0,92319.1] || -> node4(s46)*. % 76.04/76.29 92377[115:MRR:780.0,92375.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.29 92384[115:Res:53.1,92377.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.29 92386[116:Spt:92384.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 92388[116:Res:92386.0,61.1] always3(s46) || -> . % 76.04/76.29 92389[116:SSi:92388.0,78272.0,78276.0,78624.0,92318.0,92375.0] || -> . % 76.04/76.29 92390[116:Spt:92389.0,92384.0,92386.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.29 92391[116:Spt:92389.0,92384.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 92395[116:Res:92391.0,61.1] always3(s47) || -> . % 76.04/76.29 92396[116:SSi:92395.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.29 92397[114:Spt:92396.0,92317.0,92318.0] || until2p7(s46)*+ -> . % 76.04/76.29 92398[114:Spt:92396.0,92317.1] || -> node4(s45)*. % 76.04/76.29 92400[114:MRR:783.0,92398.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.29 92403[114:Res:53.1,92400.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.29 92408[115:Spt:92403.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 92410[115:Res:92408.0,61.1] always3(s45) || -> . % 76.04/76.29 92411[115:SSi:92410.0,78268.0,78271.0,78623.0,92316.0,92398.0] || -> . % 76.04/76.29 92412[115:Spt:92411.0,92403.0,92408.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.29 92413[115:Spt:92411.0,92403.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 92417[115:Res:92413.0,61.1] always3(s46) || -> . % 76.04/76.29 92418[115:SSi:92417.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.29 92419[113:Spt:92418.0,92315.0,92316.0] || until2p7(s45)*+ -> . % 76.04/76.29 92420[113:Spt:92418.0,92315.1] || -> node4(s44)*. % 76.04/76.29 92422[113:MRR:786.0,92420.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.29 92425[113:Res:53.1,92422.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.29 92427[114:Spt:92425.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 92429[114:Res:92427.0,61.1] always3(s44) || -> . % 76.04/76.29 92430[114:SSi:92429.0,78263.0,78267.0,78622.0,92314.0,92420.0] || -> . % 76.04/76.29 92431[114:Spt:92430.0,92425.0,92427.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.29 92432[114:Spt:92430.0,92425.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 92436[114:Res:92432.0,61.1] always3(s45) || -> . % 76.04/76.29 92437[114:SSi:92436.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.29 92438[112:Spt:92437.0,92313.0,92314.0] || until2p7(s44)*+ -> . % 76.04/76.29 92439[112:Spt:92437.0,92313.1] || -> node4(s43)*. % 76.04/76.29 92441[112:MRR:789.0,92439.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.29 92444[112:Res:53.1,92441.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.29 92446[113:Spt:92444.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 92448[113:Res:92446.0,61.1] always3(s43) || -> . % 76.04/76.29 92449[113:SSi:92448.0,78259.0,78262.0,78621.0,92312.0,92439.0] || -> . % 76.04/76.29 92450[113:Spt:92449.0,92444.0,92446.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.29 92451[113:Spt:92449.0,92444.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 92455[113:Res:92451.0,61.1] always3(s44) || -> . % 76.04/76.29 92456[113:SSi:92455.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.29 92457[111:Spt:92456.0,92311.0,92312.0] || until2p7(s43)*+ -> . % 76.04/76.29 92458[111:Spt:92456.0,92311.1] || -> node4(s42)*. % 76.04/76.29 92460[111:MRR:792.0,92458.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.29 92463[111:Res:53.1,92460.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.29 92465[112:Spt:92463.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 92467[112:Res:92465.0,61.1] always3(s42) || -> . % 76.04/76.29 92468[112:SSi:92467.0,78254.0,78258.0,78620.0,92310.0,92458.0] || -> . % 76.04/76.29 92469[112:Spt:92468.0,92463.0,92465.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.29 92470[112:Spt:92468.0,92463.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 92474[112:Res:92470.0,61.1] always3(s43) || -> . % 76.04/76.29 92475[112:SSi:92474.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.29 92476[110:Spt:92475.0,92309.0,92310.0] || until2p7(s42)*+ -> . % 76.04/76.29 92477[110:Spt:92475.0,92309.1] || -> node4(s41)*. % 76.04/76.29 92479[110:MRR:795.0,92477.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.29 92482[110:Res:53.1,92479.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.29 92487[111:Spt:92482.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 92489[111:Res:92487.0,61.1] always3(s41) || -> . % 76.04/76.29 92490[111:SSi:92489.0,78250.0,78253.0,78619.0,92308.0,92477.0] || -> . % 76.04/76.29 92491[111:Spt:92490.0,92482.0,92487.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.29 92492[111:Spt:92490.0,92482.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 92496[111:Res:92492.0,61.1] always3(s42) || -> . % 76.04/76.29 92497[111:SSi:92496.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.29 92498[109:Spt:92497.0,92307.0,92308.0] || until2p7(s41)*+ -> . % 76.04/76.29 92499[109:Spt:92497.0,92307.1] || -> node4(s40)*. % 76.04/76.29 92501[109:MRR:798.0,92499.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.29 92504[109:Res:53.1,92501.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.29 92506[110:Spt:92504.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 92508[110:Res:92506.0,61.1] always3(s40) || -> . % 76.04/76.29 92509[110:SSi:92508.0,78245.0,78249.0,78618.0,92306.0,92499.0] || -> . % 76.04/76.29 92510[110:Spt:92509.0,92504.0,92506.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.29 92511[110:Spt:92509.0,92504.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 92515[110:Res:92511.0,61.1] always3(s41) || -> . % 76.04/76.29 92516[110:SSi:92515.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.29 92517[108:Spt:92516.0,92305.0,92306.0] || until2p7(s40)*+ -> . % 76.04/76.29 92518[108:Spt:92516.0,92305.1] || -> node4(s39)*. % 76.04/76.29 92520[108:MRR:801.0,92518.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.29 92523[108:Res:53.1,92520.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.29 92525[109:Spt:92523.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 92527[109:Res:92525.0,61.1] always3(s39) || -> . % 76.04/76.29 92528[109:SSi:92527.0,78241.0,78244.0,78617.0,92304.0,92518.0] || -> . % 76.04/76.29 92529[109:Spt:92528.0,92523.0,92525.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.29 92530[109:Spt:92528.0,92523.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 92534[109:Res:92530.0,61.1] always3(s40) || -> . % 76.04/76.29 92535[109:SSi:92534.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.29 92536[107:Spt:92535.0,92303.0,92304.0] || until2p7(s39)*+ -> . % 76.04/76.29 92537[107:Spt:92535.0,92303.1] || -> node4(s38)*. % 76.04/76.29 92539[107:MRR:804.0,92537.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.29 92542[107:Res:53.1,92539.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.29 92544[108:Spt:92542.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 92546[108:Res:92544.0,61.1] always3(s38) || -> . % 76.04/76.29 92547[108:SSi:92546.0,78236.0,78240.0,78616.0,92302.0,92537.0] || -> . % 76.04/76.29 92548[108:Spt:92547.0,92542.0,92544.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.29 92549[108:Spt:92547.0,92542.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 92553[108:Res:92549.0,61.1] always3(s39) || -> . % 76.04/76.29 92554[108:SSi:92553.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.29 92555[106:Spt:92554.0,92301.0,92302.0] || until2p7(s38)*+ -> . % 76.04/76.29 92556[106:Spt:92554.0,92301.1] || -> node4(s37)*. % 76.04/76.29 92558[106:MRR:807.0,92556.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.29 92561[106:Res:53.1,92558.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.29 92566[107:Spt:92561.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 92568[107:Res:92566.0,61.1] always3(s37) || -> . % 76.04/76.29 92569[107:SSi:92568.0,78232.0,78235.0,78615.0,92300.0,92556.0] || -> . % 76.04/76.29 92570[107:Spt:92569.0,92561.0,92566.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.29 92571[107:Spt:92569.0,92561.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 92575[107:Res:92571.0,61.1] always3(s38) || -> . % 76.04/76.29 92576[107:SSi:92575.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.29 92577[105:Spt:92576.0,92299.0,92300.0] || until2p7(s37)*+ -> . % 76.04/76.29 92578[105:Spt:92576.0,92299.1] || -> node4(s36)*. % 76.04/76.29 92580[105:MRR:810.0,92578.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.29 92583[105:Res:53.1,92580.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.29 92585[106:Spt:92583.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 92587[106:Res:92585.0,61.1] always3(s36) || -> . % 76.04/76.29 92588[106:SSi:92587.0,78227.0,78231.0,78614.0,92298.0,92578.0] || -> . % 76.04/76.29 92589[106:Spt:92588.0,92583.0,92585.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.29 92590[106:Spt:92588.0,92583.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 92594[106:Res:92590.0,61.1] always3(s37) || -> . % 76.04/76.29 92595[106:SSi:92594.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.29 92596[104:Spt:92595.0,92297.0,92298.0] || until2p7(s36)*+ -> . % 76.04/76.29 92597[104:Spt:92595.0,92297.1] || -> node4(s35)*. % 76.04/76.29 92599[104:MRR:813.0,92597.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.29 92602[104:Res:53.1,92599.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.29 92604[105:Spt:92602.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 92606[105:Res:92604.0,61.1] always3(s35) || -> . % 76.04/76.29 92607[105:SSi:92606.0,78223.0,78226.0,78613.0,92296.0,92597.0] || -> . % 76.04/76.29 92608[105:Spt:92607.0,92602.0,92604.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.29 92609[105:Spt:92607.0,92602.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 92613[105:Res:92609.0,61.1] always3(s36) || -> . % 76.04/76.29 92614[105:SSi:92613.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.29 92615[103:Spt:92614.0,92295.0,92296.0] || until2p7(s35)*+ -> . % 76.04/76.29 92616[103:Spt:92614.0,92295.1] || -> node4(s34)*. % 76.04/76.29 92618[103:MRR:816.0,92616.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.29 92621[103:Res:53.1,92618.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.29 92623[104:Spt:92621.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 92625[104:Res:92623.0,61.1] always3(s34) || -> . % 76.04/76.29 92626[104:SSi:92625.0,78218.0,78222.0,78612.0,92294.0,92616.0] || -> . % 76.04/76.29 92627[104:Spt:92626.0,92621.0,92623.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.29 92628[104:Spt:92626.0,92621.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 92632[104:Res:92628.0,61.1] always3(s35) || -> . % 76.04/76.29 92633[104:SSi:92632.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.29 92634[102:Spt:92633.0,92293.0,92294.0] || until2p7(s34)*+ -> . % 76.04/76.29 92635[102:Spt:92633.0,92293.1] || -> node4(s33)*. % 76.04/76.29 92637[102:MRR:819.0,92635.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.29 92640[102:Res:53.1,92637.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.29 92645[103:Spt:92640.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 92647[103:Res:92645.0,61.1] always3(s33) || -> . % 76.04/76.29 92648[103:SSi:92647.0,78214.0,78217.0,78611.0,92292.0,92635.0] || -> . % 76.04/76.29 92649[103:Spt:92648.0,92640.0,92645.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.29 92650[103:Spt:92648.0,92640.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 92654[103:Res:92650.0,61.1] always3(s34) || -> . % 76.04/76.29 92655[103:SSi:92654.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.29 92656[101:Spt:92655.0,92291.0,92292.0] || until2p7(s33)*+ -> . % 76.04/76.29 92657[101:Spt:92655.0,92291.1] || -> node4(s32)*. % 76.04/76.29 92659[101:MRR:822.0,92657.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.29 92662[101:Res:53.1,92659.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.29 92664[102:Spt:92662.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 92666[102:Res:92664.0,61.1] always3(s32) || -> . % 76.04/76.29 92667[102:SSi:92666.0,78209.0,78213.0,78610.0,92290.0,92657.0] || -> . % 76.04/76.29 92668[102:Spt:92667.0,92662.0,92664.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.29 92669[102:Spt:92667.0,92662.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 92673[102:Res:92669.0,61.1] always3(s33) || -> . % 76.04/76.29 92674[102:SSi:92673.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.29 92675[100:Spt:92674.0,92289.0,92290.0] || until2p7(s32)*+ -> . % 76.04/76.29 92676[100:Spt:92674.0,92289.1] || -> node4(s31)*. % 76.04/76.29 92678[100:MRR:825.0,92676.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.29 92681[100:Res:53.1,92678.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.29 92683[101:Spt:92681.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 92685[101:Res:92683.0,61.1] always3(s31) || -> . % 76.04/76.29 92686[101:SSi:92685.0,78205.0,78208.0,78609.0,92288.0,92676.0] || -> . % 76.04/76.29 92687[101:Spt:92686.0,92681.0,92683.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.29 92688[101:Spt:92686.0,92681.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 92692[101:Res:92688.0,61.1] always3(s32) || -> . % 76.04/76.29 92693[101:SSi:92692.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.29 92694[99:Spt:92693.0,92287.0,92288.0] || until2p7(s31)*+ -> . % 76.04/76.29 92695[99:Spt:92693.0,92287.1] || -> node4(s30)*. % 76.04/76.29 92697[99:MRR:828.0,92695.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.29 92700[99:Res:53.1,92697.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.29 92702[100:Spt:92700.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 92704[100:Res:92702.0,61.1] always3(s30) || -> . % 76.04/76.29 92705[100:SSi:92704.0,78200.0,78204.0,78608.0,92286.0,92695.0] || -> . % 76.04/76.29 92706[100:Spt:92705.0,92700.0,92702.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.29 92707[100:Spt:92705.0,92700.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 92711[100:Res:92707.0,61.1] always3(s31) || -> . % 76.04/76.29 92712[100:SSi:92711.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.29 92713[98:Spt:92712.0,92285.0,92286.0] || until2p7(s30)*+ -> . % 76.04/76.29 92714[98:Spt:92712.0,92285.1] || -> node4(s29)*. % 76.04/76.29 92716[98:MRR:831.0,92714.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.29 92719[98:Res:53.1,92716.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.29 92724[99:Spt:92719.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 92726[99:Res:92724.0,61.1] always3(s29) || -> . % 76.04/76.29 92727[99:SSi:92726.0,78196.0,78199.0,78607.0,92284.0,92714.0] || -> . % 76.04/76.29 92728[99:Spt:92727.0,92719.0,92724.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.29 92729[99:Spt:92727.0,92719.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 92733[99:Res:92729.0,61.1] always3(s30) || -> . % 76.04/76.29 92734[99:SSi:92733.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.29 92735[97:Spt:92734.0,92283.0,92284.0] || until2p7(s29)*+ -> . % 76.04/76.29 92736[97:Spt:92734.0,92283.1] || -> node4(s28)*. % 76.04/76.29 92738[97:MRR:834.0,92736.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.29 92741[97:Res:53.1,92738.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.29 92743[98:Spt:92741.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 92745[98:Res:92743.0,61.1] always3(s28) || -> . % 76.04/76.29 92746[98:SSi:92745.0,78191.0,78195.0,78606.0,92282.0,92736.0] || -> . % 76.04/76.29 92747[98:Spt:92746.0,92741.0,92743.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.29 92748[98:Spt:92746.0,92741.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 92752[98:Res:92748.0,61.1] always3(s29) || -> . % 76.04/76.29 92753[98:SSi:92752.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.29 92754[96:Spt:92753.0,92281.0,92282.0] || until2p7(s28)*+ -> . % 76.04/76.29 92755[96:Spt:92753.0,92281.1] || -> node4(s27)*. % 76.04/76.29 92757[96:MRR:837.0,92755.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.29 92760[96:Res:53.1,92757.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.29 92762[97:Spt:92760.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 92764[97:Res:92762.0,61.1] always3(s27) || -> . % 76.04/76.29 92765[97:SSi:92764.0,78187.0,78190.0,78605.0,92280.0,92755.0] || -> . % 76.04/76.29 92766[97:Spt:92765.0,92760.0,92762.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.29 92767[97:Spt:92765.0,92760.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 92771[97:Res:92767.0,61.1] always3(s28) || -> . % 76.04/76.29 92772[97:SSi:92771.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.29 92773[95:Spt:92772.0,92279.0,92280.0] || until2p7(s27)*+ -> . % 76.04/76.29 92774[95:Spt:92772.0,92279.1] || -> node4(s26)*. % 76.04/76.29 92776[95:MRR:840.0,92774.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.29 92779[95:Res:53.1,92776.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.29 92781[96:Spt:92779.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 92783[96:Res:92781.0,61.1] always3(s26) || -> . % 76.04/76.29 92784[96:SSi:92783.0,78182.0,78186.0,78604.0,92278.0,92774.0] || -> . % 76.04/76.29 92785[96:Spt:92784.0,92779.0,92781.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.29 92786[96:Spt:92784.0,92779.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 92790[96:Res:92786.0,61.1] always3(s27) || -> . % 76.04/76.29 92791[96:SSi:92790.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.29 92792[94:Spt:92791.0,92277.0,92278.0] || until2p7(s26)*+ -> . % 76.04/76.29 92793[94:Spt:92791.0,92277.1] || -> node4(s25)*. % 76.04/76.29 92795[94:MRR:843.0,92793.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.29 92798[94:Res:53.1,92795.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.29 92803[95:Spt:92798.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 92805[95:Res:92803.0,61.1] always3(s25) || -> . % 76.04/76.29 92806[95:SSi:92805.0,78178.0,78181.0,78603.0,92276.0,92793.0] || -> . % 76.04/76.29 92807[95:Spt:92806.0,92798.0,92803.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.29 92808[95:Spt:92806.0,92798.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 92812[95:Res:92808.0,61.1] always3(s26) || -> . % 76.04/76.29 92813[95:SSi:92812.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.29 92814[93:Spt:92813.0,92275.0,92276.0] || until2p7(s25)*+ -> . % 76.04/76.29 92815[93:Spt:92813.0,92275.1] || -> node4(s24)*. % 76.04/76.29 92817[93:MRR:846.0,92815.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.29 92820[93:Res:53.1,92817.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.29 92822[94:Spt:92820.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 92824[94:Res:92822.0,61.1] always3(s24) || -> . % 76.04/76.29 92825[94:SSi:92824.0,78173.0,78177.0,78602.0,92274.0,92815.0] || -> . % 76.04/76.29 92826[94:Spt:92825.0,92820.0,92822.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.29 92827[94:Spt:92825.0,92820.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 92831[94:Res:92827.0,61.1] always3(s25) || -> . % 76.04/76.29 92832[94:SSi:92831.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.29 92833[92:Spt:92832.0,92273.0,92274.0] || until2p7(s24)*+ -> . % 76.04/76.29 92834[92:Spt:92832.0,92273.1] || -> node4(s23)*. % 76.04/76.29 92836[92:MRR:849.0,92834.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.29 92839[92:Res:53.1,92836.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.29 92841[93:Spt:92839.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 92843[93:Res:92841.0,61.1] always3(s23) || -> . % 76.04/76.29 92844[93:SSi:92843.0,78169.0,78172.0,78601.0,92272.0,92834.0] || -> . % 76.04/76.29 92845[93:Spt:92844.0,92839.0,92841.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.29 92846[93:Spt:92844.0,92839.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 92850[93:Res:92846.0,61.1] always3(s24) || -> . % 76.04/76.29 92851[93:SSi:92850.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.29 92852[91:Spt:92851.0,92271.0,92272.0] || until2p7(s23)*+ -> . % 76.04/76.29 92853[91:Spt:92851.0,92271.1] || -> node4(s22)*. % 76.04/76.29 92855[91:MRR:852.0,92853.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.29 92858[91:Res:53.1,92855.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.29 92860[92:Spt:92858.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 92862[92:Res:92860.0,61.1] always3(s22) || -> . % 76.04/76.29 92863[92:SSi:92862.0,78164.0,78168.0,78600.0,92270.0,92853.0] || -> . % 76.04/76.29 92864[92:Spt:92863.0,92858.0,92860.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.29 92865[92:Spt:92863.0,92858.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 92869[92:Res:92865.0,61.1] always3(s23) || -> . % 76.04/76.29 92870[92:SSi:92869.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.29 92871[90:Spt:92870.0,92269.0,92270.0] || until2p7(s22)*+ -> . % 76.04/76.29 92872[90:Spt:92870.0,92269.1] || -> node4(s21)*. % 76.04/76.29 92874[90:MRR:855.0,92872.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.29 92877[90:Res:53.1,92874.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.29 92882[91:Spt:92877.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 92884[91:Res:92882.0,61.1] always3(s21) || -> . % 76.04/76.29 92885[91:SSi:92884.0,78160.0,78163.0,78599.0,92268.0,92872.0] || -> . % 76.04/76.29 92886[91:Spt:92885.0,92877.0,92882.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.29 92887[91:Spt:92885.0,92877.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 92891[91:Res:92887.0,61.1] always3(s22) || -> . % 76.04/76.29 92892[91:SSi:92891.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.29 92893[89:Spt:92892.0,92267.0,92268.0] || until2p7(s21)*+ -> . % 76.04/76.29 92894[89:Spt:92892.0,92267.1] || -> node4(s20)*. % 76.04/76.29 92896[89:MRR:858.0,92894.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.29 92899[89:Res:53.1,92896.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.29 92901[90:Spt:92899.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 92903[90:Res:92901.0,61.1] always3(s20) || -> . % 76.04/76.29 92904[90:SSi:92903.0,78155.0,78159.0,78598.0,92266.0,92894.0] || -> . % 76.04/76.29 92905[90:Spt:92904.0,92899.0,92901.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.29 92906[90:Spt:92904.0,92899.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 92910[90:Res:92906.0,61.1] always3(s21) || -> . % 76.04/76.29 92911[90:SSi:92910.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.29 92912[88:Spt:92911.0,92265.0,92266.0] || until2p7(s20)*+ -> . % 76.04/76.29 92913[88:Spt:92911.0,92265.1] || -> node4(s19)*. % 76.04/76.29 92915[88:MRR:861.0,92913.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.29 92918[88:Res:53.1,92915.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.29 92920[89:Spt:92918.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 92922[89:Res:92920.0,61.1] always3(s19) || -> . % 76.04/76.29 92923[89:SSi:92922.0,78151.0,78154.0,78597.0,92264.0,92913.0] || -> . % 76.04/76.29 92924[89:Spt:92923.0,92918.0,92920.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.29 92925[89:Spt:92923.0,92918.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 92929[89:Res:92925.0,61.1] always3(s20) || -> . % 76.04/76.29 92930[89:SSi:92929.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.29 92931[87:Spt:92930.0,92263.0,92264.0] || until2p7(s19)*+ -> . % 76.04/76.29 92932[87:Spt:92930.0,92263.1] || -> node4(s18)*. % 76.04/76.29 92934[87:MRR:864.0,92932.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.29 92937[87:Res:53.1,92934.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.29 92939[88:Spt:92937.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 92941[88:Res:92939.0,61.1] always3(s18) || -> . % 76.04/76.29 92942[88:SSi:92941.0,78146.0,78150.0,78596.0,92262.0,92932.0] || -> . % 76.04/76.29 92943[88:Spt:92942.0,92937.0,92939.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.29 92944[88:Spt:92942.0,92937.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 92948[88:Res:92944.0,61.1] always3(s19) || -> . % 76.04/76.29 92949[88:SSi:92948.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.29 92950[86:Spt:92949.0,92261.0,92262.0] || until2p7(s18)*+ -> . % 76.04/76.29 92951[86:Spt:92949.0,92261.1] || -> node4(s17)*. % 76.04/76.29 92953[86:MRR:867.0,92951.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.29 92956[86:Res:53.1,92953.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.29 92958[86:MRR:92956.0,92251.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 92963[86:Res:92958.0,61.1] always3(s18) || -> . % 76.04/76.29 92964[86:SSi:92963.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.29 92965[84:Spt:92964.0,92128.0,92131.0] || trans(s49,s17)*+ -> . % 76.04/76.29 92966[84:Spt:92964.0,92128.1,92128.2,92128.3,92128.4,92128.5,92128.6,92128.7,92128.8,92128.9,92128.10,92128.11,92128.12,92128.13,92128.14,92128.15] || -> trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.29 92968[84:MRR:92130.1,92965.0] xuntil6(s49) || -> trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.29 92969[85:Spt:92966.0] || -> trans(s49,s16)*. % 76.04/76.29 92970[85:Res:92969.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s16)*. % 76.04/76.29 92972[85:Res:92969.0,60.0] || -> node2(s49,s16)*. % 76.04/76.29 92973[85:SSi:92970.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s16)*. % 76.04/76.29 92974[85:Res:92972.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)*. % 76.04/76.29 93082[85:SoR:92974.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)*. % 76.04/76.29 93084[85:SoR:93082.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)* xuntil6(s49). % 76.04/76.29 93085[85:SSi:93084.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s16,c_busy)* xuntil6(s49). % 76.04/76.29 93086[86:Spt:93085.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.29 93088[86:Res:93086.0,61.1] always3(s16) || -> . % 76.04/76.29 93089[86:SSi:93088.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.29 93090[86:Spt:93089.0,93085.1,93086.0] || m_main_v_state(s16,c_busy)*+ -> . % 76.04/76.29 93091[86:Spt:93089.0,93085.0,93085.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.29 93095[86:MRR:93082.2,93090.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.29 93096[86:Res:53.1,93091.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.29 93098[86:MRR:93096.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.29 93099[86:MRR:92973.0,93098.0] || -> until2p7(s16)*. % 76.04/76.29 93100[86:MRR:212.0,93099.0] || -> until2p7(s17)* node4(s16). % 76.04/76.29 93101[87:Spt:93100.0] || -> until2p7(s17)*. % 76.04/76.29 93102[87:MRR:213.0,93101.0] || -> until2p7(s18)* node4(s17). % 76.04/76.29 93103[88:Spt:93102.0] || -> until2p7(s18)*. % 76.04/76.29 93104[88:MRR:214.0,93103.0] || -> until2p7(s19)* node4(s18). % 76.04/76.29 93105[89:Spt:93104.0] || -> until2p7(s19)*. % 76.04/76.29 93106[89:MRR:215.0,93105.0] || -> until2p7(s20)* node4(s19). % 76.04/76.29 93107[90:Spt:93106.0] || -> until2p7(s20)*. % 76.04/76.29 93108[90:MRR:216.0,93107.0] || -> until2p7(s21)* node4(s20). % 76.04/76.29 93109[91:Spt:93108.0] || -> until2p7(s21)*. % 76.04/76.29 93110[91:MRR:217.0,93109.0] || -> until2p7(s22)* node4(s21). % 76.04/76.29 93111[92:Spt:93110.0] || -> until2p7(s22)*. % 76.04/76.29 93112[92:MRR:218.0,93111.0] || -> until2p7(s23)* node4(s22). % 76.04/76.29 93113[93:Spt:93112.0] || -> until2p7(s23)*. % 76.04/76.29 93114[93:MRR:219.0,93113.0] || -> until2p7(s24)* node4(s23). % 76.04/76.29 93115[94:Spt:93114.0] || -> until2p7(s24)*. % 76.04/76.29 93116[94:MRR:220.0,93115.0] || -> until2p7(s25)* node4(s24). % 76.04/76.29 93117[95:Spt:93116.0] || -> until2p7(s25)*. % 76.04/76.29 93118[95:MRR:221.0,93117.0] || -> until2p7(s26)* node4(s25). % 76.04/76.29 93119[96:Spt:93118.0] || -> until2p7(s26)*. % 76.04/76.29 93120[96:MRR:222.0,93119.0] || -> until2p7(s27)* node4(s26). % 76.04/76.29 93121[97:Spt:93120.0] || -> until2p7(s27)*. % 76.04/76.29 93122[97:MRR:223.0,93121.0] || -> until2p7(s28)* node4(s27). % 76.04/76.29 93123[98:Spt:93122.0] || -> until2p7(s28)*. % 76.04/76.29 93124[98:MRR:224.0,93123.0] || -> until2p7(s29)* node4(s28). % 76.04/76.29 93125[99:Spt:93124.0] || -> until2p7(s29)*. % 76.04/76.29 93126[99:MRR:225.0,93125.0] || -> until2p7(s30)* node4(s29). % 76.04/76.29 93127[100:Spt:93126.0] || -> until2p7(s30)*. % 76.04/76.29 93128[100:MRR:226.0,93127.0] || -> until2p7(s31)* node4(s30). % 76.04/76.29 93129[101:Spt:93128.0] || -> until2p7(s31)*. % 76.04/76.29 93130[101:MRR:227.0,93129.0] || -> until2p7(s32)* node4(s31). % 76.04/76.29 93131[102:Spt:93130.0] || -> until2p7(s32)*. % 76.04/76.29 93132[102:MRR:228.0,93131.0] || -> until2p7(s33)* node4(s32). % 76.04/76.29 93133[103:Spt:93132.0] || -> until2p7(s33)*. % 76.04/76.29 93134[103:MRR:229.0,93133.0] || -> until2p7(s34)* node4(s33). % 76.04/76.29 93135[104:Spt:93134.0] || -> until2p7(s34)*. % 76.04/76.29 93136[104:MRR:230.0,93135.0] || -> until2p7(s35)* node4(s34). % 76.04/76.29 93137[105:Spt:93136.0] || -> until2p7(s35)*. % 76.04/76.29 93138[105:MRR:231.0,93137.0] || -> until2p7(s36)* node4(s35). % 76.04/76.29 93139[106:Spt:93138.0] || -> until2p7(s36)*. % 76.04/76.29 93140[106:MRR:232.0,93139.0] || -> until2p7(s37)* node4(s36). % 76.04/76.29 93141[107:Spt:93140.0] || -> until2p7(s37)*. % 76.04/76.29 93142[107:MRR:235.0,93141.0] || -> until2p7(s38)* node4(s37). % 76.04/76.29 93143[108:Spt:93142.0] || -> until2p7(s38)*. % 76.04/76.29 93144[108:MRR:236.0,93143.0] || -> until2p7(s39)* node4(s38). % 76.04/76.29 93145[109:Spt:93144.0] || -> until2p7(s39)*. % 76.04/76.29 93146[109:MRR:237.0,93145.0] || -> until2p7(s40)* node4(s39). % 76.04/76.29 93147[110:Spt:93146.0] || -> until2p7(s40)*. % 76.04/76.29 93148[110:MRR:238.0,93147.0] || -> until2p7(s41)* node4(s40). % 76.04/76.29 93149[111:Spt:93148.0] || -> until2p7(s41)*. % 76.04/76.29 93150[111:MRR:239.0,93149.0] || -> until2p7(s42)* node4(s41). % 76.04/76.29 93151[112:Spt:93150.0] || -> until2p7(s42)*. % 76.04/76.29 93152[112:MRR:240.0,93151.0] || -> until2p7(s43)* node4(s42). % 76.04/76.29 93153[113:Spt:93152.0] || -> until2p7(s43)*. % 76.04/76.29 93154[113:MRR:241.0,93153.0] || -> until2p7(s44)* node4(s43). % 76.04/76.29 93155[114:Spt:93154.0] || -> until2p7(s44)*. % 76.04/76.29 93156[114:MRR:539.0,93155.0] || -> until2p7(s45)* node4(s44). % 76.04/76.29 93157[115:Spt:93156.0] || -> until2p7(s45)*. % 76.04/76.29 93158[115:MRR:544.0,93157.0] || -> until2p7(s46)* node4(s45). % 76.04/76.29 93159[116:Spt:93158.0] || -> until2p7(s46)*. % 76.04/76.29 93160[116:MRR:549.0,93159.0] || -> until2p7(s47)* node4(s46). % 76.04/76.29 93161[117:Spt:93160.0] || -> until2p7(s47)*. % 76.04/76.29 93162[117:MRR:554.0,93161.0] || -> until2p7(s48)* node4(s47). % 76.04/76.29 93163[118:Spt:93162.0] || -> until2p7(s48)*. % 76.04/76.29 93164[118:MRR:559.0,93163.0] || -> until2p7(s49)* node4(s48). % 76.04/76.29 93165[119:Spt:93164.0] || -> until2p7(s49)*. % 76.04/76.29 93166[119:MRR:194.0,93165.0] || -> node4(s49)*. % 76.04/76.29 93167[119:MRR:93095.0,93166.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.29 93171[119:Res:53.1,93167.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.29 93173[119:MRR:93171.0,78381.0] || -> . % 76.04/76.29 93174[119:Spt:93173.0,93164.0,93165.0] || until2p7(s49)*+ -> . % 76.04/76.29 93175[119:Spt:93173.0,93164.1] || -> node4(s48)*. % 76.04/76.29 93176[119:MRR:78384.0,93175.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.29 93179[119:Res:53.1,93176.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 93182[119:Res:93179.0,61.1] always3(s48) || -> . % 76.04/76.29 93183[119:SSi:93182.0,78281.0,78387.0,78626.0,93163.0,93175.0] || -> . % 76.04/76.29 93184[118:Spt:93183.0,93162.0,93163.0] || until2p7(s48)*+ -> . % 76.04/76.29 93185[118:Spt:93183.0,93162.1] || -> node4(s47)*. % 76.04/76.29 93187[118:MRR:777.0,93185.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.29 93199[118:Res:53.1,93187.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.29 93201[119:Spt:93199.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 93203[119:Res:93201.0,61.1] always3(s47) || -> . % 76.04/76.29 93204[119:SSi:93203.0,78277.0,78280.0,78625.0,93161.0,93185.0] || -> . % 76.04/76.29 93205[119:Spt:93204.0,93199.0,93201.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.29 93206[119:Spt:93204.0,93199.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 93210[119:Res:93206.0,61.1] always3(s48) || -> . % 76.04/76.29 93211[119:SSi:93210.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.29 93212[117:Spt:93211.0,93160.0,93161.0] || until2p7(s47)*+ -> . % 76.04/76.29 93213[117:Spt:93211.0,93160.1] || -> node4(s46)*. % 76.04/76.29 93215[117:MRR:780.0,93213.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.29 93222[117:Res:53.1,93215.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.29 93227[118:Spt:93222.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 93229[118:Res:93227.0,61.1] always3(s46) || -> . % 76.04/76.29 93230[118:SSi:93229.0,78272.0,78276.0,78624.0,93159.0,93213.0] || -> . % 76.04/76.29 93231[118:Spt:93230.0,93222.0,93227.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.29 93232[118:Spt:93230.0,93222.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 93236[118:Res:93232.0,61.1] always3(s47) || -> . % 76.04/76.29 93237[118:SSi:93236.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.29 93238[116:Spt:93237.0,93158.0,93159.0] || until2p7(s46)*+ -> . % 76.04/76.29 93239[116:Spt:93237.0,93158.1] || -> node4(s45)*. % 76.04/76.29 93241[116:MRR:783.0,93239.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.29 93244[116:Res:53.1,93241.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.29 93246[117:Spt:93244.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 93248[117:Res:93246.0,61.1] always3(s45) || -> . % 76.04/76.29 93249[117:SSi:93248.0,78268.0,78271.0,78623.0,93157.0,93239.0] || -> . % 76.04/76.29 93250[117:Spt:93249.0,93244.0,93246.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.29 93251[117:Spt:93249.0,93244.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 93255[117:Res:93251.0,61.1] always3(s46) || -> . % 76.04/76.29 93256[117:SSi:93255.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.29 93257[115:Spt:93256.0,93156.0,93157.0] || until2p7(s45)*+ -> . % 76.04/76.29 93258[115:Spt:93256.0,93156.1] || -> node4(s44)*. % 76.04/76.29 93260[115:MRR:786.0,93258.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.29 93263[115:Res:53.1,93260.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.29 93265[116:Spt:93263.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 93267[116:Res:93265.0,61.1] always3(s44) || -> . % 76.04/76.29 93268[116:SSi:93267.0,78263.0,78267.0,78622.0,93155.0,93258.0] || -> . % 76.04/76.29 93269[116:Spt:93268.0,93263.0,93265.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.29 93270[116:Spt:93268.0,93263.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 93274[116:Res:93270.0,61.1] always3(s45) || -> . % 76.04/76.29 93275[116:SSi:93274.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.29 93276[114:Spt:93275.0,93154.0,93155.0] || until2p7(s44)*+ -> . % 76.04/76.29 93277[114:Spt:93275.0,93154.1] || -> node4(s43)*. % 76.04/76.29 93279[114:MRR:789.0,93277.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.29 93282[114:Res:53.1,93279.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.29 93284[115:Spt:93282.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 93286[115:Res:93284.0,61.1] always3(s43) || -> . % 76.04/76.29 93287[115:SSi:93286.0,78259.0,78262.0,78621.0,93153.0,93277.0] || -> . % 76.04/76.29 93288[115:Spt:93287.0,93282.0,93284.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.29 93289[115:Spt:93287.0,93282.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 93293[115:Res:93289.0,61.1] always3(s44) || -> . % 76.04/76.29 93294[115:SSi:93293.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.29 93295[113:Spt:93294.0,93152.0,93153.0] || until2p7(s43)*+ -> . % 76.04/76.29 93296[113:Spt:93294.0,93152.1] || -> node4(s42)*. % 76.04/76.29 93298[113:MRR:792.0,93296.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.29 93301[113:Res:53.1,93298.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.29 93306[114:Spt:93301.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 93308[114:Res:93306.0,61.1] always3(s42) || -> . % 76.04/76.29 93309[114:SSi:93308.0,78254.0,78258.0,78620.0,93151.0,93296.0] || -> . % 76.04/76.29 93310[114:Spt:93309.0,93301.0,93306.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.29 93311[114:Spt:93309.0,93301.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 93315[114:Res:93311.0,61.1] always3(s43) || -> . % 76.04/76.29 93316[114:SSi:93315.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.29 93317[112:Spt:93316.0,93150.0,93151.0] || until2p7(s42)*+ -> . % 76.04/76.29 93318[112:Spt:93316.0,93150.1] || -> node4(s41)*. % 76.04/76.29 93320[112:MRR:795.0,93318.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.29 93323[112:Res:53.1,93320.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.29 93325[113:Spt:93323.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 93327[113:Res:93325.0,61.1] always3(s41) || -> . % 76.04/76.29 93328[113:SSi:93327.0,78250.0,78253.0,78619.0,93149.0,93318.0] || -> . % 76.04/76.29 93329[113:Spt:93328.0,93323.0,93325.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.29 93330[113:Spt:93328.0,93323.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 93334[113:Res:93330.0,61.1] always3(s42) || -> . % 76.04/76.29 93335[113:SSi:93334.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.29 93336[111:Spt:93335.0,93148.0,93149.0] || until2p7(s41)*+ -> . % 76.04/76.29 93337[111:Spt:93335.0,93148.1] || -> node4(s40)*. % 76.04/76.29 93339[111:MRR:798.0,93337.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.29 93342[111:Res:53.1,93339.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.29 93344[112:Spt:93342.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 93346[112:Res:93344.0,61.1] always3(s40) || -> . % 76.04/76.29 93347[112:SSi:93346.0,78245.0,78249.0,78618.0,93147.0,93337.0] || -> . % 76.04/76.29 93348[112:Spt:93347.0,93342.0,93344.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.29 93349[112:Spt:93347.0,93342.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 93353[112:Res:93349.0,61.1] always3(s41) || -> . % 76.04/76.29 93354[112:SSi:93353.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.29 93355[110:Spt:93354.0,93146.0,93147.0] || until2p7(s40)*+ -> . % 76.04/76.29 93356[110:Spt:93354.0,93146.1] || -> node4(s39)*. % 76.04/76.29 93358[110:MRR:801.0,93356.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.29 93361[110:Res:53.1,93358.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.29 93363[111:Spt:93361.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 93365[111:Res:93363.0,61.1] always3(s39) || -> . % 76.04/76.29 93366[111:SSi:93365.0,78241.0,78244.0,78617.0,93145.0,93356.0] || -> . % 76.04/76.29 93367[111:Spt:93366.0,93361.0,93363.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.29 93368[111:Spt:93366.0,93361.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 93372[111:Res:93368.0,61.1] always3(s40) || -> . % 76.04/76.29 93373[111:SSi:93372.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.29 93374[109:Spt:93373.0,93144.0,93145.0] || until2p7(s39)*+ -> . % 76.04/76.29 93375[109:Spt:93373.0,93144.1] || -> node4(s38)*. % 76.04/76.29 93377[109:MRR:804.0,93375.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.29 93380[109:Res:53.1,93377.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.29 93385[110:Spt:93380.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 93387[110:Res:93385.0,61.1] always3(s38) || -> . % 76.04/76.29 93388[110:SSi:93387.0,78236.0,78240.0,78616.0,93143.0,93375.0] || -> . % 76.04/76.29 93389[110:Spt:93388.0,93380.0,93385.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.29 93390[110:Spt:93388.0,93380.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 93394[110:Res:93390.0,61.1] always3(s39) || -> . % 76.04/76.29 93395[110:SSi:93394.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.29 93396[108:Spt:93395.0,93142.0,93143.0] || until2p7(s38)*+ -> . % 76.04/76.29 93397[108:Spt:93395.0,93142.1] || -> node4(s37)*. % 76.04/76.29 93399[108:MRR:807.0,93397.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.29 93402[108:Res:53.1,93399.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.29 93404[109:Spt:93402.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 93406[109:Res:93404.0,61.1] always3(s37) || -> . % 76.04/76.29 93407[109:SSi:93406.0,78232.0,78235.0,78615.0,93141.0,93397.0] || -> . % 76.04/76.29 93408[109:Spt:93407.0,93402.0,93404.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.29 93409[109:Spt:93407.0,93402.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 93413[109:Res:93409.0,61.1] always3(s38) || -> . % 76.04/76.29 93414[109:SSi:93413.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.29 93415[107:Spt:93414.0,93140.0,93141.0] || until2p7(s37)*+ -> . % 76.04/76.29 93416[107:Spt:93414.0,93140.1] || -> node4(s36)*. % 76.04/76.29 93418[107:MRR:810.0,93416.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.29 93421[107:Res:53.1,93418.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.29 93423[108:Spt:93421.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 93425[108:Res:93423.0,61.1] always3(s36) || -> . % 76.04/76.29 93426[108:SSi:93425.0,78227.0,78231.0,78614.0,93139.0,93416.0] || -> . % 76.04/76.29 93427[108:Spt:93426.0,93421.0,93423.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.29 93428[108:Spt:93426.0,93421.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 93432[108:Res:93428.0,61.1] always3(s37) || -> . % 76.04/76.29 93433[108:SSi:93432.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.29 93434[106:Spt:93433.0,93138.0,93139.0] || until2p7(s36)*+ -> . % 76.04/76.29 93435[106:Spt:93433.0,93138.1] || -> node4(s35)*. % 76.04/76.29 93437[106:MRR:813.0,93435.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.29 93440[106:Res:53.1,93437.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.29 93442[107:Spt:93440.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 93444[107:Res:93442.0,61.1] always3(s35) || -> . % 76.04/76.29 93445[107:SSi:93444.0,78223.0,78226.0,78613.0,93137.0,93435.0] || -> . % 76.04/76.29 93446[107:Spt:93445.0,93440.0,93442.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.29 93447[107:Spt:93445.0,93440.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 93451[107:Res:93447.0,61.1] always3(s36) || -> . % 76.04/76.29 93452[107:SSi:93451.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.29 93453[105:Spt:93452.0,93136.0,93137.0] || until2p7(s35)*+ -> . % 76.04/76.29 93454[105:Spt:93452.0,93136.1] || -> node4(s34)*. % 76.04/76.29 93456[105:MRR:816.0,93454.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.29 93459[105:Res:53.1,93456.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.29 93464[106:Spt:93459.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 93466[106:Res:93464.0,61.1] always3(s34) || -> . % 76.04/76.29 93467[106:SSi:93466.0,78218.0,78222.0,78612.0,93135.0,93454.0] || -> . % 76.04/76.29 93468[106:Spt:93467.0,93459.0,93464.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.29 93469[106:Spt:93467.0,93459.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 93473[106:Res:93469.0,61.1] always3(s35) || -> . % 76.04/76.29 93474[106:SSi:93473.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.29 93475[104:Spt:93474.0,93134.0,93135.0] || until2p7(s34)*+ -> . % 76.04/76.29 93476[104:Spt:93474.0,93134.1] || -> node4(s33)*. % 76.04/76.29 93478[104:MRR:819.0,93476.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.29 93481[104:Res:53.1,93478.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.29 93483[105:Spt:93481.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 93485[105:Res:93483.0,61.1] always3(s33) || -> . % 76.04/76.29 93486[105:SSi:93485.0,78214.0,78217.0,78611.0,93133.0,93476.0] || -> . % 76.04/76.29 93487[105:Spt:93486.0,93481.0,93483.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.29 93488[105:Spt:93486.0,93481.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 93492[105:Res:93488.0,61.1] always3(s34) || -> . % 76.04/76.29 93493[105:SSi:93492.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.29 93494[103:Spt:93493.0,93132.0,93133.0] || until2p7(s33)*+ -> . % 76.04/76.29 93495[103:Spt:93493.0,93132.1] || -> node4(s32)*. % 76.04/76.29 93497[103:MRR:822.0,93495.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.29 93500[103:Res:53.1,93497.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.29 93502[104:Spt:93500.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 93504[104:Res:93502.0,61.1] always3(s32) || -> . % 76.04/76.29 93505[104:SSi:93504.0,78209.0,78213.0,78610.0,93131.0,93495.0] || -> . % 76.04/76.29 93506[104:Spt:93505.0,93500.0,93502.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.29 93507[104:Spt:93505.0,93500.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 93511[104:Res:93507.0,61.1] always3(s33) || -> . % 76.04/76.29 93512[104:SSi:93511.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.29 93513[102:Spt:93512.0,93130.0,93131.0] || until2p7(s32)*+ -> . % 76.04/76.29 93514[102:Spt:93512.0,93130.1] || -> node4(s31)*. % 76.04/76.29 93516[102:MRR:825.0,93514.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.29 93519[102:Res:53.1,93516.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.29 93521[103:Spt:93519.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 93523[103:Res:93521.0,61.1] always3(s31) || -> . % 76.04/76.29 93524[103:SSi:93523.0,78205.0,78208.0,78609.0,93129.0,93514.0] || -> . % 76.04/76.29 93525[103:Spt:93524.0,93519.0,93521.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.29 93526[103:Spt:93524.0,93519.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 93530[103:Res:93526.0,61.1] always3(s32) || -> . % 76.04/76.29 93531[103:SSi:93530.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.29 93532[101:Spt:93531.0,93128.0,93129.0] || until2p7(s31)*+ -> . % 76.04/76.29 93533[101:Spt:93531.0,93128.1] || -> node4(s30)*. % 76.04/76.29 93535[101:MRR:828.0,93533.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.29 93538[101:Res:53.1,93535.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.29 93543[102:Spt:93538.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 93545[102:Res:93543.0,61.1] always3(s30) || -> . % 76.04/76.29 93546[102:SSi:93545.0,78200.0,78204.0,78608.0,93127.0,93533.0] || -> . % 76.04/76.29 93547[102:Spt:93546.0,93538.0,93543.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.29 93548[102:Spt:93546.0,93538.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 93552[102:Res:93548.0,61.1] always3(s31) || -> . % 76.04/76.29 93553[102:SSi:93552.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.29 93554[100:Spt:93553.0,93126.0,93127.0] || until2p7(s30)*+ -> . % 76.04/76.29 93555[100:Spt:93553.0,93126.1] || -> node4(s29)*. % 76.04/76.29 93557[100:MRR:831.0,93555.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.29 93560[100:Res:53.1,93557.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.29 93562[101:Spt:93560.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 93564[101:Res:93562.0,61.1] always3(s29) || -> . % 76.04/76.29 93565[101:SSi:93564.0,78196.0,78199.0,78607.0,93125.0,93555.0] || -> . % 76.04/76.29 93566[101:Spt:93565.0,93560.0,93562.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.29 93567[101:Spt:93565.0,93560.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 93571[101:Res:93567.0,61.1] always3(s30) || -> . % 76.04/76.29 93572[101:SSi:93571.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.29 93573[99:Spt:93572.0,93124.0,93125.0] || until2p7(s29)*+ -> . % 76.04/76.29 93574[99:Spt:93572.0,93124.1] || -> node4(s28)*. % 76.04/76.29 93576[99:MRR:834.0,93574.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.29 93579[99:Res:53.1,93576.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.29 93581[100:Spt:93579.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 93583[100:Res:93581.0,61.1] always3(s28) || -> . % 76.04/76.29 93584[100:SSi:93583.0,78191.0,78195.0,78606.0,93123.0,93574.0] || -> . % 76.04/76.29 93585[100:Spt:93584.0,93579.0,93581.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.29 93586[100:Spt:93584.0,93579.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 93590[100:Res:93586.0,61.1] always3(s29) || -> . % 76.04/76.29 93591[100:SSi:93590.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.29 93592[98:Spt:93591.0,93122.0,93123.0] || until2p7(s28)*+ -> . % 76.04/76.29 93593[98:Spt:93591.0,93122.1] || -> node4(s27)*. % 76.04/76.29 93595[98:MRR:837.0,93593.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.29 93598[98:Res:53.1,93595.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.29 93600[99:Spt:93598.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 93602[99:Res:93600.0,61.1] always3(s27) || -> . % 76.04/76.29 93603[99:SSi:93602.0,78187.0,78190.0,78605.0,93121.0,93593.0] || -> . % 76.04/76.29 93604[99:Spt:93603.0,93598.0,93600.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.29 93605[99:Spt:93603.0,93598.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 93609[99:Res:93605.0,61.1] always3(s28) || -> . % 76.04/76.29 93610[99:SSi:93609.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.29 93611[97:Spt:93610.0,93120.0,93121.0] || until2p7(s27)*+ -> . % 76.04/76.29 93612[97:Spt:93610.0,93120.1] || -> node4(s26)*. % 76.04/76.29 93614[97:MRR:840.0,93612.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.29 93617[97:Res:53.1,93614.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.29 93622[98:Spt:93617.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 93624[98:Res:93622.0,61.1] always3(s26) || -> . % 76.04/76.29 93625[98:SSi:93624.0,78182.0,78186.0,78604.0,93119.0,93612.0] || -> . % 76.04/76.29 93626[98:Spt:93625.0,93617.0,93622.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.29 93627[98:Spt:93625.0,93617.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 93631[98:Res:93627.0,61.1] always3(s27) || -> . % 76.04/76.29 93632[98:SSi:93631.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.29 93633[96:Spt:93632.0,93118.0,93119.0] || until2p7(s26)*+ -> . % 76.04/76.29 93634[96:Spt:93632.0,93118.1] || -> node4(s25)*. % 76.04/76.29 93636[96:MRR:843.0,93634.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.29 93639[96:Res:53.1,93636.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.29 93641[97:Spt:93639.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 93643[97:Res:93641.0,61.1] always3(s25) || -> . % 76.04/76.29 93644[97:SSi:93643.0,78178.0,78181.0,78603.0,93117.0,93634.0] || -> . % 76.04/76.29 93645[97:Spt:93644.0,93639.0,93641.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.29 93646[97:Spt:93644.0,93639.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 93650[97:Res:93646.0,61.1] always3(s26) || -> . % 76.04/76.29 93651[97:SSi:93650.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.29 93652[95:Spt:93651.0,93116.0,93117.0] || until2p7(s25)*+ -> . % 76.04/76.29 93653[95:Spt:93651.0,93116.1] || -> node4(s24)*. % 76.04/76.29 93655[95:MRR:846.0,93653.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.29 93658[95:Res:53.1,93655.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.29 93660[96:Spt:93658.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 93662[96:Res:93660.0,61.1] always3(s24) || -> . % 76.04/76.29 93663[96:SSi:93662.0,78173.0,78177.0,78602.0,93115.0,93653.0] || -> . % 76.04/76.29 93664[96:Spt:93663.0,93658.0,93660.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.29 93665[96:Spt:93663.0,93658.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 93669[96:Res:93665.0,61.1] always3(s25) || -> . % 76.04/76.29 93670[96:SSi:93669.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.29 93671[94:Spt:93670.0,93114.0,93115.0] || until2p7(s24)*+ -> . % 76.04/76.29 93672[94:Spt:93670.0,93114.1] || -> node4(s23)*. % 76.04/76.29 93674[94:MRR:849.0,93672.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.29 93677[94:Res:53.1,93674.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.29 93679[95:Spt:93677.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 93681[95:Res:93679.0,61.1] always3(s23) || -> . % 76.04/76.29 93682[95:SSi:93681.0,78169.0,78172.0,78601.0,93113.0,93672.0] || -> . % 76.04/76.29 93683[95:Spt:93682.0,93677.0,93679.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.29 93684[95:Spt:93682.0,93677.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 93688[95:Res:93684.0,61.1] always3(s24) || -> . % 76.04/76.29 93689[95:SSi:93688.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.29 93690[93:Spt:93689.0,93112.0,93113.0] || until2p7(s23)*+ -> . % 76.04/76.29 93691[93:Spt:93689.0,93112.1] || -> node4(s22)*. % 76.04/76.29 93693[93:MRR:852.0,93691.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.29 93696[93:Res:53.1,93693.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.29 93701[94:Spt:93696.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 93703[94:Res:93701.0,61.1] always3(s22) || -> . % 76.04/76.29 93704[94:SSi:93703.0,78164.0,78168.0,78600.0,93111.0,93691.0] || -> . % 76.04/76.29 93705[94:Spt:93704.0,93696.0,93701.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.29 93706[94:Spt:93704.0,93696.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 93710[94:Res:93706.0,61.1] always3(s23) || -> . % 76.04/76.29 93711[94:SSi:93710.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.29 93712[92:Spt:93711.0,93110.0,93111.0] || until2p7(s22)*+ -> . % 76.04/76.29 93713[92:Spt:93711.0,93110.1] || -> node4(s21)*. % 76.04/76.29 93715[92:MRR:855.0,93713.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.29 93718[92:Res:53.1,93715.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.29 93720[93:Spt:93718.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 93722[93:Res:93720.0,61.1] always3(s21) || -> . % 76.04/76.29 93723[93:SSi:93722.0,78160.0,78163.0,78599.0,93109.0,93713.0] || -> . % 76.04/76.29 93724[93:Spt:93723.0,93718.0,93720.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.29 93725[93:Spt:93723.0,93718.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 93729[93:Res:93725.0,61.1] always3(s22) || -> . % 76.04/76.29 93730[93:SSi:93729.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.29 93731[91:Spt:93730.0,93108.0,93109.0] || until2p7(s21)*+ -> . % 76.04/76.29 93732[91:Spt:93730.0,93108.1] || -> node4(s20)*. % 76.04/76.29 93734[91:MRR:858.0,93732.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.29 93737[91:Res:53.1,93734.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.29 93739[92:Spt:93737.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 93741[92:Res:93739.0,61.1] always3(s20) || -> . % 76.04/76.29 93742[92:SSi:93741.0,78155.0,78159.0,78598.0,93107.0,93732.0] || -> . % 76.04/76.29 93743[92:Spt:93742.0,93737.0,93739.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.29 93744[92:Spt:93742.0,93737.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 93748[92:Res:93744.0,61.1] always3(s21) || -> . % 76.04/76.29 93749[92:SSi:93748.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.29 93750[90:Spt:93749.0,93106.0,93107.0] || until2p7(s20)*+ -> . % 76.04/76.29 93751[90:Spt:93749.0,93106.1] || -> node4(s19)*. % 76.04/76.29 93753[90:MRR:861.0,93751.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.29 93756[90:Res:53.1,93753.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.29 93758[91:Spt:93756.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 93760[91:Res:93758.0,61.1] always3(s19) || -> . % 76.04/76.29 93761[91:SSi:93760.0,78151.0,78154.0,78597.0,93105.0,93751.0] || -> . % 76.04/76.29 93762[91:Spt:93761.0,93756.0,93758.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.29 93763[91:Spt:93761.0,93756.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 93767[91:Res:93763.0,61.1] always3(s20) || -> . % 76.04/76.29 93768[91:SSi:93767.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.29 93769[89:Spt:93768.0,93104.0,93105.0] || until2p7(s19)*+ -> . % 76.04/76.29 93770[89:Spt:93768.0,93104.1] || -> node4(s18)*. % 76.04/76.29 93772[89:MRR:864.0,93770.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.29 93775[89:Res:53.1,93772.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.29 93780[90:Spt:93775.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 93782[90:Res:93780.0,61.1] always3(s18) || -> . % 76.04/76.29 93783[90:SSi:93782.0,78146.0,78150.0,78596.0,93103.0,93770.0] || -> . % 76.04/76.29 93784[90:Spt:93783.0,93775.0,93780.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.29 93785[90:Spt:93783.0,93775.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 93789[90:Res:93785.0,61.1] always3(s19) || -> . % 76.04/76.29 93790[90:SSi:93789.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.29 93791[88:Spt:93790.0,93102.0,93103.0] || until2p7(s18)*+ -> . % 76.04/76.29 93792[88:Spt:93790.0,93102.1] || -> node4(s17)*. % 76.04/76.29 93794[88:MRR:867.0,93792.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.29 93797[88:Res:53.1,93794.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.29 93799[89:Spt:93797.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 93801[89:Res:93799.0,61.1] always3(s17) || -> . % 76.04/76.29 93802[89:SSi:93801.0,78142.0,78145.0,78595.0,93101.0,93792.0] || -> . % 76.04/76.29 93803[89:Spt:93802.0,93797.0,93799.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.29 93804[89:Spt:93802.0,93797.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 93808[89:Res:93804.0,61.1] always3(s18) || -> . % 76.04/76.29 93809[89:SSi:93808.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.29 93810[87:Spt:93809.0,93100.0,93101.0] || until2p7(s17)*+ -> . % 76.04/76.29 93811[87:Spt:93809.0,93100.1] || -> node4(s16)*. % 76.04/76.29 93813[87:MRR:870.0,93811.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.29 93816[87:Res:53.1,93813.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.29 93818[87:MRR:93816.0,93090.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 93820[87:Res:93818.0,61.1] always3(s17) || -> . % 76.04/76.29 93821[87:SSi:93820.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.29 93822[85:Spt:93821.0,92966.0,92969.0] || trans(s49,s16)*+ -> . % 76.04/76.29 93823[85:Spt:93821.0,92966.1,92966.2,92966.3,92966.4,92966.5,92966.6,92966.7,92966.8,92966.9,92966.10,92966.11,92966.12,92966.13,92966.14] || -> trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.29 93825[85:MRR:92968.1,93822.0] xuntil6(s49) || -> trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.29 93826[86:Spt:93823.0] || -> trans(s49,s15)*. % 76.04/76.29 93827[86:Res:93826.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s15)*. % 76.04/76.29 93829[86:Res:93826.0,60.0] || -> node2(s49,s15)*. % 76.04/76.29 93830[86:SSi:93827.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s15)*. % 76.04/76.29 93831[86:Res:93829.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)*. % 76.04/76.29 93946[86:SoR:93831.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)*. % 76.04/76.29 93948[86:SoR:93946.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)* xuntil6(s49). % 76.04/76.29 93949[86:SSi:93948.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s15,c_busy)* xuntil6(s49). % 76.04/76.29 93950[87:Spt:93949.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.29 93952[87:Res:93950.0,61.1] always3(s15) || -> . % 76.04/76.29 93953[87:SSi:93952.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.29 93954[87:Spt:93953.0,93949.1,93950.0] || m_main_v_state(s15,c_busy)*+ -> . % 76.04/76.29 93955[87:Spt:93953.0,93949.0,93949.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.29 93959[87:MRR:93946.2,93954.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.29 93960[87:Res:53.1,93955.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.29 93962[87:MRR:93960.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.29 93963[87:MRR:93830.0,93962.0] || -> until2p7(s15)*. % 76.04/76.29 93964[87:MRR:211.0,93963.0] || -> until2p7(s16)* node4(s15). % 76.04/76.29 93965[88:Spt:93964.0] || -> until2p7(s16)*. % 76.04/76.29 93966[88:MRR:212.0,93965.0] || -> until2p7(s17)* node4(s16). % 76.04/76.29 93967[89:Spt:93966.0] || -> until2p7(s17)*. % 76.04/76.29 93968[89:MRR:213.0,93967.0] || -> until2p7(s18)* node4(s17). % 76.04/76.29 93969[90:Spt:93968.0] || -> until2p7(s18)*. % 76.04/76.29 93970[90:MRR:214.0,93969.0] || -> until2p7(s19)* node4(s18). % 76.04/76.29 93971[91:Spt:93970.0] || -> until2p7(s19)*. % 76.04/76.29 93972[91:MRR:215.0,93971.0] || -> until2p7(s20)* node4(s19). % 76.04/76.29 93973[92:Spt:93972.0] || -> until2p7(s20)*. % 76.04/76.29 93974[92:MRR:216.0,93973.0] || -> until2p7(s21)* node4(s20). % 76.04/76.29 93975[93:Spt:93974.0] || -> until2p7(s21)*. % 76.04/76.29 93976[93:MRR:217.0,93975.0] || -> until2p7(s22)* node4(s21). % 76.04/76.29 93977[94:Spt:93976.0] || -> until2p7(s22)*. % 76.04/76.29 93978[94:MRR:218.0,93977.0] || -> until2p7(s23)* node4(s22). % 76.04/76.29 93979[95:Spt:93978.0] || -> until2p7(s23)*. % 76.04/76.29 93980[95:MRR:219.0,93979.0] || -> until2p7(s24)* node4(s23). % 76.04/76.29 93981[96:Spt:93980.0] || -> until2p7(s24)*. % 76.04/76.29 93982[96:MRR:220.0,93981.0] || -> until2p7(s25)* node4(s24). % 76.04/76.29 93983[97:Spt:93982.0] || -> until2p7(s25)*. % 76.04/76.29 93984[97:MRR:221.0,93983.0] || -> until2p7(s26)* node4(s25). % 76.04/76.29 93985[98:Spt:93984.0] || -> until2p7(s26)*. % 76.04/76.29 93986[98:MRR:222.0,93985.0] || -> until2p7(s27)* node4(s26). % 76.04/76.29 93987[99:Spt:93986.0] || -> until2p7(s27)*. % 76.04/76.29 93988[99:MRR:223.0,93987.0] || -> until2p7(s28)* node4(s27). % 76.04/76.29 93989[100:Spt:93988.0] || -> until2p7(s28)*. % 76.04/76.29 93990[100:MRR:224.0,93989.0] || -> until2p7(s29)* node4(s28). % 76.04/76.29 93991[101:Spt:93990.0] || -> until2p7(s29)*. % 76.04/76.29 93992[101:MRR:225.0,93991.0] || -> until2p7(s30)* node4(s29). % 76.04/76.29 93993[102:Spt:93992.0] || -> until2p7(s30)*. % 76.04/76.29 93994[102:MRR:226.0,93993.0] || -> until2p7(s31)* node4(s30). % 76.04/76.29 93995[103:Spt:93994.0] || -> until2p7(s31)*. % 76.04/76.29 93996[103:MRR:227.0,93995.0] || -> until2p7(s32)* node4(s31). % 76.04/76.29 93997[104:Spt:93996.0] || -> until2p7(s32)*. % 76.04/76.29 93998[104:MRR:228.0,93997.0] || -> until2p7(s33)* node4(s32). % 76.04/76.29 93999[105:Spt:93998.0] || -> until2p7(s33)*. % 76.04/76.29 94000[105:MRR:229.0,93999.0] || -> until2p7(s34)* node4(s33). % 76.04/76.29 94001[106:Spt:94000.0] || -> until2p7(s34)*. % 76.04/76.29 94002[106:MRR:230.0,94001.0] || -> until2p7(s35)* node4(s34). % 76.04/76.29 94003[107:Spt:94002.0] || -> until2p7(s35)*. % 76.04/76.29 94004[107:MRR:231.0,94003.0] || -> until2p7(s36)* node4(s35). % 76.04/76.29 94005[108:Spt:94004.0] || -> until2p7(s36)*. % 76.04/76.29 94006[108:MRR:232.0,94005.0] || -> until2p7(s37)* node4(s36). % 76.04/76.29 94007[109:Spt:94006.0] || -> until2p7(s37)*. % 76.04/76.29 94008[109:MRR:235.0,94007.0] || -> until2p7(s38)* node4(s37). % 76.04/76.29 94009[110:Spt:94008.0] || -> until2p7(s38)*. % 76.04/76.29 94010[110:MRR:236.0,94009.0] || -> until2p7(s39)* node4(s38). % 76.04/76.29 94011[111:Spt:94010.0] || -> until2p7(s39)*. % 76.04/76.29 94012[111:MRR:237.0,94011.0] || -> until2p7(s40)* node4(s39). % 76.04/76.29 94013[112:Spt:94012.0] || -> until2p7(s40)*. % 76.04/76.29 94014[112:MRR:238.0,94013.0] || -> until2p7(s41)* node4(s40). % 76.04/76.29 94015[113:Spt:94014.0] || -> until2p7(s41)*. % 76.04/76.29 94016[113:MRR:239.0,94015.0] || -> until2p7(s42)* node4(s41). % 76.04/76.29 94017[114:Spt:94016.0] || -> until2p7(s42)*. % 76.04/76.29 94018[114:MRR:240.0,94017.0] || -> until2p7(s43)* node4(s42). % 76.04/76.29 94019[115:Spt:94018.0] || -> until2p7(s43)*. % 76.04/76.29 94020[115:MRR:241.0,94019.0] || -> until2p7(s44)* node4(s43). % 76.04/76.29 94021[116:Spt:94020.0] || -> until2p7(s44)*. % 76.04/76.29 94022[116:MRR:539.0,94021.0] || -> until2p7(s45)* node4(s44). % 76.04/76.29 94023[117:Spt:94022.0] || -> until2p7(s45)*. % 76.04/76.29 94024[117:MRR:544.0,94023.0] || -> until2p7(s46)* node4(s45). % 76.04/76.29 94025[118:Spt:94024.0] || -> until2p7(s46)*. % 76.04/76.29 94026[118:MRR:549.0,94025.0] || -> until2p7(s47)* node4(s46). % 76.04/76.29 94027[119:Spt:94026.0] || -> until2p7(s47)*. % 76.04/76.29 94028[119:MRR:554.0,94027.0] || -> until2p7(s48)* node4(s47). % 76.04/76.29 94029[120:Spt:94028.0] || -> until2p7(s48)*. % 76.04/76.29 94030[120:MRR:559.0,94029.0] || -> until2p7(s49)* node4(s48). % 76.04/76.29 94031[121:Spt:94030.0] || -> until2p7(s49)*. % 76.04/76.29 94032[121:MRR:194.0,94031.0] || -> node4(s49)*. % 76.04/76.29 94033[121:MRR:93959.0,94032.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.29 94034[121:Res:53.1,94033.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.29 94036[121:MRR:94034.0,78381.0] || -> . % 76.04/76.29 94037[121:Spt:94036.0,94030.0,94031.0] || until2p7(s49)*+ -> . % 76.04/76.29 94038[121:Spt:94036.0,94030.1] || -> node4(s48)*. % 76.04/76.29 94039[121:MRR:78384.0,94038.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.29 94042[121:Res:53.1,94039.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 94045[121:Res:94042.0,61.1] always3(s48) || -> . % 76.04/76.29 94046[121:SSi:94045.0,78281.0,78387.0,78626.0,94029.0,94038.0] || -> . % 76.04/76.29 94047[120:Spt:94046.0,94028.0,94029.0] || until2p7(s48)*+ -> . % 76.04/76.29 94048[120:Spt:94046.0,94028.1] || -> node4(s47)*. % 76.04/76.29 94050[120:MRR:777.0,94048.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.29 94065[120:Res:53.1,94050.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.29 94067[121:Spt:94065.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 94069[121:Res:94067.0,61.1] always3(s47) || -> . % 76.04/76.29 94070[121:SSi:94069.0,78277.0,78280.0,78625.0,94027.0,94048.0] || -> . % 76.04/76.29 94071[121:Spt:94070.0,94065.0,94067.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.29 94072[121:Spt:94070.0,94065.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 94076[121:Res:94072.0,61.1] always3(s48) || -> . % 76.04/76.29 94077[121:SSi:94076.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.29 94078[119:Spt:94077.0,94026.0,94027.0] || until2p7(s47)*+ -> . % 76.04/76.29 94079[119:Spt:94077.0,94026.1] || -> node4(s46)*. % 76.04/76.29 94081[119:MRR:780.0,94079.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.29 94091[119:Res:53.1,94081.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.29 94093[120:Spt:94091.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 94095[120:Res:94093.0,61.1] always3(s46) || -> . % 76.04/76.29 94096[120:SSi:94095.0,78272.0,78276.0,78624.0,94025.0,94079.0] || -> . % 76.04/76.29 94097[120:Spt:94096.0,94091.0,94093.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.29 94098[120:Spt:94096.0,94091.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 94102[120:Res:94098.0,61.1] always3(s47) || -> . % 76.04/76.29 94103[120:SSi:94102.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.29 94104[118:Spt:94103.0,94024.0,94025.0] || until2p7(s46)*+ -> . % 76.04/76.29 94105[118:Spt:94103.0,94024.1] || -> node4(s45)*. % 76.04/76.29 94107[118:MRR:783.0,94105.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.29 94110[118:Res:53.1,94107.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.29 94112[119:Spt:94110.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 94114[119:Res:94112.0,61.1] always3(s45) || -> . % 76.04/76.29 94115[119:SSi:94114.0,78268.0,78271.0,78623.0,94023.0,94105.0] || -> . % 76.04/76.29 94116[119:Spt:94115.0,94110.0,94112.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.29 94117[119:Spt:94115.0,94110.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 94121[119:Res:94117.0,61.1] always3(s46) || -> . % 76.04/76.29 94122[119:SSi:94121.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.29 94123[117:Spt:94122.0,94022.0,94023.0] || until2p7(s45)*+ -> . % 76.04/76.29 94124[117:Spt:94122.0,94022.1] || -> node4(s44)*. % 76.04/76.29 94126[117:MRR:786.0,94124.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.29 94129[117:Res:53.1,94126.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.29 94131[118:Spt:94129.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 94133[118:Res:94131.0,61.1] always3(s44) || -> . % 76.04/76.29 94134[118:SSi:94133.0,78263.0,78267.0,78622.0,94021.0,94124.0] || -> . % 76.04/76.29 94135[118:Spt:94134.0,94129.0,94131.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.29 94136[118:Spt:94134.0,94129.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 94140[118:Res:94136.0,61.1] always3(s45) || -> . % 76.04/76.29 94141[118:SSi:94140.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.29 94142[116:Spt:94141.0,94020.0,94021.0] || until2p7(s44)*+ -> . % 76.04/76.29 94143[116:Spt:94141.0,94020.1] || -> node4(s43)*. % 76.04/76.29 94145[116:MRR:789.0,94143.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.29 94148[116:Res:53.1,94145.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.29 94153[117:Spt:94148.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 94155[117:Res:94153.0,61.1] always3(s43) || -> . % 76.04/76.29 94156[117:SSi:94155.0,78259.0,78262.0,78621.0,94019.0,94143.0] || -> . % 76.04/76.29 94157[117:Spt:94156.0,94148.0,94153.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.29 94158[117:Spt:94156.0,94148.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 94162[117:Res:94158.0,61.1] always3(s44) || -> . % 76.04/76.29 94163[117:SSi:94162.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.29 94164[115:Spt:94163.0,94018.0,94019.0] || until2p7(s43)*+ -> . % 76.04/76.29 94165[115:Spt:94163.0,94018.1] || -> node4(s42)*. % 76.04/76.29 94167[115:MRR:792.0,94165.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.29 94170[115:Res:53.1,94167.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.29 94172[116:Spt:94170.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 94174[116:Res:94172.0,61.1] always3(s42) || -> . % 76.04/76.29 94175[116:SSi:94174.0,78254.0,78258.0,78620.0,94017.0,94165.0] || -> . % 76.04/76.29 94176[116:Spt:94175.0,94170.0,94172.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.29 94177[116:Spt:94175.0,94170.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 94181[116:Res:94177.0,61.1] always3(s43) || -> . % 76.04/76.29 94182[116:SSi:94181.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.29 94183[114:Spt:94182.0,94016.0,94017.0] || until2p7(s42)*+ -> . % 76.04/76.29 94184[114:Spt:94182.0,94016.1] || -> node4(s41)*. % 76.04/76.29 94186[114:MRR:795.0,94184.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.29 94189[114:Res:53.1,94186.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.29 94191[115:Spt:94189.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 94193[115:Res:94191.0,61.1] always3(s41) || -> . % 76.04/76.29 94194[115:SSi:94193.0,78250.0,78253.0,78619.0,94015.0,94184.0] || -> . % 76.04/76.29 94195[115:Spt:94194.0,94189.0,94191.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.29 94196[115:Spt:94194.0,94189.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 94200[115:Res:94196.0,61.1] always3(s42) || -> . % 76.04/76.29 94201[115:SSi:94200.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.29 94202[113:Spt:94201.0,94014.0,94015.0] || until2p7(s41)*+ -> . % 76.04/76.29 94203[113:Spt:94201.0,94014.1] || -> node4(s40)*. % 76.04/76.29 94205[113:MRR:798.0,94203.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.29 94208[113:Res:53.1,94205.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.29 94210[114:Spt:94208.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 94212[114:Res:94210.0,61.1] always3(s40) || -> . % 76.04/76.29 94213[114:SSi:94212.0,78245.0,78249.0,78618.0,94013.0,94203.0] || -> . % 76.04/76.29 94214[114:Spt:94213.0,94208.0,94210.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.29 94215[114:Spt:94213.0,94208.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 94219[114:Res:94215.0,61.1] always3(s41) || -> . % 76.04/76.29 94220[114:SSi:94219.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.29 94221[112:Spt:94220.0,94012.0,94013.0] || until2p7(s40)*+ -> . % 76.04/76.29 94222[112:Spt:94220.0,94012.1] || -> node4(s39)*. % 76.04/76.29 94224[112:MRR:801.0,94222.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.29 94227[112:Res:53.1,94224.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.29 94232[113:Spt:94227.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 94234[113:Res:94232.0,61.1] always3(s39) || -> . % 76.04/76.29 94235[113:SSi:94234.0,78241.0,78244.0,78617.0,94011.0,94222.0] || -> . % 76.04/76.29 94236[113:Spt:94235.0,94227.0,94232.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.29 94237[113:Spt:94235.0,94227.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 94241[113:Res:94237.0,61.1] always3(s40) || -> . % 76.04/76.29 94242[113:SSi:94241.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.29 94243[111:Spt:94242.0,94010.0,94011.0] || until2p7(s39)*+ -> . % 76.04/76.29 94244[111:Spt:94242.0,94010.1] || -> node4(s38)*. % 76.04/76.29 94246[111:MRR:804.0,94244.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.29 94249[111:Res:53.1,94246.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.29 94251[112:Spt:94249.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 94253[112:Res:94251.0,61.1] always3(s38) || -> . % 76.04/76.29 94254[112:SSi:94253.0,78236.0,78240.0,78616.0,94009.0,94244.0] || -> . % 76.04/76.29 94255[112:Spt:94254.0,94249.0,94251.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.29 94256[112:Spt:94254.0,94249.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 94260[112:Res:94256.0,61.1] always3(s39) || -> . % 76.04/76.29 94261[112:SSi:94260.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.29 94262[110:Spt:94261.0,94008.0,94009.0] || until2p7(s38)*+ -> . % 76.04/76.29 94263[110:Spt:94261.0,94008.1] || -> node4(s37)*. % 76.04/76.29 94265[110:MRR:807.0,94263.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.29 94268[110:Res:53.1,94265.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.29 94270[111:Spt:94268.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 94272[111:Res:94270.0,61.1] always3(s37) || -> . % 76.04/76.29 94273[111:SSi:94272.0,78232.0,78235.0,78615.0,94007.0,94263.0] || -> . % 76.04/76.29 94274[111:Spt:94273.0,94268.0,94270.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.29 94275[111:Spt:94273.0,94268.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 94279[111:Res:94275.0,61.1] always3(s38) || -> . % 76.04/76.29 94280[111:SSi:94279.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.29 94281[109:Spt:94280.0,94006.0,94007.0] || until2p7(s37)*+ -> . % 76.04/76.29 94282[109:Spt:94280.0,94006.1] || -> node4(s36)*. % 76.04/76.29 94284[109:MRR:810.0,94282.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.29 94287[109:Res:53.1,94284.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.29 94289[110:Spt:94287.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 94291[110:Res:94289.0,61.1] always3(s36) || -> . % 76.04/76.29 94292[110:SSi:94291.0,78227.0,78231.0,78614.0,94005.0,94282.0] || -> . % 76.04/76.29 94293[110:Spt:94292.0,94287.0,94289.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.29 94294[110:Spt:94292.0,94287.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 94298[110:Res:94294.0,61.1] always3(s37) || -> . % 76.04/76.29 94299[110:SSi:94298.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.29 94300[108:Spt:94299.0,94004.0,94005.0] || until2p7(s36)*+ -> . % 76.04/76.29 94301[108:Spt:94299.0,94004.1] || -> node4(s35)*. % 76.04/76.29 94303[108:MRR:813.0,94301.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.29 94306[108:Res:53.1,94303.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.29 94311[109:Spt:94306.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 94313[109:Res:94311.0,61.1] always3(s35) || -> . % 76.04/76.29 94314[109:SSi:94313.0,78223.0,78226.0,78613.0,94003.0,94301.0] || -> . % 76.04/76.29 94315[109:Spt:94314.0,94306.0,94311.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.29 94316[109:Spt:94314.0,94306.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 94320[109:Res:94316.0,61.1] always3(s36) || -> . % 76.04/76.29 94321[109:SSi:94320.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.29 94322[107:Spt:94321.0,94002.0,94003.0] || until2p7(s35)*+ -> . % 76.04/76.29 94323[107:Spt:94321.0,94002.1] || -> node4(s34)*. % 76.04/76.29 94325[107:MRR:816.0,94323.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.29 94328[107:Res:53.1,94325.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.29 94330[108:Spt:94328.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 94332[108:Res:94330.0,61.1] always3(s34) || -> . % 76.04/76.29 94333[108:SSi:94332.0,78218.0,78222.0,78612.0,94001.0,94323.0] || -> . % 76.04/76.29 94334[108:Spt:94333.0,94328.0,94330.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.29 94335[108:Spt:94333.0,94328.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 94339[108:Res:94335.0,61.1] always3(s35) || -> . % 76.04/76.29 94340[108:SSi:94339.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.29 94341[106:Spt:94340.0,94000.0,94001.0] || until2p7(s34)*+ -> . % 76.04/76.29 94342[106:Spt:94340.0,94000.1] || -> node4(s33)*. % 76.04/76.29 94344[106:MRR:819.0,94342.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.29 94347[106:Res:53.1,94344.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.29 94349[107:Spt:94347.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 94351[107:Res:94349.0,61.1] always3(s33) || -> . % 76.04/76.29 94352[107:SSi:94351.0,78214.0,78217.0,78611.0,93999.0,94342.0] || -> . % 76.04/76.29 94353[107:Spt:94352.0,94347.0,94349.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.29 94354[107:Spt:94352.0,94347.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 94358[107:Res:94354.0,61.1] always3(s34) || -> . % 76.04/76.29 94359[107:SSi:94358.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.29 94360[105:Spt:94359.0,93998.0,93999.0] || until2p7(s33)*+ -> . % 76.04/76.29 94361[105:Spt:94359.0,93998.1] || -> node4(s32)*. % 76.04/76.29 94363[105:MRR:822.0,94361.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.29 94366[105:Res:53.1,94363.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.29 94368[106:Spt:94366.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 94370[106:Res:94368.0,61.1] always3(s32) || -> . % 76.04/76.29 94371[106:SSi:94370.0,78209.0,78213.0,78610.0,93997.0,94361.0] || -> . % 76.04/76.29 94372[106:Spt:94371.0,94366.0,94368.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.29 94373[106:Spt:94371.0,94366.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 94377[106:Res:94373.0,61.1] always3(s33) || -> . % 76.04/76.29 94378[106:SSi:94377.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.29 94379[104:Spt:94378.0,93996.0,93997.0] || until2p7(s32)*+ -> . % 76.04/76.29 94380[104:Spt:94378.0,93996.1] || -> node4(s31)*. % 76.04/76.29 94382[104:MRR:825.0,94380.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.29 94385[104:Res:53.1,94382.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.29 94390[105:Spt:94385.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 94392[105:Res:94390.0,61.1] always3(s31) || -> . % 76.04/76.29 94393[105:SSi:94392.0,78205.0,78208.0,78609.0,93995.0,94380.0] || -> . % 76.04/76.29 94394[105:Spt:94393.0,94385.0,94390.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.29 94395[105:Spt:94393.0,94385.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 94399[105:Res:94395.0,61.1] always3(s32) || -> . % 76.04/76.29 94400[105:SSi:94399.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.29 94401[103:Spt:94400.0,93994.0,93995.0] || until2p7(s31)*+ -> . % 76.04/76.29 94402[103:Spt:94400.0,93994.1] || -> node4(s30)*. % 76.04/76.29 94404[103:MRR:828.0,94402.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.29 94407[103:Res:53.1,94404.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.29 94409[104:Spt:94407.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 94411[104:Res:94409.0,61.1] always3(s30) || -> . % 76.04/76.29 94412[104:SSi:94411.0,78200.0,78204.0,78608.0,93993.0,94402.0] || -> . % 76.04/76.29 94413[104:Spt:94412.0,94407.0,94409.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.29 94414[104:Spt:94412.0,94407.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 94418[104:Res:94414.0,61.1] always3(s31) || -> . % 76.04/76.29 94419[104:SSi:94418.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.29 94420[102:Spt:94419.0,93992.0,93993.0] || until2p7(s30)*+ -> . % 76.04/76.29 94421[102:Spt:94419.0,93992.1] || -> node4(s29)*. % 76.04/76.29 94423[102:MRR:831.0,94421.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.29 94426[102:Res:53.1,94423.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.29 94428[103:Spt:94426.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 94430[103:Res:94428.0,61.1] always3(s29) || -> . % 76.04/76.29 94431[103:SSi:94430.0,78196.0,78199.0,78607.0,93991.0,94421.0] || -> . % 76.04/76.29 94432[103:Spt:94431.0,94426.0,94428.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.29 94433[103:Spt:94431.0,94426.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 94437[103:Res:94433.0,61.1] always3(s30) || -> . % 76.04/76.29 94438[103:SSi:94437.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.29 94439[101:Spt:94438.0,93990.0,93991.0] || until2p7(s29)*+ -> . % 76.04/76.29 94440[101:Spt:94438.0,93990.1] || -> node4(s28)*. % 76.04/76.29 94442[101:MRR:834.0,94440.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.29 94445[101:Res:53.1,94442.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.29 94447[102:Spt:94445.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 94449[102:Res:94447.0,61.1] always3(s28) || -> . % 76.04/76.29 94450[102:SSi:94449.0,78191.0,78195.0,78606.0,93989.0,94440.0] || -> . % 76.04/76.29 94451[102:Spt:94450.0,94445.0,94447.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.29 94452[102:Spt:94450.0,94445.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 94456[102:Res:94452.0,61.1] always3(s29) || -> . % 76.04/76.29 94457[102:SSi:94456.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.29 94458[100:Spt:94457.0,93988.0,93989.0] || until2p7(s28)*+ -> . % 76.04/76.29 94459[100:Spt:94457.0,93988.1] || -> node4(s27)*. % 76.04/76.29 94461[100:MRR:837.0,94459.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.29 94464[100:Res:53.1,94461.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.29 94469[101:Spt:94464.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 94471[101:Res:94469.0,61.1] always3(s27) || -> . % 76.04/76.29 94472[101:SSi:94471.0,78187.0,78190.0,78605.0,93987.0,94459.0] || -> . % 76.04/76.29 94473[101:Spt:94472.0,94464.0,94469.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.29 94474[101:Spt:94472.0,94464.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 94478[101:Res:94474.0,61.1] always3(s28) || -> . % 76.04/76.29 94479[101:SSi:94478.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.29 94480[99:Spt:94479.0,93986.0,93987.0] || until2p7(s27)*+ -> . % 76.04/76.29 94481[99:Spt:94479.0,93986.1] || -> node4(s26)*. % 76.04/76.29 94483[99:MRR:840.0,94481.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.29 94486[99:Res:53.1,94483.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.29 94488[100:Spt:94486.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 94490[100:Res:94488.0,61.1] always3(s26) || -> . % 76.04/76.29 94491[100:SSi:94490.0,78182.0,78186.0,78604.0,93985.0,94481.0] || -> . % 76.04/76.29 94492[100:Spt:94491.0,94486.0,94488.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.29 94493[100:Spt:94491.0,94486.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 94497[100:Res:94493.0,61.1] always3(s27) || -> . % 76.04/76.29 94498[100:SSi:94497.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.29 94499[98:Spt:94498.0,93984.0,93985.0] || until2p7(s26)*+ -> . % 76.04/76.29 94500[98:Spt:94498.0,93984.1] || -> node4(s25)*. % 76.04/76.29 94502[98:MRR:843.0,94500.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.29 94505[98:Res:53.1,94502.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.29 94507[99:Spt:94505.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 94509[99:Res:94507.0,61.1] always3(s25) || -> . % 76.04/76.29 94510[99:SSi:94509.0,78178.0,78181.0,78603.0,93983.0,94500.0] || -> . % 76.04/76.29 94511[99:Spt:94510.0,94505.0,94507.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.29 94512[99:Spt:94510.0,94505.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 94516[99:Res:94512.0,61.1] always3(s26) || -> . % 76.04/76.29 94517[99:SSi:94516.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.29 94518[97:Spt:94517.0,93982.0,93983.0] || until2p7(s25)*+ -> . % 76.04/76.29 94519[97:Spt:94517.0,93982.1] || -> node4(s24)*. % 76.04/76.29 94521[97:MRR:846.0,94519.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.29 94524[97:Res:53.1,94521.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.29 94526[98:Spt:94524.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 94528[98:Res:94526.0,61.1] always3(s24) || -> . % 76.04/76.29 94529[98:SSi:94528.0,78173.0,78177.0,78602.0,93981.0,94519.0] || -> . % 76.04/76.29 94530[98:Spt:94529.0,94524.0,94526.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.29 94531[98:Spt:94529.0,94524.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 94535[98:Res:94531.0,61.1] always3(s25) || -> . % 76.04/76.29 94536[98:SSi:94535.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.29 94537[96:Spt:94536.0,93980.0,93981.0] || until2p7(s24)*+ -> . % 76.04/76.29 94538[96:Spt:94536.0,93980.1] || -> node4(s23)*. % 76.04/76.29 94540[96:MRR:849.0,94538.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.29 94543[96:Res:53.1,94540.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.29 94548[97:Spt:94543.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 94550[97:Res:94548.0,61.1] always3(s23) || -> . % 76.04/76.29 94551[97:SSi:94550.0,78169.0,78172.0,78601.0,93979.0,94538.0] || -> . % 76.04/76.29 94552[97:Spt:94551.0,94543.0,94548.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.29 94553[97:Spt:94551.0,94543.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 94557[97:Res:94553.0,61.1] always3(s24) || -> . % 76.04/76.29 94558[97:SSi:94557.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.29 94559[95:Spt:94558.0,93978.0,93979.0] || until2p7(s23)*+ -> . % 76.04/76.29 94560[95:Spt:94558.0,93978.1] || -> node4(s22)*. % 76.04/76.29 94562[95:MRR:852.0,94560.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.29 94565[95:Res:53.1,94562.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.29 94567[96:Spt:94565.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 94569[96:Res:94567.0,61.1] always3(s22) || -> . % 76.04/76.29 94570[96:SSi:94569.0,78164.0,78168.0,78600.0,93977.0,94560.0] || -> . % 76.04/76.29 94571[96:Spt:94570.0,94565.0,94567.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.29 94572[96:Spt:94570.0,94565.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 94576[96:Res:94572.0,61.1] always3(s23) || -> . % 76.04/76.29 94577[96:SSi:94576.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.29 94578[94:Spt:94577.0,93976.0,93977.0] || until2p7(s22)*+ -> . % 76.04/76.29 94579[94:Spt:94577.0,93976.1] || -> node4(s21)*. % 76.04/76.29 94581[94:MRR:855.0,94579.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.29 94584[94:Res:53.1,94581.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.29 94586[95:Spt:94584.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 94588[95:Res:94586.0,61.1] always3(s21) || -> . % 76.04/76.29 94589[95:SSi:94588.0,78160.0,78163.0,78599.0,93975.0,94579.0] || -> . % 76.04/76.29 94590[95:Spt:94589.0,94584.0,94586.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.29 94591[95:Spt:94589.0,94584.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 94595[95:Res:94591.0,61.1] always3(s22) || -> . % 76.04/76.29 94596[95:SSi:94595.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.29 94597[93:Spt:94596.0,93974.0,93975.0] || until2p7(s21)*+ -> . % 76.04/76.29 94598[93:Spt:94596.0,93974.1] || -> node4(s20)*. % 76.04/76.29 94600[93:MRR:858.0,94598.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.29 94603[93:Res:53.1,94600.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.29 94605[94:Spt:94603.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 94607[94:Res:94605.0,61.1] always3(s20) || -> . % 76.04/76.29 94608[94:SSi:94607.0,78155.0,78159.0,78598.0,93973.0,94598.0] || -> . % 76.04/76.29 94609[94:Spt:94608.0,94603.0,94605.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.29 94610[94:Spt:94608.0,94603.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 94614[94:Res:94610.0,61.1] always3(s21) || -> . % 76.04/76.29 94615[94:SSi:94614.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.29 94616[92:Spt:94615.0,93972.0,93973.0] || until2p7(s20)*+ -> . % 76.04/76.29 94617[92:Spt:94615.0,93972.1] || -> node4(s19)*. % 76.04/76.29 94619[92:MRR:861.0,94617.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.29 94622[92:Res:53.1,94619.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.29 94627[93:Spt:94622.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 94629[93:Res:94627.0,61.1] always3(s19) || -> . % 76.04/76.29 94630[93:SSi:94629.0,78151.0,78154.0,78597.0,93971.0,94617.0] || -> . % 76.04/76.29 94631[93:Spt:94630.0,94622.0,94627.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.29 94632[93:Spt:94630.0,94622.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 94636[93:Res:94632.0,61.1] always3(s20) || -> . % 76.04/76.29 94637[93:SSi:94636.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.29 94638[91:Spt:94637.0,93970.0,93971.0] || until2p7(s19)*+ -> . % 76.04/76.29 94639[91:Spt:94637.0,93970.1] || -> node4(s18)*. % 76.04/76.29 94641[91:MRR:864.0,94639.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.29 94644[91:Res:53.1,94641.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.29 94646[92:Spt:94644.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 94648[92:Res:94646.0,61.1] always3(s18) || -> . % 76.04/76.29 94649[92:SSi:94648.0,78146.0,78150.0,78596.0,93969.0,94639.0] || -> . % 76.04/76.29 94650[92:Spt:94649.0,94644.0,94646.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.29 94651[92:Spt:94649.0,94644.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 94655[92:Res:94651.0,61.1] always3(s19) || -> . % 76.04/76.29 94656[92:SSi:94655.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.29 94657[90:Spt:94656.0,93968.0,93969.0] || until2p7(s18)*+ -> . % 76.04/76.29 94658[90:Spt:94656.0,93968.1] || -> node4(s17)*. % 76.04/76.29 94660[90:MRR:867.0,94658.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.29 94663[90:Res:53.1,94660.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.29 94665[91:Spt:94663.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 94667[91:Res:94665.0,61.1] always3(s17) || -> . % 76.04/76.29 94668[91:SSi:94667.0,78142.0,78145.0,78595.0,93967.0,94658.0] || -> . % 76.04/76.29 94669[91:Spt:94668.0,94663.0,94665.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.29 94670[91:Spt:94668.0,94663.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 94674[91:Res:94670.0,61.1] always3(s18) || -> . % 76.04/76.29 94675[91:SSi:94674.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.29 94676[89:Spt:94675.0,93966.0,93967.0] || until2p7(s17)*+ -> . % 76.04/76.29 94677[89:Spt:94675.0,93966.1] || -> node4(s16)*. % 76.04/76.29 94679[89:MRR:870.0,94677.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.29 94682[89:Res:53.1,94679.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.29 94684[90:Spt:94682.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.29 94686[90:Res:94684.0,61.1] always3(s16) || -> . % 76.04/76.29 94687[90:SSi:94686.0,78137.0,78141.0,78594.0,93965.0,94677.0] || -> . % 76.04/76.29 94688[90:Spt:94687.0,94682.0,94684.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.29 94689[90:Spt:94687.0,94682.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 94693[90:Res:94689.0,61.1] always3(s17) || -> . % 76.04/76.29 94694[90:SSi:94693.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.29 94695[88:Spt:94694.0,93964.0,93965.0] || until2p7(s16)*+ -> . % 76.04/76.29 94696[88:Spt:94694.0,93964.1] || -> node4(s15)*. % 76.04/76.29 94698[88:MRR:873.0,94696.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.29 94701[88:Res:53.1,94698.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.29 94703[88:MRR:94701.0,93954.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.29 94708[88:Res:94703.0,61.1] always3(s16) || -> . % 76.04/76.29 94709[88:SSi:94708.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.29 94710[86:Spt:94709.0,93823.0,93826.0] || trans(s49,s15)*+ -> . % 76.04/76.29 94711[86:Spt:94709.0,93823.1,93823.2,93823.3,93823.4,93823.5,93823.6,93823.7,93823.8,93823.9,93823.10,93823.11,93823.12,93823.13] || -> trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.29 94713[86:MRR:93825.1,94710.0] xuntil6(s49) || -> trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.29 94714[87:Spt:94711.0] || -> trans(s49,s14)*. % 76.04/76.29 94715[87:Res:94714.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s14)*. % 76.04/76.29 94717[87:Res:94714.0,60.0] || -> node2(s49,s14)*. % 76.04/76.29 94718[87:SSi:94715.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s14)*. % 76.04/76.29 94719[87:Res:94717.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)*. % 76.04/76.29 94835[87:SoR:94719.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)*. % 76.04/76.29 94837[87:SoR:94835.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)* xuntil6(s49). % 76.04/76.29 94838[87:SSi:94837.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s14,c_busy)* xuntil6(s49). % 76.04/76.29 94839[88:Spt:94838.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.29 94841[88:Res:94839.0,61.1] always3(s14) || -> . % 76.04/76.29 94842[88:SSi:94841.0,78128.0,78132.0,78592.0] || -> . % 76.04/76.29 94843[88:Spt:94842.0,94838.1,94839.0] || m_main_v_state(s14,c_busy)*+ -> . % 76.04/76.29 94844[88:Spt:94842.0,94838.0,94838.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.29 94848[88:MRR:94835.2,94843.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.29 94849[88:Res:53.1,94844.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.29 94851[88:MRR:94849.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.29 94852[88:MRR:94718.0,94851.0] || -> until2p7(s14)*. % 76.04/76.29 94853[88:MRR:210.0,94852.0] || -> until2p7(s15)* node4(s14). % 76.04/76.29 94854[89:Spt:94853.0] || -> until2p7(s15)*. % 76.04/76.29 94855[89:MRR:211.0,94854.0] || -> until2p7(s16)* node4(s15). % 76.04/76.29 94856[90:Spt:94855.0] || -> until2p7(s16)*. % 76.04/76.29 94857[90:MRR:212.0,94856.0] || -> until2p7(s17)* node4(s16). % 76.04/76.29 94858[91:Spt:94857.0] || -> until2p7(s17)*. % 76.04/76.29 94859[91:MRR:213.0,94858.0] || -> until2p7(s18)* node4(s17). % 76.04/76.29 94860[92:Spt:94859.0] || -> until2p7(s18)*. % 76.04/76.29 94861[92:MRR:214.0,94860.0] || -> until2p7(s19)* node4(s18). % 76.04/76.29 94862[93:Spt:94861.0] || -> until2p7(s19)*. % 76.04/76.29 94863[93:MRR:215.0,94862.0] || -> until2p7(s20)* node4(s19). % 76.04/76.29 94864[94:Spt:94863.0] || -> until2p7(s20)*. % 76.04/76.29 94865[94:MRR:216.0,94864.0] || -> until2p7(s21)* node4(s20). % 76.04/76.29 94866[95:Spt:94865.0] || -> until2p7(s21)*. % 76.04/76.29 94867[95:MRR:217.0,94866.0] || -> until2p7(s22)* node4(s21). % 76.04/76.29 94868[96:Spt:94867.0] || -> until2p7(s22)*. % 76.04/76.29 94869[96:MRR:218.0,94868.0] || -> until2p7(s23)* node4(s22). % 76.04/76.29 94870[97:Spt:94869.0] || -> until2p7(s23)*. % 76.04/76.29 94871[97:MRR:219.0,94870.0] || -> until2p7(s24)* node4(s23). % 76.04/76.29 94872[98:Spt:94871.0] || -> until2p7(s24)*. % 76.04/76.29 94873[98:MRR:220.0,94872.0] || -> until2p7(s25)* node4(s24). % 76.04/76.29 94874[99:Spt:94873.0] || -> until2p7(s25)*. % 76.04/76.29 94875[99:MRR:221.0,94874.0] || -> until2p7(s26)* node4(s25). % 76.04/76.29 94876[100:Spt:94875.0] || -> until2p7(s26)*. % 76.04/76.29 94877[100:MRR:222.0,94876.0] || -> until2p7(s27)* node4(s26). % 76.04/76.29 94878[101:Spt:94877.0] || -> until2p7(s27)*. % 76.04/76.29 94879[101:MRR:223.0,94878.0] || -> until2p7(s28)* node4(s27). % 76.04/76.29 94880[102:Spt:94879.0] || -> until2p7(s28)*. % 76.04/76.29 94881[102:MRR:224.0,94880.0] || -> until2p7(s29)* node4(s28). % 76.04/76.29 94882[103:Spt:94881.0] || -> until2p7(s29)*. % 76.04/76.29 94883[103:MRR:225.0,94882.0] || -> until2p7(s30)* node4(s29). % 76.04/76.29 94884[104:Spt:94883.0] || -> until2p7(s30)*. % 76.04/76.29 94885[104:MRR:226.0,94884.0] || -> until2p7(s31)* node4(s30). % 76.04/76.29 94886[105:Spt:94885.0] || -> until2p7(s31)*. % 76.04/76.29 94887[105:MRR:227.0,94886.0] || -> until2p7(s32)* node4(s31). % 76.04/76.29 94888[106:Spt:94887.0] || -> until2p7(s32)*. % 76.04/76.29 94889[106:MRR:228.0,94888.0] || -> until2p7(s33)* node4(s32). % 76.04/76.29 94890[107:Spt:94889.0] || -> until2p7(s33)*. % 76.04/76.29 94891[107:MRR:229.0,94890.0] || -> until2p7(s34)* node4(s33). % 76.04/76.29 94892[108:Spt:94891.0] || -> until2p7(s34)*. % 76.04/76.29 94893[108:MRR:230.0,94892.0] || -> until2p7(s35)* node4(s34). % 76.04/76.29 94894[109:Spt:94893.0] || -> until2p7(s35)*. % 76.04/76.29 94895[109:MRR:231.0,94894.0] || -> until2p7(s36)* node4(s35). % 76.04/76.29 94896[110:Spt:94895.0] || -> until2p7(s36)*. % 76.04/76.29 94897[110:MRR:232.0,94896.0] || -> until2p7(s37)* node4(s36). % 76.04/76.29 94898[111:Spt:94897.0] || -> until2p7(s37)*. % 76.04/76.29 94899[111:MRR:235.0,94898.0] || -> until2p7(s38)* node4(s37). % 76.04/76.29 94900[112:Spt:94899.0] || -> until2p7(s38)*. % 76.04/76.29 94901[112:MRR:236.0,94900.0] || -> until2p7(s39)* node4(s38). % 76.04/76.29 94902[113:Spt:94901.0] || -> until2p7(s39)*. % 76.04/76.29 94903[113:MRR:237.0,94902.0] || -> until2p7(s40)* node4(s39). % 76.04/76.29 94904[114:Spt:94903.0] || -> until2p7(s40)*. % 76.04/76.29 94905[114:MRR:238.0,94904.0] || -> until2p7(s41)* node4(s40). % 76.04/76.29 94906[115:Spt:94905.0] || -> until2p7(s41)*. % 76.04/76.29 94907[115:MRR:239.0,94906.0] || -> until2p7(s42)* node4(s41). % 76.04/76.29 94908[116:Spt:94907.0] || -> until2p7(s42)*. % 76.04/76.29 94909[116:MRR:240.0,94908.0] || -> until2p7(s43)* node4(s42). % 76.04/76.29 94910[117:Spt:94909.0] || -> until2p7(s43)*. % 76.04/76.29 94911[117:MRR:241.0,94910.0] || -> until2p7(s44)* node4(s43). % 76.04/76.29 94912[118:Spt:94911.0] || -> until2p7(s44)*. % 76.04/76.29 94913[118:MRR:539.0,94912.0] || -> until2p7(s45)* node4(s44). % 76.04/76.29 94914[119:Spt:94913.0] || -> until2p7(s45)*. % 76.04/76.29 94915[119:MRR:544.0,94914.0] || -> until2p7(s46)* node4(s45). % 76.04/76.29 94916[120:Spt:94915.0] || -> until2p7(s46)*. % 76.04/76.29 94917[120:MRR:549.0,94916.0] || -> until2p7(s47)* node4(s46). % 76.04/76.29 94918[121:Spt:94917.0] || -> until2p7(s47)*. % 76.04/76.29 94919[121:MRR:554.0,94918.0] || -> until2p7(s48)* node4(s47). % 76.04/76.29 94920[122:Spt:94919.0] || -> until2p7(s48)*. % 76.04/76.29 94921[122:MRR:559.0,94920.0] || -> until2p7(s49)* node4(s48). % 76.04/76.29 94922[123:Spt:94921.0] || -> until2p7(s49)*. % 76.04/76.29 94923[123:MRR:194.0,94922.0] || -> node4(s49)*. % 76.04/76.29 94924[123:MRR:94848.0,94923.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.29 94925[123:Res:53.1,94924.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.29 94927[123:MRR:94925.0,78381.0] || -> . % 76.04/76.29 94928[123:Spt:94927.0,94921.0,94922.0] || until2p7(s49)*+ -> . % 76.04/76.29 94929[123:Spt:94927.0,94921.1] || -> node4(s48)*. % 76.04/76.29 94930[123:MRR:78384.0,94929.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.29 94933[123:Res:53.1,94930.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 94936[123:Res:94933.0,61.1] always3(s48) || -> . % 76.04/76.29 94937[123:SSi:94936.0,78281.0,78387.0,78626.0,94920.0,94929.0] || -> . % 76.04/76.29 94938[122:Spt:94937.0,94919.0,94920.0] || until2p7(s48)*+ -> . % 76.04/76.29 94939[122:Spt:94937.0,94919.1] || -> node4(s47)*. % 76.04/76.29 94941[122:MRR:777.0,94939.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.29 94956[122:Res:53.1,94941.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.29 94958[123:Spt:94956.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 94960[123:Res:94958.0,61.1] always3(s47) || -> . % 76.04/76.29 94961[123:SSi:94960.0,78277.0,78280.0,78625.0,94918.0,94939.0] || -> . % 76.04/76.29 94962[123:Spt:94961.0,94956.0,94958.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.29 94963[123:Spt:94961.0,94956.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 94967[123:Res:94963.0,61.1] always3(s48) || -> . % 76.04/76.29 94968[123:SSi:94967.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.29 94969[121:Spt:94968.0,94917.0,94918.0] || until2p7(s47)*+ -> . % 76.04/76.29 94970[121:Spt:94968.0,94917.1] || -> node4(s46)*. % 76.04/76.29 94972[121:MRR:780.0,94970.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.29 94982[121:Res:53.1,94972.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.29 94984[122:Spt:94982.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 94986[122:Res:94984.0,61.1] always3(s46) || -> . % 76.04/76.29 94987[122:SSi:94986.0,78272.0,78276.0,78624.0,94916.0,94970.0] || -> . % 76.04/76.29 94988[122:Spt:94987.0,94982.0,94984.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.29 94989[122:Spt:94987.0,94982.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 94993[122:Res:94989.0,61.1] always3(s47) || -> . % 76.04/76.29 94994[122:SSi:94993.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.29 94995[120:Spt:94994.0,94915.0,94916.0] || until2p7(s46)*+ -> . % 76.04/76.29 94996[120:Spt:94994.0,94915.1] || -> node4(s45)*. % 76.04/76.29 94998[120:MRR:783.0,94996.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.29 95001[120:Res:53.1,94998.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.29 95003[121:Spt:95001.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 95005[121:Res:95003.0,61.1] always3(s45) || -> . % 76.04/76.29 95006[121:SSi:95005.0,78268.0,78271.0,78623.0,94914.0,94996.0] || -> . % 76.04/76.29 95007[121:Spt:95006.0,95001.0,95003.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.29 95008[121:Spt:95006.0,95001.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 95012[121:Res:95008.0,61.1] always3(s46) || -> . % 76.04/76.29 95013[121:SSi:95012.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.29 95014[119:Spt:95013.0,94913.0,94914.0] || until2p7(s45)*+ -> . % 76.04/76.29 95015[119:Spt:95013.0,94913.1] || -> node4(s44)*. % 76.04/76.29 95017[119:MRR:786.0,95015.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.29 95020[119:Res:53.1,95017.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.29 95022[120:Spt:95020.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 95024[120:Res:95022.0,61.1] always3(s44) || -> . % 76.04/76.29 95025[120:SSi:95024.0,78263.0,78267.0,78622.0,94912.0,95015.0] || -> . % 76.04/76.29 95026[120:Spt:95025.0,95020.0,95022.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.29 95027[120:Spt:95025.0,95020.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 95031[120:Res:95027.0,61.1] always3(s45) || -> . % 76.04/76.29 95032[120:SSi:95031.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.29 95033[118:Spt:95032.0,94911.0,94912.0] || until2p7(s44)*+ -> . % 76.04/76.29 95034[118:Spt:95032.0,94911.1] || -> node4(s43)*. % 76.04/76.29 95036[118:MRR:789.0,95034.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.29 95039[118:Res:53.1,95036.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.29 95044[119:Spt:95039.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 95046[119:Res:95044.0,61.1] always3(s43) || -> . % 76.04/76.29 95047[119:SSi:95046.0,78259.0,78262.0,78621.0,94910.0,95034.0] || -> . % 76.04/76.29 95048[119:Spt:95047.0,95039.0,95044.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.29 95049[119:Spt:95047.0,95039.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 95053[119:Res:95049.0,61.1] always3(s44) || -> . % 76.04/76.29 95054[119:SSi:95053.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.29 95055[117:Spt:95054.0,94909.0,94910.0] || until2p7(s43)*+ -> . % 76.04/76.29 95056[117:Spt:95054.0,94909.1] || -> node4(s42)*. % 76.04/76.29 95058[117:MRR:792.0,95056.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.29 95061[117:Res:53.1,95058.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.29 95063[118:Spt:95061.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 95065[118:Res:95063.0,61.1] always3(s42) || -> . % 76.04/76.29 95066[118:SSi:95065.0,78254.0,78258.0,78620.0,94908.0,95056.0] || -> . % 76.04/76.29 95067[118:Spt:95066.0,95061.0,95063.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.29 95068[118:Spt:95066.0,95061.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 95072[118:Res:95068.0,61.1] always3(s43) || -> . % 76.04/76.29 95073[118:SSi:95072.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.29 95074[116:Spt:95073.0,94907.0,94908.0] || until2p7(s42)*+ -> . % 76.04/76.29 95075[116:Spt:95073.0,94907.1] || -> node4(s41)*. % 76.04/76.29 95077[116:MRR:795.0,95075.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.29 95080[116:Res:53.1,95077.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.29 95082[117:Spt:95080.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 95084[117:Res:95082.0,61.1] always3(s41) || -> . % 76.04/76.29 95085[117:SSi:95084.0,78250.0,78253.0,78619.0,94906.0,95075.0] || -> . % 76.04/76.29 95086[117:Spt:95085.0,95080.0,95082.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.29 95087[117:Spt:95085.0,95080.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 95091[117:Res:95087.0,61.1] always3(s42) || -> . % 76.04/76.29 95092[117:SSi:95091.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.29 95093[115:Spt:95092.0,94905.0,94906.0] || until2p7(s41)*+ -> . % 76.04/76.29 95094[115:Spt:95092.0,94905.1] || -> node4(s40)*. % 76.04/76.29 95096[115:MRR:798.0,95094.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.29 95099[115:Res:53.1,95096.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.29 95101[116:Spt:95099.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 95103[116:Res:95101.0,61.1] always3(s40) || -> . % 76.04/76.29 95104[116:SSi:95103.0,78245.0,78249.0,78618.0,94904.0,95094.0] || -> . % 76.04/76.29 95105[116:Spt:95104.0,95099.0,95101.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.29 95106[116:Spt:95104.0,95099.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 95110[116:Res:95106.0,61.1] always3(s41) || -> . % 76.04/76.29 95111[116:SSi:95110.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.29 95112[114:Spt:95111.0,94903.0,94904.0] || until2p7(s40)*+ -> . % 76.04/76.29 95113[114:Spt:95111.0,94903.1] || -> node4(s39)*. % 76.04/76.29 95115[114:MRR:801.0,95113.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.29 95118[114:Res:53.1,95115.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.29 95123[115:Spt:95118.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 95125[115:Res:95123.0,61.1] always3(s39) || -> . % 76.04/76.29 95126[115:SSi:95125.0,78241.0,78244.0,78617.0,94902.0,95113.0] || -> . % 76.04/76.29 95127[115:Spt:95126.0,95118.0,95123.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.29 95128[115:Spt:95126.0,95118.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 95132[115:Res:95128.0,61.1] always3(s40) || -> . % 76.04/76.29 95133[115:SSi:95132.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.29 95134[113:Spt:95133.0,94901.0,94902.0] || until2p7(s39)*+ -> . % 76.04/76.29 95135[113:Spt:95133.0,94901.1] || -> node4(s38)*. % 76.04/76.29 95137[113:MRR:804.0,95135.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.29 95140[113:Res:53.1,95137.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.29 95142[114:Spt:95140.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 95144[114:Res:95142.0,61.1] always3(s38) || -> . % 76.04/76.29 95145[114:SSi:95144.0,78236.0,78240.0,78616.0,94900.0,95135.0] || -> . % 76.04/76.29 95146[114:Spt:95145.0,95140.0,95142.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.29 95147[114:Spt:95145.0,95140.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 95151[114:Res:95147.0,61.1] always3(s39) || -> . % 76.04/76.29 95152[114:SSi:95151.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.29 95153[112:Spt:95152.0,94899.0,94900.0] || until2p7(s38)*+ -> . % 76.04/76.29 95154[112:Spt:95152.0,94899.1] || -> node4(s37)*. % 76.04/76.29 95156[112:MRR:807.0,95154.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.29 95159[112:Res:53.1,95156.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.29 95161[113:Spt:95159.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 95163[113:Res:95161.0,61.1] always3(s37) || -> . % 76.04/76.29 95164[113:SSi:95163.0,78232.0,78235.0,78615.0,94898.0,95154.0] || -> . % 76.04/76.29 95165[113:Spt:95164.0,95159.0,95161.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.29 95166[113:Spt:95164.0,95159.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 95170[113:Res:95166.0,61.1] always3(s38) || -> . % 76.04/76.29 95171[113:SSi:95170.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.29 95172[111:Spt:95171.0,94897.0,94898.0] || until2p7(s37)*+ -> . % 76.04/76.29 95173[111:Spt:95171.0,94897.1] || -> node4(s36)*. % 76.04/76.29 95175[111:MRR:810.0,95173.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.29 95178[111:Res:53.1,95175.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.29 95180[112:Spt:95178.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 95182[112:Res:95180.0,61.1] always3(s36) || -> . % 76.04/76.29 95183[112:SSi:95182.0,78227.0,78231.0,78614.0,94896.0,95173.0] || -> . % 76.04/76.29 95184[112:Spt:95183.0,95178.0,95180.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.29 95185[112:Spt:95183.0,95178.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 95189[112:Res:95185.0,61.1] always3(s37) || -> . % 76.04/76.29 95190[112:SSi:95189.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.29 95191[110:Spt:95190.0,94895.0,94896.0] || until2p7(s36)*+ -> . % 76.04/76.29 95192[110:Spt:95190.0,94895.1] || -> node4(s35)*. % 76.04/76.29 95194[110:MRR:813.0,95192.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.29 95197[110:Res:53.1,95194.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.29 95202[111:Spt:95197.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 95204[111:Res:95202.0,61.1] always3(s35) || -> . % 76.04/76.29 95205[111:SSi:95204.0,78223.0,78226.0,78613.0,94894.0,95192.0] || -> . % 76.04/76.29 95206[111:Spt:95205.0,95197.0,95202.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.29 95207[111:Spt:95205.0,95197.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 95211[111:Res:95207.0,61.1] always3(s36) || -> . % 76.04/76.29 95212[111:SSi:95211.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.29 95213[109:Spt:95212.0,94893.0,94894.0] || until2p7(s35)*+ -> . % 76.04/76.29 95214[109:Spt:95212.0,94893.1] || -> node4(s34)*. % 76.04/76.29 95216[109:MRR:816.0,95214.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.29 95219[109:Res:53.1,95216.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.29 95221[110:Spt:95219.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 95223[110:Res:95221.0,61.1] always3(s34) || -> . % 76.04/76.29 95224[110:SSi:95223.0,78218.0,78222.0,78612.0,94892.0,95214.0] || -> . % 76.04/76.29 95225[110:Spt:95224.0,95219.0,95221.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.29 95226[110:Spt:95224.0,95219.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 95230[110:Res:95226.0,61.1] always3(s35) || -> . % 76.04/76.29 95231[110:SSi:95230.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.29 95232[108:Spt:95231.0,94891.0,94892.0] || until2p7(s34)*+ -> . % 76.04/76.29 95233[108:Spt:95231.0,94891.1] || -> node4(s33)*. % 76.04/76.29 95235[108:MRR:819.0,95233.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.29 95238[108:Res:53.1,95235.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.29 95240[109:Spt:95238.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 95242[109:Res:95240.0,61.1] always3(s33) || -> . % 76.04/76.29 95243[109:SSi:95242.0,78214.0,78217.0,78611.0,94890.0,95233.0] || -> . % 76.04/76.29 95244[109:Spt:95243.0,95238.0,95240.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.29 95245[109:Spt:95243.0,95238.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 95249[109:Res:95245.0,61.1] always3(s34) || -> . % 76.04/76.29 95250[109:SSi:95249.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.29 95251[107:Spt:95250.0,94889.0,94890.0] || until2p7(s33)*+ -> . % 76.04/76.29 95252[107:Spt:95250.0,94889.1] || -> node4(s32)*. % 76.04/76.29 95254[107:MRR:822.0,95252.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.29 95257[107:Res:53.1,95254.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.29 95259[108:Spt:95257.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 95261[108:Res:95259.0,61.1] always3(s32) || -> . % 76.04/76.29 95262[108:SSi:95261.0,78209.0,78213.0,78610.0,94888.0,95252.0] || -> . % 76.04/76.29 95263[108:Spt:95262.0,95257.0,95259.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.29 95264[108:Spt:95262.0,95257.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 95268[108:Res:95264.0,61.1] always3(s33) || -> . % 76.04/76.29 95269[108:SSi:95268.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.29 95270[106:Spt:95269.0,94887.0,94888.0] || until2p7(s32)*+ -> . % 76.04/76.29 95271[106:Spt:95269.0,94887.1] || -> node4(s31)*. % 76.04/76.29 95273[106:MRR:825.0,95271.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.29 95276[106:Res:53.1,95273.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.29 95281[107:Spt:95276.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 95283[107:Res:95281.0,61.1] always3(s31) || -> . % 76.04/76.29 95284[107:SSi:95283.0,78205.0,78208.0,78609.0,94886.0,95271.0] || -> . % 76.04/76.29 95285[107:Spt:95284.0,95276.0,95281.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.29 95286[107:Spt:95284.0,95276.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 95290[107:Res:95286.0,61.1] always3(s32) || -> . % 76.04/76.29 95291[107:SSi:95290.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.29 95292[105:Spt:95291.0,94885.0,94886.0] || until2p7(s31)*+ -> . % 76.04/76.29 95293[105:Spt:95291.0,94885.1] || -> node4(s30)*. % 76.04/76.29 95295[105:MRR:828.0,95293.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.29 95298[105:Res:53.1,95295.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.29 95300[106:Spt:95298.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 95302[106:Res:95300.0,61.1] always3(s30) || -> . % 76.04/76.29 95303[106:SSi:95302.0,78200.0,78204.0,78608.0,94884.0,95293.0] || -> . % 76.04/76.29 95304[106:Spt:95303.0,95298.0,95300.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.29 95305[106:Spt:95303.0,95298.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 95309[106:Res:95305.0,61.1] always3(s31) || -> . % 76.04/76.29 95310[106:SSi:95309.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.29 95311[104:Spt:95310.0,94883.0,94884.0] || until2p7(s30)*+ -> . % 76.04/76.29 95312[104:Spt:95310.0,94883.1] || -> node4(s29)*. % 76.04/76.29 95314[104:MRR:831.0,95312.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.29 95317[104:Res:53.1,95314.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.29 95319[105:Spt:95317.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 95321[105:Res:95319.0,61.1] always3(s29) || -> . % 76.04/76.29 95322[105:SSi:95321.0,78196.0,78199.0,78607.0,94882.0,95312.0] || -> . % 76.04/76.29 95323[105:Spt:95322.0,95317.0,95319.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.29 95324[105:Spt:95322.0,95317.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 95328[105:Res:95324.0,61.1] always3(s30) || -> . % 76.04/76.29 95329[105:SSi:95328.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.29 95330[103:Spt:95329.0,94881.0,94882.0] || until2p7(s29)*+ -> . % 76.04/76.29 95331[103:Spt:95329.0,94881.1] || -> node4(s28)*. % 76.04/76.29 95333[103:MRR:834.0,95331.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.29 95336[103:Res:53.1,95333.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.29 95338[104:Spt:95336.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 95340[104:Res:95338.0,61.1] always3(s28) || -> . % 76.04/76.29 95341[104:SSi:95340.0,78191.0,78195.0,78606.0,94880.0,95331.0] || -> . % 76.04/76.29 95342[104:Spt:95341.0,95336.0,95338.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.29 95343[104:Spt:95341.0,95336.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 95347[104:Res:95343.0,61.1] always3(s29) || -> . % 76.04/76.29 95348[104:SSi:95347.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.29 95349[102:Spt:95348.0,94879.0,94880.0] || until2p7(s28)*+ -> . % 76.04/76.29 95350[102:Spt:95348.0,94879.1] || -> node4(s27)*. % 76.04/76.29 95352[102:MRR:837.0,95350.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.29 95355[102:Res:53.1,95352.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.29 95360[103:Spt:95355.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 95362[103:Res:95360.0,61.1] always3(s27) || -> . % 76.04/76.29 95363[103:SSi:95362.0,78187.0,78190.0,78605.0,94878.0,95350.0] || -> . % 76.04/76.29 95364[103:Spt:95363.0,95355.0,95360.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.29 95365[103:Spt:95363.0,95355.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 95369[103:Res:95365.0,61.1] always3(s28) || -> . % 76.04/76.29 95370[103:SSi:95369.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.29 95371[101:Spt:95370.0,94877.0,94878.0] || until2p7(s27)*+ -> . % 76.04/76.29 95372[101:Spt:95370.0,94877.1] || -> node4(s26)*. % 76.04/76.29 95374[101:MRR:840.0,95372.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.29 95377[101:Res:53.1,95374.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.29 95379[102:Spt:95377.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 95381[102:Res:95379.0,61.1] always3(s26) || -> . % 76.04/76.29 95382[102:SSi:95381.0,78182.0,78186.0,78604.0,94876.0,95372.0] || -> . % 76.04/76.29 95383[102:Spt:95382.0,95377.0,95379.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.29 95384[102:Spt:95382.0,95377.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 95388[102:Res:95384.0,61.1] always3(s27) || -> . % 76.04/76.29 95389[102:SSi:95388.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.29 95390[100:Spt:95389.0,94875.0,94876.0] || until2p7(s26)*+ -> . % 76.04/76.29 95391[100:Spt:95389.0,94875.1] || -> node4(s25)*. % 76.04/76.29 95393[100:MRR:843.0,95391.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.29 95396[100:Res:53.1,95393.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.29 95398[101:Spt:95396.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 95400[101:Res:95398.0,61.1] always3(s25) || -> . % 76.04/76.29 95401[101:SSi:95400.0,78178.0,78181.0,78603.0,94874.0,95391.0] || -> . % 76.04/76.29 95402[101:Spt:95401.0,95396.0,95398.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.29 95403[101:Spt:95401.0,95396.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 95407[101:Res:95403.0,61.1] always3(s26) || -> . % 76.04/76.29 95408[101:SSi:95407.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.29 95409[99:Spt:95408.0,94873.0,94874.0] || until2p7(s25)*+ -> . % 76.04/76.29 95410[99:Spt:95408.0,94873.1] || -> node4(s24)*. % 76.04/76.29 95412[99:MRR:846.0,95410.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.29 95415[99:Res:53.1,95412.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.29 95417[100:Spt:95415.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 95419[100:Res:95417.0,61.1] always3(s24) || -> . % 76.04/76.29 95420[100:SSi:95419.0,78173.0,78177.0,78602.0,94872.0,95410.0] || -> . % 76.04/76.29 95421[100:Spt:95420.0,95415.0,95417.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.29 95422[100:Spt:95420.0,95415.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 95426[100:Res:95422.0,61.1] always3(s25) || -> . % 76.04/76.29 95427[100:SSi:95426.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.29 95428[98:Spt:95427.0,94871.0,94872.0] || until2p7(s24)*+ -> . % 76.04/76.29 95429[98:Spt:95427.0,94871.1] || -> node4(s23)*. % 76.04/76.29 95431[98:MRR:849.0,95429.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.29 95434[98:Res:53.1,95431.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.29 95439[99:Spt:95434.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 95441[99:Res:95439.0,61.1] always3(s23) || -> . % 76.04/76.29 95442[99:SSi:95441.0,78169.0,78172.0,78601.0,94870.0,95429.0] || -> . % 76.04/76.29 95443[99:Spt:95442.0,95434.0,95439.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.29 95444[99:Spt:95442.0,95434.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 95448[99:Res:95444.0,61.1] always3(s24) || -> . % 76.04/76.29 95449[99:SSi:95448.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.29 95450[97:Spt:95449.0,94869.0,94870.0] || until2p7(s23)*+ -> . % 76.04/76.29 95451[97:Spt:95449.0,94869.1] || -> node4(s22)*. % 76.04/76.29 95453[97:MRR:852.0,95451.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.29 95456[97:Res:53.1,95453.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.29 95458[98:Spt:95456.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 95460[98:Res:95458.0,61.1] always3(s22) || -> . % 76.04/76.29 95461[98:SSi:95460.0,78164.0,78168.0,78600.0,94868.0,95451.0] || -> . % 76.04/76.29 95462[98:Spt:95461.0,95456.0,95458.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.29 95463[98:Spt:95461.0,95456.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 95467[98:Res:95463.0,61.1] always3(s23) || -> . % 76.04/76.29 95468[98:SSi:95467.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.29 95469[96:Spt:95468.0,94867.0,94868.0] || until2p7(s22)*+ -> . % 76.04/76.29 95470[96:Spt:95468.0,94867.1] || -> node4(s21)*. % 76.04/76.29 95472[96:MRR:855.0,95470.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.29 95475[96:Res:53.1,95472.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.29 95477[97:Spt:95475.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 95479[97:Res:95477.0,61.1] always3(s21) || -> . % 76.04/76.29 95480[97:SSi:95479.0,78160.0,78163.0,78599.0,94866.0,95470.0] || -> . % 76.04/76.29 95481[97:Spt:95480.0,95475.0,95477.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.29 95482[97:Spt:95480.0,95475.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 95486[97:Res:95482.0,61.1] always3(s22) || -> . % 76.04/76.29 95487[97:SSi:95486.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.29 95488[95:Spt:95487.0,94865.0,94866.0] || until2p7(s21)*+ -> . % 76.04/76.29 95489[95:Spt:95487.0,94865.1] || -> node4(s20)*. % 76.04/76.29 95491[95:MRR:858.0,95489.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.29 95494[95:Res:53.1,95491.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.29 95496[96:Spt:95494.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 95498[96:Res:95496.0,61.1] always3(s20) || -> . % 76.04/76.29 95499[96:SSi:95498.0,78155.0,78159.0,78598.0,94864.0,95489.0] || -> . % 76.04/76.29 95500[96:Spt:95499.0,95494.0,95496.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.29 95501[96:Spt:95499.0,95494.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 95505[96:Res:95501.0,61.1] always3(s21) || -> . % 76.04/76.29 95506[96:SSi:95505.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.29 95507[94:Spt:95506.0,94863.0,94864.0] || until2p7(s20)*+ -> . % 76.04/76.29 95508[94:Spt:95506.0,94863.1] || -> node4(s19)*. % 76.04/76.29 95510[94:MRR:861.0,95508.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.29 95513[94:Res:53.1,95510.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.29 95518[95:Spt:95513.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 95520[95:Res:95518.0,61.1] always3(s19) || -> . % 76.04/76.29 95521[95:SSi:95520.0,78151.0,78154.0,78597.0,94862.0,95508.0] || -> . % 76.04/76.29 95522[95:Spt:95521.0,95513.0,95518.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.29 95523[95:Spt:95521.0,95513.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 95527[95:Res:95523.0,61.1] always3(s20) || -> . % 76.04/76.29 95528[95:SSi:95527.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.29 95529[93:Spt:95528.0,94861.0,94862.0] || until2p7(s19)*+ -> . % 76.04/76.29 95530[93:Spt:95528.0,94861.1] || -> node4(s18)*. % 76.04/76.29 95532[93:MRR:864.0,95530.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.29 95535[93:Res:53.1,95532.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.29 95537[94:Spt:95535.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 95539[94:Res:95537.0,61.1] always3(s18) || -> . % 76.04/76.29 95540[94:SSi:95539.0,78146.0,78150.0,78596.0,94860.0,95530.0] || -> . % 76.04/76.29 95541[94:Spt:95540.0,95535.0,95537.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.29 95542[94:Spt:95540.0,95535.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 95546[94:Res:95542.0,61.1] always3(s19) || -> . % 76.04/76.29 95547[94:SSi:95546.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.29 95548[92:Spt:95547.0,94859.0,94860.0] || until2p7(s18)*+ -> . % 76.04/76.29 95549[92:Spt:95547.0,94859.1] || -> node4(s17)*. % 76.04/76.29 95551[92:MRR:867.0,95549.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.29 95554[92:Res:53.1,95551.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.29 95556[93:Spt:95554.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 95558[93:Res:95556.0,61.1] always3(s17) || -> . % 76.04/76.29 95559[93:SSi:95558.0,78142.0,78145.0,78595.0,94858.0,95549.0] || -> . % 76.04/76.29 95560[93:Spt:95559.0,95554.0,95556.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.29 95561[93:Spt:95559.0,95554.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 95565[93:Res:95561.0,61.1] always3(s18) || -> . % 76.04/76.29 95566[93:SSi:95565.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.29 95567[91:Spt:95566.0,94857.0,94858.0] || until2p7(s17)*+ -> . % 76.04/76.29 95568[91:Spt:95566.0,94857.1] || -> node4(s16)*. % 76.04/76.29 95570[91:MRR:870.0,95568.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.29 95573[91:Res:53.1,95570.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.29 95575[92:Spt:95573.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.29 95577[92:Res:95575.0,61.1] always3(s16) || -> . % 76.04/76.29 95578[92:SSi:95577.0,78137.0,78141.0,78594.0,94856.0,95568.0] || -> . % 76.04/76.29 95579[92:Spt:95578.0,95573.0,95575.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.29 95580[92:Spt:95578.0,95573.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 95584[92:Res:95580.0,61.1] always3(s17) || -> . % 76.04/76.29 95585[92:SSi:95584.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.29 95586[90:Spt:95585.0,94855.0,94856.0] || until2p7(s16)*+ -> . % 76.04/76.29 95587[90:Spt:95585.0,94855.1] || -> node4(s15)*. % 76.04/76.29 95589[90:MRR:873.0,95587.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.29 95592[90:Res:53.1,95589.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.29 95597[91:Spt:95592.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.29 95599[91:Res:95597.0,61.1] always3(s15) || -> . % 76.04/76.29 95600[91:SSi:95599.0,78133.0,78136.0,78593.0,94854.0,95587.0] || -> . % 76.04/76.29 95601[91:Spt:95600.0,95592.0,95597.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.29 95602[91:Spt:95600.0,95592.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.29 95606[91:Res:95602.0,61.1] always3(s16) || -> . % 76.04/76.29 95607[91:SSi:95606.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.29 95608[89:Spt:95607.0,94853.0,94854.0] || until2p7(s15)*+ -> . % 76.04/76.29 95609[89:Spt:95607.0,94853.1] || -> node4(s14)*. % 76.04/76.29 95611[89:MRR:876.0,95609.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.29 95614[89:Res:53.1,95611.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.29 95616[89:MRR:95614.0,94843.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.29 95618[89:Res:95616.0,61.1] always3(s15) || -> . % 76.04/76.29 95619[89:SSi:95618.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.29 95620[87:Spt:95619.0,94711.0,94714.0] || trans(s49,s14)*+ -> . % 76.04/76.29 95621[87:Spt:95619.0,94711.1,94711.2,94711.3,94711.4,94711.5,94711.6,94711.7,94711.8,94711.9,94711.10,94711.11,94711.12] || -> trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.29 95623[87:MRR:94713.1,95620.0] xuntil6(s49) || -> trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.29 95624[88:Spt:95621.0] || -> trans(s49,s13)*. % 76.04/76.29 95625[88:Res:95624.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s13)*. % 76.04/76.29 95627[88:Res:95624.0,60.0] || -> node2(s49,s13)*. % 76.04/76.29 95628[88:SSi:95625.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s13)*. % 76.04/76.29 95629[88:Res:95627.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)*. % 76.04/76.29 95749[88:SoR:95629.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)*. % 76.04/76.29 95751[88:SoR:95749.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)* xuntil6(s49). % 76.04/76.29 95752[88:SSi:95751.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s13,c_busy)* xuntil6(s49). % 76.04/76.29 95753[89:Spt:95752.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.29 95755[89:Res:95753.0,61.1] always3(s13) || -> . % 76.04/76.29 95756[89:SSi:95755.0,78124.0,78127.0,78591.0] || -> . % 76.04/76.29 95757[89:Spt:95756.0,95752.1,95753.0] || m_main_v_state(s13,c_busy)*+ -> . % 76.04/76.29 95758[89:Spt:95756.0,95752.0,95752.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.29 95762[89:MRR:95749.2,95757.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.29 95763[89:Res:53.1,95758.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.29 95765[89:MRR:95763.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.29 95766[89:MRR:95628.0,95765.0] || -> until2p7(s13)*. % 76.04/76.29 95767[89:MRR:209.0,95766.0] || -> until2p7(s14)* node4(s13). % 76.04/76.29 95768[90:Spt:95767.0] || -> until2p7(s14)*. % 76.04/76.29 95769[90:MRR:210.0,95768.0] || -> until2p7(s15)* node4(s14). % 76.04/76.29 95770[91:Spt:95769.0] || -> until2p7(s15)*. % 76.04/76.29 95771[91:MRR:211.0,95770.0] || -> until2p7(s16)* node4(s15). % 76.04/76.29 95772[92:Spt:95771.0] || -> until2p7(s16)*. % 76.04/76.29 95773[92:MRR:212.0,95772.0] || -> until2p7(s17)* node4(s16). % 76.04/76.29 95774[93:Spt:95773.0] || -> until2p7(s17)*. % 76.04/76.29 95775[93:MRR:213.0,95774.0] || -> until2p7(s18)* node4(s17). % 76.04/76.29 95776[94:Spt:95775.0] || -> until2p7(s18)*. % 76.04/76.29 95777[94:MRR:214.0,95776.0] || -> until2p7(s19)* node4(s18). % 76.04/76.29 95778[95:Spt:95777.0] || -> until2p7(s19)*. % 76.04/76.29 95779[95:MRR:215.0,95778.0] || -> until2p7(s20)* node4(s19). % 76.04/76.29 95780[96:Spt:95779.0] || -> until2p7(s20)*. % 76.04/76.29 95781[96:MRR:216.0,95780.0] || -> until2p7(s21)* node4(s20). % 76.04/76.29 95782[97:Spt:95781.0] || -> until2p7(s21)*. % 76.04/76.29 95783[97:MRR:217.0,95782.0] || -> until2p7(s22)* node4(s21). % 76.04/76.29 95784[98:Spt:95783.0] || -> until2p7(s22)*. % 76.04/76.29 95785[98:MRR:218.0,95784.0] || -> until2p7(s23)* node4(s22). % 76.04/76.29 95786[99:Spt:95785.0] || -> until2p7(s23)*. % 76.04/76.29 95787[99:MRR:219.0,95786.0] || -> until2p7(s24)* node4(s23). % 76.04/76.29 95788[100:Spt:95787.0] || -> until2p7(s24)*. % 76.04/76.29 95789[100:MRR:220.0,95788.0] || -> until2p7(s25)* node4(s24). % 76.04/76.29 95790[101:Spt:95789.0] || -> until2p7(s25)*. % 76.04/76.29 95791[101:MRR:221.0,95790.0] || -> until2p7(s26)* node4(s25). % 76.04/76.29 95792[102:Spt:95791.0] || -> until2p7(s26)*. % 76.04/76.29 95793[102:MRR:222.0,95792.0] || -> until2p7(s27)* node4(s26). % 76.04/76.29 95794[103:Spt:95793.0] || -> until2p7(s27)*. % 76.04/76.29 95795[103:MRR:223.0,95794.0] || -> until2p7(s28)* node4(s27). % 76.04/76.29 95796[104:Spt:95795.0] || -> until2p7(s28)*. % 76.04/76.29 95797[104:MRR:224.0,95796.0] || -> until2p7(s29)* node4(s28). % 76.04/76.29 95798[105:Spt:95797.0] || -> until2p7(s29)*. % 76.04/76.29 95799[105:MRR:225.0,95798.0] || -> until2p7(s30)* node4(s29). % 76.04/76.29 95800[106:Spt:95799.0] || -> until2p7(s30)*. % 76.04/76.29 95801[106:MRR:226.0,95800.0] || -> until2p7(s31)* node4(s30). % 76.04/76.29 95802[107:Spt:95801.0] || -> until2p7(s31)*. % 76.04/76.29 95803[107:MRR:227.0,95802.0] || -> until2p7(s32)* node4(s31). % 76.04/76.29 95804[108:Spt:95803.0] || -> until2p7(s32)*. % 76.04/76.29 95805[108:MRR:228.0,95804.0] || -> until2p7(s33)* node4(s32). % 76.04/76.29 95806[109:Spt:95805.0] || -> until2p7(s33)*. % 76.04/76.29 95807[109:MRR:229.0,95806.0] || -> until2p7(s34)* node4(s33). % 76.04/76.29 95808[110:Spt:95807.0] || -> until2p7(s34)*. % 76.04/76.29 95809[110:MRR:230.0,95808.0] || -> until2p7(s35)* node4(s34). % 76.04/76.29 95810[111:Spt:95809.0] || -> until2p7(s35)*. % 76.04/76.29 95811[111:MRR:231.0,95810.0] || -> until2p7(s36)* node4(s35). % 76.04/76.29 95812[112:Spt:95811.0] || -> until2p7(s36)*. % 76.04/76.29 95813[112:MRR:232.0,95812.0] || -> until2p7(s37)* node4(s36). % 76.04/76.29 95814[113:Spt:95813.0] || -> until2p7(s37)*. % 76.04/76.29 95815[113:MRR:235.0,95814.0] || -> until2p7(s38)* node4(s37). % 76.04/76.29 95816[114:Spt:95815.0] || -> until2p7(s38)*. % 76.04/76.29 95817[114:MRR:236.0,95816.0] || -> until2p7(s39)* node4(s38). % 76.04/76.29 95818[115:Spt:95817.0] || -> until2p7(s39)*. % 76.04/76.29 95819[115:MRR:237.0,95818.0] || -> until2p7(s40)* node4(s39). % 76.04/76.29 95820[116:Spt:95819.0] || -> until2p7(s40)*. % 76.04/76.29 95821[116:MRR:238.0,95820.0] || -> until2p7(s41)* node4(s40). % 76.04/76.29 95822[117:Spt:95821.0] || -> until2p7(s41)*. % 76.04/76.29 95823[117:MRR:239.0,95822.0] || -> until2p7(s42)* node4(s41). % 76.04/76.29 95824[118:Spt:95823.0] || -> until2p7(s42)*. % 76.04/76.29 95825[118:MRR:240.0,95824.0] || -> until2p7(s43)* node4(s42). % 76.04/76.29 95826[119:Spt:95825.0] || -> until2p7(s43)*. % 76.04/76.29 95827[119:MRR:241.0,95826.0] || -> until2p7(s44)* node4(s43). % 76.04/76.29 95828[120:Spt:95827.0] || -> until2p7(s44)*. % 76.04/76.29 95829[120:MRR:539.0,95828.0] || -> until2p7(s45)* node4(s44). % 76.04/76.29 95830[121:Spt:95829.0] || -> until2p7(s45)*. % 76.04/76.29 95831[121:MRR:544.0,95830.0] || -> until2p7(s46)* node4(s45). % 76.04/76.29 95832[122:Spt:95831.0] || -> until2p7(s46)*. % 76.04/76.29 95833[122:MRR:549.0,95832.0] || -> until2p7(s47)* node4(s46). % 76.04/76.29 95834[123:Spt:95833.0] || -> until2p7(s47)*. % 76.04/76.29 95835[123:MRR:554.0,95834.0] || -> until2p7(s48)* node4(s47). % 76.04/76.29 95836[124:Spt:95835.0] || -> until2p7(s48)*. % 76.04/76.29 95837[124:MRR:559.0,95836.0] || -> until2p7(s49)* node4(s48). % 76.04/76.29 95838[125:Spt:95837.0] || -> until2p7(s49)*. % 76.04/76.29 95839[125:MRR:194.0,95838.0] || -> node4(s49)*. % 76.04/76.29 95840[125:MRR:95762.0,95839.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.29 95844[125:Res:53.1,95840.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.29 95846[125:MRR:95844.0,78381.0] || -> . % 76.04/76.29 95847[125:Spt:95846.0,95837.0,95838.0] || until2p7(s49)*+ -> . % 76.04/76.29 95848[125:Spt:95846.0,95837.1] || -> node4(s48)*. % 76.04/76.29 95849[125:MRR:78384.0,95848.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.29 95852[125:Res:53.1,95849.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 95855[125:Res:95852.0,61.1] always3(s48) || -> . % 76.04/76.29 95856[125:SSi:95855.0,78281.0,78387.0,78626.0,95836.0,95848.0] || -> . % 76.04/76.29 95857[124:Spt:95856.0,95835.0,95836.0] || until2p7(s48)*+ -> . % 76.04/76.29 95858[124:Spt:95856.0,95835.1] || -> node4(s47)*. % 76.04/76.29 95860[124:MRR:777.0,95858.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.29 95872[124:Res:53.1,95860.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.29 95874[125:Spt:95872.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 95876[125:Res:95874.0,61.1] always3(s47) || -> . % 76.04/76.29 95877[125:SSi:95876.0,78277.0,78280.0,78625.0,95834.0,95858.0] || -> . % 76.04/76.29 95878[125:Spt:95877.0,95872.0,95874.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.29 95879[125:Spt:95877.0,95872.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 95883[125:Res:95879.0,61.1] always3(s48) || -> . % 76.04/76.29 95884[125:SSi:95883.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.29 95885[123:Spt:95884.0,95833.0,95834.0] || until2p7(s47)*+ -> . % 76.04/76.29 95886[123:Spt:95884.0,95833.1] || -> node4(s46)*. % 76.04/76.29 95888[123:MRR:780.0,95886.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.29 95895[123:Res:53.1,95888.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.29 95900[124:Spt:95895.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 95902[124:Res:95900.0,61.1] always3(s46) || -> . % 76.04/76.29 95903[124:SSi:95902.0,78272.0,78276.0,78624.0,95832.0,95886.0] || -> . % 76.04/76.29 95904[124:Spt:95903.0,95895.0,95900.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.29 95905[124:Spt:95903.0,95895.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 95909[124:Res:95905.0,61.1] always3(s47) || -> . % 76.04/76.29 95910[124:SSi:95909.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.29 95911[122:Spt:95910.0,95831.0,95832.0] || until2p7(s46)*+ -> . % 76.04/76.29 95912[122:Spt:95910.0,95831.1] || -> node4(s45)*. % 76.04/76.29 95914[122:MRR:783.0,95912.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.29 95917[122:Res:53.1,95914.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.29 95919[123:Spt:95917.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 95921[123:Res:95919.0,61.1] always3(s45) || -> . % 76.04/76.29 95922[123:SSi:95921.0,78268.0,78271.0,78623.0,95830.0,95912.0] || -> . % 76.04/76.29 95923[123:Spt:95922.0,95917.0,95919.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.29 95924[123:Spt:95922.0,95917.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 95928[123:Res:95924.0,61.1] always3(s46) || -> . % 76.04/76.29 95929[123:SSi:95928.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.29 95930[121:Spt:95929.0,95829.0,95830.0] || until2p7(s45)*+ -> . % 76.04/76.29 95931[121:Spt:95929.0,95829.1] || -> node4(s44)*. % 76.04/76.29 95933[121:MRR:786.0,95931.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.29 95936[121:Res:53.1,95933.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.29 95938[122:Spt:95936.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 95940[122:Res:95938.0,61.1] always3(s44) || -> . % 76.04/76.29 95941[122:SSi:95940.0,78263.0,78267.0,78622.0,95828.0,95931.0] || -> . % 76.04/76.29 95942[122:Spt:95941.0,95936.0,95938.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.29 95943[122:Spt:95941.0,95936.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 95947[122:Res:95943.0,61.1] always3(s45) || -> . % 76.04/76.29 95948[122:SSi:95947.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.29 95949[120:Spt:95948.0,95827.0,95828.0] || until2p7(s44)*+ -> . % 76.04/76.29 95950[120:Spt:95948.0,95827.1] || -> node4(s43)*. % 76.04/76.29 95952[120:MRR:789.0,95950.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.29 95955[120:Res:53.1,95952.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.29 95957[121:Spt:95955.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 95959[121:Res:95957.0,61.1] always3(s43) || -> . % 76.04/76.29 95960[121:SSi:95959.0,78259.0,78262.0,78621.0,95826.0,95950.0] || -> . % 76.04/76.29 95961[121:Spt:95960.0,95955.0,95957.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.29 95962[121:Spt:95960.0,95955.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 95966[121:Res:95962.0,61.1] always3(s44) || -> . % 76.04/76.29 95967[121:SSi:95966.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.29 95968[119:Spt:95967.0,95825.0,95826.0] || until2p7(s43)*+ -> . % 76.04/76.29 95969[119:Spt:95967.0,95825.1] || -> node4(s42)*. % 76.04/76.29 95971[119:MRR:792.0,95969.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.29 95974[119:Res:53.1,95971.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.29 95979[120:Spt:95974.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 95981[120:Res:95979.0,61.1] always3(s42) || -> . % 76.04/76.29 95982[120:SSi:95981.0,78254.0,78258.0,78620.0,95824.0,95969.0] || -> . % 76.04/76.29 95983[120:Spt:95982.0,95974.0,95979.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.29 95984[120:Spt:95982.0,95974.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 95988[120:Res:95984.0,61.1] always3(s43) || -> . % 76.04/76.29 95989[120:SSi:95988.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.29 95990[118:Spt:95989.0,95823.0,95824.0] || until2p7(s42)*+ -> . % 76.04/76.29 95991[118:Spt:95989.0,95823.1] || -> node4(s41)*. % 76.04/76.29 95993[118:MRR:795.0,95991.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.29 95996[118:Res:53.1,95993.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.29 95998[119:Spt:95996.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 96000[119:Res:95998.0,61.1] always3(s41) || -> . % 76.04/76.29 96001[119:SSi:96000.0,78250.0,78253.0,78619.0,95822.0,95991.0] || -> . % 76.04/76.29 96002[119:Spt:96001.0,95996.0,95998.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.29 96003[119:Spt:96001.0,95996.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 96007[119:Res:96003.0,61.1] always3(s42) || -> . % 76.04/76.29 96008[119:SSi:96007.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.29 96009[117:Spt:96008.0,95821.0,95822.0] || until2p7(s41)*+ -> . % 76.04/76.29 96010[117:Spt:96008.0,95821.1] || -> node4(s40)*. % 76.04/76.29 96012[117:MRR:798.0,96010.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.29 96015[117:Res:53.1,96012.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.29 96017[118:Spt:96015.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 96019[118:Res:96017.0,61.1] always3(s40) || -> . % 76.04/76.29 96020[118:SSi:96019.0,78245.0,78249.0,78618.0,95820.0,96010.0] || -> . % 76.04/76.29 96021[118:Spt:96020.0,96015.0,96017.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.29 96022[118:Spt:96020.0,96015.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 96026[118:Res:96022.0,61.1] always3(s41) || -> . % 76.04/76.29 96027[118:SSi:96026.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.29 96028[116:Spt:96027.0,95819.0,95820.0] || until2p7(s40)*+ -> . % 76.04/76.29 96029[116:Spt:96027.0,95819.1] || -> node4(s39)*. % 76.04/76.29 96031[116:MRR:801.0,96029.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.29 96034[116:Res:53.1,96031.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.29 96036[117:Spt:96034.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 96038[117:Res:96036.0,61.1] always3(s39) || -> . % 76.04/76.29 96039[117:SSi:96038.0,78241.0,78244.0,78617.0,95818.0,96029.0] || -> . % 76.04/76.29 96040[117:Spt:96039.0,96034.0,96036.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.29 96041[117:Spt:96039.0,96034.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 96045[117:Res:96041.0,61.1] always3(s40) || -> . % 76.04/76.29 96046[117:SSi:96045.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.29 96047[115:Spt:96046.0,95817.0,95818.0] || until2p7(s39)*+ -> . % 76.04/76.29 96048[115:Spt:96046.0,95817.1] || -> node4(s38)*. % 76.04/76.29 96050[115:MRR:804.0,96048.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.29 96053[115:Res:53.1,96050.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.29 96058[116:Spt:96053.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 96060[116:Res:96058.0,61.1] always3(s38) || -> . % 76.04/76.29 96061[116:SSi:96060.0,78236.0,78240.0,78616.0,95816.0,96048.0] || -> . % 76.04/76.29 96062[116:Spt:96061.0,96053.0,96058.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.29 96063[116:Spt:96061.0,96053.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 96067[116:Res:96063.0,61.1] always3(s39) || -> . % 76.04/76.29 96068[116:SSi:96067.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.29 96069[114:Spt:96068.0,95815.0,95816.0] || until2p7(s38)*+ -> . % 76.04/76.29 96070[114:Spt:96068.0,95815.1] || -> node4(s37)*. % 76.04/76.29 96072[114:MRR:807.0,96070.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.29 96075[114:Res:53.1,96072.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.29 96077[115:Spt:96075.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 96079[115:Res:96077.0,61.1] always3(s37) || -> . % 76.04/76.29 96080[115:SSi:96079.0,78232.0,78235.0,78615.0,95814.0,96070.0] || -> . % 76.04/76.29 96081[115:Spt:96080.0,96075.0,96077.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.29 96082[115:Spt:96080.0,96075.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 96086[115:Res:96082.0,61.1] always3(s38) || -> . % 76.04/76.29 96087[115:SSi:96086.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.29 96088[113:Spt:96087.0,95813.0,95814.0] || until2p7(s37)*+ -> . % 76.04/76.29 96089[113:Spt:96087.0,95813.1] || -> node4(s36)*. % 76.04/76.29 96091[113:MRR:810.0,96089.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.29 96094[113:Res:53.1,96091.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.29 96096[114:Spt:96094.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 96098[114:Res:96096.0,61.1] always3(s36) || -> . % 76.04/76.29 96099[114:SSi:96098.0,78227.0,78231.0,78614.0,95812.0,96089.0] || -> . % 76.04/76.29 96100[114:Spt:96099.0,96094.0,96096.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.29 96101[114:Spt:96099.0,96094.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 96105[114:Res:96101.0,61.1] always3(s37) || -> . % 76.04/76.29 96106[114:SSi:96105.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.29 96107[112:Spt:96106.0,95811.0,95812.0] || until2p7(s36)*+ -> . % 76.04/76.29 96108[112:Spt:96106.0,95811.1] || -> node4(s35)*. % 76.04/76.29 96110[112:MRR:813.0,96108.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.29 96113[112:Res:53.1,96110.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.29 96115[113:Spt:96113.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 96117[113:Res:96115.0,61.1] always3(s35) || -> . % 76.04/76.29 96118[113:SSi:96117.0,78223.0,78226.0,78613.0,95810.0,96108.0] || -> . % 76.04/76.29 96119[113:Spt:96118.0,96113.0,96115.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.29 96120[113:Spt:96118.0,96113.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 96124[113:Res:96120.0,61.1] always3(s36) || -> . % 76.04/76.29 96125[113:SSi:96124.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.29 96126[111:Spt:96125.0,95809.0,95810.0] || until2p7(s35)*+ -> . % 76.04/76.29 96127[111:Spt:96125.0,95809.1] || -> node4(s34)*. % 76.04/76.29 96129[111:MRR:816.0,96127.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.29 96132[111:Res:53.1,96129.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.29 96137[112:Spt:96132.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 96139[112:Res:96137.0,61.1] always3(s34) || -> . % 76.04/76.29 96140[112:SSi:96139.0,78218.0,78222.0,78612.0,95808.0,96127.0] || -> . % 76.04/76.29 96141[112:Spt:96140.0,96132.0,96137.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.29 96142[112:Spt:96140.0,96132.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 96146[112:Res:96142.0,61.1] always3(s35) || -> . % 76.04/76.29 96147[112:SSi:96146.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.29 96148[110:Spt:96147.0,95807.0,95808.0] || until2p7(s34)*+ -> . % 76.04/76.29 96149[110:Spt:96147.0,95807.1] || -> node4(s33)*. % 76.04/76.29 96151[110:MRR:819.0,96149.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.29 96154[110:Res:53.1,96151.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.29 96156[111:Spt:96154.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 96158[111:Res:96156.0,61.1] always3(s33) || -> . % 76.04/76.29 96159[111:SSi:96158.0,78214.0,78217.0,78611.0,95806.0,96149.0] || -> . % 76.04/76.29 96160[111:Spt:96159.0,96154.0,96156.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.29 96161[111:Spt:96159.0,96154.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 96165[111:Res:96161.0,61.1] always3(s34) || -> . % 76.04/76.29 96166[111:SSi:96165.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.29 96167[109:Spt:96166.0,95805.0,95806.0] || until2p7(s33)*+ -> . % 76.04/76.29 96168[109:Spt:96166.0,95805.1] || -> node4(s32)*. % 76.04/76.29 96170[109:MRR:822.0,96168.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.29 96173[109:Res:53.1,96170.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.29 96175[110:Spt:96173.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 96177[110:Res:96175.0,61.1] always3(s32) || -> . % 76.04/76.29 96178[110:SSi:96177.0,78209.0,78213.0,78610.0,95804.0,96168.0] || -> . % 76.04/76.29 96179[110:Spt:96178.0,96173.0,96175.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.29 96180[110:Spt:96178.0,96173.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 96184[110:Res:96180.0,61.1] always3(s33) || -> . % 76.04/76.29 96185[110:SSi:96184.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.29 96186[108:Spt:96185.0,95803.0,95804.0] || until2p7(s32)*+ -> . % 76.04/76.29 96187[108:Spt:96185.0,95803.1] || -> node4(s31)*. % 76.04/76.29 96189[108:MRR:825.0,96187.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.29 96192[108:Res:53.1,96189.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.29 96194[109:Spt:96192.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 96196[109:Res:96194.0,61.1] always3(s31) || -> . % 76.04/76.29 96197[109:SSi:96196.0,78205.0,78208.0,78609.0,95802.0,96187.0] || -> . % 76.04/76.29 96198[109:Spt:96197.0,96192.0,96194.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.29 96199[109:Spt:96197.0,96192.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 96203[109:Res:96199.0,61.1] always3(s32) || -> . % 76.04/76.29 96204[109:SSi:96203.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.29 96205[107:Spt:96204.0,95801.0,95802.0] || until2p7(s31)*+ -> . % 76.04/76.29 96206[107:Spt:96204.0,95801.1] || -> node4(s30)*. % 76.04/76.29 96208[107:MRR:828.0,96206.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.29 96211[107:Res:53.1,96208.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.29 96216[108:Spt:96211.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 96218[108:Res:96216.0,61.1] always3(s30) || -> . % 76.04/76.29 96219[108:SSi:96218.0,78200.0,78204.0,78608.0,95800.0,96206.0] || -> . % 76.04/76.29 96220[108:Spt:96219.0,96211.0,96216.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.29 96221[108:Spt:96219.0,96211.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 96225[108:Res:96221.0,61.1] always3(s31) || -> . % 76.04/76.29 96226[108:SSi:96225.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.29 96227[106:Spt:96226.0,95799.0,95800.0] || until2p7(s30)*+ -> . % 76.04/76.29 96228[106:Spt:96226.0,95799.1] || -> node4(s29)*. % 76.04/76.29 96230[106:MRR:831.0,96228.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.29 96233[106:Res:53.1,96230.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.29 96235[107:Spt:96233.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 96237[107:Res:96235.0,61.1] always3(s29) || -> . % 76.04/76.29 96238[107:SSi:96237.0,78196.0,78199.0,78607.0,95798.0,96228.0] || -> . % 76.04/76.29 96239[107:Spt:96238.0,96233.0,96235.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.29 96240[107:Spt:96238.0,96233.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 96244[107:Res:96240.0,61.1] always3(s30) || -> . % 76.04/76.29 96245[107:SSi:96244.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.29 96246[105:Spt:96245.0,95797.0,95798.0] || until2p7(s29)*+ -> . % 76.04/76.29 96247[105:Spt:96245.0,95797.1] || -> node4(s28)*. % 76.04/76.29 96249[105:MRR:834.0,96247.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.29 96252[105:Res:53.1,96249.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.29 96254[106:Spt:96252.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 96256[106:Res:96254.0,61.1] always3(s28) || -> . % 76.04/76.29 96257[106:SSi:96256.0,78191.0,78195.0,78606.0,95796.0,96247.0] || -> . % 76.04/76.29 96258[106:Spt:96257.0,96252.0,96254.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.29 96259[106:Spt:96257.0,96252.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 96263[106:Res:96259.0,61.1] always3(s29) || -> . % 76.04/76.29 96264[106:SSi:96263.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.29 96265[104:Spt:96264.0,95795.0,95796.0] || until2p7(s28)*+ -> . % 76.04/76.29 96266[104:Spt:96264.0,95795.1] || -> node4(s27)*. % 76.04/76.29 96268[104:MRR:837.0,96266.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.29 96271[104:Res:53.1,96268.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.29 96273[105:Spt:96271.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 96275[105:Res:96273.0,61.1] always3(s27) || -> . % 76.04/76.29 96276[105:SSi:96275.0,78187.0,78190.0,78605.0,95794.0,96266.0] || -> . % 76.04/76.29 96277[105:Spt:96276.0,96271.0,96273.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.29 96278[105:Spt:96276.0,96271.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 96282[105:Res:96278.0,61.1] always3(s28) || -> . % 76.04/76.29 96283[105:SSi:96282.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.29 96284[103:Spt:96283.0,95793.0,95794.0] || until2p7(s27)*+ -> . % 76.04/76.29 96285[103:Spt:96283.0,95793.1] || -> node4(s26)*. % 76.04/76.29 96287[103:MRR:840.0,96285.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.29 96290[103:Res:53.1,96287.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.29 96295[104:Spt:96290.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 96297[104:Res:96295.0,61.1] always3(s26) || -> . % 76.04/76.29 96298[104:SSi:96297.0,78182.0,78186.0,78604.0,95792.0,96285.0] || -> . % 76.04/76.29 96299[104:Spt:96298.0,96290.0,96295.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.29 96300[104:Spt:96298.0,96290.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 96304[104:Res:96300.0,61.1] always3(s27) || -> . % 76.04/76.29 96305[104:SSi:96304.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.29 96306[102:Spt:96305.0,95791.0,95792.0] || until2p7(s26)*+ -> . % 76.04/76.29 96307[102:Spt:96305.0,95791.1] || -> node4(s25)*. % 76.04/76.29 96309[102:MRR:843.0,96307.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.29 96312[102:Res:53.1,96309.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.29 96314[103:Spt:96312.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 96316[103:Res:96314.0,61.1] always3(s25) || -> . % 76.04/76.29 96317[103:SSi:96316.0,78178.0,78181.0,78603.0,95790.0,96307.0] || -> . % 76.04/76.29 96318[103:Spt:96317.0,96312.0,96314.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.29 96319[103:Spt:96317.0,96312.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 96323[103:Res:96319.0,61.1] always3(s26) || -> . % 76.04/76.29 96324[103:SSi:96323.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.29 96325[101:Spt:96324.0,95789.0,95790.0] || until2p7(s25)*+ -> . % 76.04/76.29 96326[101:Spt:96324.0,95789.1] || -> node4(s24)*. % 76.04/76.29 96328[101:MRR:846.0,96326.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.29 96331[101:Res:53.1,96328.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.29 96333[102:Spt:96331.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 96335[102:Res:96333.0,61.1] always3(s24) || -> . % 76.04/76.29 96336[102:SSi:96335.0,78173.0,78177.0,78602.0,95788.0,96326.0] || -> . % 76.04/76.29 96337[102:Spt:96336.0,96331.0,96333.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.29 96338[102:Spt:96336.0,96331.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 96342[102:Res:96338.0,61.1] always3(s25) || -> . % 76.04/76.29 96343[102:SSi:96342.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.29 96344[100:Spt:96343.0,95787.0,95788.0] || until2p7(s24)*+ -> . % 76.04/76.29 96345[100:Spt:96343.0,95787.1] || -> node4(s23)*. % 76.04/76.29 96347[100:MRR:849.0,96345.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.29 96350[100:Res:53.1,96347.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.29 96352[101:Spt:96350.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 96354[101:Res:96352.0,61.1] always3(s23) || -> . % 76.04/76.29 96355[101:SSi:96354.0,78169.0,78172.0,78601.0,95786.0,96345.0] || -> . % 76.04/76.29 96356[101:Spt:96355.0,96350.0,96352.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.29 96357[101:Spt:96355.0,96350.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 96361[101:Res:96357.0,61.1] always3(s24) || -> . % 76.04/76.29 96362[101:SSi:96361.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.29 96363[99:Spt:96362.0,95785.0,95786.0] || until2p7(s23)*+ -> . % 76.04/76.29 96364[99:Spt:96362.0,95785.1] || -> node4(s22)*. % 76.04/76.29 96366[99:MRR:852.0,96364.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.29 96369[99:Res:53.1,96366.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.29 96374[100:Spt:96369.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 96376[100:Res:96374.0,61.1] always3(s22) || -> . % 76.04/76.29 96377[100:SSi:96376.0,78164.0,78168.0,78600.0,95784.0,96364.0] || -> . % 76.04/76.29 96378[100:Spt:96377.0,96369.0,96374.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.29 96379[100:Spt:96377.0,96369.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 96383[100:Res:96379.0,61.1] always3(s23) || -> . % 76.04/76.29 96384[100:SSi:96383.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.29 96385[98:Spt:96384.0,95783.0,95784.0] || until2p7(s22)*+ -> . % 76.04/76.29 96386[98:Spt:96384.0,95783.1] || -> node4(s21)*. % 76.04/76.29 96388[98:MRR:855.0,96386.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.29 96391[98:Res:53.1,96388.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.29 96393[99:Spt:96391.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 96395[99:Res:96393.0,61.1] always3(s21) || -> . % 76.04/76.29 96396[99:SSi:96395.0,78160.0,78163.0,78599.0,95782.0,96386.0] || -> . % 76.04/76.29 96397[99:Spt:96396.0,96391.0,96393.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.29 96398[99:Spt:96396.0,96391.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 96402[99:Res:96398.0,61.1] always3(s22) || -> . % 76.04/76.29 96403[99:SSi:96402.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.29 96404[97:Spt:96403.0,95781.0,95782.0] || until2p7(s21)*+ -> . % 76.04/76.29 96405[97:Spt:96403.0,95781.1] || -> node4(s20)*. % 76.04/76.29 96407[97:MRR:858.0,96405.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.29 96410[97:Res:53.1,96407.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.29 96412[98:Spt:96410.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 96414[98:Res:96412.0,61.1] always3(s20) || -> . % 76.04/76.29 96415[98:SSi:96414.0,78155.0,78159.0,78598.0,95780.0,96405.0] || -> . % 76.04/76.29 96416[98:Spt:96415.0,96410.0,96412.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.29 96417[98:Spt:96415.0,96410.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 96421[98:Res:96417.0,61.1] always3(s21) || -> . % 76.04/76.29 96422[98:SSi:96421.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.29 96423[96:Spt:96422.0,95779.0,95780.0] || until2p7(s20)*+ -> . % 76.04/76.29 96424[96:Spt:96422.0,95779.1] || -> node4(s19)*. % 76.04/76.29 96426[96:MRR:861.0,96424.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.29 96429[96:Res:53.1,96426.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.29 96431[97:Spt:96429.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 96433[97:Res:96431.0,61.1] always3(s19) || -> . % 76.04/76.29 96434[97:SSi:96433.0,78151.0,78154.0,78597.0,95778.0,96424.0] || -> . % 76.04/76.29 96435[97:Spt:96434.0,96429.0,96431.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.29 96436[97:Spt:96434.0,96429.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 96440[97:Res:96436.0,61.1] always3(s20) || -> . % 76.04/76.29 96441[97:SSi:96440.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.29 96442[95:Spt:96441.0,95777.0,95778.0] || until2p7(s19)*+ -> . % 76.04/76.29 96443[95:Spt:96441.0,95777.1] || -> node4(s18)*. % 76.04/76.29 96445[95:MRR:864.0,96443.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.29 96448[95:Res:53.1,96445.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.29 96453[96:Spt:96448.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 96455[96:Res:96453.0,61.1] always3(s18) || -> . % 76.04/76.29 96456[96:SSi:96455.0,78146.0,78150.0,78596.0,95776.0,96443.0] || -> . % 76.04/76.29 96457[96:Spt:96456.0,96448.0,96453.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.29 96458[96:Spt:96456.0,96448.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 96462[96:Res:96458.0,61.1] always3(s19) || -> . % 76.04/76.29 96463[96:SSi:96462.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.29 96464[94:Spt:96463.0,95775.0,95776.0] || until2p7(s18)*+ -> . % 76.04/76.29 96465[94:Spt:96463.0,95775.1] || -> node4(s17)*. % 76.04/76.29 96467[94:MRR:867.0,96465.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.29 96470[94:Res:53.1,96467.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.29 96472[95:Spt:96470.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 96474[95:Res:96472.0,61.1] always3(s17) || -> . % 76.04/76.29 96475[95:SSi:96474.0,78142.0,78145.0,78595.0,95774.0,96465.0] || -> . % 76.04/76.29 96476[95:Spt:96475.0,96470.0,96472.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.29 96477[95:Spt:96475.0,96470.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 96481[95:Res:96477.0,61.1] always3(s18) || -> . % 76.04/76.29 96482[95:SSi:96481.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.29 96483[93:Spt:96482.0,95773.0,95774.0] || until2p7(s17)*+ -> . % 76.04/76.29 96484[93:Spt:96482.0,95773.1] || -> node4(s16)*. % 76.04/76.29 96486[93:MRR:870.0,96484.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.29 96489[93:Res:53.1,96486.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.29 96491[94:Spt:96489.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.29 96493[94:Res:96491.0,61.1] always3(s16) || -> . % 76.04/76.29 96494[94:SSi:96493.0,78137.0,78141.0,78594.0,95772.0,96484.0] || -> . % 76.04/76.29 96495[94:Spt:96494.0,96489.0,96491.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.29 96496[94:Spt:96494.0,96489.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 96500[94:Res:96496.0,61.1] always3(s17) || -> . % 76.04/76.29 96501[94:SSi:96500.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.29 96502[92:Spt:96501.0,95771.0,95772.0] || until2p7(s16)*+ -> . % 76.04/76.29 96503[92:Spt:96501.0,95771.1] || -> node4(s15)*. % 76.04/76.29 96505[92:MRR:873.0,96503.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.29 96508[92:Res:53.1,96505.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.29 96510[93:Spt:96508.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.29 96512[93:Res:96510.0,61.1] always3(s15) || -> . % 76.04/76.29 96513[93:SSi:96512.0,78133.0,78136.0,78593.0,95770.0,96503.0] || -> . % 76.04/76.29 96514[93:Spt:96513.0,96508.0,96510.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.29 96515[93:Spt:96513.0,96508.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.29 96519[93:Res:96515.0,61.1] always3(s16) || -> . % 76.04/76.29 96520[93:SSi:96519.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.29 96521[91:Spt:96520.0,95769.0,95770.0] || until2p7(s15)*+ -> . % 76.04/76.29 96522[91:Spt:96520.0,95769.1] || -> node4(s14)*. % 76.04/76.29 96524[91:MRR:876.0,96522.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.29 96527[91:Res:53.1,96524.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.29 96532[92:Spt:96527.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.29 96534[92:Res:96532.0,61.1] always3(s14) || -> . % 76.04/76.29 96535[92:SSi:96534.0,78128.0,78132.0,78592.0,95768.0,96522.0] || -> . % 76.04/76.29 96536[92:Spt:96535.0,96527.0,96532.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.29 96537[92:Spt:96535.0,96527.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.29 96541[92:Res:96537.0,61.1] always3(s15) || -> . % 76.04/76.29 96542[92:SSi:96541.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.29 96543[90:Spt:96542.0,95767.0,95768.0] || until2p7(s14)*+ -> . % 76.04/76.29 96544[90:Spt:96542.0,95767.1] || -> node4(s13)*. % 76.04/76.29 96546[90:MRR:879.0,96544.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.29 96549[90:Res:53.1,96546.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.29 96551[90:MRR:96549.0,95757.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.29 96553[90:Res:96551.0,61.1] always3(s14) || -> . % 76.04/76.29 96554[90:SSi:96553.0,78128.0,78132.0,78592.0] || -> . % 76.04/76.29 96555[88:Spt:96554.0,95621.0,95624.0] || trans(s49,s13)*+ -> . % 76.04/76.29 96556[88:Spt:96554.0,95621.1,95621.2,95621.3,95621.4,95621.5,95621.6,95621.7,95621.8,95621.9,95621.10,95621.11] || -> trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.29 96558[88:MRR:95623.1,96555.0] xuntil6(s49) || -> trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.29 96559[89:Spt:96556.0] || -> trans(s49,s12)*. % 76.04/76.29 96560[89:Res:96559.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s12)*. % 76.04/76.29 96562[89:Res:96559.0,60.0] || -> node2(s49,s12)*. % 76.04/76.29 96563[89:SSi:96560.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s12)*. % 76.04/76.29 96564[89:Res:96562.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)*. % 76.04/76.29 96688[89:SoR:96564.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)*. % 76.04/76.29 96690[89:SoR:96688.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)* xuntil6(s49). % 76.04/76.29 96691[89:SSi:96690.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s12,c_busy)* xuntil6(s49). % 76.04/76.29 96692[90:Spt:96691.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.29 96694[90:Res:96692.0,61.1] always3(s12) || -> . % 76.04/76.29 96695[90:SSi:96694.0,78119.0,78123.0,78590.0] || -> . % 76.04/76.29 96696[90:Spt:96695.0,96691.1,96692.0] || m_main_v_state(s12,c_busy)*+ -> . % 76.04/76.29 96697[90:Spt:96695.0,96691.0,96691.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.29 96701[90:MRR:96688.2,96696.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.29 96702[90:Res:53.1,96697.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.29 96704[90:MRR:96702.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.29 96705[90:MRR:96563.0,96704.0] || -> until2p7(s12)*. % 76.04/76.29 96706[90:MRR:208.0,96705.0] || -> until2p7(s13)* node4(s12). % 76.04/76.29 96707[91:Spt:96706.0] || -> until2p7(s13)*. % 76.04/76.29 96708[91:MRR:209.0,96707.0] || -> until2p7(s14)* node4(s13). % 76.04/76.29 96709[92:Spt:96708.0] || -> until2p7(s14)*. % 76.04/76.29 96710[92:MRR:210.0,96709.0] || -> until2p7(s15)* node4(s14). % 76.04/76.29 96711[93:Spt:96710.0] || -> until2p7(s15)*. % 76.04/76.29 96712[93:MRR:211.0,96711.0] || -> until2p7(s16)* node4(s15). % 76.04/76.29 96713[94:Spt:96712.0] || -> until2p7(s16)*. % 76.04/76.29 96714[94:MRR:212.0,96713.0] || -> until2p7(s17)* node4(s16). % 76.04/76.29 96715[95:Spt:96714.0] || -> until2p7(s17)*. % 76.04/76.29 96716[95:MRR:213.0,96715.0] || -> until2p7(s18)* node4(s17). % 76.04/76.29 96717[96:Spt:96716.0] || -> until2p7(s18)*. % 76.04/76.29 96718[96:MRR:214.0,96717.0] || -> until2p7(s19)* node4(s18). % 76.04/76.29 96719[97:Spt:96718.0] || -> until2p7(s19)*. % 76.04/76.29 96720[97:MRR:215.0,96719.0] || -> until2p7(s20)* node4(s19). % 76.04/76.29 96721[98:Spt:96720.0] || -> until2p7(s20)*. % 76.04/76.29 96722[98:MRR:216.0,96721.0] || -> until2p7(s21)* node4(s20). % 76.04/76.29 96723[99:Spt:96722.0] || -> until2p7(s21)*. % 76.04/76.29 96724[99:MRR:217.0,96723.0] || -> until2p7(s22)* node4(s21). % 76.04/76.29 96725[100:Spt:96724.0] || -> until2p7(s22)*. % 76.04/76.29 96726[100:MRR:218.0,96725.0] || -> until2p7(s23)* node4(s22). % 76.04/76.29 96727[101:Spt:96726.0] || -> until2p7(s23)*. % 76.04/76.29 96728[101:MRR:219.0,96727.0] || -> until2p7(s24)* node4(s23). % 76.04/76.29 96729[102:Spt:96728.0] || -> until2p7(s24)*. % 76.04/76.29 96730[102:MRR:220.0,96729.0] || -> until2p7(s25)* node4(s24). % 76.04/76.29 96731[103:Spt:96730.0] || -> until2p7(s25)*. % 76.04/76.29 96732[103:MRR:221.0,96731.0] || -> until2p7(s26)* node4(s25). % 76.04/76.29 96733[104:Spt:96732.0] || -> until2p7(s26)*. % 76.04/76.29 96734[104:MRR:222.0,96733.0] || -> until2p7(s27)* node4(s26). % 76.04/76.29 96735[105:Spt:96734.0] || -> until2p7(s27)*. % 76.04/76.29 96736[105:MRR:223.0,96735.0] || -> until2p7(s28)* node4(s27). % 76.04/76.29 96737[106:Spt:96736.0] || -> until2p7(s28)*. % 76.04/76.29 96738[106:MRR:224.0,96737.0] || -> until2p7(s29)* node4(s28). % 76.04/76.29 96739[107:Spt:96738.0] || -> until2p7(s29)*. % 76.04/76.29 96740[107:MRR:225.0,96739.0] || -> until2p7(s30)* node4(s29). % 76.04/76.29 96741[108:Spt:96740.0] || -> until2p7(s30)*. % 76.04/76.29 96742[108:MRR:226.0,96741.0] || -> until2p7(s31)* node4(s30). % 76.04/76.29 96743[109:Spt:96742.0] || -> until2p7(s31)*. % 76.04/76.29 96744[109:MRR:227.0,96743.0] || -> until2p7(s32)* node4(s31). % 76.04/76.29 96745[110:Spt:96744.0] || -> until2p7(s32)*. % 76.04/76.29 96746[110:MRR:228.0,96745.0] || -> until2p7(s33)* node4(s32). % 76.04/76.29 96747[111:Spt:96746.0] || -> until2p7(s33)*. % 76.04/76.29 96748[111:MRR:229.0,96747.0] || -> until2p7(s34)* node4(s33). % 76.04/76.29 96749[112:Spt:96748.0] || -> until2p7(s34)*. % 76.04/76.29 96750[112:MRR:230.0,96749.0] || -> until2p7(s35)* node4(s34). % 76.04/76.29 96751[113:Spt:96750.0] || -> until2p7(s35)*. % 76.04/76.29 96752[113:MRR:231.0,96751.0] || -> until2p7(s36)* node4(s35). % 76.04/76.29 96753[114:Spt:96752.0] || -> until2p7(s36)*. % 76.04/76.29 96754[114:MRR:232.0,96753.0] || -> until2p7(s37)* node4(s36). % 76.04/76.29 96755[115:Spt:96754.0] || -> until2p7(s37)*. % 76.04/76.29 96756[115:MRR:235.0,96755.0] || -> until2p7(s38)* node4(s37). % 76.04/76.29 96757[116:Spt:96756.0] || -> until2p7(s38)*. % 76.04/76.29 96758[116:MRR:236.0,96757.0] || -> until2p7(s39)* node4(s38). % 76.04/76.29 96759[117:Spt:96758.0] || -> until2p7(s39)*. % 76.04/76.29 96760[117:MRR:237.0,96759.0] || -> until2p7(s40)* node4(s39). % 76.04/76.29 96761[118:Spt:96760.0] || -> until2p7(s40)*. % 76.04/76.29 96762[118:MRR:238.0,96761.0] || -> until2p7(s41)* node4(s40). % 76.04/76.29 96763[119:Spt:96762.0] || -> until2p7(s41)*. % 76.04/76.29 96764[119:MRR:239.0,96763.0] || -> until2p7(s42)* node4(s41). % 76.04/76.29 96765[120:Spt:96764.0] || -> until2p7(s42)*. % 76.04/76.29 96766[120:MRR:240.0,96765.0] || -> until2p7(s43)* node4(s42). % 76.04/76.29 96767[121:Spt:96766.0] || -> until2p7(s43)*. % 76.04/76.29 96768[121:MRR:241.0,96767.0] || -> until2p7(s44)* node4(s43). % 76.04/76.29 96769[122:Spt:96768.0] || -> until2p7(s44)*. % 76.04/76.29 96770[122:MRR:539.0,96769.0] || -> until2p7(s45)* node4(s44). % 76.04/76.29 96771[123:Spt:96770.0] || -> until2p7(s45)*. % 76.04/76.29 96772[123:MRR:544.0,96771.0] || -> until2p7(s46)* node4(s45). % 76.04/76.29 96773[124:Spt:96772.0] || -> until2p7(s46)*. % 76.04/76.29 96774[124:MRR:549.0,96773.0] || -> until2p7(s47)* node4(s46). % 76.04/76.29 96775[125:Spt:96774.0] || -> until2p7(s47)*. % 76.04/76.29 96776[125:MRR:554.0,96775.0] || -> until2p7(s48)* node4(s47). % 76.04/76.29 96777[126:Spt:96776.0] || -> until2p7(s48)*. % 76.04/76.29 96778[126:MRR:559.0,96777.0] || -> until2p7(s49)* node4(s48). % 76.04/76.29 96779[127:Spt:96778.0] || -> until2p7(s49)*. % 76.04/76.29 96780[127:MRR:194.0,96779.0] || -> node4(s49)*. % 76.04/76.29 96781[127:MRR:96701.0,96780.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.29 96782[127:Res:53.1,96781.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.29 96784[127:MRR:96782.0,78381.0] || -> . % 76.04/76.29 96785[127:Spt:96784.0,96778.0,96779.0] || until2p7(s49)*+ -> . % 76.04/76.29 96786[127:Spt:96784.0,96778.1] || -> node4(s48)*. % 76.04/76.29 96787[127:MRR:78384.0,96786.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.29 96790[127:Res:53.1,96787.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 96793[127:Res:96790.0,61.1] always3(s48) || -> . % 76.04/76.29 96794[127:SSi:96793.0,78281.0,78387.0,78626.0,96777.0,96786.0] || -> . % 76.04/76.29 96795[126:Spt:96794.0,96776.0,96777.0] || until2p7(s48)*+ -> . % 76.04/76.29 96796[126:Spt:96794.0,96776.1] || -> node4(s47)*. % 76.04/76.29 96798[126:MRR:777.0,96796.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.29 96813[126:Res:53.1,96798.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.29 96818[127:Spt:96813.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 96820[127:Res:96818.0,61.1] always3(s47) || -> . % 76.04/76.29 96821[127:SSi:96820.0,78277.0,78280.0,78625.0,96775.0,96796.0] || -> . % 76.04/76.29 96822[127:Spt:96821.0,96813.0,96818.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.29 96823[127:Spt:96821.0,96813.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 96827[127:Res:96823.0,61.1] always3(s48) || -> . % 76.04/76.29 96828[127:SSi:96827.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.29 96829[125:Spt:96828.0,96774.0,96775.0] || until2p7(s47)*+ -> . % 76.04/76.29 96830[125:Spt:96828.0,96774.1] || -> node4(s46)*. % 76.04/76.29 96832[125:MRR:780.0,96830.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.29 96839[125:Res:53.1,96832.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.29 96841[126:Spt:96839.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 96843[126:Res:96841.0,61.1] always3(s46) || -> . % 76.04/76.29 96844[126:SSi:96843.0,78272.0,78276.0,78624.0,96773.0,96830.0] || -> . % 76.04/76.29 96845[126:Spt:96844.0,96839.0,96841.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.29 96846[126:Spt:96844.0,96839.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 96850[126:Res:96846.0,61.1] always3(s47) || -> . % 76.04/76.29 96851[126:SSi:96850.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.29 96852[124:Spt:96851.0,96772.0,96773.0] || until2p7(s46)*+ -> . % 76.04/76.29 96853[124:Spt:96851.0,96772.1] || -> node4(s45)*. % 76.04/76.29 96855[124:MRR:783.0,96853.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.29 96858[124:Res:53.1,96855.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.29 96863[125:Spt:96858.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 96865[125:Res:96863.0,61.1] always3(s45) || -> . % 76.04/76.29 96866[125:SSi:96865.0,78268.0,78271.0,78623.0,96771.0,96853.0] || -> . % 76.04/76.29 96867[125:Spt:96866.0,96858.0,96863.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.29 96868[125:Spt:96866.0,96858.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 96872[125:Res:96868.0,61.1] always3(s46) || -> . % 76.04/76.29 96873[125:SSi:96872.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.29 96874[123:Spt:96873.0,96770.0,96771.0] || until2p7(s45)*+ -> . % 76.04/76.29 96875[123:Spt:96873.0,96770.1] || -> node4(s44)*. % 76.04/76.29 96877[123:MRR:786.0,96875.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.29 96880[123:Res:53.1,96877.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.29 96882[124:Spt:96880.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 96884[124:Res:96882.0,61.1] always3(s44) || -> . % 76.04/76.29 96885[124:SSi:96884.0,78263.0,78267.0,78622.0,96769.0,96875.0] || -> . % 76.04/76.29 96886[124:Spt:96885.0,96880.0,96882.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.29 96887[124:Spt:96885.0,96880.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 96891[124:Res:96887.0,61.1] always3(s45) || -> . % 76.04/76.29 96892[124:SSi:96891.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.29 96893[122:Spt:96892.0,96768.0,96769.0] || until2p7(s44)*+ -> . % 76.04/76.29 96894[122:Spt:96892.0,96768.1] || -> node4(s43)*. % 76.04/76.29 96896[122:MRR:789.0,96894.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.29 96899[122:Res:53.1,96896.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.29 96901[123:Spt:96899.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 96903[123:Res:96901.0,61.1] always3(s43) || -> . % 76.04/76.29 96904[123:SSi:96903.0,78259.0,78262.0,78621.0,96767.0,96894.0] || -> . % 76.04/76.29 96905[123:Spt:96904.0,96899.0,96901.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.29 96906[123:Spt:96904.0,96899.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 96910[123:Res:96906.0,61.1] always3(s44) || -> . % 76.04/76.29 96911[123:SSi:96910.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.29 96912[121:Spt:96911.0,96766.0,96767.0] || until2p7(s43)*+ -> . % 76.04/76.29 96913[121:Spt:96911.0,96766.1] || -> node4(s42)*. % 76.04/76.29 96915[121:MRR:792.0,96913.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.29 96918[121:Res:53.1,96915.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.29 96920[122:Spt:96918.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 96922[122:Res:96920.0,61.1] always3(s42) || -> . % 76.04/76.29 96923[122:SSi:96922.0,78254.0,78258.0,78620.0,96765.0,96913.0] || -> . % 76.04/76.29 96924[122:Spt:96923.0,96918.0,96920.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.29 96925[122:Spt:96923.0,96918.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 96929[122:Res:96925.0,61.1] always3(s43) || -> . % 76.04/76.29 96930[122:SSi:96929.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.29 96931[120:Spt:96930.0,96764.0,96765.0] || until2p7(s42)*+ -> . % 76.04/76.29 96932[120:Spt:96930.0,96764.1] || -> node4(s41)*. % 76.04/76.29 96934[120:MRR:795.0,96932.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.29 96937[120:Res:53.1,96934.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.29 96942[121:Spt:96937.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 96944[121:Res:96942.0,61.1] always3(s41) || -> . % 76.04/76.29 96945[121:SSi:96944.0,78250.0,78253.0,78619.0,96763.0,96932.0] || -> . % 76.04/76.29 96946[121:Spt:96945.0,96937.0,96942.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.29 96947[121:Spt:96945.0,96937.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 96951[121:Res:96947.0,61.1] always3(s42) || -> . % 76.04/76.29 96952[121:SSi:96951.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.29 96953[119:Spt:96952.0,96762.0,96763.0] || until2p7(s41)*+ -> . % 76.04/76.29 96954[119:Spt:96952.0,96762.1] || -> node4(s40)*. % 76.04/76.29 96956[119:MRR:798.0,96954.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.29 96959[119:Res:53.1,96956.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.29 96961[120:Spt:96959.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 96963[120:Res:96961.0,61.1] always3(s40) || -> . % 76.04/76.29 96964[120:SSi:96963.0,78245.0,78249.0,78618.0,96761.0,96954.0] || -> . % 76.04/76.29 96965[120:Spt:96964.0,96959.0,96961.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.29 96966[120:Spt:96964.0,96959.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 96970[120:Res:96966.0,61.1] always3(s41) || -> . % 76.04/76.29 96971[120:SSi:96970.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.29 96972[118:Spt:96971.0,96760.0,96761.0] || until2p7(s40)*+ -> . % 76.04/76.29 96973[118:Spt:96971.0,96760.1] || -> node4(s39)*. % 76.04/76.29 96975[118:MRR:801.0,96973.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.29 96978[118:Res:53.1,96975.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.29 96980[119:Spt:96978.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 96982[119:Res:96980.0,61.1] always3(s39) || -> . % 76.04/76.29 96983[119:SSi:96982.0,78241.0,78244.0,78617.0,96759.0,96973.0] || -> . % 76.04/76.29 96984[119:Spt:96983.0,96978.0,96980.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.29 96985[119:Spt:96983.0,96978.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 96989[119:Res:96985.0,61.1] always3(s40) || -> . % 76.04/76.29 96990[119:SSi:96989.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.29 96991[117:Spt:96990.0,96758.0,96759.0] || until2p7(s39)*+ -> . % 76.04/76.29 96992[117:Spt:96990.0,96758.1] || -> node4(s38)*. % 76.04/76.29 96994[117:MRR:804.0,96992.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.29 96997[117:Res:53.1,96994.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.29 96999[118:Spt:96997.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 97001[118:Res:96999.0,61.1] always3(s38) || -> . % 76.04/76.29 97002[118:SSi:97001.0,78236.0,78240.0,78616.0,96757.0,96992.0] || -> . % 76.04/76.29 97003[118:Spt:97002.0,96997.0,96999.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.29 97004[118:Spt:97002.0,96997.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 97008[118:Res:97004.0,61.1] always3(s39) || -> . % 76.04/76.29 97009[118:SSi:97008.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.29 97010[116:Spt:97009.0,96756.0,96757.0] || until2p7(s38)*+ -> . % 76.04/76.29 97011[116:Spt:97009.0,96756.1] || -> node4(s37)*. % 76.04/76.29 97013[116:MRR:807.0,97011.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.29 97016[116:Res:53.1,97013.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.29 97021[117:Spt:97016.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 97023[117:Res:97021.0,61.1] always3(s37) || -> . % 76.04/76.29 97024[117:SSi:97023.0,78232.0,78235.0,78615.0,96755.0,97011.0] || -> . % 76.04/76.29 97025[117:Spt:97024.0,97016.0,97021.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.29 97026[117:Spt:97024.0,97016.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 97030[117:Res:97026.0,61.1] always3(s38) || -> . % 76.04/76.29 97031[117:SSi:97030.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.29 97032[115:Spt:97031.0,96754.0,96755.0] || until2p7(s37)*+ -> . % 76.04/76.29 97033[115:Spt:97031.0,96754.1] || -> node4(s36)*. % 76.04/76.29 97035[115:MRR:810.0,97033.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.29 97038[115:Res:53.1,97035.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.29 97040[116:Spt:97038.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 97042[116:Res:97040.0,61.1] always3(s36) || -> . % 76.04/76.29 97043[116:SSi:97042.0,78227.0,78231.0,78614.0,96753.0,97033.0] || -> . % 76.04/76.29 97044[116:Spt:97043.0,97038.0,97040.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.29 97045[116:Spt:97043.0,97038.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 97049[116:Res:97045.0,61.1] always3(s37) || -> . % 76.04/76.29 97050[116:SSi:97049.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.29 97051[114:Spt:97050.0,96752.0,96753.0] || until2p7(s36)*+ -> . % 76.04/76.29 97052[114:Spt:97050.0,96752.1] || -> node4(s35)*. % 76.04/76.29 97054[114:MRR:813.0,97052.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.29 97057[114:Res:53.1,97054.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.29 97059[115:Spt:97057.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 97061[115:Res:97059.0,61.1] always3(s35) || -> . % 76.04/76.29 97062[115:SSi:97061.0,78223.0,78226.0,78613.0,96751.0,97052.0] || -> . % 76.04/76.29 97063[115:Spt:97062.0,97057.0,97059.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.29 97064[115:Spt:97062.0,97057.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 97068[115:Res:97064.0,61.1] always3(s36) || -> . % 76.04/76.29 97069[115:SSi:97068.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.29 97070[113:Spt:97069.0,96750.0,96751.0] || until2p7(s35)*+ -> . % 76.04/76.29 97071[113:Spt:97069.0,96750.1] || -> node4(s34)*. % 76.04/76.29 97073[113:MRR:816.0,97071.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.29 97076[113:Res:53.1,97073.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.29 97078[114:Spt:97076.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 97080[114:Res:97078.0,61.1] always3(s34) || -> . % 76.04/76.29 97081[114:SSi:97080.0,78218.0,78222.0,78612.0,96749.0,97071.0] || -> . % 76.04/76.29 97082[114:Spt:97081.0,97076.0,97078.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.29 97083[114:Spt:97081.0,97076.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 97087[114:Res:97083.0,61.1] always3(s35) || -> . % 76.04/76.29 97088[114:SSi:97087.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.29 97089[112:Spt:97088.0,96748.0,96749.0] || until2p7(s34)*+ -> . % 76.04/76.29 97090[112:Spt:97088.0,96748.1] || -> node4(s33)*. % 76.04/76.29 97092[112:MRR:819.0,97090.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.29 97095[112:Res:53.1,97092.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.29 97100[113:Spt:97095.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 97102[113:Res:97100.0,61.1] always3(s33) || -> . % 76.04/76.29 97103[113:SSi:97102.0,78214.0,78217.0,78611.0,96747.0,97090.0] || -> . % 76.04/76.29 97104[113:Spt:97103.0,97095.0,97100.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.29 97105[113:Spt:97103.0,97095.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 97109[113:Res:97105.0,61.1] always3(s34) || -> . % 76.04/76.29 97110[113:SSi:97109.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.29 97111[111:Spt:97110.0,96746.0,96747.0] || until2p7(s33)*+ -> . % 76.04/76.29 97112[111:Spt:97110.0,96746.1] || -> node4(s32)*. % 76.04/76.29 97114[111:MRR:822.0,97112.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.29 97117[111:Res:53.1,97114.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.29 97119[112:Spt:97117.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 97121[112:Res:97119.0,61.1] always3(s32) || -> . % 76.04/76.29 97122[112:SSi:97121.0,78209.0,78213.0,78610.0,96745.0,97112.0] || -> . % 76.04/76.29 97123[112:Spt:97122.0,97117.0,97119.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.29 97124[112:Spt:97122.0,97117.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 97128[112:Res:97124.0,61.1] always3(s33) || -> . % 76.04/76.29 97129[112:SSi:97128.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.29 97130[110:Spt:97129.0,96744.0,96745.0] || until2p7(s32)*+ -> . % 76.04/76.29 97131[110:Spt:97129.0,96744.1] || -> node4(s31)*. % 76.04/76.29 97133[110:MRR:825.0,97131.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.29 97136[110:Res:53.1,97133.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.29 97138[111:Spt:97136.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 97140[111:Res:97138.0,61.1] always3(s31) || -> . % 76.04/76.29 97141[111:SSi:97140.0,78205.0,78208.0,78609.0,96743.0,97131.0] || -> . % 76.04/76.29 97142[111:Spt:97141.0,97136.0,97138.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.29 97143[111:Spt:97141.0,97136.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 97147[111:Res:97143.0,61.1] always3(s32) || -> . % 76.04/76.29 97148[111:SSi:97147.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.29 97149[109:Spt:97148.0,96742.0,96743.0] || until2p7(s31)*+ -> . % 76.04/76.29 97150[109:Spt:97148.0,96742.1] || -> node4(s30)*. % 76.04/76.29 97152[109:MRR:828.0,97150.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.29 97155[109:Res:53.1,97152.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.29 97157[110:Spt:97155.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 97159[110:Res:97157.0,61.1] always3(s30) || -> . % 76.04/76.29 97160[110:SSi:97159.0,78200.0,78204.0,78608.0,96741.0,97150.0] || -> . % 76.04/76.29 97161[110:Spt:97160.0,97155.0,97157.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.29 97162[110:Spt:97160.0,97155.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 97166[110:Res:97162.0,61.1] always3(s31) || -> . % 76.04/76.29 97167[110:SSi:97166.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.29 97168[108:Spt:97167.0,96740.0,96741.0] || until2p7(s30)*+ -> . % 76.04/76.29 97169[108:Spt:97167.0,96740.1] || -> node4(s29)*. % 76.04/76.29 97171[108:MRR:831.0,97169.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.29 97174[108:Res:53.1,97171.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.29 97179[109:Spt:97174.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 97181[109:Res:97179.0,61.1] always3(s29) || -> . % 76.04/76.29 97182[109:SSi:97181.0,78196.0,78199.0,78607.0,96739.0,97169.0] || -> . % 76.04/76.29 97183[109:Spt:97182.0,97174.0,97179.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.29 97184[109:Spt:97182.0,97174.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 97188[109:Res:97184.0,61.1] always3(s30) || -> . % 76.04/76.29 97189[109:SSi:97188.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.29 97190[107:Spt:97189.0,96738.0,96739.0] || until2p7(s29)*+ -> . % 76.04/76.29 97191[107:Spt:97189.0,96738.1] || -> node4(s28)*. % 76.04/76.29 97193[107:MRR:834.0,97191.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.29 97196[107:Res:53.1,97193.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.29 97198[108:Spt:97196.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 97200[108:Res:97198.0,61.1] always3(s28) || -> . % 76.04/76.29 97201[108:SSi:97200.0,78191.0,78195.0,78606.0,96737.0,97191.0] || -> . % 76.04/76.29 97202[108:Spt:97201.0,97196.0,97198.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.29 97203[108:Spt:97201.0,97196.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 97207[108:Res:97203.0,61.1] always3(s29) || -> . % 76.04/76.29 97208[108:SSi:97207.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.29 97209[106:Spt:97208.0,96736.0,96737.0] || until2p7(s28)*+ -> . % 76.04/76.29 97210[106:Spt:97208.0,96736.1] || -> node4(s27)*. % 76.04/76.29 97212[106:MRR:837.0,97210.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.29 97215[106:Res:53.1,97212.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.29 97217[107:Spt:97215.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 97219[107:Res:97217.0,61.1] always3(s27) || -> . % 76.04/76.29 97220[107:SSi:97219.0,78187.0,78190.0,78605.0,96735.0,97210.0] || -> . % 76.04/76.29 97221[107:Spt:97220.0,97215.0,97217.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.29 97222[107:Spt:97220.0,97215.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 97226[107:Res:97222.0,61.1] always3(s28) || -> . % 76.04/76.29 97227[107:SSi:97226.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.29 97228[105:Spt:97227.0,96734.0,96735.0] || until2p7(s27)*+ -> . % 76.04/76.29 97229[105:Spt:97227.0,96734.1] || -> node4(s26)*. % 76.04/76.29 97231[105:MRR:840.0,97229.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.29 97234[105:Res:53.1,97231.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.29 97236[106:Spt:97234.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 97238[106:Res:97236.0,61.1] always3(s26) || -> . % 76.04/76.29 97239[106:SSi:97238.0,78182.0,78186.0,78604.0,96733.0,97229.0] || -> . % 76.04/76.29 97240[106:Spt:97239.0,97234.0,97236.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.29 97241[106:Spt:97239.0,97234.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 97245[106:Res:97241.0,61.1] always3(s27) || -> . % 76.04/76.29 97246[106:SSi:97245.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.29 97247[104:Spt:97246.0,96732.0,96733.0] || until2p7(s26)*+ -> . % 76.04/76.29 97248[104:Spt:97246.0,96732.1] || -> node4(s25)*. % 76.04/76.29 97250[104:MRR:843.0,97248.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.29 97253[104:Res:53.1,97250.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.29 97258[105:Spt:97253.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 97260[105:Res:97258.0,61.1] always3(s25) || -> . % 76.04/76.29 97261[105:SSi:97260.0,78178.0,78181.0,78603.0,96731.0,97248.0] || -> . % 76.04/76.29 97262[105:Spt:97261.0,97253.0,97258.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.29 97263[105:Spt:97261.0,97253.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 97267[105:Res:97263.0,61.1] always3(s26) || -> . % 76.04/76.29 97268[105:SSi:97267.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.29 97269[103:Spt:97268.0,96730.0,96731.0] || until2p7(s25)*+ -> . % 76.04/76.29 97270[103:Spt:97268.0,96730.1] || -> node4(s24)*. % 76.04/76.29 97272[103:MRR:846.0,97270.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.29 97275[103:Res:53.1,97272.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.29 97277[104:Spt:97275.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 97279[104:Res:97277.0,61.1] always3(s24) || -> . % 76.04/76.29 97280[104:SSi:97279.0,78173.0,78177.0,78602.0,96729.0,97270.0] || -> . % 76.04/76.29 97281[104:Spt:97280.0,97275.0,97277.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.29 97282[104:Spt:97280.0,97275.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 97286[104:Res:97282.0,61.1] always3(s25) || -> . % 76.04/76.29 97287[104:SSi:97286.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.29 97288[102:Spt:97287.0,96728.0,96729.0] || until2p7(s24)*+ -> . % 76.04/76.29 97289[102:Spt:97287.0,96728.1] || -> node4(s23)*. % 76.04/76.29 97291[102:MRR:849.0,97289.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.29 97294[102:Res:53.1,97291.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.29 97296[103:Spt:97294.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 97298[103:Res:97296.0,61.1] always3(s23) || -> . % 76.04/76.29 97299[103:SSi:97298.0,78169.0,78172.0,78601.0,96727.0,97289.0] || -> . % 76.04/76.29 97300[103:Spt:97299.0,97294.0,97296.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.29 97301[103:Spt:97299.0,97294.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 97305[103:Res:97301.0,61.1] always3(s24) || -> . % 76.04/76.29 97306[103:SSi:97305.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.29 97307[101:Spt:97306.0,96726.0,96727.0] || until2p7(s23)*+ -> . % 76.04/76.29 97308[101:Spt:97306.0,96726.1] || -> node4(s22)*. % 76.04/76.29 97310[101:MRR:852.0,97308.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.29 97313[101:Res:53.1,97310.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.29 97315[102:Spt:97313.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 97317[102:Res:97315.0,61.1] always3(s22) || -> . % 76.04/76.29 97318[102:SSi:97317.0,78164.0,78168.0,78600.0,96725.0,97308.0] || -> . % 76.04/76.29 97319[102:Spt:97318.0,97313.0,97315.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.29 97320[102:Spt:97318.0,97313.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 97324[102:Res:97320.0,61.1] always3(s23) || -> . % 76.04/76.29 97325[102:SSi:97324.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.29 97326[100:Spt:97325.0,96724.0,96725.0] || until2p7(s22)*+ -> . % 76.04/76.29 97327[100:Spt:97325.0,96724.1] || -> node4(s21)*. % 76.04/76.29 97329[100:MRR:855.0,97327.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.29 97332[100:Res:53.1,97329.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.29 97337[101:Spt:97332.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 97339[101:Res:97337.0,61.1] always3(s21) || -> . % 76.04/76.29 97340[101:SSi:97339.0,78160.0,78163.0,78599.0,96723.0,97327.0] || -> . % 76.04/76.29 97341[101:Spt:97340.0,97332.0,97337.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.29 97342[101:Spt:97340.0,97332.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 97346[101:Res:97342.0,61.1] always3(s22) || -> . % 76.04/76.29 97347[101:SSi:97346.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.29 97348[99:Spt:97347.0,96722.0,96723.0] || until2p7(s21)*+ -> . % 76.04/76.29 97349[99:Spt:97347.0,96722.1] || -> node4(s20)*. % 76.04/76.29 97351[99:MRR:858.0,97349.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.29 97354[99:Res:53.1,97351.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.29 97356[100:Spt:97354.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 97358[100:Res:97356.0,61.1] always3(s20) || -> . % 76.04/76.29 97359[100:SSi:97358.0,78155.0,78159.0,78598.0,96721.0,97349.0] || -> . % 76.04/76.29 97360[100:Spt:97359.0,97354.0,97356.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.29 97361[100:Spt:97359.0,97354.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 97365[100:Res:97361.0,61.1] always3(s21) || -> . % 76.04/76.29 97366[100:SSi:97365.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.29 97367[98:Spt:97366.0,96720.0,96721.0] || until2p7(s20)*+ -> . % 76.04/76.29 97368[98:Spt:97366.0,96720.1] || -> node4(s19)*. % 76.04/76.29 97370[98:MRR:861.0,97368.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.29 97373[98:Res:53.1,97370.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.29 97375[99:Spt:97373.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 97377[99:Res:97375.0,61.1] always3(s19) || -> . % 76.04/76.29 97378[99:SSi:97377.0,78151.0,78154.0,78597.0,96719.0,97368.0] || -> . % 76.04/76.29 97379[99:Spt:97378.0,97373.0,97375.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.29 97380[99:Spt:97378.0,97373.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 97384[99:Res:97380.0,61.1] always3(s20) || -> . % 76.04/76.29 97385[99:SSi:97384.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.29 97386[97:Spt:97385.0,96718.0,96719.0] || until2p7(s19)*+ -> . % 76.04/76.29 97387[97:Spt:97385.0,96718.1] || -> node4(s18)*. % 76.04/76.29 97389[97:MRR:864.0,97387.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.29 97392[97:Res:53.1,97389.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.29 97394[98:Spt:97392.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 97396[98:Res:97394.0,61.1] always3(s18) || -> . % 76.04/76.29 97397[98:SSi:97396.0,78146.0,78150.0,78596.0,96717.0,97387.0] || -> . % 76.04/76.29 97398[98:Spt:97397.0,97392.0,97394.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.29 97399[98:Spt:97397.0,97392.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 97403[98:Res:97399.0,61.1] always3(s19) || -> . % 76.04/76.29 97404[98:SSi:97403.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.29 97405[96:Spt:97404.0,96716.0,96717.0] || until2p7(s18)*+ -> . % 76.04/76.29 97406[96:Spt:97404.0,96716.1] || -> node4(s17)*. % 76.04/76.29 97408[96:MRR:867.0,97406.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.29 97411[96:Res:53.1,97408.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.29 97416[97:Spt:97411.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 97418[97:Res:97416.0,61.1] always3(s17) || -> . % 76.04/76.29 97419[97:SSi:97418.0,78142.0,78145.0,78595.0,96715.0,97406.0] || -> . % 76.04/76.29 97420[97:Spt:97419.0,97411.0,97416.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.29 97421[97:Spt:97419.0,97411.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 97425[97:Res:97421.0,61.1] always3(s18) || -> . % 76.04/76.29 97426[97:SSi:97425.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.29 97427[95:Spt:97426.0,96714.0,96715.0] || until2p7(s17)*+ -> . % 76.04/76.29 97428[95:Spt:97426.0,96714.1] || -> node4(s16)*. % 76.04/76.29 97430[95:MRR:870.0,97428.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.29 97433[95:Res:53.1,97430.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.29 97435[96:Spt:97433.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.29 97437[96:Res:97435.0,61.1] always3(s16) || -> . % 76.04/76.29 97438[96:SSi:97437.0,78137.0,78141.0,78594.0,96713.0,97428.0] || -> . % 76.04/76.29 97439[96:Spt:97438.0,97433.0,97435.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.29 97440[96:Spt:97438.0,97433.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 97444[96:Res:97440.0,61.1] always3(s17) || -> . % 76.04/76.29 97445[96:SSi:97444.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.29 97446[94:Spt:97445.0,96712.0,96713.0] || until2p7(s16)*+ -> . % 76.04/76.29 97447[94:Spt:97445.0,96712.1] || -> node4(s15)*. % 76.04/76.29 97449[94:MRR:873.0,97447.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.29 97452[94:Res:53.1,97449.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.29 97454[95:Spt:97452.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.29 97456[95:Res:97454.0,61.1] always3(s15) || -> . % 76.04/76.29 97457[95:SSi:97456.0,78133.0,78136.0,78593.0,96711.0,97447.0] || -> . % 76.04/76.29 97458[95:Spt:97457.0,97452.0,97454.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.29 97459[95:Spt:97457.0,97452.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.29 97463[95:Res:97459.0,61.1] always3(s16) || -> . % 76.04/76.29 97464[95:SSi:97463.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.29 97465[93:Spt:97464.0,96710.0,96711.0] || until2p7(s15)*+ -> . % 76.04/76.29 97466[93:Spt:97464.0,96710.1] || -> node4(s14)*. % 76.04/76.29 97468[93:MRR:876.0,97466.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.29 97471[93:Res:53.1,97468.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.29 97473[94:Spt:97471.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.29 97475[94:Res:97473.0,61.1] always3(s14) || -> . % 76.04/76.29 97476[94:SSi:97475.0,78128.0,78132.0,78592.0,96709.0,97466.0] || -> . % 76.04/76.29 97477[94:Spt:97476.0,97471.0,97473.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.29 97478[94:Spt:97476.0,97471.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.29 97482[94:Res:97478.0,61.1] always3(s15) || -> . % 76.04/76.29 97483[94:SSi:97482.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.29 97484[92:Spt:97483.0,96708.0,96709.0] || until2p7(s14)*+ -> . % 76.04/76.29 97485[92:Spt:97483.0,96708.1] || -> node4(s13)*. % 76.04/76.29 97487[92:MRR:879.0,97485.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.29 97490[92:Res:53.1,97487.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.29 97495[93:Spt:97490.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.29 97497[93:Res:97495.0,61.1] always3(s13) || -> . % 76.04/76.29 97498[93:SSi:97497.0,78124.0,78127.0,78591.0,96707.0,97485.0] || -> . % 76.04/76.29 97499[93:Spt:97498.0,97490.0,97495.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.29 97500[93:Spt:97498.0,97490.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.29 97504[93:Res:97500.0,61.1] always3(s14) || -> . % 76.04/76.29 97505[93:SSi:97504.0,78128.0,78132.0,78592.0] || -> . % 76.04/76.29 97506[91:Spt:97505.0,96706.0,96707.0] || until2p7(s13)*+ -> . % 76.04/76.29 97507[91:Spt:97505.0,96706.1] || -> node4(s12)*. % 76.04/76.29 97509[91:MRR:882.0,97507.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.29 97512[91:Res:53.1,97509.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.29 97514[91:MRR:97512.0,96696.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.29 97516[91:Res:97514.0,61.1] always3(s13) || -> . % 76.04/76.29 97517[91:SSi:97516.0,78124.0,78127.0,78591.0] || -> . % 76.04/76.29 97518[89:Spt:97517.0,96556.0,96559.0] || trans(s49,s12)*+ -> . % 76.04/76.29 97519[89:Spt:97517.0,96556.1,96556.2,96556.3,96556.4,96556.5,96556.6,96556.7,96556.8,96556.9,96556.10] || -> trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.29 97521[89:MRR:96558.1,97518.0] xuntil6(s49) || -> trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.29 97522[90:Spt:97519.0] || -> trans(s49,s11)*. % 76.04/76.29 97523[90:Res:97522.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s11)*. % 76.04/76.29 97525[90:Res:97522.0,60.0] || -> node2(s49,s11)*. % 76.04/76.29 97526[90:SSi:97523.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s11)*. % 76.04/76.29 97527[90:Res:97525.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)*. % 76.04/76.29 97652[90:SoR:97527.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)*. % 76.04/76.29 97654[90:SoR:97652.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)* xuntil6(s49). % 76.04/76.29 97655[90:SSi:97654.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s11,c_busy)* xuntil6(s49). % 76.04/76.29 97656[91:Spt:97655.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.29 97658[91:Res:97656.0,61.1] always3(s11) || -> . % 76.04/76.29 97659[91:SSi:97658.0,78115.0,78118.0,78589.0] || -> . % 76.04/76.29 97660[91:Spt:97659.0,97655.1,97656.0] || m_main_v_state(s11,c_busy)*+ -> . % 76.04/76.29 97661[91:Spt:97659.0,97655.0,97655.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.29 97665[91:MRR:97652.2,97660.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.29 97666[91:Res:53.1,97661.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.29 97668[91:MRR:97666.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.29 97669[91:MRR:97526.0,97668.0] || -> until2p7(s11)*. % 76.04/76.29 97670[91:MRR:207.0,97669.0] || -> until2p7(s12)* node4(s11). % 76.04/76.29 97671[92:Spt:97670.0] || -> until2p7(s12)*. % 76.04/76.29 97672[92:MRR:208.0,97671.0] || -> until2p7(s13)* node4(s12). % 76.04/76.29 97673[93:Spt:97672.0] || -> until2p7(s13)*. % 76.04/76.29 97674[93:MRR:209.0,97673.0] || -> until2p7(s14)* node4(s13). % 76.04/76.29 97675[94:Spt:97674.0] || -> until2p7(s14)*. % 76.04/76.29 97676[94:MRR:210.0,97675.0] || -> until2p7(s15)* node4(s14). % 76.04/76.29 97677[95:Spt:97676.0] || -> until2p7(s15)*. % 76.04/76.29 97678[95:MRR:211.0,97677.0] || -> until2p7(s16)* node4(s15). % 76.04/76.29 97679[96:Spt:97678.0] || -> until2p7(s16)*. % 76.04/76.29 97680[96:MRR:212.0,97679.0] || -> until2p7(s17)* node4(s16). % 76.04/76.29 97681[97:Spt:97680.0] || -> until2p7(s17)*. % 76.04/76.29 97682[97:MRR:213.0,97681.0] || -> until2p7(s18)* node4(s17). % 76.04/76.29 97683[98:Spt:97682.0] || -> until2p7(s18)*. % 76.04/76.29 97684[98:MRR:214.0,97683.0] || -> until2p7(s19)* node4(s18). % 76.04/76.29 97685[99:Spt:97684.0] || -> until2p7(s19)*. % 76.04/76.29 97686[99:MRR:215.0,97685.0] || -> until2p7(s20)* node4(s19). % 76.04/76.29 97687[100:Spt:97686.0] || -> until2p7(s20)*. % 76.04/76.29 97688[100:MRR:216.0,97687.0] || -> until2p7(s21)* node4(s20). % 76.04/76.29 97689[101:Spt:97688.0] || -> until2p7(s21)*. % 76.04/76.29 97690[101:MRR:217.0,97689.0] || -> until2p7(s22)* node4(s21). % 76.04/76.29 97691[102:Spt:97690.0] || -> until2p7(s22)*. % 76.04/76.29 97692[102:MRR:218.0,97691.0] || -> until2p7(s23)* node4(s22). % 76.04/76.29 97693[103:Spt:97692.0] || -> until2p7(s23)*. % 76.04/76.29 97694[103:MRR:219.0,97693.0] || -> until2p7(s24)* node4(s23). % 76.04/76.29 97695[104:Spt:97694.0] || -> until2p7(s24)*. % 76.04/76.29 97696[104:MRR:220.0,97695.0] || -> until2p7(s25)* node4(s24). % 76.04/76.29 97697[105:Spt:97696.0] || -> until2p7(s25)*. % 76.04/76.29 97698[105:MRR:221.0,97697.0] || -> until2p7(s26)* node4(s25). % 76.04/76.29 97699[106:Spt:97698.0] || -> until2p7(s26)*. % 76.04/76.29 97700[106:MRR:222.0,97699.0] || -> until2p7(s27)* node4(s26). % 76.04/76.29 97701[107:Spt:97700.0] || -> until2p7(s27)*. % 76.04/76.29 97702[107:MRR:223.0,97701.0] || -> until2p7(s28)* node4(s27). % 76.04/76.29 97703[108:Spt:97702.0] || -> until2p7(s28)*. % 76.04/76.29 97704[108:MRR:224.0,97703.0] || -> until2p7(s29)* node4(s28). % 76.04/76.29 97705[109:Spt:97704.0] || -> until2p7(s29)*. % 76.04/76.29 97706[109:MRR:225.0,97705.0] || -> until2p7(s30)* node4(s29). % 76.04/76.29 97707[110:Spt:97706.0] || -> until2p7(s30)*. % 76.04/76.29 97708[110:MRR:226.0,97707.0] || -> until2p7(s31)* node4(s30). % 76.04/76.29 97709[111:Spt:97708.0] || -> until2p7(s31)*. % 76.04/76.29 97710[111:MRR:227.0,97709.0] || -> until2p7(s32)* node4(s31). % 76.04/76.29 97711[112:Spt:97710.0] || -> until2p7(s32)*. % 76.04/76.29 97712[112:MRR:228.0,97711.0] || -> until2p7(s33)* node4(s32). % 76.04/76.29 97713[113:Spt:97712.0] || -> until2p7(s33)*. % 76.04/76.29 97714[113:MRR:229.0,97713.0] || -> until2p7(s34)* node4(s33). % 76.04/76.29 97715[114:Spt:97714.0] || -> until2p7(s34)*. % 76.04/76.29 97716[114:MRR:230.0,97715.0] || -> until2p7(s35)* node4(s34). % 76.04/76.29 97717[115:Spt:97716.0] || -> until2p7(s35)*. % 76.04/76.29 97718[115:MRR:231.0,97717.0] || -> until2p7(s36)* node4(s35). % 76.04/76.29 97719[116:Spt:97718.0] || -> until2p7(s36)*. % 76.04/76.29 97720[116:MRR:232.0,97719.0] || -> until2p7(s37)* node4(s36). % 76.04/76.29 97721[117:Spt:97720.0] || -> until2p7(s37)*. % 76.04/76.29 97722[117:MRR:235.0,97721.0] || -> until2p7(s38)* node4(s37). % 76.04/76.29 97723[118:Spt:97722.0] || -> until2p7(s38)*. % 76.04/76.29 97724[118:MRR:236.0,97723.0] || -> until2p7(s39)* node4(s38). % 76.04/76.29 97725[119:Spt:97724.0] || -> until2p7(s39)*. % 76.04/76.29 97726[119:MRR:237.0,97725.0] || -> until2p7(s40)* node4(s39). % 76.04/76.29 97727[120:Spt:97726.0] || -> until2p7(s40)*. % 76.04/76.29 97728[120:MRR:238.0,97727.0] || -> until2p7(s41)* node4(s40). % 76.04/76.29 97729[121:Spt:97728.0] || -> until2p7(s41)*. % 76.04/76.29 97730[121:MRR:239.0,97729.0] || -> until2p7(s42)* node4(s41). % 76.04/76.29 97731[122:Spt:97730.0] || -> until2p7(s42)*. % 76.04/76.29 97732[122:MRR:240.0,97731.0] || -> until2p7(s43)* node4(s42). % 76.04/76.29 97733[123:Spt:97732.0] || -> until2p7(s43)*. % 76.04/76.29 97734[123:MRR:241.0,97733.0] || -> until2p7(s44)* node4(s43). % 76.04/76.29 97735[124:Spt:97734.0] || -> until2p7(s44)*. % 76.04/76.29 97736[124:MRR:539.0,97735.0] || -> until2p7(s45)* node4(s44). % 76.04/76.29 97737[125:Spt:97736.0] || -> until2p7(s45)*. % 76.04/76.29 97738[125:MRR:544.0,97737.0] || -> until2p7(s46)* node4(s45). % 76.04/76.29 97739[126:Spt:97738.0] || -> until2p7(s46)*. % 76.04/76.29 97740[126:MRR:549.0,97739.0] || -> until2p7(s47)* node4(s46). % 76.04/76.29 97741[127:Spt:97740.0] || -> until2p7(s47)*. % 76.04/76.29 97742[127:MRR:554.0,97741.0] || -> until2p7(s48)* node4(s47). % 76.04/76.29 97743[128:Spt:97742.0] || -> until2p7(s48)*. % 76.04/76.29 97744[128:MRR:559.0,97743.0] || -> until2p7(s49)* node4(s48). % 76.04/76.29 97745[129:Spt:97744.0] || -> until2p7(s49)*. % 76.04/76.29 97746[129:MRR:194.0,97745.0] || -> node4(s49)*. % 76.04/76.29 97747[129:MRR:97665.0,97746.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.29 97751[129:Res:53.1,97747.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.29 97753[129:MRR:97751.0,78381.0] || -> . % 76.04/76.29 97754[129:Spt:97753.0,97744.0,97745.0] || until2p7(s49)*+ -> . % 76.04/76.29 97755[129:Spt:97753.0,97744.1] || -> node4(s48)*. % 76.04/76.29 97756[129:MRR:78384.0,97755.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.29 97759[129:Res:53.1,97756.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 97762[129:Res:97759.0,61.1] always3(s48) || -> . % 76.04/76.29 97763[129:SSi:97762.0,78281.0,78387.0,78626.0,97743.0,97755.0] || -> . % 76.04/76.29 97764[128:Spt:97763.0,97742.0,97743.0] || until2p7(s48)*+ -> . % 76.04/76.29 97765[128:Spt:97763.0,97742.1] || -> node4(s47)*. % 76.04/76.29 97767[128:MRR:777.0,97765.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.29 97779[128:Res:53.1,97767.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.29 97781[129:Spt:97779.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 97783[129:Res:97781.0,61.1] always3(s47) || -> . % 76.04/76.29 97784[129:SSi:97783.0,78277.0,78280.0,78625.0,97741.0,97765.0] || -> . % 76.04/76.29 97785[129:Spt:97784.0,97779.0,97781.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.29 97786[129:Spt:97784.0,97779.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 97790[129:Res:97786.0,61.1] always3(s48) || -> . % 76.04/76.29 97791[129:SSi:97790.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.29 97792[127:Spt:97791.0,97740.0,97741.0] || until2p7(s47)*+ -> . % 76.04/76.29 97793[127:Spt:97791.0,97740.1] || -> node4(s46)*. % 76.04/76.29 97795[127:MRR:780.0,97793.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.29 97802[127:Res:53.1,97795.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.29 97807[128:Spt:97802.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 97809[128:Res:97807.0,61.1] always3(s46) || -> . % 76.04/76.29 97810[128:SSi:97809.0,78272.0,78276.0,78624.0,97739.0,97793.0] || -> . % 76.04/76.29 97811[128:Spt:97810.0,97802.0,97807.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.29 97812[128:Spt:97810.0,97802.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 97816[128:Res:97812.0,61.1] always3(s47) || -> . % 76.04/76.29 97817[128:SSi:97816.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.29 97818[126:Spt:97817.0,97738.0,97739.0] || until2p7(s46)*+ -> . % 76.04/76.29 97819[126:Spt:97817.0,97738.1] || -> node4(s45)*. % 76.04/76.29 97821[126:MRR:783.0,97819.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.29 97824[126:Res:53.1,97821.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.29 97826[127:Spt:97824.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 97828[127:Res:97826.0,61.1] always3(s45) || -> . % 76.04/76.29 97829[127:SSi:97828.0,78268.0,78271.0,78623.0,97737.0,97819.0] || -> . % 76.04/76.29 97830[127:Spt:97829.0,97824.0,97826.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.29 97831[127:Spt:97829.0,97824.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 97835[127:Res:97831.0,61.1] always3(s46) || -> . % 76.04/76.29 97836[127:SSi:97835.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.29 97837[125:Spt:97836.0,97736.0,97737.0] || until2p7(s45)*+ -> . % 76.04/76.29 97838[125:Spt:97836.0,97736.1] || -> node4(s44)*. % 76.04/76.29 97840[125:MRR:786.0,97838.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.29 97843[125:Res:53.1,97840.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.29 97845[126:Spt:97843.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 97847[126:Res:97845.0,61.1] always3(s44) || -> . % 76.04/76.29 97848[126:SSi:97847.0,78263.0,78267.0,78622.0,97735.0,97838.0] || -> . % 76.04/76.29 97849[126:Spt:97848.0,97843.0,97845.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.29 97850[126:Spt:97848.0,97843.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 97854[126:Res:97850.0,61.1] always3(s45) || -> . % 76.04/76.29 97855[126:SSi:97854.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.29 97856[124:Spt:97855.0,97734.0,97735.0] || until2p7(s44)*+ -> . % 76.04/76.29 97857[124:Spt:97855.0,97734.1] || -> node4(s43)*. % 76.04/76.29 97859[124:MRR:789.0,97857.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.29 97862[124:Res:53.1,97859.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.29 97864[125:Spt:97862.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 97866[125:Res:97864.0,61.1] always3(s43) || -> . % 76.04/76.29 97867[125:SSi:97866.0,78259.0,78262.0,78621.0,97733.0,97857.0] || -> . % 76.04/76.29 97868[125:Spt:97867.0,97862.0,97864.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.29 97869[125:Spt:97867.0,97862.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 97873[125:Res:97869.0,61.1] always3(s44) || -> . % 76.04/76.29 97874[125:SSi:97873.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.29 97875[123:Spt:97874.0,97732.0,97733.0] || until2p7(s43)*+ -> . % 76.04/76.29 97876[123:Spt:97874.0,97732.1] || -> node4(s42)*. % 76.04/76.29 97878[123:MRR:792.0,97876.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.29 97881[123:Res:53.1,97878.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.29 97886[124:Spt:97881.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 97888[124:Res:97886.0,61.1] always3(s42) || -> . % 76.04/76.29 97889[124:SSi:97888.0,78254.0,78258.0,78620.0,97731.0,97876.0] || -> . % 76.04/76.29 97890[124:Spt:97889.0,97881.0,97886.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.29 97891[124:Spt:97889.0,97881.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 97895[124:Res:97891.0,61.1] always3(s43) || -> . % 76.04/76.29 97896[124:SSi:97895.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.29 97897[122:Spt:97896.0,97730.0,97731.0] || until2p7(s42)*+ -> . % 76.04/76.29 97898[122:Spt:97896.0,97730.1] || -> node4(s41)*. % 76.04/76.29 97900[122:MRR:795.0,97898.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.29 97903[122:Res:53.1,97900.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.29 97905[123:Spt:97903.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 97907[123:Res:97905.0,61.1] always3(s41) || -> . % 76.04/76.29 97908[123:SSi:97907.0,78250.0,78253.0,78619.0,97729.0,97898.0] || -> . % 76.04/76.29 97909[123:Spt:97908.0,97903.0,97905.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.29 97910[123:Spt:97908.0,97903.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 97914[123:Res:97910.0,61.1] always3(s42) || -> . % 76.04/76.29 97915[123:SSi:97914.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.29 97916[121:Spt:97915.0,97728.0,97729.0] || until2p7(s41)*+ -> . % 76.04/76.29 97917[121:Spt:97915.0,97728.1] || -> node4(s40)*. % 76.04/76.29 97919[121:MRR:798.0,97917.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.29 97922[121:Res:53.1,97919.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.29 97924[122:Spt:97922.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 97926[122:Res:97924.0,61.1] always3(s40) || -> . % 76.04/76.29 97927[122:SSi:97926.0,78245.0,78249.0,78618.0,97727.0,97917.0] || -> . % 76.04/76.29 97928[122:Spt:97927.0,97922.0,97924.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.29 97929[122:Spt:97927.0,97922.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 97933[122:Res:97929.0,61.1] always3(s41) || -> . % 76.04/76.29 97934[122:SSi:97933.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.29 97935[120:Spt:97934.0,97726.0,97727.0] || until2p7(s40)*+ -> . % 76.04/76.29 97936[120:Spt:97934.0,97726.1] || -> node4(s39)*. % 76.04/76.29 97938[120:MRR:801.0,97936.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.29 97941[120:Res:53.1,97938.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.29 97943[121:Spt:97941.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 97945[121:Res:97943.0,61.1] always3(s39) || -> . % 76.04/76.29 97946[121:SSi:97945.0,78241.0,78244.0,78617.0,97725.0,97936.0] || -> . % 76.04/76.29 97947[121:Spt:97946.0,97941.0,97943.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.29 97948[121:Spt:97946.0,97941.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 97952[121:Res:97948.0,61.1] always3(s40) || -> . % 76.04/76.29 97953[121:SSi:97952.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.29 97954[119:Spt:97953.0,97724.0,97725.0] || until2p7(s39)*+ -> . % 76.04/76.29 97955[119:Spt:97953.0,97724.1] || -> node4(s38)*. % 76.04/76.29 97957[119:MRR:804.0,97955.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.29 97960[119:Res:53.1,97957.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.29 97965[120:Spt:97960.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 97967[120:Res:97965.0,61.1] always3(s38) || -> . % 76.04/76.29 97968[120:SSi:97967.0,78236.0,78240.0,78616.0,97723.0,97955.0] || -> . % 76.04/76.29 97969[120:Spt:97968.0,97960.0,97965.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.29 97970[120:Spt:97968.0,97960.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 97974[120:Res:97970.0,61.1] always3(s39) || -> . % 76.04/76.29 97975[120:SSi:97974.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.29 97976[118:Spt:97975.0,97722.0,97723.0] || until2p7(s38)*+ -> . % 76.04/76.29 97977[118:Spt:97975.0,97722.1] || -> node4(s37)*. % 76.04/76.29 97979[118:MRR:807.0,97977.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.29 97982[118:Res:53.1,97979.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.29 97984[119:Spt:97982.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 97986[119:Res:97984.0,61.1] always3(s37) || -> . % 76.04/76.29 97987[119:SSi:97986.0,78232.0,78235.0,78615.0,97721.0,97977.0] || -> . % 76.04/76.29 97988[119:Spt:97987.0,97982.0,97984.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.29 97989[119:Spt:97987.0,97982.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 97993[119:Res:97989.0,61.1] always3(s38) || -> . % 76.04/76.29 97994[119:SSi:97993.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.29 97995[117:Spt:97994.0,97720.0,97721.0] || until2p7(s37)*+ -> . % 76.04/76.29 97996[117:Spt:97994.0,97720.1] || -> node4(s36)*. % 76.04/76.29 97998[117:MRR:810.0,97996.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.29 98001[117:Res:53.1,97998.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.29 98003[118:Spt:98001.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 98005[118:Res:98003.0,61.1] always3(s36) || -> . % 76.04/76.29 98006[118:SSi:98005.0,78227.0,78231.0,78614.0,97719.0,97996.0] || -> . % 76.04/76.29 98007[118:Spt:98006.0,98001.0,98003.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.29 98008[118:Spt:98006.0,98001.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 98012[118:Res:98008.0,61.1] always3(s37) || -> . % 76.04/76.29 98013[118:SSi:98012.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.29 98014[116:Spt:98013.0,97718.0,97719.0] || until2p7(s36)*+ -> . % 76.04/76.29 98015[116:Spt:98013.0,97718.1] || -> node4(s35)*. % 76.04/76.29 98017[116:MRR:813.0,98015.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.29 98020[116:Res:53.1,98017.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.29 98022[117:Spt:98020.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 98024[117:Res:98022.0,61.1] always3(s35) || -> . % 76.04/76.29 98025[117:SSi:98024.0,78223.0,78226.0,78613.0,97717.0,98015.0] || -> . % 76.04/76.29 98026[117:Spt:98025.0,98020.0,98022.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.29 98027[117:Spt:98025.0,98020.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 98031[117:Res:98027.0,61.1] always3(s36) || -> . % 76.04/76.29 98032[117:SSi:98031.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.29 98033[115:Spt:98032.0,97716.0,97717.0] || until2p7(s35)*+ -> . % 76.04/76.29 98034[115:Spt:98032.0,97716.1] || -> node4(s34)*. % 76.04/76.29 98036[115:MRR:816.0,98034.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.29 98039[115:Res:53.1,98036.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.29 98044[116:Spt:98039.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 98046[116:Res:98044.0,61.1] always3(s34) || -> . % 76.04/76.29 98047[116:SSi:98046.0,78218.0,78222.0,78612.0,97715.0,98034.0] || -> . % 76.04/76.29 98048[116:Spt:98047.0,98039.0,98044.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.29 98049[116:Spt:98047.0,98039.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 98053[116:Res:98049.0,61.1] always3(s35) || -> . % 76.04/76.29 98054[116:SSi:98053.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.29 98055[114:Spt:98054.0,97714.0,97715.0] || until2p7(s34)*+ -> . % 76.04/76.29 98056[114:Spt:98054.0,97714.1] || -> node4(s33)*. % 76.04/76.29 98058[114:MRR:819.0,98056.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.29 98061[114:Res:53.1,98058.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.29 98063[115:Spt:98061.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 98065[115:Res:98063.0,61.1] always3(s33) || -> . % 76.04/76.29 98066[115:SSi:98065.0,78214.0,78217.0,78611.0,97713.0,98056.0] || -> . % 76.04/76.29 98067[115:Spt:98066.0,98061.0,98063.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.29 98068[115:Spt:98066.0,98061.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 98072[115:Res:98068.0,61.1] always3(s34) || -> . % 76.04/76.29 98073[115:SSi:98072.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.29 98074[113:Spt:98073.0,97712.0,97713.0] || until2p7(s33)*+ -> . % 76.04/76.29 98075[113:Spt:98073.0,97712.1] || -> node4(s32)*. % 76.04/76.29 98077[113:MRR:822.0,98075.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.29 98080[113:Res:53.1,98077.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.29 98082[114:Spt:98080.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 98084[114:Res:98082.0,61.1] always3(s32) || -> . % 76.04/76.29 98085[114:SSi:98084.0,78209.0,78213.0,78610.0,97711.0,98075.0] || -> . % 76.04/76.29 98086[114:Spt:98085.0,98080.0,98082.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.29 98087[114:Spt:98085.0,98080.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 98091[114:Res:98087.0,61.1] always3(s33) || -> . % 76.04/76.29 98092[114:SSi:98091.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.29 98093[112:Spt:98092.0,97710.0,97711.0] || until2p7(s32)*+ -> . % 76.04/76.29 98094[112:Spt:98092.0,97710.1] || -> node4(s31)*. % 76.04/76.29 98096[112:MRR:825.0,98094.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.29 98099[112:Res:53.1,98096.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.29 98101[113:Spt:98099.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 98103[113:Res:98101.0,61.1] always3(s31) || -> . % 76.04/76.29 98104[113:SSi:98103.0,78205.0,78208.0,78609.0,97709.0,98094.0] || -> . % 76.04/76.29 98105[113:Spt:98104.0,98099.0,98101.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.29 98106[113:Spt:98104.0,98099.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 98110[113:Res:98106.0,61.1] always3(s32) || -> . % 76.04/76.29 98111[113:SSi:98110.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.29 98112[111:Spt:98111.0,97708.0,97709.0] || until2p7(s31)*+ -> . % 76.04/76.29 98113[111:Spt:98111.0,97708.1] || -> node4(s30)*. % 76.04/76.29 98115[111:MRR:828.0,98113.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.29 98118[111:Res:53.1,98115.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.29 98123[112:Spt:98118.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 98125[112:Res:98123.0,61.1] always3(s30) || -> . % 76.04/76.29 98126[112:SSi:98125.0,78200.0,78204.0,78608.0,97707.0,98113.0] || -> . % 76.04/76.29 98127[112:Spt:98126.0,98118.0,98123.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.29 98128[112:Spt:98126.0,98118.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 98132[112:Res:98128.0,61.1] always3(s31) || -> . % 76.04/76.29 98133[112:SSi:98132.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.29 98134[110:Spt:98133.0,97706.0,97707.0] || until2p7(s30)*+ -> . % 76.04/76.29 98135[110:Spt:98133.0,97706.1] || -> node4(s29)*. % 76.04/76.29 98137[110:MRR:831.0,98135.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.29 98140[110:Res:53.1,98137.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.29 98142[111:Spt:98140.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 98144[111:Res:98142.0,61.1] always3(s29) || -> . % 76.04/76.29 98145[111:SSi:98144.0,78196.0,78199.0,78607.0,97705.0,98135.0] || -> . % 76.04/76.29 98146[111:Spt:98145.0,98140.0,98142.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.29 98147[111:Spt:98145.0,98140.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 98151[111:Res:98147.0,61.1] always3(s30) || -> . % 76.04/76.29 98152[111:SSi:98151.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.29 98153[109:Spt:98152.0,97704.0,97705.0] || until2p7(s29)*+ -> . % 76.04/76.29 98154[109:Spt:98152.0,97704.1] || -> node4(s28)*. % 76.04/76.29 98156[109:MRR:834.0,98154.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.29 98159[109:Res:53.1,98156.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.29 98161[110:Spt:98159.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 98163[110:Res:98161.0,61.1] always3(s28) || -> . % 76.04/76.29 98164[110:SSi:98163.0,78191.0,78195.0,78606.0,97703.0,98154.0] || -> . % 76.04/76.29 98165[110:Spt:98164.0,98159.0,98161.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.29 98166[110:Spt:98164.0,98159.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 98170[110:Res:98166.0,61.1] always3(s29) || -> . % 76.04/76.29 98171[110:SSi:98170.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.29 98172[108:Spt:98171.0,97702.0,97703.0] || until2p7(s28)*+ -> . % 76.04/76.29 98173[108:Spt:98171.0,97702.1] || -> node4(s27)*. % 76.04/76.29 98175[108:MRR:837.0,98173.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.29 98178[108:Res:53.1,98175.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.29 98180[109:Spt:98178.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 98182[109:Res:98180.0,61.1] always3(s27) || -> . % 76.04/76.29 98183[109:SSi:98182.0,78187.0,78190.0,78605.0,97701.0,98173.0] || -> . % 76.04/76.29 98184[109:Spt:98183.0,98178.0,98180.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.29 98185[109:Spt:98183.0,98178.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 98189[109:Res:98185.0,61.1] always3(s28) || -> . % 76.04/76.29 98190[109:SSi:98189.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.29 98191[107:Spt:98190.0,97700.0,97701.0] || until2p7(s27)*+ -> . % 76.04/76.29 98192[107:Spt:98190.0,97700.1] || -> node4(s26)*. % 76.04/76.29 98194[107:MRR:840.0,98192.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.29 98197[107:Res:53.1,98194.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.29 98202[108:Spt:98197.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 98204[108:Res:98202.0,61.1] always3(s26) || -> . % 76.04/76.29 98205[108:SSi:98204.0,78182.0,78186.0,78604.0,97699.0,98192.0] || -> . % 76.04/76.29 98206[108:Spt:98205.0,98197.0,98202.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.29 98207[108:Spt:98205.0,98197.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 98211[108:Res:98207.0,61.1] always3(s27) || -> . % 76.04/76.29 98212[108:SSi:98211.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.29 98213[106:Spt:98212.0,97698.0,97699.0] || until2p7(s26)*+ -> . % 76.04/76.29 98214[106:Spt:98212.0,97698.1] || -> node4(s25)*. % 76.04/76.29 98216[106:MRR:843.0,98214.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.29 98219[106:Res:53.1,98216.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.29 98221[107:Spt:98219.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 98223[107:Res:98221.0,61.1] always3(s25) || -> . % 76.04/76.29 98224[107:SSi:98223.0,78178.0,78181.0,78603.0,97697.0,98214.0] || -> . % 76.04/76.29 98225[107:Spt:98224.0,98219.0,98221.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.29 98226[107:Spt:98224.0,98219.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.29 98230[107:Res:98226.0,61.1] always3(s26) || -> . % 76.04/76.29 98231[107:SSi:98230.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.29 98232[105:Spt:98231.0,97696.0,97697.0] || until2p7(s25)*+ -> . % 76.04/76.29 98233[105:Spt:98231.0,97696.1] || -> node4(s24)*. % 76.04/76.29 98235[105:MRR:846.0,98233.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.29 98238[105:Res:53.1,98235.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.29 98240[106:Spt:98238.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 98242[106:Res:98240.0,61.1] always3(s24) || -> . % 76.04/76.29 98243[106:SSi:98242.0,78173.0,78177.0,78602.0,97695.0,98233.0] || -> . % 76.04/76.29 98244[106:Spt:98243.0,98238.0,98240.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.29 98245[106:Spt:98243.0,98238.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.29 98249[106:Res:98245.0,61.1] always3(s25) || -> . % 76.04/76.29 98250[106:SSi:98249.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.29 98251[104:Spt:98250.0,97694.0,97695.0] || until2p7(s24)*+ -> . % 76.04/76.29 98252[104:Spt:98250.0,97694.1] || -> node4(s23)*. % 76.04/76.29 98254[104:MRR:849.0,98252.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.29 98257[104:Res:53.1,98254.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.29 98259[105:Spt:98257.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 98261[105:Res:98259.0,61.1] always3(s23) || -> . % 76.04/76.29 98262[105:SSi:98261.0,78169.0,78172.0,78601.0,97693.0,98252.0] || -> . % 76.04/76.29 98263[105:Spt:98262.0,98257.0,98259.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.29 98264[105:Spt:98262.0,98257.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.29 98268[105:Res:98264.0,61.1] always3(s24) || -> . % 76.04/76.29 98269[105:SSi:98268.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.29 98270[103:Spt:98269.0,97692.0,97693.0] || until2p7(s23)*+ -> . % 76.04/76.29 98271[103:Spt:98269.0,97692.1] || -> node4(s22)*. % 76.04/76.29 98273[103:MRR:852.0,98271.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.29 98276[103:Res:53.1,98273.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.29 98281[104:Spt:98276.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 98283[104:Res:98281.0,61.1] always3(s22) || -> . % 76.04/76.29 98284[104:SSi:98283.0,78164.0,78168.0,78600.0,97691.0,98271.0] || -> . % 76.04/76.29 98285[104:Spt:98284.0,98276.0,98281.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.29 98286[104:Spt:98284.0,98276.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.29 98290[104:Res:98286.0,61.1] always3(s23) || -> . % 76.04/76.29 98291[104:SSi:98290.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.29 98292[102:Spt:98291.0,97690.0,97691.0] || until2p7(s22)*+ -> . % 76.04/76.29 98293[102:Spt:98291.0,97690.1] || -> node4(s21)*. % 76.04/76.29 98295[102:MRR:855.0,98293.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.29 98298[102:Res:53.1,98295.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.29 98300[103:Spt:98298.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 98302[103:Res:98300.0,61.1] always3(s21) || -> . % 76.04/76.29 98303[103:SSi:98302.0,78160.0,78163.0,78599.0,97689.0,98293.0] || -> . % 76.04/76.29 98304[103:Spt:98303.0,98298.0,98300.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.29 98305[103:Spt:98303.0,98298.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.29 98309[103:Res:98305.0,61.1] always3(s22) || -> . % 76.04/76.29 98310[103:SSi:98309.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.29 98311[101:Spt:98310.0,97688.0,97689.0] || until2p7(s21)*+ -> . % 76.04/76.29 98312[101:Spt:98310.0,97688.1] || -> node4(s20)*. % 76.04/76.29 98314[101:MRR:858.0,98312.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.29 98317[101:Res:53.1,98314.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.29 98319[102:Spt:98317.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 98321[102:Res:98319.0,61.1] always3(s20) || -> . % 76.04/76.29 98322[102:SSi:98321.0,78155.0,78159.0,78598.0,97687.0,98312.0] || -> . % 76.04/76.29 98323[102:Spt:98322.0,98317.0,98319.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.29 98324[102:Spt:98322.0,98317.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.29 98328[102:Res:98324.0,61.1] always3(s21) || -> . % 76.04/76.29 98329[102:SSi:98328.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.29 98330[100:Spt:98329.0,97686.0,97687.0] || until2p7(s20)*+ -> . % 76.04/76.29 98331[100:Spt:98329.0,97686.1] || -> node4(s19)*. % 76.04/76.29 98333[100:MRR:861.0,98331.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.29 98336[100:Res:53.1,98333.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.29 98338[101:Spt:98336.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 98340[101:Res:98338.0,61.1] always3(s19) || -> . % 76.04/76.29 98341[101:SSi:98340.0,78151.0,78154.0,78597.0,97685.0,98331.0] || -> . % 76.04/76.29 98342[101:Spt:98341.0,98336.0,98338.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.29 98343[101:Spt:98341.0,98336.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.29 98347[101:Res:98343.0,61.1] always3(s20) || -> . % 76.04/76.29 98348[101:SSi:98347.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.29 98349[99:Spt:98348.0,97684.0,97685.0] || until2p7(s19)*+ -> . % 76.04/76.29 98350[99:Spt:98348.0,97684.1] || -> node4(s18)*. % 76.04/76.29 98352[99:MRR:864.0,98350.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.29 98355[99:Res:53.1,98352.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.29 98360[100:Spt:98355.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 98362[100:Res:98360.0,61.1] always3(s18) || -> . % 76.04/76.29 98363[100:SSi:98362.0,78146.0,78150.0,78596.0,97683.0,98350.0] || -> . % 76.04/76.29 98364[100:Spt:98363.0,98355.0,98360.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.29 98365[100:Spt:98363.0,98355.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.29 98369[100:Res:98365.0,61.1] always3(s19) || -> . % 76.04/76.29 98370[100:SSi:98369.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.29 98371[98:Spt:98370.0,97682.0,97683.0] || until2p7(s18)*+ -> . % 76.04/76.29 98372[98:Spt:98370.0,97682.1] || -> node4(s17)*. % 76.04/76.29 98374[98:MRR:867.0,98372.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.29 98377[98:Res:53.1,98374.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.29 98379[99:Spt:98377.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 98381[99:Res:98379.0,61.1] always3(s17) || -> . % 76.04/76.29 98382[99:SSi:98381.0,78142.0,78145.0,78595.0,97681.0,98372.0] || -> . % 76.04/76.29 98383[99:Spt:98382.0,98377.0,98379.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.29 98384[99:Spt:98382.0,98377.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.29 98388[99:Res:98384.0,61.1] always3(s18) || -> . % 76.04/76.29 98389[99:SSi:98388.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.29 98390[97:Spt:98389.0,97680.0,97681.0] || until2p7(s17)*+ -> . % 76.04/76.29 98391[97:Spt:98389.0,97680.1] || -> node4(s16)*. % 76.04/76.29 98393[97:MRR:870.0,98391.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.29 98396[97:Res:53.1,98393.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.29 98398[98:Spt:98396.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.29 98400[98:Res:98398.0,61.1] always3(s16) || -> . % 76.04/76.29 98401[98:SSi:98400.0,78137.0,78141.0,78594.0,97679.0,98391.0] || -> . % 76.04/76.29 98402[98:Spt:98401.0,98396.0,98398.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.29 98403[98:Spt:98401.0,98396.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.29 98407[98:Res:98403.0,61.1] always3(s17) || -> . % 76.04/76.29 98408[98:SSi:98407.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.29 98409[96:Spt:98408.0,97678.0,97679.0] || until2p7(s16)*+ -> . % 76.04/76.29 98410[96:Spt:98408.0,97678.1] || -> node4(s15)*. % 76.04/76.29 98412[96:MRR:873.0,98410.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.29 98415[96:Res:53.1,98412.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.29 98417[97:Spt:98415.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.29 98419[97:Res:98417.0,61.1] always3(s15) || -> . % 76.04/76.29 98420[97:SSi:98419.0,78133.0,78136.0,78593.0,97677.0,98410.0] || -> . % 76.04/76.29 98421[97:Spt:98420.0,98415.0,98417.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.29 98422[97:Spt:98420.0,98415.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.29 98426[97:Res:98422.0,61.1] always3(s16) || -> . % 76.04/76.29 98427[97:SSi:98426.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.29 98428[95:Spt:98427.0,97676.0,97677.0] || until2p7(s15)*+ -> . % 76.04/76.29 98429[95:Spt:98427.0,97676.1] || -> node4(s14)*. % 76.04/76.29 98431[95:MRR:876.0,98429.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.29 98434[95:Res:53.1,98431.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.29 98439[96:Spt:98434.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.29 98441[96:Res:98439.0,61.1] always3(s14) || -> . % 76.04/76.29 98442[96:SSi:98441.0,78128.0,78132.0,78592.0,97675.0,98429.0] || -> . % 76.04/76.29 98443[96:Spt:98442.0,98434.0,98439.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.29 98444[96:Spt:98442.0,98434.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.29 98448[96:Res:98444.0,61.1] always3(s15) || -> . % 76.04/76.29 98449[96:SSi:98448.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.29 98450[94:Spt:98449.0,97674.0,97675.0] || until2p7(s14)*+ -> . % 76.04/76.29 98451[94:Spt:98449.0,97674.1] || -> node4(s13)*. % 76.04/76.29 98453[94:MRR:879.0,98451.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.29 98456[94:Res:53.1,98453.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.29 98458[95:Spt:98456.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.29 98460[95:Res:98458.0,61.1] always3(s13) || -> . % 76.04/76.29 98461[95:SSi:98460.0,78124.0,78127.0,78591.0,97673.0,98451.0] || -> . % 76.04/76.29 98462[95:Spt:98461.0,98456.0,98458.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.29 98463[95:Spt:98461.0,98456.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.29 98467[95:Res:98463.0,61.1] always3(s14) || -> . % 76.04/76.29 98468[95:SSi:98467.0,78128.0,78132.0,78592.0] || -> . % 76.04/76.29 98469[93:Spt:98468.0,97672.0,97673.0] || until2p7(s13)*+ -> . % 76.04/76.29 98470[93:Spt:98468.0,97672.1] || -> node4(s12)*. % 76.04/76.29 98472[93:MRR:882.0,98470.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.29 98475[93:Res:53.1,98472.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.29 98477[94:Spt:98475.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.29 98479[94:Res:98477.0,61.1] always3(s12) || -> . % 76.04/76.29 98480[94:SSi:98479.0,78119.0,78123.0,78590.0,97671.0,98470.0] || -> . % 76.04/76.29 98481[94:Spt:98480.0,98475.0,98477.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.29 98482[94:Spt:98480.0,98475.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.29 98486[94:Res:98482.0,61.1] always3(s13) || -> . % 76.04/76.29 98487[94:SSi:98486.0,78124.0,78127.0,78591.0] || -> . % 76.04/76.29 98488[92:Spt:98487.0,97670.0,97671.0] || until2p7(s12)*+ -> . % 76.04/76.29 98489[92:Spt:98487.0,97670.1] || -> node4(s11)*. % 76.04/76.29 98491[92:MRR:885.0,98489.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.29 98494[92:Res:53.1,98491.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.29 98496[92:MRR:98494.0,97660.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.29 98498[92:Res:98496.0,61.1] always3(s12) || -> . % 76.04/76.29 98499[92:SSi:98498.0,78119.0,78123.0,78590.0] || -> . % 76.04/76.29 98500[90:Spt:98499.0,97519.0,97522.0] || trans(s49,s11)*+ -> . % 76.04/76.29 98501[90:Spt:98499.0,97519.1,97519.2,97519.3,97519.4,97519.5,97519.6,97519.7,97519.8,97519.9] || -> trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.29 98503[90:MRR:97521.1,98500.0] xuntil6(s49) || -> trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.29 98504[91:Spt:98501.0] || -> trans(s49,s10)*. % 76.04/76.29 98505[91:Res:98504.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s10)*. % 76.04/76.29 98507[91:Res:98504.0,60.0] || -> node2(s49,s10)*. % 76.04/76.29 98508[91:SSi:98505.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s10)*. % 76.04/76.29 98509[91:Res:98507.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)*. % 76.04/76.29 98641[91:SoR:98509.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)*. % 76.04/76.29 98643[91:SoR:98641.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)* xuntil6(s49). % 76.04/76.29 98644[91:SSi:98643.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s10,c_busy)* xuntil6(s49). % 76.04/76.29 98645[92:Spt:98644.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.29 98647[92:Res:98645.0,61.1] always3(s10) || -> . % 76.04/76.29 98648[92:SSi:98647.0,78110.0,78114.0,78588.0] || -> . % 76.04/76.29 98649[92:Spt:98648.0,98644.1,98645.0] || m_main_v_state(s10,c_busy)*+ -> . % 76.04/76.29 98650[92:Spt:98648.0,98644.0,98644.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.29 98654[92:MRR:98641.2,98649.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.29 98655[92:Res:53.1,98650.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.29 98657[92:MRR:98655.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.29 98658[92:MRR:98508.0,98657.0] || -> until2p7(s10)*. % 76.04/76.29 98659[92:MRR:206.0,98658.0] || -> until2p7(s11)* node4(s10). % 76.04/76.29 98660[93:Spt:98659.0] || -> until2p7(s11)*. % 76.04/76.29 98661[93:MRR:207.0,98660.0] || -> until2p7(s12)* node4(s11). % 76.04/76.29 98662[94:Spt:98661.0] || -> until2p7(s12)*. % 76.04/76.29 98663[94:MRR:208.0,98662.0] || -> until2p7(s13)* node4(s12). % 76.04/76.29 98664[95:Spt:98663.0] || -> until2p7(s13)*. % 76.04/76.29 98665[95:MRR:209.0,98664.0] || -> until2p7(s14)* node4(s13). % 76.04/76.29 98666[96:Spt:98665.0] || -> until2p7(s14)*. % 76.04/76.29 98667[96:MRR:210.0,98666.0] || -> until2p7(s15)* node4(s14). % 76.04/76.29 98668[97:Spt:98667.0] || -> until2p7(s15)*. % 76.04/76.29 98669[97:MRR:211.0,98668.0] || -> until2p7(s16)* node4(s15). % 76.04/76.29 98670[98:Spt:98669.0] || -> until2p7(s16)*. % 76.04/76.29 98671[98:MRR:212.0,98670.0] || -> until2p7(s17)* node4(s16). % 76.04/76.29 98672[99:Spt:98671.0] || -> until2p7(s17)*. % 76.04/76.29 98673[99:MRR:213.0,98672.0] || -> until2p7(s18)* node4(s17). % 76.04/76.29 98674[100:Spt:98673.0] || -> until2p7(s18)*. % 76.04/76.29 98675[100:MRR:214.0,98674.0] || -> until2p7(s19)* node4(s18). % 76.04/76.29 98676[101:Spt:98675.0] || -> until2p7(s19)*. % 76.04/76.29 98677[101:MRR:215.0,98676.0] || -> until2p7(s20)* node4(s19). % 76.04/76.29 98678[102:Spt:98677.0] || -> until2p7(s20)*. % 76.04/76.29 98679[102:MRR:216.0,98678.0] || -> until2p7(s21)* node4(s20). % 76.04/76.29 98680[103:Spt:98679.0] || -> until2p7(s21)*. % 76.04/76.29 98681[103:MRR:217.0,98680.0] || -> until2p7(s22)* node4(s21). % 76.04/76.29 98682[104:Spt:98681.0] || -> until2p7(s22)*. % 76.04/76.29 98683[104:MRR:218.0,98682.0] || -> until2p7(s23)* node4(s22). % 76.04/76.29 98684[105:Spt:98683.0] || -> until2p7(s23)*. % 76.04/76.29 98685[105:MRR:219.0,98684.0] || -> until2p7(s24)* node4(s23). % 76.04/76.29 98686[106:Spt:98685.0] || -> until2p7(s24)*. % 76.04/76.29 98687[106:MRR:220.0,98686.0] || -> until2p7(s25)* node4(s24). % 76.04/76.29 98688[107:Spt:98687.0] || -> until2p7(s25)*. % 76.04/76.29 98689[107:MRR:221.0,98688.0] || -> until2p7(s26)* node4(s25). % 76.04/76.29 98690[108:Spt:98689.0] || -> until2p7(s26)*. % 76.04/76.29 98691[108:MRR:222.0,98690.0] || -> until2p7(s27)* node4(s26). % 76.04/76.29 98692[109:Spt:98691.0] || -> until2p7(s27)*. % 76.04/76.29 98693[109:MRR:223.0,98692.0] || -> until2p7(s28)* node4(s27). % 76.04/76.29 98694[110:Spt:98693.0] || -> until2p7(s28)*. % 76.04/76.29 98695[110:MRR:224.0,98694.0] || -> until2p7(s29)* node4(s28). % 76.04/76.29 98696[111:Spt:98695.0] || -> until2p7(s29)*. % 76.04/76.29 98697[111:MRR:225.0,98696.0] || -> until2p7(s30)* node4(s29). % 76.04/76.29 98698[112:Spt:98697.0] || -> until2p7(s30)*. % 76.04/76.29 98699[112:MRR:226.0,98698.0] || -> until2p7(s31)* node4(s30). % 76.04/76.29 98700[113:Spt:98699.0] || -> until2p7(s31)*. % 76.04/76.29 98701[113:MRR:227.0,98700.0] || -> until2p7(s32)* node4(s31). % 76.04/76.29 98702[114:Spt:98701.0] || -> until2p7(s32)*. % 76.04/76.29 98703[114:MRR:228.0,98702.0] || -> until2p7(s33)* node4(s32). % 76.04/76.29 98704[115:Spt:98703.0] || -> until2p7(s33)*. % 76.04/76.29 98705[115:MRR:229.0,98704.0] || -> until2p7(s34)* node4(s33). % 76.04/76.29 98706[116:Spt:98705.0] || -> until2p7(s34)*. % 76.04/76.29 98707[116:MRR:230.0,98706.0] || -> until2p7(s35)* node4(s34). % 76.04/76.29 98708[117:Spt:98707.0] || -> until2p7(s35)*. % 76.04/76.29 98709[117:MRR:231.0,98708.0] || -> until2p7(s36)* node4(s35). % 76.04/76.29 98710[118:Spt:98709.0] || -> until2p7(s36)*. % 76.04/76.29 98711[118:MRR:232.0,98710.0] || -> until2p7(s37)* node4(s36). % 76.04/76.29 98712[119:Spt:98711.0] || -> until2p7(s37)*. % 76.04/76.29 98713[119:MRR:235.0,98712.0] || -> until2p7(s38)* node4(s37). % 76.04/76.29 98714[120:Spt:98713.0] || -> until2p7(s38)*. % 76.04/76.29 98715[120:MRR:236.0,98714.0] || -> until2p7(s39)* node4(s38). % 76.04/76.29 98716[121:Spt:98715.0] || -> until2p7(s39)*. % 76.04/76.29 98717[121:MRR:237.0,98716.0] || -> until2p7(s40)* node4(s39). % 76.04/76.29 98718[122:Spt:98717.0] || -> until2p7(s40)*. % 76.04/76.29 98719[122:MRR:238.0,98718.0] || -> until2p7(s41)* node4(s40). % 76.04/76.29 98720[123:Spt:98719.0] || -> until2p7(s41)*. % 76.04/76.29 98721[123:MRR:239.0,98720.0] || -> until2p7(s42)* node4(s41). % 76.04/76.29 98722[124:Spt:98721.0] || -> until2p7(s42)*. % 76.04/76.29 98723[124:MRR:240.0,98722.0] || -> until2p7(s43)* node4(s42). % 76.04/76.29 98724[125:Spt:98723.0] || -> until2p7(s43)*. % 76.04/76.29 98725[125:MRR:241.0,98724.0] || -> until2p7(s44)* node4(s43). % 76.04/76.29 98726[126:Spt:98725.0] || -> until2p7(s44)*. % 76.04/76.29 98727[126:MRR:539.0,98726.0] || -> until2p7(s45)* node4(s44). % 76.04/76.29 98728[127:Spt:98727.0] || -> until2p7(s45)*. % 76.04/76.29 98729[127:MRR:544.0,98728.0] || -> until2p7(s46)* node4(s45). % 76.04/76.29 98730[128:Spt:98729.0] || -> until2p7(s46)*. % 76.04/76.29 98731[128:MRR:549.0,98730.0] || -> until2p7(s47)* node4(s46). % 76.04/76.29 98732[129:Spt:98731.0] || -> until2p7(s47)*. % 76.04/76.29 98733[129:MRR:554.0,98732.0] || -> until2p7(s48)* node4(s47). % 76.04/76.29 98734[130:Spt:98733.0] || -> until2p7(s48)*. % 76.04/76.29 98735[130:MRR:559.0,98734.0] || -> until2p7(s49)* node4(s48). % 76.04/76.29 98736[131:Spt:98735.0] || -> until2p7(s49)*. % 76.04/76.29 98737[131:MRR:194.0,98736.0] || -> node4(s49)*. % 76.04/76.29 98738[131:MRR:98654.0,98737.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.29 98739[131:Res:53.1,98738.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.29 98741[131:MRR:98739.0,78381.0] || -> . % 76.04/76.29 98742[131:Spt:98741.0,98735.0,98736.0] || until2p7(s49)*+ -> . % 76.04/76.29 98743[131:Spt:98741.0,98735.1] || -> node4(s48)*. % 76.04/76.29 98744[131:MRR:78384.0,98743.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.29 98747[131:Res:53.1,98744.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 98750[131:Res:98747.0,61.1] always3(s48) || -> . % 76.04/76.29 98751[131:SSi:98750.0,78281.0,78387.0,78626.0,98734.0,98743.0] || -> . % 76.04/76.29 98752[130:Spt:98751.0,98733.0,98734.0] || until2p7(s48)*+ -> . % 76.04/76.29 98753[130:Spt:98751.0,98733.1] || -> node4(s47)*. % 76.04/76.29 98755[130:MRR:777.0,98753.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.29 98770[130:Res:53.1,98755.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.29 98772[131:Spt:98770.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 98774[131:Res:98772.0,61.1] always3(s47) || -> . % 76.04/76.29 98775[131:SSi:98774.0,78277.0,78280.0,78625.0,98732.0,98753.0] || -> . % 76.04/76.29 98776[131:Spt:98775.0,98770.0,98772.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.29 98777[131:Spt:98775.0,98770.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.29 98781[131:Res:98777.0,61.1] always3(s48) || -> . % 76.04/76.29 98782[131:SSi:98781.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.29 98783[129:Spt:98782.0,98731.0,98732.0] || until2p7(s47)*+ -> . % 76.04/76.29 98784[129:Spt:98782.0,98731.1] || -> node4(s46)*. % 76.04/76.29 98786[129:MRR:780.0,98784.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.29 98796[129:Res:53.1,98786.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.29 98798[130:Spt:98796.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 98800[130:Res:98798.0,61.1] always3(s46) || -> . % 76.04/76.29 98801[130:SSi:98800.0,78272.0,78276.0,78624.0,98730.0,98784.0] || -> . % 76.04/76.29 98802[130:Spt:98801.0,98796.0,98798.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.29 98803[130:Spt:98801.0,98796.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.29 98807[130:Res:98803.0,61.1] always3(s47) || -> . % 76.04/76.29 98808[130:SSi:98807.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.29 98809[128:Spt:98808.0,98729.0,98730.0] || until2p7(s46)*+ -> . % 76.04/76.29 98810[128:Spt:98808.0,98729.1] || -> node4(s45)*. % 76.04/76.29 98812[128:MRR:783.0,98810.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.29 98815[128:Res:53.1,98812.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.29 98817[129:Spt:98815.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 98819[129:Res:98817.0,61.1] always3(s45) || -> . % 76.04/76.29 98820[129:SSi:98819.0,78268.0,78271.0,78623.0,98728.0,98810.0] || -> . % 76.04/76.29 98821[129:Spt:98820.0,98815.0,98817.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.29 98822[129:Spt:98820.0,98815.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.29 98826[129:Res:98822.0,61.1] always3(s46) || -> . % 76.04/76.29 98827[129:SSi:98826.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.29 98828[127:Spt:98827.0,98727.0,98728.0] || until2p7(s45)*+ -> . % 76.04/76.29 98829[127:Spt:98827.0,98727.1] || -> node4(s44)*. % 76.04/76.29 98831[127:MRR:786.0,98829.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.29 98834[127:Res:53.1,98831.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.29 98836[128:Spt:98834.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 98838[128:Res:98836.0,61.1] always3(s44) || -> . % 76.04/76.29 98839[128:SSi:98838.0,78263.0,78267.0,78622.0,98726.0,98829.0] || -> . % 76.04/76.29 98840[128:Spt:98839.0,98834.0,98836.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.29 98841[128:Spt:98839.0,98834.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.29 98845[128:Res:98841.0,61.1] always3(s45) || -> . % 76.04/76.29 98846[128:SSi:98845.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.29 98847[126:Spt:98846.0,98725.0,98726.0] || until2p7(s44)*+ -> . % 76.04/76.29 98848[126:Spt:98846.0,98725.1] || -> node4(s43)*. % 76.04/76.29 98850[126:MRR:789.0,98848.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.29 98853[126:Res:53.1,98850.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.29 98858[127:Spt:98853.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 98860[127:Res:98858.0,61.1] always3(s43) || -> . % 76.04/76.29 98861[127:SSi:98860.0,78259.0,78262.0,78621.0,98724.0,98848.0] || -> . % 76.04/76.29 98862[127:Spt:98861.0,98853.0,98858.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.29 98863[127:Spt:98861.0,98853.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.29 98867[127:Res:98863.0,61.1] always3(s44) || -> . % 76.04/76.29 98868[127:SSi:98867.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.29 98869[125:Spt:98868.0,98723.0,98724.0] || until2p7(s43)*+ -> . % 76.04/76.29 98870[125:Spt:98868.0,98723.1] || -> node4(s42)*. % 76.04/76.29 98872[125:MRR:792.0,98870.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.29 98875[125:Res:53.1,98872.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.29 98877[126:Spt:98875.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 98879[126:Res:98877.0,61.1] always3(s42) || -> . % 76.04/76.29 98880[126:SSi:98879.0,78254.0,78258.0,78620.0,98722.0,98870.0] || -> . % 76.04/76.29 98881[126:Spt:98880.0,98875.0,98877.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.29 98882[126:Spt:98880.0,98875.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.29 98886[126:Res:98882.0,61.1] always3(s43) || -> . % 76.04/76.29 98887[126:SSi:98886.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.29 98888[124:Spt:98887.0,98721.0,98722.0] || until2p7(s42)*+ -> . % 76.04/76.29 98889[124:Spt:98887.0,98721.1] || -> node4(s41)*. % 76.04/76.29 98891[124:MRR:795.0,98889.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.29 98894[124:Res:53.1,98891.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.29 98896[125:Spt:98894.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 98898[125:Res:98896.0,61.1] always3(s41) || -> . % 76.04/76.29 98899[125:SSi:98898.0,78250.0,78253.0,78619.0,98720.0,98889.0] || -> . % 76.04/76.29 98900[125:Spt:98899.0,98894.0,98896.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.29 98901[125:Spt:98899.0,98894.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.29 98905[125:Res:98901.0,61.1] always3(s42) || -> . % 76.04/76.29 98906[125:SSi:98905.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.29 98907[123:Spt:98906.0,98719.0,98720.0] || until2p7(s41)*+ -> . % 76.04/76.29 98908[123:Spt:98906.0,98719.1] || -> node4(s40)*. % 76.04/76.29 98910[123:MRR:798.0,98908.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.29 98913[123:Res:53.1,98910.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.29 98915[124:Spt:98913.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 98917[124:Res:98915.0,61.1] always3(s40) || -> . % 76.04/76.29 98918[124:SSi:98917.0,78245.0,78249.0,78618.0,98718.0,98908.0] || -> . % 76.04/76.29 98919[124:Spt:98918.0,98913.0,98915.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.29 98920[124:Spt:98918.0,98913.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.29 98924[124:Res:98920.0,61.1] always3(s41) || -> . % 76.04/76.29 98925[124:SSi:98924.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.29 98926[122:Spt:98925.0,98717.0,98718.0] || until2p7(s40)*+ -> . % 76.04/76.29 98927[122:Spt:98925.0,98717.1] || -> node4(s39)*. % 76.04/76.29 98929[122:MRR:801.0,98927.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.29 98932[122:Res:53.1,98929.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.29 98937[123:Spt:98932.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 98939[123:Res:98937.0,61.1] always3(s39) || -> . % 76.04/76.29 98940[123:SSi:98939.0,78241.0,78244.0,78617.0,98716.0,98927.0] || -> . % 76.04/76.29 98941[123:Spt:98940.0,98932.0,98937.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.29 98942[123:Spt:98940.0,98932.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.29 98946[123:Res:98942.0,61.1] always3(s40) || -> . % 76.04/76.29 98947[123:SSi:98946.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.29 98948[121:Spt:98947.0,98715.0,98716.0] || until2p7(s39)*+ -> . % 76.04/76.29 98949[121:Spt:98947.0,98715.1] || -> node4(s38)*. % 76.04/76.29 98951[121:MRR:804.0,98949.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.29 98954[121:Res:53.1,98951.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.29 98956[122:Spt:98954.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 98958[122:Res:98956.0,61.1] always3(s38) || -> . % 76.04/76.29 98959[122:SSi:98958.0,78236.0,78240.0,78616.0,98714.0,98949.0] || -> . % 76.04/76.29 98960[122:Spt:98959.0,98954.0,98956.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.29 98961[122:Spt:98959.0,98954.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.29 98965[122:Res:98961.0,61.1] always3(s39) || -> . % 76.04/76.29 98966[122:SSi:98965.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.29 98967[120:Spt:98966.0,98713.0,98714.0] || until2p7(s38)*+ -> . % 76.04/76.29 98968[120:Spt:98966.0,98713.1] || -> node4(s37)*. % 76.04/76.29 98970[120:MRR:807.0,98968.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.29 98973[120:Res:53.1,98970.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.29 98975[121:Spt:98973.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 98977[121:Res:98975.0,61.1] always3(s37) || -> . % 76.04/76.29 98978[121:SSi:98977.0,78232.0,78235.0,78615.0,98712.0,98968.0] || -> . % 76.04/76.29 98979[121:Spt:98978.0,98973.0,98975.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.29 98980[121:Spt:98978.0,98973.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.29 98984[121:Res:98980.0,61.1] always3(s38) || -> . % 76.04/76.29 98985[121:SSi:98984.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.29 98986[119:Spt:98985.0,98711.0,98712.0] || until2p7(s37)*+ -> . % 76.04/76.29 98987[119:Spt:98985.0,98711.1] || -> node4(s36)*. % 76.04/76.29 98989[119:MRR:810.0,98987.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.29 98992[119:Res:53.1,98989.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.29 98994[120:Spt:98992.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 98996[120:Res:98994.0,61.1] always3(s36) || -> . % 76.04/76.29 98997[120:SSi:98996.0,78227.0,78231.0,78614.0,98710.0,98987.0] || -> . % 76.04/76.29 98998[120:Spt:98997.0,98992.0,98994.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.29 98999[120:Spt:98997.0,98992.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.29 99003[120:Res:98999.0,61.1] always3(s37) || -> . % 76.04/76.29 99004[120:SSi:99003.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.29 99005[118:Spt:99004.0,98709.0,98710.0] || until2p7(s36)*+ -> . % 76.04/76.29 99006[118:Spt:99004.0,98709.1] || -> node4(s35)*. % 76.04/76.29 99008[118:MRR:813.0,99006.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.29 99011[118:Res:53.1,99008.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.29 99016[119:Spt:99011.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 99018[119:Res:99016.0,61.1] always3(s35) || -> . % 76.04/76.29 99019[119:SSi:99018.0,78223.0,78226.0,78613.0,98708.0,99006.0] || -> . % 76.04/76.29 99020[119:Spt:99019.0,99011.0,99016.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.29 99021[119:Spt:99019.0,99011.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.29 99025[119:Res:99021.0,61.1] always3(s36) || -> . % 76.04/76.29 99026[119:SSi:99025.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.29 99027[117:Spt:99026.0,98707.0,98708.0] || until2p7(s35)*+ -> . % 76.04/76.29 99028[117:Spt:99026.0,98707.1] || -> node4(s34)*. % 76.04/76.29 99030[117:MRR:816.0,99028.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.29 99033[117:Res:53.1,99030.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.29 99035[118:Spt:99033.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 99037[118:Res:99035.0,61.1] always3(s34) || -> . % 76.04/76.29 99038[118:SSi:99037.0,78218.0,78222.0,78612.0,98706.0,99028.0] || -> . % 76.04/76.29 99039[118:Spt:99038.0,99033.0,99035.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.29 99040[118:Spt:99038.0,99033.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.29 99044[118:Res:99040.0,61.1] always3(s35) || -> . % 76.04/76.29 99045[118:SSi:99044.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.29 99046[116:Spt:99045.0,98705.0,98706.0] || until2p7(s34)*+ -> . % 76.04/76.29 99047[116:Spt:99045.0,98705.1] || -> node4(s33)*. % 76.04/76.29 99049[116:MRR:819.0,99047.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.29 99052[116:Res:53.1,99049.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.29 99054[117:Spt:99052.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 99056[117:Res:99054.0,61.1] always3(s33) || -> . % 76.04/76.29 99057[117:SSi:99056.0,78214.0,78217.0,78611.0,98704.0,99047.0] || -> . % 76.04/76.29 99058[117:Spt:99057.0,99052.0,99054.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.29 99059[117:Spt:99057.0,99052.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.29 99063[117:Res:99059.0,61.1] always3(s34) || -> . % 76.04/76.29 99064[117:SSi:99063.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.29 99065[115:Spt:99064.0,98703.0,98704.0] || until2p7(s33)*+ -> . % 76.04/76.29 99066[115:Spt:99064.0,98703.1] || -> node4(s32)*. % 76.04/76.29 99068[115:MRR:822.0,99066.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.29 99071[115:Res:53.1,99068.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.29 99073[116:Spt:99071.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 99075[116:Res:99073.0,61.1] always3(s32) || -> . % 76.04/76.29 99076[116:SSi:99075.0,78209.0,78213.0,78610.0,98702.0,99066.0] || -> . % 76.04/76.29 99077[116:Spt:99076.0,99071.0,99073.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.29 99078[116:Spt:99076.0,99071.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.29 99082[116:Res:99078.0,61.1] always3(s33) || -> . % 76.04/76.29 99083[116:SSi:99082.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.29 99084[114:Spt:99083.0,98701.0,98702.0] || until2p7(s32)*+ -> . % 76.04/76.29 99085[114:Spt:99083.0,98701.1] || -> node4(s31)*. % 76.04/76.29 99087[114:MRR:825.0,99085.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.29 99090[114:Res:53.1,99087.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.29 99095[115:Spt:99090.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 99097[115:Res:99095.0,61.1] always3(s31) || -> . % 76.04/76.29 99098[115:SSi:99097.0,78205.0,78208.0,78609.0,98700.0,99085.0] || -> . % 76.04/76.29 99099[115:Spt:99098.0,99090.0,99095.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.29 99100[115:Spt:99098.0,99090.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.29 99104[115:Res:99100.0,61.1] always3(s32) || -> . % 76.04/76.29 99105[115:SSi:99104.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.29 99106[113:Spt:99105.0,98699.0,98700.0] || until2p7(s31)*+ -> . % 76.04/76.29 99107[113:Spt:99105.0,98699.1] || -> node4(s30)*. % 76.04/76.29 99109[113:MRR:828.0,99107.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.29 99112[113:Res:53.1,99109.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.29 99114[114:Spt:99112.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 99116[114:Res:99114.0,61.1] always3(s30) || -> . % 76.04/76.29 99117[114:SSi:99116.0,78200.0,78204.0,78608.0,98698.0,99107.0] || -> . % 76.04/76.29 99118[114:Spt:99117.0,99112.0,99114.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.29 99119[114:Spt:99117.0,99112.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.29 99123[114:Res:99119.0,61.1] always3(s31) || -> . % 76.04/76.29 99124[114:SSi:99123.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.29 99125[112:Spt:99124.0,98697.0,98698.0] || until2p7(s30)*+ -> . % 76.04/76.29 99126[112:Spt:99124.0,98697.1] || -> node4(s29)*. % 76.04/76.29 99128[112:MRR:831.0,99126.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.29 99131[112:Res:53.1,99128.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.29 99133[113:Spt:99131.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 99135[113:Res:99133.0,61.1] always3(s29) || -> . % 76.04/76.29 99136[113:SSi:99135.0,78196.0,78199.0,78607.0,98696.0,99126.0] || -> . % 76.04/76.29 99137[113:Spt:99136.0,99131.0,99133.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.29 99138[113:Spt:99136.0,99131.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.29 99142[113:Res:99138.0,61.1] always3(s30) || -> . % 76.04/76.29 99143[113:SSi:99142.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.29 99144[111:Spt:99143.0,98695.0,98696.0] || until2p7(s29)*+ -> . % 76.04/76.29 99145[111:Spt:99143.0,98695.1] || -> node4(s28)*. % 76.04/76.29 99147[111:MRR:834.0,99145.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.29 99150[111:Res:53.1,99147.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.29 99152[112:Spt:99150.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.29 99154[112:Res:99152.0,61.1] always3(s28) || -> . % 76.04/76.29 99155[112:SSi:99154.0,78191.0,78195.0,78606.0,98694.0,99145.0] || -> . % 76.04/76.29 99156[112:Spt:99155.0,99150.0,99152.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.29 99157[112:Spt:99155.0,99150.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.29 99161[112:Res:99157.0,61.1] always3(s29) || -> . % 76.04/76.29 99162[112:SSi:99161.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.29 99163[110:Spt:99162.0,98693.0,98694.0] || until2p7(s28)*+ -> . % 76.04/76.29 99164[110:Spt:99162.0,98693.1] || -> node4(s27)*. % 76.04/76.29 99166[110:MRR:837.0,99164.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.29 99169[110:Res:53.1,99166.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.29 99174[111:Spt:99169.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.29 99176[111:Res:99174.0,61.1] always3(s27) || -> . % 76.04/76.29 99177[111:SSi:99176.0,78187.0,78190.0,78605.0,98692.0,99164.0] || -> . % 76.04/76.30 99178[111:Spt:99177.0,99169.0,99174.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.30 99179[111:Spt:99177.0,99169.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 99183[111:Res:99179.0,61.1] always3(s28) || -> . % 76.04/76.30 99184[111:SSi:99183.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.30 99185[109:Spt:99184.0,98691.0,98692.0] || until2p7(s27)*+ -> . % 76.04/76.30 99186[109:Spt:99184.0,98691.1] || -> node4(s26)*. % 76.04/76.30 99188[109:MRR:840.0,99186.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.30 99191[109:Res:53.1,99188.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.30 99193[110:Spt:99191.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 99195[110:Res:99193.0,61.1] always3(s26) || -> . % 76.04/76.30 99196[110:SSi:99195.0,78182.0,78186.0,78604.0,98690.0,99186.0] || -> . % 76.04/76.30 99197[110:Spt:99196.0,99191.0,99193.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.30 99198[110:Spt:99196.0,99191.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 99202[110:Res:99198.0,61.1] always3(s27) || -> . % 76.04/76.30 99203[110:SSi:99202.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.30 99204[108:Spt:99203.0,98689.0,98690.0] || until2p7(s26)*+ -> . % 76.04/76.30 99205[108:Spt:99203.0,98689.1] || -> node4(s25)*. % 76.04/76.30 99207[108:MRR:843.0,99205.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.30 99210[108:Res:53.1,99207.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.30 99212[109:Spt:99210.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 99214[109:Res:99212.0,61.1] always3(s25) || -> . % 76.04/76.30 99215[109:SSi:99214.0,78178.0,78181.0,78603.0,98688.0,99205.0] || -> . % 76.04/76.30 99216[109:Spt:99215.0,99210.0,99212.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.30 99217[109:Spt:99215.0,99210.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 99221[109:Res:99217.0,61.1] always3(s26) || -> . % 76.04/76.30 99222[109:SSi:99221.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.30 99223[107:Spt:99222.0,98687.0,98688.0] || until2p7(s25)*+ -> . % 76.04/76.30 99224[107:Spt:99222.0,98687.1] || -> node4(s24)*. % 76.04/76.30 99226[107:MRR:846.0,99224.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.30 99229[107:Res:53.1,99226.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.30 99231[108:Spt:99229.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 99233[108:Res:99231.0,61.1] always3(s24) || -> . % 76.04/76.30 99234[108:SSi:99233.0,78173.0,78177.0,78602.0,98686.0,99224.0] || -> . % 76.04/76.30 99235[108:Spt:99234.0,99229.0,99231.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.30 99236[108:Spt:99234.0,99229.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 99240[108:Res:99236.0,61.1] always3(s25) || -> . % 76.04/76.30 99241[108:SSi:99240.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.30 99242[106:Spt:99241.0,98685.0,98686.0] || until2p7(s24)*+ -> . % 76.04/76.30 99243[106:Spt:99241.0,98685.1] || -> node4(s23)*. % 76.04/76.30 99245[106:MRR:849.0,99243.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.30 99248[106:Res:53.1,99245.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.30 99253[107:Spt:99248.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 99255[107:Res:99253.0,61.1] always3(s23) || -> . % 76.04/76.30 99256[107:SSi:99255.0,78169.0,78172.0,78601.0,98684.0,99243.0] || -> . % 76.04/76.30 99257[107:Spt:99256.0,99248.0,99253.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.30 99258[107:Spt:99256.0,99248.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 99262[107:Res:99258.0,61.1] always3(s24) || -> . % 76.04/76.30 99263[107:SSi:99262.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.30 99264[105:Spt:99263.0,98683.0,98684.0] || until2p7(s23)*+ -> . % 76.04/76.30 99265[105:Spt:99263.0,98683.1] || -> node4(s22)*. % 76.04/76.30 99267[105:MRR:852.0,99265.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.30 99270[105:Res:53.1,99267.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.30 99272[106:Spt:99270.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 99274[106:Res:99272.0,61.1] always3(s22) || -> . % 76.04/76.30 99275[106:SSi:99274.0,78164.0,78168.0,78600.0,98682.0,99265.0] || -> . % 76.04/76.30 99276[106:Spt:99275.0,99270.0,99272.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.30 99277[106:Spt:99275.0,99270.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 99281[106:Res:99277.0,61.1] always3(s23) || -> . % 76.04/76.30 99282[106:SSi:99281.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.30 99283[104:Spt:99282.0,98681.0,98682.0] || until2p7(s22)*+ -> . % 76.04/76.30 99284[104:Spt:99282.0,98681.1] || -> node4(s21)*. % 76.04/76.30 99286[104:MRR:855.0,99284.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.30 99289[104:Res:53.1,99286.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.30 99291[105:Spt:99289.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 99293[105:Res:99291.0,61.1] always3(s21) || -> . % 76.04/76.30 99294[105:SSi:99293.0,78160.0,78163.0,78599.0,98680.0,99284.0] || -> . % 76.04/76.30 99295[105:Spt:99294.0,99289.0,99291.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.30 99296[105:Spt:99294.0,99289.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 99300[105:Res:99296.0,61.1] always3(s22) || -> . % 76.04/76.30 99301[105:SSi:99300.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.30 99302[103:Spt:99301.0,98679.0,98680.0] || until2p7(s21)*+ -> . % 76.04/76.30 99303[103:Spt:99301.0,98679.1] || -> node4(s20)*. % 76.04/76.30 99305[103:MRR:858.0,99303.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.30 99308[103:Res:53.1,99305.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.30 99310[104:Spt:99308.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 99312[104:Res:99310.0,61.1] always3(s20) || -> . % 76.04/76.30 99313[104:SSi:99312.0,78155.0,78159.0,78598.0,98678.0,99303.0] || -> . % 76.04/76.30 99314[104:Spt:99313.0,99308.0,99310.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.30 99315[104:Spt:99313.0,99308.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 99319[104:Res:99315.0,61.1] always3(s21) || -> . % 76.04/76.30 99320[104:SSi:99319.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.30 99321[102:Spt:99320.0,98677.0,98678.0] || until2p7(s20)*+ -> . % 76.04/76.30 99322[102:Spt:99320.0,98677.1] || -> node4(s19)*. % 76.04/76.30 99324[102:MRR:861.0,99322.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.30 99327[102:Res:53.1,99324.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.30 99332[103:Spt:99327.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 99334[103:Res:99332.0,61.1] always3(s19) || -> . % 76.04/76.30 99335[103:SSi:99334.0,78151.0,78154.0,78597.0,98676.0,99322.0] || -> . % 76.04/76.30 99336[103:Spt:99335.0,99327.0,99332.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.30 99337[103:Spt:99335.0,99327.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 99341[103:Res:99337.0,61.1] always3(s20) || -> . % 76.04/76.30 99342[103:SSi:99341.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.30 99343[101:Spt:99342.0,98675.0,98676.0] || until2p7(s19)*+ -> . % 76.04/76.30 99344[101:Spt:99342.0,98675.1] || -> node4(s18)*. % 76.04/76.30 99346[101:MRR:864.0,99344.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.30 99349[101:Res:53.1,99346.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.30 99351[102:Spt:99349.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 99353[102:Res:99351.0,61.1] always3(s18) || -> . % 76.04/76.30 99354[102:SSi:99353.0,78146.0,78150.0,78596.0,98674.0,99344.0] || -> . % 76.04/76.30 99355[102:Spt:99354.0,99349.0,99351.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.30 99356[102:Spt:99354.0,99349.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 99360[102:Res:99356.0,61.1] always3(s19) || -> . % 76.04/76.30 99361[102:SSi:99360.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.30 99362[100:Spt:99361.0,98673.0,98674.0] || until2p7(s18)*+ -> . % 76.04/76.30 99363[100:Spt:99361.0,98673.1] || -> node4(s17)*. % 76.04/76.30 99365[100:MRR:867.0,99363.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.30 99368[100:Res:53.1,99365.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.30 99370[101:Spt:99368.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 99372[101:Res:99370.0,61.1] always3(s17) || -> . % 76.04/76.30 99373[101:SSi:99372.0,78142.0,78145.0,78595.0,98672.0,99363.0] || -> . % 76.04/76.30 99374[101:Spt:99373.0,99368.0,99370.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.30 99375[101:Spt:99373.0,99368.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 99379[101:Res:99375.0,61.1] always3(s18) || -> . % 76.04/76.30 99380[101:SSi:99379.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.30 99381[99:Spt:99380.0,98671.0,98672.0] || until2p7(s17)*+ -> . % 76.04/76.30 99382[99:Spt:99380.0,98671.1] || -> node4(s16)*. % 76.04/76.30 99384[99:MRR:870.0,99382.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.30 99387[99:Res:53.1,99384.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.30 99389[100:Spt:99387.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 99391[100:Res:99389.0,61.1] always3(s16) || -> . % 76.04/76.30 99392[100:SSi:99391.0,78137.0,78141.0,78594.0,98670.0,99382.0] || -> . % 76.04/76.30 99393[100:Spt:99392.0,99387.0,99389.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.30 99394[100:Spt:99392.0,99387.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 99398[100:Res:99394.0,61.1] always3(s17) || -> . % 76.04/76.30 99399[100:SSi:99398.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.30 99400[98:Spt:99399.0,98669.0,98670.0] || until2p7(s16)*+ -> . % 76.04/76.30 99401[98:Spt:99399.0,98669.1] || -> node4(s15)*. % 76.04/76.30 99403[98:MRR:873.0,99401.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.30 99406[98:Res:53.1,99403.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.30 99411[99:Spt:99406.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 99413[99:Res:99411.0,61.1] always3(s15) || -> . % 76.04/76.30 99414[99:SSi:99413.0,78133.0,78136.0,78593.0,98668.0,99401.0] || -> . % 76.04/76.30 99415[99:Spt:99414.0,99406.0,99411.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.30 99416[99:Spt:99414.0,99406.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 99420[99:Res:99416.0,61.1] always3(s16) || -> . % 76.04/76.30 99421[99:SSi:99420.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.30 99422[97:Spt:99421.0,98667.0,98668.0] || until2p7(s15)*+ -> . % 76.04/76.30 99423[97:Spt:99421.0,98667.1] || -> node4(s14)*. % 76.04/76.30 99425[97:MRR:876.0,99423.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.30 99428[97:Res:53.1,99425.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.30 99430[98:Spt:99428.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 99432[98:Res:99430.0,61.1] always3(s14) || -> . % 76.04/76.30 99433[98:SSi:99432.0,78128.0,78132.0,78592.0,98666.0,99423.0] || -> . % 76.04/76.30 99434[98:Spt:99433.0,99428.0,99430.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.30 99435[98:Spt:99433.0,99428.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 99439[98:Res:99435.0,61.1] always3(s15) || -> . % 76.04/76.30 99440[98:SSi:99439.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.30 99441[96:Spt:99440.0,98665.0,98666.0] || until2p7(s14)*+ -> . % 76.04/76.30 99442[96:Spt:99440.0,98665.1] || -> node4(s13)*. % 76.04/76.30 99444[96:MRR:879.0,99442.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.30 99447[96:Res:53.1,99444.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.30 99449[97:Spt:99447.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 99451[97:Res:99449.0,61.1] always3(s13) || -> . % 76.04/76.30 99452[97:SSi:99451.0,78124.0,78127.0,78591.0,98664.0,99442.0] || -> . % 76.04/76.30 99453[97:Spt:99452.0,99447.0,99449.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.30 99454[97:Spt:99452.0,99447.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 99458[97:Res:99454.0,61.1] always3(s14) || -> . % 76.04/76.30 99459[97:SSi:99458.0,78128.0,78132.0,78592.0] || -> . % 76.04/76.30 99460[95:Spt:99459.0,98663.0,98664.0] || until2p7(s13)*+ -> . % 76.04/76.30 99461[95:Spt:99459.0,98663.1] || -> node4(s12)*. % 76.04/76.30 99463[95:MRR:882.0,99461.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.30 99466[95:Res:53.1,99463.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.30 99468[96:Spt:99466.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 99470[96:Res:99468.0,61.1] always3(s12) || -> . % 76.04/76.30 99471[96:SSi:99470.0,78119.0,78123.0,78590.0,98662.0,99461.0] || -> . % 76.04/76.30 99472[96:Spt:99471.0,99466.0,99468.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.30 99473[96:Spt:99471.0,99466.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 99477[96:Res:99473.0,61.1] always3(s13) || -> . % 76.04/76.30 99478[96:SSi:99477.0,78124.0,78127.0,78591.0] || -> . % 76.04/76.30 99479[94:Spt:99478.0,98661.0,98662.0] || until2p7(s12)*+ -> . % 76.04/76.30 99480[94:Spt:99478.0,98661.1] || -> node4(s11)*. % 76.04/76.30 99482[94:MRR:885.0,99480.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.30 99485[94:Res:53.1,99482.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.30 99490[95:Spt:99485.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 99492[95:Res:99490.0,61.1] always3(s11) || -> . % 76.04/76.30 99493[95:SSi:99492.0,78115.0,78118.0,78589.0,98660.0,99480.0] || -> . % 76.04/76.30 99494[95:Spt:99493.0,99485.0,99490.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.30 99495[95:Spt:99493.0,99485.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 99499[95:Res:99495.0,61.1] always3(s12) || -> . % 76.04/76.30 99500[95:SSi:99499.0,78119.0,78123.0,78590.0] || -> . % 76.04/76.30 99501[93:Spt:99500.0,98659.0,98660.0] || until2p7(s11)*+ -> . % 76.04/76.30 99502[93:Spt:99500.0,98659.1] || -> node4(s10)*. % 76.04/76.30 99504[93:MRR:888.0,99502.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.30 99507[93:Res:53.1,99504.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.30 99509[93:MRR:99507.0,98649.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 99511[93:Res:99509.0,61.1] always3(s11) || -> . % 76.04/76.30 99512[93:SSi:99511.0,78115.0,78118.0,78589.0] || -> . % 76.04/76.30 99513[91:Spt:99512.0,98501.0,98504.0] || trans(s49,s10)*+ -> . % 76.04/76.30 99514[91:Spt:99512.0,98501.1,98501.2,98501.3,98501.4,98501.5,98501.6,98501.7,98501.8] || -> trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.30 99516[91:MRR:98503.1,99513.0] xuntil6(s49) || -> trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.30 99517[92:Spt:99514.0] || -> trans(s49,s9)*. % 76.04/76.30 99518[92:Res:99517.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s9)*. % 76.04/76.30 99520[92:Res:99517.0,60.0] || -> node2(s49,s9)*. % 76.04/76.30 99521[92:SSi:99518.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s9)*. % 76.04/76.30 99522[92:Res:99520.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 99655[92:SoR:99522.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 99657[92:SoR:99655.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)* xuntil6(s49). % 76.04/76.30 99658[92:SSi:99657.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s9,c_busy)* xuntil6(s49). % 76.04/76.30 99659[93:Spt:99658.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 99661[93:Res:99659.0,61.1] always3(s9) || -> . % 76.04/76.30 99662[93:SSi:99661.0,78106.0,78109.0,78587.0] || -> . % 76.04/76.30 99663[93:Spt:99662.0,99658.1,99659.0] || m_main_v_state(s9,c_busy)*+ -> . % 76.04/76.30 99664[93:Spt:99662.0,99658.0,99658.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 99668[93:MRR:99655.2,99663.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 99669[93:Res:53.1,99664.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 99671[93:MRR:99669.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 99672[93:MRR:99521.0,99671.0] || -> until2p7(s9)*. % 76.04/76.30 99673[93:MRR:205.0,99672.0] || -> until2p7(s10)* node4(s9). % 76.04/76.30 99674[94:Spt:99673.0] || -> until2p7(s10)*. % 76.04/76.30 99675[94:MRR:206.0,99674.0] || -> until2p7(s11)* node4(s10). % 76.04/76.30 99676[95:Spt:99675.0] || -> until2p7(s11)*. % 76.04/76.30 99677[95:MRR:207.0,99676.0] || -> until2p7(s12)* node4(s11). % 76.04/76.30 99678[96:Spt:99677.0] || -> until2p7(s12)*. % 76.04/76.30 99679[96:MRR:208.0,99678.0] || -> until2p7(s13)* node4(s12). % 76.04/76.30 99680[97:Spt:99679.0] || -> until2p7(s13)*. % 76.04/76.30 99681[97:MRR:209.0,99680.0] || -> until2p7(s14)* node4(s13). % 76.04/76.30 99682[98:Spt:99681.0] || -> until2p7(s14)*. % 76.04/76.30 99683[98:MRR:210.0,99682.0] || -> until2p7(s15)* node4(s14). % 76.04/76.30 99684[99:Spt:99683.0] || -> until2p7(s15)*. % 76.04/76.30 99685[99:MRR:211.0,99684.0] || -> until2p7(s16)* node4(s15). % 76.04/76.30 99686[100:Spt:99685.0] || -> until2p7(s16)*. % 76.04/76.30 99687[100:MRR:212.0,99686.0] || -> until2p7(s17)* node4(s16). % 76.04/76.30 99688[101:Spt:99687.0] || -> until2p7(s17)*. % 76.04/76.30 99689[101:MRR:213.0,99688.0] || -> until2p7(s18)* node4(s17). % 76.04/76.30 99690[102:Spt:99689.0] || -> until2p7(s18)*. % 76.04/76.30 99691[102:MRR:214.0,99690.0] || -> until2p7(s19)* node4(s18). % 76.04/76.30 99692[103:Spt:99691.0] || -> until2p7(s19)*. % 76.04/76.30 99693[103:MRR:215.0,99692.0] || -> until2p7(s20)* node4(s19). % 76.04/76.30 99694[104:Spt:99693.0] || -> until2p7(s20)*. % 76.04/76.30 99695[104:MRR:216.0,99694.0] || -> until2p7(s21)* node4(s20). % 76.04/76.30 99696[105:Spt:99695.0] || -> until2p7(s21)*. % 76.04/76.30 99697[105:MRR:217.0,99696.0] || -> until2p7(s22)* node4(s21). % 76.04/76.30 99698[106:Spt:99697.0] || -> until2p7(s22)*. % 76.04/76.30 99699[106:MRR:218.0,99698.0] || -> until2p7(s23)* node4(s22). % 76.04/76.30 99700[107:Spt:99699.0] || -> until2p7(s23)*. % 76.04/76.30 99701[107:MRR:219.0,99700.0] || -> until2p7(s24)* node4(s23). % 76.04/76.30 99702[108:Spt:99701.0] || -> until2p7(s24)*. % 76.04/76.30 99703[108:MRR:220.0,99702.0] || -> until2p7(s25)* node4(s24). % 76.04/76.30 99704[109:Spt:99703.0] || -> until2p7(s25)*. % 76.04/76.30 99705[109:MRR:221.0,99704.0] || -> until2p7(s26)* node4(s25). % 76.04/76.30 99706[110:Spt:99705.0] || -> until2p7(s26)*. % 76.04/76.30 99707[110:MRR:222.0,99706.0] || -> until2p7(s27)* node4(s26). % 76.04/76.30 99708[111:Spt:99707.0] || -> until2p7(s27)*. % 76.04/76.30 99709[111:MRR:223.0,99708.0] || -> until2p7(s28)* node4(s27). % 76.04/76.30 99710[112:Spt:99709.0] || -> until2p7(s28)*. % 76.04/76.30 99711[112:MRR:224.0,99710.0] || -> until2p7(s29)* node4(s28). % 76.04/76.30 99712[113:Spt:99711.0] || -> until2p7(s29)*. % 76.04/76.30 99713[113:MRR:225.0,99712.0] || -> until2p7(s30)* node4(s29). % 76.04/76.30 99714[114:Spt:99713.0] || -> until2p7(s30)*. % 76.04/76.30 99715[114:MRR:226.0,99714.0] || -> until2p7(s31)* node4(s30). % 76.04/76.30 99716[115:Spt:99715.0] || -> until2p7(s31)*. % 76.04/76.30 99717[115:MRR:227.0,99716.0] || -> until2p7(s32)* node4(s31). % 76.04/76.30 99718[116:Spt:99717.0] || -> until2p7(s32)*. % 76.04/76.30 99719[116:MRR:228.0,99718.0] || -> until2p7(s33)* node4(s32). % 76.04/76.30 99720[117:Spt:99719.0] || -> until2p7(s33)*. % 76.04/76.30 99721[117:MRR:229.0,99720.0] || -> until2p7(s34)* node4(s33). % 76.04/76.30 99722[118:Spt:99721.0] || -> until2p7(s34)*. % 76.04/76.30 99723[118:MRR:230.0,99722.0] || -> until2p7(s35)* node4(s34). % 76.04/76.30 99724[119:Spt:99723.0] || -> until2p7(s35)*. % 76.04/76.30 99725[119:MRR:231.0,99724.0] || -> until2p7(s36)* node4(s35). % 76.04/76.30 99726[120:Spt:99725.0] || -> until2p7(s36)*. % 76.04/76.30 99727[120:MRR:232.0,99726.0] || -> until2p7(s37)* node4(s36). % 76.04/76.30 99728[121:Spt:99727.0] || -> until2p7(s37)*. % 76.04/76.30 99729[121:MRR:235.0,99728.0] || -> until2p7(s38)* node4(s37). % 76.04/76.30 99730[122:Spt:99729.0] || -> until2p7(s38)*. % 76.04/76.30 99731[122:MRR:236.0,99730.0] || -> until2p7(s39)* node4(s38). % 76.04/76.30 99732[123:Spt:99731.0] || -> until2p7(s39)*. % 76.04/76.30 99733[123:MRR:237.0,99732.0] || -> until2p7(s40)* node4(s39). % 76.04/76.30 99734[124:Spt:99733.0] || -> until2p7(s40)*. % 76.04/76.30 99735[124:MRR:238.0,99734.0] || -> until2p7(s41)* node4(s40). % 76.04/76.30 99736[125:Spt:99735.0] || -> until2p7(s41)*. % 76.04/76.30 99737[125:MRR:239.0,99736.0] || -> until2p7(s42)* node4(s41). % 76.04/76.30 99738[126:Spt:99737.0] || -> until2p7(s42)*. % 76.04/76.30 99739[126:MRR:240.0,99738.0] || -> until2p7(s43)* node4(s42). % 76.04/76.30 99740[127:Spt:99739.0] || -> until2p7(s43)*. % 76.04/76.30 99741[127:MRR:241.0,99740.0] || -> until2p7(s44)* node4(s43). % 76.04/76.30 99742[128:Spt:99741.0] || -> until2p7(s44)*. % 76.04/76.30 99743[128:MRR:539.0,99742.0] || -> until2p7(s45)* node4(s44). % 76.04/76.30 99744[129:Spt:99743.0] || -> until2p7(s45)*. % 76.04/76.30 99745[129:MRR:544.0,99744.0] || -> until2p7(s46)* node4(s45). % 76.04/76.30 99746[130:Spt:99745.0] || -> until2p7(s46)*. % 76.04/76.30 99747[130:MRR:549.0,99746.0] || -> until2p7(s47)* node4(s46). % 76.04/76.30 99748[131:Spt:99747.0] || -> until2p7(s47)*. % 76.04/76.30 99749[131:MRR:554.0,99748.0] || -> until2p7(s48)* node4(s47). % 76.04/76.30 99750[132:Spt:99749.0] || -> until2p7(s48)*. % 76.04/76.30 99751[132:MRR:559.0,99750.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 99752[133:Spt:99751.0] || -> until2p7(s49)*. % 76.04/76.30 99753[133:MRR:194.0,99752.0] || -> node4(s49)*. % 76.04/76.30 99754[133:MRR:99668.0,99753.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 99755[133:Res:53.1,99754.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 99757[133:MRR:99755.0,78381.0] || -> . % 76.04/76.30 99758[133:Spt:99757.0,99751.0,99752.0] || until2p7(s49)*+ -> . % 76.04/76.30 99759[133:Spt:99757.0,99751.1] || -> node4(s48)*. % 76.04/76.30 99760[133:MRR:78384.0,99759.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 99763[133:Res:53.1,99760.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 99766[133:Res:99763.0,61.1] always3(s48) || -> . % 76.04/76.30 99767[133:SSi:99766.0,78281.0,78387.0,78626.0,99750.0,99759.0] || -> . % 76.04/76.30 99768[132:Spt:99767.0,99749.0,99750.0] || until2p7(s48)*+ -> . % 76.04/76.30 99769[132:Spt:99767.0,99749.1] || -> node4(s47)*. % 76.04/76.30 99771[132:MRR:777.0,99769.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.30 99786[132:Res:53.1,99771.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.30 99788[133:Spt:99786.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 99790[133:Res:99788.0,61.1] always3(s47) || -> . % 76.04/76.30 99791[133:SSi:99790.0,78277.0,78280.0,78625.0,99748.0,99769.0] || -> . % 76.04/76.30 99792[133:Spt:99791.0,99786.0,99788.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.30 99793[133:Spt:99791.0,99786.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 99797[133:Res:99793.0,61.1] always3(s48) || -> . % 76.04/76.30 99798[133:SSi:99797.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.30 99799[131:Spt:99798.0,99747.0,99748.0] || until2p7(s47)*+ -> . % 76.04/76.30 99800[131:Spt:99798.0,99747.1] || -> node4(s46)*. % 76.04/76.30 99802[131:MRR:780.0,99800.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.30 99812[131:Res:53.1,99802.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.30 99814[132:Spt:99812.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 99816[132:Res:99814.0,61.1] always3(s46) || -> . % 76.04/76.30 99817[132:SSi:99816.0,78272.0,78276.0,78624.0,99746.0,99800.0] || -> . % 76.04/76.30 99818[132:Spt:99817.0,99812.0,99814.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.30 99819[132:Spt:99817.0,99812.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 99823[132:Res:99819.0,61.1] always3(s47) || -> . % 76.04/76.30 99824[132:SSi:99823.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.30 99825[130:Spt:99824.0,99745.0,99746.0] || until2p7(s46)*+ -> . % 76.04/76.30 99826[130:Spt:99824.0,99745.1] || -> node4(s45)*. % 76.04/76.30 99828[130:MRR:783.0,99826.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.30 99831[130:Res:53.1,99828.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.30 99833[131:Spt:99831.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 99835[131:Res:99833.0,61.1] always3(s45) || -> . % 76.04/76.30 99836[131:SSi:99835.0,78268.0,78271.0,78623.0,99744.0,99826.0] || -> . % 76.04/76.30 99837[131:Spt:99836.0,99831.0,99833.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.30 99838[131:Spt:99836.0,99831.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 99842[131:Res:99838.0,61.1] always3(s46) || -> . % 76.04/76.30 99843[131:SSi:99842.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.30 99844[129:Spt:99843.0,99743.0,99744.0] || until2p7(s45)*+ -> . % 76.04/76.30 99845[129:Spt:99843.0,99743.1] || -> node4(s44)*. % 76.04/76.30 99847[129:MRR:786.0,99845.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.30 99850[129:Res:53.1,99847.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.30 99852[130:Spt:99850.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 99854[130:Res:99852.0,61.1] always3(s44) || -> . % 76.04/76.30 99855[130:SSi:99854.0,78263.0,78267.0,78622.0,99742.0,99845.0] || -> . % 76.04/76.30 99856[130:Spt:99855.0,99850.0,99852.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.30 99857[130:Spt:99855.0,99850.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 99861[130:Res:99857.0,61.1] always3(s45) || -> . % 76.04/76.30 99862[130:SSi:99861.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.30 99863[128:Spt:99862.0,99741.0,99742.0] || until2p7(s44)*+ -> . % 76.04/76.30 99864[128:Spt:99862.0,99741.1] || -> node4(s43)*. % 76.04/76.30 99866[128:MRR:789.0,99864.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.30 99869[128:Res:53.1,99866.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.30 99874[129:Spt:99869.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 99876[129:Res:99874.0,61.1] always3(s43) || -> . % 76.04/76.30 99877[129:SSi:99876.0,78259.0,78262.0,78621.0,99740.0,99864.0] || -> . % 76.04/76.30 99878[129:Spt:99877.0,99869.0,99874.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.30 99879[129:Spt:99877.0,99869.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 99883[129:Res:99879.0,61.1] always3(s44) || -> . % 76.04/76.30 99884[129:SSi:99883.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.30 99885[127:Spt:99884.0,99739.0,99740.0] || until2p7(s43)*+ -> . % 76.04/76.30 99886[127:Spt:99884.0,99739.1] || -> node4(s42)*. % 76.04/76.30 99888[127:MRR:792.0,99886.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.30 99891[127:Res:53.1,99888.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.30 99893[128:Spt:99891.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 99895[128:Res:99893.0,61.1] always3(s42) || -> . % 76.04/76.30 99896[128:SSi:99895.0,78254.0,78258.0,78620.0,99738.0,99886.0] || -> . % 76.04/76.30 99897[128:Spt:99896.0,99891.0,99893.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.30 99898[128:Spt:99896.0,99891.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 99902[128:Res:99898.0,61.1] always3(s43) || -> . % 76.04/76.30 99903[128:SSi:99902.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.30 99904[126:Spt:99903.0,99737.0,99738.0] || until2p7(s42)*+ -> . % 76.04/76.30 99905[126:Spt:99903.0,99737.1] || -> node4(s41)*. % 76.04/76.30 99907[126:MRR:795.0,99905.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.30 99910[126:Res:53.1,99907.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.30 99912[127:Spt:99910.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 99914[127:Res:99912.0,61.1] always3(s41) || -> . % 76.04/76.30 99915[127:SSi:99914.0,78250.0,78253.0,78619.0,99736.0,99905.0] || -> . % 76.04/76.30 99916[127:Spt:99915.0,99910.0,99912.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.30 99917[127:Spt:99915.0,99910.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 99921[127:Res:99917.0,61.1] always3(s42) || -> . % 76.04/76.30 99922[127:SSi:99921.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.30 99923[125:Spt:99922.0,99735.0,99736.0] || until2p7(s41)*+ -> . % 76.04/76.30 99924[125:Spt:99922.0,99735.1] || -> node4(s40)*. % 76.04/76.30 99926[125:MRR:798.0,99924.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.30 99929[125:Res:53.1,99926.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.30 99931[126:Spt:99929.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 99933[126:Res:99931.0,61.1] always3(s40) || -> . % 76.04/76.30 99934[126:SSi:99933.0,78245.0,78249.0,78618.0,99734.0,99924.0] || -> . % 76.04/76.30 99935[126:Spt:99934.0,99929.0,99931.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.30 99936[126:Spt:99934.0,99929.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 99940[126:Res:99936.0,61.1] always3(s41) || -> . % 76.04/76.30 99941[126:SSi:99940.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.30 99942[124:Spt:99941.0,99733.0,99734.0] || until2p7(s40)*+ -> . % 76.04/76.30 99943[124:Spt:99941.0,99733.1] || -> node4(s39)*. % 76.04/76.30 99945[124:MRR:801.0,99943.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.30 99948[124:Res:53.1,99945.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.30 99953[125:Spt:99948.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 99955[125:Res:99953.0,61.1] always3(s39) || -> . % 76.04/76.30 99956[125:SSi:99955.0,78241.0,78244.0,78617.0,99732.0,99943.0] || -> . % 76.04/76.30 99957[125:Spt:99956.0,99948.0,99953.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.30 99958[125:Spt:99956.0,99948.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 99962[125:Res:99958.0,61.1] always3(s40) || -> . % 76.04/76.30 99963[125:SSi:99962.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.30 99964[123:Spt:99963.0,99731.0,99732.0] || until2p7(s39)*+ -> . % 76.04/76.30 99965[123:Spt:99963.0,99731.1] || -> node4(s38)*. % 76.04/76.30 99967[123:MRR:804.0,99965.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.30 99970[123:Res:53.1,99967.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.30 99972[124:Spt:99970.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 99974[124:Res:99972.0,61.1] always3(s38) || -> . % 76.04/76.30 99975[124:SSi:99974.0,78236.0,78240.0,78616.0,99730.0,99965.0] || -> . % 76.04/76.30 99976[124:Spt:99975.0,99970.0,99972.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.30 99977[124:Spt:99975.0,99970.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 99981[124:Res:99977.0,61.1] always3(s39) || -> . % 76.04/76.30 99982[124:SSi:99981.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.30 99983[122:Spt:99982.0,99729.0,99730.0] || until2p7(s38)*+ -> . % 76.04/76.30 99984[122:Spt:99982.0,99729.1] || -> node4(s37)*. % 76.04/76.30 99986[122:MRR:807.0,99984.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.30 99989[122:Res:53.1,99986.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.30 99991[123:Spt:99989.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 99993[123:Res:99991.0,61.1] always3(s37) || -> . % 76.04/76.30 99994[123:SSi:99993.0,78232.0,78235.0,78615.0,99728.0,99984.0] || -> . % 76.04/76.30 99995[123:Spt:99994.0,99989.0,99991.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.30 99996[123:Spt:99994.0,99989.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 100000[123:Res:99996.0,61.1] always3(s38) || -> . % 76.04/76.30 100001[123:SSi:100000.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.30 100002[121:Spt:100001.0,99727.0,99728.0] || until2p7(s37)*+ -> . % 76.04/76.30 100003[121:Spt:100001.0,99727.1] || -> node4(s36)*. % 76.04/76.30 100005[121:MRR:810.0,100003.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.30 100008[121:Res:53.1,100005.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.30 100010[122:Spt:100008.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 100012[122:Res:100010.0,61.1] always3(s36) || -> . % 76.04/76.30 100013[122:SSi:100012.0,78227.0,78231.0,78614.0,99726.0,100003.0] || -> . % 76.04/76.30 100014[122:Spt:100013.0,100008.0,100010.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.30 100015[122:Spt:100013.0,100008.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 100019[122:Res:100015.0,61.1] always3(s37) || -> . % 76.04/76.30 100020[122:SSi:100019.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.30 100021[120:Spt:100020.0,99725.0,99726.0] || until2p7(s36)*+ -> . % 76.04/76.30 100022[120:Spt:100020.0,99725.1] || -> node4(s35)*. % 76.04/76.30 100024[120:MRR:813.0,100022.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.30 100027[120:Res:53.1,100024.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.30 100032[121:Spt:100027.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 100034[121:Res:100032.0,61.1] always3(s35) || -> . % 76.04/76.30 100035[121:SSi:100034.0,78223.0,78226.0,78613.0,99724.0,100022.0] || -> . % 76.04/76.30 100036[121:Spt:100035.0,100027.0,100032.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.30 100037[121:Spt:100035.0,100027.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 100041[121:Res:100037.0,61.1] always3(s36) || -> . % 76.04/76.30 100042[121:SSi:100041.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.30 100043[119:Spt:100042.0,99723.0,99724.0] || until2p7(s35)*+ -> . % 76.04/76.30 100044[119:Spt:100042.0,99723.1] || -> node4(s34)*. % 76.04/76.30 100046[119:MRR:816.0,100044.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.30 100049[119:Res:53.1,100046.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.30 100051[120:Spt:100049.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 100053[120:Res:100051.0,61.1] always3(s34) || -> . % 76.04/76.30 100054[120:SSi:100053.0,78218.0,78222.0,78612.0,99722.0,100044.0] || -> . % 76.04/76.30 100055[120:Spt:100054.0,100049.0,100051.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.30 100056[120:Spt:100054.0,100049.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 100060[120:Res:100056.0,61.1] always3(s35) || -> . % 76.04/76.30 100061[120:SSi:100060.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.30 100062[118:Spt:100061.0,99721.0,99722.0] || until2p7(s34)*+ -> . % 76.04/76.30 100063[118:Spt:100061.0,99721.1] || -> node4(s33)*. % 76.04/76.30 100065[118:MRR:819.0,100063.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.30 100068[118:Res:53.1,100065.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.30 100070[119:Spt:100068.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 100072[119:Res:100070.0,61.1] always3(s33) || -> . % 76.04/76.30 100073[119:SSi:100072.0,78214.0,78217.0,78611.0,99720.0,100063.0] || -> . % 76.04/76.30 100074[119:Spt:100073.0,100068.0,100070.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.30 100075[119:Spt:100073.0,100068.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 100079[119:Res:100075.0,61.1] always3(s34) || -> . % 76.04/76.30 100080[119:SSi:100079.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.30 100081[117:Spt:100080.0,99719.0,99720.0] || until2p7(s33)*+ -> . % 76.04/76.30 100082[117:Spt:100080.0,99719.1] || -> node4(s32)*. % 76.04/76.30 100084[117:MRR:822.0,100082.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.30 100087[117:Res:53.1,100084.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.30 100089[118:Spt:100087.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 100091[118:Res:100089.0,61.1] always3(s32) || -> . % 76.04/76.30 100092[118:SSi:100091.0,78209.0,78213.0,78610.0,99718.0,100082.0] || -> . % 76.04/76.30 100093[118:Spt:100092.0,100087.0,100089.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.30 100094[118:Spt:100092.0,100087.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 100098[118:Res:100094.0,61.1] always3(s33) || -> . % 76.04/76.30 100099[118:SSi:100098.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.30 100100[116:Spt:100099.0,99717.0,99718.0] || until2p7(s32)*+ -> . % 76.04/76.30 100101[116:Spt:100099.0,99717.1] || -> node4(s31)*. % 76.04/76.30 100103[116:MRR:825.0,100101.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.30 100106[116:Res:53.1,100103.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.30 100111[117:Spt:100106.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 100113[117:Res:100111.0,61.1] always3(s31) || -> . % 76.04/76.30 100114[117:SSi:100113.0,78205.0,78208.0,78609.0,99716.0,100101.0] || -> . % 76.04/76.30 100115[117:Spt:100114.0,100106.0,100111.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.30 100116[117:Spt:100114.0,100106.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 100120[117:Res:100116.0,61.1] always3(s32) || -> . % 76.04/76.30 100121[117:SSi:100120.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.30 100122[115:Spt:100121.0,99715.0,99716.0] || until2p7(s31)*+ -> . % 76.04/76.30 100123[115:Spt:100121.0,99715.1] || -> node4(s30)*. % 76.04/76.30 100125[115:MRR:828.0,100123.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.30 100128[115:Res:53.1,100125.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.30 100130[116:Spt:100128.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 100132[116:Res:100130.0,61.1] always3(s30) || -> . % 76.04/76.30 100133[116:SSi:100132.0,78200.0,78204.0,78608.0,99714.0,100123.0] || -> . % 76.04/76.30 100134[116:Spt:100133.0,100128.0,100130.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.30 100135[116:Spt:100133.0,100128.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 100139[116:Res:100135.0,61.1] always3(s31) || -> . % 76.04/76.30 100140[116:SSi:100139.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.30 100141[114:Spt:100140.0,99713.0,99714.0] || until2p7(s30)*+ -> . % 76.04/76.30 100142[114:Spt:100140.0,99713.1] || -> node4(s29)*. % 76.04/76.30 100144[114:MRR:831.0,100142.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.30 100147[114:Res:53.1,100144.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.30 100149[115:Spt:100147.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 100151[115:Res:100149.0,61.1] always3(s29) || -> . % 76.04/76.30 100152[115:SSi:100151.0,78196.0,78199.0,78607.0,99712.0,100142.0] || -> . % 76.04/76.30 100153[115:Spt:100152.0,100147.0,100149.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.30 100154[115:Spt:100152.0,100147.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 100158[115:Res:100154.0,61.1] always3(s30) || -> . % 76.04/76.30 100159[115:SSi:100158.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.30 100160[113:Spt:100159.0,99711.0,99712.0] || until2p7(s29)*+ -> . % 76.04/76.30 100161[113:Spt:100159.0,99711.1] || -> node4(s28)*. % 76.04/76.30 100163[113:MRR:834.0,100161.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.30 100166[113:Res:53.1,100163.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.30 100168[114:Spt:100166.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 100170[114:Res:100168.0,61.1] always3(s28) || -> . % 76.04/76.30 100171[114:SSi:100170.0,78191.0,78195.0,78606.0,99710.0,100161.0] || -> . % 76.04/76.30 100172[114:Spt:100171.0,100166.0,100168.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.30 100173[114:Spt:100171.0,100166.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 100177[114:Res:100173.0,61.1] always3(s29) || -> . % 76.04/76.30 100178[114:SSi:100177.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.30 100179[112:Spt:100178.0,99709.0,99710.0] || until2p7(s28)*+ -> . % 76.04/76.30 100180[112:Spt:100178.0,99709.1] || -> node4(s27)*. % 76.04/76.30 100182[112:MRR:837.0,100180.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.30 100185[112:Res:53.1,100182.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.30 100190[113:Spt:100185.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 100192[113:Res:100190.0,61.1] always3(s27) || -> . % 76.04/76.30 100193[113:SSi:100192.0,78187.0,78190.0,78605.0,99708.0,100180.0] || -> . % 76.04/76.30 100194[113:Spt:100193.0,100185.0,100190.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.30 100195[113:Spt:100193.0,100185.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 100199[113:Res:100195.0,61.1] always3(s28) || -> . % 76.04/76.30 100200[113:SSi:100199.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.30 100201[111:Spt:100200.0,99707.0,99708.0] || until2p7(s27)*+ -> . % 76.04/76.30 100202[111:Spt:100200.0,99707.1] || -> node4(s26)*. % 76.04/76.30 100204[111:MRR:840.0,100202.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.30 100207[111:Res:53.1,100204.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.30 100209[112:Spt:100207.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 100211[112:Res:100209.0,61.1] always3(s26) || -> . % 76.04/76.30 100212[112:SSi:100211.0,78182.0,78186.0,78604.0,99706.0,100202.0] || -> . % 76.04/76.30 100213[112:Spt:100212.0,100207.0,100209.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.30 100214[112:Spt:100212.0,100207.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 100218[112:Res:100214.0,61.1] always3(s27) || -> . % 76.04/76.30 100219[112:SSi:100218.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.30 100220[110:Spt:100219.0,99705.0,99706.0] || until2p7(s26)*+ -> . % 76.04/76.30 100221[110:Spt:100219.0,99705.1] || -> node4(s25)*. % 76.04/76.30 100223[110:MRR:843.0,100221.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.30 100226[110:Res:53.1,100223.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.30 100228[111:Spt:100226.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 100230[111:Res:100228.0,61.1] always3(s25) || -> . % 76.04/76.30 100231[111:SSi:100230.0,78178.0,78181.0,78603.0,99704.0,100221.0] || -> . % 76.04/76.30 100232[111:Spt:100231.0,100226.0,100228.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.30 100233[111:Spt:100231.0,100226.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 100237[111:Res:100233.0,61.1] always3(s26) || -> . % 76.04/76.30 100238[111:SSi:100237.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.30 100239[109:Spt:100238.0,99703.0,99704.0] || until2p7(s25)*+ -> . % 76.04/76.30 100240[109:Spt:100238.0,99703.1] || -> node4(s24)*. % 76.04/76.30 100242[109:MRR:846.0,100240.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.30 100245[109:Res:53.1,100242.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.30 100247[110:Spt:100245.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 100249[110:Res:100247.0,61.1] always3(s24) || -> . % 76.04/76.30 100250[110:SSi:100249.0,78173.0,78177.0,78602.0,99702.0,100240.0] || -> . % 76.04/76.30 100251[110:Spt:100250.0,100245.0,100247.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.30 100252[110:Spt:100250.0,100245.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 100256[110:Res:100252.0,61.1] always3(s25) || -> . % 76.04/76.30 100257[110:SSi:100256.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.30 100258[108:Spt:100257.0,99701.0,99702.0] || until2p7(s24)*+ -> . % 76.04/76.30 100259[108:Spt:100257.0,99701.1] || -> node4(s23)*. % 76.04/76.30 100261[108:MRR:849.0,100259.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.30 100264[108:Res:53.1,100261.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.30 100269[109:Spt:100264.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 100271[109:Res:100269.0,61.1] always3(s23) || -> . % 76.04/76.30 100272[109:SSi:100271.0,78169.0,78172.0,78601.0,99700.0,100259.0] || -> . % 76.04/76.30 100273[109:Spt:100272.0,100264.0,100269.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.30 100274[109:Spt:100272.0,100264.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 100278[109:Res:100274.0,61.1] always3(s24) || -> . % 76.04/76.30 100279[109:SSi:100278.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.30 100280[107:Spt:100279.0,99699.0,99700.0] || until2p7(s23)*+ -> . % 76.04/76.30 100281[107:Spt:100279.0,99699.1] || -> node4(s22)*. % 76.04/76.30 100283[107:MRR:852.0,100281.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.30 100286[107:Res:53.1,100283.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.30 100288[108:Spt:100286.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 100290[108:Res:100288.0,61.1] always3(s22) || -> . % 76.04/76.30 100291[108:SSi:100290.0,78164.0,78168.0,78600.0,99698.0,100281.0] || -> . % 76.04/76.30 100292[108:Spt:100291.0,100286.0,100288.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.30 100293[108:Spt:100291.0,100286.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 100297[108:Res:100293.0,61.1] always3(s23) || -> . % 76.04/76.30 100298[108:SSi:100297.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.30 100299[106:Spt:100298.0,99697.0,99698.0] || until2p7(s22)*+ -> . % 76.04/76.30 100300[106:Spt:100298.0,99697.1] || -> node4(s21)*. % 76.04/76.30 100302[106:MRR:855.0,100300.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.30 100305[106:Res:53.1,100302.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.30 100307[107:Spt:100305.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 100309[107:Res:100307.0,61.1] always3(s21) || -> . % 76.04/76.30 100310[107:SSi:100309.0,78160.0,78163.0,78599.0,99696.0,100300.0] || -> . % 76.04/76.30 100311[107:Spt:100310.0,100305.0,100307.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.30 100312[107:Spt:100310.0,100305.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 100316[107:Res:100312.0,61.1] always3(s22) || -> . % 76.04/76.30 100317[107:SSi:100316.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.30 100318[105:Spt:100317.0,99695.0,99696.0] || until2p7(s21)*+ -> . % 76.04/76.30 100319[105:Spt:100317.0,99695.1] || -> node4(s20)*. % 76.04/76.30 100321[105:MRR:858.0,100319.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.30 100324[105:Res:53.1,100321.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.30 100326[106:Spt:100324.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 100328[106:Res:100326.0,61.1] always3(s20) || -> . % 76.04/76.30 100329[106:SSi:100328.0,78155.0,78159.0,78598.0,99694.0,100319.0] || -> . % 76.04/76.30 100330[106:Spt:100329.0,100324.0,100326.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.30 100331[106:Spt:100329.0,100324.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 100335[106:Res:100331.0,61.1] always3(s21) || -> . % 76.04/76.30 100336[106:SSi:100335.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.30 100337[104:Spt:100336.0,99693.0,99694.0] || until2p7(s20)*+ -> . % 76.04/76.30 100338[104:Spt:100336.0,99693.1] || -> node4(s19)*. % 76.04/76.30 100340[104:MRR:861.0,100338.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.30 100343[104:Res:53.1,100340.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.30 100348[105:Spt:100343.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 100350[105:Res:100348.0,61.1] always3(s19) || -> . % 76.04/76.30 100351[105:SSi:100350.0,78151.0,78154.0,78597.0,99692.0,100338.0] || -> . % 76.04/76.30 100352[105:Spt:100351.0,100343.0,100348.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.30 100353[105:Spt:100351.0,100343.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 100357[105:Res:100353.0,61.1] always3(s20) || -> . % 76.04/76.30 100358[105:SSi:100357.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.30 100359[103:Spt:100358.0,99691.0,99692.0] || until2p7(s19)*+ -> . % 76.04/76.30 100360[103:Spt:100358.0,99691.1] || -> node4(s18)*. % 76.04/76.30 100362[103:MRR:864.0,100360.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.30 100365[103:Res:53.1,100362.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.30 100367[104:Spt:100365.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 100369[104:Res:100367.0,61.1] always3(s18) || -> . % 76.04/76.30 100370[104:SSi:100369.0,78146.0,78150.0,78596.0,99690.0,100360.0] || -> . % 76.04/76.30 100371[104:Spt:100370.0,100365.0,100367.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.30 100372[104:Spt:100370.0,100365.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 100376[104:Res:100372.0,61.1] always3(s19) || -> . % 76.04/76.30 100377[104:SSi:100376.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.30 100378[102:Spt:100377.0,99689.0,99690.0] || until2p7(s18)*+ -> . % 76.04/76.30 100379[102:Spt:100377.0,99689.1] || -> node4(s17)*. % 76.04/76.30 100381[102:MRR:867.0,100379.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.30 100384[102:Res:53.1,100381.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.30 100386[103:Spt:100384.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 100388[103:Res:100386.0,61.1] always3(s17) || -> . % 76.04/76.30 100389[103:SSi:100388.0,78142.0,78145.0,78595.0,99688.0,100379.0] || -> . % 76.04/76.30 100390[103:Spt:100389.0,100384.0,100386.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.30 100391[103:Spt:100389.0,100384.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 100395[103:Res:100391.0,61.1] always3(s18) || -> . % 76.04/76.30 100396[103:SSi:100395.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.30 100397[101:Spt:100396.0,99687.0,99688.0] || until2p7(s17)*+ -> . % 76.04/76.30 100398[101:Spt:100396.0,99687.1] || -> node4(s16)*. % 76.04/76.30 100400[101:MRR:870.0,100398.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.30 100403[101:Res:53.1,100400.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.30 100405[102:Spt:100403.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 100407[102:Res:100405.0,61.1] always3(s16) || -> . % 76.04/76.30 100408[102:SSi:100407.0,78137.0,78141.0,78594.0,99686.0,100398.0] || -> . % 76.04/76.30 100409[102:Spt:100408.0,100403.0,100405.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.30 100410[102:Spt:100408.0,100403.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 100414[102:Res:100410.0,61.1] always3(s17) || -> . % 76.04/76.30 100415[102:SSi:100414.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.30 100416[100:Spt:100415.0,99685.0,99686.0] || until2p7(s16)*+ -> . % 76.04/76.30 100417[100:Spt:100415.0,99685.1] || -> node4(s15)*. % 76.04/76.30 100419[100:MRR:873.0,100417.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.30 100422[100:Res:53.1,100419.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.30 100427[101:Spt:100422.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 100429[101:Res:100427.0,61.1] always3(s15) || -> . % 76.04/76.30 100430[101:SSi:100429.0,78133.0,78136.0,78593.0,99684.0,100417.0] || -> . % 76.04/76.30 100431[101:Spt:100430.0,100422.0,100427.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.30 100432[101:Spt:100430.0,100422.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 100436[101:Res:100432.0,61.1] always3(s16) || -> . % 76.04/76.30 100437[101:SSi:100436.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.30 100438[99:Spt:100437.0,99683.0,99684.0] || until2p7(s15)*+ -> . % 76.04/76.30 100439[99:Spt:100437.0,99683.1] || -> node4(s14)*. % 76.04/76.30 100441[99:MRR:876.0,100439.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.30 100444[99:Res:53.1,100441.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.30 100446[100:Spt:100444.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 100448[100:Res:100446.0,61.1] always3(s14) || -> . % 76.04/76.30 100449[100:SSi:100448.0,78128.0,78132.0,78592.0,99682.0,100439.0] || -> . % 76.04/76.30 100450[100:Spt:100449.0,100444.0,100446.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.30 100451[100:Spt:100449.0,100444.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 100455[100:Res:100451.0,61.1] always3(s15) || -> . % 76.04/76.30 100456[100:SSi:100455.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.30 100457[98:Spt:100456.0,99681.0,99682.0] || until2p7(s14)*+ -> . % 76.04/76.30 100458[98:Spt:100456.0,99681.1] || -> node4(s13)*. % 76.04/76.30 100460[98:MRR:879.0,100458.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.30 100463[98:Res:53.1,100460.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.30 100465[99:Spt:100463.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 100467[99:Res:100465.0,61.1] always3(s13) || -> . % 76.04/76.30 100468[99:SSi:100467.0,78124.0,78127.0,78591.0,99680.0,100458.0] || -> . % 76.04/76.30 100469[99:Spt:100468.0,100463.0,100465.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.30 100470[99:Spt:100468.0,100463.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 100474[99:Res:100470.0,61.1] always3(s14) || -> . % 76.04/76.30 100475[99:SSi:100474.0,78128.0,78132.0,78592.0] || -> . % 76.04/76.30 100476[97:Spt:100475.0,99679.0,99680.0] || until2p7(s13)*+ -> . % 76.04/76.30 100477[97:Spt:100475.0,99679.1] || -> node4(s12)*. % 76.04/76.30 100479[97:MRR:882.0,100477.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.30 100482[97:Res:53.1,100479.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.30 100484[98:Spt:100482.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 100486[98:Res:100484.0,61.1] always3(s12) || -> . % 76.04/76.30 100487[98:SSi:100486.0,78119.0,78123.0,78590.0,99678.0,100477.0] || -> . % 76.04/76.30 100488[98:Spt:100487.0,100482.0,100484.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.30 100489[98:Spt:100487.0,100482.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 100493[98:Res:100489.0,61.1] always3(s13) || -> . % 76.04/76.30 100494[98:SSi:100493.0,78124.0,78127.0,78591.0] || -> . % 76.04/76.30 100495[96:Spt:100494.0,99677.0,99678.0] || until2p7(s12)*+ -> . % 76.04/76.30 100496[96:Spt:100494.0,99677.1] || -> node4(s11)*. % 76.04/76.30 100498[96:MRR:885.0,100496.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.30 100501[96:Res:53.1,100498.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.30 100506[97:Spt:100501.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 100508[97:Res:100506.0,61.1] always3(s11) || -> . % 76.04/76.30 100509[97:SSi:100508.0,78115.0,78118.0,78589.0,99676.0,100496.0] || -> . % 76.04/76.30 100510[97:Spt:100509.0,100501.0,100506.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.30 100511[97:Spt:100509.0,100501.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 100515[97:Res:100511.0,61.1] always3(s12) || -> . % 76.04/76.30 100516[97:SSi:100515.0,78119.0,78123.0,78590.0] || -> . % 76.04/76.30 100517[95:Spt:100516.0,99675.0,99676.0] || until2p7(s11)*+ -> . % 76.04/76.30 100518[95:Spt:100516.0,99675.1] || -> node4(s10)*. % 76.04/76.30 100520[95:MRR:888.0,100518.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.30 100523[95:Res:53.1,100520.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.30 100525[96:Spt:100523.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 100527[96:Res:100525.0,61.1] always3(s10) || -> . % 76.04/76.30 100528[96:SSi:100527.0,78110.0,78114.0,78588.0,99674.0,100518.0] || -> . % 76.04/76.30 100529[96:Spt:100528.0,100523.0,100525.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.30 100530[96:Spt:100528.0,100523.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 100534[96:Res:100530.0,61.1] always3(s11) || -> . % 76.04/76.30 100535[96:SSi:100534.0,78115.0,78118.0,78589.0] || -> . % 76.04/76.30 100536[94:Spt:100535.0,99673.0,99674.0] || until2p7(s10)*+ -> . % 76.04/76.30 100537[94:Spt:100535.0,99673.1] || -> node4(s9)*. % 76.04/76.30 100539[94:MRR:891.0,100537.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.30 100542[94:Res:53.1,100539.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.30 100544[94:MRR:100542.0,99663.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 100546[94:Res:100544.0,61.1] always3(s10) || -> . % 76.04/76.30 100547[94:SSi:100546.0,78110.0,78114.0,78588.0] || -> . % 76.04/76.30 100548[92:Spt:100547.0,99514.0,99517.0] || trans(s49,s9)*+ -> . % 76.04/76.30 100549[92:Spt:100547.0,99514.1,99514.2,99514.3,99514.4,99514.5,99514.6,99514.7] || -> trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.30 100551[92:MRR:99516.1,100548.0] xuntil6(s49) || -> trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.30 100552[93:Spt:100549.0] || -> trans(s49,s8)*. % 76.04/76.30 100553[93:Res:100552.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s8)*. % 76.04/76.30 100555[93:Res:100552.0,60.0] || -> node2(s49,s8)*. % 76.04/76.30 100556[93:SSi:100553.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s8)*. % 76.04/76.30 100557[93:Res:100555.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 100694[93:SoR:100557.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 100696[93:SoR:100694.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)* xuntil6(s49). % 76.04/76.30 100697[93:SSi:100696.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s8,c_busy)* xuntil6(s49). % 76.04/76.30 100698[94:Spt:100697.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 100700[94:Res:100698.0,61.1] always3(s8) || -> . % 76.04/76.30 100701[94:SSi:100700.0,78101.0,78105.0,78586.0] || -> . % 76.04/76.30 100702[94:Spt:100701.0,100697.1,100698.0] || m_main_v_state(s8,c_busy)*+ -> . % 76.04/76.30 100703[94:Spt:100701.0,100697.0,100697.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 100707[94:MRR:100694.2,100702.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 100708[94:Res:53.1,100703.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 100710[94:MRR:100708.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 100711[94:MRR:100556.0,100710.0] || -> until2p7(s8)*. % 76.04/76.30 100712[94:MRR:204.0,100711.0] || -> until2p7(s9)* node4(s8). % 76.04/76.30 100713[95:Spt:100712.0] || -> until2p7(s9)*. % 76.04/76.30 100714[95:MRR:205.0,100713.0] || -> until2p7(s10)* node4(s9). % 76.04/76.30 100715[96:Spt:100714.0] || -> until2p7(s10)*. % 76.04/76.30 100716[96:MRR:206.0,100715.0] || -> until2p7(s11)* node4(s10). % 76.04/76.30 100717[97:Spt:100716.0] || -> until2p7(s11)*. % 76.04/76.30 100718[97:MRR:207.0,100717.0] || -> until2p7(s12)* node4(s11). % 76.04/76.30 100719[98:Spt:100718.0] || -> until2p7(s12)*. % 76.04/76.30 100720[98:MRR:208.0,100719.0] || -> until2p7(s13)* node4(s12). % 76.04/76.30 100721[99:Spt:100720.0] || -> until2p7(s13)*. % 76.04/76.30 100722[99:MRR:209.0,100721.0] || -> until2p7(s14)* node4(s13). % 76.04/76.30 100723[100:Spt:100722.0] || -> until2p7(s14)*. % 76.04/76.30 100724[100:MRR:210.0,100723.0] || -> until2p7(s15)* node4(s14). % 76.04/76.30 100725[101:Spt:100724.0] || -> until2p7(s15)*. % 76.04/76.30 100726[101:MRR:211.0,100725.0] || -> until2p7(s16)* node4(s15). % 76.04/76.30 100727[102:Spt:100726.0] || -> until2p7(s16)*. % 76.04/76.30 100728[102:MRR:212.0,100727.0] || -> until2p7(s17)* node4(s16). % 76.04/76.30 100729[103:Spt:100728.0] || -> until2p7(s17)*. % 76.04/76.30 100730[103:MRR:213.0,100729.0] || -> until2p7(s18)* node4(s17). % 76.04/76.30 100731[104:Spt:100730.0] || -> until2p7(s18)*. % 76.04/76.30 100732[104:MRR:214.0,100731.0] || -> until2p7(s19)* node4(s18). % 76.04/76.30 100733[105:Spt:100732.0] || -> until2p7(s19)*. % 76.04/76.30 100734[105:MRR:215.0,100733.0] || -> until2p7(s20)* node4(s19). % 76.04/76.30 100735[106:Spt:100734.0] || -> until2p7(s20)*. % 76.04/76.30 100736[106:MRR:216.0,100735.0] || -> until2p7(s21)* node4(s20). % 76.04/76.30 100737[107:Spt:100736.0] || -> until2p7(s21)*. % 76.04/76.30 100738[107:MRR:217.0,100737.0] || -> until2p7(s22)* node4(s21). % 76.04/76.30 100739[108:Spt:100738.0] || -> until2p7(s22)*. % 76.04/76.30 100740[108:MRR:218.0,100739.0] || -> until2p7(s23)* node4(s22). % 76.04/76.30 100741[109:Spt:100740.0] || -> until2p7(s23)*. % 76.04/76.30 100742[109:MRR:219.0,100741.0] || -> until2p7(s24)* node4(s23). % 76.04/76.30 100743[110:Spt:100742.0] || -> until2p7(s24)*. % 76.04/76.30 100744[110:MRR:220.0,100743.0] || -> until2p7(s25)* node4(s24). % 76.04/76.30 100745[111:Spt:100744.0] || -> until2p7(s25)*. % 76.04/76.30 100746[111:MRR:221.0,100745.0] || -> until2p7(s26)* node4(s25). % 76.04/76.30 100747[112:Spt:100746.0] || -> until2p7(s26)*. % 76.04/76.30 100748[112:MRR:222.0,100747.0] || -> until2p7(s27)* node4(s26). % 76.04/76.30 100749[113:Spt:100748.0] || -> until2p7(s27)*. % 76.04/76.30 100750[113:MRR:223.0,100749.0] || -> until2p7(s28)* node4(s27). % 76.04/76.30 100751[114:Spt:100750.0] || -> until2p7(s28)*. % 76.04/76.30 100752[114:MRR:224.0,100751.0] || -> until2p7(s29)* node4(s28). % 76.04/76.30 100753[115:Spt:100752.0] || -> until2p7(s29)*. % 76.04/76.30 100754[115:MRR:225.0,100753.0] || -> until2p7(s30)* node4(s29). % 76.04/76.30 100755[116:Spt:100754.0] || -> until2p7(s30)*. % 76.04/76.30 100756[116:MRR:226.0,100755.0] || -> until2p7(s31)* node4(s30). % 76.04/76.30 100757[117:Spt:100756.0] || -> until2p7(s31)*. % 76.04/76.30 100758[117:MRR:227.0,100757.0] || -> until2p7(s32)* node4(s31). % 76.04/76.30 100759[118:Spt:100758.0] || -> until2p7(s32)*. % 76.04/76.30 100760[118:MRR:228.0,100759.0] || -> until2p7(s33)* node4(s32). % 76.04/76.30 100761[119:Spt:100760.0] || -> until2p7(s33)*. % 76.04/76.30 100762[119:MRR:229.0,100761.0] || -> until2p7(s34)* node4(s33). % 76.04/76.30 100763[120:Spt:100762.0] || -> until2p7(s34)*. % 76.04/76.30 100764[120:MRR:230.0,100763.0] || -> until2p7(s35)* node4(s34). % 76.04/76.30 100765[121:Spt:100764.0] || -> until2p7(s35)*. % 76.04/76.30 100766[121:MRR:231.0,100765.0] || -> until2p7(s36)* node4(s35). % 76.04/76.30 100767[122:Spt:100766.0] || -> until2p7(s36)*. % 76.04/76.30 100768[122:MRR:232.0,100767.0] || -> until2p7(s37)* node4(s36). % 76.04/76.30 100769[123:Spt:100768.0] || -> until2p7(s37)*. % 76.04/76.30 100770[123:MRR:235.0,100769.0] || -> until2p7(s38)* node4(s37). % 76.04/76.30 100771[124:Spt:100770.0] || -> until2p7(s38)*. % 76.04/76.30 100772[124:MRR:236.0,100771.0] || -> until2p7(s39)* node4(s38). % 76.04/76.30 100773[125:Spt:100772.0] || -> until2p7(s39)*. % 76.04/76.30 100774[125:MRR:237.0,100773.0] || -> until2p7(s40)* node4(s39). % 76.04/76.30 100775[126:Spt:100774.0] || -> until2p7(s40)*. % 76.04/76.30 100776[126:MRR:238.0,100775.0] || -> until2p7(s41)* node4(s40). % 76.04/76.30 100777[127:Spt:100776.0] || -> until2p7(s41)*. % 76.04/76.30 100778[127:MRR:239.0,100777.0] || -> until2p7(s42)* node4(s41). % 76.04/76.30 100779[128:Spt:100778.0] || -> until2p7(s42)*. % 76.04/76.30 100780[128:MRR:240.0,100779.0] || -> until2p7(s43)* node4(s42). % 76.04/76.30 100781[129:Spt:100780.0] || -> until2p7(s43)*. % 76.04/76.30 100782[129:MRR:241.0,100781.0] || -> until2p7(s44)* node4(s43). % 76.04/76.30 100783[130:Spt:100782.0] || -> until2p7(s44)*. % 76.04/76.30 100784[130:MRR:539.0,100783.0] || -> until2p7(s45)* node4(s44). % 76.04/76.30 100785[131:Spt:100784.0] || -> until2p7(s45)*. % 76.04/76.30 100786[131:MRR:544.0,100785.0] || -> until2p7(s46)* node4(s45). % 76.04/76.30 100787[132:Spt:100786.0] || -> until2p7(s46)*. % 76.04/76.30 100788[132:MRR:549.0,100787.0] || -> until2p7(s47)* node4(s46). % 76.04/76.30 100789[133:Spt:100788.0] || -> until2p7(s47)*. % 76.04/76.30 100790[133:MRR:554.0,100789.0] || -> until2p7(s48)* node4(s47). % 76.04/76.30 100791[134:Spt:100790.0] || -> until2p7(s48)*. % 76.04/76.30 100792[134:MRR:559.0,100791.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 100793[135:Spt:100792.0] || -> until2p7(s49)*. % 76.04/76.30 100794[135:MRR:194.0,100793.0] || -> node4(s49)*. % 76.04/76.30 100795[135:MRR:100707.0,100794.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 100799[135:Res:53.1,100795.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 100801[135:MRR:100799.0,78381.0] || -> . % 76.04/76.30 100802[135:Spt:100801.0,100792.0,100793.0] || until2p7(s49)*+ -> . % 76.04/76.30 100803[135:Spt:100801.0,100792.1] || -> node4(s48)*. % 76.04/76.30 100804[135:MRR:78384.0,100803.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 100807[135:Res:53.1,100804.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 100810[135:Res:100807.0,61.1] always3(s48) || -> . % 76.04/76.30 100811[135:SSi:100810.0,78281.0,78387.0,78626.0,100791.0,100803.0] || -> . % 76.04/76.30 100812[134:Spt:100811.0,100790.0,100791.0] || until2p7(s48)*+ -> . % 76.04/76.30 100813[134:Spt:100811.0,100790.1] || -> node4(s47)*. % 76.04/76.30 100815[134:MRR:777.0,100813.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.30 100827[134:Res:53.1,100815.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.30 100829[135:Spt:100827.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 100831[135:Res:100829.0,61.1] always3(s47) || -> . % 76.04/76.30 100832[135:SSi:100831.0,78277.0,78280.0,78625.0,100789.0,100813.0] || -> . % 76.04/76.30 100833[135:Spt:100832.0,100827.0,100829.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.30 100834[135:Spt:100832.0,100827.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 100838[135:Res:100834.0,61.1] always3(s48) || -> . % 76.04/76.30 100839[135:SSi:100838.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.30 100840[133:Spt:100839.0,100788.0,100789.0] || until2p7(s47)*+ -> . % 76.04/76.30 100841[133:Spt:100839.0,100788.1] || -> node4(s46)*. % 76.04/76.30 100843[133:MRR:780.0,100841.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.30 100850[133:Res:53.1,100843.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.30 100855[134:Spt:100850.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 100857[134:Res:100855.0,61.1] always3(s46) || -> . % 76.04/76.30 100858[134:SSi:100857.0,78272.0,78276.0,78624.0,100787.0,100841.0] || -> . % 76.04/76.30 100859[134:Spt:100858.0,100850.0,100855.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.30 100860[134:Spt:100858.0,100850.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 100864[134:Res:100860.0,61.1] always3(s47) || -> . % 76.04/76.30 100865[134:SSi:100864.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.30 100866[132:Spt:100865.0,100786.0,100787.0] || until2p7(s46)*+ -> . % 76.04/76.30 100867[132:Spt:100865.0,100786.1] || -> node4(s45)*. % 76.04/76.30 100869[132:MRR:783.0,100867.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.30 100872[132:Res:53.1,100869.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.30 100874[133:Spt:100872.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 100876[133:Res:100874.0,61.1] always3(s45) || -> . % 76.04/76.30 100877[133:SSi:100876.0,78268.0,78271.0,78623.0,100785.0,100867.0] || -> . % 76.04/76.30 100878[133:Spt:100877.0,100872.0,100874.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.30 100879[133:Spt:100877.0,100872.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 100883[133:Res:100879.0,61.1] always3(s46) || -> . % 76.04/76.30 100884[133:SSi:100883.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.30 100885[131:Spt:100884.0,100784.0,100785.0] || until2p7(s45)*+ -> . % 76.04/76.30 100886[131:Spt:100884.0,100784.1] || -> node4(s44)*. % 76.04/76.30 100888[131:MRR:786.0,100886.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.30 100891[131:Res:53.1,100888.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.30 100893[132:Spt:100891.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 100895[132:Res:100893.0,61.1] always3(s44) || -> . % 76.04/76.30 100896[132:SSi:100895.0,78263.0,78267.0,78622.0,100783.0,100886.0] || -> . % 76.04/76.30 100897[132:Spt:100896.0,100891.0,100893.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.30 100898[132:Spt:100896.0,100891.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 100902[132:Res:100898.0,61.1] always3(s45) || -> . % 76.04/76.30 100903[132:SSi:100902.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.30 100904[130:Spt:100903.0,100782.0,100783.0] || until2p7(s44)*+ -> . % 76.04/76.30 100905[130:Spt:100903.0,100782.1] || -> node4(s43)*. % 76.04/76.30 100907[130:MRR:789.0,100905.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.30 100910[130:Res:53.1,100907.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.30 100912[131:Spt:100910.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 100914[131:Res:100912.0,61.1] always3(s43) || -> . % 76.04/76.30 100915[131:SSi:100914.0,78259.0,78262.0,78621.0,100781.0,100905.0] || -> . % 76.04/76.30 100916[131:Spt:100915.0,100910.0,100912.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.30 100917[131:Spt:100915.0,100910.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 100921[131:Res:100917.0,61.1] always3(s44) || -> . % 76.04/76.30 100922[131:SSi:100921.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.30 100923[129:Spt:100922.0,100780.0,100781.0] || until2p7(s43)*+ -> . % 76.04/76.30 100924[129:Spt:100922.0,100780.1] || -> node4(s42)*. % 76.04/76.30 100926[129:MRR:792.0,100924.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.30 100929[129:Res:53.1,100926.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.30 100934[130:Spt:100929.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 100936[130:Res:100934.0,61.1] always3(s42) || -> . % 76.04/76.30 100937[130:SSi:100936.0,78254.0,78258.0,78620.0,100779.0,100924.0] || -> . % 76.04/76.30 100938[130:Spt:100937.0,100929.0,100934.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.30 100939[130:Spt:100937.0,100929.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 100943[130:Res:100939.0,61.1] always3(s43) || -> . % 76.04/76.30 100944[130:SSi:100943.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.30 100945[128:Spt:100944.0,100778.0,100779.0] || until2p7(s42)*+ -> . % 76.04/76.30 100946[128:Spt:100944.0,100778.1] || -> node4(s41)*. % 76.04/76.30 100948[128:MRR:795.0,100946.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.30 100951[128:Res:53.1,100948.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.30 100953[129:Spt:100951.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 100955[129:Res:100953.0,61.1] always3(s41) || -> . % 76.04/76.30 100956[129:SSi:100955.0,78250.0,78253.0,78619.0,100777.0,100946.0] || -> . % 76.04/76.30 100957[129:Spt:100956.0,100951.0,100953.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.30 100958[129:Spt:100956.0,100951.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 100962[129:Res:100958.0,61.1] always3(s42) || -> . % 76.04/76.30 100963[129:SSi:100962.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.30 100964[127:Spt:100963.0,100776.0,100777.0] || until2p7(s41)*+ -> . % 76.04/76.30 100965[127:Spt:100963.0,100776.1] || -> node4(s40)*. % 76.04/76.30 100967[127:MRR:798.0,100965.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.30 100970[127:Res:53.1,100967.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.30 100972[128:Spt:100970.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 100974[128:Res:100972.0,61.1] always3(s40) || -> . % 76.04/76.30 100975[128:SSi:100974.0,78245.0,78249.0,78618.0,100775.0,100965.0] || -> . % 76.04/76.30 100976[128:Spt:100975.0,100970.0,100972.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.30 100977[128:Spt:100975.0,100970.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 100981[128:Res:100977.0,61.1] always3(s41) || -> . % 76.04/76.30 100982[128:SSi:100981.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.30 100983[126:Spt:100982.0,100774.0,100775.0] || until2p7(s40)*+ -> . % 76.04/76.30 100984[126:Spt:100982.0,100774.1] || -> node4(s39)*. % 76.04/76.30 100986[126:MRR:801.0,100984.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.30 100989[126:Res:53.1,100986.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.30 100991[127:Spt:100989.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 100993[127:Res:100991.0,61.1] always3(s39) || -> . % 76.04/76.30 100994[127:SSi:100993.0,78241.0,78244.0,78617.0,100773.0,100984.0] || -> . % 76.04/76.30 100995[127:Spt:100994.0,100989.0,100991.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.30 100996[127:Spt:100994.0,100989.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 101000[127:Res:100996.0,61.1] always3(s40) || -> . % 76.04/76.30 101001[127:SSi:101000.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.30 101002[125:Spt:101001.0,100772.0,100773.0] || until2p7(s39)*+ -> . % 76.04/76.30 101003[125:Spt:101001.0,100772.1] || -> node4(s38)*. % 76.04/76.30 101005[125:MRR:804.0,101003.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.30 101008[125:Res:53.1,101005.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.30 101013[126:Spt:101008.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 101015[126:Res:101013.0,61.1] always3(s38) || -> . % 76.04/76.30 101016[126:SSi:101015.0,78236.0,78240.0,78616.0,100771.0,101003.0] || -> . % 76.04/76.30 101017[126:Spt:101016.0,101008.0,101013.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.30 101018[126:Spt:101016.0,101008.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 101022[126:Res:101018.0,61.1] always3(s39) || -> . % 76.04/76.30 101023[126:SSi:101022.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.30 101024[124:Spt:101023.0,100770.0,100771.0] || until2p7(s38)*+ -> . % 76.04/76.30 101025[124:Spt:101023.0,100770.1] || -> node4(s37)*. % 76.04/76.30 101027[124:MRR:807.0,101025.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.30 101030[124:Res:53.1,101027.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.30 101032[125:Spt:101030.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 101034[125:Res:101032.0,61.1] always3(s37) || -> . % 76.04/76.30 101035[125:SSi:101034.0,78232.0,78235.0,78615.0,100769.0,101025.0] || -> . % 76.04/76.30 101036[125:Spt:101035.0,101030.0,101032.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.30 101037[125:Spt:101035.0,101030.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 101041[125:Res:101037.0,61.1] always3(s38) || -> . % 76.04/76.30 101042[125:SSi:101041.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.30 101043[123:Spt:101042.0,100768.0,100769.0] || until2p7(s37)*+ -> . % 76.04/76.30 101044[123:Spt:101042.0,100768.1] || -> node4(s36)*. % 76.04/76.30 101046[123:MRR:810.0,101044.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.30 101049[123:Res:53.1,101046.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.30 101051[124:Spt:101049.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 101053[124:Res:101051.0,61.1] always3(s36) || -> . % 76.04/76.30 101054[124:SSi:101053.0,78227.0,78231.0,78614.0,100767.0,101044.0] || -> . % 76.04/76.30 101055[124:Spt:101054.0,101049.0,101051.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.30 101056[124:Spt:101054.0,101049.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 101060[124:Res:101056.0,61.1] always3(s37) || -> . % 76.04/76.30 101061[124:SSi:101060.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.30 101062[122:Spt:101061.0,100766.0,100767.0] || until2p7(s36)*+ -> . % 76.04/76.30 101063[122:Spt:101061.0,100766.1] || -> node4(s35)*. % 76.04/76.30 101065[122:MRR:813.0,101063.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.30 101068[122:Res:53.1,101065.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.30 101070[123:Spt:101068.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 101072[123:Res:101070.0,61.1] always3(s35) || -> . % 76.04/76.30 101073[123:SSi:101072.0,78223.0,78226.0,78613.0,100765.0,101063.0] || -> . % 76.04/76.30 101074[123:Spt:101073.0,101068.0,101070.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.30 101075[123:Spt:101073.0,101068.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 101079[123:Res:101075.0,61.1] always3(s36) || -> . % 76.04/76.30 101080[123:SSi:101079.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.30 101081[121:Spt:101080.0,100764.0,100765.0] || until2p7(s35)*+ -> . % 76.04/76.30 101082[121:Spt:101080.0,100764.1] || -> node4(s34)*. % 76.04/76.30 101084[121:MRR:816.0,101082.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.30 101087[121:Res:53.1,101084.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.30 101092[122:Spt:101087.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 101094[122:Res:101092.0,61.1] always3(s34) || -> . % 76.04/76.30 101095[122:SSi:101094.0,78218.0,78222.0,78612.0,100763.0,101082.0] || -> . % 76.04/76.30 101096[122:Spt:101095.0,101087.0,101092.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.30 101097[122:Spt:101095.0,101087.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 101101[122:Res:101097.0,61.1] always3(s35) || -> . % 76.04/76.30 101102[122:SSi:101101.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.30 101103[120:Spt:101102.0,100762.0,100763.0] || until2p7(s34)*+ -> . % 76.04/76.30 101104[120:Spt:101102.0,100762.1] || -> node4(s33)*. % 76.04/76.30 101106[120:MRR:819.0,101104.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.30 101109[120:Res:53.1,101106.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.30 101111[121:Spt:101109.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 101113[121:Res:101111.0,61.1] always3(s33) || -> . % 76.04/76.30 101114[121:SSi:101113.0,78214.0,78217.0,78611.0,100761.0,101104.0] || -> . % 76.04/76.30 101115[121:Spt:101114.0,101109.0,101111.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.30 101116[121:Spt:101114.0,101109.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 101120[121:Res:101116.0,61.1] always3(s34) || -> . % 76.04/76.30 101121[121:SSi:101120.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.30 101122[119:Spt:101121.0,100760.0,100761.0] || until2p7(s33)*+ -> . % 76.04/76.30 101123[119:Spt:101121.0,100760.1] || -> node4(s32)*. % 76.04/76.30 101125[119:MRR:822.0,101123.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.30 101128[119:Res:53.1,101125.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.30 101130[120:Spt:101128.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 101132[120:Res:101130.0,61.1] always3(s32) || -> . % 76.04/76.30 101133[120:SSi:101132.0,78209.0,78213.0,78610.0,100759.0,101123.0] || -> . % 76.04/76.30 101134[120:Spt:101133.0,101128.0,101130.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.30 101135[120:Spt:101133.0,101128.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 101139[120:Res:101135.0,61.1] always3(s33) || -> . % 76.04/76.30 101140[120:SSi:101139.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.30 101141[118:Spt:101140.0,100758.0,100759.0] || until2p7(s32)*+ -> . % 76.04/76.30 101142[118:Spt:101140.0,100758.1] || -> node4(s31)*. % 76.04/76.30 101144[118:MRR:825.0,101142.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.30 101147[118:Res:53.1,101144.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.30 101149[119:Spt:101147.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 101151[119:Res:101149.0,61.1] always3(s31) || -> . % 76.04/76.30 101152[119:SSi:101151.0,78205.0,78208.0,78609.0,100757.0,101142.0] || -> . % 76.04/76.30 101153[119:Spt:101152.0,101147.0,101149.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.30 101154[119:Spt:101152.0,101147.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 101158[119:Res:101154.0,61.1] always3(s32) || -> . % 76.04/76.30 101159[119:SSi:101158.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.30 101160[117:Spt:101159.0,100756.0,100757.0] || until2p7(s31)*+ -> . % 76.04/76.30 101161[117:Spt:101159.0,100756.1] || -> node4(s30)*. % 76.04/76.30 101163[117:MRR:828.0,101161.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.30 101166[117:Res:53.1,101163.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.30 101171[118:Spt:101166.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 101173[118:Res:101171.0,61.1] always3(s30) || -> . % 76.04/76.30 101174[118:SSi:101173.0,78200.0,78204.0,78608.0,100755.0,101161.0] || -> . % 76.04/76.30 101175[118:Spt:101174.0,101166.0,101171.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.30 101176[118:Spt:101174.0,101166.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 101180[118:Res:101176.0,61.1] always3(s31) || -> . % 76.04/76.30 101181[118:SSi:101180.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.30 101182[116:Spt:101181.0,100754.0,100755.0] || until2p7(s30)*+ -> . % 76.04/76.30 101183[116:Spt:101181.0,100754.1] || -> node4(s29)*. % 76.04/76.30 101185[116:MRR:831.0,101183.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.30 101188[116:Res:53.1,101185.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.30 101190[117:Spt:101188.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 101192[117:Res:101190.0,61.1] always3(s29) || -> . % 76.04/76.30 101193[117:SSi:101192.0,78196.0,78199.0,78607.0,100753.0,101183.0] || -> . % 76.04/76.30 101194[117:Spt:101193.0,101188.0,101190.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.30 101195[117:Spt:101193.0,101188.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 101199[117:Res:101195.0,61.1] always3(s30) || -> . % 76.04/76.30 101200[117:SSi:101199.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.30 101201[115:Spt:101200.0,100752.0,100753.0] || until2p7(s29)*+ -> . % 76.04/76.30 101202[115:Spt:101200.0,100752.1] || -> node4(s28)*. % 76.04/76.30 101204[115:MRR:834.0,101202.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.30 101207[115:Res:53.1,101204.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.30 101209[116:Spt:101207.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 101211[116:Res:101209.0,61.1] always3(s28) || -> . % 76.04/76.30 101212[116:SSi:101211.0,78191.0,78195.0,78606.0,100751.0,101202.0] || -> . % 76.04/76.30 101213[116:Spt:101212.0,101207.0,101209.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.30 101214[116:Spt:101212.0,101207.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 101218[116:Res:101214.0,61.1] always3(s29) || -> . % 76.04/76.30 101219[116:SSi:101218.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.30 101220[114:Spt:101219.0,100750.0,100751.0] || until2p7(s28)*+ -> . % 76.04/76.30 101221[114:Spt:101219.0,100750.1] || -> node4(s27)*. % 76.04/76.30 101223[114:MRR:837.0,101221.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.30 101226[114:Res:53.1,101223.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.30 101228[115:Spt:101226.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 101230[115:Res:101228.0,61.1] always3(s27) || -> . % 76.04/76.30 101231[115:SSi:101230.0,78187.0,78190.0,78605.0,100749.0,101221.0] || -> . % 76.04/76.30 101232[115:Spt:101231.0,101226.0,101228.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.30 101233[115:Spt:101231.0,101226.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 101237[115:Res:101233.0,61.1] always3(s28) || -> . % 76.04/76.30 101238[115:SSi:101237.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.30 101239[113:Spt:101238.0,100748.0,100749.0] || until2p7(s27)*+ -> . % 76.04/76.30 101240[113:Spt:101238.0,100748.1] || -> node4(s26)*. % 76.04/76.30 101242[113:MRR:840.0,101240.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.30 101245[113:Res:53.1,101242.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.30 101250[114:Spt:101245.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 101252[114:Res:101250.0,61.1] always3(s26) || -> . % 76.04/76.30 101253[114:SSi:101252.0,78182.0,78186.0,78604.0,100747.0,101240.0] || -> . % 76.04/76.30 101254[114:Spt:101253.0,101245.0,101250.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.30 101255[114:Spt:101253.0,101245.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 101259[114:Res:101255.0,61.1] always3(s27) || -> . % 76.04/76.30 101260[114:SSi:101259.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.30 101261[112:Spt:101260.0,100746.0,100747.0] || until2p7(s26)*+ -> . % 76.04/76.30 101262[112:Spt:101260.0,100746.1] || -> node4(s25)*. % 76.04/76.30 101264[112:MRR:843.0,101262.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.30 101267[112:Res:53.1,101264.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.30 101269[113:Spt:101267.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 101271[113:Res:101269.0,61.1] always3(s25) || -> . % 76.04/76.30 101272[113:SSi:101271.0,78178.0,78181.0,78603.0,100745.0,101262.0] || -> . % 76.04/76.30 101273[113:Spt:101272.0,101267.0,101269.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.30 101274[113:Spt:101272.0,101267.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 101278[113:Res:101274.0,61.1] always3(s26) || -> . % 76.04/76.30 101279[113:SSi:101278.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.30 101280[111:Spt:101279.0,100744.0,100745.0] || until2p7(s25)*+ -> . % 76.04/76.30 101281[111:Spt:101279.0,100744.1] || -> node4(s24)*. % 76.04/76.30 101283[111:MRR:846.0,101281.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.30 101286[111:Res:53.1,101283.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.30 101288[112:Spt:101286.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 101290[112:Res:101288.0,61.1] always3(s24) || -> . % 76.04/76.30 101291[112:SSi:101290.0,78173.0,78177.0,78602.0,100743.0,101281.0] || -> . % 76.04/76.30 101292[112:Spt:101291.0,101286.0,101288.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.30 101293[112:Spt:101291.0,101286.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 101297[112:Res:101293.0,61.1] always3(s25) || -> . % 76.04/76.30 101298[112:SSi:101297.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.30 101299[110:Spt:101298.0,100742.0,100743.0] || until2p7(s24)*+ -> . % 76.04/76.30 101300[110:Spt:101298.0,100742.1] || -> node4(s23)*. % 76.04/76.30 101302[110:MRR:849.0,101300.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.30 101305[110:Res:53.1,101302.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.30 101307[111:Spt:101305.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 101309[111:Res:101307.0,61.1] always3(s23) || -> . % 76.04/76.30 101310[111:SSi:101309.0,78169.0,78172.0,78601.0,100741.0,101300.0] || -> . % 76.04/76.30 101311[111:Spt:101310.0,101305.0,101307.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.30 101312[111:Spt:101310.0,101305.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 101316[111:Res:101312.0,61.1] always3(s24) || -> . % 76.04/76.30 101317[111:SSi:101316.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.30 101318[109:Spt:101317.0,100740.0,100741.0] || until2p7(s23)*+ -> . % 76.04/76.30 101319[109:Spt:101317.0,100740.1] || -> node4(s22)*. % 76.04/76.30 101321[109:MRR:852.0,101319.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.30 101324[109:Res:53.1,101321.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.30 101329[110:Spt:101324.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 101331[110:Res:101329.0,61.1] always3(s22) || -> . % 76.04/76.30 101332[110:SSi:101331.0,78164.0,78168.0,78600.0,100739.0,101319.0] || -> . % 76.04/76.30 101333[110:Spt:101332.0,101324.0,101329.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.30 101334[110:Spt:101332.0,101324.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 101338[110:Res:101334.0,61.1] always3(s23) || -> . % 76.04/76.30 101339[110:SSi:101338.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.30 101340[108:Spt:101339.0,100738.0,100739.0] || until2p7(s22)*+ -> . % 76.04/76.30 101341[108:Spt:101339.0,100738.1] || -> node4(s21)*. % 76.04/76.30 101343[108:MRR:855.0,101341.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.30 101346[108:Res:53.1,101343.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.30 101348[109:Spt:101346.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 101350[109:Res:101348.0,61.1] always3(s21) || -> . % 76.04/76.30 101351[109:SSi:101350.0,78160.0,78163.0,78599.0,100737.0,101341.0] || -> . % 76.04/76.30 101352[109:Spt:101351.0,101346.0,101348.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.30 101353[109:Spt:101351.0,101346.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 101357[109:Res:101353.0,61.1] always3(s22) || -> . % 76.04/76.30 101358[109:SSi:101357.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.30 101359[107:Spt:101358.0,100736.0,100737.0] || until2p7(s21)*+ -> . % 76.04/76.30 101360[107:Spt:101358.0,100736.1] || -> node4(s20)*. % 76.04/76.30 101362[107:MRR:858.0,101360.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.30 101365[107:Res:53.1,101362.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.30 101367[108:Spt:101365.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 101369[108:Res:101367.0,61.1] always3(s20) || -> . % 76.04/76.30 101370[108:SSi:101369.0,78155.0,78159.0,78598.0,100735.0,101360.0] || -> . % 76.04/76.30 101371[108:Spt:101370.0,101365.0,101367.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.30 101372[108:Spt:101370.0,101365.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 101376[108:Res:101372.0,61.1] always3(s21) || -> . % 76.04/76.30 101377[108:SSi:101376.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.30 101378[106:Spt:101377.0,100734.0,100735.0] || until2p7(s20)*+ -> . % 76.04/76.30 101379[106:Spt:101377.0,100734.1] || -> node4(s19)*. % 76.04/76.30 101381[106:MRR:861.0,101379.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.30 101384[106:Res:53.1,101381.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.30 101386[107:Spt:101384.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 101388[107:Res:101386.0,61.1] always3(s19) || -> . % 76.04/76.30 101389[107:SSi:101388.0,78151.0,78154.0,78597.0,100733.0,101379.0] || -> . % 76.04/76.30 101390[107:Spt:101389.0,101384.0,101386.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.30 101391[107:Spt:101389.0,101384.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 101395[107:Res:101391.0,61.1] always3(s20) || -> . % 76.04/76.30 101396[107:SSi:101395.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.30 101397[105:Spt:101396.0,100732.0,100733.0] || until2p7(s19)*+ -> . % 76.04/76.30 101398[105:Spt:101396.0,100732.1] || -> node4(s18)*. % 76.04/76.30 101400[105:MRR:864.0,101398.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.30 101403[105:Res:53.1,101400.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.30 101408[106:Spt:101403.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 101410[106:Res:101408.0,61.1] always3(s18) || -> . % 76.04/76.30 101411[106:SSi:101410.0,78146.0,78150.0,78596.0,100731.0,101398.0] || -> . % 76.04/76.30 101412[106:Spt:101411.0,101403.0,101408.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.30 101413[106:Spt:101411.0,101403.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 101417[106:Res:101413.0,61.1] always3(s19) || -> . % 76.04/76.30 101418[106:SSi:101417.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.30 101419[104:Spt:101418.0,100730.0,100731.0] || until2p7(s18)*+ -> . % 76.04/76.30 101420[104:Spt:101418.0,100730.1] || -> node4(s17)*. % 76.04/76.30 101422[104:MRR:867.0,101420.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.30 101425[104:Res:53.1,101422.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.30 101427[105:Spt:101425.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 101429[105:Res:101427.0,61.1] always3(s17) || -> . % 76.04/76.30 101430[105:SSi:101429.0,78142.0,78145.0,78595.0,100729.0,101420.0] || -> . % 76.04/76.30 101431[105:Spt:101430.0,101425.0,101427.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.30 101432[105:Spt:101430.0,101425.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 101436[105:Res:101432.0,61.1] always3(s18) || -> . % 76.04/76.30 101437[105:SSi:101436.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.30 101438[103:Spt:101437.0,100728.0,100729.0] || until2p7(s17)*+ -> . % 76.04/76.30 101439[103:Spt:101437.0,100728.1] || -> node4(s16)*. % 76.04/76.30 101441[103:MRR:870.0,101439.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.30 101444[103:Res:53.1,101441.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.30 101446[104:Spt:101444.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 101448[104:Res:101446.0,61.1] always3(s16) || -> . % 76.04/76.30 101449[104:SSi:101448.0,78137.0,78141.0,78594.0,100727.0,101439.0] || -> . % 76.04/76.30 101450[104:Spt:101449.0,101444.0,101446.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.30 101451[104:Spt:101449.0,101444.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 101455[104:Res:101451.0,61.1] always3(s17) || -> . % 76.04/76.30 101456[104:SSi:101455.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.30 101457[102:Spt:101456.0,100726.0,100727.0] || until2p7(s16)*+ -> . % 76.04/76.30 101458[102:Spt:101456.0,100726.1] || -> node4(s15)*. % 76.04/76.30 101460[102:MRR:873.0,101458.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.30 101463[102:Res:53.1,101460.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.30 101465[103:Spt:101463.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 101467[103:Res:101465.0,61.1] always3(s15) || -> . % 76.04/76.30 101468[103:SSi:101467.0,78133.0,78136.0,78593.0,100725.0,101458.0] || -> . % 76.04/76.30 101469[103:Spt:101468.0,101463.0,101465.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.30 101470[103:Spt:101468.0,101463.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 101474[103:Res:101470.0,61.1] always3(s16) || -> . % 76.04/76.30 101475[103:SSi:101474.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.30 101476[101:Spt:101475.0,100724.0,100725.0] || until2p7(s15)*+ -> . % 76.04/76.30 101477[101:Spt:101475.0,100724.1] || -> node4(s14)*. % 76.04/76.30 101479[101:MRR:876.0,101477.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.30 101482[101:Res:53.1,101479.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.30 101487[102:Spt:101482.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 101489[102:Res:101487.0,61.1] always3(s14) || -> . % 76.04/76.30 101490[102:SSi:101489.0,78128.0,78132.0,78592.0,100723.0,101477.0] || -> . % 76.04/76.30 101491[102:Spt:101490.0,101482.0,101487.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.30 101492[102:Spt:101490.0,101482.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 101496[102:Res:101492.0,61.1] always3(s15) || -> . % 76.04/76.30 101497[102:SSi:101496.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.30 101498[100:Spt:101497.0,100722.0,100723.0] || until2p7(s14)*+ -> . % 76.04/76.30 101499[100:Spt:101497.0,100722.1] || -> node4(s13)*. % 76.04/76.30 101501[100:MRR:879.0,101499.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.30 101504[100:Res:53.1,101501.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.30 101506[101:Spt:101504.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 101508[101:Res:101506.0,61.1] always3(s13) || -> . % 76.04/76.30 101509[101:SSi:101508.0,78124.0,78127.0,78591.0,100721.0,101499.0] || -> . % 76.04/76.30 101510[101:Spt:101509.0,101504.0,101506.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.30 101511[101:Spt:101509.0,101504.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 101515[101:Res:101511.0,61.1] always3(s14) || -> . % 76.04/76.30 101516[101:SSi:101515.0,78128.0,78132.0,78592.0] || -> . % 76.04/76.30 101517[99:Spt:101516.0,100720.0,100721.0] || until2p7(s13)*+ -> . % 76.04/76.30 101518[99:Spt:101516.0,100720.1] || -> node4(s12)*. % 76.04/76.30 101520[99:MRR:882.0,101518.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.30 101523[99:Res:53.1,101520.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.30 101525[100:Spt:101523.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 101527[100:Res:101525.0,61.1] always3(s12) || -> . % 76.04/76.30 101528[100:SSi:101527.0,78119.0,78123.0,78590.0,100719.0,101518.0] || -> . % 76.04/76.30 101529[100:Spt:101528.0,101523.0,101525.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.30 101530[100:Spt:101528.0,101523.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 101534[100:Res:101530.0,61.1] always3(s13) || -> . % 76.04/76.30 101535[100:SSi:101534.0,78124.0,78127.0,78591.0] || -> . % 76.04/76.30 101536[98:Spt:101535.0,100718.0,100719.0] || until2p7(s12)*+ -> . % 76.04/76.30 101537[98:Spt:101535.0,100718.1] || -> node4(s11)*. % 76.04/76.30 101539[98:MRR:885.0,101537.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.30 101542[98:Res:53.1,101539.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.30 101544[99:Spt:101542.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 101546[99:Res:101544.0,61.1] always3(s11) || -> . % 76.04/76.30 101547[99:SSi:101546.0,78115.0,78118.0,78589.0,100717.0,101537.0] || -> . % 76.04/76.30 101548[99:Spt:101547.0,101542.0,101544.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.30 101549[99:Spt:101547.0,101542.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 101553[99:Res:101549.0,61.1] always3(s12) || -> . % 76.04/76.30 101554[99:SSi:101553.0,78119.0,78123.0,78590.0] || -> . % 76.04/76.30 101555[97:Spt:101554.0,100716.0,100717.0] || until2p7(s11)*+ -> . % 76.04/76.30 101556[97:Spt:101554.0,100716.1] || -> node4(s10)*. % 76.04/76.30 101558[97:MRR:888.0,101556.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.30 101561[97:Res:53.1,101558.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.30 101566[98:Spt:101561.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 101568[98:Res:101566.0,61.1] always3(s10) || -> . % 76.04/76.30 101569[98:SSi:101568.0,78110.0,78114.0,78588.0,100715.0,101556.0] || -> . % 76.04/76.30 101570[98:Spt:101569.0,101561.0,101566.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.30 101571[98:Spt:101569.0,101561.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 101575[98:Res:101571.0,61.1] always3(s11) || -> . % 76.04/76.30 101576[98:SSi:101575.0,78115.0,78118.0,78589.0] || -> . % 76.04/76.30 101577[96:Spt:101576.0,100714.0,100715.0] || until2p7(s10)*+ -> . % 76.04/76.30 101578[96:Spt:101576.0,100714.1] || -> node4(s9)*. % 76.04/76.30 101580[96:MRR:891.0,101578.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.30 101583[96:Res:53.1,101580.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.30 101585[97:Spt:101583.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 101587[97:Res:101585.0,61.1] always3(s9) || -> . % 76.04/76.30 101588[97:SSi:101587.0,78106.0,78109.0,78587.0,100713.0,101578.0] || -> . % 76.04/76.30 101589[97:Spt:101588.0,101583.0,101585.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.30 101590[97:Spt:101588.0,101583.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 101594[97:Res:101590.0,61.1] always3(s10) || -> . % 76.04/76.30 101595[97:SSi:101594.0,78110.0,78114.0,78588.0] || -> . % 76.04/76.30 101596[95:Spt:101595.0,100712.0,100713.0] || until2p7(s9)*+ -> . % 76.04/76.30 101597[95:Spt:101595.0,100712.1] || -> node4(s8)*. % 76.04/76.30 101599[95:MRR:894.0,101597.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.30 101602[95:Res:53.1,101599.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.30 101604[95:MRR:101602.0,100702.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 101606[95:Res:101604.0,61.1] always3(s9) || -> . % 76.04/76.30 101607[95:SSi:101606.0,78106.0,78109.0,78587.0] || -> . % 76.04/76.30 101608[93:Spt:101607.0,100549.0,100552.0] || trans(s49,s8)*+ -> . % 76.04/76.30 101609[93:Spt:101607.0,100549.1,100549.2,100549.3,100549.4,100549.5,100549.6] || -> trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.30 101611[93:MRR:100551.1,101608.0] xuntil6(s49) || -> trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.30 101612[94:Spt:101609.0] || -> trans(s49,s7)*. % 76.04/76.30 101613[94:Res:101612.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s7)*. % 76.04/76.30 101615[94:Res:101612.0,60.0] || -> node2(s49,s7)*. % 76.04/76.30 101616[94:SSi:101613.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s7)*. % 76.04/76.30 101617[94:Res:101615.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)*. % 76.04/76.30 101758[94:SoR:101617.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)*. % 76.04/76.30 101760[94:SoR:101758.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)* xuntil6(s49). % 76.04/76.30 101761[94:SSi:101760.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s7,c_busy)* xuntil6(s49). % 76.04/76.30 101762[95:Spt:101761.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.30 101764[95:Res:101762.0,61.1] always3(s7) || -> . % 76.04/76.30 101765[95:SSi:101764.0,78097.0,78100.0,78585.0] || -> . % 76.04/76.30 101766[95:Spt:101765.0,101761.1,101762.0] || m_main_v_state(s7,c_busy)*+ -> . % 76.04/76.30 101767[95:Spt:101765.0,101761.0,101761.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 101771[95:MRR:101758.2,101766.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 101772[95:Res:53.1,101767.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 101774[95:MRR:101772.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 101775[95:MRR:101616.0,101774.0] || -> until2p7(s7)*. % 76.04/76.30 101776[95:MRR:203.0,101775.0] || -> until2p7(s8)* node4(s7). % 76.04/76.30 101777[96:Spt:101776.0] || -> until2p7(s8)*. % 76.04/76.30 101778[96:MRR:204.0,101777.0] || -> until2p7(s9)* node4(s8). % 76.04/76.30 101779[97:Spt:101778.0] || -> until2p7(s9)*. % 76.04/76.30 101780[97:MRR:205.0,101779.0] || -> until2p7(s10)* node4(s9). % 76.04/76.30 101781[98:Spt:101780.0] || -> until2p7(s10)*. % 76.04/76.30 101782[98:MRR:206.0,101781.0] || -> until2p7(s11)* node4(s10). % 76.04/76.30 101783[99:Spt:101782.0] || -> until2p7(s11)*. % 76.04/76.30 101784[99:MRR:207.0,101783.0] || -> until2p7(s12)* node4(s11). % 76.04/76.30 101785[100:Spt:101784.0] || -> until2p7(s12)*. % 76.04/76.30 101786[100:MRR:208.0,101785.0] || -> until2p7(s13)* node4(s12). % 76.04/76.30 101787[101:Spt:101786.0] || -> until2p7(s13)*. % 76.04/76.30 101788[101:MRR:209.0,101787.0] || -> until2p7(s14)* node4(s13). % 76.04/76.30 101789[102:Spt:101788.0] || -> until2p7(s14)*. % 76.04/76.30 101790[102:MRR:210.0,101789.0] || -> until2p7(s15)* node4(s14). % 76.04/76.30 101791[103:Spt:101790.0] || -> until2p7(s15)*. % 76.04/76.30 101792[103:MRR:211.0,101791.0] || -> until2p7(s16)* node4(s15). % 76.04/76.30 101793[104:Spt:101792.0] || -> until2p7(s16)*. % 76.04/76.30 101794[104:MRR:212.0,101793.0] || -> until2p7(s17)* node4(s16). % 76.04/76.30 101795[105:Spt:101794.0] || -> until2p7(s17)*. % 76.04/76.30 101796[105:MRR:213.0,101795.0] || -> until2p7(s18)* node4(s17). % 76.04/76.30 101797[106:Spt:101796.0] || -> until2p7(s18)*. % 76.04/76.30 101798[106:MRR:214.0,101797.0] || -> until2p7(s19)* node4(s18). % 76.04/76.30 101799[107:Spt:101798.0] || -> until2p7(s19)*. % 76.04/76.30 101800[107:MRR:215.0,101799.0] || -> until2p7(s20)* node4(s19). % 76.04/76.30 101801[108:Spt:101800.0] || -> until2p7(s20)*. % 76.04/76.30 101802[108:MRR:216.0,101801.0] || -> until2p7(s21)* node4(s20). % 76.04/76.30 101803[109:Spt:101802.0] || -> until2p7(s21)*. % 76.04/76.30 101804[109:MRR:217.0,101803.0] || -> until2p7(s22)* node4(s21). % 76.04/76.30 101805[110:Spt:101804.0] || -> until2p7(s22)*. % 76.04/76.30 101806[110:MRR:218.0,101805.0] || -> until2p7(s23)* node4(s22). % 76.04/76.30 101807[111:Spt:101806.0] || -> until2p7(s23)*. % 76.04/76.30 101808[111:MRR:219.0,101807.0] || -> until2p7(s24)* node4(s23). % 76.04/76.30 101809[112:Spt:101808.0] || -> until2p7(s24)*. % 76.04/76.30 101810[112:MRR:220.0,101809.0] || -> until2p7(s25)* node4(s24). % 76.04/76.30 101811[113:Spt:101810.0] || -> until2p7(s25)*. % 76.04/76.30 101812[113:MRR:221.0,101811.0] || -> until2p7(s26)* node4(s25). % 76.04/76.30 101813[114:Spt:101812.0] || -> until2p7(s26)*. % 76.04/76.30 101814[114:MRR:222.0,101813.0] || -> until2p7(s27)* node4(s26). % 76.04/76.30 101815[115:Spt:101814.0] || -> until2p7(s27)*. % 76.04/76.30 101816[115:MRR:223.0,101815.0] || -> until2p7(s28)* node4(s27). % 76.04/76.30 101817[116:Spt:101816.0] || -> until2p7(s28)*. % 76.04/76.30 101818[116:MRR:224.0,101817.0] || -> until2p7(s29)* node4(s28). % 76.04/76.30 101819[117:Spt:101818.0] || -> until2p7(s29)*. % 76.04/76.30 101820[117:MRR:225.0,101819.0] || -> until2p7(s30)* node4(s29). % 76.04/76.30 101821[118:Spt:101820.0] || -> until2p7(s30)*. % 76.04/76.30 101822[118:MRR:226.0,101821.0] || -> until2p7(s31)* node4(s30). % 76.04/76.30 101823[119:Spt:101822.0] || -> until2p7(s31)*. % 76.04/76.30 101824[119:MRR:227.0,101823.0] || -> until2p7(s32)* node4(s31). % 76.04/76.30 101825[120:Spt:101824.0] || -> until2p7(s32)*. % 76.04/76.30 101826[120:MRR:228.0,101825.0] || -> until2p7(s33)* node4(s32). % 76.04/76.30 101827[121:Spt:101826.0] || -> until2p7(s33)*. % 76.04/76.30 101828[121:MRR:229.0,101827.0] || -> until2p7(s34)* node4(s33). % 76.04/76.30 101829[122:Spt:101828.0] || -> until2p7(s34)*. % 76.04/76.30 101830[122:MRR:230.0,101829.0] || -> until2p7(s35)* node4(s34). % 76.04/76.30 101831[123:Spt:101830.0] || -> until2p7(s35)*. % 76.04/76.30 101832[123:MRR:231.0,101831.0] || -> until2p7(s36)* node4(s35). % 76.04/76.30 101833[124:Spt:101832.0] || -> until2p7(s36)*. % 76.04/76.30 101834[124:MRR:232.0,101833.0] || -> until2p7(s37)* node4(s36). % 76.04/76.30 101835[125:Spt:101834.0] || -> until2p7(s37)*. % 76.04/76.30 101836[125:MRR:235.0,101835.0] || -> until2p7(s38)* node4(s37). % 76.04/76.30 101837[126:Spt:101836.0] || -> until2p7(s38)*. % 76.04/76.30 101838[126:MRR:236.0,101837.0] || -> until2p7(s39)* node4(s38). % 76.04/76.30 101839[127:Spt:101838.0] || -> until2p7(s39)*. % 76.04/76.30 101840[127:MRR:237.0,101839.0] || -> until2p7(s40)* node4(s39). % 76.04/76.30 101841[128:Spt:101840.0] || -> until2p7(s40)*. % 76.04/76.30 101842[128:MRR:238.0,101841.0] || -> until2p7(s41)* node4(s40). % 76.04/76.30 101843[129:Spt:101842.0] || -> until2p7(s41)*. % 76.04/76.30 101844[129:MRR:239.0,101843.0] || -> until2p7(s42)* node4(s41). % 76.04/76.30 101845[130:Spt:101844.0] || -> until2p7(s42)*. % 76.04/76.30 101846[130:MRR:240.0,101845.0] || -> until2p7(s43)* node4(s42). % 76.04/76.30 101847[131:Spt:101846.0] || -> until2p7(s43)*. % 76.04/76.30 101848[131:MRR:241.0,101847.0] || -> until2p7(s44)* node4(s43). % 76.04/76.30 101849[132:Spt:101848.0] || -> until2p7(s44)*. % 76.04/76.30 101850[132:MRR:539.0,101849.0] || -> until2p7(s45)* node4(s44). % 76.04/76.30 101851[133:Spt:101850.0] || -> until2p7(s45)*. % 76.04/76.30 101852[133:MRR:544.0,101851.0] || -> until2p7(s46)* node4(s45). % 76.04/76.30 101853[134:Spt:101852.0] || -> until2p7(s46)*. % 76.04/76.30 101854[134:MRR:549.0,101853.0] || -> until2p7(s47)* node4(s46). % 76.04/76.30 101855[135:Spt:101854.0] || -> until2p7(s47)*. % 76.04/76.30 101856[135:MRR:554.0,101855.0] || -> until2p7(s48)* node4(s47). % 76.04/76.30 101857[136:Spt:101856.0] || -> until2p7(s48)*. % 76.04/76.30 101858[136:MRR:559.0,101857.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 101859[137:Spt:101858.0] || -> until2p7(s49)*. % 76.04/76.30 101860[137:MRR:194.0,101859.0] || -> node4(s49)*. % 76.04/76.30 101861[137:MRR:101771.0,101860.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 101862[137:Res:53.1,101861.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 101864[137:MRR:101862.0,78381.0] || -> . % 76.04/76.30 101865[137:Spt:101864.0,101858.0,101859.0] || until2p7(s49)*+ -> . % 76.04/76.30 101866[137:Spt:101864.0,101858.1] || -> node4(s48)*. % 76.04/76.30 101867[137:MRR:78384.0,101866.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 101870[137:Res:53.1,101867.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 101873[137:Res:101870.0,61.1] always3(s48) || -> . % 76.04/76.30 101874[137:SSi:101873.0,78281.0,78387.0,78626.0,101857.0,101866.0] || -> . % 76.04/76.30 101875[136:Spt:101874.0,101856.0,101857.0] || until2p7(s48)*+ -> . % 76.04/76.30 101876[136:Spt:101874.0,101856.1] || -> node4(s47)*. % 76.04/76.30 101878[136:MRR:777.0,101876.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.30 101893[136:Res:53.1,101878.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.30 101898[137:Spt:101893.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 101900[137:Res:101898.0,61.1] always3(s47) || -> . % 76.04/76.30 101901[137:SSi:101900.0,78277.0,78280.0,78625.0,101855.0,101876.0] || -> . % 76.04/76.30 101902[137:Spt:101901.0,101893.0,101898.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.30 101903[137:Spt:101901.0,101893.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 101907[137:Res:101903.0,61.1] always3(s48) || -> . % 76.04/76.30 101908[137:SSi:101907.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.30 101909[135:Spt:101908.0,101854.0,101855.0] || until2p7(s47)*+ -> . % 76.04/76.30 101910[135:Spt:101908.0,101854.1] || -> node4(s46)*. % 76.04/76.30 101912[135:MRR:780.0,101910.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.30 101919[135:Res:53.1,101912.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.30 101921[136:Spt:101919.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 101923[136:Res:101921.0,61.1] always3(s46) || -> . % 76.04/76.30 101924[136:SSi:101923.0,78272.0,78276.0,78624.0,101853.0,101910.0] || -> . % 76.04/76.30 101925[136:Spt:101924.0,101919.0,101921.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.30 101926[136:Spt:101924.0,101919.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 101930[136:Res:101926.0,61.1] always3(s47) || -> . % 76.04/76.30 101931[136:SSi:101930.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.30 101932[134:Spt:101931.0,101852.0,101853.0] || until2p7(s46)*+ -> . % 76.04/76.30 101933[134:Spt:101931.0,101852.1] || -> node4(s45)*. % 76.04/76.30 101935[134:MRR:783.0,101933.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.30 101938[134:Res:53.1,101935.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.30 101943[135:Spt:101938.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 101945[135:Res:101943.0,61.1] always3(s45) || -> . % 76.04/76.30 101946[135:SSi:101945.0,78268.0,78271.0,78623.0,101851.0,101933.0] || -> . % 76.04/76.30 101947[135:Spt:101946.0,101938.0,101943.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.30 101948[135:Spt:101946.0,101938.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 101952[135:Res:101948.0,61.1] always3(s46) || -> . % 76.04/76.30 101953[135:SSi:101952.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.30 101954[133:Spt:101953.0,101850.0,101851.0] || until2p7(s45)*+ -> . % 76.04/76.30 101955[133:Spt:101953.0,101850.1] || -> node4(s44)*. % 76.04/76.30 101957[133:MRR:786.0,101955.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.30 101960[133:Res:53.1,101957.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.30 101962[134:Spt:101960.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 101964[134:Res:101962.0,61.1] always3(s44) || -> . % 76.04/76.30 101965[134:SSi:101964.0,78263.0,78267.0,78622.0,101849.0,101955.0] || -> . % 76.04/76.30 101966[134:Spt:101965.0,101960.0,101962.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.30 101967[134:Spt:101965.0,101960.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 101971[134:Res:101967.0,61.1] always3(s45) || -> . % 76.04/76.30 101972[134:SSi:101971.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.30 101973[132:Spt:101972.0,101848.0,101849.0] || until2p7(s44)*+ -> . % 76.04/76.30 101974[132:Spt:101972.0,101848.1] || -> node4(s43)*. % 76.04/76.30 101976[132:MRR:789.0,101974.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.30 101979[132:Res:53.1,101976.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.30 101981[133:Spt:101979.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 101983[133:Res:101981.0,61.1] always3(s43) || -> . % 76.04/76.30 101984[133:SSi:101983.0,78259.0,78262.0,78621.0,101847.0,101974.0] || -> . % 76.04/76.30 101985[133:Spt:101984.0,101979.0,101981.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.30 101986[133:Spt:101984.0,101979.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 101990[133:Res:101986.0,61.1] always3(s44) || -> . % 76.04/76.30 101991[133:SSi:101990.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.30 101992[131:Spt:101991.0,101846.0,101847.0] || until2p7(s43)*+ -> . % 76.04/76.30 101993[131:Spt:101991.0,101846.1] || -> node4(s42)*. % 76.04/76.30 101995[131:MRR:792.0,101993.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.30 101998[131:Res:53.1,101995.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.30 102000[132:Spt:101998.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 102002[132:Res:102000.0,61.1] always3(s42) || -> . % 76.04/76.30 102003[132:SSi:102002.0,78254.0,78258.0,78620.0,101845.0,101993.0] || -> . % 76.04/76.30 102004[132:Spt:102003.0,101998.0,102000.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.30 102005[132:Spt:102003.0,101998.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 102009[132:Res:102005.0,61.1] always3(s43) || -> . % 76.04/76.30 102010[132:SSi:102009.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.30 102011[130:Spt:102010.0,101844.0,101845.0] || until2p7(s42)*+ -> . % 76.04/76.30 102012[130:Spt:102010.0,101844.1] || -> node4(s41)*. % 76.04/76.30 102014[130:MRR:795.0,102012.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.30 102017[130:Res:53.1,102014.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.30 102022[131:Spt:102017.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 102024[131:Res:102022.0,61.1] always3(s41) || -> . % 76.04/76.30 102025[131:SSi:102024.0,78250.0,78253.0,78619.0,101843.0,102012.0] || -> . % 76.04/76.30 102026[131:Spt:102025.0,102017.0,102022.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.30 102027[131:Spt:102025.0,102017.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 102031[131:Res:102027.0,61.1] always3(s42) || -> . % 76.04/76.30 102032[131:SSi:102031.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.30 102033[129:Spt:102032.0,101842.0,101843.0] || until2p7(s41)*+ -> . % 76.04/76.30 102034[129:Spt:102032.0,101842.1] || -> node4(s40)*. % 76.04/76.30 102036[129:MRR:798.0,102034.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.30 102039[129:Res:53.1,102036.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.30 102041[130:Spt:102039.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 102043[130:Res:102041.0,61.1] always3(s40) || -> . % 76.04/76.30 102044[130:SSi:102043.0,78245.0,78249.0,78618.0,101841.0,102034.0] || -> . % 76.04/76.30 102045[130:Spt:102044.0,102039.0,102041.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.30 102046[130:Spt:102044.0,102039.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 102050[130:Res:102046.0,61.1] always3(s41) || -> . % 76.04/76.30 102051[130:SSi:102050.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.30 102052[128:Spt:102051.0,101840.0,101841.0] || until2p7(s40)*+ -> . % 76.04/76.30 102053[128:Spt:102051.0,101840.1] || -> node4(s39)*. % 76.04/76.30 102055[128:MRR:801.0,102053.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.30 102058[128:Res:53.1,102055.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.30 102060[129:Spt:102058.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 102062[129:Res:102060.0,61.1] always3(s39) || -> . % 76.04/76.30 102063[129:SSi:102062.0,78241.0,78244.0,78617.0,101839.0,102053.0] || -> . % 76.04/76.30 102064[129:Spt:102063.0,102058.0,102060.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.30 102065[129:Spt:102063.0,102058.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 102069[129:Res:102065.0,61.1] always3(s40) || -> . % 76.04/76.30 102070[129:SSi:102069.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.30 102071[127:Spt:102070.0,101838.0,101839.0] || until2p7(s39)*+ -> . % 76.04/76.30 102072[127:Spt:102070.0,101838.1] || -> node4(s38)*. % 76.04/76.30 102074[127:MRR:804.0,102072.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.30 102077[127:Res:53.1,102074.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.30 102079[128:Spt:102077.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 102081[128:Res:102079.0,61.1] always3(s38) || -> . % 76.04/76.30 102082[128:SSi:102081.0,78236.0,78240.0,78616.0,101837.0,102072.0] || -> . % 76.04/76.30 102083[128:Spt:102082.0,102077.0,102079.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.30 102084[128:Spt:102082.0,102077.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 102088[128:Res:102084.0,61.1] always3(s39) || -> . % 76.04/76.30 102089[128:SSi:102088.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.30 102090[126:Spt:102089.0,101836.0,101837.0] || until2p7(s38)*+ -> . % 76.04/76.30 102091[126:Spt:102089.0,101836.1] || -> node4(s37)*. % 76.04/76.30 102093[126:MRR:807.0,102091.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.30 102096[126:Res:53.1,102093.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.30 102101[127:Spt:102096.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 102103[127:Res:102101.0,61.1] always3(s37) || -> . % 76.04/76.30 102104[127:SSi:102103.0,78232.0,78235.0,78615.0,101835.0,102091.0] || -> . % 76.04/76.30 102105[127:Spt:102104.0,102096.0,102101.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.30 102106[127:Spt:102104.0,102096.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 102110[127:Res:102106.0,61.1] always3(s38) || -> . % 76.04/76.30 102111[127:SSi:102110.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.30 102112[125:Spt:102111.0,101834.0,101835.0] || until2p7(s37)*+ -> . % 76.04/76.30 102113[125:Spt:102111.0,101834.1] || -> node4(s36)*. % 76.04/76.30 102115[125:MRR:810.0,102113.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.30 102118[125:Res:53.1,102115.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.30 102120[126:Spt:102118.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 102122[126:Res:102120.0,61.1] always3(s36) || -> . % 76.04/76.30 102123[126:SSi:102122.0,78227.0,78231.0,78614.0,101833.0,102113.0] || -> . % 76.04/76.30 102124[126:Spt:102123.0,102118.0,102120.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.30 102125[126:Spt:102123.0,102118.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 102129[126:Res:102125.0,61.1] always3(s37) || -> . % 76.04/76.30 102130[126:SSi:102129.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.30 102131[124:Spt:102130.0,101832.0,101833.0] || until2p7(s36)*+ -> . % 76.04/76.30 102132[124:Spt:102130.0,101832.1] || -> node4(s35)*. % 76.04/76.30 102134[124:MRR:813.0,102132.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.30 102137[124:Res:53.1,102134.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.30 102139[125:Spt:102137.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 102141[125:Res:102139.0,61.1] always3(s35) || -> . % 76.04/76.30 102142[125:SSi:102141.0,78223.0,78226.0,78613.0,101831.0,102132.0] || -> . % 76.04/76.30 102143[125:Spt:102142.0,102137.0,102139.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.30 102144[125:Spt:102142.0,102137.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 102148[125:Res:102144.0,61.1] always3(s36) || -> . % 76.04/76.30 102149[125:SSi:102148.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.30 102150[123:Spt:102149.0,101830.0,101831.0] || until2p7(s35)*+ -> . % 76.04/76.30 102151[123:Spt:102149.0,101830.1] || -> node4(s34)*. % 76.04/76.30 102153[123:MRR:816.0,102151.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.30 102156[123:Res:53.1,102153.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.30 102158[124:Spt:102156.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 102160[124:Res:102158.0,61.1] always3(s34) || -> . % 76.04/76.30 102161[124:SSi:102160.0,78218.0,78222.0,78612.0,101829.0,102151.0] || -> . % 76.04/76.30 102162[124:Spt:102161.0,102156.0,102158.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.30 102163[124:Spt:102161.0,102156.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 102167[124:Res:102163.0,61.1] always3(s35) || -> . % 76.04/76.30 102168[124:SSi:102167.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.30 102169[122:Spt:102168.0,101828.0,101829.0] || until2p7(s34)*+ -> . % 76.04/76.30 102170[122:Spt:102168.0,101828.1] || -> node4(s33)*. % 76.04/76.30 102172[122:MRR:819.0,102170.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.30 102175[122:Res:53.1,102172.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.30 102180[123:Spt:102175.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 102182[123:Res:102180.0,61.1] always3(s33) || -> . % 76.04/76.30 102183[123:SSi:102182.0,78214.0,78217.0,78611.0,101827.0,102170.0] || -> . % 76.04/76.30 102184[123:Spt:102183.0,102175.0,102180.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.30 102185[123:Spt:102183.0,102175.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 102189[123:Res:102185.0,61.1] always3(s34) || -> . % 76.04/76.30 102190[123:SSi:102189.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.30 102191[121:Spt:102190.0,101826.0,101827.0] || until2p7(s33)*+ -> . % 76.04/76.30 102192[121:Spt:102190.0,101826.1] || -> node4(s32)*. % 76.04/76.30 102194[121:MRR:822.0,102192.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.30 102197[121:Res:53.1,102194.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.30 102199[122:Spt:102197.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 102201[122:Res:102199.0,61.1] always3(s32) || -> . % 76.04/76.30 102202[122:SSi:102201.0,78209.0,78213.0,78610.0,101825.0,102192.0] || -> . % 76.04/76.30 102203[122:Spt:102202.0,102197.0,102199.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.30 102204[122:Spt:102202.0,102197.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 102208[122:Res:102204.0,61.1] always3(s33) || -> . % 76.04/76.30 102209[122:SSi:102208.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.30 102210[120:Spt:102209.0,101824.0,101825.0] || until2p7(s32)*+ -> . % 76.04/76.30 102211[120:Spt:102209.0,101824.1] || -> node4(s31)*. % 76.04/76.30 102213[120:MRR:825.0,102211.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.30 102216[120:Res:53.1,102213.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.30 102218[121:Spt:102216.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 102220[121:Res:102218.0,61.1] always3(s31) || -> . % 76.04/76.30 102221[121:SSi:102220.0,78205.0,78208.0,78609.0,101823.0,102211.0] || -> . % 76.04/76.30 102222[121:Spt:102221.0,102216.0,102218.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.30 102223[121:Spt:102221.0,102216.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 102227[121:Res:102223.0,61.1] always3(s32) || -> . % 76.04/76.30 102228[121:SSi:102227.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.30 102229[119:Spt:102228.0,101822.0,101823.0] || until2p7(s31)*+ -> . % 76.04/76.30 102230[119:Spt:102228.0,101822.1] || -> node4(s30)*. % 76.04/76.30 102232[119:MRR:828.0,102230.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.30 102235[119:Res:53.1,102232.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.30 102237[120:Spt:102235.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 102239[120:Res:102237.0,61.1] always3(s30) || -> . % 76.04/76.30 102240[120:SSi:102239.0,78200.0,78204.0,78608.0,101821.0,102230.0] || -> . % 76.04/76.30 102241[120:Spt:102240.0,102235.0,102237.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.30 102242[120:Spt:102240.0,102235.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 102246[120:Res:102242.0,61.1] always3(s31) || -> . % 76.04/76.30 102247[120:SSi:102246.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.30 102248[118:Spt:102247.0,101820.0,101821.0] || until2p7(s30)*+ -> . % 76.04/76.30 102249[118:Spt:102247.0,101820.1] || -> node4(s29)*. % 76.04/76.30 102251[118:MRR:831.0,102249.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.30 102254[118:Res:53.1,102251.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.30 102259[119:Spt:102254.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 102261[119:Res:102259.0,61.1] always3(s29) || -> . % 76.04/76.30 102262[119:SSi:102261.0,78196.0,78199.0,78607.0,101819.0,102249.0] || -> . % 76.04/76.30 102263[119:Spt:102262.0,102254.0,102259.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.30 102264[119:Spt:102262.0,102254.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 102268[119:Res:102264.0,61.1] always3(s30) || -> . % 76.04/76.30 102269[119:SSi:102268.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.30 102270[117:Spt:102269.0,101818.0,101819.0] || until2p7(s29)*+ -> . % 76.04/76.30 102271[117:Spt:102269.0,101818.1] || -> node4(s28)*. % 76.04/76.30 102273[117:MRR:834.0,102271.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.30 102276[117:Res:53.1,102273.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.30 102278[118:Spt:102276.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 102280[118:Res:102278.0,61.1] always3(s28) || -> . % 76.04/76.30 102281[118:SSi:102280.0,78191.0,78195.0,78606.0,101817.0,102271.0] || -> . % 76.04/76.30 102282[118:Spt:102281.0,102276.0,102278.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.30 102283[118:Spt:102281.0,102276.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 102287[118:Res:102283.0,61.1] always3(s29) || -> . % 76.04/76.30 102288[118:SSi:102287.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.30 102289[116:Spt:102288.0,101816.0,101817.0] || until2p7(s28)*+ -> . % 76.04/76.30 102290[116:Spt:102288.0,101816.1] || -> node4(s27)*. % 76.04/76.30 102292[116:MRR:837.0,102290.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.30 102295[116:Res:53.1,102292.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.30 102297[117:Spt:102295.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 102299[117:Res:102297.0,61.1] always3(s27) || -> . % 76.04/76.30 102300[117:SSi:102299.0,78187.0,78190.0,78605.0,101815.0,102290.0] || -> . % 76.04/76.30 102301[117:Spt:102300.0,102295.0,102297.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.30 102302[117:Spt:102300.0,102295.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 102306[117:Res:102302.0,61.1] always3(s28) || -> . % 76.04/76.30 102307[117:SSi:102306.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.30 102308[115:Spt:102307.0,101814.0,101815.0] || until2p7(s27)*+ -> . % 76.04/76.30 102309[115:Spt:102307.0,101814.1] || -> node4(s26)*. % 76.04/76.30 102311[115:MRR:840.0,102309.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.30 102314[115:Res:53.1,102311.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.30 102316[116:Spt:102314.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 102318[116:Res:102316.0,61.1] always3(s26) || -> . % 76.04/76.30 102319[116:SSi:102318.0,78182.0,78186.0,78604.0,101813.0,102309.0] || -> . % 76.04/76.30 102320[116:Spt:102319.0,102314.0,102316.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.30 102321[116:Spt:102319.0,102314.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 102325[116:Res:102321.0,61.1] always3(s27) || -> . % 76.04/76.30 102326[116:SSi:102325.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.30 102327[114:Spt:102326.0,101812.0,101813.0] || until2p7(s26)*+ -> . % 76.04/76.30 102328[114:Spt:102326.0,101812.1] || -> node4(s25)*. % 76.04/76.30 102330[114:MRR:843.0,102328.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.30 102333[114:Res:53.1,102330.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.30 102338[115:Spt:102333.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 102340[115:Res:102338.0,61.1] always3(s25) || -> . % 76.04/76.30 102341[115:SSi:102340.0,78178.0,78181.0,78603.0,101811.0,102328.0] || -> . % 76.04/76.30 102342[115:Spt:102341.0,102333.0,102338.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.30 102343[115:Spt:102341.0,102333.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 102347[115:Res:102343.0,61.1] always3(s26) || -> . % 76.04/76.30 102348[115:SSi:102347.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.30 102349[113:Spt:102348.0,101810.0,101811.0] || until2p7(s25)*+ -> . % 76.04/76.30 102350[113:Spt:102348.0,101810.1] || -> node4(s24)*. % 76.04/76.30 102352[113:MRR:846.0,102350.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.30 102355[113:Res:53.1,102352.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.30 102357[114:Spt:102355.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 102359[114:Res:102357.0,61.1] always3(s24) || -> . % 76.04/76.30 102360[114:SSi:102359.0,78173.0,78177.0,78602.0,101809.0,102350.0] || -> . % 76.04/76.30 102361[114:Spt:102360.0,102355.0,102357.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.30 102362[114:Spt:102360.0,102355.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 102366[114:Res:102362.0,61.1] always3(s25) || -> . % 76.04/76.30 102367[114:SSi:102366.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.30 102368[112:Spt:102367.0,101808.0,101809.0] || until2p7(s24)*+ -> . % 76.04/76.30 102369[112:Spt:102367.0,101808.1] || -> node4(s23)*. % 76.04/76.30 102371[112:MRR:849.0,102369.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.30 102374[112:Res:53.1,102371.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.30 102376[113:Spt:102374.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 102378[113:Res:102376.0,61.1] always3(s23) || -> . % 76.04/76.30 102379[113:SSi:102378.0,78169.0,78172.0,78601.0,101807.0,102369.0] || -> . % 76.04/76.30 102380[113:Spt:102379.0,102374.0,102376.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.30 102381[113:Spt:102379.0,102374.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 102385[113:Res:102381.0,61.1] always3(s24) || -> . % 76.04/76.30 102386[113:SSi:102385.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.30 102387[111:Spt:102386.0,101806.0,101807.0] || until2p7(s23)*+ -> . % 76.04/76.30 102388[111:Spt:102386.0,101806.1] || -> node4(s22)*. % 76.04/76.30 102390[111:MRR:852.0,102388.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.30 102393[111:Res:53.1,102390.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.30 102395[112:Spt:102393.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 102397[112:Res:102395.0,61.1] always3(s22) || -> . % 76.04/76.30 102398[112:SSi:102397.0,78164.0,78168.0,78600.0,101805.0,102388.0] || -> . % 76.04/76.30 102399[112:Spt:102398.0,102393.0,102395.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.30 102400[112:Spt:102398.0,102393.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 102404[112:Res:102400.0,61.1] always3(s23) || -> . % 76.04/76.30 102405[112:SSi:102404.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.30 102406[110:Spt:102405.0,101804.0,101805.0] || until2p7(s22)*+ -> . % 76.04/76.30 102407[110:Spt:102405.0,101804.1] || -> node4(s21)*. % 76.04/76.30 102409[110:MRR:855.0,102407.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.30 102412[110:Res:53.1,102409.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.30 102417[111:Spt:102412.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 102419[111:Res:102417.0,61.1] always3(s21) || -> . % 76.04/76.30 102420[111:SSi:102419.0,78160.0,78163.0,78599.0,101803.0,102407.0] || -> . % 76.04/76.30 102421[111:Spt:102420.0,102412.0,102417.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.30 102422[111:Spt:102420.0,102412.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 102426[111:Res:102422.0,61.1] always3(s22) || -> . % 76.04/76.30 102427[111:SSi:102426.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.30 102428[109:Spt:102427.0,101802.0,101803.0] || until2p7(s21)*+ -> . % 76.04/76.30 102429[109:Spt:102427.0,101802.1] || -> node4(s20)*. % 76.04/76.30 102431[109:MRR:858.0,102429.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.30 102434[109:Res:53.1,102431.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.30 102436[110:Spt:102434.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 102438[110:Res:102436.0,61.1] always3(s20) || -> . % 76.04/76.30 102439[110:SSi:102438.0,78155.0,78159.0,78598.0,101801.0,102429.0] || -> . % 76.04/76.30 102440[110:Spt:102439.0,102434.0,102436.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.30 102441[110:Spt:102439.0,102434.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 102445[110:Res:102441.0,61.1] always3(s21) || -> . % 76.04/76.30 102446[110:SSi:102445.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.30 102447[108:Spt:102446.0,101800.0,101801.0] || until2p7(s20)*+ -> . % 76.04/76.30 102448[108:Spt:102446.0,101800.1] || -> node4(s19)*. % 76.04/76.30 102450[108:MRR:861.0,102448.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.30 102453[108:Res:53.1,102450.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.30 102455[109:Spt:102453.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 102457[109:Res:102455.0,61.1] always3(s19) || -> . % 76.04/76.30 102458[109:SSi:102457.0,78151.0,78154.0,78597.0,101799.0,102448.0] || -> . % 76.04/76.30 102459[109:Spt:102458.0,102453.0,102455.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.30 102460[109:Spt:102458.0,102453.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 102464[109:Res:102460.0,61.1] always3(s20) || -> . % 76.04/76.30 102465[109:SSi:102464.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.30 102466[107:Spt:102465.0,101798.0,101799.0] || until2p7(s19)*+ -> . % 76.04/76.30 102467[107:Spt:102465.0,101798.1] || -> node4(s18)*. % 76.04/76.30 102469[107:MRR:864.0,102467.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.30 102472[107:Res:53.1,102469.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.30 102474[108:Spt:102472.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 102476[108:Res:102474.0,61.1] always3(s18) || -> . % 76.04/76.30 102477[108:SSi:102476.0,78146.0,78150.0,78596.0,101797.0,102467.0] || -> . % 76.04/76.30 102478[108:Spt:102477.0,102472.0,102474.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.30 102479[108:Spt:102477.0,102472.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 102483[108:Res:102479.0,61.1] always3(s19) || -> . % 76.04/76.30 102484[108:SSi:102483.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.30 102485[106:Spt:102484.0,101796.0,101797.0] || until2p7(s18)*+ -> . % 76.04/76.30 102486[106:Spt:102484.0,101796.1] || -> node4(s17)*. % 76.04/76.30 102488[106:MRR:867.0,102486.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.30 102491[106:Res:53.1,102488.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.30 102496[107:Spt:102491.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 102498[107:Res:102496.0,61.1] always3(s17) || -> . % 76.04/76.30 102499[107:SSi:102498.0,78142.0,78145.0,78595.0,101795.0,102486.0] || -> . % 76.04/76.30 102500[107:Spt:102499.0,102491.0,102496.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.30 102501[107:Spt:102499.0,102491.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 102505[107:Res:102501.0,61.1] always3(s18) || -> . % 76.04/76.30 102506[107:SSi:102505.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.30 102507[105:Spt:102506.0,101794.0,101795.0] || until2p7(s17)*+ -> . % 76.04/76.30 102508[105:Spt:102506.0,101794.1] || -> node4(s16)*. % 76.04/76.30 102510[105:MRR:870.0,102508.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.30 102513[105:Res:53.1,102510.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.30 102515[106:Spt:102513.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 102517[106:Res:102515.0,61.1] always3(s16) || -> . % 76.04/76.30 102518[106:SSi:102517.0,78137.0,78141.0,78594.0,101793.0,102508.0] || -> . % 76.04/76.30 102519[106:Spt:102518.0,102513.0,102515.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.30 102520[106:Spt:102518.0,102513.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 102524[106:Res:102520.0,61.1] always3(s17) || -> . % 76.04/76.30 102525[106:SSi:102524.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.30 102526[104:Spt:102525.0,101792.0,101793.0] || until2p7(s16)*+ -> . % 76.04/76.30 102527[104:Spt:102525.0,101792.1] || -> node4(s15)*. % 76.04/76.30 102529[104:MRR:873.0,102527.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.30 102532[104:Res:53.1,102529.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.30 102534[105:Spt:102532.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 102536[105:Res:102534.0,61.1] always3(s15) || -> . % 76.04/76.30 102537[105:SSi:102536.0,78133.0,78136.0,78593.0,101791.0,102527.0] || -> . % 76.04/76.30 102538[105:Spt:102537.0,102532.0,102534.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.30 102539[105:Spt:102537.0,102532.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 102543[105:Res:102539.0,61.1] always3(s16) || -> . % 76.04/76.30 102544[105:SSi:102543.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.30 102545[103:Spt:102544.0,101790.0,101791.0] || until2p7(s15)*+ -> . % 76.04/76.30 102546[103:Spt:102544.0,101790.1] || -> node4(s14)*. % 76.04/76.30 102548[103:MRR:876.0,102546.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.30 102551[103:Res:53.1,102548.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.30 102553[104:Spt:102551.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 102555[104:Res:102553.0,61.1] always3(s14) || -> . % 76.04/76.30 102556[104:SSi:102555.0,78128.0,78132.0,78592.0,101789.0,102546.0] || -> . % 76.04/76.30 102557[104:Spt:102556.0,102551.0,102553.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.30 102558[104:Spt:102556.0,102551.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 102562[104:Res:102558.0,61.1] always3(s15) || -> . % 76.04/76.30 102563[104:SSi:102562.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.30 102564[102:Spt:102563.0,101788.0,101789.0] || until2p7(s14)*+ -> . % 76.04/76.30 102565[102:Spt:102563.0,101788.1] || -> node4(s13)*. % 76.04/76.30 102567[102:MRR:879.0,102565.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.30 102570[102:Res:53.1,102567.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.30 102575[103:Spt:102570.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 102577[103:Res:102575.0,61.1] always3(s13) || -> . % 76.04/76.30 102578[103:SSi:102577.0,78124.0,78127.0,78591.0,101787.0,102565.0] || -> . % 76.04/76.30 102579[103:Spt:102578.0,102570.0,102575.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.30 102580[103:Spt:102578.0,102570.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 102584[103:Res:102580.0,61.1] always3(s14) || -> . % 76.04/76.30 102585[103:SSi:102584.0,78128.0,78132.0,78592.0] || -> . % 76.04/76.30 102586[101:Spt:102585.0,101786.0,101787.0] || until2p7(s13)*+ -> . % 76.04/76.30 102587[101:Spt:102585.0,101786.1] || -> node4(s12)*. % 76.04/76.30 102589[101:MRR:882.0,102587.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.30 102592[101:Res:53.1,102589.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.30 102594[102:Spt:102592.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 102596[102:Res:102594.0,61.1] always3(s12) || -> . % 76.04/76.30 102597[102:SSi:102596.0,78119.0,78123.0,78590.0,101785.0,102587.0] || -> . % 76.04/76.30 102598[102:Spt:102597.0,102592.0,102594.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.30 102599[102:Spt:102597.0,102592.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 102603[102:Res:102599.0,61.1] always3(s13) || -> . % 76.04/76.30 102604[102:SSi:102603.0,78124.0,78127.0,78591.0] || -> . % 76.04/76.30 102605[100:Spt:102604.0,101784.0,101785.0] || until2p7(s12)*+ -> . % 76.04/76.30 102606[100:Spt:102604.0,101784.1] || -> node4(s11)*. % 76.04/76.30 102608[100:MRR:885.0,102606.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.30 102611[100:Res:53.1,102608.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.30 102613[101:Spt:102611.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 102615[101:Res:102613.0,61.1] always3(s11) || -> . % 76.04/76.30 102616[101:SSi:102615.0,78115.0,78118.0,78589.0,101783.0,102606.0] || -> . % 76.04/76.30 102617[101:Spt:102616.0,102611.0,102613.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.30 102618[101:Spt:102616.0,102611.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 102622[101:Res:102618.0,61.1] always3(s12) || -> . % 76.04/76.30 102623[101:SSi:102622.0,78119.0,78123.0,78590.0] || -> . % 76.04/76.30 102624[99:Spt:102623.0,101782.0,101783.0] || until2p7(s11)*+ -> . % 76.04/76.30 102625[99:Spt:102623.0,101782.1] || -> node4(s10)*. % 76.04/76.30 102627[99:MRR:888.0,102625.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.30 102630[99:Res:53.1,102627.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.30 102632[100:Spt:102630.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 102634[100:Res:102632.0,61.1] always3(s10) || -> . % 76.04/76.30 102635[100:SSi:102634.0,78110.0,78114.0,78588.0,101781.0,102625.0] || -> . % 76.04/76.30 102636[100:Spt:102635.0,102630.0,102632.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.30 102637[100:Spt:102635.0,102630.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 102641[100:Res:102637.0,61.1] always3(s11) || -> . % 76.04/76.30 102642[100:SSi:102641.0,78115.0,78118.0,78589.0] || -> . % 76.04/76.30 102643[98:Spt:102642.0,101780.0,101781.0] || until2p7(s10)*+ -> . % 76.04/76.30 102644[98:Spt:102642.0,101780.1] || -> node4(s9)*. % 76.04/76.30 102646[98:MRR:891.0,102644.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.30 102649[98:Res:53.1,102646.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.30 102654[99:Spt:102649.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 102656[99:Res:102654.0,61.1] always3(s9) || -> . % 76.04/76.30 102657[99:SSi:102656.0,78106.0,78109.0,78587.0,101779.0,102644.0] || -> . % 76.04/76.30 102658[99:Spt:102657.0,102649.0,102654.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.30 102659[99:Spt:102657.0,102649.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 102663[99:Res:102659.0,61.1] always3(s10) || -> . % 76.04/76.30 102664[99:SSi:102663.0,78110.0,78114.0,78588.0] || -> . % 76.04/76.30 102665[97:Spt:102664.0,101778.0,101779.0] || until2p7(s9)*+ -> . % 76.04/76.30 102666[97:Spt:102664.0,101778.1] || -> node4(s8)*. % 76.04/76.30 102668[97:MRR:894.0,102666.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.30 102671[97:Res:53.1,102668.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.30 102673[98:Spt:102671.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 102675[98:Res:102673.0,61.1] always3(s8) || -> . % 76.04/76.30 102676[98:SSi:102675.0,78101.0,78105.0,78586.0,101777.0,102666.0] || -> . % 76.04/76.30 102677[98:Spt:102676.0,102671.0,102673.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.30 102678[98:Spt:102676.0,102671.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 102682[98:Res:102678.0,61.1] always3(s9) || -> . % 76.04/76.30 102683[98:SSi:102682.0,78106.0,78109.0,78587.0] || -> . % 76.04/76.30 102684[96:Spt:102683.0,101776.0,101777.0] || until2p7(s8)*+ -> . % 76.04/76.30 102685[96:Spt:102683.0,101776.1] || -> node4(s7)*. % 76.04/76.30 102687[96:MRR:897.0,102685.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.30 102690[96:Res:53.1,102687.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.30 102692[96:MRR:102690.0,101766.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 102694[96:Res:102692.0,61.1] always3(s8) || -> . % 76.04/76.30 102695[96:SSi:102694.0,78101.0,78105.0,78586.0] || -> . % 76.04/76.30 102696[94:Spt:102695.0,101609.0,101612.0] || trans(s49,s7)*+ -> . % 76.04/76.30 102697[94:Spt:102695.0,101609.1,101609.2,101609.3,101609.4,101609.5] || -> trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.30 102699[94:MRR:101611.1,102696.0] xuntil6(s49) || -> trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.30 102700[95:Spt:102697.0] || -> trans(s49,s6)*. % 76.04/76.30 102701[95:Res:102700.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s6)*. % 76.04/76.30 102703[95:Res:102700.0,60.0] || -> node2(s49,s6)*. % 76.04/76.30 102704[95:SSi:102701.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s6)*. % 76.04/76.30 102705[95:Res:102703.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)*. % 76.04/76.30 102847[95:SoR:102705.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)*. % 76.04/76.30 102849[95:SoR:102847.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)* xuntil6(s49). % 76.04/76.30 102850[95:SSi:102849.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s6,c_busy)* xuntil6(s49). % 76.04/76.30 102851[96:Spt:102850.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.30 102853[96:Res:102851.0,61.1] always3(s6) || -> . % 76.04/76.30 102854[96:SSi:102853.0,78093.0,78096.0,78584.0] || -> . % 76.04/76.30 102855[96:Spt:102854.0,102850.1,102851.0] || m_main_v_state(s6,c_busy)*+ -> . % 76.04/76.30 102856[96:Spt:102854.0,102850.0,102850.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 102860[96:MRR:102847.2,102855.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 102861[96:Res:53.1,102856.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 102863[96:MRR:102861.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 102864[96:MRR:102704.0,102863.0] || -> until2p7(s6)*. % 76.04/76.30 102865[96:MRR:202.0,102864.0] || -> until2p7(s7)* node4(s6). % 76.04/76.30 102866[97:Spt:102865.0] || -> until2p7(s7)*. % 76.04/76.30 102867[97:MRR:203.0,102866.0] || -> until2p7(s8)* node4(s7). % 76.04/76.30 102868[98:Spt:102867.0] || -> until2p7(s8)*. % 76.04/76.30 102869[98:MRR:204.0,102868.0] || -> until2p7(s9)* node4(s8). % 76.04/76.30 102870[99:Spt:102869.0] || -> until2p7(s9)*. % 76.04/76.30 102871[99:MRR:205.0,102870.0] || -> until2p7(s10)* node4(s9). % 76.04/76.30 102872[100:Spt:102871.0] || -> until2p7(s10)*. % 76.04/76.30 102873[100:MRR:206.0,102872.0] || -> until2p7(s11)* node4(s10). % 76.04/76.30 102874[101:Spt:102873.0] || -> until2p7(s11)*. % 76.04/76.30 102875[101:MRR:207.0,102874.0] || -> until2p7(s12)* node4(s11). % 76.04/76.30 102876[102:Spt:102875.0] || -> until2p7(s12)*. % 76.04/76.30 102877[102:MRR:208.0,102876.0] || -> until2p7(s13)* node4(s12). % 76.04/76.30 102878[103:Spt:102877.0] || -> until2p7(s13)*. % 76.04/76.30 102879[103:MRR:209.0,102878.0] || -> until2p7(s14)* node4(s13). % 76.04/76.30 102880[104:Spt:102879.0] || -> until2p7(s14)*. % 76.04/76.30 102881[104:MRR:210.0,102880.0] || -> until2p7(s15)* node4(s14). % 76.04/76.30 102882[105:Spt:102881.0] || -> until2p7(s15)*. % 76.04/76.30 102883[105:MRR:211.0,102882.0] || -> until2p7(s16)* node4(s15). % 76.04/76.30 102884[106:Spt:102883.0] || -> until2p7(s16)*. % 76.04/76.30 102885[106:MRR:212.0,102884.0] || -> until2p7(s17)* node4(s16). % 76.04/76.30 102886[107:Spt:102885.0] || -> until2p7(s17)*. % 76.04/76.30 102887[107:MRR:213.0,102886.0] || -> until2p7(s18)* node4(s17). % 76.04/76.30 102888[108:Spt:102887.0] || -> until2p7(s18)*. % 76.04/76.30 102889[108:MRR:214.0,102888.0] || -> until2p7(s19)* node4(s18). % 76.04/76.30 102890[109:Spt:102889.0] || -> until2p7(s19)*. % 76.04/76.30 102891[109:MRR:215.0,102890.0] || -> until2p7(s20)* node4(s19). % 76.04/76.30 102892[110:Spt:102891.0] || -> until2p7(s20)*. % 76.04/76.30 102893[110:MRR:216.0,102892.0] || -> until2p7(s21)* node4(s20). % 76.04/76.30 102894[111:Spt:102893.0] || -> until2p7(s21)*. % 76.04/76.30 102895[111:MRR:217.0,102894.0] || -> until2p7(s22)* node4(s21). % 76.04/76.30 102896[112:Spt:102895.0] || -> until2p7(s22)*. % 76.04/76.30 102897[112:MRR:218.0,102896.0] || -> until2p7(s23)* node4(s22). % 76.04/76.30 102898[113:Spt:102897.0] || -> until2p7(s23)*. % 76.04/76.30 102899[113:MRR:219.0,102898.0] || -> until2p7(s24)* node4(s23). % 76.04/76.30 102900[114:Spt:102899.0] || -> until2p7(s24)*. % 76.04/76.30 102901[114:MRR:220.0,102900.0] || -> until2p7(s25)* node4(s24). % 76.04/76.30 102902[115:Spt:102901.0] || -> until2p7(s25)*. % 76.04/76.30 102903[115:MRR:221.0,102902.0] || -> until2p7(s26)* node4(s25). % 76.04/76.30 102904[116:Spt:102903.0] || -> until2p7(s26)*. % 76.04/76.30 102905[116:MRR:222.0,102904.0] || -> until2p7(s27)* node4(s26). % 76.04/76.30 102906[117:Spt:102905.0] || -> until2p7(s27)*. % 76.04/76.30 102907[117:MRR:223.0,102906.0] || -> until2p7(s28)* node4(s27). % 76.04/76.30 102908[118:Spt:102907.0] || -> until2p7(s28)*. % 76.04/76.30 102909[118:MRR:224.0,102908.0] || -> until2p7(s29)* node4(s28). % 76.04/76.30 102910[119:Spt:102909.0] || -> until2p7(s29)*. % 76.04/76.30 102911[119:MRR:225.0,102910.0] || -> until2p7(s30)* node4(s29). % 76.04/76.30 102912[120:Spt:102911.0] || -> until2p7(s30)*. % 76.04/76.30 102913[120:MRR:226.0,102912.0] || -> until2p7(s31)* node4(s30). % 76.04/76.30 102914[121:Spt:102913.0] || -> until2p7(s31)*. % 76.04/76.30 102915[121:MRR:227.0,102914.0] || -> until2p7(s32)* node4(s31). % 76.04/76.30 102916[122:Spt:102915.0] || -> until2p7(s32)*. % 76.04/76.30 102917[122:MRR:228.0,102916.0] || -> until2p7(s33)* node4(s32). % 76.04/76.30 102918[123:Spt:102917.0] || -> until2p7(s33)*. % 76.04/76.30 102919[123:MRR:229.0,102918.0] || -> until2p7(s34)* node4(s33). % 76.04/76.30 102920[124:Spt:102919.0] || -> until2p7(s34)*. % 76.04/76.30 102921[124:MRR:230.0,102920.0] || -> until2p7(s35)* node4(s34). % 76.04/76.30 102922[125:Spt:102921.0] || -> until2p7(s35)*. % 76.04/76.30 102923[125:MRR:231.0,102922.0] || -> until2p7(s36)* node4(s35). % 76.04/76.30 102924[126:Spt:102923.0] || -> until2p7(s36)*. % 76.04/76.30 102925[126:MRR:232.0,102924.0] || -> until2p7(s37)* node4(s36). % 76.04/76.30 102926[127:Spt:102925.0] || -> until2p7(s37)*. % 76.04/76.30 102927[127:MRR:235.0,102926.0] || -> until2p7(s38)* node4(s37). % 76.04/76.30 102928[128:Spt:102927.0] || -> until2p7(s38)*. % 76.04/76.30 102929[128:MRR:236.0,102928.0] || -> until2p7(s39)* node4(s38). % 76.04/76.30 102930[129:Spt:102929.0] || -> until2p7(s39)*. % 76.04/76.30 102931[129:MRR:237.0,102930.0] || -> until2p7(s40)* node4(s39). % 76.04/76.30 102932[130:Spt:102931.0] || -> until2p7(s40)*. % 76.04/76.30 102933[130:MRR:238.0,102932.0] || -> until2p7(s41)* node4(s40). % 76.04/76.30 102934[131:Spt:102933.0] || -> until2p7(s41)*. % 76.04/76.30 102935[131:MRR:239.0,102934.0] || -> until2p7(s42)* node4(s41). % 76.04/76.30 102936[132:Spt:102935.0] || -> until2p7(s42)*. % 76.04/76.30 102937[132:MRR:240.0,102936.0] || -> until2p7(s43)* node4(s42). % 76.04/76.30 102938[133:Spt:102937.0] || -> until2p7(s43)*. % 76.04/76.30 102939[133:MRR:241.0,102938.0] || -> until2p7(s44)* node4(s43). % 76.04/76.30 102940[134:Spt:102939.0] || -> until2p7(s44)*. % 76.04/76.30 102941[134:MRR:539.0,102940.0] || -> until2p7(s45)* node4(s44). % 76.04/76.30 102942[135:Spt:102941.0] || -> until2p7(s45)*. % 76.04/76.30 102943[135:MRR:544.0,102942.0] || -> until2p7(s46)* node4(s45). % 76.04/76.30 102944[136:Spt:102943.0] || -> until2p7(s46)*. % 76.04/76.30 102945[136:MRR:549.0,102944.0] || -> until2p7(s47)* node4(s46). % 76.04/76.30 102946[137:Spt:102945.0] || -> until2p7(s47)*. % 76.04/76.30 102947[137:MRR:554.0,102946.0] || -> until2p7(s48)* node4(s47). % 76.04/76.30 102948[138:Spt:102947.0] || -> until2p7(s48)*. % 76.04/76.30 102949[138:MRR:559.0,102948.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 102950[139:Spt:102949.0] || -> until2p7(s49)*. % 76.04/76.30 102951[139:MRR:194.0,102950.0] || -> node4(s49)*. % 76.04/76.30 102952[139:MRR:102860.0,102951.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 102956[139:Res:53.1,102952.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 102958[139:MRR:102956.0,78381.0] || -> . % 76.04/76.30 102959[139:Spt:102958.0,102949.0,102950.0] || until2p7(s49)*+ -> . % 76.04/76.30 102960[139:Spt:102958.0,102949.1] || -> node4(s48)*. % 76.04/76.30 102961[139:MRR:78384.0,102960.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 102964[139:Res:53.1,102961.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 102967[139:Res:102964.0,61.1] always3(s48) || -> . % 76.04/76.30 102968[139:SSi:102967.0,78281.0,78387.0,78626.0,102948.0,102960.0] || -> . % 76.04/76.30 102969[138:Spt:102968.0,102947.0,102948.0] || until2p7(s48)*+ -> . % 76.04/76.30 102970[138:Spt:102968.0,102947.1] || -> node4(s47)*. % 76.04/76.30 102972[138:MRR:777.0,102970.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.30 102984[138:Res:53.1,102972.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.30 102986[139:Spt:102984.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 102988[139:Res:102986.0,61.1] always3(s47) || -> . % 76.04/76.30 102989[139:SSi:102988.0,78277.0,78280.0,78625.0,102946.0,102970.0] || -> . % 76.04/76.30 102990[139:Spt:102989.0,102984.0,102986.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.30 102991[139:Spt:102989.0,102984.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 102995[139:Res:102991.0,61.1] always3(s48) || -> . % 76.04/76.30 102996[139:SSi:102995.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.30 102997[137:Spt:102996.0,102945.0,102946.0] || until2p7(s47)*+ -> . % 76.04/76.30 102998[137:Spt:102996.0,102945.1] || -> node4(s46)*. % 76.04/76.30 103000[137:MRR:780.0,102998.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.30 103007[137:Res:53.1,103000.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.30 103012[138:Spt:103007.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 103014[138:Res:103012.0,61.1] always3(s46) || -> . % 76.04/76.30 103015[138:SSi:103014.0,78272.0,78276.0,78624.0,102944.0,102998.0] || -> . % 76.04/76.30 103016[138:Spt:103015.0,103007.0,103012.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.30 103017[138:Spt:103015.0,103007.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 103021[138:Res:103017.0,61.1] always3(s47) || -> . % 76.04/76.30 103022[138:SSi:103021.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.30 103023[136:Spt:103022.0,102943.0,102944.0] || until2p7(s46)*+ -> . % 76.04/76.30 103024[136:Spt:103022.0,102943.1] || -> node4(s45)*. % 76.04/76.30 103026[136:MRR:783.0,103024.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.30 103029[136:Res:53.1,103026.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.30 103031[137:Spt:103029.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 103033[137:Res:103031.0,61.1] always3(s45) || -> . % 76.04/76.30 103034[137:SSi:103033.0,78268.0,78271.0,78623.0,102942.0,103024.0] || -> . % 76.04/76.30 103035[137:Spt:103034.0,103029.0,103031.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.30 103036[137:Spt:103034.0,103029.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 103040[137:Res:103036.0,61.1] always3(s46) || -> . % 76.04/76.30 103041[137:SSi:103040.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.30 103042[135:Spt:103041.0,102941.0,102942.0] || until2p7(s45)*+ -> . % 76.04/76.30 103043[135:Spt:103041.0,102941.1] || -> node4(s44)*. % 76.04/76.30 103045[135:MRR:786.0,103043.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.30 103048[135:Res:53.1,103045.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.30 103050[136:Spt:103048.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 103052[136:Res:103050.0,61.1] always3(s44) || -> . % 76.04/76.30 103053[136:SSi:103052.0,78263.0,78267.0,78622.0,102940.0,103043.0] || -> . % 76.04/76.30 103054[136:Spt:103053.0,103048.0,103050.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.30 103055[136:Spt:103053.0,103048.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 103059[136:Res:103055.0,61.1] always3(s45) || -> . % 76.04/76.30 103060[136:SSi:103059.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.30 103061[134:Spt:103060.0,102939.0,102940.0] || until2p7(s44)*+ -> . % 76.04/76.30 103062[134:Spt:103060.0,102939.1] || -> node4(s43)*. % 76.04/76.30 103064[134:MRR:789.0,103062.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.30 103067[134:Res:53.1,103064.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.30 103069[135:Spt:103067.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 103071[135:Res:103069.0,61.1] always3(s43) || -> . % 76.04/76.30 103072[135:SSi:103071.0,78259.0,78262.0,78621.0,102938.0,103062.0] || -> . % 76.04/76.30 103073[135:Spt:103072.0,103067.0,103069.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.30 103074[135:Spt:103072.0,103067.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 103078[135:Res:103074.0,61.1] always3(s44) || -> . % 76.04/76.30 103079[135:SSi:103078.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.30 103080[133:Spt:103079.0,102937.0,102938.0] || until2p7(s43)*+ -> . % 76.04/76.30 103081[133:Spt:103079.0,102937.1] || -> node4(s42)*. % 76.04/76.30 103083[133:MRR:792.0,103081.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.30 103086[133:Res:53.1,103083.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.30 103091[134:Spt:103086.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 103093[134:Res:103091.0,61.1] always3(s42) || -> . % 76.04/76.30 103094[134:SSi:103093.0,78254.0,78258.0,78620.0,102936.0,103081.0] || -> . % 76.04/76.30 103095[134:Spt:103094.0,103086.0,103091.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.30 103096[134:Spt:103094.0,103086.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 103100[134:Res:103096.0,61.1] always3(s43) || -> . % 76.04/76.30 103101[134:SSi:103100.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.30 103102[132:Spt:103101.0,102935.0,102936.0] || until2p7(s42)*+ -> . % 76.04/76.30 103103[132:Spt:103101.0,102935.1] || -> node4(s41)*. % 76.04/76.30 103105[132:MRR:795.0,103103.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.30 103108[132:Res:53.1,103105.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.30 103110[133:Spt:103108.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 103112[133:Res:103110.0,61.1] always3(s41) || -> . % 76.04/76.30 103113[133:SSi:103112.0,78250.0,78253.0,78619.0,102934.0,103103.0] || -> . % 76.04/76.30 103114[133:Spt:103113.0,103108.0,103110.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.30 103115[133:Spt:103113.0,103108.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 103119[133:Res:103115.0,61.1] always3(s42) || -> . % 76.04/76.30 103120[133:SSi:103119.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.30 103121[131:Spt:103120.0,102933.0,102934.0] || until2p7(s41)*+ -> . % 76.04/76.30 103122[131:Spt:103120.0,102933.1] || -> node4(s40)*. % 76.04/76.30 103124[131:MRR:798.0,103122.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.30 103127[131:Res:53.1,103124.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.30 103129[132:Spt:103127.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 103131[132:Res:103129.0,61.1] always3(s40) || -> . % 76.04/76.30 103132[132:SSi:103131.0,78245.0,78249.0,78618.0,102932.0,103122.0] || -> . % 76.04/76.30 103133[132:Spt:103132.0,103127.0,103129.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.30 103134[132:Spt:103132.0,103127.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 103138[132:Res:103134.0,61.1] always3(s41) || -> . % 76.04/76.30 103139[132:SSi:103138.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.30 103140[130:Spt:103139.0,102931.0,102932.0] || until2p7(s40)*+ -> . % 76.04/76.30 103141[130:Spt:103139.0,102931.1] || -> node4(s39)*. % 76.04/76.30 103143[130:MRR:801.0,103141.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.30 103146[130:Res:53.1,103143.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.30 103148[131:Spt:103146.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 103150[131:Res:103148.0,61.1] always3(s39) || -> . % 76.04/76.30 103151[131:SSi:103150.0,78241.0,78244.0,78617.0,102930.0,103141.0] || -> . % 76.04/76.30 103152[131:Spt:103151.0,103146.0,103148.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.30 103153[131:Spt:103151.0,103146.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 103157[131:Res:103153.0,61.1] always3(s40) || -> . % 76.04/76.30 103158[131:SSi:103157.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.30 103159[129:Spt:103158.0,102929.0,102930.0] || until2p7(s39)*+ -> . % 76.04/76.30 103160[129:Spt:103158.0,102929.1] || -> node4(s38)*. % 76.04/76.30 103162[129:MRR:804.0,103160.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.30 103165[129:Res:53.1,103162.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.30 103170[130:Spt:103165.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 103172[130:Res:103170.0,61.1] always3(s38) || -> . % 76.04/76.30 103173[130:SSi:103172.0,78236.0,78240.0,78616.0,102928.0,103160.0] || -> . % 76.04/76.30 103174[130:Spt:103173.0,103165.0,103170.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.30 103175[130:Spt:103173.0,103165.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 103179[130:Res:103175.0,61.1] always3(s39) || -> . % 76.04/76.30 103180[130:SSi:103179.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.30 103181[128:Spt:103180.0,102927.0,102928.0] || until2p7(s38)*+ -> . % 76.04/76.30 103182[128:Spt:103180.0,102927.1] || -> node4(s37)*. % 76.04/76.30 103184[128:MRR:807.0,103182.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.30 103187[128:Res:53.1,103184.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.30 103189[129:Spt:103187.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 103191[129:Res:103189.0,61.1] always3(s37) || -> . % 76.04/76.30 103192[129:SSi:103191.0,78232.0,78235.0,78615.0,102926.0,103182.0] || -> . % 76.04/76.30 103193[129:Spt:103192.0,103187.0,103189.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.30 103194[129:Spt:103192.0,103187.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 103198[129:Res:103194.0,61.1] always3(s38) || -> . % 76.04/76.30 103199[129:SSi:103198.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.30 103200[127:Spt:103199.0,102925.0,102926.0] || until2p7(s37)*+ -> . % 76.04/76.30 103201[127:Spt:103199.0,102925.1] || -> node4(s36)*. % 76.04/76.30 103203[127:MRR:810.0,103201.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.30 103206[127:Res:53.1,103203.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.30 103208[128:Spt:103206.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 103210[128:Res:103208.0,61.1] always3(s36) || -> . % 76.04/76.30 103211[128:SSi:103210.0,78227.0,78231.0,78614.0,102924.0,103201.0] || -> . % 76.04/76.30 103212[128:Spt:103211.0,103206.0,103208.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.30 103213[128:Spt:103211.0,103206.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 103217[128:Res:103213.0,61.1] always3(s37) || -> . % 76.04/76.30 103218[128:SSi:103217.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.30 103219[126:Spt:103218.0,102923.0,102924.0] || until2p7(s36)*+ -> . % 76.04/76.30 103220[126:Spt:103218.0,102923.1] || -> node4(s35)*. % 76.04/76.30 103222[126:MRR:813.0,103220.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.30 103225[126:Res:53.1,103222.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.30 103227[127:Spt:103225.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 103229[127:Res:103227.0,61.1] always3(s35) || -> . % 76.04/76.30 103230[127:SSi:103229.0,78223.0,78226.0,78613.0,102922.0,103220.0] || -> . % 76.04/76.30 103231[127:Spt:103230.0,103225.0,103227.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.30 103232[127:Spt:103230.0,103225.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 103236[127:Res:103232.0,61.1] always3(s36) || -> . % 76.04/76.30 103237[127:SSi:103236.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.30 103238[125:Spt:103237.0,102921.0,102922.0] || until2p7(s35)*+ -> . % 76.04/76.30 103239[125:Spt:103237.0,102921.1] || -> node4(s34)*. % 76.04/76.30 103241[125:MRR:816.0,103239.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.30 103244[125:Res:53.1,103241.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.30 103249[126:Spt:103244.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 103251[126:Res:103249.0,61.1] always3(s34) || -> . % 76.04/76.30 103252[126:SSi:103251.0,78218.0,78222.0,78612.0,102920.0,103239.0] || -> . % 76.04/76.30 103253[126:Spt:103252.0,103244.0,103249.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.30 103254[126:Spt:103252.0,103244.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 103258[126:Res:103254.0,61.1] always3(s35) || -> . % 76.04/76.30 103259[126:SSi:103258.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.30 103260[124:Spt:103259.0,102919.0,102920.0] || until2p7(s34)*+ -> . % 76.04/76.30 103261[124:Spt:103259.0,102919.1] || -> node4(s33)*. % 76.04/76.30 103263[124:MRR:819.0,103261.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.30 103266[124:Res:53.1,103263.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.30 103268[125:Spt:103266.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 103270[125:Res:103268.0,61.1] always3(s33) || -> . % 76.04/76.30 103271[125:SSi:103270.0,78214.0,78217.0,78611.0,102918.0,103261.0] || -> . % 76.04/76.30 103272[125:Spt:103271.0,103266.0,103268.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.30 103273[125:Spt:103271.0,103266.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 103277[125:Res:103273.0,61.1] always3(s34) || -> . % 76.04/76.30 103278[125:SSi:103277.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.30 103279[123:Spt:103278.0,102917.0,102918.0] || until2p7(s33)*+ -> . % 76.04/76.30 103280[123:Spt:103278.0,102917.1] || -> node4(s32)*. % 76.04/76.30 103282[123:MRR:822.0,103280.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.30 103285[123:Res:53.1,103282.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.30 103287[124:Spt:103285.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 103289[124:Res:103287.0,61.1] always3(s32) || -> . % 76.04/76.30 103290[124:SSi:103289.0,78209.0,78213.0,78610.0,102916.0,103280.0] || -> . % 76.04/76.30 103291[124:Spt:103290.0,103285.0,103287.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.30 103292[124:Spt:103290.0,103285.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 103296[124:Res:103292.0,61.1] always3(s33) || -> . % 76.04/76.30 103297[124:SSi:103296.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.30 103298[122:Spt:103297.0,102915.0,102916.0] || until2p7(s32)*+ -> . % 76.04/76.30 103299[122:Spt:103297.0,102915.1] || -> node4(s31)*. % 76.04/76.30 103301[122:MRR:825.0,103299.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.30 103304[122:Res:53.1,103301.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.30 103306[123:Spt:103304.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 103308[123:Res:103306.0,61.1] always3(s31) || -> . % 76.04/76.30 103309[123:SSi:103308.0,78205.0,78208.0,78609.0,102914.0,103299.0] || -> . % 76.04/76.30 103310[123:Spt:103309.0,103304.0,103306.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.30 103311[123:Spt:103309.0,103304.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 103315[123:Res:103311.0,61.1] always3(s32) || -> . % 76.04/76.30 103316[123:SSi:103315.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.30 103317[121:Spt:103316.0,102913.0,102914.0] || until2p7(s31)*+ -> . % 76.04/76.30 103318[121:Spt:103316.0,102913.1] || -> node4(s30)*. % 76.04/76.30 103320[121:MRR:828.0,103318.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.30 103323[121:Res:53.1,103320.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.30 103328[122:Spt:103323.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 103330[122:Res:103328.0,61.1] always3(s30) || -> . % 76.04/76.30 103331[122:SSi:103330.0,78200.0,78204.0,78608.0,102912.0,103318.0] || -> . % 76.04/76.30 103332[122:Spt:103331.0,103323.0,103328.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.30 103333[122:Spt:103331.0,103323.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 103337[122:Res:103333.0,61.1] always3(s31) || -> . % 76.04/76.30 103338[122:SSi:103337.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.30 103339[120:Spt:103338.0,102911.0,102912.0] || until2p7(s30)*+ -> . % 76.04/76.30 103340[120:Spt:103338.0,102911.1] || -> node4(s29)*. % 76.04/76.30 103342[120:MRR:831.0,103340.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.30 103345[120:Res:53.1,103342.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.30 103347[121:Spt:103345.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 103349[121:Res:103347.0,61.1] always3(s29) || -> . % 76.04/76.30 103350[121:SSi:103349.0,78196.0,78199.0,78607.0,102910.0,103340.0] || -> . % 76.04/76.30 103351[121:Spt:103350.0,103345.0,103347.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.30 103352[121:Spt:103350.0,103345.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 103356[121:Res:103352.0,61.1] always3(s30) || -> . % 76.04/76.30 103357[121:SSi:103356.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.30 103358[119:Spt:103357.0,102909.0,102910.0] || until2p7(s29)*+ -> . % 76.04/76.30 103359[119:Spt:103357.0,102909.1] || -> node4(s28)*. % 76.04/76.30 103361[119:MRR:834.0,103359.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.30 103364[119:Res:53.1,103361.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.30 103366[120:Spt:103364.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 103368[120:Res:103366.0,61.1] always3(s28) || -> . % 76.04/76.30 103369[120:SSi:103368.0,78191.0,78195.0,78606.0,102908.0,103359.0] || -> . % 76.04/76.30 103370[120:Spt:103369.0,103364.0,103366.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.30 103371[120:Spt:103369.0,103364.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 103375[120:Res:103371.0,61.1] always3(s29) || -> . % 76.04/76.30 103376[120:SSi:103375.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.30 103377[118:Spt:103376.0,102907.0,102908.0] || until2p7(s28)*+ -> . % 76.04/76.30 103378[118:Spt:103376.0,102907.1] || -> node4(s27)*. % 76.04/76.30 103380[118:MRR:837.0,103378.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.30 103383[118:Res:53.1,103380.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.30 103385[119:Spt:103383.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 103387[119:Res:103385.0,61.1] always3(s27) || -> . % 76.04/76.30 103388[119:SSi:103387.0,78187.0,78190.0,78605.0,102906.0,103378.0] || -> . % 76.04/76.30 103389[119:Spt:103388.0,103383.0,103385.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.30 103390[119:Spt:103388.0,103383.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 103394[119:Res:103390.0,61.1] always3(s28) || -> . % 76.04/76.30 103395[119:SSi:103394.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.30 103396[117:Spt:103395.0,102905.0,102906.0] || until2p7(s27)*+ -> . % 76.04/76.30 103397[117:Spt:103395.0,102905.1] || -> node4(s26)*. % 76.04/76.30 103399[117:MRR:840.0,103397.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.30 103402[117:Res:53.1,103399.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.30 103407[118:Spt:103402.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 103409[118:Res:103407.0,61.1] always3(s26) || -> . % 76.04/76.30 103410[118:SSi:103409.0,78182.0,78186.0,78604.0,102904.0,103397.0] || -> . % 76.04/76.30 103411[118:Spt:103410.0,103402.0,103407.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.30 103412[118:Spt:103410.0,103402.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 103416[118:Res:103412.0,61.1] always3(s27) || -> . % 76.04/76.30 103417[118:SSi:103416.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.30 103418[116:Spt:103417.0,102903.0,102904.0] || until2p7(s26)*+ -> . % 76.04/76.30 103419[116:Spt:103417.0,102903.1] || -> node4(s25)*. % 76.04/76.30 103421[116:MRR:843.0,103419.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.30 103424[116:Res:53.1,103421.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.30 103426[117:Spt:103424.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 103428[117:Res:103426.0,61.1] always3(s25) || -> . % 76.04/76.30 103429[117:SSi:103428.0,78178.0,78181.0,78603.0,102902.0,103419.0] || -> . % 76.04/76.30 103430[117:Spt:103429.0,103424.0,103426.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.30 103431[117:Spt:103429.0,103424.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 103435[117:Res:103431.0,61.1] always3(s26) || -> . % 76.04/76.30 103436[117:SSi:103435.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.30 103437[115:Spt:103436.0,102901.0,102902.0] || until2p7(s25)*+ -> . % 76.04/76.30 103438[115:Spt:103436.0,102901.1] || -> node4(s24)*. % 76.04/76.30 103440[115:MRR:846.0,103438.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.30 103443[115:Res:53.1,103440.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.30 103445[116:Spt:103443.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 103447[116:Res:103445.0,61.1] always3(s24) || -> . % 76.04/76.30 103448[116:SSi:103447.0,78173.0,78177.0,78602.0,102900.0,103438.0] || -> . % 76.04/76.30 103449[116:Spt:103448.0,103443.0,103445.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.30 103450[116:Spt:103448.0,103443.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 103454[116:Res:103450.0,61.1] always3(s25) || -> . % 76.04/76.30 103455[116:SSi:103454.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.30 103456[114:Spt:103455.0,102899.0,102900.0] || until2p7(s24)*+ -> . % 76.04/76.30 103457[114:Spt:103455.0,102899.1] || -> node4(s23)*. % 76.04/76.30 103459[114:MRR:849.0,103457.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.30 103462[114:Res:53.1,103459.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.30 103464[115:Spt:103462.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 103466[115:Res:103464.0,61.1] always3(s23) || -> . % 76.04/76.30 103467[115:SSi:103466.0,78169.0,78172.0,78601.0,102898.0,103457.0] || -> . % 76.04/76.30 103468[115:Spt:103467.0,103462.0,103464.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.30 103469[115:Spt:103467.0,103462.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 103473[115:Res:103469.0,61.1] always3(s24) || -> . % 76.04/76.30 103474[115:SSi:103473.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.30 103475[113:Spt:103474.0,102897.0,102898.0] || until2p7(s23)*+ -> . % 76.04/76.30 103476[113:Spt:103474.0,102897.1] || -> node4(s22)*. % 76.04/76.30 103478[113:MRR:852.0,103476.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.30 103481[113:Res:53.1,103478.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.30 103486[114:Spt:103481.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 103488[114:Res:103486.0,61.1] always3(s22) || -> . % 76.04/76.30 103489[114:SSi:103488.0,78164.0,78168.0,78600.0,102896.0,103476.0] || -> . % 76.04/76.30 103490[114:Spt:103489.0,103481.0,103486.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.30 103491[114:Spt:103489.0,103481.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 103495[114:Res:103491.0,61.1] always3(s23) || -> . % 76.04/76.30 103496[114:SSi:103495.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.30 103497[112:Spt:103496.0,102895.0,102896.0] || until2p7(s22)*+ -> . % 76.04/76.30 103498[112:Spt:103496.0,102895.1] || -> node4(s21)*. % 76.04/76.30 103500[112:MRR:855.0,103498.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.30 103503[112:Res:53.1,103500.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.30 103505[113:Spt:103503.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 103507[113:Res:103505.0,61.1] always3(s21) || -> . % 76.04/76.30 103508[113:SSi:103507.0,78160.0,78163.0,78599.0,102894.0,103498.0] || -> . % 76.04/76.30 103509[113:Spt:103508.0,103503.0,103505.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.30 103510[113:Spt:103508.0,103503.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 103514[113:Res:103510.0,61.1] always3(s22) || -> . % 76.04/76.30 103515[113:SSi:103514.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.30 103516[111:Spt:103515.0,102893.0,102894.0] || until2p7(s21)*+ -> . % 76.04/76.30 103517[111:Spt:103515.0,102893.1] || -> node4(s20)*. % 76.04/76.30 103519[111:MRR:858.0,103517.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.30 103522[111:Res:53.1,103519.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.30 103524[112:Spt:103522.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 103526[112:Res:103524.0,61.1] always3(s20) || -> . % 76.04/76.30 103527[112:SSi:103526.0,78155.0,78159.0,78598.0,102892.0,103517.0] || -> . % 76.04/76.30 103528[112:Spt:103527.0,103522.0,103524.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.30 103529[112:Spt:103527.0,103522.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 103533[112:Res:103529.0,61.1] always3(s21) || -> . % 76.04/76.30 103534[112:SSi:103533.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.30 103535[110:Spt:103534.0,102891.0,102892.0] || until2p7(s20)*+ -> . % 76.04/76.30 103536[110:Spt:103534.0,102891.1] || -> node4(s19)*. % 76.04/76.30 103538[110:MRR:861.0,103536.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.30 103541[110:Res:53.1,103538.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.30 103543[111:Spt:103541.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 103545[111:Res:103543.0,61.1] always3(s19) || -> . % 76.04/76.30 103546[111:SSi:103545.0,78151.0,78154.0,78597.0,102890.0,103536.0] || -> . % 76.04/76.30 103547[111:Spt:103546.0,103541.0,103543.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.30 103548[111:Spt:103546.0,103541.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 103552[111:Res:103548.0,61.1] always3(s20) || -> . % 76.04/76.30 103553[111:SSi:103552.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.30 103554[109:Spt:103553.0,102889.0,102890.0] || until2p7(s19)*+ -> . % 76.04/76.30 103555[109:Spt:103553.0,102889.1] || -> node4(s18)*. % 76.04/76.30 103557[109:MRR:864.0,103555.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.30 103560[109:Res:53.1,103557.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.30 103565[110:Spt:103560.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 103567[110:Res:103565.0,61.1] always3(s18) || -> . % 76.04/76.30 103568[110:SSi:103567.0,78146.0,78150.0,78596.0,102888.0,103555.0] || -> . % 76.04/76.30 103569[110:Spt:103568.0,103560.0,103565.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.30 103570[110:Spt:103568.0,103560.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 103574[110:Res:103570.0,61.1] always3(s19) || -> . % 76.04/76.30 103575[110:SSi:103574.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.30 103576[108:Spt:103575.0,102887.0,102888.0] || until2p7(s18)*+ -> . % 76.04/76.30 103577[108:Spt:103575.0,102887.1] || -> node4(s17)*. % 76.04/76.30 103579[108:MRR:867.0,103577.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.30 103582[108:Res:53.1,103579.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.30 103584[109:Spt:103582.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 103586[109:Res:103584.0,61.1] always3(s17) || -> . % 76.04/76.30 103587[109:SSi:103586.0,78142.0,78145.0,78595.0,102886.0,103577.0] || -> . % 76.04/76.30 103588[109:Spt:103587.0,103582.0,103584.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.30 103589[109:Spt:103587.0,103582.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 103593[109:Res:103589.0,61.1] always3(s18) || -> . % 76.04/76.30 103594[109:SSi:103593.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.30 103595[107:Spt:103594.0,102885.0,102886.0] || until2p7(s17)*+ -> . % 76.04/76.30 103596[107:Spt:103594.0,102885.1] || -> node4(s16)*. % 76.04/76.30 103598[107:MRR:870.0,103596.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.30 103601[107:Res:53.1,103598.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.30 103603[108:Spt:103601.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 103605[108:Res:103603.0,61.1] always3(s16) || -> . % 76.04/76.30 103606[108:SSi:103605.0,78137.0,78141.0,78594.0,102884.0,103596.0] || -> . % 76.04/76.30 103607[108:Spt:103606.0,103601.0,103603.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.30 103608[108:Spt:103606.0,103601.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 103612[108:Res:103608.0,61.1] always3(s17) || -> . % 76.04/76.30 103613[108:SSi:103612.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.30 103614[106:Spt:103613.0,102883.0,102884.0] || until2p7(s16)*+ -> . % 76.04/76.30 103615[106:Spt:103613.0,102883.1] || -> node4(s15)*. % 76.04/76.30 103617[106:MRR:873.0,103615.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.30 103620[106:Res:53.1,103617.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.30 103622[107:Spt:103620.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 103624[107:Res:103622.0,61.1] always3(s15) || -> . % 76.04/76.30 103625[107:SSi:103624.0,78133.0,78136.0,78593.0,102882.0,103615.0] || -> . % 76.04/76.30 103626[107:Spt:103625.0,103620.0,103622.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.30 103627[107:Spt:103625.0,103620.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 103631[107:Res:103627.0,61.1] always3(s16) || -> . % 76.04/76.30 103632[107:SSi:103631.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.30 103633[105:Spt:103632.0,102881.0,102882.0] || until2p7(s15)*+ -> . % 76.04/76.30 103634[105:Spt:103632.0,102881.1] || -> node4(s14)*. % 76.04/76.30 103636[105:MRR:876.0,103634.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.30 103639[105:Res:53.1,103636.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.30 103644[106:Spt:103639.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 103646[106:Res:103644.0,61.1] always3(s14) || -> . % 76.04/76.30 103647[106:SSi:103646.0,78128.0,78132.0,78592.0,102880.0,103634.0] || -> . % 76.04/76.30 103648[106:Spt:103647.0,103639.0,103644.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.30 103649[106:Spt:103647.0,103639.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 103653[106:Res:103649.0,61.1] always3(s15) || -> . % 76.04/76.30 103654[106:SSi:103653.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.30 103655[104:Spt:103654.0,102879.0,102880.0] || until2p7(s14)*+ -> . % 76.04/76.30 103656[104:Spt:103654.0,102879.1] || -> node4(s13)*. % 76.04/76.30 103658[104:MRR:879.0,103656.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.30 103661[104:Res:53.1,103658.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.30 103663[105:Spt:103661.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 103665[105:Res:103663.0,61.1] always3(s13) || -> . % 76.04/76.30 103666[105:SSi:103665.0,78124.0,78127.0,78591.0,102878.0,103656.0] || -> . % 76.04/76.30 103667[105:Spt:103666.0,103661.0,103663.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.30 103668[105:Spt:103666.0,103661.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 103672[105:Res:103668.0,61.1] always3(s14) || -> . % 76.04/76.30 103673[105:SSi:103672.0,78128.0,78132.0,78592.0] || -> . % 76.04/76.30 103674[103:Spt:103673.0,102877.0,102878.0] || until2p7(s13)*+ -> . % 76.04/76.30 103675[103:Spt:103673.0,102877.1] || -> node4(s12)*. % 76.04/76.30 103677[103:MRR:882.0,103675.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.30 103680[103:Res:53.1,103677.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.30 103682[104:Spt:103680.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 103684[104:Res:103682.0,61.1] always3(s12) || -> . % 76.04/76.30 103685[104:SSi:103684.0,78119.0,78123.0,78590.0,102876.0,103675.0] || -> . % 76.04/76.30 103686[104:Spt:103685.0,103680.0,103682.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.30 103687[104:Spt:103685.0,103680.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 103691[104:Res:103687.0,61.1] always3(s13) || -> . % 76.04/76.30 103692[104:SSi:103691.0,78124.0,78127.0,78591.0] || -> . % 76.04/76.30 103693[102:Spt:103692.0,102875.0,102876.0] || until2p7(s12)*+ -> . % 76.04/76.30 103694[102:Spt:103692.0,102875.1] || -> node4(s11)*. % 76.04/76.30 103696[102:MRR:885.0,103694.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.30 103699[102:Res:53.1,103696.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.30 103701[103:Spt:103699.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 103703[103:Res:103701.0,61.1] always3(s11) || -> . % 76.04/76.30 103704[103:SSi:103703.0,78115.0,78118.0,78589.0,102874.0,103694.0] || -> . % 76.04/76.30 103705[103:Spt:103704.0,103699.0,103701.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.30 103706[103:Spt:103704.0,103699.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 103710[103:Res:103706.0,61.1] always3(s12) || -> . % 76.04/76.30 103711[103:SSi:103710.0,78119.0,78123.0,78590.0] || -> . % 76.04/76.30 103712[101:Spt:103711.0,102873.0,102874.0] || until2p7(s11)*+ -> . % 76.04/76.30 103713[101:Spt:103711.0,102873.1] || -> node4(s10)*. % 76.04/76.30 103715[101:MRR:888.0,103713.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.30 103718[101:Res:53.1,103715.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.30 103723[102:Spt:103718.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 103725[102:Res:103723.0,61.1] always3(s10) || -> . % 76.04/76.30 103726[102:SSi:103725.0,78110.0,78114.0,78588.0,102872.0,103713.0] || -> . % 76.04/76.30 103727[102:Spt:103726.0,103718.0,103723.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.30 103728[102:Spt:103726.0,103718.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 103732[102:Res:103728.0,61.1] always3(s11) || -> . % 76.04/76.30 103733[102:SSi:103732.0,78115.0,78118.0,78589.0] || -> . % 76.04/76.30 103734[100:Spt:103733.0,102871.0,102872.0] || until2p7(s10)*+ -> . % 76.04/76.30 103735[100:Spt:103733.0,102871.1] || -> node4(s9)*. % 76.04/76.30 103737[100:MRR:891.0,103735.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.30 103740[100:Res:53.1,103737.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.30 103742[101:Spt:103740.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 103744[101:Res:103742.0,61.1] always3(s9) || -> . % 76.04/76.30 103745[101:SSi:103744.0,78106.0,78109.0,78587.0,102870.0,103735.0] || -> . % 76.04/76.30 103746[101:Spt:103745.0,103740.0,103742.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.30 103747[101:Spt:103745.0,103740.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 103751[101:Res:103747.0,61.1] always3(s10) || -> . % 76.04/76.30 103752[101:SSi:103751.0,78110.0,78114.0,78588.0] || -> . % 76.04/76.30 103753[99:Spt:103752.0,102869.0,102870.0] || until2p7(s9)*+ -> . % 76.04/76.30 103754[99:Spt:103752.0,102869.1] || -> node4(s8)*. % 76.04/76.30 103756[99:MRR:894.0,103754.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.30 103759[99:Res:53.1,103756.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.30 103761[100:Spt:103759.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 103763[100:Res:103761.0,61.1] always3(s8) || -> . % 76.04/76.30 103764[100:SSi:103763.0,78101.0,78105.0,78586.0,102868.0,103754.0] || -> . % 76.04/76.30 103765[100:Spt:103764.0,103759.0,103761.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.30 103766[100:Spt:103764.0,103759.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 103770[100:Res:103766.0,61.1] always3(s9) || -> . % 76.04/76.30 103771[100:SSi:103770.0,78106.0,78109.0,78587.0] || -> . % 76.04/76.30 103772[98:Spt:103771.0,102867.0,102868.0] || until2p7(s8)*+ -> . % 76.04/76.30 103773[98:Spt:103771.0,102867.1] || -> node4(s7)*. % 76.04/76.30 103775[98:MRR:897.0,103773.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.30 103778[98:Res:53.1,103775.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.30 103780[99:Spt:103778.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.30 103782[99:Res:103780.0,61.1] always3(s7) || -> . % 76.04/76.30 103783[99:SSi:103782.0,78097.0,78100.0,78585.0,102866.0,103773.0] || -> . % 76.04/76.30 103784[99:Spt:103783.0,103778.0,103780.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.30 103785[99:Spt:103783.0,103778.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 103789[99:Res:103785.0,61.1] always3(s8) || -> . % 76.04/76.30 103790[99:SSi:103789.0,78101.0,78105.0,78586.0] || -> . % 76.04/76.30 103791[97:Spt:103790.0,102865.0,102866.0] || until2p7(s7)*+ -> . % 76.04/76.30 103792[97:Spt:103790.0,102865.1] || -> node4(s6)*. % 76.04/76.30 103794[97:MRR:900.0,103792.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.30 103797[97:Res:53.1,103794.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.30 103799[97:MRR:103797.0,102855.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.30 103804[97:Res:103799.0,61.1] always3(s7) || -> . % 76.04/76.30 103805[97:SSi:103804.0,78097.0,78100.0,78585.0] || -> . % 76.04/76.30 103806[95:Spt:103805.0,102697.0,102700.0] || trans(s49,s6)*+ -> . % 76.04/76.30 103807[95:Spt:103805.0,102697.1,102697.2,102697.3,102697.4] || -> trans(s49,s5) trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.30 103809[95:MRR:102699.1,103806.0] xuntil6(s49) || -> trans(s49,s5) trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.30 103810[96:Spt:103807.0] || -> trans(s49,s5)*. % 76.04/76.30 103811[96:Res:103810.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s5)*. % 76.04/76.30 103813[96:Res:103810.0,60.0] || -> node2(s49,s5)*. % 76.04/76.30 103814[96:SSi:103811.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s5)*. % 76.04/76.30 103815[96:Res:103813.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)*. % 76.04/76.30 103961[96:SoR:103815.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)*. % 76.04/76.30 103963[96:SoR:103961.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)* xuntil6(s49). % 76.04/76.30 103964[96:SSi:103963.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s5,c_busy)* xuntil6(s49). % 76.04/76.30 103965[97:Spt:103964.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.30 103967[97:Res:103965.0,61.1] always3(s5) || -> . % 76.04/76.30 103968[97:SSi:103967.0,78089.0,78092.0,78583.0] || -> . % 76.04/76.30 103969[97:Spt:103968.0,103964.1,103965.0] || m_main_v_state(s5,c_busy)*+ -> . % 76.04/76.30 103970[97:Spt:103968.0,103964.0,103964.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 103974[97:MRR:103961.2,103969.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 103975[97:Res:53.1,103970.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 103977[97:MRR:103975.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 103978[97:MRR:103814.0,103977.0] || -> until2p7(s5)*. % 76.04/76.30 103979[97:MRR:201.0,103978.0] || -> until2p7(s6)* node4(s5). % 76.04/76.30 103980[98:Spt:103979.0] || -> until2p7(s6)*. % 76.04/76.30 103981[98:MRR:202.0,103980.0] || -> until2p7(s7)* node4(s6). % 76.04/76.30 103982[99:Spt:103981.0] || -> until2p7(s7)*. % 76.04/76.30 103983[99:MRR:203.0,103982.0] || -> until2p7(s8)* node4(s7). % 76.04/76.30 103984[100:Spt:103983.0] || -> until2p7(s8)*. % 76.04/76.30 103985[100:MRR:204.0,103984.0] || -> until2p7(s9)* node4(s8). % 76.04/76.30 103986[101:Spt:103985.0] || -> until2p7(s9)*. % 76.04/76.30 103987[101:MRR:205.0,103986.0] || -> until2p7(s10)* node4(s9). % 76.04/76.30 103988[102:Spt:103987.0] || -> until2p7(s10)*. % 76.04/76.30 103989[102:MRR:206.0,103988.0] || -> until2p7(s11)* node4(s10). % 76.04/76.30 103990[103:Spt:103989.0] || -> until2p7(s11)*. % 76.04/76.30 103991[103:MRR:207.0,103990.0] || -> until2p7(s12)* node4(s11). % 76.04/76.30 103992[104:Spt:103991.0] || -> until2p7(s12)*. % 76.04/76.30 103993[104:MRR:208.0,103992.0] || -> until2p7(s13)* node4(s12). % 76.04/76.30 103994[105:Spt:103993.0] || -> until2p7(s13)*. % 76.04/76.30 103995[105:MRR:209.0,103994.0] || -> until2p7(s14)* node4(s13). % 76.04/76.30 103996[106:Spt:103995.0] || -> until2p7(s14)*. % 76.04/76.30 103997[106:MRR:210.0,103996.0] || -> until2p7(s15)* node4(s14). % 76.04/76.30 103998[107:Spt:103997.0] || -> until2p7(s15)*. % 76.04/76.30 103999[107:MRR:211.0,103998.0] || -> until2p7(s16)* node4(s15). % 76.04/76.30 104000[108:Spt:103999.0] || -> until2p7(s16)*. % 76.04/76.30 104001[108:MRR:212.0,104000.0] || -> until2p7(s17)* node4(s16). % 76.04/76.30 104002[109:Spt:104001.0] || -> until2p7(s17)*. % 76.04/76.30 104003[109:MRR:213.0,104002.0] || -> until2p7(s18)* node4(s17). % 76.04/76.30 104004[110:Spt:104003.0] || -> until2p7(s18)*. % 76.04/76.30 104005[110:MRR:214.0,104004.0] || -> until2p7(s19)* node4(s18). % 76.04/76.30 104006[111:Spt:104005.0] || -> until2p7(s19)*. % 76.04/76.30 104007[111:MRR:215.0,104006.0] || -> until2p7(s20)* node4(s19). % 76.04/76.30 104008[112:Spt:104007.0] || -> until2p7(s20)*. % 76.04/76.30 104009[112:MRR:216.0,104008.0] || -> until2p7(s21)* node4(s20). % 76.04/76.30 104010[113:Spt:104009.0] || -> until2p7(s21)*. % 76.04/76.30 104011[113:MRR:217.0,104010.0] || -> until2p7(s22)* node4(s21). % 76.04/76.30 104012[114:Spt:104011.0] || -> until2p7(s22)*. % 76.04/76.30 104013[114:MRR:218.0,104012.0] || -> until2p7(s23)* node4(s22). % 76.04/76.30 104014[115:Spt:104013.0] || -> until2p7(s23)*. % 76.04/76.30 104015[115:MRR:219.0,104014.0] || -> until2p7(s24)* node4(s23). % 76.04/76.30 104016[116:Spt:104015.0] || -> until2p7(s24)*. % 76.04/76.30 104017[116:MRR:220.0,104016.0] || -> until2p7(s25)* node4(s24). % 76.04/76.30 104018[117:Spt:104017.0] || -> until2p7(s25)*. % 76.04/76.30 104019[117:MRR:221.0,104018.0] || -> until2p7(s26)* node4(s25). % 76.04/76.30 104020[118:Spt:104019.0] || -> until2p7(s26)*. % 76.04/76.30 104021[118:MRR:222.0,104020.0] || -> until2p7(s27)* node4(s26). % 76.04/76.30 104022[119:Spt:104021.0] || -> until2p7(s27)*. % 76.04/76.30 104023[119:MRR:223.0,104022.0] || -> until2p7(s28)* node4(s27). % 76.04/76.30 104024[120:Spt:104023.0] || -> until2p7(s28)*. % 76.04/76.30 104025[120:MRR:224.0,104024.0] || -> until2p7(s29)* node4(s28). % 76.04/76.30 104026[121:Spt:104025.0] || -> until2p7(s29)*. % 76.04/76.30 104027[121:MRR:225.0,104026.0] || -> until2p7(s30)* node4(s29). % 76.04/76.30 104028[122:Spt:104027.0] || -> until2p7(s30)*. % 76.04/76.30 104029[122:MRR:226.0,104028.0] || -> until2p7(s31)* node4(s30). % 76.04/76.30 104030[123:Spt:104029.0] || -> until2p7(s31)*. % 76.04/76.30 104031[123:MRR:227.0,104030.0] || -> until2p7(s32)* node4(s31). % 76.04/76.30 104032[124:Spt:104031.0] || -> until2p7(s32)*. % 76.04/76.30 104033[124:MRR:228.0,104032.0] || -> until2p7(s33)* node4(s32). % 76.04/76.30 104034[125:Spt:104033.0] || -> until2p7(s33)*. % 76.04/76.30 104035[125:MRR:229.0,104034.0] || -> until2p7(s34)* node4(s33). % 76.04/76.30 104036[126:Spt:104035.0] || -> until2p7(s34)*. % 76.04/76.30 104037[126:MRR:230.0,104036.0] || -> until2p7(s35)* node4(s34). % 76.04/76.30 104038[127:Spt:104037.0] || -> until2p7(s35)*. % 76.04/76.30 104039[127:MRR:231.0,104038.0] || -> until2p7(s36)* node4(s35). % 76.04/76.30 104040[128:Spt:104039.0] || -> until2p7(s36)*. % 76.04/76.30 104041[128:MRR:232.0,104040.0] || -> until2p7(s37)* node4(s36). % 76.04/76.30 104042[129:Spt:104041.0] || -> until2p7(s37)*. % 76.04/76.30 104043[129:MRR:235.0,104042.0] || -> until2p7(s38)* node4(s37). % 76.04/76.30 104044[130:Spt:104043.0] || -> until2p7(s38)*. % 76.04/76.30 104045[130:MRR:236.0,104044.0] || -> until2p7(s39)* node4(s38). % 76.04/76.30 104046[131:Spt:104045.0] || -> until2p7(s39)*. % 76.04/76.30 104047[131:MRR:237.0,104046.0] || -> until2p7(s40)* node4(s39). % 76.04/76.30 104048[132:Spt:104047.0] || -> until2p7(s40)*. % 76.04/76.30 104049[132:MRR:238.0,104048.0] || -> until2p7(s41)* node4(s40). % 76.04/76.30 104050[133:Spt:104049.0] || -> until2p7(s41)*. % 76.04/76.30 104051[133:MRR:239.0,104050.0] || -> until2p7(s42)* node4(s41). % 76.04/76.30 104052[134:Spt:104051.0] || -> until2p7(s42)*. % 76.04/76.30 104053[134:MRR:240.0,104052.0] || -> until2p7(s43)* node4(s42). % 76.04/76.30 104054[135:Spt:104053.0] || -> until2p7(s43)*. % 76.04/76.30 104055[135:MRR:241.0,104054.0] || -> until2p7(s44)* node4(s43). % 76.04/76.30 104056[136:Spt:104055.0] || -> until2p7(s44)*. % 76.04/76.30 104057[136:MRR:539.0,104056.0] || -> until2p7(s45)* node4(s44). % 76.04/76.30 104058[137:Spt:104057.0] || -> until2p7(s45)*. % 76.04/76.30 104059[137:MRR:544.0,104058.0] || -> until2p7(s46)* node4(s45). % 76.04/76.30 104060[138:Spt:104059.0] || -> until2p7(s46)*. % 76.04/76.30 104061[138:MRR:549.0,104060.0] || -> until2p7(s47)* node4(s46). % 76.04/76.30 104062[139:Spt:104061.0] || -> until2p7(s47)*. % 76.04/76.30 104063[139:MRR:554.0,104062.0] || -> until2p7(s48)* node4(s47). % 76.04/76.30 104064[140:Spt:104063.0] || -> until2p7(s48)*. % 76.04/76.30 104065[140:MRR:559.0,104064.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 104066[141:Spt:104065.0] || -> until2p7(s49)*. % 76.04/76.30 104067[141:MRR:194.0,104066.0] || -> node4(s49)*. % 76.04/76.30 104068[141:MRR:103974.0,104067.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 104069[141:Res:53.1,104068.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 104071[141:MRR:104069.0,78381.0] || -> . % 76.04/76.30 104072[141:Spt:104071.0,104065.0,104066.0] || until2p7(s49)*+ -> . % 76.04/76.30 104073[141:Spt:104071.0,104065.1] || -> node4(s48)*. % 76.04/76.30 104074[141:MRR:78384.0,104073.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 104077[141:Res:53.1,104074.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 104080[141:Res:104077.0,61.1] always3(s48) || -> . % 76.04/76.30 104081[141:SSi:104080.0,78281.0,78387.0,78626.0,104064.0,104073.0] || -> . % 76.04/76.30 104082[140:Spt:104081.0,104063.0,104064.0] || until2p7(s48)*+ -> . % 76.04/76.30 104083[140:Spt:104081.0,104063.1] || -> node4(s47)*. % 76.04/76.30 104085[140:MRR:777.0,104083.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.30 104100[140:Res:53.1,104085.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.30 104102[141:Spt:104100.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 104104[141:Res:104102.0,61.1] always3(s47) || -> . % 76.04/76.30 104105[141:SSi:104104.0,78277.0,78280.0,78625.0,104062.0,104083.0] || -> . % 76.04/76.30 104106[141:Spt:104105.0,104100.0,104102.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.30 104107[141:Spt:104105.0,104100.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 104111[141:Res:104107.0,61.1] always3(s48) || -> . % 76.04/76.30 104112[141:SSi:104111.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.30 104113[139:Spt:104112.0,104061.0,104062.0] || until2p7(s47)*+ -> . % 76.04/76.30 104114[139:Spt:104112.0,104061.1] || -> node4(s46)*. % 76.04/76.30 104116[139:MRR:780.0,104114.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.30 104126[139:Res:53.1,104116.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.30 104128[140:Spt:104126.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 104130[140:Res:104128.0,61.1] always3(s46) || -> . % 76.04/76.30 104131[140:SSi:104130.0,78272.0,78276.0,78624.0,104060.0,104114.0] || -> . % 76.04/76.30 104132[140:Spt:104131.0,104126.0,104128.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.30 104133[140:Spt:104131.0,104126.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 104137[140:Res:104133.0,61.1] always3(s47) || -> . % 76.04/76.30 104138[140:SSi:104137.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.30 104139[138:Spt:104138.0,104059.0,104060.0] || until2p7(s46)*+ -> . % 76.04/76.30 104140[138:Spt:104138.0,104059.1] || -> node4(s45)*. % 76.04/76.30 104142[138:MRR:783.0,104140.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.30 104145[138:Res:53.1,104142.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.30 104147[139:Spt:104145.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 104149[139:Res:104147.0,61.1] always3(s45) || -> . % 76.04/76.30 104150[139:SSi:104149.0,78268.0,78271.0,78623.0,104058.0,104140.0] || -> . % 76.04/76.30 104151[139:Spt:104150.0,104145.0,104147.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.30 104152[139:Spt:104150.0,104145.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 104156[139:Res:104152.0,61.1] always3(s46) || -> . % 76.04/76.30 104157[139:SSi:104156.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.30 104158[137:Spt:104157.0,104057.0,104058.0] || until2p7(s45)*+ -> . % 76.04/76.30 104159[137:Spt:104157.0,104057.1] || -> node4(s44)*. % 76.04/76.30 104161[137:MRR:786.0,104159.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.30 104164[137:Res:53.1,104161.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.30 104166[138:Spt:104164.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 104168[138:Res:104166.0,61.1] always3(s44) || -> . % 76.04/76.30 104169[138:SSi:104168.0,78263.0,78267.0,78622.0,104056.0,104159.0] || -> . % 76.04/76.30 104170[138:Spt:104169.0,104164.0,104166.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.30 104171[138:Spt:104169.0,104164.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 104175[138:Res:104171.0,61.1] always3(s45) || -> . % 76.04/76.30 104176[138:SSi:104175.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.30 104177[136:Spt:104176.0,104055.0,104056.0] || until2p7(s44)*+ -> . % 76.04/76.30 104178[136:Spt:104176.0,104055.1] || -> node4(s43)*. % 76.04/76.30 104180[136:MRR:789.0,104178.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.30 104183[136:Res:53.1,104180.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.30 104188[137:Spt:104183.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 104190[137:Res:104188.0,61.1] always3(s43) || -> . % 76.04/76.30 104191[137:SSi:104190.0,78259.0,78262.0,78621.0,104054.0,104178.0] || -> . % 76.04/76.30 104192[137:Spt:104191.0,104183.0,104188.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.30 104193[137:Spt:104191.0,104183.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 104197[137:Res:104193.0,61.1] always3(s44) || -> . % 76.04/76.30 104198[137:SSi:104197.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.30 104199[135:Spt:104198.0,104053.0,104054.0] || until2p7(s43)*+ -> . % 76.04/76.30 104200[135:Spt:104198.0,104053.1] || -> node4(s42)*. % 76.04/76.30 104202[135:MRR:792.0,104200.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.30 104205[135:Res:53.1,104202.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.30 104207[136:Spt:104205.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 104209[136:Res:104207.0,61.1] always3(s42) || -> . % 76.04/76.30 104210[136:SSi:104209.0,78254.0,78258.0,78620.0,104052.0,104200.0] || -> . % 76.04/76.30 104211[136:Spt:104210.0,104205.0,104207.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.30 104212[136:Spt:104210.0,104205.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 104216[136:Res:104212.0,61.1] always3(s43) || -> . % 76.04/76.30 104217[136:SSi:104216.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.30 104218[134:Spt:104217.0,104051.0,104052.0] || until2p7(s42)*+ -> . % 76.04/76.30 104219[134:Spt:104217.0,104051.1] || -> node4(s41)*. % 76.04/76.30 104221[134:MRR:795.0,104219.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.30 104224[134:Res:53.1,104221.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.30 104226[135:Spt:104224.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 104228[135:Res:104226.0,61.1] always3(s41) || -> . % 76.04/76.30 104229[135:SSi:104228.0,78250.0,78253.0,78619.0,104050.0,104219.0] || -> . % 76.04/76.30 104230[135:Spt:104229.0,104224.0,104226.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.30 104231[135:Spt:104229.0,104224.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 104235[135:Res:104231.0,61.1] always3(s42) || -> . % 76.04/76.30 104236[135:SSi:104235.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.30 104237[133:Spt:104236.0,104049.0,104050.0] || until2p7(s41)*+ -> . % 76.04/76.30 104238[133:Spt:104236.0,104049.1] || -> node4(s40)*. % 76.04/76.30 104240[133:MRR:798.0,104238.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.30 104243[133:Res:53.1,104240.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.30 104245[134:Spt:104243.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 104247[134:Res:104245.0,61.1] always3(s40) || -> . % 76.04/76.30 104248[134:SSi:104247.0,78245.0,78249.0,78618.0,104048.0,104238.0] || -> . % 76.04/76.30 104249[134:Spt:104248.0,104243.0,104245.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.30 104250[134:Spt:104248.0,104243.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 104254[134:Res:104250.0,61.1] always3(s41) || -> . % 76.04/76.30 104255[134:SSi:104254.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.30 104256[132:Spt:104255.0,104047.0,104048.0] || until2p7(s40)*+ -> . % 76.04/76.30 104257[132:Spt:104255.0,104047.1] || -> node4(s39)*. % 76.04/76.30 104259[132:MRR:801.0,104257.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.30 104262[132:Res:53.1,104259.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.30 104267[133:Spt:104262.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 104269[133:Res:104267.0,61.1] always3(s39) || -> . % 76.04/76.30 104270[133:SSi:104269.0,78241.0,78244.0,78617.0,104046.0,104257.0] || -> . % 76.04/76.30 104271[133:Spt:104270.0,104262.0,104267.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.30 104272[133:Spt:104270.0,104262.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 104276[133:Res:104272.0,61.1] always3(s40) || -> . % 76.04/76.30 104277[133:SSi:104276.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.30 104278[131:Spt:104277.0,104045.0,104046.0] || until2p7(s39)*+ -> . % 76.04/76.30 104279[131:Spt:104277.0,104045.1] || -> node4(s38)*. % 76.04/76.30 104281[131:MRR:804.0,104279.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.30 104284[131:Res:53.1,104281.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.30 104286[132:Spt:104284.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 104288[132:Res:104286.0,61.1] always3(s38) || -> . % 76.04/76.30 104289[132:SSi:104288.0,78236.0,78240.0,78616.0,104044.0,104279.0] || -> . % 76.04/76.30 104290[132:Spt:104289.0,104284.0,104286.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.30 104291[132:Spt:104289.0,104284.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 104295[132:Res:104291.0,61.1] always3(s39) || -> . % 76.04/76.30 104296[132:SSi:104295.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.30 104297[130:Spt:104296.0,104043.0,104044.0] || until2p7(s38)*+ -> . % 76.04/76.30 104298[130:Spt:104296.0,104043.1] || -> node4(s37)*. % 76.04/76.30 104300[130:MRR:807.0,104298.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.30 104303[130:Res:53.1,104300.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.30 104305[131:Spt:104303.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 104307[131:Res:104305.0,61.1] always3(s37) || -> . % 76.04/76.30 104308[131:SSi:104307.0,78232.0,78235.0,78615.0,104042.0,104298.0] || -> . % 76.04/76.30 104309[131:Spt:104308.0,104303.0,104305.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.30 104310[131:Spt:104308.0,104303.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 104314[131:Res:104310.0,61.1] always3(s38) || -> . % 76.04/76.30 104315[131:SSi:104314.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.30 104316[129:Spt:104315.0,104041.0,104042.0] || until2p7(s37)*+ -> . % 76.04/76.30 104317[129:Spt:104315.0,104041.1] || -> node4(s36)*. % 76.04/76.30 104319[129:MRR:810.0,104317.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.30 104322[129:Res:53.1,104319.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.30 104324[130:Spt:104322.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 104326[130:Res:104324.0,61.1] always3(s36) || -> . % 76.04/76.30 104327[130:SSi:104326.0,78227.0,78231.0,78614.0,104040.0,104317.0] || -> . % 76.04/76.30 104328[130:Spt:104327.0,104322.0,104324.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.30 104329[130:Spt:104327.0,104322.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 104333[130:Res:104329.0,61.1] always3(s37) || -> . % 76.04/76.30 104334[130:SSi:104333.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.30 104335[128:Spt:104334.0,104039.0,104040.0] || until2p7(s36)*+ -> . % 76.04/76.30 104336[128:Spt:104334.0,104039.1] || -> node4(s35)*. % 76.04/76.30 104338[128:MRR:813.0,104336.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.30 104341[128:Res:53.1,104338.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.30 104346[129:Spt:104341.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 104348[129:Res:104346.0,61.1] always3(s35) || -> . % 76.04/76.30 104349[129:SSi:104348.0,78223.0,78226.0,78613.0,104038.0,104336.0] || -> . % 76.04/76.30 104350[129:Spt:104349.0,104341.0,104346.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.30 104351[129:Spt:104349.0,104341.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 104355[129:Res:104351.0,61.1] always3(s36) || -> . % 76.04/76.30 104356[129:SSi:104355.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.30 104357[127:Spt:104356.0,104037.0,104038.0] || until2p7(s35)*+ -> . % 76.04/76.30 104358[127:Spt:104356.0,104037.1] || -> node4(s34)*. % 76.04/76.30 104360[127:MRR:816.0,104358.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.30 104363[127:Res:53.1,104360.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.30 104365[128:Spt:104363.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 104367[128:Res:104365.0,61.1] always3(s34) || -> . % 76.04/76.30 104368[128:SSi:104367.0,78218.0,78222.0,78612.0,104036.0,104358.0] || -> . % 76.04/76.30 104369[128:Spt:104368.0,104363.0,104365.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.30 104370[128:Spt:104368.0,104363.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 104374[128:Res:104370.0,61.1] always3(s35) || -> . % 76.04/76.30 104375[128:SSi:104374.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.30 104376[126:Spt:104375.0,104035.0,104036.0] || until2p7(s34)*+ -> . % 76.04/76.30 104377[126:Spt:104375.0,104035.1] || -> node4(s33)*. % 76.04/76.30 104379[126:MRR:819.0,104377.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.30 104382[126:Res:53.1,104379.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.30 104384[127:Spt:104382.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 104386[127:Res:104384.0,61.1] always3(s33) || -> . % 76.04/76.30 104387[127:SSi:104386.0,78214.0,78217.0,78611.0,104034.0,104377.0] || -> . % 76.04/76.30 104388[127:Spt:104387.0,104382.0,104384.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.30 104389[127:Spt:104387.0,104382.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 104393[127:Res:104389.0,61.1] always3(s34) || -> . % 76.04/76.30 104394[127:SSi:104393.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.30 104395[125:Spt:104394.0,104033.0,104034.0] || until2p7(s33)*+ -> . % 76.04/76.30 104396[125:Spt:104394.0,104033.1] || -> node4(s32)*. % 76.04/76.30 104398[125:MRR:822.0,104396.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.30 104401[125:Res:53.1,104398.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.30 104403[126:Spt:104401.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 104405[126:Res:104403.0,61.1] always3(s32) || -> . % 76.04/76.30 104406[126:SSi:104405.0,78209.0,78213.0,78610.0,104032.0,104396.0] || -> . % 76.04/76.30 104407[126:Spt:104406.0,104401.0,104403.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.30 104408[126:Spt:104406.0,104401.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 104412[126:Res:104408.0,61.1] always3(s33) || -> . % 76.04/76.30 104413[126:SSi:104412.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.30 104414[124:Spt:104413.0,104031.0,104032.0] || until2p7(s32)*+ -> . % 76.04/76.30 104415[124:Spt:104413.0,104031.1] || -> node4(s31)*. % 76.04/76.30 104417[124:MRR:825.0,104415.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.30 104420[124:Res:53.1,104417.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.30 104425[125:Spt:104420.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 104427[125:Res:104425.0,61.1] always3(s31) || -> . % 76.04/76.30 104428[125:SSi:104427.0,78205.0,78208.0,78609.0,104030.0,104415.0] || -> . % 76.04/76.30 104429[125:Spt:104428.0,104420.0,104425.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.30 104430[125:Spt:104428.0,104420.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 104434[125:Res:104430.0,61.1] always3(s32) || -> . % 76.04/76.30 104435[125:SSi:104434.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.30 104436[123:Spt:104435.0,104029.0,104030.0] || until2p7(s31)*+ -> . % 76.04/76.30 104437[123:Spt:104435.0,104029.1] || -> node4(s30)*. % 76.04/76.30 104439[123:MRR:828.0,104437.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.30 104442[123:Res:53.1,104439.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.30 104444[124:Spt:104442.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 104446[124:Res:104444.0,61.1] always3(s30) || -> . % 76.04/76.30 104447[124:SSi:104446.0,78200.0,78204.0,78608.0,104028.0,104437.0] || -> . % 76.04/76.30 104448[124:Spt:104447.0,104442.0,104444.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.30 104449[124:Spt:104447.0,104442.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 104453[124:Res:104449.0,61.1] always3(s31) || -> . % 76.04/76.30 104454[124:SSi:104453.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.30 104455[122:Spt:104454.0,104027.0,104028.0] || until2p7(s30)*+ -> . % 76.04/76.30 104456[122:Spt:104454.0,104027.1] || -> node4(s29)*. % 76.04/76.30 104458[122:MRR:831.0,104456.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.30 104461[122:Res:53.1,104458.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.30 104463[123:Spt:104461.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 104465[123:Res:104463.0,61.1] always3(s29) || -> . % 76.04/76.30 104466[123:SSi:104465.0,78196.0,78199.0,78607.0,104026.0,104456.0] || -> . % 76.04/76.30 104467[123:Spt:104466.0,104461.0,104463.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.30 104468[123:Spt:104466.0,104461.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 104472[123:Res:104468.0,61.1] always3(s30) || -> . % 76.04/76.30 104473[123:SSi:104472.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.30 104474[121:Spt:104473.0,104025.0,104026.0] || until2p7(s29)*+ -> . % 76.04/76.30 104475[121:Spt:104473.0,104025.1] || -> node4(s28)*. % 76.04/76.30 104477[121:MRR:834.0,104475.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.30 104480[121:Res:53.1,104477.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.30 104482[122:Spt:104480.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 104484[122:Res:104482.0,61.1] always3(s28) || -> . % 76.04/76.30 104485[122:SSi:104484.0,78191.0,78195.0,78606.0,104024.0,104475.0] || -> . % 76.04/76.30 104486[122:Spt:104485.0,104480.0,104482.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.30 104487[122:Spt:104485.0,104480.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 104491[122:Res:104487.0,61.1] always3(s29) || -> . % 76.04/76.30 104492[122:SSi:104491.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.30 104493[120:Spt:104492.0,104023.0,104024.0] || until2p7(s28)*+ -> . % 76.04/76.30 104494[120:Spt:104492.0,104023.1] || -> node4(s27)*. % 76.04/76.30 104496[120:MRR:837.0,104494.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.30 104499[120:Res:53.1,104496.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.30 104504[121:Spt:104499.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 104506[121:Res:104504.0,61.1] always3(s27) || -> . % 76.04/76.30 104507[121:SSi:104506.0,78187.0,78190.0,78605.0,104022.0,104494.0] || -> . % 76.04/76.30 104508[121:Spt:104507.0,104499.0,104504.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.30 104509[121:Spt:104507.0,104499.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 104513[121:Res:104509.0,61.1] always3(s28) || -> . % 76.04/76.30 104514[121:SSi:104513.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.30 104515[119:Spt:104514.0,104021.0,104022.0] || until2p7(s27)*+ -> . % 76.04/76.30 104516[119:Spt:104514.0,104021.1] || -> node4(s26)*. % 76.04/76.30 104518[119:MRR:840.0,104516.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.30 104521[119:Res:53.1,104518.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.30 104523[120:Spt:104521.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 104525[120:Res:104523.0,61.1] always3(s26) || -> . % 76.04/76.30 104526[120:SSi:104525.0,78182.0,78186.0,78604.0,104020.0,104516.0] || -> . % 76.04/76.30 104527[120:Spt:104526.0,104521.0,104523.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.30 104528[120:Spt:104526.0,104521.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 104532[120:Res:104528.0,61.1] always3(s27) || -> . % 76.04/76.30 104533[120:SSi:104532.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.30 104534[118:Spt:104533.0,104019.0,104020.0] || until2p7(s26)*+ -> . % 76.04/76.30 104535[118:Spt:104533.0,104019.1] || -> node4(s25)*. % 76.04/76.30 104537[118:MRR:843.0,104535.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.30 104540[118:Res:53.1,104537.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.30 104542[119:Spt:104540.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 104544[119:Res:104542.0,61.1] always3(s25) || -> . % 76.04/76.30 104545[119:SSi:104544.0,78178.0,78181.0,78603.0,104018.0,104535.0] || -> . % 76.04/76.30 104546[119:Spt:104545.0,104540.0,104542.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.30 104547[119:Spt:104545.0,104540.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 104551[119:Res:104547.0,61.1] always3(s26) || -> . % 76.04/76.30 104552[119:SSi:104551.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.30 104553[117:Spt:104552.0,104017.0,104018.0] || until2p7(s25)*+ -> . % 76.04/76.30 104554[117:Spt:104552.0,104017.1] || -> node4(s24)*. % 76.04/76.30 104556[117:MRR:846.0,104554.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.30 104559[117:Res:53.1,104556.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.30 104561[118:Spt:104559.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 104563[118:Res:104561.0,61.1] always3(s24) || -> . % 76.04/76.30 104564[118:SSi:104563.0,78173.0,78177.0,78602.0,104016.0,104554.0] || -> . % 76.04/76.30 104565[118:Spt:104564.0,104559.0,104561.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.30 104566[118:Spt:104564.0,104559.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 104570[118:Res:104566.0,61.1] always3(s25) || -> . % 76.04/76.30 104571[118:SSi:104570.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.30 104572[116:Spt:104571.0,104015.0,104016.0] || until2p7(s24)*+ -> . % 76.04/76.30 104573[116:Spt:104571.0,104015.1] || -> node4(s23)*. % 76.04/76.30 104575[116:MRR:849.0,104573.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.30 104578[116:Res:53.1,104575.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.30 104583[117:Spt:104578.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 104585[117:Res:104583.0,61.1] always3(s23) || -> . % 76.04/76.30 104586[117:SSi:104585.0,78169.0,78172.0,78601.0,104014.0,104573.0] || -> . % 76.04/76.30 104587[117:Spt:104586.0,104578.0,104583.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.30 104588[117:Spt:104586.0,104578.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 104592[117:Res:104588.0,61.1] always3(s24) || -> . % 76.04/76.30 104593[117:SSi:104592.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.30 104594[115:Spt:104593.0,104013.0,104014.0] || until2p7(s23)*+ -> . % 76.04/76.30 104595[115:Spt:104593.0,104013.1] || -> node4(s22)*. % 76.04/76.30 104597[115:MRR:852.0,104595.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.30 104600[115:Res:53.1,104597.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.30 104602[116:Spt:104600.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 104604[116:Res:104602.0,61.1] always3(s22) || -> . % 76.04/76.30 104605[116:SSi:104604.0,78164.0,78168.0,78600.0,104012.0,104595.0] || -> . % 76.04/76.30 104606[116:Spt:104605.0,104600.0,104602.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.30 104607[116:Spt:104605.0,104600.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 104611[116:Res:104607.0,61.1] always3(s23) || -> . % 76.04/76.30 104612[116:SSi:104611.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.30 104613[114:Spt:104612.0,104011.0,104012.0] || until2p7(s22)*+ -> . % 76.04/76.30 104614[114:Spt:104612.0,104011.1] || -> node4(s21)*. % 76.04/76.30 104616[114:MRR:855.0,104614.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.30 104619[114:Res:53.1,104616.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.30 104621[115:Spt:104619.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 104623[115:Res:104621.0,61.1] always3(s21) || -> . % 76.04/76.30 104624[115:SSi:104623.0,78160.0,78163.0,78599.0,104010.0,104614.0] || -> . % 76.04/76.30 104625[115:Spt:104624.0,104619.0,104621.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.30 104626[115:Spt:104624.0,104619.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 104630[115:Res:104626.0,61.1] always3(s22) || -> . % 76.04/76.30 104631[115:SSi:104630.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.30 104632[113:Spt:104631.0,104009.0,104010.0] || until2p7(s21)*+ -> . % 76.04/76.30 104633[113:Spt:104631.0,104009.1] || -> node4(s20)*. % 76.04/76.30 104635[113:MRR:858.0,104633.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.30 104638[113:Res:53.1,104635.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.30 104640[114:Spt:104638.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 104642[114:Res:104640.0,61.1] always3(s20) || -> . % 76.04/76.30 104643[114:SSi:104642.0,78155.0,78159.0,78598.0,104008.0,104633.0] || -> . % 76.04/76.30 104644[114:Spt:104643.0,104638.0,104640.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.30 104645[114:Spt:104643.0,104638.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 104649[114:Res:104645.0,61.1] always3(s21) || -> . % 76.04/76.30 104650[114:SSi:104649.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.30 104651[112:Spt:104650.0,104007.0,104008.0] || until2p7(s20)*+ -> . % 76.04/76.30 104652[112:Spt:104650.0,104007.1] || -> node4(s19)*. % 76.04/76.30 104654[112:MRR:861.0,104652.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.30 104657[112:Res:53.1,104654.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.30 104662[113:Spt:104657.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 104664[113:Res:104662.0,61.1] always3(s19) || -> . % 76.04/76.30 104665[113:SSi:104664.0,78151.0,78154.0,78597.0,104006.0,104652.0] || -> . % 76.04/76.30 104666[113:Spt:104665.0,104657.0,104662.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.30 104667[113:Spt:104665.0,104657.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 104671[113:Res:104667.0,61.1] always3(s20) || -> . % 76.04/76.30 104672[113:SSi:104671.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.30 104673[111:Spt:104672.0,104005.0,104006.0] || until2p7(s19)*+ -> . % 76.04/76.30 104674[111:Spt:104672.0,104005.1] || -> node4(s18)*. % 76.04/76.30 104676[111:MRR:864.0,104674.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.30 104679[111:Res:53.1,104676.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.30 104681[112:Spt:104679.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 104683[112:Res:104681.0,61.1] always3(s18) || -> . % 76.04/76.30 104684[112:SSi:104683.0,78146.0,78150.0,78596.0,104004.0,104674.0] || -> . % 76.04/76.30 104685[112:Spt:104684.0,104679.0,104681.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.30 104686[112:Spt:104684.0,104679.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 104690[112:Res:104686.0,61.1] always3(s19) || -> . % 76.04/76.30 104691[112:SSi:104690.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.30 104692[110:Spt:104691.0,104003.0,104004.0] || until2p7(s18)*+ -> . % 76.04/76.30 104693[110:Spt:104691.0,104003.1] || -> node4(s17)*. % 76.04/76.30 104695[110:MRR:867.0,104693.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.30 104698[110:Res:53.1,104695.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.30 104700[111:Spt:104698.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 104702[111:Res:104700.0,61.1] always3(s17) || -> . % 76.04/76.30 104703[111:SSi:104702.0,78142.0,78145.0,78595.0,104002.0,104693.0] || -> . % 76.04/76.30 104704[111:Spt:104703.0,104698.0,104700.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.30 104705[111:Spt:104703.0,104698.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 104709[111:Res:104705.0,61.1] always3(s18) || -> . % 76.04/76.30 104710[111:SSi:104709.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.30 104711[109:Spt:104710.0,104001.0,104002.0] || until2p7(s17)*+ -> . % 76.04/76.30 104712[109:Spt:104710.0,104001.1] || -> node4(s16)*. % 76.04/76.30 104714[109:MRR:870.0,104712.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.30 104717[109:Res:53.1,104714.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.30 104719[110:Spt:104717.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 104721[110:Res:104719.0,61.1] always3(s16) || -> . % 76.04/76.30 104722[110:SSi:104721.0,78137.0,78141.0,78594.0,104000.0,104712.0] || -> . % 76.04/76.30 104723[110:Spt:104722.0,104717.0,104719.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.30 104724[110:Spt:104722.0,104717.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 104728[110:Res:104724.0,61.1] always3(s17) || -> . % 76.04/76.30 104729[110:SSi:104728.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.30 104730[108:Spt:104729.0,103999.0,104000.0] || until2p7(s16)*+ -> . % 76.04/76.30 104731[108:Spt:104729.0,103999.1] || -> node4(s15)*. % 76.04/76.30 104733[108:MRR:873.0,104731.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.30 104736[108:Res:53.1,104733.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.30 104741[109:Spt:104736.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 104743[109:Res:104741.0,61.1] always3(s15) || -> . % 76.04/76.30 104744[109:SSi:104743.0,78133.0,78136.0,78593.0,103998.0,104731.0] || -> . % 76.04/76.30 104745[109:Spt:104744.0,104736.0,104741.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.30 104746[109:Spt:104744.0,104736.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 104750[109:Res:104746.0,61.1] always3(s16) || -> . % 76.04/76.30 104751[109:SSi:104750.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.30 104752[107:Spt:104751.0,103997.0,103998.0] || until2p7(s15)*+ -> . % 76.04/76.30 104753[107:Spt:104751.0,103997.1] || -> node4(s14)*. % 76.04/76.30 104755[107:MRR:876.0,104753.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.30 104758[107:Res:53.1,104755.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.30 104760[108:Spt:104758.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 104762[108:Res:104760.0,61.1] always3(s14) || -> . % 76.04/76.30 104763[108:SSi:104762.0,78128.0,78132.0,78592.0,103996.0,104753.0] || -> . % 76.04/76.30 104764[108:Spt:104763.0,104758.0,104760.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.30 104765[108:Spt:104763.0,104758.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 104769[108:Res:104765.0,61.1] always3(s15) || -> . % 76.04/76.30 104770[108:SSi:104769.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.30 104771[106:Spt:104770.0,103995.0,103996.0] || until2p7(s14)*+ -> . % 76.04/76.30 104772[106:Spt:104770.0,103995.1] || -> node4(s13)*. % 76.04/76.30 104774[106:MRR:879.0,104772.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.30 104777[106:Res:53.1,104774.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.30 104779[107:Spt:104777.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 104781[107:Res:104779.0,61.1] always3(s13) || -> . % 76.04/76.30 104782[107:SSi:104781.0,78124.0,78127.0,78591.0,103994.0,104772.0] || -> . % 76.04/76.30 104783[107:Spt:104782.0,104777.0,104779.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.30 104784[107:Spt:104782.0,104777.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 104788[107:Res:104784.0,61.1] always3(s14) || -> . % 76.04/76.30 104789[107:SSi:104788.0,78128.0,78132.0,78592.0] || -> . % 76.04/76.30 104790[105:Spt:104789.0,103993.0,103994.0] || until2p7(s13)*+ -> . % 76.04/76.30 104791[105:Spt:104789.0,103993.1] || -> node4(s12)*. % 76.04/76.30 104793[105:MRR:882.0,104791.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.30 104796[105:Res:53.1,104793.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.30 104798[106:Spt:104796.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 104800[106:Res:104798.0,61.1] always3(s12) || -> . % 76.04/76.30 104801[106:SSi:104800.0,78119.0,78123.0,78590.0,103992.0,104791.0] || -> . % 76.04/76.30 104802[106:Spt:104801.0,104796.0,104798.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.30 104803[106:Spt:104801.0,104796.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 104807[106:Res:104803.0,61.1] always3(s13) || -> . % 76.04/76.30 104808[106:SSi:104807.0,78124.0,78127.0,78591.0] || -> . % 76.04/76.30 104809[104:Spt:104808.0,103991.0,103992.0] || until2p7(s12)*+ -> . % 76.04/76.30 104810[104:Spt:104808.0,103991.1] || -> node4(s11)*. % 76.04/76.30 104812[104:MRR:885.0,104810.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.30 104815[104:Res:53.1,104812.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.30 104820[105:Spt:104815.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 104822[105:Res:104820.0,61.1] always3(s11) || -> . % 76.04/76.30 104823[105:SSi:104822.0,78115.0,78118.0,78589.0,103990.0,104810.0] || -> . % 76.04/76.30 104824[105:Spt:104823.0,104815.0,104820.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.30 104825[105:Spt:104823.0,104815.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 104829[105:Res:104825.0,61.1] always3(s12) || -> . % 76.04/76.30 104830[105:SSi:104829.0,78119.0,78123.0,78590.0] || -> . % 76.04/76.30 104831[103:Spt:104830.0,103989.0,103990.0] || until2p7(s11)*+ -> . % 76.04/76.30 104832[103:Spt:104830.0,103989.1] || -> node4(s10)*. % 76.04/76.30 104834[103:MRR:888.0,104832.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.30 104837[103:Res:53.1,104834.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.30 104839[104:Spt:104837.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 104841[104:Res:104839.0,61.1] always3(s10) || -> . % 76.04/76.30 104842[104:SSi:104841.0,78110.0,78114.0,78588.0,103988.0,104832.0] || -> . % 76.04/76.30 104843[104:Spt:104842.0,104837.0,104839.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.30 104844[104:Spt:104842.0,104837.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 104848[104:Res:104844.0,61.1] always3(s11) || -> . % 76.04/76.30 104849[104:SSi:104848.0,78115.0,78118.0,78589.0] || -> . % 76.04/76.30 104850[102:Spt:104849.0,103987.0,103988.0] || until2p7(s10)*+ -> . % 76.04/76.30 104851[102:Spt:104849.0,103987.1] || -> node4(s9)*. % 76.04/76.30 104853[102:MRR:891.0,104851.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.30 104856[102:Res:53.1,104853.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.30 104858[103:Spt:104856.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 104860[103:Res:104858.0,61.1] always3(s9) || -> . % 76.04/76.30 104861[103:SSi:104860.0,78106.0,78109.0,78587.0,103986.0,104851.0] || -> . % 76.04/76.30 104862[103:Spt:104861.0,104856.0,104858.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.30 104863[103:Spt:104861.0,104856.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 104867[103:Res:104863.0,61.1] always3(s10) || -> . % 76.04/76.30 104868[103:SSi:104867.0,78110.0,78114.0,78588.0] || -> . % 76.04/76.30 104869[101:Spt:104868.0,103985.0,103986.0] || until2p7(s9)*+ -> . % 76.04/76.30 104870[101:Spt:104868.0,103985.1] || -> node4(s8)*. % 76.04/76.30 104872[101:MRR:894.0,104870.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.30 104875[101:Res:53.1,104872.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.30 104877[102:Spt:104875.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 104879[102:Res:104877.0,61.1] always3(s8) || -> . % 76.04/76.30 104880[102:SSi:104879.0,78101.0,78105.0,78586.0,103984.0,104870.0] || -> . % 76.04/76.30 104881[102:Spt:104880.0,104875.0,104877.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.30 104882[102:Spt:104880.0,104875.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 104886[102:Res:104882.0,61.1] always3(s9) || -> . % 76.04/76.30 104887[102:SSi:104886.0,78106.0,78109.0,78587.0] || -> . % 76.04/76.30 104888[100:Spt:104887.0,103983.0,103984.0] || until2p7(s8)*+ -> . % 76.04/76.30 104889[100:Spt:104887.0,103983.1] || -> node4(s7)*. % 76.04/76.30 104891[100:MRR:897.0,104889.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.30 104894[100:Res:53.1,104891.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.30 104899[101:Spt:104894.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.30 104901[101:Res:104899.0,61.1] always3(s7) || -> . % 76.04/76.30 104902[101:SSi:104901.0,78097.0,78100.0,78585.0,103982.0,104889.0] || -> . % 76.04/76.30 104903[101:Spt:104902.0,104894.0,104899.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.30 104904[101:Spt:104902.0,104894.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 104908[101:Res:104904.0,61.1] always3(s8) || -> . % 76.04/76.30 104909[101:SSi:104908.0,78101.0,78105.0,78586.0] || -> . % 76.04/76.30 104910[99:Spt:104909.0,103981.0,103982.0] || until2p7(s7)*+ -> . % 76.04/76.30 104911[99:Spt:104909.0,103981.1] || -> node4(s6)*. % 76.04/76.30 104913[99:MRR:900.0,104911.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.30 104916[99:Res:53.1,104913.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.30 104918[100:Spt:104916.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.30 104920[100:Res:104918.0,61.1] always3(s6) || -> . % 76.04/76.30 104921[100:SSi:104920.0,78093.0,78096.0,78584.0,103980.0,104911.0] || -> . % 76.04/76.30 104922[100:Spt:104921.0,104916.0,104918.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.30 104923[100:Spt:104921.0,104916.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.30 104927[100:Res:104923.0,61.1] always3(s7) || -> . % 76.04/76.30 104928[100:SSi:104927.0,78097.0,78100.0,78585.0] || -> . % 76.04/76.30 104929[98:Spt:104928.0,103979.0,103980.0] || until2p7(s6)*+ -> . % 76.04/76.30 104930[98:Spt:104928.0,103979.1] || -> node4(s5)*. % 76.04/76.30 104932[98:MRR:903.0,104930.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.30 104935[98:Res:53.1,104932.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.30 104937[98:MRR:104935.0,103969.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.30 104939[98:Res:104937.0,61.1] always3(s6) || -> . % 76.04/76.30 104940[98:SSi:104939.0,78093.0,78096.0,78584.0] || -> . % 76.04/76.30 104941[96:Spt:104940.0,103807.0,103810.0] || trans(s49,s5)*+ -> . % 76.04/76.30 104942[96:Spt:104940.0,103807.1,103807.2,103807.3] || -> trans(s49,s4) trans(s49,s3) node2(s49,s2)*. % 76.04/76.30 104944[96:MRR:103809.1,104941.0] xuntil6(s49) || -> trans(s49,s4) trans(s49,s3)* until2p7(s2). % 76.04/76.30 104945[97:Spt:104942.0] || -> trans(s49,s4)*. % 76.04/76.30 104946[97:Res:104945.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s4)*. % 76.04/76.30 104948[97:Res:104945.0,60.0] || -> node2(s49,s4)*. % 76.04/76.30 104949[97:SSi:104946.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s4)*. % 76.04/76.30 104950[97:Res:104948.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s4,c_busy)*. % 76.04/76.30 105100[97:SoR:104950.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s4,c_busy)*. % 76.04/76.30 105102[97:SoR:105100.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s4,c_busy)* xuntil6(s49). % 76.04/76.30 105103[97:SSi:105102.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s4,c_busy)* xuntil6(s49). % 76.04/76.30 105104[98:Spt:105103.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.30 105106[98:Res:105104.0,61.1] always3(s4) || -> . % 76.04/76.30 105107[98:SSi:105106.0,78085.0,78088.0,78582.0] || -> . % 76.04/76.30 105108[98:Spt:105107.0,105103.1,105104.0] || m_main_v_state(s4,c_busy)*+ -> . % 76.04/76.30 105109[98:Spt:105107.0,105103.0,105103.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 105113[98:MRR:105100.2,105108.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 105114[98:Res:53.1,105109.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 105116[98:MRR:105114.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 105117[98:MRR:104949.0,105116.0] || -> until2p7(s4)*. % 76.04/76.30 105118[98:MRR:200.0,105117.0] || -> until2p7(s5)* node4(s4). % 76.04/76.30 105119[99:Spt:105118.0] || -> until2p7(s5)*. % 76.04/76.30 105120[99:MRR:201.0,105119.0] || -> until2p7(s6)* node4(s5). % 76.04/76.30 105121[100:Spt:105120.0] || -> until2p7(s6)*. % 76.04/76.30 105122[100:MRR:202.0,105121.0] || -> until2p7(s7)* node4(s6). % 76.04/76.30 105123[101:Spt:105122.0] || -> until2p7(s7)*. % 76.04/76.30 105124[101:MRR:203.0,105123.0] || -> until2p7(s8)* node4(s7). % 76.04/76.30 105125[102:Spt:105124.0] || -> until2p7(s8)*. % 76.04/76.30 105126[102:MRR:204.0,105125.0] || -> until2p7(s9)* node4(s8). % 76.04/76.30 105127[103:Spt:105126.0] || -> until2p7(s9)*. % 76.04/76.30 105128[103:MRR:205.0,105127.0] || -> until2p7(s10)* node4(s9). % 76.04/76.30 105129[104:Spt:105128.0] || -> until2p7(s10)*. % 76.04/76.30 105130[104:MRR:206.0,105129.0] || -> until2p7(s11)* node4(s10). % 76.04/76.30 105131[105:Spt:105130.0] || -> until2p7(s11)*. % 76.04/76.30 105132[105:MRR:207.0,105131.0] || -> until2p7(s12)* node4(s11). % 76.04/76.30 105133[106:Spt:105132.0] || -> until2p7(s12)*. % 76.04/76.30 105134[106:MRR:208.0,105133.0] || -> until2p7(s13)* node4(s12). % 76.04/76.30 105135[107:Spt:105134.0] || -> until2p7(s13)*. % 76.04/76.30 105136[107:MRR:209.0,105135.0] || -> until2p7(s14)* node4(s13). % 76.04/76.30 105137[108:Spt:105136.0] || -> until2p7(s14)*. % 76.04/76.30 105138[108:MRR:210.0,105137.0] || -> until2p7(s15)* node4(s14). % 76.04/76.30 105139[109:Spt:105138.0] || -> until2p7(s15)*. % 76.04/76.30 105140[109:MRR:211.0,105139.0] || -> until2p7(s16)* node4(s15). % 76.04/76.30 105141[110:Spt:105140.0] || -> until2p7(s16)*. % 76.04/76.30 105142[110:MRR:212.0,105141.0] || -> until2p7(s17)* node4(s16). % 76.04/76.30 105143[111:Spt:105142.0] || -> until2p7(s17)*. % 76.04/76.30 105144[111:MRR:213.0,105143.0] || -> until2p7(s18)* node4(s17). % 76.04/76.30 105145[112:Spt:105144.0] || -> until2p7(s18)*. % 76.04/76.30 105146[112:MRR:214.0,105145.0] || -> until2p7(s19)* node4(s18). % 76.04/76.30 105147[113:Spt:105146.0] || -> until2p7(s19)*. % 76.04/76.30 105148[113:MRR:215.0,105147.0] || -> until2p7(s20)* node4(s19). % 76.04/76.30 105149[114:Spt:105148.0] || -> until2p7(s20)*. % 76.04/76.30 105150[114:MRR:216.0,105149.0] || -> until2p7(s21)* node4(s20). % 76.04/76.30 105151[115:Spt:105150.0] || -> until2p7(s21)*. % 76.04/76.30 105152[115:MRR:217.0,105151.0] || -> until2p7(s22)* node4(s21). % 76.04/76.30 105153[116:Spt:105152.0] || -> until2p7(s22)*. % 76.04/76.30 105154[116:MRR:218.0,105153.0] || -> until2p7(s23)* node4(s22). % 76.04/76.30 105155[117:Spt:105154.0] || -> until2p7(s23)*. % 76.04/76.30 105156[117:MRR:219.0,105155.0] || -> until2p7(s24)* node4(s23). % 76.04/76.30 105157[118:Spt:105156.0] || -> until2p7(s24)*. % 76.04/76.30 105158[118:MRR:220.0,105157.0] || -> until2p7(s25)* node4(s24). % 76.04/76.30 105159[119:Spt:105158.0] || -> until2p7(s25)*. % 76.04/76.30 105160[119:MRR:221.0,105159.0] || -> until2p7(s26)* node4(s25). % 76.04/76.30 105161[120:Spt:105160.0] || -> until2p7(s26)*. % 76.04/76.30 105162[120:MRR:222.0,105161.0] || -> until2p7(s27)* node4(s26). % 76.04/76.30 105163[121:Spt:105162.0] || -> until2p7(s27)*. % 76.04/76.30 105164[121:MRR:223.0,105163.0] || -> until2p7(s28)* node4(s27). % 76.04/76.30 105165[122:Spt:105164.0] || -> until2p7(s28)*. % 76.04/76.30 105166[122:MRR:224.0,105165.0] || -> until2p7(s29)* node4(s28). % 76.04/76.30 105167[123:Spt:105166.0] || -> until2p7(s29)*. % 76.04/76.30 105168[123:MRR:225.0,105167.0] || -> until2p7(s30)* node4(s29). % 76.04/76.30 105169[124:Spt:105168.0] || -> until2p7(s30)*. % 76.04/76.30 105170[124:MRR:226.0,105169.0] || -> until2p7(s31)* node4(s30). % 76.04/76.30 105171[125:Spt:105170.0] || -> until2p7(s31)*. % 76.04/76.30 105172[125:MRR:227.0,105171.0] || -> until2p7(s32)* node4(s31). % 76.04/76.30 105173[126:Spt:105172.0] || -> until2p7(s32)*. % 76.04/76.30 105174[126:MRR:228.0,105173.0] || -> until2p7(s33)* node4(s32). % 76.04/76.30 105175[127:Spt:105174.0] || -> until2p7(s33)*. % 76.04/76.30 105176[127:MRR:229.0,105175.0] || -> until2p7(s34)* node4(s33). % 76.04/76.30 105177[128:Spt:105176.0] || -> until2p7(s34)*. % 76.04/76.30 105178[128:MRR:230.0,105177.0] || -> until2p7(s35)* node4(s34). % 76.04/76.30 105179[129:Spt:105178.0] || -> until2p7(s35)*. % 76.04/76.30 105180[129:MRR:231.0,105179.0] || -> until2p7(s36)* node4(s35). % 76.04/76.30 105181[130:Spt:105180.0] || -> until2p7(s36)*. % 76.04/76.30 105182[130:MRR:232.0,105181.0] || -> until2p7(s37)* node4(s36). % 76.04/76.30 105183[131:Spt:105182.0] || -> until2p7(s37)*. % 76.04/76.30 105184[131:MRR:235.0,105183.0] || -> until2p7(s38)* node4(s37). % 76.04/76.30 105185[132:Spt:105184.0] || -> until2p7(s38)*. % 76.04/76.30 105186[132:MRR:236.0,105185.0] || -> until2p7(s39)* node4(s38). % 76.04/76.30 105187[133:Spt:105186.0] || -> until2p7(s39)*. % 76.04/76.30 105188[133:MRR:237.0,105187.0] || -> until2p7(s40)* node4(s39). % 76.04/76.30 105189[134:Spt:105188.0] || -> until2p7(s40)*. % 76.04/76.30 105190[134:MRR:238.0,105189.0] || -> until2p7(s41)* node4(s40). % 76.04/76.30 105191[135:Spt:105190.0] || -> until2p7(s41)*. % 76.04/76.30 105192[135:MRR:239.0,105191.0] || -> until2p7(s42)* node4(s41). % 76.04/76.30 105193[136:Spt:105192.0] || -> until2p7(s42)*. % 76.04/76.30 105194[136:MRR:240.0,105193.0] || -> until2p7(s43)* node4(s42). % 76.04/76.30 105195[137:Spt:105194.0] || -> until2p7(s43)*. % 76.04/76.30 105196[137:MRR:241.0,105195.0] || -> until2p7(s44)* node4(s43). % 76.04/76.30 105197[138:Spt:105196.0] || -> until2p7(s44)*. % 76.04/76.30 105198[138:MRR:539.0,105197.0] || -> until2p7(s45)* node4(s44). % 76.04/76.30 105199[139:Spt:105198.0] || -> until2p7(s45)*. % 76.04/76.30 105200[139:MRR:544.0,105199.0] || -> until2p7(s46)* node4(s45). % 76.04/76.30 105201[140:Spt:105200.0] || -> until2p7(s46)*. % 76.04/76.30 105202[140:MRR:549.0,105201.0] || -> until2p7(s47)* node4(s46). % 76.04/76.30 105203[141:Spt:105202.0] || -> until2p7(s47)*. % 76.04/76.30 105204[141:MRR:554.0,105203.0] || -> until2p7(s48)* node4(s47). % 76.04/76.30 105205[142:Spt:105204.0] || -> until2p7(s48)*. % 76.04/76.30 105206[142:MRR:559.0,105205.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 105207[143:Spt:105206.0] || -> until2p7(s49)*. % 76.04/76.30 105208[143:MRR:194.0,105207.0] || -> node4(s49)*. % 76.04/76.30 105209[143:MRR:105113.0,105208.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 105210[143:Res:53.1,105209.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 105212[143:MRR:105210.0,78381.0] || -> . % 76.04/76.30 105213[143:Spt:105212.0,105206.0,105207.0] || until2p7(s49)*+ -> . % 76.04/76.30 105214[143:Spt:105212.0,105206.1] || -> node4(s48)*. % 76.04/76.30 105215[143:MRR:78384.0,105214.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 105218[143:Res:53.1,105215.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 105221[143:Res:105218.0,61.1] always3(s48) || -> . % 76.04/76.30 105222[143:SSi:105221.0,78281.0,78387.0,78626.0,105205.0,105214.0] || -> . % 76.04/76.30 105223[142:Spt:105222.0,105204.0,105205.0] || until2p7(s48)*+ -> . % 76.04/76.30 105224[142:Spt:105222.0,105204.1] || -> node4(s47)*. % 76.04/76.30 105226[142:MRR:777.0,105224.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.30 105241[142:Res:53.1,105226.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.30 105243[143:Spt:105241.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 105245[143:Res:105243.0,61.1] always3(s47) || -> . % 76.04/76.30 105246[143:SSi:105245.0,78277.0,78280.0,78625.0,105203.0,105224.0] || -> . % 76.04/76.30 105247[143:Spt:105246.0,105241.0,105243.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.30 105248[143:Spt:105246.0,105241.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 105252[143:Res:105248.0,61.1] always3(s48) || -> . % 76.04/76.30 105253[143:SSi:105252.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.30 105254[141:Spt:105253.0,105202.0,105203.0] || until2p7(s47)*+ -> . % 76.04/76.30 105255[141:Spt:105253.0,105202.1] || -> node4(s46)*. % 76.04/76.30 105257[141:MRR:780.0,105255.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.30 105267[141:Res:53.1,105257.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.30 105269[142:Spt:105267.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 105271[142:Res:105269.0,61.1] always3(s46) || -> . % 76.04/76.30 105272[142:SSi:105271.0,78272.0,78276.0,78624.0,105201.0,105255.0] || -> . % 76.04/76.30 105273[142:Spt:105272.0,105267.0,105269.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.30 105274[142:Spt:105272.0,105267.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 105278[142:Res:105274.0,61.1] always3(s47) || -> . % 76.04/76.30 105279[142:SSi:105278.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.30 105280[140:Spt:105279.0,105200.0,105201.0] || until2p7(s46)*+ -> . % 76.04/76.30 105281[140:Spt:105279.0,105200.1] || -> node4(s45)*. % 76.04/76.30 105283[140:MRR:783.0,105281.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.30 105286[140:Res:53.1,105283.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.30 105288[141:Spt:105286.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 105290[141:Res:105288.0,61.1] always3(s45) || -> . % 76.04/76.30 105291[141:SSi:105290.0,78268.0,78271.0,78623.0,105199.0,105281.0] || -> . % 76.04/76.30 105292[141:Spt:105291.0,105286.0,105288.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.30 105293[141:Spt:105291.0,105286.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 105297[141:Res:105293.0,61.1] always3(s46) || -> . % 76.04/76.30 105298[141:SSi:105297.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.30 105299[139:Spt:105298.0,105198.0,105199.0] || until2p7(s45)*+ -> . % 76.04/76.30 105300[139:Spt:105298.0,105198.1] || -> node4(s44)*. % 76.04/76.30 105302[139:MRR:786.0,105300.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.30 105305[139:Res:53.1,105302.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.30 105307[140:Spt:105305.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 105309[140:Res:105307.0,61.1] always3(s44) || -> . % 76.04/76.30 105310[140:SSi:105309.0,78263.0,78267.0,78622.0,105197.0,105300.0] || -> . % 76.04/76.30 105311[140:Spt:105310.0,105305.0,105307.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.30 105312[140:Spt:105310.0,105305.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 105316[140:Res:105312.0,61.1] always3(s45) || -> . % 76.04/76.30 105317[140:SSi:105316.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.30 105318[138:Spt:105317.0,105196.0,105197.0] || until2p7(s44)*+ -> . % 76.04/76.30 105319[138:Spt:105317.0,105196.1] || -> node4(s43)*. % 76.04/76.30 105321[138:MRR:789.0,105319.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.30 105324[138:Res:53.1,105321.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.30 105329[139:Spt:105324.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 105331[139:Res:105329.0,61.1] always3(s43) || -> . % 76.04/76.30 105332[139:SSi:105331.0,78259.0,78262.0,78621.0,105195.0,105319.0] || -> . % 76.04/76.30 105333[139:Spt:105332.0,105324.0,105329.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.30 105334[139:Spt:105332.0,105324.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 105338[139:Res:105334.0,61.1] always3(s44) || -> . % 76.04/76.30 105339[139:SSi:105338.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.30 105340[137:Spt:105339.0,105194.0,105195.0] || until2p7(s43)*+ -> . % 76.04/76.30 105341[137:Spt:105339.0,105194.1] || -> node4(s42)*. % 76.04/76.30 105343[137:MRR:792.0,105341.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.30 105346[137:Res:53.1,105343.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.30 105348[138:Spt:105346.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 105350[138:Res:105348.0,61.1] always3(s42) || -> . % 76.04/76.30 105351[138:SSi:105350.0,78254.0,78258.0,78620.0,105193.0,105341.0] || -> . % 76.04/76.30 105352[138:Spt:105351.0,105346.0,105348.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.30 105353[138:Spt:105351.0,105346.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 105357[138:Res:105353.0,61.1] always3(s43) || -> . % 76.04/76.30 105358[138:SSi:105357.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.30 105359[136:Spt:105358.0,105192.0,105193.0] || until2p7(s42)*+ -> . % 76.04/76.30 105360[136:Spt:105358.0,105192.1] || -> node4(s41)*. % 76.04/76.30 105362[136:MRR:795.0,105360.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.30 105365[136:Res:53.1,105362.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.30 105367[137:Spt:105365.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 105369[137:Res:105367.0,61.1] always3(s41) || -> . % 76.04/76.30 105370[137:SSi:105369.0,78250.0,78253.0,78619.0,105191.0,105360.0] || -> . % 76.04/76.30 105371[137:Spt:105370.0,105365.0,105367.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.30 105372[137:Spt:105370.0,105365.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 105376[137:Res:105372.0,61.1] always3(s42) || -> . % 76.04/76.30 105377[137:SSi:105376.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.30 105378[135:Spt:105377.0,105190.0,105191.0] || until2p7(s41)*+ -> . % 76.04/76.30 105379[135:Spt:105377.0,105190.1] || -> node4(s40)*. % 76.04/76.30 105381[135:MRR:798.0,105379.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.30 105384[135:Res:53.1,105381.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.30 105386[136:Spt:105384.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 105388[136:Res:105386.0,61.1] always3(s40) || -> . % 76.04/76.30 105389[136:SSi:105388.0,78245.0,78249.0,78618.0,105189.0,105379.0] || -> . % 76.04/76.30 105390[136:Spt:105389.0,105384.0,105386.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.30 105391[136:Spt:105389.0,105384.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 105395[136:Res:105391.0,61.1] always3(s41) || -> . % 76.04/76.30 105396[136:SSi:105395.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.30 105397[134:Spt:105396.0,105188.0,105189.0] || until2p7(s40)*+ -> . % 76.04/76.30 105398[134:Spt:105396.0,105188.1] || -> node4(s39)*. % 76.04/76.30 105400[134:MRR:801.0,105398.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.30 105403[134:Res:53.1,105400.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.30 105408[135:Spt:105403.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 105410[135:Res:105408.0,61.1] always3(s39) || -> . % 76.04/76.30 105411[135:SSi:105410.0,78241.0,78244.0,78617.0,105187.0,105398.0] || -> . % 76.04/76.30 105412[135:Spt:105411.0,105403.0,105408.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.30 105413[135:Spt:105411.0,105403.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 105417[135:Res:105413.0,61.1] always3(s40) || -> . % 76.04/76.30 105418[135:SSi:105417.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.30 105419[133:Spt:105418.0,105186.0,105187.0] || until2p7(s39)*+ -> . % 76.04/76.30 105420[133:Spt:105418.0,105186.1] || -> node4(s38)*. % 76.04/76.30 105422[133:MRR:804.0,105420.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.30 105425[133:Res:53.1,105422.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.30 105427[134:Spt:105425.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 105429[134:Res:105427.0,61.1] always3(s38) || -> . % 76.04/76.30 105430[134:SSi:105429.0,78236.0,78240.0,78616.0,105185.0,105420.0] || -> . % 76.04/76.30 105431[134:Spt:105430.0,105425.0,105427.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.30 105432[134:Spt:105430.0,105425.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 105436[134:Res:105432.0,61.1] always3(s39) || -> . % 76.04/76.30 105437[134:SSi:105436.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.30 105438[132:Spt:105437.0,105184.0,105185.0] || until2p7(s38)*+ -> . % 76.04/76.30 105439[132:Spt:105437.0,105184.1] || -> node4(s37)*. % 76.04/76.30 105441[132:MRR:807.0,105439.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.30 105444[132:Res:53.1,105441.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.30 105446[133:Spt:105444.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 105448[133:Res:105446.0,61.1] always3(s37) || -> . % 76.04/76.30 105449[133:SSi:105448.0,78232.0,78235.0,78615.0,105183.0,105439.0] || -> . % 76.04/76.30 105450[133:Spt:105449.0,105444.0,105446.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.30 105451[133:Spt:105449.0,105444.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 105455[133:Res:105451.0,61.1] always3(s38) || -> . % 76.04/76.30 105456[133:SSi:105455.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.30 105457[131:Spt:105456.0,105182.0,105183.0] || until2p7(s37)*+ -> . % 76.04/76.30 105458[131:Spt:105456.0,105182.1] || -> node4(s36)*. % 76.04/76.30 105460[131:MRR:810.0,105458.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.30 105463[131:Res:53.1,105460.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.30 105465[132:Spt:105463.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 105467[132:Res:105465.0,61.1] always3(s36) || -> . % 76.04/76.30 105468[132:SSi:105467.0,78227.0,78231.0,78614.0,105181.0,105458.0] || -> . % 76.04/76.30 105469[132:Spt:105468.0,105463.0,105465.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.30 105470[132:Spt:105468.0,105463.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 105474[132:Res:105470.0,61.1] always3(s37) || -> . % 76.04/76.30 105475[132:SSi:105474.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.30 105476[130:Spt:105475.0,105180.0,105181.0] || until2p7(s36)*+ -> . % 76.04/76.30 105477[130:Spt:105475.0,105180.1] || -> node4(s35)*. % 76.04/76.30 105479[130:MRR:813.0,105477.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.30 105482[130:Res:53.1,105479.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.30 105487[131:Spt:105482.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 105489[131:Res:105487.0,61.1] always3(s35) || -> . % 76.04/76.30 105490[131:SSi:105489.0,78223.0,78226.0,78613.0,105179.0,105477.0] || -> . % 76.04/76.30 105491[131:Spt:105490.0,105482.0,105487.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.30 105492[131:Spt:105490.0,105482.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 105496[131:Res:105492.0,61.1] always3(s36) || -> . % 76.04/76.30 105497[131:SSi:105496.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.30 105498[129:Spt:105497.0,105178.0,105179.0] || until2p7(s35)*+ -> . % 76.04/76.30 105499[129:Spt:105497.0,105178.1] || -> node4(s34)*. % 76.04/76.30 105501[129:MRR:816.0,105499.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.30 105504[129:Res:53.1,105501.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.30 105506[130:Spt:105504.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 105508[130:Res:105506.0,61.1] always3(s34) || -> . % 76.04/76.30 105509[130:SSi:105508.0,78218.0,78222.0,78612.0,105177.0,105499.0] || -> . % 76.04/76.30 105510[130:Spt:105509.0,105504.0,105506.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.30 105511[130:Spt:105509.0,105504.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 105515[130:Res:105511.0,61.1] always3(s35) || -> . % 76.04/76.30 105516[130:SSi:105515.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.30 105517[128:Spt:105516.0,105176.0,105177.0] || until2p7(s34)*+ -> . % 76.04/76.30 105518[128:Spt:105516.0,105176.1] || -> node4(s33)*. % 76.04/76.30 105520[128:MRR:819.0,105518.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.30 105523[128:Res:53.1,105520.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.30 105525[129:Spt:105523.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 105527[129:Res:105525.0,61.1] always3(s33) || -> . % 76.04/76.30 105528[129:SSi:105527.0,78214.0,78217.0,78611.0,105175.0,105518.0] || -> . % 76.04/76.30 105529[129:Spt:105528.0,105523.0,105525.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.30 105530[129:Spt:105528.0,105523.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 105534[129:Res:105530.0,61.1] always3(s34) || -> . % 76.04/76.30 105535[129:SSi:105534.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.30 105536[127:Spt:105535.0,105174.0,105175.0] || until2p7(s33)*+ -> . % 76.04/76.30 105537[127:Spt:105535.0,105174.1] || -> node4(s32)*. % 76.04/76.30 105539[127:MRR:822.0,105537.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.30 105542[127:Res:53.1,105539.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.30 105544[128:Spt:105542.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 105546[128:Res:105544.0,61.1] always3(s32) || -> . % 76.04/76.30 105547[128:SSi:105546.0,78209.0,78213.0,78610.0,105173.0,105537.0] || -> . % 76.04/76.30 105548[128:Spt:105547.0,105542.0,105544.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.30 105549[128:Spt:105547.0,105542.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 105553[128:Res:105549.0,61.1] always3(s33) || -> . % 76.04/76.30 105554[128:SSi:105553.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.30 105555[126:Spt:105554.0,105172.0,105173.0] || until2p7(s32)*+ -> . % 76.04/76.30 105556[126:Spt:105554.0,105172.1] || -> node4(s31)*. % 76.04/76.30 105558[126:MRR:825.0,105556.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.30 105561[126:Res:53.1,105558.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.30 105566[127:Spt:105561.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 105568[127:Res:105566.0,61.1] always3(s31) || -> . % 76.04/76.30 105569[127:SSi:105568.0,78205.0,78208.0,78609.0,105171.0,105556.0] || -> . % 76.04/76.30 105570[127:Spt:105569.0,105561.0,105566.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.30 105571[127:Spt:105569.0,105561.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 105575[127:Res:105571.0,61.1] always3(s32) || -> . % 76.04/76.30 105576[127:SSi:105575.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.30 105577[125:Spt:105576.0,105170.0,105171.0] || until2p7(s31)*+ -> . % 76.04/76.30 105578[125:Spt:105576.0,105170.1] || -> node4(s30)*. % 76.04/76.30 105580[125:MRR:828.0,105578.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.30 105583[125:Res:53.1,105580.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.30 105585[126:Spt:105583.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 105587[126:Res:105585.0,61.1] always3(s30) || -> . % 76.04/76.30 105588[126:SSi:105587.0,78200.0,78204.0,78608.0,105169.0,105578.0] || -> . % 76.04/76.30 105589[126:Spt:105588.0,105583.0,105585.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.30 105590[126:Spt:105588.0,105583.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 105594[126:Res:105590.0,61.1] always3(s31) || -> . % 76.04/76.30 105595[126:SSi:105594.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.30 105596[124:Spt:105595.0,105168.0,105169.0] || until2p7(s30)*+ -> . % 76.04/76.30 105597[124:Spt:105595.0,105168.1] || -> node4(s29)*. % 76.04/76.30 105599[124:MRR:831.0,105597.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.30 105602[124:Res:53.1,105599.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.30 105604[125:Spt:105602.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 105606[125:Res:105604.0,61.1] always3(s29) || -> . % 76.04/76.30 105607[125:SSi:105606.0,78196.0,78199.0,78607.0,105167.0,105597.0] || -> . % 76.04/76.30 105608[125:Spt:105607.0,105602.0,105604.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.30 105609[125:Spt:105607.0,105602.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 105613[125:Res:105609.0,61.1] always3(s30) || -> . % 76.04/76.30 105614[125:SSi:105613.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.30 105615[123:Spt:105614.0,105166.0,105167.0] || until2p7(s29)*+ -> . % 76.04/76.30 105616[123:Spt:105614.0,105166.1] || -> node4(s28)*. % 76.04/76.30 105618[123:MRR:834.0,105616.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.30 105621[123:Res:53.1,105618.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.30 105623[124:Spt:105621.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 105625[124:Res:105623.0,61.1] always3(s28) || -> . % 76.04/76.30 105626[124:SSi:105625.0,78191.0,78195.0,78606.0,105165.0,105616.0] || -> . % 76.04/76.30 105627[124:Spt:105626.0,105621.0,105623.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.30 105628[124:Spt:105626.0,105621.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 105632[124:Res:105628.0,61.1] always3(s29) || -> . % 76.04/76.30 105633[124:SSi:105632.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.30 105634[122:Spt:105633.0,105164.0,105165.0] || until2p7(s28)*+ -> . % 76.04/76.30 105635[122:Spt:105633.0,105164.1] || -> node4(s27)*. % 76.04/76.30 105637[122:MRR:837.0,105635.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.30 105640[122:Res:53.1,105637.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.30 105645[123:Spt:105640.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 105647[123:Res:105645.0,61.1] always3(s27) || -> . % 76.04/76.30 105648[123:SSi:105647.0,78187.0,78190.0,78605.0,105163.0,105635.0] || -> . % 76.04/76.30 105649[123:Spt:105648.0,105640.0,105645.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.30 105650[123:Spt:105648.0,105640.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 105654[123:Res:105650.0,61.1] always3(s28) || -> . % 76.04/76.30 105655[123:SSi:105654.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.30 105656[121:Spt:105655.0,105162.0,105163.0] || until2p7(s27)*+ -> . % 76.04/76.30 105657[121:Spt:105655.0,105162.1] || -> node4(s26)*. % 76.04/76.30 105659[121:MRR:840.0,105657.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.30 105662[121:Res:53.1,105659.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.30 105664[122:Spt:105662.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 105666[122:Res:105664.0,61.1] always3(s26) || -> . % 76.04/76.30 105667[122:SSi:105666.0,78182.0,78186.0,78604.0,105161.0,105657.0] || -> . % 76.04/76.30 105668[122:Spt:105667.0,105662.0,105664.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.30 105669[122:Spt:105667.0,105662.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 105673[122:Res:105669.0,61.1] always3(s27) || -> . % 76.04/76.30 105674[122:SSi:105673.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.30 105675[120:Spt:105674.0,105160.0,105161.0] || until2p7(s26)*+ -> . % 76.04/76.30 105676[120:Spt:105674.0,105160.1] || -> node4(s25)*. % 76.04/76.30 105678[120:MRR:843.0,105676.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.30 105681[120:Res:53.1,105678.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.30 105683[121:Spt:105681.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 105685[121:Res:105683.0,61.1] always3(s25) || -> . % 76.04/76.30 105686[121:SSi:105685.0,78178.0,78181.0,78603.0,105159.0,105676.0] || -> . % 76.04/76.30 105687[121:Spt:105686.0,105681.0,105683.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.30 105688[121:Spt:105686.0,105681.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 105692[121:Res:105688.0,61.1] always3(s26) || -> . % 76.04/76.30 105693[121:SSi:105692.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.30 105694[119:Spt:105693.0,105158.0,105159.0] || until2p7(s25)*+ -> . % 76.04/76.30 105695[119:Spt:105693.0,105158.1] || -> node4(s24)*. % 76.04/76.30 105697[119:MRR:846.0,105695.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.30 105700[119:Res:53.1,105697.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.30 105702[120:Spt:105700.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 105704[120:Res:105702.0,61.1] always3(s24) || -> . % 76.04/76.30 105705[120:SSi:105704.0,78173.0,78177.0,78602.0,105157.0,105695.0] || -> . % 76.04/76.30 105706[120:Spt:105705.0,105700.0,105702.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.30 105707[120:Spt:105705.0,105700.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 105711[120:Res:105707.0,61.1] always3(s25) || -> . % 76.04/76.30 105712[120:SSi:105711.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.30 105713[118:Spt:105712.0,105156.0,105157.0] || until2p7(s24)*+ -> . % 76.04/76.30 105714[118:Spt:105712.0,105156.1] || -> node4(s23)*. % 76.04/76.30 105716[118:MRR:849.0,105714.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.30 105719[118:Res:53.1,105716.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.30 105724[119:Spt:105719.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 105726[119:Res:105724.0,61.1] always3(s23) || -> . % 76.04/76.30 105727[119:SSi:105726.0,78169.0,78172.0,78601.0,105155.0,105714.0] || -> . % 76.04/76.30 105728[119:Spt:105727.0,105719.0,105724.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.30 105729[119:Spt:105727.0,105719.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 105733[119:Res:105729.0,61.1] always3(s24) || -> . % 76.04/76.30 105734[119:SSi:105733.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.30 105735[117:Spt:105734.0,105154.0,105155.0] || until2p7(s23)*+ -> . % 76.04/76.30 105736[117:Spt:105734.0,105154.1] || -> node4(s22)*. % 76.04/76.30 105738[117:MRR:852.0,105736.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.30 105741[117:Res:53.1,105738.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.30 105743[118:Spt:105741.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 105745[118:Res:105743.0,61.1] always3(s22) || -> . % 76.04/76.30 105746[118:SSi:105745.0,78164.0,78168.0,78600.0,105153.0,105736.0] || -> . % 76.04/76.30 105747[118:Spt:105746.0,105741.0,105743.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.30 105748[118:Spt:105746.0,105741.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 105752[118:Res:105748.0,61.1] always3(s23) || -> . % 76.04/76.30 105753[118:SSi:105752.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.30 105754[116:Spt:105753.0,105152.0,105153.0] || until2p7(s22)*+ -> . % 76.04/76.30 105755[116:Spt:105753.0,105152.1] || -> node4(s21)*. % 76.04/76.30 105757[116:MRR:855.0,105755.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.30 105760[116:Res:53.1,105757.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.30 105762[117:Spt:105760.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 105764[117:Res:105762.0,61.1] always3(s21) || -> . % 76.04/76.30 105765[117:SSi:105764.0,78160.0,78163.0,78599.0,105151.0,105755.0] || -> . % 76.04/76.30 105766[117:Spt:105765.0,105760.0,105762.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.30 105767[117:Spt:105765.0,105760.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 105771[117:Res:105767.0,61.1] always3(s22) || -> . % 76.04/76.30 105772[117:SSi:105771.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.30 105773[115:Spt:105772.0,105150.0,105151.0] || until2p7(s21)*+ -> . % 76.04/76.30 105774[115:Spt:105772.0,105150.1] || -> node4(s20)*. % 76.04/76.30 105776[115:MRR:858.0,105774.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.30 105779[115:Res:53.1,105776.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.30 105781[116:Spt:105779.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 105783[116:Res:105781.0,61.1] always3(s20) || -> . % 76.04/76.30 105784[116:SSi:105783.0,78155.0,78159.0,78598.0,105149.0,105774.0] || -> . % 76.04/76.30 105785[116:Spt:105784.0,105779.0,105781.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.30 105786[116:Spt:105784.0,105779.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 105790[116:Res:105786.0,61.1] always3(s21) || -> . % 76.04/76.30 105791[116:SSi:105790.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.30 105792[114:Spt:105791.0,105148.0,105149.0] || until2p7(s20)*+ -> . % 76.04/76.30 105793[114:Spt:105791.0,105148.1] || -> node4(s19)*. % 76.04/76.30 105795[114:MRR:861.0,105793.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.30 105798[114:Res:53.1,105795.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.30 105803[115:Spt:105798.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 105805[115:Res:105803.0,61.1] always3(s19) || -> . % 76.04/76.30 105806[115:SSi:105805.0,78151.0,78154.0,78597.0,105147.0,105793.0] || -> . % 76.04/76.30 105807[115:Spt:105806.0,105798.0,105803.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.30 105808[115:Spt:105806.0,105798.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 105812[115:Res:105808.0,61.1] always3(s20) || -> . % 76.04/76.30 105813[115:SSi:105812.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.30 105814[113:Spt:105813.0,105146.0,105147.0] || until2p7(s19)*+ -> . % 76.04/76.30 105815[113:Spt:105813.0,105146.1] || -> node4(s18)*. % 76.04/76.30 105817[113:MRR:864.0,105815.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.30 105820[113:Res:53.1,105817.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.30 105822[114:Spt:105820.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 105824[114:Res:105822.0,61.1] always3(s18) || -> . % 76.04/76.30 105825[114:SSi:105824.0,78146.0,78150.0,78596.0,105145.0,105815.0] || -> . % 76.04/76.30 105826[114:Spt:105825.0,105820.0,105822.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.30 105827[114:Spt:105825.0,105820.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 105831[114:Res:105827.0,61.1] always3(s19) || -> . % 76.04/76.30 105832[114:SSi:105831.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.30 105833[112:Spt:105832.0,105144.0,105145.0] || until2p7(s18)*+ -> . % 76.04/76.30 105834[112:Spt:105832.0,105144.1] || -> node4(s17)*. % 76.04/76.30 105836[112:MRR:867.0,105834.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.30 105839[112:Res:53.1,105836.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.30 105841[113:Spt:105839.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 105843[113:Res:105841.0,61.1] always3(s17) || -> . % 76.04/76.30 105844[113:SSi:105843.0,78142.0,78145.0,78595.0,105143.0,105834.0] || -> . % 76.04/76.30 105845[113:Spt:105844.0,105839.0,105841.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.30 105846[113:Spt:105844.0,105839.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 105850[113:Res:105846.0,61.1] always3(s18) || -> . % 76.04/76.30 105851[113:SSi:105850.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.30 105852[111:Spt:105851.0,105142.0,105143.0] || until2p7(s17)*+ -> . % 76.04/76.30 105853[111:Spt:105851.0,105142.1] || -> node4(s16)*. % 76.04/76.30 105855[111:MRR:870.0,105853.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.30 105858[111:Res:53.1,105855.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.30 105860[112:Spt:105858.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 105862[112:Res:105860.0,61.1] always3(s16) || -> . % 76.04/76.30 105863[112:SSi:105862.0,78137.0,78141.0,78594.0,105141.0,105853.0] || -> . % 76.04/76.30 105864[112:Spt:105863.0,105858.0,105860.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.30 105865[112:Spt:105863.0,105858.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 105869[112:Res:105865.0,61.1] always3(s17) || -> . % 76.04/76.30 105870[112:SSi:105869.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.30 105871[110:Spt:105870.0,105140.0,105141.0] || until2p7(s16)*+ -> . % 76.04/76.30 105872[110:Spt:105870.0,105140.1] || -> node4(s15)*. % 76.04/76.30 105874[110:MRR:873.0,105872.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.30 105877[110:Res:53.1,105874.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.30 105882[111:Spt:105877.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 105884[111:Res:105882.0,61.1] always3(s15) || -> . % 76.04/76.30 105885[111:SSi:105884.0,78133.0,78136.0,78593.0,105139.0,105872.0] || -> . % 76.04/76.30 105886[111:Spt:105885.0,105877.0,105882.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.30 105887[111:Spt:105885.0,105877.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 105891[111:Res:105887.0,61.1] always3(s16) || -> . % 76.04/76.30 105892[111:SSi:105891.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.30 105893[109:Spt:105892.0,105138.0,105139.0] || until2p7(s15)*+ -> . % 76.04/76.30 105894[109:Spt:105892.0,105138.1] || -> node4(s14)*. % 76.04/76.30 105896[109:MRR:876.0,105894.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.30 105899[109:Res:53.1,105896.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.30 105901[110:Spt:105899.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 105903[110:Res:105901.0,61.1] always3(s14) || -> . % 76.04/76.30 105904[110:SSi:105903.0,78128.0,78132.0,78592.0,105137.0,105894.0] || -> . % 76.04/76.30 105905[110:Spt:105904.0,105899.0,105901.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.30 105906[110:Spt:105904.0,105899.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 105910[110:Res:105906.0,61.1] always3(s15) || -> . % 76.04/76.30 105911[110:SSi:105910.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.30 105912[108:Spt:105911.0,105136.0,105137.0] || until2p7(s14)*+ -> . % 76.04/76.30 105913[108:Spt:105911.0,105136.1] || -> node4(s13)*. % 76.04/76.30 105915[108:MRR:879.0,105913.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.30 105918[108:Res:53.1,105915.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.30 105920[109:Spt:105918.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 105922[109:Res:105920.0,61.1] always3(s13) || -> . % 76.04/76.30 105923[109:SSi:105922.0,78124.0,78127.0,78591.0,105135.0,105913.0] || -> . % 76.04/76.30 105924[109:Spt:105923.0,105918.0,105920.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.30 105925[109:Spt:105923.0,105918.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 105929[109:Res:105925.0,61.1] always3(s14) || -> . % 76.04/76.30 105930[109:SSi:105929.0,78128.0,78132.0,78592.0] || -> . % 76.04/76.30 105931[107:Spt:105930.0,105134.0,105135.0] || until2p7(s13)*+ -> . % 76.04/76.30 105932[107:Spt:105930.0,105134.1] || -> node4(s12)*. % 76.04/76.30 105934[107:MRR:882.0,105932.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.30 105937[107:Res:53.1,105934.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.30 105939[108:Spt:105937.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 105941[108:Res:105939.0,61.1] always3(s12) || -> . % 76.04/76.30 105942[108:SSi:105941.0,78119.0,78123.0,78590.0,105133.0,105932.0] || -> . % 76.04/76.30 105943[108:Spt:105942.0,105937.0,105939.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.30 105944[108:Spt:105942.0,105937.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 105948[108:Res:105944.0,61.1] always3(s13) || -> . % 76.04/76.30 105949[108:SSi:105948.0,78124.0,78127.0,78591.0] || -> . % 76.04/76.30 105950[106:Spt:105949.0,105132.0,105133.0] || until2p7(s12)*+ -> . % 76.04/76.30 105951[106:Spt:105949.0,105132.1] || -> node4(s11)*. % 76.04/76.30 105953[106:MRR:885.0,105951.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.30 105956[106:Res:53.1,105953.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.30 105961[107:Spt:105956.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 105963[107:Res:105961.0,61.1] always3(s11) || -> . % 76.04/76.30 105964[107:SSi:105963.0,78115.0,78118.0,78589.0,105131.0,105951.0] || -> . % 76.04/76.30 105965[107:Spt:105964.0,105956.0,105961.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.30 105966[107:Spt:105964.0,105956.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 105970[107:Res:105966.0,61.1] always3(s12) || -> . % 76.04/76.30 105971[107:SSi:105970.0,78119.0,78123.0,78590.0] || -> . % 76.04/76.30 105972[105:Spt:105971.0,105130.0,105131.0] || until2p7(s11)*+ -> . % 76.04/76.30 105973[105:Spt:105971.0,105130.1] || -> node4(s10)*. % 76.04/76.30 105975[105:MRR:888.0,105973.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.30 105978[105:Res:53.1,105975.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.30 105980[106:Spt:105978.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 105982[106:Res:105980.0,61.1] always3(s10) || -> . % 76.04/76.30 105983[106:SSi:105982.0,78110.0,78114.0,78588.0,105129.0,105973.0] || -> . % 76.04/76.30 105984[106:Spt:105983.0,105978.0,105980.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.30 105985[106:Spt:105983.0,105978.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 105989[106:Res:105985.0,61.1] always3(s11) || -> . % 76.04/76.30 105990[106:SSi:105989.0,78115.0,78118.0,78589.0] || -> . % 76.04/76.30 105991[104:Spt:105990.0,105128.0,105129.0] || until2p7(s10)*+ -> . % 76.04/76.30 105992[104:Spt:105990.0,105128.1] || -> node4(s9)*. % 76.04/76.30 105994[104:MRR:891.0,105992.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.30 105997[104:Res:53.1,105994.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.30 105999[105:Spt:105997.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 106001[105:Res:105999.0,61.1] always3(s9) || -> . % 76.04/76.30 106002[105:SSi:106001.0,78106.0,78109.0,78587.0,105127.0,105992.0] || -> . % 76.04/76.30 106003[105:Spt:106002.0,105997.0,105999.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.30 106004[105:Spt:106002.0,105997.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 106008[105:Res:106004.0,61.1] always3(s10) || -> . % 76.04/76.30 106009[105:SSi:106008.0,78110.0,78114.0,78588.0] || -> . % 76.04/76.30 106010[103:Spt:106009.0,105126.0,105127.0] || until2p7(s9)*+ -> . % 76.04/76.30 106011[103:Spt:106009.0,105126.1] || -> node4(s8)*. % 76.04/76.30 106013[103:MRR:894.0,106011.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.30 106016[103:Res:53.1,106013.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.30 106018[104:Spt:106016.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 106020[104:Res:106018.0,61.1] always3(s8) || -> . % 76.04/76.30 106021[104:SSi:106020.0,78101.0,78105.0,78586.0,105125.0,106011.0] || -> . % 76.04/76.30 106022[104:Spt:106021.0,106016.0,106018.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.30 106023[104:Spt:106021.0,106016.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 106027[104:Res:106023.0,61.1] always3(s9) || -> . % 76.04/76.30 106028[104:SSi:106027.0,78106.0,78109.0,78587.0] || -> . % 76.04/76.30 106029[102:Spt:106028.0,105124.0,105125.0] || until2p7(s8)*+ -> . % 76.04/76.30 106030[102:Spt:106028.0,105124.1] || -> node4(s7)*. % 76.04/76.30 106032[102:MRR:897.0,106030.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.30 106035[102:Res:53.1,106032.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.30 106040[103:Spt:106035.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.30 106042[103:Res:106040.0,61.1] always3(s7) || -> . % 76.04/76.30 106043[103:SSi:106042.0,78097.0,78100.0,78585.0,105123.0,106030.0] || -> . % 76.04/76.30 106044[103:Spt:106043.0,106035.0,106040.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.30 106045[103:Spt:106043.0,106035.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 106049[103:Res:106045.0,61.1] always3(s8) || -> . % 76.04/76.30 106050[103:SSi:106049.0,78101.0,78105.0,78586.0] || -> . % 76.04/76.30 106051[101:Spt:106050.0,105122.0,105123.0] || until2p7(s7)*+ -> . % 76.04/76.30 106052[101:Spt:106050.0,105122.1] || -> node4(s6)*. % 76.04/76.30 106054[101:MRR:900.0,106052.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.30 106057[101:Res:53.1,106054.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.30 106059[102:Spt:106057.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.30 106061[102:Res:106059.0,61.1] always3(s6) || -> . % 76.04/76.30 106062[102:SSi:106061.0,78093.0,78096.0,78584.0,105121.0,106052.0] || -> . % 76.04/76.30 106063[102:Spt:106062.0,106057.0,106059.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.30 106064[102:Spt:106062.0,106057.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.30 106068[102:Res:106064.0,61.1] always3(s7) || -> . % 76.04/76.30 106069[102:SSi:106068.0,78097.0,78100.0,78585.0] || -> . % 76.04/76.30 106070[100:Spt:106069.0,105120.0,105121.0] || until2p7(s6)*+ -> . % 76.04/76.30 106071[100:Spt:106069.0,105120.1] || -> node4(s5)*. % 76.04/76.30 106073[100:MRR:903.0,106071.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.30 106076[100:Res:53.1,106073.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.30 106078[101:Spt:106076.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.30 106080[101:Res:106078.0,61.1] always3(s5) || -> . % 76.04/76.30 106081[101:SSi:106080.0,78089.0,78092.0,78583.0,105119.0,106071.0] || -> . % 76.04/76.30 106082[101:Spt:106081.0,106076.0,106078.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.30 106083[101:Spt:106081.0,106076.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.30 106087[101:Res:106083.0,61.1] always3(s6) || -> . % 76.04/76.30 106088[101:SSi:106087.0,78093.0,78096.0,78584.0] || -> . % 76.04/76.30 106089[99:Spt:106088.0,105118.0,105119.0] || until2p7(s5)*+ -> . % 76.04/76.30 106090[99:Spt:106088.0,105118.1] || -> node4(s4)*. % 76.04/76.30 106092[99:MRR:906.0,106090.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.30 106095[99:Res:53.1,106092.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.30 106097[99:MRR:106095.0,105108.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.30 106099[99:Res:106097.0,61.1] always3(s5) || -> . % 76.04/76.30 106100[99:SSi:106099.0,78089.0,78092.0,78583.0] || -> . % 76.04/76.30 106101[97:Spt:106100.0,104942.0,104945.0] || trans(s49,s4)*+ -> . % 76.04/76.30 106102[97:Spt:106100.0,104942.1,104942.2] || -> trans(s49,s3) node2(s49,s2)*. % 76.04/76.30 106104[97:MRR:104944.1,106101.0] xuntil6(s49) || -> trans(s49,s3)* until2p7(s2). % 76.04/76.30 106105[98:Spt:106102.0] || -> trans(s49,s3)*. % 76.04/76.30 106106[98:Res:106105.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s3)*. % 76.04/76.30 106108[98:Res:106105.0,60.0] || -> node2(s49,s3)*. % 76.04/76.30 106109[98:SSi:106106.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s3)*. % 76.04/76.30 106110[98:Res:106108.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s3,c_busy)*. % 76.04/76.30 106264[98:SoR:106110.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s3,c_busy)*. % 76.04/76.30 106266[98:SoR:106264.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s3,c_busy)* xuntil6(s49). % 76.04/76.30 106267[98:SSi:106266.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s3,c_busy)* xuntil6(s49). % 76.04/76.30 106268[99:Spt:106267.1] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.30 106270[99:Res:106268.0,61.1] always3(s3) || -> . % 76.04/76.30 106271[99:SSi:106270.0,78081.0,78084.0,78581.0] || -> . % 76.04/76.30 106272[99:Spt:106271.0,106267.1,106268.0] || m_main_v_state(s3,c_busy)*+ -> . % 76.04/76.30 106273[99:Spt:106271.0,106267.0,106267.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 106277[99:MRR:106264.2,106272.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 106278[99:Res:53.1,106273.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 106280[99:MRR:106278.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 106281[99:MRR:106109.0,106280.0] || -> until2p7(s3)*. % 76.04/76.30 106282[99:MRR:199.0,106281.0] || -> until2p7(s4)* node4(s3). % 76.04/76.30 106283[100:Spt:106282.0] || -> until2p7(s4)*. % 76.04/76.30 106284[100:MRR:200.0,106283.0] || -> until2p7(s5)* node4(s4). % 76.04/76.30 106285[101:Spt:106284.0] || -> until2p7(s5)*. % 76.04/76.30 106286[101:MRR:201.0,106285.0] || -> until2p7(s6)* node4(s5). % 76.04/76.30 106287[102:Spt:106286.0] || -> until2p7(s6)*. % 76.04/76.30 106288[102:MRR:202.0,106287.0] || -> until2p7(s7)* node4(s6). % 76.04/76.30 106289[103:Spt:106288.0] || -> until2p7(s7)*. % 76.04/76.30 106290[103:MRR:203.0,106289.0] || -> until2p7(s8)* node4(s7). % 76.04/76.30 106291[104:Spt:106290.0] || -> until2p7(s8)*. % 76.04/76.30 106292[104:MRR:204.0,106291.0] || -> until2p7(s9)* node4(s8). % 76.04/76.30 106293[105:Spt:106292.0] || -> until2p7(s9)*. % 76.04/76.30 106294[105:MRR:205.0,106293.0] || -> until2p7(s10)* node4(s9). % 76.04/76.30 106295[106:Spt:106294.0] || -> until2p7(s10)*. % 76.04/76.30 106296[106:MRR:206.0,106295.0] || -> until2p7(s11)* node4(s10). % 76.04/76.30 106297[107:Spt:106296.0] || -> until2p7(s11)*. % 76.04/76.30 106298[107:MRR:207.0,106297.0] || -> until2p7(s12)* node4(s11). % 76.04/76.30 106299[108:Spt:106298.0] || -> until2p7(s12)*. % 76.04/76.30 106300[108:MRR:208.0,106299.0] || -> until2p7(s13)* node4(s12). % 76.04/76.30 106301[109:Spt:106300.0] || -> until2p7(s13)*. % 76.04/76.30 106302[109:MRR:209.0,106301.0] || -> until2p7(s14)* node4(s13). % 76.04/76.30 106303[110:Spt:106302.0] || -> until2p7(s14)*. % 76.04/76.30 106304[110:MRR:210.0,106303.0] || -> until2p7(s15)* node4(s14). % 76.04/76.30 106305[111:Spt:106304.0] || -> until2p7(s15)*. % 76.04/76.30 106306[111:MRR:211.0,106305.0] || -> until2p7(s16)* node4(s15). % 76.04/76.30 106307[112:Spt:106306.0] || -> until2p7(s16)*. % 76.04/76.30 106308[112:MRR:212.0,106307.0] || -> until2p7(s17)* node4(s16). % 76.04/76.30 106309[113:Spt:106308.0] || -> until2p7(s17)*. % 76.04/76.30 106310[113:MRR:213.0,106309.0] || -> until2p7(s18)* node4(s17). % 76.04/76.30 106311[114:Spt:106310.0] || -> until2p7(s18)*. % 76.04/76.30 106312[114:MRR:214.0,106311.0] || -> until2p7(s19)* node4(s18). % 76.04/76.30 106313[115:Spt:106312.0] || -> until2p7(s19)*. % 76.04/76.30 106314[115:MRR:215.0,106313.0] || -> until2p7(s20)* node4(s19). % 76.04/76.30 106315[116:Spt:106314.0] || -> until2p7(s20)*. % 76.04/76.30 106316[116:MRR:216.0,106315.0] || -> until2p7(s21)* node4(s20). % 76.04/76.30 106317[117:Spt:106316.0] || -> until2p7(s21)*. % 76.04/76.30 106318[117:MRR:217.0,106317.0] || -> until2p7(s22)* node4(s21). % 76.04/76.30 106319[118:Spt:106318.0] || -> until2p7(s22)*. % 76.04/76.30 106320[118:MRR:218.0,106319.0] || -> until2p7(s23)* node4(s22). % 76.04/76.30 106321[119:Spt:106320.0] || -> until2p7(s23)*. % 76.04/76.30 106322[119:MRR:219.0,106321.0] || -> until2p7(s24)* node4(s23). % 76.04/76.30 106323[120:Spt:106322.0] || -> until2p7(s24)*. % 76.04/76.30 106324[120:MRR:220.0,106323.0] || -> until2p7(s25)* node4(s24). % 76.04/76.30 106325[121:Spt:106324.0] || -> until2p7(s25)*. % 76.04/76.30 106326[121:MRR:221.0,106325.0] || -> until2p7(s26)* node4(s25). % 76.04/76.30 106327[122:Spt:106326.0] || -> until2p7(s26)*. % 76.04/76.30 106328[122:MRR:222.0,106327.0] || -> until2p7(s27)* node4(s26). % 76.04/76.30 106329[123:Spt:106328.0] || -> until2p7(s27)*. % 76.04/76.30 106330[123:MRR:223.0,106329.0] || -> until2p7(s28)* node4(s27). % 76.04/76.30 106331[124:Spt:106330.0] || -> until2p7(s28)*. % 76.04/76.30 106332[124:MRR:224.0,106331.0] || -> until2p7(s29)* node4(s28). % 76.04/76.30 106333[125:Spt:106332.0] || -> until2p7(s29)*. % 76.04/76.30 106334[125:MRR:225.0,106333.0] || -> until2p7(s30)* node4(s29). % 76.04/76.30 106335[126:Spt:106334.0] || -> until2p7(s30)*. % 76.04/76.30 106336[126:MRR:226.0,106335.0] || -> until2p7(s31)* node4(s30). % 76.04/76.30 106337[127:Spt:106336.0] || -> until2p7(s31)*. % 76.04/76.30 106338[127:MRR:227.0,106337.0] || -> until2p7(s32)* node4(s31). % 76.04/76.30 106339[128:Spt:106338.0] || -> until2p7(s32)*. % 76.04/76.30 106340[128:MRR:228.0,106339.0] || -> until2p7(s33)* node4(s32). % 76.04/76.30 106341[129:Spt:106340.0] || -> until2p7(s33)*. % 76.04/76.30 106342[129:MRR:229.0,106341.0] || -> until2p7(s34)* node4(s33). % 76.04/76.30 106343[130:Spt:106342.0] || -> until2p7(s34)*. % 76.04/76.30 106344[130:MRR:230.0,106343.0] || -> until2p7(s35)* node4(s34). % 76.04/76.30 106345[131:Spt:106344.0] || -> until2p7(s35)*. % 76.04/76.30 106346[131:MRR:231.0,106345.0] || -> until2p7(s36)* node4(s35). % 76.04/76.30 106347[132:Spt:106346.0] || -> until2p7(s36)*. % 76.04/76.30 106348[132:MRR:232.0,106347.0] || -> until2p7(s37)* node4(s36). % 76.04/76.30 106349[133:Spt:106348.0] || -> until2p7(s37)*. % 76.04/76.30 106350[133:MRR:235.0,106349.0] || -> until2p7(s38)* node4(s37). % 76.04/76.30 106351[134:Spt:106350.0] || -> until2p7(s38)*. % 76.04/76.30 106352[134:MRR:236.0,106351.0] || -> until2p7(s39)* node4(s38). % 76.04/76.30 106353[135:Spt:106352.0] || -> until2p7(s39)*. % 76.04/76.30 106354[135:MRR:237.0,106353.0] || -> until2p7(s40)* node4(s39). % 76.04/76.30 106355[136:Spt:106354.0] || -> until2p7(s40)*. % 76.04/76.30 106356[136:MRR:238.0,106355.0] || -> until2p7(s41)* node4(s40). % 76.04/76.30 106357[137:Spt:106356.0] || -> until2p7(s41)*. % 76.04/76.30 106358[137:MRR:239.0,106357.0] || -> until2p7(s42)* node4(s41). % 76.04/76.30 106359[138:Spt:106358.0] || -> until2p7(s42)*. % 76.04/76.30 106360[138:MRR:240.0,106359.0] || -> until2p7(s43)* node4(s42). % 76.04/76.30 106361[139:Spt:106360.0] || -> until2p7(s43)*. % 76.04/76.30 106362[139:MRR:241.0,106361.0] || -> until2p7(s44)* node4(s43). % 76.04/76.30 106363[140:Spt:106362.0] || -> until2p7(s44)*. % 76.04/76.30 106364[140:MRR:539.0,106363.0] || -> until2p7(s45)* node4(s44). % 76.04/76.30 106365[141:Spt:106364.0] || -> until2p7(s45)*. % 76.04/76.30 106366[141:MRR:544.0,106365.0] || -> until2p7(s46)* node4(s45). % 76.04/76.30 106367[142:Spt:106366.0] || -> until2p7(s46)*. % 76.04/76.30 106368[142:MRR:549.0,106367.0] || -> until2p7(s47)* node4(s46). % 76.04/76.30 106369[143:Spt:106368.0] || -> until2p7(s47)*. % 76.04/76.30 106370[143:MRR:554.0,106369.0] || -> until2p7(s48)* node4(s47). % 76.04/76.30 106371[144:Spt:106370.0] || -> until2p7(s48)*. % 76.04/76.30 106372[144:MRR:559.0,106371.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 106373[145:Spt:106372.0] || -> until2p7(s49)*. % 76.04/76.30 106374[145:MRR:194.0,106373.0] || -> node4(s49)*. % 76.04/76.30 106375[145:MRR:106277.0,106374.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 106379[145:Res:53.1,106375.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 106381[145:MRR:106379.0,78381.0] || -> . % 76.04/76.30 106382[145:Spt:106381.0,106372.0,106373.0] || until2p7(s49)*+ -> . % 76.04/76.30 106383[145:Spt:106381.0,106372.1] || -> node4(s48)*. % 76.04/76.30 106384[145:MRR:78384.0,106383.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 106387[145:Res:53.1,106384.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 106390[145:Res:106387.0,61.1] always3(s48) || -> . % 76.04/76.30 106391[145:SSi:106390.0,78281.0,78387.0,78626.0,106371.0,106383.0] || -> . % 76.04/76.30 106392[144:Spt:106391.0,106370.0,106371.0] || until2p7(s48)*+ -> . % 76.04/76.30 106393[144:Spt:106391.0,106370.1] || -> node4(s47)*. % 76.04/76.30 106395[144:MRR:777.0,106393.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.30 106407[144:Res:53.1,106395.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.30 106409[145:Spt:106407.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 106411[145:Res:106409.0,61.1] always3(s47) || -> . % 76.04/76.30 106412[145:SSi:106411.0,78277.0,78280.0,78625.0,106369.0,106393.0] || -> . % 76.04/76.30 106413[145:Spt:106412.0,106407.0,106409.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.30 106414[145:Spt:106412.0,106407.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 106418[145:Res:106414.0,61.1] always3(s48) || -> . % 76.04/76.30 106419[145:SSi:106418.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.30 106420[143:Spt:106419.0,106368.0,106369.0] || until2p7(s47)*+ -> . % 76.04/76.30 106421[143:Spt:106419.0,106368.1] || -> node4(s46)*. % 76.04/76.30 106423[143:MRR:780.0,106421.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.30 106430[143:Res:53.1,106423.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.30 106435[144:Spt:106430.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 106437[144:Res:106435.0,61.1] always3(s46) || -> . % 76.04/76.30 106438[144:SSi:106437.0,78272.0,78276.0,78624.0,106367.0,106421.0] || -> . % 76.04/76.30 106439[144:Spt:106438.0,106430.0,106435.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.30 106440[144:Spt:106438.0,106430.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 106444[144:Res:106440.0,61.1] always3(s47) || -> . % 76.04/76.30 106445[144:SSi:106444.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.30 106446[142:Spt:106445.0,106366.0,106367.0] || until2p7(s46)*+ -> . % 76.04/76.30 106447[142:Spt:106445.0,106366.1] || -> node4(s45)*. % 76.04/76.30 106449[142:MRR:783.0,106447.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.30 106452[142:Res:53.1,106449.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.30 106454[143:Spt:106452.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 106456[143:Res:106454.0,61.1] always3(s45) || -> . % 76.04/76.30 106457[143:SSi:106456.0,78268.0,78271.0,78623.0,106365.0,106447.0] || -> . % 76.04/76.30 106458[143:Spt:106457.0,106452.0,106454.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.30 106459[143:Spt:106457.0,106452.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 106463[143:Res:106459.0,61.1] always3(s46) || -> . % 76.04/76.30 106464[143:SSi:106463.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.30 106465[141:Spt:106464.0,106364.0,106365.0] || until2p7(s45)*+ -> . % 76.04/76.30 106466[141:Spt:106464.0,106364.1] || -> node4(s44)*. % 76.04/76.30 106468[141:MRR:786.0,106466.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.30 106471[141:Res:53.1,106468.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.30 106473[142:Spt:106471.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 106475[142:Res:106473.0,61.1] always3(s44) || -> . % 76.04/76.30 106476[142:SSi:106475.0,78263.0,78267.0,78622.0,106363.0,106466.0] || -> . % 76.04/76.30 106477[142:Spt:106476.0,106471.0,106473.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.30 106478[142:Spt:106476.0,106471.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 106482[142:Res:106478.0,61.1] always3(s45) || -> . % 76.04/76.30 106483[142:SSi:106482.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.30 106484[140:Spt:106483.0,106362.0,106363.0] || until2p7(s44)*+ -> . % 76.04/76.30 106485[140:Spt:106483.0,106362.1] || -> node4(s43)*. % 76.04/76.30 106487[140:MRR:789.0,106485.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.30 106490[140:Res:53.1,106487.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.30 106492[141:Spt:106490.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 106494[141:Res:106492.0,61.1] always3(s43) || -> . % 76.04/76.30 106495[141:SSi:106494.0,78259.0,78262.0,78621.0,106361.0,106485.0] || -> . % 76.04/76.30 106496[141:Spt:106495.0,106490.0,106492.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.30 106497[141:Spt:106495.0,106490.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 106501[141:Res:106497.0,61.1] always3(s44) || -> . % 76.04/76.30 106502[141:SSi:106501.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.30 106503[139:Spt:106502.0,106360.0,106361.0] || until2p7(s43)*+ -> . % 76.04/76.30 106504[139:Spt:106502.0,106360.1] || -> node4(s42)*. % 76.04/76.30 106506[139:MRR:792.0,106504.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.30 106509[139:Res:53.1,106506.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.30 106514[140:Spt:106509.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 106516[140:Res:106514.0,61.1] always3(s42) || -> . % 76.04/76.30 106517[140:SSi:106516.0,78254.0,78258.0,78620.0,106359.0,106504.0] || -> . % 76.04/76.30 106518[140:Spt:106517.0,106509.0,106514.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.30 106519[140:Spt:106517.0,106509.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 106523[140:Res:106519.0,61.1] always3(s43) || -> . % 76.04/76.30 106524[140:SSi:106523.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.30 106525[138:Spt:106524.0,106358.0,106359.0] || until2p7(s42)*+ -> . % 76.04/76.30 106526[138:Spt:106524.0,106358.1] || -> node4(s41)*. % 76.04/76.30 106528[138:MRR:795.0,106526.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.30 106531[138:Res:53.1,106528.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.30 106533[139:Spt:106531.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 106535[139:Res:106533.0,61.1] always3(s41) || -> . % 76.04/76.30 106536[139:SSi:106535.0,78250.0,78253.0,78619.0,106357.0,106526.0] || -> . % 76.04/76.30 106537[139:Spt:106536.0,106531.0,106533.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.30 106538[139:Spt:106536.0,106531.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 106542[139:Res:106538.0,61.1] always3(s42) || -> . % 76.04/76.30 106543[139:SSi:106542.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.30 106544[137:Spt:106543.0,106356.0,106357.0] || until2p7(s41)*+ -> . % 76.04/76.30 106545[137:Spt:106543.0,106356.1] || -> node4(s40)*. % 76.04/76.30 106547[137:MRR:798.0,106545.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.30 106550[137:Res:53.1,106547.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.30 106552[138:Spt:106550.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 106554[138:Res:106552.0,61.1] always3(s40) || -> . % 76.04/76.30 106555[138:SSi:106554.0,78245.0,78249.0,78618.0,106355.0,106545.0] || -> . % 76.04/76.30 106556[138:Spt:106555.0,106550.0,106552.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.30 106557[138:Spt:106555.0,106550.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 106561[138:Res:106557.0,61.1] always3(s41) || -> . % 76.04/76.30 106562[138:SSi:106561.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.30 106563[136:Spt:106562.0,106354.0,106355.0] || until2p7(s40)*+ -> . % 76.04/76.30 106564[136:Spt:106562.0,106354.1] || -> node4(s39)*. % 76.04/76.30 106566[136:MRR:801.0,106564.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.30 106569[136:Res:53.1,106566.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.30 106571[137:Spt:106569.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 106573[137:Res:106571.0,61.1] always3(s39) || -> . % 76.04/76.30 106574[137:SSi:106573.0,78241.0,78244.0,78617.0,106353.0,106564.0] || -> . % 76.04/76.30 106575[137:Spt:106574.0,106569.0,106571.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.30 106576[137:Spt:106574.0,106569.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 106580[137:Res:106576.0,61.1] always3(s40) || -> . % 76.04/76.30 106581[137:SSi:106580.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.30 106582[135:Spt:106581.0,106352.0,106353.0] || until2p7(s39)*+ -> . % 76.04/76.30 106583[135:Spt:106581.0,106352.1] || -> node4(s38)*. % 76.04/76.30 106585[135:MRR:804.0,106583.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.30 106588[135:Res:53.1,106585.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.30 106593[136:Spt:106588.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 106595[136:Res:106593.0,61.1] always3(s38) || -> . % 76.04/76.30 106596[136:SSi:106595.0,78236.0,78240.0,78616.0,106351.0,106583.0] || -> . % 76.04/76.30 106597[136:Spt:106596.0,106588.0,106593.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.30 106598[136:Spt:106596.0,106588.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 106602[136:Res:106598.0,61.1] always3(s39) || -> . % 76.04/76.30 106603[136:SSi:106602.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.30 106604[134:Spt:106603.0,106350.0,106351.0] || until2p7(s38)*+ -> . % 76.04/76.30 106605[134:Spt:106603.0,106350.1] || -> node4(s37)*. % 76.04/76.30 106607[134:MRR:807.0,106605.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.30 106610[134:Res:53.1,106607.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.30 106612[135:Spt:106610.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 106614[135:Res:106612.0,61.1] always3(s37) || -> . % 76.04/76.30 106615[135:SSi:106614.0,78232.0,78235.0,78615.0,106349.0,106605.0] || -> . % 76.04/76.30 106616[135:Spt:106615.0,106610.0,106612.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.30 106617[135:Spt:106615.0,106610.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 106621[135:Res:106617.0,61.1] always3(s38) || -> . % 76.04/76.30 106622[135:SSi:106621.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.30 106623[133:Spt:106622.0,106348.0,106349.0] || until2p7(s37)*+ -> . % 76.04/76.30 106624[133:Spt:106622.0,106348.1] || -> node4(s36)*. % 76.04/76.30 106626[133:MRR:810.0,106624.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.30 106629[133:Res:53.1,106626.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.30 106631[134:Spt:106629.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 106633[134:Res:106631.0,61.1] always3(s36) || -> . % 76.04/76.30 106634[134:SSi:106633.0,78227.0,78231.0,78614.0,106347.0,106624.0] || -> . % 76.04/76.30 106635[134:Spt:106634.0,106629.0,106631.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.30 106636[134:Spt:106634.0,106629.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 106640[134:Res:106636.0,61.1] always3(s37) || -> . % 76.04/76.30 106641[134:SSi:106640.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.30 106642[132:Spt:106641.0,106346.0,106347.0] || until2p7(s36)*+ -> . % 76.04/76.30 106643[132:Spt:106641.0,106346.1] || -> node4(s35)*. % 76.04/76.30 106645[132:MRR:813.0,106643.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.30 106648[132:Res:53.1,106645.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.30 106650[133:Spt:106648.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 106652[133:Res:106650.0,61.1] always3(s35) || -> . % 76.04/76.30 106653[133:SSi:106652.0,78223.0,78226.0,78613.0,106345.0,106643.0] || -> . % 76.04/76.30 106654[133:Spt:106653.0,106648.0,106650.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.30 106655[133:Spt:106653.0,106648.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 106659[133:Res:106655.0,61.1] always3(s36) || -> . % 76.04/76.30 106660[133:SSi:106659.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.30 106661[131:Spt:106660.0,106344.0,106345.0] || until2p7(s35)*+ -> . % 76.04/76.30 106662[131:Spt:106660.0,106344.1] || -> node4(s34)*. % 76.04/76.30 106664[131:MRR:816.0,106662.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.30 106667[131:Res:53.1,106664.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.30 106672[132:Spt:106667.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 106674[132:Res:106672.0,61.1] always3(s34) || -> . % 76.04/76.30 106675[132:SSi:106674.0,78218.0,78222.0,78612.0,106343.0,106662.0] || -> . % 76.04/76.30 106676[132:Spt:106675.0,106667.0,106672.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.30 106677[132:Spt:106675.0,106667.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 106681[132:Res:106677.0,61.1] always3(s35) || -> . % 76.04/76.30 106682[132:SSi:106681.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.30 106683[130:Spt:106682.0,106342.0,106343.0] || until2p7(s34)*+ -> . % 76.04/76.30 106684[130:Spt:106682.0,106342.1] || -> node4(s33)*. % 76.04/76.30 106686[130:MRR:819.0,106684.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.30 106689[130:Res:53.1,106686.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.30 106691[131:Spt:106689.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 106693[131:Res:106691.0,61.1] always3(s33) || -> . % 76.04/76.30 106694[131:SSi:106693.0,78214.0,78217.0,78611.0,106341.0,106684.0] || -> . % 76.04/76.30 106695[131:Spt:106694.0,106689.0,106691.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.30 106696[131:Spt:106694.0,106689.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 106700[131:Res:106696.0,61.1] always3(s34) || -> . % 76.04/76.30 106701[131:SSi:106700.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.30 106702[129:Spt:106701.0,106340.0,106341.0] || until2p7(s33)*+ -> . % 76.04/76.30 106703[129:Spt:106701.0,106340.1] || -> node4(s32)*. % 76.04/76.30 106705[129:MRR:822.0,106703.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.30 106708[129:Res:53.1,106705.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.30 106710[130:Spt:106708.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 106712[130:Res:106710.0,61.1] always3(s32) || -> . % 76.04/76.30 106713[130:SSi:106712.0,78209.0,78213.0,78610.0,106339.0,106703.0] || -> . % 76.04/76.30 106714[130:Spt:106713.0,106708.0,106710.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.30 106715[130:Spt:106713.0,106708.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 106719[130:Res:106715.0,61.1] always3(s33) || -> . % 76.04/76.30 106720[130:SSi:106719.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.30 106721[128:Spt:106720.0,106338.0,106339.0] || until2p7(s32)*+ -> . % 76.04/76.30 106722[128:Spt:106720.0,106338.1] || -> node4(s31)*. % 76.04/76.30 106724[128:MRR:825.0,106722.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.30 106727[128:Res:53.1,106724.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.30 106729[129:Spt:106727.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 106731[129:Res:106729.0,61.1] always3(s31) || -> . % 76.04/76.30 106732[129:SSi:106731.0,78205.0,78208.0,78609.0,106337.0,106722.0] || -> . % 76.04/76.30 106733[129:Spt:106732.0,106727.0,106729.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.30 106734[129:Spt:106732.0,106727.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 106738[129:Res:106734.0,61.1] always3(s32) || -> . % 76.04/76.30 106739[129:SSi:106738.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.30 106740[127:Spt:106739.0,106336.0,106337.0] || until2p7(s31)*+ -> . % 76.04/76.30 106741[127:Spt:106739.0,106336.1] || -> node4(s30)*. % 76.04/76.30 106743[127:MRR:828.0,106741.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.30 106746[127:Res:53.1,106743.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.30 106751[128:Spt:106746.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 106753[128:Res:106751.0,61.1] always3(s30) || -> . % 76.04/76.30 106754[128:SSi:106753.0,78200.0,78204.0,78608.0,106335.0,106741.0] || -> . % 76.04/76.30 106755[128:Spt:106754.0,106746.0,106751.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.30 106756[128:Spt:106754.0,106746.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 106760[128:Res:106756.0,61.1] always3(s31) || -> . % 76.04/76.30 106761[128:SSi:106760.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.30 106762[126:Spt:106761.0,106334.0,106335.0] || until2p7(s30)*+ -> . % 76.04/76.30 106763[126:Spt:106761.0,106334.1] || -> node4(s29)*. % 76.04/76.30 106765[126:MRR:831.0,106763.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.30 106768[126:Res:53.1,106765.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.30 106770[127:Spt:106768.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 106772[127:Res:106770.0,61.1] always3(s29) || -> . % 76.04/76.30 106773[127:SSi:106772.0,78196.0,78199.0,78607.0,106333.0,106763.0] || -> . % 76.04/76.30 106774[127:Spt:106773.0,106768.0,106770.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.30 106775[127:Spt:106773.0,106768.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 106779[127:Res:106775.0,61.1] always3(s30) || -> . % 76.04/76.30 106780[127:SSi:106779.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.30 106781[125:Spt:106780.0,106332.0,106333.0] || until2p7(s29)*+ -> . % 76.04/76.30 106782[125:Spt:106780.0,106332.1] || -> node4(s28)*. % 76.04/76.30 106784[125:MRR:834.0,106782.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.30 106787[125:Res:53.1,106784.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.30 106789[126:Spt:106787.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 106791[126:Res:106789.0,61.1] always3(s28) || -> . % 76.04/76.30 106792[126:SSi:106791.0,78191.0,78195.0,78606.0,106331.0,106782.0] || -> . % 76.04/76.30 106793[126:Spt:106792.0,106787.0,106789.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.30 106794[126:Spt:106792.0,106787.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 106798[126:Res:106794.0,61.1] always3(s29) || -> . % 76.04/76.30 106799[126:SSi:106798.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.30 106800[124:Spt:106799.0,106330.0,106331.0] || until2p7(s28)*+ -> . % 76.04/76.30 106801[124:Spt:106799.0,106330.1] || -> node4(s27)*. % 76.04/76.30 106803[124:MRR:837.0,106801.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.30 106806[124:Res:53.1,106803.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.30 106808[125:Spt:106806.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 106810[125:Res:106808.0,61.1] always3(s27) || -> . % 76.04/76.30 106811[125:SSi:106810.0,78187.0,78190.0,78605.0,106329.0,106801.0] || -> . % 76.04/76.30 106812[125:Spt:106811.0,106806.0,106808.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.30 106813[125:Spt:106811.0,106806.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 106817[125:Res:106813.0,61.1] always3(s28) || -> . % 76.04/76.30 106818[125:SSi:106817.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.30 106819[123:Spt:106818.0,106328.0,106329.0] || until2p7(s27)*+ -> . % 76.04/76.30 106820[123:Spt:106818.0,106328.1] || -> node4(s26)*. % 76.04/76.30 106822[123:MRR:840.0,106820.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.30 106825[123:Res:53.1,106822.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.30 106830[124:Spt:106825.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 106832[124:Res:106830.0,61.1] always3(s26) || -> . % 76.04/76.30 106833[124:SSi:106832.0,78182.0,78186.0,78604.0,106327.0,106820.0] || -> . % 76.04/76.30 106834[124:Spt:106833.0,106825.0,106830.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.30 106835[124:Spt:106833.0,106825.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 106839[124:Res:106835.0,61.1] always3(s27) || -> . % 76.04/76.30 106840[124:SSi:106839.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.30 106841[122:Spt:106840.0,106326.0,106327.0] || until2p7(s26)*+ -> . % 76.04/76.30 106842[122:Spt:106840.0,106326.1] || -> node4(s25)*. % 76.04/76.30 106844[122:MRR:843.0,106842.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.30 106847[122:Res:53.1,106844.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.30 106849[123:Spt:106847.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 106851[123:Res:106849.0,61.1] always3(s25) || -> . % 76.04/76.30 106852[123:SSi:106851.0,78178.0,78181.0,78603.0,106325.0,106842.0] || -> . % 76.04/76.30 106853[123:Spt:106852.0,106847.0,106849.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.30 106854[123:Spt:106852.0,106847.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 106858[123:Res:106854.0,61.1] always3(s26) || -> . % 76.04/76.30 106859[123:SSi:106858.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.30 106860[121:Spt:106859.0,106324.0,106325.0] || until2p7(s25)*+ -> . % 76.04/76.30 106861[121:Spt:106859.0,106324.1] || -> node4(s24)*. % 76.04/76.30 106863[121:MRR:846.0,106861.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.30 106866[121:Res:53.1,106863.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.30 106868[122:Spt:106866.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 106870[122:Res:106868.0,61.1] always3(s24) || -> . % 76.04/76.30 106871[122:SSi:106870.0,78173.0,78177.0,78602.0,106323.0,106861.0] || -> . % 76.04/76.30 106872[122:Spt:106871.0,106866.0,106868.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.30 106873[122:Spt:106871.0,106866.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 106877[122:Res:106873.0,61.1] always3(s25) || -> . % 76.04/76.30 106878[122:SSi:106877.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.30 106879[120:Spt:106878.0,106322.0,106323.0] || until2p7(s24)*+ -> . % 76.04/76.30 106880[120:Spt:106878.0,106322.1] || -> node4(s23)*. % 76.04/76.30 106882[120:MRR:849.0,106880.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.30 106885[120:Res:53.1,106882.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.30 106887[121:Spt:106885.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 106889[121:Res:106887.0,61.1] always3(s23) || -> . % 76.04/76.30 106890[121:SSi:106889.0,78169.0,78172.0,78601.0,106321.0,106880.0] || -> . % 76.04/76.30 106891[121:Spt:106890.0,106885.0,106887.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.30 106892[121:Spt:106890.0,106885.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 106896[121:Res:106892.0,61.1] always3(s24) || -> . % 76.04/76.30 106897[121:SSi:106896.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.30 106898[119:Spt:106897.0,106320.0,106321.0] || until2p7(s23)*+ -> . % 76.04/76.30 106899[119:Spt:106897.0,106320.1] || -> node4(s22)*. % 76.04/76.30 106901[119:MRR:852.0,106899.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.30 106904[119:Res:53.1,106901.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.30 106909[120:Spt:106904.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 106911[120:Res:106909.0,61.1] always3(s22) || -> . % 76.04/76.30 106912[120:SSi:106911.0,78164.0,78168.0,78600.0,106319.0,106899.0] || -> . % 76.04/76.30 106913[120:Spt:106912.0,106904.0,106909.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.30 106914[120:Spt:106912.0,106904.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 106918[120:Res:106914.0,61.1] always3(s23) || -> . % 76.04/76.30 106919[120:SSi:106918.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.30 106920[118:Spt:106919.0,106318.0,106319.0] || until2p7(s22)*+ -> . % 76.04/76.30 106921[118:Spt:106919.0,106318.1] || -> node4(s21)*. % 76.04/76.30 106923[118:MRR:855.0,106921.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.30 106926[118:Res:53.1,106923.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.30 106928[119:Spt:106926.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 106930[119:Res:106928.0,61.1] always3(s21) || -> . % 76.04/76.30 106931[119:SSi:106930.0,78160.0,78163.0,78599.0,106317.0,106921.0] || -> . % 76.04/76.30 106932[119:Spt:106931.0,106926.0,106928.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.30 106933[119:Spt:106931.0,106926.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 106937[119:Res:106933.0,61.1] always3(s22) || -> . % 76.04/76.30 106938[119:SSi:106937.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.30 106939[117:Spt:106938.0,106316.0,106317.0] || until2p7(s21)*+ -> . % 76.04/76.30 106940[117:Spt:106938.0,106316.1] || -> node4(s20)*. % 76.04/76.30 106942[117:MRR:858.0,106940.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.30 106945[117:Res:53.1,106942.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.30 106947[118:Spt:106945.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 106949[118:Res:106947.0,61.1] always3(s20) || -> . % 76.04/76.30 106950[118:SSi:106949.0,78155.0,78159.0,78598.0,106315.0,106940.0] || -> . % 76.04/76.30 106951[118:Spt:106950.0,106945.0,106947.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.30 106952[118:Spt:106950.0,106945.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 106956[118:Res:106952.0,61.1] always3(s21) || -> . % 76.04/76.30 106957[118:SSi:106956.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.30 106958[116:Spt:106957.0,106314.0,106315.0] || until2p7(s20)*+ -> . % 76.04/76.30 106959[116:Spt:106957.0,106314.1] || -> node4(s19)*. % 76.04/76.30 106961[116:MRR:861.0,106959.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.30 106964[116:Res:53.1,106961.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.30 106966[117:Spt:106964.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 106968[117:Res:106966.0,61.1] always3(s19) || -> . % 76.04/76.30 106969[117:SSi:106968.0,78151.0,78154.0,78597.0,106313.0,106959.0] || -> . % 76.04/76.30 106970[117:Spt:106969.0,106964.0,106966.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.30 106971[117:Spt:106969.0,106964.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 106975[117:Res:106971.0,61.1] always3(s20) || -> . % 76.04/76.30 106976[117:SSi:106975.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.30 106977[115:Spt:106976.0,106312.0,106313.0] || until2p7(s19)*+ -> . % 76.04/76.30 106978[115:Spt:106976.0,106312.1] || -> node4(s18)*. % 76.04/76.30 106980[115:MRR:864.0,106978.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.30 106983[115:Res:53.1,106980.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.30 106988[116:Spt:106983.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 106990[116:Res:106988.0,61.1] always3(s18) || -> . % 76.04/76.30 106991[116:SSi:106990.0,78146.0,78150.0,78596.0,106311.0,106978.0] || -> . % 76.04/76.30 106992[116:Spt:106991.0,106983.0,106988.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.30 106993[116:Spt:106991.0,106983.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 106997[116:Res:106993.0,61.1] always3(s19) || -> . % 76.04/76.30 106998[116:SSi:106997.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.30 106999[114:Spt:106998.0,106310.0,106311.0] || until2p7(s18)*+ -> . % 76.04/76.30 107000[114:Spt:106998.0,106310.1] || -> node4(s17)*. % 76.04/76.30 107002[114:MRR:867.0,107000.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.30 107005[114:Res:53.1,107002.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.30 107007[115:Spt:107005.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 107009[115:Res:107007.0,61.1] always3(s17) || -> . % 76.04/76.30 107010[115:SSi:107009.0,78142.0,78145.0,78595.0,106309.0,107000.0] || -> . % 76.04/76.30 107011[115:Spt:107010.0,107005.0,107007.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.30 107012[115:Spt:107010.0,107005.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 107016[115:Res:107012.0,61.1] always3(s18) || -> . % 76.04/76.30 107017[115:SSi:107016.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.30 107018[113:Spt:107017.0,106308.0,106309.0] || until2p7(s17)*+ -> . % 76.04/76.30 107019[113:Spt:107017.0,106308.1] || -> node4(s16)*. % 76.04/76.30 107021[113:MRR:870.0,107019.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.30 107024[113:Res:53.1,107021.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.30 107026[114:Spt:107024.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 107028[114:Res:107026.0,61.1] always3(s16) || -> . % 76.04/76.30 107029[114:SSi:107028.0,78137.0,78141.0,78594.0,106307.0,107019.0] || -> . % 76.04/76.30 107030[114:Spt:107029.0,107024.0,107026.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.30 107031[114:Spt:107029.0,107024.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 107035[114:Res:107031.0,61.1] always3(s17) || -> . % 76.04/76.30 107036[114:SSi:107035.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.30 107037[112:Spt:107036.0,106306.0,106307.0] || until2p7(s16)*+ -> . % 76.04/76.30 107038[112:Spt:107036.0,106306.1] || -> node4(s15)*. % 76.04/76.30 107040[112:MRR:873.0,107038.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.30 107043[112:Res:53.1,107040.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.30 107045[113:Spt:107043.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 107047[113:Res:107045.0,61.1] always3(s15) || -> . % 76.04/76.30 107048[113:SSi:107047.0,78133.0,78136.0,78593.0,106305.0,107038.0] || -> . % 76.04/76.30 107049[113:Spt:107048.0,107043.0,107045.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.30 107050[113:Spt:107048.0,107043.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 107054[113:Res:107050.0,61.1] always3(s16) || -> . % 76.04/76.30 107055[113:SSi:107054.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.30 107056[111:Spt:107055.0,106304.0,106305.0] || until2p7(s15)*+ -> . % 76.04/76.30 107057[111:Spt:107055.0,106304.1] || -> node4(s14)*. % 76.04/76.30 107059[111:MRR:876.0,107057.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.30 107062[111:Res:53.1,107059.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.30 107067[112:Spt:107062.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 107069[112:Res:107067.0,61.1] always3(s14) || -> . % 76.04/76.30 107070[112:SSi:107069.0,78128.0,78132.0,78592.0,106303.0,107057.0] || -> . % 76.04/76.30 107071[112:Spt:107070.0,107062.0,107067.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.30 107072[112:Spt:107070.0,107062.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 107076[112:Res:107072.0,61.1] always3(s15) || -> . % 76.04/76.30 107077[112:SSi:107076.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.30 107078[110:Spt:107077.0,106302.0,106303.0] || until2p7(s14)*+ -> . % 76.04/76.30 107079[110:Spt:107077.0,106302.1] || -> node4(s13)*. % 76.04/76.30 107081[110:MRR:879.0,107079.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.30 107084[110:Res:53.1,107081.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.30 107086[111:Spt:107084.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 107088[111:Res:107086.0,61.1] always3(s13) || -> . % 76.04/76.30 107089[111:SSi:107088.0,78124.0,78127.0,78591.0,106301.0,107079.0] || -> . % 76.04/76.30 107090[111:Spt:107089.0,107084.0,107086.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.30 107091[111:Spt:107089.0,107084.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 107095[111:Res:107091.0,61.1] always3(s14) || -> . % 76.04/76.30 107096[111:SSi:107095.0,78128.0,78132.0,78592.0] || -> . % 76.04/76.30 107097[109:Spt:107096.0,106300.0,106301.0] || until2p7(s13)*+ -> . % 76.04/76.30 107098[109:Spt:107096.0,106300.1] || -> node4(s12)*. % 76.04/76.30 107100[109:MRR:882.0,107098.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.30 107103[109:Res:53.1,107100.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.30 107105[110:Spt:107103.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 107107[110:Res:107105.0,61.1] always3(s12) || -> . % 76.04/76.30 107108[110:SSi:107107.0,78119.0,78123.0,78590.0,106299.0,107098.0] || -> . % 76.04/76.30 107109[110:Spt:107108.0,107103.0,107105.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.30 107110[110:Spt:107108.0,107103.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 107114[110:Res:107110.0,61.1] always3(s13) || -> . % 76.04/76.30 107115[110:SSi:107114.0,78124.0,78127.0,78591.0] || -> . % 76.04/76.30 107116[108:Spt:107115.0,106298.0,106299.0] || until2p7(s12)*+ -> . % 76.04/76.30 107117[108:Spt:107115.0,106298.1] || -> node4(s11)*. % 76.04/76.30 107119[108:MRR:885.0,107117.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.30 107122[108:Res:53.1,107119.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.30 107124[109:Spt:107122.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 107126[109:Res:107124.0,61.1] always3(s11) || -> . % 76.04/76.30 107127[109:SSi:107126.0,78115.0,78118.0,78589.0,106297.0,107117.0] || -> . % 76.04/76.30 107128[109:Spt:107127.0,107122.0,107124.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.30 107129[109:Spt:107127.0,107122.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 107133[109:Res:107129.0,61.1] always3(s12) || -> . % 76.04/76.30 107134[109:SSi:107133.0,78119.0,78123.0,78590.0] || -> . % 76.04/76.30 107135[107:Spt:107134.0,106296.0,106297.0] || until2p7(s11)*+ -> . % 76.04/76.30 107136[107:Spt:107134.0,106296.1] || -> node4(s10)*. % 76.04/76.30 107138[107:MRR:888.0,107136.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.30 107141[107:Res:53.1,107138.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.30 107146[108:Spt:107141.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 107148[108:Res:107146.0,61.1] always3(s10) || -> . % 76.04/76.30 107149[108:SSi:107148.0,78110.0,78114.0,78588.0,106295.0,107136.0] || -> . % 76.04/76.30 107150[108:Spt:107149.0,107141.0,107146.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.30 107151[108:Spt:107149.0,107141.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 107155[108:Res:107151.0,61.1] always3(s11) || -> . % 76.04/76.30 107156[108:SSi:107155.0,78115.0,78118.0,78589.0] || -> . % 76.04/76.30 107157[106:Spt:107156.0,106294.0,106295.0] || until2p7(s10)*+ -> . % 76.04/76.30 107158[106:Spt:107156.0,106294.1] || -> node4(s9)*. % 76.04/76.30 107160[106:MRR:891.0,107158.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.30 107163[106:Res:53.1,107160.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.30 107165[107:Spt:107163.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 107167[107:Res:107165.0,61.1] always3(s9) || -> . % 76.04/76.30 107168[107:SSi:107167.0,78106.0,78109.0,78587.0,106293.0,107158.0] || -> . % 76.04/76.30 107169[107:Spt:107168.0,107163.0,107165.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.30 107170[107:Spt:107168.0,107163.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 107174[107:Res:107170.0,61.1] always3(s10) || -> . % 76.04/76.30 107175[107:SSi:107174.0,78110.0,78114.0,78588.0] || -> . % 76.04/76.30 107176[105:Spt:107175.0,106292.0,106293.0] || until2p7(s9)*+ -> . % 76.04/76.30 107177[105:Spt:107175.0,106292.1] || -> node4(s8)*. % 76.04/76.30 107179[105:MRR:894.0,107177.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.30 107182[105:Res:53.1,107179.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.30 107184[106:Spt:107182.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 107186[106:Res:107184.0,61.1] always3(s8) || -> . % 76.04/76.30 107187[106:SSi:107186.0,78101.0,78105.0,78586.0,106291.0,107177.0] || -> . % 76.04/76.30 107188[106:Spt:107187.0,107182.0,107184.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.30 107189[106:Spt:107187.0,107182.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 107193[106:Res:107189.0,61.1] always3(s9) || -> . % 76.04/76.30 107194[106:SSi:107193.0,78106.0,78109.0,78587.0] || -> . % 76.04/76.30 107195[104:Spt:107194.0,106290.0,106291.0] || until2p7(s8)*+ -> . % 76.04/76.30 107196[104:Spt:107194.0,106290.1] || -> node4(s7)*. % 76.04/76.30 107198[104:MRR:897.0,107196.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.30 107201[104:Res:53.1,107198.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.30 107203[105:Spt:107201.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.30 107205[105:Res:107203.0,61.1] always3(s7) || -> . % 76.04/76.30 107206[105:SSi:107205.0,78097.0,78100.0,78585.0,106289.0,107196.0] || -> . % 76.04/76.30 107207[105:Spt:107206.0,107201.0,107203.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.30 107208[105:Spt:107206.0,107201.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 107212[105:Res:107208.0,61.1] always3(s8) || -> . % 76.04/76.30 107213[105:SSi:107212.0,78101.0,78105.0,78586.0] || -> . % 76.04/76.30 107214[103:Spt:107213.0,106288.0,106289.0] || until2p7(s7)*+ -> . % 76.04/76.30 107215[103:Spt:107213.0,106288.1] || -> node4(s6)*. % 76.04/76.30 107217[103:MRR:900.0,107215.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.30 107220[103:Res:53.1,107217.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.30 107225[104:Spt:107220.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.30 107227[104:Res:107225.0,61.1] always3(s6) || -> . % 76.04/76.30 107228[104:SSi:107227.0,78093.0,78096.0,78584.0,106287.0,107215.0] || -> . % 76.04/76.30 107229[104:Spt:107228.0,107220.0,107225.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.30 107230[104:Spt:107228.0,107220.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.30 107234[104:Res:107230.0,61.1] always3(s7) || -> . % 76.04/76.30 107235[104:SSi:107234.0,78097.0,78100.0,78585.0] || -> . % 76.04/76.30 107236[102:Spt:107235.0,106286.0,106287.0] || until2p7(s6)*+ -> . % 76.04/76.30 107237[102:Spt:107235.0,106286.1] || -> node4(s5)*. % 76.04/76.30 107239[102:MRR:903.0,107237.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.30 107242[102:Res:53.1,107239.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.30 107244[103:Spt:107242.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.30 107246[103:Res:107244.0,61.1] always3(s5) || -> . % 76.04/76.30 107247[103:SSi:107246.0,78089.0,78092.0,78583.0,106285.0,107237.0] || -> . % 76.04/76.30 107248[103:Spt:107247.0,107242.0,107244.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.30 107249[103:Spt:107247.0,107242.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.30 107253[103:Res:107249.0,61.1] always3(s6) || -> . % 76.04/76.30 107254[103:SSi:107253.0,78093.0,78096.0,78584.0] || -> . % 76.04/76.30 107255[101:Spt:107254.0,106284.0,106285.0] || until2p7(s5)*+ -> . % 76.04/76.30 107256[101:Spt:107254.0,106284.1] || -> node4(s4)*. % 76.04/76.30 107258[101:MRR:906.0,107256.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.30 107261[101:Res:53.1,107258.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.30 107263[102:Spt:107261.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.30 107265[102:Res:107263.0,61.1] always3(s4) || -> . % 76.04/76.30 107266[102:SSi:107265.0,78085.0,78088.0,78582.0,106283.0,107256.0] || -> . % 76.04/76.30 107267[102:Spt:107266.0,107261.0,107263.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.30 107268[102:Spt:107266.0,107261.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.30 107272[102:Res:107268.0,61.1] always3(s5) || -> . % 76.04/76.30 107273[102:SSi:107272.0,78089.0,78092.0,78583.0] || -> . % 76.04/76.30 107274[100:Spt:107273.0,106282.0,106283.0] || until2p7(s4)*+ -> . % 76.04/76.30 107275[100:Spt:107273.0,106282.1] || -> node4(s3)*. % 76.04/76.30 107277[100:MRR:909.0,107275.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.30 107280[100:Res:53.1,107277.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.30 107282[100:MRR:107280.0,106272.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.30 107284[100:Res:107282.0,61.1] always3(s4) || -> . % 76.04/76.30 107285[100:SSi:107284.0,78085.0,78088.0,78582.0] || -> . % 76.04/76.30 107286[98:Spt:107285.0,106102.0,106105.0] || trans(s49,s3)*+ -> . % 76.04/76.30 107287[98:Spt:107285.0,106102.1] || -> node2(s49,s2)*. % 76.04/76.30 107289[98:MRR:106104.1,107286.0] xuntil6(s49) || -> until2p7(s2)*. % 76.04/76.30 107290[98:Res:107287.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s2,c_busy)*. % 76.04/76.30 107451[98:SoR:107290.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s2,c_busy)*. % 76.04/76.30 107453[98:SoR:107451.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s2,c_busy)* xuntil6(s49). % 76.04/76.30 107454[98:SSi:107453.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s2,c_busy)* xuntil6(s49). % 76.04/76.30 107455[99:Spt:107454.1] || -> m_main_v_state(s2,c_busy)*. % 76.04/76.30 107457[99:Res:107455.0,61.1] always3(s2) || -> . % 76.04/76.30 107458[99:SSi:107457.0,78074.0,78080.0,78580.0] || -> . % 76.04/76.30 107459[99:Spt:107458.0,107454.1,107455.0] || m_main_v_state(s2,c_busy)*+ -> . % 76.04/76.30 107460[99:Spt:107458.0,107454.0,107454.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 107463[99:MRR:107451.2,107459.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 107464[99:Res:53.1,107460.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 107466[99:MRR:107464.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 107467[99:MRR:107289.0,107466.0] || -> until2p7(s2)*. % 76.04/76.30 107468[99:MRR:198.0,107467.0] || -> until2p7(s3)* node4(s2). % 76.04/76.30 107469[100:Spt:107468.0] || -> until2p7(s3)*. % 76.04/76.30 107470[100:MRR:199.0,107469.0] || -> until2p7(s4)* node4(s3). % 76.04/76.30 107471[101:Spt:107470.0] || -> until2p7(s4)*. % 76.04/76.30 107472[101:MRR:200.0,107471.0] || -> until2p7(s5)* node4(s4). % 76.04/76.30 107473[102:Spt:107472.0] || -> until2p7(s5)*. % 76.04/76.30 107474[102:MRR:201.0,107473.0] || -> until2p7(s6)* node4(s5). % 76.04/76.30 107475[103:Spt:107474.0] || -> until2p7(s6)*. % 76.04/76.30 107476[103:MRR:202.0,107475.0] || -> until2p7(s7)* node4(s6). % 76.04/76.30 107477[104:Spt:107476.0] || -> until2p7(s7)*. % 76.04/76.30 107478[104:MRR:203.0,107477.0] || -> until2p7(s8)* node4(s7). % 76.04/76.30 107479[105:Spt:107478.0] || -> until2p7(s8)*. % 76.04/76.30 107480[105:MRR:204.0,107479.0] || -> until2p7(s9)* node4(s8). % 76.04/76.30 107481[106:Spt:107480.0] || -> until2p7(s9)*. % 76.04/76.30 107482[106:MRR:205.0,107481.0] || -> until2p7(s10)* node4(s9). % 76.04/76.30 107483[107:Spt:107482.0] || -> until2p7(s10)*. % 76.04/76.30 107484[107:MRR:206.0,107483.0] || -> until2p7(s11)* node4(s10). % 76.04/76.30 107485[108:Spt:107484.0] || -> until2p7(s11)*. % 76.04/76.30 107486[108:MRR:207.0,107485.0] || -> until2p7(s12)* node4(s11). % 76.04/76.30 107487[109:Spt:107486.0] || -> until2p7(s12)*. % 76.04/76.30 107488[109:MRR:208.0,107487.0] || -> until2p7(s13)* node4(s12). % 76.04/76.30 107489[110:Spt:107488.0] || -> until2p7(s13)*. % 76.04/76.30 107490[110:MRR:209.0,107489.0] || -> until2p7(s14)* node4(s13). % 76.04/76.30 107491[111:Spt:107490.0] || -> until2p7(s14)*. % 76.04/76.30 107492[111:MRR:210.0,107491.0] || -> until2p7(s15)* node4(s14). % 76.04/76.30 107493[112:Spt:107492.0] || -> until2p7(s15)*. % 76.04/76.30 107494[112:MRR:211.0,107493.0] || -> until2p7(s16)* node4(s15). % 76.04/76.30 107495[113:Spt:107494.0] || -> until2p7(s16)*. % 76.04/76.30 107496[113:MRR:212.0,107495.0] || -> until2p7(s17)* node4(s16). % 76.04/76.30 107497[114:Spt:107496.0] || -> until2p7(s17)*. % 76.04/76.30 107498[114:MRR:213.0,107497.0] || -> until2p7(s18)* node4(s17). % 76.04/76.30 107499[115:Spt:107498.0] || -> until2p7(s18)*. % 76.04/76.30 107500[115:MRR:214.0,107499.0] || -> until2p7(s19)* node4(s18). % 76.04/76.30 107501[116:Spt:107500.0] || -> until2p7(s19)*. % 76.04/76.30 107502[116:MRR:215.0,107501.0] || -> until2p7(s20)* node4(s19). % 76.04/76.30 107503[117:Spt:107502.0] || -> until2p7(s20)*. % 76.04/76.30 107504[117:MRR:216.0,107503.0] || -> until2p7(s21)* node4(s20). % 76.04/76.30 107505[118:Spt:107504.0] || -> until2p7(s21)*. % 76.04/76.30 107506[118:MRR:217.0,107505.0] || -> until2p7(s22)* node4(s21). % 76.04/76.30 107507[119:Spt:107506.0] || -> until2p7(s22)*. % 76.04/76.30 107508[119:MRR:218.0,107507.0] || -> until2p7(s23)* node4(s22). % 76.04/76.30 107509[120:Spt:107508.0] || -> until2p7(s23)*. % 76.04/76.30 107510[120:MRR:219.0,107509.0] || -> until2p7(s24)* node4(s23). % 76.04/76.30 107511[121:Spt:107510.0] || -> until2p7(s24)*. % 76.04/76.30 107512[121:MRR:220.0,107511.0] || -> until2p7(s25)* node4(s24). % 76.04/76.30 107513[122:Spt:107512.0] || -> until2p7(s25)*. % 76.04/76.30 107514[122:MRR:221.0,107513.0] || -> until2p7(s26)* node4(s25). % 76.04/76.30 107515[123:Spt:107514.0] || -> until2p7(s26)*. % 76.04/76.30 107516[123:MRR:222.0,107515.0] || -> until2p7(s27)* node4(s26). % 76.04/76.30 107517[124:Spt:107516.0] || -> until2p7(s27)*. % 76.04/76.30 107518[124:MRR:223.0,107517.0] || -> until2p7(s28)* node4(s27). % 76.04/76.30 107519[125:Spt:107518.0] || -> until2p7(s28)*. % 76.04/76.30 107520[125:MRR:224.0,107519.0] || -> until2p7(s29)* node4(s28). % 76.04/76.30 107521[126:Spt:107520.0] || -> until2p7(s29)*. % 76.04/76.30 107522[126:MRR:225.0,107521.0] || -> until2p7(s30)* node4(s29). % 76.04/76.30 107523[127:Spt:107522.0] || -> until2p7(s30)*. % 76.04/76.30 107524[127:MRR:226.0,107523.0] || -> until2p7(s31)* node4(s30). % 76.04/76.30 107525[128:Spt:107524.0] || -> until2p7(s31)*. % 76.04/76.30 107526[128:MRR:227.0,107525.0] || -> until2p7(s32)* node4(s31). % 76.04/76.30 107527[129:Spt:107526.0] || -> until2p7(s32)*. % 76.04/76.30 107528[129:MRR:228.0,107527.0] || -> until2p7(s33)* node4(s32). % 76.04/76.30 107529[130:Spt:107528.0] || -> until2p7(s33)*. % 76.04/76.30 107530[130:MRR:229.0,107529.0] || -> until2p7(s34)* node4(s33). % 76.04/76.30 107531[131:Spt:107530.0] || -> until2p7(s34)*. % 76.04/76.30 107532[131:MRR:230.0,107531.0] || -> until2p7(s35)* node4(s34). % 76.04/76.30 107533[132:Spt:107532.0] || -> until2p7(s35)*. % 76.04/76.30 107534[132:MRR:231.0,107533.0] || -> until2p7(s36)* node4(s35). % 76.04/76.30 107535[133:Spt:107534.0] || -> until2p7(s36)*. % 76.04/76.30 107536[133:MRR:232.0,107535.0] || -> until2p7(s37)* node4(s36). % 76.04/76.30 107537[134:Spt:107536.0] || -> until2p7(s37)*. % 76.04/76.30 107538[134:MRR:235.0,107537.0] || -> until2p7(s38)* node4(s37). % 76.04/76.30 107539[135:Spt:107538.0] || -> until2p7(s38)*. % 76.04/76.30 107540[135:MRR:236.0,107539.0] || -> until2p7(s39)* node4(s38). % 76.04/76.30 107541[136:Spt:107540.0] || -> until2p7(s39)*. % 76.04/76.30 107542[136:MRR:237.0,107541.0] || -> until2p7(s40)* node4(s39). % 76.04/76.30 107543[137:Spt:107542.0] || -> until2p7(s40)*. % 76.04/76.30 107544[137:MRR:238.0,107543.0] || -> until2p7(s41)* node4(s40). % 76.04/76.30 107545[138:Spt:107544.0] || -> until2p7(s41)*. % 76.04/76.30 107546[138:MRR:239.0,107545.0] || -> until2p7(s42)* node4(s41). % 76.04/76.30 107547[139:Spt:107546.0] || -> until2p7(s42)*. % 76.04/76.30 107548[139:MRR:240.0,107547.0] || -> until2p7(s43)* node4(s42). % 76.04/76.30 107549[140:Spt:107548.0] || -> until2p7(s43)*. % 76.04/76.30 107550[140:MRR:241.0,107549.0] || -> until2p7(s44)* node4(s43). % 76.04/76.30 107551[141:Spt:107550.0] || -> until2p7(s44)*. % 76.04/76.30 107552[141:MRR:539.0,107551.0] || -> until2p7(s45)* node4(s44). % 76.04/76.30 107553[142:Spt:107552.0] || -> until2p7(s45)*. % 76.04/76.30 107554[142:MRR:544.0,107553.0] || -> until2p7(s46)* node4(s45). % 76.04/76.30 107555[143:Spt:107554.0] || -> until2p7(s46)*. % 76.04/76.30 107556[143:MRR:549.0,107555.0] || -> until2p7(s47)* node4(s46). % 76.04/76.30 107557[144:Spt:107556.0] || -> until2p7(s47)*. % 76.04/76.30 107558[144:MRR:554.0,107557.0] || -> until2p7(s48)* node4(s47). % 76.04/76.30 107559[145:Spt:107558.0] || -> until2p7(s48)*. % 76.04/76.30 107560[145:MRR:559.0,107559.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 107561[146:Spt:107560.0] || -> until2p7(s49)*. % 76.04/76.30 107562[146:MRR:194.0,107561.0] || -> node4(s49)*. % 76.04/76.30 107563[146:MRR:107463.0,107562.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 107564[146:Res:53.1,107563.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 107566[146:MRR:107564.0,78381.0] || -> . % 76.04/76.30 107567[146:Spt:107566.0,107560.0,107561.0] || until2p7(s49)*+ -> . % 76.04/76.30 107568[146:Spt:107566.0,107560.1] || -> node4(s48)*. % 76.04/76.30 107569[146:MRR:78384.0,107568.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 107572[146:Res:53.1,107569.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 107575[146:Res:107572.0,61.1] always3(s48) || -> . % 76.04/76.30 107576[146:SSi:107575.0,78281.0,78387.0,78626.0,107559.0,107568.0] || -> . % 76.04/76.30 107577[145:Spt:107576.0,107558.0,107559.0] || until2p7(s48)*+ -> . % 76.04/76.30 107578[145:Spt:107576.0,107558.1] || -> node4(s47)*. % 76.04/76.30 107580[145:MRR:777.0,107578.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.30 107594[145:Res:53.1,107580.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.30 107596[146:Spt:107594.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 107598[146:Res:107596.0,61.1] always3(s47) || -> . % 76.04/76.30 107599[146:SSi:107598.0,78277.0,78280.0,78625.0,107557.0,107578.0] || -> . % 76.04/76.30 107600[146:Spt:107599.0,107594.0,107596.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.30 107601[146:Spt:107599.0,107594.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 107605[146:Res:107601.0,61.1] always3(s48) || -> . % 76.04/76.30 107606[146:SSi:107605.0,78281.0,78387.0,78626.0] || -> . % 76.04/76.30 107607[144:Spt:107606.0,107556.0,107557.0] || until2p7(s47)*+ -> . % 76.04/76.30 107608[144:Spt:107606.0,107556.1] || -> node4(s46)*. % 76.04/76.30 107610[144:MRR:780.0,107608.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.30 107617[144:Res:53.1,107610.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.30 107619[145:Spt:107617.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 107621[145:Res:107619.0,61.1] always3(s46) || -> . % 76.04/76.30 107622[145:SSi:107621.0,78272.0,78276.0,78624.0,107555.0,107608.0] || -> . % 76.04/76.30 107623[145:Spt:107622.0,107617.0,107619.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.30 107624[145:Spt:107622.0,107617.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 107628[145:Res:107624.0,61.1] always3(s47) || -> . % 76.04/76.30 107629[145:SSi:107628.0,78277.0,78280.0,78625.0] || -> . % 76.04/76.30 107630[143:Spt:107629.0,107554.0,107555.0] || until2p7(s46)*+ -> . % 76.04/76.30 107631[143:Spt:107629.0,107554.1] || -> node4(s45)*. % 76.04/76.30 107633[143:MRR:783.0,107631.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.30 107636[143:Res:53.1,107633.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.30 107638[144:Spt:107636.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 107640[144:Res:107638.0,61.1] always3(s45) || -> . % 76.04/76.30 107641[144:SSi:107640.0,78268.0,78271.0,78623.0,107553.0,107631.0] || -> . % 76.04/76.30 107642[144:Spt:107641.0,107636.0,107638.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.30 107643[144:Spt:107641.0,107636.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 107647[144:Res:107643.0,61.1] always3(s46) || -> . % 76.04/76.30 107648[144:SSi:107647.0,78272.0,78276.0,78624.0] || -> . % 76.04/76.30 107649[142:Spt:107648.0,107552.0,107553.0] || until2p7(s45)*+ -> . % 76.04/76.30 107650[142:Spt:107648.0,107552.1] || -> node4(s44)*. % 76.04/76.30 107652[142:MRR:786.0,107650.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.30 107655[142:Res:53.1,107652.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.30 107657[143:Spt:107655.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 107659[143:Res:107657.0,61.1] always3(s44) || -> . % 76.04/76.30 107660[143:SSi:107659.0,78263.0,78267.0,78622.0,107551.0,107650.0] || -> . % 76.04/76.30 107661[143:Spt:107660.0,107655.0,107657.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.30 107662[143:Spt:107660.0,107655.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 107666[143:Res:107662.0,61.1] always3(s45) || -> . % 76.04/76.30 107667[143:SSi:107666.0,78268.0,78271.0,78623.0] || -> . % 76.04/76.30 107668[141:Spt:107667.0,107550.0,107551.0] || until2p7(s44)*+ -> . % 76.04/76.30 107669[141:Spt:107667.0,107550.1] || -> node4(s43)*. % 76.04/76.30 107671[141:MRR:789.0,107669.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.30 107674[141:Res:53.1,107671.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.30 107679[142:Spt:107674.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 107681[142:Res:107679.0,61.1] always3(s43) || -> . % 76.04/76.30 107682[142:SSi:107681.0,78259.0,78262.0,78621.0,107549.0,107669.0] || -> . % 76.04/76.30 107683[142:Spt:107682.0,107674.0,107679.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.30 107684[142:Spt:107682.0,107674.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 107688[142:Res:107684.0,61.1] always3(s44) || -> . % 76.04/76.30 107689[142:SSi:107688.0,78263.0,78267.0,78622.0] || -> . % 76.04/76.30 107690[140:Spt:107689.0,107548.0,107549.0] || until2p7(s43)*+ -> . % 76.04/76.30 107691[140:Spt:107689.0,107548.1] || -> node4(s42)*. % 76.04/76.30 107693[140:MRR:792.0,107691.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.30 107696[140:Res:53.1,107693.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.30 107698[141:Spt:107696.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 107700[141:Res:107698.0,61.1] always3(s42) || -> . % 76.04/76.30 107701[141:SSi:107700.0,78254.0,78258.0,78620.0,107547.0,107691.0] || -> . % 76.04/76.30 107702[141:Spt:107701.0,107696.0,107698.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.30 107703[141:Spt:107701.0,107696.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 107707[141:Res:107703.0,61.1] always3(s43) || -> . % 76.04/76.30 107708[141:SSi:107707.0,78259.0,78262.0,78621.0] || -> . % 76.04/76.30 107709[139:Spt:107708.0,107546.0,107547.0] || until2p7(s42)*+ -> . % 76.04/76.30 107710[139:Spt:107708.0,107546.1] || -> node4(s41)*. % 76.04/76.30 107712[139:MRR:795.0,107710.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.30 107715[139:Res:53.1,107712.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.30 107717[140:Spt:107715.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 107719[140:Res:107717.0,61.1] always3(s41) || -> . % 76.04/76.30 107720[140:SSi:107719.0,78250.0,78253.0,78619.0,107545.0,107710.0] || -> . % 76.04/76.30 107721[140:Spt:107720.0,107715.0,107717.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.30 107722[140:Spt:107720.0,107715.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.30 107726[140:Res:107722.0,61.1] always3(s42) || -> . % 76.04/76.30 107727[140:SSi:107726.0,78254.0,78258.0,78620.0] || -> . % 76.04/76.30 107728[138:Spt:107727.0,107544.0,107545.0] || until2p7(s41)*+ -> . % 76.04/76.30 107729[138:Spt:107727.0,107544.1] || -> node4(s40)*. % 76.04/76.30 107731[138:MRR:798.0,107729.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.30 107734[138:Res:53.1,107731.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.30 107736[139:Spt:107734.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 107738[139:Res:107736.0,61.1] always3(s40) || -> . % 76.04/76.30 107739[139:SSi:107738.0,78245.0,78249.0,78618.0,107543.0,107729.0] || -> . % 76.04/76.30 107740[139:Spt:107739.0,107734.0,107736.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.30 107741[139:Spt:107739.0,107734.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.30 107745[139:Res:107741.0,61.1] always3(s41) || -> . % 76.04/76.30 107746[139:SSi:107745.0,78250.0,78253.0,78619.0] || -> . % 76.04/76.30 107747[137:Spt:107746.0,107542.0,107543.0] || until2p7(s40)*+ -> . % 76.04/76.30 107748[137:Spt:107746.0,107542.1] || -> node4(s39)*. % 76.04/76.30 107750[137:MRR:801.0,107748.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.30 107753[137:Res:53.1,107750.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.30 107758[138:Spt:107753.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 107760[138:Res:107758.0,61.1] always3(s39) || -> . % 76.04/76.30 107761[138:SSi:107760.0,78241.0,78244.0,78617.0,107541.0,107748.0] || -> . % 76.04/76.30 107762[138:Spt:107761.0,107753.0,107758.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.30 107763[138:Spt:107761.0,107753.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.30 107767[138:Res:107763.0,61.1] always3(s40) || -> . % 76.04/76.30 107768[138:SSi:107767.0,78245.0,78249.0,78618.0] || -> . % 76.04/76.30 107769[136:Spt:107768.0,107540.0,107541.0] || until2p7(s39)*+ -> . % 76.04/76.30 107770[136:Spt:107768.0,107540.1] || -> node4(s38)*. % 76.04/76.30 107772[136:MRR:804.0,107770.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.30 107775[136:Res:53.1,107772.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.30 107777[137:Spt:107775.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 107779[137:Res:107777.0,61.1] always3(s38) || -> . % 76.04/76.30 107780[137:SSi:107779.0,78236.0,78240.0,78616.0,107539.0,107770.0] || -> . % 76.04/76.30 107781[137:Spt:107780.0,107775.0,107777.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.30 107782[137:Spt:107780.0,107775.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.30 107786[137:Res:107782.0,61.1] always3(s39) || -> . % 76.04/76.30 107787[137:SSi:107786.0,78241.0,78244.0,78617.0] || -> . % 76.04/76.30 107788[135:Spt:107787.0,107538.0,107539.0] || until2p7(s38)*+ -> . % 76.04/76.30 107789[135:Spt:107787.0,107538.1] || -> node4(s37)*. % 76.04/76.30 107791[135:MRR:807.0,107789.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.30 107794[135:Res:53.1,107791.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.30 107796[136:Spt:107794.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 107798[136:Res:107796.0,61.1] always3(s37) || -> . % 76.04/76.30 107799[136:SSi:107798.0,78232.0,78235.0,78615.0,107537.0,107789.0] || -> . % 76.04/76.30 107800[136:Spt:107799.0,107794.0,107796.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.30 107801[136:Spt:107799.0,107794.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.30 107805[136:Res:107801.0,61.1] always3(s38) || -> . % 76.04/76.30 107806[136:SSi:107805.0,78236.0,78240.0,78616.0] || -> . % 76.04/76.30 107807[134:Spt:107806.0,107536.0,107537.0] || until2p7(s37)*+ -> . % 76.04/76.30 107808[134:Spt:107806.0,107536.1] || -> node4(s36)*. % 76.04/76.30 107810[134:MRR:810.0,107808.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.30 107813[134:Res:53.1,107810.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.30 107815[135:Spt:107813.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 107817[135:Res:107815.0,61.1] always3(s36) || -> . % 76.04/76.30 107818[135:SSi:107817.0,78227.0,78231.0,78614.0,107535.0,107808.0] || -> . % 76.04/76.30 107819[135:Spt:107818.0,107813.0,107815.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.30 107820[135:Spt:107818.0,107813.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.30 107824[135:Res:107820.0,61.1] always3(s37) || -> . % 76.04/76.30 107825[135:SSi:107824.0,78232.0,78235.0,78615.0] || -> . % 76.04/76.30 107826[133:Spt:107825.0,107534.0,107535.0] || until2p7(s36)*+ -> . % 76.04/76.30 107827[133:Spt:107825.0,107534.1] || -> node4(s35)*. % 76.04/76.30 107829[133:MRR:813.0,107827.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.30 107832[133:Res:53.1,107829.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.30 107837[134:Spt:107832.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 107839[134:Res:107837.0,61.1] always3(s35) || -> . % 76.04/76.30 107840[134:SSi:107839.0,78223.0,78226.0,78613.0,107533.0,107827.0] || -> . % 76.04/76.30 107841[134:Spt:107840.0,107832.0,107837.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.30 107842[134:Spt:107840.0,107832.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.30 107846[134:Res:107842.0,61.1] always3(s36) || -> . % 76.04/76.30 107847[134:SSi:107846.0,78227.0,78231.0,78614.0] || -> . % 76.04/76.30 107848[132:Spt:107847.0,107532.0,107533.0] || until2p7(s35)*+ -> . % 76.04/76.30 107849[132:Spt:107847.0,107532.1] || -> node4(s34)*. % 76.04/76.30 107851[132:MRR:816.0,107849.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.30 107854[132:Res:53.1,107851.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.30 107856[133:Spt:107854.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 107858[133:Res:107856.0,61.1] always3(s34) || -> . % 76.04/76.30 107859[133:SSi:107858.0,78218.0,78222.0,78612.0,107531.0,107849.0] || -> . % 76.04/76.30 107860[133:Spt:107859.0,107854.0,107856.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.30 107861[133:Spt:107859.0,107854.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.30 107865[133:Res:107861.0,61.1] always3(s35) || -> . % 76.04/76.30 107866[133:SSi:107865.0,78223.0,78226.0,78613.0] || -> . % 76.04/76.30 107867[131:Spt:107866.0,107530.0,107531.0] || until2p7(s34)*+ -> . % 76.04/76.30 107868[131:Spt:107866.0,107530.1] || -> node4(s33)*. % 76.04/76.30 107870[131:MRR:819.0,107868.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.30 107873[131:Res:53.1,107870.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.30 107875[132:Spt:107873.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 107877[132:Res:107875.0,61.1] always3(s33) || -> . % 76.04/76.30 107878[132:SSi:107877.0,78214.0,78217.0,78611.0,107529.0,107868.0] || -> . % 76.04/76.30 107879[132:Spt:107878.0,107873.0,107875.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.30 107880[132:Spt:107878.0,107873.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.30 107884[132:Res:107880.0,61.1] always3(s34) || -> . % 76.04/76.30 107885[132:SSi:107884.0,78218.0,78222.0,78612.0] || -> . % 76.04/76.30 107886[130:Spt:107885.0,107528.0,107529.0] || until2p7(s33)*+ -> . % 76.04/76.30 107887[130:Spt:107885.0,107528.1] || -> node4(s32)*. % 76.04/76.30 107889[130:MRR:822.0,107887.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.30 107892[130:Res:53.1,107889.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.30 107894[131:Spt:107892.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 107896[131:Res:107894.0,61.1] always3(s32) || -> . % 76.04/76.30 107897[131:SSi:107896.0,78209.0,78213.0,78610.0,107527.0,107887.0] || -> . % 76.04/76.30 107898[131:Spt:107897.0,107892.0,107894.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.30 107899[131:Spt:107897.0,107892.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.30 107903[131:Res:107899.0,61.1] always3(s33) || -> . % 76.04/76.30 107904[131:SSi:107903.0,78214.0,78217.0,78611.0] || -> . % 76.04/76.30 107905[129:Spt:107904.0,107526.0,107527.0] || until2p7(s32)*+ -> . % 76.04/76.30 107906[129:Spt:107904.0,107526.1] || -> node4(s31)*. % 76.04/76.30 107908[129:MRR:825.0,107906.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.30 107911[129:Res:53.1,107908.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.30 107916[130:Spt:107911.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 107918[130:Res:107916.0,61.1] always3(s31) || -> . % 76.04/76.30 107919[130:SSi:107918.0,78205.0,78208.0,78609.0,107525.0,107906.0] || -> . % 76.04/76.30 107920[130:Spt:107919.0,107911.0,107916.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.30 107921[130:Spt:107919.0,107911.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.30 107925[130:Res:107921.0,61.1] always3(s32) || -> . % 76.04/76.30 107926[130:SSi:107925.0,78209.0,78213.0,78610.0] || -> . % 76.04/76.30 107927[128:Spt:107926.0,107524.0,107525.0] || until2p7(s31)*+ -> . % 76.04/76.30 107928[128:Spt:107926.0,107524.1] || -> node4(s30)*. % 76.04/76.30 107930[128:MRR:828.0,107928.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.30 107933[128:Res:53.1,107930.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.30 107935[129:Spt:107933.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 107937[129:Res:107935.0,61.1] always3(s30) || -> . % 76.04/76.30 107938[129:SSi:107937.0,78200.0,78204.0,78608.0,107523.0,107928.0] || -> . % 76.04/76.30 107939[129:Spt:107938.0,107933.0,107935.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.30 107940[129:Spt:107938.0,107933.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.30 107944[129:Res:107940.0,61.1] always3(s31) || -> . % 76.04/76.30 107945[129:SSi:107944.0,78205.0,78208.0,78609.0] || -> . % 76.04/76.30 107946[127:Spt:107945.0,107522.0,107523.0] || until2p7(s30)*+ -> . % 76.04/76.30 107947[127:Spt:107945.0,107522.1] || -> node4(s29)*. % 76.04/76.30 107949[127:MRR:831.0,107947.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.30 107952[127:Res:53.1,107949.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.30 107954[128:Spt:107952.0] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 107956[128:Res:107954.0,61.1] always3(s29) || -> . % 76.04/76.30 107957[128:SSi:107956.0,78196.0,78199.0,78607.0,107521.0,107947.0] || -> . % 76.04/76.30 107958[128:Spt:107957.0,107952.0,107954.0] || m_main_v_state(s29,c_busy)* -> . % 76.04/76.30 107959[128:Spt:107957.0,107952.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.30 107963[128:Res:107959.0,61.1] always3(s30) || -> . % 76.04/76.30 107964[128:SSi:107963.0,78200.0,78204.0,78608.0] || -> . % 76.04/76.30 107965[126:Spt:107964.0,107520.0,107521.0] || until2p7(s29)*+ -> . % 76.04/76.30 107966[126:Spt:107964.0,107520.1] || -> node4(s28)*. % 76.04/76.30 107968[126:MRR:834.0,107966.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.04/76.30 107971[126:Res:53.1,107968.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.04/76.30 107973[127:Spt:107971.0] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 107975[127:Res:107973.0,61.1] always3(s28) || -> . % 76.04/76.30 107976[127:SSi:107975.0,78191.0,78195.0,78606.0,107519.0,107966.0] || -> . % 76.04/76.30 107977[127:Spt:107976.0,107971.0,107973.0] || m_main_v_state(s28,c_busy)* -> . % 76.04/76.30 107978[127:Spt:107976.0,107971.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.30 107982[127:Res:107978.0,61.1] always3(s29) || -> . % 76.04/76.30 107983[127:SSi:107982.0,78196.0,78199.0,78607.0] || -> . % 76.04/76.30 107984[125:Spt:107983.0,107518.0,107519.0] || until2p7(s28)*+ -> . % 76.04/76.30 107985[125:Spt:107983.0,107518.1] || -> node4(s27)*. % 76.04/76.30 107987[125:MRR:837.0,107985.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.04/76.30 107990[125:Res:53.1,107987.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.04/76.30 107995[126:Spt:107990.0] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 107997[126:Res:107995.0,61.1] always3(s27) || -> . % 76.04/76.30 107998[126:SSi:107997.0,78187.0,78190.0,78605.0,107517.0,107985.0] || -> . % 76.04/76.30 107999[126:Spt:107998.0,107990.0,107995.0] || m_main_v_state(s27,c_busy)* -> . % 76.04/76.30 108000[126:Spt:107998.0,107990.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.30 108004[126:Res:108000.0,61.1] always3(s28) || -> . % 76.04/76.30 108005[126:SSi:108004.0,78191.0,78195.0,78606.0] || -> . % 76.04/76.30 108006[124:Spt:108005.0,107516.0,107517.0] || until2p7(s27)*+ -> . % 76.04/76.30 108007[124:Spt:108005.0,107516.1] || -> node4(s26)*. % 76.04/76.30 108009[124:MRR:840.0,108007.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.04/76.30 108012[124:Res:53.1,108009.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.04/76.30 108014[125:Spt:108012.0] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 108016[125:Res:108014.0,61.1] always3(s26) || -> . % 76.04/76.30 108017[125:SSi:108016.0,78182.0,78186.0,78604.0,107515.0,108007.0] || -> . % 76.04/76.30 108018[125:Spt:108017.0,108012.0,108014.0] || m_main_v_state(s26,c_busy)* -> . % 76.04/76.30 108019[125:Spt:108017.0,108012.1] || -> m_main_v_state(s27,c_busy)*. % 76.04/76.30 108023[125:Res:108019.0,61.1] always3(s27) || -> . % 76.04/76.30 108024[125:SSi:108023.0,78187.0,78190.0,78605.0] || -> . % 76.04/76.30 108025[123:Spt:108024.0,107514.0,107515.0] || until2p7(s26)*+ -> . % 76.04/76.30 108026[123:Spt:108024.0,107514.1] || -> node4(s25)*. % 76.04/76.30 108028[123:MRR:843.0,108026.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.04/76.30 108031[123:Res:53.1,108028.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.04/76.30 108033[124:Spt:108031.0] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 108035[124:Res:108033.0,61.1] always3(s25) || -> . % 76.04/76.30 108036[124:SSi:108035.0,78178.0,78181.0,78603.0,107513.0,108026.0] || -> . % 76.04/76.30 108037[124:Spt:108036.0,108031.0,108033.0] || m_main_v_state(s25,c_busy)* -> . % 76.04/76.30 108038[124:Spt:108036.0,108031.1] || -> m_main_v_state(s26,c_busy)*. % 76.04/76.30 108042[124:Res:108038.0,61.1] always3(s26) || -> . % 76.04/76.30 108043[124:SSi:108042.0,78182.0,78186.0,78604.0] || -> . % 76.04/76.30 108044[122:Spt:108043.0,107512.0,107513.0] || until2p7(s25)*+ -> . % 76.04/76.30 108045[122:Spt:108043.0,107512.1] || -> node4(s24)*. % 76.04/76.30 108047[122:MRR:846.0,108045.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.04/76.30 108050[122:Res:53.1,108047.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.04/76.30 108052[123:Spt:108050.0] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 108054[123:Res:108052.0,61.1] always3(s24) || -> . % 76.04/76.30 108055[123:SSi:108054.0,78173.0,78177.0,78602.0,107511.0,108045.0] || -> . % 76.04/76.30 108056[123:Spt:108055.0,108050.0,108052.0] || m_main_v_state(s24,c_busy)* -> . % 76.04/76.30 108057[123:Spt:108055.0,108050.1] || -> m_main_v_state(s25,c_busy)*. % 76.04/76.30 108061[123:Res:108057.0,61.1] always3(s25) || -> . % 76.04/76.30 108062[123:SSi:108061.0,78178.0,78181.0,78603.0] || -> . % 76.04/76.30 108063[121:Spt:108062.0,107510.0,107511.0] || until2p7(s24)*+ -> . % 76.04/76.30 108064[121:Spt:108062.0,107510.1] || -> node4(s23)*. % 76.04/76.30 108066[121:MRR:849.0,108064.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.04/76.30 108069[121:Res:53.1,108066.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.04/76.30 108074[122:Spt:108069.0] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 108076[122:Res:108074.0,61.1] always3(s23) || -> . % 76.04/76.30 108077[122:SSi:108076.0,78169.0,78172.0,78601.0,107509.0,108064.0] || -> . % 76.04/76.30 108078[122:Spt:108077.0,108069.0,108074.0] || m_main_v_state(s23,c_busy)* -> . % 76.04/76.30 108079[122:Spt:108077.0,108069.1] || -> m_main_v_state(s24,c_busy)*. % 76.04/76.30 108083[122:Res:108079.0,61.1] always3(s24) || -> . % 76.04/76.30 108084[122:SSi:108083.0,78173.0,78177.0,78602.0] || -> . % 76.04/76.30 108085[120:Spt:108084.0,107508.0,107509.0] || until2p7(s23)*+ -> . % 76.04/76.30 108086[120:Spt:108084.0,107508.1] || -> node4(s22)*. % 76.04/76.30 108088[120:MRR:852.0,108086.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.04/76.30 108091[120:Res:53.1,108088.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.04/76.30 108093[121:Spt:108091.0] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 108095[121:Res:108093.0,61.1] always3(s22) || -> . % 76.04/76.30 108096[121:SSi:108095.0,78164.0,78168.0,78600.0,107507.0,108086.0] || -> . % 76.04/76.30 108097[121:Spt:108096.0,108091.0,108093.0] || m_main_v_state(s22,c_busy)* -> . % 76.04/76.30 108098[121:Spt:108096.0,108091.1] || -> m_main_v_state(s23,c_busy)*. % 76.04/76.30 108102[121:Res:108098.0,61.1] always3(s23) || -> . % 76.04/76.30 108103[121:SSi:108102.0,78169.0,78172.0,78601.0] || -> . % 76.04/76.30 108104[119:Spt:108103.0,107506.0,107507.0] || until2p7(s22)*+ -> . % 76.04/76.30 108105[119:Spt:108103.0,107506.1] || -> node4(s21)*. % 76.04/76.30 108107[119:MRR:855.0,108105.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.04/76.30 108110[119:Res:53.1,108107.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.04/76.30 108112[120:Spt:108110.0] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 108114[120:Res:108112.0,61.1] always3(s21) || -> . % 76.04/76.30 108115[120:SSi:108114.0,78160.0,78163.0,78599.0,107505.0,108105.0] || -> . % 76.04/76.30 108116[120:Spt:108115.0,108110.0,108112.0] || m_main_v_state(s21,c_busy)* -> . % 76.04/76.30 108117[120:Spt:108115.0,108110.1] || -> m_main_v_state(s22,c_busy)*. % 76.04/76.30 108121[120:Res:108117.0,61.1] always3(s22) || -> . % 76.04/76.30 108122[120:SSi:108121.0,78164.0,78168.0,78600.0] || -> . % 76.04/76.30 108123[118:Spt:108122.0,107504.0,107505.0] || until2p7(s21)*+ -> . % 76.04/76.30 108124[118:Spt:108122.0,107504.1] || -> node4(s20)*. % 76.04/76.30 108126[118:MRR:858.0,108124.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.04/76.30 108129[118:Res:53.1,108126.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.04/76.30 108131[119:Spt:108129.0] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 108133[119:Res:108131.0,61.1] always3(s20) || -> . % 76.04/76.30 108134[119:SSi:108133.0,78155.0,78159.0,78598.0,107503.0,108124.0] || -> . % 76.04/76.30 108135[119:Spt:108134.0,108129.0,108131.0] || m_main_v_state(s20,c_busy)* -> . % 76.04/76.30 108136[119:Spt:108134.0,108129.1] || -> m_main_v_state(s21,c_busy)*. % 76.04/76.30 108140[119:Res:108136.0,61.1] always3(s21) || -> . % 76.04/76.30 108141[119:SSi:108140.0,78160.0,78163.0,78599.0] || -> . % 76.04/76.30 108142[117:Spt:108141.0,107502.0,107503.0] || until2p7(s20)*+ -> . % 76.04/76.30 108143[117:Spt:108141.0,107502.1] || -> node4(s19)*. % 76.04/76.30 108145[117:MRR:861.0,108143.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.04/76.30 108148[117:Res:53.1,108145.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.04/76.30 108153[118:Spt:108148.0] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 108155[118:Res:108153.0,61.1] always3(s19) || -> . % 76.04/76.30 108156[118:SSi:108155.0,78151.0,78154.0,78597.0,107501.0,108143.0] || -> . % 76.04/76.30 108157[118:Spt:108156.0,108148.0,108153.0] || m_main_v_state(s19,c_busy)* -> . % 76.04/76.30 108158[118:Spt:108156.0,108148.1] || -> m_main_v_state(s20,c_busy)*. % 76.04/76.30 108162[118:Res:108158.0,61.1] always3(s20) || -> . % 76.04/76.30 108163[118:SSi:108162.0,78155.0,78159.0,78598.0] || -> . % 76.04/76.30 108164[116:Spt:108163.0,107500.0,107501.0] || until2p7(s19)*+ -> . % 76.04/76.30 108165[116:Spt:108163.0,107500.1] || -> node4(s18)*. % 76.04/76.30 108167[116:MRR:864.0,108165.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.04/76.30 108170[116:Res:53.1,108167.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.04/76.30 108172[117:Spt:108170.0] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 108174[117:Res:108172.0,61.1] always3(s18) || -> . % 76.04/76.30 108175[117:SSi:108174.0,78146.0,78150.0,78596.0,107499.0,108165.0] || -> . % 76.04/76.30 108176[117:Spt:108175.0,108170.0,108172.0] || m_main_v_state(s18,c_busy)* -> . % 76.04/76.30 108177[117:Spt:108175.0,108170.1] || -> m_main_v_state(s19,c_busy)*. % 76.04/76.30 108181[117:Res:108177.0,61.1] always3(s19) || -> . % 76.04/76.30 108182[117:SSi:108181.0,78151.0,78154.0,78597.0] || -> . % 76.04/76.30 108183[115:Spt:108182.0,107498.0,107499.0] || until2p7(s18)*+ -> . % 76.04/76.30 108184[115:Spt:108182.0,107498.1] || -> node4(s17)*. % 76.04/76.30 108186[115:MRR:867.0,108184.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.04/76.30 108189[115:Res:53.1,108186.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.04/76.30 108191[116:Spt:108189.0] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 108193[116:Res:108191.0,61.1] always3(s17) || -> . % 76.04/76.30 108194[116:SSi:108193.0,78142.0,78145.0,78595.0,107497.0,108184.0] || -> . % 76.04/76.30 108195[116:Spt:108194.0,108189.0,108191.0] || m_main_v_state(s17,c_busy)* -> . % 76.04/76.30 108196[116:Spt:108194.0,108189.1] || -> m_main_v_state(s18,c_busy)*. % 76.04/76.30 108200[116:Res:108196.0,61.1] always3(s18) || -> . % 76.04/76.30 108201[116:SSi:108200.0,78146.0,78150.0,78596.0] || -> . % 76.04/76.30 108202[114:Spt:108201.0,107496.0,107497.0] || until2p7(s17)*+ -> . % 76.04/76.30 108203[114:Spt:108201.0,107496.1] || -> node4(s16)*. % 76.04/76.30 108205[114:MRR:870.0,108203.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.04/76.30 108208[114:Res:53.1,108205.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.04/76.30 108210[115:Spt:108208.0] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 108212[115:Res:108210.0,61.1] always3(s16) || -> . % 76.04/76.30 108213[115:SSi:108212.0,78137.0,78141.0,78594.0,107495.0,108203.0] || -> . % 76.04/76.30 108214[115:Spt:108213.0,108208.0,108210.0] || m_main_v_state(s16,c_busy)* -> . % 76.04/76.30 108215[115:Spt:108213.0,108208.1] || -> m_main_v_state(s17,c_busy)*. % 76.04/76.30 108219[115:Res:108215.0,61.1] always3(s17) || -> . % 76.04/76.30 108220[115:SSi:108219.0,78142.0,78145.0,78595.0] || -> . % 76.04/76.30 108221[113:Spt:108220.0,107494.0,107495.0] || until2p7(s16)*+ -> . % 76.04/76.30 108222[113:Spt:108220.0,107494.1] || -> node4(s15)*. % 76.04/76.30 108224[113:MRR:873.0,108222.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.04/76.30 108227[113:Res:53.1,108224.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.04/76.30 108232[114:Spt:108227.0] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 108234[114:Res:108232.0,61.1] always3(s15) || -> . % 76.04/76.30 108235[114:SSi:108234.0,78133.0,78136.0,78593.0,107493.0,108222.0] || -> . % 76.04/76.30 108236[114:Spt:108235.0,108227.0,108232.0] || m_main_v_state(s15,c_busy)* -> . % 76.04/76.30 108237[114:Spt:108235.0,108227.1] || -> m_main_v_state(s16,c_busy)*. % 76.04/76.30 108241[114:Res:108237.0,61.1] always3(s16) || -> . % 76.04/76.30 108242[114:SSi:108241.0,78137.0,78141.0,78594.0] || -> . % 76.04/76.30 108243[112:Spt:108242.0,107492.0,107493.0] || until2p7(s15)*+ -> . % 76.04/76.30 108244[112:Spt:108242.0,107492.1] || -> node4(s14)*. % 76.04/76.30 108246[112:MRR:876.0,108244.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.04/76.30 108249[112:Res:53.1,108246.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.04/76.30 108251[113:Spt:108249.0] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 108253[113:Res:108251.0,61.1] always3(s14) || -> . % 76.04/76.30 108254[113:SSi:108253.0,78128.0,78132.0,78592.0,107491.0,108244.0] || -> . % 76.04/76.30 108255[113:Spt:108254.0,108249.0,108251.0] || m_main_v_state(s14,c_busy)* -> . % 76.04/76.30 108256[113:Spt:108254.0,108249.1] || -> m_main_v_state(s15,c_busy)*. % 76.04/76.30 108260[113:Res:108256.0,61.1] always3(s15) || -> . % 76.04/76.30 108261[113:SSi:108260.0,78133.0,78136.0,78593.0] || -> . % 76.04/76.30 108262[111:Spt:108261.0,107490.0,107491.0] || until2p7(s14)*+ -> . % 76.04/76.30 108263[111:Spt:108261.0,107490.1] || -> node4(s13)*. % 76.04/76.30 108265[111:MRR:879.0,108263.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.04/76.30 108268[111:Res:53.1,108265.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.04/76.30 108270[112:Spt:108268.0] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 108272[112:Res:108270.0,61.1] always3(s13) || -> . % 76.04/76.30 108273[112:SSi:108272.0,78124.0,78127.0,78591.0,107489.0,108263.0] || -> . % 76.04/76.30 108274[112:Spt:108273.0,108268.0,108270.0] || m_main_v_state(s13,c_busy)* -> . % 76.04/76.30 108275[112:Spt:108273.0,108268.1] || -> m_main_v_state(s14,c_busy)*. % 76.04/76.30 108279[112:Res:108275.0,61.1] always3(s14) || -> . % 76.04/76.30 108280[112:SSi:108279.0,78128.0,78132.0,78592.0] || -> . % 76.04/76.30 108281[110:Spt:108280.0,107488.0,107489.0] || until2p7(s13)*+ -> . % 76.04/76.30 108282[110:Spt:108280.0,107488.1] || -> node4(s12)*. % 76.04/76.30 108284[110:MRR:882.0,108282.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.04/76.30 108287[110:Res:53.1,108284.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.04/76.30 108289[111:Spt:108287.0] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 108291[111:Res:108289.0,61.1] always3(s12) || -> . % 76.04/76.30 108292[111:SSi:108291.0,78119.0,78123.0,78590.0,107487.0,108282.0] || -> . % 76.04/76.30 108293[111:Spt:108292.0,108287.0,108289.0] || m_main_v_state(s12,c_busy)* -> . % 76.04/76.30 108294[111:Spt:108292.0,108287.1] || -> m_main_v_state(s13,c_busy)*. % 76.04/76.30 108298[111:Res:108294.0,61.1] always3(s13) || -> . % 76.04/76.30 108299[111:SSi:108298.0,78124.0,78127.0,78591.0] || -> . % 76.04/76.30 108300[109:Spt:108299.0,107486.0,107487.0] || until2p7(s12)*+ -> . % 76.04/76.30 108301[109:Spt:108299.0,107486.1] || -> node4(s11)*. % 76.04/76.30 108303[109:MRR:885.0,108301.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.04/76.30 108306[109:Res:53.1,108303.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.04/76.30 108311[110:Spt:108306.0] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 108313[110:Res:108311.0,61.1] always3(s11) || -> . % 76.04/76.30 108314[110:SSi:108313.0,78115.0,78118.0,78589.0,107485.0,108301.0] || -> . % 76.04/76.30 108315[110:Spt:108314.0,108306.0,108311.0] || m_main_v_state(s11,c_busy)* -> . % 76.04/76.30 108316[110:Spt:108314.0,108306.1] || -> m_main_v_state(s12,c_busy)*. % 76.04/76.30 108320[110:Res:108316.0,61.1] always3(s12) || -> . % 76.04/76.30 108321[110:SSi:108320.0,78119.0,78123.0,78590.0] || -> . % 76.04/76.30 108322[108:Spt:108321.0,107484.0,107485.0] || until2p7(s11)*+ -> . % 76.04/76.30 108323[108:Spt:108321.0,107484.1] || -> node4(s10)*. % 76.04/76.30 108325[108:MRR:888.0,108323.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.04/76.30 108328[108:Res:53.1,108325.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.04/76.30 108330[109:Spt:108328.0] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 108332[109:Res:108330.0,61.1] always3(s10) || -> . % 76.04/76.30 108333[109:SSi:108332.0,78110.0,78114.0,78588.0,107483.0,108323.0] || -> . % 76.04/76.30 108334[109:Spt:108333.0,108328.0,108330.0] || m_main_v_state(s10,c_busy)* -> . % 76.04/76.30 108335[109:Spt:108333.0,108328.1] || -> m_main_v_state(s11,c_busy)*. % 76.04/76.30 108339[109:Res:108335.0,61.1] always3(s11) || -> . % 76.04/76.30 108340[109:SSi:108339.0,78115.0,78118.0,78589.0] || -> . % 76.04/76.30 108341[107:Spt:108340.0,107482.0,107483.0] || until2p7(s10)*+ -> . % 76.04/76.30 108342[107:Spt:108340.0,107482.1] || -> node4(s9)*. % 76.04/76.30 108344[107:MRR:891.0,108342.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.04/76.30 108347[107:Res:53.1,108344.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.04/76.30 108349[108:Spt:108347.0] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 108351[108:Res:108349.0,61.1] always3(s9) || -> . % 76.04/76.30 108352[108:SSi:108351.0,78106.0,78109.0,78587.0,107481.0,108342.0] || -> . % 76.04/76.30 108353[108:Spt:108352.0,108347.0,108349.0] || m_main_v_state(s9,c_busy)* -> . % 76.04/76.30 108354[108:Spt:108352.0,108347.1] || -> m_main_v_state(s10,c_busy)*. % 76.04/76.30 108358[108:Res:108354.0,61.1] always3(s10) || -> . % 76.04/76.30 108359[108:SSi:108358.0,78110.0,78114.0,78588.0] || -> . % 76.04/76.30 108360[106:Spt:108359.0,107480.0,107481.0] || until2p7(s9)*+ -> . % 76.04/76.30 108361[106:Spt:108359.0,107480.1] || -> node4(s8)*. % 76.04/76.30 108363[106:MRR:894.0,108361.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.04/76.30 108366[106:Res:53.1,108363.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.04/76.30 108368[107:Spt:108366.0] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 108370[107:Res:108368.0,61.1] always3(s8) || -> . % 76.04/76.30 108371[107:SSi:108370.0,78101.0,78105.0,78586.0,107479.0,108361.0] || -> . % 76.04/76.30 108372[107:Spt:108371.0,108366.0,108368.0] || m_main_v_state(s8,c_busy)* -> . % 76.04/76.30 108373[107:Spt:108371.0,108366.1] || -> m_main_v_state(s9,c_busy)*. % 76.04/76.30 108377[107:Res:108373.0,61.1] always3(s9) || -> . % 76.04/76.30 108378[107:SSi:108377.0,78106.0,78109.0,78587.0] || -> . % 76.04/76.30 108379[105:Spt:108378.0,107478.0,107479.0] || until2p7(s8)*+ -> . % 76.04/76.30 108380[105:Spt:108378.0,107478.1] || -> node4(s7)*. % 76.04/76.30 108382[105:MRR:897.0,108380.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.04/76.30 108385[105:Res:53.1,108382.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.04/76.30 108390[106:Spt:108385.0] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.30 108392[106:Res:108390.0,61.1] always3(s7) || -> . % 76.04/76.30 108393[106:SSi:108392.0,78097.0,78100.0,78585.0,107477.0,108380.0] || -> . % 76.04/76.30 108394[106:Spt:108393.0,108385.0,108390.0] || m_main_v_state(s7,c_busy)* -> . % 76.04/76.30 108395[106:Spt:108393.0,108385.1] || -> m_main_v_state(s8,c_busy)*. % 76.04/76.30 108399[106:Res:108395.0,61.1] always3(s8) || -> . % 76.04/76.30 108400[106:SSi:108399.0,78101.0,78105.0,78586.0] || -> . % 76.04/76.30 108401[104:Spt:108400.0,107476.0,107477.0] || until2p7(s7)*+ -> . % 76.04/76.30 108402[104:Spt:108400.0,107476.1] || -> node4(s6)*. % 76.04/76.30 108404[104:MRR:900.0,108402.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.04/76.30 108407[104:Res:53.1,108404.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.04/76.30 108409[105:Spt:108407.0] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.30 108411[105:Res:108409.0,61.1] always3(s6) || -> . % 76.04/76.30 108412[105:SSi:108411.0,78093.0,78096.0,78584.0,107475.0,108402.0] || -> . % 76.04/76.30 108413[105:Spt:108412.0,108407.0,108409.0] || m_main_v_state(s6,c_busy)* -> . % 76.04/76.30 108414[105:Spt:108412.0,108407.1] || -> m_main_v_state(s7,c_busy)*. % 76.04/76.30 108418[105:Res:108414.0,61.1] always3(s7) || -> . % 76.04/76.30 108419[105:SSi:108418.0,78097.0,78100.0,78585.0] || -> . % 76.04/76.30 108420[103:Spt:108419.0,107474.0,107475.0] || until2p7(s6)*+ -> . % 76.04/76.30 108421[103:Spt:108419.0,107474.1] || -> node4(s5)*. % 76.04/76.30 108423[103:MRR:903.0,108421.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.04/76.30 108426[103:Res:53.1,108423.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.04/76.30 108428[104:Spt:108426.0] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.30 108430[104:Res:108428.0,61.1] always3(s5) || -> . % 76.04/76.30 108431[104:SSi:108430.0,78089.0,78092.0,78583.0,107473.0,108421.0] || -> . % 76.04/76.30 108432[104:Spt:108431.0,108426.0,108428.0] || m_main_v_state(s5,c_busy)* -> . % 76.04/76.30 108433[104:Spt:108431.0,108426.1] || -> m_main_v_state(s6,c_busy)*. % 76.04/76.30 108437[104:Res:108433.0,61.1] always3(s6) || -> . % 76.04/76.30 108438[104:SSi:108437.0,78093.0,78096.0,78584.0] || -> . % 76.04/76.30 108439[102:Spt:108438.0,107472.0,107473.0] || until2p7(s5)*+ -> . % 76.04/76.30 108440[102:Spt:108438.0,107472.1] || -> node4(s4)*. % 76.04/76.30 108442[102:MRR:906.0,108440.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.04/76.30 108445[102:Res:53.1,108442.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.04/76.30 108447[103:Spt:108445.0] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.30 108449[103:Res:108447.0,61.1] always3(s4) || -> . % 76.04/76.30 108450[103:SSi:108449.0,78085.0,78088.0,78582.0,107471.0,108440.0] || -> . % 76.04/76.30 108451[103:Spt:108450.0,108445.0,108447.0] || m_main_v_state(s4,c_busy)* -> . % 76.04/76.30 108452[103:Spt:108450.0,108445.1] || -> m_main_v_state(s5,c_busy)*. % 76.04/76.30 108456[103:Res:108452.0,61.1] always3(s5) || -> . % 76.04/76.30 108457[103:SSi:108456.0,78089.0,78092.0,78583.0] || -> . % 76.04/76.30 108458[101:Spt:108457.0,107470.0,107471.0] || until2p7(s4)*+ -> . % 76.04/76.30 108459[101:Spt:108457.0,107470.1] || -> node4(s3)*. % 76.04/76.30 108461[101:MRR:909.0,108459.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.04/76.30 108464[101:Res:53.1,108461.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.04/76.30 108469[102:Spt:108464.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.30 108471[102:Res:108469.0,61.1] always3(s3) || -> . % 76.04/76.30 108472[102:SSi:108471.0,78081.0,78084.0,78581.0,107469.0,108459.0] || -> . % 76.04/76.30 108473[102:Spt:108472.0,108464.0,108469.0] || m_main_v_state(s3,c_busy)* -> . % 76.04/76.30 108474[102:Spt:108472.0,108464.1] || -> m_main_v_state(s4,c_busy)*. % 76.04/76.30 108478[102:Res:108474.0,61.1] always3(s4) || -> . % 76.04/76.30 108479[102:SSi:108478.0,78085.0,78088.0,78582.0] || -> . % 76.04/76.30 108480[100:Spt:108479.0,107468.0,107469.0] || until2p7(s3)*+ -> . % 76.04/76.30 108481[100:Spt:108479.0,107468.1] || -> node4(s2)*. % 76.04/76.30 108483[100:MRR:912.0,108481.0] || m_main_v_state(s2,c_ready)*+ -> m_main_v_state(s3,c_busy). % 76.04/76.30 108486[100:Res:53.1,108483.0] || -> m_main_v_state(s2,c_busy)* m_main_v_state(s3,c_busy). % 76.04/76.30 108488[100:MRR:108486.0,107459.0] || -> m_main_v_state(s3,c_busy)*. % 76.04/76.30 108490[100:Res:108488.0,61.1] always3(s3) || -> . % 76.04/76.30 108491[100:SSi:108490.0,78081.0,78084.0,78581.0] || -> . % 76.04/76.30 108492[51:Spt:108491.0,78375.47,78580.0] || always3(s2)*+ -> . % 76.04/76.30 108493[51:Spt:108491.0,78375.0,78375.1,78375.2,78375.3,78375.4,78375.5,78375.6,78375.7,78375.8,78375.9,78375.10,78375.11,78375.12,78375.13,78375.14,78375.15,78375.16,78375.17,78375.18,78375.19,78375.20,78375.21,78375.22,78375.23,78375.24,78375.25,78375.26,78375.27,78375.28,78375.29,78375.30,78375.31,78375.32,78375.33,78375.34,78375.35,78375.36,78375.37,78375.38,78375.39,78375.40,78375.41,78375.42,78375.43,78375.44,78375.45,78375.46] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) trans(s49,s3)*. % 76.04/76.30 108495[51:Res:108493.46,69.2] xuntil6(s49) last(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.30 108496[51:Res:108493.46,62.1] always3(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* always3(s3). % 76.04/76.30 108497[51:Res:108493.46,60.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.30 108498[51:SSi:108496.0,50.0,78285.0,78388.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* always3(s3). % 76.04/76.30 108499[51:SSi:108495.1,50.0,78285.0,78388.0] xuntil6(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.30 108753[52:Spt:108498.46] || -> always3(s3)*. % 76.04/76.30 108754[52:MRR:525.0,108753.0] || -> always3(s4)*. % 76.04/76.30 108755[52:MRR:522.0,108754.0] || -> always3(s5)*. % 76.04/76.30 108756[52:MRR:519.0,108755.0] || -> always3(s6)*. % 76.04/76.30 108757[52:MRR:516.0,108756.0] || -> always3(s7)*. % 76.04/76.30 108758[52:MRR:513.0,108757.0] || -> always3(s8)*. % 76.04/76.30 108759[52:MRR:510.0,108758.0] || -> always3(s9)*. % 76.04/76.30 108760[52:MRR:507.0,108759.0] || -> always3(s10)*. % 76.04/76.30 108761[52:MRR:504.0,108760.0] || -> always3(s11)*. % 76.04/76.30 108762[52:MRR:501.0,108761.0] || -> always3(s12)*. % 76.04/76.30 108763[52:MRR:498.0,108762.0] || -> always3(s13)*. % 76.04/76.30 108764[52:MRR:495.0,108763.0] || -> always3(s14)*. % 76.04/76.30 108765[52:MRR:492.0,108764.0] || -> always3(s15)*. % 76.04/76.30 108766[52:MRR:489.0,108765.0] || -> always3(s16)*. % 76.04/76.30 108767[52:MRR:486.0,108766.0] || -> always3(s17)*. % 76.04/76.30 108768[52:MRR:483.0,108767.0] || -> always3(s18)*. % 76.04/76.30 108769[52:MRR:480.0,108768.0] || -> always3(s19)*. % 76.04/76.30 108770[52:MRR:477.0,108769.0] || -> always3(s20)*. % 76.04/76.30 108771[52:MRR:474.0,108770.0] || -> always3(s21)*. % 76.04/76.30 108772[52:MRR:471.0,108771.0] || -> always3(s22)*. % 76.04/76.30 108773[52:MRR:468.0,108772.0] || -> always3(s23)*. % 76.04/76.30 108774[52:MRR:465.0,108773.0] || -> always3(s24)*. % 76.04/76.30 108775[52:MRR:462.0,108774.0] || -> always3(s25)*. % 76.04/76.30 108776[52:MRR:459.0,108775.0] || -> always3(s26)*. % 76.04/76.30 108777[52:MRR:456.0,108776.0] || -> always3(s27)*. % 76.04/76.30 108778[52:MRR:453.0,108777.0] || -> always3(s28)*. % 76.04/76.30 108779[52:MRR:450.0,108778.0] || -> always3(s29)*. % 76.04/76.30 108780[52:MRR:427.0,108779.0] || -> always3(s30)*. % 76.04/76.30 108781[52:MRR:425.0,108780.0] || -> always3(s31)*. % 76.04/76.30 108782[52:MRR:423.0,108781.0] || -> always3(s32)*. % 76.04/76.30 108783[52:MRR:421.0,108782.0] || -> always3(s33)*. % 76.04/76.30 108784[52:MRR:370.0,108783.0] || -> always3(s34)*. % 76.04/76.30 108785[52:MRR:368.0,108784.0] || -> always3(s35)*. % 76.04/76.30 108786[52:MRR:366.0,108785.0] || -> always3(s36)*. % 76.04/76.30 108787[52:MRR:364.0,108786.0] || -> always3(s37)*. % 76.04/76.30 108788[52:MRR:313.0,108787.0] || -> always3(s38)*. % 76.04/76.30 108789[52:MRR:311.0,108788.0] || -> always3(s39)*. % 76.04/76.30 108790[52:MRR:309.0,108789.0] || -> always3(s40)*. % 76.04/76.30 108791[52:MRR:307.0,108790.0] || -> always3(s41)*. % 76.04/76.30 108792[52:MRR:306.0,108791.0] || -> always3(s42)*. % 76.04/76.30 108793[52:MRR:305.0,108792.0] || -> always3(s43)*. % 76.04/76.30 108794[52:MRR:304.0,108793.0] || -> always3(s44)*. % 76.04/76.30 108795[52:MRR:303.0,108794.0] || -> always3(s45)*. % 76.04/76.30 108796[52:MRR:302.0,108795.0] || -> always3(s46)*. % 76.04/76.30 108797[52:MRR:301.0,108796.0] || -> always3(s47)*. % 76.04/76.30 108798[52:MRR:300.0,108797.0] || -> always3(s48)*. % 76.04/76.30 108799[53:Spt:108497.0] || -> trans(s49,s49)*. % 76.04/76.30 108800[53:Res:108799.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s49)*. % 76.04/76.30 108802[53:Res:108799.0,60.0] || -> node2(s49,s49)*. % 76.04/76.30 108803[53:SSi:108800.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s49)*. % 76.04/76.30 108804[53:Res:108802.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> m_main_v_state(s49,c_busy). % 76.04/76.30 108805[53:MRR:108804.1,108804.2,53.1,78381.0] m_main_v_request(s49) || -> . % 76.04/76.30 108807[53:SoR:108805.0,64.1] node4(s49) || -> . % 76.04/76.30 108808[53:MRR:194.1,108807.0] until2p7(s49) || -> . % 76.04/76.30 108811[53:MRR:108803.1,108808.0] xuntil6(s49) || -> . % 76.04/76.30 108812[53:SoR:108807.0,66.2] until5(s49) || -> xuntil6(s49)*. % 76.04/76.30 108813[53:SSi:108812.0,50.0,78285.0,78388.0] || -> xuntil6(s49)*. % 76.04/76.30 108814[53:MRR:108813.0,108811.0] || -> . % 76.04/76.30 108815[53:Spt:108814.0,108497.0,108799.0] || trans(s49,s49)*+ -> . % 76.04/76.30 108816[53:Spt:108814.0,108497.1,108497.2,108497.3,108497.4,108497.5,108497.6,108497.7,108497.8,108497.9,108497.10,108497.11,108497.12,108497.13,108497.14,108497.15,108497.16,108497.17,108497.18,108497.19,108497.20,108497.21,108497.22,108497.23,108497.24,108497.25,108497.26,108497.27,108497.28,108497.29,108497.30,108497.31,108497.32,108497.33,108497.34,108497.35,108497.36,108497.37,108497.38,108497.39,108497.40,108497.41,108497.42,108497.43,108497.44,108497.45,108497.46] || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.30 108818[53:MRR:108499.1,108815.0] xuntil6(s49) || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.30 108819[54:Spt:108816.0] || -> trans(s49,s48)*. % 76.04/76.30 108820[54:Res:108819.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s48)*. % 76.04/76.30 108822[54:Res:108819.0,60.0] || -> node2(s49,s48)*. % 76.04/76.30 108823[54:SSi:108820.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s48)*. % 76.04/76.30 108824[54:Res:108822.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 108827[54:SoR:108824.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 108829[54:SoR:108827.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)* xuntil6(s49). % 76.04/76.30 108830[54:SSi:108829.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s48,c_busy)* xuntil6(s49). % 76.04/76.30 108831[55:Spt:108830.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 108833[55:Res:108831.0,61.1] always3(s48) || -> . % 76.04/76.30 108834[55:SSi:108833.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.30 108835[55:Spt:108834.0,108830.1,108831.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.04/76.30 108836[55:Spt:108834.0,108830.0,108830.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 108840[55:MRR:108827.2,108835.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 108841[55:Res:53.1,108836.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 108843[55:MRR:108841.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 108844[55:MRR:108823.0,108843.0] || -> until2p7(s48)*. % 76.04/76.30 108845[55:MRR:559.0,108844.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 108846[56:Spt:108845.0] || -> until2p7(s49)*. % 76.04/76.30 108847[56:MRR:194.0,108846.0] || -> node4(s49)*. % 76.04/76.30 108848[56:MRR:108840.0,108847.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 108849[56:Res:53.1,108848.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 108851[56:MRR:108849.0,78381.0] || -> . % 76.04/76.30 108852[56:Spt:108851.0,108845.0,108846.0] || until2p7(s49)*+ -> . % 76.04/76.30 108853[56:Spt:108851.0,108845.1] || -> node4(s48)*. % 76.04/76.30 108854[56:MRR:78384.0,108853.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 108857[56:Res:53.1,108854.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 108859[56:MRR:108857.0,108835.0] || -> . % 76.04/76.30 108860[54:Spt:108859.0,108816.0,108819.0] || trans(s49,s48)*+ -> . % 76.04/76.30 108861[54:Spt:108859.0,108816.1,108816.2,108816.3,108816.4,108816.5,108816.6,108816.7,108816.8,108816.9,108816.10,108816.11,108816.12,108816.13,108816.14,108816.15,108816.16,108816.17,108816.18,108816.19,108816.20,108816.21,108816.22,108816.23,108816.24,108816.25,108816.26,108816.27,108816.28,108816.29,108816.30,108816.31,108816.32,108816.33,108816.34,108816.35,108816.36,108816.37,108816.38,108816.39,108816.40,108816.41,108816.42,108816.43,108816.44,108816.45] || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.30 108863[54:MRR:108818.1,108860.0] xuntil6(s49) || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.30 108864[55:Spt:108861.0] || -> trans(s49,s47)*. % 76.04/76.30 108865[55:Res:108864.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s47)*. % 76.04/76.30 108867[55:Res:108864.0,60.0] || -> node2(s49,s47)*. % 76.04/76.30 108868[55:SSi:108865.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s47)*. % 76.04/76.30 108869[55:Res:108867.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 108881[55:SoR:108869.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 108883[55:SoR:108881.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 76.04/76.30 108884[55:SSi:108883.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 76.04/76.30 108885[56:Spt:108884.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 108887[56:Res:108885.0,61.1] always3(s47) || -> . % 76.04/76.30 108888[56:SSi:108887.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.30 108889[56:Spt:108888.0,108884.1,108885.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.04/76.30 108890[56:Spt:108888.0,108884.0,108884.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 108894[56:MRR:108881.2,108889.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 108895[56:Res:53.1,108890.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 108897[56:MRR:108895.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 108898[56:MRR:108868.0,108897.0] || -> until2p7(s47)*. % 76.04/76.30 108899[56:MRR:554.0,108898.0] || -> until2p7(s48)* node4(s47). % 76.04/76.30 108900[57:Spt:108899.0] || -> until2p7(s48)*. % 76.04/76.30 108901[57:MRR:559.0,108900.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 108902[58:Spt:108901.0] || -> until2p7(s49)*. % 76.04/76.30 108903[58:MRR:194.0,108902.0] || -> node4(s49)*. % 76.04/76.30 108904[58:MRR:108894.0,108903.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 108905[58:Res:53.1,108904.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 108907[58:MRR:108905.0,78381.0] || -> . % 76.04/76.30 108908[58:Spt:108907.0,108901.0,108902.0] || until2p7(s49)*+ -> . % 76.04/76.30 108909[58:Spt:108907.0,108901.1] || -> node4(s48)*. % 76.04/76.30 108910[58:MRR:78384.0,108909.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 108913[58:Res:53.1,108910.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 108916[58:Res:108913.0,61.1] always3(s48) || -> . % 76.04/76.30 108917[58:SSi:108916.0,78281.0,78387.0,108798.0,108900.0,108909.0] || -> . % 76.04/76.30 108918[57:Spt:108917.0,108899.0,108900.0] || until2p7(s48)*+ -> . % 76.04/76.30 108919[57:Spt:108917.0,108899.1] || -> node4(s47)*. % 76.04/76.30 108921[57:MRR:777.0,108919.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.30 108936[57:Res:53.1,108921.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.30 108938[57:MRR:108936.0,108889.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 108940[57:Res:108938.0,61.1] always3(s48) || -> . % 76.04/76.30 108941[57:SSi:108940.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.30 108942[55:Spt:108941.0,108861.0,108864.0] || trans(s49,s47)*+ -> . % 76.04/76.30 108943[55:Spt:108941.0,108861.1,108861.2,108861.3,108861.4,108861.5,108861.6,108861.7,108861.8,108861.9,108861.10,108861.11,108861.12,108861.13,108861.14,108861.15,108861.16,108861.17,108861.18,108861.19,108861.20,108861.21,108861.22,108861.23,108861.24,108861.25,108861.26,108861.27,108861.28,108861.29,108861.30,108861.31,108861.32,108861.33,108861.34,108861.35,108861.36,108861.37,108861.38,108861.39,108861.40,108861.41,108861.42,108861.43,108861.44] || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.30 108945[55:MRR:108863.1,108942.0] xuntil6(s49) || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.30 108946[56:Spt:108943.0] || -> trans(s49,s46)*. % 76.04/76.30 108947[56:Res:108946.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s46)*. % 76.04/76.30 108949[56:Res:108946.0,60.0] || -> node2(s49,s46)*. % 76.04/76.30 108950[56:SSi:108947.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s46)*. % 76.04/76.30 108951[56:Res:108949.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 108967[56:SoR:108951.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 108969[56:SoR:108967.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)* xuntil6(s49). % 76.04/76.30 108970[56:SSi:108969.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s46,c_busy)* xuntil6(s49). % 76.04/76.30 108971[57:Spt:108970.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 108973[57:Res:108971.0,61.1] always3(s46) || -> . % 76.04/76.30 108974[57:SSi:108973.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.30 108975[57:Spt:108974.0,108970.1,108971.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.04/76.30 108976[57:Spt:108974.0,108970.0,108970.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 108980[57:MRR:108967.2,108975.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 108981[57:Res:53.1,108976.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 108983[57:MRR:108981.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 108984[57:MRR:108950.0,108983.0] || -> until2p7(s46)*. % 76.04/76.30 108985[57:MRR:549.0,108984.0] || -> until2p7(s47)* node4(s46). % 76.04/76.30 108986[58:Spt:108985.0] || -> until2p7(s47)*. % 76.04/76.30 108987[58:MRR:554.0,108986.0] || -> until2p7(s48)* node4(s47). % 76.04/76.30 108988[59:Spt:108987.0] || -> until2p7(s48)*. % 76.04/76.30 108989[59:MRR:559.0,108988.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 108990[60:Spt:108989.0] || -> until2p7(s49)*. % 76.04/76.30 108991[60:MRR:194.0,108990.0] || -> node4(s49)*. % 76.04/76.30 108992[60:MRR:108980.0,108991.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 108993[60:Res:53.1,108992.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 108995[60:MRR:108993.0,78381.0] || -> . % 76.04/76.30 108996[60:Spt:108995.0,108989.0,108990.0] || until2p7(s49)*+ -> . % 76.04/76.30 108997[60:Spt:108995.0,108989.1] || -> node4(s48)*. % 76.04/76.30 108998[60:MRR:78384.0,108997.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 109001[60:Res:53.1,108998.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 109004[60:Res:109001.0,61.1] always3(s48) || -> . % 76.04/76.30 109005[60:SSi:109004.0,78281.0,78387.0,108798.0,108988.0,108997.0] || -> . % 76.04/76.30 109006[59:Spt:109005.0,108987.0,108988.0] || until2p7(s48)*+ -> . % 76.04/76.30 109007[59:Spt:109005.0,108987.1] || -> node4(s47)*. % 76.04/76.30 109009[59:MRR:777.0,109007.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.30 109024[59:Res:53.1,109009.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.30 109029[60:Spt:109024.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 109031[60:Res:109029.0,61.1] always3(s47) || -> . % 76.04/76.30 109032[60:SSi:109031.0,78277.0,78280.0,108797.0,108986.0,109007.0] || -> . % 76.04/76.30 109033[60:Spt:109032.0,109024.0,109029.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.30 109034[60:Spt:109032.0,109024.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 109038[60:Res:109034.0,61.1] always3(s48) || -> . % 76.04/76.30 109039[60:SSi:109038.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.30 109040[58:Spt:109039.0,108985.0,108986.0] || until2p7(s47)*+ -> . % 76.04/76.30 109041[58:Spt:109039.0,108985.1] || -> node4(s46)*. % 76.04/76.30 109043[58:MRR:780.0,109041.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.30 109050[58:Res:53.1,109043.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.30 109052[58:MRR:109050.0,108975.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 109054[58:Res:109052.0,61.1] always3(s47) || -> . % 76.04/76.30 109055[58:SSi:109054.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.30 109056[56:Spt:109055.0,108943.0,108946.0] || trans(s49,s46)*+ -> . % 76.04/76.30 109057[56:Spt:109055.0,108943.1,108943.2,108943.3,108943.4,108943.5,108943.6,108943.7,108943.8,108943.9,108943.10,108943.11,108943.12,108943.13,108943.14,108943.15,108943.16,108943.17,108943.18,108943.19,108943.20,108943.21,108943.22,108943.23,108943.24,108943.25,108943.26,108943.27,108943.28,108943.29,108943.30,108943.31,108943.32,108943.33,108943.34,108943.35,108943.36,108943.37,108943.38,108943.39,108943.40,108943.41,108943.42,108943.43] || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.30 109059[56:MRR:108945.1,109056.0] xuntil6(s49) || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.30 109060[57:Spt:109057.0] || -> trans(s49,s45)*. % 76.04/76.30 109061[57:Res:109060.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s45)*. % 76.04/76.30 109063[57:Res:109060.0,60.0] || -> node2(s49,s45)*. % 76.04/76.30 109064[57:SSi:109061.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s45)*. % 76.04/76.30 109065[57:Res:109063.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 109081[57:SoR:109065.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 109083[57:SoR:109081.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)* xuntil6(s49). % 76.04/76.30 109084[57:SSi:109083.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s45,c_busy)* xuntil6(s49). % 76.04/76.30 109085[58:Spt:109084.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 109087[58:Res:109085.0,61.1] always3(s45) || -> . % 76.04/76.30 109088[58:SSi:109087.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.30 109089[58:Spt:109088.0,109084.1,109085.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.04/76.30 109090[58:Spt:109088.0,109084.0,109084.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 109094[58:MRR:109081.2,109089.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 109095[58:Res:53.1,109090.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 109097[58:MRR:109095.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 109098[58:MRR:109064.0,109097.0] || -> until2p7(s45)*. % 76.04/76.30 109099[58:MRR:544.0,109098.0] || -> until2p7(s46)* node4(s45). % 76.04/76.30 109100[59:Spt:109099.0] || -> until2p7(s46)*. % 76.04/76.30 109101[59:MRR:549.0,109100.0] || -> until2p7(s47)* node4(s46). % 76.04/76.30 109102[60:Spt:109101.0] || -> until2p7(s47)*. % 76.04/76.30 109103[60:MRR:554.0,109102.0] || -> until2p7(s48)* node4(s47). % 76.04/76.30 109104[61:Spt:109103.0] || -> until2p7(s48)*. % 76.04/76.30 109105[61:MRR:559.0,109104.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 109106[62:Spt:109105.0] || -> until2p7(s49)*. % 76.04/76.30 109107[62:MRR:194.0,109106.0] || -> node4(s49)*. % 76.04/76.30 109108[62:MRR:109094.0,109107.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 109109[62:Res:53.1,109108.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 109111[62:MRR:109109.0,78381.0] || -> . % 76.04/76.30 109112[62:Spt:109111.0,109105.0,109106.0] || until2p7(s49)*+ -> . % 76.04/76.30 109113[62:Spt:109111.0,109105.1] || -> node4(s48)*. % 76.04/76.30 109114[62:MRR:78384.0,109113.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 109117[62:Res:53.1,109114.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 109120[62:Res:109117.0,61.1] always3(s48) || -> . % 76.04/76.30 109121[62:SSi:109120.0,78281.0,78387.0,108798.0,109104.0,109113.0] || -> . % 76.04/76.30 109122[61:Spt:109121.0,109103.0,109104.0] || until2p7(s48)*+ -> . % 76.04/76.30 109123[61:Spt:109121.0,109103.1] || -> node4(s47)*. % 76.04/76.30 109125[61:MRR:777.0,109123.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.30 109143[61:Res:53.1,109125.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.30 109145[62:Spt:109143.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 109147[62:Res:109145.0,61.1] always3(s47) || -> . % 76.04/76.30 109148[62:SSi:109147.0,78277.0,78280.0,108797.0,109102.0,109123.0] || -> . % 76.04/76.30 109149[62:Spt:109148.0,109143.0,109145.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.30 109150[62:Spt:109148.0,109143.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 109154[62:Res:109150.0,61.1] always3(s48) || -> . % 76.04/76.30 109155[62:SSi:109154.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.30 109156[60:Spt:109155.0,109101.0,109102.0] || until2p7(s47)*+ -> . % 76.04/76.30 109157[60:Spt:109155.0,109101.1] || -> node4(s46)*. % 76.04/76.30 109159[60:MRR:780.0,109157.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.30 109166[60:Res:53.1,109159.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.30 109171[61:Spt:109166.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 109173[61:Res:109171.0,61.1] always3(s46) || -> . % 76.04/76.30 109174[61:SSi:109173.0,78272.0,78276.0,108796.0,109100.0,109157.0] || -> . % 76.04/76.30 109175[61:Spt:109174.0,109166.0,109171.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.30 109176[61:Spt:109174.0,109166.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 109180[61:Res:109176.0,61.1] always3(s47) || -> . % 76.04/76.30 109181[61:SSi:109180.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.30 109182[59:Spt:109181.0,109099.0,109100.0] || until2p7(s46)*+ -> . % 76.04/76.30 109183[59:Spt:109181.0,109099.1] || -> node4(s45)*. % 76.04/76.30 109185[59:MRR:783.0,109183.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.30 109188[59:Res:53.1,109185.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.30 109190[59:MRR:109188.0,109089.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 109192[59:Res:109190.0,61.1] always3(s46) || -> . % 76.04/76.30 109193[59:SSi:109192.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.30 109194[57:Spt:109193.0,109057.0,109060.0] || trans(s49,s45)*+ -> . % 76.04/76.30 109195[57:Spt:109193.0,109057.1,109057.2,109057.3,109057.4,109057.5,109057.6,109057.7,109057.8,109057.9,109057.10,109057.11,109057.12,109057.13,109057.14,109057.15,109057.16,109057.17,109057.18,109057.19,109057.20,109057.21,109057.22,109057.23,109057.24,109057.25,109057.26,109057.27,109057.28,109057.29,109057.30,109057.31,109057.32,109057.33,109057.34,109057.35,109057.36,109057.37,109057.38,109057.39,109057.40,109057.41,109057.42] || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.30 109197[57:MRR:109059.1,109194.0] xuntil6(s49) || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.30 109198[58:Spt:109195.0] || -> trans(s49,s44)*. % 76.04/76.30 109199[58:Res:109198.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s44)*. % 76.04/76.30 109201[58:Res:109198.0,60.0] || -> node2(s49,s44)*. % 76.04/76.30 109202[58:SSi:109199.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s44)*. % 76.04/76.30 109203[58:Res:109201.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 109223[58:SoR:109203.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 109225[58:SoR:109223.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)* xuntil6(s49). % 76.04/76.30 109226[58:SSi:109225.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s44,c_busy)* xuntil6(s49). % 76.04/76.30 109227[59:Spt:109226.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.30 109229[59:Res:109227.0,61.1] always3(s44) || -> . % 76.04/76.30 109230[59:SSi:109229.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.30 109231[59:Spt:109230.0,109226.1,109227.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.04/76.30 109232[59:Spt:109230.0,109226.0,109226.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 109236[59:MRR:109223.2,109231.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 109237[59:Res:53.1,109232.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 109239[59:MRR:109237.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 109240[59:MRR:109202.0,109239.0] || -> until2p7(s44)*. % 76.04/76.30 109241[59:MRR:539.0,109240.0] || -> until2p7(s45)* node4(s44). % 76.04/76.30 109242[60:Spt:109241.0] || -> until2p7(s45)*. % 76.04/76.30 109243[60:MRR:544.0,109242.0] || -> until2p7(s46)* node4(s45). % 76.04/76.30 109244[61:Spt:109243.0] || -> until2p7(s46)*. % 76.04/76.30 109245[61:MRR:549.0,109244.0] || -> until2p7(s47)* node4(s46). % 76.04/76.30 109246[62:Spt:109245.0] || -> until2p7(s47)*. % 76.04/76.30 109247[62:MRR:554.0,109246.0] || -> until2p7(s48)* node4(s47). % 76.04/76.30 109248[63:Spt:109247.0] || -> until2p7(s48)*. % 76.04/76.30 109249[63:MRR:559.0,109248.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 109250[64:Spt:109249.0] || -> until2p7(s49)*. % 76.04/76.30 109251[64:MRR:194.0,109250.0] || -> node4(s49)*. % 76.04/76.30 109252[64:MRR:109236.0,109251.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 109256[64:Res:53.1,109252.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 109258[64:MRR:109256.0,78381.0] || -> . % 76.04/76.30 109259[64:Spt:109258.0,109249.0,109250.0] || until2p7(s49)*+ -> . % 76.04/76.30 109260[64:Spt:109258.0,109249.1] || -> node4(s48)*. % 76.04/76.30 109261[64:MRR:78384.0,109260.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 109264[64:Res:53.1,109261.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 109267[64:Res:109264.0,61.1] always3(s48) || -> . % 76.04/76.30 109268[64:SSi:109267.0,78281.0,78387.0,108798.0,109248.0,109260.0] || -> . % 76.04/76.30 109269[63:Spt:109268.0,109247.0,109248.0] || until2p7(s48)*+ -> . % 76.04/76.30 109270[63:Spt:109268.0,109247.1] || -> node4(s47)*. % 76.04/76.30 109272[63:MRR:777.0,109270.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.30 109284[63:Res:53.1,109272.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.30 109286[64:Spt:109284.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 109288[64:Res:109286.0,61.1] always3(s47) || -> . % 76.04/76.30 109289[64:SSi:109288.0,78277.0,78280.0,108797.0,109246.0,109270.0] || -> . % 76.04/76.30 109290[64:Spt:109289.0,109284.0,109286.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.30 109291[64:Spt:109289.0,109284.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 109295[64:Res:109291.0,61.1] always3(s48) || -> . % 76.04/76.30 109296[64:SSi:109295.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.30 109297[62:Spt:109296.0,109245.0,109246.0] || until2p7(s47)*+ -> . % 76.04/76.30 109298[62:Spt:109296.0,109245.1] || -> node4(s46)*. % 76.04/76.30 109300[62:MRR:780.0,109298.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.30 109307[62:Res:53.1,109300.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.30 109312[63:Spt:109307.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 109314[63:Res:109312.0,61.1] always3(s46) || -> . % 76.04/76.30 109315[63:SSi:109314.0,78272.0,78276.0,108796.0,109244.0,109298.0] || -> . % 76.04/76.30 109316[63:Spt:109315.0,109307.0,109312.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.30 109317[63:Spt:109315.0,109307.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 109321[63:Res:109317.0,61.1] always3(s47) || -> . % 76.04/76.30 109322[63:SSi:109321.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.30 109323[61:Spt:109322.0,109243.0,109244.0] || until2p7(s46)*+ -> . % 76.04/76.30 109324[61:Spt:109322.0,109243.1] || -> node4(s45)*. % 76.04/76.30 109326[61:MRR:783.0,109324.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.30 109329[61:Res:53.1,109326.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.30 109331[62:Spt:109329.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 109333[62:Res:109331.0,61.1] always3(s45) || -> . % 76.04/76.30 109334[62:SSi:109333.0,78268.0,78271.0,108795.0,109242.0,109324.0] || -> . % 76.04/76.30 109335[62:Spt:109334.0,109329.0,109331.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.30 109336[62:Spt:109334.0,109329.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.30 109340[62:Res:109336.0,61.1] always3(s46) || -> . % 76.04/76.30 109341[62:SSi:109340.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.30 109342[60:Spt:109341.0,109241.0,109242.0] || until2p7(s45)*+ -> . % 76.04/76.30 109343[60:Spt:109341.0,109241.1] || -> node4(s44)*. % 76.04/76.30 109345[60:MRR:786.0,109343.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.30 109348[60:Res:53.1,109345.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.30 109350[60:MRR:109348.0,109231.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.30 109352[60:Res:109350.0,61.1] always3(s45) || -> . % 76.04/76.30 109353[60:SSi:109352.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.30 109354[58:Spt:109353.0,109195.0,109198.0] || trans(s49,s44)*+ -> . % 76.04/76.30 109355[58:Spt:109353.0,109195.1,109195.2,109195.3,109195.4,109195.5,109195.6,109195.7,109195.8,109195.9,109195.10,109195.11,109195.12,109195.13,109195.14,109195.15,109195.16,109195.17,109195.18,109195.19,109195.20,109195.21,109195.22,109195.23,109195.24,109195.25,109195.26,109195.27,109195.28,109195.29,109195.30,109195.31,109195.32,109195.33,109195.34,109195.35,109195.36,109195.37,109195.38,109195.39,109195.40,109195.41] || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.30 109357[58:MRR:109197.1,109354.0] xuntil6(s49) || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.30 109358[59:Spt:109355.0] || -> trans(s49,s43)*. % 76.04/76.30 109359[59:Res:109358.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s43)*. % 76.04/76.30 109361[59:Res:109358.0,60.0] || -> node2(s49,s43)*. % 76.04/76.30 109362[59:SSi:109359.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s43)*. % 76.04/76.30 109363[59:Res:109361.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 109387[59:SoR:109363.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 109389[59:SoR:109387.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 76.04/76.30 109390[59:SSi:109389.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 76.04/76.30 109391[60:Spt:109390.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.30 109393[60:Res:109391.0,61.1] always3(s43) || -> . % 76.04/76.30 109394[60:SSi:109393.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.30 109395[60:Spt:109394.0,109390.1,109391.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.04/76.30 109396[60:Spt:109394.0,109390.0,109390.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.30 109400[60:MRR:109387.2,109395.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.30 109401[60:Res:53.1,109396.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.30 109403[60:MRR:109401.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.30 109404[60:MRR:109362.0,109403.0] || -> until2p7(s43)*. % 76.04/76.30 109405[60:MRR:241.0,109404.0] || -> until2p7(s44)* node4(s43). % 76.04/76.30 109406[61:Spt:109405.0] || -> until2p7(s44)*. % 76.04/76.30 109407[61:MRR:539.0,109406.0] || -> until2p7(s45)* node4(s44). % 76.04/76.30 109408[62:Spt:109407.0] || -> until2p7(s45)*. % 76.04/76.30 109409[62:MRR:544.0,109408.0] || -> until2p7(s46)* node4(s45). % 76.04/76.30 109410[63:Spt:109409.0] || -> until2p7(s46)*. % 76.04/76.30 109411[63:MRR:549.0,109410.0] || -> until2p7(s47)* node4(s46). % 76.04/76.30 109412[64:Spt:109411.0] || -> until2p7(s47)*. % 76.04/76.30 109413[64:MRR:554.0,109412.0] || -> until2p7(s48)* node4(s47). % 76.04/76.30 109414[65:Spt:109413.0] || -> until2p7(s48)*. % 76.04/76.30 109415[65:MRR:559.0,109414.0] || -> until2p7(s49)* node4(s48). % 76.04/76.30 109416[66:Spt:109415.0] || -> until2p7(s49)*. % 76.04/76.30 109417[66:MRR:194.0,109416.0] || -> node4(s49)*. % 76.04/76.30 109418[66:MRR:109400.0,109417.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.30 109419[66:Res:53.1,109418.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.30 109421[66:MRR:109419.0,78381.0] || -> . % 76.04/76.30 109422[66:Spt:109421.0,109415.0,109416.0] || until2p7(s49)*+ -> . % 76.04/76.30 109423[66:Spt:109421.0,109415.1] || -> node4(s48)*. % 76.04/76.30 109424[66:MRR:78384.0,109423.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.30 109427[66:Res:53.1,109424.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 109430[66:Res:109427.0,61.1] always3(s48) || -> . % 76.04/76.30 109431[66:SSi:109430.0,78281.0,78387.0,108798.0,109414.0,109423.0] || -> . % 76.04/76.30 109432[65:Spt:109431.0,109413.0,109414.0] || until2p7(s48)*+ -> . % 76.04/76.30 109433[65:Spt:109431.0,109413.1] || -> node4(s47)*. % 76.04/76.30 109435[65:MRR:777.0,109433.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.30 109453[65:Res:53.1,109435.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.30 109455[66:Spt:109453.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.30 109457[66:Res:109455.0,61.1] always3(s47) || -> . % 76.04/76.30 109458[66:SSi:109457.0,78277.0,78280.0,108797.0,109412.0,109433.0] || -> . % 76.04/76.30 109459[66:Spt:109458.0,109453.0,109455.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.30 109460[66:Spt:109458.0,109453.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.30 109464[66:Res:109460.0,61.1] always3(s48) || -> . % 76.04/76.31 109465[66:SSi:109464.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 109466[64:Spt:109465.0,109411.0,109412.0] || until2p7(s47)*+ -> . % 76.04/76.31 109467[64:Spt:109465.0,109411.1] || -> node4(s46)*. % 76.04/76.31 109469[64:MRR:780.0,109467.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 109476[64:Res:53.1,109469.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 109481[65:Spt:109476.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 109483[65:Res:109481.0,61.1] always3(s46) || -> . % 76.04/76.31 109484[65:SSi:109483.0,78272.0,78276.0,108796.0,109410.0,109467.0] || -> . % 76.04/76.31 109485[65:Spt:109484.0,109476.0,109481.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 109486[65:Spt:109484.0,109476.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 109490[65:Res:109486.0,61.1] always3(s47) || -> . % 76.04/76.31 109491[65:SSi:109490.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 109492[63:Spt:109491.0,109409.0,109410.0] || until2p7(s46)*+ -> . % 76.04/76.31 109493[63:Spt:109491.0,109409.1] || -> node4(s45)*. % 76.04/76.31 109495[63:MRR:783.0,109493.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 109498[63:Res:53.1,109495.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 109500[64:Spt:109498.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 109502[64:Res:109500.0,61.1] always3(s45) || -> . % 76.04/76.31 109503[64:SSi:109502.0,78268.0,78271.0,108795.0,109408.0,109493.0] || -> . % 76.04/76.31 109504[64:Spt:109503.0,109498.0,109500.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 109505[64:Spt:109503.0,109498.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 109509[64:Res:109505.0,61.1] always3(s46) || -> . % 76.04/76.31 109510[64:SSi:109509.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 109511[62:Spt:109510.0,109407.0,109408.0] || until2p7(s45)*+ -> . % 76.04/76.31 109512[62:Spt:109510.0,109407.1] || -> node4(s44)*. % 76.04/76.31 109514[62:MRR:786.0,109512.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 109517[62:Res:53.1,109514.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 109519[63:Spt:109517.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 109521[63:Res:109519.0,61.1] always3(s44) || -> . % 76.04/76.31 109522[63:SSi:109521.0,78263.0,78267.0,108794.0,109406.0,109512.0] || -> . % 76.04/76.31 109523[63:Spt:109522.0,109517.0,109519.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 109524[63:Spt:109522.0,109517.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 109528[63:Res:109524.0,61.1] always3(s45) || -> . % 76.04/76.31 109529[63:SSi:109528.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 109530[61:Spt:109529.0,109405.0,109406.0] || until2p7(s44)*+ -> . % 76.04/76.31 109531[61:Spt:109529.0,109405.1] || -> node4(s43)*. % 76.04/76.31 109533[61:MRR:789.0,109531.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 109536[61:Res:53.1,109533.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 109538[61:MRR:109536.0,109395.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 109540[61:Res:109538.0,61.1] always3(s44) || -> . % 76.04/76.31 109541[61:SSi:109540.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 109542[59:Spt:109541.0,109355.0,109358.0] || trans(s49,s43)*+ -> . % 76.04/76.31 109543[59:Spt:109541.0,109355.1,109355.2,109355.3,109355.4,109355.5,109355.6,109355.7,109355.8,109355.9,109355.10,109355.11,109355.12,109355.13,109355.14,109355.15,109355.16,109355.17,109355.18,109355.19,109355.20,109355.21,109355.22,109355.23,109355.24,109355.25,109355.26,109355.27,109355.28,109355.29,109355.30,109355.31,109355.32,109355.33,109355.34,109355.35,109355.36,109355.37,109355.38,109355.39,109355.40] || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 109545[59:MRR:109357.1,109542.0] xuntil6(s49) || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 109546[60:Spt:109543.0] || -> trans(s49,s42)*. % 76.04/76.31 109547[60:Res:109546.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s42)*. % 76.04/76.31 109549[60:Res:109546.0,60.0] || -> node2(s49,s42)*. % 76.04/76.31 109550[60:SSi:109547.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s42)*. % 76.04/76.31 109551[60:Res:109549.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 109579[60:SoR:109551.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 109581[60:SoR:109579.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)* xuntil6(s49). % 76.04/76.31 109582[60:SSi:109581.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s42,c_busy)* xuntil6(s49). % 76.04/76.31 109583[61:Spt:109582.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 109585[61:Res:109583.0,61.1] always3(s42) || -> . % 76.04/76.31 109586[61:SSi:109585.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 109587[61:Spt:109586.0,109582.1,109583.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.04/76.31 109588[61:Spt:109586.0,109582.0,109582.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 109592[61:MRR:109579.2,109587.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 109593[61:Res:53.1,109588.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 109595[61:MRR:109593.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 109596[61:MRR:109550.0,109595.0] || -> until2p7(s42)*. % 76.04/76.31 109597[61:MRR:240.0,109596.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 109598[62:Spt:109597.0] || -> until2p7(s43)*. % 76.04/76.31 109599[62:MRR:241.0,109598.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 109600[63:Spt:109599.0] || -> until2p7(s44)*. % 76.04/76.31 109601[63:MRR:539.0,109600.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 109602[64:Spt:109601.0] || -> until2p7(s45)*. % 76.04/76.31 109603[64:MRR:544.0,109602.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 109604[65:Spt:109603.0] || -> until2p7(s46)*. % 76.04/76.31 109605[65:MRR:549.0,109604.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 109606[66:Spt:109605.0] || -> until2p7(s47)*. % 76.04/76.31 109607[66:MRR:554.0,109606.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 109608[67:Spt:109607.0] || -> until2p7(s48)*. % 76.04/76.31 109609[67:MRR:559.0,109608.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 109610[68:Spt:109609.0] || -> until2p7(s49)*. % 76.04/76.31 109611[68:MRR:194.0,109610.0] || -> node4(s49)*. % 76.04/76.31 109612[68:MRR:109592.0,109611.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 109613[68:Res:53.1,109612.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 109615[68:MRR:109613.0,78381.0] || -> . % 76.04/76.31 109616[68:Spt:109615.0,109609.0,109610.0] || until2p7(s49)*+ -> . % 76.04/76.31 109617[68:Spt:109615.0,109609.1] || -> node4(s48)*. % 76.04/76.31 109618[68:MRR:78384.0,109617.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 109621[68:Res:53.1,109618.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 109624[68:Res:109621.0,61.1] always3(s48) || -> . % 76.04/76.31 109625[68:SSi:109624.0,78281.0,78387.0,108798.0,109608.0,109617.0] || -> . % 76.04/76.31 109626[67:Spt:109625.0,109607.0,109608.0] || until2p7(s48)*+ -> . % 76.04/76.31 109627[67:Spt:109625.0,109607.1] || -> node4(s47)*. % 76.04/76.31 109629[67:MRR:777.0,109627.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 109644[67:Res:53.1,109629.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 109649[68:Spt:109644.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 109651[68:Res:109649.0,61.1] always3(s47) || -> . % 76.04/76.31 109652[68:SSi:109651.0,78277.0,78280.0,108797.0,109606.0,109627.0] || -> . % 76.04/76.31 109653[68:Spt:109652.0,109644.0,109649.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 109654[68:Spt:109652.0,109644.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 109658[68:Res:109654.0,61.1] always3(s48) || -> . % 76.04/76.31 109659[68:SSi:109658.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 109660[66:Spt:109659.0,109605.0,109606.0] || until2p7(s47)*+ -> . % 76.04/76.31 109661[66:Spt:109659.0,109605.1] || -> node4(s46)*. % 76.04/76.31 109663[66:MRR:780.0,109661.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 109670[66:Res:53.1,109663.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 109672[67:Spt:109670.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 109674[67:Res:109672.0,61.1] always3(s46) || -> . % 76.04/76.31 109675[67:SSi:109674.0,78272.0,78276.0,108796.0,109604.0,109661.0] || -> . % 76.04/76.31 109676[67:Spt:109675.0,109670.0,109672.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 109677[67:Spt:109675.0,109670.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 109681[67:Res:109677.0,61.1] always3(s47) || -> . % 76.04/76.31 109682[67:SSi:109681.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 109683[65:Spt:109682.0,109603.0,109604.0] || until2p7(s46)*+ -> . % 76.04/76.31 109684[65:Spt:109682.0,109603.1] || -> node4(s45)*. % 76.04/76.31 109686[65:MRR:783.0,109684.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 109689[65:Res:53.1,109686.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 109694[66:Spt:109689.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 109696[66:Res:109694.0,61.1] always3(s45) || -> . % 76.04/76.31 109697[66:SSi:109696.0,78268.0,78271.0,108795.0,109602.0,109684.0] || -> . % 76.04/76.31 109698[66:Spt:109697.0,109689.0,109694.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 109699[66:Spt:109697.0,109689.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 109703[66:Res:109699.0,61.1] always3(s46) || -> . % 76.04/76.31 109704[66:SSi:109703.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 109705[64:Spt:109704.0,109601.0,109602.0] || until2p7(s45)*+ -> . % 76.04/76.31 109706[64:Spt:109704.0,109601.1] || -> node4(s44)*. % 76.04/76.31 109708[64:MRR:786.0,109706.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 109711[64:Res:53.1,109708.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 109713[65:Spt:109711.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 109715[65:Res:109713.0,61.1] always3(s44) || -> . % 76.04/76.31 109716[65:SSi:109715.0,78263.0,78267.0,108794.0,109600.0,109706.0] || -> . % 76.04/76.31 109717[65:Spt:109716.0,109711.0,109713.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 109718[65:Spt:109716.0,109711.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 109722[65:Res:109718.0,61.1] always3(s45) || -> . % 76.04/76.31 109723[65:SSi:109722.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 109724[63:Spt:109723.0,109599.0,109600.0] || until2p7(s44)*+ -> . % 76.04/76.31 109725[63:Spt:109723.0,109599.1] || -> node4(s43)*. % 76.04/76.31 109727[63:MRR:789.0,109725.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 109730[63:Res:53.1,109727.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 109732[64:Spt:109730.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 109734[64:Res:109732.0,61.1] always3(s43) || -> . % 76.04/76.31 109735[64:SSi:109734.0,78259.0,78262.0,108793.0,109598.0,109725.0] || -> . % 76.04/76.31 109736[64:Spt:109735.0,109730.0,109732.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 109737[64:Spt:109735.0,109730.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 109741[64:Res:109737.0,61.1] always3(s44) || -> . % 76.04/76.31 109742[64:SSi:109741.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 109743[62:Spt:109742.0,109597.0,109598.0] || until2p7(s43)*+ -> . % 76.04/76.31 109744[62:Spt:109742.0,109597.1] || -> node4(s42)*. % 76.04/76.31 109746[62:MRR:792.0,109744.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 109749[62:Res:53.1,109746.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 109751[62:MRR:109749.0,109587.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 109753[62:Res:109751.0,61.1] always3(s43) || -> . % 76.04/76.31 109754[62:SSi:109753.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 109755[60:Spt:109754.0,109543.0,109546.0] || trans(s49,s42)*+ -> . % 76.04/76.31 109756[60:Spt:109754.0,109543.1,109543.2,109543.3,109543.4,109543.5,109543.6,109543.7,109543.8,109543.9,109543.10,109543.11,109543.12,109543.13,109543.14,109543.15,109543.16,109543.17,109543.18,109543.19,109543.20,109543.21,109543.22,109543.23,109543.24,109543.25,109543.26,109543.27,109543.28,109543.29,109543.30,109543.31,109543.32,109543.33,109543.34,109543.35,109543.36,109543.37,109543.38,109543.39] || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 109758[60:MRR:109545.1,109755.0] xuntil6(s49) || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 109759[61:Spt:109756.0] || -> trans(s49,s41)*. % 76.04/76.31 109760[61:Res:109759.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s41)*. % 76.04/76.31 109762[61:Res:109759.0,60.0] || -> node2(s49,s41)*. % 76.04/76.31 109763[61:SSi:109760.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s41)*. % 76.04/76.31 109764[61:Res:109762.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 109793[61:SoR:109764.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 109795[61:SoR:109793.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)* xuntil6(s49). % 76.04/76.31 109796[61:SSi:109795.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s41,c_busy)* xuntil6(s49). % 76.04/76.31 109797[62:Spt:109796.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 109799[62:Res:109797.0,61.1] always3(s41) || -> . % 76.04/76.31 109800[62:SSi:109799.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 109801[62:Spt:109800.0,109796.1,109797.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.04/76.31 109802[62:Spt:109800.0,109796.0,109796.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 109806[62:MRR:109793.2,109801.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 109807[62:Res:53.1,109802.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 109809[62:MRR:109807.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 109810[62:MRR:109763.0,109809.0] || -> until2p7(s41)*. % 76.04/76.31 109811[62:MRR:239.0,109810.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 109812[63:Spt:109811.0] || -> until2p7(s42)*. % 76.04/76.31 109813[63:MRR:240.0,109812.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 109814[64:Spt:109813.0] || -> until2p7(s43)*. % 76.04/76.31 109815[64:MRR:241.0,109814.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 109816[65:Spt:109815.0] || -> until2p7(s44)*. % 76.04/76.31 109817[65:MRR:539.0,109816.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 109818[66:Spt:109817.0] || -> until2p7(s45)*. % 76.04/76.31 109819[66:MRR:544.0,109818.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 109820[67:Spt:109819.0] || -> until2p7(s46)*. % 76.04/76.31 109821[67:MRR:549.0,109820.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 109822[68:Spt:109821.0] || -> until2p7(s47)*. % 76.04/76.31 109823[68:MRR:554.0,109822.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 109824[69:Spt:109823.0] || -> until2p7(s48)*. % 76.04/76.31 109825[69:MRR:559.0,109824.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 109826[70:Spt:109825.0] || -> until2p7(s49)*. % 76.04/76.31 109827[70:MRR:194.0,109826.0] || -> node4(s49)*. % 76.04/76.31 109828[70:MRR:109806.0,109827.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 109832[70:Res:53.1,109828.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 109834[70:MRR:109832.0,78381.0] || -> . % 76.04/76.31 109835[70:Spt:109834.0,109825.0,109826.0] || until2p7(s49)*+ -> . % 76.04/76.31 109836[70:Spt:109834.0,109825.1] || -> node4(s48)*. % 76.04/76.31 109837[70:MRR:78384.0,109836.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 109840[70:Res:53.1,109837.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 109843[70:Res:109840.0,61.1] always3(s48) || -> . % 76.04/76.31 109844[70:SSi:109843.0,78281.0,78387.0,108798.0,109824.0,109836.0] || -> . % 76.04/76.31 109845[69:Spt:109844.0,109823.0,109824.0] || until2p7(s48)*+ -> . % 76.04/76.31 109846[69:Spt:109844.0,109823.1] || -> node4(s47)*. % 76.04/76.31 109848[69:MRR:777.0,109846.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 109860[69:Res:53.1,109848.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 109862[70:Spt:109860.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 109864[70:Res:109862.0,61.1] always3(s47) || -> . % 76.04/76.31 109865[70:SSi:109864.0,78277.0,78280.0,108797.0,109822.0,109846.0] || -> . % 76.04/76.31 109866[70:Spt:109865.0,109860.0,109862.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 109867[70:Spt:109865.0,109860.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 109871[70:Res:109867.0,61.1] always3(s48) || -> . % 76.04/76.31 109872[70:SSi:109871.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 109873[68:Spt:109872.0,109821.0,109822.0] || until2p7(s47)*+ -> . % 76.04/76.31 109874[68:Spt:109872.0,109821.1] || -> node4(s46)*. % 76.04/76.31 109876[68:MRR:780.0,109874.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 109883[68:Res:53.1,109876.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 109888[69:Spt:109883.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 109890[69:Res:109888.0,61.1] always3(s46) || -> . % 76.04/76.31 109891[69:SSi:109890.0,78272.0,78276.0,108796.0,109820.0,109874.0] || -> . % 76.04/76.31 109892[69:Spt:109891.0,109883.0,109888.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 109893[69:Spt:109891.0,109883.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 109897[69:Res:109893.0,61.1] always3(s47) || -> . % 76.04/76.31 109898[69:SSi:109897.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 109899[67:Spt:109898.0,109819.0,109820.0] || until2p7(s46)*+ -> . % 76.04/76.31 109900[67:Spt:109898.0,109819.1] || -> node4(s45)*. % 76.04/76.31 109902[67:MRR:783.0,109900.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 109905[67:Res:53.1,109902.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 109907[68:Spt:109905.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 109909[68:Res:109907.0,61.1] always3(s45) || -> . % 76.04/76.31 109910[68:SSi:109909.0,78268.0,78271.0,108795.0,109818.0,109900.0] || -> . % 76.04/76.31 109911[68:Spt:109910.0,109905.0,109907.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 109912[68:Spt:109910.0,109905.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 109916[68:Res:109912.0,61.1] always3(s46) || -> . % 76.04/76.31 109917[68:SSi:109916.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 109918[66:Spt:109917.0,109817.0,109818.0] || until2p7(s45)*+ -> . % 76.04/76.31 109919[66:Spt:109917.0,109817.1] || -> node4(s44)*. % 76.04/76.31 109921[66:MRR:786.0,109919.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 109924[66:Res:53.1,109921.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 109926[67:Spt:109924.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 109928[67:Res:109926.0,61.1] always3(s44) || -> . % 76.04/76.31 109929[67:SSi:109928.0,78263.0,78267.0,108794.0,109816.0,109919.0] || -> . % 76.04/76.31 109930[67:Spt:109929.0,109924.0,109926.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 109931[67:Spt:109929.0,109924.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 109935[67:Res:109931.0,61.1] always3(s45) || -> . % 76.04/76.31 109936[67:SSi:109935.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 109937[65:Spt:109936.0,109815.0,109816.0] || until2p7(s44)*+ -> . % 76.04/76.31 109938[65:Spt:109936.0,109815.1] || -> node4(s43)*. % 76.04/76.31 109940[65:MRR:789.0,109938.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 109943[65:Res:53.1,109940.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 109945[66:Spt:109943.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 109947[66:Res:109945.0,61.1] always3(s43) || -> . % 76.04/76.31 109948[66:SSi:109947.0,78259.0,78262.0,108793.0,109814.0,109938.0] || -> . % 76.04/76.31 109949[66:Spt:109948.0,109943.0,109945.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 109950[66:Spt:109948.0,109943.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 109954[66:Res:109950.0,61.1] always3(s44) || -> . % 76.04/76.31 109955[66:SSi:109954.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 109956[64:Spt:109955.0,109813.0,109814.0] || until2p7(s43)*+ -> . % 76.04/76.31 109957[64:Spt:109955.0,109813.1] || -> node4(s42)*. % 76.04/76.31 109959[64:MRR:792.0,109957.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 109962[64:Res:53.1,109959.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 109967[65:Spt:109962.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 109969[65:Res:109967.0,61.1] always3(s42) || -> . % 76.04/76.31 109970[65:SSi:109969.0,78254.0,78258.0,108792.0,109812.0,109957.0] || -> . % 76.04/76.31 109971[65:Spt:109970.0,109962.0,109967.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 109972[65:Spt:109970.0,109962.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 109976[65:Res:109972.0,61.1] always3(s43) || -> . % 76.04/76.31 109977[65:SSi:109976.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 109978[63:Spt:109977.0,109811.0,109812.0] || until2p7(s42)*+ -> . % 76.04/76.31 109979[63:Spt:109977.0,109811.1] || -> node4(s41)*. % 76.04/76.31 109981[63:MRR:795.0,109979.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 109984[63:Res:53.1,109981.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 109986[63:MRR:109984.0,109801.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 109988[63:Res:109986.0,61.1] always3(s42) || -> . % 76.04/76.31 109989[63:SSi:109988.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 109990[61:Spt:109989.0,109756.0,109759.0] || trans(s49,s41)*+ -> . % 76.04/76.31 109991[61:Spt:109989.0,109756.1,109756.2,109756.3,109756.4,109756.5,109756.6,109756.7,109756.8,109756.9,109756.10,109756.11,109756.12,109756.13,109756.14,109756.15,109756.16,109756.17,109756.18,109756.19,109756.20,109756.21,109756.22,109756.23,109756.24,109756.25,109756.26,109756.27,109756.28,109756.29,109756.30,109756.31,109756.32,109756.33,109756.34,109756.35,109756.36,109756.37,109756.38] || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 109993[61:MRR:109758.1,109990.0] xuntil6(s49) || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 109994[62:Spt:109991.0] || -> trans(s49,s40)*. % 76.04/76.31 109995[62:Res:109994.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s40)*. % 76.04/76.31 109997[62:Res:109994.0,60.0] || -> node2(s49,s40)*. % 76.04/76.31 109998[62:SSi:109995.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s40)*. % 76.04/76.31 109999[62:Res:109997.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 110032[62:SoR:109999.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 110034[62:SoR:110032.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)* xuntil6(s49). % 76.04/76.31 110035[62:SSi:110034.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s40,c_busy)* xuntil6(s49). % 76.04/76.31 110036[63:Spt:110035.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 110038[63:Res:110036.0,61.1] always3(s40) || -> . % 76.04/76.31 110039[63:SSi:110038.0,78245.0,78249.0,108790.0] || -> . % 76.04/76.31 110040[63:Spt:110039.0,110035.1,110036.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.04/76.31 110041[63:Spt:110039.0,110035.0,110035.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 110045[63:MRR:110032.2,110040.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 110046[63:Res:53.1,110041.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 110048[63:MRR:110046.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 110049[63:MRR:109998.0,110048.0] || -> until2p7(s40)*. % 76.04/76.31 110050[63:MRR:238.0,110049.0] || -> until2p7(s41)* node4(s40). % 76.04/76.31 110051[64:Spt:110050.0] || -> until2p7(s41)*. % 76.04/76.31 110052[64:MRR:239.0,110051.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 110053[65:Spt:110052.0] || -> until2p7(s42)*. % 76.04/76.31 110054[65:MRR:240.0,110053.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 110055[66:Spt:110054.0] || -> until2p7(s43)*. % 76.04/76.31 110056[66:MRR:241.0,110055.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 110057[67:Spt:110056.0] || -> until2p7(s44)*. % 76.04/76.31 110058[67:MRR:539.0,110057.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 110059[68:Spt:110058.0] || -> until2p7(s45)*. % 76.04/76.31 110060[68:MRR:544.0,110059.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 110061[69:Spt:110060.0] || -> until2p7(s46)*. % 76.04/76.31 110062[69:MRR:549.0,110061.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 110063[70:Spt:110062.0] || -> until2p7(s47)*. % 76.04/76.31 110064[70:MRR:554.0,110063.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 110065[71:Spt:110064.0] || -> until2p7(s48)*. % 76.04/76.31 110066[71:MRR:559.0,110065.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 110067[72:Spt:110066.0] || -> until2p7(s49)*. % 76.04/76.31 110068[72:MRR:194.0,110067.0] || -> node4(s49)*. % 76.04/76.31 110069[72:MRR:110045.0,110068.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 110070[72:Res:53.1,110069.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 110072[72:MRR:110070.0,78381.0] || -> . % 76.04/76.31 110073[72:Spt:110072.0,110066.0,110067.0] || until2p7(s49)*+ -> . % 76.04/76.31 110074[72:Spt:110072.0,110066.1] || -> node4(s48)*. % 76.04/76.31 110075[72:MRR:78384.0,110074.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 110078[72:Res:53.1,110075.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 110081[72:Res:110078.0,61.1] always3(s48) || -> . % 76.04/76.31 110082[72:SSi:110081.0,78281.0,78387.0,108798.0,110065.0,110074.0] || -> . % 76.04/76.31 110083[71:Spt:110082.0,110064.0,110065.0] || until2p7(s48)*+ -> . % 76.04/76.31 110084[71:Spt:110082.0,110064.1] || -> node4(s47)*. % 76.04/76.31 110086[71:MRR:777.0,110084.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 110101[71:Res:53.1,110086.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 110103[72:Spt:110101.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 110105[72:Res:110103.0,61.1] always3(s47) || -> . % 76.04/76.31 110106[72:SSi:110105.0,78277.0,78280.0,108797.0,110063.0,110084.0] || -> . % 76.04/76.31 110107[72:Spt:110106.0,110101.0,110103.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 110108[72:Spt:110106.0,110101.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 110112[72:Res:110108.0,61.1] always3(s48) || -> . % 76.04/76.31 110113[72:SSi:110112.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 110114[70:Spt:110113.0,110062.0,110063.0] || until2p7(s47)*+ -> . % 76.04/76.31 110115[70:Spt:110113.0,110062.1] || -> node4(s46)*. % 76.04/76.31 110117[70:MRR:780.0,110115.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 110127[70:Res:53.1,110117.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 110129[71:Spt:110127.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 110131[71:Res:110129.0,61.1] always3(s46) || -> . % 76.04/76.31 110132[71:SSi:110131.0,78272.0,78276.0,108796.0,110061.0,110115.0] || -> . % 76.04/76.31 110133[71:Spt:110132.0,110127.0,110129.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 110134[71:Spt:110132.0,110127.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 110138[71:Res:110134.0,61.1] always3(s47) || -> . % 76.04/76.31 110139[71:SSi:110138.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 110140[69:Spt:110139.0,110060.0,110061.0] || until2p7(s46)*+ -> . % 76.04/76.31 110141[69:Spt:110139.0,110060.1] || -> node4(s45)*. % 76.04/76.31 110143[69:MRR:783.0,110141.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 110146[69:Res:53.1,110143.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 110148[70:Spt:110146.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 110150[70:Res:110148.0,61.1] always3(s45) || -> . % 76.04/76.31 110151[70:SSi:110150.0,78268.0,78271.0,108795.0,110059.0,110141.0] || -> . % 76.04/76.31 110152[70:Spt:110151.0,110146.0,110148.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 110153[70:Spt:110151.0,110146.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 110157[70:Res:110153.0,61.1] always3(s46) || -> . % 76.04/76.31 110158[70:SSi:110157.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 110159[68:Spt:110158.0,110058.0,110059.0] || until2p7(s45)*+ -> . % 76.04/76.31 110160[68:Spt:110158.0,110058.1] || -> node4(s44)*. % 76.04/76.31 110162[68:MRR:786.0,110160.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 110165[68:Res:53.1,110162.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 110167[69:Spt:110165.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 110169[69:Res:110167.0,61.1] always3(s44) || -> . % 76.04/76.31 110170[69:SSi:110169.0,78263.0,78267.0,108794.0,110057.0,110160.0] || -> . % 76.04/76.31 110171[69:Spt:110170.0,110165.0,110167.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 110172[69:Spt:110170.0,110165.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 110176[69:Res:110172.0,61.1] always3(s45) || -> . % 76.04/76.31 110177[69:SSi:110176.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 110178[67:Spt:110177.0,110056.0,110057.0] || until2p7(s44)*+ -> . % 76.04/76.31 110179[67:Spt:110177.0,110056.1] || -> node4(s43)*. % 76.04/76.31 110181[67:MRR:789.0,110179.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 110184[67:Res:53.1,110181.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 110189[68:Spt:110184.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 110191[68:Res:110189.0,61.1] always3(s43) || -> . % 76.04/76.31 110192[68:SSi:110191.0,78259.0,78262.0,108793.0,110055.0,110179.0] || -> . % 76.04/76.31 110193[68:Spt:110192.0,110184.0,110189.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 110194[68:Spt:110192.0,110184.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 110198[68:Res:110194.0,61.1] always3(s44) || -> . % 76.04/76.31 110199[68:SSi:110198.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 110200[66:Spt:110199.0,110054.0,110055.0] || until2p7(s43)*+ -> . % 76.04/76.31 110201[66:Spt:110199.0,110054.1] || -> node4(s42)*. % 76.04/76.31 110203[66:MRR:792.0,110201.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 110206[66:Res:53.1,110203.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 110208[67:Spt:110206.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 110210[67:Res:110208.0,61.1] always3(s42) || -> . % 76.04/76.31 110211[67:SSi:110210.0,78254.0,78258.0,108792.0,110053.0,110201.0] || -> . % 76.04/76.31 110212[67:Spt:110211.0,110206.0,110208.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 110213[67:Spt:110211.0,110206.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 110217[67:Res:110213.0,61.1] always3(s43) || -> . % 76.04/76.31 110218[67:SSi:110217.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 110219[65:Spt:110218.0,110052.0,110053.0] || until2p7(s42)*+ -> . % 76.04/76.31 110220[65:Spt:110218.0,110052.1] || -> node4(s41)*. % 76.04/76.31 110222[65:MRR:795.0,110220.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 110225[65:Res:53.1,110222.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 110227[66:Spt:110225.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 110229[66:Res:110227.0,61.1] always3(s41) || -> . % 76.04/76.31 110230[66:SSi:110229.0,78250.0,78253.0,108791.0,110051.0,110220.0] || -> . % 76.04/76.31 110231[66:Spt:110230.0,110225.0,110227.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.31 110232[66:Spt:110230.0,110225.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 110236[66:Res:110232.0,61.1] always3(s42) || -> . % 76.04/76.31 110237[66:SSi:110236.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 110238[64:Spt:110237.0,110050.0,110051.0] || until2p7(s41)*+ -> . % 76.04/76.31 110239[64:Spt:110237.0,110050.1] || -> node4(s40)*. % 76.04/76.31 110241[64:MRR:798.0,110239.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.31 110244[64:Res:53.1,110241.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.31 110246[64:MRR:110244.0,110040.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 110248[64:Res:110246.0,61.1] always3(s41) || -> . % 76.04/76.31 110249[64:SSi:110248.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 110250[62:Spt:110249.0,109991.0,109994.0] || trans(s49,s40)*+ -> . % 76.04/76.31 110251[62:Spt:110249.0,109991.1,109991.2,109991.3,109991.4,109991.5,109991.6,109991.7,109991.8,109991.9,109991.10,109991.11,109991.12,109991.13,109991.14,109991.15,109991.16,109991.17,109991.18,109991.19,109991.20,109991.21,109991.22,109991.23,109991.24,109991.25,109991.26,109991.27,109991.28,109991.29,109991.30,109991.31,109991.32,109991.33,109991.34,109991.35,109991.36,109991.37] || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 110253[62:MRR:109993.1,110250.0] xuntil6(s49) || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 110254[63:Spt:110251.0] || -> trans(s49,s39)*. % 76.04/76.31 110255[63:Res:110254.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s39)*. % 76.04/76.31 110257[63:Res:110254.0,60.0] || -> node2(s49,s39)*. % 76.04/76.31 110258[63:SSi:110255.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s39)*. % 76.04/76.31 110259[63:Res:110257.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 110296[63:SoR:110259.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 110298[63:SoR:110296.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 76.04/76.31 110299[63:SSi:110298.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 76.04/76.31 110300[64:Spt:110299.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 110302[64:Res:110300.0,61.1] always3(s39) || -> . % 76.04/76.31 110303[64:SSi:110302.0,78241.0,78244.0,108789.0] || -> . % 76.04/76.31 110304[64:Spt:110303.0,110299.1,110300.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.04/76.31 110305[64:Spt:110303.0,110299.0,110299.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 110309[64:MRR:110296.2,110304.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 110310[64:Res:53.1,110305.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 110312[64:MRR:110310.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 110313[64:MRR:110258.0,110312.0] || -> until2p7(s39)*. % 76.04/76.31 110314[64:MRR:237.0,110313.0] || -> until2p7(s40)* node4(s39). % 76.04/76.31 110315[65:Spt:110314.0] || -> until2p7(s40)*. % 76.04/76.31 110316[65:MRR:238.0,110315.0] || -> until2p7(s41)* node4(s40). % 76.04/76.31 110317[66:Spt:110316.0] || -> until2p7(s41)*. % 76.04/76.31 110318[66:MRR:239.0,110317.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 110319[67:Spt:110318.0] || -> until2p7(s42)*. % 76.04/76.31 110320[67:MRR:240.0,110319.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 110321[68:Spt:110320.0] || -> until2p7(s43)*. % 76.04/76.31 110322[68:MRR:241.0,110321.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 110323[69:Spt:110322.0] || -> until2p7(s44)*. % 76.04/76.31 110324[69:MRR:539.0,110323.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 110325[70:Spt:110324.0] || -> until2p7(s45)*. % 76.04/76.31 110326[70:MRR:544.0,110325.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 110327[71:Spt:110326.0] || -> until2p7(s46)*. % 76.04/76.31 110328[71:MRR:549.0,110327.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 110329[72:Spt:110328.0] || -> until2p7(s47)*. % 76.04/76.31 110330[72:MRR:554.0,110329.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 110331[73:Spt:110330.0] || -> until2p7(s48)*. % 76.04/76.31 110332[73:MRR:559.0,110331.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 110333[74:Spt:110332.0] || -> until2p7(s49)*. % 76.04/76.31 110334[74:MRR:194.0,110333.0] || -> node4(s49)*. % 76.04/76.31 110335[74:MRR:110309.0,110334.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 110336[74:Res:53.1,110335.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 110338[74:MRR:110336.0,78381.0] || -> . % 76.04/76.31 110339[74:Spt:110338.0,110332.0,110333.0] || until2p7(s49)*+ -> . % 76.04/76.31 110340[74:Spt:110338.0,110332.1] || -> node4(s48)*. % 76.04/76.31 110341[74:MRR:78384.0,110340.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 110344[74:Res:53.1,110341.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 110347[74:Res:110344.0,61.1] always3(s48) || -> . % 76.04/76.31 110348[74:SSi:110347.0,78281.0,78387.0,108798.0,110331.0,110340.0] || -> . % 76.04/76.31 110349[73:Spt:110348.0,110330.0,110331.0] || until2p7(s48)*+ -> . % 76.04/76.31 110350[73:Spt:110348.0,110330.1] || -> node4(s47)*. % 76.04/76.31 110352[73:MRR:777.0,110350.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 110367[73:Res:53.1,110352.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 110369[74:Spt:110367.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 110371[74:Res:110369.0,61.1] always3(s47) || -> . % 76.04/76.31 110372[74:SSi:110371.0,78277.0,78280.0,108797.0,110329.0,110350.0] || -> . % 76.04/76.31 110373[74:Spt:110372.0,110367.0,110369.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 110374[74:Spt:110372.0,110367.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 110378[74:Res:110374.0,61.1] always3(s48) || -> . % 76.04/76.31 110379[74:SSi:110378.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 110380[72:Spt:110379.0,110328.0,110329.0] || until2p7(s47)*+ -> . % 76.04/76.31 110381[72:Spt:110379.0,110328.1] || -> node4(s46)*. % 76.04/76.31 110383[72:MRR:780.0,110381.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 110393[72:Res:53.1,110383.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 110395[73:Spt:110393.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 110397[73:Res:110395.0,61.1] always3(s46) || -> . % 76.04/76.31 110398[73:SSi:110397.0,78272.0,78276.0,108796.0,110327.0,110381.0] || -> . % 76.04/76.31 110399[73:Spt:110398.0,110393.0,110395.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 110400[73:Spt:110398.0,110393.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 110404[73:Res:110400.0,61.1] always3(s47) || -> . % 76.04/76.31 110405[73:SSi:110404.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 110406[71:Spt:110405.0,110326.0,110327.0] || until2p7(s46)*+ -> . % 76.04/76.31 110407[71:Spt:110405.0,110326.1] || -> node4(s45)*. % 76.04/76.31 110409[71:MRR:783.0,110407.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 110412[71:Res:53.1,110409.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 110414[72:Spt:110412.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 110416[72:Res:110414.0,61.1] always3(s45) || -> . % 76.04/76.31 110417[72:SSi:110416.0,78268.0,78271.0,108795.0,110325.0,110407.0] || -> . % 76.04/76.31 110418[72:Spt:110417.0,110412.0,110414.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 110419[72:Spt:110417.0,110412.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 110423[72:Res:110419.0,61.1] always3(s46) || -> . % 76.04/76.31 110424[72:SSi:110423.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 110425[70:Spt:110424.0,110324.0,110325.0] || until2p7(s45)*+ -> . % 76.04/76.31 110426[70:Spt:110424.0,110324.1] || -> node4(s44)*. % 76.04/76.31 110428[70:MRR:786.0,110426.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 110431[70:Res:53.1,110428.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 110433[71:Spt:110431.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 110435[71:Res:110433.0,61.1] always3(s44) || -> . % 76.04/76.31 110436[71:SSi:110435.0,78263.0,78267.0,108794.0,110323.0,110426.0] || -> . % 76.04/76.31 110437[71:Spt:110436.0,110431.0,110433.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 110438[71:Spt:110436.0,110431.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 110442[71:Res:110438.0,61.1] always3(s45) || -> . % 76.04/76.31 110443[71:SSi:110442.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 110444[69:Spt:110443.0,110322.0,110323.0] || until2p7(s44)*+ -> . % 76.04/76.31 110445[69:Spt:110443.0,110322.1] || -> node4(s43)*. % 76.04/76.31 110447[69:MRR:789.0,110445.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 110450[69:Res:53.1,110447.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 110455[70:Spt:110450.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 110457[70:Res:110455.0,61.1] always3(s43) || -> . % 76.04/76.31 110458[70:SSi:110457.0,78259.0,78262.0,108793.0,110321.0,110445.0] || -> . % 76.04/76.31 110459[70:Spt:110458.0,110450.0,110455.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 110460[70:Spt:110458.0,110450.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 110464[70:Res:110460.0,61.1] always3(s44) || -> . % 76.04/76.31 110465[70:SSi:110464.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 110466[68:Spt:110465.0,110320.0,110321.0] || until2p7(s43)*+ -> . % 76.04/76.31 110467[68:Spt:110465.0,110320.1] || -> node4(s42)*. % 76.04/76.31 110469[68:MRR:792.0,110467.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 110472[68:Res:53.1,110469.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 110474[69:Spt:110472.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 110476[69:Res:110474.0,61.1] always3(s42) || -> . % 76.04/76.31 110477[69:SSi:110476.0,78254.0,78258.0,108792.0,110319.0,110467.0] || -> . % 76.04/76.31 110478[69:Spt:110477.0,110472.0,110474.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 110479[69:Spt:110477.0,110472.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 110483[69:Res:110479.0,61.1] always3(s43) || -> . % 76.04/76.31 110484[69:SSi:110483.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 110485[67:Spt:110484.0,110318.0,110319.0] || until2p7(s42)*+ -> . % 76.04/76.31 110486[67:Spt:110484.0,110318.1] || -> node4(s41)*. % 76.04/76.31 110488[67:MRR:795.0,110486.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 110491[67:Res:53.1,110488.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 110493[68:Spt:110491.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 110495[68:Res:110493.0,61.1] always3(s41) || -> . % 76.04/76.31 110496[68:SSi:110495.0,78250.0,78253.0,108791.0,110317.0,110486.0] || -> . % 76.04/76.31 110497[68:Spt:110496.0,110491.0,110493.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.31 110498[68:Spt:110496.0,110491.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 110502[68:Res:110498.0,61.1] always3(s42) || -> . % 76.04/76.31 110503[68:SSi:110502.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 110504[66:Spt:110503.0,110316.0,110317.0] || until2p7(s41)*+ -> . % 76.04/76.31 110505[66:Spt:110503.0,110316.1] || -> node4(s40)*. % 76.04/76.31 110507[66:MRR:798.0,110505.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.31 110510[66:Res:53.1,110507.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.31 110512[67:Spt:110510.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 110514[67:Res:110512.0,61.1] always3(s40) || -> . % 76.04/76.31 110515[67:SSi:110514.0,78245.0,78249.0,108790.0,110315.0,110505.0] || -> . % 76.04/76.31 110516[67:Spt:110515.0,110510.0,110512.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.31 110517[67:Spt:110515.0,110510.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 110521[67:Res:110517.0,61.1] always3(s41) || -> . % 76.04/76.31 110522[67:SSi:110521.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 110523[65:Spt:110522.0,110314.0,110315.0] || until2p7(s40)*+ -> . % 76.04/76.31 110524[65:Spt:110522.0,110314.1] || -> node4(s39)*. % 76.04/76.31 110526[65:MRR:801.0,110524.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.31 110529[65:Res:53.1,110526.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.31 110531[65:MRR:110529.0,110304.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 110536[65:Res:110531.0,61.1] always3(s40) || -> . % 76.04/76.31 110537[65:SSi:110536.0,78245.0,78249.0,108790.0] || -> . % 76.04/76.31 110538[63:Spt:110537.0,110251.0,110254.0] || trans(s49,s39)*+ -> . % 76.04/76.31 110539[63:Spt:110537.0,110251.1,110251.2,110251.3,110251.4,110251.5,110251.6,110251.7,110251.8,110251.9,110251.10,110251.11,110251.12,110251.13,110251.14,110251.15,110251.16,110251.17,110251.18,110251.19,110251.20,110251.21,110251.22,110251.23,110251.24,110251.25,110251.26,110251.27,110251.28,110251.29,110251.30,110251.31,110251.32,110251.33,110251.34,110251.35,110251.36] || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 110541[63:MRR:110253.1,110538.0] xuntil6(s49) || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 110542[64:Spt:110539.0] || -> trans(s49,s38)*. % 76.04/76.31 110543[64:Res:110542.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s38)*. % 76.04/76.31 110545[64:Res:110542.0,60.0] || -> node2(s49,s38)*. % 76.04/76.31 110546[64:SSi:110543.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s38)*. % 76.04/76.31 110547[64:Res:110545.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 110585[64:SoR:110547.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 110587[64:SoR:110585.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)* xuntil6(s49). % 76.04/76.31 110588[64:SSi:110587.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s38,c_busy)* xuntil6(s49). % 76.04/76.31 110589[65:Spt:110588.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 110591[65:Res:110589.0,61.1] always3(s38) || -> . % 76.04/76.31 110592[65:SSi:110591.0,78236.0,78240.0,108788.0] || -> . % 76.04/76.31 110593[65:Spt:110592.0,110588.1,110589.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.04/76.31 110594[65:Spt:110592.0,110588.0,110588.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 110598[65:MRR:110585.2,110593.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 110599[65:Res:53.1,110594.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 110601[65:MRR:110599.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 110602[65:MRR:110546.0,110601.0] || -> until2p7(s38)*. % 76.04/76.31 110603[65:MRR:236.0,110602.0] || -> until2p7(s39)* node4(s38). % 76.04/76.31 110604[66:Spt:110603.0] || -> until2p7(s39)*. % 76.04/76.31 110605[66:MRR:237.0,110604.0] || -> until2p7(s40)* node4(s39). % 76.04/76.31 110606[67:Spt:110605.0] || -> until2p7(s40)*. % 76.04/76.31 110607[67:MRR:238.0,110606.0] || -> until2p7(s41)* node4(s40). % 76.04/76.31 110608[68:Spt:110607.0] || -> until2p7(s41)*. % 76.04/76.31 110609[68:MRR:239.0,110608.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 110610[69:Spt:110609.0] || -> until2p7(s42)*. % 76.04/76.31 110611[69:MRR:240.0,110610.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 110612[70:Spt:110611.0] || -> until2p7(s43)*. % 76.04/76.31 110613[70:MRR:241.0,110612.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 110614[71:Spt:110613.0] || -> until2p7(s44)*. % 76.04/76.31 110615[71:MRR:539.0,110614.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 110616[72:Spt:110615.0] || -> until2p7(s45)*. % 76.04/76.31 110617[72:MRR:544.0,110616.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 110618[73:Spt:110617.0] || -> until2p7(s46)*. % 76.04/76.31 110619[73:MRR:549.0,110618.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 110620[74:Spt:110619.0] || -> until2p7(s47)*. % 76.04/76.31 110621[74:MRR:554.0,110620.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 110622[75:Spt:110621.0] || -> until2p7(s48)*. % 76.04/76.31 110623[75:MRR:559.0,110622.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 110624[76:Spt:110623.0] || -> until2p7(s49)*. % 76.04/76.31 110625[76:MRR:194.0,110624.0] || -> node4(s49)*. % 76.04/76.31 110626[76:MRR:110598.0,110625.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 110630[76:Res:53.1,110626.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 110632[76:MRR:110630.0,78381.0] || -> . % 76.04/76.31 110633[76:Spt:110632.0,110623.0,110624.0] || until2p7(s49)*+ -> . % 76.04/76.31 110634[76:Spt:110632.0,110623.1] || -> node4(s48)*. % 76.04/76.31 110635[76:MRR:78384.0,110634.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 110638[76:Res:53.1,110635.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 110641[76:Res:110638.0,61.1] always3(s48) || -> . % 76.04/76.31 110642[76:SSi:110641.0,78281.0,78387.0,108798.0,110622.0,110634.0] || -> . % 76.04/76.31 110643[75:Spt:110642.0,110621.0,110622.0] || until2p7(s48)*+ -> . % 76.04/76.31 110644[75:Spt:110642.0,110621.1] || -> node4(s47)*. % 76.04/76.31 110646[75:MRR:777.0,110644.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 110658[75:Res:53.1,110646.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 110660[76:Spt:110658.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 110662[76:Res:110660.0,61.1] always3(s47) || -> . % 76.04/76.31 110663[76:SSi:110662.0,78277.0,78280.0,108797.0,110620.0,110644.0] || -> . % 76.04/76.31 110664[76:Spt:110663.0,110658.0,110660.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 110665[76:Spt:110663.0,110658.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 110669[76:Res:110665.0,61.1] always3(s48) || -> . % 76.04/76.31 110670[76:SSi:110669.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 110671[74:Spt:110670.0,110619.0,110620.0] || until2p7(s47)*+ -> . % 76.04/76.31 110672[74:Spt:110670.0,110619.1] || -> node4(s46)*. % 76.04/76.31 110674[74:MRR:780.0,110672.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 110681[74:Res:53.1,110674.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 110686[75:Spt:110681.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 110688[75:Res:110686.0,61.1] always3(s46) || -> . % 76.04/76.31 110689[75:SSi:110688.0,78272.0,78276.0,108796.0,110618.0,110672.0] || -> . % 76.04/76.31 110690[75:Spt:110689.0,110681.0,110686.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 110691[75:Spt:110689.0,110681.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 110695[75:Res:110691.0,61.1] always3(s47) || -> . % 76.04/76.31 110696[75:SSi:110695.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 110697[73:Spt:110696.0,110617.0,110618.0] || until2p7(s46)*+ -> . % 76.04/76.31 110698[73:Spt:110696.0,110617.1] || -> node4(s45)*. % 76.04/76.31 110700[73:MRR:783.0,110698.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 110703[73:Res:53.1,110700.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 110705[74:Spt:110703.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 110707[74:Res:110705.0,61.1] always3(s45) || -> . % 76.04/76.31 110708[74:SSi:110707.0,78268.0,78271.0,108795.0,110616.0,110698.0] || -> . % 76.04/76.31 110709[74:Spt:110708.0,110703.0,110705.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 110710[74:Spt:110708.0,110703.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 110714[74:Res:110710.0,61.1] always3(s46) || -> . % 76.04/76.31 110715[74:SSi:110714.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 110716[72:Spt:110715.0,110615.0,110616.0] || until2p7(s45)*+ -> . % 76.04/76.31 110717[72:Spt:110715.0,110615.1] || -> node4(s44)*. % 76.04/76.31 110719[72:MRR:786.0,110717.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 110722[72:Res:53.1,110719.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 110724[73:Spt:110722.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 110726[73:Res:110724.0,61.1] always3(s44) || -> . % 76.04/76.31 110727[73:SSi:110726.0,78263.0,78267.0,108794.0,110614.0,110717.0] || -> . % 76.04/76.31 110728[73:Spt:110727.0,110722.0,110724.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 110729[73:Spt:110727.0,110722.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 110733[73:Res:110729.0,61.1] always3(s45) || -> . % 76.04/76.31 110734[73:SSi:110733.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 110735[71:Spt:110734.0,110613.0,110614.0] || until2p7(s44)*+ -> . % 76.04/76.31 110736[71:Spt:110734.0,110613.1] || -> node4(s43)*. % 76.04/76.31 110738[71:MRR:789.0,110736.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 110741[71:Res:53.1,110738.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 110743[72:Spt:110741.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 110745[72:Res:110743.0,61.1] always3(s43) || -> . % 76.04/76.31 110746[72:SSi:110745.0,78259.0,78262.0,108793.0,110612.0,110736.0] || -> . % 76.04/76.31 110747[72:Spt:110746.0,110741.0,110743.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 110748[72:Spt:110746.0,110741.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 110752[72:Res:110748.0,61.1] always3(s44) || -> . % 76.04/76.31 110753[72:SSi:110752.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 110754[70:Spt:110753.0,110611.0,110612.0] || until2p7(s43)*+ -> . % 76.04/76.31 110755[70:Spt:110753.0,110611.1] || -> node4(s42)*. % 76.04/76.31 110757[70:MRR:792.0,110755.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 110760[70:Res:53.1,110757.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 110765[71:Spt:110760.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 110767[71:Res:110765.0,61.1] always3(s42) || -> . % 76.04/76.31 110768[71:SSi:110767.0,78254.0,78258.0,108792.0,110610.0,110755.0] || -> . % 76.04/76.31 110769[71:Spt:110768.0,110760.0,110765.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 110770[71:Spt:110768.0,110760.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 110774[71:Res:110770.0,61.1] always3(s43) || -> . % 76.04/76.31 110775[71:SSi:110774.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 110776[69:Spt:110775.0,110609.0,110610.0] || until2p7(s42)*+ -> . % 76.04/76.31 110777[69:Spt:110775.0,110609.1] || -> node4(s41)*. % 76.04/76.31 110779[69:MRR:795.0,110777.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 110782[69:Res:53.1,110779.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 110784[70:Spt:110782.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 110786[70:Res:110784.0,61.1] always3(s41) || -> . % 76.04/76.31 110787[70:SSi:110786.0,78250.0,78253.0,108791.0,110608.0,110777.0] || -> . % 76.04/76.31 110788[70:Spt:110787.0,110782.0,110784.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.31 110789[70:Spt:110787.0,110782.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 110793[70:Res:110789.0,61.1] always3(s42) || -> . % 76.04/76.31 110794[70:SSi:110793.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 110795[68:Spt:110794.0,110607.0,110608.0] || until2p7(s41)*+ -> . % 76.04/76.31 110796[68:Spt:110794.0,110607.1] || -> node4(s40)*. % 76.04/76.31 110798[68:MRR:798.0,110796.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.31 110801[68:Res:53.1,110798.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.31 110803[69:Spt:110801.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 110805[69:Res:110803.0,61.1] always3(s40) || -> . % 76.04/76.31 110806[69:SSi:110805.0,78245.0,78249.0,108790.0,110606.0,110796.0] || -> . % 76.04/76.31 110807[69:Spt:110806.0,110801.0,110803.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.31 110808[69:Spt:110806.0,110801.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 110812[69:Res:110808.0,61.1] always3(s41) || -> . % 76.04/76.31 110813[69:SSi:110812.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 110814[67:Spt:110813.0,110605.0,110606.0] || until2p7(s40)*+ -> . % 76.04/76.31 110815[67:Spt:110813.0,110605.1] || -> node4(s39)*. % 76.04/76.31 110817[67:MRR:801.0,110815.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.31 110820[67:Res:53.1,110817.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.31 110822[68:Spt:110820.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 110824[68:Res:110822.0,61.1] always3(s39) || -> . % 76.04/76.31 110825[68:SSi:110824.0,78241.0,78244.0,108789.0,110604.0,110815.0] || -> . % 76.04/76.31 110826[68:Spt:110825.0,110820.0,110822.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.31 110827[68:Spt:110825.0,110820.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 110831[68:Res:110827.0,61.1] always3(s40) || -> . % 76.04/76.31 110832[68:SSi:110831.0,78245.0,78249.0,108790.0] || -> . % 76.04/76.31 110833[66:Spt:110832.0,110603.0,110604.0] || until2p7(s39)*+ -> . % 76.04/76.31 110834[66:Spt:110832.0,110603.1] || -> node4(s38)*. % 76.04/76.31 110836[66:MRR:804.0,110834.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.31 110839[66:Res:53.1,110836.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.31 110841[66:MRR:110839.0,110593.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 110846[66:Res:110841.0,61.1] always3(s39) || -> . % 76.04/76.31 110847[66:SSi:110846.0,78241.0,78244.0,108789.0] || -> . % 76.04/76.31 110848[64:Spt:110847.0,110539.0,110542.0] || trans(s49,s38)*+ -> . % 76.04/76.31 110849[64:Spt:110847.0,110539.1,110539.2,110539.3,110539.4,110539.5,110539.6,110539.7,110539.8,110539.9,110539.10,110539.11,110539.12,110539.13,110539.14,110539.15,110539.16,110539.17,110539.18,110539.19,110539.20,110539.21,110539.22,110539.23,110539.24,110539.25,110539.26,110539.27,110539.28,110539.29,110539.30,110539.31,110539.32,110539.33,110539.34,110539.35] || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 110851[64:MRR:110541.1,110848.0] xuntil6(s49) || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 110852[65:Spt:110849.0] || -> trans(s49,s37)*. % 76.04/76.31 110853[65:Res:110852.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s37)*. % 76.04/76.31 110855[65:Res:110852.0,60.0] || -> node2(s49,s37)*. % 76.04/76.31 110856[65:SSi:110853.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s37)*. % 76.04/76.31 110857[65:Res:110855.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 110899[65:SoR:110857.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 110901[65:SoR:110899.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)* xuntil6(s49). % 76.04/76.31 110902[65:SSi:110901.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s37,c_busy)* xuntil6(s49). % 76.04/76.31 110903[66:Spt:110902.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 110905[66:Res:110903.0,61.1] always3(s37) || -> . % 76.04/76.31 110906[66:SSi:110905.0,78232.0,78235.0,108787.0] || -> . % 76.04/76.31 110907[66:Spt:110906.0,110902.1,110903.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.04/76.31 110908[66:Spt:110906.0,110902.0,110902.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 110912[66:MRR:110899.2,110907.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 110913[66:Res:53.1,110908.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 110915[66:MRR:110913.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 110916[66:MRR:110856.0,110915.0] || -> until2p7(s37)*. % 76.04/76.31 110917[66:MRR:235.0,110916.0] || -> until2p7(s38)* node4(s37). % 76.04/76.31 110918[67:Spt:110917.0] || -> until2p7(s38)*. % 76.04/76.31 110919[67:MRR:236.0,110918.0] || -> until2p7(s39)* node4(s38). % 76.04/76.31 110920[68:Spt:110919.0] || -> until2p7(s39)*. % 76.04/76.31 110921[68:MRR:237.0,110920.0] || -> until2p7(s40)* node4(s39). % 76.04/76.31 110922[69:Spt:110921.0] || -> until2p7(s40)*. % 76.04/76.31 110923[69:MRR:238.0,110922.0] || -> until2p7(s41)* node4(s40). % 76.04/76.31 110924[70:Spt:110923.0] || -> until2p7(s41)*. % 76.04/76.31 110925[70:MRR:239.0,110924.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 110926[71:Spt:110925.0] || -> until2p7(s42)*. % 76.04/76.31 110927[71:MRR:240.0,110926.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 110928[72:Spt:110927.0] || -> until2p7(s43)*. % 76.04/76.31 110929[72:MRR:241.0,110928.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 110930[73:Spt:110929.0] || -> until2p7(s44)*. % 76.04/76.31 110931[73:MRR:539.0,110930.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 110932[74:Spt:110931.0] || -> until2p7(s45)*. % 76.04/76.31 110933[74:MRR:544.0,110932.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 110934[75:Spt:110933.0] || -> until2p7(s46)*. % 76.04/76.31 110935[75:MRR:549.0,110934.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 110936[76:Spt:110935.0] || -> until2p7(s47)*. % 76.04/76.31 110937[76:MRR:554.0,110936.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 110938[77:Spt:110937.0] || -> until2p7(s48)*. % 76.04/76.31 110939[77:MRR:559.0,110938.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 110940[78:Spt:110939.0] || -> until2p7(s49)*. % 76.04/76.31 110941[78:MRR:194.0,110940.0] || -> node4(s49)*. % 76.04/76.31 110942[78:MRR:110912.0,110941.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 110943[78:Res:53.1,110942.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 110945[78:MRR:110943.0,78381.0] || -> . % 76.04/76.31 110946[78:Spt:110945.0,110939.0,110940.0] || until2p7(s49)*+ -> . % 76.04/76.31 110947[78:Spt:110945.0,110939.1] || -> node4(s48)*. % 76.04/76.31 110948[78:MRR:78384.0,110947.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 110951[78:Res:53.1,110948.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 110954[78:Res:110951.0,61.1] always3(s48) || -> . % 76.04/76.31 110955[78:SSi:110954.0,78281.0,78387.0,108798.0,110938.0,110947.0] || -> . % 76.04/76.31 110956[77:Spt:110955.0,110937.0,110938.0] || until2p7(s48)*+ -> . % 76.04/76.31 110957[77:Spt:110955.0,110937.1] || -> node4(s47)*. % 76.04/76.31 110959[77:MRR:777.0,110957.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 110974[77:Res:53.1,110959.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 110979[78:Spt:110974.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 110981[78:Res:110979.0,61.1] always3(s47) || -> . % 76.04/76.31 110982[78:SSi:110981.0,78277.0,78280.0,108797.0,110936.0,110957.0] || -> . % 76.04/76.31 110983[78:Spt:110982.0,110974.0,110979.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 110984[78:Spt:110982.0,110974.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 110988[78:Res:110984.0,61.1] always3(s48) || -> . % 76.04/76.31 110989[78:SSi:110988.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 110990[76:Spt:110989.0,110935.0,110936.0] || until2p7(s47)*+ -> . % 76.04/76.31 110991[76:Spt:110989.0,110935.1] || -> node4(s46)*. % 76.04/76.31 110993[76:MRR:780.0,110991.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 111000[76:Res:53.1,110993.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 111002[77:Spt:111000.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 111004[77:Res:111002.0,61.1] always3(s46) || -> . % 76.04/76.31 111005[77:SSi:111004.0,78272.0,78276.0,108796.0,110934.0,110991.0] || -> . % 76.04/76.31 111006[77:Spt:111005.0,111000.0,111002.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 111007[77:Spt:111005.0,111000.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 111011[77:Res:111007.0,61.1] always3(s47) || -> . % 76.04/76.31 111012[77:SSi:111011.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 111013[75:Spt:111012.0,110933.0,110934.0] || until2p7(s46)*+ -> . % 76.04/76.31 111014[75:Spt:111012.0,110933.1] || -> node4(s45)*. % 76.04/76.31 111016[75:MRR:783.0,111014.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 111019[75:Res:53.1,111016.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 111024[76:Spt:111019.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 111026[76:Res:111024.0,61.1] always3(s45) || -> . % 76.04/76.31 111027[76:SSi:111026.0,78268.0,78271.0,108795.0,110932.0,111014.0] || -> . % 76.04/76.31 111028[76:Spt:111027.0,111019.0,111024.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 111029[76:Spt:111027.0,111019.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 111033[76:Res:111029.0,61.1] always3(s46) || -> . % 76.04/76.31 111034[76:SSi:111033.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 111035[74:Spt:111034.0,110931.0,110932.0] || until2p7(s45)*+ -> . % 76.04/76.31 111036[74:Spt:111034.0,110931.1] || -> node4(s44)*. % 76.04/76.31 111038[74:MRR:786.0,111036.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 111041[74:Res:53.1,111038.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 111043[75:Spt:111041.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 111045[75:Res:111043.0,61.1] always3(s44) || -> . % 76.04/76.31 111046[75:SSi:111045.0,78263.0,78267.0,108794.0,110930.0,111036.0] || -> . % 76.04/76.31 111047[75:Spt:111046.0,111041.0,111043.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 111048[75:Spt:111046.0,111041.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 111052[75:Res:111048.0,61.1] always3(s45) || -> . % 76.04/76.31 111053[75:SSi:111052.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 111054[73:Spt:111053.0,110929.0,110930.0] || until2p7(s44)*+ -> . % 76.04/76.31 111055[73:Spt:111053.0,110929.1] || -> node4(s43)*. % 76.04/76.31 111057[73:MRR:789.0,111055.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 111060[73:Res:53.1,111057.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 111062[74:Spt:111060.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 111064[74:Res:111062.0,61.1] always3(s43) || -> . % 76.04/76.31 111065[74:SSi:111064.0,78259.0,78262.0,108793.0,110928.0,111055.0] || -> . % 76.04/76.31 111066[74:Spt:111065.0,111060.0,111062.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 111067[74:Spt:111065.0,111060.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 111071[74:Res:111067.0,61.1] always3(s44) || -> . % 76.04/76.31 111072[74:SSi:111071.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 111073[72:Spt:111072.0,110927.0,110928.0] || until2p7(s43)*+ -> . % 76.04/76.31 111074[72:Spt:111072.0,110927.1] || -> node4(s42)*. % 76.04/76.31 111076[72:MRR:792.0,111074.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 111079[72:Res:53.1,111076.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 111081[73:Spt:111079.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 111083[73:Res:111081.0,61.1] always3(s42) || -> . % 76.04/76.31 111084[73:SSi:111083.0,78254.0,78258.0,108792.0,110926.0,111074.0] || -> . % 76.04/76.31 111085[73:Spt:111084.0,111079.0,111081.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 111086[73:Spt:111084.0,111079.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 111090[73:Res:111086.0,61.1] always3(s43) || -> . % 76.04/76.31 111091[73:SSi:111090.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 111092[71:Spt:111091.0,110925.0,110926.0] || until2p7(s42)*+ -> . % 76.04/76.31 111093[71:Spt:111091.0,110925.1] || -> node4(s41)*. % 76.04/76.31 111095[71:MRR:795.0,111093.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 111098[71:Res:53.1,111095.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 111103[72:Spt:111098.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 111105[72:Res:111103.0,61.1] always3(s41) || -> . % 76.04/76.31 111106[72:SSi:111105.0,78250.0,78253.0,108791.0,110924.0,111093.0] || -> . % 76.04/76.31 111107[72:Spt:111106.0,111098.0,111103.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.31 111108[72:Spt:111106.0,111098.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 111112[72:Res:111108.0,61.1] always3(s42) || -> . % 76.04/76.31 111113[72:SSi:111112.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 111114[70:Spt:111113.0,110923.0,110924.0] || until2p7(s41)*+ -> . % 76.04/76.31 111115[70:Spt:111113.0,110923.1] || -> node4(s40)*. % 76.04/76.31 111117[70:MRR:798.0,111115.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.31 111120[70:Res:53.1,111117.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.31 111122[71:Spt:111120.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 111124[71:Res:111122.0,61.1] always3(s40) || -> . % 76.04/76.31 111125[71:SSi:111124.0,78245.0,78249.0,108790.0,110922.0,111115.0] || -> . % 76.04/76.31 111126[71:Spt:111125.0,111120.0,111122.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.31 111127[71:Spt:111125.0,111120.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 111131[71:Res:111127.0,61.1] always3(s41) || -> . % 76.04/76.31 111132[71:SSi:111131.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 111133[69:Spt:111132.0,110921.0,110922.0] || until2p7(s40)*+ -> . % 76.04/76.31 111134[69:Spt:111132.0,110921.1] || -> node4(s39)*. % 76.04/76.31 111136[69:MRR:801.0,111134.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.31 111139[69:Res:53.1,111136.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.31 111141[70:Spt:111139.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 111143[70:Res:111141.0,61.1] always3(s39) || -> . % 76.04/76.31 111144[70:SSi:111143.0,78241.0,78244.0,108789.0,110920.0,111134.0] || -> . % 76.04/76.31 111145[70:Spt:111144.0,111139.0,111141.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.31 111146[70:Spt:111144.0,111139.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 111150[70:Res:111146.0,61.1] always3(s40) || -> . % 76.04/76.31 111151[70:SSi:111150.0,78245.0,78249.0,108790.0] || -> . % 76.04/76.31 111152[68:Spt:111151.0,110919.0,110920.0] || until2p7(s39)*+ -> . % 76.04/76.31 111153[68:Spt:111151.0,110919.1] || -> node4(s38)*. % 76.04/76.31 111155[68:MRR:804.0,111153.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.31 111158[68:Res:53.1,111155.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.31 111160[69:Spt:111158.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 111162[69:Res:111160.0,61.1] always3(s38) || -> . % 76.04/76.31 111163[69:SSi:111162.0,78236.0,78240.0,108788.0,110918.0,111153.0] || -> . % 76.04/76.31 111164[69:Spt:111163.0,111158.0,111160.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.31 111165[69:Spt:111163.0,111158.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 111169[69:Res:111165.0,61.1] always3(s39) || -> . % 76.04/76.31 111170[69:SSi:111169.0,78241.0,78244.0,108789.0] || -> . % 76.04/76.31 111171[67:Spt:111170.0,110917.0,110918.0] || until2p7(s38)*+ -> . % 76.04/76.31 111172[67:Spt:111170.0,110917.1] || -> node4(s37)*. % 76.04/76.31 111174[67:MRR:807.0,111172.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.31 111177[67:Res:53.1,111174.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.31 111179[67:MRR:111177.0,110907.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 111184[67:Res:111179.0,61.1] always3(s38) || -> . % 76.04/76.31 111185[67:SSi:111184.0,78236.0,78240.0,108788.0] || -> . % 76.04/76.31 111186[65:Spt:111185.0,110849.0,110852.0] || trans(s49,s37)*+ -> . % 76.04/76.31 111187[65:Spt:111185.0,110849.1,110849.2,110849.3,110849.4,110849.5,110849.6,110849.7,110849.8,110849.9,110849.10,110849.11,110849.12,110849.13,110849.14,110849.15,110849.16,110849.17,110849.18,110849.19,110849.20,110849.21,110849.22,110849.23,110849.24,110849.25,110849.26,110849.27,110849.28,110849.29,110849.30,110849.31,110849.32,110849.33,110849.34] || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 111189[65:MRR:110851.1,111186.0] xuntil6(s49) || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 111190[66:Spt:111187.0] || -> trans(s49,s36)*. % 76.04/76.31 111191[66:Res:111190.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s36)*. % 76.04/76.31 111193[66:Res:111190.0,60.0] || -> node2(s49,s36)*. % 76.04/76.31 111194[66:SSi:111191.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s36)*. % 76.04/76.31 111195[66:Res:111193.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 111238[66:SoR:111195.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 111240[66:SoR:111238.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)* xuntil6(s49). % 76.04/76.31 111241[66:SSi:111240.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s36,c_busy)* xuntil6(s49). % 76.04/76.31 111242[67:Spt:111241.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 111244[67:Res:111242.0,61.1] always3(s36) || -> . % 76.04/76.31 111245[67:SSi:111244.0,78227.0,78231.0,108786.0] || -> . % 76.04/76.31 111246[67:Spt:111245.0,111241.1,111242.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.04/76.31 111247[67:Spt:111245.0,111241.0,111241.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 111251[67:MRR:111238.2,111246.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 111252[67:Res:53.1,111247.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 111254[67:MRR:111252.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 111255[67:MRR:111194.0,111254.0] || -> until2p7(s36)*. % 76.04/76.31 111256[67:MRR:232.0,111255.0] || -> until2p7(s37)* node4(s36). % 76.04/76.31 111257[68:Spt:111256.0] || -> until2p7(s37)*. % 76.04/76.31 111258[68:MRR:235.0,111257.0] || -> until2p7(s38)* node4(s37). % 76.04/76.31 111259[69:Spt:111258.0] || -> until2p7(s38)*. % 76.04/76.31 111260[69:MRR:236.0,111259.0] || -> until2p7(s39)* node4(s38). % 76.04/76.31 111261[70:Spt:111260.0] || -> until2p7(s39)*. % 76.04/76.31 111262[70:MRR:237.0,111261.0] || -> until2p7(s40)* node4(s39). % 76.04/76.31 111263[71:Spt:111262.0] || -> until2p7(s40)*. % 76.04/76.31 111264[71:MRR:238.0,111263.0] || -> until2p7(s41)* node4(s40). % 76.04/76.31 111265[72:Spt:111264.0] || -> until2p7(s41)*. % 76.04/76.31 111266[72:MRR:239.0,111265.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 111267[73:Spt:111266.0] || -> until2p7(s42)*. % 76.04/76.31 111268[73:MRR:240.0,111267.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 111269[74:Spt:111268.0] || -> until2p7(s43)*. % 76.04/76.31 111270[74:MRR:241.0,111269.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 111271[75:Spt:111270.0] || -> until2p7(s44)*. % 76.04/76.31 111272[75:MRR:539.0,111271.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 111273[76:Spt:111272.0] || -> until2p7(s45)*. % 76.04/76.31 111274[76:MRR:544.0,111273.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 111275[77:Spt:111274.0] || -> until2p7(s46)*. % 76.04/76.31 111276[77:MRR:549.0,111275.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 111277[78:Spt:111276.0] || -> until2p7(s47)*. % 76.04/76.31 111278[78:MRR:554.0,111277.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 111279[79:Spt:111278.0] || -> until2p7(s48)*. % 76.04/76.31 111280[79:MRR:559.0,111279.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 111281[80:Spt:111280.0] || -> until2p7(s49)*. % 76.04/76.31 111282[80:MRR:194.0,111281.0] || -> node4(s49)*. % 76.04/76.31 111283[80:MRR:111251.0,111282.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 111287[80:Res:53.1,111283.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 111289[80:MRR:111287.0,78381.0] || -> . % 76.04/76.31 111290[80:Spt:111289.0,111280.0,111281.0] || until2p7(s49)*+ -> . % 76.04/76.31 111291[80:Spt:111289.0,111280.1] || -> node4(s48)*. % 76.04/76.31 111292[80:MRR:78384.0,111291.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 111295[80:Res:53.1,111292.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 111298[80:Res:111295.0,61.1] always3(s48) || -> . % 76.04/76.31 111299[80:SSi:111298.0,78281.0,78387.0,108798.0,111279.0,111291.0] || -> . % 76.04/76.31 111300[79:Spt:111299.0,111278.0,111279.0] || until2p7(s48)*+ -> . % 76.04/76.31 111301[79:Spt:111299.0,111278.1] || -> node4(s47)*. % 76.04/76.31 111303[79:MRR:777.0,111301.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 111315[79:Res:53.1,111303.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 111317[80:Spt:111315.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 111319[80:Res:111317.0,61.1] always3(s47) || -> . % 76.04/76.31 111320[80:SSi:111319.0,78277.0,78280.0,108797.0,111277.0,111301.0] || -> . % 76.04/76.31 111321[80:Spt:111320.0,111315.0,111317.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 111322[80:Spt:111320.0,111315.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 111326[80:Res:111322.0,61.1] always3(s48) || -> . % 76.04/76.31 111327[80:SSi:111326.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 111328[78:Spt:111327.0,111276.0,111277.0] || until2p7(s47)*+ -> . % 76.04/76.31 111329[78:Spt:111327.0,111276.1] || -> node4(s46)*. % 76.04/76.31 111331[78:MRR:780.0,111329.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 111338[78:Res:53.1,111331.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 111343[79:Spt:111338.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 111345[79:Res:111343.0,61.1] always3(s46) || -> . % 76.04/76.31 111346[79:SSi:111345.0,78272.0,78276.0,108796.0,111275.0,111329.0] || -> . % 76.04/76.31 111347[79:Spt:111346.0,111338.0,111343.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 111348[79:Spt:111346.0,111338.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 111352[79:Res:111348.0,61.1] always3(s47) || -> . % 76.04/76.31 111353[79:SSi:111352.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 111354[77:Spt:111353.0,111274.0,111275.0] || until2p7(s46)*+ -> . % 76.04/76.31 111355[77:Spt:111353.0,111274.1] || -> node4(s45)*. % 76.04/76.31 111357[77:MRR:783.0,111355.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 111360[77:Res:53.1,111357.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 111362[78:Spt:111360.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 111364[78:Res:111362.0,61.1] always3(s45) || -> . % 76.04/76.31 111365[78:SSi:111364.0,78268.0,78271.0,108795.0,111273.0,111355.0] || -> . % 76.04/76.31 111366[78:Spt:111365.0,111360.0,111362.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 111367[78:Spt:111365.0,111360.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 111371[78:Res:111367.0,61.1] always3(s46) || -> . % 76.04/76.31 111372[78:SSi:111371.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 111373[76:Spt:111372.0,111272.0,111273.0] || until2p7(s45)*+ -> . % 76.04/76.31 111374[76:Spt:111372.0,111272.1] || -> node4(s44)*. % 76.04/76.31 111376[76:MRR:786.0,111374.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 111379[76:Res:53.1,111376.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 111381[77:Spt:111379.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 111383[77:Res:111381.0,61.1] always3(s44) || -> . % 76.04/76.31 111384[77:SSi:111383.0,78263.0,78267.0,108794.0,111271.0,111374.0] || -> . % 76.04/76.31 111385[77:Spt:111384.0,111379.0,111381.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 111386[77:Spt:111384.0,111379.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 111390[77:Res:111386.0,61.1] always3(s45) || -> . % 76.04/76.31 111391[77:SSi:111390.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 111392[75:Spt:111391.0,111270.0,111271.0] || until2p7(s44)*+ -> . % 76.04/76.31 111393[75:Spt:111391.0,111270.1] || -> node4(s43)*. % 76.04/76.31 111395[75:MRR:789.0,111393.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 111398[75:Res:53.1,111395.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 111400[76:Spt:111398.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 111402[76:Res:111400.0,61.1] always3(s43) || -> . % 76.04/76.31 111403[76:SSi:111402.0,78259.0,78262.0,108793.0,111269.0,111393.0] || -> . % 76.04/76.31 111404[76:Spt:111403.0,111398.0,111400.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 111405[76:Spt:111403.0,111398.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 111409[76:Res:111405.0,61.1] always3(s44) || -> . % 76.04/76.31 111410[76:SSi:111409.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 111411[74:Spt:111410.0,111268.0,111269.0] || until2p7(s43)*+ -> . % 76.04/76.31 111412[74:Spt:111410.0,111268.1] || -> node4(s42)*. % 76.04/76.31 111414[74:MRR:792.0,111412.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 111417[74:Res:53.1,111414.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 111422[75:Spt:111417.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 111424[75:Res:111422.0,61.1] always3(s42) || -> . % 76.04/76.31 111425[75:SSi:111424.0,78254.0,78258.0,108792.0,111267.0,111412.0] || -> . % 76.04/76.31 111426[75:Spt:111425.0,111417.0,111422.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 111427[75:Spt:111425.0,111417.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 111431[75:Res:111427.0,61.1] always3(s43) || -> . % 76.04/76.31 111432[75:SSi:111431.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 111433[73:Spt:111432.0,111266.0,111267.0] || until2p7(s42)*+ -> . % 76.04/76.31 111434[73:Spt:111432.0,111266.1] || -> node4(s41)*. % 76.04/76.31 111436[73:MRR:795.0,111434.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 111439[73:Res:53.1,111436.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 111441[74:Spt:111439.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 111443[74:Res:111441.0,61.1] always3(s41) || -> . % 76.04/76.31 111444[74:SSi:111443.0,78250.0,78253.0,108791.0,111265.0,111434.0] || -> . % 76.04/76.31 111445[74:Spt:111444.0,111439.0,111441.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.31 111446[74:Spt:111444.0,111439.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 111450[74:Res:111446.0,61.1] always3(s42) || -> . % 76.04/76.31 111451[74:SSi:111450.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 111452[72:Spt:111451.0,111264.0,111265.0] || until2p7(s41)*+ -> . % 76.04/76.31 111453[72:Spt:111451.0,111264.1] || -> node4(s40)*. % 76.04/76.31 111455[72:MRR:798.0,111453.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.31 111458[72:Res:53.1,111455.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.31 111460[73:Spt:111458.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 111462[73:Res:111460.0,61.1] always3(s40) || -> . % 76.04/76.31 111463[73:SSi:111462.0,78245.0,78249.0,108790.0,111263.0,111453.0] || -> . % 76.04/76.31 111464[73:Spt:111463.0,111458.0,111460.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.31 111465[73:Spt:111463.0,111458.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 111469[73:Res:111465.0,61.1] always3(s41) || -> . % 76.04/76.31 111470[73:SSi:111469.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 111471[71:Spt:111470.0,111262.0,111263.0] || until2p7(s40)*+ -> . % 76.04/76.31 111472[71:Spt:111470.0,111262.1] || -> node4(s39)*. % 76.04/76.31 111474[71:MRR:801.0,111472.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.31 111477[71:Res:53.1,111474.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.31 111479[72:Spt:111477.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 111481[72:Res:111479.0,61.1] always3(s39) || -> . % 76.04/76.31 111482[72:SSi:111481.0,78241.0,78244.0,108789.0,111261.0,111472.0] || -> . % 76.04/76.31 111483[72:Spt:111482.0,111477.0,111479.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.31 111484[72:Spt:111482.0,111477.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 111488[72:Res:111484.0,61.1] always3(s40) || -> . % 76.04/76.31 111489[72:SSi:111488.0,78245.0,78249.0,108790.0] || -> . % 76.04/76.31 111490[70:Spt:111489.0,111260.0,111261.0] || until2p7(s39)*+ -> . % 76.04/76.31 111491[70:Spt:111489.0,111260.1] || -> node4(s38)*. % 76.04/76.31 111493[70:MRR:804.0,111491.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.31 111496[70:Res:53.1,111493.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.31 111501[71:Spt:111496.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 111503[71:Res:111501.0,61.1] always3(s38) || -> . % 76.04/76.31 111504[71:SSi:111503.0,78236.0,78240.0,108788.0,111259.0,111491.0] || -> . % 76.04/76.31 111505[71:Spt:111504.0,111496.0,111501.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.31 111506[71:Spt:111504.0,111496.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 111510[71:Res:111506.0,61.1] always3(s39) || -> . % 76.04/76.31 111511[71:SSi:111510.0,78241.0,78244.0,108789.0] || -> . % 76.04/76.31 111512[69:Spt:111511.0,111258.0,111259.0] || until2p7(s38)*+ -> . % 76.04/76.31 111513[69:Spt:111511.0,111258.1] || -> node4(s37)*. % 76.04/76.31 111515[69:MRR:807.0,111513.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.31 111518[69:Res:53.1,111515.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.31 111520[70:Spt:111518.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 111522[70:Res:111520.0,61.1] always3(s37) || -> . % 76.04/76.31 111523[70:SSi:111522.0,78232.0,78235.0,108787.0,111257.0,111513.0] || -> . % 76.04/76.31 111524[70:Spt:111523.0,111518.0,111520.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.31 111525[70:Spt:111523.0,111518.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 111529[70:Res:111525.0,61.1] always3(s38) || -> . % 76.04/76.31 111530[70:SSi:111529.0,78236.0,78240.0,108788.0] || -> . % 76.04/76.31 111531[68:Spt:111530.0,111256.0,111257.0] || until2p7(s37)*+ -> . % 76.04/76.31 111532[68:Spt:111530.0,111256.1] || -> node4(s36)*. % 76.04/76.31 111534[68:MRR:810.0,111532.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.31 111537[68:Res:53.1,111534.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.31 111539[68:MRR:111537.0,111246.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 111541[68:Res:111539.0,61.1] always3(s37) || -> . % 76.04/76.31 111542[68:SSi:111541.0,78232.0,78235.0,108787.0] || -> . % 76.04/76.31 111543[66:Spt:111542.0,111187.0,111190.0] || trans(s49,s36)*+ -> . % 76.04/76.31 111544[66:Spt:111542.0,111187.1,111187.2,111187.3,111187.4,111187.5,111187.6,111187.7,111187.8,111187.9,111187.10,111187.11,111187.12,111187.13,111187.14,111187.15,111187.16,111187.17,111187.18,111187.19,111187.20,111187.21,111187.22,111187.23,111187.24,111187.25,111187.26,111187.27,111187.28,111187.29,111187.30,111187.31,111187.32,111187.33] || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 111546[66:MRR:111189.1,111543.0] xuntil6(s49) || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 111547[67:Spt:111544.0] || -> trans(s49,s35)*. % 76.04/76.31 111548[67:Res:111547.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s35)*. % 76.04/76.31 111550[67:Res:111547.0,60.0] || -> node2(s49,s35)*. % 76.04/76.31 111551[67:SSi:111548.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s35)*. % 76.04/76.31 111552[67:Res:111550.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 111602[67:SoR:111552.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 111604[67:SoR:111602.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 76.04/76.31 111605[67:SSi:111604.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 76.04/76.31 111606[68:Spt:111605.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 111608[68:Res:111606.0,61.1] always3(s35) || -> . % 76.04/76.31 111609[68:SSi:111608.0,78223.0,78226.0,108785.0] || -> . % 76.04/76.31 111610[68:Spt:111609.0,111605.1,111606.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.04/76.31 111611[68:Spt:111609.0,111605.0,111605.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 111615[68:MRR:111602.2,111610.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 111616[68:Res:53.1,111611.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 111618[68:MRR:111616.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 111619[68:MRR:111551.0,111618.0] || -> until2p7(s35)*. % 76.04/76.31 111620[68:MRR:231.0,111619.0] || -> until2p7(s36)* node4(s35). % 76.04/76.31 111621[69:Spt:111620.0] || -> until2p7(s36)*. % 76.04/76.31 111622[69:MRR:232.0,111621.0] || -> until2p7(s37)* node4(s36). % 76.04/76.31 111623[70:Spt:111622.0] || -> until2p7(s37)*. % 76.04/76.31 111624[70:MRR:235.0,111623.0] || -> until2p7(s38)* node4(s37). % 76.04/76.31 111625[71:Spt:111624.0] || -> until2p7(s38)*. % 76.04/76.31 111626[71:MRR:236.0,111625.0] || -> until2p7(s39)* node4(s38). % 76.04/76.31 111627[72:Spt:111626.0] || -> until2p7(s39)*. % 76.04/76.31 111628[72:MRR:237.0,111627.0] || -> until2p7(s40)* node4(s39). % 76.04/76.31 111629[73:Spt:111628.0] || -> until2p7(s40)*. % 76.04/76.31 111630[73:MRR:238.0,111629.0] || -> until2p7(s41)* node4(s40). % 76.04/76.31 111631[74:Spt:111630.0] || -> until2p7(s41)*. % 76.04/76.31 111632[74:MRR:239.0,111631.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 111633[75:Spt:111632.0] || -> until2p7(s42)*. % 76.04/76.31 111634[75:MRR:240.0,111633.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 111635[76:Spt:111634.0] || -> until2p7(s43)*. % 76.04/76.31 111636[76:MRR:241.0,111635.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 111637[77:Spt:111636.0] || -> until2p7(s44)*. % 76.04/76.31 111638[77:MRR:539.0,111637.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 111639[78:Spt:111638.0] || -> until2p7(s45)*. % 76.04/76.31 111640[78:MRR:544.0,111639.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 111641[79:Spt:111640.0] || -> until2p7(s46)*. % 76.04/76.31 111642[79:MRR:549.0,111641.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 111643[80:Spt:111642.0] || -> until2p7(s47)*. % 76.04/76.31 111644[80:MRR:554.0,111643.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 111645[81:Spt:111644.0] || -> until2p7(s48)*. % 76.04/76.31 111646[81:MRR:559.0,111645.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 111647[82:Spt:111646.0] || -> until2p7(s49)*. % 76.04/76.31 111648[82:MRR:194.0,111647.0] || -> node4(s49)*. % 76.04/76.31 111649[82:MRR:111615.0,111648.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 111650[82:Res:53.1,111649.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 111652[82:MRR:111650.0,78381.0] || -> . % 76.04/76.31 111653[82:Spt:111652.0,111646.0,111647.0] || until2p7(s49)*+ -> . % 76.04/76.31 111654[82:Spt:111652.0,111646.1] || -> node4(s48)*. % 76.04/76.31 111655[82:MRR:78384.0,111654.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 111658[82:Res:53.1,111655.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 111661[82:Res:111658.0,61.1] always3(s48) || -> . % 76.04/76.31 111662[82:SSi:111661.0,78281.0,78387.0,108798.0,111645.0,111654.0] || -> . % 76.04/76.31 111663[81:Spt:111662.0,111644.0,111645.0] || until2p7(s48)*+ -> . % 76.04/76.31 111664[81:Spt:111662.0,111644.1] || -> node4(s47)*. % 76.04/76.31 111666[81:MRR:777.0,111664.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 111681[81:Res:53.1,111666.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 111683[82:Spt:111681.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 111685[82:Res:111683.0,61.1] always3(s47) || -> . % 76.04/76.31 111686[82:SSi:111685.0,78277.0,78280.0,108797.0,111643.0,111664.0] || -> . % 76.04/76.31 111687[82:Spt:111686.0,111681.0,111683.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 111688[82:Spt:111686.0,111681.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 111692[82:Res:111688.0,61.1] always3(s48) || -> . % 76.04/76.31 111693[82:SSi:111692.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 111694[80:Spt:111693.0,111642.0,111643.0] || until2p7(s47)*+ -> . % 76.04/76.31 111695[80:Spt:111693.0,111642.1] || -> node4(s46)*. % 76.04/76.31 111697[80:MRR:780.0,111695.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 111707[80:Res:53.1,111697.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 111709[81:Spt:111707.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 111711[81:Res:111709.0,61.1] always3(s46) || -> . % 76.04/76.31 111712[81:SSi:111711.0,78272.0,78276.0,108796.0,111641.0,111695.0] || -> . % 76.04/76.31 111713[81:Spt:111712.0,111707.0,111709.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 111714[81:Spt:111712.0,111707.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 111718[81:Res:111714.0,61.1] always3(s47) || -> . % 76.04/76.31 111719[81:SSi:111718.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 111720[79:Spt:111719.0,111640.0,111641.0] || until2p7(s46)*+ -> . % 76.04/76.31 111721[79:Spt:111719.0,111640.1] || -> node4(s45)*. % 76.04/76.31 111723[79:MRR:783.0,111721.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 111726[79:Res:53.1,111723.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 111728[80:Spt:111726.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 111730[80:Res:111728.0,61.1] always3(s45) || -> . % 76.04/76.31 111731[80:SSi:111730.0,78268.0,78271.0,108795.0,111639.0,111721.0] || -> . % 76.04/76.31 111732[80:Spt:111731.0,111726.0,111728.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 111733[80:Spt:111731.0,111726.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 111737[80:Res:111733.0,61.1] always3(s46) || -> . % 76.04/76.31 111738[80:SSi:111737.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 111739[78:Spt:111738.0,111638.0,111639.0] || until2p7(s45)*+ -> . % 76.04/76.31 111740[78:Spt:111738.0,111638.1] || -> node4(s44)*. % 76.04/76.31 111742[78:MRR:786.0,111740.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 111745[78:Res:53.1,111742.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 111747[79:Spt:111745.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 111749[79:Res:111747.0,61.1] always3(s44) || -> . % 76.04/76.31 111750[79:SSi:111749.0,78263.0,78267.0,108794.0,111637.0,111740.0] || -> . % 76.04/76.31 111751[79:Spt:111750.0,111745.0,111747.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 111752[79:Spt:111750.0,111745.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 111756[79:Res:111752.0,61.1] always3(s45) || -> . % 76.04/76.31 111757[79:SSi:111756.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 111758[77:Spt:111757.0,111636.0,111637.0] || until2p7(s44)*+ -> . % 76.04/76.31 111759[77:Spt:111757.0,111636.1] || -> node4(s43)*. % 76.04/76.31 111761[77:MRR:789.0,111759.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 111764[77:Res:53.1,111761.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 111769[78:Spt:111764.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 111771[78:Res:111769.0,61.1] always3(s43) || -> . % 76.04/76.31 111772[78:SSi:111771.0,78259.0,78262.0,108793.0,111635.0,111759.0] || -> . % 76.04/76.31 111773[78:Spt:111772.0,111764.0,111769.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 111774[78:Spt:111772.0,111764.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 111778[78:Res:111774.0,61.1] always3(s44) || -> . % 76.04/76.31 111779[78:SSi:111778.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 111780[76:Spt:111779.0,111634.0,111635.0] || until2p7(s43)*+ -> . % 76.04/76.31 111781[76:Spt:111779.0,111634.1] || -> node4(s42)*. % 76.04/76.31 111783[76:MRR:792.0,111781.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 111786[76:Res:53.1,111783.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 111788[77:Spt:111786.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 111790[77:Res:111788.0,61.1] always3(s42) || -> . % 76.04/76.31 111791[77:SSi:111790.0,78254.0,78258.0,108792.0,111633.0,111781.0] || -> . % 76.04/76.31 111792[77:Spt:111791.0,111786.0,111788.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 111793[77:Spt:111791.0,111786.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 111797[77:Res:111793.0,61.1] always3(s43) || -> . % 76.04/76.31 111798[77:SSi:111797.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 111799[75:Spt:111798.0,111632.0,111633.0] || until2p7(s42)*+ -> . % 76.04/76.31 111800[75:Spt:111798.0,111632.1] || -> node4(s41)*. % 76.04/76.31 111802[75:MRR:795.0,111800.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 111805[75:Res:53.1,111802.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 111807[76:Spt:111805.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 111809[76:Res:111807.0,61.1] always3(s41) || -> . % 76.04/76.31 111810[76:SSi:111809.0,78250.0,78253.0,108791.0,111631.0,111800.0] || -> . % 76.04/76.31 111811[76:Spt:111810.0,111805.0,111807.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.31 111812[76:Spt:111810.0,111805.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 111816[76:Res:111812.0,61.1] always3(s42) || -> . % 76.04/76.31 111817[76:SSi:111816.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 111818[74:Spt:111817.0,111630.0,111631.0] || until2p7(s41)*+ -> . % 76.04/76.31 111819[74:Spt:111817.0,111630.1] || -> node4(s40)*. % 76.04/76.31 111821[74:MRR:798.0,111819.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.31 111824[74:Res:53.1,111821.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.31 111826[75:Spt:111824.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 111828[75:Res:111826.0,61.1] always3(s40) || -> . % 76.04/76.31 111829[75:SSi:111828.0,78245.0,78249.0,108790.0,111629.0,111819.0] || -> . % 76.04/76.31 111830[75:Spt:111829.0,111824.0,111826.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.31 111831[75:Spt:111829.0,111824.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 111835[75:Res:111831.0,61.1] always3(s41) || -> . % 76.04/76.31 111836[75:SSi:111835.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 111837[73:Spt:111836.0,111628.0,111629.0] || until2p7(s40)*+ -> . % 76.04/76.31 111838[73:Spt:111836.0,111628.1] || -> node4(s39)*. % 76.04/76.31 111840[73:MRR:801.0,111838.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.31 111843[73:Res:53.1,111840.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.31 111848[74:Spt:111843.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 111850[74:Res:111848.0,61.1] always3(s39) || -> . % 76.04/76.31 111851[74:SSi:111850.0,78241.0,78244.0,108789.0,111627.0,111838.0] || -> . % 76.04/76.31 111852[74:Spt:111851.0,111843.0,111848.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.31 111853[74:Spt:111851.0,111843.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 111857[74:Res:111853.0,61.1] always3(s40) || -> . % 76.04/76.31 111858[74:SSi:111857.0,78245.0,78249.0,108790.0] || -> . % 76.04/76.31 111859[72:Spt:111858.0,111626.0,111627.0] || until2p7(s39)*+ -> . % 76.04/76.31 111860[72:Spt:111858.0,111626.1] || -> node4(s38)*. % 76.04/76.31 111862[72:MRR:804.0,111860.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.31 111865[72:Res:53.1,111862.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.31 111867[73:Spt:111865.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 111869[73:Res:111867.0,61.1] always3(s38) || -> . % 76.04/76.31 111870[73:SSi:111869.0,78236.0,78240.0,108788.0,111625.0,111860.0] || -> . % 76.04/76.31 111871[73:Spt:111870.0,111865.0,111867.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.31 111872[73:Spt:111870.0,111865.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 111876[73:Res:111872.0,61.1] always3(s39) || -> . % 76.04/76.31 111877[73:SSi:111876.0,78241.0,78244.0,108789.0] || -> . % 76.04/76.31 111878[71:Spt:111877.0,111624.0,111625.0] || until2p7(s38)*+ -> . % 76.04/76.31 111879[71:Spt:111877.0,111624.1] || -> node4(s37)*. % 76.04/76.31 111881[71:MRR:807.0,111879.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.31 111884[71:Res:53.1,111881.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.31 111886[72:Spt:111884.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 111888[72:Res:111886.0,61.1] always3(s37) || -> . % 76.04/76.31 111889[72:SSi:111888.0,78232.0,78235.0,108787.0,111623.0,111879.0] || -> . % 76.04/76.31 111890[72:Spt:111889.0,111884.0,111886.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.31 111891[72:Spt:111889.0,111884.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 111895[72:Res:111891.0,61.1] always3(s38) || -> . % 76.04/76.31 111896[72:SSi:111895.0,78236.0,78240.0,108788.0] || -> . % 76.04/76.31 111897[70:Spt:111896.0,111622.0,111623.0] || until2p7(s37)*+ -> . % 76.04/76.31 111898[70:Spt:111896.0,111622.1] || -> node4(s36)*. % 76.04/76.31 111900[70:MRR:810.0,111898.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.31 111903[70:Res:53.1,111900.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.31 111905[71:Spt:111903.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 111907[71:Res:111905.0,61.1] always3(s36) || -> . % 76.04/76.31 111908[71:SSi:111907.0,78227.0,78231.0,108786.0,111621.0,111898.0] || -> . % 76.04/76.31 111909[71:Spt:111908.0,111903.0,111905.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.31 111910[71:Spt:111908.0,111903.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 111914[71:Res:111910.0,61.1] always3(s37) || -> . % 76.04/76.31 111915[71:SSi:111914.0,78232.0,78235.0,108787.0] || -> . % 76.04/76.31 111916[69:Spt:111915.0,111620.0,111621.0] || until2p7(s36)*+ -> . % 76.04/76.31 111917[69:Spt:111915.0,111620.1] || -> node4(s35)*. % 76.04/76.31 111919[69:MRR:813.0,111917.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.31 111922[69:Res:53.1,111919.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.31 111924[69:MRR:111922.0,111610.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 111929[69:Res:111924.0,61.1] always3(s36) || -> . % 76.04/76.31 111930[69:SSi:111929.0,78227.0,78231.0,108786.0] || -> . % 76.04/76.31 111931[67:Spt:111930.0,111544.0,111547.0] || trans(s49,s35)*+ -> . % 76.04/76.31 111932[67:Spt:111930.0,111544.1,111544.2,111544.3,111544.4,111544.5,111544.6,111544.7,111544.8,111544.9,111544.10,111544.11,111544.12,111544.13,111544.14,111544.15,111544.16,111544.17,111544.18,111544.19,111544.20,111544.21,111544.22,111544.23,111544.24,111544.25,111544.26,111544.27,111544.28,111544.29,111544.30,111544.31,111544.32] || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 111934[67:MRR:111546.1,111931.0] xuntil6(s49) || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 111935[68:Spt:111932.0] || -> trans(s49,s34)*. % 76.04/76.31 111936[68:Res:111935.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s34)*. % 76.04/76.31 111938[68:Res:111935.0,60.0] || -> node2(s49,s34)*. % 76.04/76.31 111939[68:SSi:111936.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s34)*. % 76.04/76.31 111940[68:Res:111938.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)*. % 76.04/76.31 111991[68:SoR:111940.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)*. % 76.04/76.31 111993[68:SoR:111991.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)* xuntil6(s49). % 76.04/76.31 111994[68:SSi:111993.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s34,c_busy)* xuntil6(s49). % 76.04/76.31 111995[69:Spt:111994.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.31 111997[69:Res:111995.0,61.1] always3(s34) || -> . % 76.04/76.31 111998[69:SSi:111997.0,78218.0,78222.0,108784.0] || -> . % 76.04/76.31 111999[69:Spt:111998.0,111994.1,111995.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.04/76.31 112000[69:Spt:111998.0,111994.0,111994.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 112004[69:MRR:111991.2,111999.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 112005[69:Res:53.1,112000.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 112007[69:MRR:112005.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 112008[69:MRR:111939.0,112007.0] || -> until2p7(s34)*. % 76.04/76.31 112009[69:MRR:230.0,112008.0] || -> until2p7(s35)* node4(s34). % 76.04/76.31 112010[70:Spt:112009.0] || -> until2p7(s35)*. % 76.04/76.31 112011[70:MRR:231.0,112010.0] || -> until2p7(s36)* node4(s35). % 76.04/76.31 112012[71:Spt:112011.0] || -> until2p7(s36)*. % 76.04/76.31 112013[71:MRR:232.0,112012.0] || -> until2p7(s37)* node4(s36). % 76.04/76.31 112014[72:Spt:112013.0] || -> until2p7(s37)*. % 76.04/76.31 112015[72:MRR:235.0,112014.0] || -> until2p7(s38)* node4(s37). % 76.04/76.31 112016[73:Spt:112015.0] || -> until2p7(s38)*. % 76.04/76.31 112017[73:MRR:236.0,112016.0] || -> until2p7(s39)* node4(s38). % 76.04/76.31 112018[74:Spt:112017.0] || -> until2p7(s39)*. % 76.04/76.31 112019[74:MRR:237.0,112018.0] || -> until2p7(s40)* node4(s39). % 76.04/76.31 112020[75:Spt:112019.0] || -> until2p7(s40)*. % 76.04/76.31 112021[75:MRR:238.0,112020.0] || -> until2p7(s41)* node4(s40). % 76.04/76.31 112022[76:Spt:112021.0] || -> until2p7(s41)*. % 76.04/76.31 112023[76:MRR:239.0,112022.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 112024[77:Spt:112023.0] || -> until2p7(s42)*. % 76.04/76.31 112025[77:MRR:240.0,112024.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 112026[78:Spt:112025.0] || -> until2p7(s43)*. % 76.04/76.31 112027[78:MRR:241.0,112026.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 112028[79:Spt:112027.0] || -> until2p7(s44)*. % 76.04/76.31 112029[79:MRR:539.0,112028.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 112030[80:Spt:112029.0] || -> until2p7(s45)*. % 76.04/76.31 112031[80:MRR:544.0,112030.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 112032[81:Spt:112031.0] || -> until2p7(s46)*. % 76.04/76.31 112033[81:MRR:549.0,112032.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 112034[82:Spt:112033.0] || -> until2p7(s47)*. % 76.04/76.31 112035[82:MRR:554.0,112034.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 112036[83:Spt:112035.0] || -> until2p7(s48)*. % 76.04/76.31 112037[83:MRR:559.0,112036.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 112038[84:Spt:112037.0] || -> until2p7(s49)*. % 76.04/76.31 112039[84:MRR:194.0,112038.0] || -> node4(s49)*. % 76.04/76.31 112040[84:MRR:112004.0,112039.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 112041[84:Res:53.1,112040.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 112043[84:MRR:112041.0,78381.0] || -> . % 76.04/76.31 112044[84:Spt:112043.0,112037.0,112038.0] || until2p7(s49)*+ -> . % 76.04/76.31 112045[84:Spt:112043.0,112037.1] || -> node4(s48)*. % 76.04/76.31 112046[84:MRR:78384.0,112045.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 112049[84:Res:53.1,112046.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 112052[84:Res:112049.0,61.1] always3(s48) || -> . % 76.04/76.31 112053[84:SSi:112052.0,78281.0,78387.0,108798.0,112036.0,112045.0] || -> . % 76.04/76.31 112054[83:Spt:112053.0,112035.0,112036.0] || until2p7(s48)*+ -> . % 76.04/76.31 112055[83:Spt:112053.0,112035.1] || -> node4(s47)*. % 76.04/76.31 112057[83:MRR:777.0,112055.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 112072[83:Res:53.1,112057.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 112074[84:Spt:112072.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 112076[84:Res:112074.0,61.1] always3(s47) || -> . % 76.04/76.31 112077[84:SSi:112076.0,78277.0,78280.0,108797.0,112034.0,112055.0] || -> . % 76.04/76.31 112078[84:Spt:112077.0,112072.0,112074.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 112079[84:Spt:112077.0,112072.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 112083[84:Res:112079.0,61.1] always3(s48) || -> . % 76.04/76.31 112084[84:SSi:112083.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 112085[82:Spt:112084.0,112033.0,112034.0] || until2p7(s47)*+ -> . % 76.04/76.31 112086[82:Spt:112084.0,112033.1] || -> node4(s46)*. % 76.04/76.31 112088[82:MRR:780.0,112086.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 112098[82:Res:53.1,112088.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 112100[83:Spt:112098.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 112102[83:Res:112100.0,61.1] always3(s46) || -> . % 76.04/76.31 112103[83:SSi:112102.0,78272.0,78276.0,108796.0,112032.0,112086.0] || -> . % 76.04/76.31 112104[83:Spt:112103.0,112098.0,112100.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 112105[83:Spt:112103.0,112098.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 112109[83:Res:112105.0,61.1] always3(s47) || -> . % 76.04/76.31 112110[83:SSi:112109.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 112111[81:Spt:112110.0,112031.0,112032.0] || until2p7(s46)*+ -> . % 76.04/76.31 112112[81:Spt:112110.0,112031.1] || -> node4(s45)*. % 76.04/76.31 112114[81:MRR:783.0,112112.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 112117[81:Res:53.1,112114.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 112119[82:Spt:112117.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 112121[82:Res:112119.0,61.1] always3(s45) || -> . % 76.04/76.31 112122[82:SSi:112121.0,78268.0,78271.0,108795.0,112030.0,112112.0] || -> . % 76.04/76.31 112123[82:Spt:112122.0,112117.0,112119.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 112124[82:Spt:112122.0,112117.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 112128[82:Res:112124.0,61.1] always3(s46) || -> . % 76.04/76.31 112129[82:SSi:112128.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 112130[80:Spt:112129.0,112029.0,112030.0] || until2p7(s45)*+ -> . % 76.04/76.31 112131[80:Spt:112129.0,112029.1] || -> node4(s44)*. % 76.04/76.31 112133[80:MRR:786.0,112131.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 112136[80:Res:53.1,112133.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 112138[81:Spt:112136.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 112140[81:Res:112138.0,61.1] always3(s44) || -> . % 76.04/76.31 112141[81:SSi:112140.0,78263.0,78267.0,108794.0,112028.0,112131.0] || -> . % 76.04/76.31 112142[81:Spt:112141.0,112136.0,112138.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 112143[81:Spt:112141.0,112136.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 112147[81:Res:112143.0,61.1] always3(s45) || -> . % 76.04/76.31 112148[81:SSi:112147.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 112149[79:Spt:112148.0,112027.0,112028.0] || until2p7(s44)*+ -> . % 76.04/76.31 112150[79:Spt:112148.0,112027.1] || -> node4(s43)*. % 76.04/76.31 112152[79:MRR:789.0,112150.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 112155[79:Res:53.1,112152.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 112160[80:Spt:112155.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 112162[80:Res:112160.0,61.1] always3(s43) || -> . % 76.04/76.31 112163[80:SSi:112162.0,78259.0,78262.0,108793.0,112026.0,112150.0] || -> . % 76.04/76.31 112164[80:Spt:112163.0,112155.0,112160.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 112165[80:Spt:112163.0,112155.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 112169[80:Res:112165.0,61.1] always3(s44) || -> . % 76.04/76.31 112170[80:SSi:112169.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 112171[78:Spt:112170.0,112025.0,112026.0] || until2p7(s43)*+ -> . % 76.04/76.31 112172[78:Spt:112170.0,112025.1] || -> node4(s42)*. % 76.04/76.31 112174[78:MRR:792.0,112172.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 112177[78:Res:53.1,112174.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 112179[79:Spt:112177.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 112181[79:Res:112179.0,61.1] always3(s42) || -> . % 76.04/76.31 112182[79:SSi:112181.0,78254.0,78258.0,108792.0,112024.0,112172.0] || -> . % 76.04/76.31 112183[79:Spt:112182.0,112177.0,112179.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 112184[79:Spt:112182.0,112177.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 112188[79:Res:112184.0,61.1] always3(s43) || -> . % 76.04/76.31 112189[79:SSi:112188.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 112190[77:Spt:112189.0,112023.0,112024.0] || until2p7(s42)*+ -> . % 76.04/76.31 112191[77:Spt:112189.0,112023.1] || -> node4(s41)*. % 76.04/76.31 112193[77:MRR:795.0,112191.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 112196[77:Res:53.1,112193.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 112198[78:Spt:112196.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 112200[78:Res:112198.0,61.1] always3(s41) || -> . % 76.04/76.31 112201[78:SSi:112200.0,78250.0,78253.0,108791.0,112022.0,112191.0] || -> . % 76.04/76.31 112202[78:Spt:112201.0,112196.0,112198.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.31 112203[78:Spt:112201.0,112196.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 112207[78:Res:112203.0,61.1] always3(s42) || -> . % 76.04/76.31 112208[78:SSi:112207.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 112209[76:Spt:112208.0,112021.0,112022.0] || until2p7(s41)*+ -> . % 76.04/76.31 112210[76:Spt:112208.0,112021.1] || -> node4(s40)*. % 76.04/76.31 112212[76:MRR:798.0,112210.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.31 112215[76:Res:53.1,112212.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.31 112217[77:Spt:112215.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 112219[77:Res:112217.0,61.1] always3(s40) || -> . % 76.04/76.31 112220[77:SSi:112219.0,78245.0,78249.0,108790.0,112020.0,112210.0] || -> . % 76.04/76.31 112221[77:Spt:112220.0,112215.0,112217.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.31 112222[77:Spt:112220.0,112215.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 112226[77:Res:112222.0,61.1] always3(s41) || -> . % 76.04/76.31 112227[77:SSi:112226.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 112228[75:Spt:112227.0,112019.0,112020.0] || until2p7(s40)*+ -> . % 76.04/76.31 112229[75:Spt:112227.0,112019.1] || -> node4(s39)*. % 76.04/76.31 112231[75:MRR:801.0,112229.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.31 112234[75:Res:53.1,112231.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.31 112239[76:Spt:112234.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 112241[76:Res:112239.0,61.1] always3(s39) || -> . % 76.04/76.31 112242[76:SSi:112241.0,78241.0,78244.0,108789.0,112018.0,112229.0] || -> . % 76.04/76.31 112243[76:Spt:112242.0,112234.0,112239.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.31 112244[76:Spt:112242.0,112234.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 112248[76:Res:112244.0,61.1] always3(s40) || -> . % 76.04/76.31 112249[76:SSi:112248.0,78245.0,78249.0,108790.0] || -> . % 76.04/76.31 112250[74:Spt:112249.0,112017.0,112018.0] || until2p7(s39)*+ -> . % 76.04/76.31 112251[74:Spt:112249.0,112017.1] || -> node4(s38)*. % 76.04/76.31 112253[74:MRR:804.0,112251.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.31 112256[74:Res:53.1,112253.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.31 112258[75:Spt:112256.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 112260[75:Res:112258.0,61.1] always3(s38) || -> . % 76.04/76.31 112261[75:SSi:112260.0,78236.0,78240.0,108788.0,112016.0,112251.0] || -> . % 76.04/76.31 112262[75:Spt:112261.0,112256.0,112258.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.31 112263[75:Spt:112261.0,112256.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 112267[75:Res:112263.0,61.1] always3(s39) || -> . % 76.04/76.31 112268[75:SSi:112267.0,78241.0,78244.0,108789.0] || -> . % 76.04/76.31 112269[73:Spt:112268.0,112015.0,112016.0] || until2p7(s38)*+ -> . % 76.04/76.31 112270[73:Spt:112268.0,112015.1] || -> node4(s37)*. % 76.04/76.31 112272[73:MRR:807.0,112270.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.31 112275[73:Res:53.1,112272.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.31 112277[74:Spt:112275.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 112279[74:Res:112277.0,61.1] always3(s37) || -> . % 76.04/76.31 112280[74:SSi:112279.0,78232.0,78235.0,108787.0,112014.0,112270.0] || -> . % 76.04/76.31 112281[74:Spt:112280.0,112275.0,112277.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.31 112282[74:Spt:112280.0,112275.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 112286[74:Res:112282.0,61.1] always3(s38) || -> . % 76.04/76.31 112287[74:SSi:112286.0,78236.0,78240.0,108788.0] || -> . % 76.04/76.31 112288[72:Spt:112287.0,112013.0,112014.0] || until2p7(s37)*+ -> . % 76.04/76.31 112289[72:Spt:112287.0,112013.1] || -> node4(s36)*. % 76.04/76.31 112291[72:MRR:810.0,112289.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.31 112294[72:Res:53.1,112291.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.31 112296[73:Spt:112294.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 112298[73:Res:112296.0,61.1] always3(s36) || -> . % 76.04/76.31 112299[73:SSi:112298.0,78227.0,78231.0,108786.0,112012.0,112289.0] || -> . % 76.04/76.31 112300[73:Spt:112299.0,112294.0,112296.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.31 112301[73:Spt:112299.0,112294.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 112305[73:Res:112301.0,61.1] always3(s37) || -> . % 76.04/76.31 112306[73:SSi:112305.0,78232.0,78235.0,108787.0] || -> . % 76.04/76.31 112307[71:Spt:112306.0,112011.0,112012.0] || until2p7(s36)*+ -> . % 76.04/76.31 112308[71:Spt:112306.0,112011.1] || -> node4(s35)*. % 76.04/76.31 112310[71:MRR:813.0,112308.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.31 112313[71:Res:53.1,112310.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.31 112318[72:Spt:112313.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 112320[72:Res:112318.0,61.1] always3(s35) || -> . % 76.04/76.31 112321[72:SSi:112320.0,78223.0,78226.0,108785.0,112010.0,112308.0] || -> . % 76.04/76.31 112322[72:Spt:112321.0,112313.0,112318.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.31 112323[72:Spt:112321.0,112313.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 112327[72:Res:112323.0,61.1] always3(s36) || -> . % 76.04/76.31 112328[72:SSi:112327.0,78227.0,78231.0,108786.0] || -> . % 76.04/76.31 112329[70:Spt:112328.0,112009.0,112010.0] || until2p7(s35)*+ -> . % 76.04/76.31 112330[70:Spt:112328.0,112009.1] || -> node4(s34)*. % 76.04/76.31 112332[70:MRR:816.0,112330.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.31 112335[70:Res:53.1,112332.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.31 112337[70:MRR:112335.0,111999.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 112339[70:Res:112337.0,61.1] always3(s35) || -> . % 76.04/76.31 112340[70:SSi:112339.0,78223.0,78226.0,108785.0] || -> . % 76.04/76.31 112341[68:Spt:112340.0,111932.0,111935.0] || trans(s49,s34)*+ -> . % 76.04/76.31 112342[68:Spt:112340.0,111932.1,111932.2,111932.3,111932.4,111932.5,111932.6,111932.7,111932.8,111932.9,111932.10,111932.11,111932.12,111932.13,111932.14,111932.15,111932.16,111932.17,111932.18,111932.19,111932.20,111932.21,111932.22,111932.23,111932.24,111932.25,111932.26,111932.27,111932.28,111932.29,111932.30,111932.31] || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 112344[68:MRR:111934.1,112341.0] xuntil6(s49) || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 112345[69:Spt:112342.0] || -> trans(s49,s33)*. % 76.04/76.31 112346[69:Res:112345.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s33)*. % 76.04/76.31 112348[69:Res:112345.0,60.0] || -> node2(s49,s33)*. % 76.04/76.31 112349[69:SSi:112346.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s33)*. % 76.04/76.31 112350[69:Res:112348.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.04/76.31 112405[69:SoR:112350.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.04/76.31 112407[69:SoR:112405.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.04/76.31 112408[69:SSi:112407.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.04/76.31 112409[70:Spt:112408.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.31 112411[70:Res:112409.0,61.1] always3(s33) || -> . % 76.04/76.31 112412[70:SSi:112411.0,78214.0,78217.0,108783.0] || -> . % 76.04/76.31 112413[70:Spt:112412.0,112408.1,112409.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.04/76.31 112414[70:Spt:112412.0,112408.0,112408.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 112418[70:MRR:112405.2,112413.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 112419[70:Res:53.1,112414.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 112421[70:MRR:112419.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 112422[70:MRR:112349.0,112421.0] || -> until2p7(s33)*. % 76.04/76.31 112423[70:MRR:229.0,112422.0] || -> until2p7(s34)* node4(s33). % 76.04/76.31 112424[71:Spt:112423.0] || -> until2p7(s34)*. % 76.04/76.31 112425[71:MRR:230.0,112424.0] || -> until2p7(s35)* node4(s34). % 76.04/76.31 112426[72:Spt:112425.0] || -> until2p7(s35)*. % 76.04/76.31 112427[72:MRR:231.0,112426.0] || -> until2p7(s36)* node4(s35). % 76.04/76.31 112428[73:Spt:112427.0] || -> until2p7(s36)*. % 76.04/76.31 112429[73:MRR:232.0,112428.0] || -> until2p7(s37)* node4(s36). % 76.04/76.31 112430[74:Spt:112429.0] || -> until2p7(s37)*. % 76.04/76.31 112431[74:MRR:235.0,112430.0] || -> until2p7(s38)* node4(s37). % 76.04/76.31 112432[75:Spt:112431.0] || -> until2p7(s38)*. % 76.04/76.31 112433[75:MRR:236.0,112432.0] || -> until2p7(s39)* node4(s38). % 76.04/76.31 112434[76:Spt:112433.0] || -> until2p7(s39)*. % 76.04/76.31 112435[76:MRR:237.0,112434.0] || -> until2p7(s40)* node4(s39). % 76.04/76.31 112436[77:Spt:112435.0] || -> until2p7(s40)*. % 76.04/76.31 112437[77:MRR:238.0,112436.0] || -> until2p7(s41)* node4(s40). % 76.04/76.31 112438[78:Spt:112437.0] || -> until2p7(s41)*. % 76.04/76.31 112439[78:MRR:239.0,112438.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 112440[79:Spt:112439.0] || -> until2p7(s42)*. % 76.04/76.31 112441[79:MRR:240.0,112440.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 112442[80:Spt:112441.0] || -> until2p7(s43)*. % 76.04/76.31 112443[80:MRR:241.0,112442.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 112444[81:Spt:112443.0] || -> until2p7(s44)*. % 76.04/76.31 112445[81:MRR:539.0,112444.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 112446[82:Spt:112445.0] || -> until2p7(s45)*. % 76.04/76.31 112447[82:MRR:544.0,112446.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 112448[83:Spt:112447.0] || -> until2p7(s46)*. % 76.04/76.31 112449[83:MRR:549.0,112448.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 112450[84:Spt:112449.0] || -> until2p7(s47)*. % 76.04/76.31 112451[84:MRR:554.0,112450.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 112452[85:Spt:112451.0] || -> until2p7(s48)*. % 76.04/76.31 112453[85:MRR:559.0,112452.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 112454[86:Spt:112453.0] || -> until2p7(s49)*. % 76.04/76.31 112455[86:MRR:194.0,112454.0] || -> node4(s49)*. % 76.04/76.31 112456[86:MRR:112418.0,112455.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 112460[86:Res:53.1,112456.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 112462[86:MRR:112460.0,78381.0] || -> . % 76.04/76.31 112463[86:Spt:112462.0,112453.0,112454.0] || until2p7(s49)*+ -> . % 76.04/76.31 112464[86:Spt:112462.0,112453.1] || -> node4(s48)*. % 76.04/76.31 112465[86:MRR:78384.0,112464.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 112468[86:Res:53.1,112465.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 112471[86:Res:112468.0,61.1] always3(s48) || -> . % 76.04/76.31 112472[86:SSi:112471.0,78281.0,78387.0,108798.0,112452.0,112464.0] || -> . % 76.04/76.31 112473[85:Spt:112472.0,112451.0,112452.0] || until2p7(s48)*+ -> . % 76.04/76.31 112474[85:Spt:112472.0,112451.1] || -> node4(s47)*. % 76.04/76.31 112476[85:MRR:777.0,112474.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 112488[85:Res:53.1,112476.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 112490[86:Spt:112488.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 112492[86:Res:112490.0,61.1] always3(s47) || -> . % 76.04/76.31 112493[86:SSi:112492.0,78277.0,78280.0,108797.0,112450.0,112474.0] || -> . % 76.04/76.31 112494[86:Spt:112493.0,112488.0,112490.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 112495[86:Spt:112493.0,112488.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 112499[86:Res:112495.0,61.1] always3(s48) || -> . % 76.04/76.31 112500[86:SSi:112499.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 112501[84:Spt:112500.0,112449.0,112450.0] || until2p7(s47)*+ -> . % 76.04/76.31 112502[84:Spt:112500.0,112449.1] || -> node4(s46)*. % 76.04/76.31 112504[84:MRR:780.0,112502.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 112511[84:Res:53.1,112504.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 112516[85:Spt:112511.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 112518[85:Res:112516.0,61.1] always3(s46) || -> . % 76.04/76.31 112519[85:SSi:112518.0,78272.0,78276.0,108796.0,112448.0,112502.0] || -> . % 76.04/76.31 112520[85:Spt:112519.0,112511.0,112516.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 112521[85:Spt:112519.0,112511.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 112525[85:Res:112521.0,61.1] always3(s47) || -> . % 76.04/76.31 112526[85:SSi:112525.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 112527[83:Spt:112526.0,112447.0,112448.0] || until2p7(s46)*+ -> . % 76.04/76.31 112528[83:Spt:112526.0,112447.1] || -> node4(s45)*. % 76.04/76.31 112530[83:MRR:783.0,112528.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 112533[83:Res:53.1,112530.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 112535[84:Spt:112533.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 112537[84:Res:112535.0,61.1] always3(s45) || -> . % 76.04/76.31 112538[84:SSi:112537.0,78268.0,78271.0,108795.0,112446.0,112528.0] || -> . % 76.04/76.31 112539[84:Spt:112538.0,112533.0,112535.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 112540[84:Spt:112538.0,112533.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 112544[84:Res:112540.0,61.1] always3(s46) || -> . % 76.04/76.31 112545[84:SSi:112544.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 112546[82:Spt:112545.0,112445.0,112446.0] || until2p7(s45)*+ -> . % 76.04/76.31 112547[82:Spt:112545.0,112445.1] || -> node4(s44)*. % 76.04/76.31 112549[82:MRR:786.0,112547.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 112552[82:Res:53.1,112549.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 112554[83:Spt:112552.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 112556[83:Res:112554.0,61.1] always3(s44) || -> . % 76.04/76.31 112557[83:SSi:112556.0,78263.0,78267.0,108794.0,112444.0,112547.0] || -> . % 76.04/76.31 112558[83:Spt:112557.0,112552.0,112554.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 112559[83:Spt:112557.0,112552.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 112563[83:Res:112559.0,61.1] always3(s45) || -> . % 76.04/76.31 112564[83:SSi:112563.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 112565[81:Spt:112564.0,112443.0,112444.0] || until2p7(s44)*+ -> . % 76.04/76.31 112566[81:Spt:112564.0,112443.1] || -> node4(s43)*. % 76.04/76.31 112568[81:MRR:789.0,112566.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 112571[81:Res:53.1,112568.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 112573[82:Spt:112571.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 112575[82:Res:112573.0,61.1] always3(s43) || -> . % 76.04/76.31 112576[82:SSi:112575.0,78259.0,78262.0,108793.0,112442.0,112566.0] || -> . % 76.04/76.31 112577[82:Spt:112576.0,112571.0,112573.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 112578[82:Spt:112576.0,112571.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 112582[82:Res:112578.0,61.1] always3(s44) || -> . % 76.04/76.31 112583[82:SSi:112582.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 112584[80:Spt:112583.0,112441.0,112442.0] || until2p7(s43)*+ -> . % 76.04/76.31 112585[80:Spt:112583.0,112441.1] || -> node4(s42)*. % 76.04/76.31 112587[80:MRR:792.0,112585.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 112590[80:Res:53.1,112587.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 112595[81:Spt:112590.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 112597[81:Res:112595.0,61.1] always3(s42) || -> . % 76.04/76.31 112598[81:SSi:112597.0,78254.0,78258.0,108792.0,112440.0,112585.0] || -> . % 76.04/76.31 112599[81:Spt:112598.0,112590.0,112595.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 112600[81:Spt:112598.0,112590.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 112604[81:Res:112600.0,61.1] always3(s43) || -> . % 76.04/76.31 112605[81:SSi:112604.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 112606[79:Spt:112605.0,112439.0,112440.0] || until2p7(s42)*+ -> . % 76.04/76.31 112607[79:Spt:112605.0,112439.1] || -> node4(s41)*. % 76.04/76.31 112609[79:MRR:795.0,112607.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 112612[79:Res:53.1,112609.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 112614[80:Spt:112612.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 112616[80:Res:112614.0,61.1] always3(s41) || -> . % 76.04/76.31 112617[80:SSi:112616.0,78250.0,78253.0,108791.0,112438.0,112607.0] || -> . % 76.04/76.31 112618[80:Spt:112617.0,112612.0,112614.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.31 112619[80:Spt:112617.0,112612.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 112623[80:Res:112619.0,61.1] always3(s42) || -> . % 76.04/76.31 112624[80:SSi:112623.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 112625[78:Spt:112624.0,112437.0,112438.0] || until2p7(s41)*+ -> . % 76.04/76.31 112626[78:Spt:112624.0,112437.1] || -> node4(s40)*. % 76.04/76.31 112628[78:MRR:798.0,112626.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.31 112631[78:Res:53.1,112628.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.31 112633[79:Spt:112631.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 112635[79:Res:112633.0,61.1] always3(s40) || -> . % 76.04/76.31 112636[79:SSi:112635.0,78245.0,78249.0,108790.0,112436.0,112626.0] || -> . % 76.04/76.31 112637[79:Spt:112636.0,112631.0,112633.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.31 112638[79:Spt:112636.0,112631.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 112642[79:Res:112638.0,61.1] always3(s41) || -> . % 76.04/76.31 112643[79:SSi:112642.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 112644[77:Spt:112643.0,112435.0,112436.0] || until2p7(s40)*+ -> . % 76.04/76.31 112645[77:Spt:112643.0,112435.1] || -> node4(s39)*. % 76.04/76.31 112647[77:MRR:801.0,112645.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.31 112650[77:Res:53.1,112647.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.31 112652[78:Spt:112650.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 112654[78:Res:112652.0,61.1] always3(s39) || -> . % 76.04/76.31 112655[78:SSi:112654.0,78241.0,78244.0,108789.0,112434.0,112645.0] || -> . % 76.04/76.31 112656[78:Spt:112655.0,112650.0,112652.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.31 112657[78:Spt:112655.0,112650.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 112661[78:Res:112657.0,61.1] always3(s40) || -> . % 76.04/76.31 112662[78:SSi:112661.0,78245.0,78249.0,108790.0] || -> . % 76.04/76.31 112663[76:Spt:112662.0,112433.0,112434.0] || until2p7(s39)*+ -> . % 76.04/76.31 112664[76:Spt:112662.0,112433.1] || -> node4(s38)*. % 76.04/76.31 112666[76:MRR:804.0,112664.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.31 112669[76:Res:53.1,112666.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.31 112674[77:Spt:112669.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 112676[77:Res:112674.0,61.1] always3(s38) || -> . % 76.04/76.31 112677[77:SSi:112676.0,78236.0,78240.0,108788.0,112432.0,112664.0] || -> . % 76.04/76.31 112678[77:Spt:112677.0,112669.0,112674.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.31 112679[77:Spt:112677.0,112669.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 112683[77:Res:112679.0,61.1] always3(s39) || -> . % 76.04/76.31 112684[77:SSi:112683.0,78241.0,78244.0,108789.0] || -> . % 76.04/76.31 112685[75:Spt:112684.0,112431.0,112432.0] || until2p7(s38)*+ -> . % 76.04/76.31 112686[75:Spt:112684.0,112431.1] || -> node4(s37)*. % 76.04/76.31 112688[75:MRR:807.0,112686.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.31 112691[75:Res:53.1,112688.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.31 112693[76:Spt:112691.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 112695[76:Res:112693.0,61.1] always3(s37) || -> . % 76.04/76.31 112696[76:SSi:112695.0,78232.0,78235.0,108787.0,112430.0,112686.0] || -> . % 76.04/76.31 112697[76:Spt:112696.0,112691.0,112693.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.31 112698[76:Spt:112696.0,112691.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 112702[76:Res:112698.0,61.1] always3(s38) || -> . % 76.04/76.31 112703[76:SSi:112702.0,78236.0,78240.0,108788.0] || -> . % 76.04/76.31 112704[74:Spt:112703.0,112429.0,112430.0] || until2p7(s37)*+ -> . % 76.04/76.31 112705[74:Spt:112703.0,112429.1] || -> node4(s36)*. % 76.04/76.31 112707[74:MRR:810.0,112705.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.31 112710[74:Res:53.1,112707.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.31 112712[75:Spt:112710.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 112714[75:Res:112712.0,61.1] always3(s36) || -> . % 76.04/76.31 112715[75:SSi:112714.0,78227.0,78231.0,108786.0,112428.0,112705.0] || -> . % 76.04/76.31 112716[75:Spt:112715.0,112710.0,112712.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.31 112717[75:Spt:112715.0,112710.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 112721[75:Res:112717.0,61.1] always3(s37) || -> . % 76.04/76.31 112722[75:SSi:112721.0,78232.0,78235.0,108787.0] || -> . % 76.04/76.31 112723[73:Spt:112722.0,112427.0,112428.0] || until2p7(s36)*+ -> . % 76.04/76.31 112724[73:Spt:112722.0,112427.1] || -> node4(s35)*. % 76.04/76.31 112726[73:MRR:813.0,112724.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.31 112729[73:Res:53.1,112726.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.31 112731[74:Spt:112729.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 112733[74:Res:112731.0,61.1] always3(s35) || -> . % 76.04/76.31 112734[74:SSi:112733.0,78223.0,78226.0,108785.0,112426.0,112724.0] || -> . % 76.04/76.31 112735[74:Spt:112734.0,112729.0,112731.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.31 112736[74:Spt:112734.0,112729.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 112740[74:Res:112736.0,61.1] always3(s36) || -> . % 76.04/76.31 112741[74:SSi:112740.0,78227.0,78231.0,108786.0] || -> . % 76.04/76.31 112742[72:Spt:112741.0,112425.0,112426.0] || until2p7(s35)*+ -> . % 76.04/76.31 112743[72:Spt:112741.0,112425.1] || -> node4(s34)*. % 76.04/76.31 112745[72:MRR:816.0,112743.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.31 112748[72:Res:53.1,112745.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.31 112753[73:Spt:112748.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.31 112755[73:Res:112753.0,61.1] always3(s34) || -> . % 76.04/76.31 112756[73:SSi:112755.0,78218.0,78222.0,108784.0,112424.0,112743.0] || -> . % 76.04/76.31 112757[73:Spt:112756.0,112748.0,112753.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.31 112758[73:Spt:112756.0,112748.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 112762[73:Res:112758.0,61.1] always3(s35) || -> . % 76.04/76.31 112763[73:SSi:112762.0,78223.0,78226.0,108785.0] || -> . % 76.04/76.31 112764[71:Spt:112763.0,112423.0,112424.0] || until2p7(s34)*+ -> . % 76.04/76.31 112765[71:Spt:112763.0,112423.1] || -> node4(s33)*. % 76.04/76.31 112767[71:MRR:819.0,112765.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.31 112770[71:Res:53.1,112767.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.31 112772[71:MRR:112770.0,112413.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.31 112774[71:Res:112772.0,61.1] always3(s34) || -> . % 76.04/76.31 112775[71:SSi:112774.0,78218.0,78222.0,108784.0] || -> . % 76.04/76.31 112776[69:Spt:112775.0,112342.0,112345.0] || trans(s49,s33)*+ -> . % 76.04/76.31 112777[69:Spt:112775.0,112342.1,112342.2,112342.3,112342.4,112342.5,112342.6,112342.7,112342.8,112342.9,112342.10,112342.11,112342.12,112342.13,112342.14,112342.15,112342.16,112342.17,112342.18,112342.19,112342.20,112342.21,112342.22,112342.23,112342.24,112342.25,112342.26,112342.27,112342.28,112342.29,112342.30] || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 112779[69:MRR:112344.1,112776.0] xuntil6(s49) || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 112780[70:Spt:112777.0] || -> trans(s49,s32)*. % 76.04/76.31 112781[70:Res:112780.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s32)*. % 76.04/76.31 112783[70:Res:112780.0,60.0] || -> node2(s49,s32)*. % 76.04/76.31 112784[70:SSi:112781.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s32)*. % 76.04/76.31 112785[70:Res:112783.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)*. % 76.04/76.31 112844[70:SoR:112785.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)*. % 76.04/76.31 112846[70:SoR:112844.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)* xuntil6(s49). % 76.04/76.31 112847[70:SSi:112846.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s32,c_busy)* xuntil6(s49). % 76.04/76.31 112848[71:Spt:112847.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.31 112850[71:Res:112848.0,61.1] always3(s32) || -> . % 76.04/76.31 112851[71:SSi:112850.0,78209.0,78213.0,108782.0] || -> . % 76.04/76.31 112852[71:Spt:112851.0,112847.1,112848.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.04/76.31 112853[71:Spt:112851.0,112847.0,112847.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 112857[71:MRR:112844.2,112852.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 112858[71:Res:53.1,112853.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 112860[71:MRR:112858.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 112861[71:MRR:112784.0,112860.0] || -> until2p7(s32)*. % 76.04/76.31 112862[71:MRR:228.0,112861.0] || -> until2p7(s33)* node4(s32). % 76.04/76.31 112863[72:Spt:112862.0] || -> until2p7(s33)*. % 76.04/76.31 112864[72:MRR:229.0,112863.0] || -> until2p7(s34)* node4(s33). % 76.04/76.31 112865[73:Spt:112864.0] || -> until2p7(s34)*. % 76.04/76.31 112866[73:MRR:230.0,112865.0] || -> until2p7(s35)* node4(s34). % 76.04/76.31 112867[74:Spt:112866.0] || -> until2p7(s35)*. % 76.04/76.31 112868[74:MRR:231.0,112867.0] || -> until2p7(s36)* node4(s35). % 76.04/76.31 112869[75:Spt:112868.0] || -> until2p7(s36)*. % 76.04/76.31 112870[75:MRR:232.0,112869.0] || -> until2p7(s37)* node4(s36). % 76.04/76.31 112871[76:Spt:112870.0] || -> until2p7(s37)*. % 76.04/76.31 112872[76:MRR:235.0,112871.0] || -> until2p7(s38)* node4(s37). % 76.04/76.31 112873[77:Spt:112872.0] || -> until2p7(s38)*. % 76.04/76.31 112874[77:MRR:236.0,112873.0] || -> until2p7(s39)* node4(s38). % 76.04/76.31 112875[78:Spt:112874.0] || -> until2p7(s39)*. % 76.04/76.31 112876[78:MRR:237.0,112875.0] || -> until2p7(s40)* node4(s39). % 76.04/76.31 112877[79:Spt:112876.0] || -> until2p7(s40)*. % 76.04/76.31 112878[79:MRR:238.0,112877.0] || -> until2p7(s41)* node4(s40). % 76.04/76.31 112879[80:Spt:112878.0] || -> until2p7(s41)*. % 76.04/76.31 112880[80:MRR:239.0,112879.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 112881[81:Spt:112880.0] || -> until2p7(s42)*. % 76.04/76.31 112882[81:MRR:240.0,112881.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 112883[82:Spt:112882.0] || -> until2p7(s43)*. % 76.04/76.31 112884[82:MRR:241.0,112883.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 112885[83:Spt:112884.0] || -> until2p7(s44)*. % 76.04/76.31 112886[83:MRR:539.0,112885.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 112887[84:Spt:112886.0] || -> until2p7(s45)*. % 76.04/76.31 112888[84:MRR:544.0,112887.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 112889[85:Spt:112888.0] || -> until2p7(s46)*. % 76.04/76.31 112890[85:MRR:549.0,112889.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 112891[86:Spt:112890.0] || -> until2p7(s47)*. % 76.04/76.31 112892[86:MRR:554.0,112891.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 112893[87:Spt:112892.0] || -> until2p7(s48)*. % 76.04/76.31 112894[87:MRR:559.0,112893.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 112895[88:Spt:112894.0] || -> until2p7(s49)*. % 76.04/76.31 112896[88:MRR:194.0,112895.0] || -> node4(s49)*. % 76.04/76.31 112897[88:MRR:112857.0,112896.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 112898[88:Res:53.1,112897.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 112900[88:MRR:112898.0,78381.0] || -> . % 76.04/76.31 112901[88:Spt:112900.0,112894.0,112895.0] || until2p7(s49)*+ -> . % 76.04/76.31 112902[88:Spt:112900.0,112894.1] || -> node4(s48)*. % 76.04/76.31 112903[88:MRR:78384.0,112902.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 112906[88:Res:53.1,112903.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 112909[88:Res:112906.0,61.1] always3(s48) || -> . % 76.04/76.31 112910[88:SSi:112909.0,78281.0,78387.0,108798.0,112893.0,112902.0] || -> . % 76.04/76.31 112911[87:Spt:112910.0,112892.0,112893.0] || until2p7(s48)*+ -> . % 76.04/76.31 112912[87:Spt:112910.0,112892.1] || -> node4(s47)*. % 76.04/76.31 112914[87:MRR:777.0,112912.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 112929[87:Res:53.1,112914.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 112934[88:Spt:112929.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 112936[88:Res:112934.0,61.1] always3(s47) || -> . % 76.04/76.31 112937[88:SSi:112936.0,78277.0,78280.0,108797.0,112891.0,112912.0] || -> . % 76.04/76.31 112938[88:Spt:112937.0,112929.0,112934.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 112939[88:Spt:112937.0,112929.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 112943[88:Res:112939.0,61.1] always3(s48) || -> . % 76.04/76.31 112944[88:SSi:112943.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 112945[86:Spt:112944.0,112890.0,112891.0] || until2p7(s47)*+ -> . % 76.04/76.31 112946[86:Spt:112944.0,112890.1] || -> node4(s46)*. % 76.04/76.31 112948[86:MRR:780.0,112946.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 112955[86:Res:53.1,112948.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 112957[87:Spt:112955.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 112959[87:Res:112957.0,61.1] always3(s46) || -> . % 76.04/76.31 112960[87:SSi:112959.0,78272.0,78276.0,108796.0,112889.0,112946.0] || -> . % 76.04/76.31 112961[87:Spt:112960.0,112955.0,112957.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 112962[87:Spt:112960.0,112955.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 112966[87:Res:112962.0,61.1] always3(s47) || -> . % 76.04/76.31 112967[87:SSi:112966.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 112968[85:Spt:112967.0,112888.0,112889.0] || until2p7(s46)*+ -> . % 76.04/76.31 112969[85:Spt:112967.0,112888.1] || -> node4(s45)*. % 76.04/76.31 112971[85:MRR:783.0,112969.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 112974[85:Res:53.1,112971.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 112979[86:Spt:112974.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 112981[86:Res:112979.0,61.1] always3(s45) || -> . % 76.04/76.31 112982[86:SSi:112981.0,78268.0,78271.0,108795.0,112887.0,112969.0] || -> . % 76.04/76.31 112983[86:Spt:112982.0,112974.0,112979.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 112984[86:Spt:112982.0,112974.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 112988[86:Res:112984.0,61.1] always3(s46) || -> . % 76.04/76.31 112989[86:SSi:112988.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 112990[84:Spt:112989.0,112886.0,112887.0] || until2p7(s45)*+ -> . % 76.04/76.31 112991[84:Spt:112989.0,112886.1] || -> node4(s44)*. % 76.04/76.31 112993[84:MRR:786.0,112991.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 112996[84:Res:53.1,112993.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 112998[85:Spt:112996.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 113000[85:Res:112998.0,61.1] always3(s44) || -> . % 76.04/76.31 113001[85:SSi:113000.0,78263.0,78267.0,108794.0,112885.0,112991.0] || -> . % 76.04/76.31 113002[85:Spt:113001.0,112996.0,112998.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 113003[85:Spt:113001.0,112996.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 113007[85:Res:113003.0,61.1] always3(s45) || -> . % 76.04/76.31 113008[85:SSi:113007.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 113009[83:Spt:113008.0,112884.0,112885.0] || until2p7(s44)*+ -> . % 76.04/76.31 113010[83:Spt:113008.0,112884.1] || -> node4(s43)*. % 76.04/76.31 113012[83:MRR:789.0,113010.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 113015[83:Res:53.1,113012.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 113017[84:Spt:113015.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 113019[84:Res:113017.0,61.1] always3(s43) || -> . % 76.04/76.31 113020[84:SSi:113019.0,78259.0,78262.0,108793.0,112883.0,113010.0] || -> . % 76.04/76.31 113021[84:Spt:113020.0,113015.0,113017.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 113022[84:Spt:113020.0,113015.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 113026[84:Res:113022.0,61.1] always3(s44) || -> . % 76.04/76.31 113027[84:SSi:113026.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 113028[82:Spt:113027.0,112882.0,112883.0] || until2p7(s43)*+ -> . % 76.04/76.31 113029[82:Spt:113027.0,112882.1] || -> node4(s42)*. % 76.04/76.31 113031[82:MRR:792.0,113029.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 113034[82:Res:53.1,113031.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 113036[83:Spt:113034.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 113038[83:Res:113036.0,61.1] always3(s42) || -> . % 76.04/76.31 113039[83:SSi:113038.0,78254.0,78258.0,108792.0,112881.0,113029.0] || -> . % 76.04/76.31 113040[83:Spt:113039.0,113034.0,113036.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 113041[83:Spt:113039.0,113034.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 113045[83:Res:113041.0,61.1] always3(s43) || -> . % 76.04/76.31 113046[83:SSi:113045.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 113047[81:Spt:113046.0,112880.0,112881.0] || until2p7(s42)*+ -> . % 76.04/76.31 113048[81:Spt:113046.0,112880.1] || -> node4(s41)*. % 76.04/76.31 113050[81:MRR:795.0,113048.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 113053[81:Res:53.1,113050.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 113058[82:Spt:113053.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 113060[82:Res:113058.0,61.1] always3(s41) || -> . % 76.04/76.31 113061[82:SSi:113060.0,78250.0,78253.0,108791.0,112879.0,113048.0] || -> . % 76.04/76.31 113062[82:Spt:113061.0,113053.0,113058.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.31 113063[82:Spt:113061.0,113053.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 113067[82:Res:113063.0,61.1] always3(s42) || -> . % 76.04/76.31 113068[82:SSi:113067.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 113069[80:Spt:113068.0,112878.0,112879.0] || until2p7(s41)*+ -> . % 76.04/76.31 113070[80:Spt:113068.0,112878.1] || -> node4(s40)*. % 76.04/76.31 113072[80:MRR:798.0,113070.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.31 113075[80:Res:53.1,113072.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.31 113077[81:Spt:113075.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 113079[81:Res:113077.0,61.1] always3(s40) || -> . % 76.04/76.31 113080[81:SSi:113079.0,78245.0,78249.0,108790.0,112877.0,113070.0] || -> . % 76.04/76.31 113081[81:Spt:113080.0,113075.0,113077.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.31 113082[81:Spt:113080.0,113075.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 113086[81:Res:113082.0,61.1] always3(s41) || -> . % 76.04/76.31 113087[81:SSi:113086.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 113088[79:Spt:113087.0,112876.0,112877.0] || until2p7(s40)*+ -> . % 76.04/76.31 113089[79:Spt:113087.0,112876.1] || -> node4(s39)*. % 76.04/76.31 113091[79:MRR:801.0,113089.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.31 113094[79:Res:53.1,113091.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.31 113096[80:Spt:113094.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 113098[80:Res:113096.0,61.1] always3(s39) || -> . % 76.04/76.31 113099[80:SSi:113098.0,78241.0,78244.0,108789.0,112875.0,113089.0] || -> . % 76.04/76.31 113100[80:Spt:113099.0,113094.0,113096.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.31 113101[80:Spt:113099.0,113094.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 113105[80:Res:113101.0,61.1] always3(s40) || -> . % 76.04/76.31 113106[80:SSi:113105.0,78245.0,78249.0,108790.0] || -> . % 76.04/76.31 113107[78:Spt:113106.0,112874.0,112875.0] || until2p7(s39)*+ -> . % 76.04/76.31 113108[78:Spt:113106.0,112874.1] || -> node4(s38)*. % 76.04/76.31 113110[78:MRR:804.0,113108.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.31 113113[78:Res:53.1,113110.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.31 113115[79:Spt:113113.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 113117[79:Res:113115.0,61.1] always3(s38) || -> . % 76.04/76.31 113118[79:SSi:113117.0,78236.0,78240.0,108788.0,112873.0,113108.0] || -> . % 76.04/76.31 113119[79:Spt:113118.0,113113.0,113115.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.31 113120[79:Spt:113118.0,113113.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 113124[79:Res:113120.0,61.1] always3(s39) || -> . % 76.04/76.31 113125[79:SSi:113124.0,78241.0,78244.0,108789.0] || -> . % 76.04/76.31 113126[77:Spt:113125.0,112872.0,112873.0] || until2p7(s38)*+ -> . % 76.04/76.31 113127[77:Spt:113125.0,112872.1] || -> node4(s37)*. % 76.04/76.31 113129[77:MRR:807.0,113127.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.31 113132[77:Res:53.1,113129.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.31 113137[78:Spt:113132.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 113139[78:Res:113137.0,61.1] always3(s37) || -> . % 76.04/76.31 113140[78:SSi:113139.0,78232.0,78235.0,108787.0,112871.0,113127.0] || -> . % 76.04/76.31 113141[78:Spt:113140.0,113132.0,113137.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.31 113142[78:Spt:113140.0,113132.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 113146[78:Res:113142.0,61.1] always3(s38) || -> . % 76.04/76.31 113147[78:SSi:113146.0,78236.0,78240.0,108788.0] || -> . % 76.04/76.31 113148[76:Spt:113147.0,112870.0,112871.0] || until2p7(s37)*+ -> . % 76.04/76.31 113149[76:Spt:113147.0,112870.1] || -> node4(s36)*. % 76.04/76.31 113151[76:MRR:810.0,113149.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.31 113154[76:Res:53.1,113151.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.31 113156[77:Spt:113154.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 113158[77:Res:113156.0,61.1] always3(s36) || -> . % 76.04/76.31 113159[77:SSi:113158.0,78227.0,78231.0,108786.0,112869.0,113149.0] || -> . % 76.04/76.31 113160[77:Spt:113159.0,113154.0,113156.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.31 113161[77:Spt:113159.0,113154.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 113165[77:Res:113161.0,61.1] always3(s37) || -> . % 76.04/76.31 113166[77:SSi:113165.0,78232.0,78235.0,108787.0] || -> . % 76.04/76.31 113167[75:Spt:113166.0,112868.0,112869.0] || until2p7(s36)*+ -> . % 76.04/76.31 113168[75:Spt:113166.0,112868.1] || -> node4(s35)*. % 76.04/76.31 113170[75:MRR:813.0,113168.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.31 113173[75:Res:53.1,113170.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.31 113175[76:Spt:113173.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 113177[76:Res:113175.0,61.1] always3(s35) || -> . % 76.04/76.31 113178[76:SSi:113177.0,78223.0,78226.0,108785.0,112867.0,113168.0] || -> . % 76.04/76.31 113179[76:Spt:113178.0,113173.0,113175.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.31 113180[76:Spt:113178.0,113173.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 113184[76:Res:113180.0,61.1] always3(s36) || -> . % 76.04/76.31 113185[76:SSi:113184.0,78227.0,78231.0,108786.0] || -> . % 76.04/76.31 113186[74:Spt:113185.0,112866.0,112867.0] || until2p7(s35)*+ -> . % 76.04/76.31 113187[74:Spt:113185.0,112866.1] || -> node4(s34)*. % 76.04/76.31 113189[74:MRR:816.0,113187.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.31 113192[74:Res:53.1,113189.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.31 113194[75:Spt:113192.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.31 113196[75:Res:113194.0,61.1] always3(s34) || -> . % 76.04/76.31 113197[75:SSi:113196.0,78218.0,78222.0,108784.0,112865.0,113187.0] || -> . % 76.04/76.31 113198[75:Spt:113197.0,113192.0,113194.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.31 113199[75:Spt:113197.0,113192.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 113203[75:Res:113199.0,61.1] always3(s35) || -> . % 76.04/76.31 113204[75:SSi:113203.0,78223.0,78226.0,108785.0] || -> . % 76.04/76.31 113205[73:Spt:113204.0,112864.0,112865.0] || until2p7(s34)*+ -> . % 76.04/76.31 113206[73:Spt:113204.0,112864.1] || -> node4(s33)*. % 76.04/76.31 113208[73:MRR:819.0,113206.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.31 113211[73:Res:53.1,113208.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.31 113216[74:Spt:113211.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.31 113218[74:Res:113216.0,61.1] always3(s33) || -> . % 76.04/76.31 113219[74:SSi:113218.0,78214.0,78217.0,108783.0,112863.0,113206.0] || -> . % 76.04/76.31 113220[74:Spt:113219.0,113211.0,113216.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.31 113221[74:Spt:113219.0,113211.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.31 113225[74:Res:113221.0,61.1] always3(s34) || -> . % 76.04/76.31 113226[74:SSi:113225.0,78218.0,78222.0,108784.0] || -> . % 76.04/76.31 113227[72:Spt:113226.0,112862.0,112863.0] || until2p7(s33)*+ -> . % 76.04/76.31 113228[72:Spt:113226.0,112862.1] || -> node4(s32)*. % 76.04/76.31 113230[72:MRR:822.0,113228.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.31 113233[72:Res:53.1,113230.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.31 113235[72:MRR:113233.0,112852.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.31 113237[72:Res:113235.0,61.1] always3(s33) || -> . % 76.04/76.31 113238[72:SSi:113237.0,78214.0,78217.0,108783.0] || -> . % 76.04/76.31 113239[70:Spt:113238.0,112777.0,112780.0] || trans(s49,s32)*+ -> . % 76.04/76.31 113240[70:Spt:113238.0,112777.1,112777.2,112777.3,112777.4,112777.5,112777.6,112777.7,112777.8,112777.9,112777.10,112777.11,112777.12,112777.13,112777.14,112777.15,112777.16,112777.17,112777.18,112777.19,112777.20,112777.21,112777.22,112777.23,112777.24,112777.25,112777.26,112777.27,112777.28,112777.29] || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 113242[70:MRR:112779.1,113239.0] xuntil6(s49) || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 113243[71:Spt:113240.0] || -> trans(s49,s31)*. % 76.04/76.31 113244[71:Res:113243.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s31)*. % 76.04/76.31 113246[71:Res:113243.0,60.0] || -> node2(s49,s31)*. % 76.04/76.31 113247[71:SSi:113244.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s31)*. % 76.04/76.31 113248[71:Res:113246.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.04/76.31 113308[71:SoR:113248.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.04/76.31 113310[71:SoR:113308.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.04/76.31 113311[71:SSi:113310.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.04/76.31 113312[72:Spt:113311.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.31 113314[72:Res:113312.0,61.1] always3(s31) || -> . % 76.04/76.31 113315[72:SSi:113314.0,78205.0,78208.0,108781.0] || -> . % 76.04/76.31 113316[72:Spt:113315.0,113311.1,113312.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.04/76.31 113317[72:Spt:113315.0,113311.0,113311.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 113321[72:MRR:113308.2,113316.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 113322[72:Res:53.1,113317.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 113324[72:MRR:113322.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 113325[72:MRR:113247.0,113324.0] || -> until2p7(s31)*. % 76.04/76.31 113326[72:MRR:227.0,113325.0] || -> until2p7(s32)* node4(s31). % 76.04/76.31 113327[73:Spt:113326.0] || -> until2p7(s32)*. % 76.04/76.31 113328[73:MRR:228.0,113327.0] || -> until2p7(s33)* node4(s32). % 76.04/76.31 113329[74:Spt:113328.0] || -> until2p7(s33)*. % 76.04/76.31 113330[74:MRR:229.0,113329.0] || -> until2p7(s34)* node4(s33). % 76.04/76.31 113331[75:Spt:113330.0] || -> until2p7(s34)*. % 76.04/76.31 113332[75:MRR:230.0,113331.0] || -> until2p7(s35)* node4(s34). % 76.04/76.31 113333[76:Spt:113332.0] || -> until2p7(s35)*. % 76.04/76.31 113334[76:MRR:231.0,113333.0] || -> until2p7(s36)* node4(s35). % 76.04/76.31 113335[77:Spt:113334.0] || -> until2p7(s36)*. % 76.04/76.31 113336[77:MRR:232.0,113335.0] || -> until2p7(s37)* node4(s36). % 76.04/76.31 113337[78:Spt:113336.0] || -> until2p7(s37)*. % 76.04/76.31 113338[78:MRR:235.0,113337.0] || -> until2p7(s38)* node4(s37). % 76.04/76.31 113339[79:Spt:113338.0] || -> until2p7(s38)*. % 76.04/76.31 113340[79:MRR:236.0,113339.0] || -> until2p7(s39)* node4(s38). % 76.04/76.31 113341[80:Spt:113340.0] || -> until2p7(s39)*. % 76.04/76.31 113342[80:MRR:237.0,113341.0] || -> until2p7(s40)* node4(s39). % 76.04/76.31 113343[81:Spt:113342.0] || -> until2p7(s40)*. % 76.04/76.31 113344[81:MRR:238.0,113343.0] || -> until2p7(s41)* node4(s40). % 76.04/76.31 113345[82:Spt:113344.0] || -> until2p7(s41)*. % 76.04/76.31 113346[82:MRR:239.0,113345.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 113347[83:Spt:113346.0] || -> until2p7(s42)*. % 76.04/76.31 113348[83:MRR:240.0,113347.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 113349[84:Spt:113348.0] || -> until2p7(s43)*. % 76.04/76.31 113350[84:MRR:241.0,113349.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 113351[85:Spt:113350.0] || -> until2p7(s44)*. % 76.04/76.31 113352[85:MRR:539.0,113351.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 113353[86:Spt:113352.0] || -> until2p7(s45)*. % 76.04/76.31 113354[86:MRR:544.0,113353.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 113355[87:Spt:113354.0] || -> until2p7(s46)*. % 76.04/76.31 113356[87:MRR:549.0,113355.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 113357[88:Spt:113356.0] || -> until2p7(s47)*. % 76.04/76.31 113358[88:MRR:554.0,113357.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 113359[89:Spt:113358.0] || -> until2p7(s48)*. % 76.04/76.31 113360[89:MRR:559.0,113359.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 113361[90:Spt:113360.0] || -> until2p7(s49)*. % 76.04/76.31 113362[90:MRR:194.0,113361.0] || -> node4(s49)*. % 76.04/76.31 113363[90:MRR:113321.0,113362.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 113367[90:Res:53.1,113363.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 113369[90:MRR:113367.0,78381.0] || -> . % 76.04/76.31 113370[90:Spt:113369.0,113360.0,113361.0] || until2p7(s49)*+ -> . % 76.04/76.31 113371[90:Spt:113369.0,113360.1] || -> node4(s48)*. % 76.04/76.31 113372[90:MRR:78384.0,113371.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 113375[90:Res:53.1,113372.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 113378[90:Res:113375.0,61.1] always3(s48) || -> . % 76.04/76.31 113379[90:SSi:113378.0,78281.0,78387.0,108798.0,113359.0,113371.0] || -> . % 76.04/76.31 113380[89:Spt:113379.0,113358.0,113359.0] || until2p7(s48)*+ -> . % 76.04/76.31 113381[89:Spt:113379.0,113358.1] || -> node4(s47)*. % 76.04/76.31 113383[89:MRR:777.0,113381.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 113395[89:Res:53.1,113383.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 113397[90:Spt:113395.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 113399[90:Res:113397.0,61.1] always3(s47) || -> . % 76.04/76.31 113400[90:SSi:113399.0,78277.0,78280.0,108797.0,113357.0,113381.0] || -> . % 76.04/76.31 113401[90:Spt:113400.0,113395.0,113397.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 113402[90:Spt:113400.0,113395.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 113406[90:Res:113402.0,61.1] always3(s48) || -> . % 76.04/76.31 113407[90:SSi:113406.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 113408[88:Spt:113407.0,113356.0,113357.0] || until2p7(s47)*+ -> . % 76.04/76.31 113409[88:Spt:113407.0,113356.1] || -> node4(s46)*. % 76.04/76.31 113411[88:MRR:780.0,113409.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 113418[88:Res:53.1,113411.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 113423[89:Spt:113418.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 113425[89:Res:113423.0,61.1] always3(s46) || -> . % 76.04/76.31 113426[89:SSi:113425.0,78272.0,78276.0,108796.0,113355.0,113409.0] || -> . % 76.04/76.31 113427[89:Spt:113426.0,113418.0,113423.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 113428[89:Spt:113426.0,113418.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 113432[89:Res:113428.0,61.1] always3(s47) || -> . % 76.04/76.31 113433[89:SSi:113432.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 113434[87:Spt:113433.0,113354.0,113355.0] || until2p7(s46)*+ -> . % 76.04/76.31 113435[87:Spt:113433.0,113354.1] || -> node4(s45)*. % 76.04/76.31 113437[87:MRR:783.0,113435.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 113440[87:Res:53.1,113437.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 113442[88:Spt:113440.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 113444[88:Res:113442.0,61.1] always3(s45) || -> . % 76.04/76.31 113445[88:SSi:113444.0,78268.0,78271.0,108795.0,113353.0,113435.0] || -> . % 76.04/76.31 113446[88:Spt:113445.0,113440.0,113442.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 113447[88:Spt:113445.0,113440.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 113451[88:Res:113447.0,61.1] always3(s46) || -> . % 76.04/76.31 113452[88:SSi:113451.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 113453[86:Spt:113452.0,113352.0,113353.0] || until2p7(s45)*+ -> . % 76.04/76.31 113454[86:Spt:113452.0,113352.1] || -> node4(s44)*. % 76.04/76.31 113456[86:MRR:786.0,113454.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 113459[86:Res:53.1,113456.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 113461[87:Spt:113459.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 113463[87:Res:113461.0,61.1] always3(s44) || -> . % 76.04/76.31 113464[87:SSi:113463.0,78263.0,78267.0,108794.0,113351.0,113454.0] || -> . % 76.04/76.31 113465[87:Spt:113464.0,113459.0,113461.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 113466[87:Spt:113464.0,113459.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 113470[87:Res:113466.0,61.1] always3(s45) || -> . % 76.04/76.31 113471[87:SSi:113470.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 113472[85:Spt:113471.0,113350.0,113351.0] || until2p7(s44)*+ -> . % 76.04/76.31 113473[85:Spt:113471.0,113350.1] || -> node4(s43)*. % 76.04/76.31 113475[85:MRR:789.0,113473.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 113478[85:Res:53.1,113475.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 113480[86:Spt:113478.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 113482[86:Res:113480.0,61.1] always3(s43) || -> . % 76.04/76.31 113483[86:SSi:113482.0,78259.0,78262.0,108793.0,113349.0,113473.0] || -> . % 76.04/76.31 113484[86:Spt:113483.0,113478.0,113480.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 113485[86:Spt:113483.0,113478.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 113489[86:Res:113485.0,61.1] always3(s44) || -> . % 76.04/76.31 113490[86:SSi:113489.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 113491[84:Spt:113490.0,113348.0,113349.0] || until2p7(s43)*+ -> . % 76.04/76.31 113492[84:Spt:113490.0,113348.1] || -> node4(s42)*. % 76.04/76.31 113494[84:MRR:792.0,113492.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 113497[84:Res:53.1,113494.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 113502[85:Spt:113497.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 113504[85:Res:113502.0,61.1] always3(s42) || -> . % 76.04/76.31 113505[85:SSi:113504.0,78254.0,78258.0,108792.0,113347.0,113492.0] || -> . % 76.04/76.31 113506[85:Spt:113505.0,113497.0,113502.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 113507[85:Spt:113505.0,113497.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 113511[85:Res:113507.0,61.1] always3(s43) || -> . % 76.04/76.31 113512[85:SSi:113511.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 113513[83:Spt:113512.0,113346.0,113347.0] || until2p7(s42)*+ -> . % 76.04/76.31 113514[83:Spt:113512.0,113346.1] || -> node4(s41)*. % 76.04/76.31 113516[83:MRR:795.0,113514.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 113519[83:Res:53.1,113516.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 113521[84:Spt:113519.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 113523[84:Res:113521.0,61.1] always3(s41) || -> . % 76.04/76.31 113524[84:SSi:113523.0,78250.0,78253.0,108791.0,113345.0,113514.0] || -> . % 76.04/76.31 113525[84:Spt:113524.0,113519.0,113521.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.31 113526[84:Spt:113524.0,113519.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 113530[84:Res:113526.0,61.1] always3(s42) || -> . % 76.04/76.31 113531[84:SSi:113530.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 113532[82:Spt:113531.0,113344.0,113345.0] || until2p7(s41)*+ -> . % 76.04/76.31 113533[82:Spt:113531.0,113344.1] || -> node4(s40)*. % 76.04/76.31 113535[82:MRR:798.0,113533.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.31 113538[82:Res:53.1,113535.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.31 113540[83:Spt:113538.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 113542[83:Res:113540.0,61.1] always3(s40) || -> . % 76.04/76.31 113543[83:SSi:113542.0,78245.0,78249.0,108790.0,113343.0,113533.0] || -> . % 76.04/76.31 113544[83:Spt:113543.0,113538.0,113540.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.31 113545[83:Spt:113543.0,113538.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 113549[83:Res:113545.0,61.1] always3(s41) || -> . % 76.04/76.31 113550[83:SSi:113549.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 113551[81:Spt:113550.0,113342.0,113343.0] || until2p7(s40)*+ -> . % 76.04/76.31 113552[81:Spt:113550.0,113342.1] || -> node4(s39)*. % 76.04/76.31 113554[81:MRR:801.0,113552.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.31 113557[81:Res:53.1,113554.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.31 113559[82:Spt:113557.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 113561[82:Res:113559.0,61.1] always3(s39) || -> . % 76.04/76.31 113562[82:SSi:113561.0,78241.0,78244.0,108789.0,113341.0,113552.0] || -> . % 76.04/76.31 113563[82:Spt:113562.0,113557.0,113559.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.31 113564[82:Spt:113562.0,113557.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 113568[82:Res:113564.0,61.1] always3(s40) || -> . % 76.04/76.31 113569[82:SSi:113568.0,78245.0,78249.0,108790.0] || -> . % 76.04/76.31 113570[80:Spt:113569.0,113340.0,113341.0] || until2p7(s39)*+ -> . % 76.04/76.31 113571[80:Spt:113569.0,113340.1] || -> node4(s38)*. % 76.04/76.31 113573[80:MRR:804.0,113571.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.31 113576[80:Res:53.1,113573.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.31 113581[81:Spt:113576.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 113583[81:Res:113581.0,61.1] always3(s38) || -> . % 76.04/76.31 113584[81:SSi:113583.0,78236.0,78240.0,108788.0,113339.0,113571.0] || -> . % 76.04/76.31 113585[81:Spt:113584.0,113576.0,113581.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.31 113586[81:Spt:113584.0,113576.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 113590[81:Res:113586.0,61.1] always3(s39) || -> . % 76.04/76.31 113591[81:SSi:113590.0,78241.0,78244.0,108789.0] || -> . % 76.04/76.31 113592[79:Spt:113591.0,113338.0,113339.0] || until2p7(s38)*+ -> . % 76.04/76.31 113593[79:Spt:113591.0,113338.1] || -> node4(s37)*. % 76.04/76.31 113595[79:MRR:807.0,113593.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.31 113598[79:Res:53.1,113595.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.31 113600[80:Spt:113598.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 113602[80:Res:113600.0,61.1] always3(s37) || -> . % 76.04/76.31 113603[80:SSi:113602.0,78232.0,78235.0,108787.0,113337.0,113593.0] || -> . % 76.04/76.31 113604[80:Spt:113603.0,113598.0,113600.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.31 113605[80:Spt:113603.0,113598.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 113609[80:Res:113605.0,61.1] always3(s38) || -> . % 76.04/76.31 113610[80:SSi:113609.0,78236.0,78240.0,108788.0] || -> . % 76.04/76.31 113611[78:Spt:113610.0,113336.0,113337.0] || until2p7(s37)*+ -> . % 76.04/76.31 113612[78:Spt:113610.0,113336.1] || -> node4(s36)*. % 76.04/76.31 113614[78:MRR:810.0,113612.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.31 113617[78:Res:53.1,113614.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.31 113619[79:Spt:113617.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 113621[79:Res:113619.0,61.1] always3(s36) || -> . % 76.04/76.31 113622[79:SSi:113621.0,78227.0,78231.0,108786.0,113335.0,113612.0] || -> . % 76.04/76.31 113623[79:Spt:113622.0,113617.0,113619.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.31 113624[79:Spt:113622.0,113617.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 113628[79:Res:113624.0,61.1] always3(s37) || -> . % 76.04/76.31 113629[79:SSi:113628.0,78232.0,78235.0,108787.0] || -> . % 76.04/76.31 113630[77:Spt:113629.0,113334.0,113335.0] || until2p7(s36)*+ -> . % 76.04/76.31 113631[77:Spt:113629.0,113334.1] || -> node4(s35)*. % 76.04/76.31 113633[77:MRR:813.0,113631.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.31 113636[77:Res:53.1,113633.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.31 113638[78:Spt:113636.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 113640[78:Res:113638.0,61.1] always3(s35) || -> . % 76.04/76.31 113641[78:SSi:113640.0,78223.0,78226.0,108785.0,113333.0,113631.0] || -> . % 76.04/76.31 113642[78:Spt:113641.0,113636.0,113638.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.31 113643[78:Spt:113641.0,113636.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 113647[78:Res:113643.0,61.1] always3(s36) || -> . % 76.04/76.31 113648[78:SSi:113647.0,78227.0,78231.0,108786.0] || -> . % 76.04/76.31 113649[76:Spt:113648.0,113332.0,113333.0] || until2p7(s35)*+ -> . % 76.04/76.31 113650[76:Spt:113648.0,113332.1] || -> node4(s34)*. % 76.04/76.31 113652[76:MRR:816.0,113650.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.31 113655[76:Res:53.1,113652.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.31 113660[77:Spt:113655.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.31 113662[77:Res:113660.0,61.1] always3(s34) || -> . % 76.04/76.31 113663[77:SSi:113662.0,78218.0,78222.0,108784.0,113331.0,113650.0] || -> . % 76.04/76.31 113664[77:Spt:113663.0,113655.0,113660.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.31 113665[77:Spt:113663.0,113655.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 113669[77:Res:113665.0,61.1] always3(s35) || -> . % 76.04/76.31 113670[77:SSi:113669.0,78223.0,78226.0,108785.0] || -> . % 76.04/76.31 113671[75:Spt:113670.0,113330.0,113331.0] || until2p7(s34)*+ -> . % 76.04/76.31 113672[75:Spt:113670.0,113330.1] || -> node4(s33)*. % 76.04/76.31 113674[75:MRR:819.0,113672.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.31 113677[75:Res:53.1,113674.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.31 113679[76:Spt:113677.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.31 113681[76:Res:113679.0,61.1] always3(s33) || -> . % 76.04/76.31 113682[76:SSi:113681.0,78214.0,78217.0,108783.0,113329.0,113672.0] || -> . % 76.04/76.31 113683[76:Spt:113682.0,113677.0,113679.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.31 113684[76:Spt:113682.0,113677.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.31 113688[76:Res:113684.0,61.1] always3(s34) || -> . % 76.04/76.31 113689[76:SSi:113688.0,78218.0,78222.0,108784.0] || -> . % 76.04/76.31 113690[74:Spt:113689.0,113328.0,113329.0] || until2p7(s33)*+ -> . % 76.04/76.31 113691[74:Spt:113689.0,113328.1] || -> node4(s32)*. % 76.04/76.31 113693[74:MRR:822.0,113691.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.31 113696[74:Res:53.1,113693.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.31 113698[75:Spt:113696.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.31 113700[75:Res:113698.0,61.1] always3(s32) || -> . % 76.04/76.31 113701[75:SSi:113700.0,78209.0,78213.0,108782.0,113327.0,113691.0] || -> . % 76.04/76.31 113702[75:Spt:113701.0,113696.0,113698.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.31 113703[75:Spt:113701.0,113696.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.31 113707[75:Res:113703.0,61.1] always3(s33) || -> . % 76.04/76.31 113708[75:SSi:113707.0,78214.0,78217.0,108783.0] || -> . % 76.04/76.31 113709[73:Spt:113708.0,113326.0,113327.0] || until2p7(s32)*+ -> . % 76.04/76.31 113710[73:Spt:113708.0,113326.1] || -> node4(s31)*. % 76.04/76.31 113712[73:MRR:825.0,113710.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.31 113715[73:Res:53.1,113712.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.31 113717[73:MRR:113715.0,113316.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.31 113719[73:Res:113717.0,61.1] always3(s32) || -> . % 76.04/76.31 113720[73:SSi:113719.0,78209.0,78213.0,108782.0] || -> . % 76.04/76.31 113721[71:Spt:113720.0,113240.0,113243.0] || trans(s49,s31)*+ -> . % 76.04/76.31 113722[71:Spt:113720.0,113240.1,113240.2,113240.3,113240.4,113240.5,113240.6,113240.7,113240.8,113240.9,113240.10,113240.11,113240.12,113240.13,113240.14,113240.15,113240.16,113240.17,113240.18,113240.19,113240.20,113240.21,113240.22,113240.23,113240.24,113240.25,113240.26,113240.27,113240.28] || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 113724[71:MRR:113242.1,113721.0] xuntil6(s49) || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 113725[72:Spt:113722.0] || -> trans(s49,s30)*. % 76.04/76.31 113726[72:Res:113725.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s30)*. % 76.04/76.31 113728[72:Res:113725.0,60.0] || -> node2(s49,s30)*. % 76.04/76.31 113729[72:SSi:113726.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s30)*. % 76.04/76.31 113730[72:Res:113728.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)*. % 76.04/76.31 113797[72:SoR:113730.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)*. % 76.04/76.31 113799[72:SoR:113797.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)* xuntil6(s49). % 76.04/76.31 113800[72:SSi:113799.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s30,c_busy)* xuntil6(s49). % 76.04/76.31 113801[73:Spt:113800.1] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.31 113803[73:Res:113801.0,61.1] always3(s30) || -> . % 76.04/76.31 113804[73:SSi:113803.0,78200.0,78204.0,108780.0] || -> . % 76.04/76.31 113805[73:Spt:113804.0,113800.1,113801.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.04/76.31 113806[73:Spt:113804.0,113800.0,113800.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 113810[73:MRR:113797.2,113805.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 113811[73:Res:53.1,113806.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 113813[73:MRR:113811.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 113814[73:MRR:113729.0,113813.0] || -> until2p7(s30)*. % 76.04/76.31 113815[73:MRR:226.0,113814.0] || -> until2p7(s31)* node4(s30). % 76.04/76.31 113816[74:Spt:113815.0] || -> until2p7(s31)*. % 76.04/76.31 113817[74:MRR:227.0,113816.0] || -> until2p7(s32)* node4(s31). % 76.04/76.31 113818[75:Spt:113817.0] || -> until2p7(s32)*. % 76.04/76.31 113819[75:MRR:228.0,113818.0] || -> until2p7(s33)* node4(s32). % 76.04/76.31 113820[76:Spt:113819.0] || -> until2p7(s33)*. % 76.04/76.31 113821[76:MRR:229.0,113820.0] || -> until2p7(s34)* node4(s33). % 76.04/76.31 113822[77:Spt:113821.0] || -> until2p7(s34)*. % 76.04/76.31 113823[77:MRR:230.0,113822.0] || -> until2p7(s35)* node4(s34). % 76.04/76.31 113824[78:Spt:113823.0] || -> until2p7(s35)*. % 76.04/76.31 113825[78:MRR:231.0,113824.0] || -> until2p7(s36)* node4(s35). % 76.04/76.31 113826[79:Spt:113825.0] || -> until2p7(s36)*. % 76.04/76.31 113827[79:MRR:232.0,113826.0] || -> until2p7(s37)* node4(s36). % 76.04/76.31 113828[80:Spt:113827.0] || -> until2p7(s37)*. % 76.04/76.31 113829[80:MRR:235.0,113828.0] || -> until2p7(s38)* node4(s37). % 76.04/76.31 113830[81:Spt:113829.0] || -> until2p7(s38)*. % 76.04/76.31 113831[81:MRR:236.0,113830.0] || -> until2p7(s39)* node4(s38). % 76.04/76.31 113832[82:Spt:113831.0] || -> until2p7(s39)*. % 76.04/76.31 113833[82:MRR:237.0,113832.0] || -> until2p7(s40)* node4(s39). % 76.04/76.31 113834[83:Spt:113833.0] || -> until2p7(s40)*. % 76.04/76.31 113835[83:MRR:238.0,113834.0] || -> until2p7(s41)* node4(s40). % 76.04/76.31 113836[84:Spt:113835.0] || -> until2p7(s41)*. % 76.04/76.31 113837[84:MRR:239.0,113836.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 113838[85:Spt:113837.0] || -> until2p7(s42)*. % 76.04/76.31 113839[85:MRR:240.0,113838.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 113840[86:Spt:113839.0] || -> until2p7(s43)*. % 76.04/76.31 113841[86:MRR:241.0,113840.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 113842[87:Spt:113841.0] || -> until2p7(s44)*. % 76.04/76.31 113843[87:MRR:539.0,113842.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 113844[88:Spt:113843.0] || -> until2p7(s45)*. % 76.04/76.31 113845[88:MRR:544.0,113844.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 113846[89:Spt:113845.0] || -> until2p7(s46)*. % 76.04/76.31 113847[89:MRR:549.0,113846.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 113848[90:Spt:113847.0] || -> until2p7(s47)*. % 76.04/76.31 113849[90:MRR:554.0,113848.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 113850[91:Spt:113849.0] || -> until2p7(s48)*. % 76.04/76.31 113851[91:MRR:559.0,113850.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 113852[92:Spt:113851.0] || -> until2p7(s49)*. % 76.04/76.31 113853[92:MRR:194.0,113852.0] || -> node4(s49)*. % 76.04/76.31 113854[92:MRR:113810.0,113853.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 113855[92:Res:53.1,113854.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 113857[92:MRR:113855.0,78381.0] || -> . % 76.04/76.31 113858[92:Spt:113857.0,113851.0,113852.0] || until2p7(s49)*+ -> . % 76.04/76.31 113859[92:Spt:113857.0,113851.1] || -> node4(s48)*. % 76.04/76.31 113860[92:MRR:78384.0,113859.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 113863[92:Res:53.1,113860.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 113866[92:Res:113863.0,61.1] always3(s48) || -> . % 76.04/76.31 113867[92:SSi:113866.0,78281.0,78387.0,108798.0,113850.0,113859.0] || -> . % 76.04/76.31 113868[91:Spt:113867.0,113849.0,113850.0] || until2p7(s48)*+ -> . % 76.04/76.31 113869[91:Spt:113867.0,113849.1] || -> node4(s47)*. % 76.04/76.31 113871[91:MRR:777.0,113869.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 113886[91:Res:53.1,113871.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 113888[92:Spt:113886.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 113890[92:Res:113888.0,61.1] always3(s47) || -> . % 76.04/76.31 113891[92:SSi:113890.0,78277.0,78280.0,108797.0,113848.0,113869.0] || -> . % 76.04/76.31 113892[92:Spt:113891.0,113886.0,113888.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 113893[92:Spt:113891.0,113886.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 113897[92:Res:113893.0,61.1] always3(s48) || -> . % 76.04/76.31 113898[92:SSi:113897.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 113899[90:Spt:113898.0,113847.0,113848.0] || until2p7(s47)*+ -> . % 76.04/76.31 113900[90:Spt:113898.0,113847.1] || -> node4(s46)*. % 76.04/76.31 113902[90:MRR:780.0,113900.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 113912[90:Res:53.1,113902.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 113914[91:Spt:113912.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 113916[91:Res:113914.0,61.1] always3(s46) || -> . % 76.04/76.31 113917[91:SSi:113916.0,78272.0,78276.0,108796.0,113846.0,113900.0] || -> . % 76.04/76.31 113918[91:Spt:113917.0,113912.0,113914.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 113919[91:Spt:113917.0,113912.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 113923[91:Res:113919.0,61.1] always3(s47) || -> . % 76.04/76.31 113924[91:SSi:113923.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 113925[89:Spt:113924.0,113845.0,113846.0] || until2p7(s46)*+ -> . % 76.04/76.31 113926[89:Spt:113924.0,113845.1] || -> node4(s45)*. % 76.04/76.31 113928[89:MRR:783.0,113926.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 113931[89:Res:53.1,113928.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 113933[90:Spt:113931.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 113935[90:Res:113933.0,61.1] always3(s45) || -> . % 76.04/76.31 113936[90:SSi:113935.0,78268.0,78271.0,108795.0,113844.0,113926.0] || -> . % 76.04/76.31 113937[90:Spt:113936.0,113931.0,113933.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 113938[90:Spt:113936.0,113931.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 113942[90:Res:113938.0,61.1] always3(s46) || -> . % 76.04/76.31 113943[90:SSi:113942.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 113944[88:Spt:113943.0,113843.0,113844.0] || until2p7(s45)*+ -> . % 76.04/76.31 113945[88:Spt:113943.0,113843.1] || -> node4(s44)*. % 76.04/76.31 113947[88:MRR:786.0,113945.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 113950[88:Res:53.1,113947.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 113952[89:Spt:113950.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 113954[89:Res:113952.0,61.1] always3(s44) || -> . % 76.04/76.31 113955[89:SSi:113954.0,78263.0,78267.0,108794.0,113842.0,113945.0] || -> . % 76.04/76.31 113956[89:Spt:113955.0,113950.0,113952.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 113957[89:Spt:113955.0,113950.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 113961[89:Res:113957.0,61.1] always3(s45) || -> . % 76.04/76.31 113962[89:SSi:113961.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 113963[87:Spt:113962.0,113841.0,113842.0] || until2p7(s44)*+ -> . % 76.04/76.31 113964[87:Spt:113962.0,113841.1] || -> node4(s43)*. % 76.04/76.31 113966[87:MRR:789.0,113964.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 113969[87:Res:53.1,113966.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 113974[88:Spt:113969.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 113976[88:Res:113974.0,61.1] always3(s43) || -> . % 76.04/76.31 113977[88:SSi:113976.0,78259.0,78262.0,108793.0,113840.0,113964.0] || -> . % 76.04/76.31 113978[88:Spt:113977.0,113969.0,113974.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 113979[88:Spt:113977.0,113969.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 113983[88:Res:113979.0,61.1] always3(s44) || -> . % 76.04/76.31 113984[88:SSi:113983.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 113985[86:Spt:113984.0,113839.0,113840.0] || until2p7(s43)*+ -> . % 76.04/76.31 113986[86:Spt:113984.0,113839.1] || -> node4(s42)*. % 76.04/76.31 113988[86:MRR:792.0,113986.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 113991[86:Res:53.1,113988.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 113993[87:Spt:113991.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 113995[87:Res:113993.0,61.1] always3(s42) || -> . % 76.04/76.31 113996[87:SSi:113995.0,78254.0,78258.0,108792.0,113838.0,113986.0] || -> . % 76.04/76.31 113997[87:Spt:113996.0,113991.0,113993.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 113998[87:Spt:113996.0,113991.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 114002[87:Res:113998.0,61.1] always3(s43) || -> . % 76.04/76.31 114003[87:SSi:114002.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 114004[85:Spt:114003.0,113837.0,113838.0] || until2p7(s42)*+ -> . % 76.04/76.31 114005[85:Spt:114003.0,113837.1] || -> node4(s41)*. % 76.04/76.31 114007[85:MRR:795.0,114005.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 114010[85:Res:53.1,114007.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 114012[86:Spt:114010.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 114014[86:Res:114012.0,61.1] always3(s41) || -> . % 76.04/76.31 114015[86:SSi:114014.0,78250.0,78253.0,108791.0,113836.0,114005.0] || -> . % 76.04/76.31 114016[86:Spt:114015.0,114010.0,114012.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.31 114017[86:Spt:114015.0,114010.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 114021[86:Res:114017.0,61.1] always3(s42) || -> . % 76.04/76.31 114022[86:SSi:114021.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 114023[84:Spt:114022.0,113835.0,113836.0] || until2p7(s41)*+ -> . % 76.04/76.31 114024[84:Spt:114022.0,113835.1] || -> node4(s40)*. % 76.04/76.31 114026[84:MRR:798.0,114024.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.31 114029[84:Res:53.1,114026.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.31 114031[85:Spt:114029.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 114033[85:Res:114031.0,61.1] always3(s40) || -> . % 76.04/76.31 114034[85:SSi:114033.0,78245.0,78249.0,108790.0,113834.0,114024.0] || -> . % 76.04/76.31 114035[85:Spt:114034.0,114029.0,114031.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.31 114036[85:Spt:114034.0,114029.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 114040[85:Res:114036.0,61.1] always3(s41) || -> . % 76.04/76.31 114041[85:SSi:114040.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 114042[83:Spt:114041.0,113833.0,113834.0] || until2p7(s40)*+ -> . % 76.04/76.31 114043[83:Spt:114041.0,113833.1] || -> node4(s39)*. % 76.04/76.31 114045[83:MRR:801.0,114043.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.31 114048[83:Res:53.1,114045.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.31 114053[84:Spt:114048.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 114055[84:Res:114053.0,61.1] always3(s39) || -> . % 76.04/76.31 114056[84:SSi:114055.0,78241.0,78244.0,108789.0,113832.0,114043.0] || -> . % 76.04/76.31 114057[84:Spt:114056.0,114048.0,114053.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.31 114058[84:Spt:114056.0,114048.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 114062[84:Res:114058.0,61.1] always3(s40) || -> . % 76.04/76.31 114063[84:SSi:114062.0,78245.0,78249.0,108790.0] || -> . % 76.04/76.31 114064[82:Spt:114063.0,113831.0,113832.0] || until2p7(s39)*+ -> . % 76.04/76.31 114065[82:Spt:114063.0,113831.1] || -> node4(s38)*. % 76.04/76.31 114067[82:MRR:804.0,114065.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.31 114070[82:Res:53.1,114067.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.31 114072[83:Spt:114070.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 114074[83:Res:114072.0,61.1] always3(s38) || -> . % 76.04/76.31 114075[83:SSi:114074.0,78236.0,78240.0,108788.0,113830.0,114065.0] || -> . % 76.04/76.31 114076[83:Spt:114075.0,114070.0,114072.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.31 114077[83:Spt:114075.0,114070.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 114081[83:Res:114077.0,61.1] always3(s39) || -> . % 76.04/76.31 114082[83:SSi:114081.0,78241.0,78244.0,108789.0] || -> . % 76.04/76.31 114083[81:Spt:114082.0,113829.0,113830.0] || until2p7(s38)*+ -> . % 76.04/76.31 114084[81:Spt:114082.0,113829.1] || -> node4(s37)*. % 76.04/76.31 114086[81:MRR:807.0,114084.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.31 114089[81:Res:53.1,114086.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.31 114091[82:Spt:114089.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 114093[82:Res:114091.0,61.1] always3(s37) || -> . % 76.04/76.31 114094[82:SSi:114093.0,78232.0,78235.0,108787.0,113828.0,114084.0] || -> . % 76.04/76.31 114095[82:Spt:114094.0,114089.0,114091.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.31 114096[82:Spt:114094.0,114089.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 114100[82:Res:114096.0,61.1] always3(s38) || -> . % 76.04/76.31 114101[82:SSi:114100.0,78236.0,78240.0,108788.0] || -> . % 76.04/76.31 114102[80:Spt:114101.0,113827.0,113828.0] || until2p7(s37)*+ -> . % 76.04/76.31 114103[80:Spt:114101.0,113827.1] || -> node4(s36)*. % 76.04/76.31 114105[80:MRR:810.0,114103.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.31 114108[80:Res:53.1,114105.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.31 114110[81:Spt:114108.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 114112[81:Res:114110.0,61.1] always3(s36) || -> . % 76.04/76.31 114113[81:SSi:114112.0,78227.0,78231.0,108786.0,113826.0,114103.0] || -> . % 76.04/76.31 114114[81:Spt:114113.0,114108.0,114110.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.31 114115[81:Spt:114113.0,114108.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 114119[81:Res:114115.0,61.1] always3(s37) || -> . % 76.04/76.31 114120[81:SSi:114119.0,78232.0,78235.0,108787.0] || -> . % 76.04/76.31 114121[79:Spt:114120.0,113825.0,113826.0] || until2p7(s36)*+ -> . % 76.04/76.31 114122[79:Spt:114120.0,113825.1] || -> node4(s35)*. % 76.04/76.31 114124[79:MRR:813.0,114122.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.31 114127[79:Res:53.1,114124.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.31 114132[80:Spt:114127.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 114134[80:Res:114132.0,61.1] always3(s35) || -> . % 76.04/76.31 114135[80:SSi:114134.0,78223.0,78226.0,108785.0,113824.0,114122.0] || -> . % 76.04/76.31 114136[80:Spt:114135.0,114127.0,114132.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.31 114137[80:Spt:114135.0,114127.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 114141[80:Res:114137.0,61.1] always3(s36) || -> . % 76.04/76.31 114142[80:SSi:114141.0,78227.0,78231.0,108786.0] || -> . % 76.04/76.31 114143[78:Spt:114142.0,113823.0,113824.0] || until2p7(s35)*+ -> . % 76.04/76.31 114144[78:Spt:114142.0,113823.1] || -> node4(s34)*. % 76.04/76.31 114146[78:MRR:816.0,114144.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.31 114149[78:Res:53.1,114146.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.31 114151[79:Spt:114149.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.31 114153[79:Res:114151.0,61.1] always3(s34) || -> . % 76.04/76.31 114154[79:SSi:114153.0,78218.0,78222.0,108784.0,113822.0,114144.0] || -> . % 76.04/76.31 114155[79:Spt:114154.0,114149.0,114151.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.31 114156[79:Spt:114154.0,114149.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 114160[79:Res:114156.0,61.1] always3(s35) || -> . % 76.04/76.31 114161[79:SSi:114160.0,78223.0,78226.0,108785.0] || -> . % 76.04/76.31 114162[77:Spt:114161.0,113821.0,113822.0] || until2p7(s34)*+ -> . % 76.04/76.31 114163[77:Spt:114161.0,113821.1] || -> node4(s33)*. % 76.04/76.31 114165[77:MRR:819.0,114163.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.31 114168[77:Res:53.1,114165.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.31 114170[78:Spt:114168.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.31 114172[78:Res:114170.0,61.1] always3(s33) || -> . % 76.04/76.31 114173[78:SSi:114172.0,78214.0,78217.0,108783.0,113820.0,114163.0] || -> . % 76.04/76.31 114174[78:Spt:114173.0,114168.0,114170.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.31 114175[78:Spt:114173.0,114168.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.31 114179[78:Res:114175.0,61.1] always3(s34) || -> . % 76.04/76.31 114180[78:SSi:114179.0,78218.0,78222.0,108784.0] || -> . % 76.04/76.31 114181[76:Spt:114180.0,113819.0,113820.0] || until2p7(s33)*+ -> . % 76.04/76.31 114182[76:Spt:114180.0,113819.1] || -> node4(s32)*. % 76.04/76.31 114184[76:MRR:822.0,114182.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.31 114187[76:Res:53.1,114184.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.31 114189[77:Spt:114187.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.31 114191[77:Res:114189.0,61.1] always3(s32) || -> . % 76.04/76.31 114192[77:SSi:114191.0,78209.0,78213.0,108782.0,113818.0,114182.0] || -> . % 76.04/76.31 114193[77:Spt:114192.0,114187.0,114189.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.31 114194[77:Spt:114192.0,114187.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.31 114198[77:Res:114194.0,61.1] always3(s33) || -> . % 76.04/76.31 114199[77:SSi:114198.0,78214.0,78217.0,108783.0] || -> . % 76.04/76.31 114200[75:Spt:114199.0,113817.0,113818.0] || until2p7(s32)*+ -> . % 76.04/76.31 114201[75:Spt:114199.0,113817.1] || -> node4(s31)*. % 76.04/76.31 114203[75:MRR:825.0,114201.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.31 114206[75:Res:53.1,114203.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.31 114211[76:Spt:114206.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.31 114213[76:Res:114211.0,61.1] always3(s31) || -> . % 76.04/76.31 114214[76:SSi:114213.0,78205.0,78208.0,108781.0,113816.0,114201.0] || -> . % 76.04/76.31 114215[76:Spt:114214.0,114206.0,114211.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.31 114216[76:Spt:114214.0,114206.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.31 114220[76:Res:114216.0,61.1] always3(s32) || -> . % 76.04/76.31 114221[76:SSi:114220.0,78209.0,78213.0,108782.0] || -> . % 76.04/76.31 114222[74:Spt:114221.0,113815.0,113816.0] || until2p7(s31)*+ -> . % 76.04/76.31 114223[74:Spt:114221.0,113815.1] || -> node4(s30)*. % 76.04/76.31 114225[74:MRR:828.0,114223.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.31 114228[74:Res:53.1,114225.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.31 114230[74:MRR:114228.0,113805.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.31 114232[74:Res:114230.0,61.1] always3(s31) || -> . % 76.04/76.31 114233[74:SSi:114232.0,78205.0,78208.0,108781.0] || -> . % 76.04/76.31 114234[72:Spt:114233.0,113722.0,113725.0] || trans(s49,s30)*+ -> . % 76.04/76.31 114235[72:Spt:114233.0,113722.1,113722.2,113722.3,113722.4,113722.5,113722.6,113722.7,113722.8,113722.9,113722.10,113722.11,113722.12,113722.13,113722.14,113722.15,113722.16,113722.17,113722.18,113722.19,113722.20,113722.21,113722.22,113722.23,113722.24,113722.25,113722.26,113722.27] || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 114237[72:MRR:113724.1,114234.0] xuntil6(s49) || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 114238[73:Spt:114235.0] || -> trans(s49,s29)*. % 76.04/76.31 114239[73:Res:114238.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s29)*. % 76.04/76.31 114241[73:Res:114238.0,60.0] || -> node2(s49,s29)*. % 76.04/76.31 114242[73:SSi:114239.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s29)*. % 76.04/76.31 114243[73:Res:114241.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.04/76.31 114311[73:SoR:114243.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.04/76.31 114313[73:SoR:114311.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.04/76.31 114314[73:SSi:114313.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.04/76.31 114315[74:Spt:114314.1] || -> m_main_v_state(s29,c_busy)*. % 76.04/76.31 114317[74:Res:114315.0,61.1] always3(s29) || -> . % 76.04/76.31 114318[74:SSi:114317.0,78196.0,78199.0,108779.0] || -> . % 76.04/76.31 114319[74:Spt:114318.0,114314.1,114315.0] || m_main_v_state(s29,c_busy)*+ -> . % 76.04/76.31 114320[74:Spt:114318.0,114314.0,114314.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 114324[74:MRR:114311.2,114319.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 114325[74:Res:53.1,114320.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 114327[74:MRR:114325.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 114328[74:MRR:114242.0,114327.0] || -> until2p7(s29)*. % 76.04/76.31 114329[74:MRR:225.0,114328.0] || -> until2p7(s30)* node4(s29). % 76.04/76.31 114330[75:Spt:114329.0] || -> until2p7(s30)*. % 76.04/76.31 114331[75:MRR:226.0,114330.0] || -> until2p7(s31)* node4(s30). % 76.04/76.31 114332[76:Spt:114331.0] || -> until2p7(s31)*. % 76.04/76.31 114333[76:MRR:227.0,114332.0] || -> until2p7(s32)* node4(s31). % 76.04/76.31 114334[77:Spt:114333.0] || -> until2p7(s32)*. % 76.04/76.31 114335[77:MRR:228.0,114334.0] || -> until2p7(s33)* node4(s32). % 76.04/76.31 114336[78:Spt:114335.0] || -> until2p7(s33)*. % 76.04/76.31 114337[78:MRR:229.0,114336.0] || -> until2p7(s34)* node4(s33). % 76.04/76.31 114338[79:Spt:114337.0] || -> until2p7(s34)*. % 76.04/76.31 114339[79:MRR:230.0,114338.0] || -> until2p7(s35)* node4(s34). % 76.04/76.31 114340[80:Spt:114339.0] || -> until2p7(s35)*. % 76.04/76.31 114341[80:MRR:231.0,114340.0] || -> until2p7(s36)* node4(s35). % 76.04/76.31 114342[81:Spt:114341.0] || -> until2p7(s36)*. % 76.04/76.31 114343[81:MRR:232.0,114342.0] || -> until2p7(s37)* node4(s36). % 76.04/76.31 114344[82:Spt:114343.0] || -> until2p7(s37)*. % 76.04/76.31 114345[82:MRR:235.0,114344.0] || -> until2p7(s38)* node4(s37). % 76.04/76.31 114346[83:Spt:114345.0] || -> until2p7(s38)*. % 76.04/76.31 114347[83:MRR:236.0,114346.0] || -> until2p7(s39)* node4(s38). % 76.04/76.31 114348[84:Spt:114347.0] || -> until2p7(s39)*. % 76.04/76.31 114349[84:MRR:237.0,114348.0] || -> until2p7(s40)* node4(s39). % 76.04/76.31 114350[85:Spt:114349.0] || -> until2p7(s40)*. % 76.04/76.31 114351[85:MRR:238.0,114350.0] || -> until2p7(s41)* node4(s40). % 76.04/76.31 114352[86:Spt:114351.0] || -> until2p7(s41)*. % 76.04/76.31 114353[86:MRR:239.0,114352.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 114354[87:Spt:114353.0] || -> until2p7(s42)*. % 76.04/76.31 114355[87:MRR:240.0,114354.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 114356[88:Spt:114355.0] || -> until2p7(s43)*. % 76.04/76.31 114357[88:MRR:241.0,114356.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 114358[89:Spt:114357.0] || -> until2p7(s44)*. % 76.04/76.31 114359[89:MRR:539.0,114358.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 114360[90:Spt:114359.0] || -> until2p7(s45)*. % 76.04/76.31 114361[90:MRR:544.0,114360.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 114362[91:Spt:114361.0] || -> until2p7(s46)*. % 76.04/76.31 114363[91:MRR:549.0,114362.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 114364[92:Spt:114363.0] || -> until2p7(s47)*. % 76.04/76.31 114365[92:MRR:554.0,114364.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 114366[93:Spt:114365.0] || -> until2p7(s48)*. % 76.04/76.31 114367[93:MRR:559.0,114366.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 114368[94:Spt:114367.0] || -> until2p7(s49)*. % 76.04/76.31 114369[94:MRR:194.0,114368.0] || -> node4(s49)*. % 76.04/76.31 114370[94:MRR:114324.0,114369.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 114371[94:Res:53.1,114370.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 114373[94:MRR:114371.0,78381.0] || -> . % 76.04/76.31 114374[94:Spt:114373.0,114367.0,114368.0] || until2p7(s49)*+ -> . % 76.04/76.31 114375[94:Spt:114373.0,114367.1] || -> node4(s48)*. % 76.04/76.31 114376[94:MRR:78384.0,114375.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 114379[94:Res:53.1,114376.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 114382[94:Res:114379.0,61.1] always3(s48) || -> . % 76.04/76.31 114383[94:SSi:114382.0,78281.0,78387.0,108798.0,114366.0,114375.0] || -> . % 76.04/76.31 114384[93:Spt:114383.0,114365.0,114366.0] || until2p7(s48)*+ -> . % 76.04/76.31 114385[93:Spt:114383.0,114365.1] || -> node4(s47)*. % 76.04/76.31 114387[93:MRR:777.0,114385.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 114402[93:Res:53.1,114387.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 114404[94:Spt:114402.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 114406[94:Res:114404.0,61.1] always3(s47) || -> . % 76.04/76.31 114407[94:SSi:114406.0,78277.0,78280.0,108797.0,114364.0,114385.0] || -> . % 76.04/76.31 114408[94:Spt:114407.0,114402.0,114404.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 114409[94:Spt:114407.0,114402.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 114413[94:Res:114409.0,61.1] always3(s48) || -> . % 76.04/76.31 114414[94:SSi:114413.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 114415[92:Spt:114414.0,114363.0,114364.0] || until2p7(s47)*+ -> . % 76.04/76.31 114416[92:Spt:114414.0,114363.1] || -> node4(s46)*. % 76.04/76.31 114418[92:MRR:780.0,114416.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 114428[92:Res:53.1,114418.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 114430[93:Spt:114428.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 114432[93:Res:114430.0,61.1] always3(s46) || -> . % 76.04/76.31 114433[93:SSi:114432.0,78272.0,78276.0,108796.0,114362.0,114416.0] || -> . % 76.04/76.31 114434[93:Spt:114433.0,114428.0,114430.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 114435[93:Spt:114433.0,114428.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 114439[93:Res:114435.0,61.1] always3(s47) || -> . % 76.04/76.31 114440[93:SSi:114439.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 114441[91:Spt:114440.0,114361.0,114362.0] || until2p7(s46)*+ -> . % 76.04/76.31 114442[91:Spt:114440.0,114361.1] || -> node4(s45)*. % 76.04/76.31 114444[91:MRR:783.0,114442.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 114447[91:Res:53.1,114444.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 114449[92:Spt:114447.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 114451[92:Res:114449.0,61.1] always3(s45) || -> . % 76.04/76.31 114452[92:SSi:114451.0,78268.0,78271.0,108795.0,114360.0,114442.0] || -> . % 76.04/76.31 114453[92:Spt:114452.0,114447.0,114449.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 114454[92:Spt:114452.0,114447.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 114458[92:Res:114454.0,61.1] always3(s46) || -> . % 76.04/76.31 114459[92:SSi:114458.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 114460[90:Spt:114459.0,114359.0,114360.0] || until2p7(s45)*+ -> . % 76.04/76.31 114461[90:Spt:114459.0,114359.1] || -> node4(s44)*. % 76.04/76.31 114463[90:MRR:786.0,114461.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 114466[90:Res:53.1,114463.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 114468[91:Spt:114466.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 114470[91:Res:114468.0,61.1] always3(s44) || -> . % 76.04/76.31 114471[91:SSi:114470.0,78263.0,78267.0,108794.0,114358.0,114461.0] || -> . % 76.04/76.31 114472[91:Spt:114471.0,114466.0,114468.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 114473[91:Spt:114471.0,114466.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 114477[91:Res:114473.0,61.1] always3(s45) || -> . % 76.04/76.31 114478[91:SSi:114477.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 114479[89:Spt:114478.0,114357.0,114358.0] || until2p7(s44)*+ -> . % 76.04/76.31 114480[89:Spt:114478.0,114357.1] || -> node4(s43)*. % 76.04/76.31 114482[89:MRR:789.0,114480.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 114485[89:Res:53.1,114482.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 114490[90:Spt:114485.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 114492[90:Res:114490.0,61.1] always3(s43) || -> . % 76.04/76.31 114493[90:SSi:114492.0,78259.0,78262.0,108793.0,114356.0,114480.0] || -> . % 76.04/76.31 114494[90:Spt:114493.0,114485.0,114490.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 114495[90:Spt:114493.0,114485.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 114499[90:Res:114495.0,61.1] always3(s44) || -> . % 76.04/76.31 114500[90:SSi:114499.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 114501[88:Spt:114500.0,114355.0,114356.0] || until2p7(s43)*+ -> . % 76.04/76.31 114502[88:Spt:114500.0,114355.1] || -> node4(s42)*. % 76.04/76.31 114504[88:MRR:792.0,114502.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 114507[88:Res:53.1,114504.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 114509[89:Spt:114507.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 114511[89:Res:114509.0,61.1] always3(s42) || -> . % 76.04/76.31 114512[89:SSi:114511.0,78254.0,78258.0,108792.0,114354.0,114502.0] || -> . % 76.04/76.31 114513[89:Spt:114512.0,114507.0,114509.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 114514[89:Spt:114512.0,114507.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 114518[89:Res:114514.0,61.1] always3(s43) || -> . % 76.04/76.31 114519[89:SSi:114518.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 114520[87:Spt:114519.0,114353.0,114354.0] || until2p7(s42)*+ -> . % 76.04/76.31 114521[87:Spt:114519.0,114353.1] || -> node4(s41)*. % 76.04/76.31 114523[87:MRR:795.0,114521.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 114526[87:Res:53.1,114523.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 114528[88:Spt:114526.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 114530[88:Res:114528.0,61.1] always3(s41) || -> . % 76.04/76.31 114531[88:SSi:114530.0,78250.0,78253.0,108791.0,114352.0,114521.0] || -> . % 76.04/76.31 114532[88:Spt:114531.0,114526.0,114528.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.31 114533[88:Spt:114531.0,114526.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 114537[88:Res:114533.0,61.1] always3(s42) || -> . % 76.04/76.31 114538[88:SSi:114537.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 114539[86:Spt:114538.0,114351.0,114352.0] || until2p7(s41)*+ -> . % 76.04/76.31 114540[86:Spt:114538.0,114351.1] || -> node4(s40)*. % 76.04/76.31 114542[86:MRR:798.0,114540.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.31 114545[86:Res:53.1,114542.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.31 114547[87:Spt:114545.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 114549[87:Res:114547.0,61.1] always3(s40) || -> . % 76.04/76.31 114550[87:SSi:114549.0,78245.0,78249.0,108790.0,114350.0,114540.0] || -> . % 76.04/76.31 114551[87:Spt:114550.0,114545.0,114547.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.31 114552[87:Spt:114550.0,114545.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 114556[87:Res:114552.0,61.1] always3(s41) || -> . % 76.04/76.31 114557[87:SSi:114556.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 114558[85:Spt:114557.0,114349.0,114350.0] || until2p7(s40)*+ -> . % 76.04/76.31 114559[85:Spt:114557.0,114349.1] || -> node4(s39)*. % 76.04/76.31 114561[85:MRR:801.0,114559.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.31 114564[85:Res:53.1,114561.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.31 114569[86:Spt:114564.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 114571[86:Res:114569.0,61.1] always3(s39) || -> . % 76.04/76.31 114572[86:SSi:114571.0,78241.0,78244.0,108789.0,114348.0,114559.0] || -> . % 76.04/76.31 114573[86:Spt:114572.0,114564.0,114569.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.31 114574[86:Spt:114572.0,114564.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 114578[86:Res:114574.0,61.1] always3(s40) || -> . % 76.04/76.31 114579[86:SSi:114578.0,78245.0,78249.0,108790.0] || -> . % 76.04/76.31 114580[84:Spt:114579.0,114347.0,114348.0] || until2p7(s39)*+ -> . % 76.04/76.31 114581[84:Spt:114579.0,114347.1] || -> node4(s38)*. % 76.04/76.31 114583[84:MRR:804.0,114581.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.31 114586[84:Res:53.1,114583.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.31 114588[85:Spt:114586.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 114590[85:Res:114588.0,61.1] always3(s38) || -> . % 76.04/76.31 114591[85:SSi:114590.0,78236.0,78240.0,108788.0,114346.0,114581.0] || -> . % 76.04/76.31 114592[85:Spt:114591.0,114586.0,114588.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.31 114593[85:Spt:114591.0,114586.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 114597[85:Res:114593.0,61.1] always3(s39) || -> . % 76.04/76.31 114598[85:SSi:114597.0,78241.0,78244.0,108789.0] || -> . % 76.04/76.31 114599[83:Spt:114598.0,114345.0,114346.0] || until2p7(s38)*+ -> . % 76.04/76.31 114600[83:Spt:114598.0,114345.1] || -> node4(s37)*. % 76.04/76.31 114602[83:MRR:807.0,114600.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.31 114605[83:Res:53.1,114602.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.31 114607[84:Spt:114605.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 114609[84:Res:114607.0,61.1] always3(s37) || -> . % 76.04/76.31 114610[84:SSi:114609.0,78232.0,78235.0,108787.0,114344.0,114600.0] || -> . % 76.04/76.31 114611[84:Spt:114610.0,114605.0,114607.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.31 114612[84:Spt:114610.0,114605.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 114616[84:Res:114612.0,61.1] always3(s38) || -> . % 76.04/76.31 114617[84:SSi:114616.0,78236.0,78240.0,108788.0] || -> . % 76.04/76.31 114618[82:Spt:114617.0,114343.0,114344.0] || until2p7(s37)*+ -> . % 76.04/76.31 114619[82:Spt:114617.0,114343.1] || -> node4(s36)*. % 76.04/76.31 114621[82:MRR:810.0,114619.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.31 114624[82:Res:53.1,114621.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.31 114626[83:Spt:114624.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 114628[83:Res:114626.0,61.1] always3(s36) || -> . % 76.04/76.31 114629[83:SSi:114628.0,78227.0,78231.0,108786.0,114342.0,114619.0] || -> . % 76.04/76.31 114630[83:Spt:114629.0,114624.0,114626.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.31 114631[83:Spt:114629.0,114624.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 114635[83:Res:114631.0,61.1] always3(s37) || -> . % 76.04/76.31 114636[83:SSi:114635.0,78232.0,78235.0,108787.0] || -> . % 76.04/76.31 114637[81:Spt:114636.0,114341.0,114342.0] || until2p7(s36)*+ -> . % 76.04/76.31 114638[81:Spt:114636.0,114341.1] || -> node4(s35)*. % 76.04/76.31 114640[81:MRR:813.0,114638.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.04/76.31 114643[81:Res:53.1,114640.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.04/76.31 114648[82:Spt:114643.0] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 114650[82:Res:114648.0,61.1] always3(s35) || -> . % 76.04/76.31 114651[82:SSi:114650.0,78223.0,78226.0,108785.0,114340.0,114638.0] || -> . % 76.04/76.31 114652[82:Spt:114651.0,114643.0,114648.0] || m_main_v_state(s35,c_busy)* -> . % 76.04/76.31 114653[82:Spt:114651.0,114643.1] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 114657[82:Res:114653.0,61.1] always3(s36) || -> . % 76.04/76.31 114658[82:SSi:114657.0,78227.0,78231.0,108786.0] || -> . % 76.04/76.31 114659[80:Spt:114658.0,114339.0,114340.0] || until2p7(s35)*+ -> . % 76.04/76.31 114660[80:Spt:114658.0,114339.1] || -> node4(s34)*. % 76.04/76.31 114662[80:MRR:816.0,114660.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.04/76.31 114665[80:Res:53.1,114662.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.04/76.31 114667[81:Spt:114665.0] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.31 114669[81:Res:114667.0,61.1] always3(s34) || -> . % 76.04/76.31 114670[81:SSi:114669.0,78218.0,78222.0,108784.0,114338.0,114660.0] || -> . % 76.04/76.31 114671[81:Spt:114670.0,114665.0,114667.0] || m_main_v_state(s34,c_busy)* -> . % 76.04/76.31 114672[81:Spt:114670.0,114665.1] || -> m_main_v_state(s35,c_busy)*. % 76.04/76.31 114676[81:Res:114672.0,61.1] always3(s35) || -> . % 76.04/76.31 114677[81:SSi:114676.0,78223.0,78226.0,108785.0] || -> . % 76.04/76.31 114678[79:Spt:114677.0,114337.0,114338.0] || until2p7(s34)*+ -> . % 76.04/76.31 114679[79:Spt:114677.0,114337.1] || -> node4(s33)*. % 76.04/76.31 114681[79:MRR:819.0,114679.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.04/76.31 114684[79:Res:53.1,114681.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.04/76.31 114686[80:Spt:114684.0] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.31 114688[80:Res:114686.0,61.1] always3(s33) || -> . % 76.04/76.31 114689[80:SSi:114688.0,78214.0,78217.0,108783.0,114336.0,114679.0] || -> . % 76.04/76.31 114690[80:Spt:114689.0,114684.0,114686.0] || m_main_v_state(s33,c_busy)* -> . % 76.04/76.31 114691[80:Spt:114689.0,114684.1] || -> m_main_v_state(s34,c_busy)*. % 76.04/76.31 114695[80:Res:114691.0,61.1] always3(s34) || -> . % 76.04/76.31 114696[80:SSi:114695.0,78218.0,78222.0,108784.0] || -> . % 76.04/76.31 114697[78:Spt:114696.0,114335.0,114336.0] || until2p7(s33)*+ -> . % 76.04/76.31 114698[78:Spt:114696.0,114335.1] || -> node4(s32)*. % 76.04/76.31 114700[78:MRR:822.0,114698.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.04/76.31 114703[78:Res:53.1,114700.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.04/76.31 114705[79:Spt:114703.0] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.31 114707[79:Res:114705.0,61.1] always3(s32) || -> . % 76.04/76.31 114708[79:SSi:114707.0,78209.0,78213.0,108782.0,114334.0,114698.0] || -> . % 76.04/76.31 114709[79:Spt:114708.0,114703.0,114705.0] || m_main_v_state(s32,c_busy)* -> . % 76.04/76.31 114710[79:Spt:114708.0,114703.1] || -> m_main_v_state(s33,c_busy)*. % 76.04/76.31 114714[79:Res:114710.0,61.1] always3(s33) || -> . % 76.04/76.31 114715[79:SSi:114714.0,78214.0,78217.0,108783.0] || -> . % 76.04/76.31 114716[77:Spt:114715.0,114333.0,114334.0] || until2p7(s32)*+ -> . % 76.04/76.31 114717[77:Spt:114715.0,114333.1] || -> node4(s31)*. % 76.04/76.31 114719[77:MRR:825.0,114717.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.04/76.31 114722[77:Res:53.1,114719.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.04/76.31 114727[78:Spt:114722.0] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.31 114729[78:Res:114727.0,61.1] always3(s31) || -> . % 76.04/76.31 114730[78:SSi:114729.0,78205.0,78208.0,108781.0,114332.0,114717.0] || -> . % 76.04/76.31 114731[78:Spt:114730.0,114722.0,114727.0] || m_main_v_state(s31,c_busy)* -> . % 76.04/76.31 114732[78:Spt:114730.0,114722.1] || -> m_main_v_state(s32,c_busy)*. % 76.04/76.31 114736[78:Res:114732.0,61.1] always3(s32) || -> . % 76.04/76.31 114737[78:SSi:114736.0,78209.0,78213.0,108782.0] || -> . % 76.04/76.31 114738[76:Spt:114737.0,114331.0,114332.0] || until2p7(s31)*+ -> . % 76.04/76.31 114739[76:Spt:114737.0,114331.1] || -> node4(s30)*. % 76.04/76.31 114741[76:MRR:828.0,114739.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.04/76.31 114744[76:Res:53.1,114741.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.04/76.31 114746[77:Spt:114744.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.31 114748[77:Res:114746.0,61.1] always3(s30) || -> . % 76.04/76.31 114749[77:SSi:114748.0,78200.0,78204.0,108780.0,114330.0,114739.0] || -> . % 76.04/76.31 114750[77:Spt:114749.0,114744.0,114746.0] || m_main_v_state(s30,c_busy)* -> . % 76.04/76.31 114751[77:Spt:114749.0,114744.1] || -> m_main_v_state(s31,c_busy)*. % 76.04/76.31 114755[77:Res:114751.0,61.1] always3(s31) || -> . % 76.04/76.31 114756[77:SSi:114755.0,78205.0,78208.0,108781.0] || -> . % 76.04/76.31 114757[75:Spt:114756.0,114329.0,114330.0] || until2p7(s30)*+ -> . % 76.04/76.31 114758[75:Spt:114756.0,114329.1] || -> node4(s29)*. % 76.04/76.31 114760[75:MRR:831.0,114758.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.04/76.31 114763[75:Res:53.1,114760.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.04/76.31 114765[75:MRR:114763.0,114319.0] || -> m_main_v_state(s30,c_busy)*. % 76.04/76.31 114767[75:Res:114765.0,61.1] always3(s30) || -> . % 76.04/76.31 114768[75:SSi:114767.0,78200.0,78204.0,108780.0] || -> . % 76.04/76.31 114769[73:Spt:114768.0,114235.0,114238.0] || trans(s49,s29)*+ -> . % 76.04/76.31 114770[73:Spt:114768.0,114235.1,114235.2,114235.3,114235.4,114235.5,114235.6,114235.7,114235.8,114235.9,114235.10,114235.11,114235.12,114235.13,114235.14,114235.15,114235.16,114235.17,114235.18,114235.19,114235.20,114235.21,114235.22,114235.23,114235.24,114235.25,114235.26] || -> trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.04/76.31 114772[73:MRR:114237.1,114769.0] xuntil6(s49) || -> trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.04/76.31 114773[74:Spt:114770.0] || -> trans(s49,s28)*. % 76.04/76.31 114774[74:Res:114773.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s28)*. % 76.04/76.31 114776[74:Res:114773.0,60.0] || -> node2(s49,s28)*. % 76.04/76.31 114777[74:SSi:114774.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s28)*. % 76.04/76.31 114778[74:Res:114776.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)*. % 76.04/76.31 114850[74:SoR:114778.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)*. % 76.04/76.31 114852[74:SoR:114850.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)* xuntil6(s49). % 76.04/76.31 114853[74:SSi:114852.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s28,c_busy)* xuntil6(s49). % 76.04/76.31 114854[75:Spt:114853.1] || -> m_main_v_state(s28,c_busy)*. % 76.04/76.31 114856[75:Res:114854.0,61.1] always3(s28) || -> . % 76.04/76.31 114857[75:SSi:114856.0,78191.0,78195.0,108778.0] || -> . % 76.04/76.31 114858[75:Spt:114857.0,114853.1,114854.0] || m_main_v_state(s28,c_busy)*+ -> . % 76.04/76.31 114859[75:Spt:114857.0,114853.0,114853.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.04/76.31 114863[75:MRR:114850.2,114858.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.04/76.31 114864[75:Res:53.1,114859.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.04/76.31 114866[75:MRR:114864.0,78381.0] || -> xuntil6(s49)*. % 76.04/76.31 114867[75:MRR:114777.0,114866.0] || -> until2p7(s28)*. % 76.04/76.31 114868[75:MRR:224.0,114867.0] || -> until2p7(s29)* node4(s28). % 76.04/76.31 114869[76:Spt:114868.0] || -> until2p7(s29)*. % 76.04/76.31 114870[76:MRR:225.0,114869.0] || -> until2p7(s30)* node4(s29). % 76.04/76.31 114871[77:Spt:114870.0] || -> until2p7(s30)*. % 76.04/76.31 114872[77:MRR:226.0,114871.0] || -> until2p7(s31)* node4(s30). % 76.04/76.31 114873[78:Spt:114872.0] || -> until2p7(s31)*. % 76.04/76.31 114874[78:MRR:227.0,114873.0] || -> until2p7(s32)* node4(s31). % 76.04/76.31 114875[79:Spt:114874.0] || -> until2p7(s32)*. % 76.04/76.31 114876[79:MRR:228.0,114875.0] || -> until2p7(s33)* node4(s32). % 76.04/76.31 114877[80:Spt:114876.0] || -> until2p7(s33)*. % 76.04/76.31 114878[80:MRR:229.0,114877.0] || -> until2p7(s34)* node4(s33). % 76.04/76.31 114879[81:Spt:114878.0] || -> until2p7(s34)*. % 76.04/76.31 114880[81:MRR:230.0,114879.0] || -> until2p7(s35)* node4(s34). % 76.04/76.31 114881[82:Spt:114880.0] || -> until2p7(s35)*. % 76.04/76.31 114882[82:MRR:231.0,114881.0] || -> until2p7(s36)* node4(s35). % 76.04/76.31 114883[83:Spt:114882.0] || -> until2p7(s36)*. % 76.04/76.31 114884[83:MRR:232.0,114883.0] || -> until2p7(s37)* node4(s36). % 76.04/76.31 114885[84:Spt:114884.0] || -> until2p7(s37)*. % 76.04/76.31 114886[84:MRR:235.0,114885.0] || -> until2p7(s38)* node4(s37). % 76.04/76.31 114887[85:Spt:114886.0] || -> until2p7(s38)*. % 76.04/76.31 114888[85:MRR:236.0,114887.0] || -> until2p7(s39)* node4(s38). % 76.04/76.31 114889[86:Spt:114888.0] || -> until2p7(s39)*. % 76.04/76.31 114890[86:MRR:237.0,114889.0] || -> until2p7(s40)* node4(s39). % 76.04/76.31 114891[87:Spt:114890.0] || -> until2p7(s40)*. % 76.04/76.31 114892[87:MRR:238.0,114891.0] || -> until2p7(s41)* node4(s40). % 76.04/76.31 114893[88:Spt:114892.0] || -> until2p7(s41)*. % 76.04/76.31 114894[88:MRR:239.0,114893.0] || -> until2p7(s42)* node4(s41). % 76.04/76.31 114895[89:Spt:114894.0] || -> until2p7(s42)*. % 76.04/76.31 114896[89:MRR:240.0,114895.0] || -> until2p7(s43)* node4(s42). % 76.04/76.31 114897[90:Spt:114896.0] || -> until2p7(s43)*. % 76.04/76.31 114898[90:MRR:241.0,114897.0] || -> until2p7(s44)* node4(s43). % 76.04/76.31 114899[91:Spt:114898.0] || -> until2p7(s44)*. % 76.04/76.31 114900[91:MRR:539.0,114899.0] || -> until2p7(s45)* node4(s44). % 76.04/76.31 114901[92:Spt:114900.0] || -> until2p7(s45)*. % 76.04/76.31 114902[92:MRR:544.0,114901.0] || -> until2p7(s46)* node4(s45). % 76.04/76.31 114903[93:Spt:114902.0] || -> until2p7(s46)*. % 76.04/76.31 114904[93:MRR:549.0,114903.0] || -> until2p7(s47)* node4(s46). % 76.04/76.31 114905[94:Spt:114904.0] || -> until2p7(s47)*. % 76.04/76.31 114906[94:MRR:554.0,114905.0] || -> until2p7(s48)* node4(s47). % 76.04/76.31 114907[95:Spt:114906.0] || -> until2p7(s48)*. % 76.04/76.31 114908[95:MRR:559.0,114907.0] || -> until2p7(s49)* node4(s48). % 76.04/76.31 114909[96:Spt:114908.0] || -> until2p7(s49)*. % 76.04/76.31 114910[96:MRR:194.0,114909.0] || -> node4(s49)*. % 76.04/76.31 114911[96:MRR:114863.0,114910.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.04/76.31 114915[96:Res:53.1,114911.0] || -> m_main_v_state(s49,c_busy)*. % 76.04/76.31 114917[96:MRR:114915.0,78381.0] || -> . % 76.04/76.31 114918[96:Spt:114917.0,114908.0,114909.0] || until2p7(s49)*+ -> . % 76.04/76.31 114919[96:Spt:114917.0,114908.1] || -> node4(s48)*. % 76.04/76.31 114920[96:MRR:78384.0,114919.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.04/76.31 114923[96:Res:53.1,114920.0] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 114926[96:Res:114923.0,61.1] always3(s48) || -> . % 76.04/76.31 114927[96:SSi:114926.0,78281.0,78387.0,108798.0,114907.0,114919.0] || -> . % 76.04/76.31 114928[95:Spt:114927.0,114906.0,114907.0] || until2p7(s48)*+ -> . % 76.04/76.31 114929[95:Spt:114927.0,114906.1] || -> node4(s47)*. % 76.04/76.31 114931[95:MRR:777.0,114929.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.04/76.31 114943[95:Res:53.1,114931.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.04/76.31 114945[96:Spt:114943.0] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 114947[96:Res:114945.0,61.1] always3(s47) || -> . % 76.04/76.31 114948[96:SSi:114947.0,78277.0,78280.0,108797.0,114905.0,114929.0] || -> . % 76.04/76.31 114949[96:Spt:114948.0,114943.0,114945.0] || m_main_v_state(s47,c_busy)* -> . % 76.04/76.31 114950[96:Spt:114948.0,114943.1] || -> m_main_v_state(s48,c_busy)*. % 76.04/76.31 114954[96:Res:114950.0,61.1] always3(s48) || -> . % 76.04/76.31 114955[96:SSi:114954.0,78281.0,78387.0,108798.0] || -> . % 76.04/76.31 114956[94:Spt:114955.0,114904.0,114905.0] || until2p7(s47)*+ -> . % 76.04/76.31 114957[94:Spt:114955.0,114904.1] || -> node4(s46)*. % 76.04/76.31 114959[94:MRR:780.0,114957.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.04/76.31 114966[94:Res:53.1,114959.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.04/76.31 114971[95:Spt:114966.0] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 114973[95:Res:114971.0,61.1] always3(s46) || -> . % 76.04/76.31 114974[95:SSi:114973.0,78272.0,78276.0,108796.0,114903.0,114957.0] || -> . % 76.04/76.31 114975[95:Spt:114974.0,114966.0,114971.0] || m_main_v_state(s46,c_busy)* -> . % 76.04/76.31 114976[95:Spt:114974.0,114966.1] || -> m_main_v_state(s47,c_busy)*. % 76.04/76.31 114980[95:Res:114976.0,61.1] always3(s47) || -> . % 76.04/76.31 114981[95:SSi:114980.0,78277.0,78280.0,108797.0] || -> . % 76.04/76.31 114982[93:Spt:114981.0,114902.0,114903.0] || until2p7(s46)*+ -> . % 76.04/76.31 114983[93:Spt:114981.0,114902.1] || -> node4(s45)*. % 76.04/76.31 114985[93:MRR:783.0,114983.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.04/76.31 114988[93:Res:53.1,114985.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.04/76.31 114990[94:Spt:114988.0] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 114992[94:Res:114990.0,61.1] always3(s45) || -> . % 76.04/76.31 114993[94:SSi:114992.0,78268.0,78271.0,108795.0,114901.0,114983.0] || -> . % 76.04/76.31 114994[94:Spt:114993.0,114988.0,114990.0] || m_main_v_state(s45,c_busy)* -> . % 76.04/76.31 114995[94:Spt:114993.0,114988.1] || -> m_main_v_state(s46,c_busy)*. % 76.04/76.31 114999[94:Res:114995.0,61.1] always3(s46) || -> . % 76.04/76.31 115000[94:SSi:114999.0,78272.0,78276.0,108796.0] || -> . % 76.04/76.31 115001[92:Spt:115000.0,114900.0,114901.0] || until2p7(s45)*+ -> . % 76.04/76.31 115002[92:Spt:115000.0,114900.1] || -> node4(s44)*. % 76.04/76.31 115004[92:MRR:786.0,115002.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.04/76.31 115007[92:Res:53.1,115004.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.04/76.31 115009[93:Spt:115007.0] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 115011[93:Res:115009.0,61.1] always3(s44) || -> . % 76.04/76.31 115012[93:SSi:115011.0,78263.0,78267.0,108794.0,114899.0,115002.0] || -> . % 76.04/76.31 115013[93:Spt:115012.0,115007.0,115009.0] || m_main_v_state(s44,c_busy)* -> . % 76.04/76.31 115014[93:Spt:115012.0,115007.1] || -> m_main_v_state(s45,c_busy)*. % 76.04/76.31 115018[93:Res:115014.0,61.1] always3(s45) || -> . % 76.04/76.31 115019[93:SSi:115018.0,78268.0,78271.0,108795.0] || -> . % 76.04/76.31 115020[91:Spt:115019.0,114898.0,114899.0] || until2p7(s44)*+ -> . % 76.04/76.31 115021[91:Spt:115019.0,114898.1] || -> node4(s43)*. % 76.04/76.31 115023[91:MRR:789.0,115021.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.04/76.31 115026[91:Res:53.1,115023.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.04/76.31 115028[92:Spt:115026.0] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 115030[92:Res:115028.0,61.1] always3(s43) || -> . % 76.04/76.31 115031[92:SSi:115030.0,78259.0,78262.0,108793.0,114897.0,115021.0] || -> . % 76.04/76.31 115032[92:Spt:115031.0,115026.0,115028.0] || m_main_v_state(s43,c_busy)* -> . % 76.04/76.31 115033[92:Spt:115031.0,115026.1] || -> m_main_v_state(s44,c_busy)*. % 76.04/76.31 115037[92:Res:115033.0,61.1] always3(s44) || -> . % 76.04/76.31 115038[92:SSi:115037.0,78263.0,78267.0,108794.0] || -> . % 76.04/76.31 115039[90:Spt:115038.0,114896.0,114897.0] || until2p7(s43)*+ -> . % 76.04/76.31 115040[90:Spt:115038.0,114896.1] || -> node4(s42)*. % 76.04/76.31 115042[90:MRR:792.0,115040.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.04/76.31 115045[90:Res:53.1,115042.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.04/76.31 115050[91:Spt:115045.0] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 115052[91:Res:115050.0,61.1] always3(s42) || -> . % 76.04/76.31 115053[91:SSi:115052.0,78254.0,78258.0,108792.0,114895.0,115040.0] || -> . % 76.04/76.31 115054[91:Spt:115053.0,115045.0,115050.0] || m_main_v_state(s42,c_busy)* -> . % 76.04/76.31 115055[91:Spt:115053.0,115045.1] || -> m_main_v_state(s43,c_busy)*. % 76.04/76.31 115059[91:Res:115055.0,61.1] always3(s43) || -> . % 76.04/76.31 115060[91:SSi:115059.0,78259.0,78262.0,108793.0] || -> . % 76.04/76.31 115061[89:Spt:115060.0,114894.0,114895.0] || until2p7(s42)*+ -> . % 76.04/76.31 115062[89:Spt:115060.0,114894.1] || -> node4(s41)*. % 76.04/76.31 115064[89:MRR:795.0,115062.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.04/76.31 115067[89:Res:53.1,115064.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.04/76.31 115069[90:Spt:115067.0] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 115071[90:Res:115069.0,61.1] always3(s41) || -> . % 76.04/76.31 115072[90:SSi:115071.0,78250.0,78253.0,108791.0,114893.0,115062.0] || -> . % 76.04/76.31 115073[90:Spt:115072.0,115067.0,115069.0] || m_main_v_state(s41,c_busy)* -> . % 76.04/76.31 115074[90:Spt:115072.0,115067.1] || -> m_main_v_state(s42,c_busy)*. % 76.04/76.31 115078[90:Res:115074.0,61.1] always3(s42) || -> . % 76.04/76.31 115079[90:SSi:115078.0,78254.0,78258.0,108792.0] || -> . % 76.04/76.31 115080[88:Spt:115079.0,114892.0,114893.0] || until2p7(s41)*+ -> . % 76.04/76.31 115081[88:Spt:115079.0,114892.1] || -> node4(s40)*. % 76.04/76.31 115083[88:MRR:798.0,115081.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.04/76.31 115086[88:Res:53.1,115083.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.04/76.31 115088[89:Spt:115086.0] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 115090[89:Res:115088.0,61.1] always3(s40) || -> . % 76.04/76.31 115091[89:SSi:115090.0,78245.0,78249.0,108790.0,114891.0,115081.0] || -> . % 76.04/76.31 115092[89:Spt:115091.0,115086.0,115088.0] || m_main_v_state(s40,c_busy)* -> . % 76.04/76.31 115093[89:Spt:115091.0,115086.1] || -> m_main_v_state(s41,c_busy)*. % 76.04/76.31 115097[89:Res:115093.0,61.1] always3(s41) || -> . % 76.04/76.31 115098[89:SSi:115097.0,78250.0,78253.0,108791.0] || -> . % 76.04/76.31 115099[87:Spt:115098.0,114890.0,114891.0] || until2p7(s40)*+ -> . % 76.04/76.31 115100[87:Spt:115098.0,114890.1] || -> node4(s39)*. % 76.04/76.31 115102[87:MRR:801.0,115100.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.04/76.31 115105[87:Res:53.1,115102.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.04/76.31 115107[88:Spt:115105.0] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 115109[88:Res:115107.0,61.1] always3(s39) || -> . % 76.04/76.31 115110[88:SSi:115109.0,78241.0,78244.0,108789.0,114889.0,115100.0] || -> . % 76.04/76.31 115111[88:Spt:115110.0,115105.0,115107.0] || m_main_v_state(s39,c_busy)* -> . % 76.04/76.31 115112[88:Spt:115110.0,115105.1] || -> m_main_v_state(s40,c_busy)*. % 76.04/76.31 115116[88:Res:115112.0,61.1] always3(s40) || -> . % 76.04/76.31 115117[88:SSi:115116.0,78245.0,78249.0,108790.0] || -> . % 76.04/76.31 115118[86:Spt:115117.0,114888.0,114889.0] || until2p7(s39)*+ -> . % 76.04/76.31 115119[86:Spt:115117.0,114888.1] || -> node4(s38)*. % 76.04/76.31 115121[86:MRR:804.0,115119.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.04/76.31 115124[86:Res:53.1,115121.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.04/76.31 115129[87:Spt:115124.0] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 115131[87:Res:115129.0,61.1] always3(s38) || -> . % 76.04/76.31 115132[87:SSi:115131.0,78236.0,78240.0,108788.0,114887.0,115119.0] || -> . % 76.04/76.31 115133[87:Spt:115132.0,115124.0,115129.0] || m_main_v_state(s38,c_busy)* -> . % 76.04/76.31 115134[87:Spt:115132.0,115124.1] || -> m_main_v_state(s39,c_busy)*. % 76.04/76.31 115138[87:Res:115134.0,61.1] always3(s39) || -> . % 76.04/76.31 115139[87:SSi:115138.0,78241.0,78244.0,108789.0] || -> . % 76.04/76.31 115140[85:Spt:115139.0,114886.0,114887.0] || until2p7(s38)*+ -> . % 76.04/76.31 115141[85:Spt:115139.0,114886.1] || -> node4(s37)*. % 76.04/76.31 115143[85:MRR:807.0,115141.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.04/76.31 115146[85:Res:53.1,115143.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.04/76.31 115148[86:Spt:115146.0] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 115150[86:Res:115148.0,61.1] always3(s37) || -> . % 76.04/76.31 115151[86:SSi:115150.0,78232.0,78235.0,108787.0,114885.0,115141.0] || -> . % 76.04/76.31 115152[86:Spt:115151.0,115146.0,115148.0] || m_main_v_state(s37,c_busy)* -> . % 76.04/76.31 115153[86:Spt:115151.0,115146.1] || -> m_main_v_state(s38,c_busy)*. % 76.04/76.31 115157[86:Res:115153.0,61.1] always3(s38) || -> . % 76.04/76.31 115158[86:SSi:115157.0,78236.0,78240.0,108788.0] || -> . % 76.04/76.31 115159[84:Spt:115158.0,114884.0,114885.0] || until2p7(s37)*+ -> . % 76.04/76.31 115160[84:Spt:115158.0,114884.1] || -> node4(s36)*. % 76.04/76.31 115162[84:MRR:810.0,115160.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.04/76.31 115165[84:Res:53.1,115162.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.04/76.31 115167[85:Spt:115165.0] || -> m_main_v_state(s36,c_busy)*. % 76.04/76.31 115169[85:Res:115167.0,61.1] always3(s36) || -> . % 76.04/76.31 115170[85:SSi:115169.0,78227.0,78231.0,108786.0,114883.0,115160.0] || -> . % 76.04/76.31 115171[85:Spt:115170.0,115165.0,115167.0] || m_main_v_state(s36,c_busy)* -> . % 76.04/76.31 115172[85:Spt:115170.0,115165.1] || -> m_main_v_state(s37,c_busy)*. % 76.04/76.31 115176[85:Res:115172.0,61.1] always3(s37) || -> . % 76.04/76.31 115177[85:SSi:115176.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.31 115178[83:Spt:115177.0,114882.0,114883.0] || until2p7(s36)*+ -> . % 76.16/76.31 115179[83:Spt:115177.0,114882.1] || -> node4(s35)*. % 76.16/76.31 115181[83:MRR:813.0,115179.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.31 115184[83:Res:53.1,115181.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.31 115186[84:Spt:115184.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 115188[84:Res:115186.0,61.1] always3(s35) || -> . % 76.16/76.31 115189[84:SSi:115188.0,78223.0,78226.0,108785.0,114881.0,115179.0] || -> . % 76.16/76.31 115190[84:Spt:115189.0,115184.0,115186.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.31 115191[84:Spt:115189.0,115184.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.31 115195[84:Res:115191.0,61.1] always3(s36) || -> . % 76.16/76.31 115196[84:SSi:115195.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.31 115197[82:Spt:115196.0,114880.0,114881.0] || until2p7(s35)*+ -> . % 76.16/76.31 115198[82:Spt:115196.0,114880.1] || -> node4(s34)*. % 76.16/76.31 115200[82:MRR:816.0,115198.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.31 115203[82:Res:53.1,115200.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.31 115208[83:Spt:115203.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 115210[83:Res:115208.0,61.1] always3(s34) || -> . % 76.16/76.31 115211[83:SSi:115210.0,78218.0,78222.0,108784.0,114879.0,115198.0] || -> . % 76.16/76.31 115212[83:Spt:115211.0,115203.0,115208.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.31 115213[83:Spt:115211.0,115203.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 115217[83:Res:115213.0,61.1] always3(s35) || -> . % 76.16/76.31 115218[83:SSi:115217.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.31 115219[81:Spt:115218.0,114878.0,114879.0] || until2p7(s34)*+ -> . % 76.16/76.31 115220[81:Spt:115218.0,114878.1] || -> node4(s33)*. % 76.16/76.31 115222[81:MRR:819.0,115220.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.31 115225[81:Res:53.1,115222.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.31 115227[82:Spt:115225.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 115229[82:Res:115227.0,61.1] always3(s33) || -> . % 76.16/76.31 115230[82:SSi:115229.0,78214.0,78217.0,108783.0,114877.0,115220.0] || -> . % 76.16/76.31 115231[82:Spt:115230.0,115225.0,115227.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.31 115232[82:Spt:115230.0,115225.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 115236[82:Res:115232.0,61.1] always3(s34) || -> . % 76.16/76.31 115237[82:SSi:115236.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.31 115238[80:Spt:115237.0,114876.0,114877.0] || until2p7(s33)*+ -> . % 76.16/76.31 115239[80:Spt:115237.0,114876.1] || -> node4(s32)*. % 76.16/76.31 115241[80:MRR:822.0,115239.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.31 115244[80:Res:53.1,115241.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.31 115246[81:Spt:115244.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 115248[81:Res:115246.0,61.1] always3(s32) || -> . % 76.16/76.31 115249[81:SSi:115248.0,78209.0,78213.0,108782.0,114875.0,115239.0] || -> . % 76.16/76.31 115250[81:Spt:115249.0,115244.0,115246.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.31 115251[81:Spt:115249.0,115244.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 115255[81:Res:115251.0,61.1] always3(s33) || -> . % 76.16/76.31 115256[81:SSi:115255.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.31 115257[79:Spt:115256.0,114874.0,114875.0] || until2p7(s32)*+ -> . % 76.16/76.31 115258[79:Spt:115256.0,114874.1] || -> node4(s31)*. % 76.16/76.31 115260[79:MRR:825.0,115258.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.31 115263[79:Res:53.1,115260.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.31 115265[80:Spt:115263.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 115267[80:Res:115265.0,61.1] always3(s31) || -> . % 76.16/76.31 115268[80:SSi:115267.0,78205.0,78208.0,108781.0,114873.0,115258.0] || -> . % 76.16/76.31 115269[80:Spt:115268.0,115263.0,115265.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.31 115270[80:Spt:115268.0,115263.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 115274[80:Res:115270.0,61.1] always3(s32) || -> . % 76.16/76.31 115275[80:SSi:115274.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.31 115276[78:Spt:115275.0,114872.0,114873.0] || until2p7(s31)*+ -> . % 76.16/76.31 115277[78:Spt:115275.0,114872.1] || -> node4(s30)*. % 76.16/76.31 115279[78:MRR:828.0,115277.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.31 115282[78:Res:53.1,115279.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.31 115287[79:Spt:115282.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 115289[79:Res:115287.0,61.1] always3(s30) || -> . % 76.16/76.31 115290[79:SSi:115289.0,78200.0,78204.0,108780.0,114871.0,115277.0] || -> . % 76.16/76.31 115291[79:Spt:115290.0,115282.0,115287.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.31 115292[79:Spt:115290.0,115282.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 115296[79:Res:115292.0,61.1] always3(s31) || -> . % 76.16/76.31 115297[79:SSi:115296.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.31 115298[77:Spt:115297.0,114870.0,114871.0] || until2p7(s30)*+ -> . % 76.16/76.31 115299[77:Spt:115297.0,114870.1] || -> node4(s29)*. % 76.16/76.31 115301[77:MRR:831.0,115299.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.31 115304[77:Res:53.1,115301.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.31 115306[78:Spt:115304.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 115308[78:Res:115306.0,61.1] always3(s29) || -> . % 76.16/76.31 115309[78:SSi:115308.0,78196.0,78199.0,108779.0,114869.0,115299.0] || -> . % 76.16/76.31 115310[78:Spt:115309.0,115304.0,115306.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.31 115311[78:Spt:115309.0,115304.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 115315[78:Res:115311.0,61.1] always3(s30) || -> . % 76.16/76.31 115316[78:SSi:115315.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.31 115317[76:Spt:115316.0,114868.0,114869.0] || until2p7(s29)*+ -> . % 76.16/76.31 115318[76:Spt:115316.0,114868.1] || -> node4(s28)*. % 76.16/76.31 115320[76:MRR:834.0,115318.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.31 115323[76:Res:53.1,115320.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.31 115325[76:MRR:115323.0,114858.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 115327[76:Res:115325.0,61.1] always3(s29) || -> . % 76.16/76.31 115328[76:SSi:115327.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.31 115329[74:Spt:115328.0,114770.0,114773.0] || trans(s49,s28)*+ -> . % 76.16/76.31 115330[74:Spt:115328.0,114770.1,114770.2,114770.3,114770.4,114770.5,114770.6,114770.7,114770.8,114770.9,114770.10,114770.11,114770.12,114770.13,114770.14,114770.15,114770.16,114770.17,114770.18,114770.19,114770.20,114770.21,114770.22,114770.23,114770.24,114770.25] || -> trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.31 115332[74:MRR:114772.1,115329.0] xuntil6(s49) || -> trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.31 115333[75:Spt:115330.0] || -> trans(s49,s27)*. % 76.16/76.31 115334[75:Res:115333.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s27)*. % 76.16/76.31 115336[75:Res:115333.0,60.0] || -> node2(s49,s27)*. % 76.16/76.31 115337[75:SSi:115334.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s27)*. % 76.16/76.31 115338[75:Res:115336.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)*. % 76.16/76.31 115414[75:SoR:115338.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)*. % 76.16/76.31 115416[75:SoR:115414.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)* xuntil6(s49). % 76.16/76.31 115417[75:SSi:115416.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s27,c_busy)* xuntil6(s49). % 76.16/76.31 115418[76:Spt:115417.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.31 115420[76:Res:115418.0,61.1] always3(s27) || -> . % 76.16/76.31 115421[76:SSi:115420.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.31 115422[76:Spt:115421.0,115417.1,115418.0] || m_main_v_state(s27,c_busy)*+ -> . % 76.16/76.31 115423[76:Spt:115421.0,115417.0,115417.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.31 115427[76:MRR:115414.2,115422.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.31 115428[76:Res:53.1,115423.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.31 115430[76:MRR:115428.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.31 115431[76:MRR:115337.0,115430.0] || -> until2p7(s27)*. % 76.16/76.31 115432[76:MRR:223.0,115431.0] || -> until2p7(s28)* node4(s27). % 76.16/76.31 115433[77:Spt:115432.0] || -> until2p7(s28)*. % 76.16/76.31 115434[77:MRR:224.0,115433.0] || -> until2p7(s29)* node4(s28). % 76.16/76.31 115435[78:Spt:115434.0] || -> until2p7(s29)*. % 76.16/76.31 115436[78:MRR:225.0,115435.0] || -> until2p7(s30)* node4(s29). % 76.16/76.31 115437[79:Spt:115436.0] || -> until2p7(s30)*. % 76.16/76.31 115438[79:MRR:226.0,115437.0] || -> until2p7(s31)* node4(s30). % 76.16/76.31 115439[80:Spt:115438.0] || -> until2p7(s31)*. % 76.16/76.31 115440[80:MRR:227.0,115439.0] || -> until2p7(s32)* node4(s31). % 76.16/76.31 115441[81:Spt:115440.0] || -> until2p7(s32)*. % 76.16/76.31 115442[81:MRR:228.0,115441.0] || -> until2p7(s33)* node4(s32). % 76.16/76.31 115443[82:Spt:115442.0] || -> until2p7(s33)*. % 76.16/76.31 115444[82:MRR:229.0,115443.0] || -> until2p7(s34)* node4(s33). % 76.16/76.31 115445[83:Spt:115444.0] || -> until2p7(s34)*. % 76.16/76.31 115446[83:MRR:230.0,115445.0] || -> until2p7(s35)* node4(s34). % 76.16/76.31 115447[84:Spt:115446.0] || -> until2p7(s35)*. % 76.16/76.31 115448[84:MRR:231.0,115447.0] || -> until2p7(s36)* node4(s35). % 76.16/76.31 115449[85:Spt:115448.0] || -> until2p7(s36)*. % 76.16/76.31 115450[85:MRR:232.0,115449.0] || -> until2p7(s37)* node4(s36). % 76.16/76.31 115451[86:Spt:115450.0] || -> until2p7(s37)*. % 76.16/76.31 115452[86:MRR:235.0,115451.0] || -> until2p7(s38)* node4(s37). % 76.16/76.31 115453[87:Spt:115452.0] || -> until2p7(s38)*. % 76.16/76.31 115454[87:MRR:236.0,115453.0] || -> until2p7(s39)* node4(s38). % 76.16/76.31 115455[88:Spt:115454.0] || -> until2p7(s39)*. % 76.16/76.31 115456[88:MRR:237.0,115455.0] || -> until2p7(s40)* node4(s39). % 76.16/76.31 115457[89:Spt:115456.0] || -> until2p7(s40)*. % 76.16/76.31 115458[89:MRR:238.0,115457.0] || -> until2p7(s41)* node4(s40). % 76.16/76.31 115459[90:Spt:115458.0] || -> until2p7(s41)*. % 76.16/76.31 115460[90:MRR:239.0,115459.0] || -> until2p7(s42)* node4(s41). % 76.16/76.31 115461[91:Spt:115460.0] || -> until2p7(s42)*. % 76.16/76.31 115462[91:MRR:240.0,115461.0] || -> until2p7(s43)* node4(s42). % 76.16/76.31 115463[92:Spt:115462.0] || -> until2p7(s43)*. % 76.16/76.31 115464[92:MRR:241.0,115463.0] || -> until2p7(s44)* node4(s43). % 76.16/76.31 115465[93:Spt:115464.0] || -> until2p7(s44)*. % 76.16/76.31 115466[93:MRR:539.0,115465.0] || -> until2p7(s45)* node4(s44). % 76.16/76.31 115467[94:Spt:115466.0] || -> until2p7(s45)*. % 76.16/76.31 115468[94:MRR:544.0,115467.0] || -> until2p7(s46)* node4(s45). % 76.16/76.31 115469[95:Spt:115468.0] || -> until2p7(s46)*. % 76.16/76.31 115470[95:MRR:549.0,115469.0] || -> until2p7(s47)* node4(s46). % 76.16/76.31 115471[96:Spt:115470.0] || -> until2p7(s47)*. % 76.16/76.31 115472[96:MRR:554.0,115471.0] || -> until2p7(s48)* node4(s47). % 76.16/76.31 115473[97:Spt:115472.0] || -> until2p7(s48)*. % 76.16/76.31 115474[97:MRR:559.0,115473.0] || -> until2p7(s49)* node4(s48). % 76.16/76.31 115475[98:Spt:115474.0] || -> until2p7(s49)*. % 76.16/76.31 115476[98:MRR:194.0,115475.0] || -> node4(s49)*. % 76.16/76.31 115477[98:MRR:115427.0,115476.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.31 115478[98:Res:53.1,115477.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.31 115480[98:MRR:115478.0,78381.0] || -> . % 76.16/76.31 115481[98:Spt:115480.0,115474.0,115475.0] || until2p7(s49)*+ -> . % 76.16/76.31 115482[98:Spt:115480.0,115474.1] || -> node4(s48)*. % 76.16/76.31 115483[98:MRR:78384.0,115482.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.31 115486[98:Res:53.1,115483.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 115489[98:Res:115486.0,61.1] always3(s48) || -> . % 76.16/76.31 115490[98:SSi:115489.0,78281.0,78387.0,108798.0,115473.0,115482.0] || -> . % 76.16/76.31 115491[97:Spt:115490.0,115472.0,115473.0] || until2p7(s48)*+ -> . % 76.16/76.31 115492[97:Spt:115490.0,115472.1] || -> node4(s47)*. % 76.16/76.31 115494[97:MRR:777.0,115492.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.31 115509[97:Res:53.1,115494.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.31 115514[98:Spt:115509.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 115516[98:Res:115514.0,61.1] always3(s47) || -> . % 76.16/76.31 115517[98:SSi:115516.0,78277.0,78280.0,108797.0,115471.0,115492.0] || -> . % 76.16/76.31 115518[98:Spt:115517.0,115509.0,115514.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.31 115519[98:Spt:115517.0,115509.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 115523[98:Res:115519.0,61.1] always3(s48) || -> . % 76.16/76.31 115524[98:SSi:115523.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.31 115525[96:Spt:115524.0,115470.0,115471.0] || until2p7(s47)*+ -> . % 76.16/76.31 115526[96:Spt:115524.0,115470.1] || -> node4(s46)*. % 76.16/76.31 115528[96:MRR:780.0,115526.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.31 115535[96:Res:53.1,115528.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.31 115537[97:Spt:115535.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 115539[97:Res:115537.0,61.1] always3(s46) || -> . % 76.16/76.31 115540[97:SSi:115539.0,78272.0,78276.0,108796.0,115469.0,115526.0] || -> . % 76.16/76.31 115541[97:Spt:115540.0,115535.0,115537.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.31 115542[97:Spt:115540.0,115535.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 115546[97:Res:115542.0,61.1] always3(s47) || -> . % 76.16/76.31 115547[97:SSi:115546.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.31 115548[95:Spt:115547.0,115468.0,115469.0] || until2p7(s46)*+ -> . % 76.16/76.31 115549[95:Spt:115547.0,115468.1] || -> node4(s45)*. % 76.16/76.31 115551[95:MRR:783.0,115549.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.31 115554[95:Res:53.1,115551.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.31 115559[96:Spt:115554.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 115561[96:Res:115559.0,61.1] always3(s45) || -> . % 76.16/76.31 115562[96:SSi:115561.0,78268.0,78271.0,108795.0,115467.0,115549.0] || -> . % 76.16/76.31 115563[96:Spt:115562.0,115554.0,115559.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.31 115564[96:Spt:115562.0,115554.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 115568[96:Res:115564.0,61.1] always3(s46) || -> . % 76.16/76.31 115569[96:SSi:115568.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.31 115570[94:Spt:115569.0,115466.0,115467.0] || until2p7(s45)*+ -> . % 76.16/76.31 115571[94:Spt:115569.0,115466.1] || -> node4(s44)*. % 76.16/76.31 115573[94:MRR:786.0,115571.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.31 115576[94:Res:53.1,115573.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.31 115578[95:Spt:115576.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 115580[95:Res:115578.0,61.1] always3(s44) || -> . % 76.16/76.31 115581[95:SSi:115580.0,78263.0,78267.0,108794.0,115465.0,115571.0] || -> . % 76.16/76.31 115582[95:Spt:115581.0,115576.0,115578.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.31 115583[95:Spt:115581.0,115576.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 115587[95:Res:115583.0,61.1] always3(s45) || -> . % 76.16/76.31 115588[95:SSi:115587.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.31 115589[93:Spt:115588.0,115464.0,115465.0] || until2p7(s44)*+ -> . % 76.16/76.31 115590[93:Spt:115588.0,115464.1] || -> node4(s43)*. % 76.16/76.31 115592[93:MRR:789.0,115590.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.31 115595[93:Res:53.1,115592.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.31 115597[94:Spt:115595.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 115599[94:Res:115597.0,61.1] always3(s43) || -> . % 76.16/76.31 115600[94:SSi:115599.0,78259.0,78262.0,108793.0,115463.0,115590.0] || -> . % 76.16/76.31 115601[94:Spt:115600.0,115595.0,115597.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.31 115602[94:Spt:115600.0,115595.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 115606[94:Res:115602.0,61.1] always3(s44) || -> . % 76.16/76.31 115607[94:SSi:115606.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.31 115608[92:Spt:115607.0,115462.0,115463.0] || until2p7(s43)*+ -> . % 76.16/76.31 115609[92:Spt:115607.0,115462.1] || -> node4(s42)*. % 76.16/76.31 115611[92:MRR:792.0,115609.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.31 115614[92:Res:53.1,115611.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.31 115616[93:Spt:115614.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 115618[93:Res:115616.0,61.1] always3(s42) || -> . % 76.16/76.31 115619[93:SSi:115618.0,78254.0,78258.0,108792.0,115461.0,115609.0] || -> . % 76.16/76.31 115620[93:Spt:115619.0,115614.0,115616.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.31 115621[93:Spt:115619.0,115614.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 115625[93:Res:115621.0,61.1] always3(s43) || -> . % 76.16/76.31 115626[93:SSi:115625.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.31 115627[91:Spt:115626.0,115460.0,115461.0] || until2p7(s42)*+ -> . % 76.16/76.31 115628[91:Spt:115626.0,115460.1] || -> node4(s41)*. % 76.16/76.31 115630[91:MRR:795.0,115628.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.31 115633[91:Res:53.1,115630.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.31 115638[92:Spt:115633.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 115640[92:Res:115638.0,61.1] always3(s41) || -> . % 76.16/76.31 115641[92:SSi:115640.0,78250.0,78253.0,108791.0,115459.0,115628.0] || -> . % 76.16/76.31 115642[92:Spt:115641.0,115633.0,115638.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.31 115643[92:Spt:115641.0,115633.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 115647[92:Res:115643.0,61.1] always3(s42) || -> . % 76.16/76.31 115648[92:SSi:115647.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.31 115649[90:Spt:115648.0,115458.0,115459.0] || until2p7(s41)*+ -> . % 76.16/76.31 115650[90:Spt:115648.0,115458.1] || -> node4(s40)*. % 76.16/76.31 115652[90:MRR:798.0,115650.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.31 115655[90:Res:53.1,115652.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.31 115657[91:Spt:115655.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.31 115659[91:Res:115657.0,61.1] always3(s40) || -> . % 76.16/76.31 115660[91:SSi:115659.0,78245.0,78249.0,108790.0,115457.0,115650.0] || -> . % 76.16/76.31 115661[91:Spt:115660.0,115655.0,115657.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.31 115662[91:Spt:115660.0,115655.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 115666[91:Res:115662.0,61.1] always3(s41) || -> . % 76.16/76.31 115667[91:SSi:115666.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.31 115668[89:Spt:115667.0,115456.0,115457.0] || until2p7(s40)*+ -> . % 76.16/76.31 115669[89:Spt:115667.0,115456.1] || -> node4(s39)*. % 76.16/76.31 115671[89:MRR:801.0,115669.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.31 115674[89:Res:53.1,115671.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.31 115676[90:Spt:115674.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.31 115678[90:Res:115676.0,61.1] always3(s39) || -> . % 76.16/76.31 115679[90:SSi:115678.0,78241.0,78244.0,108789.0,115455.0,115669.0] || -> . % 76.16/76.31 115680[90:Spt:115679.0,115674.0,115676.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.31 115681[90:Spt:115679.0,115674.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.31 115685[90:Res:115681.0,61.1] always3(s40) || -> . % 76.16/76.31 115686[90:SSi:115685.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.31 115687[88:Spt:115686.0,115454.0,115455.0] || until2p7(s39)*+ -> . % 76.16/76.31 115688[88:Spt:115686.0,115454.1] || -> node4(s38)*. % 76.16/76.31 115690[88:MRR:804.0,115688.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.31 115693[88:Res:53.1,115690.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.31 115695[89:Spt:115693.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.31 115697[89:Res:115695.0,61.1] always3(s38) || -> . % 76.16/76.31 115698[89:SSi:115697.0,78236.0,78240.0,108788.0,115453.0,115688.0] || -> . % 76.16/76.31 115699[89:Spt:115698.0,115693.0,115695.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.31 115700[89:Spt:115698.0,115693.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.31 115704[89:Res:115700.0,61.1] always3(s39) || -> . % 76.16/76.31 115705[89:SSi:115704.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.31 115706[87:Spt:115705.0,115452.0,115453.0] || until2p7(s38)*+ -> . % 76.16/76.31 115707[87:Spt:115705.0,115452.1] || -> node4(s37)*. % 76.16/76.31 115709[87:MRR:807.0,115707.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.31 115712[87:Res:53.1,115709.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.31 115717[88:Spt:115712.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.31 115719[88:Res:115717.0,61.1] always3(s37) || -> . % 76.16/76.31 115720[88:SSi:115719.0,78232.0,78235.0,108787.0,115451.0,115707.0] || -> . % 76.16/76.31 115721[88:Spt:115720.0,115712.0,115717.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.31 115722[88:Spt:115720.0,115712.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.31 115726[88:Res:115722.0,61.1] always3(s38) || -> . % 76.16/76.31 115727[88:SSi:115726.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.31 115728[86:Spt:115727.0,115450.0,115451.0] || until2p7(s37)*+ -> . % 76.16/76.31 115729[86:Spt:115727.0,115450.1] || -> node4(s36)*. % 76.16/76.31 115731[86:MRR:810.0,115729.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.31 115734[86:Res:53.1,115731.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.31 115736[87:Spt:115734.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.31 115738[87:Res:115736.0,61.1] always3(s36) || -> . % 76.16/76.31 115739[87:SSi:115738.0,78227.0,78231.0,108786.0,115449.0,115729.0] || -> . % 76.16/76.31 115740[87:Spt:115739.0,115734.0,115736.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.31 115741[87:Spt:115739.0,115734.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.31 115745[87:Res:115741.0,61.1] always3(s37) || -> . % 76.16/76.31 115746[87:SSi:115745.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.31 115747[85:Spt:115746.0,115448.0,115449.0] || until2p7(s36)*+ -> . % 76.16/76.31 115748[85:Spt:115746.0,115448.1] || -> node4(s35)*. % 76.16/76.31 115750[85:MRR:813.0,115748.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.31 115753[85:Res:53.1,115750.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.31 115755[86:Spt:115753.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 115757[86:Res:115755.0,61.1] always3(s35) || -> . % 76.16/76.31 115758[86:SSi:115757.0,78223.0,78226.0,108785.0,115447.0,115748.0] || -> . % 76.16/76.31 115759[86:Spt:115758.0,115753.0,115755.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.31 115760[86:Spt:115758.0,115753.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.31 115764[86:Res:115760.0,61.1] always3(s36) || -> . % 76.16/76.31 115765[86:SSi:115764.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.31 115766[84:Spt:115765.0,115446.0,115447.0] || until2p7(s35)*+ -> . % 76.16/76.31 115767[84:Spt:115765.0,115446.1] || -> node4(s34)*. % 76.16/76.31 115769[84:MRR:816.0,115767.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.31 115772[84:Res:53.1,115769.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.31 115774[85:Spt:115772.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 115776[85:Res:115774.0,61.1] always3(s34) || -> . % 76.16/76.31 115777[85:SSi:115776.0,78218.0,78222.0,108784.0,115445.0,115767.0] || -> . % 76.16/76.31 115778[85:Spt:115777.0,115772.0,115774.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.31 115779[85:Spt:115777.0,115772.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 115783[85:Res:115779.0,61.1] always3(s35) || -> . % 76.16/76.31 115784[85:SSi:115783.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.31 115785[83:Spt:115784.0,115444.0,115445.0] || until2p7(s34)*+ -> . % 76.16/76.31 115786[83:Spt:115784.0,115444.1] || -> node4(s33)*. % 76.16/76.31 115788[83:MRR:819.0,115786.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.31 115791[83:Res:53.1,115788.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.31 115796[84:Spt:115791.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 115798[84:Res:115796.0,61.1] always3(s33) || -> . % 76.16/76.31 115799[84:SSi:115798.0,78214.0,78217.0,108783.0,115443.0,115786.0] || -> . % 76.16/76.31 115800[84:Spt:115799.0,115791.0,115796.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.31 115801[84:Spt:115799.0,115791.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 115805[84:Res:115801.0,61.1] always3(s34) || -> . % 76.16/76.31 115806[84:SSi:115805.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.31 115807[82:Spt:115806.0,115442.0,115443.0] || until2p7(s33)*+ -> . % 76.16/76.31 115808[82:Spt:115806.0,115442.1] || -> node4(s32)*. % 76.16/76.31 115810[82:MRR:822.0,115808.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.31 115813[82:Res:53.1,115810.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.31 115815[83:Spt:115813.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 115817[83:Res:115815.0,61.1] always3(s32) || -> . % 76.16/76.31 115818[83:SSi:115817.0,78209.0,78213.0,108782.0,115441.0,115808.0] || -> . % 76.16/76.31 115819[83:Spt:115818.0,115813.0,115815.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.31 115820[83:Spt:115818.0,115813.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 115824[83:Res:115820.0,61.1] always3(s33) || -> . % 76.16/76.31 115825[83:SSi:115824.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.31 115826[81:Spt:115825.0,115440.0,115441.0] || until2p7(s32)*+ -> . % 76.16/76.31 115827[81:Spt:115825.0,115440.1] || -> node4(s31)*. % 76.16/76.31 115829[81:MRR:825.0,115827.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.31 115832[81:Res:53.1,115829.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.31 115834[82:Spt:115832.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 115836[82:Res:115834.0,61.1] always3(s31) || -> . % 76.16/76.31 115837[82:SSi:115836.0,78205.0,78208.0,108781.0,115439.0,115827.0] || -> . % 76.16/76.31 115838[82:Spt:115837.0,115832.0,115834.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.31 115839[82:Spt:115837.0,115832.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 115843[82:Res:115839.0,61.1] always3(s32) || -> . % 76.16/76.31 115844[82:SSi:115843.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.31 115845[80:Spt:115844.0,115438.0,115439.0] || until2p7(s31)*+ -> . % 76.16/76.31 115846[80:Spt:115844.0,115438.1] || -> node4(s30)*. % 76.16/76.31 115848[80:MRR:828.0,115846.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.31 115851[80:Res:53.1,115848.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.31 115853[81:Spt:115851.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 115855[81:Res:115853.0,61.1] always3(s30) || -> . % 76.16/76.31 115856[81:SSi:115855.0,78200.0,78204.0,108780.0,115437.0,115846.0] || -> . % 76.16/76.31 115857[81:Spt:115856.0,115851.0,115853.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.31 115858[81:Spt:115856.0,115851.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 115862[81:Res:115858.0,61.1] always3(s31) || -> . % 76.16/76.31 115863[81:SSi:115862.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.31 115864[79:Spt:115863.0,115436.0,115437.0] || until2p7(s30)*+ -> . % 76.16/76.31 115865[79:Spt:115863.0,115436.1] || -> node4(s29)*. % 76.16/76.31 115867[79:MRR:831.0,115865.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.31 115870[79:Res:53.1,115867.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.31 115875[80:Spt:115870.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 115877[80:Res:115875.0,61.1] always3(s29) || -> . % 76.16/76.31 115878[80:SSi:115877.0,78196.0,78199.0,108779.0,115435.0,115865.0] || -> . % 76.16/76.31 115879[80:Spt:115878.0,115870.0,115875.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.31 115880[80:Spt:115878.0,115870.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 115884[80:Res:115880.0,61.1] always3(s30) || -> . % 76.16/76.31 115885[80:SSi:115884.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.31 115886[78:Spt:115885.0,115434.0,115435.0] || until2p7(s29)*+ -> . % 76.16/76.31 115887[78:Spt:115885.0,115434.1] || -> node4(s28)*. % 76.16/76.31 115889[78:MRR:834.0,115887.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.31 115892[78:Res:53.1,115889.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.31 115894[79:Spt:115892.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.31 115896[79:Res:115894.0,61.1] always3(s28) || -> . % 76.16/76.31 115897[79:SSi:115896.0,78191.0,78195.0,108778.0,115433.0,115887.0] || -> . % 76.16/76.31 115898[79:Spt:115897.0,115892.0,115894.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.31 115899[79:Spt:115897.0,115892.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 115903[79:Res:115899.0,61.1] always3(s29) || -> . % 76.16/76.31 115904[79:SSi:115903.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.31 115905[77:Spt:115904.0,115432.0,115433.0] || until2p7(s28)*+ -> . % 76.16/76.31 115906[77:Spt:115904.0,115432.1] || -> node4(s27)*. % 76.16/76.31 115908[77:MRR:837.0,115906.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.31 115911[77:Res:53.1,115908.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.31 115913[77:MRR:115911.0,115422.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.31 115915[77:Res:115913.0,61.1] always3(s28) || -> . % 76.16/76.31 115916[77:SSi:115915.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.31 115917[75:Spt:115916.0,115330.0,115333.0] || trans(s49,s27)*+ -> . % 76.16/76.31 115918[75:Spt:115916.0,115330.1,115330.2,115330.3,115330.4,115330.5,115330.6,115330.7,115330.8,115330.9,115330.10,115330.11,115330.12,115330.13,115330.14,115330.15,115330.16,115330.17,115330.18,115330.19,115330.20,115330.21,115330.22,115330.23,115330.24] || -> trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.31 115920[75:MRR:115332.1,115917.0] xuntil6(s49) || -> trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.31 115921[76:Spt:115918.0] || -> trans(s49,s26)*. % 76.16/76.31 115922[76:Res:115921.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s26)*. % 76.16/76.31 115924[76:Res:115921.0,60.0] || -> node2(s49,s26)*. % 76.16/76.31 115925[76:SSi:115922.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s26)*. % 76.16/76.31 115926[76:Res:115924.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)*. % 76.16/76.31 116003[76:SoR:115926.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)*. % 76.16/76.31 116005[76:SoR:116003.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)* xuntil6(s49). % 76.16/76.31 116006[76:SSi:116005.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s26,c_busy)* xuntil6(s49). % 76.16/76.31 116007[77:Spt:116006.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.31 116009[77:Res:116007.0,61.1] always3(s26) || -> . % 76.16/76.31 116010[77:SSi:116009.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.31 116011[77:Spt:116010.0,116006.1,116007.0] || m_main_v_state(s26,c_busy)*+ -> . % 76.16/76.31 116012[77:Spt:116010.0,116006.0,116006.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.31 116016[77:MRR:116003.2,116011.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.31 116017[77:Res:53.1,116012.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.31 116019[77:MRR:116017.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.31 116020[77:MRR:115925.0,116019.0] || -> until2p7(s26)*. % 76.16/76.31 116021[77:MRR:222.0,116020.0] || -> until2p7(s27)* node4(s26). % 76.16/76.31 116022[78:Spt:116021.0] || -> until2p7(s27)*. % 76.16/76.31 116023[78:MRR:223.0,116022.0] || -> until2p7(s28)* node4(s27). % 76.16/76.31 116024[79:Spt:116023.0] || -> until2p7(s28)*. % 76.16/76.31 116025[79:MRR:224.0,116024.0] || -> until2p7(s29)* node4(s28). % 76.16/76.31 116026[80:Spt:116025.0] || -> until2p7(s29)*. % 76.16/76.31 116027[80:MRR:225.0,116026.0] || -> until2p7(s30)* node4(s29). % 76.16/76.31 116028[81:Spt:116027.0] || -> until2p7(s30)*. % 76.16/76.31 116029[81:MRR:226.0,116028.0] || -> until2p7(s31)* node4(s30). % 76.16/76.31 116030[82:Spt:116029.0] || -> until2p7(s31)*. % 76.16/76.31 116031[82:MRR:227.0,116030.0] || -> until2p7(s32)* node4(s31). % 76.16/76.31 116032[83:Spt:116031.0] || -> until2p7(s32)*. % 76.16/76.31 116033[83:MRR:228.0,116032.0] || -> until2p7(s33)* node4(s32). % 76.16/76.31 116034[84:Spt:116033.0] || -> until2p7(s33)*. % 76.16/76.31 116035[84:MRR:229.0,116034.0] || -> until2p7(s34)* node4(s33). % 76.16/76.31 116036[85:Spt:116035.0] || -> until2p7(s34)*. % 76.16/76.31 116037[85:MRR:230.0,116036.0] || -> until2p7(s35)* node4(s34). % 76.16/76.31 116038[86:Spt:116037.0] || -> until2p7(s35)*. % 76.16/76.31 116039[86:MRR:231.0,116038.0] || -> until2p7(s36)* node4(s35). % 76.16/76.31 116040[87:Spt:116039.0] || -> until2p7(s36)*. % 76.16/76.31 116041[87:MRR:232.0,116040.0] || -> until2p7(s37)* node4(s36). % 76.16/76.31 116042[88:Spt:116041.0] || -> until2p7(s37)*. % 76.16/76.31 116043[88:MRR:235.0,116042.0] || -> until2p7(s38)* node4(s37). % 76.16/76.31 116044[89:Spt:116043.0] || -> until2p7(s38)*. % 76.16/76.31 116045[89:MRR:236.0,116044.0] || -> until2p7(s39)* node4(s38). % 76.16/76.31 116046[90:Spt:116045.0] || -> until2p7(s39)*. % 76.16/76.31 116047[90:MRR:237.0,116046.0] || -> until2p7(s40)* node4(s39). % 76.16/76.31 116048[91:Spt:116047.0] || -> until2p7(s40)*. % 76.16/76.31 116049[91:MRR:238.0,116048.0] || -> until2p7(s41)* node4(s40). % 76.16/76.31 116050[92:Spt:116049.0] || -> until2p7(s41)*. % 76.16/76.31 116051[92:MRR:239.0,116050.0] || -> until2p7(s42)* node4(s41). % 76.16/76.31 116052[93:Spt:116051.0] || -> until2p7(s42)*. % 76.16/76.31 116053[93:MRR:240.0,116052.0] || -> until2p7(s43)* node4(s42). % 76.16/76.31 116054[94:Spt:116053.0] || -> until2p7(s43)*. % 76.16/76.31 116055[94:MRR:241.0,116054.0] || -> until2p7(s44)* node4(s43). % 76.16/76.31 116056[95:Spt:116055.0] || -> until2p7(s44)*. % 76.16/76.31 116057[95:MRR:539.0,116056.0] || -> until2p7(s45)* node4(s44). % 76.16/76.31 116058[96:Spt:116057.0] || -> until2p7(s45)*. % 76.16/76.31 116059[96:MRR:544.0,116058.0] || -> until2p7(s46)* node4(s45). % 76.16/76.31 116060[97:Spt:116059.0] || -> until2p7(s46)*. % 76.16/76.31 116061[97:MRR:549.0,116060.0] || -> until2p7(s47)* node4(s46). % 76.16/76.31 116062[98:Spt:116061.0] || -> until2p7(s47)*. % 76.16/76.31 116063[98:MRR:554.0,116062.0] || -> until2p7(s48)* node4(s47). % 76.16/76.31 116064[99:Spt:116063.0] || -> until2p7(s48)*. % 76.16/76.31 116065[99:MRR:559.0,116064.0] || -> until2p7(s49)* node4(s48). % 76.16/76.31 116066[100:Spt:116065.0] || -> until2p7(s49)*. % 76.16/76.31 116067[100:MRR:194.0,116066.0] || -> node4(s49)*. % 76.16/76.31 116068[100:MRR:116016.0,116067.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.31 116072[100:Res:53.1,116068.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.31 116074[100:MRR:116072.0,78381.0] || -> . % 76.16/76.31 116075[100:Spt:116074.0,116065.0,116066.0] || until2p7(s49)*+ -> . % 76.16/76.31 116076[100:Spt:116074.0,116065.1] || -> node4(s48)*. % 76.16/76.31 116077[100:MRR:78384.0,116076.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.31 116080[100:Res:53.1,116077.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 116083[100:Res:116080.0,61.1] always3(s48) || -> . % 76.16/76.31 116084[100:SSi:116083.0,78281.0,78387.0,108798.0,116064.0,116076.0] || -> . % 76.16/76.31 116085[99:Spt:116084.0,116063.0,116064.0] || until2p7(s48)*+ -> . % 76.16/76.31 116086[99:Spt:116084.0,116063.1] || -> node4(s47)*. % 76.16/76.31 116088[99:MRR:777.0,116086.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.31 116100[99:Res:53.1,116088.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.31 116102[100:Spt:116100.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 116104[100:Res:116102.0,61.1] always3(s47) || -> . % 76.16/76.31 116105[100:SSi:116104.0,78277.0,78280.0,108797.0,116062.0,116086.0] || -> . % 76.16/76.31 116106[100:Spt:116105.0,116100.0,116102.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.31 116107[100:Spt:116105.0,116100.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 116111[100:Res:116107.0,61.1] always3(s48) || -> . % 76.16/76.31 116112[100:SSi:116111.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.31 116113[98:Spt:116112.0,116061.0,116062.0] || until2p7(s47)*+ -> . % 76.16/76.31 116114[98:Spt:116112.0,116061.1] || -> node4(s46)*. % 76.16/76.31 116116[98:MRR:780.0,116114.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.31 116123[98:Res:53.1,116116.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.31 116128[99:Spt:116123.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 116130[99:Res:116128.0,61.1] always3(s46) || -> . % 76.16/76.31 116131[99:SSi:116130.0,78272.0,78276.0,108796.0,116060.0,116114.0] || -> . % 76.16/76.31 116132[99:Spt:116131.0,116123.0,116128.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.31 116133[99:Spt:116131.0,116123.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 116137[99:Res:116133.0,61.1] always3(s47) || -> . % 76.16/76.31 116138[99:SSi:116137.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.31 116139[97:Spt:116138.0,116059.0,116060.0] || until2p7(s46)*+ -> . % 76.16/76.31 116140[97:Spt:116138.0,116059.1] || -> node4(s45)*. % 76.16/76.31 116142[97:MRR:783.0,116140.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.31 116145[97:Res:53.1,116142.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.31 116147[98:Spt:116145.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 116149[98:Res:116147.0,61.1] always3(s45) || -> . % 76.16/76.31 116150[98:SSi:116149.0,78268.0,78271.0,108795.0,116058.0,116140.0] || -> . % 76.16/76.31 116151[98:Spt:116150.0,116145.0,116147.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.31 116152[98:Spt:116150.0,116145.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 116156[98:Res:116152.0,61.1] always3(s46) || -> . % 76.16/76.31 116157[98:SSi:116156.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.31 116158[96:Spt:116157.0,116057.0,116058.0] || until2p7(s45)*+ -> . % 76.16/76.31 116159[96:Spt:116157.0,116057.1] || -> node4(s44)*. % 76.16/76.31 116161[96:MRR:786.0,116159.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.31 116164[96:Res:53.1,116161.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.31 116166[97:Spt:116164.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 116168[97:Res:116166.0,61.1] always3(s44) || -> . % 76.16/76.31 116169[97:SSi:116168.0,78263.0,78267.0,108794.0,116056.0,116159.0] || -> . % 76.16/76.31 116170[97:Spt:116169.0,116164.0,116166.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.31 116171[97:Spt:116169.0,116164.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 116175[97:Res:116171.0,61.1] always3(s45) || -> . % 76.16/76.31 116176[97:SSi:116175.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.31 116177[95:Spt:116176.0,116055.0,116056.0] || until2p7(s44)*+ -> . % 76.16/76.31 116178[95:Spt:116176.0,116055.1] || -> node4(s43)*. % 76.16/76.31 116180[95:MRR:789.0,116178.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.31 116183[95:Res:53.1,116180.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.31 116185[96:Spt:116183.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 116187[96:Res:116185.0,61.1] always3(s43) || -> . % 76.16/76.31 116188[96:SSi:116187.0,78259.0,78262.0,108793.0,116054.0,116178.0] || -> . % 76.16/76.31 116189[96:Spt:116188.0,116183.0,116185.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.31 116190[96:Spt:116188.0,116183.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 116194[96:Res:116190.0,61.1] always3(s44) || -> . % 76.16/76.31 116195[96:SSi:116194.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.31 116196[94:Spt:116195.0,116053.0,116054.0] || until2p7(s43)*+ -> . % 76.16/76.31 116197[94:Spt:116195.0,116053.1] || -> node4(s42)*. % 76.16/76.31 116199[94:MRR:792.0,116197.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.31 116202[94:Res:53.1,116199.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.31 116207[95:Spt:116202.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 116209[95:Res:116207.0,61.1] always3(s42) || -> . % 76.16/76.31 116210[95:SSi:116209.0,78254.0,78258.0,108792.0,116052.0,116197.0] || -> . % 76.16/76.31 116211[95:Spt:116210.0,116202.0,116207.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.31 116212[95:Spt:116210.0,116202.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 116216[95:Res:116212.0,61.1] always3(s43) || -> . % 76.16/76.31 116217[95:SSi:116216.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.31 116218[93:Spt:116217.0,116051.0,116052.0] || until2p7(s42)*+ -> . % 76.16/76.31 116219[93:Spt:116217.0,116051.1] || -> node4(s41)*. % 76.16/76.31 116221[93:MRR:795.0,116219.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.31 116224[93:Res:53.1,116221.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.31 116226[94:Spt:116224.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 116228[94:Res:116226.0,61.1] always3(s41) || -> . % 76.16/76.31 116229[94:SSi:116228.0,78250.0,78253.0,108791.0,116050.0,116219.0] || -> . % 76.16/76.31 116230[94:Spt:116229.0,116224.0,116226.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.31 116231[94:Spt:116229.0,116224.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 116235[94:Res:116231.0,61.1] always3(s42) || -> . % 76.16/76.31 116236[94:SSi:116235.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.31 116237[92:Spt:116236.0,116049.0,116050.0] || until2p7(s41)*+ -> . % 76.16/76.31 116238[92:Spt:116236.0,116049.1] || -> node4(s40)*. % 76.16/76.31 116240[92:MRR:798.0,116238.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.31 116243[92:Res:53.1,116240.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.31 116245[93:Spt:116243.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.31 116247[93:Res:116245.0,61.1] always3(s40) || -> . % 76.16/76.31 116248[93:SSi:116247.0,78245.0,78249.0,108790.0,116048.0,116238.0] || -> . % 76.16/76.31 116249[93:Spt:116248.0,116243.0,116245.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.31 116250[93:Spt:116248.0,116243.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 116254[93:Res:116250.0,61.1] always3(s41) || -> . % 76.16/76.31 116255[93:SSi:116254.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.31 116256[91:Spt:116255.0,116047.0,116048.0] || until2p7(s40)*+ -> . % 76.16/76.31 116257[91:Spt:116255.0,116047.1] || -> node4(s39)*. % 76.16/76.31 116259[91:MRR:801.0,116257.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.31 116262[91:Res:53.1,116259.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.31 116264[92:Spt:116262.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.31 116266[92:Res:116264.0,61.1] always3(s39) || -> . % 76.16/76.31 116267[92:SSi:116266.0,78241.0,78244.0,108789.0,116046.0,116257.0] || -> . % 76.16/76.31 116268[92:Spt:116267.0,116262.0,116264.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.31 116269[92:Spt:116267.0,116262.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.31 116273[92:Res:116269.0,61.1] always3(s40) || -> . % 76.16/76.31 116274[92:SSi:116273.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.31 116275[90:Spt:116274.0,116045.0,116046.0] || until2p7(s39)*+ -> . % 76.16/76.31 116276[90:Spt:116274.0,116045.1] || -> node4(s38)*. % 76.16/76.31 116278[90:MRR:804.0,116276.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.31 116281[90:Res:53.1,116278.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.31 116286[91:Spt:116281.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.31 116288[91:Res:116286.0,61.1] always3(s38) || -> . % 76.16/76.31 116289[91:SSi:116288.0,78236.0,78240.0,108788.0,116044.0,116276.0] || -> . % 76.16/76.31 116290[91:Spt:116289.0,116281.0,116286.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.31 116291[91:Spt:116289.0,116281.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.31 116295[91:Res:116291.0,61.1] always3(s39) || -> . % 76.16/76.31 116296[91:SSi:116295.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.31 116297[89:Spt:116296.0,116043.0,116044.0] || until2p7(s38)*+ -> . % 76.16/76.31 116298[89:Spt:116296.0,116043.1] || -> node4(s37)*. % 76.16/76.31 116300[89:MRR:807.0,116298.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.31 116303[89:Res:53.1,116300.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.31 116305[90:Spt:116303.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.31 116307[90:Res:116305.0,61.1] always3(s37) || -> . % 76.16/76.31 116308[90:SSi:116307.0,78232.0,78235.0,108787.0,116042.0,116298.0] || -> . % 76.16/76.31 116309[90:Spt:116308.0,116303.0,116305.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.31 116310[90:Spt:116308.0,116303.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.31 116314[90:Res:116310.0,61.1] always3(s38) || -> . % 76.16/76.31 116315[90:SSi:116314.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.31 116316[88:Spt:116315.0,116041.0,116042.0] || until2p7(s37)*+ -> . % 76.16/76.31 116317[88:Spt:116315.0,116041.1] || -> node4(s36)*. % 76.16/76.31 116319[88:MRR:810.0,116317.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.31 116322[88:Res:53.1,116319.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.31 116324[89:Spt:116322.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.31 116326[89:Res:116324.0,61.1] always3(s36) || -> . % 76.16/76.31 116327[89:SSi:116326.0,78227.0,78231.0,108786.0,116040.0,116317.0] || -> . % 76.16/76.31 116328[89:Spt:116327.0,116322.0,116324.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.31 116329[89:Spt:116327.0,116322.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.31 116333[89:Res:116329.0,61.1] always3(s37) || -> . % 76.16/76.31 116334[89:SSi:116333.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.31 116335[87:Spt:116334.0,116039.0,116040.0] || until2p7(s36)*+ -> . % 76.16/76.31 116336[87:Spt:116334.0,116039.1] || -> node4(s35)*. % 76.16/76.31 116338[87:MRR:813.0,116336.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.31 116341[87:Res:53.1,116338.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.31 116343[88:Spt:116341.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 116345[88:Res:116343.0,61.1] always3(s35) || -> . % 76.16/76.31 116346[88:SSi:116345.0,78223.0,78226.0,108785.0,116038.0,116336.0] || -> . % 76.16/76.31 116347[88:Spt:116346.0,116341.0,116343.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.31 116348[88:Spt:116346.0,116341.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.31 116352[88:Res:116348.0,61.1] always3(s36) || -> . % 76.16/76.31 116353[88:SSi:116352.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.31 116354[86:Spt:116353.0,116037.0,116038.0] || until2p7(s35)*+ -> . % 76.16/76.31 116355[86:Spt:116353.0,116037.1] || -> node4(s34)*. % 76.16/76.31 116357[86:MRR:816.0,116355.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.31 116360[86:Res:53.1,116357.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.31 116365[87:Spt:116360.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 116367[87:Res:116365.0,61.1] always3(s34) || -> . % 76.16/76.31 116368[87:SSi:116367.0,78218.0,78222.0,108784.0,116036.0,116355.0] || -> . % 76.16/76.31 116369[87:Spt:116368.0,116360.0,116365.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.31 116370[87:Spt:116368.0,116360.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 116374[87:Res:116370.0,61.1] always3(s35) || -> . % 76.16/76.31 116375[87:SSi:116374.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.31 116376[85:Spt:116375.0,116035.0,116036.0] || until2p7(s34)*+ -> . % 76.16/76.31 116377[85:Spt:116375.0,116035.1] || -> node4(s33)*. % 76.16/76.31 116379[85:MRR:819.0,116377.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.31 116382[85:Res:53.1,116379.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.31 116384[86:Spt:116382.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 116386[86:Res:116384.0,61.1] always3(s33) || -> . % 76.16/76.31 116387[86:SSi:116386.0,78214.0,78217.0,108783.0,116034.0,116377.0] || -> . % 76.16/76.31 116388[86:Spt:116387.0,116382.0,116384.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.31 116389[86:Spt:116387.0,116382.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 116393[86:Res:116389.0,61.1] always3(s34) || -> . % 76.16/76.31 116394[86:SSi:116393.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.31 116395[84:Spt:116394.0,116033.0,116034.0] || until2p7(s33)*+ -> . % 76.16/76.31 116396[84:Spt:116394.0,116033.1] || -> node4(s32)*. % 76.16/76.31 116398[84:MRR:822.0,116396.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.31 116401[84:Res:53.1,116398.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.31 116403[85:Spt:116401.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 116405[85:Res:116403.0,61.1] always3(s32) || -> . % 76.16/76.31 116406[85:SSi:116405.0,78209.0,78213.0,108782.0,116032.0,116396.0] || -> . % 76.16/76.31 116407[85:Spt:116406.0,116401.0,116403.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.31 116408[85:Spt:116406.0,116401.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 116412[85:Res:116408.0,61.1] always3(s33) || -> . % 76.16/76.31 116413[85:SSi:116412.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.31 116414[83:Spt:116413.0,116031.0,116032.0] || until2p7(s32)*+ -> . % 76.16/76.31 116415[83:Spt:116413.0,116031.1] || -> node4(s31)*. % 76.16/76.31 116417[83:MRR:825.0,116415.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.31 116420[83:Res:53.1,116417.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.31 116422[84:Spt:116420.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 116424[84:Res:116422.0,61.1] always3(s31) || -> . % 76.16/76.31 116425[84:SSi:116424.0,78205.0,78208.0,108781.0,116030.0,116415.0] || -> . % 76.16/76.31 116426[84:Spt:116425.0,116420.0,116422.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.31 116427[84:Spt:116425.0,116420.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 116431[84:Res:116427.0,61.1] always3(s32) || -> . % 76.16/76.31 116432[84:SSi:116431.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.31 116433[82:Spt:116432.0,116029.0,116030.0] || until2p7(s31)*+ -> . % 76.16/76.31 116434[82:Spt:116432.0,116029.1] || -> node4(s30)*. % 76.16/76.31 116436[82:MRR:828.0,116434.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.31 116439[82:Res:53.1,116436.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.31 116444[83:Spt:116439.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 116446[83:Res:116444.0,61.1] always3(s30) || -> . % 76.16/76.31 116447[83:SSi:116446.0,78200.0,78204.0,108780.0,116028.0,116434.0] || -> . % 76.16/76.31 116448[83:Spt:116447.0,116439.0,116444.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.31 116449[83:Spt:116447.0,116439.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 116453[83:Res:116449.0,61.1] always3(s31) || -> . % 76.16/76.31 116454[83:SSi:116453.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.31 116455[81:Spt:116454.0,116027.0,116028.0] || until2p7(s30)*+ -> . % 76.16/76.31 116456[81:Spt:116454.0,116027.1] || -> node4(s29)*. % 76.16/76.31 116458[81:MRR:831.0,116456.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.31 116461[81:Res:53.1,116458.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.31 116463[82:Spt:116461.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 116465[82:Res:116463.0,61.1] always3(s29) || -> . % 76.16/76.31 116466[82:SSi:116465.0,78196.0,78199.0,108779.0,116026.0,116456.0] || -> . % 76.16/76.31 116467[82:Spt:116466.0,116461.0,116463.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.31 116468[82:Spt:116466.0,116461.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 116472[82:Res:116468.0,61.1] always3(s30) || -> . % 76.16/76.31 116473[82:SSi:116472.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.31 116474[80:Spt:116473.0,116025.0,116026.0] || until2p7(s29)*+ -> . % 76.16/76.31 116475[80:Spt:116473.0,116025.1] || -> node4(s28)*. % 76.16/76.31 116477[80:MRR:834.0,116475.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.31 116480[80:Res:53.1,116477.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.31 116482[81:Spt:116480.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.31 116484[81:Res:116482.0,61.1] always3(s28) || -> . % 76.16/76.31 116485[81:SSi:116484.0,78191.0,78195.0,108778.0,116024.0,116475.0] || -> . % 76.16/76.31 116486[81:Spt:116485.0,116480.0,116482.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.31 116487[81:Spt:116485.0,116480.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 116491[81:Res:116487.0,61.1] always3(s29) || -> . % 76.16/76.31 116492[81:SSi:116491.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.31 116493[79:Spt:116492.0,116023.0,116024.0] || until2p7(s28)*+ -> . % 76.16/76.31 116494[79:Spt:116492.0,116023.1] || -> node4(s27)*. % 76.16/76.31 116496[79:MRR:837.0,116494.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.31 116499[79:Res:53.1,116496.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.31 116501[80:Spt:116499.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.31 116503[80:Res:116501.0,61.1] always3(s27) || -> . % 76.16/76.31 116504[80:SSi:116503.0,78187.0,78190.0,108777.0,116022.0,116494.0] || -> . % 76.16/76.31 116505[80:Spt:116504.0,116499.0,116501.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.31 116506[80:Spt:116504.0,116499.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.31 116510[80:Res:116506.0,61.1] always3(s28) || -> . % 76.16/76.31 116511[80:SSi:116510.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.31 116512[78:Spt:116511.0,116021.0,116022.0] || until2p7(s27)*+ -> . % 76.16/76.31 116513[78:Spt:116511.0,116021.1] || -> node4(s26)*. % 76.16/76.31 116515[78:MRR:840.0,116513.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.31 116518[78:Res:53.1,116515.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.31 116520[78:MRR:116518.0,116011.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.31 116525[78:Res:116520.0,61.1] always3(s27) || -> . % 76.16/76.31 116526[78:SSi:116525.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.31 116527[76:Spt:116526.0,115918.0,115921.0] || trans(s49,s26)*+ -> . % 76.16/76.31 116528[76:Spt:116526.0,115918.1,115918.2,115918.3,115918.4,115918.5,115918.6,115918.7,115918.8,115918.9,115918.10,115918.11,115918.12,115918.13,115918.14,115918.15,115918.16,115918.17,115918.18,115918.19,115918.20,115918.21,115918.22,115918.23] || -> trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.31 116530[76:MRR:115920.1,116527.0] xuntil6(s49) || -> trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.31 116531[77:Spt:116528.0] || -> trans(s49,s25)*. % 76.16/76.31 116532[77:Res:116531.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s25)*. % 76.16/76.31 116534[77:Res:116531.0,60.0] || -> node2(s49,s25)*. % 76.16/76.31 116535[77:SSi:116532.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s25)*. % 76.16/76.31 116536[77:Res:116534.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)*. % 76.16/76.31 116617[77:SoR:116536.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)*. % 76.16/76.31 116619[77:SoR:116617.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)* xuntil6(s49). % 76.16/76.31 116620[77:SSi:116619.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s25,c_busy)* xuntil6(s49). % 76.16/76.31 116621[78:Spt:116620.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.31 116623[78:Res:116621.0,61.1] always3(s25) || -> . % 76.16/76.31 116624[78:SSi:116623.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.31 116625[78:Spt:116624.0,116620.1,116621.0] || m_main_v_state(s25,c_busy)*+ -> . % 76.16/76.31 116626[78:Spt:116624.0,116620.0,116620.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.31 116630[78:MRR:116617.2,116625.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.31 116631[78:Res:53.1,116626.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.31 116633[78:MRR:116631.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.31 116634[78:MRR:116535.0,116633.0] || -> until2p7(s25)*. % 76.16/76.31 116635[78:MRR:221.0,116634.0] || -> until2p7(s26)* node4(s25). % 76.16/76.31 116636[79:Spt:116635.0] || -> until2p7(s26)*. % 76.16/76.31 116637[79:MRR:222.0,116636.0] || -> until2p7(s27)* node4(s26). % 76.16/76.31 116638[80:Spt:116637.0] || -> until2p7(s27)*. % 76.16/76.31 116639[80:MRR:223.0,116638.0] || -> until2p7(s28)* node4(s27). % 76.16/76.31 116640[81:Spt:116639.0] || -> until2p7(s28)*. % 76.16/76.31 116641[81:MRR:224.0,116640.0] || -> until2p7(s29)* node4(s28). % 76.16/76.31 116642[82:Spt:116641.0] || -> until2p7(s29)*. % 76.16/76.31 116643[82:MRR:225.0,116642.0] || -> until2p7(s30)* node4(s29). % 76.16/76.31 116644[83:Spt:116643.0] || -> until2p7(s30)*. % 76.16/76.31 116645[83:MRR:226.0,116644.0] || -> until2p7(s31)* node4(s30). % 76.16/76.31 116646[84:Spt:116645.0] || -> until2p7(s31)*. % 76.16/76.31 116647[84:MRR:227.0,116646.0] || -> until2p7(s32)* node4(s31). % 76.16/76.31 116648[85:Spt:116647.0] || -> until2p7(s32)*. % 76.16/76.31 116649[85:MRR:228.0,116648.0] || -> until2p7(s33)* node4(s32). % 76.16/76.31 116650[86:Spt:116649.0] || -> until2p7(s33)*. % 76.16/76.31 116651[86:MRR:229.0,116650.0] || -> until2p7(s34)* node4(s33). % 76.16/76.31 116652[87:Spt:116651.0] || -> until2p7(s34)*. % 76.16/76.31 116653[87:MRR:230.0,116652.0] || -> until2p7(s35)* node4(s34). % 76.16/76.31 116654[88:Spt:116653.0] || -> until2p7(s35)*. % 76.16/76.31 116655[88:MRR:231.0,116654.0] || -> until2p7(s36)* node4(s35). % 76.16/76.31 116656[89:Spt:116655.0] || -> until2p7(s36)*. % 76.16/76.31 116657[89:MRR:232.0,116656.0] || -> until2p7(s37)* node4(s36). % 76.16/76.31 116658[90:Spt:116657.0] || -> until2p7(s37)*. % 76.16/76.31 116659[90:MRR:235.0,116658.0] || -> until2p7(s38)* node4(s37). % 76.16/76.31 116660[91:Spt:116659.0] || -> until2p7(s38)*. % 76.16/76.31 116661[91:MRR:236.0,116660.0] || -> until2p7(s39)* node4(s38). % 76.16/76.31 116662[92:Spt:116661.0] || -> until2p7(s39)*. % 76.16/76.31 116663[92:MRR:237.0,116662.0] || -> until2p7(s40)* node4(s39). % 76.16/76.31 116664[93:Spt:116663.0] || -> until2p7(s40)*. % 76.16/76.31 116665[93:MRR:238.0,116664.0] || -> until2p7(s41)* node4(s40). % 76.16/76.31 116666[94:Spt:116665.0] || -> until2p7(s41)*. % 76.16/76.31 116667[94:MRR:239.0,116666.0] || -> until2p7(s42)* node4(s41). % 76.16/76.31 116668[95:Spt:116667.0] || -> until2p7(s42)*. % 76.16/76.31 116669[95:MRR:240.0,116668.0] || -> until2p7(s43)* node4(s42). % 76.16/76.31 116670[96:Spt:116669.0] || -> until2p7(s43)*. % 76.16/76.31 116671[96:MRR:241.0,116670.0] || -> until2p7(s44)* node4(s43). % 76.16/76.31 116672[97:Spt:116671.0] || -> until2p7(s44)*. % 76.16/76.31 116673[97:MRR:539.0,116672.0] || -> until2p7(s45)* node4(s44). % 76.16/76.31 116674[98:Spt:116673.0] || -> until2p7(s45)*. % 76.16/76.31 116675[98:MRR:544.0,116674.0] || -> until2p7(s46)* node4(s45). % 76.16/76.31 116676[99:Spt:116675.0] || -> until2p7(s46)*. % 76.16/76.31 116677[99:MRR:549.0,116676.0] || -> until2p7(s47)* node4(s46). % 76.16/76.31 116678[100:Spt:116677.0] || -> until2p7(s47)*. % 76.16/76.31 116679[100:MRR:554.0,116678.0] || -> until2p7(s48)* node4(s47). % 76.16/76.31 116680[101:Spt:116679.0] || -> until2p7(s48)*. % 76.16/76.31 116681[101:MRR:559.0,116680.0] || -> until2p7(s49)* node4(s48). % 76.16/76.31 116682[102:Spt:116681.0] || -> until2p7(s49)*. % 76.16/76.31 116683[102:MRR:194.0,116682.0] || -> node4(s49)*. % 76.16/76.31 116684[102:MRR:116630.0,116683.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.31 116685[102:Res:53.1,116684.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.31 116687[102:MRR:116685.0,78381.0] || -> . % 76.16/76.31 116688[102:Spt:116687.0,116681.0,116682.0] || until2p7(s49)*+ -> . % 76.16/76.31 116689[102:Spt:116687.0,116681.1] || -> node4(s48)*. % 76.16/76.31 116690[102:MRR:78384.0,116689.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.31 116693[102:Res:53.1,116690.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 116696[102:Res:116693.0,61.1] always3(s48) || -> . % 76.16/76.31 116697[102:SSi:116696.0,78281.0,78387.0,108798.0,116680.0,116689.0] || -> . % 76.16/76.31 116698[101:Spt:116697.0,116679.0,116680.0] || until2p7(s48)*+ -> . % 76.16/76.31 116699[101:Spt:116697.0,116679.1] || -> node4(s47)*. % 76.16/76.31 116701[101:MRR:777.0,116699.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.31 116716[101:Res:53.1,116701.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.31 116718[102:Spt:116716.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 116720[102:Res:116718.0,61.1] always3(s47) || -> . % 76.16/76.31 116721[102:SSi:116720.0,78277.0,78280.0,108797.0,116678.0,116699.0] || -> . % 76.16/76.31 116722[102:Spt:116721.0,116716.0,116718.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.31 116723[102:Spt:116721.0,116716.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 116727[102:Res:116723.0,61.1] always3(s48) || -> . % 76.16/76.31 116728[102:SSi:116727.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.31 116729[100:Spt:116728.0,116677.0,116678.0] || until2p7(s47)*+ -> . % 76.16/76.31 116730[100:Spt:116728.0,116677.1] || -> node4(s46)*. % 76.16/76.31 116732[100:MRR:780.0,116730.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.31 116742[100:Res:53.1,116732.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.31 116744[101:Spt:116742.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 116746[101:Res:116744.0,61.1] always3(s46) || -> . % 76.16/76.31 116747[101:SSi:116746.0,78272.0,78276.0,108796.0,116676.0,116730.0] || -> . % 76.16/76.31 116748[101:Spt:116747.0,116742.0,116744.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.31 116749[101:Spt:116747.0,116742.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 116753[101:Res:116749.0,61.1] always3(s47) || -> . % 76.16/76.31 116754[101:SSi:116753.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.31 116755[99:Spt:116754.0,116675.0,116676.0] || until2p7(s46)*+ -> . % 76.16/76.31 116756[99:Spt:116754.0,116675.1] || -> node4(s45)*. % 76.16/76.31 116758[99:MRR:783.0,116756.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.31 116761[99:Res:53.1,116758.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.31 116763[100:Spt:116761.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 116765[100:Res:116763.0,61.1] always3(s45) || -> . % 76.16/76.31 116766[100:SSi:116765.0,78268.0,78271.0,108795.0,116674.0,116756.0] || -> . % 76.16/76.31 116767[100:Spt:116766.0,116761.0,116763.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.31 116768[100:Spt:116766.0,116761.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 116772[100:Res:116768.0,61.1] always3(s46) || -> . % 76.16/76.31 116773[100:SSi:116772.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.31 116774[98:Spt:116773.0,116673.0,116674.0] || until2p7(s45)*+ -> . % 76.16/76.31 116775[98:Spt:116773.0,116673.1] || -> node4(s44)*. % 76.16/76.31 116777[98:MRR:786.0,116775.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.31 116780[98:Res:53.1,116777.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.31 116782[99:Spt:116780.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 116784[99:Res:116782.0,61.1] always3(s44) || -> . % 76.16/76.31 116785[99:SSi:116784.0,78263.0,78267.0,108794.0,116672.0,116775.0] || -> . % 76.16/76.31 116786[99:Spt:116785.0,116780.0,116782.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.31 116787[99:Spt:116785.0,116780.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 116791[99:Res:116787.0,61.1] always3(s45) || -> . % 76.16/76.31 116792[99:SSi:116791.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.31 116793[97:Spt:116792.0,116671.0,116672.0] || until2p7(s44)*+ -> . % 76.16/76.31 116794[97:Spt:116792.0,116671.1] || -> node4(s43)*. % 76.16/76.31 116796[97:MRR:789.0,116794.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.31 116799[97:Res:53.1,116796.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.31 116804[98:Spt:116799.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 116806[98:Res:116804.0,61.1] always3(s43) || -> . % 76.16/76.31 116807[98:SSi:116806.0,78259.0,78262.0,108793.0,116670.0,116794.0] || -> . % 76.16/76.31 116808[98:Spt:116807.0,116799.0,116804.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.31 116809[98:Spt:116807.0,116799.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 116813[98:Res:116809.0,61.1] always3(s44) || -> . % 76.16/76.31 116814[98:SSi:116813.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.31 116815[96:Spt:116814.0,116669.0,116670.0] || until2p7(s43)*+ -> . % 76.16/76.31 116816[96:Spt:116814.0,116669.1] || -> node4(s42)*. % 76.16/76.31 116818[96:MRR:792.0,116816.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.31 116821[96:Res:53.1,116818.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.31 116823[97:Spt:116821.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 116825[97:Res:116823.0,61.1] always3(s42) || -> . % 76.16/76.31 116826[97:SSi:116825.0,78254.0,78258.0,108792.0,116668.0,116816.0] || -> . % 76.16/76.31 116827[97:Spt:116826.0,116821.0,116823.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.31 116828[97:Spt:116826.0,116821.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 116832[97:Res:116828.0,61.1] always3(s43) || -> . % 76.16/76.31 116833[97:SSi:116832.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.31 116834[95:Spt:116833.0,116667.0,116668.0] || until2p7(s42)*+ -> . % 76.16/76.31 116835[95:Spt:116833.0,116667.1] || -> node4(s41)*. % 76.16/76.31 116837[95:MRR:795.0,116835.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.31 116840[95:Res:53.1,116837.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.31 116842[96:Spt:116840.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 116844[96:Res:116842.0,61.1] always3(s41) || -> . % 76.16/76.31 116845[96:SSi:116844.0,78250.0,78253.0,108791.0,116666.0,116835.0] || -> . % 76.16/76.31 116846[96:Spt:116845.0,116840.0,116842.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.31 116847[96:Spt:116845.0,116840.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 116851[96:Res:116847.0,61.1] always3(s42) || -> . % 76.16/76.31 116852[96:SSi:116851.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.31 116853[94:Spt:116852.0,116665.0,116666.0] || until2p7(s41)*+ -> . % 76.16/76.31 116854[94:Spt:116852.0,116665.1] || -> node4(s40)*. % 76.16/76.31 116856[94:MRR:798.0,116854.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.31 116859[94:Res:53.1,116856.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.31 116861[95:Spt:116859.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.31 116863[95:Res:116861.0,61.1] always3(s40) || -> . % 76.16/76.31 116864[95:SSi:116863.0,78245.0,78249.0,108790.0,116664.0,116854.0] || -> . % 76.16/76.31 116865[95:Spt:116864.0,116859.0,116861.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.31 116866[95:Spt:116864.0,116859.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 116870[95:Res:116866.0,61.1] always3(s41) || -> . % 76.16/76.31 116871[95:SSi:116870.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.31 116872[93:Spt:116871.0,116663.0,116664.0] || until2p7(s40)*+ -> . % 76.16/76.31 116873[93:Spt:116871.0,116663.1] || -> node4(s39)*. % 76.16/76.31 116875[93:MRR:801.0,116873.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.31 116878[93:Res:53.1,116875.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.31 116883[94:Spt:116878.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.31 116885[94:Res:116883.0,61.1] always3(s39) || -> . % 76.16/76.31 116886[94:SSi:116885.0,78241.0,78244.0,108789.0,116662.0,116873.0] || -> . % 76.16/76.31 116887[94:Spt:116886.0,116878.0,116883.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.31 116888[94:Spt:116886.0,116878.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.31 116892[94:Res:116888.0,61.1] always3(s40) || -> . % 76.16/76.31 116893[94:SSi:116892.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.31 116894[92:Spt:116893.0,116661.0,116662.0] || until2p7(s39)*+ -> . % 76.16/76.31 116895[92:Spt:116893.0,116661.1] || -> node4(s38)*. % 76.16/76.31 116897[92:MRR:804.0,116895.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.31 116900[92:Res:53.1,116897.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.31 116902[93:Spt:116900.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.31 116904[93:Res:116902.0,61.1] always3(s38) || -> . % 76.16/76.31 116905[93:SSi:116904.0,78236.0,78240.0,108788.0,116660.0,116895.0] || -> . % 76.16/76.31 116906[93:Spt:116905.0,116900.0,116902.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.31 116907[93:Spt:116905.0,116900.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.31 116911[93:Res:116907.0,61.1] always3(s39) || -> . % 76.16/76.31 116912[93:SSi:116911.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.31 116913[91:Spt:116912.0,116659.0,116660.0] || until2p7(s38)*+ -> . % 76.16/76.31 116914[91:Spt:116912.0,116659.1] || -> node4(s37)*. % 76.16/76.31 116916[91:MRR:807.0,116914.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.31 116919[91:Res:53.1,116916.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.31 116921[92:Spt:116919.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.31 116923[92:Res:116921.0,61.1] always3(s37) || -> . % 76.16/76.31 116924[92:SSi:116923.0,78232.0,78235.0,108787.0,116658.0,116914.0] || -> . % 76.16/76.31 116925[92:Spt:116924.0,116919.0,116921.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.31 116926[92:Spt:116924.0,116919.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.31 116930[92:Res:116926.0,61.1] always3(s38) || -> . % 76.16/76.31 116931[92:SSi:116930.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.31 116932[90:Spt:116931.0,116657.0,116658.0] || until2p7(s37)*+ -> . % 76.16/76.31 116933[90:Spt:116931.0,116657.1] || -> node4(s36)*. % 76.16/76.31 116935[90:MRR:810.0,116933.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.31 116938[90:Res:53.1,116935.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.31 116940[91:Spt:116938.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.31 116942[91:Res:116940.0,61.1] always3(s36) || -> . % 76.16/76.31 116943[91:SSi:116942.0,78227.0,78231.0,108786.0,116656.0,116933.0] || -> . % 76.16/76.31 116944[91:Spt:116943.0,116938.0,116940.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.31 116945[91:Spt:116943.0,116938.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.31 116949[91:Res:116945.0,61.1] always3(s37) || -> . % 76.16/76.31 116950[91:SSi:116949.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.31 116951[89:Spt:116950.0,116655.0,116656.0] || until2p7(s36)*+ -> . % 76.16/76.31 116952[89:Spt:116950.0,116655.1] || -> node4(s35)*. % 76.16/76.31 116954[89:MRR:813.0,116952.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.31 116957[89:Res:53.1,116954.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.31 116962[90:Spt:116957.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 116964[90:Res:116962.0,61.1] always3(s35) || -> . % 76.16/76.31 116965[90:SSi:116964.0,78223.0,78226.0,108785.0,116654.0,116952.0] || -> . % 76.16/76.31 116966[90:Spt:116965.0,116957.0,116962.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.31 116967[90:Spt:116965.0,116957.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.31 116971[90:Res:116967.0,61.1] always3(s36) || -> . % 76.16/76.31 116972[90:SSi:116971.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.31 116973[88:Spt:116972.0,116653.0,116654.0] || until2p7(s35)*+ -> . % 76.16/76.31 116974[88:Spt:116972.0,116653.1] || -> node4(s34)*. % 76.16/76.31 116976[88:MRR:816.0,116974.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.31 116979[88:Res:53.1,116976.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.31 116981[89:Spt:116979.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 116983[89:Res:116981.0,61.1] always3(s34) || -> . % 76.16/76.31 116984[89:SSi:116983.0,78218.0,78222.0,108784.0,116652.0,116974.0] || -> . % 76.16/76.31 116985[89:Spt:116984.0,116979.0,116981.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.31 116986[89:Spt:116984.0,116979.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 116990[89:Res:116986.0,61.1] always3(s35) || -> . % 76.16/76.31 116991[89:SSi:116990.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.31 116992[87:Spt:116991.0,116651.0,116652.0] || until2p7(s34)*+ -> . % 76.16/76.31 116993[87:Spt:116991.0,116651.1] || -> node4(s33)*. % 76.16/76.31 116995[87:MRR:819.0,116993.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.31 116998[87:Res:53.1,116995.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.31 117000[88:Spt:116998.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 117002[88:Res:117000.0,61.1] always3(s33) || -> . % 76.16/76.31 117003[88:SSi:117002.0,78214.0,78217.0,108783.0,116650.0,116993.0] || -> . % 76.16/76.31 117004[88:Spt:117003.0,116998.0,117000.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.31 117005[88:Spt:117003.0,116998.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 117009[88:Res:117005.0,61.1] always3(s34) || -> . % 76.16/76.31 117010[88:SSi:117009.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.31 117011[86:Spt:117010.0,116649.0,116650.0] || until2p7(s33)*+ -> . % 76.16/76.31 117012[86:Spt:117010.0,116649.1] || -> node4(s32)*. % 76.16/76.31 117014[86:MRR:822.0,117012.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.31 117017[86:Res:53.1,117014.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.31 117019[87:Spt:117017.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 117021[87:Res:117019.0,61.1] always3(s32) || -> . % 76.16/76.31 117022[87:SSi:117021.0,78209.0,78213.0,108782.0,116648.0,117012.0] || -> . % 76.16/76.31 117023[87:Spt:117022.0,117017.0,117019.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.31 117024[87:Spt:117022.0,117017.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 117028[87:Res:117024.0,61.1] always3(s33) || -> . % 76.16/76.31 117029[87:SSi:117028.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.31 117030[85:Spt:117029.0,116647.0,116648.0] || until2p7(s32)*+ -> . % 76.16/76.31 117031[85:Spt:117029.0,116647.1] || -> node4(s31)*. % 76.16/76.31 117033[85:MRR:825.0,117031.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.31 117036[85:Res:53.1,117033.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.31 117041[86:Spt:117036.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 117043[86:Res:117041.0,61.1] always3(s31) || -> . % 76.16/76.31 117044[86:SSi:117043.0,78205.0,78208.0,108781.0,116646.0,117031.0] || -> . % 76.16/76.31 117045[86:Spt:117044.0,117036.0,117041.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.31 117046[86:Spt:117044.0,117036.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 117050[86:Res:117046.0,61.1] always3(s32) || -> . % 76.16/76.31 117051[86:SSi:117050.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.31 117052[84:Spt:117051.0,116645.0,116646.0] || until2p7(s31)*+ -> . % 76.16/76.31 117053[84:Spt:117051.0,116645.1] || -> node4(s30)*. % 76.16/76.31 117055[84:MRR:828.0,117053.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.31 117058[84:Res:53.1,117055.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.31 117060[85:Spt:117058.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 117062[85:Res:117060.0,61.1] always3(s30) || -> . % 76.16/76.31 117063[85:SSi:117062.0,78200.0,78204.0,108780.0,116644.0,117053.0] || -> . % 76.16/76.31 117064[85:Spt:117063.0,117058.0,117060.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.31 117065[85:Spt:117063.0,117058.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 117069[85:Res:117065.0,61.1] always3(s31) || -> . % 76.16/76.31 117070[85:SSi:117069.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.31 117071[83:Spt:117070.0,116643.0,116644.0] || until2p7(s30)*+ -> . % 76.16/76.31 117072[83:Spt:117070.0,116643.1] || -> node4(s29)*. % 76.16/76.31 117074[83:MRR:831.0,117072.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.31 117077[83:Res:53.1,117074.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.31 117079[84:Spt:117077.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 117081[84:Res:117079.0,61.1] always3(s29) || -> . % 76.16/76.31 117082[84:SSi:117081.0,78196.0,78199.0,108779.0,116642.0,117072.0] || -> . % 76.16/76.31 117083[84:Spt:117082.0,117077.0,117079.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.31 117084[84:Spt:117082.0,117077.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 117088[84:Res:117084.0,61.1] always3(s30) || -> . % 76.16/76.31 117089[84:SSi:117088.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.31 117090[82:Spt:117089.0,116641.0,116642.0] || until2p7(s29)*+ -> . % 76.16/76.31 117091[82:Spt:117089.0,116641.1] || -> node4(s28)*. % 76.16/76.31 117093[82:MRR:834.0,117091.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.31 117096[82:Res:53.1,117093.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.31 117098[83:Spt:117096.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.31 117100[83:Res:117098.0,61.1] always3(s28) || -> . % 76.16/76.31 117101[83:SSi:117100.0,78191.0,78195.0,108778.0,116640.0,117091.0] || -> . % 76.16/76.31 117102[83:Spt:117101.0,117096.0,117098.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.31 117103[83:Spt:117101.0,117096.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 117107[83:Res:117103.0,61.1] always3(s29) || -> . % 76.16/76.31 117108[83:SSi:117107.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.31 117109[81:Spt:117108.0,116639.0,116640.0] || until2p7(s28)*+ -> . % 76.16/76.31 117110[81:Spt:117108.0,116639.1] || -> node4(s27)*. % 76.16/76.31 117112[81:MRR:837.0,117110.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.31 117115[81:Res:53.1,117112.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.31 117120[82:Spt:117115.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.31 117122[82:Res:117120.0,61.1] always3(s27) || -> . % 76.16/76.31 117123[82:SSi:117122.0,78187.0,78190.0,108777.0,116638.0,117110.0] || -> . % 76.16/76.31 117124[82:Spt:117123.0,117115.0,117120.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.31 117125[82:Spt:117123.0,117115.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.31 117129[82:Res:117125.0,61.1] always3(s28) || -> . % 76.16/76.31 117130[82:SSi:117129.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.31 117131[80:Spt:117130.0,116637.0,116638.0] || until2p7(s27)*+ -> . % 76.16/76.31 117132[80:Spt:117130.0,116637.1] || -> node4(s26)*. % 76.16/76.31 117134[80:MRR:840.0,117132.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.31 117137[80:Res:53.1,117134.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.31 117139[81:Spt:117137.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.31 117141[81:Res:117139.0,61.1] always3(s26) || -> . % 76.16/76.31 117142[81:SSi:117141.0,78182.0,78186.0,108776.0,116636.0,117132.0] || -> . % 76.16/76.31 117143[81:Spt:117142.0,117137.0,117139.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.31 117144[81:Spt:117142.0,117137.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.31 117148[81:Res:117144.0,61.1] always3(s27) || -> . % 76.16/76.31 117149[81:SSi:117148.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.31 117150[79:Spt:117149.0,116635.0,116636.0] || until2p7(s26)*+ -> . % 76.16/76.31 117151[79:Spt:117149.0,116635.1] || -> node4(s25)*. % 76.16/76.31 117153[79:MRR:843.0,117151.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.31 117156[79:Res:53.1,117153.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.31 117158[79:MRR:117156.0,116625.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.31 117160[79:Res:117158.0,61.1] always3(s26) || -> . % 76.16/76.31 117161[79:SSi:117160.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.31 117162[77:Spt:117161.0,116528.0,116531.0] || trans(s49,s25)*+ -> . % 76.16/76.31 117163[77:Spt:117161.0,116528.1,116528.2,116528.3,116528.4,116528.5,116528.6,116528.7,116528.8,116528.9,116528.10,116528.11,116528.12,116528.13,116528.14,116528.15,116528.16,116528.17,116528.18,116528.19,116528.20,116528.21,116528.22] || -> trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.31 117165[77:MRR:116530.1,117162.0] xuntil6(s49) || -> trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.31 117166[78:Spt:117163.0] || -> trans(s49,s24)*. % 76.16/76.31 117167[78:Res:117166.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s24)*. % 76.16/76.31 117169[78:Res:117166.0,60.0] || -> node2(s49,s24)*. % 76.16/76.31 117170[78:SSi:117167.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s24)*. % 76.16/76.31 117171[78:Res:117169.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)*. % 76.16/76.31 117256[78:SoR:117171.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)*. % 76.16/76.31 117258[78:SoR:117256.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)* xuntil6(s49). % 76.16/76.31 117259[78:SSi:117258.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s24,c_busy)* xuntil6(s49). % 76.16/76.31 117260[79:Spt:117259.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.31 117262[79:Res:117260.0,61.1] always3(s24) || -> . % 76.16/76.31 117263[79:SSi:117262.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.31 117264[79:Spt:117263.0,117259.1,117260.0] || m_main_v_state(s24,c_busy)*+ -> . % 76.16/76.31 117265[79:Spt:117263.0,117259.0,117259.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.31 117269[79:MRR:117256.2,117264.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.31 117270[79:Res:53.1,117265.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.31 117272[79:MRR:117270.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.31 117273[79:MRR:117170.0,117272.0] || -> until2p7(s24)*. % 76.16/76.31 117274[79:MRR:220.0,117273.0] || -> until2p7(s25)* node4(s24). % 76.16/76.31 117275[80:Spt:117274.0] || -> until2p7(s25)*. % 76.16/76.31 117276[80:MRR:221.0,117275.0] || -> until2p7(s26)* node4(s25). % 76.16/76.31 117277[81:Spt:117276.0] || -> until2p7(s26)*. % 76.16/76.31 117278[81:MRR:222.0,117277.0] || -> until2p7(s27)* node4(s26). % 76.16/76.31 117279[82:Spt:117278.0] || -> until2p7(s27)*. % 76.16/76.31 117280[82:MRR:223.0,117279.0] || -> until2p7(s28)* node4(s27). % 76.16/76.31 117281[83:Spt:117280.0] || -> until2p7(s28)*. % 76.16/76.31 117282[83:MRR:224.0,117281.0] || -> until2p7(s29)* node4(s28). % 76.16/76.31 117283[84:Spt:117282.0] || -> until2p7(s29)*. % 76.16/76.31 117284[84:MRR:225.0,117283.0] || -> until2p7(s30)* node4(s29). % 76.16/76.31 117285[85:Spt:117284.0] || -> until2p7(s30)*. % 76.16/76.31 117286[85:MRR:226.0,117285.0] || -> until2p7(s31)* node4(s30). % 76.16/76.31 117287[86:Spt:117286.0] || -> until2p7(s31)*. % 76.16/76.31 117288[86:MRR:227.0,117287.0] || -> until2p7(s32)* node4(s31). % 76.16/76.31 117289[87:Spt:117288.0] || -> until2p7(s32)*. % 76.16/76.31 117290[87:MRR:228.0,117289.0] || -> until2p7(s33)* node4(s32). % 76.16/76.31 117291[88:Spt:117290.0] || -> until2p7(s33)*. % 76.16/76.31 117292[88:MRR:229.0,117291.0] || -> until2p7(s34)* node4(s33). % 76.16/76.31 117293[89:Spt:117292.0] || -> until2p7(s34)*. % 76.16/76.31 117294[89:MRR:230.0,117293.0] || -> until2p7(s35)* node4(s34). % 76.16/76.31 117295[90:Spt:117294.0] || -> until2p7(s35)*. % 76.16/76.31 117296[90:MRR:231.0,117295.0] || -> until2p7(s36)* node4(s35). % 76.16/76.31 117297[91:Spt:117296.0] || -> until2p7(s36)*. % 76.16/76.31 117298[91:MRR:232.0,117297.0] || -> until2p7(s37)* node4(s36). % 76.16/76.31 117299[92:Spt:117298.0] || -> until2p7(s37)*. % 76.16/76.31 117300[92:MRR:235.0,117299.0] || -> until2p7(s38)* node4(s37). % 76.16/76.31 117301[93:Spt:117300.0] || -> until2p7(s38)*. % 76.16/76.31 117302[93:MRR:236.0,117301.0] || -> until2p7(s39)* node4(s38). % 76.16/76.31 117303[94:Spt:117302.0] || -> until2p7(s39)*. % 76.16/76.31 117304[94:MRR:237.0,117303.0] || -> until2p7(s40)* node4(s39). % 76.16/76.31 117305[95:Spt:117304.0] || -> until2p7(s40)*. % 76.16/76.31 117306[95:MRR:238.0,117305.0] || -> until2p7(s41)* node4(s40). % 76.16/76.31 117307[96:Spt:117306.0] || -> until2p7(s41)*. % 76.16/76.31 117308[96:MRR:239.0,117307.0] || -> until2p7(s42)* node4(s41). % 76.16/76.31 117309[97:Spt:117308.0] || -> until2p7(s42)*. % 76.16/76.31 117310[97:MRR:240.0,117309.0] || -> until2p7(s43)* node4(s42). % 76.16/76.31 117311[98:Spt:117310.0] || -> until2p7(s43)*. % 76.16/76.31 117312[98:MRR:241.0,117311.0] || -> until2p7(s44)* node4(s43). % 76.16/76.31 117313[99:Spt:117312.0] || -> until2p7(s44)*. % 76.16/76.31 117314[99:MRR:539.0,117313.0] || -> until2p7(s45)* node4(s44). % 76.16/76.31 117315[100:Spt:117314.0] || -> until2p7(s45)*. % 76.16/76.31 117316[100:MRR:544.0,117315.0] || -> until2p7(s46)* node4(s45). % 76.16/76.31 117317[101:Spt:117316.0] || -> until2p7(s46)*. % 76.16/76.31 117318[101:MRR:549.0,117317.0] || -> until2p7(s47)* node4(s46). % 76.16/76.31 117319[102:Spt:117318.0] || -> until2p7(s47)*. % 76.16/76.31 117320[102:MRR:554.0,117319.0] || -> until2p7(s48)* node4(s47). % 76.16/76.31 117321[103:Spt:117320.0] || -> until2p7(s48)*. % 76.16/76.31 117322[103:MRR:559.0,117321.0] || -> until2p7(s49)* node4(s48). % 76.16/76.31 117323[104:Spt:117322.0] || -> until2p7(s49)*. % 76.16/76.31 117324[104:MRR:194.0,117323.0] || -> node4(s49)*. % 76.16/76.31 117325[104:MRR:117269.0,117324.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.31 117326[104:Res:53.1,117325.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.31 117328[104:MRR:117326.0,78381.0] || -> . % 76.16/76.31 117329[104:Spt:117328.0,117322.0,117323.0] || until2p7(s49)*+ -> . % 76.16/76.31 117330[104:Spt:117328.0,117322.1] || -> node4(s48)*. % 76.16/76.31 117331[104:MRR:78384.0,117330.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.31 117334[104:Res:53.1,117331.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 117337[104:Res:117334.0,61.1] always3(s48) || -> . % 76.16/76.31 117338[104:SSi:117337.0,78281.0,78387.0,108798.0,117321.0,117330.0] || -> . % 76.16/76.31 117339[103:Spt:117338.0,117320.0,117321.0] || until2p7(s48)*+ -> . % 76.16/76.31 117340[103:Spt:117338.0,117320.1] || -> node4(s47)*. % 76.16/76.31 117342[103:MRR:777.0,117340.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.31 117357[103:Res:53.1,117342.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.31 117359[104:Spt:117357.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 117361[104:Res:117359.0,61.1] always3(s47) || -> . % 76.16/76.31 117362[104:SSi:117361.0,78277.0,78280.0,108797.0,117319.0,117340.0] || -> . % 76.16/76.31 117363[104:Spt:117362.0,117357.0,117359.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.31 117364[104:Spt:117362.0,117357.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 117368[104:Res:117364.0,61.1] always3(s48) || -> . % 76.16/76.31 117369[104:SSi:117368.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.31 117370[102:Spt:117369.0,117318.0,117319.0] || until2p7(s47)*+ -> . % 76.16/76.31 117371[102:Spt:117369.0,117318.1] || -> node4(s46)*. % 76.16/76.31 117373[102:MRR:780.0,117371.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.31 117383[102:Res:53.1,117373.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.31 117385[103:Spt:117383.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 117387[103:Res:117385.0,61.1] always3(s46) || -> . % 76.16/76.31 117388[103:SSi:117387.0,78272.0,78276.0,108796.0,117317.0,117371.0] || -> . % 76.16/76.31 117389[103:Spt:117388.0,117383.0,117385.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.31 117390[103:Spt:117388.0,117383.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 117394[103:Res:117390.0,61.1] always3(s47) || -> . % 76.16/76.31 117395[103:SSi:117394.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.31 117396[101:Spt:117395.0,117316.0,117317.0] || until2p7(s46)*+ -> . % 76.16/76.31 117397[101:Spt:117395.0,117316.1] || -> node4(s45)*. % 76.16/76.31 117399[101:MRR:783.0,117397.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.31 117402[101:Res:53.1,117399.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.31 117404[102:Spt:117402.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 117406[102:Res:117404.0,61.1] always3(s45) || -> . % 76.16/76.31 117407[102:SSi:117406.0,78268.0,78271.0,108795.0,117315.0,117397.0] || -> . % 76.16/76.31 117408[102:Spt:117407.0,117402.0,117404.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.31 117409[102:Spt:117407.0,117402.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 117413[102:Res:117409.0,61.1] always3(s46) || -> . % 76.16/76.31 117414[102:SSi:117413.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.31 117415[100:Spt:117414.0,117314.0,117315.0] || until2p7(s45)*+ -> . % 76.16/76.31 117416[100:Spt:117414.0,117314.1] || -> node4(s44)*. % 76.16/76.31 117418[100:MRR:786.0,117416.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.31 117421[100:Res:53.1,117418.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.31 117423[101:Spt:117421.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 117425[101:Res:117423.0,61.1] always3(s44) || -> . % 76.16/76.31 117426[101:SSi:117425.0,78263.0,78267.0,108794.0,117313.0,117416.0] || -> . % 76.16/76.31 117427[101:Spt:117426.0,117421.0,117423.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.31 117428[101:Spt:117426.0,117421.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 117432[101:Res:117428.0,61.1] always3(s45) || -> . % 76.16/76.31 117433[101:SSi:117432.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.31 117434[99:Spt:117433.0,117312.0,117313.0] || until2p7(s44)*+ -> . % 76.16/76.31 117435[99:Spt:117433.0,117312.1] || -> node4(s43)*. % 76.16/76.31 117437[99:MRR:789.0,117435.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.31 117440[99:Res:53.1,117437.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.31 117445[100:Spt:117440.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 117447[100:Res:117445.0,61.1] always3(s43) || -> . % 76.16/76.31 117448[100:SSi:117447.0,78259.0,78262.0,108793.0,117311.0,117435.0] || -> . % 76.16/76.31 117449[100:Spt:117448.0,117440.0,117445.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.31 117450[100:Spt:117448.0,117440.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 117454[100:Res:117450.0,61.1] always3(s44) || -> . % 76.16/76.31 117455[100:SSi:117454.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.31 117456[98:Spt:117455.0,117310.0,117311.0] || until2p7(s43)*+ -> . % 76.16/76.31 117457[98:Spt:117455.0,117310.1] || -> node4(s42)*. % 76.16/76.31 117459[98:MRR:792.0,117457.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.31 117462[98:Res:53.1,117459.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.31 117464[99:Spt:117462.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 117466[99:Res:117464.0,61.1] always3(s42) || -> . % 76.16/76.31 117467[99:SSi:117466.0,78254.0,78258.0,108792.0,117309.0,117457.0] || -> . % 76.16/76.31 117468[99:Spt:117467.0,117462.0,117464.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.31 117469[99:Spt:117467.0,117462.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 117473[99:Res:117469.0,61.1] always3(s43) || -> . % 76.16/76.31 117474[99:SSi:117473.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.31 117475[97:Spt:117474.0,117308.0,117309.0] || until2p7(s42)*+ -> . % 76.16/76.31 117476[97:Spt:117474.0,117308.1] || -> node4(s41)*. % 76.16/76.31 117478[97:MRR:795.0,117476.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.31 117481[97:Res:53.1,117478.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.31 117483[98:Spt:117481.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 117485[98:Res:117483.0,61.1] always3(s41) || -> . % 76.16/76.31 117486[98:SSi:117485.0,78250.0,78253.0,108791.0,117307.0,117476.0] || -> . % 76.16/76.31 117487[98:Spt:117486.0,117481.0,117483.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.31 117488[98:Spt:117486.0,117481.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 117492[98:Res:117488.0,61.1] always3(s42) || -> . % 76.16/76.31 117493[98:SSi:117492.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.31 117494[96:Spt:117493.0,117306.0,117307.0] || until2p7(s41)*+ -> . % 76.16/76.31 117495[96:Spt:117493.0,117306.1] || -> node4(s40)*. % 76.16/76.31 117497[96:MRR:798.0,117495.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.31 117500[96:Res:53.1,117497.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.31 117502[97:Spt:117500.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.31 117504[97:Res:117502.0,61.1] always3(s40) || -> . % 76.16/76.31 117505[97:SSi:117504.0,78245.0,78249.0,108790.0,117305.0,117495.0] || -> . % 76.16/76.31 117506[97:Spt:117505.0,117500.0,117502.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.31 117507[97:Spt:117505.0,117500.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 117511[97:Res:117507.0,61.1] always3(s41) || -> . % 76.16/76.31 117512[97:SSi:117511.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.31 117513[95:Spt:117512.0,117304.0,117305.0] || until2p7(s40)*+ -> . % 76.16/76.31 117514[95:Spt:117512.0,117304.1] || -> node4(s39)*. % 76.16/76.31 117516[95:MRR:801.0,117514.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.31 117519[95:Res:53.1,117516.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.31 117524[96:Spt:117519.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.31 117526[96:Res:117524.0,61.1] always3(s39) || -> . % 76.16/76.31 117527[96:SSi:117526.0,78241.0,78244.0,108789.0,117303.0,117514.0] || -> . % 76.16/76.31 117528[96:Spt:117527.0,117519.0,117524.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.31 117529[96:Spt:117527.0,117519.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.31 117533[96:Res:117529.0,61.1] always3(s40) || -> . % 76.16/76.31 117534[96:SSi:117533.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.31 117535[94:Spt:117534.0,117302.0,117303.0] || until2p7(s39)*+ -> . % 76.16/76.31 117536[94:Spt:117534.0,117302.1] || -> node4(s38)*. % 76.16/76.31 117538[94:MRR:804.0,117536.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.31 117541[94:Res:53.1,117538.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.31 117543[95:Spt:117541.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.31 117545[95:Res:117543.0,61.1] always3(s38) || -> . % 76.16/76.31 117546[95:SSi:117545.0,78236.0,78240.0,108788.0,117301.0,117536.0] || -> . % 76.16/76.31 117547[95:Spt:117546.0,117541.0,117543.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.31 117548[95:Spt:117546.0,117541.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.31 117552[95:Res:117548.0,61.1] always3(s39) || -> . % 76.16/76.31 117553[95:SSi:117552.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.31 117554[93:Spt:117553.0,117300.0,117301.0] || until2p7(s38)*+ -> . % 76.16/76.31 117555[93:Spt:117553.0,117300.1] || -> node4(s37)*. % 76.16/76.31 117557[93:MRR:807.0,117555.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.31 117560[93:Res:53.1,117557.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.31 117562[94:Spt:117560.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.31 117564[94:Res:117562.0,61.1] always3(s37) || -> . % 76.16/76.31 117565[94:SSi:117564.0,78232.0,78235.0,108787.0,117299.0,117555.0] || -> . % 76.16/76.31 117566[94:Spt:117565.0,117560.0,117562.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.31 117567[94:Spt:117565.0,117560.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.31 117571[94:Res:117567.0,61.1] always3(s38) || -> . % 76.16/76.31 117572[94:SSi:117571.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.31 117573[92:Spt:117572.0,117298.0,117299.0] || until2p7(s37)*+ -> . % 76.16/76.31 117574[92:Spt:117572.0,117298.1] || -> node4(s36)*. % 76.16/76.31 117576[92:MRR:810.0,117574.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.31 117579[92:Res:53.1,117576.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.31 117581[93:Spt:117579.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.31 117583[93:Res:117581.0,61.1] always3(s36) || -> . % 76.16/76.31 117584[93:SSi:117583.0,78227.0,78231.0,108786.0,117297.0,117574.0] || -> . % 76.16/76.31 117585[93:Spt:117584.0,117579.0,117581.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.31 117586[93:Spt:117584.0,117579.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.31 117590[93:Res:117586.0,61.1] always3(s37) || -> . % 76.16/76.31 117591[93:SSi:117590.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.31 117592[91:Spt:117591.0,117296.0,117297.0] || until2p7(s36)*+ -> . % 76.16/76.31 117593[91:Spt:117591.0,117296.1] || -> node4(s35)*. % 76.16/76.31 117595[91:MRR:813.0,117593.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.31 117598[91:Res:53.1,117595.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.31 117603[92:Spt:117598.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 117605[92:Res:117603.0,61.1] always3(s35) || -> . % 76.16/76.31 117606[92:SSi:117605.0,78223.0,78226.0,108785.0,117295.0,117593.0] || -> . % 76.16/76.31 117607[92:Spt:117606.0,117598.0,117603.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.31 117608[92:Spt:117606.0,117598.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.31 117612[92:Res:117608.0,61.1] always3(s36) || -> . % 76.16/76.31 117613[92:SSi:117612.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.31 117614[90:Spt:117613.0,117294.0,117295.0] || until2p7(s35)*+ -> . % 76.16/76.31 117615[90:Spt:117613.0,117294.1] || -> node4(s34)*. % 76.16/76.31 117617[90:MRR:816.0,117615.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.31 117620[90:Res:53.1,117617.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.31 117622[91:Spt:117620.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 117624[91:Res:117622.0,61.1] always3(s34) || -> . % 76.16/76.31 117625[91:SSi:117624.0,78218.0,78222.0,108784.0,117293.0,117615.0] || -> . % 76.16/76.31 117626[91:Spt:117625.0,117620.0,117622.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.31 117627[91:Spt:117625.0,117620.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 117631[91:Res:117627.0,61.1] always3(s35) || -> . % 76.16/76.31 117632[91:SSi:117631.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.31 117633[89:Spt:117632.0,117292.0,117293.0] || until2p7(s34)*+ -> . % 76.16/76.31 117634[89:Spt:117632.0,117292.1] || -> node4(s33)*. % 76.16/76.31 117636[89:MRR:819.0,117634.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.31 117639[89:Res:53.1,117636.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.31 117641[90:Spt:117639.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 117643[90:Res:117641.0,61.1] always3(s33) || -> . % 76.16/76.31 117644[90:SSi:117643.0,78214.0,78217.0,108783.0,117291.0,117634.0] || -> . % 76.16/76.31 117645[90:Spt:117644.0,117639.0,117641.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.31 117646[90:Spt:117644.0,117639.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 117650[90:Res:117646.0,61.1] always3(s34) || -> . % 76.16/76.31 117651[90:SSi:117650.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.31 117652[88:Spt:117651.0,117290.0,117291.0] || until2p7(s33)*+ -> . % 76.16/76.31 117653[88:Spt:117651.0,117290.1] || -> node4(s32)*. % 76.16/76.31 117655[88:MRR:822.0,117653.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.31 117658[88:Res:53.1,117655.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.31 117660[89:Spt:117658.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 117662[89:Res:117660.0,61.1] always3(s32) || -> . % 76.16/76.31 117663[89:SSi:117662.0,78209.0,78213.0,108782.0,117289.0,117653.0] || -> . % 76.16/76.31 117664[89:Spt:117663.0,117658.0,117660.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.31 117665[89:Spt:117663.0,117658.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 117669[89:Res:117665.0,61.1] always3(s33) || -> . % 76.16/76.31 117670[89:SSi:117669.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.31 117671[87:Spt:117670.0,117288.0,117289.0] || until2p7(s32)*+ -> . % 76.16/76.31 117672[87:Spt:117670.0,117288.1] || -> node4(s31)*. % 76.16/76.31 117674[87:MRR:825.0,117672.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.31 117677[87:Res:53.1,117674.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.31 117682[88:Spt:117677.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 117684[88:Res:117682.0,61.1] always3(s31) || -> . % 76.16/76.31 117685[88:SSi:117684.0,78205.0,78208.0,108781.0,117287.0,117672.0] || -> . % 76.16/76.31 117686[88:Spt:117685.0,117677.0,117682.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.31 117687[88:Spt:117685.0,117677.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 117691[88:Res:117687.0,61.1] always3(s32) || -> . % 76.16/76.31 117692[88:SSi:117691.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.31 117693[86:Spt:117692.0,117286.0,117287.0] || until2p7(s31)*+ -> . % 76.16/76.31 117694[86:Spt:117692.0,117286.1] || -> node4(s30)*. % 76.16/76.31 117696[86:MRR:828.0,117694.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.31 117699[86:Res:53.1,117696.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.31 117701[87:Spt:117699.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 117703[87:Res:117701.0,61.1] always3(s30) || -> . % 76.16/76.31 117704[87:SSi:117703.0,78200.0,78204.0,108780.0,117285.0,117694.0] || -> . % 76.16/76.31 117705[87:Spt:117704.0,117699.0,117701.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.31 117706[87:Spt:117704.0,117699.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 117710[87:Res:117706.0,61.1] always3(s31) || -> . % 76.16/76.31 117711[87:SSi:117710.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.31 117712[85:Spt:117711.0,117284.0,117285.0] || until2p7(s30)*+ -> . % 76.16/76.31 117713[85:Spt:117711.0,117284.1] || -> node4(s29)*. % 76.16/76.31 117715[85:MRR:831.0,117713.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.31 117718[85:Res:53.1,117715.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.31 117720[86:Spt:117718.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 117722[86:Res:117720.0,61.1] always3(s29) || -> . % 76.16/76.31 117723[86:SSi:117722.0,78196.0,78199.0,108779.0,117283.0,117713.0] || -> . % 76.16/76.31 117724[86:Spt:117723.0,117718.0,117720.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.31 117725[86:Spt:117723.0,117718.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 117729[86:Res:117725.0,61.1] always3(s30) || -> . % 76.16/76.31 117730[86:SSi:117729.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.31 117731[84:Spt:117730.0,117282.0,117283.0] || until2p7(s29)*+ -> . % 76.16/76.31 117732[84:Spt:117730.0,117282.1] || -> node4(s28)*. % 76.16/76.31 117734[84:MRR:834.0,117732.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.31 117737[84:Res:53.1,117734.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.31 117739[85:Spt:117737.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.31 117741[85:Res:117739.0,61.1] always3(s28) || -> . % 76.16/76.31 117742[85:SSi:117741.0,78191.0,78195.0,108778.0,117281.0,117732.0] || -> . % 76.16/76.31 117743[85:Spt:117742.0,117737.0,117739.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.31 117744[85:Spt:117742.0,117737.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 117748[85:Res:117744.0,61.1] always3(s29) || -> . % 76.16/76.31 117749[85:SSi:117748.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.31 117750[83:Spt:117749.0,117280.0,117281.0] || until2p7(s28)*+ -> . % 76.16/76.31 117751[83:Spt:117749.0,117280.1] || -> node4(s27)*. % 76.16/76.31 117753[83:MRR:837.0,117751.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.31 117756[83:Res:53.1,117753.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.31 117761[84:Spt:117756.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.31 117763[84:Res:117761.0,61.1] always3(s27) || -> . % 76.16/76.31 117764[84:SSi:117763.0,78187.0,78190.0,108777.0,117279.0,117751.0] || -> . % 76.16/76.31 117765[84:Spt:117764.0,117756.0,117761.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.31 117766[84:Spt:117764.0,117756.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.31 117770[84:Res:117766.0,61.1] always3(s28) || -> . % 76.16/76.31 117771[84:SSi:117770.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.31 117772[82:Spt:117771.0,117278.0,117279.0] || until2p7(s27)*+ -> . % 76.16/76.31 117773[82:Spt:117771.0,117278.1] || -> node4(s26)*. % 76.16/76.31 117775[82:MRR:840.0,117773.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.31 117778[82:Res:53.1,117775.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.31 117780[83:Spt:117778.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.31 117782[83:Res:117780.0,61.1] always3(s26) || -> . % 76.16/76.31 117783[83:SSi:117782.0,78182.0,78186.0,108776.0,117277.0,117773.0] || -> . % 76.16/76.31 117784[83:Spt:117783.0,117778.0,117780.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.31 117785[83:Spt:117783.0,117778.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.31 117789[83:Res:117785.0,61.1] always3(s27) || -> . % 76.16/76.31 117790[83:SSi:117789.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.31 117791[81:Spt:117790.0,117276.0,117277.0] || until2p7(s26)*+ -> . % 76.16/76.31 117792[81:Spt:117790.0,117276.1] || -> node4(s25)*. % 76.16/76.31 117794[81:MRR:843.0,117792.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.31 117797[81:Res:53.1,117794.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.31 117799[82:Spt:117797.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.31 117801[82:Res:117799.0,61.1] always3(s25) || -> . % 76.16/76.31 117802[82:SSi:117801.0,78178.0,78181.0,108775.0,117275.0,117792.0] || -> . % 76.16/76.31 117803[82:Spt:117802.0,117797.0,117799.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.31 117804[82:Spt:117802.0,117797.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.31 117808[82:Res:117804.0,61.1] always3(s26) || -> . % 76.16/76.31 117809[82:SSi:117808.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.31 117810[80:Spt:117809.0,117274.0,117275.0] || until2p7(s25)*+ -> . % 76.16/76.31 117811[80:Spt:117809.0,117274.1] || -> node4(s24)*. % 76.16/76.31 117813[80:MRR:846.0,117811.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.31 117816[80:Res:53.1,117813.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.31 117818[80:MRR:117816.0,117264.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.31 117820[80:Res:117818.0,61.1] always3(s25) || -> . % 76.16/76.31 117821[80:SSi:117820.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.31 117822[78:Spt:117821.0,117163.0,117166.0] || trans(s49,s24)*+ -> . % 76.16/76.31 117823[78:Spt:117821.0,117163.1,117163.2,117163.3,117163.4,117163.5,117163.6,117163.7,117163.8,117163.9,117163.10,117163.11,117163.12,117163.13,117163.14,117163.15,117163.16,117163.17,117163.18,117163.19,117163.20,117163.21] || -> trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.31 117825[78:MRR:117165.1,117822.0] xuntil6(s49) || -> trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.31 117826[79:Spt:117823.0] || -> trans(s49,s23)*. % 76.16/76.31 117827[79:Res:117826.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s23)*. % 76.16/76.31 117829[79:Res:117826.0,60.0] || -> node2(s49,s23)*. % 76.16/76.31 117830[79:SSi:117827.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s23)*. % 76.16/76.31 117831[79:Res:117829.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)*. % 76.16/76.31 117920[79:SoR:117831.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)*. % 76.16/76.31 117922[79:SoR:117920.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)* xuntil6(s49). % 76.16/76.31 117923[79:SSi:117922.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s23,c_busy)* xuntil6(s49). % 76.16/76.31 117924[80:Spt:117923.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.31 117926[80:Res:117924.0,61.1] always3(s23) || -> . % 76.16/76.31 117927[80:SSi:117926.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.31 117928[80:Spt:117927.0,117923.1,117924.0] || m_main_v_state(s23,c_busy)*+ -> . % 76.16/76.31 117929[80:Spt:117927.0,117923.0,117923.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.31 117933[80:MRR:117920.2,117928.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.31 117934[80:Res:53.1,117929.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.31 117936[80:MRR:117934.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.31 117937[80:MRR:117830.0,117936.0] || -> until2p7(s23)*. % 76.16/76.31 117938[80:MRR:219.0,117937.0] || -> until2p7(s24)* node4(s23). % 76.16/76.31 117939[81:Spt:117938.0] || -> until2p7(s24)*. % 76.16/76.31 117940[81:MRR:220.0,117939.0] || -> until2p7(s25)* node4(s24). % 76.16/76.31 117941[82:Spt:117940.0] || -> until2p7(s25)*. % 76.16/76.31 117942[82:MRR:221.0,117941.0] || -> until2p7(s26)* node4(s25). % 76.16/76.31 117943[83:Spt:117942.0] || -> until2p7(s26)*. % 76.16/76.31 117944[83:MRR:222.0,117943.0] || -> until2p7(s27)* node4(s26). % 76.16/76.31 117945[84:Spt:117944.0] || -> until2p7(s27)*. % 76.16/76.31 117946[84:MRR:223.0,117945.0] || -> until2p7(s28)* node4(s27). % 76.16/76.31 117947[85:Spt:117946.0] || -> until2p7(s28)*. % 76.16/76.31 117948[85:MRR:224.0,117947.0] || -> until2p7(s29)* node4(s28). % 76.16/76.31 117949[86:Spt:117948.0] || -> until2p7(s29)*. % 76.16/76.31 117950[86:MRR:225.0,117949.0] || -> until2p7(s30)* node4(s29). % 76.16/76.31 117951[87:Spt:117950.0] || -> until2p7(s30)*. % 76.16/76.31 117952[87:MRR:226.0,117951.0] || -> until2p7(s31)* node4(s30). % 76.16/76.31 117953[88:Spt:117952.0] || -> until2p7(s31)*. % 76.16/76.31 117954[88:MRR:227.0,117953.0] || -> until2p7(s32)* node4(s31). % 76.16/76.31 117955[89:Spt:117954.0] || -> until2p7(s32)*. % 76.16/76.31 117956[89:MRR:228.0,117955.0] || -> until2p7(s33)* node4(s32). % 76.16/76.31 117957[90:Spt:117956.0] || -> until2p7(s33)*. % 76.16/76.31 117958[90:MRR:229.0,117957.0] || -> until2p7(s34)* node4(s33). % 76.16/76.31 117959[91:Spt:117958.0] || -> until2p7(s34)*. % 76.16/76.31 117960[91:MRR:230.0,117959.0] || -> until2p7(s35)* node4(s34). % 76.16/76.31 117961[92:Spt:117960.0] || -> until2p7(s35)*. % 76.16/76.31 117962[92:MRR:231.0,117961.0] || -> until2p7(s36)* node4(s35). % 76.16/76.31 117963[93:Spt:117962.0] || -> until2p7(s36)*. % 76.16/76.31 117964[93:MRR:232.0,117963.0] || -> until2p7(s37)* node4(s36). % 76.16/76.31 117965[94:Spt:117964.0] || -> until2p7(s37)*. % 76.16/76.31 117966[94:MRR:235.0,117965.0] || -> until2p7(s38)* node4(s37). % 76.16/76.31 117967[95:Spt:117966.0] || -> until2p7(s38)*. % 76.16/76.31 117968[95:MRR:236.0,117967.0] || -> until2p7(s39)* node4(s38). % 76.16/76.31 117969[96:Spt:117968.0] || -> until2p7(s39)*. % 76.16/76.31 117970[96:MRR:237.0,117969.0] || -> until2p7(s40)* node4(s39). % 76.16/76.31 117971[97:Spt:117970.0] || -> until2p7(s40)*. % 76.16/76.31 117972[97:MRR:238.0,117971.0] || -> until2p7(s41)* node4(s40). % 76.16/76.31 117973[98:Spt:117972.0] || -> until2p7(s41)*. % 76.16/76.31 117974[98:MRR:239.0,117973.0] || -> until2p7(s42)* node4(s41). % 76.16/76.31 117975[99:Spt:117974.0] || -> until2p7(s42)*. % 76.16/76.31 117976[99:MRR:240.0,117975.0] || -> until2p7(s43)* node4(s42). % 76.16/76.31 117977[100:Spt:117976.0] || -> until2p7(s43)*. % 76.16/76.31 117978[100:MRR:241.0,117977.0] || -> until2p7(s44)* node4(s43). % 76.16/76.31 117979[101:Spt:117978.0] || -> until2p7(s44)*. % 76.16/76.31 117980[101:MRR:539.0,117979.0] || -> until2p7(s45)* node4(s44). % 76.16/76.31 117981[102:Spt:117980.0] || -> until2p7(s45)*. % 76.16/76.31 117982[102:MRR:544.0,117981.0] || -> until2p7(s46)* node4(s45). % 76.16/76.31 117983[103:Spt:117982.0] || -> until2p7(s46)*. % 76.16/76.31 117984[103:MRR:549.0,117983.0] || -> until2p7(s47)* node4(s46). % 76.16/76.31 117985[104:Spt:117984.0] || -> until2p7(s47)*. % 76.16/76.31 117986[104:MRR:554.0,117985.0] || -> until2p7(s48)* node4(s47). % 76.16/76.31 117987[105:Spt:117986.0] || -> until2p7(s48)*. % 76.16/76.31 117988[105:MRR:559.0,117987.0] || -> until2p7(s49)* node4(s48). % 76.16/76.31 117989[106:Spt:117988.0] || -> until2p7(s49)*. % 76.16/76.31 117990[106:MRR:194.0,117989.0] || -> node4(s49)*. % 76.16/76.31 117991[106:MRR:117933.0,117990.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.31 117995[106:Res:53.1,117991.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.31 117997[106:MRR:117995.0,78381.0] || -> . % 76.16/76.31 117998[106:Spt:117997.0,117988.0,117989.0] || until2p7(s49)*+ -> . % 76.16/76.31 117999[106:Spt:117997.0,117988.1] || -> node4(s48)*. % 76.16/76.31 118000[106:MRR:78384.0,117999.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.31 118003[106:Res:53.1,118000.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 118006[106:Res:118003.0,61.1] always3(s48) || -> . % 76.16/76.31 118007[106:SSi:118006.0,78281.0,78387.0,108798.0,117987.0,117999.0] || -> . % 76.16/76.31 118008[105:Spt:118007.0,117986.0,117987.0] || until2p7(s48)*+ -> . % 76.16/76.31 118009[105:Spt:118007.0,117986.1] || -> node4(s47)*. % 76.16/76.31 118011[105:MRR:777.0,118009.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.31 118023[105:Res:53.1,118011.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.31 118025[106:Spt:118023.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 118027[106:Res:118025.0,61.1] always3(s47) || -> . % 76.16/76.31 118028[106:SSi:118027.0,78277.0,78280.0,108797.0,117985.0,118009.0] || -> . % 76.16/76.31 118029[106:Spt:118028.0,118023.0,118025.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.31 118030[106:Spt:118028.0,118023.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 118034[106:Res:118030.0,61.1] always3(s48) || -> . % 76.16/76.31 118035[106:SSi:118034.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.31 118036[104:Spt:118035.0,117984.0,117985.0] || until2p7(s47)*+ -> . % 76.16/76.31 118037[104:Spt:118035.0,117984.1] || -> node4(s46)*. % 76.16/76.31 118039[104:MRR:780.0,118037.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.31 118046[104:Res:53.1,118039.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.31 118051[105:Spt:118046.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 118053[105:Res:118051.0,61.1] always3(s46) || -> . % 76.16/76.31 118054[105:SSi:118053.0,78272.0,78276.0,108796.0,117983.0,118037.0] || -> . % 76.16/76.31 118055[105:Spt:118054.0,118046.0,118051.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.31 118056[105:Spt:118054.0,118046.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 118060[105:Res:118056.0,61.1] always3(s47) || -> . % 76.16/76.31 118061[105:SSi:118060.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.31 118062[103:Spt:118061.0,117982.0,117983.0] || until2p7(s46)*+ -> . % 76.16/76.31 118063[103:Spt:118061.0,117982.1] || -> node4(s45)*. % 76.16/76.31 118065[103:MRR:783.0,118063.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.31 118068[103:Res:53.1,118065.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.31 118070[104:Spt:118068.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 118072[104:Res:118070.0,61.1] always3(s45) || -> . % 76.16/76.31 118073[104:SSi:118072.0,78268.0,78271.0,108795.0,117981.0,118063.0] || -> . % 76.16/76.31 118074[104:Spt:118073.0,118068.0,118070.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.31 118075[104:Spt:118073.0,118068.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 118079[104:Res:118075.0,61.1] always3(s46) || -> . % 76.16/76.31 118080[104:SSi:118079.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.31 118081[102:Spt:118080.0,117980.0,117981.0] || until2p7(s45)*+ -> . % 76.16/76.31 118082[102:Spt:118080.0,117980.1] || -> node4(s44)*. % 76.16/76.31 118084[102:MRR:786.0,118082.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.31 118087[102:Res:53.1,118084.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.31 118089[103:Spt:118087.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 118091[103:Res:118089.0,61.1] always3(s44) || -> . % 76.16/76.31 118092[103:SSi:118091.0,78263.0,78267.0,108794.0,117979.0,118082.0] || -> . % 76.16/76.31 118093[103:Spt:118092.0,118087.0,118089.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.31 118094[103:Spt:118092.0,118087.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 118098[103:Res:118094.0,61.1] always3(s45) || -> . % 76.16/76.31 118099[103:SSi:118098.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.31 118100[101:Spt:118099.0,117978.0,117979.0] || until2p7(s44)*+ -> . % 76.16/76.31 118101[101:Spt:118099.0,117978.1] || -> node4(s43)*. % 76.16/76.31 118103[101:MRR:789.0,118101.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.31 118106[101:Res:53.1,118103.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.31 118108[102:Spt:118106.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 118110[102:Res:118108.0,61.1] always3(s43) || -> . % 76.16/76.31 118111[102:SSi:118110.0,78259.0,78262.0,108793.0,117977.0,118101.0] || -> . % 76.16/76.31 118112[102:Spt:118111.0,118106.0,118108.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.31 118113[102:Spt:118111.0,118106.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 118117[102:Res:118113.0,61.1] always3(s44) || -> . % 76.16/76.31 118118[102:SSi:118117.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.31 118119[100:Spt:118118.0,117976.0,117977.0] || until2p7(s43)*+ -> . % 76.16/76.31 118120[100:Spt:118118.0,117976.1] || -> node4(s42)*. % 76.16/76.31 118122[100:MRR:792.0,118120.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.31 118125[100:Res:53.1,118122.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.31 118130[101:Spt:118125.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 118132[101:Res:118130.0,61.1] always3(s42) || -> . % 76.16/76.31 118133[101:SSi:118132.0,78254.0,78258.0,108792.0,117975.0,118120.0] || -> . % 76.16/76.31 118134[101:Spt:118133.0,118125.0,118130.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.31 118135[101:Spt:118133.0,118125.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 118139[101:Res:118135.0,61.1] always3(s43) || -> . % 76.16/76.31 118140[101:SSi:118139.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.31 118141[99:Spt:118140.0,117974.0,117975.0] || until2p7(s42)*+ -> . % 76.16/76.31 118142[99:Spt:118140.0,117974.1] || -> node4(s41)*. % 76.16/76.31 118144[99:MRR:795.0,118142.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.31 118147[99:Res:53.1,118144.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.31 118149[100:Spt:118147.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 118151[100:Res:118149.0,61.1] always3(s41) || -> . % 76.16/76.31 118152[100:SSi:118151.0,78250.0,78253.0,108791.0,117973.0,118142.0] || -> . % 76.16/76.31 118153[100:Spt:118152.0,118147.0,118149.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.31 118154[100:Spt:118152.0,118147.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 118158[100:Res:118154.0,61.1] always3(s42) || -> . % 76.16/76.31 118159[100:SSi:118158.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.31 118160[98:Spt:118159.0,117972.0,117973.0] || until2p7(s41)*+ -> . % 76.16/76.31 118161[98:Spt:118159.0,117972.1] || -> node4(s40)*. % 76.16/76.31 118163[98:MRR:798.0,118161.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.31 118166[98:Res:53.1,118163.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.31 118168[99:Spt:118166.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.31 118170[99:Res:118168.0,61.1] always3(s40) || -> . % 76.16/76.31 118171[99:SSi:118170.0,78245.0,78249.0,108790.0,117971.0,118161.0] || -> . % 76.16/76.31 118172[99:Spt:118171.0,118166.0,118168.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.31 118173[99:Spt:118171.0,118166.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 118177[99:Res:118173.0,61.1] always3(s41) || -> . % 76.16/76.31 118178[99:SSi:118177.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.31 118179[97:Spt:118178.0,117970.0,117971.0] || until2p7(s40)*+ -> . % 76.16/76.31 118180[97:Spt:118178.0,117970.1] || -> node4(s39)*. % 76.16/76.31 118182[97:MRR:801.0,118180.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.31 118185[97:Res:53.1,118182.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.31 118187[98:Spt:118185.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.31 118189[98:Res:118187.0,61.1] always3(s39) || -> . % 76.16/76.31 118190[98:SSi:118189.0,78241.0,78244.0,108789.0,117969.0,118180.0] || -> . % 76.16/76.31 118191[98:Spt:118190.0,118185.0,118187.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.31 118192[98:Spt:118190.0,118185.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.31 118196[98:Res:118192.0,61.1] always3(s40) || -> . % 76.16/76.31 118197[98:SSi:118196.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.31 118198[96:Spt:118197.0,117968.0,117969.0] || until2p7(s39)*+ -> . % 76.16/76.31 118199[96:Spt:118197.0,117968.1] || -> node4(s38)*. % 76.16/76.31 118201[96:MRR:804.0,118199.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.31 118204[96:Res:53.1,118201.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.31 118209[97:Spt:118204.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.31 118211[97:Res:118209.0,61.1] always3(s38) || -> . % 76.16/76.31 118212[97:SSi:118211.0,78236.0,78240.0,108788.0,117967.0,118199.0] || -> . % 76.16/76.31 118213[97:Spt:118212.0,118204.0,118209.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.31 118214[97:Spt:118212.0,118204.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.31 118218[97:Res:118214.0,61.1] always3(s39) || -> . % 76.16/76.31 118219[97:SSi:118218.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.31 118220[95:Spt:118219.0,117966.0,117967.0] || until2p7(s38)*+ -> . % 76.16/76.31 118221[95:Spt:118219.0,117966.1] || -> node4(s37)*. % 76.16/76.31 118223[95:MRR:807.0,118221.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.31 118226[95:Res:53.1,118223.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.31 118228[96:Spt:118226.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.31 118230[96:Res:118228.0,61.1] always3(s37) || -> . % 76.16/76.31 118231[96:SSi:118230.0,78232.0,78235.0,108787.0,117965.0,118221.0] || -> . % 76.16/76.31 118232[96:Spt:118231.0,118226.0,118228.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.31 118233[96:Spt:118231.0,118226.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.31 118237[96:Res:118233.0,61.1] always3(s38) || -> . % 76.16/76.31 118238[96:SSi:118237.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.31 118239[94:Spt:118238.0,117964.0,117965.0] || until2p7(s37)*+ -> . % 76.16/76.31 118240[94:Spt:118238.0,117964.1] || -> node4(s36)*. % 76.16/76.31 118242[94:MRR:810.0,118240.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.31 118245[94:Res:53.1,118242.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.31 118247[95:Spt:118245.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.31 118249[95:Res:118247.0,61.1] always3(s36) || -> . % 76.16/76.31 118250[95:SSi:118249.0,78227.0,78231.0,108786.0,117963.0,118240.0] || -> . % 76.16/76.31 118251[95:Spt:118250.0,118245.0,118247.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.31 118252[95:Spt:118250.0,118245.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.31 118256[95:Res:118252.0,61.1] always3(s37) || -> . % 76.16/76.31 118257[95:SSi:118256.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.31 118258[93:Spt:118257.0,117962.0,117963.0] || until2p7(s36)*+ -> . % 76.16/76.31 118259[93:Spt:118257.0,117962.1] || -> node4(s35)*. % 76.16/76.31 118261[93:MRR:813.0,118259.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.31 118264[93:Res:53.1,118261.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.31 118266[94:Spt:118264.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 118268[94:Res:118266.0,61.1] always3(s35) || -> . % 76.16/76.31 118269[94:SSi:118268.0,78223.0,78226.0,108785.0,117961.0,118259.0] || -> . % 76.16/76.31 118270[94:Spt:118269.0,118264.0,118266.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.31 118271[94:Spt:118269.0,118264.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.31 118275[94:Res:118271.0,61.1] always3(s36) || -> . % 76.16/76.31 118276[94:SSi:118275.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.31 118277[92:Spt:118276.0,117960.0,117961.0] || until2p7(s35)*+ -> . % 76.16/76.31 118278[92:Spt:118276.0,117960.1] || -> node4(s34)*. % 76.16/76.31 118280[92:MRR:816.0,118278.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.31 118283[92:Res:53.1,118280.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.31 118288[93:Spt:118283.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 118290[93:Res:118288.0,61.1] always3(s34) || -> . % 76.16/76.31 118291[93:SSi:118290.0,78218.0,78222.0,108784.0,117959.0,118278.0] || -> . % 76.16/76.31 118292[93:Spt:118291.0,118283.0,118288.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.31 118293[93:Spt:118291.0,118283.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 118297[93:Res:118293.0,61.1] always3(s35) || -> . % 76.16/76.31 118298[93:SSi:118297.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.31 118299[91:Spt:118298.0,117958.0,117959.0] || until2p7(s34)*+ -> . % 76.16/76.31 118300[91:Spt:118298.0,117958.1] || -> node4(s33)*. % 76.16/76.31 118302[91:MRR:819.0,118300.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.31 118305[91:Res:53.1,118302.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.31 118307[92:Spt:118305.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 118309[92:Res:118307.0,61.1] always3(s33) || -> . % 76.16/76.31 118310[92:SSi:118309.0,78214.0,78217.0,108783.0,117957.0,118300.0] || -> . % 76.16/76.31 118311[92:Spt:118310.0,118305.0,118307.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.31 118312[92:Spt:118310.0,118305.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 118316[92:Res:118312.0,61.1] always3(s34) || -> . % 76.16/76.31 118317[92:SSi:118316.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.31 118318[90:Spt:118317.0,117956.0,117957.0] || until2p7(s33)*+ -> . % 76.16/76.31 118319[90:Spt:118317.0,117956.1] || -> node4(s32)*. % 76.16/76.31 118321[90:MRR:822.0,118319.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.31 118324[90:Res:53.1,118321.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.31 118326[91:Spt:118324.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 118328[91:Res:118326.0,61.1] always3(s32) || -> . % 76.16/76.31 118329[91:SSi:118328.0,78209.0,78213.0,108782.0,117955.0,118319.0] || -> . % 76.16/76.31 118330[91:Spt:118329.0,118324.0,118326.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.31 118331[91:Spt:118329.0,118324.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 118335[91:Res:118331.0,61.1] always3(s33) || -> . % 76.16/76.31 118336[91:SSi:118335.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.31 118337[89:Spt:118336.0,117954.0,117955.0] || until2p7(s32)*+ -> . % 76.16/76.31 118338[89:Spt:118336.0,117954.1] || -> node4(s31)*. % 76.16/76.31 118340[89:MRR:825.0,118338.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.31 118343[89:Res:53.1,118340.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.31 118345[90:Spt:118343.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 118347[90:Res:118345.0,61.1] always3(s31) || -> . % 76.16/76.31 118348[90:SSi:118347.0,78205.0,78208.0,108781.0,117953.0,118338.0] || -> . % 76.16/76.31 118349[90:Spt:118348.0,118343.0,118345.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.31 118350[90:Spt:118348.0,118343.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 118354[90:Res:118350.0,61.1] always3(s32) || -> . % 76.16/76.31 118355[90:SSi:118354.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.31 118356[88:Spt:118355.0,117952.0,117953.0] || until2p7(s31)*+ -> . % 76.16/76.31 118357[88:Spt:118355.0,117952.1] || -> node4(s30)*. % 76.16/76.31 118359[88:MRR:828.0,118357.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.31 118362[88:Res:53.1,118359.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.31 118367[89:Spt:118362.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 118369[89:Res:118367.0,61.1] always3(s30) || -> . % 76.16/76.31 118370[89:SSi:118369.0,78200.0,78204.0,108780.0,117951.0,118357.0] || -> . % 76.16/76.31 118371[89:Spt:118370.0,118362.0,118367.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.31 118372[89:Spt:118370.0,118362.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 118376[89:Res:118372.0,61.1] always3(s31) || -> . % 76.16/76.31 118377[89:SSi:118376.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.31 118378[87:Spt:118377.0,117950.0,117951.0] || until2p7(s30)*+ -> . % 76.16/76.31 118379[87:Spt:118377.0,117950.1] || -> node4(s29)*. % 76.16/76.31 118381[87:MRR:831.0,118379.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.31 118384[87:Res:53.1,118381.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.31 118386[88:Spt:118384.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 118388[88:Res:118386.0,61.1] always3(s29) || -> . % 76.16/76.31 118389[88:SSi:118388.0,78196.0,78199.0,108779.0,117949.0,118379.0] || -> . % 76.16/76.31 118390[88:Spt:118389.0,118384.0,118386.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.31 118391[88:Spt:118389.0,118384.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 118395[88:Res:118391.0,61.1] always3(s30) || -> . % 76.16/76.31 118396[88:SSi:118395.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.31 118397[86:Spt:118396.0,117948.0,117949.0] || until2p7(s29)*+ -> . % 76.16/76.31 118398[86:Spt:118396.0,117948.1] || -> node4(s28)*. % 76.16/76.31 118400[86:MRR:834.0,118398.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.31 118403[86:Res:53.1,118400.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.31 118405[87:Spt:118403.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.31 118407[87:Res:118405.0,61.1] always3(s28) || -> . % 76.16/76.31 118408[87:SSi:118407.0,78191.0,78195.0,108778.0,117947.0,118398.0] || -> . % 76.16/76.31 118409[87:Spt:118408.0,118403.0,118405.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.31 118410[87:Spt:118408.0,118403.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 118414[87:Res:118410.0,61.1] always3(s29) || -> . % 76.16/76.31 118415[87:SSi:118414.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.31 118416[85:Spt:118415.0,117946.0,117947.0] || until2p7(s28)*+ -> . % 76.16/76.31 118417[85:Spt:118415.0,117946.1] || -> node4(s27)*. % 76.16/76.31 118419[85:MRR:837.0,118417.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.31 118422[85:Res:53.1,118419.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.31 118424[86:Spt:118422.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.31 118426[86:Res:118424.0,61.1] always3(s27) || -> . % 76.16/76.31 118427[86:SSi:118426.0,78187.0,78190.0,108777.0,117945.0,118417.0] || -> . % 76.16/76.31 118428[86:Spt:118427.0,118422.0,118424.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.31 118429[86:Spt:118427.0,118422.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.31 118433[86:Res:118429.0,61.1] always3(s28) || -> . % 76.16/76.31 118434[86:SSi:118433.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.31 118435[84:Spt:118434.0,117944.0,117945.0] || until2p7(s27)*+ -> . % 76.16/76.31 118436[84:Spt:118434.0,117944.1] || -> node4(s26)*. % 76.16/76.31 118438[84:MRR:840.0,118436.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.31 118441[84:Res:53.1,118438.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.31 118446[85:Spt:118441.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.31 118448[85:Res:118446.0,61.1] always3(s26) || -> . % 76.16/76.31 118449[85:SSi:118448.0,78182.0,78186.0,108776.0,117943.0,118436.0] || -> . % 76.16/76.31 118450[85:Spt:118449.0,118441.0,118446.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.31 118451[85:Spt:118449.0,118441.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.31 118455[85:Res:118451.0,61.1] always3(s27) || -> . % 76.16/76.31 118456[85:SSi:118455.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.31 118457[83:Spt:118456.0,117942.0,117943.0] || until2p7(s26)*+ -> . % 76.16/76.31 118458[83:Spt:118456.0,117942.1] || -> node4(s25)*. % 76.16/76.31 118460[83:MRR:843.0,118458.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.31 118463[83:Res:53.1,118460.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.31 118465[84:Spt:118463.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.31 118467[84:Res:118465.0,61.1] always3(s25) || -> . % 76.16/76.31 118468[84:SSi:118467.0,78178.0,78181.0,108775.0,117941.0,118458.0] || -> . % 76.16/76.31 118469[84:Spt:118468.0,118463.0,118465.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.31 118470[84:Spt:118468.0,118463.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.31 118474[84:Res:118470.0,61.1] always3(s26) || -> . % 76.16/76.31 118475[84:SSi:118474.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.31 118476[82:Spt:118475.0,117940.0,117941.0] || until2p7(s25)*+ -> . % 76.16/76.31 118477[82:Spt:118475.0,117940.1] || -> node4(s24)*. % 76.16/76.31 118479[82:MRR:846.0,118477.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.31 118482[82:Res:53.1,118479.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.31 118484[83:Spt:118482.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.31 118486[83:Res:118484.0,61.1] always3(s24) || -> . % 76.16/76.31 118487[83:SSi:118486.0,78173.0,78177.0,108774.0,117939.0,118477.0] || -> . % 76.16/76.31 118488[83:Spt:118487.0,118482.0,118484.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.31 118489[83:Spt:118487.0,118482.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.31 118493[83:Res:118489.0,61.1] always3(s25) || -> . % 76.16/76.31 118494[83:SSi:118493.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.31 118495[81:Spt:118494.0,117938.0,117939.0] || until2p7(s24)*+ -> . % 76.16/76.31 118496[81:Spt:118494.0,117938.1] || -> node4(s23)*. % 76.16/76.31 118498[81:MRR:849.0,118496.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.31 118501[81:Res:53.1,118498.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.31 118503[81:MRR:118501.0,117928.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.31 118505[81:Res:118503.0,61.1] always3(s24) || -> . % 76.16/76.31 118506[81:SSi:118505.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.31 118507[79:Spt:118506.0,117823.0,117826.0] || trans(s49,s23)*+ -> . % 76.16/76.31 118508[79:Spt:118506.0,117823.1,117823.2,117823.3,117823.4,117823.5,117823.6,117823.7,117823.8,117823.9,117823.10,117823.11,117823.12,117823.13,117823.14,117823.15,117823.16,117823.17,117823.18,117823.19,117823.20] || -> trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.31 118510[79:MRR:117825.1,118507.0] xuntil6(s49) || -> trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.31 118511[80:Spt:118508.0] || -> trans(s49,s22)*. % 76.16/76.31 118512[80:Res:118511.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s22)*. % 76.16/76.31 118514[80:Res:118511.0,60.0] || -> node2(s49,s22)*. % 76.16/76.31 118515[80:SSi:118512.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s22)*. % 76.16/76.31 118516[80:Res:118514.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)*. % 76.16/76.31 118609[80:SoR:118516.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)*. % 76.16/76.31 118611[80:SoR:118609.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)* xuntil6(s49). % 76.16/76.31 118612[80:SSi:118611.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s22,c_busy)* xuntil6(s49). % 76.16/76.31 118613[81:Spt:118612.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.31 118615[81:Res:118613.0,61.1] always3(s22) || -> . % 76.16/76.31 118616[81:SSi:118615.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.31 118617[81:Spt:118616.0,118612.1,118613.0] || m_main_v_state(s22,c_busy)*+ -> . % 76.16/76.31 118618[81:Spt:118616.0,118612.0,118612.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.31 118622[81:MRR:118609.2,118617.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.31 118623[81:Res:53.1,118618.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.31 118625[81:MRR:118623.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.31 118626[81:MRR:118515.0,118625.0] || -> until2p7(s22)*. % 76.16/76.31 118627[81:MRR:218.0,118626.0] || -> until2p7(s23)* node4(s22). % 76.16/76.31 118628[82:Spt:118627.0] || -> until2p7(s23)*. % 76.16/76.31 118629[82:MRR:219.0,118628.0] || -> until2p7(s24)* node4(s23). % 76.16/76.31 118630[83:Spt:118629.0] || -> until2p7(s24)*. % 76.16/76.31 118631[83:MRR:220.0,118630.0] || -> until2p7(s25)* node4(s24). % 76.16/76.31 118632[84:Spt:118631.0] || -> until2p7(s25)*. % 76.16/76.31 118633[84:MRR:221.0,118632.0] || -> until2p7(s26)* node4(s25). % 76.16/76.31 118634[85:Spt:118633.0] || -> until2p7(s26)*. % 76.16/76.31 118635[85:MRR:222.0,118634.0] || -> until2p7(s27)* node4(s26). % 76.16/76.31 118636[86:Spt:118635.0] || -> until2p7(s27)*. % 76.16/76.31 118637[86:MRR:223.0,118636.0] || -> until2p7(s28)* node4(s27). % 76.16/76.31 118638[87:Spt:118637.0] || -> until2p7(s28)*. % 76.16/76.31 118639[87:MRR:224.0,118638.0] || -> until2p7(s29)* node4(s28). % 76.16/76.31 118640[88:Spt:118639.0] || -> until2p7(s29)*. % 76.16/76.31 118641[88:MRR:225.0,118640.0] || -> until2p7(s30)* node4(s29). % 76.16/76.31 118642[89:Spt:118641.0] || -> until2p7(s30)*. % 76.16/76.31 118643[89:MRR:226.0,118642.0] || -> until2p7(s31)* node4(s30). % 76.16/76.31 118644[90:Spt:118643.0] || -> until2p7(s31)*. % 76.16/76.31 118645[90:MRR:227.0,118644.0] || -> until2p7(s32)* node4(s31). % 76.16/76.31 118646[91:Spt:118645.0] || -> until2p7(s32)*. % 76.16/76.31 118647[91:MRR:228.0,118646.0] || -> until2p7(s33)* node4(s32). % 76.16/76.31 118648[92:Spt:118647.0] || -> until2p7(s33)*. % 76.16/76.31 118649[92:MRR:229.0,118648.0] || -> until2p7(s34)* node4(s33). % 76.16/76.31 118650[93:Spt:118649.0] || -> until2p7(s34)*. % 76.16/76.31 118651[93:MRR:230.0,118650.0] || -> until2p7(s35)* node4(s34). % 76.16/76.31 118652[94:Spt:118651.0] || -> until2p7(s35)*. % 76.16/76.31 118653[94:MRR:231.0,118652.0] || -> until2p7(s36)* node4(s35). % 76.16/76.31 118654[95:Spt:118653.0] || -> until2p7(s36)*. % 76.16/76.31 118655[95:MRR:232.0,118654.0] || -> until2p7(s37)* node4(s36). % 76.16/76.31 118656[96:Spt:118655.0] || -> until2p7(s37)*. % 76.16/76.31 118657[96:MRR:235.0,118656.0] || -> until2p7(s38)* node4(s37). % 76.16/76.31 118658[97:Spt:118657.0] || -> until2p7(s38)*. % 76.16/76.31 118659[97:MRR:236.0,118658.0] || -> until2p7(s39)* node4(s38). % 76.16/76.31 118660[98:Spt:118659.0] || -> until2p7(s39)*. % 76.16/76.31 118661[98:MRR:237.0,118660.0] || -> until2p7(s40)* node4(s39). % 76.16/76.31 118662[99:Spt:118661.0] || -> until2p7(s40)*. % 76.16/76.31 118663[99:MRR:238.0,118662.0] || -> until2p7(s41)* node4(s40). % 76.16/76.31 118664[100:Spt:118663.0] || -> until2p7(s41)*. % 76.16/76.31 118665[100:MRR:239.0,118664.0] || -> until2p7(s42)* node4(s41). % 76.16/76.31 118666[101:Spt:118665.0] || -> until2p7(s42)*. % 76.16/76.31 118667[101:MRR:240.0,118666.0] || -> until2p7(s43)* node4(s42). % 76.16/76.31 118668[102:Spt:118667.0] || -> until2p7(s43)*. % 76.16/76.31 118669[102:MRR:241.0,118668.0] || -> until2p7(s44)* node4(s43). % 76.16/76.31 118670[103:Spt:118669.0] || -> until2p7(s44)*. % 76.16/76.31 118671[103:MRR:539.0,118670.0] || -> until2p7(s45)* node4(s44). % 76.16/76.31 118672[104:Spt:118671.0] || -> until2p7(s45)*. % 76.16/76.31 118673[104:MRR:544.0,118672.0] || -> until2p7(s46)* node4(s45). % 76.16/76.31 118674[105:Spt:118673.0] || -> until2p7(s46)*. % 76.16/76.31 118675[105:MRR:549.0,118674.0] || -> until2p7(s47)* node4(s46). % 76.16/76.31 118676[106:Spt:118675.0] || -> until2p7(s47)*. % 76.16/76.31 118677[106:MRR:554.0,118676.0] || -> until2p7(s48)* node4(s47). % 76.16/76.31 118678[107:Spt:118677.0] || -> until2p7(s48)*. % 76.16/76.31 118679[107:MRR:559.0,118678.0] || -> until2p7(s49)* node4(s48). % 76.16/76.31 118680[108:Spt:118679.0] || -> until2p7(s49)*. % 76.16/76.31 118681[108:MRR:194.0,118680.0] || -> node4(s49)*. % 76.16/76.31 118682[108:MRR:118622.0,118681.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.31 118683[108:Res:53.1,118682.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.31 118685[108:MRR:118683.0,78381.0] || -> . % 76.16/76.31 118686[108:Spt:118685.0,118679.0,118680.0] || until2p7(s49)*+ -> . % 76.16/76.31 118687[108:Spt:118685.0,118679.1] || -> node4(s48)*. % 76.16/76.31 118688[108:MRR:78384.0,118687.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.31 118691[108:Res:53.1,118688.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 118694[108:Res:118691.0,61.1] always3(s48) || -> . % 76.16/76.31 118695[108:SSi:118694.0,78281.0,78387.0,108798.0,118678.0,118687.0] || -> . % 76.16/76.31 118696[107:Spt:118695.0,118677.0,118678.0] || until2p7(s48)*+ -> . % 76.16/76.31 118697[107:Spt:118695.0,118677.1] || -> node4(s47)*. % 76.16/76.31 118699[107:MRR:777.0,118697.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.31 118714[107:Res:53.1,118699.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.31 118719[108:Spt:118714.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 118721[108:Res:118719.0,61.1] always3(s47) || -> . % 76.16/76.31 118722[108:SSi:118721.0,78277.0,78280.0,108797.0,118676.0,118697.0] || -> . % 76.16/76.31 118723[108:Spt:118722.0,118714.0,118719.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.31 118724[108:Spt:118722.0,118714.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 118728[108:Res:118724.0,61.1] always3(s48) || -> . % 76.16/76.31 118729[108:SSi:118728.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.31 118730[106:Spt:118729.0,118675.0,118676.0] || until2p7(s47)*+ -> . % 76.16/76.31 118731[106:Spt:118729.0,118675.1] || -> node4(s46)*. % 76.16/76.31 118733[106:MRR:780.0,118731.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.31 118740[106:Res:53.1,118733.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.31 118742[107:Spt:118740.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 118744[107:Res:118742.0,61.1] always3(s46) || -> . % 76.16/76.31 118745[107:SSi:118744.0,78272.0,78276.0,108796.0,118674.0,118731.0] || -> . % 76.16/76.31 118746[107:Spt:118745.0,118740.0,118742.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.31 118747[107:Spt:118745.0,118740.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 118751[107:Res:118747.0,61.1] always3(s47) || -> . % 76.16/76.31 118752[107:SSi:118751.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.31 118753[105:Spt:118752.0,118673.0,118674.0] || until2p7(s46)*+ -> . % 76.16/76.31 118754[105:Spt:118752.0,118673.1] || -> node4(s45)*. % 76.16/76.31 118756[105:MRR:783.0,118754.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.31 118759[105:Res:53.1,118756.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.31 118764[106:Spt:118759.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 118766[106:Res:118764.0,61.1] always3(s45) || -> . % 76.16/76.31 118767[106:SSi:118766.0,78268.0,78271.0,108795.0,118672.0,118754.0] || -> . % 76.16/76.31 118768[106:Spt:118767.0,118759.0,118764.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.31 118769[106:Spt:118767.0,118759.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 118773[106:Res:118769.0,61.1] always3(s46) || -> . % 76.16/76.31 118774[106:SSi:118773.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.31 118775[104:Spt:118774.0,118671.0,118672.0] || until2p7(s45)*+ -> . % 76.16/76.31 118776[104:Spt:118774.0,118671.1] || -> node4(s44)*. % 76.16/76.31 118778[104:MRR:786.0,118776.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.31 118781[104:Res:53.1,118778.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.31 118783[105:Spt:118781.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 118785[105:Res:118783.0,61.1] always3(s44) || -> . % 76.16/76.31 118786[105:SSi:118785.0,78263.0,78267.0,108794.0,118670.0,118776.0] || -> . % 76.16/76.31 118787[105:Spt:118786.0,118781.0,118783.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.31 118788[105:Spt:118786.0,118781.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 118792[105:Res:118788.0,61.1] always3(s45) || -> . % 76.16/76.31 118793[105:SSi:118792.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.31 118794[103:Spt:118793.0,118669.0,118670.0] || until2p7(s44)*+ -> . % 76.16/76.31 118795[103:Spt:118793.0,118669.1] || -> node4(s43)*. % 76.16/76.31 118797[103:MRR:789.0,118795.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.31 118800[103:Res:53.1,118797.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.31 118802[104:Spt:118800.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 118804[104:Res:118802.0,61.1] always3(s43) || -> . % 76.16/76.31 118805[104:SSi:118804.0,78259.0,78262.0,108793.0,118668.0,118795.0] || -> . % 76.16/76.31 118806[104:Spt:118805.0,118800.0,118802.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.31 118807[104:Spt:118805.0,118800.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 118811[104:Res:118807.0,61.1] always3(s44) || -> . % 76.16/76.31 118812[104:SSi:118811.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.31 118813[102:Spt:118812.0,118667.0,118668.0] || until2p7(s43)*+ -> . % 76.16/76.31 118814[102:Spt:118812.0,118667.1] || -> node4(s42)*. % 76.16/76.31 118816[102:MRR:792.0,118814.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.31 118819[102:Res:53.1,118816.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.31 118821[103:Spt:118819.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 118823[103:Res:118821.0,61.1] always3(s42) || -> . % 76.16/76.31 118824[103:SSi:118823.0,78254.0,78258.0,108792.0,118666.0,118814.0] || -> . % 76.16/76.31 118825[103:Spt:118824.0,118819.0,118821.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.31 118826[103:Spt:118824.0,118819.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 118830[103:Res:118826.0,61.1] always3(s43) || -> . % 76.16/76.31 118831[103:SSi:118830.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.31 118832[101:Spt:118831.0,118665.0,118666.0] || until2p7(s42)*+ -> . % 76.16/76.31 118833[101:Spt:118831.0,118665.1] || -> node4(s41)*. % 76.16/76.31 118835[101:MRR:795.0,118833.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.31 118838[101:Res:53.1,118835.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.31 118843[102:Spt:118838.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 118845[102:Res:118843.0,61.1] always3(s41) || -> . % 76.16/76.31 118846[102:SSi:118845.0,78250.0,78253.0,108791.0,118664.0,118833.0] || -> . % 76.16/76.31 118847[102:Spt:118846.0,118838.0,118843.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.31 118848[102:Spt:118846.0,118838.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 118852[102:Res:118848.0,61.1] always3(s42) || -> . % 76.16/76.31 118853[102:SSi:118852.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.31 118854[100:Spt:118853.0,118663.0,118664.0] || until2p7(s41)*+ -> . % 76.16/76.31 118855[100:Spt:118853.0,118663.1] || -> node4(s40)*. % 76.16/76.31 118857[100:MRR:798.0,118855.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.31 118860[100:Res:53.1,118857.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.31 118862[101:Spt:118860.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.31 118864[101:Res:118862.0,61.1] always3(s40) || -> . % 76.16/76.31 118865[101:SSi:118864.0,78245.0,78249.0,108790.0,118662.0,118855.0] || -> . % 76.16/76.31 118866[101:Spt:118865.0,118860.0,118862.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.31 118867[101:Spt:118865.0,118860.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 118871[101:Res:118867.0,61.1] always3(s41) || -> . % 76.16/76.31 118872[101:SSi:118871.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.31 118873[99:Spt:118872.0,118661.0,118662.0] || until2p7(s40)*+ -> . % 76.16/76.31 118874[99:Spt:118872.0,118661.1] || -> node4(s39)*. % 76.16/76.31 118876[99:MRR:801.0,118874.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.31 118879[99:Res:53.1,118876.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.31 118881[100:Spt:118879.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.31 118883[100:Res:118881.0,61.1] always3(s39) || -> . % 76.16/76.31 118884[100:SSi:118883.0,78241.0,78244.0,108789.0,118660.0,118874.0] || -> . % 76.16/76.31 118885[100:Spt:118884.0,118879.0,118881.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.31 118886[100:Spt:118884.0,118879.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.31 118890[100:Res:118886.0,61.1] always3(s40) || -> . % 76.16/76.31 118891[100:SSi:118890.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.31 118892[98:Spt:118891.0,118659.0,118660.0] || until2p7(s39)*+ -> . % 76.16/76.31 118893[98:Spt:118891.0,118659.1] || -> node4(s38)*. % 76.16/76.31 118895[98:MRR:804.0,118893.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.31 118898[98:Res:53.1,118895.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.31 118900[99:Spt:118898.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.31 118902[99:Res:118900.0,61.1] always3(s38) || -> . % 76.16/76.31 118903[99:SSi:118902.0,78236.0,78240.0,108788.0,118658.0,118893.0] || -> . % 76.16/76.31 118904[99:Spt:118903.0,118898.0,118900.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.31 118905[99:Spt:118903.0,118898.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.31 118909[99:Res:118905.0,61.1] always3(s39) || -> . % 76.16/76.31 118910[99:SSi:118909.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.31 118911[97:Spt:118910.0,118657.0,118658.0] || until2p7(s38)*+ -> . % 76.16/76.31 118912[97:Spt:118910.0,118657.1] || -> node4(s37)*. % 76.16/76.31 118914[97:MRR:807.0,118912.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.31 118917[97:Res:53.1,118914.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.31 118922[98:Spt:118917.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.31 118924[98:Res:118922.0,61.1] always3(s37) || -> . % 76.16/76.31 118925[98:SSi:118924.0,78232.0,78235.0,108787.0,118656.0,118912.0] || -> . % 76.16/76.31 118926[98:Spt:118925.0,118917.0,118922.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.31 118927[98:Spt:118925.0,118917.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.31 118931[98:Res:118927.0,61.1] always3(s38) || -> . % 76.16/76.31 118932[98:SSi:118931.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.31 118933[96:Spt:118932.0,118655.0,118656.0] || until2p7(s37)*+ -> . % 76.16/76.31 118934[96:Spt:118932.0,118655.1] || -> node4(s36)*. % 76.16/76.31 118936[96:MRR:810.0,118934.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.31 118939[96:Res:53.1,118936.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.31 118941[97:Spt:118939.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.31 118943[97:Res:118941.0,61.1] always3(s36) || -> . % 76.16/76.31 118944[97:SSi:118943.0,78227.0,78231.0,108786.0,118654.0,118934.0] || -> . % 76.16/76.31 118945[97:Spt:118944.0,118939.0,118941.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.31 118946[97:Spt:118944.0,118939.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.31 118950[97:Res:118946.0,61.1] always3(s37) || -> . % 76.16/76.31 118951[97:SSi:118950.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.31 118952[95:Spt:118951.0,118653.0,118654.0] || until2p7(s36)*+ -> . % 76.16/76.31 118953[95:Spt:118951.0,118653.1] || -> node4(s35)*. % 76.16/76.31 118955[95:MRR:813.0,118953.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.31 118958[95:Res:53.1,118955.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.31 118960[96:Spt:118958.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 118962[96:Res:118960.0,61.1] always3(s35) || -> . % 76.16/76.31 118963[96:SSi:118962.0,78223.0,78226.0,108785.0,118652.0,118953.0] || -> . % 76.16/76.31 118964[96:Spt:118963.0,118958.0,118960.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.31 118965[96:Spt:118963.0,118958.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.31 118969[96:Res:118965.0,61.1] always3(s36) || -> . % 76.16/76.31 118970[96:SSi:118969.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.31 118971[94:Spt:118970.0,118651.0,118652.0] || until2p7(s35)*+ -> . % 76.16/76.31 118972[94:Spt:118970.0,118651.1] || -> node4(s34)*. % 76.16/76.31 118974[94:MRR:816.0,118972.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.31 118977[94:Res:53.1,118974.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.31 118979[95:Spt:118977.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 118981[95:Res:118979.0,61.1] always3(s34) || -> . % 76.16/76.31 118982[95:SSi:118981.0,78218.0,78222.0,108784.0,118650.0,118972.0] || -> . % 76.16/76.31 118983[95:Spt:118982.0,118977.0,118979.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.31 118984[95:Spt:118982.0,118977.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.31 118988[95:Res:118984.0,61.1] always3(s35) || -> . % 76.16/76.31 118989[95:SSi:118988.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.31 118990[93:Spt:118989.0,118649.0,118650.0] || until2p7(s34)*+ -> . % 76.16/76.31 118991[93:Spt:118989.0,118649.1] || -> node4(s33)*. % 76.16/76.31 118993[93:MRR:819.0,118991.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.31 118996[93:Res:53.1,118993.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.31 119001[94:Spt:118996.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 119003[94:Res:119001.0,61.1] always3(s33) || -> . % 76.16/76.31 119004[94:SSi:119003.0,78214.0,78217.0,108783.0,118648.0,118991.0] || -> . % 76.16/76.31 119005[94:Spt:119004.0,118996.0,119001.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.31 119006[94:Spt:119004.0,118996.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.31 119010[94:Res:119006.0,61.1] always3(s34) || -> . % 76.16/76.31 119011[94:SSi:119010.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.31 119012[92:Spt:119011.0,118647.0,118648.0] || until2p7(s33)*+ -> . % 76.16/76.31 119013[92:Spt:119011.0,118647.1] || -> node4(s32)*. % 76.16/76.31 119015[92:MRR:822.0,119013.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.31 119018[92:Res:53.1,119015.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.31 119020[93:Spt:119018.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 119022[93:Res:119020.0,61.1] always3(s32) || -> . % 76.16/76.31 119023[93:SSi:119022.0,78209.0,78213.0,108782.0,118646.0,119013.0] || -> . % 76.16/76.31 119024[93:Spt:119023.0,119018.0,119020.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.31 119025[93:Spt:119023.0,119018.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.31 119029[93:Res:119025.0,61.1] always3(s33) || -> . % 76.16/76.31 119030[93:SSi:119029.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.31 119031[91:Spt:119030.0,118645.0,118646.0] || until2p7(s32)*+ -> . % 76.16/76.31 119032[91:Spt:119030.0,118645.1] || -> node4(s31)*. % 76.16/76.31 119034[91:MRR:825.0,119032.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.31 119037[91:Res:53.1,119034.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.31 119039[92:Spt:119037.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 119041[92:Res:119039.0,61.1] always3(s31) || -> . % 76.16/76.31 119042[92:SSi:119041.0,78205.0,78208.0,108781.0,118644.0,119032.0] || -> . % 76.16/76.31 119043[92:Spt:119042.0,119037.0,119039.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.31 119044[92:Spt:119042.0,119037.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.31 119048[92:Res:119044.0,61.1] always3(s32) || -> . % 76.16/76.31 119049[92:SSi:119048.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.31 119050[90:Spt:119049.0,118643.0,118644.0] || until2p7(s31)*+ -> . % 76.16/76.31 119051[90:Spt:119049.0,118643.1] || -> node4(s30)*. % 76.16/76.31 119053[90:MRR:828.0,119051.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.31 119056[90:Res:53.1,119053.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.31 119058[91:Spt:119056.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 119060[91:Res:119058.0,61.1] always3(s30) || -> . % 76.16/76.31 119061[91:SSi:119060.0,78200.0,78204.0,108780.0,118642.0,119051.0] || -> . % 76.16/76.31 119062[91:Spt:119061.0,119056.0,119058.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.31 119063[91:Spt:119061.0,119056.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.31 119067[91:Res:119063.0,61.1] always3(s31) || -> . % 76.16/76.31 119068[91:SSi:119067.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.31 119069[89:Spt:119068.0,118641.0,118642.0] || until2p7(s30)*+ -> . % 76.16/76.31 119070[89:Spt:119068.0,118641.1] || -> node4(s29)*. % 76.16/76.31 119072[89:MRR:831.0,119070.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.31 119075[89:Res:53.1,119072.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.31 119080[90:Spt:119075.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 119082[90:Res:119080.0,61.1] always3(s29) || -> . % 76.16/76.31 119083[90:SSi:119082.0,78196.0,78199.0,108779.0,118640.0,119070.0] || -> . % 76.16/76.31 119084[90:Spt:119083.0,119075.0,119080.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.31 119085[90:Spt:119083.0,119075.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.31 119089[90:Res:119085.0,61.1] always3(s30) || -> . % 76.16/76.31 119090[90:SSi:119089.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.31 119091[88:Spt:119090.0,118639.0,118640.0] || until2p7(s29)*+ -> . % 76.16/76.31 119092[88:Spt:119090.0,118639.1] || -> node4(s28)*. % 76.16/76.31 119094[88:MRR:834.0,119092.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.31 119097[88:Res:53.1,119094.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.31 119099[89:Spt:119097.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.31 119101[89:Res:119099.0,61.1] always3(s28) || -> . % 76.16/76.31 119102[89:SSi:119101.0,78191.0,78195.0,108778.0,118638.0,119092.0] || -> . % 76.16/76.31 119103[89:Spt:119102.0,119097.0,119099.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.31 119104[89:Spt:119102.0,119097.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.31 119108[89:Res:119104.0,61.1] always3(s29) || -> . % 76.16/76.31 119109[89:SSi:119108.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.31 119110[87:Spt:119109.0,118637.0,118638.0] || until2p7(s28)*+ -> . % 76.16/76.31 119111[87:Spt:119109.0,118637.1] || -> node4(s27)*. % 76.16/76.31 119113[87:MRR:837.0,119111.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.31 119116[87:Res:53.1,119113.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.31 119118[88:Spt:119116.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.31 119120[88:Res:119118.0,61.1] always3(s27) || -> . % 76.16/76.31 119121[88:SSi:119120.0,78187.0,78190.0,108777.0,118636.0,119111.0] || -> . % 76.16/76.31 119122[88:Spt:119121.0,119116.0,119118.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.31 119123[88:Spt:119121.0,119116.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.31 119127[88:Res:119123.0,61.1] always3(s28) || -> . % 76.16/76.31 119128[88:SSi:119127.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.31 119129[86:Spt:119128.0,118635.0,118636.0] || until2p7(s27)*+ -> . % 76.16/76.31 119130[86:Spt:119128.0,118635.1] || -> node4(s26)*. % 76.16/76.31 119132[86:MRR:840.0,119130.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.31 119135[86:Res:53.1,119132.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.31 119137[87:Spt:119135.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.31 119139[87:Res:119137.0,61.1] always3(s26) || -> . % 76.16/76.31 119140[87:SSi:119139.0,78182.0,78186.0,108776.0,118634.0,119130.0] || -> . % 76.16/76.31 119141[87:Spt:119140.0,119135.0,119137.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.31 119142[87:Spt:119140.0,119135.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.31 119146[87:Res:119142.0,61.1] always3(s27) || -> . % 76.16/76.31 119147[87:SSi:119146.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.31 119148[85:Spt:119147.0,118633.0,118634.0] || until2p7(s26)*+ -> . % 76.16/76.31 119149[85:Spt:119147.0,118633.1] || -> node4(s25)*. % 76.16/76.31 119151[85:MRR:843.0,119149.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.31 119154[85:Res:53.1,119151.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.31 119159[86:Spt:119154.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.31 119161[86:Res:119159.0,61.1] always3(s25) || -> . % 76.16/76.31 119162[86:SSi:119161.0,78178.0,78181.0,108775.0,118632.0,119149.0] || -> . % 76.16/76.31 119163[86:Spt:119162.0,119154.0,119159.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.31 119164[86:Spt:119162.0,119154.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.31 119168[86:Res:119164.0,61.1] always3(s26) || -> . % 76.16/76.31 119169[86:SSi:119168.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.31 119170[84:Spt:119169.0,118631.0,118632.0] || until2p7(s25)*+ -> . % 76.16/76.31 119171[84:Spt:119169.0,118631.1] || -> node4(s24)*. % 76.16/76.31 119173[84:MRR:846.0,119171.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.31 119176[84:Res:53.1,119173.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.31 119178[85:Spt:119176.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.31 119180[85:Res:119178.0,61.1] always3(s24) || -> . % 76.16/76.31 119181[85:SSi:119180.0,78173.0,78177.0,108774.0,118630.0,119171.0] || -> . % 76.16/76.31 119182[85:Spt:119181.0,119176.0,119178.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.31 119183[85:Spt:119181.0,119176.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.31 119187[85:Res:119183.0,61.1] always3(s25) || -> . % 76.16/76.31 119188[85:SSi:119187.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.31 119189[83:Spt:119188.0,118629.0,118630.0] || until2p7(s24)*+ -> . % 76.16/76.31 119190[83:Spt:119188.0,118629.1] || -> node4(s23)*. % 76.16/76.31 119192[83:MRR:849.0,119190.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.31 119195[83:Res:53.1,119192.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.31 119197[84:Spt:119195.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.31 119199[84:Res:119197.0,61.1] always3(s23) || -> . % 76.16/76.31 119200[84:SSi:119199.0,78169.0,78172.0,108773.0,118628.0,119190.0] || -> . % 76.16/76.31 119201[84:Spt:119200.0,119195.0,119197.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.31 119202[84:Spt:119200.0,119195.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.31 119206[84:Res:119202.0,61.1] always3(s24) || -> . % 76.16/76.31 119207[84:SSi:119206.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.31 119208[82:Spt:119207.0,118627.0,118628.0] || until2p7(s23)*+ -> . % 76.16/76.31 119209[82:Spt:119207.0,118627.1] || -> node4(s22)*. % 76.16/76.31 119211[82:MRR:852.0,119209.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.31 119214[82:Res:53.1,119211.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.31 119216[82:MRR:119214.0,118617.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.31 119218[82:Res:119216.0,61.1] always3(s23) || -> . % 76.16/76.31 119219[82:SSi:119218.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.31 119220[80:Spt:119219.0,118508.0,118511.0] || trans(s49,s22)*+ -> . % 76.16/76.31 119221[80:Spt:119219.0,118508.1,118508.2,118508.3,118508.4,118508.5,118508.6,118508.7,118508.8,118508.9,118508.10,118508.11,118508.12,118508.13,118508.14,118508.15,118508.16,118508.17,118508.18,118508.19] || -> trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.31 119223[80:MRR:118510.1,119220.0] xuntil6(s49) || -> trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.31 119224[81:Spt:119221.0] || -> trans(s49,s21)*. % 76.16/76.31 119225[81:Res:119224.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s21)*. % 76.16/76.31 119227[81:Res:119224.0,60.0] || -> node2(s49,s21)*. % 76.16/76.31 119228[81:SSi:119225.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s21)*. % 76.16/76.31 119229[81:Res:119227.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)*. % 76.16/76.31 119323[81:SoR:119229.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)*. % 76.16/76.31 119325[81:SoR:119323.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)* xuntil6(s49). % 76.16/76.31 119326[81:SSi:119325.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s21,c_busy)* xuntil6(s49). % 76.16/76.31 119327[82:Spt:119326.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.31 119329[82:Res:119327.0,61.1] always3(s21) || -> . % 76.16/76.31 119330[82:SSi:119329.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.31 119331[82:Spt:119330.0,119326.1,119327.0] || m_main_v_state(s21,c_busy)*+ -> . % 76.16/76.31 119332[82:Spt:119330.0,119326.0,119326.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.31 119336[82:MRR:119323.2,119331.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.31 119337[82:Res:53.1,119332.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.31 119339[82:MRR:119337.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.31 119340[82:MRR:119228.0,119339.0] || -> until2p7(s21)*. % 76.16/76.31 119341[82:MRR:217.0,119340.0] || -> until2p7(s22)* node4(s21). % 76.16/76.31 119342[83:Spt:119341.0] || -> until2p7(s22)*. % 76.16/76.31 119343[83:MRR:218.0,119342.0] || -> until2p7(s23)* node4(s22). % 76.16/76.31 119344[84:Spt:119343.0] || -> until2p7(s23)*. % 76.16/76.31 119345[84:MRR:219.0,119344.0] || -> until2p7(s24)* node4(s23). % 76.16/76.31 119346[85:Spt:119345.0] || -> until2p7(s24)*. % 76.16/76.31 119347[85:MRR:220.0,119346.0] || -> until2p7(s25)* node4(s24). % 76.16/76.31 119348[86:Spt:119347.0] || -> until2p7(s25)*. % 76.16/76.31 119349[86:MRR:221.0,119348.0] || -> until2p7(s26)* node4(s25). % 76.16/76.31 119350[87:Spt:119349.0] || -> until2p7(s26)*. % 76.16/76.31 119351[87:MRR:222.0,119350.0] || -> until2p7(s27)* node4(s26). % 76.16/76.31 119352[88:Spt:119351.0] || -> until2p7(s27)*. % 76.16/76.31 119353[88:MRR:223.0,119352.0] || -> until2p7(s28)* node4(s27). % 76.16/76.31 119354[89:Spt:119353.0] || -> until2p7(s28)*. % 76.16/76.31 119355[89:MRR:224.0,119354.0] || -> until2p7(s29)* node4(s28). % 76.16/76.31 119356[90:Spt:119355.0] || -> until2p7(s29)*. % 76.16/76.31 119357[90:MRR:225.0,119356.0] || -> until2p7(s30)* node4(s29). % 76.16/76.31 119358[91:Spt:119357.0] || -> until2p7(s30)*. % 76.16/76.31 119359[91:MRR:226.0,119358.0] || -> until2p7(s31)* node4(s30). % 76.16/76.31 119360[92:Spt:119359.0] || -> until2p7(s31)*. % 76.16/76.31 119361[92:MRR:227.0,119360.0] || -> until2p7(s32)* node4(s31). % 76.16/76.31 119362[93:Spt:119361.0] || -> until2p7(s32)*. % 76.16/76.31 119363[93:MRR:228.0,119362.0] || -> until2p7(s33)* node4(s32). % 76.16/76.31 119364[94:Spt:119363.0] || -> until2p7(s33)*. % 76.16/76.31 119365[94:MRR:229.0,119364.0] || -> until2p7(s34)* node4(s33). % 76.16/76.31 119366[95:Spt:119365.0] || -> until2p7(s34)*. % 76.16/76.31 119367[95:MRR:230.0,119366.0] || -> until2p7(s35)* node4(s34). % 76.16/76.31 119368[96:Spt:119367.0] || -> until2p7(s35)*. % 76.16/76.31 119369[96:MRR:231.0,119368.0] || -> until2p7(s36)* node4(s35). % 76.16/76.31 119370[97:Spt:119369.0] || -> until2p7(s36)*. % 76.16/76.31 119371[97:MRR:232.0,119370.0] || -> until2p7(s37)* node4(s36). % 76.16/76.31 119372[98:Spt:119371.0] || -> until2p7(s37)*. % 76.16/76.31 119373[98:MRR:235.0,119372.0] || -> until2p7(s38)* node4(s37). % 76.16/76.31 119374[99:Spt:119373.0] || -> until2p7(s38)*. % 76.16/76.31 119375[99:MRR:236.0,119374.0] || -> until2p7(s39)* node4(s38). % 76.16/76.31 119376[100:Spt:119375.0] || -> until2p7(s39)*. % 76.16/76.31 119377[100:MRR:237.0,119376.0] || -> until2p7(s40)* node4(s39). % 76.16/76.31 119378[101:Spt:119377.0] || -> until2p7(s40)*. % 76.16/76.31 119379[101:MRR:238.0,119378.0] || -> until2p7(s41)* node4(s40). % 76.16/76.31 119380[102:Spt:119379.0] || -> until2p7(s41)*. % 76.16/76.31 119381[102:MRR:239.0,119380.0] || -> until2p7(s42)* node4(s41). % 76.16/76.31 119382[103:Spt:119381.0] || -> until2p7(s42)*. % 76.16/76.31 119383[103:MRR:240.0,119382.0] || -> until2p7(s43)* node4(s42). % 76.16/76.31 119384[104:Spt:119383.0] || -> until2p7(s43)*. % 76.16/76.31 119385[104:MRR:241.0,119384.0] || -> until2p7(s44)* node4(s43). % 76.16/76.31 119386[105:Spt:119385.0] || -> until2p7(s44)*. % 76.16/76.31 119387[105:MRR:539.0,119386.0] || -> until2p7(s45)* node4(s44). % 76.16/76.31 119388[106:Spt:119387.0] || -> until2p7(s45)*. % 76.16/76.31 119389[106:MRR:544.0,119388.0] || -> until2p7(s46)* node4(s45). % 76.16/76.31 119390[107:Spt:119389.0] || -> until2p7(s46)*. % 76.16/76.31 119391[107:MRR:549.0,119390.0] || -> until2p7(s47)* node4(s46). % 76.16/76.31 119392[108:Spt:119391.0] || -> until2p7(s47)*. % 76.16/76.31 119393[108:MRR:554.0,119392.0] || -> until2p7(s48)* node4(s47). % 76.16/76.31 119394[109:Spt:119393.0] || -> until2p7(s48)*. % 76.16/76.31 119395[109:MRR:559.0,119394.0] || -> until2p7(s49)* node4(s48). % 76.16/76.31 119396[110:Spt:119395.0] || -> until2p7(s49)*. % 76.16/76.31 119397[110:MRR:194.0,119396.0] || -> node4(s49)*. % 76.16/76.31 119398[110:MRR:119336.0,119397.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.31 119402[110:Res:53.1,119398.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.31 119404[110:MRR:119402.0,78381.0] || -> . % 76.16/76.31 119405[110:Spt:119404.0,119395.0,119396.0] || until2p7(s49)*+ -> . % 76.16/76.31 119406[110:Spt:119404.0,119395.1] || -> node4(s48)*. % 76.16/76.31 119407[110:MRR:78384.0,119406.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.31 119410[110:Res:53.1,119407.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 119413[110:Res:119410.0,61.1] always3(s48) || -> . % 76.16/76.31 119414[110:SSi:119413.0,78281.0,78387.0,108798.0,119394.0,119406.0] || -> . % 76.16/76.31 119415[109:Spt:119414.0,119393.0,119394.0] || until2p7(s48)*+ -> . % 76.16/76.31 119416[109:Spt:119414.0,119393.1] || -> node4(s47)*. % 76.16/76.31 119418[109:MRR:777.0,119416.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.31 119430[109:Res:53.1,119418.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.31 119432[110:Spt:119430.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 119434[110:Res:119432.0,61.1] always3(s47) || -> . % 76.16/76.31 119435[110:SSi:119434.0,78277.0,78280.0,108797.0,119392.0,119416.0] || -> . % 76.16/76.31 119436[110:Spt:119435.0,119430.0,119432.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.31 119437[110:Spt:119435.0,119430.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.31 119441[110:Res:119437.0,61.1] always3(s48) || -> . % 76.16/76.31 119442[110:SSi:119441.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.31 119443[108:Spt:119442.0,119391.0,119392.0] || until2p7(s47)*+ -> . % 76.16/76.31 119444[108:Spt:119442.0,119391.1] || -> node4(s46)*. % 76.16/76.31 119446[108:MRR:780.0,119444.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.31 119453[108:Res:53.1,119446.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.31 119458[109:Spt:119453.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 119460[109:Res:119458.0,61.1] always3(s46) || -> . % 76.16/76.31 119461[109:SSi:119460.0,78272.0,78276.0,108796.0,119390.0,119444.0] || -> . % 76.16/76.31 119462[109:Spt:119461.0,119453.0,119458.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.31 119463[109:Spt:119461.0,119453.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.31 119467[109:Res:119463.0,61.1] always3(s47) || -> . % 76.16/76.31 119468[109:SSi:119467.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.31 119469[107:Spt:119468.0,119389.0,119390.0] || until2p7(s46)*+ -> . % 76.16/76.31 119470[107:Spt:119468.0,119389.1] || -> node4(s45)*. % 76.16/76.31 119472[107:MRR:783.0,119470.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.31 119475[107:Res:53.1,119472.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.31 119477[108:Spt:119475.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 119479[108:Res:119477.0,61.1] always3(s45) || -> . % 76.16/76.31 119480[108:SSi:119479.0,78268.0,78271.0,108795.0,119388.0,119470.0] || -> . % 76.16/76.31 119481[108:Spt:119480.0,119475.0,119477.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.31 119482[108:Spt:119480.0,119475.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.31 119486[108:Res:119482.0,61.1] always3(s46) || -> . % 76.16/76.31 119487[108:SSi:119486.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.31 119488[106:Spt:119487.0,119387.0,119388.0] || until2p7(s45)*+ -> . % 76.16/76.31 119489[106:Spt:119487.0,119387.1] || -> node4(s44)*. % 76.16/76.31 119491[106:MRR:786.0,119489.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.31 119494[106:Res:53.1,119491.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.31 119496[107:Spt:119494.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 119498[107:Res:119496.0,61.1] always3(s44) || -> . % 76.16/76.31 119499[107:SSi:119498.0,78263.0,78267.0,108794.0,119386.0,119489.0] || -> . % 76.16/76.31 119500[107:Spt:119499.0,119494.0,119496.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.31 119501[107:Spt:119499.0,119494.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.31 119505[107:Res:119501.0,61.1] always3(s45) || -> . % 76.16/76.31 119506[107:SSi:119505.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.31 119507[105:Spt:119506.0,119385.0,119386.0] || until2p7(s44)*+ -> . % 76.16/76.31 119508[105:Spt:119506.0,119385.1] || -> node4(s43)*. % 76.16/76.31 119510[105:MRR:789.0,119508.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.31 119513[105:Res:53.1,119510.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.31 119515[106:Spt:119513.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 119517[106:Res:119515.0,61.1] always3(s43) || -> . % 76.16/76.31 119518[106:SSi:119517.0,78259.0,78262.0,108793.0,119384.0,119508.0] || -> . % 76.16/76.31 119519[106:Spt:119518.0,119513.0,119515.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.31 119520[106:Spt:119518.0,119513.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.31 119524[106:Res:119520.0,61.1] always3(s44) || -> . % 76.16/76.31 119525[106:SSi:119524.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.31 119526[104:Spt:119525.0,119383.0,119384.0] || until2p7(s43)*+ -> . % 76.16/76.31 119527[104:Spt:119525.0,119383.1] || -> node4(s42)*. % 76.16/76.31 119529[104:MRR:792.0,119527.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.31 119532[104:Res:53.1,119529.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.31 119537[105:Spt:119532.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 119539[105:Res:119537.0,61.1] always3(s42) || -> . % 76.16/76.31 119540[105:SSi:119539.0,78254.0,78258.0,108792.0,119382.0,119527.0] || -> . % 76.16/76.31 119541[105:Spt:119540.0,119532.0,119537.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.31 119542[105:Spt:119540.0,119532.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.31 119546[105:Res:119542.0,61.1] always3(s43) || -> . % 76.16/76.31 119547[105:SSi:119546.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.31 119548[103:Spt:119547.0,119381.0,119382.0] || until2p7(s42)*+ -> . % 76.16/76.31 119549[103:Spt:119547.0,119381.1] || -> node4(s41)*. % 76.16/76.31 119551[103:MRR:795.0,119549.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.31 119554[103:Res:53.1,119551.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.31 119556[104:Spt:119554.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 119558[104:Res:119556.0,61.1] always3(s41) || -> . % 76.16/76.31 119559[104:SSi:119558.0,78250.0,78253.0,108791.0,119380.0,119549.0] || -> . % 76.16/76.31 119560[104:Spt:119559.0,119554.0,119556.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.31 119561[104:Spt:119559.0,119554.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.31 119565[104:Res:119561.0,61.1] always3(s42) || -> . % 76.16/76.31 119566[104:SSi:119565.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.31 119567[102:Spt:119566.0,119379.0,119380.0] || until2p7(s41)*+ -> . % 76.16/76.31 119568[102:Spt:119566.0,119379.1] || -> node4(s40)*. % 76.16/76.31 119570[102:MRR:798.0,119568.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.31 119573[102:Res:53.1,119570.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.31 119575[103:Spt:119573.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.31 119577[103:Res:119575.0,61.1] always3(s40) || -> . % 76.16/76.31 119578[103:SSi:119577.0,78245.0,78249.0,108790.0,119378.0,119568.0] || -> . % 76.16/76.31 119579[103:Spt:119578.0,119573.0,119575.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.31 119580[103:Spt:119578.0,119573.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.31 119584[103:Res:119580.0,61.1] always3(s41) || -> . % 76.16/76.31 119585[103:SSi:119584.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.31 119586[101:Spt:119585.0,119377.0,119378.0] || until2p7(s40)*+ -> . % 76.16/76.31 119587[101:Spt:119585.0,119377.1] || -> node4(s39)*. % 76.16/76.31 119589[101:MRR:801.0,119587.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.31 119592[101:Res:53.1,119589.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.31 119594[102:Spt:119592.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.31 119596[102:Res:119594.0,61.1] always3(s39) || -> . % 76.16/76.31 119597[102:SSi:119596.0,78241.0,78244.0,108789.0,119376.0,119587.0] || -> . % 76.16/76.31 119598[102:Spt:119597.0,119592.0,119594.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.31 119599[102:Spt:119597.0,119592.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 119603[102:Res:119599.0,61.1] always3(s40) || -> . % 76.16/76.32 119604[102:SSi:119603.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.32 119605[100:Spt:119604.0,119375.0,119376.0] || until2p7(s39)*+ -> . % 76.16/76.32 119606[100:Spt:119604.0,119375.1] || -> node4(s38)*. % 76.16/76.32 119608[100:MRR:804.0,119606.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.32 119611[100:Res:53.1,119608.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.32 119616[101:Spt:119611.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 119618[101:Res:119616.0,61.1] always3(s38) || -> . % 76.16/76.32 119619[101:SSi:119618.0,78236.0,78240.0,108788.0,119374.0,119606.0] || -> . % 76.16/76.32 119620[101:Spt:119619.0,119611.0,119616.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.32 119621[101:Spt:119619.0,119611.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 119625[101:Res:119621.0,61.1] always3(s39) || -> . % 76.16/76.32 119626[101:SSi:119625.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.32 119627[99:Spt:119626.0,119373.0,119374.0] || until2p7(s38)*+ -> . % 76.16/76.32 119628[99:Spt:119626.0,119373.1] || -> node4(s37)*. % 76.16/76.32 119630[99:MRR:807.0,119628.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.32 119633[99:Res:53.1,119630.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.32 119635[100:Spt:119633.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 119637[100:Res:119635.0,61.1] always3(s37) || -> . % 76.16/76.32 119638[100:SSi:119637.0,78232.0,78235.0,108787.0,119372.0,119628.0] || -> . % 76.16/76.32 119639[100:Spt:119638.0,119633.0,119635.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.32 119640[100:Spt:119638.0,119633.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 119644[100:Res:119640.0,61.1] always3(s38) || -> . % 76.16/76.32 119645[100:SSi:119644.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.32 119646[98:Spt:119645.0,119371.0,119372.0] || until2p7(s37)*+ -> . % 76.16/76.32 119647[98:Spt:119645.0,119371.1] || -> node4(s36)*. % 76.16/76.32 119649[98:MRR:810.0,119647.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.32 119652[98:Res:53.1,119649.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.32 119654[99:Spt:119652.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 119656[99:Res:119654.0,61.1] always3(s36) || -> . % 76.16/76.32 119657[99:SSi:119656.0,78227.0,78231.0,108786.0,119370.0,119647.0] || -> . % 76.16/76.32 119658[99:Spt:119657.0,119652.0,119654.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.32 119659[99:Spt:119657.0,119652.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 119663[99:Res:119659.0,61.1] always3(s37) || -> . % 76.16/76.32 119664[99:SSi:119663.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.32 119665[97:Spt:119664.0,119369.0,119370.0] || until2p7(s36)*+ -> . % 76.16/76.32 119666[97:Spt:119664.0,119369.1] || -> node4(s35)*. % 76.16/76.32 119668[97:MRR:813.0,119666.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.32 119671[97:Res:53.1,119668.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.32 119673[98:Spt:119671.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 119675[98:Res:119673.0,61.1] always3(s35) || -> . % 76.16/76.32 119676[98:SSi:119675.0,78223.0,78226.0,108785.0,119368.0,119666.0] || -> . % 76.16/76.32 119677[98:Spt:119676.0,119671.0,119673.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.32 119678[98:Spt:119676.0,119671.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 119682[98:Res:119678.0,61.1] always3(s36) || -> . % 76.16/76.32 119683[98:SSi:119682.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.32 119684[96:Spt:119683.0,119367.0,119368.0] || until2p7(s35)*+ -> . % 76.16/76.32 119685[96:Spt:119683.0,119367.1] || -> node4(s34)*. % 76.16/76.32 119687[96:MRR:816.0,119685.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.32 119690[96:Res:53.1,119687.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.32 119695[97:Spt:119690.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 119697[97:Res:119695.0,61.1] always3(s34) || -> . % 76.16/76.32 119698[97:SSi:119697.0,78218.0,78222.0,108784.0,119366.0,119685.0] || -> . % 76.16/76.32 119699[97:Spt:119698.0,119690.0,119695.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.32 119700[97:Spt:119698.0,119690.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 119704[97:Res:119700.0,61.1] always3(s35) || -> . % 76.16/76.32 119705[97:SSi:119704.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.32 119706[95:Spt:119705.0,119365.0,119366.0] || until2p7(s34)*+ -> . % 76.16/76.32 119707[95:Spt:119705.0,119365.1] || -> node4(s33)*. % 76.16/76.32 119709[95:MRR:819.0,119707.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.32 119712[95:Res:53.1,119709.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.32 119714[96:Spt:119712.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 119716[96:Res:119714.0,61.1] always3(s33) || -> . % 76.16/76.32 119717[96:SSi:119716.0,78214.0,78217.0,108783.0,119364.0,119707.0] || -> . % 76.16/76.32 119718[96:Spt:119717.0,119712.0,119714.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.32 119719[96:Spt:119717.0,119712.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 119723[96:Res:119719.0,61.1] always3(s34) || -> . % 76.16/76.32 119724[96:SSi:119723.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.32 119725[94:Spt:119724.0,119363.0,119364.0] || until2p7(s33)*+ -> . % 76.16/76.32 119726[94:Spt:119724.0,119363.1] || -> node4(s32)*. % 76.16/76.32 119728[94:MRR:822.0,119726.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.32 119731[94:Res:53.1,119728.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.32 119733[95:Spt:119731.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 119735[95:Res:119733.0,61.1] always3(s32) || -> . % 76.16/76.32 119736[95:SSi:119735.0,78209.0,78213.0,108782.0,119362.0,119726.0] || -> . % 76.16/76.32 119737[95:Spt:119736.0,119731.0,119733.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.32 119738[95:Spt:119736.0,119731.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 119742[95:Res:119738.0,61.1] always3(s33) || -> . % 76.16/76.32 119743[95:SSi:119742.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.32 119744[93:Spt:119743.0,119361.0,119362.0] || until2p7(s32)*+ -> . % 76.16/76.32 119745[93:Spt:119743.0,119361.1] || -> node4(s31)*. % 76.16/76.32 119747[93:MRR:825.0,119745.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.32 119750[93:Res:53.1,119747.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.32 119752[94:Spt:119750.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 119754[94:Res:119752.0,61.1] always3(s31) || -> . % 76.16/76.32 119755[94:SSi:119754.0,78205.0,78208.0,108781.0,119360.0,119745.0] || -> . % 76.16/76.32 119756[94:Spt:119755.0,119750.0,119752.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.32 119757[94:Spt:119755.0,119750.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 119761[94:Res:119757.0,61.1] always3(s32) || -> . % 76.16/76.32 119762[94:SSi:119761.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.32 119763[92:Spt:119762.0,119359.0,119360.0] || until2p7(s31)*+ -> . % 76.16/76.32 119764[92:Spt:119762.0,119359.1] || -> node4(s30)*. % 76.16/76.32 119766[92:MRR:828.0,119764.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.32 119769[92:Res:53.1,119766.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.32 119774[93:Spt:119769.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 119776[93:Res:119774.0,61.1] always3(s30) || -> . % 76.16/76.32 119777[93:SSi:119776.0,78200.0,78204.0,108780.0,119358.0,119764.0] || -> . % 76.16/76.32 119778[93:Spt:119777.0,119769.0,119774.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.32 119779[93:Spt:119777.0,119769.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 119783[93:Res:119779.0,61.1] always3(s31) || -> . % 76.16/76.32 119784[93:SSi:119783.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.32 119785[91:Spt:119784.0,119357.0,119358.0] || until2p7(s30)*+ -> . % 76.16/76.32 119786[91:Spt:119784.0,119357.1] || -> node4(s29)*. % 76.16/76.32 119788[91:MRR:831.0,119786.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.32 119791[91:Res:53.1,119788.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.32 119793[92:Spt:119791.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 119795[92:Res:119793.0,61.1] always3(s29) || -> . % 76.16/76.32 119796[92:SSi:119795.0,78196.0,78199.0,108779.0,119356.0,119786.0] || -> . % 76.16/76.32 119797[92:Spt:119796.0,119791.0,119793.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.32 119798[92:Spt:119796.0,119791.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 119802[92:Res:119798.0,61.1] always3(s30) || -> . % 76.16/76.32 119803[92:SSi:119802.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.32 119804[90:Spt:119803.0,119355.0,119356.0] || until2p7(s29)*+ -> . % 76.16/76.32 119805[90:Spt:119803.0,119355.1] || -> node4(s28)*. % 76.16/76.32 119807[90:MRR:834.0,119805.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.32 119810[90:Res:53.1,119807.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.32 119812[91:Spt:119810.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 119814[91:Res:119812.0,61.1] always3(s28) || -> . % 76.16/76.32 119815[91:SSi:119814.0,78191.0,78195.0,108778.0,119354.0,119805.0] || -> . % 76.16/76.32 119816[91:Spt:119815.0,119810.0,119812.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.32 119817[91:Spt:119815.0,119810.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 119821[91:Res:119817.0,61.1] always3(s29) || -> . % 76.16/76.32 119822[91:SSi:119821.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.32 119823[89:Spt:119822.0,119353.0,119354.0] || until2p7(s28)*+ -> . % 76.16/76.32 119824[89:Spt:119822.0,119353.1] || -> node4(s27)*. % 76.16/76.32 119826[89:MRR:837.0,119824.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.32 119829[89:Res:53.1,119826.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.32 119831[90:Spt:119829.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 119833[90:Res:119831.0,61.1] always3(s27) || -> . % 76.16/76.32 119834[90:SSi:119833.0,78187.0,78190.0,108777.0,119352.0,119824.0] || -> . % 76.16/76.32 119835[90:Spt:119834.0,119829.0,119831.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.32 119836[90:Spt:119834.0,119829.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 119840[90:Res:119836.0,61.1] always3(s28) || -> . % 76.16/76.32 119841[90:SSi:119840.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.32 119842[88:Spt:119841.0,119351.0,119352.0] || until2p7(s27)*+ -> . % 76.16/76.32 119843[88:Spt:119841.0,119351.1] || -> node4(s26)*. % 76.16/76.32 119845[88:MRR:840.0,119843.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.32 119848[88:Res:53.1,119845.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.32 119853[89:Spt:119848.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 119855[89:Res:119853.0,61.1] always3(s26) || -> . % 76.16/76.32 119856[89:SSi:119855.0,78182.0,78186.0,108776.0,119350.0,119843.0] || -> . % 76.16/76.32 119857[89:Spt:119856.0,119848.0,119853.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.32 119858[89:Spt:119856.0,119848.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 119862[89:Res:119858.0,61.1] always3(s27) || -> . % 76.16/76.32 119863[89:SSi:119862.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.32 119864[87:Spt:119863.0,119349.0,119350.0] || until2p7(s26)*+ -> . % 76.16/76.32 119865[87:Spt:119863.0,119349.1] || -> node4(s25)*. % 76.16/76.32 119867[87:MRR:843.0,119865.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.32 119870[87:Res:53.1,119867.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.32 119872[88:Spt:119870.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 119874[88:Res:119872.0,61.1] always3(s25) || -> . % 76.16/76.32 119875[88:SSi:119874.0,78178.0,78181.0,108775.0,119348.0,119865.0] || -> . % 76.16/76.32 119876[88:Spt:119875.0,119870.0,119872.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.32 119877[88:Spt:119875.0,119870.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 119881[88:Res:119877.0,61.1] always3(s26) || -> . % 76.16/76.32 119882[88:SSi:119881.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.32 119883[86:Spt:119882.0,119347.0,119348.0] || until2p7(s25)*+ -> . % 76.16/76.32 119884[86:Spt:119882.0,119347.1] || -> node4(s24)*. % 76.16/76.32 119886[86:MRR:846.0,119884.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.32 119889[86:Res:53.1,119886.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.32 119891[87:Spt:119889.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 119893[87:Res:119891.0,61.1] always3(s24) || -> . % 76.16/76.32 119894[87:SSi:119893.0,78173.0,78177.0,108774.0,119346.0,119884.0] || -> . % 76.16/76.32 119895[87:Spt:119894.0,119889.0,119891.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.32 119896[87:Spt:119894.0,119889.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 119900[87:Res:119896.0,61.1] always3(s25) || -> . % 76.16/76.32 119901[87:SSi:119900.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.32 119902[85:Spt:119901.0,119345.0,119346.0] || until2p7(s24)*+ -> . % 76.16/76.32 119903[85:Spt:119901.0,119345.1] || -> node4(s23)*. % 76.16/76.32 119905[85:MRR:849.0,119903.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.32 119908[85:Res:53.1,119905.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.32 119910[86:Spt:119908.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 119912[86:Res:119910.0,61.1] always3(s23) || -> . % 76.16/76.32 119913[86:SSi:119912.0,78169.0,78172.0,108773.0,119344.0,119903.0] || -> . % 76.16/76.32 119914[86:Spt:119913.0,119908.0,119910.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.32 119915[86:Spt:119913.0,119908.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 119919[86:Res:119915.0,61.1] always3(s24) || -> . % 76.16/76.32 119920[86:SSi:119919.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.32 119921[84:Spt:119920.0,119343.0,119344.0] || until2p7(s23)*+ -> . % 76.16/76.32 119922[84:Spt:119920.0,119343.1] || -> node4(s22)*. % 76.16/76.32 119924[84:MRR:852.0,119922.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.32 119927[84:Res:53.1,119924.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.32 119932[85:Spt:119927.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 119934[85:Res:119932.0,61.1] always3(s22) || -> . % 76.16/76.32 119935[85:SSi:119934.0,78164.0,78168.0,108772.0,119342.0,119922.0] || -> . % 76.16/76.32 119936[85:Spt:119935.0,119927.0,119932.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.32 119937[85:Spt:119935.0,119927.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 119941[85:Res:119937.0,61.1] always3(s23) || -> . % 76.16/76.32 119942[85:SSi:119941.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.32 119943[83:Spt:119942.0,119341.0,119342.0] || until2p7(s22)*+ -> . % 76.16/76.32 119944[83:Spt:119942.0,119341.1] || -> node4(s21)*. % 76.16/76.32 119946[83:MRR:855.0,119944.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.32 119949[83:Res:53.1,119946.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.32 119951[83:MRR:119949.0,119331.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 119953[83:Res:119951.0,61.1] always3(s22) || -> . % 76.16/76.32 119954[83:SSi:119953.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.32 119955[81:Spt:119954.0,119221.0,119224.0] || trans(s49,s21)*+ -> . % 76.16/76.32 119956[81:Spt:119954.0,119221.1,119221.2,119221.3,119221.4,119221.5,119221.6,119221.7,119221.8,119221.9,119221.10,119221.11,119221.12,119221.13,119221.14,119221.15,119221.16,119221.17,119221.18] || -> trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.32 119958[81:MRR:119223.1,119955.0] xuntil6(s49) || -> trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.32 119959[82:Spt:119956.0] || -> trans(s49,s20)*. % 76.16/76.32 119960[82:Res:119959.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s20)*. % 76.16/76.32 119962[82:Res:119959.0,60.0] || -> node2(s49,s20)*. % 76.16/76.32 119963[82:SSi:119960.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s20)*. % 76.16/76.32 119964[82:Res:119962.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 120062[82:SoR:119964.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 120064[82:SoR:120062.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)* xuntil6(s49). % 76.16/76.32 120065[82:SSi:120064.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s20,c_busy)* xuntil6(s49). % 76.16/76.32 120066[83:Spt:120065.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 120068[83:Res:120066.0,61.1] always3(s20) || -> . % 76.16/76.32 120069[83:SSi:120068.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.32 120070[83:Spt:120069.0,120065.1,120066.0] || m_main_v_state(s20,c_busy)*+ -> . % 76.16/76.32 120071[83:Spt:120069.0,120065.0,120065.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.32 120075[83:MRR:120062.2,120070.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.32 120076[83:Res:53.1,120071.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.32 120078[83:MRR:120076.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.32 120079[83:MRR:119963.0,120078.0] || -> until2p7(s20)*. % 76.16/76.32 120080[83:MRR:216.0,120079.0] || -> until2p7(s21)* node4(s20). % 76.16/76.32 120081[84:Spt:120080.0] || -> until2p7(s21)*. % 76.16/76.32 120082[84:MRR:217.0,120081.0] || -> until2p7(s22)* node4(s21). % 76.16/76.32 120083[85:Spt:120082.0] || -> until2p7(s22)*. % 76.16/76.32 120084[85:MRR:218.0,120083.0] || -> until2p7(s23)* node4(s22). % 76.16/76.32 120085[86:Spt:120084.0] || -> until2p7(s23)*. % 76.16/76.32 120086[86:MRR:219.0,120085.0] || -> until2p7(s24)* node4(s23). % 76.16/76.32 120087[87:Spt:120086.0] || -> until2p7(s24)*. % 76.16/76.32 120088[87:MRR:220.0,120087.0] || -> until2p7(s25)* node4(s24). % 76.16/76.32 120089[88:Spt:120088.0] || -> until2p7(s25)*. % 76.16/76.32 120090[88:MRR:221.0,120089.0] || -> until2p7(s26)* node4(s25). % 76.16/76.32 120091[89:Spt:120090.0] || -> until2p7(s26)*. % 76.16/76.32 120092[89:MRR:222.0,120091.0] || -> until2p7(s27)* node4(s26). % 76.16/76.32 120093[90:Spt:120092.0] || -> until2p7(s27)*. % 76.16/76.32 120094[90:MRR:223.0,120093.0] || -> until2p7(s28)* node4(s27). % 76.16/76.32 120095[91:Spt:120094.0] || -> until2p7(s28)*. % 76.16/76.32 120096[91:MRR:224.0,120095.0] || -> until2p7(s29)* node4(s28). % 76.16/76.32 120097[92:Spt:120096.0] || -> until2p7(s29)*. % 76.16/76.32 120098[92:MRR:225.0,120097.0] || -> until2p7(s30)* node4(s29). % 76.16/76.32 120099[93:Spt:120098.0] || -> until2p7(s30)*. % 76.16/76.32 120100[93:MRR:226.0,120099.0] || -> until2p7(s31)* node4(s30). % 76.16/76.32 120101[94:Spt:120100.0] || -> until2p7(s31)*. % 76.16/76.32 120102[94:MRR:227.0,120101.0] || -> until2p7(s32)* node4(s31). % 76.16/76.32 120103[95:Spt:120102.0] || -> until2p7(s32)*. % 76.16/76.32 120104[95:MRR:228.0,120103.0] || -> until2p7(s33)* node4(s32). % 76.16/76.32 120105[96:Spt:120104.0] || -> until2p7(s33)*. % 76.16/76.32 120106[96:MRR:229.0,120105.0] || -> until2p7(s34)* node4(s33). % 76.16/76.32 120107[97:Spt:120106.0] || -> until2p7(s34)*. % 76.16/76.32 120108[97:MRR:230.0,120107.0] || -> until2p7(s35)* node4(s34). % 76.16/76.32 120109[98:Spt:120108.0] || -> until2p7(s35)*. % 76.16/76.32 120110[98:MRR:231.0,120109.0] || -> until2p7(s36)* node4(s35). % 76.16/76.32 120111[99:Spt:120110.0] || -> until2p7(s36)*. % 76.16/76.32 120112[99:MRR:232.0,120111.0] || -> until2p7(s37)* node4(s36). % 76.16/76.32 120113[100:Spt:120112.0] || -> until2p7(s37)*. % 76.16/76.32 120114[100:MRR:235.0,120113.0] || -> until2p7(s38)* node4(s37). % 76.16/76.32 120115[101:Spt:120114.0] || -> until2p7(s38)*. % 76.16/76.32 120116[101:MRR:236.0,120115.0] || -> until2p7(s39)* node4(s38). % 76.16/76.32 120117[102:Spt:120116.0] || -> until2p7(s39)*. % 76.16/76.32 120118[102:MRR:237.0,120117.0] || -> until2p7(s40)* node4(s39). % 76.16/76.32 120119[103:Spt:120118.0] || -> until2p7(s40)*. % 76.16/76.32 120120[103:MRR:238.0,120119.0] || -> until2p7(s41)* node4(s40). % 76.16/76.32 120121[104:Spt:120120.0] || -> until2p7(s41)*. % 76.16/76.32 120122[104:MRR:239.0,120121.0] || -> until2p7(s42)* node4(s41). % 76.16/76.32 120123[105:Spt:120122.0] || -> until2p7(s42)*. % 76.16/76.32 120124[105:MRR:240.0,120123.0] || -> until2p7(s43)* node4(s42). % 76.16/76.32 120125[106:Spt:120124.0] || -> until2p7(s43)*. % 76.16/76.32 120126[106:MRR:241.0,120125.0] || -> until2p7(s44)* node4(s43). % 76.16/76.32 120127[107:Spt:120126.0] || -> until2p7(s44)*. % 76.16/76.32 120128[107:MRR:539.0,120127.0] || -> until2p7(s45)* node4(s44). % 76.16/76.32 120129[108:Spt:120128.0] || -> until2p7(s45)*. % 76.16/76.32 120130[108:MRR:544.0,120129.0] || -> until2p7(s46)* node4(s45). % 76.16/76.32 120131[109:Spt:120130.0] || -> until2p7(s46)*. % 76.16/76.32 120132[109:MRR:549.0,120131.0] || -> until2p7(s47)* node4(s46). % 76.16/76.32 120133[110:Spt:120132.0] || -> until2p7(s47)*. % 76.16/76.32 120134[110:MRR:554.0,120133.0] || -> until2p7(s48)* node4(s47). % 76.16/76.32 120135[111:Spt:120134.0] || -> until2p7(s48)*. % 76.16/76.32 120136[111:MRR:559.0,120135.0] || -> until2p7(s49)* node4(s48). % 76.16/76.32 120137[112:Spt:120136.0] || -> until2p7(s49)*. % 76.16/76.32 120138[112:MRR:194.0,120137.0] || -> node4(s49)*. % 76.16/76.32 120139[112:MRR:120075.0,120138.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.32 120140[112:Res:53.1,120139.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.32 120142[112:MRR:120140.0,78381.0] || -> . % 76.16/76.32 120143[112:Spt:120142.0,120136.0,120137.0] || until2p7(s49)*+ -> . % 76.16/76.32 120144[112:Spt:120142.0,120136.1] || -> node4(s48)*. % 76.16/76.32 120145[112:MRR:78384.0,120144.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.32 120148[112:Res:53.1,120145.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 120151[112:Res:120148.0,61.1] always3(s48) || -> . % 76.16/76.32 120152[112:SSi:120151.0,78281.0,78387.0,108798.0,120135.0,120144.0] || -> . % 76.16/76.32 120153[111:Spt:120152.0,120134.0,120135.0] || until2p7(s48)*+ -> . % 76.16/76.32 120154[111:Spt:120152.0,120134.1] || -> node4(s47)*. % 76.16/76.32 120156[111:MRR:777.0,120154.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.32 120171[111:Res:53.1,120156.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.32 120173[112:Spt:120171.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 120175[112:Res:120173.0,61.1] always3(s47) || -> . % 76.16/76.32 120176[112:SSi:120175.0,78277.0,78280.0,108797.0,120133.0,120154.0] || -> . % 76.16/76.32 120177[112:Spt:120176.0,120171.0,120173.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.32 120178[112:Spt:120176.0,120171.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 120182[112:Res:120178.0,61.1] always3(s48) || -> . % 76.16/76.32 120183[112:SSi:120182.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.32 120184[110:Spt:120183.0,120132.0,120133.0] || until2p7(s47)*+ -> . % 76.16/76.32 120185[110:Spt:120183.0,120132.1] || -> node4(s46)*. % 76.16/76.32 120187[110:MRR:780.0,120185.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.32 120197[110:Res:53.1,120187.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.32 120199[111:Spt:120197.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 120201[111:Res:120199.0,61.1] always3(s46) || -> . % 76.16/76.32 120202[111:SSi:120201.0,78272.0,78276.0,108796.0,120131.0,120185.0] || -> . % 76.16/76.32 120203[111:Spt:120202.0,120197.0,120199.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.32 120204[111:Spt:120202.0,120197.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 120208[111:Res:120204.0,61.1] always3(s47) || -> . % 76.16/76.32 120209[111:SSi:120208.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.32 120210[109:Spt:120209.0,120130.0,120131.0] || until2p7(s46)*+ -> . % 76.16/76.32 120211[109:Spt:120209.0,120130.1] || -> node4(s45)*. % 76.16/76.32 120213[109:MRR:783.0,120211.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.32 120216[109:Res:53.1,120213.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.32 120218[110:Spt:120216.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 120220[110:Res:120218.0,61.1] always3(s45) || -> . % 76.16/76.32 120221[110:SSi:120220.0,78268.0,78271.0,108795.0,120129.0,120211.0] || -> . % 76.16/76.32 120222[110:Spt:120221.0,120216.0,120218.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.32 120223[110:Spt:120221.0,120216.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 120227[110:Res:120223.0,61.1] always3(s46) || -> . % 76.16/76.32 120228[110:SSi:120227.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.32 120229[108:Spt:120228.0,120128.0,120129.0] || until2p7(s45)*+ -> . % 76.16/76.32 120230[108:Spt:120228.0,120128.1] || -> node4(s44)*. % 76.16/76.32 120232[108:MRR:786.0,120230.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.32 120235[108:Res:53.1,120232.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.32 120237[109:Spt:120235.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 120239[109:Res:120237.0,61.1] always3(s44) || -> . % 76.16/76.32 120240[109:SSi:120239.0,78263.0,78267.0,108794.0,120127.0,120230.0] || -> . % 76.16/76.32 120241[109:Spt:120240.0,120235.0,120237.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.32 120242[109:Spt:120240.0,120235.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 120246[109:Res:120242.0,61.1] always3(s45) || -> . % 76.16/76.32 120247[109:SSi:120246.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.32 120248[107:Spt:120247.0,120126.0,120127.0] || until2p7(s44)*+ -> . % 76.16/76.32 120249[107:Spt:120247.0,120126.1] || -> node4(s43)*. % 76.16/76.32 120251[107:MRR:789.0,120249.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.32 120254[107:Res:53.1,120251.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.32 120259[108:Spt:120254.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 120261[108:Res:120259.0,61.1] always3(s43) || -> . % 76.16/76.32 120262[108:SSi:120261.0,78259.0,78262.0,108793.0,120125.0,120249.0] || -> . % 76.16/76.32 120263[108:Spt:120262.0,120254.0,120259.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.32 120264[108:Spt:120262.0,120254.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 120268[108:Res:120264.0,61.1] always3(s44) || -> . % 76.16/76.32 120269[108:SSi:120268.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.32 120270[106:Spt:120269.0,120124.0,120125.0] || until2p7(s43)*+ -> . % 76.16/76.32 120271[106:Spt:120269.0,120124.1] || -> node4(s42)*. % 76.16/76.32 120273[106:MRR:792.0,120271.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.32 120276[106:Res:53.1,120273.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.32 120278[107:Spt:120276.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 120280[107:Res:120278.0,61.1] always3(s42) || -> . % 76.16/76.32 120281[107:SSi:120280.0,78254.0,78258.0,108792.0,120123.0,120271.0] || -> . % 76.16/76.32 120282[107:Spt:120281.0,120276.0,120278.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.32 120283[107:Spt:120281.0,120276.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 120287[107:Res:120283.0,61.1] always3(s43) || -> . % 76.16/76.32 120288[107:SSi:120287.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.32 120289[105:Spt:120288.0,120122.0,120123.0] || until2p7(s42)*+ -> . % 76.16/76.32 120290[105:Spt:120288.0,120122.1] || -> node4(s41)*. % 76.16/76.32 120292[105:MRR:795.0,120290.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.32 120295[105:Res:53.1,120292.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.32 120297[106:Spt:120295.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 120299[106:Res:120297.0,61.1] always3(s41) || -> . % 76.16/76.32 120300[106:SSi:120299.0,78250.0,78253.0,108791.0,120121.0,120290.0] || -> . % 76.16/76.32 120301[106:Spt:120300.0,120295.0,120297.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.32 120302[106:Spt:120300.0,120295.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 120306[106:Res:120302.0,61.1] always3(s42) || -> . % 76.16/76.32 120307[106:SSi:120306.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.32 120308[104:Spt:120307.0,120120.0,120121.0] || until2p7(s41)*+ -> . % 76.16/76.32 120309[104:Spt:120307.0,120120.1] || -> node4(s40)*. % 76.16/76.32 120311[104:MRR:798.0,120309.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.32 120314[104:Res:53.1,120311.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.32 120316[105:Spt:120314.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 120318[105:Res:120316.0,61.1] always3(s40) || -> . % 76.16/76.32 120319[105:SSi:120318.0,78245.0,78249.0,108790.0,120119.0,120309.0] || -> . % 76.16/76.32 120320[105:Spt:120319.0,120314.0,120316.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.32 120321[105:Spt:120319.0,120314.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 120325[105:Res:120321.0,61.1] always3(s41) || -> . % 76.16/76.32 120326[105:SSi:120325.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.32 120327[103:Spt:120326.0,120118.0,120119.0] || until2p7(s40)*+ -> . % 76.16/76.32 120328[103:Spt:120326.0,120118.1] || -> node4(s39)*. % 76.16/76.32 120330[103:MRR:801.0,120328.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.32 120333[103:Res:53.1,120330.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.32 120338[104:Spt:120333.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 120340[104:Res:120338.0,61.1] always3(s39) || -> . % 76.16/76.32 120341[104:SSi:120340.0,78241.0,78244.0,108789.0,120117.0,120328.0] || -> . % 76.16/76.32 120342[104:Spt:120341.0,120333.0,120338.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.32 120343[104:Spt:120341.0,120333.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 120347[104:Res:120343.0,61.1] always3(s40) || -> . % 76.16/76.32 120348[104:SSi:120347.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.32 120349[102:Spt:120348.0,120116.0,120117.0] || until2p7(s39)*+ -> . % 76.16/76.32 120350[102:Spt:120348.0,120116.1] || -> node4(s38)*. % 76.16/76.32 120352[102:MRR:804.0,120350.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.32 120355[102:Res:53.1,120352.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.32 120357[103:Spt:120355.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 120359[103:Res:120357.0,61.1] always3(s38) || -> . % 76.16/76.32 120360[103:SSi:120359.0,78236.0,78240.0,108788.0,120115.0,120350.0] || -> . % 76.16/76.32 120361[103:Spt:120360.0,120355.0,120357.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.32 120362[103:Spt:120360.0,120355.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 120366[103:Res:120362.0,61.1] always3(s39) || -> . % 76.16/76.32 120367[103:SSi:120366.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.32 120368[101:Spt:120367.0,120114.0,120115.0] || until2p7(s38)*+ -> . % 76.16/76.32 120369[101:Spt:120367.0,120114.1] || -> node4(s37)*. % 76.16/76.32 120371[101:MRR:807.0,120369.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.32 120374[101:Res:53.1,120371.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.32 120376[102:Spt:120374.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 120378[102:Res:120376.0,61.1] always3(s37) || -> . % 76.16/76.32 120379[102:SSi:120378.0,78232.0,78235.0,108787.0,120113.0,120369.0] || -> . % 76.16/76.32 120380[102:Spt:120379.0,120374.0,120376.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.32 120381[102:Spt:120379.0,120374.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 120385[102:Res:120381.0,61.1] always3(s38) || -> . % 76.16/76.32 120386[102:SSi:120385.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.32 120387[100:Spt:120386.0,120112.0,120113.0] || until2p7(s37)*+ -> . % 76.16/76.32 120388[100:Spt:120386.0,120112.1] || -> node4(s36)*. % 76.16/76.32 120390[100:MRR:810.0,120388.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.32 120393[100:Res:53.1,120390.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.32 120395[101:Spt:120393.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 120397[101:Res:120395.0,61.1] always3(s36) || -> . % 76.16/76.32 120398[101:SSi:120397.0,78227.0,78231.0,108786.0,120111.0,120388.0] || -> . % 76.16/76.32 120399[101:Spt:120398.0,120393.0,120395.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.32 120400[101:Spt:120398.0,120393.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 120404[101:Res:120400.0,61.1] always3(s37) || -> . % 76.16/76.32 120405[101:SSi:120404.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.32 120406[99:Spt:120405.0,120110.0,120111.0] || until2p7(s36)*+ -> . % 76.16/76.32 120407[99:Spt:120405.0,120110.1] || -> node4(s35)*. % 76.16/76.32 120409[99:MRR:813.0,120407.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.32 120412[99:Res:53.1,120409.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.32 120417[100:Spt:120412.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 120419[100:Res:120417.0,61.1] always3(s35) || -> . % 76.16/76.32 120420[100:SSi:120419.0,78223.0,78226.0,108785.0,120109.0,120407.0] || -> . % 76.16/76.32 120421[100:Spt:120420.0,120412.0,120417.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.32 120422[100:Spt:120420.0,120412.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 120426[100:Res:120422.0,61.1] always3(s36) || -> . % 76.16/76.32 120427[100:SSi:120426.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.32 120428[98:Spt:120427.0,120108.0,120109.0] || until2p7(s35)*+ -> . % 76.16/76.32 120429[98:Spt:120427.0,120108.1] || -> node4(s34)*. % 76.16/76.32 120431[98:MRR:816.0,120429.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.32 120434[98:Res:53.1,120431.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.32 120436[99:Spt:120434.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 120438[99:Res:120436.0,61.1] always3(s34) || -> . % 76.16/76.32 120439[99:SSi:120438.0,78218.0,78222.0,108784.0,120107.0,120429.0] || -> . % 76.16/76.32 120440[99:Spt:120439.0,120434.0,120436.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.32 120441[99:Spt:120439.0,120434.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 120445[99:Res:120441.0,61.1] always3(s35) || -> . % 76.16/76.32 120446[99:SSi:120445.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.32 120447[97:Spt:120446.0,120106.0,120107.0] || until2p7(s34)*+ -> . % 76.16/76.32 120448[97:Spt:120446.0,120106.1] || -> node4(s33)*. % 76.16/76.32 120450[97:MRR:819.0,120448.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.32 120453[97:Res:53.1,120450.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.32 120455[98:Spt:120453.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 120457[98:Res:120455.0,61.1] always3(s33) || -> . % 76.16/76.32 120458[98:SSi:120457.0,78214.0,78217.0,108783.0,120105.0,120448.0] || -> . % 76.16/76.32 120459[98:Spt:120458.0,120453.0,120455.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.32 120460[98:Spt:120458.0,120453.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 120464[98:Res:120460.0,61.1] always3(s34) || -> . % 76.16/76.32 120465[98:SSi:120464.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.32 120466[96:Spt:120465.0,120104.0,120105.0] || until2p7(s33)*+ -> . % 76.16/76.32 120467[96:Spt:120465.0,120104.1] || -> node4(s32)*. % 76.16/76.32 120469[96:MRR:822.0,120467.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.32 120472[96:Res:53.1,120469.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.32 120474[97:Spt:120472.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 120476[97:Res:120474.0,61.1] always3(s32) || -> . % 76.16/76.32 120477[97:SSi:120476.0,78209.0,78213.0,108782.0,120103.0,120467.0] || -> . % 76.16/76.32 120478[97:Spt:120477.0,120472.0,120474.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.32 120479[97:Spt:120477.0,120472.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 120483[97:Res:120479.0,61.1] always3(s33) || -> . % 76.16/76.32 120484[97:SSi:120483.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.32 120485[95:Spt:120484.0,120102.0,120103.0] || until2p7(s32)*+ -> . % 76.16/76.32 120486[95:Spt:120484.0,120102.1] || -> node4(s31)*. % 76.16/76.32 120488[95:MRR:825.0,120486.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.32 120491[95:Res:53.1,120488.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.32 120496[96:Spt:120491.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 120498[96:Res:120496.0,61.1] always3(s31) || -> . % 76.16/76.32 120499[96:SSi:120498.0,78205.0,78208.0,108781.0,120101.0,120486.0] || -> . % 76.16/76.32 120500[96:Spt:120499.0,120491.0,120496.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.32 120501[96:Spt:120499.0,120491.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 120505[96:Res:120501.0,61.1] always3(s32) || -> . % 76.16/76.32 120506[96:SSi:120505.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.32 120507[94:Spt:120506.0,120100.0,120101.0] || until2p7(s31)*+ -> . % 76.16/76.32 120508[94:Spt:120506.0,120100.1] || -> node4(s30)*. % 76.16/76.32 120510[94:MRR:828.0,120508.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.32 120513[94:Res:53.1,120510.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.32 120515[95:Spt:120513.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 120517[95:Res:120515.0,61.1] always3(s30) || -> . % 76.16/76.32 120518[95:SSi:120517.0,78200.0,78204.0,108780.0,120099.0,120508.0] || -> . % 76.16/76.32 120519[95:Spt:120518.0,120513.0,120515.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.32 120520[95:Spt:120518.0,120513.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 120524[95:Res:120520.0,61.1] always3(s31) || -> . % 76.16/76.32 120525[95:SSi:120524.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.32 120526[93:Spt:120525.0,120098.0,120099.0] || until2p7(s30)*+ -> . % 76.16/76.32 120527[93:Spt:120525.0,120098.1] || -> node4(s29)*. % 76.16/76.32 120529[93:MRR:831.0,120527.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.32 120532[93:Res:53.1,120529.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.32 120534[94:Spt:120532.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 120536[94:Res:120534.0,61.1] always3(s29) || -> . % 76.16/76.32 120537[94:SSi:120536.0,78196.0,78199.0,108779.0,120097.0,120527.0] || -> . % 76.16/76.32 120538[94:Spt:120537.0,120532.0,120534.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.32 120539[94:Spt:120537.0,120532.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 120543[94:Res:120539.0,61.1] always3(s30) || -> . % 76.16/76.32 120544[94:SSi:120543.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.32 120545[92:Spt:120544.0,120096.0,120097.0] || until2p7(s29)*+ -> . % 76.16/76.32 120546[92:Spt:120544.0,120096.1] || -> node4(s28)*. % 76.16/76.32 120548[92:MRR:834.0,120546.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.32 120551[92:Res:53.1,120548.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.32 120553[93:Spt:120551.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 120555[93:Res:120553.0,61.1] always3(s28) || -> . % 76.16/76.32 120556[93:SSi:120555.0,78191.0,78195.0,108778.0,120095.0,120546.0] || -> . % 76.16/76.32 120557[93:Spt:120556.0,120551.0,120553.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.32 120558[93:Spt:120556.0,120551.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 120562[93:Res:120558.0,61.1] always3(s29) || -> . % 76.16/76.32 120563[93:SSi:120562.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.32 120564[91:Spt:120563.0,120094.0,120095.0] || until2p7(s28)*+ -> . % 76.16/76.32 120565[91:Spt:120563.0,120094.1] || -> node4(s27)*. % 76.16/76.32 120567[91:MRR:837.0,120565.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.32 120570[91:Res:53.1,120567.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.32 120575[92:Spt:120570.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 120577[92:Res:120575.0,61.1] always3(s27) || -> . % 76.16/76.32 120578[92:SSi:120577.0,78187.0,78190.0,108777.0,120093.0,120565.0] || -> . % 76.16/76.32 120579[92:Spt:120578.0,120570.0,120575.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.32 120580[92:Spt:120578.0,120570.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 120584[92:Res:120580.0,61.1] always3(s28) || -> . % 76.16/76.32 120585[92:SSi:120584.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.32 120586[90:Spt:120585.0,120092.0,120093.0] || until2p7(s27)*+ -> . % 76.16/76.32 120587[90:Spt:120585.0,120092.1] || -> node4(s26)*. % 76.16/76.32 120589[90:MRR:840.0,120587.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.32 120592[90:Res:53.1,120589.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.32 120594[91:Spt:120592.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 120596[91:Res:120594.0,61.1] always3(s26) || -> . % 76.16/76.32 120597[91:SSi:120596.0,78182.0,78186.0,108776.0,120091.0,120587.0] || -> . % 76.16/76.32 120598[91:Spt:120597.0,120592.0,120594.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.32 120599[91:Spt:120597.0,120592.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 120603[91:Res:120599.0,61.1] always3(s27) || -> . % 76.16/76.32 120604[91:SSi:120603.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.32 120605[89:Spt:120604.0,120090.0,120091.0] || until2p7(s26)*+ -> . % 76.16/76.32 120606[89:Spt:120604.0,120090.1] || -> node4(s25)*. % 76.16/76.32 120608[89:MRR:843.0,120606.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.32 120611[89:Res:53.1,120608.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.32 120613[90:Spt:120611.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 120615[90:Res:120613.0,61.1] always3(s25) || -> . % 76.16/76.32 120616[90:SSi:120615.0,78178.0,78181.0,108775.0,120089.0,120606.0] || -> . % 76.16/76.32 120617[90:Spt:120616.0,120611.0,120613.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.32 120618[90:Spt:120616.0,120611.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 120622[90:Res:120618.0,61.1] always3(s26) || -> . % 76.16/76.32 120623[90:SSi:120622.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.32 120624[88:Spt:120623.0,120088.0,120089.0] || until2p7(s25)*+ -> . % 76.16/76.32 120625[88:Spt:120623.0,120088.1] || -> node4(s24)*. % 76.16/76.32 120627[88:MRR:846.0,120625.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.32 120630[88:Res:53.1,120627.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.32 120632[89:Spt:120630.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 120634[89:Res:120632.0,61.1] always3(s24) || -> . % 76.16/76.32 120635[89:SSi:120634.0,78173.0,78177.0,108774.0,120087.0,120625.0] || -> . % 76.16/76.32 120636[89:Spt:120635.0,120630.0,120632.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.32 120637[89:Spt:120635.0,120630.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 120641[89:Res:120637.0,61.1] always3(s25) || -> . % 76.16/76.32 120642[89:SSi:120641.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.32 120643[87:Spt:120642.0,120086.0,120087.0] || until2p7(s24)*+ -> . % 76.16/76.32 120644[87:Spt:120642.0,120086.1] || -> node4(s23)*. % 76.16/76.32 120646[87:MRR:849.0,120644.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.32 120649[87:Res:53.1,120646.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.32 120654[88:Spt:120649.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 120656[88:Res:120654.0,61.1] always3(s23) || -> . % 76.16/76.32 120657[88:SSi:120656.0,78169.0,78172.0,108773.0,120085.0,120644.0] || -> . % 76.16/76.32 120658[88:Spt:120657.0,120649.0,120654.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.32 120659[88:Spt:120657.0,120649.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 120663[88:Res:120659.0,61.1] always3(s24) || -> . % 76.16/76.32 120664[88:SSi:120663.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.32 120665[86:Spt:120664.0,120084.0,120085.0] || until2p7(s23)*+ -> . % 76.16/76.32 120666[86:Spt:120664.0,120084.1] || -> node4(s22)*. % 76.16/76.32 120668[86:MRR:852.0,120666.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.32 120671[86:Res:53.1,120668.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.32 120673[87:Spt:120671.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 120675[87:Res:120673.0,61.1] always3(s22) || -> . % 76.16/76.32 120676[87:SSi:120675.0,78164.0,78168.0,108772.0,120083.0,120666.0] || -> . % 76.16/76.32 120677[87:Spt:120676.0,120671.0,120673.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.32 120678[87:Spt:120676.0,120671.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 120682[87:Res:120678.0,61.1] always3(s23) || -> . % 76.16/76.32 120683[87:SSi:120682.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.32 120684[85:Spt:120683.0,120082.0,120083.0] || until2p7(s22)*+ -> . % 76.16/76.32 120685[85:Spt:120683.0,120082.1] || -> node4(s21)*. % 76.16/76.32 120687[85:MRR:855.0,120685.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.32 120690[85:Res:53.1,120687.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.32 120692[86:Spt:120690.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 120694[86:Res:120692.0,61.1] always3(s21) || -> . % 76.16/76.32 120695[86:SSi:120694.0,78160.0,78163.0,108771.0,120081.0,120685.0] || -> . % 76.16/76.32 120696[86:Spt:120695.0,120690.0,120692.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.32 120697[86:Spt:120695.0,120690.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 120701[86:Res:120697.0,61.1] always3(s22) || -> . % 76.16/76.32 120702[86:SSi:120701.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.32 120703[84:Spt:120702.0,120080.0,120081.0] || until2p7(s21)*+ -> . % 76.16/76.32 120704[84:Spt:120702.0,120080.1] || -> node4(s20)*. % 76.16/76.32 120706[84:MRR:858.0,120704.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.32 120709[84:Res:53.1,120706.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.32 120711[84:MRR:120709.0,120070.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 120713[84:Res:120711.0,61.1] always3(s21) || -> . % 76.16/76.32 120714[84:SSi:120713.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.32 120715[82:Spt:120714.0,119956.0,119959.0] || trans(s49,s20)*+ -> . % 76.16/76.32 120716[82:Spt:120714.0,119956.1,119956.2,119956.3,119956.4,119956.5,119956.6,119956.7,119956.8,119956.9,119956.10,119956.11,119956.12,119956.13,119956.14,119956.15,119956.16,119956.17] || -> trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.32 120718[82:MRR:119958.1,120715.0] xuntil6(s49) || -> trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.32 120719[83:Spt:120716.0] || -> trans(s49,s19)*. % 76.16/76.32 120720[83:Res:120719.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s19)*. % 76.16/76.32 120722[83:Res:120719.0,60.0] || -> node2(s49,s19)*. % 76.16/76.32 120723[83:SSi:120720.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s19)*. % 76.16/76.32 120724[83:Res:120722.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 120826[83:SoR:120724.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 120828[83:SoR:120826.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)* xuntil6(s49). % 76.16/76.32 120829[83:SSi:120828.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s19,c_busy)* xuntil6(s49). % 76.16/76.32 120830[84:Spt:120829.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 120832[84:Res:120830.0,61.1] always3(s19) || -> . % 76.16/76.32 120833[84:SSi:120832.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.32 120834[84:Spt:120833.0,120829.1,120830.0] || m_main_v_state(s19,c_busy)*+ -> . % 76.16/76.32 120835[84:Spt:120833.0,120829.0,120829.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.32 120839[84:MRR:120826.2,120834.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.32 120840[84:Res:53.1,120835.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.32 120842[84:MRR:120840.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.32 120843[84:MRR:120723.0,120842.0] || -> until2p7(s19)*. % 76.16/76.32 120844[84:MRR:215.0,120843.0] || -> until2p7(s20)* node4(s19). % 76.16/76.32 120845[85:Spt:120844.0] || -> until2p7(s20)*. % 76.16/76.32 120846[85:MRR:216.0,120845.0] || -> until2p7(s21)* node4(s20). % 76.16/76.32 120847[86:Spt:120846.0] || -> until2p7(s21)*. % 76.16/76.32 120848[86:MRR:217.0,120847.0] || -> until2p7(s22)* node4(s21). % 76.16/76.32 120849[87:Spt:120848.0] || -> until2p7(s22)*. % 76.16/76.32 120850[87:MRR:218.0,120849.0] || -> until2p7(s23)* node4(s22). % 76.16/76.32 120851[88:Spt:120850.0] || -> until2p7(s23)*. % 76.16/76.32 120852[88:MRR:219.0,120851.0] || -> until2p7(s24)* node4(s23). % 76.16/76.32 120853[89:Spt:120852.0] || -> until2p7(s24)*. % 76.16/76.32 120854[89:MRR:220.0,120853.0] || -> until2p7(s25)* node4(s24). % 76.16/76.32 120855[90:Spt:120854.0] || -> until2p7(s25)*. % 76.16/76.32 120856[90:MRR:221.0,120855.0] || -> until2p7(s26)* node4(s25). % 76.16/76.32 120857[91:Spt:120856.0] || -> until2p7(s26)*. % 76.16/76.32 120858[91:MRR:222.0,120857.0] || -> until2p7(s27)* node4(s26). % 76.16/76.32 120859[92:Spt:120858.0] || -> until2p7(s27)*. % 76.16/76.32 120860[92:MRR:223.0,120859.0] || -> until2p7(s28)* node4(s27). % 76.16/76.32 120861[93:Spt:120860.0] || -> until2p7(s28)*. % 76.16/76.32 120862[93:MRR:224.0,120861.0] || -> until2p7(s29)* node4(s28). % 76.16/76.32 120863[94:Spt:120862.0] || -> until2p7(s29)*. % 76.16/76.32 120864[94:MRR:225.0,120863.0] || -> until2p7(s30)* node4(s29). % 76.16/76.32 120865[95:Spt:120864.0] || -> until2p7(s30)*. % 76.16/76.32 120866[95:MRR:226.0,120865.0] || -> until2p7(s31)* node4(s30). % 76.16/76.32 120867[96:Spt:120866.0] || -> until2p7(s31)*. % 76.16/76.32 120868[96:MRR:227.0,120867.0] || -> until2p7(s32)* node4(s31). % 76.16/76.32 120869[97:Spt:120868.0] || -> until2p7(s32)*. % 76.16/76.32 120870[97:MRR:228.0,120869.0] || -> until2p7(s33)* node4(s32). % 76.16/76.32 120871[98:Spt:120870.0] || -> until2p7(s33)*. % 76.16/76.32 120872[98:MRR:229.0,120871.0] || -> until2p7(s34)* node4(s33). % 76.16/76.32 120873[99:Spt:120872.0] || -> until2p7(s34)*. % 76.16/76.32 120874[99:MRR:230.0,120873.0] || -> until2p7(s35)* node4(s34). % 76.16/76.32 120875[100:Spt:120874.0] || -> until2p7(s35)*. % 76.16/76.32 120876[100:MRR:231.0,120875.0] || -> until2p7(s36)* node4(s35). % 76.16/76.32 120877[101:Spt:120876.0] || -> until2p7(s36)*. % 76.16/76.32 120878[101:MRR:232.0,120877.0] || -> until2p7(s37)* node4(s36). % 76.16/76.32 120879[102:Spt:120878.0] || -> until2p7(s37)*. % 76.16/76.32 120880[102:MRR:235.0,120879.0] || -> until2p7(s38)* node4(s37). % 76.16/76.32 120881[103:Spt:120880.0] || -> until2p7(s38)*. % 76.16/76.32 120882[103:MRR:236.0,120881.0] || -> until2p7(s39)* node4(s38). % 76.16/76.32 120883[104:Spt:120882.0] || -> until2p7(s39)*. % 76.16/76.32 120884[104:MRR:237.0,120883.0] || -> until2p7(s40)* node4(s39). % 76.16/76.32 120885[105:Spt:120884.0] || -> until2p7(s40)*. % 76.16/76.32 120886[105:MRR:238.0,120885.0] || -> until2p7(s41)* node4(s40). % 76.16/76.32 120887[106:Spt:120886.0] || -> until2p7(s41)*. % 76.16/76.32 120888[106:MRR:239.0,120887.0] || -> until2p7(s42)* node4(s41). % 76.16/76.32 120889[107:Spt:120888.0] || -> until2p7(s42)*. % 76.16/76.32 120890[107:MRR:240.0,120889.0] || -> until2p7(s43)* node4(s42). % 76.16/76.32 120891[108:Spt:120890.0] || -> until2p7(s43)*. % 76.16/76.32 120892[108:MRR:241.0,120891.0] || -> until2p7(s44)* node4(s43). % 76.16/76.32 120893[109:Spt:120892.0] || -> until2p7(s44)*. % 76.16/76.32 120894[109:MRR:539.0,120893.0] || -> until2p7(s45)* node4(s44). % 76.16/76.32 120895[110:Spt:120894.0] || -> until2p7(s45)*. % 76.16/76.32 120896[110:MRR:544.0,120895.0] || -> until2p7(s46)* node4(s45). % 76.16/76.32 120897[111:Spt:120896.0] || -> until2p7(s46)*. % 76.16/76.32 120898[111:MRR:549.0,120897.0] || -> until2p7(s47)* node4(s46). % 76.16/76.32 120899[112:Spt:120898.0] || -> until2p7(s47)*. % 76.16/76.32 120900[112:MRR:554.0,120899.0] || -> until2p7(s48)* node4(s47). % 76.16/76.32 120901[113:Spt:120900.0] || -> until2p7(s48)*. % 76.16/76.32 120902[113:MRR:559.0,120901.0] || -> until2p7(s49)* node4(s48). % 76.16/76.32 120903[114:Spt:120902.0] || -> until2p7(s49)*. % 76.16/76.32 120904[114:MRR:194.0,120903.0] || -> node4(s49)*. % 76.16/76.32 120905[114:MRR:120839.0,120904.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.32 120906[114:Res:53.1,120905.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.32 120908[114:MRR:120906.0,78381.0] || -> . % 76.16/76.32 120909[114:Spt:120908.0,120902.0,120903.0] || until2p7(s49)*+ -> . % 76.16/76.32 120910[114:Spt:120908.0,120902.1] || -> node4(s48)*. % 76.16/76.32 120911[114:MRR:78384.0,120910.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.32 120914[114:Res:53.1,120911.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 120917[114:Res:120914.0,61.1] always3(s48) || -> . % 76.16/76.32 120918[114:SSi:120917.0,78281.0,78387.0,108798.0,120901.0,120910.0] || -> . % 76.16/76.32 120919[113:Spt:120918.0,120900.0,120901.0] || until2p7(s48)*+ -> . % 76.16/76.32 120920[113:Spt:120918.0,120900.1] || -> node4(s47)*. % 76.16/76.32 120922[113:MRR:777.0,120920.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.32 120937[113:Res:53.1,120922.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.32 120939[114:Spt:120937.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 120941[114:Res:120939.0,61.1] always3(s47) || -> . % 76.16/76.32 120942[114:SSi:120941.0,78277.0,78280.0,108797.0,120899.0,120920.0] || -> . % 76.16/76.32 120943[114:Spt:120942.0,120937.0,120939.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.32 120944[114:Spt:120942.0,120937.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 120948[114:Res:120944.0,61.1] always3(s48) || -> . % 76.16/76.32 120949[114:SSi:120948.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.32 120950[112:Spt:120949.0,120898.0,120899.0] || until2p7(s47)*+ -> . % 76.16/76.32 120951[112:Spt:120949.0,120898.1] || -> node4(s46)*. % 76.16/76.32 120953[112:MRR:780.0,120951.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.32 120963[112:Res:53.1,120953.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.32 120965[113:Spt:120963.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 120967[113:Res:120965.0,61.1] always3(s46) || -> . % 76.16/76.32 120968[113:SSi:120967.0,78272.0,78276.0,108796.0,120897.0,120951.0] || -> . % 76.16/76.32 120969[113:Spt:120968.0,120963.0,120965.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.32 120970[113:Spt:120968.0,120963.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 120974[113:Res:120970.0,61.1] always3(s47) || -> . % 76.16/76.32 120975[113:SSi:120974.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.32 120976[111:Spt:120975.0,120896.0,120897.0] || until2p7(s46)*+ -> . % 76.16/76.32 120977[111:Spt:120975.0,120896.1] || -> node4(s45)*. % 76.16/76.32 120979[111:MRR:783.0,120977.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.32 120982[111:Res:53.1,120979.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.32 120984[112:Spt:120982.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 120986[112:Res:120984.0,61.1] always3(s45) || -> . % 76.16/76.32 120987[112:SSi:120986.0,78268.0,78271.0,108795.0,120895.0,120977.0] || -> . % 76.16/76.32 120988[112:Spt:120987.0,120982.0,120984.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.32 120989[112:Spt:120987.0,120982.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 120993[112:Res:120989.0,61.1] always3(s46) || -> . % 76.16/76.32 120994[112:SSi:120993.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.32 120995[110:Spt:120994.0,120894.0,120895.0] || until2p7(s45)*+ -> . % 76.16/76.32 120996[110:Spt:120994.0,120894.1] || -> node4(s44)*. % 76.16/76.32 120998[110:MRR:786.0,120996.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.32 121001[110:Res:53.1,120998.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.32 121003[111:Spt:121001.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 121005[111:Res:121003.0,61.1] always3(s44) || -> . % 76.16/76.32 121006[111:SSi:121005.0,78263.0,78267.0,108794.0,120893.0,120996.0] || -> . % 76.16/76.32 121007[111:Spt:121006.0,121001.0,121003.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.32 121008[111:Spt:121006.0,121001.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 121012[111:Res:121008.0,61.1] always3(s45) || -> . % 76.16/76.32 121013[111:SSi:121012.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.32 121014[109:Spt:121013.0,120892.0,120893.0] || until2p7(s44)*+ -> . % 76.16/76.32 121015[109:Spt:121013.0,120892.1] || -> node4(s43)*. % 76.16/76.32 121017[109:MRR:789.0,121015.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.32 121020[109:Res:53.1,121017.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.32 121025[110:Spt:121020.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 121027[110:Res:121025.0,61.1] always3(s43) || -> . % 76.16/76.32 121028[110:SSi:121027.0,78259.0,78262.0,108793.0,120891.0,121015.0] || -> . % 76.16/76.32 121029[110:Spt:121028.0,121020.0,121025.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.32 121030[110:Spt:121028.0,121020.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 121034[110:Res:121030.0,61.1] always3(s44) || -> . % 76.16/76.32 121035[110:SSi:121034.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.32 121036[108:Spt:121035.0,120890.0,120891.0] || until2p7(s43)*+ -> . % 76.16/76.32 121037[108:Spt:121035.0,120890.1] || -> node4(s42)*. % 76.16/76.32 121039[108:MRR:792.0,121037.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.32 121042[108:Res:53.1,121039.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.32 121044[109:Spt:121042.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 121046[109:Res:121044.0,61.1] always3(s42) || -> . % 76.16/76.32 121047[109:SSi:121046.0,78254.0,78258.0,108792.0,120889.0,121037.0] || -> . % 76.16/76.32 121048[109:Spt:121047.0,121042.0,121044.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.32 121049[109:Spt:121047.0,121042.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 121053[109:Res:121049.0,61.1] always3(s43) || -> . % 76.16/76.32 121054[109:SSi:121053.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.32 121055[107:Spt:121054.0,120888.0,120889.0] || until2p7(s42)*+ -> . % 76.16/76.32 121056[107:Spt:121054.0,120888.1] || -> node4(s41)*. % 76.16/76.32 121058[107:MRR:795.0,121056.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.32 121061[107:Res:53.1,121058.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.32 121063[108:Spt:121061.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 121065[108:Res:121063.0,61.1] always3(s41) || -> . % 76.16/76.32 121066[108:SSi:121065.0,78250.0,78253.0,108791.0,120887.0,121056.0] || -> . % 76.16/76.32 121067[108:Spt:121066.0,121061.0,121063.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.32 121068[108:Spt:121066.0,121061.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 121072[108:Res:121068.0,61.1] always3(s42) || -> . % 76.16/76.32 121073[108:SSi:121072.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.32 121074[106:Spt:121073.0,120886.0,120887.0] || until2p7(s41)*+ -> . % 76.16/76.32 121075[106:Spt:121073.0,120886.1] || -> node4(s40)*. % 76.16/76.32 121077[106:MRR:798.0,121075.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.32 121080[106:Res:53.1,121077.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.32 121082[107:Spt:121080.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 121084[107:Res:121082.0,61.1] always3(s40) || -> . % 76.16/76.32 121085[107:SSi:121084.0,78245.0,78249.0,108790.0,120885.0,121075.0] || -> . % 76.16/76.32 121086[107:Spt:121085.0,121080.0,121082.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.32 121087[107:Spt:121085.0,121080.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 121091[107:Res:121087.0,61.1] always3(s41) || -> . % 76.16/76.32 121092[107:SSi:121091.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.32 121093[105:Spt:121092.0,120884.0,120885.0] || until2p7(s40)*+ -> . % 76.16/76.32 121094[105:Spt:121092.0,120884.1] || -> node4(s39)*. % 76.16/76.32 121096[105:MRR:801.0,121094.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.32 121099[105:Res:53.1,121096.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.32 121104[106:Spt:121099.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 121106[106:Res:121104.0,61.1] always3(s39) || -> . % 76.16/76.32 121107[106:SSi:121106.0,78241.0,78244.0,108789.0,120883.0,121094.0] || -> . % 76.16/76.32 121108[106:Spt:121107.0,121099.0,121104.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.32 121109[106:Spt:121107.0,121099.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 121113[106:Res:121109.0,61.1] always3(s40) || -> . % 76.16/76.32 121114[106:SSi:121113.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.32 121115[104:Spt:121114.0,120882.0,120883.0] || until2p7(s39)*+ -> . % 76.16/76.32 121116[104:Spt:121114.0,120882.1] || -> node4(s38)*. % 76.16/76.32 121118[104:MRR:804.0,121116.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.32 121121[104:Res:53.1,121118.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.32 121123[105:Spt:121121.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 121125[105:Res:121123.0,61.1] always3(s38) || -> . % 76.16/76.32 121126[105:SSi:121125.0,78236.0,78240.0,108788.0,120881.0,121116.0] || -> . % 76.16/76.32 121127[105:Spt:121126.0,121121.0,121123.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.32 121128[105:Spt:121126.0,121121.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 121132[105:Res:121128.0,61.1] always3(s39) || -> . % 76.16/76.32 121133[105:SSi:121132.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.32 121134[103:Spt:121133.0,120880.0,120881.0] || until2p7(s38)*+ -> . % 76.16/76.32 121135[103:Spt:121133.0,120880.1] || -> node4(s37)*. % 76.16/76.32 121137[103:MRR:807.0,121135.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.32 121140[103:Res:53.1,121137.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.32 121142[104:Spt:121140.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 121144[104:Res:121142.0,61.1] always3(s37) || -> . % 76.16/76.32 121145[104:SSi:121144.0,78232.0,78235.0,108787.0,120879.0,121135.0] || -> . % 76.16/76.32 121146[104:Spt:121145.0,121140.0,121142.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.32 121147[104:Spt:121145.0,121140.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 121151[104:Res:121147.0,61.1] always3(s38) || -> . % 76.16/76.32 121152[104:SSi:121151.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.32 121153[102:Spt:121152.0,120878.0,120879.0] || until2p7(s37)*+ -> . % 76.16/76.32 121154[102:Spt:121152.0,120878.1] || -> node4(s36)*. % 76.16/76.32 121156[102:MRR:810.0,121154.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.32 121159[102:Res:53.1,121156.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.32 121161[103:Spt:121159.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 121163[103:Res:121161.0,61.1] always3(s36) || -> . % 76.16/76.32 121164[103:SSi:121163.0,78227.0,78231.0,108786.0,120877.0,121154.0] || -> . % 76.16/76.32 121165[103:Spt:121164.0,121159.0,121161.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.32 121166[103:Spt:121164.0,121159.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 121170[103:Res:121166.0,61.1] always3(s37) || -> . % 76.16/76.32 121171[103:SSi:121170.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.32 121172[101:Spt:121171.0,120876.0,120877.0] || until2p7(s36)*+ -> . % 76.16/76.32 121173[101:Spt:121171.0,120876.1] || -> node4(s35)*. % 76.16/76.32 121175[101:MRR:813.0,121173.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.32 121178[101:Res:53.1,121175.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.32 121183[102:Spt:121178.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 121185[102:Res:121183.0,61.1] always3(s35) || -> . % 76.16/76.32 121186[102:SSi:121185.0,78223.0,78226.0,108785.0,120875.0,121173.0] || -> . % 76.16/76.32 121187[102:Spt:121186.0,121178.0,121183.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.32 121188[102:Spt:121186.0,121178.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 121192[102:Res:121188.0,61.1] always3(s36) || -> . % 76.16/76.32 121193[102:SSi:121192.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.32 121194[100:Spt:121193.0,120874.0,120875.0] || until2p7(s35)*+ -> . % 76.16/76.32 121195[100:Spt:121193.0,120874.1] || -> node4(s34)*. % 76.16/76.32 121197[100:MRR:816.0,121195.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.32 121200[100:Res:53.1,121197.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.32 121202[101:Spt:121200.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 121204[101:Res:121202.0,61.1] always3(s34) || -> . % 76.16/76.32 121205[101:SSi:121204.0,78218.0,78222.0,108784.0,120873.0,121195.0] || -> . % 76.16/76.32 121206[101:Spt:121205.0,121200.0,121202.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.32 121207[101:Spt:121205.0,121200.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 121211[101:Res:121207.0,61.1] always3(s35) || -> . % 76.16/76.32 121212[101:SSi:121211.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.32 121213[99:Spt:121212.0,120872.0,120873.0] || until2p7(s34)*+ -> . % 76.16/76.32 121214[99:Spt:121212.0,120872.1] || -> node4(s33)*. % 76.16/76.32 121216[99:MRR:819.0,121214.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.32 121219[99:Res:53.1,121216.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.32 121221[100:Spt:121219.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 121223[100:Res:121221.0,61.1] always3(s33) || -> . % 76.16/76.32 121224[100:SSi:121223.0,78214.0,78217.0,108783.0,120871.0,121214.0] || -> . % 76.16/76.32 121225[100:Spt:121224.0,121219.0,121221.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.32 121226[100:Spt:121224.0,121219.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 121230[100:Res:121226.0,61.1] always3(s34) || -> . % 76.16/76.32 121231[100:SSi:121230.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.32 121232[98:Spt:121231.0,120870.0,120871.0] || until2p7(s33)*+ -> . % 76.16/76.32 121233[98:Spt:121231.0,120870.1] || -> node4(s32)*. % 76.16/76.32 121235[98:MRR:822.0,121233.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.32 121238[98:Res:53.1,121235.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.32 121240[99:Spt:121238.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 121242[99:Res:121240.0,61.1] always3(s32) || -> . % 76.16/76.32 121243[99:SSi:121242.0,78209.0,78213.0,108782.0,120869.0,121233.0] || -> . % 76.16/76.32 121244[99:Spt:121243.0,121238.0,121240.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.32 121245[99:Spt:121243.0,121238.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 121249[99:Res:121245.0,61.1] always3(s33) || -> . % 76.16/76.32 121250[99:SSi:121249.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.32 121251[97:Spt:121250.0,120868.0,120869.0] || until2p7(s32)*+ -> . % 76.16/76.32 121252[97:Spt:121250.0,120868.1] || -> node4(s31)*. % 76.16/76.32 121254[97:MRR:825.0,121252.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.32 121257[97:Res:53.1,121254.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.32 121262[98:Spt:121257.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 121264[98:Res:121262.0,61.1] always3(s31) || -> . % 76.16/76.32 121265[98:SSi:121264.0,78205.0,78208.0,108781.0,120867.0,121252.0] || -> . % 76.16/76.32 121266[98:Spt:121265.0,121257.0,121262.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.32 121267[98:Spt:121265.0,121257.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 121271[98:Res:121267.0,61.1] always3(s32) || -> . % 76.16/76.32 121272[98:SSi:121271.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.32 121273[96:Spt:121272.0,120866.0,120867.0] || until2p7(s31)*+ -> . % 76.16/76.32 121274[96:Spt:121272.0,120866.1] || -> node4(s30)*. % 76.16/76.32 121276[96:MRR:828.0,121274.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.32 121279[96:Res:53.1,121276.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.32 121281[97:Spt:121279.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 121283[97:Res:121281.0,61.1] always3(s30) || -> . % 76.16/76.32 121284[97:SSi:121283.0,78200.0,78204.0,108780.0,120865.0,121274.0] || -> . % 76.16/76.32 121285[97:Spt:121284.0,121279.0,121281.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.32 121286[97:Spt:121284.0,121279.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 121290[97:Res:121286.0,61.1] always3(s31) || -> . % 76.16/76.32 121291[97:SSi:121290.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.32 121292[95:Spt:121291.0,120864.0,120865.0] || until2p7(s30)*+ -> . % 76.16/76.32 121293[95:Spt:121291.0,120864.1] || -> node4(s29)*. % 76.16/76.32 121295[95:MRR:831.0,121293.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.32 121298[95:Res:53.1,121295.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.32 121300[96:Spt:121298.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 121302[96:Res:121300.0,61.1] always3(s29) || -> . % 76.16/76.32 121303[96:SSi:121302.0,78196.0,78199.0,108779.0,120863.0,121293.0] || -> . % 76.16/76.32 121304[96:Spt:121303.0,121298.0,121300.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.32 121305[96:Spt:121303.0,121298.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 121309[96:Res:121305.0,61.1] always3(s30) || -> . % 76.16/76.32 121310[96:SSi:121309.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.32 121311[94:Spt:121310.0,120862.0,120863.0] || until2p7(s29)*+ -> . % 76.16/76.32 121312[94:Spt:121310.0,120862.1] || -> node4(s28)*. % 76.16/76.32 121314[94:MRR:834.0,121312.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.32 121317[94:Res:53.1,121314.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.32 121319[95:Spt:121317.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 121321[95:Res:121319.0,61.1] always3(s28) || -> . % 76.16/76.32 121322[95:SSi:121321.0,78191.0,78195.0,108778.0,120861.0,121312.0] || -> . % 76.16/76.32 121323[95:Spt:121322.0,121317.0,121319.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.32 121324[95:Spt:121322.0,121317.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 121328[95:Res:121324.0,61.1] always3(s29) || -> . % 76.16/76.32 121329[95:SSi:121328.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.32 121330[93:Spt:121329.0,120860.0,120861.0] || until2p7(s28)*+ -> . % 76.16/76.32 121331[93:Spt:121329.0,120860.1] || -> node4(s27)*. % 76.16/76.32 121333[93:MRR:837.0,121331.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.32 121336[93:Res:53.1,121333.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.32 121341[94:Spt:121336.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 121343[94:Res:121341.0,61.1] always3(s27) || -> . % 76.16/76.32 121344[94:SSi:121343.0,78187.0,78190.0,108777.0,120859.0,121331.0] || -> . % 76.16/76.32 121345[94:Spt:121344.0,121336.0,121341.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.32 121346[94:Spt:121344.0,121336.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 121350[94:Res:121346.0,61.1] always3(s28) || -> . % 76.16/76.32 121351[94:SSi:121350.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.32 121352[92:Spt:121351.0,120858.0,120859.0] || until2p7(s27)*+ -> . % 76.16/76.32 121353[92:Spt:121351.0,120858.1] || -> node4(s26)*. % 76.16/76.32 121355[92:MRR:840.0,121353.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.32 121358[92:Res:53.1,121355.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.32 121360[93:Spt:121358.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 121362[93:Res:121360.0,61.1] always3(s26) || -> . % 76.16/76.32 121363[93:SSi:121362.0,78182.0,78186.0,108776.0,120857.0,121353.0] || -> . % 76.16/76.32 121364[93:Spt:121363.0,121358.0,121360.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.32 121365[93:Spt:121363.0,121358.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 121369[93:Res:121365.0,61.1] always3(s27) || -> . % 76.16/76.32 121370[93:SSi:121369.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.32 121371[91:Spt:121370.0,120856.0,120857.0] || until2p7(s26)*+ -> . % 76.16/76.32 121372[91:Spt:121370.0,120856.1] || -> node4(s25)*. % 76.16/76.32 121374[91:MRR:843.0,121372.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.32 121377[91:Res:53.1,121374.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.32 121379[92:Spt:121377.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 121381[92:Res:121379.0,61.1] always3(s25) || -> . % 76.16/76.32 121382[92:SSi:121381.0,78178.0,78181.0,108775.0,120855.0,121372.0] || -> . % 76.16/76.32 121383[92:Spt:121382.0,121377.0,121379.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.32 121384[92:Spt:121382.0,121377.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 121388[92:Res:121384.0,61.1] always3(s26) || -> . % 76.16/76.32 121389[92:SSi:121388.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.32 121390[90:Spt:121389.0,120854.0,120855.0] || until2p7(s25)*+ -> . % 76.16/76.32 121391[90:Spt:121389.0,120854.1] || -> node4(s24)*. % 76.16/76.32 121393[90:MRR:846.0,121391.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.32 121396[90:Res:53.1,121393.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.32 121398[91:Spt:121396.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 121400[91:Res:121398.0,61.1] always3(s24) || -> . % 76.16/76.32 121401[91:SSi:121400.0,78173.0,78177.0,108774.0,120853.0,121391.0] || -> . % 76.16/76.32 121402[91:Spt:121401.0,121396.0,121398.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.32 121403[91:Spt:121401.0,121396.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 121407[91:Res:121403.0,61.1] always3(s25) || -> . % 76.16/76.32 121408[91:SSi:121407.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.32 121409[89:Spt:121408.0,120852.0,120853.0] || until2p7(s24)*+ -> . % 76.16/76.32 121410[89:Spt:121408.0,120852.1] || -> node4(s23)*. % 76.16/76.32 121412[89:MRR:849.0,121410.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.32 121415[89:Res:53.1,121412.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.32 121420[90:Spt:121415.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 121422[90:Res:121420.0,61.1] always3(s23) || -> . % 76.16/76.32 121423[90:SSi:121422.0,78169.0,78172.0,108773.0,120851.0,121410.0] || -> . % 76.16/76.32 121424[90:Spt:121423.0,121415.0,121420.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.32 121425[90:Spt:121423.0,121415.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 121429[90:Res:121425.0,61.1] always3(s24) || -> . % 76.16/76.32 121430[90:SSi:121429.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.32 121431[88:Spt:121430.0,120850.0,120851.0] || until2p7(s23)*+ -> . % 76.16/76.32 121432[88:Spt:121430.0,120850.1] || -> node4(s22)*. % 76.16/76.32 121434[88:MRR:852.0,121432.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.32 121437[88:Res:53.1,121434.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.32 121439[89:Spt:121437.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 121441[89:Res:121439.0,61.1] always3(s22) || -> . % 76.16/76.32 121442[89:SSi:121441.0,78164.0,78168.0,108772.0,120849.0,121432.0] || -> . % 76.16/76.32 121443[89:Spt:121442.0,121437.0,121439.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.32 121444[89:Spt:121442.0,121437.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 121448[89:Res:121444.0,61.1] always3(s23) || -> . % 76.16/76.32 121449[89:SSi:121448.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.32 121450[87:Spt:121449.0,120848.0,120849.0] || until2p7(s22)*+ -> . % 76.16/76.32 121451[87:Spt:121449.0,120848.1] || -> node4(s21)*. % 76.16/76.32 121453[87:MRR:855.0,121451.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.32 121456[87:Res:53.1,121453.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.32 121458[88:Spt:121456.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 121460[88:Res:121458.0,61.1] always3(s21) || -> . % 76.16/76.32 121461[88:SSi:121460.0,78160.0,78163.0,108771.0,120847.0,121451.0] || -> . % 76.16/76.32 121462[88:Spt:121461.0,121456.0,121458.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.32 121463[88:Spt:121461.0,121456.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 121467[88:Res:121463.0,61.1] always3(s22) || -> . % 76.16/76.32 121468[88:SSi:121467.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.32 121469[86:Spt:121468.0,120846.0,120847.0] || until2p7(s21)*+ -> . % 76.16/76.32 121470[86:Spt:121468.0,120846.1] || -> node4(s20)*. % 76.16/76.32 121472[86:MRR:858.0,121470.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.32 121475[86:Res:53.1,121472.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.32 121477[87:Spt:121475.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 121479[87:Res:121477.0,61.1] always3(s20) || -> . % 76.16/76.32 121480[87:SSi:121479.0,78155.0,78159.0,108770.0,120845.0,121470.0] || -> . % 76.16/76.32 121481[87:Spt:121480.0,121475.0,121477.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.32 121482[87:Spt:121480.0,121475.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 121486[87:Res:121482.0,61.1] always3(s21) || -> . % 76.16/76.32 121487[87:SSi:121486.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.32 121488[85:Spt:121487.0,120844.0,120845.0] || until2p7(s20)*+ -> . % 76.16/76.32 121489[85:Spt:121487.0,120844.1] || -> node4(s19)*. % 76.16/76.32 121491[85:MRR:861.0,121489.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.32 121494[85:Res:53.1,121491.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.32 121496[85:MRR:121494.0,120834.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 121501[85:Res:121496.0,61.1] always3(s20) || -> . % 76.16/76.32 121502[85:SSi:121501.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.32 121503[83:Spt:121502.0,120716.0,120719.0] || trans(s49,s19)*+ -> . % 76.16/76.32 121504[83:Spt:121502.0,120716.1,120716.2,120716.3,120716.4,120716.5,120716.6,120716.7,120716.8,120716.9,120716.10,120716.11,120716.12,120716.13,120716.14,120716.15,120716.16] || -> trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.32 121506[83:MRR:120718.1,121503.0] xuntil6(s49) || -> trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.32 121507[84:Spt:121504.0] || -> trans(s49,s18)*. % 76.16/76.32 121508[84:Res:121507.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s18)*. % 76.16/76.32 121510[84:Res:121507.0,60.0] || -> node2(s49,s18)*. % 76.16/76.32 121511[84:SSi:121508.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s18)*. % 76.16/76.32 121512[84:Res:121510.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 121615[84:SoR:121512.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 121617[84:SoR:121615.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)* xuntil6(s49). % 76.16/76.32 121618[84:SSi:121617.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s18,c_busy)* xuntil6(s49). % 76.16/76.32 121619[85:Spt:121618.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 121621[85:Res:121619.0,61.1] always3(s18) || -> . % 76.16/76.32 121622[85:SSi:121621.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.32 121623[85:Spt:121622.0,121618.1,121619.0] || m_main_v_state(s18,c_busy)*+ -> . % 76.16/76.32 121624[85:Spt:121622.0,121618.0,121618.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.32 121628[85:MRR:121615.2,121623.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.32 121629[85:Res:53.1,121624.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.32 121631[85:MRR:121629.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.32 121632[85:MRR:121511.0,121631.0] || -> until2p7(s18)*. % 76.16/76.32 121633[85:MRR:214.0,121632.0] || -> until2p7(s19)* node4(s18). % 76.16/76.32 121634[86:Spt:121633.0] || -> until2p7(s19)*. % 76.16/76.32 121635[86:MRR:215.0,121634.0] || -> until2p7(s20)* node4(s19). % 76.16/76.32 121636[87:Spt:121635.0] || -> until2p7(s20)*. % 76.16/76.32 121637[87:MRR:216.0,121636.0] || -> until2p7(s21)* node4(s20). % 76.16/76.32 121638[88:Spt:121637.0] || -> until2p7(s21)*. % 76.16/76.32 121639[88:MRR:217.0,121638.0] || -> until2p7(s22)* node4(s21). % 76.16/76.32 121640[89:Spt:121639.0] || -> until2p7(s22)*. % 76.16/76.32 121641[89:MRR:218.0,121640.0] || -> until2p7(s23)* node4(s22). % 76.16/76.32 121642[90:Spt:121641.0] || -> until2p7(s23)*. % 76.16/76.32 121643[90:MRR:219.0,121642.0] || -> until2p7(s24)* node4(s23). % 76.16/76.32 121644[91:Spt:121643.0] || -> until2p7(s24)*. % 76.16/76.32 121645[91:MRR:220.0,121644.0] || -> until2p7(s25)* node4(s24). % 76.16/76.32 121646[92:Spt:121645.0] || -> until2p7(s25)*. % 76.16/76.32 121647[92:MRR:221.0,121646.0] || -> until2p7(s26)* node4(s25). % 76.16/76.32 121648[93:Spt:121647.0] || -> until2p7(s26)*. % 76.16/76.32 121649[93:MRR:222.0,121648.0] || -> until2p7(s27)* node4(s26). % 76.16/76.32 121650[94:Spt:121649.0] || -> until2p7(s27)*. % 76.16/76.32 121651[94:MRR:223.0,121650.0] || -> until2p7(s28)* node4(s27). % 76.16/76.32 121652[95:Spt:121651.0] || -> until2p7(s28)*. % 76.16/76.32 121653[95:MRR:224.0,121652.0] || -> until2p7(s29)* node4(s28). % 76.16/76.32 121654[96:Spt:121653.0] || -> until2p7(s29)*. % 76.16/76.32 121655[96:MRR:225.0,121654.0] || -> until2p7(s30)* node4(s29). % 76.16/76.32 121656[97:Spt:121655.0] || -> until2p7(s30)*. % 76.16/76.32 121657[97:MRR:226.0,121656.0] || -> until2p7(s31)* node4(s30). % 76.16/76.32 121658[98:Spt:121657.0] || -> until2p7(s31)*. % 76.16/76.32 121659[98:MRR:227.0,121658.0] || -> until2p7(s32)* node4(s31). % 76.16/76.32 121660[99:Spt:121659.0] || -> until2p7(s32)*. % 76.16/76.32 121661[99:MRR:228.0,121660.0] || -> until2p7(s33)* node4(s32). % 76.16/76.32 121662[100:Spt:121661.0] || -> until2p7(s33)*. % 76.16/76.32 121663[100:MRR:229.0,121662.0] || -> until2p7(s34)* node4(s33). % 76.16/76.32 121664[101:Spt:121663.0] || -> until2p7(s34)*. % 76.16/76.32 121665[101:MRR:230.0,121664.0] || -> until2p7(s35)* node4(s34). % 76.16/76.32 121666[102:Spt:121665.0] || -> until2p7(s35)*. % 76.16/76.32 121667[102:MRR:231.0,121666.0] || -> until2p7(s36)* node4(s35). % 76.16/76.32 121668[103:Spt:121667.0] || -> until2p7(s36)*. % 76.16/76.32 121669[103:MRR:232.0,121668.0] || -> until2p7(s37)* node4(s36). % 76.16/76.32 121670[104:Spt:121669.0] || -> until2p7(s37)*. % 76.16/76.32 121671[104:MRR:235.0,121670.0] || -> until2p7(s38)* node4(s37). % 76.16/76.32 121672[105:Spt:121671.0] || -> until2p7(s38)*. % 76.16/76.32 121673[105:MRR:236.0,121672.0] || -> until2p7(s39)* node4(s38). % 76.16/76.32 121674[106:Spt:121673.0] || -> until2p7(s39)*. % 76.16/76.32 121675[106:MRR:237.0,121674.0] || -> until2p7(s40)* node4(s39). % 76.16/76.32 121676[107:Spt:121675.0] || -> until2p7(s40)*. % 76.16/76.32 121677[107:MRR:238.0,121676.0] || -> until2p7(s41)* node4(s40). % 76.16/76.32 121678[108:Spt:121677.0] || -> until2p7(s41)*. % 76.16/76.32 121679[108:MRR:239.0,121678.0] || -> until2p7(s42)* node4(s41). % 76.16/76.32 121680[109:Spt:121679.0] || -> until2p7(s42)*. % 76.16/76.32 121681[109:MRR:240.0,121680.0] || -> until2p7(s43)* node4(s42). % 76.16/76.32 121682[110:Spt:121681.0] || -> until2p7(s43)*. % 76.16/76.32 121683[110:MRR:241.0,121682.0] || -> until2p7(s44)* node4(s43). % 76.16/76.32 121684[111:Spt:121683.0] || -> until2p7(s44)*. % 76.16/76.32 121685[111:MRR:539.0,121684.0] || -> until2p7(s45)* node4(s44). % 76.16/76.32 121686[112:Spt:121685.0] || -> until2p7(s45)*. % 76.16/76.32 121687[112:MRR:544.0,121686.0] || -> until2p7(s46)* node4(s45). % 76.16/76.32 121688[113:Spt:121687.0] || -> until2p7(s46)*. % 76.16/76.32 121689[113:MRR:549.0,121688.0] || -> until2p7(s47)* node4(s46). % 76.16/76.32 121690[114:Spt:121689.0] || -> until2p7(s47)*. % 76.16/76.32 121691[114:MRR:554.0,121690.0] || -> until2p7(s48)* node4(s47). % 76.16/76.32 121692[115:Spt:121691.0] || -> until2p7(s48)*. % 76.16/76.32 121693[115:MRR:559.0,121692.0] || -> until2p7(s49)* node4(s48). % 76.16/76.32 121694[116:Spt:121693.0] || -> until2p7(s49)*. % 76.16/76.32 121695[116:MRR:194.0,121694.0] || -> node4(s49)*. % 76.16/76.32 121696[116:MRR:121628.0,121695.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.32 121700[116:Res:53.1,121696.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.32 121702[116:MRR:121700.0,78381.0] || -> . % 76.16/76.32 121703[116:Spt:121702.0,121693.0,121694.0] || until2p7(s49)*+ -> . % 76.16/76.32 121704[116:Spt:121702.0,121693.1] || -> node4(s48)*. % 76.16/76.32 121705[116:MRR:78384.0,121704.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.32 121708[116:Res:53.1,121705.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 121711[116:Res:121708.0,61.1] always3(s48) || -> . % 76.16/76.32 121712[116:SSi:121711.0,78281.0,78387.0,108798.0,121692.0,121704.0] || -> . % 76.16/76.32 121713[115:Spt:121712.0,121691.0,121692.0] || until2p7(s48)*+ -> . % 76.16/76.32 121714[115:Spt:121712.0,121691.1] || -> node4(s47)*. % 76.16/76.32 121716[115:MRR:777.0,121714.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.32 121728[115:Res:53.1,121716.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.32 121730[116:Spt:121728.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 121732[116:Res:121730.0,61.1] always3(s47) || -> . % 76.16/76.32 121733[116:SSi:121732.0,78277.0,78280.0,108797.0,121690.0,121714.0] || -> . % 76.16/76.32 121734[116:Spt:121733.0,121728.0,121730.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.32 121735[116:Spt:121733.0,121728.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 121739[116:Res:121735.0,61.1] always3(s48) || -> . % 76.16/76.32 121740[116:SSi:121739.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.32 121741[114:Spt:121740.0,121689.0,121690.0] || until2p7(s47)*+ -> . % 76.16/76.32 121742[114:Spt:121740.0,121689.1] || -> node4(s46)*. % 76.16/76.32 121744[114:MRR:780.0,121742.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.32 121751[114:Res:53.1,121744.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.32 121756[115:Spt:121751.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 121758[115:Res:121756.0,61.1] always3(s46) || -> . % 76.16/76.32 121759[115:SSi:121758.0,78272.0,78276.0,108796.0,121688.0,121742.0] || -> . % 76.16/76.32 121760[115:Spt:121759.0,121751.0,121756.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.32 121761[115:Spt:121759.0,121751.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 121765[115:Res:121761.0,61.1] always3(s47) || -> . % 76.16/76.32 121766[115:SSi:121765.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.32 121767[113:Spt:121766.0,121687.0,121688.0] || until2p7(s46)*+ -> . % 76.16/76.32 121768[113:Spt:121766.0,121687.1] || -> node4(s45)*. % 76.16/76.32 121770[113:MRR:783.0,121768.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.32 121773[113:Res:53.1,121770.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.32 121775[114:Spt:121773.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 121777[114:Res:121775.0,61.1] always3(s45) || -> . % 76.16/76.32 121778[114:SSi:121777.0,78268.0,78271.0,108795.0,121686.0,121768.0] || -> . % 76.16/76.32 121779[114:Spt:121778.0,121773.0,121775.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.32 121780[114:Spt:121778.0,121773.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 121784[114:Res:121780.0,61.1] always3(s46) || -> . % 76.16/76.32 121785[114:SSi:121784.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.32 121786[112:Spt:121785.0,121685.0,121686.0] || until2p7(s45)*+ -> . % 76.16/76.32 121787[112:Spt:121785.0,121685.1] || -> node4(s44)*. % 76.16/76.32 121789[112:MRR:786.0,121787.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.32 121792[112:Res:53.1,121789.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.32 121794[113:Spt:121792.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 121796[113:Res:121794.0,61.1] always3(s44) || -> . % 76.16/76.32 121797[113:SSi:121796.0,78263.0,78267.0,108794.0,121684.0,121787.0] || -> . % 76.16/76.32 121798[113:Spt:121797.0,121792.0,121794.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.32 121799[113:Spt:121797.0,121792.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 121803[113:Res:121799.0,61.1] always3(s45) || -> . % 76.16/76.32 121804[113:SSi:121803.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.32 121805[111:Spt:121804.0,121683.0,121684.0] || until2p7(s44)*+ -> . % 76.16/76.32 121806[111:Spt:121804.0,121683.1] || -> node4(s43)*. % 76.16/76.32 121808[111:MRR:789.0,121806.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.32 121811[111:Res:53.1,121808.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.32 121813[112:Spt:121811.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 121815[112:Res:121813.0,61.1] always3(s43) || -> . % 76.16/76.32 121816[112:SSi:121815.0,78259.0,78262.0,108793.0,121682.0,121806.0] || -> . % 76.16/76.32 121817[112:Spt:121816.0,121811.0,121813.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.32 121818[112:Spt:121816.0,121811.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 121822[112:Res:121818.0,61.1] always3(s44) || -> . % 76.16/76.32 121823[112:SSi:121822.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.32 121824[110:Spt:121823.0,121681.0,121682.0] || until2p7(s43)*+ -> . % 76.16/76.32 121825[110:Spt:121823.0,121681.1] || -> node4(s42)*. % 76.16/76.32 121827[110:MRR:792.0,121825.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.32 121830[110:Res:53.1,121827.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.32 121835[111:Spt:121830.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 121837[111:Res:121835.0,61.1] always3(s42) || -> . % 76.16/76.32 121838[111:SSi:121837.0,78254.0,78258.0,108792.0,121680.0,121825.0] || -> . % 76.16/76.32 121839[111:Spt:121838.0,121830.0,121835.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.32 121840[111:Spt:121838.0,121830.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 121844[111:Res:121840.0,61.1] always3(s43) || -> . % 76.16/76.32 121845[111:SSi:121844.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.32 121846[109:Spt:121845.0,121679.0,121680.0] || until2p7(s42)*+ -> . % 76.16/76.32 121847[109:Spt:121845.0,121679.1] || -> node4(s41)*. % 76.16/76.32 121849[109:MRR:795.0,121847.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.32 121852[109:Res:53.1,121849.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.32 121854[110:Spt:121852.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 121856[110:Res:121854.0,61.1] always3(s41) || -> . % 76.16/76.32 121857[110:SSi:121856.0,78250.0,78253.0,108791.0,121678.0,121847.0] || -> . % 76.16/76.32 121858[110:Spt:121857.0,121852.0,121854.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.32 121859[110:Spt:121857.0,121852.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 121863[110:Res:121859.0,61.1] always3(s42) || -> . % 76.16/76.32 121864[110:SSi:121863.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.32 121865[108:Spt:121864.0,121677.0,121678.0] || until2p7(s41)*+ -> . % 76.16/76.32 121866[108:Spt:121864.0,121677.1] || -> node4(s40)*. % 76.16/76.32 121868[108:MRR:798.0,121866.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.32 121871[108:Res:53.1,121868.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.32 121873[109:Spt:121871.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 121875[109:Res:121873.0,61.1] always3(s40) || -> . % 76.16/76.32 121876[109:SSi:121875.0,78245.0,78249.0,108790.0,121676.0,121866.0] || -> . % 76.16/76.32 121877[109:Spt:121876.0,121871.0,121873.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.32 121878[109:Spt:121876.0,121871.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 121882[109:Res:121878.0,61.1] always3(s41) || -> . % 76.16/76.32 121883[109:SSi:121882.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.32 121884[107:Spt:121883.0,121675.0,121676.0] || until2p7(s40)*+ -> . % 76.16/76.32 121885[107:Spt:121883.0,121675.1] || -> node4(s39)*. % 76.16/76.32 121887[107:MRR:801.0,121885.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.32 121890[107:Res:53.1,121887.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.32 121892[108:Spt:121890.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 121894[108:Res:121892.0,61.1] always3(s39) || -> . % 76.16/76.32 121895[108:SSi:121894.0,78241.0,78244.0,108789.0,121674.0,121885.0] || -> . % 76.16/76.32 121896[108:Spt:121895.0,121890.0,121892.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.32 121897[108:Spt:121895.0,121890.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 121901[108:Res:121897.0,61.1] always3(s40) || -> . % 76.16/76.32 121902[108:SSi:121901.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.32 121903[106:Spt:121902.0,121673.0,121674.0] || until2p7(s39)*+ -> . % 76.16/76.32 121904[106:Spt:121902.0,121673.1] || -> node4(s38)*. % 76.16/76.32 121906[106:MRR:804.0,121904.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.32 121909[106:Res:53.1,121906.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.32 121914[107:Spt:121909.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 121916[107:Res:121914.0,61.1] always3(s38) || -> . % 76.16/76.32 121917[107:SSi:121916.0,78236.0,78240.0,108788.0,121672.0,121904.0] || -> . % 76.16/76.32 121918[107:Spt:121917.0,121909.0,121914.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.32 121919[107:Spt:121917.0,121909.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 121923[107:Res:121919.0,61.1] always3(s39) || -> . % 76.16/76.32 121924[107:SSi:121923.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.32 121925[105:Spt:121924.0,121671.0,121672.0] || until2p7(s38)*+ -> . % 76.16/76.32 121926[105:Spt:121924.0,121671.1] || -> node4(s37)*. % 76.16/76.32 121928[105:MRR:807.0,121926.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.32 121931[105:Res:53.1,121928.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.32 121933[106:Spt:121931.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 121935[106:Res:121933.0,61.1] always3(s37) || -> . % 76.16/76.32 121936[106:SSi:121935.0,78232.0,78235.0,108787.0,121670.0,121926.0] || -> . % 76.16/76.32 121937[106:Spt:121936.0,121931.0,121933.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.32 121938[106:Spt:121936.0,121931.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 121942[106:Res:121938.0,61.1] always3(s38) || -> . % 76.16/76.32 121943[106:SSi:121942.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.32 121944[104:Spt:121943.0,121669.0,121670.0] || until2p7(s37)*+ -> . % 76.16/76.32 121945[104:Spt:121943.0,121669.1] || -> node4(s36)*. % 76.16/76.32 121947[104:MRR:810.0,121945.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.32 121950[104:Res:53.1,121947.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.32 121952[105:Spt:121950.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 121954[105:Res:121952.0,61.1] always3(s36) || -> . % 76.16/76.32 121955[105:SSi:121954.0,78227.0,78231.0,108786.0,121668.0,121945.0] || -> . % 76.16/76.32 121956[105:Spt:121955.0,121950.0,121952.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.32 121957[105:Spt:121955.0,121950.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 121961[105:Res:121957.0,61.1] always3(s37) || -> . % 76.16/76.32 121962[105:SSi:121961.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.32 121963[103:Spt:121962.0,121667.0,121668.0] || until2p7(s36)*+ -> . % 76.16/76.32 121964[103:Spt:121962.0,121667.1] || -> node4(s35)*. % 76.16/76.32 121966[103:MRR:813.0,121964.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.32 121969[103:Res:53.1,121966.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.32 121971[104:Spt:121969.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 121973[104:Res:121971.0,61.1] always3(s35) || -> . % 76.16/76.32 121974[104:SSi:121973.0,78223.0,78226.0,108785.0,121666.0,121964.0] || -> . % 76.16/76.32 121975[104:Spt:121974.0,121969.0,121971.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.32 121976[104:Spt:121974.0,121969.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 121980[104:Res:121976.0,61.1] always3(s36) || -> . % 76.16/76.32 121981[104:SSi:121980.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.32 121982[102:Spt:121981.0,121665.0,121666.0] || until2p7(s35)*+ -> . % 76.16/76.32 121983[102:Spt:121981.0,121665.1] || -> node4(s34)*. % 76.16/76.32 121985[102:MRR:816.0,121983.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.32 121988[102:Res:53.1,121985.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.32 121993[103:Spt:121988.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 121995[103:Res:121993.0,61.1] always3(s34) || -> . % 76.16/76.32 121996[103:SSi:121995.0,78218.0,78222.0,108784.0,121664.0,121983.0] || -> . % 76.16/76.32 121997[103:Spt:121996.0,121988.0,121993.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.32 121998[103:Spt:121996.0,121988.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 122002[103:Res:121998.0,61.1] always3(s35) || -> . % 76.16/76.32 122003[103:SSi:122002.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.32 122004[101:Spt:122003.0,121663.0,121664.0] || until2p7(s34)*+ -> . % 76.16/76.32 122005[101:Spt:122003.0,121663.1] || -> node4(s33)*. % 76.16/76.32 122007[101:MRR:819.0,122005.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.32 122010[101:Res:53.1,122007.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.32 122012[102:Spt:122010.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 122014[102:Res:122012.0,61.1] always3(s33) || -> . % 76.16/76.32 122015[102:SSi:122014.0,78214.0,78217.0,108783.0,121662.0,122005.0] || -> . % 76.16/76.32 122016[102:Spt:122015.0,122010.0,122012.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.32 122017[102:Spt:122015.0,122010.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 122021[102:Res:122017.0,61.1] always3(s34) || -> . % 76.16/76.32 122022[102:SSi:122021.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.32 122023[100:Spt:122022.0,121661.0,121662.0] || until2p7(s33)*+ -> . % 76.16/76.32 122024[100:Spt:122022.0,121661.1] || -> node4(s32)*. % 76.16/76.32 122026[100:MRR:822.0,122024.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.32 122029[100:Res:53.1,122026.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.32 122031[101:Spt:122029.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 122033[101:Res:122031.0,61.1] always3(s32) || -> . % 76.16/76.32 122034[101:SSi:122033.0,78209.0,78213.0,108782.0,121660.0,122024.0] || -> . % 76.16/76.32 122035[101:Spt:122034.0,122029.0,122031.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.32 122036[101:Spt:122034.0,122029.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 122040[101:Res:122036.0,61.1] always3(s33) || -> . % 76.16/76.32 122041[101:SSi:122040.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.32 122042[99:Spt:122041.0,121659.0,121660.0] || until2p7(s32)*+ -> . % 76.16/76.32 122043[99:Spt:122041.0,121659.1] || -> node4(s31)*. % 76.16/76.32 122045[99:MRR:825.0,122043.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.32 122048[99:Res:53.1,122045.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.32 122050[100:Spt:122048.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 122052[100:Res:122050.0,61.1] always3(s31) || -> . % 76.16/76.32 122053[100:SSi:122052.0,78205.0,78208.0,108781.0,121658.0,122043.0] || -> . % 76.16/76.32 122054[100:Spt:122053.0,122048.0,122050.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.32 122055[100:Spt:122053.0,122048.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 122059[100:Res:122055.0,61.1] always3(s32) || -> . % 76.16/76.32 122060[100:SSi:122059.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.32 122061[98:Spt:122060.0,121657.0,121658.0] || until2p7(s31)*+ -> . % 76.16/76.32 122062[98:Spt:122060.0,121657.1] || -> node4(s30)*. % 76.16/76.32 122064[98:MRR:828.0,122062.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.32 122067[98:Res:53.1,122064.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.32 122072[99:Spt:122067.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 122074[99:Res:122072.0,61.1] always3(s30) || -> . % 76.16/76.32 122075[99:SSi:122074.0,78200.0,78204.0,108780.0,121656.0,122062.0] || -> . % 76.16/76.32 122076[99:Spt:122075.0,122067.0,122072.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.32 122077[99:Spt:122075.0,122067.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 122081[99:Res:122077.0,61.1] always3(s31) || -> . % 76.16/76.32 122082[99:SSi:122081.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.32 122083[97:Spt:122082.0,121655.0,121656.0] || until2p7(s30)*+ -> . % 76.16/76.32 122084[97:Spt:122082.0,121655.1] || -> node4(s29)*. % 76.16/76.32 122086[97:MRR:831.0,122084.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.32 122089[97:Res:53.1,122086.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.32 122091[98:Spt:122089.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 122093[98:Res:122091.0,61.1] always3(s29) || -> . % 76.16/76.32 122094[98:SSi:122093.0,78196.0,78199.0,108779.0,121654.0,122084.0] || -> . % 76.16/76.32 122095[98:Spt:122094.0,122089.0,122091.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.32 122096[98:Spt:122094.0,122089.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 122100[98:Res:122096.0,61.1] always3(s30) || -> . % 76.16/76.32 122101[98:SSi:122100.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.32 122102[96:Spt:122101.0,121653.0,121654.0] || until2p7(s29)*+ -> . % 76.16/76.32 122103[96:Spt:122101.0,121653.1] || -> node4(s28)*. % 76.16/76.32 122105[96:MRR:834.0,122103.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.32 122108[96:Res:53.1,122105.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.32 122110[97:Spt:122108.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 122112[97:Res:122110.0,61.1] always3(s28) || -> . % 76.16/76.32 122113[97:SSi:122112.0,78191.0,78195.0,108778.0,121652.0,122103.0] || -> . % 76.16/76.32 122114[97:Spt:122113.0,122108.0,122110.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.32 122115[97:Spt:122113.0,122108.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 122119[97:Res:122115.0,61.1] always3(s29) || -> . % 76.16/76.32 122120[97:SSi:122119.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.32 122121[95:Spt:122120.0,121651.0,121652.0] || until2p7(s28)*+ -> . % 76.16/76.32 122122[95:Spt:122120.0,121651.1] || -> node4(s27)*. % 76.16/76.32 122124[95:MRR:837.0,122122.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.32 122127[95:Res:53.1,122124.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.32 122129[96:Spt:122127.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 122131[96:Res:122129.0,61.1] always3(s27) || -> . % 76.16/76.32 122132[96:SSi:122131.0,78187.0,78190.0,108777.0,121650.0,122122.0] || -> . % 76.16/76.32 122133[96:Spt:122132.0,122127.0,122129.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.32 122134[96:Spt:122132.0,122127.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 122138[96:Res:122134.0,61.1] always3(s28) || -> . % 76.16/76.32 122139[96:SSi:122138.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.32 122140[94:Spt:122139.0,121649.0,121650.0] || until2p7(s27)*+ -> . % 76.16/76.32 122141[94:Spt:122139.0,121649.1] || -> node4(s26)*. % 76.16/76.32 122143[94:MRR:840.0,122141.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.32 122146[94:Res:53.1,122143.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.32 122151[95:Spt:122146.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 122153[95:Res:122151.0,61.1] always3(s26) || -> . % 76.16/76.32 122154[95:SSi:122153.0,78182.0,78186.0,108776.0,121648.0,122141.0] || -> . % 76.16/76.32 122155[95:Spt:122154.0,122146.0,122151.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.32 122156[95:Spt:122154.0,122146.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 122160[95:Res:122156.0,61.1] always3(s27) || -> . % 76.16/76.32 122161[95:SSi:122160.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.32 122162[93:Spt:122161.0,121647.0,121648.0] || until2p7(s26)*+ -> . % 76.16/76.32 122163[93:Spt:122161.0,121647.1] || -> node4(s25)*. % 76.16/76.32 122165[93:MRR:843.0,122163.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.32 122168[93:Res:53.1,122165.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.32 122170[94:Spt:122168.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 122172[94:Res:122170.0,61.1] always3(s25) || -> . % 76.16/76.32 122173[94:SSi:122172.0,78178.0,78181.0,108775.0,121646.0,122163.0] || -> . % 76.16/76.32 122174[94:Spt:122173.0,122168.0,122170.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.32 122175[94:Spt:122173.0,122168.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 122179[94:Res:122175.0,61.1] always3(s26) || -> . % 76.16/76.32 122180[94:SSi:122179.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.32 122181[92:Spt:122180.0,121645.0,121646.0] || until2p7(s25)*+ -> . % 76.16/76.32 122182[92:Spt:122180.0,121645.1] || -> node4(s24)*. % 76.16/76.32 122184[92:MRR:846.0,122182.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.32 122187[92:Res:53.1,122184.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.32 122189[93:Spt:122187.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 122191[93:Res:122189.0,61.1] always3(s24) || -> . % 76.16/76.32 122192[93:SSi:122191.0,78173.0,78177.0,108774.0,121644.0,122182.0] || -> . % 76.16/76.32 122193[93:Spt:122192.0,122187.0,122189.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.32 122194[93:Spt:122192.0,122187.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 122198[93:Res:122194.0,61.1] always3(s25) || -> . % 76.16/76.32 122199[93:SSi:122198.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.32 122200[91:Spt:122199.0,121643.0,121644.0] || until2p7(s24)*+ -> . % 76.16/76.32 122201[91:Spt:122199.0,121643.1] || -> node4(s23)*. % 76.16/76.32 122203[91:MRR:849.0,122201.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.32 122206[91:Res:53.1,122203.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.32 122208[92:Spt:122206.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 122210[92:Res:122208.0,61.1] always3(s23) || -> . % 76.16/76.32 122211[92:SSi:122210.0,78169.0,78172.0,108773.0,121642.0,122201.0] || -> . % 76.16/76.32 122212[92:Spt:122211.0,122206.0,122208.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.32 122213[92:Spt:122211.0,122206.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 122217[92:Res:122213.0,61.1] always3(s24) || -> . % 76.16/76.32 122218[92:SSi:122217.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.32 122219[90:Spt:122218.0,121641.0,121642.0] || until2p7(s23)*+ -> . % 76.16/76.32 122220[90:Spt:122218.0,121641.1] || -> node4(s22)*. % 76.16/76.32 122222[90:MRR:852.0,122220.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.32 122225[90:Res:53.1,122222.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.32 122230[91:Spt:122225.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 122232[91:Res:122230.0,61.1] always3(s22) || -> . % 76.16/76.32 122233[91:SSi:122232.0,78164.0,78168.0,108772.0,121640.0,122220.0] || -> . % 76.16/76.32 122234[91:Spt:122233.0,122225.0,122230.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.32 122235[91:Spt:122233.0,122225.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 122239[91:Res:122235.0,61.1] always3(s23) || -> . % 76.16/76.32 122240[91:SSi:122239.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.32 122241[89:Spt:122240.0,121639.0,121640.0] || until2p7(s22)*+ -> . % 76.16/76.32 122242[89:Spt:122240.0,121639.1] || -> node4(s21)*. % 76.16/76.32 122244[89:MRR:855.0,122242.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.32 122247[89:Res:53.1,122244.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.32 122249[90:Spt:122247.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 122251[90:Res:122249.0,61.1] always3(s21) || -> . % 76.16/76.32 122252[90:SSi:122251.0,78160.0,78163.0,108771.0,121638.0,122242.0] || -> . % 76.16/76.32 122253[90:Spt:122252.0,122247.0,122249.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.32 122254[90:Spt:122252.0,122247.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 122258[90:Res:122254.0,61.1] always3(s22) || -> . % 76.16/76.32 122259[90:SSi:122258.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.32 122260[88:Spt:122259.0,121637.0,121638.0] || until2p7(s21)*+ -> . % 76.16/76.32 122261[88:Spt:122259.0,121637.1] || -> node4(s20)*. % 76.16/76.32 122263[88:MRR:858.0,122261.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.32 122266[88:Res:53.1,122263.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.32 122268[89:Spt:122266.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 122270[89:Res:122268.0,61.1] always3(s20) || -> . % 76.16/76.32 122271[89:SSi:122270.0,78155.0,78159.0,108770.0,121636.0,122261.0] || -> . % 76.16/76.32 122272[89:Spt:122271.0,122266.0,122268.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.32 122273[89:Spt:122271.0,122266.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 122277[89:Res:122273.0,61.1] always3(s21) || -> . % 76.16/76.32 122278[89:SSi:122277.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.32 122279[87:Spt:122278.0,121635.0,121636.0] || until2p7(s20)*+ -> . % 76.16/76.32 122280[87:Spt:122278.0,121635.1] || -> node4(s19)*. % 76.16/76.32 122282[87:MRR:861.0,122280.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.32 122285[87:Res:53.1,122282.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.32 122287[88:Spt:122285.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 122289[88:Res:122287.0,61.1] always3(s19) || -> . % 76.16/76.32 122290[88:SSi:122289.0,78151.0,78154.0,108769.0,121634.0,122280.0] || -> . % 76.16/76.32 122291[88:Spt:122290.0,122285.0,122287.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.32 122292[88:Spt:122290.0,122285.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 122296[88:Res:122292.0,61.1] always3(s20) || -> . % 76.16/76.32 122297[88:SSi:122296.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.32 122298[86:Spt:122297.0,121633.0,121634.0] || until2p7(s19)*+ -> . % 76.16/76.32 122299[86:Spt:122297.0,121633.1] || -> node4(s18)*. % 76.16/76.32 122301[86:MRR:864.0,122299.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.32 122304[86:Res:53.1,122301.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.32 122306[86:MRR:122304.0,121623.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 122311[86:Res:122306.0,61.1] always3(s19) || -> . % 76.16/76.32 122312[86:SSi:122311.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.32 122313[84:Spt:122312.0,121504.0,121507.0] || trans(s49,s18)*+ -> . % 76.16/76.32 122314[84:Spt:122312.0,121504.1,121504.2,121504.3,121504.4,121504.5,121504.6,121504.7,121504.8,121504.9,121504.10,121504.11,121504.12,121504.13,121504.14,121504.15] || -> trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.32 122316[84:MRR:121506.1,122313.0] xuntil6(s49) || -> trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.32 122317[85:Spt:122314.0] || -> trans(s49,s17)*. % 76.16/76.32 122318[85:Res:122317.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s17)*. % 76.16/76.32 122320[85:Res:122317.0,60.0] || -> node2(s49,s17)*. % 76.16/76.32 122321[85:SSi:122318.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s17)*. % 76.16/76.32 122322[85:Res:122320.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 122429[85:SoR:122322.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 122431[85:SoR:122429.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)* xuntil6(s49). % 76.16/76.32 122432[85:SSi:122431.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s17,c_busy)* xuntil6(s49). % 76.16/76.32 122433[86:Spt:122432.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 122435[86:Res:122433.0,61.1] always3(s17) || -> . % 76.16/76.32 122436[86:SSi:122435.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.32 122437[86:Spt:122436.0,122432.1,122433.0] || m_main_v_state(s17,c_busy)*+ -> . % 76.16/76.32 122438[86:Spt:122436.0,122432.0,122432.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.32 122442[86:MRR:122429.2,122437.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.32 122443[86:Res:53.1,122438.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.32 122445[86:MRR:122443.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.32 122446[86:MRR:122321.0,122445.0] || -> until2p7(s17)*. % 76.16/76.32 122447[86:MRR:213.0,122446.0] || -> until2p7(s18)* node4(s17). % 76.16/76.32 122448[87:Spt:122447.0] || -> until2p7(s18)*. % 76.16/76.32 122449[87:MRR:214.0,122448.0] || -> until2p7(s19)* node4(s18). % 76.16/76.32 122450[88:Spt:122449.0] || -> until2p7(s19)*. % 76.16/76.32 122451[88:MRR:215.0,122450.0] || -> until2p7(s20)* node4(s19). % 76.16/76.32 122452[89:Spt:122451.0] || -> until2p7(s20)*. % 76.16/76.32 122453[89:MRR:216.0,122452.0] || -> until2p7(s21)* node4(s20). % 76.16/76.32 122454[90:Spt:122453.0] || -> until2p7(s21)*. % 76.16/76.32 122455[90:MRR:217.0,122454.0] || -> until2p7(s22)* node4(s21). % 76.16/76.32 122456[91:Spt:122455.0] || -> until2p7(s22)*. % 76.16/76.32 122457[91:MRR:218.0,122456.0] || -> until2p7(s23)* node4(s22). % 76.16/76.32 122458[92:Spt:122457.0] || -> until2p7(s23)*. % 76.16/76.32 122459[92:MRR:219.0,122458.0] || -> until2p7(s24)* node4(s23). % 76.16/76.32 122460[93:Spt:122459.0] || -> until2p7(s24)*. % 76.16/76.32 122461[93:MRR:220.0,122460.0] || -> until2p7(s25)* node4(s24). % 76.16/76.32 122462[94:Spt:122461.0] || -> until2p7(s25)*. % 76.16/76.32 122463[94:MRR:221.0,122462.0] || -> until2p7(s26)* node4(s25). % 76.16/76.32 122464[95:Spt:122463.0] || -> until2p7(s26)*. % 76.16/76.32 122465[95:MRR:222.0,122464.0] || -> until2p7(s27)* node4(s26). % 76.16/76.32 122466[96:Spt:122465.0] || -> until2p7(s27)*. % 76.16/76.32 122467[96:MRR:223.0,122466.0] || -> until2p7(s28)* node4(s27). % 76.16/76.32 122468[97:Spt:122467.0] || -> until2p7(s28)*. % 76.16/76.32 122469[97:MRR:224.0,122468.0] || -> until2p7(s29)* node4(s28). % 76.16/76.32 122470[98:Spt:122469.0] || -> until2p7(s29)*. % 76.16/76.32 122471[98:MRR:225.0,122470.0] || -> until2p7(s30)* node4(s29). % 76.16/76.32 122472[99:Spt:122471.0] || -> until2p7(s30)*. % 76.16/76.32 122473[99:MRR:226.0,122472.0] || -> until2p7(s31)* node4(s30). % 76.16/76.32 122474[100:Spt:122473.0] || -> until2p7(s31)*. % 76.16/76.32 122475[100:MRR:227.0,122474.0] || -> until2p7(s32)* node4(s31). % 76.16/76.32 122476[101:Spt:122475.0] || -> until2p7(s32)*. % 76.16/76.32 122477[101:MRR:228.0,122476.0] || -> until2p7(s33)* node4(s32). % 76.16/76.32 122478[102:Spt:122477.0] || -> until2p7(s33)*. % 76.16/76.32 122479[102:MRR:229.0,122478.0] || -> until2p7(s34)* node4(s33). % 76.16/76.32 122480[103:Spt:122479.0] || -> until2p7(s34)*. % 76.16/76.32 122481[103:MRR:230.0,122480.0] || -> until2p7(s35)* node4(s34). % 76.16/76.32 122482[104:Spt:122481.0] || -> until2p7(s35)*. % 76.16/76.32 122483[104:MRR:231.0,122482.0] || -> until2p7(s36)* node4(s35). % 76.16/76.32 122484[105:Spt:122483.0] || -> until2p7(s36)*. % 76.16/76.32 122485[105:MRR:232.0,122484.0] || -> until2p7(s37)* node4(s36). % 76.16/76.32 122486[106:Spt:122485.0] || -> until2p7(s37)*. % 76.16/76.32 122487[106:MRR:235.0,122486.0] || -> until2p7(s38)* node4(s37). % 76.16/76.32 122488[107:Spt:122487.0] || -> until2p7(s38)*. % 76.16/76.32 122489[107:MRR:236.0,122488.0] || -> until2p7(s39)* node4(s38). % 76.16/76.32 122490[108:Spt:122489.0] || -> until2p7(s39)*. % 76.16/76.32 122491[108:MRR:237.0,122490.0] || -> until2p7(s40)* node4(s39). % 76.16/76.32 122492[109:Spt:122491.0] || -> until2p7(s40)*. % 76.16/76.32 122493[109:MRR:238.0,122492.0] || -> until2p7(s41)* node4(s40). % 76.16/76.32 122494[110:Spt:122493.0] || -> until2p7(s41)*. % 76.16/76.32 122495[110:MRR:239.0,122494.0] || -> until2p7(s42)* node4(s41). % 76.16/76.32 122496[111:Spt:122495.0] || -> until2p7(s42)*. % 76.16/76.32 122497[111:MRR:240.0,122496.0] || -> until2p7(s43)* node4(s42). % 76.16/76.32 122498[112:Spt:122497.0] || -> until2p7(s43)*. % 76.16/76.32 122499[112:MRR:241.0,122498.0] || -> until2p7(s44)* node4(s43). % 76.16/76.32 122500[113:Spt:122499.0] || -> until2p7(s44)*. % 76.16/76.32 122501[113:MRR:539.0,122500.0] || -> until2p7(s45)* node4(s44). % 76.16/76.32 122502[114:Spt:122501.0] || -> until2p7(s45)*. % 76.16/76.32 122503[114:MRR:544.0,122502.0] || -> until2p7(s46)* node4(s45). % 76.16/76.32 122504[115:Spt:122503.0] || -> until2p7(s46)*. % 76.16/76.32 122505[115:MRR:549.0,122504.0] || -> until2p7(s47)* node4(s46). % 76.16/76.32 122506[116:Spt:122505.0] || -> until2p7(s47)*. % 76.16/76.32 122507[116:MRR:554.0,122506.0] || -> until2p7(s48)* node4(s47). % 76.16/76.32 122508[117:Spt:122507.0] || -> until2p7(s48)*. % 76.16/76.32 122509[117:MRR:559.0,122508.0] || -> until2p7(s49)* node4(s48). % 76.16/76.32 122510[118:Spt:122509.0] || -> until2p7(s49)*. % 76.16/76.32 122511[118:MRR:194.0,122510.0] || -> node4(s49)*. % 76.16/76.32 122512[118:MRR:122442.0,122511.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.32 122513[118:Res:53.1,122512.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.32 122515[118:MRR:122513.0,78381.0] || -> . % 76.16/76.32 122516[118:Spt:122515.0,122509.0,122510.0] || until2p7(s49)*+ -> . % 76.16/76.32 122517[118:Spt:122515.0,122509.1] || -> node4(s48)*. % 76.16/76.32 122518[118:MRR:78384.0,122517.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.32 122521[118:Res:53.1,122518.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 122524[118:Res:122521.0,61.1] always3(s48) || -> . % 76.16/76.32 122525[118:SSi:122524.0,78281.0,78387.0,108798.0,122508.0,122517.0] || -> . % 76.16/76.32 122526[117:Spt:122525.0,122507.0,122508.0] || until2p7(s48)*+ -> . % 76.16/76.32 122527[117:Spt:122525.0,122507.1] || -> node4(s47)*. % 76.16/76.32 122529[117:MRR:777.0,122527.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.32 122544[117:Res:53.1,122529.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.32 122549[118:Spt:122544.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 122551[118:Res:122549.0,61.1] always3(s47) || -> . % 76.16/76.32 122552[118:SSi:122551.0,78277.0,78280.0,108797.0,122506.0,122527.0] || -> . % 76.16/76.32 122553[118:Spt:122552.0,122544.0,122549.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.32 122554[118:Spt:122552.0,122544.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 122558[118:Res:122554.0,61.1] always3(s48) || -> . % 76.16/76.32 122559[118:SSi:122558.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.32 122560[116:Spt:122559.0,122505.0,122506.0] || until2p7(s47)*+ -> . % 76.16/76.32 122561[116:Spt:122559.0,122505.1] || -> node4(s46)*. % 76.16/76.32 122563[116:MRR:780.0,122561.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.32 122570[116:Res:53.1,122563.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.32 122572[117:Spt:122570.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 122574[117:Res:122572.0,61.1] always3(s46) || -> . % 76.16/76.32 122575[117:SSi:122574.0,78272.0,78276.0,108796.0,122504.0,122561.0] || -> . % 76.16/76.32 122576[117:Spt:122575.0,122570.0,122572.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.32 122577[117:Spt:122575.0,122570.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 122581[117:Res:122577.0,61.1] always3(s47) || -> . % 76.16/76.32 122582[117:SSi:122581.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.32 122583[115:Spt:122582.0,122503.0,122504.0] || until2p7(s46)*+ -> . % 76.16/76.32 122584[115:Spt:122582.0,122503.1] || -> node4(s45)*. % 76.16/76.32 122586[115:MRR:783.0,122584.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.32 122589[115:Res:53.1,122586.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.32 122594[116:Spt:122589.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 122596[116:Res:122594.0,61.1] always3(s45) || -> . % 76.16/76.32 122597[116:SSi:122596.0,78268.0,78271.0,108795.0,122502.0,122584.0] || -> . % 76.16/76.32 122598[116:Spt:122597.0,122589.0,122594.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.32 122599[116:Spt:122597.0,122589.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 122603[116:Res:122599.0,61.1] always3(s46) || -> . % 76.16/76.32 122604[116:SSi:122603.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.32 122605[114:Spt:122604.0,122501.0,122502.0] || until2p7(s45)*+ -> . % 76.16/76.32 122606[114:Spt:122604.0,122501.1] || -> node4(s44)*. % 76.16/76.32 122608[114:MRR:786.0,122606.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.32 122611[114:Res:53.1,122608.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.32 122613[115:Spt:122611.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 122615[115:Res:122613.0,61.1] always3(s44) || -> . % 76.16/76.32 122616[115:SSi:122615.0,78263.0,78267.0,108794.0,122500.0,122606.0] || -> . % 76.16/76.32 122617[115:Spt:122616.0,122611.0,122613.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.32 122618[115:Spt:122616.0,122611.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 122622[115:Res:122618.0,61.1] always3(s45) || -> . % 76.16/76.32 122623[115:SSi:122622.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.32 122624[113:Spt:122623.0,122499.0,122500.0] || until2p7(s44)*+ -> . % 76.16/76.32 122625[113:Spt:122623.0,122499.1] || -> node4(s43)*. % 76.16/76.32 122627[113:MRR:789.0,122625.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.32 122630[113:Res:53.1,122627.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.32 122632[114:Spt:122630.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 122634[114:Res:122632.0,61.1] always3(s43) || -> . % 76.16/76.32 122635[114:SSi:122634.0,78259.0,78262.0,108793.0,122498.0,122625.0] || -> . % 76.16/76.32 122636[114:Spt:122635.0,122630.0,122632.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.32 122637[114:Spt:122635.0,122630.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 122641[114:Res:122637.0,61.1] always3(s44) || -> . % 76.16/76.32 122642[114:SSi:122641.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.32 122643[112:Spt:122642.0,122497.0,122498.0] || until2p7(s43)*+ -> . % 76.16/76.32 122644[112:Spt:122642.0,122497.1] || -> node4(s42)*. % 76.16/76.32 122646[112:MRR:792.0,122644.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.32 122649[112:Res:53.1,122646.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.32 122651[113:Spt:122649.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 122653[113:Res:122651.0,61.1] always3(s42) || -> . % 76.16/76.32 122654[113:SSi:122653.0,78254.0,78258.0,108792.0,122496.0,122644.0] || -> . % 76.16/76.32 122655[113:Spt:122654.0,122649.0,122651.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.32 122656[113:Spt:122654.0,122649.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 122660[113:Res:122656.0,61.1] always3(s43) || -> . % 76.16/76.32 122661[113:SSi:122660.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.32 122662[111:Spt:122661.0,122495.0,122496.0] || until2p7(s42)*+ -> . % 76.16/76.32 122663[111:Spt:122661.0,122495.1] || -> node4(s41)*. % 76.16/76.32 122665[111:MRR:795.0,122663.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.32 122668[111:Res:53.1,122665.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.32 122673[112:Spt:122668.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 122675[112:Res:122673.0,61.1] always3(s41) || -> . % 76.16/76.32 122676[112:SSi:122675.0,78250.0,78253.0,108791.0,122494.0,122663.0] || -> . % 76.16/76.32 122677[112:Spt:122676.0,122668.0,122673.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.32 122678[112:Spt:122676.0,122668.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 122682[112:Res:122678.0,61.1] always3(s42) || -> . % 76.16/76.32 122683[112:SSi:122682.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.32 122684[110:Spt:122683.0,122493.0,122494.0] || until2p7(s41)*+ -> . % 76.16/76.32 122685[110:Spt:122683.0,122493.1] || -> node4(s40)*. % 76.16/76.32 122687[110:MRR:798.0,122685.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.32 122690[110:Res:53.1,122687.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.32 122692[111:Spt:122690.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 122694[111:Res:122692.0,61.1] always3(s40) || -> . % 76.16/76.32 122695[111:SSi:122694.0,78245.0,78249.0,108790.0,122492.0,122685.0] || -> . % 76.16/76.32 122696[111:Spt:122695.0,122690.0,122692.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.32 122697[111:Spt:122695.0,122690.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 122701[111:Res:122697.0,61.1] always3(s41) || -> . % 76.16/76.32 122702[111:SSi:122701.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.32 122703[109:Spt:122702.0,122491.0,122492.0] || until2p7(s40)*+ -> . % 76.16/76.32 122704[109:Spt:122702.0,122491.1] || -> node4(s39)*. % 76.16/76.32 122706[109:MRR:801.0,122704.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.32 122709[109:Res:53.1,122706.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.32 122711[110:Spt:122709.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 122713[110:Res:122711.0,61.1] always3(s39) || -> . % 76.16/76.32 122714[110:SSi:122713.0,78241.0,78244.0,108789.0,122490.0,122704.0] || -> . % 76.16/76.32 122715[110:Spt:122714.0,122709.0,122711.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.32 122716[110:Spt:122714.0,122709.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 122720[110:Res:122716.0,61.1] always3(s40) || -> . % 76.16/76.32 122721[110:SSi:122720.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.32 122722[108:Spt:122721.0,122489.0,122490.0] || until2p7(s39)*+ -> . % 76.16/76.32 122723[108:Spt:122721.0,122489.1] || -> node4(s38)*. % 76.16/76.32 122725[108:MRR:804.0,122723.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.32 122728[108:Res:53.1,122725.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.32 122730[109:Spt:122728.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 122732[109:Res:122730.0,61.1] always3(s38) || -> . % 76.16/76.32 122733[109:SSi:122732.0,78236.0,78240.0,108788.0,122488.0,122723.0] || -> . % 76.16/76.32 122734[109:Spt:122733.0,122728.0,122730.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.32 122735[109:Spt:122733.0,122728.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 122739[109:Res:122735.0,61.1] always3(s39) || -> . % 76.16/76.32 122740[109:SSi:122739.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.32 122741[107:Spt:122740.0,122487.0,122488.0] || until2p7(s38)*+ -> . % 76.16/76.32 122742[107:Spt:122740.0,122487.1] || -> node4(s37)*. % 76.16/76.32 122744[107:MRR:807.0,122742.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.32 122747[107:Res:53.1,122744.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.32 122752[108:Spt:122747.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 122754[108:Res:122752.0,61.1] always3(s37) || -> . % 76.16/76.32 122755[108:SSi:122754.0,78232.0,78235.0,108787.0,122486.0,122742.0] || -> . % 76.16/76.32 122756[108:Spt:122755.0,122747.0,122752.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.32 122757[108:Spt:122755.0,122747.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 122761[108:Res:122757.0,61.1] always3(s38) || -> . % 76.16/76.32 122762[108:SSi:122761.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.32 122763[106:Spt:122762.0,122485.0,122486.0] || until2p7(s37)*+ -> . % 76.16/76.32 122764[106:Spt:122762.0,122485.1] || -> node4(s36)*. % 76.16/76.32 122766[106:MRR:810.0,122764.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.32 122769[106:Res:53.1,122766.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.32 122771[107:Spt:122769.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 122773[107:Res:122771.0,61.1] always3(s36) || -> . % 76.16/76.32 122774[107:SSi:122773.0,78227.0,78231.0,108786.0,122484.0,122764.0] || -> . % 76.16/76.32 122775[107:Spt:122774.0,122769.0,122771.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.32 122776[107:Spt:122774.0,122769.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 122780[107:Res:122776.0,61.1] always3(s37) || -> . % 76.16/76.32 122781[107:SSi:122780.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.32 122782[105:Spt:122781.0,122483.0,122484.0] || until2p7(s36)*+ -> . % 76.16/76.32 122783[105:Spt:122781.0,122483.1] || -> node4(s35)*. % 76.16/76.32 122785[105:MRR:813.0,122783.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.32 122788[105:Res:53.1,122785.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.32 122790[106:Spt:122788.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 122792[106:Res:122790.0,61.1] always3(s35) || -> . % 76.16/76.32 122793[106:SSi:122792.0,78223.0,78226.0,108785.0,122482.0,122783.0] || -> . % 76.16/76.32 122794[106:Spt:122793.0,122788.0,122790.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.32 122795[106:Spt:122793.0,122788.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 122799[106:Res:122795.0,61.1] always3(s36) || -> . % 76.16/76.32 122800[106:SSi:122799.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.32 122801[104:Spt:122800.0,122481.0,122482.0] || until2p7(s35)*+ -> . % 76.16/76.32 122802[104:Spt:122800.0,122481.1] || -> node4(s34)*. % 76.16/76.32 122804[104:MRR:816.0,122802.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.32 122807[104:Res:53.1,122804.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.32 122809[105:Spt:122807.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 122811[105:Res:122809.0,61.1] always3(s34) || -> . % 76.16/76.32 122812[105:SSi:122811.0,78218.0,78222.0,108784.0,122480.0,122802.0] || -> . % 76.16/76.32 122813[105:Spt:122812.0,122807.0,122809.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.32 122814[105:Spt:122812.0,122807.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 122818[105:Res:122814.0,61.1] always3(s35) || -> . % 76.16/76.32 122819[105:SSi:122818.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.32 122820[103:Spt:122819.0,122479.0,122480.0] || until2p7(s34)*+ -> . % 76.16/76.32 122821[103:Spt:122819.0,122479.1] || -> node4(s33)*. % 76.16/76.32 122823[103:MRR:819.0,122821.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.32 122826[103:Res:53.1,122823.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.32 122831[104:Spt:122826.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 122833[104:Res:122831.0,61.1] always3(s33) || -> . % 76.16/76.32 122834[104:SSi:122833.0,78214.0,78217.0,108783.0,122478.0,122821.0] || -> . % 76.16/76.32 122835[104:Spt:122834.0,122826.0,122831.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.32 122836[104:Spt:122834.0,122826.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 122840[104:Res:122836.0,61.1] always3(s34) || -> . % 76.16/76.32 122841[104:SSi:122840.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.32 122842[102:Spt:122841.0,122477.0,122478.0] || until2p7(s33)*+ -> . % 76.16/76.32 122843[102:Spt:122841.0,122477.1] || -> node4(s32)*. % 76.16/76.32 122845[102:MRR:822.0,122843.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.32 122848[102:Res:53.1,122845.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.32 122850[103:Spt:122848.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 122852[103:Res:122850.0,61.1] always3(s32) || -> . % 76.16/76.32 122853[103:SSi:122852.0,78209.0,78213.0,108782.0,122476.0,122843.0] || -> . % 76.16/76.32 122854[103:Spt:122853.0,122848.0,122850.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.32 122855[103:Spt:122853.0,122848.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 122859[103:Res:122855.0,61.1] always3(s33) || -> . % 76.16/76.32 122860[103:SSi:122859.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.32 122861[101:Spt:122860.0,122475.0,122476.0] || until2p7(s32)*+ -> . % 76.16/76.32 122862[101:Spt:122860.0,122475.1] || -> node4(s31)*. % 76.16/76.32 122864[101:MRR:825.0,122862.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.32 122867[101:Res:53.1,122864.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.32 122869[102:Spt:122867.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 122871[102:Res:122869.0,61.1] always3(s31) || -> . % 76.16/76.32 122872[102:SSi:122871.0,78205.0,78208.0,108781.0,122474.0,122862.0] || -> . % 76.16/76.32 122873[102:Spt:122872.0,122867.0,122869.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.32 122874[102:Spt:122872.0,122867.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 122878[102:Res:122874.0,61.1] always3(s32) || -> . % 76.16/76.32 122879[102:SSi:122878.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.32 122880[100:Spt:122879.0,122473.0,122474.0] || until2p7(s31)*+ -> . % 76.16/76.32 122881[100:Spt:122879.0,122473.1] || -> node4(s30)*. % 76.16/76.32 122883[100:MRR:828.0,122881.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.32 122886[100:Res:53.1,122883.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.32 122888[101:Spt:122886.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 122890[101:Res:122888.0,61.1] always3(s30) || -> . % 76.16/76.32 122891[101:SSi:122890.0,78200.0,78204.0,108780.0,122472.0,122881.0] || -> . % 76.16/76.32 122892[101:Spt:122891.0,122886.0,122888.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.32 122893[101:Spt:122891.0,122886.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 122897[101:Res:122893.0,61.1] always3(s31) || -> . % 76.16/76.32 122898[101:SSi:122897.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.32 122899[99:Spt:122898.0,122471.0,122472.0] || until2p7(s30)*+ -> . % 76.16/76.32 122900[99:Spt:122898.0,122471.1] || -> node4(s29)*. % 76.16/76.32 122902[99:MRR:831.0,122900.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.32 122905[99:Res:53.1,122902.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.32 122910[100:Spt:122905.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 122912[100:Res:122910.0,61.1] always3(s29) || -> . % 76.16/76.32 122913[100:SSi:122912.0,78196.0,78199.0,108779.0,122470.0,122900.0] || -> . % 76.16/76.32 122914[100:Spt:122913.0,122905.0,122910.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.32 122915[100:Spt:122913.0,122905.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 122919[100:Res:122915.0,61.1] always3(s30) || -> . % 76.16/76.32 122920[100:SSi:122919.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.32 122921[98:Spt:122920.0,122469.0,122470.0] || until2p7(s29)*+ -> . % 76.16/76.32 122922[98:Spt:122920.0,122469.1] || -> node4(s28)*. % 76.16/76.32 122924[98:MRR:834.0,122922.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.32 122927[98:Res:53.1,122924.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.32 122929[99:Spt:122927.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 122931[99:Res:122929.0,61.1] always3(s28) || -> . % 76.16/76.32 122932[99:SSi:122931.0,78191.0,78195.0,108778.0,122468.0,122922.0] || -> . % 76.16/76.32 122933[99:Spt:122932.0,122927.0,122929.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.32 122934[99:Spt:122932.0,122927.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 122938[99:Res:122934.0,61.1] always3(s29) || -> . % 76.16/76.32 122939[99:SSi:122938.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.32 122940[97:Spt:122939.0,122467.0,122468.0] || until2p7(s28)*+ -> . % 76.16/76.32 122941[97:Spt:122939.0,122467.1] || -> node4(s27)*. % 76.16/76.32 122943[97:MRR:837.0,122941.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.32 122946[97:Res:53.1,122943.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.32 122948[98:Spt:122946.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 122950[98:Res:122948.0,61.1] always3(s27) || -> . % 76.16/76.32 122951[98:SSi:122950.0,78187.0,78190.0,108777.0,122466.0,122941.0] || -> . % 76.16/76.32 122952[98:Spt:122951.0,122946.0,122948.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.32 122953[98:Spt:122951.0,122946.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 122957[98:Res:122953.0,61.1] always3(s28) || -> . % 76.16/76.32 122958[98:SSi:122957.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.32 122959[96:Spt:122958.0,122465.0,122466.0] || until2p7(s27)*+ -> . % 76.16/76.32 122960[96:Spt:122958.0,122465.1] || -> node4(s26)*. % 76.16/76.32 122962[96:MRR:840.0,122960.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.32 122965[96:Res:53.1,122962.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.32 122967[97:Spt:122965.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 122969[97:Res:122967.0,61.1] always3(s26) || -> . % 76.16/76.32 122970[97:SSi:122969.0,78182.0,78186.0,108776.0,122464.0,122960.0] || -> . % 76.16/76.32 122971[97:Spt:122970.0,122965.0,122967.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.32 122972[97:Spt:122970.0,122965.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 122976[97:Res:122972.0,61.1] always3(s27) || -> . % 76.16/76.32 122977[97:SSi:122976.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.32 122978[95:Spt:122977.0,122463.0,122464.0] || until2p7(s26)*+ -> . % 76.16/76.32 122979[95:Spt:122977.0,122463.1] || -> node4(s25)*. % 76.16/76.32 122981[95:MRR:843.0,122979.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.32 122984[95:Res:53.1,122981.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.32 122989[96:Spt:122984.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 122991[96:Res:122989.0,61.1] always3(s25) || -> . % 76.16/76.32 122992[96:SSi:122991.0,78178.0,78181.0,108775.0,122462.0,122979.0] || -> . % 76.16/76.32 122993[96:Spt:122992.0,122984.0,122989.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.32 122994[96:Spt:122992.0,122984.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 122998[96:Res:122994.0,61.1] always3(s26) || -> . % 76.16/76.32 122999[96:SSi:122998.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.32 123000[94:Spt:122999.0,122461.0,122462.0] || until2p7(s25)*+ -> . % 76.16/76.32 123001[94:Spt:122999.0,122461.1] || -> node4(s24)*. % 76.16/76.32 123003[94:MRR:846.0,123001.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.32 123006[94:Res:53.1,123003.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.32 123008[95:Spt:123006.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 123010[95:Res:123008.0,61.1] always3(s24) || -> . % 76.16/76.32 123011[95:SSi:123010.0,78173.0,78177.0,108774.0,122460.0,123001.0] || -> . % 76.16/76.32 123012[95:Spt:123011.0,123006.0,123008.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.32 123013[95:Spt:123011.0,123006.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 123017[95:Res:123013.0,61.1] always3(s25) || -> . % 76.16/76.32 123018[95:SSi:123017.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.32 123019[93:Spt:123018.0,122459.0,122460.0] || until2p7(s24)*+ -> . % 76.16/76.32 123020[93:Spt:123018.0,122459.1] || -> node4(s23)*. % 76.16/76.32 123022[93:MRR:849.0,123020.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.32 123025[93:Res:53.1,123022.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.32 123027[94:Spt:123025.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 123029[94:Res:123027.0,61.1] always3(s23) || -> . % 76.16/76.32 123030[94:SSi:123029.0,78169.0,78172.0,108773.0,122458.0,123020.0] || -> . % 76.16/76.32 123031[94:Spt:123030.0,123025.0,123027.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.32 123032[94:Spt:123030.0,123025.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 123036[94:Res:123032.0,61.1] always3(s24) || -> . % 76.16/76.32 123037[94:SSi:123036.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.32 123038[92:Spt:123037.0,122457.0,122458.0] || until2p7(s23)*+ -> . % 76.16/76.32 123039[92:Spt:123037.0,122457.1] || -> node4(s22)*. % 76.16/76.32 123041[92:MRR:852.0,123039.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.32 123044[92:Res:53.1,123041.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.32 123046[93:Spt:123044.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 123048[93:Res:123046.0,61.1] always3(s22) || -> . % 76.16/76.32 123049[93:SSi:123048.0,78164.0,78168.0,108772.0,122456.0,123039.0] || -> . % 76.16/76.32 123050[93:Spt:123049.0,123044.0,123046.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.32 123051[93:Spt:123049.0,123044.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 123055[93:Res:123051.0,61.1] always3(s23) || -> . % 76.16/76.32 123056[93:SSi:123055.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.32 123057[91:Spt:123056.0,122455.0,122456.0] || until2p7(s22)*+ -> . % 76.16/76.32 123058[91:Spt:123056.0,122455.1] || -> node4(s21)*. % 76.16/76.32 123060[91:MRR:855.0,123058.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.32 123063[91:Res:53.1,123060.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.32 123068[92:Spt:123063.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 123070[92:Res:123068.0,61.1] always3(s21) || -> . % 76.16/76.32 123071[92:SSi:123070.0,78160.0,78163.0,108771.0,122454.0,123058.0] || -> . % 76.16/76.32 123072[92:Spt:123071.0,123063.0,123068.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.32 123073[92:Spt:123071.0,123063.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 123077[92:Res:123073.0,61.1] always3(s22) || -> . % 76.16/76.32 123078[92:SSi:123077.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.32 123079[90:Spt:123078.0,122453.0,122454.0] || until2p7(s21)*+ -> . % 76.16/76.32 123080[90:Spt:123078.0,122453.1] || -> node4(s20)*. % 76.16/76.32 123082[90:MRR:858.0,123080.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.32 123085[90:Res:53.1,123082.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.32 123087[91:Spt:123085.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 123089[91:Res:123087.0,61.1] always3(s20) || -> . % 76.16/76.32 123090[91:SSi:123089.0,78155.0,78159.0,108770.0,122452.0,123080.0] || -> . % 76.16/76.32 123091[91:Spt:123090.0,123085.0,123087.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.32 123092[91:Spt:123090.0,123085.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 123096[91:Res:123092.0,61.1] always3(s21) || -> . % 76.16/76.32 123097[91:SSi:123096.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.32 123098[89:Spt:123097.0,122451.0,122452.0] || until2p7(s20)*+ -> . % 76.16/76.32 123099[89:Spt:123097.0,122451.1] || -> node4(s19)*. % 76.16/76.32 123101[89:MRR:861.0,123099.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.32 123104[89:Res:53.1,123101.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.32 123106[90:Spt:123104.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 123108[90:Res:123106.0,61.1] always3(s19) || -> . % 76.16/76.32 123109[90:SSi:123108.0,78151.0,78154.0,108769.0,122450.0,123099.0] || -> . % 76.16/76.32 123110[90:Spt:123109.0,123104.0,123106.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.32 123111[90:Spt:123109.0,123104.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 123115[90:Res:123111.0,61.1] always3(s20) || -> . % 76.16/76.32 123116[90:SSi:123115.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.32 123117[88:Spt:123116.0,122449.0,122450.0] || until2p7(s19)*+ -> . % 76.16/76.32 123118[88:Spt:123116.0,122449.1] || -> node4(s18)*. % 76.16/76.32 123120[88:MRR:864.0,123118.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.32 123123[88:Res:53.1,123120.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.32 123125[89:Spt:123123.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 123127[89:Res:123125.0,61.1] always3(s18) || -> . % 76.16/76.32 123128[89:SSi:123127.0,78146.0,78150.0,108768.0,122448.0,123118.0] || -> . % 76.16/76.32 123129[89:Spt:123128.0,123123.0,123125.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.32 123130[89:Spt:123128.0,123123.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 123134[89:Res:123130.0,61.1] always3(s19) || -> . % 76.16/76.32 123135[89:SSi:123134.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.32 123136[87:Spt:123135.0,122447.0,122448.0] || until2p7(s18)*+ -> . % 76.16/76.32 123137[87:Spt:123135.0,122447.1] || -> node4(s17)*. % 76.16/76.32 123139[87:MRR:867.0,123137.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.32 123142[87:Res:53.1,123139.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.32 123144[87:MRR:123142.0,122437.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 123149[87:Res:123144.0,61.1] always3(s18) || -> . % 76.16/76.32 123150[87:SSi:123149.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.32 123151[85:Spt:123150.0,122314.0,122317.0] || trans(s49,s17)*+ -> . % 76.16/76.32 123152[85:Spt:123150.0,122314.1,122314.2,122314.3,122314.4,122314.5,122314.6,122314.7,122314.8,122314.9,122314.10,122314.11,122314.12,122314.13,122314.14] || -> trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.32 123154[85:MRR:122316.1,123151.0] xuntil6(s49) || -> trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.32 123155[86:Spt:123152.0] || -> trans(s49,s16)*. % 76.16/76.32 123156[86:Res:123155.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s16)*. % 76.16/76.32 123158[86:Res:123155.0,60.0] || -> node2(s49,s16)*. % 76.16/76.32 123159[86:SSi:123156.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s16)*. % 76.16/76.32 123160[86:Res:123158.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)*. % 76.16/76.32 123268[86:SoR:123160.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)*. % 76.16/76.32 123270[86:SoR:123268.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)* xuntil6(s49). % 76.16/76.32 123271[86:SSi:123270.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s16,c_busy)* xuntil6(s49). % 76.16/76.32 123272[87:Spt:123271.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.32 123274[87:Res:123272.0,61.1] always3(s16) || -> . % 76.16/76.32 123275[87:SSi:123274.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.32 123276[87:Spt:123275.0,123271.1,123272.0] || m_main_v_state(s16,c_busy)*+ -> . % 76.16/76.32 123277[87:Spt:123275.0,123271.0,123271.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.32 123281[87:MRR:123268.2,123276.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.32 123282[87:Res:53.1,123277.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.32 123284[87:MRR:123282.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.32 123285[87:MRR:123159.0,123284.0] || -> until2p7(s16)*. % 76.16/76.32 123286[87:MRR:212.0,123285.0] || -> until2p7(s17)* node4(s16). % 76.16/76.32 123287[88:Spt:123286.0] || -> until2p7(s17)*. % 76.16/76.32 123288[88:MRR:213.0,123287.0] || -> until2p7(s18)* node4(s17). % 76.16/76.32 123289[89:Spt:123288.0] || -> until2p7(s18)*. % 76.16/76.32 123290[89:MRR:214.0,123289.0] || -> until2p7(s19)* node4(s18). % 76.16/76.32 123291[90:Spt:123290.0] || -> until2p7(s19)*. % 76.16/76.32 123292[90:MRR:215.0,123291.0] || -> until2p7(s20)* node4(s19). % 76.16/76.32 123293[91:Spt:123292.0] || -> until2p7(s20)*. % 76.16/76.32 123294[91:MRR:216.0,123293.0] || -> until2p7(s21)* node4(s20). % 76.16/76.32 123295[92:Spt:123294.0] || -> until2p7(s21)*. % 76.16/76.32 123296[92:MRR:217.0,123295.0] || -> until2p7(s22)* node4(s21). % 76.16/76.32 123297[93:Spt:123296.0] || -> until2p7(s22)*. % 76.16/76.32 123298[93:MRR:218.0,123297.0] || -> until2p7(s23)* node4(s22). % 76.16/76.32 123299[94:Spt:123298.0] || -> until2p7(s23)*. % 76.16/76.32 123300[94:MRR:219.0,123299.0] || -> until2p7(s24)* node4(s23). % 76.16/76.32 123301[95:Spt:123300.0] || -> until2p7(s24)*. % 76.16/76.32 123302[95:MRR:220.0,123301.0] || -> until2p7(s25)* node4(s24). % 76.16/76.32 123303[96:Spt:123302.0] || -> until2p7(s25)*. % 76.16/76.32 123304[96:MRR:221.0,123303.0] || -> until2p7(s26)* node4(s25). % 76.16/76.32 123305[97:Spt:123304.0] || -> until2p7(s26)*. % 76.16/76.32 123306[97:MRR:222.0,123305.0] || -> until2p7(s27)* node4(s26). % 76.16/76.32 123307[98:Spt:123306.0] || -> until2p7(s27)*. % 76.16/76.32 123308[98:MRR:223.0,123307.0] || -> until2p7(s28)* node4(s27). % 76.16/76.32 123309[99:Spt:123308.0] || -> until2p7(s28)*. % 76.16/76.32 123310[99:MRR:224.0,123309.0] || -> until2p7(s29)* node4(s28). % 76.16/76.32 123311[100:Spt:123310.0] || -> until2p7(s29)*. % 76.16/76.32 123312[100:MRR:225.0,123311.0] || -> until2p7(s30)* node4(s29). % 76.16/76.32 123313[101:Spt:123312.0] || -> until2p7(s30)*. % 76.16/76.32 123314[101:MRR:226.0,123313.0] || -> until2p7(s31)* node4(s30). % 76.16/76.32 123315[102:Spt:123314.0] || -> until2p7(s31)*. % 76.16/76.32 123316[102:MRR:227.0,123315.0] || -> until2p7(s32)* node4(s31). % 76.16/76.32 123317[103:Spt:123316.0] || -> until2p7(s32)*. % 76.16/76.32 123318[103:MRR:228.0,123317.0] || -> until2p7(s33)* node4(s32). % 76.16/76.32 123319[104:Spt:123318.0] || -> until2p7(s33)*. % 76.16/76.32 123320[104:MRR:229.0,123319.0] || -> until2p7(s34)* node4(s33). % 76.16/76.32 123321[105:Spt:123320.0] || -> until2p7(s34)*. % 76.16/76.32 123322[105:MRR:230.0,123321.0] || -> until2p7(s35)* node4(s34). % 76.16/76.32 123323[106:Spt:123322.0] || -> until2p7(s35)*. % 76.16/76.32 123324[106:MRR:231.0,123323.0] || -> until2p7(s36)* node4(s35). % 76.16/76.32 123325[107:Spt:123324.0] || -> until2p7(s36)*. % 76.16/76.32 123326[107:MRR:232.0,123325.0] || -> until2p7(s37)* node4(s36). % 76.16/76.32 123327[108:Spt:123326.0] || -> until2p7(s37)*. % 76.16/76.32 123328[108:MRR:235.0,123327.0] || -> until2p7(s38)* node4(s37). % 76.16/76.32 123329[109:Spt:123328.0] || -> until2p7(s38)*. % 76.16/76.32 123330[109:MRR:236.0,123329.0] || -> until2p7(s39)* node4(s38). % 76.16/76.32 123331[110:Spt:123330.0] || -> until2p7(s39)*. % 76.16/76.32 123332[110:MRR:237.0,123331.0] || -> until2p7(s40)* node4(s39). % 76.16/76.32 123333[111:Spt:123332.0] || -> until2p7(s40)*. % 76.16/76.32 123334[111:MRR:238.0,123333.0] || -> until2p7(s41)* node4(s40). % 76.16/76.32 123335[112:Spt:123334.0] || -> until2p7(s41)*. % 76.16/76.32 123336[112:MRR:239.0,123335.0] || -> until2p7(s42)* node4(s41). % 76.16/76.32 123337[113:Spt:123336.0] || -> until2p7(s42)*. % 76.16/76.32 123338[113:MRR:240.0,123337.0] || -> until2p7(s43)* node4(s42). % 76.16/76.32 123339[114:Spt:123338.0] || -> until2p7(s43)*. % 76.16/76.32 123340[114:MRR:241.0,123339.0] || -> until2p7(s44)* node4(s43). % 76.16/76.32 123341[115:Spt:123340.0] || -> until2p7(s44)*. % 76.16/76.32 123342[115:MRR:539.0,123341.0] || -> until2p7(s45)* node4(s44). % 76.16/76.32 123343[116:Spt:123342.0] || -> until2p7(s45)*. % 76.16/76.32 123344[116:MRR:544.0,123343.0] || -> until2p7(s46)* node4(s45). % 76.16/76.32 123345[117:Spt:123344.0] || -> until2p7(s46)*. % 76.16/76.32 123346[117:MRR:549.0,123345.0] || -> until2p7(s47)* node4(s46). % 76.16/76.32 123347[118:Spt:123346.0] || -> until2p7(s47)*. % 76.16/76.32 123348[118:MRR:554.0,123347.0] || -> until2p7(s48)* node4(s47). % 76.16/76.32 123349[119:Spt:123348.0] || -> until2p7(s48)*. % 76.16/76.32 123350[119:MRR:559.0,123349.0] || -> until2p7(s49)* node4(s48). % 76.16/76.32 123351[120:Spt:123350.0] || -> until2p7(s49)*. % 76.16/76.32 123352[120:MRR:194.0,123351.0] || -> node4(s49)*. % 76.16/76.32 123353[120:MRR:123281.0,123352.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.32 123357[120:Res:53.1,123353.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.32 123359[120:MRR:123357.0,78381.0] || -> . % 76.16/76.32 123360[120:Spt:123359.0,123350.0,123351.0] || until2p7(s49)*+ -> . % 76.16/76.32 123361[120:Spt:123359.0,123350.1] || -> node4(s48)*. % 76.16/76.32 123362[120:MRR:78384.0,123361.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.32 123365[120:Res:53.1,123362.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 123368[120:Res:123365.0,61.1] always3(s48) || -> . % 76.16/76.32 123369[120:SSi:123368.0,78281.0,78387.0,108798.0,123349.0,123361.0] || -> . % 76.16/76.32 123370[119:Spt:123369.0,123348.0,123349.0] || until2p7(s48)*+ -> . % 76.16/76.32 123371[119:Spt:123369.0,123348.1] || -> node4(s47)*. % 76.16/76.32 123373[119:MRR:777.0,123371.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.32 123385[119:Res:53.1,123373.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.32 123387[120:Spt:123385.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 123389[120:Res:123387.0,61.1] always3(s47) || -> . % 76.16/76.32 123390[120:SSi:123389.0,78277.0,78280.0,108797.0,123347.0,123371.0] || -> . % 76.16/76.32 123391[120:Spt:123390.0,123385.0,123387.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.32 123392[120:Spt:123390.0,123385.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 123396[120:Res:123392.0,61.1] always3(s48) || -> . % 76.16/76.32 123397[120:SSi:123396.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.32 123398[118:Spt:123397.0,123346.0,123347.0] || until2p7(s47)*+ -> . % 76.16/76.32 123399[118:Spt:123397.0,123346.1] || -> node4(s46)*. % 76.16/76.32 123401[118:MRR:780.0,123399.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.32 123408[118:Res:53.1,123401.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.32 123413[119:Spt:123408.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 123415[119:Res:123413.0,61.1] always3(s46) || -> . % 76.16/76.32 123416[119:SSi:123415.0,78272.0,78276.0,108796.0,123345.0,123399.0] || -> . % 76.16/76.32 123417[119:Spt:123416.0,123408.0,123413.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.32 123418[119:Spt:123416.0,123408.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 123422[119:Res:123418.0,61.1] always3(s47) || -> . % 76.16/76.32 123423[119:SSi:123422.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.32 123424[117:Spt:123423.0,123344.0,123345.0] || until2p7(s46)*+ -> . % 76.16/76.32 123425[117:Spt:123423.0,123344.1] || -> node4(s45)*. % 76.16/76.32 123427[117:MRR:783.0,123425.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.32 123430[117:Res:53.1,123427.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.32 123432[118:Spt:123430.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 123434[118:Res:123432.0,61.1] always3(s45) || -> . % 76.16/76.32 123435[118:SSi:123434.0,78268.0,78271.0,108795.0,123343.0,123425.0] || -> . % 76.16/76.32 123436[118:Spt:123435.0,123430.0,123432.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.32 123437[118:Spt:123435.0,123430.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 123441[118:Res:123437.0,61.1] always3(s46) || -> . % 76.16/76.32 123442[118:SSi:123441.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.32 123443[116:Spt:123442.0,123342.0,123343.0] || until2p7(s45)*+ -> . % 76.16/76.32 123444[116:Spt:123442.0,123342.1] || -> node4(s44)*. % 76.16/76.32 123446[116:MRR:786.0,123444.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.32 123449[116:Res:53.1,123446.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.32 123451[117:Spt:123449.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 123453[117:Res:123451.0,61.1] always3(s44) || -> . % 76.16/76.32 123454[117:SSi:123453.0,78263.0,78267.0,108794.0,123341.0,123444.0] || -> . % 76.16/76.32 123455[117:Spt:123454.0,123449.0,123451.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.32 123456[117:Spt:123454.0,123449.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 123460[117:Res:123456.0,61.1] always3(s45) || -> . % 76.16/76.32 123461[117:SSi:123460.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.32 123462[115:Spt:123461.0,123340.0,123341.0] || until2p7(s44)*+ -> . % 76.16/76.32 123463[115:Spt:123461.0,123340.1] || -> node4(s43)*. % 76.16/76.32 123465[115:MRR:789.0,123463.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.32 123468[115:Res:53.1,123465.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.32 123470[116:Spt:123468.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 123472[116:Res:123470.0,61.1] always3(s43) || -> . % 76.16/76.32 123473[116:SSi:123472.0,78259.0,78262.0,108793.0,123339.0,123463.0] || -> . % 76.16/76.32 123474[116:Spt:123473.0,123468.0,123470.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.32 123475[116:Spt:123473.0,123468.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 123479[116:Res:123475.0,61.1] always3(s44) || -> . % 76.16/76.32 123480[116:SSi:123479.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.32 123481[114:Spt:123480.0,123338.0,123339.0] || until2p7(s43)*+ -> . % 76.16/76.32 123482[114:Spt:123480.0,123338.1] || -> node4(s42)*. % 76.16/76.32 123484[114:MRR:792.0,123482.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.32 123487[114:Res:53.1,123484.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.32 123492[115:Spt:123487.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 123494[115:Res:123492.0,61.1] always3(s42) || -> . % 76.16/76.32 123495[115:SSi:123494.0,78254.0,78258.0,108792.0,123337.0,123482.0] || -> . % 76.16/76.32 123496[115:Spt:123495.0,123487.0,123492.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.32 123497[115:Spt:123495.0,123487.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 123501[115:Res:123497.0,61.1] always3(s43) || -> . % 76.16/76.32 123502[115:SSi:123501.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.32 123503[113:Spt:123502.0,123336.0,123337.0] || until2p7(s42)*+ -> . % 76.16/76.32 123504[113:Spt:123502.0,123336.1] || -> node4(s41)*. % 76.16/76.32 123506[113:MRR:795.0,123504.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.32 123509[113:Res:53.1,123506.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.32 123511[114:Spt:123509.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 123513[114:Res:123511.0,61.1] always3(s41) || -> . % 76.16/76.32 123514[114:SSi:123513.0,78250.0,78253.0,108791.0,123335.0,123504.0] || -> . % 76.16/76.32 123515[114:Spt:123514.0,123509.0,123511.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.32 123516[114:Spt:123514.0,123509.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 123520[114:Res:123516.0,61.1] always3(s42) || -> . % 76.16/76.32 123521[114:SSi:123520.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.32 123522[112:Spt:123521.0,123334.0,123335.0] || until2p7(s41)*+ -> . % 76.16/76.32 123523[112:Spt:123521.0,123334.1] || -> node4(s40)*. % 76.16/76.32 123525[112:MRR:798.0,123523.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.32 123528[112:Res:53.1,123525.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.32 123530[113:Spt:123528.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 123532[113:Res:123530.0,61.1] always3(s40) || -> . % 76.16/76.32 123533[113:SSi:123532.0,78245.0,78249.0,108790.0,123333.0,123523.0] || -> . % 76.16/76.32 123534[113:Spt:123533.0,123528.0,123530.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.32 123535[113:Spt:123533.0,123528.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 123539[113:Res:123535.0,61.1] always3(s41) || -> . % 76.16/76.32 123540[113:SSi:123539.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.32 123541[111:Spt:123540.0,123332.0,123333.0] || until2p7(s40)*+ -> . % 76.16/76.32 123542[111:Spt:123540.0,123332.1] || -> node4(s39)*. % 76.16/76.32 123544[111:MRR:801.0,123542.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.32 123547[111:Res:53.1,123544.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.32 123549[112:Spt:123547.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 123551[112:Res:123549.0,61.1] always3(s39) || -> . % 76.16/76.32 123552[112:SSi:123551.0,78241.0,78244.0,108789.0,123331.0,123542.0] || -> . % 76.16/76.32 123553[112:Spt:123552.0,123547.0,123549.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.32 123554[112:Spt:123552.0,123547.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 123558[112:Res:123554.0,61.1] always3(s40) || -> . % 76.16/76.32 123559[112:SSi:123558.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.32 123560[110:Spt:123559.0,123330.0,123331.0] || until2p7(s39)*+ -> . % 76.16/76.32 123561[110:Spt:123559.0,123330.1] || -> node4(s38)*. % 76.16/76.32 123563[110:MRR:804.0,123561.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.32 123566[110:Res:53.1,123563.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.32 123571[111:Spt:123566.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 123573[111:Res:123571.0,61.1] always3(s38) || -> . % 76.16/76.32 123574[111:SSi:123573.0,78236.0,78240.0,108788.0,123329.0,123561.0] || -> . % 76.16/76.32 123575[111:Spt:123574.0,123566.0,123571.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.32 123576[111:Spt:123574.0,123566.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 123580[111:Res:123576.0,61.1] always3(s39) || -> . % 76.16/76.32 123581[111:SSi:123580.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.32 123582[109:Spt:123581.0,123328.0,123329.0] || until2p7(s38)*+ -> . % 76.16/76.32 123583[109:Spt:123581.0,123328.1] || -> node4(s37)*. % 76.16/76.32 123585[109:MRR:807.0,123583.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.32 123588[109:Res:53.1,123585.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.32 123590[110:Spt:123588.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 123592[110:Res:123590.0,61.1] always3(s37) || -> . % 76.16/76.32 123593[110:SSi:123592.0,78232.0,78235.0,108787.0,123327.0,123583.0] || -> . % 76.16/76.32 123594[110:Spt:123593.0,123588.0,123590.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.32 123595[110:Spt:123593.0,123588.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 123599[110:Res:123595.0,61.1] always3(s38) || -> . % 76.16/76.32 123600[110:SSi:123599.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.32 123601[108:Spt:123600.0,123326.0,123327.0] || until2p7(s37)*+ -> . % 76.16/76.32 123602[108:Spt:123600.0,123326.1] || -> node4(s36)*. % 76.16/76.32 123604[108:MRR:810.0,123602.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.32 123607[108:Res:53.1,123604.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.32 123609[109:Spt:123607.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 123611[109:Res:123609.0,61.1] always3(s36) || -> . % 76.16/76.32 123612[109:SSi:123611.0,78227.0,78231.0,108786.0,123325.0,123602.0] || -> . % 76.16/76.32 123613[109:Spt:123612.0,123607.0,123609.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.32 123614[109:Spt:123612.0,123607.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 123618[109:Res:123614.0,61.1] always3(s37) || -> . % 76.16/76.32 123619[109:SSi:123618.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.32 123620[107:Spt:123619.0,123324.0,123325.0] || until2p7(s36)*+ -> . % 76.16/76.32 123621[107:Spt:123619.0,123324.1] || -> node4(s35)*. % 76.16/76.32 123623[107:MRR:813.0,123621.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.32 123626[107:Res:53.1,123623.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.32 123628[108:Spt:123626.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 123630[108:Res:123628.0,61.1] always3(s35) || -> . % 76.16/76.32 123631[108:SSi:123630.0,78223.0,78226.0,108785.0,123323.0,123621.0] || -> . % 76.16/76.32 123632[108:Spt:123631.0,123626.0,123628.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.32 123633[108:Spt:123631.0,123626.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 123637[108:Res:123633.0,61.1] always3(s36) || -> . % 76.16/76.32 123638[108:SSi:123637.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.32 123639[106:Spt:123638.0,123322.0,123323.0] || until2p7(s35)*+ -> . % 76.16/76.32 123640[106:Spt:123638.0,123322.1] || -> node4(s34)*. % 76.16/76.32 123642[106:MRR:816.0,123640.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.32 123645[106:Res:53.1,123642.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.32 123650[107:Spt:123645.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 123652[107:Res:123650.0,61.1] always3(s34) || -> . % 76.16/76.32 123653[107:SSi:123652.0,78218.0,78222.0,108784.0,123321.0,123640.0] || -> . % 76.16/76.32 123654[107:Spt:123653.0,123645.0,123650.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.32 123655[107:Spt:123653.0,123645.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 123659[107:Res:123655.0,61.1] always3(s35) || -> . % 76.16/76.32 123660[107:SSi:123659.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.32 123661[105:Spt:123660.0,123320.0,123321.0] || until2p7(s34)*+ -> . % 76.16/76.32 123662[105:Spt:123660.0,123320.1] || -> node4(s33)*. % 76.16/76.32 123664[105:MRR:819.0,123662.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.32 123667[105:Res:53.1,123664.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.32 123669[106:Spt:123667.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 123671[106:Res:123669.0,61.1] always3(s33) || -> . % 76.16/76.32 123672[106:SSi:123671.0,78214.0,78217.0,108783.0,123319.0,123662.0] || -> . % 76.16/76.32 123673[106:Spt:123672.0,123667.0,123669.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.32 123674[106:Spt:123672.0,123667.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 123678[106:Res:123674.0,61.1] always3(s34) || -> . % 76.16/76.32 123679[106:SSi:123678.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.32 123680[104:Spt:123679.0,123318.0,123319.0] || until2p7(s33)*+ -> . % 76.16/76.32 123681[104:Spt:123679.0,123318.1] || -> node4(s32)*. % 76.16/76.32 123683[104:MRR:822.0,123681.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.32 123686[104:Res:53.1,123683.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.32 123688[105:Spt:123686.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 123690[105:Res:123688.0,61.1] always3(s32) || -> . % 76.16/76.32 123691[105:SSi:123690.0,78209.0,78213.0,108782.0,123317.0,123681.0] || -> . % 76.16/76.32 123692[105:Spt:123691.0,123686.0,123688.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.32 123693[105:Spt:123691.0,123686.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 123697[105:Res:123693.0,61.1] always3(s33) || -> . % 76.16/76.32 123698[105:SSi:123697.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.32 123699[103:Spt:123698.0,123316.0,123317.0] || until2p7(s32)*+ -> . % 76.16/76.32 123700[103:Spt:123698.0,123316.1] || -> node4(s31)*. % 76.16/76.32 123702[103:MRR:825.0,123700.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.32 123705[103:Res:53.1,123702.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.32 123707[104:Spt:123705.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 123709[104:Res:123707.0,61.1] always3(s31) || -> . % 76.16/76.32 123710[104:SSi:123709.0,78205.0,78208.0,108781.0,123315.0,123700.0] || -> . % 76.16/76.32 123711[104:Spt:123710.0,123705.0,123707.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.32 123712[104:Spt:123710.0,123705.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 123716[104:Res:123712.0,61.1] always3(s32) || -> . % 76.16/76.32 123717[104:SSi:123716.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.32 123718[102:Spt:123717.0,123314.0,123315.0] || until2p7(s31)*+ -> . % 76.16/76.32 123719[102:Spt:123717.0,123314.1] || -> node4(s30)*. % 76.16/76.32 123721[102:MRR:828.0,123719.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.32 123724[102:Res:53.1,123721.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.32 123729[103:Spt:123724.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 123731[103:Res:123729.0,61.1] always3(s30) || -> . % 76.16/76.32 123732[103:SSi:123731.0,78200.0,78204.0,108780.0,123313.0,123719.0] || -> . % 76.16/76.32 123733[103:Spt:123732.0,123724.0,123729.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.32 123734[103:Spt:123732.0,123724.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 123738[103:Res:123734.0,61.1] always3(s31) || -> . % 76.16/76.32 123739[103:SSi:123738.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.32 123740[101:Spt:123739.0,123312.0,123313.0] || until2p7(s30)*+ -> . % 76.16/76.32 123741[101:Spt:123739.0,123312.1] || -> node4(s29)*. % 76.16/76.32 123743[101:MRR:831.0,123741.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.32 123746[101:Res:53.1,123743.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.32 123748[102:Spt:123746.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 123750[102:Res:123748.0,61.1] always3(s29) || -> . % 76.16/76.32 123751[102:SSi:123750.0,78196.0,78199.0,108779.0,123311.0,123741.0] || -> . % 76.16/76.32 123752[102:Spt:123751.0,123746.0,123748.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.32 123753[102:Spt:123751.0,123746.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 123757[102:Res:123753.0,61.1] always3(s30) || -> . % 76.16/76.32 123758[102:SSi:123757.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.32 123759[100:Spt:123758.0,123310.0,123311.0] || until2p7(s29)*+ -> . % 76.16/76.32 123760[100:Spt:123758.0,123310.1] || -> node4(s28)*. % 76.16/76.32 123762[100:MRR:834.0,123760.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.32 123765[100:Res:53.1,123762.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.32 123767[101:Spt:123765.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 123769[101:Res:123767.0,61.1] always3(s28) || -> . % 76.16/76.32 123770[101:SSi:123769.0,78191.0,78195.0,108778.0,123309.0,123760.0] || -> . % 76.16/76.32 123771[101:Spt:123770.0,123765.0,123767.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.32 123772[101:Spt:123770.0,123765.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 123776[101:Res:123772.0,61.1] always3(s29) || -> . % 76.16/76.32 123777[101:SSi:123776.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.32 123778[99:Spt:123777.0,123308.0,123309.0] || until2p7(s28)*+ -> . % 76.16/76.32 123779[99:Spt:123777.0,123308.1] || -> node4(s27)*. % 76.16/76.32 123781[99:MRR:837.0,123779.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.32 123784[99:Res:53.1,123781.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.32 123786[100:Spt:123784.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 123788[100:Res:123786.0,61.1] always3(s27) || -> . % 76.16/76.32 123789[100:SSi:123788.0,78187.0,78190.0,108777.0,123307.0,123779.0] || -> . % 76.16/76.32 123790[100:Spt:123789.0,123784.0,123786.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.32 123791[100:Spt:123789.0,123784.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 123795[100:Res:123791.0,61.1] always3(s28) || -> . % 76.16/76.32 123796[100:SSi:123795.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.32 123797[98:Spt:123796.0,123306.0,123307.0] || until2p7(s27)*+ -> . % 76.16/76.32 123798[98:Spt:123796.0,123306.1] || -> node4(s26)*. % 76.16/76.32 123800[98:MRR:840.0,123798.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.32 123803[98:Res:53.1,123800.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.32 123808[99:Spt:123803.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 123810[99:Res:123808.0,61.1] always3(s26) || -> . % 76.16/76.32 123811[99:SSi:123810.0,78182.0,78186.0,108776.0,123305.0,123798.0] || -> . % 76.16/76.32 123812[99:Spt:123811.0,123803.0,123808.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.32 123813[99:Spt:123811.0,123803.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 123817[99:Res:123813.0,61.1] always3(s27) || -> . % 76.16/76.32 123818[99:SSi:123817.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.32 123819[97:Spt:123818.0,123304.0,123305.0] || until2p7(s26)*+ -> . % 76.16/76.32 123820[97:Spt:123818.0,123304.1] || -> node4(s25)*. % 76.16/76.32 123822[97:MRR:843.0,123820.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.32 123825[97:Res:53.1,123822.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.32 123827[98:Spt:123825.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 123829[98:Res:123827.0,61.1] always3(s25) || -> . % 76.16/76.32 123830[98:SSi:123829.0,78178.0,78181.0,108775.0,123303.0,123820.0] || -> . % 76.16/76.32 123831[98:Spt:123830.0,123825.0,123827.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.32 123832[98:Spt:123830.0,123825.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 123836[98:Res:123832.0,61.1] always3(s26) || -> . % 76.16/76.32 123837[98:SSi:123836.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.32 123838[96:Spt:123837.0,123302.0,123303.0] || until2p7(s25)*+ -> . % 76.16/76.32 123839[96:Spt:123837.0,123302.1] || -> node4(s24)*. % 76.16/76.32 123841[96:MRR:846.0,123839.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.32 123844[96:Res:53.1,123841.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.32 123846[97:Spt:123844.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 123848[97:Res:123846.0,61.1] always3(s24) || -> . % 76.16/76.32 123849[97:SSi:123848.0,78173.0,78177.0,108774.0,123301.0,123839.0] || -> . % 76.16/76.32 123850[97:Spt:123849.0,123844.0,123846.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.32 123851[97:Spt:123849.0,123844.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 123855[97:Res:123851.0,61.1] always3(s25) || -> . % 76.16/76.32 123856[97:SSi:123855.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.32 123857[95:Spt:123856.0,123300.0,123301.0] || until2p7(s24)*+ -> . % 76.16/76.32 123858[95:Spt:123856.0,123300.1] || -> node4(s23)*. % 76.16/76.32 123860[95:MRR:849.0,123858.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.32 123863[95:Res:53.1,123860.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.32 123865[96:Spt:123863.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 123867[96:Res:123865.0,61.1] always3(s23) || -> . % 76.16/76.32 123868[96:SSi:123867.0,78169.0,78172.0,108773.0,123299.0,123858.0] || -> . % 76.16/76.32 123869[96:Spt:123868.0,123863.0,123865.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.32 123870[96:Spt:123868.0,123863.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 123874[96:Res:123870.0,61.1] always3(s24) || -> . % 76.16/76.32 123875[96:SSi:123874.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.32 123876[94:Spt:123875.0,123298.0,123299.0] || until2p7(s23)*+ -> . % 76.16/76.32 123877[94:Spt:123875.0,123298.1] || -> node4(s22)*. % 76.16/76.32 123879[94:MRR:852.0,123877.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.32 123882[94:Res:53.1,123879.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.32 123887[95:Spt:123882.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 123889[95:Res:123887.0,61.1] always3(s22) || -> . % 76.16/76.32 123890[95:SSi:123889.0,78164.0,78168.0,108772.0,123297.0,123877.0] || -> . % 76.16/76.32 123891[95:Spt:123890.0,123882.0,123887.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.32 123892[95:Spt:123890.0,123882.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 123896[95:Res:123892.0,61.1] always3(s23) || -> . % 76.16/76.32 123897[95:SSi:123896.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.32 123898[93:Spt:123897.0,123296.0,123297.0] || until2p7(s22)*+ -> . % 76.16/76.32 123899[93:Spt:123897.0,123296.1] || -> node4(s21)*. % 76.16/76.32 123901[93:MRR:855.0,123899.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.32 123904[93:Res:53.1,123901.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.32 123906[94:Spt:123904.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 123908[94:Res:123906.0,61.1] always3(s21) || -> . % 76.16/76.32 123909[94:SSi:123908.0,78160.0,78163.0,108771.0,123295.0,123899.0] || -> . % 76.16/76.32 123910[94:Spt:123909.0,123904.0,123906.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.32 123911[94:Spt:123909.0,123904.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 123915[94:Res:123911.0,61.1] always3(s22) || -> . % 76.16/76.32 123916[94:SSi:123915.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.32 123917[92:Spt:123916.0,123294.0,123295.0] || until2p7(s21)*+ -> . % 76.16/76.32 123918[92:Spt:123916.0,123294.1] || -> node4(s20)*. % 76.16/76.32 123920[92:MRR:858.0,123918.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.32 123923[92:Res:53.1,123920.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.32 123925[93:Spt:123923.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 123927[93:Res:123925.0,61.1] always3(s20) || -> . % 76.16/76.32 123928[93:SSi:123927.0,78155.0,78159.0,108770.0,123293.0,123918.0] || -> . % 76.16/76.32 123929[93:Spt:123928.0,123923.0,123925.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.32 123930[93:Spt:123928.0,123923.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 123934[93:Res:123930.0,61.1] always3(s21) || -> . % 76.16/76.32 123935[93:SSi:123934.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.32 123936[91:Spt:123935.0,123292.0,123293.0] || until2p7(s20)*+ -> . % 76.16/76.32 123937[91:Spt:123935.0,123292.1] || -> node4(s19)*. % 76.16/76.32 123939[91:MRR:861.0,123937.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.32 123942[91:Res:53.1,123939.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.32 123944[92:Spt:123942.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 123946[92:Res:123944.0,61.1] always3(s19) || -> . % 76.16/76.32 123947[92:SSi:123946.0,78151.0,78154.0,108769.0,123291.0,123937.0] || -> . % 76.16/76.32 123948[92:Spt:123947.0,123942.0,123944.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.32 123949[92:Spt:123947.0,123942.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 123953[92:Res:123949.0,61.1] always3(s20) || -> . % 76.16/76.32 123954[92:SSi:123953.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.32 123955[90:Spt:123954.0,123290.0,123291.0] || until2p7(s19)*+ -> . % 76.16/76.32 123956[90:Spt:123954.0,123290.1] || -> node4(s18)*. % 76.16/76.32 123958[90:MRR:864.0,123956.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.32 123961[90:Res:53.1,123958.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.32 123966[91:Spt:123961.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 123968[91:Res:123966.0,61.1] always3(s18) || -> . % 76.16/76.32 123969[91:SSi:123968.0,78146.0,78150.0,108768.0,123289.0,123956.0] || -> . % 76.16/76.32 123970[91:Spt:123969.0,123961.0,123966.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.32 123971[91:Spt:123969.0,123961.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 123975[91:Res:123971.0,61.1] always3(s19) || -> . % 76.16/76.32 123976[91:SSi:123975.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.32 123977[89:Spt:123976.0,123288.0,123289.0] || until2p7(s18)*+ -> . % 76.16/76.32 123978[89:Spt:123976.0,123288.1] || -> node4(s17)*. % 76.16/76.32 123980[89:MRR:867.0,123978.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.32 123983[89:Res:53.1,123980.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.32 123985[90:Spt:123983.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 123987[90:Res:123985.0,61.1] always3(s17) || -> . % 76.16/76.32 123988[90:SSi:123987.0,78142.0,78145.0,108767.0,123287.0,123978.0] || -> . % 76.16/76.32 123989[90:Spt:123988.0,123983.0,123985.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.32 123990[90:Spt:123988.0,123983.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 123994[90:Res:123990.0,61.1] always3(s18) || -> . % 76.16/76.32 123995[90:SSi:123994.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.32 123996[88:Spt:123995.0,123286.0,123287.0] || until2p7(s17)*+ -> . % 76.16/76.32 123997[88:Spt:123995.0,123286.1] || -> node4(s16)*. % 76.16/76.32 123999[88:MRR:870.0,123997.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.32 124002[88:Res:53.1,123999.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.32 124004[88:MRR:124002.0,123276.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 124006[88:Res:124004.0,61.1] always3(s17) || -> . % 76.16/76.32 124007[88:SSi:124006.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.32 124008[86:Spt:124007.0,123152.0,123155.0] || trans(s49,s16)*+ -> . % 76.16/76.32 124009[86:Spt:124007.0,123152.1,123152.2,123152.3,123152.4,123152.5,123152.6,123152.7,123152.8,123152.9,123152.10,123152.11,123152.12,123152.13] || -> trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.32 124011[86:MRR:123154.1,124008.0] xuntil6(s49) || -> trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.32 124012[87:Spt:124009.0] || -> trans(s49,s15)*. % 76.16/76.32 124013[87:Res:124012.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s15)*. % 76.16/76.32 124015[87:Res:124012.0,60.0] || -> node2(s49,s15)*. % 76.16/76.32 124016[87:SSi:124013.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s15)*. % 76.16/76.32 124017[87:Res:124015.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)*. % 76.16/76.32 124132[87:SoR:124017.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)*. % 76.16/76.32 124134[87:SoR:124132.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)* xuntil6(s49). % 76.16/76.32 124135[87:SSi:124134.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s15,c_busy)* xuntil6(s49). % 76.16/76.32 124136[88:Spt:124135.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.32 124138[88:Res:124136.0,61.1] always3(s15) || -> . % 76.16/76.32 124139[88:SSi:124138.0,78133.0,78136.0,108765.0] || -> . % 76.16/76.32 124140[88:Spt:124139.0,124135.1,124136.0] || m_main_v_state(s15,c_busy)*+ -> . % 76.16/76.32 124141[88:Spt:124139.0,124135.0,124135.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.32 124145[88:MRR:124132.2,124140.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.32 124146[88:Res:53.1,124141.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.32 124148[88:MRR:124146.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.32 124149[88:MRR:124016.0,124148.0] || -> until2p7(s15)*. % 76.16/76.32 124150[88:MRR:211.0,124149.0] || -> until2p7(s16)* node4(s15). % 76.16/76.32 124151[89:Spt:124150.0] || -> until2p7(s16)*. % 76.16/76.32 124152[89:MRR:212.0,124151.0] || -> until2p7(s17)* node4(s16). % 76.16/76.32 124153[90:Spt:124152.0] || -> until2p7(s17)*. % 76.16/76.32 124154[90:MRR:213.0,124153.0] || -> until2p7(s18)* node4(s17). % 76.16/76.32 124155[91:Spt:124154.0] || -> until2p7(s18)*. % 76.16/76.32 124156[91:MRR:214.0,124155.0] || -> until2p7(s19)* node4(s18). % 76.16/76.32 124157[92:Spt:124156.0] || -> until2p7(s19)*. % 76.16/76.32 124158[92:MRR:215.0,124157.0] || -> until2p7(s20)* node4(s19). % 76.16/76.32 124159[93:Spt:124158.0] || -> until2p7(s20)*. % 76.16/76.32 124160[93:MRR:216.0,124159.0] || -> until2p7(s21)* node4(s20). % 76.16/76.32 124161[94:Spt:124160.0] || -> until2p7(s21)*. % 76.16/76.32 124162[94:MRR:217.0,124161.0] || -> until2p7(s22)* node4(s21). % 76.16/76.32 124163[95:Spt:124162.0] || -> until2p7(s22)*. % 76.16/76.32 124164[95:MRR:218.0,124163.0] || -> until2p7(s23)* node4(s22). % 76.16/76.32 124165[96:Spt:124164.0] || -> until2p7(s23)*. % 76.16/76.32 124166[96:MRR:219.0,124165.0] || -> until2p7(s24)* node4(s23). % 76.16/76.32 124167[97:Spt:124166.0] || -> until2p7(s24)*. % 76.16/76.32 124168[97:MRR:220.0,124167.0] || -> until2p7(s25)* node4(s24). % 76.16/76.32 124169[98:Spt:124168.0] || -> until2p7(s25)*. % 76.16/76.32 124170[98:MRR:221.0,124169.0] || -> until2p7(s26)* node4(s25). % 76.16/76.32 124171[99:Spt:124170.0] || -> until2p7(s26)*. % 76.16/76.32 124172[99:MRR:222.0,124171.0] || -> until2p7(s27)* node4(s26). % 76.16/76.32 124173[100:Spt:124172.0] || -> until2p7(s27)*. % 76.16/76.32 124174[100:MRR:223.0,124173.0] || -> until2p7(s28)* node4(s27). % 76.16/76.32 124175[101:Spt:124174.0] || -> until2p7(s28)*. % 76.16/76.32 124176[101:MRR:224.0,124175.0] || -> until2p7(s29)* node4(s28). % 76.16/76.32 124177[102:Spt:124176.0] || -> until2p7(s29)*. % 76.16/76.32 124178[102:MRR:225.0,124177.0] || -> until2p7(s30)* node4(s29). % 76.16/76.32 124179[103:Spt:124178.0] || -> until2p7(s30)*. % 76.16/76.32 124180[103:MRR:226.0,124179.0] || -> until2p7(s31)* node4(s30). % 76.16/76.32 124181[104:Spt:124180.0] || -> until2p7(s31)*. % 76.16/76.32 124182[104:MRR:227.0,124181.0] || -> until2p7(s32)* node4(s31). % 76.16/76.32 124183[105:Spt:124182.0] || -> until2p7(s32)*. % 76.16/76.32 124184[105:MRR:228.0,124183.0] || -> until2p7(s33)* node4(s32). % 76.16/76.32 124185[106:Spt:124184.0] || -> until2p7(s33)*. % 76.16/76.32 124186[106:MRR:229.0,124185.0] || -> until2p7(s34)* node4(s33). % 76.16/76.32 124187[107:Spt:124186.0] || -> until2p7(s34)*. % 76.16/76.32 124188[107:MRR:230.0,124187.0] || -> until2p7(s35)* node4(s34). % 76.16/76.32 124189[108:Spt:124188.0] || -> until2p7(s35)*. % 76.16/76.32 124190[108:MRR:231.0,124189.0] || -> until2p7(s36)* node4(s35). % 76.16/76.32 124191[109:Spt:124190.0] || -> until2p7(s36)*. % 76.16/76.32 124192[109:MRR:232.0,124191.0] || -> until2p7(s37)* node4(s36). % 76.16/76.32 124193[110:Spt:124192.0] || -> until2p7(s37)*. % 76.16/76.32 124194[110:MRR:235.0,124193.0] || -> until2p7(s38)* node4(s37). % 76.16/76.32 124195[111:Spt:124194.0] || -> until2p7(s38)*. % 76.16/76.32 124196[111:MRR:236.0,124195.0] || -> until2p7(s39)* node4(s38). % 76.16/76.32 124197[112:Spt:124196.0] || -> until2p7(s39)*. % 76.16/76.32 124198[112:MRR:237.0,124197.0] || -> until2p7(s40)* node4(s39). % 76.16/76.32 124199[113:Spt:124198.0] || -> until2p7(s40)*. % 76.16/76.32 124200[113:MRR:238.0,124199.0] || -> until2p7(s41)* node4(s40). % 76.16/76.32 124201[114:Spt:124200.0] || -> until2p7(s41)*. % 76.16/76.32 124202[114:MRR:239.0,124201.0] || -> until2p7(s42)* node4(s41). % 76.16/76.32 124203[115:Spt:124202.0] || -> until2p7(s42)*. % 76.16/76.32 124204[115:MRR:240.0,124203.0] || -> until2p7(s43)* node4(s42). % 76.16/76.32 124205[116:Spt:124204.0] || -> until2p7(s43)*. % 76.16/76.32 124206[116:MRR:241.0,124205.0] || -> until2p7(s44)* node4(s43). % 76.16/76.32 124207[117:Spt:124206.0] || -> until2p7(s44)*. % 76.16/76.32 124208[117:MRR:539.0,124207.0] || -> until2p7(s45)* node4(s44). % 76.16/76.32 124209[118:Spt:124208.0] || -> until2p7(s45)*. % 76.16/76.32 124210[118:MRR:544.0,124209.0] || -> until2p7(s46)* node4(s45). % 76.16/76.32 124211[119:Spt:124210.0] || -> until2p7(s46)*. % 76.16/76.32 124212[119:MRR:549.0,124211.0] || -> until2p7(s47)* node4(s46). % 76.16/76.32 124213[120:Spt:124212.0] || -> until2p7(s47)*. % 76.16/76.32 124214[120:MRR:554.0,124213.0] || -> until2p7(s48)* node4(s47). % 76.16/76.32 124215[121:Spt:124214.0] || -> until2p7(s48)*. % 76.16/76.32 124216[121:MRR:559.0,124215.0] || -> until2p7(s49)* node4(s48). % 76.16/76.32 124217[122:Spt:124216.0] || -> until2p7(s49)*. % 76.16/76.32 124218[122:MRR:194.0,124217.0] || -> node4(s49)*. % 76.16/76.32 124219[122:MRR:124145.0,124218.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.32 124220[122:Res:53.1,124219.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.32 124222[122:MRR:124220.0,78381.0] || -> . % 76.16/76.32 124223[122:Spt:124222.0,124216.0,124217.0] || until2p7(s49)*+ -> . % 76.16/76.32 124224[122:Spt:124222.0,124216.1] || -> node4(s48)*. % 76.16/76.32 124225[122:MRR:78384.0,124224.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.32 124228[122:Res:53.1,124225.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 124231[122:Res:124228.0,61.1] always3(s48) || -> . % 76.16/76.32 124232[122:SSi:124231.0,78281.0,78387.0,108798.0,124215.0,124224.0] || -> . % 76.16/76.32 124233[121:Spt:124232.0,124214.0,124215.0] || until2p7(s48)*+ -> . % 76.16/76.32 124234[121:Spt:124232.0,124214.1] || -> node4(s47)*. % 76.16/76.32 124236[121:MRR:777.0,124234.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.32 124251[121:Res:53.1,124236.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.32 124253[122:Spt:124251.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 124255[122:Res:124253.0,61.1] always3(s47) || -> . % 76.16/76.32 124256[122:SSi:124255.0,78277.0,78280.0,108797.0,124213.0,124234.0] || -> . % 76.16/76.32 124257[122:Spt:124256.0,124251.0,124253.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.32 124258[122:Spt:124256.0,124251.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 124262[122:Res:124258.0,61.1] always3(s48) || -> . % 76.16/76.32 124263[122:SSi:124262.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.32 124264[120:Spt:124263.0,124212.0,124213.0] || until2p7(s47)*+ -> . % 76.16/76.32 124265[120:Spt:124263.0,124212.1] || -> node4(s46)*. % 76.16/76.32 124267[120:MRR:780.0,124265.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.32 124277[120:Res:53.1,124267.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.32 124279[121:Spt:124277.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 124281[121:Res:124279.0,61.1] always3(s46) || -> . % 76.16/76.32 124282[121:SSi:124281.0,78272.0,78276.0,108796.0,124211.0,124265.0] || -> . % 76.16/76.32 124283[121:Spt:124282.0,124277.0,124279.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.32 124284[121:Spt:124282.0,124277.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 124288[121:Res:124284.0,61.1] always3(s47) || -> . % 76.16/76.32 124289[121:SSi:124288.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.32 124290[119:Spt:124289.0,124210.0,124211.0] || until2p7(s46)*+ -> . % 76.16/76.32 124291[119:Spt:124289.0,124210.1] || -> node4(s45)*. % 76.16/76.32 124293[119:MRR:783.0,124291.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.32 124296[119:Res:53.1,124293.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.32 124298[120:Spt:124296.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 124300[120:Res:124298.0,61.1] always3(s45) || -> . % 76.16/76.32 124301[120:SSi:124300.0,78268.0,78271.0,108795.0,124209.0,124291.0] || -> . % 76.16/76.32 124302[120:Spt:124301.0,124296.0,124298.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.32 124303[120:Spt:124301.0,124296.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 124307[120:Res:124303.0,61.1] always3(s46) || -> . % 76.16/76.32 124308[120:SSi:124307.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.32 124309[118:Spt:124308.0,124208.0,124209.0] || until2p7(s45)*+ -> . % 76.16/76.32 124310[118:Spt:124308.0,124208.1] || -> node4(s44)*. % 76.16/76.32 124312[118:MRR:786.0,124310.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.32 124315[118:Res:53.1,124312.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.32 124317[119:Spt:124315.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 124319[119:Res:124317.0,61.1] always3(s44) || -> . % 76.16/76.32 124320[119:SSi:124319.0,78263.0,78267.0,108794.0,124207.0,124310.0] || -> . % 76.16/76.32 124321[119:Spt:124320.0,124315.0,124317.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.32 124322[119:Spt:124320.0,124315.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 124326[119:Res:124322.0,61.1] always3(s45) || -> . % 76.16/76.32 124327[119:SSi:124326.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.32 124328[117:Spt:124327.0,124206.0,124207.0] || until2p7(s44)*+ -> . % 76.16/76.32 124329[117:Spt:124327.0,124206.1] || -> node4(s43)*. % 76.16/76.32 124331[117:MRR:789.0,124329.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.32 124334[117:Res:53.1,124331.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.32 124339[118:Spt:124334.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 124341[118:Res:124339.0,61.1] always3(s43) || -> . % 76.16/76.32 124342[118:SSi:124341.0,78259.0,78262.0,108793.0,124205.0,124329.0] || -> . % 76.16/76.32 124343[118:Spt:124342.0,124334.0,124339.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.32 124344[118:Spt:124342.0,124334.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 124348[118:Res:124344.0,61.1] always3(s44) || -> . % 76.16/76.32 124349[118:SSi:124348.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.32 124350[116:Spt:124349.0,124204.0,124205.0] || until2p7(s43)*+ -> . % 76.16/76.32 124351[116:Spt:124349.0,124204.1] || -> node4(s42)*. % 76.16/76.32 124353[116:MRR:792.0,124351.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.32 124356[116:Res:53.1,124353.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.32 124358[117:Spt:124356.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 124360[117:Res:124358.0,61.1] always3(s42) || -> . % 76.16/76.32 124361[117:SSi:124360.0,78254.0,78258.0,108792.0,124203.0,124351.0] || -> . % 76.16/76.32 124362[117:Spt:124361.0,124356.0,124358.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.32 124363[117:Spt:124361.0,124356.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 124367[117:Res:124363.0,61.1] always3(s43) || -> . % 76.16/76.32 124368[117:SSi:124367.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.32 124369[115:Spt:124368.0,124202.0,124203.0] || until2p7(s42)*+ -> . % 76.16/76.32 124370[115:Spt:124368.0,124202.1] || -> node4(s41)*. % 76.16/76.32 124372[115:MRR:795.0,124370.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.32 124375[115:Res:53.1,124372.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.32 124377[116:Spt:124375.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 124379[116:Res:124377.0,61.1] always3(s41) || -> . % 76.16/76.32 124380[116:SSi:124379.0,78250.0,78253.0,108791.0,124201.0,124370.0] || -> . % 76.16/76.32 124381[116:Spt:124380.0,124375.0,124377.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.32 124382[116:Spt:124380.0,124375.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 124386[116:Res:124382.0,61.1] always3(s42) || -> . % 76.16/76.32 124387[116:SSi:124386.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.32 124388[114:Spt:124387.0,124200.0,124201.0] || until2p7(s41)*+ -> . % 76.16/76.32 124389[114:Spt:124387.0,124200.1] || -> node4(s40)*. % 76.16/76.32 124391[114:MRR:798.0,124389.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.32 124394[114:Res:53.1,124391.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.32 124396[115:Spt:124394.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 124398[115:Res:124396.0,61.1] always3(s40) || -> . % 76.16/76.32 124399[115:SSi:124398.0,78245.0,78249.0,108790.0,124199.0,124389.0] || -> . % 76.16/76.32 124400[115:Spt:124399.0,124394.0,124396.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.32 124401[115:Spt:124399.0,124394.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 124405[115:Res:124401.0,61.1] always3(s41) || -> . % 76.16/76.32 124406[115:SSi:124405.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.32 124407[113:Spt:124406.0,124198.0,124199.0] || until2p7(s40)*+ -> . % 76.16/76.32 124408[113:Spt:124406.0,124198.1] || -> node4(s39)*. % 76.16/76.32 124410[113:MRR:801.0,124408.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.32 124413[113:Res:53.1,124410.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.32 124418[114:Spt:124413.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 124420[114:Res:124418.0,61.1] always3(s39) || -> . % 76.16/76.32 124421[114:SSi:124420.0,78241.0,78244.0,108789.0,124197.0,124408.0] || -> . % 76.16/76.32 124422[114:Spt:124421.0,124413.0,124418.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.32 124423[114:Spt:124421.0,124413.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 124427[114:Res:124423.0,61.1] always3(s40) || -> . % 76.16/76.32 124428[114:SSi:124427.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.32 124429[112:Spt:124428.0,124196.0,124197.0] || until2p7(s39)*+ -> . % 76.16/76.32 124430[112:Spt:124428.0,124196.1] || -> node4(s38)*. % 76.16/76.32 124432[112:MRR:804.0,124430.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.32 124435[112:Res:53.1,124432.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.32 124437[113:Spt:124435.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 124439[113:Res:124437.0,61.1] always3(s38) || -> . % 76.16/76.32 124440[113:SSi:124439.0,78236.0,78240.0,108788.0,124195.0,124430.0] || -> . % 76.16/76.32 124441[113:Spt:124440.0,124435.0,124437.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.32 124442[113:Spt:124440.0,124435.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 124446[113:Res:124442.0,61.1] always3(s39) || -> . % 76.16/76.32 124447[113:SSi:124446.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.32 124448[111:Spt:124447.0,124194.0,124195.0] || until2p7(s38)*+ -> . % 76.16/76.32 124449[111:Spt:124447.0,124194.1] || -> node4(s37)*. % 76.16/76.32 124451[111:MRR:807.0,124449.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.32 124454[111:Res:53.1,124451.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.32 124456[112:Spt:124454.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 124458[112:Res:124456.0,61.1] always3(s37) || -> . % 76.16/76.32 124459[112:SSi:124458.0,78232.0,78235.0,108787.0,124193.0,124449.0] || -> . % 76.16/76.32 124460[112:Spt:124459.0,124454.0,124456.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.32 124461[112:Spt:124459.0,124454.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 124465[112:Res:124461.0,61.1] always3(s38) || -> . % 76.16/76.32 124466[112:SSi:124465.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.32 124467[110:Spt:124466.0,124192.0,124193.0] || until2p7(s37)*+ -> . % 76.16/76.32 124468[110:Spt:124466.0,124192.1] || -> node4(s36)*. % 76.16/76.32 124470[110:MRR:810.0,124468.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.32 124473[110:Res:53.1,124470.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.32 124475[111:Spt:124473.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 124477[111:Res:124475.0,61.1] always3(s36) || -> . % 76.16/76.32 124478[111:SSi:124477.0,78227.0,78231.0,108786.0,124191.0,124468.0] || -> . % 76.16/76.32 124479[111:Spt:124478.0,124473.0,124475.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.32 124480[111:Spt:124478.0,124473.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 124484[111:Res:124480.0,61.1] always3(s37) || -> . % 76.16/76.32 124485[111:SSi:124484.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.32 124486[109:Spt:124485.0,124190.0,124191.0] || until2p7(s36)*+ -> . % 76.16/76.32 124487[109:Spt:124485.0,124190.1] || -> node4(s35)*. % 76.16/76.32 124489[109:MRR:813.0,124487.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.32 124492[109:Res:53.1,124489.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.32 124497[110:Spt:124492.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 124499[110:Res:124497.0,61.1] always3(s35) || -> . % 76.16/76.32 124500[110:SSi:124499.0,78223.0,78226.0,108785.0,124189.0,124487.0] || -> . % 76.16/76.32 124501[110:Spt:124500.0,124492.0,124497.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.32 124502[110:Spt:124500.0,124492.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 124506[110:Res:124502.0,61.1] always3(s36) || -> . % 76.16/76.32 124507[110:SSi:124506.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.32 124508[108:Spt:124507.0,124188.0,124189.0] || until2p7(s35)*+ -> . % 76.16/76.32 124509[108:Spt:124507.0,124188.1] || -> node4(s34)*. % 76.16/76.32 124511[108:MRR:816.0,124509.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.32 124514[108:Res:53.1,124511.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.32 124516[109:Spt:124514.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 124518[109:Res:124516.0,61.1] always3(s34) || -> . % 76.16/76.32 124519[109:SSi:124518.0,78218.0,78222.0,108784.0,124187.0,124509.0] || -> . % 76.16/76.32 124520[109:Spt:124519.0,124514.0,124516.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.32 124521[109:Spt:124519.0,124514.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 124525[109:Res:124521.0,61.1] always3(s35) || -> . % 76.16/76.32 124526[109:SSi:124525.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.32 124527[107:Spt:124526.0,124186.0,124187.0] || until2p7(s34)*+ -> . % 76.16/76.32 124528[107:Spt:124526.0,124186.1] || -> node4(s33)*. % 76.16/76.32 124530[107:MRR:819.0,124528.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.32 124533[107:Res:53.1,124530.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.32 124535[108:Spt:124533.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 124537[108:Res:124535.0,61.1] always3(s33) || -> . % 76.16/76.32 124538[108:SSi:124537.0,78214.0,78217.0,108783.0,124185.0,124528.0] || -> . % 76.16/76.32 124539[108:Spt:124538.0,124533.0,124535.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.32 124540[108:Spt:124538.0,124533.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 124544[108:Res:124540.0,61.1] always3(s34) || -> . % 76.16/76.32 124545[108:SSi:124544.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.32 124546[106:Spt:124545.0,124184.0,124185.0] || until2p7(s33)*+ -> . % 76.16/76.32 124547[106:Spt:124545.0,124184.1] || -> node4(s32)*. % 76.16/76.32 124549[106:MRR:822.0,124547.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.32 124552[106:Res:53.1,124549.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.32 124554[107:Spt:124552.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 124556[107:Res:124554.0,61.1] always3(s32) || -> . % 76.16/76.32 124557[107:SSi:124556.0,78209.0,78213.0,108782.0,124183.0,124547.0] || -> . % 76.16/76.32 124558[107:Spt:124557.0,124552.0,124554.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.32 124559[107:Spt:124557.0,124552.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 124563[107:Res:124559.0,61.1] always3(s33) || -> . % 76.16/76.32 124564[107:SSi:124563.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.32 124565[105:Spt:124564.0,124182.0,124183.0] || until2p7(s32)*+ -> . % 76.16/76.32 124566[105:Spt:124564.0,124182.1] || -> node4(s31)*. % 76.16/76.32 124568[105:MRR:825.0,124566.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.32 124571[105:Res:53.1,124568.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.32 124576[106:Spt:124571.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 124578[106:Res:124576.0,61.1] always3(s31) || -> . % 76.16/76.32 124579[106:SSi:124578.0,78205.0,78208.0,108781.0,124181.0,124566.0] || -> . % 76.16/76.32 124580[106:Spt:124579.0,124571.0,124576.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.32 124581[106:Spt:124579.0,124571.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 124585[106:Res:124581.0,61.1] always3(s32) || -> . % 76.16/76.32 124586[106:SSi:124585.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.32 124587[104:Spt:124586.0,124180.0,124181.0] || until2p7(s31)*+ -> . % 76.16/76.32 124588[104:Spt:124586.0,124180.1] || -> node4(s30)*. % 76.16/76.32 124590[104:MRR:828.0,124588.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.32 124593[104:Res:53.1,124590.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.32 124595[105:Spt:124593.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 124597[105:Res:124595.0,61.1] always3(s30) || -> . % 76.16/76.32 124598[105:SSi:124597.0,78200.0,78204.0,108780.0,124179.0,124588.0] || -> . % 76.16/76.32 124599[105:Spt:124598.0,124593.0,124595.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.32 124600[105:Spt:124598.0,124593.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 124604[105:Res:124600.0,61.1] always3(s31) || -> . % 76.16/76.32 124605[105:SSi:124604.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.32 124606[103:Spt:124605.0,124178.0,124179.0] || until2p7(s30)*+ -> . % 76.16/76.32 124607[103:Spt:124605.0,124178.1] || -> node4(s29)*. % 76.16/76.32 124609[103:MRR:831.0,124607.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.32 124612[103:Res:53.1,124609.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.32 124614[104:Spt:124612.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 124616[104:Res:124614.0,61.1] always3(s29) || -> . % 76.16/76.32 124617[104:SSi:124616.0,78196.0,78199.0,108779.0,124177.0,124607.0] || -> . % 76.16/76.32 124618[104:Spt:124617.0,124612.0,124614.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.32 124619[104:Spt:124617.0,124612.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 124623[104:Res:124619.0,61.1] always3(s30) || -> . % 76.16/76.32 124624[104:SSi:124623.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.32 124625[102:Spt:124624.0,124176.0,124177.0] || until2p7(s29)*+ -> . % 76.16/76.32 124626[102:Spt:124624.0,124176.1] || -> node4(s28)*. % 76.16/76.32 124628[102:MRR:834.0,124626.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.32 124631[102:Res:53.1,124628.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.32 124633[103:Spt:124631.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 124635[103:Res:124633.0,61.1] always3(s28) || -> . % 76.16/76.32 124636[103:SSi:124635.0,78191.0,78195.0,108778.0,124175.0,124626.0] || -> . % 76.16/76.32 124637[103:Spt:124636.0,124631.0,124633.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.32 124638[103:Spt:124636.0,124631.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 124642[103:Res:124638.0,61.1] always3(s29) || -> . % 76.16/76.32 124643[103:SSi:124642.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.32 124644[101:Spt:124643.0,124174.0,124175.0] || until2p7(s28)*+ -> . % 76.16/76.32 124645[101:Spt:124643.0,124174.1] || -> node4(s27)*. % 76.16/76.32 124647[101:MRR:837.0,124645.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.32 124650[101:Res:53.1,124647.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.32 124655[102:Spt:124650.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 124657[102:Res:124655.0,61.1] always3(s27) || -> . % 76.16/76.32 124658[102:SSi:124657.0,78187.0,78190.0,108777.0,124173.0,124645.0] || -> . % 76.16/76.32 124659[102:Spt:124658.0,124650.0,124655.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.32 124660[102:Spt:124658.0,124650.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 124664[102:Res:124660.0,61.1] always3(s28) || -> . % 76.16/76.32 124665[102:SSi:124664.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.32 124666[100:Spt:124665.0,124172.0,124173.0] || until2p7(s27)*+ -> . % 76.16/76.32 124667[100:Spt:124665.0,124172.1] || -> node4(s26)*. % 76.16/76.32 124669[100:MRR:840.0,124667.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.32 124672[100:Res:53.1,124669.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.32 124674[101:Spt:124672.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 124676[101:Res:124674.0,61.1] always3(s26) || -> . % 76.16/76.32 124677[101:SSi:124676.0,78182.0,78186.0,108776.0,124171.0,124667.0] || -> . % 76.16/76.32 124678[101:Spt:124677.0,124672.0,124674.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.32 124679[101:Spt:124677.0,124672.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 124683[101:Res:124679.0,61.1] always3(s27) || -> . % 76.16/76.32 124684[101:SSi:124683.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.32 124685[99:Spt:124684.0,124170.0,124171.0] || until2p7(s26)*+ -> . % 76.16/76.32 124686[99:Spt:124684.0,124170.1] || -> node4(s25)*. % 76.16/76.32 124688[99:MRR:843.0,124686.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.32 124691[99:Res:53.1,124688.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.32 124693[100:Spt:124691.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 124695[100:Res:124693.0,61.1] always3(s25) || -> . % 76.16/76.32 124696[100:SSi:124695.0,78178.0,78181.0,108775.0,124169.0,124686.0] || -> . % 76.16/76.32 124697[100:Spt:124696.0,124691.0,124693.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.32 124698[100:Spt:124696.0,124691.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 124702[100:Res:124698.0,61.1] always3(s26) || -> . % 76.16/76.32 124703[100:SSi:124702.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.32 124704[98:Spt:124703.0,124168.0,124169.0] || until2p7(s25)*+ -> . % 76.16/76.32 124705[98:Spt:124703.0,124168.1] || -> node4(s24)*. % 76.16/76.32 124707[98:MRR:846.0,124705.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.32 124710[98:Res:53.1,124707.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.32 124712[99:Spt:124710.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 124714[99:Res:124712.0,61.1] always3(s24) || -> . % 76.16/76.32 124715[99:SSi:124714.0,78173.0,78177.0,108774.0,124167.0,124705.0] || -> . % 76.16/76.32 124716[99:Spt:124715.0,124710.0,124712.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.32 124717[99:Spt:124715.0,124710.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 124721[99:Res:124717.0,61.1] always3(s25) || -> . % 76.16/76.32 124722[99:SSi:124721.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.32 124723[97:Spt:124722.0,124166.0,124167.0] || until2p7(s24)*+ -> . % 76.16/76.32 124724[97:Spt:124722.0,124166.1] || -> node4(s23)*. % 76.16/76.32 124726[97:MRR:849.0,124724.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.32 124729[97:Res:53.1,124726.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.32 124734[98:Spt:124729.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 124736[98:Res:124734.0,61.1] always3(s23) || -> . % 76.16/76.32 124737[98:SSi:124736.0,78169.0,78172.0,108773.0,124165.0,124724.0] || -> . % 76.16/76.32 124738[98:Spt:124737.0,124729.0,124734.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.32 124739[98:Spt:124737.0,124729.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 124743[98:Res:124739.0,61.1] always3(s24) || -> . % 76.16/76.32 124744[98:SSi:124743.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.32 124745[96:Spt:124744.0,124164.0,124165.0] || until2p7(s23)*+ -> . % 76.16/76.32 124746[96:Spt:124744.0,124164.1] || -> node4(s22)*. % 76.16/76.32 124748[96:MRR:852.0,124746.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.32 124751[96:Res:53.1,124748.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.32 124753[97:Spt:124751.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 124755[97:Res:124753.0,61.1] always3(s22) || -> . % 76.16/76.32 124756[97:SSi:124755.0,78164.0,78168.0,108772.0,124163.0,124746.0] || -> . % 76.16/76.32 124757[97:Spt:124756.0,124751.0,124753.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.32 124758[97:Spt:124756.0,124751.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 124762[97:Res:124758.0,61.1] always3(s23) || -> . % 76.16/76.32 124763[97:SSi:124762.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.32 124764[95:Spt:124763.0,124162.0,124163.0] || until2p7(s22)*+ -> . % 76.16/76.32 124765[95:Spt:124763.0,124162.1] || -> node4(s21)*. % 76.16/76.32 124767[95:MRR:855.0,124765.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.32 124770[95:Res:53.1,124767.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.32 124772[96:Spt:124770.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 124774[96:Res:124772.0,61.1] always3(s21) || -> . % 76.16/76.32 124775[96:SSi:124774.0,78160.0,78163.0,108771.0,124161.0,124765.0] || -> . % 76.16/76.32 124776[96:Spt:124775.0,124770.0,124772.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.32 124777[96:Spt:124775.0,124770.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 124781[96:Res:124777.0,61.1] always3(s22) || -> . % 76.16/76.32 124782[96:SSi:124781.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.32 124783[94:Spt:124782.0,124160.0,124161.0] || until2p7(s21)*+ -> . % 76.16/76.32 124784[94:Spt:124782.0,124160.1] || -> node4(s20)*. % 76.16/76.32 124786[94:MRR:858.0,124784.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.32 124789[94:Res:53.1,124786.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.32 124791[95:Spt:124789.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 124793[95:Res:124791.0,61.1] always3(s20) || -> . % 76.16/76.32 124794[95:SSi:124793.0,78155.0,78159.0,108770.0,124159.0,124784.0] || -> . % 76.16/76.32 124795[95:Spt:124794.0,124789.0,124791.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.32 124796[95:Spt:124794.0,124789.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 124800[95:Res:124796.0,61.1] always3(s21) || -> . % 76.16/76.32 124801[95:SSi:124800.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.32 124802[93:Spt:124801.0,124158.0,124159.0] || until2p7(s20)*+ -> . % 76.16/76.32 124803[93:Spt:124801.0,124158.1] || -> node4(s19)*. % 76.16/76.32 124805[93:MRR:861.0,124803.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.32 124808[93:Res:53.1,124805.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.32 124813[94:Spt:124808.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 124815[94:Res:124813.0,61.1] always3(s19) || -> . % 76.16/76.32 124816[94:SSi:124815.0,78151.0,78154.0,108769.0,124157.0,124803.0] || -> . % 76.16/76.32 124817[94:Spt:124816.0,124808.0,124813.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.32 124818[94:Spt:124816.0,124808.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 124822[94:Res:124818.0,61.1] always3(s20) || -> . % 76.16/76.32 124823[94:SSi:124822.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.32 124824[92:Spt:124823.0,124156.0,124157.0] || until2p7(s19)*+ -> . % 76.16/76.32 124825[92:Spt:124823.0,124156.1] || -> node4(s18)*. % 76.16/76.32 124827[92:MRR:864.0,124825.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.32 124830[92:Res:53.1,124827.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.32 124832[93:Spt:124830.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 124834[93:Res:124832.0,61.1] always3(s18) || -> . % 76.16/76.32 124835[93:SSi:124834.0,78146.0,78150.0,108768.0,124155.0,124825.0] || -> . % 76.16/76.32 124836[93:Spt:124835.0,124830.0,124832.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.32 124837[93:Spt:124835.0,124830.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 124841[93:Res:124837.0,61.1] always3(s19) || -> . % 76.16/76.32 124842[93:SSi:124841.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.32 124843[91:Spt:124842.0,124154.0,124155.0] || until2p7(s18)*+ -> . % 76.16/76.32 124844[91:Spt:124842.0,124154.1] || -> node4(s17)*. % 76.16/76.32 124846[91:MRR:867.0,124844.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.32 124849[91:Res:53.1,124846.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.32 124851[92:Spt:124849.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 124853[92:Res:124851.0,61.1] always3(s17) || -> . % 76.16/76.32 124854[92:SSi:124853.0,78142.0,78145.0,108767.0,124153.0,124844.0] || -> . % 76.16/76.32 124855[92:Spt:124854.0,124849.0,124851.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.32 124856[92:Spt:124854.0,124849.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 124860[92:Res:124856.0,61.1] always3(s18) || -> . % 76.16/76.32 124861[92:SSi:124860.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.32 124862[90:Spt:124861.0,124152.0,124153.0] || until2p7(s17)*+ -> . % 76.16/76.32 124863[90:Spt:124861.0,124152.1] || -> node4(s16)*. % 76.16/76.32 124865[90:MRR:870.0,124863.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.32 124868[90:Res:53.1,124865.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.32 124870[91:Spt:124868.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.32 124872[91:Res:124870.0,61.1] always3(s16) || -> . % 76.16/76.32 124873[91:SSi:124872.0,78137.0,78141.0,108766.0,124151.0,124863.0] || -> . % 76.16/76.32 124874[91:Spt:124873.0,124868.0,124870.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.32 124875[91:Spt:124873.0,124868.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 124879[91:Res:124875.0,61.1] always3(s17) || -> . % 76.16/76.32 124880[91:SSi:124879.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.32 124881[89:Spt:124880.0,124150.0,124151.0] || until2p7(s16)*+ -> . % 76.16/76.32 124882[89:Spt:124880.0,124150.1] || -> node4(s15)*. % 76.16/76.32 124884[89:MRR:873.0,124882.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.32 124887[89:Res:53.1,124884.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.32 124889[89:MRR:124887.0,124140.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.32 124894[89:Res:124889.0,61.1] always3(s16) || -> . % 76.16/76.32 124895[89:SSi:124894.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.32 124896[87:Spt:124895.0,124009.0,124012.0] || trans(s49,s15)*+ -> . % 76.16/76.32 124897[87:Spt:124895.0,124009.1,124009.2,124009.3,124009.4,124009.5,124009.6,124009.7,124009.8,124009.9,124009.10,124009.11,124009.12] || -> trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.32 124899[87:MRR:124011.1,124896.0] xuntil6(s49) || -> trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.32 124900[88:Spt:124897.0] || -> trans(s49,s14)*. % 76.16/76.32 124901[88:Res:124900.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s14)*. % 76.16/76.32 124903[88:Res:124900.0,60.0] || -> node2(s49,s14)*. % 76.16/76.32 124904[88:SSi:124901.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s14)*. % 76.16/76.32 124905[88:Res:124903.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)*. % 76.16/76.32 125021[88:SoR:124905.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)*. % 76.16/76.32 125023[88:SoR:125021.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)* xuntil6(s49). % 76.16/76.32 125024[88:SSi:125023.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s14,c_busy)* xuntil6(s49). % 76.16/76.32 125025[89:Spt:125024.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.32 125027[89:Res:125025.0,61.1] always3(s14) || -> . % 76.16/76.32 125028[89:SSi:125027.0,78128.0,78132.0,108764.0] || -> . % 76.16/76.32 125029[89:Spt:125028.0,125024.1,125025.0] || m_main_v_state(s14,c_busy)*+ -> . % 76.16/76.32 125030[89:Spt:125028.0,125024.0,125024.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.32 125034[89:MRR:125021.2,125029.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.32 125035[89:Res:53.1,125030.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.32 125037[89:MRR:125035.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.32 125038[89:MRR:124904.0,125037.0] || -> until2p7(s14)*. % 76.16/76.32 125039[89:MRR:210.0,125038.0] || -> until2p7(s15)* node4(s14). % 76.16/76.32 125040[90:Spt:125039.0] || -> until2p7(s15)*. % 76.16/76.32 125041[90:MRR:211.0,125040.0] || -> until2p7(s16)* node4(s15). % 76.16/76.32 125042[91:Spt:125041.0] || -> until2p7(s16)*. % 76.16/76.32 125043[91:MRR:212.0,125042.0] || -> until2p7(s17)* node4(s16). % 76.16/76.32 125044[92:Spt:125043.0] || -> until2p7(s17)*. % 76.16/76.32 125045[92:MRR:213.0,125044.0] || -> until2p7(s18)* node4(s17). % 76.16/76.32 125046[93:Spt:125045.0] || -> until2p7(s18)*. % 76.16/76.32 125047[93:MRR:214.0,125046.0] || -> until2p7(s19)* node4(s18). % 76.16/76.32 125048[94:Spt:125047.0] || -> until2p7(s19)*. % 76.16/76.32 125049[94:MRR:215.0,125048.0] || -> until2p7(s20)* node4(s19). % 76.16/76.32 125050[95:Spt:125049.0] || -> until2p7(s20)*. % 76.16/76.32 125051[95:MRR:216.0,125050.0] || -> until2p7(s21)* node4(s20). % 76.16/76.32 125052[96:Spt:125051.0] || -> until2p7(s21)*. % 76.16/76.32 125053[96:MRR:217.0,125052.0] || -> until2p7(s22)* node4(s21). % 76.16/76.32 125054[97:Spt:125053.0] || -> until2p7(s22)*. % 76.16/76.32 125055[97:MRR:218.0,125054.0] || -> until2p7(s23)* node4(s22). % 76.16/76.32 125056[98:Spt:125055.0] || -> until2p7(s23)*. % 76.16/76.32 125057[98:MRR:219.0,125056.0] || -> until2p7(s24)* node4(s23). % 76.16/76.32 125058[99:Spt:125057.0] || -> until2p7(s24)*. % 76.16/76.32 125059[99:MRR:220.0,125058.0] || -> until2p7(s25)* node4(s24). % 76.16/76.32 125060[100:Spt:125059.0] || -> until2p7(s25)*. % 76.16/76.32 125061[100:MRR:221.0,125060.0] || -> until2p7(s26)* node4(s25). % 76.16/76.32 125062[101:Spt:125061.0] || -> until2p7(s26)*. % 76.16/76.32 125063[101:MRR:222.0,125062.0] || -> until2p7(s27)* node4(s26). % 76.16/76.32 125064[102:Spt:125063.0] || -> until2p7(s27)*. % 76.16/76.32 125065[102:MRR:223.0,125064.0] || -> until2p7(s28)* node4(s27). % 76.16/76.32 125066[103:Spt:125065.0] || -> until2p7(s28)*. % 76.16/76.32 125067[103:MRR:224.0,125066.0] || -> until2p7(s29)* node4(s28). % 76.16/76.32 125068[104:Spt:125067.0] || -> until2p7(s29)*. % 76.16/76.32 125069[104:MRR:225.0,125068.0] || -> until2p7(s30)* node4(s29). % 76.16/76.32 125070[105:Spt:125069.0] || -> until2p7(s30)*. % 76.16/76.32 125071[105:MRR:226.0,125070.0] || -> until2p7(s31)* node4(s30). % 76.16/76.32 125072[106:Spt:125071.0] || -> until2p7(s31)*. % 76.16/76.32 125073[106:MRR:227.0,125072.0] || -> until2p7(s32)* node4(s31). % 76.16/76.32 125074[107:Spt:125073.0] || -> until2p7(s32)*. % 76.16/76.32 125075[107:MRR:228.0,125074.0] || -> until2p7(s33)* node4(s32). % 76.16/76.32 125076[108:Spt:125075.0] || -> until2p7(s33)*. % 76.16/76.32 125077[108:MRR:229.0,125076.0] || -> until2p7(s34)* node4(s33). % 76.16/76.32 125078[109:Spt:125077.0] || -> until2p7(s34)*. % 76.16/76.32 125079[109:MRR:230.0,125078.0] || -> until2p7(s35)* node4(s34). % 76.16/76.32 125080[110:Spt:125079.0] || -> until2p7(s35)*. % 76.16/76.32 125081[110:MRR:231.0,125080.0] || -> until2p7(s36)* node4(s35). % 76.16/76.32 125082[111:Spt:125081.0] || -> until2p7(s36)*. % 76.16/76.32 125083[111:MRR:232.0,125082.0] || -> until2p7(s37)* node4(s36). % 76.16/76.32 125084[112:Spt:125083.0] || -> until2p7(s37)*. % 76.16/76.32 125085[112:MRR:235.0,125084.0] || -> until2p7(s38)* node4(s37). % 76.16/76.32 125086[113:Spt:125085.0] || -> until2p7(s38)*. % 76.16/76.32 125087[113:MRR:236.0,125086.0] || -> until2p7(s39)* node4(s38). % 76.16/76.32 125088[114:Spt:125087.0] || -> until2p7(s39)*. % 76.16/76.32 125089[114:MRR:237.0,125088.0] || -> until2p7(s40)* node4(s39). % 76.16/76.32 125090[115:Spt:125089.0] || -> until2p7(s40)*. % 76.16/76.32 125091[115:MRR:238.0,125090.0] || -> until2p7(s41)* node4(s40). % 76.16/76.32 125092[116:Spt:125091.0] || -> until2p7(s41)*. % 76.16/76.32 125093[116:MRR:239.0,125092.0] || -> until2p7(s42)* node4(s41). % 76.16/76.32 125094[117:Spt:125093.0] || -> until2p7(s42)*. % 76.16/76.32 125095[117:MRR:240.0,125094.0] || -> until2p7(s43)* node4(s42). % 76.16/76.32 125096[118:Spt:125095.0] || -> until2p7(s43)*. % 76.16/76.32 125097[118:MRR:241.0,125096.0] || -> until2p7(s44)* node4(s43). % 76.16/76.32 125098[119:Spt:125097.0] || -> until2p7(s44)*. % 76.16/76.32 125099[119:MRR:539.0,125098.0] || -> until2p7(s45)* node4(s44). % 76.16/76.32 125100[120:Spt:125099.0] || -> until2p7(s45)*. % 76.16/76.32 125101[120:MRR:544.0,125100.0] || -> until2p7(s46)* node4(s45). % 76.16/76.32 125102[121:Spt:125101.0] || -> until2p7(s46)*. % 76.16/76.32 125103[121:MRR:549.0,125102.0] || -> until2p7(s47)* node4(s46). % 76.16/76.32 125104[122:Spt:125103.0] || -> until2p7(s47)*. % 76.16/76.32 125105[122:MRR:554.0,125104.0] || -> until2p7(s48)* node4(s47). % 76.16/76.32 125106[123:Spt:125105.0] || -> until2p7(s48)*. % 76.16/76.32 125107[123:MRR:559.0,125106.0] || -> until2p7(s49)* node4(s48). % 76.16/76.32 125108[124:Spt:125107.0] || -> until2p7(s49)*. % 76.16/76.32 125109[124:MRR:194.0,125108.0] || -> node4(s49)*. % 76.16/76.32 125110[124:MRR:125034.0,125109.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.32 125111[124:Res:53.1,125110.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.32 125113[124:MRR:125111.0,78381.0] || -> . % 76.16/76.32 125114[124:Spt:125113.0,125107.0,125108.0] || until2p7(s49)*+ -> . % 76.16/76.32 125115[124:Spt:125113.0,125107.1] || -> node4(s48)*. % 76.16/76.32 125116[124:MRR:78384.0,125115.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.32 125119[124:Res:53.1,125116.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 125122[124:Res:125119.0,61.1] always3(s48) || -> . % 76.16/76.32 125123[124:SSi:125122.0,78281.0,78387.0,108798.0,125106.0,125115.0] || -> . % 76.16/76.32 125124[123:Spt:125123.0,125105.0,125106.0] || until2p7(s48)*+ -> . % 76.16/76.32 125125[123:Spt:125123.0,125105.1] || -> node4(s47)*. % 76.16/76.32 125127[123:MRR:777.0,125125.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.32 125142[123:Res:53.1,125127.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.32 125144[124:Spt:125142.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 125146[124:Res:125144.0,61.1] always3(s47) || -> . % 76.16/76.32 125147[124:SSi:125146.0,78277.0,78280.0,108797.0,125104.0,125125.0] || -> . % 76.16/76.32 125148[124:Spt:125147.0,125142.0,125144.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.32 125149[124:Spt:125147.0,125142.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 125153[124:Res:125149.0,61.1] always3(s48) || -> . % 76.16/76.32 125154[124:SSi:125153.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.32 125155[122:Spt:125154.0,125103.0,125104.0] || until2p7(s47)*+ -> . % 76.16/76.32 125156[122:Spt:125154.0,125103.1] || -> node4(s46)*. % 76.16/76.32 125158[122:MRR:780.0,125156.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.32 125168[122:Res:53.1,125158.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.32 125170[123:Spt:125168.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 125172[123:Res:125170.0,61.1] always3(s46) || -> . % 76.16/76.32 125173[123:SSi:125172.0,78272.0,78276.0,108796.0,125102.0,125156.0] || -> . % 76.16/76.32 125174[123:Spt:125173.0,125168.0,125170.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.32 125175[123:Spt:125173.0,125168.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 125179[123:Res:125175.0,61.1] always3(s47) || -> . % 76.16/76.32 125180[123:SSi:125179.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.32 125181[121:Spt:125180.0,125101.0,125102.0] || until2p7(s46)*+ -> . % 76.16/76.32 125182[121:Spt:125180.0,125101.1] || -> node4(s45)*. % 76.16/76.32 125184[121:MRR:783.0,125182.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.32 125187[121:Res:53.1,125184.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.32 125189[122:Spt:125187.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 125191[122:Res:125189.0,61.1] always3(s45) || -> . % 76.16/76.32 125192[122:SSi:125191.0,78268.0,78271.0,108795.0,125100.0,125182.0] || -> . % 76.16/76.32 125193[122:Spt:125192.0,125187.0,125189.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.32 125194[122:Spt:125192.0,125187.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 125198[122:Res:125194.0,61.1] always3(s46) || -> . % 76.16/76.32 125199[122:SSi:125198.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.32 125200[120:Spt:125199.0,125099.0,125100.0] || until2p7(s45)*+ -> . % 76.16/76.32 125201[120:Spt:125199.0,125099.1] || -> node4(s44)*. % 76.16/76.32 125203[120:MRR:786.0,125201.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.32 125206[120:Res:53.1,125203.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.32 125208[121:Spt:125206.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 125210[121:Res:125208.0,61.1] always3(s44) || -> . % 76.16/76.32 125211[121:SSi:125210.0,78263.0,78267.0,108794.0,125098.0,125201.0] || -> . % 76.16/76.32 125212[121:Spt:125211.0,125206.0,125208.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.32 125213[121:Spt:125211.0,125206.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 125217[121:Res:125213.0,61.1] always3(s45) || -> . % 76.16/76.32 125218[121:SSi:125217.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.32 125219[119:Spt:125218.0,125097.0,125098.0] || until2p7(s44)*+ -> . % 76.16/76.32 125220[119:Spt:125218.0,125097.1] || -> node4(s43)*. % 76.16/76.32 125222[119:MRR:789.0,125220.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.32 125225[119:Res:53.1,125222.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.32 125230[120:Spt:125225.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 125232[120:Res:125230.0,61.1] always3(s43) || -> . % 76.16/76.32 125233[120:SSi:125232.0,78259.0,78262.0,108793.0,125096.0,125220.0] || -> . % 76.16/76.32 125234[120:Spt:125233.0,125225.0,125230.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.32 125235[120:Spt:125233.0,125225.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 125239[120:Res:125235.0,61.1] always3(s44) || -> . % 76.16/76.32 125240[120:SSi:125239.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.32 125241[118:Spt:125240.0,125095.0,125096.0] || until2p7(s43)*+ -> . % 76.16/76.32 125242[118:Spt:125240.0,125095.1] || -> node4(s42)*. % 76.16/76.32 125244[118:MRR:792.0,125242.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.32 125247[118:Res:53.1,125244.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.32 125249[119:Spt:125247.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 125251[119:Res:125249.0,61.1] always3(s42) || -> . % 76.16/76.32 125252[119:SSi:125251.0,78254.0,78258.0,108792.0,125094.0,125242.0] || -> . % 76.16/76.32 125253[119:Spt:125252.0,125247.0,125249.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.32 125254[119:Spt:125252.0,125247.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 125258[119:Res:125254.0,61.1] always3(s43) || -> . % 76.16/76.32 125259[119:SSi:125258.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.32 125260[117:Spt:125259.0,125093.0,125094.0] || until2p7(s42)*+ -> . % 76.16/76.32 125261[117:Spt:125259.0,125093.1] || -> node4(s41)*. % 76.16/76.32 125263[117:MRR:795.0,125261.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.32 125266[117:Res:53.1,125263.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.32 125268[118:Spt:125266.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 125270[118:Res:125268.0,61.1] always3(s41) || -> . % 76.16/76.32 125271[118:SSi:125270.0,78250.0,78253.0,108791.0,125092.0,125261.0] || -> . % 76.16/76.32 125272[118:Spt:125271.0,125266.0,125268.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.32 125273[118:Spt:125271.0,125266.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 125277[118:Res:125273.0,61.1] always3(s42) || -> . % 76.16/76.32 125278[118:SSi:125277.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.32 125279[116:Spt:125278.0,125091.0,125092.0] || until2p7(s41)*+ -> . % 76.16/76.32 125280[116:Spt:125278.0,125091.1] || -> node4(s40)*. % 76.16/76.32 125282[116:MRR:798.0,125280.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.32 125285[116:Res:53.1,125282.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.32 125287[117:Spt:125285.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 125289[117:Res:125287.0,61.1] always3(s40) || -> . % 76.16/76.32 125290[117:SSi:125289.0,78245.0,78249.0,108790.0,125090.0,125280.0] || -> . % 76.16/76.32 125291[117:Spt:125290.0,125285.0,125287.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.32 125292[117:Spt:125290.0,125285.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 125296[117:Res:125292.0,61.1] always3(s41) || -> . % 76.16/76.32 125297[117:SSi:125296.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.32 125298[115:Spt:125297.0,125089.0,125090.0] || until2p7(s40)*+ -> . % 76.16/76.32 125299[115:Spt:125297.0,125089.1] || -> node4(s39)*. % 76.16/76.32 125301[115:MRR:801.0,125299.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.32 125304[115:Res:53.1,125301.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.32 125309[116:Spt:125304.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 125311[116:Res:125309.0,61.1] always3(s39) || -> . % 76.16/76.32 125312[116:SSi:125311.0,78241.0,78244.0,108789.0,125088.0,125299.0] || -> . % 76.16/76.32 125313[116:Spt:125312.0,125304.0,125309.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.32 125314[116:Spt:125312.0,125304.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 125318[116:Res:125314.0,61.1] always3(s40) || -> . % 76.16/76.32 125319[116:SSi:125318.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.32 125320[114:Spt:125319.0,125087.0,125088.0] || until2p7(s39)*+ -> . % 76.16/76.32 125321[114:Spt:125319.0,125087.1] || -> node4(s38)*. % 76.16/76.32 125323[114:MRR:804.0,125321.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.32 125326[114:Res:53.1,125323.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.32 125328[115:Spt:125326.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 125330[115:Res:125328.0,61.1] always3(s38) || -> . % 76.16/76.32 125331[115:SSi:125330.0,78236.0,78240.0,108788.0,125086.0,125321.0] || -> . % 76.16/76.32 125332[115:Spt:125331.0,125326.0,125328.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.32 125333[115:Spt:125331.0,125326.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 125337[115:Res:125333.0,61.1] always3(s39) || -> . % 76.16/76.32 125338[115:SSi:125337.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.32 125339[113:Spt:125338.0,125085.0,125086.0] || until2p7(s38)*+ -> . % 76.16/76.32 125340[113:Spt:125338.0,125085.1] || -> node4(s37)*. % 76.16/76.32 125342[113:MRR:807.0,125340.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.32 125345[113:Res:53.1,125342.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.32 125347[114:Spt:125345.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 125349[114:Res:125347.0,61.1] always3(s37) || -> . % 76.16/76.32 125350[114:SSi:125349.0,78232.0,78235.0,108787.0,125084.0,125340.0] || -> . % 76.16/76.32 125351[114:Spt:125350.0,125345.0,125347.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.32 125352[114:Spt:125350.0,125345.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 125356[114:Res:125352.0,61.1] always3(s38) || -> . % 76.16/76.32 125357[114:SSi:125356.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.32 125358[112:Spt:125357.0,125083.0,125084.0] || until2p7(s37)*+ -> . % 76.16/76.32 125359[112:Spt:125357.0,125083.1] || -> node4(s36)*. % 76.16/76.32 125361[112:MRR:810.0,125359.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.32 125364[112:Res:53.1,125361.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.32 125366[113:Spt:125364.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 125368[113:Res:125366.0,61.1] always3(s36) || -> . % 76.16/76.32 125369[113:SSi:125368.0,78227.0,78231.0,108786.0,125082.0,125359.0] || -> . % 76.16/76.32 125370[113:Spt:125369.0,125364.0,125366.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.32 125371[113:Spt:125369.0,125364.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 125375[113:Res:125371.0,61.1] always3(s37) || -> . % 76.16/76.32 125376[113:SSi:125375.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.32 125377[111:Spt:125376.0,125081.0,125082.0] || until2p7(s36)*+ -> . % 76.16/76.32 125378[111:Spt:125376.0,125081.1] || -> node4(s35)*. % 76.16/76.32 125380[111:MRR:813.0,125378.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.32 125383[111:Res:53.1,125380.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.32 125388[112:Spt:125383.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 125390[112:Res:125388.0,61.1] always3(s35) || -> . % 76.16/76.32 125391[112:SSi:125390.0,78223.0,78226.0,108785.0,125080.0,125378.0] || -> . % 76.16/76.32 125392[112:Spt:125391.0,125383.0,125388.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.32 125393[112:Spt:125391.0,125383.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 125397[112:Res:125393.0,61.1] always3(s36) || -> . % 76.16/76.32 125398[112:SSi:125397.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.32 125399[110:Spt:125398.0,125079.0,125080.0] || until2p7(s35)*+ -> . % 76.16/76.32 125400[110:Spt:125398.0,125079.1] || -> node4(s34)*. % 76.16/76.32 125402[110:MRR:816.0,125400.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.32 125405[110:Res:53.1,125402.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.32 125407[111:Spt:125405.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 125409[111:Res:125407.0,61.1] always3(s34) || -> . % 76.16/76.32 125410[111:SSi:125409.0,78218.0,78222.0,108784.0,125078.0,125400.0] || -> . % 76.16/76.32 125411[111:Spt:125410.0,125405.0,125407.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.32 125412[111:Spt:125410.0,125405.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 125416[111:Res:125412.0,61.1] always3(s35) || -> . % 76.16/76.32 125417[111:SSi:125416.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.32 125418[109:Spt:125417.0,125077.0,125078.0] || until2p7(s34)*+ -> . % 76.16/76.32 125419[109:Spt:125417.0,125077.1] || -> node4(s33)*. % 76.16/76.32 125421[109:MRR:819.0,125419.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.32 125424[109:Res:53.1,125421.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.32 125426[110:Spt:125424.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 125428[110:Res:125426.0,61.1] always3(s33) || -> . % 76.16/76.32 125429[110:SSi:125428.0,78214.0,78217.0,108783.0,125076.0,125419.0] || -> . % 76.16/76.32 125430[110:Spt:125429.0,125424.0,125426.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.32 125431[110:Spt:125429.0,125424.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 125435[110:Res:125431.0,61.1] always3(s34) || -> . % 76.16/76.32 125436[110:SSi:125435.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.32 125437[108:Spt:125436.0,125075.0,125076.0] || until2p7(s33)*+ -> . % 76.16/76.32 125438[108:Spt:125436.0,125075.1] || -> node4(s32)*. % 76.16/76.32 125440[108:MRR:822.0,125438.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.32 125443[108:Res:53.1,125440.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.32 125445[109:Spt:125443.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 125447[109:Res:125445.0,61.1] always3(s32) || -> . % 76.16/76.32 125448[109:SSi:125447.0,78209.0,78213.0,108782.0,125074.0,125438.0] || -> . % 76.16/76.32 125449[109:Spt:125448.0,125443.0,125445.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.32 125450[109:Spt:125448.0,125443.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 125454[109:Res:125450.0,61.1] always3(s33) || -> . % 76.16/76.32 125455[109:SSi:125454.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.32 125456[107:Spt:125455.0,125073.0,125074.0] || until2p7(s32)*+ -> . % 76.16/76.32 125457[107:Spt:125455.0,125073.1] || -> node4(s31)*. % 76.16/76.32 125459[107:MRR:825.0,125457.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.32 125462[107:Res:53.1,125459.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.32 125467[108:Spt:125462.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 125469[108:Res:125467.0,61.1] always3(s31) || -> . % 76.16/76.32 125470[108:SSi:125469.0,78205.0,78208.0,108781.0,125072.0,125457.0] || -> . % 76.16/76.32 125471[108:Spt:125470.0,125462.0,125467.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.32 125472[108:Spt:125470.0,125462.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 125476[108:Res:125472.0,61.1] always3(s32) || -> . % 76.16/76.32 125477[108:SSi:125476.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.32 125478[106:Spt:125477.0,125071.0,125072.0] || until2p7(s31)*+ -> . % 76.16/76.32 125479[106:Spt:125477.0,125071.1] || -> node4(s30)*. % 76.16/76.32 125481[106:MRR:828.0,125479.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.32 125484[106:Res:53.1,125481.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.32 125486[107:Spt:125484.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 125488[107:Res:125486.0,61.1] always3(s30) || -> . % 76.16/76.32 125489[107:SSi:125488.0,78200.0,78204.0,108780.0,125070.0,125479.0] || -> . % 76.16/76.32 125490[107:Spt:125489.0,125484.0,125486.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.32 125491[107:Spt:125489.0,125484.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 125495[107:Res:125491.0,61.1] always3(s31) || -> . % 76.16/76.32 125496[107:SSi:125495.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.32 125497[105:Spt:125496.0,125069.0,125070.0] || until2p7(s30)*+ -> . % 76.16/76.32 125498[105:Spt:125496.0,125069.1] || -> node4(s29)*. % 76.16/76.32 125500[105:MRR:831.0,125498.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.32 125503[105:Res:53.1,125500.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.32 125505[106:Spt:125503.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 125507[106:Res:125505.0,61.1] always3(s29) || -> . % 76.16/76.32 125508[106:SSi:125507.0,78196.0,78199.0,108779.0,125068.0,125498.0] || -> . % 76.16/76.32 125509[106:Spt:125508.0,125503.0,125505.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.32 125510[106:Spt:125508.0,125503.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 125514[106:Res:125510.0,61.1] always3(s30) || -> . % 76.16/76.32 125515[106:SSi:125514.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.32 125516[104:Spt:125515.0,125067.0,125068.0] || until2p7(s29)*+ -> . % 76.16/76.32 125517[104:Spt:125515.0,125067.1] || -> node4(s28)*. % 76.16/76.32 125519[104:MRR:834.0,125517.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.32 125522[104:Res:53.1,125519.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.32 125524[105:Spt:125522.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 125526[105:Res:125524.0,61.1] always3(s28) || -> . % 76.16/76.32 125527[105:SSi:125526.0,78191.0,78195.0,108778.0,125066.0,125517.0] || -> . % 76.16/76.32 125528[105:Spt:125527.0,125522.0,125524.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.32 125529[105:Spt:125527.0,125522.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 125533[105:Res:125529.0,61.1] always3(s29) || -> . % 76.16/76.32 125534[105:SSi:125533.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.32 125535[103:Spt:125534.0,125065.0,125066.0] || until2p7(s28)*+ -> . % 76.16/76.32 125536[103:Spt:125534.0,125065.1] || -> node4(s27)*. % 76.16/76.32 125538[103:MRR:837.0,125536.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.32 125541[103:Res:53.1,125538.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.32 125546[104:Spt:125541.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 125548[104:Res:125546.0,61.1] always3(s27) || -> . % 76.16/76.32 125549[104:SSi:125548.0,78187.0,78190.0,108777.0,125064.0,125536.0] || -> . % 76.16/76.32 125550[104:Spt:125549.0,125541.0,125546.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.32 125551[104:Spt:125549.0,125541.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 125555[104:Res:125551.0,61.1] always3(s28) || -> . % 76.16/76.32 125556[104:SSi:125555.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.32 125557[102:Spt:125556.0,125063.0,125064.0] || until2p7(s27)*+ -> . % 76.16/76.32 125558[102:Spt:125556.0,125063.1] || -> node4(s26)*. % 76.16/76.32 125560[102:MRR:840.0,125558.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.32 125563[102:Res:53.1,125560.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.32 125565[103:Spt:125563.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 125567[103:Res:125565.0,61.1] always3(s26) || -> . % 76.16/76.32 125568[103:SSi:125567.0,78182.0,78186.0,108776.0,125062.0,125558.0] || -> . % 76.16/76.32 125569[103:Spt:125568.0,125563.0,125565.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.32 125570[103:Spt:125568.0,125563.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 125574[103:Res:125570.0,61.1] always3(s27) || -> . % 76.16/76.32 125575[103:SSi:125574.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.32 125576[101:Spt:125575.0,125061.0,125062.0] || until2p7(s26)*+ -> . % 76.16/76.32 125577[101:Spt:125575.0,125061.1] || -> node4(s25)*. % 76.16/76.32 125579[101:MRR:843.0,125577.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.32 125582[101:Res:53.1,125579.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.32 125584[102:Spt:125582.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 125586[102:Res:125584.0,61.1] always3(s25) || -> . % 76.16/76.32 125587[102:SSi:125586.0,78178.0,78181.0,108775.0,125060.0,125577.0] || -> . % 76.16/76.32 125588[102:Spt:125587.0,125582.0,125584.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.32 125589[102:Spt:125587.0,125582.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 125593[102:Res:125589.0,61.1] always3(s26) || -> . % 76.16/76.32 125594[102:SSi:125593.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.32 125595[100:Spt:125594.0,125059.0,125060.0] || until2p7(s25)*+ -> . % 76.16/76.32 125596[100:Spt:125594.0,125059.1] || -> node4(s24)*. % 76.16/76.32 125598[100:MRR:846.0,125596.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.32 125601[100:Res:53.1,125598.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.32 125603[101:Spt:125601.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 125605[101:Res:125603.0,61.1] always3(s24) || -> . % 76.16/76.32 125606[101:SSi:125605.0,78173.0,78177.0,108774.0,125058.0,125596.0] || -> . % 76.16/76.32 125607[101:Spt:125606.0,125601.0,125603.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.32 125608[101:Spt:125606.0,125601.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 125612[101:Res:125608.0,61.1] always3(s25) || -> . % 76.16/76.32 125613[101:SSi:125612.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.32 125614[99:Spt:125613.0,125057.0,125058.0] || until2p7(s24)*+ -> . % 76.16/76.32 125615[99:Spt:125613.0,125057.1] || -> node4(s23)*. % 76.16/76.32 125617[99:MRR:849.0,125615.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.32 125620[99:Res:53.1,125617.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.32 125625[100:Spt:125620.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 125627[100:Res:125625.0,61.1] always3(s23) || -> . % 76.16/76.32 125628[100:SSi:125627.0,78169.0,78172.0,108773.0,125056.0,125615.0] || -> . % 76.16/76.32 125629[100:Spt:125628.0,125620.0,125625.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.32 125630[100:Spt:125628.0,125620.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 125634[100:Res:125630.0,61.1] always3(s24) || -> . % 76.16/76.32 125635[100:SSi:125634.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.32 125636[98:Spt:125635.0,125055.0,125056.0] || until2p7(s23)*+ -> . % 76.16/76.32 125637[98:Spt:125635.0,125055.1] || -> node4(s22)*. % 76.16/76.32 125639[98:MRR:852.0,125637.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.32 125642[98:Res:53.1,125639.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.32 125644[99:Spt:125642.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 125646[99:Res:125644.0,61.1] always3(s22) || -> . % 76.16/76.32 125647[99:SSi:125646.0,78164.0,78168.0,108772.0,125054.0,125637.0] || -> . % 76.16/76.32 125648[99:Spt:125647.0,125642.0,125644.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.32 125649[99:Spt:125647.0,125642.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 125653[99:Res:125649.0,61.1] always3(s23) || -> . % 76.16/76.32 125654[99:SSi:125653.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.32 125655[97:Spt:125654.0,125053.0,125054.0] || until2p7(s22)*+ -> . % 76.16/76.32 125656[97:Spt:125654.0,125053.1] || -> node4(s21)*. % 76.16/76.32 125658[97:MRR:855.0,125656.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.32 125661[97:Res:53.1,125658.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.32 125663[98:Spt:125661.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 125665[98:Res:125663.0,61.1] always3(s21) || -> . % 76.16/76.32 125666[98:SSi:125665.0,78160.0,78163.0,108771.0,125052.0,125656.0] || -> . % 76.16/76.32 125667[98:Spt:125666.0,125661.0,125663.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.32 125668[98:Spt:125666.0,125661.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 125672[98:Res:125668.0,61.1] always3(s22) || -> . % 76.16/76.32 125673[98:SSi:125672.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.32 125674[96:Spt:125673.0,125051.0,125052.0] || until2p7(s21)*+ -> . % 76.16/76.32 125675[96:Spt:125673.0,125051.1] || -> node4(s20)*. % 76.16/76.32 125677[96:MRR:858.0,125675.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.32 125680[96:Res:53.1,125677.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.32 125682[97:Spt:125680.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 125684[97:Res:125682.0,61.1] always3(s20) || -> . % 76.16/76.32 125685[97:SSi:125684.0,78155.0,78159.0,108770.0,125050.0,125675.0] || -> . % 76.16/76.32 125686[97:Spt:125685.0,125680.0,125682.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.32 125687[97:Spt:125685.0,125680.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 125691[97:Res:125687.0,61.1] always3(s21) || -> . % 76.16/76.32 125692[97:SSi:125691.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.32 125693[95:Spt:125692.0,125049.0,125050.0] || until2p7(s20)*+ -> . % 76.16/76.32 125694[95:Spt:125692.0,125049.1] || -> node4(s19)*. % 76.16/76.32 125696[95:MRR:861.0,125694.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.32 125699[95:Res:53.1,125696.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.32 125704[96:Spt:125699.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 125706[96:Res:125704.0,61.1] always3(s19) || -> . % 76.16/76.32 125707[96:SSi:125706.0,78151.0,78154.0,108769.0,125048.0,125694.0] || -> . % 76.16/76.32 125708[96:Spt:125707.0,125699.0,125704.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.32 125709[96:Spt:125707.0,125699.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 125713[96:Res:125709.0,61.1] always3(s20) || -> . % 76.16/76.32 125714[96:SSi:125713.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.32 125715[94:Spt:125714.0,125047.0,125048.0] || until2p7(s19)*+ -> . % 76.16/76.32 125716[94:Spt:125714.0,125047.1] || -> node4(s18)*. % 76.16/76.32 125718[94:MRR:864.0,125716.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.32 125721[94:Res:53.1,125718.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.32 125723[95:Spt:125721.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 125725[95:Res:125723.0,61.1] always3(s18) || -> . % 76.16/76.32 125726[95:SSi:125725.0,78146.0,78150.0,108768.0,125046.0,125716.0] || -> . % 76.16/76.32 125727[95:Spt:125726.0,125721.0,125723.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.32 125728[95:Spt:125726.0,125721.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 125732[95:Res:125728.0,61.1] always3(s19) || -> . % 76.16/76.32 125733[95:SSi:125732.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.32 125734[93:Spt:125733.0,125045.0,125046.0] || until2p7(s18)*+ -> . % 76.16/76.32 125735[93:Spt:125733.0,125045.1] || -> node4(s17)*. % 76.16/76.32 125737[93:MRR:867.0,125735.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.32 125740[93:Res:53.1,125737.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.32 125742[94:Spt:125740.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 125744[94:Res:125742.0,61.1] always3(s17) || -> . % 76.16/76.32 125745[94:SSi:125744.0,78142.0,78145.0,108767.0,125044.0,125735.0] || -> . % 76.16/76.32 125746[94:Spt:125745.0,125740.0,125742.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.32 125747[94:Spt:125745.0,125740.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 125751[94:Res:125747.0,61.1] always3(s18) || -> . % 76.16/76.32 125752[94:SSi:125751.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.32 125753[92:Spt:125752.0,125043.0,125044.0] || until2p7(s17)*+ -> . % 76.16/76.32 125754[92:Spt:125752.0,125043.1] || -> node4(s16)*. % 76.16/76.32 125756[92:MRR:870.0,125754.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.32 125759[92:Res:53.1,125756.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.32 125761[93:Spt:125759.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.32 125763[93:Res:125761.0,61.1] always3(s16) || -> . % 76.16/76.32 125764[93:SSi:125763.0,78137.0,78141.0,108766.0,125042.0,125754.0] || -> . % 76.16/76.32 125765[93:Spt:125764.0,125759.0,125761.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.32 125766[93:Spt:125764.0,125759.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 125770[93:Res:125766.0,61.1] always3(s17) || -> . % 76.16/76.32 125771[93:SSi:125770.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.32 125772[91:Spt:125771.0,125041.0,125042.0] || until2p7(s16)*+ -> . % 76.16/76.32 125773[91:Spt:125771.0,125041.1] || -> node4(s15)*. % 76.16/76.32 125775[91:MRR:873.0,125773.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.32 125778[91:Res:53.1,125775.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.32 125783[92:Spt:125778.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.32 125785[92:Res:125783.0,61.1] always3(s15) || -> . % 76.16/76.32 125786[92:SSi:125785.0,78133.0,78136.0,108765.0,125040.0,125773.0] || -> . % 76.16/76.32 125787[92:Spt:125786.0,125778.0,125783.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.32 125788[92:Spt:125786.0,125778.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.32 125792[92:Res:125788.0,61.1] always3(s16) || -> . % 76.16/76.32 125793[92:SSi:125792.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.32 125794[90:Spt:125793.0,125039.0,125040.0] || until2p7(s15)*+ -> . % 76.16/76.32 125795[90:Spt:125793.0,125039.1] || -> node4(s14)*. % 76.16/76.32 125797[90:MRR:876.0,125795.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.32 125800[90:Res:53.1,125797.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.32 125802[90:MRR:125800.0,125029.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.32 125804[90:Res:125802.0,61.1] always3(s15) || -> . % 76.16/76.32 125805[90:SSi:125804.0,78133.0,78136.0,108765.0] || -> . % 76.16/76.32 125806[88:Spt:125805.0,124897.0,124900.0] || trans(s49,s14)*+ -> . % 76.16/76.32 125807[88:Spt:125805.0,124897.1,124897.2,124897.3,124897.4,124897.5,124897.6,124897.7,124897.8,124897.9,124897.10,124897.11] || -> trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.32 125809[88:MRR:124899.1,125806.0] xuntil6(s49) || -> trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.32 125810[89:Spt:125807.0] || -> trans(s49,s13)*. % 76.16/76.32 125811[89:Res:125810.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s13)*. % 76.16/76.32 125813[89:Res:125810.0,60.0] || -> node2(s49,s13)*. % 76.16/76.32 125814[89:SSi:125811.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s13)*. % 76.16/76.32 125815[89:Res:125813.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)*. % 76.16/76.32 125935[89:SoR:125815.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)*. % 76.16/76.32 125937[89:SoR:125935.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)* xuntil6(s49). % 76.16/76.32 125938[89:SSi:125937.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s13,c_busy)* xuntil6(s49). % 76.16/76.32 125939[90:Spt:125938.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.32 125941[90:Res:125939.0,61.1] always3(s13) || -> . % 76.16/76.32 125942[90:SSi:125941.0,78124.0,78127.0,108763.0] || -> . % 76.16/76.32 125943[90:Spt:125942.0,125938.1,125939.0] || m_main_v_state(s13,c_busy)*+ -> . % 76.16/76.32 125944[90:Spt:125942.0,125938.0,125938.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.32 125948[90:MRR:125935.2,125943.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.32 125949[90:Res:53.1,125944.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.32 125951[90:MRR:125949.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.32 125952[90:MRR:125814.0,125951.0] || -> until2p7(s13)*. % 76.16/76.32 125953[90:MRR:209.0,125952.0] || -> until2p7(s14)* node4(s13). % 76.16/76.32 125954[91:Spt:125953.0] || -> until2p7(s14)*. % 76.16/76.32 125955[91:MRR:210.0,125954.0] || -> until2p7(s15)* node4(s14). % 76.16/76.32 125956[92:Spt:125955.0] || -> until2p7(s15)*. % 76.16/76.32 125957[92:MRR:211.0,125956.0] || -> until2p7(s16)* node4(s15). % 76.16/76.32 125958[93:Spt:125957.0] || -> until2p7(s16)*. % 76.16/76.32 125959[93:MRR:212.0,125958.0] || -> until2p7(s17)* node4(s16). % 76.16/76.32 125960[94:Spt:125959.0] || -> until2p7(s17)*. % 76.16/76.32 125961[94:MRR:213.0,125960.0] || -> until2p7(s18)* node4(s17). % 76.16/76.32 125962[95:Spt:125961.0] || -> until2p7(s18)*. % 76.16/76.32 125963[95:MRR:214.0,125962.0] || -> until2p7(s19)* node4(s18). % 76.16/76.32 125964[96:Spt:125963.0] || -> until2p7(s19)*. % 76.16/76.32 125965[96:MRR:215.0,125964.0] || -> until2p7(s20)* node4(s19). % 76.16/76.32 125966[97:Spt:125965.0] || -> until2p7(s20)*. % 76.16/76.32 125967[97:MRR:216.0,125966.0] || -> until2p7(s21)* node4(s20). % 76.16/76.32 125968[98:Spt:125967.0] || -> until2p7(s21)*. % 76.16/76.32 125969[98:MRR:217.0,125968.0] || -> until2p7(s22)* node4(s21). % 76.16/76.32 125970[99:Spt:125969.0] || -> until2p7(s22)*. % 76.16/76.32 125971[99:MRR:218.0,125970.0] || -> until2p7(s23)* node4(s22). % 76.16/76.32 125972[100:Spt:125971.0] || -> until2p7(s23)*. % 76.16/76.32 125973[100:MRR:219.0,125972.0] || -> until2p7(s24)* node4(s23). % 76.16/76.32 125974[101:Spt:125973.0] || -> until2p7(s24)*. % 76.16/76.32 125975[101:MRR:220.0,125974.0] || -> until2p7(s25)* node4(s24). % 76.16/76.32 125976[102:Spt:125975.0] || -> until2p7(s25)*. % 76.16/76.32 125977[102:MRR:221.0,125976.0] || -> until2p7(s26)* node4(s25). % 76.16/76.32 125978[103:Spt:125977.0] || -> until2p7(s26)*. % 76.16/76.32 125979[103:MRR:222.0,125978.0] || -> until2p7(s27)* node4(s26). % 76.16/76.32 125980[104:Spt:125979.0] || -> until2p7(s27)*. % 76.16/76.32 125981[104:MRR:223.0,125980.0] || -> until2p7(s28)* node4(s27). % 76.16/76.32 125982[105:Spt:125981.0] || -> until2p7(s28)*. % 76.16/76.32 125983[105:MRR:224.0,125982.0] || -> until2p7(s29)* node4(s28). % 76.16/76.32 125984[106:Spt:125983.0] || -> until2p7(s29)*. % 76.16/76.32 125985[106:MRR:225.0,125984.0] || -> until2p7(s30)* node4(s29). % 76.16/76.32 125986[107:Spt:125985.0] || -> until2p7(s30)*. % 76.16/76.32 125987[107:MRR:226.0,125986.0] || -> until2p7(s31)* node4(s30). % 76.16/76.32 125988[108:Spt:125987.0] || -> until2p7(s31)*. % 76.16/76.32 125989[108:MRR:227.0,125988.0] || -> until2p7(s32)* node4(s31). % 76.16/76.32 125990[109:Spt:125989.0] || -> until2p7(s32)*. % 76.16/76.32 125991[109:MRR:228.0,125990.0] || -> until2p7(s33)* node4(s32). % 76.16/76.32 125992[110:Spt:125991.0] || -> until2p7(s33)*. % 76.16/76.32 125993[110:MRR:229.0,125992.0] || -> until2p7(s34)* node4(s33). % 76.16/76.32 125994[111:Spt:125993.0] || -> until2p7(s34)*. % 76.16/76.32 125995[111:MRR:230.0,125994.0] || -> until2p7(s35)* node4(s34). % 76.16/76.32 125996[112:Spt:125995.0] || -> until2p7(s35)*. % 76.16/76.32 125997[112:MRR:231.0,125996.0] || -> until2p7(s36)* node4(s35). % 76.16/76.32 125998[113:Spt:125997.0] || -> until2p7(s36)*. % 76.16/76.32 125999[113:MRR:232.0,125998.0] || -> until2p7(s37)* node4(s36). % 76.16/76.32 126000[114:Spt:125999.0] || -> until2p7(s37)*. % 76.16/76.32 126001[114:MRR:235.0,126000.0] || -> until2p7(s38)* node4(s37). % 76.16/76.32 126002[115:Spt:126001.0] || -> until2p7(s38)*. % 76.16/76.32 126003[115:MRR:236.0,126002.0] || -> until2p7(s39)* node4(s38). % 76.16/76.32 126004[116:Spt:126003.0] || -> until2p7(s39)*. % 76.16/76.32 126005[116:MRR:237.0,126004.0] || -> until2p7(s40)* node4(s39). % 76.16/76.32 126006[117:Spt:126005.0] || -> until2p7(s40)*. % 76.16/76.32 126007[117:MRR:238.0,126006.0] || -> until2p7(s41)* node4(s40). % 76.16/76.32 126008[118:Spt:126007.0] || -> until2p7(s41)*. % 76.16/76.32 126009[118:MRR:239.0,126008.0] || -> until2p7(s42)* node4(s41). % 76.16/76.32 126010[119:Spt:126009.0] || -> until2p7(s42)*. % 76.16/76.32 126011[119:MRR:240.0,126010.0] || -> until2p7(s43)* node4(s42). % 76.16/76.32 126012[120:Spt:126011.0] || -> until2p7(s43)*. % 76.16/76.32 126013[120:MRR:241.0,126012.0] || -> until2p7(s44)* node4(s43). % 76.16/76.32 126014[121:Spt:126013.0] || -> until2p7(s44)*. % 76.16/76.32 126015[121:MRR:539.0,126014.0] || -> until2p7(s45)* node4(s44). % 76.16/76.32 126016[122:Spt:126015.0] || -> until2p7(s45)*. % 76.16/76.32 126017[122:MRR:544.0,126016.0] || -> until2p7(s46)* node4(s45). % 76.16/76.32 126018[123:Spt:126017.0] || -> until2p7(s46)*. % 76.16/76.32 126019[123:MRR:549.0,126018.0] || -> until2p7(s47)* node4(s46). % 76.16/76.32 126020[124:Spt:126019.0] || -> until2p7(s47)*. % 76.16/76.32 126021[124:MRR:554.0,126020.0] || -> until2p7(s48)* node4(s47). % 76.16/76.32 126022[125:Spt:126021.0] || -> until2p7(s48)*. % 76.16/76.32 126023[125:MRR:559.0,126022.0] || -> until2p7(s49)* node4(s48). % 76.16/76.32 126024[126:Spt:126023.0] || -> until2p7(s49)*. % 76.16/76.32 126025[126:MRR:194.0,126024.0] || -> node4(s49)*. % 76.16/76.32 126026[126:MRR:125948.0,126025.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.32 126030[126:Res:53.1,126026.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.32 126032[126:MRR:126030.0,78381.0] || -> . % 76.16/76.32 126033[126:Spt:126032.0,126023.0,126024.0] || until2p7(s49)*+ -> . % 76.16/76.32 126034[126:Spt:126032.0,126023.1] || -> node4(s48)*. % 76.16/76.32 126035[126:MRR:78384.0,126034.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.32 126038[126:Res:53.1,126035.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 126041[126:Res:126038.0,61.1] always3(s48) || -> . % 76.16/76.32 126042[126:SSi:126041.0,78281.0,78387.0,108798.0,126022.0,126034.0] || -> . % 76.16/76.32 126043[125:Spt:126042.0,126021.0,126022.0] || until2p7(s48)*+ -> . % 76.16/76.32 126044[125:Spt:126042.0,126021.1] || -> node4(s47)*. % 76.16/76.32 126046[125:MRR:777.0,126044.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.32 126058[125:Res:53.1,126046.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.32 126060[126:Spt:126058.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 126062[126:Res:126060.0,61.1] always3(s47) || -> . % 76.16/76.32 126063[126:SSi:126062.0,78277.0,78280.0,108797.0,126020.0,126044.0] || -> . % 76.16/76.32 126064[126:Spt:126063.0,126058.0,126060.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.32 126065[126:Spt:126063.0,126058.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 126069[126:Res:126065.0,61.1] always3(s48) || -> . % 76.16/76.32 126070[126:SSi:126069.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.32 126071[124:Spt:126070.0,126019.0,126020.0] || until2p7(s47)*+ -> . % 76.16/76.32 126072[124:Spt:126070.0,126019.1] || -> node4(s46)*. % 76.16/76.32 126074[124:MRR:780.0,126072.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.32 126081[124:Res:53.1,126074.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.32 126086[125:Spt:126081.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 126088[125:Res:126086.0,61.1] always3(s46) || -> . % 76.16/76.32 126089[125:SSi:126088.0,78272.0,78276.0,108796.0,126018.0,126072.0] || -> . % 76.16/76.32 126090[125:Spt:126089.0,126081.0,126086.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.32 126091[125:Spt:126089.0,126081.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 126095[125:Res:126091.0,61.1] always3(s47) || -> . % 76.16/76.32 126096[125:SSi:126095.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.32 126097[123:Spt:126096.0,126017.0,126018.0] || until2p7(s46)*+ -> . % 76.16/76.32 126098[123:Spt:126096.0,126017.1] || -> node4(s45)*. % 76.16/76.32 126100[123:MRR:783.0,126098.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.32 126103[123:Res:53.1,126100.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.32 126105[124:Spt:126103.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 126107[124:Res:126105.0,61.1] always3(s45) || -> . % 76.16/76.32 126108[124:SSi:126107.0,78268.0,78271.0,108795.0,126016.0,126098.0] || -> . % 76.16/76.32 126109[124:Spt:126108.0,126103.0,126105.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.32 126110[124:Spt:126108.0,126103.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 126114[124:Res:126110.0,61.1] always3(s46) || -> . % 76.16/76.32 126115[124:SSi:126114.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.32 126116[122:Spt:126115.0,126015.0,126016.0] || until2p7(s45)*+ -> . % 76.16/76.32 126117[122:Spt:126115.0,126015.1] || -> node4(s44)*. % 76.16/76.32 126119[122:MRR:786.0,126117.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.32 126122[122:Res:53.1,126119.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.32 126124[123:Spt:126122.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 126126[123:Res:126124.0,61.1] always3(s44) || -> . % 76.16/76.32 126127[123:SSi:126126.0,78263.0,78267.0,108794.0,126014.0,126117.0] || -> . % 76.16/76.32 126128[123:Spt:126127.0,126122.0,126124.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.32 126129[123:Spt:126127.0,126122.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 126133[123:Res:126129.0,61.1] always3(s45) || -> . % 76.16/76.32 126134[123:SSi:126133.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.32 126135[121:Spt:126134.0,126013.0,126014.0] || until2p7(s44)*+ -> . % 76.16/76.32 126136[121:Spt:126134.0,126013.1] || -> node4(s43)*. % 76.16/76.32 126138[121:MRR:789.0,126136.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.32 126141[121:Res:53.1,126138.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.32 126143[122:Spt:126141.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 126145[122:Res:126143.0,61.1] always3(s43) || -> . % 76.16/76.32 126146[122:SSi:126145.0,78259.0,78262.0,108793.0,126012.0,126136.0] || -> . % 76.16/76.32 126147[122:Spt:126146.0,126141.0,126143.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.32 126148[122:Spt:126146.0,126141.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 126152[122:Res:126148.0,61.1] always3(s44) || -> . % 76.16/76.32 126153[122:SSi:126152.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.32 126154[120:Spt:126153.0,126011.0,126012.0] || until2p7(s43)*+ -> . % 76.16/76.32 126155[120:Spt:126153.0,126011.1] || -> node4(s42)*. % 76.16/76.32 126157[120:MRR:792.0,126155.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.32 126160[120:Res:53.1,126157.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.32 126165[121:Spt:126160.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 126167[121:Res:126165.0,61.1] always3(s42) || -> . % 76.16/76.32 126168[121:SSi:126167.0,78254.0,78258.0,108792.0,126010.0,126155.0] || -> . % 76.16/76.32 126169[121:Spt:126168.0,126160.0,126165.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.32 126170[121:Spt:126168.0,126160.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 126174[121:Res:126170.0,61.1] always3(s43) || -> . % 76.16/76.32 126175[121:SSi:126174.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.32 126176[119:Spt:126175.0,126009.0,126010.0] || until2p7(s42)*+ -> . % 76.16/76.32 126177[119:Spt:126175.0,126009.1] || -> node4(s41)*. % 76.16/76.32 126179[119:MRR:795.0,126177.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.32 126182[119:Res:53.1,126179.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.32 126184[120:Spt:126182.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 126186[120:Res:126184.0,61.1] always3(s41) || -> . % 76.16/76.32 126187[120:SSi:126186.0,78250.0,78253.0,108791.0,126008.0,126177.0] || -> . % 76.16/76.32 126188[120:Spt:126187.0,126182.0,126184.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.32 126189[120:Spt:126187.0,126182.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 126193[120:Res:126189.0,61.1] always3(s42) || -> . % 76.16/76.32 126194[120:SSi:126193.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.32 126195[118:Spt:126194.0,126007.0,126008.0] || until2p7(s41)*+ -> . % 76.16/76.32 126196[118:Spt:126194.0,126007.1] || -> node4(s40)*. % 76.16/76.32 126198[118:MRR:798.0,126196.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.32 126201[118:Res:53.1,126198.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.32 126203[119:Spt:126201.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 126205[119:Res:126203.0,61.1] always3(s40) || -> . % 76.16/76.32 126206[119:SSi:126205.0,78245.0,78249.0,108790.0,126006.0,126196.0] || -> . % 76.16/76.32 126207[119:Spt:126206.0,126201.0,126203.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.32 126208[119:Spt:126206.0,126201.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 126212[119:Res:126208.0,61.1] always3(s41) || -> . % 76.16/76.32 126213[119:SSi:126212.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.32 126214[117:Spt:126213.0,126005.0,126006.0] || until2p7(s40)*+ -> . % 76.16/76.32 126215[117:Spt:126213.0,126005.1] || -> node4(s39)*. % 76.16/76.32 126217[117:MRR:801.0,126215.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.32 126220[117:Res:53.1,126217.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.32 126222[118:Spt:126220.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 126224[118:Res:126222.0,61.1] always3(s39) || -> . % 76.16/76.32 126225[118:SSi:126224.0,78241.0,78244.0,108789.0,126004.0,126215.0] || -> . % 76.16/76.32 126226[118:Spt:126225.0,126220.0,126222.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.32 126227[118:Spt:126225.0,126220.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 126231[118:Res:126227.0,61.1] always3(s40) || -> . % 76.16/76.32 126232[118:SSi:126231.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.32 126233[116:Spt:126232.0,126003.0,126004.0] || until2p7(s39)*+ -> . % 76.16/76.32 126234[116:Spt:126232.0,126003.1] || -> node4(s38)*. % 76.16/76.32 126236[116:MRR:804.0,126234.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.32 126239[116:Res:53.1,126236.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.32 126244[117:Spt:126239.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 126246[117:Res:126244.0,61.1] always3(s38) || -> . % 76.16/76.32 126247[117:SSi:126246.0,78236.0,78240.0,108788.0,126002.0,126234.0] || -> . % 76.16/76.32 126248[117:Spt:126247.0,126239.0,126244.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.32 126249[117:Spt:126247.0,126239.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 126253[117:Res:126249.0,61.1] always3(s39) || -> . % 76.16/76.32 126254[117:SSi:126253.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.32 126255[115:Spt:126254.0,126001.0,126002.0] || until2p7(s38)*+ -> . % 76.16/76.32 126256[115:Spt:126254.0,126001.1] || -> node4(s37)*. % 76.16/76.32 126258[115:MRR:807.0,126256.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.32 126261[115:Res:53.1,126258.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.32 126263[116:Spt:126261.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 126265[116:Res:126263.0,61.1] always3(s37) || -> . % 76.16/76.32 126266[116:SSi:126265.0,78232.0,78235.0,108787.0,126000.0,126256.0] || -> . % 76.16/76.32 126267[116:Spt:126266.0,126261.0,126263.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.32 126268[116:Spt:126266.0,126261.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 126272[116:Res:126268.0,61.1] always3(s38) || -> . % 76.16/76.32 126273[116:SSi:126272.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.32 126274[114:Spt:126273.0,125999.0,126000.0] || until2p7(s37)*+ -> . % 76.16/76.32 126275[114:Spt:126273.0,125999.1] || -> node4(s36)*. % 76.16/76.32 126277[114:MRR:810.0,126275.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.32 126280[114:Res:53.1,126277.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.32 126282[115:Spt:126280.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 126284[115:Res:126282.0,61.1] always3(s36) || -> . % 76.16/76.32 126285[115:SSi:126284.0,78227.0,78231.0,108786.0,125998.0,126275.0] || -> . % 76.16/76.32 126286[115:Spt:126285.0,126280.0,126282.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.32 126287[115:Spt:126285.0,126280.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 126291[115:Res:126287.0,61.1] always3(s37) || -> . % 76.16/76.32 126292[115:SSi:126291.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.32 126293[113:Spt:126292.0,125997.0,125998.0] || until2p7(s36)*+ -> . % 76.16/76.32 126294[113:Spt:126292.0,125997.1] || -> node4(s35)*. % 76.16/76.32 126296[113:MRR:813.0,126294.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.32 126299[113:Res:53.1,126296.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.32 126301[114:Spt:126299.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 126303[114:Res:126301.0,61.1] always3(s35) || -> . % 76.16/76.32 126304[114:SSi:126303.0,78223.0,78226.0,108785.0,125996.0,126294.0] || -> . % 76.16/76.32 126305[114:Spt:126304.0,126299.0,126301.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.32 126306[114:Spt:126304.0,126299.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 126310[114:Res:126306.0,61.1] always3(s36) || -> . % 76.16/76.32 126311[114:SSi:126310.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.32 126312[112:Spt:126311.0,125995.0,125996.0] || until2p7(s35)*+ -> . % 76.16/76.32 126313[112:Spt:126311.0,125995.1] || -> node4(s34)*. % 76.16/76.32 126315[112:MRR:816.0,126313.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.32 126318[112:Res:53.1,126315.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.32 126323[113:Spt:126318.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 126325[113:Res:126323.0,61.1] always3(s34) || -> . % 76.16/76.32 126326[113:SSi:126325.0,78218.0,78222.0,108784.0,125994.0,126313.0] || -> . % 76.16/76.32 126327[113:Spt:126326.0,126318.0,126323.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.32 126328[113:Spt:126326.0,126318.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 126332[113:Res:126328.0,61.1] always3(s35) || -> . % 76.16/76.32 126333[113:SSi:126332.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.32 126334[111:Spt:126333.0,125993.0,125994.0] || until2p7(s34)*+ -> . % 76.16/76.32 126335[111:Spt:126333.0,125993.1] || -> node4(s33)*. % 76.16/76.32 126337[111:MRR:819.0,126335.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.32 126340[111:Res:53.1,126337.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.32 126342[112:Spt:126340.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 126344[112:Res:126342.0,61.1] always3(s33) || -> . % 76.16/76.32 126345[112:SSi:126344.0,78214.0,78217.0,108783.0,125992.0,126335.0] || -> . % 76.16/76.32 126346[112:Spt:126345.0,126340.0,126342.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.32 126347[112:Spt:126345.0,126340.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 126351[112:Res:126347.0,61.1] always3(s34) || -> . % 76.16/76.32 126352[112:SSi:126351.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.32 126353[110:Spt:126352.0,125991.0,125992.0] || until2p7(s33)*+ -> . % 76.16/76.32 126354[110:Spt:126352.0,125991.1] || -> node4(s32)*. % 76.16/76.32 126356[110:MRR:822.0,126354.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.32 126359[110:Res:53.1,126356.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.32 126361[111:Spt:126359.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 126363[111:Res:126361.0,61.1] always3(s32) || -> . % 76.16/76.32 126364[111:SSi:126363.0,78209.0,78213.0,108782.0,125990.0,126354.0] || -> . % 76.16/76.32 126365[111:Spt:126364.0,126359.0,126361.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.32 126366[111:Spt:126364.0,126359.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 126370[111:Res:126366.0,61.1] always3(s33) || -> . % 76.16/76.32 126371[111:SSi:126370.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.32 126372[109:Spt:126371.0,125989.0,125990.0] || until2p7(s32)*+ -> . % 76.16/76.32 126373[109:Spt:126371.0,125989.1] || -> node4(s31)*. % 76.16/76.32 126375[109:MRR:825.0,126373.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.32 126378[109:Res:53.1,126375.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.32 126380[110:Spt:126378.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 126382[110:Res:126380.0,61.1] always3(s31) || -> . % 76.16/76.32 126383[110:SSi:126382.0,78205.0,78208.0,108781.0,125988.0,126373.0] || -> . % 76.16/76.32 126384[110:Spt:126383.0,126378.0,126380.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.32 126385[110:Spt:126383.0,126378.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 126389[110:Res:126385.0,61.1] always3(s32) || -> . % 76.16/76.32 126390[110:SSi:126389.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.32 126391[108:Spt:126390.0,125987.0,125988.0] || until2p7(s31)*+ -> . % 76.16/76.32 126392[108:Spt:126390.0,125987.1] || -> node4(s30)*. % 76.16/76.32 126394[108:MRR:828.0,126392.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.32 126397[108:Res:53.1,126394.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.32 126402[109:Spt:126397.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 126404[109:Res:126402.0,61.1] always3(s30) || -> . % 76.16/76.32 126405[109:SSi:126404.0,78200.0,78204.0,108780.0,125986.0,126392.0] || -> . % 76.16/76.32 126406[109:Spt:126405.0,126397.0,126402.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.32 126407[109:Spt:126405.0,126397.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 126411[109:Res:126407.0,61.1] always3(s31) || -> . % 76.16/76.32 126412[109:SSi:126411.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.32 126413[107:Spt:126412.0,125985.0,125986.0] || until2p7(s30)*+ -> . % 76.16/76.32 126414[107:Spt:126412.0,125985.1] || -> node4(s29)*. % 76.16/76.32 126416[107:MRR:831.0,126414.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.32 126419[107:Res:53.1,126416.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.32 126421[108:Spt:126419.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 126423[108:Res:126421.0,61.1] always3(s29) || -> . % 76.16/76.32 126424[108:SSi:126423.0,78196.0,78199.0,108779.0,125984.0,126414.0] || -> . % 76.16/76.32 126425[108:Spt:126424.0,126419.0,126421.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.32 126426[108:Spt:126424.0,126419.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 126430[108:Res:126426.0,61.1] always3(s30) || -> . % 76.16/76.32 126431[108:SSi:126430.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.32 126432[106:Spt:126431.0,125983.0,125984.0] || until2p7(s29)*+ -> . % 76.16/76.32 126433[106:Spt:126431.0,125983.1] || -> node4(s28)*. % 76.16/76.32 126435[106:MRR:834.0,126433.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.32 126438[106:Res:53.1,126435.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.32 126440[107:Spt:126438.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 126442[107:Res:126440.0,61.1] always3(s28) || -> . % 76.16/76.32 126443[107:SSi:126442.0,78191.0,78195.0,108778.0,125982.0,126433.0] || -> . % 76.16/76.32 126444[107:Spt:126443.0,126438.0,126440.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.32 126445[107:Spt:126443.0,126438.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 126449[107:Res:126445.0,61.1] always3(s29) || -> . % 76.16/76.32 126450[107:SSi:126449.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.32 126451[105:Spt:126450.0,125981.0,125982.0] || until2p7(s28)*+ -> . % 76.16/76.32 126452[105:Spt:126450.0,125981.1] || -> node4(s27)*. % 76.16/76.32 126454[105:MRR:837.0,126452.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.32 126457[105:Res:53.1,126454.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.32 126459[106:Spt:126457.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 126461[106:Res:126459.0,61.1] always3(s27) || -> . % 76.16/76.32 126462[106:SSi:126461.0,78187.0,78190.0,108777.0,125980.0,126452.0] || -> . % 76.16/76.32 126463[106:Spt:126462.0,126457.0,126459.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.32 126464[106:Spt:126462.0,126457.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 126468[106:Res:126464.0,61.1] always3(s28) || -> . % 76.16/76.32 126469[106:SSi:126468.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.32 126470[104:Spt:126469.0,125979.0,125980.0] || until2p7(s27)*+ -> . % 76.16/76.32 126471[104:Spt:126469.0,125979.1] || -> node4(s26)*. % 76.16/76.32 126473[104:MRR:840.0,126471.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.32 126476[104:Res:53.1,126473.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.32 126481[105:Spt:126476.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 126483[105:Res:126481.0,61.1] always3(s26) || -> . % 76.16/76.32 126484[105:SSi:126483.0,78182.0,78186.0,108776.0,125978.0,126471.0] || -> . % 76.16/76.32 126485[105:Spt:126484.0,126476.0,126481.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.32 126486[105:Spt:126484.0,126476.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 126490[105:Res:126486.0,61.1] always3(s27) || -> . % 76.16/76.32 126491[105:SSi:126490.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.32 126492[103:Spt:126491.0,125977.0,125978.0] || until2p7(s26)*+ -> . % 76.16/76.32 126493[103:Spt:126491.0,125977.1] || -> node4(s25)*. % 76.16/76.32 126495[103:MRR:843.0,126493.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.32 126498[103:Res:53.1,126495.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.32 126500[104:Spt:126498.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 126502[104:Res:126500.0,61.1] always3(s25) || -> . % 76.16/76.32 126503[104:SSi:126502.0,78178.0,78181.0,108775.0,125976.0,126493.0] || -> . % 76.16/76.32 126504[104:Spt:126503.0,126498.0,126500.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.32 126505[104:Spt:126503.0,126498.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 126509[104:Res:126505.0,61.1] always3(s26) || -> . % 76.16/76.32 126510[104:SSi:126509.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.32 126511[102:Spt:126510.0,125975.0,125976.0] || until2p7(s25)*+ -> . % 76.16/76.32 126512[102:Spt:126510.0,125975.1] || -> node4(s24)*. % 76.16/76.32 126514[102:MRR:846.0,126512.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.32 126517[102:Res:53.1,126514.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.32 126519[103:Spt:126517.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 126521[103:Res:126519.0,61.1] always3(s24) || -> . % 76.16/76.32 126522[103:SSi:126521.0,78173.0,78177.0,108774.0,125974.0,126512.0] || -> . % 76.16/76.32 126523[103:Spt:126522.0,126517.0,126519.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.32 126524[103:Spt:126522.0,126517.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 126528[103:Res:126524.0,61.1] always3(s25) || -> . % 76.16/76.32 126529[103:SSi:126528.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.32 126530[101:Spt:126529.0,125973.0,125974.0] || until2p7(s24)*+ -> . % 76.16/76.32 126531[101:Spt:126529.0,125973.1] || -> node4(s23)*. % 76.16/76.32 126533[101:MRR:849.0,126531.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.32 126536[101:Res:53.1,126533.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.32 126538[102:Spt:126536.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 126540[102:Res:126538.0,61.1] always3(s23) || -> . % 76.16/76.32 126541[102:SSi:126540.0,78169.0,78172.0,108773.0,125972.0,126531.0] || -> . % 76.16/76.32 126542[102:Spt:126541.0,126536.0,126538.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.32 126543[102:Spt:126541.0,126536.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 126547[102:Res:126543.0,61.1] always3(s24) || -> . % 76.16/76.32 126548[102:SSi:126547.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.32 126549[100:Spt:126548.0,125971.0,125972.0] || until2p7(s23)*+ -> . % 76.16/76.32 126550[100:Spt:126548.0,125971.1] || -> node4(s22)*. % 76.16/76.32 126552[100:MRR:852.0,126550.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.32 126555[100:Res:53.1,126552.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.32 126560[101:Spt:126555.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 126562[101:Res:126560.0,61.1] always3(s22) || -> . % 76.16/76.32 126563[101:SSi:126562.0,78164.0,78168.0,108772.0,125970.0,126550.0] || -> . % 76.16/76.32 126564[101:Spt:126563.0,126555.0,126560.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.32 126565[101:Spt:126563.0,126555.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 126569[101:Res:126565.0,61.1] always3(s23) || -> . % 76.16/76.32 126570[101:SSi:126569.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.32 126571[99:Spt:126570.0,125969.0,125970.0] || until2p7(s22)*+ -> . % 76.16/76.32 126572[99:Spt:126570.0,125969.1] || -> node4(s21)*. % 76.16/76.32 126574[99:MRR:855.0,126572.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.32 126577[99:Res:53.1,126574.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.32 126579[100:Spt:126577.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 126581[100:Res:126579.0,61.1] always3(s21) || -> . % 76.16/76.32 126582[100:SSi:126581.0,78160.0,78163.0,108771.0,125968.0,126572.0] || -> . % 76.16/76.32 126583[100:Spt:126582.0,126577.0,126579.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.32 126584[100:Spt:126582.0,126577.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 126588[100:Res:126584.0,61.1] always3(s22) || -> . % 76.16/76.32 126589[100:SSi:126588.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.32 126590[98:Spt:126589.0,125967.0,125968.0] || until2p7(s21)*+ -> . % 76.16/76.32 126591[98:Spt:126589.0,125967.1] || -> node4(s20)*. % 76.16/76.32 126593[98:MRR:858.0,126591.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.32 126596[98:Res:53.1,126593.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.32 126598[99:Spt:126596.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 126600[99:Res:126598.0,61.1] always3(s20) || -> . % 76.16/76.32 126601[99:SSi:126600.0,78155.0,78159.0,108770.0,125966.0,126591.0] || -> . % 76.16/76.32 126602[99:Spt:126601.0,126596.0,126598.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.32 126603[99:Spt:126601.0,126596.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 126607[99:Res:126603.0,61.1] always3(s21) || -> . % 76.16/76.32 126608[99:SSi:126607.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.32 126609[97:Spt:126608.0,125965.0,125966.0] || until2p7(s20)*+ -> . % 76.16/76.32 126610[97:Spt:126608.0,125965.1] || -> node4(s19)*. % 76.16/76.32 126612[97:MRR:861.0,126610.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.32 126615[97:Res:53.1,126612.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.32 126617[98:Spt:126615.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 126619[98:Res:126617.0,61.1] always3(s19) || -> . % 76.16/76.32 126620[98:SSi:126619.0,78151.0,78154.0,108769.0,125964.0,126610.0] || -> . % 76.16/76.32 126621[98:Spt:126620.0,126615.0,126617.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.32 126622[98:Spt:126620.0,126615.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 126626[98:Res:126622.0,61.1] always3(s20) || -> . % 76.16/76.32 126627[98:SSi:126626.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.32 126628[96:Spt:126627.0,125963.0,125964.0] || until2p7(s19)*+ -> . % 76.16/76.32 126629[96:Spt:126627.0,125963.1] || -> node4(s18)*. % 76.16/76.32 126631[96:MRR:864.0,126629.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.32 126634[96:Res:53.1,126631.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.32 126639[97:Spt:126634.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 126641[97:Res:126639.0,61.1] always3(s18) || -> . % 76.16/76.32 126642[97:SSi:126641.0,78146.0,78150.0,108768.0,125962.0,126629.0] || -> . % 76.16/76.32 126643[97:Spt:126642.0,126634.0,126639.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.32 126644[97:Spt:126642.0,126634.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 126648[97:Res:126644.0,61.1] always3(s19) || -> . % 76.16/76.32 126649[97:SSi:126648.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.32 126650[95:Spt:126649.0,125961.0,125962.0] || until2p7(s18)*+ -> . % 76.16/76.32 126651[95:Spt:126649.0,125961.1] || -> node4(s17)*. % 76.16/76.32 126653[95:MRR:867.0,126651.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.32 126656[95:Res:53.1,126653.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.32 126658[96:Spt:126656.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 126660[96:Res:126658.0,61.1] always3(s17) || -> . % 76.16/76.32 126661[96:SSi:126660.0,78142.0,78145.0,108767.0,125960.0,126651.0] || -> . % 76.16/76.32 126662[96:Spt:126661.0,126656.0,126658.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.32 126663[96:Spt:126661.0,126656.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 126667[96:Res:126663.0,61.1] always3(s18) || -> . % 76.16/76.32 126668[96:SSi:126667.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.32 126669[94:Spt:126668.0,125959.0,125960.0] || until2p7(s17)*+ -> . % 76.16/76.32 126670[94:Spt:126668.0,125959.1] || -> node4(s16)*. % 76.16/76.32 126672[94:MRR:870.0,126670.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.32 126675[94:Res:53.1,126672.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.32 126677[95:Spt:126675.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.32 126679[95:Res:126677.0,61.1] always3(s16) || -> . % 76.16/76.32 126680[95:SSi:126679.0,78137.0,78141.0,108766.0,125958.0,126670.0] || -> . % 76.16/76.32 126681[95:Spt:126680.0,126675.0,126677.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.32 126682[95:Spt:126680.0,126675.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 126686[95:Res:126682.0,61.1] always3(s17) || -> . % 76.16/76.32 126687[95:SSi:126686.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.32 126688[93:Spt:126687.0,125957.0,125958.0] || until2p7(s16)*+ -> . % 76.16/76.32 126689[93:Spt:126687.0,125957.1] || -> node4(s15)*. % 76.16/76.32 126691[93:MRR:873.0,126689.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.32 126694[93:Res:53.1,126691.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.32 126696[94:Spt:126694.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.32 126698[94:Res:126696.0,61.1] always3(s15) || -> . % 76.16/76.32 126699[94:SSi:126698.0,78133.0,78136.0,108765.0,125956.0,126689.0] || -> . % 76.16/76.32 126700[94:Spt:126699.0,126694.0,126696.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.32 126701[94:Spt:126699.0,126694.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.32 126705[94:Res:126701.0,61.1] always3(s16) || -> . % 76.16/76.32 126706[94:SSi:126705.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.32 126707[92:Spt:126706.0,125955.0,125956.0] || until2p7(s15)*+ -> . % 76.16/76.32 126708[92:Spt:126706.0,125955.1] || -> node4(s14)*. % 76.16/76.32 126710[92:MRR:876.0,126708.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.32 126713[92:Res:53.1,126710.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.32 126718[93:Spt:126713.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.32 126720[93:Res:126718.0,61.1] always3(s14) || -> . % 76.16/76.32 126721[93:SSi:126720.0,78128.0,78132.0,108764.0,125954.0,126708.0] || -> . % 76.16/76.32 126722[93:Spt:126721.0,126713.0,126718.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.32 126723[93:Spt:126721.0,126713.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.32 126727[93:Res:126723.0,61.1] always3(s15) || -> . % 76.16/76.32 126728[93:SSi:126727.0,78133.0,78136.0,108765.0] || -> . % 76.16/76.32 126729[91:Spt:126728.0,125953.0,125954.0] || until2p7(s14)*+ -> . % 76.16/76.32 126730[91:Spt:126728.0,125953.1] || -> node4(s13)*. % 76.16/76.32 126732[91:MRR:879.0,126730.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.32 126735[91:Res:53.1,126732.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.32 126737[91:MRR:126735.0,125943.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.32 126739[91:Res:126737.0,61.1] always3(s14) || -> . % 76.16/76.32 126740[91:SSi:126739.0,78128.0,78132.0,108764.0] || -> . % 76.16/76.32 126741[89:Spt:126740.0,125807.0,125810.0] || trans(s49,s13)*+ -> . % 76.16/76.32 126742[89:Spt:126740.0,125807.1,125807.2,125807.3,125807.4,125807.5,125807.6,125807.7,125807.8,125807.9,125807.10] || -> trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.32 126744[89:MRR:125809.1,126741.0] xuntil6(s49) || -> trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.32 126745[90:Spt:126742.0] || -> trans(s49,s12)*. % 76.16/76.32 126746[90:Res:126745.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s12)*. % 76.16/76.32 126748[90:Res:126745.0,60.0] || -> node2(s49,s12)*. % 76.16/76.32 126749[90:SSi:126746.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s12)*. % 76.16/76.32 126750[90:Res:126748.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)*. % 76.16/76.32 126874[90:SoR:126750.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)*. % 76.16/76.32 126876[90:SoR:126874.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)* xuntil6(s49). % 76.16/76.32 126877[90:SSi:126876.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s12,c_busy)* xuntil6(s49). % 76.16/76.32 126878[91:Spt:126877.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.32 126880[91:Res:126878.0,61.1] always3(s12) || -> . % 76.16/76.32 126881[91:SSi:126880.0,78119.0,78123.0,108762.0] || -> . % 76.16/76.32 126882[91:Spt:126881.0,126877.1,126878.0] || m_main_v_state(s12,c_busy)*+ -> . % 76.16/76.32 126883[91:Spt:126881.0,126877.0,126877.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.32 126887[91:MRR:126874.2,126882.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.32 126888[91:Res:53.1,126883.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.32 126890[91:MRR:126888.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.32 126891[91:MRR:126749.0,126890.0] || -> until2p7(s12)*. % 76.16/76.32 126892[91:MRR:208.0,126891.0] || -> until2p7(s13)* node4(s12). % 76.16/76.32 126893[92:Spt:126892.0] || -> until2p7(s13)*. % 76.16/76.32 126894[92:MRR:209.0,126893.0] || -> until2p7(s14)* node4(s13). % 76.16/76.32 126895[93:Spt:126894.0] || -> until2p7(s14)*. % 76.16/76.32 126896[93:MRR:210.0,126895.0] || -> until2p7(s15)* node4(s14). % 76.16/76.32 126897[94:Spt:126896.0] || -> until2p7(s15)*. % 76.16/76.32 126898[94:MRR:211.0,126897.0] || -> until2p7(s16)* node4(s15). % 76.16/76.32 126899[95:Spt:126898.0] || -> until2p7(s16)*. % 76.16/76.32 126900[95:MRR:212.0,126899.0] || -> until2p7(s17)* node4(s16). % 76.16/76.32 126901[96:Spt:126900.0] || -> until2p7(s17)*. % 76.16/76.32 126902[96:MRR:213.0,126901.0] || -> until2p7(s18)* node4(s17). % 76.16/76.32 126903[97:Spt:126902.0] || -> until2p7(s18)*. % 76.16/76.32 126904[97:MRR:214.0,126903.0] || -> until2p7(s19)* node4(s18). % 76.16/76.32 126905[98:Spt:126904.0] || -> until2p7(s19)*. % 76.16/76.32 126906[98:MRR:215.0,126905.0] || -> until2p7(s20)* node4(s19). % 76.16/76.32 126907[99:Spt:126906.0] || -> until2p7(s20)*. % 76.16/76.32 126908[99:MRR:216.0,126907.0] || -> until2p7(s21)* node4(s20). % 76.16/76.32 126909[100:Spt:126908.0] || -> until2p7(s21)*. % 76.16/76.32 126910[100:MRR:217.0,126909.0] || -> until2p7(s22)* node4(s21). % 76.16/76.32 126911[101:Spt:126910.0] || -> until2p7(s22)*. % 76.16/76.32 126912[101:MRR:218.0,126911.0] || -> until2p7(s23)* node4(s22). % 76.16/76.32 126913[102:Spt:126912.0] || -> until2p7(s23)*. % 76.16/76.32 126914[102:MRR:219.0,126913.0] || -> until2p7(s24)* node4(s23). % 76.16/76.32 126915[103:Spt:126914.0] || -> until2p7(s24)*. % 76.16/76.32 126916[103:MRR:220.0,126915.0] || -> until2p7(s25)* node4(s24). % 76.16/76.32 126917[104:Spt:126916.0] || -> until2p7(s25)*. % 76.16/76.32 126918[104:MRR:221.0,126917.0] || -> until2p7(s26)* node4(s25). % 76.16/76.32 126919[105:Spt:126918.0] || -> until2p7(s26)*. % 76.16/76.32 126920[105:MRR:222.0,126919.0] || -> until2p7(s27)* node4(s26). % 76.16/76.32 126921[106:Spt:126920.0] || -> until2p7(s27)*. % 76.16/76.32 126922[106:MRR:223.0,126921.0] || -> until2p7(s28)* node4(s27). % 76.16/76.32 126923[107:Spt:126922.0] || -> until2p7(s28)*. % 76.16/76.32 126924[107:MRR:224.0,126923.0] || -> until2p7(s29)* node4(s28). % 76.16/76.32 126925[108:Spt:126924.0] || -> until2p7(s29)*. % 76.16/76.32 126926[108:MRR:225.0,126925.0] || -> until2p7(s30)* node4(s29). % 76.16/76.32 126927[109:Spt:126926.0] || -> until2p7(s30)*. % 76.16/76.32 126928[109:MRR:226.0,126927.0] || -> until2p7(s31)* node4(s30). % 76.16/76.32 126929[110:Spt:126928.0] || -> until2p7(s31)*. % 76.16/76.32 126930[110:MRR:227.0,126929.0] || -> until2p7(s32)* node4(s31). % 76.16/76.32 126931[111:Spt:126930.0] || -> until2p7(s32)*. % 76.16/76.32 126932[111:MRR:228.0,126931.0] || -> until2p7(s33)* node4(s32). % 76.16/76.32 126933[112:Spt:126932.0] || -> until2p7(s33)*. % 76.16/76.32 126934[112:MRR:229.0,126933.0] || -> until2p7(s34)* node4(s33). % 76.16/76.32 126935[113:Spt:126934.0] || -> until2p7(s34)*. % 76.16/76.32 126936[113:MRR:230.0,126935.0] || -> until2p7(s35)* node4(s34). % 76.16/76.32 126937[114:Spt:126936.0] || -> until2p7(s35)*. % 76.16/76.32 126938[114:MRR:231.0,126937.0] || -> until2p7(s36)* node4(s35). % 76.16/76.32 126939[115:Spt:126938.0] || -> until2p7(s36)*. % 76.16/76.32 126940[115:MRR:232.0,126939.0] || -> until2p7(s37)* node4(s36). % 76.16/76.32 126941[116:Spt:126940.0] || -> until2p7(s37)*. % 76.16/76.32 126942[116:MRR:235.0,126941.0] || -> until2p7(s38)* node4(s37). % 76.16/76.32 126943[117:Spt:126942.0] || -> until2p7(s38)*. % 76.16/76.32 126944[117:MRR:236.0,126943.0] || -> until2p7(s39)* node4(s38). % 76.16/76.32 126945[118:Spt:126944.0] || -> until2p7(s39)*. % 76.16/76.32 126946[118:MRR:237.0,126945.0] || -> until2p7(s40)* node4(s39). % 76.16/76.32 126947[119:Spt:126946.0] || -> until2p7(s40)*. % 76.16/76.32 126948[119:MRR:238.0,126947.0] || -> until2p7(s41)* node4(s40). % 76.16/76.32 126949[120:Spt:126948.0] || -> until2p7(s41)*. % 76.16/76.32 126950[120:MRR:239.0,126949.0] || -> until2p7(s42)* node4(s41). % 76.16/76.32 126951[121:Spt:126950.0] || -> until2p7(s42)*. % 76.16/76.32 126952[121:MRR:240.0,126951.0] || -> until2p7(s43)* node4(s42). % 76.16/76.32 126953[122:Spt:126952.0] || -> until2p7(s43)*. % 76.16/76.32 126954[122:MRR:241.0,126953.0] || -> until2p7(s44)* node4(s43). % 76.16/76.32 126955[123:Spt:126954.0] || -> until2p7(s44)*. % 76.16/76.32 126956[123:MRR:539.0,126955.0] || -> until2p7(s45)* node4(s44). % 76.16/76.32 126957[124:Spt:126956.0] || -> until2p7(s45)*. % 76.16/76.32 126958[124:MRR:544.0,126957.0] || -> until2p7(s46)* node4(s45). % 76.16/76.32 126959[125:Spt:126958.0] || -> until2p7(s46)*. % 76.16/76.32 126960[125:MRR:549.0,126959.0] || -> until2p7(s47)* node4(s46). % 76.16/76.32 126961[126:Spt:126960.0] || -> until2p7(s47)*. % 76.16/76.32 126962[126:MRR:554.0,126961.0] || -> until2p7(s48)* node4(s47). % 76.16/76.32 126963[127:Spt:126962.0] || -> until2p7(s48)*. % 76.16/76.32 126964[127:MRR:559.0,126963.0] || -> until2p7(s49)* node4(s48). % 76.16/76.32 126965[128:Spt:126964.0] || -> until2p7(s49)*. % 76.16/76.32 126966[128:MRR:194.0,126965.0] || -> node4(s49)*. % 76.16/76.32 126967[128:MRR:126887.0,126966.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.32 126968[128:Res:53.1,126967.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.32 126970[128:MRR:126968.0,78381.0] || -> . % 76.16/76.32 126971[128:Spt:126970.0,126964.0,126965.0] || until2p7(s49)*+ -> . % 76.16/76.32 126972[128:Spt:126970.0,126964.1] || -> node4(s48)*. % 76.16/76.32 126973[128:MRR:78384.0,126972.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.32 126976[128:Res:53.1,126973.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 126979[128:Res:126976.0,61.1] always3(s48) || -> . % 76.16/76.32 126980[128:SSi:126979.0,78281.0,78387.0,108798.0,126963.0,126972.0] || -> . % 76.16/76.32 126981[127:Spt:126980.0,126962.0,126963.0] || until2p7(s48)*+ -> . % 76.16/76.32 126982[127:Spt:126980.0,126962.1] || -> node4(s47)*. % 76.16/76.32 126984[127:MRR:777.0,126982.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.32 126999[127:Res:53.1,126984.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.32 127004[128:Spt:126999.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 127006[128:Res:127004.0,61.1] always3(s47) || -> . % 76.16/76.32 127007[128:SSi:127006.0,78277.0,78280.0,108797.0,126961.0,126982.0] || -> . % 76.16/76.32 127008[128:Spt:127007.0,126999.0,127004.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.32 127009[128:Spt:127007.0,126999.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 127013[128:Res:127009.0,61.1] always3(s48) || -> . % 76.16/76.32 127014[128:SSi:127013.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.32 127015[126:Spt:127014.0,126960.0,126961.0] || until2p7(s47)*+ -> . % 76.16/76.32 127016[126:Spt:127014.0,126960.1] || -> node4(s46)*. % 76.16/76.32 127018[126:MRR:780.0,127016.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.32 127025[126:Res:53.1,127018.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.32 127027[127:Spt:127025.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 127029[127:Res:127027.0,61.1] always3(s46) || -> . % 76.16/76.32 127030[127:SSi:127029.0,78272.0,78276.0,108796.0,126959.0,127016.0] || -> . % 76.16/76.32 127031[127:Spt:127030.0,127025.0,127027.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.32 127032[127:Spt:127030.0,127025.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 127036[127:Res:127032.0,61.1] always3(s47) || -> . % 76.16/76.32 127037[127:SSi:127036.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.32 127038[125:Spt:127037.0,126958.0,126959.0] || until2p7(s46)*+ -> . % 76.16/76.32 127039[125:Spt:127037.0,126958.1] || -> node4(s45)*. % 76.16/76.32 127041[125:MRR:783.0,127039.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.32 127044[125:Res:53.1,127041.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.32 127049[126:Spt:127044.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 127051[126:Res:127049.0,61.1] always3(s45) || -> . % 76.16/76.32 127052[126:SSi:127051.0,78268.0,78271.0,108795.0,126957.0,127039.0] || -> . % 76.16/76.32 127053[126:Spt:127052.0,127044.0,127049.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.32 127054[126:Spt:127052.0,127044.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 127058[126:Res:127054.0,61.1] always3(s46) || -> . % 76.16/76.32 127059[126:SSi:127058.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.32 127060[124:Spt:127059.0,126956.0,126957.0] || until2p7(s45)*+ -> . % 76.16/76.32 127061[124:Spt:127059.0,126956.1] || -> node4(s44)*. % 76.16/76.32 127063[124:MRR:786.0,127061.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.32 127066[124:Res:53.1,127063.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.32 127068[125:Spt:127066.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 127070[125:Res:127068.0,61.1] always3(s44) || -> . % 76.16/76.32 127071[125:SSi:127070.0,78263.0,78267.0,108794.0,126955.0,127061.0] || -> . % 76.16/76.32 127072[125:Spt:127071.0,127066.0,127068.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.32 127073[125:Spt:127071.0,127066.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 127077[125:Res:127073.0,61.1] always3(s45) || -> . % 76.16/76.32 127078[125:SSi:127077.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.32 127079[123:Spt:127078.0,126954.0,126955.0] || until2p7(s44)*+ -> . % 76.16/76.32 127080[123:Spt:127078.0,126954.1] || -> node4(s43)*. % 76.16/76.32 127082[123:MRR:789.0,127080.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.32 127085[123:Res:53.1,127082.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.32 127087[124:Spt:127085.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 127089[124:Res:127087.0,61.1] always3(s43) || -> . % 76.16/76.32 127090[124:SSi:127089.0,78259.0,78262.0,108793.0,126953.0,127080.0] || -> . % 76.16/76.32 127091[124:Spt:127090.0,127085.0,127087.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.32 127092[124:Spt:127090.0,127085.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 127096[124:Res:127092.0,61.1] always3(s44) || -> . % 76.16/76.32 127097[124:SSi:127096.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.32 127098[122:Spt:127097.0,126952.0,126953.0] || until2p7(s43)*+ -> . % 76.16/76.32 127099[122:Spt:127097.0,126952.1] || -> node4(s42)*. % 76.16/76.32 127101[122:MRR:792.0,127099.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.32 127104[122:Res:53.1,127101.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.32 127106[123:Spt:127104.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 127108[123:Res:127106.0,61.1] always3(s42) || -> . % 76.16/76.32 127109[123:SSi:127108.0,78254.0,78258.0,108792.0,126951.0,127099.0] || -> . % 76.16/76.32 127110[123:Spt:127109.0,127104.0,127106.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.32 127111[123:Spt:127109.0,127104.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 127115[123:Res:127111.0,61.1] always3(s43) || -> . % 76.16/76.32 127116[123:SSi:127115.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.32 127117[121:Spt:127116.0,126950.0,126951.0] || until2p7(s42)*+ -> . % 76.16/76.32 127118[121:Spt:127116.0,126950.1] || -> node4(s41)*. % 76.16/76.32 127120[121:MRR:795.0,127118.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.32 127123[121:Res:53.1,127120.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.32 127128[122:Spt:127123.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 127130[122:Res:127128.0,61.1] always3(s41) || -> . % 76.16/76.32 127131[122:SSi:127130.0,78250.0,78253.0,108791.0,126949.0,127118.0] || -> . % 76.16/76.32 127132[122:Spt:127131.0,127123.0,127128.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.32 127133[122:Spt:127131.0,127123.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 127137[122:Res:127133.0,61.1] always3(s42) || -> . % 76.16/76.32 127138[122:SSi:127137.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.32 127139[120:Spt:127138.0,126948.0,126949.0] || until2p7(s41)*+ -> . % 76.16/76.32 127140[120:Spt:127138.0,126948.1] || -> node4(s40)*. % 76.16/76.32 127142[120:MRR:798.0,127140.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.32 127145[120:Res:53.1,127142.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.32 127147[121:Spt:127145.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 127149[121:Res:127147.0,61.1] always3(s40) || -> . % 76.16/76.32 127150[121:SSi:127149.0,78245.0,78249.0,108790.0,126947.0,127140.0] || -> . % 76.16/76.32 127151[121:Spt:127150.0,127145.0,127147.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.32 127152[121:Spt:127150.0,127145.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 127156[121:Res:127152.0,61.1] always3(s41) || -> . % 76.16/76.32 127157[121:SSi:127156.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.32 127158[119:Spt:127157.0,126946.0,126947.0] || until2p7(s40)*+ -> . % 76.16/76.32 127159[119:Spt:127157.0,126946.1] || -> node4(s39)*. % 76.16/76.32 127161[119:MRR:801.0,127159.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.32 127164[119:Res:53.1,127161.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.32 127166[120:Spt:127164.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 127168[120:Res:127166.0,61.1] always3(s39) || -> . % 76.16/76.32 127169[120:SSi:127168.0,78241.0,78244.0,108789.0,126945.0,127159.0] || -> . % 76.16/76.32 127170[120:Spt:127169.0,127164.0,127166.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.32 127171[120:Spt:127169.0,127164.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 127175[120:Res:127171.0,61.1] always3(s40) || -> . % 76.16/76.32 127176[120:SSi:127175.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.32 127177[118:Spt:127176.0,126944.0,126945.0] || until2p7(s39)*+ -> . % 76.16/76.32 127178[118:Spt:127176.0,126944.1] || -> node4(s38)*. % 76.16/76.32 127180[118:MRR:804.0,127178.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.32 127183[118:Res:53.1,127180.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.32 127185[119:Spt:127183.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 127187[119:Res:127185.0,61.1] always3(s38) || -> . % 76.16/76.32 127188[119:SSi:127187.0,78236.0,78240.0,108788.0,126943.0,127178.0] || -> . % 76.16/76.32 127189[119:Spt:127188.0,127183.0,127185.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.32 127190[119:Spt:127188.0,127183.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 127194[119:Res:127190.0,61.1] always3(s39) || -> . % 76.16/76.32 127195[119:SSi:127194.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.32 127196[117:Spt:127195.0,126942.0,126943.0] || until2p7(s38)*+ -> . % 76.16/76.32 127197[117:Spt:127195.0,126942.1] || -> node4(s37)*. % 76.16/76.32 127199[117:MRR:807.0,127197.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.32 127202[117:Res:53.1,127199.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.32 127207[118:Spt:127202.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 127209[118:Res:127207.0,61.1] always3(s37) || -> . % 76.16/76.32 127210[118:SSi:127209.0,78232.0,78235.0,108787.0,126941.0,127197.0] || -> . % 76.16/76.32 127211[118:Spt:127210.0,127202.0,127207.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.32 127212[118:Spt:127210.0,127202.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 127216[118:Res:127212.0,61.1] always3(s38) || -> . % 76.16/76.32 127217[118:SSi:127216.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.32 127218[116:Spt:127217.0,126940.0,126941.0] || until2p7(s37)*+ -> . % 76.16/76.32 127219[116:Spt:127217.0,126940.1] || -> node4(s36)*. % 76.16/76.32 127221[116:MRR:810.0,127219.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.32 127224[116:Res:53.1,127221.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.32 127226[117:Spt:127224.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 127228[117:Res:127226.0,61.1] always3(s36) || -> . % 76.16/76.32 127229[117:SSi:127228.0,78227.0,78231.0,108786.0,126939.0,127219.0] || -> . % 76.16/76.32 127230[117:Spt:127229.0,127224.0,127226.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.32 127231[117:Spt:127229.0,127224.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 127235[117:Res:127231.0,61.1] always3(s37) || -> . % 76.16/76.32 127236[117:SSi:127235.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.32 127237[115:Spt:127236.0,126938.0,126939.0] || until2p7(s36)*+ -> . % 76.16/76.32 127238[115:Spt:127236.0,126938.1] || -> node4(s35)*. % 76.16/76.32 127240[115:MRR:813.0,127238.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.32 127243[115:Res:53.1,127240.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.32 127245[116:Spt:127243.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 127247[116:Res:127245.0,61.1] always3(s35) || -> . % 76.16/76.32 127248[116:SSi:127247.0,78223.0,78226.0,108785.0,126937.0,127238.0] || -> . % 76.16/76.32 127249[116:Spt:127248.0,127243.0,127245.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.32 127250[116:Spt:127248.0,127243.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 127254[116:Res:127250.0,61.1] always3(s36) || -> . % 76.16/76.32 127255[116:SSi:127254.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.32 127256[114:Spt:127255.0,126936.0,126937.0] || until2p7(s35)*+ -> . % 76.16/76.32 127257[114:Spt:127255.0,126936.1] || -> node4(s34)*. % 76.16/76.32 127259[114:MRR:816.0,127257.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.32 127262[114:Res:53.1,127259.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.32 127264[115:Spt:127262.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 127266[115:Res:127264.0,61.1] always3(s34) || -> . % 76.16/76.32 127267[115:SSi:127266.0,78218.0,78222.0,108784.0,126935.0,127257.0] || -> . % 76.16/76.32 127268[115:Spt:127267.0,127262.0,127264.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.32 127269[115:Spt:127267.0,127262.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 127273[115:Res:127269.0,61.1] always3(s35) || -> . % 76.16/76.32 127274[115:SSi:127273.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.32 127275[113:Spt:127274.0,126934.0,126935.0] || until2p7(s34)*+ -> . % 76.16/76.32 127276[113:Spt:127274.0,126934.1] || -> node4(s33)*. % 76.16/76.32 127278[113:MRR:819.0,127276.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.32 127281[113:Res:53.1,127278.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.32 127286[114:Spt:127281.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 127288[114:Res:127286.0,61.1] always3(s33) || -> . % 76.16/76.32 127289[114:SSi:127288.0,78214.0,78217.0,108783.0,126933.0,127276.0] || -> . % 76.16/76.32 127290[114:Spt:127289.0,127281.0,127286.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.32 127291[114:Spt:127289.0,127281.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 127295[114:Res:127291.0,61.1] always3(s34) || -> . % 76.16/76.32 127296[114:SSi:127295.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.32 127297[112:Spt:127296.0,126932.0,126933.0] || until2p7(s33)*+ -> . % 76.16/76.32 127298[112:Spt:127296.0,126932.1] || -> node4(s32)*. % 76.16/76.32 127300[112:MRR:822.0,127298.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.32 127303[112:Res:53.1,127300.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.32 127305[113:Spt:127303.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 127307[113:Res:127305.0,61.1] always3(s32) || -> . % 76.16/76.32 127308[113:SSi:127307.0,78209.0,78213.0,108782.0,126931.0,127298.0] || -> . % 76.16/76.32 127309[113:Spt:127308.0,127303.0,127305.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.32 127310[113:Spt:127308.0,127303.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 127314[113:Res:127310.0,61.1] always3(s33) || -> . % 76.16/76.32 127315[113:SSi:127314.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.32 127316[111:Spt:127315.0,126930.0,126931.0] || until2p7(s32)*+ -> . % 76.16/76.32 127317[111:Spt:127315.0,126930.1] || -> node4(s31)*. % 76.16/76.32 127319[111:MRR:825.0,127317.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.32 127322[111:Res:53.1,127319.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.32 127324[112:Spt:127322.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 127326[112:Res:127324.0,61.1] always3(s31) || -> . % 76.16/76.32 127327[112:SSi:127326.0,78205.0,78208.0,108781.0,126929.0,127317.0] || -> . % 76.16/76.32 127328[112:Spt:127327.0,127322.0,127324.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.32 127329[112:Spt:127327.0,127322.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 127333[112:Res:127329.0,61.1] always3(s32) || -> . % 76.16/76.32 127334[112:SSi:127333.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.32 127335[110:Spt:127334.0,126928.0,126929.0] || until2p7(s31)*+ -> . % 76.16/76.32 127336[110:Spt:127334.0,126928.1] || -> node4(s30)*. % 76.16/76.32 127338[110:MRR:828.0,127336.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.32 127341[110:Res:53.1,127338.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.32 127343[111:Spt:127341.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 127345[111:Res:127343.0,61.1] always3(s30) || -> . % 76.16/76.32 127346[111:SSi:127345.0,78200.0,78204.0,108780.0,126927.0,127336.0] || -> . % 76.16/76.32 127347[111:Spt:127346.0,127341.0,127343.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.32 127348[111:Spt:127346.0,127341.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 127352[111:Res:127348.0,61.1] always3(s31) || -> . % 76.16/76.32 127353[111:SSi:127352.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.32 127354[109:Spt:127353.0,126926.0,126927.0] || until2p7(s30)*+ -> . % 76.16/76.32 127355[109:Spt:127353.0,126926.1] || -> node4(s29)*. % 76.16/76.32 127357[109:MRR:831.0,127355.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.32 127360[109:Res:53.1,127357.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.32 127365[110:Spt:127360.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 127367[110:Res:127365.0,61.1] always3(s29) || -> . % 76.16/76.32 127368[110:SSi:127367.0,78196.0,78199.0,108779.0,126925.0,127355.0] || -> . % 76.16/76.32 127369[110:Spt:127368.0,127360.0,127365.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.32 127370[110:Spt:127368.0,127360.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 127374[110:Res:127370.0,61.1] always3(s30) || -> . % 76.16/76.32 127375[110:SSi:127374.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.32 127376[108:Spt:127375.0,126924.0,126925.0] || until2p7(s29)*+ -> . % 76.16/76.32 127377[108:Spt:127375.0,126924.1] || -> node4(s28)*. % 76.16/76.32 127379[108:MRR:834.0,127377.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.32 127382[108:Res:53.1,127379.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.32 127384[109:Spt:127382.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 127386[109:Res:127384.0,61.1] always3(s28) || -> . % 76.16/76.32 127387[109:SSi:127386.0,78191.0,78195.0,108778.0,126923.0,127377.0] || -> . % 76.16/76.32 127388[109:Spt:127387.0,127382.0,127384.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.32 127389[109:Spt:127387.0,127382.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 127393[109:Res:127389.0,61.1] always3(s29) || -> . % 76.16/76.32 127394[109:SSi:127393.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.32 127395[107:Spt:127394.0,126922.0,126923.0] || until2p7(s28)*+ -> . % 76.16/76.32 127396[107:Spt:127394.0,126922.1] || -> node4(s27)*. % 76.16/76.32 127398[107:MRR:837.0,127396.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.32 127401[107:Res:53.1,127398.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.32 127403[108:Spt:127401.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 127405[108:Res:127403.0,61.1] always3(s27) || -> . % 76.16/76.32 127406[108:SSi:127405.0,78187.0,78190.0,108777.0,126921.0,127396.0] || -> . % 76.16/76.32 127407[108:Spt:127406.0,127401.0,127403.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.32 127408[108:Spt:127406.0,127401.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 127412[108:Res:127408.0,61.1] always3(s28) || -> . % 76.16/76.32 127413[108:SSi:127412.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.32 127414[106:Spt:127413.0,126920.0,126921.0] || until2p7(s27)*+ -> . % 76.16/76.32 127415[106:Spt:127413.0,126920.1] || -> node4(s26)*. % 76.16/76.32 127417[106:MRR:840.0,127415.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.32 127420[106:Res:53.1,127417.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.32 127422[107:Spt:127420.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 127424[107:Res:127422.0,61.1] always3(s26) || -> . % 76.16/76.32 127425[107:SSi:127424.0,78182.0,78186.0,108776.0,126919.0,127415.0] || -> . % 76.16/76.32 127426[107:Spt:127425.0,127420.0,127422.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.32 127427[107:Spt:127425.0,127420.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 127431[107:Res:127427.0,61.1] always3(s27) || -> . % 76.16/76.32 127432[107:SSi:127431.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.32 127433[105:Spt:127432.0,126918.0,126919.0] || until2p7(s26)*+ -> . % 76.16/76.32 127434[105:Spt:127432.0,126918.1] || -> node4(s25)*. % 76.16/76.32 127436[105:MRR:843.0,127434.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.32 127439[105:Res:53.1,127436.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.32 127444[106:Spt:127439.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 127446[106:Res:127444.0,61.1] always3(s25) || -> . % 76.16/76.32 127447[106:SSi:127446.0,78178.0,78181.0,108775.0,126917.0,127434.0] || -> . % 76.16/76.32 127448[106:Spt:127447.0,127439.0,127444.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.32 127449[106:Spt:127447.0,127439.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 127453[106:Res:127449.0,61.1] always3(s26) || -> . % 76.16/76.32 127454[106:SSi:127453.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.32 127455[104:Spt:127454.0,126916.0,126917.0] || until2p7(s25)*+ -> . % 76.16/76.32 127456[104:Spt:127454.0,126916.1] || -> node4(s24)*. % 76.16/76.32 127458[104:MRR:846.0,127456.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.32 127461[104:Res:53.1,127458.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.32 127463[105:Spt:127461.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 127465[105:Res:127463.0,61.1] always3(s24) || -> . % 76.16/76.32 127466[105:SSi:127465.0,78173.0,78177.0,108774.0,126915.0,127456.0] || -> . % 76.16/76.32 127467[105:Spt:127466.0,127461.0,127463.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.32 127468[105:Spt:127466.0,127461.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 127472[105:Res:127468.0,61.1] always3(s25) || -> . % 76.16/76.32 127473[105:SSi:127472.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.32 127474[103:Spt:127473.0,126914.0,126915.0] || until2p7(s24)*+ -> . % 76.16/76.32 127475[103:Spt:127473.0,126914.1] || -> node4(s23)*. % 76.16/76.32 127477[103:MRR:849.0,127475.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.32 127480[103:Res:53.1,127477.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.32 127482[104:Spt:127480.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 127484[104:Res:127482.0,61.1] always3(s23) || -> . % 76.16/76.32 127485[104:SSi:127484.0,78169.0,78172.0,108773.0,126913.0,127475.0] || -> . % 76.16/76.32 127486[104:Spt:127485.0,127480.0,127482.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.32 127487[104:Spt:127485.0,127480.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 127491[104:Res:127487.0,61.1] always3(s24) || -> . % 76.16/76.32 127492[104:SSi:127491.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.32 127493[102:Spt:127492.0,126912.0,126913.0] || until2p7(s23)*+ -> . % 76.16/76.32 127494[102:Spt:127492.0,126912.1] || -> node4(s22)*. % 76.16/76.32 127496[102:MRR:852.0,127494.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.32 127499[102:Res:53.1,127496.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.32 127501[103:Spt:127499.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 127503[103:Res:127501.0,61.1] always3(s22) || -> . % 76.16/76.32 127504[103:SSi:127503.0,78164.0,78168.0,108772.0,126911.0,127494.0] || -> . % 76.16/76.32 127505[103:Spt:127504.0,127499.0,127501.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.32 127506[103:Spt:127504.0,127499.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 127510[103:Res:127506.0,61.1] always3(s23) || -> . % 76.16/76.32 127511[103:SSi:127510.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.32 127512[101:Spt:127511.0,126910.0,126911.0] || until2p7(s22)*+ -> . % 76.16/76.32 127513[101:Spt:127511.0,126910.1] || -> node4(s21)*. % 76.16/76.32 127515[101:MRR:855.0,127513.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.32 127518[101:Res:53.1,127515.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.32 127523[102:Spt:127518.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 127525[102:Res:127523.0,61.1] always3(s21) || -> . % 76.16/76.32 127526[102:SSi:127525.0,78160.0,78163.0,108771.0,126909.0,127513.0] || -> . % 76.16/76.32 127527[102:Spt:127526.0,127518.0,127523.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.32 127528[102:Spt:127526.0,127518.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 127532[102:Res:127528.0,61.1] always3(s22) || -> . % 76.16/76.32 127533[102:SSi:127532.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.32 127534[100:Spt:127533.0,126908.0,126909.0] || until2p7(s21)*+ -> . % 76.16/76.32 127535[100:Spt:127533.0,126908.1] || -> node4(s20)*. % 76.16/76.32 127537[100:MRR:858.0,127535.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.32 127540[100:Res:53.1,127537.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.32 127542[101:Spt:127540.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 127544[101:Res:127542.0,61.1] always3(s20) || -> . % 76.16/76.32 127545[101:SSi:127544.0,78155.0,78159.0,108770.0,126907.0,127535.0] || -> . % 76.16/76.32 127546[101:Spt:127545.0,127540.0,127542.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.32 127547[101:Spt:127545.0,127540.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 127551[101:Res:127547.0,61.1] always3(s21) || -> . % 76.16/76.32 127552[101:SSi:127551.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.32 127553[99:Spt:127552.0,126906.0,126907.0] || until2p7(s20)*+ -> . % 76.16/76.32 127554[99:Spt:127552.0,126906.1] || -> node4(s19)*. % 76.16/76.32 127556[99:MRR:861.0,127554.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.32 127559[99:Res:53.1,127556.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.32 127561[100:Spt:127559.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 127563[100:Res:127561.0,61.1] always3(s19) || -> . % 76.16/76.32 127564[100:SSi:127563.0,78151.0,78154.0,108769.0,126905.0,127554.0] || -> . % 76.16/76.32 127565[100:Spt:127564.0,127559.0,127561.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.32 127566[100:Spt:127564.0,127559.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 127570[100:Res:127566.0,61.1] always3(s20) || -> . % 76.16/76.32 127571[100:SSi:127570.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.32 127572[98:Spt:127571.0,126904.0,126905.0] || until2p7(s19)*+ -> . % 76.16/76.32 127573[98:Spt:127571.0,126904.1] || -> node4(s18)*. % 76.16/76.32 127575[98:MRR:864.0,127573.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.32 127578[98:Res:53.1,127575.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.32 127580[99:Spt:127578.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 127582[99:Res:127580.0,61.1] always3(s18) || -> . % 76.16/76.32 127583[99:SSi:127582.0,78146.0,78150.0,108768.0,126903.0,127573.0] || -> . % 76.16/76.32 127584[99:Spt:127583.0,127578.0,127580.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.32 127585[99:Spt:127583.0,127578.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 127589[99:Res:127585.0,61.1] always3(s19) || -> . % 76.16/76.32 127590[99:SSi:127589.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.32 127591[97:Spt:127590.0,126902.0,126903.0] || until2p7(s18)*+ -> . % 76.16/76.32 127592[97:Spt:127590.0,126902.1] || -> node4(s17)*. % 76.16/76.32 127594[97:MRR:867.0,127592.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.32 127597[97:Res:53.1,127594.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.32 127602[98:Spt:127597.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 127604[98:Res:127602.0,61.1] always3(s17) || -> . % 76.16/76.32 127605[98:SSi:127604.0,78142.0,78145.0,108767.0,126901.0,127592.0] || -> . % 76.16/76.32 127606[98:Spt:127605.0,127597.0,127602.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.32 127607[98:Spt:127605.0,127597.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 127611[98:Res:127607.0,61.1] always3(s18) || -> . % 76.16/76.32 127612[98:SSi:127611.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.32 127613[96:Spt:127612.0,126900.0,126901.0] || until2p7(s17)*+ -> . % 76.16/76.32 127614[96:Spt:127612.0,126900.1] || -> node4(s16)*. % 76.16/76.32 127616[96:MRR:870.0,127614.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.32 127619[96:Res:53.1,127616.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.32 127621[97:Spt:127619.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.32 127623[97:Res:127621.0,61.1] always3(s16) || -> . % 76.16/76.32 127624[97:SSi:127623.0,78137.0,78141.0,108766.0,126899.0,127614.0] || -> . % 76.16/76.32 127625[97:Spt:127624.0,127619.0,127621.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.32 127626[97:Spt:127624.0,127619.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 127630[97:Res:127626.0,61.1] always3(s17) || -> . % 76.16/76.32 127631[97:SSi:127630.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.32 127632[95:Spt:127631.0,126898.0,126899.0] || until2p7(s16)*+ -> . % 76.16/76.32 127633[95:Spt:127631.0,126898.1] || -> node4(s15)*. % 76.16/76.32 127635[95:MRR:873.0,127633.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.32 127638[95:Res:53.1,127635.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.32 127640[96:Spt:127638.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.32 127642[96:Res:127640.0,61.1] always3(s15) || -> . % 76.16/76.32 127643[96:SSi:127642.0,78133.0,78136.0,108765.0,126897.0,127633.0] || -> . % 76.16/76.32 127644[96:Spt:127643.0,127638.0,127640.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.32 127645[96:Spt:127643.0,127638.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.32 127649[96:Res:127645.0,61.1] always3(s16) || -> . % 76.16/76.32 127650[96:SSi:127649.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.32 127651[94:Spt:127650.0,126896.0,126897.0] || until2p7(s15)*+ -> . % 76.16/76.32 127652[94:Spt:127650.0,126896.1] || -> node4(s14)*. % 76.16/76.32 127654[94:MRR:876.0,127652.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.32 127657[94:Res:53.1,127654.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.32 127659[95:Spt:127657.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.32 127661[95:Res:127659.0,61.1] always3(s14) || -> . % 76.16/76.32 127662[95:SSi:127661.0,78128.0,78132.0,108764.0,126895.0,127652.0] || -> . % 76.16/76.32 127663[95:Spt:127662.0,127657.0,127659.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.32 127664[95:Spt:127662.0,127657.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.32 127668[95:Res:127664.0,61.1] always3(s15) || -> . % 76.16/76.32 127669[95:SSi:127668.0,78133.0,78136.0,108765.0] || -> . % 76.16/76.32 127670[93:Spt:127669.0,126894.0,126895.0] || until2p7(s14)*+ -> . % 76.16/76.32 127671[93:Spt:127669.0,126894.1] || -> node4(s13)*. % 76.16/76.32 127673[93:MRR:879.0,127671.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.32 127676[93:Res:53.1,127673.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.32 127681[94:Spt:127676.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.32 127683[94:Res:127681.0,61.1] always3(s13) || -> . % 76.16/76.32 127684[94:SSi:127683.0,78124.0,78127.0,108763.0,126893.0,127671.0] || -> . % 76.16/76.32 127685[94:Spt:127684.0,127676.0,127681.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.32 127686[94:Spt:127684.0,127676.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.32 127690[94:Res:127686.0,61.1] always3(s14) || -> . % 76.16/76.32 127691[94:SSi:127690.0,78128.0,78132.0,108764.0] || -> . % 76.16/76.32 127692[92:Spt:127691.0,126892.0,126893.0] || until2p7(s13)*+ -> . % 76.16/76.32 127693[92:Spt:127691.0,126892.1] || -> node4(s12)*. % 76.16/76.32 127695[92:MRR:882.0,127693.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.32 127698[92:Res:53.1,127695.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.32 127700[92:MRR:127698.0,126882.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.32 127702[92:Res:127700.0,61.1] always3(s13) || -> . % 76.16/76.32 127703[92:SSi:127702.0,78124.0,78127.0,108763.0] || -> . % 76.16/76.32 127704[90:Spt:127703.0,126742.0,126745.0] || trans(s49,s12)*+ -> . % 76.16/76.32 127705[90:Spt:127703.0,126742.1,126742.2,126742.3,126742.4,126742.5,126742.6,126742.7,126742.8,126742.9] || -> trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.32 127707[90:MRR:126744.1,127704.0] xuntil6(s49) || -> trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.32 127708[91:Spt:127705.0] || -> trans(s49,s11)*. % 76.16/76.32 127709[91:Res:127708.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s11)*. % 76.16/76.32 127711[91:Res:127708.0,60.0] || -> node2(s49,s11)*. % 76.16/76.32 127712[91:SSi:127709.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s11)*. % 76.16/76.32 127713[91:Res:127711.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)*. % 76.16/76.32 127838[91:SoR:127713.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)*. % 76.16/76.32 127840[91:SoR:127838.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)* xuntil6(s49). % 76.16/76.32 127841[91:SSi:127840.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s11,c_busy)* xuntil6(s49). % 76.16/76.32 127842[92:Spt:127841.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.32 127844[92:Res:127842.0,61.1] always3(s11) || -> . % 76.16/76.32 127845[92:SSi:127844.0,78115.0,78118.0,108761.0] || -> . % 76.16/76.32 127846[92:Spt:127845.0,127841.1,127842.0] || m_main_v_state(s11,c_busy)*+ -> . % 76.16/76.32 127847[92:Spt:127845.0,127841.0,127841.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.32 127851[92:MRR:127838.2,127846.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.32 127852[92:Res:53.1,127847.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.32 127854[92:MRR:127852.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.32 127855[92:MRR:127712.0,127854.0] || -> until2p7(s11)*. % 76.16/76.32 127856[92:MRR:207.0,127855.0] || -> until2p7(s12)* node4(s11). % 76.16/76.32 127857[93:Spt:127856.0] || -> until2p7(s12)*. % 76.16/76.32 127858[93:MRR:208.0,127857.0] || -> until2p7(s13)* node4(s12). % 76.16/76.32 127859[94:Spt:127858.0] || -> until2p7(s13)*. % 76.16/76.32 127860[94:MRR:209.0,127859.0] || -> until2p7(s14)* node4(s13). % 76.16/76.32 127861[95:Spt:127860.0] || -> until2p7(s14)*. % 76.16/76.32 127862[95:MRR:210.0,127861.0] || -> until2p7(s15)* node4(s14). % 76.16/76.32 127863[96:Spt:127862.0] || -> until2p7(s15)*. % 76.16/76.32 127864[96:MRR:211.0,127863.0] || -> until2p7(s16)* node4(s15). % 76.16/76.32 127865[97:Spt:127864.0] || -> until2p7(s16)*. % 76.16/76.32 127866[97:MRR:212.0,127865.0] || -> until2p7(s17)* node4(s16). % 76.16/76.32 127867[98:Spt:127866.0] || -> until2p7(s17)*. % 76.16/76.32 127868[98:MRR:213.0,127867.0] || -> until2p7(s18)* node4(s17). % 76.16/76.32 127869[99:Spt:127868.0] || -> until2p7(s18)*. % 76.16/76.32 127870[99:MRR:214.0,127869.0] || -> until2p7(s19)* node4(s18). % 76.16/76.32 127871[100:Spt:127870.0] || -> until2p7(s19)*. % 76.16/76.32 127872[100:MRR:215.0,127871.0] || -> until2p7(s20)* node4(s19). % 76.16/76.32 127873[101:Spt:127872.0] || -> until2p7(s20)*. % 76.16/76.32 127874[101:MRR:216.0,127873.0] || -> until2p7(s21)* node4(s20). % 76.16/76.32 127875[102:Spt:127874.0] || -> until2p7(s21)*. % 76.16/76.32 127876[102:MRR:217.0,127875.0] || -> until2p7(s22)* node4(s21). % 76.16/76.32 127877[103:Spt:127876.0] || -> until2p7(s22)*. % 76.16/76.32 127878[103:MRR:218.0,127877.0] || -> until2p7(s23)* node4(s22). % 76.16/76.32 127879[104:Spt:127878.0] || -> until2p7(s23)*. % 76.16/76.32 127880[104:MRR:219.0,127879.0] || -> until2p7(s24)* node4(s23). % 76.16/76.32 127881[105:Spt:127880.0] || -> until2p7(s24)*. % 76.16/76.32 127882[105:MRR:220.0,127881.0] || -> until2p7(s25)* node4(s24). % 76.16/76.32 127883[106:Spt:127882.0] || -> until2p7(s25)*. % 76.16/76.32 127884[106:MRR:221.0,127883.0] || -> until2p7(s26)* node4(s25). % 76.16/76.32 127885[107:Spt:127884.0] || -> until2p7(s26)*. % 76.16/76.32 127886[107:MRR:222.0,127885.0] || -> until2p7(s27)* node4(s26). % 76.16/76.32 127887[108:Spt:127886.0] || -> until2p7(s27)*. % 76.16/76.32 127888[108:MRR:223.0,127887.0] || -> until2p7(s28)* node4(s27). % 76.16/76.32 127889[109:Spt:127888.0] || -> until2p7(s28)*. % 76.16/76.32 127890[109:MRR:224.0,127889.0] || -> until2p7(s29)* node4(s28). % 76.16/76.32 127891[110:Spt:127890.0] || -> until2p7(s29)*. % 76.16/76.32 127892[110:MRR:225.0,127891.0] || -> until2p7(s30)* node4(s29). % 76.16/76.32 127893[111:Spt:127892.0] || -> until2p7(s30)*. % 76.16/76.32 127894[111:MRR:226.0,127893.0] || -> until2p7(s31)* node4(s30). % 76.16/76.32 127895[112:Spt:127894.0] || -> until2p7(s31)*. % 76.16/76.32 127896[112:MRR:227.0,127895.0] || -> until2p7(s32)* node4(s31). % 76.16/76.32 127897[113:Spt:127896.0] || -> until2p7(s32)*. % 76.16/76.32 127898[113:MRR:228.0,127897.0] || -> until2p7(s33)* node4(s32). % 76.16/76.32 127899[114:Spt:127898.0] || -> until2p7(s33)*. % 76.16/76.32 127900[114:MRR:229.0,127899.0] || -> until2p7(s34)* node4(s33). % 76.16/76.32 127901[115:Spt:127900.0] || -> until2p7(s34)*. % 76.16/76.32 127902[115:MRR:230.0,127901.0] || -> until2p7(s35)* node4(s34). % 76.16/76.32 127903[116:Spt:127902.0] || -> until2p7(s35)*. % 76.16/76.32 127904[116:MRR:231.0,127903.0] || -> until2p7(s36)* node4(s35). % 76.16/76.32 127905[117:Spt:127904.0] || -> until2p7(s36)*. % 76.16/76.32 127906[117:MRR:232.0,127905.0] || -> until2p7(s37)* node4(s36). % 76.16/76.32 127907[118:Spt:127906.0] || -> until2p7(s37)*. % 76.16/76.32 127908[118:MRR:235.0,127907.0] || -> until2p7(s38)* node4(s37). % 76.16/76.32 127909[119:Spt:127908.0] || -> until2p7(s38)*. % 76.16/76.32 127910[119:MRR:236.0,127909.0] || -> until2p7(s39)* node4(s38). % 76.16/76.32 127911[120:Spt:127910.0] || -> until2p7(s39)*. % 76.16/76.32 127912[120:MRR:237.0,127911.0] || -> until2p7(s40)* node4(s39). % 76.16/76.32 127913[121:Spt:127912.0] || -> until2p7(s40)*. % 76.16/76.32 127914[121:MRR:238.0,127913.0] || -> until2p7(s41)* node4(s40). % 76.16/76.32 127915[122:Spt:127914.0] || -> until2p7(s41)*. % 76.16/76.32 127916[122:MRR:239.0,127915.0] || -> until2p7(s42)* node4(s41). % 76.16/76.32 127917[123:Spt:127916.0] || -> until2p7(s42)*. % 76.16/76.32 127918[123:MRR:240.0,127917.0] || -> until2p7(s43)* node4(s42). % 76.16/76.32 127919[124:Spt:127918.0] || -> until2p7(s43)*. % 76.16/76.32 127920[124:MRR:241.0,127919.0] || -> until2p7(s44)* node4(s43). % 76.16/76.32 127921[125:Spt:127920.0] || -> until2p7(s44)*. % 76.16/76.32 127922[125:MRR:539.0,127921.0] || -> until2p7(s45)* node4(s44). % 76.16/76.32 127923[126:Spt:127922.0] || -> until2p7(s45)*. % 76.16/76.32 127924[126:MRR:544.0,127923.0] || -> until2p7(s46)* node4(s45). % 76.16/76.32 127925[127:Spt:127924.0] || -> until2p7(s46)*. % 76.16/76.32 127926[127:MRR:549.0,127925.0] || -> until2p7(s47)* node4(s46). % 76.16/76.32 127927[128:Spt:127926.0] || -> until2p7(s47)*. % 76.16/76.32 127928[128:MRR:554.0,127927.0] || -> until2p7(s48)* node4(s47). % 76.16/76.32 127929[129:Spt:127928.0] || -> until2p7(s48)*. % 76.16/76.32 127930[129:MRR:559.0,127929.0] || -> until2p7(s49)* node4(s48). % 76.16/76.32 127931[130:Spt:127930.0] || -> until2p7(s49)*. % 76.16/76.32 127932[130:MRR:194.0,127931.0] || -> node4(s49)*. % 76.16/76.32 127933[130:MRR:127851.0,127932.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.32 127937[130:Res:53.1,127933.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.32 127939[130:MRR:127937.0,78381.0] || -> . % 76.16/76.32 127940[130:Spt:127939.0,127930.0,127931.0] || until2p7(s49)*+ -> . % 76.16/76.32 127941[130:Spt:127939.0,127930.1] || -> node4(s48)*. % 76.16/76.32 127942[130:MRR:78384.0,127941.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.32 127945[130:Res:53.1,127942.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 127948[130:Res:127945.0,61.1] always3(s48) || -> . % 76.16/76.32 127949[130:SSi:127948.0,78281.0,78387.0,108798.0,127929.0,127941.0] || -> . % 76.16/76.32 127950[129:Spt:127949.0,127928.0,127929.0] || until2p7(s48)*+ -> . % 76.16/76.32 127951[129:Spt:127949.0,127928.1] || -> node4(s47)*. % 76.16/76.32 127953[129:MRR:777.0,127951.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.32 127965[129:Res:53.1,127953.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.32 127967[130:Spt:127965.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 127969[130:Res:127967.0,61.1] always3(s47) || -> . % 76.16/76.32 127970[130:SSi:127969.0,78277.0,78280.0,108797.0,127927.0,127951.0] || -> . % 76.16/76.32 127971[130:Spt:127970.0,127965.0,127967.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.32 127972[130:Spt:127970.0,127965.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 127976[130:Res:127972.0,61.1] always3(s48) || -> . % 76.16/76.32 127977[130:SSi:127976.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.32 127978[128:Spt:127977.0,127926.0,127927.0] || until2p7(s47)*+ -> . % 76.16/76.32 127979[128:Spt:127977.0,127926.1] || -> node4(s46)*. % 76.16/76.32 127981[128:MRR:780.0,127979.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.32 127988[128:Res:53.1,127981.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.32 127993[129:Spt:127988.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 127995[129:Res:127993.0,61.1] always3(s46) || -> . % 76.16/76.32 127996[129:SSi:127995.0,78272.0,78276.0,108796.0,127925.0,127979.0] || -> . % 76.16/76.32 127997[129:Spt:127996.0,127988.0,127993.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.32 127998[129:Spt:127996.0,127988.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 128002[129:Res:127998.0,61.1] always3(s47) || -> . % 76.16/76.32 128003[129:SSi:128002.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.32 128004[127:Spt:128003.0,127924.0,127925.0] || until2p7(s46)*+ -> . % 76.16/76.32 128005[127:Spt:128003.0,127924.1] || -> node4(s45)*. % 76.16/76.32 128007[127:MRR:783.0,128005.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.32 128010[127:Res:53.1,128007.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.32 128012[128:Spt:128010.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 128014[128:Res:128012.0,61.1] always3(s45) || -> . % 76.16/76.32 128015[128:SSi:128014.0,78268.0,78271.0,108795.0,127923.0,128005.0] || -> . % 76.16/76.32 128016[128:Spt:128015.0,128010.0,128012.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.32 128017[128:Spt:128015.0,128010.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 128021[128:Res:128017.0,61.1] always3(s46) || -> . % 76.16/76.32 128022[128:SSi:128021.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.32 128023[126:Spt:128022.0,127922.0,127923.0] || until2p7(s45)*+ -> . % 76.16/76.32 128024[126:Spt:128022.0,127922.1] || -> node4(s44)*. % 76.16/76.32 128026[126:MRR:786.0,128024.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.32 128029[126:Res:53.1,128026.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.32 128031[127:Spt:128029.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 128033[127:Res:128031.0,61.1] always3(s44) || -> . % 76.16/76.32 128034[127:SSi:128033.0,78263.0,78267.0,108794.0,127921.0,128024.0] || -> . % 76.16/76.32 128035[127:Spt:128034.0,128029.0,128031.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.32 128036[127:Spt:128034.0,128029.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 128040[127:Res:128036.0,61.1] always3(s45) || -> . % 76.16/76.32 128041[127:SSi:128040.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.32 128042[125:Spt:128041.0,127920.0,127921.0] || until2p7(s44)*+ -> . % 76.16/76.32 128043[125:Spt:128041.0,127920.1] || -> node4(s43)*. % 76.16/76.32 128045[125:MRR:789.0,128043.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.32 128048[125:Res:53.1,128045.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.32 128050[126:Spt:128048.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 128052[126:Res:128050.0,61.1] always3(s43) || -> . % 76.16/76.32 128053[126:SSi:128052.0,78259.0,78262.0,108793.0,127919.0,128043.0] || -> . % 76.16/76.32 128054[126:Spt:128053.0,128048.0,128050.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.32 128055[126:Spt:128053.0,128048.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 128059[126:Res:128055.0,61.1] always3(s44) || -> . % 76.16/76.32 128060[126:SSi:128059.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.32 128061[124:Spt:128060.0,127918.0,127919.0] || until2p7(s43)*+ -> . % 76.16/76.32 128062[124:Spt:128060.0,127918.1] || -> node4(s42)*. % 76.16/76.32 128064[124:MRR:792.0,128062.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.32 128067[124:Res:53.1,128064.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.32 128072[125:Spt:128067.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 128074[125:Res:128072.0,61.1] always3(s42) || -> . % 76.16/76.32 128075[125:SSi:128074.0,78254.0,78258.0,108792.0,127917.0,128062.0] || -> . % 76.16/76.32 128076[125:Spt:128075.0,128067.0,128072.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.32 128077[125:Spt:128075.0,128067.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 128081[125:Res:128077.0,61.1] always3(s43) || -> . % 76.16/76.32 128082[125:SSi:128081.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.32 128083[123:Spt:128082.0,127916.0,127917.0] || until2p7(s42)*+ -> . % 76.16/76.32 128084[123:Spt:128082.0,127916.1] || -> node4(s41)*. % 76.16/76.32 128086[123:MRR:795.0,128084.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.32 128089[123:Res:53.1,128086.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.32 128091[124:Spt:128089.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 128093[124:Res:128091.0,61.1] always3(s41) || -> . % 76.16/76.32 128094[124:SSi:128093.0,78250.0,78253.0,108791.0,127915.0,128084.0] || -> . % 76.16/76.32 128095[124:Spt:128094.0,128089.0,128091.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.32 128096[124:Spt:128094.0,128089.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 128100[124:Res:128096.0,61.1] always3(s42) || -> . % 76.16/76.32 128101[124:SSi:128100.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.32 128102[122:Spt:128101.0,127914.0,127915.0] || until2p7(s41)*+ -> . % 76.16/76.32 128103[122:Spt:128101.0,127914.1] || -> node4(s40)*. % 76.16/76.32 128105[122:MRR:798.0,128103.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.32 128108[122:Res:53.1,128105.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.32 128110[123:Spt:128108.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 128112[123:Res:128110.0,61.1] always3(s40) || -> . % 76.16/76.32 128113[123:SSi:128112.0,78245.0,78249.0,108790.0,127913.0,128103.0] || -> . % 76.16/76.32 128114[123:Spt:128113.0,128108.0,128110.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.32 128115[123:Spt:128113.0,128108.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 128119[123:Res:128115.0,61.1] always3(s41) || -> . % 76.16/76.32 128120[123:SSi:128119.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.32 128121[121:Spt:128120.0,127912.0,127913.0] || until2p7(s40)*+ -> . % 76.16/76.32 128122[121:Spt:128120.0,127912.1] || -> node4(s39)*. % 76.16/76.32 128124[121:MRR:801.0,128122.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.32 128127[121:Res:53.1,128124.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.32 128129[122:Spt:128127.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 128131[122:Res:128129.0,61.1] always3(s39) || -> . % 76.16/76.32 128132[122:SSi:128131.0,78241.0,78244.0,108789.0,127911.0,128122.0] || -> . % 76.16/76.32 128133[122:Spt:128132.0,128127.0,128129.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.32 128134[122:Spt:128132.0,128127.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 128138[122:Res:128134.0,61.1] always3(s40) || -> . % 76.16/76.32 128139[122:SSi:128138.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.32 128140[120:Spt:128139.0,127910.0,127911.0] || until2p7(s39)*+ -> . % 76.16/76.32 128141[120:Spt:128139.0,127910.1] || -> node4(s38)*. % 76.16/76.32 128143[120:MRR:804.0,128141.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.32 128146[120:Res:53.1,128143.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.32 128151[121:Spt:128146.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 128153[121:Res:128151.0,61.1] always3(s38) || -> . % 76.16/76.32 128154[121:SSi:128153.0,78236.0,78240.0,108788.0,127909.0,128141.0] || -> . % 76.16/76.32 128155[121:Spt:128154.0,128146.0,128151.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.32 128156[121:Spt:128154.0,128146.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 128160[121:Res:128156.0,61.1] always3(s39) || -> . % 76.16/76.32 128161[121:SSi:128160.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.32 128162[119:Spt:128161.0,127908.0,127909.0] || until2p7(s38)*+ -> . % 76.16/76.32 128163[119:Spt:128161.0,127908.1] || -> node4(s37)*. % 76.16/76.32 128165[119:MRR:807.0,128163.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.32 128168[119:Res:53.1,128165.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.32 128170[120:Spt:128168.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 128172[120:Res:128170.0,61.1] always3(s37) || -> . % 76.16/76.32 128173[120:SSi:128172.0,78232.0,78235.0,108787.0,127907.0,128163.0] || -> . % 76.16/76.32 128174[120:Spt:128173.0,128168.0,128170.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.32 128175[120:Spt:128173.0,128168.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 128179[120:Res:128175.0,61.1] always3(s38) || -> . % 76.16/76.32 128180[120:SSi:128179.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.32 128181[118:Spt:128180.0,127906.0,127907.0] || until2p7(s37)*+ -> . % 76.16/76.32 128182[118:Spt:128180.0,127906.1] || -> node4(s36)*. % 76.16/76.32 128184[118:MRR:810.0,128182.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.32 128187[118:Res:53.1,128184.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.32 128189[119:Spt:128187.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 128191[119:Res:128189.0,61.1] always3(s36) || -> . % 76.16/76.32 128192[119:SSi:128191.0,78227.0,78231.0,108786.0,127905.0,128182.0] || -> . % 76.16/76.32 128193[119:Spt:128192.0,128187.0,128189.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.32 128194[119:Spt:128192.0,128187.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 128198[119:Res:128194.0,61.1] always3(s37) || -> . % 76.16/76.32 128199[119:SSi:128198.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.32 128200[117:Spt:128199.0,127904.0,127905.0] || until2p7(s36)*+ -> . % 76.16/76.32 128201[117:Spt:128199.0,127904.1] || -> node4(s35)*. % 76.16/76.32 128203[117:MRR:813.0,128201.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.32 128206[117:Res:53.1,128203.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.32 128208[118:Spt:128206.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 128210[118:Res:128208.0,61.1] always3(s35) || -> . % 76.16/76.32 128211[118:SSi:128210.0,78223.0,78226.0,108785.0,127903.0,128201.0] || -> . % 76.16/76.32 128212[118:Spt:128211.0,128206.0,128208.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.32 128213[118:Spt:128211.0,128206.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 128217[118:Res:128213.0,61.1] always3(s36) || -> . % 76.16/76.32 128218[118:SSi:128217.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.32 128219[116:Spt:128218.0,127902.0,127903.0] || until2p7(s35)*+ -> . % 76.16/76.32 128220[116:Spt:128218.0,127902.1] || -> node4(s34)*. % 76.16/76.32 128222[116:MRR:816.0,128220.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.32 128225[116:Res:53.1,128222.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.32 128230[117:Spt:128225.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 128232[117:Res:128230.0,61.1] always3(s34) || -> . % 76.16/76.32 128233[117:SSi:128232.0,78218.0,78222.0,108784.0,127901.0,128220.0] || -> . % 76.16/76.32 128234[117:Spt:128233.0,128225.0,128230.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.32 128235[117:Spt:128233.0,128225.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 128239[117:Res:128235.0,61.1] always3(s35) || -> . % 76.16/76.32 128240[117:SSi:128239.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.32 128241[115:Spt:128240.0,127900.0,127901.0] || until2p7(s34)*+ -> . % 76.16/76.32 128242[115:Spt:128240.0,127900.1] || -> node4(s33)*. % 76.16/76.32 128244[115:MRR:819.0,128242.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.32 128247[115:Res:53.1,128244.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.32 128249[116:Spt:128247.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 128251[116:Res:128249.0,61.1] always3(s33) || -> . % 76.16/76.32 128252[116:SSi:128251.0,78214.0,78217.0,108783.0,127899.0,128242.0] || -> . % 76.16/76.32 128253[116:Spt:128252.0,128247.0,128249.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.32 128254[116:Spt:128252.0,128247.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 128258[116:Res:128254.0,61.1] always3(s34) || -> . % 76.16/76.32 128259[116:SSi:128258.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.32 128260[114:Spt:128259.0,127898.0,127899.0] || until2p7(s33)*+ -> . % 76.16/76.32 128261[114:Spt:128259.0,127898.1] || -> node4(s32)*. % 76.16/76.32 128263[114:MRR:822.0,128261.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.32 128266[114:Res:53.1,128263.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.32 128268[115:Spt:128266.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 128270[115:Res:128268.0,61.1] always3(s32) || -> . % 76.16/76.32 128271[115:SSi:128270.0,78209.0,78213.0,108782.0,127897.0,128261.0] || -> . % 76.16/76.32 128272[115:Spt:128271.0,128266.0,128268.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.32 128273[115:Spt:128271.0,128266.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 128277[115:Res:128273.0,61.1] always3(s33) || -> . % 76.16/76.32 128278[115:SSi:128277.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.32 128279[113:Spt:128278.0,127896.0,127897.0] || until2p7(s32)*+ -> . % 76.16/76.32 128280[113:Spt:128278.0,127896.1] || -> node4(s31)*. % 76.16/76.32 128282[113:MRR:825.0,128280.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.32 128285[113:Res:53.1,128282.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.32 128287[114:Spt:128285.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 128289[114:Res:128287.0,61.1] always3(s31) || -> . % 76.16/76.32 128290[114:SSi:128289.0,78205.0,78208.0,108781.0,127895.0,128280.0] || -> . % 76.16/76.32 128291[114:Spt:128290.0,128285.0,128287.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.32 128292[114:Spt:128290.0,128285.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 128296[114:Res:128292.0,61.1] always3(s32) || -> . % 76.16/76.32 128297[114:SSi:128296.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.32 128298[112:Spt:128297.0,127894.0,127895.0] || until2p7(s31)*+ -> . % 76.16/76.32 128299[112:Spt:128297.0,127894.1] || -> node4(s30)*. % 76.16/76.32 128301[112:MRR:828.0,128299.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.32 128304[112:Res:53.1,128301.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.32 128309[113:Spt:128304.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 128311[113:Res:128309.0,61.1] always3(s30) || -> . % 76.16/76.32 128312[113:SSi:128311.0,78200.0,78204.0,108780.0,127893.0,128299.0] || -> . % 76.16/76.32 128313[113:Spt:128312.0,128304.0,128309.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.32 128314[113:Spt:128312.0,128304.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 128318[113:Res:128314.0,61.1] always3(s31) || -> . % 76.16/76.32 128319[113:SSi:128318.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.32 128320[111:Spt:128319.0,127892.0,127893.0] || until2p7(s30)*+ -> . % 76.16/76.32 128321[111:Spt:128319.0,127892.1] || -> node4(s29)*. % 76.16/76.32 128323[111:MRR:831.0,128321.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.32 128326[111:Res:53.1,128323.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.32 128328[112:Spt:128326.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 128330[112:Res:128328.0,61.1] always3(s29) || -> . % 76.16/76.32 128331[112:SSi:128330.0,78196.0,78199.0,108779.0,127891.0,128321.0] || -> . % 76.16/76.32 128332[112:Spt:128331.0,128326.0,128328.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.32 128333[112:Spt:128331.0,128326.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 128337[112:Res:128333.0,61.1] always3(s30) || -> . % 76.16/76.32 128338[112:SSi:128337.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.32 128339[110:Spt:128338.0,127890.0,127891.0] || until2p7(s29)*+ -> . % 76.16/76.32 128340[110:Spt:128338.0,127890.1] || -> node4(s28)*. % 76.16/76.32 128342[110:MRR:834.0,128340.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.32 128345[110:Res:53.1,128342.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.32 128347[111:Spt:128345.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 128349[111:Res:128347.0,61.1] always3(s28) || -> . % 76.16/76.32 128350[111:SSi:128349.0,78191.0,78195.0,108778.0,127889.0,128340.0] || -> . % 76.16/76.32 128351[111:Spt:128350.0,128345.0,128347.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.32 128352[111:Spt:128350.0,128345.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 128356[111:Res:128352.0,61.1] always3(s29) || -> . % 76.16/76.32 128357[111:SSi:128356.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.32 128358[109:Spt:128357.0,127888.0,127889.0] || until2p7(s28)*+ -> . % 76.16/76.32 128359[109:Spt:128357.0,127888.1] || -> node4(s27)*. % 76.16/76.32 128361[109:MRR:837.0,128359.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.32 128364[109:Res:53.1,128361.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.32 128366[110:Spt:128364.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 128368[110:Res:128366.0,61.1] always3(s27) || -> . % 76.16/76.32 128369[110:SSi:128368.0,78187.0,78190.0,108777.0,127887.0,128359.0] || -> . % 76.16/76.32 128370[110:Spt:128369.0,128364.0,128366.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.32 128371[110:Spt:128369.0,128364.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 128375[110:Res:128371.0,61.1] always3(s28) || -> . % 76.16/76.32 128376[110:SSi:128375.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.32 128377[108:Spt:128376.0,127886.0,127887.0] || until2p7(s27)*+ -> . % 76.16/76.32 128378[108:Spt:128376.0,127886.1] || -> node4(s26)*. % 76.16/76.32 128380[108:MRR:840.0,128378.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.32 128383[108:Res:53.1,128380.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.32 128388[109:Spt:128383.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 128390[109:Res:128388.0,61.1] always3(s26) || -> . % 76.16/76.32 128391[109:SSi:128390.0,78182.0,78186.0,108776.0,127885.0,128378.0] || -> . % 76.16/76.32 128392[109:Spt:128391.0,128383.0,128388.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.32 128393[109:Spt:128391.0,128383.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 128397[109:Res:128393.0,61.1] always3(s27) || -> . % 76.16/76.32 128398[109:SSi:128397.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.32 128399[107:Spt:128398.0,127884.0,127885.0] || until2p7(s26)*+ -> . % 76.16/76.32 128400[107:Spt:128398.0,127884.1] || -> node4(s25)*. % 76.16/76.32 128402[107:MRR:843.0,128400.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.32 128405[107:Res:53.1,128402.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.32 128407[108:Spt:128405.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 128409[108:Res:128407.0,61.1] always3(s25) || -> . % 76.16/76.32 128410[108:SSi:128409.0,78178.0,78181.0,108775.0,127883.0,128400.0] || -> . % 76.16/76.32 128411[108:Spt:128410.0,128405.0,128407.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.32 128412[108:Spt:128410.0,128405.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 128416[108:Res:128412.0,61.1] always3(s26) || -> . % 76.16/76.32 128417[108:SSi:128416.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.32 128418[106:Spt:128417.0,127882.0,127883.0] || until2p7(s25)*+ -> . % 76.16/76.32 128419[106:Spt:128417.0,127882.1] || -> node4(s24)*. % 76.16/76.32 128421[106:MRR:846.0,128419.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.32 128424[106:Res:53.1,128421.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.32 128426[107:Spt:128424.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 128428[107:Res:128426.0,61.1] always3(s24) || -> . % 76.16/76.32 128429[107:SSi:128428.0,78173.0,78177.0,108774.0,127881.0,128419.0] || -> . % 76.16/76.32 128430[107:Spt:128429.0,128424.0,128426.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.32 128431[107:Spt:128429.0,128424.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 128435[107:Res:128431.0,61.1] always3(s25) || -> . % 76.16/76.32 128436[107:SSi:128435.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.32 128437[105:Spt:128436.0,127880.0,127881.0] || until2p7(s24)*+ -> . % 76.16/76.32 128438[105:Spt:128436.0,127880.1] || -> node4(s23)*. % 76.16/76.32 128440[105:MRR:849.0,128438.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.32 128443[105:Res:53.1,128440.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.32 128445[106:Spt:128443.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 128447[106:Res:128445.0,61.1] always3(s23) || -> . % 76.16/76.32 128448[106:SSi:128447.0,78169.0,78172.0,108773.0,127879.0,128438.0] || -> . % 76.16/76.32 128449[106:Spt:128448.0,128443.0,128445.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.32 128450[106:Spt:128448.0,128443.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 128454[106:Res:128450.0,61.1] always3(s24) || -> . % 76.16/76.32 128455[106:SSi:128454.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.32 128456[104:Spt:128455.0,127878.0,127879.0] || until2p7(s23)*+ -> . % 76.16/76.32 128457[104:Spt:128455.0,127878.1] || -> node4(s22)*. % 76.16/76.32 128459[104:MRR:852.0,128457.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.32 128462[104:Res:53.1,128459.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.32 128467[105:Spt:128462.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 128469[105:Res:128467.0,61.1] always3(s22) || -> . % 76.16/76.32 128470[105:SSi:128469.0,78164.0,78168.0,108772.0,127877.0,128457.0] || -> . % 76.16/76.32 128471[105:Spt:128470.0,128462.0,128467.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.32 128472[105:Spt:128470.0,128462.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 128476[105:Res:128472.0,61.1] always3(s23) || -> . % 76.16/76.32 128477[105:SSi:128476.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.32 128478[103:Spt:128477.0,127876.0,127877.0] || until2p7(s22)*+ -> . % 76.16/76.32 128479[103:Spt:128477.0,127876.1] || -> node4(s21)*. % 76.16/76.32 128481[103:MRR:855.0,128479.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.32 128484[103:Res:53.1,128481.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.32 128486[104:Spt:128484.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 128488[104:Res:128486.0,61.1] always3(s21) || -> . % 76.16/76.32 128489[104:SSi:128488.0,78160.0,78163.0,108771.0,127875.0,128479.0] || -> . % 76.16/76.32 128490[104:Spt:128489.0,128484.0,128486.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.32 128491[104:Spt:128489.0,128484.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 128495[104:Res:128491.0,61.1] always3(s22) || -> . % 76.16/76.32 128496[104:SSi:128495.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.32 128497[102:Spt:128496.0,127874.0,127875.0] || until2p7(s21)*+ -> . % 76.16/76.32 128498[102:Spt:128496.0,127874.1] || -> node4(s20)*. % 76.16/76.32 128500[102:MRR:858.0,128498.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.32 128503[102:Res:53.1,128500.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.32 128505[103:Spt:128503.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 128507[103:Res:128505.0,61.1] always3(s20) || -> . % 76.16/76.32 128508[103:SSi:128507.0,78155.0,78159.0,108770.0,127873.0,128498.0] || -> . % 76.16/76.32 128509[103:Spt:128508.0,128503.0,128505.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.32 128510[103:Spt:128508.0,128503.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 128514[103:Res:128510.0,61.1] always3(s21) || -> . % 76.16/76.32 128515[103:SSi:128514.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.32 128516[101:Spt:128515.0,127872.0,127873.0] || until2p7(s20)*+ -> . % 76.16/76.32 128517[101:Spt:128515.0,127872.1] || -> node4(s19)*. % 76.16/76.32 128519[101:MRR:861.0,128517.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.32 128522[101:Res:53.1,128519.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.32 128524[102:Spt:128522.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 128526[102:Res:128524.0,61.1] always3(s19) || -> . % 76.16/76.32 128527[102:SSi:128526.0,78151.0,78154.0,108769.0,127871.0,128517.0] || -> . % 76.16/76.32 128528[102:Spt:128527.0,128522.0,128524.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.32 128529[102:Spt:128527.0,128522.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 128533[102:Res:128529.0,61.1] always3(s20) || -> . % 76.16/76.32 128534[102:SSi:128533.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.32 128535[100:Spt:128534.0,127870.0,127871.0] || until2p7(s19)*+ -> . % 76.16/76.32 128536[100:Spt:128534.0,127870.1] || -> node4(s18)*. % 76.16/76.32 128538[100:MRR:864.0,128536.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.32 128541[100:Res:53.1,128538.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.32 128546[101:Spt:128541.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 128548[101:Res:128546.0,61.1] always3(s18) || -> . % 76.16/76.32 128549[101:SSi:128548.0,78146.0,78150.0,108768.0,127869.0,128536.0] || -> . % 76.16/76.32 128550[101:Spt:128549.0,128541.0,128546.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.32 128551[101:Spt:128549.0,128541.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 128555[101:Res:128551.0,61.1] always3(s19) || -> . % 76.16/76.32 128556[101:SSi:128555.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.32 128557[99:Spt:128556.0,127868.0,127869.0] || until2p7(s18)*+ -> . % 76.16/76.32 128558[99:Spt:128556.0,127868.1] || -> node4(s17)*. % 76.16/76.32 128560[99:MRR:867.0,128558.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.32 128563[99:Res:53.1,128560.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.32 128565[100:Spt:128563.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 128567[100:Res:128565.0,61.1] always3(s17) || -> . % 76.16/76.32 128568[100:SSi:128567.0,78142.0,78145.0,108767.0,127867.0,128558.0] || -> . % 76.16/76.32 128569[100:Spt:128568.0,128563.0,128565.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.32 128570[100:Spt:128568.0,128563.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 128574[100:Res:128570.0,61.1] always3(s18) || -> . % 76.16/76.32 128575[100:SSi:128574.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.32 128576[98:Spt:128575.0,127866.0,127867.0] || until2p7(s17)*+ -> . % 76.16/76.32 128577[98:Spt:128575.0,127866.1] || -> node4(s16)*. % 76.16/76.32 128579[98:MRR:870.0,128577.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.32 128582[98:Res:53.1,128579.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.32 128584[99:Spt:128582.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.32 128586[99:Res:128584.0,61.1] always3(s16) || -> . % 76.16/76.32 128587[99:SSi:128586.0,78137.0,78141.0,108766.0,127865.0,128577.0] || -> . % 76.16/76.32 128588[99:Spt:128587.0,128582.0,128584.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.32 128589[99:Spt:128587.0,128582.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.32 128593[99:Res:128589.0,61.1] always3(s17) || -> . % 76.16/76.32 128594[99:SSi:128593.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.32 128595[97:Spt:128594.0,127864.0,127865.0] || until2p7(s16)*+ -> . % 76.16/76.32 128596[97:Spt:128594.0,127864.1] || -> node4(s15)*. % 76.16/76.32 128598[97:MRR:873.0,128596.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.32 128601[97:Res:53.1,128598.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.32 128603[98:Spt:128601.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.32 128605[98:Res:128603.0,61.1] always3(s15) || -> . % 76.16/76.32 128606[98:SSi:128605.0,78133.0,78136.0,108765.0,127863.0,128596.0] || -> . % 76.16/76.32 128607[98:Spt:128606.0,128601.0,128603.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.32 128608[98:Spt:128606.0,128601.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.32 128612[98:Res:128608.0,61.1] always3(s16) || -> . % 76.16/76.32 128613[98:SSi:128612.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.32 128614[96:Spt:128613.0,127862.0,127863.0] || until2p7(s15)*+ -> . % 76.16/76.32 128615[96:Spt:128613.0,127862.1] || -> node4(s14)*. % 76.16/76.32 128617[96:MRR:876.0,128615.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.32 128620[96:Res:53.1,128617.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.32 128625[97:Spt:128620.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.32 128627[97:Res:128625.0,61.1] always3(s14) || -> . % 76.16/76.32 128628[97:SSi:128627.0,78128.0,78132.0,108764.0,127861.0,128615.0] || -> . % 76.16/76.32 128629[97:Spt:128628.0,128620.0,128625.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.32 128630[97:Spt:128628.0,128620.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.32 128634[97:Res:128630.0,61.1] always3(s15) || -> . % 76.16/76.32 128635[97:SSi:128634.0,78133.0,78136.0,108765.0] || -> . % 76.16/76.32 128636[95:Spt:128635.0,127860.0,127861.0] || until2p7(s14)*+ -> . % 76.16/76.32 128637[95:Spt:128635.0,127860.1] || -> node4(s13)*. % 76.16/76.32 128639[95:MRR:879.0,128637.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.32 128642[95:Res:53.1,128639.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.32 128644[96:Spt:128642.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.32 128646[96:Res:128644.0,61.1] always3(s13) || -> . % 76.16/76.32 128647[96:SSi:128646.0,78124.0,78127.0,108763.0,127859.0,128637.0] || -> . % 76.16/76.32 128648[96:Spt:128647.0,128642.0,128644.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.32 128649[96:Spt:128647.0,128642.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.32 128653[96:Res:128649.0,61.1] always3(s14) || -> . % 76.16/76.32 128654[96:SSi:128653.0,78128.0,78132.0,108764.0] || -> . % 76.16/76.32 128655[94:Spt:128654.0,127858.0,127859.0] || until2p7(s13)*+ -> . % 76.16/76.32 128656[94:Spt:128654.0,127858.1] || -> node4(s12)*. % 76.16/76.32 128658[94:MRR:882.0,128656.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.32 128661[94:Res:53.1,128658.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.32 128663[95:Spt:128661.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.32 128665[95:Res:128663.0,61.1] always3(s12) || -> . % 76.16/76.32 128666[95:SSi:128665.0,78119.0,78123.0,108762.0,127857.0,128656.0] || -> . % 76.16/76.32 128667[95:Spt:128666.0,128661.0,128663.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.32 128668[95:Spt:128666.0,128661.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.32 128672[95:Res:128668.0,61.1] always3(s13) || -> . % 76.16/76.32 128673[95:SSi:128672.0,78124.0,78127.0,108763.0] || -> . % 76.16/76.32 128674[93:Spt:128673.0,127856.0,127857.0] || until2p7(s12)*+ -> . % 76.16/76.32 128675[93:Spt:128673.0,127856.1] || -> node4(s11)*. % 76.16/76.32 128677[93:MRR:885.0,128675.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.32 128680[93:Res:53.1,128677.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.32 128682[93:MRR:128680.0,127846.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.32 128684[93:Res:128682.0,61.1] always3(s12) || -> . % 76.16/76.32 128685[93:SSi:128684.0,78119.0,78123.0,108762.0] || -> . % 76.16/76.32 128686[91:Spt:128685.0,127705.0,127708.0] || trans(s49,s11)*+ -> . % 76.16/76.32 128687[91:Spt:128685.0,127705.1,127705.2,127705.3,127705.4,127705.5,127705.6,127705.7,127705.8] || -> trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.32 128689[91:MRR:127707.1,128686.0] xuntil6(s49) || -> trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.32 128690[92:Spt:128687.0] || -> trans(s49,s10)*. % 76.16/76.32 128691[92:Res:128690.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s10)*. % 76.16/76.32 128693[92:Res:128690.0,60.0] || -> node2(s49,s10)*. % 76.16/76.32 128694[92:SSi:128691.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s10)*. % 76.16/76.32 128695[92:Res:128693.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)*. % 76.16/76.32 128827[92:SoR:128695.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)*. % 76.16/76.32 128829[92:SoR:128827.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)* xuntil6(s49). % 76.16/76.32 128830[92:SSi:128829.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s10,c_busy)* xuntil6(s49). % 76.16/76.32 128831[93:Spt:128830.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.32 128833[93:Res:128831.0,61.1] always3(s10) || -> . % 76.16/76.32 128834[93:SSi:128833.0,78110.0,78114.0,108760.0] || -> . % 76.16/76.32 128835[93:Spt:128834.0,128830.1,128831.0] || m_main_v_state(s10,c_busy)*+ -> . % 76.16/76.32 128836[93:Spt:128834.0,128830.0,128830.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.32 128840[93:MRR:128827.2,128835.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.32 128841[93:Res:53.1,128836.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.32 128843[93:MRR:128841.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.32 128844[93:MRR:128694.0,128843.0] || -> until2p7(s10)*. % 76.16/76.32 128845[93:MRR:206.0,128844.0] || -> until2p7(s11)* node4(s10). % 76.16/76.32 128846[94:Spt:128845.0] || -> until2p7(s11)*. % 76.16/76.32 128847[94:MRR:207.0,128846.0] || -> until2p7(s12)* node4(s11). % 76.16/76.32 128848[95:Spt:128847.0] || -> until2p7(s12)*. % 76.16/76.32 128849[95:MRR:208.0,128848.0] || -> until2p7(s13)* node4(s12). % 76.16/76.32 128850[96:Spt:128849.0] || -> until2p7(s13)*. % 76.16/76.32 128851[96:MRR:209.0,128850.0] || -> until2p7(s14)* node4(s13). % 76.16/76.32 128852[97:Spt:128851.0] || -> until2p7(s14)*. % 76.16/76.32 128853[97:MRR:210.0,128852.0] || -> until2p7(s15)* node4(s14). % 76.16/76.32 128854[98:Spt:128853.0] || -> until2p7(s15)*. % 76.16/76.32 128855[98:MRR:211.0,128854.0] || -> until2p7(s16)* node4(s15). % 76.16/76.32 128856[99:Spt:128855.0] || -> until2p7(s16)*. % 76.16/76.32 128857[99:MRR:212.0,128856.0] || -> until2p7(s17)* node4(s16). % 76.16/76.32 128858[100:Spt:128857.0] || -> until2p7(s17)*. % 76.16/76.32 128859[100:MRR:213.0,128858.0] || -> until2p7(s18)* node4(s17). % 76.16/76.32 128860[101:Spt:128859.0] || -> until2p7(s18)*. % 76.16/76.32 128861[101:MRR:214.0,128860.0] || -> until2p7(s19)* node4(s18). % 76.16/76.32 128862[102:Spt:128861.0] || -> until2p7(s19)*. % 76.16/76.32 128863[102:MRR:215.0,128862.0] || -> until2p7(s20)* node4(s19). % 76.16/76.32 128864[103:Spt:128863.0] || -> until2p7(s20)*. % 76.16/76.32 128865[103:MRR:216.0,128864.0] || -> until2p7(s21)* node4(s20). % 76.16/76.32 128866[104:Spt:128865.0] || -> until2p7(s21)*. % 76.16/76.32 128867[104:MRR:217.0,128866.0] || -> until2p7(s22)* node4(s21). % 76.16/76.32 128868[105:Spt:128867.0] || -> until2p7(s22)*. % 76.16/76.32 128869[105:MRR:218.0,128868.0] || -> until2p7(s23)* node4(s22). % 76.16/76.32 128870[106:Spt:128869.0] || -> until2p7(s23)*. % 76.16/76.32 128871[106:MRR:219.0,128870.0] || -> until2p7(s24)* node4(s23). % 76.16/76.32 128872[107:Spt:128871.0] || -> until2p7(s24)*. % 76.16/76.32 128873[107:MRR:220.0,128872.0] || -> until2p7(s25)* node4(s24). % 76.16/76.32 128874[108:Spt:128873.0] || -> until2p7(s25)*. % 76.16/76.32 128875[108:MRR:221.0,128874.0] || -> until2p7(s26)* node4(s25). % 76.16/76.32 128876[109:Spt:128875.0] || -> until2p7(s26)*. % 76.16/76.32 128877[109:MRR:222.0,128876.0] || -> until2p7(s27)* node4(s26). % 76.16/76.32 128878[110:Spt:128877.0] || -> until2p7(s27)*. % 76.16/76.32 128879[110:MRR:223.0,128878.0] || -> until2p7(s28)* node4(s27). % 76.16/76.32 128880[111:Spt:128879.0] || -> until2p7(s28)*. % 76.16/76.32 128881[111:MRR:224.0,128880.0] || -> until2p7(s29)* node4(s28). % 76.16/76.32 128882[112:Spt:128881.0] || -> until2p7(s29)*. % 76.16/76.32 128883[112:MRR:225.0,128882.0] || -> until2p7(s30)* node4(s29). % 76.16/76.32 128884[113:Spt:128883.0] || -> until2p7(s30)*. % 76.16/76.32 128885[113:MRR:226.0,128884.0] || -> until2p7(s31)* node4(s30). % 76.16/76.32 128886[114:Spt:128885.0] || -> until2p7(s31)*. % 76.16/76.32 128887[114:MRR:227.0,128886.0] || -> until2p7(s32)* node4(s31). % 76.16/76.32 128888[115:Spt:128887.0] || -> until2p7(s32)*. % 76.16/76.32 128889[115:MRR:228.0,128888.0] || -> until2p7(s33)* node4(s32). % 76.16/76.32 128890[116:Spt:128889.0] || -> until2p7(s33)*. % 76.16/76.32 128891[116:MRR:229.0,128890.0] || -> until2p7(s34)* node4(s33). % 76.16/76.32 128892[117:Spt:128891.0] || -> until2p7(s34)*. % 76.16/76.32 128893[117:MRR:230.0,128892.0] || -> until2p7(s35)* node4(s34). % 76.16/76.32 128894[118:Spt:128893.0] || -> until2p7(s35)*. % 76.16/76.32 128895[118:MRR:231.0,128894.0] || -> until2p7(s36)* node4(s35). % 76.16/76.32 128896[119:Spt:128895.0] || -> until2p7(s36)*. % 76.16/76.32 128897[119:MRR:232.0,128896.0] || -> until2p7(s37)* node4(s36). % 76.16/76.32 128898[120:Spt:128897.0] || -> until2p7(s37)*. % 76.16/76.32 128899[120:MRR:235.0,128898.0] || -> until2p7(s38)* node4(s37). % 76.16/76.32 128900[121:Spt:128899.0] || -> until2p7(s38)*. % 76.16/76.32 128901[121:MRR:236.0,128900.0] || -> until2p7(s39)* node4(s38). % 76.16/76.32 128902[122:Spt:128901.0] || -> until2p7(s39)*. % 76.16/76.32 128903[122:MRR:237.0,128902.0] || -> until2p7(s40)* node4(s39). % 76.16/76.32 128904[123:Spt:128903.0] || -> until2p7(s40)*. % 76.16/76.32 128905[123:MRR:238.0,128904.0] || -> until2p7(s41)* node4(s40). % 76.16/76.32 128906[124:Spt:128905.0] || -> until2p7(s41)*. % 76.16/76.32 128907[124:MRR:239.0,128906.0] || -> until2p7(s42)* node4(s41). % 76.16/76.32 128908[125:Spt:128907.0] || -> until2p7(s42)*. % 76.16/76.32 128909[125:MRR:240.0,128908.0] || -> until2p7(s43)* node4(s42). % 76.16/76.32 128910[126:Spt:128909.0] || -> until2p7(s43)*. % 76.16/76.32 128911[126:MRR:241.0,128910.0] || -> until2p7(s44)* node4(s43). % 76.16/76.32 128912[127:Spt:128911.0] || -> until2p7(s44)*. % 76.16/76.32 128913[127:MRR:539.0,128912.0] || -> until2p7(s45)* node4(s44). % 76.16/76.32 128914[128:Spt:128913.0] || -> until2p7(s45)*. % 76.16/76.32 128915[128:MRR:544.0,128914.0] || -> until2p7(s46)* node4(s45). % 76.16/76.32 128916[129:Spt:128915.0] || -> until2p7(s46)*. % 76.16/76.32 128917[129:MRR:549.0,128916.0] || -> until2p7(s47)* node4(s46). % 76.16/76.32 128918[130:Spt:128917.0] || -> until2p7(s47)*. % 76.16/76.32 128919[130:MRR:554.0,128918.0] || -> until2p7(s48)* node4(s47). % 76.16/76.32 128920[131:Spt:128919.0] || -> until2p7(s48)*. % 76.16/76.32 128921[131:MRR:559.0,128920.0] || -> until2p7(s49)* node4(s48). % 76.16/76.32 128922[132:Spt:128921.0] || -> until2p7(s49)*. % 76.16/76.32 128923[132:MRR:194.0,128922.0] || -> node4(s49)*. % 76.16/76.32 128924[132:MRR:128840.0,128923.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.32 128925[132:Res:53.1,128924.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.32 128927[132:MRR:128925.0,78381.0] || -> . % 76.16/76.32 128928[132:Spt:128927.0,128921.0,128922.0] || until2p7(s49)*+ -> . % 76.16/76.32 128929[132:Spt:128927.0,128921.1] || -> node4(s48)*. % 76.16/76.32 128930[132:MRR:78384.0,128929.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.32 128933[132:Res:53.1,128930.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 128936[132:Res:128933.0,61.1] always3(s48) || -> . % 76.16/76.32 128937[132:SSi:128936.0,78281.0,78387.0,108798.0,128920.0,128929.0] || -> . % 76.16/76.32 128938[131:Spt:128937.0,128919.0,128920.0] || until2p7(s48)*+ -> . % 76.16/76.32 128939[131:Spt:128937.0,128919.1] || -> node4(s47)*. % 76.16/76.32 128941[131:MRR:777.0,128939.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.32 128956[131:Res:53.1,128941.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.32 128958[132:Spt:128956.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 128960[132:Res:128958.0,61.1] always3(s47) || -> . % 76.16/76.32 128961[132:SSi:128960.0,78277.0,78280.0,108797.0,128918.0,128939.0] || -> . % 76.16/76.32 128962[132:Spt:128961.0,128956.0,128958.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.32 128963[132:Spt:128961.0,128956.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.32 128967[132:Res:128963.0,61.1] always3(s48) || -> . % 76.16/76.32 128968[132:SSi:128967.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.32 128969[130:Spt:128968.0,128917.0,128918.0] || until2p7(s47)*+ -> . % 76.16/76.32 128970[130:Spt:128968.0,128917.1] || -> node4(s46)*. % 76.16/76.32 128972[130:MRR:780.0,128970.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.32 128982[130:Res:53.1,128972.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.32 128984[131:Spt:128982.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 128986[131:Res:128984.0,61.1] always3(s46) || -> . % 76.16/76.32 128987[131:SSi:128986.0,78272.0,78276.0,108796.0,128916.0,128970.0] || -> . % 76.16/76.32 128988[131:Spt:128987.0,128982.0,128984.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.32 128989[131:Spt:128987.0,128982.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.32 128993[131:Res:128989.0,61.1] always3(s47) || -> . % 76.16/76.32 128994[131:SSi:128993.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.32 128995[129:Spt:128994.0,128915.0,128916.0] || until2p7(s46)*+ -> . % 76.16/76.32 128996[129:Spt:128994.0,128915.1] || -> node4(s45)*. % 76.16/76.32 128998[129:MRR:783.0,128996.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.32 129001[129:Res:53.1,128998.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.32 129003[130:Spt:129001.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 129005[130:Res:129003.0,61.1] always3(s45) || -> . % 76.16/76.32 129006[130:SSi:129005.0,78268.0,78271.0,108795.0,128914.0,128996.0] || -> . % 76.16/76.32 129007[130:Spt:129006.0,129001.0,129003.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.32 129008[130:Spt:129006.0,129001.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.32 129012[130:Res:129008.0,61.1] always3(s46) || -> . % 76.16/76.32 129013[130:SSi:129012.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.32 129014[128:Spt:129013.0,128913.0,128914.0] || until2p7(s45)*+ -> . % 76.16/76.32 129015[128:Spt:129013.0,128913.1] || -> node4(s44)*. % 76.16/76.32 129017[128:MRR:786.0,129015.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.32 129020[128:Res:53.1,129017.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.32 129022[129:Spt:129020.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 129024[129:Res:129022.0,61.1] always3(s44) || -> . % 76.16/76.32 129025[129:SSi:129024.0,78263.0,78267.0,108794.0,128912.0,129015.0] || -> . % 76.16/76.32 129026[129:Spt:129025.0,129020.0,129022.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.32 129027[129:Spt:129025.0,129020.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.32 129031[129:Res:129027.0,61.1] always3(s45) || -> . % 76.16/76.32 129032[129:SSi:129031.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.32 129033[127:Spt:129032.0,128911.0,128912.0] || until2p7(s44)*+ -> . % 76.16/76.32 129034[127:Spt:129032.0,128911.1] || -> node4(s43)*. % 76.16/76.32 129036[127:MRR:789.0,129034.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.32 129039[127:Res:53.1,129036.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.32 129044[128:Spt:129039.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 129046[128:Res:129044.0,61.1] always3(s43) || -> . % 76.16/76.32 129047[128:SSi:129046.0,78259.0,78262.0,108793.0,128910.0,129034.0] || -> . % 76.16/76.32 129048[128:Spt:129047.0,129039.0,129044.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.32 129049[128:Spt:129047.0,129039.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.32 129053[128:Res:129049.0,61.1] always3(s44) || -> . % 76.16/76.32 129054[128:SSi:129053.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.32 129055[126:Spt:129054.0,128909.0,128910.0] || until2p7(s43)*+ -> . % 76.16/76.32 129056[126:Spt:129054.0,128909.1] || -> node4(s42)*. % 76.16/76.32 129058[126:MRR:792.0,129056.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.32 129061[126:Res:53.1,129058.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.32 129063[127:Spt:129061.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 129065[127:Res:129063.0,61.1] always3(s42) || -> . % 76.16/76.32 129066[127:SSi:129065.0,78254.0,78258.0,108792.0,128908.0,129056.0] || -> . % 76.16/76.32 129067[127:Spt:129066.0,129061.0,129063.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.32 129068[127:Spt:129066.0,129061.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.32 129072[127:Res:129068.0,61.1] always3(s43) || -> . % 76.16/76.32 129073[127:SSi:129072.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.32 129074[125:Spt:129073.0,128907.0,128908.0] || until2p7(s42)*+ -> . % 76.16/76.32 129075[125:Spt:129073.0,128907.1] || -> node4(s41)*. % 76.16/76.32 129077[125:MRR:795.0,129075.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.32 129080[125:Res:53.1,129077.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.32 129082[126:Spt:129080.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 129084[126:Res:129082.0,61.1] always3(s41) || -> . % 76.16/76.32 129085[126:SSi:129084.0,78250.0,78253.0,108791.0,128906.0,129075.0] || -> . % 76.16/76.32 129086[126:Spt:129085.0,129080.0,129082.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.32 129087[126:Spt:129085.0,129080.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.32 129091[126:Res:129087.0,61.1] always3(s42) || -> . % 76.16/76.32 129092[126:SSi:129091.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.32 129093[124:Spt:129092.0,128905.0,128906.0] || until2p7(s41)*+ -> . % 76.16/76.32 129094[124:Spt:129092.0,128905.1] || -> node4(s40)*. % 76.16/76.32 129096[124:MRR:798.0,129094.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.32 129099[124:Res:53.1,129096.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.32 129101[125:Spt:129099.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 129103[125:Res:129101.0,61.1] always3(s40) || -> . % 76.16/76.32 129104[125:SSi:129103.0,78245.0,78249.0,108790.0,128904.0,129094.0] || -> . % 76.16/76.32 129105[125:Spt:129104.0,129099.0,129101.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.32 129106[125:Spt:129104.0,129099.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.32 129110[125:Res:129106.0,61.1] always3(s41) || -> . % 76.16/76.32 129111[125:SSi:129110.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.32 129112[123:Spt:129111.0,128903.0,128904.0] || until2p7(s40)*+ -> . % 76.16/76.32 129113[123:Spt:129111.0,128903.1] || -> node4(s39)*. % 76.16/76.32 129115[123:MRR:801.0,129113.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.32 129118[123:Res:53.1,129115.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.32 129123[124:Spt:129118.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 129125[124:Res:129123.0,61.1] always3(s39) || -> . % 76.16/76.32 129126[124:SSi:129125.0,78241.0,78244.0,108789.0,128902.0,129113.0] || -> . % 76.16/76.32 129127[124:Spt:129126.0,129118.0,129123.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.32 129128[124:Spt:129126.0,129118.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.32 129132[124:Res:129128.0,61.1] always3(s40) || -> . % 76.16/76.32 129133[124:SSi:129132.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.32 129134[122:Spt:129133.0,128901.0,128902.0] || until2p7(s39)*+ -> . % 76.16/76.32 129135[122:Spt:129133.0,128901.1] || -> node4(s38)*. % 76.16/76.32 129137[122:MRR:804.0,129135.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.32 129140[122:Res:53.1,129137.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.32 129142[123:Spt:129140.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 129144[123:Res:129142.0,61.1] always3(s38) || -> . % 76.16/76.32 129145[123:SSi:129144.0,78236.0,78240.0,108788.0,128900.0,129135.0] || -> . % 76.16/76.32 129146[123:Spt:129145.0,129140.0,129142.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.32 129147[123:Spt:129145.0,129140.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.32 129151[123:Res:129147.0,61.1] always3(s39) || -> . % 76.16/76.32 129152[123:SSi:129151.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.32 129153[121:Spt:129152.0,128899.0,128900.0] || until2p7(s38)*+ -> . % 76.16/76.32 129154[121:Spt:129152.0,128899.1] || -> node4(s37)*. % 76.16/76.32 129156[121:MRR:807.0,129154.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.32 129159[121:Res:53.1,129156.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.32 129161[122:Spt:129159.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 129163[122:Res:129161.0,61.1] always3(s37) || -> . % 76.16/76.32 129164[122:SSi:129163.0,78232.0,78235.0,108787.0,128898.0,129154.0] || -> . % 76.16/76.32 129165[122:Spt:129164.0,129159.0,129161.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.32 129166[122:Spt:129164.0,129159.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.32 129170[122:Res:129166.0,61.1] always3(s38) || -> . % 76.16/76.32 129171[122:SSi:129170.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.32 129172[120:Spt:129171.0,128897.0,128898.0] || until2p7(s37)*+ -> . % 76.16/76.32 129173[120:Spt:129171.0,128897.1] || -> node4(s36)*. % 76.16/76.32 129175[120:MRR:810.0,129173.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.32 129178[120:Res:53.1,129175.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.32 129180[121:Spt:129178.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 129182[121:Res:129180.0,61.1] always3(s36) || -> . % 76.16/76.32 129183[121:SSi:129182.0,78227.0,78231.0,108786.0,128896.0,129173.0] || -> . % 76.16/76.32 129184[121:Spt:129183.0,129178.0,129180.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.32 129185[121:Spt:129183.0,129178.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.32 129189[121:Res:129185.0,61.1] always3(s37) || -> . % 76.16/76.32 129190[121:SSi:129189.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.32 129191[119:Spt:129190.0,128895.0,128896.0] || until2p7(s36)*+ -> . % 76.16/76.32 129192[119:Spt:129190.0,128895.1] || -> node4(s35)*. % 76.16/76.32 129194[119:MRR:813.0,129192.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.32 129197[119:Res:53.1,129194.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.32 129202[120:Spt:129197.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 129204[120:Res:129202.0,61.1] always3(s35) || -> . % 76.16/76.32 129205[120:SSi:129204.0,78223.0,78226.0,108785.0,128894.0,129192.0] || -> . % 76.16/76.32 129206[120:Spt:129205.0,129197.0,129202.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.32 129207[120:Spt:129205.0,129197.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.32 129211[120:Res:129207.0,61.1] always3(s36) || -> . % 76.16/76.32 129212[120:SSi:129211.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.32 129213[118:Spt:129212.0,128893.0,128894.0] || until2p7(s35)*+ -> . % 76.16/76.32 129214[118:Spt:129212.0,128893.1] || -> node4(s34)*. % 76.16/76.32 129216[118:MRR:816.0,129214.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.32 129219[118:Res:53.1,129216.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.32 129221[119:Spt:129219.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 129223[119:Res:129221.0,61.1] always3(s34) || -> . % 76.16/76.32 129224[119:SSi:129223.0,78218.0,78222.0,108784.0,128892.0,129214.0] || -> . % 76.16/76.32 129225[119:Spt:129224.0,129219.0,129221.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.32 129226[119:Spt:129224.0,129219.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.32 129230[119:Res:129226.0,61.1] always3(s35) || -> . % 76.16/76.32 129231[119:SSi:129230.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.32 129232[117:Spt:129231.0,128891.0,128892.0] || until2p7(s34)*+ -> . % 76.16/76.32 129233[117:Spt:129231.0,128891.1] || -> node4(s33)*. % 76.16/76.32 129235[117:MRR:819.0,129233.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.32 129238[117:Res:53.1,129235.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.32 129240[118:Spt:129238.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 129242[118:Res:129240.0,61.1] always3(s33) || -> . % 76.16/76.32 129243[118:SSi:129242.0,78214.0,78217.0,108783.0,128890.0,129233.0] || -> . % 76.16/76.32 129244[118:Spt:129243.0,129238.0,129240.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.32 129245[118:Spt:129243.0,129238.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.32 129249[118:Res:129245.0,61.1] always3(s34) || -> . % 76.16/76.32 129250[118:SSi:129249.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.32 129251[116:Spt:129250.0,128889.0,128890.0] || until2p7(s33)*+ -> . % 76.16/76.32 129252[116:Spt:129250.0,128889.1] || -> node4(s32)*. % 76.16/76.32 129254[116:MRR:822.0,129252.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.32 129257[116:Res:53.1,129254.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.32 129259[117:Spt:129257.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 129261[117:Res:129259.0,61.1] always3(s32) || -> . % 76.16/76.32 129262[117:SSi:129261.0,78209.0,78213.0,108782.0,128888.0,129252.0] || -> . % 76.16/76.32 129263[117:Spt:129262.0,129257.0,129259.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.32 129264[117:Spt:129262.0,129257.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.32 129268[117:Res:129264.0,61.1] always3(s33) || -> . % 76.16/76.32 129269[117:SSi:129268.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.32 129270[115:Spt:129269.0,128887.0,128888.0] || until2p7(s32)*+ -> . % 76.16/76.32 129271[115:Spt:129269.0,128887.1] || -> node4(s31)*. % 76.16/76.32 129273[115:MRR:825.0,129271.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.32 129276[115:Res:53.1,129273.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.32 129281[116:Spt:129276.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 129283[116:Res:129281.0,61.1] always3(s31) || -> . % 76.16/76.32 129284[116:SSi:129283.0,78205.0,78208.0,108781.0,128886.0,129271.0] || -> . % 76.16/76.32 129285[116:Spt:129284.0,129276.0,129281.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.32 129286[116:Spt:129284.0,129276.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.32 129290[116:Res:129286.0,61.1] always3(s32) || -> . % 76.16/76.32 129291[116:SSi:129290.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.32 129292[114:Spt:129291.0,128885.0,128886.0] || until2p7(s31)*+ -> . % 76.16/76.32 129293[114:Spt:129291.0,128885.1] || -> node4(s30)*. % 76.16/76.32 129295[114:MRR:828.0,129293.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.32 129298[114:Res:53.1,129295.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.32 129300[115:Spt:129298.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 129302[115:Res:129300.0,61.1] always3(s30) || -> . % 76.16/76.32 129303[115:SSi:129302.0,78200.0,78204.0,108780.0,128884.0,129293.0] || -> . % 76.16/76.32 129304[115:Spt:129303.0,129298.0,129300.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.32 129305[115:Spt:129303.0,129298.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.32 129309[115:Res:129305.0,61.1] always3(s31) || -> . % 76.16/76.32 129310[115:SSi:129309.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.32 129311[113:Spt:129310.0,128883.0,128884.0] || until2p7(s30)*+ -> . % 76.16/76.32 129312[113:Spt:129310.0,128883.1] || -> node4(s29)*. % 76.16/76.32 129314[113:MRR:831.0,129312.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.32 129317[113:Res:53.1,129314.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.32 129319[114:Spt:129317.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 129321[114:Res:129319.0,61.1] always3(s29) || -> . % 76.16/76.32 129322[114:SSi:129321.0,78196.0,78199.0,108779.0,128882.0,129312.0] || -> . % 76.16/76.32 129323[114:Spt:129322.0,129317.0,129319.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.32 129324[114:Spt:129322.0,129317.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.32 129328[114:Res:129324.0,61.1] always3(s30) || -> . % 76.16/76.32 129329[114:SSi:129328.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.32 129330[112:Spt:129329.0,128881.0,128882.0] || until2p7(s29)*+ -> . % 76.16/76.32 129331[112:Spt:129329.0,128881.1] || -> node4(s28)*. % 76.16/76.32 129333[112:MRR:834.0,129331.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.32 129336[112:Res:53.1,129333.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.32 129338[113:Spt:129336.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 129340[113:Res:129338.0,61.1] always3(s28) || -> . % 76.16/76.32 129341[113:SSi:129340.0,78191.0,78195.0,108778.0,128880.0,129331.0] || -> . % 76.16/76.32 129342[113:Spt:129341.0,129336.0,129338.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.32 129343[113:Spt:129341.0,129336.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.32 129347[113:Res:129343.0,61.1] always3(s29) || -> . % 76.16/76.32 129348[113:SSi:129347.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.32 129349[111:Spt:129348.0,128879.0,128880.0] || until2p7(s28)*+ -> . % 76.16/76.32 129350[111:Spt:129348.0,128879.1] || -> node4(s27)*. % 76.16/76.32 129352[111:MRR:837.0,129350.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.32 129355[111:Res:53.1,129352.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.32 129360[112:Spt:129355.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 129362[112:Res:129360.0,61.1] always3(s27) || -> . % 76.16/76.32 129363[112:SSi:129362.0,78187.0,78190.0,108777.0,128878.0,129350.0] || -> . % 76.16/76.32 129364[112:Spt:129363.0,129355.0,129360.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.32 129365[112:Spt:129363.0,129355.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.32 129369[112:Res:129365.0,61.1] always3(s28) || -> . % 76.16/76.32 129370[112:SSi:129369.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.32 129371[110:Spt:129370.0,128877.0,128878.0] || until2p7(s27)*+ -> . % 76.16/76.32 129372[110:Spt:129370.0,128877.1] || -> node4(s26)*. % 76.16/76.32 129374[110:MRR:840.0,129372.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.32 129377[110:Res:53.1,129374.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.32 129379[111:Spt:129377.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 129381[111:Res:129379.0,61.1] always3(s26) || -> . % 76.16/76.32 129382[111:SSi:129381.0,78182.0,78186.0,108776.0,128876.0,129372.0] || -> . % 76.16/76.32 129383[111:Spt:129382.0,129377.0,129379.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.32 129384[111:Spt:129382.0,129377.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.32 129388[111:Res:129384.0,61.1] always3(s27) || -> . % 76.16/76.32 129389[111:SSi:129388.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.32 129390[109:Spt:129389.0,128875.0,128876.0] || until2p7(s26)*+ -> . % 76.16/76.32 129391[109:Spt:129389.0,128875.1] || -> node4(s25)*. % 76.16/76.32 129393[109:MRR:843.0,129391.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.32 129396[109:Res:53.1,129393.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.32 129398[110:Spt:129396.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 129400[110:Res:129398.0,61.1] always3(s25) || -> . % 76.16/76.32 129401[110:SSi:129400.0,78178.0,78181.0,108775.0,128874.0,129391.0] || -> . % 76.16/76.32 129402[110:Spt:129401.0,129396.0,129398.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.32 129403[110:Spt:129401.0,129396.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.32 129407[110:Res:129403.0,61.1] always3(s26) || -> . % 76.16/76.32 129408[110:SSi:129407.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.32 129409[108:Spt:129408.0,128873.0,128874.0] || until2p7(s25)*+ -> . % 76.16/76.32 129410[108:Spt:129408.0,128873.1] || -> node4(s24)*. % 76.16/76.32 129412[108:MRR:846.0,129410.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.32 129415[108:Res:53.1,129412.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.32 129417[109:Spt:129415.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 129419[109:Res:129417.0,61.1] always3(s24) || -> . % 76.16/76.32 129420[109:SSi:129419.0,78173.0,78177.0,108774.0,128872.0,129410.0] || -> . % 76.16/76.32 129421[109:Spt:129420.0,129415.0,129417.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.32 129422[109:Spt:129420.0,129415.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.32 129426[109:Res:129422.0,61.1] always3(s25) || -> . % 76.16/76.32 129427[109:SSi:129426.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.32 129428[107:Spt:129427.0,128871.0,128872.0] || until2p7(s24)*+ -> . % 76.16/76.32 129429[107:Spt:129427.0,128871.1] || -> node4(s23)*. % 76.16/76.32 129431[107:MRR:849.0,129429.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.32 129434[107:Res:53.1,129431.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.32 129439[108:Spt:129434.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 129441[108:Res:129439.0,61.1] always3(s23) || -> . % 76.16/76.32 129442[108:SSi:129441.0,78169.0,78172.0,108773.0,128870.0,129429.0] || -> . % 76.16/76.32 129443[108:Spt:129442.0,129434.0,129439.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.32 129444[108:Spt:129442.0,129434.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.32 129448[108:Res:129444.0,61.1] always3(s24) || -> . % 76.16/76.32 129449[108:SSi:129448.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.32 129450[106:Spt:129449.0,128869.0,128870.0] || until2p7(s23)*+ -> . % 76.16/76.32 129451[106:Spt:129449.0,128869.1] || -> node4(s22)*. % 76.16/76.32 129453[106:MRR:852.0,129451.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.32 129456[106:Res:53.1,129453.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.32 129458[107:Spt:129456.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 129460[107:Res:129458.0,61.1] always3(s22) || -> . % 76.16/76.32 129461[107:SSi:129460.0,78164.0,78168.0,108772.0,128868.0,129451.0] || -> . % 76.16/76.32 129462[107:Spt:129461.0,129456.0,129458.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.32 129463[107:Spt:129461.0,129456.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.32 129467[107:Res:129463.0,61.1] always3(s23) || -> . % 76.16/76.32 129468[107:SSi:129467.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.32 129469[105:Spt:129468.0,128867.0,128868.0] || until2p7(s22)*+ -> . % 76.16/76.32 129470[105:Spt:129468.0,128867.1] || -> node4(s21)*. % 76.16/76.32 129472[105:MRR:855.0,129470.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.32 129475[105:Res:53.1,129472.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.32 129477[106:Spt:129475.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 129479[106:Res:129477.0,61.1] always3(s21) || -> . % 76.16/76.32 129480[106:SSi:129479.0,78160.0,78163.0,108771.0,128866.0,129470.0] || -> . % 76.16/76.32 129481[106:Spt:129480.0,129475.0,129477.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.32 129482[106:Spt:129480.0,129475.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.32 129486[106:Res:129482.0,61.1] always3(s22) || -> . % 76.16/76.32 129487[106:SSi:129486.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.32 129488[104:Spt:129487.0,128865.0,128866.0] || until2p7(s21)*+ -> . % 76.16/76.32 129489[104:Spt:129487.0,128865.1] || -> node4(s20)*. % 76.16/76.32 129491[104:MRR:858.0,129489.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.32 129494[104:Res:53.1,129491.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.32 129496[105:Spt:129494.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 129498[105:Res:129496.0,61.1] always3(s20) || -> . % 76.16/76.32 129499[105:SSi:129498.0,78155.0,78159.0,108770.0,128864.0,129489.0] || -> . % 76.16/76.32 129500[105:Spt:129499.0,129494.0,129496.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.32 129501[105:Spt:129499.0,129494.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.32 129505[105:Res:129501.0,61.1] always3(s21) || -> . % 76.16/76.32 129506[105:SSi:129505.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.32 129507[103:Spt:129506.0,128863.0,128864.0] || until2p7(s20)*+ -> . % 76.16/76.32 129508[103:Spt:129506.0,128863.1] || -> node4(s19)*. % 76.16/76.32 129510[103:MRR:861.0,129508.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.32 129513[103:Res:53.1,129510.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.32 129518[104:Spt:129513.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.32 129520[104:Res:129518.0,61.1] always3(s19) || -> . % 76.16/76.32 129521[104:SSi:129520.0,78151.0,78154.0,108769.0,128862.0,129508.0] || -> . % 76.16/76.32 129522[104:Spt:129521.0,129513.0,129518.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.32 129523[104:Spt:129521.0,129513.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.32 129527[104:Res:129523.0,61.1] always3(s20) || -> . % 76.16/76.32 129528[104:SSi:129527.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.32 129529[102:Spt:129528.0,128861.0,128862.0] || until2p7(s19)*+ -> . % 76.16/76.32 129530[102:Spt:129528.0,128861.1] || -> node4(s18)*. % 76.16/76.32 129532[102:MRR:864.0,129530.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.32 129535[102:Res:53.1,129532.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.32 129537[103:Spt:129535.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.32 129539[103:Res:129537.0,61.1] always3(s18) || -> . % 76.16/76.32 129540[103:SSi:129539.0,78146.0,78150.0,108768.0,128860.0,129530.0] || -> . % 76.16/76.33 129541[103:Spt:129540.0,129535.0,129537.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.33 129542[103:Spt:129540.0,129535.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 129546[103:Res:129542.0,61.1] always3(s19) || -> . % 76.16/76.33 129547[103:SSi:129546.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.33 129548[101:Spt:129547.0,128859.0,128860.0] || until2p7(s18)*+ -> . % 76.16/76.33 129549[101:Spt:129547.0,128859.1] || -> node4(s17)*. % 76.16/76.33 129551[101:MRR:867.0,129549.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.33 129554[101:Res:53.1,129551.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.33 129556[102:Spt:129554.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 129558[102:Res:129556.0,61.1] always3(s17) || -> . % 76.16/76.33 129559[102:SSi:129558.0,78142.0,78145.0,108767.0,128858.0,129549.0] || -> . % 76.16/76.33 129560[102:Spt:129559.0,129554.0,129556.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.33 129561[102:Spt:129559.0,129554.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 129565[102:Res:129561.0,61.1] always3(s18) || -> . % 76.16/76.33 129566[102:SSi:129565.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.33 129567[100:Spt:129566.0,128857.0,128858.0] || until2p7(s17)*+ -> . % 76.16/76.33 129568[100:Spt:129566.0,128857.1] || -> node4(s16)*. % 76.16/76.33 129570[100:MRR:870.0,129568.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.33 129573[100:Res:53.1,129570.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.33 129575[101:Spt:129573.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 129577[101:Res:129575.0,61.1] always3(s16) || -> . % 76.16/76.33 129578[101:SSi:129577.0,78137.0,78141.0,108766.0,128856.0,129568.0] || -> . % 76.16/76.33 129579[101:Spt:129578.0,129573.0,129575.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.33 129580[101:Spt:129578.0,129573.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 129584[101:Res:129580.0,61.1] always3(s17) || -> . % 76.16/76.33 129585[101:SSi:129584.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.33 129586[99:Spt:129585.0,128855.0,128856.0] || until2p7(s16)*+ -> . % 76.16/76.33 129587[99:Spt:129585.0,128855.1] || -> node4(s15)*. % 76.16/76.33 129589[99:MRR:873.0,129587.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.33 129592[99:Res:53.1,129589.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.33 129597[100:Spt:129592.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 129599[100:Res:129597.0,61.1] always3(s15) || -> . % 76.16/76.33 129600[100:SSi:129599.0,78133.0,78136.0,108765.0,128854.0,129587.0] || -> . % 76.16/76.33 129601[100:Spt:129600.0,129592.0,129597.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.33 129602[100:Spt:129600.0,129592.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 129606[100:Res:129602.0,61.1] always3(s16) || -> . % 76.16/76.33 129607[100:SSi:129606.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.33 129608[98:Spt:129607.0,128853.0,128854.0] || until2p7(s15)*+ -> . % 76.16/76.33 129609[98:Spt:129607.0,128853.1] || -> node4(s14)*. % 76.16/76.33 129611[98:MRR:876.0,129609.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.33 129614[98:Res:53.1,129611.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.33 129616[99:Spt:129614.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 129618[99:Res:129616.0,61.1] always3(s14) || -> . % 76.16/76.33 129619[99:SSi:129618.0,78128.0,78132.0,108764.0,128852.0,129609.0] || -> . % 76.16/76.33 129620[99:Spt:129619.0,129614.0,129616.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.33 129621[99:Spt:129619.0,129614.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 129625[99:Res:129621.0,61.1] always3(s15) || -> . % 76.16/76.33 129626[99:SSi:129625.0,78133.0,78136.0,108765.0] || -> . % 76.16/76.33 129627[97:Spt:129626.0,128851.0,128852.0] || until2p7(s14)*+ -> . % 76.16/76.33 129628[97:Spt:129626.0,128851.1] || -> node4(s13)*. % 76.16/76.33 129630[97:MRR:879.0,129628.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.33 129633[97:Res:53.1,129630.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.33 129635[98:Spt:129633.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 129637[98:Res:129635.0,61.1] always3(s13) || -> . % 76.16/76.33 129638[98:SSi:129637.0,78124.0,78127.0,108763.0,128850.0,129628.0] || -> . % 76.16/76.33 129639[98:Spt:129638.0,129633.0,129635.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.33 129640[98:Spt:129638.0,129633.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 129644[98:Res:129640.0,61.1] always3(s14) || -> . % 76.16/76.33 129645[98:SSi:129644.0,78128.0,78132.0,108764.0] || -> . % 76.16/76.33 129646[96:Spt:129645.0,128849.0,128850.0] || until2p7(s13)*+ -> . % 76.16/76.33 129647[96:Spt:129645.0,128849.1] || -> node4(s12)*. % 76.16/76.33 129649[96:MRR:882.0,129647.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.33 129652[96:Res:53.1,129649.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.33 129654[97:Spt:129652.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 129656[97:Res:129654.0,61.1] always3(s12) || -> . % 76.16/76.33 129657[97:SSi:129656.0,78119.0,78123.0,108762.0,128848.0,129647.0] || -> . % 76.16/76.33 129658[97:Spt:129657.0,129652.0,129654.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.33 129659[97:Spt:129657.0,129652.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 129663[97:Res:129659.0,61.1] always3(s13) || -> . % 76.16/76.33 129664[97:SSi:129663.0,78124.0,78127.0,108763.0] || -> . % 76.16/76.33 129665[95:Spt:129664.0,128847.0,128848.0] || until2p7(s12)*+ -> . % 76.16/76.33 129666[95:Spt:129664.0,128847.1] || -> node4(s11)*. % 76.16/76.33 129668[95:MRR:885.0,129666.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.33 129671[95:Res:53.1,129668.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.33 129676[96:Spt:129671.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 129678[96:Res:129676.0,61.1] always3(s11) || -> . % 76.16/76.33 129679[96:SSi:129678.0,78115.0,78118.0,108761.0,128846.0,129666.0] || -> . % 76.16/76.33 129680[96:Spt:129679.0,129671.0,129676.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.33 129681[96:Spt:129679.0,129671.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 129685[96:Res:129681.0,61.1] always3(s12) || -> . % 76.16/76.33 129686[96:SSi:129685.0,78119.0,78123.0,108762.0] || -> . % 76.16/76.33 129687[94:Spt:129686.0,128845.0,128846.0] || until2p7(s11)*+ -> . % 76.16/76.33 129688[94:Spt:129686.0,128845.1] || -> node4(s10)*. % 76.16/76.33 129690[94:MRR:888.0,129688.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.33 129693[94:Res:53.1,129690.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.33 129695[94:MRR:129693.0,128835.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 129697[94:Res:129695.0,61.1] always3(s11) || -> . % 76.16/76.33 129698[94:SSi:129697.0,78115.0,78118.0,108761.0] || -> . % 76.16/76.33 129699[92:Spt:129698.0,128687.0,128690.0] || trans(s49,s10)*+ -> . % 76.16/76.33 129700[92:Spt:129698.0,128687.1,128687.2,128687.3,128687.4,128687.5,128687.6,128687.7] || -> trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.33 129702[92:MRR:128689.1,129699.0] xuntil6(s49) || -> trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.33 129703[93:Spt:129700.0] || -> trans(s49,s9)*. % 76.16/76.33 129704[93:Res:129703.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s9)*. % 76.16/76.33 129706[93:Res:129703.0,60.0] || -> node2(s49,s9)*. % 76.16/76.33 129707[93:SSi:129704.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s9)*. % 76.16/76.33 129708[93:Res:129706.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 129841[93:SoR:129708.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 129843[93:SoR:129841.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)* xuntil6(s49). % 76.16/76.33 129844[93:SSi:129843.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s9,c_busy)* xuntil6(s49). % 76.16/76.33 129845[94:Spt:129844.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 129847[94:Res:129845.0,61.1] always3(s9) || -> . % 76.16/76.33 129848[94:SSi:129847.0,78106.0,78109.0,108759.0] || -> . % 76.16/76.33 129849[94:Spt:129848.0,129844.1,129845.0] || m_main_v_state(s9,c_busy)*+ -> . % 76.16/76.33 129850[94:Spt:129848.0,129844.0,129844.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 129854[94:MRR:129841.2,129849.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 129855[94:Res:53.1,129850.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 129857[94:MRR:129855.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 129858[94:MRR:129707.0,129857.0] || -> until2p7(s9)*. % 76.16/76.33 129859[94:MRR:205.0,129858.0] || -> until2p7(s10)* node4(s9). % 76.16/76.33 129860[95:Spt:129859.0] || -> until2p7(s10)*. % 76.16/76.33 129861[95:MRR:206.0,129860.0] || -> until2p7(s11)* node4(s10). % 76.16/76.33 129862[96:Spt:129861.0] || -> until2p7(s11)*. % 76.16/76.33 129863[96:MRR:207.0,129862.0] || -> until2p7(s12)* node4(s11). % 76.16/76.33 129864[97:Spt:129863.0] || -> until2p7(s12)*. % 76.16/76.33 129865[97:MRR:208.0,129864.0] || -> until2p7(s13)* node4(s12). % 76.16/76.33 129866[98:Spt:129865.0] || -> until2p7(s13)*. % 76.16/76.33 129867[98:MRR:209.0,129866.0] || -> until2p7(s14)* node4(s13). % 76.16/76.33 129868[99:Spt:129867.0] || -> until2p7(s14)*. % 76.16/76.33 129869[99:MRR:210.0,129868.0] || -> until2p7(s15)* node4(s14). % 76.16/76.33 129870[100:Spt:129869.0] || -> until2p7(s15)*. % 76.16/76.33 129871[100:MRR:211.0,129870.0] || -> until2p7(s16)* node4(s15). % 76.16/76.33 129872[101:Spt:129871.0] || -> until2p7(s16)*. % 76.16/76.33 129873[101:MRR:212.0,129872.0] || -> until2p7(s17)* node4(s16). % 76.16/76.33 129874[102:Spt:129873.0] || -> until2p7(s17)*. % 76.16/76.33 129875[102:MRR:213.0,129874.0] || -> until2p7(s18)* node4(s17). % 76.16/76.33 129876[103:Spt:129875.0] || -> until2p7(s18)*. % 76.16/76.33 129877[103:MRR:214.0,129876.0] || -> until2p7(s19)* node4(s18). % 76.16/76.33 129878[104:Spt:129877.0] || -> until2p7(s19)*. % 76.16/76.33 129879[104:MRR:215.0,129878.0] || -> until2p7(s20)* node4(s19). % 76.16/76.33 129880[105:Spt:129879.0] || -> until2p7(s20)*. % 76.16/76.33 129881[105:MRR:216.0,129880.0] || -> until2p7(s21)* node4(s20). % 76.16/76.33 129882[106:Spt:129881.0] || -> until2p7(s21)*. % 76.16/76.33 129883[106:MRR:217.0,129882.0] || -> until2p7(s22)* node4(s21). % 76.16/76.33 129884[107:Spt:129883.0] || -> until2p7(s22)*. % 76.16/76.33 129885[107:MRR:218.0,129884.0] || -> until2p7(s23)* node4(s22). % 76.16/76.33 129886[108:Spt:129885.0] || -> until2p7(s23)*. % 76.16/76.33 129887[108:MRR:219.0,129886.0] || -> until2p7(s24)* node4(s23). % 76.16/76.33 129888[109:Spt:129887.0] || -> until2p7(s24)*. % 76.16/76.33 129889[109:MRR:220.0,129888.0] || -> until2p7(s25)* node4(s24). % 76.16/76.33 129890[110:Spt:129889.0] || -> until2p7(s25)*. % 76.16/76.33 129891[110:MRR:221.0,129890.0] || -> until2p7(s26)* node4(s25). % 76.16/76.33 129892[111:Spt:129891.0] || -> until2p7(s26)*. % 76.16/76.33 129893[111:MRR:222.0,129892.0] || -> until2p7(s27)* node4(s26). % 76.16/76.33 129894[112:Spt:129893.0] || -> until2p7(s27)*. % 76.16/76.33 129895[112:MRR:223.0,129894.0] || -> until2p7(s28)* node4(s27). % 76.16/76.33 129896[113:Spt:129895.0] || -> until2p7(s28)*. % 76.16/76.33 129897[113:MRR:224.0,129896.0] || -> until2p7(s29)* node4(s28). % 76.16/76.33 129898[114:Spt:129897.0] || -> until2p7(s29)*. % 76.16/76.33 129899[114:MRR:225.0,129898.0] || -> until2p7(s30)* node4(s29). % 76.16/76.33 129900[115:Spt:129899.0] || -> until2p7(s30)*. % 76.16/76.33 129901[115:MRR:226.0,129900.0] || -> until2p7(s31)* node4(s30). % 76.16/76.33 129902[116:Spt:129901.0] || -> until2p7(s31)*. % 76.16/76.33 129903[116:MRR:227.0,129902.0] || -> until2p7(s32)* node4(s31). % 76.16/76.33 129904[117:Spt:129903.0] || -> until2p7(s32)*. % 76.16/76.33 129905[117:MRR:228.0,129904.0] || -> until2p7(s33)* node4(s32). % 76.16/76.33 129906[118:Spt:129905.0] || -> until2p7(s33)*. % 76.16/76.33 129907[118:MRR:229.0,129906.0] || -> until2p7(s34)* node4(s33). % 76.16/76.33 129908[119:Spt:129907.0] || -> until2p7(s34)*. % 76.16/76.33 129909[119:MRR:230.0,129908.0] || -> until2p7(s35)* node4(s34). % 76.16/76.33 129910[120:Spt:129909.0] || -> until2p7(s35)*. % 76.16/76.33 129911[120:MRR:231.0,129910.0] || -> until2p7(s36)* node4(s35). % 76.16/76.33 129912[121:Spt:129911.0] || -> until2p7(s36)*. % 76.16/76.33 129913[121:MRR:232.0,129912.0] || -> until2p7(s37)* node4(s36). % 76.16/76.33 129914[122:Spt:129913.0] || -> until2p7(s37)*. % 76.16/76.33 129915[122:MRR:235.0,129914.0] || -> until2p7(s38)* node4(s37). % 76.16/76.33 129916[123:Spt:129915.0] || -> until2p7(s38)*. % 76.16/76.33 129917[123:MRR:236.0,129916.0] || -> until2p7(s39)* node4(s38). % 76.16/76.33 129918[124:Spt:129917.0] || -> until2p7(s39)*. % 76.16/76.33 129919[124:MRR:237.0,129918.0] || -> until2p7(s40)* node4(s39). % 76.16/76.33 129920[125:Spt:129919.0] || -> until2p7(s40)*. % 76.16/76.33 129921[125:MRR:238.0,129920.0] || -> until2p7(s41)* node4(s40). % 76.16/76.33 129922[126:Spt:129921.0] || -> until2p7(s41)*. % 76.16/76.33 129923[126:MRR:239.0,129922.0] || -> until2p7(s42)* node4(s41). % 76.16/76.33 129924[127:Spt:129923.0] || -> until2p7(s42)*. % 76.16/76.33 129925[127:MRR:240.0,129924.0] || -> until2p7(s43)* node4(s42). % 76.16/76.33 129926[128:Spt:129925.0] || -> until2p7(s43)*. % 76.16/76.33 129927[128:MRR:241.0,129926.0] || -> until2p7(s44)* node4(s43). % 76.16/76.33 129928[129:Spt:129927.0] || -> until2p7(s44)*. % 76.16/76.33 129929[129:MRR:539.0,129928.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 129930[130:Spt:129929.0] || -> until2p7(s45)*. % 76.16/76.33 129931[130:MRR:544.0,129930.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 129932[131:Spt:129931.0] || -> until2p7(s46)*. % 76.16/76.33 129933[131:MRR:549.0,129932.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 129934[132:Spt:129933.0] || -> until2p7(s47)*. % 76.16/76.33 129935[132:MRR:554.0,129934.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 129936[133:Spt:129935.0] || -> until2p7(s48)*. % 76.16/76.33 129937[133:MRR:559.0,129936.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 129938[134:Spt:129937.0] || -> until2p7(s49)*. % 76.16/76.33 129939[134:MRR:194.0,129938.0] || -> node4(s49)*. % 76.16/76.33 129940[134:MRR:129854.0,129939.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 129941[134:Res:53.1,129940.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 129943[134:MRR:129941.0,78381.0] || -> . % 76.16/76.33 129944[134:Spt:129943.0,129937.0,129938.0] || until2p7(s49)*+ -> . % 76.16/76.33 129945[134:Spt:129943.0,129937.1] || -> node4(s48)*. % 76.16/76.33 129946[134:MRR:78384.0,129945.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 129949[134:Res:53.1,129946.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 129952[134:Res:129949.0,61.1] always3(s48) || -> . % 76.16/76.33 129953[134:SSi:129952.0,78281.0,78387.0,108798.0,129936.0,129945.0] || -> . % 76.16/76.33 129954[133:Spt:129953.0,129935.0,129936.0] || until2p7(s48)*+ -> . % 76.16/76.33 129955[133:Spt:129953.0,129935.1] || -> node4(s47)*. % 76.16/76.33 129957[133:MRR:777.0,129955.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 129972[133:Res:53.1,129957.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 129974[134:Spt:129972.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 129976[134:Res:129974.0,61.1] always3(s47) || -> . % 76.16/76.33 129977[134:SSi:129976.0,78277.0,78280.0,108797.0,129934.0,129955.0] || -> . % 76.16/76.33 129978[134:Spt:129977.0,129972.0,129974.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 129979[134:Spt:129977.0,129972.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 129983[134:Res:129979.0,61.1] always3(s48) || -> . % 76.16/76.33 129984[134:SSi:129983.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.33 129985[132:Spt:129984.0,129933.0,129934.0] || until2p7(s47)*+ -> . % 76.16/76.33 129986[132:Spt:129984.0,129933.1] || -> node4(s46)*. % 76.16/76.33 129988[132:MRR:780.0,129986.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 129998[132:Res:53.1,129988.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 130000[133:Spt:129998.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 130002[133:Res:130000.0,61.1] always3(s46) || -> . % 76.16/76.33 130003[133:SSi:130002.0,78272.0,78276.0,108796.0,129932.0,129986.0] || -> . % 76.16/76.33 130004[133:Spt:130003.0,129998.0,130000.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 130005[133:Spt:130003.0,129998.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 130009[133:Res:130005.0,61.1] always3(s47) || -> . % 76.16/76.33 130010[133:SSi:130009.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.33 130011[131:Spt:130010.0,129931.0,129932.0] || until2p7(s46)*+ -> . % 76.16/76.33 130012[131:Spt:130010.0,129931.1] || -> node4(s45)*. % 76.16/76.33 130014[131:MRR:783.0,130012.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 130017[131:Res:53.1,130014.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 130019[132:Spt:130017.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 130021[132:Res:130019.0,61.1] always3(s45) || -> . % 76.16/76.33 130022[132:SSi:130021.0,78268.0,78271.0,108795.0,129930.0,130012.0] || -> . % 76.16/76.33 130023[132:Spt:130022.0,130017.0,130019.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.33 130024[132:Spt:130022.0,130017.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 130028[132:Res:130024.0,61.1] always3(s46) || -> . % 76.16/76.33 130029[132:SSi:130028.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.33 130030[130:Spt:130029.0,129929.0,129930.0] || until2p7(s45)*+ -> . % 76.16/76.33 130031[130:Spt:130029.0,129929.1] || -> node4(s44)*. % 76.16/76.33 130033[130:MRR:786.0,130031.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.33 130036[130:Res:53.1,130033.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.33 130038[131:Spt:130036.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 130040[131:Res:130038.0,61.1] always3(s44) || -> . % 76.16/76.33 130041[131:SSi:130040.0,78263.0,78267.0,108794.0,129928.0,130031.0] || -> . % 76.16/76.33 130042[131:Spt:130041.0,130036.0,130038.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.33 130043[131:Spt:130041.0,130036.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 130047[131:Res:130043.0,61.1] always3(s45) || -> . % 76.16/76.33 130048[131:SSi:130047.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.33 130049[129:Spt:130048.0,129927.0,129928.0] || until2p7(s44)*+ -> . % 76.16/76.33 130050[129:Spt:130048.0,129927.1] || -> node4(s43)*. % 76.16/76.33 130052[129:MRR:789.0,130050.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.33 130055[129:Res:53.1,130052.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.33 130060[130:Spt:130055.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 130062[130:Res:130060.0,61.1] always3(s43) || -> . % 76.16/76.33 130063[130:SSi:130062.0,78259.0,78262.0,108793.0,129926.0,130050.0] || -> . % 76.16/76.33 130064[130:Spt:130063.0,130055.0,130060.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.33 130065[130:Spt:130063.0,130055.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 130069[130:Res:130065.0,61.1] always3(s44) || -> . % 76.16/76.33 130070[130:SSi:130069.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.33 130071[128:Spt:130070.0,129925.0,129926.0] || until2p7(s43)*+ -> . % 76.16/76.33 130072[128:Spt:130070.0,129925.1] || -> node4(s42)*. % 76.16/76.33 130074[128:MRR:792.0,130072.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.33 130077[128:Res:53.1,130074.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.33 130079[129:Spt:130077.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 130081[129:Res:130079.0,61.1] always3(s42) || -> . % 76.16/76.33 130082[129:SSi:130081.0,78254.0,78258.0,108792.0,129924.0,130072.0] || -> . % 76.16/76.33 130083[129:Spt:130082.0,130077.0,130079.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.33 130084[129:Spt:130082.0,130077.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 130088[129:Res:130084.0,61.1] always3(s43) || -> . % 76.16/76.33 130089[129:SSi:130088.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.33 130090[127:Spt:130089.0,129923.0,129924.0] || until2p7(s42)*+ -> . % 76.16/76.33 130091[127:Spt:130089.0,129923.1] || -> node4(s41)*. % 76.16/76.33 130093[127:MRR:795.0,130091.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.33 130096[127:Res:53.1,130093.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.33 130098[128:Spt:130096.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 130100[128:Res:130098.0,61.1] always3(s41) || -> . % 76.16/76.33 130101[128:SSi:130100.0,78250.0,78253.0,108791.0,129922.0,130091.0] || -> . % 76.16/76.33 130102[128:Spt:130101.0,130096.0,130098.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.33 130103[128:Spt:130101.0,130096.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 130107[128:Res:130103.0,61.1] always3(s42) || -> . % 76.16/76.33 130108[128:SSi:130107.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.33 130109[126:Spt:130108.0,129921.0,129922.0] || until2p7(s41)*+ -> . % 76.16/76.33 130110[126:Spt:130108.0,129921.1] || -> node4(s40)*. % 76.16/76.33 130112[126:MRR:798.0,130110.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.33 130115[126:Res:53.1,130112.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.33 130117[127:Spt:130115.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 130119[127:Res:130117.0,61.1] always3(s40) || -> . % 76.16/76.33 130120[127:SSi:130119.0,78245.0,78249.0,108790.0,129920.0,130110.0] || -> . % 76.16/76.33 130121[127:Spt:130120.0,130115.0,130117.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.33 130122[127:Spt:130120.0,130115.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 130126[127:Res:130122.0,61.1] always3(s41) || -> . % 76.16/76.33 130127[127:SSi:130126.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.33 130128[125:Spt:130127.0,129919.0,129920.0] || until2p7(s40)*+ -> . % 76.16/76.33 130129[125:Spt:130127.0,129919.1] || -> node4(s39)*. % 76.16/76.33 130131[125:MRR:801.0,130129.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.33 130134[125:Res:53.1,130131.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.33 130139[126:Spt:130134.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 130141[126:Res:130139.0,61.1] always3(s39) || -> . % 76.16/76.33 130142[126:SSi:130141.0,78241.0,78244.0,108789.0,129918.0,130129.0] || -> . % 76.16/76.33 130143[126:Spt:130142.0,130134.0,130139.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.33 130144[126:Spt:130142.0,130134.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 130148[126:Res:130144.0,61.1] always3(s40) || -> . % 76.16/76.33 130149[126:SSi:130148.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.33 130150[124:Spt:130149.0,129917.0,129918.0] || until2p7(s39)*+ -> . % 76.16/76.33 130151[124:Spt:130149.0,129917.1] || -> node4(s38)*. % 76.16/76.33 130153[124:MRR:804.0,130151.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.33 130156[124:Res:53.1,130153.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.33 130158[125:Spt:130156.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 130160[125:Res:130158.0,61.1] always3(s38) || -> . % 76.16/76.33 130161[125:SSi:130160.0,78236.0,78240.0,108788.0,129916.0,130151.0] || -> . % 76.16/76.33 130162[125:Spt:130161.0,130156.0,130158.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.33 130163[125:Spt:130161.0,130156.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 130167[125:Res:130163.0,61.1] always3(s39) || -> . % 76.16/76.33 130168[125:SSi:130167.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.33 130169[123:Spt:130168.0,129915.0,129916.0] || until2p7(s38)*+ -> . % 76.16/76.33 130170[123:Spt:130168.0,129915.1] || -> node4(s37)*. % 76.16/76.33 130172[123:MRR:807.0,130170.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.33 130175[123:Res:53.1,130172.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.33 130177[124:Spt:130175.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 130179[124:Res:130177.0,61.1] always3(s37) || -> . % 76.16/76.33 130180[124:SSi:130179.0,78232.0,78235.0,108787.0,129914.0,130170.0] || -> . % 76.16/76.33 130181[124:Spt:130180.0,130175.0,130177.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.33 130182[124:Spt:130180.0,130175.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 130186[124:Res:130182.0,61.1] always3(s38) || -> . % 76.16/76.33 130187[124:SSi:130186.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.33 130188[122:Spt:130187.0,129913.0,129914.0] || until2p7(s37)*+ -> . % 76.16/76.33 130189[122:Spt:130187.0,129913.1] || -> node4(s36)*. % 76.16/76.33 130191[122:MRR:810.0,130189.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.33 130194[122:Res:53.1,130191.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.33 130196[123:Spt:130194.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 130198[123:Res:130196.0,61.1] always3(s36) || -> . % 76.16/76.33 130199[123:SSi:130198.0,78227.0,78231.0,108786.0,129912.0,130189.0] || -> . % 76.16/76.33 130200[123:Spt:130199.0,130194.0,130196.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.33 130201[123:Spt:130199.0,130194.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 130205[123:Res:130201.0,61.1] always3(s37) || -> . % 76.16/76.33 130206[123:SSi:130205.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.33 130207[121:Spt:130206.0,129911.0,129912.0] || until2p7(s36)*+ -> . % 76.16/76.33 130208[121:Spt:130206.0,129911.1] || -> node4(s35)*. % 76.16/76.33 130210[121:MRR:813.0,130208.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.33 130213[121:Res:53.1,130210.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.33 130218[122:Spt:130213.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 130220[122:Res:130218.0,61.1] always3(s35) || -> . % 76.16/76.33 130221[122:SSi:130220.0,78223.0,78226.0,108785.0,129910.0,130208.0] || -> . % 76.16/76.33 130222[122:Spt:130221.0,130213.0,130218.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.33 130223[122:Spt:130221.0,130213.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 130227[122:Res:130223.0,61.1] always3(s36) || -> . % 76.16/76.33 130228[122:SSi:130227.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.33 130229[120:Spt:130228.0,129909.0,129910.0] || until2p7(s35)*+ -> . % 76.16/76.33 130230[120:Spt:130228.0,129909.1] || -> node4(s34)*. % 76.16/76.33 130232[120:MRR:816.0,130230.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.33 130235[120:Res:53.1,130232.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.33 130237[121:Spt:130235.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 130239[121:Res:130237.0,61.1] always3(s34) || -> . % 76.16/76.33 130240[121:SSi:130239.0,78218.0,78222.0,108784.0,129908.0,130230.0] || -> . % 76.16/76.33 130241[121:Spt:130240.0,130235.0,130237.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.33 130242[121:Spt:130240.0,130235.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 130246[121:Res:130242.0,61.1] always3(s35) || -> . % 76.16/76.33 130247[121:SSi:130246.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.33 130248[119:Spt:130247.0,129907.0,129908.0] || until2p7(s34)*+ -> . % 76.16/76.33 130249[119:Spt:130247.0,129907.1] || -> node4(s33)*. % 76.16/76.33 130251[119:MRR:819.0,130249.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.33 130254[119:Res:53.1,130251.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.33 130256[120:Spt:130254.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 130258[120:Res:130256.0,61.1] always3(s33) || -> . % 76.16/76.33 130259[120:SSi:130258.0,78214.0,78217.0,108783.0,129906.0,130249.0] || -> . % 76.16/76.33 130260[120:Spt:130259.0,130254.0,130256.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.33 130261[120:Spt:130259.0,130254.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 130265[120:Res:130261.0,61.1] always3(s34) || -> . % 76.16/76.33 130266[120:SSi:130265.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.33 130267[118:Spt:130266.0,129905.0,129906.0] || until2p7(s33)*+ -> . % 76.16/76.33 130268[118:Spt:130266.0,129905.1] || -> node4(s32)*. % 76.16/76.33 130270[118:MRR:822.0,130268.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.33 130273[118:Res:53.1,130270.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.33 130275[119:Spt:130273.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 130277[119:Res:130275.0,61.1] always3(s32) || -> . % 76.16/76.33 130278[119:SSi:130277.0,78209.0,78213.0,108782.0,129904.0,130268.0] || -> . % 76.16/76.33 130279[119:Spt:130278.0,130273.0,130275.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.33 130280[119:Spt:130278.0,130273.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 130284[119:Res:130280.0,61.1] always3(s33) || -> . % 76.16/76.33 130285[119:SSi:130284.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.33 130286[117:Spt:130285.0,129903.0,129904.0] || until2p7(s32)*+ -> . % 76.16/76.33 130287[117:Spt:130285.0,129903.1] || -> node4(s31)*. % 76.16/76.33 130289[117:MRR:825.0,130287.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.33 130292[117:Res:53.1,130289.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.33 130297[118:Spt:130292.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 130299[118:Res:130297.0,61.1] always3(s31) || -> . % 76.16/76.33 130300[118:SSi:130299.0,78205.0,78208.0,108781.0,129902.0,130287.0] || -> . % 76.16/76.33 130301[118:Spt:130300.0,130292.0,130297.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.33 130302[118:Spt:130300.0,130292.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 130306[118:Res:130302.0,61.1] always3(s32) || -> . % 76.16/76.33 130307[118:SSi:130306.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.33 130308[116:Spt:130307.0,129901.0,129902.0] || until2p7(s31)*+ -> . % 76.16/76.33 130309[116:Spt:130307.0,129901.1] || -> node4(s30)*. % 76.16/76.33 130311[116:MRR:828.0,130309.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.33 130314[116:Res:53.1,130311.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.33 130316[117:Spt:130314.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 130318[117:Res:130316.0,61.1] always3(s30) || -> . % 76.16/76.33 130319[117:SSi:130318.0,78200.0,78204.0,108780.0,129900.0,130309.0] || -> . % 76.16/76.33 130320[117:Spt:130319.0,130314.0,130316.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.33 130321[117:Spt:130319.0,130314.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 130325[117:Res:130321.0,61.1] always3(s31) || -> . % 76.16/76.33 130326[117:SSi:130325.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.33 130327[115:Spt:130326.0,129899.0,129900.0] || until2p7(s30)*+ -> . % 76.16/76.33 130328[115:Spt:130326.0,129899.1] || -> node4(s29)*. % 76.16/76.33 130330[115:MRR:831.0,130328.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.33 130333[115:Res:53.1,130330.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.33 130335[116:Spt:130333.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 130337[116:Res:130335.0,61.1] always3(s29) || -> . % 76.16/76.33 130338[116:SSi:130337.0,78196.0,78199.0,108779.0,129898.0,130328.0] || -> . % 76.16/76.33 130339[116:Spt:130338.0,130333.0,130335.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.33 130340[116:Spt:130338.0,130333.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 130344[116:Res:130340.0,61.1] always3(s30) || -> . % 76.16/76.33 130345[116:SSi:130344.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.33 130346[114:Spt:130345.0,129897.0,129898.0] || until2p7(s29)*+ -> . % 76.16/76.33 130347[114:Spt:130345.0,129897.1] || -> node4(s28)*. % 76.16/76.33 130349[114:MRR:834.0,130347.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.33 130352[114:Res:53.1,130349.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.33 130354[115:Spt:130352.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 130356[115:Res:130354.0,61.1] always3(s28) || -> . % 76.16/76.33 130357[115:SSi:130356.0,78191.0,78195.0,108778.0,129896.0,130347.0] || -> . % 76.16/76.33 130358[115:Spt:130357.0,130352.0,130354.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.33 130359[115:Spt:130357.0,130352.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 130363[115:Res:130359.0,61.1] always3(s29) || -> . % 76.16/76.33 130364[115:SSi:130363.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.33 130365[113:Spt:130364.0,129895.0,129896.0] || until2p7(s28)*+ -> . % 76.16/76.33 130366[113:Spt:130364.0,129895.1] || -> node4(s27)*. % 76.16/76.33 130368[113:MRR:837.0,130366.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.33 130371[113:Res:53.1,130368.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.33 130376[114:Spt:130371.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 130378[114:Res:130376.0,61.1] always3(s27) || -> . % 76.16/76.33 130379[114:SSi:130378.0,78187.0,78190.0,108777.0,129894.0,130366.0] || -> . % 76.16/76.33 130380[114:Spt:130379.0,130371.0,130376.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.33 130381[114:Spt:130379.0,130371.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 130385[114:Res:130381.0,61.1] always3(s28) || -> . % 76.16/76.33 130386[114:SSi:130385.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.33 130387[112:Spt:130386.0,129893.0,129894.0] || until2p7(s27)*+ -> . % 76.16/76.33 130388[112:Spt:130386.0,129893.1] || -> node4(s26)*. % 76.16/76.33 130390[112:MRR:840.0,130388.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.33 130393[112:Res:53.1,130390.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.33 130395[113:Spt:130393.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 130397[113:Res:130395.0,61.1] always3(s26) || -> . % 76.16/76.33 130398[113:SSi:130397.0,78182.0,78186.0,108776.0,129892.0,130388.0] || -> . % 76.16/76.33 130399[113:Spt:130398.0,130393.0,130395.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.33 130400[113:Spt:130398.0,130393.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 130404[113:Res:130400.0,61.1] always3(s27) || -> . % 76.16/76.33 130405[113:SSi:130404.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.33 130406[111:Spt:130405.0,129891.0,129892.0] || until2p7(s26)*+ -> . % 76.16/76.33 130407[111:Spt:130405.0,129891.1] || -> node4(s25)*. % 76.16/76.33 130409[111:MRR:843.0,130407.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.33 130412[111:Res:53.1,130409.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.33 130414[112:Spt:130412.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 130416[112:Res:130414.0,61.1] always3(s25) || -> . % 76.16/76.33 130417[112:SSi:130416.0,78178.0,78181.0,108775.0,129890.0,130407.0] || -> . % 76.16/76.33 130418[112:Spt:130417.0,130412.0,130414.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.33 130419[112:Spt:130417.0,130412.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 130423[112:Res:130419.0,61.1] always3(s26) || -> . % 76.16/76.33 130424[112:SSi:130423.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.33 130425[110:Spt:130424.0,129889.0,129890.0] || until2p7(s25)*+ -> . % 76.16/76.33 130426[110:Spt:130424.0,129889.1] || -> node4(s24)*. % 76.16/76.33 130428[110:MRR:846.0,130426.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.33 130431[110:Res:53.1,130428.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.33 130433[111:Spt:130431.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 130435[111:Res:130433.0,61.1] always3(s24) || -> . % 76.16/76.33 130436[111:SSi:130435.0,78173.0,78177.0,108774.0,129888.0,130426.0] || -> . % 76.16/76.33 130437[111:Spt:130436.0,130431.0,130433.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.33 130438[111:Spt:130436.0,130431.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 130442[111:Res:130438.0,61.1] always3(s25) || -> . % 76.16/76.33 130443[111:SSi:130442.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.33 130444[109:Spt:130443.0,129887.0,129888.0] || until2p7(s24)*+ -> . % 76.16/76.33 130445[109:Spt:130443.0,129887.1] || -> node4(s23)*. % 76.16/76.33 130447[109:MRR:849.0,130445.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.33 130450[109:Res:53.1,130447.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.33 130455[110:Spt:130450.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 130457[110:Res:130455.0,61.1] always3(s23) || -> . % 76.16/76.33 130458[110:SSi:130457.0,78169.0,78172.0,108773.0,129886.0,130445.0] || -> . % 76.16/76.33 130459[110:Spt:130458.0,130450.0,130455.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.33 130460[110:Spt:130458.0,130450.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 130464[110:Res:130460.0,61.1] always3(s24) || -> . % 76.16/76.33 130465[110:SSi:130464.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.33 130466[108:Spt:130465.0,129885.0,129886.0] || until2p7(s23)*+ -> . % 76.16/76.33 130467[108:Spt:130465.0,129885.1] || -> node4(s22)*. % 76.16/76.33 130469[108:MRR:852.0,130467.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.33 130472[108:Res:53.1,130469.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.33 130474[109:Spt:130472.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 130476[109:Res:130474.0,61.1] always3(s22) || -> . % 76.16/76.33 130477[109:SSi:130476.0,78164.0,78168.0,108772.0,129884.0,130467.0] || -> . % 76.16/76.33 130478[109:Spt:130477.0,130472.0,130474.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.33 130479[109:Spt:130477.0,130472.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 130483[109:Res:130479.0,61.1] always3(s23) || -> . % 76.16/76.33 130484[109:SSi:130483.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.33 130485[107:Spt:130484.0,129883.0,129884.0] || until2p7(s22)*+ -> . % 76.16/76.33 130486[107:Spt:130484.0,129883.1] || -> node4(s21)*. % 76.16/76.33 130488[107:MRR:855.0,130486.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.33 130491[107:Res:53.1,130488.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.33 130493[108:Spt:130491.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 130495[108:Res:130493.0,61.1] always3(s21) || -> . % 76.16/76.33 130496[108:SSi:130495.0,78160.0,78163.0,108771.0,129882.0,130486.0] || -> . % 76.16/76.33 130497[108:Spt:130496.0,130491.0,130493.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.33 130498[108:Spt:130496.0,130491.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 130502[108:Res:130498.0,61.1] always3(s22) || -> . % 76.16/76.33 130503[108:SSi:130502.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.33 130504[106:Spt:130503.0,129881.0,129882.0] || until2p7(s21)*+ -> . % 76.16/76.33 130505[106:Spt:130503.0,129881.1] || -> node4(s20)*. % 76.16/76.33 130507[106:MRR:858.0,130505.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.33 130510[106:Res:53.1,130507.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.33 130512[107:Spt:130510.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 130514[107:Res:130512.0,61.1] always3(s20) || -> . % 76.16/76.33 130515[107:SSi:130514.0,78155.0,78159.0,108770.0,129880.0,130505.0] || -> . % 76.16/76.33 130516[107:Spt:130515.0,130510.0,130512.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.33 130517[107:Spt:130515.0,130510.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 130521[107:Res:130517.0,61.1] always3(s21) || -> . % 76.16/76.33 130522[107:SSi:130521.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.33 130523[105:Spt:130522.0,129879.0,129880.0] || until2p7(s20)*+ -> . % 76.16/76.33 130524[105:Spt:130522.0,129879.1] || -> node4(s19)*. % 76.16/76.33 130526[105:MRR:861.0,130524.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.33 130529[105:Res:53.1,130526.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.33 130534[106:Spt:130529.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 130536[106:Res:130534.0,61.1] always3(s19) || -> . % 76.16/76.33 130537[106:SSi:130536.0,78151.0,78154.0,108769.0,129878.0,130524.0] || -> . % 76.16/76.33 130538[106:Spt:130537.0,130529.0,130534.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.33 130539[106:Spt:130537.0,130529.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 130543[106:Res:130539.0,61.1] always3(s20) || -> . % 76.16/76.33 130544[106:SSi:130543.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.33 130545[104:Spt:130544.0,129877.0,129878.0] || until2p7(s19)*+ -> . % 76.16/76.33 130546[104:Spt:130544.0,129877.1] || -> node4(s18)*. % 76.16/76.33 130548[104:MRR:864.0,130546.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.33 130551[104:Res:53.1,130548.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.33 130553[105:Spt:130551.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 130555[105:Res:130553.0,61.1] always3(s18) || -> . % 76.16/76.33 130556[105:SSi:130555.0,78146.0,78150.0,108768.0,129876.0,130546.0] || -> . % 76.16/76.33 130557[105:Spt:130556.0,130551.0,130553.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.33 130558[105:Spt:130556.0,130551.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 130562[105:Res:130558.0,61.1] always3(s19) || -> . % 76.16/76.33 130563[105:SSi:130562.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.33 130564[103:Spt:130563.0,129875.0,129876.0] || until2p7(s18)*+ -> . % 76.16/76.33 130565[103:Spt:130563.0,129875.1] || -> node4(s17)*. % 76.16/76.33 130567[103:MRR:867.0,130565.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.33 130570[103:Res:53.1,130567.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.33 130572[104:Spt:130570.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 130574[104:Res:130572.0,61.1] always3(s17) || -> . % 76.16/76.33 130575[104:SSi:130574.0,78142.0,78145.0,108767.0,129874.0,130565.0] || -> . % 76.16/76.33 130576[104:Spt:130575.0,130570.0,130572.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.33 130577[104:Spt:130575.0,130570.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 130581[104:Res:130577.0,61.1] always3(s18) || -> . % 76.16/76.33 130582[104:SSi:130581.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.33 130583[102:Spt:130582.0,129873.0,129874.0] || until2p7(s17)*+ -> . % 76.16/76.33 130584[102:Spt:130582.0,129873.1] || -> node4(s16)*. % 76.16/76.33 130586[102:MRR:870.0,130584.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.33 130589[102:Res:53.1,130586.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.33 130591[103:Spt:130589.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 130593[103:Res:130591.0,61.1] always3(s16) || -> . % 76.16/76.33 130594[103:SSi:130593.0,78137.0,78141.0,108766.0,129872.0,130584.0] || -> . % 76.16/76.33 130595[103:Spt:130594.0,130589.0,130591.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.33 130596[103:Spt:130594.0,130589.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 130600[103:Res:130596.0,61.1] always3(s17) || -> . % 76.16/76.33 130601[103:SSi:130600.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.33 130602[101:Spt:130601.0,129871.0,129872.0] || until2p7(s16)*+ -> . % 76.16/76.33 130603[101:Spt:130601.0,129871.1] || -> node4(s15)*. % 76.16/76.33 130605[101:MRR:873.0,130603.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.33 130608[101:Res:53.1,130605.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.33 130613[102:Spt:130608.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 130615[102:Res:130613.0,61.1] always3(s15) || -> . % 76.16/76.33 130616[102:SSi:130615.0,78133.0,78136.0,108765.0,129870.0,130603.0] || -> . % 76.16/76.33 130617[102:Spt:130616.0,130608.0,130613.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.33 130618[102:Spt:130616.0,130608.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 130622[102:Res:130618.0,61.1] always3(s16) || -> . % 76.16/76.33 130623[102:SSi:130622.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.33 130624[100:Spt:130623.0,129869.0,129870.0] || until2p7(s15)*+ -> . % 76.16/76.33 130625[100:Spt:130623.0,129869.1] || -> node4(s14)*. % 76.16/76.33 130627[100:MRR:876.0,130625.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.33 130630[100:Res:53.1,130627.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.33 130632[101:Spt:130630.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 130634[101:Res:130632.0,61.1] always3(s14) || -> . % 76.16/76.33 130635[101:SSi:130634.0,78128.0,78132.0,108764.0,129868.0,130625.0] || -> . % 76.16/76.33 130636[101:Spt:130635.0,130630.0,130632.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.33 130637[101:Spt:130635.0,130630.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 130641[101:Res:130637.0,61.1] always3(s15) || -> . % 76.16/76.33 130642[101:SSi:130641.0,78133.0,78136.0,108765.0] || -> . % 76.16/76.33 130643[99:Spt:130642.0,129867.0,129868.0] || until2p7(s14)*+ -> . % 76.16/76.33 130644[99:Spt:130642.0,129867.1] || -> node4(s13)*. % 76.16/76.33 130646[99:MRR:879.0,130644.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.33 130649[99:Res:53.1,130646.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.33 130651[100:Spt:130649.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 130653[100:Res:130651.0,61.1] always3(s13) || -> . % 76.16/76.33 130654[100:SSi:130653.0,78124.0,78127.0,108763.0,129866.0,130644.0] || -> . % 76.16/76.33 130655[100:Spt:130654.0,130649.0,130651.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.33 130656[100:Spt:130654.0,130649.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 130660[100:Res:130656.0,61.1] always3(s14) || -> . % 76.16/76.33 130661[100:SSi:130660.0,78128.0,78132.0,108764.0] || -> . % 76.16/76.33 130662[98:Spt:130661.0,129865.0,129866.0] || until2p7(s13)*+ -> . % 76.16/76.33 130663[98:Spt:130661.0,129865.1] || -> node4(s12)*. % 76.16/76.33 130665[98:MRR:882.0,130663.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.33 130668[98:Res:53.1,130665.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.33 130670[99:Spt:130668.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 130672[99:Res:130670.0,61.1] always3(s12) || -> . % 76.16/76.33 130673[99:SSi:130672.0,78119.0,78123.0,108762.0,129864.0,130663.0] || -> . % 76.16/76.33 130674[99:Spt:130673.0,130668.0,130670.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.33 130675[99:Spt:130673.0,130668.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 130679[99:Res:130675.0,61.1] always3(s13) || -> . % 76.16/76.33 130680[99:SSi:130679.0,78124.0,78127.0,108763.0] || -> . % 76.16/76.33 130681[97:Spt:130680.0,129863.0,129864.0] || until2p7(s12)*+ -> . % 76.16/76.33 130682[97:Spt:130680.0,129863.1] || -> node4(s11)*. % 76.16/76.33 130684[97:MRR:885.0,130682.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.33 130687[97:Res:53.1,130684.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.33 130692[98:Spt:130687.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 130694[98:Res:130692.0,61.1] always3(s11) || -> . % 76.16/76.33 130695[98:SSi:130694.0,78115.0,78118.0,108761.0,129862.0,130682.0] || -> . % 76.16/76.33 130696[98:Spt:130695.0,130687.0,130692.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.33 130697[98:Spt:130695.0,130687.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 130701[98:Res:130697.0,61.1] always3(s12) || -> . % 76.16/76.33 130702[98:SSi:130701.0,78119.0,78123.0,108762.0] || -> . % 76.16/76.33 130703[96:Spt:130702.0,129861.0,129862.0] || until2p7(s11)*+ -> . % 76.16/76.33 130704[96:Spt:130702.0,129861.1] || -> node4(s10)*. % 76.16/76.33 130706[96:MRR:888.0,130704.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.33 130709[96:Res:53.1,130706.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.33 130711[97:Spt:130709.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 130713[97:Res:130711.0,61.1] always3(s10) || -> . % 76.16/76.33 130714[97:SSi:130713.0,78110.0,78114.0,108760.0,129860.0,130704.0] || -> . % 76.16/76.33 130715[97:Spt:130714.0,130709.0,130711.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.33 130716[97:Spt:130714.0,130709.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 130720[97:Res:130716.0,61.1] always3(s11) || -> . % 76.16/76.33 130721[97:SSi:130720.0,78115.0,78118.0,108761.0] || -> . % 76.16/76.33 130722[95:Spt:130721.0,129859.0,129860.0] || until2p7(s10)*+ -> . % 76.16/76.33 130723[95:Spt:130721.0,129859.1] || -> node4(s9)*. % 76.16/76.33 130725[95:MRR:891.0,130723.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.33 130728[95:Res:53.1,130725.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.33 130730[95:MRR:130728.0,129849.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 130732[95:Res:130730.0,61.1] always3(s10) || -> . % 76.16/76.33 130733[95:SSi:130732.0,78110.0,78114.0,108760.0] || -> . % 76.16/76.33 130734[93:Spt:130733.0,129700.0,129703.0] || trans(s49,s9)*+ -> . % 76.16/76.33 130735[93:Spt:130733.0,129700.1,129700.2,129700.3,129700.4,129700.5,129700.6] || -> trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.33 130737[93:MRR:129702.1,130734.0] xuntil6(s49) || -> trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.33 130738[94:Spt:130735.0] || -> trans(s49,s8)*. % 76.16/76.33 130739[94:Res:130738.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s8)*. % 76.16/76.33 130741[94:Res:130738.0,60.0] || -> node2(s49,s8)*. % 76.16/76.33 130742[94:SSi:130739.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s8)*. % 76.16/76.33 130743[94:Res:130741.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)*. % 76.16/76.33 130880[94:SoR:130743.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)*. % 76.16/76.33 130882[94:SoR:130880.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)* xuntil6(s49). % 76.16/76.33 130883[94:SSi:130882.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s8,c_busy)* xuntil6(s49). % 76.16/76.33 130884[95:Spt:130883.1] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.33 130886[95:Res:130884.0,61.1] always3(s8) || -> . % 76.16/76.33 130887[95:SSi:130886.0,78101.0,78105.0,108758.0] || -> . % 76.16/76.33 130888[95:Spt:130887.0,130883.1,130884.0] || m_main_v_state(s8,c_busy)*+ -> . % 76.16/76.33 130889[95:Spt:130887.0,130883.0,130883.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 130893[95:MRR:130880.2,130888.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 130894[95:Res:53.1,130889.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 130896[95:MRR:130894.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 130897[95:MRR:130742.0,130896.0] || -> until2p7(s8)*. % 76.16/76.33 130898[95:MRR:204.0,130897.0] || -> until2p7(s9)* node4(s8). % 76.16/76.33 130899[96:Spt:130898.0] || -> until2p7(s9)*. % 76.16/76.33 130900[96:MRR:205.0,130899.0] || -> until2p7(s10)* node4(s9). % 76.16/76.33 130901[97:Spt:130900.0] || -> until2p7(s10)*. % 76.16/76.33 130902[97:MRR:206.0,130901.0] || -> until2p7(s11)* node4(s10). % 76.16/76.33 130903[98:Spt:130902.0] || -> until2p7(s11)*. % 76.16/76.33 130904[98:MRR:207.0,130903.0] || -> until2p7(s12)* node4(s11). % 76.16/76.33 130905[99:Spt:130904.0] || -> until2p7(s12)*. % 76.16/76.33 130906[99:MRR:208.0,130905.0] || -> until2p7(s13)* node4(s12). % 76.16/76.33 130907[100:Spt:130906.0] || -> until2p7(s13)*. % 76.16/76.33 130908[100:MRR:209.0,130907.0] || -> until2p7(s14)* node4(s13). % 76.16/76.33 130909[101:Spt:130908.0] || -> until2p7(s14)*. % 76.16/76.33 130910[101:MRR:210.0,130909.0] || -> until2p7(s15)* node4(s14). % 76.16/76.33 130911[102:Spt:130910.0] || -> until2p7(s15)*. % 76.16/76.33 130912[102:MRR:211.0,130911.0] || -> until2p7(s16)* node4(s15). % 76.16/76.33 130913[103:Spt:130912.0] || -> until2p7(s16)*. % 76.16/76.33 130914[103:MRR:212.0,130913.0] || -> until2p7(s17)* node4(s16). % 76.16/76.33 130915[104:Spt:130914.0] || -> until2p7(s17)*. % 76.16/76.33 130916[104:MRR:213.0,130915.0] || -> until2p7(s18)* node4(s17). % 76.16/76.33 130917[105:Spt:130916.0] || -> until2p7(s18)*. % 76.16/76.33 130918[105:MRR:214.0,130917.0] || -> until2p7(s19)* node4(s18). % 76.16/76.33 130919[106:Spt:130918.0] || -> until2p7(s19)*. % 76.16/76.33 130920[106:MRR:215.0,130919.0] || -> until2p7(s20)* node4(s19). % 76.16/76.33 130921[107:Spt:130920.0] || -> until2p7(s20)*. % 76.16/76.33 130922[107:MRR:216.0,130921.0] || -> until2p7(s21)* node4(s20). % 76.16/76.33 130923[108:Spt:130922.0] || -> until2p7(s21)*. % 76.16/76.33 130924[108:MRR:217.0,130923.0] || -> until2p7(s22)* node4(s21). % 76.16/76.33 130925[109:Spt:130924.0] || -> until2p7(s22)*. % 76.16/76.33 130926[109:MRR:218.0,130925.0] || -> until2p7(s23)* node4(s22). % 76.16/76.33 130927[110:Spt:130926.0] || -> until2p7(s23)*. % 76.16/76.33 130928[110:MRR:219.0,130927.0] || -> until2p7(s24)* node4(s23). % 76.16/76.33 130929[111:Spt:130928.0] || -> until2p7(s24)*. % 76.16/76.33 130930[111:MRR:220.0,130929.0] || -> until2p7(s25)* node4(s24). % 76.16/76.33 130931[112:Spt:130930.0] || -> until2p7(s25)*. % 76.16/76.33 130932[112:MRR:221.0,130931.0] || -> until2p7(s26)* node4(s25). % 76.16/76.33 130933[113:Spt:130932.0] || -> until2p7(s26)*. % 76.16/76.33 130934[113:MRR:222.0,130933.0] || -> until2p7(s27)* node4(s26). % 76.16/76.33 130935[114:Spt:130934.0] || -> until2p7(s27)*. % 76.16/76.33 130936[114:MRR:223.0,130935.0] || -> until2p7(s28)* node4(s27). % 76.16/76.33 130937[115:Spt:130936.0] || -> until2p7(s28)*. % 76.16/76.33 130938[115:MRR:224.0,130937.0] || -> until2p7(s29)* node4(s28). % 76.16/76.33 130939[116:Spt:130938.0] || -> until2p7(s29)*. % 76.16/76.33 130940[116:MRR:225.0,130939.0] || -> until2p7(s30)* node4(s29). % 76.16/76.33 130941[117:Spt:130940.0] || -> until2p7(s30)*. % 76.16/76.33 130942[117:MRR:226.0,130941.0] || -> until2p7(s31)* node4(s30). % 76.16/76.33 130943[118:Spt:130942.0] || -> until2p7(s31)*. % 76.16/76.33 130944[118:MRR:227.0,130943.0] || -> until2p7(s32)* node4(s31). % 76.16/76.33 130945[119:Spt:130944.0] || -> until2p7(s32)*. % 76.16/76.33 130946[119:MRR:228.0,130945.0] || -> until2p7(s33)* node4(s32). % 76.16/76.33 130947[120:Spt:130946.0] || -> until2p7(s33)*. % 76.16/76.33 130948[120:MRR:229.0,130947.0] || -> until2p7(s34)* node4(s33). % 76.16/76.33 130949[121:Spt:130948.0] || -> until2p7(s34)*. % 76.16/76.33 130950[121:MRR:230.0,130949.0] || -> until2p7(s35)* node4(s34). % 76.16/76.33 130951[122:Spt:130950.0] || -> until2p7(s35)*. % 76.16/76.33 130952[122:MRR:231.0,130951.0] || -> until2p7(s36)* node4(s35). % 76.16/76.33 130953[123:Spt:130952.0] || -> until2p7(s36)*. % 76.16/76.33 130954[123:MRR:232.0,130953.0] || -> until2p7(s37)* node4(s36). % 76.16/76.33 130955[124:Spt:130954.0] || -> until2p7(s37)*. % 76.16/76.33 130956[124:MRR:235.0,130955.0] || -> until2p7(s38)* node4(s37). % 76.16/76.33 130957[125:Spt:130956.0] || -> until2p7(s38)*. % 76.16/76.33 130958[125:MRR:236.0,130957.0] || -> until2p7(s39)* node4(s38). % 76.16/76.33 130959[126:Spt:130958.0] || -> until2p7(s39)*. % 76.16/76.33 130960[126:MRR:237.0,130959.0] || -> until2p7(s40)* node4(s39). % 76.16/76.33 130961[127:Spt:130960.0] || -> until2p7(s40)*. % 76.16/76.33 130962[127:MRR:238.0,130961.0] || -> until2p7(s41)* node4(s40). % 76.16/76.33 130963[128:Spt:130962.0] || -> until2p7(s41)*. % 76.16/76.33 130964[128:MRR:239.0,130963.0] || -> until2p7(s42)* node4(s41). % 76.16/76.33 130965[129:Spt:130964.0] || -> until2p7(s42)*. % 76.16/76.33 130966[129:MRR:240.0,130965.0] || -> until2p7(s43)* node4(s42). % 76.16/76.33 130967[130:Spt:130966.0] || -> until2p7(s43)*. % 76.16/76.33 130968[130:MRR:241.0,130967.0] || -> until2p7(s44)* node4(s43). % 76.16/76.33 130969[131:Spt:130968.0] || -> until2p7(s44)*. % 76.16/76.33 130970[131:MRR:539.0,130969.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 130971[132:Spt:130970.0] || -> until2p7(s45)*. % 76.16/76.33 130972[132:MRR:544.0,130971.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 130973[133:Spt:130972.0] || -> until2p7(s46)*. % 76.16/76.33 130974[133:MRR:549.0,130973.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 130975[134:Spt:130974.0] || -> until2p7(s47)*. % 76.16/76.33 130976[134:MRR:554.0,130975.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 130977[135:Spt:130976.0] || -> until2p7(s48)*. % 76.16/76.33 130978[135:MRR:559.0,130977.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 130979[136:Spt:130978.0] || -> until2p7(s49)*. % 76.16/76.33 130980[136:MRR:194.0,130979.0] || -> node4(s49)*. % 76.16/76.33 130981[136:MRR:130893.0,130980.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 130985[136:Res:53.1,130981.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 130987[136:MRR:130985.0,78381.0] || -> . % 76.16/76.33 130988[136:Spt:130987.0,130978.0,130979.0] || until2p7(s49)*+ -> . % 76.16/76.33 130989[136:Spt:130987.0,130978.1] || -> node4(s48)*. % 76.16/76.33 130990[136:MRR:78384.0,130989.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 130993[136:Res:53.1,130990.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 130996[136:Res:130993.0,61.1] always3(s48) || -> . % 76.16/76.33 130997[136:SSi:130996.0,78281.0,78387.0,108798.0,130977.0,130989.0] || -> . % 76.16/76.33 130998[135:Spt:130997.0,130976.0,130977.0] || until2p7(s48)*+ -> . % 76.16/76.33 130999[135:Spt:130997.0,130976.1] || -> node4(s47)*. % 76.16/76.33 131001[135:MRR:777.0,130999.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 131013[135:Res:53.1,131001.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 131015[136:Spt:131013.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 131017[136:Res:131015.0,61.1] always3(s47) || -> . % 76.16/76.33 131018[136:SSi:131017.0,78277.0,78280.0,108797.0,130975.0,130999.0] || -> . % 76.16/76.33 131019[136:Spt:131018.0,131013.0,131015.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 131020[136:Spt:131018.0,131013.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 131024[136:Res:131020.0,61.1] always3(s48) || -> . % 76.16/76.33 131025[136:SSi:131024.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.33 131026[134:Spt:131025.0,130974.0,130975.0] || until2p7(s47)*+ -> . % 76.16/76.33 131027[134:Spt:131025.0,130974.1] || -> node4(s46)*. % 76.16/76.33 131029[134:MRR:780.0,131027.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 131036[134:Res:53.1,131029.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 131041[135:Spt:131036.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 131043[135:Res:131041.0,61.1] always3(s46) || -> . % 76.16/76.33 131044[135:SSi:131043.0,78272.0,78276.0,108796.0,130973.0,131027.0] || -> . % 76.16/76.33 131045[135:Spt:131044.0,131036.0,131041.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 131046[135:Spt:131044.0,131036.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 131050[135:Res:131046.0,61.1] always3(s47) || -> . % 76.16/76.33 131051[135:SSi:131050.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.33 131052[133:Spt:131051.0,130972.0,130973.0] || until2p7(s46)*+ -> . % 76.16/76.33 131053[133:Spt:131051.0,130972.1] || -> node4(s45)*. % 76.16/76.33 131055[133:MRR:783.0,131053.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 131058[133:Res:53.1,131055.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 131060[134:Spt:131058.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 131062[134:Res:131060.0,61.1] always3(s45) || -> . % 76.16/76.33 131063[134:SSi:131062.0,78268.0,78271.0,108795.0,130971.0,131053.0] || -> . % 76.16/76.33 131064[134:Spt:131063.0,131058.0,131060.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.33 131065[134:Spt:131063.0,131058.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 131069[134:Res:131065.0,61.1] always3(s46) || -> . % 76.16/76.33 131070[134:SSi:131069.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.33 131071[132:Spt:131070.0,130970.0,130971.0] || until2p7(s45)*+ -> . % 76.16/76.33 131072[132:Spt:131070.0,130970.1] || -> node4(s44)*. % 76.16/76.33 131074[132:MRR:786.0,131072.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.33 131077[132:Res:53.1,131074.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.33 131079[133:Spt:131077.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 131081[133:Res:131079.0,61.1] always3(s44) || -> . % 76.16/76.33 131082[133:SSi:131081.0,78263.0,78267.0,108794.0,130969.0,131072.0] || -> . % 76.16/76.33 131083[133:Spt:131082.0,131077.0,131079.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.33 131084[133:Spt:131082.0,131077.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 131088[133:Res:131084.0,61.1] always3(s45) || -> . % 76.16/76.33 131089[133:SSi:131088.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.33 131090[131:Spt:131089.0,130968.0,130969.0] || until2p7(s44)*+ -> . % 76.16/76.33 131091[131:Spt:131089.0,130968.1] || -> node4(s43)*. % 76.16/76.33 131093[131:MRR:789.0,131091.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.33 131096[131:Res:53.1,131093.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.33 131098[132:Spt:131096.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 131100[132:Res:131098.0,61.1] always3(s43) || -> . % 76.16/76.33 131101[132:SSi:131100.0,78259.0,78262.0,108793.0,130967.0,131091.0] || -> . % 76.16/76.33 131102[132:Spt:131101.0,131096.0,131098.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.33 131103[132:Spt:131101.0,131096.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 131107[132:Res:131103.0,61.1] always3(s44) || -> . % 76.16/76.33 131108[132:SSi:131107.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.33 131109[130:Spt:131108.0,130966.0,130967.0] || until2p7(s43)*+ -> . % 76.16/76.33 131110[130:Spt:131108.0,130966.1] || -> node4(s42)*. % 76.16/76.33 131112[130:MRR:792.0,131110.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.33 131115[130:Res:53.1,131112.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.33 131120[131:Spt:131115.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 131122[131:Res:131120.0,61.1] always3(s42) || -> . % 76.16/76.33 131123[131:SSi:131122.0,78254.0,78258.0,108792.0,130965.0,131110.0] || -> . % 76.16/76.33 131124[131:Spt:131123.0,131115.0,131120.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.33 131125[131:Spt:131123.0,131115.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 131129[131:Res:131125.0,61.1] always3(s43) || -> . % 76.16/76.33 131130[131:SSi:131129.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.33 131131[129:Spt:131130.0,130964.0,130965.0] || until2p7(s42)*+ -> . % 76.16/76.33 131132[129:Spt:131130.0,130964.1] || -> node4(s41)*. % 76.16/76.33 131134[129:MRR:795.0,131132.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.33 131137[129:Res:53.1,131134.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.33 131139[130:Spt:131137.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 131141[130:Res:131139.0,61.1] always3(s41) || -> . % 76.16/76.33 131142[130:SSi:131141.0,78250.0,78253.0,108791.0,130963.0,131132.0] || -> . % 76.16/76.33 131143[130:Spt:131142.0,131137.0,131139.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.33 131144[130:Spt:131142.0,131137.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 131148[130:Res:131144.0,61.1] always3(s42) || -> . % 76.16/76.33 131149[130:SSi:131148.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.33 131150[128:Spt:131149.0,130962.0,130963.0] || until2p7(s41)*+ -> . % 76.16/76.33 131151[128:Spt:131149.0,130962.1] || -> node4(s40)*. % 76.16/76.33 131153[128:MRR:798.0,131151.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.33 131156[128:Res:53.1,131153.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.33 131158[129:Spt:131156.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 131160[129:Res:131158.0,61.1] always3(s40) || -> . % 76.16/76.33 131161[129:SSi:131160.0,78245.0,78249.0,108790.0,130961.0,131151.0] || -> . % 76.16/76.33 131162[129:Spt:131161.0,131156.0,131158.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.33 131163[129:Spt:131161.0,131156.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 131167[129:Res:131163.0,61.1] always3(s41) || -> . % 76.16/76.33 131168[129:SSi:131167.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.33 131169[127:Spt:131168.0,130960.0,130961.0] || until2p7(s40)*+ -> . % 76.16/76.33 131170[127:Spt:131168.0,130960.1] || -> node4(s39)*. % 76.16/76.33 131172[127:MRR:801.0,131170.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.33 131175[127:Res:53.1,131172.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.33 131177[128:Spt:131175.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 131179[128:Res:131177.0,61.1] always3(s39) || -> . % 76.16/76.33 131180[128:SSi:131179.0,78241.0,78244.0,108789.0,130959.0,131170.0] || -> . % 76.16/76.33 131181[128:Spt:131180.0,131175.0,131177.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.33 131182[128:Spt:131180.0,131175.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 131186[128:Res:131182.0,61.1] always3(s40) || -> . % 76.16/76.33 131187[128:SSi:131186.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.33 131188[126:Spt:131187.0,130958.0,130959.0] || until2p7(s39)*+ -> . % 76.16/76.33 131189[126:Spt:131187.0,130958.1] || -> node4(s38)*. % 76.16/76.33 131191[126:MRR:804.0,131189.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.33 131194[126:Res:53.1,131191.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.33 131199[127:Spt:131194.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 131201[127:Res:131199.0,61.1] always3(s38) || -> . % 76.16/76.33 131202[127:SSi:131201.0,78236.0,78240.0,108788.0,130957.0,131189.0] || -> . % 76.16/76.33 131203[127:Spt:131202.0,131194.0,131199.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.33 131204[127:Spt:131202.0,131194.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 131208[127:Res:131204.0,61.1] always3(s39) || -> . % 76.16/76.33 131209[127:SSi:131208.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.33 131210[125:Spt:131209.0,130956.0,130957.0] || until2p7(s38)*+ -> . % 76.16/76.33 131211[125:Spt:131209.0,130956.1] || -> node4(s37)*. % 76.16/76.33 131213[125:MRR:807.0,131211.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.33 131216[125:Res:53.1,131213.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.33 131218[126:Spt:131216.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 131220[126:Res:131218.0,61.1] always3(s37) || -> . % 76.16/76.33 131221[126:SSi:131220.0,78232.0,78235.0,108787.0,130955.0,131211.0] || -> . % 76.16/76.33 131222[126:Spt:131221.0,131216.0,131218.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.33 131223[126:Spt:131221.0,131216.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 131227[126:Res:131223.0,61.1] always3(s38) || -> . % 76.16/76.33 131228[126:SSi:131227.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.33 131229[124:Spt:131228.0,130954.0,130955.0] || until2p7(s37)*+ -> . % 76.16/76.33 131230[124:Spt:131228.0,130954.1] || -> node4(s36)*. % 76.16/76.33 131232[124:MRR:810.0,131230.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.33 131235[124:Res:53.1,131232.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.33 131237[125:Spt:131235.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 131239[125:Res:131237.0,61.1] always3(s36) || -> . % 76.16/76.33 131240[125:SSi:131239.0,78227.0,78231.0,108786.0,130953.0,131230.0] || -> . % 76.16/76.33 131241[125:Spt:131240.0,131235.0,131237.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.33 131242[125:Spt:131240.0,131235.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 131246[125:Res:131242.0,61.1] always3(s37) || -> . % 76.16/76.33 131247[125:SSi:131246.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.33 131248[123:Spt:131247.0,130952.0,130953.0] || until2p7(s36)*+ -> . % 76.16/76.33 131249[123:Spt:131247.0,130952.1] || -> node4(s35)*. % 76.16/76.33 131251[123:MRR:813.0,131249.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.33 131254[123:Res:53.1,131251.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.33 131256[124:Spt:131254.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 131258[124:Res:131256.0,61.1] always3(s35) || -> . % 76.16/76.33 131259[124:SSi:131258.0,78223.0,78226.0,108785.0,130951.0,131249.0] || -> . % 76.16/76.33 131260[124:Spt:131259.0,131254.0,131256.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.33 131261[124:Spt:131259.0,131254.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 131265[124:Res:131261.0,61.1] always3(s36) || -> . % 76.16/76.33 131266[124:SSi:131265.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.33 131267[122:Spt:131266.0,130950.0,130951.0] || until2p7(s35)*+ -> . % 76.16/76.33 131268[122:Spt:131266.0,130950.1] || -> node4(s34)*. % 76.16/76.33 131270[122:MRR:816.0,131268.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.33 131273[122:Res:53.1,131270.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.33 131278[123:Spt:131273.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 131280[123:Res:131278.0,61.1] always3(s34) || -> . % 76.16/76.33 131281[123:SSi:131280.0,78218.0,78222.0,108784.0,130949.0,131268.0] || -> . % 76.16/76.33 131282[123:Spt:131281.0,131273.0,131278.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.33 131283[123:Spt:131281.0,131273.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 131287[123:Res:131283.0,61.1] always3(s35) || -> . % 76.16/76.33 131288[123:SSi:131287.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.33 131289[121:Spt:131288.0,130948.0,130949.0] || until2p7(s34)*+ -> . % 76.16/76.33 131290[121:Spt:131288.0,130948.1] || -> node4(s33)*. % 76.16/76.33 131292[121:MRR:819.0,131290.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.33 131295[121:Res:53.1,131292.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.33 131297[122:Spt:131295.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 131299[122:Res:131297.0,61.1] always3(s33) || -> . % 76.16/76.33 131300[122:SSi:131299.0,78214.0,78217.0,108783.0,130947.0,131290.0] || -> . % 76.16/76.33 131301[122:Spt:131300.0,131295.0,131297.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.33 131302[122:Spt:131300.0,131295.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 131306[122:Res:131302.0,61.1] always3(s34) || -> . % 76.16/76.33 131307[122:SSi:131306.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.33 131308[120:Spt:131307.0,130946.0,130947.0] || until2p7(s33)*+ -> . % 76.16/76.33 131309[120:Spt:131307.0,130946.1] || -> node4(s32)*. % 76.16/76.33 131311[120:MRR:822.0,131309.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.33 131314[120:Res:53.1,131311.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.33 131316[121:Spt:131314.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 131318[121:Res:131316.0,61.1] always3(s32) || -> . % 76.16/76.33 131319[121:SSi:131318.0,78209.0,78213.0,108782.0,130945.0,131309.0] || -> . % 76.16/76.33 131320[121:Spt:131319.0,131314.0,131316.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.33 131321[121:Spt:131319.0,131314.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 131325[121:Res:131321.0,61.1] always3(s33) || -> . % 76.16/76.33 131326[121:SSi:131325.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.33 131327[119:Spt:131326.0,130944.0,130945.0] || until2p7(s32)*+ -> . % 76.16/76.33 131328[119:Spt:131326.0,130944.1] || -> node4(s31)*. % 76.16/76.33 131330[119:MRR:825.0,131328.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.33 131333[119:Res:53.1,131330.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.33 131335[120:Spt:131333.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 131337[120:Res:131335.0,61.1] always3(s31) || -> . % 76.16/76.33 131338[120:SSi:131337.0,78205.0,78208.0,108781.0,130943.0,131328.0] || -> . % 76.16/76.33 131339[120:Spt:131338.0,131333.0,131335.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.33 131340[120:Spt:131338.0,131333.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 131344[120:Res:131340.0,61.1] always3(s32) || -> . % 76.16/76.33 131345[120:SSi:131344.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.33 131346[118:Spt:131345.0,130942.0,130943.0] || until2p7(s31)*+ -> . % 76.16/76.33 131347[118:Spt:131345.0,130942.1] || -> node4(s30)*. % 76.16/76.33 131349[118:MRR:828.0,131347.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.33 131352[118:Res:53.1,131349.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.33 131357[119:Spt:131352.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 131359[119:Res:131357.0,61.1] always3(s30) || -> . % 76.16/76.33 131360[119:SSi:131359.0,78200.0,78204.0,108780.0,130941.0,131347.0] || -> . % 76.16/76.33 131361[119:Spt:131360.0,131352.0,131357.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.33 131362[119:Spt:131360.0,131352.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 131366[119:Res:131362.0,61.1] always3(s31) || -> . % 76.16/76.33 131367[119:SSi:131366.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.33 131368[117:Spt:131367.0,130940.0,130941.0] || until2p7(s30)*+ -> . % 76.16/76.33 131369[117:Spt:131367.0,130940.1] || -> node4(s29)*. % 76.16/76.33 131371[117:MRR:831.0,131369.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.33 131374[117:Res:53.1,131371.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.33 131376[118:Spt:131374.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 131378[118:Res:131376.0,61.1] always3(s29) || -> . % 76.16/76.33 131379[118:SSi:131378.0,78196.0,78199.0,108779.0,130939.0,131369.0] || -> . % 76.16/76.33 131380[118:Spt:131379.0,131374.0,131376.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.33 131381[118:Spt:131379.0,131374.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 131385[118:Res:131381.0,61.1] always3(s30) || -> . % 76.16/76.33 131386[118:SSi:131385.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.33 131387[116:Spt:131386.0,130938.0,130939.0] || until2p7(s29)*+ -> . % 76.16/76.33 131388[116:Spt:131386.0,130938.1] || -> node4(s28)*. % 76.16/76.33 131390[116:MRR:834.0,131388.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.33 131393[116:Res:53.1,131390.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.33 131395[117:Spt:131393.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 131397[117:Res:131395.0,61.1] always3(s28) || -> . % 76.16/76.33 131398[117:SSi:131397.0,78191.0,78195.0,108778.0,130937.0,131388.0] || -> . % 76.16/76.33 131399[117:Spt:131398.0,131393.0,131395.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.33 131400[117:Spt:131398.0,131393.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 131404[117:Res:131400.0,61.1] always3(s29) || -> . % 76.16/76.33 131405[117:SSi:131404.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.33 131406[115:Spt:131405.0,130936.0,130937.0] || until2p7(s28)*+ -> . % 76.16/76.33 131407[115:Spt:131405.0,130936.1] || -> node4(s27)*. % 76.16/76.33 131409[115:MRR:837.0,131407.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.33 131412[115:Res:53.1,131409.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.33 131414[116:Spt:131412.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 131416[116:Res:131414.0,61.1] always3(s27) || -> . % 76.16/76.33 131417[116:SSi:131416.0,78187.0,78190.0,108777.0,130935.0,131407.0] || -> . % 76.16/76.33 131418[116:Spt:131417.0,131412.0,131414.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.33 131419[116:Spt:131417.0,131412.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 131423[116:Res:131419.0,61.1] always3(s28) || -> . % 76.16/76.33 131424[116:SSi:131423.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.33 131425[114:Spt:131424.0,130934.0,130935.0] || until2p7(s27)*+ -> . % 76.16/76.33 131426[114:Spt:131424.0,130934.1] || -> node4(s26)*. % 76.16/76.33 131428[114:MRR:840.0,131426.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.33 131431[114:Res:53.1,131428.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.33 131436[115:Spt:131431.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 131438[115:Res:131436.0,61.1] always3(s26) || -> . % 76.16/76.33 131439[115:SSi:131438.0,78182.0,78186.0,108776.0,130933.0,131426.0] || -> . % 76.16/76.33 131440[115:Spt:131439.0,131431.0,131436.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.33 131441[115:Spt:131439.0,131431.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 131445[115:Res:131441.0,61.1] always3(s27) || -> . % 76.16/76.33 131446[115:SSi:131445.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.33 131447[113:Spt:131446.0,130932.0,130933.0] || until2p7(s26)*+ -> . % 76.16/76.33 131448[113:Spt:131446.0,130932.1] || -> node4(s25)*. % 76.16/76.33 131450[113:MRR:843.0,131448.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.33 131453[113:Res:53.1,131450.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.33 131455[114:Spt:131453.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 131457[114:Res:131455.0,61.1] always3(s25) || -> . % 76.16/76.33 131458[114:SSi:131457.0,78178.0,78181.0,108775.0,130931.0,131448.0] || -> . % 76.16/76.33 131459[114:Spt:131458.0,131453.0,131455.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.33 131460[114:Spt:131458.0,131453.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 131464[114:Res:131460.0,61.1] always3(s26) || -> . % 76.16/76.33 131465[114:SSi:131464.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.33 131466[112:Spt:131465.0,130930.0,130931.0] || until2p7(s25)*+ -> . % 76.16/76.33 131467[112:Spt:131465.0,130930.1] || -> node4(s24)*. % 76.16/76.33 131469[112:MRR:846.0,131467.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.33 131472[112:Res:53.1,131469.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.33 131474[113:Spt:131472.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 131476[113:Res:131474.0,61.1] always3(s24) || -> . % 76.16/76.33 131477[113:SSi:131476.0,78173.0,78177.0,108774.0,130929.0,131467.0] || -> . % 76.16/76.33 131478[113:Spt:131477.0,131472.0,131474.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.33 131479[113:Spt:131477.0,131472.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 131483[113:Res:131479.0,61.1] always3(s25) || -> . % 76.16/76.33 131484[113:SSi:131483.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.33 131485[111:Spt:131484.0,130928.0,130929.0] || until2p7(s24)*+ -> . % 76.16/76.33 131486[111:Spt:131484.0,130928.1] || -> node4(s23)*. % 76.16/76.33 131488[111:MRR:849.0,131486.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.33 131491[111:Res:53.1,131488.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.33 131493[112:Spt:131491.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 131495[112:Res:131493.0,61.1] always3(s23) || -> . % 76.16/76.33 131496[112:SSi:131495.0,78169.0,78172.0,108773.0,130927.0,131486.0] || -> . % 76.16/76.33 131497[112:Spt:131496.0,131491.0,131493.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.33 131498[112:Spt:131496.0,131491.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 131502[112:Res:131498.0,61.1] always3(s24) || -> . % 76.16/76.33 131503[112:SSi:131502.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.33 131504[110:Spt:131503.0,130926.0,130927.0] || until2p7(s23)*+ -> . % 76.16/76.33 131505[110:Spt:131503.0,130926.1] || -> node4(s22)*. % 76.16/76.33 131507[110:MRR:852.0,131505.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.33 131510[110:Res:53.1,131507.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.33 131515[111:Spt:131510.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 131517[111:Res:131515.0,61.1] always3(s22) || -> . % 76.16/76.33 131518[111:SSi:131517.0,78164.0,78168.0,108772.0,130925.0,131505.0] || -> . % 76.16/76.33 131519[111:Spt:131518.0,131510.0,131515.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.33 131520[111:Spt:131518.0,131510.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 131524[111:Res:131520.0,61.1] always3(s23) || -> . % 76.16/76.33 131525[111:SSi:131524.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.33 131526[109:Spt:131525.0,130924.0,130925.0] || until2p7(s22)*+ -> . % 76.16/76.33 131527[109:Spt:131525.0,130924.1] || -> node4(s21)*. % 76.16/76.33 131529[109:MRR:855.0,131527.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.33 131532[109:Res:53.1,131529.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.33 131534[110:Spt:131532.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 131536[110:Res:131534.0,61.1] always3(s21) || -> . % 76.16/76.33 131537[110:SSi:131536.0,78160.0,78163.0,108771.0,130923.0,131527.0] || -> . % 76.16/76.33 131538[110:Spt:131537.0,131532.0,131534.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.33 131539[110:Spt:131537.0,131532.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 131543[110:Res:131539.0,61.1] always3(s22) || -> . % 76.16/76.33 131544[110:SSi:131543.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.33 131545[108:Spt:131544.0,130922.0,130923.0] || until2p7(s21)*+ -> . % 76.16/76.33 131546[108:Spt:131544.0,130922.1] || -> node4(s20)*. % 76.16/76.33 131548[108:MRR:858.0,131546.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.33 131551[108:Res:53.1,131548.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.33 131553[109:Spt:131551.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 131555[109:Res:131553.0,61.1] always3(s20) || -> . % 76.16/76.33 131556[109:SSi:131555.0,78155.0,78159.0,108770.0,130921.0,131546.0] || -> . % 76.16/76.33 131557[109:Spt:131556.0,131551.0,131553.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.33 131558[109:Spt:131556.0,131551.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 131562[109:Res:131558.0,61.1] always3(s21) || -> . % 76.16/76.33 131563[109:SSi:131562.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.33 131564[107:Spt:131563.0,130920.0,130921.0] || until2p7(s20)*+ -> . % 76.16/76.33 131565[107:Spt:131563.0,130920.1] || -> node4(s19)*. % 76.16/76.33 131567[107:MRR:861.0,131565.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.33 131570[107:Res:53.1,131567.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.33 131572[108:Spt:131570.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 131574[108:Res:131572.0,61.1] always3(s19) || -> . % 76.16/76.33 131575[108:SSi:131574.0,78151.0,78154.0,108769.0,130919.0,131565.0] || -> . % 76.16/76.33 131576[108:Spt:131575.0,131570.0,131572.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.33 131577[108:Spt:131575.0,131570.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 131581[108:Res:131577.0,61.1] always3(s20) || -> . % 76.16/76.33 131582[108:SSi:131581.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.33 131583[106:Spt:131582.0,130918.0,130919.0] || until2p7(s19)*+ -> . % 76.16/76.33 131584[106:Spt:131582.0,130918.1] || -> node4(s18)*. % 76.16/76.33 131586[106:MRR:864.0,131584.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.33 131589[106:Res:53.1,131586.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.33 131594[107:Spt:131589.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 131596[107:Res:131594.0,61.1] always3(s18) || -> . % 76.16/76.33 131597[107:SSi:131596.0,78146.0,78150.0,108768.0,130917.0,131584.0] || -> . % 76.16/76.33 131598[107:Spt:131597.0,131589.0,131594.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.33 131599[107:Spt:131597.0,131589.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 131603[107:Res:131599.0,61.1] always3(s19) || -> . % 76.16/76.33 131604[107:SSi:131603.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.33 131605[105:Spt:131604.0,130916.0,130917.0] || until2p7(s18)*+ -> . % 76.16/76.33 131606[105:Spt:131604.0,130916.1] || -> node4(s17)*. % 76.16/76.33 131608[105:MRR:867.0,131606.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.33 131611[105:Res:53.1,131608.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.33 131613[106:Spt:131611.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 131615[106:Res:131613.0,61.1] always3(s17) || -> . % 76.16/76.33 131616[106:SSi:131615.0,78142.0,78145.0,108767.0,130915.0,131606.0] || -> . % 76.16/76.33 131617[106:Spt:131616.0,131611.0,131613.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.33 131618[106:Spt:131616.0,131611.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 131622[106:Res:131618.0,61.1] always3(s18) || -> . % 76.16/76.33 131623[106:SSi:131622.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.33 131624[104:Spt:131623.0,130914.0,130915.0] || until2p7(s17)*+ -> . % 76.16/76.33 131625[104:Spt:131623.0,130914.1] || -> node4(s16)*. % 76.16/76.33 131627[104:MRR:870.0,131625.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.33 131630[104:Res:53.1,131627.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.33 131632[105:Spt:131630.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 131634[105:Res:131632.0,61.1] always3(s16) || -> . % 76.16/76.33 131635[105:SSi:131634.0,78137.0,78141.0,108766.0,130913.0,131625.0] || -> . % 76.16/76.33 131636[105:Spt:131635.0,131630.0,131632.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.33 131637[105:Spt:131635.0,131630.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 131641[105:Res:131637.0,61.1] always3(s17) || -> . % 76.16/76.33 131642[105:SSi:131641.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.33 131643[103:Spt:131642.0,130912.0,130913.0] || until2p7(s16)*+ -> . % 76.16/76.33 131644[103:Spt:131642.0,130912.1] || -> node4(s15)*. % 76.16/76.33 131646[103:MRR:873.0,131644.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.33 131649[103:Res:53.1,131646.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.33 131651[104:Spt:131649.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 131653[104:Res:131651.0,61.1] always3(s15) || -> . % 76.16/76.33 131654[104:SSi:131653.0,78133.0,78136.0,108765.0,130911.0,131644.0] || -> . % 76.16/76.33 131655[104:Spt:131654.0,131649.0,131651.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.33 131656[104:Spt:131654.0,131649.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 131660[104:Res:131656.0,61.1] always3(s16) || -> . % 76.16/76.33 131661[104:SSi:131660.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.33 131662[102:Spt:131661.0,130910.0,130911.0] || until2p7(s15)*+ -> . % 76.16/76.33 131663[102:Spt:131661.0,130910.1] || -> node4(s14)*. % 76.16/76.33 131665[102:MRR:876.0,131663.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.33 131668[102:Res:53.1,131665.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.33 131673[103:Spt:131668.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 131675[103:Res:131673.0,61.1] always3(s14) || -> . % 76.16/76.33 131676[103:SSi:131675.0,78128.0,78132.0,108764.0,130909.0,131663.0] || -> . % 76.16/76.33 131677[103:Spt:131676.0,131668.0,131673.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.33 131678[103:Spt:131676.0,131668.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 131682[103:Res:131678.0,61.1] always3(s15) || -> . % 76.16/76.33 131683[103:SSi:131682.0,78133.0,78136.0,108765.0] || -> . % 76.16/76.33 131684[101:Spt:131683.0,130908.0,130909.0] || until2p7(s14)*+ -> . % 76.16/76.33 131685[101:Spt:131683.0,130908.1] || -> node4(s13)*. % 76.16/76.33 131687[101:MRR:879.0,131685.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.33 131690[101:Res:53.1,131687.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.33 131692[102:Spt:131690.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 131694[102:Res:131692.0,61.1] always3(s13) || -> . % 76.16/76.33 131695[102:SSi:131694.0,78124.0,78127.0,108763.0,130907.0,131685.0] || -> . % 76.16/76.33 131696[102:Spt:131695.0,131690.0,131692.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.33 131697[102:Spt:131695.0,131690.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 131701[102:Res:131697.0,61.1] always3(s14) || -> . % 76.16/76.33 131702[102:SSi:131701.0,78128.0,78132.0,108764.0] || -> . % 76.16/76.33 131703[100:Spt:131702.0,130906.0,130907.0] || until2p7(s13)*+ -> . % 76.16/76.33 131704[100:Spt:131702.0,130906.1] || -> node4(s12)*. % 76.16/76.33 131706[100:MRR:882.0,131704.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.33 131709[100:Res:53.1,131706.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.33 131711[101:Spt:131709.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 131713[101:Res:131711.0,61.1] always3(s12) || -> . % 76.16/76.33 131714[101:SSi:131713.0,78119.0,78123.0,108762.0,130905.0,131704.0] || -> . % 76.16/76.33 131715[101:Spt:131714.0,131709.0,131711.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.33 131716[101:Spt:131714.0,131709.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 131720[101:Res:131716.0,61.1] always3(s13) || -> . % 76.16/76.33 131721[101:SSi:131720.0,78124.0,78127.0,108763.0] || -> . % 76.16/76.33 131722[99:Spt:131721.0,130904.0,130905.0] || until2p7(s12)*+ -> . % 76.16/76.33 131723[99:Spt:131721.0,130904.1] || -> node4(s11)*. % 76.16/76.33 131725[99:MRR:885.0,131723.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.33 131728[99:Res:53.1,131725.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.33 131730[100:Spt:131728.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 131732[100:Res:131730.0,61.1] always3(s11) || -> . % 76.16/76.33 131733[100:SSi:131732.0,78115.0,78118.0,108761.0,130903.0,131723.0] || -> . % 76.16/76.33 131734[100:Spt:131733.0,131728.0,131730.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.33 131735[100:Spt:131733.0,131728.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 131739[100:Res:131735.0,61.1] always3(s12) || -> . % 76.16/76.33 131740[100:SSi:131739.0,78119.0,78123.0,108762.0] || -> . % 76.16/76.33 131741[98:Spt:131740.0,130902.0,130903.0] || until2p7(s11)*+ -> . % 76.16/76.33 131742[98:Spt:131740.0,130902.1] || -> node4(s10)*. % 76.16/76.33 131744[98:MRR:888.0,131742.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.33 131747[98:Res:53.1,131744.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.33 131752[99:Spt:131747.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 131754[99:Res:131752.0,61.1] always3(s10) || -> . % 76.16/76.33 131755[99:SSi:131754.0,78110.0,78114.0,108760.0,130901.0,131742.0] || -> . % 76.16/76.33 131756[99:Spt:131755.0,131747.0,131752.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.33 131757[99:Spt:131755.0,131747.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 131761[99:Res:131757.0,61.1] always3(s11) || -> . % 76.16/76.33 131762[99:SSi:131761.0,78115.0,78118.0,108761.0] || -> . % 76.16/76.33 131763[97:Spt:131762.0,130900.0,130901.0] || until2p7(s10)*+ -> . % 76.16/76.33 131764[97:Spt:131762.0,130900.1] || -> node4(s9)*. % 76.16/76.33 131766[97:MRR:891.0,131764.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.33 131769[97:Res:53.1,131766.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.33 131771[98:Spt:131769.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 131773[98:Res:131771.0,61.1] always3(s9) || -> . % 76.16/76.33 131774[98:SSi:131773.0,78106.0,78109.0,108759.0,130899.0,131764.0] || -> . % 76.16/76.33 131775[98:Spt:131774.0,131769.0,131771.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.33 131776[98:Spt:131774.0,131769.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 131780[98:Res:131776.0,61.1] always3(s10) || -> . % 76.16/76.33 131781[98:SSi:131780.0,78110.0,78114.0,108760.0] || -> . % 76.16/76.33 131782[96:Spt:131781.0,130898.0,130899.0] || until2p7(s9)*+ -> . % 76.16/76.33 131783[96:Spt:131781.0,130898.1] || -> node4(s8)*. % 76.16/76.33 131785[96:MRR:894.0,131783.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.33 131788[96:Res:53.1,131785.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.33 131790[96:MRR:131788.0,130888.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 131792[96:Res:131790.0,61.1] always3(s9) || -> . % 76.16/76.33 131793[96:SSi:131792.0,78106.0,78109.0,108759.0] || -> . % 76.16/76.33 131794[94:Spt:131793.0,130735.0,130738.0] || trans(s49,s8)*+ -> . % 76.16/76.33 131795[94:Spt:131793.0,130735.1,130735.2,130735.3,130735.4,130735.5] || -> trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.33 131797[94:MRR:130737.1,131794.0] xuntil6(s49) || -> trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.33 131798[95:Spt:131795.0] || -> trans(s49,s7)*. % 76.16/76.33 131799[95:Res:131798.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s7)*. % 76.16/76.33 131801[95:Res:131798.0,60.0] || -> node2(s49,s7)*. % 76.16/76.33 131802[95:SSi:131799.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s7)*. % 76.16/76.33 131803[95:Res:131801.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)*. % 76.16/76.33 131944[95:SoR:131803.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)*. % 76.16/76.33 131946[95:SoR:131944.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)* xuntil6(s49). % 76.16/76.33 131947[95:SSi:131946.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s7,c_busy)* xuntil6(s49). % 76.16/76.33 131948[96:Spt:131947.1] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.33 131950[96:Res:131948.0,61.1] always3(s7) || -> . % 76.16/76.33 131951[96:SSi:131950.0,78097.0,78100.0,108757.0] || -> . % 76.16/76.33 131952[96:Spt:131951.0,131947.1,131948.0] || m_main_v_state(s7,c_busy)*+ -> . % 76.16/76.33 131953[96:Spt:131951.0,131947.0,131947.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 131957[96:MRR:131944.2,131952.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 131958[96:Res:53.1,131953.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 131960[96:MRR:131958.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 131961[96:MRR:131802.0,131960.0] || -> until2p7(s7)*. % 76.16/76.33 131962[96:MRR:203.0,131961.0] || -> until2p7(s8)* node4(s7). % 76.16/76.33 131963[97:Spt:131962.0] || -> until2p7(s8)*. % 76.16/76.33 131964[97:MRR:204.0,131963.0] || -> until2p7(s9)* node4(s8). % 76.16/76.33 131965[98:Spt:131964.0] || -> until2p7(s9)*. % 76.16/76.33 131966[98:MRR:205.0,131965.0] || -> until2p7(s10)* node4(s9). % 76.16/76.33 131967[99:Spt:131966.0] || -> until2p7(s10)*. % 76.16/76.33 131968[99:MRR:206.0,131967.0] || -> until2p7(s11)* node4(s10). % 76.16/76.33 131969[100:Spt:131968.0] || -> until2p7(s11)*. % 76.16/76.33 131970[100:MRR:207.0,131969.0] || -> until2p7(s12)* node4(s11). % 76.16/76.33 131971[101:Spt:131970.0] || -> until2p7(s12)*. % 76.16/76.33 131972[101:MRR:208.0,131971.0] || -> until2p7(s13)* node4(s12). % 76.16/76.33 131973[102:Spt:131972.0] || -> until2p7(s13)*. % 76.16/76.33 131974[102:MRR:209.0,131973.0] || -> until2p7(s14)* node4(s13). % 76.16/76.33 131975[103:Spt:131974.0] || -> until2p7(s14)*. % 76.16/76.33 131976[103:MRR:210.0,131975.0] || -> until2p7(s15)* node4(s14). % 76.16/76.33 131977[104:Spt:131976.0] || -> until2p7(s15)*. % 76.16/76.33 131978[104:MRR:211.0,131977.0] || -> until2p7(s16)* node4(s15). % 76.16/76.33 131979[105:Spt:131978.0] || -> until2p7(s16)*. % 76.16/76.33 131980[105:MRR:212.0,131979.0] || -> until2p7(s17)* node4(s16). % 76.16/76.33 131981[106:Spt:131980.0] || -> until2p7(s17)*. % 76.16/76.33 131982[106:MRR:213.0,131981.0] || -> until2p7(s18)* node4(s17). % 76.16/76.33 131983[107:Spt:131982.0] || -> until2p7(s18)*. % 76.16/76.33 131984[107:MRR:214.0,131983.0] || -> until2p7(s19)* node4(s18). % 76.16/76.33 131985[108:Spt:131984.0] || -> until2p7(s19)*. % 76.16/76.33 131986[108:MRR:215.0,131985.0] || -> until2p7(s20)* node4(s19). % 76.16/76.33 131987[109:Spt:131986.0] || -> until2p7(s20)*. % 76.16/76.33 131988[109:MRR:216.0,131987.0] || -> until2p7(s21)* node4(s20). % 76.16/76.33 131989[110:Spt:131988.0] || -> until2p7(s21)*. % 76.16/76.33 131990[110:MRR:217.0,131989.0] || -> until2p7(s22)* node4(s21). % 76.16/76.33 131991[111:Spt:131990.0] || -> until2p7(s22)*. % 76.16/76.33 131992[111:MRR:218.0,131991.0] || -> until2p7(s23)* node4(s22). % 76.16/76.33 131993[112:Spt:131992.0] || -> until2p7(s23)*. % 76.16/76.33 131994[112:MRR:219.0,131993.0] || -> until2p7(s24)* node4(s23). % 76.16/76.33 131995[113:Spt:131994.0] || -> until2p7(s24)*. % 76.16/76.33 131996[113:MRR:220.0,131995.0] || -> until2p7(s25)* node4(s24). % 76.16/76.33 131997[114:Spt:131996.0] || -> until2p7(s25)*. % 76.16/76.33 131998[114:MRR:221.0,131997.0] || -> until2p7(s26)* node4(s25). % 76.16/76.33 131999[115:Spt:131998.0] || -> until2p7(s26)*. % 76.16/76.33 132000[115:MRR:222.0,131999.0] || -> until2p7(s27)* node4(s26). % 76.16/76.33 132001[116:Spt:132000.0] || -> until2p7(s27)*. % 76.16/76.33 132002[116:MRR:223.0,132001.0] || -> until2p7(s28)* node4(s27). % 76.16/76.33 132003[117:Spt:132002.0] || -> until2p7(s28)*. % 76.16/76.33 132004[117:MRR:224.0,132003.0] || -> until2p7(s29)* node4(s28). % 76.16/76.33 132005[118:Spt:132004.0] || -> until2p7(s29)*. % 76.16/76.33 132006[118:MRR:225.0,132005.0] || -> until2p7(s30)* node4(s29). % 76.16/76.33 132007[119:Spt:132006.0] || -> until2p7(s30)*. % 76.16/76.33 132008[119:MRR:226.0,132007.0] || -> until2p7(s31)* node4(s30). % 76.16/76.33 132009[120:Spt:132008.0] || -> until2p7(s31)*. % 76.16/76.33 132010[120:MRR:227.0,132009.0] || -> until2p7(s32)* node4(s31). % 76.16/76.33 132011[121:Spt:132010.0] || -> until2p7(s32)*. % 76.16/76.33 132012[121:MRR:228.0,132011.0] || -> until2p7(s33)* node4(s32). % 76.16/76.33 132013[122:Spt:132012.0] || -> until2p7(s33)*. % 76.16/76.33 132014[122:MRR:229.0,132013.0] || -> until2p7(s34)* node4(s33). % 76.16/76.33 132015[123:Spt:132014.0] || -> until2p7(s34)*. % 76.16/76.33 132016[123:MRR:230.0,132015.0] || -> until2p7(s35)* node4(s34). % 76.16/76.33 132017[124:Spt:132016.0] || -> until2p7(s35)*. % 76.16/76.33 132018[124:MRR:231.0,132017.0] || -> until2p7(s36)* node4(s35). % 76.16/76.33 132019[125:Spt:132018.0] || -> until2p7(s36)*. % 76.16/76.33 132020[125:MRR:232.0,132019.0] || -> until2p7(s37)* node4(s36). % 76.16/76.33 132021[126:Spt:132020.0] || -> until2p7(s37)*. % 76.16/76.33 132022[126:MRR:235.0,132021.0] || -> until2p7(s38)* node4(s37). % 76.16/76.33 132023[127:Spt:132022.0] || -> until2p7(s38)*. % 76.16/76.33 132024[127:MRR:236.0,132023.0] || -> until2p7(s39)* node4(s38). % 76.16/76.33 132025[128:Spt:132024.0] || -> until2p7(s39)*. % 76.16/76.33 132026[128:MRR:237.0,132025.0] || -> until2p7(s40)* node4(s39). % 76.16/76.33 132027[129:Spt:132026.0] || -> until2p7(s40)*. % 76.16/76.33 132028[129:MRR:238.0,132027.0] || -> until2p7(s41)* node4(s40). % 76.16/76.33 132029[130:Spt:132028.0] || -> until2p7(s41)*. % 76.16/76.33 132030[130:MRR:239.0,132029.0] || -> until2p7(s42)* node4(s41). % 76.16/76.33 132031[131:Spt:132030.0] || -> until2p7(s42)*. % 76.16/76.33 132032[131:MRR:240.0,132031.0] || -> until2p7(s43)* node4(s42). % 76.16/76.33 132033[132:Spt:132032.0] || -> until2p7(s43)*. % 76.16/76.33 132034[132:MRR:241.0,132033.0] || -> until2p7(s44)* node4(s43). % 76.16/76.33 132035[133:Spt:132034.0] || -> until2p7(s44)*. % 76.16/76.33 132036[133:MRR:539.0,132035.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 132037[134:Spt:132036.0] || -> until2p7(s45)*. % 76.16/76.33 132038[134:MRR:544.0,132037.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 132039[135:Spt:132038.0] || -> until2p7(s46)*. % 76.16/76.33 132040[135:MRR:549.0,132039.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 132041[136:Spt:132040.0] || -> until2p7(s47)*. % 76.16/76.33 132042[136:MRR:554.0,132041.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 132043[137:Spt:132042.0] || -> until2p7(s48)*. % 76.16/76.33 132044[137:MRR:559.0,132043.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 132045[138:Spt:132044.0] || -> until2p7(s49)*. % 76.16/76.33 132046[138:MRR:194.0,132045.0] || -> node4(s49)*. % 76.16/76.33 132047[138:MRR:131957.0,132046.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 132048[138:Res:53.1,132047.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 132050[138:MRR:132048.0,78381.0] || -> . % 76.16/76.33 132051[138:Spt:132050.0,132044.0,132045.0] || until2p7(s49)*+ -> . % 76.16/76.33 132052[138:Spt:132050.0,132044.1] || -> node4(s48)*. % 76.16/76.33 132053[138:MRR:78384.0,132052.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 132056[138:Res:53.1,132053.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 132059[138:Res:132056.0,61.1] always3(s48) || -> . % 76.16/76.33 132060[138:SSi:132059.0,78281.0,78387.0,108798.0,132043.0,132052.0] || -> . % 76.16/76.33 132061[137:Spt:132060.0,132042.0,132043.0] || until2p7(s48)*+ -> . % 76.16/76.33 132062[137:Spt:132060.0,132042.1] || -> node4(s47)*. % 76.16/76.33 132064[137:MRR:777.0,132062.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 132079[137:Res:53.1,132064.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 132084[138:Spt:132079.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 132086[138:Res:132084.0,61.1] always3(s47) || -> . % 76.16/76.33 132087[138:SSi:132086.0,78277.0,78280.0,108797.0,132041.0,132062.0] || -> . % 76.16/76.33 132088[138:Spt:132087.0,132079.0,132084.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 132089[138:Spt:132087.0,132079.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 132093[138:Res:132089.0,61.1] always3(s48) || -> . % 76.16/76.33 132094[138:SSi:132093.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.33 132095[136:Spt:132094.0,132040.0,132041.0] || until2p7(s47)*+ -> . % 76.16/76.33 132096[136:Spt:132094.0,132040.1] || -> node4(s46)*. % 76.16/76.33 132098[136:MRR:780.0,132096.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 132105[136:Res:53.1,132098.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 132107[137:Spt:132105.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 132109[137:Res:132107.0,61.1] always3(s46) || -> . % 76.16/76.33 132110[137:SSi:132109.0,78272.0,78276.0,108796.0,132039.0,132096.0] || -> . % 76.16/76.33 132111[137:Spt:132110.0,132105.0,132107.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 132112[137:Spt:132110.0,132105.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 132116[137:Res:132112.0,61.1] always3(s47) || -> . % 76.16/76.33 132117[137:SSi:132116.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.33 132118[135:Spt:132117.0,132038.0,132039.0] || until2p7(s46)*+ -> . % 76.16/76.33 132119[135:Spt:132117.0,132038.1] || -> node4(s45)*. % 76.16/76.33 132121[135:MRR:783.0,132119.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 132124[135:Res:53.1,132121.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 132129[136:Spt:132124.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 132131[136:Res:132129.0,61.1] always3(s45) || -> . % 76.16/76.33 132132[136:SSi:132131.0,78268.0,78271.0,108795.0,132037.0,132119.0] || -> . % 76.16/76.33 132133[136:Spt:132132.0,132124.0,132129.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.33 132134[136:Spt:132132.0,132124.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 132138[136:Res:132134.0,61.1] always3(s46) || -> . % 76.16/76.33 132139[136:SSi:132138.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.33 132140[134:Spt:132139.0,132036.0,132037.0] || until2p7(s45)*+ -> . % 76.16/76.33 132141[134:Spt:132139.0,132036.1] || -> node4(s44)*. % 76.16/76.33 132143[134:MRR:786.0,132141.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.33 132146[134:Res:53.1,132143.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.33 132148[135:Spt:132146.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 132150[135:Res:132148.0,61.1] always3(s44) || -> . % 76.16/76.33 132151[135:SSi:132150.0,78263.0,78267.0,108794.0,132035.0,132141.0] || -> . % 76.16/76.33 132152[135:Spt:132151.0,132146.0,132148.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.33 132153[135:Spt:132151.0,132146.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 132157[135:Res:132153.0,61.1] always3(s45) || -> . % 76.16/76.33 132158[135:SSi:132157.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.33 132159[133:Spt:132158.0,132034.0,132035.0] || until2p7(s44)*+ -> . % 76.16/76.33 132160[133:Spt:132158.0,132034.1] || -> node4(s43)*. % 76.16/76.33 132162[133:MRR:789.0,132160.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.33 132165[133:Res:53.1,132162.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.33 132167[134:Spt:132165.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 132169[134:Res:132167.0,61.1] always3(s43) || -> . % 76.16/76.33 132170[134:SSi:132169.0,78259.0,78262.0,108793.0,132033.0,132160.0] || -> . % 76.16/76.33 132171[134:Spt:132170.0,132165.0,132167.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.33 132172[134:Spt:132170.0,132165.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 132176[134:Res:132172.0,61.1] always3(s44) || -> . % 76.16/76.33 132177[134:SSi:132176.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.33 132178[132:Spt:132177.0,132032.0,132033.0] || until2p7(s43)*+ -> . % 76.16/76.33 132179[132:Spt:132177.0,132032.1] || -> node4(s42)*. % 76.16/76.33 132181[132:MRR:792.0,132179.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.33 132184[132:Res:53.1,132181.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.33 132186[133:Spt:132184.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 132188[133:Res:132186.0,61.1] always3(s42) || -> . % 76.16/76.33 132189[133:SSi:132188.0,78254.0,78258.0,108792.0,132031.0,132179.0] || -> . % 76.16/76.33 132190[133:Spt:132189.0,132184.0,132186.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.33 132191[133:Spt:132189.0,132184.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 132195[133:Res:132191.0,61.1] always3(s43) || -> . % 76.16/76.33 132196[133:SSi:132195.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.33 132197[131:Spt:132196.0,132030.0,132031.0] || until2p7(s42)*+ -> . % 76.16/76.33 132198[131:Spt:132196.0,132030.1] || -> node4(s41)*. % 76.16/76.33 132200[131:MRR:795.0,132198.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.33 132203[131:Res:53.1,132200.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.33 132208[132:Spt:132203.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 132210[132:Res:132208.0,61.1] always3(s41) || -> . % 76.16/76.33 132211[132:SSi:132210.0,78250.0,78253.0,108791.0,132029.0,132198.0] || -> . % 76.16/76.33 132212[132:Spt:132211.0,132203.0,132208.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.33 132213[132:Spt:132211.0,132203.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 132217[132:Res:132213.0,61.1] always3(s42) || -> . % 76.16/76.33 132218[132:SSi:132217.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.33 132219[130:Spt:132218.0,132028.0,132029.0] || until2p7(s41)*+ -> . % 76.16/76.33 132220[130:Spt:132218.0,132028.1] || -> node4(s40)*. % 76.16/76.33 132222[130:MRR:798.0,132220.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.33 132225[130:Res:53.1,132222.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.33 132227[131:Spt:132225.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 132229[131:Res:132227.0,61.1] always3(s40) || -> . % 76.16/76.33 132230[131:SSi:132229.0,78245.0,78249.0,108790.0,132027.0,132220.0] || -> . % 76.16/76.33 132231[131:Spt:132230.0,132225.0,132227.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.33 132232[131:Spt:132230.0,132225.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 132236[131:Res:132232.0,61.1] always3(s41) || -> . % 76.16/76.33 132237[131:SSi:132236.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.33 132238[129:Spt:132237.0,132026.0,132027.0] || until2p7(s40)*+ -> . % 76.16/76.33 132239[129:Spt:132237.0,132026.1] || -> node4(s39)*. % 76.16/76.33 132241[129:MRR:801.0,132239.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.33 132244[129:Res:53.1,132241.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.33 132246[130:Spt:132244.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 132248[130:Res:132246.0,61.1] always3(s39) || -> . % 76.16/76.33 132249[130:SSi:132248.0,78241.0,78244.0,108789.0,132025.0,132239.0] || -> . % 76.16/76.33 132250[130:Spt:132249.0,132244.0,132246.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.33 132251[130:Spt:132249.0,132244.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 132255[130:Res:132251.0,61.1] always3(s40) || -> . % 76.16/76.33 132256[130:SSi:132255.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.33 132257[128:Spt:132256.0,132024.0,132025.0] || until2p7(s39)*+ -> . % 76.16/76.33 132258[128:Spt:132256.0,132024.1] || -> node4(s38)*. % 76.16/76.33 132260[128:MRR:804.0,132258.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.33 132263[128:Res:53.1,132260.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.33 132265[129:Spt:132263.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 132267[129:Res:132265.0,61.1] always3(s38) || -> . % 76.16/76.33 132268[129:SSi:132267.0,78236.0,78240.0,108788.0,132023.0,132258.0] || -> . % 76.16/76.33 132269[129:Spt:132268.0,132263.0,132265.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.33 132270[129:Spt:132268.0,132263.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 132274[129:Res:132270.0,61.1] always3(s39) || -> . % 76.16/76.33 132275[129:SSi:132274.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.33 132276[127:Spt:132275.0,132022.0,132023.0] || until2p7(s38)*+ -> . % 76.16/76.33 132277[127:Spt:132275.0,132022.1] || -> node4(s37)*. % 76.16/76.33 132279[127:MRR:807.0,132277.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.33 132282[127:Res:53.1,132279.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.33 132287[128:Spt:132282.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 132289[128:Res:132287.0,61.1] always3(s37) || -> . % 76.16/76.33 132290[128:SSi:132289.0,78232.0,78235.0,108787.0,132021.0,132277.0] || -> . % 76.16/76.33 132291[128:Spt:132290.0,132282.0,132287.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.33 132292[128:Spt:132290.0,132282.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 132296[128:Res:132292.0,61.1] always3(s38) || -> . % 76.16/76.33 132297[128:SSi:132296.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.33 132298[126:Spt:132297.0,132020.0,132021.0] || until2p7(s37)*+ -> . % 76.16/76.33 132299[126:Spt:132297.0,132020.1] || -> node4(s36)*. % 76.16/76.33 132301[126:MRR:810.0,132299.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.33 132304[126:Res:53.1,132301.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.33 132306[127:Spt:132304.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 132308[127:Res:132306.0,61.1] always3(s36) || -> . % 76.16/76.33 132309[127:SSi:132308.0,78227.0,78231.0,108786.0,132019.0,132299.0] || -> . % 76.16/76.33 132310[127:Spt:132309.0,132304.0,132306.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.33 132311[127:Spt:132309.0,132304.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 132315[127:Res:132311.0,61.1] always3(s37) || -> . % 76.16/76.33 132316[127:SSi:132315.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.33 132317[125:Spt:132316.0,132018.0,132019.0] || until2p7(s36)*+ -> . % 76.16/76.33 132318[125:Spt:132316.0,132018.1] || -> node4(s35)*. % 76.16/76.33 132320[125:MRR:813.0,132318.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.33 132323[125:Res:53.1,132320.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.33 132325[126:Spt:132323.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 132327[126:Res:132325.0,61.1] always3(s35) || -> . % 76.16/76.33 132328[126:SSi:132327.0,78223.0,78226.0,108785.0,132017.0,132318.0] || -> . % 76.16/76.33 132329[126:Spt:132328.0,132323.0,132325.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.33 132330[126:Spt:132328.0,132323.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 132334[126:Res:132330.0,61.1] always3(s36) || -> . % 76.16/76.33 132335[126:SSi:132334.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.33 132336[124:Spt:132335.0,132016.0,132017.0] || until2p7(s35)*+ -> . % 76.16/76.33 132337[124:Spt:132335.0,132016.1] || -> node4(s34)*. % 76.16/76.33 132339[124:MRR:816.0,132337.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.33 132342[124:Res:53.1,132339.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.33 132344[125:Spt:132342.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 132346[125:Res:132344.0,61.1] always3(s34) || -> . % 76.16/76.33 132347[125:SSi:132346.0,78218.0,78222.0,108784.0,132015.0,132337.0] || -> . % 76.16/76.33 132348[125:Spt:132347.0,132342.0,132344.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.33 132349[125:Spt:132347.0,132342.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 132353[125:Res:132349.0,61.1] always3(s35) || -> . % 76.16/76.33 132354[125:SSi:132353.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.33 132355[123:Spt:132354.0,132014.0,132015.0] || until2p7(s34)*+ -> . % 76.16/76.33 132356[123:Spt:132354.0,132014.1] || -> node4(s33)*. % 76.16/76.33 132358[123:MRR:819.0,132356.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.33 132361[123:Res:53.1,132358.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.33 132366[124:Spt:132361.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 132368[124:Res:132366.0,61.1] always3(s33) || -> . % 76.16/76.33 132369[124:SSi:132368.0,78214.0,78217.0,108783.0,132013.0,132356.0] || -> . % 76.16/76.33 132370[124:Spt:132369.0,132361.0,132366.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.33 132371[124:Spt:132369.0,132361.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 132375[124:Res:132371.0,61.1] always3(s34) || -> . % 76.16/76.33 132376[124:SSi:132375.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.33 132377[122:Spt:132376.0,132012.0,132013.0] || until2p7(s33)*+ -> . % 76.16/76.33 132378[122:Spt:132376.0,132012.1] || -> node4(s32)*. % 76.16/76.33 132380[122:MRR:822.0,132378.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.33 132383[122:Res:53.1,132380.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.33 132385[123:Spt:132383.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 132387[123:Res:132385.0,61.1] always3(s32) || -> . % 76.16/76.33 132388[123:SSi:132387.0,78209.0,78213.0,108782.0,132011.0,132378.0] || -> . % 76.16/76.33 132389[123:Spt:132388.0,132383.0,132385.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.33 132390[123:Spt:132388.0,132383.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 132394[123:Res:132390.0,61.1] always3(s33) || -> . % 76.16/76.33 132395[123:SSi:132394.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.33 132396[121:Spt:132395.0,132010.0,132011.0] || until2p7(s32)*+ -> . % 76.16/76.33 132397[121:Spt:132395.0,132010.1] || -> node4(s31)*. % 76.16/76.33 132399[121:MRR:825.0,132397.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.33 132402[121:Res:53.1,132399.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.33 132404[122:Spt:132402.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 132406[122:Res:132404.0,61.1] always3(s31) || -> . % 76.16/76.33 132407[122:SSi:132406.0,78205.0,78208.0,108781.0,132009.0,132397.0] || -> . % 76.16/76.33 132408[122:Spt:132407.0,132402.0,132404.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.33 132409[122:Spt:132407.0,132402.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 132413[122:Res:132409.0,61.1] always3(s32) || -> . % 76.16/76.33 132414[122:SSi:132413.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.33 132415[120:Spt:132414.0,132008.0,132009.0] || until2p7(s31)*+ -> . % 76.16/76.33 132416[120:Spt:132414.0,132008.1] || -> node4(s30)*. % 76.16/76.33 132418[120:MRR:828.0,132416.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.33 132421[120:Res:53.1,132418.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.33 132423[121:Spt:132421.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 132425[121:Res:132423.0,61.1] always3(s30) || -> . % 76.16/76.33 132426[121:SSi:132425.0,78200.0,78204.0,108780.0,132007.0,132416.0] || -> . % 76.16/76.33 132427[121:Spt:132426.0,132421.0,132423.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.33 132428[121:Spt:132426.0,132421.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 132432[121:Res:132428.0,61.1] always3(s31) || -> . % 76.16/76.33 132433[121:SSi:132432.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.33 132434[119:Spt:132433.0,132006.0,132007.0] || until2p7(s30)*+ -> . % 76.16/76.33 132435[119:Spt:132433.0,132006.1] || -> node4(s29)*. % 76.16/76.33 132437[119:MRR:831.0,132435.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.33 132440[119:Res:53.1,132437.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.33 132445[120:Spt:132440.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 132447[120:Res:132445.0,61.1] always3(s29) || -> . % 76.16/76.33 132448[120:SSi:132447.0,78196.0,78199.0,108779.0,132005.0,132435.0] || -> . % 76.16/76.33 132449[120:Spt:132448.0,132440.0,132445.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.33 132450[120:Spt:132448.0,132440.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 132454[120:Res:132450.0,61.1] always3(s30) || -> . % 76.16/76.33 132455[120:SSi:132454.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.33 132456[118:Spt:132455.0,132004.0,132005.0] || until2p7(s29)*+ -> . % 76.16/76.33 132457[118:Spt:132455.0,132004.1] || -> node4(s28)*. % 76.16/76.33 132459[118:MRR:834.0,132457.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.33 132462[118:Res:53.1,132459.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.33 132464[119:Spt:132462.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 132466[119:Res:132464.0,61.1] always3(s28) || -> . % 76.16/76.33 132467[119:SSi:132466.0,78191.0,78195.0,108778.0,132003.0,132457.0] || -> . % 76.16/76.33 132468[119:Spt:132467.0,132462.0,132464.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.33 132469[119:Spt:132467.0,132462.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 132473[119:Res:132469.0,61.1] always3(s29) || -> . % 76.16/76.33 132474[119:SSi:132473.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.33 132475[117:Spt:132474.0,132002.0,132003.0] || until2p7(s28)*+ -> . % 76.16/76.33 132476[117:Spt:132474.0,132002.1] || -> node4(s27)*. % 76.16/76.33 132478[117:MRR:837.0,132476.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.33 132481[117:Res:53.1,132478.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.33 132483[118:Spt:132481.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 132485[118:Res:132483.0,61.1] always3(s27) || -> . % 76.16/76.33 132486[118:SSi:132485.0,78187.0,78190.0,108777.0,132001.0,132476.0] || -> . % 76.16/76.33 132487[118:Spt:132486.0,132481.0,132483.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.33 132488[118:Spt:132486.0,132481.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 132492[118:Res:132488.0,61.1] always3(s28) || -> . % 76.16/76.33 132493[118:SSi:132492.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.33 132494[116:Spt:132493.0,132000.0,132001.0] || until2p7(s27)*+ -> . % 76.16/76.33 132495[116:Spt:132493.0,132000.1] || -> node4(s26)*. % 76.16/76.33 132497[116:MRR:840.0,132495.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.33 132500[116:Res:53.1,132497.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.33 132502[117:Spt:132500.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 132504[117:Res:132502.0,61.1] always3(s26) || -> . % 76.16/76.33 132505[117:SSi:132504.0,78182.0,78186.0,108776.0,131999.0,132495.0] || -> . % 76.16/76.33 132506[117:Spt:132505.0,132500.0,132502.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.33 132507[117:Spt:132505.0,132500.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 132511[117:Res:132507.0,61.1] always3(s27) || -> . % 76.16/76.33 132512[117:SSi:132511.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.33 132513[115:Spt:132512.0,131998.0,131999.0] || until2p7(s26)*+ -> . % 76.16/76.33 132514[115:Spt:132512.0,131998.1] || -> node4(s25)*. % 76.16/76.33 132516[115:MRR:843.0,132514.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.33 132519[115:Res:53.1,132516.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.33 132524[116:Spt:132519.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 132526[116:Res:132524.0,61.1] always3(s25) || -> . % 76.16/76.33 132527[116:SSi:132526.0,78178.0,78181.0,108775.0,131997.0,132514.0] || -> . % 76.16/76.33 132528[116:Spt:132527.0,132519.0,132524.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.33 132529[116:Spt:132527.0,132519.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 132533[116:Res:132529.0,61.1] always3(s26) || -> . % 76.16/76.33 132534[116:SSi:132533.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.33 132535[114:Spt:132534.0,131996.0,131997.0] || until2p7(s25)*+ -> . % 76.16/76.33 132536[114:Spt:132534.0,131996.1] || -> node4(s24)*. % 76.16/76.33 132538[114:MRR:846.0,132536.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.33 132541[114:Res:53.1,132538.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.33 132543[115:Spt:132541.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 132545[115:Res:132543.0,61.1] always3(s24) || -> . % 76.16/76.33 132546[115:SSi:132545.0,78173.0,78177.0,108774.0,131995.0,132536.0] || -> . % 76.16/76.33 132547[115:Spt:132546.0,132541.0,132543.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.33 132548[115:Spt:132546.0,132541.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 132552[115:Res:132548.0,61.1] always3(s25) || -> . % 76.16/76.33 132553[115:SSi:132552.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.33 132554[113:Spt:132553.0,131994.0,131995.0] || until2p7(s24)*+ -> . % 76.16/76.33 132555[113:Spt:132553.0,131994.1] || -> node4(s23)*. % 76.16/76.33 132557[113:MRR:849.0,132555.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.33 132560[113:Res:53.1,132557.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.33 132562[114:Spt:132560.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 132564[114:Res:132562.0,61.1] always3(s23) || -> . % 76.16/76.33 132565[114:SSi:132564.0,78169.0,78172.0,108773.0,131993.0,132555.0] || -> . % 76.16/76.33 132566[114:Spt:132565.0,132560.0,132562.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.33 132567[114:Spt:132565.0,132560.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 132571[114:Res:132567.0,61.1] always3(s24) || -> . % 76.16/76.33 132572[114:SSi:132571.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.33 132573[112:Spt:132572.0,131992.0,131993.0] || until2p7(s23)*+ -> . % 76.16/76.33 132574[112:Spt:132572.0,131992.1] || -> node4(s22)*. % 76.16/76.33 132576[112:MRR:852.0,132574.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.33 132579[112:Res:53.1,132576.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.33 132581[113:Spt:132579.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 132583[113:Res:132581.0,61.1] always3(s22) || -> . % 76.16/76.33 132584[113:SSi:132583.0,78164.0,78168.0,108772.0,131991.0,132574.0] || -> . % 76.16/76.33 132585[113:Spt:132584.0,132579.0,132581.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.33 132586[113:Spt:132584.0,132579.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 132590[113:Res:132586.0,61.1] always3(s23) || -> . % 76.16/76.33 132591[113:SSi:132590.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.33 132592[111:Spt:132591.0,131990.0,131991.0] || until2p7(s22)*+ -> . % 76.16/76.33 132593[111:Spt:132591.0,131990.1] || -> node4(s21)*. % 76.16/76.33 132595[111:MRR:855.0,132593.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.33 132598[111:Res:53.1,132595.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.33 132603[112:Spt:132598.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 132605[112:Res:132603.0,61.1] always3(s21) || -> . % 76.16/76.33 132606[112:SSi:132605.0,78160.0,78163.0,108771.0,131989.0,132593.0] || -> . % 76.16/76.33 132607[112:Spt:132606.0,132598.0,132603.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.33 132608[112:Spt:132606.0,132598.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 132612[112:Res:132608.0,61.1] always3(s22) || -> . % 76.16/76.33 132613[112:SSi:132612.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.33 132614[110:Spt:132613.0,131988.0,131989.0] || until2p7(s21)*+ -> . % 76.16/76.33 132615[110:Spt:132613.0,131988.1] || -> node4(s20)*. % 76.16/76.33 132617[110:MRR:858.0,132615.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.33 132620[110:Res:53.1,132617.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.33 132622[111:Spt:132620.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 132624[111:Res:132622.0,61.1] always3(s20) || -> . % 76.16/76.33 132625[111:SSi:132624.0,78155.0,78159.0,108770.0,131987.0,132615.0] || -> . % 76.16/76.33 132626[111:Spt:132625.0,132620.0,132622.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.33 132627[111:Spt:132625.0,132620.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 132631[111:Res:132627.0,61.1] always3(s21) || -> . % 76.16/76.33 132632[111:SSi:132631.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.33 132633[109:Spt:132632.0,131986.0,131987.0] || until2p7(s20)*+ -> . % 76.16/76.33 132634[109:Spt:132632.0,131986.1] || -> node4(s19)*. % 76.16/76.33 132636[109:MRR:861.0,132634.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.33 132639[109:Res:53.1,132636.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.33 132641[110:Spt:132639.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 132643[110:Res:132641.0,61.1] always3(s19) || -> . % 76.16/76.33 132644[110:SSi:132643.0,78151.0,78154.0,108769.0,131985.0,132634.0] || -> . % 76.16/76.33 132645[110:Spt:132644.0,132639.0,132641.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.33 132646[110:Spt:132644.0,132639.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 132650[110:Res:132646.0,61.1] always3(s20) || -> . % 76.16/76.33 132651[110:SSi:132650.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.33 132652[108:Spt:132651.0,131984.0,131985.0] || until2p7(s19)*+ -> . % 76.16/76.33 132653[108:Spt:132651.0,131984.1] || -> node4(s18)*. % 76.16/76.33 132655[108:MRR:864.0,132653.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.33 132658[108:Res:53.1,132655.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.33 132660[109:Spt:132658.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 132662[109:Res:132660.0,61.1] always3(s18) || -> . % 76.16/76.33 132663[109:SSi:132662.0,78146.0,78150.0,108768.0,131983.0,132653.0] || -> . % 76.16/76.33 132664[109:Spt:132663.0,132658.0,132660.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.33 132665[109:Spt:132663.0,132658.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 132669[109:Res:132665.0,61.1] always3(s19) || -> . % 76.16/76.33 132670[109:SSi:132669.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.33 132671[107:Spt:132670.0,131982.0,131983.0] || until2p7(s18)*+ -> . % 76.16/76.33 132672[107:Spt:132670.0,131982.1] || -> node4(s17)*. % 76.16/76.33 132674[107:MRR:867.0,132672.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.33 132677[107:Res:53.1,132674.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.33 132682[108:Spt:132677.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 132684[108:Res:132682.0,61.1] always3(s17) || -> . % 76.16/76.33 132685[108:SSi:132684.0,78142.0,78145.0,108767.0,131981.0,132672.0] || -> . % 76.16/76.33 132686[108:Spt:132685.0,132677.0,132682.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.33 132687[108:Spt:132685.0,132677.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 132691[108:Res:132687.0,61.1] always3(s18) || -> . % 76.16/76.33 132692[108:SSi:132691.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.33 132693[106:Spt:132692.0,131980.0,131981.0] || until2p7(s17)*+ -> . % 76.16/76.33 132694[106:Spt:132692.0,131980.1] || -> node4(s16)*. % 76.16/76.33 132696[106:MRR:870.0,132694.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.33 132699[106:Res:53.1,132696.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.33 132701[107:Spt:132699.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 132703[107:Res:132701.0,61.1] always3(s16) || -> . % 76.16/76.33 132704[107:SSi:132703.0,78137.0,78141.0,108766.0,131979.0,132694.0] || -> . % 76.16/76.33 132705[107:Spt:132704.0,132699.0,132701.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.33 132706[107:Spt:132704.0,132699.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 132710[107:Res:132706.0,61.1] always3(s17) || -> . % 76.16/76.33 132711[107:SSi:132710.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.33 132712[105:Spt:132711.0,131978.0,131979.0] || until2p7(s16)*+ -> . % 76.16/76.33 132713[105:Spt:132711.0,131978.1] || -> node4(s15)*. % 76.16/76.33 132715[105:MRR:873.0,132713.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.33 132718[105:Res:53.1,132715.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.33 132720[106:Spt:132718.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 132722[106:Res:132720.0,61.1] always3(s15) || -> . % 76.16/76.33 132723[106:SSi:132722.0,78133.0,78136.0,108765.0,131977.0,132713.0] || -> . % 76.16/76.33 132724[106:Spt:132723.0,132718.0,132720.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.33 132725[106:Spt:132723.0,132718.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 132729[106:Res:132725.0,61.1] always3(s16) || -> . % 76.16/76.33 132730[106:SSi:132729.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.33 132731[104:Spt:132730.0,131976.0,131977.0] || until2p7(s15)*+ -> . % 76.16/76.33 132732[104:Spt:132730.0,131976.1] || -> node4(s14)*. % 76.16/76.33 132734[104:MRR:876.0,132732.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.33 132737[104:Res:53.1,132734.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.33 132739[105:Spt:132737.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 132741[105:Res:132739.0,61.1] always3(s14) || -> . % 76.16/76.33 132742[105:SSi:132741.0,78128.0,78132.0,108764.0,131975.0,132732.0] || -> . % 76.16/76.33 132743[105:Spt:132742.0,132737.0,132739.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.33 132744[105:Spt:132742.0,132737.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 132748[105:Res:132744.0,61.1] always3(s15) || -> . % 76.16/76.33 132749[105:SSi:132748.0,78133.0,78136.0,108765.0] || -> . % 76.16/76.33 132750[103:Spt:132749.0,131974.0,131975.0] || until2p7(s14)*+ -> . % 76.16/76.33 132751[103:Spt:132749.0,131974.1] || -> node4(s13)*. % 76.16/76.33 132753[103:MRR:879.0,132751.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.33 132756[103:Res:53.1,132753.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.33 132761[104:Spt:132756.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 132763[104:Res:132761.0,61.1] always3(s13) || -> . % 76.16/76.33 132764[104:SSi:132763.0,78124.0,78127.0,108763.0,131973.0,132751.0] || -> . % 76.16/76.33 132765[104:Spt:132764.0,132756.0,132761.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.33 132766[104:Spt:132764.0,132756.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 132770[104:Res:132766.0,61.1] always3(s14) || -> . % 76.16/76.33 132771[104:SSi:132770.0,78128.0,78132.0,108764.0] || -> . % 76.16/76.33 132772[102:Spt:132771.0,131972.0,131973.0] || until2p7(s13)*+ -> . % 76.16/76.33 132773[102:Spt:132771.0,131972.1] || -> node4(s12)*. % 76.16/76.33 132775[102:MRR:882.0,132773.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.33 132778[102:Res:53.1,132775.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.33 132780[103:Spt:132778.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 132782[103:Res:132780.0,61.1] always3(s12) || -> . % 76.16/76.33 132783[103:SSi:132782.0,78119.0,78123.0,108762.0,131971.0,132773.0] || -> . % 76.16/76.33 132784[103:Spt:132783.0,132778.0,132780.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.33 132785[103:Spt:132783.0,132778.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 132789[103:Res:132785.0,61.1] always3(s13) || -> . % 76.16/76.33 132790[103:SSi:132789.0,78124.0,78127.0,108763.0] || -> . % 76.16/76.33 132791[101:Spt:132790.0,131970.0,131971.0] || until2p7(s12)*+ -> . % 76.16/76.33 132792[101:Spt:132790.0,131970.1] || -> node4(s11)*. % 76.16/76.33 132794[101:MRR:885.0,132792.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.33 132797[101:Res:53.1,132794.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.33 132799[102:Spt:132797.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 132801[102:Res:132799.0,61.1] always3(s11) || -> . % 76.16/76.33 132802[102:SSi:132801.0,78115.0,78118.0,108761.0,131969.0,132792.0] || -> . % 76.16/76.33 132803[102:Spt:132802.0,132797.0,132799.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.33 132804[102:Spt:132802.0,132797.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 132808[102:Res:132804.0,61.1] always3(s12) || -> . % 76.16/76.33 132809[102:SSi:132808.0,78119.0,78123.0,108762.0] || -> . % 76.16/76.33 132810[100:Spt:132809.0,131968.0,131969.0] || until2p7(s11)*+ -> . % 76.16/76.33 132811[100:Spt:132809.0,131968.1] || -> node4(s10)*. % 76.16/76.33 132813[100:MRR:888.0,132811.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.33 132816[100:Res:53.1,132813.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.33 132818[101:Spt:132816.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 132820[101:Res:132818.0,61.1] always3(s10) || -> . % 76.16/76.33 132821[101:SSi:132820.0,78110.0,78114.0,108760.0,131967.0,132811.0] || -> . % 76.16/76.33 132822[101:Spt:132821.0,132816.0,132818.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.33 132823[101:Spt:132821.0,132816.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 132827[101:Res:132823.0,61.1] always3(s11) || -> . % 76.16/76.33 132828[101:SSi:132827.0,78115.0,78118.0,108761.0] || -> . % 76.16/76.33 132829[99:Spt:132828.0,131966.0,131967.0] || until2p7(s10)*+ -> . % 76.16/76.33 132830[99:Spt:132828.0,131966.1] || -> node4(s9)*. % 76.16/76.33 132832[99:MRR:891.0,132830.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.33 132835[99:Res:53.1,132832.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.33 132840[100:Spt:132835.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 132842[100:Res:132840.0,61.1] always3(s9) || -> . % 76.16/76.33 132843[100:SSi:132842.0,78106.0,78109.0,108759.0,131965.0,132830.0] || -> . % 76.16/76.33 132844[100:Spt:132843.0,132835.0,132840.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.33 132845[100:Spt:132843.0,132835.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 132849[100:Res:132845.0,61.1] always3(s10) || -> . % 76.16/76.33 132850[100:SSi:132849.0,78110.0,78114.0,108760.0] || -> . % 76.16/76.33 132851[98:Spt:132850.0,131964.0,131965.0] || until2p7(s9)*+ -> . % 76.16/76.33 132852[98:Spt:132850.0,131964.1] || -> node4(s8)*. % 76.16/76.33 132854[98:MRR:894.0,132852.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.33 132857[98:Res:53.1,132854.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.33 132859[99:Spt:132857.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.33 132861[99:Res:132859.0,61.1] always3(s8) || -> . % 76.16/76.33 132862[99:SSi:132861.0,78101.0,78105.0,108758.0,131963.0,132852.0] || -> . % 76.16/76.33 132863[99:Spt:132862.0,132857.0,132859.0] || m_main_v_state(s8,c_busy)* -> . % 76.16/76.33 132864[99:Spt:132862.0,132857.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 132868[99:Res:132864.0,61.1] always3(s9) || -> . % 76.16/76.33 132869[99:SSi:132868.0,78106.0,78109.0,108759.0] || -> . % 76.16/76.33 132870[97:Spt:132869.0,131962.0,131963.0] || until2p7(s8)*+ -> . % 76.16/76.33 132871[97:Spt:132869.0,131962.1] || -> node4(s7)*. % 76.16/76.33 132873[97:MRR:897.0,132871.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.16/76.33 132876[97:Res:53.1,132873.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.16/76.33 132878[97:MRR:132876.0,131952.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.33 132880[97:Res:132878.0,61.1] always3(s8) || -> . % 76.16/76.33 132881[97:SSi:132880.0,78101.0,78105.0,108758.0] || -> . % 76.16/76.33 132882[95:Spt:132881.0,131795.0,131798.0] || trans(s49,s7)*+ -> . % 76.16/76.33 132883[95:Spt:132881.0,131795.1,131795.2,131795.3,131795.4] || -> trans(s49,s6) trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.33 132885[95:MRR:131797.1,132882.0] xuntil6(s49) || -> trans(s49,s6) trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.33 132886[96:Spt:132883.0] || -> trans(s49,s6)*. % 76.16/76.33 132887[96:Res:132886.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s6)*. % 76.16/76.33 132889[96:Res:132886.0,60.0] || -> node2(s49,s6)*. % 76.16/76.33 132890[96:SSi:132887.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s6)*. % 76.16/76.33 132891[96:Res:132889.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)*. % 76.16/76.33 133033[96:SoR:132891.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)*. % 76.16/76.33 133035[96:SoR:133033.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)* xuntil6(s49). % 76.16/76.33 133036[96:SSi:133035.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s6,c_busy)* xuntil6(s49). % 76.16/76.33 133037[97:Spt:133036.1] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.33 133039[97:Res:133037.0,61.1] always3(s6) || -> . % 76.16/76.33 133040[97:SSi:133039.0,78093.0,78096.0,108756.0] || -> . % 76.16/76.33 133041[97:Spt:133040.0,133036.1,133037.0] || m_main_v_state(s6,c_busy)*+ -> . % 76.16/76.33 133042[97:Spt:133040.0,133036.0,133036.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 133046[97:MRR:133033.2,133041.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 133047[97:Res:53.1,133042.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 133049[97:MRR:133047.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 133050[97:MRR:132890.0,133049.0] || -> until2p7(s6)*. % 76.16/76.33 133051[97:MRR:202.0,133050.0] || -> until2p7(s7)* node4(s6). % 76.16/76.33 133052[98:Spt:133051.0] || -> until2p7(s7)*. % 76.16/76.33 133053[98:MRR:203.0,133052.0] || -> until2p7(s8)* node4(s7). % 76.16/76.33 133054[99:Spt:133053.0] || -> until2p7(s8)*. % 76.16/76.33 133055[99:MRR:204.0,133054.0] || -> until2p7(s9)* node4(s8). % 76.16/76.33 133056[100:Spt:133055.0] || -> until2p7(s9)*. % 76.16/76.33 133057[100:MRR:205.0,133056.0] || -> until2p7(s10)* node4(s9). % 76.16/76.33 133058[101:Spt:133057.0] || -> until2p7(s10)*. % 76.16/76.33 133059[101:MRR:206.0,133058.0] || -> until2p7(s11)* node4(s10). % 76.16/76.33 133060[102:Spt:133059.0] || -> until2p7(s11)*. % 76.16/76.33 133061[102:MRR:207.0,133060.0] || -> until2p7(s12)* node4(s11). % 76.16/76.33 133062[103:Spt:133061.0] || -> until2p7(s12)*. % 76.16/76.33 133063[103:MRR:208.0,133062.0] || -> until2p7(s13)* node4(s12). % 76.16/76.33 133064[104:Spt:133063.0] || -> until2p7(s13)*. % 76.16/76.33 133065[104:MRR:209.0,133064.0] || -> until2p7(s14)* node4(s13). % 76.16/76.33 133066[105:Spt:133065.0] || -> until2p7(s14)*. % 76.16/76.33 133067[105:MRR:210.0,133066.0] || -> until2p7(s15)* node4(s14). % 76.16/76.33 133068[106:Spt:133067.0] || -> until2p7(s15)*. % 76.16/76.33 133069[106:MRR:211.0,133068.0] || -> until2p7(s16)* node4(s15). % 76.16/76.33 133070[107:Spt:133069.0] || -> until2p7(s16)*. % 76.16/76.33 133071[107:MRR:212.0,133070.0] || -> until2p7(s17)* node4(s16). % 76.16/76.33 133072[108:Spt:133071.0] || -> until2p7(s17)*. % 76.16/76.33 133073[108:MRR:213.0,133072.0] || -> until2p7(s18)* node4(s17). % 76.16/76.33 133074[109:Spt:133073.0] || -> until2p7(s18)*. % 76.16/76.33 133075[109:MRR:214.0,133074.0] || -> until2p7(s19)* node4(s18). % 76.16/76.33 133076[110:Spt:133075.0] || -> until2p7(s19)*. % 76.16/76.33 133077[110:MRR:215.0,133076.0] || -> until2p7(s20)* node4(s19). % 76.16/76.33 133078[111:Spt:133077.0] || -> until2p7(s20)*. % 76.16/76.33 133079[111:MRR:216.0,133078.0] || -> until2p7(s21)* node4(s20). % 76.16/76.33 133080[112:Spt:133079.0] || -> until2p7(s21)*. % 76.16/76.33 133081[112:MRR:217.0,133080.0] || -> until2p7(s22)* node4(s21). % 76.16/76.33 133082[113:Spt:133081.0] || -> until2p7(s22)*. % 76.16/76.33 133083[113:MRR:218.0,133082.0] || -> until2p7(s23)* node4(s22). % 76.16/76.33 133084[114:Spt:133083.0] || -> until2p7(s23)*. % 76.16/76.33 133085[114:MRR:219.0,133084.0] || -> until2p7(s24)* node4(s23). % 76.16/76.33 133086[115:Spt:133085.0] || -> until2p7(s24)*. % 76.16/76.33 133087[115:MRR:220.0,133086.0] || -> until2p7(s25)* node4(s24). % 76.16/76.33 133088[116:Spt:133087.0] || -> until2p7(s25)*. % 76.16/76.33 133089[116:MRR:221.0,133088.0] || -> until2p7(s26)* node4(s25). % 76.16/76.33 133090[117:Spt:133089.0] || -> until2p7(s26)*. % 76.16/76.33 133091[117:MRR:222.0,133090.0] || -> until2p7(s27)* node4(s26). % 76.16/76.33 133092[118:Spt:133091.0] || -> until2p7(s27)*. % 76.16/76.33 133093[118:MRR:223.0,133092.0] || -> until2p7(s28)* node4(s27). % 76.16/76.33 133094[119:Spt:133093.0] || -> until2p7(s28)*. % 76.16/76.33 133095[119:MRR:224.0,133094.0] || -> until2p7(s29)* node4(s28). % 76.16/76.33 133096[120:Spt:133095.0] || -> until2p7(s29)*. % 76.16/76.33 133097[120:MRR:225.0,133096.0] || -> until2p7(s30)* node4(s29). % 76.16/76.33 133098[121:Spt:133097.0] || -> until2p7(s30)*. % 76.16/76.33 133099[121:MRR:226.0,133098.0] || -> until2p7(s31)* node4(s30). % 76.16/76.33 133100[122:Spt:133099.0] || -> until2p7(s31)*. % 76.16/76.33 133101[122:MRR:227.0,133100.0] || -> until2p7(s32)* node4(s31). % 76.16/76.33 133102[123:Spt:133101.0] || -> until2p7(s32)*. % 76.16/76.33 133103[123:MRR:228.0,133102.0] || -> until2p7(s33)* node4(s32). % 76.16/76.33 133104[124:Spt:133103.0] || -> until2p7(s33)*. % 76.16/76.33 133105[124:MRR:229.0,133104.0] || -> until2p7(s34)* node4(s33). % 76.16/76.33 133106[125:Spt:133105.0] || -> until2p7(s34)*. % 76.16/76.33 133107[125:MRR:230.0,133106.0] || -> until2p7(s35)* node4(s34). % 76.16/76.33 133108[126:Spt:133107.0] || -> until2p7(s35)*. % 76.16/76.33 133109[126:MRR:231.0,133108.0] || -> until2p7(s36)* node4(s35). % 76.16/76.33 133110[127:Spt:133109.0] || -> until2p7(s36)*. % 76.16/76.33 133111[127:MRR:232.0,133110.0] || -> until2p7(s37)* node4(s36). % 76.16/76.33 133112[128:Spt:133111.0] || -> until2p7(s37)*. % 76.16/76.33 133113[128:MRR:235.0,133112.0] || -> until2p7(s38)* node4(s37). % 76.16/76.33 133114[129:Spt:133113.0] || -> until2p7(s38)*. % 76.16/76.33 133115[129:MRR:236.0,133114.0] || -> until2p7(s39)* node4(s38). % 76.16/76.33 133116[130:Spt:133115.0] || -> until2p7(s39)*. % 76.16/76.33 133117[130:MRR:237.0,133116.0] || -> until2p7(s40)* node4(s39). % 76.16/76.33 133118[131:Spt:133117.0] || -> until2p7(s40)*. % 76.16/76.33 133119[131:MRR:238.0,133118.0] || -> until2p7(s41)* node4(s40). % 76.16/76.33 133120[132:Spt:133119.0] || -> until2p7(s41)*. % 76.16/76.33 133121[132:MRR:239.0,133120.0] || -> until2p7(s42)* node4(s41). % 76.16/76.33 133122[133:Spt:133121.0] || -> until2p7(s42)*. % 76.16/76.33 133123[133:MRR:240.0,133122.0] || -> until2p7(s43)* node4(s42). % 76.16/76.33 133124[134:Spt:133123.0] || -> until2p7(s43)*. % 76.16/76.33 133125[134:MRR:241.0,133124.0] || -> until2p7(s44)* node4(s43). % 76.16/76.33 133126[135:Spt:133125.0] || -> until2p7(s44)*. % 76.16/76.33 133127[135:MRR:539.0,133126.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 133128[136:Spt:133127.0] || -> until2p7(s45)*. % 76.16/76.33 133129[136:MRR:544.0,133128.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 133130[137:Spt:133129.0] || -> until2p7(s46)*. % 76.16/76.33 133131[137:MRR:549.0,133130.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 133132[138:Spt:133131.0] || -> until2p7(s47)*. % 76.16/76.33 133133[138:MRR:554.0,133132.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 133134[139:Spt:133133.0] || -> until2p7(s48)*. % 76.16/76.33 133135[139:MRR:559.0,133134.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 133136[140:Spt:133135.0] || -> until2p7(s49)*. % 76.16/76.33 133137[140:MRR:194.0,133136.0] || -> node4(s49)*. % 76.16/76.33 133138[140:MRR:133046.0,133137.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 133142[140:Res:53.1,133138.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 133144[140:MRR:133142.0,78381.0] || -> . % 76.16/76.33 133145[140:Spt:133144.0,133135.0,133136.0] || until2p7(s49)*+ -> . % 76.16/76.33 133146[140:Spt:133144.0,133135.1] || -> node4(s48)*. % 76.16/76.33 133147[140:MRR:78384.0,133146.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 133150[140:Res:53.1,133147.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 133153[140:Res:133150.0,61.1] always3(s48) || -> . % 76.16/76.33 133154[140:SSi:133153.0,78281.0,78387.0,108798.0,133134.0,133146.0] || -> . % 76.16/76.33 133155[139:Spt:133154.0,133133.0,133134.0] || until2p7(s48)*+ -> . % 76.16/76.33 133156[139:Spt:133154.0,133133.1] || -> node4(s47)*. % 76.16/76.33 133158[139:MRR:777.0,133156.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 133170[139:Res:53.1,133158.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 133172[140:Spt:133170.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 133174[140:Res:133172.0,61.1] always3(s47) || -> . % 76.16/76.33 133175[140:SSi:133174.0,78277.0,78280.0,108797.0,133132.0,133156.0] || -> . % 76.16/76.33 133176[140:Spt:133175.0,133170.0,133172.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 133177[140:Spt:133175.0,133170.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 133181[140:Res:133177.0,61.1] always3(s48) || -> . % 76.16/76.33 133182[140:SSi:133181.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.33 133183[138:Spt:133182.0,133131.0,133132.0] || until2p7(s47)*+ -> . % 76.16/76.33 133184[138:Spt:133182.0,133131.1] || -> node4(s46)*. % 76.16/76.33 133186[138:MRR:780.0,133184.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 133193[138:Res:53.1,133186.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 133198[139:Spt:133193.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 133200[139:Res:133198.0,61.1] always3(s46) || -> . % 76.16/76.33 133201[139:SSi:133200.0,78272.0,78276.0,108796.0,133130.0,133184.0] || -> . % 76.16/76.33 133202[139:Spt:133201.0,133193.0,133198.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 133203[139:Spt:133201.0,133193.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 133207[139:Res:133203.0,61.1] always3(s47) || -> . % 76.16/76.33 133208[139:SSi:133207.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.33 133209[137:Spt:133208.0,133129.0,133130.0] || until2p7(s46)*+ -> . % 76.16/76.33 133210[137:Spt:133208.0,133129.1] || -> node4(s45)*. % 76.16/76.33 133212[137:MRR:783.0,133210.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 133215[137:Res:53.1,133212.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 133217[138:Spt:133215.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 133219[138:Res:133217.0,61.1] always3(s45) || -> . % 76.16/76.33 133220[138:SSi:133219.0,78268.0,78271.0,108795.0,133128.0,133210.0] || -> . % 76.16/76.33 133221[138:Spt:133220.0,133215.0,133217.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.33 133222[138:Spt:133220.0,133215.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 133226[138:Res:133222.0,61.1] always3(s46) || -> . % 76.16/76.33 133227[138:SSi:133226.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.33 133228[136:Spt:133227.0,133127.0,133128.0] || until2p7(s45)*+ -> . % 76.16/76.33 133229[136:Spt:133227.0,133127.1] || -> node4(s44)*. % 76.16/76.33 133231[136:MRR:786.0,133229.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.33 133234[136:Res:53.1,133231.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.33 133236[137:Spt:133234.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 133238[137:Res:133236.0,61.1] always3(s44) || -> . % 76.16/76.33 133239[137:SSi:133238.0,78263.0,78267.0,108794.0,133126.0,133229.0] || -> . % 76.16/76.33 133240[137:Spt:133239.0,133234.0,133236.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.33 133241[137:Spt:133239.0,133234.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 133245[137:Res:133241.0,61.1] always3(s45) || -> . % 76.16/76.33 133246[137:SSi:133245.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.33 133247[135:Spt:133246.0,133125.0,133126.0] || until2p7(s44)*+ -> . % 76.16/76.33 133248[135:Spt:133246.0,133125.1] || -> node4(s43)*. % 76.16/76.33 133250[135:MRR:789.0,133248.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.33 133253[135:Res:53.1,133250.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.33 133255[136:Spt:133253.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 133257[136:Res:133255.0,61.1] always3(s43) || -> . % 76.16/76.33 133258[136:SSi:133257.0,78259.0,78262.0,108793.0,133124.0,133248.0] || -> . % 76.16/76.33 133259[136:Spt:133258.0,133253.0,133255.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.33 133260[136:Spt:133258.0,133253.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 133264[136:Res:133260.0,61.1] always3(s44) || -> . % 76.16/76.33 133265[136:SSi:133264.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.33 133266[134:Spt:133265.0,133123.0,133124.0] || until2p7(s43)*+ -> . % 76.16/76.33 133267[134:Spt:133265.0,133123.1] || -> node4(s42)*. % 76.16/76.33 133269[134:MRR:792.0,133267.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.33 133272[134:Res:53.1,133269.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.33 133277[135:Spt:133272.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 133279[135:Res:133277.0,61.1] always3(s42) || -> . % 76.16/76.33 133280[135:SSi:133279.0,78254.0,78258.0,108792.0,133122.0,133267.0] || -> . % 76.16/76.33 133281[135:Spt:133280.0,133272.0,133277.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.33 133282[135:Spt:133280.0,133272.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 133286[135:Res:133282.0,61.1] always3(s43) || -> . % 76.16/76.33 133287[135:SSi:133286.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.33 133288[133:Spt:133287.0,133121.0,133122.0] || until2p7(s42)*+ -> . % 76.16/76.33 133289[133:Spt:133287.0,133121.1] || -> node4(s41)*. % 76.16/76.33 133291[133:MRR:795.0,133289.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.33 133294[133:Res:53.1,133291.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.33 133296[134:Spt:133294.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 133298[134:Res:133296.0,61.1] always3(s41) || -> . % 76.16/76.33 133299[134:SSi:133298.0,78250.0,78253.0,108791.0,133120.0,133289.0] || -> . % 76.16/76.33 133300[134:Spt:133299.0,133294.0,133296.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.33 133301[134:Spt:133299.0,133294.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 133305[134:Res:133301.0,61.1] always3(s42) || -> . % 76.16/76.33 133306[134:SSi:133305.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.33 133307[132:Spt:133306.0,133119.0,133120.0] || until2p7(s41)*+ -> . % 76.16/76.33 133308[132:Spt:133306.0,133119.1] || -> node4(s40)*. % 76.16/76.33 133310[132:MRR:798.0,133308.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.33 133313[132:Res:53.1,133310.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.33 133315[133:Spt:133313.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 133317[133:Res:133315.0,61.1] always3(s40) || -> . % 76.16/76.33 133318[133:SSi:133317.0,78245.0,78249.0,108790.0,133118.0,133308.0] || -> . % 76.16/76.33 133319[133:Spt:133318.0,133313.0,133315.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.33 133320[133:Spt:133318.0,133313.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 133324[133:Res:133320.0,61.1] always3(s41) || -> . % 76.16/76.33 133325[133:SSi:133324.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.33 133326[131:Spt:133325.0,133117.0,133118.0] || until2p7(s40)*+ -> . % 76.16/76.33 133327[131:Spt:133325.0,133117.1] || -> node4(s39)*. % 76.16/76.33 133329[131:MRR:801.0,133327.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.33 133332[131:Res:53.1,133329.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.33 133334[132:Spt:133332.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 133336[132:Res:133334.0,61.1] always3(s39) || -> . % 76.16/76.33 133337[132:SSi:133336.0,78241.0,78244.0,108789.0,133116.0,133327.0] || -> . % 76.16/76.33 133338[132:Spt:133337.0,133332.0,133334.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.33 133339[132:Spt:133337.0,133332.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 133343[132:Res:133339.0,61.1] always3(s40) || -> . % 76.16/76.33 133344[132:SSi:133343.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.33 133345[130:Spt:133344.0,133115.0,133116.0] || until2p7(s39)*+ -> . % 76.16/76.33 133346[130:Spt:133344.0,133115.1] || -> node4(s38)*. % 76.16/76.33 133348[130:MRR:804.0,133346.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.33 133351[130:Res:53.1,133348.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.33 133356[131:Spt:133351.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 133358[131:Res:133356.0,61.1] always3(s38) || -> . % 76.16/76.33 133359[131:SSi:133358.0,78236.0,78240.0,108788.0,133114.0,133346.0] || -> . % 76.16/76.33 133360[131:Spt:133359.0,133351.0,133356.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.33 133361[131:Spt:133359.0,133351.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 133365[131:Res:133361.0,61.1] always3(s39) || -> . % 76.16/76.33 133366[131:SSi:133365.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.33 133367[129:Spt:133366.0,133113.0,133114.0] || until2p7(s38)*+ -> . % 76.16/76.33 133368[129:Spt:133366.0,133113.1] || -> node4(s37)*. % 76.16/76.33 133370[129:MRR:807.0,133368.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.33 133373[129:Res:53.1,133370.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.33 133375[130:Spt:133373.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 133377[130:Res:133375.0,61.1] always3(s37) || -> . % 76.16/76.33 133378[130:SSi:133377.0,78232.0,78235.0,108787.0,133112.0,133368.0] || -> . % 76.16/76.33 133379[130:Spt:133378.0,133373.0,133375.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.33 133380[130:Spt:133378.0,133373.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 133384[130:Res:133380.0,61.1] always3(s38) || -> . % 76.16/76.33 133385[130:SSi:133384.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.33 133386[128:Spt:133385.0,133111.0,133112.0] || until2p7(s37)*+ -> . % 76.16/76.33 133387[128:Spt:133385.0,133111.1] || -> node4(s36)*. % 76.16/76.33 133389[128:MRR:810.0,133387.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.33 133392[128:Res:53.1,133389.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.33 133394[129:Spt:133392.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 133396[129:Res:133394.0,61.1] always3(s36) || -> . % 76.16/76.33 133397[129:SSi:133396.0,78227.0,78231.0,108786.0,133110.0,133387.0] || -> . % 76.16/76.33 133398[129:Spt:133397.0,133392.0,133394.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.33 133399[129:Spt:133397.0,133392.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 133403[129:Res:133399.0,61.1] always3(s37) || -> . % 76.16/76.33 133404[129:SSi:133403.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.33 133405[127:Spt:133404.0,133109.0,133110.0] || until2p7(s36)*+ -> . % 76.16/76.33 133406[127:Spt:133404.0,133109.1] || -> node4(s35)*. % 76.16/76.33 133408[127:MRR:813.0,133406.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.33 133411[127:Res:53.1,133408.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.33 133413[128:Spt:133411.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 133415[128:Res:133413.0,61.1] always3(s35) || -> . % 76.16/76.33 133416[128:SSi:133415.0,78223.0,78226.0,108785.0,133108.0,133406.0] || -> . % 76.16/76.33 133417[128:Spt:133416.0,133411.0,133413.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.33 133418[128:Spt:133416.0,133411.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 133422[128:Res:133418.0,61.1] always3(s36) || -> . % 76.16/76.33 133423[128:SSi:133422.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.33 133424[126:Spt:133423.0,133107.0,133108.0] || until2p7(s35)*+ -> . % 76.16/76.33 133425[126:Spt:133423.0,133107.1] || -> node4(s34)*. % 76.16/76.33 133427[126:MRR:816.0,133425.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.33 133430[126:Res:53.1,133427.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.33 133435[127:Spt:133430.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 133437[127:Res:133435.0,61.1] always3(s34) || -> . % 76.16/76.33 133438[127:SSi:133437.0,78218.0,78222.0,108784.0,133106.0,133425.0] || -> . % 76.16/76.33 133439[127:Spt:133438.0,133430.0,133435.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.33 133440[127:Spt:133438.0,133430.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 133444[127:Res:133440.0,61.1] always3(s35) || -> . % 76.16/76.33 133445[127:SSi:133444.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.33 133446[125:Spt:133445.0,133105.0,133106.0] || until2p7(s34)*+ -> . % 76.16/76.33 133447[125:Spt:133445.0,133105.1] || -> node4(s33)*. % 76.16/76.33 133449[125:MRR:819.0,133447.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.33 133452[125:Res:53.1,133449.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.33 133454[126:Spt:133452.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 133456[126:Res:133454.0,61.1] always3(s33) || -> . % 76.16/76.33 133457[126:SSi:133456.0,78214.0,78217.0,108783.0,133104.0,133447.0] || -> . % 76.16/76.33 133458[126:Spt:133457.0,133452.0,133454.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.33 133459[126:Spt:133457.0,133452.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 133463[126:Res:133459.0,61.1] always3(s34) || -> . % 76.16/76.33 133464[126:SSi:133463.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.33 133465[124:Spt:133464.0,133103.0,133104.0] || until2p7(s33)*+ -> . % 76.16/76.33 133466[124:Spt:133464.0,133103.1] || -> node4(s32)*. % 76.16/76.33 133468[124:MRR:822.0,133466.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.33 133471[124:Res:53.1,133468.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.33 133473[125:Spt:133471.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 133475[125:Res:133473.0,61.1] always3(s32) || -> . % 76.16/76.33 133476[125:SSi:133475.0,78209.0,78213.0,108782.0,133102.0,133466.0] || -> . % 76.16/76.33 133477[125:Spt:133476.0,133471.0,133473.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.33 133478[125:Spt:133476.0,133471.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 133482[125:Res:133478.0,61.1] always3(s33) || -> . % 76.16/76.33 133483[125:SSi:133482.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.33 133484[123:Spt:133483.0,133101.0,133102.0] || until2p7(s32)*+ -> . % 76.16/76.33 133485[123:Spt:133483.0,133101.1] || -> node4(s31)*. % 76.16/76.33 133487[123:MRR:825.0,133485.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.33 133490[123:Res:53.1,133487.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.33 133492[124:Spt:133490.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 133494[124:Res:133492.0,61.1] always3(s31) || -> . % 76.16/76.33 133495[124:SSi:133494.0,78205.0,78208.0,108781.0,133100.0,133485.0] || -> . % 76.16/76.33 133496[124:Spt:133495.0,133490.0,133492.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.33 133497[124:Spt:133495.0,133490.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 133501[124:Res:133497.0,61.1] always3(s32) || -> . % 76.16/76.33 133502[124:SSi:133501.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.33 133503[122:Spt:133502.0,133099.0,133100.0] || until2p7(s31)*+ -> . % 76.16/76.33 133504[122:Spt:133502.0,133099.1] || -> node4(s30)*. % 76.16/76.33 133506[122:MRR:828.0,133504.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.33 133509[122:Res:53.1,133506.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.33 133514[123:Spt:133509.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 133516[123:Res:133514.0,61.1] always3(s30) || -> . % 76.16/76.33 133517[123:SSi:133516.0,78200.0,78204.0,108780.0,133098.0,133504.0] || -> . % 76.16/76.33 133518[123:Spt:133517.0,133509.0,133514.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.33 133519[123:Spt:133517.0,133509.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 133523[123:Res:133519.0,61.1] always3(s31) || -> . % 76.16/76.33 133524[123:SSi:133523.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.33 133525[121:Spt:133524.0,133097.0,133098.0] || until2p7(s30)*+ -> . % 76.16/76.33 133526[121:Spt:133524.0,133097.1] || -> node4(s29)*. % 76.16/76.33 133528[121:MRR:831.0,133526.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.33 133531[121:Res:53.1,133528.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.33 133533[122:Spt:133531.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 133535[122:Res:133533.0,61.1] always3(s29) || -> . % 76.16/76.33 133536[122:SSi:133535.0,78196.0,78199.0,108779.0,133096.0,133526.0] || -> . % 76.16/76.33 133537[122:Spt:133536.0,133531.0,133533.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.33 133538[122:Spt:133536.0,133531.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 133542[122:Res:133538.0,61.1] always3(s30) || -> . % 76.16/76.33 133543[122:SSi:133542.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.33 133544[120:Spt:133543.0,133095.0,133096.0] || until2p7(s29)*+ -> . % 76.16/76.33 133545[120:Spt:133543.0,133095.1] || -> node4(s28)*. % 76.16/76.33 133547[120:MRR:834.0,133545.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.33 133550[120:Res:53.1,133547.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.33 133552[121:Spt:133550.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 133554[121:Res:133552.0,61.1] always3(s28) || -> . % 76.16/76.33 133555[121:SSi:133554.0,78191.0,78195.0,108778.0,133094.0,133545.0] || -> . % 76.16/76.33 133556[121:Spt:133555.0,133550.0,133552.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.33 133557[121:Spt:133555.0,133550.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 133561[121:Res:133557.0,61.1] always3(s29) || -> . % 76.16/76.33 133562[121:SSi:133561.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.33 133563[119:Spt:133562.0,133093.0,133094.0] || until2p7(s28)*+ -> . % 76.16/76.33 133564[119:Spt:133562.0,133093.1] || -> node4(s27)*. % 76.16/76.33 133566[119:MRR:837.0,133564.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.33 133569[119:Res:53.1,133566.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.33 133571[120:Spt:133569.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 133573[120:Res:133571.0,61.1] always3(s27) || -> . % 76.16/76.33 133574[120:SSi:133573.0,78187.0,78190.0,108777.0,133092.0,133564.0] || -> . % 76.16/76.33 133575[120:Spt:133574.0,133569.0,133571.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.33 133576[120:Spt:133574.0,133569.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 133580[120:Res:133576.0,61.1] always3(s28) || -> . % 76.16/76.33 133581[120:SSi:133580.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.33 133582[118:Spt:133581.0,133091.0,133092.0] || until2p7(s27)*+ -> . % 76.16/76.33 133583[118:Spt:133581.0,133091.1] || -> node4(s26)*. % 76.16/76.33 133585[118:MRR:840.0,133583.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.33 133588[118:Res:53.1,133585.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.33 133593[119:Spt:133588.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 133595[119:Res:133593.0,61.1] always3(s26) || -> . % 76.16/76.33 133596[119:SSi:133595.0,78182.0,78186.0,108776.0,133090.0,133583.0] || -> . % 76.16/76.33 133597[119:Spt:133596.0,133588.0,133593.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.33 133598[119:Spt:133596.0,133588.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 133602[119:Res:133598.0,61.1] always3(s27) || -> . % 76.16/76.33 133603[119:SSi:133602.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.33 133604[117:Spt:133603.0,133089.0,133090.0] || until2p7(s26)*+ -> . % 76.16/76.33 133605[117:Spt:133603.0,133089.1] || -> node4(s25)*. % 76.16/76.33 133607[117:MRR:843.0,133605.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.33 133610[117:Res:53.1,133607.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.33 133612[118:Spt:133610.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 133614[118:Res:133612.0,61.1] always3(s25) || -> . % 76.16/76.33 133615[118:SSi:133614.0,78178.0,78181.0,108775.0,133088.0,133605.0] || -> . % 76.16/76.33 133616[118:Spt:133615.0,133610.0,133612.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.33 133617[118:Spt:133615.0,133610.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 133621[118:Res:133617.0,61.1] always3(s26) || -> . % 76.16/76.33 133622[118:SSi:133621.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.33 133623[116:Spt:133622.0,133087.0,133088.0] || until2p7(s25)*+ -> . % 76.16/76.33 133624[116:Spt:133622.0,133087.1] || -> node4(s24)*. % 76.16/76.33 133626[116:MRR:846.0,133624.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.33 133629[116:Res:53.1,133626.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.33 133631[117:Spt:133629.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 133633[117:Res:133631.0,61.1] always3(s24) || -> . % 76.16/76.33 133634[117:SSi:133633.0,78173.0,78177.0,108774.0,133086.0,133624.0] || -> . % 76.16/76.33 133635[117:Spt:133634.0,133629.0,133631.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.33 133636[117:Spt:133634.0,133629.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 133640[117:Res:133636.0,61.1] always3(s25) || -> . % 76.16/76.33 133641[117:SSi:133640.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.33 133642[115:Spt:133641.0,133085.0,133086.0] || until2p7(s24)*+ -> . % 76.16/76.33 133643[115:Spt:133641.0,133085.1] || -> node4(s23)*. % 76.16/76.33 133645[115:MRR:849.0,133643.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.33 133648[115:Res:53.1,133645.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.33 133650[116:Spt:133648.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 133652[116:Res:133650.0,61.1] always3(s23) || -> . % 76.16/76.33 133653[116:SSi:133652.0,78169.0,78172.0,108773.0,133084.0,133643.0] || -> . % 76.16/76.33 133654[116:Spt:133653.0,133648.0,133650.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.33 133655[116:Spt:133653.0,133648.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 133659[116:Res:133655.0,61.1] always3(s24) || -> . % 76.16/76.33 133660[116:SSi:133659.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.33 133661[114:Spt:133660.0,133083.0,133084.0] || until2p7(s23)*+ -> . % 76.16/76.33 133662[114:Spt:133660.0,133083.1] || -> node4(s22)*. % 76.16/76.33 133664[114:MRR:852.0,133662.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.33 133667[114:Res:53.1,133664.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.33 133672[115:Spt:133667.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 133674[115:Res:133672.0,61.1] always3(s22) || -> . % 76.16/76.33 133675[115:SSi:133674.0,78164.0,78168.0,108772.0,133082.0,133662.0] || -> . % 76.16/76.33 133676[115:Spt:133675.0,133667.0,133672.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.33 133677[115:Spt:133675.0,133667.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 133681[115:Res:133677.0,61.1] always3(s23) || -> . % 76.16/76.33 133682[115:SSi:133681.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.33 133683[113:Spt:133682.0,133081.0,133082.0] || until2p7(s22)*+ -> . % 76.16/76.33 133684[113:Spt:133682.0,133081.1] || -> node4(s21)*. % 76.16/76.33 133686[113:MRR:855.0,133684.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.33 133689[113:Res:53.1,133686.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.33 133691[114:Spt:133689.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 133693[114:Res:133691.0,61.1] always3(s21) || -> . % 76.16/76.33 133694[114:SSi:133693.0,78160.0,78163.0,108771.0,133080.0,133684.0] || -> . % 76.16/76.33 133695[114:Spt:133694.0,133689.0,133691.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.33 133696[114:Spt:133694.0,133689.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 133700[114:Res:133696.0,61.1] always3(s22) || -> . % 76.16/76.33 133701[114:SSi:133700.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.33 133702[112:Spt:133701.0,133079.0,133080.0] || until2p7(s21)*+ -> . % 76.16/76.33 133703[112:Spt:133701.0,133079.1] || -> node4(s20)*. % 76.16/76.33 133705[112:MRR:858.0,133703.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.33 133708[112:Res:53.1,133705.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.33 133710[113:Spt:133708.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 133712[113:Res:133710.0,61.1] always3(s20) || -> . % 76.16/76.33 133713[113:SSi:133712.0,78155.0,78159.0,108770.0,133078.0,133703.0] || -> . % 76.16/76.33 133714[113:Spt:133713.0,133708.0,133710.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.33 133715[113:Spt:133713.0,133708.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 133719[113:Res:133715.0,61.1] always3(s21) || -> . % 76.16/76.33 133720[113:SSi:133719.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.33 133721[111:Spt:133720.0,133077.0,133078.0] || until2p7(s20)*+ -> . % 76.16/76.33 133722[111:Spt:133720.0,133077.1] || -> node4(s19)*. % 76.16/76.33 133724[111:MRR:861.0,133722.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.33 133727[111:Res:53.1,133724.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.33 133729[112:Spt:133727.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 133731[112:Res:133729.0,61.1] always3(s19) || -> . % 76.16/76.33 133732[112:SSi:133731.0,78151.0,78154.0,108769.0,133076.0,133722.0] || -> . % 76.16/76.33 133733[112:Spt:133732.0,133727.0,133729.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.33 133734[112:Spt:133732.0,133727.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 133738[112:Res:133734.0,61.1] always3(s20) || -> . % 76.16/76.33 133739[112:SSi:133738.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.33 133740[110:Spt:133739.0,133075.0,133076.0] || until2p7(s19)*+ -> . % 76.16/76.33 133741[110:Spt:133739.0,133075.1] || -> node4(s18)*. % 76.16/76.33 133743[110:MRR:864.0,133741.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.33 133746[110:Res:53.1,133743.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.33 133751[111:Spt:133746.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 133753[111:Res:133751.0,61.1] always3(s18) || -> . % 76.16/76.33 133754[111:SSi:133753.0,78146.0,78150.0,108768.0,133074.0,133741.0] || -> . % 76.16/76.33 133755[111:Spt:133754.0,133746.0,133751.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.33 133756[111:Spt:133754.0,133746.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 133760[111:Res:133756.0,61.1] always3(s19) || -> . % 76.16/76.33 133761[111:SSi:133760.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.33 133762[109:Spt:133761.0,133073.0,133074.0] || until2p7(s18)*+ -> . % 76.16/76.33 133763[109:Spt:133761.0,133073.1] || -> node4(s17)*. % 76.16/76.33 133765[109:MRR:867.0,133763.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.33 133768[109:Res:53.1,133765.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.33 133770[110:Spt:133768.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 133772[110:Res:133770.0,61.1] always3(s17) || -> . % 76.16/76.33 133773[110:SSi:133772.0,78142.0,78145.0,108767.0,133072.0,133763.0] || -> . % 76.16/76.33 133774[110:Spt:133773.0,133768.0,133770.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.33 133775[110:Spt:133773.0,133768.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 133779[110:Res:133775.0,61.1] always3(s18) || -> . % 76.16/76.33 133780[110:SSi:133779.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.33 133781[108:Spt:133780.0,133071.0,133072.0] || until2p7(s17)*+ -> . % 76.16/76.33 133782[108:Spt:133780.0,133071.1] || -> node4(s16)*. % 76.16/76.33 133784[108:MRR:870.0,133782.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.33 133787[108:Res:53.1,133784.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.33 133789[109:Spt:133787.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 133791[109:Res:133789.0,61.1] always3(s16) || -> . % 76.16/76.33 133792[109:SSi:133791.0,78137.0,78141.0,108766.0,133070.0,133782.0] || -> . % 76.16/76.33 133793[109:Spt:133792.0,133787.0,133789.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.33 133794[109:Spt:133792.0,133787.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 133798[109:Res:133794.0,61.1] always3(s17) || -> . % 76.16/76.33 133799[109:SSi:133798.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.33 133800[107:Spt:133799.0,133069.0,133070.0] || until2p7(s16)*+ -> . % 76.16/76.33 133801[107:Spt:133799.0,133069.1] || -> node4(s15)*. % 76.16/76.33 133803[107:MRR:873.0,133801.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.33 133806[107:Res:53.1,133803.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.33 133808[108:Spt:133806.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 133810[108:Res:133808.0,61.1] always3(s15) || -> . % 76.16/76.33 133811[108:SSi:133810.0,78133.0,78136.0,108765.0,133068.0,133801.0] || -> . % 76.16/76.33 133812[108:Spt:133811.0,133806.0,133808.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.33 133813[108:Spt:133811.0,133806.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 133817[108:Res:133813.0,61.1] always3(s16) || -> . % 76.16/76.33 133818[108:SSi:133817.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.33 133819[106:Spt:133818.0,133067.0,133068.0] || until2p7(s15)*+ -> . % 76.16/76.33 133820[106:Spt:133818.0,133067.1] || -> node4(s14)*. % 76.16/76.33 133822[106:MRR:876.0,133820.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.33 133825[106:Res:53.1,133822.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.33 133830[107:Spt:133825.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 133832[107:Res:133830.0,61.1] always3(s14) || -> . % 76.16/76.33 133833[107:SSi:133832.0,78128.0,78132.0,108764.0,133066.0,133820.0] || -> . % 76.16/76.33 133834[107:Spt:133833.0,133825.0,133830.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.33 133835[107:Spt:133833.0,133825.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 133839[107:Res:133835.0,61.1] always3(s15) || -> . % 76.16/76.33 133840[107:SSi:133839.0,78133.0,78136.0,108765.0] || -> . % 76.16/76.33 133841[105:Spt:133840.0,133065.0,133066.0] || until2p7(s14)*+ -> . % 76.16/76.33 133842[105:Spt:133840.0,133065.1] || -> node4(s13)*. % 76.16/76.33 133844[105:MRR:879.0,133842.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.33 133847[105:Res:53.1,133844.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.33 133849[106:Spt:133847.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 133851[106:Res:133849.0,61.1] always3(s13) || -> . % 76.16/76.33 133852[106:SSi:133851.0,78124.0,78127.0,108763.0,133064.0,133842.0] || -> . % 76.16/76.33 133853[106:Spt:133852.0,133847.0,133849.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.33 133854[106:Spt:133852.0,133847.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 133858[106:Res:133854.0,61.1] always3(s14) || -> . % 76.16/76.33 133859[106:SSi:133858.0,78128.0,78132.0,108764.0] || -> . % 76.16/76.33 133860[104:Spt:133859.0,133063.0,133064.0] || until2p7(s13)*+ -> . % 76.16/76.33 133861[104:Spt:133859.0,133063.1] || -> node4(s12)*. % 76.16/76.33 133863[104:MRR:882.0,133861.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.33 133866[104:Res:53.1,133863.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.33 133868[105:Spt:133866.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 133870[105:Res:133868.0,61.1] always3(s12) || -> . % 76.16/76.33 133871[105:SSi:133870.0,78119.0,78123.0,108762.0,133062.0,133861.0] || -> . % 76.16/76.33 133872[105:Spt:133871.0,133866.0,133868.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.33 133873[105:Spt:133871.0,133866.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 133877[105:Res:133873.0,61.1] always3(s13) || -> . % 76.16/76.33 133878[105:SSi:133877.0,78124.0,78127.0,108763.0] || -> . % 76.16/76.33 133879[103:Spt:133878.0,133061.0,133062.0] || until2p7(s12)*+ -> . % 76.16/76.33 133880[103:Spt:133878.0,133061.1] || -> node4(s11)*. % 76.16/76.33 133882[103:MRR:885.0,133880.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.33 133885[103:Res:53.1,133882.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.33 133887[104:Spt:133885.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 133889[104:Res:133887.0,61.1] always3(s11) || -> . % 76.16/76.33 133890[104:SSi:133889.0,78115.0,78118.0,108761.0,133060.0,133880.0] || -> . % 76.16/76.33 133891[104:Spt:133890.0,133885.0,133887.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.33 133892[104:Spt:133890.0,133885.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 133896[104:Res:133892.0,61.1] always3(s12) || -> . % 76.16/76.33 133897[104:SSi:133896.0,78119.0,78123.0,108762.0] || -> . % 76.16/76.33 133898[102:Spt:133897.0,133059.0,133060.0] || until2p7(s11)*+ -> . % 76.16/76.33 133899[102:Spt:133897.0,133059.1] || -> node4(s10)*. % 76.16/76.33 133901[102:MRR:888.0,133899.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.33 133904[102:Res:53.1,133901.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.33 133909[103:Spt:133904.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 133911[103:Res:133909.0,61.1] always3(s10) || -> . % 76.16/76.33 133912[103:SSi:133911.0,78110.0,78114.0,108760.0,133058.0,133899.0] || -> . % 76.16/76.33 133913[103:Spt:133912.0,133904.0,133909.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.33 133914[103:Spt:133912.0,133904.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 133918[103:Res:133914.0,61.1] always3(s11) || -> . % 76.16/76.33 133919[103:SSi:133918.0,78115.0,78118.0,108761.0] || -> . % 76.16/76.33 133920[101:Spt:133919.0,133057.0,133058.0] || until2p7(s10)*+ -> . % 76.16/76.33 133921[101:Spt:133919.0,133057.1] || -> node4(s9)*. % 76.16/76.33 133923[101:MRR:891.0,133921.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.33 133926[101:Res:53.1,133923.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.33 133928[102:Spt:133926.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 133930[102:Res:133928.0,61.1] always3(s9) || -> . % 76.16/76.33 133931[102:SSi:133930.0,78106.0,78109.0,108759.0,133056.0,133921.0] || -> . % 76.16/76.33 133932[102:Spt:133931.0,133926.0,133928.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.33 133933[102:Spt:133931.0,133926.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 133937[102:Res:133933.0,61.1] always3(s10) || -> . % 76.16/76.33 133938[102:SSi:133937.0,78110.0,78114.0,108760.0] || -> . % 76.16/76.33 133939[100:Spt:133938.0,133055.0,133056.0] || until2p7(s9)*+ -> . % 76.16/76.33 133940[100:Spt:133938.0,133055.1] || -> node4(s8)*. % 76.16/76.33 133942[100:MRR:894.0,133940.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.33 133945[100:Res:53.1,133942.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.33 133947[101:Spt:133945.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.33 133949[101:Res:133947.0,61.1] always3(s8) || -> . % 76.16/76.33 133950[101:SSi:133949.0,78101.0,78105.0,108758.0,133054.0,133940.0] || -> . % 76.16/76.33 133951[101:Spt:133950.0,133945.0,133947.0] || m_main_v_state(s8,c_busy)* -> . % 76.16/76.33 133952[101:Spt:133950.0,133945.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 133956[101:Res:133952.0,61.1] always3(s9) || -> . % 76.16/76.33 133957[101:SSi:133956.0,78106.0,78109.0,108759.0] || -> . % 76.16/76.33 133958[99:Spt:133957.0,133053.0,133054.0] || until2p7(s8)*+ -> . % 76.16/76.33 133959[99:Spt:133957.0,133053.1] || -> node4(s7)*. % 76.16/76.33 133961[99:MRR:897.0,133959.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.16/76.33 133964[99:Res:53.1,133961.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.16/76.33 133966[100:Spt:133964.0] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.33 133968[100:Res:133966.0,61.1] always3(s7) || -> . % 76.16/76.33 133969[100:SSi:133968.0,78097.0,78100.0,108757.0,133052.0,133959.0] || -> . % 76.16/76.33 133970[100:Spt:133969.0,133964.0,133966.0] || m_main_v_state(s7,c_busy)* -> . % 76.16/76.33 133971[100:Spt:133969.0,133964.1] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.33 133975[100:Res:133971.0,61.1] always3(s8) || -> . % 76.16/76.33 133976[100:SSi:133975.0,78101.0,78105.0,108758.0] || -> . % 76.16/76.33 133977[98:Spt:133976.0,133051.0,133052.0] || until2p7(s7)*+ -> . % 76.16/76.33 133978[98:Spt:133976.0,133051.1] || -> node4(s6)*. % 76.16/76.33 133980[98:MRR:900.0,133978.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.16/76.33 133983[98:Res:53.1,133980.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.16/76.33 133985[98:MRR:133983.0,133041.0] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.33 133990[98:Res:133985.0,61.1] always3(s7) || -> . % 76.16/76.33 133991[98:SSi:133990.0,78097.0,78100.0,108757.0] || -> . % 76.16/76.33 133992[96:Spt:133991.0,132883.0,132886.0] || trans(s49,s6)*+ -> . % 76.16/76.33 133993[96:Spt:133991.0,132883.1,132883.2,132883.3] || -> trans(s49,s5) trans(s49,s4) node2(s49,s3)*. % 76.16/76.33 133995[96:MRR:132885.1,133992.0] xuntil6(s49) || -> trans(s49,s5) trans(s49,s4)* until2p7(s3). % 76.16/76.33 133996[97:Spt:133993.0] || -> trans(s49,s5)*. % 76.16/76.33 133997[97:Res:133996.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s5)*. % 76.16/76.33 133999[97:Res:133996.0,60.0] || -> node2(s49,s5)*. % 76.16/76.33 134000[97:SSi:133997.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s5)*. % 76.16/76.33 134001[97:Res:133999.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)*. % 76.16/76.33 134147[97:SoR:134001.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)*. % 76.16/76.33 134149[97:SoR:134147.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)* xuntil6(s49). % 76.16/76.33 134150[97:SSi:134149.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s5,c_busy)* xuntil6(s49). % 76.16/76.33 134151[98:Spt:134150.1] || -> m_main_v_state(s5,c_busy)*. % 76.16/76.33 134153[98:Res:134151.0,61.1] always3(s5) || -> . % 76.16/76.33 134154[98:SSi:134153.0,78089.0,78092.0,108755.0] || -> . % 76.16/76.33 134155[98:Spt:134154.0,134150.1,134151.0] || m_main_v_state(s5,c_busy)*+ -> . % 76.16/76.33 134156[98:Spt:134154.0,134150.0,134150.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 134160[98:MRR:134147.2,134155.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 134161[98:Res:53.1,134156.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 134163[98:MRR:134161.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 134164[98:MRR:134000.0,134163.0] || -> until2p7(s5)*. % 76.16/76.33 134165[98:MRR:201.0,134164.0] || -> until2p7(s6)* node4(s5). % 76.16/76.33 134166[99:Spt:134165.0] || -> until2p7(s6)*. % 76.16/76.33 134167[99:MRR:202.0,134166.0] || -> until2p7(s7)* node4(s6). % 76.16/76.33 134168[100:Spt:134167.0] || -> until2p7(s7)*. % 76.16/76.33 134169[100:MRR:203.0,134168.0] || -> until2p7(s8)* node4(s7). % 76.16/76.33 134170[101:Spt:134169.0] || -> until2p7(s8)*. % 76.16/76.33 134171[101:MRR:204.0,134170.0] || -> until2p7(s9)* node4(s8). % 76.16/76.33 134172[102:Spt:134171.0] || -> until2p7(s9)*. % 76.16/76.33 134173[102:MRR:205.0,134172.0] || -> until2p7(s10)* node4(s9). % 76.16/76.33 134174[103:Spt:134173.0] || -> until2p7(s10)*. % 76.16/76.33 134175[103:MRR:206.0,134174.0] || -> until2p7(s11)* node4(s10). % 76.16/76.33 134176[104:Spt:134175.0] || -> until2p7(s11)*. % 76.16/76.33 134177[104:MRR:207.0,134176.0] || -> until2p7(s12)* node4(s11). % 76.16/76.33 134178[105:Spt:134177.0] || -> until2p7(s12)*. % 76.16/76.33 134179[105:MRR:208.0,134178.0] || -> until2p7(s13)* node4(s12). % 76.16/76.33 134180[106:Spt:134179.0] || -> until2p7(s13)*. % 76.16/76.33 134181[106:MRR:209.0,134180.0] || -> until2p7(s14)* node4(s13). % 76.16/76.33 134182[107:Spt:134181.0] || -> until2p7(s14)*. % 76.16/76.33 134183[107:MRR:210.0,134182.0] || -> until2p7(s15)* node4(s14). % 76.16/76.33 134184[108:Spt:134183.0] || -> until2p7(s15)*. % 76.16/76.33 134185[108:MRR:211.0,134184.0] || -> until2p7(s16)* node4(s15). % 76.16/76.33 134186[109:Spt:134185.0] || -> until2p7(s16)*. % 76.16/76.33 134187[109:MRR:212.0,134186.0] || -> until2p7(s17)* node4(s16). % 76.16/76.33 134188[110:Spt:134187.0] || -> until2p7(s17)*. % 76.16/76.33 134189[110:MRR:213.0,134188.0] || -> until2p7(s18)* node4(s17). % 76.16/76.33 134190[111:Spt:134189.0] || -> until2p7(s18)*. % 76.16/76.33 134191[111:MRR:214.0,134190.0] || -> until2p7(s19)* node4(s18). % 76.16/76.33 134192[112:Spt:134191.0] || -> until2p7(s19)*. % 76.16/76.33 134193[112:MRR:215.0,134192.0] || -> until2p7(s20)* node4(s19). % 76.16/76.33 134194[113:Spt:134193.0] || -> until2p7(s20)*. % 76.16/76.33 134195[113:MRR:216.0,134194.0] || -> until2p7(s21)* node4(s20). % 76.16/76.33 134196[114:Spt:134195.0] || -> until2p7(s21)*. % 76.16/76.33 134197[114:MRR:217.0,134196.0] || -> until2p7(s22)* node4(s21). % 76.16/76.33 134198[115:Spt:134197.0] || -> until2p7(s22)*. % 76.16/76.33 134199[115:MRR:218.0,134198.0] || -> until2p7(s23)* node4(s22). % 76.16/76.33 134200[116:Spt:134199.0] || -> until2p7(s23)*. % 76.16/76.33 134201[116:MRR:219.0,134200.0] || -> until2p7(s24)* node4(s23). % 76.16/76.33 134202[117:Spt:134201.0] || -> until2p7(s24)*. % 76.16/76.33 134203[117:MRR:220.0,134202.0] || -> until2p7(s25)* node4(s24). % 76.16/76.33 134204[118:Spt:134203.0] || -> until2p7(s25)*. % 76.16/76.33 134205[118:MRR:221.0,134204.0] || -> until2p7(s26)* node4(s25). % 76.16/76.33 134206[119:Spt:134205.0] || -> until2p7(s26)*. % 76.16/76.33 134207[119:MRR:222.0,134206.0] || -> until2p7(s27)* node4(s26). % 76.16/76.33 134208[120:Spt:134207.0] || -> until2p7(s27)*. % 76.16/76.33 134209[120:MRR:223.0,134208.0] || -> until2p7(s28)* node4(s27). % 76.16/76.33 134210[121:Spt:134209.0] || -> until2p7(s28)*. % 76.16/76.33 134211[121:MRR:224.0,134210.0] || -> until2p7(s29)* node4(s28). % 76.16/76.33 134212[122:Spt:134211.0] || -> until2p7(s29)*. % 76.16/76.33 134213[122:MRR:225.0,134212.0] || -> until2p7(s30)* node4(s29). % 76.16/76.33 134214[123:Spt:134213.0] || -> until2p7(s30)*. % 76.16/76.33 134215[123:MRR:226.0,134214.0] || -> until2p7(s31)* node4(s30). % 76.16/76.33 134216[124:Spt:134215.0] || -> until2p7(s31)*. % 76.16/76.33 134217[124:MRR:227.0,134216.0] || -> until2p7(s32)* node4(s31). % 76.16/76.33 134218[125:Spt:134217.0] || -> until2p7(s32)*. % 76.16/76.33 134219[125:MRR:228.0,134218.0] || -> until2p7(s33)* node4(s32). % 76.16/76.33 134220[126:Spt:134219.0] || -> until2p7(s33)*. % 76.16/76.33 134221[126:MRR:229.0,134220.0] || -> until2p7(s34)* node4(s33). % 76.16/76.33 134222[127:Spt:134221.0] || -> until2p7(s34)*. % 76.16/76.33 134223[127:MRR:230.0,134222.0] || -> until2p7(s35)* node4(s34). % 76.16/76.33 134224[128:Spt:134223.0] || -> until2p7(s35)*. % 76.16/76.33 134225[128:MRR:231.0,134224.0] || -> until2p7(s36)* node4(s35). % 76.16/76.33 134226[129:Spt:134225.0] || -> until2p7(s36)*. % 76.16/76.33 134227[129:MRR:232.0,134226.0] || -> until2p7(s37)* node4(s36). % 76.16/76.33 134228[130:Spt:134227.0] || -> until2p7(s37)*. % 76.16/76.33 134229[130:MRR:235.0,134228.0] || -> until2p7(s38)* node4(s37). % 76.16/76.33 134230[131:Spt:134229.0] || -> until2p7(s38)*. % 76.16/76.33 134231[131:MRR:236.0,134230.0] || -> until2p7(s39)* node4(s38). % 76.16/76.33 134232[132:Spt:134231.0] || -> until2p7(s39)*. % 76.16/76.33 134233[132:MRR:237.0,134232.0] || -> until2p7(s40)* node4(s39). % 76.16/76.33 134234[133:Spt:134233.0] || -> until2p7(s40)*. % 76.16/76.33 134235[133:MRR:238.0,134234.0] || -> until2p7(s41)* node4(s40). % 76.16/76.33 134236[134:Spt:134235.0] || -> until2p7(s41)*. % 76.16/76.33 134237[134:MRR:239.0,134236.0] || -> until2p7(s42)* node4(s41). % 76.16/76.33 134238[135:Spt:134237.0] || -> until2p7(s42)*. % 76.16/76.33 134239[135:MRR:240.0,134238.0] || -> until2p7(s43)* node4(s42). % 76.16/76.33 134240[136:Spt:134239.0] || -> until2p7(s43)*. % 76.16/76.33 134241[136:MRR:241.0,134240.0] || -> until2p7(s44)* node4(s43). % 76.16/76.33 134242[137:Spt:134241.0] || -> until2p7(s44)*. % 76.16/76.33 134243[137:MRR:539.0,134242.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 134244[138:Spt:134243.0] || -> until2p7(s45)*. % 76.16/76.33 134245[138:MRR:544.0,134244.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 134246[139:Spt:134245.0] || -> until2p7(s46)*. % 76.16/76.33 134247[139:MRR:549.0,134246.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 134248[140:Spt:134247.0] || -> until2p7(s47)*. % 76.16/76.33 134249[140:MRR:554.0,134248.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 134250[141:Spt:134249.0] || -> until2p7(s48)*. % 76.16/76.33 134251[141:MRR:559.0,134250.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 134252[142:Spt:134251.0] || -> until2p7(s49)*. % 76.16/76.33 134253[142:MRR:194.0,134252.0] || -> node4(s49)*. % 76.16/76.33 134254[142:MRR:134160.0,134253.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 134255[142:Res:53.1,134254.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 134257[142:MRR:134255.0,78381.0] || -> . % 76.16/76.33 134258[142:Spt:134257.0,134251.0,134252.0] || until2p7(s49)*+ -> . % 76.16/76.33 134259[142:Spt:134257.0,134251.1] || -> node4(s48)*. % 76.16/76.33 134260[142:MRR:78384.0,134259.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 134263[142:Res:53.1,134260.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 134266[142:Res:134263.0,61.1] always3(s48) || -> . % 76.16/76.33 134267[142:SSi:134266.0,78281.0,78387.0,108798.0,134250.0,134259.0] || -> . % 76.16/76.33 134268[141:Spt:134267.0,134249.0,134250.0] || until2p7(s48)*+ -> . % 76.16/76.33 134269[141:Spt:134267.0,134249.1] || -> node4(s47)*. % 76.16/76.33 134271[141:MRR:777.0,134269.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 134286[141:Res:53.1,134271.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 134288[142:Spt:134286.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 134290[142:Res:134288.0,61.1] always3(s47) || -> . % 76.16/76.33 134291[142:SSi:134290.0,78277.0,78280.0,108797.0,134248.0,134269.0] || -> . % 76.16/76.33 134292[142:Spt:134291.0,134286.0,134288.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 134293[142:Spt:134291.0,134286.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 134297[142:Res:134293.0,61.1] always3(s48) || -> . % 76.16/76.33 134298[142:SSi:134297.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.33 134299[140:Spt:134298.0,134247.0,134248.0] || until2p7(s47)*+ -> . % 76.16/76.33 134300[140:Spt:134298.0,134247.1] || -> node4(s46)*. % 76.16/76.33 134302[140:MRR:780.0,134300.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 134312[140:Res:53.1,134302.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 134314[141:Spt:134312.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 134316[141:Res:134314.0,61.1] always3(s46) || -> . % 76.16/76.33 134317[141:SSi:134316.0,78272.0,78276.0,108796.0,134246.0,134300.0] || -> . % 76.16/76.33 134318[141:Spt:134317.0,134312.0,134314.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 134319[141:Spt:134317.0,134312.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 134323[141:Res:134319.0,61.1] always3(s47) || -> . % 76.16/76.33 134324[141:SSi:134323.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.33 134325[139:Spt:134324.0,134245.0,134246.0] || until2p7(s46)*+ -> . % 76.16/76.33 134326[139:Spt:134324.0,134245.1] || -> node4(s45)*. % 76.16/76.33 134328[139:MRR:783.0,134326.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 134331[139:Res:53.1,134328.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 134333[140:Spt:134331.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 134335[140:Res:134333.0,61.1] always3(s45) || -> . % 76.16/76.33 134336[140:SSi:134335.0,78268.0,78271.0,108795.0,134244.0,134326.0] || -> . % 76.16/76.33 134337[140:Spt:134336.0,134331.0,134333.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.33 134338[140:Spt:134336.0,134331.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 134342[140:Res:134338.0,61.1] always3(s46) || -> . % 76.16/76.33 134343[140:SSi:134342.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.33 134344[138:Spt:134343.0,134243.0,134244.0] || until2p7(s45)*+ -> . % 76.16/76.33 134345[138:Spt:134343.0,134243.1] || -> node4(s44)*. % 76.16/76.33 134347[138:MRR:786.0,134345.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.33 134350[138:Res:53.1,134347.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.33 134352[139:Spt:134350.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 134354[139:Res:134352.0,61.1] always3(s44) || -> . % 76.16/76.33 134355[139:SSi:134354.0,78263.0,78267.0,108794.0,134242.0,134345.0] || -> . % 76.16/76.33 134356[139:Spt:134355.0,134350.0,134352.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.33 134357[139:Spt:134355.0,134350.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 134361[139:Res:134357.0,61.1] always3(s45) || -> . % 76.16/76.33 134362[139:SSi:134361.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.33 134363[137:Spt:134362.0,134241.0,134242.0] || until2p7(s44)*+ -> . % 76.16/76.33 134364[137:Spt:134362.0,134241.1] || -> node4(s43)*. % 76.16/76.33 134366[137:MRR:789.0,134364.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.33 134369[137:Res:53.1,134366.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.33 134374[138:Spt:134369.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 134376[138:Res:134374.0,61.1] always3(s43) || -> . % 76.16/76.33 134377[138:SSi:134376.0,78259.0,78262.0,108793.0,134240.0,134364.0] || -> . % 76.16/76.33 134378[138:Spt:134377.0,134369.0,134374.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.33 134379[138:Spt:134377.0,134369.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 134383[138:Res:134379.0,61.1] always3(s44) || -> . % 76.16/76.33 134384[138:SSi:134383.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.33 134385[136:Spt:134384.0,134239.0,134240.0] || until2p7(s43)*+ -> . % 76.16/76.33 134386[136:Spt:134384.0,134239.1] || -> node4(s42)*. % 76.16/76.33 134388[136:MRR:792.0,134386.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.33 134391[136:Res:53.1,134388.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.33 134393[137:Spt:134391.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 134395[137:Res:134393.0,61.1] always3(s42) || -> . % 76.16/76.33 134396[137:SSi:134395.0,78254.0,78258.0,108792.0,134238.0,134386.0] || -> . % 76.16/76.33 134397[137:Spt:134396.0,134391.0,134393.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.33 134398[137:Spt:134396.0,134391.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 134402[137:Res:134398.0,61.1] always3(s43) || -> . % 76.16/76.33 134403[137:SSi:134402.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.33 134404[135:Spt:134403.0,134237.0,134238.0] || until2p7(s42)*+ -> . % 76.16/76.33 134405[135:Spt:134403.0,134237.1] || -> node4(s41)*. % 76.16/76.33 134407[135:MRR:795.0,134405.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.33 134410[135:Res:53.1,134407.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.33 134412[136:Spt:134410.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 134414[136:Res:134412.0,61.1] always3(s41) || -> . % 76.16/76.33 134415[136:SSi:134414.0,78250.0,78253.0,108791.0,134236.0,134405.0] || -> . % 76.16/76.33 134416[136:Spt:134415.0,134410.0,134412.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.33 134417[136:Spt:134415.0,134410.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 134421[136:Res:134417.0,61.1] always3(s42) || -> . % 76.16/76.33 134422[136:SSi:134421.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.33 134423[134:Spt:134422.0,134235.0,134236.0] || until2p7(s41)*+ -> . % 76.16/76.33 134424[134:Spt:134422.0,134235.1] || -> node4(s40)*. % 76.16/76.33 134426[134:MRR:798.0,134424.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.33 134429[134:Res:53.1,134426.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.33 134431[135:Spt:134429.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 134433[135:Res:134431.0,61.1] always3(s40) || -> . % 76.16/76.33 134434[135:SSi:134433.0,78245.0,78249.0,108790.0,134234.0,134424.0] || -> . % 76.16/76.33 134435[135:Spt:134434.0,134429.0,134431.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.33 134436[135:Spt:134434.0,134429.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 134440[135:Res:134436.0,61.1] always3(s41) || -> . % 76.16/76.33 134441[135:SSi:134440.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.33 134442[133:Spt:134441.0,134233.0,134234.0] || until2p7(s40)*+ -> . % 76.16/76.33 134443[133:Spt:134441.0,134233.1] || -> node4(s39)*. % 76.16/76.33 134445[133:MRR:801.0,134443.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.33 134448[133:Res:53.1,134445.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.33 134453[134:Spt:134448.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 134455[134:Res:134453.0,61.1] always3(s39) || -> . % 76.16/76.33 134456[134:SSi:134455.0,78241.0,78244.0,108789.0,134232.0,134443.0] || -> . % 76.16/76.33 134457[134:Spt:134456.0,134448.0,134453.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.33 134458[134:Spt:134456.0,134448.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 134462[134:Res:134458.0,61.1] always3(s40) || -> . % 76.16/76.33 134463[134:SSi:134462.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.33 134464[132:Spt:134463.0,134231.0,134232.0] || until2p7(s39)*+ -> . % 76.16/76.33 134465[132:Spt:134463.0,134231.1] || -> node4(s38)*. % 76.16/76.33 134467[132:MRR:804.0,134465.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.33 134470[132:Res:53.1,134467.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.33 134472[133:Spt:134470.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 134474[133:Res:134472.0,61.1] always3(s38) || -> . % 76.16/76.33 134475[133:SSi:134474.0,78236.0,78240.0,108788.0,134230.0,134465.0] || -> . % 76.16/76.33 134476[133:Spt:134475.0,134470.0,134472.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.33 134477[133:Spt:134475.0,134470.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 134481[133:Res:134477.0,61.1] always3(s39) || -> . % 76.16/76.33 134482[133:SSi:134481.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.33 134483[131:Spt:134482.0,134229.0,134230.0] || until2p7(s38)*+ -> . % 76.16/76.33 134484[131:Spt:134482.0,134229.1] || -> node4(s37)*. % 76.16/76.33 134486[131:MRR:807.0,134484.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.33 134489[131:Res:53.1,134486.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.33 134491[132:Spt:134489.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 134493[132:Res:134491.0,61.1] always3(s37) || -> . % 76.16/76.33 134494[132:SSi:134493.0,78232.0,78235.0,108787.0,134228.0,134484.0] || -> . % 76.16/76.33 134495[132:Spt:134494.0,134489.0,134491.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.33 134496[132:Spt:134494.0,134489.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 134500[132:Res:134496.0,61.1] always3(s38) || -> . % 76.16/76.33 134501[132:SSi:134500.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.33 134502[130:Spt:134501.0,134227.0,134228.0] || until2p7(s37)*+ -> . % 76.16/76.33 134503[130:Spt:134501.0,134227.1] || -> node4(s36)*. % 76.16/76.33 134505[130:MRR:810.0,134503.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.33 134508[130:Res:53.1,134505.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.33 134510[131:Spt:134508.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 134512[131:Res:134510.0,61.1] always3(s36) || -> . % 76.16/76.33 134513[131:SSi:134512.0,78227.0,78231.0,108786.0,134226.0,134503.0] || -> . % 76.16/76.33 134514[131:Spt:134513.0,134508.0,134510.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.33 134515[131:Spt:134513.0,134508.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 134519[131:Res:134515.0,61.1] always3(s37) || -> . % 76.16/76.33 134520[131:SSi:134519.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.33 134521[129:Spt:134520.0,134225.0,134226.0] || until2p7(s36)*+ -> . % 76.16/76.33 134522[129:Spt:134520.0,134225.1] || -> node4(s35)*. % 76.16/76.33 134524[129:MRR:813.0,134522.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.33 134527[129:Res:53.1,134524.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.33 134532[130:Spt:134527.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 134534[130:Res:134532.0,61.1] always3(s35) || -> . % 76.16/76.33 134535[130:SSi:134534.0,78223.0,78226.0,108785.0,134224.0,134522.0] || -> . % 76.16/76.33 134536[130:Spt:134535.0,134527.0,134532.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.33 134537[130:Spt:134535.0,134527.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 134541[130:Res:134537.0,61.1] always3(s36) || -> . % 76.16/76.33 134542[130:SSi:134541.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.33 134543[128:Spt:134542.0,134223.0,134224.0] || until2p7(s35)*+ -> . % 76.16/76.33 134544[128:Spt:134542.0,134223.1] || -> node4(s34)*. % 76.16/76.33 134546[128:MRR:816.0,134544.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.33 134549[128:Res:53.1,134546.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.33 134551[129:Spt:134549.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 134553[129:Res:134551.0,61.1] always3(s34) || -> . % 76.16/76.33 134554[129:SSi:134553.0,78218.0,78222.0,108784.0,134222.0,134544.0] || -> . % 76.16/76.33 134555[129:Spt:134554.0,134549.0,134551.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.33 134556[129:Spt:134554.0,134549.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 134560[129:Res:134556.0,61.1] always3(s35) || -> . % 76.16/76.33 134561[129:SSi:134560.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.33 134562[127:Spt:134561.0,134221.0,134222.0] || until2p7(s34)*+ -> . % 76.16/76.33 134563[127:Spt:134561.0,134221.1] || -> node4(s33)*. % 76.16/76.33 134565[127:MRR:819.0,134563.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.33 134568[127:Res:53.1,134565.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.33 134570[128:Spt:134568.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 134572[128:Res:134570.0,61.1] always3(s33) || -> . % 76.16/76.33 134573[128:SSi:134572.0,78214.0,78217.0,108783.0,134220.0,134563.0] || -> . % 76.16/76.33 134574[128:Spt:134573.0,134568.0,134570.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.33 134575[128:Spt:134573.0,134568.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 134579[128:Res:134575.0,61.1] always3(s34) || -> . % 76.16/76.33 134580[128:SSi:134579.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.33 134581[126:Spt:134580.0,134219.0,134220.0] || until2p7(s33)*+ -> . % 76.16/76.33 134582[126:Spt:134580.0,134219.1] || -> node4(s32)*. % 76.16/76.33 134584[126:MRR:822.0,134582.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.33 134587[126:Res:53.1,134584.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.33 134589[127:Spt:134587.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 134591[127:Res:134589.0,61.1] always3(s32) || -> . % 76.16/76.33 134592[127:SSi:134591.0,78209.0,78213.0,108782.0,134218.0,134582.0] || -> . % 76.16/76.33 134593[127:Spt:134592.0,134587.0,134589.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.33 134594[127:Spt:134592.0,134587.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 134598[127:Res:134594.0,61.1] always3(s33) || -> . % 76.16/76.33 134599[127:SSi:134598.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.33 134600[125:Spt:134599.0,134217.0,134218.0] || until2p7(s32)*+ -> . % 76.16/76.33 134601[125:Spt:134599.0,134217.1] || -> node4(s31)*. % 76.16/76.33 134603[125:MRR:825.0,134601.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.33 134606[125:Res:53.1,134603.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.33 134611[126:Spt:134606.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 134613[126:Res:134611.0,61.1] always3(s31) || -> . % 76.16/76.33 134614[126:SSi:134613.0,78205.0,78208.0,108781.0,134216.0,134601.0] || -> . % 76.16/76.33 134615[126:Spt:134614.0,134606.0,134611.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.33 134616[126:Spt:134614.0,134606.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 134620[126:Res:134616.0,61.1] always3(s32) || -> . % 76.16/76.33 134621[126:SSi:134620.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.33 134622[124:Spt:134621.0,134215.0,134216.0] || until2p7(s31)*+ -> . % 76.16/76.33 134623[124:Spt:134621.0,134215.1] || -> node4(s30)*. % 76.16/76.33 134625[124:MRR:828.0,134623.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.33 134628[124:Res:53.1,134625.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.33 134630[125:Spt:134628.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 134632[125:Res:134630.0,61.1] always3(s30) || -> . % 76.16/76.33 134633[125:SSi:134632.0,78200.0,78204.0,108780.0,134214.0,134623.0] || -> . % 76.16/76.33 134634[125:Spt:134633.0,134628.0,134630.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.33 134635[125:Spt:134633.0,134628.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 134639[125:Res:134635.0,61.1] always3(s31) || -> . % 76.16/76.33 134640[125:SSi:134639.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.33 134641[123:Spt:134640.0,134213.0,134214.0] || until2p7(s30)*+ -> . % 76.16/76.33 134642[123:Spt:134640.0,134213.1] || -> node4(s29)*. % 76.16/76.33 134644[123:MRR:831.0,134642.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.33 134647[123:Res:53.1,134644.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.33 134649[124:Spt:134647.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 134651[124:Res:134649.0,61.1] always3(s29) || -> . % 76.16/76.33 134652[124:SSi:134651.0,78196.0,78199.0,108779.0,134212.0,134642.0] || -> . % 76.16/76.33 134653[124:Spt:134652.0,134647.0,134649.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.33 134654[124:Spt:134652.0,134647.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 134658[124:Res:134654.0,61.1] always3(s30) || -> . % 76.16/76.33 134659[124:SSi:134658.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.33 134660[122:Spt:134659.0,134211.0,134212.0] || until2p7(s29)*+ -> . % 76.16/76.33 134661[122:Spt:134659.0,134211.1] || -> node4(s28)*. % 76.16/76.33 134663[122:MRR:834.0,134661.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.33 134666[122:Res:53.1,134663.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.33 134668[123:Spt:134666.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 134670[123:Res:134668.0,61.1] always3(s28) || -> . % 76.16/76.33 134671[123:SSi:134670.0,78191.0,78195.0,108778.0,134210.0,134661.0] || -> . % 76.16/76.33 134672[123:Spt:134671.0,134666.0,134668.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.33 134673[123:Spt:134671.0,134666.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 134677[123:Res:134673.0,61.1] always3(s29) || -> . % 76.16/76.33 134678[123:SSi:134677.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.33 134679[121:Spt:134678.0,134209.0,134210.0] || until2p7(s28)*+ -> . % 76.16/76.33 134680[121:Spt:134678.0,134209.1] || -> node4(s27)*. % 76.16/76.33 134682[121:MRR:837.0,134680.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.33 134685[121:Res:53.1,134682.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.33 134690[122:Spt:134685.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 134692[122:Res:134690.0,61.1] always3(s27) || -> . % 76.16/76.33 134693[122:SSi:134692.0,78187.0,78190.0,108777.0,134208.0,134680.0] || -> . % 76.16/76.33 134694[122:Spt:134693.0,134685.0,134690.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.33 134695[122:Spt:134693.0,134685.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 134699[122:Res:134695.0,61.1] always3(s28) || -> . % 76.16/76.33 134700[122:SSi:134699.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.33 134701[120:Spt:134700.0,134207.0,134208.0] || until2p7(s27)*+ -> . % 76.16/76.33 134702[120:Spt:134700.0,134207.1] || -> node4(s26)*. % 76.16/76.33 134704[120:MRR:840.0,134702.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.33 134707[120:Res:53.1,134704.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.33 134709[121:Spt:134707.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 134711[121:Res:134709.0,61.1] always3(s26) || -> . % 76.16/76.33 134712[121:SSi:134711.0,78182.0,78186.0,108776.0,134206.0,134702.0] || -> . % 76.16/76.33 134713[121:Spt:134712.0,134707.0,134709.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.33 134714[121:Spt:134712.0,134707.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 134718[121:Res:134714.0,61.1] always3(s27) || -> . % 76.16/76.33 134719[121:SSi:134718.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.33 134720[119:Spt:134719.0,134205.0,134206.0] || until2p7(s26)*+ -> . % 76.16/76.33 134721[119:Spt:134719.0,134205.1] || -> node4(s25)*. % 76.16/76.33 134723[119:MRR:843.0,134721.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.33 134726[119:Res:53.1,134723.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.33 134728[120:Spt:134726.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 134730[120:Res:134728.0,61.1] always3(s25) || -> . % 76.16/76.33 134731[120:SSi:134730.0,78178.0,78181.0,108775.0,134204.0,134721.0] || -> . % 76.16/76.33 134732[120:Spt:134731.0,134726.0,134728.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.33 134733[120:Spt:134731.0,134726.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 134737[120:Res:134733.0,61.1] always3(s26) || -> . % 76.16/76.33 134738[120:SSi:134737.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.33 134739[118:Spt:134738.0,134203.0,134204.0] || until2p7(s25)*+ -> . % 76.16/76.33 134740[118:Spt:134738.0,134203.1] || -> node4(s24)*. % 76.16/76.33 134742[118:MRR:846.0,134740.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.33 134745[118:Res:53.1,134742.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.33 134747[119:Spt:134745.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 134749[119:Res:134747.0,61.1] always3(s24) || -> . % 76.16/76.33 134750[119:SSi:134749.0,78173.0,78177.0,108774.0,134202.0,134740.0] || -> . % 76.16/76.33 134751[119:Spt:134750.0,134745.0,134747.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.33 134752[119:Spt:134750.0,134745.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 134756[119:Res:134752.0,61.1] always3(s25) || -> . % 76.16/76.33 134757[119:SSi:134756.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.33 134758[117:Spt:134757.0,134201.0,134202.0] || until2p7(s24)*+ -> . % 76.16/76.33 134759[117:Spt:134757.0,134201.1] || -> node4(s23)*. % 76.16/76.33 134761[117:MRR:849.0,134759.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.33 134764[117:Res:53.1,134761.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.33 134769[118:Spt:134764.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 134771[118:Res:134769.0,61.1] always3(s23) || -> . % 76.16/76.33 134772[118:SSi:134771.0,78169.0,78172.0,108773.0,134200.0,134759.0] || -> . % 76.16/76.33 134773[118:Spt:134772.0,134764.0,134769.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.33 134774[118:Spt:134772.0,134764.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 134778[118:Res:134774.0,61.1] always3(s24) || -> . % 76.16/76.33 134779[118:SSi:134778.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.33 134780[116:Spt:134779.0,134199.0,134200.0] || until2p7(s23)*+ -> . % 76.16/76.33 134781[116:Spt:134779.0,134199.1] || -> node4(s22)*. % 76.16/76.33 134783[116:MRR:852.0,134781.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.33 134786[116:Res:53.1,134783.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.33 134788[117:Spt:134786.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 134790[117:Res:134788.0,61.1] always3(s22) || -> . % 76.16/76.33 134791[117:SSi:134790.0,78164.0,78168.0,108772.0,134198.0,134781.0] || -> . % 76.16/76.33 134792[117:Spt:134791.0,134786.0,134788.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.33 134793[117:Spt:134791.0,134786.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 134797[117:Res:134793.0,61.1] always3(s23) || -> . % 76.16/76.33 134798[117:SSi:134797.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.33 134799[115:Spt:134798.0,134197.0,134198.0] || until2p7(s22)*+ -> . % 76.16/76.33 134800[115:Spt:134798.0,134197.1] || -> node4(s21)*. % 76.16/76.33 134802[115:MRR:855.0,134800.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.33 134805[115:Res:53.1,134802.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.33 134807[116:Spt:134805.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 134809[116:Res:134807.0,61.1] always3(s21) || -> . % 76.16/76.33 134810[116:SSi:134809.0,78160.0,78163.0,108771.0,134196.0,134800.0] || -> . % 76.16/76.33 134811[116:Spt:134810.0,134805.0,134807.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.33 134812[116:Spt:134810.0,134805.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 134816[116:Res:134812.0,61.1] always3(s22) || -> . % 76.16/76.33 134817[116:SSi:134816.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.33 134818[114:Spt:134817.0,134195.0,134196.0] || until2p7(s21)*+ -> . % 76.16/76.33 134819[114:Spt:134817.0,134195.1] || -> node4(s20)*. % 76.16/76.33 134821[114:MRR:858.0,134819.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.33 134824[114:Res:53.1,134821.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.33 134826[115:Spt:134824.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 134828[115:Res:134826.0,61.1] always3(s20) || -> . % 76.16/76.33 134829[115:SSi:134828.0,78155.0,78159.0,108770.0,134194.0,134819.0] || -> . % 76.16/76.33 134830[115:Spt:134829.0,134824.0,134826.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.33 134831[115:Spt:134829.0,134824.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 134835[115:Res:134831.0,61.1] always3(s21) || -> . % 76.16/76.33 134836[115:SSi:134835.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.33 134837[113:Spt:134836.0,134193.0,134194.0] || until2p7(s20)*+ -> . % 76.16/76.33 134838[113:Spt:134836.0,134193.1] || -> node4(s19)*. % 76.16/76.33 134840[113:MRR:861.0,134838.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.33 134843[113:Res:53.1,134840.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.33 134848[114:Spt:134843.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 134850[114:Res:134848.0,61.1] always3(s19) || -> . % 76.16/76.33 134851[114:SSi:134850.0,78151.0,78154.0,108769.0,134192.0,134838.0] || -> . % 76.16/76.33 134852[114:Spt:134851.0,134843.0,134848.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.33 134853[114:Spt:134851.0,134843.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 134857[114:Res:134853.0,61.1] always3(s20) || -> . % 76.16/76.33 134858[114:SSi:134857.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.33 134859[112:Spt:134858.0,134191.0,134192.0] || until2p7(s19)*+ -> . % 76.16/76.33 134860[112:Spt:134858.0,134191.1] || -> node4(s18)*. % 76.16/76.33 134862[112:MRR:864.0,134860.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.33 134865[112:Res:53.1,134862.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.33 134867[113:Spt:134865.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 134869[113:Res:134867.0,61.1] always3(s18) || -> . % 76.16/76.33 134870[113:SSi:134869.0,78146.0,78150.0,108768.0,134190.0,134860.0] || -> . % 76.16/76.33 134871[113:Spt:134870.0,134865.0,134867.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.33 134872[113:Spt:134870.0,134865.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 134876[113:Res:134872.0,61.1] always3(s19) || -> . % 76.16/76.33 134877[113:SSi:134876.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.33 134878[111:Spt:134877.0,134189.0,134190.0] || until2p7(s18)*+ -> . % 76.16/76.33 134879[111:Spt:134877.0,134189.1] || -> node4(s17)*. % 76.16/76.33 134881[111:MRR:867.0,134879.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.33 134884[111:Res:53.1,134881.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.33 134886[112:Spt:134884.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 134888[112:Res:134886.0,61.1] always3(s17) || -> . % 76.16/76.33 134889[112:SSi:134888.0,78142.0,78145.0,108767.0,134188.0,134879.0] || -> . % 76.16/76.33 134890[112:Spt:134889.0,134884.0,134886.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.33 134891[112:Spt:134889.0,134884.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 134895[112:Res:134891.0,61.1] always3(s18) || -> . % 76.16/76.33 134896[112:SSi:134895.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.33 134897[110:Spt:134896.0,134187.0,134188.0] || until2p7(s17)*+ -> . % 76.16/76.33 134898[110:Spt:134896.0,134187.1] || -> node4(s16)*. % 76.16/76.33 134900[110:MRR:870.0,134898.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.33 134903[110:Res:53.1,134900.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.33 134905[111:Spt:134903.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 134907[111:Res:134905.0,61.1] always3(s16) || -> . % 76.16/76.33 134908[111:SSi:134907.0,78137.0,78141.0,108766.0,134186.0,134898.0] || -> . % 76.16/76.33 134909[111:Spt:134908.0,134903.0,134905.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.33 134910[111:Spt:134908.0,134903.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 134914[111:Res:134910.0,61.1] always3(s17) || -> . % 76.16/76.33 134915[111:SSi:134914.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.33 134916[109:Spt:134915.0,134185.0,134186.0] || until2p7(s16)*+ -> . % 76.16/76.33 134917[109:Spt:134915.0,134185.1] || -> node4(s15)*. % 76.16/76.33 134919[109:MRR:873.0,134917.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.33 134922[109:Res:53.1,134919.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.33 134927[110:Spt:134922.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 134929[110:Res:134927.0,61.1] always3(s15) || -> . % 76.16/76.33 134930[110:SSi:134929.0,78133.0,78136.0,108765.0,134184.0,134917.0] || -> . % 76.16/76.33 134931[110:Spt:134930.0,134922.0,134927.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.33 134932[110:Spt:134930.0,134922.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 134936[110:Res:134932.0,61.1] always3(s16) || -> . % 76.16/76.33 134937[110:SSi:134936.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.33 134938[108:Spt:134937.0,134183.0,134184.0] || until2p7(s15)*+ -> . % 76.16/76.33 134939[108:Spt:134937.0,134183.1] || -> node4(s14)*. % 76.16/76.33 134941[108:MRR:876.0,134939.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.33 134944[108:Res:53.1,134941.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.33 134946[109:Spt:134944.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 134948[109:Res:134946.0,61.1] always3(s14) || -> . % 76.16/76.33 134949[109:SSi:134948.0,78128.0,78132.0,108764.0,134182.0,134939.0] || -> . % 76.16/76.33 134950[109:Spt:134949.0,134944.0,134946.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.33 134951[109:Spt:134949.0,134944.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 134955[109:Res:134951.0,61.1] always3(s15) || -> . % 76.16/76.33 134956[109:SSi:134955.0,78133.0,78136.0,108765.0] || -> . % 76.16/76.33 134957[107:Spt:134956.0,134181.0,134182.0] || until2p7(s14)*+ -> . % 76.16/76.33 134958[107:Spt:134956.0,134181.1] || -> node4(s13)*. % 76.16/76.33 134960[107:MRR:879.0,134958.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.33 134963[107:Res:53.1,134960.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.33 134965[108:Spt:134963.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 134967[108:Res:134965.0,61.1] always3(s13) || -> . % 76.16/76.33 134968[108:SSi:134967.0,78124.0,78127.0,108763.0,134180.0,134958.0] || -> . % 76.16/76.33 134969[108:Spt:134968.0,134963.0,134965.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.33 134970[108:Spt:134968.0,134963.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 134974[108:Res:134970.0,61.1] always3(s14) || -> . % 76.16/76.33 134975[108:SSi:134974.0,78128.0,78132.0,108764.0] || -> . % 76.16/76.33 134976[106:Spt:134975.0,134179.0,134180.0] || until2p7(s13)*+ -> . % 76.16/76.33 134977[106:Spt:134975.0,134179.1] || -> node4(s12)*. % 76.16/76.33 134979[106:MRR:882.0,134977.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.33 134982[106:Res:53.1,134979.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.33 134984[107:Spt:134982.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 134986[107:Res:134984.0,61.1] always3(s12) || -> . % 76.16/76.33 134987[107:SSi:134986.0,78119.0,78123.0,108762.0,134178.0,134977.0] || -> . % 76.16/76.33 134988[107:Spt:134987.0,134982.0,134984.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.33 134989[107:Spt:134987.0,134982.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 134993[107:Res:134989.0,61.1] always3(s13) || -> . % 76.16/76.33 134994[107:SSi:134993.0,78124.0,78127.0,108763.0] || -> . % 76.16/76.33 134995[105:Spt:134994.0,134177.0,134178.0] || until2p7(s12)*+ -> . % 76.16/76.33 134996[105:Spt:134994.0,134177.1] || -> node4(s11)*. % 76.16/76.33 134998[105:MRR:885.0,134996.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.33 135001[105:Res:53.1,134998.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.33 135006[106:Spt:135001.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 135008[106:Res:135006.0,61.1] always3(s11) || -> . % 76.16/76.33 135009[106:SSi:135008.0,78115.0,78118.0,108761.0,134176.0,134996.0] || -> . % 76.16/76.33 135010[106:Spt:135009.0,135001.0,135006.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.33 135011[106:Spt:135009.0,135001.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 135015[106:Res:135011.0,61.1] always3(s12) || -> . % 76.16/76.33 135016[106:SSi:135015.0,78119.0,78123.0,108762.0] || -> . % 76.16/76.33 135017[104:Spt:135016.0,134175.0,134176.0] || until2p7(s11)*+ -> . % 76.16/76.33 135018[104:Spt:135016.0,134175.1] || -> node4(s10)*. % 76.16/76.33 135020[104:MRR:888.0,135018.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.33 135023[104:Res:53.1,135020.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.33 135025[105:Spt:135023.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 135027[105:Res:135025.0,61.1] always3(s10) || -> . % 76.16/76.33 135028[105:SSi:135027.0,78110.0,78114.0,108760.0,134174.0,135018.0] || -> . % 76.16/76.33 135029[105:Spt:135028.0,135023.0,135025.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.33 135030[105:Spt:135028.0,135023.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 135034[105:Res:135030.0,61.1] always3(s11) || -> . % 76.16/76.33 135035[105:SSi:135034.0,78115.0,78118.0,108761.0] || -> . % 76.16/76.33 135036[103:Spt:135035.0,134173.0,134174.0] || until2p7(s10)*+ -> . % 76.16/76.33 135037[103:Spt:135035.0,134173.1] || -> node4(s9)*. % 76.16/76.33 135039[103:MRR:891.0,135037.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.33 135042[103:Res:53.1,135039.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.33 135044[104:Spt:135042.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 135046[104:Res:135044.0,61.1] always3(s9) || -> . % 76.16/76.33 135047[104:SSi:135046.0,78106.0,78109.0,108759.0,134172.0,135037.0] || -> . % 76.16/76.33 135048[104:Spt:135047.0,135042.0,135044.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.33 135049[104:Spt:135047.0,135042.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 135053[104:Res:135049.0,61.1] always3(s10) || -> . % 76.16/76.33 135054[104:SSi:135053.0,78110.0,78114.0,108760.0] || -> . % 76.16/76.33 135055[102:Spt:135054.0,134171.0,134172.0] || until2p7(s9)*+ -> . % 76.16/76.33 135056[102:Spt:135054.0,134171.1] || -> node4(s8)*. % 76.16/76.33 135058[102:MRR:894.0,135056.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.33 135061[102:Res:53.1,135058.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.33 135063[103:Spt:135061.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.33 135065[103:Res:135063.0,61.1] always3(s8) || -> . % 76.16/76.33 135066[103:SSi:135065.0,78101.0,78105.0,108758.0,134170.0,135056.0] || -> . % 76.16/76.33 135067[103:Spt:135066.0,135061.0,135063.0] || m_main_v_state(s8,c_busy)* -> . % 76.16/76.33 135068[103:Spt:135066.0,135061.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 135072[103:Res:135068.0,61.1] always3(s9) || -> . % 76.16/76.33 135073[103:SSi:135072.0,78106.0,78109.0,108759.0] || -> . % 76.16/76.33 135074[101:Spt:135073.0,134169.0,134170.0] || until2p7(s8)*+ -> . % 76.16/76.33 135075[101:Spt:135073.0,134169.1] || -> node4(s7)*. % 76.16/76.33 135077[101:MRR:897.0,135075.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.16/76.33 135080[101:Res:53.1,135077.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.16/76.33 135085[102:Spt:135080.0] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.33 135087[102:Res:135085.0,61.1] always3(s7) || -> . % 76.16/76.33 135088[102:SSi:135087.0,78097.0,78100.0,108757.0,134168.0,135075.0] || -> . % 76.16/76.33 135089[102:Spt:135088.0,135080.0,135085.0] || m_main_v_state(s7,c_busy)* -> . % 76.16/76.33 135090[102:Spt:135088.0,135080.1] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.33 135094[102:Res:135090.0,61.1] always3(s8) || -> . % 76.16/76.33 135095[102:SSi:135094.0,78101.0,78105.0,108758.0] || -> . % 76.16/76.33 135096[100:Spt:135095.0,134167.0,134168.0] || until2p7(s7)*+ -> . % 76.16/76.33 135097[100:Spt:135095.0,134167.1] || -> node4(s6)*. % 76.16/76.33 135099[100:MRR:900.0,135097.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.16/76.33 135102[100:Res:53.1,135099.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.16/76.33 135104[101:Spt:135102.0] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.33 135106[101:Res:135104.0,61.1] always3(s6) || -> . % 76.16/76.33 135107[101:SSi:135106.0,78093.0,78096.0,108756.0,134166.0,135097.0] || -> . % 76.16/76.33 135108[101:Spt:135107.0,135102.0,135104.0] || m_main_v_state(s6,c_busy)* -> . % 76.16/76.33 135109[101:Spt:135107.0,135102.1] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.33 135113[101:Res:135109.0,61.1] always3(s7) || -> . % 76.16/76.33 135114[101:SSi:135113.0,78097.0,78100.0,108757.0] || -> . % 76.16/76.33 135115[99:Spt:135114.0,134165.0,134166.0] || until2p7(s6)*+ -> . % 76.16/76.33 135116[99:Spt:135114.0,134165.1] || -> node4(s5)*. % 76.16/76.33 135118[99:MRR:903.0,135116.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.16/76.33 135121[99:Res:53.1,135118.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.16/76.33 135123[99:MRR:135121.0,134155.0] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.33 135125[99:Res:135123.0,61.1] always3(s6) || -> . % 76.16/76.33 135126[99:SSi:135125.0,78093.0,78096.0,108756.0] || -> . % 76.16/76.33 135127[97:Spt:135126.0,133993.0,133996.0] || trans(s49,s5)*+ -> . % 76.16/76.33 135128[97:Spt:135126.0,133993.1,133993.2] || -> trans(s49,s4) node2(s49,s3)*. % 76.16/76.33 135130[97:MRR:133995.1,135127.0] xuntil6(s49) || -> trans(s49,s4)* until2p7(s3). % 76.16/76.33 135131[98:Spt:135128.0] || -> trans(s49,s4)*. % 76.16/76.33 135132[98:Res:135131.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s4)*. % 76.16/76.33 135134[98:Res:135131.0,60.0] || -> node2(s49,s4)*. % 76.16/76.33 135135[98:SSi:135132.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s4)*. % 76.16/76.33 135136[98:Res:135134.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s4,c_busy)*. % 76.16/76.33 135286[98:SoR:135136.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s4,c_busy)*. % 76.16/76.33 135288[98:SoR:135286.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s4,c_busy)* xuntil6(s49). % 76.16/76.33 135289[98:SSi:135288.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s4,c_busy)* xuntil6(s49). % 76.16/76.33 135290[99:Spt:135289.1] || -> m_main_v_state(s4,c_busy)*. % 76.16/76.33 135292[99:Res:135290.0,61.1] always3(s4) || -> . % 76.16/76.33 135293[99:SSi:135292.0,78085.0,78088.0,108754.0] || -> . % 76.16/76.33 135294[99:Spt:135293.0,135289.1,135290.0] || m_main_v_state(s4,c_busy)*+ -> . % 76.16/76.33 135295[99:Spt:135293.0,135289.0,135289.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 135299[99:MRR:135286.2,135294.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 135300[99:Res:53.1,135295.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 135302[99:MRR:135300.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 135303[99:MRR:135135.0,135302.0] || -> until2p7(s4)*. % 76.16/76.33 135304[99:MRR:200.0,135303.0] || -> until2p7(s5)* node4(s4). % 76.16/76.33 135305[100:Spt:135304.0] || -> until2p7(s5)*. % 76.16/76.33 135306[100:MRR:201.0,135305.0] || -> until2p7(s6)* node4(s5). % 76.16/76.33 135307[101:Spt:135306.0] || -> until2p7(s6)*. % 76.16/76.33 135308[101:MRR:202.0,135307.0] || -> until2p7(s7)* node4(s6). % 76.16/76.33 135309[102:Spt:135308.0] || -> until2p7(s7)*. % 76.16/76.33 135310[102:MRR:203.0,135309.0] || -> until2p7(s8)* node4(s7). % 76.16/76.33 135311[103:Spt:135310.0] || -> until2p7(s8)*. % 76.16/76.33 135312[103:MRR:204.0,135311.0] || -> until2p7(s9)* node4(s8). % 76.16/76.33 135313[104:Spt:135312.0] || -> until2p7(s9)*. % 76.16/76.33 135314[104:MRR:205.0,135313.0] || -> until2p7(s10)* node4(s9). % 76.16/76.33 135315[105:Spt:135314.0] || -> until2p7(s10)*. % 76.16/76.33 135316[105:MRR:206.0,135315.0] || -> until2p7(s11)* node4(s10). % 76.16/76.33 135317[106:Spt:135316.0] || -> until2p7(s11)*. % 76.16/76.33 135318[106:MRR:207.0,135317.0] || -> until2p7(s12)* node4(s11). % 76.16/76.33 135319[107:Spt:135318.0] || -> until2p7(s12)*. % 76.16/76.33 135320[107:MRR:208.0,135319.0] || -> until2p7(s13)* node4(s12). % 76.16/76.33 135321[108:Spt:135320.0] || -> until2p7(s13)*. % 76.16/76.33 135322[108:MRR:209.0,135321.0] || -> until2p7(s14)* node4(s13). % 76.16/76.33 135323[109:Spt:135322.0] || -> until2p7(s14)*. % 76.16/76.33 135324[109:MRR:210.0,135323.0] || -> until2p7(s15)* node4(s14). % 76.16/76.33 135325[110:Spt:135324.0] || -> until2p7(s15)*. % 76.16/76.33 135326[110:MRR:211.0,135325.0] || -> until2p7(s16)* node4(s15). % 76.16/76.33 135327[111:Spt:135326.0] || -> until2p7(s16)*. % 76.16/76.33 135328[111:MRR:212.0,135327.0] || -> until2p7(s17)* node4(s16). % 76.16/76.33 135329[112:Spt:135328.0] || -> until2p7(s17)*. % 76.16/76.33 135330[112:MRR:213.0,135329.0] || -> until2p7(s18)* node4(s17). % 76.16/76.33 135331[113:Spt:135330.0] || -> until2p7(s18)*. % 76.16/76.33 135332[113:MRR:214.0,135331.0] || -> until2p7(s19)* node4(s18). % 76.16/76.33 135333[114:Spt:135332.0] || -> until2p7(s19)*. % 76.16/76.33 135334[114:MRR:215.0,135333.0] || -> until2p7(s20)* node4(s19). % 76.16/76.33 135335[115:Spt:135334.0] || -> until2p7(s20)*. % 76.16/76.33 135336[115:MRR:216.0,135335.0] || -> until2p7(s21)* node4(s20). % 76.16/76.33 135337[116:Spt:135336.0] || -> until2p7(s21)*. % 76.16/76.33 135338[116:MRR:217.0,135337.0] || -> until2p7(s22)* node4(s21). % 76.16/76.33 135339[117:Spt:135338.0] || -> until2p7(s22)*. % 76.16/76.33 135340[117:MRR:218.0,135339.0] || -> until2p7(s23)* node4(s22). % 76.16/76.33 135341[118:Spt:135340.0] || -> until2p7(s23)*. % 76.16/76.33 135342[118:MRR:219.0,135341.0] || -> until2p7(s24)* node4(s23). % 76.16/76.33 135343[119:Spt:135342.0] || -> until2p7(s24)*. % 76.16/76.33 135344[119:MRR:220.0,135343.0] || -> until2p7(s25)* node4(s24). % 76.16/76.33 135345[120:Spt:135344.0] || -> until2p7(s25)*. % 76.16/76.33 135346[120:MRR:221.0,135345.0] || -> until2p7(s26)* node4(s25). % 76.16/76.33 135347[121:Spt:135346.0] || -> until2p7(s26)*. % 76.16/76.33 135348[121:MRR:222.0,135347.0] || -> until2p7(s27)* node4(s26). % 76.16/76.33 135349[122:Spt:135348.0] || -> until2p7(s27)*. % 76.16/76.33 135350[122:MRR:223.0,135349.0] || -> until2p7(s28)* node4(s27). % 76.16/76.33 135351[123:Spt:135350.0] || -> until2p7(s28)*. % 76.16/76.33 135352[123:MRR:224.0,135351.0] || -> until2p7(s29)* node4(s28). % 76.16/76.33 135353[124:Spt:135352.0] || -> until2p7(s29)*. % 76.16/76.33 135354[124:MRR:225.0,135353.0] || -> until2p7(s30)* node4(s29). % 76.16/76.33 135355[125:Spt:135354.0] || -> until2p7(s30)*. % 76.16/76.33 135356[125:MRR:226.0,135355.0] || -> until2p7(s31)* node4(s30). % 76.16/76.33 135357[126:Spt:135356.0] || -> until2p7(s31)*. % 76.16/76.33 135358[126:MRR:227.0,135357.0] || -> until2p7(s32)* node4(s31). % 76.16/76.33 135359[127:Spt:135358.0] || -> until2p7(s32)*. % 76.16/76.33 135360[127:MRR:228.0,135359.0] || -> until2p7(s33)* node4(s32). % 76.16/76.33 135361[128:Spt:135360.0] || -> until2p7(s33)*. % 76.16/76.33 135362[128:MRR:229.0,135361.0] || -> until2p7(s34)* node4(s33). % 76.16/76.33 135363[129:Spt:135362.0] || -> until2p7(s34)*. % 76.16/76.33 135364[129:MRR:230.0,135363.0] || -> until2p7(s35)* node4(s34). % 76.16/76.33 135365[130:Spt:135364.0] || -> until2p7(s35)*. % 76.16/76.33 135366[130:MRR:231.0,135365.0] || -> until2p7(s36)* node4(s35). % 76.16/76.33 135367[131:Spt:135366.0] || -> until2p7(s36)*. % 76.16/76.33 135368[131:MRR:232.0,135367.0] || -> until2p7(s37)* node4(s36). % 76.16/76.33 135369[132:Spt:135368.0] || -> until2p7(s37)*. % 76.16/76.33 135370[132:MRR:235.0,135369.0] || -> until2p7(s38)* node4(s37). % 76.16/76.33 135371[133:Spt:135370.0] || -> until2p7(s38)*. % 76.16/76.33 135372[133:MRR:236.0,135371.0] || -> until2p7(s39)* node4(s38). % 76.16/76.33 135373[134:Spt:135372.0] || -> until2p7(s39)*. % 76.16/76.33 135374[134:MRR:237.0,135373.0] || -> until2p7(s40)* node4(s39). % 76.16/76.33 135375[135:Spt:135374.0] || -> until2p7(s40)*. % 76.16/76.33 135376[135:MRR:238.0,135375.0] || -> until2p7(s41)* node4(s40). % 76.16/76.33 135377[136:Spt:135376.0] || -> until2p7(s41)*. % 76.16/76.33 135378[136:MRR:239.0,135377.0] || -> until2p7(s42)* node4(s41). % 76.16/76.33 135379[137:Spt:135378.0] || -> until2p7(s42)*. % 76.16/76.33 135380[137:MRR:240.0,135379.0] || -> until2p7(s43)* node4(s42). % 76.16/76.33 135381[138:Spt:135380.0] || -> until2p7(s43)*. % 76.16/76.33 135382[138:MRR:241.0,135381.0] || -> until2p7(s44)* node4(s43). % 76.16/76.33 135383[139:Spt:135382.0] || -> until2p7(s44)*. % 76.16/76.33 135384[139:MRR:539.0,135383.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 135385[140:Spt:135384.0] || -> until2p7(s45)*. % 76.16/76.33 135386[140:MRR:544.0,135385.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 135387[141:Spt:135386.0] || -> until2p7(s46)*. % 76.16/76.33 135388[141:MRR:549.0,135387.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 135389[142:Spt:135388.0] || -> until2p7(s47)*. % 76.16/76.33 135390[142:MRR:554.0,135389.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 135391[143:Spt:135390.0] || -> until2p7(s48)*. % 76.16/76.33 135392[143:MRR:559.0,135391.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 135393[144:Spt:135392.0] || -> until2p7(s49)*. % 76.16/76.33 135394[144:MRR:194.0,135393.0] || -> node4(s49)*. % 76.16/76.33 135395[144:MRR:135299.0,135394.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 135396[144:Res:53.1,135395.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 135398[144:MRR:135396.0,78381.0] || -> . % 76.16/76.33 135399[144:Spt:135398.0,135392.0,135393.0] || until2p7(s49)*+ -> . % 76.16/76.33 135400[144:Spt:135398.0,135392.1] || -> node4(s48)*. % 76.16/76.33 135401[144:MRR:78384.0,135400.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 135404[144:Res:53.1,135401.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 135407[144:Res:135404.0,61.1] always3(s48) || -> . % 76.16/76.33 135408[144:SSi:135407.0,78281.0,78387.0,108798.0,135391.0,135400.0] || -> . % 76.16/76.33 135409[143:Spt:135408.0,135390.0,135391.0] || until2p7(s48)*+ -> . % 76.16/76.33 135410[143:Spt:135408.0,135390.1] || -> node4(s47)*. % 76.16/76.33 135412[143:MRR:777.0,135410.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 135427[143:Res:53.1,135412.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 135429[144:Spt:135427.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 135431[144:Res:135429.0,61.1] always3(s47) || -> . % 76.16/76.33 135432[144:SSi:135431.0,78277.0,78280.0,108797.0,135389.0,135410.0] || -> . % 76.16/76.33 135433[144:Spt:135432.0,135427.0,135429.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 135434[144:Spt:135432.0,135427.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 135438[144:Res:135434.0,61.1] always3(s48) || -> . % 76.16/76.33 135439[144:SSi:135438.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.33 135440[142:Spt:135439.0,135388.0,135389.0] || until2p7(s47)*+ -> . % 76.16/76.33 135441[142:Spt:135439.0,135388.1] || -> node4(s46)*. % 76.16/76.33 135443[142:MRR:780.0,135441.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 135453[142:Res:53.1,135443.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 135455[143:Spt:135453.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 135457[143:Res:135455.0,61.1] always3(s46) || -> . % 76.16/76.33 135458[143:SSi:135457.0,78272.0,78276.0,108796.0,135387.0,135441.0] || -> . % 76.16/76.33 135459[143:Spt:135458.0,135453.0,135455.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 135460[143:Spt:135458.0,135453.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 135464[143:Res:135460.0,61.1] always3(s47) || -> . % 76.16/76.33 135465[143:SSi:135464.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.33 135466[141:Spt:135465.0,135386.0,135387.0] || until2p7(s46)*+ -> . % 76.16/76.33 135467[141:Spt:135465.0,135386.1] || -> node4(s45)*. % 76.16/76.33 135469[141:MRR:783.0,135467.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 135472[141:Res:53.1,135469.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 135474[142:Spt:135472.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 135476[142:Res:135474.0,61.1] always3(s45) || -> . % 76.16/76.33 135477[142:SSi:135476.0,78268.0,78271.0,108795.0,135385.0,135467.0] || -> . % 76.16/76.33 135478[142:Spt:135477.0,135472.0,135474.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.33 135479[142:Spt:135477.0,135472.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 135483[142:Res:135479.0,61.1] always3(s46) || -> . % 76.16/76.33 135484[142:SSi:135483.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.33 135485[140:Spt:135484.0,135384.0,135385.0] || until2p7(s45)*+ -> . % 76.16/76.33 135486[140:Spt:135484.0,135384.1] || -> node4(s44)*. % 76.16/76.33 135488[140:MRR:786.0,135486.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.33 135491[140:Res:53.1,135488.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.33 135493[141:Spt:135491.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 135495[141:Res:135493.0,61.1] always3(s44) || -> . % 76.16/76.33 135496[141:SSi:135495.0,78263.0,78267.0,108794.0,135383.0,135486.0] || -> . % 76.16/76.33 135497[141:Spt:135496.0,135491.0,135493.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.33 135498[141:Spt:135496.0,135491.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 135502[141:Res:135498.0,61.1] always3(s45) || -> . % 76.16/76.33 135503[141:SSi:135502.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.33 135504[139:Spt:135503.0,135382.0,135383.0] || until2p7(s44)*+ -> . % 76.16/76.33 135505[139:Spt:135503.0,135382.1] || -> node4(s43)*. % 76.16/76.33 135507[139:MRR:789.0,135505.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.33 135510[139:Res:53.1,135507.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.33 135515[140:Spt:135510.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 135517[140:Res:135515.0,61.1] always3(s43) || -> . % 76.16/76.33 135518[140:SSi:135517.0,78259.0,78262.0,108793.0,135381.0,135505.0] || -> . % 76.16/76.33 135519[140:Spt:135518.0,135510.0,135515.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.33 135520[140:Spt:135518.0,135510.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 135524[140:Res:135520.0,61.1] always3(s44) || -> . % 76.16/76.33 135525[140:SSi:135524.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.33 135526[138:Spt:135525.0,135380.0,135381.0] || until2p7(s43)*+ -> . % 76.16/76.33 135527[138:Spt:135525.0,135380.1] || -> node4(s42)*. % 76.16/76.33 135529[138:MRR:792.0,135527.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.33 135532[138:Res:53.1,135529.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.33 135534[139:Spt:135532.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 135536[139:Res:135534.0,61.1] always3(s42) || -> . % 76.16/76.33 135537[139:SSi:135536.0,78254.0,78258.0,108792.0,135379.0,135527.0] || -> . % 76.16/76.33 135538[139:Spt:135537.0,135532.0,135534.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.33 135539[139:Spt:135537.0,135532.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 135543[139:Res:135539.0,61.1] always3(s43) || -> . % 76.16/76.33 135544[139:SSi:135543.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.33 135545[137:Spt:135544.0,135378.0,135379.0] || until2p7(s42)*+ -> . % 76.16/76.33 135546[137:Spt:135544.0,135378.1] || -> node4(s41)*. % 76.16/76.33 135548[137:MRR:795.0,135546.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.33 135551[137:Res:53.1,135548.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.33 135553[138:Spt:135551.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 135555[138:Res:135553.0,61.1] always3(s41) || -> . % 76.16/76.33 135556[138:SSi:135555.0,78250.0,78253.0,108791.0,135377.0,135546.0] || -> . % 76.16/76.33 135557[138:Spt:135556.0,135551.0,135553.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.33 135558[138:Spt:135556.0,135551.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 135562[138:Res:135558.0,61.1] always3(s42) || -> . % 76.16/76.33 135563[138:SSi:135562.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.33 135564[136:Spt:135563.0,135376.0,135377.0] || until2p7(s41)*+ -> . % 76.16/76.33 135565[136:Spt:135563.0,135376.1] || -> node4(s40)*. % 76.16/76.33 135567[136:MRR:798.0,135565.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.33 135570[136:Res:53.1,135567.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.33 135572[137:Spt:135570.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 135574[137:Res:135572.0,61.1] always3(s40) || -> . % 76.16/76.33 135575[137:SSi:135574.0,78245.0,78249.0,108790.0,135375.0,135565.0] || -> . % 76.16/76.33 135576[137:Spt:135575.0,135570.0,135572.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.33 135577[137:Spt:135575.0,135570.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 135581[137:Res:135577.0,61.1] always3(s41) || -> . % 76.16/76.33 135582[137:SSi:135581.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.33 135583[135:Spt:135582.0,135374.0,135375.0] || until2p7(s40)*+ -> . % 76.16/76.33 135584[135:Spt:135582.0,135374.1] || -> node4(s39)*. % 76.16/76.33 135586[135:MRR:801.0,135584.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.33 135589[135:Res:53.1,135586.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.33 135594[136:Spt:135589.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 135596[136:Res:135594.0,61.1] always3(s39) || -> . % 76.16/76.33 135597[136:SSi:135596.0,78241.0,78244.0,108789.0,135373.0,135584.0] || -> . % 76.16/76.33 135598[136:Spt:135597.0,135589.0,135594.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.33 135599[136:Spt:135597.0,135589.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 135603[136:Res:135599.0,61.1] always3(s40) || -> . % 76.16/76.33 135604[136:SSi:135603.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.33 135605[134:Spt:135604.0,135372.0,135373.0] || until2p7(s39)*+ -> . % 76.16/76.33 135606[134:Spt:135604.0,135372.1] || -> node4(s38)*. % 76.16/76.33 135608[134:MRR:804.0,135606.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.33 135611[134:Res:53.1,135608.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.33 135613[135:Spt:135611.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 135615[135:Res:135613.0,61.1] always3(s38) || -> . % 76.16/76.33 135616[135:SSi:135615.0,78236.0,78240.0,108788.0,135371.0,135606.0] || -> . % 76.16/76.33 135617[135:Spt:135616.0,135611.0,135613.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.33 135618[135:Spt:135616.0,135611.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 135622[135:Res:135618.0,61.1] always3(s39) || -> . % 76.16/76.33 135623[135:SSi:135622.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.33 135624[133:Spt:135623.0,135370.0,135371.0] || until2p7(s38)*+ -> . % 76.16/76.33 135625[133:Spt:135623.0,135370.1] || -> node4(s37)*. % 76.16/76.33 135627[133:MRR:807.0,135625.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.33 135630[133:Res:53.1,135627.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.33 135632[134:Spt:135630.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 135634[134:Res:135632.0,61.1] always3(s37) || -> . % 76.16/76.33 135635[134:SSi:135634.0,78232.0,78235.0,108787.0,135369.0,135625.0] || -> . % 76.16/76.33 135636[134:Spt:135635.0,135630.0,135632.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.33 135637[134:Spt:135635.0,135630.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 135641[134:Res:135637.0,61.1] always3(s38) || -> . % 76.16/76.33 135642[134:SSi:135641.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.33 135643[132:Spt:135642.0,135368.0,135369.0] || until2p7(s37)*+ -> . % 76.16/76.33 135644[132:Spt:135642.0,135368.1] || -> node4(s36)*. % 76.16/76.33 135646[132:MRR:810.0,135644.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.33 135649[132:Res:53.1,135646.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.33 135651[133:Spt:135649.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 135653[133:Res:135651.0,61.1] always3(s36) || -> . % 76.16/76.33 135654[133:SSi:135653.0,78227.0,78231.0,108786.0,135367.0,135644.0] || -> . % 76.16/76.33 135655[133:Spt:135654.0,135649.0,135651.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.33 135656[133:Spt:135654.0,135649.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 135660[133:Res:135656.0,61.1] always3(s37) || -> . % 76.16/76.33 135661[133:SSi:135660.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.33 135662[131:Spt:135661.0,135366.0,135367.0] || until2p7(s36)*+ -> . % 76.16/76.33 135663[131:Spt:135661.0,135366.1] || -> node4(s35)*. % 76.16/76.33 135665[131:MRR:813.0,135663.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.33 135668[131:Res:53.1,135665.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.33 135673[132:Spt:135668.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 135675[132:Res:135673.0,61.1] always3(s35) || -> . % 76.16/76.33 135676[132:SSi:135675.0,78223.0,78226.0,108785.0,135365.0,135663.0] || -> . % 76.16/76.33 135677[132:Spt:135676.0,135668.0,135673.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.33 135678[132:Spt:135676.0,135668.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 135682[132:Res:135678.0,61.1] always3(s36) || -> . % 76.16/76.33 135683[132:SSi:135682.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.33 135684[130:Spt:135683.0,135364.0,135365.0] || until2p7(s35)*+ -> . % 76.16/76.33 135685[130:Spt:135683.0,135364.1] || -> node4(s34)*. % 76.16/76.33 135687[130:MRR:816.0,135685.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.33 135690[130:Res:53.1,135687.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.33 135692[131:Spt:135690.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 135694[131:Res:135692.0,61.1] always3(s34) || -> . % 76.16/76.33 135695[131:SSi:135694.0,78218.0,78222.0,108784.0,135363.0,135685.0] || -> . % 76.16/76.33 135696[131:Spt:135695.0,135690.0,135692.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.33 135697[131:Spt:135695.0,135690.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 135701[131:Res:135697.0,61.1] always3(s35) || -> . % 76.16/76.33 135702[131:SSi:135701.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.33 135703[129:Spt:135702.0,135362.0,135363.0] || until2p7(s34)*+ -> . % 76.16/76.33 135704[129:Spt:135702.0,135362.1] || -> node4(s33)*. % 76.16/76.33 135706[129:MRR:819.0,135704.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.33 135709[129:Res:53.1,135706.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.33 135711[130:Spt:135709.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 135713[130:Res:135711.0,61.1] always3(s33) || -> . % 76.16/76.33 135714[130:SSi:135713.0,78214.0,78217.0,108783.0,135361.0,135704.0] || -> . % 76.16/76.33 135715[130:Spt:135714.0,135709.0,135711.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.33 135716[130:Spt:135714.0,135709.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 135720[130:Res:135716.0,61.1] always3(s34) || -> . % 76.16/76.33 135721[130:SSi:135720.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.33 135722[128:Spt:135721.0,135360.0,135361.0] || until2p7(s33)*+ -> . % 76.16/76.33 135723[128:Spt:135721.0,135360.1] || -> node4(s32)*. % 76.16/76.33 135725[128:MRR:822.0,135723.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.33 135728[128:Res:53.1,135725.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.33 135730[129:Spt:135728.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 135732[129:Res:135730.0,61.1] always3(s32) || -> . % 76.16/76.33 135733[129:SSi:135732.0,78209.0,78213.0,108782.0,135359.0,135723.0] || -> . % 76.16/76.33 135734[129:Spt:135733.0,135728.0,135730.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.33 135735[129:Spt:135733.0,135728.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 135739[129:Res:135735.0,61.1] always3(s33) || -> . % 76.16/76.33 135740[129:SSi:135739.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.33 135741[127:Spt:135740.0,135358.0,135359.0] || until2p7(s32)*+ -> . % 76.16/76.33 135742[127:Spt:135740.0,135358.1] || -> node4(s31)*. % 76.16/76.33 135744[127:MRR:825.0,135742.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.33 135747[127:Res:53.1,135744.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.33 135752[128:Spt:135747.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 135754[128:Res:135752.0,61.1] always3(s31) || -> . % 76.16/76.33 135755[128:SSi:135754.0,78205.0,78208.0,108781.0,135357.0,135742.0] || -> . % 76.16/76.33 135756[128:Spt:135755.0,135747.0,135752.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.33 135757[128:Spt:135755.0,135747.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 135761[128:Res:135757.0,61.1] always3(s32) || -> . % 76.16/76.33 135762[128:SSi:135761.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.33 135763[126:Spt:135762.0,135356.0,135357.0] || until2p7(s31)*+ -> . % 76.16/76.33 135764[126:Spt:135762.0,135356.1] || -> node4(s30)*. % 76.16/76.33 135766[126:MRR:828.0,135764.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.33 135769[126:Res:53.1,135766.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.33 135771[127:Spt:135769.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 135773[127:Res:135771.0,61.1] always3(s30) || -> . % 76.16/76.33 135774[127:SSi:135773.0,78200.0,78204.0,108780.0,135355.0,135764.0] || -> . % 76.16/76.33 135775[127:Spt:135774.0,135769.0,135771.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.33 135776[127:Spt:135774.0,135769.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 135780[127:Res:135776.0,61.1] always3(s31) || -> . % 76.16/76.33 135781[127:SSi:135780.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.33 135782[125:Spt:135781.0,135354.0,135355.0] || until2p7(s30)*+ -> . % 76.16/76.33 135783[125:Spt:135781.0,135354.1] || -> node4(s29)*. % 76.16/76.33 135785[125:MRR:831.0,135783.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.33 135788[125:Res:53.1,135785.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.33 135790[126:Spt:135788.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 135792[126:Res:135790.0,61.1] always3(s29) || -> . % 76.16/76.33 135793[126:SSi:135792.0,78196.0,78199.0,108779.0,135353.0,135783.0] || -> . % 76.16/76.33 135794[126:Spt:135793.0,135788.0,135790.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.33 135795[126:Spt:135793.0,135788.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 135799[126:Res:135795.0,61.1] always3(s30) || -> . % 76.16/76.33 135800[126:SSi:135799.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.33 135801[124:Spt:135800.0,135352.0,135353.0] || until2p7(s29)*+ -> . % 76.16/76.33 135802[124:Spt:135800.0,135352.1] || -> node4(s28)*. % 76.16/76.33 135804[124:MRR:834.0,135802.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.33 135807[124:Res:53.1,135804.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.33 135809[125:Spt:135807.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 135811[125:Res:135809.0,61.1] always3(s28) || -> . % 76.16/76.33 135812[125:SSi:135811.0,78191.0,78195.0,108778.0,135351.0,135802.0] || -> . % 76.16/76.33 135813[125:Spt:135812.0,135807.0,135809.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.33 135814[125:Spt:135812.0,135807.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 135818[125:Res:135814.0,61.1] always3(s29) || -> . % 76.16/76.33 135819[125:SSi:135818.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.33 135820[123:Spt:135819.0,135350.0,135351.0] || until2p7(s28)*+ -> . % 76.16/76.33 135821[123:Spt:135819.0,135350.1] || -> node4(s27)*. % 76.16/76.33 135823[123:MRR:837.0,135821.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.33 135826[123:Res:53.1,135823.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.33 135831[124:Spt:135826.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 135833[124:Res:135831.0,61.1] always3(s27) || -> . % 76.16/76.33 135834[124:SSi:135833.0,78187.0,78190.0,108777.0,135349.0,135821.0] || -> . % 76.16/76.33 135835[124:Spt:135834.0,135826.0,135831.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.33 135836[124:Spt:135834.0,135826.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 135840[124:Res:135836.0,61.1] always3(s28) || -> . % 76.16/76.33 135841[124:SSi:135840.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.33 135842[122:Spt:135841.0,135348.0,135349.0] || until2p7(s27)*+ -> . % 76.16/76.33 135843[122:Spt:135841.0,135348.1] || -> node4(s26)*. % 76.16/76.33 135845[122:MRR:840.0,135843.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.33 135848[122:Res:53.1,135845.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.33 135850[123:Spt:135848.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 135852[123:Res:135850.0,61.1] always3(s26) || -> . % 76.16/76.33 135853[123:SSi:135852.0,78182.0,78186.0,108776.0,135347.0,135843.0] || -> . % 76.16/76.33 135854[123:Spt:135853.0,135848.0,135850.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.33 135855[123:Spt:135853.0,135848.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 135859[123:Res:135855.0,61.1] always3(s27) || -> . % 76.16/76.33 135860[123:SSi:135859.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.33 135861[121:Spt:135860.0,135346.0,135347.0] || until2p7(s26)*+ -> . % 76.16/76.33 135862[121:Spt:135860.0,135346.1] || -> node4(s25)*. % 76.16/76.33 135864[121:MRR:843.0,135862.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.33 135867[121:Res:53.1,135864.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.33 135869[122:Spt:135867.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 135871[122:Res:135869.0,61.1] always3(s25) || -> . % 76.16/76.33 135872[122:SSi:135871.0,78178.0,78181.0,108775.0,135345.0,135862.0] || -> . % 76.16/76.33 135873[122:Spt:135872.0,135867.0,135869.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.33 135874[122:Spt:135872.0,135867.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 135878[122:Res:135874.0,61.1] always3(s26) || -> . % 76.16/76.33 135879[122:SSi:135878.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.33 135880[120:Spt:135879.0,135344.0,135345.0] || until2p7(s25)*+ -> . % 76.16/76.33 135881[120:Spt:135879.0,135344.1] || -> node4(s24)*. % 76.16/76.33 135883[120:MRR:846.0,135881.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.33 135886[120:Res:53.1,135883.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.33 135888[121:Spt:135886.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 135890[121:Res:135888.0,61.1] always3(s24) || -> . % 76.16/76.33 135891[121:SSi:135890.0,78173.0,78177.0,108774.0,135343.0,135881.0] || -> . % 76.16/76.33 135892[121:Spt:135891.0,135886.0,135888.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.33 135893[121:Spt:135891.0,135886.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 135897[121:Res:135893.0,61.1] always3(s25) || -> . % 76.16/76.33 135898[121:SSi:135897.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.33 135899[119:Spt:135898.0,135342.0,135343.0] || until2p7(s24)*+ -> . % 76.16/76.33 135900[119:Spt:135898.0,135342.1] || -> node4(s23)*. % 76.16/76.33 135902[119:MRR:849.0,135900.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.33 135905[119:Res:53.1,135902.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.33 135910[120:Spt:135905.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 135912[120:Res:135910.0,61.1] always3(s23) || -> . % 76.16/76.33 135913[120:SSi:135912.0,78169.0,78172.0,108773.0,135341.0,135900.0] || -> . % 76.16/76.33 135914[120:Spt:135913.0,135905.0,135910.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.33 135915[120:Spt:135913.0,135905.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 135919[120:Res:135915.0,61.1] always3(s24) || -> . % 76.16/76.33 135920[120:SSi:135919.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.33 135921[118:Spt:135920.0,135340.0,135341.0] || until2p7(s23)*+ -> . % 76.16/76.33 135922[118:Spt:135920.0,135340.1] || -> node4(s22)*. % 76.16/76.33 135924[118:MRR:852.0,135922.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.33 135927[118:Res:53.1,135924.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.33 135929[119:Spt:135927.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 135931[119:Res:135929.0,61.1] always3(s22) || -> . % 76.16/76.33 135932[119:SSi:135931.0,78164.0,78168.0,108772.0,135339.0,135922.0] || -> . % 76.16/76.33 135933[119:Spt:135932.0,135927.0,135929.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.33 135934[119:Spt:135932.0,135927.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 135938[119:Res:135934.0,61.1] always3(s23) || -> . % 76.16/76.33 135939[119:SSi:135938.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.33 135940[117:Spt:135939.0,135338.0,135339.0] || until2p7(s22)*+ -> . % 76.16/76.33 135941[117:Spt:135939.0,135338.1] || -> node4(s21)*. % 76.16/76.33 135943[117:MRR:855.0,135941.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.33 135946[117:Res:53.1,135943.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.33 135948[118:Spt:135946.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 135950[118:Res:135948.0,61.1] always3(s21) || -> . % 76.16/76.33 135951[118:SSi:135950.0,78160.0,78163.0,108771.0,135337.0,135941.0] || -> . % 76.16/76.33 135952[118:Spt:135951.0,135946.0,135948.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.33 135953[118:Spt:135951.0,135946.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 135957[118:Res:135953.0,61.1] always3(s22) || -> . % 76.16/76.33 135958[118:SSi:135957.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.33 135959[116:Spt:135958.0,135336.0,135337.0] || until2p7(s21)*+ -> . % 76.16/76.33 135960[116:Spt:135958.0,135336.1] || -> node4(s20)*. % 76.16/76.33 135962[116:MRR:858.0,135960.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.33 135965[116:Res:53.1,135962.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.33 135967[117:Spt:135965.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 135969[117:Res:135967.0,61.1] always3(s20) || -> . % 76.16/76.33 135970[117:SSi:135969.0,78155.0,78159.0,108770.0,135335.0,135960.0] || -> . % 76.16/76.33 135971[117:Spt:135970.0,135965.0,135967.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.33 135972[117:Spt:135970.0,135965.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 135976[117:Res:135972.0,61.1] always3(s21) || -> . % 76.16/76.33 135977[117:SSi:135976.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.33 135978[115:Spt:135977.0,135334.0,135335.0] || until2p7(s20)*+ -> . % 76.16/76.33 135979[115:Spt:135977.0,135334.1] || -> node4(s19)*. % 76.16/76.33 135981[115:MRR:861.0,135979.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.33 135984[115:Res:53.1,135981.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.33 135989[116:Spt:135984.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 135991[116:Res:135989.0,61.1] always3(s19) || -> . % 76.16/76.33 135992[116:SSi:135991.0,78151.0,78154.0,108769.0,135333.0,135979.0] || -> . % 76.16/76.33 135993[116:Spt:135992.0,135984.0,135989.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.33 135994[116:Spt:135992.0,135984.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 135998[116:Res:135994.0,61.1] always3(s20) || -> . % 76.16/76.33 135999[116:SSi:135998.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.33 136000[114:Spt:135999.0,135332.0,135333.0] || until2p7(s19)*+ -> . % 76.16/76.33 136001[114:Spt:135999.0,135332.1] || -> node4(s18)*. % 76.16/76.33 136003[114:MRR:864.0,136001.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.33 136006[114:Res:53.1,136003.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.33 136008[115:Spt:136006.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 136010[115:Res:136008.0,61.1] always3(s18) || -> . % 76.16/76.33 136011[115:SSi:136010.0,78146.0,78150.0,108768.0,135331.0,136001.0] || -> . % 76.16/76.33 136012[115:Spt:136011.0,136006.0,136008.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.33 136013[115:Spt:136011.0,136006.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 136017[115:Res:136013.0,61.1] always3(s19) || -> . % 76.16/76.33 136018[115:SSi:136017.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.33 136019[113:Spt:136018.0,135330.0,135331.0] || until2p7(s18)*+ -> . % 76.16/76.33 136020[113:Spt:136018.0,135330.1] || -> node4(s17)*. % 76.16/76.33 136022[113:MRR:867.0,136020.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.33 136025[113:Res:53.1,136022.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.33 136027[114:Spt:136025.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 136029[114:Res:136027.0,61.1] always3(s17) || -> . % 76.16/76.33 136030[114:SSi:136029.0,78142.0,78145.0,108767.0,135329.0,136020.0] || -> . % 76.16/76.33 136031[114:Spt:136030.0,136025.0,136027.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.33 136032[114:Spt:136030.0,136025.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 136036[114:Res:136032.0,61.1] always3(s18) || -> . % 76.16/76.33 136037[114:SSi:136036.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.33 136038[112:Spt:136037.0,135328.0,135329.0] || until2p7(s17)*+ -> . % 76.16/76.33 136039[112:Spt:136037.0,135328.1] || -> node4(s16)*. % 76.16/76.33 136041[112:MRR:870.0,136039.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.33 136044[112:Res:53.1,136041.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.33 136046[113:Spt:136044.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 136048[113:Res:136046.0,61.1] always3(s16) || -> . % 76.16/76.33 136049[113:SSi:136048.0,78137.0,78141.0,108766.0,135327.0,136039.0] || -> . % 76.16/76.33 136050[113:Spt:136049.0,136044.0,136046.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.33 136051[113:Spt:136049.0,136044.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 136055[113:Res:136051.0,61.1] always3(s17) || -> . % 76.16/76.33 136056[113:SSi:136055.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.33 136057[111:Spt:136056.0,135326.0,135327.0] || until2p7(s16)*+ -> . % 76.16/76.33 136058[111:Spt:136056.0,135326.1] || -> node4(s15)*. % 76.16/76.33 136060[111:MRR:873.0,136058.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.33 136063[111:Res:53.1,136060.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.33 136068[112:Spt:136063.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 136070[112:Res:136068.0,61.1] always3(s15) || -> . % 76.16/76.33 136071[112:SSi:136070.0,78133.0,78136.0,108765.0,135325.0,136058.0] || -> . % 76.16/76.33 136072[112:Spt:136071.0,136063.0,136068.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.33 136073[112:Spt:136071.0,136063.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 136077[112:Res:136073.0,61.1] always3(s16) || -> . % 76.16/76.33 136078[112:SSi:136077.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.33 136079[110:Spt:136078.0,135324.0,135325.0] || until2p7(s15)*+ -> . % 76.16/76.33 136080[110:Spt:136078.0,135324.1] || -> node4(s14)*. % 76.16/76.33 136082[110:MRR:876.0,136080.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.33 136085[110:Res:53.1,136082.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.33 136087[111:Spt:136085.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 136089[111:Res:136087.0,61.1] always3(s14) || -> . % 76.16/76.33 136090[111:SSi:136089.0,78128.0,78132.0,108764.0,135323.0,136080.0] || -> . % 76.16/76.33 136091[111:Spt:136090.0,136085.0,136087.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.33 136092[111:Spt:136090.0,136085.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 136096[111:Res:136092.0,61.1] always3(s15) || -> . % 76.16/76.33 136097[111:SSi:136096.0,78133.0,78136.0,108765.0] || -> . % 76.16/76.33 136098[109:Spt:136097.0,135322.0,135323.0] || until2p7(s14)*+ -> . % 76.16/76.33 136099[109:Spt:136097.0,135322.1] || -> node4(s13)*. % 76.16/76.33 136101[109:MRR:879.0,136099.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.33 136104[109:Res:53.1,136101.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.33 136106[110:Spt:136104.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 136108[110:Res:136106.0,61.1] always3(s13) || -> . % 76.16/76.33 136109[110:SSi:136108.0,78124.0,78127.0,108763.0,135321.0,136099.0] || -> . % 76.16/76.33 136110[110:Spt:136109.0,136104.0,136106.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.33 136111[110:Spt:136109.0,136104.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 136115[110:Res:136111.0,61.1] always3(s14) || -> . % 76.16/76.33 136116[110:SSi:136115.0,78128.0,78132.0,108764.0] || -> . % 76.16/76.33 136117[108:Spt:136116.0,135320.0,135321.0] || until2p7(s13)*+ -> . % 76.16/76.33 136118[108:Spt:136116.0,135320.1] || -> node4(s12)*. % 76.16/76.33 136120[108:MRR:882.0,136118.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.33 136123[108:Res:53.1,136120.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.33 136125[109:Spt:136123.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 136127[109:Res:136125.0,61.1] always3(s12) || -> . % 76.16/76.33 136128[109:SSi:136127.0,78119.0,78123.0,108762.0,135319.0,136118.0] || -> . % 76.16/76.33 136129[109:Spt:136128.0,136123.0,136125.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.33 136130[109:Spt:136128.0,136123.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 136134[109:Res:136130.0,61.1] always3(s13) || -> . % 76.16/76.33 136135[109:SSi:136134.0,78124.0,78127.0,108763.0] || -> . % 76.16/76.33 136136[107:Spt:136135.0,135318.0,135319.0] || until2p7(s12)*+ -> . % 76.16/76.33 136137[107:Spt:136135.0,135318.1] || -> node4(s11)*. % 76.16/76.33 136139[107:MRR:885.0,136137.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.33 136142[107:Res:53.1,136139.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.33 136147[108:Spt:136142.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 136149[108:Res:136147.0,61.1] always3(s11) || -> . % 76.16/76.33 136150[108:SSi:136149.0,78115.0,78118.0,108761.0,135317.0,136137.0] || -> . % 76.16/76.33 136151[108:Spt:136150.0,136142.0,136147.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.33 136152[108:Spt:136150.0,136142.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 136156[108:Res:136152.0,61.1] always3(s12) || -> . % 76.16/76.33 136157[108:SSi:136156.0,78119.0,78123.0,108762.0] || -> . % 76.16/76.33 136158[106:Spt:136157.0,135316.0,135317.0] || until2p7(s11)*+ -> . % 76.16/76.33 136159[106:Spt:136157.0,135316.1] || -> node4(s10)*. % 76.16/76.33 136161[106:MRR:888.0,136159.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.33 136164[106:Res:53.1,136161.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.33 136166[107:Spt:136164.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 136168[107:Res:136166.0,61.1] always3(s10) || -> . % 76.16/76.33 136169[107:SSi:136168.0,78110.0,78114.0,108760.0,135315.0,136159.0] || -> . % 76.16/76.33 136170[107:Spt:136169.0,136164.0,136166.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.33 136171[107:Spt:136169.0,136164.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 136175[107:Res:136171.0,61.1] always3(s11) || -> . % 76.16/76.33 136176[107:SSi:136175.0,78115.0,78118.0,108761.0] || -> . % 76.16/76.33 136177[105:Spt:136176.0,135314.0,135315.0] || until2p7(s10)*+ -> . % 76.16/76.33 136178[105:Spt:136176.0,135314.1] || -> node4(s9)*. % 76.16/76.33 136180[105:MRR:891.0,136178.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.33 136183[105:Res:53.1,136180.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.33 136185[106:Spt:136183.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 136187[106:Res:136185.0,61.1] always3(s9) || -> . % 76.16/76.33 136188[106:SSi:136187.0,78106.0,78109.0,108759.0,135313.0,136178.0] || -> . % 76.16/76.33 136189[106:Spt:136188.0,136183.0,136185.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.33 136190[106:Spt:136188.0,136183.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 136194[106:Res:136190.0,61.1] always3(s10) || -> . % 76.16/76.33 136195[106:SSi:136194.0,78110.0,78114.0,108760.0] || -> . % 76.16/76.33 136196[104:Spt:136195.0,135312.0,135313.0] || until2p7(s9)*+ -> . % 76.16/76.33 136197[104:Spt:136195.0,135312.1] || -> node4(s8)*. % 76.16/76.33 136199[104:MRR:894.0,136197.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.33 136202[104:Res:53.1,136199.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.33 136204[105:Spt:136202.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.33 136206[105:Res:136204.0,61.1] always3(s8) || -> . % 76.16/76.33 136207[105:SSi:136206.0,78101.0,78105.0,108758.0,135311.0,136197.0] || -> . % 76.16/76.33 136208[105:Spt:136207.0,136202.0,136204.0] || m_main_v_state(s8,c_busy)* -> . % 76.16/76.33 136209[105:Spt:136207.0,136202.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 136213[105:Res:136209.0,61.1] always3(s9) || -> . % 76.16/76.33 136214[105:SSi:136213.0,78106.0,78109.0,108759.0] || -> . % 76.16/76.33 136215[103:Spt:136214.0,135310.0,135311.0] || until2p7(s8)*+ -> . % 76.16/76.33 136216[103:Spt:136214.0,135310.1] || -> node4(s7)*. % 76.16/76.33 136218[103:MRR:897.0,136216.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.16/76.33 136221[103:Res:53.1,136218.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.16/76.33 136226[104:Spt:136221.0] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.33 136228[104:Res:136226.0,61.1] always3(s7) || -> . % 76.16/76.33 136229[104:SSi:136228.0,78097.0,78100.0,108757.0,135309.0,136216.0] || -> . % 76.16/76.33 136230[104:Spt:136229.0,136221.0,136226.0] || m_main_v_state(s7,c_busy)* -> . % 76.16/76.33 136231[104:Spt:136229.0,136221.1] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.33 136235[104:Res:136231.0,61.1] always3(s8) || -> . % 76.16/76.33 136236[104:SSi:136235.0,78101.0,78105.0,108758.0] || -> . % 76.16/76.33 136237[102:Spt:136236.0,135308.0,135309.0] || until2p7(s7)*+ -> . % 76.16/76.33 136238[102:Spt:136236.0,135308.1] || -> node4(s6)*. % 76.16/76.33 136240[102:MRR:900.0,136238.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.16/76.33 136243[102:Res:53.1,136240.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.16/76.33 136245[103:Spt:136243.0] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.33 136247[103:Res:136245.0,61.1] always3(s6) || -> . % 76.16/76.33 136248[103:SSi:136247.0,78093.0,78096.0,108756.0,135307.0,136238.0] || -> . % 76.16/76.33 136249[103:Spt:136248.0,136243.0,136245.0] || m_main_v_state(s6,c_busy)* -> . % 76.16/76.33 136250[103:Spt:136248.0,136243.1] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.33 136254[103:Res:136250.0,61.1] always3(s7) || -> . % 76.16/76.33 136255[103:SSi:136254.0,78097.0,78100.0,108757.0] || -> . % 76.16/76.33 136256[101:Spt:136255.0,135306.0,135307.0] || until2p7(s6)*+ -> . % 76.16/76.33 136257[101:Spt:136255.0,135306.1] || -> node4(s5)*. % 76.16/76.33 136259[101:MRR:903.0,136257.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.16/76.33 136262[101:Res:53.1,136259.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.16/76.33 136264[102:Spt:136262.0] || -> m_main_v_state(s5,c_busy)*. % 76.16/76.33 136266[102:Res:136264.0,61.1] always3(s5) || -> . % 76.16/76.33 136267[102:SSi:136266.0,78089.0,78092.0,108755.0,135305.0,136257.0] || -> . % 76.16/76.33 136268[102:Spt:136267.0,136262.0,136264.0] || m_main_v_state(s5,c_busy)* -> . % 76.16/76.33 136269[102:Spt:136267.0,136262.1] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.33 136273[102:Res:136269.0,61.1] always3(s6) || -> . % 76.16/76.33 136274[102:SSi:136273.0,78093.0,78096.0,108756.0] || -> . % 76.16/76.33 136275[100:Spt:136274.0,135304.0,135305.0] || until2p7(s5)*+ -> . % 76.16/76.33 136276[100:Spt:136274.0,135304.1] || -> node4(s4)*. % 76.16/76.33 136278[100:MRR:906.0,136276.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.16/76.33 136281[100:Res:53.1,136278.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.16/76.33 136283[100:MRR:136281.0,135294.0] || -> m_main_v_state(s5,c_busy)*. % 76.16/76.33 136285[100:Res:136283.0,61.1] always3(s5) || -> . % 76.16/76.33 136286[100:SSi:136285.0,78089.0,78092.0,108755.0] || -> . % 76.16/76.33 136287[98:Spt:136286.0,135128.0,135131.0] || trans(s49,s4)*+ -> . % 76.16/76.33 136288[98:Spt:136286.0,135128.1] || -> node2(s49,s3)*. % 76.16/76.33 136290[98:MRR:135130.1,136287.0] xuntil6(s49) || -> until2p7(s3)*. % 76.16/76.33 136291[98:Res:136288.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s3,c_busy)*. % 76.16/76.33 136448[98:SoR:136291.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s3,c_busy)*. % 76.16/76.33 136450[98:SoR:136448.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s3,c_busy)* xuntil6(s49). % 76.16/76.33 136451[98:SSi:136450.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s3,c_busy)* xuntil6(s49). % 76.16/76.33 136452[99:Spt:136451.1] || -> m_main_v_state(s3,c_busy)*. % 76.16/76.33 136454[99:Res:136452.0,61.1] always3(s3) || -> . % 76.16/76.33 136455[99:SSi:136454.0,78081.0,78084.0,108753.0] || -> . % 76.16/76.33 136456[99:Spt:136455.0,136451.1,136452.0] || m_main_v_state(s3,c_busy)*+ -> . % 76.16/76.33 136457[99:Spt:136455.0,136451.0,136451.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 136460[99:MRR:136448.2,136456.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 136461[99:Res:53.1,136457.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 136463[99:MRR:136461.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 136464[99:MRR:136290.0,136463.0] || -> until2p7(s3)*. % 76.16/76.33 136465[99:MRR:199.0,136464.0] || -> until2p7(s4)* node4(s3). % 76.16/76.33 136466[100:Spt:136465.0] || -> until2p7(s4)*. % 76.16/76.33 136467[100:MRR:200.0,136466.0] || -> until2p7(s5)* node4(s4). % 76.16/76.33 136468[101:Spt:136467.0] || -> until2p7(s5)*. % 76.16/76.33 136469[101:MRR:201.0,136468.0] || -> until2p7(s6)* node4(s5). % 76.16/76.33 136470[102:Spt:136469.0] || -> until2p7(s6)*. % 76.16/76.33 136471[102:MRR:202.0,136470.0] || -> until2p7(s7)* node4(s6). % 76.16/76.33 136472[103:Spt:136471.0] || -> until2p7(s7)*. % 76.16/76.33 136473[103:MRR:203.0,136472.0] || -> until2p7(s8)* node4(s7). % 76.16/76.33 136474[104:Spt:136473.0] || -> until2p7(s8)*. % 76.16/76.33 136475[104:MRR:204.0,136474.0] || -> until2p7(s9)* node4(s8). % 76.16/76.33 136476[105:Spt:136475.0] || -> until2p7(s9)*. % 76.16/76.33 136477[105:MRR:205.0,136476.0] || -> until2p7(s10)* node4(s9). % 76.16/76.33 136478[106:Spt:136477.0] || -> until2p7(s10)*. % 76.16/76.33 136479[106:MRR:206.0,136478.0] || -> until2p7(s11)* node4(s10). % 76.16/76.33 136480[107:Spt:136479.0] || -> until2p7(s11)*. % 76.16/76.33 136481[107:MRR:207.0,136480.0] || -> until2p7(s12)* node4(s11). % 76.16/76.33 136482[108:Spt:136481.0] || -> until2p7(s12)*. % 76.16/76.33 136483[108:MRR:208.0,136482.0] || -> until2p7(s13)* node4(s12). % 76.16/76.33 136484[109:Spt:136483.0] || -> until2p7(s13)*. % 76.16/76.33 136485[109:MRR:209.0,136484.0] || -> until2p7(s14)* node4(s13). % 76.16/76.33 136486[110:Spt:136485.0] || -> until2p7(s14)*. % 76.16/76.33 136487[110:MRR:210.0,136486.0] || -> until2p7(s15)* node4(s14). % 76.16/76.33 136488[111:Spt:136487.0] || -> until2p7(s15)*. % 76.16/76.33 136489[111:MRR:211.0,136488.0] || -> until2p7(s16)* node4(s15). % 76.16/76.33 136490[112:Spt:136489.0] || -> until2p7(s16)*. % 76.16/76.33 136491[112:MRR:212.0,136490.0] || -> until2p7(s17)* node4(s16). % 76.16/76.33 136492[113:Spt:136491.0] || -> until2p7(s17)*. % 76.16/76.33 136493[113:MRR:213.0,136492.0] || -> until2p7(s18)* node4(s17). % 76.16/76.33 136494[114:Spt:136493.0] || -> until2p7(s18)*. % 76.16/76.33 136495[114:MRR:214.0,136494.0] || -> until2p7(s19)* node4(s18). % 76.16/76.33 136496[115:Spt:136495.0] || -> until2p7(s19)*. % 76.16/76.33 136497[115:MRR:215.0,136496.0] || -> until2p7(s20)* node4(s19). % 76.16/76.33 136498[116:Spt:136497.0] || -> until2p7(s20)*. % 76.16/76.33 136499[116:MRR:216.0,136498.0] || -> until2p7(s21)* node4(s20). % 76.16/76.33 136500[117:Spt:136499.0] || -> until2p7(s21)*. % 76.16/76.33 136501[117:MRR:217.0,136500.0] || -> until2p7(s22)* node4(s21). % 76.16/76.33 136502[118:Spt:136501.0] || -> until2p7(s22)*. % 76.16/76.33 136503[118:MRR:218.0,136502.0] || -> until2p7(s23)* node4(s22). % 76.16/76.33 136504[119:Spt:136503.0] || -> until2p7(s23)*. % 76.16/76.33 136505[119:MRR:219.0,136504.0] || -> until2p7(s24)* node4(s23). % 76.16/76.33 136506[120:Spt:136505.0] || -> until2p7(s24)*. % 76.16/76.33 136507[120:MRR:220.0,136506.0] || -> until2p7(s25)* node4(s24). % 76.16/76.33 136508[121:Spt:136507.0] || -> until2p7(s25)*. % 76.16/76.33 136509[121:MRR:221.0,136508.0] || -> until2p7(s26)* node4(s25). % 76.16/76.33 136510[122:Spt:136509.0] || -> until2p7(s26)*. % 76.16/76.33 136511[122:MRR:222.0,136510.0] || -> until2p7(s27)* node4(s26). % 76.16/76.33 136512[123:Spt:136511.0] || -> until2p7(s27)*. % 76.16/76.33 136513[123:MRR:223.0,136512.0] || -> until2p7(s28)* node4(s27). % 76.16/76.33 136514[124:Spt:136513.0] || -> until2p7(s28)*. % 76.16/76.33 136515[124:MRR:224.0,136514.0] || -> until2p7(s29)* node4(s28). % 76.16/76.33 136516[125:Spt:136515.0] || -> until2p7(s29)*. % 76.16/76.33 136517[125:MRR:225.0,136516.0] || -> until2p7(s30)* node4(s29). % 76.16/76.33 136518[126:Spt:136517.0] || -> until2p7(s30)*. % 76.16/76.33 136519[126:MRR:226.0,136518.0] || -> until2p7(s31)* node4(s30). % 76.16/76.33 136520[127:Spt:136519.0] || -> until2p7(s31)*. % 76.16/76.33 136521[127:MRR:227.0,136520.0] || -> until2p7(s32)* node4(s31). % 76.16/76.33 136522[128:Spt:136521.0] || -> until2p7(s32)*. % 76.16/76.33 136523[128:MRR:228.0,136522.0] || -> until2p7(s33)* node4(s32). % 76.16/76.33 136524[129:Spt:136523.0] || -> until2p7(s33)*. % 76.16/76.33 136525[129:MRR:229.0,136524.0] || -> until2p7(s34)* node4(s33). % 76.16/76.33 136526[130:Spt:136525.0] || -> until2p7(s34)*. % 76.16/76.33 136527[130:MRR:230.0,136526.0] || -> until2p7(s35)* node4(s34). % 76.16/76.33 136528[131:Spt:136527.0] || -> until2p7(s35)*. % 76.16/76.33 136529[131:MRR:231.0,136528.0] || -> until2p7(s36)* node4(s35). % 76.16/76.33 136530[132:Spt:136529.0] || -> until2p7(s36)*. % 76.16/76.33 136531[132:MRR:232.0,136530.0] || -> until2p7(s37)* node4(s36). % 76.16/76.33 136532[133:Spt:136531.0] || -> until2p7(s37)*. % 76.16/76.33 136533[133:MRR:235.0,136532.0] || -> until2p7(s38)* node4(s37). % 76.16/76.33 136534[134:Spt:136533.0] || -> until2p7(s38)*. % 76.16/76.33 136535[134:MRR:236.0,136534.0] || -> until2p7(s39)* node4(s38). % 76.16/76.33 136536[135:Spt:136535.0] || -> until2p7(s39)*. % 76.16/76.33 136537[135:MRR:237.0,136536.0] || -> until2p7(s40)* node4(s39). % 76.16/76.33 136538[136:Spt:136537.0] || -> until2p7(s40)*. % 76.16/76.33 136539[136:MRR:238.0,136538.0] || -> until2p7(s41)* node4(s40). % 76.16/76.33 136540[137:Spt:136539.0] || -> until2p7(s41)*. % 76.16/76.33 136541[137:MRR:239.0,136540.0] || -> until2p7(s42)* node4(s41). % 76.16/76.33 136542[138:Spt:136541.0] || -> until2p7(s42)*. % 76.16/76.33 136543[138:MRR:240.0,136542.0] || -> until2p7(s43)* node4(s42). % 76.16/76.33 136544[139:Spt:136543.0] || -> until2p7(s43)*. % 76.16/76.33 136545[139:MRR:241.0,136544.0] || -> until2p7(s44)* node4(s43). % 76.16/76.33 136546[140:Spt:136545.0] || -> until2p7(s44)*. % 76.16/76.33 136547[140:MRR:539.0,136546.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 136548[141:Spt:136547.0] || -> until2p7(s45)*. % 76.16/76.33 136549[141:MRR:544.0,136548.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 136550[142:Spt:136549.0] || -> until2p7(s46)*. % 76.16/76.33 136551[142:MRR:549.0,136550.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 136552[143:Spt:136551.0] || -> until2p7(s47)*. % 76.16/76.33 136553[143:MRR:554.0,136552.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 136554[144:Spt:136553.0] || -> until2p7(s48)*. % 76.16/76.33 136555[144:MRR:559.0,136554.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 136556[145:Spt:136555.0] || -> until2p7(s49)*. % 76.16/76.33 136557[145:MRR:194.0,136556.0] || -> node4(s49)*. % 76.16/76.33 136558[145:MRR:136460.0,136557.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 136562[145:Res:53.1,136558.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 136564[145:MRR:136562.0,78381.0] || -> . % 76.16/76.33 136565[145:Spt:136564.0,136555.0,136556.0] || until2p7(s49)*+ -> . % 76.16/76.33 136566[145:Spt:136564.0,136555.1] || -> node4(s48)*. % 76.16/76.33 136567[145:MRR:78384.0,136566.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 136570[145:Res:53.1,136567.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 136573[145:Res:136570.0,61.1] always3(s48) || -> . % 76.16/76.33 136574[145:SSi:136573.0,78281.0,78387.0,108798.0,136554.0,136566.0] || -> . % 76.16/76.33 136575[144:Spt:136574.0,136553.0,136554.0] || until2p7(s48)*+ -> . % 76.16/76.33 136576[144:Spt:136574.0,136553.1] || -> node4(s47)*. % 76.16/76.33 136578[144:MRR:777.0,136576.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 136592[144:Res:53.1,136578.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 136594[145:Spt:136592.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 136596[145:Res:136594.0,61.1] always3(s47) || -> . % 76.16/76.33 136597[145:SSi:136596.0,78277.0,78280.0,108797.0,136552.0,136576.0] || -> . % 76.16/76.33 136598[145:Spt:136597.0,136592.0,136594.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 136599[145:Spt:136597.0,136592.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 136603[145:Res:136599.0,61.1] always3(s48) || -> . % 76.16/76.33 136604[145:SSi:136603.0,78281.0,78387.0,108798.0] || -> . % 76.16/76.33 136605[143:Spt:136604.0,136551.0,136552.0] || until2p7(s47)*+ -> . % 76.16/76.33 136606[143:Spt:136604.0,136551.1] || -> node4(s46)*. % 76.16/76.33 136608[143:MRR:780.0,136606.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 136615[143:Res:53.1,136608.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 136620[144:Spt:136615.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 136622[144:Res:136620.0,61.1] always3(s46) || -> . % 76.16/76.33 136623[144:SSi:136622.0,78272.0,78276.0,108796.0,136550.0,136606.0] || -> . % 76.16/76.33 136624[144:Spt:136623.0,136615.0,136620.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 136625[144:Spt:136623.0,136615.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 136629[144:Res:136625.0,61.1] always3(s47) || -> . % 76.16/76.33 136630[144:SSi:136629.0,78277.0,78280.0,108797.0] || -> . % 76.16/76.33 136631[142:Spt:136630.0,136549.0,136550.0] || until2p7(s46)*+ -> . % 76.16/76.33 136632[142:Spt:136630.0,136549.1] || -> node4(s45)*. % 76.16/76.33 136634[142:MRR:783.0,136632.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 136637[142:Res:53.1,136634.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 136639[143:Spt:136637.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 136641[143:Res:136639.0,61.1] always3(s45) || -> . % 76.16/76.33 136642[143:SSi:136641.0,78268.0,78271.0,108795.0,136548.0,136632.0] || -> . % 76.16/76.33 136643[143:Spt:136642.0,136637.0,136639.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.33 136644[143:Spt:136642.0,136637.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 136648[143:Res:136644.0,61.1] always3(s46) || -> . % 76.16/76.33 136649[143:SSi:136648.0,78272.0,78276.0,108796.0] || -> . % 76.16/76.33 136650[141:Spt:136649.0,136547.0,136548.0] || until2p7(s45)*+ -> . % 76.16/76.33 136651[141:Spt:136649.0,136547.1] || -> node4(s44)*. % 76.16/76.33 136653[141:MRR:786.0,136651.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.33 136656[141:Res:53.1,136653.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.33 136658[142:Spt:136656.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 136660[142:Res:136658.0,61.1] always3(s44) || -> . % 76.16/76.33 136661[142:SSi:136660.0,78263.0,78267.0,108794.0,136546.0,136651.0] || -> . % 76.16/76.33 136662[142:Spt:136661.0,136656.0,136658.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.33 136663[142:Spt:136661.0,136656.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 136667[142:Res:136663.0,61.1] always3(s45) || -> . % 76.16/76.33 136668[142:SSi:136667.0,78268.0,78271.0,108795.0] || -> . % 76.16/76.33 136669[140:Spt:136668.0,136545.0,136546.0] || until2p7(s44)*+ -> . % 76.16/76.33 136670[140:Spt:136668.0,136545.1] || -> node4(s43)*. % 76.16/76.33 136672[140:MRR:789.0,136670.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.33 136675[140:Res:53.1,136672.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.33 136677[141:Spt:136675.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 136679[141:Res:136677.0,61.1] always3(s43) || -> . % 76.16/76.33 136680[141:SSi:136679.0,78259.0,78262.0,108793.0,136544.0,136670.0] || -> . % 76.16/76.33 136681[141:Spt:136680.0,136675.0,136677.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.33 136682[141:Spt:136680.0,136675.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 136686[141:Res:136682.0,61.1] always3(s44) || -> . % 76.16/76.33 136687[141:SSi:136686.0,78263.0,78267.0,108794.0] || -> . % 76.16/76.33 136688[139:Spt:136687.0,136543.0,136544.0] || until2p7(s43)*+ -> . % 76.16/76.33 136689[139:Spt:136687.0,136543.1] || -> node4(s42)*. % 76.16/76.33 136691[139:MRR:792.0,136689.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.33 136694[139:Res:53.1,136691.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.33 136699[140:Spt:136694.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 136701[140:Res:136699.0,61.1] always3(s42) || -> . % 76.16/76.33 136702[140:SSi:136701.0,78254.0,78258.0,108792.0,136542.0,136689.0] || -> . % 76.16/76.33 136703[140:Spt:136702.0,136694.0,136699.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.33 136704[140:Spt:136702.0,136694.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 136708[140:Res:136704.0,61.1] always3(s43) || -> . % 76.16/76.33 136709[140:SSi:136708.0,78259.0,78262.0,108793.0] || -> . % 76.16/76.33 136710[138:Spt:136709.0,136541.0,136542.0] || until2p7(s42)*+ -> . % 76.16/76.33 136711[138:Spt:136709.0,136541.1] || -> node4(s41)*. % 76.16/76.33 136713[138:MRR:795.0,136711.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.33 136716[138:Res:53.1,136713.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.33 136718[139:Spt:136716.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 136720[139:Res:136718.0,61.1] always3(s41) || -> . % 76.16/76.33 136721[139:SSi:136720.0,78250.0,78253.0,108791.0,136540.0,136711.0] || -> . % 76.16/76.33 136722[139:Spt:136721.0,136716.0,136718.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.33 136723[139:Spt:136721.0,136716.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 136727[139:Res:136723.0,61.1] always3(s42) || -> . % 76.16/76.33 136728[139:SSi:136727.0,78254.0,78258.0,108792.0] || -> . % 76.16/76.33 136729[137:Spt:136728.0,136539.0,136540.0] || until2p7(s41)*+ -> . % 76.16/76.33 136730[137:Spt:136728.0,136539.1] || -> node4(s40)*. % 76.16/76.33 136732[137:MRR:798.0,136730.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.33 136735[137:Res:53.1,136732.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.33 136737[138:Spt:136735.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 136739[138:Res:136737.0,61.1] always3(s40) || -> . % 76.16/76.33 136740[138:SSi:136739.0,78245.0,78249.0,108790.0,136538.0,136730.0] || -> . % 76.16/76.33 136741[138:Spt:136740.0,136735.0,136737.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.33 136742[138:Spt:136740.0,136735.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 136746[138:Res:136742.0,61.1] always3(s41) || -> . % 76.16/76.33 136747[138:SSi:136746.0,78250.0,78253.0,108791.0] || -> . % 76.16/76.33 136748[136:Spt:136747.0,136537.0,136538.0] || until2p7(s40)*+ -> . % 76.16/76.33 136749[136:Spt:136747.0,136537.1] || -> node4(s39)*. % 76.16/76.33 136751[136:MRR:801.0,136749.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.33 136754[136:Res:53.1,136751.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.33 136756[137:Spt:136754.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 136758[137:Res:136756.0,61.1] always3(s39) || -> . % 76.16/76.33 136759[137:SSi:136758.0,78241.0,78244.0,108789.0,136536.0,136749.0] || -> . % 76.16/76.33 136760[137:Spt:136759.0,136754.0,136756.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.33 136761[137:Spt:136759.0,136754.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 136765[137:Res:136761.0,61.1] always3(s40) || -> . % 76.16/76.33 136766[137:SSi:136765.0,78245.0,78249.0,108790.0] || -> . % 76.16/76.33 136767[135:Spt:136766.0,136535.0,136536.0] || until2p7(s39)*+ -> . % 76.16/76.33 136768[135:Spt:136766.0,136535.1] || -> node4(s38)*. % 76.16/76.33 136770[135:MRR:804.0,136768.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.33 136773[135:Res:53.1,136770.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.33 136778[136:Spt:136773.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 136780[136:Res:136778.0,61.1] always3(s38) || -> . % 76.16/76.33 136781[136:SSi:136780.0,78236.0,78240.0,108788.0,136534.0,136768.0] || -> . % 76.16/76.33 136782[136:Spt:136781.0,136773.0,136778.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.33 136783[136:Spt:136781.0,136773.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 136787[136:Res:136783.0,61.1] always3(s39) || -> . % 76.16/76.33 136788[136:SSi:136787.0,78241.0,78244.0,108789.0] || -> . % 76.16/76.33 136789[134:Spt:136788.0,136533.0,136534.0] || until2p7(s38)*+ -> . % 76.16/76.33 136790[134:Spt:136788.0,136533.1] || -> node4(s37)*. % 76.16/76.33 136792[134:MRR:807.0,136790.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.33 136795[134:Res:53.1,136792.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.33 136797[135:Spt:136795.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 136799[135:Res:136797.0,61.1] always3(s37) || -> . % 76.16/76.33 136800[135:SSi:136799.0,78232.0,78235.0,108787.0,136532.0,136790.0] || -> . % 76.16/76.33 136801[135:Spt:136800.0,136795.0,136797.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.33 136802[135:Spt:136800.0,136795.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 136806[135:Res:136802.0,61.1] always3(s38) || -> . % 76.16/76.33 136807[135:SSi:136806.0,78236.0,78240.0,108788.0] || -> . % 76.16/76.33 136808[133:Spt:136807.0,136531.0,136532.0] || until2p7(s37)*+ -> . % 76.16/76.33 136809[133:Spt:136807.0,136531.1] || -> node4(s36)*. % 76.16/76.33 136811[133:MRR:810.0,136809.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.33 136814[133:Res:53.1,136811.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.33 136816[134:Spt:136814.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 136818[134:Res:136816.0,61.1] always3(s36) || -> . % 76.16/76.33 136819[134:SSi:136818.0,78227.0,78231.0,108786.0,136530.0,136809.0] || -> . % 76.16/76.33 136820[134:Spt:136819.0,136814.0,136816.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.33 136821[134:Spt:136819.0,136814.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.33 136825[134:Res:136821.0,61.1] always3(s37) || -> . % 76.16/76.33 136826[134:SSi:136825.0,78232.0,78235.0,108787.0] || -> . % 76.16/76.33 136827[132:Spt:136826.0,136529.0,136530.0] || until2p7(s36)*+ -> . % 76.16/76.33 136828[132:Spt:136826.0,136529.1] || -> node4(s35)*. % 76.16/76.33 136830[132:MRR:813.0,136828.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.33 136833[132:Res:53.1,136830.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.33 136835[133:Spt:136833.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 136837[133:Res:136835.0,61.1] always3(s35) || -> . % 76.16/76.33 136838[133:SSi:136837.0,78223.0,78226.0,108785.0,136528.0,136828.0] || -> . % 76.16/76.33 136839[133:Spt:136838.0,136833.0,136835.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.33 136840[133:Spt:136838.0,136833.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.33 136844[133:Res:136840.0,61.1] always3(s36) || -> . % 76.16/76.33 136845[133:SSi:136844.0,78227.0,78231.0,108786.0] || -> . % 76.16/76.33 136846[131:Spt:136845.0,136527.0,136528.0] || until2p7(s35)*+ -> . % 76.16/76.33 136847[131:Spt:136845.0,136527.1] || -> node4(s34)*. % 76.16/76.33 136849[131:MRR:816.0,136847.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.33 136852[131:Res:53.1,136849.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.33 136857[132:Spt:136852.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 136859[132:Res:136857.0,61.1] always3(s34) || -> . % 76.16/76.33 136860[132:SSi:136859.0,78218.0,78222.0,108784.0,136526.0,136847.0] || -> . % 76.16/76.33 136861[132:Spt:136860.0,136852.0,136857.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.33 136862[132:Spt:136860.0,136852.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.33 136866[132:Res:136862.0,61.1] always3(s35) || -> . % 76.16/76.33 136867[132:SSi:136866.0,78223.0,78226.0,108785.0] || -> . % 76.16/76.33 136868[130:Spt:136867.0,136525.0,136526.0] || until2p7(s34)*+ -> . % 76.16/76.33 136869[130:Spt:136867.0,136525.1] || -> node4(s33)*. % 76.16/76.33 136871[130:MRR:819.0,136869.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.33 136874[130:Res:53.1,136871.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.33 136876[131:Spt:136874.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 136878[131:Res:136876.0,61.1] always3(s33) || -> . % 76.16/76.33 136879[131:SSi:136878.0,78214.0,78217.0,108783.0,136524.0,136869.0] || -> . % 76.16/76.33 136880[131:Spt:136879.0,136874.0,136876.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.33 136881[131:Spt:136879.0,136874.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.33 136885[131:Res:136881.0,61.1] always3(s34) || -> . % 76.16/76.33 136886[131:SSi:136885.0,78218.0,78222.0,108784.0] || -> . % 76.16/76.33 136887[129:Spt:136886.0,136523.0,136524.0] || until2p7(s33)*+ -> . % 76.16/76.33 136888[129:Spt:136886.0,136523.1] || -> node4(s32)*. % 76.16/76.33 136890[129:MRR:822.0,136888.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.33 136893[129:Res:53.1,136890.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.33 136895[130:Spt:136893.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 136897[130:Res:136895.0,61.1] always3(s32) || -> . % 76.16/76.33 136898[130:SSi:136897.0,78209.0,78213.0,108782.0,136522.0,136888.0] || -> . % 76.16/76.33 136899[130:Spt:136898.0,136893.0,136895.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.33 136900[130:Spt:136898.0,136893.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.33 136904[130:Res:136900.0,61.1] always3(s33) || -> . % 76.16/76.33 136905[130:SSi:136904.0,78214.0,78217.0,108783.0] || -> . % 76.16/76.33 136906[128:Spt:136905.0,136521.0,136522.0] || until2p7(s32)*+ -> . % 76.16/76.33 136907[128:Spt:136905.0,136521.1] || -> node4(s31)*. % 76.16/76.33 136909[128:MRR:825.0,136907.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.33 136912[128:Res:53.1,136909.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.33 136914[129:Spt:136912.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 136916[129:Res:136914.0,61.1] always3(s31) || -> . % 76.16/76.33 136917[129:SSi:136916.0,78205.0,78208.0,108781.0,136520.0,136907.0] || -> . % 76.16/76.33 136918[129:Spt:136917.0,136912.0,136914.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.33 136919[129:Spt:136917.0,136912.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.33 136923[129:Res:136919.0,61.1] always3(s32) || -> . % 76.16/76.33 136924[129:SSi:136923.0,78209.0,78213.0,108782.0] || -> . % 76.16/76.33 136925[127:Spt:136924.0,136519.0,136520.0] || until2p7(s31)*+ -> . % 76.16/76.33 136926[127:Spt:136924.0,136519.1] || -> node4(s30)*. % 76.16/76.33 136928[127:MRR:828.0,136926.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.33 136931[127:Res:53.1,136928.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.33 136936[128:Spt:136931.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 136938[128:Res:136936.0,61.1] always3(s30) || -> . % 76.16/76.33 136939[128:SSi:136938.0,78200.0,78204.0,108780.0,136518.0,136926.0] || -> . % 76.16/76.33 136940[128:Spt:136939.0,136931.0,136936.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.33 136941[128:Spt:136939.0,136931.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.33 136945[128:Res:136941.0,61.1] always3(s31) || -> . % 76.16/76.33 136946[128:SSi:136945.0,78205.0,78208.0,108781.0] || -> . % 76.16/76.33 136947[126:Spt:136946.0,136517.0,136518.0] || until2p7(s30)*+ -> . % 76.16/76.33 136948[126:Spt:136946.0,136517.1] || -> node4(s29)*. % 76.16/76.33 136950[126:MRR:831.0,136948.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.33 136953[126:Res:53.1,136950.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.33 136955[127:Spt:136953.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 136957[127:Res:136955.0,61.1] always3(s29) || -> . % 76.16/76.33 136958[127:SSi:136957.0,78196.0,78199.0,108779.0,136516.0,136948.0] || -> . % 76.16/76.33 136959[127:Spt:136958.0,136953.0,136955.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.33 136960[127:Spt:136958.0,136953.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.33 136964[127:Res:136960.0,61.1] always3(s30) || -> . % 76.16/76.33 136965[127:SSi:136964.0,78200.0,78204.0,108780.0] || -> . % 76.16/76.33 136966[125:Spt:136965.0,136515.0,136516.0] || until2p7(s29)*+ -> . % 76.16/76.33 136967[125:Spt:136965.0,136515.1] || -> node4(s28)*. % 76.16/76.33 136969[125:MRR:834.0,136967.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.33 136972[125:Res:53.1,136969.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.33 136974[126:Spt:136972.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 136976[126:Res:136974.0,61.1] always3(s28) || -> . % 76.16/76.33 136977[126:SSi:136976.0,78191.0,78195.0,108778.0,136514.0,136967.0] || -> . % 76.16/76.33 136978[126:Spt:136977.0,136972.0,136974.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.33 136979[126:Spt:136977.0,136972.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.33 136983[126:Res:136979.0,61.1] always3(s29) || -> . % 76.16/76.33 136984[126:SSi:136983.0,78196.0,78199.0,108779.0] || -> . % 76.16/76.33 136985[124:Spt:136984.0,136513.0,136514.0] || until2p7(s28)*+ -> . % 76.16/76.33 136986[124:Spt:136984.0,136513.1] || -> node4(s27)*. % 76.16/76.33 136988[124:MRR:837.0,136986.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.33 136991[124:Res:53.1,136988.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.33 136993[125:Spt:136991.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 136995[125:Res:136993.0,61.1] always3(s27) || -> . % 76.16/76.33 136996[125:SSi:136995.0,78187.0,78190.0,108777.0,136512.0,136986.0] || -> . % 76.16/76.33 136997[125:Spt:136996.0,136991.0,136993.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.33 136998[125:Spt:136996.0,136991.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.33 137002[125:Res:136998.0,61.1] always3(s28) || -> . % 76.16/76.33 137003[125:SSi:137002.0,78191.0,78195.0,108778.0] || -> . % 76.16/76.33 137004[123:Spt:137003.0,136511.0,136512.0] || until2p7(s27)*+ -> . % 76.16/76.33 137005[123:Spt:137003.0,136511.1] || -> node4(s26)*. % 76.16/76.33 137007[123:MRR:840.0,137005.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.33 137010[123:Res:53.1,137007.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.33 137015[124:Spt:137010.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 137017[124:Res:137015.0,61.1] always3(s26) || -> . % 76.16/76.33 137018[124:SSi:137017.0,78182.0,78186.0,108776.0,136510.0,137005.0] || -> . % 76.16/76.33 137019[124:Spt:137018.0,137010.0,137015.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.33 137020[124:Spt:137018.0,137010.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.33 137024[124:Res:137020.0,61.1] always3(s27) || -> . % 76.16/76.33 137025[124:SSi:137024.0,78187.0,78190.0,108777.0] || -> . % 76.16/76.33 137026[122:Spt:137025.0,136509.0,136510.0] || until2p7(s26)*+ -> . % 76.16/76.33 137027[122:Spt:137025.0,136509.1] || -> node4(s25)*. % 76.16/76.33 137029[122:MRR:843.0,137027.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.33 137032[122:Res:53.1,137029.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.33 137034[123:Spt:137032.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 137036[123:Res:137034.0,61.1] always3(s25) || -> . % 76.16/76.33 137037[123:SSi:137036.0,78178.0,78181.0,108775.0,136508.0,137027.0] || -> . % 76.16/76.33 137038[123:Spt:137037.0,137032.0,137034.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.33 137039[123:Spt:137037.0,137032.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.33 137043[123:Res:137039.0,61.1] always3(s26) || -> . % 76.16/76.33 137044[123:SSi:137043.0,78182.0,78186.0,108776.0] || -> . % 76.16/76.33 137045[121:Spt:137044.0,136507.0,136508.0] || until2p7(s25)*+ -> . % 76.16/76.33 137046[121:Spt:137044.0,136507.1] || -> node4(s24)*. % 76.16/76.33 137048[121:MRR:846.0,137046.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.33 137051[121:Res:53.1,137048.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.33 137053[122:Spt:137051.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 137055[122:Res:137053.0,61.1] always3(s24) || -> . % 76.16/76.33 137056[122:SSi:137055.0,78173.0,78177.0,108774.0,136506.0,137046.0] || -> . % 76.16/76.33 137057[122:Spt:137056.0,137051.0,137053.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.33 137058[122:Spt:137056.0,137051.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.33 137062[122:Res:137058.0,61.1] always3(s25) || -> . % 76.16/76.33 137063[122:SSi:137062.0,78178.0,78181.0,108775.0] || -> . % 76.16/76.33 137064[120:Spt:137063.0,136505.0,136506.0] || until2p7(s24)*+ -> . % 76.16/76.33 137065[120:Spt:137063.0,136505.1] || -> node4(s23)*. % 76.16/76.33 137067[120:MRR:849.0,137065.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.33 137070[120:Res:53.1,137067.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.33 137072[121:Spt:137070.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 137074[121:Res:137072.0,61.1] always3(s23) || -> . % 76.16/76.33 137075[121:SSi:137074.0,78169.0,78172.0,108773.0,136504.0,137065.0] || -> . % 76.16/76.33 137076[121:Spt:137075.0,137070.0,137072.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.33 137077[121:Spt:137075.0,137070.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.33 137081[121:Res:137077.0,61.1] always3(s24) || -> . % 76.16/76.33 137082[121:SSi:137081.0,78173.0,78177.0,108774.0] || -> . % 76.16/76.33 137083[119:Spt:137082.0,136503.0,136504.0] || until2p7(s23)*+ -> . % 76.16/76.33 137084[119:Spt:137082.0,136503.1] || -> node4(s22)*. % 76.16/76.33 137086[119:MRR:852.0,137084.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.33 137089[119:Res:53.1,137086.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.33 137094[120:Spt:137089.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 137096[120:Res:137094.0,61.1] always3(s22) || -> . % 76.16/76.33 137097[120:SSi:137096.0,78164.0,78168.0,108772.0,136502.0,137084.0] || -> . % 76.16/76.33 137098[120:Spt:137097.0,137089.0,137094.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.33 137099[120:Spt:137097.0,137089.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.33 137103[120:Res:137099.0,61.1] always3(s23) || -> . % 76.16/76.33 137104[120:SSi:137103.0,78169.0,78172.0,108773.0] || -> . % 76.16/76.33 137105[118:Spt:137104.0,136501.0,136502.0] || until2p7(s22)*+ -> . % 76.16/76.33 137106[118:Spt:137104.0,136501.1] || -> node4(s21)*. % 76.16/76.33 137108[118:MRR:855.0,137106.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.33 137111[118:Res:53.1,137108.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.33 137113[119:Spt:137111.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 137115[119:Res:137113.0,61.1] always3(s21) || -> . % 76.16/76.33 137116[119:SSi:137115.0,78160.0,78163.0,108771.0,136500.0,137106.0] || -> . % 76.16/76.33 137117[119:Spt:137116.0,137111.0,137113.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.33 137118[119:Spt:137116.0,137111.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.33 137122[119:Res:137118.0,61.1] always3(s22) || -> . % 76.16/76.33 137123[119:SSi:137122.0,78164.0,78168.0,108772.0] || -> . % 76.16/76.33 137124[117:Spt:137123.0,136499.0,136500.0] || until2p7(s21)*+ -> . % 76.16/76.33 137125[117:Spt:137123.0,136499.1] || -> node4(s20)*. % 76.16/76.33 137127[117:MRR:858.0,137125.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.33 137130[117:Res:53.1,137127.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.33 137132[118:Spt:137130.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 137134[118:Res:137132.0,61.1] always3(s20) || -> . % 76.16/76.33 137135[118:SSi:137134.0,78155.0,78159.0,108770.0,136498.0,137125.0] || -> . % 76.16/76.33 137136[118:Spt:137135.0,137130.0,137132.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.33 137137[118:Spt:137135.0,137130.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.33 137141[118:Res:137137.0,61.1] always3(s21) || -> . % 76.16/76.33 137142[118:SSi:137141.0,78160.0,78163.0,108771.0] || -> . % 76.16/76.33 137143[116:Spt:137142.0,136497.0,136498.0] || until2p7(s20)*+ -> . % 76.16/76.33 137144[116:Spt:137142.0,136497.1] || -> node4(s19)*. % 76.16/76.33 137146[116:MRR:861.0,137144.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.33 137149[116:Res:53.1,137146.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.33 137151[117:Spt:137149.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 137153[117:Res:137151.0,61.1] always3(s19) || -> . % 76.16/76.33 137154[117:SSi:137153.0,78151.0,78154.0,108769.0,136496.0,137144.0] || -> . % 76.16/76.33 137155[117:Spt:137154.0,137149.0,137151.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.33 137156[117:Spt:137154.0,137149.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.33 137160[117:Res:137156.0,61.1] always3(s20) || -> . % 76.16/76.33 137161[117:SSi:137160.0,78155.0,78159.0,108770.0] || -> . % 76.16/76.33 137162[115:Spt:137161.0,136495.0,136496.0] || until2p7(s19)*+ -> . % 76.16/76.33 137163[115:Spt:137161.0,136495.1] || -> node4(s18)*. % 76.16/76.33 137165[115:MRR:864.0,137163.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.33 137168[115:Res:53.1,137165.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.33 137173[116:Spt:137168.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 137175[116:Res:137173.0,61.1] always3(s18) || -> . % 76.16/76.33 137176[116:SSi:137175.0,78146.0,78150.0,108768.0,136494.0,137163.0] || -> . % 76.16/76.33 137177[116:Spt:137176.0,137168.0,137173.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.33 137178[116:Spt:137176.0,137168.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.33 137182[116:Res:137178.0,61.1] always3(s19) || -> . % 76.16/76.33 137183[116:SSi:137182.0,78151.0,78154.0,108769.0] || -> . % 76.16/76.33 137184[114:Spt:137183.0,136493.0,136494.0] || until2p7(s18)*+ -> . % 76.16/76.33 137185[114:Spt:137183.0,136493.1] || -> node4(s17)*. % 76.16/76.33 137187[114:MRR:867.0,137185.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.33 137190[114:Res:53.1,137187.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.33 137192[115:Spt:137190.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 137194[115:Res:137192.0,61.1] always3(s17) || -> . % 76.16/76.33 137195[115:SSi:137194.0,78142.0,78145.0,108767.0,136492.0,137185.0] || -> . % 76.16/76.33 137196[115:Spt:137195.0,137190.0,137192.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.33 137197[115:Spt:137195.0,137190.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.33 137201[115:Res:137197.0,61.1] always3(s18) || -> . % 76.16/76.33 137202[115:SSi:137201.0,78146.0,78150.0,108768.0] || -> . % 76.16/76.33 137203[113:Spt:137202.0,136491.0,136492.0] || until2p7(s17)*+ -> . % 76.16/76.33 137204[113:Spt:137202.0,136491.1] || -> node4(s16)*. % 76.16/76.33 137206[113:MRR:870.0,137204.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.33 137209[113:Res:53.1,137206.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.33 137211[114:Spt:137209.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 137213[114:Res:137211.0,61.1] always3(s16) || -> . % 76.16/76.33 137214[114:SSi:137213.0,78137.0,78141.0,108766.0,136490.0,137204.0] || -> . % 76.16/76.33 137215[114:Spt:137214.0,137209.0,137211.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.33 137216[114:Spt:137214.0,137209.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.33 137220[114:Res:137216.0,61.1] always3(s17) || -> . % 76.16/76.33 137221[114:SSi:137220.0,78142.0,78145.0,108767.0] || -> . % 76.16/76.33 137222[112:Spt:137221.0,136489.0,136490.0] || until2p7(s16)*+ -> . % 76.16/76.33 137223[112:Spt:137221.0,136489.1] || -> node4(s15)*. % 76.16/76.33 137225[112:MRR:873.0,137223.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.33 137228[112:Res:53.1,137225.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.33 137230[113:Spt:137228.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 137232[113:Res:137230.0,61.1] always3(s15) || -> . % 76.16/76.33 137233[113:SSi:137232.0,78133.0,78136.0,108765.0,136488.0,137223.0] || -> . % 76.16/76.33 137234[113:Spt:137233.0,137228.0,137230.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.33 137235[113:Spt:137233.0,137228.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.33 137239[113:Res:137235.0,61.1] always3(s16) || -> . % 76.16/76.33 137240[113:SSi:137239.0,78137.0,78141.0,108766.0] || -> . % 76.16/76.33 137241[111:Spt:137240.0,136487.0,136488.0] || until2p7(s15)*+ -> . % 76.16/76.33 137242[111:Spt:137240.0,136487.1] || -> node4(s14)*. % 76.16/76.33 137244[111:MRR:876.0,137242.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.33 137247[111:Res:53.1,137244.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.33 137252[112:Spt:137247.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 137254[112:Res:137252.0,61.1] always3(s14) || -> . % 76.16/76.33 137255[112:SSi:137254.0,78128.0,78132.0,108764.0,136486.0,137242.0] || -> . % 76.16/76.33 137256[112:Spt:137255.0,137247.0,137252.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.33 137257[112:Spt:137255.0,137247.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.33 137261[112:Res:137257.0,61.1] always3(s15) || -> . % 76.16/76.33 137262[112:SSi:137261.0,78133.0,78136.0,108765.0] || -> . % 76.16/76.33 137263[110:Spt:137262.0,136485.0,136486.0] || until2p7(s14)*+ -> . % 76.16/76.33 137264[110:Spt:137262.0,136485.1] || -> node4(s13)*. % 76.16/76.33 137266[110:MRR:879.0,137264.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.33 137269[110:Res:53.1,137266.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.33 137271[111:Spt:137269.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 137273[111:Res:137271.0,61.1] always3(s13) || -> . % 76.16/76.33 137274[111:SSi:137273.0,78124.0,78127.0,108763.0,136484.0,137264.0] || -> . % 76.16/76.33 137275[111:Spt:137274.0,137269.0,137271.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.33 137276[111:Spt:137274.0,137269.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.33 137280[111:Res:137276.0,61.1] always3(s14) || -> . % 76.16/76.33 137281[111:SSi:137280.0,78128.0,78132.0,108764.0] || -> . % 76.16/76.33 137282[109:Spt:137281.0,136483.0,136484.0] || until2p7(s13)*+ -> . % 76.16/76.33 137283[109:Spt:137281.0,136483.1] || -> node4(s12)*. % 76.16/76.33 137285[109:MRR:882.0,137283.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.33 137288[109:Res:53.1,137285.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.33 137290[110:Spt:137288.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 137292[110:Res:137290.0,61.1] always3(s12) || -> . % 76.16/76.33 137293[110:SSi:137292.0,78119.0,78123.0,108762.0,136482.0,137283.0] || -> . % 76.16/76.33 137294[110:Spt:137293.0,137288.0,137290.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.33 137295[110:Spt:137293.0,137288.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.33 137299[110:Res:137295.0,61.1] always3(s13) || -> . % 76.16/76.33 137300[110:SSi:137299.0,78124.0,78127.0,108763.0] || -> . % 76.16/76.33 137301[108:Spt:137300.0,136481.0,136482.0] || until2p7(s12)*+ -> . % 76.16/76.33 137302[108:Spt:137300.0,136481.1] || -> node4(s11)*. % 76.16/76.33 137304[108:MRR:885.0,137302.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.33 137307[108:Res:53.1,137304.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.33 137309[109:Spt:137307.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 137311[109:Res:137309.0,61.1] always3(s11) || -> . % 76.16/76.33 137312[109:SSi:137311.0,78115.0,78118.0,108761.0,136480.0,137302.0] || -> . % 76.16/76.33 137313[109:Spt:137312.0,137307.0,137309.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.33 137314[109:Spt:137312.0,137307.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.33 137318[109:Res:137314.0,61.1] always3(s12) || -> . % 76.16/76.33 137319[109:SSi:137318.0,78119.0,78123.0,108762.0] || -> . % 76.16/76.33 137320[107:Spt:137319.0,136479.0,136480.0] || until2p7(s11)*+ -> . % 76.16/76.33 137321[107:Spt:137319.0,136479.1] || -> node4(s10)*. % 76.16/76.33 137323[107:MRR:888.0,137321.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.33 137326[107:Res:53.1,137323.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.33 137331[108:Spt:137326.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 137333[108:Res:137331.0,61.1] always3(s10) || -> . % 76.16/76.33 137334[108:SSi:137333.0,78110.0,78114.0,108760.0,136478.0,137321.0] || -> . % 76.16/76.33 137335[108:Spt:137334.0,137326.0,137331.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.33 137336[108:Spt:137334.0,137326.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.33 137340[108:Res:137336.0,61.1] always3(s11) || -> . % 76.16/76.33 137341[108:SSi:137340.0,78115.0,78118.0,108761.0] || -> . % 76.16/76.33 137342[106:Spt:137341.0,136477.0,136478.0] || until2p7(s10)*+ -> . % 76.16/76.33 137343[106:Spt:137341.0,136477.1] || -> node4(s9)*. % 76.16/76.33 137345[106:MRR:891.0,137343.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.33 137348[106:Res:53.1,137345.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.33 137350[107:Spt:137348.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 137352[107:Res:137350.0,61.1] always3(s9) || -> . % 76.16/76.33 137353[107:SSi:137352.0,78106.0,78109.0,108759.0,136476.0,137343.0] || -> . % 76.16/76.33 137354[107:Spt:137353.0,137348.0,137350.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.33 137355[107:Spt:137353.0,137348.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.33 137359[107:Res:137355.0,61.1] always3(s10) || -> . % 76.16/76.33 137360[107:SSi:137359.0,78110.0,78114.0,108760.0] || -> . % 76.16/76.33 137361[105:Spt:137360.0,136475.0,136476.0] || until2p7(s9)*+ -> . % 76.16/76.33 137362[105:Spt:137360.0,136475.1] || -> node4(s8)*. % 76.16/76.33 137364[105:MRR:894.0,137362.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.33 137367[105:Res:53.1,137364.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.33 137369[106:Spt:137367.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.33 137371[106:Res:137369.0,61.1] always3(s8) || -> . % 76.16/76.33 137372[106:SSi:137371.0,78101.0,78105.0,108758.0,136474.0,137362.0] || -> . % 76.16/76.33 137373[106:Spt:137372.0,137367.0,137369.0] || m_main_v_state(s8,c_busy)* -> . % 76.16/76.33 137374[106:Spt:137372.0,137367.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.33 137378[106:Res:137374.0,61.1] always3(s9) || -> . % 76.16/76.33 137379[106:SSi:137378.0,78106.0,78109.0,108759.0] || -> . % 76.16/76.33 137380[104:Spt:137379.0,136473.0,136474.0] || until2p7(s8)*+ -> . % 76.16/76.33 137381[104:Spt:137379.0,136473.1] || -> node4(s7)*. % 76.16/76.33 137383[104:MRR:897.0,137381.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.16/76.33 137386[104:Res:53.1,137383.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.16/76.33 137388[105:Spt:137386.0] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.33 137390[105:Res:137388.0,61.1] always3(s7) || -> . % 76.16/76.33 137391[105:SSi:137390.0,78097.0,78100.0,108757.0,136472.0,137381.0] || -> . % 76.16/76.33 137392[105:Spt:137391.0,137386.0,137388.0] || m_main_v_state(s7,c_busy)* -> . % 76.16/76.33 137393[105:Spt:137391.0,137386.1] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.33 137397[105:Res:137393.0,61.1] always3(s8) || -> . % 76.16/76.33 137398[105:SSi:137397.0,78101.0,78105.0,108758.0] || -> . % 76.16/76.33 137399[103:Spt:137398.0,136471.0,136472.0] || until2p7(s7)*+ -> . % 76.16/76.33 137400[103:Spt:137398.0,136471.1] || -> node4(s6)*. % 76.16/76.33 137402[103:MRR:900.0,137400.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.16/76.33 137405[103:Res:53.1,137402.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.16/76.33 137410[104:Spt:137405.0] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.33 137412[104:Res:137410.0,61.1] always3(s6) || -> . % 76.16/76.33 137413[104:SSi:137412.0,78093.0,78096.0,108756.0,136470.0,137400.0] || -> . % 76.16/76.33 137414[104:Spt:137413.0,137405.0,137410.0] || m_main_v_state(s6,c_busy)* -> . % 76.16/76.33 137415[104:Spt:137413.0,137405.1] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.33 137419[104:Res:137415.0,61.1] always3(s7) || -> . % 76.16/76.33 137420[104:SSi:137419.0,78097.0,78100.0,108757.0] || -> . % 76.16/76.33 137421[102:Spt:137420.0,136469.0,136470.0] || until2p7(s6)*+ -> . % 76.16/76.33 137422[102:Spt:137420.0,136469.1] || -> node4(s5)*. % 76.16/76.33 137424[102:MRR:903.0,137422.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.16/76.33 137427[102:Res:53.1,137424.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.16/76.33 137429[103:Spt:137427.0] || -> m_main_v_state(s5,c_busy)*. % 76.16/76.33 137431[103:Res:137429.0,61.1] always3(s5) || -> . % 76.16/76.33 137432[103:SSi:137431.0,78089.0,78092.0,108755.0,136468.0,137422.0] || -> . % 76.16/76.33 137433[103:Spt:137432.0,137427.0,137429.0] || m_main_v_state(s5,c_busy)* -> . % 76.16/76.33 137434[103:Spt:137432.0,137427.1] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.33 137438[103:Res:137434.0,61.1] always3(s6) || -> . % 76.16/76.33 137439[103:SSi:137438.0,78093.0,78096.0,108756.0] || -> . % 76.16/76.33 137440[101:Spt:137439.0,136467.0,136468.0] || until2p7(s5)*+ -> . % 76.16/76.33 137441[101:Spt:137439.0,136467.1] || -> node4(s4)*. % 76.16/76.33 137443[101:MRR:906.0,137441.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.16/76.33 137446[101:Res:53.1,137443.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.16/76.33 137448[102:Spt:137446.0] || -> m_main_v_state(s4,c_busy)*. % 76.16/76.33 137450[102:Res:137448.0,61.1] always3(s4) || -> . % 76.16/76.33 137451[102:SSi:137450.0,78085.0,78088.0,108754.0,136466.0,137441.0] || -> . % 76.16/76.33 137452[102:Spt:137451.0,137446.0,137448.0] || m_main_v_state(s4,c_busy)* -> . % 76.16/76.33 137453[102:Spt:137451.0,137446.1] || -> m_main_v_state(s5,c_busy)*. % 76.16/76.33 137457[102:Res:137453.0,61.1] always3(s5) || -> . % 76.16/76.33 137458[102:SSi:137457.0,78089.0,78092.0,108755.0] || -> . % 76.16/76.33 137459[100:Spt:137458.0,136465.0,136466.0] || until2p7(s4)*+ -> . % 76.16/76.33 137460[100:Spt:137458.0,136465.1] || -> node4(s3)*. % 76.16/76.33 137462[100:MRR:909.0,137460.0] || m_main_v_state(s3,c_ready)*+ -> m_main_v_state(s4,c_busy). % 76.16/76.33 137465[100:Res:53.1,137462.0] || -> m_main_v_state(s3,c_busy)* m_main_v_state(s4,c_busy). % 76.16/76.33 137467[100:MRR:137465.0,136456.0] || -> m_main_v_state(s4,c_busy)*. % 76.16/76.33 137469[100:Res:137467.0,61.1] always3(s4) || -> . % 76.16/76.33 137470[100:SSi:137469.0,78085.0,78088.0,108754.0] || -> . % 76.16/76.33 137471[52:Spt:137470.0,108498.46,108753.0] || always3(s3)*+ -> . % 76.16/76.33 137472[52:Spt:137470.0,108498.0,108498.1,108498.2,108498.3,108498.4,108498.5,108498.6,108498.7,108498.8,108498.9,108498.10,108498.11,108498.12,108498.13,108498.14,108498.15,108498.16,108498.17,108498.18,108498.19,108498.20,108498.21,108498.22,108498.23,108498.24,108498.25,108498.26,108498.27,108498.28,108498.29,108498.30,108498.31,108498.32,108498.33,108498.34,108498.35,108498.36,108498.37,108498.38,108498.39,108498.40,108498.41,108498.42,108498.43,108498.44,108498.45] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) trans(s49,s4)*. % 76.16/76.33 137474[52:Res:137472.45,69.2] xuntil6(s49) last(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.33 137475[52:Res:137472.45,62.1] always3(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* always3(s4). % 76.16/76.33 137476[52:Res:137472.45,60.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.33 137477[52:SSi:137475.0,50.0,78285.0,78388.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* always3(s4). % 76.16/76.33 137478[52:SSi:137474.1,50.0,78285.0,78388.0] xuntil6(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.33 137726[53:Spt:137477.45] || -> always3(s4)*. % 76.16/76.33 137727[53:MRR:522.0,137726.0] || -> always3(s5)*. % 76.16/76.33 137728[53:MRR:519.0,137727.0] || -> always3(s6)*. % 76.16/76.33 137729[53:MRR:516.0,137728.0] || -> always3(s7)*. % 76.16/76.33 137730[53:MRR:513.0,137729.0] || -> always3(s8)*. % 76.16/76.33 137731[53:MRR:510.0,137730.0] || -> always3(s9)*. % 76.16/76.33 137732[53:MRR:507.0,137731.0] || -> always3(s10)*. % 76.16/76.33 137733[53:MRR:504.0,137732.0] || -> always3(s11)*. % 76.16/76.33 137734[53:MRR:501.0,137733.0] || -> always3(s12)*. % 76.16/76.33 137735[53:MRR:498.0,137734.0] || -> always3(s13)*. % 76.16/76.33 137736[53:MRR:495.0,137735.0] || -> always3(s14)*. % 76.16/76.33 137737[53:MRR:492.0,137736.0] || -> always3(s15)*. % 76.16/76.33 137738[53:MRR:489.0,137737.0] || -> always3(s16)*. % 76.16/76.33 137739[53:MRR:486.0,137738.0] || -> always3(s17)*. % 76.16/76.33 137740[53:MRR:483.0,137739.0] || -> always3(s18)*. % 76.16/76.33 137741[53:MRR:480.0,137740.0] || -> always3(s19)*. % 76.16/76.33 137742[53:MRR:477.0,137741.0] || -> always3(s20)*. % 76.16/76.33 137743[53:MRR:474.0,137742.0] || -> always3(s21)*. % 76.16/76.33 137744[53:MRR:471.0,137743.0] || -> always3(s22)*. % 76.16/76.33 137745[53:MRR:468.0,137744.0] || -> always3(s23)*. % 76.16/76.33 137746[53:MRR:465.0,137745.0] || -> always3(s24)*. % 76.16/76.33 137747[53:MRR:462.0,137746.0] || -> always3(s25)*. % 76.16/76.33 137748[53:MRR:459.0,137747.0] || -> always3(s26)*. % 76.16/76.33 137749[53:MRR:456.0,137748.0] || -> always3(s27)*. % 76.16/76.33 137750[53:MRR:453.0,137749.0] || -> always3(s28)*. % 76.16/76.33 137751[53:MRR:450.0,137750.0] || -> always3(s29)*. % 76.16/76.33 137752[53:MRR:427.0,137751.0] || -> always3(s30)*. % 76.16/76.33 137753[53:MRR:425.0,137752.0] || -> always3(s31)*. % 76.16/76.33 137754[53:MRR:423.0,137753.0] || -> always3(s32)*. % 76.16/76.33 137755[53:MRR:421.0,137754.0] || -> always3(s33)*. % 76.16/76.33 137756[53:MRR:370.0,137755.0] || -> always3(s34)*. % 76.16/76.33 137757[53:MRR:368.0,137756.0] || -> always3(s35)*. % 76.16/76.33 137758[53:MRR:366.0,137757.0] || -> always3(s36)*. % 76.16/76.33 137759[53:MRR:364.0,137758.0] || -> always3(s37)*. % 76.16/76.33 137760[53:MRR:313.0,137759.0] || -> always3(s38)*. % 76.16/76.33 137761[53:MRR:311.0,137760.0] || -> always3(s39)*. % 76.16/76.33 137762[53:MRR:309.0,137761.0] || -> always3(s40)*. % 76.16/76.33 137763[53:MRR:307.0,137762.0] || -> always3(s41)*. % 76.16/76.33 137764[53:MRR:306.0,137763.0] || -> always3(s42)*. % 76.16/76.33 137765[53:MRR:305.0,137764.0] || -> always3(s43)*. % 76.16/76.33 137766[53:MRR:304.0,137765.0] || -> always3(s44)*. % 76.16/76.33 137767[53:MRR:303.0,137766.0] || -> always3(s45)*. % 76.16/76.33 137768[53:MRR:302.0,137767.0] || -> always3(s46)*. % 76.16/76.33 137769[53:MRR:301.0,137768.0] || -> always3(s47)*. % 76.16/76.33 137770[53:MRR:300.0,137769.0] || -> always3(s48)*. % 76.16/76.33 137771[54:Spt:137476.0] || -> trans(s49,s49)*. % 76.16/76.33 137772[54:Res:137771.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s49)*. % 76.16/76.33 137774[54:Res:137771.0,60.0] || -> node2(s49,s49)*. % 76.16/76.33 137775[54:SSi:137772.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s49)*. % 76.16/76.33 137776[54:Res:137774.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> m_main_v_state(s49,c_busy). % 76.16/76.33 137777[54:MRR:137776.1,137776.2,53.1,78381.0] m_main_v_request(s49) || -> . % 76.16/76.33 137779[54:SoR:137777.0,64.1] node4(s49) || -> . % 76.16/76.33 137780[54:MRR:194.1,137779.0] until2p7(s49) || -> . % 76.16/76.33 137783[54:MRR:137775.1,137780.0] xuntil6(s49) || -> . % 76.16/76.33 137784[54:SoR:137779.0,66.2] until5(s49) || -> xuntil6(s49)*. % 76.16/76.33 137785[54:SSi:137784.0,50.0,78285.0,78388.0] || -> xuntil6(s49)*. % 76.16/76.33 137786[54:MRR:137785.0,137783.0] || -> . % 76.16/76.33 137787[54:Spt:137786.0,137476.0,137771.0] || trans(s49,s49)*+ -> . % 76.16/76.33 137788[54:Spt:137786.0,137476.1,137476.2,137476.3,137476.4,137476.5,137476.6,137476.7,137476.8,137476.9,137476.10,137476.11,137476.12,137476.13,137476.14,137476.15,137476.16,137476.17,137476.18,137476.19,137476.20,137476.21,137476.22,137476.23,137476.24,137476.25,137476.26,137476.27,137476.28,137476.29,137476.30,137476.31,137476.32,137476.33,137476.34,137476.35,137476.36,137476.37,137476.38,137476.39,137476.40,137476.41,137476.42,137476.43,137476.44,137476.45] || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.33 137790[54:MRR:137478.1,137787.0] xuntil6(s49) || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.33 137791[55:Spt:137788.0] || -> trans(s49,s48)*. % 76.16/76.33 137792[55:Res:137791.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s48)*. % 76.16/76.33 137794[55:Res:137791.0,60.0] || -> node2(s49,s48)*. % 76.16/76.33 137795[55:SSi:137792.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s48)*. % 76.16/76.33 137796[55:Res:137794.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 137799[55:SoR:137796.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 137801[55:SoR:137799.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)* xuntil6(s49). % 76.16/76.33 137802[55:SSi:137801.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s48,c_busy)* xuntil6(s49). % 76.16/76.33 137803[56:Spt:137802.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 137805[56:Res:137803.0,61.1] always3(s48) || -> . % 76.16/76.33 137806[56:SSi:137805.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.33 137807[56:Spt:137806.0,137802.1,137803.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.16/76.33 137808[56:Spt:137806.0,137802.0,137802.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 137812[56:MRR:137799.2,137807.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 137813[56:Res:53.1,137808.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 137815[56:MRR:137813.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 137816[56:MRR:137795.0,137815.0] || -> until2p7(s48)*. % 76.16/76.33 137817[56:MRR:559.0,137816.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 137818[57:Spt:137817.0] || -> until2p7(s49)*. % 76.16/76.33 137819[57:MRR:194.0,137818.0] || -> node4(s49)*. % 76.16/76.33 137820[57:MRR:137812.0,137819.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 137821[57:Res:53.1,137820.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 137823[57:MRR:137821.0,78381.0] || -> . % 76.16/76.33 137824[57:Spt:137823.0,137817.0,137818.0] || until2p7(s49)*+ -> . % 76.16/76.33 137825[57:Spt:137823.0,137817.1] || -> node4(s48)*. % 76.16/76.33 137826[57:MRR:78384.0,137825.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 137829[57:Res:53.1,137826.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 137831[57:MRR:137829.0,137807.0] || -> . % 76.16/76.33 137832[55:Spt:137831.0,137788.0,137791.0] || trans(s49,s48)*+ -> . % 76.16/76.33 137833[55:Spt:137831.0,137788.1,137788.2,137788.3,137788.4,137788.5,137788.6,137788.7,137788.8,137788.9,137788.10,137788.11,137788.12,137788.13,137788.14,137788.15,137788.16,137788.17,137788.18,137788.19,137788.20,137788.21,137788.22,137788.23,137788.24,137788.25,137788.26,137788.27,137788.28,137788.29,137788.30,137788.31,137788.32,137788.33,137788.34,137788.35,137788.36,137788.37,137788.38,137788.39,137788.40,137788.41,137788.42,137788.43,137788.44] || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.33 137835[55:MRR:137790.1,137832.0] xuntil6(s49) || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.33 137836[56:Spt:137833.0] || -> trans(s49,s47)*. % 76.16/76.33 137837[56:Res:137836.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s47)*. % 76.16/76.33 137839[56:Res:137836.0,60.0] || -> node2(s49,s47)*. % 76.16/76.33 137840[56:SSi:137837.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s47)*. % 76.16/76.33 137841[56:Res:137839.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 137853[56:SoR:137841.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 137855[56:SoR:137853.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 76.16/76.33 137856[56:SSi:137855.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 76.16/76.33 137857[57:Spt:137856.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 137859[57:Res:137857.0,61.1] always3(s47) || -> . % 76.16/76.33 137860[57:SSi:137859.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.33 137861[57:Spt:137860.0,137856.1,137857.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.16/76.33 137862[57:Spt:137860.0,137856.0,137856.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 137866[57:MRR:137853.2,137861.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 137867[57:Res:53.1,137862.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 137869[57:MRR:137867.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 137870[57:MRR:137840.0,137869.0] || -> until2p7(s47)*. % 76.16/76.33 137871[57:MRR:554.0,137870.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 137872[58:Spt:137871.0] || -> until2p7(s48)*. % 76.16/76.33 137873[58:MRR:559.0,137872.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 137874[59:Spt:137873.0] || -> until2p7(s49)*. % 76.16/76.33 137875[59:MRR:194.0,137874.0] || -> node4(s49)*. % 76.16/76.33 137876[59:MRR:137866.0,137875.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 137877[59:Res:53.1,137876.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 137879[59:MRR:137877.0,78381.0] || -> . % 76.16/76.33 137880[59:Spt:137879.0,137873.0,137874.0] || until2p7(s49)*+ -> . % 76.16/76.33 137881[59:Spt:137879.0,137873.1] || -> node4(s48)*. % 76.16/76.33 137882[59:MRR:78384.0,137881.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 137885[59:Res:53.1,137882.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 137888[59:Res:137885.0,61.1] always3(s48) || -> . % 76.16/76.33 137889[59:SSi:137888.0,78281.0,78387.0,137770.0,137872.0,137881.0] || -> . % 76.16/76.33 137890[58:Spt:137889.0,137871.0,137872.0] || until2p7(s48)*+ -> . % 76.16/76.33 137891[58:Spt:137889.0,137871.1] || -> node4(s47)*. % 76.16/76.33 137893[58:MRR:777.0,137891.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 137908[58:Res:53.1,137893.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 137910[58:MRR:137908.0,137861.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 137912[58:Res:137910.0,61.1] always3(s48) || -> . % 76.16/76.33 137913[58:SSi:137912.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.33 137914[56:Spt:137913.0,137833.0,137836.0] || trans(s49,s47)*+ -> . % 76.16/76.33 137915[56:Spt:137913.0,137833.1,137833.2,137833.3,137833.4,137833.5,137833.6,137833.7,137833.8,137833.9,137833.10,137833.11,137833.12,137833.13,137833.14,137833.15,137833.16,137833.17,137833.18,137833.19,137833.20,137833.21,137833.22,137833.23,137833.24,137833.25,137833.26,137833.27,137833.28,137833.29,137833.30,137833.31,137833.32,137833.33,137833.34,137833.35,137833.36,137833.37,137833.38,137833.39,137833.40,137833.41,137833.42,137833.43] || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.33 137917[56:MRR:137835.1,137914.0] xuntil6(s49) || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.33 137918[57:Spt:137915.0] || -> trans(s49,s46)*. % 76.16/76.33 137919[57:Res:137918.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s46)*. % 76.16/76.33 137921[57:Res:137918.0,60.0] || -> node2(s49,s46)*. % 76.16/76.33 137922[57:SSi:137919.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s46)*. % 76.16/76.33 137923[57:Res:137921.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 137939[57:SoR:137923.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 137941[57:SoR:137939.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)* xuntil6(s49). % 76.16/76.33 137942[57:SSi:137941.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s46,c_busy)* xuntil6(s49). % 76.16/76.33 137943[58:Spt:137942.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 137945[58:Res:137943.0,61.1] always3(s46) || -> . % 76.16/76.33 137946[58:SSi:137945.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.33 137947[58:Spt:137946.0,137942.1,137943.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.16/76.33 137948[58:Spt:137946.0,137942.0,137942.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 137952[58:MRR:137939.2,137947.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 137953[58:Res:53.1,137948.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 137955[58:MRR:137953.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 137956[58:MRR:137922.0,137955.0] || -> until2p7(s46)*. % 76.16/76.33 137957[58:MRR:549.0,137956.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 137958[59:Spt:137957.0] || -> until2p7(s47)*. % 76.16/76.33 137959[59:MRR:554.0,137958.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 137960[60:Spt:137959.0] || -> until2p7(s48)*. % 76.16/76.33 137961[60:MRR:559.0,137960.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 137962[61:Spt:137961.0] || -> until2p7(s49)*. % 76.16/76.33 137963[61:MRR:194.0,137962.0] || -> node4(s49)*. % 76.16/76.33 137964[61:MRR:137952.0,137963.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 137968[61:Res:53.1,137964.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 137970[61:MRR:137968.0,78381.0] || -> . % 76.16/76.33 137971[61:Spt:137970.0,137961.0,137962.0] || until2p7(s49)*+ -> . % 76.16/76.33 137972[61:Spt:137970.0,137961.1] || -> node4(s48)*. % 76.16/76.33 137973[61:MRR:78384.0,137972.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 137976[61:Res:53.1,137973.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 137979[61:Res:137976.0,61.1] always3(s48) || -> . % 76.16/76.33 137980[61:SSi:137979.0,78281.0,78387.0,137770.0,137960.0,137972.0] || -> . % 76.16/76.33 137981[60:Spt:137980.0,137959.0,137960.0] || until2p7(s48)*+ -> . % 76.16/76.33 137982[60:Spt:137980.0,137959.1] || -> node4(s47)*. % 76.16/76.33 137984[60:MRR:777.0,137982.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 137996[60:Res:53.1,137984.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 137998[61:Spt:137996.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 138000[61:Res:137998.0,61.1] always3(s48) || -> . % 76.16/76.33 138001[61:SSi:138000.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.33 138002[61:Spt:138001.0,137996.1,137998.0] || m_main_v_state(s48,c_busy)* -> . % 76.16/76.33 138003[61:Spt:138001.0,137996.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 138006[61:Res:138003.0,61.1] always3(s47) || -> . % 76.16/76.33 138007[61:SSi:138006.0,78277.0,78280.0,137769.0,137958.0,137982.0] || -> . % 76.16/76.33 138008[59:Spt:138007.0,137957.0,137958.0] || until2p7(s47)*+ -> . % 76.16/76.33 138009[59:Spt:138007.0,137957.1] || -> node4(s46)*. % 76.16/76.33 138011[59:MRR:780.0,138009.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 138018[59:Res:53.1,138011.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 138020[59:MRR:138018.0,137947.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 138025[59:Res:138020.0,61.1] always3(s47) || -> . % 76.16/76.33 138026[59:SSi:138025.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.33 138027[57:Spt:138026.0,137915.0,137918.0] || trans(s49,s46)*+ -> . % 76.16/76.33 138028[57:Spt:138026.0,137915.1,137915.2,137915.3,137915.4,137915.5,137915.6,137915.7,137915.8,137915.9,137915.10,137915.11,137915.12,137915.13,137915.14,137915.15,137915.16,137915.17,137915.18,137915.19,137915.20,137915.21,137915.22,137915.23,137915.24,137915.25,137915.26,137915.27,137915.28,137915.29,137915.30,137915.31,137915.32,137915.33,137915.34,137915.35,137915.36,137915.37,137915.38,137915.39,137915.40,137915.41,137915.42] || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.33 138030[57:MRR:137917.1,138027.0] xuntil6(s49) || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.33 138031[58:Spt:138028.0] || -> trans(s49,s45)*. % 76.16/76.33 138032[58:Res:138031.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s45)*. % 76.16/76.33 138034[58:Res:138031.0,60.0] || -> node2(s49,s45)*. % 76.16/76.33 138035[58:SSi:138032.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s45)*. % 76.16/76.33 138036[58:Res:138034.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 138052[58:SoR:138036.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 138054[58:SoR:138052.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)* xuntil6(s49). % 76.16/76.33 138055[58:SSi:138054.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s45,c_busy)* xuntil6(s49). % 76.16/76.33 138056[59:Spt:138055.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 138058[59:Res:138056.0,61.1] always3(s45) || -> . % 76.16/76.33 138059[59:SSi:138058.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.33 138060[59:Spt:138059.0,138055.1,138056.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.16/76.33 138061[59:Spt:138059.0,138055.0,138055.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 138065[59:MRR:138052.2,138060.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 138066[59:Res:53.1,138061.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 138068[59:MRR:138066.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 138069[59:MRR:138035.0,138068.0] || -> until2p7(s45)*. % 76.16/76.33 138070[59:MRR:544.0,138069.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 138071[60:Spt:138070.0] || -> until2p7(s46)*. % 76.16/76.33 138072[60:MRR:549.0,138071.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 138073[61:Spt:138072.0] || -> until2p7(s47)*. % 76.16/76.33 138074[61:MRR:554.0,138073.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 138075[62:Spt:138074.0] || -> until2p7(s48)*. % 76.16/76.33 138076[62:MRR:559.0,138075.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 138077[63:Spt:138076.0] || -> until2p7(s49)*. % 76.16/76.33 138078[63:MRR:194.0,138077.0] || -> node4(s49)*. % 76.16/76.33 138079[63:MRR:138065.0,138078.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 138080[63:Res:53.1,138079.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 138082[63:MRR:138080.0,78381.0] || -> . % 76.16/76.33 138083[63:Spt:138082.0,138076.0,138077.0] || until2p7(s49)*+ -> . % 76.16/76.33 138084[63:Spt:138082.0,138076.1] || -> node4(s48)*. % 76.16/76.33 138085[63:MRR:78384.0,138084.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 138088[63:Res:53.1,138085.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 138091[63:Res:138088.0,61.1] always3(s48) || -> . % 76.16/76.33 138092[63:SSi:138091.0,78281.0,78387.0,137770.0,138075.0,138084.0] || -> . % 76.16/76.33 138093[62:Spt:138092.0,138074.0,138075.0] || until2p7(s48)*+ -> . % 76.16/76.33 138094[62:Spt:138092.0,138074.1] || -> node4(s47)*. % 76.16/76.33 138096[62:MRR:777.0,138094.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 138111[62:Res:53.1,138096.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 138113[63:Spt:138111.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 138115[63:Res:138113.0,61.1] always3(s47) || -> . % 76.16/76.33 138116[63:SSi:138115.0,78277.0,78280.0,137769.0,138073.0,138094.0] || -> . % 76.16/76.33 138117[63:Spt:138116.0,138111.0,138113.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 138118[63:Spt:138116.0,138111.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 138122[63:Res:138118.0,61.1] always3(s48) || -> . % 76.16/76.33 138123[63:SSi:138122.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.33 138124[61:Spt:138123.0,138072.0,138073.0] || until2p7(s47)*+ -> . % 76.16/76.33 138125[61:Spt:138123.0,138072.1] || -> node4(s46)*. % 76.16/76.33 138127[61:MRR:780.0,138125.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 138137[61:Res:53.1,138127.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 138139[62:Spt:138137.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 138141[62:Res:138139.0,61.1] always3(s46) || -> . % 76.16/76.33 138142[62:SSi:138141.0,78272.0,78276.0,137768.0,138071.0,138125.0] || -> . % 76.16/76.33 138143[62:Spt:138142.0,138137.0,138139.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 138144[62:Spt:138142.0,138137.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 138148[62:Res:138144.0,61.1] always3(s47) || -> . % 76.16/76.33 138149[62:SSi:138148.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.33 138150[60:Spt:138149.0,138070.0,138071.0] || until2p7(s46)*+ -> . % 76.16/76.33 138151[60:Spt:138149.0,138070.1] || -> node4(s45)*. % 76.16/76.33 138153[60:MRR:783.0,138151.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 138156[60:Res:53.1,138153.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 138158[60:MRR:138156.0,138060.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 138160[60:Res:138158.0,61.1] always3(s46) || -> . % 76.16/76.33 138161[60:SSi:138160.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.33 138162[58:Spt:138161.0,138028.0,138031.0] || trans(s49,s45)*+ -> . % 76.16/76.33 138163[58:Spt:138161.0,138028.1,138028.2,138028.3,138028.4,138028.5,138028.6,138028.7,138028.8,138028.9,138028.10,138028.11,138028.12,138028.13,138028.14,138028.15,138028.16,138028.17,138028.18,138028.19,138028.20,138028.21,138028.22,138028.23,138028.24,138028.25,138028.26,138028.27,138028.28,138028.29,138028.30,138028.31,138028.32,138028.33,138028.34,138028.35,138028.36,138028.37,138028.38,138028.39,138028.40,138028.41] || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.33 138165[58:MRR:138030.1,138162.0] xuntil6(s49) || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.33 138166[59:Spt:138163.0] || -> trans(s49,s44)*. % 76.16/76.33 138167[59:Res:138166.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s44)*. % 76.16/76.33 138169[59:Res:138166.0,60.0] || -> node2(s49,s44)*. % 76.16/76.33 138170[59:SSi:138167.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s44)*. % 76.16/76.33 138171[59:Res:138169.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 138191[59:SoR:138171.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 138193[59:SoR:138191.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)* xuntil6(s49). % 76.16/76.33 138194[59:SSi:138193.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s44,c_busy)* xuntil6(s49). % 76.16/76.33 138195[60:Spt:138194.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 138197[60:Res:138195.0,61.1] always3(s44) || -> . % 76.16/76.33 138198[60:SSi:138197.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.33 138199[60:Spt:138198.0,138194.1,138195.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.16/76.33 138200[60:Spt:138198.0,138194.0,138194.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 138204[60:MRR:138191.2,138199.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 138205[60:Res:53.1,138200.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 138207[60:MRR:138205.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 138208[60:MRR:138170.0,138207.0] || -> until2p7(s44)*. % 76.16/76.33 138209[60:MRR:539.0,138208.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 138210[61:Spt:138209.0] || -> until2p7(s45)*. % 76.16/76.33 138211[61:MRR:544.0,138210.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 138212[62:Spt:138211.0] || -> until2p7(s46)*. % 76.16/76.33 138213[62:MRR:549.0,138212.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 138214[63:Spt:138213.0] || -> until2p7(s47)*. % 76.16/76.33 138215[63:MRR:554.0,138214.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 138216[64:Spt:138215.0] || -> until2p7(s48)*. % 76.16/76.33 138217[64:MRR:559.0,138216.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 138218[65:Spt:138217.0] || -> until2p7(s49)*. % 76.16/76.33 138219[65:MRR:194.0,138218.0] || -> node4(s49)*. % 76.16/76.33 138220[65:MRR:138204.0,138219.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 138221[65:Res:53.1,138220.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 138223[65:MRR:138221.0,78381.0] || -> . % 76.16/76.33 138224[65:Spt:138223.0,138217.0,138218.0] || until2p7(s49)*+ -> . % 76.16/76.33 138225[65:Spt:138223.0,138217.1] || -> node4(s48)*. % 76.16/76.33 138226[65:MRR:78384.0,138225.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 138229[65:Res:53.1,138226.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 138232[65:Res:138229.0,61.1] always3(s48) || -> . % 76.16/76.33 138233[65:SSi:138232.0,78281.0,78387.0,137770.0,138216.0,138225.0] || -> . % 76.16/76.33 138234[64:Spt:138233.0,138215.0,138216.0] || until2p7(s48)*+ -> . % 76.16/76.33 138235[64:Spt:138233.0,138215.1] || -> node4(s47)*. % 76.16/76.33 138237[64:MRR:777.0,138235.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 138252[64:Res:53.1,138237.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 138254[65:Spt:138252.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 138256[65:Res:138254.0,61.1] always3(s47) || -> . % 76.16/76.33 138257[65:SSi:138256.0,78277.0,78280.0,137769.0,138214.0,138235.0] || -> . % 76.16/76.33 138258[65:Spt:138257.0,138252.0,138254.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 138259[65:Spt:138257.0,138252.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 138263[65:Res:138259.0,61.1] always3(s48) || -> . % 76.16/76.33 138264[65:SSi:138263.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.33 138265[63:Spt:138264.0,138213.0,138214.0] || until2p7(s47)*+ -> . % 76.16/76.33 138266[63:Spt:138264.0,138213.1] || -> node4(s46)*. % 76.16/76.33 138268[63:MRR:780.0,138266.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 138278[63:Res:53.1,138268.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 138280[64:Spt:138278.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 138282[64:Res:138280.0,61.1] always3(s46) || -> . % 76.16/76.33 138283[64:SSi:138282.0,78272.0,78276.0,137768.0,138212.0,138266.0] || -> . % 76.16/76.33 138284[64:Spt:138283.0,138278.0,138280.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 138285[64:Spt:138283.0,138278.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 138289[64:Res:138285.0,61.1] always3(s47) || -> . % 76.16/76.33 138290[64:SSi:138289.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.33 138291[62:Spt:138290.0,138211.0,138212.0] || until2p7(s46)*+ -> . % 76.16/76.33 138292[62:Spt:138290.0,138211.1] || -> node4(s45)*. % 76.16/76.33 138294[62:MRR:783.0,138292.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 138297[62:Res:53.1,138294.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 138299[63:Spt:138297.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 138301[63:Res:138299.0,61.1] always3(s45) || -> . % 76.16/76.33 138302[63:SSi:138301.0,78268.0,78271.0,137767.0,138210.0,138292.0] || -> . % 76.16/76.33 138303[63:Spt:138302.0,138297.0,138299.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.33 138304[63:Spt:138302.0,138297.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 138308[63:Res:138304.0,61.1] always3(s46) || -> . % 76.16/76.33 138309[63:SSi:138308.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.33 138310[61:Spt:138309.0,138209.0,138210.0] || until2p7(s45)*+ -> . % 76.16/76.33 138311[61:Spt:138309.0,138209.1] || -> node4(s44)*. % 76.16/76.33 138313[61:MRR:786.0,138311.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.33 138316[61:Res:53.1,138313.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.33 138318[61:MRR:138316.0,138199.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 138320[61:Res:138318.0,61.1] always3(s45) || -> . % 76.16/76.33 138321[61:SSi:138320.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.33 138322[59:Spt:138321.0,138163.0,138166.0] || trans(s49,s44)*+ -> . % 76.16/76.33 138323[59:Spt:138321.0,138163.1,138163.2,138163.3,138163.4,138163.5,138163.6,138163.7,138163.8,138163.9,138163.10,138163.11,138163.12,138163.13,138163.14,138163.15,138163.16,138163.17,138163.18,138163.19,138163.20,138163.21,138163.22,138163.23,138163.24,138163.25,138163.26,138163.27,138163.28,138163.29,138163.30,138163.31,138163.32,138163.33,138163.34,138163.35,138163.36,138163.37,138163.38,138163.39,138163.40] || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.33 138325[59:MRR:138165.1,138322.0] xuntil6(s49) || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.33 138326[60:Spt:138323.0] || -> trans(s49,s43)*. % 76.16/76.33 138327[60:Res:138326.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s43)*. % 76.16/76.33 138329[60:Res:138326.0,60.0] || -> node2(s49,s43)*. % 76.16/76.33 138330[60:SSi:138327.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s43)*. % 76.16/76.33 138331[60:Res:138329.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 138355[60:SoR:138331.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 138357[60:SoR:138355.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 76.16/76.33 138358[60:SSi:138357.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 76.16/76.33 138359[61:Spt:138358.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 138361[61:Res:138359.0,61.1] always3(s43) || -> . % 76.16/76.33 138362[61:SSi:138361.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.33 138363[61:Spt:138362.0,138358.1,138359.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.16/76.33 138364[61:Spt:138362.0,138358.0,138358.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 138368[61:MRR:138355.2,138363.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 138369[61:Res:53.1,138364.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 138371[61:MRR:138369.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 138372[61:MRR:138330.0,138371.0] || -> until2p7(s43)*. % 76.16/76.33 138373[61:MRR:241.0,138372.0] || -> until2p7(s44)* node4(s43). % 76.16/76.33 138374[62:Spt:138373.0] || -> until2p7(s44)*. % 76.16/76.33 138375[62:MRR:539.0,138374.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 138376[63:Spt:138375.0] || -> until2p7(s45)*. % 76.16/76.33 138377[63:MRR:544.0,138376.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 138378[64:Spt:138377.0] || -> until2p7(s46)*. % 76.16/76.33 138379[64:MRR:549.0,138378.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 138380[65:Spt:138379.0] || -> until2p7(s47)*. % 76.16/76.33 138381[65:MRR:554.0,138380.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 138382[66:Spt:138381.0] || -> until2p7(s48)*. % 76.16/76.33 138383[66:MRR:559.0,138382.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 138384[67:Spt:138383.0] || -> until2p7(s49)*. % 76.16/76.33 138385[67:MRR:194.0,138384.0] || -> node4(s49)*. % 76.16/76.33 138386[67:MRR:138368.0,138385.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 138390[67:Res:53.1,138386.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 138392[67:MRR:138390.0,78381.0] || -> . % 76.16/76.33 138393[67:Spt:138392.0,138383.0,138384.0] || until2p7(s49)*+ -> . % 76.16/76.33 138394[67:Spt:138392.0,138383.1] || -> node4(s48)*. % 76.16/76.33 138395[67:MRR:78384.0,138394.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 138398[67:Res:53.1,138395.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 138401[67:Res:138398.0,61.1] always3(s48) || -> . % 76.16/76.33 138402[67:SSi:138401.0,78281.0,78387.0,137770.0,138382.0,138394.0] || -> . % 76.16/76.33 138403[66:Spt:138402.0,138381.0,138382.0] || until2p7(s48)*+ -> . % 76.16/76.33 138404[66:Spt:138402.0,138381.1] || -> node4(s47)*. % 76.16/76.33 138406[66:MRR:777.0,138404.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 138418[66:Res:53.1,138406.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 138420[67:Spt:138418.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 138422[67:Res:138420.0,61.1] always3(s47) || -> . % 76.16/76.33 138423[67:SSi:138422.0,78277.0,78280.0,137769.0,138380.0,138404.0] || -> . % 76.16/76.33 138424[67:Spt:138423.0,138418.0,138420.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 138425[67:Spt:138423.0,138418.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 138429[67:Res:138425.0,61.1] always3(s48) || -> . % 76.16/76.33 138430[67:SSi:138429.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.33 138431[65:Spt:138430.0,138379.0,138380.0] || until2p7(s47)*+ -> . % 76.16/76.33 138432[65:Spt:138430.0,138379.1] || -> node4(s46)*. % 76.16/76.33 138434[65:MRR:780.0,138432.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 138441[65:Res:53.1,138434.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 138446[66:Spt:138441.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 138448[66:Res:138446.0,61.1] always3(s46) || -> . % 76.16/76.33 138449[66:SSi:138448.0,78272.0,78276.0,137768.0,138378.0,138432.0] || -> . % 76.16/76.33 138450[66:Spt:138449.0,138441.0,138446.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 138451[66:Spt:138449.0,138441.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 138455[66:Res:138451.0,61.1] always3(s47) || -> . % 76.16/76.33 138456[66:SSi:138455.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.33 138457[64:Spt:138456.0,138377.0,138378.0] || until2p7(s46)*+ -> . % 76.16/76.33 138458[64:Spt:138456.0,138377.1] || -> node4(s45)*. % 76.16/76.33 138460[64:MRR:783.0,138458.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 138463[64:Res:53.1,138460.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 138465[65:Spt:138463.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 138467[65:Res:138465.0,61.1] always3(s45) || -> . % 76.16/76.33 138468[65:SSi:138467.0,78268.0,78271.0,137767.0,138376.0,138458.0] || -> . % 76.16/76.33 138469[65:Spt:138468.0,138463.0,138465.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.33 138470[65:Spt:138468.0,138463.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 138474[65:Res:138470.0,61.1] always3(s46) || -> . % 76.16/76.33 138475[65:SSi:138474.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.33 138476[63:Spt:138475.0,138375.0,138376.0] || until2p7(s45)*+ -> . % 76.16/76.33 138477[63:Spt:138475.0,138375.1] || -> node4(s44)*. % 76.16/76.33 138479[63:MRR:786.0,138477.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.33 138482[63:Res:53.1,138479.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.33 138484[64:Spt:138482.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 138486[64:Res:138484.0,61.1] always3(s44) || -> . % 76.16/76.33 138487[64:SSi:138486.0,78263.0,78267.0,137766.0,138374.0,138477.0] || -> . % 76.16/76.33 138488[64:Spt:138487.0,138482.0,138484.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.33 138489[64:Spt:138487.0,138482.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 138493[64:Res:138489.0,61.1] always3(s45) || -> . % 76.16/76.33 138494[64:SSi:138493.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.33 138495[62:Spt:138494.0,138373.0,138374.0] || until2p7(s44)*+ -> . % 76.16/76.33 138496[62:Spt:138494.0,138373.1] || -> node4(s43)*. % 76.16/76.33 138498[62:MRR:789.0,138496.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.33 138501[62:Res:53.1,138498.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.33 138503[62:MRR:138501.0,138363.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 138505[62:Res:138503.0,61.1] always3(s44) || -> . % 76.16/76.33 138506[62:SSi:138505.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.33 138507[60:Spt:138506.0,138323.0,138326.0] || trans(s49,s43)*+ -> . % 76.16/76.33 138508[60:Spt:138506.0,138323.1,138323.2,138323.3,138323.4,138323.5,138323.6,138323.7,138323.8,138323.9,138323.10,138323.11,138323.12,138323.13,138323.14,138323.15,138323.16,138323.17,138323.18,138323.19,138323.20,138323.21,138323.22,138323.23,138323.24,138323.25,138323.26,138323.27,138323.28,138323.29,138323.30,138323.31,138323.32,138323.33,138323.34,138323.35,138323.36,138323.37,138323.38,138323.39] || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.33 138510[60:MRR:138325.1,138507.0] xuntil6(s49) || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.33 138511[61:Spt:138508.0] || -> trans(s49,s42)*. % 76.16/76.33 138512[61:Res:138511.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s42)*. % 76.16/76.33 138514[61:Res:138511.0,60.0] || -> node2(s49,s42)*. % 76.16/76.33 138515[61:SSi:138512.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s42)*. % 76.16/76.33 138516[61:Res:138514.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 138544[61:SoR:138516.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 138546[61:SoR:138544.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)* xuntil6(s49). % 76.16/76.33 138547[61:SSi:138546.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s42,c_busy)* xuntil6(s49). % 76.16/76.33 138548[62:Spt:138547.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 138550[62:Res:138548.0,61.1] always3(s42) || -> . % 76.16/76.33 138551[62:SSi:138550.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.33 138552[62:Spt:138551.0,138547.1,138548.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.16/76.33 138553[62:Spt:138551.0,138547.0,138547.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 138557[62:MRR:138544.2,138552.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 138558[62:Res:53.1,138553.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 138560[62:MRR:138558.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 138561[62:MRR:138515.0,138560.0] || -> until2p7(s42)*. % 76.16/76.33 138562[62:MRR:240.0,138561.0] || -> until2p7(s43)* node4(s42). % 76.16/76.33 138563[63:Spt:138562.0] || -> until2p7(s43)*. % 76.16/76.33 138564[63:MRR:241.0,138563.0] || -> until2p7(s44)* node4(s43). % 76.16/76.33 138565[64:Spt:138564.0] || -> until2p7(s44)*. % 76.16/76.33 138566[64:MRR:539.0,138565.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 138567[65:Spt:138566.0] || -> until2p7(s45)*. % 76.16/76.33 138568[65:MRR:544.0,138567.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 138569[66:Spt:138568.0] || -> until2p7(s46)*. % 76.16/76.33 138570[66:MRR:549.0,138569.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 138571[67:Spt:138570.0] || -> until2p7(s47)*. % 76.16/76.33 138572[67:MRR:554.0,138571.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 138573[68:Spt:138572.0] || -> until2p7(s48)*. % 76.16/76.33 138574[68:MRR:559.0,138573.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 138575[69:Spt:138574.0] || -> until2p7(s49)*. % 76.16/76.33 138576[69:MRR:194.0,138575.0] || -> node4(s49)*. % 76.16/76.33 138577[69:MRR:138557.0,138576.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 138578[69:Res:53.1,138577.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 138580[69:MRR:138578.0,78381.0] || -> . % 76.16/76.33 138581[69:Spt:138580.0,138574.0,138575.0] || until2p7(s49)*+ -> . % 76.16/76.33 138582[69:Spt:138580.0,138574.1] || -> node4(s48)*. % 76.16/76.33 138583[69:MRR:78384.0,138582.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 138586[69:Res:53.1,138583.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 138589[69:Res:138586.0,61.1] always3(s48) || -> . % 76.16/76.33 138590[69:SSi:138589.0,78281.0,78387.0,137770.0,138573.0,138582.0] || -> . % 76.16/76.33 138591[68:Spt:138590.0,138572.0,138573.0] || until2p7(s48)*+ -> . % 76.16/76.33 138592[68:Spt:138590.0,138572.1] || -> node4(s47)*. % 76.16/76.33 138594[68:MRR:777.0,138592.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 138609[68:Res:53.1,138594.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 138614[69:Spt:138609.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 138616[69:Res:138614.0,61.1] always3(s47) || -> . % 76.16/76.33 138617[69:SSi:138616.0,78277.0,78280.0,137769.0,138571.0,138592.0] || -> . % 76.16/76.33 138618[69:Spt:138617.0,138609.0,138614.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 138619[69:Spt:138617.0,138609.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 138623[69:Res:138619.0,61.1] always3(s48) || -> . % 76.16/76.33 138624[69:SSi:138623.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.33 138625[67:Spt:138624.0,138570.0,138571.0] || until2p7(s47)*+ -> . % 76.16/76.33 138626[67:Spt:138624.0,138570.1] || -> node4(s46)*. % 76.16/76.33 138628[67:MRR:780.0,138626.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 138635[67:Res:53.1,138628.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 138637[68:Spt:138635.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 138639[68:Res:138637.0,61.1] always3(s46) || -> . % 76.16/76.33 138640[68:SSi:138639.0,78272.0,78276.0,137768.0,138569.0,138626.0] || -> . % 76.16/76.33 138641[68:Spt:138640.0,138635.0,138637.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 138642[68:Spt:138640.0,138635.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 138646[68:Res:138642.0,61.1] always3(s47) || -> . % 76.16/76.33 138647[68:SSi:138646.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.33 138648[66:Spt:138647.0,138568.0,138569.0] || until2p7(s46)*+ -> . % 76.16/76.33 138649[66:Spt:138647.0,138568.1] || -> node4(s45)*. % 76.16/76.33 138651[66:MRR:783.0,138649.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 138654[66:Res:53.1,138651.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 138659[67:Spt:138654.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 138661[67:Res:138659.0,61.1] always3(s45) || -> . % 76.16/76.33 138662[67:SSi:138661.0,78268.0,78271.0,137767.0,138567.0,138649.0] || -> . % 76.16/76.33 138663[67:Spt:138662.0,138654.0,138659.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.33 138664[67:Spt:138662.0,138654.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 138668[67:Res:138664.0,61.1] always3(s46) || -> . % 76.16/76.33 138669[67:SSi:138668.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.33 138670[65:Spt:138669.0,138566.0,138567.0] || until2p7(s45)*+ -> . % 76.16/76.33 138671[65:Spt:138669.0,138566.1] || -> node4(s44)*. % 76.16/76.33 138673[65:MRR:786.0,138671.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.33 138676[65:Res:53.1,138673.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.33 138678[66:Spt:138676.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 138680[66:Res:138678.0,61.1] always3(s44) || -> . % 76.16/76.33 138681[66:SSi:138680.0,78263.0,78267.0,137766.0,138565.0,138671.0] || -> . % 76.16/76.33 138682[66:Spt:138681.0,138676.0,138678.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.33 138683[66:Spt:138681.0,138676.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 138687[66:Res:138683.0,61.1] always3(s45) || -> . % 76.16/76.33 138688[66:SSi:138687.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.33 138689[64:Spt:138688.0,138564.0,138565.0] || until2p7(s44)*+ -> . % 76.16/76.33 138690[64:Spt:138688.0,138564.1] || -> node4(s43)*. % 76.16/76.33 138692[64:MRR:789.0,138690.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.33 138695[64:Res:53.1,138692.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.33 138697[65:Spt:138695.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 138699[65:Res:138697.0,61.1] always3(s43) || -> . % 76.16/76.33 138700[65:SSi:138699.0,78259.0,78262.0,137765.0,138563.0,138690.0] || -> . % 76.16/76.33 138701[65:Spt:138700.0,138695.0,138697.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.33 138702[65:Spt:138700.0,138695.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 138706[65:Res:138702.0,61.1] always3(s44) || -> . % 76.16/76.33 138707[65:SSi:138706.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.33 138708[63:Spt:138707.0,138562.0,138563.0] || until2p7(s43)*+ -> . % 76.16/76.33 138709[63:Spt:138707.0,138562.1] || -> node4(s42)*. % 76.16/76.33 138711[63:MRR:792.0,138709.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.33 138714[63:Res:53.1,138711.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.33 138716[63:MRR:138714.0,138552.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 138718[63:Res:138716.0,61.1] always3(s43) || -> . % 76.16/76.33 138719[63:SSi:138718.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.33 138720[61:Spt:138719.0,138508.0,138511.0] || trans(s49,s42)*+ -> . % 76.16/76.33 138721[61:Spt:138719.0,138508.1,138508.2,138508.3,138508.4,138508.5,138508.6,138508.7,138508.8,138508.9,138508.10,138508.11,138508.12,138508.13,138508.14,138508.15,138508.16,138508.17,138508.18,138508.19,138508.20,138508.21,138508.22,138508.23,138508.24,138508.25,138508.26,138508.27,138508.28,138508.29,138508.30,138508.31,138508.32,138508.33,138508.34,138508.35,138508.36,138508.37,138508.38] || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.33 138723[61:MRR:138510.1,138720.0] xuntil6(s49) || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.33 138724[62:Spt:138721.0] || -> trans(s49,s41)*. % 76.16/76.33 138725[62:Res:138724.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s41)*. % 76.16/76.33 138727[62:Res:138724.0,60.0] || -> node2(s49,s41)*. % 76.16/76.33 138728[62:SSi:138725.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s41)*. % 76.16/76.33 138729[62:Res:138727.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 138758[62:SoR:138729.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 138760[62:SoR:138758.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)* xuntil6(s49). % 76.16/76.33 138761[62:SSi:138760.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s41,c_busy)* xuntil6(s49). % 76.16/76.33 138762[63:Spt:138761.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 138764[63:Res:138762.0,61.1] always3(s41) || -> . % 76.16/76.33 138765[63:SSi:138764.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.33 138766[63:Spt:138765.0,138761.1,138762.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.16/76.33 138767[63:Spt:138765.0,138761.0,138761.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 138771[63:MRR:138758.2,138766.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 138772[63:Res:53.1,138767.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 138774[63:MRR:138772.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 138775[63:MRR:138728.0,138774.0] || -> until2p7(s41)*. % 76.16/76.33 138776[63:MRR:239.0,138775.0] || -> until2p7(s42)* node4(s41). % 76.16/76.33 138777[64:Spt:138776.0] || -> until2p7(s42)*. % 76.16/76.33 138778[64:MRR:240.0,138777.0] || -> until2p7(s43)* node4(s42). % 76.16/76.33 138779[65:Spt:138778.0] || -> until2p7(s43)*. % 76.16/76.33 138780[65:MRR:241.0,138779.0] || -> until2p7(s44)* node4(s43). % 76.16/76.33 138781[66:Spt:138780.0] || -> until2p7(s44)*. % 76.16/76.33 138782[66:MRR:539.0,138781.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 138783[67:Spt:138782.0] || -> until2p7(s45)*. % 76.16/76.33 138784[67:MRR:544.0,138783.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 138785[68:Spt:138784.0] || -> until2p7(s46)*. % 76.16/76.33 138786[68:MRR:549.0,138785.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 138787[69:Spt:138786.0] || -> until2p7(s47)*. % 76.16/76.33 138788[69:MRR:554.0,138787.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 138789[70:Spt:138788.0] || -> until2p7(s48)*. % 76.16/76.33 138790[70:MRR:559.0,138789.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 138791[71:Spt:138790.0] || -> until2p7(s49)*. % 76.16/76.33 138792[71:MRR:194.0,138791.0] || -> node4(s49)*. % 76.16/76.33 138793[71:MRR:138771.0,138792.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 138797[71:Res:53.1,138793.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 138799[71:MRR:138797.0,78381.0] || -> . % 76.16/76.33 138800[71:Spt:138799.0,138790.0,138791.0] || until2p7(s49)*+ -> . % 76.16/76.33 138801[71:Spt:138799.0,138790.1] || -> node4(s48)*. % 76.16/76.33 138802[71:MRR:78384.0,138801.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 138805[71:Res:53.1,138802.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 138808[71:Res:138805.0,61.1] always3(s48) || -> . % 76.16/76.33 138809[71:SSi:138808.0,78281.0,78387.0,137770.0,138789.0,138801.0] || -> . % 76.16/76.33 138810[70:Spt:138809.0,138788.0,138789.0] || until2p7(s48)*+ -> . % 76.16/76.33 138811[70:Spt:138809.0,138788.1] || -> node4(s47)*. % 76.16/76.33 138813[70:MRR:777.0,138811.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 138825[70:Res:53.1,138813.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 138827[71:Spt:138825.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 138829[71:Res:138827.0,61.1] always3(s47) || -> . % 76.16/76.33 138830[71:SSi:138829.0,78277.0,78280.0,137769.0,138787.0,138811.0] || -> . % 76.16/76.33 138831[71:Spt:138830.0,138825.0,138827.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 138832[71:Spt:138830.0,138825.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 138836[71:Res:138832.0,61.1] always3(s48) || -> . % 76.16/76.33 138837[71:SSi:138836.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.33 138838[69:Spt:138837.0,138786.0,138787.0] || until2p7(s47)*+ -> . % 76.16/76.33 138839[69:Spt:138837.0,138786.1] || -> node4(s46)*. % 76.16/76.33 138841[69:MRR:780.0,138839.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 138848[69:Res:53.1,138841.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 138853[70:Spt:138848.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 138855[70:Res:138853.0,61.1] always3(s46) || -> . % 76.16/76.33 138856[70:SSi:138855.0,78272.0,78276.0,137768.0,138785.0,138839.0] || -> . % 76.16/76.33 138857[70:Spt:138856.0,138848.0,138853.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 138858[70:Spt:138856.0,138848.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 138862[70:Res:138858.0,61.1] always3(s47) || -> . % 76.16/76.33 138863[70:SSi:138862.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.33 138864[68:Spt:138863.0,138784.0,138785.0] || until2p7(s46)*+ -> . % 76.16/76.33 138865[68:Spt:138863.0,138784.1] || -> node4(s45)*. % 76.16/76.33 138867[68:MRR:783.0,138865.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 138870[68:Res:53.1,138867.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 138872[69:Spt:138870.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 138874[69:Res:138872.0,61.1] always3(s45) || -> . % 76.16/76.33 138875[69:SSi:138874.0,78268.0,78271.0,137767.0,138783.0,138865.0] || -> . % 76.16/76.33 138876[69:Spt:138875.0,138870.0,138872.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.33 138877[69:Spt:138875.0,138870.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 138881[69:Res:138877.0,61.1] always3(s46) || -> . % 76.16/76.33 138882[69:SSi:138881.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.33 138883[67:Spt:138882.0,138782.0,138783.0] || until2p7(s45)*+ -> . % 76.16/76.33 138884[67:Spt:138882.0,138782.1] || -> node4(s44)*. % 76.16/76.33 138886[67:MRR:786.0,138884.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.33 138889[67:Res:53.1,138886.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.33 138891[68:Spt:138889.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 138893[68:Res:138891.0,61.1] always3(s44) || -> . % 76.16/76.33 138894[68:SSi:138893.0,78263.0,78267.0,137766.0,138781.0,138884.0] || -> . % 76.16/76.33 138895[68:Spt:138894.0,138889.0,138891.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.33 138896[68:Spt:138894.0,138889.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 138900[68:Res:138896.0,61.1] always3(s45) || -> . % 76.16/76.33 138901[68:SSi:138900.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.33 138902[66:Spt:138901.0,138780.0,138781.0] || until2p7(s44)*+ -> . % 76.16/76.33 138903[66:Spt:138901.0,138780.1] || -> node4(s43)*. % 76.16/76.33 138905[66:MRR:789.0,138903.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.33 138908[66:Res:53.1,138905.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.33 138910[67:Spt:138908.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 138912[67:Res:138910.0,61.1] always3(s43) || -> . % 76.16/76.33 138913[67:SSi:138912.0,78259.0,78262.0,137765.0,138779.0,138903.0] || -> . % 76.16/76.33 138914[67:Spt:138913.0,138908.0,138910.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.33 138915[67:Spt:138913.0,138908.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 138919[67:Res:138915.0,61.1] always3(s44) || -> . % 76.16/76.33 138920[67:SSi:138919.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.33 138921[65:Spt:138920.0,138778.0,138779.0] || until2p7(s43)*+ -> . % 76.16/76.33 138922[65:Spt:138920.0,138778.1] || -> node4(s42)*. % 76.16/76.33 138924[65:MRR:792.0,138922.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.33 138927[65:Res:53.1,138924.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.33 138932[66:Spt:138927.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 138934[66:Res:138932.0,61.1] always3(s42) || -> . % 76.16/76.33 138935[66:SSi:138934.0,78254.0,78258.0,137764.0,138777.0,138922.0] || -> . % 76.16/76.33 138936[66:Spt:138935.0,138927.0,138932.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.33 138937[66:Spt:138935.0,138927.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 138941[66:Res:138937.0,61.1] always3(s43) || -> . % 76.16/76.33 138942[66:SSi:138941.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.33 138943[64:Spt:138942.0,138776.0,138777.0] || until2p7(s42)*+ -> . % 76.16/76.33 138944[64:Spt:138942.0,138776.1] || -> node4(s41)*. % 76.16/76.33 138946[64:MRR:795.0,138944.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.33 138949[64:Res:53.1,138946.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.33 138951[64:MRR:138949.0,138766.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 138953[64:Res:138951.0,61.1] always3(s42) || -> . % 76.16/76.33 138954[64:SSi:138953.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.33 138955[62:Spt:138954.0,138721.0,138724.0] || trans(s49,s41)*+ -> . % 76.16/76.33 138956[62:Spt:138954.0,138721.1,138721.2,138721.3,138721.4,138721.5,138721.6,138721.7,138721.8,138721.9,138721.10,138721.11,138721.12,138721.13,138721.14,138721.15,138721.16,138721.17,138721.18,138721.19,138721.20,138721.21,138721.22,138721.23,138721.24,138721.25,138721.26,138721.27,138721.28,138721.29,138721.30,138721.31,138721.32,138721.33,138721.34,138721.35,138721.36,138721.37] || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.33 138958[62:MRR:138723.1,138955.0] xuntil6(s49) || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.33 138959[63:Spt:138956.0] || -> trans(s49,s40)*. % 76.16/76.33 138960[63:Res:138959.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s40)*. % 76.16/76.33 138962[63:Res:138959.0,60.0] || -> node2(s49,s40)*. % 76.16/76.33 138963[63:SSi:138960.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s40)*. % 76.16/76.33 138964[63:Res:138962.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 138997[63:SoR:138964.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 138999[63:SoR:138997.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)* xuntil6(s49). % 76.16/76.33 139000[63:SSi:138999.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s40,c_busy)* xuntil6(s49). % 76.16/76.33 139001[64:Spt:139000.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 139003[64:Res:139001.0,61.1] always3(s40) || -> . % 76.16/76.33 139004[64:SSi:139003.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.33 139005[64:Spt:139004.0,139000.1,139001.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.16/76.33 139006[64:Spt:139004.0,139000.0,139000.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 139010[64:MRR:138997.2,139005.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 139011[64:Res:53.1,139006.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 139013[64:MRR:139011.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 139014[64:MRR:138963.0,139013.0] || -> until2p7(s40)*. % 76.16/76.33 139015[64:MRR:238.0,139014.0] || -> until2p7(s41)* node4(s40). % 76.16/76.33 139016[65:Spt:139015.0] || -> until2p7(s41)*. % 76.16/76.33 139017[65:MRR:239.0,139016.0] || -> until2p7(s42)* node4(s41). % 76.16/76.33 139018[66:Spt:139017.0] || -> until2p7(s42)*. % 76.16/76.33 139019[66:MRR:240.0,139018.0] || -> until2p7(s43)* node4(s42). % 76.16/76.33 139020[67:Spt:139019.0] || -> until2p7(s43)*. % 76.16/76.33 139021[67:MRR:241.0,139020.0] || -> until2p7(s44)* node4(s43). % 76.16/76.33 139022[68:Spt:139021.0] || -> until2p7(s44)*. % 76.16/76.33 139023[68:MRR:539.0,139022.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 139024[69:Spt:139023.0] || -> until2p7(s45)*. % 76.16/76.33 139025[69:MRR:544.0,139024.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 139026[70:Spt:139025.0] || -> until2p7(s46)*. % 76.16/76.33 139027[70:MRR:549.0,139026.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 139028[71:Spt:139027.0] || -> until2p7(s47)*. % 76.16/76.33 139029[71:MRR:554.0,139028.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 139030[72:Spt:139029.0] || -> until2p7(s48)*. % 76.16/76.33 139031[72:MRR:559.0,139030.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 139032[73:Spt:139031.0] || -> until2p7(s49)*. % 76.16/76.33 139033[73:MRR:194.0,139032.0] || -> node4(s49)*. % 76.16/76.33 139034[73:MRR:139010.0,139033.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 139035[73:Res:53.1,139034.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 139037[73:MRR:139035.0,78381.0] || -> . % 76.16/76.33 139038[73:Spt:139037.0,139031.0,139032.0] || until2p7(s49)*+ -> . % 76.16/76.33 139039[73:Spt:139037.0,139031.1] || -> node4(s48)*. % 76.16/76.33 139040[73:MRR:78384.0,139039.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 139043[73:Res:53.1,139040.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 139046[73:Res:139043.0,61.1] always3(s48) || -> . % 76.16/76.33 139047[73:SSi:139046.0,78281.0,78387.0,137770.0,139030.0,139039.0] || -> . % 76.16/76.33 139048[72:Spt:139047.0,139029.0,139030.0] || until2p7(s48)*+ -> . % 76.16/76.33 139049[72:Spt:139047.0,139029.1] || -> node4(s47)*. % 76.16/76.33 139051[72:MRR:777.0,139049.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 139066[72:Res:53.1,139051.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 139068[73:Spt:139066.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 139070[73:Res:139068.0,61.1] always3(s47) || -> . % 76.16/76.33 139071[73:SSi:139070.0,78277.0,78280.0,137769.0,139028.0,139049.0] || -> . % 76.16/76.33 139072[73:Spt:139071.0,139066.0,139068.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 139073[73:Spt:139071.0,139066.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 139077[73:Res:139073.0,61.1] always3(s48) || -> . % 76.16/76.33 139078[73:SSi:139077.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.33 139079[71:Spt:139078.0,139027.0,139028.0] || until2p7(s47)*+ -> . % 76.16/76.33 139080[71:Spt:139078.0,139027.1] || -> node4(s46)*. % 76.16/76.33 139082[71:MRR:780.0,139080.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 139092[71:Res:53.1,139082.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 139094[72:Spt:139092.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 139096[72:Res:139094.0,61.1] always3(s46) || -> . % 76.16/76.33 139097[72:SSi:139096.0,78272.0,78276.0,137768.0,139026.0,139080.0] || -> . % 76.16/76.33 139098[72:Spt:139097.0,139092.0,139094.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 139099[72:Spt:139097.0,139092.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 139103[72:Res:139099.0,61.1] always3(s47) || -> . % 76.16/76.33 139104[72:SSi:139103.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.33 139105[70:Spt:139104.0,139025.0,139026.0] || until2p7(s46)*+ -> . % 76.16/76.33 139106[70:Spt:139104.0,139025.1] || -> node4(s45)*. % 76.16/76.33 139108[70:MRR:783.0,139106.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 139111[70:Res:53.1,139108.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 139113[71:Spt:139111.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 139115[71:Res:139113.0,61.1] always3(s45) || -> . % 76.16/76.33 139116[71:SSi:139115.0,78268.0,78271.0,137767.0,139024.0,139106.0] || -> . % 76.16/76.33 139117[71:Spt:139116.0,139111.0,139113.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.33 139118[71:Spt:139116.0,139111.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 139122[71:Res:139118.0,61.1] always3(s46) || -> . % 76.16/76.33 139123[71:SSi:139122.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.33 139124[69:Spt:139123.0,139023.0,139024.0] || until2p7(s45)*+ -> . % 76.16/76.33 139125[69:Spt:139123.0,139023.1] || -> node4(s44)*. % 76.16/76.33 139127[69:MRR:786.0,139125.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.33 139130[69:Res:53.1,139127.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.33 139132[70:Spt:139130.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 139134[70:Res:139132.0,61.1] always3(s44) || -> . % 76.16/76.33 139135[70:SSi:139134.0,78263.0,78267.0,137766.0,139022.0,139125.0] || -> . % 76.16/76.33 139136[70:Spt:139135.0,139130.0,139132.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.33 139137[70:Spt:139135.0,139130.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 139141[70:Res:139137.0,61.1] always3(s45) || -> . % 76.16/76.33 139142[70:SSi:139141.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.33 139143[68:Spt:139142.0,139021.0,139022.0] || until2p7(s44)*+ -> . % 76.16/76.33 139144[68:Spt:139142.0,139021.1] || -> node4(s43)*. % 76.16/76.33 139146[68:MRR:789.0,139144.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.33 139149[68:Res:53.1,139146.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.33 139154[69:Spt:139149.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 139156[69:Res:139154.0,61.1] always3(s43) || -> . % 76.16/76.33 139157[69:SSi:139156.0,78259.0,78262.0,137765.0,139020.0,139144.0] || -> . % 76.16/76.33 139158[69:Spt:139157.0,139149.0,139154.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.33 139159[69:Spt:139157.0,139149.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 139163[69:Res:139159.0,61.1] always3(s44) || -> . % 76.16/76.33 139164[69:SSi:139163.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.33 139165[67:Spt:139164.0,139019.0,139020.0] || until2p7(s43)*+ -> . % 76.16/76.33 139166[67:Spt:139164.0,139019.1] || -> node4(s42)*. % 76.16/76.33 139168[67:MRR:792.0,139166.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.33 139171[67:Res:53.1,139168.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.33 139173[68:Spt:139171.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 139175[68:Res:139173.0,61.1] always3(s42) || -> . % 76.16/76.33 139176[68:SSi:139175.0,78254.0,78258.0,137764.0,139018.0,139166.0] || -> . % 76.16/76.33 139177[68:Spt:139176.0,139171.0,139173.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.33 139178[68:Spt:139176.0,139171.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 139182[68:Res:139178.0,61.1] always3(s43) || -> . % 76.16/76.33 139183[68:SSi:139182.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.33 139184[66:Spt:139183.0,139017.0,139018.0] || until2p7(s42)*+ -> . % 76.16/76.33 139185[66:Spt:139183.0,139017.1] || -> node4(s41)*. % 76.16/76.33 139187[66:MRR:795.0,139185.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.33 139190[66:Res:53.1,139187.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.33 139192[67:Spt:139190.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 139194[67:Res:139192.0,61.1] always3(s41) || -> . % 76.16/76.33 139195[67:SSi:139194.0,78250.0,78253.0,137763.0,139016.0,139185.0] || -> . % 76.16/76.33 139196[67:Spt:139195.0,139190.0,139192.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.33 139197[67:Spt:139195.0,139190.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 139201[67:Res:139197.0,61.1] always3(s42) || -> . % 76.16/76.33 139202[67:SSi:139201.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.33 139203[65:Spt:139202.0,139015.0,139016.0] || until2p7(s41)*+ -> . % 76.16/76.33 139204[65:Spt:139202.0,139015.1] || -> node4(s40)*. % 76.16/76.33 139206[65:MRR:798.0,139204.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.33 139209[65:Res:53.1,139206.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.33 139211[65:MRR:139209.0,139005.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 139213[65:Res:139211.0,61.1] always3(s41) || -> . % 76.16/76.33 139214[65:SSi:139213.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.33 139215[63:Spt:139214.0,138956.0,138959.0] || trans(s49,s40)*+ -> . % 76.16/76.33 139216[63:Spt:139214.0,138956.1,138956.2,138956.3,138956.4,138956.5,138956.6,138956.7,138956.8,138956.9,138956.10,138956.11,138956.12,138956.13,138956.14,138956.15,138956.16,138956.17,138956.18,138956.19,138956.20,138956.21,138956.22,138956.23,138956.24,138956.25,138956.26,138956.27,138956.28,138956.29,138956.30,138956.31,138956.32,138956.33,138956.34,138956.35,138956.36] || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.33 139218[63:MRR:138958.1,139215.0] xuntil6(s49) || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.33 139219[64:Spt:139216.0] || -> trans(s49,s39)*. % 76.16/76.33 139220[64:Res:139219.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s39)*. % 76.16/76.33 139222[64:Res:139219.0,60.0] || -> node2(s49,s39)*. % 76.16/76.33 139223[64:SSi:139220.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s39)*. % 76.16/76.33 139224[64:Res:139222.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 139261[64:SoR:139224.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 139263[64:SoR:139261.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 76.16/76.33 139264[64:SSi:139263.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 76.16/76.33 139265[65:Spt:139264.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.33 139267[65:Res:139265.0,61.1] always3(s39) || -> . % 76.16/76.33 139268[65:SSi:139267.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.33 139269[65:Spt:139268.0,139264.1,139265.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.16/76.33 139270[65:Spt:139268.0,139264.0,139264.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 139274[65:MRR:139261.2,139269.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 139275[65:Res:53.1,139270.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 139277[65:MRR:139275.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 139278[65:MRR:139223.0,139277.0] || -> until2p7(s39)*. % 76.16/76.33 139279[65:MRR:237.0,139278.0] || -> until2p7(s40)* node4(s39). % 76.16/76.33 139280[66:Spt:139279.0] || -> until2p7(s40)*. % 76.16/76.33 139281[66:MRR:238.0,139280.0] || -> until2p7(s41)* node4(s40). % 76.16/76.33 139282[67:Spt:139281.0] || -> until2p7(s41)*. % 76.16/76.33 139283[67:MRR:239.0,139282.0] || -> until2p7(s42)* node4(s41). % 76.16/76.33 139284[68:Spt:139283.0] || -> until2p7(s42)*. % 76.16/76.33 139285[68:MRR:240.0,139284.0] || -> until2p7(s43)* node4(s42). % 76.16/76.33 139286[69:Spt:139285.0] || -> until2p7(s43)*. % 76.16/76.33 139287[69:MRR:241.0,139286.0] || -> until2p7(s44)* node4(s43). % 76.16/76.33 139288[70:Spt:139287.0] || -> until2p7(s44)*. % 76.16/76.33 139289[70:MRR:539.0,139288.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 139290[71:Spt:139289.0] || -> until2p7(s45)*. % 76.16/76.33 139291[71:MRR:544.0,139290.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 139292[72:Spt:139291.0] || -> until2p7(s46)*. % 76.16/76.33 139293[72:MRR:549.0,139292.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 139294[73:Spt:139293.0] || -> until2p7(s47)*. % 76.16/76.33 139295[73:MRR:554.0,139294.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 139296[74:Spt:139295.0] || -> until2p7(s48)*. % 76.16/76.33 139297[74:MRR:559.0,139296.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 139298[75:Spt:139297.0] || -> until2p7(s49)*. % 76.16/76.33 139299[75:MRR:194.0,139298.0] || -> node4(s49)*. % 76.16/76.33 139300[75:MRR:139274.0,139299.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 139301[75:Res:53.1,139300.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 139303[75:MRR:139301.0,78381.0] || -> . % 76.16/76.33 139304[75:Spt:139303.0,139297.0,139298.0] || until2p7(s49)*+ -> . % 76.16/76.33 139305[75:Spt:139303.0,139297.1] || -> node4(s48)*. % 76.16/76.33 139306[75:MRR:78384.0,139305.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 139309[75:Res:53.1,139306.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 139312[75:Res:139309.0,61.1] always3(s48) || -> . % 76.16/76.33 139313[75:SSi:139312.0,78281.0,78387.0,137770.0,139296.0,139305.0] || -> . % 76.16/76.33 139314[74:Spt:139313.0,139295.0,139296.0] || until2p7(s48)*+ -> . % 76.16/76.33 139315[74:Spt:139313.0,139295.1] || -> node4(s47)*. % 76.16/76.33 139317[74:MRR:777.0,139315.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 139332[74:Res:53.1,139317.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 139334[75:Spt:139332.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 139336[75:Res:139334.0,61.1] always3(s47) || -> . % 76.16/76.33 139337[75:SSi:139336.0,78277.0,78280.0,137769.0,139294.0,139315.0] || -> . % 76.16/76.33 139338[75:Spt:139337.0,139332.0,139334.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.33 139339[75:Spt:139337.0,139332.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 139343[75:Res:139339.0,61.1] always3(s48) || -> . % 76.16/76.33 139344[75:SSi:139343.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.33 139345[73:Spt:139344.0,139293.0,139294.0] || until2p7(s47)*+ -> . % 76.16/76.33 139346[73:Spt:139344.0,139293.1] || -> node4(s46)*. % 76.16/76.33 139348[73:MRR:780.0,139346.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.33 139358[73:Res:53.1,139348.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.33 139360[74:Spt:139358.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 139362[74:Res:139360.0,61.1] always3(s46) || -> . % 76.16/76.33 139363[74:SSi:139362.0,78272.0,78276.0,137768.0,139292.0,139346.0] || -> . % 76.16/76.33 139364[74:Spt:139363.0,139358.0,139360.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.33 139365[74:Spt:139363.0,139358.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 139369[74:Res:139365.0,61.1] always3(s47) || -> . % 76.16/76.33 139370[74:SSi:139369.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.33 139371[72:Spt:139370.0,139291.0,139292.0] || until2p7(s46)*+ -> . % 76.16/76.33 139372[72:Spt:139370.0,139291.1] || -> node4(s45)*. % 76.16/76.33 139374[72:MRR:783.0,139372.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.33 139377[72:Res:53.1,139374.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.33 139379[73:Spt:139377.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 139381[73:Res:139379.0,61.1] always3(s45) || -> . % 76.16/76.33 139382[73:SSi:139381.0,78268.0,78271.0,137767.0,139290.0,139372.0] || -> . % 76.16/76.33 139383[73:Spt:139382.0,139377.0,139379.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.33 139384[73:Spt:139382.0,139377.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.33 139388[73:Res:139384.0,61.1] always3(s46) || -> . % 76.16/76.33 139389[73:SSi:139388.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.33 139390[71:Spt:139389.0,139289.0,139290.0] || until2p7(s45)*+ -> . % 76.16/76.33 139391[71:Spt:139389.0,139289.1] || -> node4(s44)*. % 76.16/76.33 139393[71:MRR:786.0,139391.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.33 139396[71:Res:53.1,139393.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.33 139398[72:Spt:139396.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 139400[72:Res:139398.0,61.1] always3(s44) || -> . % 76.16/76.33 139401[72:SSi:139400.0,78263.0,78267.0,137766.0,139288.0,139391.0] || -> . % 76.16/76.33 139402[72:Spt:139401.0,139396.0,139398.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.33 139403[72:Spt:139401.0,139396.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.33 139407[72:Res:139403.0,61.1] always3(s45) || -> . % 76.16/76.33 139408[72:SSi:139407.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.33 139409[70:Spt:139408.0,139287.0,139288.0] || until2p7(s44)*+ -> . % 76.16/76.33 139410[70:Spt:139408.0,139287.1] || -> node4(s43)*. % 76.16/76.33 139412[70:MRR:789.0,139410.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.33 139415[70:Res:53.1,139412.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.33 139420[71:Spt:139415.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 139422[71:Res:139420.0,61.1] always3(s43) || -> . % 76.16/76.33 139423[71:SSi:139422.0,78259.0,78262.0,137765.0,139286.0,139410.0] || -> . % 76.16/76.33 139424[71:Spt:139423.0,139415.0,139420.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.33 139425[71:Spt:139423.0,139415.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.33 139429[71:Res:139425.0,61.1] always3(s44) || -> . % 76.16/76.33 139430[71:SSi:139429.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.33 139431[69:Spt:139430.0,139285.0,139286.0] || until2p7(s43)*+ -> . % 76.16/76.33 139432[69:Spt:139430.0,139285.1] || -> node4(s42)*. % 76.16/76.33 139434[69:MRR:792.0,139432.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.33 139437[69:Res:53.1,139434.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.33 139439[70:Spt:139437.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 139441[70:Res:139439.0,61.1] always3(s42) || -> . % 76.16/76.33 139442[70:SSi:139441.0,78254.0,78258.0,137764.0,139284.0,139432.0] || -> . % 76.16/76.33 139443[70:Spt:139442.0,139437.0,139439.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.33 139444[70:Spt:139442.0,139437.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.33 139448[70:Res:139444.0,61.1] always3(s43) || -> . % 76.16/76.33 139449[70:SSi:139448.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.33 139450[68:Spt:139449.0,139283.0,139284.0] || until2p7(s42)*+ -> . % 76.16/76.33 139451[68:Spt:139449.0,139283.1] || -> node4(s41)*. % 76.16/76.33 139453[68:MRR:795.0,139451.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.33 139456[68:Res:53.1,139453.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.33 139458[69:Spt:139456.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 139460[69:Res:139458.0,61.1] always3(s41) || -> . % 76.16/76.33 139461[69:SSi:139460.0,78250.0,78253.0,137763.0,139282.0,139451.0] || -> . % 76.16/76.33 139462[69:Spt:139461.0,139456.0,139458.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.33 139463[69:Spt:139461.0,139456.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.33 139467[69:Res:139463.0,61.1] always3(s42) || -> . % 76.16/76.33 139468[69:SSi:139467.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.33 139469[67:Spt:139468.0,139281.0,139282.0] || until2p7(s41)*+ -> . % 76.16/76.33 139470[67:Spt:139468.0,139281.1] || -> node4(s40)*. % 76.16/76.33 139472[67:MRR:798.0,139470.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.33 139475[67:Res:53.1,139472.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.33 139477[68:Spt:139475.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 139479[68:Res:139477.0,61.1] always3(s40) || -> . % 76.16/76.33 139480[68:SSi:139479.0,78245.0,78249.0,137762.0,139280.0,139470.0] || -> . % 76.16/76.33 139481[68:Spt:139480.0,139475.0,139477.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.33 139482[68:Spt:139480.0,139475.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.33 139486[68:Res:139482.0,61.1] always3(s41) || -> . % 76.16/76.33 139487[68:SSi:139486.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.33 139488[66:Spt:139487.0,139279.0,139280.0] || until2p7(s40)*+ -> . % 76.16/76.33 139489[66:Spt:139487.0,139279.1] || -> node4(s39)*. % 76.16/76.33 139491[66:MRR:801.0,139489.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.33 139494[66:Res:53.1,139491.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.33 139496[66:MRR:139494.0,139269.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.33 139501[66:Res:139496.0,61.1] always3(s40) || -> . % 76.16/76.33 139502[66:SSi:139501.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.33 139503[64:Spt:139502.0,139216.0,139219.0] || trans(s49,s39)*+ -> . % 76.16/76.33 139504[64:Spt:139502.0,139216.1,139216.2,139216.3,139216.4,139216.5,139216.6,139216.7,139216.8,139216.9,139216.10,139216.11,139216.12,139216.13,139216.14,139216.15,139216.16,139216.17,139216.18,139216.19,139216.20,139216.21,139216.22,139216.23,139216.24,139216.25,139216.26,139216.27,139216.28,139216.29,139216.30,139216.31,139216.32,139216.33,139216.34,139216.35] || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.33 139506[64:MRR:139218.1,139503.0] xuntil6(s49) || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.33 139507[65:Spt:139504.0] || -> trans(s49,s38)*. % 76.16/76.33 139508[65:Res:139507.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s38)*. % 76.16/76.33 139510[65:Res:139507.0,60.0] || -> node2(s49,s38)*. % 76.16/76.33 139511[65:SSi:139508.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s38)*. % 76.16/76.33 139512[65:Res:139510.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 139550[65:SoR:139512.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 139552[65:SoR:139550.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)* xuntil6(s49). % 76.16/76.33 139553[65:SSi:139552.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s38,c_busy)* xuntil6(s49). % 76.16/76.33 139554[66:Spt:139553.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.33 139556[66:Res:139554.0,61.1] always3(s38) || -> . % 76.16/76.33 139557[66:SSi:139556.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.33 139558[66:Spt:139557.0,139553.1,139554.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.16/76.33 139559[66:Spt:139557.0,139553.0,139553.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.33 139563[66:MRR:139550.2,139558.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.33 139564[66:Res:53.1,139559.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.33 139566[66:MRR:139564.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.33 139567[66:MRR:139511.0,139566.0] || -> until2p7(s38)*. % 76.16/76.33 139568[66:MRR:236.0,139567.0] || -> until2p7(s39)* node4(s38). % 76.16/76.33 139569[67:Spt:139568.0] || -> until2p7(s39)*. % 76.16/76.33 139570[67:MRR:237.0,139569.0] || -> until2p7(s40)* node4(s39). % 76.16/76.33 139571[68:Spt:139570.0] || -> until2p7(s40)*. % 76.16/76.33 139572[68:MRR:238.0,139571.0] || -> until2p7(s41)* node4(s40). % 76.16/76.33 139573[69:Spt:139572.0] || -> until2p7(s41)*. % 76.16/76.33 139574[69:MRR:239.0,139573.0] || -> until2p7(s42)* node4(s41). % 76.16/76.33 139575[70:Spt:139574.0] || -> until2p7(s42)*. % 76.16/76.33 139576[70:MRR:240.0,139575.0] || -> until2p7(s43)* node4(s42). % 76.16/76.33 139577[71:Spt:139576.0] || -> until2p7(s43)*. % 76.16/76.33 139578[71:MRR:241.0,139577.0] || -> until2p7(s44)* node4(s43). % 76.16/76.33 139579[72:Spt:139578.0] || -> until2p7(s44)*. % 76.16/76.33 139580[72:MRR:539.0,139579.0] || -> until2p7(s45)* node4(s44). % 76.16/76.33 139581[73:Spt:139580.0] || -> until2p7(s45)*. % 76.16/76.33 139582[73:MRR:544.0,139581.0] || -> until2p7(s46)* node4(s45). % 76.16/76.33 139583[74:Spt:139582.0] || -> until2p7(s46)*. % 76.16/76.33 139584[74:MRR:549.0,139583.0] || -> until2p7(s47)* node4(s46). % 76.16/76.33 139585[75:Spt:139584.0] || -> until2p7(s47)*. % 76.16/76.33 139586[75:MRR:554.0,139585.0] || -> until2p7(s48)* node4(s47). % 76.16/76.33 139587[76:Spt:139586.0] || -> until2p7(s48)*. % 76.16/76.33 139588[76:MRR:559.0,139587.0] || -> until2p7(s49)* node4(s48). % 76.16/76.33 139589[77:Spt:139588.0] || -> until2p7(s49)*. % 76.16/76.33 139590[77:MRR:194.0,139589.0] || -> node4(s49)*. % 76.16/76.33 139591[77:MRR:139563.0,139590.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.33 139595[77:Res:53.1,139591.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.33 139597[77:MRR:139595.0,78381.0] || -> . % 76.16/76.33 139598[77:Spt:139597.0,139588.0,139589.0] || until2p7(s49)*+ -> . % 76.16/76.33 139599[77:Spt:139597.0,139588.1] || -> node4(s48)*. % 76.16/76.33 139600[77:MRR:78384.0,139599.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.33 139603[77:Res:53.1,139600.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.33 139606[77:Res:139603.0,61.1] always3(s48) || -> . % 76.16/76.33 139607[77:SSi:139606.0,78281.0,78387.0,137770.0,139587.0,139599.0] || -> . % 76.16/76.33 139608[76:Spt:139607.0,139586.0,139587.0] || until2p7(s48)*+ -> . % 76.16/76.33 139609[76:Spt:139607.0,139586.1] || -> node4(s47)*. % 76.16/76.33 139611[76:MRR:777.0,139609.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.33 139623[76:Res:53.1,139611.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.33 139625[77:Spt:139623.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.33 139627[77:Res:139625.0,61.1] always3(s47) || -> . % 76.16/76.33 139628[77:SSi:139627.0,78277.0,78280.0,137769.0,139585.0,139609.0] || -> . % 76.16/76.34 139629[77:Spt:139628.0,139623.0,139625.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 139630[77:Spt:139628.0,139623.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 139634[77:Res:139630.0,61.1] always3(s48) || -> . % 76.16/76.34 139635[77:SSi:139634.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 139636[75:Spt:139635.0,139584.0,139585.0] || until2p7(s47)*+ -> . % 76.16/76.34 139637[75:Spt:139635.0,139584.1] || -> node4(s46)*. % 76.16/76.34 139639[75:MRR:780.0,139637.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 139646[75:Res:53.1,139639.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 139651[76:Spt:139646.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 139653[76:Res:139651.0,61.1] always3(s46) || -> . % 76.16/76.34 139654[76:SSi:139653.0,78272.0,78276.0,137768.0,139583.0,139637.0] || -> . % 76.16/76.34 139655[76:Spt:139654.0,139646.0,139651.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 139656[76:Spt:139654.0,139646.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 139660[76:Res:139656.0,61.1] always3(s47) || -> . % 76.16/76.34 139661[76:SSi:139660.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 139662[74:Spt:139661.0,139582.0,139583.0] || until2p7(s46)*+ -> . % 76.16/76.34 139663[74:Spt:139661.0,139582.1] || -> node4(s45)*. % 76.16/76.34 139665[74:MRR:783.0,139663.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 139668[74:Res:53.1,139665.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 139670[75:Spt:139668.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 139672[75:Res:139670.0,61.1] always3(s45) || -> . % 76.16/76.34 139673[75:SSi:139672.0,78268.0,78271.0,137767.0,139581.0,139663.0] || -> . % 76.16/76.34 139674[75:Spt:139673.0,139668.0,139670.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 139675[75:Spt:139673.0,139668.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 139679[75:Res:139675.0,61.1] always3(s46) || -> . % 76.16/76.34 139680[75:SSi:139679.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 139681[73:Spt:139680.0,139580.0,139581.0] || until2p7(s45)*+ -> . % 76.16/76.34 139682[73:Spt:139680.0,139580.1] || -> node4(s44)*. % 76.16/76.34 139684[73:MRR:786.0,139682.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 139687[73:Res:53.1,139684.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 139689[74:Spt:139687.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 139691[74:Res:139689.0,61.1] always3(s44) || -> . % 76.16/76.34 139692[74:SSi:139691.0,78263.0,78267.0,137766.0,139579.0,139682.0] || -> . % 76.16/76.34 139693[74:Spt:139692.0,139687.0,139689.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 139694[74:Spt:139692.0,139687.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 139698[74:Res:139694.0,61.1] always3(s45) || -> . % 76.16/76.34 139699[74:SSi:139698.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 139700[72:Spt:139699.0,139578.0,139579.0] || until2p7(s44)*+ -> . % 76.16/76.34 139701[72:Spt:139699.0,139578.1] || -> node4(s43)*. % 76.16/76.34 139703[72:MRR:789.0,139701.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 139706[72:Res:53.1,139703.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 139708[73:Spt:139706.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 139710[73:Res:139708.0,61.1] always3(s43) || -> . % 76.16/76.34 139711[73:SSi:139710.0,78259.0,78262.0,137765.0,139577.0,139701.0] || -> . % 76.16/76.34 139712[73:Spt:139711.0,139706.0,139708.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 139713[73:Spt:139711.0,139706.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 139717[73:Res:139713.0,61.1] always3(s44) || -> . % 76.16/76.34 139718[73:SSi:139717.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 139719[71:Spt:139718.0,139576.0,139577.0] || until2p7(s43)*+ -> . % 76.16/76.34 139720[71:Spt:139718.0,139576.1] || -> node4(s42)*. % 76.16/76.34 139722[71:MRR:792.0,139720.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 139725[71:Res:53.1,139722.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 139730[72:Spt:139725.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 139732[72:Res:139730.0,61.1] always3(s42) || -> . % 76.16/76.34 139733[72:SSi:139732.0,78254.0,78258.0,137764.0,139575.0,139720.0] || -> . % 76.16/76.34 139734[72:Spt:139733.0,139725.0,139730.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 139735[72:Spt:139733.0,139725.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 139739[72:Res:139735.0,61.1] always3(s43) || -> . % 76.16/76.34 139740[72:SSi:139739.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 139741[70:Spt:139740.0,139574.0,139575.0] || until2p7(s42)*+ -> . % 76.16/76.34 139742[70:Spt:139740.0,139574.1] || -> node4(s41)*. % 76.16/76.34 139744[70:MRR:795.0,139742.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 139747[70:Res:53.1,139744.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 139749[71:Spt:139747.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 139751[71:Res:139749.0,61.1] always3(s41) || -> . % 76.16/76.34 139752[71:SSi:139751.0,78250.0,78253.0,137763.0,139573.0,139742.0] || -> . % 76.16/76.34 139753[71:Spt:139752.0,139747.0,139749.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 139754[71:Spt:139752.0,139747.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 139758[71:Res:139754.0,61.1] always3(s42) || -> . % 76.16/76.34 139759[71:SSi:139758.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 139760[69:Spt:139759.0,139572.0,139573.0] || until2p7(s41)*+ -> . % 76.16/76.34 139761[69:Spt:139759.0,139572.1] || -> node4(s40)*. % 76.16/76.34 139763[69:MRR:798.0,139761.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 139766[69:Res:53.1,139763.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 139768[70:Spt:139766.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 139770[70:Res:139768.0,61.1] always3(s40) || -> . % 76.16/76.34 139771[70:SSi:139770.0,78245.0,78249.0,137762.0,139571.0,139761.0] || -> . % 76.16/76.34 139772[70:Spt:139771.0,139766.0,139768.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 139773[70:Spt:139771.0,139766.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 139777[70:Res:139773.0,61.1] always3(s41) || -> . % 76.16/76.34 139778[70:SSi:139777.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 139779[68:Spt:139778.0,139570.0,139571.0] || until2p7(s40)*+ -> . % 76.16/76.34 139780[68:Spt:139778.0,139570.1] || -> node4(s39)*. % 76.16/76.34 139782[68:MRR:801.0,139780.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 139785[68:Res:53.1,139782.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 139787[69:Spt:139785.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 139789[69:Res:139787.0,61.1] always3(s39) || -> . % 76.16/76.34 139790[69:SSi:139789.0,78241.0,78244.0,137761.0,139569.0,139780.0] || -> . % 76.16/76.34 139791[69:Spt:139790.0,139785.0,139787.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 139792[69:Spt:139790.0,139785.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 139796[69:Res:139792.0,61.1] always3(s40) || -> . % 76.16/76.34 139797[69:SSi:139796.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 139798[67:Spt:139797.0,139568.0,139569.0] || until2p7(s39)*+ -> . % 76.16/76.34 139799[67:Spt:139797.0,139568.1] || -> node4(s38)*. % 76.16/76.34 139801[67:MRR:804.0,139799.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 139804[67:Res:53.1,139801.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 139806[67:MRR:139804.0,139558.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 139811[67:Res:139806.0,61.1] always3(s39) || -> . % 76.16/76.34 139812[67:SSi:139811.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 139813[65:Spt:139812.0,139504.0,139507.0] || trans(s49,s38)*+ -> . % 76.16/76.34 139814[65:Spt:139812.0,139504.1,139504.2,139504.3,139504.4,139504.5,139504.6,139504.7,139504.8,139504.9,139504.10,139504.11,139504.12,139504.13,139504.14,139504.15,139504.16,139504.17,139504.18,139504.19,139504.20,139504.21,139504.22,139504.23,139504.24,139504.25,139504.26,139504.27,139504.28,139504.29,139504.30,139504.31,139504.32,139504.33,139504.34] || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 139816[65:MRR:139506.1,139813.0] xuntil6(s49) || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 139817[66:Spt:139814.0] || -> trans(s49,s37)*. % 76.16/76.34 139818[66:Res:139817.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s37)*. % 76.16/76.34 139820[66:Res:139817.0,60.0] || -> node2(s49,s37)*. % 76.16/76.34 139821[66:SSi:139818.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s37)*. % 76.16/76.34 139822[66:Res:139820.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 139864[66:SoR:139822.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 139866[66:SoR:139864.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)* xuntil6(s49). % 76.16/76.34 139867[66:SSi:139866.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s37,c_busy)* xuntil6(s49). % 76.16/76.34 139868[67:Spt:139867.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 139870[67:Res:139868.0,61.1] always3(s37) || -> . % 76.16/76.34 139871[67:SSi:139870.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 139872[67:Spt:139871.0,139867.1,139868.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.16/76.34 139873[67:Spt:139871.0,139867.0,139867.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 139877[67:MRR:139864.2,139872.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 139878[67:Res:53.1,139873.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 139880[67:MRR:139878.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 139881[67:MRR:139821.0,139880.0] || -> until2p7(s37)*. % 76.16/76.34 139882[67:MRR:235.0,139881.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 139883[68:Spt:139882.0] || -> until2p7(s38)*. % 76.16/76.34 139884[68:MRR:236.0,139883.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 139885[69:Spt:139884.0] || -> until2p7(s39)*. % 76.16/76.34 139886[69:MRR:237.0,139885.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 139887[70:Spt:139886.0] || -> until2p7(s40)*. % 76.16/76.34 139888[70:MRR:238.0,139887.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 139889[71:Spt:139888.0] || -> until2p7(s41)*. % 76.16/76.34 139890[71:MRR:239.0,139889.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 139891[72:Spt:139890.0] || -> until2p7(s42)*. % 76.16/76.34 139892[72:MRR:240.0,139891.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 139893[73:Spt:139892.0] || -> until2p7(s43)*. % 76.16/76.34 139894[73:MRR:241.0,139893.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 139895[74:Spt:139894.0] || -> until2p7(s44)*. % 76.16/76.34 139896[74:MRR:539.0,139895.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 139897[75:Spt:139896.0] || -> until2p7(s45)*. % 76.16/76.34 139898[75:MRR:544.0,139897.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 139899[76:Spt:139898.0] || -> until2p7(s46)*. % 76.16/76.34 139900[76:MRR:549.0,139899.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 139901[77:Spt:139900.0] || -> until2p7(s47)*. % 76.16/76.34 139902[77:MRR:554.0,139901.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 139903[78:Spt:139902.0] || -> until2p7(s48)*. % 76.16/76.34 139904[78:MRR:559.0,139903.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 139905[79:Spt:139904.0] || -> until2p7(s49)*. % 76.16/76.34 139906[79:MRR:194.0,139905.0] || -> node4(s49)*. % 76.16/76.34 139907[79:MRR:139877.0,139906.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 139908[79:Res:53.1,139907.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 139910[79:MRR:139908.0,78381.0] || -> . % 76.16/76.34 139911[79:Spt:139910.0,139904.0,139905.0] || until2p7(s49)*+ -> . % 76.16/76.34 139912[79:Spt:139910.0,139904.1] || -> node4(s48)*. % 76.16/76.34 139913[79:MRR:78384.0,139912.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 139916[79:Res:53.1,139913.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 139919[79:Res:139916.0,61.1] always3(s48) || -> . % 76.16/76.34 139920[79:SSi:139919.0,78281.0,78387.0,137770.0,139903.0,139912.0] || -> . % 76.16/76.34 139921[78:Spt:139920.0,139902.0,139903.0] || until2p7(s48)*+ -> . % 76.16/76.34 139922[78:Spt:139920.0,139902.1] || -> node4(s47)*. % 76.16/76.34 139924[78:MRR:777.0,139922.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 139939[78:Res:53.1,139924.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 139944[79:Spt:139939.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 139946[79:Res:139944.0,61.1] always3(s47) || -> . % 76.16/76.34 139947[79:SSi:139946.0,78277.0,78280.0,137769.0,139901.0,139922.0] || -> . % 76.16/76.34 139948[79:Spt:139947.0,139939.0,139944.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 139949[79:Spt:139947.0,139939.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 139953[79:Res:139949.0,61.1] always3(s48) || -> . % 76.16/76.34 139954[79:SSi:139953.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 139955[77:Spt:139954.0,139900.0,139901.0] || until2p7(s47)*+ -> . % 76.16/76.34 139956[77:Spt:139954.0,139900.1] || -> node4(s46)*. % 76.16/76.34 139958[77:MRR:780.0,139956.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 139965[77:Res:53.1,139958.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 139967[78:Spt:139965.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 139969[78:Res:139967.0,61.1] always3(s46) || -> . % 76.16/76.34 139970[78:SSi:139969.0,78272.0,78276.0,137768.0,139899.0,139956.0] || -> . % 76.16/76.34 139971[78:Spt:139970.0,139965.0,139967.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 139972[78:Spt:139970.0,139965.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 139976[78:Res:139972.0,61.1] always3(s47) || -> . % 76.16/76.34 139977[78:SSi:139976.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 139978[76:Spt:139977.0,139898.0,139899.0] || until2p7(s46)*+ -> . % 76.16/76.34 139979[76:Spt:139977.0,139898.1] || -> node4(s45)*. % 76.16/76.34 139981[76:MRR:783.0,139979.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 139984[76:Res:53.1,139981.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 139989[77:Spt:139984.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 139991[77:Res:139989.0,61.1] always3(s45) || -> . % 76.16/76.34 139992[77:SSi:139991.0,78268.0,78271.0,137767.0,139897.0,139979.0] || -> . % 76.16/76.34 139993[77:Spt:139992.0,139984.0,139989.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 139994[77:Spt:139992.0,139984.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 139998[77:Res:139994.0,61.1] always3(s46) || -> . % 76.16/76.34 139999[77:SSi:139998.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 140000[75:Spt:139999.0,139896.0,139897.0] || until2p7(s45)*+ -> . % 76.16/76.34 140001[75:Spt:139999.0,139896.1] || -> node4(s44)*. % 76.16/76.34 140003[75:MRR:786.0,140001.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 140006[75:Res:53.1,140003.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 140008[76:Spt:140006.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 140010[76:Res:140008.0,61.1] always3(s44) || -> . % 76.16/76.34 140011[76:SSi:140010.0,78263.0,78267.0,137766.0,139895.0,140001.0] || -> . % 76.16/76.34 140012[76:Spt:140011.0,140006.0,140008.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 140013[76:Spt:140011.0,140006.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 140017[76:Res:140013.0,61.1] always3(s45) || -> . % 76.16/76.34 140018[76:SSi:140017.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 140019[74:Spt:140018.0,139894.0,139895.0] || until2p7(s44)*+ -> . % 76.16/76.34 140020[74:Spt:140018.0,139894.1] || -> node4(s43)*. % 76.16/76.34 140022[74:MRR:789.0,140020.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 140025[74:Res:53.1,140022.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 140027[75:Spt:140025.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 140029[75:Res:140027.0,61.1] always3(s43) || -> . % 76.16/76.34 140030[75:SSi:140029.0,78259.0,78262.0,137765.0,139893.0,140020.0] || -> . % 76.16/76.34 140031[75:Spt:140030.0,140025.0,140027.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 140032[75:Spt:140030.0,140025.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 140036[75:Res:140032.0,61.1] always3(s44) || -> . % 76.16/76.34 140037[75:SSi:140036.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 140038[73:Spt:140037.0,139892.0,139893.0] || until2p7(s43)*+ -> . % 76.16/76.34 140039[73:Spt:140037.0,139892.1] || -> node4(s42)*. % 76.16/76.34 140041[73:MRR:792.0,140039.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 140044[73:Res:53.1,140041.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 140046[74:Spt:140044.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 140048[74:Res:140046.0,61.1] always3(s42) || -> . % 76.16/76.34 140049[74:SSi:140048.0,78254.0,78258.0,137764.0,139891.0,140039.0] || -> . % 76.16/76.34 140050[74:Spt:140049.0,140044.0,140046.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 140051[74:Spt:140049.0,140044.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 140055[74:Res:140051.0,61.1] always3(s43) || -> . % 76.16/76.34 140056[74:SSi:140055.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 140057[72:Spt:140056.0,139890.0,139891.0] || until2p7(s42)*+ -> . % 76.16/76.34 140058[72:Spt:140056.0,139890.1] || -> node4(s41)*. % 76.16/76.34 140060[72:MRR:795.0,140058.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 140063[72:Res:53.1,140060.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 140068[73:Spt:140063.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 140070[73:Res:140068.0,61.1] always3(s41) || -> . % 76.16/76.34 140071[73:SSi:140070.0,78250.0,78253.0,137763.0,139889.0,140058.0] || -> . % 76.16/76.34 140072[73:Spt:140071.0,140063.0,140068.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 140073[73:Spt:140071.0,140063.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 140077[73:Res:140073.0,61.1] always3(s42) || -> . % 76.16/76.34 140078[73:SSi:140077.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 140079[71:Spt:140078.0,139888.0,139889.0] || until2p7(s41)*+ -> . % 76.16/76.34 140080[71:Spt:140078.0,139888.1] || -> node4(s40)*. % 76.16/76.34 140082[71:MRR:798.0,140080.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 140085[71:Res:53.1,140082.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 140087[72:Spt:140085.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 140089[72:Res:140087.0,61.1] always3(s40) || -> . % 76.16/76.34 140090[72:SSi:140089.0,78245.0,78249.0,137762.0,139887.0,140080.0] || -> . % 76.16/76.34 140091[72:Spt:140090.0,140085.0,140087.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 140092[72:Spt:140090.0,140085.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 140096[72:Res:140092.0,61.1] always3(s41) || -> . % 76.16/76.34 140097[72:SSi:140096.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 140098[70:Spt:140097.0,139886.0,139887.0] || until2p7(s40)*+ -> . % 76.16/76.34 140099[70:Spt:140097.0,139886.1] || -> node4(s39)*. % 76.16/76.34 140101[70:MRR:801.0,140099.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 140104[70:Res:53.1,140101.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 140106[71:Spt:140104.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 140108[71:Res:140106.0,61.1] always3(s39) || -> . % 76.16/76.34 140109[71:SSi:140108.0,78241.0,78244.0,137761.0,139885.0,140099.0] || -> . % 76.16/76.34 140110[71:Spt:140109.0,140104.0,140106.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 140111[71:Spt:140109.0,140104.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 140115[71:Res:140111.0,61.1] always3(s40) || -> . % 76.16/76.34 140116[71:SSi:140115.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 140117[69:Spt:140116.0,139884.0,139885.0] || until2p7(s39)*+ -> . % 76.16/76.34 140118[69:Spt:140116.0,139884.1] || -> node4(s38)*. % 76.16/76.34 140120[69:MRR:804.0,140118.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 140123[69:Res:53.1,140120.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 140125[70:Spt:140123.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 140127[70:Res:140125.0,61.1] always3(s38) || -> . % 76.16/76.34 140128[70:SSi:140127.0,78236.0,78240.0,137760.0,139883.0,140118.0] || -> . % 76.16/76.34 140129[70:Spt:140128.0,140123.0,140125.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 140130[70:Spt:140128.0,140123.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 140134[70:Res:140130.0,61.1] always3(s39) || -> . % 76.16/76.34 140135[70:SSi:140134.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 140136[68:Spt:140135.0,139882.0,139883.0] || until2p7(s38)*+ -> . % 76.16/76.34 140137[68:Spt:140135.0,139882.1] || -> node4(s37)*. % 76.16/76.34 140139[68:MRR:807.0,140137.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 140142[68:Res:53.1,140139.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 140144[68:MRR:140142.0,139872.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 140149[68:Res:140144.0,61.1] always3(s38) || -> . % 76.16/76.34 140150[68:SSi:140149.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 140151[66:Spt:140150.0,139814.0,139817.0] || trans(s49,s37)*+ -> . % 76.16/76.34 140152[66:Spt:140150.0,139814.1,139814.2,139814.3,139814.4,139814.5,139814.6,139814.7,139814.8,139814.9,139814.10,139814.11,139814.12,139814.13,139814.14,139814.15,139814.16,139814.17,139814.18,139814.19,139814.20,139814.21,139814.22,139814.23,139814.24,139814.25,139814.26,139814.27,139814.28,139814.29,139814.30,139814.31,139814.32,139814.33] || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 140154[66:MRR:139816.1,140151.0] xuntil6(s49) || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 140155[67:Spt:140152.0] || -> trans(s49,s36)*. % 76.16/76.34 140156[67:Res:140155.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s36)*. % 76.16/76.34 140158[67:Res:140155.0,60.0] || -> node2(s49,s36)*. % 76.16/76.34 140159[67:SSi:140156.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s36)*. % 76.16/76.34 140160[67:Res:140158.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 140203[67:SoR:140160.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 140205[67:SoR:140203.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)* xuntil6(s49). % 76.16/76.34 140206[67:SSi:140205.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s36,c_busy)* xuntil6(s49). % 76.16/76.34 140207[68:Spt:140206.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 140209[68:Res:140207.0,61.1] always3(s36) || -> . % 76.16/76.34 140210[68:SSi:140209.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 140211[68:Spt:140210.0,140206.1,140207.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.16/76.34 140212[68:Spt:140210.0,140206.0,140206.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 140216[68:MRR:140203.2,140211.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 140217[68:Res:53.1,140212.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 140219[68:MRR:140217.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 140220[68:MRR:140159.0,140219.0] || -> until2p7(s36)*. % 76.16/76.34 140221[68:MRR:232.0,140220.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 140222[69:Spt:140221.0] || -> until2p7(s37)*. % 76.16/76.34 140223[69:MRR:235.0,140222.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 140224[70:Spt:140223.0] || -> until2p7(s38)*. % 76.16/76.34 140225[70:MRR:236.0,140224.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 140226[71:Spt:140225.0] || -> until2p7(s39)*. % 76.16/76.34 140227[71:MRR:237.0,140226.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 140228[72:Spt:140227.0] || -> until2p7(s40)*. % 76.16/76.34 140229[72:MRR:238.0,140228.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 140230[73:Spt:140229.0] || -> until2p7(s41)*. % 76.16/76.34 140231[73:MRR:239.0,140230.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 140232[74:Spt:140231.0] || -> until2p7(s42)*. % 76.16/76.34 140233[74:MRR:240.0,140232.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 140234[75:Spt:140233.0] || -> until2p7(s43)*. % 76.16/76.34 140235[75:MRR:241.0,140234.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 140236[76:Spt:140235.0] || -> until2p7(s44)*. % 76.16/76.34 140237[76:MRR:539.0,140236.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 140238[77:Spt:140237.0] || -> until2p7(s45)*. % 76.16/76.34 140239[77:MRR:544.0,140238.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 140240[78:Spt:140239.0] || -> until2p7(s46)*. % 76.16/76.34 140241[78:MRR:549.0,140240.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 140242[79:Spt:140241.0] || -> until2p7(s47)*. % 76.16/76.34 140243[79:MRR:554.0,140242.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 140244[80:Spt:140243.0] || -> until2p7(s48)*. % 76.16/76.34 140245[80:MRR:559.0,140244.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 140246[81:Spt:140245.0] || -> until2p7(s49)*. % 76.16/76.34 140247[81:MRR:194.0,140246.0] || -> node4(s49)*. % 76.16/76.34 140248[81:MRR:140216.0,140247.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 140252[81:Res:53.1,140248.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 140254[81:MRR:140252.0,78381.0] || -> . % 76.16/76.34 140255[81:Spt:140254.0,140245.0,140246.0] || until2p7(s49)*+ -> . % 76.16/76.34 140256[81:Spt:140254.0,140245.1] || -> node4(s48)*. % 76.16/76.34 140257[81:MRR:78384.0,140256.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 140260[81:Res:53.1,140257.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 140263[81:Res:140260.0,61.1] always3(s48) || -> . % 76.16/76.34 140264[81:SSi:140263.0,78281.0,78387.0,137770.0,140244.0,140256.0] || -> . % 76.16/76.34 140265[80:Spt:140264.0,140243.0,140244.0] || until2p7(s48)*+ -> . % 76.16/76.34 140266[80:Spt:140264.0,140243.1] || -> node4(s47)*. % 76.16/76.34 140268[80:MRR:777.0,140266.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 140280[80:Res:53.1,140268.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 140282[81:Spt:140280.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 140284[81:Res:140282.0,61.1] always3(s47) || -> . % 76.16/76.34 140285[81:SSi:140284.0,78277.0,78280.0,137769.0,140242.0,140266.0] || -> . % 76.16/76.34 140286[81:Spt:140285.0,140280.0,140282.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 140287[81:Spt:140285.0,140280.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 140291[81:Res:140287.0,61.1] always3(s48) || -> . % 76.16/76.34 140292[81:SSi:140291.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 140293[79:Spt:140292.0,140241.0,140242.0] || until2p7(s47)*+ -> . % 76.16/76.34 140294[79:Spt:140292.0,140241.1] || -> node4(s46)*. % 76.16/76.34 140296[79:MRR:780.0,140294.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 140303[79:Res:53.1,140296.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 140308[80:Spt:140303.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 140310[80:Res:140308.0,61.1] always3(s46) || -> . % 76.16/76.34 140311[80:SSi:140310.0,78272.0,78276.0,137768.0,140240.0,140294.0] || -> . % 76.16/76.34 140312[80:Spt:140311.0,140303.0,140308.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 140313[80:Spt:140311.0,140303.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 140317[80:Res:140313.0,61.1] always3(s47) || -> . % 76.16/76.34 140318[80:SSi:140317.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 140319[78:Spt:140318.0,140239.0,140240.0] || until2p7(s46)*+ -> . % 76.16/76.34 140320[78:Spt:140318.0,140239.1] || -> node4(s45)*. % 76.16/76.34 140322[78:MRR:783.0,140320.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 140325[78:Res:53.1,140322.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 140327[79:Spt:140325.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 140329[79:Res:140327.0,61.1] always3(s45) || -> . % 76.16/76.34 140330[79:SSi:140329.0,78268.0,78271.0,137767.0,140238.0,140320.0] || -> . % 76.16/76.34 140331[79:Spt:140330.0,140325.0,140327.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 140332[79:Spt:140330.0,140325.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 140336[79:Res:140332.0,61.1] always3(s46) || -> . % 76.16/76.34 140337[79:SSi:140336.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 140338[77:Spt:140337.0,140237.0,140238.0] || until2p7(s45)*+ -> . % 76.16/76.34 140339[77:Spt:140337.0,140237.1] || -> node4(s44)*. % 76.16/76.34 140341[77:MRR:786.0,140339.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 140344[77:Res:53.1,140341.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 140346[78:Spt:140344.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 140348[78:Res:140346.0,61.1] always3(s44) || -> . % 76.16/76.34 140349[78:SSi:140348.0,78263.0,78267.0,137766.0,140236.0,140339.0] || -> . % 76.16/76.34 140350[78:Spt:140349.0,140344.0,140346.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 140351[78:Spt:140349.0,140344.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 140355[78:Res:140351.0,61.1] always3(s45) || -> . % 76.16/76.34 140356[78:SSi:140355.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 140357[76:Spt:140356.0,140235.0,140236.0] || until2p7(s44)*+ -> . % 76.16/76.34 140358[76:Spt:140356.0,140235.1] || -> node4(s43)*. % 76.16/76.34 140360[76:MRR:789.0,140358.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 140363[76:Res:53.1,140360.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 140365[77:Spt:140363.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 140367[77:Res:140365.0,61.1] always3(s43) || -> . % 76.16/76.34 140368[77:SSi:140367.0,78259.0,78262.0,137765.0,140234.0,140358.0] || -> . % 76.16/76.34 140369[77:Spt:140368.0,140363.0,140365.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 140370[77:Spt:140368.0,140363.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 140374[77:Res:140370.0,61.1] always3(s44) || -> . % 76.16/76.34 140375[77:SSi:140374.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 140376[75:Spt:140375.0,140233.0,140234.0] || until2p7(s43)*+ -> . % 76.16/76.34 140377[75:Spt:140375.0,140233.1] || -> node4(s42)*. % 76.16/76.34 140379[75:MRR:792.0,140377.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 140382[75:Res:53.1,140379.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 140387[76:Spt:140382.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 140389[76:Res:140387.0,61.1] always3(s42) || -> . % 76.16/76.34 140390[76:SSi:140389.0,78254.0,78258.0,137764.0,140232.0,140377.0] || -> . % 76.16/76.34 140391[76:Spt:140390.0,140382.0,140387.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 140392[76:Spt:140390.0,140382.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 140396[76:Res:140392.0,61.1] always3(s43) || -> . % 76.16/76.34 140397[76:SSi:140396.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 140398[74:Spt:140397.0,140231.0,140232.0] || until2p7(s42)*+ -> . % 76.16/76.34 140399[74:Spt:140397.0,140231.1] || -> node4(s41)*. % 76.16/76.34 140401[74:MRR:795.0,140399.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 140404[74:Res:53.1,140401.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 140406[75:Spt:140404.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 140408[75:Res:140406.0,61.1] always3(s41) || -> . % 76.16/76.34 140409[75:SSi:140408.0,78250.0,78253.0,137763.0,140230.0,140399.0] || -> . % 76.16/76.34 140410[75:Spt:140409.0,140404.0,140406.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 140411[75:Spt:140409.0,140404.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 140415[75:Res:140411.0,61.1] always3(s42) || -> . % 76.16/76.34 140416[75:SSi:140415.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 140417[73:Spt:140416.0,140229.0,140230.0] || until2p7(s41)*+ -> . % 76.16/76.34 140418[73:Spt:140416.0,140229.1] || -> node4(s40)*. % 76.16/76.34 140420[73:MRR:798.0,140418.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 140423[73:Res:53.1,140420.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 140425[74:Spt:140423.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 140427[74:Res:140425.0,61.1] always3(s40) || -> . % 76.16/76.34 140428[74:SSi:140427.0,78245.0,78249.0,137762.0,140228.0,140418.0] || -> . % 76.16/76.34 140429[74:Spt:140428.0,140423.0,140425.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 140430[74:Spt:140428.0,140423.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 140434[74:Res:140430.0,61.1] always3(s41) || -> . % 76.16/76.34 140435[74:SSi:140434.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 140436[72:Spt:140435.0,140227.0,140228.0] || until2p7(s40)*+ -> . % 76.16/76.34 140437[72:Spt:140435.0,140227.1] || -> node4(s39)*. % 76.16/76.34 140439[72:MRR:801.0,140437.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 140442[72:Res:53.1,140439.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 140444[73:Spt:140442.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 140446[73:Res:140444.0,61.1] always3(s39) || -> . % 76.16/76.34 140447[73:SSi:140446.0,78241.0,78244.0,137761.0,140226.0,140437.0] || -> . % 76.16/76.34 140448[73:Spt:140447.0,140442.0,140444.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 140449[73:Spt:140447.0,140442.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 140453[73:Res:140449.0,61.1] always3(s40) || -> . % 76.16/76.34 140454[73:SSi:140453.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 140455[71:Spt:140454.0,140225.0,140226.0] || until2p7(s39)*+ -> . % 76.16/76.34 140456[71:Spt:140454.0,140225.1] || -> node4(s38)*. % 76.16/76.34 140458[71:MRR:804.0,140456.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 140461[71:Res:53.1,140458.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 140466[72:Spt:140461.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 140468[72:Res:140466.0,61.1] always3(s38) || -> . % 76.16/76.34 140469[72:SSi:140468.0,78236.0,78240.0,137760.0,140224.0,140456.0] || -> . % 76.16/76.34 140470[72:Spt:140469.0,140461.0,140466.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 140471[72:Spt:140469.0,140461.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 140475[72:Res:140471.0,61.1] always3(s39) || -> . % 76.16/76.34 140476[72:SSi:140475.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 140477[70:Spt:140476.0,140223.0,140224.0] || until2p7(s38)*+ -> . % 76.16/76.34 140478[70:Spt:140476.0,140223.1] || -> node4(s37)*. % 76.16/76.34 140480[70:MRR:807.0,140478.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 140483[70:Res:53.1,140480.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 140485[71:Spt:140483.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 140487[71:Res:140485.0,61.1] always3(s37) || -> . % 76.16/76.34 140488[71:SSi:140487.0,78232.0,78235.0,137759.0,140222.0,140478.0] || -> . % 76.16/76.34 140489[71:Spt:140488.0,140483.0,140485.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 140490[71:Spt:140488.0,140483.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 140494[71:Res:140490.0,61.1] always3(s38) || -> . % 76.16/76.34 140495[71:SSi:140494.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 140496[69:Spt:140495.0,140221.0,140222.0] || until2p7(s37)*+ -> . % 76.16/76.34 140497[69:Spt:140495.0,140221.1] || -> node4(s36)*. % 76.16/76.34 140499[69:MRR:810.0,140497.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 140502[69:Res:53.1,140499.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 140504[69:MRR:140502.0,140211.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 140506[69:Res:140504.0,61.1] always3(s37) || -> . % 76.16/76.34 140507[69:SSi:140506.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 140508[67:Spt:140507.0,140152.0,140155.0] || trans(s49,s36)*+ -> . % 76.16/76.34 140509[67:Spt:140507.0,140152.1,140152.2,140152.3,140152.4,140152.5,140152.6,140152.7,140152.8,140152.9,140152.10,140152.11,140152.12,140152.13,140152.14,140152.15,140152.16,140152.17,140152.18,140152.19,140152.20,140152.21,140152.22,140152.23,140152.24,140152.25,140152.26,140152.27,140152.28,140152.29,140152.30,140152.31,140152.32] || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 140511[67:MRR:140154.1,140508.0] xuntil6(s49) || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 140512[68:Spt:140509.0] || -> trans(s49,s35)*. % 76.16/76.34 140513[68:Res:140512.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s35)*. % 76.16/76.34 140515[68:Res:140512.0,60.0] || -> node2(s49,s35)*. % 76.16/76.34 140516[68:SSi:140513.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s35)*. % 76.16/76.34 140517[68:Res:140515.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 140567[68:SoR:140517.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 140569[68:SoR:140567.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 76.16/76.34 140570[68:SSi:140569.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 76.16/76.34 140571[69:Spt:140570.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 140573[69:Res:140571.0,61.1] always3(s35) || -> . % 76.16/76.34 140574[69:SSi:140573.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 140575[69:Spt:140574.0,140570.1,140571.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.16/76.34 140576[69:Spt:140574.0,140570.0,140570.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 140580[69:MRR:140567.2,140575.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 140581[69:Res:53.1,140576.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 140583[69:MRR:140581.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 140584[69:MRR:140516.0,140583.0] || -> until2p7(s35)*. % 76.16/76.34 140585[69:MRR:231.0,140584.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 140586[70:Spt:140585.0] || -> until2p7(s36)*. % 76.16/76.34 140587[70:MRR:232.0,140586.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 140588[71:Spt:140587.0] || -> until2p7(s37)*. % 76.16/76.34 140589[71:MRR:235.0,140588.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 140590[72:Spt:140589.0] || -> until2p7(s38)*. % 76.16/76.34 140591[72:MRR:236.0,140590.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 140592[73:Spt:140591.0] || -> until2p7(s39)*. % 76.16/76.34 140593[73:MRR:237.0,140592.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 140594[74:Spt:140593.0] || -> until2p7(s40)*. % 76.16/76.34 140595[74:MRR:238.0,140594.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 140596[75:Spt:140595.0] || -> until2p7(s41)*. % 76.16/76.34 140597[75:MRR:239.0,140596.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 140598[76:Spt:140597.0] || -> until2p7(s42)*. % 76.16/76.34 140599[76:MRR:240.0,140598.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 140600[77:Spt:140599.0] || -> until2p7(s43)*. % 76.16/76.34 140601[77:MRR:241.0,140600.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 140602[78:Spt:140601.0] || -> until2p7(s44)*. % 76.16/76.34 140603[78:MRR:539.0,140602.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 140604[79:Spt:140603.0] || -> until2p7(s45)*. % 76.16/76.34 140605[79:MRR:544.0,140604.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 140606[80:Spt:140605.0] || -> until2p7(s46)*. % 76.16/76.34 140607[80:MRR:549.0,140606.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 140608[81:Spt:140607.0] || -> until2p7(s47)*. % 76.16/76.34 140609[81:MRR:554.0,140608.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 140610[82:Spt:140609.0] || -> until2p7(s48)*. % 76.16/76.34 140611[82:MRR:559.0,140610.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 140612[83:Spt:140611.0] || -> until2p7(s49)*. % 76.16/76.34 140613[83:MRR:194.0,140612.0] || -> node4(s49)*. % 76.16/76.34 140614[83:MRR:140580.0,140613.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 140615[83:Res:53.1,140614.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 140617[83:MRR:140615.0,78381.0] || -> . % 76.16/76.34 140618[83:Spt:140617.0,140611.0,140612.0] || until2p7(s49)*+ -> . % 76.16/76.34 140619[83:Spt:140617.0,140611.1] || -> node4(s48)*. % 76.16/76.34 140620[83:MRR:78384.0,140619.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 140623[83:Res:53.1,140620.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 140626[83:Res:140623.0,61.1] always3(s48) || -> . % 76.16/76.34 140627[83:SSi:140626.0,78281.0,78387.0,137770.0,140610.0,140619.0] || -> . % 76.16/76.34 140628[82:Spt:140627.0,140609.0,140610.0] || until2p7(s48)*+ -> . % 76.16/76.34 140629[82:Spt:140627.0,140609.1] || -> node4(s47)*. % 76.16/76.34 140631[82:MRR:777.0,140629.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 140646[82:Res:53.1,140631.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 140648[83:Spt:140646.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 140650[83:Res:140648.0,61.1] always3(s47) || -> . % 76.16/76.34 140651[83:SSi:140650.0,78277.0,78280.0,137769.0,140608.0,140629.0] || -> . % 76.16/76.34 140652[83:Spt:140651.0,140646.0,140648.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 140653[83:Spt:140651.0,140646.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 140657[83:Res:140653.0,61.1] always3(s48) || -> . % 76.16/76.34 140658[83:SSi:140657.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 140659[81:Spt:140658.0,140607.0,140608.0] || until2p7(s47)*+ -> . % 76.16/76.34 140660[81:Spt:140658.0,140607.1] || -> node4(s46)*. % 76.16/76.34 140662[81:MRR:780.0,140660.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 140672[81:Res:53.1,140662.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 140674[82:Spt:140672.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 140676[82:Res:140674.0,61.1] always3(s46) || -> . % 76.16/76.34 140677[82:SSi:140676.0,78272.0,78276.0,137768.0,140606.0,140660.0] || -> . % 76.16/76.34 140678[82:Spt:140677.0,140672.0,140674.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 140679[82:Spt:140677.0,140672.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 140683[82:Res:140679.0,61.1] always3(s47) || -> . % 76.16/76.34 140684[82:SSi:140683.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 140685[80:Spt:140684.0,140605.0,140606.0] || until2p7(s46)*+ -> . % 76.16/76.34 140686[80:Spt:140684.0,140605.1] || -> node4(s45)*. % 76.16/76.34 140688[80:MRR:783.0,140686.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 140691[80:Res:53.1,140688.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 140693[81:Spt:140691.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 140695[81:Res:140693.0,61.1] always3(s45) || -> . % 76.16/76.34 140696[81:SSi:140695.0,78268.0,78271.0,137767.0,140604.0,140686.0] || -> . % 76.16/76.34 140697[81:Spt:140696.0,140691.0,140693.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 140698[81:Spt:140696.0,140691.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 140702[81:Res:140698.0,61.1] always3(s46) || -> . % 76.16/76.34 140703[81:SSi:140702.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 140704[79:Spt:140703.0,140603.0,140604.0] || until2p7(s45)*+ -> . % 76.16/76.34 140705[79:Spt:140703.0,140603.1] || -> node4(s44)*. % 76.16/76.34 140707[79:MRR:786.0,140705.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 140710[79:Res:53.1,140707.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 140712[80:Spt:140710.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 140714[80:Res:140712.0,61.1] always3(s44) || -> . % 76.16/76.34 140715[80:SSi:140714.0,78263.0,78267.0,137766.0,140602.0,140705.0] || -> . % 76.16/76.34 140716[80:Spt:140715.0,140710.0,140712.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 140717[80:Spt:140715.0,140710.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 140721[80:Res:140717.0,61.1] always3(s45) || -> . % 76.16/76.34 140722[80:SSi:140721.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 140723[78:Spt:140722.0,140601.0,140602.0] || until2p7(s44)*+ -> . % 76.16/76.34 140724[78:Spt:140722.0,140601.1] || -> node4(s43)*. % 76.16/76.34 140726[78:MRR:789.0,140724.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 140729[78:Res:53.1,140726.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 140734[79:Spt:140729.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 140736[79:Res:140734.0,61.1] always3(s43) || -> . % 76.16/76.34 140737[79:SSi:140736.0,78259.0,78262.0,137765.0,140600.0,140724.0] || -> . % 76.16/76.34 140738[79:Spt:140737.0,140729.0,140734.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 140739[79:Spt:140737.0,140729.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 140743[79:Res:140739.0,61.1] always3(s44) || -> . % 76.16/76.34 140744[79:SSi:140743.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 140745[77:Spt:140744.0,140599.0,140600.0] || until2p7(s43)*+ -> . % 76.16/76.34 140746[77:Spt:140744.0,140599.1] || -> node4(s42)*. % 76.16/76.34 140748[77:MRR:792.0,140746.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 140751[77:Res:53.1,140748.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 140753[78:Spt:140751.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 140755[78:Res:140753.0,61.1] always3(s42) || -> . % 76.16/76.34 140756[78:SSi:140755.0,78254.0,78258.0,137764.0,140598.0,140746.0] || -> . % 76.16/76.34 140757[78:Spt:140756.0,140751.0,140753.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 140758[78:Spt:140756.0,140751.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 140762[78:Res:140758.0,61.1] always3(s43) || -> . % 76.16/76.34 140763[78:SSi:140762.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 140764[76:Spt:140763.0,140597.0,140598.0] || until2p7(s42)*+ -> . % 76.16/76.34 140765[76:Spt:140763.0,140597.1] || -> node4(s41)*. % 76.16/76.34 140767[76:MRR:795.0,140765.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 140770[76:Res:53.1,140767.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 140772[77:Spt:140770.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 140774[77:Res:140772.0,61.1] always3(s41) || -> . % 76.16/76.34 140775[77:SSi:140774.0,78250.0,78253.0,137763.0,140596.0,140765.0] || -> . % 76.16/76.34 140776[77:Spt:140775.0,140770.0,140772.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 140777[77:Spt:140775.0,140770.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 140781[77:Res:140777.0,61.1] always3(s42) || -> . % 76.16/76.34 140782[77:SSi:140781.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 140783[75:Spt:140782.0,140595.0,140596.0] || until2p7(s41)*+ -> . % 76.16/76.34 140784[75:Spt:140782.0,140595.1] || -> node4(s40)*. % 76.16/76.34 140786[75:MRR:798.0,140784.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 140789[75:Res:53.1,140786.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 140791[76:Spt:140789.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 140793[76:Res:140791.0,61.1] always3(s40) || -> . % 76.16/76.34 140794[76:SSi:140793.0,78245.0,78249.0,137762.0,140594.0,140784.0] || -> . % 76.16/76.34 140795[76:Spt:140794.0,140789.0,140791.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 140796[76:Spt:140794.0,140789.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 140800[76:Res:140796.0,61.1] always3(s41) || -> . % 76.16/76.34 140801[76:SSi:140800.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 140802[74:Spt:140801.0,140593.0,140594.0] || until2p7(s40)*+ -> . % 76.16/76.34 140803[74:Spt:140801.0,140593.1] || -> node4(s39)*. % 76.16/76.34 140805[74:MRR:801.0,140803.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 140808[74:Res:53.1,140805.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 140813[75:Spt:140808.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 140815[75:Res:140813.0,61.1] always3(s39) || -> . % 76.16/76.34 140816[75:SSi:140815.0,78241.0,78244.0,137761.0,140592.0,140803.0] || -> . % 76.16/76.34 140817[75:Spt:140816.0,140808.0,140813.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 140818[75:Spt:140816.0,140808.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 140822[75:Res:140818.0,61.1] always3(s40) || -> . % 76.16/76.34 140823[75:SSi:140822.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 140824[73:Spt:140823.0,140591.0,140592.0] || until2p7(s39)*+ -> . % 76.16/76.34 140825[73:Spt:140823.0,140591.1] || -> node4(s38)*. % 76.16/76.34 140827[73:MRR:804.0,140825.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 140830[73:Res:53.1,140827.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 140832[74:Spt:140830.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 140834[74:Res:140832.0,61.1] always3(s38) || -> . % 76.16/76.34 140835[74:SSi:140834.0,78236.0,78240.0,137760.0,140590.0,140825.0] || -> . % 76.16/76.34 140836[74:Spt:140835.0,140830.0,140832.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 140837[74:Spt:140835.0,140830.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 140841[74:Res:140837.0,61.1] always3(s39) || -> . % 76.16/76.34 140842[74:SSi:140841.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 140843[72:Spt:140842.0,140589.0,140590.0] || until2p7(s38)*+ -> . % 76.16/76.34 140844[72:Spt:140842.0,140589.1] || -> node4(s37)*. % 76.16/76.34 140846[72:MRR:807.0,140844.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 140849[72:Res:53.1,140846.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 140851[73:Spt:140849.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 140853[73:Res:140851.0,61.1] always3(s37) || -> . % 76.16/76.34 140854[73:SSi:140853.0,78232.0,78235.0,137759.0,140588.0,140844.0] || -> . % 76.16/76.34 140855[73:Spt:140854.0,140849.0,140851.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 140856[73:Spt:140854.0,140849.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 140860[73:Res:140856.0,61.1] always3(s38) || -> . % 76.16/76.34 140861[73:SSi:140860.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 140862[71:Spt:140861.0,140587.0,140588.0] || until2p7(s37)*+ -> . % 76.16/76.34 140863[71:Spt:140861.0,140587.1] || -> node4(s36)*. % 76.16/76.34 140865[71:MRR:810.0,140863.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 140868[71:Res:53.1,140865.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 140870[72:Spt:140868.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 140872[72:Res:140870.0,61.1] always3(s36) || -> . % 76.16/76.34 140873[72:SSi:140872.0,78227.0,78231.0,137758.0,140586.0,140863.0] || -> . % 76.16/76.34 140874[72:Spt:140873.0,140868.0,140870.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 140875[72:Spt:140873.0,140868.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 140879[72:Res:140875.0,61.1] always3(s37) || -> . % 76.16/76.34 140880[72:SSi:140879.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 140881[70:Spt:140880.0,140585.0,140586.0] || until2p7(s36)*+ -> . % 76.16/76.34 140882[70:Spt:140880.0,140585.1] || -> node4(s35)*. % 76.16/76.34 140884[70:MRR:813.0,140882.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 140887[70:Res:53.1,140884.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 140889[70:MRR:140887.0,140575.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 140894[70:Res:140889.0,61.1] always3(s36) || -> . % 76.16/76.34 140895[70:SSi:140894.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 140896[68:Spt:140895.0,140509.0,140512.0] || trans(s49,s35)*+ -> . % 76.16/76.34 140897[68:Spt:140895.0,140509.1,140509.2,140509.3,140509.4,140509.5,140509.6,140509.7,140509.8,140509.9,140509.10,140509.11,140509.12,140509.13,140509.14,140509.15,140509.16,140509.17,140509.18,140509.19,140509.20,140509.21,140509.22,140509.23,140509.24,140509.25,140509.26,140509.27,140509.28,140509.29,140509.30,140509.31] || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 140899[68:MRR:140511.1,140896.0] xuntil6(s49) || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 140900[69:Spt:140897.0] || -> trans(s49,s34)*. % 76.16/76.34 140901[69:Res:140900.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s34)*. % 76.16/76.34 140903[69:Res:140900.0,60.0] || -> node2(s49,s34)*. % 76.16/76.34 140904[69:SSi:140901.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s34)*. % 76.16/76.34 140905[69:Res:140903.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 140956[69:SoR:140905.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 140958[69:SoR:140956.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)* xuntil6(s49). % 76.16/76.34 140959[69:SSi:140958.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s34,c_busy)* xuntil6(s49). % 76.16/76.34 140960[70:Spt:140959.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 140962[70:Res:140960.0,61.1] always3(s34) || -> . % 76.16/76.34 140963[70:SSi:140962.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 140964[70:Spt:140963.0,140959.1,140960.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.16/76.34 140965[70:Spt:140963.0,140959.0,140959.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 140969[70:MRR:140956.2,140964.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 140970[70:Res:53.1,140965.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 140972[70:MRR:140970.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 140973[70:MRR:140904.0,140972.0] || -> until2p7(s34)*. % 76.16/76.34 140974[70:MRR:230.0,140973.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 140975[71:Spt:140974.0] || -> until2p7(s35)*. % 76.16/76.34 140976[71:MRR:231.0,140975.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 140977[72:Spt:140976.0] || -> until2p7(s36)*. % 76.16/76.34 140978[72:MRR:232.0,140977.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 140979[73:Spt:140978.0] || -> until2p7(s37)*. % 76.16/76.34 140980[73:MRR:235.0,140979.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 140981[74:Spt:140980.0] || -> until2p7(s38)*. % 76.16/76.34 140982[74:MRR:236.0,140981.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 140983[75:Spt:140982.0] || -> until2p7(s39)*. % 76.16/76.34 140984[75:MRR:237.0,140983.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 140985[76:Spt:140984.0] || -> until2p7(s40)*. % 76.16/76.34 140986[76:MRR:238.0,140985.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 140987[77:Spt:140986.0] || -> until2p7(s41)*. % 76.16/76.34 140988[77:MRR:239.0,140987.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 140989[78:Spt:140988.0] || -> until2p7(s42)*. % 76.16/76.34 140990[78:MRR:240.0,140989.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 140991[79:Spt:140990.0] || -> until2p7(s43)*. % 76.16/76.34 140992[79:MRR:241.0,140991.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 140993[80:Spt:140992.0] || -> until2p7(s44)*. % 76.16/76.34 140994[80:MRR:539.0,140993.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 140995[81:Spt:140994.0] || -> until2p7(s45)*. % 76.16/76.34 140996[81:MRR:544.0,140995.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 140997[82:Spt:140996.0] || -> until2p7(s46)*. % 76.16/76.34 140998[82:MRR:549.0,140997.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 140999[83:Spt:140998.0] || -> until2p7(s47)*. % 76.16/76.34 141000[83:MRR:554.0,140999.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 141001[84:Spt:141000.0] || -> until2p7(s48)*. % 76.16/76.34 141002[84:MRR:559.0,141001.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 141003[85:Spt:141002.0] || -> until2p7(s49)*. % 76.16/76.34 141004[85:MRR:194.0,141003.0] || -> node4(s49)*. % 76.16/76.34 141005[85:MRR:140969.0,141004.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 141006[85:Res:53.1,141005.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 141008[85:MRR:141006.0,78381.0] || -> . % 76.16/76.34 141009[85:Spt:141008.0,141002.0,141003.0] || until2p7(s49)*+ -> . % 76.16/76.34 141010[85:Spt:141008.0,141002.1] || -> node4(s48)*. % 76.16/76.34 141011[85:MRR:78384.0,141010.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 141014[85:Res:53.1,141011.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 141017[85:Res:141014.0,61.1] always3(s48) || -> . % 76.16/76.34 141018[85:SSi:141017.0,78281.0,78387.0,137770.0,141001.0,141010.0] || -> . % 76.16/76.34 141019[84:Spt:141018.0,141000.0,141001.0] || until2p7(s48)*+ -> . % 76.16/76.34 141020[84:Spt:141018.0,141000.1] || -> node4(s47)*. % 76.16/76.34 141022[84:MRR:777.0,141020.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 141037[84:Res:53.1,141022.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 141039[85:Spt:141037.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 141041[85:Res:141039.0,61.1] always3(s47) || -> . % 76.16/76.34 141042[85:SSi:141041.0,78277.0,78280.0,137769.0,140999.0,141020.0] || -> . % 76.16/76.34 141043[85:Spt:141042.0,141037.0,141039.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 141044[85:Spt:141042.0,141037.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 141048[85:Res:141044.0,61.1] always3(s48) || -> . % 76.16/76.34 141049[85:SSi:141048.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 141050[83:Spt:141049.0,140998.0,140999.0] || until2p7(s47)*+ -> . % 76.16/76.34 141051[83:Spt:141049.0,140998.1] || -> node4(s46)*. % 76.16/76.34 141053[83:MRR:780.0,141051.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 141063[83:Res:53.1,141053.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 141065[84:Spt:141063.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 141067[84:Res:141065.0,61.1] always3(s46) || -> . % 76.16/76.34 141068[84:SSi:141067.0,78272.0,78276.0,137768.0,140997.0,141051.0] || -> . % 76.16/76.34 141069[84:Spt:141068.0,141063.0,141065.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 141070[84:Spt:141068.0,141063.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 141074[84:Res:141070.0,61.1] always3(s47) || -> . % 76.16/76.34 141075[84:SSi:141074.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 141076[82:Spt:141075.0,140996.0,140997.0] || until2p7(s46)*+ -> . % 76.16/76.34 141077[82:Spt:141075.0,140996.1] || -> node4(s45)*. % 76.16/76.34 141079[82:MRR:783.0,141077.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 141082[82:Res:53.1,141079.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 141084[83:Spt:141082.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 141086[83:Res:141084.0,61.1] always3(s45) || -> . % 76.16/76.34 141087[83:SSi:141086.0,78268.0,78271.0,137767.0,140995.0,141077.0] || -> . % 76.16/76.34 141088[83:Spt:141087.0,141082.0,141084.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 141089[83:Spt:141087.0,141082.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 141093[83:Res:141089.0,61.1] always3(s46) || -> . % 76.16/76.34 141094[83:SSi:141093.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 141095[81:Spt:141094.0,140994.0,140995.0] || until2p7(s45)*+ -> . % 76.16/76.34 141096[81:Spt:141094.0,140994.1] || -> node4(s44)*. % 76.16/76.34 141098[81:MRR:786.0,141096.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 141101[81:Res:53.1,141098.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 141103[82:Spt:141101.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 141105[82:Res:141103.0,61.1] always3(s44) || -> . % 76.16/76.34 141106[82:SSi:141105.0,78263.0,78267.0,137766.0,140993.0,141096.0] || -> . % 76.16/76.34 141107[82:Spt:141106.0,141101.0,141103.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 141108[82:Spt:141106.0,141101.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 141112[82:Res:141108.0,61.1] always3(s45) || -> . % 76.16/76.34 141113[82:SSi:141112.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 141114[80:Spt:141113.0,140992.0,140993.0] || until2p7(s44)*+ -> . % 76.16/76.34 141115[80:Spt:141113.0,140992.1] || -> node4(s43)*. % 76.16/76.34 141117[80:MRR:789.0,141115.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 141120[80:Res:53.1,141117.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 141125[81:Spt:141120.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 141127[81:Res:141125.0,61.1] always3(s43) || -> . % 76.16/76.34 141128[81:SSi:141127.0,78259.0,78262.0,137765.0,140991.0,141115.0] || -> . % 76.16/76.34 141129[81:Spt:141128.0,141120.0,141125.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 141130[81:Spt:141128.0,141120.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 141134[81:Res:141130.0,61.1] always3(s44) || -> . % 76.16/76.34 141135[81:SSi:141134.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 141136[79:Spt:141135.0,140990.0,140991.0] || until2p7(s43)*+ -> . % 76.16/76.34 141137[79:Spt:141135.0,140990.1] || -> node4(s42)*. % 76.16/76.34 141139[79:MRR:792.0,141137.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 141142[79:Res:53.1,141139.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 141144[80:Spt:141142.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 141146[80:Res:141144.0,61.1] always3(s42) || -> . % 76.16/76.34 141147[80:SSi:141146.0,78254.0,78258.0,137764.0,140989.0,141137.0] || -> . % 76.16/76.34 141148[80:Spt:141147.0,141142.0,141144.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 141149[80:Spt:141147.0,141142.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 141153[80:Res:141149.0,61.1] always3(s43) || -> . % 76.16/76.34 141154[80:SSi:141153.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 141155[78:Spt:141154.0,140988.0,140989.0] || until2p7(s42)*+ -> . % 76.16/76.34 141156[78:Spt:141154.0,140988.1] || -> node4(s41)*. % 76.16/76.34 141158[78:MRR:795.0,141156.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 141161[78:Res:53.1,141158.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 141163[79:Spt:141161.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 141165[79:Res:141163.0,61.1] always3(s41) || -> . % 76.16/76.34 141166[79:SSi:141165.0,78250.0,78253.0,137763.0,140987.0,141156.0] || -> . % 76.16/76.34 141167[79:Spt:141166.0,141161.0,141163.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 141168[79:Spt:141166.0,141161.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 141172[79:Res:141168.0,61.1] always3(s42) || -> . % 76.16/76.34 141173[79:SSi:141172.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 141174[77:Spt:141173.0,140986.0,140987.0] || until2p7(s41)*+ -> . % 76.16/76.34 141175[77:Spt:141173.0,140986.1] || -> node4(s40)*. % 76.16/76.34 141177[77:MRR:798.0,141175.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 141180[77:Res:53.1,141177.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 141182[78:Spt:141180.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 141184[78:Res:141182.0,61.1] always3(s40) || -> . % 76.16/76.34 141185[78:SSi:141184.0,78245.0,78249.0,137762.0,140985.0,141175.0] || -> . % 76.16/76.34 141186[78:Spt:141185.0,141180.0,141182.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 141187[78:Spt:141185.0,141180.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 141191[78:Res:141187.0,61.1] always3(s41) || -> . % 76.16/76.34 141192[78:SSi:141191.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 141193[76:Spt:141192.0,140984.0,140985.0] || until2p7(s40)*+ -> . % 76.16/76.34 141194[76:Spt:141192.0,140984.1] || -> node4(s39)*. % 76.16/76.34 141196[76:MRR:801.0,141194.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 141199[76:Res:53.1,141196.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 141204[77:Spt:141199.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 141206[77:Res:141204.0,61.1] always3(s39) || -> . % 76.16/76.34 141207[77:SSi:141206.0,78241.0,78244.0,137761.0,140983.0,141194.0] || -> . % 76.16/76.34 141208[77:Spt:141207.0,141199.0,141204.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 141209[77:Spt:141207.0,141199.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 141213[77:Res:141209.0,61.1] always3(s40) || -> . % 76.16/76.34 141214[77:SSi:141213.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 141215[75:Spt:141214.0,140982.0,140983.0] || until2p7(s39)*+ -> . % 76.16/76.34 141216[75:Spt:141214.0,140982.1] || -> node4(s38)*. % 76.16/76.34 141218[75:MRR:804.0,141216.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 141221[75:Res:53.1,141218.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 141223[76:Spt:141221.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 141225[76:Res:141223.0,61.1] always3(s38) || -> . % 76.16/76.34 141226[76:SSi:141225.0,78236.0,78240.0,137760.0,140981.0,141216.0] || -> . % 76.16/76.34 141227[76:Spt:141226.0,141221.0,141223.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 141228[76:Spt:141226.0,141221.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 141232[76:Res:141228.0,61.1] always3(s39) || -> . % 76.16/76.34 141233[76:SSi:141232.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 141234[74:Spt:141233.0,140980.0,140981.0] || until2p7(s38)*+ -> . % 76.16/76.34 141235[74:Spt:141233.0,140980.1] || -> node4(s37)*. % 76.16/76.34 141237[74:MRR:807.0,141235.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 141240[74:Res:53.1,141237.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 141242[75:Spt:141240.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 141244[75:Res:141242.0,61.1] always3(s37) || -> . % 76.16/76.34 141245[75:SSi:141244.0,78232.0,78235.0,137759.0,140979.0,141235.0] || -> . % 76.16/76.34 141246[75:Spt:141245.0,141240.0,141242.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 141247[75:Spt:141245.0,141240.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 141251[75:Res:141247.0,61.1] always3(s38) || -> . % 76.16/76.34 141252[75:SSi:141251.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 141253[73:Spt:141252.0,140978.0,140979.0] || until2p7(s37)*+ -> . % 76.16/76.34 141254[73:Spt:141252.0,140978.1] || -> node4(s36)*. % 76.16/76.34 141256[73:MRR:810.0,141254.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 141259[73:Res:53.1,141256.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 141261[74:Spt:141259.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 141263[74:Res:141261.0,61.1] always3(s36) || -> . % 76.16/76.34 141264[74:SSi:141263.0,78227.0,78231.0,137758.0,140977.0,141254.0] || -> . % 76.16/76.34 141265[74:Spt:141264.0,141259.0,141261.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 141266[74:Spt:141264.0,141259.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 141270[74:Res:141266.0,61.1] always3(s37) || -> . % 76.16/76.34 141271[74:SSi:141270.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 141272[72:Spt:141271.0,140976.0,140977.0] || until2p7(s36)*+ -> . % 76.16/76.34 141273[72:Spt:141271.0,140976.1] || -> node4(s35)*. % 76.16/76.34 141275[72:MRR:813.0,141273.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 141278[72:Res:53.1,141275.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 141283[73:Spt:141278.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 141285[73:Res:141283.0,61.1] always3(s35) || -> . % 76.16/76.34 141286[73:SSi:141285.0,78223.0,78226.0,137757.0,140975.0,141273.0] || -> . % 76.16/76.34 141287[73:Spt:141286.0,141278.0,141283.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 141288[73:Spt:141286.0,141278.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 141292[73:Res:141288.0,61.1] always3(s36) || -> . % 76.16/76.34 141293[73:SSi:141292.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 141294[71:Spt:141293.0,140974.0,140975.0] || until2p7(s35)*+ -> . % 76.16/76.34 141295[71:Spt:141293.0,140974.1] || -> node4(s34)*. % 76.16/76.34 141297[71:MRR:816.0,141295.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 141300[71:Res:53.1,141297.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 141302[71:MRR:141300.0,140964.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 141304[71:Res:141302.0,61.1] always3(s35) || -> . % 76.16/76.34 141305[71:SSi:141304.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 141306[69:Spt:141305.0,140897.0,140900.0] || trans(s49,s34)*+ -> . % 76.16/76.34 141307[69:Spt:141305.0,140897.1,140897.2,140897.3,140897.4,140897.5,140897.6,140897.7,140897.8,140897.9,140897.10,140897.11,140897.12,140897.13,140897.14,140897.15,140897.16,140897.17,140897.18,140897.19,140897.20,140897.21,140897.22,140897.23,140897.24,140897.25,140897.26,140897.27,140897.28,140897.29,140897.30] || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 141309[69:MRR:140899.1,141306.0] xuntil6(s49) || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 141310[70:Spt:141307.0] || -> trans(s49,s33)*. % 76.16/76.34 141311[70:Res:141310.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s33)*. % 76.16/76.34 141313[70:Res:141310.0,60.0] || -> node2(s49,s33)*. % 76.16/76.34 141314[70:SSi:141311.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s33)*. % 76.16/76.34 141315[70:Res:141313.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 141370[70:SoR:141315.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 141372[70:SoR:141370.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.16/76.34 141373[70:SSi:141372.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.16/76.34 141374[71:Spt:141373.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 141376[71:Res:141374.0,61.1] always3(s33) || -> . % 76.16/76.34 141377[71:SSi:141376.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 141378[71:Spt:141377.0,141373.1,141374.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.16/76.34 141379[71:Spt:141377.0,141373.0,141373.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 141383[71:MRR:141370.2,141378.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 141384[71:Res:53.1,141379.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 141386[71:MRR:141384.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 141387[71:MRR:141314.0,141386.0] || -> until2p7(s33)*. % 76.16/76.34 141388[71:MRR:229.0,141387.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 141389[72:Spt:141388.0] || -> until2p7(s34)*. % 76.16/76.34 141390[72:MRR:230.0,141389.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 141391[73:Spt:141390.0] || -> until2p7(s35)*. % 76.16/76.34 141392[73:MRR:231.0,141391.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 141393[74:Spt:141392.0] || -> until2p7(s36)*. % 76.16/76.34 141394[74:MRR:232.0,141393.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 141395[75:Spt:141394.0] || -> until2p7(s37)*. % 76.16/76.34 141396[75:MRR:235.0,141395.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 141397[76:Spt:141396.0] || -> until2p7(s38)*. % 76.16/76.34 141398[76:MRR:236.0,141397.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 141399[77:Spt:141398.0] || -> until2p7(s39)*. % 76.16/76.34 141400[77:MRR:237.0,141399.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 141401[78:Spt:141400.0] || -> until2p7(s40)*. % 76.16/76.34 141402[78:MRR:238.0,141401.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 141403[79:Spt:141402.0] || -> until2p7(s41)*. % 76.16/76.34 141404[79:MRR:239.0,141403.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 141405[80:Spt:141404.0] || -> until2p7(s42)*. % 76.16/76.34 141406[80:MRR:240.0,141405.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 141407[81:Spt:141406.0] || -> until2p7(s43)*. % 76.16/76.34 141408[81:MRR:241.0,141407.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 141409[82:Spt:141408.0] || -> until2p7(s44)*. % 76.16/76.34 141410[82:MRR:539.0,141409.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 141411[83:Spt:141410.0] || -> until2p7(s45)*. % 76.16/76.34 141412[83:MRR:544.0,141411.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 141413[84:Spt:141412.0] || -> until2p7(s46)*. % 76.16/76.34 141414[84:MRR:549.0,141413.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 141415[85:Spt:141414.0] || -> until2p7(s47)*. % 76.16/76.34 141416[85:MRR:554.0,141415.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 141417[86:Spt:141416.0] || -> until2p7(s48)*. % 76.16/76.34 141418[86:MRR:559.0,141417.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 141419[87:Spt:141418.0] || -> until2p7(s49)*. % 76.16/76.34 141420[87:MRR:194.0,141419.0] || -> node4(s49)*. % 76.16/76.34 141421[87:MRR:141383.0,141420.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 141425[87:Res:53.1,141421.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 141427[87:MRR:141425.0,78381.0] || -> . % 76.16/76.34 141428[87:Spt:141427.0,141418.0,141419.0] || until2p7(s49)*+ -> . % 76.16/76.34 141429[87:Spt:141427.0,141418.1] || -> node4(s48)*. % 76.16/76.34 141430[87:MRR:78384.0,141429.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 141433[87:Res:53.1,141430.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 141436[87:Res:141433.0,61.1] always3(s48) || -> . % 76.16/76.34 141437[87:SSi:141436.0,78281.0,78387.0,137770.0,141417.0,141429.0] || -> . % 76.16/76.34 141438[86:Spt:141437.0,141416.0,141417.0] || until2p7(s48)*+ -> . % 76.16/76.34 141439[86:Spt:141437.0,141416.1] || -> node4(s47)*. % 76.16/76.34 141441[86:MRR:777.0,141439.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 141453[86:Res:53.1,141441.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 141455[87:Spt:141453.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 141457[87:Res:141455.0,61.1] always3(s47) || -> . % 76.16/76.34 141458[87:SSi:141457.0,78277.0,78280.0,137769.0,141415.0,141439.0] || -> . % 76.16/76.34 141459[87:Spt:141458.0,141453.0,141455.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 141460[87:Spt:141458.0,141453.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 141464[87:Res:141460.0,61.1] always3(s48) || -> . % 76.16/76.34 141465[87:SSi:141464.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 141466[85:Spt:141465.0,141414.0,141415.0] || until2p7(s47)*+ -> . % 76.16/76.34 141467[85:Spt:141465.0,141414.1] || -> node4(s46)*. % 76.16/76.34 141469[85:MRR:780.0,141467.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 141476[85:Res:53.1,141469.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 141481[86:Spt:141476.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 141483[86:Res:141481.0,61.1] always3(s46) || -> . % 76.16/76.34 141484[86:SSi:141483.0,78272.0,78276.0,137768.0,141413.0,141467.0] || -> . % 76.16/76.34 141485[86:Spt:141484.0,141476.0,141481.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 141486[86:Spt:141484.0,141476.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 141490[86:Res:141486.0,61.1] always3(s47) || -> . % 76.16/76.34 141491[86:SSi:141490.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 141492[84:Spt:141491.0,141412.0,141413.0] || until2p7(s46)*+ -> . % 76.16/76.34 141493[84:Spt:141491.0,141412.1] || -> node4(s45)*. % 76.16/76.34 141495[84:MRR:783.0,141493.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 141498[84:Res:53.1,141495.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 141500[85:Spt:141498.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 141502[85:Res:141500.0,61.1] always3(s45) || -> . % 76.16/76.34 141503[85:SSi:141502.0,78268.0,78271.0,137767.0,141411.0,141493.0] || -> . % 76.16/76.34 141504[85:Spt:141503.0,141498.0,141500.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 141505[85:Spt:141503.0,141498.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 141509[85:Res:141505.0,61.1] always3(s46) || -> . % 76.16/76.34 141510[85:SSi:141509.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 141511[83:Spt:141510.0,141410.0,141411.0] || until2p7(s45)*+ -> . % 76.16/76.34 141512[83:Spt:141510.0,141410.1] || -> node4(s44)*. % 76.16/76.34 141514[83:MRR:786.0,141512.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 141517[83:Res:53.1,141514.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 141519[84:Spt:141517.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 141521[84:Res:141519.0,61.1] always3(s44) || -> . % 76.16/76.34 141522[84:SSi:141521.0,78263.0,78267.0,137766.0,141409.0,141512.0] || -> . % 76.16/76.34 141523[84:Spt:141522.0,141517.0,141519.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 141524[84:Spt:141522.0,141517.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 141528[84:Res:141524.0,61.1] always3(s45) || -> . % 76.16/76.34 141529[84:SSi:141528.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 141530[82:Spt:141529.0,141408.0,141409.0] || until2p7(s44)*+ -> . % 76.16/76.34 141531[82:Spt:141529.0,141408.1] || -> node4(s43)*. % 76.16/76.34 141533[82:MRR:789.0,141531.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 141536[82:Res:53.1,141533.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 141538[83:Spt:141536.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 141540[83:Res:141538.0,61.1] always3(s43) || -> . % 76.16/76.34 141541[83:SSi:141540.0,78259.0,78262.0,137765.0,141407.0,141531.0] || -> . % 76.16/76.34 141542[83:Spt:141541.0,141536.0,141538.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 141543[83:Spt:141541.0,141536.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 141547[83:Res:141543.0,61.1] always3(s44) || -> . % 76.16/76.34 141548[83:SSi:141547.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 141549[81:Spt:141548.0,141406.0,141407.0] || until2p7(s43)*+ -> . % 76.16/76.34 141550[81:Spt:141548.0,141406.1] || -> node4(s42)*. % 76.16/76.34 141552[81:MRR:792.0,141550.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 141555[81:Res:53.1,141552.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 141560[82:Spt:141555.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 141562[82:Res:141560.0,61.1] always3(s42) || -> . % 76.16/76.34 141563[82:SSi:141562.0,78254.0,78258.0,137764.0,141405.0,141550.0] || -> . % 76.16/76.34 141564[82:Spt:141563.0,141555.0,141560.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 141565[82:Spt:141563.0,141555.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 141569[82:Res:141565.0,61.1] always3(s43) || -> . % 76.16/76.34 141570[82:SSi:141569.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 141571[80:Spt:141570.0,141404.0,141405.0] || until2p7(s42)*+ -> . % 76.16/76.34 141572[80:Spt:141570.0,141404.1] || -> node4(s41)*. % 76.16/76.34 141574[80:MRR:795.0,141572.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 141577[80:Res:53.1,141574.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 141579[81:Spt:141577.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 141581[81:Res:141579.0,61.1] always3(s41) || -> . % 76.16/76.34 141582[81:SSi:141581.0,78250.0,78253.0,137763.0,141403.0,141572.0] || -> . % 76.16/76.34 141583[81:Spt:141582.0,141577.0,141579.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 141584[81:Spt:141582.0,141577.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 141588[81:Res:141584.0,61.1] always3(s42) || -> . % 76.16/76.34 141589[81:SSi:141588.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 141590[79:Spt:141589.0,141402.0,141403.0] || until2p7(s41)*+ -> . % 76.16/76.34 141591[79:Spt:141589.0,141402.1] || -> node4(s40)*. % 76.16/76.34 141593[79:MRR:798.0,141591.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 141596[79:Res:53.1,141593.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 141598[80:Spt:141596.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 141600[80:Res:141598.0,61.1] always3(s40) || -> . % 76.16/76.34 141601[80:SSi:141600.0,78245.0,78249.0,137762.0,141401.0,141591.0] || -> . % 76.16/76.34 141602[80:Spt:141601.0,141596.0,141598.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 141603[80:Spt:141601.0,141596.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 141607[80:Res:141603.0,61.1] always3(s41) || -> . % 76.16/76.34 141608[80:SSi:141607.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 141609[78:Spt:141608.0,141400.0,141401.0] || until2p7(s40)*+ -> . % 76.16/76.34 141610[78:Spt:141608.0,141400.1] || -> node4(s39)*. % 76.16/76.34 141612[78:MRR:801.0,141610.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 141615[78:Res:53.1,141612.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 141617[79:Spt:141615.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 141619[79:Res:141617.0,61.1] always3(s39) || -> . % 76.16/76.34 141620[79:SSi:141619.0,78241.0,78244.0,137761.0,141399.0,141610.0] || -> . % 76.16/76.34 141621[79:Spt:141620.0,141615.0,141617.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 141622[79:Spt:141620.0,141615.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 141626[79:Res:141622.0,61.1] always3(s40) || -> . % 76.16/76.34 141627[79:SSi:141626.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 141628[77:Spt:141627.0,141398.0,141399.0] || until2p7(s39)*+ -> . % 76.16/76.34 141629[77:Spt:141627.0,141398.1] || -> node4(s38)*. % 76.16/76.34 141631[77:MRR:804.0,141629.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 141634[77:Res:53.1,141631.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 141639[78:Spt:141634.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 141641[78:Res:141639.0,61.1] always3(s38) || -> . % 76.16/76.34 141642[78:SSi:141641.0,78236.0,78240.0,137760.0,141397.0,141629.0] || -> . % 76.16/76.34 141643[78:Spt:141642.0,141634.0,141639.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 141644[78:Spt:141642.0,141634.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 141648[78:Res:141644.0,61.1] always3(s39) || -> . % 76.16/76.34 141649[78:SSi:141648.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 141650[76:Spt:141649.0,141396.0,141397.0] || until2p7(s38)*+ -> . % 76.16/76.34 141651[76:Spt:141649.0,141396.1] || -> node4(s37)*. % 76.16/76.34 141653[76:MRR:807.0,141651.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 141656[76:Res:53.1,141653.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 141658[77:Spt:141656.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 141660[77:Res:141658.0,61.1] always3(s37) || -> . % 76.16/76.34 141661[77:SSi:141660.0,78232.0,78235.0,137759.0,141395.0,141651.0] || -> . % 76.16/76.34 141662[77:Spt:141661.0,141656.0,141658.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 141663[77:Spt:141661.0,141656.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 141667[77:Res:141663.0,61.1] always3(s38) || -> . % 76.16/76.34 141668[77:SSi:141667.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 141669[75:Spt:141668.0,141394.0,141395.0] || until2p7(s37)*+ -> . % 76.16/76.34 141670[75:Spt:141668.0,141394.1] || -> node4(s36)*. % 76.16/76.34 141672[75:MRR:810.0,141670.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 141675[75:Res:53.1,141672.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 141677[76:Spt:141675.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 141679[76:Res:141677.0,61.1] always3(s36) || -> . % 76.16/76.34 141680[76:SSi:141679.0,78227.0,78231.0,137758.0,141393.0,141670.0] || -> . % 76.16/76.34 141681[76:Spt:141680.0,141675.0,141677.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 141682[76:Spt:141680.0,141675.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 141686[76:Res:141682.0,61.1] always3(s37) || -> . % 76.16/76.34 141687[76:SSi:141686.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 141688[74:Spt:141687.0,141392.0,141393.0] || until2p7(s36)*+ -> . % 76.16/76.34 141689[74:Spt:141687.0,141392.1] || -> node4(s35)*. % 76.16/76.34 141691[74:MRR:813.0,141689.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 141694[74:Res:53.1,141691.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 141696[75:Spt:141694.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 141698[75:Res:141696.0,61.1] always3(s35) || -> . % 76.16/76.34 141699[75:SSi:141698.0,78223.0,78226.0,137757.0,141391.0,141689.0] || -> . % 76.16/76.34 141700[75:Spt:141699.0,141694.0,141696.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 141701[75:Spt:141699.0,141694.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 141705[75:Res:141701.0,61.1] always3(s36) || -> . % 76.16/76.34 141706[75:SSi:141705.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 141707[73:Spt:141706.0,141390.0,141391.0] || until2p7(s35)*+ -> . % 76.16/76.34 141708[73:Spt:141706.0,141390.1] || -> node4(s34)*. % 76.16/76.34 141710[73:MRR:816.0,141708.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 141713[73:Res:53.1,141710.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 141718[74:Spt:141713.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 141720[74:Res:141718.0,61.1] always3(s34) || -> . % 76.16/76.34 141721[74:SSi:141720.0,78218.0,78222.0,137756.0,141389.0,141708.0] || -> . % 76.16/76.34 141722[74:Spt:141721.0,141713.0,141718.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 141723[74:Spt:141721.0,141713.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 141727[74:Res:141723.0,61.1] always3(s35) || -> . % 76.16/76.34 141728[74:SSi:141727.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 141729[72:Spt:141728.0,141388.0,141389.0] || until2p7(s34)*+ -> . % 76.16/76.34 141730[72:Spt:141728.0,141388.1] || -> node4(s33)*. % 76.16/76.34 141732[72:MRR:819.0,141730.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 141735[72:Res:53.1,141732.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 141737[72:MRR:141735.0,141378.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 141739[72:Res:141737.0,61.1] always3(s34) || -> . % 76.16/76.34 141740[72:SSi:141739.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 141741[70:Spt:141740.0,141307.0,141310.0] || trans(s49,s33)*+ -> . % 76.16/76.34 141742[70:Spt:141740.0,141307.1,141307.2,141307.3,141307.4,141307.5,141307.6,141307.7,141307.8,141307.9,141307.10,141307.11,141307.12,141307.13,141307.14,141307.15,141307.16,141307.17,141307.18,141307.19,141307.20,141307.21,141307.22,141307.23,141307.24,141307.25,141307.26,141307.27,141307.28,141307.29] || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 141744[70:MRR:141309.1,141741.0] xuntil6(s49) || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 141745[71:Spt:141742.0] || -> trans(s49,s32)*. % 76.16/76.34 141746[71:Res:141745.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s32)*. % 76.16/76.34 141748[71:Res:141745.0,60.0] || -> node2(s49,s32)*. % 76.16/76.34 141749[71:SSi:141746.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s32)*. % 76.16/76.34 141750[71:Res:141748.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 141809[71:SoR:141750.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 141811[71:SoR:141809.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)* xuntil6(s49). % 76.16/76.34 141812[71:SSi:141811.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s32,c_busy)* xuntil6(s49). % 76.16/76.34 141813[72:Spt:141812.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 141815[72:Res:141813.0,61.1] always3(s32) || -> . % 76.16/76.34 141816[72:SSi:141815.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.34 141817[72:Spt:141816.0,141812.1,141813.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.16/76.34 141818[72:Spt:141816.0,141812.0,141812.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 141822[72:MRR:141809.2,141817.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 141823[72:Res:53.1,141818.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 141825[72:MRR:141823.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 141826[72:MRR:141749.0,141825.0] || -> until2p7(s32)*. % 76.16/76.34 141827[72:MRR:228.0,141826.0] || -> until2p7(s33)* node4(s32). % 76.16/76.34 141828[73:Spt:141827.0] || -> until2p7(s33)*. % 76.16/76.34 141829[73:MRR:229.0,141828.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 141830[74:Spt:141829.0] || -> until2p7(s34)*. % 76.16/76.34 141831[74:MRR:230.0,141830.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 141832[75:Spt:141831.0] || -> until2p7(s35)*. % 76.16/76.34 141833[75:MRR:231.0,141832.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 141834[76:Spt:141833.0] || -> until2p7(s36)*. % 76.16/76.34 141835[76:MRR:232.0,141834.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 141836[77:Spt:141835.0] || -> until2p7(s37)*. % 76.16/76.34 141837[77:MRR:235.0,141836.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 141838[78:Spt:141837.0] || -> until2p7(s38)*. % 76.16/76.34 141839[78:MRR:236.0,141838.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 141840[79:Spt:141839.0] || -> until2p7(s39)*. % 76.16/76.34 141841[79:MRR:237.0,141840.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 141842[80:Spt:141841.0] || -> until2p7(s40)*. % 76.16/76.34 141843[80:MRR:238.0,141842.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 141844[81:Spt:141843.0] || -> until2p7(s41)*. % 76.16/76.34 141845[81:MRR:239.0,141844.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 141846[82:Spt:141845.0] || -> until2p7(s42)*. % 76.16/76.34 141847[82:MRR:240.0,141846.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 141848[83:Spt:141847.0] || -> until2p7(s43)*. % 76.16/76.34 141849[83:MRR:241.0,141848.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 141850[84:Spt:141849.0] || -> until2p7(s44)*. % 76.16/76.34 141851[84:MRR:539.0,141850.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 141852[85:Spt:141851.0] || -> until2p7(s45)*. % 76.16/76.34 141853[85:MRR:544.0,141852.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 141854[86:Spt:141853.0] || -> until2p7(s46)*. % 76.16/76.34 141855[86:MRR:549.0,141854.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 141856[87:Spt:141855.0] || -> until2p7(s47)*. % 76.16/76.34 141857[87:MRR:554.0,141856.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 141858[88:Spt:141857.0] || -> until2p7(s48)*. % 76.16/76.34 141859[88:MRR:559.0,141858.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 141860[89:Spt:141859.0] || -> until2p7(s49)*. % 76.16/76.34 141861[89:MRR:194.0,141860.0] || -> node4(s49)*. % 76.16/76.34 141862[89:MRR:141822.0,141861.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 141863[89:Res:53.1,141862.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 141865[89:MRR:141863.0,78381.0] || -> . % 76.16/76.34 141866[89:Spt:141865.0,141859.0,141860.0] || until2p7(s49)*+ -> . % 76.16/76.34 141867[89:Spt:141865.0,141859.1] || -> node4(s48)*. % 76.16/76.34 141868[89:MRR:78384.0,141867.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 141871[89:Res:53.1,141868.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 141874[89:Res:141871.0,61.1] always3(s48) || -> . % 76.16/76.34 141875[89:SSi:141874.0,78281.0,78387.0,137770.0,141858.0,141867.0] || -> . % 76.16/76.34 141876[88:Spt:141875.0,141857.0,141858.0] || until2p7(s48)*+ -> . % 76.16/76.34 141877[88:Spt:141875.0,141857.1] || -> node4(s47)*. % 76.16/76.34 141879[88:MRR:777.0,141877.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 141894[88:Res:53.1,141879.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 141899[89:Spt:141894.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 141901[89:Res:141899.0,61.1] always3(s47) || -> . % 76.16/76.34 141902[89:SSi:141901.0,78277.0,78280.0,137769.0,141856.0,141877.0] || -> . % 76.16/76.34 141903[89:Spt:141902.0,141894.0,141899.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 141904[89:Spt:141902.0,141894.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 141908[89:Res:141904.0,61.1] always3(s48) || -> . % 76.16/76.34 141909[89:SSi:141908.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 141910[87:Spt:141909.0,141855.0,141856.0] || until2p7(s47)*+ -> . % 76.16/76.34 141911[87:Spt:141909.0,141855.1] || -> node4(s46)*. % 76.16/76.34 141913[87:MRR:780.0,141911.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 141920[87:Res:53.1,141913.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 141922[88:Spt:141920.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 141924[88:Res:141922.0,61.1] always3(s46) || -> . % 76.16/76.34 141925[88:SSi:141924.0,78272.0,78276.0,137768.0,141854.0,141911.0] || -> . % 76.16/76.34 141926[88:Spt:141925.0,141920.0,141922.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 141927[88:Spt:141925.0,141920.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 141931[88:Res:141927.0,61.1] always3(s47) || -> . % 76.16/76.34 141932[88:SSi:141931.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 141933[86:Spt:141932.0,141853.0,141854.0] || until2p7(s46)*+ -> . % 76.16/76.34 141934[86:Spt:141932.0,141853.1] || -> node4(s45)*. % 76.16/76.34 141936[86:MRR:783.0,141934.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 141939[86:Res:53.1,141936.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 141944[87:Spt:141939.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 141946[87:Res:141944.0,61.1] always3(s45) || -> . % 76.16/76.34 141947[87:SSi:141946.0,78268.0,78271.0,137767.0,141852.0,141934.0] || -> . % 76.16/76.34 141948[87:Spt:141947.0,141939.0,141944.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 141949[87:Spt:141947.0,141939.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 141953[87:Res:141949.0,61.1] always3(s46) || -> . % 76.16/76.34 141954[87:SSi:141953.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 141955[85:Spt:141954.0,141851.0,141852.0] || until2p7(s45)*+ -> . % 76.16/76.34 141956[85:Spt:141954.0,141851.1] || -> node4(s44)*. % 76.16/76.34 141958[85:MRR:786.0,141956.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 141961[85:Res:53.1,141958.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 141963[86:Spt:141961.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 141965[86:Res:141963.0,61.1] always3(s44) || -> . % 76.16/76.34 141966[86:SSi:141965.0,78263.0,78267.0,137766.0,141850.0,141956.0] || -> . % 76.16/76.34 141967[86:Spt:141966.0,141961.0,141963.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 141968[86:Spt:141966.0,141961.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 141972[86:Res:141968.0,61.1] always3(s45) || -> . % 76.16/76.34 141973[86:SSi:141972.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 141974[84:Spt:141973.0,141849.0,141850.0] || until2p7(s44)*+ -> . % 76.16/76.34 141975[84:Spt:141973.0,141849.1] || -> node4(s43)*. % 76.16/76.34 141977[84:MRR:789.0,141975.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 141980[84:Res:53.1,141977.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 141982[85:Spt:141980.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 141984[85:Res:141982.0,61.1] always3(s43) || -> . % 76.16/76.34 141985[85:SSi:141984.0,78259.0,78262.0,137765.0,141848.0,141975.0] || -> . % 76.16/76.34 141986[85:Spt:141985.0,141980.0,141982.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 141987[85:Spt:141985.0,141980.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 141991[85:Res:141987.0,61.1] always3(s44) || -> . % 76.16/76.34 141992[85:SSi:141991.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 141993[83:Spt:141992.0,141847.0,141848.0] || until2p7(s43)*+ -> . % 76.16/76.34 141994[83:Spt:141992.0,141847.1] || -> node4(s42)*. % 76.16/76.34 141996[83:MRR:792.0,141994.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 141999[83:Res:53.1,141996.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 142001[84:Spt:141999.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 142003[84:Res:142001.0,61.1] always3(s42) || -> . % 76.16/76.34 142004[84:SSi:142003.0,78254.0,78258.0,137764.0,141846.0,141994.0] || -> . % 76.16/76.34 142005[84:Spt:142004.0,141999.0,142001.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 142006[84:Spt:142004.0,141999.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 142010[84:Res:142006.0,61.1] always3(s43) || -> . % 76.16/76.34 142011[84:SSi:142010.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 142012[82:Spt:142011.0,141845.0,141846.0] || until2p7(s42)*+ -> . % 76.16/76.34 142013[82:Spt:142011.0,141845.1] || -> node4(s41)*. % 76.16/76.34 142015[82:MRR:795.0,142013.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 142018[82:Res:53.1,142015.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 142023[83:Spt:142018.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 142025[83:Res:142023.0,61.1] always3(s41) || -> . % 76.16/76.34 142026[83:SSi:142025.0,78250.0,78253.0,137763.0,141844.0,142013.0] || -> . % 76.16/76.34 142027[83:Spt:142026.0,142018.0,142023.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 142028[83:Spt:142026.0,142018.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 142032[83:Res:142028.0,61.1] always3(s42) || -> . % 76.16/76.34 142033[83:SSi:142032.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 142034[81:Spt:142033.0,141843.0,141844.0] || until2p7(s41)*+ -> . % 76.16/76.34 142035[81:Spt:142033.0,141843.1] || -> node4(s40)*. % 76.16/76.34 142037[81:MRR:798.0,142035.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 142040[81:Res:53.1,142037.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 142042[82:Spt:142040.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 142044[82:Res:142042.0,61.1] always3(s40) || -> . % 76.16/76.34 142045[82:SSi:142044.0,78245.0,78249.0,137762.0,141842.0,142035.0] || -> . % 76.16/76.34 142046[82:Spt:142045.0,142040.0,142042.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 142047[82:Spt:142045.0,142040.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 142051[82:Res:142047.0,61.1] always3(s41) || -> . % 76.16/76.34 142052[82:SSi:142051.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 142053[80:Spt:142052.0,141841.0,141842.0] || until2p7(s40)*+ -> . % 76.16/76.34 142054[80:Spt:142052.0,141841.1] || -> node4(s39)*. % 76.16/76.34 142056[80:MRR:801.0,142054.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 142059[80:Res:53.1,142056.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 142061[81:Spt:142059.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 142063[81:Res:142061.0,61.1] always3(s39) || -> . % 76.16/76.34 142064[81:SSi:142063.0,78241.0,78244.0,137761.0,141840.0,142054.0] || -> . % 76.16/76.34 142065[81:Spt:142064.0,142059.0,142061.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 142066[81:Spt:142064.0,142059.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 142070[81:Res:142066.0,61.1] always3(s40) || -> . % 76.16/76.34 142071[81:SSi:142070.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 142072[79:Spt:142071.0,141839.0,141840.0] || until2p7(s39)*+ -> . % 76.16/76.34 142073[79:Spt:142071.0,141839.1] || -> node4(s38)*. % 76.16/76.34 142075[79:MRR:804.0,142073.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 142078[79:Res:53.1,142075.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 142080[80:Spt:142078.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 142082[80:Res:142080.0,61.1] always3(s38) || -> . % 76.16/76.34 142083[80:SSi:142082.0,78236.0,78240.0,137760.0,141838.0,142073.0] || -> . % 76.16/76.34 142084[80:Spt:142083.0,142078.0,142080.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 142085[80:Spt:142083.0,142078.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 142089[80:Res:142085.0,61.1] always3(s39) || -> . % 76.16/76.34 142090[80:SSi:142089.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 142091[78:Spt:142090.0,141837.0,141838.0] || until2p7(s38)*+ -> . % 76.16/76.34 142092[78:Spt:142090.0,141837.1] || -> node4(s37)*. % 76.16/76.34 142094[78:MRR:807.0,142092.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 142097[78:Res:53.1,142094.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 142102[79:Spt:142097.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 142104[79:Res:142102.0,61.1] always3(s37) || -> . % 76.16/76.34 142105[79:SSi:142104.0,78232.0,78235.0,137759.0,141836.0,142092.0] || -> . % 76.16/76.34 142106[79:Spt:142105.0,142097.0,142102.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 142107[79:Spt:142105.0,142097.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 142111[79:Res:142107.0,61.1] always3(s38) || -> . % 76.16/76.34 142112[79:SSi:142111.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 142113[77:Spt:142112.0,141835.0,141836.0] || until2p7(s37)*+ -> . % 76.16/76.34 142114[77:Spt:142112.0,141835.1] || -> node4(s36)*. % 76.16/76.34 142116[77:MRR:810.0,142114.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 142119[77:Res:53.1,142116.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 142121[78:Spt:142119.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 142123[78:Res:142121.0,61.1] always3(s36) || -> . % 76.16/76.34 142124[78:SSi:142123.0,78227.0,78231.0,137758.0,141834.0,142114.0] || -> . % 76.16/76.34 142125[78:Spt:142124.0,142119.0,142121.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 142126[78:Spt:142124.0,142119.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 142130[78:Res:142126.0,61.1] always3(s37) || -> . % 76.16/76.34 142131[78:SSi:142130.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 142132[76:Spt:142131.0,141833.0,141834.0] || until2p7(s36)*+ -> . % 76.16/76.34 142133[76:Spt:142131.0,141833.1] || -> node4(s35)*. % 76.16/76.34 142135[76:MRR:813.0,142133.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 142138[76:Res:53.1,142135.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 142140[77:Spt:142138.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 142142[77:Res:142140.0,61.1] always3(s35) || -> . % 76.16/76.34 142143[77:SSi:142142.0,78223.0,78226.0,137757.0,141832.0,142133.0] || -> . % 76.16/76.34 142144[77:Spt:142143.0,142138.0,142140.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 142145[77:Spt:142143.0,142138.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 142149[77:Res:142145.0,61.1] always3(s36) || -> . % 76.16/76.34 142150[77:SSi:142149.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 142151[75:Spt:142150.0,141831.0,141832.0] || until2p7(s35)*+ -> . % 76.16/76.34 142152[75:Spt:142150.0,141831.1] || -> node4(s34)*. % 76.16/76.34 142154[75:MRR:816.0,142152.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 142157[75:Res:53.1,142154.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 142159[76:Spt:142157.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 142161[76:Res:142159.0,61.1] always3(s34) || -> . % 76.16/76.34 142162[76:SSi:142161.0,78218.0,78222.0,137756.0,141830.0,142152.0] || -> . % 76.16/76.34 142163[76:Spt:142162.0,142157.0,142159.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 142164[76:Spt:142162.0,142157.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 142168[76:Res:142164.0,61.1] always3(s35) || -> . % 76.16/76.34 142169[76:SSi:142168.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 142170[74:Spt:142169.0,141829.0,141830.0] || until2p7(s34)*+ -> . % 76.16/76.34 142171[74:Spt:142169.0,141829.1] || -> node4(s33)*. % 76.16/76.34 142173[74:MRR:819.0,142171.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 142176[74:Res:53.1,142173.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 142181[75:Spt:142176.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 142183[75:Res:142181.0,61.1] always3(s33) || -> . % 76.16/76.34 142184[75:SSi:142183.0,78214.0,78217.0,137755.0,141828.0,142171.0] || -> . % 76.16/76.34 142185[75:Spt:142184.0,142176.0,142181.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.34 142186[75:Spt:142184.0,142176.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 142190[75:Res:142186.0,61.1] always3(s34) || -> . % 76.16/76.34 142191[75:SSi:142190.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 142192[73:Spt:142191.0,141827.0,141828.0] || until2p7(s33)*+ -> . % 76.16/76.34 142193[73:Spt:142191.0,141827.1] || -> node4(s32)*. % 76.16/76.34 142195[73:MRR:822.0,142193.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.34 142198[73:Res:53.1,142195.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.34 142200[73:MRR:142198.0,141817.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 142202[73:Res:142200.0,61.1] always3(s33) || -> . % 76.16/76.34 142203[73:SSi:142202.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 142204[71:Spt:142203.0,141742.0,141745.0] || trans(s49,s32)*+ -> . % 76.16/76.34 142205[71:Spt:142203.0,141742.1,141742.2,141742.3,141742.4,141742.5,141742.6,141742.7,141742.8,141742.9,141742.10,141742.11,141742.12,141742.13,141742.14,141742.15,141742.16,141742.17,141742.18,141742.19,141742.20,141742.21,141742.22,141742.23,141742.24,141742.25,141742.26,141742.27,141742.28] || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 142207[71:MRR:141744.1,142204.0] xuntil6(s49) || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 142208[72:Spt:142205.0] || -> trans(s49,s31)*. % 76.16/76.34 142209[72:Res:142208.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s31)*. % 76.16/76.34 142211[72:Res:142208.0,60.0] || -> node2(s49,s31)*. % 76.16/76.34 142212[72:SSi:142209.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s31)*. % 76.16/76.34 142213[72:Res:142211.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 142273[72:SoR:142213.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 142275[72:SoR:142273.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.16/76.34 142276[72:SSi:142275.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.16/76.34 142277[73:Spt:142276.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 142279[73:Res:142277.0,61.1] always3(s31) || -> . % 76.16/76.34 142280[73:SSi:142279.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.34 142281[73:Spt:142280.0,142276.1,142277.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.16/76.34 142282[73:Spt:142280.0,142276.0,142276.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 142286[73:MRR:142273.2,142281.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 142287[73:Res:53.1,142282.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 142289[73:MRR:142287.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 142290[73:MRR:142212.0,142289.0] || -> until2p7(s31)*. % 76.16/76.34 142291[73:MRR:227.0,142290.0] || -> until2p7(s32)* node4(s31). % 76.16/76.34 142292[74:Spt:142291.0] || -> until2p7(s32)*. % 76.16/76.34 142293[74:MRR:228.0,142292.0] || -> until2p7(s33)* node4(s32). % 76.16/76.34 142294[75:Spt:142293.0] || -> until2p7(s33)*. % 76.16/76.34 142295[75:MRR:229.0,142294.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 142296[76:Spt:142295.0] || -> until2p7(s34)*. % 76.16/76.34 142297[76:MRR:230.0,142296.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 142298[77:Spt:142297.0] || -> until2p7(s35)*. % 76.16/76.34 142299[77:MRR:231.0,142298.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 142300[78:Spt:142299.0] || -> until2p7(s36)*. % 76.16/76.34 142301[78:MRR:232.0,142300.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 142302[79:Spt:142301.0] || -> until2p7(s37)*. % 76.16/76.34 142303[79:MRR:235.0,142302.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 142304[80:Spt:142303.0] || -> until2p7(s38)*. % 76.16/76.34 142305[80:MRR:236.0,142304.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 142306[81:Spt:142305.0] || -> until2p7(s39)*. % 76.16/76.34 142307[81:MRR:237.0,142306.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 142308[82:Spt:142307.0] || -> until2p7(s40)*. % 76.16/76.34 142309[82:MRR:238.0,142308.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 142310[83:Spt:142309.0] || -> until2p7(s41)*. % 76.16/76.34 142311[83:MRR:239.0,142310.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 142312[84:Spt:142311.0] || -> until2p7(s42)*. % 76.16/76.34 142313[84:MRR:240.0,142312.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 142314[85:Spt:142313.0] || -> until2p7(s43)*. % 76.16/76.34 142315[85:MRR:241.0,142314.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 142316[86:Spt:142315.0] || -> until2p7(s44)*. % 76.16/76.34 142317[86:MRR:539.0,142316.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 142318[87:Spt:142317.0] || -> until2p7(s45)*. % 76.16/76.34 142319[87:MRR:544.0,142318.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 142320[88:Spt:142319.0] || -> until2p7(s46)*. % 76.16/76.34 142321[88:MRR:549.0,142320.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 142322[89:Spt:142321.0] || -> until2p7(s47)*. % 76.16/76.34 142323[89:MRR:554.0,142322.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 142324[90:Spt:142323.0] || -> until2p7(s48)*. % 76.16/76.34 142325[90:MRR:559.0,142324.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 142326[91:Spt:142325.0] || -> until2p7(s49)*. % 76.16/76.34 142327[91:MRR:194.0,142326.0] || -> node4(s49)*. % 76.16/76.34 142328[91:MRR:142286.0,142327.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 142332[91:Res:53.1,142328.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 142334[91:MRR:142332.0,78381.0] || -> . % 76.16/76.34 142335[91:Spt:142334.0,142325.0,142326.0] || until2p7(s49)*+ -> . % 76.16/76.34 142336[91:Spt:142334.0,142325.1] || -> node4(s48)*. % 76.16/76.34 142337[91:MRR:78384.0,142336.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 142340[91:Res:53.1,142337.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 142343[91:Res:142340.0,61.1] always3(s48) || -> . % 76.16/76.34 142344[91:SSi:142343.0,78281.0,78387.0,137770.0,142324.0,142336.0] || -> . % 76.16/76.34 142345[90:Spt:142344.0,142323.0,142324.0] || until2p7(s48)*+ -> . % 76.16/76.34 142346[90:Spt:142344.0,142323.1] || -> node4(s47)*. % 76.16/76.34 142348[90:MRR:777.0,142346.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 142360[90:Res:53.1,142348.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 142362[91:Spt:142360.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 142364[91:Res:142362.0,61.1] always3(s47) || -> . % 76.16/76.34 142365[91:SSi:142364.0,78277.0,78280.0,137769.0,142322.0,142346.0] || -> . % 76.16/76.34 142366[91:Spt:142365.0,142360.0,142362.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 142367[91:Spt:142365.0,142360.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 142371[91:Res:142367.0,61.1] always3(s48) || -> . % 76.16/76.34 142372[91:SSi:142371.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 142373[89:Spt:142372.0,142321.0,142322.0] || until2p7(s47)*+ -> . % 76.16/76.34 142374[89:Spt:142372.0,142321.1] || -> node4(s46)*. % 76.16/76.34 142376[89:MRR:780.0,142374.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 142383[89:Res:53.1,142376.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 142388[90:Spt:142383.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 142390[90:Res:142388.0,61.1] always3(s46) || -> . % 76.16/76.34 142391[90:SSi:142390.0,78272.0,78276.0,137768.0,142320.0,142374.0] || -> . % 76.16/76.34 142392[90:Spt:142391.0,142383.0,142388.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 142393[90:Spt:142391.0,142383.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 142397[90:Res:142393.0,61.1] always3(s47) || -> . % 76.16/76.34 142398[90:SSi:142397.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 142399[88:Spt:142398.0,142319.0,142320.0] || until2p7(s46)*+ -> . % 76.16/76.34 142400[88:Spt:142398.0,142319.1] || -> node4(s45)*. % 76.16/76.34 142402[88:MRR:783.0,142400.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 142405[88:Res:53.1,142402.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 142407[89:Spt:142405.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 142409[89:Res:142407.0,61.1] always3(s45) || -> . % 76.16/76.34 142410[89:SSi:142409.0,78268.0,78271.0,137767.0,142318.0,142400.0] || -> . % 76.16/76.34 142411[89:Spt:142410.0,142405.0,142407.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 142412[89:Spt:142410.0,142405.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 142416[89:Res:142412.0,61.1] always3(s46) || -> . % 76.16/76.34 142417[89:SSi:142416.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 142418[87:Spt:142417.0,142317.0,142318.0] || until2p7(s45)*+ -> . % 76.16/76.34 142419[87:Spt:142417.0,142317.1] || -> node4(s44)*. % 76.16/76.34 142421[87:MRR:786.0,142419.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 142424[87:Res:53.1,142421.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 142426[88:Spt:142424.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 142428[88:Res:142426.0,61.1] always3(s44) || -> . % 76.16/76.34 142429[88:SSi:142428.0,78263.0,78267.0,137766.0,142316.0,142419.0] || -> . % 76.16/76.34 142430[88:Spt:142429.0,142424.0,142426.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 142431[88:Spt:142429.0,142424.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 142435[88:Res:142431.0,61.1] always3(s45) || -> . % 76.16/76.34 142436[88:SSi:142435.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 142437[86:Spt:142436.0,142315.0,142316.0] || until2p7(s44)*+ -> . % 76.16/76.34 142438[86:Spt:142436.0,142315.1] || -> node4(s43)*. % 76.16/76.34 142440[86:MRR:789.0,142438.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 142443[86:Res:53.1,142440.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 142445[87:Spt:142443.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 142447[87:Res:142445.0,61.1] always3(s43) || -> . % 76.16/76.34 142448[87:SSi:142447.0,78259.0,78262.0,137765.0,142314.0,142438.0] || -> . % 76.16/76.34 142449[87:Spt:142448.0,142443.0,142445.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 142450[87:Spt:142448.0,142443.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 142454[87:Res:142450.0,61.1] always3(s44) || -> . % 76.16/76.34 142455[87:SSi:142454.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 142456[85:Spt:142455.0,142313.0,142314.0] || until2p7(s43)*+ -> . % 76.16/76.34 142457[85:Spt:142455.0,142313.1] || -> node4(s42)*. % 76.16/76.34 142459[85:MRR:792.0,142457.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 142462[85:Res:53.1,142459.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 142467[86:Spt:142462.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 142469[86:Res:142467.0,61.1] always3(s42) || -> . % 76.16/76.34 142470[86:SSi:142469.0,78254.0,78258.0,137764.0,142312.0,142457.0] || -> . % 76.16/76.34 142471[86:Spt:142470.0,142462.0,142467.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 142472[86:Spt:142470.0,142462.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 142476[86:Res:142472.0,61.1] always3(s43) || -> . % 76.16/76.34 142477[86:SSi:142476.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 142478[84:Spt:142477.0,142311.0,142312.0] || until2p7(s42)*+ -> . % 76.16/76.34 142479[84:Spt:142477.0,142311.1] || -> node4(s41)*. % 76.16/76.34 142481[84:MRR:795.0,142479.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 142484[84:Res:53.1,142481.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 142486[85:Spt:142484.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 142488[85:Res:142486.0,61.1] always3(s41) || -> . % 76.16/76.34 142489[85:SSi:142488.0,78250.0,78253.0,137763.0,142310.0,142479.0] || -> . % 76.16/76.34 142490[85:Spt:142489.0,142484.0,142486.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 142491[85:Spt:142489.0,142484.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 142495[85:Res:142491.0,61.1] always3(s42) || -> . % 76.16/76.34 142496[85:SSi:142495.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 142497[83:Spt:142496.0,142309.0,142310.0] || until2p7(s41)*+ -> . % 76.16/76.34 142498[83:Spt:142496.0,142309.1] || -> node4(s40)*. % 76.16/76.34 142500[83:MRR:798.0,142498.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 142503[83:Res:53.1,142500.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 142505[84:Spt:142503.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 142507[84:Res:142505.0,61.1] always3(s40) || -> . % 76.16/76.34 142508[84:SSi:142507.0,78245.0,78249.0,137762.0,142308.0,142498.0] || -> . % 76.16/76.34 142509[84:Spt:142508.0,142503.0,142505.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 142510[84:Spt:142508.0,142503.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 142514[84:Res:142510.0,61.1] always3(s41) || -> . % 76.16/76.34 142515[84:SSi:142514.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 142516[82:Spt:142515.0,142307.0,142308.0] || until2p7(s40)*+ -> . % 76.16/76.34 142517[82:Spt:142515.0,142307.1] || -> node4(s39)*. % 76.16/76.34 142519[82:MRR:801.0,142517.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 142522[82:Res:53.1,142519.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 142524[83:Spt:142522.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 142526[83:Res:142524.0,61.1] always3(s39) || -> . % 76.16/76.34 142527[83:SSi:142526.0,78241.0,78244.0,137761.0,142306.0,142517.0] || -> . % 76.16/76.34 142528[83:Spt:142527.0,142522.0,142524.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 142529[83:Spt:142527.0,142522.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 142533[83:Res:142529.0,61.1] always3(s40) || -> . % 76.16/76.34 142534[83:SSi:142533.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 142535[81:Spt:142534.0,142305.0,142306.0] || until2p7(s39)*+ -> . % 76.16/76.34 142536[81:Spt:142534.0,142305.1] || -> node4(s38)*. % 76.16/76.34 142538[81:MRR:804.0,142536.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 142541[81:Res:53.1,142538.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 142546[82:Spt:142541.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 142548[82:Res:142546.0,61.1] always3(s38) || -> . % 76.16/76.34 142549[82:SSi:142548.0,78236.0,78240.0,137760.0,142304.0,142536.0] || -> . % 76.16/76.34 142550[82:Spt:142549.0,142541.0,142546.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 142551[82:Spt:142549.0,142541.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 142555[82:Res:142551.0,61.1] always3(s39) || -> . % 76.16/76.34 142556[82:SSi:142555.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 142557[80:Spt:142556.0,142303.0,142304.0] || until2p7(s38)*+ -> . % 76.16/76.34 142558[80:Spt:142556.0,142303.1] || -> node4(s37)*. % 76.16/76.34 142560[80:MRR:807.0,142558.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 142563[80:Res:53.1,142560.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 142565[81:Spt:142563.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 142567[81:Res:142565.0,61.1] always3(s37) || -> . % 76.16/76.34 142568[81:SSi:142567.0,78232.0,78235.0,137759.0,142302.0,142558.0] || -> . % 76.16/76.34 142569[81:Spt:142568.0,142563.0,142565.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 142570[81:Spt:142568.0,142563.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 142574[81:Res:142570.0,61.1] always3(s38) || -> . % 76.16/76.34 142575[81:SSi:142574.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 142576[79:Spt:142575.0,142301.0,142302.0] || until2p7(s37)*+ -> . % 76.16/76.34 142577[79:Spt:142575.0,142301.1] || -> node4(s36)*. % 76.16/76.34 142579[79:MRR:810.0,142577.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 142582[79:Res:53.1,142579.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 142584[80:Spt:142582.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 142586[80:Res:142584.0,61.1] always3(s36) || -> . % 76.16/76.34 142587[80:SSi:142586.0,78227.0,78231.0,137758.0,142300.0,142577.0] || -> . % 76.16/76.34 142588[80:Spt:142587.0,142582.0,142584.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 142589[80:Spt:142587.0,142582.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 142593[80:Res:142589.0,61.1] always3(s37) || -> . % 76.16/76.34 142594[80:SSi:142593.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 142595[78:Spt:142594.0,142299.0,142300.0] || until2p7(s36)*+ -> . % 76.16/76.34 142596[78:Spt:142594.0,142299.1] || -> node4(s35)*. % 76.16/76.34 142598[78:MRR:813.0,142596.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 142601[78:Res:53.1,142598.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 142603[79:Spt:142601.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 142605[79:Res:142603.0,61.1] always3(s35) || -> . % 76.16/76.34 142606[79:SSi:142605.0,78223.0,78226.0,137757.0,142298.0,142596.0] || -> . % 76.16/76.34 142607[79:Spt:142606.0,142601.0,142603.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 142608[79:Spt:142606.0,142601.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 142612[79:Res:142608.0,61.1] always3(s36) || -> . % 76.16/76.34 142613[79:SSi:142612.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 142614[77:Spt:142613.0,142297.0,142298.0] || until2p7(s35)*+ -> . % 76.16/76.34 142615[77:Spt:142613.0,142297.1] || -> node4(s34)*. % 76.16/76.34 142617[77:MRR:816.0,142615.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 142620[77:Res:53.1,142617.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 142625[78:Spt:142620.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 142627[78:Res:142625.0,61.1] always3(s34) || -> . % 76.16/76.34 142628[78:SSi:142627.0,78218.0,78222.0,137756.0,142296.0,142615.0] || -> . % 76.16/76.34 142629[78:Spt:142628.0,142620.0,142625.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 142630[78:Spt:142628.0,142620.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 142634[78:Res:142630.0,61.1] always3(s35) || -> . % 76.16/76.34 142635[78:SSi:142634.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 142636[76:Spt:142635.0,142295.0,142296.0] || until2p7(s34)*+ -> . % 76.16/76.34 142637[76:Spt:142635.0,142295.1] || -> node4(s33)*. % 76.16/76.34 142639[76:MRR:819.0,142637.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 142642[76:Res:53.1,142639.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 142644[77:Spt:142642.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 142646[77:Res:142644.0,61.1] always3(s33) || -> . % 76.16/76.34 142647[77:SSi:142646.0,78214.0,78217.0,137755.0,142294.0,142637.0] || -> . % 76.16/76.34 142648[77:Spt:142647.0,142642.0,142644.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.34 142649[77:Spt:142647.0,142642.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 142653[77:Res:142649.0,61.1] always3(s34) || -> . % 76.16/76.34 142654[77:SSi:142653.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 142655[75:Spt:142654.0,142293.0,142294.0] || until2p7(s33)*+ -> . % 76.16/76.34 142656[75:Spt:142654.0,142293.1] || -> node4(s32)*. % 76.16/76.34 142658[75:MRR:822.0,142656.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.34 142661[75:Res:53.1,142658.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.34 142663[76:Spt:142661.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 142665[76:Res:142663.0,61.1] always3(s32) || -> . % 76.16/76.34 142666[76:SSi:142665.0,78209.0,78213.0,137754.0,142292.0,142656.0] || -> . % 76.16/76.34 142667[76:Spt:142666.0,142661.0,142663.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.34 142668[76:Spt:142666.0,142661.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 142672[76:Res:142668.0,61.1] always3(s33) || -> . % 76.16/76.34 142673[76:SSi:142672.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 142674[74:Spt:142673.0,142291.0,142292.0] || until2p7(s32)*+ -> . % 76.16/76.34 142675[74:Spt:142673.0,142291.1] || -> node4(s31)*. % 76.16/76.34 142677[74:MRR:825.0,142675.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.34 142680[74:Res:53.1,142677.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.34 142682[74:MRR:142680.0,142281.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 142684[74:Res:142682.0,61.1] always3(s32) || -> . % 76.16/76.34 142685[74:SSi:142684.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.34 142686[72:Spt:142685.0,142205.0,142208.0] || trans(s49,s31)*+ -> . % 76.16/76.34 142687[72:Spt:142685.0,142205.1,142205.2,142205.3,142205.4,142205.5,142205.6,142205.7,142205.8,142205.9,142205.10,142205.11,142205.12,142205.13,142205.14,142205.15,142205.16,142205.17,142205.18,142205.19,142205.20,142205.21,142205.22,142205.23,142205.24,142205.25,142205.26,142205.27] || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 142689[72:MRR:142207.1,142686.0] xuntil6(s49) || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 142690[73:Spt:142687.0] || -> trans(s49,s30)*. % 76.16/76.34 142691[73:Res:142690.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s30)*. % 76.16/76.34 142693[73:Res:142690.0,60.0] || -> node2(s49,s30)*. % 76.16/76.34 142694[73:SSi:142691.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s30)*. % 76.16/76.34 142695[73:Res:142693.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 142762[73:SoR:142695.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 142764[73:SoR:142762.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)* xuntil6(s49). % 76.16/76.34 142765[73:SSi:142764.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s30,c_busy)* xuntil6(s49). % 76.16/76.34 142766[74:Spt:142765.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 142768[74:Res:142766.0,61.1] always3(s30) || -> . % 76.16/76.34 142769[74:SSi:142768.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.34 142770[74:Spt:142769.0,142765.1,142766.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.16/76.34 142771[74:Spt:142769.0,142765.0,142765.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 142775[74:MRR:142762.2,142770.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 142776[74:Res:53.1,142771.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 142778[74:MRR:142776.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 142779[74:MRR:142694.0,142778.0] || -> until2p7(s30)*. % 76.16/76.34 142780[74:MRR:226.0,142779.0] || -> until2p7(s31)* node4(s30). % 76.16/76.34 142781[75:Spt:142780.0] || -> until2p7(s31)*. % 76.16/76.34 142782[75:MRR:227.0,142781.0] || -> until2p7(s32)* node4(s31). % 76.16/76.34 142783[76:Spt:142782.0] || -> until2p7(s32)*. % 76.16/76.34 142784[76:MRR:228.0,142783.0] || -> until2p7(s33)* node4(s32). % 76.16/76.34 142785[77:Spt:142784.0] || -> until2p7(s33)*. % 76.16/76.34 142786[77:MRR:229.0,142785.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 142787[78:Spt:142786.0] || -> until2p7(s34)*. % 76.16/76.34 142788[78:MRR:230.0,142787.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 142789[79:Spt:142788.0] || -> until2p7(s35)*. % 76.16/76.34 142790[79:MRR:231.0,142789.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 142791[80:Spt:142790.0] || -> until2p7(s36)*. % 76.16/76.34 142792[80:MRR:232.0,142791.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 142793[81:Spt:142792.0] || -> until2p7(s37)*. % 76.16/76.34 142794[81:MRR:235.0,142793.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 142795[82:Spt:142794.0] || -> until2p7(s38)*. % 76.16/76.34 142796[82:MRR:236.0,142795.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 142797[83:Spt:142796.0] || -> until2p7(s39)*. % 76.16/76.34 142798[83:MRR:237.0,142797.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 142799[84:Spt:142798.0] || -> until2p7(s40)*. % 76.16/76.34 142800[84:MRR:238.0,142799.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 142801[85:Spt:142800.0] || -> until2p7(s41)*. % 76.16/76.34 142802[85:MRR:239.0,142801.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 142803[86:Spt:142802.0] || -> until2p7(s42)*. % 76.16/76.34 142804[86:MRR:240.0,142803.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 142805[87:Spt:142804.0] || -> until2p7(s43)*. % 76.16/76.34 142806[87:MRR:241.0,142805.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 142807[88:Spt:142806.0] || -> until2p7(s44)*. % 76.16/76.34 142808[88:MRR:539.0,142807.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 142809[89:Spt:142808.0] || -> until2p7(s45)*. % 76.16/76.34 142810[89:MRR:544.0,142809.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 142811[90:Spt:142810.0] || -> until2p7(s46)*. % 76.16/76.34 142812[90:MRR:549.0,142811.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 142813[91:Spt:142812.0] || -> until2p7(s47)*. % 76.16/76.34 142814[91:MRR:554.0,142813.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 142815[92:Spt:142814.0] || -> until2p7(s48)*. % 76.16/76.34 142816[92:MRR:559.0,142815.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 142817[93:Spt:142816.0] || -> until2p7(s49)*. % 76.16/76.34 142818[93:MRR:194.0,142817.0] || -> node4(s49)*. % 76.16/76.34 142819[93:MRR:142775.0,142818.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 142820[93:Res:53.1,142819.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 142822[93:MRR:142820.0,78381.0] || -> . % 76.16/76.34 142823[93:Spt:142822.0,142816.0,142817.0] || until2p7(s49)*+ -> . % 76.16/76.34 142824[93:Spt:142822.0,142816.1] || -> node4(s48)*. % 76.16/76.34 142825[93:MRR:78384.0,142824.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 142828[93:Res:53.1,142825.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 142831[93:Res:142828.0,61.1] always3(s48) || -> . % 76.16/76.34 142832[93:SSi:142831.0,78281.0,78387.0,137770.0,142815.0,142824.0] || -> . % 76.16/76.34 142833[92:Spt:142832.0,142814.0,142815.0] || until2p7(s48)*+ -> . % 76.16/76.34 142834[92:Spt:142832.0,142814.1] || -> node4(s47)*. % 76.16/76.34 142836[92:MRR:777.0,142834.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 142851[92:Res:53.1,142836.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 142853[93:Spt:142851.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 142855[93:Res:142853.0,61.1] always3(s47) || -> . % 76.16/76.34 142856[93:SSi:142855.0,78277.0,78280.0,137769.0,142813.0,142834.0] || -> . % 76.16/76.34 142857[93:Spt:142856.0,142851.0,142853.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 142858[93:Spt:142856.0,142851.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 142862[93:Res:142858.0,61.1] always3(s48) || -> . % 76.16/76.34 142863[93:SSi:142862.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 142864[91:Spt:142863.0,142812.0,142813.0] || until2p7(s47)*+ -> . % 76.16/76.34 142865[91:Spt:142863.0,142812.1] || -> node4(s46)*. % 76.16/76.34 142867[91:MRR:780.0,142865.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 142877[91:Res:53.1,142867.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 142879[92:Spt:142877.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 142881[92:Res:142879.0,61.1] always3(s46) || -> . % 76.16/76.34 142882[92:SSi:142881.0,78272.0,78276.0,137768.0,142811.0,142865.0] || -> . % 76.16/76.34 142883[92:Spt:142882.0,142877.0,142879.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 142884[92:Spt:142882.0,142877.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 142888[92:Res:142884.0,61.1] always3(s47) || -> . % 76.16/76.34 142889[92:SSi:142888.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 142890[90:Spt:142889.0,142810.0,142811.0] || until2p7(s46)*+ -> . % 76.16/76.34 142891[90:Spt:142889.0,142810.1] || -> node4(s45)*. % 76.16/76.34 142893[90:MRR:783.0,142891.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 142896[90:Res:53.1,142893.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 142898[91:Spt:142896.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 142900[91:Res:142898.0,61.1] always3(s45) || -> . % 76.16/76.34 142901[91:SSi:142900.0,78268.0,78271.0,137767.0,142809.0,142891.0] || -> . % 76.16/76.34 142902[91:Spt:142901.0,142896.0,142898.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 142903[91:Spt:142901.0,142896.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 142907[91:Res:142903.0,61.1] always3(s46) || -> . % 76.16/76.34 142908[91:SSi:142907.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 142909[89:Spt:142908.0,142808.0,142809.0] || until2p7(s45)*+ -> . % 76.16/76.34 142910[89:Spt:142908.0,142808.1] || -> node4(s44)*. % 76.16/76.34 142912[89:MRR:786.0,142910.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 142915[89:Res:53.1,142912.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 142917[90:Spt:142915.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 142919[90:Res:142917.0,61.1] always3(s44) || -> . % 76.16/76.34 142920[90:SSi:142919.0,78263.0,78267.0,137766.0,142807.0,142910.0] || -> . % 76.16/76.34 142921[90:Spt:142920.0,142915.0,142917.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 142922[90:Spt:142920.0,142915.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 142926[90:Res:142922.0,61.1] always3(s45) || -> . % 76.16/76.34 142927[90:SSi:142926.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 142928[88:Spt:142927.0,142806.0,142807.0] || until2p7(s44)*+ -> . % 76.16/76.34 142929[88:Spt:142927.0,142806.1] || -> node4(s43)*. % 76.16/76.34 142931[88:MRR:789.0,142929.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 142934[88:Res:53.1,142931.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 142939[89:Spt:142934.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 142941[89:Res:142939.0,61.1] always3(s43) || -> . % 76.16/76.34 142942[89:SSi:142941.0,78259.0,78262.0,137765.0,142805.0,142929.0] || -> . % 76.16/76.34 142943[89:Spt:142942.0,142934.0,142939.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 142944[89:Spt:142942.0,142934.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 142948[89:Res:142944.0,61.1] always3(s44) || -> . % 76.16/76.34 142949[89:SSi:142948.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 142950[87:Spt:142949.0,142804.0,142805.0] || until2p7(s43)*+ -> . % 76.16/76.34 142951[87:Spt:142949.0,142804.1] || -> node4(s42)*. % 76.16/76.34 142953[87:MRR:792.0,142951.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 142956[87:Res:53.1,142953.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 142958[88:Spt:142956.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 142960[88:Res:142958.0,61.1] always3(s42) || -> . % 76.16/76.34 142961[88:SSi:142960.0,78254.0,78258.0,137764.0,142803.0,142951.0] || -> . % 76.16/76.34 142962[88:Spt:142961.0,142956.0,142958.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 142963[88:Spt:142961.0,142956.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 142967[88:Res:142963.0,61.1] always3(s43) || -> . % 76.16/76.34 142968[88:SSi:142967.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 142969[86:Spt:142968.0,142802.0,142803.0] || until2p7(s42)*+ -> . % 76.16/76.34 142970[86:Spt:142968.0,142802.1] || -> node4(s41)*. % 76.16/76.34 142972[86:MRR:795.0,142970.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 142975[86:Res:53.1,142972.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 142977[87:Spt:142975.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 142979[87:Res:142977.0,61.1] always3(s41) || -> . % 76.16/76.34 142980[87:SSi:142979.0,78250.0,78253.0,137763.0,142801.0,142970.0] || -> . % 76.16/76.34 142981[87:Spt:142980.0,142975.0,142977.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 142982[87:Spt:142980.0,142975.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 142986[87:Res:142982.0,61.1] always3(s42) || -> . % 76.16/76.34 142987[87:SSi:142986.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 142988[85:Spt:142987.0,142800.0,142801.0] || until2p7(s41)*+ -> . % 76.16/76.34 142989[85:Spt:142987.0,142800.1] || -> node4(s40)*. % 76.16/76.34 142991[85:MRR:798.0,142989.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 142994[85:Res:53.1,142991.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 142996[86:Spt:142994.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 142998[86:Res:142996.0,61.1] always3(s40) || -> . % 76.16/76.34 142999[86:SSi:142998.0,78245.0,78249.0,137762.0,142799.0,142989.0] || -> . % 76.16/76.34 143000[86:Spt:142999.0,142994.0,142996.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 143001[86:Spt:142999.0,142994.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 143005[86:Res:143001.0,61.1] always3(s41) || -> . % 76.16/76.34 143006[86:SSi:143005.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 143007[84:Spt:143006.0,142798.0,142799.0] || until2p7(s40)*+ -> . % 76.16/76.34 143008[84:Spt:143006.0,142798.1] || -> node4(s39)*. % 76.16/76.34 143010[84:MRR:801.0,143008.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 143013[84:Res:53.1,143010.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 143018[85:Spt:143013.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 143020[85:Res:143018.0,61.1] always3(s39) || -> . % 76.16/76.34 143021[85:SSi:143020.0,78241.0,78244.0,137761.0,142797.0,143008.0] || -> . % 76.16/76.34 143022[85:Spt:143021.0,143013.0,143018.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 143023[85:Spt:143021.0,143013.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 143027[85:Res:143023.0,61.1] always3(s40) || -> . % 76.16/76.34 143028[85:SSi:143027.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 143029[83:Spt:143028.0,142796.0,142797.0] || until2p7(s39)*+ -> . % 76.16/76.34 143030[83:Spt:143028.0,142796.1] || -> node4(s38)*. % 76.16/76.34 143032[83:MRR:804.0,143030.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 143035[83:Res:53.1,143032.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 143037[84:Spt:143035.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 143039[84:Res:143037.0,61.1] always3(s38) || -> . % 76.16/76.34 143040[84:SSi:143039.0,78236.0,78240.0,137760.0,142795.0,143030.0] || -> . % 76.16/76.34 143041[84:Spt:143040.0,143035.0,143037.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 143042[84:Spt:143040.0,143035.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 143046[84:Res:143042.0,61.1] always3(s39) || -> . % 76.16/76.34 143047[84:SSi:143046.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 143048[82:Spt:143047.0,142794.0,142795.0] || until2p7(s38)*+ -> . % 76.16/76.34 143049[82:Spt:143047.0,142794.1] || -> node4(s37)*. % 76.16/76.34 143051[82:MRR:807.0,143049.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 143054[82:Res:53.1,143051.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 143056[83:Spt:143054.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 143058[83:Res:143056.0,61.1] always3(s37) || -> . % 76.16/76.34 143059[83:SSi:143058.0,78232.0,78235.0,137759.0,142793.0,143049.0] || -> . % 76.16/76.34 143060[83:Spt:143059.0,143054.0,143056.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 143061[83:Spt:143059.0,143054.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 143065[83:Res:143061.0,61.1] always3(s38) || -> . % 76.16/76.34 143066[83:SSi:143065.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 143067[81:Spt:143066.0,142792.0,142793.0] || until2p7(s37)*+ -> . % 76.16/76.34 143068[81:Spt:143066.0,142792.1] || -> node4(s36)*. % 76.16/76.34 143070[81:MRR:810.0,143068.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 143073[81:Res:53.1,143070.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 143075[82:Spt:143073.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 143077[82:Res:143075.0,61.1] always3(s36) || -> . % 76.16/76.34 143078[82:SSi:143077.0,78227.0,78231.0,137758.0,142791.0,143068.0] || -> . % 76.16/76.34 143079[82:Spt:143078.0,143073.0,143075.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 143080[82:Spt:143078.0,143073.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 143084[82:Res:143080.0,61.1] always3(s37) || -> . % 76.16/76.34 143085[82:SSi:143084.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 143086[80:Spt:143085.0,142790.0,142791.0] || until2p7(s36)*+ -> . % 76.16/76.34 143087[80:Spt:143085.0,142790.1] || -> node4(s35)*. % 76.16/76.34 143089[80:MRR:813.0,143087.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 143092[80:Res:53.1,143089.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 143097[81:Spt:143092.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 143099[81:Res:143097.0,61.1] always3(s35) || -> . % 76.16/76.34 143100[81:SSi:143099.0,78223.0,78226.0,137757.0,142789.0,143087.0] || -> . % 76.16/76.34 143101[81:Spt:143100.0,143092.0,143097.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 143102[81:Spt:143100.0,143092.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 143106[81:Res:143102.0,61.1] always3(s36) || -> . % 76.16/76.34 143107[81:SSi:143106.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 143108[79:Spt:143107.0,142788.0,142789.0] || until2p7(s35)*+ -> . % 76.16/76.34 143109[79:Spt:143107.0,142788.1] || -> node4(s34)*. % 76.16/76.34 143111[79:MRR:816.0,143109.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 143114[79:Res:53.1,143111.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 143116[80:Spt:143114.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 143118[80:Res:143116.0,61.1] always3(s34) || -> . % 76.16/76.34 143119[80:SSi:143118.0,78218.0,78222.0,137756.0,142787.0,143109.0] || -> . % 76.16/76.34 143120[80:Spt:143119.0,143114.0,143116.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 143121[80:Spt:143119.0,143114.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 143125[80:Res:143121.0,61.1] always3(s35) || -> . % 76.16/76.34 143126[80:SSi:143125.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 143127[78:Spt:143126.0,142786.0,142787.0] || until2p7(s34)*+ -> . % 76.16/76.34 143128[78:Spt:143126.0,142786.1] || -> node4(s33)*. % 76.16/76.34 143130[78:MRR:819.0,143128.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 143133[78:Res:53.1,143130.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 143135[79:Spt:143133.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 143137[79:Res:143135.0,61.1] always3(s33) || -> . % 76.16/76.34 143138[79:SSi:143137.0,78214.0,78217.0,137755.0,142785.0,143128.0] || -> . % 76.16/76.34 143139[79:Spt:143138.0,143133.0,143135.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.34 143140[79:Spt:143138.0,143133.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 143144[79:Res:143140.0,61.1] always3(s34) || -> . % 76.16/76.34 143145[79:SSi:143144.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 143146[77:Spt:143145.0,142784.0,142785.0] || until2p7(s33)*+ -> . % 76.16/76.34 143147[77:Spt:143145.0,142784.1] || -> node4(s32)*. % 76.16/76.34 143149[77:MRR:822.0,143147.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.34 143152[77:Res:53.1,143149.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.34 143154[78:Spt:143152.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 143156[78:Res:143154.0,61.1] always3(s32) || -> . % 76.16/76.34 143157[78:SSi:143156.0,78209.0,78213.0,137754.0,142783.0,143147.0] || -> . % 76.16/76.34 143158[78:Spt:143157.0,143152.0,143154.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.34 143159[78:Spt:143157.0,143152.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 143163[78:Res:143159.0,61.1] always3(s33) || -> . % 76.16/76.34 143164[78:SSi:143163.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 143165[76:Spt:143164.0,142782.0,142783.0] || until2p7(s32)*+ -> . % 76.16/76.34 143166[76:Spt:143164.0,142782.1] || -> node4(s31)*. % 76.16/76.34 143168[76:MRR:825.0,143166.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.34 143171[76:Res:53.1,143168.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.34 143176[77:Spt:143171.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 143178[77:Res:143176.0,61.1] always3(s31) || -> . % 76.16/76.34 143179[77:SSi:143178.0,78205.0,78208.0,137753.0,142781.0,143166.0] || -> . % 76.16/76.34 143180[77:Spt:143179.0,143171.0,143176.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.34 143181[77:Spt:143179.0,143171.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 143185[77:Res:143181.0,61.1] always3(s32) || -> . % 76.16/76.34 143186[77:SSi:143185.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.34 143187[75:Spt:143186.0,142780.0,142781.0] || until2p7(s31)*+ -> . % 76.16/76.34 143188[75:Spt:143186.0,142780.1] || -> node4(s30)*. % 76.16/76.34 143190[75:MRR:828.0,143188.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.34 143193[75:Res:53.1,143190.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.34 143195[75:MRR:143193.0,142770.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 143197[75:Res:143195.0,61.1] always3(s31) || -> . % 76.16/76.34 143198[75:SSi:143197.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.34 143199[73:Spt:143198.0,142687.0,142690.0] || trans(s49,s30)*+ -> . % 76.16/76.34 143200[73:Spt:143198.0,142687.1,142687.2,142687.3,142687.4,142687.5,142687.6,142687.7,142687.8,142687.9,142687.10,142687.11,142687.12,142687.13,142687.14,142687.15,142687.16,142687.17,142687.18,142687.19,142687.20,142687.21,142687.22,142687.23,142687.24,142687.25,142687.26] || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 143202[73:MRR:142689.1,143199.0] xuntil6(s49) || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 143203[74:Spt:143200.0] || -> trans(s49,s29)*. % 76.16/76.34 143204[74:Res:143203.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s29)*. % 76.16/76.34 143206[74:Res:143203.0,60.0] || -> node2(s49,s29)*. % 76.16/76.34 143207[74:SSi:143204.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s29)*. % 76.16/76.34 143208[74:Res:143206.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 143276[74:SoR:143208.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 143278[74:SoR:143276.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.16/76.34 143279[74:SSi:143278.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.16/76.34 143280[75:Spt:143279.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 143282[75:Res:143280.0,61.1] always3(s29) || -> . % 76.16/76.34 143283[75:SSi:143282.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.34 143284[75:Spt:143283.0,143279.1,143280.0] || m_main_v_state(s29,c_busy)*+ -> . % 76.16/76.34 143285[75:Spt:143283.0,143279.0,143279.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 143289[75:MRR:143276.2,143284.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 143290[75:Res:53.1,143285.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 143292[75:MRR:143290.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 143293[75:MRR:143207.0,143292.0] || -> until2p7(s29)*. % 76.16/76.34 143294[75:MRR:225.0,143293.0] || -> until2p7(s30)* node4(s29). % 76.16/76.34 143295[76:Spt:143294.0] || -> until2p7(s30)*. % 76.16/76.34 143296[76:MRR:226.0,143295.0] || -> until2p7(s31)* node4(s30). % 76.16/76.34 143297[77:Spt:143296.0] || -> until2p7(s31)*. % 76.16/76.34 143298[77:MRR:227.0,143297.0] || -> until2p7(s32)* node4(s31). % 76.16/76.34 143299[78:Spt:143298.0] || -> until2p7(s32)*. % 76.16/76.34 143300[78:MRR:228.0,143299.0] || -> until2p7(s33)* node4(s32). % 76.16/76.34 143301[79:Spt:143300.0] || -> until2p7(s33)*. % 76.16/76.34 143302[79:MRR:229.0,143301.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 143303[80:Spt:143302.0] || -> until2p7(s34)*. % 76.16/76.34 143304[80:MRR:230.0,143303.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 143305[81:Spt:143304.0] || -> until2p7(s35)*. % 76.16/76.34 143306[81:MRR:231.0,143305.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 143307[82:Spt:143306.0] || -> until2p7(s36)*. % 76.16/76.34 143308[82:MRR:232.0,143307.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 143309[83:Spt:143308.0] || -> until2p7(s37)*. % 76.16/76.34 143310[83:MRR:235.0,143309.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 143311[84:Spt:143310.0] || -> until2p7(s38)*. % 76.16/76.34 143312[84:MRR:236.0,143311.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 143313[85:Spt:143312.0] || -> until2p7(s39)*. % 76.16/76.34 143314[85:MRR:237.0,143313.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 143315[86:Spt:143314.0] || -> until2p7(s40)*. % 76.16/76.34 143316[86:MRR:238.0,143315.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 143317[87:Spt:143316.0] || -> until2p7(s41)*. % 76.16/76.34 143318[87:MRR:239.0,143317.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 143319[88:Spt:143318.0] || -> until2p7(s42)*. % 76.16/76.34 143320[88:MRR:240.0,143319.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 143321[89:Spt:143320.0] || -> until2p7(s43)*. % 76.16/76.34 143322[89:MRR:241.0,143321.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 143323[90:Spt:143322.0] || -> until2p7(s44)*. % 76.16/76.34 143324[90:MRR:539.0,143323.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 143325[91:Spt:143324.0] || -> until2p7(s45)*. % 76.16/76.34 143326[91:MRR:544.0,143325.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 143327[92:Spt:143326.0] || -> until2p7(s46)*. % 76.16/76.34 143328[92:MRR:549.0,143327.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 143329[93:Spt:143328.0] || -> until2p7(s47)*. % 76.16/76.34 143330[93:MRR:554.0,143329.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 143331[94:Spt:143330.0] || -> until2p7(s48)*. % 76.16/76.34 143332[94:MRR:559.0,143331.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 143333[95:Spt:143332.0] || -> until2p7(s49)*. % 76.16/76.34 143334[95:MRR:194.0,143333.0] || -> node4(s49)*. % 76.16/76.34 143335[95:MRR:143289.0,143334.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 143336[95:Res:53.1,143335.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 143338[95:MRR:143336.0,78381.0] || -> . % 76.16/76.34 143339[95:Spt:143338.0,143332.0,143333.0] || until2p7(s49)*+ -> . % 76.16/76.34 143340[95:Spt:143338.0,143332.1] || -> node4(s48)*. % 76.16/76.34 143341[95:MRR:78384.0,143340.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 143344[95:Res:53.1,143341.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 143347[95:Res:143344.0,61.1] always3(s48) || -> . % 76.16/76.34 143348[95:SSi:143347.0,78281.0,78387.0,137770.0,143331.0,143340.0] || -> . % 76.16/76.34 143349[94:Spt:143348.0,143330.0,143331.0] || until2p7(s48)*+ -> . % 76.16/76.34 143350[94:Spt:143348.0,143330.1] || -> node4(s47)*. % 76.16/76.34 143352[94:MRR:777.0,143350.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 143367[94:Res:53.1,143352.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 143369[95:Spt:143367.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 143371[95:Res:143369.0,61.1] always3(s47) || -> . % 76.16/76.34 143372[95:SSi:143371.0,78277.0,78280.0,137769.0,143329.0,143350.0] || -> . % 76.16/76.34 143373[95:Spt:143372.0,143367.0,143369.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 143374[95:Spt:143372.0,143367.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 143378[95:Res:143374.0,61.1] always3(s48) || -> . % 76.16/76.34 143379[95:SSi:143378.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 143380[93:Spt:143379.0,143328.0,143329.0] || until2p7(s47)*+ -> . % 76.16/76.34 143381[93:Spt:143379.0,143328.1] || -> node4(s46)*. % 76.16/76.34 143383[93:MRR:780.0,143381.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 143393[93:Res:53.1,143383.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 143395[94:Spt:143393.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 143397[94:Res:143395.0,61.1] always3(s46) || -> . % 76.16/76.34 143398[94:SSi:143397.0,78272.0,78276.0,137768.0,143327.0,143381.0] || -> . % 76.16/76.34 143399[94:Spt:143398.0,143393.0,143395.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 143400[94:Spt:143398.0,143393.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 143404[94:Res:143400.0,61.1] always3(s47) || -> . % 76.16/76.34 143405[94:SSi:143404.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 143406[92:Spt:143405.0,143326.0,143327.0] || until2p7(s46)*+ -> . % 76.16/76.34 143407[92:Spt:143405.0,143326.1] || -> node4(s45)*. % 76.16/76.34 143409[92:MRR:783.0,143407.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 143412[92:Res:53.1,143409.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 143414[93:Spt:143412.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 143416[93:Res:143414.0,61.1] always3(s45) || -> . % 76.16/76.34 143417[93:SSi:143416.0,78268.0,78271.0,137767.0,143325.0,143407.0] || -> . % 76.16/76.34 143418[93:Spt:143417.0,143412.0,143414.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 143419[93:Spt:143417.0,143412.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 143423[93:Res:143419.0,61.1] always3(s46) || -> . % 76.16/76.34 143424[93:SSi:143423.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 143425[91:Spt:143424.0,143324.0,143325.0] || until2p7(s45)*+ -> . % 76.16/76.34 143426[91:Spt:143424.0,143324.1] || -> node4(s44)*. % 76.16/76.34 143428[91:MRR:786.0,143426.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 143431[91:Res:53.1,143428.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 143433[92:Spt:143431.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 143435[92:Res:143433.0,61.1] always3(s44) || -> . % 76.16/76.34 143436[92:SSi:143435.0,78263.0,78267.0,137766.0,143323.0,143426.0] || -> . % 76.16/76.34 143437[92:Spt:143436.0,143431.0,143433.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 143438[92:Spt:143436.0,143431.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 143442[92:Res:143438.0,61.1] always3(s45) || -> . % 76.16/76.34 143443[92:SSi:143442.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 143444[90:Spt:143443.0,143322.0,143323.0] || until2p7(s44)*+ -> . % 76.16/76.34 143445[90:Spt:143443.0,143322.1] || -> node4(s43)*. % 76.16/76.34 143447[90:MRR:789.0,143445.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 143450[90:Res:53.1,143447.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 143455[91:Spt:143450.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 143457[91:Res:143455.0,61.1] always3(s43) || -> . % 76.16/76.34 143458[91:SSi:143457.0,78259.0,78262.0,137765.0,143321.0,143445.0] || -> . % 76.16/76.34 143459[91:Spt:143458.0,143450.0,143455.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 143460[91:Spt:143458.0,143450.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 143464[91:Res:143460.0,61.1] always3(s44) || -> . % 76.16/76.34 143465[91:SSi:143464.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 143466[89:Spt:143465.0,143320.0,143321.0] || until2p7(s43)*+ -> . % 76.16/76.34 143467[89:Spt:143465.0,143320.1] || -> node4(s42)*. % 76.16/76.34 143469[89:MRR:792.0,143467.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 143472[89:Res:53.1,143469.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 143474[90:Spt:143472.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 143476[90:Res:143474.0,61.1] always3(s42) || -> . % 76.16/76.34 143477[90:SSi:143476.0,78254.0,78258.0,137764.0,143319.0,143467.0] || -> . % 76.16/76.34 143478[90:Spt:143477.0,143472.0,143474.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 143479[90:Spt:143477.0,143472.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 143483[90:Res:143479.0,61.1] always3(s43) || -> . % 76.16/76.34 143484[90:SSi:143483.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 143485[88:Spt:143484.0,143318.0,143319.0] || until2p7(s42)*+ -> . % 76.16/76.34 143486[88:Spt:143484.0,143318.1] || -> node4(s41)*. % 76.16/76.34 143488[88:MRR:795.0,143486.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 143491[88:Res:53.1,143488.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 143493[89:Spt:143491.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 143495[89:Res:143493.0,61.1] always3(s41) || -> . % 76.16/76.34 143496[89:SSi:143495.0,78250.0,78253.0,137763.0,143317.0,143486.0] || -> . % 76.16/76.34 143497[89:Spt:143496.0,143491.0,143493.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 143498[89:Spt:143496.0,143491.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 143502[89:Res:143498.0,61.1] always3(s42) || -> . % 76.16/76.34 143503[89:SSi:143502.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 143504[87:Spt:143503.0,143316.0,143317.0] || until2p7(s41)*+ -> . % 76.16/76.34 143505[87:Spt:143503.0,143316.1] || -> node4(s40)*. % 76.16/76.34 143507[87:MRR:798.0,143505.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 143510[87:Res:53.1,143507.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 143512[88:Spt:143510.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 143514[88:Res:143512.0,61.1] always3(s40) || -> . % 76.16/76.34 143515[88:SSi:143514.0,78245.0,78249.0,137762.0,143315.0,143505.0] || -> . % 76.16/76.34 143516[88:Spt:143515.0,143510.0,143512.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 143517[88:Spt:143515.0,143510.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 143521[88:Res:143517.0,61.1] always3(s41) || -> . % 76.16/76.34 143522[88:SSi:143521.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 143523[86:Spt:143522.0,143314.0,143315.0] || until2p7(s40)*+ -> . % 76.16/76.34 143524[86:Spt:143522.0,143314.1] || -> node4(s39)*. % 76.16/76.34 143526[86:MRR:801.0,143524.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 143529[86:Res:53.1,143526.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 143534[87:Spt:143529.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 143536[87:Res:143534.0,61.1] always3(s39) || -> . % 76.16/76.34 143537[87:SSi:143536.0,78241.0,78244.0,137761.0,143313.0,143524.0] || -> . % 76.16/76.34 143538[87:Spt:143537.0,143529.0,143534.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 143539[87:Spt:143537.0,143529.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 143543[87:Res:143539.0,61.1] always3(s40) || -> . % 76.16/76.34 143544[87:SSi:143543.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 143545[85:Spt:143544.0,143312.0,143313.0] || until2p7(s39)*+ -> . % 76.16/76.34 143546[85:Spt:143544.0,143312.1] || -> node4(s38)*. % 76.16/76.34 143548[85:MRR:804.0,143546.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 143551[85:Res:53.1,143548.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 143553[86:Spt:143551.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 143555[86:Res:143553.0,61.1] always3(s38) || -> . % 76.16/76.34 143556[86:SSi:143555.0,78236.0,78240.0,137760.0,143311.0,143546.0] || -> . % 76.16/76.34 143557[86:Spt:143556.0,143551.0,143553.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 143558[86:Spt:143556.0,143551.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 143562[86:Res:143558.0,61.1] always3(s39) || -> . % 76.16/76.34 143563[86:SSi:143562.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 143564[84:Spt:143563.0,143310.0,143311.0] || until2p7(s38)*+ -> . % 76.16/76.34 143565[84:Spt:143563.0,143310.1] || -> node4(s37)*. % 76.16/76.34 143567[84:MRR:807.0,143565.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 143570[84:Res:53.1,143567.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 143572[85:Spt:143570.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 143574[85:Res:143572.0,61.1] always3(s37) || -> . % 76.16/76.34 143575[85:SSi:143574.0,78232.0,78235.0,137759.0,143309.0,143565.0] || -> . % 76.16/76.34 143576[85:Spt:143575.0,143570.0,143572.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 143577[85:Spt:143575.0,143570.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 143581[85:Res:143577.0,61.1] always3(s38) || -> . % 76.16/76.34 143582[85:SSi:143581.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 143583[83:Spt:143582.0,143308.0,143309.0] || until2p7(s37)*+ -> . % 76.16/76.34 143584[83:Spt:143582.0,143308.1] || -> node4(s36)*. % 76.16/76.34 143586[83:MRR:810.0,143584.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 143589[83:Res:53.1,143586.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 143591[84:Spt:143589.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 143593[84:Res:143591.0,61.1] always3(s36) || -> . % 76.16/76.34 143594[84:SSi:143593.0,78227.0,78231.0,137758.0,143307.0,143584.0] || -> . % 76.16/76.34 143595[84:Spt:143594.0,143589.0,143591.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 143596[84:Spt:143594.0,143589.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 143600[84:Res:143596.0,61.1] always3(s37) || -> . % 76.16/76.34 143601[84:SSi:143600.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 143602[82:Spt:143601.0,143306.0,143307.0] || until2p7(s36)*+ -> . % 76.16/76.34 143603[82:Spt:143601.0,143306.1] || -> node4(s35)*. % 76.16/76.34 143605[82:MRR:813.0,143603.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 143608[82:Res:53.1,143605.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 143613[83:Spt:143608.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 143615[83:Res:143613.0,61.1] always3(s35) || -> . % 76.16/76.34 143616[83:SSi:143615.0,78223.0,78226.0,137757.0,143305.0,143603.0] || -> . % 76.16/76.34 143617[83:Spt:143616.0,143608.0,143613.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 143618[83:Spt:143616.0,143608.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 143622[83:Res:143618.0,61.1] always3(s36) || -> . % 76.16/76.34 143623[83:SSi:143622.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 143624[81:Spt:143623.0,143304.0,143305.0] || until2p7(s35)*+ -> . % 76.16/76.34 143625[81:Spt:143623.0,143304.1] || -> node4(s34)*. % 76.16/76.34 143627[81:MRR:816.0,143625.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 143630[81:Res:53.1,143627.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 143632[82:Spt:143630.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 143634[82:Res:143632.0,61.1] always3(s34) || -> . % 76.16/76.34 143635[82:SSi:143634.0,78218.0,78222.0,137756.0,143303.0,143625.0] || -> . % 76.16/76.34 143636[82:Spt:143635.0,143630.0,143632.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 143637[82:Spt:143635.0,143630.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 143641[82:Res:143637.0,61.1] always3(s35) || -> . % 76.16/76.34 143642[82:SSi:143641.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 143643[80:Spt:143642.0,143302.0,143303.0] || until2p7(s34)*+ -> . % 76.16/76.34 143644[80:Spt:143642.0,143302.1] || -> node4(s33)*. % 76.16/76.34 143646[80:MRR:819.0,143644.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 143649[80:Res:53.1,143646.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 143651[81:Spt:143649.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 143653[81:Res:143651.0,61.1] always3(s33) || -> . % 76.16/76.34 143654[81:SSi:143653.0,78214.0,78217.0,137755.0,143301.0,143644.0] || -> . % 76.16/76.34 143655[81:Spt:143654.0,143649.0,143651.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.34 143656[81:Spt:143654.0,143649.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 143660[81:Res:143656.0,61.1] always3(s34) || -> . % 76.16/76.34 143661[81:SSi:143660.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 143662[79:Spt:143661.0,143300.0,143301.0] || until2p7(s33)*+ -> . % 76.16/76.34 143663[79:Spt:143661.0,143300.1] || -> node4(s32)*. % 76.16/76.34 143665[79:MRR:822.0,143663.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.34 143668[79:Res:53.1,143665.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.34 143670[80:Spt:143668.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 143672[80:Res:143670.0,61.1] always3(s32) || -> . % 76.16/76.34 143673[80:SSi:143672.0,78209.0,78213.0,137754.0,143299.0,143663.0] || -> . % 76.16/76.34 143674[80:Spt:143673.0,143668.0,143670.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.34 143675[80:Spt:143673.0,143668.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 143679[80:Res:143675.0,61.1] always3(s33) || -> . % 76.16/76.34 143680[80:SSi:143679.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 143681[78:Spt:143680.0,143298.0,143299.0] || until2p7(s32)*+ -> . % 76.16/76.34 143682[78:Spt:143680.0,143298.1] || -> node4(s31)*. % 76.16/76.34 143684[78:MRR:825.0,143682.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.34 143687[78:Res:53.1,143684.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.34 143692[79:Spt:143687.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 143694[79:Res:143692.0,61.1] always3(s31) || -> . % 76.16/76.34 143695[79:SSi:143694.0,78205.0,78208.0,137753.0,143297.0,143682.0] || -> . % 76.16/76.34 143696[79:Spt:143695.0,143687.0,143692.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.34 143697[79:Spt:143695.0,143687.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 143701[79:Res:143697.0,61.1] always3(s32) || -> . % 76.16/76.34 143702[79:SSi:143701.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.34 143703[77:Spt:143702.0,143296.0,143297.0] || until2p7(s31)*+ -> . % 76.16/76.34 143704[77:Spt:143702.0,143296.1] || -> node4(s30)*. % 76.16/76.34 143706[77:MRR:828.0,143704.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.34 143709[77:Res:53.1,143706.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.34 143711[78:Spt:143709.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 143713[78:Res:143711.0,61.1] always3(s30) || -> . % 76.16/76.34 143714[78:SSi:143713.0,78200.0,78204.0,137752.0,143295.0,143704.0] || -> . % 76.16/76.34 143715[78:Spt:143714.0,143709.0,143711.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.34 143716[78:Spt:143714.0,143709.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 143720[78:Res:143716.0,61.1] always3(s31) || -> . % 76.16/76.34 143721[78:SSi:143720.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.34 143722[76:Spt:143721.0,143294.0,143295.0] || until2p7(s30)*+ -> . % 76.16/76.34 143723[76:Spt:143721.0,143294.1] || -> node4(s29)*. % 76.16/76.34 143725[76:MRR:831.0,143723.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.34 143728[76:Res:53.1,143725.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.34 143730[76:MRR:143728.0,143284.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 143732[76:Res:143730.0,61.1] always3(s30) || -> . % 76.16/76.34 143733[76:SSi:143732.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.34 143734[74:Spt:143733.0,143200.0,143203.0] || trans(s49,s29)*+ -> . % 76.16/76.34 143735[74:Spt:143733.0,143200.1,143200.2,143200.3,143200.4,143200.5,143200.6,143200.7,143200.8,143200.9,143200.10,143200.11,143200.12,143200.13,143200.14,143200.15,143200.16,143200.17,143200.18,143200.19,143200.20,143200.21,143200.22,143200.23,143200.24,143200.25] || -> trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 143737[74:MRR:143202.1,143734.0] xuntil6(s49) || -> trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 143738[75:Spt:143735.0] || -> trans(s49,s28)*. % 76.16/76.34 143739[75:Res:143738.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s28)*. % 76.16/76.34 143741[75:Res:143738.0,60.0] || -> node2(s49,s28)*. % 76.16/76.34 143742[75:SSi:143739.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s28)*. % 76.16/76.34 143743[75:Res:143741.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 143815[75:SoR:143743.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 143817[75:SoR:143815.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)* xuntil6(s49). % 76.16/76.34 143818[75:SSi:143817.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s28,c_busy)* xuntil6(s49). % 76.16/76.34 143819[76:Spt:143818.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 143821[76:Res:143819.0,61.1] always3(s28) || -> . % 76.16/76.34 143822[76:SSi:143821.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.34 143823[76:Spt:143822.0,143818.1,143819.0] || m_main_v_state(s28,c_busy)*+ -> . % 76.16/76.34 143824[76:Spt:143822.0,143818.0,143818.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 143828[76:MRR:143815.2,143823.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 143829[76:Res:53.1,143824.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 143831[76:MRR:143829.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 143832[76:MRR:143742.0,143831.0] || -> until2p7(s28)*. % 76.16/76.34 143833[76:MRR:224.0,143832.0] || -> until2p7(s29)* node4(s28). % 76.16/76.34 143834[77:Spt:143833.0] || -> until2p7(s29)*. % 76.16/76.34 143835[77:MRR:225.0,143834.0] || -> until2p7(s30)* node4(s29). % 76.16/76.34 143836[78:Spt:143835.0] || -> until2p7(s30)*. % 76.16/76.34 143837[78:MRR:226.0,143836.0] || -> until2p7(s31)* node4(s30). % 76.16/76.34 143838[79:Spt:143837.0] || -> until2p7(s31)*. % 76.16/76.34 143839[79:MRR:227.0,143838.0] || -> until2p7(s32)* node4(s31). % 76.16/76.34 143840[80:Spt:143839.0] || -> until2p7(s32)*. % 76.16/76.34 143841[80:MRR:228.0,143840.0] || -> until2p7(s33)* node4(s32). % 76.16/76.34 143842[81:Spt:143841.0] || -> until2p7(s33)*. % 76.16/76.34 143843[81:MRR:229.0,143842.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 143844[82:Spt:143843.0] || -> until2p7(s34)*. % 76.16/76.34 143845[82:MRR:230.0,143844.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 143846[83:Spt:143845.0] || -> until2p7(s35)*. % 76.16/76.34 143847[83:MRR:231.0,143846.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 143848[84:Spt:143847.0] || -> until2p7(s36)*. % 76.16/76.34 143849[84:MRR:232.0,143848.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 143850[85:Spt:143849.0] || -> until2p7(s37)*. % 76.16/76.34 143851[85:MRR:235.0,143850.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 143852[86:Spt:143851.0] || -> until2p7(s38)*. % 76.16/76.34 143853[86:MRR:236.0,143852.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 143854[87:Spt:143853.0] || -> until2p7(s39)*. % 76.16/76.34 143855[87:MRR:237.0,143854.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 143856[88:Spt:143855.0] || -> until2p7(s40)*. % 76.16/76.34 143857[88:MRR:238.0,143856.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 143858[89:Spt:143857.0] || -> until2p7(s41)*. % 76.16/76.34 143859[89:MRR:239.0,143858.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 143860[90:Spt:143859.0] || -> until2p7(s42)*. % 76.16/76.34 143861[90:MRR:240.0,143860.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 143862[91:Spt:143861.0] || -> until2p7(s43)*. % 76.16/76.34 143863[91:MRR:241.0,143862.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 143864[92:Spt:143863.0] || -> until2p7(s44)*. % 76.16/76.34 143865[92:MRR:539.0,143864.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 143866[93:Spt:143865.0] || -> until2p7(s45)*. % 76.16/76.34 143867[93:MRR:544.0,143866.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 143868[94:Spt:143867.0] || -> until2p7(s46)*. % 76.16/76.34 143869[94:MRR:549.0,143868.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 143870[95:Spt:143869.0] || -> until2p7(s47)*. % 76.16/76.34 143871[95:MRR:554.0,143870.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 143872[96:Spt:143871.0] || -> until2p7(s48)*. % 76.16/76.34 143873[96:MRR:559.0,143872.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 143874[97:Spt:143873.0] || -> until2p7(s49)*. % 76.16/76.34 143875[97:MRR:194.0,143874.0] || -> node4(s49)*. % 76.16/76.34 143876[97:MRR:143828.0,143875.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 143880[97:Res:53.1,143876.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 143882[97:MRR:143880.0,78381.0] || -> . % 76.16/76.34 143883[97:Spt:143882.0,143873.0,143874.0] || until2p7(s49)*+ -> . % 76.16/76.34 143884[97:Spt:143882.0,143873.1] || -> node4(s48)*. % 76.16/76.34 143885[97:MRR:78384.0,143884.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 143888[97:Res:53.1,143885.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 143891[97:Res:143888.0,61.1] always3(s48) || -> . % 76.16/76.34 143892[97:SSi:143891.0,78281.0,78387.0,137770.0,143872.0,143884.0] || -> . % 76.16/76.34 143893[96:Spt:143892.0,143871.0,143872.0] || until2p7(s48)*+ -> . % 76.16/76.34 143894[96:Spt:143892.0,143871.1] || -> node4(s47)*. % 76.16/76.34 143896[96:MRR:777.0,143894.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 143908[96:Res:53.1,143896.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 143910[97:Spt:143908.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 143912[97:Res:143910.0,61.1] always3(s47) || -> . % 76.16/76.34 143913[97:SSi:143912.0,78277.0,78280.0,137769.0,143870.0,143894.0] || -> . % 76.16/76.34 143914[97:Spt:143913.0,143908.0,143910.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 143915[97:Spt:143913.0,143908.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 143919[97:Res:143915.0,61.1] always3(s48) || -> . % 76.16/76.34 143920[97:SSi:143919.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 143921[95:Spt:143920.0,143869.0,143870.0] || until2p7(s47)*+ -> . % 76.16/76.34 143922[95:Spt:143920.0,143869.1] || -> node4(s46)*. % 76.16/76.34 143924[95:MRR:780.0,143922.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 143931[95:Res:53.1,143924.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 143936[96:Spt:143931.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 143938[96:Res:143936.0,61.1] always3(s46) || -> . % 76.16/76.34 143939[96:SSi:143938.0,78272.0,78276.0,137768.0,143868.0,143922.0] || -> . % 76.16/76.34 143940[96:Spt:143939.0,143931.0,143936.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 143941[96:Spt:143939.0,143931.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 143945[96:Res:143941.0,61.1] always3(s47) || -> . % 76.16/76.34 143946[96:SSi:143945.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 143947[94:Spt:143946.0,143867.0,143868.0] || until2p7(s46)*+ -> . % 76.16/76.34 143948[94:Spt:143946.0,143867.1] || -> node4(s45)*. % 76.16/76.34 143950[94:MRR:783.0,143948.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 143953[94:Res:53.1,143950.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 143955[95:Spt:143953.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 143957[95:Res:143955.0,61.1] always3(s45) || -> . % 76.16/76.34 143958[95:SSi:143957.0,78268.0,78271.0,137767.0,143866.0,143948.0] || -> . % 76.16/76.34 143959[95:Spt:143958.0,143953.0,143955.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 143960[95:Spt:143958.0,143953.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 143964[95:Res:143960.0,61.1] always3(s46) || -> . % 76.16/76.34 143965[95:SSi:143964.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 143966[93:Spt:143965.0,143865.0,143866.0] || until2p7(s45)*+ -> . % 76.16/76.34 143967[93:Spt:143965.0,143865.1] || -> node4(s44)*. % 76.16/76.34 143969[93:MRR:786.0,143967.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 143972[93:Res:53.1,143969.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 143974[94:Spt:143972.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 143976[94:Res:143974.0,61.1] always3(s44) || -> . % 76.16/76.34 143977[94:SSi:143976.0,78263.0,78267.0,137766.0,143864.0,143967.0] || -> . % 76.16/76.34 143978[94:Spt:143977.0,143972.0,143974.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 143979[94:Spt:143977.0,143972.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 143983[94:Res:143979.0,61.1] always3(s45) || -> . % 76.16/76.34 143984[94:SSi:143983.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 143985[92:Spt:143984.0,143863.0,143864.0] || until2p7(s44)*+ -> . % 76.16/76.34 143986[92:Spt:143984.0,143863.1] || -> node4(s43)*. % 76.16/76.34 143988[92:MRR:789.0,143986.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 143991[92:Res:53.1,143988.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 143993[93:Spt:143991.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 143995[93:Res:143993.0,61.1] always3(s43) || -> . % 76.16/76.34 143996[93:SSi:143995.0,78259.0,78262.0,137765.0,143862.0,143986.0] || -> . % 76.16/76.34 143997[93:Spt:143996.0,143991.0,143993.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 143998[93:Spt:143996.0,143991.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 144002[93:Res:143998.0,61.1] always3(s44) || -> . % 76.16/76.34 144003[93:SSi:144002.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 144004[91:Spt:144003.0,143861.0,143862.0] || until2p7(s43)*+ -> . % 76.16/76.34 144005[91:Spt:144003.0,143861.1] || -> node4(s42)*. % 76.16/76.34 144007[91:MRR:792.0,144005.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 144010[91:Res:53.1,144007.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 144015[92:Spt:144010.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 144017[92:Res:144015.0,61.1] always3(s42) || -> . % 76.16/76.34 144018[92:SSi:144017.0,78254.0,78258.0,137764.0,143860.0,144005.0] || -> . % 76.16/76.34 144019[92:Spt:144018.0,144010.0,144015.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 144020[92:Spt:144018.0,144010.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 144024[92:Res:144020.0,61.1] always3(s43) || -> . % 76.16/76.34 144025[92:SSi:144024.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 144026[90:Spt:144025.0,143859.0,143860.0] || until2p7(s42)*+ -> . % 76.16/76.34 144027[90:Spt:144025.0,143859.1] || -> node4(s41)*. % 76.16/76.34 144029[90:MRR:795.0,144027.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 144032[90:Res:53.1,144029.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 144034[91:Spt:144032.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 144036[91:Res:144034.0,61.1] always3(s41) || -> . % 76.16/76.34 144037[91:SSi:144036.0,78250.0,78253.0,137763.0,143858.0,144027.0] || -> . % 76.16/76.34 144038[91:Spt:144037.0,144032.0,144034.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 144039[91:Spt:144037.0,144032.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 144043[91:Res:144039.0,61.1] always3(s42) || -> . % 76.16/76.34 144044[91:SSi:144043.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 144045[89:Spt:144044.0,143857.0,143858.0] || until2p7(s41)*+ -> . % 76.16/76.34 144046[89:Spt:144044.0,143857.1] || -> node4(s40)*. % 76.16/76.34 144048[89:MRR:798.0,144046.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 144051[89:Res:53.1,144048.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 144053[90:Spt:144051.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 144055[90:Res:144053.0,61.1] always3(s40) || -> . % 76.16/76.34 144056[90:SSi:144055.0,78245.0,78249.0,137762.0,143856.0,144046.0] || -> . % 76.16/76.34 144057[90:Spt:144056.0,144051.0,144053.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 144058[90:Spt:144056.0,144051.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 144062[90:Res:144058.0,61.1] always3(s41) || -> . % 76.16/76.34 144063[90:SSi:144062.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 144064[88:Spt:144063.0,143855.0,143856.0] || until2p7(s40)*+ -> . % 76.16/76.34 144065[88:Spt:144063.0,143855.1] || -> node4(s39)*. % 76.16/76.34 144067[88:MRR:801.0,144065.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 144070[88:Res:53.1,144067.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 144072[89:Spt:144070.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 144074[89:Res:144072.0,61.1] always3(s39) || -> . % 76.16/76.34 144075[89:SSi:144074.0,78241.0,78244.0,137761.0,143854.0,144065.0] || -> . % 76.16/76.34 144076[89:Spt:144075.0,144070.0,144072.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 144077[89:Spt:144075.0,144070.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 144081[89:Res:144077.0,61.1] always3(s40) || -> . % 76.16/76.34 144082[89:SSi:144081.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 144083[87:Spt:144082.0,143853.0,143854.0] || until2p7(s39)*+ -> . % 76.16/76.34 144084[87:Spt:144082.0,143853.1] || -> node4(s38)*. % 76.16/76.34 144086[87:MRR:804.0,144084.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 144089[87:Res:53.1,144086.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 144094[88:Spt:144089.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 144096[88:Res:144094.0,61.1] always3(s38) || -> . % 76.16/76.34 144097[88:SSi:144096.0,78236.0,78240.0,137760.0,143852.0,144084.0] || -> . % 76.16/76.34 144098[88:Spt:144097.0,144089.0,144094.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 144099[88:Spt:144097.0,144089.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 144103[88:Res:144099.0,61.1] always3(s39) || -> . % 76.16/76.34 144104[88:SSi:144103.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 144105[86:Spt:144104.0,143851.0,143852.0] || until2p7(s38)*+ -> . % 76.16/76.34 144106[86:Spt:144104.0,143851.1] || -> node4(s37)*. % 76.16/76.34 144108[86:MRR:807.0,144106.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 144111[86:Res:53.1,144108.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 144113[87:Spt:144111.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 144115[87:Res:144113.0,61.1] always3(s37) || -> . % 76.16/76.34 144116[87:SSi:144115.0,78232.0,78235.0,137759.0,143850.0,144106.0] || -> . % 76.16/76.34 144117[87:Spt:144116.0,144111.0,144113.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 144118[87:Spt:144116.0,144111.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 144122[87:Res:144118.0,61.1] always3(s38) || -> . % 76.16/76.34 144123[87:SSi:144122.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 144124[85:Spt:144123.0,143849.0,143850.0] || until2p7(s37)*+ -> . % 76.16/76.34 144125[85:Spt:144123.0,143849.1] || -> node4(s36)*. % 76.16/76.34 144127[85:MRR:810.0,144125.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 144130[85:Res:53.1,144127.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 144132[86:Spt:144130.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 144134[86:Res:144132.0,61.1] always3(s36) || -> . % 76.16/76.34 144135[86:SSi:144134.0,78227.0,78231.0,137758.0,143848.0,144125.0] || -> . % 76.16/76.34 144136[86:Spt:144135.0,144130.0,144132.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 144137[86:Spt:144135.0,144130.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 144141[86:Res:144137.0,61.1] always3(s37) || -> . % 76.16/76.34 144142[86:SSi:144141.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 144143[84:Spt:144142.0,143847.0,143848.0] || until2p7(s36)*+ -> . % 76.16/76.34 144144[84:Spt:144142.0,143847.1] || -> node4(s35)*. % 76.16/76.34 144146[84:MRR:813.0,144144.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 144149[84:Res:53.1,144146.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 144151[85:Spt:144149.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 144153[85:Res:144151.0,61.1] always3(s35) || -> . % 76.16/76.34 144154[85:SSi:144153.0,78223.0,78226.0,137757.0,143846.0,144144.0] || -> . % 76.16/76.34 144155[85:Spt:144154.0,144149.0,144151.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 144156[85:Spt:144154.0,144149.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 144160[85:Res:144156.0,61.1] always3(s36) || -> . % 76.16/76.34 144161[85:SSi:144160.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 144162[83:Spt:144161.0,143845.0,143846.0] || until2p7(s35)*+ -> . % 76.16/76.34 144163[83:Spt:144161.0,143845.1] || -> node4(s34)*. % 76.16/76.34 144165[83:MRR:816.0,144163.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 144168[83:Res:53.1,144165.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 144173[84:Spt:144168.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 144175[84:Res:144173.0,61.1] always3(s34) || -> . % 76.16/76.34 144176[84:SSi:144175.0,78218.0,78222.0,137756.0,143844.0,144163.0] || -> . % 76.16/76.34 144177[84:Spt:144176.0,144168.0,144173.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 144178[84:Spt:144176.0,144168.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 144182[84:Res:144178.0,61.1] always3(s35) || -> . % 76.16/76.34 144183[84:SSi:144182.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 144184[82:Spt:144183.0,143843.0,143844.0] || until2p7(s34)*+ -> . % 76.16/76.34 144185[82:Spt:144183.0,143843.1] || -> node4(s33)*. % 76.16/76.34 144187[82:MRR:819.0,144185.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 144190[82:Res:53.1,144187.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 144192[83:Spt:144190.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 144194[83:Res:144192.0,61.1] always3(s33) || -> . % 76.16/76.34 144195[83:SSi:144194.0,78214.0,78217.0,137755.0,143842.0,144185.0] || -> . % 76.16/76.34 144196[83:Spt:144195.0,144190.0,144192.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.34 144197[83:Spt:144195.0,144190.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 144201[83:Res:144197.0,61.1] always3(s34) || -> . % 76.16/76.34 144202[83:SSi:144201.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 144203[81:Spt:144202.0,143841.0,143842.0] || until2p7(s33)*+ -> . % 76.16/76.34 144204[81:Spt:144202.0,143841.1] || -> node4(s32)*. % 76.16/76.34 144206[81:MRR:822.0,144204.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.34 144209[81:Res:53.1,144206.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.34 144211[82:Spt:144209.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 144213[82:Res:144211.0,61.1] always3(s32) || -> . % 76.16/76.34 144214[82:SSi:144213.0,78209.0,78213.0,137754.0,143840.0,144204.0] || -> . % 76.16/76.34 144215[82:Spt:144214.0,144209.0,144211.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.34 144216[82:Spt:144214.0,144209.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 144220[82:Res:144216.0,61.1] always3(s33) || -> . % 76.16/76.34 144221[82:SSi:144220.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 144222[80:Spt:144221.0,143839.0,143840.0] || until2p7(s32)*+ -> . % 76.16/76.34 144223[80:Spt:144221.0,143839.1] || -> node4(s31)*. % 76.16/76.34 144225[80:MRR:825.0,144223.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.34 144228[80:Res:53.1,144225.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.34 144230[81:Spt:144228.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 144232[81:Res:144230.0,61.1] always3(s31) || -> . % 76.16/76.34 144233[81:SSi:144232.0,78205.0,78208.0,137753.0,143838.0,144223.0] || -> . % 76.16/76.34 144234[81:Spt:144233.0,144228.0,144230.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.34 144235[81:Spt:144233.0,144228.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 144239[81:Res:144235.0,61.1] always3(s32) || -> . % 76.16/76.34 144240[81:SSi:144239.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.34 144241[79:Spt:144240.0,143837.0,143838.0] || until2p7(s31)*+ -> . % 76.16/76.34 144242[79:Spt:144240.0,143837.1] || -> node4(s30)*. % 76.16/76.34 144244[79:MRR:828.0,144242.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.34 144247[79:Res:53.1,144244.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.34 144252[80:Spt:144247.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 144254[80:Res:144252.0,61.1] always3(s30) || -> . % 76.16/76.34 144255[80:SSi:144254.0,78200.0,78204.0,137752.0,143836.0,144242.0] || -> . % 76.16/76.34 144256[80:Spt:144255.0,144247.0,144252.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.34 144257[80:Spt:144255.0,144247.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 144261[80:Res:144257.0,61.1] always3(s31) || -> . % 76.16/76.34 144262[80:SSi:144261.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.34 144263[78:Spt:144262.0,143835.0,143836.0] || until2p7(s30)*+ -> . % 76.16/76.34 144264[78:Spt:144262.0,143835.1] || -> node4(s29)*. % 76.16/76.34 144266[78:MRR:831.0,144264.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.34 144269[78:Res:53.1,144266.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.34 144271[79:Spt:144269.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 144273[79:Res:144271.0,61.1] always3(s29) || -> . % 76.16/76.34 144274[79:SSi:144273.0,78196.0,78199.0,137751.0,143834.0,144264.0] || -> . % 76.16/76.34 144275[79:Spt:144274.0,144269.0,144271.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.34 144276[79:Spt:144274.0,144269.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 144280[79:Res:144276.0,61.1] always3(s30) || -> . % 76.16/76.34 144281[79:SSi:144280.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.34 144282[77:Spt:144281.0,143833.0,143834.0] || until2p7(s29)*+ -> . % 76.16/76.34 144283[77:Spt:144281.0,143833.1] || -> node4(s28)*. % 76.16/76.34 144285[77:MRR:834.0,144283.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.34 144288[77:Res:53.1,144285.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.34 144290[77:MRR:144288.0,143823.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 144292[77:Res:144290.0,61.1] always3(s29) || -> . % 76.16/76.34 144293[77:SSi:144292.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.34 144294[75:Spt:144293.0,143735.0,143738.0] || trans(s49,s28)*+ -> . % 76.16/76.34 144295[75:Spt:144293.0,143735.1,143735.2,143735.3,143735.4,143735.5,143735.6,143735.7,143735.8,143735.9,143735.10,143735.11,143735.12,143735.13,143735.14,143735.15,143735.16,143735.17,143735.18,143735.19,143735.20,143735.21,143735.22,143735.23,143735.24] || -> trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 144297[75:MRR:143737.1,144294.0] xuntil6(s49) || -> trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 144298[76:Spt:144295.0] || -> trans(s49,s27)*. % 76.16/76.34 144299[76:Res:144298.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s27)*. % 76.16/76.34 144301[76:Res:144298.0,60.0] || -> node2(s49,s27)*. % 76.16/76.34 144302[76:SSi:144299.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s27)*. % 76.16/76.34 144303[76:Res:144301.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 144379[76:SoR:144303.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 144381[76:SoR:144379.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)* xuntil6(s49). % 76.16/76.34 144382[76:SSi:144381.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s27,c_busy)* xuntil6(s49). % 76.16/76.34 144383[77:Spt:144382.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 144385[77:Res:144383.0,61.1] always3(s27) || -> . % 76.16/76.34 144386[77:SSi:144385.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.34 144387[77:Spt:144386.0,144382.1,144383.0] || m_main_v_state(s27,c_busy)*+ -> . % 76.16/76.34 144388[77:Spt:144386.0,144382.0,144382.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 144392[77:MRR:144379.2,144387.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 144393[77:Res:53.1,144388.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 144395[77:MRR:144393.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 144396[77:MRR:144302.0,144395.0] || -> until2p7(s27)*. % 76.16/76.34 144397[77:MRR:223.0,144396.0] || -> until2p7(s28)* node4(s27). % 76.16/76.34 144398[78:Spt:144397.0] || -> until2p7(s28)*. % 76.16/76.34 144399[78:MRR:224.0,144398.0] || -> until2p7(s29)* node4(s28). % 76.16/76.34 144400[79:Spt:144399.0] || -> until2p7(s29)*. % 76.16/76.34 144401[79:MRR:225.0,144400.0] || -> until2p7(s30)* node4(s29). % 76.16/76.34 144402[80:Spt:144401.0] || -> until2p7(s30)*. % 76.16/76.34 144403[80:MRR:226.0,144402.0] || -> until2p7(s31)* node4(s30). % 76.16/76.34 144404[81:Spt:144403.0] || -> until2p7(s31)*. % 76.16/76.34 144405[81:MRR:227.0,144404.0] || -> until2p7(s32)* node4(s31). % 76.16/76.34 144406[82:Spt:144405.0] || -> until2p7(s32)*. % 76.16/76.34 144407[82:MRR:228.0,144406.0] || -> until2p7(s33)* node4(s32). % 76.16/76.34 144408[83:Spt:144407.0] || -> until2p7(s33)*. % 76.16/76.34 144409[83:MRR:229.0,144408.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 144410[84:Spt:144409.0] || -> until2p7(s34)*. % 76.16/76.34 144411[84:MRR:230.0,144410.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 144412[85:Spt:144411.0] || -> until2p7(s35)*. % 76.16/76.34 144413[85:MRR:231.0,144412.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 144414[86:Spt:144413.0] || -> until2p7(s36)*. % 76.16/76.34 144415[86:MRR:232.0,144414.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 144416[87:Spt:144415.0] || -> until2p7(s37)*. % 76.16/76.34 144417[87:MRR:235.0,144416.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 144418[88:Spt:144417.0] || -> until2p7(s38)*. % 76.16/76.34 144419[88:MRR:236.0,144418.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 144420[89:Spt:144419.0] || -> until2p7(s39)*. % 76.16/76.34 144421[89:MRR:237.0,144420.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 144422[90:Spt:144421.0] || -> until2p7(s40)*. % 76.16/76.34 144423[90:MRR:238.0,144422.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 144424[91:Spt:144423.0] || -> until2p7(s41)*. % 76.16/76.34 144425[91:MRR:239.0,144424.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 144426[92:Spt:144425.0] || -> until2p7(s42)*. % 76.16/76.34 144427[92:MRR:240.0,144426.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 144428[93:Spt:144427.0] || -> until2p7(s43)*. % 76.16/76.34 144429[93:MRR:241.0,144428.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 144430[94:Spt:144429.0] || -> until2p7(s44)*. % 76.16/76.34 144431[94:MRR:539.0,144430.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 144432[95:Spt:144431.0] || -> until2p7(s45)*. % 76.16/76.34 144433[95:MRR:544.0,144432.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 144434[96:Spt:144433.0] || -> until2p7(s46)*. % 76.16/76.34 144435[96:MRR:549.0,144434.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 144436[97:Spt:144435.0] || -> until2p7(s47)*. % 76.16/76.34 144437[97:MRR:554.0,144436.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 144438[98:Spt:144437.0] || -> until2p7(s48)*. % 76.16/76.34 144439[98:MRR:559.0,144438.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 144440[99:Spt:144439.0] || -> until2p7(s49)*. % 76.16/76.34 144441[99:MRR:194.0,144440.0] || -> node4(s49)*. % 76.16/76.34 144442[99:MRR:144392.0,144441.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 144443[99:Res:53.1,144442.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 144445[99:MRR:144443.0,78381.0] || -> . % 76.16/76.34 144446[99:Spt:144445.0,144439.0,144440.0] || until2p7(s49)*+ -> . % 76.16/76.34 144447[99:Spt:144445.0,144439.1] || -> node4(s48)*. % 76.16/76.34 144448[99:MRR:78384.0,144447.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 144451[99:Res:53.1,144448.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 144454[99:Res:144451.0,61.1] always3(s48) || -> . % 76.16/76.34 144455[99:SSi:144454.0,78281.0,78387.0,137770.0,144438.0,144447.0] || -> . % 76.16/76.34 144456[98:Spt:144455.0,144437.0,144438.0] || until2p7(s48)*+ -> . % 76.16/76.34 144457[98:Spt:144455.0,144437.1] || -> node4(s47)*. % 76.16/76.34 144459[98:MRR:777.0,144457.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 144474[98:Res:53.1,144459.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 144479[99:Spt:144474.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 144481[99:Res:144479.0,61.1] always3(s47) || -> . % 76.16/76.34 144482[99:SSi:144481.0,78277.0,78280.0,137769.0,144436.0,144457.0] || -> . % 76.16/76.34 144483[99:Spt:144482.0,144474.0,144479.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 144484[99:Spt:144482.0,144474.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 144488[99:Res:144484.0,61.1] always3(s48) || -> . % 76.16/76.34 144489[99:SSi:144488.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 144490[97:Spt:144489.0,144435.0,144436.0] || until2p7(s47)*+ -> . % 76.16/76.34 144491[97:Spt:144489.0,144435.1] || -> node4(s46)*. % 76.16/76.34 144493[97:MRR:780.0,144491.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 144500[97:Res:53.1,144493.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 144502[98:Spt:144500.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 144504[98:Res:144502.0,61.1] always3(s46) || -> . % 76.16/76.34 144505[98:SSi:144504.0,78272.0,78276.0,137768.0,144434.0,144491.0] || -> . % 76.16/76.34 144506[98:Spt:144505.0,144500.0,144502.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 144507[98:Spt:144505.0,144500.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 144511[98:Res:144507.0,61.1] always3(s47) || -> . % 76.16/76.34 144512[98:SSi:144511.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 144513[96:Spt:144512.0,144433.0,144434.0] || until2p7(s46)*+ -> . % 76.16/76.34 144514[96:Spt:144512.0,144433.1] || -> node4(s45)*. % 76.16/76.34 144516[96:MRR:783.0,144514.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 144519[96:Res:53.1,144516.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 144524[97:Spt:144519.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 144526[97:Res:144524.0,61.1] always3(s45) || -> . % 76.16/76.34 144527[97:SSi:144526.0,78268.0,78271.0,137767.0,144432.0,144514.0] || -> . % 76.16/76.34 144528[97:Spt:144527.0,144519.0,144524.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 144529[97:Spt:144527.0,144519.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 144533[97:Res:144529.0,61.1] always3(s46) || -> . % 76.16/76.34 144534[97:SSi:144533.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 144535[95:Spt:144534.0,144431.0,144432.0] || until2p7(s45)*+ -> . % 76.16/76.34 144536[95:Spt:144534.0,144431.1] || -> node4(s44)*. % 76.16/76.34 144538[95:MRR:786.0,144536.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 144541[95:Res:53.1,144538.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 144543[96:Spt:144541.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 144545[96:Res:144543.0,61.1] always3(s44) || -> . % 76.16/76.34 144546[96:SSi:144545.0,78263.0,78267.0,137766.0,144430.0,144536.0] || -> . % 76.16/76.34 144547[96:Spt:144546.0,144541.0,144543.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 144548[96:Spt:144546.0,144541.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 144552[96:Res:144548.0,61.1] always3(s45) || -> . % 76.16/76.34 144553[96:SSi:144552.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 144554[94:Spt:144553.0,144429.0,144430.0] || until2p7(s44)*+ -> . % 76.16/76.34 144555[94:Spt:144553.0,144429.1] || -> node4(s43)*. % 76.16/76.34 144557[94:MRR:789.0,144555.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 144560[94:Res:53.1,144557.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 144562[95:Spt:144560.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 144564[95:Res:144562.0,61.1] always3(s43) || -> . % 76.16/76.34 144565[95:SSi:144564.0,78259.0,78262.0,137765.0,144428.0,144555.0] || -> . % 76.16/76.34 144566[95:Spt:144565.0,144560.0,144562.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 144567[95:Spt:144565.0,144560.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 144571[95:Res:144567.0,61.1] always3(s44) || -> . % 76.16/76.34 144572[95:SSi:144571.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 144573[93:Spt:144572.0,144427.0,144428.0] || until2p7(s43)*+ -> . % 76.16/76.34 144574[93:Spt:144572.0,144427.1] || -> node4(s42)*. % 76.16/76.34 144576[93:MRR:792.0,144574.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 144579[93:Res:53.1,144576.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 144581[94:Spt:144579.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 144583[94:Res:144581.0,61.1] always3(s42) || -> . % 76.16/76.34 144584[94:SSi:144583.0,78254.0,78258.0,137764.0,144426.0,144574.0] || -> . % 76.16/76.34 144585[94:Spt:144584.0,144579.0,144581.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 144586[94:Spt:144584.0,144579.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 144590[94:Res:144586.0,61.1] always3(s43) || -> . % 76.16/76.34 144591[94:SSi:144590.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 144592[92:Spt:144591.0,144425.0,144426.0] || until2p7(s42)*+ -> . % 76.16/76.34 144593[92:Spt:144591.0,144425.1] || -> node4(s41)*. % 76.16/76.34 144595[92:MRR:795.0,144593.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 144598[92:Res:53.1,144595.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 144603[93:Spt:144598.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 144605[93:Res:144603.0,61.1] always3(s41) || -> . % 76.16/76.34 144606[93:SSi:144605.0,78250.0,78253.0,137763.0,144424.0,144593.0] || -> . % 76.16/76.34 144607[93:Spt:144606.0,144598.0,144603.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 144608[93:Spt:144606.0,144598.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 144612[93:Res:144608.0,61.1] always3(s42) || -> . % 76.16/76.34 144613[93:SSi:144612.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 144614[91:Spt:144613.0,144423.0,144424.0] || until2p7(s41)*+ -> . % 76.16/76.34 144615[91:Spt:144613.0,144423.1] || -> node4(s40)*. % 76.16/76.34 144617[91:MRR:798.0,144615.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 144620[91:Res:53.1,144617.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 144622[92:Spt:144620.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 144624[92:Res:144622.0,61.1] always3(s40) || -> . % 76.16/76.34 144625[92:SSi:144624.0,78245.0,78249.0,137762.0,144422.0,144615.0] || -> . % 76.16/76.34 144626[92:Spt:144625.0,144620.0,144622.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 144627[92:Spt:144625.0,144620.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 144631[92:Res:144627.0,61.1] always3(s41) || -> . % 76.16/76.34 144632[92:SSi:144631.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 144633[90:Spt:144632.0,144421.0,144422.0] || until2p7(s40)*+ -> . % 76.16/76.34 144634[90:Spt:144632.0,144421.1] || -> node4(s39)*. % 76.16/76.34 144636[90:MRR:801.0,144634.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 144639[90:Res:53.1,144636.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 144641[91:Spt:144639.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 144643[91:Res:144641.0,61.1] always3(s39) || -> . % 76.16/76.34 144644[91:SSi:144643.0,78241.0,78244.0,137761.0,144420.0,144634.0] || -> . % 76.16/76.34 144645[91:Spt:144644.0,144639.0,144641.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 144646[91:Spt:144644.0,144639.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 144650[91:Res:144646.0,61.1] always3(s40) || -> . % 76.16/76.34 144651[91:SSi:144650.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 144652[89:Spt:144651.0,144419.0,144420.0] || until2p7(s39)*+ -> . % 76.16/76.34 144653[89:Spt:144651.0,144419.1] || -> node4(s38)*. % 76.16/76.34 144655[89:MRR:804.0,144653.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 144658[89:Res:53.1,144655.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 144660[90:Spt:144658.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 144662[90:Res:144660.0,61.1] always3(s38) || -> . % 76.16/76.34 144663[90:SSi:144662.0,78236.0,78240.0,137760.0,144418.0,144653.0] || -> . % 76.16/76.34 144664[90:Spt:144663.0,144658.0,144660.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 144665[90:Spt:144663.0,144658.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 144669[90:Res:144665.0,61.1] always3(s39) || -> . % 76.16/76.34 144670[90:SSi:144669.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 144671[88:Spt:144670.0,144417.0,144418.0] || until2p7(s38)*+ -> . % 76.16/76.34 144672[88:Spt:144670.0,144417.1] || -> node4(s37)*. % 76.16/76.34 144674[88:MRR:807.0,144672.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 144677[88:Res:53.1,144674.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 144682[89:Spt:144677.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 144684[89:Res:144682.0,61.1] always3(s37) || -> . % 76.16/76.34 144685[89:SSi:144684.0,78232.0,78235.0,137759.0,144416.0,144672.0] || -> . % 76.16/76.34 144686[89:Spt:144685.0,144677.0,144682.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 144687[89:Spt:144685.0,144677.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 144691[89:Res:144687.0,61.1] always3(s38) || -> . % 76.16/76.34 144692[89:SSi:144691.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 144693[87:Spt:144692.0,144415.0,144416.0] || until2p7(s37)*+ -> . % 76.16/76.34 144694[87:Spt:144692.0,144415.1] || -> node4(s36)*. % 76.16/76.34 144696[87:MRR:810.0,144694.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 144699[87:Res:53.1,144696.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 144701[88:Spt:144699.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 144703[88:Res:144701.0,61.1] always3(s36) || -> . % 76.16/76.34 144704[88:SSi:144703.0,78227.0,78231.0,137758.0,144414.0,144694.0] || -> . % 76.16/76.34 144705[88:Spt:144704.0,144699.0,144701.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 144706[88:Spt:144704.0,144699.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 144710[88:Res:144706.0,61.1] always3(s37) || -> . % 76.16/76.34 144711[88:SSi:144710.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 144712[86:Spt:144711.0,144413.0,144414.0] || until2p7(s36)*+ -> . % 76.16/76.34 144713[86:Spt:144711.0,144413.1] || -> node4(s35)*. % 76.16/76.34 144715[86:MRR:813.0,144713.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 144718[86:Res:53.1,144715.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 144720[87:Spt:144718.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 144722[87:Res:144720.0,61.1] always3(s35) || -> . % 76.16/76.34 144723[87:SSi:144722.0,78223.0,78226.0,137757.0,144412.0,144713.0] || -> . % 76.16/76.34 144724[87:Spt:144723.0,144718.0,144720.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 144725[87:Spt:144723.0,144718.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 144729[87:Res:144725.0,61.1] always3(s36) || -> . % 76.16/76.34 144730[87:SSi:144729.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 144731[85:Spt:144730.0,144411.0,144412.0] || until2p7(s35)*+ -> . % 76.16/76.34 144732[85:Spt:144730.0,144411.1] || -> node4(s34)*. % 76.16/76.34 144734[85:MRR:816.0,144732.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 144737[85:Res:53.1,144734.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 144739[86:Spt:144737.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 144741[86:Res:144739.0,61.1] always3(s34) || -> . % 76.16/76.34 144742[86:SSi:144741.0,78218.0,78222.0,137756.0,144410.0,144732.0] || -> . % 76.16/76.34 144743[86:Spt:144742.0,144737.0,144739.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 144744[86:Spt:144742.0,144737.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 144748[86:Res:144744.0,61.1] always3(s35) || -> . % 76.16/76.34 144749[86:SSi:144748.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 144750[84:Spt:144749.0,144409.0,144410.0] || until2p7(s34)*+ -> . % 76.16/76.34 144751[84:Spt:144749.0,144409.1] || -> node4(s33)*. % 76.16/76.34 144753[84:MRR:819.0,144751.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 144756[84:Res:53.1,144753.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 144761[85:Spt:144756.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 144763[85:Res:144761.0,61.1] always3(s33) || -> . % 76.16/76.34 144764[85:SSi:144763.0,78214.0,78217.0,137755.0,144408.0,144751.0] || -> . % 76.16/76.34 144765[85:Spt:144764.0,144756.0,144761.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.34 144766[85:Spt:144764.0,144756.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 144770[85:Res:144766.0,61.1] always3(s34) || -> . % 76.16/76.34 144771[85:SSi:144770.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 144772[83:Spt:144771.0,144407.0,144408.0] || until2p7(s33)*+ -> . % 76.16/76.34 144773[83:Spt:144771.0,144407.1] || -> node4(s32)*. % 76.16/76.34 144775[83:MRR:822.0,144773.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.34 144778[83:Res:53.1,144775.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.34 144780[84:Spt:144778.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 144782[84:Res:144780.0,61.1] always3(s32) || -> . % 76.16/76.34 144783[84:SSi:144782.0,78209.0,78213.0,137754.0,144406.0,144773.0] || -> . % 76.16/76.34 144784[84:Spt:144783.0,144778.0,144780.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.34 144785[84:Spt:144783.0,144778.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 144789[84:Res:144785.0,61.1] always3(s33) || -> . % 76.16/76.34 144790[84:SSi:144789.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 144791[82:Spt:144790.0,144405.0,144406.0] || until2p7(s32)*+ -> . % 76.16/76.34 144792[82:Spt:144790.0,144405.1] || -> node4(s31)*. % 76.16/76.34 144794[82:MRR:825.0,144792.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.34 144797[82:Res:53.1,144794.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.34 144799[83:Spt:144797.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 144801[83:Res:144799.0,61.1] always3(s31) || -> . % 76.16/76.34 144802[83:SSi:144801.0,78205.0,78208.0,137753.0,144404.0,144792.0] || -> . % 76.16/76.34 144803[83:Spt:144802.0,144797.0,144799.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.34 144804[83:Spt:144802.0,144797.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 144808[83:Res:144804.0,61.1] always3(s32) || -> . % 76.16/76.34 144809[83:SSi:144808.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.34 144810[81:Spt:144809.0,144403.0,144404.0] || until2p7(s31)*+ -> . % 76.16/76.34 144811[81:Spt:144809.0,144403.1] || -> node4(s30)*. % 76.16/76.34 144813[81:MRR:828.0,144811.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.34 144816[81:Res:53.1,144813.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.34 144818[82:Spt:144816.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 144820[82:Res:144818.0,61.1] always3(s30) || -> . % 76.16/76.34 144821[82:SSi:144820.0,78200.0,78204.0,137752.0,144402.0,144811.0] || -> . % 76.16/76.34 144822[82:Spt:144821.0,144816.0,144818.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.34 144823[82:Spt:144821.0,144816.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 144827[82:Res:144823.0,61.1] always3(s31) || -> . % 76.16/76.34 144828[82:SSi:144827.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.34 144829[80:Spt:144828.0,144401.0,144402.0] || until2p7(s30)*+ -> . % 76.16/76.34 144830[80:Spt:144828.0,144401.1] || -> node4(s29)*. % 76.16/76.34 144832[80:MRR:831.0,144830.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.34 144835[80:Res:53.1,144832.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.34 144840[81:Spt:144835.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 144842[81:Res:144840.0,61.1] always3(s29) || -> . % 76.16/76.34 144843[81:SSi:144842.0,78196.0,78199.0,137751.0,144400.0,144830.0] || -> . % 76.16/76.34 144844[81:Spt:144843.0,144835.0,144840.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.34 144845[81:Spt:144843.0,144835.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 144849[81:Res:144845.0,61.1] always3(s30) || -> . % 76.16/76.34 144850[81:SSi:144849.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.34 144851[79:Spt:144850.0,144399.0,144400.0] || until2p7(s29)*+ -> . % 76.16/76.34 144852[79:Spt:144850.0,144399.1] || -> node4(s28)*. % 76.16/76.34 144854[79:MRR:834.0,144852.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.34 144857[79:Res:53.1,144854.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.34 144859[80:Spt:144857.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 144861[80:Res:144859.0,61.1] always3(s28) || -> . % 76.16/76.34 144862[80:SSi:144861.0,78191.0,78195.0,137750.0,144398.0,144852.0] || -> . % 76.16/76.34 144863[80:Spt:144862.0,144857.0,144859.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.34 144864[80:Spt:144862.0,144857.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 144868[80:Res:144864.0,61.1] always3(s29) || -> . % 76.16/76.34 144869[80:SSi:144868.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.34 144870[78:Spt:144869.0,144397.0,144398.0] || until2p7(s28)*+ -> . % 76.16/76.34 144871[78:Spt:144869.0,144397.1] || -> node4(s27)*. % 76.16/76.34 144873[78:MRR:837.0,144871.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.34 144876[78:Res:53.1,144873.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.34 144878[78:MRR:144876.0,144387.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 144880[78:Res:144878.0,61.1] always3(s28) || -> . % 76.16/76.34 144881[78:SSi:144880.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.34 144882[76:Spt:144881.0,144295.0,144298.0] || trans(s49,s27)*+ -> . % 76.16/76.34 144883[76:Spt:144881.0,144295.1,144295.2,144295.3,144295.4,144295.5,144295.6,144295.7,144295.8,144295.9,144295.10,144295.11,144295.12,144295.13,144295.14,144295.15,144295.16,144295.17,144295.18,144295.19,144295.20,144295.21,144295.22,144295.23] || -> trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 144885[76:MRR:144297.1,144882.0] xuntil6(s49) || -> trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 144886[77:Spt:144883.0] || -> trans(s49,s26)*. % 76.16/76.34 144887[77:Res:144886.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s26)*. % 76.16/76.34 144889[77:Res:144886.0,60.0] || -> node2(s49,s26)*. % 76.16/76.34 144890[77:SSi:144887.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s26)*. % 76.16/76.34 144891[77:Res:144889.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 144968[77:SoR:144891.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 144970[77:SoR:144968.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)* xuntil6(s49). % 76.16/76.34 144971[77:SSi:144970.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s26,c_busy)* xuntil6(s49). % 76.16/76.34 144972[78:Spt:144971.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 144974[78:Res:144972.0,61.1] always3(s26) || -> . % 76.16/76.34 144975[78:SSi:144974.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.34 144976[78:Spt:144975.0,144971.1,144972.0] || m_main_v_state(s26,c_busy)*+ -> . % 76.16/76.34 144977[78:Spt:144975.0,144971.0,144971.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 144981[78:MRR:144968.2,144976.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 144982[78:Res:53.1,144977.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 144984[78:MRR:144982.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 144985[78:MRR:144890.0,144984.0] || -> until2p7(s26)*. % 76.16/76.34 144986[78:MRR:222.0,144985.0] || -> until2p7(s27)* node4(s26). % 76.16/76.34 144987[79:Spt:144986.0] || -> until2p7(s27)*. % 76.16/76.34 144988[79:MRR:223.0,144987.0] || -> until2p7(s28)* node4(s27). % 76.16/76.34 144989[80:Spt:144988.0] || -> until2p7(s28)*. % 76.16/76.34 144990[80:MRR:224.0,144989.0] || -> until2p7(s29)* node4(s28). % 76.16/76.34 144991[81:Spt:144990.0] || -> until2p7(s29)*. % 76.16/76.34 144992[81:MRR:225.0,144991.0] || -> until2p7(s30)* node4(s29). % 76.16/76.34 144993[82:Spt:144992.0] || -> until2p7(s30)*. % 76.16/76.34 144994[82:MRR:226.0,144993.0] || -> until2p7(s31)* node4(s30). % 76.16/76.34 144995[83:Spt:144994.0] || -> until2p7(s31)*. % 76.16/76.34 144996[83:MRR:227.0,144995.0] || -> until2p7(s32)* node4(s31). % 76.16/76.34 144997[84:Spt:144996.0] || -> until2p7(s32)*. % 76.16/76.34 144998[84:MRR:228.0,144997.0] || -> until2p7(s33)* node4(s32). % 76.16/76.34 144999[85:Spt:144998.0] || -> until2p7(s33)*. % 76.16/76.34 145000[85:MRR:229.0,144999.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 145001[86:Spt:145000.0] || -> until2p7(s34)*. % 76.16/76.34 145002[86:MRR:230.0,145001.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 145003[87:Spt:145002.0] || -> until2p7(s35)*. % 76.16/76.34 145004[87:MRR:231.0,145003.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 145005[88:Spt:145004.0] || -> until2p7(s36)*. % 76.16/76.34 145006[88:MRR:232.0,145005.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 145007[89:Spt:145006.0] || -> until2p7(s37)*. % 76.16/76.34 145008[89:MRR:235.0,145007.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 145009[90:Spt:145008.0] || -> until2p7(s38)*. % 76.16/76.34 145010[90:MRR:236.0,145009.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 145011[91:Spt:145010.0] || -> until2p7(s39)*. % 76.16/76.34 145012[91:MRR:237.0,145011.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 145013[92:Spt:145012.0] || -> until2p7(s40)*. % 76.16/76.34 145014[92:MRR:238.0,145013.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 145015[93:Spt:145014.0] || -> until2p7(s41)*. % 76.16/76.34 145016[93:MRR:239.0,145015.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 145017[94:Spt:145016.0] || -> until2p7(s42)*. % 76.16/76.34 145018[94:MRR:240.0,145017.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 145019[95:Spt:145018.0] || -> until2p7(s43)*. % 76.16/76.34 145020[95:MRR:241.0,145019.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 145021[96:Spt:145020.0] || -> until2p7(s44)*. % 76.16/76.34 145022[96:MRR:539.0,145021.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 145023[97:Spt:145022.0] || -> until2p7(s45)*. % 76.16/76.34 145024[97:MRR:544.0,145023.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 145025[98:Spt:145024.0] || -> until2p7(s46)*. % 76.16/76.34 145026[98:MRR:549.0,145025.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 145027[99:Spt:145026.0] || -> until2p7(s47)*. % 76.16/76.34 145028[99:MRR:554.0,145027.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 145029[100:Spt:145028.0] || -> until2p7(s48)*. % 76.16/76.34 145030[100:MRR:559.0,145029.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 145031[101:Spt:145030.0] || -> until2p7(s49)*. % 76.16/76.34 145032[101:MRR:194.0,145031.0] || -> node4(s49)*. % 76.16/76.34 145033[101:MRR:144981.0,145032.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 145037[101:Res:53.1,145033.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 145039[101:MRR:145037.0,78381.0] || -> . % 76.16/76.34 145040[101:Spt:145039.0,145030.0,145031.0] || until2p7(s49)*+ -> . % 76.16/76.34 145041[101:Spt:145039.0,145030.1] || -> node4(s48)*. % 76.16/76.34 145042[101:MRR:78384.0,145041.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 145045[101:Res:53.1,145042.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 145048[101:Res:145045.0,61.1] always3(s48) || -> . % 76.16/76.34 145049[101:SSi:145048.0,78281.0,78387.0,137770.0,145029.0,145041.0] || -> . % 76.16/76.34 145050[100:Spt:145049.0,145028.0,145029.0] || until2p7(s48)*+ -> . % 76.16/76.34 145051[100:Spt:145049.0,145028.1] || -> node4(s47)*. % 76.16/76.34 145053[100:MRR:777.0,145051.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 145065[100:Res:53.1,145053.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 145067[101:Spt:145065.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 145069[101:Res:145067.0,61.1] always3(s47) || -> . % 76.16/76.34 145070[101:SSi:145069.0,78277.0,78280.0,137769.0,145027.0,145051.0] || -> . % 76.16/76.34 145071[101:Spt:145070.0,145065.0,145067.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 145072[101:Spt:145070.0,145065.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 145076[101:Res:145072.0,61.1] always3(s48) || -> . % 76.16/76.34 145077[101:SSi:145076.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 145078[99:Spt:145077.0,145026.0,145027.0] || until2p7(s47)*+ -> . % 76.16/76.34 145079[99:Spt:145077.0,145026.1] || -> node4(s46)*. % 76.16/76.34 145081[99:MRR:780.0,145079.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 145088[99:Res:53.1,145081.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 145093[100:Spt:145088.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 145095[100:Res:145093.0,61.1] always3(s46) || -> . % 76.16/76.34 145096[100:SSi:145095.0,78272.0,78276.0,137768.0,145025.0,145079.0] || -> . % 76.16/76.34 145097[100:Spt:145096.0,145088.0,145093.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 145098[100:Spt:145096.0,145088.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 145102[100:Res:145098.0,61.1] always3(s47) || -> . % 76.16/76.34 145103[100:SSi:145102.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 145104[98:Spt:145103.0,145024.0,145025.0] || until2p7(s46)*+ -> . % 76.16/76.34 145105[98:Spt:145103.0,145024.1] || -> node4(s45)*. % 76.16/76.34 145107[98:MRR:783.0,145105.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 145110[98:Res:53.1,145107.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 145112[99:Spt:145110.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 145114[99:Res:145112.0,61.1] always3(s45) || -> . % 76.16/76.34 145115[99:SSi:145114.0,78268.0,78271.0,137767.0,145023.0,145105.0] || -> . % 76.16/76.34 145116[99:Spt:145115.0,145110.0,145112.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 145117[99:Spt:145115.0,145110.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 145121[99:Res:145117.0,61.1] always3(s46) || -> . % 76.16/76.34 145122[99:SSi:145121.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 145123[97:Spt:145122.0,145022.0,145023.0] || until2p7(s45)*+ -> . % 76.16/76.34 145124[97:Spt:145122.0,145022.1] || -> node4(s44)*. % 76.16/76.34 145126[97:MRR:786.0,145124.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 145129[97:Res:53.1,145126.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 145131[98:Spt:145129.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 145133[98:Res:145131.0,61.1] always3(s44) || -> . % 76.16/76.34 145134[98:SSi:145133.0,78263.0,78267.0,137766.0,145021.0,145124.0] || -> . % 76.16/76.34 145135[98:Spt:145134.0,145129.0,145131.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 145136[98:Spt:145134.0,145129.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 145140[98:Res:145136.0,61.1] always3(s45) || -> . % 76.16/76.34 145141[98:SSi:145140.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 145142[96:Spt:145141.0,145020.0,145021.0] || until2p7(s44)*+ -> . % 76.16/76.34 145143[96:Spt:145141.0,145020.1] || -> node4(s43)*. % 76.16/76.34 145145[96:MRR:789.0,145143.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 145148[96:Res:53.1,145145.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 145150[97:Spt:145148.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 145152[97:Res:145150.0,61.1] always3(s43) || -> . % 76.16/76.34 145153[97:SSi:145152.0,78259.0,78262.0,137765.0,145019.0,145143.0] || -> . % 76.16/76.34 145154[97:Spt:145153.0,145148.0,145150.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 145155[97:Spt:145153.0,145148.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 145159[97:Res:145155.0,61.1] always3(s44) || -> . % 76.16/76.34 145160[97:SSi:145159.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 145161[95:Spt:145160.0,145018.0,145019.0] || until2p7(s43)*+ -> . % 76.16/76.34 145162[95:Spt:145160.0,145018.1] || -> node4(s42)*. % 76.16/76.34 145164[95:MRR:792.0,145162.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 145167[95:Res:53.1,145164.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 145172[96:Spt:145167.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 145174[96:Res:145172.0,61.1] always3(s42) || -> . % 76.16/76.34 145175[96:SSi:145174.0,78254.0,78258.0,137764.0,145017.0,145162.0] || -> . % 76.16/76.34 145176[96:Spt:145175.0,145167.0,145172.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 145177[96:Spt:145175.0,145167.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 145181[96:Res:145177.0,61.1] always3(s43) || -> . % 76.16/76.34 145182[96:SSi:145181.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 145183[94:Spt:145182.0,145016.0,145017.0] || until2p7(s42)*+ -> . % 76.16/76.34 145184[94:Spt:145182.0,145016.1] || -> node4(s41)*. % 76.16/76.34 145186[94:MRR:795.0,145184.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 145189[94:Res:53.1,145186.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 145191[95:Spt:145189.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 145193[95:Res:145191.0,61.1] always3(s41) || -> . % 76.16/76.34 145194[95:SSi:145193.0,78250.0,78253.0,137763.0,145015.0,145184.0] || -> . % 76.16/76.34 145195[95:Spt:145194.0,145189.0,145191.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 145196[95:Spt:145194.0,145189.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 145200[95:Res:145196.0,61.1] always3(s42) || -> . % 76.16/76.34 145201[95:SSi:145200.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 145202[93:Spt:145201.0,145014.0,145015.0] || until2p7(s41)*+ -> . % 76.16/76.34 145203[93:Spt:145201.0,145014.1] || -> node4(s40)*. % 76.16/76.34 145205[93:MRR:798.0,145203.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 145208[93:Res:53.1,145205.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 145210[94:Spt:145208.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 145212[94:Res:145210.0,61.1] always3(s40) || -> . % 76.16/76.34 145213[94:SSi:145212.0,78245.0,78249.0,137762.0,145013.0,145203.0] || -> . % 76.16/76.34 145214[94:Spt:145213.0,145208.0,145210.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 145215[94:Spt:145213.0,145208.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 145219[94:Res:145215.0,61.1] always3(s41) || -> . % 76.16/76.34 145220[94:SSi:145219.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 145221[92:Spt:145220.0,145012.0,145013.0] || until2p7(s40)*+ -> . % 76.16/76.34 145222[92:Spt:145220.0,145012.1] || -> node4(s39)*. % 76.16/76.34 145224[92:MRR:801.0,145222.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 145227[92:Res:53.1,145224.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 145229[93:Spt:145227.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 145231[93:Res:145229.0,61.1] always3(s39) || -> . % 76.16/76.34 145232[93:SSi:145231.0,78241.0,78244.0,137761.0,145011.0,145222.0] || -> . % 76.16/76.34 145233[93:Spt:145232.0,145227.0,145229.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 145234[93:Spt:145232.0,145227.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 145238[93:Res:145234.0,61.1] always3(s40) || -> . % 76.16/76.34 145239[93:SSi:145238.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 145240[91:Spt:145239.0,145010.0,145011.0] || until2p7(s39)*+ -> . % 76.16/76.34 145241[91:Spt:145239.0,145010.1] || -> node4(s38)*. % 76.16/76.34 145243[91:MRR:804.0,145241.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 145246[91:Res:53.1,145243.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 145251[92:Spt:145246.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 145253[92:Res:145251.0,61.1] always3(s38) || -> . % 76.16/76.34 145254[92:SSi:145253.0,78236.0,78240.0,137760.0,145009.0,145241.0] || -> . % 76.16/76.34 145255[92:Spt:145254.0,145246.0,145251.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 145256[92:Spt:145254.0,145246.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 145260[92:Res:145256.0,61.1] always3(s39) || -> . % 76.16/76.34 145261[92:SSi:145260.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 145262[90:Spt:145261.0,145008.0,145009.0] || until2p7(s38)*+ -> . % 76.16/76.34 145263[90:Spt:145261.0,145008.1] || -> node4(s37)*. % 76.16/76.34 145265[90:MRR:807.0,145263.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 145268[90:Res:53.1,145265.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 145270[91:Spt:145268.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 145272[91:Res:145270.0,61.1] always3(s37) || -> . % 76.16/76.34 145273[91:SSi:145272.0,78232.0,78235.0,137759.0,145007.0,145263.0] || -> . % 76.16/76.34 145274[91:Spt:145273.0,145268.0,145270.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 145275[91:Spt:145273.0,145268.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 145279[91:Res:145275.0,61.1] always3(s38) || -> . % 76.16/76.34 145280[91:SSi:145279.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 145281[89:Spt:145280.0,145006.0,145007.0] || until2p7(s37)*+ -> . % 76.16/76.34 145282[89:Spt:145280.0,145006.1] || -> node4(s36)*. % 76.16/76.34 145284[89:MRR:810.0,145282.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 145287[89:Res:53.1,145284.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 145289[90:Spt:145287.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 145291[90:Res:145289.0,61.1] always3(s36) || -> . % 76.16/76.34 145292[90:SSi:145291.0,78227.0,78231.0,137758.0,145005.0,145282.0] || -> . % 76.16/76.34 145293[90:Spt:145292.0,145287.0,145289.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 145294[90:Spt:145292.0,145287.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 145298[90:Res:145294.0,61.1] always3(s37) || -> . % 76.16/76.34 145299[90:SSi:145298.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 145300[88:Spt:145299.0,145004.0,145005.0] || until2p7(s36)*+ -> . % 76.16/76.34 145301[88:Spt:145299.0,145004.1] || -> node4(s35)*. % 76.16/76.34 145303[88:MRR:813.0,145301.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 145306[88:Res:53.1,145303.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 145308[89:Spt:145306.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 145310[89:Res:145308.0,61.1] always3(s35) || -> . % 76.16/76.34 145311[89:SSi:145310.0,78223.0,78226.0,137757.0,145003.0,145301.0] || -> . % 76.16/76.34 145312[89:Spt:145311.0,145306.0,145308.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 145313[89:Spt:145311.0,145306.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 145317[89:Res:145313.0,61.1] always3(s36) || -> . % 76.16/76.34 145318[89:SSi:145317.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 145319[87:Spt:145318.0,145002.0,145003.0] || until2p7(s35)*+ -> . % 76.16/76.34 145320[87:Spt:145318.0,145002.1] || -> node4(s34)*. % 76.16/76.34 145322[87:MRR:816.0,145320.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 145325[87:Res:53.1,145322.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 145330[88:Spt:145325.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 145332[88:Res:145330.0,61.1] always3(s34) || -> . % 76.16/76.34 145333[88:SSi:145332.0,78218.0,78222.0,137756.0,145001.0,145320.0] || -> . % 76.16/76.34 145334[88:Spt:145333.0,145325.0,145330.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 145335[88:Spt:145333.0,145325.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 145339[88:Res:145335.0,61.1] always3(s35) || -> . % 76.16/76.34 145340[88:SSi:145339.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 145341[86:Spt:145340.0,145000.0,145001.0] || until2p7(s34)*+ -> . % 76.16/76.34 145342[86:Spt:145340.0,145000.1] || -> node4(s33)*. % 76.16/76.34 145344[86:MRR:819.0,145342.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 145347[86:Res:53.1,145344.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 145349[87:Spt:145347.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 145351[87:Res:145349.0,61.1] always3(s33) || -> . % 76.16/76.34 145352[87:SSi:145351.0,78214.0,78217.0,137755.0,144999.0,145342.0] || -> . % 76.16/76.34 145353[87:Spt:145352.0,145347.0,145349.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.34 145354[87:Spt:145352.0,145347.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 145358[87:Res:145354.0,61.1] always3(s34) || -> . % 76.16/76.34 145359[87:SSi:145358.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 145360[85:Spt:145359.0,144998.0,144999.0] || until2p7(s33)*+ -> . % 76.16/76.34 145361[85:Spt:145359.0,144998.1] || -> node4(s32)*. % 76.16/76.34 145363[85:MRR:822.0,145361.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.34 145366[85:Res:53.1,145363.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.34 145368[86:Spt:145366.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 145370[86:Res:145368.0,61.1] always3(s32) || -> . % 76.16/76.34 145371[86:SSi:145370.0,78209.0,78213.0,137754.0,144997.0,145361.0] || -> . % 76.16/76.34 145372[86:Spt:145371.0,145366.0,145368.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.34 145373[86:Spt:145371.0,145366.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 145377[86:Res:145373.0,61.1] always3(s33) || -> . % 76.16/76.34 145378[86:SSi:145377.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 145379[84:Spt:145378.0,144996.0,144997.0] || until2p7(s32)*+ -> . % 76.16/76.34 145380[84:Spt:145378.0,144996.1] || -> node4(s31)*. % 76.16/76.34 145382[84:MRR:825.0,145380.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.34 145385[84:Res:53.1,145382.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.34 145387[85:Spt:145385.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 145389[85:Res:145387.0,61.1] always3(s31) || -> . % 76.16/76.34 145390[85:SSi:145389.0,78205.0,78208.0,137753.0,144995.0,145380.0] || -> . % 76.16/76.34 145391[85:Spt:145390.0,145385.0,145387.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.34 145392[85:Spt:145390.0,145385.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 145396[85:Res:145392.0,61.1] always3(s32) || -> . % 76.16/76.34 145397[85:SSi:145396.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.34 145398[83:Spt:145397.0,144994.0,144995.0] || until2p7(s31)*+ -> . % 76.16/76.34 145399[83:Spt:145397.0,144994.1] || -> node4(s30)*. % 76.16/76.34 145401[83:MRR:828.0,145399.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.34 145404[83:Res:53.1,145401.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.34 145409[84:Spt:145404.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 145411[84:Res:145409.0,61.1] always3(s30) || -> . % 76.16/76.34 145412[84:SSi:145411.0,78200.0,78204.0,137752.0,144993.0,145399.0] || -> . % 76.16/76.34 145413[84:Spt:145412.0,145404.0,145409.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.34 145414[84:Spt:145412.0,145404.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 145418[84:Res:145414.0,61.1] always3(s31) || -> . % 76.16/76.34 145419[84:SSi:145418.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.34 145420[82:Spt:145419.0,144992.0,144993.0] || until2p7(s30)*+ -> . % 76.16/76.34 145421[82:Spt:145419.0,144992.1] || -> node4(s29)*. % 76.16/76.34 145423[82:MRR:831.0,145421.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.34 145426[82:Res:53.1,145423.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.34 145428[83:Spt:145426.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 145430[83:Res:145428.0,61.1] always3(s29) || -> . % 76.16/76.34 145431[83:SSi:145430.0,78196.0,78199.0,137751.0,144991.0,145421.0] || -> . % 76.16/76.34 145432[83:Spt:145431.0,145426.0,145428.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.34 145433[83:Spt:145431.0,145426.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 145437[83:Res:145433.0,61.1] always3(s30) || -> . % 76.16/76.34 145438[83:SSi:145437.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.34 145439[81:Spt:145438.0,144990.0,144991.0] || until2p7(s29)*+ -> . % 76.16/76.34 145440[81:Spt:145438.0,144990.1] || -> node4(s28)*. % 76.16/76.34 145442[81:MRR:834.0,145440.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.34 145445[81:Res:53.1,145442.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.34 145447[82:Spt:145445.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 145449[82:Res:145447.0,61.1] always3(s28) || -> . % 76.16/76.34 145450[82:SSi:145449.0,78191.0,78195.0,137750.0,144989.0,145440.0] || -> . % 76.16/76.34 145451[82:Spt:145450.0,145445.0,145447.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.34 145452[82:Spt:145450.0,145445.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 145456[82:Res:145452.0,61.1] always3(s29) || -> . % 76.16/76.34 145457[82:SSi:145456.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.34 145458[80:Spt:145457.0,144988.0,144989.0] || until2p7(s28)*+ -> . % 76.16/76.34 145459[80:Spt:145457.0,144988.1] || -> node4(s27)*. % 76.16/76.34 145461[80:MRR:837.0,145459.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.34 145464[80:Res:53.1,145461.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.34 145466[81:Spt:145464.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 145468[81:Res:145466.0,61.1] always3(s27) || -> . % 76.16/76.34 145469[81:SSi:145468.0,78187.0,78190.0,137749.0,144987.0,145459.0] || -> . % 76.16/76.34 145470[81:Spt:145469.0,145464.0,145466.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.34 145471[81:Spt:145469.0,145464.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 145475[81:Res:145471.0,61.1] always3(s28) || -> . % 76.16/76.34 145476[81:SSi:145475.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.34 145477[79:Spt:145476.0,144986.0,144987.0] || until2p7(s27)*+ -> . % 76.16/76.34 145478[79:Spt:145476.0,144986.1] || -> node4(s26)*. % 76.16/76.34 145480[79:MRR:840.0,145478.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.34 145483[79:Res:53.1,145480.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.34 145485[79:MRR:145483.0,144976.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 145490[79:Res:145485.0,61.1] always3(s27) || -> . % 76.16/76.34 145491[79:SSi:145490.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.34 145492[77:Spt:145491.0,144883.0,144886.0] || trans(s49,s26)*+ -> . % 76.16/76.34 145493[77:Spt:145491.0,144883.1,144883.2,144883.3,144883.4,144883.5,144883.6,144883.7,144883.8,144883.9,144883.10,144883.11,144883.12,144883.13,144883.14,144883.15,144883.16,144883.17,144883.18,144883.19,144883.20,144883.21,144883.22] || -> trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 145495[77:MRR:144885.1,145492.0] xuntil6(s49) || -> trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 145496[78:Spt:145493.0] || -> trans(s49,s25)*. % 76.16/76.34 145497[78:Res:145496.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s25)*. % 76.16/76.34 145499[78:Res:145496.0,60.0] || -> node2(s49,s25)*. % 76.16/76.34 145500[78:SSi:145497.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s25)*. % 76.16/76.34 145501[78:Res:145499.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)*. % 76.16/76.34 145582[78:SoR:145501.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)*. % 76.16/76.34 145584[78:SoR:145582.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)* xuntil6(s49). % 76.16/76.34 145585[78:SSi:145584.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s25,c_busy)* xuntil6(s49). % 76.16/76.34 145586[79:Spt:145585.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.34 145588[79:Res:145586.0,61.1] always3(s25) || -> . % 76.16/76.34 145589[79:SSi:145588.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.34 145590[79:Spt:145589.0,145585.1,145586.0] || m_main_v_state(s25,c_busy)*+ -> . % 76.16/76.34 145591[79:Spt:145589.0,145585.0,145585.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 145595[79:MRR:145582.2,145590.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 145596[79:Res:53.1,145591.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 145598[79:MRR:145596.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 145599[79:MRR:145500.0,145598.0] || -> until2p7(s25)*. % 76.16/76.34 145600[79:MRR:221.0,145599.0] || -> until2p7(s26)* node4(s25). % 76.16/76.34 145601[80:Spt:145600.0] || -> until2p7(s26)*. % 76.16/76.34 145602[80:MRR:222.0,145601.0] || -> until2p7(s27)* node4(s26). % 76.16/76.34 145603[81:Spt:145602.0] || -> until2p7(s27)*. % 76.16/76.34 145604[81:MRR:223.0,145603.0] || -> until2p7(s28)* node4(s27). % 76.16/76.34 145605[82:Spt:145604.0] || -> until2p7(s28)*. % 76.16/76.34 145606[82:MRR:224.0,145605.0] || -> until2p7(s29)* node4(s28). % 76.16/76.34 145607[83:Spt:145606.0] || -> until2p7(s29)*. % 76.16/76.34 145608[83:MRR:225.0,145607.0] || -> until2p7(s30)* node4(s29). % 76.16/76.34 145609[84:Spt:145608.0] || -> until2p7(s30)*. % 76.16/76.34 145610[84:MRR:226.0,145609.0] || -> until2p7(s31)* node4(s30). % 76.16/76.34 145611[85:Spt:145610.0] || -> until2p7(s31)*. % 76.16/76.34 145612[85:MRR:227.0,145611.0] || -> until2p7(s32)* node4(s31). % 76.16/76.34 145613[86:Spt:145612.0] || -> until2p7(s32)*. % 76.16/76.34 145614[86:MRR:228.0,145613.0] || -> until2p7(s33)* node4(s32). % 76.16/76.34 145615[87:Spt:145614.0] || -> until2p7(s33)*. % 76.16/76.34 145616[87:MRR:229.0,145615.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 145617[88:Spt:145616.0] || -> until2p7(s34)*. % 76.16/76.34 145618[88:MRR:230.0,145617.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 145619[89:Spt:145618.0] || -> until2p7(s35)*. % 76.16/76.34 145620[89:MRR:231.0,145619.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 145621[90:Spt:145620.0] || -> until2p7(s36)*. % 76.16/76.34 145622[90:MRR:232.0,145621.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 145623[91:Spt:145622.0] || -> until2p7(s37)*. % 76.16/76.34 145624[91:MRR:235.0,145623.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 145625[92:Spt:145624.0] || -> until2p7(s38)*. % 76.16/76.34 145626[92:MRR:236.0,145625.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 145627[93:Spt:145626.0] || -> until2p7(s39)*. % 76.16/76.34 145628[93:MRR:237.0,145627.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 145629[94:Spt:145628.0] || -> until2p7(s40)*. % 76.16/76.34 145630[94:MRR:238.0,145629.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 145631[95:Spt:145630.0] || -> until2p7(s41)*. % 76.16/76.34 145632[95:MRR:239.0,145631.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 145633[96:Spt:145632.0] || -> until2p7(s42)*. % 76.16/76.34 145634[96:MRR:240.0,145633.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 145635[97:Spt:145634.0] || -> until2p7(s43)*. % 76.16/76.34 145636[97:MRR:241.0,145635.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 145637[98:Spt:145636.0] || -> until2p7(s44)*. % 76.16/76.34 145638[98:MRR:539.0,145637.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 145639[99:Spt:145638.0] || -> until2p7(s45)*. % 76.16/76.34 145640[99:MRR:544.0,145639.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 145641[100:Spt:145640.0] || -> until2p7(s46)*. % 76.16/76.34 145642[100:MRR:549.0,145641.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 145643[101:Spt:145642.0] || -> until2p7(s47)*. % 76.16/76.34 145644[101:MRR:554.0,145643.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 145645[102:Spt:145644.0] || -> until2p7(s48)*. % 76.16/76.34 145646[102:MRR:559.0,145645.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 145647[103:Spt:145646.0] || -> until2p7(s49)*. % 76.16/76.34 145648[103:MRR:194.0,145647.0] || -> node4(s49)*. % 76.16/76.34 145649[103:MRR:145595.0,145648.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 145650[103:Res:53.1,145649.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 145652[103:MRR:145650.0,78381.0] || -> . % 76.16/76.34 145653[103:Spt:145652.0,145646.0,145647.0] || until2p7(s49)*+ -> . % 76.16/76.34 145654[103:Spt:145652.0,145646.1] || -> node4(s48)*. % 76.16/76.34 145655[103:MRR:78384.0,145654.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 145658[103:Res:53.1,145655.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 145661[103:Res:145658.0,61.1] always3(s48) || -> . % 76.16/76.34 145662[103:SSi:145661.0,78281.0,78387.0,137770.0,145645.0,145654.0] || -> . % 76.16/76.34 145663[102:Spt:145662.0,145644.0,145645.0] || until2p7(s48)*+ -> . % 76.16/76.34 145664[102:Spt:145662.0,145644.1] || -> node4(s47)*. % 76.16/76.34 145666[102:MRR:777.0,145664.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 145681[102:Res:53.1,145666.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 145683[103:Spt:145681.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 145685[103:Res:145683.0,61.1] always3(s47) || -> . % 76.16/76.34 145686[103:SSi:145685.0,78277.0,78280.0,137769.0,145643.0,145664.0] || -> . % 76.16/76.34 145687[103:Spt:145686.0,145681.0,145683.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 145688[103:Spt:145686.0,145681.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 145692[103:Res:145688.0,61.1] always3(s48) || -> . % 76.16/76.34 145693[103:SSi:145692.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 145694[101:Spt:145693.0,145642.0,145643.0] || until2p7(s47)*+ -> . % 76.16/76.34 145695[101:Spt:145693.0,145642.1] || -> node4(s46)*. % 76.16/76.34 145697[101:MRR:780.0,145695.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 145707[101:Res:53.1,145697.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 145709[102:Spt:145707.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 145711[102:Res:145709.0,61.1] always3(s46) || -> . % 76.16/76.34 145712[102:SSi:145711.0,78272.0,78276.0,137768.0,145641.0,145695.0] || -> . % 76.16/76.34 145713[102:Spt:145712.0,145707.0,145709.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 145714[102:Spt:145712.0,145707.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 145718[102:Res:145714.0,61.1] always3(s47) || -> . % 76.16/76.34 145719[102:SSi:145718.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 145720[100:Spt:145719.0,145640.0,145641.0] || until2p7(s46)*+ -> . % 76.16/76.34 145721[100:Spt:145719.0,145640.1] || -> node4(s45)*. % 76.16/76.34 145723[100:MRR:783.0,145721.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 145726[100:Res:53.1,145723.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 145728[101:Spt:145726.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 145730[101:Res:145728.0,61.1] always3(s45) || -> . % 76.16/76.34 145731[101:SSi:145730.0,78268.0,78271.0,137767.0,145639.0,145721.0] || -> . % 76.16/76.34 145732[101:Spt:145731.0,145726.0,145728.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 145733[101:Spt:145731.0,145726.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 145737[101:Res:145733.0,61.1] always3(s46) || -> . % 76.16/76.34 145738[101:SSi:145737.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 145739[99:Spt:145738.0,145638.0,145639.0] || until2p7(s45)*+ -> . % 76.16/76.34 145740[99:Spt:145738.0,145638.1] || -> node4(s44)*. % 76.16/76.34 145742[99:MRR:786.0,145740.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 145745[99:Res:53.1,145742.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 145747[100:Spt:145745.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 145749[100:Res:145747.0,61.1] always3(s44) || -> . % 76.16/76.34 145750[100:SSi:145749.0,78263.0,78267.0,137766.0,145637.0,145740.0] || -> . % 76.16/76.34 145751[100:Spt:145750.0,145745.0,145747.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 145752[100:Spt:145750.0,145745.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 145756[100:Res:145752.0,61.1] always3(s45) || -> . % 76.16/76.34 145757[100:SSi:145756.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 145758[98:Spt:145757.0,145636.0,145637.0] || until2p7(s44)*+ -> . % 76.16/76.34 145759[98:Spt:145757.0,145636.1] || -> node4(s43)*. % 76.16/76.34 145761[98:MRR:789.0,145759.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 145764[98:Res:53.1,145761.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 145769[99:Spt:145764.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 145771[99:Res:145769.0,61.1] always3(s43) || -> . % 76.16/76.34 145772[99:SSi:145771.0,78259.0,78262.0,137765.0,145635.0,145759.0] || -> . % 76.16/76.34 145773[99:Spt:145772.0,145764.0,145769.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 145774[99:Spt:145772.0,145764.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 145778[99:Res:145774.0,61.1] always3(s44) || -> . % 76.16/76.34 145779[99:SSi:145778.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 145780[97:Spt:145779.0,145634.0,145635.0] || until2p7(s43)*+ -> . % 76.16/76.34 145781[97:Spt:145779.0,145634.1] || -> node4(s42)*. % 76.16/76.34 145783[97:MRR:792.0,145781.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 145786[97:Res:53.1,145783.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 145788[98:Spt:145786.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 145790[98:Res:145788.0,61.1] always3(s42) || -> . % 76.16/76.34 145791[98:SSi:145790.0,78254.0,78258.0,137764.0,145633.0,145781.0] || -> . % 76.16/76.34 145792[98:Spt:145791.0,145786.0,145788.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 145793[98:Spt:145791.0,145786.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 145797[98:Res:145793.0,61.1] always3(s43) || -> . % 76.16/76.34 145798[98:SSi:145797.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 145799[96:Spt:145798.0,145632.0,145633.0] || until2p7(s42)*+ -> . % 76.16/76.34 145800[96:Spt:145798.0,145632.1] || -> node4(s41)*. % 76.16/76.34 145802[96:MRR:795.0,145800.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 145805[96:Res:53.1,145802.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 145807[97:Spt:145805.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 145809[97:Res:145807.0,61.1] always3(s41) || -> . % 76.16/76.34 145810[97:SSi:145809.0,78250.0,78253.0,137763.0,145631.0,145800.0] || -> . % 76.16/76.34 145811[97:Spt:145810.0,145805.0,145807.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 145812[97:Spt:145810.0,145805.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 145816[97:Res:145812.0,61.1] always3(s42) || -> . % 76.16/76.34 145817[97:SSi:145816.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 145818[95:Spt:145817.0,145630.0,145631.0] || until2p7(s41)*+ -> . % 76.16/76.34 145819[95:Spt:145817.0,145630.1] || -> node4(s40)*. % 76.16/76.34 145821[95:MRR:798.0,145819.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 145824[95:Res:53.1,145821.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 145826[96:Spt:145824.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 145828[96:Res:145826.0,61.1] always3(s40) || -> . % 76.16/76.34 145829[96:SSi:145828.0,78245.0,78249.0,137762.0,145629.0,145819.0] || -> . % 76.16/76.34 145830[96:Spt:145829.0,145824.0,145826.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 145831[96:Spt:145829.0,145824.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 145835[96:Res:145831.0,61.1] always3(s41) || -> . % 76.16/76.34 145836[96:SSi:145835.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 145837[94:Spt:145836.0,145628.0,145629.0] || until2p7(s40)*+ -> . % 76.16/76.34 145838[94:Spt:145836.0,145628.1] || -> node4(s39)*. % 76.16/76.34 145840[94:MRR:801.0,145838.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 145843[94:Res:53.1,145840.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 145848[95:Spt:145843.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 145850[95:Res:145848.0,61.1] always3(s39) || -> . % 76.16/76.34 145851[95:SSi:145850.0,78241.0,78244.0,137761.0,145627.0,145838.0] || -> . % 76.16/76.34 145852[95:Spt:145851.0,145843.0,145848.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 145853[95:Spt:145851.0,145843.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 145857[95:Res:145853.0,61.1] always3(s40) || -> . % 76.16/76.34 145858[95:SSi:145857.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 145859[93:Spt:145858.0,145626.0,145627.0] || until2p7(s39)*+ -> . % 76.16/76.34 145860[93:Spt:145858.0,145626.1] || -> node4(s38)*. % 76.16/76.34 145862[93:MRR:804.0,145860.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 145865[93:Res:53.1,145862.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 145867[94:Spt:145865.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 145869[94:Res:145867.0,61.1] always3(s38) || -> . % 76.16/76.34 145870[94:SSi:145869.0,78236.0,78240.0,137760.0,145625.0,145860.0] || -> . % 76.16/76.34 145871[94:Spt:145870.0,145865.0,145867.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 145872[94:Spt:145870.0,145865.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 145876[94:Res:145872.0,61.1] always3(s39) || -> . % 76.16/76.34 145877[94:SSi:145876.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 145878[92:Spt:145877.0,145624.0,145625.0] || until2p7(s38)*+ -> . % 76.16/76.34 145879[92:Spt:145877.0,145624.1] || -> node4(s37)*. % 76.16/76.34 145881[92:MRR:807.0,145879.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 145884[92:Res:53.1,145881.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 145886[93:Spt:145884.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 145888[93:Res:145886.0,61.1] always3(s37) || -> . % 76.16/76.34 145889[93:SSi:145888.0,78232.0,78235.0,137759.0,145623.0,145879.0] || -> . % 76.16/76.34 145890[93:Spt:145889.0,145884.0,145886.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 145891[93:Spt:145889.0,145884.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 145895[93:Res:145891.0,61.1] always3(s38) || -> . % 76.16/76.34 145896[93:SSi:145895.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 145897[91:Spt:145896.0,145622.0,145623.0] || until2p7(s37)*+ -> . % 76.16/76.34 145898[91:Spt:145896.0,145622.1] || -> node4(s36)*. % 76.16/76.34 145900[91:MRR:810.0,145898.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 145903[91:Res:53.1,145900.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 145905[92:Spt:145903.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 145907[92:Res:145905.0,61.1] always3(s36) || -> . % 76.16/76.34 145908[92:SSi:145907.0,78227.0,78231.0,137758.0,145621.0,145898.0] || -> . % 76.16/76.34 145909[92:Spt:145908.0,145903.0,145905.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 145910[92:Spt:145908.0,145903.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 145914[92:Res:145910.0,61.1] always3(s37) || -> . % 76.16/76.34 145915[92:SSi:145914.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 145916[90:Spt:145915.0,145620.0,145621.0] || until2p7(s36)*+ -> . % 76.16/76.34 145917[90:Spt:145915.0,145620.1] || -> node4(s35)*. % 76.16/76.34 145919[90:MRR:813.0,145917.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 145922[90:Res:53.1,145919.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 145927[91:Spt:145922.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 145929[91:Res:145927.0,61.1] always3(s35) || -> . % 76.16/76.34 145930[91:SSi:145929.0,78223.0,78226.0,137757.0,145619.0,145917.0] || -> . % 76.16/76.34 145931[91:Spt:145930.0,145922.0,145927.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 145932[91:Spt:145930.0,145922.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 145936[91:Res:145932.0,61.1] always3(s36) || -> . % 76.16/76.34 145937[91:SSi:145936.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 145938[89:Spt:145937.0,145618.0,145619.0] || until2p7(s35)*+ -> . % 76.16/76.34 145939[89:Spt:145937.0,145618.1] || -> node4(s34)*. % 76.16/76.34 145941[89:MRR:816.0,145939.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 145944[89:Res:53.1,145941.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 145946[90:Spt:145944.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 145948[90:Res:145946.0,61.1] always3(s34) || -> . % 76.16/76.34 145949[90:SSi:145948.0,78218.0,78222.0,137756.0,145617.0,145939.0] || -> . % 76.16/76.34 145950[90:Spt:145949.0,145944.0,145946.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 145951[90:Spt:145949.0,145944.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 145955[90:Res:145951.0,61.1] always3(s35) || -> . % 76.16/76.34 145956[90:SSi:145955.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 145957[88:Spt:145956.0,145616.0,145617.0] || until2p7(s34)*+ -> . % 76.16/76.34 145958[88:Spt:145956.0,145616.1] || -> node4(s33)*. % 76.16/76.34 145960[88:MRR:819.0,145958.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 145963[88:Res:53.1,145960.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 145965[89:Spt:145963.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 145967[89:Res:145965.0,61.1] always3(s33) || -> . % 76.16/76.34 145968[89:SSi:145967.0,78214.0,78217.0,137755.0,145615.0,145958.0] || -> . % 76.16/76.34 145969[89:Spt:145968.0,145963.0,145965.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.34 145970[89:Spt:145968.0,145963.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 145974[89:Res:145970.0,61.1] always3(s34) || -> . % 76.16/76.34 145975[89:SSi:145974.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 145976[87:Spt:145975.0,145614.0,145615.0] || until2p7(s33)*+ -> . % 76.16/76.34 145977[87:Spt:145975.0,145614.1] || -> node4(s32)*. % 76.16/76.34 145979[87:MRR:822.0,145977.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.34 145982[87:Res:53.1,145979.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.34 145984[88:Spt:145982.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 145986[88:Res:145984.0,61.1] always3(s32) || -> . % 76.16/76.34 145987[88:SSi:145986.0,78209.0,78213.0,137754.0,145613.0,145977.0] || -> . % 76.16/76.34 145988[88:Spt:145987.0,145982.0,145984.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.34 145989[88:Spt:145987.0,145982.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 145993[88:Res:145989.0,61.1] always3(s33) || -> . % 76.16/76.34 145994[88:SSi:145993.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 145995[86:Spt:145994.0,145612.0,145613.0] || until2p7(s32)*+ -> . % 76.16/76.34 145996[86:Spt:145994.0,145612.1] || -> node4(s31)*. % 76.16/76.34 145998[86:MRR:825.0,145996.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.34 146001[86:Res:53.1,145998.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.34 146006[87:Spt:146001.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 146008[87:Res:146006.0,61.1] always3(s31) || -> . % 76.16/76.34 146009[87:SSi:146008.0,78205.0,78208.0,137753.0,145611.0,145996.0] || -> . % 76.16/76.34 146010[87:Spt:146009.0,146001.0,146006.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.34 146011[87:Spt:146009.0,146001.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 146015[87:Res:146011.0,61.1] always3(s32) || -> . % 76.16/76.34 146016[87:SSi:146015.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.34 146017[85:Spt:146016.0,145610.0,145611.0] || until2p7(s31)*+ -> . % 76.16/76.34 146018[85:Spt:146016.0,145610.1] || -> node4(s30)*. % 76.16/76.34 146020[85:MRR:828.0,146018.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.34 146023[85:Res:53.1,146020.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.34 146025[86:Spt:146023.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 146027[86:Res:146025.0,61.1] always3(s30) || -> . % 76.16/76.34 146028[86:SSi:146027.0,78200.0,78204.0,137752.0,145609.0,146018.0] || -> . % 76.16/76.34 146029[86:Spt:146028.0,146023.0,146025.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.34 146030[86:Spt:146028.0,146023.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 146034[86:Res:146030.0,61.1] always3(s31) || -> . % 76.16/76.34 146035[86:SSi:146034.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.34 146036[84:Spt:146035.0,145608.0,145609.0] || until2p7(s30)*+ -> . % 76.16/76.34 146037[84:Spt:146035.0,145608.1] || -> node4(s29)*. % 76.16/76.34 146039[84:MRR:831.0,146037.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.34 146042[84:Res:53.1,146039.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.34 146044[85:Spt:146042.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 146046[85:Res:146044.0,61.1] always3(s29) || -> . % 76.16/76.34 146047[85:SSi:146046.0,78196.0,78199.0,137751.0,145607.0,146037.0] || -> . % 76.16/76.34 146048[85:Spt:146047.0,146042.0,146044.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.34 146049[85:Spt:146047.0,146042.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 146053[85:Res:146049.0,61.1] always3(s30) || -> . % 76.16/76.34 146054[85:SSi:146053.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.34 146055[83:Spt:146054.0,145606.0,145607.0] || until2p7(s29)*+ -> . % 76.16/76.34 146056[83:Spt:146054.0,145606.1] || -> node4(s28)*. % 76.16/76.34 146058[83:MRR:834.0,146056.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.34 146061[83:Res:53.1,146058.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.34 146063[84:Spt:146061.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 146065[84:Res:146063.0,61.1] always3(s28) || -> . % 76.16/76.34 146066[84:SSi:146065.0,78191.0,78195.0,137750.0,145605.0,146056.0] || -> . % 76.16/76.34 146067[84:Spt:146066.0,146061.0,146063.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.34 146068[84:Spt:146066.0,146061.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 146072[84:Res:146068.0,61.1] always3(s29) || -> . % 76.16/76.34 146073[84:SSi:146072.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.34 146074[82:Spt:146073.0,145604.0,145605.0] || until2p7(s28)*+ -> . % 76.16/76.34 146075[82:Spt:146073.0,145604.1] || -> node4(s27)*. % 76.16/76.34 146077[82:MRR:837.0,146075.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.34 146080[82:Res:53.1,146077.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.34 146085[83:Spt:146080.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 146087[83:Res:146085.0,61.1] always3(s27) || -> . % 76.16/76.34 146088[83:SSi:146087.0,78187.0,78190.0,137749.0,145603.0,146075.0] || -> . % 76.16/76.34 146089[83:Spt:146088.0,146080.0,146085.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.34 146090[83:Spt:146088.0,146080.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 146094[83:Res:146090.0,61.1] always3(s28) || -> . % 76.16/76.34 146095[83:SSi:146094.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.34 146096[81:Spt:146095.0,145602.0,145603.0] || until2p7(s27)*+ -> . % 76.16/76.34 146097[81:Spt:146095.0,145602.1] || -> node4(s26)*. % 76.16/76.34 146099[81:MRR:840.0,146097.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.34 146102[81:Res:53.1,146099.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.34 146104[82:Spt:146102.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 146106[82:Res:146104.0,61.1] always3(s26) || -> . % 76.16/76.34 146107[82:SSi:146106.0,78182.0,78186.0,137748.0,145601.0,146097.0] || -> . % 76.16/76.34 146108[82:Spt:146107.0,146102.0,146104.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.34 146109[82:Spt:146107.0,146102.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 146113[82:Res:146109.0,61.1] always3(s27) || -> . % 76.16/76.34 146114[82:SSi:146113.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.34 146115[80:Spt:146114.0,145600.0,145601.0] || until2p7(s26)*+ -> . % 76.16/76.34 146116[80:Spt:146114.0,145600.1] || -> node4(s25)*. % 76.16/76.34 146118[80:MRR:843.0,146116.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.34 146121[80:Res:53.1,146118.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.34 146123[80:MRR:146121.0,145590.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 146125[80:Res:146123.0,61.1] always3(s26) || -> . % 76.16/76.34 146126[80:SSi:146125.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.34 146127[78:Spt:146126.0,145493.0,145496.0] || trans(s49,s25)*+ -> . % 76.16/76.34 146128[78:Spt:146126.0,145493.1,145493.2,145493.3,145493.4,145493.5,145493.6,145493.7,145493.8,145493.9,145493.10,145493.11,145493.12,145493.13,145493.14,145493.15,145493.16,145493.17,145493.18,145493.19,145493.20,145493.21] || -> trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 146130[78:MRR:145495.1,146127.0] xuntil6(s49) || -> trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 146131[79:Spt:146128.0] || -> trans(s49,s24)*. % 76.16/76.34 146132[79:Res:146131.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s24)*. % 76.16/76.34 146134[79:Res:146131.0,60.0] || -> node2(s49,s24)*. % 76.16/76.34 146135[79:SSi:146132.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s24)*. % 76.16/76.34 146136[79:Res:146134.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)*. % 76.16/76.34 146221[79:SoR:146136.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)*. % 76.16/76.34 146223[79:SoR:146221.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)* xuntil6(s49). % 76.16/76.34 146224[79:SSi:146223.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s24,c_busy)* xuntil6(s49). % 76.16/76.34 146225[80:Spt:146224.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.34 146227[80:Res:146225.0,61.1] always3(s24) || -> . % 76.16/76.34 146228[80:SSi:146227.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.34 146229[80:Spt:146228.0,146224.1,146225.0] || m_main_v_state(s24,c_busy)*+ -> . % 76.16/76.34 146230[80:Spt:146228.0,146224.0,146224.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 146234[80:MRR:146221.2,146229.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 146235[80:Res:53.1,146230.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 146237[80:MRR:146235.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 146238[80:MRR:146135.0,146237.0] || -> until2p7(s24)*. % 76.16/76.34 146239[80:MRR:220.0,146238.0] || -> until2p7(s25)* node4(s24). % 76.16/76.34 146240[81:Spt:146239.0] || -> until2p7(s25)*. % 76.16/76.34 146241[81:MRR:221.0,146240.0] || -> until2p7(s26)* node4(s25). % 76.16/76.34 146242[82:Spt:146241.0] || -> until2p7(s26)*. % 76.16/76.34 146243[82:MRR:222.0,146242.0] || -> until2p7(s27)* node4(s26). % 76.16/76.34 146244[83:Spt:146243.0] || -> until2p7(s27)*. % 76.16/76.34 146245[83:MRR:223.0,146244.0] || -> until2p7(s28)* node4(s27). % 76.16/76.34 146246[84:Spt:146245.0] || -> until2p7(s28)*. % 76.16/76.34 146247[84:MRR:224.0,146246.0] || -> until2p7(s29)* node4(s28). % 76.16/76.34 146248[85:Spt:146247.0] || -> until2p7(s29)*. % 76.16/76.34 146249[85:MRR:225.0,146248.0] || -> until2p7(s30)* node4(s29). % 76.16/76.34 146250[86:Spt:146249.0] || -> until2p7(s30)*. % 76.16/76.34 146251[86:MRR:226.0,146250.0] || -> until2p7(s31)* node4(s30). % 76.16/76.34 146252[87:Spt:146251.0] || -> until2p7(s31)*. % 76.16/76.34 146253[87:MRR:227.0,146252.0] || -> until2p7(s32)* node4(s31). % 76.16/76.34 146254[88:Spt:146253.0] || -> until2p7(s32)*. % 76.16/76.34 146255[88:MRR:228.0,146254.0] || -> until2p7(s33)* node4(s32). % 76.16/76.34 146256[89:Spt:146255.0] || -> until2p7(s33)*. % 76.16/76.34 146257[89:MRR:229.0,146256.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 146258[90:Spt:146257.0] || -> until2p7(s34)*. % 76.16/76.34 146259[90:MRR:230.0,146258.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 146260[91:Spt:146259.0] || -> until2p7(s35)*. % 76.16/76.34 146261[91:MRR:231.0,146260.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 146262[92:Spt:146261.0] || -> until2p7(s36)*. % 76.16/76.34 146263[92:MRR:232.0,146262.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 146264[93:Spt:146263.0] || -> until2p7(s37)*. % 76.16/76.34 146265[93:MRR:235.0,146264.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 146266[94:Spt:146265.0] || -> until2p7(s38)*. % 76.16/76.34 146267[94:MRR:236.0,146266.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 146268[95:Spt:146267.0] || -> until2p7(s39)*. % 76.16/76.34 146269[95:MRR:237.0,146268.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 146270[96:Spt:146269.0] || -> until2p7(s40)*. % 76.16/76.34 146271[96:MRR:238.0,146270.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 146272[97:Spt:146271.0] || -> until2p7(s41)*. % 76.16/76.34 146273[97:MRR:239.0,146272.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 146274[98:Spt:146273.0] || -> until2p7(s42)*. % 76.16/76.34 146275[98:MRR:240.0,146274.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 146276[99:Spt:146275.0] || -> until2p7(s43)*. % 76.16/76.34 146277[99:MRR:241.0,146276.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 146278[100:Spt:146277.0] || -> until2p7(s44)*. % 76.16/76.34 146279[100:MRR:539.0,146278.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 146280[101:Spt:146279.0] || -> until2p7(s45)*. % 76.16/76.34 146281[101:MRR:544.0,146280.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 146282[102:Spt:146281.0] || -> until2p7(s46)*. % 76.16/76.34 146283[102:MRR:549.0,146282.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 146284[103:Spt:146283.0] || -> until2p7(s47)*. % 76.16/76.34 146285[103:MRR:554.0,146284.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 146286[104:Spt:146285.0] || -> until2p7(s48)*. % 76.16/76.34 146287[104:MRR:559.0,146286.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 146288[105:Spt:146287.0] || -> until2p7(s49)*. % 76.16/76.34 146289[105:MRR:194.0,146288.0] || -> node4(s49)*. % 76.16/76.34 146290[105:MRR:146234.0,146289.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 146291[105:Res:53.1,146290.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 146293[105:MRR:146291.0,78381.0] || -> . % 76.16/76.34 146294[105:Spt:146293.0,146287.0,146288.0] || until2p7(s49)*+ -> . % 76.16/76.34 146295[105:Spt:146293.0,146287.1] || -> node4(s48)*. % 76.16/76.34 146296[105:MRR:78384.0,146295.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 146299[105:Res:53.1,146296.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 146302[105:Res:146299.0,61.1] always3(s48) || -> . % 76.16/76.34 146303[105:SSi:146302.0,78281.0,78387.0,137770.0,146286.0,146295.0] || -> . % 76.16/76.34 146304[104:Spt:146303.0,146285.0,146286.0] || until2p7(s48)*+ -> . % 76.16/76.34 146305[104:Spt:146303.0,146285.1] || -> node4(s47)*. % 76.16/76.34 146307[104:MRR:777.0,146305.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 146322[104:Res:53.1,146307.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 146324[105:Spt:146322.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 146326[105:Res:146324.0,61.1] always3(s47) || -> . % 76.16/76.34 146327[105:SSi:146326.0,78277.0,78280.0,137769.0,146284.0,146305.0] || -> . % 76.16/76.34 146328[105:Spt:146327.0,146322.0,146324.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 146329[105:Spt:146327.0,146322.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 146333[105:Res:146329.0,61.1] always3(s48) || -> . % 76.16/76.34 146334[105:SSi:146333.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 146335[103:Spt:146334.0,146283.0,146284.0] || until2p7(s47)*+ -> . % 76.16/76.34 146336[103:Spt:146334.0,146283.1] || -> node4(s46)*. % 76.16/76.34 146338[103:MRR:780.0,146336.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 146348[103:Res:53.1,146338.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 146350[104:Spt:146348.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 146352[104:Res:146350.0,61.1] always3(s46) || -> . % 76.16/76.34 146353[104:SSi:146352.0,78272.0,78276.0,137768.0,146282.0,146336.0] || -> . % 76.16/76.34 146354[104:Spt:146353.0,146348.0,146350.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 146355[104:Spt:146353.0,146348.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 146359[104:Res:146355.0,61.1] always3(s47) || -> . % 76.16/76.34 146360[104:SSi:146359.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 146361[102:Spt:146360.0,146281.0,146282.0] || until2p7(s46)*+ -> . % 76.16/76.34 146362[102:Spt:146360.0,146281.1] || -> node4(s45)*. % 76.16/76.34 146364[102:MRR:783.0,146362.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 146367[102:Res:53.1,146364.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 146369[103:Spt:146367.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 146371[103:Res:146369.0,61.1] always3(s45) || -> . % 76.16/76.34 146372[103:SSi:146371.0,78268.0,78271.0,137767.0,146280.0,146362.0] || -> . % 76.16/76.34 146373[103:Spt:146372.0,146367.0,146369.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 146374[103:Spt:146372.0,146367.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 146378[103:Res:146374.0,61.1] always3(s46) || -> . % 76.16/76.34 146379[103:SSi:146378.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 146380[101:Spt:146379.0,146279.0,146280.0] || until2p7(s45)*+ -> . % 76.16/76.34 146381[101:Spt:146379.0,146279.1] || -> node4(s44)*. % 76.16/76.34 146383[101:MRR:786.0,146381.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 146386[101:Res:53.1,146383.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 146388[102:Spt:146386.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 146390[102:Res:146388.0,61.1] always3(s44) || -> . % 76.16/76.34 146391[102:SSi:146390.0,78263.0,78267.0,137766.0,146278.0,146381.0] || -> . % 76.16/76.34 146392[102:Spt:146391.0,146386.0,146388.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 146393[102:Spt:146391.0,146386.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 146397[102:Res:146393.0,61.1] always3(s45) || -> . % 76.16/76.34 146398[102:SSi:146397.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 146399[100:Spt:146398.0,146277.0,146278.0] || until2p7(s44)*+ -> . % 76.16/76.34 146400[100:Spt:146398.0,146277.1] || -> node4(s43)*. % 76.16/76.34 146402[100:MRR:789.0,146400.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 146405[100:Res:53.1,146402.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 146410[101:Spt:146405.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 146412[101:Res:146410.0,61.1] always3(s43) || -> . % 76.16/76.34 146413[101:SSi:146412.0,78259.0,78262.0,137765.0,146276.0,146400.0] || -> . % 76.16/76.34 146414[101:Spt:146413.0,146405.0,146410.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 146415[101:Spt:146413.0,146405.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 146419[101:Res:146415.0,61.1] always3(s44) || -> . % 76.16/76.34 146420[101:SSi:146419.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 146421[99:Spt:146420.0,146275.0,146276.0] || until2p7(s43)*+ -> . % 76.16/76.34 146422[99:Spt:146420.0,146275.1] || -> node4(s42)*. % 76.16/76.34 146424[99:MRR:792.0,146422.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 146427[99:Res:53.1,146424.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 146429[100:Spt:146427.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 146431[100:Res:146429.0,61.1] always3(s42) || -> . % 76.16/76.34 146432[100:SSi:146431.0,78254.0,78258.0,137764.0,146274.0,146422.0] || -> . % 76.16/76.34 146433[100:Spt:146432.0,146427.0,146429.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 146434[100:Spt:146432.0,146427.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 146438[100:Res:146434.0,61.1] always3(s43) || -> . % 76.16/76.34 146439[100:SSi:146438.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 146440[98:Spt:146439.0,146273.0,146274.0] || until2p7(s42)*+ -> . % 76.16/76.34 146441[98:Spt:146439.0,146273.1] || -> node4(s41)*. % 76.16/76.34 146443[98:MRR:795.0,146441.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 146446[98:Res:53.1,146443.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 146448[99:Spt:146446.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 146450[99:Res:146448.0,61.1] always3(s41) || -> . % 76.16/76.34 146451[99:SSi:146450.0,78250.0,78253.0,137763.0,146272.0,146441.0] || -> . % 76.16/76.34 146452[99:Spt:146451.0,146446.0,146448.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 146453[99:Spt:146451.0,146446.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 146457[99:Res:146453.0,61.1] always3(s42) || -> . % 76.16/76.34 146458[99:SSi:146457.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 146459[97:Spt:146458.0,146271.0,146272.0] || until2p7(s41)*+ -> . % 76.16/76.34 146460[97:Spt:146458.0,146271.1] || -> node4(s40)*. % 76.16/76.34 146462[97:MRR:798.0,146460.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 146465[97:Res:53.1,146462.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 146467[98:Spt:146465.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 146469[98:Res:146467.0,61.1] always3(s40) || -> . % 76.16/76.34 146470[98:SSi:146469.0,78245.0,78249.0,137762.0,146270.0,146460.0] || -> . % 76.16/76.34 146471[98:Spt:146470.0,146465.0,146467.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 146472[98:Spt:146470.0,146465.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 146476[98:Res:146472.0,61.1] always3(s41) || -> . % 76.16/76.34 146477[98:SSi:146476.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 146478[96:Spt:146477.0,146269.0,146270.0] || until2p7(s40)*+ -> . % 76.16/76.34 146479[96:Spt:146477.0,146269.1] || -> node4(s39)*. % 76.16/76.34 146481[96:MRR:801.0,146479.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 146484[96:Res:53.1,146481.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 146489[97:Spt:146484.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 146491[97:Res:146489.0,61.1] always3(s39) || -> . % 76.16/76.34 146492[97:SSi:146491.0,78241.0,78244.0,137761.0,146268.0,146479.0] || -> . % 76.16/76.34 146493[97:Spt:146492.0,146484.0,146489.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 146494[97:Spt:146492.0,146484.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 146498[97:Res:146494.0,61.1] always3(s40) || -> . % 76.16/76.34 146499[97:SSi:146498.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 146500[95:Spt:146499.0,146267.0,146268.0] || until2p7(s39)*+ -> . % 76.16/76.34 146501[95:Spt:146499.0,146267.1] || -> node4(s38)*. % 76.16/76.34 146503[95:MRR:804.0,146501.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 146506[95:Res:53.1,146503.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 146508[96:Spt:146506.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 146510[96:Res:146508.0,61.1] always3(s38) || -> . % 76.16/76.34 146511[96:SSi:146510.0,78236.0,78240.0,137760.0,146266.0,146501.0] || -> . % 76.16/76.34 146512[96:Spt:146511.0,146506.0,146508.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 146513[96:Spt:146511.0,146506.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 146517[96:Res:146513.0,61.1] always3(s39) || -> . % 76.16/76.34 146518[96:SSi:146517.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 146519[94:Spt:146518.0,146265.0,146266.0] || until2p7(s38)*+ -> . % 76.16/76.34 146520[94:Spt:146518.0,146265.1] || -> node4(s37)*. % 76.16/76.34 146522[94:MRR:807.0,146520.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 146525[94:Res:53.1,146522.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 146527[95:Spt:146525.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 146529[95:Res:146527.0,61.1] always3(s37) || -> . % 76.16/76.34 146530[95:SSi:146529.0,78232.0,78235.0,137759.0,146264.0,146520.0] || -> . % 76.16/76.34 146531[95:Spt:146530.0,146525.0,146527.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 146532[95:Spt:146530.0,146525.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 146536[95:Res:146532.0,61.1] always3(s38) || -> . % 76.16/76.34 146537[95:SSi:146536.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 146538[93:Spt:146537.0,146263.0,146264.0] || until2p7(s37)*+ -> . % 76.16/76.34 146539[93:Spt:146537.0,146263.1] || -> node4(s36)*. % 76.16/76.34 146541[93:MRR:810.0,146539.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 146544[93:Res:53.1,146541.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 146546[94:Spt:146544.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 146548[94:Res:146546.0,61.1] always3(s36) || -> . % 76.16/76.34 146549[94:SSi:146548.0,78227.0,78231.0,137758.0,146262.0,146539.0] || -> . % 76.16/76.34 146550[94:Spt:146549.0,146544.0,146546.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 146551[94:Spt:146549.0,146544.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 146555[94:Res:146551.0,61.1] always3(s37) || -> . % 76.16/76.34 146556[94:SSi:146555.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 146557[92:Spt:146556.0,146261.0,146262.0] || until2p7(s36)*+ -> . % 76.16/76.34 146558[92:Spt:146556.0,146261.1] || -> node4(s35)*. % 76.16/76.34 146560[92:MRR:813.0,146558.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 146563[92:Res:53.1,146560.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 146568[93:Spt:146563.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 146570[93:Res:146568.0,61.1] always3(s35) || -> . % 76.16/76.34 146571[93:SSi:146570.0,78223.0,78226.0,137757.0,146260.0,146558.0] || -> . % 76.16/76.34 146572[93:Spt:146571.0,146563.0,146568.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 146573[93:Spt:146571.0,146563.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 146577[93:Res:146573.0,61.1] always3(s36) || -> . % 76.16/76.34 146578[93:SSi:146577.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 146579[91:Spt:146578.0,146259.0,146260.0] || until2p7(s35)*+ -> . % 76.16/76.34 146580[91:Spt:146578.0,146259.1] || -> node4(s34)*. % 76.16/76.34 146582[91:MRR:816.0,146580.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 146585[91:Res:53.1,146582.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 146587[92:Spt:146585.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 146589[92:Res:146587.0,61.1] always3(s34) || -> . % 76.16/76.34 146590[92:SSi:146589.0,78218.0,78222.0,137756.0,146258.0,146580.0] || -> . % 76.16/76.34 146591[92:Spt:146590.0,146585.0,146587.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 146592[92:Spt:146590.0,146585.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 146596[92:Res:146592.0,61.1] always3(s35) || -> . % 76.16/76.34 146597[92:SSi:146596.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 146598[90:Spt:146597.0,146257.0,146258.0] || until2p7(s34)*+ -> . % 76.16/76.34 146599[90:Spt:146597.0,146257.1] || -> node4(s33)*. % 76.16/76.34 146601[90:MRR:819.0,146599.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 146604[90:Res:53.1,146601.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 146606[91:Spt:146604.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 146608[91:Res:146606.0,61.1] always3(s33) || -> . % 76.16/76.34 146609[91:SSi:146608.0,78214.0,78217.0,137755.0,146256.0,146599.0] || -> . % 76.16/76.34 146610[91:Spt:146609.0,146604.0,146606.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.34 146611[91:Spt:146609.0,146604.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 146615[91:Res:146611.0,61.1] always3(s34) || -> . % 76.16/76.34 146616[91:SSi:146615.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 146617[89:Spt:146616.0,146255.0,146256.0] || until2p7(s33)*+ -> . % 76.16/76.34 146618[89:Spt:146616.0,146255.1] || -> node4(s32)*. % 76.16/76.34 146620[89:MRR:822.0,146618.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.34 146623[89:Res:53.1,146620.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.34 146625[90:Spt:146623.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 146627[90:Res:146625.0,61.1] always3(s32) || -> . % 76.16/76.34 146628[90:SSi:146627.0,78209.0,78213.0,137754.0,146254.0,146618.0] || -> . % 76.16/76.34 146629[90:Spt:146628.0,146623.0,146625.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.34 146630[90:Spt:146628.0,146623.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 146634[90:Res:146630.0,61.1] always3(s33) || -> . % 76.16/76.34 146635[90:SSi:146634.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 146636[88:Spt:146635.0,146253.0,146254.0] || until2p7(s32)*+ -> . % 76.16/76.34 146637[88:Spt:146635.0,146253.1] || -> node4(s31)*. % 76.16/76.34 146639[88:MRR:825.0,146637.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.34 146642[88:Res:53.1,146639.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.34 146647[89:Spt:146642.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 146649[89:Res:146647.0,61.1] always3(s31) || -> . % 76.16/76.34 146650[89:SSi:146649.0,78205.0,78208.0,137753.0,146252.0,146637.0] || -> . % 76.16/76.34 146651[89:Spt:146650.0,146642.0,146647.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.34 146652[89:Spt:146650.0,146642.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 146656[89:Res:146652.0,61.1] always3(s32) || -> . % 76.16/76.34 146657[89:SSi:146656.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.34 146658[87:Spt:146657.0,146251.0,146252.0] || until2p7(s31)*+ -> . % 76.16/76.34 146659[87:Spt:146657.0,146251.1] || -> node4(s30)*. % 76.16/76.34 146661[87:MRR:828.0,146659.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.34 146664[87:Res:53.1,146661.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.34 146666[88:Spt:146664.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 146668[88:Res:146666.0,61.1] always3(s30) || -> . % 76.16/76.34 146669[88:SSi:146668.0,78200.0,78204.0,137752.0,146250.0,146659.0] || -> . % 76.16/76.34 146670[88:Spt:146669.0,146664.0,146666.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.34 146671[88:Spt:146669.0,146664.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 146675[88:Res:146671.0,61.1] always3(s31) || -> . % 76.16/76.34 146676[88:SSi:146675.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.34 146677[86:Spt:146676.0,146249.0,146250.0] || until2p7(s30)*+ -> . % 76.16/76.34 146678[86:Spt:146676.0,146249.1] || -> node4(s29)*. % 76.16/76.34 146680[86:MRR:831.0,146678.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.34 146683[86:Res:53.1,146680.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.34 146685[87:Spt:146683.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 146687[87:Res:146685.0,61.1] always3(s29) || -> . % 76.16/76.34 146688[87:SSi:146687.0,78196.0,78199.0,137751.0,146248.0,146678.0] || -> . % 76.16/76.34 146689[87:Spt:146688.0,146683.0,146685.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.34 146690[87:Spt:146688.0,146683.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 146694[87:Res:146690.0,61.1] always3(s30) || -> . % 76.16/76.34 146695[87:SSi:146694.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.34 146696[85:Spt:146695.0,146247.0,146248.0] || until2p7(s29)*+ -> . % 76.16/76.34 146697[85:Spt:146695.0,146247.1] || -> node4(s28)*. % 76.16/76.34 146699[85:MRR:834.0,146697.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.34 146702[85:Res:53.1,146699.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.34 146704[86:Spt:146702.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 146706[86:Res:146704.0,61.1] always3(s28) || -> . % 76.16/76.34 146707[86:SSi:146706.0,78191.0,78195.0,137750.0,146246.0,146697.0] || -> . % 76.16/76.34 146708[86:Spt:146707.0,146702.0,146704.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.34 146709[86:Spt:146707.0,146702.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 146713[86:Res:146709.0,61.1] always3(s29) || -> . % 76.16/76.34 146714[86:SSi:146713.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.34 146715[84:Spt:146714.0,146245.0,146246.0] || until2p7(s28)*+ -> . % 76.16/76.34 146716[84:Spt:146714.0,146245.1] || -> node4(s27)*. % 76.16/76.34 146718[84:MRR:837.0,146716.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.34 146721[84:Res:53.1,146718.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.34 146726[85:Spt:146721.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 146728[85:Res:146726.0,61.1] always3(s27) || -> . % 76.16/76.34 146729[85:SSi:146728.0,78187.0,78190.0,137749.0,146244.0,146716.0] || -> . % 76.16/76.34 146730[85:Spt:146729.0,146721.0,146726.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.34 146731[85:Spt:146729.0,146721.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 146735[85:Res:146731.0,61.1] always3(s28) || -> . % 76.16/76.34 146736[85:SSi:146735.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.34 146737[83:Spt:146736.0,146243.0,146244.0] || until2p7(s27)*+ -> . % 76.16/76.34 146738[83:Spt:146736.0,146243.1] || -> node4(s26)*. % 76.16/76.34 146740[83:MRR:840.0,146738.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.34 146743[83:Res:53.1,146740.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.34 146745[84:Spt:146743.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 146747[84:Res:146745.0,61.1] always3(s26) || -> . % 76.16/76.34 146748[84:SSi:146747.0,78182.0,78186.0,137748.0,146242.0,146738.0] || -> . % 76.16/76.34 146749[84:Spt:146748.0,146743.0,146745.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.34 146750[84:Spt:146748.0,146743.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 146754[84:Res:146750.0,61.1] always3(s27) || -> . % 76.16/76.34 146755[84:SSi:146754.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.34 146756[82:Spt:146755.0,146241.0,146242.0] || until2p7(s26)*+ -> . % 76.16/76.34 146757[82:Spt:146755.0,146241.1] || -> node4(s25)*. % 76.16/76.34 146759[82:MRR:843.0,146757.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.34 146762[82:Res:53.1,146759.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.34 146764[83:Spt:146762.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.34 146766[83:Res:146764.0,61.1] always3(s25) || -> . % 76.16/76.34 146767[83:SSi:146766.0,78178.0,78181.0,137747.0,146240.0,146757.0] || -> . % 76.16/76.34 146768[83:Spt:146767.0,146762.0,146764.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.34 146769[83:Spt:146767.0,146762.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 146773[83:Res:146769.0,61.1] always3(s26) || -> . % 76.16/76.34 146774[83:SSi:146773.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.34 146775[81:Spt:146774.0,146239.0,146240.0] || until2p7(s25)*+ -> . % 76.16/76.34 146776[81:Spt:146774.0,146239.1] || -> node4(s24)*. % 76.16/76.34 146778[81:MRR:846.0,146776.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.34 146781[81:Res:53.1,146778.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.34 146783[81:MRR:146781.0,146229.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.34 146785[81:Res:146783.0,61.1] always3(s25) || -> . % 76.16/76.34 146786[81:SSi:146785.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.34 146787[79:Spt:146786.0,146128.0,146131.0] || trans(s49,s24)*+ -> . % 76.16/76.34 146788[79:Spt:146786.0,146128.1,146128.2,146128.3,146128.4,146128.5,146128.6,146128.7,146128.8,146128.9,146128.10,146128.11,146128.12,146128.13,146128.14,146128.15,146128.16,146128.17,146128.18,146128.19,146128.20] || -> trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 146790[79:MRR:146130.1,146787.0] xuntil6(s49) || -> trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 146791[80:Spt:146788.0] || -> trans(s49,s23)*. % 76.16/76.34 146792[80:Res:146791.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s23)*. % 76.16/76.34 146794[80:Res:146791.0,60.0] || -> node2(s49,s23)*. % 76.16/76.34 146795[80:SSi:146792.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s23)*. % 76.16/76.34 146796[80:Res:146794.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)*. % 76.16/76.34 146885[80:SoR:146796.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)*. % 76.16/76.34 146887[80:SoR:146885.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)* xuntil6(s49). % 76.16/76.34 146888[80:SSi:146887.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s23,c_busy)* xuntil6(s49). % 76.16/76.34 146889[81:Spt:146888.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.34 146891[81:Res:146889.0,61.1] always3(s23) || -> . % 76.16/76.34 146892[81:SSi:146891.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.34 146893[81:Spt:146892.0,146888.1,146889.0] || m_main_v_state(s23,c_busy)*+ -> . % 76.16/76.34 146894[81:Spt:146892.0,146888.0,146888.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 146898[81:MRR:146885.2,146893.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 146899[81:Res:53.1,146894.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 146901[81:MRR:146899.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 146902[81:MRR:146795.0,146901.0] || -> until2p7(s23)*. % 76.16/76.34 146903[81:MRR:219.0,146902.0] || -> until2p7(s24)* node4(s23). % 76.16/76.34 146904[82:Spt:146903.0] || -> until2p7(s24)*. % 76.16/76.34 146905[82:MRR:220.0,146904.0] || -> until2p7(s25)* node4(s24). % 76.16/76.34 146906[83:Spt:146905.0] || -> until2p7(s25)*. % 76.16/76.34 146907[83:MRR:221.0,146906.0] || -> until2p7(s26)* node4(s25). % 76.16/76.34 146908[84:Spt:146907.0] || -> until2p7(s26)*. % 76.16/76.34 146909[84:MRR:222.0,146908.0] || -> until2p7(s27)* node4(s26). % 76.16/76.34 146910[85:Spt:146909.0] || -> until2p7(s27)*. % 76.16/76.34 146911[85:MRR:223.0,146910.0] || -> until2p7(s28)* node4(s27). % 76.16/76.34 146912[86:Spt:146911.0] || -> until2p7(s28)*. % 76.16/76.34 146913[86:MRR:224.0,146912.0] || -> until2p7(s29)* node4(s28). % 76.16/76.34 146914[87:Spt:146913.0] || -> until2p7(s29)*. % 76.16/76.34 146915[87:MRR:225.0,146914.0] || -> until2p7(s30)* node4(s29). % 76.16/76.34 146916[88:Spt:146915.0] || -> until2p7(s30)*. % 76.16/76.34 146917[88:MRR:226.0,146916.0] || -> until2p7(s31)* node4(s30). % 76.16/76.34 146918[89:Spt:146917.0] || -> until2p7(s31)*. % 76.16/76.34 146919[89:MRR:227.0,146918.0] || -> until2p7(s32)* node4(s31). % 76.16/76.34 146920[90:Spt:146919.0] || -> until2p7(s32)*. % 76.16/76.34 146921[90:MRR:228.0,146920.0] || -> until2p7(s33)* node4(s32). % 76.16/76.34 146922[91:Spt:146921.0] || -> until2p7(s33)*. % 76.16/76.34 146923[91:MRR:229.0,146922.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 146924[92:Spt:146923.0] || -> until2p7(s34)*. % 76.16/76.34 146925[92:MRR:230.0,146924.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 146926[93:Spt:146925.0] || -> until2p7(s35)*. % 76.16/76.34 146927[93:MRR:231.0,146926.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 146928[94:Spt:146927.0] || -> until2p7(s36)*. % 76.16/76.34 146929[94:MRR:232.0,146928.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 146930[95:Spt:146929.0] || -> until2p7(s37)*. % 76.16/76.34 146931[95:MRR:235.0,146930.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 146932[96:Spt:146931.0] || -> until2p7(s38)*. % 76.16/76.34 146933[96:MRR:236.0,146932.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 146934[97:Spt:146933.0] || -> until2p7(s39)*. % 76.16/76.34 146935[97:MRR:237.0,146934.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 146936[98:Spt:146935.0] || -> until2p7(s40)*. % 76.16/76.34 146937[98:MRR:238.0,146936.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 146938[99:Spt:146937.0] || -> until2p7(s41)*. % 76.16/76.34 146939[99:MRR:239.0,146938.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 146940[100:Spt:146939.0] || -> until2p7(s42)*. % 76.16/76.34 146941[100:MRR:240.0,146940.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 146942[101:Spt:146941.0] || -> until2p7(s43)*. % 76.16/76.34 146943[101:MRR:241.0,146942.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 146944[102:Spt:146943.0] || -> until2p7(s44)*. % 76.16/76.34 146945[102:MRR:539.0,146944.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 146946[103:Spt:146945.0] || -> until2p7(s45)*. % 76.16/76.34 146947[103:MRR:544.0,146946.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 146948[104:Spt:146947.0] || -> until2p7(s46)*. % 76.16/76.34 146949[104:MRR:549.0,146948.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 146950[105:Spt:146949.0] || -> until2p7(s47)*. % 76.16/76.34 146951[105:MRR:554.0,146950.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 146952[106:Spt:146951.0] || -> until2p7(s48)*. % 76.16/76.34 146953[106:MRR:559.0,146952.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 146954[107:Spt:146953.0] || -> until2p7(s49)*. % 76.16/76.34 146955[107:MRR:194.0,146954.0] || -> node4(s49)*. % 76.16/76.34 146956[107:MRR:146898.0,146955.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 146960[107:Res:53.1,146956.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 146962[107:MRR:146960.0,78381.0] || -> . % 76.16/76.34 146963[107:Spt:146962.0,146953.0,146954.0] || until2p7(s49)*+ -> . % 76.16/76.34 146964[107:Spt:146962.0,146953.1] || -> node4(s48)*. % 76.16/76.34 146965[107:MRR:78384.0,146964.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 146968[107:Res:53.1,146965.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 146971[107:Res:146968.0,61.1] always3(s48) || -> . % 76.16/76.34 146972[107:SSi:146971.0,78281.0,78387.0,137770.0,146952.0,146964.0] || -> . % 76.16/76.34 146973[106:Spt:146972.0,146951.0,146952.0] || until2p7(s48)*+ -> . % 76.16/76.34 146974[106:Spt:146972.0,146951.1] || -> node4(s47)*. % 76.16/76.34 146976[106:MRR:777.0,146974.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 146988[106:Res:53.1,146976.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 146990[107:Spt:146988.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 146992[107:Res:146990.0,61.1] always3(s47) || -> . % 76.16/76.34 146993[107:SSi:146992.0,78277.0,78280.0,137769.0,146950.0,146974.0] || -> . % 76.16/76.34 146994[107:Spt:146993.0,146988.0,146990.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 146995[107:Spt:146993.0,146988.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 146999[107:Res:146995.0,61.1] always3(s48) || -> . % 76.16/76.34 147000[107:SSi:146999.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 147001[105:Spt:147000.0,146949.0,146950.0] || until2p7(s47)*+ -> . % 76.16/76.34 147002[105:Spt:147000.0,146949.1] || -> node4(s46)*. % 76.16/76.34 147004[105:MRR:780.0,147002.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 147011[105:Res:53.1,147004.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 147016[106:Spt:147011.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 147018[106:Res:147016.0,61.1] always3(s46) || -> . % 76.16/76.34 147019[106:SSi:147018.0,78272.0,78276.0,137768.0,146948.0,147002.0] || -> . % 76.16/76.34 147020[106:Spt:147019.0,147011.0,147016.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 147021[106:Spt:147019.0,147011.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 147025[106:Res:147021.0,61.1] always3(s47) || -> . % 76.16/76.34 147026[106:SSi:147025.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 147027[104:Spt:147026.0,146947.0,146948.0] || until2p7(s46)*+ -> . % 76.16/76.34 147028[104:Spt:147026.0,146947.1] || -> node4(s45)*. % 76.16/76.34 147030[104:MRR:783.0,147028.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 147033[104:Res:53.1,147030.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 147035[105:Spt:147033.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 147037[105:Res:147035.0,61.1] always3(s45) || -> . % 76.16/76.34 147038[105:SSi:147037.0,78268.0,78271.0,137767.0,146946.0,147028.0] || -> . % 76.16/76.34 147039[105:Spt:147038.0,147033.0,147035.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 147040[105:Spt:147038.0,147033.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 147044[105:Res:147040.0,61.1] always3(s46) || -> . % 76.16/76.34 147045[105:SSi:147044.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 147046[103:Spt:147045.0,146945.0,146946.0] || until2p7(s45)*+ -> . % 76.16/76.34 147047[103:Spt:147045.0,146945.1] || -> node4(s44)*. % 76.16/76.34 147049[103:MRR:786.0,147047.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 147052[103:Res:53.1,147049.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 147054[104:Spt:147052.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 147056[104:Res:147054.0,61.1] always3(s44) || -> . % 76.16/76.34 147057[104:SSi:147056.0,78263.0,78267.0,137766.0,146944.0,147047.0] || -> . % 76.16/76.34 147058[104:Spt:147057.0,147052.0,147054.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 147059[104:Spt:147057.0,147052.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 147063[104:Res:147059.0,61.1] always3(s45) || -> . % 76.16/76.34 147064[104:SSi:147063.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 147065[102:Spt:147064.0,146943.0,146944.0] || until2p7(s44)*+ -> . % 76.16/76.34 147066[102:Spt:147064.0,146943.1] || -> node4(s43)*. % 76.16/76.34 147068[102:MRR:789.0,147066.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 147071[102:Res:53.1,147068.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 147073[103:Spt:147071.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 147075[103:Res:147073.0,61.1] always3(s43) || -> . % 76.16/76.34 147076[103:SSi:147075.0,78259.0,78262.0,137765.0,146942.0,147066.0] || -> . % 76.16/76.34 147077[103:Spt:147076.0,147071.0,147073.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 147078[103:Spt:147076.0,147071.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 147082[103:Res:147078.0,61.1] always3(s44) || -> . % 76.16/76.34 147083[103:SSi:147082.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 147084[101:Spt:147083.0,146941.0,146942.0] || until2p7(s43)*+ -> . % 76.16/76.34 147085[101:Spt:147083.0,146941.1] || -> node4(s42)*. % 76.16/76.34 147087[101:MRR:792.0,147085.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 147090[101:Res:53.1,147087.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 147095[102:Spt:147090.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 147097[102:Res:147095.0,61.1] always3(s42) || -> . % 76.16/76.34 147098[102:SSi:147097.0,78254.0,78258.0,137764.0,146940.0,147085.0] || -> . % 76.16/76.34 147099[102:Spt:147098.0,147090.0,147095.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 147100[102:Spt:147098.0,147090.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 147104[102:Res:147100.0,61.1] always3(s43) || -> . % 76.16/76.34 147105[102:SSi:147104.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 147106[100:Spt:147105.0,146939.0,146940.0] || until2p7(s42)*+ -> . % 76.16/76.34 147107[100:Spt:147105.0,146939.1] || -> node4(s41)*. % 76.16/76.34 147109[100:MRR:795.0,147107.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 147112[100:Res:53.1,147109.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 147114[101:Spt:147112.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 147116[101:Res:147114.0,61.1] always3(s41) || -> . % 76.16/76.34 147117[101:SSi:147116.0,78250.0,78253.0,137763.0,146938.0,147107.0] || -> . % 76.16/76.34 147118[101:Spt:147117.0,147112.0,147114.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 147119[101:Spt:147117.0,147112.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 147123[101:Res:147119.0,61.1] always3(s42) || -> . % 76.16/76.34 147124[101:SSi:147123.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 147125[99:Spt:147124.0,146937.0,146938.0] || until2p7(s41)*+ -> . % 76.16/76.34 147126[99:Spt:147124.0,146937.1] || -> node4(s40)*. % 76.16/76.34 147128[99:MRR:798.0,147126.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 147131[99:Res:53.1,147128.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 147133[100:Spt:147131.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 147135[100:Res:147133.0,61.1] always3(s40) || -> . % 76.16/76.34 147136[100:SSi:147135.0,78245.0,78249.0,137762.0,146936.0,147126.0] || -> . % 76.16/76.34 147137[100:Spt:147136.0,147131.0,147133.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 147138[100:Spt:147136.0,147131.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 147142[100:Res:147138.0,61.1] always3(s41) || -> . % 76.16/76.34 147143[100:SSi:147142.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 147144[98:Spt:147143.0,146935.0,146936.0] || until2p7(s40)*+ -> . % 76.16/76.34 147145[98:Spt:147143.0,146935.1] || -> node4(s39)*. % 76.16/76.34 147147[98:MRR:801.0,147145.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 147150[98:Res:53.1,147147.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 147152[99:Spt:147150.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 147154[99:Res:147152.0,61.1] always3(s39) || -> . % 76.16/76.34 147155[99:SSi:147154.0,78241.0,78244.0,137761.0,146934.0,147145.0] || -> . % 76.16/76.34 147156[99:Spt:147155.0,147150.0,147152.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 147157[99:Spt:147155.0,147150.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 147161[99:Res:147157.0,61.1] always3(s40) || -> . % 76.16/76.34 147162[99:SSi:147161.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 147163[97:Spt:147162.0,146933.0,146934.0] || until2p7(s39)*+ -> . % 76.16/76.34 147164[97:Spt:147162.0,146933.1] || -> node4(s38)*. % 76.16/76.34 147166[97:MRR:804.0,147164.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 147169[97:Res:53.1,147166.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 147174[98:Spt:147169.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 147176[98:Res:147174.0,61.1] always3(s38) || -> . % 76.16/76.34 147177[98:SSi:147176.0,78236.0,78240.0,137760.0,146932.0,147164.0] || -> . % 76.16/76.34 147178[98:Spt:147177.0,147169.0,147174.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 147179[98:Spt:147177.0,147169.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 147183[98:Res:147179.0,61.1] always3(s39) || -> . % 76.16/76.34 147184[98:SSi:147183.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 147185[96:Spt:147184.0,146931.0,146932.0] || until2p7(s38)*+ -> . % 76.16/76.34 147186[96:Spt:147184.0,146931.1] || -> node4(s37)*. % 76.16/76.34 147188[96:MRR:807.0,147186.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 147191[96:Res:53.1,147188.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 147193[97:Spt:147191.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 147195[97:Res:147193.0,61.1] always3(s37) || -> . % 76.16/76.34 147196[97:SSi:147195.0,78232.0,78235.0,137759.0,146930.0,147186.0] || -> . % 76.16/76.34 147197[97:Spt:147196.0,147191.0,147193.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 147198[97:Spt:147196.0,147191.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 147202[97:Res:147198.0,61.1] always3(s38) || -> . % 76.16/76.34 147203[97:SSi:147202.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 147204[95:Spt:147203.0,146929.0,146930.0] || until2p7(s37)*+ -> . % 76.16/76.34 147205[95:Spt:147203.0,146929.1] || -> node4(s36)*. % 76.16/76.34 147207[95:MRR:810.0,147205.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 147210[95:Res:53.1,147207.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 147212[96:Spt:147210.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 147214[96:Res:147212.0,61.1] always3(s36) || -> . % 76.16/76.34 147215[96:SSi:147214.0,78227.0,78231.0,137758.0,146928.0,147205.0] || -> . % 76.16/76.34 147216[96:Spt:147215.0,147210.0,147212.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 147217[96:Spt:147215.0,147210.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 147221[96:Res:147217.0,61.1] always3(s37) || -> . % 76.16/76.34 147222[96:SSi:147221.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 147223[94:Spt:147222.0,146927.0,146928.0] || until2p7(s36)*+ -> . % 76.16/76.34 147224[94:Spt:147222.0,146927.1] || -> node4(s35)*. % 76.16/76.34 147226[94:MRR:813.0,147224.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 147229[94:Res:53.1,147226.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 147231[95:Spt:147229.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 147233[95:Res:147231.0,61.1] always3(s35) || -> . % 76.16/76.34 147234[95:SSi:147233.0,78223.0,78226.0,137757.0,146926.0,147224.0] || -> . % 76.16/76.34 147235[95:Spt:147234.0,147229.0,147231.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 147236[95:Spt:147234.0,147229.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 147240[95:Res:147236.0,61.1] always3(s36) || -> . % 76.16/76.34 147241[95:SSi:147240.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 147242[93:Spt:147241.0,146925.0,146926.0] || until2p7(s35)*+ -> . % 76.16/76.34 147243[93:Spt:147241.0,146925.1] || -> node4(s34)*. % 76.16/76.34 147245[93:MRR:816.0,147243.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 147248[93:Res:53.1,147245.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 147253[94:Spt:147248.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 147255[94:Res:147253.0,61.1] always3(s34) || -> . % 76.16/76.34 147256[94:SSi:147255.0,78218.0,78222.0,137756.0,146924.0,147243.0] || -> . % 76.16/76.34 147257[94:Spt:147256.0,147248.0,147253.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 147258[94:Spt:147256.0,147248.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 147262[94:Res:147258.0,61.1] always3(s35) || -> . % 76.16/76.34 147263[94:SSi:147262.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 147264[92:Spt:147263.0,146923.0,146924.0] || until2p7(s34)*+ -> . % 76.16/76.34 147265[92:Spt:147263.0,146923.1] || -> node4(s33)*. % 76.16/76.34 147267[92:MRR:819.0,147265.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 147270[92:Res:53.1,147267.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 147272[93:Spt:147270.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 147274[93:Res:147272.0,61.1] always3(s33) || -> . % 76.16/76.34 147275[93:SSi:147274.0,78214.0,78217.0,137755.0,146922.0,147265.0] || -> . % 76.16/76.34 147276[93:Spt:147275.0,147270.0,147272.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.34 147277[93:Spt:147275.0,147270.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 147281[93:Res:147277.0,61.1] always3(s34) || -> . % 76.16/76.34 147282[93:SSi:147281.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 147283[91:Spt:147282.0,146921.0,146922.0] || until2p7(s33)*+ -> . % 76.16/76.34 147284[91:Spt:147282.0,146921.1] || -> node4(s32)*. % 76.16/76.34 147286[91:MRR:822.0,147284.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.34 147289[91:Res:53.1,147286.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.34 147291[92:Spt:147289.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 147293[92:Res:147291.0,61.1] always3(s32) || -> . % 76.16/76.34 147294[92:SSi:147293.0,78209.0,78213.0,137754.0,146920.0,147284.0] || -> . % 76.16/76.34 147295[92:Spt:147294.0,147289.0,147291.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.34 147296[92:Spt:147294.0,147289.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 147300[92:Res:147296.0,61.1] always3(s33) || -> . % 76.16/76.34 147301[92:SSi:147300.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 147302[90:Spt:147301.0,146919.0,146920.0] || until2p7(s32)*+ -> . % 76.16/76.34 147303[90:Spt:147301.0,146919.1] || -> node4(s31)*. % 76.16/76.34 147305[90:MRR:825.0,147303.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.34 147308[90:Res:53.1,147305.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.34 147310[91:Spt:147308.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 147312[91:Res:147310.0,61.1] always3(s31) || -> . % 76.16/76.34 147313[91:SSi:147312.0,78205.0,78208.0,137753.0,146918.0,147303.0] || -> . % 76.16/76.34 147314[91:Spt:147313.0,147308.0,147310.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.34 147315[91:Spt:147313.0,147308.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 147319[91:Res:147315.0,61.1] always3(s32) || -> . % 76.16/76.34 147320[91:SSi:147319.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.34 147321[89:Spt:147320.0,146917.0,146918.0] || until2p7(s31)*+ -> . % 76.16/76.34 147322[89:Spt:147320.0,146917.1] || -> node4(s30)*. % 76.16/76.34 147324[89:MRR:828.0,147322.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.34 147327[89:Res:53.1,147324.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.34 147332[90:Spt:147327.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 147334[90:Res:147332.0,61.1] always3(s30) || -> . % 76.16/76.34 147335[90:SSi:147334.0,78200.0,78204.0,137752.0,146916.0,147322.0] || -> . % 76.16/76.34 147336[90:Spt:147335.0,147327.0,147332.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.34 147337[90:Spt:147335.0,147327.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 147341[90:Res:147337.0,61.1] always3(s31) || -> . % 76.16/76.34 147342[90:SSi:147341.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.34 147343[88:Spt:147342.0,146915.0,146916.0] || until2p7(s30)*+ -> . % 76.16/76.34 147344[88:Spt:147342.0,146915.1] || -> node4(s29)*. % 76.16/76.34 147346[88:MRR:831.0,147344.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.34 147349[88:Res:53.1,147346.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.34 147351[89:Spt:147349.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 147353[89:Res:147351.0,61.1] always3(s29) || -> . % 76.16/76.34 147354[89:SSi:147353.0,78196.0,78199.0,137751.0,146914.0,147344.0] || -> . % 76.16/76.34 147355[89:Spt:147354.0,147349.0,147351.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.34 147356[89:Spt:147354.0,147349.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 147360[89:Res:147356.0,61.1] always3(s30) || -> . % 76.16/76.34 147361[89:SSi:147360.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.34 147362[87:Spt:147361.0,146913.0,146914.0] || until2p7(s29)*+ -> . % 76.16/76.34 147363[87:Spt:147361.0,146913.1] || -> node4(s28)*. % 76.16/76.34 147365[87:MRR:834.0,147363.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.34 147368[87:Res:53.1,147365.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.34 147370[88:Spt:147368.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 147372[88:Res:147370.0,61.1] always3(s28) || -> . % 76.16/76.34 147373[88:SSi:147372.0,78191.0,78195.0,137750.0,146912.0,147363.0] || -> . % 76.16/76.34 147374[88:Spt:147373.0,147368.0,147370.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.34 147375[88:Spt:147373.0,147368.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 147379[88:Res:147375.0,61.1] always3(s29) || -> . % 76.16/76.34 147380[88:SSi:147379.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.34 147381[86:Spt:147380.0,146911.0,146912.0] || until2p7(s28)*+ -> . % 76.16/76.34 147382[86:Spt:147380.0,146911.1] || -> node4(s27)*. % 76.16/76.34 147384[86:MRR:837.0,147382.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.34 147387[86:Res:53.1,147384.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.34 147389[87:Spt:147387.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 147391[87:Res:147389.0,61.1] always3(s27) || -> . % 76.16/76.34 147392[87:SSi:147391.0,78187.0,78190.0,137749.0,146910.0,147382.0] || -> . % 76.16/76.34 147393[87:Spt:147392.0,147387.0,147389.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.34 147394[87:Spt:147392.0,147387.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 147398[87:Res:147394.0,61.1] always3(s28) || -> . % 76.16/76.34 147399[87:SSi:147398.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.34 147400[85:Spt:147399.0,146909.0,146910.0] || until2p7(s27)*+ -> . % 76.16/76.34 147401[85:Spt:147399.0,146909.1] || -> node4(s26)*. % 76.16/76.34 147403[85:MRR:840.0,147401.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.34 147406[85:Res:53.1,147403.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.34 147411[86:Spt:147406.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 147413[86:Res:147411.0,61.1] always3(s26) || -> . % 76.16/76.34 147414[86:SSi:147413.0,78182.0,78186.0,137748.0,146908.0,147401.0] || -> . % 76.16/76.34 147415[86:Spt:147414.0,147406.0,147411.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.34 147416[86:Spt:147414.0,147406.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 147420[86:Res:147416.0,61.1] always3(s27) || -> . % 76.16/76.34 147421[86:SSi:147420.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.34 147422[84:Spt:147421.0,146907.0,146908.0] || until2p7(s26)*+ -> . % 76.16/76.34 147423[84:Spt:147421.0,146907.1] || -> node4(s25)*. % 76.16/76.34 147425[84:MRR:843.0,147423.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.34 147428[84:Res:53.1,147425.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.34 147430[85:Spt:147428.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.34 147432[85:Res:147430.0,61.1] always3(s25) || -> . % 76.16/76.34 147433[85:SSi:147432.0,78178.0,78181.0,137747.0,146906.0,147423.0] || -> . % 76.16/76.34 147434[85:Spt:147433.0,147428.0,147430.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.34 147435[85:Spt:147433.0,147428.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 147439[85:Res:147435.0,61.1] always3(s26) || -> . % 76.16/76.34 147440[85:SSi:147439.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.34 147441[83:Spt:147440.0,146905.0,146906.0] || until2p7(s25)*+ -> . % 76.16/76.34 147442[83:Spt:147440.0,146905.1] || -> node4(s24)*. % 76.16/76.34 147444[83:MRR:846.0,147442.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.34 147447[83:Res:53.1,147444.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.34 147449[84:Spt:147447.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.34 147451[84:Res:147449.0,61.1] always3(s24) || -> . % 76.16/76.34 147452[84:SSi:147451.0,78173.0,78177.0,137746.0,146904.0,147442.0] || -> . % 76.16/76.34 147453[84:Spt:147452.0,147447.0,147449.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.34 147454[84:Spt:147452.0,147447.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.34 147458[84:Res:147454.0,61.1] always3(s25) || -> . % 76.16/76.34 147459[84:SSi:147458.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.34 147460[82:Spt:147459.0,146903.0,146904.0] || until2p7(s24)*+ -> . % 76.16/76.34 147461[82:Spt:147459.0,146903.1] || -> node4(s23)*. % 76.16/76.34 147463[82:MRR:849.0,147461.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.34 147466[82:Res:53.1,147463.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.34 147468[82:MRR:147466.0,146893.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.34 147470[82:Res:147468.0,61.1] always3(s24) || -> . % 76.16/76.34 147471[82:SSi:147470.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.34 147472[80:Spt:147471.0,146788.0,146791.0] || trans(s49,s23)*+ -> . % 76.16/76.34 147473[80:Spt:147471.0,146788.1,146788.2,146788.3,146788.4,146788.5,146788.6,146788.7,146788.8,146788.9,146788.10,146788.11,146788.12,146788.13,146788.14,146788.15,146788.16,146788.17,146788.18,146788.19] || -> trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 147475[80:MRR:146790.1,147472.0] xuntil6(s49) || -> trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 147476[81:Spt:147473.0] || -> trans(s49,s22)*. % 76.16/76.34 147477[81:Res:147476.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s22)*. % 76.16/76.34 147479[81:Res:147476.0,60.0] || -> node2(s49,s22)*. % 76.16/76.34 147480[81:SSi:147477.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s22)*. % 76.16/76.34 147481[81:Res:147479.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)*. % 76.16/76.34 147574[81:SoR:147481.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)*. % 76.16/76.34 147576[81:SoR:147574.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)* xuntil6(s49). % 76.16/76.34 147577[81:SSi:147576.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s22,c_busy)* xuntil6(s49). % 76.16/76.34 147578[82:Spt:147577.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.34 147580[82:Res:147578.0,61.1] always3(s22) || -> . % 76.16/76.34 147581[82:SSi:147580.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.34 147582[82:Spt:147581.0,147577.1,147578.0] || m_main_v_state(s22,c_busy)*+ -> . % 76.16/76.34 147583[82:Spt:147581.0,147577.0,147577.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 147587[82:MRR:147574.2,147582.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 147588[82:Res:53.1,147583.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 147590[82:MRR:147588.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 147591[82:MRR:147480.0,147590.0] || -> until2p7(s22)*. % 76.16/76.34 147592[82:MRR:218.0,147591.0] || -> until2p7(s23)* node4(s22). % 76.16/76.34 147593[83:Spt:147592.0] || -> until2p7(s23)*. % 76.16/76.34 147594[83:MRR:219.0,147593.0] || -> until2p7(s24)* node4(s23). % 76.16/76.34 147595[84:Spt:147594.0] || -> until2p7(s24)*. % 76.16/76.34 147596[84:MRR:220.0,147595.0] || -> until2p7(s25)* node4(s24). % 76.16/76.34 147597[85:Spt:147596.0] || -> until2p7(s25)*. % 76.16/76.34 147598[85:MRR:221.0,147597.0] || -> until2p7(s26)* node4(s25). % 76.16/76.34 147599[86:Spt:147598.0] || -> until2p7(s26)*. % 76.16/76.34 147600[86:MRR:222.0,147599.0] || -> until2p7(s27)* node4(s26). % 76.16/76.34 147601[87:Spt:147600.0] || -> until2p7(s27)*. % 76.16/76.34 147602[87:MRR:223.0,147601.0] || -> until2p7(s28)* node4(s27). % 76.16/76.34 147603[88:Spt:147602.0] || -> until2p7(s28)*. % 76.16/76.34 147604[88:MRR:224.0,147603.0] || -> until2p7(s29)* node4(s28). % 76.16/76.34 147605[89:Spt:147604.0] || -> until2p7(s29)*. % 76.16/76.34 147606[89:MRR:225.0,147605.0] || -> until2p7(s30)* node4(s29). % 76.16/76.34 147607[90:Spt:147606.0] || -> until2p7(s30)*. % 76.16/76.34 147608[90:MRR:226.0,147607.0] || -> until2p7(s31)* node4(s30). % 76.16/76.34 147609[91:Spt:147608.0] || -> until2p7(s31)*. % 76.16/76.34 147610[91:MRR:227.0,147609.0] || -> until2p7(s32)* node4(s31). % 76.16/76.34 147611[92:Spt:147610.0] || -> until2p7(s32)*. % 76.16/76.34 147612[92:MRR:228.0,147611.0] || -> until2p7(s33)* node4(s32). % 76.16/76.34 147613[93:Spt:147612.0] || -> until2p7(s33)*. % 76.16/76.34 147614[93:MRR:229.0,147613.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 147615[94:Spt:147614.0] || -> until2p7(s34)*. % 76.16/76.34 147616[94:MRR:230.0,147615.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 147617[95:Spt:147616.0] || -> until2p7(s35)*. % 76.16/76.34 147618[95:MRR:231.0,147617.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 147619[96:Spt:147618.0] || -> until2p7(s36)*. % 76.16/76.34 147620[96:MRR:232.0,147619.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 147621[97:Spt:147620.0] || -> until2p7(s37)*. % 76.16/76.34 147622[97:MRR:235.0,147621.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 147623[98:Spt:147622.0] || -> until2p7(s38)*. % 76.16/76.34 147624[98:MRR:236.0,147623.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 147625[99:Spt:147624.0] || -> until2p7(s39)*. % 76.16/76.34 147626[99:MRR:237.0,147625.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 147627[100:Spt:147626.0] || -> until2p7(s40)*. % 76.16/76.34 147628[100:MRR:238.0,147627.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 147629[101:Spt:147628.0] || -> until2p7(s41)*. % 76.16/76.34 147630[101:MRR:239.0,147629.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 147631[102:Spt:147630.0] || -> until2p7(s42)*. % 76.16/76.34 147632[102:MRR:240.0,147631.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 147633[103:Spt:147632.0] || -> until2p7(s43)*. % 76.16/76.34 147634[103:MRR:241.0,147633.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 147635[104:Spt:147634.0] || -> until2p7(s44)*. % 76.16/76.34 147636[104:MRR:539.0,147635.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 147637[105:Spt:147636.0] || -> until2p7(s45)*. % 76.16/76.34 147638[105:MRR:544.0,147637.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 147639[106:Spt:147638.0] || -> until2p7(s46)*. % 76.16/76.34 147640[106:MRR:549.0,147639.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 147641[107:Spt:147640.0] || -> until2p7(s47)*. % 76.16/76.34 147642[107:MRR:554.0,147641.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 147643[108:Spt:147642.0] || -> until2p7(s48)*. % 76.16/76.34 147644[108:MRR:559.0,147643.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 147645[109:Spt:147644.0] || -> until2p7(s49)*. % 76.16/76.34 147646[109:MRR:194.0,147645.0] || -> node4(s49)*. % 76.16/76.34 147647[109:MRR:147587.0,147646.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 147648[109:Res:53.1,147647.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 147650[109:MRR:147648.0,78381.0] || -> . % 76.16/76.34 147651[109:Spt:147650.0,147644.0,147645.0] || until2p7(s49)*+ -> . % 76.16/76.34 147652[109:Spt:147650.0,147644.1] || -> node4(s48)*. % 76.16/76.34 147653[109:MRR:78384.0,147652.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 147656[109:Res:53.1,147653.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 147659[109:Res:147656.0,61.1] always3(s48) || -> . % 76.16/76.34 147660[109:SSi:147659.0,78281.0,78387.0,137770.0,147643.0,147652.0] || -> . % 76.16/76.34 147661[108:Spt:147660.0,147642.0,147643.0] || until2p7(s48)*+ -> . % 76.16/76.34 147662[108:Spt:147660.0,147642.1] || -> node4(s47)*. % 76.16/76.34 147664[108:MRR:777.0,147662.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 147679[108:Res:53.1,147664.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 147684[109:Spt:147679.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 147686[109:Res:147684.0,61.1] always3(s47) || -> . % 76.16/76.34 147687[109:SSi:147686.0,78277.0,78280.0,137769.0,147641.0,147662.0] || -> . % 76.16/76.34 147688[109:Spt:147687.0,147679.0,147684.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 147689[109:Spt:147687.0,147679.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 147693[109:Res:147689.0,61.1] always3(s48) || -> . % 76.16/76.34 147694[109:SSi:147693.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 147695[107:Spt:147694.0,147640.0,147641.0] || until2p7(s47)*+ -> . % 76.16/76.34 147696[107:Spt:147694.0,147640.1] || -> node4(s46)*. % 76.16/76.34 147698[107:MRR:780.0,147696.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 147705[107:Res:53.1,147698.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 147707[108:Spt:147705.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 147709[108:Res:147707.0,61.1] always3(s46) || -> . % 76.16/76.34 147710[108:SSi:147709.0,78272.0,78276.0,137768.0,147639.0,147696.0] || -> . % 76.16/76.34 147711[108:Spt:147710.0,147705.0,147707.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 147712[108:Spt:147710.0,147705.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 147716[108:Res:147712.0,61.1] always3(s47) || -> . % 76.16/76.34 147717[108:SSi:147716.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 147718[106:Spt:147717.0,147638.0,147639.0] || until2p7(s46)*+ -> . % 76.16/76.34 147719[106:Spt:147717.0,147638.1] || -> node4(s45)*. % 76.16/76.34 147721[106:MRR:783.0,147719.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 147724[106:Res:53.1,147721.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 147729[107:Spt:147724.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 147731[107:Res:147729.0,61.1] always3(s45) || -> . % 76.16/76.34 147732[107:SSi:147731.0,78268.0,78271.0,137767.0,147637.0,147719.0] || -> . % 76.16/76.34 147733[107:Spt:147732.0,147724.0,147729.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 147734[107:Spt:147732.0,147724.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 147738[107:Res:147734.0,61.1] always3(s46) || -> . % 76.16/76.34 147739[107:SSi:147738.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 147740[105:Spt:147739.0,147636.0,147637.0] || until2p7(s45)*+ -> . % 76.16/76.34 147741[105:Spt:147739.0,147636.1] || -> node4(s44)*. % 76.16/76.34 147743[105:MRR:786.0,147741.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 147746[105:Res:53.1,147743.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 147748[106:Spt:147746.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 147750[106:Res:147748.0,61.1] always3(s44) || -> . % 76.16/76.34 147751[106:SSi:147750.0,78263.0,78267.0,137766.0,147635.0,147741.0] || -> . % 76.16/76.34 147752[106:Spt:147751.0,147746.0,147748.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 147753[106:Spt:147751.0,147746.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 147757[106:Res:147753.0,61.1] always3(s45) || -> . % 76.16/76.34 147758[106:SSi:147757.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 147759[104:Spt:147758.0,147634.0,147635.0] || until2p7(s44)*+ -> . % 76.16/76.34 147760[104:Spt:147758.0,147634.1] || -> node4(s43)*. % 76.16/76.34 147762[104:MRR:789.0,147760.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 147765[104:Res:53.1,147762.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 147767[105:Spt:147765.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 147769[105:Res:147767.0,61.1] always3(s43) || -> . % 76.16/76.34 147770[105:SSi:147769.0,78259.0,78262.0,137765.0,147633.0,147760.0] || -> . % 76.16/76.34 147771[105:Spt:147770.0,147765.0,147767.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 147772[105:Spt:147770.0,147765.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 147776[105:Res:147772.0,61.1] always3(s44) || -> . % 76.16/76.34 147777[105:SSi:147776.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 147778[103:Spt:147777.0,147632.0,147633.0] || until2p7(s43)*+ -> . % 76.16/76.34 147779[103:Spt:147777.0,147632.1] || -> node4(s42)*. % 76.16/76.34 147781[103:MRR:792.0,147779.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 147784[103:Res:53.1,147781.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 147786[104:Spt:147784.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 147788[104:Res:147786.0,61.1] always3(s42) || -> . % 76.16/76.34 147789[104:SSi:147788.0,78254.0,78258.0,137764.0,147631.0,147779.0] || -> . % 76.16/76.34 147790[104:Spt:147789.0,147784.0,147786.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 147791[104:Spt:147789.0,147784.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 147795[104:Res:147791.0,61.1] always3(s43) || -> . % 76.16/76.34 147796[104:SSi:147795.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 147797[102:Spt:147796.0,147630.0,147631.0] || until2p7(s42)*+ -> . % 76.16/76.34 147798[102:Spt:147796.0,147630.1] || -> node4(s41)*. % 76.16/76.34 147800[102:MRR:795.0,147798.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 147803[102:Res:53.1,147800.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 147808[103:Spt:147803.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 147810[103:Res:147808.0,61.1] always3(s41) || -> . % 76.16/76.34 147811[103:SSi:147810.0,78250.0,78253.0,137763.0,147629.0,147798.0] || -> . % 76.16/76.34 147812[103:Spt:147811.0,147803.0,147808.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 147813[103:Spt:147811.0,147803.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 147817[103:Res:147813.0,61.1] always3(s42) || -> . % 76.16/76.34 147818[103:SSi:147817.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 147819[101:Spt:147818.0,147628.0,147629.0] || until2p7(s41)*+ -> . % 76.16/76.34 147820[101:Spt:147818.0,147628.1] || -> node4(s40)*. % 76.16/76.34 147822[101:MRR:798.0,147820.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 147825[101:Res:53.1,147822.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 147827[102:Spt:147825.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 147829[102:Res:147827.0,61.1] always3(s40) || -> . % 76.16/76.34 147830[102:SSi:147829.0,78245.0,78249.0,137762.0,147627.0,147820.0] || -> . % 76.16/76.34 147831[102:Spt:147830.0,147825.0,147827.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 147832[102:Spt:147830.0,147825.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 147836[102:Res:147832.0,61.1] always3(s41) || -> . % 76.16/76.34 147837[102:SSi:147836.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 147838[100:Spt:147837.0,147626.0,147627.0] || until2p7(s40)*+ -> . % 76.16/76.34 147839[100:Spt:147837.0,147626.1] || -> node4(s39)*. % 76.16/76.34 147841[100:MRR:801.0,147839.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 147844[100:Res:53.1,147841.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 147846[101:Spt:147844.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 147848[101:Res:147846.0,61.1] always3(s39) || -> . % 76.16/76.34 147849[101:SSi:147848.0,78241.0,78244.0,137761.0,147625.0,147839.0] || -> . % 76.16/76.34 147850[101:Spt:147849.0,147844.0,147846.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 147851[101:Spt:147849.0,147844.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 147855[101:Res:147851.0,61.1] always3(s40) || -> . % 76.16/76.34 147856[101:SSi:147855.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 147857[99:Spt:147856.0,147624.0,147625.0] || until2p7(s39)*+ -> . % 76.16/76.34 147858[99:Spt:147856.0,147624.1] || -> node4(s38)*. % 76.16/76.34 147860[99:MRR:804.0,147858.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 147863[99:Res:53.1,147860.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 147865[100:Spt:147863.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 147867[100:Res:147865.0,61.1] always3(s38) || -> . % 76.16/76.34 147868[100:SSi:147867.0,78236.0,78240.0,137760.0,147623.0,147858.0] || -> . % 76.16/76.34 147869[100:Spt:147868.0,147863.0,147865.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 147870[100:Spt:147868.0,147863.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 147874[100:Res:147870.0,61.1] always3(s39) || -> . % 76.16/76.34 147875[100:SSi:147874.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 147876[98:Spt:147875.0,147622.0,147623.0] || until2p7(s38)*+ -> . % 76.16/76.34 147877[98:Spt:147875.0,147622.1] || -> node4(s37)*. % 76.16/76.34 147879[98:MRR:807.0,147877.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 147882[98:Res:53.1,147879.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 147887[99:Spt:147882.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 147889[99:Res:147887.0,61.1] always3(s37) || -> . % 76.16/76.34 147890[99:SSi:147889.0,78232.0,78235.0,137759.0,147621.0,147877.0] || -> . % 76.16/76.34 147891[99:Spt:147890.0,147882.0,147887.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 147892[99:Spt:147890.0,147882.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 147896[99:Res:147892.0,61.1] always3(s38) || -> . % 76.16/76.34 147897[99:SSi:147896.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 147898[97:Spt:147897.0,147620.0,147621.0] || until2p7(s37)*+ -> . % 76.16/76.34 147899[97:Spt:147897.0,147620.1] || -> node4(s36)*. % 76.16/76.34 147901[97:MRR:810.0,147899.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 147904[97:Res:53.1,147901.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 147906[98:Spt:147904.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 147908[98:Res:147906.0,61.1] always3(s36) || -> . % 76.16/76.34 147909[98:SSi:147908.0,78227.0,78231.0,137758.0,147619.0,147899.0] || -> . % 76.16/76.34 147910[98:Spt:147909.0,147904.0,147906.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 147911[98:Spt:147909.0,147904.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 147915[98:Res:147911.0,61.1] always3(s37) || -> . % 76.16/76.34 147916[98:SSi:147915.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 147917[96:Spt:147916.0,147618.0,147619.0] || until2p7(s36)*+ -> . % 76.16/76.34 147918[96:Spt:147916.0,147618.1] || -> node4(s35)*. % 76.16/76.34 147920[96:MRR:813.0,147918.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 147923[96:Res:53.1,147920.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 147925[97:Spt:147923.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 147927[97:Res:147925.0,61.1] always3(s35) || -> . % 76.16/76.34 147928[97:SSi:147927.0,78223.0,78226.0,137757.0,147617.0,147918.0] || -> . % 76.16/76.34 147929[97:Spt:147928.0,147923.0,147925.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 147930[97:Spt:147928.0,147923.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 147934[97:Res:147930.0,61.1] always3(s36) || -> . % 76.16/76.34 147935[97:SSi:147934.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 147936[95:Spt:147935.0,147616.0,147617.0] || until2p7(s35)*+ -> . % 76.16/76.34 147937[95:Spt:147935.0,147616.1] || -> node4(s34)*. % 76.16/76.34 147939[95:MRR:816.0,147937.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 147942[95:Res:53.1,147939.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 147944[96:Spt:147942.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 147946[96:Res:147944.0,61.1] always3(s34) || -> . % 76.16/76.34 147947[96:SSi:147946.0,78218.0,78222.0,137756.0,147615.0,147937.0] || -> . % 76.16/76.34 147948[96:Spt:147947.0,147942.0,147944.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 147949[96:Spt:147947.0,147942.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 147953[96:Res:147949.0,61.1] always3(s35) || -> . % 76.16/76.34 147954[96:SSi:147953.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 147955[94:Spt:147954.0,147614.0,147615.0] || until2p7(s34)*+ -> . % 76.16/76.34 147956[94:Spt:147954.0,147614.1] || -> node4(s33)*. % 76.16/76.34 147958[94:MRR:819.0,147956.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 147961[94:Res:53.1,147958.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 147966[95:Spt:147961.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 147968[95:Res:147966.0,61.1] always3(s33) || -> . % 76.16/76.34 147969[95:SSi:147968.0,78214.0,78217.0,137755.0,147613.0,147956.0] || -> . % 76.16/76.34 147970[95:Spt:147969.0,147961.0,147966.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.34 147971[95:Spt:147969.0,147961.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 147975[95:Res:147971.0,61.1] always3(s34) || -> . % 76.16/76.34 147976[95:SSi:147975.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 147977[93:Spt:147976.0,147612.0,147613.0] || until2p7(s33)*+ -> . % 76.16/76.34 147978[93:Spt:147976.0,147612.1] || -> node4(s32)*. % 76.16/76.34 147980[93:MRR:822.0,147978.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.34 147983[93:Res:53.1,147980.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.34 147985[94:Spt:147983.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 147987[94:Res:147985.0,61.1] always3(s32) || -> . % 76.16/76.34 147988[94:SSi:147987.0,78209.0,78213.0,137754.0,147611.0,147978.0] || -> . % 76.16/76.34 147989[94:Spt:147988.0,147983.0,147985.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.34 147990[94:Spt:147988.0,147983.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 147994[94:Res:147990.0,61.1] always3(s33) || -> . % 76.16/76.34 147995[94:SSi:147994.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 147996[92:Spt:147995.0,147610.0,147611.0] || until2p7(s32)*+ -> . % 76.16/76.34 147997[92:Spt:147995.0,147610.1] || -> node4(s31)*. % 76.16/76.34 147999[92:MRR:825.0,147997.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.34 148002[92:Res:53.1,147999.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.34 148004[93:Spt:148002.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 148006[93:Res:148004.0,61.1] always3(s31) || -> . % 76.16/76.34 148007[93:SSi:148006.0,78205.0,78208.0,137753.0,147609.0,147997.0] || -> . % 76.16/76.34 148008[93:Spt:148007.0,148002.0,148004.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.34 148009[93:Spt:148007.0,148002.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 148013[93:Res:148009.0,61.1] always3(s32) || -> . % 76.16/76.34 148014[93:SSi:148013.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.34 148015[91:Spt:148014.0,147608.0,147609.0] || until2p7(s31)*+ -> . % 76.16/76.34 148016[91:Spt:148014.0,147608.1] || -> node4(s30)*. % 76.16/76.34 148018[91:MRR:828.0,148016.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.34 148021[91:Res:53.1,148018.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.34 148023[92:Spt:148021.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 148025[92:Res:148023.0,61.1] always3(s30) || -> . % 76.16/76.34 148026[92:SSi:148025.0,78200.0,78204.0,137752.0,147607.0,148016.0] || -> . % 76.16/76.34 148027[92:Spt:148026.0,148021.0,148023.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.34 148028[92:Spt:148026.0,148021.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 148032[92:Res:148028.0,61.1] always3(s31) || -> . % 76.16/76.34 148033[92:SSi:148032.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.34 148034[90:Spt:148033.0,147606.0,147607.0] || until2p7(s30)*+ -> . % 76.16/76.34 148035[90:Spt:148033.0,147606.1] || -> node4(s29)*. % 76.16/76.34 148037[90:MRR:831.0,148035.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.34 148040[90:Res:53.1,148037.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.34 148045[91:Spt:148040.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 148047[91:Res:148045.0,61.1] always3(s29) || -> . % 76.16/76.34 148048[91:SSi:148047.0,78196.0,78199.0,137751.0,147605.0,148035.0] || -> . % 76.16/76.34 148049[91:Spt:148048.0,148040.0,148045.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.34 148050[91:Spt:148048.0,148040.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 148054[91:Res:148050.0,61.1] always3(s30) || -> . % 76.16/76.34 148055[91:SSi:148054.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.34 148056[89:Spt:148055.0,147604.0,147605.0] || until2p7(s29)*+ -> . % 76.16/76.34 148057[89:Spt:148055.0,147604.1] || -> node4(s28)*. % 76.16/76.34 148059[89:MRR:834.0,148057.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.34 148062[89:Res:53.1,148059.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.34 148064[90:Spt:148062.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 148066[90:Res:148064.0,61.1] always3(s28) || -> . % 76.16/76.34 148067[90:SSi:148066.0,78191.0,78195.0,137750.0,147603.0,148057.0] || -> . % 76.16/76.34 148068[90:Spt:148067.0,148062.0,148064.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.34 148069[90:Spt:148067.0,148062.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 148073[90:Res:148069.0,61.1] always3(s29) || -> . % 76.16/76.34 148074[90:SSi:148073.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.34 148075[88:Spt:148074.0,147602.0,147603.0] || until2p7(s28)*+ -> . % 76.16/76.34 148076[88:Spt:148074.0,147602.1] || -> node4(s27)*. % 76.16/76.34 148078[88:MRR:837.0,148076.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.34 148081[88:Res:53.1,148078.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.34 148083[89:Spt:148081.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 148085[89:Res:148083.0,61.1] always3(s27) || -> . % 76.16/76.34 148086[89:SSi:148085.0,78187.0,78190.0,137749.0,147601.0,148076.0] || -> . % 76.16/76.34 148087[89:Spt:148086.0,148081.0,148083.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.34 148088[89:Spt:148086.0,148081.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 148092[89:Res:148088.0,61.1] always3(s28) || -> . % 76.16/76.34 148093[89:SSi:148092.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.34 148094[87:Spt:148093.0,147600.0,147601.0] || until2p7(s27)*+ -> . % 76.16/76.34 148095[87:Spt:148093.0,147600.1] || -> node4(s26)*. % 76.16/76.34 148097[87:MRR:840.0,148095.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.34 148100[87:Res:53.1,148097.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.34 148102[88:Spt:148100.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 148104[88:Res:148102.0,61.1] always3(s26) || -> . % 76.16/76.34 148105[88:SSi:148104.0,78182.0,78186.0,137748.0,147599.0,148095.0] || -> . % 76.16/76.34 148106[88:Spt:148105.0,148100.0,148102.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.34 148107[88:Spt:148105.0,148100.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 148111[88:Res:148107.0,61.1] always3(s27) || -> . % 76.16/76.34 148112[88:SSi:148111.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.34 148113[86:Spt:148112.0,147598.0,147599.0] || until2p7(s26)*+ -> . % 76.16/76.34 148114[86:Spt:148112.0,147598.1] || -> node4(s25)*. % 76.16/76.34 148116[86:MRR:843.0,148114.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.34 148119[86:Res:53.1,148116.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.34 148124[87:Spt:148119.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.34 148126[87:Res:148124.0,61.1] always3(s25) || -> . % 76.16/76.34 148127[87:SSi:148126.0,78178.0,78181.0,137747.0,147597.0,148114.0] || -> . % 76.16/76.34 148128[87:Spt:148127.0,148119.0,148124.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.34 148129[87:Spt:148127.0,148119.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 148133[87:Res:148129.0,61.1] always3(s26) || -> . % 76.16/76.34 148134[87:SSi:148133.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.34 148135[85:Spt:148134.0,147596.0,147597.0] || until2p7(s25)*+ -> . % 76.16/76.34 148136[85:Spt:148134.0,147596.1] || -> node4(s24)*. % 76.16/76.34 148138[85:MRR:846.0,148136.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.34 148141[85:Res:53.1,148138.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.34 148143[86:Spt:148141.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.34 148145[86:Res:148143.0,61.1] always3(s24) || -> . % 76.16/76.34 148146[86:SSi:148145.0,78173.0,78177.0,137746.0,147595.0,148136.0] || -> . % 76.16/76.34 148147[86:Spt:148146.0,148141.0,148143.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.34 148148[86:Spt:148146.0,148141.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.34 148152[86:Res:148148.0,61.1] always3(s25) || -> . % 76.16/76.34 148153[86:SSi:148152.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.34 148154[84:Spt:148153.0,147594.0,147595.0] || until2p7(s24)*+ -> . % 76.16/76.34 148155[84:Spt:148153.0,147594.1] || -> node4(s23)*. % 76.16/76.34 148157[84:MRR:849.0,148155.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.34 148160[84:Res:53.1,148157.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.34 148162[85:Spt:148160.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.34 148164[85:Res:148162.0,61.1] always3(s23) || -> . % 76.16/76.34 148165[85:SSi:148164.0,78169.0,78172.0,137745.0,147593.0,148155.0] || -> . % 76.16/76.34 148166[85:Spt:148165.0,148160.0,148162.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.34 148167[85:Spt:148165.0,148160.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.34 148171[85:Res:148167.0,61.1] always3(s24) || -> . % 76.16/76.34 148172[85:SSi:148171.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.34 148173[83:Spt:148172.0,147592.0,147593.0] || until2p7(s23)*+ -> . % 76.16/76.34 148174[83:Spt:148172.0,147592.1] || -> node4(s22)*. % 76.16/76.34 148176[83:MRR:852.0,148174.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.34 148179[83:Res:53.1,148176.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.34 148181[83:MRR:148179.0,147582.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.34 148183[83:Res:148181.0,61.1] always3(s23) || -> . % 76.16/76.34 148184[83:SSi:148183.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.34 148185[81:Spt:148184.0,147473.0,147476.0] || trans(s49,s22)*+ -> . % 76.16/76.34 148186[81:Spt:148184.0,147473.1,147473.2,147473.3,147473.4,147473.5,147473.6,147473.7,147473.8,147473.9,147473.10,147473.11,147473.12,147473.13,147473.14,147473.15,147473.16,147473.17,147473.18] || -> trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 148188[81:MRR:147475.1,148185.0] xuntil6(s49) || -> trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 148189[82:Spt:148186.0] || -> trans(s49,s21)*. % 76.16/76.34 148190[82:Res:148189.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s21)*. % 76.16/76.34 148192[82:Res:148189.0,60.0] || -> node2(s49,s21)*. % 76.16/76.34 148193[82:SSi:148190.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s21)*. % 76.16/76.34 148194[82:Res:148192.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)*. % 76.16/76.34 148288[82:SoR:148194.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)*. % 76.16/76.34 148290[82:SoR:148288.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)* xuntil6(s49). % 76.16/76.34 148291[82:SSi:148290.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s21,c_busy)* xuntil6(s49). % 76.16/76.34 148292[83:Spt:148291.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.34 148294[83:Res:148292.0,61.1] always3(s21) || -> . % 76.16/76.34 148295[83:SSi:148294.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.34 148296[83:Spt:148295.0,148291.1,148292.0] || m_main_v_state(s21,c_busy)*+ -> . % 76.16/76.34 148297[83:Spt:148295.0,148291.0,148291.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 148301[83:MRR:148288.2,148296.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 148302[83:Res:53.1,148297.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 148304[83:MRR:148302.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 148305[83:MRR:148193.0,148304.0] || -> until2p7(s21)*. % 76.16/76.34 148306[83:MRR:217.0,148305.0] || -> until2p7(s22)* node4(s21). % 76.16/76.34 148307[84:Spt:148306.0] || -> until2p7(s22)*. % 76.16/76.34 148308[84:MRR:218.0,148307.0] || -> until2p7(s23)* node4(s22). % 76.16/76.34 148309[85:Spt:148308.0] || -> until2p7(s23)*. % 76.16/76.34 148310[85:MRR:219.0,148309.0] || -> until2p7(s24)* node4(s23). % 76.16/76.34 148311[86:Spt:148310.0] || -> until2p7(s24)*. % 76.16/76.34 148312[86:MRR:220.0,148311.0] || -> until2p7(s25)* node4(s24). % 76.16/76.34 148313[87:Spt:148312.0] || -> until2p7(s25)*. % 76.16/76.34 148314[87:MRR:221.0,148313.0] || -> until2p7(s26)* node4(s25). % 76.16/76.34 148315[88:Spt:148314.0] || -> until2p7(s26)*. % 76.16/76.34 148316[88:MRR:222.0,148315.0] || -> until2p7(s27)* node4(s26). % 76.16/76.34 148317[89:Spt:148316.0] || -> until2p7(s27)*. % 76.16/76.34 148318[89:MRR:223.0,148317.0] || -> until2p7(s28)* node4(s27). % 76.16/76.34 148319[90:Spt:148318.0] || -> until2p7(s28)*. % 76.16/76.34 148320[90:MRR:224.0,148319.0] || -> until2p7(s29)* node4(s28). % 76.16/76.34 148321[91:Spt:148320.0] || -> until2p7(s29)*. % 76.16/76.34 148322[91:MRR:225.0,148321.0] || -> until2p7(s30)* node4(s29). % 76.16/76.34 148323[92:Spt:148322.0] || -> until2p7(s30)*. % 76.16/76.34 148324[92:MRR:226.0,148323.0] || -> until2p7(s31)* node4(s30). % 76.16/76.34 148325[93:Spt:148324.0] || -> until2p7(s31)*. % 76.16/76.34 148326[93:MRR:227.0,148325.0] || -> until2p7(s32)* node4(s31). % 76.16/76.34 148327[94:Spt:148326.0] || -> until2p7(s32)*. % 76.16/76.34 148328[94:MRR:228.0,148327.0] || -> until2p7(s33)* node4(s32). % 76.16/76.34 148329[95:Spt:148328.0] || -> until2p7(s33)*. % 76.16/76.34 148330[95:MRR:229.0,148329.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 148331[96:Spt:148330.0] || -> until2p7(s34)*. % 76.16/76.34 148332[96:MRR:230.0,148331.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 148333[97:Spt:148332.0] || -> until2p7(s35)*. % 76.16/76.34 148334[97:MRR:231.0,148333.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 148335[98:Spt:148334.0] || -> until2p7(s36)*. % 76.16/76.34 148336[98:MRR:232.0,148335.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 148337[99:Spt:148336.0] || -> until2p7(s37)*. % 76.16/76.34 148338[99:MRR:235.0,148337.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 148339[100:Spt:148338.0] || -> until2p7(s38)*. % 76.16/76.34 148340[100:MRR:236.0,148339.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 148341[101:Spt:148340.0] || -> until2p7(s39)*. % 76.16/76.34 148342[101:MRR:237.0,148341.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 148343[102:Spt:148342.0] || -> until2p7(s40)*. % 76.16/76.34 148344[102:MRR:238.0,148343.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 148345[103:Spt:148344.0] || -> until2p7(s41)*. % 76.16/76.34 148346[103:MRR:239.0,148345.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 148347[104:Spt:148346.0] || -> until2p7(s42)*. % 76.16/76.34 148348[104:MRR:240.0,148347.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 148349[105:Spt:148348.0] || -> until2p7(s43)*. % 76.16/76.34 148350[105:MRR:241.0,148349.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 148351[106:Spt:148350.0] || -> until2p7(s44)*. % 76.16/76.34 148352[106:MRR:539.0,148351.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 148353[107:Spt:148352.0] || -> until2p7(s45)*. % 76.16/76.34 148354[107:MRR:544.0,148353.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 148355[108:Spt:148354.0] || -> until2p7(s46)*. % 76.16/76.34 148356[108:MRR:549.0,148355.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 148357[109:Spt:148356.0] || -> until2p7(s47)*. % 76.16/76.34 148358[109:MRR:554.0,148357.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 148359[110:Spt:148358.0] || -> until2p7(s48)*. % 76.16/76.34 148360[110:MRR:559.0,148359.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 148361[111:Spt:148360.0] || -> until2p7(s49)*. % 76.16/76.34 148362[111:MRR:194.0,148361.0] || -> node4(s49)*. % 76.16/76.34 148363[111:MRR:148301.0,148362.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 148367[111:Res:53.1,148363.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 148369[111:MRR:148367.0,78381.0] || -> . % 76.16/76.34 148370[111:Spt:148369.0,148360.0,148361.0] || until2p7(s49)*+ -> . % 76.16/76.34 148371[111:Spt:148369.0,148360.1] || -> node4(s48)*. % 76.16/76.34 148372[111:MRR:78384.0,148371.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 148375[111:Res:53.1,148372.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 148378[111:Res:148375.0,61.1] always3(s48) || -> . % 76.16/76.34 148379[111:SSi:148378.0,78281.0,78387.0,137770.0,148359.0,148371.0] || -> . % 76.16/76.34 148380[110:Spt:148379.0,148358.0,148359.0] || until2p7(s48)*+ -> . % 76.16/76.34 148381[110:Spt:148379.0,148358.1] || -> node4(s47)*. % 76.16/76.34 148383[110:MRR:777.0,148381.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 148395[110:Res:53.1,148383.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 148397[111:Spt:148395.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 148399[111:Res:148397.0,61.1] always3(s47) || -> . % 76.16/76.34 148400[111:SSi:148399.0,78277.0,78280.0,137769.0,148357.0,148381.0] || -> . % 76.16/76.34 148401[111:Spt:148400.0,148395.0,148397.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 148402[111:Spt:148400.0,148395.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 148406[111:Res:148402.0,61.1] always3(s48) || -> . % 76.16/76.34 148407[111:SSi:148406.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 148408[109:Spt:148407.0,148356.0,148357.0] || until2p7(s47)*+ -> . % 76.16/76.34 148409[109:Spt:148407.0,148356.1] || -> node4(s46)*. % 76.16/76.34 148411[109:MRR:780.0,148409.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 148418[109:Res:53.1,148411.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 148423[110:Spt:148418.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 148425[110:Res:148423.0,61.1] always3(s46) || -> . % 76.16/76.34 148426[110:SSi:148425.0,78272.0,78276.0,137768.0,148355.0,148409.0] || -> . % 76.16/76.34 148427[110:Spt:148426.0,148418.0,148423.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 148428[110:Spt:148426.0,148418.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 148432[110:Res:148428.0,61.1] always3(s47) || -> . % 76.16/76.34 148433[110:SSi:148432.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 148434[108:Spt:148433.0,148354.0,148355.0] || until2p7(s46)*+ -> . % 76.16/76.34 148435[108:Spt:148433.0,148354.1] || -> node4(s45)*. % 76.16/76.34 148437[108:MRR:783.0,148435.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 148440[108:Res:53.1,148437.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 148442[109:Spt:148440.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 148444[109:Res:148442.0,61.1] always3(s45) || -> . % 76.16/76.34 148445[109:SSi:148444.0,78268.0,78271.0,137767.0,148353.0,148435.0] || -> . % 76.16/76.34 148446[109:Spt:148445.0,148440.0,148442.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 148447[109:Spt:148445.0,148440.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 148451[109:Res:148447.0,61.1] always3(s46) || -> . % 76.16/76.34 148452[109:SSi:148451.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 148453[107:Spt:148452.0,148352.0,148353.0] || until2p7(s45)*+ -> . % 76.16/76.34 148454[107:Spt:148452.0,148352.1] || -> node4(s44)*. % 76.16/76.34 148456[107:MRR:786.0,148454.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 148459[107:Res:53.1,148456.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 148461[108:Spt:148459.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 148463[108:Res:148461.0,61.1] always3(s44) || -> . % 76.16/76.34 148464[108:SSi:148463.0,78263.0,78267.0,137766.0,148351.0,148454.0] || -> . % 76.16/76.34 148465[108:Spt:148464.0,148459.0,148461.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 148466[108:Spt:148464.0,148459.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 148470[108:Res:148466.0,61.1] always3(s45) || -> . % 76.16/76.34 148471[108:SSi:148470.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 148472[106:Spt:148471.0,148350.0,148351.0] || until2p7(s44)*+ -> . % 76.16/76.34 148473[106:Spt:148471.0,148350.1] || -> node4(s43)*. % 76.16/76.34 148475[106:MRR:789.0,148473.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 148478[106:Res:53.1,148475.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 148480[107:Spt:148478.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 148482[107:Res:148480.0,61.1] always3(s43) || -> . % 76.16/76.34 148483[107:SSi:148482.0,78259.0,78262.0,137765.0,148349.0,148473.0] || -> . % 76.16/76.34 148484[107:Spt:148483.0,148478.0,148480.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 148485[107:Spt:148483.0,148478.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 148489[107:Res:148485.0,61.1] always3(s44) || -> . % 76.16/76.34 148490[107:SSi:148489.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 148491[105:Spt:148490.0,148348.0,148349.0] || until2p7(s43)*+ -> . % 76.16/76.34 148492[105:Spt:148490.0,148348.1] || -> node4(s42)*. % 76.16/76.34 148494[105:MRR:792.0,148492.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 148497[105:Res:53.1,148494.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 148502[106:Spt:148497.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 148504[106:Res:148502.0,61.1] always3(s42) || -> . % 76.16/76.34 148505[106:SSi:148504.0,78254.0,78258.0,137764.0,148347.0,148492.0] || -> . % 76.16/76.34 148506[106:Spt:148505.0,148497.0,148502.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 148507[106:Spt:148505.0,148497.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 148511[106:Res:148507.0,61.1] always3(s43) || -> . % 76.16/76.34 148512[106:SSi:148511.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 148513[104:Spt:148512.0,148346.0,148347.0] || until2p7(s42)*+ -> . % 76.16/76.34 148514[104:Spt:148512.0,148346.1] || -> node4(s41)*. % 76.16/76.34 148516[104:MRR:795.0,148514.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 148519[104:Res:53.1,148516.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 148521[105:Spt:148519.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 148523[105:Res:148521.0,61.1] always3(s41) || -> . % 76.16/76.34 148524[105:SSi:148523.0,78250.0,78253.0,137763.0,148345.0,148514.0] || -> . % 76.16/76.34 148525[105:Spt:148524.0,148519.0,148521.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 148526[105:Spt:148524.0,148519.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 148530[105:Res:148526.0,61.1] always3(s42) || -> . % 76.16/76.34 148531[105:SSi:148530.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 148532[103:Spt:148531.0,148344.0,148345.0] || until2p7(s41)*+ -> . % 76.16/76.34 148533[103:Spt:148531.0,148344.1] || -> node4(s40)*. % 76.16/76.34 148535[103:MRR:798.0,148533.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 148538[103:Res:53.1,148535.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 148540[104:Spt:148538.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 148542[104:Res:148540.0,61.1] always3(s40) || -> . % 76.16/76.34 148543[104:SSi:148542.0,78245.0,78249.0,137762.0,148343.0,148533.0] || -> . % 76.16/76.34 148544[104:Spt:148543.0,148538.0,148540.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 148545[104:Spt:148543.0,148538.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 148549[104:Res:148545.0,61.1] always3(s41) || -> . % 76.16/76.34 148550[104:SSi:148549.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 148551[102:Spt:148550.0,148342.0,148343.0] || until2p7(s40)*+ -> . % 76.16/76.34 148552[102:Spt:148550.0,148342.1] || -> node4(s39)*. % 76.16/76.34 148554[102:MRR:801.0,148552.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 148557[102:Res:53.1,148554.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 148559[103:Spt:148557.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 148561[103:Res:148559.0,61.1] always3(s39) || -> . % 76.16/76.34 148562[103:SSi:148561.0,78241.0,78244.0,137761.0,148341.0,148552.0] || -> . % 76.16/76.34 148563[103:Spt:148562.0,148557.0,148559.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 148564[103:Spt:148562.0,148557.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 148568[103:Res:148564.0,61.1] always3(s40) || -> . % 76.16/76.34 148569[103:SSi:148568.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 148570[101:Spt:148569.0,148340.0,148341.0] || until2p7(s39)*+ -> . % 76.16/76.34 148571[101:Spt:148569.0,148340.1] || -> node4(s38)*. % 76.16/76.34 148573[101:MRR:804.0,148571.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 148576[101:Res:53.1,148573.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 148581[102:Spt:148576.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 148583[102:Res:148581.0,61.1] always3(s38) || -> . % 76.16/76.34 148584[102:SSi:148583.0,78236.0,78240.0,137760.0,148339.0,148571.0] || -> . % 76.16/76.34 148585[102:Spt:148584.0,148576.0,148581.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 148586[102:Spt:148584.0,148576.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 148590[102:Res:148586.0,61.1] always3(s39) || -> . % 76.16/76.34 148591[102:SSi:148590.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 148592[100:Spt:148591.0,148338.0,148339.0] || until2p7(s38)*+ -> . % 76.16/76.34 148593[100:Spt:148591.0,148338.1] || -> node4(s37)*. % 76.16/76.34 148595[100:MRR:807.0,148593.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 148598[100:Res:53.1,148595.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 148600[101:Spt:148598.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 148602[101:Res:148600.0,61.1] always3(s37) || -> . % 76.16/76.34 148603[101:SSi:148602.0,78232.0,78235.0,137759.0,148337.0,148593.0] || -> . % 76.16/76.34 148604[101:Spt:148603.0,148598.0,148600.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 148605[101:Spt:148603.0,148598.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 148609[101:Res:148605.0,61.1] always3(s38) || -> . % 76.16/76.34 148610[101:SSi:148609.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 148611[99:Spt:148610.0,148336.0,148337.0] || until2p7(s37)*+ -> . % 76.16/76.34 148612[99:Spt:148610.0,148336.1] || -> node4(s36)*. % 76.16/76.34 148614[99:MRR:810.0,148612.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 148617[99:Res:53.1,148614.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 148619[100:Spt:148617.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 148621[100:Res:148619.0,61.1] always3(s36) || -> . % 76.16/76.34 148622[100:SSi:148621.0,78227.0,78231.0,137758.0,148335.0,148612.0] || -> . % 76.16/76.34 148623[100:Spt:148622.0,148617.0,148619.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 148624[100:Spt:148622.0,148617.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 148628[100:Res:148624.0,61.1] always3(s37) || -> . % 76.16/76.34 148629[100:SSi:148628.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 148630[98:Spt:148629.0,148334.0,148335.0] || until2p7(s36)*+ -> . % 76.16/76.34 148631[98:Spt:148629.0,148334.1] || -> node4(s35)*. % 76.16/76.34 148633[98:MRR:813.0,148631.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 148636[98:Res:53.1,148633.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 148638[99:Spt:148636.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 148640[99:Res:148638.0,61.1] always3(s35) || -> . % 76.16/76.34 148641[99:SSi:148640.0,78223.0,78226.0,137757.0,148333.0,148631.0] || -> . % 76.16/76.34 148642[99:Spt:148641.0,148636.0,148638.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 148643[99:Spt:148641.0,148636.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 148647[99:Res:148643.0,61.1] always3(s36) || -> . % 76.16/76.34 148648[99:SSi:148647.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 148649[97:Spt:148648.0,148332.0,148333.0] || until2p7(s35)*+ -> . % 76.16/76.34 148650[97:Spt:148648.0,148332.1] || -> node4(s34)*. % 76.16/76.34 148652[97:MRR:816.0,148650.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 148655[97:Res:53.1,148652.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 148660[98:Spt:148655.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 148662[98:Res:148660.0,61.1] always3(s34) || -> . % 76.16/76.34 148663[98:SSi:148662.0,78218.0,78222.0,137756.0,148331.0,148650.0] || -> . % 76.16/76.34 148664[98:Spt:148663.0,148655.0,148660.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 148665[98:Spt:148663.0,148655.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 148669[98:Res:148665.0,61.1] always3(s35) || -> . % 76.16/76.34 148670[98:SSi:148669.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 148671[96:Spt:148670.0,148330.0,148331.0] || until2p7(s34)*+ -> . % 76.16/76.34 148672[96:Spt:148670.0,148330.1] || -> node4(s33)*. % 76.16/76.34 148674[96:MRR:819.0,148672.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 148677[96:Res:53.1,148674.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 148679[97:Spt:148677.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 148681[97:Res:148679.0,61.1] always3(s33) || -> . % 76.16/76.34 148682[97:SSi:148681.0,78214.0,78217.0,137755.0,148329.0,148672.0] || -> . % 76.16/76.34 148683[97:Spt:148682.0,148677.0,148679.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.34 148684[97:Spt:148682.0,148677.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 148688[97:Res:148684.0,61.1] always3(s34) || -> . % 76.16/76.34 148689[97:SSi:148688.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 148690[95:Spt:148689.0,148328.0,148329.0] || until2p7(s33)*+ -> . % 76.16/76.34 148691[95:Spt:148689.0,148328.1] || -> node4(s32)*. % 76.16/76.34 148693[95:MRR:822.0,148691.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.34 148696[95:Res:53.1,148693.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.34 148698[96:Spt:148696.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 148700[96:Res:148698.0,61.1] always3(s32) || -> . % 76.16/76.34 148701[96:SSi:148700.0,78209.0,78213.0,137754.0,148327.0,148691.0] || -> . % 76.16/76.34 148702[96:Spt:148701.0,148696.0,148698.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.34 148703[96:Spt:148701.0,148696.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 148707[96:Res:148703.0,61.1] always3(s33) || -> . % 76.16/76.34 148708[96:SSi:148707.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 148709[94:Spt:148708.0,148326.0,148327.0] || until2p7(s32)*+ -> . % 76.16/76.34 148710[94:Spt:148708.0,148326.1] || -> node4(s31)*. % 76.16/76.34 148712[94:MRR:825.0,148710.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.34 148715[94:Res:53.1,148712.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.34 148717[95:Spt:148715.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 148719[95:Res:148717.0,61.1] always3(s31) || -> . % 76.16/76.34 148720[95:SSi:148719.0,78205.0,78208.0,137753.0,148325.0,148710.0] || -> . % 76.16/76.34 148721[95:Spt:148720.0,148715.0,148717.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.34 148722[95:Spt:148720.0,148715.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 148726[95:Res:148722.0,61.1] always3(s32) || -> . % 76.16/76.34 148727[95:SSi:148726.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.34 148728[93:Spt:148727.0,148324.0,148325.0] || until2p7(s31)*+ -> . % 76.16/76.34 148729[93:Spt:148727.0,148324.1] || -> node4(s30)*. % 76.16/76.34 148731[93:MRR:828.0,148729.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.34 148734[93:Res:53.1,148731.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.34 148739[94:Spt:148734.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 148741[94:Res:148739.0,61.1] always3(s30) || -> . % 76.16/76.34 148742[94:SSi:148741.0,78200.0,78204.0,137752.0,148323.0,148729.0] || -> . % 76.16/76.34 148743[94:Spt:148742.0,148734.0,148739.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.34 148744[94:Spt:148742.0,148734.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 148748[94:Res:148744.0,61.1] always3(s31) || -> . % 76.16/76.34 148749[94:SSi:148748.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.34 148750[92:Spt:148749.0,148322.0,148323.0] || until2p7(s30)*+ -> . % 76.16/76.34 148751[92:Spt:148749.0,148322.1] || -> node4(s29)*. % 76.16/76.34 148753[92:MRR:831.0,148751.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.34 148756[92:Res:53.1,148753.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.34 148758[93:Spt:148756.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 148760[93:Res:148758.0,61.1] always3(s29) || -> . % 76.16/76.34 148761[93:SSi:148760.0,78196.0,78199.0,137751.0,148321.0,148751.0] || -> . % 76.16/76.34 148762[93:Spt:148761.0,148756.0,148758.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.34 148763[93:Spt:148761.0,148756.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 148767[93:Res:148763.0,61.1] always3(s30) || -> . % 76.16/76.34 148768[93:SSi:148767.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.34 148769[91:Spt:148768.0,148320.0,148321.0] || until2p7(s29)*+ -> . % 76.16/76.34 148770[91:Spt:148768.0,148320.1] || -> node4(s28)*. % 76.16/76.34 148772[91:MRR:834.0,148770.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.34 148775[91:Res:53.1,148772.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.34 148777[92:Spt:148775.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 148779[92:Res:148777.0,61.1] always3(s28) || -> . % 76.16/76.34 148780[92:SSi:148779.0,78191.0,78195.0,137750.0,148319.0,148770.0] || -> . % 76.16/76.34 148781[92:Spt:148780.0,148775.0,148777.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.34 148782[92:Spt:148780.0,148775.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 148786[92:Res:148782.0,61.1] always3(s29) || -> . % 76.16/76.34 148787[92:SSi:148786.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.34 148788[90:Spt:148787.0,148318.0,148319.0] || until2p7(s28)*+ -> . % 76.16/76.34 148789[90:Spt:148787.0,148318.1] || -> node4(s27)*. % 76.16/76.34 148791[90:MRR:837.0,148789.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.34 148794[90:Res:53.1,148791.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.34 148796[91:Spt:148794.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 148798[91:Res:148796.0,61.1] always3(s27) || -> . % 76.16/76.34 148799[91:SSi:148798.0,78187.0,78190.0,137749.0,148317.0,148789.0] || -> . % 76.16/76.34 148800[91:Spt:148799.0,148794.0,148796.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.34 148801[91:Spt:148799.0,148794.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 148805[91:Res:148801.0,61.1] always3(s28) || -> . % 76.16/76.34 148806[91:SSi:148805.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.34 148807[89:Spt:148806.0,148316.0,148317.0] || until2p7(s27)*+ -> . % 76.16/76.34 148808[89:Spt:148806.0,148316.1] || -> node4(s26)*. % 76.16/76.34 148810[89:MRR:840.0,148808.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.34 148813[89:Res:53.1,148810.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.34 148818[90:Spt:148813.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 148820[90:Res:148818.0,61.1] always3(s26) || -> . % 76.16/76.34 148821[90:SSi:148820.0,78182.0,78186.0,137748.0,148315.0,148808.0] || -> . % 76.16/76.34 148822[90:Spt:148821.0,148813.0,148818.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.34 148823[90:Spt:148821.0,148813.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 148827[90:Res:148823.0,61.1] always3(s27) || -> . % 76.16/76.34 148828[90:SSi:148827.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.34 148829[88:Spt:148828.0,148314.0,148315.0] || until2p7(s26)*+ -> . % 76.16/76.34 148830[88:Spt:148828.0,148314.1] || -> node4(s25)*. % 76.16/76.34 148832[88:MRR:843.0,148830.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.34 148835[88:Res:53.1,148832.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.34 148837[89:Spt:148835.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.34 148839[89:Res:148837.0,61.1] always3(s25) || -> . % 76.16/76.34 148840[89:SSi:148839.0,78178.0,78181.0,137747.0,148313.0,148830.0] || -> . % 76.16/76.34 148841[89:Spt:148840.0,148835.0,148837.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.34 148842[89:Spt:148840.0,148835.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 148846[89:Res:148842.0,61.1] always3(s26) || -> . % 76.16/76.34 148847[89:SSi:148846.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.34 148848[87:Spt:148847.0,148312.0,148313.0] || until2p7(s25)*+ -> . % 76.16/76.34 148849[87:Spt:148847.0,148312.1] || -> node4(s24)*. % 76.16/76.34 148851[87:MRR:846.0,148849.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.34 148854[87:Res:53.1,148851.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.34 148856[88:Spt:148854.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.34 148858[88:Res:148856.0,61.1] always3(s24) || -> . % 76.16/76.34 148859[88:SSi:148858.0,78173.0,78177.0,137746.0,148311.0,148849.0] || -> . % 76.16/76.34 148860[88:Spt:148859.0,148854.0,148856.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.34 148861[88:Spt:148859.0,148854.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.34 148865[88:Res:148861.0,61.1] always3(s25) || -> . % 76.16/76.34 148866[88:SSi:148865.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.34 148867[86:Spt:148866.0,148310.0,148311.0] || until2p7(s24)*+ -> . % 76.16/76.34 148868[86:Spt:148866.0,148310.1] || -> node4(s23)*. % 76.16/76.34 148870[86:MRR:849.0,148868.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.34 148873[86:Res:53.1,148870.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.34 148875[87:Spt:148873.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.34 148877[87:Res:148875.0,61.1] always3(s23) || -> . % 76.16/76.34 148878[87:SSi:148877.0,78169.0,78172.0,137745.0,148309.0,148868.0] || -> . % 76.16/76.34 148879[87:Spt:148878.0,148873.0,148875.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.34 148880[87:Spt:148878.0,148873.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.34 148884[87:Res:148880.0,61.1] always3(s24) || -> . % 76.16/76.34 148885[87:SSi:148884.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.34 148886[85:Spt:148885.0,148308.0,148309.0] || until2p7(s23)*+ -> . % 76.16/76.34 148887[85:Spt:148885.0,148308.1] || -> node4(s22)*. % 76.16/76.34 148889[85:MRR:852.0,148887.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.34 148892[85:Res:53.1,148889.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.34 148897[86:Spt:148892.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.34 148899[86:Res:148897.0,61.1] always3(s22) || -> . % 76.16/76.34 148900[86:SSi:148899.0,78164.0,78168.0,137744.0,148307.0,148887.0] || -> . % 76.16/76.34 148901[86:Spt:148900.0,148892.0,148897.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.34 148902[86:Spt:148900.0,148892.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.34 148906[86:Res:148902.0,61.1] always3(s23) || -> . % 76.16/76.34 148907[86:SSi:148906.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.34 148908[84:Spt:148907.0,148306.0,148307.0] || until2p7(s22)*+ -> . % 76.16/76.34 148909[84:Spt:148907.0,148306.1] || -> node4(s21)*. % 76.16/76.34 148911[84:MRR:855.0,148909.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.34 148914[84:Res:53.1,148911.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.34 148916[84:MRR:148914.0,148296.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.34 148918[84:Res:148916.0,61.1] always3(s22) || -> . % 76.16/76.34 148919[84:SSi:148918.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.34 148920[82:Spt:148919.0,148186.0,148189.0] || trans(s49,s21)*+ -> . % 76.16/76.34 148921[82:Spt:148919.0,148186.1,148186.2,148186.3,148186.4,148186.5,148186.6,148186.7,148186.8,148186.9,148186.10,148186.11,148186.12,148186.13,148186.14,148186.15,148186.16,148186.17] || -> trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.34 148923[82:MRR:148188.1,148920.0] xuntil6(s49) || -> trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.34 148924[83:Spt:148921.0] || -> trans(s49,s20)*. % 76.16/76.34 148925[83:Res:148924.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s20)*. % 76.16/76.34 148927[83:Res:148924.0,60.0] || -> node2(s49,s20)*. % 76.16/76.34 148928[83:SSi:148925.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s20)*. % 76.16/76.34 148929[83:Res:148927.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)*. % 76.16/76.34 149027[83:SoR:148929.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)*. % 76.16/76.34 149029[83:SoR:149027.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)* xuntil6(s49). % 76.16/76.34 149030[83:SSi:149029.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s20,c_busy)* xuntil6(s49). % 76.16/76.34 149031[84:Spt:149030.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.34 149033[84:Res:149031.0,61.1] always3(s20) || -> . % 76.16/76.34 149034[84:SSi:149033.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.34 149035[84:Spt:149034.0,149030.1,149031.0] || m_main_v_state(s20,c_busy)*+ -> . % 76.16/76.34 149036[84:Spt:149034.0,149030.0,149030.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.34 149040[84:MRR:149027.2,149035.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.34 149041[84:Res:53.1,149036.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.34 149043[84:MRR:149041.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.34 149044[84:MRR:148928.0,149043.0] || -> until2p7(s20)*. % 76.16/76.34 149045[84:MRR:216.0,149044.0] || -> until2p7(s21)* node4(s20). % 76.16/76.34 149046[85:Spt:149045.0] || -> until2p7(s21)*. % 76.16/76.34 149047[85:MRR:217.0,149046.0] || -> until2p7(s22)* node4(s21). % 76.16/76.34 149048[86:Spt:149047.0] || -> until2p7(s22)*. % 76.16/76.34 149049[86:MRR:218.0,149048.0] || -> until2p7(s23)* node4(s22). % 76.16/76.34 149050[87:Spt:149049.0] || -> until2p7(s23)*. % 76.16/76.34 149051[87:MRR:219.0,149050.0] || -> until2p7(s24)* node4(s23). % 76.16/76.34 149052[88:Spt:149051.0] || -> until2p7(s24)*. % 76.16/76.34 149053[88:MRR:220.0,149052.0] || -> until2p7(s25)* node4(s24). % 76.16/76.34 149054[89:Spt:149053.0] || -> until2p7(s25)*. % 76.16/76.34 149055[89:MRR:221.0,149054.0] || -> until2p7(s26)* node4(s25). % 76.16/76.34 149056[90:Spt:149055.0] || -> until2p7(s26)*. % 76.16/76.34 149057[90:MRR:222.0,149056.0] || -> until2p7(s27)* node4(s26). % 76.16/76.34 149058[91:Spt:149057.0] || -> until2p7(s27)*. % 76.16/76.34 149059[91:MRR:223.0,149058.0] || -> until2p7(s28)* node4(s27). % 76.16/76.34 149060[92:Spt:149059.0] || -> until2p7(s28)*. % 76.16/76.34 149061[92:MRR:224.0,149060.0] || -> until2p7(s29)* node4(s28). % 76.16/76.34 149062[93:Spt:149061.0] || -> until2p7(s29)*. % 76.16/76.34 149063[93:MRR:225.0,149062.0] || -> until2p7(s30)* node4(s29). % 76.16/76.34 149064[94:Spt:149063.0] || -> until2p7(s30)*. % 76.16/76.34 149065[94:MRR:226.0,149064.0] || -> until2p7(s31)* node4(s30). % 76.16/76.34 149066[95:Spt:149065.0] || -> until2p7(s31)*. % 76.16/76.34 149067[95:MRR:227.0,149066.0] || -> until2p7(s32)* node4(s31). % 76.16/76.34 149068[96:Spt:149067.0] || -> until2p7(s32)*. % 76.16/76.34 149069[96:MRR:228.0,149068.0] || -> until2p7(s33)* node4(s32). % 76.16/76.34 149070[97:Spt:149069.0] || -> until2p7(s33)*. % 76.16/76.34 149071[97:MRR:229.0,149070.0] || -> until2p7(s34)* node4(s33). % 76.16/76.34 149072[98:Spt:149071.0] || -> until2p7(s34)*. % 76.16/76.34 149073[98:MRR:230.0,149072.0] || -> until2p7(s35)* node4(s34). % 76.16/76.34 149074[99:Spt:149073.0] || -> until2p7(s35)*. % 76.16/76.34 149075[99:MRR:231.0,149074.0] || -> until2p7(s36)* node4(s35). % 76.16/76.34 149076[100:Spt:149075.0] || -> until2p7(s36)*. % 76.16/76.34 149077[100:MRR:232.0,149076.0] || -> until2p7(s37)* node4(s36). % 76.16/76.34 149078[101:Spt:149077.0] || -> until2p7(s37)*. % 76.16/76.34 149079[101:MRR:235.0,149078.0] || -> until2p7(s38)* node4(s37). % 76.16/76.34 149080[102:Spt:149079.0] || -> until2p7(s38)*. % 76.16/76.34 149081[102:MRR:236.0,149080.0] || -> until2p7(s39)* node4(s38). % 76.16/76.34 149082[103:Spt:149081.0] || -> until2p7(s39)*. % 76.16/76.34 149083[103:MRR:237.0,149082.0] || -> until2p7(s40)* node4(s39). % 76.16/76.34 149084[104:Spt:149083.0] || -> until2p7(s40)*. % 76.16/76.34 149085[104:MRR:238.0,149084.0] || -> until2p7(s41)* node4(s40). % 76.16/76.34 149086[105:Spt:149085.0] || -> until2p7(s41)*. % 76.16/76.34 149087[105:MRR:239.0,149086.0] || -> until2p7(s42)* node4(s41). % 76.16/76.34 149088[106:Spt:149087.0] || -> until2p7(s42)*. % 76.16/76.34 149089[106:MRR:240.0,149088.0] || -> until2p7(s43)* node4(s42). % 76.16/76.34 149090[107:Spt:149089.0] || -> until2p7(s43)*. % 76.16/76.34 149091[107:MRR:241.0,149090.0] || -> until2p7(s44)* node4(s43). % 76.16/76.34 149092[108:Spt:149091.0] || -> until2p7(s44)*. % 76.16/76.34 149093[108:MRR:539.0,149092.0] || -> until2p7(s45)* node4(s44). % 76.16/76.34 149094[109:Spt:149093.0] || -> until2p7(s45)*. % 76.16/76.34 149095[109:MRR:544.0,149094.0] || -> until2p7(s46)* node4(s45). % 76.16/76.34 149096[110:Spt:149095.0] || -> until2p7(s46)*. % 76.16/76.34 149097[110:MRR:549.0,149096.0] || -> until2p7(s47)* node4(s46). % 76.16/76.34 149098[111:Spt:149097.0] || -> until2p7(s47)*. % 76.16/76.34 149099[111:MRR:554.0,149098.0] || -> until2p7(s48)* node4(s47). % 76.16/76.34 149100[112:Spt:149099.0] || -> until2p7(s48)*. % 76.16/76.34 149101[112:MRR:559.0,149100.0] || -> until2p7(s49)* node4(s48). % 76.16/76.34 149102[113:Spt:149101.0] || -> until2p7(s49)*. % 76.16/76.34 149103[113:MRR:194.0,149102.0] || -> node4(s49)*. % 76.16/76.34 149104[113:MRR:149040.0,149103.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.34 149105[113:Res:53.1,149104.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.34 149107[113:MRR:149105.0,78381.0] || -> . % 76.16/76.34 149108[113:Spt:149107.0,149101.0,149102.0] || until2p7(s49)*+ -> . % 76.16/76.34 149109[113:Spt:149107.0,149101.1] || -> node4(s48)*. % 76.16/76.34 149110[113:MRR:78384.0,149109.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.34 149113[113:Res:53.1,149110.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 149116[113:Res:149113.0,61.1] always3(s48) || -> . % 76.16/76.34 149117[113:SSi:149116.0,78281.0,78387.0,137770.0,149100.0,149109.0] || -> . % 76.16/76.34 149118[112:Spt:149117.0,149099.0,149100.0] || until2p7(s48)*+ -> . % 76.16/76.34 149119[112:Spt:149117.0,149099.1] || -> node4(s47)*. % 76.16/76.34 149121[112:MRR:777.0,149119.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.34 149136[112:Res:53.1,149121.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.34 149138[113:Spt:149136.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 149140[113:Res:149138.0,61.1] always3(s47) || -> . % 76.16/76.34 149141[113:SSi:149140.0,78277.0,78280.0,137769.0,149098.0,149119.0] || -> . % 76.16/76.34 149142[113:Spt:149141.0,149136.0,149138.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.34 149143[113:Spt:149141.0,149136.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.34 149147[113:Res:149143.0,61.1] always3(s48) || -> . % 76.16/76.34 149148[113:SSi:149147.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.34 149149[111:Spt:149148.0,149097.0,149098.0] || until2p7(s47)*+ -> . % 76.16/76.34 149150[111:Spt:149148.0,149097.1] || -> node4(s46)*. % 76.16/76.34 149152[111:MRR:780.0,149150.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.34 149162[111:Res:53.1,149152.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.34 149164[112:Spt:149162.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 149166[112:Res:149164.0,61.1] always3(s46) || -> . % 76.16/76.34 149167[112:SSi:149166.0,78272.0,78276.0,137768.0,149096.0,149150.0] || -> . % 76.16/76.34 149168[112:Spt:149167.0,149162.0,149164.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.34 149169[112:Spt:149167.0,149162.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.34 149173[112:Res:149169.0,61.1] always3(s47) || -> . % 76.16/76.34 149174[112:SSi:149173.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.34 149175[110:Spt:149174.0,149095.0,149096.0] || until2p7(s46)*+ -> . % 76.16/76.34 149176[110:Spt:149174.0,149095.1] || -> node4(s45)*. % 76.16/76.34 149178[110:MRR:783.0,149176.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.34 149181[110:Res:53.1,149178.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.34 149183[111:Spt:149181.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 149185[111:Res:149183.0,61.1] always3(s45) || -> . % 76.16/76.34 149186[111:SSi:149185.0,78268.0,78271.0,137767.0,149094.0,149176.0] || -> . % 76.16/76.34 149187[111:Spt:149186.0,149181.0,149183.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.34 149188[111:Spt:149186.0,149181.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.34 149192[111:Res:149188.0,61.1] always3(s46) || -> . % 76.16/76.34 149193[111:SSi:149192.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.34 149194[109:Spt:149193.0,149093.0,149094.0] || until2p7(s45)*+ -> . % 76.16/76.34 149195[109:Spt:149193.0,149093.1] || -> node4(s44)*. % 76.16/76.34 149197[109:MRR:786.0,149195.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.34 149200[109:Res:53.1,149197.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.34 149202[110:Spt:149200.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 149204[110:Res:149202.0,61.1] always3(s44) || -> . % 76.16/76.34 149205[110:SSi:149204.0,78263.0,78267.0,137766.0,149092.0,149195.0] || -> . % 76.16/76.34 149206[110:Spt:149205.0,149200.0,149202.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.34 149207[110:Spt:149205.0,149200.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.34 149211[110:Res:149207.0,61.1] always3(s45) || -> . % 76.16/76.34 149212[110:SSi:149211.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.34 149213[108:Spt:149212.0,149091.0,149092.0] || until2p7(s44)*+ -> . % 76.16/76.34 149214[108:Spt:149212.0,149091.1] || -> node4(s43)*. % 76.16/76.34 149216[108:MRR:789.0,149214.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.34 149219[108:Res:53.1,149216.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.34 149224[109:Spt:149219.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 149226[109:Res:149224.0,61.1] always3(s43) || -> . % 76.16/76.34 149227[109:SSi:149226.0,78259.0,78262.0,137765.0,149090.0,149214.0] || -> . % 76.16/76.34 149228[109:Spt:149227.0,149219.0,149224.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.34 149229[109:Spt:149227.0,149219.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.34 149233[109:Res:149229.0,61.1] always3(s44) || -> . % 76.16/76.34 149234[109:SSi:149233.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.34 149235[107:Spt:149234.0,149089.0,149090.0] || until2p7(s43)*+ -> . % 76.16/76.34 149236[107:Spt:149234.0,149089.1] || -> node4(s42)*. % 76.16/76.34 149238[107:MRR:792.0,149236.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.34 149241[107:Res:53.1,149238.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.34 149243[108:Spt:149241.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 149245[108:Res:149243.0,61.1] always3(s42) || -> . % 76.16/76.34 149246[108:SSi:149245.0,78254.0,78258.0,137764.0,149088.0,149236.0] || -> . % 76.16/76.34 149247[108:Spt:149246.0,149241.0,149243.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.34 149248[108:Spt:149246.0,149241.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.34 149252[108:Res:149248.0,61.1] always3(s43) || -> . % 76.16/76.34 149253[108:SSi:149252.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.34 149254[106:Spt:149253.0,149087.0,149088.0] || until2p7(s42)*+ -> . % 76.16/76.34 149255[106:Spt:149253.0,149087.1] || -> node4(s41)*. % 76.16/76.34 149257[106:MRR:795.0,149255.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.34 149260[106:Res:53.1,149257.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.34 149262[107:Spt:149260.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 149264[107:Res:149262.0,61.1] always3(s41) || -> . % 76.16/76.34 149265[107:SSi:149264.0,78250.0,78253.0,137763.0,149086.0,149255.0] || -> . % 76.16/76.34 149266[107:Spt:149265.0,149260.0,149262.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.34 149267[107:Spt:149265.0,149260.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.34 149271[107:Res:149267.0,61.1] always3(s42) || -> . % 76.16/76.34 149272[107:SSi:149271.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.34 149273[105:Spt:149272.0,149085.0,149086.0] || until2p7(s41)*+ -> . % 76.16/76.34 149274[105:Spt:149272.0,149085.1] || -> node4(s40)*. % 76.16/76.34 149276[105:MRR:798.0,149274.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.34 149279[105:Res:53.1,149276.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.34 149281[106:Spt:149279.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 149283[106:Res:149281.0,61.1] always3(s40) || -> . % 76.16/76.34 149284[106:SSi:149283.0,78245.0,78249.0,137762.0,149084.0,149274.0] || -> . % 76.16/76.34 149285[106:Spt:149284.0,149279.0,149281.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.34 149286[106:Spt:149284.0,149279.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.34 149290[106:Res:149286.0,61.1] always3(s41) || -> . % 76.16/76.34 149291[106:SSi:149290.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.34 149292[104:Spt:149291.0,149083.0,149084.0] || until2p7(s40)*+ -> . % 76.16/76.34 149293[104:Spt:149291.0,149083.1] || -> node4(s39)*. % 76.16/76.34 149295[104:MRR:801.0,149293.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.34 149298[104:Res:53.1,149295.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.34 149303[105:Spt:149298.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 149305[105:Res:149303.0,61.1] always3(s39) || -> . % 76.16/76.34 149306[105:SSi:149305.0,78241.0,78244.0,137761.0,149082.0,149293.0] || -> . % 76.16/76.34 149307[105:Spt:149306.0,149298.0,149303.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.34 149308[105:Spt:149306.0,149298.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.34 149312[105:Res:149308.0,61.1] always3(s40) || -> . % 76.16/76.34 149313[105:SSi:149312.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.34 149314[103:Spt:149313.0,149081.0,149082.0] || until2p7(s39)*+ -> . % 76.16/76.34 149315[103:Spt:149313.0,149081.1] || -> node4(s38)*. % 76.16/76.34 149317[103:MRR:804.0,149315.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.34 149320[103:Res:53.1,149317.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.34 149322[104:Spt:149320.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 149324[104:Res:149322.0,61.1] always3(s38) || -> . % 76.16/76.34 149325[104:SSi:149324.0,78236.0,78240.0,137760.0,149080.0,149315.0] || -> . % 76.16/76.34 149326[104:Spt:149325.0,149320.0,149322.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.34 149327[104:Spt:149325.0,149320.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.34 149331[104:Res:149327.0,61.1] always3(s39) || -> . % 76.16/76.34 149332[104:SSi:149331.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.34 149333[102:Spt:149332.0,149079.0,149080.0] || until2p7(s38)*+ -> . % 76.16/76.34 149334[102:Spt:149332.0,149079.1] || -> node4(s37)*. % 76.16/76.34 149336[102:MRR:807.0,149334.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.34 149339[102:Res:53.1,149336.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.34 149341[103:Spt:149339.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 149343[103:Res:149341.0,61.1] always3(s37) || -> . % 76.16/76.34 149344[103:SSi:149343.0,78232.0,78235.0,137759.0,149078.0,149334.0] || -> . % 76.16/76.34 149345[103:Spt:149344.0,149339.0,149341.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.34 149346[103:Spt:149344.0,149339.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.34 149350[103:Res:149346.0,61.1] always3(s38) || -> . % 76.16/76.34 149351[103:SSi:149350.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.34 149352[101:Spt:149351.0,149077.0,149078.0] || until2p7(s37)*+ -> . % 76.16/76.34 149353[101:Spt:149351.0,149077.1] || -> node4(s36)*. % 76.16/76.34 149355[101:MRR:810.0,149353.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.34 149358[101:Res:53.1,149355.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.34 149360[102:Spt:149358.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 149362[102:Res:149360.0,61.1] always3(s36) || -> . % 76.16/76.34 149363[102:SSi:149362.0,78227.0,78231.0,137758.0,149076.0,149353.0] || -> . % 76.16/76.34 149364[102:Spt:149363.0,149358.0,149360.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.34 149365[102:Spt:149363.0,149358.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.34 149369[102:Res:149365.0,61.1] always3(s37) || -> . % 76.16/76.34 149370[102:SSi:149369.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.34 149371[100:Spt:149370.0,149075.0,149076.0] || until2p7(s36)*+ -> . % 76.16/76.34 149372[100:Spt:149370.0,149075.1] || -> node4(s35)*. % 76.16/76.34 149374[100:MRR:813.0,149372.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.34 149377[100:Res:53.1,149374.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.34 149382[101:Spt:149377.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 149384[101:Res:149382.0,61.1] always3(s35) || -> . % 76.16/76.34 149385[101:SSi:149384.0,78223.0,78226.0,137757.0,149074.0,149372.0] || -> . % 76.16/76.34 149386[101:Spt:149385.0,149377.0,149382.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.34 149387[101:Spt:149385.0,149377.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.34 149391[101:Res:149387.0,61.1] always3(s36) || -> . % 76.16/76.34 149392[101:SSi:149391.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.34 149393[99:Spt:149392.0,149073.0,149074.0] || until2p7(s35)*+ -> . % 76.16/76.34 149394[99:Spt:149392.0,149073.1] || -> node4(s34)*. % 76.16/76.34 149396[99:MRR:816.0,149394.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.34 149399[99:Res:53.1,149396.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.34 149401[100:Spt:149399.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 149403[100:Res:149401.0,61.1] always3(s34) || -> . % 76.16/76.34 149404[100:SSi:149403.0,78218.0,78222.0,137756.0,149072.0,149394.0] || -> . % 76.16/76.34 149405[100:Spt:149404.0,149399.0,149401.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.34 149406[100:Spt:149404.0,149399.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.34 149410[100:Res:149406.0,61.1] always3(s35) || -> . % 76.16/76.34 149411[100:SSi:149410.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.34 149412[98:Spt:149411.0,149071.0,149072.0] || until2p7(s34)*+ -> . % 76.16/76.34 149413[98:Spt:149411.0,149071.1] || -> node4(s33)*. % 76.16/76.34 149415[98:MRR:819.0,149413.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.34 149418[98:Res:53.1,149415.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.34 149420[99:Spt:149418.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 149422[99:Res:149420.0,61.1] always3(s33) || -> . % 76.16/76.34 149423[99:SSi:149422.0,78214.0,78217.0,137755.0,149070.0,149413.0] || -> . % 76.16/76.34 149424[99:Spt:149423.0,149418.0,149420.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.34 149425[99:Spt:149423.0,149418.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.34 149429[99:Res:149425.0,61.1] always3(s34) || -> . % 76.16/76.34 149430[99:SSi:149429.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.34 149431[97:Spt:149430.0,149069.0,149070.0] || until2p7(s33)*+ -> . % 76.16/76.34 149432[97:Spt:149430.0,149069.1] || -> node4(s32)*. % 76.16/76.34 149434[97:MRR:822.0,149432.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.34 149437[97:Res:53.1,149434.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.34 149439[98:Spt:149437.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 149441[98:Res:149439.0,61.1] always3(s32) || -> . % 76.16/76.34 149442[98:SSi:149441.0,78209.0,78213.0,137754.0,149068.0,149432.0] || -> . % 76.16/76.34 149443[98:Spt:149442.0,149437.0,149439.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.34 149444[98:Spt:149442.0,149437.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.34 149448[98:Res:149444.0,61.1] always3(s33) || -> . % 76.16/76.34 149449[98:SSi:149448.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.34 149450[96:Spt:149449.0,149067.0,149068.0] || until2p7(s32)*+ -> . % 76.16/76.34 149451[96:Spt:149449.0,149067.1] || -> node4(s31)*. % 76.16/76.34 149453[96:MRR:825.0,149451.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.34 149456[96:Res:53.1,149453.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.34 149461[97:Spt:149456.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 149463[97:Res:149461.0,61.1] always3(s31) || -> . % 76.16/76.34 149464[97:SSi:149463.0,78205.0,78208.0,137753.0,149066.0,149451.0] || -> . % 76.16/76.34 149465[97:Spt:149464.0,149456.0,149461.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.34 149466[97:Spt:149464.0,149456.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.34 149470[97:Res:149466.0,61.1] always3(s32) || -> . % 76.16/76.34 149471[97:SSi:149470.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.34 149472[95:Spt:149471.0,149065.0,149066.0] || until2p7(s31)*+ -> . % 76.16/76.34 149473[95:Spt:149471.0,149065.1] || -> node4(s30)*. % 76.16/76.34 149475[95:MRR:828.0,149473.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.34 149478[95:Res:53.1,149475.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.34 149480[96:Spt:149478.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 149482[96:Res:149480.0,61.1] always3(s30) || -> . % 76.16/76.34 149483[96:SSi:149482.0,78200.0,78204.0,137752.0,149064.0,149473.0] || -> . % 76.16/76.34 149484[96:Spt:149483.0,149478.0,149480.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.34 149485[96:Spt:149483.0,149478.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.34 149489[96:Res:149485.0,61.1] always3(s31) || -> . % 76.16/76.34 149490[96:SSi:149489.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.34 149491[94:Spt:149490.0,149063.0,149064.0] || until2p7(s30)*+ -> . % 76.16/76.34 149492[94:Spt:149490.0,149063.1] || -> node4(s29)*. % 76.16/76.34 149494[94:MRR:831.0,149492.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.34 149497[94:Res:53.1,149494.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.34 149499[95:Spt:149497.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 149501[95:Res:149499.0,61.1] always3(s29) || -> . % 76.16/76.34 149502[95:SSi:149501.0,78196.0,78199.0,137751.0,149062.0,149492.0] || -> . % 76.16/76.34 149503[95:Spt:149502.0,149497.0,149499.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.34 149504[95:Spt:149502.0,149497.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.34 149508[95:Res:149504.0,61.1] always3(s30) || -> . % 76.16/76.34 149509[95:SSi:149508.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.34 149510[93:Spt:149509.0,149061.0,149062.0] || until2p7(s29)*+ -> . % 76.16/76.34 149511[93:Spt:149509.0,149061.1] || -> node4(s28)*. % 76.16/76.34 149513[93:MRR:834.0,149511.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.34 149516[93:Res:53.1,149513.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.34 149518[94:Spt:149516.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 149520[94:Res:149518.0,61.1] always3(s28) || -> . % 76.16/76.34 149521[94:SSi:149520.0,78191.0,78195.0,137750.0,149060.0,149511.0] || -> . % 76.16/76.34 149522[94:Spt:149521.0,149516.0,149518.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.34 149523[94:Spt:149521.0,149516.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.34 149527[94:Res:149523.0,61.1] always3(s29) || -> . % 76.16/76.34 149528[94:SSi:149527.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.34 149529[92:Spt:149528.0,149059.0,149060.0] || until2p7(s28)*+ -> . % 76.16/76.34 149530[92:Spt:149528.0,149059.1] || -> node4(s27)*. % 76.16/76.34 149532[92:MRR:837.0,149530.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.34 149535[92:Res:53.1,149532.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.34 149540[93:Spt:149535.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.34 149542[93:Res:149540.0,61.1] always3(s27) || -> . % 76.16/76.34 149543[93:SSi:149542.0,78187.0,78190.0,137749.0,149058.0,149530.0] || -> . % 76.16/76.34 149544[93:Spt:149543.0,149535.0,149540.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.34 149545[93:Spt:149543.0,149535.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.34 149549[93:Res:149545.0,61.1] always3(s28) || -> . % 76.16/76.34 149550[93:SSi:149549.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.34 149551[91:Spt:149550.0,149057.0,149058.0] || until2p7(s27)*+ -> . % 76.16/76.34 149552[91:Spt:149550.0,149057.1] || -> node4(s26)*. % 76.16/76.34 149554[91:MRR:840.0,149552.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.34 149557[91:Res:53.1,149554.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.34 149559[92:Spt:149557.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.34 149561[92:Res:149559.0,61.1] always3(s26) || -> . % 76.16/76.34 149562[92:SSi:149561.0,78182.0,78186.0,137748.0,149056.0,149552.0] || -> . % 76.16/76.34 149563[92:Spt:149562.0,149557.0,149559.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.34 149564[92:Spt:149562.0,149557.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 149568[92:Res:149564.0,61.1] always3(s27) || -> . % 76.16/76.35 149569[92:SSi:149568.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.35 149570[90:Spt:149569.0,149055.0,149056.0] || until2p7(s26)*+ -> . % 76.16/76.35 149571[90:Spt:149569.0,149055.1] || -> node4(s25)*. % 76.16/76.35 149573[90:MRR:843.0,149571.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.35 149576[90:Res:53.1,149573.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.35 149578[91:Spt:149576.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 149580[91:Res:149578.0,61.1] always3(s25) || -> . % 76.16/76.35 149581[91:SSi:149580.0,78178.0,78181.0,137747.0,149054.0,149571.0] || -> . % 76.16/76.35 149582[91:Spt:149581.0,149576.0,149578.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.35 149583[91:Spt:149581.0,149576.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 149587[91:Res:149583.0,61.1] always3(s26) || -> . % 76.16/76.35 149588[91:SSi:149587.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.35 149589[89:Spt:149588.0,149053.0,149054.0] || until2p7(s25)*+ -> . % 76.16/76.35 149590[89:Spt:149588.0,149053.1] || -> node4(s24)*. % 76.16/76.35 149592[89:MRR:846.0,149590.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.35 149595[89:Res:53.1,149592.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.35 149597[90:Spt:149595.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 149599[90:Res:149597.0,61.1] always3(s24) || -> . % 76.16/76.35 149600[90:SSi:149599.0,78173.0,78177.0,137746.0,149052.0,149590.0] || -> . % 76.16/76.35 149601[90:Spt:149600.0,149595.0,149597.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.35 149602[90:Spt:149600.0,149595.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 149606[90:Res:149602.0,61.1] always3(s25) || -> . % 76.16/76.35 149607[90:SSi:149606.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.35 149608[88:Spt:149607.0,149051.0,149052.0] || until2p7(s24)*+ -> . % 76.16/76.35 149609[88:Spt:149607.0,149051.1] || -> node4(s23)*. % 76.16/76.35 149611[88:MRR:849.0,149609.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.35 149614[88:Res:53.1,149611.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.35 149619[89:Spt:149614.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 149621[89:Res:149619.0,61.1] always3(s23) || -> . % 76.16/76.35 149622[89:SSi:149621.0,78169.0,78172.0,137745.0,149050.0,149609.0] || -> . % 76.16/76.35 149623[89:Spt:149622.0,149614.0,149619.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.35 149624[89:Spt:149622.0,149614.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 149628[89:Res:149624.0,61.1] always3(s24) || -> . % 76.16/76.35 149629[89:SSi:149628.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.35 149630[87:Spt:149629.0,149049.0,149050.0] || until2p7(s23)*+ -> . % 76.16/76.35 149631[87:Spt:149629.0,149049.1] || -> node4(s22)*. % 76.16/76.35 149633[87:MRR:852.0,149631.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.35 149636[87:Res:53.1,149633.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.35 149638[88:Spt:149636.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 149640[88:Res:149638.0,61.1] always3(s22) || -> . % 76.16/76.35 149641[88:SSi:149640.0,78164.0,78168.0,137744.0,149048.0,149631.0] || -> . % 76.16/76.35 149642[88:Spt:149641.0,149636.0,149638.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.35 149643[88:Spt:149641.0,149636.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 149647[88:Res:149643.0,61.1] always3(s23) || -> . % 76.16/76.35 149648[88:SSi:149647.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.35 149649[86:Spt:149648.0,149047.0,149048.0] || until2p7(s22)*+ -> . % 76.16/76.35 149650[86:Spt:149648.0,149047.1] || -> node4(s21)*. % 76.16/76.35 149652[86:MRR:855.0,149650.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.35 149655[86:Res:53.1,149652.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.35 149657[87:Spt:149655.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 149659[87:Res:149657.0,61.1] always3(s21) || -> . % 76.16/76.35 149660[87:SSi:149659.0,78160.0,78163.0,137743.0,149046.0,149650.0] || -> . % 76.16/76.35 149661[87:Spt:149660.0,149655.0,149657.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.35 149662[87:Spt:149660.0,149655.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 149666[87:Res:149662.0,61.1] always3(s22) || -> . % 76.16/76.35 149667[87:SSi:149666.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.35 149668[85:Spt:149667.0,149045.0,149046.0] || until2p7(s21)*+ -> . % 76.16/76.35 149669[85:Spt:149667.0,149045.1] || -> node4(s20)*. % 76.16/76.35 149671[85:MRR:858.0,149669.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.35 149674[85:Res:53.1,149671.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.35 149676[85:MRR:149674.0,149035.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 149678[85:Res:149676.0,61.1] always3(s21) || -> . % 76.16/76.35 149679[85:SSi:149678.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.35 149680[83:Spt:149679.0,148921.0,148924.0] || trans(s49,s20)*+ -> . % 76.16/76.35 149681[83:Spt:149679.0,148921.1,148921.2,148921.3,148921.4,148921.5,148921.6,148921.7,148921.8,148921.9,148921.10,148921.11,148921.12,148921.13,148921.14,148921.15,148921.16] || -> trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.35 149683[83:MRR:148923.1,149680.0] xuntil6(s49) || -> trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.35 149684[84:Spt:149681.0] || -> trans(s49,s19)*. % 76.16/76.35 149685[84:Res:149684.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s19)*. % 76.16/76.35 149687[84:Res:149684.0,60.0] || -> node2(s49,s19)*. % 76.16/76.35 149688[84:SSi:149685.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s19)*. % 76.16/76.35 149689[84:Res:149687.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 149791[84:SoR:149689.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 149793[84:SoR:149791.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)* xuntil6(s49). % 76.16/76.35 149794[84:SSi:149793.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s19,c_busy)* xuntil6(s49). % 76.16/76.35 149795[85:Spt:149794.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 149797[85:Res:149795.0,61.1] always3(s19) || -> . % 76.16/76.35 149798[85:SSi:149797.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.35 149799[85:Spt:149798.0,149794.1,149795.0] || m_main_v_state(s19,c_busy)*+ -> . % 76.16/76.35 149800[85:Spt:149798.0,149794.0,149794.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.35 149804[85:MRR:149791.2,149799.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.35 149805[85:Res:53.1,149800.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.35 149807[85:MRR:149805.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.35 149808[85:MRR:149688.0,149807.0] || -> until2p7(s19)*. % 76.16/76.35 149809[85:MRR:215.0,149808.0] || -> until2p7(s20)* node4(s19). % 76.16/76.35 149810[86:Spt:149809.0] || -> until2p7(s20)*. % 76.16/76.35 149811[86:MRR:216.0,149810.0] || -> until2p7(s21)* node4(s20). % 76.16/76.35 149812[87:Spt:149811.0] || -> until2p7(s21)*. % 76.16/76.35 149813[87:MRR:217.0,149812.0] || -> until2p7(s22)* node4(s21). % 76.16/76.35 149814[88:Spt:149813.0] || -> until2p7(s22)*. % 76.16/76.35 149815[88:MRR:218.0,149814.0] || -> until2p7(s23)* node4(s22). % 76.16/76.35 149816[89:Spt:149815.0] || -> until2p7(s23)*. % 76.16/76.35 149817[89:MRR:219.0,149816.0] || -> until2p7(s24)* node4(s23). % 76.16/76.35 149818[90:Spt:149817.0] || -> until2p7(s24)*. % 76.16/76.35 149819[90:MRR:220.0,149818.0] || -> until2p7(s25)* node4(s24). % 76.16/76.35 149820[91:Spt:149819.0] || -> until2p7(s25)*. % 76.16/76.35 149821[91:MRR:221.0,149820.0] || -> until2p7(s26)* node4(s25). % 76.16/76.35 149822[92:Spt:149821.0] || -> until2p7(s26)*. % 76.16/76.35 149823[92:MRR:222.0,149822.0] || -> until2p7(s27)* node4(s26). % 76.16/76.35 149824[93:Spt:149823.0] || -> until2p7(s27)*. % 76.16/76.35 149825[93:MRR:223.0,149824.0] || -> until2p7(s28)* node4(s27). % 76.16/76.35 149826[94:Spt:149825.0] || -> until2p7(s28)*. % 76.16/76.35 149827[94:MRR:224.0,149826.0] || -> until2p7(s29)* node4(s28). % 76.16/76.35 149828[95:Spt:149827.0] || -> until2p7(s29)*. % 76.16/76.35 149829[95:MRR:225.0,149828.0] || -> until2p7(s30)* node4(s29). % 76.16/76.35 149830[96:Spt:149829.0] || -> until2p7(s30)*. % 76.16/76.35 149831[96:MRR:226.0,149830.0] || -> until2p7(s31)* node4(s30). % 76.16/76.35 149832[97:Spt:149831.0] || -> until2p7(s31)*. % 76.16/76.35 149833[97:MRR:227.0,149832.0] || -> until2p7(s32)* node4(s31). % 76.16/76.35 149834[98:Spt:149833.0] || -> until2p7(s32)*. % 76.16/76.35 149835[98:MRR:228.0,149834.0] || -> until2p7(s33)* node4(s32). % 76.16/76.35 149836[99:Spt:149835.0] || -> until2p7(s33)*. % 76.16/76.35 149837[99:MRR:229.0,149836.0] || -> until2p7(s34)* node4(s33). % 76.16/76.35 149838[100:Spt:149837.0] || -> until2p7(s34)*. % 76.16/76.35 149839[100:MRR:230.0,149838.0] || -> until2p7(s35)* node4(s34). % 76.16/76.35 149840[101:Spt:149839.0] || -> until2p7(s35)*. % 76.16/76.35 149841[101:MRR:231.0,149840.0] || -> until2p7(s36)* node4(s35). % 76.16/76.35 149842[102:Spt:149841.0] || -> until2p7(s36)*. % 76.16/76.35 149843[102:MRR:232.0,149842.0] || -> until2p7(s37)* node4(s36). % 76.16/76.35 149844[103:Spt:149843.0] || -> until2p7(s37)*. % 76.16/76.35 149845[103:MRR:235.0,149844.0] || -> until2p7(s38)* node4(s37). % 76.16/76.35 149846[104:Spt:149845.0] || -> until2p7(s38)*. % 76.16/76.35 149847[104:MRR:236.0,149846.0] || -> until2p7(s39)* node4(s38). % 76.16/76.35 149848[105:Spt:149847.0] || -> until2p7(s39)*. % 76.16/76.35 149849[105:MRR:237.0,149848.0] || -> until2p7(s40)* node4(s39). % 76.16/76.35 149850[106:Spt:149849.0] || -> until2p7(s40)*. % 76.16/76.35 149851[106:MRR:238.0,149850.0] || -> until2p7(s41)* node4(s40). % 76.16/76.35 149852[107:Spt:149851.0] || -> until2p7(s41)*. % 76.16/76.35 149853[107:MRR:239.0,149852.0] || -> until2p7(s42)* node4(s41). % 76.16/76.35 149854[108:Spt:149853.0] || -> until2p7(s42)*. % 76.16/76.35 149855[108:MRR:240.0,149854.0] || -> until2p7(s43)* node4(s42). % 76.16/76.35 149856[109:Spt:149855.0] || -> until2p7(s43)*. % 76.16/76.35 149857[109:MRR:241.0,149856.0] || -> until2p7(s44)* node4(s43). % 76.16/76.35 149858[110:Spt:149857.0] || -> until2p7(s44)*. % 76.16/76.35 149859[110:MRR:539.0,149858.0] || -> until2p7(s45)* node4(s44). % 76.16/76.35 149860[111:Spt:149859.0] || -> until2p7(s45)*. % 76.16/76.35 149861[111:MRR:544.0,149860.0] || -> until2p7(s46)* node4(s45). % 76.16/76.35 149862[112:Spt:149861.0] || -> until2p7(s46)*. % 76.16/76.35 149863[112:MRR:549.0,149862.0] || -> until2p7(s47)* node4(s46). % 76.16/76.35 149864[113:Spt:149863.0] || -> until2p7(s47)*. % 76.16/76.35 149865[113:MRR:554.0,149864.0] || -> until2p7(s48)* node4(s47). % 76.16/76.35 149866[114:Spt:149865.0] || -> until2p7(s48)*. % 76.16/76.35 149867[114:MRR:559.0,149866.0] || -> until2p7(s49)* node4(s48). % 76.16/76.35 149868[115:Spt:149867.0] || -> until2p7(s49)*. % 76.16/76.35 149869[115:MRR:194.0,149868.0] || -> node4(s49)*. % 76.16/76.35 149870[115:MRR:149804.0,149869.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.35 149871[115:Res:53.1,149870.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.35 149873[115:MRR:149871.0,78381.0] || -> . % 76.16/76.35 149874[115:Spt:149873.0,149867.0,149868.0] || until2p7(s49)*+ -> . % 76.16/76.35 149875[115:Spt:149873.0,149867.1] || -> node4(s48)*. % 76.16/76.35 149876[115:MRR:78384.0,149875.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.35 149879[115:Res:53.1,149876.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 149882[115:Res:149879.0,61.1] always3(s48) || -> . % 76.16/76.35 149883[115:SSi:149882.0,78281.0,78387.0,137770.0,149866.0,149875.0] || -> . % 76.16/76.35 149884[114:Spt:149883.0,149865.0,149866.0] || until2p7(s48)*+ -> . % 76.16/76.35 149885[114:Spt:149883.0,149865.1] || -> node4(s47)*. % 76.16/76.35 149887[114:MRR:777.0,149885.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.35 149902[114:Res:53.1,149887.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.35 149904[115:Spt:149902.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 149906[115:Res:149904.0,61.1] always3(s47) || -> . % 76.16/76.35 149907[115:SSi:149906.0,78277.0,78280.0,137769.0,149864.0,149885.0] || -> . % 76.16/76.35 149908[115:Spt:149907.0,149902.0,149904.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.35 149909[115:Spt:149907.0,149902.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 149913[115:Res:149909.0,61.1] always3(s48) || -> . % 76.16/76.35 149914[115:SSi:149913.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.35 149915[113:Spt:149914.0,149863.0,149864.0] || until2p7(s47)*+ -> . % 76.16/76.35 149916[113:Spt:149914.0,149863.1] || -> node4(s46)*. % 76.16/76.35 149918[113:MRR:780.0,149916.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.35 149928[113:Res:53.1,149918.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.35 149930[114:Spt:149928.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 149932[114:Res:149930.0,61.1] always3(s46) || -> . % 76.16/76.35 149933[114:SSi:149932.0,78272.0,78276.0,137768.0,149862.0,149916.0] || -> . % 76.16/76.35 149934[114:Spt:149933.0,149928.0,149930.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.35 149935[114:Spt:149933.0,149928.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 149939[114:Res:149935.0,61.1] always3(s47) || -> . % 76.16/76.35 149940[114:SSi:149939.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.35 149941[112:Spt:149940.0,149861.0,149862.0] || until2p7(s46)*+ -> . % 76.16/76.35 149942[112:Spt:149940.0,149861.1] || -> node4(s45)*. % 76.16/76.35 149944[112:MRR:783.0,149942.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.35 149947[112:Res:53.1,149944.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.35 149949[113:Spt:149947.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 149951[113:Res:149949.0,61.1] always3(s45) || -> . % 76.16/76.35 149952[113:SSi:149951.0,78268.0,78271.0,137767.0,149860.0,149942.0] || -> . % 76.16/76.35 149953[113:Spt:149952.0,149947.0,149949.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.35 149954[113:Spt:149952.0,149947.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 149958[113:Res:149954.0,61.1] always3(s46) || -> . % 76.16/76.35 149959[113:SSi:149958.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.35 149960[111:Spt:149959.0,149859.0,149860.0] || until2p7(s45)*+ -> . % 76.16/76.35 149961[111:Spt:149959.0,149859.1] || -> node4(s44)*. % 76.16/76.35 149963[111:MRR:786.0,149961.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.35 149966[111:Res:53.1,149963.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.35 149968[112:Spt:149966.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 149970[112:Res:149968.0,61.1] always3(s44) || -> . % 76.16/76.35 149971[112:SSi:149970.0,78263.0,78267.0,137766.0,149858.0,149961.0] || -> . % 76.16/76.35 149972[112:Spt:149971.0,149966.0,149968.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.35 149973[112:Spt:149971.0,149966.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 149977[112:Res:149973.0,61.1] always3(s45) || -> . % 76.16/76.35 149978[112:SSi:149977.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.35 149979[110:Spt:149978.0,149857.0,149858.0] || until2p7(s44)*+ -> . % 76.16/76.35 149980[110:Spt:149978.0,149857.1] || -> node4(s43)*. % 76.16/76.35 149982[110:MRR:789.0,149980.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.35 149985[110:Res:53.1,149982.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.35 149990[111:Spt:149985.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 149992[111:Res:149990.0,61.1] always3(s43) || -> . % 76.16/76.35 149993[111:SSi:149992.0,78259.0,78262.0,137765.0,149856.0,149980.0] || -> . % 76.16/76.35 149994[111:Spt:149993.0,149985.0,149990.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.35 149995[111:Spt:149993.0,149985.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 149999[111:Res:149995.0,61.1] always3(s44) || -> . % 76.16/76.35 150000[111:SSi:149999.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.35 150001[109:Spt:150000.0,149855.0,149856.0] || until2p7(s43)*+ -> . % 76.16/76.35 150002[109:Spt:150000.0,149855.1] || -> node4(s42)*. % 76.16/76.35 150004[109:MRR:792.0,150002.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.35 150007[109:Res:53.1,150004.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.35 150009[110:Spt:150007.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 150011[110:Res:150009.0,61.1] always3(s42) || -> . % 76.16/76.35 150012[110:SSi:150011.0,78254.0,78258.0,137764.0,149854.0,150002.0] || -> . % 76.16/76.35 150013[110:Spt:150012.0,150007.0,150009.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.35 150014[110:Spt:150012.0,150007.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 150018[110:Res:150014.0,61.1] always3(s43) || -> . % 76.16/76.35 150019[110:SSi:150018.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.35 150020[108:Spt:150019.0,149853.0,149854.0] || until2p7(s42)*+ -> . % 76.16/76.35 150021[108:Spt:150019.0,149853.1] || -> node4(s41)*. % 76.16/76.35 150023[108:MRR:795.0,150021.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.35 150026[108:Res:53.1,150023.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.35 150028[109:Spt:150026.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 150030[109:Res:150028.0,61.1] always3(s41) || -> . % 76.16/76.35 150031[109:SSi:150030.0,78250.0,78253.0,137763.0,149852.0,150021.0] || -> . % 76.16/76.35 150032[109:Spt:150031.0,150026.0,150028.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.35 150033[109:Spt:150031.0,150026.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 150037[109:Res:150033.0,61.1] always3(s42) || -> . % 76.16/76.35 150038[109:SSi:150037.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.35 150039[107:Spt:150038.0,149851.0,149852.0] || until2p7(s41)*+ -> . % 76.16/76.35 150040[107:Spt:150038.0,149851.1] || -> node4(s40)*. % 76.16/76.35 150042[107:MRR:798.0,150040.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.35 150045[107:Res:53.1,150042.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.35 150047[108:Spt:150045.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 150049[108:Res:150047.0,61.1] always3(s40) || -> . % 76.16/76.35 150050[108:SSi:150049.0,78245.0,78249.0,137762.0,149850.0,150040.0] || -> . % 76.16/76.35 150051[108:Spt:150050.0,150045.0,150047.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.35 150052[108:Spt:150050.0,150045.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 150056[108:Res:150052.0,61.1] always3(s41) || -> . % 76.16/76.35 150057[108:SSi:150056.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.35 150058[106:Spt:150057.0,149849.0,149850.0] || until2p7(s40)*+ -> . % 76.16/76.35 150059[106:Spt:150057.0,149849.1] || -> node4(s39)*. % 76.16/76.35 150061[106:MRR:801.0,150059.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.35 150064[106:Res:53.1,150061.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.35 150069[107:Spt:150064.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 150071[107:Res:150069.0,61.1] always3(s39) || -> . % 76.16/76.35 150072[107:SSi:150071.0,78241.0,78244.0,137761.0,149848.0,150059.0] || -> . % 76.16/76.35 150073[107:Spt:150072.0,150064.0,150069.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.35 150074[107:Spt:150072.0,150064.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 150078[107:Res:150074.0,61.1] always3(s40) || -> . % 76.16/76.35 150079[107:SSi:150078.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.35 150080[105:Spt:150079.0,149847.0,149848.0] || until2p7(s39)*+ -> . % 76.16/76.35 150081[105:Spt:150079.0,149847.1] || -> node4(s38)*. % 76.16/76.35 150083[105:MRR:804.0,150081.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.35 150086[105:Res:53.1,150083.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.35 150088[106:Spt:150086.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 150090[106:Res:150088.0,61.1] always3(s38) || -> . % 76.16/76.35 150091[106:SSi:150090.0,78236.0,78240.0,137760.0,149846.0,150081.0] || -> . % 76.16/76.35 150092[106:Spt:150091.0,150086.0,150088.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.35 150093[106:Spt:150091.0,150086.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 150097[106:Res:150093.0,61.1] always3(s39) || -> . % 76.16/76.35 150098[106:SSi:150097.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.35 150099[104:Spt:150098.0,149845.0,149846.0] || until2p7(s38)*+ -> . % 76.16/76.35 150100[104:Spt:150098.0,149845.1] || -> node4(s37)*. % 76.16/76.35 150102[104:MRR:807.0,150100.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.35 150105[104:Res:53.1,150102.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.35 150107[105:Spt:150105.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 150109[105:Res:150107.0,61.1] always3(s37) || -> . % 76.16/76.35 150110[105:SSi:150109.0,78232.0,78235.0,137759.0,149844.0,150100.0] || -> . % 76.16/76.35 150111[105:Spt:150110.0,150105.0,150107.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.35 150112[105:Spt:150110.0,150105.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 150116[105:Res:150112.0,61.1] always3(s38) || -> . % 76.16/76.35 150117[105:SSi:150116.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.35 150118[103:Spt:150117.0,149843.0,149844.0] || until2p7(s37)*+ -> . % 76.16/76.35 150119[103:Spt:150117.0,149843.1] || -> node4(s36)*. % 76.16/76.35 150121[103:MRR:810.0,150119.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.35 150124[103:Res:53.1,150121.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.35 150126[104:Spt:150124.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 150128[104:Res:150126.0,61.1] always3(s36) || -> . % 76.16/76.35 150129[104:SSi:150128.0,78227.0,78231.0,137758.0,149842.0,150119.0] || -> . % 76.16/76.35 150130[104:Spt:150129.0,150124.0,150126.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.35 150131[104:Spt:150129.0,150124.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 150135[104:Res:150131.0,61.1] always3(s37) || -> . % 76.16/76.35 150136[104:SSi:150135.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.35 150137[102:Spt:150136.0,149841.0,149842.0] || until2p7(s36)*+ -> . % 76.16/76.35 150138[102:Spt:150136.0,149841.1] || -> node4(s35)*. % 76.16/76.35 150140[102:MRR:813.0,150138.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.35 150143[102:Res:53.1,150140.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.35 150148[103:Spt:150143.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 150150[103:Res:150148.0,61.1] always3(s35) || -> . % 76.16/76.35 150151[103:SSi:150150.0,78223.0,78226.0,137757.0,149840.0,150138.0] || -> . % 76.16/76.35 150152[103:Spt:150151.0,150143.0,150148.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.35 150153[103:Spt:150151.0,150143.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 150157[103:Res:150153.0,61.1] always3(s36) || -> . % 76.16/76.35 150158[103:SSi:150157.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.35 150159[101:Spt:150158.0,149839.0,149840.0] || until2p7(s35)*+ -> . % 76.16/76.35 150160[101:Spt:150158.0,149839.1] || -> node4(s34)*. % 76.16/76.35 150162[101:MRR:816.0,150160.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.35 150165[101:Res:53.1,150162.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.35 150167[102:Spt:150165.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 150169[102:Res:150167.0,61.1] always3(s34) || -> . % 76.16/76.35 150170[102:SSi:150169.0,78218.0,78222.0,137756.0,149838.0,150160.0] || -> . % 76.16/76.35 150171[102:Spt:150170.0,150165.0,150167.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.35 150172[102:Spt:150170.0,150165.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 150176[102:Res:150172.0,61.1] always3(s35) || -> . % 76.16/76.35 150177[102:SSi:150176.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.35 150178[100:Spt:150177.0,149837.0,149838.0] || until2p7(s34)*+ -> . % 76.16/76.35 150179[100:Spt:150177.0,149837.1] || -> node4(s33)*. % 76.16/76.35 150181[100:MRR:819.0,150179.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.35 150184[100:Res:53.1,150181.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.35 150186[101:Spt:150184.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 150188[101:Res:150186.0,61.1] always3(s33) || -> . % 76.16/76.35 150189[101:SSi:150188.0,78214.0,78217.0,137755.0,149836.0,150179.0] || -> . % 76.16/76.35 150190[101:Spt:150189.0,150184.0,150186.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.35 150191[101:Spt:150189.0,150184.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 150195[101:Res:150191.0,61.1] always3(s34) || -> . % 76.16/76.35 150196[101:SSi:150195.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.35 150197[99:Spt:150196.0,149835.0,149836.0] || until2p7(s33)*+ -> . % 76.16/76.35 150198[99:Spt:150196.0,149835.1] || -> node4(s32)*. % 76.16/76.35 150200[99:MRR:822.0,150198.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.35 150203[99:Res:53.1,150200.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.35 150205[100:Spt:150203.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 150207[100:Res:150205.0,61.1] always3(s32) || -> . % 76.16/76.35 150208[100:SSi:150207.0,78209.0,78213.0,137754.0,149834.0,150198.0] || -> . % 76.16/76.35 150209[100:Spt:150208.0,150203.0,150205.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.35 150210[100:Spt:150208.0,150203.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 150214[100:Res:150210.0,61.1] always3(s33) || -> . % 76.16/76.35 150215[100:SSi:150214.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.35 150216[98:Spt:150215.0,149833.0,149834.0] || until2p7(s32)*+ -> . % 76.16/76.35 150217[98:Spt:150215.0,149833.1] || -> node4(s31)*. % 76.16/76.35 150219[98:MRR:825.0,150217.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.35 150222[98:Res:53.1,150219.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.35 150227[99:Spt:150222.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 150229[99:Res:150227.0,61.1] always3(s31) || -> . % 76.16/76.35 150230[99:SSi:150229.0,78205.0,78208.0,137753.0,149832.0,150217.0] || -> . % 76.16/76.35 150231[99:Spt:150230.0,150222.0,150227.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.35 150232[99:Spt:150230.0,150222.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 150236[99:Res:150232.0,61.1] always3(s32) || -> . % 76.16/76.35 150237[99:SSi:150236.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.35 150238[97:Spt:150237.0,149831.0,149832.0] || until2p7(s31)*+ -> . % 76.16/76.35 150239[97:Spt:150237.0,149831.1] || -> node4(s30)*. % 76.16/76.35 150241[97:MRR:828.0,150239.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.35 150244[97:Res:53.1,150241.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.35 150246[98:Spt:150244.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 150248[98:Res:150246.0,61.1] always3(s30) || -> . % 76.16/76.35 150249[98:SSi:150248.0,78200.0,78204.0,137752.0,149830.0,150239.0] || -> . % 76.16/76.35 150250[98:Spt:150249.0,150244.0,150246.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.35 150251[98:Spt:150249.0,150244.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 150255[98:Res:150251.0,61.1] always3(s31) || -> . % 76.16/76.35 150256[98:SSi:150255.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.35 150257[96:Spt:150256.0,149829.0,149830.0] || until2p7(s30)*+ -> . % 76.16/76.35 150258[96:Spt:150256.0,149829.1] || -> node4(s29)*. % 76.16/76.35 150260[96:MRR:831.0,150258.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.35 150263[96:Res:53.1,150260.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.35 150265[97:Spt:150263.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 150267[97:Res:150265.0,61.1] always3(s29) || -> . % 76.16/76.35 150268[97:SSi:150267.0,78196.0,78199.0,137751.0,149828.0,150258.0] || -> . % 76.16/76.35 150269[97:Spt:150268.0,150263.0,150265.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.35 150270[97:Spt:150268.0,150263.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 150274[97:Res:150270.0,61.1] always3(s30) || -> . % 76.16/76.35 150275[97:SSi:150274.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.35 150276[95:Spt:150275.0,149827.0,149828.0] || until2p7(s29)*+ -> . % 76.16/76.35 150277[95:Spt:150275.0,149827.1] || -> node4(s28)*. % 76.16/76.35 150279[95:MRR:834.0,150277.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.35 150282[95:Res:53.1,150279.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.35 150284[96:Spt:150282.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 150286[96:Res:150284.0,61.1] always3(s28) || -> . % 76.16/76.35 150287[96:SSi:150286.0,78191.0,78195.0,137750.0,149826.0,150277.0] || -> . % 76.16/76.35 150288[96:Spt:150287.0,150282.0,150284.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.35 150289[96:Spt:150287.0,150282.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 150293[96:Res:150289.0,61.1] always3(s29) || -> . % 76.16/76.35 150294[96:SSi:150293.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.35 150295[94:Spt:150294.0,149825.0,149826.0] || until2p7(s28)*+ -> . % 76.16/76.35 150296[94:Spt:150294.0,149825.1] || -> node4(s27)*. % 76.16/76.35 150298[94:MRR:837.0,150296.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.35 150301[94:Res:53.1,150298.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.35 150306[95:Spt:150301.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 150308[95:Res:150306.0,61.1] always3(s27) || -> . % 76.16/76.35 150309[95:SSi:150308.0,78187.0,78190.0,137749.0,149824.0,150296.0] || -> . % 76.16/76.35 150310[95:Spt:150309.0,150301.0,150306.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.35 150311[95:Spt:150309.0,150301.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 150315[95:Res:150311.0,61.1] always3(s28) || -> . % 76.16/76.35 150316[95:SSi:150315.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.35 150317[93:Spt:150316.0,149823.0,149824.0] || until2p7(s27)*+ -> . % 76.16/76.35 150318[93:Spt:150316.0,149823.1] || -> node4(s26)*. % 76.16/76.35 150320[93:MRR:840.0,150318.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.35 150323[93:Res:53.1,150320.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.35 150325[94:Spt:150323.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 150327[94:Res:150325.0,61.1] always3(s26) || -> . % 76.16/76.35 150328[94:SSi:150327.0,78182.0,78186.0,137748.0,149822.0,150318.0] || -> . % 76.16/76.35 150329[94:Spt:150328.0,150323.0,150325.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.35 150330[94:Spt:150328.0,150323.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 150334[94:Res:150330.0,61.1] always3(s27) || -> . % 76.16/76.35 150335[94:SSi:150334.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.35 150336[92:Spt:150335.0,149821.0,149822.0] || until2p7(s26)*+ -> . % 76.16/76.35 150337[92:Spt:150335.0,149821.1] || -> node4(s25)*. % 76.16/76.35 150339[92:MRR:843.0,150337.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.35 150342[92:Res:53.1,150339.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.35 150344[93:Spt:150342.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 150346[93:Res:150344.0,61.1] always3(s25) || -> . % 76.16/76.35 150347[93:SSi:150346.0,78178.0,78181.0,137747.0,149820.0,150337.0] || -> . % 76.16/76.35 150348[93:Spt:150347.0,150342.0,150344.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.35 150349[93:Spt:150347.0,150342.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 150353[93:Res:150349.0,61.1] always3(s26) || -> . % 76.16/76.35 150354[93:SSi:150353.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.35 150355[91:Spt:150354.0,149819.0,149820.0] || until2p7(s25)*+ -> . % 76.16/76.35 150356[91:Spt:150354.0,149819.1] || -> node4(s24)*. % 76.16/76.35 150358[91:MRR:846.0,150356.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.35 150361[91:Res:53.1,150358.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.35 150363[92:Spt:150361.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 150365[92:Res:150363.0,61.1] always3(s24) || -> . % 76.16/76.35 150366[92:SSi:150365.0,78173.0,78177.0,137746.0,149818.0,150356.0] || -> . % 76.16/76.35 150367[92:Spt:150366.0,150361.0,150363.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.35 150368[92:Spt:150366.0,150361.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 150372[92:Res:150368.0,61.1] always3(s25) || -> . % 76.16/76.35 150373[92:SSi:150372.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.35 150374[90:Spt:150373.0,149817.0,149818.0] || until2p7(s24)*+ -> . % 76.16/76.35 150375[90:Spt:150373.0,149817.1] || -> node4(s23)*. % 76.16/76.35 150377[90:MRR:849.0,150375.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.35 150380[90:Res:53.1,150377.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.35 150385[91:Spt:150380.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 150387[91:Res:150385.0,61.1] always3(s23) || -> . % 76.16/76.35 150388[91:SSi:150387.0,78169.0,78172.0,137745.0,149816.0,150375.0] || -> . % 76.16/76.35 150389[91:Spt:150388.0,150380.0,150385.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.35 150390[91:Spt:150388.0,150380.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 150394[91:Res:150390.0,61.1] always3(s24) || -> . % 76.16/76.35 150395[91:SSi:150394.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.35 150396[89:Spt:150395.0,149815.0,149816.0] || until2p7(s23)*+ -> . % 76.16/76.35 150397[89:Spt:150395.0,149815.1] || -> node4(s22)*. % 76.16/76.35 150399[89:MRR:852.0,150397.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.35 150402[89:Res:53.1,150399.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.35 150404[90:Spt:150402.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 150406[90:Res:150404.0,61.1] always3(s22) || -> . % 76.16/76.35 150407[90:SSi:150406.0,78164.0,78168.0,137744.0,149814.0,150397.0] || -> . % 76.16/76.35 150408[90:Spt:150407.0,150402.0,150404.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.35 150409[90:Spt:150407.0,150402.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 150413[90:Res:150409.0,61.1] always3(s23) || -> . % 76.16/76.35 150414[90:SSi:150413.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.35 150415[88:Spt:150414.0,149813.0,149814.0] || until2p7(s22)*+ -> . % 76.16/76.35 150416[88:Spt:150414.0,149813.1] || -> node4(s21)*. % 76.16/76.35 150418[88:MRR:855.0,150416.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.35 150421[88:Res:53.1,150418.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.35 150423[89:Spt:150421.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 150425[89:Res:150423.0,61.1] always3(s21) || -> . % 76.16/76.35 150426[89:SSi:150425.0,78160.0,78163.0,137743.0,149812.0,150416.0] || -> . % 76.16/76.35 150427[89:Spt:150426.0,150421.0,150423.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.35 150428[89:Spt:150426.0,150421.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 150432[89:Res:150428.0,61.1] always3(s22) || -> . % 76.16/76.35 150433[89:SSi:150432.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.35 150434[87:Spt:150433.0,149811.0,149812.0] || until2p7(s21)*+ -> . % 76.16/76.35 150435[87:Spt:150433.0,149811.1] || -> node4(s20)*. % 76.16/76.35 150437[87:MRR:858.0,150435.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.35 150440[87:Res:53.1,150437.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.35 150442[88:Spt:150440.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 150444[88:Res:150442.0,61.1] always3(s20) || -> . % 76.16/76.35 150445[88:SSi:150444.0,78155.0,78159.0,137742.0,149810.0,150435.0] || -> . % 76.16/76.35 150446[88:Spt:150445.0,150440.0,150442.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.35 150447[88:Spt:150445.0,150440.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 150451[88:Res:150447.0,61.1] always3(s21) || -> . % 76.16/76.35 150452[88:SSi:150451.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.35 150453[86:Spt:150452.0,149809.0,149810.0] || until2p7(s20)*+ -> . % 76.16/76.35 150454[86:Spt:150452.0,149809.1] || -> node4(s19)*. % 76.16/76.35 150456[86:MRR:861.0,150454.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.35 150459[86:Res:53.1,150456.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.35 150461[86:MRR:150459.0,149799.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 150466[86:Res:150461.0,61.1] always3(s20) || -> . % 76.16/76.35 150467[86:SSi:150466.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.35 150468[84:Spt:150467.0,149681.0,149684.0] || trans(s49,s19)*+ -> . % 76.16/76.35 150469[84:Spt:150467.0,149681.1,149681.2,149681.3,149681.4,149681.5,149681.6,149681.7,149681.8,149681.9,149681.10,149681.11,149681.12,149681.13,149681.14,149681.15] || -> trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.35 150471[84:MRR:149683.1,150468.0] xuntil6(s49) || -> trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.35 150472[85:Spt:150469.0] || -> trans(s49,s18)*. % 76.16/76.35 150473[85:Res:150472.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s18)*. % 76.16/76.35 150475[85:Res:150472.0,60.0] || -> node2(s49,s18)*. % 76.16/76.35 150476[85:SSi:150473.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s18)*. % 76.16/76.35 150477[85:Res:150475.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 150580[85:SoR:150477.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 150582[85:SoR:150580.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)* xuntil6(s49). % 76.16/76.35 150583[85:SSi:150582.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s18,c_busy)* xuntil6(s49). % 76.16/76.35 150584[86:Spt:150583.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 150586[86:Res:150584.0,61.1] always3(s18) || -> . % 76.16/76.35 150587[86:SSi:150586.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.35 150588[86:Spt:150587.0,150583.1,150584.0] || m_main_v_state(s18,c_busy)*+ -> . % 76.16/76.35 150589[86:Spt:150587.0,150583.0,150583.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.35 150593[86:MRR:150580.2,150588.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.35 150594[86:Res:53.1,150589.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.35 150596[86:MRR:150594.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.35 150597[86:MRR:150476.0,150596.0] || -> until2p7(s18)*. % 76.16/76.35 150598[86:MRR:214.0,150597.0] || -> until2p7(s19)* node4(s18). % 76.16/76.35 150599[87:Spt:150598.0] || -> until2p7(s19)*. % 76.16/76.35 150600[87:MRR:215.0,150599.0] || -> until2p7(s20)* node4(s19). % 76.16/76.35 150601[88:Spt:150600.0] || -> until2p7(s20)*. % 76.16/76.35 150602[88:MRR:216.0,150601.0] || -> until2p7(s21)* node4(s20). % 76.16/76.35 150603[89:Spt:150602.0] || -> until2p7(s21)*. % 76.16/76.35 150604[89:MRR:217.0,150603.0] || -> until2p7(s22)* node4(s21). % 76.16/76.35 150605[90:Spt:150604.0] || -> until2p7(s22)*. % 76.16/76.35 150606[90:MRR:218.0,150605.0] || -> until2p7(s23)* node4(s22). % 76.16/76.35 150607[91:Spt:150606.0] || -> until2p7(s23)*. % 76.16/76.35 150608[91:MRR:219.0,150607.0] || -> until2p7(s24)* node4(s23). % 76.16/76.35 150609[92:Spt:150608.0] || -> until2p7(s24)*. % 76.16/76.35 150610[92:MRR:220.0,150609.0] || -> until2p7(s25)* node4(s24). % 76.16/76.35 150611[93:Spt:150610.0] || -> until2p7(s25)*. % 76.16/76.35 150612[93:MRR:221.0,150611.0] || -> until2p7(s26)* node4(s25). % 76.16/76.35 150613[94:Spt:150612.0] || -> until2p7(s26)*. % 76.16/76.35 150614[94:MRR:222.0,150613.0] || -> until2p7(s27)* node4(s26). % 76.16/76.35 150615[95:Spt:150614.0] || -> until2p7(s27)*. % 76.16/76.35 150616[95:MRR:223.0,150615.0] || -> until2p7(s28)* node4(s27). % 76.16/76.35 150617[96:Spt:150616.0] || -> until2p7(s28)*. % 76.16/76.35 150618[96:MRR:224.0,150617.0] || -> until2p7(s29)* node4(s28). % 76.16/76.35 150619[97:Spt:150618.0] || -> until2p7(s29)*. % 76.16/76.35 150620[97:MRR:225.0,150619.0] || -> until2p7(s30)* node4(s29). % 76.16/76.35 150621[98:Spt:150620.0] || -> until2p7(s30)*. % 76.16/76.35 150622[98:MRR:226.0,150621.0] || -> until2p7(s31)* node4(s30). % 76.16/76.35 150623[99:Spt:150622.0] || -> until2p7(s31)*. % 76.16/76.35 150624[99:MRR:227.0,150623.0] || -> until2p7(s32)* node4(s31). % 76.16/76.35 150625[100:Spt:150624.0] || -> until2p7(s32)*. % 76.16/76.35 150626[100:MRR:228.0,150625.0] || -> until2p7(s33)* node4(s32). % 76.16/76.35 150627[101:Spt:150626.0] || -> until2p7(s33)*. % 76.16/76.35 150628[101:MRR:229.0,150627.0] || -> until2p7(s34)* node4(s33). % 76.16/76.35 150629[102:Spt:150628.0] || -> until2p7(s34)*. % 76.16/76.35 150630[102:MRR:230.0,150629.0] || -> until2p7(s35)* node4(s34). % 76.16/76.35 150631[103:Spt:150630.0] || -> until2p7(s35)*. % 76.16/76.35 150632[103:MRR:231.0,150631.0] || -> until2p7(s36)* node4(s35). % 76.16/76.35 150633[104:Spt:150632.0] || -> until2p7(s36)*. % 76.16/76.35 150634[104:MRR:232.0,150633.0] || -> until2p7(s37)* node4(s36). % 76.16/76.35 150635[105:Spt:150634.0] || -> until2p7(s37)*. % 76.16/76.35 150636[105:MRR:235.0,150635.0] || -> until2p7(s38)* node4(s37). % 76.16/76.35 150637[106:Spt:150636.0] || -> until2p7(s38)*. % 76.16/76.35 150638[106:MRR:236.0,150637.0] || -> until2p7(s39)* node4(s38). % 76.16/76.35 150639[107:Spt:150638.0] || -> until2p7(s39)*. % 76.16/76.35 150640[107:MRR:237.0,150639.0] || -> until2p7(s40)* node4(s39). % 76.16/76.35 150641[108:Spt:150640.0] || -> until2p7(s40)*. % 76.16/76.35 150642[108:MRR:238.0,150641.0] || -> until2p7(s41)* node4(s40). % 76.16/76.35 150643[109:Spt:150642.0] || -> until2p7(s41)*. % 76.16/76.35 150644[109:MRR:239.0,150643.0] || -> until2p7(s42)* node4(s41). % 76.16/76.35 150645[110:Spt:150644.0] || -> until2p7(s42)*. % 76.16/76.35 150646[110:MRR:240.0,150645.0] || -> until2p7(s43)* node4(s42). % 76.16/76.35 150647[111:Spt:150646.0] || -> until2p7(s43)*. % 76.16/76.35 150648[111:MRR:241.0,150647.0] || -> until2p7(s44)* node4(s43). % 76.16/76.35 150649[112:Spt:150648.0] || -> until2p7(s44)*. % 76.16/76.35 150650[112:MRR:539.0,150649.0] || -> until2p7(s45)* node4(s44). % 76.16/76.35 150651[113:Spt:150650.0] || -> until2p7(s45)*. % 76.16/76.35 150652[113:MRR:544.0,150651.0] || -> until2p7(s46)* node4(s45). % 76.16/76.35 150653[114:Spt:150652.0] || -> until2p7(s46)*. % 76.16/76.35 150654[114:MRR:549.0,150653.0] || -> until2p7(s47)* node4(s46). % 76.16/76.35 150655[115:Spt:150654.0] || -> until2p7(s47)*. % 76.16/76.35 150656[115:MRR:554.0,150655.0] || -> until2p7(s48)* node4(s47). % 76.16/76.35 150657[116:Spt:150656.0] || -> until2p7(s48)*. % 76.16/76.35 150658[116:MRR:559.0,150657.0] || -> until2p7(s49)* node4(s48). % 76.16/76.35 150659[117:Spt:150658.0] || -> until2p7(s49)*. % 76.16/76.35 150660[117:MRR:194.0,150659.0] || -> node4(s49)*. % 76.16/76.35 150661[117:MRR:150593.0,150660.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.35 150665[117:Res:53.1,150661.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.35 150667[117:MRR:150665.0,78381.0] || -> . % 76.16/76.35 150668[117:Spt:150667.0,150658.0,150659.0] || until2p7(s49)*+ -> . % 76.16/76.35 150669[117:Spt:150667.0,150658.1] || -> node4(s48)*. % 76.16/76.35 150670[117:MRR:78384.0,150669.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.35 150673[117:Res:53.1,150670.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 150676[117:Res:150673.0,61.1] always3(s48) || -> . % 76.16/76.35 150677[117:SSi:150676.0,78281.0,78387.0,137770.0,150657.0,150669.0] || -> . % 76.16/76.35 150678[116:Spt:150677.0,150656.0,150657.0] || until2p7(s48)*+ -> . % 76.16/76.35 150679[116:Spt:150677.0,150656.1] || -> node4(s47)*. % 76.16/76.35 150681[116:MRR:777.0,150679.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.35 150693[116:Res:53.1,150681.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.35 150695[117:Spt:150693.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 150697[117:Res:150695.0,61.1] always3(s47) || -> . % 76.16/76.35 150698[117:SSi:150697.0,78277.0,78280.0,137769.0,150655.0,150679.0] || -> . % 76.16/76.35 150699[117:Spt:150698.0,150693.0,150695.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.35 150700[117:Spt:150698.0,150693.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 150704[117:Res:150700.0,61.1] always3(s48) || -> . % 76.16/76.35 150705[117:SSi:150704.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.35 150706[115:Spt:150705.0,150654.0,150655.0] || until2p7(s47)*+ -> . % 76.16/76.35 150707[115:Spt:150705.0,150654.1] || -> node4(s46)*. % 76.16/76.35 150709[115:MRR:780.0,150707.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.35 150716[115:Res:53.1,150709.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.35 150721[116:Spt:150716.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 150723[116:Res:150721.0,61.1] always3(s46) || -> . % 76.16/76.35 150724[116:SSi:150723.0,78272.0,78276.0,137768.0,150653.0,150707.0] || -> . % 76.16/76.35 150725[116:Spt:150724.0,150716.0,150721.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.35 150726[116:Spt:150724.0,150716.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 150730[116:Res:150726.0,61.1] always3(s47) || -> . % 76.16/76.35 150731[116:SSi:150730.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.35 150732[114:Spt:150731.0,150652.0,150653.0] || until2p7(s46)*+ -> . % 76.16/76.35 150733[114:Spt:150731.0,150652.1] || -> node4(s45)*. % 76.16/76.35 150735[114:MRR:783.0,150733.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.35 150738[114:Res:53.1,150735.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.35 150740[115:Spt:150738.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 150742[115:Res:150740.0,61.1] always3(s45) || -> . % 76.16/76.35 150743[115:SSi:150742.0,78268.0,78271.0,137767.0,150651.0,150733.0] || -> . % 76.16/76.35 150744[115:Spt:150743.0,150738.0,150740.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.35 150745[115:Spt:150743.0,150738.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 150749[115:Res:150745.0,61.1] always3(s46) || -> . % 76.16/76.35 150750[115:SSi:150749.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.35 150751[113:Spt:150750.0,150650.0,150651.0] || until2p7(s45)*+ -> . % 76.16/76.35 150752[113:Spt:150750.0,150650.1] || -> node4(s44)*. % 76.16/76.35 150754[113:MRR:786.0,150752.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.35 150757[113:Res:53.1,150754.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.35 150759[114:Spt:150757.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 150761[114:Res:150759.0,61.1] always3(s44) || -> . % 76.16/76.35 150762[114:SSi:150761.0,78263.0,78267.0,137766.0,150649.0,150752.0] || -> . % 76.16/76.35 150763[114:Spt:150762.0,150757.0,150759.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.35 150764[114:Spt:150762.0,150757.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 150768[114:Res:150764.0,61.1] always3(s45) || -> . % 76.16/76.35 150769[114:SSi:150768.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.35 150770[112:Spt:150769.0,150648.0,150649.0] || until2p7(s44)*+ -> . % 76.16/76.35 150771[112:Spt:150769.0,150648.1] || -> node4(s43)*. % 76.16/76.35 150773[112:MRR:789.0,150771.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.35 150776[112:Res:53.1,150773.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.35 150778[113:Spt:150776.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 150780[113:Res:150778.0,61.1] always3(s43) || -> . % 76.16/76.35 150781[113:SSi:150780.0,78259.0,78262.0,137765.0,150647.0,150771.0] || -> . % 76.16/76.35 150782[113:Spt:150781.0,150776.0,150778.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.35 150783[113:Spt:150781.0,150776.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 150787[113:Res:150783.0,61.1] always3(s44) || -> . % 76.16/76.35 150788[113:SSi:150787.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.35 150789[111:Spt:150788.0,150646.0,150647.0] || until2p7(s43)*+ -> . % 76.16/76.35 150790[111:Spt:150788.0,150646.1] || -> node4(s42)*. % 76.16/76.35 150792[111:MRR:792.0,150790.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.35 150795[111:Res:53.1,150792.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.35 150800[112:Spt:150795.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 150802[112:Res:150800.0,61.1] always3(s42) || -> . % 76.16/76.35 150803[112:SSi:150802.0,78254.0,78258.0,137764.0,150645.0,150790.0] || -> . % 76.16/76.35 150804[112:Spt:150803.0,150795.0,150800.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.35 150805[112:Spt:150803.0,150795.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 150809[112:Res:150805.0,61.1] always3(s43) || -> . % 76.16/76.35 150810[112:SSi:150809.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.35 150811[110:Spt:150810.0,150644.0,150645.0] || until2p7(s42)*+ -> . % 76.16/76.35 150812[110:Spt:150810.0,150644.1] || -> node4(s41)*. % 76.16/76.35 150814[110:MRR:795.0,150812.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.35 150817[110:Res:53.1,150814.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.35 150819[111:Spt:150817.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 150821[111:Res:150819.0,61.1] always3(s41) || -> . % 76.16/76.35 150822[111:SSi:150821.0,78250.0,78253.0,137763.0,150643.0,150812.0] || -> . % 76.16/76.35 150823[111:Spt:150822.0,150817.0,150819.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.35 150824[111:Spt:150822.0,150817.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 150828[111:Res:150824.0,61.1] always3(s42) || -> . % 76.16/76.35 150829[111:SSi:150828.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.35 150830[109:Spt:150829.0,150642.0,150643.0] || until2p7(s41)*+ -> . % 76.16/76.35 150831[109:Spt:150829.0,150642.1] || -> node4(s40)*. % 76.16/76.35 150833[109:MRR:798.0,150831.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.35 150836[109:Res:53.1,150833.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.35 150838[110:Spt:150836.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 150840[110:Res:150838.0,61.1] always3(s40) || -> . % 76.16/76.35 150841[110:SSi:150840.0,78245.0,78249.0,137762.0,150641.0,150831.0] || -> . % 76.16/76.35 150842[110:Spt:150841.0,150836.0,150838.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.35 150843[110:Spt:150841.0,150836.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 150847[110:Res:150843.0,61.1] always3(s41) || -> . % 76.16/76.35 150848[110:SSi:150847.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.35 150849[108:Spt:150848.0,150640.0,150641.0] || until2p7(s40)*+ -> . % 76.16/76.35 150850[108:Spt:150848.0,150640.1] || -> node4(s39)*. % 76.16/76.35 150852[108:MRR:801.0,150850.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.35 150855[108:Res:53.1,150852.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.35 150857[109:Spt:150855.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 150859[109:Res:150857.0,61.1] always3(s39) || -> . % 76.16/76.35 150860[109:SSi:150859.0,78241.0,78244.0,137761.0,150639.0,150850.0] || -> . % 76.16/76.35 150861[109:Spt:150860.0,150855.0,150857.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.35 150862[109:Spt:150860.0,150855.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 150866[109:Res:150862.0,61.1] always3(s40) || -> . % 76.16/76.35 150867[109:SSi:150866.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.35 150868[107:Spt:150867.0,150638.0,150639.0] || until2p7(s39)*+ -> . % 76.16/76.35 150869[107:Spt:150867.0,150638.1] || -> node4(s38)*. % 76.16/76.35 150871[107:MRR:804.0,150869.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.35 150874[107:Res:53.1,150871.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.35 150879[108:Spt:150874.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 150881[108:Res:150879.0,61.1] always3(s38) || -> . % 76.16/76.35 150882[108:SSi:150881.0,78236.0,78240.0,137760.0,150637.0,150869.0] || -> . % 76.16/76.35 150883[108:Spt:150882.0,150874.0,150879.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.35 150884[108:Spt:150882.0,150874.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 150888[108:Res:150884.0,61.1] always3(s39) || -> . % 76.16/76.35 150889[108:SSi:150888.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.35 150890[106:Spt:150889.0,150636.0,150637.0] || until2p7(s38)*+ -> . % 76.16/76.35 150891[106:Spt:150889.0,150636.1] || -> node4(s37)*. % 76.16/76.35 150893[106:MRR:807.0,150891.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.35 150896[106:Res:53.1,150893.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.35 150898[107:Spt:150896.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 150900[107:Res:150898.0,61.1] always3(s37) || -> . % 76.16/76.35 150901[107:SSi:150900.0,78232.0,78235.0,137759.0,150635.0,150891.0] || -> . % 76.16/76.35 150902[107:Spt:150901.0,150896.0,150898.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.35 150903[107:Spt:150901.0,150896.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 150907[107:Res:150903.0,61.1] always3(s38) || -> . % 76.16/76.35 150908[107:SSi:150907.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.35 150909[105:Spt:150908.0,150634.0,150635.0] || until2p7(s37)*+ -> . % 76.16/76.35 150910[105:Spt:150908.0,150634.1] || -> node4(s36)*. % 76.16/76.35 150912[105:MRR:810.0,150910.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.35 150915[105:Res:53.1,150912.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.35 150917[106:Spt:150915.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 150919[106:Res:150917.0,61.1] always3(s36) || -> . % 76.16/76.35 150920[106:SSi:150919.0,78227.0,78231.0,137758.0,150633.0,150910.0] || -> . % 76.16/76.35 150921[106:Spt:150920.0,150915.0,150917.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.35 150922[106:Spt:150920.0,150915.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 150926[106:Res:150922.0,61.1] always3(s37) || -> . % 76.16/76.35 150927[106:SSi:150926.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.35 150928[104:Spt:150927.0,150632.0,150633.0] || until2p7(s36)*+ -> . % 76.16/76.35 150929[104:Spt:150927.0,150632.1] || -> node4(s35)*. % 76.16/76.35 150931[104:MRR:813.0,150929.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.35 150934[104:Res:53.1,150931.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.35 150936[105:Spt:150934.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 150938[105:Res:150936.0,61.1] always3(s35) || -> . % 76.16/76.35 150939[105:SSi:150938.0,78223.0,78226.0,137757.0,150631.0,150929.0] || -> . % 76.16/76.35 150940[105:Spt:150939.0,150934.0,150936.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.35 150941[105:Spt:150939.0,150934.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 150945[105:Res:150941.0,61.1] always3(s36) || -> . % 76.16/76.35 150946[105:SSi:150945.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.35 150947[103:Spt:150946.0,150630.0,150631.0] || until2p7(s35)*+ -> . % 76.16/76.35 150948[103:Spt:150946.0,150630.1] || -> node4(s34)*. % 76.16/76.35 150950[103:MRR:816.0,150948.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.35 150953[103:Res:53.1,150950.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.35 150958[104:Spt:150953.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 150960[104:Res:150958.0,61.1] always3(s34) || -> . % 76.16/76.35 150961[104:SSi:150960.0,78218.0,78222.0,137756.0,150629.0,150948.0] || -> . % 76.16/76.35 150962[104:Spt:150961.0,150953.0,150958.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.35 150963[104:Spt:150961.0,150953.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 150967[104:Res:150963.0,61.1] always3(s35) || -> . % 76.16/76.35 150968[104:SSi:150967.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.35 150969[102:Spt:150968.0,150628.0,150629.0] || until2p7(s34)*+ -> . % 76.16/76.35 150970[102:Spt:150968.0,150628.1] || -> node4(s33)*. % 76.16/76.35 150972[102:MRR:819.0,150970.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.35 150975[102:Res:53.1,150972.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.35 150977[103:Spt:150975.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 150979[103:Res:150977.0,61.1] always3(s33) || -> . % 76.16/76.35 150980[103:SSi:150979.0,78214.0,78217.0,137755.0,150627.0,150970.0] || -> . % 76.16/76.35 150981[103:Spt:150980.0,150975.0,150977.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.35 150982[103:Spt:150980.0,150975.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 150986[103:Res:150982.0,61.1] always3(s34) || -> . % 76.16/76.35 150987[103:SSi:150986.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.35 150988[101:Spt:150987.0,150626.0,150627.0] || until2p7(s33)*+ -> . % 76.16/76.35 150989[101:Spt:150987.0,150626.1] || -> node4(s32)*. % 76.16/76.35 150991[101:MRR:822.0,150989.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.35 150994[101:Res:53.1,150991.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.35 150996[102:Spt:150994.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 150998[102:Res:150996.0,61.1] always3(s32) || -> . % 76.16/76.35 150999[102:SSi:150998.0,78209.0,78213.0,137754.0,150625.0,150989.0] || -> . % 76.16/76.35 151000[102:Spt:150999.0,150994.0,150996.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.35 151001[102:Spt:150999.0,150994.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 151005[102:Res:151001.0,61.1] always3(s33) || -> . % 76.16/76.35 151006[102:SSi:151005.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.35 151007[100:Spt:151006.0,150624.0,150625.0] || until2p7(s32)*+ -> . % 76.16/76.35 151008[100:Spt:151006.0,150624.1] || -> node4(s31)*. % 76.16/76.35 151010[100:MRR:825.0,151008.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.35 151013[100:Res:53.1,151010.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.35 151015[101:Spt:151013.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 151017[101:Res:151015.0,61.1] always3(s31) || -> . % 76.16/76.35 151018[101:SSi:151017.0,78205.0,78208.0,137753.0,150623.0,151008.0] || -> . % 76.16/76.35 151019[101:Spt:151018.0,151013.0,151015.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.35 151020[101:Spt:151018.0,151013.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 151024[101:Res:151020.0,61.1] always3(s32) || -> . % 76.16/76.35 151025[101:SSi:151024.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.35 151026[99:Spt:151025.0,150622.0,150623.0] || until2p7(s31)*+ -> . % 76.16/76.35 151027[99:Spt:151025.0,150622.1] || -> node4(s30)*. % 76.16/76.35 151029[99:MRR:828.0,151027.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.35 151032[99:Res:53.1,151029.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.35 151037[100:Spt:151032.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 151039[100:Res:151037.0,61.1] always3(s30) || -> . % 76.16/76.35 151040[100:SSi:151039.0,78200.0,78204.0,137752.0,150621.0,151027.0] || -> . % 76.16/76.35 151041[100:Spt:151040.0,151032.0,151037.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.35 151042[100:Spt:151040.0,151032.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 151046[100:Res:151042.0,61.1] always3(s31) || -> . % 76.16/76.35 151047[100:SSi:151046.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.35 151048[98:Spt:151047.0,150620.0,150621.0] || until2p7(s30)*+ -> . % 76.16/76.35 151049[98:Spt:151047.0,150620.1] || -> node4(s29)*. % 76.16/76.35 151051[98:MRR:831.0,151049.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.35 151054[98:Res:53.1,151051.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.35 151056[99:Spt:151054.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 151058[99:Res:151056.0,61.1] always3(s29) || -> . % 76.16/76.35 151059[99:SSi:151058.0,78196.0,78199.0,137751.0,150619.0,151049.0] || -> . % 76.16/76.35 151060[99:Spt:151059.0,151054.0,151056.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.35 151061[99:Spt:151059.0,151054.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 151065[99:Res:151061.0,61.1] always3(s30) || -> . % 76.16/76.35 151066[99:SSi:151065.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.35 151067[97:Spt:151066.0,150618.0,150619.0] || until2p7(s29)*+ -> . % 76.16/76.35 151068[97:Spt:151066.0,150618.1] || -> node4(s28)*. % 76.16/76.35 151070[97:MRR:834.0,151068.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.35 151073[97:Res:53.1,151070.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.35 151075[98:Spt:151073.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 151077[98:Res:151075.0,61.1] always3(s28) || -> . % 76.16/76.35 151078[98:SSi:151077.0,78191.0,78195.0,137750.0,150617.0,151068.0] || -> . % 76.16/76.35 151079[98:Spt:151078.0,151073.0,151075.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.35 151080[98:Spt:151078.0,151073.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 151084[98:Res:151080.0,61.1] always3(s29) || -> . % 76.16/76.35 151085[98:SSi:151084.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.35 151086[96:Spt:151085.0,150616.0,150617.0] || until2p7(s28)*+ -> . % 76.16/76.35 151087[96:Spt:151085.0,150616.1] || -> node4(s27)*. % 76.16/76.35 151089[96:MRR:837.0,151087.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.35 151092[96:Res:53.1,151089.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.35 151094[97:Spt:151092.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 151096[97:Res:151094.0,61.1] always3(s27) || -> . % 76.16/76.35 151097[97:SSi:151096.0,78187.0,78190.0,137749.0,150615.0,151087.0] || -> . % 76.16/76.35 151098[97:Spt:151097.0,151092.0,151094.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.35 151099[97:Spt:151097.0,151092.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 151103[97:Res:151099.0,61.1] always3(s28) || -> . % 76.16/76.35 151104[97:SSi:151103.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.35 151105[95:Spt:151104.0,150614.0,150615.0] || until2p7(s27)*+ -> . % 76.16/76.35 151106[95:Spt:151104.0,150614.1] || -> node4(s26)*. % 76.16/76.35 151108[95:MRR:840.0,151106.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.35 151111[95:Res:53.1,151108.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.35 151116[96:Spt:151111.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 151118[96:Res:151116.0,61.1] always3(s26) || -> . % 76.16/76.35 151119[96:SSi:151118.0,78182.0,78186.0,137748.0,150613.0,151106.0] || -> . % 76.16/76.35 151120[96:Spt:151119.0,151111.0,151116.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.35 151121[96:Spt:151119.0,151111.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 151125[96:Res:151121.0,61.1] always3(s27) || -> . % 76.16/76.35 151126[96:SSi:151125.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.35 151127[94:Spt:151126.0,150612.0,150613.0] || until2p7(s26)*+ -> . % 76.16/76.35 151128[94:Spt:151126.0,150612.1] || -> node4(s25)*. % 76.16/76.35 151130[94:MRR:843.0,151128.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.35 151133[94:Res:53.1,151130.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.35 151135[95:Spt:151133.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 151137[95:Res:151135.0,61.1] always3(s25) || -> . % 76.16/76.35 151138[95:SSi:151137.0,78178.0,78181.0,137747.0,150611.0,151128.0] || -> . % 76.16/76.35 151139[95:Spt:151138.0,151133.0,151135.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.35 151140[95:Spt:151138.0,151133.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 151144[95:Res:151140.0,61.1] always3(s26) || -> . % 76.16/76.35 151145[95:SSi:151144.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.35 151146[93:Spt:151145.0,150610.0,150611.0] || until2p7(s25)*+ -> . % 76.16/76.35 151147[93:Spt:151145.0,150610.1] || -> node4(s24)*. % 76.16/76.35 151149[93:MRR:846.0,151147.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.35 151152[93:Res:53.1,151149.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.35 151154[94:Spt:151152.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 151156[94:Res:151154.0,61.1] always3(s24) || -> . % 76.16/76.35 151157[94:SSi:151156.0,78173.0,78177.0,137746.0,150609.0,151147.0] || -> . % 76.16/76.35 151158[94:Spt:151157.0,151152.0,151154.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.35 151159[94:Spt:151157.0,151152.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 151163[94:Res:151159.0,61.1] always3(s25) || -> . % 76.16/76.35 151164[94:SSi:151163.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.35 151165[92:Spt:151164.0,150608.0,150609.0] || until2p7(s24)*+ -> . % 76.16/76.35 151166[92:Spt:151164.0,150608.1] || -> node4(s23)*. % 76.16/76.35 151168[92:MRR:849.0,151166.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.35 151171[92:Res:53.1,151168.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.35 151173[93:Spt:151171.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 151175[93:Res:151173.0,61.1] always3(s23) || -> . % 76.16/76.35 151176[93:SSi:151175.0,78169.0,78172.0,137745.0,150607.0,151166.0] || -> . % 76.16/76.35 151177[93:Spt:151176.0,151171.0,151173.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.35 151178[93:Spt:151176.0,151171.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 151182[93:Res:151178.0,61.1] always3(s24) || -> . % 76.16/76.35 151183[93:SSi:151182.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.35 151184[91:Spt:151183.0,150606.0,150607.0] || until2p7(s23)*+ -> . % 76.16/76.35 151185[91:Spt:151183.0,150606.1] || -> node4(s22)*. % 76.16/76.35 151187[91:MRR:852.0,151185.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.35 151190[91:Res:53.1,151187.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.35 151195[92:Spt:151190.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 151197[92:Res:151195.0,61.1] always3(s22) || -> . % 76.16/76.35 151198[92:SSi:151197.0,78164.0,78168.0,137744.0,150605.0,151185.0] || -> . % 76.16/76.35 151199[92:Spt:151198.0,151190.0,151195.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.35 151200[92:Spt:151198.0,151190.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 151204[92:Res:151200.0,61.1] always3(s23) || -> . % 76.16/76.35 151205[92:SSi:151204.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.35 151206[90:Spt:151205.0,150604.0,150605.0] || until2p7(s22)*+ -> . % 76.16/76.35 151207[90:Spt:151205.0,150604.1] || -> node4(s21)*. % 76.16/76.35 151209[90:MRR:855.0,151207.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.35 151212[90:Res:53.1,151209.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.35 151214[91:Spt:151212.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 151216[91:Res:151214.0,61.1] always3(s21) || -> . % 76.16/76.35 151217[91:SSi:151216.0,78160.0,78163.0,137743.0,150603.0,151207.0] || -> . % 76.16/76.35 151218[91:Spt:151217.0,151212.0,151214.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.35 151219[91:Spt:151217.0,151212.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 151223[91:Res:151219.0,61.1] always3(s22) || -> . % 76.16/76.35 151224[91:SSi:151223.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.35 151225[89:Spt:151224.0,150602.0,150603.0] || until2p7(s21)*+ -> . % 76.16/76.35 151226[89:Spt:151224.0,150602.1] || -> node4(s20)*. % 76.16/76.35 151228[89:MRR:858.0,151226.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.35 151231[89:Res:53.1,151228.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.35 151233[90:Spt:151231.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 151235[90:Res:151233.0,61.1] always3(s20) || -> . % 76.16/76.35 151236[90:SSi:151235.0,78155.0,78159.0,137742.0,150601.0,151226.0] || -> . % 76.16/76.35 151237[90:Spt:151236.0,151231.0,151233.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.35 151238[90:Spt:151236.0,151231.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 151242[90:Res:151238.0,61.1] always3(s21) || -> . % 76.16/76.35 151243[90:SSi:151242.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.35 151244[88:Spt:151243.0,150600.0,150601.0] || until2p7(s20)*+ -> . % 76.16/76.35 151245[88:Spt:151243.0,150600.1] || -> node4(s19)*. % 76.16/76.35 151247[88:MRR:861.0,151245.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.35 151250[88:Res:53.1,151247.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.35 151252[89:Spt:151250.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 151254[89:Res:151252.0,61.1] always3(s19) || -> . % 76.16/76.35 151255[89:SSi:151254.0,78151.0,78154.0,137741.0,150599.0,151245.0] || -> . % 76.16/76.35 151256[89:Spt:151255.0,151250.0,151252.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.35 151257[89:Spt:151255.0,151250.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 151261[89:Res:151257.0,61.1] always3(s20) || -> . % 76.16/76.35 151262[89:SSi:151261.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.35 151263[87:Spt:151262.0,150598.0,150599.0] || until2p7(s19)*+ -> . % 76.16/76.35 151264[87:Spt:151262.0,150598.1] || -> node4(s18)*. % 76.16/76.35 151266[87:MRR:864.0,151264.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.35 151269[87:Res:53.1,151266.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.35 151271[87:MRR:151269.0,150588.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 151276[87:Res:151271.0,61.1] always3(s19) || -> . % 76.16/76.35 151277[87:SSi:151276.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.35 151278[85:Spt:151277.0,150469.0,150472.0] || trans(s49,s18)*+ -> . % 76.16/76.35 151279[85:Spt:151277.0,150469.1,150469.2,150469.3,150469.4,150469.5,150469.6,150469.7,150469.8,150469.9,150469.10,150469.11,150469.12,150469.13,150469.14] || -> trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.35 151281[85:MRR:150471.1,151278.0] xuntil6(s49) || -> trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.35 151282[86:Spt:151279.0] || -> trans(s49,s17)*. % 76.16/76.35 151283[86:Res:151282.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s17)*. % 76.16/76.35 151285[86:Res:151282.0,60.0] || -> node2(s49,s17)*. % 76.16/76.35 151286[86:SSi:151283.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s17)*. % 76.16/76.35 151287[86:Res:151285.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 151394[86:SoR:151287.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 151396[86:SoR:151394.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)* xuntil6(s49). % 76.16/76.35 151397[86:SSi:151396.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s17,c_busy)* xuntil6(s49). % 76.16/76.35 151398[87:Spt:151397.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 151400[87:Res:151398.0,61.1] always3(s17) || -> . % 76.16/76.35 151401[87:SSi:151400.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.35 151402[87:Spt:151401.0,151397.1,151398.0] || m_main_v_state(s17,c_busy)*+ -> . % 76.16/76.35 151403[87:Spt:151401.0,151397.0,151397.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.35 151407[87:MRR:151394.2,151402.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.35 151408[87:Res:53.1,151403.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.35 151410[87:MRR:151408.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.35 151411[87:MRR:151286.0,151410.0] || -> until2p7(s17)*. % 76.16/76.35 151412[87:MRR:213.0,151411.0] || -> until2p7(s18)* node4(s17). % 76.16/76.35 151413[88:Spt:151412.0] || -> until2p7(s18)*. % 76.16/76.35 151414[88:MRR:214.0,151413.0] || -> until2p7(s19)* node4(s18). % 76.16/76.35 151415[89:Spt:151414.0] || -> until2p7(s19)*. % 76.16/76.35 151416[89:MRR:215.0,151415.0] || -> until2p7(s20)* node4(s19). % 76.16/76.35 151417[90:Spt:151416.0] || -> until2p7(s20)*. % 76.16/76.35 151418[90:MRR:216.0,151417.0] || -> until2p7(s21)* node4(s20). % 76.16/76.35 151419[91:Spt:151418.0] || -> until2p7(s21)*. % 76.16/76.35 151420[91:MRR:217.0,151419.0] || -> until2p7(s22)* node4(s21). % 76.16/76.35 151421[92:Spt:151420.0] || -> until2p7(s22)*. % 76.16/76.35 151422[92:MRR:218.0,151421.0] || -> until2p7(s23)* node4(s22). % 76.16/76.35 151423[93:Spt:151422.0] || -> until2p7(s23)*. % 76.16/76.35 151424[93:MRR:219.0,151423.0] || -> until2p7(s24)* node4(s23). % 76.16/76.35 151425[94:Spt:151424.0] || -> until2p7(s24)*. % 76.16/76.35 151426[94:MRR:220.0,151425.0] || -> until2p7(s25)* node4(s24). % 76.16/76.35 151427[95:Spt:151426.0] || -> until2p7(s25)*. % 76.16/76.35 151428[95:MRR:221.0,151427.0] || -> until2p7(s26)* node4(s25). % 76.16/76.35 151429[96:Spt:151428.0] || -> until2p7(s26)*. % 76.16/76.35 151430[96:MRR:222.0,151429.0] || -> until2p7(s27)* node4(s26). % 76.16/76.35 151431[97:Spt:151430.0] || -> until2p7(s27)*. % 76.16/76.35 151432[97:MRR:223.0,151431.0] || -> until2p7(s28)* node4(s27). % 76.16/76.35 151433[98:Spt:151432.0] || -> until2p7(s28)*. % 76.16/76.35 151434[98:MRR:224.0,151433.0] || -> until2p7(s29)* node4(s28). % 76.16/76.35 151435[99:Spt:151434.0] || -> until2p7(s29)*. % 76.16/76.35 151436[99:MRR:225.0,151435.0] || -> until2p7(s30)* node4(s29). % 76.16/76.35 151437[100:Spt:151436.0] || -> until2p7(s30)*. % 76.16/76.35 151438[100:MRR:226.0,151437.0] || -> until2p7(s31)* node4(s30). % 76.16/76.35 151439[101:Spt:151438.0] || -> until2p7(s31)*. % 76.16/76.35 151440[101:MRR:227.0,151439.0] || -> until2p7(s32)* node4(s31). % 76.16/76.35 151441[102:Spt:151440.0] || -> until2p7(s32)*. % 76.16/76.35 151442[102:MRR:228.0,151441.0] || -> until2p7(s33)* node4(s32). % 76.16/76.35 151443[103:Spt:151442.0] || -> until2p7(s33)*. % 76.16/76.35 151444[103:MRR:229.0,151443.0] || -> until2p7(s34)* node4(s33). % 76.16/76.35 151445[104:Spt:151444.0] || -> until2p7(s34)*. % 76.16/76.35 151446[104:MRR:230.0,151445.0] || -> until2p7(s35)* node4(s34). % 76.16/76.35 151447[105:Spt:151446.0] || -> until2p7(s35)*. % 76.16/76.35 151448[105:MRR:231.0,151447.0] || -> until2p7(s36)* node4(s35). % 76.16/76.35 151449[106:Spt:151448.0] || -> until2p7(s36)*. % 76.16/76.35 151450[106:MRR:232.0,151449.0] || -> until2p7(s37)* node4(s36). % 76.16/76.35 151451[107:Spt:151450.0] || -> until2p7(s37)*. % 76.16/76.35 151452[107:MRR:235.0,151451.0] || -> until2p7(s38)* node4(s37). % 76.16/76.35 151453[108:Spt:151452.0] || -> until2p7(s38)*. % 76.16/76.35 151454[108:MRR:236.0,151453.0] || -> until2p7(s39)* node4(s38). % 76.16/76.35 151455[109:Spt:151454.0] || -> until2p7(s39)*. % 76.16/76.35 151456[109:MRR:237.0,151455.0] || -> until2p7(s40)* node4(s39). % 76.16/76.35 151457[110:Spt:151456.0] || -> until2p7(s40)*. % 76.16/76.35 151458[110:MRR:238.0,151457.0] || -> until2p7(s41)* node4(s40). % 76.16/76.35 151459[111:Spt:151458.0] || -> until2p7(s41)*. % 76.16/76.35 151460[111:MRR:239.0,151459.0] || -> until2p7(s42)* node4(s41). % 76.16/76.35 151461[112:Spt:151460.0] || -> until2p7(s42)*. % 76.16/76.35 151462[112:MRR:240.0,151461.0] || -> until2p7(s43)* node4(s42). % 76.16/76.35 151463[113:Spt:151462.0] || -> until2p7(s43)*. % 76.16/76.35 151464[113:MRR:241.0,151463.0] || -> until2p7(s44)* node4(s43). % 76.16/76.35 151465[114:Spt:151464.0] || -> until2p7(s44)*. % 76.16/76.35 151466[114:MRR:539.0,151465.0] || -> until2p7(s45)* node4(s44). % 76.16/76.35 151467[115:Spt:151466.0] || -> until2p7(s45)*. % 76.16/76.35 151468[115:MRR:544.0,151467.0] || -> until2p7(s46)* node4(s45). % 76.16/76.35 151469[116:Spt:151468.0] || -> until2p7(s46)*. % 76.16/76.35 151470[116:MRR:549.0,151469.0] || -> until2p7(s47)* node4(s46). % 76.16/76.35 151471[117:Spt:151470.0] || -> until2p7(s47)*. % 76.16/76.35 151472[117:MRR:554.0,151471.0] || -> until2p7(s48)* node4(s47). % 76.16/76.35 151473[118:Spt:151472.0] || -> until2p7(s48)*. % 76.16/76.35 151474[118:MRR:559.0,151473.0] || -> until2p7(s49)* node4(s48). % 76.16/76.35 151475[119:Spt:151474.0] || -> until2p7(s49)*. % 76.16/76.35 151476[119:MRR:194.0,151475.0] || -> node4(s49)*. % 76.16/76.35 151477[119:MRR:151407.0,151476.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.35 151478[119:Res:53.1,151477.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.35 151480[119:MRR:151478.0,78381.0] || -> . % 76.16/76.35 151481[119:Spt:151480.0,151474.0,151475.0] || until2p7(s49)*+ -> . % 76.16/76.35 151482[119:Spt:151480.0,151474.1] || -> node4(s48)*. % 76.16/76.35 151483[119:MRR:78384.0,151482.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.35 151486[119:Res:53.1,151483.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 151489[119:Res:151486.0,61.1] always3(s48) || -> . % 76.16/76.35 151490[119:SSi:151489.0,78281.0,78387.0,137770.0,151473.0,151482.0] || -> . % 76.16/76.35 151491[118:Spt:151490.0,151472.0,151473.0] || until2p7(s48)*+ -> . % 76.16/76.35 151492[118:Spt:151490.0,151472.1] || -> node4(s47)*. % 76.16/76.35 151494[118:MRR:777.0,151492.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.35 151509[118:Res:53.1,151494.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.35 151514[119:Spt:151509.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 151516[119:Res:151514.0,61.1] always3(s47) || -> . % 76.16/76.35 151517[119:SSi:151516.0,78277.0,78280.0,137769.0,151471.0,151492.0] || -> . % 76.16/76.35 151518[119:Spt:151517.0,151509.0,151514.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.35 151519[119:Spt:151517.0,151509.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 151523[119:Res:151519.0,61.1] always3(s48) || -> . % 76.16/76.35 151524[119:SSi:151523.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.35 151525[117:Spt:151524.0,151470.0,151471.0] || until2p7(s47)*+ -> . % 76.16/76.35 151526[117:Spt:151524.0,151470.1] || -> node4(s46)*. % 76.16/76.35 151528[117:MRR:780.0,151526.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.35 151535[117:Res:53.1,151528.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.35 151537[118:Spt:151535.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 151539[118:Res:151537.0,61.1] always3(s46) || -> . % 76.16/76.35 151540[118:SSi:151539.0,78272.0,78276.0,137768.0,151469.0,151526.0] || -> . % 76.16/76.35 151541[118:Spt:151540.0,151535.0,151537.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.35 151542[118:Spt:151540.0,151535.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 151546[118:Res:151542.0,61.1] always3(s47) || -> . % 76.16/76.35 151547[118:SSi:151546.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.35 151548[116:Spt:151547.0,151468.0,151469.0] || until2p7(s46)*+ -> . % 76.16/76.35 151549[116:Spt:151547.0,151468.1] || -> node4(s45)*. % 76.16/76.35 151551[116:MRR:783.0,151549.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.35 151554[116:Res:53.1,151551.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.35 151559[117:Spt:151554.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 151561[117:Res:151559.0,61.1] always3(s45) || -> . % 76.16/76.35 151562[117:SSi:151561.0,78268.0,78271.0,137767.0,151467.0,151549.0] || -> . % 76.16/76.35 151563[117:Spt:151562.0,151554.0,151559.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.35 151564[117:Spt:151562.0,151554.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 151568[117:Res:151564.0,61.1] always3(s46) || -> . % 76.16/76.35 151569[117:SSi:151568.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.35 151570[115:Spt:151569.0,151466.0,151467.0] || until2p7(s45)*+ -> . % 76.16/76.35 151571[115:Spt:151569.0,151466.1] || -> node4(s44)*. % 76.16/76.35 151573[115:MRR:786.0,151571.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.35 151576[115:Res:53.1,151573.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.35 151578[116:Spt:151576.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 151580[116:Res:151578.0,61.1] always3(s44) || -> . % 76.16/76.35 151581[116:SSi:151580.0,78263.0,78267.0,137766.0,151465.0,151571.0] || -> . % 76.16/76.35 151582[116:Spt:151581.0,151576.0,151578.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.35 151583[116:Spt:151581.0,151576.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 151587[116:Res:151583.0,61.1] always3(s45) || -> . % 76.16/76.35 151588[116:SSi:151587.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.35 151589[114:Spt:151588.0,151464.0,151465.0] || until2p7(s44)*+ -> . % 76.16/76.35 151590[114:Spt:151588.0,151464.1] || -> node4(s43)*. % 76.16/76.35 151592[114:MRR:789.0,151590.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.35 151595[114:Res:53.1,151592.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.35 151597[115:Spt:151595.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 151599[115:Res:151597.0,61.1] always3(s43) || -> . % 76.16/76.35 151600[115:SSi:151599.0,78259.0,78262.0,137765.0,151463.0,151590.0] || -> . % 76.16/76.35 151601[115:Spt:151600.0,151595.0,151597.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.35 151602[115:Spt:151600.0,151595.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 151606[115:Res:151602.0,61.1] always3(s44) || -> . % 76.16/76.35 151607[115:SSi:151606.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.35 151608[113:Spt:151607.0,151462.0,151463.0] || until2p7(s43)*+ -> . % 76.16/76.35 151609[113:Spt:151607.0,151462.1] || -> node4(s42)*. % 76.16/76.35 151611[113:MRR:792.0,151609.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.35 151614[113:Res:53.1,151611.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.35 151616[114:Spt:151614.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 151618[114:Res:151616.0,61.1] always3(s42) || -> . % 76.16/76.35 151619[114:SSi:151618.0,78254.0,78258.0,137764.0,151461.0,151609.0] || -> . % 76.16/76.35 151620[114:Spt:151619.0,151614.0,151616.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.35 151621[114:Spt:151619.0,151614.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 151625[114:Res:151621.0,61.1] always3(s43) || -> . % 76.16/76.35 151626[114:SSi:151625.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.35 151627[112:Spt:151626.0,151460.0,151461.0] || until2p7(s42)*+ -> . % 76.16/76.35 151628[112:Spt:151626.0,151460.1] || -> node4(s41)*. % 76.16/76.35 151630[112:MRR:795.0,151628.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.35 151633[112:Res:53.1,151630.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.35 151638[113:Spt:151633.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 151640[113:Res:151638.0,61.1] always3(s41) || -> . % 76.16/76.35 151641[113:SSi:151640.0,78250.0,78253.0,137763.0,151459.0,151628.0] || -> . % 76.16/76.35 151642[113:Spt:151641.0,151633.0,151638.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.35 151643[113:Spt:151641.0,151633.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 151647[113:Res:151643.0,61.1] always3(s42) || -> . % 76.16/76.35 151648[113:SSi:151647.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.35 151649[111:Spt:151648.0,151458.0,151459.0] || until2p7(s41)*+ -> . % 76.16/76.35 151650[111:Spt:151648.0,151458.1] || -> node4(s40)*. % 76.16/76.35 151652[111:MRR:798.0,151650.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.35 151655[111:Res:53.1,151652.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.35 151657[112:Spt:151655.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 151659[112:Res:151657.0,61.1] always3(s40) || -> . % 76.16/76.35 151660[112:SSi:151659.0,78245.0,78249.0,137762.0,151457.0,151650.0] || -> . % 76.16/76.35 151661[112:Spt:151660.0,151655.0,151657.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.35 151662[112:Spt:151660.0,151655.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 151666[112:Res:151662.0,61.1] always3(s41) || -> . % 76.16/76.35 151667[112:SSi:151666.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.35 151668[110:Spt:151667.0,151456.0,151457.0] || until2p7(s40)*+ -> . % 76.16/76.35 151669[110:Spt:151667.0,151456.1] || -> node4(s39)*. % 76.16/76.35 151671[110:MRR:801.0,151669.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.35 151674[110:Res:53.1,151671.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.35 151676[111:Spt:151674.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 151678[111:Res:151676.0,61.1] always3(s39) || -> . % 76.16/76.35 151679[111:SSi:151678.0,78241.0,78244.0,137761.0,151455.0,151669.0] || -> . % 76.16/76.35 151680[111:Spt:151679.0,151674.0,151676.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.35 151681[111:Spt:151679.0,151674.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 151685[111:Res:151681.0,61.1] always3(s40) || -> . % 76.16/76.35 151686[111:SSi:151685.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.35 151687[109:Spt:151686.0,151454.0,151455.0] || until2p7(s39)*+ -> . % 76.16/76.35 151688[109:Spt:151686.0,151454.1] || -> node4(s38)*. % 76.16/76.35 151690[109:MRR:804.0,151688.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.35 151693[109:Res:53.1,151690.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.35 151695[110:Spt:151693.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 151697[110:Res:151695.0,61.1] always3(s38) || -> . % 76.16/76.35 151698[110:SSi:151697.0,78236.0,78240.0,137760.0,151453.0,151688.0] || -> . % 76.16/76.35 151699[110:Spt:151698.0,151693.0,151695.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.35 151700[110:Spt:151698.0,151693.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 151704[110:Res:151700.0,61.1] always3(s39) || -> . % 76.16/76.35 151705[110:SSi:151704.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.35 151706[108:Spt:151705.0,151452.0,151453.0] || until2p7(s38)*+ -> . % 76.16/76.35 151707[108:Spt:151705.0,151452.1] || -> node4(s37)*. % 76.16/76.35 151709[108:MRR:807.0,151707.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.35 151712[108:Res:53.1,151709.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.35 151717[109:Spt:151712.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 151719[109:Res:151717.0,61.1] always3(s37) || -> . % 76.16/76.35 151720[109:SSi:151719.0,78232.0,78235.0,137759.0,151451.0,151707.0] || -> . % 76.16/76.35 151721[109:Spt:151720.0,151712.0,151717.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.35 151722[109:Spt:151720.0,151712.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 151726[109:Res:151722.0,61.1] always3(s38) || -> . % 76.16/76.35 151727[109:SSi:151726.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.35 151728[107:Spt:151727.0,151450.0,151451.0] || until2p7(s37)*+ -> . % 76.16/76.35 151729[107:Spt:151727.0,151450.1] || -> node4(s36)*. % 76.16/76.35 151731[107:MRR:810.0,151729.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.35 151734[107:Res:53.1,151731.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.35 151736[108:Spt:151734.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 151738[108:Res:151736.0,61.1] always3(s36) || -> . % 76.16/76.35 151739[108:SSi:151738.0,78227.0,78231.0,137758.0,151449.0,151729.0] || -> . % 76.16/76.35 151740[108:Spt:151739.0,151734.0,151736.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.35 151741[108:Spt:151739.0,151734.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 151745[108:Res:151741.0,61.1] always3(s37) || -> . % 76.16/76.35 151746[108:SSi:151745.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.35 151747[106:Spt:151746.0,151448.0,151449.0] || until2p7(s36)*+ -> . % 76.16/76.35 151748[106:Spt:151746.0,151448.1] || -> node4(s35)*. % 76.16/76.35 151750[106:MRR:813.0,151748.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.35 151753[106:Res:53.1,151750.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.35 151755[107:Spt:151753.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 151757[107:Res:151755.0,61.1] always3(s35) || -> . % 76.16/76.35 151758[107:SSi:151757.0,78223.0,78226.0,137757.0,151447.0,151748.0] || -> . % 76.16/76.35 151759[107:Spt:151758.0,151753.0,151755.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.35 151760[107:Spt:151758.0,151753.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 151764[107:Res:151760.0,61.1] always3(s36) || -> . % 76.16/76.35 151765[107:SSi:151764.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.35 151766[105:Spt:151765.0,151446.0,151447.0] || until2p7(s35)*+ -> . % 76.16/76.35 151767[105:Spt:151765.0,151446.1] || -> node4(s34)*. % 76.16/76.35 151769[105:MRR:816.0,151767.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.35 151772[105:Res:53.1,151769.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.35 151774[106:Spt:151772.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 151776[106:Res:151774.0,61.1] always3(s34) || -> . % 76.16/76.35 151777[106:SSi:151776.0,78218.0,78222.0,137756.0,151445.0,151767.0] || -> . % 76.16/76.35 151778[106:Spt:151777.0,151772.0,151774.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.35 151779[106:Spt:151777.0,151772.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 151783[106:Res:151779.0,61.1] always3(s35) || -> . % 76.16/76.35 151784[106:SSi:151783.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.35 151785[104:Spt:151784.0,151444.0,151445.0] || until2p7(s34)*+ -> . % 76.16/76.35 151786[104:Spt:151784.0,151444.1] || -> node4(s33)*. % 76.16/76.35 151788[104:MRR:819.0,151786.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.35 151791[104:Res:53.1,151788.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.35 151796[105:Spt:151791.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 151798[105:Res:151796.0,61.1] always3(s33) || -> . % 76.16/76.35 151799[105:SSi:151798.0,78214.0,78217.0,137755.0,151443.0,151786.0] || -> . % 76.16/76.35 151800[105:Spt:151799.0,151791.0,151796.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.35 151801[105:Spt:151799.0,151791.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 151805[105:Res:151801.0,61.1] always3(s34) || -> . % 76.16/76.35 151806[105:SSi:151805.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.35 151807[103:Spt:151806.0,151442.0,151443.0] || until2p7(s33)*+ -> . % 76.16/76.35 151808[103:Spt:151806.0,151442.1] || -> node4(s32)*. % 76.16/76.35 151810[103:MRR:822.0,151808.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.35 151813[103:Res:53.1,151810.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.35 151815[104:Spt:151813.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 151817[104:Res:151815.0,61.1] always3(s32) || -> . % 76.16/76.35 151818[104:SSi:151817.0,78209.0,78213.0,137754.0,151441.0,151808.0] || -> . % 76.16/76.35 151819[104:Spt:151818.0,151813.0,151815.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.35 151820[104:Spt:151818.0,151813.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 151824[104:Res:151820.0,61.1] always3(s33) || -> . % 76.16/76.35 151825[104:SSi:151824.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.35 151826[102:Spt:151825.0,151440.0,151441.0] || until2p7(s32)*+ -> . % 76.16/76.35 151827[102:Spt:151825.0,151440.1] || -> node4(s31)*. % 76.16/76.35 151829[102:MRR:825.0,151827.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.35 151832[102:Res:53.1,151829.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.35 151834[103:Spt:151832.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 151836[103:Res:151834.0,61.1] always3(s31) || -> . % 76.16/76.35 151837[103:SSi:151836.0,78205.0,78208.0,137753.0,151439.0,151827.0] || -> . % 76.16/76.35 151838[103:Spt:151837.0,151832.0,151834.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.35 151839[103:Spt:151837.0,151832.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 151843[103:Res:151839.0,61.1] always3(s32) || -> . % 76.16/76.35 151844[103:SSi:151843.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.35 151845[101:Spt:151844.0,151438.0,151439.0] || until2p7(s31)*+ -> . % 76.16/76.35 151846[101:Spt:151844.0,151438.1] || -> node4(s30)*. % 76.16/76.35 151848[101:MRR:828.0,151846.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.35 151851[101:Res:53.1,151848.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.35 151853[102:Spt:151851.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 151855[102:Res:151853.0,61.1] always3(s30) || -> . % 76.16/76.35 151856[102:SSi:151855.0,78200.0,78204.0,137752.0,151437.0,151846.0] || -> . % 76.16/76.35 151857[102:Spt:151856.0,151851.0,151853.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.35 151858[102:Spt:151856.0,151851.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 151862[102:Res:151858.0,61.1] always3(s31) || -> . % 76.16/76.35 151863[102:SSi:151862.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.35 151864[100:Spt:151863.0,151436.0,151437.0] || until2p7(s30)*+ -> . % 76.16/76.35 151865[100:Spt:151863.0,151436.1] || -> node4(s29)*. % 76.16/76.35 151867[100:MRR:831.0,151865.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.35 151870[100:Res:53.1,151867.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.35 151875[101:Spt:151870.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 151877[101:Res:151875.0,61.1] always3(s29) || -> . % 76.16/76.35 151878[101:SSi:151877.0,78196.0,78199.0,137751.0,151435.0,151865.0] || -> . % 76.16/76.35 151879[101:Spt:151878.0,151870.0,151875.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.35 151880[101:Spt:151878.0,151870.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 151884[101:Res:151880.0,61.1] always3(s30) || -> . % 76.16/76.35 151885[101:SSi:151884.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.35 151886[99:Spt:151885.0,151434.0,151435.0] || until2p7(s29)*+ -> . % 76.16/76.35 151887[99:Spt:151885.0,151434.1] || -> node4(s28)*. % 76.16/76.35 151889[99:MRR:834.0,151887.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.35 151892[99:Res:53.1,151889.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.35 151894[100:Spt:151892.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 151896[100:Res:151894.0,61.1] always3(s28) || -> . % 76.16/76.35 151897[100:SSi:151896.0,78191.0,78195.0,137750.0,151433.0,151887.0] || -> . % 76.16/76.35 151898[100:Spt:151897.0,151892.0,151894.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.35 151899[100:Spt:151897.0,151892.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 151903[100:Res:151899.0,61.1] always3(s29) || -> . % 76.16/76.35 151904[100:SSi:151903.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.35 151905[98:Spt:151904.0,151432.0,151433.0] || until2p7(s28)*+ -> . % 76.16/76.35 151906[98:Spt:151904.0,151432.1] || -> node4(s27)*. % 76.16/76.35 151908[98:MRR:837.0,151906.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.35 151911[98:Res:53.1,151908.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.35 151913[99:Spt:151911.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 151915[99:Res:151913.0,61.1] always3(s27) || -> . % 76.16/76.35 151916[99:SSi:151915.0,78187.0,78190.0,137749.0,151431.0,151906.0] || -> . % 76.16/76.35 151917[99:Spt:151916.0,151911.0,151913.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.35 151918[99:Spt:151916.0,151911.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 151922[99:Res:151918.0,61.1] always3(s28) || -> . % 76.16/76.35 151923[99:SSi:151922.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.35 151924[97:Spt:151923.0,151430.0,151431.0] || until2p7(s27)*+ -> . % 76.16/76.35 151925[97:Spt:151923.0,151430.1] || -> node4(s26)*. % 76.16/76.35 151927[97:MRR:840.0,151925.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.35 151930[97:Res:53.1,151927.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.35 151932[98:Spt:151930.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 151934[98:Res:151932.0,61.1] always3(s26) || -> . % 76.16/76.35 151935[98:SSi:151934.0,78182.0,78186.0,137748.0,151429.0,151925.0] || -> . % 76.16/76.35 151936[98:Spt:151935.0,151930.0,151932.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.35 151937[98:Spt:151935.0,151930.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 151941[98:Res:151937.0,61.1] always3(s27) || -> . % 76.16/76.35 151942[98:SSi:151941.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.35 151943[96:Spt:151942.0,151428.0,151429.0] || until2p7(s26)*+ -> . % 76.16/76.35 151944[96:Spt:151942.0,151428.1] || -> node4(s25)*. % 76.16/76.35 151946[96:MRR:843.0,151944.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.35 151949[96:Res:53.1,151946.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.35 151954[97:Spt:151949.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 151956[97:Res:151954.0,61.1] always3(s25) || -> . % 76.16/76.35 151957[97:SSi:151956.0,78178.0,78181.0,137747.0,151427.0,151944.0] || -> . % 76.16/76.35 151958[97:Spt:151957.0,151949.0,151954.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.35 151959[97:Spt:151957.0,151949.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 151963[97:Res:151959.0,61.1] always3(s26) || -> . % 76.16/76.35 151964[97:SSi:151963.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.35 151965[95:Spt:151964.0,151426.0,151427.0] || until2p7(s25)*+ -> . % 76.16/76.35 151966[95:Spt:151964.0,151426.1] || -> node4(s24)*. % 76.16/76.35 151968[95:MRR:846.0,151966.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.35 151971[95:Res:53.1,151968.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.35 151973[96:Spt:151971.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 151975[96:Res:151973.0,61.1] always3(s24) || -> . % 76.16/76.35 151976[96:SSi:151975.0,78173.0,78177.0,137746.0,151425.0,151966.0] || -> . % 76.16/76.35 151977[96:Spt:151976.0,151971.0,151973.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.35 151978[96:Spt:151976.0,151971.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 151982[96:Res:151978.0,61.1] always3(s25) || -> . % 76.16/76.35 151983[96:SSi:151982.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.35 151984[94:Spt:151983.0,151424.0,151425.0] || until2p7(s24)*+ -> . % 76.16/76.35 151985[94:Spt:151983.0,151424.1] || -> node4(s23)*. % 76.16/76.35 151987[94:MRR:849.0,151985.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.35 151990[94:Res:53.1,151987.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.35 151992[95:Spt:151990.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 151994[95:Res:151992.0,61.1] always3(s23) || -> . % 76.16/76.35 151995[95:SSi:151994.0,78169.0,78172.0,137745.0,151423.0,151985.0] || -> . % 76.16/76.35 151996[95:Spt:151995.0,151990.0,151992.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.35 151997[95:Spt:151995.0,151990.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 152001[95:Res:151997.0,61.1] always3(s24) || -> . % 76.16/76.35 152002[95:SSi:152001.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.35 152003[93:Spt:152002.0,151422.0,151423.0] || until2p7(s23)*+ -> . % 76.16/76.35 152004[93:Spt:152002.0,151422.1] || -> node4(s22)*. % 76.16/76.35 152006[93:MRR:852.0,152004.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.35 152009[93:Res:53.1,152006.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.35 152011[94:Spt:152009.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 152013[94:Res:152011.0,61.1] always3(s22) || -> . % 76.16/76.35 152014[94:SSi:152013.0,78164.0,78168.0,137744.0,151421.0,152004.0] || -> . % 76.16/76.35 152015[94:Spt:152014.0,152009.0,152011.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.35 152016[94:Spt:152014.0,152009.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 152020[94:Res:152016.0,61.1] always3(s23) || -> . % 76.16/76.35 152021[94:SSi:152020.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.35 152022[92:Spt:152021.0,151420.0,151421.0] || until2p7(s22)*+ -> . % 76.16/76.35 152023[92:Spt:152021.0,151420.1] || -> node4(s21)*. % 76.16/76.35 152025[92:MRR:855.0,152023.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.35 152028[92:Res:53.1,152025.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.35 152033[93:Spt:152028.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 152035[93:Res:152033.0,61.1] always3(s21) || -> . % 76.16/76.35 152036[93:SSi:152035.0,78160.0,78163.0,137743.0,151419.0,152023.0] || -> . % 76.16/76.35 152037[93:Spt:152036.0,152028.0,152033.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.35 152038[93:Spt:152036.0,152028.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 152042[93:Res:152038.0,61.1] always3(s22) || -> . % 76.16/76.35 152043[93:SSi:152042.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.35 152044[91:Spt:152043.0,151418.0,151419.0] || until2p7(s21)*+ -> . % 76.16/76.35 152045[91:Spt:152043.0,151418.1] || -> node4(s20)*. % 76.16/76.35 152047[91:MRR:858.0,152045.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.35 152050[91:Res:53.1,152047.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.35 152052[92:Spt:152050.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 152054[92:Res:152052.0,61.1] always3(s20) || -> . % 76.16/76.35 152055[92:SSi:152054.0,78155.0,78159.0,137742.0,151417.0,152045.0] || -> . % 76.16/76.35 152056[92:Spt:152055.0,152050.0,152052.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.35 152057[92:Spt:152055.0,152050.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 152061[92:Res:152057.0,61.1] always3(s21) || -> . % 76.16/76.35 152062[92:SSi:152061.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.35 152063[90:Spt:152062.0,151416.0,151417.0] || until2p7(s20)*+ -> . % 76.16/76.35 152064[90:Spt:152062.0,151416.1] || -> node4(s19)*. % 76.16/76.35 152066[90:MRR:861.0,152064.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.35 152069[90:Res:53.1,152066.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.35 152071[91:Spt:152069.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 152073[91:Res:152071.0,61.1] always3(s19) || -> . % 76.16/76.35 152074[91:SSi:152073.0,78151.0,78154.0,137741.0,151415.0,152064.0] || -> . % 76.16/76.35 152075[91:Spt:152074.0,152069.0,152071.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.35 152076[91:Spt:152074.0,152069.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 152080[91:Res:152076.0,61.1] always3(s20) || -> . % 76.16/76.35 152081[91:SSi:152080.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.35 152082[89:Spt:152081.0,151414.0,151415.0] || until2p7(s19)*+ -> . % 76.16/76.35 152083[89:Spt:152081.0,151414.1] || -> node4(s18)*. % 76.16/76.35 152085[89:MRR:864.0,152083.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.35 152088[89:Res:53.1,152085.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.35 152090[90:Spt:152088.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 152092[90:Res:152090.0,61.1] always3(s18) || -> . % 76.16/76.35 152093[90:SSi:152092.0,78146.0,78150.0,137740.0,151413.0,152083.0] || -> . % 76.16/76.35 152094[90:Spt:152093.0,152088.0,152090.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.35 152095[90:Spt:152093.0,152088.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 152099[90:Res:152095.0,61.1] always3(s19) || -> . % 76.16/76.35 152100[90:SSi:152099.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.35 152101[88:Spt:152100.0,151412.0,151413.0] || until2p7(s18)*+ -> . % 76.16/76.35 152102[88:Spt:152100.0,151412.1] || -> node4(s17)*. % 76.16/76.35 152104[88:MRR:867.0,152102.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.35 152107[88:Res:53.1,152104.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.35 152109[88:MRR:152107.0,151402.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 152114[88:Res:152109.0,61.1] always3(s18) || -> . % 76.16/76.35 152115[88:SSi:152114.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.35 152116[86:Spt:152115.0,151279.0,151282.0] || trans(s49,s17)*+ -> . % 76.16/76.35 152117[86:Spt:152115.0,151279.1,151279.2,151279.3,151279.4,151279.5,151279.6,151279.7,151279.8,151279.9,151279.10,151279.11,151279.12,151279.13] || -> trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.35 152119[86:MRR:151281.1,152116.0] xuntil6(s49) || -> trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.35 152120[87:Spt:152117.0] || -> trans(s49,s16)*. % 76.16/76.35 152121[87:Res:152120.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s16)*. % 76.16/76.35 152123[87:Res:152120.0,60.0] || -> node2(s49,s16)*. % 76.16/76.35 152124[87:SSi:152121.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s16)*. % 76.16/76.35 152125[87:Res:152123.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 152233[87:SoR:152125.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 152235[87:SoR:152233.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)* xuntil6(s49). % 76.16/76.35 152236[87:SSi:152235.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s16,c_busy)* xuntil6(s49). % 76.16/76.35 152237[88:Spt:152236.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 152239[88:Res:152237.0,61.1] always3(s16) || -> . % 76.16/76.35 152240[88:SSi:152239.0,78137.0,78141.0,137738.0] || -> . % 76.16/76.35 152241[88:Spt:152240.0,152236.1,152237.0] || m_main_v_state(s16,c_busy)*+ -> . % 76.16/76.35 152242[88:Spt:152240.0,152236.0,152236.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.35 152246[88:MRR:152233.2,152241.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.35 152247[88:Res:53.1,152242.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.35 152249[88:MRR:152247.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.35 152250[88:MRR:152124.0,152249.0] || -> until2p7(s16)*. % 76.16/76.35 152251[88:MRR:212.0,152250.0] || -> until2p7(s17)* node4(s16). % 76.16/76.35 152252[89:Spt:152251.0] || -> until2p7(s17)*. % 76.16/76.35 152253[89:MRR:213.0,152252.0] || -> until2p7(s18)* node4(s17). % 76.16/76.35 152254[90:Spt:152253.0] || -> until2p7(s18)*. % 76.16/76.35 152255[90:MRR:214.0,152254.0] || -> until2p7(s19)* node4(s18). % 76.16/76.35 152256[91:Spt:152255.0] || -> until2p7(s19)*. % 76.16/76.35 152257[91:MRR:215.0,152256.0] || -> until2p7(s20)* node4(s19). % 76.16/76.35 152258[92:Spt:152257.0] || -> until2p7(s20)*. % 76.16/76.35 152259[92:MRR:216.0,152258.0] || -> until2p7(s21)* node4(s20). % 76.16/76.35 152260[93:Spt:152259.0] || -> until2p7(s21)*. % 76.16/76.35 152261[93:MRR:217.0,152260.0] || -> until2p7(s22)* node4(s21). % 76.16/76.35 152262[94:Spt:152261.0] || -> until2p7(s22)*. % 76.16/76.35 152263[94:MRR:218.0,152262.0] || -> until2p7(s23)* node4(s22). % 76.16/76.35 152264[95:Spt:152263.0] || -> until2p7(s23)*. % 76.16/76.35 152265[95:MRR:219.0,152264.0] || -> until2p7(s24)* node4(s23). % 76.16/76.35 152266[96:Spt:152265.0] || -> until2p7(s24)*. % 76.16/76.35 152267[96:MRR:220.0,152266.0] || -> until2p7(s25)* node4(s24). % 76.16/76.35 152268[97:Spt:152267.0] || -> until2p7(s25)*. % 76.16/76.35 152269[97:MRR:221.0,152268.0] || -> until2p7(s26)* node4(s25). % 76.16/76.35 152270[98:Spt:152269.0] || -> until2p7(s26)*. % 76.16/76.35 152271[98:MRR:222.0,152270.0] || -> until2p7(s27)* node4(s26). % 76.16/76.35 152272[99:Spt:152271.0] || -> until2p7(s27)*. % 76.16/76.35 152273[99:MRR:223.0,152272.0] || -> until2p7(s28)* node4(s27). % 76.16/76.35 152274[100:Spt:152273.0] || -> until2p7(s28)*. % 76.16/76.35 152275[100:MRR:224.0,152274.0] || -> until2p7(s29)* node4(s28). % 76.16/76.35 152276[101:Spt:152275.0] || -> until2p7(s29)*. % 76.16/76.35 152277[101:MRR:225.0,152276.0] || -> until2p7(s30)* node4(s29). % 76.16/76.35 152278[102:Spt:152277.0] || -> until2p7(s30)*. % 76.16/76.35 152279[102:MRR:226.0,152278.0] || -> until2p7(s31)* node4(s30). % 76.16/76.35 152280[103:Spt:152279.0] || -> until2p7(s31)*. % 76.16/76.35 152281[103:MRR:227.0,152280.0] || -> until2p7(s32)* node4(s31). % 76.16/76.35 152282[104:Spt:152281.0] || -> until2p7(s32)*. % 76.16/76.35 152283[104:MRR:228.0,152282.0] || -> until2p7(s33)* node4(s32). % 76.16/76.35 152284[105:Spt:152283.0] || -> until2p7(s33)*. % 76.16/76.35 152285[105:MRR:229.0,152284.0] || -> until2p7(s34)* node4(s33). % 76.16/76.35 152286[106:Spt:152285.0] || -> until2p7(s34)*. % 76.16/76.35 152287[106:MRR:230.0,152286.0] || -> until2p7(s35)* node4(s34). % 76.16/76.35 152288[107:Spt:152287.0] || -> until2p7(s35)*. % 76.16/76.35 152289[107:MRR:231.0,152288.0] || -> until2p7(s36)* node4(s35). % 76.16/76.35 152290[108:Spt:152289.0] || -> until2p7(s36)*. % 76.16/76.35 152291[108:MRR:232.0,152290.0] || -> until2p7(s37)* node4(s36). % 76.16/76.35 152292[109:Spt:152291.0] || -> until2p7(s37)*. % 76.16/76.35 152293[109:MRR:235.0,152292.0] || -> until2p7(s38)* node4(s37). % 76.16/76.35 152294[110:Spt:152293.0] || -> until2p7(s38)*. % 76.16/76.35 152295[110:MRR:236.0,152294.0] || -> until2p7(s39)* node4(s38). % 76.16/76.35 152296[111:Spt:152295.0] || -> until2p7(s39)*. % 76.16/76.35 152297[111:MRR:237.0,152296.0] || -> until2p7(s40)* node4(s39). % 76.16/76.35 152298[112:Spt:152297.0] || -> until2p7(s40)*. % 76.16/76.35 152299[112:MRR:238.0,152298.0] || -> until2p7(s41)* node4(s40). % 76.16/76.35 152300[113:Spt:152299.0] || -> until2p7(s41)*. % 76.16/76.35 152301[113:MRR:239.0,152300.0] || -> until2p7(s42)* node4(s41). % 76.16/76.35 152302[114:Spt:152301.0] || -> until2p7(s42)*. % 76.16/76.35 152303[114:MRR:240.0,152302.0] || -> until2p7(s43)* node4(s42). % 76.16/76.35 152304[115:Spt:152303.0] || -> until2p7(s43)*. % 76.16/76.35 152305[115:MRR:241.0,152304.0] || -> until2p7(s44)* node4(s43). % 76.16/76.35 152306[116:Spt:152305.0] || -> until2p7(s44)*. % 76.16/76.35 152307[116:MRR:539.0,152306.0] || -> until2p7(s45)* node4(s44). % 76.16/76.35 152308[117:Spt:152307.0] || -> until2p7(s45)*. % 76.16/76.35 152309[117:MRR:544.0,152308.0] || -> until2p7(s46)* node4(s45). % 76.16/76.35 152310[118:Spt:152309.0] || -> until2p7(s46)*. % 76.16/76.35 152311[118:MRR:549.0,152310.0] || -> until2p7(s47)* node4(s46). % 76.16/76.35 152312[119:Spt:152311.0] || -> until2p7(s47)*. % 76.16/76.35 152313[119:MRR:554.0,152312.0] || -> until2p7(s48)* node4(s47). % 76.16/76.35 152314[120:Spt:152313.0] || -> until2p7(s48)*. % 76.16/76.35 152315[120:MRR:559.0,152314.0] || -> until2p7(s49)* node4(s48). % 76.16/76.35 152316[121:Spt:152315.0] || -> until2p7(s49)*. % 76.16/76.35 152317[121:MRR:194.0,152316.0] || -> node4(s49)*. % 76.16/76.35 152318[121:MRR:152246.0,152317.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.35 152322[121:Res:53.1,152318.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.35 152324[121:MRR:152322.0,78381.0] || -> . % 76.16/76.35 152325[121:Spt:152324.0,152315.0,152316.0] || until2p7(s49)*+ -> . % 76.16/76.35 152326[121:Spt:152324.0,152315.1] || -> node4(s48)*. % 76.16/76.35 152327[121:MRR:78384.0,152326.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.35 152330[121:Res:53.1,152327.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 152333[121:Res:152330.0,61.1] always3(s48) || -> . % 76.16/76.35 152334[121:SSi:152333.0,78281.0,78387.0,137770.0,152314.0,152326.0] || -> . % 76.16/76.35 152335[120:Spt:152334.0,152313.0,152314.0] || until2p7(s48)*+ -> . % 76.16/76.35 152336[120:Spt:152334.0,152313.1] || -> node4(s47)*. % 76.16/76.35 152338[120:MRR:777.0,152336.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.35 152350[120:Res:53.1,152338.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.35 152352[121:Spt:152350.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 152354[121:Res:152352.0,61.1] always3(s47) || -> . % 76.16/76.35 152355[121:SSi:152354.0,78277.0,78280.0,137769.0,152312.0,152336.0] || -> . % 76.16/76.35 152356[121:Spt:152355.0,152350.0,152352.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.35 152357[121:Spt:152355.0,152350.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 152361[121:Res:152357.0,61.1] always3(s48) || -> . % 76.16/76.35 152362[121:SSi:152361.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.35 152363[119:Spt:152362.0,152311.0,152312.0] || until2p7(s47)*+ -> . % 76.16/76.35 152364[119:Spt:152362.0,152311.1] || -> node4(s46)*. % 76.16/76.35 152366[119:MRR:780.0,152364.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.35 152373[119:Res:53.1,152366.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.35 152378[120:Spt:152373.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 152380[120:Res:152378.0,61.1] always3(s46) || -> . % 76.16/76.35 152381[120:SSi:152380.0,78272.0,78276.0,137768.0,152310.0,152364.0] || -> . % 76.16/76.35 152382[120:Spt:152381.0,152373.0,152378.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.35 152383[120:Spt:152381.0,152373.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 152387[120:Res:152383.0,61.1] always3(s47) || -> . % 76.16/76.35 152388[120:SSi:152387.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.35 152389[118:Spt:152388.0,152309.0,152310.0] || until2p7(s46)*+ -> . % 76.16/76.35 152390[118:Spt:152388.0,152309.1] || -> node4(s45)*. % 76.16/76.35 152392[118:MRR:783.0,152390.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.35 152395[118:Res:53.1,152392.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.35 152397[119:Spt:152395.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 152399[119:Res:152397.0,61.1] always3(s45) || -> . % 76.16/76.35 152400[119:SSi:152399.0,78268.0,78271.0,137767.0,152308.0,152390.0] || -> . % 76.16/76.35 152401[119:Spt:152400.0,152395.0,152397.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.35 152402[119:Spt:152400.0,152395.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 152406[119:Res:152402.0,61.1] always3(s46) || -> . % 76.16/76.35 152407[119:SSi:152406.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.35 152408[117:Spt:152407.0,152307.0,152308.0] || until2p7(s45)*+ -> . % 76.16/76.35 152409[117:Spt:152407.0,152307.1] || -> node4(s44)*. % 76.16/76.35 152411[117:MRR:786.0,152409.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.35 152414[117:Res:53.1,152411.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.35 152416[118:Spt:152414.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 152418[118:Res:152416.0,61.1] always3(s44) || -> . % 76.16/76.35 152419[118:SSi:152418.0,78263.0,78267.0,137766.0,152306.0,152409.0] || -> . % 76.16/76.35 152420[118:Spt:152419.0,152414.0,152416.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.35 152421[118:Spt:152419.0,152414.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 152425[118:Res:152421.0,61.1] always3(s45) || -> . % 76.16/76.35 152426[118:SSi:152425.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.35 152427[116:Spt:152426.0,152305.0,152306.0] || until2p7(s44)*+ -> . % 76.16/76.35 152428[116:Spt:152426.0,152305.1] || -> node4(s43)*. % 76.16/76.35 152430[116:MRR:789.0,152428.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.35 152433[116:Res:53.1,152430.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.35 152435[117:Spt:152433.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 152437[117:Res:152435.0,61.1] always3(s43) || -> . % 76.16/76.35 152438[117:SSi:152437.0,78259.0,78262.0,137765.0,152304.0,152428.0] || -> . % 76.16/76.35 152439[117:Spt:152438.0,152433.0,152435.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.35 152440[117:Spt:152438.0,152433.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 152444[117:Res:152440.0,61.1] always3(s44) || -> . % 76.16/76.35 152445[117:SSi:152444.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.35 152446[115:Spt:152445.0,152303.0,152304.0] || until2p7(s43)*+ -> . % 76.16/76.35 152447[115:Spt:152445.0,152303.1] || -> node4(s42)*. % 76.16/76.35 152449[115:MRR:792.0,152447.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.35 152452[115:Res:53.1,152449.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.35 152457[116:Spt:152452.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 152459[116:Res:152457.0,61.1] always3(s42) || -> . % 76.16/76.35 152460[116:SSi:152459.0,78254.0,78258.0,137764.0,152302.0,152447.0] || -> . % 76.16/76.35 152461[116:Spt:152460.0,152452.0,152457.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.35 152462[116:Spt:152460.0,152452.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 152466[116:Res:152462.0,61.1] always3(s43) || -> . % 76.16/76.35 152467[116:SSi:152466.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.35 152468[114:Spt:152467.0,152301.0,152302.0] || until2p7(s42)*+ -> . % 76.16/76.35 152469[114:Spt:152467.0,152301.1] || -> node4(s41)*. % 76.16/76.35 152471[114:MRR:795.0,152469.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.35 152474[114:Res:53.1,152471.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.35 152476[115:Spt:152474.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 152478[115:Res:152476.0,61.1] always3(s41) || -> . % 76.16/76.35 152479[115:SSi:152478.0,78250.0,78253.0,137763.0,152300.0,152469.0] || -> . % 76.16/76.35 152480[115:Spt:152479.0,152474.0,152476.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.35 152481[115:Spt:152479.0,152474.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 152485[115:Res:152481.0,61.1] always3(s42) || -> . % 76.16/76.35 152486[115:SSi:152485.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.35 152487[113:Spt:152486.0,152299.0,152300.0] || until2p7(s41)*+ -> . % 76.16/76.35 152488[113:Spt:152486.0,152299.1] || -> node4(s40)*. % 76.16/76.35 152490[113:MRR:798.0,152488.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.35 152493[113:Res:53.1,152490.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.35 152495[114:Spt:152493.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 152497[114:Res:152495.0,61.1] always3(s40) || -> . % 76.16/76.35 152498[114:SSi:152497.0,78245.0,78249.0,137762.0,152298.0,152488.0] || -> . % 76.16/76.35 152499[114:Spt:152498.0,152493.0,152495.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.35 152500[114:Spt:152498.0,152493.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 152504[114:Res:152500.0,61.1] always3(s41) || -> . % 76.16/76.35 152505[114:SSi:152504.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.35 152506[112:Spt:152505.0,152297.0,152298.0] || until2p7(s40)*+ -> . % 76.16/76.35 152507[112:Spt:152505.0,152297.1] || -> node4(s39)*. % 76.16/76.35 152509[112:MRR:801.0,152507.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.35 152512[112:Res:53.1,152509.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.35 152514[113:Spt:152512.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 152516[113:Res:152514.0,61.1] always3(s39) || -> . % 76.16/76.35 152517[113:SSi:152516.0,78241.0,78244.0,137761.0,152296.0,152507.0] || -> . % 76.16/76.35 152518[113:Spt:152517.0,152512.0,152514.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.35 152519[113:Spt:152517.0,152512.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 152523[113:Res:152519.0,61.1] always3(s40) || -> . % 76.16/76.35 152524[113:SSi:152523.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.35 152525[111:Spt:152524.0,152295.0,152296.0] || until2p7(s39)*+ -> . % 76.16/76.35 152526[111:Spt:152524.0,152295.1] || -> node4(s38)*. % 76.16/76.35 152528[111:MRR:804.0,152526.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.35 152531[111:Res:53.1,152528.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.35 152536[112:Spt:152531.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 152538[112:Res:152536.0,61.1] always3(s38) || -> . % 76.16/76.35 152539[112:SSi:152538.0,78236.0,78240.0,137760.0,152294.0,152526.0] || -> . % 76.16/76.35 152540[112:Spt:152539.0,152531.0,152536.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.35 152541[112:Spt:152539.0,152531.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 152545[112:Res:152541.0,61.1] always3(s39) || -> . % 76.16/76.35 152546[112:SSi:152545.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.35 152547[110:Spt:152546.0,152293.0,152294.0] || until2p7(s38)*+ -> . % 76.16/76.35 152548[110:Spt:152546.0,152293.1] || -> node4(s37)*. % 76.16/76.35 152550[110:MRR:807.0,152548.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.35 152553[110:Res:53.1,152550.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.35 152555[111:Spt:152553.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 152557[111:Res:152555.0,61.1] always3(s37) || -> . % 76.16/76.35 152558[111:SSi:152557.0,78232.0,78235.0,137759.0,152292.0,152548.0] || -> . % 76.16/76.35 152559[111:Spt:152558.0,152553.0,152555.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.35 152560[111:Spt:152558.0,152553.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 152564[111:Res:152560.0,61.1] always3(s38) || -> . % 76.16/76.35 152565[111:SSi:152564.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.35 152566[109:Spt:152565.0,152291.0,152292.0] || until2p7(s37)*+ -> . % 76.16/76.35 152567[109:Spt:152565.0,152291.1] || -> node4(s36)*. % 76.16/76.35 152569[109:MRR:810.0,152567.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.35 152572[109:Res:53.1,152569.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.35 152574[110:Spt:152572.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 152576[110:Res:152574.0,61.1] always3(s36) || -> . % 76.16/76.35 152577[110:SSi:152576.0,78227.0,78231.0,137758.0,152290.0,152567.0] || -> . % 76.16/76.35 152578[110:Spt:152577.0,152572.0,152574.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.35 152579[110:Spt:152577.0,152572.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 152583[110:Res:152579.0,61.1] always3(s37) || -> . % 76.16/76.35 152584[110:SSi:152583.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.35 152585[108:Spt:152584.0,152289.0,152290.0] || until2p7(s36)*+ -> . % 76.16/76.35 152586[108:Spt:152584.0,152289.1] || -> node4(s35)*. % 76.16/76.35 152588[108:MRR:813.0,152586.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.35 152591[108:Res:53.1,152588.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.35 152593[109:Spt:152591.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 152595[109:Res:152593.0,61.1] always3(s35) || -> . % 76.16/76.35 152596[109:SSi:152595.0,78223.0,78226.0,137757.0,152288.0,152586.0] || -> . % 76.16/76.35 152597[109:Spt:152596.0,152591.0,152593.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.35 152598[109:Spt:152596.0,152591.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 152602[109:Res:152598.0,61.1] always3(s36) || -> . % 76.16/76.35 152603[109:SSi:152602.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.35 152604[107:Spt:152603.0,152287.0,152288.0] || until2p7(s35)*+ -> . % 76.16/76.35 152605[107:Spt:152603.0,152287.1] || -> node4(s34)*. % 76.16/76.35 152607[107:MRR:816.0,152605.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.35 152610[107:Res:53.1,152607.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.35 152615[108:Spt:152610.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 152617[108:Res:152615.0,61.1] always3(s34) || -> . % 76.16/76.35 152618[108:SSi:152617.0,78218.0,78222.0,137756.0,152286.0,152605.0] || -> . % 76.16/76.35 152619[108:Spt:152618.0,152610.0,152615.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.35 152620[108:Spt:152618.0,152610.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 152624[108:Res:152620.0,61.1] always3(s35) || -> . % 76.16/76.35 152625[108:SSi:152624.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.35 152626[106:Spt:152625.0,152285.0,152286.0] || until2p7(s34)*+ -> . % 76.16/76.35 152627[106:Spt:152625.0,152285.1] || -> node4(s33)*. % 76.16/76.35 152629[106:MRR:819.0,152627.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.35 152632[106:Res:53.1,152629.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.35 152634[107:Spt:152632.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 152636[107:Res:152634.0,61.1] always3(s33) || -> . % 76.16/76.35 152637[107:SSi:152636.0,78214.0,78217.0,137755.0,152284.0,152627.0] || -> . % 76.16/76.35 152638[107:Spt:152637.0,152632.0,152634.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.35 152639[107:Spt:152637.0,152632.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 152643[107:Res:152639.0,61.1] always3(s34) || -> . % 76.16/76.35 152644[107:SSi:152643.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.35 152645[105:Spt:152644.0,152283.0,152284.0] || until2p7(s33)*+ -> . % 76.16/76.35 152646[105:Spt:152644.0,152283.1] || -> node4(s32)*. % 76.16/76.35 152648[105:MRR:822.0,152646.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.35 152651[105:Res:53.1,152648.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.35 152653[106:Spt:152651.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 152655[106:Res:152653.0,61.1] always3(s32) || -> . % 76.16/76.35 152656[106:SSi:152655.0,78209.0,78213.0,137754.0,152282.0,152646.0] || -> . % 76.16/76.35 152657[106:Spt:152656.0,152651.0,152653.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.35 152658[106:Spt:152656.0,152651.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 152662[106:Res:152658.0,61.1] always3(s33) || -> . % 76.16/76.35 152663[106:SSi:152662.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.35 152664[104:Spt:152663.0,152281.0,152282.0] || until2p7(s32)*+ -> . % 76.16/76.35 152665[104:Spt:152663.0,152281.1] || -> node4(s31)*. % 76.16/76.35 152667[104:MRR:825.0,152665.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.35 152670[104:Res:53.1,152667.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.35 152672[105:Spt:152670.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 152674[105:Res:152672.0,61.1] always3(s31) || -> . % 76.16/76.35 152675[105:SSi:152674.0,78205.0,78208.0,137753.0,152280.0,152665.0] || -> . % 76.16/76.35 152676[105:Spt:152675.0,152670.0,152672.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.35 152677[105:Spt:152675.0,152670.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 152681[105:Res:152677.0,61.1] always3(s32) || -> . % 76.16/76.35 152682[105:SSi:152681.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.35 152683[103:Spt:152682.0,152279.0,152280.0] || until2p7(s31)*+ -> . % 76.16/76.35 152684[103:Spt:152682.0,152279.1] || -> node4(s30)*. % 76.16/76.35 152686[103:MRR:828.0,152684.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.35 152689[103:Res:53.1,152686.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.35 152694[104:Spt:152689.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 152696[104:Res:152694.0,61.1] always3(s30) || -> . % 76.16/76.35 152697[104:SSi:152696.0,78200.0,78204.0,137752.0,152278.0,152684.0] || -> . % 76.16/76.35 152698[104:Spt:152697.0,152689.0,152694.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.35 152699[104:Spt:152697.0,152689.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 152703[104:Res:152699.0,61.1] always3(s31) || -> . % 76.16/76.35 152704[104:SSi:152703.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.35 152705[102:Spt:152704.0,152277.0,152278.0] || until2p7(s30)*+ -> . % 76.16/76.35 152706[102:Spt:152704.0,152277.1] || -> node4(s29)*. % 76.16/76.35 152708[102:MRR:831.0,152706.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.35 152711[102:Res:53.1,152708.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.35 152713[103:Spt:152711.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 152715[103:Res:152713.0,61.1] always3(s29) || -> . % 76.16/76.35 152716[103:SSi:152715.0,78196.0,78199.0,137751.0,152276.0,152706.0] || -> . % 76.16/76.35 152717[103:Spt:152716.0,152711.0,152713.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.35 152718[103:Spt:152716.0,152711.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 152722[103:Res:152718.0,61.1] always3(s30) || -> . % 76.16/76.35 152723[103:SSi:152722.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.35 152724[101:Spt:152723.0,152275.0,152276.0] || until2p7(s29)*+ -> . % 76.16/76.35 152725[101:Spt:152723.0,152275.1] || -> node4(s28)*. % 76.16/76.35 152727[101:MRR:834.0,152725.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.35 152730[101:Res:53.1,152727.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.35 152732[102:Spt:152730.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 152734[102:Res:152732.0,61.1] always3(s28) || -> . % 76.16/76.35 152735[102:SSi:152734.0,78191.0,78195.0,137750.0,152274.0,152725.0] || -> . % 76.16/76.35 152736[102:Spt:152735.0,152730.0,152732.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.35 152737[102:Spt:152735.0,152730.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 152741[102:Res:152737.0,61.1] always3(s29) || -> . % 76.16/76.35 152742[102:SSi:152741.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.35 152743[100:Spt:152742.0,152273.0,152274.0] || until2p7(s28)*+ -> . % 76.16/76.35 152744[100:Spt:152742.0,152273.1] || -> node4(s27)*. % 76.16/76.35 152746[100:MRR:837.0,152744.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.35 152749[100:Res:53.1,152746.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.35 152751[101:Spt:152749.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 152753[101:Res:152751.0,61.1] always3(s27) || -> . % 76.16/76.35 152754[101:SSi:152753.0,78187.0,78190.0,137749.0,152272.0,152744.0] || -> . % 76.16/76.35 152755[101:Spt:152754.0,152749.0,152751.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.35 152756[101:Spt:152754.0,152749.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 152760[101:Res:152756.0,61.1] always3(s28) || -> . % 76.16/76.35 152761[101:SSi:152760.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.35 152762[99:Spt:152761.0,152271.0,152272.0] || until2p7(s27)*+ -> . % 76.16/76.35 152763[99:Spt:152761.0,152271.1] || -> node4(s26)*. % 76.16/76.35 152765[99:MRR:840.0,152763.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.35 152768[99:Res:53.1,152765.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.35 152773[100:Spt:152768.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 152775[100:Res:152773.0,61.1] always3(s26) || -> . % 76.16/76.35 152776[100:SSi:152775.0,78182.0,78186.0,137748.0,152270.0,152763.0] || -> . % 76.16/76.35 152777[100:Spt:152776.0,152768.0,152773.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.35 152778[100:Spt:152776.0,152768.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 152782[100:Res:152778.0,61.1] always3(s27) || -> . % 76.16/76.35 152783[100:SSi:152782.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.35 152784[98:Spt:152783.0,152269.0,152270.0] || until2p7(s26)*+ -> . % 76.16/76.35 152785[98:Spt:152783.0,152269.1] || -> node4(s25)*. % 76.16/76.35 152787[98:MRR:843.0,152785.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.35 152790[98:Res:53.1,152787.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.35 152792[99:Spt:152790.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 152794[99:Res:152792.0,61.1] always3(s25) || -> . % 76.16/76.35 152795[99:SSi:152794.0,78178.0,78181.0,137747.0,152268.0,152785.0] || -> . % 76.16/76.35 152796[99:Spt:152795.0,152790.0,152792.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.35 152797[99:Spt:152795.0,152790.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 152801[99:Res:152797.0,61.1] always3(s26) || -> . % 76.16/76.35 152802[99:SSi:152801.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.35 152803[97:Spt:152802.0,152267.0,152268.0] || until2p7(s25)*+ -> . % 76.16/76.35 152804[97:Spt:152802.0,152267.1] || -> node4(s24)*. % 76.16/76.35 152806[97:MRR:846.0,152804.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.35 152809[97:Res:53.1,152806.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.35 152811[98:Spt:152809.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 152813[98:Res:152811.0,61.1] always3(s24) || -> . % 76.16/76.35 152814[98:SSi:152813.0,78173.0,78177.0,137746.0,152266.0,152804.0] || -> . % 76.16/76.35 152815[98:Spt:152814.0,152809.0,152811.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.35 152816[98:Spt:152814.0,152809.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 152820[98:Res:152816.0,61.1] always3(s25) || -> . % 76.16/76.35 152821[98:SSi:152820.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.35 152822[96:Spt:152821.0,152265.0,152266.0] || until2p7(s24)*+ -> . % 76.16/76.35 152823[96:Spt:152821.0,152265.1] || -> node4(s23)*. % 76.16/76.35 152825[96:MRR:849.0,152823.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.35 152828[96:Res:53.1,152825.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.35 152830[97:Spt:152828.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 152832[97:Res:152830.0,61.1] always3(s23) || -> . % 76.16/76.35 152833[97:SSi:152832.0,78169.0,78172.0,137745.0,152264.0,152823.0] || -> . % 76.16/76.35 152834[97:Spt:152833.0,152828.0,152830.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.35 152835[97:Spt:152833.0,152828.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 152839[97:Res:152835.0,61.1] always3(s24) || -> . % 76.16/76.35 152840[97:SSi:152839.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.35 152841[95:Spt:152840.0,152263.0,152264.0] || until2p7(s23)*+ -> . % 76.16/76.35 152842[95:Spt:152840.0,152263.1] || -> node4(s22)*. % 76.16/76.35 152844[95:MRR:852.0,152842.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.35 152847[95:Res:53.1,152844.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.35 152852[96:Spt:152847.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 152854[96:Res:152852.0,61.1] always3(s22) || -> . % 76.16/76.35 152855[96:SSi:152854.0,78164.0,78168.0,137744.0,152262.0,152842.0] || -> . % 76.16/76.35 152856[96:Spt:152855.0,152847.0,152852.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.35 152857[96:Spt:152855.0,152847.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 152861[96:Res:152857.0,61.1] always3(s23) || -> . % 76.16/76.35 152862[96:SSi:152861.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.35 152863[94:Spt:152862.0,152261.0,152262.0] || until2p7(s22)*+ -> . % 76.16/76.35 152864[94:Spt:152862.0,152261.1] || -> node4(s21)*. % 76.16/76.35 152866[94:MRR:855.0,152864.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.35 152869[94:Res:53.1,152866.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.35 152871[95:Spt:152869.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 152873[95:Res:152871.0,61.1] always3(s21) || -> . % 76.16/76.35 152874[95:SSi:152873.0,78160.0,78163.0,137743.0,152260.0,152864.0] || -> . % 76.16/76.35 152875[95:Spt:152874.0,152869.0,152871.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.35 152876[95:Spt:152874.0,152869.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 152880[95:Res:152876.0,61.1] always3(s22) || -> . % 76.16/76.35 152881[95:SSi:152880.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.35 152882[93:Spt:152881.0,152259.0,152260.0] || until2p7(s21)*+ -> . % 76.16/76.35 152883[93:Spt:152881.0,152259.1] || -> node4(s20)*. % 76.16/76.35 152885[93:MRR:858.0,152883.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.35 152888[93:Res:53.1,152885.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.35 152890[94:Spt:152888.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 152892[94:Res:152890.0,61.1] always3(s20) || -> . % 76.16/76.35 152893[94:SSi:152892.0,78155.0,78159.0,137742.0,152258.0,152883.0] || -> . % 76.16/76.35 152894[94:Spt:152893.0,152888.0,152890.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.35 152895[94:Spt:152893.0,152888.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 152899[94:Res:152895.0,61.1] always3(s21) || -> . % 76.16/76.35 152900[94:SSi:152899.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.35 152901[92:Spt:152900.0,152257.0,152258.0] || until2p7(s20)*+ -> . % 76.16/76.35 152902[92:Spt:152900.0,152257.1] || -> node4(s19)*. % 76.16/76.35 152904[92:MRR:861.0,152902.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.35 152907[92:Res:53.1,152904.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.35 152909[93:Spt:152907.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 152911[93:Res:152909.0,61.1] always3(s19) || -> . % 76.16/76.35 152912[93:SSi:152911.0,78151.0,78154.0,137741.0,152256.0,152902.0] || -> . % 76.16/76.35 152913[93:Spt:152912.0,152907.0,152909.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.35 152914[93:Spt:152912.0,152907.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 152918[93:Res:152914.0,61.1] always3(s20) || -> . % 76.16/76.35 152919[93:SSi:152918.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.35 152920[91:Spt:152919.0,152255.0,152256.0] || until2p7(s19)*+ -> . % 76.16/76.35 152921[91:Spt:152919.0,152255.1] || -> node4(s18)*. % 76.16/76.35 152923[91:MRR:864.0,152921.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.35 152926[91:Res:53.1,152923.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.35 152931[92:Spt:152926.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 152933[92:Res:152931.0,61.1] always3(s18) || -> . % 76.16/76.35 152934[92:SSi:152933.0,78146.0,78150.0,137740.0,152254.0,152921.0] || -> . % 76.16/76.35 152935[92:Spt:152934.0,152926.0,152931.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.35 152936[92:Spt:152934.0,152926.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 152940[92:Res:152936.0,61.1] always3(s19) || -> . % 76.16/76.35 152941[92:SSi:152940.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.35 152942[90:Spt:152941.0,152253.0,152254.0] || until2p7(s18)*+ -> . % 76.16/76.35 152943[90:Spt:152941.0,152253.1] || -> node4(s17)*. % 76.16/76.35 152945[90:MRR:867.0,152943.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.35 152948[90:Res:53.1,152945.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.35 152950[91:Spt:152948.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 152952[91:Res:152950.0,61.1] always3(s17) || -> . % 76.16/76.35 152953[91:SSi:152952.0,78142.0,78145.0,137739.0,152252.0,152943.0] || -> . % 76.16/76.35 152954[91:Spt:152953.0,152948.0,152950.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.35 152955[91:Spt:152953.0,152948.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 152959[91:Res:152955.0,61.1] always3(s18) || -> . % 76.16/76.35 152960[91:SSi:152959.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.35 152961[89:Spt:152960.0,152251.0,152252.0] || until2p7(s17)*+ -> . % 76.16/76.35 152962[89:Spt:152960.0,152251.1] || -> node4(s16)*. % 76.16/76.35 152964[89:MRR:870.0,152962.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.35 152967[89:Res:53.1,152964.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.35 152969[89:MRR:152967.0,152241.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 152971[89:Res:152969.0,61.1] always3(s17) || -> . % 76.16/76.35 152972[89:SSi:152971.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.35 152973[87:Spt:152972.0,152117.0,152120.0] || trans(s49,s16)*+ -> . % 76.16/76.35 152974[87:Spt:152972.0,152117.1,152117.2,152117.3,152117.4,152117.5,152117.6,152117.7,152117.8,152117.9,152117.10,152117.11,152117.12] || -> trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.35 152976[87:MRR:152119.1,152973.0] xuntil6(s49) || -> trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.35 152977[88:Spt:152974.0] || -> trans(s49,s15)*. % 76.16/76.35 152978[88:Res:152977.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s15)*. % 76.16/76.35 152980[88:Res:152977.0,60.0] || -> node2(s49,s15)*. % 76.16/76.35 152981[88:SSi:152978.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s15)*. % 76.16/76.35 152982[88:Res:152980.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 153097[88:SoR:152982.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 153099[88:SoR:153097.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)* xuntil6(s49). % 76.16/76.35 153100[88:SSi:153099.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s15,c_busy)* xuntil6(s49). % 76.16/76.35 153101[89:Spt:153100.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 153103[89:Res:153101.0,61.1] always3(s15) || -> . % 76.16/76.35 153104[89:SSi:153103.0,78133.0,78136.0,137737.0] || -> . % 76.16/76.35 153105[89:Spt:153104.0,153100.1,153101.0] || m_main_v_state(s15,c_busy)*+ -> . % 76.16/76.35 153106[89:Spt:153104.0,153100.0,153100.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.35 153110[89:MRR:153097.2,153105.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.35 153111[89:Res:53.1,153106.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.35 153113[89:MRR:153111.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.35 153114[89:MRR:152981.0,153113.0] || -> until2p7(s15)*. % 76.16/76.35 153115[89:MRR:211.0,153114.0] || -> until2p7(s16)* node4(s15). % 76.16/76.35 153116[90:Spt:153115.0] || -> until2p7(s16)*. % 76.16/76.35 153117[90:MRR:212.0,153116.0] || -> until2p7(s17)* node4(s16). % 76.16/76.35 153118[91:Spt:153117.0] || -> until2p7(s17)*. % 76.16/76.35 153119[91:MRR:213.0,153118.0] || -> until2p7(s18)* node4(s17). % 76.16/76.35 153120[92:Spt:153119.0] || -> until2p7(s18)*. % 76.16/76.35 153121[92:MRR:214.0,153120.0] || -> until2p7(s19)* node4(s18). % 76.16/76.35 153122[93:Spt:153121.0] || -> until2p7(s19)*. % 76.16/76.35 153123[93:MRR:215.0,153122.0] || -> until2p7(s20)* node4(s19). % 76.16/76.35 153124[94:Spt:153123.0] || -> until2p7(s20)*. % 76.16/76.35 153125[94:MRR:216.0,153124.0] || -> until2p7(s21)* node4(s20). % 76.16/76.35 153126[95:Spt:153125.0] || -> until2p7(s21)*. % 76.16/76.35 153127[95:MRR:217.0,153126.0] || -> until2p7(s22)* node4(s21). % 76.16/76.35 153128[96:Spt:153127.0] || -> until2p7(s22)*. % 76.16/76.35 153129[96:MRR:218.0,153128.0] || -> until2p7(s23)* node4(s22). % 76.16/76.35 153130[97:Spt:153129.0] || -> until2p7(s23)*. % 76.16/76.35 153131[97:MRR:219.0,153130.0] || -> until2p7(s24)* node4(s23). % 76.16/76.35 153132[98:Spt:153131.0] || -> until2p7(s24)*. % 76.16/76.35 153133[98:MRR:220.0,153132.0] || -> until2p7(s25)* node4(s24). % 76.16/76.35 153134[99:Spt:153133.0] || -> until2p7(s25)*. % 76.16/76.35 153135[99:MRR:221.0,153134.0] || -> until2p7(s26)* node4(s25). % 76.16/76.35 153136[100:Spt:153135.0] || -> until2p7(s26)*. % 76.16/76.35 153137[100:MRR:222.0,153136.0] || -> until2p7(s27)* node4(s26). % 76.16/76.35 153138[101:Spt:153137.0] || -> until2p7(s27)*. % 76.16/76.35 153139[101:MRR:223.0,153138.0] || -> until2p7(s28)* node4(s27). % 76.16/76.35 153140[102:Spt:153139.0] || -> until2p7(s28)*. % 76.16/76.35 153141[102:MRR:224.0,153140.0] || -> until2p7(s29)* node4(s28). % 76.16/76.35 153142[103:Spt:153141.0] || -> until2p7(s29)*. % 76.16/76.35 153143[103:MRR:225.0,153142.0] || -> until2p7(s30)* node4(s29). % 76.16/76.35 153144[104:Spt:153143.0] || -> until2p7(s30)*. % 76.16/76.35 153145[104:MRR:226.0,153144.0] || -> until2p7(s31)* node4(s30). % 76.16/76.35 153146[105:Spt:153145.0] || -> until2p7(s31)*. % 76.16/76.35 153147[105:MRR:227.0,153146.0] || -> until2p7(s32)* node4(s31). % 76.16/76.35 153148[106:Spt:153147.0] || -> until2p7(s32)*. % 76.16/76.35 153149[106:MRR:228.0,153148.0] || -> until2p7(s33)* node4(s32). % 76.16/76.35 153150[107:Spt:153149.0] || -> until2p7(s33)*. % 76.16/76.35 153151[107:MRR:229.0,153150.0] || -> until2p7(s34)* node4(s33). % 76.16/76.35 153152[108:Spt:153151.0] || -> until2p7(s34)*. % 76.16/76.35 153153[108:MRR:230.0,153152.0] || -> until2p7(s35)* node4(s34). % 76.16/76.35 153154[109:Spt:153153.0] || -> until2p7(s35)*. % 76.16/76.35 153155[109:MRR:231.0,153154.0] || -> until2p7(s36)* node4(s35). % 76.16/76.35 153156[110:Spt:153155.0] || -> until2p7(s36)*. % 76.16/76.35 153157[110:MRR:232.0,153156.0] || -> until2p7(s37)* node4(s36). % 76.16/76.35 153158[111:Spt:153157.0] || -> until2p7(s37)*. % 76.16/76.35 153159[111:MRR:235.0,153158.0] || -> until2p7(s38)* node4(s37). % 76.16/76.35 153160[112:Spt:153159.0] || -> until2p7(s38)*. % 76.16/76.35 153161[112:MRR:236.0,153160.0] || -> until2p7(s39)* node4(s38). % 76.16/76.35 153162[113:Spt:153161.0] || -> until2p7(s39)*. % 76.16/76.35 153163[113:MRR:237.0,153162.0] || -> until2p7(s40)* node4(s39). % 76.16/76.35 153164[114:Spt:153163.0] || -> until2p7(s40)*. % 76.16/76.35 153165[114:MRR:238.0,153164.0] || -> until2p7(s41)* node4(s40). % 76.16/76.35 153166[115:Spt:153165.0] || -> until2p7(s41)*. % 76.16/76.35 153167[115:MRR:239.0,153166.0] || -> until2p7(s42)* node4(s41). % 76.16/76.35 153168[116:Spt:153167.0] || -> until2p7(s42)*. % 76.16/76.35 153169[116:MRR:240.0,153168.0] || -> until2p7(s43)* node4(s42). % 76.16/76.35 153170[117:Spt:153169.0] || -> until2p7(s43)*. % 76.16/76.35 153171[117:MRR:241.0,153170.0] || -> until2p7(s44)* node4(s43). % 76.16/76.35 153172[118:Spt:153171.0] || -> until2p7(s44)*. % 76.16/76.35 153173[118:MRR:539.0,153172.0] || -> until2p7(s45)* node4(s44). % 76.16/76.35 153174[119:Spt:153173.0] || -> until2p7(s45)*. % 76.16/76.35 153175[119:MRR:544.0,153174.0] || -> until2p7(s46)* node4(s45). % 76.16/76.35 153176[120:Spt:153175.0] || -> until2p7(s46)*. % 76.16/76.35 153177[120:MRR:549.0,153176.0] || -> until2p7(s47)* node4(s46). % 76.16/76.35 153178[121:Spt:153177.0] || -> until2p7(s47)*. % 76.16/76.35 153179[121:MRR:554.0,153178.0] || -> until2p7(s48)* node4(s47). % 76.16/76.35 153180[122:Spt:153179.0] || -> until2p7(s48)*. % 76.16/76.35 153181[122:MRR:559.0,153180.0] || -> until2p7(s49)* node4(s48). % 76.16/76.35 153182[123:Spt:153181.0] || -> until2p7(s49)*. % 76.16/76.35 153183[123:MRR:194.0,153182.0] || -> node4(s49)*. % 76.16/76.35 153184[123:MRR:153110.0,153183.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.35 153185[123:Res:53.1,153184.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.35 153187[123:MRR:153185.0,78381.0] || -> . % 76.16/76.35 153188[123:Spt:153187.0,153181.0,153182.0] || until2p7(s49)*+ -> . % 76.16/76.35 153189[123:Spt:153187.0,153181.1] || -> node4(s48)*. % 76.16/76.35 153190[123:MRR:78384.0,153189.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.35 153193[123:Res:53.1,153190.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 153196[123:Res:153193.0,61.1] always3(s48) || -> . % 76.16/76.35 153197[123:SSi:153196.0,78281.0,78387.0,137770.0,153180.0,153189.0] || -> . % 76.16/76.35 153198[122:Spt:153197.0,153179.0,153180.0] || until2p7(s48)*+ -> . % 76.16/76.35 153199[122:Spt:153197.0,153179.1] || -> node4(s47)*. % 76.16/76.35 153201[122:MRR:777.0,153199.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.35 153216[122:Res:53.1,153201.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.35 153218[123:Spt:153216.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 153220[123:Res:153218.0,61.1] always3(s47) || -> . % 76.16/76.35 153221[123:SSi:153220.0,78277.0,78280.0,137769.0,153178.0,153199.0] || -> . % 76.16/76.35 153222[123:Spt:153221.0,153216.0,153218.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.35 153223[123:Spt:153221.0,153216.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 153227[123:Res:153223.0,61.1] always3(s48) || -> . % 76.16/76.35 153228[123:SSi:153227.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.35 153229[121:Spt:153228.0,153177.0,153178.0] || until2p7(s47)*+ -> . % 76.16/76.35 153230[121:Spt:153228.0,153177.1] || -> node4(s46)*. % 76.16/76.35 153232[121:MRR:780.0,153230.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.35 153242[121:Res:53.1,153232.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.35 153244[122:Spt:153242.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 153246[122:Res:153244.0,61.1] always3(s46) || -> . % 76.16/76.35 153247[122:SSi:153246.0,78272.0,78276.0,137768.0,153176.0,153230.0] || -> . % 76.16/76.35 153248[122:Spt:153247.0,153242.0,153244.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.35 153249[122:Spt:153247.0,153242.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 153253[122:Res:153249.0,61.1] always3(s47) || -> . % 76.16/76.35 153254[122:SSi:153253.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.35 153255[120:Spt:153254.0,153175.0,153176.0] || until2p7(s46)*+ -> . % 76.16/76.35 153256[120:Spt:153254.0,153175.1] || -> node4(s45)*. % 76.16/76.35 153258[120:MRR:783.0,153256.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.35 153261[120:Res:53.1,153258.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.35 153263[121:Spt:153261.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 153265[121:Res:153263.0,61.1] always3(s45) || -> . % 76.16/76.35 153266[121:SSi:153265.0,78268.0,78271.0,137767.0,153174.0,153256.0] || -> . % 76.16/76.35 153267[121:Spt:153266.0,153261.0,153263.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.35 153268[121:Spt:153266.0,153261.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 153272[121:Res:153268.0,61.1] always3(s46) || -> . % 76.16/76.35 153273[121:SSi:153272.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.35 153274[119:Spt:153273.0,153173.0,153174.0] || until2p7(s45)*+ -> . % 76.16/76.35 153275[119:Spt:153273.0,153173.1] || -> node4(s44)*. % 76.16/76.35 153277[119:MRR:786.0,153275.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.35 153280[119:Res:53.1,153277.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.35 153282[120:Spt:153280.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 153284[120:Res:153282.0,61.1] always3(s44) || -> . % 76.16/76.35 153285[120:SSi:153284.0,78263.0,78267.0,137766.0,153172.0,153275.0] || -> . % 76.16/76.35 153286[120:Spt:153285.0,153280.0,153282.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.35 153287[120:Spt:153285.0,153280.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 153291[120:Res:153287.0,61.1] always3(s45) || -> . % 76.16/76.35 153292[120:SSi:153291.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.35 153293[118:Spt:153292.0,153171.0,153172.0] || until2p7(s44)*+ -> . % 76.16/76.35 153294[118:Spt:153292.0,153171.1] || -> node4(s43)*. % 76.16/76.35 153296[118:MRR:789.0,153294.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.35 153299[118:Res:53.1,153296.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.35 153304[119:Spt:153299.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 153306[119:Res:153304.0,61.1] always3(s43) || -> . % 76.16/76.35 153307[119:SSi:153306.0,78259.0,78262.0,137765.0,153170.0,153294.0] || -> . % 76.16/76.35 153308[119:Spt:153307.0,153299.0,153304.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.35 153309[119:Spt:153307.0,153299.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 153313[119:Res:153309.0,61.1] always3(s44) || -> . % 76.16/76.35 153314[119:SSi:153313.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.35 153315[117:Spt:153314.0,153169.0,153170.0] || until2p7(s43)*+ -> . % 76.16/76.35 153316[117:Spt:153314.0,153169.1] || -> node4(s42)*. % 76.16/76.35 153318[117:MRR:792.0,153316.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.35 153321[117:Res:53.1,153318.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.35 153323[118:Spt:153321.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 153325[118:Res:153323.0,61.1] always3(s42) || -> . % 76.16/76.35 153326[118:SSi:153325.0,78254.0,78258.0,137764.0,153168.0,153316.0] || -> . % 76.16/76.35 153327[118:Spt:153326.0,153321.0,153323.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.35 153328[118:Spt:153326.0,153321.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 153332[118:Res:153328.0,61.1] always3(s43) || -> . % 76.16/76.35 153333[118:SSi:153332.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.35 153334[116:Spt:153333.0,153167.0,153168.0] || until2p7(s42)*+ -> . % 76.16/76.35 153335[116:Spt:153333.0,153167.1] || -> node4(s41)*. % 76.16/76.35 153337[116:MRR:795.0,153335.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.35 153340[116:Res:53.1,153337.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.35 153342[117:Spt:153340.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 153344[117:Res:153342.0,61.1] always3(s41) || -> . % 76.16/76.35 153345[117:SSi:153344.0,78250.0,78253.0,137763.0,153166.0,153335.0] || -> . % 76.16/76.35 153346[117:Spt:153345.0,153340.0,153342.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.35 153347[117:Spt:153345.0,153340.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 153351[117:Res:153347.0,61.1] always3(s42) || -> . % 76.16/76.35 153352[117:SSi:153351.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.35 153353[115:Spt:153352.0,153165.0,153166.0] || until2p7(s41)*+ -> . % 76.16/76.35 153354[115:Spt:153352.0,153165.1] || -> node4(s40)*. % 76.16/76.35 153356[115:MRR:798.0,153354.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.35 153359[115:Res:53.1,153356.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.35 153361[116:Spt:153359.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 153363[116:Res:153361.0,61.1] always3(s40) || -> . % 76.16/76.35 153364[116:SSi:153363.0,78245.0,78249.0,137762.0,153164.0,153354.0] || -> . % 76.16/76.35 153365[116:Spt:153364.0,153359.0,153361.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.35 153366[116:Spt:153364.0,153359.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 153370[116:Res:153366.0,61.1] always3(s41) || -> . % 76.16/76.35 153371[116:SSi:153370.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.35 153372[114:Spt:153371.0,153163.0,153164.0] || until2p7(s40)*+ -> . % 76.16/76.35 153373[114:Spt:153371.0,153163.1] || -> node4(s39)*. % 76.16/76.35 153375[114:MRR:801.0,153373.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.35 153378[114:Res:53.1,153375.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.35 153383[115:Spt:153378.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 153385[115:Res:153383.0,61.1] always3(s39) || -> . % 76.16/76.35 153386[115:SSi:153385.0,78241.0,78244.0,137761.0,153162.0,153373.0] || -> . % 76.16/76.35 153387[115:Spt:153386.0,153378.0,153383.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.35 153388[115:Spt:153386.0,153378.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 153392[115:Res:153388.0,61.1] always3(s40) || -> . % 76.16/76.35 153393[115:SSi:153392.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.35 153394[113:Spt:153393.0,153161.0,153162.0] || until2p7(s39)*+ -> . % 76.16/76.35 153395[113:Spt:153393.0,153161.1] || -> node4(s38)*. % 76.16/76.35 153397[113:MRR:804.0,153395.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.35 153400[113:Res:53.1,153397.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.35 153402[114:Spt:153400.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 153404[114:Res:153402.0,61.1] always3(s38) || -> . % 76.16/76.35 153405[114:SSi:153404.0,78236.0,78240.0,137760.0,153160.0,153395.0] || -> . % 76.16/76.35 153406[114:Spt:153405.0,153400.0,153402.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.35 153407[114:Spt:153405.0,153400.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 153411[114:Res:153407.0,61.1] always3(s39) || -> . % 76.16/76.35 153412[114:SSi:153411.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.35 153413[112:Spt:153412.0,153159.0,153160.0] || until2p7(s38)*+ -> . % 76.16/76.35 153414[112:Spt:153412.0,153159.1] || -> node4(s37)*. % 76.16/76.35 153416[112:MRR:807.0,153414.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.35 153419[112:Res:53.1,153416.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.35 153421[113:Spt:153419.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 153423[113:Res:153421.0,61.1] always3(s37) || -> . % 76.16/76.35 153424[113:SSi:153423.0,78232.0,78235.0,137759.0,153158.0,153414.0] || -> . % 76.16/76.35 153425[113:Spt:153424.0,153419.0,153421.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.35 153426[113:Spt:153424.0,153419.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 153430[113:Res:153426.0,61.1] always3(s38) || -> . % 76.16/76.35 153431[113:SSi:153430.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.35 153432[111:Spt:153431.0,153157.0,153158.0] || until2p7(s37)*+ -> . % 76.16/76.35 153433[111:Spt:153431.0,153157.1] || -> node4(s36)*. % 76.16/76.35 153435[111:MRR:810.0,153433.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.35 153438[111:Res:53.1,153435.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.35 153440[112:Spt:153438.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 153442[112:Res:153440.0,61.1] always3(s36) || -> . % 76.16/76.35 153443[112:SSi:153442.0,78227.0,78231.0,137758.0,153156.0,153433.0] || -> . % 76.16/76.35 153444[112:Spt:153443.0,153438.0,153440.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.35 153445[112:Spt:153443.0,153438.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 153449[112:Res:153445.0,61.1] always3(s37) || -> . % 76.16/76.35 153450[112:SSi:153449.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.35 153451[110:Spt:153450.0,153155.0,153156.0] || until2p7(s36)*+ -> . % 76.16/76.35 153452[110:Spt:153450.0,153155.1] || -> node4(s35)*. % 76.16/76.35 153454[110:MRR:813.0,153452.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.35 153457[110:Res:53.1,153454.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.35 153462[111:Spt:153457.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 153464[111:Res:153462.0,61.1] always3(s35) || -> . % 76.16/76.35 153465[111:SSi:153464.0,78223.0,78226.0,137757.0,153154.0,153452.0] || -> . % 76.16/76.35 153466[111:Spt:153465.0,153457.0,153462.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.35 153467[111:Spt:153465.0,153457.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 153471[111:Res:153467.0,61.1] always3(s36) || -> . % 76.16/76.35 153472[111:SSi:153471.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.35 153473[109:Spt:153472.0,153153.0,153154.0] || until2p7(s35)*+ -> . % 76.16/76.35 153474[109:Spt:153472.0,153153.1] || -> node4(s34)*. % 76.16/76.35 153476[109:MRR:816.0,153474.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.35 153479[109:Res:53.1,153476.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.35 153481[110:Spt:153479.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 153483[110:Res:153481.0,61.1] always3(s34) || -> . % 76.16/76.35 153484[110:SSi:153483.0,78218.0,78222.0,137756.0,153152.0,153474.0] || -> . % 76.16/76.35 153485[110:Spt:153484.0,153479.0,153481.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.35 153486[110:Spt:153484.0,153479.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 153490[110:Res:153486.0,61.1] always3(s35) || -> . % 76.16/76.35 153491[110:SSi:153490.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.35 153492[108:Spt:153491.0,153151.0,153152.0] || until2p7(s34)*+ -> . % 76.16/76.35 153493[108:Spt:153491.0,153151.1] || -> node4(s33)*. % 76.16/76.35 153495[108:MRR:819.0,153493.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.35 153498[108:Res:53.1,153495.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.35 153500[109:Spt:153498.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 153502[109:Res:153500.0,61.1] always3(s33) || -> . % 76.16/76.35 153503[109:SSi:153502.0,78214.0,78217.0,137755.0,153150.0,153493.0] || -> . % 76.16/76.35 153504[109:Spt:153503.0,153498.0,153500.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.35 153505[109:Spt:153503.0,153498.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 153509[109:Res:153505.0,61.1] always3(s34) || -> . % 76.16/76.35 153510[109:SSi:153509.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.35 153511[107:Spt:153510.0,153149.0,153150.0] || until2p7(s33)*+ -> . % 76.16/76.35 153512[107:Spt:153510.0,153149.1] || -> node4(s32)*. % 76.16/76.35 153514[107:MRR:822.0,153512.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.35 153517[107:Res:53.1,153514.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.35 153519[108:Spt:153517.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 153521[108:Res:153519.0,61.1] always3(s32) || -> . % 76.16/76.35 153522[108:SSi:153521.0,78209.0,78213.0,137754.0,153148.0,153512.0] || -> . % 76.16/76.35 153523[108:Spt:153522.0,153517.0,153519.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.35 153524[108:Spt:153522.0,153517.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 153528[108:Res:153524.0,61.1] always3(s33) || -> . % 76.16/76.35 153529[108:SSi:153528.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.35 153530[106:Spt:153529.0,153147.0,153148.0] || until2p7(s32)*+ -> . % 76.16/76.35 153531[106:Spt:153529.0,153147.1] || -> node4(s31)*. % 76.16/76.35 153533[106:MRR:825.0,153531.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.35 153536[106:Res:53.1,153533.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.35 153541[107:Spt:153536.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 153543[107:Res:153541.0,61.1] always3(s31) || -> . % 76.16/76.35 153544[107:SSi:153543.0,78205.0,78208.0,137753.0,153146.0,153531.0] || -> . % 76.16/76.35 153545[107:Spt:153544.0,153536.0,153541.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.35 153546[107:Spt:153544.0,153536.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 153550[107:Res:153546.0,61.1] always3(s32) || -> . % 76.16/76.35 153551[107:SSi:153550.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.35 153552[105:Spt:153551.0,153145.0,153146.0] || until2p7(s31)*+ -> . % 76.16/76.35 153553[105:Spt:153551.0,153145.1] || -> node4(s30)*. % 76.16/76.35 153555[105:MRR:828.0,153553.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.35 153558[105:Res:53.1,153555.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.35 153560[106:Spt:153558.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 153562[106:Res:153560.0,61.1] always3(s30) || -> . % 76.16/76.35 153563[106:SSi:153562.0,78200.0,78204.0,137752.0,153144.0,153553.0] || -> . % 76.16/76.35 153564[106:Spt:153563.0,153558.0,153560.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.35 153565[106:Spt:153563.0,153558.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 153569[106:Res:153565.0,61.1] always3(s31) || -> . % 76.16/76.35 153570[106:SSi:153569.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.35 153571[104:Spt:153570.0,153143.0,153144.0] || until2p7(s30)*+ -> . % 76.16/76.35 153572[104:Spt:153570.0,153143.1] || -> node4(s29)*. % 76.16/76.35 153574[104:MRR:831.0,153572.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.35 153577[104:Res:53.1,153574.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.35 153579[105:Spt:153577.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 153581[105:Res:153579.0,61.1] always3(s29) || -> . % 76.16/76.35 153582[105:SSi:153581.0,78196.0,78199.0,137751.0,153142.0,153572.0] || -> . % 76.16/76.35 153583[105:Spt:153582.0,153577.0,153579.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.35 153584[105:Spt:153582.0,153577.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 153588[105:Res:153584.0,61.1] always3(s30) || -> . % 76.16/76.35 153589[105:SSi:153588.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.35 153590[103:Spt:153589.0,153141.0,153142.0] || until2p7(s29)*+ -> . % 76.16/76.35 153591[103:Spt:153589.0,153141.1] || -> node4(s28)*. % 76.16/76.35 153593[103:MRR:834.0,153591.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.35 153596[103:Res:53.1,153593.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.35 153598[104:Spt:153596.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 153600[104:Res:153598.0,61.1] always3(s28) || -> . % 76.16/76.35 153601[104:SSi:153600.0,78191.0,78195.0,137750.0,153140.0,153591.0] || -> . % 76.16/76.35 153602[104:Spt:153601.0,153596.0,153598.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.35 153603[104:Spt:153601.0,153596.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 153607[104:Res:153603.0,61.1] always3(s29) || -> . % 76.16/76.35 153608[104:SSi:153607.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.35 153609[102:Spt:153608.0,153139.0,153140.0] || until2p7(s28)*+ -> . % 76.16/76.35 153610[102:Spt:153608.0,153139.1] || -> node4(s27)*. % 76.16/76.35 153612[102:MRR:837.0,153610.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.35 153615[102:Res:53.1,153612.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.35 153620[103:Spt:153615.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 153622[103:Res:153620.0,61.1] always3(s27) || -> . % 76.16/76.35 153623[103:SSi:153622.0,78187.0,78190.0,137749.0,153138.0,153610.0] || -> . % 76.16/76.35 153624[103:Spt:153623.0,153615.0,153620.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.35 153625[103:Spt:153623.0,153615.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 153629[103:Res:153625.0,61.1] always3(s28) || -> . % 76.16/76.35 153630[103:SSi:153629.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.35 153631[101:Spt:153630.0,153137.0,153138.0] || until2p7(s27)*+ -> . % 76.16/76.35 153632[101:Spt:153630.0,153137.1] || -> node4(s26)*. % 76.16/76.35 153634[101:MRR:840.0,153632.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.35 153637[101:Res:53.1,153634.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.35 153639[102:Spt:153637.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 153641[102:Res:153639.0,61.1] always3(s26) || -> . % 76.16/76.35 153642[102:SSi:153641.0,78182.0,78186.0,137748.0,153136.0,153632.0] || -> . % 76.16/76.35 153643[102:Spt:153642.0,153637.0,153639.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.35 153644[102:Spt:153642.0,153637.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 153648[102:Res:153644.0,61.1] always3(s27) || -> . % 76.16/76.35 153649[102:SSi:153648.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.35 153650[100:Spt:153649.0,153135.0,153136.0] || until2p7(s26)*+ -> . % 76.16/76.35 153651[100:Spt:153649.0,153135.1] || -> node4(s25)*. % 76.16/76.35 153653[100:MRR:843.0,153651.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.35 153656[100:Res:53.1,153653.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.35 153658[101:Spt:153656.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 153660[101:Res:153658.0,61.1] always3(s25) || -> . % 76.16/76.35 153661[101:SSi:153660.0,78178.0,78181.0,137747.0,153134.0,153651.0] || -> . % 76.16/76.35 153662[101:Spt:153661.0,153656.0,153658.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.35 153663[101:Spt:153661.0,153656.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 153667[101:Res:153663.0,61.1] always3(s26) || -> . % 76.16/76.35 153668[101:SSi:153667.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.35 153669[99:Spt:153668.0,153133.0,153134.0] || until2p7(s25)*+ -> . % 76.16/76.35 153670[99:Spt:153668.0,153133.1] || -> node4(s24)*. % 76.16/76.35 153672[99:MRR:846.0,153670.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.35 153675[99:Res:53.1,153672.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.35 153677[100:Spt:153675.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 153679[100:Res:153677.0,61.1] always3(s24) || -> . % 76.16/76.35 153680[100:SSi:153679.0,78173.0,78177.0,137746.0,153132.0,153670.0] || -> . % 76.16/76.35 153681[100:Spt:153680.0,153675.0,153677.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.35 153682[100:Spt:153680.0,153675.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 153686[100:Res:153682.0,61.1] always3(s25) || -> . % 76.16/76.35 153687[100:SSi:153686.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.35 153688[98:Spt:153687.0,153131.0,153132.0] || until2p7(s24)*+ -> . % 76.16/76.35 153689[98:Spt:153687.0,153131.1] || -> node4(s23)*. % 76.16/76.35 153691[98:MRR:849.0,153689.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.35 153694[98:Res:53.1,153691.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.35 153699[99:Spt:153694.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 153701[99:Res:153699.0,61.1] always3(s23) || -> . % 76.16/76.35 153702[99:SSi:153701.0,78169.0,78172.0,137745.0,153130.0,153689.0] || -> . % 76.16/76.35 153703[99:Spt:153702.0,153694.0,153699.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.35 153704[99:Spt:153702.0,153694.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 153708[99:Res:153704.0,61.1] always3(s24) || -> . % 76.16/76.35 153709[99:SSi:153708.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.35 153710[97:Spt:153709.0,153129.0,153130.0] || until2p7(s23)*+ -> . % 76.16/76.35 153711[97:Spt:153709.0,153129.1] || -> node4(s22)*. % 76.16/76.35 153713[97:MRR:852.0,153711.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.35 153716[97:Res:53.1,153713.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.35 153718[98:Spt:153716.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 153720[98:Res:153718.0,61.1] always3(s22) || -> . % 76.16/76.35 153721[98:SSi:153720.0,78164.0,78168.0,137744.0,153128.0,153711.0] || -> . % 76.16/76.35 153722[98:Spt:153721.0,153716.0,153718.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.35 153723[98:Spt:153721.0,153716.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 153727[98:Res:153723.0,61.1] always3(s23) || -> . % 76.16/76.35 153728[98:SSi:153727.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.35 153729[96:Spt:153728.0,153127.0,153128.0] || until2p7(s22)*+ -> . % 76.16/76.35 153730[96:Spt:153728.0,153127.1] || -> node4(s21)*. % 76.16/76.35 153732[96:MRR:855.0,153730.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.35 153735[96:Res:53.1,153732.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.35 153737[97:Spt:153735.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 153739[97:Res:153737.0,61.1] always3(s21) || -> . % 76.16/76.35 153740[97:SSi:153739.0,78160.0,78163.0,137743.0,153126.0,153730.0] || -> . % 76.16/76.35 153741[97:Spt:153740.0,153735.0,153737.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.35 153742[97:Spt:153740.0,153735.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 153746[97:Res:153742.0,61.1] always3(s22) || -> . % 76.16/76.35 153747[97:SSi:153746.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.35 153748[95:Spt:153747.0,153125.0,153126.0] || until2p7(s21)*+ -> . % 76.16/76.35 153749[95:Spt:153747.0,153125.1] || -> node4(s20)*. % 76.16/76.35 153751[95:MRR:858.0,153749.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.35 153754[95:Res:53.1,153751.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.35 153756[96:Spt:153754.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 153758[96:Res:153756.0,61.1] always3(s20) || -> . % 76.16/76.35 153759[96:SSi:153758.0,78155.0,78159.0,137742.0,153124.0,153749.0] || -> . % 76.16/76.35 153760[96:Spt:153759.0,153754.0,153756.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.35 153761[96:Spt:153759.0,153754.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 153765[96:Res:153761.0,61.1] always3(s21) || -> . % 76.16/76.35 153766[96:SSi:153765.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.35 153767[94:Spt:153766.0,153123.0,153124.0] || until2p7(s20)*+ -> . % 76.16/76.35 153768[94:Spt:153766.0,153123.1] || -> node4(s19)*. % 76.16/76.35 153770[94:MRR:861.0,153768.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.35 153773[94:Res:53.1,153770.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.35 153778[95:Spt:153773.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 153780[95:Res:153778.0,61.1] always3(s19) || -> . % 76.16/76.35 153781[95:SSi:153780.0,78151.0,78154.0,137741.0,153122.0,153768.0] || -> . % 76.16/76.35 153782[95:Spt:153781.0,153773.0,153778.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.35 153783[95:Spt:153781.0,153773.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 153787[95:Res:153783.0,61.1] always3(s20) || -> . % 76.16/76.35 153788[95:SSi:153787.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.35 153789[93:Spt:153788.0,153121.0,153122.0] || until2p7(s19)*+ -> . % 76.16/76.35 153790[93:Spt:153788.0,153121.1] || -> node4(s18)*. % 76.16/76.35 153792[93:MRR:864.0,153790.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.35 153795[93:Res:53.1,153792.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.35 153797[94:Spt:153795.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 153799[94:Res:153797.0,61.1] always3(s18) || -> . % 76.16/76.35 153800[94:SSi:153799.0,78146.0,78150.0,137740.0,153120.0,153790.0] || -> . % 76.16/76.35 153801[94:Spt:153800.0,153795.0,153797.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.35 153802[94:Spt:153800.0,153795.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 153806[94:Res:153802.0,61.1] always3(s19) || -> . % 76.16/76.35 153807[94:SSi:153806.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.35 153808[92:Spt:153807.0,153119.0,153120.0] || until2p7(s18)*+ -> . % 76.16/76.35 153809[92:Spt:153807.0,153119.1] || -> node4(s17)*. % 76.16/76.35 153811[92:MRR:867.0,153809.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.35 153814[92:Res:53.1,153811.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.35 153816[93:Spt:153814.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 153818[93:Res:153816.0,61.1] always3(s17) || -> . % 76.16/76.35 153819[93:SSi:153818.0,78142.0,78145.0,137739.0,153118.0,153809.0] || -> . % 76.16/76.35 153820[93:Spt:153819.0,153814.0,153816.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.35 153821[93:Spt:153819.0,153814.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 153825[93:Res:153821.0,61.1] always3(s18) || -> . % 76.16/76.35 153826[93:SSi:153825.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.35 153827[91:Spt:153826.0,153117.0,153118.0] || until2p7(s17)*+ -> . % 76.16/76.35 153828[91:Spt:153826.0,153117.1] || -> node4(s16)*. % 76.16/76.35 153830[91:MRR:870.0,153828.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.35 153833[91:Res:53.1,153830.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.35 153835[92:Spt:153833.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 153837[92:Res:153835.0,61.1] always3(s16) || -> . % 76.16/76.35 153838[92:SSi:153837.0,78137.0,78141.0,137738.0,153116.0,153828.0] || -> . % 76.16/76.35 153839[92:Spt:153838.0,153833.0,153835.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.35 153840[92:Spt:153838.0,153833.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 153844[92:Res:153840.0,61.1] always3(s17) || -> . % 76.16/76.35 153845[92:SSi:153844.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.35 153846[90:Spt:153845.0,153115.0,153116.0] || until2p7(s16)*+ -> . % 76.16/76.35 153847[90:Spt:153845.0,153115.1] || -> node4(s15)*. % 76.16/76.35 153849[90:MRR:873.0,153847.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.35 153852[90:Res:53.1,153849.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.35 153854[90:MRR:153852.0,153105.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 153859[90:Res:153854.0,61.1] always3(s16) || -> . % 76.16/76.35 153860[90:SSi:153859.0,78137.0,78141.0,137738.0] || -> . % 76.16/76.35 153861[88:Spt:153860.0,152974.0,152977.0] || trans(s49,s15)*+ -> . % 76.16/76.35 153862[88:Spt:153860.0,152974.1,152974.2,152974.3,152974.4,152974.5,152974.6,152974.7,152974.8,152974.9,152974.10,152974.11] || -> trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.35 153864[88:MRR:152976.1,153861.0] xuntil6(s49) || -> trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.35 153865[89:Spt:153862.0] || -> trans(s49,s14)*. % 76.16/76.35 153866[89:Res:153865.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s14)*. % 76.16/76.35 153868[89:Res:153865.0,60.0] || -> node2(s49,s14)*. % 76.16/76.35 153869[89:SSi:153866.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s14)*. % 76.16/76.35 153870[89:Res:153868.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)*. % 76.16/76.35 153986[89:SoR:153870.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)*. % 76.16/76.35 153988[89:SoR:153986.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)* xuntil6(s49). % 76.16/76.35 153989[89:SSi:153988.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s14,c_busy)* xuntil6(s49). % 76.16/76.35 153990[90:Spt:153989.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.35 153992[90:Res:153990.0,61.1] always3(s14) || -> . % 76.16/76.35 153993[90:SSi:153992.0,78128.0,78132.0,137736.0] || -> . % 76.16/76.35 153994[90:Spt:153993.0,153989.1,153990.0] || m_main_v_state(s14,c_busy)*+ -> . % 76.16/76.35 153995[90:Spt:153993.0,153989.0,153989.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.35 153999[90:MRR:153986.2,153994.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.35 154000[90:Res:53.1,153995.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.35 154002[90:MRR:154000.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.35 154003[90:MRR:153869.0,154002.0] || -> until2p7(s14)*. % 76.16/76.35 154004[90:MRR:210.0,154003.0] || -> until2p7(s15)* node4(s14). % 76.16/76.35 154005[91:Spt:154004.0] || -> until2p7(s15)*. % 76.16/76.35 154006[91:MRR:211.0,154005.0] || -> until2p7(s16)* node4(s15). % 76.16/76.35 154007[92:Spt:154006.0] || -> until2p7(s16)*. % 76.16/76.35 154008[92:MRR:212.0,154007.0] || -> until2p7(s17)* node4(s16). % 76.16/76.35 154009[93:Spt:154008.0] || -> until2p7(s17)*. % 76.16/76.35 154010[93:MRR:213.0,154009.0] || -> until2p7(s18)* node4(s17). % 76.16/76.35 154011[94:Spt:154010.0] || -> until2p7(s18)*. % 76.16/76.35 154012[94:MRR:214.0,154011.0] || -> until2p7(s19)* node4(s18). % 76.16/76.35 154013[95:Spt:154012.0] || -> until2p7(s19)*. % 76.16/76.35 154014[95:MRR:215.0,154013.0] || -> until2p7(s20)* node4(s19). % 76.16/76.35 154015[96:Spt:154014.0] || -> until2p7(s20)*. % 76.16/76.35 154016[96:MRR:216.0,154015.0] || -> until2p7(s21)* node4(s20). % 76.16/76.35 154017[97:Spt:154016.0] || -> until2p7(s21)*. % 76.16/76.35 154018[97:MRR:217.0,154017.0] || -> until2p7(s22)* node4(s21). % 76.16/76.35 154019[98:Spt:154018.0] || -> until2p7(s22)*. % 76.16/76.35 154020[98:MRR:218.0,154019.0] || -> until2p7(s23)* node4(s22). % 76.16/76.35 154021[99:Spt:154020.0] || -> until2p7(s23)*. % 76.16/76.35 154022[99:MRR:219.0,154021.0] || -> until2p7(s24)* node4(s23). % 76.16/76.35 154023[100:Spt:154022.0] || -> until2p7(s24)*. % 76.16/76.35 154024[100:MRR:220.0,154023.0] || -> until2p7(s25)* node4(s24). % 76.16/76.35 154025[101:Spt:154024.0] || -> until2p7(s25)*. % 76.16/76.35 154026[101:MRR:221.0,154025.0] || -> until2p7(s26)* node4(s25). % 76.16/76.35 154027[102:Spt:154026.0] || -> until2p7(s26)*. % 76.16/76.35 154028[102:MRR:222.0,154027.0] || -> until2p7(s27)* node4(s26). % 76.16/76.35 154029[103:Spt:154028.0] || -> until2p7(s27)*. % 76.16/76.35 154030[103:MRR:223.0,154029.0] || -> until2p7(s28)* node4(s27). % 76.16/76.35 154031[104:Spt:154030.0] || -> until2p7(s28)*. % 76.16/76.35 154032[104:MRR:224.0,154031.0] || -> until2p7(s29)* node4(s28). % 76.16/76.35 154033[105:Spt:154032.0] || -> until2p7(s29)*. % 76.16/76.35 154034[105:MRR:225.0,154033.0] || -> until2p7(s30)* node4(s29). % 76.16/76.35 154035[106:Spt:154034.0] || -> until2p7(s30)*. % 76.16/76.35 154036[106:MRR:226.0,154035.0] || -> until2p7(s31)* node4(s30). % 76.16/76.35 154037[107:Spt:154036.0] || -> until2p7(s31)*. % 76.16/76.35 154038[107:MRR:227.0,154037.0] || -> until2p7(s32)* node4(s31). % 76.16/76.35 154039[108:Spt:154038.0] || -> until2p7(s32)*. % 76.16/76.35 154040[108:MRR:228.0,154039.0] || -> until2p7(s33)* node4(s32). % 76.16/76.35 154041[109:Spt:154040.0] || -> until2p7(s33)*. % 76.16/76.35 154042[109:MRR:229.0,154041.0] || -> until2p7(s34)* node4(s33). % 76.16/76.35 154043[110:Spt:154042.0] || -> until2p7(s34)*. % 76.16/76.35 154044[110:MRR:230.0,154043.0] || -> until2p7(s35)* node4(s34). % 76.16/76.35 154045[111:Spt:154044.0] || -> until2p7(s35)*. % 76.16/76.35 154046[111:MRR:231.0,154045.0] || -> until2p7(s36)* node4(s35). % 76.16/76.35 154047[112:Spt:154046.0] || -> until2p7(s36)*. % 76.16/76.35 154048[112:MRR:232.0,154047.0] || -> until2p7(s37)* node4(s36). % 76.16/76.35 154049[113:Spt:154048.0] || -> until2p7(s37)*. % 76.16/76.35 154050[113:MRR:235.0,154049.0] || -> until2p7(s38)* node4(s37). % 76.16/76.35 154051[114:Spt:154050.0] || -> until2p7(s38)*. % 76.16/76.35 154052[114:MRR:236.0,154051.0] || -> until2p7(s39)* node4(s38). % 76.16/76.35 154053[115:Spt:154052.0] || -> until2p7(s39)*. % 76.16/76.35 154054[115:MRR:237.0,154053.0] || -> until2p7(s40)* node4(s39). % 76.16/76.35 154055[116:Spt:154054.0] || -> until2p7(s40)*. % 76.16/76.35 154056[116:MRR:238.0,154055.0] || -> until2p7(s41)* node4(s40). % 76.16/76.35 154057[117:Spt:154056.0] || -> until2p7(s41)*. % 76.16/76.35 154058[117:MRR:239.0,154057.0] || -> until2p7(s42)* node4(s41). % 76.16/76.35 154059[118:Spt:154058.0] || -> until2p7(s42)*. % 76.16/76.35 154060[118:MRR:240.0,154059.0] || -> until2p7(s43)* node4(s42). % 76.16/76.35 154061[119:Spt:154060.0] || -> until2p7(s43)*. % 76.16/76.35 154062[119:MRR:241.0,154061.0] || -> until2p7(s44)* node4(s43). % 76.16/76.35 154063[120:Spt:154062.0] || -> until2p7(s44)*. % 76.16/76.35 154064[120:MRR:539.0,154063.0] || -> until2p7(s45)* node4(s44). % 76.16/76.35 154065[121:Spt:154064.0] || -> until2p7(s45)*. % 76.16/76.35 154066[121:MRR:544.0,154065.0] || -> until2p7(s46)* node4(s45). % 76.16/76.35 154067[122:Spt:154066.0] || -> until2p7(s46)*. % 76.16/76.35 154068[122:MRR:549.0,154067.0] || -> until2p7(s47)* node4(s46). % 76.16/76.35 154069[123:Spt:154068.0] || -> until2p7(s47)*. % 76.16/76.35 154070[123:MRR:554.0,154069.0] || -> until2p7(s48)* node4(s47). % 76.16/76.35 154071[124:Spt:154070.0] || -> until2p7(s48)*. % 76.16/76.35 154072[124:MRR:559.0,154071.0] || -> until2p7(s49)* node4(s48). % 76.16/76.35 154073[125:Spt:154072.0] || -> until2p7(s49)*. % 76.16/76.35 154074[125:MRR:194.0,154073.0] || -> node4(s49)*. % 76.16/76.35 154075[125:MRR:153999.0,154074.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.35 154076[125:Res:53.1,154075.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.35 154078[125:MRR:154076.0,78381.0] || -> . % 76.16/76.35 154079[125:Spt:154078.0,154072.0,154073.0] || until2p7(s49)*+ -> . % 76.16/76.35 154080[125:Spt:154078.0,154072.1] || -> node4(s48)*. % 76.16/76.35 154081[125:MRR:78384.0,154080.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.35 154084[125:Res:53.1,154081.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 154087[125:Res:154084.0,61.1] always3(s48) || -> . % 76.16/76.35 154088[125:SSi:154087.0,78281.0,78387.0,137770.0,154071.0,154080.0] || -> . % 76.16/76.35 154089[124:Spt:154088.0,154070.0,154071.0] || until2p7(s48)*+ -> . % 76.16/76.35 154090[124:Spt:154088.0,154070.1] || -> node4(s47)*. % 76.16/76.35 154092[124:MRR:777.0,154090.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.35 154107[124:Res:53.1,154092.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.35 154109[125:Spt:154107.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 154111[125:Res:154109.0,61.1] always3(s47) || -> . % 76.16/76.35 154112[125:SSi:154111.0,78277.0,78280.0,137769.0,154069.0,154090.0] || -> . % 76.16/76.35 154113[125:Spt:154112.0,154107.0,154109.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.35 154114[125:Spt:154112.0,154107.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 154118[125:Res:154114.0,61.1] always3(s48) || -> . % 76.16/76.35 154119[125:SSi:154118.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.35 154120[123:Spt:154119.0,154068.0,154069.0] || until2p7(s47)*+ -> . % 76.16/76.35 154121[123:Spt:154119.0,154068.1] || -> node4(s46)*. % 76.16/76.35 154123[123:MRR:780.0,154121.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.35 154133[123:Res:53.1,154123.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.35 154135[124:Spt:154133.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 154137[124:Res:154135.0,61.1] always3(s46) || -> . % 76.16/76.35 154138[124:SSi:154137.0,78272.0,78276.0,137768.0,154067.0,154121.0] || -> . % 76.16/76.35 154139[124:Spt:154138.0,154133.0,154135.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.35 154140[124:Spt:154138.0,154133.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 154144[124:Res:154140.0,61.1] always3(s47) || -> . % 76.16/76.35 154145[124:SSi:154144.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.35 154146[122:Spt:154145.0,154066.0,154067.0] || until2p7(s46)*+ -> . % 76.16/76.35 154147[122:Spt:154145.0,154066.1] || -> node4(s45)*. % 76.16/76.35 154149[122:MRR:783.0,154147.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.35 154152[122:Res:53.1,154149.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.35 154154[123:Spt:154152.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 154156[123:Res:154154.0,61.1] always3(s45) || -> . % 76.16/76.35 154157[123:SSi:154156.0,78268.0,78271.0,137767.0,154065.0,154147.0] || -> . % 76.16/76.35 154158[123:Spt:154157.0,154152.0,154154.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.35 154159[123:Spt:154157.0,154152.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 154163[123:Res:154159.0,61.1] always3(s46) || -> . % 76.16/76.35 154164[123:SSi:154163.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.35 154165[121:Spt:154164.0,154064.0,154065.0] || until2p7(s45)*+ -> . % 76.16/76.35 154166[121:Spt:154164.0,154064.1] || -> node4(s44)*. % 76.16/76.35 154168[121:MRR:786.0,154166.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.35 154171[121:Res:53.1,154168.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.35 154173[122:Spt:154171.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 154175[122:Res:154173.0,61.1] always3(s44) || -> . % 76.16/76.35 154176[122:SSi:154175.0,78263.0,78267.0,137766.0,154063.0,154166.0] || -> . % 76.16/76.35 154177[122:Spt:154176.0,154171.0,154173.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.35 154178[122:Spt:154176.0,154171.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 154182[122:Res:154178.0,61.1] always3(s45) || -> . % 76.16/76.35 154183[122:SSi:154182.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.35 154184[120:Spt:154183.0,154062.0,154063.0] || until2p7(s44)*+ -> . % 76.16/76.35 154185[120:Spt:154183.0,154062.1] || -> node4(s43)*. % 76.16/76.35 154187[120:MRR:789.0,154185.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.35 154190[120:Res:53.1,154187.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.35 154195[121:Spt:154190.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 154197[121:Res:154195.0,61.1] always3(s43) || -> . % 76.16/76.35 154198[121:SSi:154197.0,78259.0,78262.0,137765.0,154061.0,154185.0] || -> . % 76.16/76.35 154199[121:Spt:154198.0,154190.0,154195.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.35 154200[121:Spt:154198.0,154190.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 154204[121:Res:154200.0,61.1] always3(s44) || -> . % 76.16/76.35 154205[121:SSi:154204.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.35 154206[119:Spt:154205.0,154060.0,154061.0] || until2p7(s43)*+ -> . % 76.16/76.35 154207[119:Spt:154205.0,154060.1] || -> node4(s42)*. % 76.16/76.35 154209[119:MRR:792.0,154207.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.35 154212[119:Res:53.1,154209.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.35 154214[120:Spt:154212.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 154216[120:Res:154214.0,61.1] always3(s42) || -> . % 76.16/76.35 154217[120:SSi:154216.0,78254.0,78258.0,137764.0,154059.0,154207.0] || -> . % 76.16/76.35 154218[120:Spt:154217.0,154212.0,154214.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.35 154219[120:Spt:154217.0,154212.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 154223[120:Res:154219.0,61.1] always3(s43) || -> . % 76.16/76.35 154224[120:SSi:154223.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.35 154225[118:Spt:154224.0,154058.0,154059.0] || until2p7(s42)*+ -> . % 76.16/76.35 154226[118:Spt:154224.0,154058.1] || -> node4(s41)*. % 76.16/76.35 154228[118:MRR:795.0,154226.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.35 154231[118:Res:53.1,154228.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.35 154233[119:Spt:154231.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 154235[119:Res:154233.0,61.1] always3(s41) || -> . % 76.16/76.35 154236[119:SSi:154235.0,78250.0,78253.0,137763.0,154057.0,154226.0] || -> . % 76.16/76.35 154237[119:Spt:154236.0,154231.0,154233.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.35 154238[119:Spt:154236.0,154231.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 154242[119:Res:154238.0,61.1] always3(s42) || -> . % 76.16/76.35 154243[119:SSi:154242.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.35 154244[117:Spt:154243.0,154056.0,154057.0] || until2p7(s41)*+ -> . % 76.16/76.35 154245[117:Spt:154243.0,154056.1] || -> node4(s40)*. % 76.16/76.35 154247[117:MRR:798.0,154245.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.35 154250[117:Res:53.1,154247.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.35 154252[118:Spt:154250.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 154254[118:Res:154252.0,61.1] always3(s40) || -> . % 76.16/76.35 154255[118:SSi:154254.0,78245.0,78249.0,137762.0,154055.0,154245.0] || -> . % 76.16/76.35 154256[118:Spt:154255.0,154250.0,154252.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.35 154257[118:Spt:154255.0,154250.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 154261[118:Res:154257.0,61.1] always3(s41) || -> . % 76.16/76.35 154262[118:SSi:154261.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.35 154263[116:Spt:154262.0,154054.0,154055.0] || until2p7(s40)*+ -> . % 76.16/76.35 154264[116:Spt:154262.0,154054.1] || -> node4(s39)*. % 76.16/76.35 154266[116:MRR:801.0,154264.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.35 154269[116:Res:53.1,154266.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.35 154274[117:Spt:154269.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 154276[117:Res:154274.0,61.1] always3(s39) || -> . % 76.16/76.35 154277[117:SSi:154276.0,78241.0,78244.0,137761.0,154053.0,154264.0] || -> . % 76.16/76.35 154278[117:Spt:154277.0,154269.0,154274.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.35 154279[117:Spt:154277.0,154269.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 154283[117:Res:154279.0,61.1] always3(s40) || -> . % 76.16/76.35 154284[117:SSi:154283.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.35 154285[115:Spt:154284.0,154052.0,154053.0] || until2p7(s39)*+ -> . % 76.16/76.35 154286[115:Spt:154284.0,154052.1] || -> node4(s38)*. % 76.16/76.35 154288[115:MRR:804.0,154286.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.35 154291[115:Res:53.1,154288.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.35 154293[116:Spt:154291.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 154295[116:Res:154293.0,61.1] always3(s38) || -> . % 76.16/76.35 154296[116:SSi:154295.0,78236.0,78240.0,137760.0,154051.0,154286.0] || -> . % 76.16/76.35 154297[116:Spt:154296.0,154291.0,154293.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.35 154298[116:Spt:154296.0,154291.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 154302[116:Res:154298.0,61.1] always3(s39) || -> . % 76.16/76.35 154303[116:SSi:154302.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.35 154304[114:Spt:154303.0,154050.0,154051.0] || until2p7(s38)*+ -> . % 76.16/76.35 154305[114:Spt:154303.0,154050.1] || -> node4(s37)*. % 76.16/76.35 154307[114:MRR:807.0,154305.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.35 154310[114:Res:53.1,154307.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.35 154312[115:Spt:154310.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 154314[115:Res:154312.0,61.1] always3(s37) || -> . % 76.16/76.35 154315[115:SSi:154314.0,78232.0,78235.0,137759.0,154049.0,154305.0] || -> . % 76.16/76.35 154316[115:Spt:154315.0,154310.0,154312.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.35 154317[115:Spt:154315.0,154310.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 154321[115:Res:154317.0,61.1] always3(s38) || -> . % 76.16/76.35 154322[115:SSi:154321.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.35 154323[113:Spt:154322.0,154048.0,154049.0] || until2p7(s37)*+ -> . % 76.16/76.35 154324[113:Spt:154322.0,154048.1] || -> node4(s36)*. % 76.16/76.35 154326[113:MRR:810.0,154324.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.35 154329[113:Res:53.1,154326.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.35 154331[114:Spt:154329.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 154333[114:Res:154331.0,61.1] always3(s36) || -> . % 76.16/76.35 154334[114:SSi:154333.0,78227.0,78231.0,137758.0,154047.0,154324.0] || -> . % 76.16/76.35 154335[114:Spt:154334.0,154329.0,154331.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.35 154336[114:Spt:154334.0,154329.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 154340[114:Res:154336.0,61.1] always3(s37) || -> . % 76.16/76.35 154341[114:SSi:154340.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.35 154342[112:Spt:154341.0,154046.0,154047.0] || until2p7(s36)*+ -> . % 76.16/76.35 154343[112:Spt:154341.0,154046.1] || -> node4(s35)*. % 76.16/76.35 154345[112:MRR:813.0,154343.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.35 154348[112:Res:53.1,154345.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.35 154353[113:Spt:154348.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 154355[113:Res:154353.0,61.1] always3(s35) || -> . % 76.16/76.35 154356[113:SSi:154355.0,78223.0,78226.0,137757.0,154045.0,154343.0] || -> . % 76.16/76.35 154357[113:Spt:154356.0,154348.0,154353.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.35 154358[113:Spt:154356.0,154348.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 154362[113:Res:154358.0,61.1] always3(s36) || -> . % 76.16/76.35 154363[113:SSi:154362.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.35 154364[111:Spt:154363.0,154044.0,154045.0] || until2p7(s35)*+ -> . % 76.16/76.35 154365[111:Spt:154363.0,154044.1] || -> node4(s34)*. % 76.16/76.35 154367[111:MRR:816.0,154365.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.35 154370[111:Res:53.1,154367.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.35 154372[112:Spt:154370.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 154374[112:Res:154372.0,61.1] always3(s34) || -> . % 76.16/76.35 154375[112:SSi:154374.0,78218.0,78222.0,137756.0,154043.0,154365.0] || -> . % 76.16/76.35 154376[112:Spt:154375.0,154370.0,154372.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.35 154377[112:Spt:154375.0,154370.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 154381[112:Res:154377.0,61.1] always3(s35) || -> . % 76.16/76.35 154382[112:SSi:154381.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.35 154383[110:Spt:154382.0,154042.0,154043.0] || until2p7(s34)*+ -> . % 76.16/76.35 154384[110:Spt:154382.0,154042.1] || -> node4(s33)*. % 76.16/76.35 154386[110:MRR:819.0,154384.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.35 154389[110:Res:53.1,154386.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.35 154391[111:Spt:154389.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 154393[111:Res:154391.0,61.1] always3(s33) || -> . % 76.16/76.35 154394[111:SSi:154393.0,78214.0,78217.0,137755.0,154041.0,154384.0] || -> . % 76.16/76.35 154395[111:Spt:154394.0,154389.0,154391.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.35 154396[111:Spt:154394.0,154389.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 154400[111:Res:154396.0,61.1] always3(s34) || -> . % 76.16/76.35 154401[111:SSi:154400.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.35 154402[109:Spt:154401.0,154040.0,154041.0] || until2p7(s33)*+ -> . % 76.16/76.35 154403[109:Spt:154401.0,154040.1] || -> node4(s32)*. % 76.16/76.35 154405[109:MRR:822.0,154403.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.35 154408[109:Res:53.1,154405.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.35 154410[110:Spt:154408.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 154412[110:Res:154410.0,61.1] always3(s32) || -> . % 76.16/76.35 154413[110:SSi:154412.0,78209.0,78213.0,137754.0,154039.0,154403.0] || -> . % 76.16/76.35 154414[110:Spt:154413.0,154408.0,154410.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.35 154415[110:Spt:154413.0,154408.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 154419[110:Res:154415.0,61.1] always3(s33) || -> . % 76.16/76.35 154420[110:SSi:154419.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.35 154421[108:Spt:154420.0,154038.0,154039.0] || until2p7(s32)*+ -> . % 76.16/76.35 154422[108:Spt:154420.0,154038.1] || -> node4(s31)*. % 76.16/76.35 154424[108:MRR:825.0,154422.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.35 154427[108:Res:53.1,154424.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.35 154432[109:Spt:154427.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 154434[109:Res:154432.0,61.1] always3(s31) || -> . % 76.16/76.35 154435[109:SSi:154434.0,78205.0,78208.0,137753.0,154037.0,154422.0] || -> . % 76.16/76.35 154436[109:Spt:154435.0,154427.0,154432.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.35 154437[109:Spt:154435.0,154427.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 154441[109:Res:154437.0,61.1] always3(s32) || -> . % 76.16/76.35 154442[109:SSi:154441.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.35 154443[107:Spt:154442.0,154036.0,154037.0] || until2p7(s31)*+ -> . % 76.16/76.35 154444[107:Spt:154442.0,154036.1] || -> node4(s30)*. % 76.16/76.35 154446[107:MRR:828.0,154444.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.35 154449[107:Res:53.1,154446.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.35 154451[108:Spt:154449.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 154453[108:Res:154451.0,61.1] always3(s30) || -> . % 76.16/76.35 154454[108:SSi:154453.0,78200.0,78204.0,137752.0,154035.0,154444.0] || -> . % 76.16/76.35 154455[108:Spt:154454.0,154449.0,154451.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.35 154456[108:Spt:154454.0,154449.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 154460[108:Res:154456.0,61.1] always3(s31) || -> . % 76.16/76.35 154461[108:SSi:154460.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.35 154462[106:Spt:154461.0,154034.0,154035.0] || until2p7(s30)*+ -> . % 76.16/76.35 154463[106:Spt:154461.0,154034.1] || -> node4(s29)*. % 76.16/76.35 154465[106:MRR:831.0,154463.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.35 154468[106:Res:53.1,154465.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.35 154470[107:Spt:154468.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 154472[107:Res:154470.0,61.1] always3(s29) || -> . % 76.16/76.35 154473[107:SSi:154472.0,78196.0,78199.0,137751.0,154033.0,154463.0] || -> . % 76.16/76.35 154474[107:Spt:154473.0,154468.0,154470.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.35 154475[107:Spt:154473.0,154468.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 154479[107:Res:154475.0,61.1] always3(s30) || -> . % 76.16/76.35 154480[107:SSi:154479.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.35 154481[105:Spt:154480.0,154032.0,154033.0] || until2p7(s29)*+ -> . % 76.16/76.35 154482[105:Spt:154480.0,154032.1] || -> node4(s28)*. % 76.16/76.35 154484[105:MRR:834.0,154482.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.35 154487[105:Res:53.1,154484.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.35 154489[106:Spt:154487.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 154491[106:Res:154489.0,61.1] always3(s28) || -> . % 76.16/76.35 154492[106:SSi:154491.0,78191.0,78195.0,137750.0,154031.0,154482.0] || -> . % 76.16/76.35 154493[106:Spt:154492.0,154487.0,154489.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.35 154494[106:Spt:154492.0,154487.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 154498[106:Res:154494.0,61.1] always3(s29) || -> . % 76.16/76.35 154499[106:SSi:154498.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.35 154500[104:Spt:154499.0,154030.0,154031.0] || until2p7(s28)*+ -> . % 76.16/76.35 154501[104:Spt:154499.0,154030.1] || -> node4(s27)*. % 76.16/76.35 154503[104:MRR:837.0,154501.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.35 154506[104:Res:53.1,154503.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.35 154511[105:Spt:154506.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 154513[105:Res:154511.0,61.1] always3(s27) || -> . % 76.16/76.35 154514[105:SSi:154513.0,78187.0,78190.0,137749.0,154029.0,154501.0] || -> . % 76.16/76.35 154515[105:Spt:154514.0,154506.0,154511.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.35 154516[105:Spt:154514.0,154506.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 154520[105:Res:154516.0,61.1] always3(s28) || -> . % 76.16/76.35 154521[105:SSi:154520.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.35 154522[103:Spt:154521.0,154028.0,154029.0] || until2p7(s27)*+ -> . % 76.16/76.35 154523[103:Spt:154521.0,154028.1] || -> node4(s26)*. % 76.16/76.35 154525[103:MRR:840.0,154523.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.35 154528[103:Res:53.1,154525.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.35 154530[104:Spt:154528.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 154532[104:Res:154530.0,61.1] always3(s26) || -> . % 76.16/76.35 154533[104:SSi:154532.0,78182.0,78186.0,137748.0,154027.0,154523.0] || -> . % 76.16/76.35 154534[104:Spt:154533.0,154528.0,154530.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.35 154535[104:Spt:154533.0,154528.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 154539[104:Res:154535.0,61.1] always3(s27) || -> . % 76.16/76.35 154540[104:SSi:154539.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.35 154541[102:Spt:154540.0,154026.0,154027.0] || until2p7(s26)*+ -> . % 76.16/76.35 154542[102:Spt:154540.0,154026.1] || -> node4(s25)*. % 76.16/76.35 154544[102:MRR:843.0,154542.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.35 154547[102:Res:53.1,154544.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.35 154549[103:Spt:154547.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 154551[103:Res:154549.0,61.1] always3(s25) || -> . % 76.16/76.35 154552[103:SSi:154551.0,78178.0,78181.0,137747.0,154025.0,154542.0] || -> . % 76.16/76.35 154553[103:Spt:154552.0,154547.0,154549.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.35 154554[103:Spt:154552.0,154547.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 154558[103:Res:154554.0,61.1] always3(s26) || -> . % 76.16/76.35 154559[103:SSi:154558.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.35 154560[101:Spt:154559.0,154024.0,154025.0] || until2p7(s25)*+ -> . % 76.16/76.35 154561[101:Spt:154559.0,154024.1] || -> node4(s24)*. % 76.16/76.35 154563[101:MRR:846.0,154561.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.35 154566[101:Res:53.1,154563.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.35 154568[102:Spt:154566.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 154570[102:Res:154568.0,61.1] always3(s24) || -> . % 76.16/76.35 154571[102:SSi:154570.0,78173.0,78177.0,137746.0,154023.0,154561.0] || -> . % 76.16/76.35 154572[102:Spt:154571.0,154566.0,154568.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.35 154573[102:Spt:154571.0,154566.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 154577[102:Res:154573.0,61.1] always3(s25) || -> . % 76.16/76.35 154578[102:SSi:154577.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.35 154579[100:Spt:154578.0,154022.0,154023.0] || until2p7(s24)*+ -> . % 76.16/76.35 154580[100:Spt:154578.0,154022.1] || -> node4(s23)*. % 76.16/76.35 154582[100:MRR:849.0,154580.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.35 154585[100:Res:53.1,154582.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.35 154590[101:Spt:154585.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 154592[101:Res:154590.0,61.1] always3(s23) || -> . % 76.16/76.35 154593[101:SSi:154592.0,78169.0,78172.0,137745.0,154021.0,154580.0] || -> . % 76.16/76.35 154594[101:Spt:154593.0,154585.0,154590.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.35 154595[101:Spt:154593.0,154585.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 154599[101:Res:154595.0,61.1] always3(s24) || -> . % 76.16/76.35 154600[101:SSi:154599.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.35 154601[99:Spt:154600.0,154020.0,154021.0] || until2p7(s23)*+ -> . % 76.16/76.35 154602[99:Spt:154600.0,154020.1] || -> node4(s22)*. % 76.16/76.35 154604[99:MRR:852.0,154602.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.35 154607[99:Res:53.1,154604.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.35 154609[100:Spt:154607.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 154611[100:Res:154609.0,61.1] always3(s22) || -> . % 76.16/76.35 154612[100:SSi:154611.0,78164.0,78168.0,137744.0,154019.0,154602.0] || -> . % 76.16/76.35 154613[100:Spt:154612.0,154607.0,154609.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.35 154614[100:Spt:154612.0,154607.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 154618[100:Res:154614.0,61.1] always3(s23) || -> . % 76.16/76.35 154619[100:SSi:154618.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.35 154620[98:Spt:154619.0,154018.0,154019.0] || until2p7(s22)*+ -> . % 76.16/76.35 154621[98:Spt:154619.0,154018.1] || -> node4(s21)*. % 76.16/76.35 154623[98:MRR:855.0,154621.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.35 154626[98:Res:53.1,154623.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.35 154628[99:Spt:154626.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 154630[99:Res:154628.0,61.1] always3(s21) || -> . % 76.16/76.35 154631[99:SSi:154630.0,78160.0,78163.0,137743.0,154017.0,154621.0] || -> . % 76.16/76.35 154632[99:Spt:154631.0,154626.0,154628.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.35 154633[99:Spt:154631.0,154626.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 154637[99:Res:154633.0,61.1] always3(s22) || -> . % 76.16/76.35 154638[99:SSi:154637.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.35 154639[97:Spt:154638.0,154016.0,154017.0] || until2p7(s21)*+ -> . % 76.16/76.35 154640[97:Spt:154638.0,154016.1] || -> node4(s20)*. % 76.16/76.35 154642[97:MRR:858.0,154640.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.35 154645[97:Res:53.1,154642.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.35 154647[98:Spt:154645.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 154649[98:Res:154647.0,61.1] always3(s20) || -> . % 76.16/76.35 154650[98:SSi:154649.0,78155.0,78159.0,137742.0,154015.0,154640.0] || -> . % 76.16/76.35 154651[98:Spt:154650.0,154645.0,154647.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.35 154652[98:Spt:154650.0,154645.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 154656[98:Res:154652.0,61.1] always3(s21) || -> . % 76.16/76.35 154657[98:SSi:154656.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.35 154658[96:Spt:154657.0,154014.0,154015.0] || until2p7(s20)*+ -> . % 76.16/76.35 154659[96:Spt:154657.0,154014.1] || -> node4(s19)*. % 76.16/76.35 154661[96:MRR:861.0,154659.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.35 154664[96:Res:53.1,154661.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.35 154669[97:Spt:154664.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 154671[97:Res:154669.0,61.1] always3(s19) || -> . % 76.16/76.35 154672[97:SSi:154671.0,78151.0,78154.0,137741.0,154013.0,154659.0] || -> . % 76.16/76.35 154673[97:Spt:154672.0,154664.0,154669.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.35 154674[97:Spt:154672.0,154664.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 154678[97:Res:154674.0,61.1] always3(s20) || -> . % 76.16/76.35 154679[97:SSi:154678.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.35 154680[95:Spt:154679.0,154012.0,154013.0] || until2p7(s19)*+ -> . % 76.16/76.35 154681[95:Spt:154679.0,154012.1] || -> node4(s18)*. % 76.16/76.35 154683[95:MRR:864.0,154681.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.35 154686[95:Res:53.1,154683.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.35 154688[96:Spt:154686.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 154690[96:Res:154688.0,61.1] always3(s18) || -> . % 76.16/76.35 154691[96:SSi:154690.0,78146.0,78150.0,137740.0,154011.0,154681.0] || -> . % 76.16/76.35 154692[96:Spt:154691.0,154686.0,154688.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.35 154693[96:Spt:154691.0,154686.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 154697[96:Res:154693.0,61.1] always3(s19) || -> . % 76.16/76.35 154698[96:SSi:154697.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.35 154699[94:Spt:154698.0,154010.0,154011.0] || until2p7(s18)*+ -> . % 76.16/76.35 154700[94:Spt:154698.0,154010.1] || -> node4(s17)*. % 76.16/76.35 154702[94:MRR:867.0,154700.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.35 154705[94:Res:53.1,154702.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.35 154707[95:Spt:154705.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 154709[95:Res:154707.0,61.1] always3(s17) || -> . % 76.16/76.35 154710[95:SSi:154709.0,78142.0,78145.0,137739.0,154009.0,154700.0] || -> . % 76.16/76.35 154711[95:Spt:154710.0,154705.0,154707.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.35 154712[95:Spt:154710.0,154705.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 154716[95:Res:154712.0,61.1] always3(s18) || -> . % 76.16/76.35 154717[95:SSi:154716.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.35 154718[93:Spt:154717.0,154008.0,154009.0] || until2p7(s17)*+ -> . % 76.16/76.35 154719[93:Spt:154717.0,154008.1] || -> node4(s16)*. % 76.16/76.35 154721[93:MRR:870.0,154719.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.35 154724[93:Res:53.1,154721.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.35 154726[94:Spt:154724.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 154728[94:Res:154726.0,61.1] always3(s16) || -> . % 76.16/76.35 154729[94:SSi:154728.0,78137.0,78141.0,137738.0,154007.0,154719.0] || -> . % 76.16/76.35 154730[94:Spt:154729.0,154724.0,154726.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.35 154731[94:Spt:154729.0,154724.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 154735[94:Res:154731.0,61.1] always3(s17) || -> . % 76.16/76.35 154736[94:SSi:154735.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.35 154737[92:Spt:154736.0,154006.0,154007.0] || until2p7(s16)*+ -> . % 76.16/76.35 154738[92:Spt:154736.0,154006.1] || -> node4(s15)*. % 76.16/76.35 154740[92:MRR:873.0,154738.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.35 154743[92:Res:53.1,154740.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.35 154748[93:Spt:154743.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 154750[93:Res:154748.0,61.1] always3(s15) || -> . % 76.16/76.35 154751[93:SSi:154750.0,78133.0,78136.0,137737.0,154005.0,154738.0] || -> . % 76.16/76.35 154752[93:Spt:154751.0,154743.0,154748.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.35 154753[93:Spt:154751.0,154743.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 154757[93:Res:154753.0,61.1] always3(s16) || -> . % 76.16/76.35 154758[93:SSi:154757.0,78137.0,78141.0,137738.0] || -> . % 76.16/76.35 154759[91:Spt:154758.0,154004.0,154005.0] || until2p7(s15)*+ -> . % 76.16/76.35 154760[91:Spt:154758.0,154004.1] || -> node4(s14)*. % 76.16/76.35 154762[91:MRR:876.0,154760.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.35 154765[91:Res:53.1,154762.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.35 154767[91:MRR:154765.0,153994.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 154769[91:Res:154767.0,61.1] always3(s15) || -> . % 76.16/76.35 154770[91:SSi:154769.0,78133.0,78136.0,137737.0] || -> . % 76.16/76.35 154771[89:Spt:154770.0,153862.0,153865.0] || trans(s49,s14)*+ -> . % 76.16/76.35 154772[89:Spt:154770.0,153862.1,153862.2,153862.3,153862.4,153862.5,153862.6,153862.7,153862.8,153862.9,153862.10] || -> trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.35 154774[89:MRR:153864.1,154771.0] xuntil6(s49) || -> trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.35 154775[90:Spt:154772.0] || -> trans(s49,s13)*. % 76.16/76.35 154776[90:Res:154775.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s13)*. % 76.16/76.35 154778[90:Res:154775.0,60.0] || -> node2(s49,s13)*. % 76.16/76.35 154779[90:SSi:154776.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s13)*. % 76.16/76.35 154780[90:Res:154778.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)*. % 76.16/76.35 154900[90:SoR:154780.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)*. % 76.16/76.35 154902[90:SoR:154900.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)* xuntil6(s49). % 76.16/76.35 154903[90:SSi:154902.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s13,c_busy)* xuntil6(s49). % 76.16/76.35 154904[91:Spt:154903.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.35 154906[91:Res:154904.0,61.1] always3(s13) || -> . % 76.16/76.35 154907[91:SSi:154906.0,78124.0,78127.0,137735.0] || -> . % 76.16/76.35 154908[91:Spt:154907.0,154903.1,154904.0] || m_main_v_state(s13,c_busy)*+ -> . % 76.16/76.35 154909[91:Spt:154907.0,154903.0,154903.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.35 154913[91:MRR:154900.2,154908.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.35 154914[91:Res:53.1,154909.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.35 154916[91:MRR:154914.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.35 154917[91:MRR:154779.0,154916.0] || -> until2p7(s13)*. % 76.16/76.35 154918[91:MRR:209.0,154917.0] || -> until2p7(s14)* node4(s13). % 76.16/76.35 154919[92:Spt:154918.0] || -> until2p7(s14)*. % 76.16/76.35 154920[92:MRR:210.0,154919.0] || -> until2p7(s15)* node4(s14). % 76.16/76.35 154921[93:Spt:154920.0] || -> until2p7(s15)*. % 76.16/76.35 154922[93:MRR:211.0,154921.0] || -> until2p7(s16)* node4(s15). % 76.16/76.35 154923[94:Spt:154922.0] || -> until2p7(s16)*. % 76.16/76.35 154924[94:MRR:212.0,154923.0] || -> until2p7(s17)* node4(s16). % 76.16/76.35 154925[95:Spt:154924.0] || -> until2p7(s17)*. % 76.16/76.35 154926[95:MRR:213.0,154925.0] || -> until2p7(s18)* node4(s17). % 76.16/76.35 154927[96:Spt:154926.0] || -> until2p7(s18)*. % 76.16/76.35 154928[96:MRR:214.0,154927.0] || -> until2p7(s19)* node4(s18). % 76.16/76.35 154929[97:Spt:154928.0] || -> until2p7(s19)*. % 76.16/76.35 154930[97:MRR:215.0,154929.0] || -> until2p7(s20)* node4(s19). % 76.16/76.35 154931[98:Spt:154930.0] || -> until2p7(s20)*. % 76.16/76.35 154932[98:MRR:216.0,154931.0] || -> until2p7(s21)* node4(s20). % 76.16/76.35 154933[99:Spt:154932.0] || -> until2p7(s21)*. % 76.16/76.35 154934[99:MRR:217.0,154933.0] || -> until2p7(s22)* node4(s21). % 76.16/76.35 154935[100:Spt:154934.0] || -> until2p7(s22)*. % 76.16/76.35 154936[100:MRR:218.0,154935.0] || -> until2p7(s23)* node4(s22). % 76.16/76.35 154937[101:Spt:154936.0] || -> until2p7(s23)*. % 76.16/76.35 154938[101:MRR:219.0,154937.0] || -> until2p7(s24)* node4(s23). % 76.16/76.35 154939[102:Spt:154938.0] || -> until2p7(s24)*. % 76.16/76.35 154940[102:MRR:220.0,154939.0] || -> until2p7(s25)* node4(s24). % 76.16/76.35 154941[103:Spt:154940.0] || -> until2p7(s25)*. % 76.16/76.35 154942[103:MRR:221.0,154941.0] || -> until2p7(s26)* node4(s25). % 76.16/76.35 154943[104:Spt:154942.0] || -> until2p7(s26)*. % 76.16/76.35 154944[104:MRR:222.0,154943.0] || -> until2p7(s27)* node4(s26). % 76.16/76.35 154945[105:Spt:154944.0] || -> until2p7(s27)*. % 76.16/76.35 154946[105:MRR:223.0,154945.0] || -> until2p7(s28)* node4(s27). % 76.16/76.35 154947[106:Spt:154946.0] || -> until2p7(s28)*. % 76.16/76.35 154948[106:MRR:224.0,154947.0] || -> until2p7(s29)* node4(s28). % 76.16/76.35 154949[107:Spt:154948.0] || -> until2p7(s29)*. % 76.16/76.35 154950[107:MRR:225.0,154949.0] || -> until2p7(s30)* node4(s29). % 76.16/76.35 154951[108:Spt:154950.0] || -> until2p7(s30)*. % 76.16/76.35 154952[108:MRR:226.0,154951.0] || -> until2p7(s31)* node4(s30). % 76.16/76.35 154953[109:Spt:154952.0] || -> until2p7(s31)*. % 76.16/76.35 154954[109:MRR:227.0,154953.0] || -> until2p7(s32)* node4(s31). % 76.16/76.35 154955[110:Spt:154954.0] || -> until2p7(s32)*. % 76.16/76.35 154956[110:MRR:228.0,154955.0] || -> until2p7(s33)* node4(s32). % 76.16/76.35 154957[111:Spt:154956.0] || -> until2p7(s33)*. % 76.16/76.35 154958[111:MRR:229.0,154957.0] || -> until2p7(s34)* node4(s33). % 76.16/76.35 154959[112:Spt:154958.0] || -> until2p7(s34)*. % 76.16/76.35 154960[112:MRR:230.0,154959.0] || -> until2p7(s35)* node4(s34). % 76.16/76.35 154961[113:Spt:154960.0] || -> until2p7(s35)*. % 76.16/76.35 154962[113:MRR:231.0,154961.0] || -> until2p7(s36)* node4(s35). % 76.16/76.35 154963[114:Spt:154962.0] || -> until2p7(s36)*. % 76.16/76.35 154964[114:MRR:232.0,154963.0] || -> until2p7(s37)* node4(s36). % 76.16/76.35 154965[115:Spt:154964.0] || -> until2p7(s37)*. % 76.16/76.35 154966[115:MRR:235.0,154965.0] || -> until2p7(s38)* node4(s37). % 76.16/76.35 154967[116:Spt:154966.0] || -> until2p7(s38)*. % 76.16/76.35 154968[116:MRR:236.0,154967.0] || -> until2p7(s39)* node4(s38). % 76.16/76.35 154969[117:Spt:154968.0] || -> until2p7(s39)*. % 76.16/76.35 154970[117:MRR:237.0,154969.0] || -> until2p7(s40)* node4(s39). % 76.16/76.35 154971[118:Spt:154970.0] || -> until2p7(s40)*. % 76.16/76.35 154972[118:MRR:238.0,154971.0] || -> until2p7(s41)* node4(s40). % 76.16/76.35 154973[119:Spt:154972.0] || -> until2p7(s41)*. % 76.16/76.35 154974[119:MRR:239.0,154973.0] || -> until2p7(s42)* node4(s41). % 76.16/76.35 154975[120:Spt:154974.0] || -> until2p7(s42)*. % 76.16/76.35 154976[120:MRR:240.0,154975.0] || -> until2p7(s43)* node4(s42). % 76.16/76.35 154977[121:Spt:154976.0] || -> until2p7(s43)*. % 76.16/76.35 154978[121:MRR:241.0,154977.0] || -> until2p7(s44)* node4(s43). % 76.16/76.35 154979[122:Spt:154978.0] || -> until2p7(s44)*. % 76.16/76.35 154980[122:MRR:539.0,154979.0] || -> until2p7(s45)* node4(s44). % 76.16/76.35 154981[123:Spt:154980.0] || -> until2p7(s45)*. % 76.16/76.35 154982[123:MRR:544.0,154981.0] || -> until2p7(s46)* node4(s45). % 76.16/76.35 154983[124:Spt:154982.0] || -> until2p7(s46)*. % 76.16/76.35 154984[124:MRR:549.0,154983.0] || -> until2p7(s47)* node4(s46). % 76.16/76.35 154985[125:Spt:154984.0] || -> until2p7(s47)*. % 76.16/76.35 154986[125:MRR:554.0,154985.0] || -> until2p7(s48)* node4(s47). % 76.16/76.35 154987[126:Spt:154986.0] || -> until2p7(s48)*. % 76.16/76.35 154988[126:MRR:559.0,154987.0] || -> until2p7(s49)* node4(s48). % 76.16/76.35 154989[127:Spt:154988.0] || -> until2p7(s49)*. % 76.16/76.35 154990[127:MRR:194.0,154989.0] || -> node4(s49)*. % 76.16/76.35 154991[127:MRR:154913.0,154990.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.35 154995[127:Res:53.1,154991.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.35 154997[127:MRR:154995.0,78381.0] || -> . % 76.16/76.35 154998[127:Spt:154997.0,154988.0,154989.0] || until2p7(s49)*+ -> . % 76.16/76.35 154999[127:Spt:154997.0,154988.1] || -> node4(s48)*. % 76.16/76.35 155000[127:MRR:78384.0,154999.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.35 155003[127:Res:53.1,155000.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 155006[127:Res:155003.0,61.1] always3(s48) || -> . % 76.16/76.35 155007[127:SSi:155006.0,78281.0,78387.0,137770.0,154987.0,154999.0] || -> . % 76.16/76.35 155008[126:Spt:155007.0,154986.0,154987.0] || until2p7(s48)*+ -> . % 76.16/76.35 155009[126:Spt:155007.0,154986.1] || -> node4(s47)*. % 76.16/76.35 155011[126:MRR:777.0,155009.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.35 155023[126:Res:53.1,155011.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.35 155025[127:Spt:155023.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 155027[127:Res:155025.0,61.1] always3(s47) || -> . % 76.16/76.35 155028[127:SSi:155027.0,78277.0,78280.0,137769.0,154985.0,155009.0] || -> . % 76.16/76.35 155029[127:Spt:155028.0,155023.0,155025.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.35 155030[127:Spt:155028.0,155023.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 155034[127:Res:155030.0,61.1] always3(s48) || -> . % 76.16/76.35 155035[127:SSi:155034.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.35 155036[125:Spt:155035.0,154984.0,154985.0] || until2p7(s47)*+ -> . % 76.16/76.35 155037[125:Spt:155035.0,154984.1] || -> node4(s46)*. % 76.16/76.35 155039[125:MRR:780.0,155037.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.35 155046[125:Res:53.1,155039.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.35 155051[126:Spt:155046.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 155053[126:Res:155051.0,61.1] always3(s46) || -> . % 76.16/76.35 155054[126:SSi:155053.0,78272.0,78276.0,137768.0,154983.0,155037.0] || -> . % 76.16/76.35 155055[126:Spt:155054.0,155046.0,155051.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.35 155056[126:Spt:155054.0,155046.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 155060[126:Res:155056.0,61.1] always3(s47) || -> . % 76.16/76.35 155061[126:SSi:155060.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.35 155062[124:Spt:155061.0,154982.0,154983.0] || until2p7(s46)*+ -> . % 76.16/76.35 155063[124:Spt:155061.0,154982.1] || -> node4(s45)*. % 76.16/76.35 155065[124:MRR:783.0,155063.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.35 155068[124:Res:53.1,155065.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.35 155070[125:Spt:155068.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 155072[125:Res:155070.0,61.1] always3(s45) || -> . % 76.16/76.35 155073[125:SSi:155072.0,78268.0,78271.0,137767.0,154981.0,155063.0] || -> . % 76.16/76.35 155074[125:Spt:155073.0,155068.0,155070.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.35 155075[125:Spt:155073.0,155068.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 155079[125:Res:155075.0,61.1] always3(s46) || -> . % 76.16/76.35 155080[125:SSi:155079.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.35 155081[123:Spt:155080.0,154980.0,154981.0] || until2p7(s45)*+ -> . % 76.16/76.35 155082[123:Spt:155080.0,154980.1] || -> node4(s44)*. % 76.16/76.35 155084[123:MRR:786.0,155082.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.35 155087[123:Res:53.1,155084.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.35 155089[124:Spt:155087.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 155091[124:Res:155089.0,61.1] always3(s44) || -> . % 76.16/76.35 155092[124:SSi:155091.0,78263.0,78267.0,137766.0,154979.0,155082.0] || -> . % 76.16/76.35 155093[124:Spt:155092.0,155087.0,155089.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.35 155094[124:Spt:155092.0,155087.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 155098[124:Res:155094.0,61.1] always3(s45) || -> . % 76.16/76.35 155099[124:SSi:155098.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.35 155100[122:Spt:155099.0,154978.0,154979.0] || until2p7(s44)*+ -> . % 76.16/76.35 155101[122:Spt:155099.0,154978.1] || -> node4(s43)*. % 76.16/76.35 155103[122:MRR:789.0,155101.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.35 155106[122:Res:53.1,155103.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.35 155108[123:Spt:155106.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 155110[123:Res:155108.0,61.1] always3(s43) || -> . % 76.16/76.35 155111[123:SSi:155110.0,78259.0,78262.0,137765.0,154977.0,155101.0] || -> . % 76.16/76.35 155112[123:Spt:155111.0,155106.0,155108.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.35 155113[123:Spt:155111.0,155106.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 155117[123:Res:155113.0,61.1] always3(s44) || -> . % 76.16/76.35 155118[123:SSi:155117.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.35 155119[121:Spt:155118.0,154976.0,154977.0] || until2p7(s43)*+ -> . % 76.16/76.35 155120[121:Spt:155118.0,154976.1] || -> node4(s42)*. % 76.16/76.35 155122[121:MRR:792.0,155120.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.35 155125[121:Res:53.1,155122.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.35 155130[122:Spt:155125.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 155132[122:Res:155130.0,61.1] always3(s42) || -> . % 76.16/76.35 155133[122:SSi:155132.0,78254.0,78258.0,137764.0,154975.0,155120.0] || -> . % 76.16/76.35 155134[122:Spt:155133.0,155125.0,155130.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.35 155135[122:Spt:155133.0,155125.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 155139[122:Res:155135.0,61.1] always3(s43) || -> . % 76.16/76.35 155140[122:SSi:155139.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.35 155141[120:Spt:155140.0,154974.0,154975.0] || until2p7(s42)*+ -> . % 76.16/76.35 155142[120:Spt:155140.0,154974.1] || -> node4(s41)*. % 76.16/76.35 155144[120:MRR:795.0,155142.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.35 155147[120:Res:53.1,155144.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.35 155149[121:Spt:155147.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 155151[121:Res:155149.0,61.1] always3(s41) || -> . % 76.16/76.35 155152[121:SSi:155151.0,78250.0,78253.0,137763.0,154973.0,155142.0] || -> . % 76.16/76.35 155153[121:Spt:155152.0,155147.0,155149.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.35 155154[121:Spt:155152.0,155147.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 155158[121:Res:155154.0,61.1] always3(s42) || -> . % 76.16/76.35 155159[121:SSi:155158.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.35 155160[119:Spt:155159.0,154972.0,154973.0] || until2p7(s41)*+ -> . % 76.16/76.35 155161[119:Spt:155159.0,154972.1] || -> node4(s40)*. % 76.16/76.35 155163[119:MRR:798.0,155161.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.35 155166[119:Res:53.1,155163.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.35 155168[120:Spt:155166.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 155170[120:Res:155168.0,61.1] always3(s40) || -> . % 76.16/76.35 155171[120:SSi:155170.0,78245.0,78249.0,137762.0,154971.0,155161.0] || -> . % 76.16/76.35 155172[120:Spt:155171.0,155166.0,155168.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.35 155173[120:Spt:155171.0,155166.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 155177[120:Res:155173.0,61.1] always3(s41) || -> . % 76.16/76.35 155178[120:SSi:155177.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.35 155179[118:Spt:155178.0,154970.0,154971.0] || until2p7(s40)*+ -> . % 76.16/76.35 155180[118:Spt:155178.0,154970.1] || -> node4(s39)*. % 76.16/76.35 155182[118:MRR:801.0,155180.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.35 155185[118:Res:53.1,155182.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.35 155187[119:Spt:155185.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 155189[119:Res:155187.0,61.1] always3(s39) || -> . % 76.16/76.35 155190[119:SSi:155189.0,78241.0,78244.0,137761.0,154969.0,155180.0] || -> . % 76.16/76.35 155191[119:Spt:155190.0,155185.0,155187.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.35 155192[119:Spt:155190.0,155185.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 155196[119:Res:155192.0,61.1] always3(s40) || -> . % 76.16/76.35 155197[119:SSi:155196.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.35 155198[117:Spt:155197.0,154968.0,154969.0] || until2p7(s39)*+ -> . % 76.16/76.35 155199[117:Spt:155197.0,154968.1] || -> node4(s38)*. % 76.16/76.35 155201[117:MRR:804.0,155199.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.35 155204[117:Res:53.1,155201.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.35 155209[118:Spt:155204.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 155211[118:Res:155209.0,61.1] always3(s38) || -> . % 76.16/76.35 155212[118:SSi:155211.0,78236.0,78240.0,137760.0,154967.0,155199.0] || -> . % 76.16/76.35 155213[118:Spt:155212.0,155204.0,155209.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.35 155214[118:Spt:155212.0,155204.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 155218[118:Res:155214.0,61.1] always3(s39) || -> . % 76.16/76.35 155219[118:SSi:155218.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.35 155220[116:Spt:155219.0,154966.0,154967.0] || until2p7(s38)*+ -> . % 76.16/76.35 155221[116:Spt:155219.0,154966.1] || -> node4(s37)*. % 76.16/76.35 155223[116:MRR:807.0,155221.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.35 155226[116:Res:53.1,155223.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.35 155228[117:Spt:155226.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 155230[117:Res:155228.0,61.1] always3(s37) || -> . % 76.16/76.35 155231[117:SSi:155230.0,78232.0,78235.0,137759.0,154965.0,155221.0] || -> . % 76.16/76.35 155232[117:Spt:155231.0,155226.0,155228.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.35 155233[117:Spt:155231.0,155226.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 155237[117:Res:155233.0,61.1] always3(s38) || -> . % 76.16/76.35 155238[117:SSi:155237.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.35 155239[115:Spt:155238.0,154964.0,154965.0] || until2p7(s37)*+ -> . % 76.16/76.35 155240[115:Spt:155238.0,154964.1] || -> node4(s36)*. % 76.16/76.35 155242[115:MRR:810.0,155240.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.35 155245[115:Res:53.1,155242.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.35 155247[116:Spt:155245.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 155249[116:Res:155247.0,61.1] always3(s36) || -> . % 76.16/76.35 155250[116:SSi:155249.0,78227.0,78231.0,137758.0,154963.0,155240.0] || -> . % 76.16/76.35 155251[116:Spt:155250.0,155245.0,155247.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.35 155252[116:Spt:155250.0,155245.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 155256[116:Res:155252.0,61.1] always3(s37) || -> . % 76.16/76.35 155257[116:SSi:155256.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.35 155258[114:Spt:155257.0,154962.0,154963.0] || until2p7(s36)*+ -> . % 76.16/76.35 155259[114:Spt:155257.0,154962.1] || -> node4(s35)*. % 76.16/76.35 155261[114:MRR:813.0,155259.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.35 155264[114:Res:53.1,155261.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.35 155266[115:Spt:155264.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 155268[115:Res:155266.0,61.1] always3(s35) || -> . % 76.16/76.35 155269[115:SSi:155268.0,78223.0,78226.0,137757.0,154961.0,155259.0] || -> . % 76.16/76.35 155270[115:Spt:155269.0,155264.0,155266.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.35 155271[115:Spt:155269.0,155264.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 155275[115:Res:155271.0,61.1] always3(s36) || -> . % 76.16/76.35 155276[115:SSi:155275.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.35 155277[113:Spt:155276.0,154960.0,154961.0] || until2p7(s35)*+ -> . % 76.16/76.35 155278[113:Spt:155276.0,154960.1] || -> node4(s34)*. % 76.16/76.35 155280[113:MRR:816.0,155278.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.35 155283[113:Res:53.1,155280.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.35 155288[114:Spt:155283.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 155290[114:Res:155288.0,61.1] always3(s34) || -> . % 76.16/76.35 155291[114:SSi:155290.0,78218.0,78222.0,137756.0,154959.0,155278.0] || -> . % 76.16/76.35 155292[114:Spt:155291.0,155283.0,155288.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.35 155293[114:Spt:155291.0,155283.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 155297[114:Res:155293.0,61.1] always3(s35) || -> . % 76.16/76.35 155298[114:SSi:155297.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.35 155299[112:Spt:155298.0,154958.0,154959.0] || until2p7(s34)*+ -> . % 76.16/76.35 155300[112:Spt:155298.0,154958.1] || -> node4(s33)*. % 76.16/76.35 155302[112:MRR:819.0,155300.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.35 155305[112:Res:53.1,155302.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.35 155307[113:Spt:155305.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 155309[113:Res:155307.0,61.1] always3(s33) || -> . % 76.16/76.35 155310[113:SSi:155309.0,78214.0,78217.0,137755.0,154957.0,155300.0] || -> . % 76.16/76.35 155311[113:Spt:155310.0,155305.0,155307.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.35 155312[113:Spt:155310.0,155305.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 155316[113:Res:155312.0,61.1] always3(s34) || -> . % 76.16/76.35 155317[113:SSi:155316.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.35 155318[111:Spt:155317.0,154956.0,154957.0] || until2p7(s33)*+ -> . % 76.16/76.35 155319[111:Spt:155317.0,154956.1] || -> node4(s32)*. % 76.16/76.35 155321[111:MRR:822.0,155319.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.35 155324[111:Res:53.1,155321.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.35 155326[112:Spt:155324.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 155328[112:Res:155326.0,61.1] always3(s32) || -> . % 76.16/76.35 155329[112:SSi:155328.0,78209.0,78213.0,137754.0,154955.0,155319.0] || -> . % 76.16/76.35 155330[112:Spt:155329.0,155324.0,155326.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.35 155331[112:Spt:155329.0,155324.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 155335[112:Res:155331.0,61.1] always3(s33) || -> . % 76.16/76.35 155336[112:SSi:155335.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.35 155337[110:Spt:155336.0,154954.0,154955.0] || until2p7(s32)*+ -> . % 76.16/76.35 155338[110:Spt:155336.0,154954.1] || -> node4(s31)*. % 76.16/76.35 155340[110:MRR:825.0,155338.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.35 155343[110:Res:53.1,155340.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.35 155345[111:Spt:155343.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 155347[111:Res:155345.0,61.1] always3(s31) || -> . % 76.16/76.35 155348[111:SSi:155347.0,78205.0,78208.0,137753.0,154953.0,155338.0] || -> . % 76.16/76.35 155349[111:Spt:155348.0,155343.0,155345.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.35 155350[111:Spt:155348.0,155343.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 155354[111:Res:155350.0,61.1] always3(s32) || -> . % 76.16/76.35 155355[111:SSi:155354.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.35 155356[109:Spt:155355.0,154952.0,154953.0] || until2p7(s31)*+ -> . % 76.16/76.35 155357[109:Spt:155355.0,154952.1] || -> node4(s30)*. % 76.16/76.35 155359[109:MRR:828.0,155357.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.35 155362[109:Res:53.1,155359.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.35 155367[110:Spt:155362.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 155369[110:Res:155367.0,61.1] always3(s30) || -> . % 76.16/76.35 155370[110:SSi:155369.0,78200.0,78204.0,137752.0,154951.0,155357.0] || -> . % 76.16/76.35 155371[110:Spt:155370.0,155362.0,155367.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.35 155372[110:Spt:155370.0,155362.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 155376[110:Res:155372.0,61.1] always3(s31) || -> . % 76.16/76.35 155377[110:SSi:155376.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.35 155378[108:Spt:155377.0,154950.0,154951.0] || until2p7(s30)*+ -> . % 76.16/76.35 155379[108:Spt:155377.0,154950.1] || -> node4(s29)*. % 76.16/76.35 155381[108:MRR:831.0,155379.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.35 155384[108:Res:53.1,155381.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.35 155386[109:Spt:155384.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 155388[109:Res:155386.0,61.1] always3(s29) || -> . % 76.16/76.35 155389[109:SSi:155388.0,78196.0,78199.0,137751.0,154949.0,155379.0] || -> . % 76.16/76.35 155390[109:Spt:155389.0,155384.0,155386.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.35 155391[109:Spt:155389.0,155384.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 155395[109:Res:155391.0,61.1] always3(s30) || -> . % 76.16/76.35 155396[109:SSi:155395.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.35 155397[107:Spt:155396.0,154948.0,154949.0] || until2p7(s29)*+ -> . % 76.16/76.35 155398[107:Spt:155396.0,154948.1] || -> node4(s28)*. % 76.16/76.35 155400[107:MRR:834.0,155398.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.35 155403[107:Res:53.1,155400.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.35 155405[108:Spt:155403.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 155407[108:Res:155405.0,61.1] always3(s28) || -> . % 76.16/76.35 155408[108:SSi:155407.0,78191.0,78195.0,137750.0,154947.0,155398.0] || -> . % 76.16/76.35 155409[108:Spt:155408.0,155403.0,155405.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.35 155410[108:Spt:155408.0,155403.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 155414[108:Res:155410.0,61.1] always3(s29) || -> . % 76.16/76.35 155415[108:SSi:155414.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.35 155416[106:Spt:155415.0,154946.0,154947.0] || until2p7(s28)*+ -> . % 76.16/76.35 155417[106:Spt:155415.0,154946.1] || -> node4(s27)*. % 76.16/76.35 155419[106:MRR:837.0,155417.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.35 155422[106:Res:53.1,155419.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.35 155424[107:Spt:155422.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 155426[107:Res:155424.0,61.1] always3(s27) || -> . % 76.16/76.35 155427[107:SSi:155426.0,78187.0,78190.0,137749.0,154945.0,155417.0] || -> . % 76.16/76.35 155428[107:Spt:155427.0,155422.0,155424.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.35 155429[107:Spt:155427.0,155422.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 155433[107:Res:155429.0,61.1] always3(s28) || -> . % 76.16/76.35 155434[107:SSi:155433.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.35 155435[105:Spt:155434.0,154944.0,154945.0] || until2p7(s27)*+ -> . % 76.16/76.35 155436[105:Spt:155434.0,154944.1] || -> node4(s26)*. % 76.16/76.35 155438[105:MRR:840.0,155436.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.35 155441[105:Res:53.1,155438.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.35 155446[106:Spt:155441.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 155448[106:Res:155446.0,61.1] always3(s26) || -> . % 76.16/76.35 155449[106:SSi:155448.0,78182.0,78186.0,137748.0,154943.0,155436.0] || -> . % 76.16/76.35 155450[106:Spt:155449.0,155441.0,155446.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.35 155451[106:Spt:155449.0,155441.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 155455[106:Res:155451.0,61.1] always3(s27) || -> . % 76.16/76.35 155456[106:SSi:155455.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.35 155457[104:Spt:155456.0,154942.0,154943.0] || until2p7(s26)*+ -> . % 76.16/76.35 155458[104:Spt:155456.0,154942.1] || -> node4(s25)*. % 76.16/76.35 155460[104:MRR:843.0,155458.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.35 155463[104:Res:53.1,155460.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.35 155465[105:Spt:155463.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 155467[105:Res:155465.0,61.1] always3(s25) || -> . % 76.16/76.35 155468[105:SSi:155467.0,78178.0,78181.0,137747.0,154941.0,155458.0] || -> . % 76.16/76.35 155469[105:Spt:155468.0,155463.0,155465.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.35 155470[105:Spt:155468.0,155463.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 155474[105:Res:155470.0,61.1] always3(s26) || -> . % 76.16/76.35 155475[105:SSi:155474.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.35 155476[103:Spt:155475.0,154940.0,154941.0] || until2p7(s25)*+ -> . % 76.16/76.35 155477[103:Spt:155475.0,154940.1] || -> node4(s24)*. % 76.16/76.35 155479[103:MRR:846.0,155477.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.35 155482[103:Res:53.1,155479.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.35 155484[104:Spt:155482.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 155486[104:Res:155484.0,61.1] always3(s24) || -> . % 76.16/76.35 155487[104:SSi:155486.0,78173.0,78177.0,137746.0,154939.0,155477.0] || -> . % 76.16/76.35 155488[104:Spt:155487.0,155482.0,155484.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.35 155489[104:Spt:155487.0,155482.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 155493[104:Res:155489.0,61.1] always3(s25) || -> . % 76.16/76.35 155494[104:SSi:155493.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.35 155495[102:Spt:155494.0,154938.0,154939.0] || until2p7(s24)*+ -> . % 76.16/76.35 155496[102:Spt:155494.0,154938.1] || -> node4(s23)*. % 76.16/76.35 155498[102:MRR:849.0,155496.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.35 155501[102:Res:53.1,155498.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.35 155503[103:Spt:155501.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 155505[103:Res:155503.0,61.1] always3(s23) || -> . % 76.16/76.35 155506[103:SSi:155505.0,78169.0,78172.0,137745.0,154937.0,155496.0] || -> . % 76.16/76.35 155507[103:Spt:155506.0,155501.0,155503.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.35 155508[103:Spt:155506.0,155501.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 155512[103:Res:155508.0,61.1] always3(s24) || -> . % 76.16/76.35 155513[103:SSi:155512.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.35 155514[101:Spt:155513.0,154936.0,154937.0] || until2p7(s23)*+ -> . % 76.16/76.35 155515[101:Spt:155513.0,154936.1] || -> node4(s22)*. % 76.16/76.35 155517[101:MRR:852.0,155515.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.35 155520[101:Res:53.1,155517.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.35 155525[102:Spt:155520.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 155527[102:Res:155525.0,61.1] always3(s22) || -> . % 76.16/76.35 155528[102:SSi:155527.0,78164.0,78168.0,137744.0,154935.0,155515.0] || -> . % 76.16/76.35 155529[102:Spt:155528.0,155520.0,155525.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.35 155530[102:Spt:155528.0,155520.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 155534[102:Res:155530.0,61.1] always3(s23) || -> . % 76.16/76.35 155535[102:SSi:155534.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.35 155536[100:Spt:155535.0,154934.0,154935.0] || until2p7(s22)*+ -> . % 76.16/76.35 155537[100:Spt:155535.0,154934.1] || -> node4(s21)*. % 76.16/76.35 155539[100:MRR:855.0,155537.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.35 155542[100:Res:53.1,155539.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.35 155544[101:Spt:155542.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 155546[101:Res:155544.0,61.1] always3(s21) || -> . % 76.16/76.35 155547[101:SSi:155546.0,78160.0,78163.0,137743.0,154933.0,155537.0] || -> . % 76.16/76.35 155548[101:Spt:155547.0,155542.0,155544.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.35 155549[101:Spt:155547.0,155542.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 155553[101:Res:155549.0,61.1] always3(s22) || -> . % 76.16/76.35 155554[101:SSi:155553.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.35 155555[99:Spt:155554.0,154932.0,154933.0] || until2p7(s21)*+ -> . % 76.16/76.35 155556[99:Spt:155554.0,154932.1] || -> node4(s20)*. % 76.16/76.35 155558[99:MRR:858.0,155556.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.35 155561[99:Res:53.1,155558.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.35 155563[100:Spt:155561.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 155565[100:Res:155563.0,61.1] always3(s20) || -> . % 76.16/76.35 155566[100:SSi:155565.0,78155.0,78159.0,137742.0,154931.0,155556.0] || -> . % 76.16/76.35 155567[100:Spt:155566.0,155561.0,155563.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.35 155568[100:Spt:155566.0,155561.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 155572[100:Res:155568.0,61.1] always3(s21) || -> . % 76.16/76.35 155573[100:SSi:155572.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.35 155574[98:Spt:155573.0,154930.0,154931.0] || until2p7(s20)*+ -> . % 76.16/76.35 155575[98:Spt:155573.0,154930.1] || -> node4(s19)*. % 76.16/76.35 155577[98:MRR:861.0,155575.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.35 155580[98:Res:53.1,155577.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.35 155582[99:Spt:155580.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 155584[99:Res:155582.0,61.1] always3(s19) || -> . % 76.16/76.35 155585[99:SSi:155584.0,78151.0,78154.0,137741.0,154929.0,155575.0] || -> . % 76.16/76.35 155586[99:Spt:155585.0,155580.0,155582.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.35 155587[99:Spt:155585.0,155580.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 155591[99:Res:155587.0,61.1] always3(s20) || -> . % 76.16/76.35 155592[99:SSi:155591.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.35 155593[97:Spt:155592.0,154928.0,154929.0] || until2p7(s19)*+ -> . % 76.16/76.35 155594[97:Spt:155592.0,154928.1] || -> node4(s18)*. % 76.16/76.35 155596[97:MRR:864.0,155594.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.35 155599[97:Res:53.1,155596.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.35 155604[98:Spt:155599.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 155606[98:Res:155604.0,61.1] always3(s18) || -> . % 76.16/76.35 155607[98:SSi:155606.0,78146.0,78150.0,137740.0,154927.0,155594.0] || -> . % 76.16/76.35 155608[98:Spt:155607.0,155599.0,155604.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.35 155609[98:Spt:155607.0,155599.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 155613[98:Res:155609.0,61.1] always3(s19) || -> . % 76.16/76.35 155614[98:SSi:155613.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.35 155615[96:Spt:155614.0,154926.0,154927.0] || until2p7(s18)*+ -> . % 76.16/76.35 155616[96:Spt:155614.0,154926.1] || -> node4(s17)*. % 76.16/76.35 155618[96:MRR:867.0,155616.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.35 155621[96:Res:53.1,155618.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.35 155623[97:Spt:155621.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 155625[97:Res:155623.0,61.1] always3(s17) || -> . % 76.16/76.35 155626[97:SSi:155625.0,78142.0,78145.0,137739.0,154925.0,155616.0] || -> . % 76.16/76.35 155627[97:Spt:155626.0,155621.0,155623.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.35 155628[97:Spt:155626.0,155621.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 155632[97:Res:155628.0,61.1] always3(s18) || -> . % 76.16/76.35 155633[97:SSi:155632.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.35 155634[95:Spt:155633.0,154924.0,154925.0] || until2p7(s17)*+ -> . % 76.16/76.35 155635[95:Spt:155633.0,154924.1] || -> node4(s16)*. % 76.16/76.35 155637[95:MRR:870.0,155635.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.35 155640[95:Res:53.1,155637.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.35 155642[96:Spt:155640.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 155644[96:Res:155642.0,61.1] always3(s16) || -> . % 76.16/76.35 155645[96:SSi:155644.0,78137.0,78141.0,137738.0,154923.0,155635.0] || -> . % 76.16/76.35 155646[96:Spt:155645.0,155640.0,155642.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.35 155647[96:Spt:155645.0,155640.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 155651[96:Res:155647.0,61.1] always3(s17) || -> . % 76.16/76.35 155652[96:SSi:155651.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.35 155653[94:Spt:155652.0,154922.0,154923.0] || until2p7(s16)*+ -> . % 76.16/76.35 155654[94:Spt:155652.0,154922.1] || -> node4(s15)*. % 76.16/76.35 155656[94:MRR:873.0,155654.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.35 155659[94:Res:53.1,155656.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.35 155661[95:Spt:155659.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 155663[95:Res:155661.0,61.1] always3(s15) || -> . % 76.16/76.35 155664[95:SSi:155663.0,78133.0,78136.0,137737.0,154921.0,155654.0] || -> . % 76.16/76.35 155665[95:Spt:155664.0,155659.0,155661.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.35 155666[95:Spt:155664.0,155659.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 155670[95:Res:155666.0,61.1] always3(s16) || -> . % 76.16/76.35 155671[95:SSi:155670.0,78137.0,78141.0,137738.0] || -> . % 76.16/76.35 155672[93:Spt:155671.0,154920.0,154921.0] || until2p7(s15)*+ -> . % 76.16/76.35 155673[93:Spt:155671.0,154920.1] || -> node4(s14)*. % 76.16/76.35 155675[93:MRR:876.0,155673.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.35 155678[93:Res:53.1,155675.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.35 155683[94:Spt:155678.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.35 155685[94:Res:155683.0,61.1] always3(s14) || -> . % 76.16/76.35 155686[94:SSi:155685.0,78128.0,78132.0,137736.0,154919.0,155673.0] || -> . % 76.16/76.35 155687[94:Spt:155686.0,155678.0,155683.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.35 155688[94:Spt:155686.0,155678.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 155692[94:Res:155688.0,61.1] always3(s15) || -> . % 76.16/76.35 155693[94:SSi:155692.0,78133.0,78136.0,137737.0] || -> . % 76.16/76.35 155694[92:Spt:155693.0,154918.0,154919.0] || until2p7(s14)*+ -> . % 76.16/76.35 155695[92:Spt:155693.0,154918.1] || -> node4(s13)*. % 76.16/76.35 155697[92:MRR:879.0,155695.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.35 155700[92:Res:53.1,155697.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.35 155702[92:MRR:155700.0,154908.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.35 155704[92:Res:155702.0,61.1] always3(s14) || -> . % 76.16/76.35 155705[92:SSi:155704.0,78128.0,78132.0,137736.0] || -> . % 76.16/76.35 155706[90:Spt:155705.0,154772.0,154775.0] || trans(s49,s13)*+ -> . % 76.16/76.35 155707[90:Spt:155705.0,154772.1,154772.2,154772.3,154772.4,154772.5,154772.6,154772.7,154772.8,154772.9] || -> trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.35 155709[90:MRR:154774.1,155706.0] xuntil6(s49) || -> trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.35 155710[91:Spt:155707.0] || -> trans(s49,s12)*. % 76.16/76.35 155711[91:Res:155710.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s12)*. % 76.16/76.35 155713[91:Res:155710.0,60.0] || -> node2(s49,s12)*. % 76.16/76.35 155714[91:SSi:155711.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s12)*. % 76.16/76.35 155715[91:Res:155713.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)*. % 76.16/76.35 155839[91:SoR:155715.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)*. % 76.16/76.35 155841[91:SoR:155839.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)* xuntil6(s49). % 76.16/76.35 155842[91:SSi:155841.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s12,c_busy)* xuntil6(s49). % 76.16/76.35 155843[92:Spt:155842.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.35 155845[92:Res:155843.0,61.1] always3(s12) || -> . % 76.16/76.35 155846[92:SSi:155845.0,78119.0,78123.0,137734.0] || -> . % 76.16/76.35 155847[92:Spt:155846.0,155842.1,155843.0] || m_main_v_state(s12,c_busy)*+ -> . % 76.16/76.35 155848[92:Spt:155846.0,155842.0,155842.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.35 155852[92:MRR:155839.2,155847.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.35 155853[92:Res:53.1,155848.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.35 155855[92:MRR:155853.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.35 155856[92:MRR:155714.0,155855.0] || -> until2p7(s12)*. % 76.16/76.35 155857[92:MRR:208.0,155856.0] || -> until2p7(s13)* node4(s12). % 76.16/76.35 155858[93:Spt:155857.0] || -> until2p7(s13)*. % 76.16/76.35 155859[93:MRR:209.0,155858.0] || -> until2p7(s14)* node4(s13). % 76.16/76.35 155860[94:Spt:155859.0] || -> until2p7(s14)*. % 76.16/76.35 155861[94:MRR:210.0,155860.0] || -> until2p7(s15)* node4(s14). % 76.16/76.35 155862[95:Spt:155861.0] || -> until2p7(s15)*. % 76.16/76.35 155863[95:MRR:211.0,155862.0] || -> until2p7(s16)* node4(s15). % 76.16/76.35 155864[96:Spt:155863.0] || -> until2p7(s16)*. % 76.16/76.35 155865[96:MRR:212.0,155864.0] || -> until2p7(s17)* node4(s16). % 76.16/76.35 155866[97:Spt:155865.0] || -> until2p7(s17)*. % 76.16/76.35 155867[97:MRR:213.0,155866.0] || -> until2p7(s18)* node4(s17). % 76.16/76.35 155868[98:Spt:155867.0] || -> until2p7(s18)*. % 76.16/76.35 155869[98:MRR:214.0,155868.0] || -> until2p7(s19)* node4(s18). % 76.16/76.35 155870[99:Spt:155869.0] || -> until2p7(s19)*. % 76.16/76.35 155871[99:MRR:215.0,155870.0] || -> until2p7(s20)* node4(s19). % 76.16/76.35 155872[100:Spt:155871.0] || -> until2p7(s20)*. % 76.16/76.35 155873[100:MRR:216.0,155872.0] || -> until2p7(s21)* node4(s20). % 76.16/76.35 155874[101:Spt:155873.0] || -> until2p7(s21)*. % 76.16/76.35 155875[101:MRR:217.0,155874.0] || -> until2p7(s22)* node4(s21). % 76.16/76.35 155876[102:Spt:155875.0] || -> until2p7(s22)*. % 76.16/76.35 155877[102:MRR:218.0,155876.0] || -> until2p7(s23)* node4(s22). % 76.16/76.35 155878[103:Spt:155877.0] || -> until2p7(s23)*. % 76.16/76.35 155879[103:MRR:219.0,155878.0] || -> until2p7(s24)* node4(s23). % 76.16/76.35 155880[104:Spt:155879.0] || -> until2p7(s24)*. % 76.16/76.35 155881[104:MRR:220.0,155880.0] || -> until2p7(s25)* node4(s24). % 76.16/76.35 155882[105:Spt:155881.0] || -> until2p7(s25)*. % 76.16/76.35 155883[105:MRR:221.0,155882.0] || -> until2p7(s26)* node4(s25). % 76.16/76.35 155884[106:Spt:155883.0] || -> until2p7(s26)*. % 76.16/76.35 155885[106:MRR:222.0,155884.0] || -> until2p7(s27)* node4(s26). % 76.16/76.35 155886[107:Spt:155885.0] || -> until2p7(s27)*. % 76.16/76.35 155887[107:MRR:223.0,155886.0] || -> until2p7(s28)* node4(s27). % 76.16/76.35 155888[108:Spt:155887.0] || -> until2p7(s28)*. % 76.16/76.35 155889[108:MRR:224.0,155888.0] || -> until2p7(s29)* node4(s28). % 76.16/76.35 155890[109:Spt:155889.0] || -> until2p7(s29)*. % 76.16/76.35 155891[109:MRR:225.0,155890.0] || -> until2p7(s30)* node4(s29). % 76.16/76.35 155892[110:Spt:155891.0] || -> until2p7(s30)*. % 76.16/76.35 155893[110:MRR:226.0,155892.0] || -> until2p7(s31)* node4(s30). % 76.16/76.35 155894[111:Spt:155893.0] || -> until2p7(s31)*. % 76.16/76.35 155895[111:MRR:227.0,155894.0] || -> until2p7(s32)* node4(s31). % 76.16/76.35 155896[112:Spt:155895.0] || -> until2p7(s32)*. % 76.16/76.35 155897[112:MRR:228.0,155896.0] || -> until2p7(s33)* node4(s32). % 76.16/76.35 155898[113:Spt:155897.0] || -> until2p7(s33)*. % 76.16/76.35 155899[113:MRR:229.0,155898.0] || -> until2p7(s34)* node4(s33). % 76.16/76.35 155900[114:Spt:155899.0] || -> until2p7(s34)*. % 76.16/76.35 155901[114:MRR:230.0,155900.0] || -> until2p7(s35)* node4(s34). % 76.16/76.35 155902[115:Spt:155901.0] || -> until2p7(s35)*. % 76.16/76.35 155903[115:MRR:231.0,155902.0] || -> until2p7(s36)* node4(s35). % 76.16/76.35 155904[116:Spt:155903.0] || -> until2p7(s36)*. % 76.16/76.35 155905[116:MRR:232.0,155904.0] || -> until2p7(s37)* node4(s36). % 76.16/76.35 155906[117:Spt:155905.0] || -> until2p7(s37)*. % 76.16/76.35 155907[117:MRR:235.0,155906.0] || -> until2p7(s38)* node4(s37). % 76.16/76.35 155908[118:Spt:155907.0] || -> until2p7(s38)*. % 76.16/76.35 155909[118:MRR:236.0,155908.0] || -> until2p7(s39)* node4(s38). % 76.16/76.35 155910[119:Spt:155909.0] || -> until2p7(s39)*. % 76.16/76.35 155911[119:MRR:237.0,155910.0] || -> until2p7(s40)* node4(s39). % 76.16/76.35 155912[120:Spt:155911.0] || -> until2p7(s40)*. % 76.16/76.35 155913[120:MRR:238.0,155912.0] || -> until2p7(s41)* node4(s40). % 76.16/76.35 155914[121:Spt:155913.0] || -> until2p7(s41)*. % 76.16/76.35 155915[121:MRR:239.0,155914.0] || -> until2p7(s42)* node4(s41). % 76.16/76.35 155916[122:Spt:155915.0] || -> until2p7(s42)*. % 76.16/76.35 155917[122:MRR:240.0,155916.0] || -> until2p7(s43)* node4(s42). % 76.16/76.35 155918[123:Spt:155917.0] || -> until2p7(s43)*. % 76.16/76.35 155919[123:MRR:241.0,155918.0] || -> until2p7(s44)* node4(s43). % 76.16/76.35 155920[124:Spt:155919.0] || -> until2p7(s44)*. % 76.16/76.35 155921[124:MRR:539.0,155920.0] || -> until2p7(s45)* node4(s44). % 76.16/76.35 155922[125:Spt:155921.0] || -> until2p7(s45)*. % 76.16/76.35 155923[125:MRR:544.0,155922.0] || -> until2p7(s46)* node4(s45). % 76.16/76.35 155924[126:Spt:155923.0] || -> until2p7(s46)*. % 76.16/76.35 155925[126:MRR:549.0,155924.0] || -> until2p7(s47)* node4(s46). % 76.16/76.35 155926[127:Spt:155925.0] || -> until2p7(s47)*. % 76.16/76.35 155927[127:MRR:554.0,155926.0] || -> until2p7(s48)* node4(s47). % 76.16/76.35 155928[128:Spt:155927.0] || -> until2p7(s48)*. % 76.16/76.35 155929[128:MRR:559.0,155928.0] || -> until2p7(s49)* node4(s48). % 76.16/76.35 155930[129:Spt:155929.0] || -> until2p7(s49)*. % 76.16/76.35 155931[129:MRR:194.0,155930.0] || -> node4(s49)*. % 76.16/76.35 155932[129:MRR:155852.0,155931.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.35 155933[129:Res:53.1,155932.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.35 155935[129:MRR:155933.0,78381.0] || -> . % 76.16/76.35 155936[129:Spt:155935.0,155929.0,155930.0] || until2p7(s49)*+ -> . % 76.16/76.35 155937[129:Spt:155935.0,155929.1] || -> node4(s48)*. % 76.16/76.35 155938[129:MRR:78384.0,155937.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.35 155941[129:Res:53.1,155938.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 155944[129:Res:155941.0,61.1] always3(s48) || -> . % 76.16/76.35 155945[129:SSi:155944.0,78281.0,78387.0,137770.0,155928.0,155937.0] || -> . % 76.16/76.35 155946[128:Spt:155945.0,155927.0,155928.0] || until2p7(s48)*+ -> . % 76.16/76.35 155947[128:Spt:155945.0,155927.1] || -> node4(s47)*. % 76.16/76.35 155949[128:MRR:777.0,155947.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.35 155964[128:Res:53.1,155949.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.35 155969[129:Spt:155964.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 155971[129:Res:155969.0,61.1] always3(s47) || -> . % 76.16/76.35 155972[129:SSi:155971.0,78277.0,78280.0,137769.0,155926.0,155947.0] || -> . % 76.16/76.35 155973[129:Spt:155972.0,155964.0,155969.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.35 155974[129:Spt:155972.0,155964.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 155978[129:Res:155974.0,61.1] always3(s48) || -> . % 76.16/76.35 155979[129:SSi:155978.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.35 155980[127:Spt:155979.0,155925.0,155926.0] || until2p7(s47)*+ -> . % 76.16/76.35 155981[127:Spt:155979.0,155925.1] || -> node4(s46)*. % 76.16/76.35 155983[127:MRR:780.0,155981.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.35 155990[127:Res:53.1,155983.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.35 155992[128:Spt:155990.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 155994[128:Res:155992.0,61.1] always3(s46) || -> . % 76.16/76.35 155995[128:SSi:155994.0,78272.0,78276.0,137768.0,155924.0,155981.0] || -> . % 76.16/76.35 155996[128:Spt:155995.0,155990.0,155992.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.35 155997[128:Spt:155995.0,155990.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 156001[128:Res:155997.0,61.1] always3(s47) || -> . % 76.16/76.35 156002[128:SSi:156001.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.35 156003[126:Spt:156002.0,155923.0,155924.0] || until2p7(s46)*+ -> . % 76.16/76.35 156004[126:Spt:156002.0,155923.1] || -> node4(s45)*. % 76.16/76.35 156006[126:MRR:783.0,156004.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.35 156009[126:Res:53.1,156006.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.35 156014[127:Spt:156009.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 156016[127:Res:156014.0,61.1] always3(s45) || -> . % 76.16/76.35 156017[127:SSi:156016.0,78268.0,78271.0,137767.0,155922.0,156004.0] || -> . % 76.16/76.35 156018[127:Spt:156017.0,156009.0,156014.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.35 156019[127:Spt:156017.0,156009.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 156023[127:Res:156019.0,61.1] always3(s46) || -> . % 76.16/76.35 156024[127:SSi:156023.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.35 156025[125:Spt:156024.0,155921.0,155922.0] || until2p7(s45)*+ -> . % 76.16/76.35 156026[125:Spt:156024.0,155921.1] || -> node4(s44)*. % 76.16/76.35 156028[125:MRR:786.0,156026.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.35 156031[125:Res:53.1,156028.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.35 156033[126:Spt:156031.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 156035[126:Res:156033.0,61.1] always3(s44) || -> . % 76.16/76.35 156036[126:SSi:156035.0,78263.0,78267.0,137766.0,155920.0,156026.0] || -> . % 76.16/76.35 156037[126:Spt:156036.0,156031.0,156033.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.35 156038[126:Spt:156036.0,156031.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 156042[126:Res:156038.0,61.1] always3(s45) || -> . % 76.16/76.35 156043[126:SSi:156042.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.35 156044[124:Spt:156043.0,155919.0,155920.0] || until2p7(s44)*+ -> . % 76.16/76.35 156045[124:Spt:156043.0,155919.1] || -> node4(s43)*. % 76.16/76.35 156047[124:MRR:789.0,156045.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.35 156050[124:Res:53.1,156047.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.35 156052[125:Spt:156050.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 156054[125:Res:156052.0,61.1] always3(s43) || -> . % 76.16/76.35 156055[125:SSi:156054.0,78259.0,78262.0,137765.0,155918.0,156045.0] || -> . % 76.16/76.35 156056[125:Spt:156055.0,156050.0,156052.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.35 156057[125:Spt:156055.0,156050.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 156061[125:Res:156057.0,61.1] always3(s44) || -> . % 76.16/76.35 156062[125:SSi:156061.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.35 156063[123:Spt:156062.0,155917.0,155918.0] || until2p7(s43)*+ -> . % 76.16/76.35 156064[123:Spt:156062.0,155917.1] || -> node4(s42)*. % 76.16/76.35 156066[123:MRR:792.0,156064.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.35 156069[123:Res:53.1,156066.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.35 156071[124:Spt:156069.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 156073[124:Res:156071.0,61.1] always3(s42) || -> . % 76.16/76.35 156074[124:SSi:156073.0,78254.0,78258.0,137764.0,155916.0,156064.0] || -> . % 76.16/76.35 156075[124:Spt:156074.0,156069.0,156071.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.35 156076[124:Spt:156074.0,156069.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 156080[124:Res:156076.0,61.1] always3(s43) || -> . % 76.16/76.35 156081[124:SSi:156080.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.35 156082[122:Spt:156081.0,155915.0,155916.0] || until2p7(s42)*+ -> . % 76.16/76.35 156083[122:Spt:156081.0,155915.1] || -> node4(s41)*. % 76.16/76.35 156085[122:MRR:795.0,156083.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.35 156088[122:Res:53.1,156085.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.35 156093[123:Spt:156088.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 156095[123:Res:156093.0,61.1] always3(s41) || -> . % 76.16/76.35 156096[123:SSi:156095.0,78250.0,78253.0,137763.0,155914.0,156083.0] || -> . % 76.16/76.35 156097[123:Spt:156096.0,156088.0,156093.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.35 156098[123:Spt:156096.0,156088.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 156102[123:Res:156098.0,61.1] always3(s42) || -> . % 76.16/76.35 156103[123:SSi:156102.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.35 156104[121:Spt:156103.0,155913.0,155914.0] || until2p7(s41)*+ -> . % 76.16/76.35 156105[121:Spt:156103.0,155913.1] || -> node4(s40)*. % 76.16/76.35 156107[121:MRR:798.0,156105.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.35 156110[121:Res:53.1,156107.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.35 156112[122:Spt:156110.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 156114[122:Res:156112.0,61.1] always3(s40) || -> . % 76.16/76.35 156115[122:SSi:156114.0,78245.0,78249.0,137762.0,155912.0,156105.0] || -> . % 76.16/76.35 156116[122:Spt:156115.0,156110.0,156112.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.35 156117[122:Spt:156115.0,156110.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 156121[122:Res:156117.0,61.1] always3(s41) || -> . % 76.16/76.35 156122[122:SSi:156121.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.35 156123[120:Spt:156122.0,155911.0,155912.0] || until2p7(s40)*+ -> . % 76.16/76.35 156124[120:Spt:156122.0,155911.1] || -> node4(s39)*. % 76.16/76.35 156126[120:MRR:801.0,156124.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.35 156129[120:Res:53.1,156126.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.35 156131[121:Spt:156129.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 156133[121:Res:156131.0,61.1] always3(s39) || -> . % 76.16/76.35 156134[121:SSi:156133.0,78241.0,78244.0,137761.0,155910.0,156124.0] || -> . % 76.16/76.35 156135[121:Spt:156134.0,156129.0,156131.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.35 156136[121:Spt:156134.0,156129.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 156140[121:Res:156136.0,61.1] always3(s40) || -> . % 76.16/76.35 156141[121:SSi:156140.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.35 156142[119:Spt:156141.0,155909.0,155910.0] || until2p7(s39)*+ -> . % 76.16/76.35 156143[119:Spt:156141.0,155909.1] || -> node4(s38)*. % 76.16/76.35 156145[119:MRR:804.0,156143.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.35 156148[119:Res:53.1,156145.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.35 156150[120:Spt:156148.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 156152[120:Res:156150.0,61.1] always3(s38) || -> . % 76.16/76.35 156153[120:SSi:156152.0,78236.0,78240.0,137760.0,155908.0,156143.0] || -> . % 76.16/76.35 156154[120:Spt:156153.0,156148.0,156150.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.35 156155[120:Spt:156153.0,156148.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 156159[120:Res:156155.0,61.1] always3(s39) || -> . % 76.16/76.35 156160[120:SSi:156159.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.35 156161[118:Spt:156160.0,155907.0,155908.0] || until2p7(s38)*+ -> . % 76.16/76.35 156162[118:Spt:156160.0,155907.1] || -> node4(s37)*. % 76.16/76.35 156164[118:MRR:807.0,156162.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.35 156167[118:Res:53.1,156164.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.35 156172[119:Spt:156167.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 156174[119:Res:156172.0,61.1] always3(s37) || -> . % 76.16/76.35 156175[119:SSi:156174.0,78232.0,78235.0,137759.0,155906.0,156162.0] || -> . % 76.16/76.35 156176[119:Spt:156175.0,156167.0,156172.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.35 156177[119:Spt:156175.0,156167.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 156181[119:Res:156177.0,61.1] always3(s38) || -> . % 76.16/76.35 156182[119:SSi:156181.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.35 156183[117:Spt:156182.0,155905.0,155906.0] || until2p7(s37)*+ -> . % 76.16/76.35 156184[117:Spt:156182.0,155905.1] || -> node4(s36)*. % 76.16/76.35 156186[117:MRR:810.0,156184.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.35 156189[117:Res:53.1,156186.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.35 156191[118:Spt:156189.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 156193[118:Res:156191.0,61.1] always3(s36) || -> . % 76.16/76.35 156194[118:SSi:156193.0,78227.0,78231.0,137758.0,155904.0,156184.0] || -> . % 76.16/76.35 156195[118:Spt:156194.0,156189.0,156191.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.35 156196[118:Spt:156194.0,156189.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 156200[118:Res:156196.0,61.1] always3(s37) || -> . % 76.16/76.35 156201[118:SSi:156200.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.35 156202[116:Spt:156201.0,155903.0,155904.0] || until2p7(s36)*+ -> . % 76.16/76.35 156203[116:Spt:156201.0,155903.1] || -> node4(s35)*. % 76.16/76.35 156205[116:MRR:813.0,156203.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.35 156208[116:Res:53.1,156205.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.35 156210[117:Spt:156208.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 156212[117:Res:156210.0,61.1] always3(s35) || -> . % 76.16/76.35 156213[117:SSi:156212.0,78223.0,78226.0,137757.0,155902.0,156203.0] || -> . % 76.16/76.35 156214[117:Spt:156213.0,156208.0,156210.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.35 156215[117:Spt:156213.0,156208.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 156219[117:Res:156215.0,61.1] always3(s36) || -> . % 76.16/76.35 156220[117:SSi:156219.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.35 156221[115:Spt:156220.0,155901.0,155902.0] || until2p7(s35)*+ -> . % 76.16/76.35 156222[115:Spt:156220.0,155901.1] || -> node4(s34)*. % 76.16/76.35 156224[115:MRR:816.0,156222.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.35 156227[115:Res:53.1,156224.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.35 156229[116:Spt:156227.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 156231[116:Res:156229.0,61.1] always3(s34) || -> . % 76.16/76.35 156232[116:SSi:156231.0,78218.0,78222.0,137756.0,155900.0,156222.0] || -> . % 76.16/76.35 156233[116:Spt:156232.0,156227.0,156229.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.35 156234[116:Spt:156232.0,156227.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 156238[116:Res:156234.0,61.1] always3(s35) || -> . % 76.16/76.35 156239[116:SSi:156238.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.35 156240[114:Spt:156239.0,155899.0,155900.0] || until2p7(s34)*+ -> . % 76.16/76.35 156241[114:Spt:156239.0,155899.1] || -> node4(s33)*. % 76.16/76.35 156243[114:MRR:819.0,156241.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.35 156246[114:Res:53.1,156243.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.35 156251[115:Spt:156246.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 156253[115:Res:156251.0,61.1] always3(s33) || -> . % 76.16/76.35 156254[115:SSi:156253.0,78214.0,78217.0,137755.0,155898.0,156241.0] || -> . % 76.16/76.35 156255[115:Spt:156254.0,156246.0,156251.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.35 156256[115:Spt:156254.0,156246.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 156260[115:Res:156256.0,61.1] always3(s34) || -> . % 76.16/76.35 156261[115:SSi:156260.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.35 156262[113:Spt:156261.0,155897.0,155898.0] || until2p7(s33)*+ -> . % 76.16/76.35 156263[113:Spt:156261.0,155897.1] || -> node4(s32)*. % 76.16/76.35 156265[113:MRR:822.0,156263.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.35 156268[113:Res:53.1,156265.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.35 156270[114:Spt:156268.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 156272[114:Res:156270.0,61.1] always3(s32) || -> . % 76.16/76.35 156273[114:SSi:156272.0,78209.0,78213.0,137754.0,155896.0,156263.0] || -> . % 76.16/76.35 156274[114:Spt:156273.0,156268.0,156270.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.35 156275[114:Spt:156273.0,156268.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 156279[114:Res:156275.0,61.1] always3(s33) || -> . % 76.16/76.35 156280[114:SSi:156279.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.35 156281[112:Spt:156280.0,155895.0,155896.0] || until2p7(s32)*+ -> . % 76.16/76.35 156282[112:Spt:156280.0,155895.1] || -> node4(s31)*. % 76.16/76.35 156284[112:MRR:825.0,156282.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.35 156287[112:Res:53.1,156284.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.35 156289[113:Spt:156287.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 156291[113:Res:156289.0,61.1] always3(s31) || -> . % 76.16/76.35 156292[113:SSi:156291.0,78205.0,78208.0,137753.0,155894.0,156282.0] || -> . % 76.16/76.35 156293[113:Spt:156292.0,156287.0,156289.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.35 156294[113:Spt:156292.0,156287.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 156298[113:Res:156294.0,61.1] always3(s32) || -> . % 76.16/76.35 156299[113:SSi:156298.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.35 156300[111:Spt:156299.0,155893.0,155894.0] || until2p7(s31)*+ -> . % 76.16/76.35 156301[111:Spt:156299.0,155893.1] || -> node4(s30)*. % 76.16/76.35 156303[111:MRR:828.0,156301.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.35 156306[111:Res:53.1,156303.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.35 156308[112:Spt:156306.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 156310[112:Res:156308.0,61.1] always3(s30) || -> . % 76.16/76.35 156311[112:SSi:156310.0,78200.0,78204.0,137752.0,155892.0,156301.0] || -> . % 76.16/76.35 156312[112:Spt:156311.0,156306.0,156308.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.35 156313[112:Spt:156311.0,156306.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 156317[112:Res:156313.0,61.1] always3(s31) || -> . % 76.16/76.35 156318[112:SSi:156317.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.35 156319[110:Spt:156318.0,155891.0,155892.0] || until2p7(s30)*+ -> . % 76.16/76.35 156320[110:Spt:156318.0,155891.1] || -> node4(s29)*. % 76.16/76.35 156322[110:MRR:831.0,156320.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.35 156325[110:Res:53.1,156322.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.35 156330[111:Spt:156325.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 156332[111:Res:156330.0,61.1] always3(s29) || -> . % 76.16/76.35 156333[111:SSi:156332.0,78196.0,78199.0,137751.0,155890.0,156320.0] || -> . % 76.16/76.35 156334[111:Spt:156333.0,156325.0,156330.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.35 156335[111:Spt:156333.0,156325.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 156339[111:Res:156335.0,61.1] always3(s30) || -> . % 76.16/76.35 156340[111:SSi:156339.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.35 156341[109:Spt:156340.0,155889.0,155890.0] || until2p7(s29)*+ -> . % 76.16/76.35 156342[109:Spt:156340.0,155889.1] || -> node4(s28)*. % 76.16/76.35 156344[109:MRR:834.0,156342.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.35 156347[109:Res:53.1,156344.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.35 156349[110:Spt:156347.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 156351[110:Res:156349.0,61.1] always3(s28) || -> . % 76.16/76.35 156352[110:SSi:156351.0,78191.0,78195.0,137750.0,155888.0,156342.0] || -> . % 76.16/76.35 156353[110:Spt:156352.0,156347.0,156349.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.35 156354[110:Spt:156352.0,156347.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 156358[110:Res:156354.0,61.1] always3(s29) || -> . % 76.16/76.35 156359[110:SSi:156358.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.35 156360[108:Spt:156359.0,155887.0,155888.0] || until2p7(s28)*+ -> . % 76.16/76.35 156361[108:Spt:156359.0,155887.1] || -> node4(s27)*. % 76.16/76.35 156363[108:MRR:837.0,156361.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.35 156366[108:Res:53.1,156363.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.35 156368[109:Spt:156366.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 156370[109:Res:156368.0,61.1] always3(s27) || -> . % 76.16/76.35 156371[109:SSi:156370.0,78187.0,78190.0,137749.0,155886.0,156361.0] || -> . % 76.16/76.35 156372[109:Spt:156371.0,156366.0,156368.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.35 156373[109:Spt:156371.0,156366.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 156377[109:Res:156373.0,61.1] always3(s28) || -> . % 76.16/76.35 156378[109:SSi:156377.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.35 156379[107:Spt:156378.0,155885.0,155886.0] || until2p7(s27)*+ -> . % 76.16/76.35 156380[107:Spt:156378.0,155885.1] || -> node4(s26)*. % 76.16/76.35 156382[107:MRR:840.0,156380.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.35 156385[107:Res:53.1,156382.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.35 156387[108:Spt:156385.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 156389[108:Res:156387.0,61.1] always3(s26) || -> . % 76.16/76.35 156390[108:SSi:156389.0,78182.0,78186.0,137748.0,155884.0,156380.0] || -> . % 76.16/76.35 156391[108:Spt:156390.0,156385.0,156387.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.35 156392[108:Spt:156390.0,156385.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 156396[108:Res:156392.0,61.1] always3(s27) || -> . % 76.16/76.35 156397[108:SSi:156396.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.35 156398[106:Spt:156397.0,155883.0,155884.0] || until2p7(s26)*+ -> . % 76.16/76.35 156399[106:Spt:156397.0,155883.1] || -> node4(s25)*. % 76.16/76.35 156401[106:MRR:843.0,156399.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.35 156404[106:Res:53.1,156401.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.35 156409[107:Spt:156404.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 156411[107:Res:156409.0,61.1] always3(s25) || -> . % 76.16/76.35 156412[107:SSi:156411.0,78178.0,78181.0,137747.0,155882.0,156399.0] || -> . % 76.16/76.35 156413[107:Spt:156412.0,156404.0,156409.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.35 156414[107:Spt:156412.0,156404.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 156418[107:Res:156414.0,61.1] always3(s26) || -> . % 76.16/76.35 156419[107:SSi:156418.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.35 156420[105:Spt:156419.0,155881.0,155882.0] || until2p7(s25)*+ -> . % 76.16/76.35 156421[105:Spt:156419.0,155881.1] || -> node4(s24)*. % 76.16/76.35 156423[105:MRR:846.0,156421.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.35 156426[105:Res:53.1,156423.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.35 156428[106:Spt:156426.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 156430[106:Res:156428.0,61.1] always3(s24) || -> . % 76.16/76.35 156431[106:SSi:156430.0,78173.0,78177.0,137746.0,155880.0,156421.0] || -> . % 76.16/76.35 156432[106:Spt:156431.0,156426.0,156428.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.35 156433[106:Spt:156431.0,156426.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 156437[106:Res:156433.0,61.1] always3(s25) || -> . % 76.16/76.35 156438[106:SSi:156437.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.35 156439[104:Spt:156438.0,155879.0,155880.0] || until2p7(s24)*+ -> . % 76.16/76.35 156440[104:Spt:156438.0,155879.1] || -> node4(s23)*. % 76.16/76.35 156442[104:MRR:849.0,156440.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.35 156445[104:Res:53.1,156442.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.35 156447[105:Spt:156445.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 156449[105:Res:156447.0,61.1] always3(s23) || -> . % 76.16/76.35 156450[105:SSi:156449.0,78169.0,78172.0,137745.0,155878.0,156440.0] || -> . % 76.16/76.35 156451[105:Spt:156450.0,156445.0,156447.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.35 156452[105:Spt:156450.0,156445.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 156456[105:Res:156452.0,61.1] always3(s24) || -> . % 76.16/76.35 156457[105:SSi:156456.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.35 156458[103:Spt:156457.0,155877.0,155878.0] || until2p7(s23)*+ -> . % 76.16/76.35 156459[103:Spt:156457.0,155877.1] || -> node4(s22)*. % 76.16/76.35 156461[103:MRR:852.0,156459.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.35 156464[103:Res:53.1,156461.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.35 156466[104:Spt:156464.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 156468[104:Res:156466.0,61.1] always3(s22) || -> . % 76.16/76.35 156469[104:SSi:156468.0,78164.0,78168.0,137744.0,155876.0,156459.0] || -> . % 76.16/76.35 156470[104:Spt:156469.0,156464.0,156466.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.35 156471[104:Spt:156469.0,156464.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 156475[104:Res:156471.0,61.1] always3(s23) || -> . % 76.16/76.35 156476[104:SSi:156475.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.35 156477[102:Spt:156476.0,155875.0,155876.0] || until2p7(s22)*+ -> . % 76.16/76.35 156478[102:Spt:156476.0,155875.1] || -> node4(s21)*. % 76.16/76.35 156480[102:MRR:855.0,156478.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.35 156483[102:Res:53.1,156480.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.35 156488[103:Spt:156483.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 156490[103:Res:156488.0,61.1] always3(s21) || -> . % 76.16/76.35 156491[103:SSi:156490.0,78160.0,78163.0,137743.0,155874.0,156478.0] || -> . % 76.16/76.35 156492[103:Spt:156491.0,156483.0,156488.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.35 156493[103:Spt:156491.0,156483.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 156497[103:Res:156493.0,61.1] always3(s22) || -> . % 76.16/76.35 156498[103:SSi:156497.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.35 156499[101:Spt:156498.0,155873.0,155874.0] || until2p7(s21)*+ -> . % 76.16/76.35 156500[101:Spt:156498.0,155873.1] || -> node4(s20)*. % 76.16/76.35 156502[101:MRR:858.0,156500.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.35 156505[101:Res:53.1,156502.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.35 156507[102:Spt:156505.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 156509[102:Res:156507.0,61.1] always3(s20) || -> . % 76.16/76.35 156510[102:SSi:156509.0,78155.0,78159.0,137742.0,155872.0,156500.0] || -> . % 76.16/76.35 156511[102:Spt:156510.0,156505.0,156507.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.35 156512[102:Spt:156510.0,156505.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 156516[102:Res:156512.0,61.1] always3(s21) || -> . % 76.16/76.35 156517[102:SSi:156516.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.35 156518[100:Spt:156517.0,155871.0,155872.0] || until2p7(s20)*+ -> . % 76.16/76.35 156519[100:Spt:156517.0,155871.1] || -> node4(s19)*. % 76.16/76.35 156521[100:MRR:861.0,156519.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.35 156524[100:Res:53.1,156521.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.35 156526[101:Spt:156524.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 156528[101:Res:156526.0,61.1] always3(s19) || -> . % 76.16/76.35 156529[101:SSi:156528.0,78151.0,78154.0,137741.0,155870.0,156519.0] || -> . % 76.16/76.35 156530[101:Spt:156529.0,156524.0,156526.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.35 156531[101:Spt:156529.0,156524.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 156535[101:Res:156531.0,61.1] always3(s20) || -> . % 76.16/76.35 156536[101:SSi:156535.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.35 156537[99:Spt:156536.0,155869.0,155870.0] || until2p7(s19)*+ -> . % 76.16/76.35 156538[99:Spt:156536.0,155869.1] || -> node4(s18)*. % 76.16/76.35 156540[99:MRR:864.0,156538.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.35 156543[99:Res:53.1,156540.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.35 156545[100:Spt:156543.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 156547[100:Res:156545.0,61.1] always3(s18) || -> . % 76.16/76.35 156548[100:SSi:156547.0,78146.0,78150.0,137740.0,155868.0,156538.0] || -> . % 76.16/76.35 156549[100:Spt:156548.0,156543.0,156545.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.35 156550[100:Spt:156548.0,156543.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 156554[100:Res:156550.0,61.1] always3(s19) || -> . % 76.16/76.35 156555[100:SSi:156554.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.35 156556[98:Spt:156555.0,155867.0,155868.0] || until2p7(s18)*+ -> . % 76.16/76.35 156557[98:Spt:156555.0,155867.1] || -> node4(s17)*. % 76.16/76.35 156559[98:MRR:867.0,156557.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.35 156562[98:Res:53.1,156559.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.35 156567[99:Spt:156562.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 156569[99:Res:156567.0,61.1] always3(s17) || -> . % 76.16/76.35 156570[99:SSi:156569.0,78142.0,78145.0,137739.0,155866.0,156557.0] || -> . % 76.16/76.35 156571[99:Spt:156570.0,156562.0,156567.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.35 156572[99:Spt:156570.0,156562.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 156576[99:Res:156572.0,61.1] always3(s18) || -> . % 76.16/76.35 156577[99:SSi:156576.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.35 156578[97:Spt:156577.0,155865.0,155866.0] || until2p7(s17)*+ -> . % 76.16/76.35 156579[97:Spt:156577.0,155865.1] || -> node4(s16)*. % 76.16/76.35 156581[97:MRR:870.0,156579.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.35 156584[97:Res:53.1,156581.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.35 156586[98:Spt:156584.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 156588[98:Res:156586.0,61.1] always3(s16) || -> . % 76.16/76.35 156589[98:SSi:156588.0,78137.0,78141.0,137738.0,155864.0,156579.0] || -> . % 76.16/76.35 156590[98:Spt:156589.0,156584.0,156586.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.35 156591[98:Spt:156589.0,156584.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 156595[98:Res:156591.0,61.1] always3(s17) || -> . % 76.16/76.35 156596[98:SSi:156595.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.35 156597[96:Spt:156596.0,155863.0,155864.0] || until2p7(s16)*+ -> . % 76.16/76.35 156598[96:Spt:156596.0,155863.1] || -> node4(s15)*. % 76.16/76.35 156600[96:MRR:873.0,156598.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.35 156603[96:Res:53.1,156600.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.35 156605[97:Spt:156603.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 156607[97:Res:156605.0,61.1] always3(s15) || -> . % 76.16/76.35 156608[97:SSi:156607.0,78133.0,78136.0,137737.0,155862.0,156598.0] || -> . % 76.16/76.35 156609[97:Spt:156608.0,156603.0,156605.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.35 156610[97:Spt:156608.0,156603.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 156614[97:Res:156610.0,61.1] always3(s16) || -> . % 76.16/76.35 156615[97:SSi:156614.0,78137.0,78141.0,137738.0] || -> . % 76.16/76.35 156616[95:Spt:156615.0,155861.0,155862.0] || until2p7(s15)*+ -> . % 76.16/76.35 156617[95:Spt:156615.0,155861.1] || -> node4(s14)*. % 76.16/76.35 156619[95:MRR:876.0,156617.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.35 156622[95:Res:53.1,156619.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.35 156624[96:Spt:156622.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.35 156626[96:Res:156624.0,61.1] always3(s14) || -> . % 76.16/76.35 156627[96:SSi:156626.0,78128.0,78132.0,137736.0,155860.0,156617.0] || -> . % 76.16/76.35 156628[96:Spt:156627.0,156622.0,156624.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.35 156629[96:Spt:156627.0,156622.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 156633[96:Res:156629.0,61.1] always3(s15) || -> . % 76.16/76.35 156634[96:SSi:156633.0,78133.0,78136.0,137737.0] || -> . % 76.16/76.35 156635[94:Spt:156634.0,155859.0,155860.0] || until2p7(s14)*+ -> . % 76.16/76.35 156636[94:Spt:156634.0,155859.1] || -> node4(s13)*. % 76.16/76.35 156638[94:MRR:879.0,156636.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.35 156641[94:Res:53.1,156638.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.35 156646[95:Spt:156641.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.35 156648[95:Res:156646.0,61.1] always3(s13) || -> . % 76.16/76.35 156649[95:SSi:156648.0,78124.0,78127.0,137735.0,155858.0,156636.0] || -> . % 76.16/76.35 156650[95:Spt:156649.0,156641.0,156646.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.35 156651[95:Spt:156649.0,156641.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.35 156655[95:Res:156651.0,61.1] always3(s14) || -> . % 76.16/76.35 156656[95:SSi:156655.0,78128.0,78132.0,137736.0] || -> . % 76.16/76.35 156657[93:Spt:156656.0,155857.0,155858.0] || until2p7(s13)*+ -> . % 76.16/76.35 156658[93:Spt:156656.0,155857.1] || -> node4(s12)*. % 76.16/76.35 156660[93:MRR:882.0,156658.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.35 156663[93:Res:53.1,156660.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.35 156665[93:MRR:156663.0,155847.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.35 156667[93:Res:156665.0,61.1] always3(s13) || -> . % 76.16/76.35 156668[93:SSi:156667.0,78124.0,78127.0,137735.0] || -> . % 76.16/76.35 156669[91:Spt:156668.0,155707.0,155710.0] || trans(s49,s12)*+ -> . % 76.16/76.35 156670[91:Spt:156668.0,155707.1,155707.2,155707.3,155707.4,155707.5,155707.6,155707.7,155707.8] || -> trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.35 156672[91:MRR:155709.1,156669.0] xuntil6(s49) || -> trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.35 156673[92:Spt:156670.0] || -> trans(s49,s11)*. % 76.16/76.35 156674[92:Res:156673.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s11)*. % 76.16/76.35 156676[92:Res:156673.0,60.0] || -> node2(s49,s11)*. % 76.16/76.35 156677[92:SSi:156674.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s11)*. % 76.16/76.35 156678[92:Res:156676.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)*. % 76.16/76.35 156803[92:SoR:156678.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)*. % 76.16/76.35 156805[92:SoR:156803.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)* xuntil6(s49). % 76.16/76.35 156806[92:SSi:156805.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s11,c_busy)* xuntil6(s49). % 76.16/76.35 156807[93:Spt:156806.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.35 156809[93:Res:156807.0,61.1] always3(s11) || -> . % 76.16/76.35 156810[93:SSi:156809.0,78115.0,78118.0,137733.0] || -> . % 76.16/76.35 156811[93:Spt:156810.0,156806.1,156807.0] || m_main_v_state(s11,c_busy)*+ -> . % 76.16/76.35 156812[93:Spt:156810.0,156806.0,156806.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.35 156816[93:MRR:156803.2,156811.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.35 156817[93:Res:53.1,156812.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.35 156819[93:MRR:156817.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.35 156820[93:MRR:156677.0,156819.0] || -> until2p7(s11)*. % 76.16/76.35 156821[93:MRR:207.0,156820.0] || -> until2p7(s12)* node4(s11). % 76.16/76.35 156822[94:Spt:156821.0] || -> until2p7(s12)*. % 76.16/76.35 156823[94:MRR:208.0,156822.0] || -> until2p7(s13)* node4(s12). % 76.16/76.35 156824[95:Spt:156823.0] || -> until2p7(s13)*. % 76.16/76.35 156825[95:MRR:209.0,156824.0] || -> until2p7(s14)* node4(s13). % 76.16/76.35 156826[96:Spt:156825.0] || -> until2p7(s14)*. % 76.16/76.35 156827[96:MRR:210.0,156826.0] || -> until2p7(s15)* node4(s14). % 76.16/76.35 156828[97:Spt:156827.0] || -> until2p7(s15)*. % 76.16/76.35 156829[97:MRR:211.0,156828.0] || -> until2p7(s16)* node4(s15). % 76.16/76.35 156830[98:Spt:156829.0] || -> until2p7(s16)*. % 76.16/76.35 156831[98:MRR:212.0,156830.0] || -> until2p7(s17)* node4(s16). % 76.16/76.35 156832[99:Spt:156831.0] || -> until2p7(s17)*. % 76.16/76.35 156833[99:MRR:213.0,156832.0] || -> until2p7(s18)* node4(s17). % 76.16/76.35 156834[100:Spt:156833.0] || -> until2p7(s18)*. % 76.16/76.35 156835[100:MRR:214.0,156834.0] || -> until2p7(s19)* node4(s18). % 76.16/76.35 156836[101:Spt:156835.0] || -> until2p7(s19)*. % 76.16/76.35 156837[101:MRR:215.0,156836.0] || -> until2p7(s20)* node4(s19). % 76.16/76.35 156838[102:Spt:156837.0] || -> until2p7(s20)*. % 76.16/76.35 156839[102:MRR:216.0,156838.0] || -> until2p7(s21)* node4(s20). % 76.16/76.35 156840[103:Spt:156839.0] || -> until2p7(s21)*. % 76.16/76.35 156841[103:MRR:217.0,156840.0] || -> until2p7(s22)* node4(s21). % 76.16/76.35 156842[104:Spt:156841.0] || -> until2p7(s22)*. % 76.16/76.35 156843[104:MRR:218.0,156842.0] || -> until2p7(s23)* node4(s22). % 76.16/76.35 156844[105:Spt:156843.0] || -> until2p7(s23)*. % 76.16/76.35 156845[105:MRR:219.0,156844.0] || -> until2p7(s24)* node4(s23). % 76.16/76.35 156846[106:Spt:156845.0] || -> until2p7(s24)*. % 76.16/76.35 156847[106:MRR:220.0,156846.0] || -> until2p7(s25)* node4(s24). % 76.16/76.35 156848[107:Spt:156847.0] || -> until2p7(s25)*. % 76.16/76.35 156849[107:MRR:221.0,156848.0] || -> until2p7(s26)* node4(s25). % 76.16/76.35 156850[108:Spt:156849.0] || -> until2p7(s26)*. % 76.16/76.35 156851[108:MRR:222.0,156850.0] || -> until2p7(s27)* node4(s26). % 76.16/76.35 156852[109:Spt:156851.0] || -> until2p7(s27)*. % 76.16/76.35 156853[109:MRR:223.0,156852.0] || -> until2p7(s28)* node4(s27). % 76.16/76.35 156854[110:Spt:156853.0] || -> until2p7(s28)*. % 76.16/76.35 156855[110:MRR:224.0,156854.0] || -> until2p7(s29)* node4(s28). % 76.16/76.35 156856[111:Spt:156855.0] || -> until2p7(s29)*. % 76.16/76.35 156857[111:MRR:225.0,156856.0] || -> until2p7(s30)* node4(s29). % 76.16/76.35 156858[112:Spt:156857.0] || -> until2p7(s30)*. % 76.16/76.35 156859[112:MRR:226.0,156858.0] || -> until2p7(s31)* node4(s30). % 76.16/76.35 156860[113:Spt:156859.0] || -> until2p7(s31)*. % 76.16/76.35 156861[113:MRR:227.0,156860.0] || -> until2p7(s32)* node4(s31). % 76.16/76.35 156862[114:Spt:156861.0] || -> until2p7(s32)*. % 76.16/76.35 156863[114:MRR:228.0,156862.0] || -> until2p7(s33)* node4(s32). % 76.16/76.35 156864[115:Spt:156863.0] || -> until2p7(s33)*. % 76.16/76.35 156865[115:MRR:229.0,156864.0] || -> until2p7(s34)* node4(s33). % 76.16/76.35 156866[116:Spt:156865.0] || -> until2p7(s34)*. % 76.16/76.35 156867[116:MRR:230.0,156866.0] || -> until2p7(s35)* node4(s34). % 76.16/76.35 156868[117:Spt:156867.0] || -> until2p7(s35)*. % 76.16/76.35 156869[117:MRR:231.0,156868.0] || -> until2p7(s36)* node4(s35). % 76.16/76.35 156870[118:Spt:156869.0] || -> until2p7(s36)*. % 76.16/76.35 156871[118:MRR:232.0,156870.0] || -> until2p7(s37)* node4(s36). % 76.16/76.35 156872[119:Spt:156871.0] || -> until2p7(s37)*. % 76.16/76.35 156873[119:MRR:235.0,156872.0] || -> until2p7(s38)* node4(s37). % 76.16/76.35 156874[120:Spt:156873.0] || -> until2p7(s38)*. % 76.16/76.35 156875[120:MRR:236.0,156874.0] || -> until2p7(s39)* node4(s38). % 76.16/76.35 156876[121:Spt:156875.0] || -> until2p7(s39)*. % 76.16/76.35 156877[121:MRR:237.0,156876.0] || -> until2p7(s40)* node4(s39). % 76.16/76.35 156878[122:Spt:156877.0] || -> until2p7(s40)*. % 76.16/76.35 156879[122:MRR:238.0,156878.0] || -> until2p7(s41)* node4(s40). % 76.16/76.35 156880[123:Spt:156879.0] || -> until2p7(s41)*. % 76.16/76.35 156881[123:MRR:239.0,156880.0] || -> until2p7(s42)* node4(s41). % 76.16/76.35 156882[124:Spt:156881.0] || -> until2p7(s42)*. % 76.16/76.35 156883[124:MRR:240.0,156882.0] || -> until2p7(s43)* node4(s42). % 76.16/76.35 156884[125:Spt:156883.0] || -> until2p7(s43)*. % 76.16/76.35 156885[125:MRR:241.0,156884.0] || -> until2p7(s44)* node4(s43). % 76.16/76.35 156886[126:Spt:156885.0] || -> until2p7(s44)*. % 76.16/76.35 156887[126:MRR:539.0,156886.0] || -> until2p7(s45)* node4(s44). % 76.16/76.35 156888[127:Spt:156887.0] || -> until2p7(s45)*. % 76.16/76.35 156889[127:MRR:544.0,156888.0] || -> until2p7(s46)* node4(s45). % 76.16/76.35 156890[128:Spt:156889.0] || -> until2p7(s46)*. % 76.16/76.35 156891[128:MRR:549.0,156890.0] || -> until2p7(s47)* node4(s46). % 76.16/76.35 156892[129:Spt:156891.0] || -> until2p7(s47)*. % 76.16/76.35 156893[129:MRR:554.0,156892.0] || -> until2p7(s48)* node4(s47). % 76.16/76.35 156894[130:Spt:156893.0] || -> until2p7(s48)*. % 76.16/76.35 156895[130:MRR:559.0,156894.0] || -> until2p7(s49)* node4(s48). % 76.16/76.35 156896[131:Spt:156895.0] || -> until2p7(s49)*. % 76.16/76.35 156897[131:MRR:194.0,156896.0] || -> node4(s49)*. % 76.16/76.35 156898[131:MRR:156816.0,156897.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.35 156902[131:Res:53.1,156898.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.35 156904[131:MRR:156902.0,78381.0] || -> . % 76.16/76.35 156905[131:Spt:156904.0,156895.0,156896.0] || until2p7(s49)*+ -> . % 76.16/76.35 156906[131:Spt:156904.0,156895.1] || -> node4(s48)*. % 76.16/76.35 156907[131:MRR:78384.0,156906.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.35 156910[131:Res:53.1,156907.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 156913[131:Res:156910.0,61.1] always3(s48) || -> . % 76.16/76.35 156914[131:SSi:156913.0,78281.0,78387.0,137770.0,156894.0,156906.0] || -> . % 76.16/76.35 156915[130:Spt:156914.0,156893.0,156894.0] || until2p7(s48)*+ -> . % 76.16/76.35 156916[130:Spt:156914.0,156893.1] || -> node4(s47)*. % 76.16/76.35 156918[130:MRR:777.0,156916.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.35 156930[130:Res:53.1,156918.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.35 156932[131:Spt:156930.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 156934[131:Res:156932.0,61.1] always3(s47) || -> . % 76.16/76.35 156935[131:SSi:156934.0,78277.0,78280.0,137769.0,156892.0,156916.0] || -> . % 76.16/76.35 156936[131:Spt:156935.0,156930.0,156932.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.35 156937[131:Spt:156935.0,156930.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 156941[131:Res:156937.0,61.1] always3(s48) || -> . % 76.16/76.35 156942[131:SSi:156941.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.35 156943[129:Spt:156942.0,156891.0,156892.0] || until2p7(s47)*+ -> . % 76.16/76.35 156944[129:Spt:156942.0,156891.1] || -> node4(s46)*. % 76.16/76.35 156946[129:MRR:780.0,156944.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.35 156953[129:Res:53.1,156946.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.35 156958[130:Spt:156953.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 156960[130:Res:156958.0,61.1] always3(s46) || -> . % 76.16/76.35 156961[130:SSi:156960.0,78272.0,78276.0,137768.0,156890.0,156944.0] || -> . % 76.16/76.35 156962[130:Spt:156961.0,156953.0,156958.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.35 156963[130:Spt:156961.0,156953.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 156967[130:Res:156963.0,61.1] always3(s47) || -> . % 76.16/76.35 156968[130:SSi:156967.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.35 156969[128:Spt:156968.0,156889.0,156890.0] || until2p7(s46)*+ -> . % 76.16/76.35 156970[128:Spt:156968.0,156889.1] || -> node4(s45)*. % 76.16/76.35 156972[128:MRR:783.0,156970.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.35 156975[128:Res:53.1,156972.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.35 156977[129:Spt:156975.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 156979[129:Res:156977.0,61.1] always3(s45) || -> . % 76.16/76.35 156980[129:SSi:156979.0,78268.0,78271.0,137767.0,156888.0,156970.0] || -> . % 76.16/76.35 156981[129:Spt:156980.0,156975.0,156977.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.35 156982[129:Spt:156980.0,156975.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 156986[129:Res:156982.0,61.1] always3(s46) || -> . % 76.16/76.35 156987[129:SSi:156986.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.35 156988[127:Spt:156987.0,156887.0,156888.0] || until2p7(s45)*+ -> . % 76.16/76.35 156989[127:Spt:156987.0,156887.1] || -> node4(s44)*. % 76.16/76.35 156991[127:MRR:786.0,156989.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.35 156994[127:Res:53.1,156991.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.35 156996[128:Spt:156994.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 156998[128:Res:156996.0,61.1] always3(s44) || -> . % 76.16/76.35 156999[128:SSi:156998.0,78263.0,78267.0,137766.0,156886.0,156989.0] || -> . % 76.16/76.35 157000[128:Spt:156999.0,156994.0,156996.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.35 157001[128:Spt:156999.0,156994.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 157005[128:Res:157001.0,61.1] always3(s45) || -> . % 76.16/76.35 157006[128:SSi:157005.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.35 157007[126:Spt:157006.0,156885.0,156886.0] || until2p7(s44)*+ -> . % 76.16/76.35 157008[126:Spt:157006.0,156885.1] || -> node4(s43)*. % 76.16/76.35 157010[126:MRR:789.0,157008.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.35 157013[126:Res:53.1,157010.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.35 157015[127:Spt:157013.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 157017[127:Res:157015.0,61.1] always3(s43) || -> . % 76.16/76.35 157018[127:SSi:157017.0,78259.0,78262.0,137765.0,156884.0,157008.0] || -> . % 76.16/76.35 157019[127:Spt:157018.0,157013.0,157015.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.35 157020[127:Spt:157018.0,157013.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 157024[127:Res:157020.0,61.1] always3(s44) || -> . % 76.16/76.35 157025[127:SSi:157024.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.35 157026[125:Spt:157025.0,156883.0,156884.0] || until2p7(s43)*+ -> . % 76.16/76.35 157027[125:Spt:157025.0,156883.1] || -> node4(s42)*. % 76.16/76.35 157029[125:MRR:792.0,157027.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.35 157032[125:Res:53.1,157029.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.35 157037[126:Spt:157032.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 157039[126:Res:157037.0,61.1] always3(s42) || -> . % 76.16/76.35 157040[126:SSi:157039.0,78254.0,78258.0,137764.0,156882.0,157027.0] || -> . % 76.16/76.35 157041[126:Spt:157040.0,157032.0,157037.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.35 157042[126:Spt:157040.0,157032.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 157046[126:Res:157042.0,61.1] always3(s43) || -> . % 76.16/76.35 157047[126:SSi:157046.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.35 157048[124:Spt:157047.0,156881.0,156882.0] || until2p7(s42)*+ -> . % 76.16/76.35 157049[124:Spt:157047.0,156881.1] || -> node4(s41)*. % 76.16/76.35 157051[124:MRR:795.0,157049.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.35 157054[124:Res:53.1,157051.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.35 157056[125:Spt:157054.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 157058[125:Res:157056.0,61.1] always3(s41) || -> . % 76.16/76.35 157059[125:SSi:157058.0,78250.0,78253.0,137763.0,156880.0,157049.0] || -> . % 76.16/76.35 157060[125:Spt:157059.0,157054.0,157056.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.35 157061[125:Spt:157059.0,157054.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 157065[125:Res:157061.0,61.1] always3(s42) || -> . % 76.16/76.35 157066[125:SSi:157065.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.35 157067[123:Spt:157066.0,156879.0,156880.0] || until2p7(s41)*+ -> . % 76.16/76.35 157068[123:Spt:157066.0,156879.1] || -> node4(s40)*. % 76.16/76.35 157070[123:MRR:798.0,157068.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.35 157073[123:Res:53.1,157070.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.35 157075[124:Spt:157073.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 157077[124:Res:157075.0,61.1] always3(s40) || -> . % 76.16/76.35 157078[124:SSi:157077.0,78245.0,78249.0,137762.0,156878.0,157068.0] || -> . % 76.16/76.35 157079[124:Spt:157078.0,157073.0,157075.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.35 157080[124:Spt:157078.0,157073.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 157084[124:Res:157080.0,61.1] always3(s41) || -> . % 76.16/76.35 157085[124:SSi:157084.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.35 157086[122:Spt:157085.0,156877.0,156878.0] || until2p7(s40)*+ -> . % 76.16/76.35 157087[122:Spt:157085.0,156877.1] || -> node4(s39)*. % 76.16/76.35 157089[122:MRR:801.0,157087.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.35 157092[122:Res:53.1,157089.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.35 157094[123:Spt:157092.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 157096[123:Res:157094.0,61.1] always3(s39) || -> . % 76.16/76.35 157097[123:SSi:157096.0,78241.0,78244.0,137761.0,156876.0,157087.0] || -> . % 76.16/76.35 157098[123:Spt:157097.0,157092.0,157094.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.35 157099[123:Spt:157097.0,157092.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 157103[123:Res:157099.0,61.1] always3(s40) || -> . % 76.16/76.35 157104[123:SSi:157103.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.35 157105[121:Spt:157104.0,156875.0,156876.0] || until2p7(s39)*+ -> . % 76.16/76.35 157106[121:Spt:157104.0,156875.1] || -> node4(s38)*. % 76.16/76.35 157108[121:MRR:804.0,157106.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.35 157111[121:Res:53.1,157108.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.35 157116[122:Spt:157111.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 157118[122:Res:157116.0,61.1] always3(s38) || -> . % 76.16/76.35 157119[122:SSi:157118.0,78236.0,78240.0,137760.0,156874.0,157106.0] || -> . % 76.16/76.35 157120[122:Spt:157119.0,157111.0,157116.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.35 157121[122:Spt:157119.0,157111.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 157125[122:Res:157121.0,61.1] always3(s39) || -> . % 76.16/76.35 157126[122:SSi:157125.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.35 157127[120:Spt:157126.0,156873.0,156874.0] || until2p7(s38)*+ -> . % 76.16/76.35 157128[120:Spt:157126.0,156873.1] || -> node4(s37)*. % 76.16/76.35 157130[120:MRR:807.0,157128.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.35 157133[120:Res:53.1,157130.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.35 157135[121:Spt:157133.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 157137[121:Res:157135.0,61.1] always3(s37) || -> . % 76.16/76.35 157138[121:SSi:157137.0,78232.0,78235.0,137759.0,156872.0,157128.0] || -> . % 76.16/76.35 157139[121:Spt:157138.0,157133.0,157135.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.35 157140[121:Spt:157138.0,157133.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 157144[121:Res:157140.0,61.1] always3(s38) || -> . % 76.16/76.35 157145[121:SSi:157144.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.35 157146[119:Spt:157145.0,156871.0,156872.0] || until2p7(s37)*+ -> . % 76.16/76.35 157147[119:Spt:157145.0,156871.1] || -> node4(s36)*. % 76.16/76.35 157149[119:MRR:810.0,157147.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.35 157152[119:Res:53.1,157149.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.35 157154[120:Spt:157152.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 157156[120:Res:157154.0,61.1] always3(s36) || -> . % 76.16/76.35 157157[120:SSi:157156.0,78227.0,78231.0,137758.0,156870.0,157147.0] || -> . % 76.16/76.35 157158[120:Spt:157157.0,157152.0,157154.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.35 157159[120:Spt:157157.0,157152.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 157163[120:Res:157159.0,61.1] always3(s37) || -> . % 76.16/76.35 157164[120:SSi:157163.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.35 157165[118:Spt:157164.0,156869.0,156870.0] || until2p7(s36)*+ -> . % 76.16/76.35 157166[118:Spt:157164.0,156869.1] || -> node4(s35)*. % 76.16/76.35 157168[118:MRR:813.0,157166.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.35 157171[118:Res:53.1,157168.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.35 157173[119:Spt:157171.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 157175[119:Res:157173.0,61.1] always3(s35) || -> . % 76.16/76.35 157176[119:SSi:157175.0,78223.0,78226.0,137757.0,156868.0,157166.0] || -> . % 76.16/76.35 157177[119:Spt:157176.0,157171.0,157173.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.35 157178[119:Spt:157176.0,157171.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 157182[119:Res:157178.0,61.1] always3(s36) || -> . % 76.16/76.35 157183[119:SSi:157182.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.35 157184[117:Spt:157183.0,156867.0,156868.0] || until2p7(s35)*+ -> . % 76.16/76.35 157185[117:Spt:157183.0,156867.1] || -> node4(s34)*. % 76.16/76.35 157187[117:MRR:816.0,157185.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.35 157190[117:Res:53.1,157187.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.35 157195[118:Spt:157190.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 157197[118:Res:157195.0,61.1] always3(s34) || -> . % 76.16/76.35 157198[118:SSi:157197.0,78218.0,78222.0,137756.0,156866.0,157185.0] || -> . % 76.16/76.35 157199[118:Spt:157198.0,157190.0,157195.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.35 157200[118:Spt:157198.0,157190.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 157204[118:Res:157200.0,61.1] always3(s35) || -> . % 76.16/76.35 157205[118:SSi:157204.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.35 157206[116:Spt:157205.0,156865.0,156866.0] || until2p7(s34)*+ -> . % 76.16/76.35 157207[116:Spt:157205.0,156865.1] || -> node4(s33)*. % 76.16/76.35 157209[116:MRR:819.0,157207.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.35 157212[116:Res:53.1,157209.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.35 157214[117:Spt:157212.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 157216[117:Res:157214.0,61.1] always3(s33) || -> . % 76.16/76.35 157217[117:SSi:157216.0,78214.0,78217.0,137755.0,156864.0,157207.0] || -> . % 76.16/76.35 157218[117:Spt:157217.0,157212.0,157214.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.35 157219[117:Spt:157217.0,157212.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 157223[117:Res:157219.0,61.1] always3(s34) || -> . % 76.16/76.35 157224[117:SSi:157223.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.35 157225[115:Spt:157224.0,156863.0,156864.0] || until2p7(s33)*+ -> . % 76.16/76.35 157226[115:Spt:157224.0,156863.1] || -> node4(s32)*. % 76.16/76.35 157228[115:MRR:822.0,157226.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.35 157231[115:Res:53.1,157228.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.35 157233[116:Spt:157231.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 157235[116:Res:157233.0,61.1] always3(s32) || -> . % 76.16/76.35 157236[116:SSi:157235.0,78209.0,78213.0,137754.0,156862.0,157226.0] || -> . % 76.16/76.35 157237[116:Spt:157236.0,157231.0,157233.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.35 157238[116:Spt:157236.0,157231.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 157242[116:Res:157238.0,61.1] always3(s33) || -> . % 76.16/76.35 157243[116:SSi:157242.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.35 157244[114:Spt:157243.0,156861.0,156862.0] || until2p7(s32)*+ -> . % 76.16/76.35 157245[114:Spt:157243.0,156861.1] || -> node4(s31)*. % 76.16/76.35 157247[114:MRR:825.0,157245.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.35 157250[114:Res:53.1,157247.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.35 157252[115:Spt:157250.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 157254[115:Res:157252.0,61.1] always3(s31) || -> . % 76.16/76.35 157255[115:SSi:157254.0,78205.0,78208.0,137753.0,156860.0,157245.0] || -> . % 76.16/76.35 157256[115:Spt:157255.0,157250.0,157252.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.35 157257[115:Spt:157255.0,157250.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 157261[115:Res:157257.0,61.1] always3(s32) || -> . % 76.16/76.35 157262[115:SSi:157261.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.35 157263[113:Spt:157262.0,156859.0,156860.0] || until2p7(s31)*+ -> . % 76.16/76.35 157264[113:Spt:157262.0,156859.1] || -> node4(s30)*. % 76.16/76.35 157266[113:MRR:828.0,157264.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.35 157269[113:Res:53.1,157266.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.35 157274[114:Spt:157269.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 157276[114:Res:157274.0,61.1] always3(s30) || -> . % 76.16/76.35 157277[114:SSi:157276.0,78200.0,78204.0,137752.0,156858.0,157264.0] || -> . % 76.16/76.35 157278[114:Spt:157277.0,157269.0,157274.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.35 157279[114:Spt:157277.0,157269.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 157283[114:Res:157279.0,61.1] always3(s31) || -> . % 76.16/76.35 157284[114:SSi:157283.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.35 157285[112:Spt:157284.0,156857.0,156858.0] || until2p7(s30)*+ -> . % 76.16/76.35 157286[112:Spt:157284.0,156857.1] || -> node4(s29)*. % 76.16/76.35 157288[112:MRR:831.0,157286.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.35 157291[112:Res:53.1,157288.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.35 157293[113:Spt:157291.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 157295[113:Res:157293.0,61.1] always3(s29) || -> . % 76.16/76.35 157296[113:SSi:157295.0,78196.0,78199.0,137751.0,156856.0,157286.0] || -> . % 76.16/76.35 157297[113:Spt:157296.0,157291.0,157293.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.35 157298[113:Spt:157296.0,157291.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 157302[113:Res:157298.0,61.1] always3(s30) || -> . % 76.16/76.35 157303[113:SSi:157302.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.35 157304[111:Spt:157303.0,156855.0,156856.0] || until2p7(s29)*+ -> . % 76.16/76.35 157305[111:Spt:157303.0,156855.1] || -> node4(s28)*. % 76.16/76.35 157307[111:MRR:834.0,157305.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.35 157310[111:Res:53.1,157307.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.35 157312[112:Spt:157310.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 157314[112:Res:157312.0,61.1] always3(s28) || -> . % 76.16/76.35 157315[112:SSi:157314.0,78191.0,78195.0,137750.0,156854.0,157305.0] || -> . % 76.16/76.35 157316[112:Spt:157315.0,157310.0,157312.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.35 157317[112:Spt:157315.0,157310.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 157321[112:Res:157317.0,61.1] always3(s29) || -> . % 76.16/76.35 157322[112:SSi:157321.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.35 157323[110:Spt:157322.0,156853.0,156854.0] || until2p7(s28)*+ -> . % 76.16/76.35 157324[110:Spt:157322.0,156853.1] || -> node4(s27)*. % 76.16/76.35 157326[110:MRR:837.0,157324.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.35 157329[110:Res:53.1,157326.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.35 157331[111:Spt:157329.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 157333[111:Res:157331.0,61.1] always3(s27) || -> . % 76.16/76.35 157334[111:SSi:157333.0,78187.0,78190.0,137749.0,156852.0,157324.0] || -> . % 76.16/76.35 157335[111:Spt:157334.0,157329.0,157331.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.35 157336[111:Spt:157334.0,157329.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 157340[111:Res:157336.0,61.1] always3(s28) || -> . % 76.16/76.35 157341[111:SSi:157340.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.35 157342[109:Spt:157341.0,156851.0,156852.0] || until2p7(s27)*+ -> . % 76.16/76.35 157343[109:Spt:157341.0,156851.1] || -> node4(s26)*. % 76.16/76.35 157345[109:MRR:840.0,157343.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.35 157348[109:Res:53.1,157345.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.35 157353[110:Spt:157348.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 157355[110:Res:157353.0,61.1] always3(s26) || -> . % 76.16/76.35 157356[110:SSi:157355.0,78182.0,78186.0,137748.0,156850.0,157343.0] || -> . % 76.16/76.35 157357[110:Spt:157356.0,157348.0,157353.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.35 157358[110:Spt:157356.0,157348.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 157362[110:Res:157358.0,61.1] always3(s27) || -> . % 76.16/76.35 157363[110:SSi:157362.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.35 157364[108:Spt:157363.0,156849.0,156850.0] || until2p7(s26)*+ -> . % 76.16/76.35 157365[108:Spt:157363.0,156849.1] || -> node4(s25)*. % 76.16/76.35 157367[108:MRR:843.0,157365.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.35 157370[108:Res:53.1,157367.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.35 157372[109:Spt:157370.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 157374[109:Res:157372.0,61.1] always3(s25) || -> . % 76.16/76.35 157375[109:SSi:157374.0,78178.0,78181.0,137747.0,156848.0,157365.0] || -> . % 76.16/76.35 157376[109:Spt:157375.0,157370.0,157372.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.35 157377[109:Spt:157375.0,157370.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 157381[109:Res:157377.0,61.1] always3(s26) || -> . % 76.16/76.35 157382[109:SSi:157381.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.35 157383[107:Spt:157382.0,156847.0,156848.0] || until2p7(s25)*+ -> . % 76.16/76.35 157384[107:Spt:157382.0,156847.1] || -> node4(s24)*. % 76.16/76.35 157386[107:MRR:846.0,157384.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.35 157389[107:Res:53.1,157386.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.35 157391[108:Spt:157389.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 157393[108:Res:157391.0,61.1] always3(s24) || -> . % 76.16/76.35 157394[108:SSi:157393.0,78173.0,78177.0,137746.0,156846.0,157384.0] || -> . % 76.16/76.35 157395[108:Spt:157394.0,157389.0,157391.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.35 157396[108:Spt:157394.0,157389.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 157400[108:Res:157396.0,61.1] always3(s25) || -> . % 76.16/76.35 157401[108:SSi:157400.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.35 157402[106:Spt:157401.0,156845.0,156846.0] || until2p7(s24)*+ -> . % 76.16/76.35 157403[106:Spt:157401.0,156845.1] || -> node4(s23)*. % 76.16/76.35 157405[106:MRR:849.0,157403.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.35 157408[106:Res:53.1,157405.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.35 157410[107:Spt:157408.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 157412[107:Res:157410.0,61.1] always3(s23) || -> . % 76.16/76.35 157413[107:SSi:157412.0,78169.0,78172.0,137745.0,156844.0,157403.0] || -> . % 76.16/76.35 157414[107:Spt:157413.0,157408.0,157410.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.35 157415[107:Spt:157413.0,157408.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 157419[107:Res:157415.0,61.1] always3(s24) || -> . % 76.16/76.35 157420[107:SSi:157419.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.35 157421[105:Spt:157420.0,156843.0,156844.0] || until2p7(s23)*+ -> . % 76.16/76.35 157422[105:Spt:157420.0,156843.1] || -> node4(s22)*. % 76.16/76.35 157424[105:MRR:852.0,157422.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.35 157427[105:Res:53.1,157424.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.35 157432[106:Spt:157427.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 157434[106:Res:157432.0,61.1] always3(s22) || -> . % 76.16/76.35 157435[106:SSi:157434.0,78164.0,78168.0,137744.0,156842.0,157422.0] || -> . % 76.16/76.35 157436[106:Spt:157435.0,157427.0,157432.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.35 157437[106:Spt:157435.0,157427.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 157441[106:Res:157437.0,61.1] always3(s23) || -> . % 76.16/76.35 157442[106:SSi:157441.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.35 157443[104:Spt:157442.0,156841.0,156842.0] || until2p7(s22)*+ -> . % 76.16/76.35 157444[104:Spt:157442.0,156841.1] || -> node4(s21)*. % 76.16/76.35 157446[104:MRR:855.0,157444.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.35 157449[104:Res:53.1,157446.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.35 157451[105:Spt:157449.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 157453[105:Res:157451.0,61.1] always3(s21) || -> . % 76.16/76.35 157454[105:SSi:157453.0,78160.0,78163.0,137743.0,156840.0,157444.0] || -> . % 76.16/76.35 157455[105:Spt:157454.0,157449.0,157451.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.35 157456[105:Spt:157454.0,157449.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 157460[105:Res:157456.0,61.1] always3(s22) || -> . % 76.16/76.35 157461[105:SSi:157460.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.35 157462[103:Spt:157461.0,156839.0,156840.0] || until2p7(s21)*+ -> . % 76.16/76.35 157463[103:Spt:157461.0,156839.1] || -> node4(s20)*. % 76.16/76.35 157465[103:MRR:858.0,157463.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.35 157468[103:Res:53.1,157465.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.35 157470[104:Spt:157468.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 157472[104:Res:157470.0,61.1] always3(s20) || -> . % 76.16/76.35 157473[104:SSi:157472.0,78155.0,78159.0,137742.0,156838.0,157463.0] || -> . % 76.16/76.35 157474[104:Spt:157473.0,157468.0,157470.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.35 157475[104:Spt:157473.0,157468.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 157479[104:Res:157475.0,61.1] always3(s21) || -> . % 76.16/76.35 157480[104:SSi:157479.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.35 157481[102:Spt:157480.0,156837.0,156838.0] || until2p7(s20)*+ -> . % 76.16/76.35 157482[102:Spt:157480.0,156837.1] || -> node4(s19)*. % 76.16/76.35 157484[102:MRR:861.0,157482.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.35 157487[102:Res:53.1,157484.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.35 157489[103:Spt:157487.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 157491[103:Res:157489.0,61.1] always3(s19) || -> . % 76.16/76.35 157492[103:SSi:157491.0,78151.0,78154.0,137741.0,156836.0,157482.0] || -> . % 76.16/76.35 157493[103:Spt:157492.0,157487.0,157489.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.35 157494[103:Spt:157492.0,157487.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 157498[103:Res:157494.0,61.1] always3(s20) || -> . % 76.16/76.35 157499[103:SSi:157498.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.35 157500[101:Spt:157499.0,156835.0,156836.0] || until2p7(s19)*+ -> . % 76.16/76.35 157501[101:Spt:157499.0,156835.1] || -> node4(s18)*. % 76.16/76.35 157503[101:MRR:864.0,157501.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.35 157506[101:Res:53.1,157503.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.35 157511[102:Spt:157506.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 157513[102:Res:157511.0,61.1] always3(s18) || -> . % 76.16/76.35 157514[102:SSi:157513.0,78146.0,78150.0,137740.0,156834.0,157501.0] || -> . % 76.16/76.35 157515[102:Spt:157514.0,157506.0,157511.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.35 157516[102:Spt:157514.0,157506.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 157520[102:Res:157516.0,61.1] always3(s19) || -> . % 76.16/76.35 157521[102:SSi:157520.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.35 157522[100:Spt:157521.0,156833.0,156834.0] || until2p7(s18)*+ -> . % 76.16/76.35 157523[100:Spt:157521.0,156833.1] || -> node4(s17)*. % 76.16/76.35 157525[100:MRR:867.0,157523.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.35 157528[100:Res:53.1,157525.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.35 157530[101:Spt:157528.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 157532[101:Res:157530.0,61.1] always3(s17) || -> . % 76.16/76.35 157533[101:SSi:157532.0,78142.0,78145.0,137739.0,156832.0,157523.0] || -> . % 76.16/76.35 157534[101:Spt:157533.0,157528.0,157530.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.35 157535[101:Spt:157533.0,157528.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 157539[101:Res:157535.0,61.1] always3(s18) || -> . % 76.16/76.35 157540[101:SSi:157539.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.35 157541[99:Spt:157540.0,156831.0,156832.0] || until2p7(s17)*+ -> . % 76.16/76.35 157542[99:Spt:157540.0,156831.1] || -> node4(s16)*. % 76.16/76.35 157544[99:MRR:870.0,157542.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.35 157547[99:Res:53.1,157544.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.35 157549[100:Spt:157547.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 157551[100:Res:157549.0,61.1] always3(s16) || -> . % 76.16/76.35 157552[100:SSi:157551.0,78137.0,78141.0,137738.0,156830.0,157542.0] || -> . % 76.16/76.35 157553[100:Spt:157552.0,157547.0,157549.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.35 157554[100:Spt:157552.0,157547.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 157558[100:Res:157554.0,61.1] always3(s17) || -> . % 76.16/76.35 157559[100:SSi:157558.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.35 157560[98:Spt:157559.0,156829.0,156830.0] || until2p7(s16)*+ -> . % 76.16/76.35 157561[98:Spt:157559.0,156829.1] || -> node4(s15)*. % 76.16/76.35 157563[98:MRR:873.0,157561.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.35 157566[98:Res:53.1,157563.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.35 157568[99:Spt:157566.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 157570[99:Res:157568.0,61.1] always3(s15) || -> . % 76.16/76.35 157571[99:SSi:157570.0,78133.0,78136.0,137737.0,156828.0,157561.0] || -> . % 76.16/76.35 157572[99:Spt:157571.0,157566.0,157568.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.35 157573[99:Spt:157571.0,157566.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 157577[99:Res:157573.0,61.1] always3(s16) || -> . % 76.16/76.35 157578[99:SSi:157577.0,78137.0,78141.0,137738.0] || -> . % 76.16/76.35 157579[97:Spt:157578.0,156827.0,156828.0] || until2p7(s15)*+ -> . % 76.16/76.35 157580[97:Spt:157578.0,156827.1] || -> node4(s14)*. % 76.16/76.35 157582[97:MRR:876.0,157580.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.35 157585[97:Res:53.1,157582.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.35 157590[98:Spt:157585.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.35 157592[98:Res:157590.0,61.1] always3(s14) || -> . % 76.16/76.35 157593[98:SSi:157592.0,78128.0,78132.0,137736.0,156826.0,157580.0] || -> . % 76.16/76.35 157594[98:Spt:157593.0,157585.0,157590.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.35 157595[98:Spt:157593.0,157585.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 157599[98:Res:157595.0,61.1] always3(s15) || -> . % 76.16/76.35 157600[98:SSi:157599.0,78133.0,78136.0,137737.0] || -> . % 76.16/76.35 157601[96:Spt:157600.0,156825.0,156826.0] || until2p7(s14)*+ -> . % 76.16/76.35 157602[96:Spt:157600.0,156825.1] || -> node4(s13)*. % 76.16/76.35 157604[96:MRR:879.0,157602.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.35 157607[96:Res:53.1,157604.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.35 157609[97:Spt:157607.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.35 157611[97:Res:157609.0,61.1] always3(s13) || -> . % 76.16/76.35 157612[97:SSi:157611.0,78124.0,78127.0,137735.0,156824.0,157602.0] || -> . % 76.16/76.35 157613[97:Spt:157612.0,157607.0,157609.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.35 157614[97:Spt:157612.0,157607.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.35 157618[97:Res:157614.0,61.1] always3(s14) || -> . % 76.16/76.35 157619[97:SSi:157618.0,78128.0,78132.0,137736.0] || -> . % 76.16/76.35 157620[95:Spt:157619.0,156823.0,156824.0] || until2p7(s13)*+ -> . % 76.16/76.35 157621[95:Spt:157619.0,156823.1] || -> node4(s12)*. % 76.16/76.35 157623[95:MRR:882.0,157621.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.35 157626[95:Res:53.1,157623.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.35 157628[96:Spt:157626.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.35 157630[96:Res:157628.0,61.1] always3(s12) || -> . % 76.16/76.35 157631[96:SSi:157630.0,78119.0,78123.0,137734.0,156822.0,157621.0] || -> . % 76.16/76.35 157632[96:Spt:157631.0,157626.0,157628.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.35 157633[96:Spt:157631.0,157626.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.35 157637[96:Res:157633.0,61.1] always3(s13) || -> . % 76.16/76.35 157638[96:SSi:157637.0,78124.0,78127.0,137735.0] || -> . % 76.16/76.35 157639[94:Spt:157638.0,156821.0,156822.0] || until2p7(s12)*+ -> . % 76.16/76.35 157640[94:Spt:157638.0,156821.1] || -> node4(s11)*. % 76.16/76.35 157642[94:MRR:885.0,157640.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.35 157645[94:Res:53.1,157642.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.35 157647[94:MRR:157645.0,156811.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.35 157649[94:Res:157647.0,61.1] always3(s12) || -> . % 76.16/76.35 157650[94:SSi:157649.0,78119.0,78123.0,137734.0] || -> . % 76.16/76.35 157651[92:Spt:157650.0,156670.0,156673.0] || trans(s49,s11)*+ -> . % 76.16/76.35 157652[92:Spt:157650.0,156670.1,156670.2,156670.3,156670.4,156670.5,156670.6,156670.7] || -> trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.35 157654[92:MRR:156672.1,157651.0] xuntil6(s49) || -> trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.35 157655[93:Spt:157652.0] || -> trans(s49,s10)*. % 76.16/76.35 157656[93:Res:157655.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s10)*. % 76.16/76.35 157658[93:Res:157655.0,60.0] || -> node2(s49,s10)*. % 76.16/76.35 157659[93:SSi:157656.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s10)*. % 76.16/76.35 157660[93:Res:157658.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)*. % 76.16/76.35 157792[93:SoR:157660.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)*. % 76.16/76.35 157794[93:SoR:157792.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)* xuntil6(s49). % 76.16/76.35 157795[93:SSi:157794.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s10,c_busy)* xuntil6(s49). % 76.16/76.35 157796[94:Spt:157795.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.35 157798[94:Res:157796.0,61.1] always3(s10) || -> . % 76.16/76.35 157799[94:SSi:157798.0,78110.0,78114.0,137732.0] || -> . % 76.16/76.35 157800[94:Spt:157799.0,157795.1,157796.0] || m_main_v_state(s10,c_busy)*+ -> . % 76.16/76.35 157801[94:Spt:157799.0,157795.0,157795.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.35 157805[94:MRR:157792.2,157800.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.35 157806[94:Res:53.1,157801.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.35 157808[94:MRR:157806.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.35 157809[94:MRR:157659.0,157808.0] || -> until2p7(s10)*. % 76.16/76.35 157810[94:MRR:206.0,157809.0] || -> until2p7(s11)* node4(s10). % 76.16/76.35 157811[95:Spt:157810.0] || -> until2p7(s11)*. % 76.16/76.35 157812[95:MRR:207.0,157811.0] || -> until2p7(s12)* node4(s11). % 76.16/76.35 157813[96:Spt:157812.0] || -> until2p7(s12)*. % 76.16/76.35 157814[96:MRR:208.0,157813.0] || -> until2p7(s13)* node4(s12). % 76.16/76.35 157815[97:Spt:157814.0] || -> until2p7(s13)*. % 76.16/76.35 157816[97:MRR:209.0,157815.0] || -> until2p7(s14)* node4(s13). % 76.16/76.35 157817[98:Spt:157816.0] || -> until2p7(s14)*. % 76.16/76.35 157818[98:MRR:210.0,157817.0] || -> until2p7(s15)* node4(s14). % 76.16/76.35 157819[99:Spt:157818.0] || -> until2p7(s15)*. % 76.16/76.35 157820[99:MRR:211.0,157819.0] || -> until2p7(s16)* node4(s15). % 76.16/76.35 157821[100:Spt:157820.0] || -> until2p7(s16)*. % 76.16/76.35 157822[100:MRR:212.0,157821.0] || -> until2p7(s17)* node4(s16). % 76.16/76.35 157823[101:Spt:157822.0] || -> until2p7(s17)*. % 76.16/76.35 157824[101:MRR:213.0,157823.0] || -> until2p7(s18)* node4(s17). % 76.16/76.35 157825[102:Spt:157824.0] || -> until2p7(s18)*. % 76.16/76.35 157826[102:MRR:214.0,157825.0] || -> until2p7(s19)* node4(s18). % 76.16/76.35 157827[103:Spt:157826.0] || -> until2p7(s19)*. % 76.16/76.35 157828[103:MRR:215.0,157827.0] || -> until2p7(s20)* node4(s19). % 76.16/76.35 157829[104:Spt:157828.0] || -> until2p7(s20)*. % 76.16/76.35 157830[104:MRR:216.0,157829.0] || -> until2p7(s21)* node4(s20). % 76.16/76.35 157831[105:Spt:157830.0] || -> until2p7(s21)*. % 76.16/76.35 157832[105:MRR:217.0,157831.0] || -> until2p7(s22)* node4(s21). % 76.16/76.35 157833[106:Spt:157832.0] || -> until2p7(s22)*. % 76.16/76.35 157834[106:MRR:218.0,157833.0] || -> until2p7(s23)* node4(s22). % 76.16/76.35 157835[107:Spt:157834.0] || -> until2p7(s23)*. % 76.16/76.35 157836[107:MRR:219.0,157835.0] || -> until2p7(s24)* node4(s23). % 76.16/76.35 157837[108:Spt:157836.0] || -> until2p7(s24)*. % 76.16/76.35 157838[108:MRR:220.0,157837.0] || -> until2p7(s25)* node4(s24). % 76.16/76.35 157839[109:Spt:157838.0] || -> until2p7(s25)*. % 76.16/76.35 157840[109:MRR:221.0,157839.0] || -> until2p7(s26)* node4(s25). % 76.16/76.35 157841[110:Spt:157840.0] || -> until2p7(s26)*. % 76.16/76.35 157842[110:MRR:222.0,157841.0] || -> until2p7(s27)* node4(s26). % 76.16/76.35 157843[111:Spt:157842.0] || -> until2p7(s27)*. % 76.16/76.35 157844[111:MRR:223.0,157843.0] || -> until2p7(s28)* node4(s27). % 76.16/76.35 157845[112:Spt:157844.0] || -> until2p7(s28)*. % 76.16/76.35 157846[112:MRR:224.0,157845.0] || -> until2p7(s29)* node4(s28). % 76.16/76.35 157847[113:Spt:157846.0] || -> until2p7(s29)*. % 76.16/76.35 157848[113:MRR:225.0,157847.0] || -> until2p7(s30)* node4(s29). % 76.16/76.35 157849[114:Spt:157848.0] || -> until2p7(s30)*. % 76.16/76.35 157850[114:MRR:226.0,157849.0] || -> until2p7(s31)* node4(s30). % 76.16/76.35 157851[115:Spt:157850.0] || -> until2p7(s31)*. % 76.16/76.35 157852[115:MRR:227.0,157851.0] || -> until2p7(s32)* node4(s31). % 76.16/76.35 157853[116:Spt:157852.0] || -> until2p7(s32)*. % 76.16/76.35 157854[116:MRR:228.0,157853.0] || -> until2p7(s33)* node4(s32). % 76.16/76.35 157855[117:Spt:157854.0] || -> until2p7(s33)*. % 76.16/76.35 157856[117:MRR:229.0,157855.0] || -> until2p7(s34)* node4(s33). % 76.16/76.35 157857[118:Spt:157856.0] || -> until2p7(s34)*. % 76.16/76.35 157858[118:MRR:230.0,157857.0] || -> until2p7(s35)* node4(s34). % 76.16/76.35 157859[119:Spt:157858.0] || -> until2p7(s35)*. % 76.16/76.35 157860[119:MRR:231.0,157859.0] || -> until2p7(s36)* node4(s35). % 76.16/76.35 157861[120:Spt:157860.0] || -> until2p7(s36)*. % 76.16/76.35 157862[120:MRR:232.0,157861.0] || -> until2p7(s37)* node4(s36). % 76.16/76.35 157863[121:Spt:157862.0] || -> until2p7(s37)*. % 76.16/76.35 157864[121:MRR:235.0,157863.0] || -> until2p7(s38)* node4(s37). % 76.16/76.35 157865[122:Spt:157864.0] || -> until2p7(s38)*. % 76.16/76.35 157866[122:MRR:236.0,157865.0] || -> until2p7(s39)* node4(s38). % 76.16/76.35 157867[123:Spt:157866.0] || -> until2p7(s39)*. % 76.16/76.35 157868[123:MRR:237.0,157867.0] || -> until2p7(s40)* node4(s39). % 76.16/76.35 157869[124:Spt:157868.0] || -> until2p7(s40)*. % 76.16/76.35 157870[124:MRR:238.0,157869.0] || -> until2p7(s41)* node4(s40). % 76.16/76.35 157871[125:Spt:157870.0] || -> until2p7(s41)*. % 76.16/76.35 157872[125:MRR:239.0,157871.0] || -> until2p7(s42)* node4(s41). % 76.16/76.35 157873[126:Spt:157872.0] || -> until2p7(s42)*. % 76.16/76.35 157874[126:MRR:240.0,157873.0] || -> until2p7(s43)* node4(s42). % 76.16/76.35 157875[127:Spt:157874.0] || -> until2p7(s43)*. % 76.16/76.35 157876[127:MRR:241.0,157875.0] || -> until2p7(s44)* node4(s43). % 76.16/76.35 157877[128:Spt:157876.0] || -> until2p7(s44)*. % 76.16/76.35 157878[128:MRR:539.0,157877.0] || -> until2p7(s45)* node4(s44). % 76.16/76.35 157879[129:Spt:157878.0] || -> until2p7(s45)*. % 76.16/76.35 157880[129:MRR:544.0,157879.0] || -> until2p7(s46)* node4(s45). % 76.16/76.35 157881[130:Spt:157880.0] || -> until2p7(s46)*. % 76.16/76.35 157882[130:MRR:549.0,157881.0] || -> until2p7(s47)* node4(s46). % 76.16/76.35 157883[131:Spt:157882.0] || -> until2p7(s47)*. % 76.16/76.35 157884[131:MRR:554.0,157883.0] || -> until2p7(s48)* node4(s47). % 76.16/76.35 157885[132:Spt:157884.0] || -> until2p7(s48)*. % 76.16/76.35 157886[132:MRR:559.0,157885.0] || -> until2p7(s49)* node4(s48). % 76.16/76.35 157887[133:Spt:157886.0] || -> until2p7(s49)*. % 76.16/76.35 157888[133:MRR:194.0,157887.0] || -> node4(s49)*. % 76.16/76.35 157889[133:MRR:157805.0,157888.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.35 157890[133:Res:53.1,157889.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.35 157892[133:MRR:157890.0,78381.0] || -> . % 76.16/76.35 157893[133:Spt:157892.0,157886.0,157887.0] || until2p7(s49)*+ -> . % 76.16/76.35 157894[133:Spt:157892.0,157886.1] || -> node4(s48)*. % 76.16/76.35 157895[133:MRR:78384.0,157894.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.35 157898[133:Res:53.1,157895.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 157901[133:Res:157898.0,61.1] always3(s48) || -> . % 76.16/76.35 157902[133:SSi:157901.0,78281.0,78387.0,137770.0,157885.0,157894.0] || -> . % 76.16/76.35 157903[132:Spt:157902.0,157884.0,157885.0] || until2p7(s48)*+ -> . % 76.16/76.35 157904[132:Spt:157902.0,157884.1] || -> node4(s47)*. % 76.16/76.35 157906[132:MRR:777.0,157904.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.35 157921[132:Res:53.1,157906.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.35 157923[133:Spt:157921.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 157925[133:Res:157923.0,61.1] always3(s47) || -> . % 76.16/76.35 157926[133:SSi:157925.0,78277.0,78280.0,137769.0,157883.0,157904.0] || -> . % 76.16/76.35 157927[133:Spt:157926.0,157921.0,157923.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.35 157928[133:Spt:157926.0,157921.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 157932[133:Res:157928.0,61.1] always3(s48) || -> . % 76.16/76.35 157933[133:SSi:157932.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.35 157934[131:Spt:157933.0,157882.0,157883.0] || until2p7(s47)*+ -> . % 76.16/76.35 157935[131:Spt:157933.0,157882.1] || -> node4(s46)*. % 76.16/76.35 157937[131:MRR:780.0,157935.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.35 157947[131:Res:53.1,157937.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.35 157949[132:Spt:157947.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 157951[132:Res:157949.0,61.1] always3(s46) || -> . % 76.16/76.35 157952[132:SSi:157951.0,78272.0,78276.0,137768.0,157881.0,157935.0] || -> . % 76.16/76.35 157953[132:Spt:157952.0,157947.0,157949.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.35 157954[132:Spt:157952.0,157947.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 157958[132:Res:157954.0,61.1] always3(s47) || -> . % 76.16/76.35 157959[132:SSi:157958.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.35 157960[130:Spt:157959.0,157880.0,157881.0] || until2p7(s46)*+ -> . % 76.16/76.35 157961[130:Spt:157959.0,157880.1] || -> node4(s45)*. % 76.16/76.35 157963[130:MRR:783.0,157961.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.35 157966[130:Res:53.1,157963.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.35 157968[131:Spt:157966.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 157970[131:Res:157968.0,61.1] always3(s45) || -> . % 76.16/76.35 157971[131:SSi:157970.0,78268.0,78271.0,137767.0,157879.0,157961.0] || -> . % 76.16/76.35 157972[131:Spt:157971.0,157966.0,157968.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.35 157973[131:Spt:157971.0,157966.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 157977[131:Res:157973.0,61.1] always3(s46) || -> . % 76.16/76.35 157978[131:SSi:157977.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.35 157979[129:Spt:157978.0,157878.0,157879.0] || until2p7(s45)*+ -> . % 76.16/76.35 157980[129:Spt:157978.0,157878.1] || -> node4(s44)*. % 76.16/76.35 157982[129:MRR:786.0,157980.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.35 157985[129:Res:53.1,157982.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.35 157987[130:Spt:157985.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 157989[130:Res:157987.0,61.1] always3(s44) || -> . % 76.16/76.35 157990[130:SSi:157989.0,78263.0,78267.0,137766.0,157877.0,157980.0] || -> . % 76.16/76.35 157991[130:Spt:157990.0,157985.0,157987.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.35 157992[130:Spt:157990.0,157985.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 157996[130:Res:157992.0,61.1] always3(s45) || -> . % 76.16/76.35 157997[130:SSi:157996.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.35 157998[128:Spt:157997.0,157876.0,157877.0] || until2p7(s44)*+ -> . % 76.16/76.35 157999[128:Spt:157997.0,157876.1] || -> node4(s43)*. % 76.16/76.35 158001[128:MRR:789.0,157999.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.35 158004[128:Res:53.1,158001.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.35 158009[129:Spt:158004.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 158011[129:Res:158009.0,61.1] always3(s43) || -> . % 76.16/76.35 158012[129:SSi:158011.0,78259.0,78262.0,137765.0,157875.0,157999.0] || -> . % 76.16/76.35 158013[129:Spt:158012.0,158004.0,158009.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.35 158014[129:Spt:158012.0,158004.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 158018[129:Res:158014.0,61.1] always3(s44) || -> . % 76.16/76.35 158019[129:SSi:158018.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.35 158020[127:Spt:158019.0,157874.0,157875.0] || until2p7(s43)*+ -> . % 76.16/76.35 158021[127:Spt:158019.0,157874.1] || -> node4(s42)*. % 76.16/76.35 158023[127:MRR:792.0,158021.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.35 158026[127:Res:53.1,158023.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.35 158028[128:Spt:158026.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 158030[128:Res:158028.0,61.1] always3(s42) || -> . % 76.16/76.35 158031[128:SSi:158030.0,78254.0,78258.0,137764.0,157873.0,158021.0] || -> . % 76.16/76.35 158032[128:Spt:158031.0,158026.0,158028.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.35 158033[128:Spt:158031.0,158026.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 158037[128:Res:158033.0,61.1] always3(s43) || -> . % 76.16/76.35 158038[128:SSi:158037.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.35 158039[126:Spt:158038.0,157872.0,157873.0] || until2p7(s42)*+ -> . % 76.16/76.35 158040[126:Spt:158038.0,157872.1] || -> node4(s41)*. % 76.16/76.35 158042[126:MRR:795.0,158040.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.35 158045[126:Res:53.1,158042.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.35 158047[127:Spt:158045.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 158049[127:Res:158047.0,61.1] always3(s41) || -> . % 76.16/76.35 158050[127:SSi:158049.0,78250.0,78253.0,137763.0,157871.0,158040.0] || -> . % 76.16/76.35 158051[127:Spt:158050.0,158045.0,158047.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.35 158052[127:Spt:158050.0,158045.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 158056[127:Res:158052.0,61.1] always3(s42) || -> . % 76.16/76.35 158057[127:SSi:158056.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.35 158058[125:Spt:158057.0,157870.0,157871.0] || until2p7(s41)*+ -> . % 76.16/76.35 158059[125:Spt:158057.0,157870.1] || -> node4(s40)*. % 76.16/76.35 158061[125:MRR:798.0,158059.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.35 158064[125:Res:53.1,158061.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.35 158066[126:Spt:158064.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 158068[126:Res:158066.0,61.1] always3(s40) || -> . % 76.16/76.35 158069[126:SSi:158068.0,78245.0,78249.0,137762.0,157869.0,158059.0] || -> . % 76.16/76.35 158070[126:Spt:158069.0,158064.0,158066.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.35 158071[126:Spt:158069.0,158064.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 158075[126:Res:158071.0,61.1] always3(s41) || -> . % 76.16/76.35 158076[126:SSi:158075.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.35 158077[124:Spt:158076.0,157868.0,157869.0] || until2p7(s40)*+ -> . % 76.16/76.35 158078[124:Spt:158076.0,157868.1] || -> node4(s39)*. % 76.16/76.35 158080[124:MRR:801.0,158078.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.35 158083[124:Res:53.1,158080.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.35 158088[125:Spt:158083.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 158090[125:Res:158088.0,61.1] always3(s39) || -> . % 76.16/76.35 158091[125:SSi:158090.0,78241.0,78244.0,137761.0,157867.0,158078.0] || -> . % 76.16/76.35 158092[125:Spt:158091.0,158083.0,158088.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.35 158093[125:Spt:158091.0,158083.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 158097[125:Res:158093.0,61.1] always3(s40) || -> . % 76.16/76.35 158098[125:SSi:158097.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.35 158099[123:Spt:158098.0,157866.0,157867.0] || until2p7(s39)*+ -> . % 76.16/76.35 158100[123:Spt:158098.0,157866.1] || -> node4(s38)*. % 76.16/76.35 158102[123:MRR:804.0,158100.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.35 158105[123:Res:53.1,158102.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.35 158107[124:Spt:158105.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 158109[124:Res:158107.0,61.1] always3(s38) || -> . % 76.16/76.35 158110[124:SSi:158109.0,78236.0,78240.0,137760.0,157865.0,158100.0] || -> . % 76.16/76.35 158111[124:Spt:158110.0,158105.0,158107.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.35 158112[124:Spt:158110.0,158105.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 158116[124:Res:158112.0,61.1] always3(s39) || -> . % 76.16/76.35 158117[124:SSi:158116.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.35 158118[122:Spt:158117.0,157864.0,157865.0] || until2p7(s38)*+ -> . % 76.16/76.35 158119[122:Spt:158117.0,157864.1] || -> node4(s37)*. % 76.16/76.35 158121[122:MRR:807.0,158119.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.35 158124[122:Res:53.1,158121.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.35 158126[123:Spt:158124.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 158128[123:Res:158126.0,61.1] always3(s37) || -> . % 76.16/76.35 158129[123:SSi:158128.0,78232.0,78235.0,137759.0,157863.0,158119.0] || -> . % 76.16/76.35 158130[123:Spt:158129.0,158124.0,158126.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.35 158131[123:Spt:158129.0,158124.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 158135[123:Res:158131.0,61.1] always3(s38) || -> . % 76.16/76.35 158136[123:SSi:158135.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.35 158137[121:Spt:158136.0,157862.0,157863.0] || until2p7(s37)*+ -> . % 76.16/76.35 158138[121:Spt:158136.0,157862.1] || -> node4(s36)*. % 76.16/76.35 158140[121:MRR:810.0,158138.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.35 158143[121:Res:53.1,158140.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.35 158145[122:Spt:158143.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 158147[122:Res:158145.0,61.1] always3(s36) || -> . % 76.16/76.35 158148[122:SSi:158147.0,78227.0,78231.0,137758.0,157861.0,158138.0] || -> . % 76.16/76.35 158149[122:Spt:158148.0,158143.0,158145.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.35 158150[122:Spt:158148.0,158143.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 158154[122:Res:158150.0,61.1] always3(s37) || -> . % 76.16/76.35 158155[122:SSi:158154.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.35 158156[120:Spt:158155.0,157860.0,157861.0] || until2p7(s36)*+ -> . % 76.16/76.35 158157[120:Spt:158155.0,157860.1] || -> node4(s35)*. % 76.16/76.35 158159[120:MRR:813.0,158157.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.35 158162[120:Res:53.1,158159.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.35 158167[121:Spt:158162.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 158169[121:Res:158167.0,61.1] always3(s35) || -> . % 76.16/76.35 158170[121:SSi:158169.0,78223.0,78226.0,137757.0,157859.0,158157.0] || -> . % 76.16/76.35 158171[121:Spt:158170.0,158162.0,158167.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.35 158172[121:Spt:158170.0,158162.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 158176[121:Res:158172.0,61.1] always3(s36) || -> . % 76.16/76.35 158177[121:SSi:158176.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.35 158178[119:Spt:158177.0,157858.0,157859.0] || until2p7(s35)*+ -> . % 76.16/76.35 158179[119:Spt:158177.0,157858.1] || -> node4(s34)*. % 76.16/76.35 158181[119:MRR:816.0,158179.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.35 158184[119:Res:53.1,158181.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.35 158186[120:Spt:158184.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 158188[120:Res:158186.0,61.1] always3(s34) || -> . % 76.16/76.35 158189[120:SSi:158188.0,78218.0,78222.0,137756.0,157857.0,158179.0] || -> . % 76.16/76.35 158190[120:Spt:158189.0,158184.0,158186.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.35 158191[120:Spt:158189.0,158184.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 158195[120:Res:158191.0,61.1] always3(s35) || -> . % 76.16/76.35 158196[120:SSi:158195.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.35 158197[118:Spt:158196.0,157856.0,157857.0] || until2p7(s34)*+ -> . % 76.16/76.35 158198[118:Spt:158196.0,157856.1] || -> node4(s33)*. % 76.16/76.35 158200[118:MRR:819.0,158198.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.35 158203[118:Res:53.1,158200.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.35 158205[119:Spt:158203.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 158207[119:Res:158205.0,61.1] always3(s33) || -> . % 76.16/76.35 158208[119:SSi:158207.0,78214.0,78217.0,137755.0,157855.0,158198.0] || -> . % 76.16/76.35 158209[119:Spt:158208.0,158203.0,158205.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.35 158210[119:Spt:158208.0,158203.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 158214[119:Res:158210.0,61.1] always3(s34) || -> . % 76.16/76.35 158215[119:SSi:158214.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.35 158216[117:Spt:158215.0,157854.0,157855.0] || until2p7(s33)*+ -> . % 76.16/76.35 158217[117:Spt:158215.0,157854.1] || -> node4(s32)*. % 76.16/76.35 158219[117:MRR:822.0,158217.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.35 158222[117:Res:53.1,158219.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.35 158224[118:Spt:158222.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 158226[118:Res:158224.0,61.1] always3(s32) || -> . % 76.16/76.35 158227[118:SSi:158226.0,78209.0,78213.0,137754.0,157853.0,158217.0] || -> . % 76.16/76.35 158228[118:Spt:158227.0,158222.0,158224.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.35 158229[118:Spt:158227.0,158222.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 158233[118:Res:158229.0,61.1] always3(s33) || -> . % 76.16/76.35 158234[118:SSi:158233.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.35 158235[116:Spt:158234.0,157852.0,157853.0] || until2p7(s32)*+ -> . % 76.16/76.35 158236[116:Spt:158234.0,157852.1] || -> node4(s31)*. % 76.16/76.35 158238[116:MRR:825.0,158236.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.35 158241[116:Res:53.1,158238.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.35 158246[117:Spt:158241.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 158248[117:Res:158246.0,61.1] always3(s31) || -> . % 76.16/76.35 158249[117:SSi:158248.0,78205.0,78208.0,137753.0,157851.0,158236.0] || -> . % 76.16/76.35 158250[117:Spt:158249.0,158241.0,158246.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.35 158251[117:Spt:158249.0,158241.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 158255[117:Res:158251.0,61.1] always3(s32) || -> . % 76.16/76.35 158256[117:SSi:158255.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.35 158257[115:Spt:158256.0,157850.0,157851.0] || until2p7(s31)*+ -> . % 76.16/76.35 158258[115:Spt:158256.0,157850.1] || -> node4(s30)*. % 76.16/76.35 158260[115:MRR:828.0,158258.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.35 158263[115:Res:53.1,158260.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.35 158265[116:Spt:158263.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 158267[116:Res:158265.0,61.1] always3(s30) || -> . % 76.16/76.35 158268[116:SSi:158267.0,78200.0,78204.0,137752.0,157849.0,158258.0] || -> . % 76.16/76.35 158269[116:Spt:158268.0,158263.0,158265.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.35 158270[116:Spt:158268.0,158263.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 158274[116:Res:158270.0,61.1] always3(s31) || -> . % 76.16/76.35 158275[116:SSi:158274.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.35 158276[114:Spt:158275.0,157848.0,157849.0] || until2p7(s30)*+ -> . % 76.16/76.35 158277[114:Spt:158275.0,157848.1] || -> node4(s29)*. % 76.16/76.35 158279[114:MRR:831.0,158277.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.35 158282[114:Res:53.1,158279.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.35 158284[115:Spt:158282.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 158286[115:Res:158284.0,61.1] always3(s29) || -> . % 76.16/76.35 158287[115:SSi:158286.0,78196.0,78199.0,137751.0,157847.0,158277.0] || -> . % 76.16/76.35 158288[115:Spt:158287.0,158282.0,158284.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.35 158289[115:Spt:158287.0,158282.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 158293[115:Res:158289.0,61.1] always3(s30) || -> . % 76.16/76.35 158294[115:SSi:158293.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.35 158295[113:Spt:158294.0,157846.0,157847.0] || until2p7(s29)*+ -> . % 76.16/76.35 158296[113:Spt:158294.0,157846.1] || -> node4(s28)*. % 76.16/76.35 158298[113:MRR:834.0,158296.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.35 158301[113:Res:53.1,158298.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.35 158303[114:Spt:158301.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 158305[114:Res:158303.0,61.1] always3(s28) || -> . % 76.16/76.35 158306[114:SSi:158305.0,78191.0,78195.0,137750.0,157845.0,158296.0] || -> . % 76.16/76.35 158307[114:Spt:158306.0,158301.0,158303.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.35 158308[114:Spt:158306.0,158301.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 158312[114:Res:158308.0,61.1] always3(s29) || -> . % 76.16/76.35 158313[114:SSi:158312.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.35 158314[112:Spt:158313.0,157844.0,157845.0] || until2p7(s28)*+ -> . % 76.16/76.35 158315[112:Spt:158313.0,157844.1] || -> node4(s27)*. % 76.16/76.35 158317[112:MRR:837.0,158315.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.35 158320[112:Res:53.1,158317.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.35 158325[113:Spt:158320.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 158327[113:Res:158325.0,61.1] always3(s27) || -> . % 76.16/76.35 158328[113:SSi:158327.0,78187.0,78190.0,137749.0,157843.0,158315.0] || -> . % 76.16/76.35 158329[113:Spt:158328.0,158320.0,158325.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.35 158330[113:Spt:158328.0,158320.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 158334[113:Res:158330.0,61.1] always3(s28) || -> . % 76.16/76.35 158335[113:SSi:158334.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.35 158336[111:Spt:158335.0,157842.0,157843.0] || until2p7(s27)*+ -> . % 76.16/76.35 158337[111:Spt:158335.0,157842.1] || -> node4(s26)*. % 76.16/76.35 158339[111:MRR:840.0,158337.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.35 158342[111:Res:53.1,158339.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.35 158344[112:Spt:158342.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 158346[112:Res:158344.0,61.1] always3(s26) || -> . % 76.16/76.35 158347[112:SSi:158346.0,78182.0,78186.0,137748.0,157841.0,158337.0] || -> . % 76.16/76.35 158348[112:Spt:158347.0,158342.0,158344.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.35 158349[112:Spt:158347.0,158342.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 158353[112:Res:158349.0,61.1] always3(s27) || -> . % 76.16/76.35 158354[112:SSi:158353.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.35 158355[110:Spt:158354.0,157840.0,157841.0] || until2p7(s26)*+ -> . % 76.16/76.35 158356[110:Spt:158354.0,157840.1] || -> node4(s25)*. % 76.16/76.35 158358[110:MRR:843.0,158356.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.35 158361[110:Res:53.1,158358.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.35 158363[111:Spt:158361.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 158365[111:Res:158363.0,61.1] always3(s25) || -> . % 76.16/76.35 158366[111:SSi:158365.0,78178.0,78181.0,137747.0,157839.0,158356.0] || -> . % 76.16/76.35 158367[111:Spt:158366.0,158361.0,158363.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.35 158368[111:Spt:158366.0,158361.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 158372[111:Res:158368.0,61.1] always3(s26) || -> . % 76.16/76.35 158373[111:SSi:158372.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.35 158374[109:Spt:158373.0,157838.0,157839.0] || until2p7(s25)*+ -> . % 76.16/76.35 158375[109:Spt:158373.0,157838.1] || -> node4(s24)*. % 76.16/76.35 158377[109:MRR:846.0,158375.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.35 158380[109:Res:53.1,158377.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.35 158382[110:Spt:158380.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 158384[110:Res:158382.0,61.1] always3(s24) || -> . % 76.16/76.35 158385[110:SSi:158384.0,78173.0,78177.0,137746.0,157837.0,158375.0] || -> . % 76.16/76.35 158386[110:Spt:158385.0,158380.0,158382.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.35 158387[110:Spt:158385.0,158380.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 158391[110:Res:158387.0,61.1] always3(s25) || -> . % 76.16/76.35 158392[110:SSi:158391.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.35 158393[108:Spt:158392.0,157836.0,157837.0] || until2p7(s24)*+ -> . % 76.16/76.35 158394[108:Spt:158392.0,157836.1] || -> node4(s23)*. % 76.16/76.35 158396[108:MRR:849.0,158394.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.35 158399[108:Res:53.1,158396.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.35 158404[109:Spt:158399.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 158406[109:Res:158404.0,61.1] always3(s23) || -> . % 76.16/76.35 158407[109:SSi:158406.0,78169.0,78172.0,137745.0,157835.0,158394.0] || -> . % 76.16/76.35 158408[109:Spt:158407.0,158399.0,158404.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.35 158409[109:Spt:158407.0,158399.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 158413[109:Res:158409.0,61.1] always3(s24) || -> . % 76.16/76.35 158414[109:SSi:158413.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.35 158415[107:Spt:158414.0,157834.0,157835.0] || until2p7(s23)*+ -> . % 76.16/76.35 158416[107:Spt:158414.0,157834.1] || -> node4(s22)*. % 76.16/76.35 158418[107:MRR:852.0,158416.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.35 158421[107:Res:53.1,158418.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.35 158423[108:Spt:158421.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 158425[108:Res:158423.0,61.1] always3(s22) || -> . % 76.16/76.35 158426[108:SSi:158425.0,78164.0,78168.0,137744.0,157833.0,158416.0] || -> . % 76.16/76.35 158427[108:Spt:158426.0,158421.0,158423.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.35 158428[108:Spt:158426.0,158421.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 158432[108:Res:158428.0,61.1] always3(s23) || -> . % 76.16/76.35 158433[108:SSi:158432.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.35 158434[106:Spt:158433.0,157832.0,157833.0] || until2p7(s22)*+ -> . % 76.16/76.35 158435[106:Spt:158433.0,157832.1] || -> node4(s21)*. % 76.16/76.35 158437[106:MRR:855.0,158435.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.35 158440[106:Res:53.1,158437.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.35 158442[107:Spt:158440.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 158444[107:Res:158442.0,61.1] always3(s21) || -> . % 76.16/76.35 158445[107:SSi:158444.0,78160.0,78163.0,137743.0,157831.0,158435.0] || -> . % 76.16/76.35 158446[107:Spt:158445.0,158440.0,158442.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.35 158447[107:Spt:158445.0,158440.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 158451[107:Res:158447.0,61.1] always3(s22) || -> . % 76.16/76.35 158452[107:SSi:158451.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.35 158453[105:Spt:158452.0,157830.0,157831.0] || until2p7(s21)*+ -> . % 76.16/76.35 158454[105:Spt:158452.0,157830.1] || -> node4(s20)*. % 76.16/76.35 158456[105:MRR:858.0,158454.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.35 158459[105:Res:53.1,158456.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.35 158461[106:Spt:158459.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 158463[106:Res:158461.0,61.1] always3(s20) || -> . % 76.16/76.35 158464[106:SSi:158463.0,78155.0,78159.0,137742.0,157829.0,158454.0] || -> . % 76.16/76.35 158465[106:Spt:158464.0,158459.0,158461.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.35 158466[106:Spt:158464.0,158459.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 158470[106:Res:158466.0,61.1] always3(s21) || -> . % 76.16/76.35 158471[106:SSi:158470.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.35 158472[104:Spt:158471.0,157828.0,157829.0] || until2p7(s20)*+ -> . % 76.16/76.35 158473[104:Spt:158471.0,157828.1] || -> node4(s19)*. % 76.16/76.35 158475[104:MRR:861.0,158473.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.35 158478[104:Res:53.1,158475.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.35 158483[105:Spt:158478.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 158485[105:Res:158483.0,61.1] always3(s19) || -> . % 76.16/76.35 158486[105:SSi:158485.0,78151.0,78154.0,137741.0,157827.0,158473.0] || -> . % 76.16/76.35 158487[105:Spt:158486.0,158478.0,158483.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.35 158488[105:Spt:158486.0,158478.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 158492[105:Res:158488.0,61.1] always3(s20) || -> . % 76.16/76.35 158493[105:SSi:158492.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.35 158494[103:Spt:158493.0,157826.0,157827.0] || until2p7(s19)*+ -> . % 76.16/76.35 158495[103:Spt:158493.0,157826.1] || -> node4(s18)*. % 76.16/76.35 158497[103:MRR:864.0,158495.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.35 158500[103:Res:53.1,158497.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.35 158502[104:Spt:158500.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 158504[104:Res:158502.0,61.1] always3(s18) || -> . % 76.16/76.35 158505[104:SSi:158504.0,78146.0,78150.0,137740.0,157825.0,158495.0] || -> . % 76.16/76.35 158506[104:Spt:158505.0,158500.0,158502.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.35 158507[104:Spt:158505.0,158500.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 158511[104:Res:158507.0,61.1] always3(s19) || -> . % 76.16/76.35 158512[104:SSi:158511.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.35 158513[102:Spt:158512.0,157824.0,157825.0] || until2p7(s18)*+ -> . % 76.16/76.35 158514[102:Spt:158512.0,157824.1] || -> node4(s17)*. % 76.16/76.35 158516[102:MRR:867.0,158514.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.35 158519[102:Res:53.1,158516.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.35 158521[103:Spt:158519.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 158523[103:Res:158521.0,61.1] always3(s17) || -> . % 76.16/76.35 158524[103:SSi:158523.0,78142.0,78145.0,137739.0,157823.0,158514.0] || -> . % 76.16/76.35 158525[103:Spt:158524.0,158519.0,158521.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.35 158526[103:Spt:158524.0,158519.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 158530[103:Res:158526.0,61.1] always3(s18) || -> . % 76.16/76.35 158531[103:SSi:158530.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.35 158532[101:Spt:158531.0,157822.0,157823.0] || until2p7(s17)*+ -> . % 76.16/76.35 158533[101:Spt:158531.0,157822.1] || -> node4(s16)*. % 76.16/76.35 158535[101:MRR:870.0,158533.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.35 158538[101:Res:53.1,158535.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.35 158540[102:Spt:158538.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 158542[102:Res:158540.0,61.1] always3(s16) || -> . % 76.16/76.35 158543[102:SSi:158542.0,78137.0,78141.0,137738.0,157821.0,158533.0] || -> . % 76.16/76.35 158544[102:Spt:158543.0,158538.0,158540.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.35 158545[102:Spt:158543.0,158538.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 158549[102:Res:158545.0,61.1] always3(s17) || -> . % 76.16/76.35 158550[102:SSi:158549.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.35 158551[100:Spt:158550.0,157820.0,157821.0] || until2p7(s16)*+ -> . % 76.16/76.35 158552[100:Spt:158550.0,157820.1] || -> node4(s15)*. % 76.16/76.35 158554[100:MRR:873.0,158552.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.35 158557[100:Res:53.1,158554.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.35 158562[101:Spt:158557.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 158564[101:Res:158562.0,61.1] always3(s15) || -> . % 76.16/76.35 158565[101:SSi:158564.0,78133.0,78136.0,137737.0,157819.0,158552.0] || -> . % 76.16/76.35 158566[101:Spt:158565.0,158557.0,158562.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.35 158567[101:Spt:158565.0,158557.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 158571[101:Res:158567.0,61.1] always3(s16) || -> . % 76.16/76.35 158572[101:SSi:158571.0,78137.0,78141.0,137738.0] || -> . % 76.16/76.35 158573[99:Spt:158572.0,157818.0,157819.0] || until2p7(s15)*+ -> . % 76.16/76.35 158574[99:Spt:158572.0,157818.1] || -> node4(s14)*. % 76.16/76.35 158576[99:MRR:876.0,158574.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.35 158579[99:Res:53.1,158576.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.35 158581[100:Spt:158579.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.35 158583[100:Res:158581.0,61.1] always3(s14) || -> . % 76.16/76.35 158584[100:SSi:158583.0,78128.0,78132.0,137736.0,157817.0,158574.0] || -> . % 76.16/76.35 158585[100:Spt:158584.0,158579.0,158581.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.35 158586[100:Spt:158584.0,158579.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 158590[100:Res:158586.0,61.1] always3(s15) || -> . % 76.16/76.35 158591[100:SSi:158590.0,78133.0,78136.0,137737.0] || -> . % 76.16/76.35 158592[98:Spt:158591.0,157816.0,157817.0] || until2p7(s14)*+ -> . % 76.16/76.35 158593[98:Spt:158591.0,157816.1] || -> node4(s13)*. % 76.16/76.35 158595[98:MRR:879.0,158593.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.35 158598[98:Res:53.1,158595.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.35 158600[99:Spt:158598.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.35 158602[99:Res:158600.0,61.1] always3(s13) || -> . % 76.16/76.35 158603[99:SSi:158602.0,78124.0,78127.0,137735.0,157815.0,158593.0] || -> . % 76.16/76.35 158604[99:Spt:158603.0,158598.0,158600.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.35 158605[99:Spt:158603.0,158598.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.35 158609[99:Res:158605.0,61.1] always3(s14) || -> . % 76.16/76.35 158610[99:SSi:158609.0,78128.0,78132.0,137736.0] || -> . % 76.16/76.35 158611[97:Spt:158610.0,157814.0,157815.0] || until2p7(s13)*+ -> . % 76.16/76.35 158612[97:Spt:158610.0,157814.1] || -> node4(s12)*. % 76.16/76.35 158614[97:MRR:882.0,158612.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.35 158617[97:Res:53.1,158614.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.35 158619[98:Spt:158617.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.35 158621[98:Res:158619.0,61.1] always3(s12) || -> . % 76.16/76.35 158622[98:SSi:158621.0,78119.0,78123.0,137734.0,157813.0,158612.0] || -> . % 76.16/76.35 158623[98:Spt:158622.0,158617.0,158619.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.35 158624[98:Spt:158622.0,158617.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.35 158628[98:Res:158624.0,61.1] always3(s13) || -> . % 76.16/76.35 158629[98:SSi:158628.0,78124.0,78127.0,137735.0] || -> . % 76.16/76.35 158630[96:Spt:158629.0,157812.0,157813.0] || until2p7(s12)*+ -> . % 76.16/76.35 158631[96:Spt:158629.0,157812.1] || -> node4(s11)*. % 76.16/76.35 158633[96:MRR:885.0,158631.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.35 158636[96:Res:53.1,158633.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.35 158641[97:Spt:158636.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.35 158643[97:Res:158641.0,61.1] always3(s11) || -> . % 76.16/76.35 158644[97:SSi:158643.0,78115.0,78118.0,137733.0,157811.0,158631.0] || -> . % 76.16/76.35 158645[97:Spt:158644.0,158636.0,158641.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.35 158646[97:Spt:158644.0,158636.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.35 158650[97:Res:158646.0,61.1] always3(s12) || -> . % 76.16/76.35 158651[97:SSi:158650.0,78119.0,78123.0,137734.0] || -> . % 76.16/76.35 158652[95:Spt:158651.0,157810.0,157811.0] || until2p7(s11)*+ -> . % 76.16/76.35 158653[95:Spt:158651.0,157810.1] || -> node4(s10)*. % 76.16/76.35 158655[95:MRR:888.0,158653.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.35 158658[95:Res:53.1,158655.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.35 158660[95:MRR:158658.0,157800.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.35 158662[95:Res:158660.0,61.1] always3(s11) || -> . % 76.16/76.35 158663[95:SSi:158662.0,78115.0,78118.0,137733.0] || -> . % 76.16/76.35 158664[93:Spt:158663.0,157652.0,157655.0] || trans(s49,s10)*+ -> . % 76.16/76.35 158665[93:Spt:158663.0,157652.1,157652.2,157652.3,157652.4,157652.5,157652.6] || -> trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.35 158667[93:MRR:157654.1,158664.0] xuntil6(s49) || -> trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.35 158668[94:Spt:158665.0] || -> trans(s49,s9)*. % 76.16/76.35 158669[94:Res:158668.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s9)*. % 76.16/76.35 158671[94:Res:158668.0,60.0] || -> node2(s49,s9)*. % 76.16/76.35 158672[94:SSi:158669.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s9)*. % 76.16/76.35 158673[94:Res:158671.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)*. % 76.16/76.35 158806[94:SoR:158673.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)*. % 76.16/76.35 158808[94:SoR:158806.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)* xuntil6(s49). % 76.16/76.35 158809[94:SSi:158808.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s9,c_busy)* xuntil6(s49). % 76.16/76.35 158810[95:Spt:158809.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.35 158812[95:Res:158810.0,61.1] always3(s9) || -> . % 76.16/76.35 158813[95:SSi:158812.0,78106.0,78109.0,137731.0] || -> . % 76.16/76.35 158814[95:Spt:158813.0,158809.1,158810.0] || m_main_v_state(s9,c_busy)*+ -> . % 76.16/76.35 158815[95:Spt:158813.0,158809.0,158809.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.35 158819[95:MRR:158806.2,158814.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.35 158820[95:Res:53.1,158815.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.35 158822[95:MRR:158820.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.35 158823[95:MRR:158672.0,158822.0] || -> until2p7(s9)*. % 76.16/76.35 158824[95:MRR:205.0,158823.0] || -> until2p7(s10)* node4(s9). % 76.16/76.35 158825[96:Spt:158824.0] || -> until2p7(s10)*. % 76.16/76.35 158826[96:MRR:206.0,158825.0] || -> until2p7(s11)* node4(s10). % 76.16/76.35 158827[97:Spt:158826.0] || -> until2p7(s11)*. % 76.16/76.35 158828[97:MRR:207.0,158827.0] || -> until2p7(s12)* node4(s11). % 76.16/76.35 158829[98:Spt:158828.0] || -> until2p7(s12)*. % 76.16/76.35 158830[98:MRR:208.0,158829.0] || -> until2p7(s13)* node4(s12). % 76.16/76.35 158831[99:Spt:158830.0] || -> until2p7(s13)*. % 76.16/76.35 158832[99:MRR:209.0,158831.0] || -> until2p7(s14)* node4(s13). % 76.16/76.35 158833[100:Spt:158832.0] || -> until2p7(s14)*. % 76.16/76.35 158834[100:MRR:210.0,158833.0] || -> until2p7(s15)* node4(s14). % 76.16/76.35 158835[101:Spt:158834.0] || -> until2p7(s15)*. % 76.16/76.35 158836[101:MRR:211.0,158835.0] || -> until2p7(s16)* node4(s15). % 76.16/76.35 158837[102:Spt:158836.0] || -> until2p7(s16)*. % 76.16/76.35 158838[102:MRR:212.0,158837.0] || -> until2p7(s17)* node4(s16). % 76.16/76.35 158839[103:Spt:158838.0] || -> until2p7(s17)*. % 76.16/76.35 158840[103:MRR:213.0,158839.0] || -> until2p7(s18)* node4(s17). % 76.16/76.35 158841[104:Spt:158840.0] || -> until2p7(s18)*. % 76.16/76.35 158842[104:MRR:214.0,158841.0] || -> until2p7(s19)* node4(s18). % 76.16/76.35 158843[105:Spt:158842.0] || -> until2p7(s19)*. % 76.16/76.35 158844[105:MRR:215.0,158843.0] || -> until2p7(s20)* node4(s19). % 76.16/76.35 158845[106:Spt:158844.0] || -> until2p7(s20)*. % 76.16/76.35 158846[106:MRR:216.0,158845.0] || -> until2p7(s21)* node4(s20). % 76.16/76.35 158847[107:Spt:158846.0] || -> until2p7(s21)*. % 76.16/76.35 158848[107:MRR:217.0,158847.0] || -> until2p7(s22)* node4(s21). % 76.16/76.35 158849[108:Spt:158848.0] || -> until2p7(s22)*. % 76.16/76.35 158850[108:MRR:218.0,158849.0] || -> until2p7(s23)* node4(s22). % 76.16/76.35 158851[109:Spt:158850.0] || -> until2p7(s23)*. % 76.16/76.35 158852[109:MRR:219.0,158851.0] || -> until2p7(s24)* node4(s23). % 76.16/76.35 158853[110:Spt:158852.0] || -> until2p7(s24)*. % 76.16/76.35 158854[110:MRR:220.0,158853.0] || -> until2p7(s25)* node4(s24). % 76.16/76.35 158855[111:Spt:158854.0] || -> until2p7(s25)*. % 76.16/76.35 158856[111:MRR:221.0,158855.0] || -> until2p7(s26)* node4(s25). % 76.16/76.35 158857[112:Spt:158856.0] || -> until2p7(s26)*. % 76.16/76.35 158858[112:MRR:222.0,158857.0] || -> until2p7(s27)* node4(s26). % 76.16/76.35 158859[113:Spt:158858.0] || -> until2p7(s27)*. % 76.16/76.35 158860[113:MRR:223.0,158859.0] || -> until2p7(s28)* node4(s27). % 76.16/76.35 158861[114:Spt:158860.0] || -> until2p7(s28)*. % 76.16/76.35 158862[114:MRR:224.0,158861.0] || -> until2p7(s29)* node4(s28). % 76.16/76.35 158863[115:Spt:158862.0] || -> until2p7(s29)*. % 76.16/76.35 158864[115:MRR:225.0,158863.0] || -> until2p7(s30)* node4(s29). % 76.16/76.35 158865[116:Spt:158864.0] || -> until2p7(s30)*. % 76.16/76.35 158866[116:MRR:226.0,158865.0] || -> until2p7(s31)* node4(s30). % 76.16/76.35 158867[117:Spt:158866.0] || -> until2p7(s31)*. % 76.16/76.35 158868[117:MRR:227.0,158867.0] || -> until2p7(s32)* node4(s31). % 76.16/76.35 158869[118:Spt:158868.0] || -> until2p7(s32)*. % 76.16/76.35 158870[118:MRR:228.0,158869.0] || -> until2p7(s33)* node4(s32). % 76.16/76.35 158871[119:Spt:158870.0] || -> until2p7(s33)*. % 76.16/76.35 158872[119:MRR:229.0,158871.0] || -> until2p7(s34)* node4(s33). % 76.16/76.35 158873[120:Spt:158872.0] || -> until2p7(s34)*. % 76.16/76.35 158874[120:MRR:230.0,158873.0] || -> until2p7(s35)* node4(s34). % 76.16/76.35 158875[121:Spt:158874.0] || -> until2p7(s35)*. % 76.16/76.35 158876[121:MRR:231.0,158875.0] || -> until2p7(s36)* node4(s35). % 76.16/76.35 158877[122:Spt:158876.0] || -> until2p7(s36)*. % 76.16/76.35 158878[122:MRR:232.0,158877.0] || -> until2p7(s37)* node4(s36). % 76.16/76.35 158879[123:Spt:158878.0] || -> until2p7(s37)*. % 76.16/76.35 158880[123:MRR:235.0,158879.0] || -> until2p7(s38)* node4(s37). % 76.16/76.35 158881[124:Spt:158880.0] || -> until2p7(s38)*. % 76.16/76.35 158882[124:MRR:236.0,158881.0] || -> until2p7(s39)* node4(s38). % 76.16/76.35 158883[125:Spt:158882.0] || -> until2p7(s39)*. % 76.16/76.35 158884[125:MRR:237.0,158883.0] || -> until2p7(s40)* node4(s39). % 76.16/76.35 158885[126:Spt:158884.0] || -> until2p7(s40)*. % 76.16/76.35 158886[126:MRR:238.0,158885.0] || -> until2p7(s41)* node4(s40). % 76.16/76.35 158887[127:Spt:158886.0] || -> until2p7(s41)*. % 76.16/76.35 158888[127:MRR:239.0,158887.0] || -> until2p7(s42)* node4(s41). % 76.16/76.35 158889[128:Spt:158888.0] || -> until2p7(s42)*. % 76.16/76.35 158890[128:MRR:240.0,158889.0] || -> until2p7(s43)* node4(s42). % 76.16/76.35 158891[129:Spt:158890.0] || -> until2p7(s43)*. % 76.16/76.35 158892[129:MRR:241.0,158891.0] || -> until2p7(s44)* node4(s43). % 76.16/76.35 158893[130:Spt:158892.0] || -> until2p7(s44)*. % 76.16/76.35 158894[130:MRR:539.0,158893.0] || -> until2p7(s45)* node4(s44). % 76.16/76.35 158895[131:Spt:158894.0] || -> until2p7(s45)*. % 76.16/76.35 158896[131:MRR:544.0,158895.0] || -> until2p7(s46)* node4(s45). % 76.16/76.35 158897[132:Spt:158896.0] || -> until2p7(s46)*. % 76.16/76.35 158898[132:MRR:549.0,158897.0] || -> until2p7(s47)* node4(s46). % 76.16/76.35 158899[133:Spt:158898.0] || -> until2p7(s47)*. % 76.16/76.35 158900[133:MRR:554.0,158899.0] || -> until2p7(s48)* node4(s47). % 76.16/76.35 158901[134:Spt:158900.0] || -> until2p7(s48)*. % 76.16/76.35 158902[134:MRR:559.0,158901.0] || -> until2p7(s49)* node4(s48). % 76.16/76.35 158903[135:Spt:158902.0] || -> until2p7(s49)*. % 76.16/76.35 158904[135:MRR:194.0,158903.0] || -> node4(s49)*. % 76.16/76.35 158905[135:MRR:158819.0,158904.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.35 158906[135:Res:53.1,158905.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.35 158908[135:MRR:158906.0,78381.0] || -> . % 76.16/76.35 158909[135:Spt:158908.0,158902.0,158903.0] || until2p7(s49)*+ -> . % 76.16/76.35 158910[135:Spt:158908.0,158902.1] || -> node4(s48)*. % 76.16/76.35 158911[135:MRR:78384.0,158910.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.35 158914[135:Res:53.1,158911.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 158917[135:Res:158914.0,61.1] always3(s48) || -> . % 76.16/76.35 158918[135:SSi:158917.0,78281.0,78387.0,137770.0,158901.0,158910.0] || -> . % 76.16/76.35 158919[134:Spt:158918.0,158900.0,158901.0] || until2p7(s48)*+ -> . % 76.16/76.35 158920[134:Spt:158918.0,158900.1] || -> node4(s47)*. % 76.16/76.35 158922[134:MRR:777.0,158920.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.35 158937[134:Res:53.1,158922.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.35 158939[135:Spt:158937.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 158941[135:Res:158939.0,61.1] always3(s47) || -> . % 76.16/76.35 158942[135:SSi:158941.0,78277.0,78280.0,137769.0,158899.0,158920.0] || -> . % 76.16/76.35 158943[135:Spt:158942.0,158937.0,158939.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.35 158944[135:Spt:158942.0,158937.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.35 158948[135:Res:158944.0,61.1] always3(s48) || -> . % 76.16/76.35 158949[135:SSi:158948.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.35 158950[133:Spt:158949.0,158898.0,158899.0] || until2p7(s47)*+ -> . % 76.16/76.35 158951[133:Spt:158949.0,158898.1] || -> node4(s46)*. % 76.16/76.35 158953[133:MRR:780.0,158951.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.35 158963[133:Res:53.1,158953.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.35 158965[134:Spt:158963.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 158967[134:Res:158965.0,61.1] always3(s46) || -> . % 76.16/76.35 158968[134:SSi:158967.0,78272.0,78276.0,137768.0,158897.0,158951.0] || -> . % 76.16/76.35 158969[134:Spt:158968.0,158963.0,158965.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.35 158970[134:Spt:158968.0,158963.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.35 158974[134:Res:158970.0,61.1] always3(s47) || -> . % 76.16/76.35 158975[134:SSi:158974.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.35 158976[132:Spt:158975.0,158896.0,158897.0] || until2p7(s46)*+ -> . % 76.16/76.35 158977[132:Spt:158975.0,158896.1] || -> node4(s45)*. % 76.16/76.35 158979[132:MRR:783.0,158977.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.35 158982[132:Res:53.1,158979.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.35 158984[133:Spt:158982.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 158986[133:Res:158984.0,61.1] always3(s45) || -> . % 76.16/76.35 158987[133:SSi:158986.0,78268.0,78271.0,137767.0,158895.0,158977.0] || -> . % 76.16/76.35 158988[133:Spt:158987.0,158982.0,158984.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.35 158989[133:Spt:158987.0,158982.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.35 158993[133:Res:158989.0,61.1] always3(s46) || -> . % 76.16/76.35 158994[133:SSi:158993.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.35 158995[131:Spt:158994.0,158894.0,158895.0] || until2p7(s45)*+ -> . % 76.16/76.35 158996[131:Spt:158994.0,158894.1] || -> node4(s44)*. % 76.16/76.35 158998[131:MRR:786.0,158996.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.35 159001[131:Res:53.1,158998.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.35 159003[132:Spt:159001.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 159005[132:Res:159003.0,61.1] always3(s44) || -> . % 76.16/76.35 159006[132:SSi:159005.0,78263.0,78267.0,137766.0,158893.0,158996.0] || -> . % 76.16/76.35 159007[132:Spt:159006.0,159001.0,159003.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.35 159008[132:Spt:159006.0,159001.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.35 159012[132:Res:159008.0,61.1] always3(s45) || -> . % 76.16/76.35 159013[132:SSi:159012.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.35 159014[130:Spt:159013.0,158892.0,158893.0] || until2p7(s44)*+ -> . % 76.16/76.35 159015[130:Spt:159013.0,158892.1] || -> node4(s43)*. % 76.16/76.35 159017[130:MRR:789.0,159015.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.35 159020[130:Res:53.1,159017.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.35 159025[131:Spt:159020.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 159027[131:Res:159025.0,61.1] always3(s43) || -> . % 76.16/76.35 159028[131:SSi:159027.0,78259.0,78262.0,137765.0,158891.0,159015.0] || -> . % 76.16/76.35 159029[131:Spt:159028.0,159020.0,159025.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.35 159030[131:Spt:159028.0,159020.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.35 159034[131:Res:159030.0,61.1] always3(s44) || -> . % 76.16/76.35 159035[131:SSi:159034.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.35 159036[129:Spt:159035.0,158890.0,158891.0] || until2p7(s43)*+ -> . % 76.16/76.35 159037[129:Spt:159035.0,158890.1] || -> node4(s42)*. % 76.16/76.35 159039[129:MRR:792.0,159037.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.35 159042[129:Res:53.1,159039.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.35 159044[130:Spt:159042.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 159046[130:Res:159044.0,61.1] always3(s42) || -> . % 76.16/76.35 159047[130:SSi:159046.0,78254.0,78258.0,137764.0,158889.0,159037.0] || -> . % 76.16/76.35 159048[130:Spt:159047.0,159042.0,159044.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.35 159049[130:Spt:159047.0,159042.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.35 159053[130:Res:159049.0,61.1] always3(s43) || -> . % 76.16/76.35 159054[130:SSi:159053.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.35 159055[128:Spt:159054.0,158888.0,158889.0] || until2p7(s42)*+ -> . % 76.16/76.35 159056[128:Spt:159054.0,158888.1] || -> node4(s41)*. % 76.16/76.35 159058[128:MRR:795.0,159056.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.35 159061[128:Res:53.1,159058.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.35 159063[129:Spt:159061.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 159065[129:Res:159063.0,61.1] always3(s41) || -> . % 76.16/76.35 159066[129:SSi:159065.0,78250.0,78253.0,137763.0,158887.0,159056.0] || -> . % 76.16/76.35 159067[129:Spt:159066.0,159061.0,159063.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.35 159068[129:Spt:159066.0,159061.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.35 159072[129:Res:159068.0,61.1] always3(s42) || -> . % 76.16/76.35 159073[129:SSi:159072.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.35 159074[127:Spt:159073.0,158886.0,158887.0] || until2p7(s41)*+ -> . % 76.16/76.35 159075[127:Spt:159073.0,158886.1] || -> node4(s40)*. % 76.16/76.35 159077[127:MRR:798.0,159075.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.35 159080[127:Res:53.1,159077.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.35 159082[128:Spt:159080.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 159084[128:Res:159082.0,61.1] always3(s40) || -> . % 76.16/76.35 159085[128:SSi:159084.0,78245.0,78249.0,137762.0,158885.0,159075.0] || -> . % 76.16/76.35 159086[128:Spt:159085.0,159080.0,159082.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.35 159087[128:Spt:159085.0,159080.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.35 159091[128:Res:159087.0,61.1] always3(s41) || -> . % 76.16/76.35 159092[128:SSi:159091.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.35 159093[126:Spt:159092.0,158884.0,158885.0] || until2p7(s40)*+ -> . % 76.16/76.35 159094[126:Spt:159092.0,158884.1] || -> node4(s39)*. % 76.16/76.35 159096[126:MRR:801.0,159094.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.35 159099[126:Res:53.1,159096.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.35 159104[127:Spt:159099.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 159106[127:Res:159104.0,61.1] always3(s39) || -> . % 76.16/76.35 159107[127:SSi:159106.0,78241.0,78244.0,137761.0,158883.0,159094.0] || -> . % 76.16/76.35 159108[127:Spt:159107.0,159099.0,159104.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.35 159109[127:Spt:159107.0,159099.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.35 159113[127:Res:159109.0,61.1] always3(s40) || -> . % 76.16/76.35 159114[127:SSi:159113.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.35 159115[125:Spt:159114.0,158882.0,158883.0] || until2p7(s39)*+ -> . % 76.16/76.35 159116[125:Spt:159114.0,158882.1] || -> node4(s38)*. % 76.16/76.35 159118[125:MRR:804.0,159116.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.35 159121[125:Res:53.1,159118.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.35 159123[126:Spt:159121.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 159125[126:Res:159123.0,61.1] always3(s38) || -> . % 76.16/76.35 159126[126:SSi:159125.0,78236.0,78240.0,137760.0,158881.0,159116.0] || -> . % 76.16/76.35 159127[126:Spt:159126.0,159121.0,159123.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.35 159128[126:Spt:159126.0,159121.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.35 159132[126:Res:159128.0,61.1] always3(s39) || -> . % 76.16/76.35 159133[126:SSi:159132.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.35 159134[124:Spt:159133.0,158880.0,158881.0] || until2p7(s38)*+ -> . % 76.16/76.35 159135[124:Spt:159133.0,158880.1] || -> node4(s37)*. % 76.16/76.35 159137[124:MRR:807.0,159135.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.35 159140[124:Res:53.1,159137.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.35 159142[125:Spt:159140.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 159144[125:Res:159142.0,61.1] always3(s37) || -> . % 76.16/76.35 159145[125:SSi:159144.0,78232.0,78235.0,137759.0,158879.0,159135.0] || -> . % 76.16/76.35 159146[125:Spt:159145.0,159140.0,159142.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.35 159147[125:Spt:159145.0,159140.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.35 159151[125:Res:159147.0,61.1] always3(s38) || -> . % 76.16/76.35 159152[125:SSi:159151.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.35 159153[123:Spt:159152.0,158878.0,158879.0] || until2p7(s37)*+ -> . % 76.16/76.35 159154[123:Spt:159152.0,158878.1] || -> node4(s36)*. % 76.16/76.35 159156[123:MRR:810.0,159154.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.35 159159[123:Res:53.1,159156.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.35 159161[124:Spt:159159.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 159163[124:Res:159161.0,61.1] always3(s36) || -> . % 76.16/76.35 159164[124:SSi:159163.0,78227.0,78231.0,137758.0,158877.0,159154.0] || -> . % 76.16/76.35 159165[124:Spt:159164.0,159159.0,159161.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.35 159166[124:Spt:159164.0,159159.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.35 159170[124:Res:159166.0,61.1] always3(s37) || -> . % 76.16/76.35 159171[124:SSi:159170.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.35 159172[122:Spt:159171.0,158876.0,158877.0] || until2p7(s36)*+ -> . % 76.16/76.35 159173[122:Spt:159171.0,158876.1] || -> node4(s35)*. % 76.16/76.35 159175[122:MRR:813.0,159173.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.35 159178[122:Res:53.1,159175.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.35 159183[123:Spt:159178.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 159185[123:Res:159183.0,61.1] always3(s35) || -> . % 76.16/76.35 159186[123:SSi:159185.0,78223.0,78226.0,137757.0,158875.0,159173.0] || -> . % 76.16/76.35 159187[123:Spt:159186.0,159178.0,159183.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.35 159188[123:Spt:159186.0,159178.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.35 159192[123:Res:159188.0,61.1] always3(s36) || -> . % 76.16/76.35 159193[123:SSi:159192.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.35 159194[121:Spt:159193.0,158874.0,158875.0] || until2p7(s35)*+ -> . % 76.16/76.35 159195[121:Spt:159193.0,158874.1] || -> node4(s34)*. % 76.16/76.35 159197[121:MRR:816.0,159195.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.35 159200[121:Res:53.1,159197.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.35 159202[122:Spt:159200.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 159204[122:Res:159202.0,61.1] always3(s34) || -> . % 76.16/76.35 159205[122:SSi:159204.0,78218.0,78222.0,137756.0,158873.0,159195.0] || -> . % 76.16/76.35 159206[122:Spt:159205.0,159200.0,159202.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.35 159207[122:Spt:159205.0,159200.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.35 159211[122:Res:159207.0,61.1] always3(s35) || -> . % 76.16/76.35 159212[122:SSi:159211.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.35 159213[120:Spt:159212.0,158872.0,158873.0] || until2p7(s34)*+ -> . % 76.16/76.35 159214[120:Spt:159212.0,158872.1] || -> node4(s33)*. % 76.16/76.35 159216[120:MRR:819.0,159214.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.35 159219[120:Res:53.1,159216.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.35 159221[121:Spt:159219.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 159223[121:Res:159221.0,61.1] always3(s33) || -> . % 76.16/76.35 159224[121:SSi:159223.0,78214.0,78217.0,137755.0,158871.0,159214.0] || -> . % 76.16/76.35 159225[121:Spt:159224.0,159219.0,159221.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.35 159226[121:Spt:159224.0,159219.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.35 159230[121:Res:159226.0,61.1] always3(s34) || -> . % 76.16/76.35 159231[121:SSi:159230.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.35 159232[119:Spt:159231.0,158870.0,158871.0] || until2p7(s33)*+ -> . % 76.16/76.35 159233[119:Spt:159231.0,158870.1] || -> node4(s32)*. % 76.16/76.35 159235[119:MRR:822.0,159233.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.35 159238[119:Res:53.1,159235.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.35 159240[120:Spt:159238.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 159242[120:Res:159240.0,61.1] always3(s32) || -> . % 76.16/76.35 159243[120:SSi:159242.0,78209.0,78213.0,137754.0,158869.0,159233.0] || -> . % 76.16/76.35 159244[120:Spt:159243.0,159238.0,159240.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.35 159245[120:Spt:159243.0,159238.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.35 159249[120:Res:159245.0,61.1] always3(s33) || -> . % 76.16/76.35 159250[120:SSi:159249.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.35 159251[118:Spt:159250.0,158868.0,158869.0] || until2p7(s32)*+ -> . % 76.16/76.35 159252[118:Spt:159250.0,158868.1] || -> node4(s31)*. % 76.16/76.35 159254[118:MRR:825.0,159252.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.35 159257[118:Res:53.1,159254.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.35 159262[119:Spt:159257.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 159264[119:Res:159262.0,61.1] always3(s31) || -> . % 76.16/76.35 159265[119:SSi:159264.0,78205.0,78208.0,137753.0,158867.0,159252.0] || -> . % 76.16/76.35 159266[119:Spt:159265.0,159257.0,159262.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.35 159267[119:Spt:159265.0,159257.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.35 159271[119:Res:159267.0,61.1] always3(s32) || -> . % 76.16/76.35 159272[119:SSi:159271.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.35 159273[117:Spt:159272.0,158866.0,158867.0] || until2p7(s31)*+ -> . % 76.16/76.35 159274[117:Spt:159272.0,158866.1] || -> node4(s30)*. % 76.16/76.35 159276[117:MRR:828.0,159274.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.35 159279[117:Res:53.1,159276.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.35 159281[118:Spt:159279.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 159283[118:Res:159281.0,61.1] always3(s30) || -> . % 76.16/76.35 159284[118:SSi:159283.0,78200.0,78204.0,137752.0,158865.0,159274.0] || -> . % 76.16/76.35 159285[118:Spt:159284.0,159279.0,159281.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.35 159286[118:Spt:159284.0,159279.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.35 159290[118:Res:159286.0,61.1] always3(s31) || -> . % 76.16/76.35 159291[118:SSi:159290.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.35 159292[116:Spt:159291.0,158864.0,158865.0] || until2p7(s30)*+ -> . % 76.16/76.35 159293[116:Spt:159291.0,158864.1] || -> node4(s29)*. % 76.16/76.35 159295[116:MRR:831.0,159293.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.35 159298[116:Res:53.1,159295.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.35 159300[117:Spt:159298.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 159302[117:Res:159300.0,61.1] always3(s29) || -> . % 76.16/76.35 159303[117:SSi:159302.0,78196.0,78199.0,137751.0,158863.0,159293.0] || -> . % 76.16/76.35 159304[117:Spt:159303.0,159298.0,159300.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.35 159305[117:Spt:159303.0,159298.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.35 159309[117:Res:159305.0,61.1] always3(s30) || -> . % 76.16/76.35 159310[117:SSi:159309.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.35 159311[115:Spt:159310.0,158862.0,158863.0] || until2p7(s29)*+ -> . % 76.16/76.35 159312[115:Spt:159310.0,158862.1] || -> node4(s28)*. % 76.16/76.35 159314[115:MRR:834.0,159312.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.35 159317[115:Res:53.1,159314.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.35 159319[116:Spt:159317.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 159321[116:Res:159319.0,61.1] always3(s28) || -> . % 76.16/76.35 159322[116:SSi:159321.0,78191.0,78195.0,137750.0,158861.0,159312.0] || -> . % 76.16/76.35 159323[116:Spt:159322.0,159317.0,159319.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.35 159324[116:Spt:159322.0,159317.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.35 159328[116:Res:159324.0,61.1] always3(s29) || -> . % 76.16/76.35 159329[116:SSi:159328.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.35 159330[114:Spt:159329.0,158860.0,158861.0] || until2p7(s28)*+ -> . % 76.16/76.35 159331[114:Spt:159329.0,158860.1] || -> node4(s27)*. % 76.16/76.35 159333[114:MRR:837.0,159331.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.35 159336[114:Res:53.1,159333.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.35 159341[115:Spt:159336.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 159343[115:Res:159341.0,61.1] always3(s27) || -> . % 76.16/76.35 159344[115:SSi:159343.0,78187.0,78190.0,137749.0,158859.0,159331.0] || -> . % 76.16/76.35 159345[115:Spt:159344.0,159336.0,159341.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.35 159346[115:Spt:159344.0,159336.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.35 159350[115:Res:159346.0,61.1] always3(s28) || -> . % 76.16/76.35 159351[115:SSi:159350.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.35 159352[113:Spt:159351.0,158858.0,158859.0] || until2p7(s27)*+ -> . % 76.16/76.35 159353[113:Spt:159351.0,158858.1] || -> node4(s26)*. % 76.16/76.35 159355[113:MRR:840.0,159353.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.35 159358[113:Res:53.1,159355.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.35 159360[114:Spt:159358.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 159362[114:Res:159360.0,61.1] always3(s26) || -> . % 76.16/76.35 159363[114:SSi:159362.0,78182.0,78186.0,137748.0,158857.0,159353.0] || -> . % 76.16/76.35 159364[114:Spt:159363.0,159358.0,159360.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.35 159365[114:Spt:159363.0,159358.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.35 159369[114:Res:159365.0,61.1] always3(s27) || -> . % 76.16/76.35 159370[114:SSi:159369.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.35 159371[112:Spt:159370.0,158856.0,158857.0] || until2p7(s26)*+ -> . % 76.16/76.35 159372[112:Spt:159370.0,158856.1] || -> node4(s25)*. % 76.16/76.35 159374[112:MRR:843.0,159372.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.35 159377[112:Res:53.1,159374.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.35 159379[113:Spt:159377.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 159381[113:Res:159379.0,61.1] always3(s25) || -> . % 76.16/76.35 159382[113:SSi:159381.0,78178.0,78181.0,137747.0,158855.0,159372.0] || -> . % 76.16/76.35 159383[113:Spt:159382.0,159377.0,159379.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.35 159384[113:Spt:159382.0,159377.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.35 159388[113:Res:159384.0,61.1] always3(s26) || -> . % 76.16/76.35 159389[113:SSi:159388.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.35 159390[111:Spt:159389.0,158854.0,158855.0] || until2p7(s25)*+ -> . % 76.16/76.35 159391[111:Spt:159389.0,158854.1] || -> node4(s24)*. % 76.16/76.35 159393[111:MRR:846.0,159391.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.35 159396[111:Res:53.1,159393.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.35 159398[112:Spt:159396.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 159400[112:Res:159398.0,61.1] always3(s24) || -> . % 76.16/76.35 159401[112:SSi:159400.0,78173.0,78177.0,137746.0,158853.0,159391.0] || -> . % 76.16/76.35 159402[112:Spt:159401.0,159396.0,159398.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.35 159403[112:Spt:159401.0,159396.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.35 159407[112:Res:159403.0,61.1] always3(s25) || -> . % 76.16/76.35 159408[112:SSi:159407.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.35 159409[110:Spt:159408.0,158852.0,158853.0] || until2p7(s24)*+ -> . % 76.16/76.35 159410[110:Spt:159408.0,158852.1] || -> node4(s23)*. % 76.16/76.35 159412[110:MRR:849.0,159410.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.35 159415[110:Res:53.1,159412.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.35 159420[111:Spt:159415.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 159422[111:Res:159420.0,61.1] always3(s23) || -> . % 76.16/76.35 159423[111:SSi:159422.0,78169.0,78172.0,137745.0,158851.0,159410.0] || -> . % 76.16/76.35 159424[111:Spt:159423.0,159415.0,159420.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.35 159425[111:Spt:159423.0,159415.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.35 159429[111:Res:159425.0,61.1] always3(s24) || -> . % 76.16/76.35 159430[111:SSi:159429.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.35 159431[109:Spt:159430.0,158850.0,158851.0] || until2p7(s23)*+ -> . % 76.16/76.35 159432[109:Spt:159430.0,158850.1] || -> node4(s22)*. % 76.16/76.35 159434[109:MRR:852.0,159432.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.35 159437[109:Res:53.1,159434.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.35 159439[110:Spt:159437.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 159441[110:Res:159439.0,61.1] always3(s22) || -> . % 76.16/76.35 159442[110:SSi:159441.0,78164.0,78168.0,137744.0,158849.0,159432.0] || -> . % 76.16/76.35 159443[110:Spt:159442.0,159437.0,159439.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.35 159444[110:Spt:159442.0,159437.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.35 159448[110:Res:159444.0,61.1] always3(s23) || -> . % 76.16/76.35 159449[110:SSi:159448.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.35 159450[108:Spt:159449.0,158848.0,158849.0] || until2p7(s22)*+ -> . % 76.16/76.35 159451[108:Spt:159449.0,158848.1] || -> node4(s21)*. % 76.16/76.35 159453[108:MRR:855.0,159451.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.35 159456[108:Res:53.1,159453.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.35 159458[109:Spt:159456.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 159460[109:Res:159458.0,61.1] always3(s21) || -> . % 76.16/76.35 159461[109:SSi:159460.0,78160.0,78163.0,137743.0,158847.0,159451.0] || -> . % 76.16/76.35 159462[109:Spt:159461.0,159456.0,159458.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.35 159463[109:Spt:159461.0,159456.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.35 159467[109:Res:159463.0,61.1] always3(s22) || -> . % 76.16/76.35 159468[109:SSi:159467.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.35 159469[107:Spt:159468.0,158846.0,158847.0] || until2p7(s21)*+ -> . % 76.16/76.35 159470[107:Spt:159468.0,158846.1] || -> node4(s20)*. % 76.16/76.35 159472[107:MRR:858.0,159470.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.35 159475[107:Res:53.1,159472.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.35 159477[108:Spt:159475.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 159479[108:Res:159477.0,61.1] always3(s20) || -> . % 76.16/76.35 159480[108:SSi:159479.0,78155.0,78159.0,137742.0,158845.0,159470.0] || -> . % 76.16/76.35 159481[108:Spt:159480.0,159475.0,159477.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.35 159482[108:Spt:159480.0,159475.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.35 159486[108:Res:159482.0,61.1] always3(s21) || -> . % 76.16/76.35 159487[108:SSi:159486.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.35 159488[106:Spt:159487.0,158844.0,158845.0] || until2p7(s20)*+ -> . % 76.16/76.35 159489[106:Spt:159487.0,158844.1] || -> node4(s19)*. % 76.16/76.35 159491[106:MRR:861.0,159489.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.35 159494[106:Res:53.1,159491.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.35 159499[107:Spt:159494.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 159501[107:Res:159499.0,61.1] always3(s19) || -> . % 76.16/76.35 159502[107:SSi:159501.0,78151.0,78154.0,137741.0,158843.0,159489.0] || -> . % 76.16/76.35 159503[107:Spt:159502.0,159494.0,159499.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.35 159504[107:Spt:159502.0,159494.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.35 159508[107:Res:159504.0,61.1] always3(s20) || -> . % 76.16/76.35 159509[107:SSi:159508.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.35 159510[105:Spt:159509.0,158842.0,158843.0] || until2p7(s19)*+ -> . % 76.16/76.35 159511[105:Spt:159509.0,158842.1] || -> node4(s18)*. % 76.16/76.35 159513[105:MRR:864.0,159511.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.35 159516[105:Res:53.1,159513.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.35 159518[106:Spt:159516.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 159520[106:Res:159518.0,61.1] always3(s18) || -> . % 76.16/76.35 159521[106:SSi:159520.0,78146.0,78150.0,137740.0,158841.0,159511.0] || -> . % 76.16/76.35 159522[106:Spt:159521.0,159516.0,159518.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.35 159523[106:Spt:159521.0,159516.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.35 159527[106:Res:159523.0,61.1] always3(s19) || -> . % 76.16/76.35 159528[106:SSi:159527.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.35 159529[104:Spt:159528.0,158840.0,158841.0] || until2p7(s18)*+ -> . % 76.16/76.35 159530[104:Spt:159528.0,158840.1] || -> node4(s17)*. % 76.16/76.35 159532[104:MRR:867.0,159530.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.35 159535[104:Res:53.1,159532.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.35 159537[105:Spt:159535.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 159539[105:Res:159537.0,61.1] always3(s17) || -> . % 76.16/76.35 159540[105:SSi:159539.0,78142.0,78145.0,137739.0,158839.0,159530.0] || -> . % 76.16/76.35 159541[105:Spt:159540.0,159535.0,159537.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.35 159542[105:Spt:159540.0,159535.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.35 159546[105:Res:159542.0,61.1] always3(s18) || -> . % 76.16/76.35 159547[105:SSi:159546.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.35 159548[103:Spt:159547.0,158838.0,158839.0] || until2p7(s17)*+ -> . % 76.16/76.35 159549[103:Spt:159547.0,158838.1] || -> node4(s16)*. % 76.16/76.35 159551[103:MRR:870.0,159549.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.35 159554[103:Res:53.1,159551.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.35 159556[104:Spt:159554.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 159558[104:Res:159556.0,61.1] always3(s16) || -> . % 76.16/76.35 159559[104:SSi:159558.0,78137.0,78141.0,137738.0,158837.0,159549.0] || -> . % 76.16/76.35 159560[104:Spt:159559.0,159554.0,159556.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.35 159561[104:Spt:159559.0,159554.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.35 159565[104:Res:159561.0,61.1] always3(s17) || -> . % 76.16/76.35 159566[104:SSi:159565.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.35 159567[102:Spt:159566.0,158836.0,158837.0] || until2p7(s16)*+ -> . % 76.16/76.35 159568[102:Spt:159566.0,158836.1] || -> node4(s15)*. % 76.16/76.35 159570[102:MRR:873.0,159568.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.35 159573[102:Res:53.1,159570.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.35 159578[103:Spt:159573.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 159580[103:Res:159578.0,61.1] always3(s15) || -> . % 76.16/76.35 159581[103:SSi:159580.0,78133.0,78136.0,137737.0,158835.0,159568.0] || -> . % 76.16/76.35 159582[103:Spt:159581.0,159573.0,159578.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.35 159583[103:Spt:159581.0,159573.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.35 159587[103:Res:159583.0,61.1] always3(s16) || -> . % 76.16/76.35 159588[103:SSi:159587.0,78137.0,78141.0,137738.0] || -> . % 76.16/76.35 159589[101:Spt:159588.0,158834.0,158835.0] || until2p7(s15)*+ -> . % 76.16/76.35 159590[101:Spt:159588.0,158834.1] || -> node4(s14)*. % 76.16/76.35 159592[101:MRR:876.0,159590.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.35 159595[101:Res:53.1,159592.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.35 159597[102:Spt:159595.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.35 159599[102:Res:159597.0,61.1] always3(s14) || -> . % 76.16/76.35 159600[102:SSi:159599.0,78128.0,78132.0,137736.0,158833.0,159590.0] || -> . % 76.16/76.35 159601[102:Spt:159600.0,159595.0,159597.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.35 159602[102:Spt:159600.0,159595.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.35 159606[102:Res:159602.0,61.1] always3(s15) || -> . % 76.16/76.35 159607[102:SSi:159606.0,78133.0,78136.0,137737.0] || -> . % 76.16/76.35 159608[100:Spt:159607.0,158832.0,158833.0] || until2p7(s14)*+ -> . % 76.16/76.35 159609[100:Spt:159607.0,158832.1] || -> node4(s13)*. % 76.16/76.35 159611[100:MRR:879.0,159609.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.35 159614[100:Res:53.1,159611.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.35 159616[101:Spt:159614.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.35 159618[101:Res:159616.0,61.1] always3(s13) || -> . % 76.16/76.35 159619[101:SSi:159618.0,78124.0,78127.0,137735.0,158831.0,159609.0] || -> . % 76.16/76.35 159620[101:Spt:159619.0,159614.0,159616.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.36 159621[101:Spt:159619.0,159614.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.36 159625[101:Res:159621.0,61.1] always3(s14) || -> . % 76.16/76.36 159626[101:SSi:159625.0,78128.0,78132.0,137736.0] || -> . % 76.16/76.36 159627[99:Spt:159626.0,158830.0,158831.0] || until2p7(s13)*+ -> . % 76.16/76.36 159628[99:Spt:159626.0,158830.1] || -> node4(s12)*. % 76.16/76.36 159630[99:MRR:882.0,159628.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.36 159633[99:Res:53.1,159630.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.36 159635[100:Spt:159633.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.36 159637[100:Res:159635.0,61.1] always3(s12) || -> . % 76.16/76.36 159638[100:SSi:159637.0,78119.0,78123.0,137734.0,158829.0,159628.0] || -> . % 76.16/76.36 159639[100:Spt:159638.0,159633.0,159635.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.36 159640[100:Spt:159638.0,159633.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.36 159644[100:Res:159640.0,61.1] always3(s13) || -> . % 76.16/76.36 159645[100:SSi:159644.0,78124.0,78127.0,137735.0] || -> . % 76.16/76.36 159646[98:Spt:159645.0,158828.0,158829.0] || until2p7(s12)*+ -> . % 76.16/76.36 159647[98:Spt:159645.0,158828.1] || -> node4(s11)*. % 76.16/76.36 159649[98:MRR:885.0,159647.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.36 159652[98:Res:53.1,159649.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.36 159657[99:Spt:159652.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.36 159659[99:Res:159657.0,61.1] always3(s11) || -> . % 76.16/76.36 159660[99:SSi:159659.0,78115.0,78118.0,137733.0,158827.0,159647.0] || -> . % 76.16/76.36 159661[99:Spt:159660.0,159652.0,159657.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.36 159662[99:Spt:159660.0,159652.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.36 159666[99:Res:159662.0,61.1] always3(s12) || -> . % 76.16/76.36 159667[99:SSi:159666.0,78119.0,78123.0,137734.0] || -> . % 76.16/76.36 159668[97:Spt:159667.0,158826.0,158827.0] || until2p7(s11)*+ -> . % 76.16/76.36 159669[97:Spt:159667.0,158826.1] || -> node4(s10)*. % 76.16/76.36 159671[97:MRR:888.0,159669.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.36 159674[97:Res:53.1,159671.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.36 159676[98:Spt:159674.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.36 159678[98:Res:159676.0,61.1] always3(s10) || -> . % 76.16/76.36 159679[98:SSi:159678.0,78110.0,78114.0,137732.0,158825.0,159669.0] || -> . % 76.16/76.36 159680[98:Spt:159679.0,159674.0,159676.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.36 159681[98:Spt:159679.0,159674.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.36 159685[98:Res:159681.0,61.1] always3(s11) || -> . % 76.16/76.36 159686[98:SSi:159685.0,78115.0,78118.0,137733.0] || -> . % 76.16/76.36 159687[96:Spt:159686.0,158824.0,158825.0] || until2p7(s10)*+ -> . % 76.16/76.36 159688[96:Spt:159686.0,158824.1] || -> node4(s9)*. % 76.16/76.36 159690[96:MRR:891.0,159688.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.36 159693[96:Res:53.1,159690.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.36 159695[96:MRR:159693.0,158814.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.36 159697[96:Res:159695.0,61.1] always3(s10) || -> . % 76.16/76.36 159698[96:SSi:159697.0,78110.0,78114.0,137732.0] || -> . % 76.16/76.36 159699[94:Spt:159698.0,158665.0,158668.0] || trans(s49,s9)*+ -> . % 76.16/76.36 159700[94:Spt:159698.0,158665.1,158665.2,158665.3,158665.4,158665.5] || -> trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.36 159702[94:MRR:158667.1,159699.0] xuntil6(s49) || -> trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.36 159703[95:Spt:159700.0] || -> trans(s49,s8)*. % 76.16/76.36 159704[95:Res:159703.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s8)*. % 76.16/76.36 159706[95:Res:159703.0,60.0] || -> node2(s49,s8)*. % 76.16/76.36 159707[95:SSi:159704.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s8)*. % 76.16/76.36 159708[95:Res:159706.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)*. % 76.16/76.36 159845[95:SoR:159708.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)*. % 76.16/76.36 159847[95:SoR:159845.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)* xuntil6(s49). % 76.16/76.36 159848[95:SSi:159847.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s8,c_busy)* xuntil6(s49). % 76.16/76.36 159849[96:Spt:159848.1] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.36 159851[96:Res:159849.0,61.1] always3(s8) || -> . % 76.16/76.36 159852[96:SSi:159851.0,78101.0,78105.0,137730.0] || -> . % 76.16/76.36 159853[96:Spt:159852.0,159848.1,159849.0] || m_main_v_state(s8,c_busy)*+ -> . % 76.16/76.36 159854[96:Spt:159852.0,159848.0,159848.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 159858[96:MRR:159845.2,159853.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 159859[96:Res:53.1,159854.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 159861[96:MRR:159859.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 159862[96:MRR:159707.0,159861.0] || -> until2p7(s8)*. % 76.16/76.36 159863[96:MRR:204.0,159862.0] || -> until2p7(s9)* node4(s8). % 76.16/76.36 159864[97:Spt:159863.0] || -> until2p7(s9)*. % 76.16/76.36 159865[97:MRR:205.0,159864.0] || -> until2p7(s10)* node4(s9). % 76.16/76.36 159866[98:Spt:159865.0] || -> until2p7(s10)*. % 76.16/76.36 159867[98:MRR:206.0,159866.0] || -> until2p7(s11)* node4(s10). % 76.16/76.36 159868[99:Spt:159867.0] || -> until2p7(s11)*. % 76.16/76.36 159869[99:MRR:207.0,159868.0] || -> until2p7(s12)* node4(s11). % 76.16/76.36 159870[100:Spt:159869.0] || -> until2p7(s12)*. % 76.16/76.36 159871[100:MRR:208.0,159870.0] || -> until2p7(s13)* node4(s12). % 76.16/76.36 159872[101:Spt:159871.0] || -> until2p7(s13)*. % 76.16/76.36 159873[101:MRR:209.0,159872.0] || -> until2p7(s14)* node4(s13). % 76.16/76.36 159874[102:Spt:159873.0] || -> until2p7(s14)*. % 76.16/76.36 159875[102:MRR:210.0,159874.0] || -> until2p7(s15)* node4(s14). % 76.16/76.36 159876[103:Spt:159875.0] || -> until2p7(s15)*. % 76.16/76.36 159877[103:MRR:211.0,159876.0] || -> until2p7(s16)* node4(s15). % 76.16/76.36 159878[104:Spt:159877.0] || -> until2p7(s16)*. % 76.16/76.36 159879[104:MRR:212.0,159878.0] || -> until2p7(s17)* node4(s16). % 76.16/76.36 159880[105:Spt:159879.0] || -> until2p7(s17)*. % 76.16/76.36 159881[105:MRR:213.0,159880.0] || -> until2p7(s18)* node4(s17). % 76.16/76.36 159882[106:Spt:159881.0] || -> until2p7(s18)*. % 76.16/76.36 159883[106:MRR:214.0,159882.0] || -> until2p7(s19)* node4(s18). % 76.16/76.36 159884[107:Spt:159883.0] || -> until2p7(s19)*. % 76.16/76.36 159885[107:MRR:215.0,159884.0] || -> until2p7(s20)* node4(s19). % 76.16/76.36 159886[108:Spt:159885.0] || -> until2p7(s20)*. % 76.16/76.36 159887[108:MRR:216.0,159886.0] || -> until2p7(s21)* node4(s20). % 76.16/76.36 159888[109:Spt:159887.0] || -> until2p7(s21)*. % 76.16/76.36 159889[109:MRR:217.0,159888.0] || -> until2p7(s22)* node4(s21). % 76.16/76.36 159890[110:Spt:159889.0] || -> until2p7(s22)*. % 76.16/76.36 159891[110:MRR:218.0,159890.0] || -> until2p7(s23)* node4(s22). % 76.16/76.36 159892[111:Spt:159891.0] || -> until2p7(s23)*. % 76.16/76.36 159893[111:MRR:219.0,159892.0] || -> until2p7(s24)* node4(s23). % 76.16/76.36 159894[112:Spt:159893.0] || -> until2p7(s24)*. % 76.16/76.36 159895[112:MRR:220.0,159894.0] || -> until2p7(s25)* node4(s24). % 76.16/76.36 159896[113:Spt:159895.0] || -> until2p7(s25)*. % 76.16/76.36 159897[113:MRR:221.0,159896.0] || -> until2p7(s26)* node4(s25). % 76.16/76.36 159898[114:Spt:159897.0] || -> until2p7(s26)*. % 76.16/76.36 159899[114:MRR:222.0,159898.0] || -> until2p7(s27)* node4(s26). % 76.16/76.36 159900[115:Spt:159899.0] || -> until2p7(s27)*. % 76.16/76.36 159901[115:MRR:223.0,159900.0] || -> until2p7(s28)* node4(s27). % 76.16/76.36 159902[116:Spt:159901.0] || -> until2p7(s28)*. % 76.16/76.36 159903[116:MRR:224.0,159902.0] || -> until2p7(s29)* node4(s28). % 76.16/76.36 159904[117:Spt:159903.0] || -> until2p7(s29)*. % 76.16/76.36 159905[117:MRR:225.0,159904.0] || -> until2p7(s30)* node4(s29). % 76.16/76.36 159906[118:Spt:159905.0] || -> until2p7(s30)*. % 76.16/76.36 159907[118:MRR:226.0,159906.0] || -> until2p7(s31)* node4(s30). % 76.16/76.36 159908[119:Spt:159907.0] || -> until2p7(s31)*. % 76.16/76.36 159909[119:MRR:227.0,159908.0] || -> until2p7(s32)* node4(s31). % 76.16/76.36 159910[120:Spt:159909.0] || -> until2p7(s32)*. % 76.16/76.36 159911[120:MRR:228.0,159910.0] || -> until2p7(s33)* node4(s32). % 76.16/76.36 159912[121:Spt:159911.0] || -> until2p7(s33)*. % 76.16/76.36 159913[121:MRR:229.0,159912.0] || -> until2p7(s34)* node4(s33). % 76.16/76.36 159914[122:Spt:159913.0] || -> until2p7(s34)*. % 76.16/76.36 159915[122:MRR:230.0,159914.0] || -> until2p7(s35)* node4(s34). % 76.16/76.36 159916[123:Spt:159915.0] || -> until2p7(s35)*. % 76.16/76.36 159917[123:MRR:231.0,159916.0] || -> until2p7(s36)* node4(s35). % 76.16/76.36 159918[124:Spt:159917.0] || -> until2p7(s36)*. % 76.16/76.36 159919[124:MRR:232.0,159918.0] || -> until2p7(s37)* node4(s36). % 76.16/76.36 159920[125:Spt:159919.0] || -> until2p7(s37)*. % 76.16/76.36 159921[125:MRR:235.0,159920.0] || -> until2p7(s38)* node4(s37). % 76.16/76.36 159922[126:Spt:159921.0] || -> until2p7(s38)*. % 76.16/76.36 159923[126:MRR:236.0,159922.0] || -> until2p7(s39)* node4(s38). % 76.16/76.36 159924[127:Spt:159923.0] || -> until2p7(s39)*. % 76.16/76.36 159925[127:MRR:237.0,159924.0] || -> until2p7(s40)* node4(s39). % 76.16/76.36 159926[128:Spt:159925.0] || -> until2p7(s40)*. % 76.16/76.36 159927[128:MRR:238.0,159926.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 159928[129:Spt:159927.0] || -> until2p7(s41)*. % 76.16/76.36 159929[129:MRR:239.0,159928.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 159930[130:Spt:159929.0] || -> until2p7(s42)*. % 76.16/76.36 159931[130:MRR:240.0,159930.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 159932[131:Spt:159931.0] || -> until2p7(s43)*. % 76.16/76.36 159933[131:MRR:241.0,159932.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 159934[132:Spt:159933.0] || -> until2p7(s44)*. % 76.16/76.36 159935[132:MRR:539.0,159934.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 159936[133:Spt:159935.0] || -> until2p7(s45)*. % 76.16/76.36 159937[133:MRR:544.0,159936.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 159938[134:Spt:159937.0] || -> until2p7(s46)*. % 76.16/76.36 159939[134:MRR:549.0,159938.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 159940[135:Spt:159939.0] || -> until2p7(s47)*. % 76.16/76.36 159941[135:MRR:554.0,159940.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 159942[136:Spt:159941.0] || -> until2p7(s48)*. % 76.16/76.36 159943[136:MRR:559.0,159942.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 159944[137:Spt:159943.0] || -> until2p7(s49)*. % 76.16/76.36 159945[137:MRR:194.0,159944.0] || -> node4(s49)*. % 76.16/76.36 159946[137:MRR:159858.0,159945.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 159950[137:Res:53.1,159946.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 159952[137:MRR:159950.0,78381.0] || -> . % 76.16/76.36 159953[137:Spt:159952.0,159943.0,159944.0] || until2p7(s49)*+ -> . % 76.16/76.36 159954[137:Spt:159952.0,159943.1] || -> node4(s48)*. % 76.16/76.36 159955[137:MRR:78384.0,159954.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 159958[137:Res:53.1,159955.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 159961[137:Res:159958.0,61.1] always3(s48) || -> . % 76.16/76.36 159962[137:SSi:159961.0,78281.0,78387.0,137770.0,159942.0,159954.0] || -> . % 76.16/76.36 159963[136:Spt:159962.0,159941.0,159942.0] || until2p7(s48)*+ -> . % 76.16/76.36 159964[136:Spt:159962.0,159941.1] || -> node4(s47)*. % 76.16/76.36 159966[136:MRR:777.0,159964.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 159978[136:Res:53.1,159966.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 159980[137:Spt:159978.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 159982[137:Res:159980.0,61.1] always3(s47) || -> . % 76.16/76.36 159983[137:SSi:159982.0,78277.0,78280.0,137769.0,159940.0,159964.0] || -> . % 76.16/76.36 159984[137:Spt:159983.0,159978.0,159980.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 159985[137:Spt:159983.0,159978.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 159989[137:Res:159985.0,61.1] always3(s48) || -> . % 76.16/76.36 159990[137:SSi:159989.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.36 159991[135:Spt:159990.0,159939.0,159940.0] || until2p7(s47)*+ -> . % 76.16/76.36 159992[135:Spt:159990.0,159939.1] || -> node4(s46)*. % 76.16/76.36 159994[135:MRR:780.0,159992.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 160001[135:Res:53.1,159994.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 160006[136:Spt:160001.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 160008[136:Res:160006.0,61.1] always3(s46) || -> . % 76.16/76.36 160009[136:SSi:160008.0,78272.0,78276.0,137768.0,159938.0,159992.0] || -> . % 76.16/76.36 160010[136:Spt:160009.0,160001.0,160006.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 160011[136:Spt:160009.0,160001.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 160015[136:Res:160011.0,61.1] always3(s47) || -> . % 76.16/76.36 160016[136:SSi:160015.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.36 160017[134:Spt:160016.0,159937.0,159938.0] || until2p7(s46)*+ -> . % 76.16/76.36 160018[134:Spt:160016.0,159937.1] || -> node4(s45)*. % 76.16/76.36 160020[134:MRR:783.0,160018.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 160023[134:Res:53.1,160020.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 160025[135:Spt:160023.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 160027[135:Res:160025.0,61.1] always3(s45) || -> . % 76.16/76.36 160028[135:SSi:160027.0,78268.0,78271.0,137767.0,159936.0,160018.0] || -> . % 76.16/76.36 160029[135:Spt:160028.0,160023.0,160025.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 160030[135:Spt:160028.0,160023.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 160034[135:Res:160030.0,61.1] always3(s46) || -> . % 76.16/76.36 160035[135:SSi:160034.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.36 160036[133:Spt:160035.0,159935.0,159936.0] || until2p7(s45)*+ -> . % 76.16/76.36 160037[133:Spt:160035.0,159935.1] || -> node4(s44)*. % 76.16/76.36 160039[133:MRR:786.0,160037.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 160042[133:Res:53.1,160039.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 160044[134:Spt:160042.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 160046[134:Res:160044.0,61.1] always3(s44) || -> . % 76.16/76.36 160047[134:SSi:160046.0,78263.0,78267.0,137766.0,159934.0,160037.0] || -> . % 76.16/76.36 160048[134:Spt:160047.0,160042.0,160044.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 160049[134:Spt:160047.0,160042.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 160053[134:Res:160049.0,61.1] always3(s45) || -> . % 76.16/76.36 160054[134:SSi:160053.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.36 160055[132:Spt:160054.0,159933.0,159934.0] || until2p7(s44)*+ -> . % 76.16/76.36 160056[132:Spt:160054.0,159933.1] || -> node4(s43)*. % 76.16/76.36 160058[132:MRR:789.0,160056.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 160061[132:Res:53.1,160058.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 160063[133:Spt:160061.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 160065[133:Res:160063.0,61.1] always3(s43) || -> . % 76.16/76.36 160066[133:SSi:160065.0,78259.0,78262.0,137765.0,159932.0,160056.0] || -> . % 76.16/76.36 160067[133:Spt:160066.0,160061.0,160063.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 160068[133:Spt:160066.0,160061.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 160072[133:Res:160068.0,61.1] always3(s44) || -> . % 76.16/76.36 160073[133:SSi:160072.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.36 160074[131:Spt:160073.0,159931.0,159932.0] || until2p7(s43)*+ -> . % 76.16/76.36 160075[131:Spt:160073.0,159931.1] || -> node4(s42)*. % 76.16/76.36 160077[131:MRR:792.0,160075.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 160080[131:Res:53.1,160077.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 160085[132:Spt:160080.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 160087[132:Res:160085.0,61.1] always3(s42) || -> . % 76.16/76.36 160088[132:SSi:160087.0,78254.0,78258.0,137764.0,159930.0,160075.0] || -> . % 76.16/76.36 160089[132:Spt:160088.0,160080.0,160085.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 160090[132:Spt:160088.0,160080.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 160094[132:Res:160090.0,61.1] always3(s43) || -> . % 76.16/76.36 160095[132:SSi:160094.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.36 160096[130:Spt:160095.0,159929.0,159930.0] || until2p7(s42)*+ -> . % 76.16/76.36 160097[130:Spt:160095.0,159929.1] || -> node4(s41)*. % 76.16/76.36 160099[130:MRR:795.0,160097.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 160102[130:Res:53.1,160099.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 160104[131:Spt:160102.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 160106[131:Res:160104.0,61.1] always3(s41) || -> . % 76.16/76.36 160107[131:SSi:160106.0,78250.0,78253.0,137763.0,159928.0,160097.0] || -> . % 76.16/76.36 160108[131:Spt:160107.0,160102.0,160104.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 160109[131:Spt:160107.0,160102.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 160113[131:Res:160109.0,61.1] always3(s42) || -> . % 76.16/76.36 160114[131:SSi:160113.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.36 160115[129:Spt:160114.0,159927.0,159928.0] || until2p7(s41)*+ -> . % 76.16/76.36 160116[129:Spt:160114.0,159927.1] || -> node4(s40)*. % 76.16/76.36 160118[129:MRR:798.0,160116.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 160121[129:Res:53.1,160118.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 160123[130:Spt:160121.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 160125[130:Res:160123.0,61.1] always3(s40) || -> . % 76.16/76.36 160126[130:SSi:160125.0,78245.0,78249.0,137762.0,159926.0,160116.0] || -> . % 76.16/76.36 160127[130:Spt:160126.0,160121.0,160123.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.36 160128[130:Spt:160126.0,160121.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 160132[130:Res:160128.0,61.1] always3(s41) || -> . % 76.16/76.36 160133[130:SSi:160132.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.36 160134[128:Spt:160133.0,159925.0,159926.0] || until2p7(s40)*+ -> . % 76.16/76.36 160135[128:Spt:160133.0,159925.1] || -> node4(s39)*. % 76.16/76.36 160137[128:MRR:801.0,160135.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.36 160140[128:Res:53.1,160137.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.36 160142[129:Spt:160140.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 160144[129:Res:160142.0,61.1] always3(s39) || -> . % 76.16/76.36 160145[129:SSi:160144.0,78241.0,78244.0,137761.0,159924.0,160135.0] || -> . % 76.16/76.36 160146[129:Spt:160145.0,160140.0,160142.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.36 160147[129:Spt:160145.0,160140.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 160151[129:Res:160147.0,61.1] always3(s40) || -> . % 76.16/76.36 160152[129:SSi:160151.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.36 160153[127:Spt:160152.0,159923.0,159924.0] || until2p7(s39)*+ -> . % 76.16/76.36 160154[127:Spt:160152.0,159923.1] || -> node4(s38)*. % 76.16/76.36 160156[127:MRR:804.0,160154.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.36 160159[127:Res:53.1,160156.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.36 160164[128:Spt:160159.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 160166[128:Res:160164.0,61.1] always3(s38) || -> . % 76.16/76.36 160167[128:SSi:160166.0,78236.0,78240.0,137760.0,159922.0,160154.0] || -> . % 76.16/76.36 160168[128:Spt:160167.0,160159.0,160164.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.36 160169[128:Spt:160167.0,160159.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 160173[128:Res:160169.0,61.1] always3(s39) || -> . % 76.16/76.36 160174[128:SSi:160173.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.36 160175[126:Spt:160174.0,159921.0,159922.0] || until2p7(s38)*+ -> . % 76.16/76.36 160176[126:Spt:160174.0,159921.1] || -> node4(s37)*. % 76.16/76.36 160178[126:MRR:807.0,160176.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.36 160181[126:Res:53.1,160178.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.36 160183[127:Spt:160181.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 160185[127:Res:160183.0,61.1] always3(s37) || -> . % 76.16/76.36 160186[127:SSi:160185.0,78232.0,78235.0,137759.0,159920.0,160176.0] || -> . % 76.16/76.36 160187[127:Spt:160186.0,160181.0,160183.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.36 160188[127:Spt:160186.0,160181.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 160192[127:Res:160188.0,61.1] always3(s38) || -> . % 76.16/76.36 160193[127:SSi:160192.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.36 160194[125:Spt:160193.0,159919.0,159920.0] || until2p7(s37)*+ -> . % 76.16/76.36 160195[125:Spt:160193.0,159919.1] || -> node4(s36)*. % 76.16/76.36 160197[125:MRR:810.0,160195.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.36 160200[125:Res:53.1,160197.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.36 160202[126:Spt:160200.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 160204[126:Res:160202.0,61.1] always3(s36) || -> . % 76.16/76.36 160205[126:SSi:160204.0,78227.0,78231.0,137758.0,159918.0,160195.0] || -> . % 76.16/76.36 160206[126:Spt:160205.0,160200.0,160202.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.36 160207[126:Spt:160205.0,160200.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 160211[126:Res:160207.0,61.1] always3(s37) || -> . % 76.16/76.36 160212[126:SSi:160211.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.36 160213[124:Spt:160212.0,159917.0,159918.0] || until2p7(s36)*+ -> . % 76.16/76.36 160214[124:Spt:160212.0,159917.1] || -> node4(s35)*. % 76.16/76.36 160216[124:MRR:813.0,160214.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.36 160219[124:Res:53.1,160216.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.36 160221[125:Spt:160219.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 160223[125:Res:160221.0,61.1] always3(s35) || -> . % 76.16/76.36 160224[125:SSi:160223.0,78223.0,78226.0,137757.0,159916.0,160214.0] || -> . % 76.16/76.36 160225[125:Spt:160224.0,160219.0,160221.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.36 160226[125:Spt:160224.0,160219.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 160230[125:Res:160226.0,61.1] always3(s36) || -> . % 76.16/76.36 160231[125:SSi:160230.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.36 160232[123:Spt:160231.0,159915.0,159916.0] || until2p7(s35)*+ -> . % 76.16/76.36 160233[123:Spt:160231.0,159915.1] || -> node4(s34)*. % 76.16/76.36 160235[123:MRR:816.0,160233.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.36 160238[123:Res:53.1,160235.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.36 160243[124:Spt:160238.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 160245[124:Res:160243.0,61.1] always3(s34) || -> . % 76.16/76.36 160246[124:SSi:160245.0,78218.0,78222.0,137756.0,159914.0,160233.0] || -> . % 76.16/76.36 160247[124:Spt:160246.0,160238.0,160243.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.36 160248[124:Spt:160246.0,160238.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 160252[124:Res:160248.0,61.1] always3(s35) || -> . % 76.16/76.36 160253[124:SSi:160252.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.36 160254[122:Spt:160253.0,159913.0,159914.0] || until2p7(s34)*+ -> . % 76.16/76.36 160255[122:Spt:160253.0,159913.1] || -> node4(s33)*. % 76.16/76.36 160257[122:MRR:819.0,160255.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.36 160260[122:Res:53.1,160257.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.36 160262[123:Spt:160260.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.36 160264[123:Res:160262.0,61.1] always3(s33) || -> . % 76.16/76.36 160265[123:SSi:160264.0,78214.0,78217.0,137755.0,159912.0,160255.0] || -> . % 76.16/76.36 160266[123:Spt:160265.0,160260.0,160262.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.36 160267[123:Spt:160265.0,160260.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 160271[123:Res:160267.0,61.1] always3(s34) || -> . % 76.16/76.36 160272[123:SSi:160271.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.36 160273[121:Spt:160272.0,159911.0,159912.0] || until2p7(s33)*+ -> . % 76.16/76.36 160274[121:Spt:160272.0,159911.1] || -> node4(s32)*. % 76.16/76.36 160276[121:MRR:822.0,160274.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.36 160279[121:Res:53.1,160276.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.36 160281[122:Spt:160279.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.36 160283[122:Res:160281.0,61.1] always3(s32) || -> . % 76.16/76.36 160284[122:SSi:160283.0,78209.0,78213.0,137754.0,159910.0,160274.0] || -> . % 76.16/76.36 160285[122:Spt:160284.0,160279.0,160281.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.36 160286[122:Spt:160284.0,160279.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.36 160290[122:Res:160286.0,61.1] always3(s33) || -> . % 76.16/76.36 160291[122:SSi:160290.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.36 160292[120:Spt:160291.0,159909.0,159910.0] || until2p7(s32)*+ -> . % 76.16/76.36 160293[120:Spt:160291.0,159909.1] || -> node4(s31)*. % 76.16/76.36 160295[120:MRR:825.0,160293.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.36 160298[120:Res:53.1,160295.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.36 160300[121:Spt:160298.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.36 160302[121:Res:160300.0,61.1] always3(s31) || -> . % 76.16/76.36 160303[121:SSi:160302.0,78205.0,78208.0,137753.0,159908.0,160293.0] || -> . % 76.16/76.36 160304[121:Spt:160303.0,160298.0,160300.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.36 160305[121:Spt:160303.0,160298.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.36 160309[121:Res:160305.0,61.1] always3(s32) || -> . % 76.16/76.36 160310[121:SSi:160309.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.36 160311[119:Spt:160310.0,159907.0,159908.0] || until2p7(s31)*+ -> . % 76.16/76.36 160312[119:Spt:160310.0,159907.1] || -> node4(s30)*. % 76.16/76.36 160314[119:MRR:828.0,160312.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.36 160317[119:Res:53.1,160314.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.36 160322[120:Spt:160317.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.36 160324[120:Res:160322.0,61.1] always3(s30) || -> . % 76.16/76.36 160325[120:SSi:160324.0,78200.0,78204.0,137752.0,159906.0,160312.0] || -> . % 76.16/76.36 160326[120:Spt:160325.0,160317.0,160322.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.36 160327[120:Spt:160325.0,160317.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.36 160331[120:Res:160327.0,61.1] always3(s31) || -> . % 76.16/76.36 160332[120:SSi:160331.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.36 160333[118:Spt:160332.0,159905.0,159906.0] || until2p7(s30)*+ -> . % 76.16/76.36 160334[118:Spt:160332.0,159905.1] || -> node4(s29)*. % 76.16/76.36 160336[118:MRR:831.0,160334.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.36 160339[118:Res:53.1,160336.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.36 160341[119:Spt:160339.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.36 160343[119:Res:160341.0,61.1] always3(s29) || -> . % 76.16/76.36 160344[119:SSi:160343.0,78196.0,78199.0,137751.0,159904.0,160334.0] || -> . % 76.16/76.36 160345[119:Spt:160344.0,160339.0,160341.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.36 160346[119:Spt:160344.0,160339.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.36 160350[119:Res:160346.0,61.1] always3(s30) || -> . % 76.16/76.36 160351[119:SSi:160350.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.36 160352[117:Spt:160351.0,159903.0,159904.0] || until2p7(s29)*+ -> . % 76.16/76.36 160353[117:Spt:160351.0,159903.1] || -> node4(s28)*. % 76.16/76.36 160355[117:MRR:834.0,160353.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.36 160358[117:Res:53.1,160355.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.36 160360[118:Spt:160358.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.36 160362[118:Res:160360.0,61.1] always3(s28) || -> . % 76.16/76.36 160363[118:SSi:160362.0,78191.0,78195.0,137750.0,159902.0,160353.0] || -> . % 76.16/76.36 160364[118:Spt:160363.0,160358.0,160360.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.36 160365[118:Spt:160363.0,160358.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.36 160369[118:Res:160365.0,61.1] always3(s29) || -> . % 76.16/76.36 160370[118:SSi:160369.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.36 160371[116:Spt:160370.0,159901.0,159902.0] || until2p7(s28)*+ -> . % 76.16/76.36 160372[116:Spt:160370.0,159901.1] || -> node4(s27)*. % 76.16/76.36 160374[116:MRR:837.0,160372.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.36 160377[116:Res:53.1,160374.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.36 160379[117:Spt:160377.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.36 160381[117:Res:160379.0,61.1] always3(s27) || -> . % 76.16/76.36 160382[117:SSi:160381.0,78187.0,78190.0,137749.0,159900.0,160372.0] || -> . % 76.16/76.36 160383[117:Spt:160382.0,160377.0,160379.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.36 160384[117:Spt:160382.0,160377.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.36 160388[117:Res:160384.0,61.1] always3(s28) || -> . % 76.16/76.36 160389[117:SSi:160388.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.36 160390[115:Spt:160389.0,159899.0,159900.0] || until2p7(s27)*+ -> . % 76.16/76.36 160391[115:Spt:160389.0,159899.1] || -> node4(s26)*. % 76.16/76.36 160393[115:MRR:840.0,160391.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.36 160396[115:Res:53.1,160393.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.36 160401[116:Spt:160396.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.36 160403[116:Res:160401.0,61.1] always3(s26) || -> . % 76.16/76.36 160404[116:SSi:160403.0,78182.0,78186.0,137748.0,159898.0,160391.0] || -> . % 76.16/76.36 160405[116:Spt:160404.0,160396.0,160401.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.36 160406[116:Spt:160404.0,160396.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.36 160410[116:Res:160406.0,61.1] always3(s27) || -> . % 76.16/76.36 160411[116:SSi:160410.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.36 160412[114:Spt:160411.0,159897.0,159898.0] || until2p7(s26)*+ -> . % 76.16/76.36 160413[114:Spt:160411.0,159897.1] || -> node4(s25)*. % 76.16/76.36 160415[114:MRR:843.0,160413.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.36 160418[114:Res:53.1,160415.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.36 160420[115:Spt:160418.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.36 160422[115:Res:160420.0,61.1] always3(s25) || -> . % 76.16/76.36 160423[115:SSi:160422.0,78178.0,78181.0,137747.0,159896.0,160413.0] || -> . % 76.16/76.36 160424[115:Spt:160423.0,160418.0,160420.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.36 160425[115:Spt:160423.0,160418.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.36 160429[115:Res:160425.0,61.1] always3(s26) || -> . % 76.16/76.36 160430[115:SSi:160429.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.36 160431[113:Spt:160430.0,159895.0,159896.0] || until2p7(s25)*+ -> . % 76.16/76.36 160432[113:Spt:160430.0,159895.1] || -> node4(s24)*. % 76.16/76.36 160434[113:MRR:846.0,160432.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.36 160437[113:Res:53.1,160434.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.36 160439[114:Spt:160437.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.36 160441[114:Res:160439.0,61.1] always3(s24) || -> . % 76.16/76.36 160442[114:SSi:160441.0,78173.0,78177.0,137746.0,159894.0,160432.0] || -> . % 76.16/76.36 160443[114:Spt:160442.0,160437.0,160439.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.36 160444[114:Spt:160442.0,160437.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.36 160448[114:Res:160444.0,61.1] always3(s25) || -> . % 76.16/76.36 160449[114:SSi:160448.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.36 160450[112:Spt:160449.0,159893.0,159894.0] || until2p7(s24)*+ -> . % 76.16/76.36 160451[112:Spt:160449.0,159893.1] || -> node4(s23)*. % 76.16/76.36 160453[112:MRR:849.0,160451.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.36 160456[112:Res:53.1,160453.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.36 160458[113:Spt:160456.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.36 160460[113:Res:160458.0,61.1] always3(s23) || -> . % 76.16/76.36 160461[113:SSi:160460.0,78169.0,78172.0,137745.0,159892.0,160451.0] || -> . % 76.16/76.36 160462[113:Spt:160461.0,160456.0,160458.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.36 160463[113:Spt:160461.0,160456.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.36 160467[113:Res:160463.0,61.1] always3(s24) || -> . % 76.16/76.36 160468[113:SSi:160467.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.36 160469[111:Spt:160468.0,159891.0,159892.0] || until2p7(s23)*+ -> . % 76.16/76.36 160470[111:Spt:160468.0,159891.1] || -> node4(s22)*. % 76.16/76.36 160472[111:MRR:852.0,160470.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.36 160475[111:Res:53.1,160472.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.36 160480[112:Spt:160475.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.36 160482[112:Res:160480.0,61.1] always3(s22) || -> . % 76.16/76.36 160483[112:SSi:160482.0,78164.0,78168.0,137744.0,159890.0,160470.0] || -> . % 76.16/76.36 160484[112:Spt:160483.0,160475.0,160480.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.36 160485[112:Spt:160483.0,160475.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.36 160489[112:Res:160485.0,61.1] always3(s23) || -> . % 76.16/76.36 160490[112:SSi:160489.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.36 160491[110:Spt:160490.0,159889.0,159890.0] || until2p7(s22)*+ -> . % 76.16/76.36 160492[110:Spt:160490.0,159889.1] || -> node4(s21)*. % 76.16/76.36 160494[110:MRR:855.0,160492.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.36 160497[110:Res:53.1,160494.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.36 160499[111:Spt:160497.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.36 160501[111:Res:160499.0,61.1] always3(s21) || -> . % 76.16/76.36 160502[111:SSi:160501.0,78160.0,78163.0,137743.0,159888.0,160492.0] || -> . % 76.16/76.36 160503[111:Spt:160502.0,160497.0,160499.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.36 160504[111:Spt:160502.0,160497.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.36 160508[111:Res:160504.0,61.1] always3(s22) || -> . % 76.16/76.36 160509[111:SSi:160508.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.36 160510[109:Spt:160509.0,159887.0,159888.0] || until2p7(s21)*+ -> . % 76.16/76.36 160511[109:Spt:160509.0,159887.1] || -> node4(s20)*. % 76.16/76.36 160513[109:MRR:858.0,160511.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.36 160516[109:Res:53.1,160513.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.36 160518[110:Spt:160516.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.36 160520[110:Res:160518.0,61.1] always3(s20) || -> . % 76.16/76.36 160521[110:SSi:160520.0,78155.0,78159.0,137742.0,159886.0,160511.0] || -> . % 76.16/76.36 160522[110:Spt:160521.0,160516.0,160518.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.36 160523[110:Spt:160521.0,160516.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.36 160527[110:Res:160523.0,61.1] always3(s21) || -> . % 76.16/76.36 160528[110:SSi:160527.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.36 160529[108:Spt:160528.0,159885.0,159886.0] || until2p7(s20)*+ -> . % 76.16/76.36 160530[108:Spt:160528.0,159885.1] || -> node4(s19)*. % 76.16/76.36 160532[108:MRR:861.0,160530.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.36 160535[108:Res:53.1,160532.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.36 160537[109:Spt:160535.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.36 160539[109:Res:160537.0,61.1] always3(s19) || -> . % 76.16/76.36 160540[109:SSi:160539.0,78151.0,78154.0,137741.0,159884.0,160530.0] || -> . % 76.16/76.36 160541[109:Spt:160540.0,160535.0,160537.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.36 160542[109:Spt:160540.0,160535.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.36 160546[109:Res:160542.0,61.1] always3(s20) || -> . % 76.16/76.36 160547[109:SSi:160546.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.36 160548[107:Spt:160547.0,159883.0,159884.0] || until2p7(s19)*+ -> . % 76.16/76.36 160549[107:Spt:160547.0,159883.1] || -> node4(s18)*. % 76.16/76.36 160551[107:MRR:864.0,160549.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.36 160554[107:Res:53.1,160551.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.36 160559[108:Spt:160554.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.36 160561[108:Res:160559.0,61.1] always3(s18) || -> . % 76.16/76.36 160562[108:SSi:160561.0,78146.0,78150.0,137740.0,159882.0,160549.0] || -> . % 76.16/76.36 160563[108:Spt:160562.0,160554.0,160559.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.36 160564[108:Spt:160562.0,160554.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.36 160568[108:Res:160564.0,61.1] always3(s19) || -> . % 76.16/76.36 160569[108:SSi:160568.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.36 160570[106:Spt:160569.0,159881.0,159882.0] || until2p7(s18)*+ -> . % 76.16/76.36 160571[106:Spt:160569.0,159881.1] || -> node4(s17)*. % 76.16/76.36 160573[106:MRR:867.0,160571.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.36 160576[106:Res:53.1,160573.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.36 160578[107:Spt:160576.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.36 160580[107:Res:160578.0,61.1] always3(s17) || -> . % 76.16/76.36 160581[107:SSi:160580.0,78142.0,78145.0,137739.0,159880.0,160571.0] || -> . % 76.16/76.36 160582[107:Spt:160581.0,160576.0,160578.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.36 160583[107:Spt:160581.0,160576.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.36 160587[107:Res:160583.0,61.1] always3(s18) || -> . % 76.16/76.36 160588[107:SSi:160587.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.36 160589[105:Spt:160588.0,159879.0,159880.0] || until2p7(s17)*+ -> . % 76.16/76.36 160590[105:Spt:160588.0,159879.1] || -> node4(s16)*. % 76.16/76.36 160592[105:MRR:870.0,160590.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.36 160595[105:Res:53.1,160592.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.36 160597[106:Spt:160595.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.36 160599[106:Res:160597.0,61.1] always3(s16) || -> . % 76.16/76.36 160600[106:SSi:160599.0,78137.0,78141.0,137738.0,159878.0,160590.0] || -> . % 76.16/76.36 160601[106:Spt:160600.0,160595.0,160597.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.36 160602[106:Spt:160600.0,160595.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.36 160606[106:Res:160602.0,61.1] always3(s17) || -> . % 76.16/76.36 160607[106:SSi:160606.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.36 160608[104:Spt:160607.0,159877.0,159878.0] || until2p7(s16)*+ -> . % 76.16/76.36 160609[104:Spt:160607.0,159877.1] || -> node4(s15)*. % 76.16/76.36 160611[104:MRR:873.0,160609.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.36 160614[104:Res:53.1,160611.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.36 160616[105:Spt:160614.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.36 160618[105:Res:160616.0,61.1] always3(s15) || -> . % 76.16/76.36 160619[105:SSi:160618.0,78133.0,78136.0,137737.0,159876.0,160609.0] || -> . % 76.16/76.36 160620[105:Spt:160619.0,160614.0,160616.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.36 160621[105:Spt:160619.0,160614.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.36 160625[105:Res:160621.0,61.1] always3(s16) || -> . % 76.16/76.36 160626[105:SSi:160625.0,78137.0,78141.0,137738.0] || -> . % 76.16/76.36 160627[103:Spt:160626.0,159875.0,159876.0] || until2p7(s15)*+ -> . % 76.16/76.36 160628[103:Spt:160626.0,159875.1] || -> node4(s14)*. % 76.16/76.36 160630[103:MRR:876.0,160628.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.36 160633[103:Res:53.1,160630.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.36 160638[104:Spt:160633.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.36 160640[104:Res:160638.0,61.1] always3(s14) || -> . % 76.16/76.36 160641[104:SSi:160640.0,78128.0,78132.0,137736.0,159874.0,160628.0] || -> . % 76.16/76.36 160642[104:Spt:160641.0,160633.0,160638.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.36 160643[104:Spt:160641.0,160633.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.36 160647[104:Res:160643.0,61.1] always3(s15) || -> . % 76.16/76.36 160648[104:SSi:160647.0,78133.0,78136.0,137737.0] || -> . % 76.16/76.36 160649[102:Spt:160648.0,159873.0,159874.0] || until2p7(s14)*+ -> . % 76.16/76.36 160650[102:Spt:160648.0,159873.1] || -> node4(s13)*. % 76.16/76.36 160652[102:MRR:879.0,160650.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.36 160655[102:Res:53.1,160652.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.36 160657[103:Spt:160655.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.36 160659[103:Res:160657.0,61.1] always3(s13) || -> . % 76.16/76.36 160660[103:SSi:160659.0,78124.0,78127.0,137735.0,159872.0,160650.0] || -> . % 76.16/76.36 160661[103:Spt:160660.0,160655.0,160657.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.36 160662[103:Spt:160660.0,160655.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.36 160666[103:Res:160662.0,61.1] always3(s14) || -> . % 76.16/76.36 160667[103:SSi:160666.0,78128.0,78132.0,137736.0] || -> . % 76.16/76.36 160668[101:Spt:160667.0,159871.0,159872.0] || until2p7(s13)*+ -> . % 76.16/76.36 160669[101:Spt:160667.0,159871.1] || -> node4(s12)*. % 76.16/76.36 160671[101:MRR:882.0,160669.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.36 160674[101:Res:53.1,160671.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.36 160676[102:Spt:160674.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.36 160678[102:Res:160676.0,61.1] always3(s12) || -> . % 76.16/76.36 160679[102:SSi:160678.0,78119.0,78123.0,137734.0,159870.0,160669.0] || -> . % 76.16/76.36 160680[102:Spt:160679.0,160674.0,160676.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.36 160681[102:Spt:160679.0,160674.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.36 160685[102:Res:160681.0,61.1] always3(s13) || -> . % 76.16/76.36 160686[102:SSi:160685.0,78124.0,78127.0,137735.0] || -> . % 76.16/76.36 160687[100:Spt:160686.0,159869.0,159870.0] || until2p7(s12)*+ -> . % 76.16/76.36 160688[100:Spt:160686.0,159869.1] || -> node4(s11)*. % 76.16/76.36 160690[100:MRR:885.0,160688.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.36 160693[100:Res:53.1,160690.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.36 160695[101:Spt:160693.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.36 160697[101:Res:160695.0,61.1] always3(s11) || -> . % 76.16/76.36 160698[101:SSi:160697.0,78115.0,78118.0,137733.0,159868.0,160688.0] || -> . % 76.16/76.36 160699[101:Spt:160698.0,160693.0,160695.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.36 160700[101:Spt:160698.0,160693.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.36 160704[101:Res:160700.0,61.1] always3(s12) || -> . % 76.16/76.36 160705[101:SSi:160704.0,78119.0,78123.0,137734.0] || -> . % 76.16/76.36 160706[99:Spt:160705.0,159867.0,159868.0] || until2p7(s11)*+ -> . % 76.16/76.36 160707[99:Spt:160705.0,159867.1] || -> node4(s10)*. % 76.16/76.36 160709[99:MRR:888.0,160707.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.36 160712[99:Res:53.1,160709.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.36 160717[100:Spt:160712.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.36 160719[100:Res:160717.0,61.1] always3(s10) || -> . % 76.16/76.36 160720[100:SSi:160719.0,78110.0,78114.0,137732.0,159866.0,160707.0] || -> . % 76.16/76.36 160721[100:Spt:160720.0,160712.0,160717.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.36 160722[100:Spt:160720.0,160712.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.36 160726[100:Res:160722.0,61.1] always3(s11) || -> . % 76.16/76.36 160727[100:SSi:160726.0,78115.0,78118.0,137733.0] || -> . % 76.16/76.36 160728[98:Spt:160727.0,159865.0,159866.0] || until2p7(s10)*+ -> . % 76.16/76.36 160729[98:Spt:160727.0,159865.1] || -> node4(s9)*. % 76.16/76.36 160731[98:MRR:891.0,160729.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.36 160734[98:Res:53.1,160731.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.36 160736[99:Spt:160734.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.36 160738[99:Res:160736.0,61.1] always3(s9) || -> . % 76.16/76.36 160739[99:SSi:160738.0,78106.0,78109.0,137731.0,159864.0,160729.0] || -> . % 76.16/76.36 160740[99:Spt:160739.0,160734.0,160736.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.36 160741[99:Spt:160739.0,160734.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.36 160745[99:Res:160741.0,61.1] always3(s10) || -> . % 76.16/76.36 160746[99:SSi:160745.0,78110.0,78114.0,137732.0] || -> . % 76.16/76.36 160747[97:Spt:160746.0,159863.0,159864.0] || until2p7(s9)*+ -> . % 76.16/76.36 160748[97:Spt:160746.0,159863.1] || -> node4(s8)*. % 76.16/76.36 160750[97:MRR:894.0,160748.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.36 160753[97:Res:53.1,160750.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.36 160755[97:MRR:160753.0,159853.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.36 160757[97:Res:160755.0,61.1] always3(s9) || -> . % 76.16/76.36 160758[97:SSi:160757.0,78106.0,78109.0,137731.0] || -> . % 76.16/76.36 160759[95:Spt:160758.0,159700.0,159703.0] || trans(s49,s8)*+ -> . % 76.16/76.36 160760[95:Spt:160758.0,159700.1,159700.2,159700.3,159700.4] || -> trans(s49,s7) trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.36 160762[95:MRR:159702.1,160759.0] xuntil6(s49) || -> trans(s49,s7) trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.36 160763[96:Spt:160760.0] || -> trans(s49,s7)*. % 76.16/76.36 160764[96:Res:160763.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s7)*. % 76.16/76.36 160766[96:Res:160763.0,60.0] || -> node2(s49,s7)*. % 76.16/76.36 160767[96:SSi:160764.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s7)*. % 76.16/76.36 160768[96:Res:160766.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)*. % 76.16/76.36 160909[96:SoR:160768.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)*. % 76.16/76.36 160911[96:SoR:160909.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)* xuntil6(s49). % 76.16/76.36 160912[96:SSi:160911.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s7,c_busy)* xuntil6(s49). % 76.16/76.36 160913[97:Spt:160912.1] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.36 160915[97:Res:160913.0,61.1] always3(s7) || -> . % 76.16/76.36 160916[97:SSi:160915.0,78097.0,78100.0,137729.0] || -> . % 76.16/76.36 160917[97:Spt:160916.0,160912.1,160913.0] || m_main_v_state(s7,c_busy)*+ -> . % 76.16/76.36 160918[97:Spt:160916.0,160912.0,160912.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 160922[97:MRR:160909.2,160917.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 160923[97:Res:53.1,160918.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 160925[97:MRR:160923.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 160926[97:MRR:160767.0,160925.0] || -> until2p7(s7)*. % 76.16/76.36 160927[97:MRR:203.0,160926.0] || -> until2p7(s8)* node4(s7). % 76.16/76.36 160928[98:Spt:160927.0] || -> until2p7(s8)*. % 76.16/76.36 160929[98:MRR:204.0,160928.0] || -> until2p7(s9)* node4(s8). % 76.16/76.36 160930[99:Spt:160929.0] || -> until2p7(s9)*. % 76.16/76.36 160931[99:MRR:205.0,160930.0] || -> until2p7(s10)* node4(s9). % 76.16/76.36 160932[100:Spt:160931.0] || -> until2p7(s10)*. % 76.16/76.36 160933[100:MRR:206.0,160932.0] || -> until2p7(s11)* node4(s10). % 76.16/76.36 160934[101:Spt:160933.0] || -> until2p7(s11)*. % 76.16/76.36 160935[101:MRR:207.0,160934.0] || -> until2p7(s12)* node4(s11). % 76.16/76.36 160936[102:Spt:160935.0] || -> until2p7(s12)*. % 76.16/76.36 160937[102:MRR:208.0,160936.0] || -> until2p7(s13)* node4(s12). % 76.16/76.36 160938[103:Spt:160937.0] || -> until2p7(s13)*. % 76.16/76.36 160939[103:MRR:209.0,160938.0] || -> until2p7(s14)* node4(s13). % 76.16/76.36 160940[104:Spt:160939.0] || -> until2p7(s14)*. % 76.16/76.36 160941[104:MRR:210.0,160940.0] || -> until2p7(s15)* node4(s14). % 76.16/76.36 160942[105:Spt:160941.0] || -> until2p7(s15)*. % 76.16/76.36 160943[105:MRR:211.0,160942.0] || -> until2p7(s16)* node4(s15). % 76.16/76.36 160944[106:Spt:160943.0] || -> until2p7(s16)*. % 76.16/76.36 160945[106:MRR:212.0,160944.0] || -> until2p7(s17)* node4(s16). % 76.16/76.36 160946[107:Spt:160945.0] || -> until2p7(s17)*. % 76.16/76.36 160947[107:MRR:213.0,160946.0] || -> until2p7(s18)* node4(s17). % 76.16/76.36 160948[108:Spt:160947.0] || -> until2p7(s18)*. % 76.16/76.36 160949[108:MRR:214.0,160948.0] || -> until2p7(s19)* node4(s18). % 76.16/76.36 160950[109:Spt:160949.0] || -> until2p7(s19)*. % 76.16/76.36 160951[109:MRR:215.0,160950.0] || -> until2p7(s20)* node4(s19). % 76.16/76.36 160952[110:Spt:160951.0] || -> until2p7(s20)*. % 76.16/76.36 160953[110:MRR:216.0,160952.0] || -> until2p7(s21)* node4(s20). % 76.16/76.36 160954[111:Spt:160953.0] || -> until2p7(s21)*. % 76.16/76.36 160955[111:MRR:217.0,160954.0] || -> until2p7(s22)* node4(s21). % 76.16/76.36 160956[112:Spt:160955.0] || -> until2p7(s22)*. % 76.16/76.36 160957[112:MRR:218.0,160956.0] || -> until2p7(s23)* node4(s22). % 76.16/76.36 160958[113:Spt:160957.0] || -> until2p7(s23)*. % 76.16/76.36 160959[113:MRR:219.0,160958.0] || -> until2p7(s24)* node4(s23). % 76.16/76.36 160960[114:Spt:160959.0] || -> until2p7(s24)*. % 76.16/76.36 160961[114:MRR:220.0,160960.0] || -> until2p7(s25)* node4(s24). % 76.16/76.36 160962[115:Spt:160961.0] || -> until2p7(s25)*. % 76.16/76.36 160963[115:MRR:221.0,160962.0] || -> until2p7(s26)* node4(s25). % 76.16/76.36 160964[116:Spt:160963.0] || -> until2p7(s26)*. % 76.16/76.36 160965[116:MRR:222.0,160964.0] || -> until2p7(s27)* node4(s26). % 76.16/76.36 160966[117:Spt:160965.0] || -> until2p7(s27)*. % 76.16/76.36 160967[117:MRR:223.0,160966.0] || -> until2p7(s28)* node4(s27). % 76.16/76.36 160968[118:Spt:160967.0] || -> until2p7(s28)*. % 76.16/76.36 160969[118:MRR:224.0,160968.0] || -> until2p7(s29)* node4(s28). % 76.16/76.36 160970[119:Spt:160969.0] || -> until2p7(s29)*. % 76.16/76.36 160971[119:MRR:225.0,160970.0] || -> until2p7(s30)* node4(s29). % 76.16/76.36 160972[120:Spt:160971.0] || -> until2p7(s30)*. % 76.16/76.36 160973[120:MRR:226.0,160972.0] || -> until2p7(s31)* node4(s30). % 76.16/76.36 160974[121:Spt:160973.0] || -> until2p7(s31)*. % 76.16/76.36 160975[121:MRR:227.0,160974.0] || -> until2p7(s32)* node4(s31). % 76.16/76.36 160976[122:Spt:160975.0] || -> until2p7(s32)*. % 76.16/76.36 160977[122:MRR:228.0,160976.0] || -> until2p7(s33)* node4(s32). % 76.16/76.36 160978[123:Spt:160977.0] || -> until2p7(s33)*. % 76.16/76.36 160979[123:MRR:229.0,160978.0] || -> until2p7(s34)* node4(s33). % 76.16/76.36 160980[124:Spt:160979.0] || -> until2p7(s34)*. % 76.16/76.36 160981[124:MRR:230.0,160980.0] || -> until2p7(s35)* node4(s34). % 76.16/76.36 160982[125:Spt:160981.0] || -> until2p7(s35)*. % 76.16/76.36 160983[125:MRR:231.0,160982.0] || -> until2p7(s36)* node4(s35). % 76.16/76.36 160984[126:Spt:160983.0] || -> until2p7(s36)*. % 76.16/76.36 160985[126:MRR:232.0,160984.0] || -> until2p7(s37)* node4(s36). % 76.16/76.36 160986[127:Spt:160985.0] || -> until2p7(s37)*. % 76.16/76.36 160987[127:MRR:235.0,160986.0] || -> until2p7(s38)* node4(s37). % 76.16/76.36 160988[128:Spt:160987.0] || -> until2p7(s38)*. % 76.16/76.36 160989[128:MRR:236.0,160988.0] || -> until2p7(s39)* node4(s38). % 76.16/76.36 160990[129:Spt:160989.0] || -> until2p7(s39)*. % 76.16/76.36 160991[129:MRR:237.0,160990.0] || -> until2p7(s40)* node4(s39). % 76.16/76.36 160992[130:Spt:160991.0] || -> until2p7(s40)*. % 76.16/76.36 160993[130:MRR:238.0,160992.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 160994[131:Spt:160993.0] || -> until2p7(s41)*. % 76.16/76.36 160995[131:MRR:239.0,160994.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 160996[132:Spt:160995.0] || -> until2p7(s42)*. % 76.16/76.36 160997[132:MRR:240.0,160996.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 160998[133:Spt:160997.0] || -> until2p7(s43)*. % 76.16/76.36 160999[133:MRR:241.0,160998.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 161000[134:Spt:160999.0] || -> until2p7(s44)*. % 76.16/76.36 161001[134:MRR:539.0,161000.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 161002[135:Spt:161001.0] || -> until2p7(s45)*. % 76.16/76.36 161003[135:MRR:544.0,161002.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 161004[136:Spt:161003.0] || -> until2p7(s46)*. % 76.16/76.36 161005[136:MRR:549.0,161004.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 161006[137:Spt:161005.0] || -> until2p7(s47)*. % 76.16/76.36 161007[137:MRR:554.0,161006.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 161008[138:Spt:161007.0] || -> until2p7(s48)*. % 76.16/76.36 161009[138:MRR:559.0,161008.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 161010[139:Spt:161009.0] || -> until2p7(s49)*. % 76.16/76.36 161011[139:MRR:194.0,161010.0] || -> node4(s49)*. % 76.16/76.36 161012[139:MRR:160922.0,161011.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 161013[139:Res:53.1,161012.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 161015[139:MRR:161013.0,78381.0] || -> . % 76.16/76.36 161016[139:Spt:161015.0,161009.0,161010.0] || until2p7(s49)*+ -> . % 76.16/76.36 161017[139:Spt:161015.0,161009.1] || -> node4(s48)*. % 76.16/76.36 161018[139:MRR:78384.0,161017.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 161021[139:Res:53.1,161018.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 161024[139:Res:161021.0,61.1] always3(s48) || -> . % 76.16/76.36 161025[139:SSi:161024.0,78281.0,78387.0,137770.0,161008.0,161017.0] || -> . % 76.16/76.36 161026[138:Spt:161025.0,161007.0,161008.0] || until2p7(s48)*+ -> . % 76.16/76.36 161027[138:Spt:161025.0,161007.1] || -> node4(s47)*. % 76.16/76.36 161029[138:MRR:777.0,161027.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 161044[138:Res:53.1,161029.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 161049[139:Spt:161044.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 161051[139:Res:161049.0,61.1] always3(s47) || -> . % 76.16/76.36 161052[139:SSi:161051.0,78277.0,78280.0,137769.0,161006.0,161027.0] || -> . % 76.16/76.36 161053[139:Spt:161052.0,161044.0,161049.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 161054[139:Spt:161052.0,161044.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 161058[139:Res:161054.0,61.1] always3(s48) || -> . % 76.16/76.36 161059[139:SSi:161058.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.36 161060[137:Spt:161059.0,161005.0,161006.0] || until2p7(s47)*+ -> . % 76.16/76.36 161061[137:Spt:161059.0,161005.1] || -> node4(s46)*. % 76.16/76.36 161063[137:MRR:780.0,161061.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 161070[137:Res:53.1,161063.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 161072[138:Spt:161070.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 161074[138:Res:161072.0,61.1] always3(s46) || -> . % 76.16/76.36 161075[138:SSi:161074.0,78272.0,78276.0,137768.0,161004.0,161061.0] || -> . % 76.16/76.36 161076[138:Spt:161075.0,161070.0,161072.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 161077[138:Spt:161075.0,161070.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 161081[138:Res:161077.0,61.1] always3(s47) || -> . % 76.16/76.36 161082[138:SSi:161081.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.36 161083[136:Spt:161082.0,161003.0,161004.0] || until2p7(s46)*+ -> . % 76.16/76.36 161084[136:Spt:161082.0,161003.1] || -> node4(s45)*. % 76.16/76.36 161086[136:MRR:783.0,161084.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 161089[136:Res:53.1,161086.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 161094[137:Spt:161089.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 161096[137:Res:161094.0,61.1] always3(s45) || -> . % 76.16/76.36 161097[137:SSi:161096.0,78268.0,78271.0,137767.0,161002.0,161084.0] || -> . % 76.16/76.36 161098[137:Spt:161097.0,161089.0,161094.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 161099[137:Spt:161097.0,161089.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 161103[137:Res:161099.0,61.1] always3(s46) || -> . % 76.16/76.36 161104[137:SSi:161103.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.36 161105[135:Spt:161104.0,161001.0,161002.0] || until2p7(s45)*+ -> . % 76.16/76.36 161106[135:Spt:161104.0,161001.1] || -> node4(s44)*. % 76.16/76.36 161108[135:MRR:786.0,161106.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 161111[135:Res:53.1,161108.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 161113[136:Spt:161111.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 161115[136:Res:161113.0,61.1] always3(s44) || -> . % 76.16/76.36 161116[136:SSi:161115.0,78263.0,78267.0,137766.0,161000.0,161106.0] || -> . % 76.16/76.36 161117[136:Spt:161116.0,161111.0,161113.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 161118[136:Spt:161116.0,161111.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 161122[136:Res:161118.0,61.1] always3(s45) || -> . % 76.16/76.36 161123[136:SSi:161122.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.36 161124[134:Spt:161123.0,160999.0,161000.0] || until2p7(s44)*+ -> . % 76.16/76.36 161125[134:Spt:161123.0,160999.1] || -> node4(s43)*. % 76.16/76.36 161127[134:MRR:789.0,161125.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 161130[134:Res:53.1,161127.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 161132[135:Spt:161130.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 161134[135:Res:161132.0,61.1] always3(s43) || -> . % 76.16/76.36 161135[135:SSi:161134.0,78259.0,78262.0,137765.0,160998.0,161125.0] || -> . % 76.16/76.36 161136[135:Spt:161135.0,161130.0,161132.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 161137[135:Spt:161135.0,161130.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 161141[135:Res:161137.0,61.1] always3(s44) || -> . % 76.16/76.36 161142[135:SSi:161141.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.36 161143[133:Spt:161142.0,160997.0,160998.0] || until2p7(s43)*+ -> . % 76.16/76.36 161144[133:Spt:161142.0,160997.1] || -> node4(s42)*. % 76.16/76.36 161146[133:MRR:792.0,161144.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 161149[133:Res:53.1,161146.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 161151[134:Spt:161149.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 161153[134:Res:161151.0,61.1] always3(s42) || -> . % 76.16/76.36 161154[134:SSi:161153.0,78254.0,78258.0,137764.0,160996.0,161144.0] || -> . % 76.16/76.36 161155[134:Spt:161154.0,161149.0,161151.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 161156[134:Spt:161154.0,161149.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 161160[134:Res:161156.0,61.1] always3(s43) || -> . % 76.16/76.36 161161[134:SSi:161160.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.36 161162[132:Spt:161161.0,160995.0,160996.0] || until2p7(s42)*+ -> . % 76.16/76.36 161163[132:Spt:161161.0,160995.1] || -> node4(s41)*. % 76.16/76.36 161165[132:MRR:795.0,161163.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 161168[132:Res:53.1,161165.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 161173[133:Spt:161168.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 161175[133:Res:161173.0,61.1] always3(s41) || -> . % 76.16/76.36 161176[133:SSi:161175.0,78250.0,78253.0,137763.0,160994.0,161163.0] || -> . % 76.16/76.36 161177[133:Spt:161176.0,161168.0,161173.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 161178[133:Spt:161176.0,161168.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 161182[133:Res:161178.0,61.1] always3(s42) || -> . % 76.16/76.36 161183[133:SSi:161182.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.36 161184[131:Spt:161183.0,160993.0,160994.0] || until2p7(s41)*+ -> . % 76.16/76.36 161185[131:Spt:161183.0,160993.1] || -> node4(s40)*. % 76.16/76.36 161187[131:MRR:798.0,161185.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 161190[131:Res:53.1,161187.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 161192[132:Spt:161190.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 161194[132:Res:161192.0,61.1] always3(s40) || -> . % 76.16/76.36 161195[132:SSi:161194.0,78245.0,78249.0,137762.0,160992.0,161185.0] || -> . % 76.16/76.36 161196[132:Spt:161195.0,161190.0,161192.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.36 161197[132:Spt:161195.0,161190.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 161201[132:Res:161197.0,61.1] always3(s41) || -> . % 76.16/76.36 161202[132:SSi:161201.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.36 161203[130:Spt:161202.0,160991.0,160992.0] || until2p7(s40)*+ -> . % 76.16/76.36 161204[130:Spt:161202.0,160991.1] || -> node4(s39)*. % 76.16/76.36 161206[130:MRR:801.0,161204.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.36 161209[130:Res:53.1,161206.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.36 161211[131:Spt:161209.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 161213[131:Res:161211.0,61.1] always3(s39) || -> . % 76.16/76.36 161214[131:SSi:161213.0,78241.0,78244.0,137761.0,160990.0,161204.0] || -> . % 76.16/76.36 161215[131:Spt:161214.0,161209.0,161211.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.36 161216[131:Spt:161214.0,161209.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 161220[131:Res:161216.0,61.1] always3(s40) || -> . % 76.16/76.36 161221[131:SSi:161220.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.36 161222[129:Spt:161221.0,160989.0,160990.0] || until2p7(s39)*+ -> . % 76.16/76.36 161223[129:Spt:161221.0,160989.1] || -> node4(s38)*. % 76.16/76.36 161225[129:MRR:804.0,161223.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.36 161228[129:Res:53.1,161225.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.36 161230[130:Spt:161228.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 161232[130:Res:161230.0,61.1] always3(s38) || -> . % 76.16/76.36 161233[130:SSi:161232.0,78236.0,78240.0,137760.0,160988.0,161223.0] || -> . % 76.16/76.36 161234[130:Spt:161233.0,161228.0,161230.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.36 161235[130:Spt:161233.0,161228.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 161239[130:Res:161235.0,61.1] always3(s39) || -> . % 76.16/76.36 161240[130:SSi:161239.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.36 161241[128:Spt:161240.0,160987.0,160988.0] || until2p7(s38)*+ -> . % 76.16/76.36 161242[128:Spt:161240.0,160987.1] || -> node4(s37)*. % 76.16/76.36 161244[128:MRR:807.0,161242.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.36 161247[128:Res:53.1,161244.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.36 161252[129:Spt:161247.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 161254[129:Res:161252.0,61.1] always3(s37) || -> . % 76.16/76.36 161255[129:SSi:161254.0,78232.0,78235.0,137759.0,160986.0,161242.0] || -> . % 76.16/76.36 161256[129:Spt:161255.0,161247.0,161252.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.36 161257[129:Spt:161255.0,161247.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 161261[129:Res:161257.0,61.1] always3(s38) || -> . % 76.16/76.36 161262[129:SSi:161261.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.36 161263[127:Spt:161262.0,160985.0,160986.0] || until2p7(s37)*+ -> . % 76.16/76.36 161264[127:Spt:161262.0,160985.1] || -> node4(s36)*. % 76.16/76.36 161266[127:MRR:810.0,161264.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.36 161269[127:Res:53.1,161266.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.36 161271[128:Spt:161269.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 161273[128:Res:161271.0,61.1] always3(s36) || -> . % 76.16/76.36 161274[128:SSi:161273.0,78227.0,78231.0,137758.0,160984.0,161264.0] || -> . % 76.16/76.36 161275[128:Spt:161274.0,161269.0,161271.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.36 161276[128:Spt:161274.0,161269.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 161280[128:Res:161276.0,61.1] always3(s37) || -> . % 76.16/76.36 161281[128:SSi:161280.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.36 161282[126:Spt:161281.0,160983.0,160984.0] || until2p7(s36)*+ -> . % 76.16/76.36 161283[126:Spt:161281.0,160983.1] || -> node4(s35)*. % 76.16/76.36 161285[126:MRR:813.0,161283.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.36 161288[126:Res:53.1,161285.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.36 161290[127:Spt:161288.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 161292[127:Res:161290.0,61.1] always3(s35) || -> . % 76.16/76.36 161293[127:SSi:161292.0,78223.0,78226.0,137757.0,160982.0,161283.0] || -> . % 76.16/76.36 161294[127:Spt:161293.0,161288.0,161290.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.36 161295[127:Spt:161293.0,161288.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 161299[127:Res:161295.0,61.1] always3(s36) || -> . % 76.16/76.36 161300[127:SSi:161299.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.36 161301[125:Spt:161300.0,160981.0,160982.0] || until2p7(s35)*+ -> . % 76.16/76.36 161302[125:Spt:161300.0,160981.1] || -> node4(s34)*. % 76.16/76.36 161304[125:MRR:816.0,161302.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.36 161307[125:Res:53.1,161304.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.36 161309[126:Spt:161307.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 161311[126:Res:161309.0,61.1] always3(s34) || -> . % 76.16/76.36 161312[126:SSi:161311.0,78218.0,78222.0,137756.0,160980.0,161302.0] || -> . % 76.16/76.36 161313[126:Spt:161312.0,161307.0,161309.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.36 161314[126:Spt:161312.0,161307.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 161318[126:Res:161314.0,61.1] always3(s35) || -> . % 76.16/76.36 161319[126:SSi:161318.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.36 161320[124:Spt:161319.0,160979.0,160980.0] || until2p7(s34)*+ -> . % 76.16/76.36 161321[124:Spt:161319.0,160979.1] || -> node4(s33)*. % 76.16/76.36 161323[124:MRR:819.0,161321.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.36 161326[124:Res:53.1,161323.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.36 161331[125:Spt:161326.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.36 161333[125:Res:161331.0,61.1] always3(s33) || -> . % 76.16/76.36 161334[125:SSi:161333.0,78214.0,78217.0,137755.0,160978.0,161321.0] || -> . % 76.16/76.36 161335[125:Spt:161334.0,161326.0,161331.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.36 161336[125:Spt:161334.0,161326.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 161340[125:Res:161336.0,61.1] always3(s34) || -> . % 76.16/76.36 161341[125:SSi:161340.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.36 161342[123:Spt:161341.0,160977.0,160978.0] || until2p7(s33)*+ -> . % 76.16/76.36 161343[123:Spt:161341.0,160977.1] || -> node4(s32)*. % 76.16/76.36 161345[123:MRR:822.0,161343.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.36 161348[123:Res:53.1,161345.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.36 161350[124:Spt:161348.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.36 161352[124:Res:161350.0,61.1] always3(s32) || -> . % 76.16/76.36 161353[124:SSi:161352.0,78209.0,78213.0,137754.0,160976.0,161343.0] || -> . % 76.16/76.36 161354[124:Spt:161353.0,161348.0,161350.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.36 161355[124:Spt:161353.0,161348.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.36 161359[124:Res:161355.0,61.1] always3(s33) || -> . % 76.16/76.36 161360[124:SSi:161359.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.36 161361[122:Spt:161360.0,160975.0,160976.0] || until2p7(s32)*+ -> . % 76.16/76.36 161362[122:Spt:161360.0,160975.1] || -> node4(s31)*. % 76.16/76.36 161364[122:MRR:825.0,161362.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.36 161367[122:Res:53.1,161364.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.36 161369[123:Spt:161367.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.36 161371[123:Res:161369.0,61.1] always3(s31) || -> . % 76.16/76.36 161372[123:SSi:161371.0,78205.0,78208.0,137753.0,160974.0,161362.0] || -> . % 76.16/76.36 161373[123:Spt:161372.0,161367.0,161369.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.36 161374[123:Spt:161372.0,161367.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.36 161378[123:Res:161374.0,61.1] always3(s32) || -> . % 76.16/76.36 161379[123:SSi:161378.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.36 161380[121:Spt:161379.0,160973.0,160974.0] || until2p7(s31)*+ -> . % 76.16/76.36 161381[121:Spt:161379.0,160973.1] || -> node4(s30)*. % 76.16/76.36 161383[121:MRR:828.0,161381.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.36 161386[121:Res:53.1,161383.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.36 161388[122:Spt:161386.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.36 161390[122:Res:161388.0,61.1] always3(s30) || -> . % 76.16/76.36 161391[122:SSi:161390.0,78200.0,78204.0,137752.0,160972.0,161381.0] || -> . % 76.16/76.36 161392[122:Spt:161391.0,161386.0,161388.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.36 161393[122:Spt:161391.0,161386.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.36 161397[122:Res:161393.0,61.1] always3(s31) || -> . % 76.16/76.36 161398[122:SSi:161397.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.36 161399[120:Spt:161398.0,160971.0,160972.0] || until2p7(s30)*+ -> . % 76.16/76.36 161400[120:Spt:161398.0,160971.1] || -> node4(s29)*. % 76.16/76.36 161402[120:MRR:831.0,161400.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.36 161405[120:Res:53.1,161402.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.36 161410[121:Spt:161405.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.36 161412[121:Res:161410.0,61.1] always3(s29) || -> . % 76.16/76.36 161413[121:SSi:161412.0,78196.0,78199.0,137751.0,160970.0,161400.0] || -> . % 76.16/76.36 161414[121:Spt:161413.0,161405.0,161410.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.36 161415[121:Spt:161413.0,161405.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.36 161419[121:Res:161415.0,61.1] always3(s30) || -> . % 76.16/76.36 161420[121:SSi:161419.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.36 161421[119:Spt:161420.0,160969.0,160970.0] || until2p7(s29)*+ -> . % 76.16/76.36 161422[119:Spt:161420.0,160969.1] || -> node4(s28)*. % 76.16/76.36 161424[119:MRR:834.0,161422.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.36 161427[119:Res:53.1,161424.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.36 161429[120:Spt:161427.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.36 161431[120:Res:161429.0,61.1] always3(s28) || -> . % 76.16/76.36 161432[120:SSi:161431.0,78191.0,78195.0,137750.0,160968.0,161422.0] || -> . % 76.16/76.36 161433[120:Spt:161432.0,161427.0,161429.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.36 161434[120:Spt:161432.0,161427.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.36 161438[120:Res:161434.0,61.1] always3(s29) || -> . % 76.16/76.36 161439[120:SSi:161438.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.36 161440[118:Spt:161439.0,160967.0,160968.0] || until2p7(s28)*+ -> . % 76.16/76.36 161441[118:Spt:161439.0,160967.1] || -> node4(s27)*. % 76.16/76.36 161443[118:MRR:837.0,161441.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.36 161446[118:Res:53.1,161443.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.36 161448[119:Spt:161446.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.36 161450[119:Res:161448.0,61.1] always3(s27) || -> . % 76.16/76.36 161451[119:SSi:161450.0,78187.0,78190.0,137749.0,160966.0,161441.0] || -> . % 76.16/76.36 161452[119:Spt:161451.0,161446.0,161448.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.36 161453[119:Spt:161451.0,161446.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.36 161457[119:Res:161453.0,61.1] always3(s28) || -> . % 76.16/76.36 161458[119:SSi:161457.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.36 161459[117:Spt:161458.0,160965.0,160966.0] || until2p7(s27)*+ -> . % 76.16/76.36 161460[117:Spt:161458.0,160965.1] || -> node4(s26)*. % 76.16/76.36 161462[117:MRR:840.0,161460.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.36 161465[117:Res:53.1,161462.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.36 161467[118:Spt:161465.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.36 161469[118:Res:161467.0,61.1] always3(s26) || -> . % 76.16/76.36 161470[118:SSi:161469.0,78182.0,78186.0,137748.0,160964.0,161460.0] || -> . % 76.16/76.36 161471[118:Spt:161470.0,161465.0,161467.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.36 161472[118:Spt:161470.0,161465.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.36 161476[118:Res:161472.0,61.1] always3(s27) || -> . % 76.16/76.36 161477[118:SSi:161476.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.36 161478[116:Spt:161477.0,160963.0,160964.0] || until2p7(s26)*+ -> . % 76.16/76.36 161479[116:Spt:161477.0,160963.1] || -> node4(s25)*. % 76.16/76.36 161481[116:MRR:843.0,161479.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.36 161484[116:Res:53.1,161481.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.36 161489[117:Spt:161484.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.36 161491[117:Res:161489.0,61.1] always3(s25) || -> . % 76.16/76.36 161492[117:SSi:161491.0,78178.0,78181.0,137747.0,160962.0,161479.0] || -> . % 76.16/76.36 161493[117:Spt:161492.0,161484.0,161489.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.36 161494[117:Spt:161492.0,161484.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.36 161498[117:Res:161494.0,61.1] always3(s26) || -> . % 76.16/76.36 161499[117:SSi:161498.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.36 161500[115:Spt:161499.0,160961.0,160962.0] || until2p7(s25)*+ -> . % 76.16/76.36 161501[115:Spt:161499.0,160961.1] || -> node4(s24)*. % 76.16/76.36 161503[115:MRR:846.0,161501.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.36 161506[115:Res:53.1,161503.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.36 161508[116:Spt:161506.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.36 161510[116:Res:161508.0,61.1] always3(s24) || -> . % 76.16/76.36 161511[116:SSi:161510.0,78173.0,78177.0,137746.0,160960.0,161501.0] || -> . % 76.16/76.36 161512[116:Spt:161511.0,161506.0,161508.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.36 161513[116:Spt:161511.0,161506.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.36 161517[116:Res:161513.0,61.1] always3(s25) || -> . % 76.16/76.36 161518[116:SSi:161517.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.36 161519[114:Spt:161518.0,160959.0,160960.0] || until2p7(s24)*+ -> . % 76.16/76.36 161520[114:Spt:161518.0,160959.1] || -> node4(s23)*. % 76.16/76.36 161522[114:MRR:849.0,161520.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.36 161525[114:Res:53.1,161522.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.36 161527[115:Spt:161525.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.36 161529[115:Res:161527.0,61.1] always3(s23) || -> . % 76.16/76.36 161530[115:SSi:161529.0,78169.0,78172.0,137745.0,160958.0,161520.0] || -> . % 76.16/76.36 161531[115:Spt:161530.0,161525.0,161527.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.36 161532[115:Spt:161530.0,161525.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.36 161536[115:Res:161532.0,61.1] always3(s24) || -> . % 76.16/76.36 161537[115:SSi:161536.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.36 161538[113:Spt:161537.0,160957.0,160958.0] || until2p7(s23)*+ -> . % 76.16/76.36 161539[113:Spt:161537.0,160957.1] || -> node4(s22)*. % 76.16/76.36 161541[113:MRR:852.0,161539.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.36 161544[113:Res:53.1,161541.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.36 161546[114:Spt:161544.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.36 161548[114:Res:161546.0,61.1] always3(s22) || -> . % 76.16/76.36 161549[114:SSi:161548.0,78164.0,78168.0,137744.0,160956.0,161539.0] || -> . % 76.16/76.36 161550[114:Spt:161549.0,161544.0,161546.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.36 161551[114:Spt:161549.0,161544.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.36 161555[114:Res:161551.0,61.1] always3(s23) || -> . % 76.16/76.36 161556[114:SSi:161555.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.36 161557[112:Spt:161556.0,160955.0,160956.0] || until2p7(s22)*+ -> . % 76.16/76.36 161558[112:Spt:161556.0,160955.1] || -> node4(s21)*. % 76.16/76.36 161560[112:MRR:855.0,161558.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.36 161563[112:Res:53.1,161560.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.36 161568[113:Spt:161563.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.36 161570[113:Res:161568.0,61.1] always3(s21) || -> . % 76.16/76.36 161571[113:SSi:161570.0,78160.0,78163.0,137743.0,160954.0,161558.0] || -> . % 76.16/76.36 161572[113:Spt:161571.0,161563.0,161568.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.36 161573[113:Spt:161571.0,161563.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.36 161577[113:Res:161573.0,61.1] always3(s22) || -> . % 76.16/76.36 161578[113:SSi:161577.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.36 161579[111:Spt:161578.0,160953.0,160954.0] || until2p7(s21)*+ -> . % 76.16/76.36 161580[111:Spt:161578.0,160953.1] || -> node4(s20)*. % 76.16/76.36 161582[111:MRR:858.0,161580.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.36 161585[111:Res:53.1,161582.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.36 161587[112:Spt:161585.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.36 161589[112:Res:161587.0,61.1] always3(s20) || -> . % 76.16/76.36 161590[112:SSi:161589.0,78155.0,78159.0,137742.0,160952.0,161580.0] || -> . % 76.16/76.36 161591[112:Spt:161590.0,161585.0,161587.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.36 161592[112:Spt:161590.0,161585.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.36 161596[112:Res:161592.0,61.1] always3(s21) || -> . % 76.16/76.36 161597[112:SSi:161596.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.36 161598[110:Spt:161597.0,160951.0,160952.0] || until2p7(s20)*+ -> . % 76.16/76.36 161599[110:Spt:161597.0,160951.1] || -> node4(s19)*. % 76.16/76.36 161601[110:MRR:861.0,161599.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.36 161604[110:Res:53.1,161601.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.36 161606[111:Spt:161604.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.36 161608[111:Res:161606.0,61.1] always3(s19) || -> . % 76.16/76.36 161609[111:SSi:161608.0,78151.0,78154.0,137741.0,160950.0,161599.0] || -> . % 76.16/76.36 161610[111:Spt:161609.0,161604.0,161606.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.36 161611[111:Spt:161609.0,161604.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.36 161615[111:Res:161611.0,61.1] always3(s20) || -> . % 76.16/76.36 161616[111:SSi:161615.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.36 161617[109:Spt:161616.0,160949.0,160950.0] || until2p7(s19)*+ -> . % 76.16/76.36 161618[109:Spt:161616.0,160949.1] || -> node4(s18)*. % 76.16/76.36 161620[109:MRR:864.0,161618.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.36 161623[109:Res:53.1,161620.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.36 161625[110:Spt:161623.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.36 161627[110:Res:161625.0,61.1] always3(s18) || -> . % 76.16/76.36 161628[110:SSi:161627.0,78146.0,78150.0,137740.0,160948.0,161618.0] || -> . % 76.16/76.36 161629[110:Spt:161628.0,161623.0,161625.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.36 161630[110:Spt:161628.0,161623.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.36 161634[110:Res:161630.0,61.1] always3(s19) || -> . % 76.16/76.36 161635[110:SSi:161634.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.36 161636[108:Spt:161635.0,160947.0,160948.0] || until2p7(s18)*+ -> . % 76.16/76.36 161637[108:Spt:161635.0,160947.1] || -> node4(s17)*. % 76.16/76.36 161639[108:MRR:867.0,161637.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.36 161642[108:Res:53.1,161639.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.36 161647[109:Spt:161642.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.36 161649[109:Res:161647.0,61.1] always3(s17) || -> . % 76.16/76.36 161650[109:SSi:161649.0,78142.0,78145.0,137739.0,160946.0,161637.0] || -> . % 76.16/76.36 161651[109:Spt:161650.0,161642.0,161647.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.36 161652[109:Spt:161650.0,161642.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.36 161656[109:Res:161652.0,61.1] always3(s18) || -> . % 76.16/76.36 161657[109:SSi:161656.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.36 161658[107:Spt:161657.0,160945.0,160946.0] || until2p7(s17)*+ -> . % 76.16/76.36 161659[107:Spt:161657.0,160945.1] || -> node4(s16)*. % 76.16/76.36 161661[107:MRR:870.0,161659.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.36 161664[107:Res:53.1,161661.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.36 161666[108:Spt:161664.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.36 161668[108:Res:161666.0,61.1] always3(s16) || -> . % 76.16/76.36 161669[108:SSi:161668.0,78137.0,78141.0,137738.0,160944.0,161659.0] || -> . % 76.16/76.36 161670[108:Spt:161669.0,161664.0,161666.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.36 161671[108:Spt:161669.0,161664.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.36 161675[108:Res:161671.0,61.1] always3(s17) || -> . % 76.16/76.36 161676[108:SSi:161675.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.36 161677[106:Spt:161676.0,160943.0,160944.0] || until2p7(s16)*+ -> . % 76.16/76.36 161678[106:Spt:161676.0,160943.1] || -> node4(s15)*. % 76.16/76.36 161680[106:MRR:873.0,161678.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.36 161683[106:Res:53.1,161680.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.36 161685[107:Spt:161683.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.36 161687[107:Res:161685.0,61.1] always3(s15) || -> . % 76.16/76.36 161688[107:SSi:161687.0,78133.0,78136.0,137737.0,160942.0,161678.0] || -> . % 76.16/76.36 161689[107:Spt:161688.0,161683.0,161685.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.36 161690[107:Spt:161688.0,161683.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.36 161694[107:Res:161690.0,61.1] always3(s16) || -> . % 76.16/76.36 161695[107:SSi:161694.0,78137.0,78141.0,137738.0] || -> . % 76.16/76.36 161696[105:Spt:161695.0,160941.0,160942.0] || until2p7(s15)*+ -> . % 76.16/76.36 161697[105:Spt:161695.0,160941.1] || -> node4(s14)*. % 76.16/76.36 161699[105:MRR:876.0,161697.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.36 161702[105:Res:53.1,161699.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.36 161704[106:Spt:161702.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.36 161706[106:Res:161704.0,61.1] always3(s14) || -> . % 76.16/76.36 161707[106:SSi:161706.0,78128.0,78132.0,137736.0,160940.0,161697.0] || -> . % 76.16/76.36 161708[106:Spt:161707.0,161702.0,161704.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.36 161709[106:Spt:161707.0,161702.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.36 161713[106:Res:161709.0,61.1] always3(s15) || -> . % 76.16/76.36 161714[106:SSi:161713.0,78133.0,78136.0,137737.0] || -> . % 76.16/76.36 161715[104:Spt:161714.0,160939.0,160940.0] || until2p7(s14)*+ -> . % 76.16/76.36 161716[104:Spt:161714.0,160939.1] || -> node4(s13)*. % 76.16/76.36 161718[104:MRR:879.0,161716.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.36 161721[104:Res:53.1,161718.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.36 161726[105:Spt:161721.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.36 161728[105:Res:161726.0,61.1] always3(s13) || -> . % 76.16/76.36 161729[105:SSi:161728.0,78124.0,78127.0,137735.0,160938.0,161716.0] || -> . % 76.16/76.36 161730[105:Spt:161729.0,161721.0,161726.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.36 161731[105:Spt:161729.0,161721.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.36 161735[105:Res:161731.0,61.1] always3(s14) || -> . % 76.16/76.36 161736[105:SSi:161735.0,78128.0,78132.0,137736.0] || -> . % 76.16/76.36 161737[103:Spt:161736.0,160937.0,160938.0] || until2p7(s13)*+ -> . % 76.16/76.36 161738[103:Spt:161736.0,160937.1] || -> node4(s12)*. % 76.16/76.36 161740[103:MRR:882.0,161738.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.36 161743[103:Res:53.1,161740.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.36 161745[104:Spt:161743.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.36 161747[104:Res:161745.0,61.1] always3(s12) || -> . % 76.16/76.36 161748[104:SSi:161747.0,78119.0,78123.0,137734.0,160936.0,161738.0] || -> . % 76.16/76.36 161749[104:Spt:161748.0,161743.0,161745.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.36 161750[104:Spt:161748.0,161743.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.36 161754[104:Res:161750.0,61.1] always3(s13) || -> . % 76.16/76.36 161755[104:SSi:161754.0,78124.0,78127.0,137735.0] || -> . % 76.16/76.36 161756[102:Spt:161755.0,160935.0,160936.0] || until2p7(s12)*+ -> . % 76.16/76.36 161757[102:Spt:161755.0,160935.1] || -> node4(s11)*. % 76.16/76.36 161759[102:MRR:885.0,161757.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.36 161762[102:Res:53.1,161759.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.36 161764[103:Spt:161762.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.36 161766[103:Res:161764.0,61.1] always3(s11) || -> . % 76.16/76.36 161767[103:SSi:161766.0,78115.0,78118.0,137733.0,160934.0,161757.0] || -> . % 76.16/76.36 161768[103:Spt:161767.0,161762.0,161764.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.36 161769[103:Spt:161767.0,161762.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.36 161773[103:Res:161769.0,61.1] always3(s12) || -> . % 76.16/76.36 161774[103:SSi:161773.0,78119.0,78123.0,137734.0] || -> . % 76.16/76.36 161775[101:Spt:161774.0,160933.0,160934.0] || until2p7(s11)*+ -> . % 76.16/76.36 161776[101:Spt:161774.0,160933.1] || -> node4(s10)*. % 76.16/76.36 161778[101:MRR:888.0,161776.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.36 161781[101:Res:53.1,161778.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.36 161783[102:Spt:161781.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.36 161785[102:Res:161783.0,61.1] always3(s10) || -> . % 76.16/76.36 161786[102:SSi:161785.0,78110.0,78114.0,137732.0,160932.0,161776.0] || -> . % 76.16/76.36 161787[102:Spt:161786.0,161781.0,161783.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.36 161788[102:Spt:161786.0,161781.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.36 161792[102:Res:161788.0,61.1] always3(s11) || -> . % 76.16/76.36 161793[102:SSi:161792.0,78115.0,78118.0,137733.0] || -> . % 76.16/76.36 161794[100:Spt:161793.0,160931.0,160932.0] || until2p7(s10)*+ -> . % 76.16/76.36 161795[100:Spt:161793.0,160931.1] || -> node4(s9)*. % 76.16/76.36 161797[100:MRR:891.0,161795.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.36 161800[100:Res:53.1,161797.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.36 161805[101:Spt:161800.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.36 161807[101:Res:161805.0,61.1] always3(s9) || -> . % 76.16/76.36 161808[101:SSi:161807.0,78106.0,78109.0,137731.0,160930.0,161795.0] || -> . % 76.16/76.36 161809[101:Spt:161808.0,161800.0,161805.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.36 161810[101:Spt:161808.0,161800.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.36 161814[101:Res:161810.0,61.1] always3(s10) || -> . % 76.16/76.36 161815[101:SSi:161814.0,78110.0,78114.0,137732.0] || -> . % 76.16/76.36 161816[99:Spt:161815.0,160929.0,160930.0] || until2p7(s9)*+ -> . % 76.16/76.36 161817[99:Spt:161815.0,160929.1] || -> node4(s8)*. % 76.16/76.36 161819[99:MRR:894.0,161817.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.36 161822[99:Res:53.1,161819.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.36 161824[100:Spt:161822.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.36 161826[100:Res:161824.0,61.1] always3(s8) || -> . % 76.16/76.36 161827[100:SSi:161826.0,78101.0,78105.0,137730.0,160928.0,161817.0] || -> . % 76.16/76.36 161828[100:Spt:161827.0,161822.0,161824.0] || m_main_v_state(s8,c_busy)* -> . % 76.16/76.36 161829[100:Spt:161827.0,161822.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.36 161833[100:Res:161829.0,61.1] always3(s9) || -> . % 76.16/76.36 161834[100:SSi:161833.0,78106.0,78109.0,137731.0] || -> . % 76.16/76.36 161835[98:Spt:161834.0,160927.0,160928.0] || until2p7(s8)*+ -> . % 76.16/76.36 161836[98:Spt:161834.0,160927.1] || -> node4(s7)*. % 76.16/76.36 161838[98:MRR:897.0,161836.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.16/76.36 161841[98:Res:53.1,161838.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.16/76.36 161843[98:MRR:161841.0,160917.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.36 161845[98:Res:161843.0,61.1] always3(s8) || -> . % 76.16/76.36 161846[98:SSi:161845.0,78101.0,78105.0,137730.0] || -> . % 76.16/76.36 161847[96:Spt:161846.0,160760.0,160763.0] || trans(s49,s7)*+ -> . % 76.16/76.36 161848[96:Spt:161846.0,160760.1,160760.2,160760.3] || -> trans(s49,s6) trans(s49,s5) node2(s49,s4)*. % 76.16/76.36 161850[96:MRR:160762.1,161847.0] xuntil6(s49) || -> trans(s49,s6) trans(s49,s5)* until2p7(s4). % 76.16/76.36 161851[97:Spt:161848.0] || -> trans(s49,s6)*. % 76.16/76.36 161852[97:Res:161851.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s6)*. % 76.16/76.36 161854[97:Res:161851.0,60.0] || -> node2(s49,s6)*. % 76.16/76.36 161855[97:SSi:161852.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s6)*. % 76.16/76.36 161856[97:Res:161854.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)*. % 76.16/76.36 161998[97:SoR:161856.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)*. % 76.16/76.36 162000[97:SoR:161998.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)* xuntil6(s49). % 76.16/76.36 162001[97:SSi:162000.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s6,c_busy)* xuntil6(s49). % 76.16/76.36 162002[98:Spt:162001.1] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.36 162004[98:Res:162002.0,61.1] always3(s6) || -> . % 76.16/76.36 162005[98:SSi:162004.0,78093.0,78096.0,137728.0] || -> . % 76.16/76.36 162006[98:Spt:162005.0,162001.1,162002.0] || m_main_v_state(s6,c_busy)*+ -> . % 76.16/76.36 162007[98:Spt:162005.0,162001.0,162001.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 162011[98:MRR:161998.2,162006.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 162012[98:Res:53.1,162007.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 162014[98:MRR:162012.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 162015[98:MRR:161855.0,162014.0] || -> until2p7(s6)*. % 76.16/76.36 162016[98:MRR:202.0,162015.0] || -> until2p7(s7)* node4(s6). % 76.16/76.36 162017[99:Spt:162016.0] || -> until2p7(s7)*. % 76.16/76.36 162018[99:MRR:203.0,162017.0] || -> until2p7(s8)* node4(s7). % 76.16/76.36 162019[100:Spt:162018.0] || -> until2p7(s8)*. % 76.16/76.36 162020[100:MRR:204.0,162019.0] || -> until2p7(s9)* node4(s8). % 76.16/76.36 162021[101:Spt:162020.0] || -> until2p7(s9)*. % 76.16/76.36 162022[101:MRR:205.0,162021.0] || -> until2p7(s10)* node4(s9). % 76.16/76.36 162023[102:Spt:162022.0] || -> until2p7(s10)*. % 76.16/76.36 162024[102:MRR:206.0,162023.0] || -> until2p7(s11)* node4(s10). % 76.16/76.36 162025[103:Spt:162024.0] || -> until2p7(s11)*. % 76.16/76.36 162026[103:MRR:207.0,162025.0] || -> until2p7(s12)* node4(s11). % 76.16/76.36 162027[104:Spt:162026.0] || -> until2p7(s12)*. % 76.16/76.36 162028[104:MRR:208.0,162027.0] || -> until2p7(s13)* node4(s12). % 76.16/76.36 162029[105:Spt:162028.0] || -> until2p7(s13)*. % 76.16/76.36 162030[105:MRR:209.0,162029.0] || -> until2p7(s14)* node4(s13). % 76.16/76.36 162031[106:Spt:162030.0] || -> until2p7(s14)*. % 76.16/76.36 162032[106:MRR:210.0,162031.0] || -> until2p7(s15)* node4(s14). % 76.16/76.36 162033[107:Spt:162032.0] || -> until2p7(s15)*. % 76.16/76.36 162034[107:MRR:211.0,162033.0] || -> until2p7(s16)* node4(s15). % 76.16/76.36 162035[108:Spt:162034.0] || -> until2p7(s16)*. % 76.16/76.36 162036[108:MRR:212.0,162035.0] || -> until2p7(s17)* node4(s16). % 76.16/76.36 162037[109:Spt:162036.0] || -> until2p7(s17)*. % 76.16/76.36 162038[109:MRR:213.0,162037.0] || -> until2p7(s18)* node4(s17). % 76.16/76.36 162039[110:Spt:162038.0] || -> until2p7(s18)*. % 76.16/76.36 162040[110:MRR:214.0,162039.0] || -> until2p7(s19)* node4(s18). % 76.16/76.36 162041[111:Spt:162040.0] || -> until2p7(s19)*. % 76.16/76.36 162042[111:MRR:215.0,162041.0] || -> until2p7(s20)* node4(s19). % 76.16/76.36 162043[112:Spt:162042.0] || -> until2p7(s20)*. % 76.16/76.36 162044[112:MRR:216.0,162043.0] || -> until2p7(s21)* node4(s20). % 76.16/76.36 162045[113:Spt:162044.0] || -> until2p7(s21)*. % 76.16/76.36 162046[113:MRR:217.0,162045.0] || -> until2p7(s22)* node4(s21). % 76.16/76.36 162047[114:Spt:162046.0] || -> until2p7(s22)*. % 76.16/76.36 162048[114:MRR:218.0,162047.0] || -> until2p7(s23)* node4(s22). % 76.16/76.36 162049[115:Spt:162048.0] || -> until2p7(s23)*. % 76.16/76.36 162050[115:MRR:219.0,162049.0] || -> until2p7(s24)* node4(s23). % 76.16/76.36 162051[116:Spt:162050.0] || -> until2p7(s24)*. % 76.16/76.36 162052[116:MRR:220.0,162051.0] || -> until2p7(s25)* node4(s24). % 76.16/76.36 162053[117:Spt:162052.0] || -> until2p7(s25)*. % 76.16/76.36 162054[117:MRR:221.0,162053.0] || -> until2p7(s26)* node4(s25). % 76.16/76.36 162055[118:Spt:162054.0] || -> until2p7(s26)*. % 76.16/76.36 162056[118:MRR:222.0,162055.0] || -> until2p7(s27)* node4(s26). % 76.16/76.36 162057[119:Spt:162056.0] || -> until2p7(s27)*. % 76.16/76.36 162058[119:MRR:223.0,162057.0] || -> until2p7(s28)* node4(s27). % 76.16/76.36 162059[120:Spt:162058.0] || -> until2p7(s28)*. % 76.16/76.36 162060[120:MRR:224.0,162059.0] || -> until2p7(s29)* node4(s28). % 76.16/76.36 162061[121:Spt:162060.0] || -> until2p7(s29)*. % 76.16/76.36 162062[121:MRR:225.0,162061.0] || -> until2p7(s30)* node4(s29). % 76.16/76.36 162063[122:Spt:162062.0] || -> until2p7(s30)*. % 76.16/76.36 162064[122:MRR:226.0,162063.0] || -> until2p7(s31)* node4(s30). % 76.16/76.36 162065[123:Spt:162064.0] || -> until2p7(s31)*. % 76.16/76.36 162066[123:MRR:227.0,162065.0] || -> until2p7(s32)* node4(s31). % 76.16/76.36 162067[124:Spt:162066.0] || -> until2p7(s32)*. % 76.16/76.36 162068[124:MRR:228.0,162067.0] || -> until2p7(s33)* node4(s32). % 76.16/76.36 162069[125:Spt:162068.0] || -> until2p7(s33)*. % 76.16/76.36 162070[125:MRR:229.0,162069.0] || -> until2p7(s34)* node4(s33). % 76.16/76.36 162071[126:Spt:162070.0] || -> until2p7(s34)*. % 76.16/76.36 162072[126:MRR:230.0,162071.0] || -> until2p7(s35)* node4(s34). % 76.16/76.36 162073[127:Spt:162072.0] || -> until2p7(s35)*. % 76.16/76.36 162074[127:MRR:231.0,162073.0] || -> until2p7(s36)* node4(s35). % 76.16/76.36 162075[128:Spt:162074.0] || -> until2p7(s36)*. % 76.16/76.36 162076[128:MRR:232.0,162075.0] || -> until2p7(s37)* node4(s36). % 76.16/76.36 162077[129:Spt:162076.0] || -> until2p7(s37)*. % 76.16/76.36 162078[129:MRR:235.0,162077.0] || -> until2p7(s38)* node4(s37). % 76.16/76.36 162079[130:Spt:162078.0] || -> until2p7(s38)*. % 76.16/76.36 162080[130:MRR:236.0,162079.0] || -> until2p7(s39)* node4(s38). % 76.16/76.36 162081[131:Spt:162080.0] || -> until2p7(s39)*. % 76.16/76.36 162082[131:MRR:237.0,162081.0] || -> until2p7(s40)* node4(s39). % 76.16/76.36 162083[132:Spt:162082.0] || -> until2p7(s40)*. % 76.16/76.36 162084[132:MRR:238.0,162083.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 162085[133:Spt:162084.0] || -> until2p7(s41)*. % 76.16/76.36 162086[133:MRR:239.0,162085.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 162087[134:Spt:162086.0] || -> until2p7(s42)*. % 76.16/76.36 162088[134:MRR:240.0,162087.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 162089[135:Spt:162088.0] || -> until2p7(s43)*. % 76.16/76.36 162090[135:MRR:241.0,162089.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 162091[136:Spt:162090.0] || -> until2p7(s44)*. % 76.16/76.36 162092[136:MRR:539.0,162091.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 162093[137:Spt:162092.0] || -> until2p7(s45)*. % 76.16/76.36 162094[137:MRR:544.0,162093.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 162095[138:Spt:162094.0] || -> until2p7(s46)*. % 76.16/76.36 162096[138:MRR:549.0,162095.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 162097[139:Spt:162096.0] || -> until2p7(s47)*. % 76.16/76.36 162098[139:MRR:554.0,162097.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 162099[140:Spt:162098.0] || -> until2p7(s48)*. % 76.16/76.36 162100[140:MRR:559.0,162099.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 162101[141:Spt:162100.0] || -> until2p7(s49)*. % 76.16/76.36 162102[141:MRR:194.0,162101.0] || -> node4(s49)*. % 76.16/76.36 162103[141:MRR:162011.0,162102.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 162107[141:Res:53.1,162103.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 162109[141:MRR:162107.0,78381.0] || -> . % 76.16/76.36 162110[141:Spt:162109.0,162100.0,162101.0] || until2p7(s49)*+ -> . % 76.16/76.36 162111[141:Spt:162109.0,162100.1] || -> node4(s48)*. % 76.16/76.36 162112[141:MRR:78384.0,162111.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 162115[141:Res:53.1,162112.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 162118[141:Res:162115.0,61.1] always3(s48) || -> . % 76.16/76.36 162119[141:SSi:162118.0,78281.0,78387.0,137770.0,162099.0,162111.0] || -> . % 76.16/76.36 162120[140:Spt:162119.0,162098.0,162099.0] || until2p7(s48)*+ -> . % 76.16/76.36 162121[140:Spt:162119.0,162098.1] || -> node4(s47)*. % 76.16/76.36 162123[140:MRR:777.0,162121.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 162135[140:Res:53.1,162123.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 162137[141:Spt:162135.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 162139[141:Res:162137.0,61.1] always3(s47) || -> . % 76.16/76.36 162140[141:SSi:162139.0,78277.0,78280.0,137769.0,162097.0,162121.0] || -> . % 76.16/76.36 162141[141:Spt:162140.0,162135.0,162137.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 162142[141:Spt:162140.0,162135.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 162146[141:Res:162142.0,61.1] always3(s48) || -> . % 76.16/76.36 162147[141:SSi:162146.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.36 162148[139:Spt:162147.0,162096.0,162097.0] || until2p7(s47)*+ -> . % 76.16/76.36 162149[139:Spt:162147.0,162096.1] || -> node4(s46)*. % 76.16/76.36 162151[139:MRR:780.0,162149.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 162158[139:Res:53.1,162151.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 162163[140:Spt:162158.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 162165[140:Res:162163.0,61.1] always3(s46) || -> . % 76.16/76.36 162166[140:SSi:162165.0,78272.0,78276.0,137768.0,162095.0,162149.0] || -> . % 76.16/76.36 162167[140:Spt:162166.0,162158.0,162163.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 162168[140:Spt:162166.0,162158.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 162172[140:Res:162168.0,61.1] always3(s47) || -> . % 76.16/76.36 162173[140:SSi:162172.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.36 162174[138:Spt:162173.0,162094.0,162095.0] || until2p7(s46)*+ -> . % 76.16/76.36 162175[138:Spt:162173.0,162094.1] || -> node4(s45)*. % 76.16/76.36 162177[138:MRR:783.0,162175.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 162180[138:Res:53.1,162177.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 162182[139:Spt:162180.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 162184[139:Res:162182.0,61.1] always3(s45) || -> . % 76.16/76.36 162185[139:SSi:162184.0,78268.0,78271.0,137767.0,162093.0,162175.0] || -> . % 76.16/76.36 162186[139:Spt:162185.0,162180.0,162182.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 162187[139:Spt:162185.0,162180.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 162191[139:Res:162187.0,61.1] always3(s46) || -> . % 76.16/76.36 162192[139:SSi:162191.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.36 162193[137:Spt:162192.0,162092.0,162093.0] || until2p7(s45)*+ -> . % 76.16/76.36 162194[137:Spt:162192.0,162092.1] || -> node4(s44)*. % 76.16/76.36 162196[137:MRR:786.0,162194.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 162199[137:Res:53.1,162196.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 162201[138:Spt:162199.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 162203[138:Res:162201.0,61.1] always3(s44) || -> . % 76.16/76.36 162204[138:SSi:162203.0,78263.0,78267.0,137766.0,162091.0,162194.0] || -> . % 76.16/76.36 162205[138:Spt:162204.0,162199.0,162201.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 162206[138:Spt:162204.0,162199.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 162210[138:Res:162206.0,61.1] always3(s45) || -> . % 76.16/76.36 162211[138:SSi:162210.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.36 162212[136:Spt:162211.0,162090.0,162091.0] || until2p7(s44)*+ -> . % 76.16/76.36 162213[136:Spt:162211.0,162090.1] || -> node4(s43)*. % 76.16/76.36 162215[136:MRR:789.0,162213.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 162218[136:Res:53.1,162215.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 162220[137:Spt:162218.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 162222[137:Res:162220.0,61.1] always3(s43) || -> . % 76.16/76.36 162223[137:SSi:162222.0,78259.0,78262.0,137765.0,162089.0,162213.0] || -> . % 76.16/76.36 162224[137:Spt:162223.0,162218.0,162220.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 162225[137:Spt:162223.0,162218.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 162229[137:Res:162225.0,61.1] always3(s44) || -> . % 76.16/76.36 162230[137:SSi:162229.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.36 162231[135:Spt:162230.0,162088.0,162089.0] || until2p7(s43)*+ -> . % 76.16/76.36 162232[135:Spt:162230.0,162088.1] || -> node4(s42)*. % 76.16/76.36 162234[135:MRR:792.0,162232.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 162237[135:Res:53.1,162234.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 162242[136:Spt:162237.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 162244[136:Res:162242.0,61.1] always3(s42) || -> . % 76.16/76.36 162245[136:SSi:162244.0,78254.0,78258.0,137764.0,162087.0,162232.0] || -> . % 76.16/76.36 162246[136:Spt:162245.0,162237.0,162242.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 162247[136:Spt:162245.0,162237.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 162251[136:Res:162247.0,61.1] always3(s43) || -> . % 76.16/76.36 162252[136:SSi:162251.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.36 162253[134:Spt:162252.0,162086.0,162087.0] || until2p7(s42)*+ -> . % 76.16/76.36 162254[134:Spt:162252.0,162086.1] || -> node4(s41)*. % 76.16/76.36 162256[134:MRR:795.0,162254.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 162259[134:Res:53.1,162256.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 162261[135:Spt:162259.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 162263[135:Res:162261.0,61.1] always3(s41) || -> . % 76.16/76.36 162264[135:SSi:162263.0,78250.0,78253.0,137763.0,162085.0,162254.0] || -> . % 76.16/76.36 162265[135:Spt:162264.0,162259.0,162261.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 162266[135:Spt:162264.0,162259.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 162270[135:Res:162266.0,61.1] always3(s42) || -> . % 76.16/76.36 162271[135:SSi:162270.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.36 162272[133:Spt:162271.0,162084.0,162085.0] || until2p7(s41)*+ -> . % 76.16/76.36 162273[133:Spt:162271.0,162084.1] || -> node4(s40)*. % 76.16/76.36 162275[133:MRR:798.0,162273.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 162278[133:Res:53.1,162275.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 162280[134:Spt:162278.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 162282[134:Res:162280.0,61.1] always3(s40) || -> . % 76.16/76.36 162283[134:SSi:162282.0,78245.0,78249.0,137762.0,162083.0,162273.0] || -> . % 76.16/76.36 162284[134:Spt:162283.0,162278.0,162280.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.36 162285[134:Spt:162283.0,162278.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 162289[134:Res:162285.0,61.1] always3(s41) || -> . % 76.16/76.36 162290[134:SSi:162289.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.36 162291[132:Spt:162290.0,162082.0,162083.0] || until2p7(s40)*+ -> . % 76.16/76.36 162292[132:Spt:162290.0,162082.1] || -> node4(s39)*. % 76.16/76.36 162294[132:MRR:801.0,162292.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.36 162297[132:Res:53.1,162294.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.36 162299[133:Spt:162297.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 162301[133:Res:162299.0,61.1] always3(s39) || -> . % 76.16/76.36 162302[133:SSi:162301.0,78241.0,78244.0,137761.0,162081.0,162292.0] || -> . % 76.16/76.36 162303[133:Spt:162302.0,162297.0,162299.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.36 162304[133:Spt:162302.0,162297.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 162308[133:Res:162304.0,61.1] always3(s40) || -> . % 76.16/76.36 162309[133:SSi:162308.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.36 162310[131:Spt:162309.0,162080.0,162081.0] || until2p7(s39)*+ -> . % 76.16/76.36 162311[131:Spt:162309.0,162080.1] || -> node4(s38)*. % 76.16/76.36 162313[131:MRR:804.0,162311.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.36 162316[131:Res:53.1,162313.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.36 162321[132:Spt:162316.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 162323[132:Res:162321.0,61.1] always3(s38) || -> . % 76.16/76.36 162324[132:SSi:162323.0,78236.0,78240.0,137760.0,162079.0,162311.0] || -> . % 76.16/76.36 162325[132:Spt:162324.0,162316.0,162321.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.36 162326[132:Spt:162324.0,162316.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 162330[132:Res:162326.0,61.1] always3(s39) || -> . % 76.16/76.36 162331[132:SSi:162330.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.36 162332[130:Spt:162331.0,162078.0,162079.0] || until2p7(s38)*+ -> . % 76.16/76.36 162333[130:Spt:162331.0,162078.1] || -> node4(s37)*. % 76.16/76.36 162335[130:MRR:807.0,162333.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.36 162338[130:Res:53.1,162335.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.36 162340[131:Spt:162338.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 162342[131:Res:162340.0,61.1] always3(s37) || -> . % 76.16/76.36 162343[131:SSi:162342.0,78232.0,78235.0,137759.0,162077.0,162333.0] || -> . % 76.16/76.36 162344[131:Spt:162343.0,162338.0,162340.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.36 162345[131:Spt:162343.0,162338.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 162349[131:Res:162345.0,61.1] always3(s38) || -> . % 76.16/76.36 162350[131:SSi:162349.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.36 162351[129:Spt:162350.0,162076.0,162077.0] || until2p7(s37)*+ -> . % 76.16/76.36 162352[129:Spt:162350.0,162076.1] || -> node4(s36)*. % 76.16/76.36 162354[129:MRR:810.0,162352.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.36 162357[129:Res:53.1,162354.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.36 162359[130:Spt:162357.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 162361[130:Res:162359.0,61.1] always3(s36) || -> . % 76.16/76.36 162362[130:SSi:162361.0,78227.0,78231.0,137758.0,162075.0,162352.0] || -> . % 76.16/76.36 162363[130:Spt:162362.0,162357.0,162359.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.36 162364[130:Spt:162362.0,162357.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 162368[130:Res:162364.0,61.1] always3(s37) || -> . % 76.16/76.36 162369[130:SSi:162368.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.36 162370[128:Spt:162369.0,162074.0,162075.0] || until2p7(s36)*+ -> . % 76.16/76.36 162371[128:Spt:162369.0,162074.1] || -> node4(s35)*. % 76.16/76.36 162373[128:MRR:813.0,162371.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.36 162376[128:Res:53.1,162373.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.36 162378[129:Spt:162376.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 162380[129:Res:162378.0,61.1] always3(s35) || -> . % 76.16/76.36 162381[129:SSi:162380.0,78223.0,78226.0,137757.0,162073.0,162371.0] || -> . % 76.16/76.36 162382[129:Spt:162381.0,162376.0,162378.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.36 162383[129:Spt:162381.0,162376.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 162387[129:Res:162383.0,61.1] always3(s36) || -> . % 76.16/76.36 162388[129:SSi:162387.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.36 162389[127:Spt:162388.0,162072.0,162073.0] || until2p7(s35)*+ -> . % 76.16/76.36 162390[127:Spt:162388.0,162072.1] || -> node4(s34)*. % 76.16/76.36 162392[127:MRR:816.0,162390.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.36 162395[127:Res:53.1,162392.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.36 162400[128:Spt:162395.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 162402[128:Res:162400.0,61.1] always3(s34) || -> . % 76.16/76.36 162403[128:SSi:162402.0,78218.0,78222.0,137756.0,162071.0,162390.0] || -> . % 76.16/76.36 162404[128:Spt:162403.0,162395.0,162400.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.36 162405[128:Spt:162403.0,162395.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 162409[128:Res:162405.0,61.1] always3(s35) || -> . % 76.16/76.36 162410[128:SSi:162409.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.36 162411[126:Spt:162410.0,162070.0,162071.0] || until2p7(s34)*+ -> . % 76.16/76.36 162412[126:Spt:162410.0,162070.1] || -> node4(s33)*. % 76.16/76.36 162414[126:MRR:819.0,162412.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.36 162417[126:Res:53.1,162414.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.36 162419[127:Spt:162417.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.36 162421[127:Res:162419.0,61.1] always3(s33) || -> . % 76.16/76.36 162422[127:SSi:162421.0,78214.0,78217.0,137755.0,162069.0,162412.0] || -> . % 76.16/76.36 162423[127:Spt:162422.0,162417.0,162419.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.36 162424[127:Spt:162422.0,162417.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 162428[127:Res:162424.0,61.1] always3(s34) || -> . % 76.16/76.36 162429[127:SSi:162428.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.36 162430[125:Spt:162429.0,162068.0,162069.0] || until2p7(s33)*+ -> . % 76.16/76.36 162431[125:Spt:162429.0,162068.1] || -> node4(s32)*. % 76.16/76.36 162433[125:MRR:822.0,162431.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.36 162436[125:Res:53.1,162433.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.36 162438[126:Spt:162436.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.36 162440[126:Res:162438.0,61.1] always3(s32) || -> . % 76.16/76.36 162441[126:SSi:162440.0,78209.0,78213.0,137754.0,162067.0,162431.0] || -> . % 76.16/76.36 162442[126:Spt:162441.0,162436.0,162438.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.36 162443[126:Spt:162441.0,162436.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.36 162447[126:Res:162443.0,61.1] always3(s33) || -> . % 76.16/76.36 162448[126:SSi:162447.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.36 162449[124:Spt:162448.0,162066.0,162067.0] || until2p7(s32)*+ -> . % 76.16/76.36 162450[124:Spt:162448.0,162066.1] || -> node4(s31)*. % 76.16/76.36 162452[124:MRR:825.0,162450.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.36 162455[124:Res:53.1,162452.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.36 162457[125:Spt:162455.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.36 162459[125:Res:162457.0,61.1] always3(s31) || -> . % 76.16/76.36 162460[125:SSi:162459.0,78205.0,78208.0,137753.0,162065.0,162450.0] || -> . % 76.16/76.36 162461[125:Spt:162460.0,162455.0,162457.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.36 162462[125:Spt:162460.0,162455.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.36 162466[125:Res:162462.0,61.1] always3(s32) || -> . % 76.16/76.36 162467[125:SSi:162466.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.36 162468[123:Spt:162467.0,162064.0,162065.0] || until2p7(s31)*+ -> . % 76.16/76.36 162469[123:Spt:162467.0,162064.1] || -> node4(s30)*. % 76.16/76.36 162471[123:MRR:828.0,162469.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.36 162474[123:Res:53.1,162471.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.36 162479[124:Spt:162474.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.36 162481[124:Res:162479.0,61.1] always3(s30) || -> . % 76.16/76.36 162482[124:SSi:162481.0,78200.0,78204.0,137752.0,162063.0,162469.0] || -> . % 76.16/76.36 162483[124:Spt:162482.0,162474.0,162479.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.36 162484[124:Spt:162482.0,162474.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.36 162488[124:Res:162484.0,61.1] always3(s31) || -> . % 76.16/76.36 162489[124:SSi:162488.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.36 162490[122:Spt:162489.0,162062.0,162063.0] || until2p7(s30)*+ -> . % 76.16/76.36 162491[122:Spt:162489.0,162062.1] || -> node4(s29)*. % 76.16/76.36 162493[122:MRR:831.0,162491.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.36 162496[122:Res:53.1,162493.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.36 162498[123:Spt:162496.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.36 162500[123:Res:162498.0,61.1] always3(s29) || -> . % 76.16/76.36 162501[123:SSi:162500.0,78196.0,78199.0,137751.0,162061.0,162491.0] || -> . % 76.16/76.36 162502[123:Spt:162501.0,162496.0,162498.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.36 162503[123:Spt:162501.0,162496.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.36 162507[123:Res:162503.0,61.1] always3(s30) || -> . % 76.16/76.36 162508[123:SSi:162507.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.36 162509[121:Spt:162508.0,162060.0,162061.0] || until2p7(s29)*+ -> . % 76.16/76.36 162510[121:Spt:162508.0,162060.1] || -> node4(s28)*. % 76.16/76.36 162512[121:MRR:834.0,162510.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.36 162515[121:Res:53.1,162512.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.36 162517[122:Spt:162515.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.36 162519[122:Res:162517.0,61.1] always3(s28) || -> . % 76.16/76.36 162520[122:SSi:162519.0,78191.0,78195.0,137750.0,162059.0,162510.0] || -> . % 76.16/76.36 162521[122:Spt:162520.0,162515.0,162517.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.36 162522[122:Spt:162520.0,162515.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.36 162526[122:Res:162522.0,61.1] always3(s29) || -> . % 76.16/76.36 162527[122:SSi:162526.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.36 162528[120:Spt:162527.0,162058.0,162059.0] || until2p7(s28)*+ -> . % 76.16/76.36 162529[120:Spt:162527.0,162058.1] || -> node4(s27)*. % 76.16/76.36 162531[120:MRR:837.0,162529.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.36 162534[120:Res:53.1,162531.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.36 162536[121:Spt:162534.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.36 162538[121:Res:162536.0,61.1] always3(s27) || -> . % 76.16/76.36 162539[121:SSi:162538.0,78187.0,78190.0,137749.0,162057.0,162529.0] || -> . % 76.16/76.36 162540[121:Spt:162539.0,162534.0,162536.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.36 162541[121:Spt:162539.0,162534.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.36 162545[121:Res:162541.0,61.1] always3(s28) || -> . % 76.16/76.36 162546[121:SSi:162545.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.36 162547[119:Spt:162546.0,162056.0,162057.0] || until2p7(s27)*+ -> . % 76.16/76.36 162548[119:Spt:162546.0,162056.1] || -> node4(s26)*. % 76.16/76.36 162550[119:MRR:840.0,162548.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.36 162553[119:Res:53.1,162550.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.36 162558[120:Spt:162553.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.36 162560[120:Res:162558.0,61.1] always3(s26) || -> . % 76.16/76.36 162561[120:SSi:162560.0,78182.0,78186.0,137748.0,162055.0,162548.0] || -> . % 76.16/76.36 162562[120:Spt:162561.0,162553.0,162558.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.36 162563[120:Spt:162561.0,162553.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.36 162567[120:Res:162563.0,61.1] always3(s27) || -> . % 76.16/76.36 162568[120:SSi:162567.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.36 162569[118:Spt:162568.0,162054.0,162055.0] || until2p7(s26)*+ -> . % 76.16/76.36 162570[118:Spt:162568.0,162054.1] || -> node4(s25)*. % 76.16/76.36 162572[118:MRR:843.0,162570.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.36 162575[118:Res:53.1,162572.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.36 162577[119:Spt:162575.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.36 162579[119:Res:162577.0,61.1] always3(s25) || -> . % 76.16/76.36 162580[119:SSi:162579.0,78178.0,78181.0,137747.0,162053.0,162570.0] || -> . % 76.16/76.36 162581[119:Spt:162580.0,162575.0,162577.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.36 162582[119:Spt:162580.0,162575.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.36 162586[119:Res:162582.0,61.1] always3(s26) || -> . % 76.16/76.36 162587[119:SSi:162586.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.36 162588[117:Spt:162587.0,162052.0,162053.0] || until2p7(s25)*+ -> . % 76.16/76.36 162589[117:Spt:162587.0,162052.1] || -> node4(s24)*. % 76.16/76.36 162591[117:MRR:846.0,162589.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.36 162594[117:Res:53.1,162591.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.36 162596[118:Spt:162594.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.36 162598[118:Res:162596.0,61.1] always3(s24) || -> . % 76.16/76.36 162599[118:SSi:162598.0,78173.0,78177.0,137746.0,162051.0,162589.0] || -> . % 76.16/76.36 162600[118:Spt:162599.0,162594.0,162596.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.36 162601[118:Spt:162599.0,162594.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.36 162605[118:Res:162601.0,61.1] always3(s25) || -> . % 76.16/76.36 162606[118:SSi:162605.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.36 162607[116:Spt:162606.0,162050.0,162051.0] || until2p7(s24)*+ -> . % 76.16/76.36 162608[116:Spt:162606.0,162050.1] || -> node4(s23)*. % 76.16/76.36 162610[116:MRR:849.0,162608.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.36 162613[116:Res:53.1,162610.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.36 162615[117:Spt:162613.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.36 162617[117:Res:162615.0,61.1] always3(s23) || -> . % 76.16/76.36 162618[117:SSi:162617.0,78169.0,78172.0,137745.0,162049.0,162608.0] || -> . % 76.16/76.36 162619[117:Spt:162618.0,162613.0,162615.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.36 162620[117:Spt:162618.0,162613.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.36 162624[117:Res:162620.0,61.1] always3(s24) || -> . % 76.16/76.36 162625[117:SSi:162624.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.36 162626[115:Spt:162625.0,162048.0,162049.0] || until2p7(s23)*+ -> . % 76.16/76.36 162627[115:Spt:162625.0,162048.1] || -> node4(s22)*. % 76.16/76.36 162629[115:MRR:852.0,162627.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.36 162632[115:Res:53.1,162629.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.36 162637[116:Spt:162632.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.36 162639[116:Res:162637.0,61.1] always3(s22) || -> . % 76.16/76.36 162640[116:SSi:162639.0,78164.0,78168.0,137744.0,162047.0,162627.0] || -> . % 76.16/76.36 162641[116:Spt:162640.0,162632.0,162637.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.36 162642[116:Spt:162640.0,162632.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.36 162646[116:Res:162642.0,61.1] always3(s23) || -> . % 76.16/76.36 162647[116:SSi:162646.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.36 162648[114:Spt:162647.0,162046.0,162047.0] || until2p7(s22)*+ -> . % 76.16/76.36 162649[114:Spt:162647.0,162046.1] || -> node4(s21)*. % 76.16/76.36 162651[114:MRR:855.0,162649.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.36 162654[114:Res:53.1,162651.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.36 162656[115:Spt:162654.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.36 162658[115:Res:162656.0,61.1] always3(s21) || -> . % 76.16/76.36 162659[115:SSi:162658.0,78160.0,78163.0,137743.0,162045.0,162649.0] || -> . % 76.16/76.36 162660[115:Spt:162659.0,162654.0,162656.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.36 162661[115:Spt:162659.0,162654.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.36 162665[115:Res:162661.0,61.1] always3(s22) || -> . % 76.16/76.36 162666[115:SSi:162665.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.36 162667[113:Spt:162666.0,162044.0,162045.0] || until2p7(s21)*+ -> . % 76.16/76.36 162668[113:Spt:162666.0,162044.1] || -> node4(s20)*. % 76.16/76.36 162670[113:MRR:858.0,162668.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.36 162673[113:Res:53.1,162670.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.36 162675[114:Spt:162673.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.36 162677[114:Res:162675.0,61.1] always3(s20) || -> . % 76.16/76.36 162678[114:SSi:162677.0,78155.0,78159.0,137742.0,162043.0,162668.0] || -> . % 76.16/76.36 162679[114:Spt:162678.0,162673.0,162675.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.36 162680[114:Spt:162678.0,162673.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.36 162684[114:Res:162680.0,61.1] always3(s21) || -> . % 76.16/76.36 162685[114:SSi:162684.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.36 162686[112:Spt:162685.0,162042.0,162043.0] || until2p7(s20)*+ -> . % 76.16/76.36 162687[112:Spt:162685.0,162042.1] || -> node4(s19)*. % 76.16/76.36 162689[112:MRR:861.0,162687.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.36 162692[112:Res:53.1,162689.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.36 162694[113:Spt:162692.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.36 162696[113:Res:162694.0,61.1] always3(s19) || -> . % 76.16/76.36 162697[113:SSi:162696.0,78151.0,78154.0,137741.0,162041.0,162687.0] || -> . % 76.16/76.36 162698[113:Spt:162697.0,162692.0,162694.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.36 162699[113:Spt:162697.0,162692.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.36 162703[113:Res:162699.0,61.1] always3(s20) || -> . % 76.16/76.36 162704[113:SSi:162703.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.36 162705[111:Spt:162704.0,162040.0,162041.0] || until2p7(s19)*+ -> . % 76.16/76.36 162706[111:Spt:162704.0,162040.1] || -> node4(s18)*. % 76.16/76.36 162708[111:MRR:864.0,162706.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.36 162711[111:Res:53.1,162708.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.36 162716[112:Spt:162711.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.36 162718[112:Res:162716.0,61.1] always3(s18) || -> . % 76.16/76.36 162719[112:SSi:162718.0,78146.0,78150.0,137740.0,162039.0,162706.0] || -> . % 76.16/76.36 162720[112:Spt:162719.0,162711.0,162716.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.36 162721[112:Spt:162719.0,162711.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.36 162725[112:Res:162721.0,61.1] always3(s19) || -> . % 76.16/76.36 162726[112:SSi:162725.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.36 162727[110:Spt:162726.0,162038.0,162039.0] || until2p7(s18)*+ -> . % 76.16/76.36 162728[110:Spt:162726.0,162038.1] || -> node4(s17)*. % 76.16/76.36 162730[110:MRR:867.0,162728.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.36 162733[110:Res:53.1,162730.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.36 162735[111:Spt:162733.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.36 162737[111:Res:162735.0,61.1] always3(s17) || -> . % 76.16/76.36 162738[111:SSi:162737.0,78142.0,78145.0,137739.0,162037.0,162728.0] || -> . % 76.16/76.36 162739[111:Spt:162738.0,162733.0,162735.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.36 162740[111:Spt:162738.0,162733.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.36 162744[111:Res:162740.0,61.1] always3(s18) || -> . % 76.16/76.36 162745[111:SSi:162744.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.36 162746[109:Spt:162745.0,162036.0,162037.0] || until2p7(s17)*+ -> . % 76.16/76.36 162747[109:Spt:162745.0,162036.1] || -> node4(s16)*. % 76.16/76.36 162749[109:MRR:870.0,162747.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.36 162752[109:Res:53.1,162749.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.36 162754[110:Spt:162752.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.36 162756[110:Res:162754.0,61.1] always3(s16) || -> . % 76.16/76.36 162757[110:SSi:162756.0,78137.0,78141.0,137738.0,162035.0,162747.0] || -> . % 76.16/76.36 162758[110:Spt:162757.0,162752.0,162754.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.36 162759[110:Spt:162757.0,162752.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.36 162763[110:Res:162759.0,61.1] always3(s17) || -> . % 76.16/76.36 162764[110:SSi:162763.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.36 162765[108:Spt:162764.0,162034.0,162035.0] || until2p7(s16)*+ -> . % 76.16/76.36 162766[108:Spt:162764.0,162034.1] || -> node4(s15)*. % 76.16/76.36 162768[108:MRR:873.0,162766.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.36 162771[108:Res:53.1,162768.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.36 162773[109:Spt:162771.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.36 162775[109:Res:162773.0,61.1] always3(s15) || -> . % 76.16/76.36 162776[109:SSi:162775.0,78133.0,78136.0,137737.0,162033.0,162766.0] || -> . % 76.16/76.36 162777[109:Spt:162776.0,162771.0,162773.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.36 162778[109:Spt:162776.0,162771.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.36 162782[109:Res:162778.0,61.1] always3(s16) || -> . % 76.16/76.36 162783[109:SSi:162782.0,78137.0,78141.0,137738.0] || -> . % 76.16/76.36 162784[107:Spt:162783.0,162032.0,162033.0] || until2p7(s15)*+ -> . % 76.16/76.36 162785[107:Spt:162783.0,162032.1] || -> node4(s14)*. % 76.16/76.36 162787[107:MRR:876.0,162785.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.36 162790[107:Res:53.1,162787.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.36 162795[108:Spt:162790.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.36 162797[108:Res:162795.0,61.1] always3(s14) || -> . % 76.16/76.36 162798[108:SSi:162797.0,78128.0,78132.0,137736.0,162031.0,162785.0] || -> . % 76.16/76.36 162799[108:Spt:162798.0,162790.0,162795.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.36 162800[108:Spt:162798.0,162790.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.36 162804[108:Res:162800.0,61.1] always3(s15) || -> . % 76.16/76.36 162805[108:SSi:162804.0,78133.0,78136.0,137737.0] || -> . % 76.16/76.36 162806[106:Spt:162805.0,162030.0,162031.0] || until2p7(s14)*+ -> . % 76.16/76.36 162807[106:Spt:162805.0,162030.1] || -> node4(s13)*. % 76.16/76.36 162809[106:MRR:879.0,162807.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.36 162812[106:Res:53.1,162809.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.36 162814[107:Spt:162812.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.36 162816[107:Res:162814.0,61.1] always3(s13) || -> . % 76.16/76.36 162817[107:SSi:162816.0,78124.0,78127.0,137735.0,162029.0,162807.0] || -> . % 76.16/76.36 162818[107:Spt:162817.0,162812.0,162814.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.36 162819[107:Spt:162817.0,162812.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.36 162823[107:Res:162819.0,61.1] always3(s14) || -> . % 76.16/76.36 162824[107:SSi:162823.0,78128.0,78132.0,137736.0] || -> . % 76.16/76.36 162825[105:Spt:162824.0,162028.0,162029.0] || until2p7(s13)*+ -> . % 76.16/76.36 162826[105:Spt:162824.0,162028.1] || -> node4(s12)*. % 76.16/76.36 162828[105:MRR:882.0,162826.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.36 162831[105:Res:53.1,162828.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.36 162833[106:Spt:162831.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.36 162835[106:Res:162833.0,61.1] always3(s12) || -> . % 76.16/76.36 162836[106:SSi:162835.0,78119.0,78123.0,137734.0,162027.0,162826.0] || -> . % 76.16/76.36 162837[106:Spt:162836.0,162831.0,162833.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.36 162838[106:Spt:162836.0,162831.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.36 162842[106:Res:162838.0,61.1] always3(s13) || -> . % 76.16/76.36 162843[106:SSi:162842.0,78124.0,78127.0,137735.0] || -> . % 76.16/76.36 162844[104:Spt:162843.0,162026.0,162027.0] || until2p7(s12)*+ -> . % 76.16/76.36 162845[104:Spt:162843.0,162026.1] || -> node4(s11)*. % 76.16/76.36 162847[104:MRR:885.0,162845.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.36 162850[104:Res:53.1,162847.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.36 162852[105:Spt:162850.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.36 162854[105:Res:162852.0,61.1] always3(s11) || -> . % 76.16/76.36 162855[105:SSi:162854.0,78115.0,78118.0,137733.0,162025.0,162845.0] || -> . % 76.16/76.36 162856[105:Spt:162855.0,162850.0,162852.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.36 162857[105:Spt:162855.0,162850.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.36 162861[105:Res:162857.0,61.1] always3(s12) || -> . % 76.16/76.36 162862[105:SSi:162861.0,78119.0,78123.0,137734.0] || -> . % 76.16/76.36 162863[103:Spt:162862.0,162024.0,162025.0] || until2p7(s11)*+ -> . % 76.16/76.36 162864[103:Spt:162862.0,162024.1] || -> node4(s10)*. % 76.16/76.36 162866[103:MRR:888.0,162864.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.36 162869[103:Res:53.1,162866.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.36 162874[104:Spt:162869.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.36 162876[104:Res:162874.0,61.1] always3(s10) || -> . % 76.16/76.36 162877[104:SSi:162876.0,78110.0,78114.0,137732.0,162023.0,162864.0] || -> . % 76.16/76.36 162878[104:Spt:162877.0,162869.0,162874.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.36 162879[104:Spt:162877.0,162869.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.36 162883[104:Res:162879.0,61.1] always3(s11) || -> . % 76.16/76.36 162884[104:SSi:162883.0,78115.0,78118.0,137733.0] || -> . % 76.16/76.36 162885[102:Spt:162884.0,162022.0,162023.0] || until2p7(s10)*+ -> . % 76.16/76.36 162886[102:Spt:162884.0,162022.1] || -> node4(s9)*. % 76.16/76.36 162888[102:MRR:891.0,162886.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.36 162891[102:Res:53.1,162888.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.36 162893[103:Spt:162891.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.36 162895[103:Res:162893.0,61.1] always3(s9) || -> . % 76.16/76.36 162896[103:SSi:162895.0,78106.0,78109.0,137731.0,162021.0,162886.0] || -> . % 76.16/76.36 162897[103:Spt:162896.0,162891.0,162893.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.36 162898[103:Spt:162896.0,162891.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.36 162902[103:Res:162898.0,61.1] always3(s10) || -> . % 76.16/76.36 162903[103:SSi:162902.0,78110.0,78114.0,137732.0] || -> . % 76.16/76.36 162904[101:Spt:162903.0,162020.0,162021.0] || until2p7(s9)*+ -> . % 76.16/76.36 162905[101:Spt:162903.0,162020.1] || -> node4(s8)*. % 76.16/76.36 162907[101:MRR:894.0,162905.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.36 162910[101:Res:53.1,162907.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.36 162912[102:Spt:162910.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.36 162914[102:Res:162912.0,61.1] always3(s8) || -> . % 76.16/76.36 162915[102:SSi:162914.0,78101.0,78105.0,137730.0,162019.0,162905.0] || -> . % 76.16/76.36 162916[102:Spt:162915.0,162910.0,162912.0] || m_main_v_state(s8,c_busy)* -> . % 76.16/76.36 162917[102:Spt:162915.0,162910.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.36 162921[102:Res:162917.0,61.1] always3(s9) || -> . % 76.16/76.36 162922[102:SSi:162921.0,78106.0,78109.0,137731.0] || -> . % 76.16/76.36 162923[100:Spt:162922.0,162018.0,162019.0] || until2p7(s8)*+ -> . % 76.16/76.36 162924[100:Spt:162922.0,162018.1] || -> node4(s7)*. % 76.16/76.36 162926[100:MRR:897.0,162924.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.16/76.36 162929[100:Res:53.1,162926.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.16/76.36 162931[101:Spt:162929.0] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.36 162933[101:Res:162931.0,61.1] always3(s7) || -> . % 76.16/76.36 162934[101:SSi:162933.0,78097.0,78100.0,137729.0,162017.0,162924.0] || -> . % 76.16/76.36 162935[101:Spt:162934.0,162929.0,162931.0] || m_main_v_state(s7,c_busy)* -> . % 76.16/76.36 162936[101:Spt:162934.0,162929.1] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.36 162940[101:Res:162936.0,61.1] always3(s8) || -> . % 76.16/76.36 162941[101:SSi:162940.0,78101.0,78105.0,137730.0] || -> . % 76.16/76.36 162942[99:Spt:162941.0,162016.0,162017.0] || until2p7(s7)*+ -> . % 76.16/76.36 162943[99:Spt:162941.0,162016.1] || -> node4(s6)*. % 76.16/76.36 162945[99:MRR:900.0,162943.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.16/76.36 162948[99:Res:53.1,162945.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.16/76.36 162950[99:MRR:162948.0,162006.0] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.36 162955[99:Res:162950.0,61.1] always3(s7) || -> . % 76.16/76.36 162956[99:SSi:162955.0,78097.0,78100.0,137729.0] || -> . % 76.16/76.36 162957[97:Spt:162956.0,161848.0,161851.0] || trans(s49,s6)*+ -> . % 76.16/76.36 162958[97:Spt:162956.0,161848.1,161848.2] || -> trans(s49,s5) node2(s49,s4)*. % 76.16/76.36 162960[97:MRR:161850.1,162957.0] xuntil6(s49) || -> trans(s49,s5)* until2p7(s4). % 76.16/76.36 162961[98:Spt:162958.0] || -> trans(s49,s5)*. % 76.16/76.36 162962[98:Res:162961.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s5)*. % 76.16/76.36 162964[98:Res:162961.0,60.0] || -> node2(s49,s5)*. % 76.16/76.36 162965[98:SSi:162962.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s5)*. % 76.16/76.36 162966[98:Res:162964.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)*. % 76.16/76.36 163112[98:SoR:162966.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)*. % 76.16/76.36 163114[98:SoR:163112.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)* xuntil6(s49). % 76.16/76.36 163115[98:SSi:163114.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s5,c_busy)* xuntil6(s49). % 76.16/76.36 163116[99:Spt:163115.1] || -> m_main_v_state(s5,c_busy)*. % 76.16/76.36 163118[99:Res:163116.0,61.1] always3(s5) || -> . % 76.16/76.36 163119[99:SSi:163118.0,78089.0,78092.0,137727.0] || -> . % 76.16/76.36 163120[99:Spt:163119.0,163115.1,163116.0] || m_main_v_state(s5,c_busy)*+ -> . % 76.16/76.36 163121[99:Spt:163119.0,163115.0,163115.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 163125[99:MRR:163112.2,163120.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 163126[99:Res:53.1,163121.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 163128[99:MRR:163126.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 163129[99:MRR:162965.0,163128.0] || -> until2p7(s5)*. % 76.16/76.36 163130[99:MRR:201.0,163129.0] || -> until2p7(s6)* node4(s5). % 76.16/76.36 163131[100:Spt:163130.0] || -> until2p7(s6)*. % 76.16/76.36 163132[100:MRR:202.0,163131.0] || -> until2p7(s7)* node4(s6). % 76.16/76.36 163133[101:Spt:163132.0] || -> until2p7(s7)*. % 76.16/76.36 163134[101:MRR:203.0,163133.0] || -> until2p7(s8)* node4(s7). % 76.16/76.36 163135[102:Spt:163134.0] || -> until2p7(s8)*. % 76.16/76.36 163136[102:MRR:204.0,163135.0] || -> until2p7(s9)* node4(s8). % 76.16/76.36 163137[103:Spt:163136.0] || -> until2p7(s9)*. % 76.16/76.36 163138[103:MRR:205.0,163137.0] || -> until2p7(s10)* node4(s9). % 76.16/76.36 163139[104:Spt:163138.0] || -> until2p7(s10)*. % 76.16/76.36 163140[104:MRR:206.0,163139.0] || -> until2p7(s11)* node4(s10). % 76.16/76.36 163141[105:Spt:163140.0] || -> until2p7(s11)*. % 76.16/76.36 163142[105:MRR:207.0,163141.0] || -> until2p7(s12)* node4(s11). % 76.16/76.36 163143[106:Spt:163142.0] || -> until2p7(s12)*. % 76.16/76.36 163144[106:MRR:208.0,163143.0] || -> until2p7(s13)* node4(s12). % 76.16/76.36 163145[107:Spt:163144.0] || -> until2p7(s13)*. % 76.16/76.36 163146[107:MRR:209.0,163145.0] || -> until2p7(s14)* node4(s13). % 76.16/76.36 163147[108:Spt:163146.0] || -> until2p7(s14)*. % 76.16/76.36 163148[108:MRR:210.0,163147.0] || -> until2p7(s15)* node4(s14). % 76.16/76.36 163149[109:Spt:163148.0] || -> until2p7(s15)*. % 76.16/76.36 163150[109:MRR:211.0,163149.0] || -> until2p7(s16)* node4(s15). % 76.16/76.36 163151[110:Spt:163150.0] || -> until2p7(s16)*. % 76.16/76.36 163152[110:MRR:212.0,163151.0] || -> until2p7(s17)* node4(s16). % 76.16/76.36 163153[111:Spt:163152.0] || -> until2p7(s17)*. % 76.16/76.36 163154[111:MRR:213.0,163153.0] || -> until2p7(s18)* node4(s17). % 76.16/76.36 163155[112:Spt:163154.0] || -> until2p7(s18)*. % 76.16/76.36 163156[112:MRR:214.0,163155.0] || -> until2p7(s19)* node4(s18). % 76.16/76.36 163157[113:Spt:163156.0] || -> until2p7(s19)*. % 76.16/76.36 163158[113:MRR:215.0,163157.0] || -> until2p7(s20)* node4(s19). % 76.16/76.36 163159[114:Spt:163158.0] || -> until2p7(s20)*. % 76.16/76.36 163160[114:MRR:216.0,163159.0] || -> until2p7(s21)* node4(s20). % 76.16/76.36 163161[115:Spt:163160.0] || -> until2p7(s21)*. % 76.16/76.36 163162[115:MRR:217.0,163161.0] || -> until2p7(s22)* node4(s21). % 76.16/76.36 163163[116:Spt:163162.0] || -> until2p7(s22)*. % 76.16/76.36 163164[116:MRR:218.0,163163.0] || -> until2p7(s23)* node4(s22). % 76.16/76.36 163165[117:Spt:163164.0] || -> until2p7(s23)*. % 76.16/76.36 163166[117:MRR:219.0,163165.0] || -> until2p7(s24)* node4(s23). % 76.16/76.36 163167[118:Spt:163166.0] || -> until2p7(s24)*. % 76.16/76.36 163168[118:MRR:220.0,163167.0] || -> until2p7(s25)* node4(s24). % 76.16/76.36 163169[119:Spt:163168.0] || -> until2p7(s25)*. % 76.16/76.36 163170[119:MRR:221.0,163169.0] || -> until2p7(s26)* node4(s25). % 76.16/76.36 163171[120:Spt:163170.0] || -> until2p7(s26)*. % 76.16/76.36 163172[120:MRR:222.0,163171.0] || -> until2p7(s27)* node4(s26). % 76.16/76.36 163173[121:Spt:163172.0] || -> until2p7(s27)*. % 76.16/76.36 163174[121:MRR:223.0,163173.0] || -> until2p7(s28)* node4(s27). % 76.16/76.36 163175[122:Spt:163174.0] || -> until2p7(s28)*. % 76.16/76.36 163176[122:MRR:224.0,163175.0] || -> until2p7(s29)* node4(s28). % 76.16/76.36 163177[123:Spt:163176.0] || -> until2p7(s29)*. % 76.16/76.36 163178[123:MRR:225.0,163177.0] || -> until2p7(s30)* node4(s29). % 76.16/76.36 163179[124:Spt:163178.0] || -> until2p7(s30)*. % 76.16/76.36 163180[124:MRR:226.0,163179.0] || -> until2p7(s31)* node4(s30). % 76.16/76.36 163181[125:Spt:163180.0] || -> until2p7(s31)*. % 76.16/76.36 163182[125:MRR:227.0,163181.0] || -> until2p7(s32)* node4(s31). % 76.16/76.36 163183[126:Spt:163182.0] || -> until2p7(s32)*. % 76.16/76.36 163184[126:MRR:228.0,163183.0] || -> until2p7(s33)* node4(s32). % 76.16/76.36 163185[127:Spt:163184.0] || -> until2p7(s33)*. % 76.16/76.36 163186[127:MRR:229.0,163185.0] || -> until2p7(s34)* node4(s33). % 76.16/76.36 163187[128:Spt:163186.0] || -> until2p7(s34)*. % 76.16/76.36 163188[128:MRR:230.0,163187.0] || -> until2p7(s35)* node4(s34). % 76.16/76.36 163189[129:Spt:163188.0] || -> until2p7(s35)*. % 76.16/76.36 163190[129:MRR:231.0,163189.0] || -> until2p7(s36)* node4(s35). % 76.16/76.36 163191[130:Spt:163190.0] || -> until2p7(s36)*. % 76.16/76.36 163192[130:MRR:232.0,163191.0] || -> until2p7(s37)* node4(s36). % 76.16/76.36 163193[131:Spt:163192.0] || -> until2p7(s37)*. % 76.16/76.36 163194[131:MRR:235.0,163193.0] || -> until2p7(s38)* node4(s37). % 76.16/76.36 163195[132:Spt:163194.0] || -> until2p7(s38)*. % 76.16/76.36 163196[132:MRR:236.0,163195.0] || -> until2p7(s39)* node4(s38). % 76.16/76.36 163197[133:Spt:163196.0] || -> until2p7(s39)*. % 76.16/76.36 163198[133:MRR:237.0,163197.0] || -> until2p7(s40)* node4(s39). % 76.16/76.36 163199[134:Spt:163198.0] || -> until2p7(s40)*. % 76.16/76.36 163200[134:MRR:238.0,163199.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 163201[135:Spt:163200.0] || -> until2p7(s41)*. % 76.16/76.36 163202[135:MRR:239.0,163201.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 163203[136:Spt:163202.0] || -> until2p7(s42)*. % 76.16/76.36 163204[136:MRR:240.0,163203.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 163205[137:Spt:163204.0] || -> until2p7(s43)*. % 76.16/76.36 163206[137:MRR:241.0,163205.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 163207[138:Spt:163206.0] || -> until2p7(s44)*. % 76.16/76.36 163208[138:MRR:539.0,163207.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 163209[139:Spt:163208.0] || -> until2p7(s45)*. % 76.16/76.36 163210[139:MRR:544.0,163209.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 163211[140:Spt:163210.0] || -> until2p7(s46)*. % 76.16/76.36 163212[140:MRR:549.0,163211.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 163213[141:Spt:163212.0] || -> until2p7(s47)*. % 76.16/76.36 163214[141:MRR:554.0,163213.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 163215[142:Spt:163214.0] || -> until2p7(s48)*. % 76.16/76.36 163216[142:MRR:559.0,163215.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 163217[143:Spt:163216.0] || -> until2p7(s49)*. % 76.16/76.36 163218[143:MRR:194.0,163217.0] || -> node4(s49)*. % 76.16/76.36 163219[143:MRR:163125.0,163218.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 163220[143:Res:53.1,163219.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 163222[143:MRR:163220.0,78381.0] || -> . % 76.16/76.36 163223[143:Spt:163222.0,163216.0,163217.0] || until2p7(s49)*+ -> . % 76.16/76.36 163224[143:Spt:163222.0,163216.1] || -> node4(s48)*. % 76.16/76.36 163225[143:MRR:78384.0,163224.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 163228[143:Res:53.1,163225.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 163231[143:Res:163228.0,61.1] always3(s48) || -> . % 76.16/76.36 163232[143:SSi:163231.0,78281.0,78387.0,137770.0,163215.0,163224.0] || -> . % 76.16/76.36 163233[142:Spt:163232.0,163214.0,163215.0] || until2p7(s48)*+ -> . % 76.16/76.36 163234[142:Spt:163232.0,163214.1] || -> node4(s47)*. % 76.16/76.36 163236[142:MRR:777.0,163234.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 163251[142:Res:53.1,163236.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 163253[143:Spt:163251.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 163255[143:Res:163253.0,61.1] always3(s47) || -> . % 76.16/76.36 163256[143:SSi:163255.0,78277.0,78280.0,137769.0,163213.0,163234.0] || -> . % 76.16/76.36 163257[143:Spt:163256.0,163251.0,163253.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 163258[143:Spt:163256.0,163251.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 163262[143:Res:163258.0,61.1] always3(s48) || -> . % 76.16/76.36 163263[143:SSi:163262.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.36 163264[141:Spt:163263.0,163212.0,163213.0] || until2p7(s47)*+ -> . % 76.16/76.36 163265[141:Spt:163263.0,163212.1] || -> node4(s46)*. % 76.16/76.36 163267[141:MRR:780.0,163265.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 163277[141:Res:53.1,163267.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 163279[142:Spt:163277.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 163281[142:Res:163279.0,61.1] always3(s46) || -> . % 76.16/76.36 163282[142:SSi:163281.0,78272.0,78276.0,137768.0,163211.0,163265.0] || -> . % 76.16/76.36 163283[142:Spt:163282.0,163277.0,163279.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 163284[142:Spt:163282.0,163277.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 163288[142:Res:163284.0,61.1] always3(s47) || -> . % 76.16/76.36 163289[142:SSi:163288.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.36 163290[140:Spt:163289.0,163210.0,163211.0] || until2p7(s46)*+ -> . % 76.16/76.36 163291[140:Spt:163289.0,163210.1] || -> node4(s45)*. % 76.16/76.36 163293[140:MRR:783.0,163291.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 163296[140:Res:53.1,163293.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 163298[141:Spt:163296.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 163300[141:Res:163298.0,61.1] always3(s45) || -> . % 76.16/76.36 163301[141:SSi:163300.0,78268.0,78271.0,137767.0,163209.0,163291.0] || -> . % 76.16/76.36 163302[141:Spt:163301.0,163296.0,163298.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 163303[141:Spt:163301.0,163296.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 163307[141:Res:163303.0,61.1] always3(s46) || -> . % 76.16/76.36 163308[141:SSi:163307.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.36 163309[139:Spt:163308.0,163208.0,163209.0] || until2p7(s45)*+ -> . % 76.16/76.36 163310[139:Spt:163308.0,163208.1] || -> node4(s44)*. % 76.16/76.36 163312[139:MRR:786.0,163310.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 163315[139:Res:53.1,163312.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 163317[140:Spt:163315.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 163319[140:Res:163317.0,61.1] always3(s44) || -> . % 76.16/76.36 163320[140:SSi:163319.0,78263.0,78267.0,137766.0,163207.0,163310.0] || -> . % 76.16/76.36 163321[140:Spt:163320.0,163315.0,163317.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 163322[140:Spt:163320.0,163315.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 163326[140:Res:163322.0,61.1] always3(s45) || -> . % 76.16/76.36 163327[140:SSi:163326.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.36 163328[138:Spt:163327.0,163206.0,163207.0] || until2p7(s44)*+ -> . % 76.16/76.36 163329[138:Spt:163327.0,163206.1] || -> node4(s43)*. % 76.16/76.36 163331[138:MRR:789.0,163329.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 163334[138:Res:53.1,163331.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 163339[139:Spt:163334.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 163341[139:Res:163339.0,61.1] always3(s43) || -> . % 76.16/76.36 163342[139:SSi:163341.0,78259.0,78262.0,137765.0,163205.0,163329.0] || -> . % 76.16/76.36 163343[139:Spt:163342.0,163334.0,163339.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 163344[139:Spt:163342.0,163334.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 163348[139:Res:163344.0,61.1] always3(s44) || -> . % 76.16/76.36 163349[139:SSi:163348.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.36 163350[137:Spt:163349.0,163204.0,163205.0] || until2p7(s43)*+ -> . % 76.16/76.36 163351[137:Spt:163349.0,163204.1] || -> node4(s42)*. % 76.16/76.36 163353[137:MRR:792.0,163351.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 163356[137:Res:53.1,163353.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 163358[138:Spt:163356.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 163360[138:Res:163358.0,61.1] always3(s42) || -> . % 76.16/76.36 163361[138:SSi:163360.0,78254.0,78258.0,137764.0,163203.0,163351.0] || -> . % 76.16/76.36 163362[138:Spt:163361.0,163356.0,163358.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 163363[138:Spt:163361.0,163356.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 163367[138:Res:163363.0,61.1] always3(s43) || -> . % 76.16/76.36 163368[138:SSi:163367.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.36 163369[136:Spt:163368.0,163202.0,163203.0] || until2p7(s42)*+ -> . % 76.16/76.36 163370[136:Spt:163368.0,163202.1] || -> node4(s41)*. % 76.16/76.36 163372[136:MRR:795.0,163370.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 163375[136:Res:53.1,163372.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 163377[137:Spt:163375.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 163379[137:Res:163377.0,61.1] always3(s41) || -> . % 76.16/76.36 163380[137:SSi:163379.0,78250.0,78253.0,137763.0,163201.0,163370.0] || -> . % 76.16/76.36 163381[137:Spt:163380.0,163375.0,163377.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 163382[137:Spt:163380.0,163375.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 163386[137:Res:163382.0,61.1] always3(s42) || -> . % 76.16/76.36 163387[137:SSi:163386.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.36 163388[135:Spt:163387.0,163200.0,163201.0] || until2p7(s41)*+ -> . % 76.16/76.36 163389[135:Spt:163387.0,163200.1] || -> node4(s40)*. % 76.16/76.36 163391[135:MRR:798.0,163389.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 163394[135:Res:53.1,163391.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 163396[136:Spt:163394.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 163398[136:Res:163396.0,61.1] always3(s40) || -> . % 76.16/76.36 163399[136:SSi:163398.0,78245.0,78249.0,137762.0,163199.0,163389.0] || -> . % 76.16/76.36 163400[136:Spt:163399.0,163394.0,163396.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.36 163401[136:Spt:163399.0,163394.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 163405[136:Res:163401.0,61.1] always3(s41) || -> . % 76.16/76.36 163406[136:SSi:163405.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.36 163407[134:Spt:163406.0,163198.0,163199.0] || until2p7(s40)*+ -> . % 76.16/76.36 163408[134:Spt:163406.0,163198.1] || -> node4(s39)*. % 76.16/76.36 163410[134:MRR:801.0,163408.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.36 163413[134:Res:53.1,163410.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.36 163418[135:Spt:163413.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 163420[135:Res:163418.0,61.1] always3(s39) || -> . % 76.16/76.36 163421[135:SSi:163420.0,78241.0,78244.0,137761.0,163197.0,163408.0] || -> . % 76.16/76.36 163422[135:Spt:163421.0,163413.0,163418.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.36 163423[135:Spt:163421.0,163413.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 163427[135:Res:163423.0,61.1] always3(s40) || -> . % 76.16/76.36 163428[135:SSi:163427.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.36 163429[133:Spt:163428.0,163196.0,163197.0] || until2p7(s39)*+ -> . % 76.16/76.36 163430[133:Spt:163428.0,163196.1] || -> node4(s38)*. % 76.16/76.36 163432[133:MRR:804.0,163430.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.36 163435[133:Res:53.1,163432.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.36 163437[134:Spt:163435.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 163439[134:Res:163437.0,61.1] always3(s38) || -> . % 76.16/76.36 163440[134:SSi:163439.0,78236.0,78240.0,137760.0,163195.0,163430.0] || -> . % 76.16/76.36 163441[134:Spt:163440.0,163435.0,163437.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.36 163442[134:Spt:163440.0,163435.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 163446[134:Res:163442.0,61.1] always3(s39) || -> . % 76.16/76.36 163447[134:SSi:163446.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.36 163448[132:Spt:163447.0,163194.0,163195.0] || until2p7(s38)*+ -> . % 76.16/76.36 163449[132:Spt:163447.0,163194.1] || -> node4(s37)*. % 76.16/76.36 163451[132:MRR:807.0,163449.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.36 163454[132:Res:53.1,163451.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.36 163456[133:Spt:163454.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 163458[133:Res:163456.0,61.1] always3(s37) || -> . % 76.16/76.36 163459[133:SSi:163458.0,78232.0,78235.0,137759.0,163193.0,163449.0] || -> . % 76.16/76.36 163460[133:Spt:163459.0,163454.0,163456.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.36 163461[133:Spt:163459.0,163454.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 163465[133:Res:163461.0,61.1] always3(s38) || -> . % 76.16/76.36 163466[133:SSi:163465.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.36 163467[131:Spt:163466.0,163192.0,163193.0] || until2p7(s37)*+ -> . % 76.16/76.36 163468[131:Spt:163466.0,163192.1] || -> node4(s36)*. % 76.16/76.36 163470[131:MRR:810.0,163468.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.36 163473[131:Res:53.1,163470.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.36 163475[132:Spt:163473.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 163477[132:Res:163475.0,61.1] always3(s36) || -> . % 76.16/76.36 163478[132:SSi:163477.0,78227.0,78231.0,137758.0,163191.0,163468.0] || -> . % 76.16/76.36 163479[132:Spt:163478.0,163473.0,163475.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.36 163480[132:Spt:163478.0,163473.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 163484[132:Res:163480.0,61.1] always3(s37) || -> . % 76.16/76.36 163485[132:SSi:163484.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.36 163486[130:Spt:163485.0,163190.0,163191.0] || until2p7(s36)*+ -> . % 76.16/76.36 163487[130:Spt:163485.0,163190.1] || -> node4(s35)*. % 76.16/76.36 163489[130:MRR:813.0,163487.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.36 163492[130:Res:53.1,163489.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.36 163497[131:Spt:163492.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 163499[131:Res:163497.0,61.1] always3(s35) || -> . % 76.16/76.36 163500[131:SSi:163499.0,78223.0,78226.0,137757.0,163189.0,163487.0] || -> . % 76.16/76.36 163501[131:Spt:163500.0,163492.0,163497.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.36 163502[131:Spt:163500.0,163492.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 163506[131:Res:163502.0,61.1] always3(s36) || -> . % 76.16/76.36 163507[131:SSi:163506.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.36 163508[129:Spt:163507.0,163188.0,163189.0] || until2p7(s35)*+ -> . % 76.16/76.36 163509[129:Spt:163507.0,163188.1] || -> node4(s34)*. % 76.16/76.36 163511[129:MRR:816.0,163509.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.36 163514[129:Res:53.1,163511.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.36 163516[130:Spt:163514.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 163518[130:Res:163516.0,61.1] always3(s34) || -> . % 76.16/76.36 163519[130:SSi:163518.0,78218.0,78222.0,137756.0,163187.0,163509.0] || -> . % 76.16/76.36 163520[130:Spt:163519.0,163514.0,163516.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.36 163521[130:Spt:163519.0,163514.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 163525[130:Res:163521.0,61.1] always3(s35) || -> . % 76.16/76.36 163526[130:SSi:163525.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.36 163527[128:Spt:163526.0,163186.0,163187.0] || until2p7(s34)*+ -> . % 76.16/76.36 163528[128:Spt:163526.0,163186.1] || -> node4(s33)*. % 76.16/76.36 163530[128:MRR:819.0,163528.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.36 163533[128:Res:53.1,163530.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.36 163535[129:Spt:163533.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.36 163537[129:Res:163535.0,61.1] always3(s33) || -> . % 76.16/76.36 163538[129:SSi:163537.0,78214.0,78217.0,137755.0,163185.0,163528.0] || -> . % 76.16/76.36 163539[129:Spt:163538.0,163533.0,163535.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.36 163540[129:Spt:163538.0,163533.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 163544[129:Res:163540.0,61.1] always3(s34) || -> . % 76.16/76.36 163545[129:SSi:163544.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.36 163546[127:Spt:163545.0,163184.0,163185.0] || until2p7(s33)*+ -> . % 76.16/76.36 163547[127:Spt:163545.0,163184.1] || -> node4(s32)*. % 76.16/76.36 163549[127:MRR:822.0,163547.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.36 163552[127:Res:53.1,163549.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.36 163554[128:Spt:163552.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.36 163556[128:Res:163554.0,61.1] always3(s32) || -> . % 76.16/76.36 163557[128:SSi:163556.0,78209.0,78213.0,137754.0,163183.0,163547.0] || -> . % 76.16/76.36 163558[128:Spt:163557.0,163552.0,163554.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.36 163559[128:Spt:163557.0,163552.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.36 163563[128:Res:163559.0,61.1] always3(s33) || -> . % 76.16/76.36 163564[128:SSi:163563.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.36 163565[126:Spt:163564.0,163182.0,163183.0] || until2p7(s32)*+ -> . % 76.16/76.36 163566[126:Spt:163564.0,163182.1] || -> node4(s31)*. % 76.16/76.36 163568[126:MRR:825.0,163566.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.36 163571[126:Res:53.1,163568.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.36 163576[127:Spt:163571.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.36 163578[127:Res:163576.0,61.1] always3(s31) || -> . % 76.16/76.36 163579[127:SSi:163578.0,78205.0,78208.0,137753.0,163181.0,163566.0] || -> . % 76.16/76.36 163580[127:Spt:163579.0,163571.0,163576.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.36 163581[127:Spt:163579.0,163571.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.36 163585[127:Res:163581.0,61.1] always3(s32) || -> . % 76.16/76.36 163586[127:SSi:163585.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.36 163587[125:Spt:163586.0,163180.0,163181.0] || until2p7(s31)*+ -> . % 76.16/76.36 163588[125:Spt:163586.0,163180.1] || -> node4(s30)*. % 76.16/76.36 163590[125:MRR:828.0,163588.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.36 163593[125:Res:53.1,163590.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.36 163595[126:Spt:163593.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.36 163597[126:Res:163595.0,61.1] always3(s30) || -> . % 76.16/76.36 163598[126:SSi:163597.0,78200.0,78204.0,137752.0,163179.0,163588.0] || -> . % 76.16/76.36 163599[126:Spt:163598.0,163593.0,163595.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.36 163600[126:Spt:163598.0,163593.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.36 163604[126:Res:163600.0,61.1] always3(s31) || -> . % 76.16/76.36 163605[126:SSi:163604.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.36 163606[124:Spt:163605.0,163178.0,163179.0] || until2p7(s30)*+ -> . % 76.16/76.36 163607[124:Spt:163605.0,163178.1] || -> node4(s29)*. % 76.16/76.36 163609[124:MRR:831.0,163607.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.36 163612[124:Res:53.1,163609.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.36 163614[125:Spt:163612.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.36 163616[125:Res:163614.0,61.1] always3(s29) || -> . % 76.16/76.36 163617[125:SSi:163616.0,78196.0,78199.0,137751.0,163177.0,163607.0] || -> . % 76.16/76.36 163618[125:Spt:163617.0,163612.0,163614.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.36 163619[125:Spt:163617.0,163612.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.36 163623[125:Res:163619.0,61.1] always3(s30) || -> . % 76.16/76.36 163624[125:SSi:163623.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.36 163625[123:Spt:163624.0,163176.0,163177.0] || until2p7(s29)*+ -> . % 76.16/76.36 163626[123:Spt:163624.0,163176.1] || -> node4(s28)*. % 76.16/76.36 163628[123:MRR:834.0,163626.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.36 163631[123:Res:53.1,163628.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.36 163633[124:Spt:163631.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.36 163635[124:Res:163633.0,61.1] always3(s28) || -> . % 76.16/76.36 163636[124:SSi:163635.0,78191.0,78195.0,137750.0,163175.0,163626.0] || -> . % 76.16/76.36 163637[124:Spt:163636.0,163631.0,163633.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.36 163638[124:Spt:163636.0,163631.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.36 163642[124:Res:163638.0,61.1] always3(s29) || -> . % 76.16/76.36 163643[124:SSi:163642.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.36 163644[122:Spt:163643.0,163174.0,163175.0] || until2p7(s28)*+ -> . % 76.16/76.36 163645[122:Spt:163643.0,163174.1] || -> node4(s27)*. % 76.16/76.36 163647[122:MRR:837.0,163645.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.36 163650[122:Res:53.1,163647.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.36 163655[123:Spt:163650.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.36 163657[123:Res:163655.0,61.1] always3(s27) || -> . % 76.16/76.36 163658[123:SSi:163657.0,78187.0,78190.0,137749.0,163173.0,163645.0] || -> . % 76.16/76.36 163659[123:Spt:163658.0,163650.0,163655.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.36 163660[123:Spt:163658.0,163650.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.36 163664[123:Res:163660.0,61.1] always3(s28) || -> . % 76.16/76.36 163665[123:SSi:163664.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.36 163666[121:Spt:163665.0,163172.0,163173.0] || until2p7(s27)*+ -> . % 76.16/76.36 163667[121:Spt:163665.0,163172.1] || -> node4(s26)*. % 76.16/76.36 163669[121:MRR:840.0,163667.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.36 163672[121:Res:53.1,163669.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.36 163674[122:Spt:163672.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.36 163676[122:Res:163674.0,61.1] always3(s26) || -> . % 76.16/76.36 163677[122:SSi:163676.0,78182.0,78186.0,137748.0,163171.0,163667.0] || -> . % 76.16/76.36 163678[122:Spt:163677.0,163672.0,163674.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.36 163679[122:Spt:163677.0,163672.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.36 163683[122:Res:163679.0,61.1] always3(s27) || -> . % 76.16/76.36 163684[122:SSi:163683.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.36 163685[120:Spt:163684.0,163170.0,163171.0] || until2p7(s26)*+ -> . % 76.16/76.36 163686[120:Spt:163684.0,163170.1] || -> node4(s25)*. % 76.16/76.36 163688[120:MRR:843.0,163686.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.36 163691[120:Res:53.1,163688.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.36 163693[121:Spt:163691.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.36 163695[121:Res:163693.0,61.1] always3(s25) || -> . % 76.16/76.36 163696[121:SSi:163695.0,78178.0,78181.0,137747.0,163169.0,163686.0] || -> . % 76.16/76.36 163697[121:Spt:163696.0,163691.0,163693.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.36 163698[121:Spt:163696.0,163691.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.36 163702[121:Res:163698.0,61.1] always3(s26) || -> . % 76.16/76.36 163703[121:SSi:163702.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.36 163704[119:Spt:163703.0,163168.0,163169.0] || until2p7(s25)*+ -> . % 76.16/76.36 163705[119:Spt:163703.0,163168.1] || -> node4(s24)*. % 76.16/76.36 163707[119:MRR:846.0,163705.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.36 163710[119:Res:53.1,163707.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.36 163712[120:Spt:163710.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.36 163714[120:Res:163712.0,61.1] always3(s24) || -> . % 76.16/76.36 163715[120:SSi:163714.0,78173.0,78177.0,137746.0,163167.0,163705.0] || -> . % 76.16/76.36 163716[120:Spt:163715.0,163710.0,163712.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.36 163717[120:Spt:163715.0,163710.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.36 163721[120:Res:163717.0,61.1] always3(s25) || -> . % 76.16/76.36 163722[120:SSi:163721.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.36 163723[118:Spt:163722.0,163166.0,163167.0] || until2p7(s24)*+ -> . % 76.16/76.36 163724[118:Spt:163722.0,163166.1] || -> node4(s23)*. % 76.16/76.36 163726[118:MRR:849.0,163724.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.36 163729[118:Res:53.1,163726.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.36 163734[119:Spt:163729.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.36 163736[119:Res:163734.0,61.1] always3(s23) || -> . % 76.16/76.36 163737[119:SSi:163736.0,78169.0,78172.0,137745.0,163165.0,163724.0] || -> . % 76.16/76.36 163738[119:Spt:163737.0,163729.0,163734.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.36 163739[119:Spt:163737.0,163729.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.36 163743[119:Res:163739.0,61.1] always3(s24) || -> . % 76.16/76.36 163744[119:SSi:163743.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.36 163745[117:Spt:163744.0,163164.0,163165.0] || until2p7(s23)*+ -> . % 76.16/76.36 163746[117:Spt:163744.0,163164.1] || -> node4(s22)*. % 76.16/76.36 163748[117:MRR:852.0,163746.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.36 163751[117:Res:53.1,163748.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.36 163753[118:Spt:163751.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.36 163755[118:Res:163753.0,61.1] always3(s22) || -> . % 76.16/76.36 163756[118:SSi:163755.0,78164.0,78168.0,137744.0,163163.0,163746.0] || -> . % 76.16/76.36 163757[118:Spt:163756.0,163751.0,163753.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.36 163758[118:Spt:163756.0,163751.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.36 163762[118:Res:163758.0,61.1] always3(s23) || -> . % 76.16/76.36 163763[118:SSi:163762.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.36 163764[116:Spt:163763.0,163162.0,163163.0] || until2p7(s22)*+ -> . % 76.16/76.36 163765[116:Spt:163763.0,163162.1] || -> node4(s21)*. % 76.16/76.36 163767[116:MRR:855.0,163765.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.36 163770[116:Res:53.1,163767.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.36 163772[117:Spt:163770.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.36 163774[117:Res:163772.0,61.1] always3(s21) || -> . % 76.16/76.36 163775[117:SSi:163774.0,78160.0,78163.0,137743.0,163161.0,163765.0] || -> . % 76.16/76.36 163776[117:Spt:163775.0,163770.0,163772.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.36 163777[117:Spt:163775.0,163770.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.36 163781[117:Res:163777.0,61.1] always3(s22) || -> . % 76.16/76.36 163782[117:SSi:163781.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.36 163783[115:Spt:163782.0,163160.0,163161.0] || until2p7(s21)*+ -> . % 76.16/76.36 163784[115:Spt:163782.0,163160.1] || -> node4(s20)*. % 76.16/76.36 163786[115:MRR:858.0,163784.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.36 163789[115:Res:53.1,163786.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.36 163791[116:Spt:163789.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.36 163793[116:Res:163791.0,61.1] always3(s20) || -> . % 76.16/76.36 163794[116:SSi:163793.0,78155.0,78159.0,137742.0,163159.0,163784.0] || -> . % 76.16/76.36 163795[116:Spt:163794.0,163789.0,163791.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.36 163796[116:Spt:163794.0,163789.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.36 163800[116:Res:163796.0,61.1] always3(s21) || -> . % 76.16/76.36 163801[116:SSi:163800.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.36 163802[114:Spt:163801.0,163158.0,163159.0] || until2p7(s20)*+ -> . % 76.16/76.36 163803[114:Spt:163801.0,163158.1] || -> node4(s19)*. % 76.16/76.36 163805[114:MRR:861.0,163803.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.36 163808[114:Res:53.1,163805.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.36 163813[115:Spt:163808.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.36 163815[115:Res:163813.0,61.1] always3(s19) || -> . % 76.16/76.36 163816[115:SSi:163815.0,78151.0,78154.0,137741.0,163157.0,163803.0] || -> . % 76.16/76.36 163817[115:Spt:163816.0,163808.0,163813.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.36 163818[115:Spt:163816.0,163808.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.36 163822[115:Res:163818.0,61.1] always3(s20) || -> . % 76.16/76.36 163823[115:SSi:163822.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.36 163824[113:Spt:163823.0,163156.0,163157.0] || until2p7(s19)*+ -> . % 76.16/76.36 163825[113:Spt:163823.0,163156.1] || -> node4(s18)*. % 76.16/76.36 163827[113:MRR:864.0,163825.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.36 163830[113:Res:53.1,163827.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.36 163832[114:Spt:163830.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.36 163834[114:Res:163832.0,61.1] always3(s18) || -> . % 76.16/76.36 163835[114:SSi:163834.0,78146.0,78150.0,137740.0,163155.0,163825.0] || -> . % 76.16/76.36 163836[114:Spt:163835.0,163830.0,163832.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.36 163837[114:Spt:163835.0,163830.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.36 163841[114:Res:163837.0,61.1] always3(s19) || -> . % 76.16/76.36 163842[114:SSi:163841.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.36 163843[112:Spt:163842.0,163154.0,163155.0] || until2p7(s18)*+ -> . % 76.16/76.36 163844[112:Spt:163842.0,163154.1] || -> node4(s17)*. % 76.16/76.36 163846[112:MRR:867.0,163844.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.36 163849[112:Res:53.1,163846.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.36 163851[113:Spt:163849.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.36 163853[113:Res:163851.0,61.1] always3(s17) || -> . % 76.16/76.36 163854[113:SSi:163853.0,78142.0,78145.0,137739.0,163153.0,163844.0] || -> . % 76.16/76.36 163855[113:Spt:163854.0,163849.0,163851.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.36 163856[113:Spt:163854.0,163849.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.36 163860[113:Res:163856.0,61.1] always3(s18) || -> . % 76.16/76.36 163861[113:SSi:163860.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.36 163862[111:Spt:163861.0,163152.0,163153.0] || until2p7(s17)*+ -> . % 76.16/76.36 163863[111:Spt:163861.0,163152.1] || -> node4(s16)*. % 76.16/76.36 163865[111:MRR:870.0,163863.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.36 163868[111:Res:53.1,163865.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.36 163870[112:Spt:163868.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.36 163872[112:Res:163870.0,61.1] always3(s16) || -> . % 76.16/76.36 163873[112:SSi:163872.0,78137.0,78141.0,137738.0,163151.0,163863.0] || -> . % 76.16/76.36 163874[112:Spt:163873.0,163868.0,163870.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.36 163875[112:Spt:163873.0,163868.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.36 163879[112:Res:163875.0,61.1] always3(s17) || -> . % 76.16/76.36 163880[112:SSi:163879.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.36 163881[110:Spt:163880.0,163150.0,163151.0] || until2p7(s16)*+ -> . % 76.16/76.36 163882[110:Spt:163880.0,163150.1] || -> node4(s15)*. % 76.16/76.36 163884[110:MRR:873.0,163882.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.36 163887[110:Res:53.1,163884.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.36 163892[111:Spt:163887.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.36 163894[111:Res:163892.0,61.1] always3(s15) || -> . % 76.16/76.36 163895[111:SSi:163894.0,78133.0,78136.0,137737.0,163149.0,163882.0] || -> . % 76.16/76.36 163896[111:Spt:163895.0,163887.0,163892.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.36 163897[111:Spt:163895.0,163887.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.36 163901[111:Res:163897.0,61.1] always3(s16) || -> . % 76.16/76.36 163902[111:SSi:163901.0,78137.0,78141.0,137738.0] || -> . % 76.16/76.36 163903[109:Spt:163902.0,163148.0,163149.0] || until2p7(s15)*+ -> . % 76.16/76.36 163904[109:Spt:163902.0,163148.1] || -> node4(s14)*. % 76.16/76.36 163906[109:MRR:876.0,163904.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.36 163909[109:Res:53.1,163906.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.36 163911[110:Spt:163909.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.36 163913[110:Res:163911.0,61.1] always3(s14) || -> . % 76.16/76.36 163914[110:SSi:163913.0,78128.0,78132.0,137736.0,163147.0,163904.0] || -> . % 76.16/76.36 163915[110:Spt:163914.0,163909.0,163911.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.36 163916[110:Spt:163914.0,163909.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.36 163920[110:Res:163916.0,61.1] always3(s15) || -> . % 76.16/76.36 163921[110:SSi:163920.0,78133.0,78136.0,137737.0] || -> . % 76.16/76.36 163922[108:Spt:163921.0,163146.0,163147.0] || until2p7(s14)*+ -> . % 76.16/76.36 163923[108:Spt:163921.0,163146.1] || -> node4(s13)*. % 76.16/76.36 163925[108:MRR:879.0,163923.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.36 163928[108:Res:53.1,163925.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.36 163930[109:Spt:163928.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.36 163932[109:Res:163930.0,61.1] always3(s13) || -> . % 76.16/76.36 163933[109:SSi:163932.0,78124.0,78127.0,137735.0,163145.0,163923.0] || -> . % 76.16/76.36 163934[109:Spt:163933.0,163928.0,163930.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.36 163935[109:Spt:163933.0,163928.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.36 163939[109:Res:163935.0,61.1] always3(s14) || -> . % 76.16/76.36 163940[109:SSi:163939.0,78128.0,78132.0,137736.0] || -> . % 76.16/76.36 163941[107:Spt:163940.0,163144.0,163145.0] || until2p7(s13)*+ -> . % 76.16/76.36 163942[107:Spt:163940.0,163144.1] || -> node4(s12)*. % 76.16/76.36 163944[107:MRR:882.0,163942.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.36 163947[107:Res:53.1,163944.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.36 163949[108:Spt:163947.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.36 163951[108:Res:163949.0,61.1] always3(s12) || -> . % 76.16/76.36 163952[108:SSi:163951.0,78119.0,78123.0,137734.0,163143.0,163942.0] || -> . % 76.16/76.36 163953[108:Spt:163952.0,163947.0,163949.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.36 163954[108:Spt:163952.0,163947.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.36 163958[108:Res:163954.0,61.1] always3(s13) || -> . % 76.16/76.36 163959[108:SSi:163958.0,78124.0,78127.0,137735.0] || -> . % 76.16/76.36 163960[106:Spt:163959.0,163142.0,163143.0] || until2p7(s12)*+ -> . % 76.16/76.36 163961[106:Spt:163959.0,163142.1] || -> node4(s11)*. % 76.16/76.36 163963[106:MRR:885.0,163961.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.36 163966[106:Res:53.1,163963.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.36 163971[107:Spt:163966.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.36 163973[107:Res:163971.0,61.1] always3(s11) || -> . % 76.16/76.36 163974[107:SSi:163973.0,78115.0,78118.0,137733.0,163141.0,163961.0] || -> . % 76.16/76.36 163975[107:Spt:163974.0,163966.0,163971.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.36 163976[107:Spt:163974.0,163966.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.36 163980[107:Res:163976.0,61.1] always3(s12) || -> . % 76.16/76.36 163981[107:SSi:163980.0,78119.0,78123.0,137734.0] || -> . % 76.16/76.36 163982[105:Spt:163981.0,163140.0,163141.0] || until2p7(s11)*+ -> . % 76.16/76.36 163983[105:Spt:163981.0,163140.1] || -> node4(s10)*. % 76.16/76.36 163985[105:MRR:888.0,163983.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.36 163988[105:Res:53.1,163985.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.36 163990[106:Spt:163988.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.36 163992[106:Res:163990.0,61.1] always3(s10) || -> . % 76.16/76.36 163993[106:SSi:163992.0,78110.0,78114.0,137732.0,163139.0,163983.0] || -> . % 76.16/76.36 163994[106:Spt:163993.0,163988.0,163990.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.36 163995[106:Spt:163993.0,163988.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.36 163999[106:Res:163995.0,61.1] always3(s11) || -> . % 76.16/76.36 164000[106:SSi:163999.0,78115.0,78118.0,137733.0] || -> . % 76.16/76.36 164001[104:Spt:164000.0,163138.0,163139.0] || until2p7(s10)*+ -> . % 76.16/76.36 164002[104:Spt:164000.0,163138.1] || -> node4(s9)*. % 76.16/76.36 164004[104:MRR:891.0,164002.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.36 164007[104:Res:53.1,164004.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.36 164009[105:Spt:164007.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.36 164011[105:Res:164009.0,61.1] always3(s9) || -> . % 76.16/76.36 164012[105:SSi:164011.0,78106.0,78109.0,137731.0,163137.0,164002.0] || -> . % 76.16/76.36 164013[105:Spt:164012.0,164007.0,164009.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.36 164014[105:Spt:164012.0,164007.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.36 164018[105:Res:164014.0,61.1] always3(s10) || -> . % 76.16/76.36 164019[105:SSi:164018.0,78110.0,78114.0,137732.0] || -> . % 76.16/76.36 164020[103:Spt:164019.0,163136.0,163137.0] || until2p7(s9)*+ -> . % 76.16/76.36 164021[103:Spt:164019.0,163136.1] || -> node4(s8)*. % 76.16/76.36 164023[103:MRR:894.0,164021.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.36 164026[103:Res:53.1,164023.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.36 164028[104:Spt:164026.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.36 164030[104:Res:164028.0,61.1] always3(s8) || -> . % 76.16/76.36 164031[104:SSi:164030.0,78101.0,78105.0,137730.0,163135.0,164021.0] || -> . % 76.16/76.36 164032[104:Spt:164031.0,164026.0,164028.0] || m_main_v_state(s8,c_busy)* -> . % 76.16/76.36 164033[104:Spt:164031.0,164026.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.36 164037[104:Res:164033.0,61.1] always3(s9) || -> . % 76.16/76.36 164038[104:SSi:164037.0,78106.0,78109.0,137731.0] || -> . % 76.16/76.36 164039[102:Spt:164038.0,163134.0,163135.0] || until2p7(s8)*+ -> . % 76.16/76.36 164040[102:Spt:164038.0,163134.1] || -> node4(s7)*. % 76.16/76.36 164042[102:MRR:897.0,164040.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.16/76.36 164045[102:Res:53.1,164042.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.16/76.36 164050[103:Spt:164045.0] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.36 164052[103:Res:164050.0,61.1] always3(s7) || -> . % 76.16/76.36 164053[103:SSi:164052.0,78097.0,78100.0,137729.0,163133.0,164040.0] || -> . % 76.16/76.36 164054[103:Spt:164053.0,164045.0,164050.0] || m_main_v_state(s7,c_busy)* -> . % 76.16/76.36 164055[103:Spt:164053.0,164045.1] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.36 164059[103:Res:164055.0,61.1] always3(s8) || -> . % 76.16/76.36 164060[103:SSi:164059.0,78101.0,78105.0,137730.0] || -> . % 76.16/76.36 164061[101:Spt:164060.0,163132.0,163133.0] || until2p7(s7)*+ -> . % 76.16/76.36 164062[101:Spt:164060.0,163132.1] || -> node4(s6)*. % 76.16/76.36 164064[101:MRR:900.0,164062.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.16/76.36 164067[101:Res:53.1,164064.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.16/76.36 164069[102:Spt:164067.0] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.36 164071[102:Res:164069.0,61.1] always3(s6) || -> . % 76.16/76.36 164072[102:SSi:164071.0,78093.0,78096.0,137728.0,163131.0,164062.0] || -> . % 76.16/76.36 164073[102:Spt:164072.0,164067.0,164069.0] || m_main_v_state(s6,c_busy)* -> . % 76.16/76.36 164074[102:Spt:164072.0,164067.1] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.36 164078[102:Res:164074.0,61.1] always3(s7) || -> . % 76.16/76.36 164079[102:SSi:164078.0,78097.0,78100.0,137729.0] || -> . % 76.16/76.36 164080[100:Spt:164079.0,163130.0,163131.0] || until2p7(s6)*+ -> . % 76.16/76.36 164081[100:Spt:164079.0,163130.1] || -> node4(s5)*. % 76.16/76.36 164083[100:MRR:903.0,164081.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.16/76.36 164086[100:Res:53.1,164083.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.16/76.36 164088[100:MRR:164086.0,163120.0] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.36 164090[100:Res:164088.0,61.1] always3(s6) || -> . % 76.16/76.36 164091[100:SSi:164090.0,78093.0,78096.0,137728.0] || -> . % 76.16/76.36 164092[98:Spt:164091.0,162958.0,162961.0] || trans(s49,s5)*+ -> . % 76.16/76.36 164093[98:Spt:164091.0,162958.1] || -> node2(s49,s4)*. % 76.16/76.36 164095[98:MRR:162960.1,164092.0] xuntil6(s49) || -> until2p7(s4)*. % 76.16/76.36 164096[98:Res:164093.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s4,c_busy)*. % 76.16/76.36 164249[98:SoR:164096.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s4,c_busy)*. % 76.16/76.36 164251[98:SoR:164249.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s4,c_busy)* xuntil6(s49). % 76.16/76.36 164252[98:SSi:164251.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s4,c_busy)* xuntil6(s49). % 76.16/76.36 164253[99:Spt:164252.1] || -> m_main_v_state(s4,c_busy)*. % 76.16/76.36 164255[99:Res:164253.0,61.1] always3(s4) || -> . % 76.16/76.36 164256[99:SSi:164255.0,78085.0,78088.0,137726.0] || -> . % 76.16/76.36 164257[99:Spt:164256.0,164252.1,164253.0] || m_main_v_state(s4,c_busy)*+ -> . % 76.16/76.36 164258[99:Spt:164256.0,164252.0,164252.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 164261[99:MRR:164249.2,164257.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 164262[99:Res:53.1,164258.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 164264[99:MRR:164262.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 164265[99:MRR:164095.0,164264.0] || -> until2p7(s4)*. % 76.16/76.36 164266[99:MRR:200.0,164265.0] || -> until2p7(s5)* node4(s4). % 76.16/76.36 164267[100:Spt:164266.0] || -> until2p7(s5)*. % 76.16/76.36 164268[100:MRR:201.0,164267.0] || -> until2p7(s6)* node4(s5). % 76.16/76.36 164269[101:Spt:164268.0] || -> until2p7(s6)*. % 76.16/76.36 164270[101:MRR:202.0,164269.0] || -> until2p7(s7)* node4(s6). % 76.16/76.36 164271[102:Spt:164270.0] || -> until2p7(s7)*. % 76.16/76.36 164272[102:MRR:203.0,164271.0] || -> until2p7(s8)* node4(s7). % 76.16/76.36 164273[103:Spt:164272.0] || -> until2p7(s8)*. % 76.16/76.36 164274[103:MRR:204.0,164273.0] || -> until2p7(s9)* node4(s8). % 76.16/76.36 164275[104:Spt:164274.0] || -> until2p7(s9)*. % 76.16/76.36 164276[104:MRR:205.0,164275.0] || -> until2p7(s10)* node4(s9). % 76.16/76.36 164277[105:Spt:164276.0] || -> until2p7(s10)*. % 76.16/76.36 164278[105:MRR:206.0,164277.0] || -> until2p7(s11)* node4(s10). % 76.16/76.36 164279[106:Spt:164278.0] || -> until2p7(s11)*. % 76.16/76.36 164280[106:MRR:207.0,164279.0] || -> until2p7(s12)* node4(s11). % 76.16/76.36 164281[107:Spt:164280.0] || -> until2p7(s12)*. % 76.16/76.36 164282[107:MRR:208.0,164281.0] || -> until2p7(s13)* node4(s12). % 76.16/76.36 164283[108:Spt:164282.0] || -> until2p7(s13)*. % 76.16/76.36 164284[108:MRR:209.0,164283.0] || -> until2p7(s14)* node4(s13). % 76.16/76.36 164285[109:Spt:164284.0] || -> until2p7(s14)*. % 76.16/76.36 164286[109:MRR:210.0,164285.0] || -> until2p7(s15)* node4(s14). % 76.16/76.36 164287[110:Spt:164286.0] || -> until2p7(s15)*. % 76.16/76.36 164288[110:MRR:211.0,164287.0] || -> until2p7(s16)* node4(s15). % 76.16/76.36 164289[111:Spt:164288.0] || -> until2p7(s16)*. % 76.16/76.36 164290[111:MRR:212.0,164289.0] || -> until2p7(s17)* node4(s16). % 76.16/76.36 164291[112:Spt:164290.0] || -> until2p7(s17)*. % 76.16/76.36 164292[112:MRR:213.0,164291.0] || -> until2p7(s18)* node4(s17). % 76.16/76.36 164293[113:Spt:164292.0] || -> until2p7(s18)*. % 76.16/76.36 164294[113:MRR:214.0,164293.0] || -> until2p7(s19)* node4(s18). % 76.16/76.36 164295[114:Spt:164294.0] || -> until2p7(s19)*. % 76.16/76.36 164296[114:MRR:215.0,164295.0] || -> until2p7(s20)* node4(s19). % 76.16/76.36 164297[115:Spt:164296.0] || -> until2p7(s20)*. % 76.16/76.36 164298[115:MRR:216.0,164297.0] || -> until2p7(s21)* node4(s20). % 76.16/76.36 164299[116:Spt:164298.0] || -> until2p7(s21)*. % 76.16/76.36 164300[116:MRR:217.0,164299.0] || -> until2p7(s22)* node4(s21). % 76.16/76.36 164301[117:Spt:164300.0] || -> until2p7(s22)*. % 76.16/76.36 164302[117:MRR:218.0,164301.0] || -> until2p7(s23)* node4(s22). % 76.16/76.36 164303[118:Spt:164302.0] || -> until2p7(s23)*. % 76.16/76.36 164304[118:MRR:219.0,164303.0] || -> until2p7(s24)* node4(s23). % 76.16/76.36 164305[119:Spt:164304.0] || -> until2p7(s24)*. % 76.16/76.36 164306[119:MRR:220.0,164305.0] || -> until2p7(s25)* node4(s24). % 76.16/76.36 164307[120:Spt:164306.0] || -> until2p7(s25)*. % 76.16/76.36 164308[120:MRR:221.0,164307.0] || -> until2p7(s26)* node4(s25). % 76.16/76.36 164309[121:Spt:164308.0] || -> until2p7(s26)*. % 76.16/76.36 164310[121:MRR:222.0,164309.0] || -> until2p7(s27)* node4(s26). % 76.16/76.36 164311[122:Spt:164310.0] || -> until2p7(s27)*. % 76.16/76.36 164312[122:MRR:223.0,164311.0] || -> until2p7(s28)* node4(s27). % 76.16/76.36 164313[123:Spt:164312.0] || -> until2p7(s28)*. % 76.16/76.36 164314[123:MRR:224.0,164313.0] || -> until2p7(s29)* node4(s28). % 76.16/76.36 164315[124:Spt:164314.0] || -> until2p7(s29)*. % 76.16/76.36 164316[124:MRR:225.0,164315.0] || -> until2p7(s30)* node4(s29). % 76.16/76.36 164317[125:Spt:164316.0] || -> until2p7(s30)*. % 76.16/76.36 164318[125:MRR:226.0,164317.0] || -> until2p7(s31)* node4(s30). % 76.16/76.36 164319[126:Spt:164318.0] || -> until2p7(s31)*. % 76.16/76.36 164320[126:MRR:227.0,164319.0] || -> until2p7(s32)* node4(s31). % 76.16/76.36 164321[127:Spt:164320.0] || -> until2p7(s32)*. % 76.16/76.36 164322[127:MRR:228.0,164321.0] || -> until2p7(s33)* node4(s32). % 76.16/76.36 164323[128:Spt:164322.0] || -> until2p7(s33)*. % 76.16/76.36 164324[128:MRR:229.0,164323.0] || -> until2p7(s34)* node4(s33). % 76.16/76.36 164325[129:Spt:164324.0] || -> until2p7(s34)*. % 76.16/76.36 164326[129:MRR:230.0,164325.0] || -> until2p7(s35)* node4(s34). % 76.16/76.36 164327[130:Spt:164326.0] || -> until2p7(s35)*. % 76.16/76.36 164328[130:MRR:231.0,164327.0] || -> until2p7(s36)* node4(s35). % 76.16/76.36 164329[131:Spt:164328.0] || -> until2p7(s36)*. % 76.16/76.36 164330[131:MRR:232.0,164329.0] || -> until2p7(s37)* node4(s36). % 76.16/76.36 164331[132:Spt:164330.0] || -> until2p7(s37)*. % 76.16/76.36 164332[132:MRR:235.0,164331.0] || -> until2p7(s38)* node4(s37). % 76.16/76.36 164333[133:Spt:164332.0] || -> until2p7(s38)*. % 76.16/76.36 164334[133:MRR:236.0,164333.0] || -> until2p7(s39)* node4(s38). % 76.16/76.36 164335[134:Spt:164334.0] || -> until2p7(s39)*. % 76.16/76.36 164336[134:MRR:237.0,164335.0] || -> until2p7(s40)* node4(s39). % 76.16/76.36 164337[135:Spt:164336.0] || -> until2p7(s40)*. % 76.16/76.36 164338[135:MRR:238.0,164337.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 164339[136:Spt:164338.0] || -> until2p7(s41)*. % 76.16/76.36 164340[136:MRR:239.0,164339.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 164341[137:Spt:164340.0] || -> until2p7(s42)*. % 76.16/76.36 164342[137:MRR:240.0,164341.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 164343[138:Spt:164342.0] || -> until2p7(s43)*. % 76.16/76.36 164344[138:MRR:241.0,164343.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 164345[139:Spt:164344.0] || -> until2p7(s44)*. % 76.16/76.36 164346[139:MRR:539.0,164345.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 164347[140:Spt:164346.0] || -> until2p7(s45)*. % 76.16/76.36 164348[140:MRR:544.0,164347.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 164349[141:Spt:164348.0] || -> until2p7(s46)*. % 76.16/76.36 164350[141:MRR:549.0,164349.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 164351[142:Spt:164350.0] || -> until2p7(s47)*. % 76.16/76.36 164352[142:MRR:554.0,164351.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 164353[143:Spt:164352.0] || -> until2p7(s48)*. % 76.16/76.36 164354[143:MRR:559.0,164353.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 164355[144:Spt:164354.0] || -> until2p7(s49)*. % 76.16/76.36 164356[144:MRR:194.0,164355.0] || -> node4(s49)*. % 76.16/76.36 164357[144:MRR:164261.0,164356.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 164358[144:Res:53.1,164357.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 164360[144:MRR:164358.0,78381.0] || -> . % 76.16/76.36 164361[144:Spt:164360.0,164354.0,164355.0] || until2p7(s49)*+ -> . % 76.16/76.36 164362[144:Spt:164360.0,164354.1] || -> node4(s48)*. % 76.16/76.36 164363[144:MRR:78384.0,164362.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 164366[144:Res:53.1,164363.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 164369[144:Res:164366.0,61.1] always3(s48) || -> . % 76.16/76.36 164370[144:SSi:164369.0,78281.0,78387.0,137770.0,164353.0,164362.0] || -> . % 76.16/76.36 164371[143:Spt:164370.0,164352.0,164353.0] || until2p7(s48)*+ -> . % 76.16/76.36 164372[143:Spt:164370.0,164352.1] || -> node4(s47)*. % 76.16/76.36 164374[143:MRR:777.0,164372.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 164388[143:Res:53.1,164374.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 164390[144:Spt:164388.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 164392[144:Res:164390.0,61.1] always3(s47) || -> . % 76.16/76.36 164393[144:SSi:164392.0,78277.0,78280.0,137769.0,164351.0,164372.0] || -> . % 76.16/76.36 164394[144:Spt:164393.0,164388.0,164390.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 164395[144:Spt:164393.0,164388.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 164399[144:Res:164395.0,61.1] always3(s48) || -> . % 76.16/76.36 164400[144:SSi:164399.0,78281.0,78387.0,137770.0] || -> . % 76.16/76.36 164401[142:Spt:164400.0,164350.0,164351.0] || until2p7(s47)*+ -> . % 76.16/76.36 164402[142:Spt:164400.0,164350.1] || -> node4(s46)*. % 76.16/76.36 164404[142:MRR:780.0,164402.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 164411[142:Res:53.1,164404.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 164416[143:Spt:164411.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 164418[143:Res:164416.0,61.1] always3(s46) || -> . % 76.16/76.36 164419[143:SSi:164418.0,78272.0,78276.0,137768.0,164349.0,164402.0] || -> . % 76.16/76.36 164420[143:Spt:164419.0,164411.0,164416.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 164421[143:Spt:164419.0,164411.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 164425[143:Res:164421.0,61.1] always3(s47) || -> . % 76.16/76.36 164426[143:SSi:164425.0,78277.0,78280.0,137769.0] || -> . % 76.16/76.36 164427[141:Spt:164426.0,164348.0,164349.0] || until2p7(s46)*+ -> . % 76.16/76.36 164428[141:Spt:164426.0,164348.1] || -> node4(s45)*. % 76.16/76.36 164430[141:MRR:783.0,164428.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 164433[141:Res:53.1,164430.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 164435[142:Spt:164433.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 164437[142:Res:164435.0,61.1] always3(s45) || -> . % 76.16/76.36 164438[142:SSi:164437.0,78268.0,78271.0,137767.0,164347.0,164428.0] || -> . % 76.16/76.36 164439[142:Spt:164438.0,164433.0,164435.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 164440[142:Spt:164438.0,164433.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 164444[142:Res:164440.0,61.1] always3(s46) || -> . % 76.16/76.36 164445[142:SSi:164444.0,78272.0,78276.0,137768.0] || -> . % 76.16/76.36 164446[140:Spt:164445.0,164346.0,164347.0] || until2p7(s45)*+ -> . % 76.16/76.36 164447[140:Spt:164445.0,164346.1] || -> node4(s44)*. % 76.16/76.36 164449[140:MRR:786.0,164447.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 164452[140:Res:53.1,164449.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 164454[141:Spt:164452.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 164456[141:Res:164454.0,61.1] always3(s44) || -> . % 76.16/76.36 164457[141:SSi:164456.0,78263.0,78267.0,137766.0,164345.0,164447.0] || -> . % 76.16/76.36 164458[141:Spt:164457.0,164452.0,164454.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 164459[141:Spt:164457.0,164452.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 164463[141:Res:164459.0,61.1] always3(s45) || -> . % 76.16/76.36 164464[141:SSi:164463.0,78268.0,78271.0,137767.0] || -> . % 76.16/76.36 164465[139:Spt:164464.0,164344.0,164345.0] || until2p7(s44)*+ -> . % 76.16/76.36 164466[139:Spt:164464.0,164344.1] || -> node4(s43)*. % 76.16/76.36 164468[139:MRR:789.0,164466.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 164471[139:Res:53.1,164468.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 164473[140:Spt:164471.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 164475[140:Res:164473.0,61.1] always3(s43) || -> . % 76.16/76.36 164476[140:SSi:164475.0,78259.0,78262.0,137765.0,164343.0,164466.0] || -> . % 76.16/76.36 164477[140:Spt:164476.0,164471.0,164473.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 164478[140:Spt:164476.0,164471.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 164482[140:Res:164478.0,61.1] always3(s44) || -> . % 76.16/76.36 164483[140:SSi:164482.0,78263.0,78267.0,137766.0] || -> . % 76.16/76.36 164484[138:Spt:164483.0,164342.0,164343.0] || until2p7(s43)*+ -> . % 76.16/76.36 164485[138:Spt:164483.0,164342.1] || -> node4(s42)*. % 76.16/76.36 164487[138:MRR:792.0,164485.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 164490[138:Res:53.1,164487.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 164495[139:Spt:164490.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 164497[139:Res:164495.0,61.1] always3(s42) || -> . % 76.16/76.36 164498[139:SSi:164497.0,78254.0,78258.0,137764.0,164341.0,164485.0] || -> . % 76.16/76.36 164499[139:Spt:164498.0,164490.0,164495.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 164500[139:Spt:164498.0,164490.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 164504[139:Res:164500.0,61.1] always3(s43) || -> . % 76.16/76.36 164505[139:SSi:164504.0,78259.0,78262.0,137765.0] || -> . % 76.16/76.36 164506[137:Spt:164505.0,164340.0,164341.0] || until2p7(s42)*+ -> . % 76.16/76.36 164507[137:Spt:164505.0,164340.1] || -> node4(s41)*. % 76.16/76.36 164509[137:MRR:795.0,164507.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 164512[137:Res:53.1,164509.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 164514[138:Spt:164512.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 164516[138:Res:164514.0,61.1] always3(s41) || -> . % 76.16/76.36 164517[138:SSi:164516.0,78250.0,78253.0,137763.0,164339.0,164507.0] || -> . % 76.16/76.36 164518[138:Spt:164517.0,164512.0,164514.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 164519[138:Spt:164517.0,164512.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 164523[138:Res:164519.0,61.1] always3(s42) || -> . % 76.16/76.36 164524[138:SSi:164523.0,78254.0,78258.0,137764.0] || -> . % 76.16/76.36 164525[136:Spt:164524.0,164338.0,164339.0] || until2p7(s41)*+ -> . % 76.16/76.36 164526[136:Spt:164524.0,164338.1] || -> node4(s40)*. % 76.16/76.36 164528[136:MRR:798.0,164526.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 164531[136:Res:53.1,164528.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 164533[137:Spt:164531.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 164535[137:Res:164533.0,61.1] always3(s40) || -> . % 76.16/76.36 164536[137:SSi:164535.0,78245.0,78249.0,137762.0,164337.0,164526.0] || -> . % 76.16/76.36 164537[137:Spt:164536.0,164531.0,164533.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.36 164538[137:Spt:164536.0,164531.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 164542[137:Res:164538.0,61.1] always3(s41) || -> . % 76.16/76.36 164543[137:SSi:164542.0,78250.0,78253.0,137763.0] || -> . % 76.16/76.36 164544[135:Spt:164543.0,164336.0,164337.0] || until2p7(s40)*+ -> . % 76.16/76.36 164545[135:Spt:164543.0,164336.1] || -> node4(s39)*. % 76.16/76.36 164547[135:MRR:801.0,164545.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.36 164550[135:Res:53.1,164547.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.36 164552[136:Spt:164550.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 164554[136:Res:164552.0,61.1] always3(s39) || -> . % 76.16/76.36 164555[136:SSi:164554.0,78241.0,78244.0,137761.0,164335.0,164545.0] || -> . % 76.16/76.36 164556[136:Spt:164555.0,164550.0,164552.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.36 164557[136:Spt:164555.0,164550.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 164561[136:Res:164557.0,61.1] always3(s40) || -> . % 76.16/76.36 164562[136:SSi:164561.0,78245.0,78249.0,137762.0] || -> . % 76.16/76.36 164563[134:Spt:164562.0,164334.0,164335.0] || until2p7(s39)*+ -> . % 76.16/76.36 164564[134:Spt:164562.0,164334.1] || -> node4(s38)*. % 76.16/76.36 164566[134:MRR:804.0,164564.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.36 164569[134:Res:53.1,164566.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.36 164574[135:Spt:164569.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 164576[135:Res:164574.0,61.1] always3(s38) || -> . % 76.16/76.36 164577[135:SSi:164576.0,78236.0,78240.0,137760.0,164333.0,164564.0] || -> . % 76.16/76.36 164578[135:Spt:164577.0,164569.0,164574.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.36 164579[135:Spt:164577.0,164569.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 164583[135:Res:164579.0,61.1] always3(s39) || -> . % 76.16/76.36 164584[135:SSi:164583.0,78241.0,78244.0,137761.0] || -> . % 76.16/76.36 164585[133:Spt:164584.0,164332.0,164333.0] || until2p7(s38)*+ -> . % 76.16/76.36 164586[133:Spt:164584.0,164332.1] || -> node4(s37)*. % 76.16/76.36 164588[133:MRR:807.0,164586.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.36 164591[133:Res:53.1,164588.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.36 164593[134:Spt:164591.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 164595[134:Res:164593.0,61.1] always3(s37) || -> . % 76.16/76.36 164596[134:SSi:164595.0,78232.0,78235.0,137759.0,164331.0,164586.0] || -> . % 76.16/76.36 164597[134:Spt:164596.0,164591.0,164593.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.36 164598[134:Spt:164596.0,164591.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 164602[134:Res:164598.0,61.1] always3(s38) || -> . % 76.16/76.36 164603[134:SSi:164602.0,78236.0,78240.0,137760.0] || -> . % 76.16/76.36 164604[132:Spt:164603.0,164330.0,164331.0] || until2p7(s37)*+ -> . % 76.16/76.36 164605[132:Spt:164603.0,164330.1] || -> node4(s36)*. % 76.16/76.36 164607[132:MRR:810.0,164605.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.36 164610[132:Res:53.1,164607.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.36 164612[133:Spt:164610.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 164614[133:Res:164612.0,61.1] always3(s36) || -> . % 76.16/76.36 164615[133:SSi:164614.0,78227.0,78231.0,137758.0,164329.0,164605.0] || -> . % 76.16/76.36 164616[133:Spt:164615.0,164610.0,164612.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.36 164617[133:Spt:164615.0,164610.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 164621[133:Res:164617.0,61.1] always3(s37) || -> . % 76.16/76.36 164622[133:SSi:164621.0,78232.0,78235.0,137759.0] || -> . % 76.16/76.36 164623[131:Spt:164622.0,164328.0,164329.0] || until2p7(s36)*+ -> . % 76.16/76.36 164624[131:Spt:164622.0,164328.1] || -> node4(s35)*. % 76.16/76.36 164626[131:MRR:813.0,164624.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.36 164629[131:Res:53.1,164626.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.36 164631[132:Spt:164629.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 164633[132:Res:164631.0,61.1] always3(s35) || -> . % 76.16/76.36 164634[132:SSi:164633.0,78223.0,78226.0,137757.0,164327.0,164624.0] || -> . % 76.16/76.36 164635[132:Spt:164634.0,164629.0,164631.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.36 164636[132:Spt:164634.0,164629.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 164640[132:Res:164636.0,61.1] always3(s36) || -> . % 76.16/76.36 164641[132:SSi:164640.0,78227.0,78231.0,137758.0] || -> . % 76.16/76.36 164642[130:Spt:164641.0,164326.0,164327.0] || until2p7(s35)*+ -> . % 76.16/76.36 164643[130:Spt:164641.0,164326.1] || -> node4(s34)*. % 76.16/76.36 164645[130:MRR:816.0,164643.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.36 164648[130:Res:53.1,164645.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.36 164653[131:Spt:164648.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 164655[131:Res:164653.0,61.1] always3(s34) || -> . % 76.16/76.36 164656[131:SSi:164655.0,78218.0,78222.0,137756.0,164325.0,164643.0] || -> . % 76.16/76.36 164657[131:Spt:164656.0,164648.0,164653.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.36 164658[131:Spt:164656.0,164648.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 164662[131:Res:164658.0,61.1] always3(s35) || -> . % 76.16/76.36 164663[131:SSi:164662.0,78223.0,78226.0,137757.0] || -> . % 76.16/76.36 164664[129:Spt:164663.0,164324.0,164325.0] || until2p7(s34)*+ -> . % 76.16/76.36 164665[129:Spt:164663.0,164324.1] || -> node4(s33)*. % 76.16/76.36 164667[129:MRR:819.0,164665.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.36 164670[129:Res:53.1,164667.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.36 164672[130:Spt:164670.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.36 164674[130:Res:164672.0,61.1] always3(s33) || -> . % 76.16/76.36 164675[130:SSi:164674.0,78214.0,78217.0,137755.0,164323.0,164665.0] || -> . % 76.16/76.36 164676[130:Spt:164675.0,164670.0,164672.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.36 164677[130:Spt:164675.0,164670.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 164681[130:Res:164677.0,61.1] always3(s34) || -> . % 76.16/76.36 164682[130:SSi:164681.0,78218.0,78222.0,137756.0] || -> . % 76.16/76.36 164683[128:Spt:164682.0,164322.0,164323.0] || until2p7(s33)*+ -> . % 76.16/76.36 164684[128:Spt:164682.0,164322.1] || -> node4(s32)*. % 76.16/76.36 164686[128:MRR:822.0,164684.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.36 164689[128:Res:53.1,164686.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.36 164691[129:Spt:164689.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.36 164693[129:Res:164691.0,61.1] always3(s32) || -> . % 76.16/76.36 164694[129:SSi:164693.0,78209.0,78213.0,137754.0,164321.0,164684.0] || -> . % 76.16/76.36 164695[129:Spt:164694.0,164689.0,164691.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.36 164696[129:Spt:164694.0,164689.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.36 164700[129:Res:164696.0,61.1] always3(s33) || -> . % 76.16/76.36 164701[129:SSi:164700.0,78214.0,78217.0,137755.0] || -> . % 76.16/76.36 164702[127:Spt:164701.0,164320.0,164321.0] || until2p7(s32)*+ -> . % 76.16/76.36 164703[127:Spt:164701.0,164320.1] || -> node4(s31)*. % 76.16/76.36 164705[127:MRR:825.0,164703.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.36 164708[127:Res:53.1,164705.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.36 164710[128:Spt:164708.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.36 164712[128:Res:164710.0,61.1] always3(s31) || -> . % 76.16/76.36 164713[128:SSi:164712.0,78205.0,78208.0,137753.0,164319.0,164703.0] || -> . % 76.16/76.36 164714[128:Spt:164713.0,164708.0,164710.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.36 164715[128:Spt:164713.0,164708.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.36 164719[128:Res:164715.0,61.1] always3(s32) || -> . % 76.16/76.36 164720[128:SSi:164719.0,78209.0,78213.0,137754.0] || -> . % 76.16/76.36 164721[126:Spt:164720.0,164318.0,164319.0] || until2p7(s31)*+ -> . % 76.16/76.36 164722[126:Spt:164720.0,164318.1] || -> node4(s30)*. % 76.16/76.36 164724[126:MRR:828.0,164722.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.36 164727[126:Res:53.1,164724.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.36 164732[127:Spt:164727.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.36 164734[127:Res:164732.0,61.1] always3(s30) || -> . % 76.16/76.36 164735[127:SSi:164734.0,78200.0,78204.0,137752.0,164317.0,164722.0] || -> . % 76.16/76.36 164736[127:Spt:164735.0,164727.0,164732.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.36 164737[127:Spt:164735.0,164727.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.36 164741[127:Res:164737.0,61.1] always3(s31) || -> . % 76.16/76.36 164742[127:SSi:164741.0,78205.0,78208.0,137753.0] || -> . % 76.16/76.36 164743[125:Spt:164742.0,164316.0,164317.0] || until2p7(s30)*+ -> . % 76.16/76.36 164744[125:Spt:164742.0,164316.1] || -> node4(s29)*. % 76.16/76.36 164746[125:MRR:831.0,164744.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.36 164749[125:Res:53.1,164746.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.36 164751[126:Spt:164749.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.36 164753[126:Res:164751.0,61.1] always3(s29) || -> . % 76.16/76.36 164754[126:SSi:164753.0,78196.0,78199.0,137751.0,164315.0,164744.0] || -> . % 76.16/76.36 164755[126:Spt:164754.0,164749.0,164751.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.36 164756[126:Spt:164754.0,164749.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.36 164760[126:Res:164756.0,61.1] always3(s30) || -> . % 76.16/76.36 164761[126:SSi:164760.0,78200.0,78204.0,137752.0] || -> . % 76.16/76.36 164762[124:Spt:164761.0,164314.0,164315.0] || until2p7(s29)*+ -> . % 76.16/76.36 164763[124:Spt:164761.0,164314.1] || -> node4(s28)*. % 76.16/76.36 164765[124:MRR:834.0,164763.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.36 164768[124:Res:53.1,164765.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.36 164770[125:Spt:164768.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.36 164772[125:Res:164770.0,61.1] always3(s28) || -> . % 76.16/76.36 164773[125:SSi:164772.0,78191.0,78195.0,137750.0,164313.0,164763.0] || -> . % 76.16/76.36 164774[125:Spt:164773.0,164768.0,164770.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.36 164775[125:Spt:164773.0,164768.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.36 164779[125:Res:164775.0,61.1] always3(s29) || -> . % 76.16/76.36 164780[125:SSi:164779.0,78196.0,78199.0,137751.0] || -> . % 76.16/76.36 164781[123:Spt:164780.0,164312.0,164313.0] || until2p7(s28)*+ -> . % 76.16/76.36 164782[123:Spt:164780.0,164312.1] || -> node4(s27)*. % 76.16/76.36 164784[123:MRR:837.0,164782.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.36 164787[123:Res:53.1,164784.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.36 164789[124:Spt:164787.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.36 164791[124:Res:164789.0,61.1] always3(s27) || -> . % 76.16/76.36 164792[124:SSi:164791.0,78187.0,78190.0,137749.0,164311.0,164782.0] || -> . % 76.16/76.36 164793[124:Spt:164792.0,164787.0,164789.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.36 164794[124:Spt:164792.0,164787.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.36 164798[124:Res:164794.0,61.1] always3(s28) || -> . % 76.16/76.36 164799[124:SSi:164798.0,78191.0,78195.0,137750.0] || -> . % 76.16/76.36 164800[122:Spt:164799.0,164310.0,164311.0] || until2p7(s27)*+ -> . % 76.16/76.36 164801[122:Spt:164799.0,164310.1] || -> node4(s26)*. % 76.16/76.36 164803[122:MRR:840.0,164801.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.36 164806[122:Res:53.1,164803.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.36 164811[123:Spt:164806.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.36 164813[123:Res:164811.0,61.1] always3(s26) || -> . % 76.16/76.36 164814[123:SSi:164813.0,78182.0,78186.0,137748.0,164309.0,164801.0] || -> . % 76.16/76.36 164815[123:Spt:164814.0,164806.0,164811.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.36 164816[123:Spt:164814.0,164806.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.36 164820[123:Res:164816.0,61.1] always3(s27) || -> . % 76.16/76.36 164821[123:SSi:164820.0,78187.0,78190.0,137749.0] || -> . % 76.16/76.36 164822[121:Spt:164821.0,164308.0,164309.0] || until2p7(s26)*+ -> . % 76.16/76.36 164823[121:Spt:164821.0,164308.1] || -> node4(s25)*. % 76.16/76.36 164825[121:MRR:843.0,164823.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.36 164828[121:Res:53.1,164825.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.36 164830[122:Spt:164828.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.36 164832[122:Res:164830.0,61.1] always3(s25) || -> . % 76.16/76.36 164833[122:SSi:164832.0,78178.0,78181.0,137747.0,164307.0,164823.0] || -> . % 76.16/76.36 164834[122:Spt:164833.0,164828.0,164830.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.36 164835[122:Spt:164833.0,164828.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.36 164839[122:Res:164835.0,61.1] always3(s26) || -> . % 76.16/76.36 164840[122:SSi:164839.0,78182.0,78186.0,137748.0] || -> . % 76.16/76.36 164841[120:Spt:164840.0,164306.0,164307.0] || until2p7(s25)*+ -> . % 76.16/76.36 164842[120:Spt:164840.0,164306.1] || -> node4(s24)*. % 76.16/76.36 164844[120:MRR:846.0,164842.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.36 164847[120:Res:53.1,164844.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.36 164849[121:Spt:164847.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.36 164851[121:Res:164849.0,61.1] always3(s24) || -> . % 76.16/76.36 164852[121:SSi:164851.0,78173.0,78177.0,137746.0,164305.0,164842.0] || -> . % 76.16/76.36 164853[121:Spt:164852.0,164847.0,164849.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.36 164854[121:Spt:164852.0,164847.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.36 164858[121:Res:164854.0,61.1] always3(s25) || -> . % 76.16/76.36 164859[121:SSi:164858.0,78178.0,78181.0,137747.0] || -> . % 76.16/76.36 164860[119:Spt:164859.0,164304.0,164305.0] || until2p7(s24)*+ -> . % 76.16/76.36 164861[119:Spt:164859.0,164304.1] || -> node4(s23)*. % 76.16/76.36 164863[119:MRR:849.0,164861.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.36 164866[119:Res:53.1,164863.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.36 164868[120:Spt:164866.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.36 164870[120:Res:164868.0,61.1] always3(s23) || -> . % 76.16/76.36 164871[120:SSi:164870.0,78169.0,78172.0,137745.0,164303.0,164861.0] || -> . % 76.16/76.36 164872[120:Spt:164871.0,164866.0,164868.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.36 164873[120:Spt:164871.0,164866.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.36 164877[120:Res:164873.0,61.1] always3(s24) || -> . % 76.16/76.36 164878[120:SSi:164877.0,78173.0,78177.0,137746.0] || -> . % 76.16/76.36 164879[118:Spt:164878.0,164302.0,164303.0] || until2p7(s23)*+ -> . % 76.16/76.36 164880[118:Spt:164878.0,164302.1] || -> node4(s22)*. % 76.16/76.36 164882[118:MRR:852.0,164880.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.36 164885[118:Res:53.1,164882.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.36 164890[119:Spt:164885.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.36 164892[119:Res:164890.0,61.1] always3(s22) || -> . % 76.16/76.36 164893[119:SSi:164892.0,78164.0,78168.0,137744.0,164301.0,164880.0] || -> . % 76.16/76.36 164894[119:Spt:164893.0,164885.0,164890.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.36 164895[119:Spt:164893.0,164885.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.36 164899[119:Res:164895.0,61.1] always3(s23) || -> . % 76.16/76.36 164900[119:SSi:164899.0,78169.0,78172.0,137745.0] || -> . % 76.16/76.36 164901[117:Spt:164900.0,164300.0,164301.0] || until2p7(s22)*+ -> . % 76.16/76.36 164902[117:Spt:164900.0,164300.1] || -> node4(s21)*. % 76.16/76.36 164904[117:MRR:855.0,164902.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.36 164907[117:Res:53.1,164904.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.36 164909[118:Spt:164907.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.36 164911[118:Res:164909.0,61.1] always3(s21) || -> . % 76.16/76.36 164912[118:SSi:164911.0,78160.0,78163.0,137743.0,164299.0,164902.0] || -> . % 76.16/76.36 164913[118:Spt:164912.0,164907.0,164909.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.36 164914[118:Spt:164912.0,164907.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.36 164918[118:Res:164914.0,61.1] always3(s22) || -> . % 76.16/76.36 164919[118:SSi:164918.0,78164.0,78168.0,137744.0] || -> . % 76.16/76.36 164920[116:Spt:164919.0,164298.0,164299.0] || until2p7(s21)*+ -> . % 76.16/76.36 164921[116:Spt:164919.0,164298.1] || -> node4(s20)*. % 76.16/76.36 164923[116:MRR:858.0,164921.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.36 164926[116:Res:53.1,164923.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.36 164928[117:Spt:164926.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.36 164930[117:Res:164928.0,61.1] always3(s20) || -> . % 76.16/76.36 164931[117:SSi:164930.0,78155.0,78159.0,137742.0,164297.0,164921.0] || -> . % 76.16/76.36 164932[117:Spt:164931.0,164926.0,164928.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.36 164933[117:Spt:164931.0,164926.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.36 164937[117:Res:164933.0,61.1] always3(s21) || -> . % 76.16/76.36 164938[117:SSi:164937.0,78160.0,78163.0,137743.0] || -> . % 76.16/76.36 164939[115:Spt:164938.0,164296.0,164297.0] || until2p7(s20)*+ -> . % 76.16/76.36 164940[115:Spt:164938.0,164296.1] || -> node4(s19)*. % 76.16/76.36 164942[115:MRR:861.0,164940.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.36 164945[115:Res:53.1,164942.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.36 164947[116:Spt:164945.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.36 164949[116:Res:164947.0,61.1] always3(s19) || -> . % 76.16/76.36 164950[116:SSi:164949.0,78151.0,78154.0,137741.0,164295.0,164940.0] || -> . % 76.16/76.36 164951[116:Spt:164950.0,164945.0,164947.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.36 164952[116:Spt:164950.0,164945.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.36 164956[116:Res:164952.0,61.1] always3(s20) || -> . % 76.16/76.36 164957[116:SSi:164956.0,78155.0,78159.0,137742.0] || -> . % 76.16/76.36 164958[114:Spt:164957.0,164294.0,164295.0] || until2p7(s19)*+ -> . % 76.16/76.36 164959[114:Spt:164957.0,164294.1] || -> node4(s18)*. % 76.16/76.36 164961[114:MRR:864.0,164959.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.36 164964[114:Res:53.1,164961.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.36 164969[115:Spt:164964.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.36 164971[115:Res:164969.0,61.1] always3(s18) || -> . % 76.16/76.36 164972[115:SSi:164971.0,78146.0,78150.0,137740.0,164293.0,164959.0] || -> . % 76.16/76.36 164973[115:Spt:164972.0,164964.0,164969.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.36 164974[115:Spt:164972.0,164964.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.36 164978[115:Res:164974.0,61.1] always3(s19) || -> . % 76.16/76.36 164979[115:SSi:164978.0,78151.0,78154.0,137741.0] || -> . % 76.16/76.36 164980[113:Spt:164979.0,164292.0,164293.0] || until2p7(s18)*+ -> . % 76.16/76.36 164981[113:Spt:164979.0,164292.1] || -> node4(s17)*. % 76.16/76.36 164983[113:MRR:867.0,164981.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.36 164986[113:Res:53.1,164983.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.36 164988[114:Spt:164986.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.36 164990[114:Res:164988.0,61.1] always3(s17) || -> . % 76.16/76.36 164991[114:SSi:164990.0,78142.0,78145.0,137739.0,164291.0,164981.0] || -> . % 76.16/76.36 164992[114:Spt:164991.0,164986.0,164988.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.36 164993[114:Spt:164991.0,164986.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.36 164997[114:Res:164993.0,61.1] always3(s18) || -> . % 76.16/76.36 164998[114:SSi:164997.0,78146.0,78150.0,137740.0] || -> . % 76.16/76.36 164999[112:Spt:164998.0,164290.0,164291.0] || until2p7(s17)*+ -> . % 76.16/76.36 165000[112:Spt:164998.0,164290.1] || -> node4(s16)*. % 76.16/76.36 165002[112:MRR:870.0,165000.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.36 165005[112:Res:53.1,165002.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.36 165007[113:Spt:165005.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.36 165009[113:Res:165007.0,61.1] always3(s16) || -> . % 76.16/76.36 165010[113:SSi:165009.0,78137.0,78141.0,137738.0,164289.0,165000.0] || -> . % 76.16/76.36 165011[113:Spt:165010.0,165005.0,165007.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.36 165012[113:Spt:165010.0,165005.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.36 165016[113:Res:165012.0,61.1] always3(s17) || -> . % 76.16/76.36 165017[113:SSi:165016.0,78142.0,78145.0,137739.0] || -> . % 76.16/76.36 165018[111:Spt:165017.0,164288.0,164289.0] || until2p7(s16)*+ -> . % 76.16/76.36 165019[111:Spt:165017.0,164288.1] || -> node4(s15)*. % 76.16/76.36 165021[111:MRR:873.0,165019.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.36 165024[111:Res:53.1,165021.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.36 165026[112:Spt:165024.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.36 165028[112:Res:165026.0,61.1] always3(s15) || -> . % 76.16/76.36 165029[112:SSi:165028.0,78133.0,78136.0,137737.0,164287.0,165019.0] || -> . % 76.16/76.36 165030[112:Spt:165029.0,165024.0,165026.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.36 165031[112:Spt:165029.0,165024.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.36 165035[112:Res:165031.0,61.1] always3(s16) || -> . % 76.16/76.36 165036[112:SSi:165035.0,78137.0,78141.0,137738.0] || -> . % 76.16/76.36 165037[110:Spt:165036.0,164286.0,164287.0] || until2p7(s15)*+ -> . % 76.16/76.36 165038[110:Spt:165036.0,164286.1] || -> node4(s14)*. % 76.16/76.36 165040[110:MRR:876.0,165038.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.36 165043[110:Res:53.1,165040.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.36 165048[111:Spt:165043.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.36 165050[111:Res:165048.0,61.1] always3(s14) || -> . % 76.16/76.36 165051[111:SSi:165050.0,78128.0,78132.0,137736.0,164285.0,165038.0] || -> . % 76.16/76.36 165052[111:Spt:165051.0,165043.0,165048.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.36 165053[111:Spt:165051.0,165043.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.36 165057[111:Res:165053.0,61.1] always3(s15) || -> . % 76.16/76.36 165058[111:SSi:165057.0,78133.0,78136.0,137737.0] || -> . % 76.16/76.36 165059[109:Spt:165058.0,164284.0,164285.0] || until2p7(s14)*+ -> . % 76.16/76.36 165060[109:Spt:165058.0,164284.1] || -> node4(s13)*. % 76.16/76.36 165062[109:MRR:879.0,165060.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.36 165065[109:Res:53.1,165062.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.36 165067[110:Spt:165065.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.36 165069[110:Res:165067.0,61.1] always3(s13) || -> . % 76.16/76.36 165070[110:SSi:165069.0,78124.0,78127.0,137735.0,164283.0,165060.0] || -> . % 76.16/76.36 165071[110:Spt:165070.0,165065.0,165067.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.36 165072[110:Spt:165070.0,165065.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.36 165076[110:Res:165072.0,61.1] always3(s14) || -> . % 76.16/76.36 165077[110:SSi:165076.0,78128.0,78132.0,137736.0] || -> . % 76.16/76.36 165078[108:Spt:165077.0,164282.0,164283.0] || until2p7(s13)*+ -> . % 76.16/76.36 165079[108:Spt:165077.0,164282.1] || -> node4(s12)*. % 76.16/76.36 165081[108:MRR:882.0,165079.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.36 165084[108:Res:53.1,165081.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.36 165086[109:Spt:165084.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.36 165088[109:Res:165086.0,61.1] always3(s12) || -> . % 76.16/76.36 165089[109:SSi:165088.0,78119.0,78123.0,137734.0,164281.0,165079.0] || -> . % 76.16/76.36 165090[109:Spt:165089.0,165084.0,165086.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.36 165091[109:Spt:165089.0,165084.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.36 165095[109:Res:165091.0,61.1] always3(s13) || -> . % 76.16/76.36 165096[109:SSi:165095.0,78124.0,78127.0,137735.0] || -> . % 76.16/76.36 165097[107:Spt:165096.0,164280.0,164281.0] || until2p7(s12)*+ -> . % 76.16/76.36 165098[107:Spt:165096.0,164280.1] || -> node4(s11)*. % 76.16/76.36 165100[107:MRR:885.0,165098.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.36 165103[107:Res:53.1,165100.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.36 165105[108:Spt:165103.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.36 165107[108:Res:165105.0,61.1] always3(s11) || -> . % 76.16/76.36 165108[108:SSi:165107.0,78115.0,78118.0,137733.0,164279.0,165098.0] || -> . % 76.16/76.36 165109[108:Spt:165108.0,165103.0,165105.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.36 165110[108:Spt:165108.0,165103.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.36 165114[108:Res:165110.0,61.1] always3(s12) || -> . % 76.16/76.36 165115[108:SSi:165114.0,78119.0,78123.0,137734.0] || -> . % 76.16/76.36 165116[106:Spt:165115.0,164278.0,164279.0] || until2p7(s11)*+ -> . % 76.16/76.36 165117[106:Spt:165115.0,164278.1] || -> node4(s10)*. % 76.16/76.36 165119[106:MRR:888.0,165117.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.36 165122[106:Res:53.1,165119.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.36 165127[107:Spt:165122.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.36 165129[107:Res:165127.0,61.1] always3(s10) || -> . % 76.16/76.36 165130[107:SSi:165129.0,78110.0,78114.0,137732.0,164277.0,165117.0] || -> . % 76.16/76.36 165131[107:Spt:165130.0,165122.0,165127.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.36 165132[107:Spt:165130.0,165122.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.36 165136[107:Res:165132.0,61.1] always3(s11) || -> . % 76.16/76.36 165137[107:SSi:165136.0,78115.0,78118.0,137733.0] || -> . % 76.16/76.36 165138[105:Spt:165137.0,164276.0,164277.0] || until2p7(s10)*+ -> . % 76.16/76.36 165139[105:Spt:165137.0,164276.1] || -> node4(s9)*. % 76.16/76.36 165141[105:MRR:891.0,165139.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.36 165144[105:Res:53.1,165141.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.36 165146[106:Spt:165144.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.36 165148[106:Res:165146.0,61.1] always3(s9) || -> . % 76.16/76.36 165149[106:SSi:165148.0,78106.0,78109.0,137731.0,164275.0,165139.0] || -> . % 76.16/76.36 165150[106:Spt:165149.0,165144.0,165146.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.36 165151[106:Spt:165149.0,165144.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.36 165155[106:Res:165151.0,61.1] always3(s10) || -> . % 76.16/76.36 165156[106:SSi:165155.0,78110.0,78114.0,137732.0] || -> . % 76.16/76.36 165157[104:Spt:165156.0,164274.0,164275.0] || until2p7(s9)*+ -> . % 76.16/76.36 165158[104:Spt:165156.0,164274.1] || -> node4(s8)*. % 76.16/76.36 165160[104:MRR:894.0,165158.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.36 165163[104:Res:53.1,165160.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.36 165165[105:Spt:165163.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.36 165167[105:Res:165165.0,61.1] always3(s8) || -> . % 76.16/76.36 165168[105:SSi:165167.0,78101.0,78105.0,137730.0,164273.0,165158.0] || -> . % 76.16/76.36 165169[105:Spt:165168.0,165163.0,165165.0] || m_main_v_state(s8,c_busy)* -> . % 76.16/76.36 165170[105:Spt:165168.0,165163.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.36 165174[105:Res:165170.0,61.1] always3(s9) || -> . % 76.16/76.36 165175[105:SSi:165174.0,78106.0,78109.0,137731.0] || -> . % 76.16/76.36 165176[103:Spt:165175.0,164272.0,164273.0] || until2p7(s8)*+ -> . % 76.16/76.36 165177[103:Spt:165175.0,164272.1] || -> node4(s7)*. % 76.16/76.36 165179[103:MRR:897.0,165177.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.16/76.36 165182[103:Res:53.1,165179.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.16/76.36 165184[104:Spt:165182.0] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.36 165186[104:Res:165184.0,61.1] always3(s7) || -> . % 76.16/76.36 165187[104:SSi:165186.0,78097.0,78100.0,137729.0,164271.0,165177.0] || -> . % 76.16/76.36 165188[104:Spt:165187.0,165182.0,165184.0] || m_main_v_state(s7,c_busy)* -> . % 76.16/76.36 165189[104:Spt:165187.0,165182.1] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.36 165193[104:Res:165189.0,61.1] always3(s8) || -> . % 76.16/76.36 165194[104:SSi:165193.0,78101.0,78105.0,137730.0] || -> . % 76.16/76.36 165195[102:Spt:165194.0,164270.0,164271.0] || until2p7(s7)*+ -> . % 76.16/76.36 165196[102:Spt:165194.0,164270.1] || -> node4(s6)*. % 76.16/76.36 165198[102:MRR:900.0,165196.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.16/76.36 165201[102:Res:53.1,165198.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.16/76.36 165206[103:Spt:165201.0] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.36 165208[103:Res:165206.0,61.1] always3(s6) || -> . % 76.16/76.36 165209[103:SSi:165208.0,78093.0,78096.0,137728.0,164269.0,165196.0] || -> . % 76.16/76.36 165210[103:Spt:165209.0,165201.0,165206.0] || m_main_v_state(s6,c_busy)* -> . % 76.16/76.36 165211[103:Spt:165209.0,165201.1] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.36 165215[103:Res:165211.0,61.1] always3(s7) || -> . % 76.16/76.36 165216[103:SSi:165215.0,78097.0,78100.0,137729.0] || -> . % 76.16/76.36 165217[101:Spt:165216.0,164268.0,164269.0] || until2p7(s6)*+ -> . % 76.16/76.36 165218[101:Spt:165216.0,164268.1] || -> node4(s5)*. % 76.16/76.36 165220[101:MRR:903.0,165218.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.16/76.36 165223[101:Res:53.1,165220.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.16/76.36 165225[102:Spt:165223.0] || -> m_main_v_state(s5,c_busy)*. % 76.16/76.36 165227[102:Res:165225.0,61.1] always3(s5) || -> . % 76.16/76.36 165228[102:SSi:165227.0,78089.0,78092.0,137727.0,164267.0,165218.0] || -> . % 76.16/76.36 165229[102:Spt:165228.0,165223.0,165225.0] || m_main_v_state(s5,c_busy)* -> . % 76.16/76.36 165230[102:Spt:165228.0,165223.1] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.36 165234[102:Res:165230.0,61.1] always3(s6) || -> . % 76.16/76.36 165235[102:SSi:165234.0,78093.0,78096.0,137728.0] || -> . % 76.16/76.36 165236[100:Spt:165235.0,164266.0,164267.0] || until2p7(s5)*+ -> . % 76.16/76.36 165237[100:Spt:165235.0,164266.1] || -> node4(s4)*. % 76.16/76.36 165239[100:MRR:906.0,165237.0] || m_main_v_state(s4,c_ready)*+ -> m_main_v_state(s5,c_busy). % 76.16/76.36 165242[100:Res:53.1,165239.0] || -> m_main_v_state(s4,c_busy)* m_main_v_state(s5,c_busy). % 76.16/76.36 165244[100:MRR:165242.0,164257.0] || -> m_main_v_state(s5,c_busy)*. % 76.16/76.36 165246[100:Res:165244.0,61.1] always3(s5) || -> . % 76.16/76.36 165247[100:SSi:165246.0,78089.0,78092.0,137727.0] || -> . % 76.16/76.36 165248[53:Spt:165247.0,137477.45,137726.0] || always3(s4)*+ -> . % 76.16/76.36 165249[53:Spt:165247.0,137477.0,137477.1,137477.2,137477.3,137477.4,137477.5,137477.6,137477.7,137477.8,137477.9,137477.10,137477.11,137477.12,137477.13,137477.14,137477.15,137477.16,137477.17,137477.18,137477.19,137477.20,137477.21,137477.22,137477.23,137477.24,137477.25,137477.26,137477.27,137477.28,137477.29,137477.30,137477.31,137477.32,137477.33,137477.34,137477.35,137477.36,137477.37,137477.38,137477.39,137477.40,137477.41,137477.42,137477.43,137477.44] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) trans(s49,s5)*. % 76.16/76.36 165251[53:Res:165249.44,69.2] xuntil6(s49) last(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 165252[53:Res:165249.44,62.1] always3(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* always3(s5). % 76.16/76.36 165253[53:Res:165249.44,60.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 165254[53:SSi:165252.0,50.0,78285.0,78388.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* always3(s5). % 76.16/76.36 165255[53:SSi:165251.1,50.0,78285.0,78388.0] xuntil6(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 165497[54:Spt:165254.44] || -> always3(s5)*. % 76.16/76.36 165498[54:MRR:519.0,165497.0] || -> always3(s6)*. % 76.16/76.36 165499[54:MRR:516.0,165498.0] || -> always3(s7)*. % 76.16/76.36 165500[54:MRR:513.0,165499.0] || -> always3(s8)*. % 76.16/76.36 165501[54:MRR:510.0,165500.0] || -> always3(s9)*. % 76.16/76.36 165502[54:MRR:507.0,165501.0] || -> always3(s10)*. % 76.16/76.36 165503[54:MRR:504.0,165502.0] || -> always3(s11)*. % 76.16/76.36 165504[54:MRR:501.0,165503.0] || -> always3(s12)*. % 76.16/76.36 165505[54:MRR:498.0,165504.0] || -> always3(s13)*. % 76.16/76.36 165506[54:MRR:495.0,165505.0] || -> always3(s14)*. % 76.16/76.36 165507[54:MRR:492.0,165506.0] || -> always3(s15)*. % 76.16/76.36 165508[54:MRR:489.0,165507.0] || -> always3(s16)*. % 76.16/76.36 165509[54:MRR:486.0,165508.0] || -> always3(s17)*. % 76.16/76.36 165510[54:MRR:483.0,165509.0] || -> always3(s18)*. % 76.16/76.36 165511[54:MRR:480.0,165510.0] || -> always3(s19)*. % 76.16/76.36 165512[54:MRR:477.0,165511.0] || -> always3(s20)*. % 76.16/76.36 165513[54:MRR:474.0,165512.0] || -> always3(s21)*. % 76.16/76.36 165514[54:MRR:471.0,165513.0] || -> always3(s22)*. % 76.16/76.36 165515[54:MRR:468.0,165514.0] || -> always3(s23)*. % 76.16/76.36 165516[54:MRR:465.0,165515.0] || -> always3(s24)*. % 76.16/76.36 165517[54:MRR:462.0,165516.0] || -> always3(s25)*. % 76.16/76.36 165518[54:MRR:459.0,165517.0] || -> always3(s26)*. % 76.16/76.36 165519[54:MRR:456.0,165518.0] || -> always3(s27)*. % 76.16/76.36 165520[54:MRR:453.0,165519.0] || -> always3(s28)*. % 76.16/76.36 165521[54:MRR:450.0,165520.0] || -> always3(s29)*. % 76.16/76.36 165522[54:MRR:427.0,165521.0] || -> always3(s30)*. % 76.16/76.36 165523[54:MRR:425.0,165522.0] || -> always3(s31)*. % 76.16/76.36 165524[54:MRR:423.0,165523.0] || -> always3(s32)*. % 76.16/76.36 165525[54:MRR:421.0,165524.0] || -> always3(s33)*. % 76.16/76.36 165526[54:MRR:370.0,165525.0] || -> always3(s34)*. % 76.16/76.36 165527[54:MRR:368.0,165526.0] || -> always3(s35)*. % 76.16/76.36 165528[54:MRR:366.0,165527.0] || -> always3(s36)*. % 76.16/76.36 165529[54:MRR:364.0,165528.0] || -> always3(s37)*. % 76.16/76.36 165530[54:MRR:313.0,165529.0] || -> always3(s38)*. % 76.16/76.36 165531[54:MRR:311.0,165530.0] || -> always3(s39)*. % 76.16/76.36 165532[54:MRR:309.0,165531.0] || -> always3(s40)*. % 76.16/76.36 165533[54:MRR:307.0,165532.0] || -> always3(s41)*. % 76.16/76.36 165534[54:MRR:306.0,165533.0] || -> always3(s42)*. % 76.16/76.36 165535[54:MRR:305.0,165534.0] || -> always3(s43)*. % 76.16/76.36 165536[54:MRR:304.0,165535.0] || -> always3(s44)*. % 76.16/76.36 165537[54:MRR:303.0,165536.0] || -> always3(s45)*. % 76.16/76.36 165538[54:MRR:302.0,165537.0] || -> always3(s46)*. % 76.16/76.36 165539[54:MRR:301.0,165538.0] || -> always3(s47)*. % 76.16/76.36 165540[54:MRR:300.0,165539.0] || -> always3(s48)*. % 76.16/76.36 165541[55:Spt:165253.0] || -> trans(s49,s49)*. % 76.16/76.36 165542[55:Res:165541.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s49)*. % 76.16/76.36 165544[55:Res:165541.0,60.0] || -> node2(s49,s49)*. % 76.16/76.36 165545[55:SSi:165542.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s49)*. % 76.16/76.36 165546[55:Res:165544.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> m_main_v_state(s49,c_busy). % 76.16/76.36 165547[55:MRR:165546.1,165546.2,53.1,78381.0] m_main_v_request(s49) || -> . % 76.16/76.36 165549[55:SoR:165547.0,64.1] node4(s49) || -> . % 76.16/76.36 165550[55:MRR:194.1,165549.0] until2p7(s49) || -> . % 76.16/76.36 165553[55:MRR:165545.1,165550.0] xuntil6(s49) || -> . % 76.16/76.36 165554[55:SoR:165549.0,66.2] until5(s49) || -> xuntil6(s49)*. % 76.16/76.36 165555[55:SSi:165554.0,50.0,78285.0,78388.0] || -> xuntil6(s49)*. % 76.16/76.36 165556[55:MRR:165555.0,165553.0] || -> . % 76.16/76.36 165557[55:Spt:165556.0,165253.0,165541.0] || trans(s49,s49)*+ -> . % 76.16/76.36 165558[55:Spt:165556.0,165253.1,165253.2,165253.3,165253.4,165253.5,165253.6,165253.7,165253.8,165253.9,165253.10,165253.11,165253.12,165253.13,165253.14,165253.15,165253.16,165253.17,165253.18,165253.19,165253.20,165253.21,165253.22,165253.23,165253.24,165253.25,165253.26,165253.27,165253.28,165253.29,165253.30,165253.31,165253.32,165253.33,165253.34,165253.35,165253.36,165253.37,165253.38,165253.39,165253.40,165253.41,165253.42,165253.43,165253.44] || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 165560[55:MRR:165255.1,165557.0] xuntil6(s49) || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 165561[56:Spt:165558.0] || -> trans(s49,s48)*. % 76.16/76.36 165562[56:Res:165561.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s48)*. % 76.16/76.36 165564[56:Res:165561.0,60.0] || -> node2(s49,s48)*. % 76.16/76.36 165565[56:SSi:165562.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s48)*. % 76.16/76.36 165566[56:Res:165564.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 165569[56:SoR:165566.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 165571[56:SoR:165569.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)* xuntil6(s49). % 76.16/76.36 165572[56:SSi:165571.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s48,c_busy)* xuntil6(s49). % 76.16/76.36 165573[57:Spt:165572.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 165575[57:Res:165573.0,61.1] always3(s48) || -> . % 76.16/76.36 165576[57:SSi:165575.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 165577[57:Spt:165576.0,165572.1,165573.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.16/76.36 165578[57:Spt:165576.0,165572.0,165572.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 165582[57:MRR:165569.2,165577.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 165583[57:Res:53.1,165578.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 165585[57:MRR:165583.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 165586[57:MRR:165565.0,165585.0] || -> until2p7(s48)*. % 76.16/76.36 165587[57:MRR:559.0,165586.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 165588[58:Spt:165587.0] || -> until2p7(s49)*. % 76.16/76.36 165589[58:MRR:194.0,165588.0] || -> node4(s49)*. % 76.16/76.36 165590[58:MRR:165582.0,165589.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 165591[58:Res:53.1,165590.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 165593[58:MRR:165591.0,78381.0] || -> . % 76.16/76.36 165594[58:Spt:165593.0,165587.0,165588.0] || until2p7(s49)*+ -> . % 76.16/76.36 165595[58:Spt:165593.0,165587.1] || -> node4(s48)*. % 76.16/76.36 165596[58:MRR:78384.0,165595.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 165599[58:Res:53.1,165596.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 165601[58:MRR:165599.0,165577.0] || -> . % 76.16/76.36 165602[56:Spt:165601.0,165558.0,165561.0] || trans(s49,s48)*+ -> . % 76.16/76.36 165603[56:Spt:165601.0,165558.1,165558.2,165558.3,165558.4,165558.5,165558.6,165558.7,165558.8,165558.9,165558.10,165558.11,165558.12,165558.13,165558.14,165558.15,165558.16,165558.17,165558.18,165558.19,165558.20,165558.21,165558.22,165558.23,165558.24,165558.25,165558.26,165558.27,165558.28,165558.29,165558.30,165558.31,165558.32,165558.33,165558.34,165558.35,165558.36,165558.37,165558.38,165558.39,165558.40,165558.41,165558.42,165558.43] || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 165605[56:MRR:165560.1,165602.0] xuntil6(s49) || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 165606[57:Spt:165603.0] || -> trans(s49,s47)*. % 76.16/76.36 165607[57:Res:165606.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s47)*. % 76.16/76.36 165609[57:Res:165606.0,60.0] || -> node2(s49,s47)*. % 76.16/76.36 165610[57:SSi:165607.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s47)*. % 76.16/76.36 165611[57:Res:165609.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 165623[57:SoR:165611.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 165625[57:SoR:165623.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 76.16/76.36 165626[57:SSi:165625.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 76.16/76.36 165627[58:Spt:165626.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 165629[58:Res:165627.0,61.1] always3(s47) || -> . % 76.16/76.36 165630[58:SSi:165629.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 165631[58:Spt:165630.0,165626.1,165627.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.16/76.36 165632[58:Spt:165630.0,165626.0,165626.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 165636[58:MRR:165623.2,165631.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 165637[58:Res:53.1,165632.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 165639[58:MRR:165637.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 165640[58:MRR:165610.0,165639.0] || -> until2p7(s47)*. % 76.16/76.36 165641[58:MRR:554.0,165640.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 165642[59:Spt:165641.0] || -> until2p7(s48)*. % 76.16/76.36 165643[59:MRR:559.0,165642.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 165644[60:Spt:165643.0] || -> until2p7(s49)*. % 76.16/76.36 165645[60:MRR:194.0,165644.0] || -> node4(s49)*. % 76.16/76.36 165646[60:MRR:165636.0,165645.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 165647[60:Res:53.1,165646.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 165649[60:MRR:165647.0,78381.0] || -> . % 76.16/76.36 165650[60:Spt:165649.0,165643.0,165644.0] || until2p7(s49)*+ -> . % 76.16/76.36 165651[60:Spt:165649.0,165643.1] || -> node4(s48)*. % 76.16/76.36 165652[60:MRR:78384.0,165651.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 165655[60:Res:53.1,165652.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 165658[60:Res:165655.0,61.1] always3(s48) || -> . % 76.16/76.36 165659[60:SSi:165658.0,78281.0,78387.0,165540.0,165642.0,165651.0] || -> . % 76.16/76.36 165660[59:Spt:165659.0,165641.0,165642.0] || until2p7(s48)*+ -> . % 76.16/76.36 165661[59:Spt:165659.0,165641.1] || -> node4(s47)*. % 76.16/76.36 165663[59:MRR:777.0,165661.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 165678[59:Res:53.1,165663.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 165680[59:MRR:165678.0,165631.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 165682[59:Res:165680.0,61.1] always3(s48) || -> . % 76.16/76.36 165683[59:SSi:165682.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 165684[57:Spt:165683.0,165603.0,165606.0] || trans(s49,s47)*+ -> . % 76.16/76.36 165685[57:Spt:165683.0,165603.1,165603.2,165603.3,165603.4,165603.5,165603.6,165603.7,165603.8,165603.9,165603.10,165603.11,165603.12,165603.13,165603.14,165603.15,165603.16,165603.17,165603.18,165603.19,165603.20,165603.21,165603.22,165603.23,165603.24,165603.25,165603.26,165603.27,165603.28,165603.29,165603.30,165603.31,165603.32,165603.33,165603.34,165603.35,165603.36,165603.37,165603.38,165603.39,165603.40,165603.41,165603.42] || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 165687[57:MRR:165605.1,165684.0] xuntil6(s49) || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 165688[58:Spt:165685.0] || -> trans(s49,s46)*. % 76.16/76.36 165689[58:Res:165688.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s46)*. % 76.16/76.36 165691[58:Res:165688.0,60.0] || -> node2(s49,s46)*. % 76.16/76.36 165692[58:SSi:165689.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s46)*. % 76.16/76.36 165693[58:Res:165691.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 165709[58:SoR:165693.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 165711[58:SoR:165709.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)* xuntil6(s49). % 76.16/76.36 165712[58:SSi:165711.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s46,c_busy)* xuntil6(s49). % 76.16/76.36 165713[59:Spt:165712.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 165715[59:Res:165713.0,61.1] always3(s46) || -> . % 76.16/76.36 165716[59:SSi:165715.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 165717[59:Spt:165716.0,165712.1,165713.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.16/76.36 165718[59:Spt:165716.0,165712.0,165712.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 165722[59:MRR:165709.2,165717.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 165723[59:Res:53.1,165718.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 165725[59:MRR:165723.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 165726[59:MRR:165692.0,165725.0] || -> until2p7(s46)*. % 76.16/76.36 165727[59:MRR:549.0,165726.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 165728[60:Spt:165727.0] || -> until2p7(s47)*. % 76.16/76.36 165729[60:MRR:554.0,165728.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 165730[61:Spt:165729.0] || -> until2p7(s48)*. % 76.16/76.36 165731[61:MRR:559.0,165730.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 165732[62:Spt:165731.0] || -> until2p7(s49)*. % 76.16/76.36 165733[62:MRR:194.0,165732.0] || -> node4(s49)*. % 76.16/76.36 165734[62:MRR:165722.0,165733.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 165735[62:Res:53.1,165734.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 165737[62:MRR:165735.0,78381.0] || -> . % 76.16/76.36 165738[62:Spt:165737.0,165731.0,165732.0] || until2p7(s49)*+ -> . % 76.16/76.36 165739[62:Spt:165737.0,165731.1] || -> node4(s48)*. % 76.16/76.36 165740[62:MRR:78384.0,165739.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 165743[62:Res:53.1,165740.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 165746[62:Res:165743.0,61.1] always3(s48) || -> . % 76.16/76.36 165747[62:SSi:165746.0,78281.0,78387.0,165540.0,165730.0,165739.0] || -> . % 76.16/76.36 165748[61:Spt:165747.0,165729.0,165730.0] || until2p7(s48)*+ -> . % 76.16/76.36 165749[61:Spt:165747.0,165729.1] || -> node4(s47)*. % 76.16/76.36 165751[61:MRR:777.0,165749.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 165769[61:Res:53.1,165751.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 165771[62:Spt:165769.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 165773[62:Res:165771.0,61.1] always3(s47) || -> . % 76.16/76.36 165774[62:SSi:165773.0,78277.0,78280.0,165539.0,165728.0,165749.0] || -> . % 76.16/76.36 165775[62:Spt:165774.0,165769.0,165771.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 165776[62:Spt:165774.0,165769.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 165780[62:Res:165776.0,61.1] always3(s48) || -> . % 76.16/76.36 165781[62:SSi:165780.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 165782[60:Spt:165781.0,165727.0,165728.0] || until2p7(s47)*+ -> . % 76.16/76.36 165783[60:Spt:165781.0,165727.1] || -> node4(s46)*. % 76.16/76.36 165785[60:MRR:780.0,165783.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 165792[60:Res:53.1,165785.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 165794[60:MRR:165792.0,165717.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 165799[60:Res:165794.0,61.1] always3(s47) || -> . % 76.16/76.36 165800[60:SSi:165799.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 165801[58:Spt:165800.0,165685.0,165688.0] || trans(s49,s46)*+ -> . % 76.16/76.36 165802[58:Spt:165800.0,165685.1,165685.2,165685.3,165685.4,165685.5,165685.6,165685.7,165685.8,165685.9,165685.10,165685.11,165685.12,165685.13,165685.14,165685.15,165685.16,165685.17,165685.18,165685.19,165685.20,165685.21,165685.22,165685.23,165685.24,165685.25,165685.26,165685.27,165685.28,165685.29,165685.30,165685.31,165685.32,165685.33,165685.34,165685.35,165685.36,165685.37,165685.38,165685.39,165685.40,165685.41] || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 165804[58:MRR:165687.1,165801.0] xuntil6(s49) || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 165805[59:Spt:165802.0] || -> trans(s49,s45)*. % 76.16/76.36 165806[59:Res:165805.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s45)*. % 76.16/76.36 165808[59:Res:165805.0,60.0] || -> node2(s49,s45)*. % 76.16/76.36 165809[59:SSi:165806.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s45)*. % 76.16/76.36 165810[59:Res:165808.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 165826[59:SoR:165810.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 165828[59:SoR:165826.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)* xuntil6(s49). % 76.16/76.36 165829[59:SSi:165828.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s45,c_busy)* xuntil6(s49). % 76.16/76.36 165830[60:Spt:165829.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 165832[60:Res:165830.0,61.1] always3(s45) || -> . % 76.16/76.36 165833[60:SSi:165832.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 165834[60:Spt:165833.0,165829.1,165830.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.16/76.36 165835[60:Spt:165833.0,165829.0,165829.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 165839[60:MRR:165826.2,165834.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 165840[60:Res:53.1,165835.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 165842[60:MRR:165840.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 165843[60:MRR:165809.0,165842.0] || -> until2p7(s45)*. % 76.16/76.36 165844[60:MRR:544.0,165843.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 165845[61:Spt:165844.0] || -> until2p7(s46)*. % 76.16/76.36 165846[61:MRR:549.0,165845.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 165847[62:Spt:165846.0] || -> until2p7(s47)*. % 76.16/76.36 165848[62:MRR:554.0,165847.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 165849[63:Spt:165848.0] || -> until2p7(s48)*. % 76.16/76.36 165850[63:MRR:559.0,165849.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 165851[64:Spt:165850.0] || -> until2p7(s49)*. % 76.16/76.36 165852[64:MRR:194.0,165851.0] || -> node4(s49)*. % 76.16/76.36 165853[64:MRR:165839.0,165852.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 165854[64:Res:53.1,165853.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 165856[64:MRR:165854.0,78381.0] || -> . % 76.16/76.36 165857[64:Spt:165856.0,165850.0,165851.0] || until2p7(s49)*+ -> . % 76.16/76.36 165858[64:Spt:165856.0,165850.1] || -> node4(s48)*. % 76.16/76.36 165859[64:MRR:78384.0,165858.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 165862[64:Res:53.1,165859.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 165865[64:Res:165862.0,61.1] always3(s48) || -> . % 76.16/76.36 165866[64:SSi:165865.0,78281.0,78387.0,165540.0,165849.0,165858.0] || -> . % 76.16/76.36 165867[63:Spt:165866.0,165848.0,165849.0] || until2p7(s48)*+ -> . % 76.16/76.36 165868[63:Spt:165866.0,165848.1] || -> node4(s47)*. % 76.16/76.36 165870[63:MRR:777.0,165868.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 165885[63:Res:53.1,165870.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 165887[64:Spt:165885.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 165889[64:Res:165887.0,61.1] always3(s47) || -> . % 76.16/76.36 165890[64:SSi:165889.0,78277.0,78280.0,165539.0,165847.0,165868.0] || -> . % 76.16/76.36 165891[64:Spt:165890.0,165885.0,165887.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 165892[64:Spt:165890.0,165885.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 165896[64:Res:165892.0,61.1] always3(s48) || -> . % 76.16/76.36 165897[64:SSi:165896.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 165898[62:Spt:165897.0,165846.0,165847.0] || until2p7(s47)*+ -> . % 76.16/76.36 165899[62:Spt:165897.0,165846.1] || -> node4(s46)*. % 76.16/76.36 165901[62:MRR:780.0,165899.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 165911[62:Res:53.1,165901.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 165913[63:Spt:165911.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 165915[63:Res:165913.0,61.1] always3(s46) || -> . % 76.16/76.36 165916[63:SSi:165915.0,78272.0,78276.0,165538.0,165845.0,165899.0] || -> . % 76.16/76.36 165917[63:Spt:165916.0,165911.0,165913.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 165918[63:Spt:165916.0,165911.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 165922[63:Res:165918.0,61.1] always3(s47) || -> . % 76.16/76.36 165923[63:SSi:165922.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 165924[61:Spt:165923.0,165844.0,165845.0] || until2p7(s46)*+ -> . % 76.16/76.36 165925[61:Spt:165923.0,165844.1] || -> node4(s45)*. % 76.16/76.36 165927[61:MRR:783.0,165925.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 165930[61:Res:53.1,165927.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 165932[61:MRR:165930.0,165834.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 165934[61:Res:165932.0,61.1] always3(s46) || -> . % 76.16/76.36 165935[61:SSi:165934.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 165936[59:Spt:165935.0,165802.0,165805.0] || trans(s49,s45)*+ -> . % 76.16/76.36 165937[59:Spt:165935.0,165802.1,165802.2,165802.3,165802.4,165802.5,165802.6,165802.7,165802.8,165802.9,165802.10,165802.11,165802.12,165802.13,165802.14,165802.15,165802.16,165802.17,165802.18,165802.19,165802.20,165802.21,165802.22,165802.23,165802.24,165802.25,165802.26,165802.27,165802.28,165802.29,165802.30,165802.31,165802.32,165802.33,165802.34,165802.35,165802.36,165802.37,165802.38,165802.39,165802.40] || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 165939[59:MRR:165804.1,165936.0] xuntil6(s49) || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 165940[60:Spt:165937.0] || -> trans(s49,s44)*. % 76.16/76.36 165941[60:Res:165940.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s44)*. % 76.16/76.36 165943[60:Res:165940.0,60.0] || -> node2(s49,s44)*. % 76.16/76.36 165944[60:SSi:165941.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s44)*. % 76.16/76.36 165945[60:Res:165943.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 165965[60:SoR:165945.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 165967[60:SoR:165965.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)* xuntil6(s49). % 76.16/76.36 165968[60:SSi:165967.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s44,c_busy)* xuntil6(s49). % 76.16/76.36 165969[61:Spt:165968.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 165971[61:Res:165969.0,61.1] always3(s44) || -> . % 76.16/76.36 165972[61:SSi:165971.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.36 165973[61:Spt:165972.0,165968.1,165969.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.16/76.36 165974[61:Spt:165972.0,165968.0,165968.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 165978[61:MRR:165965.2,165973.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 165979[61:Res:53.1,165974.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 165981[61:MRR:165979.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 165982[61:MRR:165944.0,165981.0] || -> until2p7(s44)*. % 76.16/76.36 165983[61:MRR:539.0,165982.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 165984[62:Spt:165983.0] || -> until2p7(s45)*. % 76.16/76.36 165985[62:MRR:544.0,165984.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 165986[63:Spt:165985.0] || -> until2p7(s46)*. % 76.16/76.36 165987[63:MRR:549.0,165986.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 165988[64:Spt:165987.0] || -> until2p7(s47)*. % 76.16/76.36 165989[64:MRR:554.0,165988.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 165990[65:Spt:165989.0] || -> until2p7(s48)*. % 76.16/76.36 165991[65:MRR:559.0,165990.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 165992[66:Spt:165991.0] || -> until2p7(s49)*. % 76.16/76.36 165993[66:MRR:194.0,165992.0] || -> node4(s49)*. % 76.16/76.36 165994[66:MRR:165978.0,165993.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 165995[66:Res:53.1,165994.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 165997[66:MRR:165995.0,78381.0] || -> . % 76.16/76.36 165998[66:Spt:165997.0,165991.0,165992.0] || until2p7(s49)*+ -> . % 76.16/76.36 165999[66:Spt:165997.0,165991.1] || -> node4(s48)*. % 76.16/76.36 166000[66:MRR:78384.0,165999.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 166003[66:Res:53.1,166000.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 166006[66:Res:166003.0,61.1] always3(s48) || -> . % 76.16/76.36 166007[66:SSi:166006.0,78281.0,78387.0,165540.0,165990.0,165999.0] || -> . % 76.16/76.36 166008[65:Spt:166007.0,165989.0,165990.0] || until2p7(s48)*+ -> . % 76.16/76.36 166009[65:Spt:166007.0,165989.1] || -> node4(s47)*. % 76.16/76.36 166011[65:MRR:777.0,166009.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 166026[65:Res:53.1,166011.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 166028[66:Spt:166026.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 166030[66:Res:166028.0,61.1] always3(s47) || -> . % 76.16/76.36 166031[66:SSi:166030.0,78277.0,78280.0,165539.0,165988.0,166009.0] || -> . % 76.16/76.36 166032[66:Spt:166031.0,166026.0,166028.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 166033[66:Spt:166031.0,166026.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 166037[66:Res:166033.0,61.1] always3(s48) || -> . % 76.16/76.36 166038[66:SSi:166037.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 166039[64:Spt:166038.0,165987.0,165988.0] || until2p7(s47)*+ -> . % 76.16/76.36 166040[64:Spt:166038.0,165987.1] || -> node4(s46)*. % 76.16/76.36 166042[64:MRR:780.0,166040.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 166052[64:Res:53.1,166042.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 166054[65:Spt:166052.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 166056[65:Res:166054.0,61.1] always3(s46) || -> . % 76.16/76.36 166057[65:SSi:166056.0,78272.0,78276.0,165538.0,165986.0,166040.0] || -> . % 76.16/76.36 166058[65:Spt:166057.0,166052.0,166054.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 166059[65:Spt:166057.0,166052.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 166063[65:Res:166059.0,61.1] always3(s47) || -> . % 76.16/76.36 166064[65:SSi:166063.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 166065[63:Spt:166064.0,165985.0,165986.0] || until2p7(s46)*+ -> . % 76.16/76.36 166066[63:Spt:166064.0,165985.1] || -> node4(s45)*. % 76.16/76.36 166068[63:MRR:783.0,166066.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 166071[63:Res:53.1,166068.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 166073[64:Spt:166071.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 166075[64:Res:166073.0,61.1] always3(s45) || -> . % 76.16/76.36 166076[64:SSi:166075.0,78268.0,78271.0,165537.0,165984.0,166066.0] || -> . % 76.16/76.36 166077[64:Spt:166076.0,166071.0,166073.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 166078[64:Spt:166076.0,166071.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 166082[64:Res:166078.0,61.1] always3(s46) || -> . % 76.16/76.36 166083[64:SSi:166082.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 166084[62:Spt:166083.0,165983.0,165984.0] || until2p7(s45)*+ -> . % 76.16/76.36 166085[62:Spt:166083.0,165983.1] || -> node4(s44)*. % 76.16/76.36 166087[62:MRR:786.0,166085.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 166090[62:Res:53.1,166087.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 166092[62:MRR:166090.0,165973.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 166094[62:Res:166092.0,61.1] always3(s45) || -> . % 76.16/76.36 166095[62:SSi:166094.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 166096[60:Spt:166095.0,165937.0,165940.0] || trans(s49,s44)*+ -> . % 76.16/76.36 166097[60:Spt:166095.0,165937.1,165937.2,165937.3,165937.4,165937.5,165937.6,165937.7,165937.8,165937.9,165937.10,165937.11,165937.12,165937.13,165937.14,165937.15,165937.16,165937.17,165937.18,165937.19,165937.20,165937.21,165937.22,165937.23,165937.24,165937.25,165937.26,165937.27,165937.28,165937.29,165937.30,165937.31,165937.32,165937.33,165937.34,165937.35,165937.36,165937.37,165937.38,165937.39] || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 166099[60:MRR:165939.1,166096.0] xuntil6(s49) || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 166100[61:Spt:166097.0] || -> trans(s49,s43)*. % 76.16/76.36 166101[61:Res:166100.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s43)*. % 76.16/76.36 166103[61:Res:166100.0,60.0] || -> node2(s49,s43)*. % 76.16/76.36 166104[61:SSi:166101.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s43)*. % 76.16/76.36 166105[61:Res:166103.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 166129[61:SoR:166105.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 166131[61:SoR:166129.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 76.16/76.36 166132[61:SSi:166131.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 76.16/76.36 166133[62:Spt:166132.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 166135[62:Res:166133.0,61.1] always3(s43) || -> . % 76.16/76.36 166136[62:SSi:166135.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.36 166137[62:Spt:166136.0,166132.1,166133.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.16/76.36 166138[62:Spt:166136.0,166132.0,166132.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 166142[62:MRR:166129.2,166137.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 166143[62:Res:53.1,166138.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 166145[62:MRR:166143.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 166146[62:MRR:166104.0,166145.0] || -> until2p7(s43)*. % 76.16/76.36 166147[62:MRR:241.0,166146.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 166148[63:Spt:166147.0] || -> until2p7(s44)*. % 76.16/76.36 166149[63:MRR:539.0,166148.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 166150[64:Spt:166149.0] || -> until2p7(s45)*. % 76.16/76.36 166151[64:MRR:544.0,166150.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 166152[65:Spt:166151.0] || -> until2p7(s46)*. % 76.16/76.36 166153[65:MRR:549.0,166152.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 166154[66:Spt:166153.0] || -> until2p7(s47)*. % 76.16/76.36 166155[66:MRR:554.0,166154.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 166156[67:Spt:166155.0] || -> until2p7(s48)*. % 76.16/76.36 166157[67:MRR:559.0,166156.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 166158[68:Spt:166157.0] || -> until2p7(s49)*. % 76.16/76.36 166159[68:MRR:194.0,166158.0] || -> node4(s49)*. % 76.16/76.36 166160[68:MRR:166142.0,166159.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 166164[68:Res:53.1,166160.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 166166[68:MRR:166164.0,78381.0] || -> . % 76.16/76.36 166167[68:Spt:166166.0,166157.0,166158.0] || until2p7(s49)*+ -> . % 76.16/76.36 166168[68:Spt:166166.0,166157.1] || -> node4(s48)*. % 76.16/76.36 166169[68:MRR:78384.0,166168.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 166172[68:Res:53.1,166169.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 166175[68:Res:166172.0,61.1] always3(s48) || -> . % 76.16/76.36 166176[68:SSi:166175.0,78281.0,78387.0,165540.0,166156.0,166168.0] || -> . % 76.16/76.36 166177[67:Spt:166176.0,166155.0,166156.0] || until2p7(s48)*+ -> . % 76.16/76.36 166178[67:Spt:166176.0,166155.1] || -> node4(s47)*. % 76.16/76.36 166180[67:MRR:777.0,166178.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 166192[67:Res:53.1,166180.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 166194[68:Spt:166192.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 166196[68:Res:166194.0,61.1] always3(s47) || -> . % 76.16/76.36 166197[68:SSi:166196.0,78277.0,78280.0,165539.0,166154.0,166178.0] || -> . % 76.16/76.36 166198[68:Spt:166197.0,166192.0,166194.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 166199[68:Spt:166197.0,166192.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 166203[68:Res:166199.0,61.1] always3(s48) || -> . % 76.16/76.36 166204[68:SSi:166203.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 166205[66:Spt:166204.0,166153.0,166154.0] || until2p7(s47)*+ -> . % 76.16/76.36 166206[66:Spt:166204.0,166153.1] || -> node4(s46)*. % 76.16/76.36 166208[66:MRR:780.0,166206.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 166215[66:Res:53.1,166208.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 166220[67:Spt:166215.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 166222[67:Res:166220.0,61.1] always3(s46) || -> . % 76.16/76.36 166223[67:SSi:166222.0,78272.0,78276.0,165538.0,166152.0,166206.0] || -> . % 76.16/76.36 166224[67:Spt:166223.0,166215.0,166220.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 166225[67:Spt:166223.0,166215.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 166229[67:Res:166225.0,61.1] always3(s47) || -> . % 76.16/76.36 166230[67:SSi:166229.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 166231[65:Spt:166230.0,166151.0,166152.0] || until2p7(s46)*+ -> . % 76.16/76.36 166232[65:Spt:166230.0,166151.1] || -> node4(s45)*. % 76.16/76.36 166234[65:MRR:783.0,166232.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 166237[65:Res:53.1,166234.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 166239[66:Spt:166237.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 166241[66:Res:166239.0,61.1] always3(s45) || -> . % 76.16/76.36 166242[66:SSi:166241.0,78268.0,78271.0,165537.0,166150.0,166232.0] || -> . % 76.16/76.36 166243[66:Spt:166242.0,166237.0,166239.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 166244[66:Spt:166242.0,166237.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 166248[66:Res:166244.0,61.1] always3(s46) || -> . % 76.16/76.36 166249[66:SSi:166248.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 166250[64:Spt:166249.0,166149.0,166150.0] || until2p7(s45)*+ -> . % 76.16/76.36 166251[64:Spt:166249.0,166149.1] || -> node4(s44)*. % 76.16/76.36 166253[64:MRR:786.0,166251.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 166256[64:Res:53.1,166253.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 166258[65:Spt:166256.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 166260[65:Res:166258.0,61.1] always3(s44) || -> . % 76.16/76.36 166261[65:SSi:166260.0,78263.0,78267.0,165536.0,166148.0,166251.0] || -> . % 76.16/76.36 166262[65:Spt:166261.0,166256.0,166258.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 166263[65:Spt:166261.0,166256.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 166267[65:Res:166263.0,61.1] always3(s45) || -> . % 76.16/76.36 166268[65:SSi:166267.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 166269[63:Spt:166268.0,166147.0,166148.0] || until2p7(s44)*+ -> . % 76.16/76.36 166270[63:Spt:166268.0,166147.1] || -> node4(s43)*. % 76.16/76.36 166272[63:MRR:789.0,166270.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 166275[63:Res:53.1,166272.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 166277[63:MRR:166275.0,166137.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 166279[63:Res:166277.0,61.1] always3(s44) || -> . % 76.16/76.36 166280[63:SSi:166279.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.36 166281[61:Spt:166280.0,166097.0,166100.0] || trans(s49,s43)*+ -> . % 76.16/76.36 166282[61:Spt:166280.0,166097.1,166097.2,166097.3,166097.4,166097.5,166097.6,166097.7,166097.8,166097.9,166097.10,166097.11,166097.12,166097.13,166097.14,166097.15,166097.16,166097.17,166097.18,166097.19,166097.20,166097.21,166097.22,166097.23,166097.24,166097.25,166097.26,166097.27,166097.28,166097.29,166097.30,166097.31,166097.32,166097.33,166097.34,166097.35,166097.36,166097.37,166097.38] || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 166284[61:MRR:166099.1,166281.0] xuntil6(s49) || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 166285[62:Spt:166282.0] || -> trans(s49,s42)*. % 76.16/76.36 166286[62:Res:166285.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s42)*. % 76.16/76.36 166288[62:Res:166285.0,60.0] || -> node2(s49,s42)*. % 76.16/76.36 166289[62:SSi:166286.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s42)*. % 76.16/76.36 166290[62:Res:166288.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 166318[62:SoR:166290.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 166320[62:SoR:166318.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)* xuntil6(s49). % 76.16/76.36 166321[62:SSi:166320.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s42,c_busy)* xuntil6(s49). % 76.16/76.36 166322[63:Spt:166321.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 166324[63:Res:166322.0,61.1] always3(s42) || -> . % 76.16/76.36 166325[63:SSi:166324.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.36 166326[63:Spt:166325.0,166321.1,166322.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.16/76.36 166327[63:Spt:166325.0,166321.0,166321.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 166331[63:MRR:166318.2,166326.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 166332[63:Res:53.1,166327.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 166334[63:MRR:166332.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 166335[63:MRR:166289.0,166334.0] || -> until2p7(s42)*. % 76.16/76.36 166336[63:MRR:240.0,166335.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 166337[64:Spt:166336.0] || -> until2p7(s43)*. % 76.16/76.36 166338[64:MRR:241.0,166337.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 166339[65:Spt:166338.0] || -> until2p7(s44)*. % 76.16/76.36 166340[65:MRR:539.0,166339.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 166341[66:Spt:166340.0] || -> until2p7(s45)*. % 76.16/76.36 166342[66:MRR:544.0,166341.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 166343[67:Spt:166342.0] || -> until2p7(s46)*. % 76.16/76.36 166344[67:MRR:549.0,166343.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 166345[68:Spt:166344.0] || -> until2p7(s47)*. % 76.16/76.36 166346[68:MRR:554.0,166345.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 166347[69:Spt:166346.0] || -> until2p7(s48)*. % 76.16/76.36 166348[69:MRR:559.0,166347.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 166349[70:Spt:166348.0] || -> until2p7(s49)*. % 76.16/76.36 166350[70:MRR:194.0,166349.0] || -> node4(s49)*. % 76.16/76.36 166351[70:MRR:166331.0,166350.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 166352[70:Res:53.1,166351.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 166354[70:MRR:166352.0,78381.0] || -> . % 76.16/76.36 166355[70:Spt:166354.0,166348.0,166349.0] || until2p7(s49)*+ -> . % 76.16/76.36 166356[70:Spt:166354.0,166348.1] || -> node4(s48)*. % 76.16/76.36 166357[70:MRR:78384.0,166356.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 166360[70:Res:53.1,166357.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 166363[70:Res:166360.0,61.1] always3(s48) || -> . % 76.16/76.36 166364[70:SSi:166363.0,78281.0,78387.0,165540.0,166347.0,166356.0] || -> . % 76.16/76.36 166365[69:Spt:166364.0,166346.0,166347.0] || until2p7(s48)*+ -> . % 76.16/76.36 166366[69:Spt:166364.0,166346.1] || -> node4(s47)*. % 76.16/76.36 166368[69:MRR:777.0,166366.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 166383[69:Res:53.1,166368.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 166388[70:Spt:166383.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 166390[70:Res:166388.0,61.1] always3(s47) || -> . % 76.16/76.36 166391[70:SSi:166390.0,78277.0,78280.0,165539.0,166345.0,166366.0] || -> . % 76.16/76.36 166392[70:Spt:166391.0,166383.0,166388.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 166393[70:Spt:166391.0,166383.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 166397[70:Res:166393.0,61.1] always3(s48) || -> . % 76.16/76.36 166398[70:SSi:166397.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 166399[68:Spt:166398.0,166344.0,166345.0] || until2p7(s47)*+ -> . % 76.16/76.36 166400[68:Spt:166398.0,166344.1] || -> node4(s46)*. % 76.16/76.36 166402[68:MRR:780.0,166400.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 166409[68:Res:53.1,166402.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 166411[69:Spt:166409.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 166413[69:Res:166411.0,61.1] always3(s46) || -> . % 76.16/76.36 166414[69:SSi:166413.0,78272.0,78276.0,165538.0,166343.0,166400.0] || -> . % 76.16/76.36 166415[69:Spt:166414.0,166409.0,166411.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 166416[69:Spt:166414.0,166409.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 166420[69:Res:166416.0,61.1] always3(s47) || -> . % 76.16/76.36 166421[69:SSi:166420.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 166422[67:Spt:166421.0,166342.0,166343.0] || until2p7(s46)*+ -> . % 76.16/76.36 166423[67:Spt:166421.0,166342.1] || -> node4(s45)*. % 76.16/76.36 166425[67:MRR:783.0,166423.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 166428[67:Res:53.1,166425.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 166433[68:Spt:166428.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 166435[68:Res:166433.0,61.1] always3(s45) || -> . % 76.16/76.36 166436[68:SSi:166435.0,78268.0,78271.0,165537.0,166341.0,166423.0] || -> . % 76.16/76.36 166437[68:Spt:166436.0,166428.0,166433.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 166438[68:Spt:166436.0,166428.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 166442[68:Res:166438.0,61.1] always3(s46) || -> . % 76.16/76.36 166443[68:SSi:166442.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 166444[66:Spt:166443.0,166340.0,166341.0] || until2p7(s45)*+ -> . % 76.16/76.36 166445[66:Spt:166443.0,166340.1] || -> node4(s44)*. % 76.16/76.36 166447[66:MRR:786.0,166445.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 166450[66:Res:53.1,166447.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 166452[67:Spt:166450.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 166454[67:Res:166452.0,61.1] always3(s44) || -> . % 76.16/76.36 166455[67:SSi:166454.0,78263.0,78267.0,165536.0,166339.0,166445.0] || -> . % 76.16/76.36 166456[67:Spt:166455.0,166450.0,166452.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 166457[67:Spt:166455.0,166450.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 166461[67:Res:166457.0,61.1] always3(s45) || -> . % 76.16/76.36 166462[67:SSi:166461.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 166463[65:Spt:166462.0,166338.0,166339.0] || until2p7(s44)*+ -> . % 76.16/76.36 166464[65:Spt:166462.0,166338.1] || -> node4(s43)*. % 76.16/76.36 166466[65:MRR:789.0,166464.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 166469[65:Res:53.1,166466.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 166471[66:Spt:166469.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 166473[66:Res:166471.0,61.1] always3(s43) || -> . % 76.16/76.36 166474[66:SSi:166473.0,78259.0,78262.0,165535.0,166337.0,166464.0] || -> . % 76.16/76.36 166475[66:Spt:166474.0,166469.0,166471.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 166476[66:Spt:166474.0,166469.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 166480[66:Res:166476.0,61.1] always3(s44) || -> . % 76.16/76.36 166481[66:SSi:166480.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.36 166482[64:Spt:166481.0,166336.0,166337.0] || until2p7(s43)*+ -> . % 76.16/76.36 166483[64:Spt:166481.0,166336.1] || -> node4(s42)*. % 76.16/76.36 166485[64:MRR:792.0,166483.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 166488[64:Res:53.1,166485.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 166490[64:MRR:166488.0,166326.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 166492[64:Res:166490.0,61.1] always3(s43) || -> . % 76.16/76.36 166493[64:SSi:166492.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.36 166494[62:Spt:166493.0,166282.0,166285.0] || trans(s49,s42)*+ -> . % 76.16/76.36 166495[62:Spt:166493.0,166282.1,166282.2,166282.3,166282.4,166282.5,166282.6,166282.7,166282.8,166282.9,166282.10,166282.11,166282.12,166282.13,166282.14,166282.15,166282.16,166282.17,166282.18,166282.19,166282.20,166282.21,166282.22,166282.23,166282.24,166282.25,166282.26,166282.27,166282.28,166282.29,166282.30,166282.31,166282.32,166282.33,166282.34,166282.35,166282.36,166282.37] || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 166497[62:MRR:166284.1,166494.0] xuntil6(s49) || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 166498[63:Spt:166495.0] || -> trans(s49,s41)*. % 76.16/76.36 166499[63:Res:166498.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s41)*. % 76.16/76.36 166501[63:Res:166498.0,60.0] || -> node2(s49,s41)*. % 76.16/76.36 166502[63:SSi:166499.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s41)*. % 76.16/76.36 166503[63:Res:166501.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 166532[63:SoR:166503.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 166534[63:SoR:166532.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)* xuntil6(s49). % 76.16/76.36 166535[63:SSi:166534.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s41,c_busy)* xuntil6(s49). % 76.16/76.36 166536[64:Spt:166535.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 166538[64:Res:166536.0,61.1] always3(s41) || -> . % 76.16/76.36 166539[64:SSi:166538.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.36 166540[64:Spt:166539.0,166535.1,166536.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.16/76.36 166541[64:Spt:166539.0,166535.0,166535.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 166545[64:MRR:166532.2,166540.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 166546[64:Res:53.1,166541.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 166548[64:MRR:166546.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 166549[64:MRR:166502.0,166548.0] || -> until2p7(s41)*. % 76.16/76.36 166550[64:MRR:239.0,166549.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 166551[65:Spt:166550.0] || -> until2p7(s42)*. % 76.16/76.36 166552[65:MRR:240.0,166551.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 166553[66:Spt:166552.0] || -> until2p7(s43)*. % 76.16/76.36 166554[66:MRR:241.0,166553.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 166555[67:Spt:166554.0] || -> until2p7(s44)*. % 76.16/76.36 166556[67:MRR:539.0,166555.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 166557[68:Spt:166556.0] || -> until2p7(s45)*. % 76.16/76.36 166558[68:MRR:544.0,166557.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 166559[69:Spt:166558.0] || -> until2p7(s46)*. % 76.16/76.36 166560[69:MRR:549.0,166559.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 166561[70:Spt:166560.0] || -> until2p7(s47)*. % 76.16/76.36 166562[70:MRR:554.0,166561.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 166563[71:Spt:166562.0] || -> until2p7(s48)*. % 76.16/76.36 166564[71:MRR:559.0,166563.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 166565[72:Spt:166564.0] || -> until2p7(s49)*. % 76.16/76.36 166566[72:MRR:194.0,166565.0] || -> node4(s49)*. % 76.16/76.36 166567[72:MRR:166545.0,166566.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 166571[72:Res:53.1,166567.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 166573[72:MRR:166571.0,78381.0] || -> . % 76.16/76.36 166574[72:Spt:166573.0,166564.0,166565.0] || until2p7(s49)*+ -> . % 76.16/76.36 166575[72:Spt:166573.0,166564.1] || -> node4(s48)*. % 76.16/76.36 166576[72:MRR:78384.0,166575.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 166579[72:Res:53.1,166576.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 166582[72:Res:166579.0,61.1] always3(s48) || -> . % 76.16/76.36 166583[72:SSi:166582.0,78281.0,78387.0,165540.0,166563.0,166575.0] || -> . % 76.16/76.36 166584[71:Spt:166583.0,166562.0,166563.0] || until2p7(s48)*+ -> . % 76.16/76.36 166585[71:Spt:166583.0,166562.1] || -> node4(s47)*. % 76.16/76.36 166587[71:MRR:777.0,166585.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 166599[71:Res:53.1,166587.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 166601[72:Spt:166599.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 166603[72:Res:166601.0,61.1] always3(s47) || -> . % 76.16/76.36 166604[72:SSi:166603.0,78277.0,78280.0,165539.0,166561.0,166585.0] || -> . % 76.16/76.36 166605[72:Spt:166604.0,166599.0,166601.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 166606[72:Spt:166604.0,166599.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 166610[72:Res:166606.0,61.1] always3(s48) || -> . % 76.16/76.36 166611[72:SSi:166610.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 166612[70:Spt:166611.0,166560.0,166561.0] || until2p7(s47)*+ -> . % 76.16/76.36 166613[70:Spt:166611.0,166560.1] || -> node4(s46)*. % 76.16/76.36 166615[70:MRR:780.0,166613.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 166622[70:Res:53.1,166615.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 166627[71:Spt:166622.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 166629[71:Res:166627.0,61.1] always3(s46) || -> . % 76.16/76.36 166630[71:SSi:166629.0,78272.0,78276.0,165538.0,166559.0,166613.0] || -> . % 76.16/76.36 166631[71:Spt:166630.0,166622.0,166627.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 166632[71:Spt:166630.0,166622.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 166636[71:Res:166632.0,61.1] always3(s47) || -> . % 76.16/76.36 166637[71:SSi:166636.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 166638[69:Spt:166637.0,166558.0,166559.0] || until2p7(s46)*+ -> . % 76.16/76.36 166639[69:Spt:166637.0,166558.1] || -> node4(s45)*. % 76.16/76.36 166641[69:MRR:783.0,166639.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 166644[69:Res:53.1,166641.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 166646[70:Spt:166644.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 166648[70:Res:166646.0,61.1] always3(s45) || -> . % 76.16/76.36 166649[70:SSi:166648.0,78268.0,78271.0,165537.0,166557.0,166639.0] || -> . % 76.16/76.36 166650[70:Spt:166649.0,166644.0,166646.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 166651[70:Spt:166649.0,166644.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 166655[70:Res:166651.0,61.1] always3(s46) || -> . % 76.16/76.36 166656[70:SSi:166655.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 166657[68:Spt:166656.0,166556.0,166557.0] || until2p7(s45)*+ -> . % 76.16/76.36 166658[68:Spt:166656.0,166556.1] || -> node4(s44)*. % 76.16/76.36 166660[68:MRR:786.0,166658.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 166663[68:Res:53.1,166660.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 166665[69:Spt:166663.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 166667[69:Res:166665.0,61.1] always3(s44) || -> . % 76.16/76.36 166668[69:SSi:166667.0,78263.0,78267.0,165536.0,166555.0,166658.0] || -> . % 76.16/76.36 166669[69:Spt:166668.0,166663.0,166665.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 166670[69:Spt:166668.0,166663.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 166674[69:Res:166670.0,61.1] always3(s45) || -> . % 76.16/76.36 166675[69:SSi:166674.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 166676[67:Spt:166675.0,166554.0,166555.0] || until2p7(s44)*+ -> . % 76.16/76.36 166677[67:Spt:166675.0,166554.1] || -> node4(s43)*. % 76.16/76.36 166679[67:MRR:789.0,166677.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 166682[67:Res:53.1,166679.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 166684[68:Spt:166682.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 166686[68:Res:166684.0,61.1] always3(s43) || -> . % 76.16/76.36 166687[68:SSi:166686.0,78259.0,78262.0,165535.0,166553.0,166677.0] || -> . % 76.16/76.36 166688[68:Spt:166687.0,166682.0,166684.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 166689[68:Spt:166687.0,166682.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 166693[68:Res:166689.0,61.1] always3(s44) || -> . % 76.16/76.36 166694[68:SSi:166693.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.36 166695[66:Spt:166694.0,166552.0,166553.0] || until2p7(s43)*+ -> . % 76.16/76.36 166696[66:Spt:166694.0,166552.1] || -> node4(s42)*. % 76.16/76.36 166698[66:MRR:792.0,166696.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 166701[66:Res:53.1,166698.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 166706[67:Spt:166701.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 166708[67:Res:166706.0,61.1] always3(s42) || -> . % 76.16/76.36 166709[67:SSi:166708.0,78254.0,78258.0,165534.0,166551.0,166696.0] || -> . % 76.16/76.36 166710[67:Spt:166709.0,166701.0,166706.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 166711[67:Spt:166709.0,166701.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 166715[67:Res:166711.0,61.1] always3(s43) || -> . % 76.16/76.36 166716[67:SSi:166715.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.36 166717[65:Spt:166716.0,166550.0,166551.0] || until2p7(s42)*+ -> . % 76.16/76.36 166718[65:Spt:166716.0,166550.1] || -> node4(s41)*. % 76.16/76.36 166720[65:MRR:795.0,166718.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 166723[65:Res:53.1,166720.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 166725[65:MRR:166723.0,166540.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 166727[65:Res:166725.0,61.1] always3(s42) || -> . % 76.16/76.36 166728[65:SSi:166727.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.36 166729[63:Spt:166728.0,166495.0,166498.0] || trans(s49,s41)*+ -> . % 76.16/76.36 166730[63:Spt:166728.0,166495.1,166495.2,166495.3,166495.4,166495.5,166495.6,166495.7,166495.8,166495.9,166495.10,166495.11,166495.12,166495.13,166495.14,166495.15,166495.16,166495.17,166495.18,166495.19,166495.20,166495.21,166495.22,166495.23,166495.24,166495.25,166495.26,166495.27,166495.28,166495.29,166495.30,166495.31,166495.32,166495.33,166495.34,166495.35,166495.36] || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 166732[63:MRR:166497.1,166729.0] xuntil6(s49) || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 166733[64:Spt:166730.0] || -> trans(s49,s40)*. % 76.16/76.36 166734[64:Res:166733.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s40)*. % 76.16/76.36 166736[64:Res:166733.0,60.0] || -> node2(s49,s40)*. % 76.16/76.36 166737[64:SSi:166734.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s40)*. % 76.16/76.36 166738[64:Res:166736.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 166771[64:SoR:166738.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 166773[64:SoR:166771.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)* xuntil6(s49). % 76.16/76.36 166774[64:SSi:166773.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s40,c_busy)* xuntil6(s49). % 76.16/76.36 166775[65:Spt:166774.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 166777[65:Res:166775.0,61.1] always3(s40) || -> . % 76.16/76.36 166778[65:SSi:166777.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.36 166779[65:Spt:166778.0,166774.1,166775.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.16/76.36 166780[65:Spt:166778.0,166774.0,166774.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 166784[65:MRR:166771.2,166779.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 166785[65:Res:53.1,166780.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 166787[65:MRR:166785.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 166788[65:MRR:166737.0,166787.0] || -> until2p7(s40)*. % 76.16/76.36 166789[65:MRR:238.0,166788.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 166790[66:Spt:166789.0] || -> until2p7(s41)*. % 76.16/76.36 166791[66:MRR:239.0,166790.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 166792[67:Spt:166791.0] || -> until2p7(s42)*. % 76.16/76.36 166793[67:MRR:240.0,166792.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 166794[68:Spt:166793.0] || -> until2p7(s43)*. % 76.16/76.36 166795[68:MRR:241.0,166794.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 166796[69:Spt:166795.0] || -> until2p7(s44)*. % 76.16/76.36 166797[69:MRR:539.0,166796.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 166798[70:Spt:166797.0] || -> until2p7(s45)*. % 76.16/76.36 166799[70:MRR:544.0,166798.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 166800[71:Spt:166799.0] || -> until2p7(s46)*. % 76.16/76.36 166801[71:MRR:549.0,166800.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 166802[72:Spt:166801.0] || -> until2p7(s47)*. % 76.16/76.36 166803[72:MRR:554.0,166802.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 166804[73:Spt:166803.0] || -> until2p7(s48)*. % 76.16/76.36 166805[73:MRR:559.0,166804.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 166806[74:Spt:166805.0] || -> until2p7(s49)*. % 76.16/76.36 166807[74:MRR:194.0,166806.0] || -> node4(s49)*. % 76.16/76.36 166808[74:MRR:166784.0,166807.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 166809[74:Res:53.1,166808.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 166811[74:MRR:166809.0,78381.0] || -> . % 76.16/76.36 166812[74:Spt:166811.0,166805.0,166806.0] || until2p7(s49)*+ -> . % 76.16/76.36 166813[74:Spt:166811.0,166805.1] || -> node4(s48)*. % 76.16/76.36 166814[74:MRR:78384.0,166813.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 166817[74:Res:53.1,166814.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 166820[74:Res:166817.0,61.1] always3(s48) || -> . % 76.16/76.36 166821[74:SSi:166820.0,78281.0,78387.0,165540.0,166804.0,166813.0] || -> . % 76.16/76.36 166822[73:Spt:166821.0,166803.0,166804.0] || until2p7(s48)*+ -> . % 76.16/76.36 166823[73:Spt:166821.0,166803.1] || -> node4(s47)*. % 76.16/76.36 166825[73:MRR:777.0,166823.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 166840[73:Res:53.1,166825.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 166842[74:Spt:166840.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 166844[74:Res:166842.0,61.1] always3(s47) || -> . % 76.16/76.36 166845[74:SSi:166844.0,78277.0,78280.0,165539.0,166802.0,166823.0] || -> . % 76.16/76.36 166846[74:Spt:166845.0,166840.0,166842.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 166847[74:Spt:166845.0,166840.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 166851[74:Res:166847.0,61.1] always3(s48) || -> . % 76.16/76.36 166852[74:SSi:166851.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 166853[72:Spt:166852.0,166801.0,166802.0] || until2p7(s47)*+ -> . % 76.16/76.36 166854[72:Spt:166852.0,166801.1] || -> node4(s46)*. % 76.16/76.36 166856[72:MRR:780.0,166854.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 166866[72:Res:53.1,166856.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 166868[73:Spt:166866.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 166870[73:Res:166868.0,61.1] always3(s46) || -> . % 76.16/76.36 166871[73:SSi:166870.0,78272.0,78276.0,165538.0,166800.0,166854.0] || -> . % 76.16/76.36 166872[73:Spt:166871.0,166866.0,166868.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 166873[73:Spt:166871.0,166866.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 166877[73:Res:166873.0,61.1] always3(s47) || -> . % 76.16/76.36 166878[73:SSi:166877.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 166879[71:Spt:166878.0,166799.0,166800.0] || until2p7(s46)*+ -> . % 76.16/76.36 166880[71:Spt:166878.0,166799.1] || -> node4(s45)*. % 76.16/76.36 166882[71:MRR:783.0,166880.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 166885[71:Res:53.1,166882.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 166887[72:Spt:166885.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 166889[72:Res:166887.0,61.1] always3(s45) || -> . % 76.16/76.36 166890[72:SSi:166889.0,78268.0,78271.0,165537.0,166798.0,166880.0] || -> . % 76.16/76.36 166891[72:Spt:166890.0,166885.0,166887.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 166892[72:Spt:166890.0,166885.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 166896[72:Res:166892.0,61.1] always3(s46) || -> . % 76.16/76.36 166897[72:SSi:166896.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 166898[70:Spt:166897.0,166797.0,166798.0] || until2p7(s45)*+ -> . % 76.16/76.36 166899[70:Spt:166897.0,166797.1] || -> node4(s44)*. % 76.16/76.36 166901[70:MRR:786.0,166899.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 166904[70:Res:53.1,166901.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 166906[71:Spt:166904.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 166908[71:Res:166906.0,61.1] always3(s44) || -> . % 76.16/76.36 166909[71:SSi:166908.0,78263.0,78267.0,165536.0,166796.0,166899.0] || -> . % 76.16/76.36 166910[71:Spt:166909.0,166904.0,166906.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 166911[71:Spt:166909.0,166904.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 166915[71:Res:166911.0,61.1] always3(s45) || -> . % 76.16/76.36 166916[71:SSi:166915.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 166917[69:Spt:166916.0,166795.0,166796.0] || until2p7(s44)*+ -> . % 76.16/76.36 166918[69:Spt:166916.0,166795.1] || -> node4(s43)*. % 76.16/76.36 166920[69:MRR:789.0,166918.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 166923[69:Res:53.1,166920.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 166928[70:Spt:166923.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 166930[70:Res:166928.0,61.1] always3(s43) || -> . % 76.16/76.36 166931[70:SSi:166930.0,78259.0,78262.0,165535.0,166794.0,166918.0] || -> . % 76.16/76.36 166932[70:Spt:166931.0,166923.0,166928.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 166933[70:Spt:166931.0,166923.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 166937[70:Res:166933.0,61.1] always3(s44) || -> . % 76.16/76.36 166938[70:SSi:166937.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.36 166939[68:Spt:166938.0,166793.0,166794.0] || until2p7(s43)*+ -> . % 76.16/76.36 166940[68:Spt:166938.0,166793.1] || -> node4(s42)*. % 76.16/76.36 166942[68:MRR:792.0,166940.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 166945[68:Res:53.1,166942.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 166947[69:Spt:166945.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 166949[69:Res:166947.0,61.1] always3(s42) || -> . % 76.16/76.36 166950[69:SSi:166949.0,78254.0,78258.0,165534.0,166792.0,166940.0] || -> . % 76.16/76.36 166951[69:Spt:166950.0,166945.0,166947.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 166952[69:Spt:166950.0,166945.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 166956[69:Res:166952.0,61.1] always3(s43) || -> . % 76.16/76.36 166957[69:SSi:166956.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.36 166958[67:Spt:166957.0,166791.0,166792.0] || until2p7(s42)*+ -> . % 76.16/76.36 166959[67:Spt:166957.0,166791.1] || -> node4(s41)*. % 76.16/76.36 166961[67:MRR:795.0,166959.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 166964[67:Res:53.1,166961.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 166966[68:Spt:166964.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 166968[68:Res:166966.0,61.1] always3(s41) || -> . % 76.16/76.36 166969[68:SSi:166968.0,78250.0,78253.0,165533.0,166790.0,166959.0] || -> . % 76.16/76.36 166970[68:Spt:166969.0,166964.0,166966.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 166971[68:Spt:166969.0,166964.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 166975[68:Res:166971.0,61.1] always3(s42) || -> . % 76.16/76.36 166976[68:SSi:166975.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.36 166977[66:Spt:166976.0,166789.0,166790.0] || until2p7(s41)*+ -> . % 76.16/76.36 166978[66:Spt:166976.0,166789.1] || -> node4(s40)*. % 76.16/76.36 166980[66:MRR:798.0,166978.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 166983[66:Res:53.1,166980.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 166985[66:MRR:166983.0,166779.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 166987[66:Res:166985.0,61.1] always3(s41) || -> . % 76.16/76.36 166988[66:SSi:166987.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.36 166989[64:Spt:166988.0,166730.0,166733.0] || trans(s49,s40)*+ -> . % 76.16/76.36 166990[64:Spt:166988.0,166730.1,166730.2,166730.3,166730.4,166730.5,166730.6,166730.7,166730.8,166730.9,166730.10,166730.11,166730.12,166730.13,166730.14,166730.15,166730.16,166730.17,166730.18,166730.19,166730.20,166730.21,166730.22,166730.23,166730.24,166730.25,166730.26,166730.27,166730.28,166730.29,166730.30,166730.31,166730.32,166730.33,166730.34,166730.35] || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 166992[64:MRR:166732.1,166989.0] xuntil6(s49) || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 166993[65:Spt:166990.0] || -> trans(s49,s39)*. % 76.16/76.36 166994[65:Res:166993.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s39)*. % 76.16/76.36 166996[65:Res:166993.0,60.0] || -> node2(s49,s39)*. % 76.16/76.36 166997[65:SSi:166994.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s39)*. % 76.16/76.36 166998[65:Res:166996.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 167035[65:SoR:166998.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 167037[65:SoR:167035.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 76.16/76.36 167038[65:SSi:167037.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 76.16/76.36 167039[66:Spt:167038.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 167041[66:Res:167039.0,61.1] always3(s39) || -> . % 76.16/76.36 167042[66:SSi:167041.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.36 167043[66:Spt:167042.0,167038.1,167039.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.16/76.36 167044[66:Spt:167042.0,167038.0,167038.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 167048[66:MRR:167035.2,167043.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 167049[66:Res:53.1,167044.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 167051[66:MRR:167049.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 167052[66:MRR:166997.0,167051.0] || -> until2p7(s39)*. % 76.16/76.36 167053[66:MRR:237.0,167052.0] || -> until2p7(s40)* node4(s39). % 76.16/76.36 167054[67:Spt:167053.0] || -> until2p7(s40)*. % 76.16/76.36 167055[67:MRR:238.0,167054.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 167056[68:Spt:167055.0] || -> until2p7(s41)*. % 76.16/76.36 167057[68:MRR:239.0,167056.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 167058[69:Spt:167057.0] || -> until2p7(s42)*. % 76.16/76.36 167059[69:MRR:240.0,167058.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 167060[70:Spt:167059.0] || -> until2p7(s43)*. % 76.16/76.36 167061[70:MRR:241.0,167060.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 167062[71:Spt:167061.0] || -> until2p7(s44)*. % 76.16/76.36 167063[71:MRR:539.0,167062.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 167064[72:Spt:167063.0] || -> until2p7(s45)*. % 76.16/76.36 167065[72:MRR:544.0,167064.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 167066[73:Spt:167065.0] || -> until2p7(s46)*. % 76.16/76.36 167067[73:MRR:549.0,167066.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 167068[74:Spt:167067.0] || -> until2p7(s47)*. % 76.16/76.36 167069[74:MRR:554.0,167068.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 167070[75:Spt:167069.0] || -> until2p7(s48)*. % 76.16/76.36 167071[75:MRR:559.0,167070.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 167072[76:Spt:167071.0] || -> until2p7(s49)*. % 76.16/76.36 167073[76:MRR:194.0,167072.0] || -> node4(s49)*. % 76.16/76.36 167074[76:MRR:167048.0,167073.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 167075[76:Res:53.1,167074.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 167077[76:MRR:167075.0,78381.0] || -> . % 76.16/76.36 167078[76:Spt:167077.0,167071.0,167072.0] || until2p7(s49)*+ -> . % 76.16/76.36 167079[76:Spt:167077.0,167071.1] || -> node4(s48)*. % 76.16/76.36 167080[76:MRR:78384.0,167079.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 167083[76:Res:53.1,167080.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 167086[76:Res:167083.0,61.1] always3(s48) || -> . % 76.16/76.36 167087[76:SSi:167086.0,78281.0,78387.0,165540.0,167070.0,167079.0] || -> . % 76.16/76.36 167088[75:Spt:167087.0,167069.0,167070.0] || until2p7(s48)*+ -> . % 76.16/76.36 167089[75:Spt:167087.0,167069.1] || -> node4(s47)*. % 76.16/76.36 167091[75:MRR:777.0,167089.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 167106[75:Res:53.1,167091.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 167108[76:Spt:167106.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 167110[76:Res:167108.0,61.1] always3(s47) || -> . % 76.16/76.36 167111[76:SSi:167110.0,78277.0,78280.0,165539.0,167068.0,167089.0] || -> . % 76.16/76.36 167112[76:Spt:167111.0,167106.0,167108.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 167113[76:Spt:167111.0,167106.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 167117[76:Res:167113.0,61.1] always3(s48) || -> . % 76.16/76.36 167118[76:SSi:167117.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 167119[74:Spt:167118.0,167067.0,167068.0] || until2p7(s47)*+ -> . % 76.16/76.36 167120[74:Spt:167118.0,167067.1] || -> node4(s46)*. % 76.16/76.36 167122[74:MRR:780.0,167120.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 167132[74:Res:53.1,167122.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 167134[75:Spt:167132.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 167136[75:Res:167134.0,61.1] always3(s46) || -> . % 76.16/76.36 167137[75:SSi:167136.0,78272.0,78276.0,165538.0,167066.0,167120.0] || -> . % 76.16/76.36 167138[75:Spt:167137.0,167132.0,167134.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 167139[75:Spt:167137.0,167132.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 167143[75:Res:167139.0,61.1] always3(s47) || -> . % 76.16/76.36 167144[75:SSi:167143.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 167145[73:Spt:167144.0,167065.0,167066.0] || until2p7(s46)*+ -> . % 76.16/76.36 167146[73:Spt:167144.0,167065.1] || -> node4(s45)*. % 76.16/76.36 167148[73:MRR:783.0,167146.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 167151[73:Res:53.1,167148.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 167153[74:Spt:167151.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 167155[74:Res:167153.0,61.1] always3(s45) || -> . % 76.16/76.36 167156[74:SSi:167155.0,78268.0,78271.0,165537.0,167064.0,167146.0] || -> . % 76.16/76.36 167157[74:Spt:167156.0,167151.0,167153.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 167158[74:Spt:167156.0,167151.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 167162[74:Res:167158.0,61.1] always3(s46) || -> . % 76.16/76.36 167163[74:SSi:167162.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 167164[72:Spt:167163.0,167063.0,167064.0] || until2p7(s45)*+ -> . % 76.16/76.36 167165[72:Spt:167163.0,167063.1] || -> node4(s44)*. % 76.16/76.36 167167[72:MRR:786.0,167165.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 167170[72:Res:53.1,167167.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 167172[73:Spt:167170.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 167174[73:Res:167172.0,61.1] always3(s44) || -> . % 76.16/76.36 167175[73:SSi:167174.0,78263.0,78267.0,165536.0,167062.0,167165.0] || -> . % 76.16/76.36 167176[73:Spt:167175.0,167170.0,167172.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 167177[73:Spt:167175.0,167170.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 167181[73:Res:167177.0,61.1] always3(s45) || -> . % 76.16/76.36 167182[73:SSi:167181.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 167183[71:Spt:167182.0,167061.0,167062.0] || until2p7(s44)*+ -> . % 76.16/76.36 167184[71:Spt:167182.0,167061.1] || -> node4(s43)*. % 76.16/76.36 167186[71:MRR:789.0,167184.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 167189[71:Res:53.1,167186.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 167194[72:Spt:167189.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 167196[72:Res:167194.0,61.1] always3(s43) || -> . % 76.16/76.36 167197[72:SSi:167196.0,78259.0,78262.0,165535.0,167060.0,167184.0] || -> . % 76.16/76.36 167198[72:Spt:167197.0,167189.0,167194.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 167199[72:Spt:167197.0,167189.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 167203[72:Res:167199.0,61.1] always3(s44) || -> . % 76.16/76.36 167204[72:SSi:167203.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.36 167205[70:Spt:167204.0,167059.0,167060.0] || until2p7(s43)*+ -> . % 76.16/76.36 167206[70:Spt:167204.0,167059.1] || -> node4(s42)*. % 76.16/76.36 167208[70:MRR:792.0,167206.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 167211[70:Res:53.1,167208.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 167213[71:Spt:167211.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 167215[71:Res:167213.0,61.1] always3(s42) || -> . % 76.16/76.36 167216[71:SSi:167215.0,78254.0,78258.0,165534.0,167058.0,167206.0] || -> . % 76.16/76.36 167217[71:Spt:167216.0,167211.0,167213.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 167218[71:Spt:167216.0,167211.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 167222[71:Res:167218.0,61.1] always3(s43) || -> . % 76.16/76.36 167223[71:SSi:167222.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.36 167224[69:Spt:167223.0,167057.0,167058.0] || until2p7(s42)*+ -> . % 76.16/76.36 167225[69:Spt:167223.0,167057.1] || -> node4(s41)*. % 76.16/76.36 167227[69:MRR:795.0,167225.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 167230[69:Res:53.1,167227.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 167232[70:Spt:167230.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 167234[70:Res:167232.0,61.1] always3(s41) || -> . % 76.16/76.36 167235[70:SSi:167234.0,78250.0,78253.0,165533.0,167056.0,167225.0] || -> . % 76.16/76.36 167236[70:Spt:167235.0,167230.0,167232.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 167237[70:Spt:167235.0,167230.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 167241[70:Res:167237.0,61.1] always3(s42) || -> . % 76.16/76.36 167242[70:SSi:167241.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.36 167243[68:Spt:167242.0,167055.0,167056.0] || until2p7(s41)*+ -> . % 76.16/76.36 167244[68:Spt:167242.0,167055.1] || -> node4(s40)*. % 76.16/76.36 167246[68:MRR:798.0,167244.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 167249[68:Res:53.1,167246.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 167251[69:Spt:167249.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 167253[69:Res:167251.0,61.1] always3(s40) || -> . % 76.16/76.36 167254[69:SSi:167253.0,78245.0,78249.0,165532.0,167054.0,167244.0] || -> . % 76.16/76.36 167255[69:Spt:167254.0,167249.0,167251.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.36 167256[69:Spt:167254.0,167249.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 167260[69:Res:167256.0,61.1] always3(s41) || -> . % 76.16/76.36 167261[69:SSi:167260.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.36 167262[67:Spt:167261.0,167053.0,167054.0] || until2p7(s40)*+ -> . % 76.16/76.36 167263[67:Spt:167261.0,167053.1] || -> node4(s39)*. % 76.16/76.36 167265[67:MRR:801.0,167263.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.36 167268[67:Res:53.1,167265.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.36 167270[67:MRR:167268.0,167043.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 167275[67:Res:167270.0,61.1] always3(s40) || -> . % 76.16/76.36 167276[67:SSi:167275.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.36 167277[65:Spt:167276.0,166990.0,166993.0] || trans(s49,s39)*+ -> . % 76.16/76.36 167278[65:Spt:167276.0,166990.1,166990.2,166990.3,166990.4,166990.5,166990.6,166990.7,166990.8,166990.9,166990.10,166990.11,166990.12,166990.13,166990.14,166990.15,166990.16,166990.17,166990.18,166990.19,166990.20,166990.21,166990.22,166990.23,166990.24,166990.25,166990.26,166990.27,166990.28,166990.29,166990.30,166990.31,166990.32,166990.33,166990.34] || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 167280[65:MRR:166992.1,167277.0] xuntil6(s49) || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 167281[66:Spt:167278.0] || -> trans(s49,s38)*. % 76.16/76.36 167282[66:Res:167281.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s38)*. % 76.16/76.36 167284[66:Res:167281.0,60.0] || -> node2(s49,s38)*. % 76.16/76.36 167285[66:SSi:167282.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s38)*. % 76.16/76.36 167286[66:Res:167284.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 167324[66:SoR:167286.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 167326[66:SoR:167324.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)* xuntil6(s49). % 76.16/76.36 167327[66:SSi:167326.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s38,c_busy)* xuntil6(s49). % 76.16/76.36 167328[67:Spt:167327.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 167330[67:Res:167328.0,61.1] always3(s38) || -> . % 76.16/76.36 167331[67:SSi:167330.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.36 167332[67:Spt:167331.0,167327.1,167328.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.16/76.36 167333[67:Spt:167331.0,167327.0,167327.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 167337[67:MRR:167324.2,167332.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 167338[67:Res:53.1,167333.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 167340[67:MRR:167338.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 167341[67:MRR:167285.0,167340.0] || -> until2p7(s38)*. % 76.16/76.36 167342[67:MRR:236.0,167341.0] || -> until2p7(s39)* node4(s38). % 76.16/76.36 167343[68:Spt:167342.0] || -> until2p7(s39)*. % 76.16/76.36 167344[68:MRR:237.0,167343.0] || -> until2p7(s40)* node4(s39). % 76.16/76.36 167345[69:Spt:167344.0] || -> until2p7(s40)*. % 76.16/76.36 167346[69:MRR:238.0,167345.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 167347[70:Spt:167346.0] || -> until2p7(s41)*. % 76.16/76.36 167348[70:MRR:239.0,167347.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 167349[71:Spt:167348.0] || -> until2p7(s42)*. % 76.16/76.36 167350[71:MRR:240.0,167349.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 167351[72:Spt:167350.0] || -> until2p7(s43)*. % 76.16/76.36 167352[72:MRR:241.0,167351.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 167353[73:Spt:167352.0] || -> until2p7(s44)*. % 76.16/76.36 167354[73:MRR:539.0,167353.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 167355[74:Spt:167354.0] || -> until2p7(s45)*. % 76.16/76.36 167356[74:MRR:544.0,167355.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 167357[75:Spt:167356.0] || -> until2p7(s46)*. % 76.16/76.36 167358[75:MRR:549.0,167357.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 167359[76:Spt:167358.0] || -> until2p7(s47)*. % 76.16/76.36 167360[76:MRR:554.0,167359.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 167361[77:Spt:167360.0] || -> until2p7(s48)*. % 76.16/76.36 167362[77:MRR:559.0,167361.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 167363[78:Spt:167362.0] || -> until2p7(s49)*. % 76.16/76.36 167364[78:MRR:194.0,167363.0] || -> node4(s49)*. % 76.16/76.36 167365[78:MRR:167337.0,167364.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 167369[78:Res:53.1,167365.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 167371[78:MRR:167369.0,78381.0] || -> . % 76.16/76.36 167372[78:Spt:167371.0,167362.0,167363.0] || until2p7(s49)*+ -> . % 76.16/76.36 167373[78:Spt:167371.0,167362.1] || -> node4(s48)*. % 76.16/76.36 167374[78:MRR:78384.0,167373.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 167377[78:Res:53.1,167374.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 167380[78:Res:167377.0,61.1] always3(s48) || -> . % 76.16/76.36 167381[78:SSi:167380.0,78281.0,78387.0,165540.0,167361.0,167373.0] || -> . % 76.16/76.36 167382[77:Spt:167381.0,167360.0,167361.0] || until2p7(s48)*+ -> . % 76.16/76.36 167383[77:Spt:167381.0,167360.1] || -> node4(s47)*. % 76.16/76.36 167385[77:MRR:777.0,167383.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 167397[77:Res:53.1,167385.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 167399[78:Spt:167397.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 167401[78:Res:167399.0,61.1] always3(s47) || -> . % 76.16/76.36 167402[78:SSi:167401.0,78277.0,78280.0,165539.0,167359.0,167383.0] || -> . % 76.16/76.36 167403[78:Spt:167402.0,167397.0,167399.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 167404[78:Spt:167402.0,167397.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 167408[78:Res:167404.0,61.1] always3(s48) || -> . % 76.16/76.36 167409[78:SSi:167408.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 167410[76:Spt:167409.0,167358.0,167359.0] || until2p7(s47)*+ -> . % 76.16/76.36 167411[76:Spt:167409.0,167358.1] || -> node4(s46)*. % 76.16/76.36 167413[76:MRR:780.0,167411.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 167420[76:Res:53.1,167413.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 167425[77:Spt:167420.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 167427[77:Res:167425.0,61.1] always3(s46) || -> . % 76.16/76.36 167428[77:SSi:167427.0,78272.0,78276.0,165538.0,167357.0,167411.0] || -> . % 76.16/76.36 167429[77:Spt:167428.0,167420.0,167425.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 167430[77:Spt:167428.0,167420.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 167434[77:Res:167430.0,61.1] always3(s47) || -> . % 76.16/76.36 167435[77:SSi:167434.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 167436[75:Spt:167435.0,167356.0,167357.0] || until2p7(s46)*+ -> . % 76.16/76.36 167437[75:Spt:167435.0,167356.1] || -> node4(s45)*. % 76.16/76.36 167439[75:MRR:783.0,167437.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 167442[75:Res:53.1,167439.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 167444[76:Spt:167442.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 167446[76:Res:167444.0,61.1] always3(s45) || -> . % 76.16/76.36 167447[76:SSi:167446.0,78268.0,78271.0,165537.0,167355.0,167437.0] || -> . % 76.16/76.36 167448[76:Spt:167447.0,167442.0,167444.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 167449[76:Spt:167447.0,167442.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 167453[76:Res:167449.0,61.1] always3(s46) || -> . % 76.16/76.36 167454[76:SSi:167453.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 167455[74:Spt:167454.0,167354.0,167355.0] || until2p7(s45)*+ -> . % 76.16/76.36 167456[74:Spt:167454.0,167354.1] || -> node4(s44)*. % 76.16/76.36 167458[74:MRR:786.0,167456.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 167461[74:Res:53.1,167458.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 167463[75:Spt:167461.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 167465[75:Res:167463.0,61.1] always3(s44) || -> . % 76.16/76.36 167466[75:SSi:167465.0,78263.0,78267.0,165536.0,167353.0,167456.0] || -> . % 76.16/76.36 167467[75:Spt:167466.0,167461.0,167463.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 167468[75:Spt:167466.0,167461.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 167472[75:Res:167468.0,61.1] always3(s45) || -> . % 76.16/76.36 167473[75:SSi:167472.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 167474[73:Spt:167473.0,167352.0,167353.0] || until2p7(s44)*+ -> . % 76.16/76.36 167475[73:Spt:167473.0,167352.1] || -> node4(s43)*. % 76.16/76.36 167477[73:MRR:789.0,167475.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 167480[73:Res:53.1,167477.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 167482[74:Spt:167480.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 167484[74:Res:167482.0,61.1] always3(s43) || -> . % 76.16/76.36 167485[74:SSi:167484.0,78259.0,78262.0,165535.0,167351.0,167475.0] || -> . % 76.16/76.36 167486[74:Spt:167485.0,167480.0,167482.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 167487[74:Spt:167485.0,167480.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 167491[74:Res:167487.0,61.1] always3(s44) || -> . % 76.16/76.36 167492[74:SSi:167491.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.36 167493[72:Spt:167492.0,167350.0,167351.0] || until2p7(s43)*+ -> . % 76.16/76.36 167494[72:Spt:167492.0,167350.1] || -> node4(s42)*. % 76.16/76.36 167496[72:MRR:792.0,167494.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 167499[72:Res:53.1,167496.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 167504[73:Spt:167499.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 167506[73:Res:167504.0,61.1] always3(s42) || -> . % 76.16/76.36 167507[73:SSi:167506.0,78254.0,78258.0,165534.0,167349.0,167494.0] || -> . % 76.16/76.36 167508[73:Spt:167507.0,167499.0,167504.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 167509[73:Spt:167507.0,167499.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 167513[73:Res:167509.0,61.1] always3(s43) || -> . % 76.16/76.36 167514[73:SSi:167513.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.36 167515[71:Spt:167514.0,167348.0,167349.0] || until2p7(s42)*+ -> . % 76.16/76.36 167516[71:Spt:167514.0,167348.1] || -> node4(s41)*. % 76.16/76.36 167518[71:MRR:795.0,167516.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 167521[71:Res:53.1,167518.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 167523[72:Spt:167521.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 167525[72:Res:167523.0,61.1] always3(s41) || -> . % 76.16/76.36 167526[72:SSi:167525.0,78250.0,78253.0,165533.0,167347.0,167516.0] || -> . % 76.16/76.36 167527[72:Spt:167526.0,167521.0,167523.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 167528[72:Spt:167526.0,167521.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 167532[72:Res:167528.0,61.1] always3(s42) || -> . % 76.16/76.36 167533[72:SSi:167532.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.36 167534[70:Spt:167533.0,167346.0,167347.0] || until2p7(s41)*+ -> . % 76.16/76.36 167535[70:Spt:167533.0,167346.1] || -> node4(s40)*. % 76.16/76.36 167537[70:MRR:798.0,167535.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 167540[70:Res:53.1,167537.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 167542[71:Spt:167540.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 167544[71:Res:167542.0,61.1] always3(s40) || -> . % 76.16/76.36 167545[71:SSi:167544.0,78245.0,78249.0,165532.0,167345.0,167535.0] || -> . % 76.16/76.36 167546[71:Spt:167545.0,167540.0,167542.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.36 167547[71:Spt:167545.0,167540.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 167551[71:Res:167547.0,61.1] always3(s41) || -> . % 76.16/76.36 167552[71:SSi:167551.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.36 167553[69:Spt:167552.0,167344.0,167345.0] || until2p7(s40)*+ -> . % 76.16/76.36 167554[69:Spt:167552.0,167344.1] || -> node4(s39)*. % 76.16/76.36 167556[69:MRR:801.0,167554.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.36 167559[69:Res:53.1,167556.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.36 167561[70:Spt:167559.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 167563[70:Res:167561.0,61.1] always3(s39) || -> . % 76.16/76.36 167564[70:SSi:167563.0,78241.0,78244.0,165531.0,167343.0,167554.0] || -> . % 76.16/76.36 167565[70:Spt:167564.0,167559.0,167561.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.36 167566[70:Spt:167564.0,167559.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 167570[70:Res:167566.0,61.1] always3(s40) || -> . % 76.16/76.36 167571[70:SSi:167570.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.36 167572[68:Spt:167571.0,167342.0,167343.0] || until2p7(s39)*+ -> . % 76.16/76.36 167573[68:Spt:167571.0,167342.1] || -> node4(s38)*. % 76.16/76.36 167575[68:MRR:804.0,167573.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.36 167578[68:Res:53.1,167575.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.36 167580[68:MRR:167578.0,167332.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 167585[68:Res:167580.0,61.1] always3(s39) || -> . % 76.16/76.36 167586[68:SSi:167585.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.36 167587[66:Spt:167586.0,167278.0,167281.0] || trans(s49,s38)*+ -> . % 76.16/76.36 167588[66:Spt:167586.0,167278.1,167278.2,167278.3,167278.4,167278.5,167278.6,167278.7,167278.8,167278.9,167278.10,167278.11,167278.12,167278.13,167278.14,167278.15,167278.16,167278.17,167278.18,167278.19,167278.20,167278.21,167278.22,167278.23,167278.24,167278.25,167278.26,167278.27,167278.28,167278.29,167278.30,167278.31,167278.32,167278.33] || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 167590[66:MRR:167280.1,167587.0] xuntil6(s49) || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 167591[67:Spt:167588.0] || -> trans(s49,s37)*. % 76.16/76.36 167592[67:Res:167591.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s37)*. % 76.16/76.36 167594[67:Res:167591.0,60.0] || -> node2(s49,s37)*. % 76.16/76.36 167595[67:SSi:167592.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s37)*. % 76.16/76.36 167596[67:Res:167594.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 167638[67:SoR:167596.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 167640[67:SoR:167638.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)* xuntil6(s49). % 76.16/76.36 167641[67:SSi:167640.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s37,c_busy)* xuntil6(s49). % 76.16/76.36 167642[68:Spt:167641.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 167644[68:Res:167642.0,61.1] always3(s37) || -> . % 76.16/76.36 167645[68:SSi:167644.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.36 167646[68:Spt:167645.0,167641.1,167642.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.16/76.36 167647[68:Spt:167645.0,167641.0,167641.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 167651[68:MRR:167638.2,167646.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 167652[68:Res:53.1,167647.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 167654[68:MRR:167652.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 167655[68:MRR:167595.0,167654.0] || -> until2p7(s37)*. % 76.16/76.36 167656[68:MRR:235.0,167655.0] || -> until2p7(s38)* node4(s37). % 76.16/76.36 167657[69:Spt:167656.0] || -> until2p7(s38)*. % 76.16/76.36 167658[69:MRR:236.0,167657.0] || -> until2p7(s39)* node4(s38). % 76.16/76.36 167659[70:Spt:167658.0] || -> until2p7(s39)*. % 76.16/76.36 167660[70:MRR:237.0,167659.0] || -> until2p7(s40)* node4(s39). % 76.16/76.36 167661[71:Spt:167660.0] || -> until2p7(s40)*. % 76.16/76.36 167662[71:MRR:238.0,167661.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 167663[72:Spt:167662.0] || -> until2p7(s41)*. % 76.16/76.36 167664[72:MRR:239.0,167663.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 167665[73:Spt:167664.0] || -> until2p7(s42)*. % 76.16/76.36 167666[73:MRR:240.0,167665.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 167667[74:Spt:167666.0] || -> until2p7(s43)*. % 76.16/76.36 167668[74:MRR:241.0,167667.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 167669[75:Spt:167668.0] || -> until2p7(s44)*. % 76.16/76.36 167670[75:MRR:539.0,167669.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 167671[76:Spt:167670.0] || -> until2p7(s45)*. % 76.16/76.36 167672[76:MRR:544.0,167671.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 167673[77:Spt:167672.0] || -> until2p7(s46)*. % 76.16/76.36 167674[77:MRR:549.0,167673.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 167675[78:Spt:167674.0] || -> until2p7(s47)*. % 76.16/76.36 167676[78:MRR:554.0,167675.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 167677[79:Spt:167676.0] || -> until2p7(s48)*. % 76.16/76.36 167678[79:MRR:559.0,167677.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 167679[80:Spt:167678.0] || -> until2p7(s49)*. % 76.16/76.36 167680[80:MRR:194.0,167679.0] || -> node4(s49)*. % 76.16/76.36 167681[80:MRR:167651.0,167680.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 167682[80:Res:53.1,167681.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 167684[80:MRR:167682.0,78381.0] || -> . % 76.16/76.36 167685[80:Spt:167684.0,167678.0,167679.0] || until2p7(s49)*+ -> . % 76.16/76.36 167686[80:Spt:167684.0,167678.1] || -> node4(s48)*. % 76.16/76.36 167687[80:MRR:78384.0,167686.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 167690[80:Res:53.1,167687.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 167693[80:Res:167690.0,61.1] always3(s48) || -> . % 76.16/76.36 167694[80:SSi:167693.0,78281.0,78387.0,165540.0,167677.0,167686.0] || -> . % 76.16/76.36 167695[79:Spt:167694.0,167676.0,167677.0] || until2p7(s48)*+ -> . % 76.16/76.36 167696[79:Spt:167694.0,167676.1] || -> node4(s47)*. % 76.16/76.36 167698[79:MRR:777.0,167696.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 167713[79:Res:53.1,167698.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 167718[80:Spt:167713.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 167720[80:Res:167718.0,61.1] always3(s47) || -> . % 76.16/76.36 167721[80:SSi:167720.0,78277.0,78280.0,165539.0,167675.0,167696.0] || -> . % 76.16/76.36 167722[80:Spt:167721.0,167713.0,167718.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 167723[80:Spt:167721.0,167713.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 167727[80:Res:167723.0,61.1] always3(s48) || -> . % 76.16/76.36 167728[80:SSi:167727.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 167729[78:Spt:167728.0,167674.0,167675.0] || until2p7(s47)*+ -> . % 76.16/76.36 167730[78:Spt:167728.0,167674.1] || -> node4(s46)*. % 76.16/76.36 167732[78:MRR:780.0,167730.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 167739[78:Res:53.1,167732.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 167741[79:Spt:167739.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 167743[79:Res:167741.0,61.1] always3(s46) || -> . % 76.16/76.36 167744[79:SSi:167743.0,78272.0,78276.0,165538.0,167673.0,167730.0] || -> . % 76.16/76.36 167745[79:Spt:167744.0,167739.0,167741.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 167746[79:Spt:167744.0,167739.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 167750[79:Res:167746.0,61.1] always3(s47) || -> . % 76.16/76.36 167751[79:SSi:167750.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 167752[77:Spt:167751.0,167672.0,167673.0] || until2p7(s46)*+ -> . % 76.16/76.36 167753[77:Spt:167751.0,167672.1] || -> node4(s45)*. % 76.16/76.36 167755[77:MRR:783.0,167753.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 167758[77:Res:53.1,167755.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 167763[78:Spt:167758.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 167765[78:Res:167763.0,61.1] always3(s45) || -> . % 76.16/76.36 167766[78:SSi:167765.0,78268.0,78271.0,165537.0,167671.0,167753.0] || -> . % 76.16/76.36 167767[78:Spt:167766.0,167758.0,167763.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 167768[78:Spt:167766.0,167758.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 167772[78:Res:167768.0,61.1] always3(s46) || -> . % 76.16/76.36 167773[78:SSi:167772.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 167774[76:Spt:167773.0,167670.0,167671.0] || until2p7(s45)*+ -> . % 76.16/76.36 167775[76:Spt:167773.0,167670.1] || -> node4(s44)*. % 76.16/76.36 167777[76:MRR:786.0,167775.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 167780[76:Res:53.1,167777.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 167782[77:Spt:167780.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 167784[77:Res:167782.0,61.1] always3(s44) || -> . % 76.16/76.36 167785[77:SSi:167784.0,78263.0,78267.0,165536.0,167669.0,167775.0] || -> . % 76.16/76.36 167786[77:Spt:167785.0,167780.0,167782.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 167787[77:Spt:167785.0,167780.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 167791[77:Res:167787.0,61.1] always3(s45) || -> . % 76.16/76.36 167792[77:SSi:167791.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 167793[75:Spt:167792.0,167668.0,167669.0] || until2p7(s44)*+ -> . % 76.16/76.36 167794[75:Spt:167792.0,167668.1] || -> node4(s43)*. % 76.16/76.36 167796[75:MRR:789.0,167794.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 167799[75:Res:53.1,167796.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 167801[76:Spt:167799.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 167803[76:Res:167801.0,61.1] always3(s43) || -> . % 76.16/76.36 167804[76:SSi:167803.0,78259.0,78262.0,165535.0,167667.0,167794.0] || -> . % 76.16/76.36 167805[76:Spt:167804.0,167799.0,167801.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 167806[76:Spt:167804.0,167799.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 167810[76:Res:167806.0,61.1] always3(s44) || -> . % 76.16/76.36 167811[76:SSi:167810.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.36 167812[74:Spt:167811.0,167666.0,167667.0] || until2p7(s43)*+ -> . % 76.16/76.36 167813[74:Spt:167811.0,167666.1] || -> node4(s42)*. % 76.16/76.36 167815[74:MRR:792.0,167813.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 167818[74:Res:53.1,167815.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 167820[75:Spt:167818.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 167822[75:Res:167820.0,61.1] always3(s42) || -> . % 76.16/76.36 167823[75:SSi:167822.0,78254.0,78258.0,165534.0,167665.0,167813.0] || -> . % 76.16/76.36 167824[75:Spt:167823.0,167818.0,167820.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 167825[75:Spt:167823.0,167818.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 167829[75:Res:167825.0,61.1] always3(s43) || -> . % 76.16/76.36 167830[75:SSi:167829.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.36 167831[73:Spt:167830.0,167664.0,167665.0] || until2p7(s42)*+ -> . % 76.16/76.36 167832[73:Spt:167830.0,167664.1] || -> node4(s41)*. % 76.16/76.36 167834[73:MRR:795.0,167832.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 167837[73:Res:53.1,167834.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 167842[74:Spt:167837.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 167844[74:Res:167842.0,61.1] always3(s41) || -> . % 76.16/76.36 167845[74:SSi:167844.0,78250.0,78253.0,165533.0,167663.0,167832.0] || -> . % 76.16/76.36 167846[74:Spt:167845.0,167837.0,167842.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 167847[74:Spt:167845.0,167837.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 167851[74:Res:167847.0,61.1] always3(s42) || -> . % 76.16/76.36 167852[74:SSi:167851.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.36 167853[72:Spt:167852.0,167662.0,167663.0] || until2p7(s41)*+ -> . % 76.16/76.36 167854[72:Spt:167852.0,167662.1] || -> node4(s40)*. % 76.16/76.36 167856[72:MRR:798.0,167854.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 167859[72:Res:53.1,167856.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 167861[73:Spt:167859.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 167863[73:Res:167861.0,61.1] always3(s40) || -> . % 76.16/76.36 167864[73:SSi:167863.0,78245.0,78249.0,165532.0,167661.0,167854.0] || -> . % 76.16/76.36 167865[73:Spt:167864.0,167859.0,167861.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.36 167866[73:Spt:167864.0,167859.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 167870[73:Res:167866.0,61.1] always3(s41) || -> . % 76.16/76.36 167871[73:SSi:167870.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.36 167872[71:Spt:167871.0,167660.0,167661.0] || until2p7(s40)*+ -> . % 76.16/76.36 167873[71:Spt:167871.0,167660.1] || -> node4(s39)*. % 76.16/76.36 167875[71:MRR:801.0,167873.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.36 167878[71:Res:53.1,167875.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.36 167880[72:Spt:167878.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 167882[72:Res:167880.0,61.1] always3(s39) || -> . % 76.16/76.36 167883[72:SSi:167882.0,78241.0,78244.0,165531.0,167659.0,167873.0] || -> . % 76.16/76.36 167884[72:Spt:167883.0,167878.0,167880.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.36 167885[72:Spt:167883.0,167878.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 167889[72:Res:167885.0,61.1] always3(s40) || -> . % 76.16/76.36 167890[72:SSi:167889.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.36 167891[70:Spt:167890.0,167658.0,167659.0] || until2p7(s39)*+ -> . % 76.16/76.36 167892[70:Spt:167890.0,167658.1] || -> node4(s38)*. % 76.16/76.36 167894[70:MRR:804.0,167892.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.36 167897[70:Res:53.1,167894.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.36 167899[71:Spt:167897.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 167901[71:Res:167899.0,61.1] always3(s38) || -> . % 76.16/76.36 167902[71:SSi:167901.0,78236.0,78240.0,165530.0,167657.0,167892.0] || -> . % 76.16/76.36 167903[71:Spt:167902.0,167897.0,167899.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.36 167904[71:Spt:167902.0,167897.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 167908[71:Res:167904.0,61.1] always3(s39) || -> . % 76.16/76.36 167909[71:SSi:167908.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.36 167910[69:Spt:167909.0,167656.0,167657.0] || until2p7(s38)*+ -> . % 76.16/76.36 167911[69:Spt:167909.0,167656.1] || -> node4(s37)*. % 76.16/76.36 167913[69:MRR:807.0,167911.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.36 167916[69:Res:53.1,167913.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.36 167918[69:MRR:167916.0,167646.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 167923[69:Res:167918.0,61.1] always3(s38) || -> . % 76.16/76.36 167924[69:SSi:167923.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.36 167925[67:Spt:167924.0,167588.0,167591.0] || trans(s49,s37)*+ -> . % 76.16/76.36 167926[67:Spt:167924.0,167588.1,167588.2,167588.3,167588.4,167588.5,167588.6,167588.7,167588.8,167588.9,167588.10,167588.11,167588.12,167588.13,167588.14,167588.15,167588.16,167588.17,167588.18,167588.19,167588.20,167588.21,167588.22,167588.23,167588.24,167588.25,167588.26,167588.27,167588.28,167588.29,167588.30,167588.31,167588.32] || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 167928[67:MRR:167590.1,167925.0] xuntil6(s49) || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 167929[68:Spt:167926.0] || -> trans(s49,s36)*. % 76.16/76.36 167930[68:Res:167929.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s36)*. % 76.16/76.36 167932[68:Res:167929.0,60.0] || -> node2(s49,s36)*. % 76.16/76.36 167933[68:SSi:167930.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s36)*. % 76.16/76.36 167934[68:Res:167932.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 167977[68:SoR:167934.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 167979[68:SoR:167977.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)* xuntil6(s49). % 76.16/76.36 167980[68:SSi:167979.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s36,c_busy)* xuntil6(s49). % 76.16/76.36 167981[69:Spt:167980.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 167983[69:Res:167981.0,61.1] always3(s36) || -> . % 76.16/76.36 167984[69:SSi:167983.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.36 167985[69:Spt:167984.0,167980.1,167981.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.16/76.36 167986[69:Spt:167984.0,167980.0,167980.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 167990[69:MRR:167977.2,167985.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 167991[69:Res:53.1,167986.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 167993[69:MRR:167991.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 167994[69:MRR:167933.0,167993.0] || -> until2p7(s36)*. % 76.16/76.36 167995[69:MRR:232.0,167994.0] || -> until2p7(s37)* node4(s36). % 76.16/76.36 167996[70:Spt:167995.0] || -> until2p7(s37)*. % 76.16/76.36 167997[70:MRR:235.0,167996.0] || -> until2p7(s38)* node4(s37). % 76.16/76.36 167998[71:Spt:167997.0] || -> until2p7(s38)*. % 76.16/76.36 167999[71:MRR:236.0,167998.0] || -> until2p7(s39)* node4(s38). % 76.16/76.36 168000[72:Spt:167999.0] || -> until2p7(s39)*. % 76.16/76.36 168001[72:MRR:237.0,168000.0] || -> until2p7(s40)* node4(s39). % 76.16/76.36 168002[73:Spt:168001.0] || -> until2p7(s40)*. % 76.16/76.36 168003[73:MRR:238.0,168002.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 168004[74:Spt:168003.0] || -> until2p7(s41)*. % 76.16/76.36 168005[74:MRR:239.0,168004.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 168006[75:Spt:168005.0] || -> until2p7(s42)*. % 76.16/76.36 168007[75:MRR:240.0,168006.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 168008[76:Spt:168007.0] || -> until2p7(s43)*. % 76.16/76.36 168009[76:MRR:241.0,168008.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 168010[77:Spt:168009.0] || -> until2p7(s44)*. % 76.16/76.36 168011[77:MRR:539.0,168010.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 168012[78:Spt:168011.0] || -> until2p7(s45)*. % 76.16/76.36 168013[78:MRR:544.0,168012.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 168014[79:Spt:168013.0] || -> until2p7(s46)*. % 76.16/76.36 168015[79:MRR:549.0,168014.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 168016[80:Spt:168015.0] || -> until2p7(s47)*. % 76.16/76.36 168017[80:MRR:554.0,168016.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 168018[81:Spt:168017.0] || -> until2p7(s48)*. % 76.16/76.36 168019[81:MRR:559.0,168018.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 168020[82:Spt:168019.0] || -> until2p7(s49)*. % 76.16/76.36 168021[82:MRR:194.0,168020.0] || -> node4(s49)*. % 76.16/76.36 168022[82:MRR:167990.0,168021.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 168026[82:Res:53.1,168022.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 168028[82:MRR:168026.0,78381.0] || -> . % 76.16/76.36 168029[82:Spt:168028.0,168019.0,168020.0] || until2p7(s49)*+ -> . % 76.16/76.36 168030[82:Spt:168028.0,168019.1] || -> node4(s48)*. % 76.16/76.36 168031[82:MRR:78384.0,168030.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 168034[82:Res:53.1,168031.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 168037[82:Res:168034.0,61.1] always3(s48) || -> . % 76.16/76.36 168038[82:SSi:168037.0,78281.0,78387.0,165540.0,168018.0,168030.0] || -> . % 76.16/76.36 168039[81:Spt:168038.0,168017.0,168018.0] || until2p7(s48)*+ -> . % 76.16/76.36 168040[81:Spt:168038.0,168017.1] || -> node4(s47)*. % 76.16/76.36 168042[81:MRR:777.0,168040.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 168054[81:Res:53.1,168042.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 168056[82:Spt:168054.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 168058[82:Res:168056.0,61.1] always3(s47) || -> . % 76.16/76.36 168059[82:SSi:168058.0,78277.0,78280.0,165539.0,168016.0,168040.0] || -> . % 76.16/76.36 168060[82:Spt:168059.0,168054.0,168056.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 168061[82:Spt:168059.0,168054.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 168065[82:Res:168061.0,61.1] always3(s48) || -> . % 76.16/76.36 168066[82:SSi:168065.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 168067[80:Spt:168066.0,168015.0,168016.0] || until2p7(s47)*+ -> . % 76.16/76.36 168068[80:Spt:168066.0,168015.1] || -> node4(s46)*. % 76.16/76.36 168070[80:MRR:780.0,168068.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 168077[80:Res:53.1,168070.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 168082[81:Spt:168077.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 168084[81:Res:168082.0,61.1] always3(s46) || -> . % 76.16/76.36 168085[81:SSi:168084.0,78272.0,78276.0,165538.0,168014.0,168068.0] || -> . % 76.16/76.36 168086[81:Spt:168085.0,168077.0,168082.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 168087[81:Spt:168085.0,168077.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 168091[81:Res:168087.0,61.1] always3(s47) || -> . % 76.16/76.36 168092[81:SSi:168091.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 168093[79:Spt:168092.0,168013.0,168014.0] || until2p7(s46)*+ -> . % 76.16/76.36 168094[79:Spt:168092.0,168013.1] || -> node4(s45)*. % 76.16/76.36 168096[79:MRR:783.0,168094.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 168099[79:Res:53.1,168096.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 168101[80:Spt:168099.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 168103[80:Res:168101.0,61.1] always3(s45) || -> . % 76.16/76.36 168104[80:SSi:168103.0,78268.0,78271.0,165537.0,168012.0,168094.0] || -> . % 76.16/76.36 168105[80:Spt:168104.0,168099.0,168101.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 168106[80:Spt:168104.0,168099.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 168110[80:Res:168106.0,61.1] always3(s46) || -> . % 76.16/76.36 168111[80:SSi:168110.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 168112[78:Spt:168111.0,168011.0,168012.0] || until2p7(s45)*+ -> . % 76.16/76.36 168113[78:Spt:168111.0,168011.1] || -> node4(s44)*. % 76.16/76.36 168115[78:MRR:786.0,168113.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 168118[78:Res:53.1,168115.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 168120[79:Spt:168118.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 168122[79:Res:168120.0,61.1] always3(s44) || -> . % 76.16/76.36 168123[79:SSi:168122.0,78263.0,78267.0,165536.0,168010.0,168113.0] || -> . % 76.16/76.36 168124[79:Spt:168123.0,168118.0,168120.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 168125[79:Spt:168123.0,168118.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 168129[79:Res:168125.0,61.1] always3(s45) || -> . % 76.16/76.36 168130[79:SSi:168129.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 168131[77:Spt:168130.0,168009.0,168010.0] || until2p7(s44)*+ -> . % 76.16/76.36 168132[77:Spt:168130.0,168009.1] || -> node4(s43)*. % 76.16/76.36 168134[77:MRR:789.0,168132.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 168137[77:Res:53.1,168134.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 168139[78:Spt:168137.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 168141[78:Res:168139.0,61.1] always3(s43) || -> . % 76.16/76.36 168142[78:SSi:168141.0,78259.0,78262.0,165535.0,168008.0,168132.0] || -> . % 76.16/76.36 168143[78:Spt:168142.0,168137.0,168139.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 168144[78:Spt:168142.0,168137.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 168148[78:Res:168144.0,61.1] always3(s44) || -> . % 76.16/76.36 168149[78:SSi:168148.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.36 168150[76:Spt:168149.0,168007.0,168008.0] || until2p7(s43)*+ -> . % 76.16/76.36 168151[76:Spt:168149.0,168007.1] || -> node4(s42)*. % 76.16/76.36 168153[76:MRR:792.0,168151.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 168156[76:Res:53.1,168153.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 168161[77:Spt:168156.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 168163[77:Res:168161.0,61.1] always3(s42) || -> . % 76.16/76.36 168164[77:SSi:168163.0,78254.0,78258.0,165534.0,168006.0,168151.0] || -> . % 76.16/76.36 168165[77:Spt:168164.0,168156.0,168161.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 168166[77:Spt:168164.0,168156.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 168170[77:Res:168166.0,61.1] always3(s43) || -> . % 76.16/76.36 168171[77:SSi:168170.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.36 168172[75:Spt:168171.0,168005.0,168006.0] || until2p7(s42)*+ -> . % 76.16/76.36 168173[75:Spt:168171.0,168005.1] || -> node4(s41)*. % 76.16/76.36 168175[75:MRR:795.0,168173.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 168178[75:Res:53.1,168175.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 168180[76:Spt:168178.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 168182[76:Res:168180.0,61.1] always3(s41) || -> . % 76.16/76.36 168183[76:SSi:168182.0,78250.0,78253.0,165533.0,168004.0,168173.0] || -> . % 76.16/76.36 168184[76:Spt:168183.0,168178.0,168180.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 168185[76:Spt:168183.0,168178.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 168189[76:Res:168185.0,61.1] always3(s42) || -> . % 76.16/76.36 168190[76:SSi:168189.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.36 168191[74:Spt:168190.0,168003.0,168004.0] || until2p7(s41)*+ -> . % 76.16/76.36 168192[74:Spt:168190.0,168003.1] || -> node4(s40)*. % 76.16/76.36 168194[74:MRR:798.0,168192.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 168197[74:Res:53.1,168194.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 168199[75:Spt:168197.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 168201[75:Res:168199.0,61.1] always3(s40) || -> . % 76.16/76.36 168202[75:SSi:168201.0,78245.0,78249.0,165532.0,168002.0,168192.0] || -> . % 76.16/76.36 168203[75:Spt:168202.0,168197.0,168199.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.36 168204[75:Spt:168202.0,168197.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 168208[75:Res:168204.0,61.1] always3(s41) || -> . % 76.16/76.36 168209[75:SSi:168208.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.36 168210[73:Spt:168209.0,168001.0,168002.0] || until2p7(s40)*+ -> . % 76.16/76.36 168211[73:Spt:168209.0,168001.1] || -> node4(s39)*. % 76.16/76.36 168213[73:MRR:801.0,168211.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.36 168216[73:Res:53.1,168213.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.36 168218[74:Spt:168216.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 168220[74:Res:168218.0,61.1] always3(s39) || -> . % 76.16/76.36 168221[74:SSi:168220.0,78241.0,78244.0,165531.0,168000.0,168211.0] || -> . % 76.16/76.36 168222[74:Spt:168221.0,168216.0,168218.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.36 168223[74:Spt:168221.0,168216.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 168227[74:Res:168223.0,61.1] always3(s40) || -> . % 76.16/76.36 168228[74:SSi:168227.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.36 168229[72:Spt:168228.0,167999.0,168000.0] || until2p7(s39)*+ -> . % 76.16/76.36 168230[72:Spt:168228.0,167999.1] || -> node4(s38)*. % 76.16/76.36 168232[72:MRR:804.0,168230.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.36 168235[72:Res:53.1,168232.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.36 168240[73:Spt:168235.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 168242[73:Res:168240.0,61.1] always3(s38) || -> . % 76.16/76.36 168243[73:SSi:168242.0,78236.0,78240.0,165530.0,167998.0,168230.0] || -> . % 76.16/76.36 168244[73:Spt:168243.0,168235.0,168240.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.36 168245[73:Spt:168243.0,168235.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 168249[73:Res:168245.0,61.1] always3(s39) || -> . % 76.16/76.36 168250[73:SSi:168249.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.36 168251[71:Spt:168250.0,167997.0,167998.0] || until2p7(s38)*+ -> . % 76.16/76.36 168252[71:Spt:168250.0,167997.1] || -> node4(s37)*. % 76.16/76.36 168254[71:MRR:807.0,168252.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.36 168257[71:Res:53.1,168254.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.36 168259[72:Spt:168257.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 168261[72:Res:168259.0,61.1] always3(s37) || -> . % 76.16/76.36 168262[72:SSi:168261.0,78232.0,78235.0,165529.0,167996.0,168252.0] || -> . % 76.16/76.36 168263[72:Spt:168262.0,168257.0,168259.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.36 168264[72:Spt:168262.0,168257.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 168268[72:Res:168264.0,61.1] always3(s38) || -> . % 76.16/76.36 168269[72:SSi:168268.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.36 168270[70:Spt:168269.0,167995.0,167996.0] || until2p7(s37)*+ -> . % 76.16/76.36 168271[70:Spt:168269.0,167995.1] || -> node4(s36)*. % 76.16/76.36 168273[70:MRR:810.0,168271.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.36 168276[70:Res:53.1,168273.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.36 168278[70:MRR:168276.0,167985.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 168280[70:Res:168278.0,61.1] always3(s37) || -> . % 76.16/76.36 168281[70:SSi:168280.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.36 168282[68:Spt:168281.0,167926.0,167929.0] || trans(s49,s36)*+ -> . % 76.16/76.36 168283[68:Spt:168281.0,167926.1,167926.2,167926.3,167926.4,167926.5,167926.6,167926.7,167926.8,167926.9,167926.10,167926.11,167926.12,167926.13,167926.14,167926.15,167926.16,167926.17,167926.18,167926.19,167926.20,167926.21,167926.22,167926.23,167926.24,167926.25,167926.26,167926.27,167926.28,167926.29,167926.30,167926.31] || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 168285[68:MRR:167928.1,168282.0] xuntil6(s49) || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 168286[69:Spt:168283.0] || -> trans(s49,s35)*. % 76.16/76.36 168287[69:Res:168286.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s35)*. % 76.16/76.36 168289[69:Res:168286.0,60.0] || -> node2(s49,s35)*. % 76.16/76.36 168290[69:SSi:168287.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s35)*. % 76.16/76.36 168291[69:Res:168289.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 168341[69:SoR:168291.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 168343[69:SoR:168341.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 76.16/76.36 168344[69:SSi:168343.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 76.16/76.36 168345[70:Spt:168344.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 168347[70:Res:168345.0,61.1] always3(s35) || -> . % 76.16/76.36 168348[70:SSi:168347.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.36 168349[70:Spt:168348.0,168344.1,168345.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.16/76.36 168350[70:Spt:168348.0,168344.0,168344.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 168354[70:MRR:168341.2,168349.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 168355[70:Res:53.1,168350.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 168357[70:MRR:168355.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 168358[70:MRR:168290.0,168357.0] || -> until2p7(s35)*. % 76.16/76.36 168359[70:MRR:231.0,168358.0] || -> until2p7(s36)* node4(s35). % 76.16/76.36 168360[71:Spt:168359.0] || -> until2p7(s36)*. % 76.16/76.36 168361[71:MRR:232.0,168360.0] || -> until2p7(s37)* node4(s36). % 76.16/76.36 168362[72:Spt:168361.0] || -> until2p7(s37)*. % 76.16/76.36 168363[72:MRR:235.0,168362.0] || -> until2p7(s38)* node4(s37). % 76.16/76.36 168364[73:Spt:168363.0] || -> until2p7(s38)*. % 76.16/76.36 168365[73:MRR:236.0,168364.0] || -> until2p7(s39)* node4(s38). % 76.16/76.36 168366[74:Spt:168365.0] || -> until2p7(s39)*. % 76.16/76.36 168367[74:MRR:237.0,168366.0] || -> until2p7(s40)* node4(s39). % 76.16/76.36 168368[75:Spt:168367.0] || -> until2p7(s40)*. % 76.16/76.36 168369[75:MRR:238.0,168368.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 168370[76:Spt:168369.0] || -> until2p7(s41)*. % 76.16/76.36 168371[76:MRR:239.0,168370.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 168372[77:Spt:168371.0] || -> until2p7(s42)*. % 76.16/76.36 168373[77:MRR:240.0,168372.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 168374[78:Spt:168373.0] || -> until2p7(s43)*. % 76.16/76.36 168375[78:MRR:241.0,168374.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 168376[79:Spt:168375.0] || -> until2p7(s44)*. % 76.16/76.36 168377[79:MRR:539.0,168376.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 168378[80:Spt:168377.0] || -> until2p7(s45)*. % 76.16/76.36 168379[80:MRR:544.0,168378.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 168380[81:Spt:168379.0] || -> until2p7(s46)*. % 76.16/76.36 168381[81:MRR:549.0,168380.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 168382[82:Spt:168381.0] || -> until2p7(s47)*. % 76.16/76.36 168383[82:MRR:554.0,168382.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 168384[83:Spt:168383.0] || -> until2p7(s48)*. % 76.16/76.36 168385[83:MRR:559.0,168384.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 168386[84:Spt:168385.0] || -> until2p7(s49)*. % 76.16/76.36 168387[84:MRR:194.0,168386.0] || -> node4(s49)*. % 76.16/76.36 168388[84:MRR:168354.0,168387.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 168389[84:Res:53.1,168388.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 168391[84:MRR:168389.0,78381.0] || -> . % 76.16/76.36 168392[84:Spt:168391.0,168385.0,168386.0] || until2p7(s49)*+ -> . % 76.16/76.36 168393[84:Spt:168391.0,168385.1] || -> node4(s48)*. % 76.16/76.36 168394[84:MRR:78384.0,168393.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 168397[84:Res:53.1,168394.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 168400[84:Res:168397.0,61.1] always3(s48) || -> . % 76.16/76.36 168401[84:SSi:168400.0,78281.0,78387.0,165540.0,168384.0,168393.0] || -> . % 76.16/76.36 168402[83:Spt:168401.0,168383.0,168384.0] || until2p7(s48)*+ -> . % 76.16/76.36 168403[83:Spt:168401.0,168383.1] || -> node4(s47)*. % 76.16/76.36 168405[83:MRR:777.0,168403.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 168420[83:Res:53.1,168405.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 168422[84:Spt:168420.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 168424[84:Res:168422.0,61.1] always3(s47) || -> . % 76.16/76.36 168425[84:SSi:168424.0,78277.0,78280.0,165539.0,168382.0,168403.0] || -> . % 76.16/76.36 168426[84:Spt:168425.0,168420.0,168422.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 168427[84:Spt:168425.0,168420.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 168431[84:Res:168427.0,61.1] always3(s48) || -> . % 76.16/76.36 168432[84:SSi:168431.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 168433[82:Spt:168432.0,168381.0,168382.0] || until2p7(s47)*+ -> . % 76.16/76.36 168434[82:Spt:168432.0,168381.1] || -> node4(s46)*. % 76.16/76.36 168436[82:MRR:780.0,168434.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 168446[82:Res:53.1,168436.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 168448[83:Spt:168446.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 168450[83:Res:168448.0,61.1] always3(s46) || -> . % 76.16/76.36 168451[83:SSi:168450.0,78272.0,78276.0,165538.0,168380.0,168434.0] || -> . % 76.16/76.36 168452[83:Spt:168451.0,168446.0,168448.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 168453[83:Spt:168451.0,168446.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 168457[83:Res:168453.0,61.1] always3(s47) || -> . % 76.16/76.36 168458[83:SSi:168457.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 168459[81:Spt:168458.0,168379.0,168380.0] || until2p7(s46)*+ -> . % 76.16/76.36 168460[81:Spt:168458.0,168379.1] || -> node4(s45)*. % 76.16/76.36 168462[81:MRR:783.0,168460.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 168465[81:Res:53.1,168462.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 168467[82:Spt:168465.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 168469[82:Res:168467.0,61.1] always3(s45) || -> . % 76.16/76.36 168470[82:SSi:168469.0,78268.0,78271.0,165537.0,168378.0,168460.0] || -> . % 76.16/76.36 168471[82:Spt:168470.0,168465.0,168467.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 168472[82:Spt:168470.0,168465.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 168476[82:Res:168472.0,61.1] always3(s46) || -> . % 76.16/76.36 168477[82:SSi:168476.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 168478[80:Spt:168477.0,168377.0,168378.0] || until2p7(s45)*+ -> . % 76.16/76.36 168479[80:Spt:168477.0,168377.1] || -> node4(s44)*. % 76.16/76.36 168481[80:MRR:786.0,168479.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 168484[80:Res:53.1,168481.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 168486[81:Spt:168484.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 168488[81:Res:168486.0,61.1] always3(s44) || -> . % 76.16/76.36 168489[81:SSi:168488.0,78263.0,78267.0,165536.0,168376.0,168479.0] || -> . % 76.16/76.36 168490[81:Spt:168489.0,168484.0,168486.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 168491[81:Spt:168489.0,168484.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 168495[81:Res:168491.0,61.1] always3(s45) || -> . % 76.16/76.36 168496[81:SSi:168495.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 168497[79:Spt:168496.0,168375.0,168376.0] || until2p7(s44)*+ -> . % 76.16/76.36 168498[79:Spt:168496.0,168375.1] || -> node4(s43)*. % 76.16/76.36 168500[79:MRR:789.0,168498.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 168503[79:Res:53.1,168500.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 168508[80:Spt:168503.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 168510[80:Res:168508.0,61.1] always3(s43) || -> . % 76.16/76.36 168511[80:SSi:168510.0,78259.0,78262.0,165535.0,168374.0,168498.0] || -> . % 76.16/76.36 168512[80:Spt:168511.0,168503.0,168508.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 168513[80:Spt:168511.0,168503.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 168517[80:Res:168513.0,61.1] always3(s44) || -> . % 76.16/76.36 168518[80:SSi:168517.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.36 168519[78:Spt:168518.0,168373.0,168374.0] || until2p7(s43)*+ -> . % 76.16/76.36 168520[78:Spt:168518.0,168373.1] || -> node4(s42)*. % 76.16/76.36 168522[78:MRR:792.0,168520.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 168525[78:Res:53.1,168522.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 168527[79:Spt:168525.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 168529[79:Res:168527.0,61.1] always3(s42) || -> . % 76.16/76.36 168530[79:SSi:168529.0,78254.0,78258.0,165534.0,168372.0,168520.0] || -> . % 76.16/76.36 168531[79:Spt:168530.0,168525.0,168527.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 168532[79:Spt:168530.0,168525.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 168536[79:Res:168532.0,61.1] always3(s43) || -> . % 76.16/76.36 168537[79:SSi:168536.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.36 168538[77:Spt:168537.0,168371.0,168372.0] || until2p7(s42)*+ -> . % 76.16/76.36 168539[77:Spt:168537.0,168371.1] || -> node4(s41)*. % 76.16/76.36 168541[77:MRR:795.0,168539.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 168544[77:Res:53.1,168541.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 168546[78:Spt:168544.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 168548[78:Res:168546.0,61.1] always3(s41) || -> . % 76.16/76.36 168549[78:SSi:168548.0,78250.0,78253.0,165533.0,168370.0,168539.0] || -> . % 76.16/76.36 168550[78:Spt:168549.0,168544.0,168546.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 168551[78:Spt:168549.0,168544.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 168555[78:Res:168551.0,61.1] always3(s42) || -> . % 76.16/76.36 168556[78:SSi:168555.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.36 168557[76:Spt:168556.0,168369.0,168370.0] || until2p7(s41)*+ -> . % 76.16/76.36 168558[76:Spt:168556.0,168369.1] || -> node4(s40)*. % 76.16/76.36 168560[76:MRR:798.0,168558.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 168563[76:Res:53.1,168560.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 168565[77:Spt:168563.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 168567[77:Res:168565.0,61.1] always3(s40) || -> . % 76.16/76.36 168568[77:SSi:168567.0,78245.0,78249.0,165532.0,168368.0,168558.0] || -> . % 76.16/76.36 168569[77:Spt:168568.0,168563.0,168565.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.36 168570[77:Spt:168568.0,168563.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 168574[77:Res:168570.0,61.1] always3(s41) || -> . % 76.16/76.36 168575[77:SSi:168574.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.36 168576[75:Spt:168575.0,168367.0,168368.0] || until2p7(s40)*+ -> . % 76.16/76.36 168577[75:Spt:168575.0,168367.1] || -> node4(s39)*. % 76.16/76.36 168579[75:MRR:801.0,168577.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.36 168582[75:Res:53.1,168579.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.36 168587[76:Spt:168582.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 168589[76:Res:168587.0,61.1] always3(s39) || -> . % 76.16/76.36 168590[76:SSi:168589.0,78241.0,78244.0,165531.0,168366.0,168577.0] || -> . % 76.16/76.36 168591[76:Spt:168590.0,168582.0,168587.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.36 168592[76:Spt:168590.0,168582.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 168596[76:Res:168592.0,61.1] always3(s40) || -> . % 76.16/76.36 168597[76:SSi:168596.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.36 168598[74:Spt:168597.0,168365.0,168366.0] || until2p7(s39)*+ -> . % 76.16/76.36 168599[74:Spt:168597.0,168365.1] || -> node4(s38)*. % 76.16/76.36 168601[74:MRR:804.0,168599.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.36 168604[74:Res:53.1,168601.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.36 168606[75:Spt:168604.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 168608[75:Res:168606.0,61.1] always3(s38) || -> . % 76.16/76.36 168609[75:SSi:168608.0,78236.0,78240.0,165530.0,168364.0,168599.0] || -> . % 76.16/76.36 168610[75:Spt:168609.0,168604.0,168606.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.36 168611[75:Spt:168609.0,168604.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 168615[75:Res:168611.0,61.1] always3(s39) || -> . % 76.16/76.36 168616[75:SSi:168615.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.36 168617[73:Spt:168616.0,168363.0,168364.0] || until2p7(s38)*+ -> . % 76.16/76.36 168618[73:Spt:168616.0,168363.1] || -> node4(s37)*. % 76.16/76.36 168620[73:MRR:807.0,168618.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.36 168623[73:Res:53.1,168620.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.36 168625[74:Spt:168623.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 168627[74:Res:168625.0,61.1] always3(s37) || -> . % 76.16/76.36 168628[74:SSi:168627.0,78232.0,78235.0,165529.0,168362.0,168618.0] || -> . % 76.16/76.36 168629[74:Spt:168628.0,168623.0,168625.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.36 168630[74:Spt:168628.0,168623.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 168634[74:Res:168630.0,61.1] always3(s38) || -> . % 76.16/76.36 168635[74:SSi:168634.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.36 168636[72:Spt:168635.0,168361.0,168362.0] || until2p7(s37)*+ -> . % 76.16/76.36 168637[72:Spt:168635.0,168361.1] || -> node4(s36)*. % 76.16/76.36 168639[72:MRR:810.0,168637.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.36 168642[72:Res:53.1,168639.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.36 168644[73:Spt:168642.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 168646[73:Res:168644.0,61.1] always3(s36) || -> . % 76.16/76.36 168647[73:SSi:168646.0,78227.0,78231.0,165528.0,168360.0,168637.0] || -> . % 76.16/76.36 168648[73:Spt:168647.0,168642.0,168644.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.36 168649[73:Spt:168647.0,168642.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 168653[73:Res:168649.0,61.1] always3(s37) || -> . % 76.16/76.36 168654[73:SSi:168653.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.36 168655[71:Spt:168654.0,168359.0,168360.0] || until2p7(s36)*+ -> . % 76.16/76.36 168656[71:Spt:168654.0,168359.1] || -> node4(s35)*. % 76.16/76.36 168658[71:MRR:813.0,168656.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.36 168661[71:Res:53.1,168658.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.36 168663[71:MRR:168661.0,168349.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 168668[71:Res:168663.0,61.1] always3(s36) || -> . % 76.16/76.36 168669[71:SSi:168668.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.36 168670[69:Spt:168669.0,168283.0,168286.0] || trans(s49,s35)*+ -> . % 76.16/76.36 168671[69:Spt:168669.0,168283.1,168283.2,168283.3,168283.4,168283.5,168283.6,168283.7,168283.8,168283.9,168283.10,168283.11,168283.12,168283.13,168283.14,168283.15,168283.16,168283.17,168283.18,168283.19,168283.20,168283.21,168283.22,168283.23,168283.24,168283.25,168283.26,168283.27,168283.28,168283.29,168283.30] || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 168673[69:MRR:168285.1,168670.0] xuntil6(s49) || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 168674[70:Spt:168671.0] || -> trans(s49,s34)*. % 76.16/76.36 168675[70:Res:168674.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s34)*. % 76.16/76.36 168677[70:Res:168674.0,60.0] || -> node2(s49,s34)*. % 76.16/76.36 168678[70:SSi:168675.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s34)*. % 76.16/76.36 168679[70:Res:168677.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 168730[70:SoR:168679.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 168732[70:SoR:168730.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)* xuntil6(s49). % 76.16/76.36 168733[70:SSi:168732.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s34,c_busy)* xuntil6(s49). % 76.16/76.36 168734[71:Spt:168733.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 168736[71:Res:168734.0,61.1] always3(s34) || -> . % 76.16/76.36 168737[71:SSi:168736.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.36 168738[71:Spt:168737.0,168733.1,168734.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.16/76.36 168739[71:Spt:168737.0,168733.0,168733.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 168743[71:MRR:168730.2,168738.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 168744[71:Res:53.1,168739.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 168746[71:MRR:168744.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 168747[71:MRR:168678.0,168746.0] || -> until2p7(s34)*. % 76.16/76.36 168748[71:MRR:230.0,168747.0] || -> until2p7(s35)* node4(s34). % 76.16/76.36 168749[72:Spt:168748.0] || -> until2p7(s35)*. % 76.16/76.36 168750[72:MRR:231.0,168749.0] || -> until2p7(s36)* node4(s35). % 76.16/76.36 168751[73:Spt:168750.0] || -> until2p7(s36)*. % 76.16/76.36 168752[73:MRR:232.0,168751.0] || -> until2p7(s37)* node4(s36). % 76.16/76.36 168753[74:Spt:168752.0] || -> until2p7(s37)*. % 76.16/76.36 168754[74:MRR:235.0,168753.0] || -> until2p7(s38)* node4(s37). % 76.16/76.36 168755[75:Spt:168754.0] || -> until2p7(s38)*. % 76.16/76.36 168756[75:MRR:236.0,168755.0] || -> until2p7(s39)* node4(s38). % 76.16/76.36 168757[76:Spt:168756.0] || -> until2p7(s39)*. % 76.16/76.36 168758[76:MRR:237.0,168757.0] || -> until2p7(s40)* node4(s39). % 76.16/76.36 168759[77:Spt:168758.0] || -> until2p7(s40)*. % 76.16/76.36 168760[77:MRR:238.0,168759.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 168761[78:Spt:168760.0] || -> until2p7(s41)*. % 76.16/76.36 168762[78:MRR:239.0,168761.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 168763[79:Spt:168762.0] || -> until2p7(s42)*. % 76.16/76.36 168764[79:MRR:240.0,168763.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 168765[80:Spt:168764.0] || -> until2p7(s43)*. % 76.16/76.36 168766[80:MRR:241.0,168765.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 168767[81:Spt:168766.0] || -> until2p7(s44)*. % 76.16/76.36 168768[81:MRR:539.0,168767.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 168769[82:Spt:168768.0] || -> until2p7(s45)*. % 76.16/76.36 168770[82:MRR:544.0,168769.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 168771[83:Spt:168770.0] || -> until2p7(s46)*. % 76.16/76.36 168772[83:MRR:549.0,168771.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 168773[84:Spt:168772.0] || -> until2p7(s47)*. % 76.16/76.36 168774[84:MRR:554.0,168773.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 168775[85:Spt:168774.0] || -> until2p7(s48)*. % 76.16/76.36 168776[85:MRR:559.0,168775.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 168777[86:Spt:168776.0] || -> until2p7(s49)*. % 76.16/76.36 168778[86:MRR:194.0,168777.0] || -> node4(s49)*. % 76.16/76.36 168779[86:MRR:168743.0,168778.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 168780[86:Res:53.1,168779.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 168782[86:MRR:168780.0,78381.0] || -> . % 76.16/76.36 168783[86:Spt:168782.0,168776.0,168777.0] || until2p7(s49)*+ -> . % 76.16/76.36 168784[86:Spt:168782.0,168776.1] || -> node4(s48)*. % 76.16/76.36 168785[86:MRR:78384.0,168784.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 168788[86:Res:53.1,168785.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 168791[86:Res:168788.0,61.1] always3(s48) || -> . % 76.16/76.36 168792[86:SSi:168791.0,78281.0,78387.0,165540.0,168775.0,168784.0] || -> . % 76.16/76.36 168793[85:Spt:168792.0,168774.0,168775.0] || until2p7(s48)*+ -> . % 76.16/76.36 168794[85:Spt:168792.0,168774.1] || -> node4(s47)*. % 76.16/76.36 168796[85:MRR:777.0,168794.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 168811[85:Res:53.1,168796.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 168813[86:Spt:168811.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 168815[86:Res:168813.0,61.1] always3(s47) || -> . % 76.16/76.36 168816[86:SSi:168815.0,78277.0,78280.0,165539.0,168773.0,168794.0] || -> . % 76.16/76.36 168817[86:Spt:168816.0,168811.0,168813.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 168818[86:Spt:168816.0,168811.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 168822[86:Res:168818.0,61.1] always3(s48) || -> . % 76.16/76.36 168823[86:SSi:168822.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 168824[84:Spt:168823.0,168772.0,168773.0] || until2p7(s47)*+ -> . % 76.16/76.36 168825[84:Spt:168823.0,168772.1] || -> node4(s46)*. % 76.16/76.36 168827[84:MRR:780.0,168825.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 168837[84:Res:53.1,168827.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 168839[85:Spt:168837.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 168841[85:Res:168839.0,61.1] always3(s46) || -> . % 76.16/76.36 168842[85:SSi:168841.0,78272.0,78276.0,165538.0,168771.0,168825.0] || -> . % 76.16/76.36 168843[85:Spt:168842.0,168837.0,168839.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 168844[85:Spt:168842.0,168837.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 168848[85:Res:168844.0,61.1] always3(s47) || -> . % 76.16/76.36 168849[85:SSi:168848.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 168850[83:Spt:168849.0,168770.0,168771.0] || until2p7(s46)*+ -> . % 76.16/76.36 168851[83:Spt:168849.0,168770.1] || -> node4(s45)*. % 76.16/76.36 168853[83:MRR:783.0,168851.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 168856[83:Res:53.1,168853.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 168858[84:Spt:168856.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 168860[84:Res:168858.0,61.1] always3(s45) || -> . % 76.16/76.36 168861[84:SSi:168860.0,78268.0,78271.0,165537.0,168769.0,168851.0] || -> . % 76.16/76.36 168862[84:Spt:168861.0,168856.0,168858.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 168863[84:Spt:168861.0,168856.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 168867[84:Res:168863.0,61.1] always3(s46) || -> . % 76.16/76.36 168868[84:SSi:168867.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 168869[82:Spt:168868.0,168768.0,168769.0] || until2p7(s45)*+ -> . % 76.16/76.36 168870[82:Spt:168868.0,168768.1] || -> node4(s44)*. % 76.16/76.36 168872[82:MRR:786.0,168870.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 168875[82:Res:53.1,168872.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 168877[83:Spt:168875.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 168879[83:Res:168877.0,61.1] always3(s44) || -> . % 76.16/76.36 168880[83:SSi:168879.0,78263.0,78267.0,165536.0,168767.0,168870.0] || -> . % 76.16/76.36 168881[83:Spt:168880.0,168875.0,168877.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 168882[83:Spt:168880.0,168875.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 168886[83:Res:168882.0,61.1] always3(s45) || -> . % 76.16/76.36 168887[83:SSi:168886.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 168888[81:Spt:168887.0,168766.0,168767.0] || until2p7(s44)*+ -> . % 76.16/76.36 168889[81:Spt:168887.0,168766.1] || -> node4(s43)*. % 76.16/76.36 168891[81:MRR:789.0,168889.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 168894[81:Res:53.1,168891.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 168899[82:Spt:168894.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 168901[82:Res:168899.0,61.1] always3(s43) || -> . % 76.16/76.36 168902[82:SSi:168901.0,78259.0,78262.0,165535.0,168765.0,168889.0] || -> . % 76.16/76.36 168903[82:Spt:168902.0,168894.0,168899.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 168904[82:Spt:168902.0,168894.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 168908[82:Res:168904.0,61.1] always3(s44) || -> . % 76.16/76.36 168909[82:SSi:168908.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.36 168910[80:Spt:168909.0,168764.0,168765.0] || until2p7(s43)*+ -> . % 76.16/76.36 168911[80:Spt:168909.0,168764.1] || -> node4(s42)*. % 76.16/76.36 168913[80:MRR:792.0,168911.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 168916[80:Res:53.1,168913.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 168918[81:Spt:168916.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 168920[81:Res:168918.0,61.1] always3(s42) || -> . % 76.16/76.36 168921[81:SSi:168920.0,78254.0,78258.0,165534.0,168763.0,168911.0] || -> . % 76.16/76.36 168922[81:Spt:168921.0,168916.0,168918.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 168923[81:Spt:168921.0,168916.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 168927[81:Res:168923.0,61.1] always3(s43) || -> . % 76.16/76.36 168928[81:SSi:168927.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.36 168929[79:Spt:168928.0,168762.0,168763.0] || until2p7(s42)*+ -> . % 76.16/76.36 168930[79:Spt:168928.0,168762.1] || -> node4(s41)*. % 76.16/76.36 168932[79:MRR:795.0,168930.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 168935[79:Res:53.1,168932.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 168937[80:Spt:168935.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 168939[80:Res:168937.0,61.1] always3(s41) || -> . % 76.16/76.36 168940[80:SSi:168939.0,78250.0,78253.0,165533.0,168761.0,168930.0] || -> . % 76.16/76.36 168941[80:Spt:168940.0,168935.0,168937.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 168942[80:Spt:168940.0,168935.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 168946[80:Res:168942.0,61.1] always3(s42) || -> . % 76.16/76.36 168947[80:SSi:168946.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.36 168948[78:Spt:168947.0,168760.0,168761.0] || until2p7(s41)*+ -> . % 76.16/76.36 168949[78:Spt:168947.0,168760.1] || -> node4(s40)*. % 76.16/76.36 168951[78:MRR:798.0,168949.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 168954[78:Res:53.1,168951.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 168956[79:Spt:168954.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 168958[79:Res:168956.0,61.1] always3(s40) || -> . % 76.16/76.36 168959[79:SSi:168958.0,78245.0,78249.0,165532.0,168759.0,168949.0] || -> . % 76.16/76.36 168960[79:Spt:168959.0,168954.0,168956.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.36 168961[79:Spt:168959.0,168954.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 168965[79:Res:168961.0,61.1] always3(s41) || -> . % 76.16/76.36 168966[79:SSi:168965.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.36 168967[77:Spt:168966.0,168758.0,168759.0] || until2p7(s40)*+ -> . % 76.16/76.36 168968[77:Spt:168966.0,168758.1] || -> node4(s39)*. % 76.16/76.36 168970[77:MRR:801.0,168968.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.36 168973[77:Res:53.1,168970.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.36 168978[78:Spt:168973.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 168980[78:Res:168978.0,61.1] always3(s39) || -> . % 76.16/76.36 168981[78:SSi:168980.0,78241.0,78244.0,165531.0,168757.0,168968.0] || -> . % 76.16/76.36 168982[78:Spt:168981.0,168973.0,168978.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.36 168983[78:Spt:168981.0,168973.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 168987[78:Res:168983.0,61.1] always3(s40) || -> . % 76.16/76.36 168988[78:SSi:168987.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.36 168989[76:Spt:168988.0,168756.0,168757.0] || until2p7(s39)*+ -> . % 76.16/76.36 168990[76:Spt:168988.0,168756.1] || -> node4(s38)*. % 76.16/76.36 168992[76:MRR:804.0,168990.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.36 168995[76:Res:53.1,168992.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.36 168997[77:Spt:168995.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 168999[77:Res:168997.0,61.1] always3(s38) || -> . % 76.16/76.36 169000[77:SSi:168999.0,78236.0,78240.0,165530.0,168755.0,168990.0] || -> . % 76.16/76.36 169001[77:Spt:169000.0,168995.0,168997.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.36 169002[77:Spt:169000.0,168995.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 169006[77:Res:169002.0,61.1] always3(s39) || -> . % 76.16/76.36 169007[77:SSi:169006.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.36 169008[75:Spt:169007.0,168754.0,168755.0] || until2p7(s38)*+ -> . % 76.16/76.36 169009[75:Spt:169007.0,168754.1] || -> node4(s37)*. % 76.16/76.36 169011[75:MRR:807.0,169009.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.36 169014[75:Res:53.1,169011.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.36 169016[76:Spt:169014.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 169018[76:Res:169016.0,61.1] always3(s37) || -> . % 76.16/76.36 169019[76:SSi:169018.0,78232.0,78235.0,165529.0,168753.0,169009.0] || -> . % 76.16/76.36 169020[76:Spt:169019.0,169014.0,169016.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.36 169021[76:Spt:169019.0,169014.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 169025[76:Res:169021.0,61.1] always3(s38) || -> . % 76.16/76.36 169026[76:SSi:169025.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.36 169027[74:Spt:169026.0,168752.0,168753.0] || until2p7(s37)*+ -> . % 76.16/76.36 169028[74:Spt:169026.0,168752.1] || -> node4(s36)*. % 76.16/76.36 169030[74:MRR:810.0,169028.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.36 169033[74:Res:53.1,169030.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.36 169035[75:Spt:169033.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 169037[75:Res:169035.0,61.1] always3(s36) || -> . % 76.16/76.36 169038[75:SSi:169037.0,78227.0,78231.0,165528.0,168751.0,169028.0] || -> . % 76.16/76.36 169039[75:Spt:169038.0,169033.0,169035.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.36 169040[75:Spt:169038.0,169033.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 169044[75:Res:169040.0,61.1] always3(s37) || -> . % 76.16/76.36 169045[75:SSi:169044.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.36 169046[73:Spt:169045.0,168750.0,168751.0] || until2p7(s36)*+ -> . % 76.16/76.36 169047[73:Spt:169045.0,168750.1] || -> node4(s35)*. % 76.16/76.36 169049[73:MRR:813.0,169047.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.36 169052[73:Res:53.1,169049.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.36 169057[74:Spt:169052.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 169059[74:Res:169057.0,61.1] always3(s35) || -> . % 76.16/76.36 169060[74:SSi:169059.0,78223.0,78226.0,165527.0,168749.0,169047.0] || -> . % 76.16/76.36 169061[74:Spt:169060.0,169052.0,169057.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.36 169062[74:Spt:169060.0,169052.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 169066[74:Res:169062.0,61.1] always3(s36) || -> . % 76.16/76.36 169067[74:SSi:169066.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.36 169068[72:Spt:169067.0,168748.0,168749.0] || until2p7(s35)*+ -> . % 76.16/76.36 169069[72:Spt:169067.0,168748.1] || -> node4(s34)*. % 76.16/76.36 169071[72:MRR:816.0,169069.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.36 169074[72:Res:53.1,169071.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.36 169076[72:MRR:169074.0,168738.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 169078[72:Res:169076.0,61.1] always3(s35) || -> . % 76.16/76.36 169079[72:SSi:169078.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.36 169080[70:Spt:169079.0,168671.0,168674.0] || trans(s49,s34)*+ -> . % 76.16/76.36 169081[70:Spt:169079.0,168671.1,168671.2,168671.3,168671.4,168671.5,168671.6,168671.7,168671.8,168671.9,168671.10,168671.11,168671.12,168671.13,168671.14,168671.15,168671.16,168671.17,168671.18,168671.19,168671.20,168671.21,168671.22,168671.23,168671.24,168671.25,168671.26,168671.27,168671.28,168671.29] || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 169083[70:MRR:168673.1,169080.0] xuntil6(s49) || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 169084[71:Spt:169081.0] || -> trans(s49,s33)*. % 76.16/76.36 169085[71:Res:169084.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s33)*. % 76.16/76.36 169087[71:Res:169084.0,60.0] || -> node2(s49,s33)*. % 76.16/76.36 169088[71:SSi:169085.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s33)*. % 76.16/76.36 169089[71:Res:169087.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.16/76.36 169144[71:SoR:169089.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.16/76.36 169146[71:SoR:169144.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.16/76.36 169147[71:SSi:169146.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.16/76.36 169148[72:Spt:169147.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.36 169150[72:Res:169148.0,61.1] always3(s33) || -> . % 76.16/76.36 169151[72:SSi:169150.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.36 169152[72:Spt:169151.0,169147.1,169148.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.16/76.36 169153[72:Spt:169151.0,169147.0,169147.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 169157[72:MRR:169144.2,169152.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 169158[72:Res:53.1,169153.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 169160[72:MRR:169158.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 169161[72:MRR:169088.0,169160.0] || -> until2p7(s33)*. % 76.16/76.36 169162[72:MRR:229.0,169161.0] || -> until2p7(s34)* node4(s33). % 76.16/76.36 169163[73:Spt:169162.0] || -> until2p7(s34)*. % 76.16/76.36 169164[73:MRR:230.0,169163.0] || -> until2p7(s35)* node4(s34). % 76.16/76.36 169165[74:Spt:169164.0] || -> until2p7(s35)*. % 76.16/76.36 169166[74:MRR:231.0,169165.0] || -> until2p7(s36)* node4(s35). % 76.16/76.36 169167[75:Spt:169166.0] || -> until2p7(s36)*. % 76.16/76.36 169168[75:MRR:232.0,169167.0] || -> until2p7(s37)* node4(s36). % 76.16/76.36 169169[76:Spt:169168.0] || -> until2p7(s37)*. % 76.16/76.36 169170[76:MRR:235.0,169169.0] || -> until2p7(s38)* node4(s37). % 76.16/76.36 169171[77:Spt:169170.0] || -> until2p7(s38)*. % 76.16/76.36 169172[77:MRR:236.0,169171.0] || -> until2p7(s39)* node4(s38). % 76.16/76.36 169173[78:Spt:169172.0] || -> until2p7(s39)*. % 76.16/76.36 169174[78:MRR:237.0,169173.0] || -> until2p7(s40)* node4(s39). % 76.16/76.36 169175[79:Spt:169174.0] || -> until2p7(s40)*. % 76.16/76.36 169176[79:MRR:238.0,169175.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 169177[80:Spt:169176.0] || -> until2p7(s41)*. % 76.16/76.36 169178[80:MRR:239.0,169177.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 169179[81:Spt:169178.0] || -> until2p7(s42)*. % 76.16/76.36 169180[81:MRR:240.0,169179.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 169181[82:Spt:169180.0] || -> until2p7(s43)*. % 76.16/76.36 169182[82:MRR:241.0,169181.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 169183[83:Spt:169182.0] || -> until2p7(s44)*. % 76.16/76.36 169184[83:MRR:539.0,169183.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 169185[84:Spt:169184.0] || -> until2p7(s45)*. % 76.16/76.36 169186[84:MRR:544.0,169185.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 169187[85:Spt:169186.0] || -> until2p7(s46)*. % 76.16/76.36 169188[85:MRR:549.0,169187.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 169189[86:Spt:169188.0] || -> until2p7(s47)*. % 76.16/76.36 169190[86:MRR:554.0,169189.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 169191[87:Spt:169190.0] || -> until2p7(s48)*. % 76.16/76.36 169192[87:MRR:559.0,169191.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 169193[88:Spt:169192.0] || -> until2p7(s49)*. % 76.16/76.36 169194[88:MRR:194.0,169193.0] || -> node4(s49)*. % 76.16/76.36 169195[88:MRR:169157.0,169194.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 169199[88:Res:53.1,169195.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 169201[88:MRR:169199.0,78381.0] || -> . % 76.16/76.36 169202[88:Spt:169201.0,169192.0,169193.0] || until2p7(s49)*+ -> . % 76.16/76.36 169203[88:Spt:169201.0,169192.1] || -> node4(s48)*. % 76.16/76.36 169204[88:MRR:78384.0,169203.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 169207[88:Res:53.1,169204.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 169210[88:Res:169207.0,61.1] always3(s48) || -> . % 76.16/76.36 169211[88:SSi:169210.0,78281.0,78387.0,165540.0,169191.0,169203.0] || -> . % 76.16/76.36 169212[87:Spt:169211.0,169190.0,169191.0] || until2p7(s48)*+ -> . % 76.16/76.36 169213[87:Spt:169211.0,169190.1] || -> node4(s47)*. % 76.16/76.36 169215[87:MRR:777.0,169213.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 169227[87:Res:53.1,169215.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 169229[88:Spt:169227.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 169231[88:Res:169229.0,61.1] always3(s47) || -> . % 76.16/76.36 169232[88:SSi:169231.0,78277.0,78280.0,165539.0,169189.0,169213.0] || -> . % 76.16/76.36 169233[88:Spt:169232.0,169227.0,169229.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 169234[88:Spt:169232.0,169227.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 169238[88:Res:169234.0,61.1] always3(s48) || -> . % 76.16/76.36 169239[88:SSi:169238.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 169240[86:Spt:169239.0,169188.0,169189.0] || until2p7(s47)*+ -> . % 76.16/76.36 169241[86:Spt:169239.0,169188.1] || -> node4(s46)*. % 76.16/76.36 169243[86:MRR:780.0,169241.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 169250[86:Res:53.1,169243.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 169255[87:Spt:169250.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 169257[87:Res:169255.0,61.1] always3(s46) || -> . % 76.16/76.36 169258[87:SSi:169257.0,78272.0,78276.0,165538.0,169187.0,169241.0] || -> . % 76.16/76.36 169259[87:Spt:169258.0,169250.0,169255.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 169260[87:Spt:169258.0,169250.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 169264[87:Res:169260.0,61.1] always3(s47) || -> . % 76.16/76.36 169265[87:SSi:169264.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 169266[85:Spt:169265.0,169186.0,169187.0] || until2p7(s46)*+ -> . % 76.16/76.36 169267[85:Spt:169265.0,169186.1] || -> node4(s45)*. % 76.16/76.36 169269[85:MRR:783.0,169267.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 169272[85:Res:53.1,169269.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 169274[86:Spt:169272.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 169276[86:Res:169274.0,61.1] always3(s45) || -> . % 76.16/76.36 169277[86:SSi:169276.0,78268.0,78271.0,165537.0,169185.0,169267.0] || -> . % 76.16/76.36 169278[86:Spt:169277.0,169272.0,169274.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 169279[86:Spt:169277.0,169272.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 169283[86:Res:169279.0,61.1] always3(s46) || -> . % 76.16/76.36 169284[86:SSi:169283.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 169285[84:Spt:169284.0,169184.0,169185.0] || until2p7(s45)*+ -> . % 76.16/76.36 169286[84:Spt:169284.0,169184.1] || -> node4(s44)*. % 76.16/76.36 169288[84:MRR:786.0,169286.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 169291[84:Res:53.1,169288.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 169293[85:Spt:169291.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 169295[85:Res:169293.0,61.1] always3(s44) || -> . % 76.16/76.36 169296[85:SSi:169295.0,78263.0,78267.0,165536.0,169183.0,169286.0] || -> . % 76.16/76.36 169297[85:Spt:169296.0,169291.0,169293.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 169298[85:Spt:169296.0,169291.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 169302[85:Res:169298.0,61.1] always3(s45) || -> . % 76.16/76.36 169303[85:SSi:169302.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 169304[83:Spt:169303.0,169182.0,169183.0] || until2p7(s44)*+ -> . % 76.16/76.36 169305[83:Spt:169303.0,169182.1] || -> node4(s43)*. % 76.16/76.36 169307[83:MRR:789.0,169305.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 169310[83:Res:53.1,169307.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 169312[84:Spt:169310.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 169314[84:Res:169312.0,61.1] always3(s43) || -> . % 76.16/76.36 169315[84:SSi:169314.0,78259.0,78262.0,165535.0,169181.0,169305.0] || -> . % 76.16/76.36 169316[84:Spt:169315.0,169310.0,169312.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 169317[84:Spt:169315.0,169310.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 169321[84:Res:169317.0,61.1] always3(s44) || -> . % 76.16/76.36 169322[84:SSi:169321.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.36 169323[82:Spt:169322.0,169180.0,169181.0] || until2p7(s43)*+ -> . % 76.16/76.36 169324[82:Spt:169322.0,169180.1] || -> node4(s42)*. % 76.16/76.36 169326[82:MRR:792.0,169324.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 169329[82:Res:53.1,169326.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 169334[83:Spt:169329.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 169336[83:Res:169334.0,61.1] always3(s42) || -> . % 76.16/76.36 169337[83:SSi:169336.0,78254.0,78258.0,165534.0,169179.0,169324.0] || -> . % 76.16/76.36 169338[83:Spt:169337.0,169329.0,169334.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 169339[83:Spt:169337.0,169329.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 169343[83:Res:169339.0,61.1] always3(s43) || -> . % 76.16/76.36 169344[83:SSi:169343.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.36 169345[81:Spt:169344.0,169178.0,169179.0] || until2p7(s42)*+ -> . % 76.16/76.36 169346[81:Spt:169344.0,169178.1] || -> node4(s41)*. % 76.16/76.36 169348[81:MRR:795.0,169346.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 169351[81:Res:53.1,169348.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 169353[82:Spt:169351.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 169355[82:Res:169353.0,61.1] always3(s41) || -> . % 76.16/76.36 169356[82:SSi:169355.0,78250.0,78253.0,165533.0,169177.0,169346.0] || -> . % 76.16/76.36 169357[82:Spt:169356.0,169351.0,169353.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 169358[82:Spt:169356.0,169351.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 169362[82:Res:169358.0,61.1] always3(s42) || -> . % 76.16/76.36 169363[82:SSi:169362.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.36 169364[80:Spt:169363.0,169176.0,169177.0] || until2p7(s41)*+ -> . % 76.16/76.36 169365[80:Spt:169363.0,169176.1] || -> node4(s40)*. % 76.16/76.36 169367[80:MRR:798.0,169365.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 169370[80:Res:53.1,169367.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 169372[81:Spt:169370.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 169374[81:Res:169372.0,61.1] always3(s40) || -> . % 76.16/76.36 169375[81:SSi:169374.0,78245.0,78249.0,165532.0,169175.0,169365.0] || -> . % 76.16/76.36 169376[81:Spt:169375.0,169370.0,169372.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.36 169377[81:Spt:169375.0,169370.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 169381[81:Res:169377.0,61.1] always3(s41) || -> . % 76.16/76.36 169382[81:SSi:169381.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.36 169383[79:Spt:169382.0,169174.0,169175.0] || until2p7(s40)*+ -> . % 76.16/76.36 169384[79:Spt:169382.0,169174.1] || -> node4(s39)*. % 76.16/76.36 169386[79:MRR:801.0,169384.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.36 169389[79:Res:53.1,169386.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.36 169391[80:Spt:169389.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 169393[80:Res:169391.0,61.1] always3(s39) || -> . % 76.16/76.36 169394[80:SSi:169393.0,78241.0,78244.0,165531.0,169173.0,169384.0] || -> . % 76.16/76.36 169395[80:Spt:169394.0,169389.0,169391.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.36 169396[80:Spt:169394.0,169389.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 169400[80:Res:169396.0,61.1] always3(s40) || -> . % 76.16/76.36 169401[80:SSi:169400.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.36 169402[78:Spt:169401.0,169172.0,169173.0] || until2p7(s39)*+ -> . % 76.16/76.36 169403[78:Spt:169401.0,169172.1] || -> node4(s38)*. % 76.16/76.36 169405[78:MRR:804.0,169403.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.36 169408[78:Res:53.1,169405.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.36 169413[79:Spt:169408.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 169415[79:Res:169413.0,61.1] always3(s38) || -> . % 76.16/76.36 169416[79:SSi:169415.0,78236.0,78240.0,165530.0,169171.0,169403.0] || -> . % 76.16/76.36 169417[79:Spt:169416.0,169408.0,169413.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.36 169418[79:Spt:169416.0,169408.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.36 169422[79:Res:169418.0,61.1] always3(s39) || -> . % 76.16/76.36 169423[79:SSi:169422.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.36 169424[77:Spt:169423.0,169170.0,169171.0] || until2p7(s38)*+ -> . % 76.16/76.36 169425[77:Spt:169423.0,169170.1] || -> node4(s37)*. % 76.16/76.36 169427[77:MRR:807.0,169425.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.36 169430[77:Res:53.1,169427.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.36 169432[78:Spt:169430.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 169434[78:Res:169432.0,61.1] always3(s37) || -> . % 76.16/76.36 169435[78:SSi:169434.0,78232.0,78235.0,165529.0,169169.0,169425.0] || -> . % 76.16/76.36 169436[78:Spt:169435.0,169430.0,169432.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.36 169437[78:Spt:169435.0,169430.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.36 169441[78:Res:169437.0,61.1] always3(s38) || -> . % 76.16/76.36 169442[78:SSi:169441.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.36 169443[76:Spt:169442.0,169168.0,169169.0] || until2p7(s37)*+ -> . % 76.16/76.36 169444[76:Spt:169442.0,169168.1] || -> node4(s36)*. % 76.16/76.36 169446[76:MRR:810.0,169444.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.36 169449[76:Res:53.1,169446.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.36 169451[77:Spt:169449.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 169453[77:Res:169451.0,61.1] always3(s36) || -> . % 76.16/76.36 169454[77:SSi:169453.0,78227.0,78231.0,165528.0,169167.0,169444.0] || -> . % 76.16/76.36 169455[77:Spt:169454.0,169449.0,169451.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.36 169456[77:Spt:169454.0,169449.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.36 169460[77:Res:169456.0,61.1] always3(s37) || -> . % 76.16/76.36 169461[77:SSi:169460.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.36 169462[75:Spt:169461.0,169166.0,169167.0] || until2p7(s36)*+ -> . % 76.16/76.36 169463[75:Spt:169461.0,169166.1] || -> node4(s35)*. % 76.16/76.36 169465[75:MRR:813.0,169463.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.36 169468[75:Res:53.1,169465.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.36 169470[76:Spt:169468.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 169472[76:Res:169470.0,61.1] always3(s35) || -> . % 76.16/76.36 169473[76:SSi:169472.0,78223.0,78226.0,165527.0,169165.0,169463.0] || -> . % 76.16/76.36 169474[76:Spt:169473.0,169468.0,169470.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.36 169475[76:Spt:169473.0,169468.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.36 169479[76:Res:169475.0,61.1] always3(s36) || -> . % 76.16/76.36 169480[76:SSi:169479.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.36 169481[74:Spt:169480.0,169164.0,169165.0] || until2p7(s35)*+ -> . % 76.16/76.36 169482[74:Spt:169480.0,169164.1] || -> node4(s34)*. % 76.16/76.36 169484[74:MRR:816.0,169482.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.36 169487[74:Res:53.1,169484.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.36 169492[75:Spt:169487.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 169494[75:Res:169492.0,61.1] always3(s34) || -> . % 76.16/76.36 169495[75:SSi:169494.0,78218.0,78222.0,165526.0,169163.0,169482.0] || -> . % 76.16/76.36 169496[75:Spt:169495.0,169487.0,169492.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.36 169497[75:Spt:169495.0,169487.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.36 169501[75:Res:169497.0,61.1] always3(s35) || -> . % 76.16/76.36 169502[75:SSi:169501.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.36 169503[73:Spt:169502.0,169162.0,169163.0] || until2p7(s34)*+ -> . % 76.16/76.36 169504[73:Spt:169502.0,169162.1] || -> node4(s33)*. % 76.16/76.36 169506[73:MRR:819.0,169504.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.36 169509[73:Res:53.1,169506.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.36 169511[73:MRR:169509.0,169152.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.36 169513[73:Res:169511.0,61.1] always3(s34) || -> . % 76.16/76.36 169514[73:SSi:169513.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.36 169515[71:Spt:169514.0,169081.0,169084.0] || trans(s49,s33)*+ -> . % 76.16/76.36 169516[71:Spt:169514.0,169081.1,169081.2,169081.3,169081.4,169081.5,169081.6,169081.7,169081.8,169081.9,169081.10,169081.11,169081.12,169081.13,169081.14,169081.15,169081.16,169081.17,169081.18,169081.19,169081.20,169081.21,169081.22,169081.23,169081.24,169081.25,169081.26,169081.27,169081.28] || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.36 169518[71:MRR:169083.1,169515.0] xuntil6(s49) || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.36 169519[72:Spt:169516.0] || -> trans(s49,s32)*. % 76.16/76.36 169520[72:Res:169519.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s32)*. % 76.16/76.36 169522[72:Res:169519.0,60.0] || -> node2(s49,s32)*. % 76.16/76.36 169523[72:SSi:169520.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s32)*. % 76.16/76.36 169524[72:Res:169522.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)*. % 76.16/76.36 169583[72:SoR:169524.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)*. % 76.16/76.36 169585[72:SoR:169583.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)* xuntil6(s49). % 76.16/76.36 169586[72:SSi:169585.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s32,c_busy)* xuntil6(s49). % 76.16/76.36 169587[73:Spt:169586.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.36 169589[73:Res:169587.0,61.1] always3(s32) || -> . % 76.16/76.36 169590[73:SSi:169589.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.36 169591[73:Spt:169590.0,169586.1,169587.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.16/76.36 169592[73:Spt:169590.0,169586.0,169586.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.36 169596[73:MRR:169583.2,169591.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.36 169597[73:Res:53.1,169592.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.36 169599[73:MRR:169597.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.36 169600[73:MRR:169523.0,169599.0] || -> until2p7(s32)*. % 76.16/76.36 169601[73:MRR:228.0,169600.0] || -> until2p7(s33)* node4(s32). % 76.16/76.36 169602[74:Spt:169601.0] || -> until2p7(s33)*. % 76.16/76.36 169603[74:MRR:229.0,169602.0] || -> until2p7(s34)* node4(s33). % 76.16/76.36 169604[75:Spt:169603.0] || -> until2p7(s34)*. % 76.16/76.36 169605[75:MRR:230.0,169604.0] || -> until2p7(s35)* node4(s34). % 76.16/76.36 169606[76:Spt:169605.0] || -> until2p7(s35)*. % 76.16/76.36 169607[76:MRR:231.0,169606.0] || -> until2p7(s36)* node4(s35). % 76.16/76.36 169608[77:Spt:169607.0] || -> until2p7(s36)*. % 76.16/76.36 169609[77:MRR:232.0,169608.0] || -> until2p7(s37)* node4(s36). % 76.16/76.36 169610[78:Spt:169609.0] || -> until2p7(s37)*. % 76.16/76.36 169611[78:MRR:235.0,169610.0] || -> until2p7(s38)* node4(s37). % 76.16/76.36 169612[79:Spt:169611.0] || -> until2p7(s38)*. % 76.16/76.36 169613[79:MRR:236.0,169612.0] || -> until2p7(s39)* node4(s38). % 76.16/76.36 169614[80:Spt:169613.0] || -> until2p7(s39)*. % 76.16/76.36 169615[80:MRR:237.0,169614.0] || -> until2p7(s40)* node4(s39). % 76.16/76.36 169616[81:Spt:169615.0] || -> until2p7(s40)*. % 76.16/76.36 169617[81:MRR:238.0,169616.0] || -> until2p7(s41)* node4(s40). % 76.16/76.36 169618[82:Spt:169617.0] || -> until2p7(s41)*. % 76.16/76.36 169619[82:MRR:239.0,169618.0] || -> until2p7(s42)* node4(s41). % 76.16/76.36 169620[83:Spt:169619.0] || -> until2p7(s42)*. % 76.16/76.36 169621[83:MRR:240.0,169620.0] || -> until2p7(s43)* node4(s42). % 76.16/76.36 169622[84:Spt:169621.0] || -> until2p7(s43)*. % 76.16/76.36 169623[84:MRR:241.0,169622.0] || -> until2p7(s44)* node4(s43). % 76.16/76.36 169624[85:Spt:169623.0] || -> until2p7(s44)*. % 76.16/76.36 169625[85:MRR:539.0,169624.0] || -> until2p7(s45)* node4(s44). % 76.16/76.36 169626[86:Spt:169625.0] || -> until2p7(s45)*. % 76.16/76.36 169627[86:MRR:544.0,169626.0] || -> until2p7(s46)* node4(s45). % 76.16/76.36 169628[87:Spt:169627.0] || -> until2p7(s46)*. % 76.16/76.36 169629[87:MRR:549.0,169628.0] || -> until2p7(s47)* node4(s46). % 76.16/76.36 169630[88:Spt:169629.0] || -> until2p7(s47)*. % 76.16/76.36 169631[88:MRR:554.0,169630.0] || -> until2p7(s48)* node4(s47). % 76.16/76.36 169632[89:Spt:169631.0] || -> until2p7(s48)*. % 76.16/76.36 169633[89:MRR:559.0,169632.0] || -> until2p7(s49)* node4(s48). % 76.16/76.36 169634[90:Spt:169633.0] || -> until2p7(s49)*. % 76.16/76.36 169635[90:MRR:194.0,169634.0] || -> node4(s49)*. % 76.16/76.36 169636[90:MRR:169596.0,169635.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.36 169637[90:Res:53.1,169636.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.36 169639[90:MRR:169637.0,78381.0] || -> . % 76.16/76.36 169640[90:Spt:169639.0,169633.0,169634.0] || until2p7(s49)*+ -> . % 76.16/76.36 169641[90:Spt:169639.0,169633.1] || -> node4(s48)*. % 76.16/76.36 169642[90:MRR:78384.0,169641.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.36 169645[90:Res:53.1,169642.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 169648[90:Res:169645.0,61.1] always3(s48) || -> . % 76.16/76.36 169649[90:SSi:169648.0,78281.0,78387.0,165540.0,169632.0,169641.0] || -> . % 76.16/76.36 169650[89:Spt:169649.0,169631.0,169632.0] || until2p7(s48)*+ -> . % 76.16/76.36 169651[89:Spt:169649.0,169631.1] || -> node4(s47)*. % 76.16/76.36 169653[89:MRR:777.0,169651.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.36 169668[89:Res:53.1,169653.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.36 169673[90:Spt:169668.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 169675[90:Res:169673.0,61.1] always3(s47) || -> . % 76.16/76.36 169676[90:SSi:169675.0,78277.0,78280.0,165539.0,169630.0,169651.0] || -> . % 76.16/76.36 169677[90:Spt:169676.0,169668.0,169673.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.36 169678[90:Spt:169676.0,169668.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.36 169682[90:Res:169678.0,61.1] always3(s48) || -> . % 76.16/76.36 169683[90:SSi:169682.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.36 169684[88:Spt:169683.0,169629.0,169630.0] || until2p7(s47)*+ -> . % 76.16/76.36 169685[88:Spt:169683.0,169629.1] || -> node4(s46)*. % 76.16/76.36 169687[88:MRR:780.0,169685.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.36 169694[88:Res:53.1,169687.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.36 169696[89:Spt:169694.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 169698[89:Res:169696.0,61.1] always3(s46) || -> . % 76.16/76.36 169699[89:SSi:169698.0,78272.0,78276.0,165538.0,169628.0,169685.0] || -> . % 76.16/76.36 169700[89:Spt:169699.0,169694.0,169696.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.36 169701[89:Spt:169699.0,169694.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.36 169705[89:Res:169701.0,61.1] always3(s47) || -> . % 76.16/76.36 169706[89:SSi:169705.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.36 169707[87:Spt:169706.0,169627.0,169628.0] || until2p7(s46)*+ -> . % 76.16/76.36 169708[87:Spt:169706.0,169627.1] || -> node4(s45)*. % 76.16/76.36 169710[87:MRR:783.0,169708.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.36 169713[87:Res:53.1,169710.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.36 169718[88:Spt:169713.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 169720[88:Res:169718.0,61.1] always3(s45) || -> . % 76.16/76.36 169721[88:SSi:169720.0,78268.0,78271.0,165537.0,169626.0,169708.0] || -> . % 76.16/76.36 169722[88:Spt:169721.0,169713.0,169718.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.36 169723[88:Spt:169721.0,169713.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.36 169727[88:Res:169723.0,61.1] always3(s46) || -> . % 76.16/76.36 169728[88:SSi:169727.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.36 169729[86:Spt:169728.0,169625.0,169626.0] || until2p7(s45)*+ -> . % 76.16/76.36 169730[86:Spt:169728.0,169625.1] || -> node4(s44)*. % 76.16/76.36 169732[86:MRR:786.0,169730.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.36 169735[86:Res:53.1,169732.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.36 169737[87:Spt:169735.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 169739[87:Res:169737.0,61.1] always3(s44) || -> . % 76.16/76.36 169740[87:SSi:169739.0,78263.0,78267.0,165536.0,169624.0,169730.0] || -> . % 76.16/76.36 169741[87:Spt:169740.0,169735.0,169737.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.36 169742[87:Spt:169740.0,169735.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.36 169746[87:Res:169742.0,61.1] always3(s45) || -> . % 76.16/76.36 169747[87:SSi:169746.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.36 169748[85:Spt:169747.0,169623.0,169624.0] || until2p7(s44)*+ -> . % 76.16/76.36 169749[85:Spt:169747.0,169623.1] || -> node4(s43)*. % 76.16/76.36 169751[85:MRR:789.0,169749.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.36 169754[85:Res:53.1,169751.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.36 169756[86:Spt:169754.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 169758[86:Res:169756.0,61.1] always3(s43) || -> . % 76.16/76.36 169759[86:SSi:169758.0,78259.0,78262.0,165535.0,169622.0,169749.0] || -> . % 76.16/76.36 169760[86:Spt:169759.0,169754.0,169756.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.36 169761[86:Spt:169759.0,169754.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.36 169765[86:Res:169761.0,61.1] always3(s44) || -> . % 76.16/76.36 169766[86:SSi:169765.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.36 169767[84:Spt:169766.0,169621.0,169622.0] || until2p7(s43)*+ -> . % 76.16/76.36 169768[84:Spt:169766.0,169621.1] || -> node4(s42)*. % 76.16/76.36 169770[84:MRR:792.0,169768.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.36 169773[84:Res:53.1,169770.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.36 169775[85:Spt:169773.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 169777[85:Res:169775.0,61.1] always3(s42) || -> . % 76.16/76.36 169778[85:SSi:169777.0,78254.0,78258.0,165534.0,169620.0,169768.0] || -> . % 76.16/76.36 169779[85:Spt:169778.0,169773.0,169775.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.36 169780[85:Spt:169778.0,169773.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.36 169784[85:Res:169780.0,61.1] always3(s43) || -> . % 76.16/76.36 169785[85:SSi:169784.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.36 169786[83:Spt:169785.0,169619.0,169620.0] || until2p7(s42)*+ -> . % 76.16/76.36 169787[83:Spt:169785.0,169619.1] || -> node4(s41)*. % 76.16/76.36 169789[83:MRR:795.0,169787.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.36 169792[83:Res:53.1,169789.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.36 169797[84:Spt:169792.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.36 169799[84:Res:169797.0,61.1] always3(s41) || -> . % 76.16/76.36 169800[84:SSi:169799.0,78250.0,78253.0,165533.0,169618.0,169787.0] || -> . % 76.16/76.36 169801[84:Spt:169800.0,169792.0,169797.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.36 169802[84:Spt:169800.0,169792.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.36 169806[84:Res:169802.0,61.1] always3(s42) || -> . % 76.16/76.36 169807[84:SSi:169806.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.36 169808[82:Spt:169807.0,169617.0,169618.0] || until2p7(s41)*+ -> . % 76.16/76.36 169809[82:Spt:169807.0,169617.1] || -> node4(s40)*. % 76.16/76.36 169811[82:MRR:798.0,169809.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.36 169814[82:Res:53.1,169811.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.36 169816[83:Spt:169814.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.36 169818[83:Res:169816.0,61.1] always3(s40) || -> . % 76.16/76.36 169819[83:SSi:169818.0,78245.0,78249.0,165532.0,169616.0,169809.0] || -> . % 76.16/76.36 169820[83:Spt:169819.0,169814.0,169816.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.36 169821[83:Spt:169819.0,169814.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 169825[83:Res:169821.0,61.1] always3(s41) || -> . % 76.16/76.37 169826[83:SSi:169825.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 169827[81:Spt:169826.0,169615.0,169616.0] || until2p7(s40)*+ -> . % 76.16/76.37 169828[81:Spt:169826.0,169615.1] || -> node4(s39)*. % 76.16/76.37 169830[81:MRR:801.0,169828.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 169833[81:Res:53.1,169830.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 169835[82:Spt:169833.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 169837[82:Res:169835.0,61.1] always3(s39) || -> . % 76.16/76.37 169838[82:SSi:169837.0,78241.0,78244.0,165531.0,169614.0,169828.0] || -> . % 76.16/76.37 169839[82:Spt:169838.0,169833.0,169835.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 169840[82:Spt:169838.0,169833.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 169844[82:Res:169840.0,61.1] always3(s40) || -> . % 76.16/76.37 169845[82:SSi:169844.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 169846[80:Spt:169845.0,169613.0,169614.0] || until2p7(s39)*+ -> . % 76.16/76.37 169847[80:Spt:169845.0,169613.1] || -> node4(s38)*. % 76.16/76.37 169849[80:MRR:804.0,169847.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 169852[80:Res:53.1,169849.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 169854[81:Spt:169852.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 169856[81:Res:169854.0,61.1] always3(s38) || -> . % 76.16/76.37 169857[81:SSi:169856.0,78236.0,78240.0,165530.0,169612.0,169847.0] || -> . % 76.16/76.37 169858[81:Spt:169857.0,169852.0,169854.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 169859[81:Spt:169857.0,169852.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 169863[81:Res:169859.0,61.1] always3(s39) || -> . % 76.16/76.37 169864[81:SSi:169863.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 169865[79:Spt:169864.0,169611.0,169612.0] || until2p7(s38)*+ -> . % 76.16/76.37 169866[79:Spt:169864.0,169611.1] || -> node4(s37)*. % 76.16/76.37 169868[79:MRR:807.0,169866.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 169871[79:Res:53.1,169868.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 169876[80:Spt:169871.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 169878[80:Res:169876.0,61.1] always3(s37) || -> . % 76.16/76.37 169879[80:SSi:169878.0,78232.0,78235.0,165529.0,169610.0,169866.0] || -> . % 76.16/76.37 169880[80:Spt:169879.0,169871.0,169876.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 169881[80:Spt:169879.0,169871.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 169885[80:Res:169881.0,61.1] always3(s38) || -> . % 76.16/76.37 169886[80:SSi:169885.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 169887[78:Spt:169886.0,169609.0,169610.0] || until2p7(s37)*+ -> . % 76.16/76.37 169888[78:Spt:169886.0,169609.1] || -> node4(s36)*. % 76.16/76.37 169890[78:MRR:810.0,169888.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 169893[78:Res:53.1,169890.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 169895[79:Spt:169893.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 169897[79:Res:169895.0,61.1] always3(s36) || -> . % 76.16/76.37 169898[79:SSi:169897.0,78227.0,78231.0,165528.0,169608.0,169888.0] || -> . % 76.16/76.37 169899[79:Spt:169898.0,169893.0,169895.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 169900[79:Spt:169898.0,169893.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 169904[79:Res:169900.0,61.1] always3(s37) || -> . % 76.16/76.37 169905[79:SSi:169904.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 169906[77:Spt:169905.0,169607.0,169608.0] || until2p7(s36)*+ -> . % 76.16/76.37 169907[77:Spt:169905.0,169607.1] || -> node4(s35)*. % 76.16/76.37 169909[77:MRR:813.0,169907.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 169912[77:Res:53.1,169909.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 169914[78:Spt:169912.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 169916[78:Res:169914.0,61.1] always3(s35) || -> . % 76.16/76.37 169917[78:SSi:169916.0,78223.0,78226.0,165527.0,169606.0,169907.0] || -> . % 76.16/76.37 169918[78:Spt:169917.0,169912.0,169914.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 169919[78:Spt:169917.0,169912.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 169923[78:Res:169919.0,61.1] always3(s36) || -> . % 76.16/76.37 169924[78:SSi:169923.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 169925[76:Spt:169924.0,169605.0,169606.0] || until2p7(s35)*+ -> . % 76.16/76.37 169926[76:Spt:169924.0,169605.1] || -> node4(s34)*. % 76.16/76.37 169928[76:MRR:816.0,169926.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 169931[76:Res:53.1,169928.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 169933[77:Spt:169931.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 169935[77:Res:169933.0,61.1] always3(s34) || -> . % 76.16/76.37 169936[77:SSi:169935.0,78218.0,78222.0,165526.0,169604.0,169926.0] || -> . % 76.16/76.37 169937[77:Spt:169936.0,169931.0,169933.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 169938[77:Spt:169936.0,169931.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 169942[77:Res:169938.0,61.1] always3(s35) || -> . % 76.16/76.37 169943[77:SSi:169942.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 169944[75:Spt:169943.0,169603.0,169604.0] || until2p7(s34)*+ -> . % 76.16/76.37 169945[75:Spt:169943.0,169603.1] || -> node4(s33)*. % 76.16/76.37 169947[75:MRR:819.0,169945.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 169950[75:Res:53.1,169947.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 169955[76:Spt:169950.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 169957[76:Res:169955.0,61.1] always3(s33) || -> . % 76.16/76.37 169958[76:SSi:169957.0,78214.0,78217.0,165525.0,169602.0,169945.0] || -> . % 76.16/76.37 169959[76:Spt:169958.0,169950.0,169955.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 169960[76:Spt:169958.0,169950.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 169964[76:Res:169960.0,61.1] always3(s34) || -> . % 76.16/76.37 169965[76:SSi:169964.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 169966[74:Spt:169965.0,169601.0,169602.0] || until2p7(s33)*+ -> . % 76.16/76.37 169967[74:Spt:169965.0,169601.1] || -> node4(s32)*. % 76.16/76.37 169969[74:MRR:822.0,169967.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 169972[74:Res:53.1,169969.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 169974[74:MRR:169972.0,169591.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 169976[74:Res:169974.0,61.1] always3(s33) || -> . % 76.16/76.37 169977[74:SSi:169976.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 169978[72:Spt:169977.0,169516.0,169519.0] || trans(s49,s32)*+ -> . % 76.16/76.37 169979[72:Spt:169977.0,169516.1,169516.2,169516.3,169516.4,169516.5,169516.6,169516.7,169516.8,169516.9,169516.10,169516.11,169516.12,169516.13,169516.14,169516.15,169516.16,169516.17,169516.18,169516.19,169516.20,169516.21,169516.22,169516.23,169516.24,169516.25,169516.26,169516.27] || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 169981[72:MRR:169518.1,169978.0] xuntil6(s49) || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 169982[73:Spt:169979.0] || -> trans(s49,s31)*. % 76.16/76.37 169983[73:Res:169982.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s31)*. % 76.16/76.37 169985[73:Res:169982.0,60.0] || -> node2(s49,s31)*. % 76.16/76.37 169986[73:SSi:169983.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s31)*. % 76.16/76.37 169987[73:Res:169985.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 170047[73:SoR:169987.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 170049[73:SoR:170047.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.16/76.37 170050[73:SSi:170049.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.16/76.37 170051[74:Spt:170050.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 170053[74:Res:170051.0,61.1] always3(s31) || -> . % 76.16/76.37 170054[74:SSi:170053.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 170055[74:Spt:170054.0,170050.1,170051.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.16/76.37 170056[74:Spt:170054.0,170050.0,170050.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 170060[74:MRR:170047.2,170055.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 170061[74:Res:53.1,170056.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 170063[74:MRR:170061.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 170064[74:MRR:169986.0,170063.0] || -> until2p7(s31)*. % 76.16/76.37 170065[74:MRR:227.0,170064.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 170066[75:Spt:170065.0] || -> until2p7(s32)*. % 76.16/76.37 170067[75:MRR:228.0,170066.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 170068[76:Spt:170067.0] || -> until2p7(s33)*. % 76.16/76.37 170069[76:MRR:229.0,170068.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 170070[77:Spt:170069.0] || -> until2p7(s34)*. % 76.16/76.37 170071[77:MRR:230.0,170070.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 170072[78:Spt:170071.0] || -> until2p7(s35)*. % 76.16/76.37 170073[78:MRR:231.0,170072.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 170074[79:Spt:170073.0] || -> until2p7(s36)*. % 76.16/76.37 170075[79:MRR:232.0,170074.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 170076[80:Spt:170075.0] || -> until2p7(s37)*. % 76.16/76.37 170077[80:MRR:235.0,170076.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 170078[81:Spt:170077.0] || -> until2p7(s38)*. % 76.16/76.37 170079[81:MRR:236.0,170078.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 170080[82:Spt:170079.0] || -> until2p7(s39)*. % 76.16/76.37 170081[82:MRR:237.0,170080.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 170082[83:Spt:170081.0] || -> until2p7(s40)*. % 76.16/76.37 170083[83:MRR:238.0,170082.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 170084[84:Spt:170083.0] || -> until2p7(s41)*. % 76.16/76.37 170085[84:MRR:239.0,170084.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 170086[85:Spt:170085.0] || -> until2p7(s42)*. % 76.16/76.37 170087[85:MRR:240.0,170086.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 170088[86:Spt:170087.0] || -> until2p7(s43)*. % 76.16/76.37 170089[86:MRR:241.0,170088.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 170090[87:Spt:170089.0] || -> until2p7(s44)*. % 76.16/76.37 170091[87:MRR:539.0,170090.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 170092[88:Spt:170091.0] || -> until2p7(s45)*. % 76.16/76.37 170093[88:MRR:544.0,170092.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 170094[89:Spt:170093.0] || -> until2p7(s46)*. % 76.16/76.37 170095[89:MRR:549.0,170094.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 170096[90:Spt:170095.0] || -> until2p7(s47)*. % 76.16/76.37 170097[90:MRR:554.0,170096.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 170098[91:Spt:170097.0] || -> until2p7(s48)*. % 76.16/76.37 170099[91:MRR:559.0,170098.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 170100[92:Spt:170099.0] || -> until2p7(s49)*. % 76.16/76.37 170101[92:MRR:194.0,170100.0] || -> node4(s49)*. % 76.16/76.37 170102[92:MRR:170060.0,170101.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 170106[92:Res:53.1,170102.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 170108[92:MRR:170106.0,78381.0] || -> . % 76.16/76.37 170109[92:Spt:170108.0,170099.0,170100.0] || until2p7(s49)*+ -> . % 76.16/76.37 170110[92:Spt:170108.0,170099.1] || -> node4(s48)*. % 76.16/76.37 170111[92:MRR:78384.0,170110.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 170114[92:Res:53.1,170111.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 170117[92:Res:170114.0,61.1] always3(s48) || -> . % 76.16/76.37 170118[92:SSi:170117.0,78281.0,78387.0,165540.0,170098.0,170110.0] || -> . % 76.16/76.37 170119[91:Spt:170118.0,170097.0,170098.0] || until2p7(s48)*+ -> . % 76.16/76.37 170120[91:Spt:170118.0,170097.1] || -> node4(s47)*. % 76.16/76.37 170122[91:MRR:777.0,170120.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 170134[91:Res:53.1,170122.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 170136[92:Spt:170134.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 170138[92:Res:170136.0,61.1] always3(s47) || -> . % 76.16/76.37 170139[92:SSi:170138.0,78277.0,78280.0,165539.0,170096.0,170120.0] || -> . % 76.16/76.37 170140[92:Spt:170139.0,170134.0,170136.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 170141[92:Spt:170139.0,170134.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 170145[92:Res:170141.0,61.1] always3(s48) || -> . % 76.16/76.37 170146[92:SSi:170145.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 170147[90:Spt:170146.0,170095.0,170096.0] || until2p7(s47)*+ -> . % 76.16/76.37 170148[90:Spt:170146.0,170095.1] || -> node4(s46)*. % 76.16/76.37 170150[90:MRR:780.0,170148.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 170157[90:Res:53.1,170150.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 170162[91:Spt:170157.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 170164[91:Res:170162.0,61.1] always3(s46) || -> . % 76.16/76.37 170165[91:SSi:170164.0,78272.0,78276.0,165538.0,170094.0,170148.0] || -> . % 76.16/76.37 170166[91:Spt:170165.0,170157.0,170162.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 170167[91:Spt:170165.0,170157.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 170171[91:Res:170167.0,61.1] always3(s47) || -> . % 76.16/76.37 170172[91:SSi:170171.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 170173[89:Spt:170172.0,170093.0,170094.0] || until2p7(s46)*+ -> . % 76.16/76.37 170174[89:Spt:170172.0,170093.1] || -> node4(s45)*. % 76.16/76.37 170176[89:MRR:783.0,170174.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 170179[89:Res:53.1,170176.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 170181[90:Spt:170179.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 170183[90:Res:170181.0,61.1] always3(s45) || -> . % 76.16/76.37 170184[90:SSi:170183.0,78268.0,78271.0,165537.0,170092.0,170174.0] || -> . % 76.16/76.37 170185[90:Spt:170184.0,170179.0,170181.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 170186[90:Spt:170184.0,170179.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 170190[90:Res:170186.0,61.1] always3(s46) || -> . % 76.16/76.37 170191[90:SSi:170190.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 170192[88:Spt:170191.0,170091.0,170092.0] || until2p7(s45)*+ -> . % 76.16/76.37 170193[88:Spt:170191.0,170091.1] || -> node4(s44)*. % 76.16/76.37 170195[88:MRR:786.0,170193.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 170198[88:Res:53.1,170195.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 170200[89:Spt:170198.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 170202[89:Res:170200.0,61.1] always3(s44) || -> . % 76.16/76.37 170203[89:SSi:170202.0,78263.0,78267.0,165536.0,170090.0,170193.0] || -> . % 76.16/76.37 170204[89:Spt:170203.0,170198.0,170200.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 170205[89:Spt:170203.0,170198.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 170209[89:Res:170205.0,61.1] always3(s45) || -> . % 76.16/76.37 170210[89:SSi:170209.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 170211[87:Spt:170210.0,170089.0,170090.0] || until2p7(s44)*+ -> . % 76.16/76.37 170212[87:Spt:170210.0,170089.1] || -> node4(s43)*. % 76.16/76.37 170214[87:MRR:789.0,170212.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 170217[87:Res:53.1,170214.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 170219[88:Spt:170217.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 170221[88:Res:170219.0,61.1] always3(s43) || -> . % 76.16/76.37 170222[88:SSi:170221.0,78259.0,78262.0,165535.0,170088.0,170212.0] || -> . % 76.16/76.37 170223[88:Spt:170222.0,170217.0,170219.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 170224[88:Spt:170222.0,170217.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 170228[88:Res:170224.0,61.1] always3(s44) || -> . % 76.16/76.37 170229[88:SSi:170228.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 170230[86:Spt:170229.0,170087.0,170088.0] || until2p7(s43)*+ -> . % 76.16/76.37 170231[86:Spt:170229.0,170087.1] || -> node4(s42)*. % 76.16/76.37 170233[86:MRR:792.0,170231.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 170236[86:Res:53.1,170233.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 170241[87:Spt:170236.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 170243[87:Res:170241.0,61.1] always3(s42) || -> . % 76.16/76.37 170244[87:SSi:170243.0,78254.0,78258.0,165534.0,170086.0,170231.0] || -> . % 76.16/76.37 170245[87:Spt:170244.0,170236.0,170241.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 170246[87:Spt:170244.0,170236.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 170250[87:Res:170246.0,61.1] always3(s43) || -> . % 76.16/76.37 170251[87:SSi:170250.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 170252[85:Spt:170251.0,170085.0,170086.0] || until2p7(s42)*+ -> . % 76.16/76.37 170253[85:Spt:170251.0,170085.1] || -> node4(s41)*. % 76.16/76.37 170255[85:MRR:795.0,170253.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 170258[85:Res:53.1,170255.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 170260[86:Spt:170258.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 170262[86:Res:170260.0,61.1] always3(s41) || -> . % 76.16/76.37 170263[86:SSi:170262.0,78250.0,78253.0,165533.0,170084.0,170253.0] || -> . % 76.16/76.37 170264[86:Spt:170263.0,170258.0,170260.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 170265[86:Spt:170263.0,170258.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 170269[86:Res:170265.0,61.1] always3(s42) || -> . % 76.16/76.37 170270[86:SSi:170269.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 170271[84:Spt:170270.0,170083.0,170084.0] || until2p7(s41)*+ -> . % 76.16/76.37 170272[84:Spt:170270.0,170083.1] || -> node4(s40)*. % 76.16/76.37 170274[84:MRR:798.0,170272.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 170277[84:Res:53.1,170274.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 170279[85:Spt:170277.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 170281[85:Res:170279.0,61.1] always3(s40) || -> . % 76.16/76.37 170282[85:SSi:170281.0,78245.0,78249.0,165532.0,170082.0,170272.0] || -> . % 76.16/76.37 170283[85:Spt:170282.0,170277.0,170279.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 170284[85:Spt:170282.0,170277.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 170288[85:Res:170284.0,61.1] always3(s41) || -> . % 76.16/76.37 170289[85:SSi:170288.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 170290[83:Spt:170289.0,170081.0,170082.0] || until2p7(s40)*+ -> . % 76.16/76.37 170291[83:Spt:170289.0,170081.1] || -> node4(s39)*. % 76.16/76.37 170293[83:MRR:801.0,170291.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 170296[83:Res:53.1,170293.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 170298[84:Spt:170296.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 170300[84:Res:170298.0,61.1] always3(s39) || -> . % 76.16/76.37 170301[84:SSi:170300.0,78241.0,78244.0,165531.0,170080.0,170291.0] || -> . % 76.16/76.37 170302[84:Spt:170301.0,170296.0,170298.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 170303[84:Spt:170301.0,170296.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 170307[84:Res:170303.0,61.1] always3(s40) || -> . % 76.16/76.37 170308[84:SSi:170307.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 170309[82:Spt:170308.0,170079.0,170080.0] || until2p7(s39)*+ -> . % 76.16/76.37 170310[82:Spt:170308.0,170079.1] || -> node4(s38)*. % 76.16/76.37 170312[82:MRR:804.0,170310.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 170315[82:Res:53.1,170312.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 170320[83:Spt:170315.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 170322[83:Res:170320.0,61.1] always3(s38) || -> . % 76.16/76.37 170323[83:SSi:170322.0,78236.0,78240.0,165530.0,170078.0,170310.0] || -> . % 76.16/76.37 170324[83:Spt:170323.0,170315.0,170320.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 170325[83:Spt:170323.0,170315.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 170329[83:Res:170325.0,61.1] always3(s39) || -> . % 76.16/76.37 170330[83:SSi:170329.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 170331[81:Spt:170330.0,170077.0,170078.0] || until2p7(s38)*+ -> . % 76.16/76.37 170332[81:Spt:170330.0,170077.1] || -> node4(s37)*. % 76.16/76.37 170334[81:MRR:807.0,170332.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 170337[81:Res:53.1,170334.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 170339[82:Spt:170337.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 170341[82:Res:170339.0,61.1] always3(s37) || -> . % 76.16/76.37 170342[82:SSi:170341.0,78232.0,78235.0,165529.0,170076.0,170332.0] || -> . % 76.16/76.37 170343[82:Spt:170342.0,170337.0,170339.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 170344[82:Spt:170342.0,170337.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 170348[82:Res:170344.0,61.1] always3(s38) || -> . % 76.16/76.37 170349[82:SSi:170348.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 170350[80:Spt:170349.0,170075.0,170076.0] || until2p7(s37)*+ -> . % 76.16/76.37 170351[80:Spt:170349.0,170075.1] || -> node4(s36)*. % 76.16/76.37 170353[80:MRR:810.0,170351.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 170356[80:Res:53.1,170353.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 170358[81:Spt:170356.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 170360[81:Res:170358.0,61.1] always3(s36) || -> . % 76.16/76.37 170361[81:SSi:170360.0,78227.0,78231.0,165528.0,170074.0,170351.0] || -> . % 76.16/76.37 170362[81:Spt:170361.0,170356.0,170358.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 170363[81:Spt:170361.0,170356.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 170367[81:Res:170363.0,61.1] always3(s37) || -> . % 76.16/76.37 170368[81:SSi:170367.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 170369[79:Spt:170368.0,170073.0,170074.0] || until2p7(s36)*+ -> . % 76.16/76.37 170370[79:Spt:170368.0,170073.1] || -> node4(s35)*. % 76.16/76.37 170372[79:MRR:813.0,170370.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 170375[79:Res:53.1,170372.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 170377[80:Spt:170375.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 170379[80:Res:170377.0,61.1] always3(s35) || -> . % 76.16/76.37 170380[80:SSi:170379.0,78223.0,78226.0,165527.0,170072.0,170370.0] || -> . % 76.16/76.37 170381[80:Spt:170380.0,170375.0,170377.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 170382[80:Spt:170380.0,170375.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 170386[80:Res:170382.0,61.1] always3(s36) || -> . % 76.16/76.37 170387[80:SSi:170386.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 170388[78:Spt:170387.0,170071.0,170072.0] || until2p7(s35)*+ -> . % 76.16/76.37 170389[78:Spt:170387.0,170071.1] || -> node4(s34)*. % 76.16/76.37 170391[78:MRR:816.0,170389.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 170394[78:Res:53.1,170391.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 170399[79:Spt:170394.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 170401[79:Res:170399.0,61.1] always3(s34) || -> . % 76.16/76.37 170402[79:SSi:170401.0,78218.0,78222.0,165526.0,170070.0,170389.0] || -> . % 76.16/76.37 170403[79:Spt:170402.0,170394.0,170399.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 170404[79:Spt:170402.0,170394.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 170408[79:Res:170404.0,61.1] always3(s35) || -> . % 76.16/76.37 170409[79:SSi:170408.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 170410[77:Spt:170409.0,170069.0,170070.0] || until2p7(s34)*+ -> . % 76.16/76.37 170411[77:Spt:170409.0,170069.1] || -> node4(s33)*. % 76.16/76.37 170413[77:MRR:819.0,170411.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 170416[77:Res:53.1,170413.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 170418[78:Spt:170416.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 170420[78:Res:170418.0,61.1] always3(s33) || -> . % 76.16/76.37 170421[78:SSi:170420.0,78214.0,78217.0,165525.0,170068.0,170411.0] || -> . % 76.16/76.37 170422[78:Spt:170421.0,170416.0,170418.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 170423[78:Spt:170421.0,170416.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 170427[78:Res:170423.0,61.1] always3(s34) || -> . % 76.16/76.37 170428[78:SSi:170427.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 170429[76:Spt:170428.0,170067.0,170068.0] || until2p7(s33)*+ -> . % 76.16/76.37 170430[76:Spt:170428.0,170067.1] || -> node4(s32)*. % 76.16/76.37 170432[76:MRR:822.0,170430.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 170435[76:Res:53.1,170432.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 170437[77:Spt:170435.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 170439[77:Res:170437.0,61.1] always3(s32) || -> . % 76.16/76.37 170440[77:SSi:170439.0,78209.0,78213.0,165524.0,170066.0,170430.0] || -> . % 76.16/76.37 170441[77:Spt:170440.0,170435.0,170437.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 170442[77:Spt:170440.0,170435.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 170446[77:Res:170442.0,61.1] always3(s33) || -> . % 76.16/76.37 170447[77:SSi:170446.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 170448[75:Spt:170447.0,170065.0,170066.0] || until2p7(s32)*+ -> . % 76.16/76.37 170449[75:Spt:170447.0,170065.1] || -> node4(s31)*. % 76.16/76.37 170451[75:MRR:825.0,170449.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 170454[75:Res:53.1,170451.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 170456[75:MRR:170454.0,170055.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 170458[75:Res:170456.0,61.1] always3(s32) || -> . % 76.16/76.37 170459[75:SSi:170458.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 170460[73:Spt:170459.0,169979.0,169982.0] || trans(s49,s31)*+ -> . % 76.16/76.37 170461[73:Spt:170459.0,169979.1,169979.2,169979.3,169979.4,169979.5,169979.6,169979.7,169979.8,169979.9,169979.10,169979.11,169979.12,169979.13,169979.14,169979.15,169979.16,169979.17,169979.18,169979.19,169979.20,169979.21,169979.22,169979.23,169979.24,169979.25,169979.26] || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 170463[73:MRR:169981.1,170460.0] xuntil6(s49) || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 170464[74:Spt:170461.0] || -> trans(s49,s30)*. % 76.16/76.37 170465[74:Res:170464.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s30)*. % 76.16/76.37 170467[74:Res:170464.0,60.0] || -> node2(s49,s30)*. % 76.16/76.37 170468[74:SSi:170465.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s30)*. % 76.16/76.37 170469[74:Res:170467.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 170536[74:SoR:170469.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 170538[74:SoR:170536.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)* xuntil6(s49). % 76.16/76.37 170539[74:SSi:170538.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s30,c_busy)* xuntil6(s49). % 76.16/76.37 170540[75:Spt:170539.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 170542[75:Res:170540.0,61.1] always3(s30) || -> . % 76.16/76.37 170543[75:SSi:170542.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 170544[75:Spt:170543.0,170539.1,170540.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.16/76.37 170545[75:Spt:170543.0,170539.0,170539.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 170549[75:MRR:170536.2,170544.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 170550[75:Res:53.1,170545.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 170552[75:MRR:170550.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 170553[75:MRR:170468.0,170552.0] || -> until2p7(s30)*. % 76.16/76.37 170554[75:MRR:226.0,170553.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 170555[76:Spt:170554.0] || -> until2p7(s31)*. % 76.16/76.37 170556[76:MRR:227.0,170555.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 170557[77:Spt:170556.0] || -> until2p7(s32)*. % 76.16/76.37 170558[77:MRR:228.0,170557.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 170559[78:Spt:170558.0] || -> until2p7(s33)*. % 76.16/76.37 170560[78:MRR:229.0,170559.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 170561[79:Spt:170560.0] || -> until2p7(s34)*. % 76.16/76.37 170562[79:MRR:230.0,170561.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 170563[80:Spt:170562.0] || -> until2p7(s35)*. % 76.16/76.37 170564[80:MRR:231.0,170563.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 170565[81:Spt:170564.0] || -> until2p7(s36)*. % 76.16/76.37 170566[81:MRR:232.0,170565.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 170567[82:Spt:170566.0] || -> until2p7(s37)*. % 76.16/76.37 170568[82:MRR:235.0,170567.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 170569[83:Spt:170568.0] || -> until2p7(s38)*. % 76.16/76.37 170570[83:MRR:236.0,170569.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 170571[84:Spt:170570.0] || -> until2p7(s39)*. % 76.16/76.37 170572[84:MRR:237.0,170571.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 170573[85:Spt:170572.0] || -> until2p7(s40)*. % 76.16/76.37 170574[85:MRR:238.0,170573.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 170575[86:Spt:170574.0] || -> until2p7(s41)*. % 76.16/76.37 170576[86:MRR:239.0,170575.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 170577[87:Spt:170576.0] || -> until2p7(s42)*. % 76.16/76.37 170578[87:MRR:240.0,170577.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 170579[88:Spt:170578.0] || -> until2p7(s43)*. % 76.16/76.37 170580[88:MRR:241.0,170579.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 170581[89:Spt:170580.0] || -> until2p7(s44)*. % 76.16/76.37 170582[89:MRR:539.0,170581.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 170583[90:Spt:170582.0] || -> until2p7(s45)*. % 76.16/76.37 170584[90:MRR:544.0,170583.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 170585[91:Spt:170584.0] || -> until2p7(s46)*. % 76.16/76.37 170586[91:MRR:549.0,170585.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 170587[92:Spt:170586.0] || -> until2p7(s47)*. % 76.16/76.37 170588[92:MRR:554.0,170587.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 170589[93:Spt:170588.0] || -> until2p7(s48)*. % 76.16/76.37 170590[93:MRR:559.0,170589.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 170591[94:Spt:170590.0] || -> until2p7(s49)*. % 76.16/76.37 170592[94:MRR:194.0,170591.0] || -> node4(s49)*. % 76.16/76.37 170593[94:MRR:170549.0,170592.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 170594[94:Res:53.1,170593.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 170596[94:MRR:170594.0,78381.0] || -> . % 76.16/76.37 170597[94:Spt:170596.0,170590.0,170591.0] || until2p7(s49)*+ -> . % 76.16/76.37 170598[94:Spt:170596.0,170590.1] || -> node4(s48)*. % 76.16/76.37 170599[94:MRR:78384.0,170598.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 170602[94:Res:53.1,170599.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 170605[94:Res:170602.0,61.1] always3(s48) || -> . % 76.16/76.37 170606[94:SSi:170605.0,78281.0,78387.0,165540.0,170589.0,170598.0] || -> . % 76.16/76.37 170607[93:Spt:170606.0,170588.0,170589.0] || until2p7(s48)*+ -> . % 76.16/76.37 170608[93:Spt:170606.0,170588.1] || -> node4(s47)*. % 76.16/76.37 170610[93:MRR:777.0,170608.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 170625[93:Res:53.1,170610.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 170627[94:Spt:170625.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 170629[94:Res:170627.0,61.1] always3(s47) || -> . % 76.16/76.37 170630[94:SSi:170629.0,78277.0,78280.0,165539.0,170587.0,170608.0] || -> . % 76.16/76.37 170631[94:Spt:170630.0,170625.0,170627.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 170632[94:Spt:170630.0,170625.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 170636[94:Res:170632.0,61.1] always3(s48) || -> . % 76.16/76.37 170637[94:SSi:170636.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 170638[92:Spt:170637.0,170586.0,170587.0] || until2p7(s47)*+ -> . % 76.16/76.37 170639[92:Spt:170637.0,170586.1] || -> node4(s46)*. % 76.16/76.37 170641[92:MRR:780.0,170639.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 170651[92:Res:53.1,170641.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 170653[93:Spt:170651.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 170655[93:Res:170653.0,61.1] always3(s46) || -> . % 76.16/76.37 170656[93:SSi:170655.0,78272.0,78276.0,165538.0,170585.0,170639.0] || -> . % 76.16/76.37 170657[93:Spt:170656.0,170651.0,170653.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 170658[93:Spt:170656.0,170651.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 170662[93:Res:170658.0,61.1] always3(s47) || -> . % 76.16/76.37 170663[93:SSi:170662.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 170664[91:Spt:170663.0,170584.0,170585.0] || until2p7(s46)*+ -> . % 76.16/76.37 170665[91:Spt:170663.0,170584.1] || -> node4(s45)*. % 76.16/76.37 170667[91:MRR:783.0,170665.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 170670[91:Res:53.1,170667.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 170672[92:Spt:170670.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 170674[92:Res:170672.0,61.1] always3(s45) || -> . % 76.16/76.37 170675[92:SSi:170674.0,78268.0,78271.0,165537.0,170583.0,170665.0] || -> . % 76.16/76.37 170676[92:Spt:170675.0,170670.0,170672.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 170677[92:Spt:170675.0,170670.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 170681[92:Res:170677.0,61.1] always3(s46) || -> . % 76.16/76.37 170682[92:SSi:170681.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 170683[90:Spt:170682.0,170582.0,170583.0] || until2p7(s45)*+ -> . % 76.16/76.37 170684[90:Spt:170682.0,170582.1] || -> node4(s44)*. % 76.16/76.37 170686[90:MRR:786.0,170684.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 170689[90:Res:53.1,170686.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 170691[91:Spt:170689.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 170693[91:Res:170691.0,61.1] always3(s44) || -> . % 76.16/76.37 170694[91:SSi:170693.0,78263.0,78267.0,165536.0,170581.0,170684.0] || -> . % 76.16/76.37 170695[91:Spt:170694.0,170689.0,170691.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 170696[91:Spt:170694.0,170689.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 170700[91:Res:170696.0,61.1] always3(s45) || -> . % 76.16/76.37 170701[91:SSi:170700.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 170702[89:Spt:170701.0,170580.0,170581.0] || until2p7(s44)*+ -> . % 76.16/76.37 170703[89:Spt:170701.0,170580.1] || -> node4(s43)*. % 76.16/76.37 170705[89:MRR:789.0,170703.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 170708[89:Res:53.1,170705.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 170713[90:Spt:170708.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 170715[90:Res:170713.0,61.1] always3(s43) || -> . % 76.16/76.37 170716[90:SSi:170715.0,78259.0,78262.0,165535.0,170579.0,170703.0] || -> . % 76.16/76.37 170717[90:Spt:170716.0,170708.0,170713.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 170718[90:Spt:170716.0,170708.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 170722[90:Res:170718.0,61.1] always3(s44) || -> . % 76.16/76.37 170723[90:SSi:170722.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 170724[88:Spt:170723.0,170578.0,170579.0] || until2p7(s43)*+ -> . % 76.16/76.37 170725[88:Spt:170723.0,170578.1] || -> node4(s42)*. % 76.16/76.37 170727[88:MRR:792.0,170725.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 170730[88:Res:53.1,170727.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 170732[89:Spt:170730.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 170734[89:Res:170732.0,61.1] always3(s42) || -> . % 76.16/76.37 170735[89:SSi:170734.0,78254.0,78258.0,165534.0,170577.0,170725.0] || -> . % 76.16/76.37 170736[89:Spt:170735.0,170730.0,170732.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 170737[89:Spt:170735.0,170730.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 170741[89:Res:170737.0,61.1] always3(s43) || -> . % 76.16/76.37 170742[89:SSi:170741.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 170743[87:Spt:170742.0,170576.0,170577.0] || until2p7(s42)*+ -> . % 76.16/76.37 170744[87:Spt:170742.0,170576.1] || -> node4(s41)*. % 76.16/76.37 170746[87:MRR:795.0,170744.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 170749[87:Res:53.1,170746.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 170751[88:Spt:170749.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 170753[88:Res:170751.0,61.1] always3(s41) || -> . % 76.16/76.37 170754[88:SSi:170753.0,78250.0,78253.0,165533.0,170575.0,170744.0] || -> . % 76.16/76.37 170755[88:Spt:170754.0,170749.0,170751.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 170756[88:Spt:170754.0,170749.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 170760[88:Res:170756.0,61.1] always3(s42) || -> . % 76.16/76.37 170761[88:SSi:170760.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 170762[86:Spt:170761.0,170574.0,170575.0] || until2p7(s41)*+ -> . % 76.16/76.37 170763[86:Spt:170761.0,170574.1] || -> node4(s40)*. % 76.16/76.37 170765[86:MRR:798.0,170763.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 170768[86:Res:53.1,170765.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 170770[87:Spt:170768.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 170772[87:Res:170770.0,61.1] always3(s40) || -> . % 76.16/76.37 170773[87:SSi:170772.0,78245.0,78249.0,165532.0,170573.0,170763.0] || -> . % 76.16/76.37 170774[87:Spt:170773.0,170768.0,170770.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 170775[87:Spt:170773.0,170768.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 170779[87:Res:170775.0,61.1] always3(s41) || -> . % 76.16/76.37 170780[87:SSi:170779.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 170781[85:Spt:170780.0,170572.0,170573.0] || until2p7(s40)*+ -> . % 76.16/76.37 170782[85:Spt:170780.0,170572.1] || -> node4(s39)*. % 76.16/76.37 170784[85:MRR:801.0,170782.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 170787[85:Res:53.1,170784.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 170792[86:Spt:170787.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 170794[86:Res:170792.0,61.1] always3(s39) || -> . % 76.16/76.37 170795[86:SSi:170794.0,78241.0,78244.0,165531.0,170571.0,170782.0] || -> . % 76.16/76.37 170796[86:Spt:170795.0,170787.0,170792.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 170797[86:Spt:170795.0,170787.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 170801[86:Res:170797.0,61.1] always3(s40) || -> . % 76.16/76.37 170802[86:SSi:170801.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 170803[84:Spt:170802.0,170570.0,170571.0] || until2p7(s39)*+ -> . % 76.16/76.37 170804[84:Spt:170802.0,170570.1] || -> node4(s38)*. % 76.16/76.37 170806[84:MRR:804.0,170804.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 170809[84:Res:53.1,170806.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 170811[85:Spt:170809.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 170813[85:Res:170811.0,61.1] always3(s38) || -> . % 76.16/76.37 170814[85:SSi:170813.0,78236.0,78240.0,165530.0,170569.0,170804.0] || -> . % 76.16/76.37 170815[85:Spt:170814.0,170809.0,170811.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 170816[85:Spt:170814.0,170809.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 170820[85:Res:170816.0,61.1] always3(s39) || -> . % 76.16/76.37 170821[85:SSi:170820.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 170822[83:Spt:170821.0,170568.0,170569.0] || until2p7(s38)*+ -> . % 76.16/76.37 170823[83:Spt:170821.0,170568.1] || -> node4(s37)*. % 76.16/76.37 170825[83:MRR:807.0,170823.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 170828[83:Res:53.1,170825.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 170830[84:Spt:170828.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 170832[84:Res:170830.0,61.1] always3(s37) || -> . % 76.16/76.37 170833[84:SSi:170832.0,78232.0,78235.0,165529.0,170567.0,170823.0] || -> . % 76.16/76.37 170834[84:Spt:170833.0,170828.0,170830.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 170835[84:Spt:170833.0,170828.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 170839[84:Res:170835.0,61.1] always3(s38) || -> . % 76.16/76.37 170840[84:SSi:170839.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 170841[82:Spt:170840.0,170566.0,170567.0] || until2p7(s37)*+ -> . % 76.16/76.37 170842[82:Spt:170840.0,170566.1] || -> node4(s36)*. % 76.16/76.37 170844[82:MRR:810.0,170842.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 170847[82:Res:53.1,170844.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 170849[83:Spt:170847.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 170851[83:Res:170849.0,61.1] always3(s36) || -> . % 76.16/76.37 170852[83:SSi:170851.0,78227.0,78231.0,165528.0,170565.0,170842.0] || -> . % 76.16/76.37 170853[83:Spt:170852.0,170847.0,170849.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 170854[83:Spt:170852.0,170847.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 170858[83:Res:170854.0,61.1] always3(s37) || -> . % 76.16/76.37 170859[83:SSi:170858.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 170860[81:Spt:170859.0,170564.0,170565.0] || until2p7(s36)*+ -> . % 76.16/76.37 170861[81:Spt:170859.0,170564.1] || -> node4(s35)*. % 76.16/76.37 170863[81:MRR:813.0,170861.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 170866[81:Res:53.1,170863.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 170871[82:Spt:170866.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 170873[82:Res:170871.0,61.1] always3(s35) || -> . % 76.16/76.37 170874[82:SSi:170873.0,78223.0,78226.0,165527.0,170563.0,170861.0] || -> . % 76.16/76.37 170875[82:Spt:170874.0,170866.0,170871.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 170876[82:Spt:170874.0,170866.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 170880[82:Res:170876.0,61.1] always3(s36) || -> . % 76.16/76.37 170881[82:SSi:170880.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 170882[80:Spt:170881.0,170562.0,170563.0] || until2p7(s35)*+ -> . % 76.16/76.37 170883[80:Spt:170881.0,170562.1] || -> node4(s34)*. % 76.16/76.37 170885[80:MRR:816.0,170883.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 170888[80:Res:53.1,170885.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 170890[81:Spt:170888.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 170892[81:Res:170890.0,61.1] always3(s34) || -> . % 76.16/76.37 170893[81:SSi:170892.0,78218.0,78222.0,165526.0,170561.0,170883.0] || -> . % 76.16/76.37 170894[81:Spt:170893.0,170888.0,170890.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 170895[81:Spt:170893.0,170888.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 170899[81:Res:170895.0,61.1] always3(s35) || -> . % 76.16/76.37 170900[81:SSi:170899.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 170901[79:Spt:170900.0,170560.0,170561.0] || until2p7(s34)*+ -> . % 76.16/76.37 170902[79:Spt:170900.0,170560.1] || -> node4(s33)*. % 76.16/76.37 170904[79:MRR:819.0,170902.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 170907[79:Res:53.1,170904.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 170909[80:Spt:170907.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 170911[80:Res:170909.0,61.1] always3(s33) || -> . % 76.16/76.37 170912[80:SSi:170911.0,78214.0,78217.0,165525.0,170559.0,170902.0] || -> . % 76.16/76.37 170913[80:Spt:170912.0,170907.0,170909.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 170914[80:Spt:170912.0,170907.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 170918[80:Res:170914.0,61.1] always3(s34) || -> . % 76.16/76.37 170919[80:SSi:170918.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 170920[78:Spt:170919.0,170558.0,170559.0] || until2p7(s33)*+ -> . % 76.16/76.37 170921[78:Spt:170919.0,170558.1] || -> node4(s32)*. % 76.16/76.37 170923[78:MRR:822.0,170921.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 170926[78:Res:53.1,170923.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 170928[79:Spt:170926.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 170930[79:Res:170928.0,61.1] always3(s32) || -> . % 76.16/76.37 170931[79:SSi:170930.0,78209.0,78213.0,165524.0,170557.0,170921.0] || -> . % 76.16/76.37 170932[79:Spt:170931.0,170926.0,170928.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 170933[79:Spt:170931.0,170926.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 170937[79:Res:170933.0,61.1] always3(s33) || -> . % 76.16/76.37 170938[79:SSi:170937.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 170939[77:Spt:170938.0,170556.0,170557.0] || until2p7(s32)*+ -> . % 76.16/76.37 170940[77:Spt:170938.0,170556.1] || -> node4(s31)*. % 76.16/76.37 170942[77:MRR:825.0,170940.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 170945[77:Res:53.1,170942.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 170950[78:Spt:170945.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 170952[78:Res:170950.0,61.1] always3(s31) || -> . % 76.16/76.37 170953[78:SSi:170952.0,78205.0,78208.0,165523.0,170555.0,170940.0] || -> . % 76.16/76.37 170954[78:Spt:170953.0,170945.0,170950.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 170955[78:Spt:170953.0,170945.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 170959[78:Res:170955.0,61.1] always3(s32) || -> . % 76.16/76.37 170960[78:SSi:170959.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 170961[76:Spt:170960.0,170554.0,170555.0] || until2p7(s31)*+ -> . % 76.16/76.37 170962[76:Spt:170960.0,170554.1] || -> node4(s30)*. % 76.16/76.37 170964[76:MRR:828.0,170962.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 170967[76:Res:53.1,170964.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 170969[76:MRR:170967.0,170544.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 170971[76:Res:170969.0,61.1] always3(s31) || -> . % 76.16/76.37 170972[76:SSi:170971.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 170973[74:Spt:170972.0,170461.0,170464.0] || trans(s49,s30)*+ -> . % 76.16/76.37 170974[74:Spt:170972.0,170461.1,170461.2,170461.3,170461.4,170461.5,170461.6,170461.7,170461.8,170461.9,170461.10,170461.11,170461.12,170461.13,170461.14,170461.15,170461.16,170461.17,170461.18,170461.19,170461.20,170461.21,170461.22,170461.23,170461.24,170461.25] || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 170976[74:MRR:170463.1,170973.0] xuntil6(s49) || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 170977[75:Spt:170974.0] || -> trans(s49,s29)*. % 76.16/76.37 170978[75:Res:170977.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s29)*. % 76.16/76.37 170980[75:Res:170977.0,60.0] || -> node2(s49,s29)*. % 76.16/76.37 170981[75:SSi:170978.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s29)*. % 76.16/76.37 170982[75:Res:170980.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 171050[75:SoR:170982.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 171052[75:SoR:171050.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.16/76.37 171053[75:SSi:171052.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.16/76.37 171054[76:Spt:171053.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 171056[76:Res:171054.0,61.1] always3(s29) || -> . % 76.16/76.37 171057[76:SSi:171056.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.37 171058[76:Spt:171057.0,171053.1,171054.0] || m_main_v_state(s29,c_busy)*+ -> . % 76.16/76.37 171059[76:Spt:171057.0,171053.0,171053.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 171063[76:MRR:171050.2,171058.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 171064[76:Res:53.1,171059.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 171066[76:MRR:171064.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 171067[76:MRR:170981.0,171066.0] || -> until2p7(s29)*. % 76.16/76.37 171068[76:MRR:225.0,171067.0] || -> until2p7(s30)* node4(s29). % 76.16/76.37 171069[77:Spt:171068.0] || -> until2p7(s30)*. % 76.16/76.37 171070[77:MRR:226.0,171069.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 171071[78:Spt:171070.0] || -> until2p7(s31)*. % 76.16/76.37 171072[78:MRR:227.0,171071.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 171073[79:Spt:171072.0] || -> until2p7(s32)*. % 76.16/76.37 171074[79:MRR:228.0,171073.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 171075[80:Spt:171074.0] || -> until2p7(s33)*. % 76.16/76.37 171076[80:MRR:229.0,171075.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 171077[81:Spt:171076.0] || -> until2p7(s34)*. % 76.16/76.37 171078[81:MRR:230.0,171077.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 171079[82:Spt:171078.0] || -> until2p7(s35)*. % 76.16/76.37 171080[82:MRR:231.0,171079.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 171081[83:Spt:171080.0] || -> until2p7(s36)*. % 76.16/76.37 171082[83:MRR:232.0,171081.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 171083[84:Spt:171082.0] || -> until2p7(s37)*. % 76.16/76.37 171084[84:MRR:235.0,171083.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 171085[85:Spt:171084.0] || -> until2p7(s38)*. % 76.16/76.37 171086[85:MRR:236.0,171085.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 171087[86:Spt:171086.0] || -> until2p7(s39)*. % 76.16/76.37 171088[86:MRR:237.0,171087.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 171089[87:Spt:171088.0] || -> until2p7(s40)*. % 76.16/76.37 171090[87:MRR:238.0,171089.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 171091[88:Spt:171090.0] || -> until2p7(s41)*. % 76.16/76.37 171092[88:MRR:239.0,171091.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 171093[89:Spt:171092.0] || -> until2p7(s42)*. % 76.16/76.37 171094[89:MRR:240.0,171093.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 171095[90:Spt:171094.0] || -> until2p7(s43)*. % 76.16/76.37 171096[90:MRR:241.0,171095.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 171097[91:Spt:171096.0] || -> until2p7(s44)*. % 76.16/76.37 171098[91:MRR:539.0,171097.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 171099[92:Spt:171098.0] || -> until2p7(s45)*. % 76.16/76.37 171100[92:MRR:544.0,171099.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 171101[93:Spt:171100.0] || -> until2p7(s46)*. % 76.16/76.37 171102[93:MRR:549.0,171101.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 171103[94:Spt:171102.0] || -> until2p7(s47)*. % 76.16/76.37 171104[94:MRR:554.0,171103.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 171105[95:Spt:171104.0] || -> until2p7(s48)*. % 76.16/76.37 171106[95:MRR:559.0,171105.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 171107[96:Spt:171106.0] || -> until2p7(s49)*. % 76.16/76.37 171108[96:MRR:194.0,171107.0] || -> node4(s49)*. % 76.16/76.37 171109[96:MRR:171063.0,171108.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 171110[96:Res:53.1,171109.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 171112[96:MRR:171110.0,78381.0] || -> . % 76.16/76.37 171113[96:Spt:171112.0,171106.0,171107.0] || until2p7(s49)*+ -> . % 76.16/76.37 171114[96:Spt:171112.0,171106.1] || -> node4(s48)*. % 76.16/76.37 171115[96:MRR:78384.0,171114.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 171118[96:Res:53.1,171115.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 171121[96:Res:171118.0,61.1] always3(s48) || -> . % 76.16/76.37 171122[96:SSi:171121.0,78281.0,78387.0,165540.0,171105.0,171114.0] || -> . % 76.16/76.37 171123[95:Spt:171122.0,171104.0,171105.0] || until2p7(s48)*+ -> . % 76.16/76.37 171124[95:Spt:171122.0,171104.1] || -> node4(s47)*. % 76.16/76.37 171126[95:MRR:777.0,171124.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 171141[95:Res:53.1,171126.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 171143[96:Spt:171141.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 171145[96:Res:171143.0,61.1] always3(s47) || -> . % 76.16/76.37 171146[96:SSi:171145.0,78277.0,78280.0,165539.0,171103.0,171124.0] || -> . % 76.16/76.37 171147[96:Spt:171146.0,171141.0,171143.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 171148[96:Spt:171146.0,171141.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 171152[96:Res:171148.0,61.1] always3(s48) || -> . % 76.16/76.37 171153[96:SSi:171152.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 171154[94:Spt:171153.0,171102.0,171103.0] || until2p7(s47)*+ -> . % 76.16/76.37 171155[94:Spt:171153.0,171102.1] || -> node4(s46)*. % 76.16/76.37 171157[94:MRR:780.0,171155.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 171167[94:Res:53.1,171157.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 171169[95:Spt:171167.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 171171[95:Res:171169.0,61.1] always3(s46) || -> . % 76.16/76.37 171172[95:SSi:171171.0,78272.0,78276.0,165538.0,171101.0,171155.0] || -> . % 76.16/76.37 171173[95:Spt:171172.0,171167.0,171169.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 171174[95:Spt:171172.0,171167.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 171178[95:Res:171174.0,61.1] always3(s47) || -> . % 76.16/76.37 171179[95:SSi:171178.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 171180[93:Spt:171179.0,171100.0,171101.0] || until2p7(s46)*+ -> . % 76.16/76.37 171181[93:Spt:171179.0,171100.1] || -> node4(s45)*. % 76.16/76.37 171183[93:MRR:783.0,171181.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 171186[93:Res:53.1,171183.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 171188[94:Spt:171186.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 171190[94:Res:171188.0,61.1] always3(s45) || -> . % 76.16/76.37 171191[94:SSi:171190.0,78268.0,78271.0,165537.0,171099.0,171181.0] || -> . % 76.16/76.37 171192[94:Spt:171191.0,171186.0,171188.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 171193[94:Spt:171191.0,171186.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 171197[94:Res:171193.0,61.1] always3(s46) || -> . % 76.16/76.37 171198[94:SSi:171197.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 171199[92:Spt:171198.0,171098.0,171099.0] || until2p7(s45)*+ -> . % 76.16/76.37 171200[92:Spt:171198.0,171098.1] || -> node4(s44)*. % 76.16/76.37 171202[92:MRR:786.0,171200.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 171205[92:Res:53.1,171202.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 171207[93:Spt:171205.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 171209[93:Res:171207.0,61.1] always3(s44) || -> . % 76.16/76.37 171210[93:SSi:171209.0,78263.0,78267.0,165536.0,171097.0,171200.0] || -> . % 76.16/76.37 171211[93:Spt:171210.0,171205.0,171207.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 171212[93:Spt:171210.0,171205.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 171216[93:Res:171212.0,61.1] always3(s45) || -> . % 76.16/76.37 171217[93:SSi:171216.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 171218[91:Spt:171217.0,171096.0,171097.0] || until2p7(s44)*+ -> . % 76.16/76.37 171219[91:Spt:171217.0,171096.1] || -> node4(s43)*. % 76.16/76.37 171221[91:MRR:789.0,171219.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 171224[91:Res:53.1,171221.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 171229[92:Spt:171224.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 171231[92:Res:171229.0,61.1] always3(s43) || -> . % 76.16/76.37 171232[92:SSi:171231.0,78259.0,78262.0,165535.0,171095.0,171219.0] || -> . % 76.16/76.37 171233[92:Spt:171232.0,171224.0,171229.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 171234[92:Spt:171232.0,171224.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 171238[92:Res:171234.0,61.1] always3(s44) || -> . % 76.16/76.37 171239[92:SSi:171238.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 171240[90:Spt:171239.0,171094.0,171095.0] || until2p7(s43)*+ -> . % 76.16/76.37 171241[90:Spt:171239.0,171094.1] || -> node4(s42)*. % 76.16/76.37 171243[90:MRR:792.0,171241.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 171246[90:Res:53.1,171243.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 171248[91:Spt:171246.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 171250[91:Res:171248.0,61.1] always3(s42) || -> . % 76.16/76.37 171251[91:SSi:171250.0,78254.0,78258.0,165534.0,171093.0,171241.0] || -> . % 76.16/76.37 171252[91:Spt:171251.0,171246.0,171248.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 171253[91:Spt:171251.0,171246.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 171257[91:Res:171253.0,61.1] always3(s43) || -> . % 76.16/76.37 171258[91:SSi:171257.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 171259[89:Spt:171258.0,171092.0,171093.0] || until2p7(s42)*+ -> . % 76.16/76.37 171260[89:Spt:171258.0,171092.1] || -> node4(s41)*. % 76.16/76.37 171262[89:MRR:795.0,171260.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 171265[89:Res:53.1,171262.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 171267[90:Spt:171265.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 171269[90:Res:171267.0,61.1] always3(s41) || -> . % 76.16/76.37 171270[90:SSi:171269.0,78250.0,78253.0,165533.0,171091.0,171260.0] || -> . % 76.16/76.37 171271[90:Spt:171270.0,171265.0,171267.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 171272[90:Spt:171270.0,171265.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 171276[90:Res:171272.0,61.1] always3(s42) || -> . % 76.16/76.37 171277[90:SSi:171276.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 171278[88:Spt:171277.0,171090.0,171091.0] || until2p7(s41)*+ -> . % 76.16/76.37 171279[88:Spt:171277.0,171090.1] || -> node4(s40)*. % 76.16/76.37 171281[88:MRR:798.0,171279.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 171284[88:Res:53.1,171281.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 171286[89:Spt:171284.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 171288[89:Res:171286.0,61.1] always3(s40) || -> . % 76.16/76.37 171289[89:SSi:171288.0,78245.0,78249.0,165532.0,171089.0,171279.0] || -> . % 76.16/76.37 171290[89:Spt:171289.0,171284.0,171286.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 171291[89:Spt:171289.0,171284.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 171295[89:Res:171291.0,61.1] always3(s41) || -> . % 76.16/76.37 171296[89:SSi:171295.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 171297[87:Spt:171296.0,171088.0,171089.0] || until2p7(s40)*+ -> . % 76.16/76.37 171298[87:Spt:171296.0,171088.1] || -> node4(s39)*. % 76.16/76.37 171300[87:MRR:801.0,171298.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 171303[87:Res:53.1,171300.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 171308[88:Spt:171303.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 171310[88:Res:171308.0,61.1] always3(s39) || -> . % 76.16/76.37 171311[88:SSi:171310.0,78241.0,78244.0,165531.0,171087.0,171298.0] || -> . % 76.16/76.37 171312[88:Spt:171311.0,171303.0,171308.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 171313[88:Spt:171311.0,171303.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 171317[88:Res:171313.0,61.1] always3(s40) || -> . % 76.16/76.37 171318[88:SSi:171317.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 171319[86:Spt:171318.0,171086.0,171087.0] || until2p7(s39)*+ -> . % 76.16/76.37 171320[86:Spt:171318.0,171086.1] || -> node4(s38)*. % 76.16/76.37 171322[86:MRR:804.0,171320.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 171325[86:Res:53.1,171322.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 171327[87:Spt:171325.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 171329[87:Res:171327.0,61.1] always3(s38) || -> . % 76.16/76.37 171330[87:SSi:171329.0,78236.0,78240.0,165530.0,171085.0,171320.0] || -> . % 76.16/76.37 171331[87:Spt:171330.0,171325.0,171327.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 171332[87:Spt:171330.0,171325.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 171336[87:Res:171332.0,61.1] always3(s39) || -> . % 76.16/76.37 171337[87:SSi:171336.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 171338[85:Spt:171337.0,171084.0,171085.0] || until2p7(s38)*+ -> . % 76.16/76.37 171339[85:Spt:171337.0,171084.1] || -> node4(s37)*. % 76.16/76.37 171341[85:MRR:807.0,171339.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 171344[85:Res:53.1,171341.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 171346[86:Spt:171344.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 171348[86:Res:171346.0,61.1] always3(s37) || -> . % 76.16/76.37 171349[86:SSi:171348.0,78232.0,78235.0,165529.0,171083.0,171339.0] || -> . % 76.16/76.37 171350[86:Spt:171349.0,171344.0,171346.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 171351[86:Spt:171349.0,171344.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 171355[86:Res:171351.0,61.1] always3(s38) || -> . % 76.16/76.37 171356[86:SSi:171355.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 171357[84:Spt:171356.0,171082.0,171083.0] || until2p7(s37)*+ -> . % 76.16/76.37 171358[84:Spt:171356.0,171082.1] || -> node4(s36)*. % 76.16/76.37 171360[84:MRR:810.0,171358.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 171363[84:Res:53.1,171360.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 171365[85:Spt:171363.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 171367[85:Res:171365.0,61.1] always3(s36) || -> . % 76.16/76.37 171368[85:SSi:171367.0,78227.0,78231.0,165528.0,171081.0,171358.0] || -> . % 76.16/76.37 171369[85:Spt:171368.0,171363.0,171365.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 171370[85:Spt:171368.0,171363.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 171374[85:Res:171370.0,61.1] always3(s37) || -> . % 76.16/76.37 171375[85:SSi:171374.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 171376[83:Spt:171375.0,171080.0,171081.0] || until2p7(s36)*+ -> . % 76.16/76.37 171377[83:Spt:171375.0,171080.1] || -> node4(s35)*. % 76.16/76.37 171379[83:MRR:813.0,171377.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 171382[83:Res:53.1,171379.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 171387[84:Spt:171382.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 171389[84:Res:171387.0,61.1] always3(s35) || -> . % 76.16/76.37 171390[84:SSi:171389.0,78223.0,78226.0,165527.0,171079.0,171377.0] || -> . % 76.16/76.37 171391[84:Spt:171390.0,171382.0,171387.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 171392[84:Spt:171390.0,171382.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 171396[84:Res:171392.0,61.1] always3(s36) || -> . % 76.16/76.37 171397[84:SSi:171396.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 171398[82:Spt:171397.0,171078.0,171079.0] || until2p7(s35)*+ -> . % 76.16/76.37 171399[82:Spt:171397.0,171078.1] || -> node4(s34)*. % 76.16/76.37 171401[82:MRR:816.0,171399.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 171404[82:Res:53.1,171401.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 171406[83:Spt:171404.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 171408[83:Res:171406.0,61.1] always3(s34) || -> . % 76.16/76.37 171409[83:SSi:171408.0,78218.0,78222.0,165526.0,171077.0,171399.0] || -> . % 76.16/76.37 171410[83:Spt:171409.0,171404.0,171406.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 171411[83:Spt:171409.0,171404.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 171415[83:Res:171411.0,61.1] always3(s35) || -> . % 76.16/76.37 171416[83:SSi:171415.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 171417[81:Spt:171416.0,171076.0,171077.0] || until2p7(s34)*+ -> . % 76.16/76.37 171418[81:Spt:171416.0,171076.1] || -> node4(s33)*. % 76.16/76.37 171420[81:MRR:819.0,171418.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 171423[81:Res:53.1,171420.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 171425[82:Spt:171423.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 171427[82:Res:171425.0,61.1] always3(s33) || -> . % 76.16/76.37 171428[82:SSi:171427.0,78214.0,78217.0,165525.0,171075.0,171418.0] || -> . % 76.16/76.37 171429[82:Spt:171428.0,171423.0,171425.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 171430[82:Spt:171428.0,171423.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 171434[82:Res:171430.0,61.1] always3(s34) || -> . % 76.16/76.37 171435[82:SSi:171434.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 171436[80:Spt:171435.0,171074.0,171075.0] || until2p7(s33)*+ -> . % 76.16/76.37 171437[80:Spt:171435.0,171074.1] || -> node4(s32)*. % 76.16/76.37 171439[80:MRR:822.0,171437.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 171442[80:Res:53.1,171439.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 171444[81:Spt:171442.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 171446[81:Res:171444.0,61.1] always3(s32) || -> . % 76.16/76.37 171447[81:SSi:171446.0,78209.0,78213.0,165524.0,171073.0,171437.0] || -> . % 76.16/76.37 171448[81:Spt:171447.0,171442.0,171444.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 171449[81:Spt:171447.0,171442.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 171453[81:Res:171449.0,61.1] always3(s33) || -> . % 76.16/76.37 171454[81:SSi:171453.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 171455[79:Spt:171454.0,171072.0,171073.0] || until2p7(s32)*+ -> . % 76.16/76.37 171456[79:Spt:171454.0,171072.1] || -> node4(s31)*. % 76.16/76.37 171458[79:MRR:825.0,171456.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 171461[79:Res:53.1,171458.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 171466[80:Spt:171461.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 171468[80:Res:171466.0,61.1] always3(s31) || -> . % 76.16/76.37 171469[80:SSi:171468.0,78205.0,78208.0,165523.0,171071.0,171456.0] || -> . % 76.16/76.37 171470[80:Spt:171469.0,171461.0,171466.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 171471[80:Spt:171469.0,171461.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 171475[80:Res:171471.0,61.1] always3(s32) || -> . % 76.16/76.37 171476[80:SSi:171475.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 171477[78:Spt:171476.0,171070.0,171071.0] || until2p7(s31)*+ -> . % 76.16/76.37 171478[78:Spt:171476.0,171070.1] || -> node4(s30)*. % 76.16/76.37 171480[78:MRR:828.0,171478.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 171483[78:Res:53.1,171480.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 171485[79:Spt:171483.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 171487[79:Res:171485.0,61.1] always3(s30) || -> . % 76.16/76.37 171488[79:SSi:171487.0,78200.0,78204.0,165522.0,171069.0,171478.0] || -> . % 76.16/76.37 171489[79:Spt:171488.0,171483.0,171485.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.37 171490[79:Spt:171488.0,171483.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 171494[79:Res:171490.0,61.1] always3(s31) || -> . % 76.16/76.37 171495[79:SSi:171494.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 171496[77:Spt:171495.0,171068.0,171069.0] || until2p7(s30)*+ -> . % 76.16/76.37 171497[77:Spt:171495.0,171068.1] || -> node4(s29)*. % 76.16/76.37 171499[77:MRR:831.0,171497.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.37 171502[77:Res:53.1,171499.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.37 171504[77:MRR:171502.0,171058.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 171506[77:Res:171504.0,61.1] always3(s30) || -> . % 76.16/76.37 171507[77:SSi:171506.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 171508[75:Spt:171507.0,170974.0,170977.0] || trans(s49,s29)*+ -> . % 76.16/76.37 171509[75:Spt:171507.0,170974.1,170974.2,170974.3,170974.4,170974.5,170974.6,170974.7,170974.8,170974.9,170974.10,170974.11,170974.12,170974.13,170974.14,170974.15,170974.16,170974.17,170974.18,170974.19,170974.20,170974.21,170974.22,170974.23,170974.24] || -> trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 171511[75:MRR:170976.1,171508.0] xuntil6(s49) || -> trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 171512[76:Spt:171509.0] || -> trans(s49,s28)*. % 76.16/76.37 171513[76:Res:171512.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s28)*. % 76.16/76.37 171515[76:Res:171512.0,60.0] || -> node2(s49,s28)*. % 76.16/76.37 171516[76:SSi:171513.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s28)*. % 76.16/76.37 171517[76:Res:171515.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 171589[76:SoR:171517.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 171591[76:SoR:171589.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)* xuntil6(s49). % 76.16/76.37 171592[76:SSi:171591.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s28,c_busy)* xuntil6(s49). % 76.16/76.37 171593[77:Spt:171592.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 171595[77:Res:171593.0,61.1] always3(s28) || -> . % 76.16/76.37 171596[77:SSi:171595.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.37 171597[77:Spt:171596.0,171592.1,171593.0] || m_main_v_state(s28,c_busy)*+ -> . % 76.16/76.37 171598[77:Spt:171596.0,171592.0,171592.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 171602[77:MRR:171589.2,171597.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 171603[77:Res:53.1,171598.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 171605[77:MRR:171603.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 171606[77:MRR:171516.0,171605.0] || -> until2p7(s28)*. % 76.16/76.37 171607[77:MRR:224.0,171606.0] || -> until2p7(s29)* node4(s28). % 76.16/76.37 171608[78:Spt:171607.0] || -> until2p7(s29)*. % 76.16/76.37 171609[78:MRR:225.0,171608.0] || -> until2p7(s30)* node4(s29). % 76.16/76.37 171610[79:Spt:171609.0] || -> until2p7(s30)*. % 76.16/76.37 171611[79:MRR:226.0,171610.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 171612[80:Spt:171611.0] || -> until2p7(s31)*. % 76.16/76.37 171613[80:MRR:227.0,171612.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 171614[81:Spt:171613.0] || -> until2p7(s32)*. % 76.16/76.37 171615[81:MRR:228.0,171614.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 171616[82:Spt:171615.0] || -> until2p7(s33)*. % 76.16/76.37 171617[82:MRR:229.0,171616.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 171618[83:Spt:171617.0] || -> until2p7(s34)*. % 76.16/76.37 171619[83:MRR:230.0,171618.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 171620[84:Spt:171619.0] || -> until2p7(s35)*. % 76.16/76.37 171621[84:MRR:231.0,171620.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 171622[85:Spt:171621.0] || -> until2p7(s36)*. % 76.16/76.37 171623[85:MRR:232.0,171622.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 171624[86:Spt:171623.0] || -> until2p7(s37)*. % 76.16/76.37 171625[86:MRR:235.0,171624.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 171626[87:Spt:171625.0] || -> until2p7(s38)*. % 76.16/76.37 171627[87:MRR:236.0,171626.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 171628[88:Spt:171627.0] || -> until2p7(s39)*. % 76.16/76.37 171629[88:MRR:237.0,171628.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 171630[89:Spt:171629.0] || -> until2p7(s40)*. % 76.16/76.37 171631[89:MRR:238.0,171630.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 171632[90:Spt:171631.0] || -> until2p7(s41)*. % 76.16/76.37 171633[90:MRR:239.0,171632.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 171634[91:Spt:171633.0] || -> until2p7(s42)*. % 76.16/76.37 171635[91:MRR:240.0,171634.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 171636[92:Spt:171635.0] || -> until2p7(s43)*. % 76.16/76.37 171637[92:MRR:241.0,171636.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 171638[93:Spt:171637.0] || -> until2p7(s44)*. % 76.16/76.37 171639[93:MRR:539.0,171638.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 171640[94:Spt:171639.0] || -> until2p7(s45)*. % 76.16/76.37 171641[94:MRR:544.0,171640.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 171642[95:Spt:171641.0] || -> until2p7(s46)*. % 76.16/76.37 171643[95:MRR:549.0,171642.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 171644[96:Spt:171643.0] || -> until2p7(s47)*. % 76.16/76.37 171645[96:MRR:554.0,171644.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 171646[97:Spt:171645.0] || -> until2p7(s48)*. % 76.16/76.37 171647[97:MRR:559.0,171646.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 171648[98:Spt:171647.0] || -> until2p7(s49)*. % 76.16/76.37 171649[98:MRR:194.0,171648.0] || -> node4(s49)*. % 76.16/76.37 171650[98:MRR:171602.0,171649.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 171654[98:Res:53.1,171650.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 171656[98:MRR:171654.0,78381.0] || -> . % 76.16/76.37 171657[98:Spt:171656.0,171647.0,171648.0] || until2p7(s49)*+ -> . % 76.16/76.37 171658[98:Spt:171656.0,171647.1] || -> node4(s48)*. % 76.16/76.37 171659[98:MRR:78384.0,171658.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 171662[98:Res:53.1,171659.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 171665[98:Res:171662.0,61.1] always3(s48) || -> . % 76.16/76.37 171666[98:SSi:171665.0,78281.0,78387.0,165540.0,171646.0,171658.0] || -> . % 76.16/76.37 171667[97:Spt:171666.0,171645.0,171646.0] || until2p7(s48)*+ -> . % 76.16/76.37 171668[97:Spt:171666.0,171645.1] || -> node4(s47)*. % 76.16/76.37 171670[97:MRR:777.0,171668.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 171682[97:Res:53.1,171670.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 171684[98:Spt:171682.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 171686[98:Res:171684.0,61.1] always3(s47) || -> . % 76.16/76.37 171687[98:SSi:171686.0,78277.0,78280.0,165539.0,171644.0,171668.0] || -> . % 76.16/76.37 171688[98:Spt:171687.0,171682.0,171684.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 171689[98:Spt:171687.0,171682.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 171693[98:Res:171689.0,61.1] always3(s48) || -> . % 76.16/76.37 171694[98:SSi:171693.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 171695[96:Spt:171694.0,171643.0,171644.0] || until2p7(s47)*+ -> . % 76.16/76.37 171696[96:Spt:171694.0,171643.1] || -> node4(s46)*. % 76.16/76.37 171698[96:MRR:780.0,171696.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 171705[96:Res:53.1,171698.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 171710[97:Spt:171705.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 171712[97:Res:171710.0,61.1] always3(s46) || -> . % 76.16/76.37 171713[97:SSi:171712.0,78272.0,78276.0,165538.0,171642.0,171696.0] || -> . % 76.16/76.37 171714[97:Spt:171713.0,171705.0,171710.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 171715[97:Spt:171713.0,171705.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 171719[97:Res:171715.0,61.1] always3(s47) || -> . % 76.16/76.37 171720[97:SSi:171719.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 171721[95:Spt:171720.0,171641.0,171642.0] || until2p7(s46)*+ -> . % 76.16/76.37 171722[95:Spt:171720.0,171641.1] || -> node4(s45)*. % 76.16/76.37 171724[95:MRR:783.0,171722.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 171727[95:Res:53.1,171724.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 171729[96:Spt:171727.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 171731[96:Res:171729.0,61.1] always3(s45) || -> . % 76.16/76.37 171732[96:SSi:171731.0,78268.0,78271.0,165537.0,171640.0,171722.0] || -> . % 76.16/76.37 171733[96:Spt:171732.0,171727.0,171729.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 171734[96:Spt:171732.0,171727.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 171738[96:Res:171734.0,61.1] always3(s46) || -> . % 76.16/76.37 171739[96:SSi:171738.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 171740[94:Spt:171739.0,171639.0,171640.0] || until2p7(s45)*+ -> . % 76.16/76.37 171741[94:Spt:171739.0,171639.1] || -> node4(s44)*. % 76.16/76.37 171743[94:MRR:786.0,171741.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 171746[94:Res:53.1,171743.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 171748[95:Spt:171746.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 171750[95:Res:171748.0,61.1] always3(s44) || -> . % 76.16/76.37 171751[95:SSi:171750.0,78263.0,78267.0,165536.0,171638.0,171741.0] || -> . % 76.16/76.37 171752[95:Spt:171751.0,171746.0,171748.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 171753[95:Spt:171751.0,171746.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 171757[95:Res:171753.0,61.1] always3(s45) || -> . % 76.16/76.37 171758[95:SSi:171757.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 171759[93:Spt:171758.0,171637.0,171638.0] || until2p7(s44)*+ -> . % 76.16/76.37 171760[93:Spt:171758.0,171637.1] || -> node4(s43)*. % 76.16/76.37 171762[93:MRR:789.0,171760.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 171765[93:Res:53.1,171762.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 171767[94:Spt:171765.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 171769[94:Res:171767.0,61.1] always3(s43) || -> . % 76.16/76.37 171770[94:SSi:171769.0,78259.0,78262.0,165535.0,171636.0,171760.0] || -> . % 76.16/76.37 171771[94:Spt:171770.0,171765.0,171767.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 171772[94:Spt:171770.0,171765.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 171776[94:Res:171772.0,61.1] always3(s44) || -> . % 76.16/76.37 171777[94:SSi:171776.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 171778[92:Spt:171777.0,171635.0,171636.0] || until2p7(s43)*+ -> . % 76.16/76.37 171779[92:Spt:171777.0,171635.1] || -> node4(s42)*. % 76.16/76.37 171781[92:MRR:792.0,171779.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 171784[92:Res:53.1,171781.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 171789[93:Spt:171784.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 171791[93:Res:171789.0,61.1] always3(s42) || -> . % 76.16/76.37 171792[93:SSi:171791.0,78254.0,78258.0,165534.0,171634.0,171779.0] || -> . % 76.16/76.37 171793[93:Spt:171792.0,171784.0,171789.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 171794[93:Spt:171792.0,171784.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 171798[93:Res:171794.0,61.1] always3(s43) || -> . % 76.16/76.37 171799[93:SSi:171798.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 171800[91:Spt:171799.0,171633.0,171634.0] || until2p7(s42)*+ -> . % 76.16/76.37 171801[91:Spt:171799.0,171633.1] || -> node4(s41)*. % 76.16/76.37 171803[91:MRR:795.0,171801.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 171806[91:Res:53.1,171803.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 171808[92:Spt:171806.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 171810[92:Res:171808.0,61.1] always3(s41) || -> . % 76.16/76.37 171811[92:SSi:171810.0,78250.0,78253.0,165533.0,171632.0,171801.0] || -> . % 76.16/76.37 171812[92:Spt:171811.0,171806.0,171808.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 171813[92:Spt:171811.0,171806.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 171817[92:Res:171813.0,61.1] always3(s42) || -> . % 76.16/76.37 171818[92:SSi:171817.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 171819[90:Spt:171818.0,171631.0,171632.0] || until2p7(s41)*+ -> . % 76.16/76.37 171820[90:Spt:171818.0,171631.1] || -> node4(s40)*. % 76.16/76.37 171822[90:MRR:798.0,171820.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 171825[90:Res:53.1,171822.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 171827[91:Spt:171825.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 171829[91:Res:171827.0,61.1] always3(s40) || -> . % 76.16/76.37 171830[91:SSi:171829.0,78245.0,78249.0,165532.0,171630.0,171820.0] || -> . % 76.16/76.37 171831[91:Spt:171830.0,171825.0,171827.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 171832[91:Spt:171830.0,171825.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 171836[91:Res:171832.0,61.1] always3(s41) || -> . % 76.16/76.37 171837[91:SSi:171836.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 171838[89:Spt:171837.0,171629.0,171630.0] || until2p7(s40)*+ -> . % 76.16/76.37 171839[89:Spt:171837.0,171629.1] || -> node4(s39)*. % 76.16/76.37 171841[89:MRR:801.0,171839.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 171844[89:Res:53.1,171841.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 171846[90:Spt:171844.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 171848[90:Res:171846.0,61.1] always3(s39) || -> . % 76.16/76.37 171849[90:SSi:171848.0,78241.0,78244.0,165531.0,171628.0,171839.0] || -> . % 76.16/76.37 171850[90:Spt:171849.0,171844.0,171846.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 171851[90:Spt:171849.0,171844.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 171855[90:Res:171851.0,61.1] always3(s40) || -> . % 76.16/76.37 171856[90:SSi:171855.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 171857[88:Spt:171856.0,171627.0,171628.0] || until2p7(s39)*+ -> . % 76.16/76.37 171858[88:Spt:171856.0,171627.1] || -> node4(s38)*. % 76.16/76.37 171860[88:MRR:804.0,171858.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 171863[88:Res:53.1,171860.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 171868[89:Spt:171863.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 171870[89:Res:171868.0,61.1] always3(s38) || -> . % 76.16/76.37 171871[89:SSi:171870.0,78236.0,78240.0,165530.0,171626.0,171858.0] || -> . % 76.16/76.37 171872[89:Spt:171871.0,171863.0,171868.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 171873[89:Spt:171871.0,171863.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 171877[89:Res:171873.0,61.1] always3(s39) || -> . % 76.16/76.37 171878[89:SSi:171877.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 171879[87:Spt:171878.0,171625.0,171626.0] || until2p7(s38)*+ -> . % 76.16/76.37 171880[87:Spt:171878.0,171625.1] || -> node4(s37)*. % 76.16/76.37 171882[87:MRR:807.0,171880.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 171885[87:Res:53.1,171882.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 171887[88:Spt:171885.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 171889[88:Res:171887.0,61.1] always3(s37) || -> . % 76.16/76.37 171890[88:SSi:171889.0,78232.0,78235.0,165529.0,171624.0,171880.0] || -> . % 76.16/76.37 171891[88:Spt:171890.0,171885.0,171887.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 171892[88:Spt:171890.0,171885.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 171896[88:Res:171892.0,61.1] always3(s38) || -> . % 76.16/76.37 171897[88:SSi:171896.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 171898[86:Spt:171897.0,171623.0,171624.0] || until2p7(s37)*+ -> . % 76.16/76.37 171899[86:Spt:171897.0,171623.1] || -> node4(s36)*. % 76.16/76.37 171901[86:MRR:810.0,171899.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 171904[86:Res:53.1,171901.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 171906[87:Spt:171904.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 171908[87:Res:171906.0,61.1] always3(s36) || -> . % 76.16/76.37 171909[87:SSi:171908.0,78227.0,78231.0,165528.0,171622.0,171899.0] || -> . % 76.16/76.37 171910[87:Spt:171909.0,171904.0,171906.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 171911[87:Spt:171909.0,171904.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 171915[87:Res:171911.0,61.1] always3(s37) || -> . % 76.16/76.37 171916[87:SSi:171915.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 171917[85:Spt:171916.0,171621.0,171622.0] || until2p7(s36)*+ -> . % 76.16/76.37 171918[85:Spt:171916.0,171621.1] || -> node4(s35)*. % 76.16/76.37 171920[85:MRR:813.0,171918.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 171923[85:Res:53.1,171920.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 171925[86:Spt:171923.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 171927[86:Res:171925.0,61.1] always3(s35) || -> . % 76.16/76.37 171928[86:SSi:171927.0,78223.0,78226.0,165527.0,171620.0,171918.0] || -> . % 76.16/76.37 171929[86:Spt:171928.0,171923.0,171925.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 171930[86:Spt:171928.0,171923.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 171934[86:Res:171930.0,61.1] always3(s36) || -> . % 76.16/76.37 171935[86:SSi:171934.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 171936[84:Spt:171935.0,171619.0,171620.0] || until2p7(s35)*+ -> . % 76.16/76.37 171937[84:Spt:171935.0,171619.1] || -> node4(s34)*. % 76.16/76.37 171939[84:MRR:816.0,171937.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 171942[84:Res:53.1,171939.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 171947[85:Spt:171942.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 171949[85:Res:171947.0,61.1] always3(s34) || -> . % 76.16/76.37 171950[85:SSi:171949.0,78218.0,78222.0,165526.0,171618.0,171937.0] || -> . % 76.16/76.37 171951[85:Spt:171950.0,171942.0,171947.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 171952[85:Spt:171950.0,171942.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 171956[85:Res:171952.0,61.1] always3(s35) || -> . % 76.16/76.37 171957[85:SSi:171956.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 171958[83:Spt:171957.0,171617.0,171618.0] || until2p7(s34)*+ -> . % 76.16/76.37 171959[83:Spt:171957.0,171617.1] || -> node4(s33)*. % 76.16/76.37 171961[83:MRR:819.0,171959.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 171964[83:Res:53.1,171961.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 171966[84:Spt:171964.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 171968[84:Res:171966.0,61.1] always3(s33) || -> . % 76.16/76.37 171969[84:SSi:171968.0,78214.0,78217.0,165525.0,171616.0,171959.0] || -> . % 76.16/76.37 171970[84:Spt:171969.0,171964.0,171966.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 171971[84:Spt:171969.0,171964.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 171975[84:Res:171971.0,61.1] always3(s34) || -> . % 76.16/76.37 171976[84:SSi:171975.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 171977[82:Spt:171976.0,171615.0,171616.0] || until2p7(s33)*+ -> . % 76.16/76.37 171978[82:Spt:171976.0,171615.1] || -> node4(s32)*. % 76.16/76.37 171980[82:MRR:822.0,171978.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 171983[82:Res:53.1,171980.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 171985[83:Spt:171983.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 171987[83:Res:171985.0,61.1] always3(s32) || -> . % 76.16/76.37 171988[83:SSi:171987.0,78209.0,78213.0,165524.0,171614.0,171978.0] || -> . % 76.16/76.37 171989[83:Spt:171988.0,171983.0,171985.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 171990[83:Spt:171988.0,171983.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 171994[83:Res:171990.0,61.1] always3(s33) || -> . % 76.16/76.37 171995[83:SSi:171994.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 171996[81:Spt:171995.0,171613.0,171614.0] || until2p7(s32)*+ -> . % 76.16/76.37 171997[81:Spt:171995.0,171613.1] || -> node4(s31)*. % 76.16/76.37 171999[81:MRR:825.0,171997.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 172002[81:Res:53.1,171999.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 172004[82:Spt:172002.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 172006[82:Res:172004.0,61.1] always3(s31) || -> . % 76.16/76.37 172007[82:SSi:172006.0,78205.0,78208.0,165523.0,171612.0,171997.0] || -> . % 76.16/76.37 172008[82:Spt:172007.0,172002.0,172004.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 172009[82:Spt:172007.0,172002.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 172013[82:Res:172009.0,61.1] always3(s32) || -> . % 76.16/76.37 172014[82:SSi:172013.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 172015[80:Spt:172014.0,171611.0,171612.0] || until2p7(s31)*+ -> . % 76.16/76.37 172016[80:Spt:172014.0,171611.1] || -> node4(s30)*. % 76.16/76.37 172018[80:MRR:828.0,172016.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 172021[80:Res:53.1,172018.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 172026[81:Spt:172021.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 172028[81:Res:172026.0,61.1] always3(s30) || -> . % 76.16/76.37 172029[81:SSi:172028.0,78200.0,78204.0,165522.0,171610.0,172016.0] || -> . % 76.16/76.37 172030[81:Spt:172029.0,172021.0,172026.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.37 172031[81:Spt:172029.0,172021.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 172035[81:Res:172031.0,61.1] always3(s31) || -> . % 76.16/76.37 172036[81:SSi:172035.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 172037[79:Spt:172036.0,171609.0,171610.0] || until2p7(s30)*+ -> . % 76.16/76.37 172038[79:Spt:172036.0,171609.1] || -> node4(s29)*. % 76.16/76.37 172040[79:MRR:831.0,172038.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.37 172043[79:Res:53.1,172040.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.37 172045[80:Spt:172043.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 172047[80:Res:172045.0,61.1] always3(s29) || -> . % 76.16/76.37 172048[80:SSi:172047.0,78196.0,78199.0,165521.0,171608.0,172038.0] || -> . % 76.16/76.37 172049[80:Spt:172048.0,172043.0,172045.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.37 172050[80:Spt:172048.0,172043.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 172054[80:Res:172050.0,61.1] always3(s30) || -> . % 76.16/76.37 172055[80:SSi:172054.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 172056[78:Spt:172055.0,171607.0,171608.0] || until2p7(s29)*+ -> . % 76.16/76.37 172057[78:Spt:172055.0,171607.1] || -> node4(s28)*. % 76.16/76.37 172059[78:MRR:834.0,172057.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.37 172062[78:Res:53.1,172059.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.37 172064[78:MRR:172062.0,171597.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 172066[78:Res:172064.0,61.1] always3(s29) || -> . % 76.16/76.37 172067[78:SSi:172066.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.37 172068[76:Spt:172067.0,171509.0,171512.0] || trans(s49,s28)*+ -> . % 76.16/76.37 172069[76:Spt:172067.0,171509.1,171509.2,171509.3,171509.4,171509.5,171509.6,171509.7,171509.8,171509.9,171509.10,171509.11,171509.12,171509.13,171509.14,171509.15,171509.16,171509.17,171509.18,171509.19,171509.20,171509.21,171509.22,171509.23] || -> trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 172071[76:MRR:171511.1,172068.0] xuntil6(s49) || -> trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 172072[77:Spt:172069.0] || -> trans(s49,s27)*. % 76.16/76.37 172073[77:Res:172072.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s27)*. % 76.16/76.37 172075[77:Res:172072.0,60.0] || -> node2(s49,s27)*. % 76.16/76.37 172076[77:SSi:172073.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s27)*. % 76.16/76.37 172077[77:Res:172075.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 172153[77:SoR:172077.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 172155[77:SoR:172153.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)* xuntil6(s49). % 76.16/76.37 172156[77:SSi:172155.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s27,c_busy)* xuntil6(s49). % 76.16/76.37 172157[78:Spt:172156.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 172159[78:Res:172157.0,61.1] always3(s27) || -> . % 76.16/76.37 172160[78:SSi:172159.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.37 172161[78:Spt:172160.0,172156.1,172157.0] || m_main_v_state(s27,c_busy)*+ -> . % 76.16/76.37 172162[78:Spt:172160.0,172156.0,172156.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 172166[78:MRR:172153.2,172161.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 172167[78:Res:53.1,172162.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 172169[78:MRR:172167.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 172170[78:MRR:172076.0,172169.0] || -> until2p7(s27)*. % 76.16/76.37 172171[78:MRR:223.0,172170.0] || -> until2p7(s28)* node4(s27). % 76.16/76.37 172172[79:Spt:172171.0] || -> until2p7(s28)*. % 76.16/76.37 172173[79:MRR:224.0,172172.0] || -> until2p7(s29)* node4(s28). % 76.16/76.37 172174[80:Spt:172173.0] || -> until2p7(s29)*. % 76.16/76.37 172175[80:MRR:225.0,172174.0] || -> until2p7(s30)* node4(s29). % 76.16/76.37 172176[81:Spt:172175.0] || -> until2p7(s30)*. % 76.16/76.37 172177[81:MRR:226.0,172176.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 172178[82:Spt:172177.0] || -> until2p7(s31)*. % 76.16/76.37 172179[82:MRR:227.0,172178.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 172180[83:Spt:172179.0] || -> until2p7(s32)*. % 76.16/76.37 172181[83:MRR:228.0,172180.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 172182[84:Spt:172181.0] || -> until2p7(s33)*. % 76.16/76.37 172183[84:MRR:229.0,172182.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 172184[85:Spt:172183.0] || -> until2p7(s34)*. % 76.16/76.37 172185[85:MRR:230.0,172184.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 172186[86:Spt:172185.0] || -> until2p7(s35)*. % 76.16/76.37 172187[86:MRR:231.0,172186.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 172188[87:Spt:172187.0] || -> until2p7(s36)*. % 76.16/76.37 172189[87:MRR:232.0,172188.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 172190[88:Spt:172189.0] || -> until2p7(s37)*. % 76.16/76.37 172191[88:MRR:235.0,172190.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 172192[89:Spt:172191.0] || -> until2p7(s38)*. % 76.16/76.37 172193[89:MRR:236.0,172192.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 172194[90:Spt:172193.0] || -> until2p7(s39)*. % 76.16/76.37 172195[90:MRR:237.0,172194.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 172196[91:Spt:172195.0] || -> until2p7(s40)*. % 76.16/76.37 172197[91:MRR:238.0,172196.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 172198[92:Spt:172197.0] || -> until2p7(s41)*. % 76.16/76.37 172199[92:MRR:239.0,172198.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 172200[93:Spt:172199.0] || -> until2p7(s42)*. % 76.16/76.37 172201[93:MRR:240.0,172200.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 172202[94:Spt:172201.0] || -> until2p7(s43)*. % 76.16/76.37 172203[94:MRR:241.0,172202.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 172204[95:Spt:172203.0] || -> until2p7(s44)*. % 76.16/76.37 172205[95:MRR:539.0,172204.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 172206[96:Spt:172205.0] || -> until2p7(s45)*. % 76.16/76.37 172207[96:MRR:544.0,172206.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 172208[97:Spt:172207.0] || -> until2p7(s46)*. % 76.16/76.37 172209[97:MRR:549.0,172208.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 172210[98:Spt:172209.0] || -> until2p7(s47)*. % 76.16/76.37 172211[98:MRR:554.0,172210.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 172212[99:Spt:172211.0] || -> until2p7(s48)*. % 76.16/76.37 172213[99:MRR:559.0,172212.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 172214[100:Spt:172213.0] || -> until2p7(s49)*. % 76.16/76.37 172215[100:MRR:194.0,172214.0] || -> node4(s49)*. % 76.16/76.37 172216[100:MRR:172166.0,172215.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 172217[100:Res:53.1,172216.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 172219[100:MRR:172217.0,78381.0] || -> . % 76.16/76.37 172220[100:Spt:172219.0,172213.0,172214.0] || until2p7(s49)*+ -> . % 76.16/76.37 172221[100:Spt:172219.0,172213.1] || -> node4(s48)*. % 76.16/76.37 172222[100:MRR:78384.0,172221.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 172225[100:Res:53.1,172222.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 172228[100:Res:172225.0,61.1] always3(s48) || -> . % 76.16/76.37 172229[100:SSi:172228.0,78281.0,78387.0,165540.0,172212.0,172221.0] || -> . % 76.16/76.37 172230[99:Spt:172229.0,172211.0,172212.0] || until2p7(s48)*+ -> . % 76.16/76.37 172231[99:Spt:172229.0,172211.1] || -> node4(s47)*. % 76.16/76.37 172233[99:MRR:777.0,172231.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 172248[99:Res:53.1,172233.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 172253[100:Spt:172248.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 172255[100:Res:172253.0,61.1] always3(s47) || -> . % 76.16/76.37 172256[100:SSi:172255.0,78277.0,78280.0,165539.0,172210.0,172231.0] || -> . % 76.16/76.37 172257[100:Spt:172256.0,172248.0,172253.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 172258[100:Spt:172256.0,172248.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 172262[100:Res:172258.0,61.1] always3(s48) || -> . % 76.16/76.37 172263[100:SSi:172262.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 172264[98:Spt:172263.0,172209.0,172210.0] || until2p7(s47)*+ -> . % 76.16/76.37 172265[98:Spt:172263.0,172209.1] || -> node4(s46)*. % 76.16/76.37 172267[98:MRR:780.0,172265.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 172274[98:Res:53.1,172267.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 172276[99:Spt:172274.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 172278[99:Res:172276.0,61.1] always3(s46) || -> . % 76.16/76.37 172279[99:SSi:172278.0,78272.0,78276.0,165538.0,172208.0,172265.0] || -> . % 76.16/76.37 172280[99:Spt:172279.0,172274.0,172276.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 172281[99:Spt:172279.0,172274.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 172285[99:Res:172281.0,61.1] always3(s47) || -> . % 76.16/76.37 172286[99:SSi:172285.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 172287[97:Spt:172286.0,172207.0,172208.0] || until2p7(s46)*+ -> . % 76.16/76.37 172288[97:Spt:172286.0,172207.1] || -> node4(s45)*. % 76.16/76.37 172290[97:MRR:783.0,172288.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 172293[97:Res:53.1,172290.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 172298[98:Spt:172293.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 172300[98:Res:172298.0,61.1] always3(s45) || -> . % 76.16/76.37 172301[98:SSi:172300.0,78268.0,78271.0,165537.0,172206.0,172288.0] || -> . % 76.16/76.37 172302[98:Spt:172301.0,172293.0,172298.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 172303[98:Spt:172301.0,172293.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 172307[98:Res:172303.0,61.1] always3(s46) || -> . % 76.16/76.37 172308[98:SSi:172307.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 172309[96:Spt:172308.0,172205.0,172206.0] || until2p7(s45)*+ -> . % 76.16/76.37 172310[96:Spt:172308.0,172205.1] || -> node4(s44)*. % 76.16/76.37 172312[96:MRR:786.0,172310.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 172315[96:Res:53.1,172312.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 172317[97:Spt:172315.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 172319[97:Res:172317.0,61.1] always3(s44) || -> . % 76.16/76.37 172320[97:SSi:172319.0,78263.0,78267.0,165536.0,172204.0,172310.0] || -> . % 76.16/76.37 172321[97:Spt:172320.0,172315.0,172317.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 172322[97:Spt:172320.0,172315.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 172326[97:Res:172322.0,61.1] always3(s45) || -> . % 76.16/76.37 172327[97:SSi:172326.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 172328[95:Spt:172327.0,172203.0,172204.0] || until2p7(s44)*+ -> . % 76.16/76.37 172329[95:Spt:172327.0,172203.1] || -> node4(s43)*. % 76.16/76.37 172331[95:MRR:789.0,172329.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 172334[95:Res:53.1,172331.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 172336[96:Spt:172334.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 172338[96:Res:172336.0,61.1] always3(s43) || -> . % 76.16/76.37 172339[96:SSi:172338.0,78259.0,78262.0,165535.0,172202.0,172329.0] || -> . % 76.16/76.37 172340[96:Spt:172339.0,172334.0,172336.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 172341[96:Spt:172339.0,172334.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 172345[96:Res:172341.0,61.1] always3(s44) || -> . % 76.16/76.37 172346[96:SSi:172345.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 172347[94:Spt:172346.0,172201.0,172202.0] || until2p7(s43)*+ -> . % 76.16/76.37 172348[94:Spt:172346.0,172201.1] || -> node4(s42)*. % 76.16/76.37 172350[94:MRR:792.0,172348.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 172353[94:Res:53.1,172350.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 172355[95:Spt:172353.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 172357[95:Res:172355.0,61.1] always3(s42) || -> . % 76.16/76.37 172358[95:SSi:172357.0,78254.0,78258.0,165534.0,172200.0,172348.0] || -> . % 76.16/76.37 172359[95:Spt:172358.0,172353.0,172355.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 172360[95:Spt:172358.0,172353.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 172364[95:Res:172360.0,61.1] always3(s43) || -> . % 76.16/76.37 172365[95:SSi:172364.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 172366[93:Spt:172365.0,172199.0,172200.0] || until2p7(s42)*+ -> . % 76.16/76.37 172367[93:Spt:172365.0,172199.1] || -> node4(s41)*. % 76.16/76.37 172369[93:MRR:795.0,172367.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 172372[93:Res:53.1,172369.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 172377[94:Spt:172372.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 172379[94:Res:172377.0,61.1] always3(s41) || -> . % 76.16/76.37 172380[94:SSi:172379.0,78250.0,78253.0,165533.0,172198.0,172367.0] || -> . % 76.16/76.37 172381[94:Spt:172380.0,172372.0,172377.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 172382[94:Spt:172380.0,172372.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 172386[94:Res:172382.0,61.1] always3(s42) || -> . % 76.16/76.37 172387[94:SSi:172386.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 172388[92:Spt:172387.0,172197.0,172198.0] || until2p7(s41)*+ -> . % 76.16/76.37 172389[92:Spt:172387.0,172197.1] || -> node4(s40)*. % 76.16/76.37 172391[92:MRR:798.0,172389.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 172394[92:Res:53.1,172391.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 172396[93:Spt:172394.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 172398[93:Res:172396.0,61.1] always3(s40) || -> . % 76.16/76.37 172399[93:SSi:172398.0,78245.0,78249.0,165532.0,172196.0,172389.0] || -> . % 76.16/76.37 172400[93:Spt:172399.0,172394.0,172396.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 172401[93:Spt:172399.0,172394.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 172405[93:Res:172401.0,61.1] always3(s41) || -> . % 76.16/76.37 172406[93:SSi:172405.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 172407[91:Spt:172406.0,172195.0,172196.0] || until2p7(s40)*+ -> . % 76.16/76.37 172408[91:Spt:172406.0,172195.1] || -> node4(s39)*. % 76.16/76.37 172410[91:MRR:801.0,172408.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 172413[91:Res:53.1,172410.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 172415[92:Spt:172413.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 172417[92:Res:172415.0,61.1] always3(s39) || -> . % 76.16/76.37 172418[92:SSi:172417.0,78241.0,78244.0,165531.0,172194.0,172408.0] || -> . % 76.16/76.37 172419[92:Spt:172418.0,172413.0,172415.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 172420[92:Spt:172418.0,172413.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 172424[92:Res:172420.0,61.1] always3(s40) || -> . % 76.16/76.37 172425[92:SSi:172424.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 172426[90:Spt:172425.0,172193.0,172194.0] || until2p7(s39)*+ -> . % 76.16/76.37 172427[90:Spt:172425.0,172193.1] || -> node4(s38)*. % 76.16/76.37 172429[90:MRR:804.0,172427.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 172432[90:Res:53.1,172429.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 172434[91:Spt:172432.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 172436[91:Res:172434.0,61.1] always3(s38) || -> . % 76.16/76.37 172437[91:SSi:172436.0,78236.0,78240.0,165530.0,172192.0,172427.0] || -> . % 76.16/76.37 172438[91:Spt:172437.0,172432.0,172434.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 172439[91:Spt:172437.0,172432.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 172443[91:Res:172439.0,61.1] always3(s39) || -> . % 76.16/76.37 172444[91:SSi:172443.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 172445[89:Spt:172444.0,172191.0,172192.0] || until2p7(s38)*+ -> . % 76.16/76.37 172446[89:Spt:172444.0,172191.1] || -> node4(s37)*. % 76.16/76.37 172448[89:MRR:807.0,172446.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 172451[89:Res:53.1,172448.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 172456[90:Spt:172451.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 172458[90:Res:172456.0,61.1] always3(s37) || -> . % 76.16/76.37 172459[90:SSi:172458.0,78232.0,78235.0,165529.0,172190.0,172446.0] || -> . % 76.16/76.37 172460[90:Spt:172459.0,172451.0,172456.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 172461[90:Spt:172459.0,172451.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 172465[90:Res:172461.0,61.1] always3(s38) || -> . % 76.16/76.37 172466[90:SSi:172465.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 172467[88:Spt:172466.0,172189.0,172190.0] || until2p7(s37)*+ -> . % 76.16/76.37 172468[88:Spt:172466.0,172189.1] || -> node4(s36)*. % 76.16/76.37 172470[88:MRR:810.0,172468.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 172473[88:Res:53.1,172470.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 172475[89:Spt:172473.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 172477[89:Res:172475.0,61.1] always3(s36) || -> . % 76.16/76.37 172478[89:SSi:172477.0,78227.0,78231.0,165528.0,172188.0,172468.0] || -> . % 76.16/76.37 172479[89:Spt:172478.0,172473.0,172475.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 172480[89:Spt:172478.0,172473.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 172484[89:Res:172480.0,61.1] always3(s37) || -> . % 76.16/76.37 172485[89:SSi:172484.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 172486[87:Spt:172485.0,172187.0,172188.0] || until2p7(s36)*+ -> . % 76.16/76.37 172487[87:Spt:172485.0,172187.1] || -> node4(s35)*. % 76.16/76.37 172489[87:MRR:813.0,172487.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 172492[87:Res:53.1,172489.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 172494[88:Spt:172492.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 172496[88:Res:172494.0,61.1] always3(s35) || -> . % 76.16/76.37 172497[88:SSi:172496.0,78223.0,78226.0,165527.0,172186.0,172487.0] || -> . % 76.16/76.37 172498[88:Spt:172497.0,172492.0,172494.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 172499[88:Spt:172497.0,172492.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 172503[88:Res:172499.0,61.1] always3(s36) || -> . % 76.16/76.37 172504[88:SSi:172503.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 172505[86:Spt:172504.0,172185.0,172186.0] || until2p7(s35)*+ -> . % 76.16/76.37 172506[86:Spt:172504.0,172185.1] || -> node4(s34)*. % 76.16/76.37 172508[86:MRR:816.0,172506.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 172511[86:Res:53.1,172508.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 172513[87:Spt:172511.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 172515[87:Res:172513.0,61.1] always3(s34) || -> . % 76.16/76.37 172516[87:SSi:172515.0,78218.0,78222.0,165526.0,172184.0,172506.0] || -> . % 76.16/76.37 172517[87:Spt:172516.0,172511.0,172513.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 172518[87:Spt:172516.0,172511.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 172522[87:Res:172518.0,61.1] always3(s35) || -> . % 76.16/76.37 172523[87:SSi:172522.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 172524[85:Spt:172523.0,172183.0,172184.0] || until2p7(s34)*+ -> . % 76.16/76.37 172525[85:Spt:172523.0,172183.1] || -> node4(s33)*. % 76.16/76.37 172527[85:MRR:819.0,172525.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 172530[85:Res:53.1,172527.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 172535[86:Spt:172530.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 172537[86:Res:172535.0,61.1] always3(s33) || -> . % 76.16/76.37 172538[86:SSi:172537.0,78214.0,78217.0,165525.0,172182.0,172525.0] || -> . % 76.16/76.37 172539[86:Spt:172538.0,172530.0,172535.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 172540[86:Spt:172538.0,172530.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 172544[86:Res:172540.0,61.1] always3(s34) || -> . % 76.16/76.37 172545[86:SSi:172544.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 172546[84:Spt:172545.0,172181.0,172182.0] || until2p7(s33)*+ -> . % 76.16/76.37 172547[84:Spt:172545.0,172181.1] || -> node4(s32)*. % 76.16/76.37 172549[84:MRR:822.0,172547.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 172552[84:Res:53.1,172549.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 172554[85:Spt:172552.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 172556[85:Res:172554.0,61.1] always3(s32) || -> . % 76.16/76.37 172557[85:SSi:172556.0,78209.0,78213.0,165524.0,172180.0,172547.0] || -> . % 76.16/76.37 172558[85:Spt:172557.0,172552.0,172554.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 172559[85:Spt:172557.0,172552.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 172563[85:Res:172559.0,61.1] always3(s33) || -> . % 76.16/76.37 172564[85:SSi:172563.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 172565[83:Spt:172564.0,172179.0,172180.0] || until2p7(s32)*+ -> . % 76.16/76.37 172566[83:Spt:172564.0,172179.1] || -> node4(s31)*. % 76.16/76.37 172568[83:MRR:825.0,172566.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 172571[83:Res:53.1,172568.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 172573[84:Spt:172571.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 172575[84:Res:172573.0,61.1] always3(s31) || -> . % 76.16/76.37 172576[84:SSi:172575.0,78205.0,78208.0,165523.0,172178.0,172566.0] || -> . % 76.16/76.37 172577[84:Spt:172576.0,172571.0,172573.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 172578[84:Spt:172576.0,172571.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 172582[84:Res:172578.0,61.1] always3(s32) || -> . % 76.16/76.37 172583[84:SSi:172582.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 172584[82:Spt:172583.0,172177.0,172178.0] || until2p7(s31)*+ -> . % 76.16/76.37 172585[82:Spt:172583.0,172177.1] || -> node4(s30)*. % 76.16/76.37 172587[82:MRR:828.0,172585.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 172590[82:Res:53.1,172587.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 172592[83:Spt:172590.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 172594[83:Res:172592.0,61.1] always3(s30) || -> . % 76.16/76.37 172595[83:SSi:172594.0,78200.0,78204.0,165522.0,172176.0,172585.0] || -> . % 76.16/76.37 172596[83:Spt:172595.0,172590.0,172592.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.37 172597[83:Spt:172595.0,172590.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 172601[83:Res:172597.0,61.1] always3(s31) || -> . % 76.16/76.37 172602[83:SSi:172601.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 172603[81:Spt:172602.0,172175.0,172176.0] || until2p7(s30)*+ -> . % 76.16/76.37 172604[81:Spt:172602.0,172175.1] || -> node4(s29)*. % 76.16/76.37 172606[81:MRR:831.0,172604.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.37 172609[81:Res:53.1,172606.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.37 172614[82:Spt:172609.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 172616[82:Res:172614.0,61.1] always3(s29) || -> . % 76.16/76.37 172617[82:SSi:172616.0,78196.0,78199.0,165521.0,172174.0,172604.0] || -> . % 76.16/76.37 172618[82:Spt:172617.0,172609.0,172614.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.37 172619[82:Spt:172617.0,172609.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 172623[82:Res:172619.0,61.1] always3(s30) || -> . % 76.16/76.37 172624[82:SSi:172623.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 172625[80:Spt:172624.0,172173.0,172174.0] || until2p7(s29)*+ -> . % 76.16/76.37 172626[80:Spt:172624.0,172173.1] || -> node4(s28)*. % 76.16/76.37 172628[80:MRR:834.0,172626.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.37 172631[80:Res:53.1,172628.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.37 172633[81:Spt:172631.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 172635[81:Res:172633.0,61.1] always3(s28) || -> . % 76.16/76.37 172636[81:SSi:172635.0,78191.0,78195.0,165520.0,172172.0,172626.0] || -> . % 76.16/76.37 172637[81:Spt:172636.0,172631.0,172633.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.37 172638[81:Spt:172636.0,172631.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 172642[81:Res:172638.0,61.1] always3(s29) || -> . % 76.16/76.37 172643[81:SSi:172642.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.37 172644[79:Spt:172643.0,172171.0,172172.0] || until2p7(s28)*+ -> . % 76.16/76.37 172645[79:Spt:172643.0,172171.1] || -> node4(s27)*. % 76.16/76.37 172647[79:MRR:837.0,172645.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.37 172650[79:Res:53.1,172647.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.37 172652[79:MRR:172650.0,172161.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 172654[79:Res:172652.0,61.1] always3(s28) || -> . % 76.16/76.37 172655[79:SSi:172654.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.37 172656[77:Spt:172655.0,172069.0,172072.0] || trans(s49,s27)*+ -> . % 76.16/76.37 172657[77:Spt:172655.0,172069.1,172069.2,172069.3,172069.4,172069.5,172069.6,172069.7,172069.8,172069.9,172069.10,172069.11,172069.12,172069.13,172069.14,172069.15,172069.16,172069.17,172069.18,172069.19,172069.20,172069.21,172069.22] || -> trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 172659[77:MRR:172071.1,172656.0] xuntil6(s49) || -> trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 172660[78:Spt:172657.0] || -> trans(s49,s26)*. % 76.16/76.37 172661[78:Res:172660.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s26)*. % 76.16/76.37 172663[78:Res:172660.0,60.0] || -> node2(s49,s26)*. % 76.16/76.37 172664[78:SSi:172661.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s26)*. % 76.16/76.37 172665[78:Res:172663.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 172742[78:SoR:172665.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 172744[78:SoR:172742.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)* xuntil6(s49). % 76.16/76.37 172745[78:SSi:172744.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s26,c_busy)* xuntil6(s49). % 76.16/76.37 172746[79:Spt:172745.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 172748[79:Res:172746.0,61.1] always3(s26) || -> . % 76.16/76.37 172749[79:SSi:172748.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.37 172750[79:Spt:172749.0,172745.1,172746.0] || m_main_v_state(s26,c_busy)*+ -> . % 76.16/76.37 172751[79:Spt:172749.0,172745.0,172745.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 172755[79:MRR:172742.2,172750.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 172756[79:Res:53.1,172751.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 172758[79:MRR:172756.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 172759[79:MRR:172664.0,172758.0] || -> until2p7(s26)*. % 76.16/76.37 172760[79:MRR:222.0,172759.0] || -> until2p7(s27)* node4(s26). % 76.16/76.37 172761[80:Spt:172760.0] || -> until2p7(s27)*. % 76.16/76.37 172762[80:MRR:223.0,172761.0] || -> until2p7(s28)* node4(s27). % 76.16/76.37 172763[81:Spt:172762.0] || -> until2p7(s28)*. % 76.16/76.37 172764[81:MRR:224.0,172763.0] || -> until2p7(s29)* node4(s28). % 76.16/76.37 172765[82:Spt:172764.0] || -> until2p7(s29)*. % 76.16/76.37 172766[82:MRR:225.0,172765.0] || -> until2p7(s30)* node4(s29). % 76.16/76.37 172767[83:Spt:172766.0] || -> until2p7(s30)*. % 76.16/76.37 172768[83:MRR:226.0,172767.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 172769[84:Spt:172768.0] || -> until2p7(s31)*. % 76.16/76.37 172770[84:MRR:227.0,172769.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 172771[85:Spt:172770.0] || -> until2p7(s32)*. % 76.16/76.37 172772[85:MRR:228.0,172771.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 172773[86:Spt:172772.0] || -> until2p7(s33)*. % 76.16/76.37 172774[86:MRR:229.0,172773.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 172775[87:Spt:172774.0] || -> until2p7(s34)*. % 76.16/76.37 172776[87:MRR:230.0,172775.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 172777[88:Spt:172776.0] || -> until2p7(s35)*. % 76.16/76.37 172778[88:MRR:231.0,172777.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 172779[89:Spt:172778.0] || -> until2p7(s36)*. % 76.16/76.37 172780[89:MRR:232.0,172779.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 172781[90:Spt:172780.0] || -> until2p7(s37)*. % 76.16/76.37 172782[90:MRR:235.0,172781.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 172783[91:Spt:172782.0] || -> until2p7(s38)*. % 76.16/76.37 172784[91:MRR:236.0,172783.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 172785[92:Spt:172784.0] || -> until2p7(s39)*. % 76.16/76.37 172786[92:MRR:237.0,172785.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 172787[93:Spt:172786.0] || -> until2p7(s40)*. % 76.16/76.37 172788[93:MRR:238.0,172787.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 172789[94:Spt:172788.0] || -> until2p7(s41)*. % 76.16/76.37 172790[94:MRR:239.0,172789.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 172791[95:Spt:172790.0] || -> until2p7(s42)*. % 76.16/76.37 172792[95:MRR:240.0,172791.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 172793[96:Spt:172792.0] || -> until2p7(s43)*. % 76.16/76.37 172794[96:MRR:241.0,172793.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 172795[97:Spt:172794.0] || -> until2p7(s44)*. % 76.16/76.37 172796[97:MRR:539.0,172795.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 172797[98:Spt:172796.0] || -> until2p7(s45)*. % 76.16/76.37 172798[98:MRR:544.0,172797.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 172799[99:Spt:172798.0] || -> until2p7(s46)*. % 76.16/76.37 172800[99:MRR:549.0,172799.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 172801[100:Spt:172800.0] || -> until2p7(s47)*. % 76.16/76.37 172802[100:MRR:554.0,172801.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 172803[101:Spt:172802.0] || -> until2p7(s48)*. % 76.16/76.37 172804[101:MRR:559.0,172803.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 172805[102:Spt:172804.0] || -> until2p7(s49)*. % 76.16/76.37 172806[102:MRR:194.0,172805.0] || -> node4(s49)*. % 76.16/76.37 172807[102:MRR:172755.0,172806.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 172811[102:Res:53.1,172807.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 172813[102:MRR:172811.0,78381.0] || -> . % 76.16/76.37 172814[102:Spt:172813.0,172804.0,172805.0] || until2p7(s49)*+ -> . % 76.16/76.37 172815[102:Spt:172813.0,172804.1] || -> node4(s48)*. % 76.16/76.37 172816[102:MRR:78384.0,172815.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 172819[102:Res:53.1,172816.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 172822[102:Res:172819.0,61.1] always3(s48) || -> . % 76.16/76.37 172823[102:SSi:172822.0,78281.0,78387.0,165540.0,172803.0,172815.0] || -> . % 76.16/76.37 172824[101:Spt:172823.0,172802.0,172803.0] || until2p7(s48)*+ -> . % 76.16/76.37 172825[101:Spt:172823.0,172802.1] || -> node4(s47)*. % 76.16/76.37 172827[101:MRR:777.0,172825.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 172839[101:Res:53.1,172827.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 172841[102:Spt:172839.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 172843[102:Res:172841.0,61.1] always3(s47) || -> . % 76.16/76.37 172844[102:SSi:172843.0,78277.0,78280.0,165539.0,172801.0,172825.0] || -> . % 76.16/76.37 172845[102:Spt:172844.0,172839.0,172841.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 172846[102:Spt:172844.0,172839.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 172850[102:Res:172846.0,61.1] always3(s48) || -> . % 76.16/76.37 172851[102:SSi:172850.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 172852[100:Spt:172851.0,172800.0,172801.0] || until2p7(s47)*+ -> . % 76.16/76.37 172853[100:Spt:172851.0,172800.1] || -> node4(s46)*. % 76.16/76.37 172855[100:MRR:780.0,172853.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 172862[100:Res:53.1,172855.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 172867[101:Spt:172862.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 172869[101:Res:172867.0,61.1] always3(s46) || -> . % 76.16/76.37 172870[101:SSi:172869.0,78272.0,78276.0,165538.0,172799.0,172853.0] || -> . % 76.16/76.37 172871[101:Spt:172870.0,172862.0,172867.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 172872[101:Spt:172870.0,172862.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 172876[101:Res:172872.0,61.1] always3(s47) || -> . % 76.16/76.37 172877[101:SSi:172876.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 172878[99:Spt:172877.0,172798.0,172799.0] || until2p7(s46)*+ -> . % 76.16/76.37 172879[99:Spt:172877.0,172798.1] || -> node4(s45)*. % 76.16/76.37 172881[99:MRR:783.0,172879.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 172884[99:Res:53.1,172881.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 172886[100:Spt:172884.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 172888[100:Res:172886.0,61.1] always3(s45) || -> . % 76.16/76.37 172889[100:SSi:172888.0,78268.0,78271.0,165537.0,172797.0,172879.0] || -> . % 76.16/76.37 172890[100:Spt:172889.0,172884.0,172886.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 172891[100:Spt:172889.0,172884.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 172895[100:Res:172891.0,61.1] always3(s46) || -> . % 76.16/76.37 172896[100:SSi:172895.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 172897[98:Spt:172896.0,172796.0,172797.0] || until2p7(s45)*+ -> . % 76.16/76.37 172898[98:Spt:172896.0,172796.1] || -> node4(s44)*. % 76.16/76.37 172900[98:MRR:786.0,172898.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 172903[98:Res:53.1,172900.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 172905[99:Spt:172903.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 172907[99:Res:172905.0,61.1] always3(s44) || -> . % 76.16/76.37 172908[99:SSi:172907.0,78263.0,78267.0,165536.0,172795.0,172898.0] || -> . % 76.16/76.37 172909[99:Spt:172908.0,172903.0,172905.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 172910[99:Spt:172908.0,172903.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 172914[99:Res:172910.0,61.1] always3(s45) || -> . % 76.16/76.37 172915[99:SSi:172914.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 172916[97:Spt:172915.0,172794.0,172795.0] || until2p7(s44)*+ -> . % 76.16/76.37 172917[97:Spt:172915.0,172794.1] || -> node4(s43)*. % 76.16/76.37 172919[97:MRR:789.0,172917.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 172922[97:Res:53.1,172919.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 172924[98:Spt:172922.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 172926[98:Res:172924.0,61.1] always3(s43) || -> . % 76.16/76.37 172927[98:SSi:172926.0,78259.0,78262.0,165535.0,172793.0,172917.0] || -> . % 76.16/76.37 172928[98:Spt:172927.0,172922.0,172924.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 172929[98:Spt:172927.0,172922.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 172933[98:Res:172929.0,61.1] always3(s44) || -> . % 76.16/76.37 172934[98:SSi:172933.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 172935[96:Spt:172934.0,172792.0,172793.0] || until2p7(s43)*+ -> . % 76.16/76.37 172936[96:Spt:172934.0,172792.1] || -> node4(s42)*. % 76.16/76.37 172938[96:MRR:792.0,172936.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 172941[96:Res:53.1,172938.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 172946[97:Spt:172941.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 172948[97:Res:172946.0,61.1] always3(s42) || -> . % 76.16/76.37 172949[97:SSi:172948.0,78254.0,78258.0,165534.0,172791.0,172936.0] || -> . % 76.16/76.37 172950[97:Spt:172949.0,172941.0,172946.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 172951[97:Spt:172949.0,172941.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 172955[97:Res:172951.0,61.1] always3(s43) || -> . % 76.16/76.37 172956[97:SSi:172955.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 172957[95:Spt:172956.0,172790.0,172791.0] || until2p7(s42)*+ -> . % 76.16/76.37 172958[95:Spt:172956.0,172790.1] || -> node4(s41)*. % 76.16/76.37 172960[95:MRR:795.0,172958.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 172963[95:Res:53.1,172960.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 172965[96:Spt:172963.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 172967[96:Res:172965.0,61.1] always3(s41) || -> . % 76.16/76.37 172968[96:SSi:172967.0,78250.0,78253.0,165533.0,172789.0,172958.0] || -> . % 76.16/76.37 172969[96:Spt:172968.0,172963.0,172965.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 172970[96:Spt:172968.0,172963.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 172974[96:Res:172970.0,61.1] always3(s42) || -> . % 76.16/76.37 172975[96:SSi:172974.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 172976[94:Spt:172975.0,172788.0,172789.0] || until2p7(s41)*+ -> . % 76.16/76.37 172977[94:Spt:172975.0,172788.1] || -> node4(s40)*. % 76.16/76.37 172979[94:MRR:798.0,172977.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 172982[94:Res:53.1,172979.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 172984[95:Spt:172982.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 172986[95:Res:172984.0,61.1] always3(s40) || -> . % 76.16/76.37 172987[95:SSi:172986.0,78245.0,78249.0,165532.0,172787.0,172977.0] || -> . % 76.16/76.37 172988[95:Spt:172987.0,172982.0,172984.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 172989[95:Spt:172987.0,172982.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 172993[95:Res:172989.0,61.1] always3(s41) || -> . % 76.16/76.37 172994[95:SSi:172993.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 172995[93:Spt:172994.0,172786.0,172787.0] || until2p7(s40)*+ -> . % 76.16/76.37 172996[93:Spt:172994.0,172786.1] || -> node4(s39)*. % 76.16/76.37 172998[93:MRR:801.0,172996.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 173001[93:Res:53.1,172998.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 173003[94:Spt:173001.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 173005[94:Res:173003.0,61.1] always3(s39) || -> . % 76.16/76.37 173006[94:SSi:173005.0,78241.0,78244.0,165531.0,172785.0,172996.0] || -> . % 76.16/76.37 173007[94:Spt:173006.0,173001.0,173003.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 173008[94:Spt:173006.0,173001.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 173012[94:Res:173008.0,61.1] always3(s40) || -> . % 76.16/76.37 173013[94:SSi:173012.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 173014[92:Spt:173013.0,172784.0,172785.0] || until2p7(s39)*+ -> . % 76.16/76.37 173015[92:Spt:173013.0,172784.1] || -> node4(s38)*. % 76.16/76.37 173017[92:MRR:804.0,173015.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 173020[92:Res:53.1,173017.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 173025[93:Spt:173020.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 173027[93:Res:173025.0,61.1] always3(s38) || -> . % 76.16/76.37 173028[93:SSi:173027.0,78236.0,78240.0,165530.0,172783.0,173015.0] || -> . % 76.16/76.37 173029[93:Spt:173028.0,173020.0,173025.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 173030[93:Spt:173028.0,173020.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 173034[93:Res:173030.0,61.1] always3(s39) || -> . % 76.16/76.37 173035[93:SSi:173034.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 173036[91:Spt:173035.0,172782.0,172783.0] || until2p7(s38)*+ -> . % 76.16/76.37 173037[91:Spt:173035.0,172782.1] || -> node4(s37)*. % 76.16/76.37 173039[91:MRR:807.0,173037.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 173042[91:Res:53.1,173039.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 173044[92:Spt:173042.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 173046[92:Res:173044.0,61.1] always3(s37) || -> . % 76.16/76.37 173047[92:SSi:173046.0,78232.0,78235.0,165529.0,172781.0,173037.0] || -> . % 76.16/76.37 173048[92:Spt:173047.0,173042.0,173044.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 173049[92:Spt:173047.0,173042.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 173053[92:Res:173049.0,61.1] always3(s38) || -> . % 76.16/76.37 173054[92:SSi:173053.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 173055[90:Spt:173054.0,172780.0,172781.0] || until2p7(s37)*+ -> . % 76.16/76.37 173056[90:Spt:173054.0,172780.1] || -> node4(s36)*. % 76.16/76.37 173058[90:MRR:810.0,173056.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 173061[90:Res:53.1,173058.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 173063[91:Spt:173061.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 173065[91:Res:173063.0,61.1] always3(s36) || -> . % 76.16/76.37 173066[91:SSi:173065.0,78227.0,78231.0,165528.0,172779.0,173056.0] || -> . % 76.16/76.37 173067[91:Spt:173066.0,173061.0,173063.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 173068[91:Spt:173066.0,173061.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 173072[91:Res:173068.0,61.1] always3(s37) || -> . % 76.16/76.37 173073[91:SSi:173072.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 173074[89:Spt:173073.0,172778.0,172779.0] || until2p7(s36)*+ -> . % 76.16/76.37 173075[89:Spt:173073.0,172778.1] || -> node4(s35)*. % 76.16/76.37 173077[89:MRR:813.0,173075.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 173080[89:Res:53.1,173077.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 173082[90:Spt:173080.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 173084[90:Res:173082.0,61.1] always3(s35) || -> . % 76.16/76.37 173085[90:SSi:173084.0,78223.0,78226.0,165527.0,172777.0,173075.0] || -> . % 76.16/76.37 173086[90:Spt:173085.0,173080.0,173082.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 173087[90:Spt:173085.0,173080.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 173091[90:Res:173087.0,61.1] always3(s36) || -> . % 76.16/76.37 173092[90:SSi:173091.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 173093[88:Spt:173092.0,172776.0,172777.0] || until2p7(s35)*+ -> . % 76.16/76.37 173094[88:Spt:173092.0,172776.1] || -> node4(s34)*. % 76.16/76.37 173096[88:MRR:816.0,173094.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 173099[88:Res:53.1,173096.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 173104[89:Spt:173099.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 173106[89:Res:173104.0,61.1] always3(s34) || -> . % 76.16/76.37 173107[89:SSi:173106.0,78218.0,78222.0,165526.0,172775.0,173094.0] || -> . % 76.16/76.37 173108[89:Spt:173107.0,173099.0,173104.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 173109[89:Spt:173107.0,173099.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 173113[89:Res:173109.0,61.1] always3(s35) || -> . % 76.16/76.37 173114[89:SSi:173113.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 173115[87:Spt:173114.0,172774.0,172775.0] || until2p7(s34)*+ -> . % 76.16/76.37 173116[87:Spt:173114.0,172774.1] || -> node4(s33)*. % 76.16/76.37 173118[87:MRR:819.0,173116.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 173121[87:Res:53.1,173118.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 173123[88:Spt:173121.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 173125[88:Res:173123.0,61.1] always3(s33) || -> . % 76.16/76.37 173126[88:SSi:173125.0,78214.0,78217.0,165525.0,172773.0,173116.0] || -> . % 76.16/76.37 173127[88:Spt:173126.0,173121.0,173123.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 173128[88:Spt:173126.0,173121.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 173132[88:Res:173128.0,61.1] always3(s34) || -> . % 76.16/76.37 173133[88:SSi:173132.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 173134[86:Spt:173133.0,172772.0,172773.0] || until2p7(s33)*+ -> . % 76.16/76.37 173135[86:Spt:173133.0,172772.1] || -> node4(s32)*. % 76.16/76.37 173137[86:MRR:822.0,173135.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 173140[86:Res:53.1,173137.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 173142[87:Spt:173140.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 173144[87:Res:173142.0,61.1] always3(s32) || -> . % 76.16/76.37 173145[87:SSi:173144.0,78209.0,78213.0,165524.0,172771.0,173135.0] || -> . % 76.16/76.37 173146[87:Spt:173145.0,173140.0,173142.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 173147[87:Spt:173145.0,173140.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 173151[87:Res:173147.0,61.1] always3(s33) || -> . % 76.16/76.37 173152[87:SSi:173151.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 173153[85:Spt:173152.0,172770.0,172771.0] || until2p7(s32)*+ -> . % 76.16/76.37 173154[85:Spt:173152.0,172770.1] || -> node4(s31)*. % 76.16/76.37 173156[85:MRR:825.0,173154.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 173159[85:Res:53.1,173156.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 173161[86:Spt:173159.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 173163[86:Res:173161.0,61.1] always3(s31) || -> . % 76.16/76.37 173164[86:SSi:173163.0,78205.0,78208.0,165523.0,172769.0,173154.0] || -> . % 76.16/76.37 173165[86:Spt:173164.0,173159.0,173161.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 173166[86:Spt:173164.0,173159.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 173170[86:Res:173166.0,61.1] always3(s32) || -> . % 76.16/76.37 173171[86:SSi:173170.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 173172[84:Spt:173171.0,172768.0,172769.0] || until2p7(s31)*+ -> . % 76.16/76.37 173173[84:Spt:173171.0,172768.1] || -> node4(s30)*. % 76.16/76.37 173175[84:MRR:828.0,173173.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 173178[84:Res:53.1,173175.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 173183[85:Spt:173178.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 173185[85:Res:173183.0,61.1] always3(s30) || -> . % 76.16/76.37 173186[85:SSi:173185.0,78200.0,78204.0,165522.0,172767.0,173173.0] || -> . % 76.16/76.37 173187[85:Spt:173186.0,173178.0,173183.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.37 173188[85:Spt:173186.0,173178.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 173192[85:Res:173188.0,61.1] always3(s31) || -> . % 76.16/76.37 173193[85:SSi:173192.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 173194[83:Spt:173193.0,172766.0,172767.0] || until2p7(s30)*+ -> . % 76.16/76.37 173195[83:Spt:173193.0,172766.1] || -> node4(s29)*. % 76.16/76.37 173197[83:MRR:831.0,173195.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.37 173200[83:Res:53.1,173197.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.37 173202[84:Spt:173200.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 173204[84:Res:173202.0,61.1] always3(s29) || -> . % 76.16/76.37 173205[84:SSi:173204.0,78196.0,78199.0,165521.0,172765.0,173195.0] || -> . % 76.16/76.37 173206[84:Spt:173205.0,173200.0,173202.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.37 173207[84:Spt:173205.0,173200.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 173211[84:Res:173207.0,61.1] always3(s30) || -> . % 76.16/76.37 173212[84:SSi:173211.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 173213[82:Spt:173212.0,172764.0,172765.0] || until2p7(s29)*+ -> . % 76.16/76.37 173214[82:Spt:173212.0,172764.1] || -> node4(s28)*. % 76.16/76.37 173216[82:MRR:834.0,173214.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.37 173219[82:Res:53.1,173216.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.37 173221[83:Spt:173219.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 173223[83:Res:173221.0,61.1] always3(s28) || -> . % 76.16/76.37 173224[83:SSi:173223.0,78191.0,78195.0,165520.0,172763.0,173214.0] || -> . % 76.16/76.37 173225[83:Spt:173224.0,173219.0,173221.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.37 173226[83:Spt:173224.0,173219.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 173230[83:Res:173226.0,61.1] always3(s29) || -> . % 76.16/76.37 173231[83:SSi:173230.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.37 173232[81:Spt:173231.0,172762.0,172763.0] || until2p7(s28)*+ -> . % 76.16/76.37 173233[81:Spt:173231.0,172762.1] || -> node4(s27)*. % 76.16/76.37 173235[81:MRR:837.0,173233.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.37 173238[81:Res:53.1,173235.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.37 173240[82:Spt:173238.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 173242[82:Res:173240.0,61.1] always3(s27) || -> . % 76.16/76.37 173243[82:SSi:173242.0,78187.0,78190.0,165519.0,172761.0,173233.0] || -> . % 76.16/76.37 173244[82:Spt:173243.0,173238.0,173240.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.37 173245[82:Spt:173243.0,173238.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 173249[82:Res:173245.0,61.1] always3(s28) || -> . % 76.16/76.37 173250[82:SSi:173249.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.37 173251[80:Spt:173250.0,172760.0,172761.0] || until2p7(s27)*+ -> . % 76.16/76.37 173252[80:Spt:173250.0,172760.1] || -> node4(s26)*. % 76.16/76.37 173254[80:MRR:840.0,173252.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.37 173257[80:Res:53.1,173254.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.37 173259[80:MRR:173257.0,172750.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 173264[80:Res:173259.0,61.1] always3(s27) || -> . % 76.16/76.37 173265[80:SSi:173264.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.37 173266[78:Spt:173265.0,172657.0,172660.0] || trans(s49,s26)*+ -> . % 76.16/76.37 173267[78:Spt:173265.0,172657.1,172657.2,172657.3,172657.4,172657.5,172657.6,172657.7,172657.8,172657.9,172657.10,172657.11,172657.12,172657.13,172657.14,172657.15,172657.16,172657.17,172657.18,172657.19,172657.20,172657.21] || -> trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 173269[78:MRR:172659.1,173266.0] xuntil6(s49) || -> trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 173270[79:Spt:173267.0] || -> trans(s49,s25)*. % 76.16/76.37 173271[79:Res:173270.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s25)*. % 76.16/76.37 173273[79:Res:173270.0,60.0] || -> node2(s49,s25)*. % 76.16/76.37 173274[79:SSi:173271.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s25)*. % 76.16/76.37 173275[79:Res:173273.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 173356[79:SoR:173275.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 173358[79:SoR:173356.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)* xuntil6(s49). % 76.16/76.37 173359[79:SSi:173358.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s25,c_busy)* xuntil6(s49). % 76.16/76.37 173360[80:Spt:173359.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 173362[80:Res:173360.0,61.1] always3(s25) || -> . % 76.16/76.37 173363[80:SSi:173362.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.37 173364[80:Spt:173363.0,173359.1,173360.0] || m_main_v_state(s25,c_busy)*+ -> . % 76.16/76.37 173365[80:Spt:173363.0,173359.0,173359.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 173369[80:MRR:173356.2,173364.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 173370[80:Res:53.1,173365.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 173372[80:MRR:173370.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 173373[80:MRR:173274.0,173372.0] || -> until2p7(s25)*. % 76.16/76.37 173374[80:MRR:221.0,173373.0] || -> until2p7(s26)* node4(s25). % 76.16/76.37 173375[81:Spt:173374.0] || -> until2p7(s26)*. % 76.16/76.37 173376[81:MRR:222.0,173375.0] || -> until2p7(s27)* node4(s26). % 76.16/76.37 173377[82:Spt:173376.0] || -> until2p7(s27)*. % 76.16/76.37 173378[82:MRR:223.0,173377.0] || -> until2p7(s28)* node4(s27). % 76.16/76.37 173379[83:Spt:173378.0] || -> until2p7(s28)*. % 76.16/76.37 173380[83:MRR:224.0,173379.0] || -> until2p7(s29)* node4(s28). % 76.16/76.37 173381[84:Spt:173380.0] || -> until2p7(s29)*. % 76.16/76.37 173382[84:MRR:225.0,173381.0] || -> until2p7(s30)* node4(s29). % 76.16/76.37 173383[85:Spt:173382.0] || -> until2p7(s30)*. % 76.16/76.37 173384[85:MRR:226.0,173383.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 173385[86:Spt:173384.0] || -> until2p7(s31)*. % 76.16/76.37 173386[86:MRR:227.0,173385.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 173387[87:Spt:173386.0] || -> until2p7(s32)*. % 76.16/76.37 173388[87:MRR:228.0,173387.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 173389[88:Spt:173388.0] || -> until2p7(s33)*. % 76.16/76.37 173390[88:MRR:229.0,173389.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 173391[89:Spt:173390.0] || -> until2p7(s34)*. % 76.16/76.37 173392[89:MRR:230.0,173391.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 173393[90:Spt:173392.0] || -> until2p7(s35)*. % 76.16/76.37 173394[90:MRR:231.0,173393.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 173395[91:Spt:173394.0] || -> until2p7(s36)*. % 76.16/76.37 173396[91:MRR:232.0,173395.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 173397[92:Spt:173396.0] || -> until2p7(s37)*. % 76.16/76.37 173398[92:MRR:235.0,173397.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 173399[93:Spt:173398.0] || -> until2p7(s38)*. % 76.16/76.37 173400[93:MRR:236.0,173399.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 173401[94:Spt:173400.0] || -> until2p7(s39)*. % 76.16/76.37 173402[94:MRR:237.0,173401.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 173403[95:Spt:173402.0] || -> until2p7(s40)*. % 76.16/76.37 173404[95:MRR:238.0,173403.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 173405[96:Spt:173404.0] || -> until2p7(s41)*. % 76.16/76.37 173406[96:MRR:239.0,173405.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 173407[97:Spt:173406.0] || -> until2p7(s42)*. % 76.16/76.37 173408[97:MRR:240.0,173407.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 173409[98:Spt:173408.0] || -> until2p7(s43)*. % 76.16/76.37 173410[98:MRR:241.0,173409.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 173411[99:Spt:173410.0] || -> until2p7(s44)*. % 76.16/76.37 173412[99:MRR:539.0,173411.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 173413[100:Spt:173412.0] || -> until2p7(s45)*. % 76.16/76.37 173414[100:MRR:544.0,173413.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 173415[101:Spt:173414.0] || -> until2p7(s46)*. % 76.16/76.37 173416[101:MRR:549.0,173415.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 173417[102:Spt:173416.0] || -> until2p7(s47)*. % 76.16/76.37 173418[102:MRR:554.0,173417.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 173419[103:Spt:173418.0] || -> until2p7(s48)*. % 76.16/76.37 173420[103:MRR:559.0,173419.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 173421[104:Spt:173420.0] || -> until2p7(s49)*. % 76.16/76.37 173422[104:MRR:194.0,173421.0] || -> node4(s49)*. % 76.16/76.37 173423[104:MRR:173369.0,173422.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 173424[104:Res:53.1,173423.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 173426[104:MRR:173424.0,78381.0] || -> . % 76.16/76.37 173427[104:Spt:173426.0,173420.0,173421.0] || until2p7(s49)*+ -> . % 76.16/76.37 173428[104:Spt:173426.0,173420.1] || -> node4(s48)*. % 76.16/76.37 173429[104:MRR:78384.0,173428.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 173432[104:Res:53.1,173429.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 173435[104:Res:173432.0,61.1] always3(s48) || -> . % 76.16/76.37 173436[104:SSi:173435.0,78281.0,78387.0,165540.0,173419.0,173428.0] || -> . % 76.16/76.37 173437[103:Spt:173436.0,173418.0,173419.0] || until2p7(s48)*+ -> . % 76.16/76.37 173438[103:Spt:173436.0,173418.1] || -> node4(s47)*. % 76.16/76.37 173440[103:MRR:777.0,173438.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 173455[103:Res:53.1,173440.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 173457[104:Spt:173455.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 173459[104:Res:173457.0,61.1] always3(s47) || -> . % 76.16/76.37 173460[104:SSi:173459.0,78277.0,78280.0,165539.0,173417.0,173438.0] || -> . % 76.16/76.37 173461[104:Spt:173460.0,173455.0,173457.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 173462[104:Spt:173460.0,173455.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 173466[104:Res:173462.0,61.1] always3(s48) || -> . % 76.16/76.37 173467[104:SSi:173466.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 173468[102:Spt:173467.0,173416.0,173417.0] || until2p7(s47)*+ -> . % 76.16/76.37 173469[102:Spt:173467.0,173416.1] || -> node4(s46)*. % 76.16/76.37 173471[102:MRR:780.0,173469.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 173481[102:Res:53.1,173471.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 173483[103:Spt:173481.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 173485[103:Res:173483.0,61.1] always3(s46) || -> . % 76.16/76.37 173486[103:SSi:173485.0,78272.0,78276.0,165538.0,173415.0,173469.0] || -> . % 76.16/76.37 173487[103:Spt:173486.0,173481.0,173483.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 173488[103:Spt:173486.0,173481.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 173492[103:Res:173488.0,61.1] always3(s47) || -> . % 76.16/76.37 173493[103:SSi:173492.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 173494[101:Spt:173493.0,173414.0,173415.0] || until2p7(s46)*+ -> . % 76.16/76.37 173495[101:Spt:173493.0,173414.1] || -> node4(s45)*. % 76.16/76.37 173497[101:MRR:783.0,173495.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 173500[101:Res:53.1,173497.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 173502[102:Spt:173500.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 173504[102:Res:173502.0,61.1] always3(s45) || -> . % 76.16/76.37 173505[102:SSi:173504.0,78268.0,78271.0,165537.0,173413.0,173495.0] || -> . % 76.16/76.37 173506[102:Spt:173505.0,173500.0,173502.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 173507[102:Spt:173505.0,173500.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 173511[102:Res:173507.0,61.1] always3(s46) || -> . % 76.16/76.37 173512[102:SSi:173511.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 173513[100:Spt:173512.0,173412.0,173413.0] || until2p7(s45)*+ -> . % 76.16/76.37 173514[100:Spt:173512.0,173412.1] || -> node4(s44)*. % 76.16/76.37 173516[100:MRR:786.0,173514.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 173519[100:Res:53.1,173516.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 173521[101:Spt:173519.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 173523[101:Res:173521.0,61.1] always3(s44) || -> . % 76.16/76.37 173524[101:SSi:173523.0,78263.0,78267.0,165536.0,173411.0,173514.0] || -> . % 76.16/76.37 173525[101:Spt:173524.0,173519.0,173521.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 173526[101:Spt:173524.0,173519.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 173530[101:Res:173526.0,61.1] always3(s45) || -> . % 76.16/76.37 173531[101:SSi:173530.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 173532[99:Spt:173531.0,173410.0,173411.0] || until2p7(s44)*+ -> . % 76.16/76.37 173533[99:Spt:173531.0,173410.1] || -> node4(s43)*. % 76.16/76.37 173535[99:MRR:789.0,173533.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 173538[99:Res:53.1,173535.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 173543[100:Spt:173538.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 173545[100:Res:173543.0,61.1] always3(s43) || -> . % 76.16/76.37 173546[100:SSi:173545.0,78259.0,78262.0,165535.0,173409.0,173533.0] || -> . % 76.16/76.37 173547[100:Spt:173546.0,173538.0,173543.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 173548[100:Spt:173546.0,173538.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 173552[100:Res:173548.0,61.1] always3(s44) || -> . % 76.16/76.37 173553[100:SSi:173552.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 173554[98:Spt:173553.0,173408.0,173409.0] || until2p7(s43)*+ -> . % 76.16/76.37 173555[98:Spt:173553.0,173408.1] || -> node4(s42)*. % 76.16/76.37 173557[98:MRR:792.0,173555.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 173560[98:Res:53.1,173557.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 173562[99:Spt:173560.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 173564[99:Res:173562.0,61.1] always3(s42) || -> . % 76.16/76.37 173565[99:SSi:173564.0,78254.0,78258.0,165534.0,173407.0,173555.0] || -> . % 76.16/76.37 173566[99:Spt:173565.0,173560.0,173562.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 173567[99:Spt:173565.0,173560.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 173571[99:Res:173567.0,61.1] always3(s43) || -> . % 76.16/76.37 173572[99:SSi:173571.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 173573[97:Spt:173572.0,173406.0,173407.0] || until2p7(s42)*+ -> . % 76.16/76.37 173574[97:Spt:173572.0,173406.1] || -> node4(s41)*. % 76.16/76.37 173576[97:MRR:795.0,173574.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 173579[97:Res:53.1,173576.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 173581[98:Spt:173579.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 173583[98:Res:173581.0,61.1] always3(s41) || -> . % 76.16/76.37 173584[98:SSi:173583.0,78250.0,78253.0,165533.0,173405.0,173574.0] || -> . % 76.16/76.37 173585[98:Spt:173584.0,173579.0,173581.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 173586[98:Spt:173584.0,173579.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 173590[98:Res:173586.0,61.1] always3(s42) || -> . % 76.16/76.37 173591[98:SSi:173590.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 173592[96:Spt:173591.0,173404.0,173405.0] || until2p7(s41)*+ -> . % 76.16/76.37 173593[96:Spt:173591.0,173404.1] || -> node4(s40)*. % 76.16/76.37 173595[96:MRR:798.0,173593.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 173598[96:Res:53.1,173595.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 173600[97:Spt:173598.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 173602[97:Res:173600.0,61.1] always3(s40) || -> . % 76.16/76.37 173603[97:SSi:173602.0,78245.0,78249.0,165532.0,173403.0,173593.0] || -> . % 76.16/76.37 173604[97:Spt:173603.0,173598.0,173600.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 173605[97:Spt:173603.0,173598.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 173609[97:Res:173605.0,61.1] always3(s41) || -> . % 76.16/76.37 173610[97:SSi:173609.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 173611[95:Spt:173610.0,173402.0,173403.0] || until2p7(s40)*+ -> . % 76.16/76.37 173612[95:Spt:173610.0,173402.1] || -> node4(s39)*. % 76.16/76.37 173614[95:MRR:801.0,173612.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 173617[95:Res:53.1,173614.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 173622[96:Spt:173617.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 173624[96:Res:173622.0,61.1] always3(s39) || -> . % 76.16/76.37 173625[96:SSi:173624.0,78241.0,78244.0,165531.0,173401.0,173612.0] || -> . % 76.16/76.37 173626[96:Spt:173625.0,173617.0,173622.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 173627[96:Spt:173625.0,173617.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 173631[96:Res:173627.0,61.1] always3(s40) || -> . % 76.16/76.37 173632[96:SSi:173631.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 173633[94:Spt:173632.0,173400.0,173401.0] || until2p7(s39)*+ -> . % 76.16/76.37 173634[94:Spt:173632.0,173400.1] || -> node4(s38)*. % 76.16/76.37 173636[94:MRR:804.0,173634.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 173639[94:Res:53.1,173636.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 173641[95:Spt:173639.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 173643[95:Res:173641.0,61.1] always3(s38) || -> . % 76.16/76.37 173644[95:SSi:173643.0,78236.0,78240.0,165530.0,173399.0,173634.0] || -> . % 76.16/76.37 173645[95:Spt:173644.0,173639.0,173641.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 173646[95:Spt:173644.0,173639.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 173650[95:Res:173646.0,61.1] always3(s39) || -> . % 76.16/76.37 173651[95:SSi:173650.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 173652[93:Spt:173651.0,173398.0,173399.0] || until2p7(s38)*+ -> . % 76.16/76.37 173653[93:Spt:173651.0,173398.1] || -> node4(s37)*. % 76.16/76.37 173655[93:MRR:807.0,173653.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 173658[93:Res:53.1,173655.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 173660[94:Spt:173658.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 173662[94:Res:173660.0,61.1] always3(s37) || -> . % 76.16/76.37 173663[94:SSi:173662.0,78232.0,78235.0,165529.0,173397.0,173653.0] || -> . % 76.16/76.37 173664[94:Spt:173663.0,173658.0,173660.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 173665[94:Spt:173663.0,173658.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 173669[94:Res:173665.0,61.1] always3(s38) || -> . % 76.16/76.37 173670[94:SSi:173669.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 173671[92:Spt:173670.0,173396.0,173397.0] || until2p7(s37)*+ -> . % 76.16/76.37 173672[92:Spt:173670.0,173396.1] || -> node4(s36)*. % 76.16/76.37 173674[92:MRR:810.0,173672.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 173677[92:Res:53.1,173674.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 173679[93:Spt:173677.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 173681[93:Res:173679.0,61.1] always3(s36) || -> . % 76.16/76.37 173682[93:SSi:173681.0,78227.0,78231.0,165528.0,173395.0,173672.0] || -> . % 76.16/76.37 173683[93:Spt:173682.0,173677.0,173679.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 173684[93:Spt:173682.0,173677.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 173688[93:Res:173684.0,61.1] always3(s37) || -> . % 76.16/76.37 173689[93:SSi:173688.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 173690[91:Spt:173689.0,173394.0,173395.0] || until2p7(s36)*+ -> . % 76.16/76.37 173691[91:Spt:173689.0,173394.1] || -> node4(s35)*. % 76.16/76.37 173693[91:MRR:813.0,173691.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 173696[91:Res:53.1,173693.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 173701[92:Spt:173696.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 173703[92:Res:173701.0,61.1] always3(s35) || -> . % 76.16/76.37 173704[92:SSi:173703.0,78223.0,78226.0,165527.0,173393.0,173691.0] || -> . % 76.16/76.37 173705[92:Spt:173704.0,173696.0,173701.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 173706[92:Spt:173704.0,173696.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 173710[92:Res:173706.0,61.1] always3(s36) || -> . % 76.16/76.37 173711[92:SSi:173710.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 173712[90:Spt:173711.0,173392.0,173393.0] || until2p7(s35)*+ -> . % 76.16/76.37 173713[90:Spt:173711.0,173392.1] || -> node4(s34)*. % 76.16/76.37 173715[90:MRR:816.0,173713.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 173718[90:Res:53.1,173715.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 173720[91:Spt:173718.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 173722[91:Res:173720.0,61.1] always3(s34) || -> . % 76.16/76.37 173723[91:SSi:173722.0,78218.0,78222.0,165526.0,173391.0,173713.0] || -> . % 76.16/76.37 173724[91:Spt:173723.0,173718.0,173720.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 173725[91:Spt:173723.0,173718.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 173729[91:Res:173725.0,61.1] always3(s35) || -> . % 76.16/76.37 173730[91:SSi:173729.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 173731[89:Spt:173730.0,173390.0,173391.0] || until2p7(s34)*+ -> . % 76.16/76.37 173732[89:Spt:173730.0,173390.1] || -> node4(s33)*. % 76.16/76.37 173734[89:MRR:819.0,173732.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 173737[89:Res:53.1,173734.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 173739[90:Spt:173737.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 173741[90:Res:173739.0,61.1] always3(s33) || -> . % 76.16/76.37 173742[90:SSi:173741.0,78214.0,78217.0,165525.0,173389.0,173732.0] || -> . % 76.16/76.37 173743[90:Spt:173742.0,173737.0,173739.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 173744[90:Spt:173742.0,173737.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 173748[90:Res:173744.0,61.1] always3(s34) || -> . % 76.16/76.37 173749[90:SSi:173748.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 173750[88:Spt:173749.0,173388.0,173389.0] || until2p7(s33)*+ -> . % 76.16/76.37 173751[88:Spt:173749.0,173388.1] || -> node4(s32)*. % 76.16/76.37 173753[88:MRR:822.0,173751.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 173756[88:Res:53.1,173753.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 173758[89:Spt:173756.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 173760[89:Res:173758.0,61.1] always3(s32) || -> . % 76.16/76.37 173761[89:SSi:173760.0,78209.0,78213.0,165524.0,173387.0,173751.0] || -> . % 76.16/76.37 173762[89:Spt:173761.0,173756.0,173758.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 173763[89:Spt:173761.0,173756.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 173767[89:Res:173763.0,61.1] always3(s33) || -> . % 76.16/76.37 173768[89:SSi:173767.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 173769[87:Spt:173768.0,173386.0,173387.0] || until2p7(s32)*+ -> . % 76.16/76.37 173770[87:Spt:173768.0,173386.1] || -> node4(s31)*. % 76.16/76.37 173772[87:MRR:825.0,173770.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 173775[87:Res:53.1,173772.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 173780[88:Spt:173775.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 173782[88:Res:173780.0,61.1] always3(s31) || -> . % 76.16/76.37 173783[88:SSi:173782.0,78205.0,78208.0,165523.0,173385.0,173770.0] || -> . % 76.16/76.37 173784[88:Spt:173783.0,173775.0,173780.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 173785[88:Spt:173783.0,173775.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 173789[88:Res:173785.0,61.1] always3(s32) || -> . % 76.16/76.37 173790[88:SSi:173789.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 173791[86:Spt:173790.0,173384.0,173385.0] || until2p7(s31)*+ -> . % 76.16/76.37 173792[86:Spt:173790.0,173384.1] || -> node4(s30)*. % 76.16/76.37 173794[86:MRR:828.0,173792.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 173797[86:Res:53.1,173794.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 173799[87:Spt:173797.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 173801[87:Res:173799.0,61.1] always3(s30) || -> . % 76.16/76.37 173802[87:SSi:173801.0,78200.0,78204.0,165522.0,173383.0,173792.0] || -> . % 76.16/76.37 173803[87:Spt:173802.0,173797.0,173799.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.37 173804[87:Spt:173802.0,173797.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 173808[87:Res:173804.0,61.1] always3(s31) || -> . % 76.16/76.37 173809[87:SSi:173808.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 173810[85:Spt:173809.0,173382.0,173383.0] || until2p7(s30)*+ -> . % 76.16/76.37 173811[85:Spt:173809.0,173382.1] || -> node4(s29)*. % 76.16/76.37 173813[85:MRR:831.0,173811.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.37 173816[85:Res:53.1,173813.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.37 173818[86:Spt:173816.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 173820[86:Res:173818.0,61.1] always3(s29) || -> . % 76.16/76.37 173821[86:SSi:173820.0,78196.0,78199.0,165521.0,173381.0,173811.0] || -> . % 76.16/76.37 173822[86:Spt:173821.0,173816.0,173818.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.37 173823[86:Spt:173821.0,173816.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 173827[86:Res:173823.0,61.1] always3(s30) || -> . % 76.16/76.37 173828[86:SSi:173827.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 173829[84:Spt:173828.0,173380.0,173381.0] || until2p7(s29)*+ -> . % 76.16/76.37 173830[84:Spt:173828.0,173380.1] || -> node4(s28)*. % 76.16/76.37 173832[84:MRR:834.0,173830.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.37 173835[84:Res:53.1,173832.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.37 173837[85:Spt:173835.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 173839[85:Res:173837.0,61.1] always3(s28) || -> . % 76.16/76.37 173840[85:SSi:173839.0,78191.0,78195.0,165520.0,173379.0,173830.0] || -> . % 76.16/76.37 173841[85:Spt:173840.0,173835.0,173837.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.37 173842[85:Spt:173840.0,173835.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 173846[85:Res:173842.0,61.1] always3(s29) || -> . % 76.16/76.37 173847[85:SSi:173846.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.37 173848[83:Spt:173847.0,173378.0,173379.0] || until2p7(s28)*+ -> . % 76.16/76.37 173849[83:Spt:173847.0,173378.1] || -> node4(s27)*. % 76.16/76.37 173851[83:MRR:837.0,173849.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.37 173854[83:Res:53.1,173851.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.37 173859[84:Spt:173854.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 173861[84:Res:173859.0,61.1] always3(s27) || -> . % 76.16/76.37 173862[84:SSi:173861.0,78187.0,78190.0,165519.0,173377.0,173849.0] || -> . % 76.16/76.37 173863[84:Spt:173862.0,173854.0,173859.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.37 173864[84:Spt:173862.0,173854.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 173868[84:Res:173864.0,61.1] always3(s28) || -> . % 76.16/76.37 173869[84:SSi:173868.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.37 173870[82:Spt:173869.0,173376.0,173377.0] || until2p7(s27)*+ -> . % 76.16/76.37 173871[82:Spt:173869.0,173376.1] || -> node4(s26)*. % 76.16/76.37 173873[82:MRR:840.0,173871.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.37 173876[82:Res:53.1,173873.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.37 173878[83:Spt:173876.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 173880[83:Res:173878.0,61.1] always3(s26) || -> . % 76.16/76.37 173881[83:SSi:173880.0,78182.0,78186.0,165518.0,173375.0,173871.0] || -> . % 76.16/76.37 173882[83:Spt:173881.0,173876.0,173878.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.37 173883[83:Spt:173881.0,173876.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 173887[83:Res:173883.0,61.1] always3(s27) || -> . % 76.16/76.37 173888[83:SSi:173887.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.37 173889[81:Spt:173888.0,173374.0,173375.0] || until2p7(s26)*+ -> . % 76.16/76.37 173890[81:Spt:173888.0,173374.1] || -> node4(s25)*. % 76.16/76.37 173892[81:MRR:843.0,173890.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.37 173895[81:Res:53.1,173892.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.37 173897[81:MRR:173895.0,173364.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 173899[81:Res:173897.0,61.1] always3(s26) || -> . % 76.16/76.37 173900[81:SSi:173899.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.37 173901[79:Spt:173900.0,173267.0,173270.0] || trans(s49,s25)*+ -> . % 76.16/76.37 173902[79:Spt:173900.0,173267.1,173267.2,173267.3,173267.4,173267.5,173267.6,173267.7,173267.8,173267.9,173267.10,173267.11,173267.12,173267.13,173267.14,173267.15,173267.16,173267.17,173267.18,173267.19,173267.20] || -> trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 173904[79:MRR:173269.1,173901.0] xuntil6(s49) || -> trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 173905[80:Spt:173902.0] || -> trans(s49,s24)*. % 76.16/76.37 173906[80:Res:173905.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s24)*. % 76.16/76.37 173908[80:Res:173905.0,60.0] || -> node2(s49,s24)*. % 76.16/76.37 173909[80:SSi:173906.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s24)*. % 76.16/76.37 173910[80:Res:173908.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 173995[80:SoR:173910.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 173997[80:SoR:173995.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)* xuntil6(s49). % 76.16/76.37 173998[80:SSi:173997.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s24,c_busy)* xuntil6(s49). % 76.16/76.37 173999[81:Spt:173998.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 174001[81:Res:173999.0,61.1] always3(s24) || -> . % 76.16/76.37 174002[81:SSi:174001.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.37 174003[81:Spt:174002.0,173998.1,173999.0] || m_main_v_state(s24,c_busy)*+ -> . % 76.16/76.37 174004[81:Spt:174002.0,173998.0,173998.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 174008[81:MRR:173995.2,174003.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 174009[81:Res:53.1,174004.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 174011[81:MRR:174009.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 174012[81:MRR:173909.0,174011.0] || -> until2p7(s24)*. % 76.16/76.37 174013[81:MRR:220.0,174012.0] || -> until2p7(s25)* node4(s24). % 76.16/76.37 174014[82:Spt:174013.0] || -> until2p7(s25)*. % 76.16/76.37 174015[82:MRR:221.0,174014.0] || -> until2p7(s26)* node4(s25). % 76.16/76.37 174016[83:Spt:174015.0] || -> until2p7(s26)*. % 76.16/76.37 174017[83:MRR:222.0,174016.0] || -> until2p7(s27)* node4(s26). % 76.16/76.37 174018[84:Spt:174017.0] || -> until2p7(s27)*. % 76.16/76.37 174019[84:MRR:223.0,174018.0] || -> until2p7(s28)* node4(s27). % 76.16/76.37 174020[85:Spt:174019.0] || -> until2p7(s28)*. % 76.16/76.37 174021[85:MRR:224.0,174020.0] || -> until2p7(s29)* node4(s28). % 76.16/76.37 174022[86:Spt:174021.0] || -> until2p7(s29)*. % 76.16/76.37 174023[86:MRR:225.0,174022.0] || -> until2p7(s30)* node4(s29). % 76.16/76.37 174024[87:Spt:174023.0] || -> until2p7(s30)*. % 76.16/76.37 174025[87:MRR:226.0,174024.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 174026[88:Spt:174025.0] || -> until2p7(s31)*. % 76.16/76.37 174027[88:MRR:227.0,174026.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 174028[89:Spt:174027.0] || -> until2p7(s32)*. % 76.16/76.37 174029[89:MRR:228.0,174028.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 174030[90:Spt:174029.0] || -> until2p7(s33)*. % 76.16/76.37 174031[90:MRR:229.0,174030.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 174032[91:Spt:174031.0] || -> until2p7(s34)*. % 76.16/76.37 174033[91:MRR:230.0,174032.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 174034[92:Spt:174033.0] || -> until2p7(s35)*. % 76.16/76.37 174035[92:MRR:231.0,174034.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 174036[93:Spt:174035.0] || -> until2p7(s36)*. % 76.16/76.37 174037[93:MRR:232.0,174036.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 174038[94:Spt:174037.0] || -> until2p7(s37)*. % 76.16/76.37 174039[94:MRR:235.0,174038.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 174040[95:Spt:174039.0] || -> until2p7(s38)*. % 76.16/76.37 174041[95:MRR:236.0,174040.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 174042[96:Spt:174041.0] || -> until2p7(s39)*. % 76.16/76.37 174043[96:MRR:237.0,174042.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 174044[97:Spt:174043.0] || -> until2p7(s40)*. % 76.16/76.37 174045[97:MRR:238.0,174044.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 174046[98:Spt:174045.0] || -> until2p7(s41)*. % 76.16/76.37 174047[98:MRR:239.0,174046.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 174048[99:Spt:174047.0] || -> until2p7(s42)*. % 76.16/76.37 174049[99:MRR:240.0,174048.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 174050[100:Spt:174049.0] || -> until2p7(s43)*. % 76.16/76.37 174051[100:MRR:241.0,174050.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 174052[101:Spt:174051.0] || -> until2p7(s44)*. % 76.16/76.37 174053[101:MRR:539.0,174052.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 174054[102:Spt:174053.0] || -> until2p7(s45)*. % 76.16/76.37 174055[102:MRR:544.0,174054.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 174056[103:Spt:174055.0] || -> until2p7(s46)*. % 76.16/76.37 174057[103:MRR:549.0,174056.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 174058[104:Spt:174057.0] || -> until2p7(s47)*. % 76.16/76.37 174059[104:MRR:554.0,174058.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 174060[105:Spt:174059.0] || -> until2p7(s48)*. % 76.16/76.37 174061[105:MRR:559.0,174060.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 174062[106:Spt:174061.0] || -> until2p7(s49)*. % 76.16/76.37 174063[106:MRR:194.0,174062.0] || -> node4(s49)*. % 76.16/76.37 174064[106:MRR:174008.0,174063.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 174065[106:Res:53.1,174064.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 174067[106:MRR:174065.0,78381.0] || -> . % 76.16/76.37 174068[106:Spt:174067.0,174061.0,174062.0] || until2p7(s49)*+ -> . % 76.16/76.37 174069[106:Spt:174067.0,174061.1] || -> node4(s48)*. % 76.16/76.37 174070[106:MRR:78384.0,174069.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 174073[106:Res:53.1,174070.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 174076[106:Res:174073.0,61.1] always3(s48) || -> . % 76.16/76.37 174077[106:SSi:174076.0,78281.0,78387.0,165540.0,174060.0,174069.0] || -> . % 76.16/76.37 174078[105:Spt:174077.0,174059.0,174060.0] || until2p7(s48)*+ -> . % 76.16/76.37 174079[105:Spt:174077.0,174059.1] || -> node4(s47)*. % 76.16/76.37 174081[105:MRR:777.0,174079.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 174096[105:Res:53.1,174081.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 174098[106:Spt:174096.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 174100[106:Res:174098.0,61.1] always3(s47) || -> . % 76.16/76.37 174101[106:SSi:174100.0,78277.0,78280.0,165539.0,174058.0,174079.0] || -> . % 76.16/76.37 174102[106:Spt:174101.0,174096.0,174098.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 174103[106:Spt:174101.0,174096.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 174107[106:Res:174103.0,61.1] always3(s48) || -> . % 76.16/76.37 174108[106:SSi:174107.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 174109[104:Spt:174108.0,174057.0,174058.0] || until2p7(s47)*+ -> . % 76.16/76.37 174110[104:Spt:174108.0,174057.1] || -> node4(s46)*. % 76.16/76.37 174112[104:MRR:780.0,174110.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 174122[104:Res:53.1,174112.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 174124[105:Spt:174122.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 174126[105:Res:174124.0,61.1] always3(s46) || -> . % 76.16/76.37 174127[105:SSi:174126.0,78272.0,78276.0,165538.0,174056.0,174110.0] || -> . % 76.16/76.37 174128[105:Spt:174127.0,174122.0,174124.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 174129[105:Spt:174127.0,174122.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 174133[105:Res:174129.0,61.1] always3(s47) || -> . % 76.16/76.37 174134[105:SSi:174133.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 174135[103:Spt:174134.0,174055.0,174056.0] || until2p7(s46)*+ -> . % 76.16/76.37 174136[103:Spt:174134.0,174055.1] || -> node4(s45)*. % 76.16/76.37 174138[103:MRR:783.0,174136.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 174141[103:Res:53.1,174138.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 174143[104:Spt:174141.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 174145[104:Res:174143.0,61.1] always3(s45) || -> . % 76.16/76.37 174146[104:SSi:174145.0,78268.0,78271.0,165537.0,174054.0,174136.0] || -> . % 76.16/76.37 174147[104:Spt:174146.0,174141.0,174143.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 174148[104:Spt:174146.0,174141.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 174152[104:Res:174148.0,61.1] always3(s46) || -> . % 76.16/76.37 174153[104:SSi:174152.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 174154[102:Spt:174153.0,174053.0,174054.0] || until2p7(s45)*+ -> . % 76.16/76.37 174155[102:Spt:174153.0,174053.1] || -> node4(s44)*. % 76.16/76.37 174157[102:MRR:786.0,174155.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 174160[102:Res:53.1,174157.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 174162[103:Spt:174160.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 174164[103:Res:174162.0,61.1] always3(s44) || -> . % 76.16/76.37 174165[103:SSi:174164.0,78263.0,78267.0,165536.0,174052.0,174155.0] || -> . % 76.16/76.37 174166[103:Spt:174165.0,174160.0,174162.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 174167[103:Spt:174165.0,174160.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 174171[103:Res:174167.0,61.1] always3(s45) || -> . % 76.16/76.37 174172[103:SSi:174171.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 174173[101:Spt:174172.0,174051.0,174052.0] || until2p7(s44)*+ -> . % 76.16/76.37 174174[101:Spt:174172.0,174051.1] || -> node4(s43)*. % 76.16/76.37 174176[101:MRR:789.0,174174.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 174179[101:Res:53.1,174176.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 174184[102:Spt:174179.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 174186[102:Res:174184.0,61.1] always3(s43) || -> . % 76.16/76.37 174187[102:SSi:174186.0,78259.0,78262.0,165535.0,174050.0,174174.0] || -> . % 76.16/76.37 174188[102:Spt:174187.0,174179.0,174184.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 174189[102:Spt:174187.0,174179.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 174193[102:Res:174189.0,61.1] always3(s44) || -> . % 76.16/76.37 174194[102:SSi:174193.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 174195[100:Spt:174194.0,174049.0,174050.0] || until2p7(s43)*+ -> . % 76.16/76.37 174196[100:Spt:174194.0,174049.1] || -> node4(s42)*. % 76.16/76.37 174198[100:MRR:792.0,174196.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 174201[100:Res:53.1,174198.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 174203[101:Spt:174201.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 174205[101:Res:174203.0,61.1] always3(s42) || -> . % 76.16/76.37 174206[101:SSi:174205.0,78254.0,78258.0,165534.0,174048.0,174196.0] || -> . % 76.16/76.37 174207[101:Spt:174206.0,174201.0,174203.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 174208[101:Spt:174206.0,174201.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 174212[101:Res:174208.0,61.1] always3(s43) || -> . % 76.16/76.37 174213[101:SSi:174212.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 174214[99:Spt:174213.0,174047.0,174048.0] || until2p7(s42)*+ -> . % 76.16/76.37 174215[99:Spt:174213.0,174047.1] || -> node4(s41)*. % 76.16/76.37 174217[99:MRR:795.0,174215.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 174220[99:Res:53.1,174217.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 174222[100:Spt:174220.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 174224[100:Res:174222.0,61.1] always3(s41) || -> . % 76.16/76.37 174225[100:SSi:174224.0,78250.0,78253.0,165533.0,174046.0,174215.0] || -> . % 76.16/76.37 174226[100:Spt:174225.0,174220.0,174222.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 174227[100:Spt:174225.0,174220.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 174231[100:Res:174227.0,61.1] always3(s42) || -> . % 76.16/76.37 174232[100:SSi:174231.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 174233[98:Spt:174232.0,174045.0,174046.0] || until2p7(s41)*+ -> . % 76.16/76.37 174234[98:Spt:174232.0,174045.1] || -> node4(s40)*. % 76.16/76.37 174236[98:MRR:798.0,174234.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 174239[98:Res:53.1,174236.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 174241[99:Spt:174239.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 174243[99:Res:174241.0,61.1] always3(s40) || -> . % 76.16/76.37 174244[99:SSi:174243.0,78245.0,78249.0,165532.0,174044.0,174234.0] || -> . % 76.16/76.37 174245[99:Spt:174244.0,174239.0,174241.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 174246[99:Spt:174244.0,174239.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 174250[99:Res:174246.0,61.1] always3(s41) || -> . % 76.16/76.37 174251[99:SSi:174250.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 174252[97:Spt:174251.0,174043.0,174044.0] || until2p7(s40)*+ -> . % 76.16/76.37 174253[97:Spt:174251.0,174043.1] || -> node4(s39)*. % 76.16/76.37 174255[97:MRR:801.0,174253.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 174258[97:Res:53.1,174255.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 174263[98:Spt:174258.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 174265[98:Res:174263.0,61.1] always3(s39) || -> . % 76.16/76.37 174266[98:SSi:174265.0,78241.0,78244.0,165531.0,174042.0,174253.0] || -> . % 76.16/76.37 174267[98:Spt:174266.0,174258.0,174263.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 174268[98:Spt:174266.0,174258.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 174272[98:Res:174268.0,61.1] always3(s40) || -> . % 76.16/76.37 174273[98:SSi:174272.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 174274[96:Spt:174273.0,174041.0,174042.0] || until2p7(s39)*+ -> . % 76.16/76.37 174275[96:Spt:174273.0,174041.1] || -> node4(s38)*. % 76.16/76.37 174277[96:MRR:804.0,174275.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 174280[96:Res:53.1,174277.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 174282[97:Spt:174280.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 174284[97:Res:174282.0,61.1] always3(s38) || -> . % 76.16/76.37 174285[97:SSi:174284.0,78236.0,78240.0,165530.0,174040.0,174275.0] || -> . % 76.16/76.37 174286[97:Spt:174285.0,174280.0,174282.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 174287[97:Spt:174285.0,174280.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 174291[97:Res:174287.0,61.1] always3(s39) || -> . % 76.16/76.37 174292[97:SSi:174291.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 174293[95:Spt:174292.0,174039.0,174040.0] || until2p7(s38)*+ -> . % 76.16/76.37 174294[95:Spt:174292.0,174039.1] || -> node4(s37)*. % 76.16/76.37 174296[95:MRR:807.0,174294.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 174299[95:Res:53.1,174296.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 174301[96:Spt:174299.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 174303[96:Res:174301.0,61.1] always3(s37) || -> . % 76.16/76.37 174304[96:SSi:174303.0,78232.0,78235.0,165529.0,174038.0,174294.0] || -> . % 76.16/76.37 174305[96:Spt:174304.0,174299.0,174301.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 174306[96:Spt:174304.0,174299.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 174310[96:Res:174306.0,61.1] always3(s38) || -> . % 76.16/76.37 174311[96:SSi:174310.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 174312[94:Spt:174311.0,174037.0,174038.0] || until2p7(s37)*+ -> . % 76.16/76.37 174313[94:Spt:174311.0,174037.1] || -> node4(s36)*. % 76.16/76.37 174315[94:MRR:810.0,174313.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 174318[94:Res:53.1,174315.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 174320[95:Spt:174318.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 174322[95:Res:174320.0,61.1] always3(s36) || -> . % 76.16/76.37 174323[95:SSi:174322.0,78227.0,78231.0,165528.0,174036.0,174313.0] || -> . % 76.16/76.37 174324[95:Spt:174323.0,174318.0,174320.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 174325[95:Spt:174323.0,174318.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 174329[95:Res:174325.0,61.1] always3(s37) || -> . % 76.16/76.37 174330[95:SSi:174329.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 174331[93:Spt:174330.0,174035.0,174036.0] || until2p7(s36)*+ -> . % 76.16/76.37 174332[93:Spt:174330.0,174035.1] || -> node4(s35)*. % 76.16/76.37 174334[93:MRR:813.0,174332.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 174337[93:Res:53.1,174334.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 174342[94:Spt:174337.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 174344[94:Res:174342.0,61.1] always3(s35) || -> . % 76.16/76.37 174345[94:SSi:174344.0,78223.0,78226.0,165527.0,174034.0,174332.0] || -> . % 76.16/76.37 174346[94:Spt:174345.0,174337.0,174342.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 174347[94:Spt:174345.0,174337.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 174351[94:Res:174347.0,61.1] always3(s36) || -> . % 76.16/76.37 174352[94:SSi:174351.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 174353[92:Spt:174352.0,174033.0,174034.0] || until2p7(s35)*+ -> . % 76.16/76.37 174354[92:Spt:174352.0,174033.1] || -> node4(s34)*. % 76.16/76.37 174356[92:MRR:816.0,174354.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 174359[92:Res:53.1,174356.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 174361[93:Spt:174359.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 174363[93:Res:174361.0,61.1] always3(s34) || -> . % 76.16/76.37 174364[93:SSi:174363.0,78218.0,78222.0,165526.0,174032.0,174354.0] || -> . % 76.16/76.37 174365[93:Spt:174364.0,174359.0,174361.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 174366[93:Spt:174364.0,174359.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 174370[93:Res:174366.0,61.1] always3(s35) || -> . % 76.16/76.37 174371[93:SSi:174370.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 174372[91:Spt:174371.0,174031.0,174032.0] || until2p7(s34)*+ -> . % 76.16/76.37 174373[91:Spt:174371.0,174031.1] || -> node4(s33)*. % 76.16/76.37 174375[91:MRR:819.0,174373.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 174378[91:Res:53.1,174375.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 174380[92:Spt:174378.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 174382[92:Res:174380.0,61.1] always3(s33) || -> . % 76.16/76.37 174383[92:SSi:174382.0,78214.0,78217.0,165525.0,174030.0,174373.0] || -> . % 76.16/76.37 174384[92:Spt:174383.0,174378.0,174380.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 174385[92:Spt:174383.0,174378.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 174389[92:Res:174385.0,61.1] always3(s34) || -> . % 76.16/76.37 174390[92:SSi:174389.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 174391[90:Spt:174390.0,174029.0,174030.0] || until2p7(s33)*+ -> . % 76.16/76.37 174392[90:Spt:174390.0,174029.1] || -> node4(s32)*. % 76.16/76.37 174394[90:MRR:822.0,174392.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 174397[90:Res:53.1,174394.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 174399[91:Spt:174397.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 174401[91:Res:174399.0,61.1] always3(s32) || -> . % 76.16/76.37 174402[91:SSi:174401.0,78209.0,78213.0,165524.0,174028.0,174392.0] || -> . % 76.16/76.37 174403[91:Spt:174402.0,174397.0,174399.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 174404[91:Spt:174402.0,174397.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 174408[91:Res:174404.0,61.1] always3(s33) || -> . % 76.16/76.37 174409[91:SSi:174408.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 174410[89:Spt:174409.0,174027.0,174028.0] || until2p7(s32)*+ -> . % 76.16/76.37 174411[89:Spt:174409.0,174027.1] || -> node4(s31)*. % 76.16/76.37 174413[89:MRR:825.0,174411.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 174416[89:Res:53.1,174413.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 174421[90:Spt:174416.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 174423[90:Res:174421.0,61.1] always3(s31) || -> . % 76.16/76.37 174424[90:SSi:174423.0,78205.0,78208.0,165523.0,174026.0,174411.0] || -> . % 76.16/76.37 174425[90:Spt:174424.0,174416.0,174421.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 174426[90:Spt:174424.0,174416.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 174430[90:Res:174426.0,61.1] always3(s32) || -> . % 76.16/76.37 174431[90:SSi:174430.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 174432[88:Spt:174431.0,174025.0,174026.0] || until2p7(s31)*+ -> . % 76.16/76.37 174433[88:Spt:174431.0,174025.1] || -> node4(s30)*. % 76.16/76.37 174435[88:MRR:828.0,174433.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 174438[88:Res:53.1,174435.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 174440[89:Spt:174438.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 174442[89:Res:174440.0,61.1] always3(s30) || -> . % 76.16/76.37 174443[89:SSi:174442.0,78200.0,78204.0,165522.0,174024.0,174433.0] || -> . % 76.16/76.37 174444[89:Spt:174443.0,174438.0,174440.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.37 174445[89:Spt:174443.0,174438.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 174449[89:Res:174445.0,61.1] always3(s31) || -> . % 76.16/76.37 174450[89:SSi:174449.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 174451[87:Spt:174450.0,174023.0,174024.0] || until2p7(s30)*+ -> . % 76.16/76.37 174452[87:Spt:174450.0,174023.1] || -> node4(s29)*. % 76.16/76.37 174454[87:MRR:831.0,174452.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.37 174457[87:Res:53.1,174454.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.37 174459[88:Spt:174457.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 174461[88:Res:174459.0,61.1] always3(s29) || -> . % 76.16/76.37 174462[88:SSi:174461.0,78196.0,78199.0,165521.0,174022.0,174452.0] || -> . % 76.16/76.37 174463[88:Spt:174462.0,174457.0,174459.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.37 174464[88:Spt:174462.0,174457.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 174468[88:Res:174464.0,61.1] always3(s30) || -> . % 76.16/76.37 174469[88:SSi:174468.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 174470[86:Spt:174469.0,174021.0,174022.0] || until2p7(s29)*+ -> . % 76.16/76.37 174471[86:Spt:174469.0,174021.1] || -> node4(s28)*. % 76.16/76.37 174473[86:MRR:834.0,174471.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.37 174476[86:Res:53.1,174473.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.37 174478[87:Spt:174476.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 174480[87:Res:174478.0,61.1] always3(s28) || -> . % 76.16/76.37 174481[87:SSi:174480.0,78191.0,78195.0,165520.0,174020.0,174471.0] || -> . % 76.16/76.37 174482[87:Spt:174481.0,174476.0,174478.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.37 174483[87:Spt:174481.0,174476.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 174487[87:Res:174483.0,61.1] always3(s29) || -> . % 76.16/76.37 174488[87:SSi:174487.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.37 174489[85:Spt:174488.0,174019.0,174020.0] || until2p7(s28)*+ -> . % 76.16/76.37 174490[85:Spt:174488.0,174019.1] || -> node4(s27)*. % 76.16/76.37 174492[85:MRR:837.0,174490.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.37 174495[85:Res:53.1,174492.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.37 174500[86:Spt:174495.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 174502[86:Res:174500.0,61.1] always3(s27) || -> . % 76.16/76.37 174503[86:SSi:174502.0,78187.0,78190.0,165519.0,174018.0,174490.0] || -> . % 76.16/76.37 174504[86:Spt:174503.0,174495.0,174500.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.37 174505[86:Spt:174503.0,174495.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 174509[86:Res:174505.0,61.1] always3(s28) || -> . % 76.16/76.37 174510[86:SSi:174509.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.37 174511[84:Spt:174510.0,174017.0,174018.0] || until2p7(s27)*+ -> . % 76.16/76.37 174512[84:Spt:174510.0,174017.1] || -> node4(s26)*. % 76.16/76.37 174514[84:MRR:840.0,174512.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.37 174517[84:Res:53.1,174514.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.37 174519[85:Spt:174517.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 174521[85:Res:174519.0,61.1] always3(s26) || -> . % 76.16/76.37 174522[85:SSi:174521.0,78182.0,78186.0,165518.0,174016.0,174512.0] || -> . % 76.16/76.37 174523[85:Spt:174522.0,174517.0,174519.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.37 174524[85:Spt:174522.0,174517.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 174528[85:Res:174524.0,61.1] always3(s27) || -> . % 76.16/76.37 174529[85:SSi:174528.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.37 174530[83:Spt:174529.0,174015.0,174016.0] || until2p7(s26)*+ -> . % 76.16/76.37 174531[83:Spt:174529.0,174015.1] || -> node4(s25)*. % 76.16/76.37 174533[83:MRR:843.0,174531.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.37 174536[83:Res:53.1,174533.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.37 174538[84:Spt:174536.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 174540[84:Res:174538.0,61.1] always3(s25) || -> . % 76.16/76.37 174541[84:SSi:174540.0,78178.0,78181.0,165517.0,174014.0,174531.0] || -> . % 76.16/76.37 174542[84:Spt:174541.0,174536.0,174538.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.37 174543[84:Spt:174541.0,174536.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 174547[84:Res:174543.0,61.1] always3(s26) || -> . % 76.16/76.37 174548[84:SSi:174547.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.37 174549[82:Spt:174548.0,174013.0,174014.0] || until2p7(s25)*+ -> . % 76.16/76.37 174550[82:Spt:174548.0,174013.1] || -> node4(s24)*. % 76.16/76.37 174552[82:MRR:846.0,174550.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.37 174555[82:Res:53.1,174552.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.37 174557[82:MRR:174555.0,174003.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 174559[82:Res:174557.0,61.1] always3(s25) || -> . % 76.16/76.37 174560[82:SSi:174559.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.37 174561[80:Spt:174560.0,173902.0,173905.0] || trans(s49,s24)*+ -> . % 76.16/76.37 174562[80:Spt:174560.0,173902.1,173902.2,173902.3,173902.4,173902.5,173902.6,173902.7,173902.8,173902.9,173902.10,173902.11,173902.12,173902.13,173902.14,173902.15,173902.16,173902.17,173902.18,173902.19] || -> trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 174564[80:MRR:173904.1,174561.0] xuntil6(s49) || -> trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 174565[81:Spt:174562.0] || -> trans(s49,s23)*. % 76.16/76.37 174566[81:Res:174565.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s23)*. % 76.16/76.37 174568[81:Res:174565.0,60.0] || -> node2(s49,s23)*. % 76.16/76.37 174569[81:SSi:174566.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s23)*. % 76.16/76.37 174570[81:Res:174568.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 174659[81:SoR:174570.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 174661[81:SoR:174659.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)* xuntil6(s49). % 76.16/76.37 174662[81:SSi:174661.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s23,c_busy)* xuntil6(s49). % 76.16/76.37 174663[82:Spt:174662.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 174665[82:Res:174663.0,61.1] always3(s23) || -> . % 76.16/76.37 174666[82:SSi:174665.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.37 174667[82:Spt:174666.0,174662.1,174663.0] || m_main_v_state(s23,c_busy)*+ -> . % 76.16/76.37 174668[82:Spt:174666.0,174662.0,174662.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 174672[82:MRR:174659.2,174667.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 174673[82:Res:53.1,174668.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 174675[82:MRR:174673.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 174676[82:MRR:174569.0,174675.0] || -> until2p7(s23)*. % 76.16/76.37 174677[82:MRR:219.0,174676.0] || -> until2p7(s24)* node4(s23). % 76.16/76.37 174678[83:Spt:174677.0] || -> until2p7(s24)*. % 76.16/76.37 174679[83:MRR:220.0,174678.0] || -> until2p7(s25)* node4(s24). % 76.16/76.37 174680[84:Spt:174679.0] || -> until2p7(s25)*. % 76.16/76.37 174681[84:MRR:221.0,174680.0] || -> until2p7(s26)* node4(s25). % 76.16/76.37 174682[85:Spt:174681.0] || -> until2p7(s26)*. % 76.16/76.37 174683[85:MRR:222.0,174682.0] || -> until2p7(s27)* node4(s26). % 76.16/76.37 174684[86:Spt:174683.0] || -> until2p7(s27)*. % 76.16/76.37 174685[86:MRR:223.0,174684.0] || -> until2p7(s28)* node4(s27). % 76.16/76.37 174686[87:Spt:174685.0] || -> until2p7(s28)*. % 76.16/76.37 174687[87:MRR:224.0,174686.0] || -> until2p7(s29)* node4(s28). % 76.16/76.37 174688[88:Spt:174687.0] || -> until2p7(s29)*. % 76.16/76.37 174689[88:MRR:225.0,174688.0] || -> until2p7(s30)* node4(s29). % 76.16/76.37 174690[89:Spt:174689.0] || -> until2p7(s30)*. % 76.16/76.37 174691[89:MRR:226.0,174690.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 174692[90:Spt:174691.0] || -> until2p7(s31)*. % 76.16/76.37 174693[90:MRR:227.0,174692.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 174694[91:Spt:174693.0] || -> until2p7(s32)*. % 76.16/76.37 174695[91:MRR:228.0,174694.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 174696[92:Spt:174695.0] || -> until2p7(s33)*. % 76.16/76.37 174697[92:MRR:229.0,174696.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 174698[93:Spt:174697.0] || -> until2p7(s34)*. % 76.16/76.37 174699[93:MRR:230.0,174698.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 174700[94:Spt:174699.0] || -> until2p7(s35)*. % 76.16/76.37 174701[94:MRR:231.0,174700.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 174702[95:Spt:174701.0] || -> until2p7(s36)*. % 76.16/76.37 174703[95:MRR:232.0,174702.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 174704[96:Spt:174703.0] || -> until2p7(s37)*. % 76.16/76.37 174705[96:MRR:235.0,174704.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 174706[97:Spt:174705.0] || -> until2p7(s38)*. % 76.16/76.37 174707[97:MRR:236.0,174706.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 174708[98:Spt:174707.0] || -> until2p7(s39)*. % 76.16/76.37 174709[98:MRR:237.0,174708.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 174710[99:Spt:174709.0] || -> until2p7(s40)*. % 76.16/76.37 174711[99:MRR:238.0,174710.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 174712[100:Spt:174711.0] || -> until2p7(s41)*. % 76.16/76.37 174713[100:MRR:239.0,174712.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 174714[101:Spt:174713.0] || -> until2p7(s42)*. % 76.16/76.37 174715[101:MRR:240.0,174714.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 174716[102:Spt:174715.0] || -> until2p7(s43)*. % 76.16/76.37 174717[102:MRR:241.0,174716.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 174718[103:Spt:174717.0] || -> until2p7(s44)*. % 76.16/76.37 174719[103:MRR:539.0,174718.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 174720[104:Spt:174719.0] || -> until2p7(s45)*. % 76.16/76.37 174721[104:MRR:544.0,174720.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 174722[105:Spt:174721.0] || -> until2p7(s46)*. % 76.16/76.37 174723[105:MRR:549.0,174722.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 174724[106:Spt:174723.0] || -> until2p7(s47)*. % 76.16/76.37 174725[106:MRR:554.0,174724.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 174726[107:Spt:174725.0] || -> until2p7(s48)*. % 76.16/76.37 174727[107:MRR:559.0,174726.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 174728[108:Spt:174727.0] || -> until2p7(s49)*. % 76.16/76.37 174729[108:MRR:194.0,174728.0] || -> node4(s49)*. % 76.16/76.37 174730[108:MRR:174672.0,174729.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 174734[108:Res:53.1,174730.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 174736[108:MRR:174734.0,78381.0] || -> . % 76.16/76.37 174737[108:Spt:174736.0,174727.0,174728.0] || until2p7(s49)*+ -> . % 76.16/76.37 174738[108:Spt:174736.0,174727.1] || -> node4(s48)*. % 76.16/76.37 174739[108:MRR:78384.0,174738.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 174742[108:Res:53.1,174739.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 174745[108:Res:174742.0,61.1] always3(s48) || -> . % 76.16/76.37 174746[108:SSi:174745.0,78281.0,78387.0,165540.0,174726.0,174738.0] || -> . % 76.16/76.37 174747[107:Spt:174746.0,174725.0,174726.0] || until2p7(s48)*+ -> . % 76.16/76.37 174748[107:Spt:174746.0,174725.1] || -> node4(s47)*. % 76.16/76.37 174750[107:MRR:777.0,174748.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 174762[107:Res:53.1,174750.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 174764[108:Spt:174762.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 174766[108:Res:174764.0,61.1] always3(s47) || -> . % 76.16/76.37 174767[108:SSi:174766.0,78277.0,78280.0,165539.0,174724.0,174748.0] || -> . % 76.16/76.37 174768[108:Spt:174767.0,174762.0,174764.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 174769[108:Spt:174767.0,174762.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 174773[108:Res:174769.0,61.1] always3(s48) || -> . % 76.16/76.37 174774[108:SSi:174773.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 174775[106:Spt:174774.0,174723.0,174724.0] || until2p7(s47)*+ -> . % 76.16/76.37 174776[106:Spt:174774.0,174723.1] || -> node4(s46)*. % 76.16/76.37 174778[106:MRR:780.0,174776.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 174785[106:Res:53.1,174778.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 174790[107:Spt:174785.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 174792[107:Res:174790.0,61.1] always3(s46) || -> . % 76.16/76.37 174793[107:SSi:174792.0,78272.0,78276.0,165538.0,174722.0,174776.0] || -> . % 76.16/76.37 174794[107:Spt:174793.0,174785.0,174790.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 174795[107:Spt:174793.0,174785.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 174799[107:Res:174795.0,61.1] always3(s47) || -> . % 76.16/76.37 174800[107:SSi:174799.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 174801[105:Spt:174800.0,174721.0,174722.0] || until2p7(s46)*+ -> . % 76.16/76.37 174802[105:Spt:174800.0,174721.1] || -> node4(s45)*. % 76.16/76.37 174804[105:MRR:783.0,174802.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 174807[105:Res:53.1,174804.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 174809[106:Spt:174807.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 174811[106:Res:174809.0,61.1] always3(s45) || -> . % 76.16/76.37 174812[106:SSi:174811.0,78268.0,78271.0,165537.0,174720.0,174802.0] || -> . % 76.16/76.37 174813[106:Spt:174812.0,174807.0,174809.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 174814[106:Spt:174812.0,174807.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 174818[106:Res:174814.0,61.1] always3(s46) || -> . % 76.16/76.37 174819[106:SSi:174818.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 174820[104:Spt:174819.0,174719.0,174720.0] || until2p7(s45)*+ -> . % 76.16/76.37 174821[104:Spt:174819.0,174719.1] || -> node4(s44)*. % 76.16/76.37 174823[104:MRR:786.0,174821.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 174826[104:Res:53.1,174823.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 174828[105:Spt:174826.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 174830[105:Res:174828.0,61.1] always3(s44) || -> . % 76.16/76.37 174831[105:SSi:174830.0,78263.0,78267.0,165536.0,174718.0,174821.0] || -> . % 76.16/76.37 174832[105:Spt:174831.0,174826.0,174828.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 174833[105:Spt:174831.0,174826.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 174837[105:Res:174833.0,61.1] always3(s45) || -> . % 76.16/76.37 174838[105:SSi:174837.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 174839[103:Spt:174838.0,174717.0,174718.0] || until2p7(s44)*+ -> . % 76.16/76.37 174840[103:Spt:174838.0,174717.1] || -> node4(s43)*. % 76.16/76.37 174842[103:MRR:789.0,174840.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 174845[103:Res:53.1,174842.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 174847[104:Spt:174845.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 174849[104:Res:174847.0,61.1] always3(s43) || -> . % 76.16/76.37 174850[104:SSi:174849.0,78259.0,78262.0,165535.0,174716.0,174840.0] || -> . % 76.16/76.37 174851[104:Spt:174850.0,174845.0,174847.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 174852[104:Spt:174850.0,174845.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 174856[104:Res:174852.0,61.1] always3(s44) || -> . % 76.16/76.37 174857[104:SSi:174856.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 174858[102:Spt:174857.0,174715.0,174716.0] || until2p7(s43)*+ -> . % 76.16/76.37 174859[102:Spt:174857.0,174715.1] || -> node4(s42)*. % 76.16/76.37 174861[102:MRR:792.0,174859.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 174864[102:Res:53.1,174861.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 174869[103:Spt:174864.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 174871[103:Res:174869.0,61.1] always3(s42) || -> . % 76.16/76.37 174872[103:SSi:174871.0,78254.0,78258.0,165534.0,174714.0,174859.0] || -> . % 76.16/76.37 174873[103:Spt:174872.0,174864.0,174869.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 174874[103:Spt:174872.0,174864.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 174878[103:Res:174874.0,61.1] always3(s43) || -> . % 76.16/76.37 174879[103:SSi:174878.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 174880[101:Spt:174879.0,174713.0,174714.0] || until2p7(s42)*+ -> . % 76.16/76.37 174881[101:Spt:174879.0,174713.1] || -> node4(s41)*. % 76.16/76.37 174883[101:MRR:795.0,174881.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 174886[101:Res:53.1,174883.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 174888[102:Spt:174886.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 174890[102:Res:174888.0,61.1] always3(s41) || -> . % 76.16/76.37 174891[102:SSi:174890.0,78250.0,78253.0,165533.0,174712.0,174881.0] || -> . % 76.16/76.37 174892[102:Spt:174891.0,174886.0,174888.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 174893[102:Spt:174891.0,174886.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 174897[102:Res:174893.0,61.1] always3(s42) || -> . % 76.16/76.37 174898[102:SSi:174897.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 174899[100:Spt:174898.0,174711.0,174712.0] || until2p7(s41)*+ -> . % 76.16/76.37 174900[100:Spt:174898.0,174711.1] || -> node4(s40)*. % 76.16/76.37 174902[100:MRR:798.0,174900.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 174905[100:Res:53.1,174902.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 174907[101:Spt:174905.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 174909[101:Res:174907.0,61.1] always3(s40) || -> . % 76.16/76.37 174910[101:SSi:174909.0,78245.0,78249.0,165532.0,174710.0,174900.0] || -> . % 76.16/76.37 174911[101:Spt:174910.0,174905.0,174907.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 174912[101:Spt:174910.0,174905.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 174916[101:Res:174912.0,61.1] always3(s41) || -> . % 76.16/76.37 174917[101:SSi:174916.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 174918[99:Spt:174917.0,174709.0,174710.0] || until2p7(s40)*+ -> . % 76.16/76.37 174919[99:Spt:174917.0,174709.1] || -> node4(s39)*. % 76.16/76.37 174921[99:MRR:801.0,174919.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 174924[99:Res:53.1,174921.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 174926[100:Spt:174924.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 174928[100:Res:174926.0,61.1] always3(s39) || -> . % 76.16/76.37 174929[100:SSi:174928.0,78241.0,78244.0,165531.0,174708.0,174919.0] || -> . % 76.16/76.37 174930[100:Spt:174929.0,174924.0,174926.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 174931[100:Spt:174929.0,174924.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 174935[100:Res:174931.0,61.1] always3(s40) || -> . % 76.16/76.37 174936[100:SSi:174935.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 174937[98:Spt:174936.0,174707.0,174708.0] || until2p7(s39)*+ -> . % 76.16/76.37 174938[98:Spt:174936.0,174707.1] || -> node4(s38)*. % 76.16/76.37 174940[98:MRR:804.0,174938.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 174943[98:Res:53.1,174940.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 174948[99:Spt:174943.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 174950[99:Res:174948.0,61.1] always3(s38) || -> . % 76.16/76.37 174951[99:SSi:174950.0,78236.0,78240.0,165530.0,174706.0,174938.0] || -> . % 76.16/76.37 174952[99:Spt:174951.0,174943.0,174948.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 174953[99:Spt:174951.0,174943.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 174957[99:Res:174953.0,61.1] always3(s39) || -> . % 76.16/76.37 174958[99:SSi:174957.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 174959[97:Spt:174958.0,174705.0,174706.0] || until2p7(s38)*+ -> . % 76.16/76.37 174960[97:Spt:174958.0,174705.1] || -> node4(s37)*. % 76.16/76.37 174962[97:MRR:807.0,174960.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 174965[97:Res:53.1,174962.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 174967[98:Spt:174965.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 174969[98:Res:174967.0,61.1] always3(s37) || -> . % 76.16/76.37 174970[98:SSi:174969.0,78232.0,78235.0,165529.0,174704.0,174960.0] || -> . % 76.16/76.37 174971[98:Spt:174970.0,174965.0,174967.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 174972[98:Spt:174970.0,174965.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 174976[98:Res:174972.0,61.1] always3(s38) || -> . % 76.16/76.37 174977[98:SSi:174976.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 174978[96:Spt:174977.0,174703.0,174704.0] || until2p7(s37)*+ -> . % 76.16/76.37 174979[96:Spt:174977.0,174703.1] || -> node4(s36)*. % 76.16/76.37 174981[96:MRR:810.0,174979.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 174984[96:Res:53.1,174981.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 174986[97:Spt:174984.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 174988[97:Res:174986.0,61.1] always3(s36) || -> . % 76.16/76.37 174989[97:SSi:174988.0,78227.0,78231.0,165528.0,174702.0,174979.0] || -> . % 76.16/76.37 174990[97:Spt:174989.0,174984.0,174986.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 174991[97:Spt:174989.0,174984.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 174995[97:Res:174991.0,61.1] always3(s37) || -> . % 76.16/76.37 174996[97:SSi:174995.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 174997[95:Spt:174996.0,174701.0,174702.0] || until2p7(s36)*+ -> . % 76.16/76.37 174998[95:Spt:174996.0,174701.1] || -> node4(s35)*. % 76.16/76.37 175000[95:MRR:813.0,174998.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 175003[95:Res:53.1,175000.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 175005[96:Spt:175003.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 175007[96:Res:175005.0,61.1] always3(s35) || -> . % 76.16/76.37 175008[96:SSi:175007.0,78223.0,78226.0,165527.0,174700.0,174998.0] || -> . % 76.16/76.37 175009[96:Spt:175008.0,175003.0,175005.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 175010[96:Spt:175008.0,175003.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 175014[96:Res:175010.0,61.1] always3(s36) || -> . % 76.16/76.37 175015[96:SSi:175014.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 175016[94:Spt:175015.0,174699.0,174700.0] || until2p7(s35)*+ -> . % 76.16/76.37 175017[94:Spt:175015.0,174699.1] || -> node4(s34)*. % 76.16/76.37 175019[94:MRR:816.0,175017.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 175022[94:Res:53.1,175019.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 175027[95:Spt:175022.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 175029[95:Res:175027.0,61.1] always3(s34) || -> . % 76.16/76.37 175030[95:SSi:175029.0,78218.0,78222.0,165526.0,174698.0,175017.0] || -> . % 76.16/76.37 175031[95:Spt:175030.0,175022.0,175027.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 175032[95:Spt:175030.0,175022.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 175036[95:Res:175032.0,61.1] always3(s35) || -> . % 76.16/76.37 175037[95:SSi:175036.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 175038[93:Spt:175037.0,174697.0,174698.0] || until2p7(s34)*+ -> . % 76.16/76.37 175039[93:Spt:175037.0,174697.1] || -> node4(s33)*. % 76.16/76.37 175041[93:MRR:819.0,175039.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 175044[93:Res:53.1,175041.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 175046[94:Spt:175044.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 175048[94:Res:175046.0,61.1] always3(s33) || -> . % 76.16/76.37 175049[94:SSi:175048.0,78214.0,78217.0,165525.0,174696.0,175039.0] || -> . % 76.16/76.37 175050[94:Spt:175049.0,175044.0,175046.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 175051[94:Spt:175049.0,175044.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 175055[94:Res:175051.0,61.1] always3(s34) || -> . % 76.16/76.37 175056[94:SSi:175055.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 175057[92:Spt:175056.0,174695.0,174696.0] || until2p7(s33)*+ -> . % 76.16/76.37 175058[92:Spt:175056.0,174695.1] || -> node4(s32)*. % 76.16/76.37 175060[92:MRR:822.0,175058.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 175063[92:Res:53.1,175060.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 175065[93:Spt:175063.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 175067[93:Res:175065.0,61.1] always3(s32) || -> . % 76.16/76.37 175068[93:SSi:175067.0,78209.0,78213.0,165524.0,174694.0,175058.0] || -> . % 76.16/76.37 175069[93:Spt:175068.0,175063.0,175065.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 175070[93:Spt:175068.0,175063.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 175074[93:Res:175070.0,61.1] always3(s33) || -> . % 76.16/76.37 175075[93:SSi:175074.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 175076[91:Spt:175075.0,174693.0,174694.0] || until2p7(s32)*+ -> . % 76.16/76.37 175077[91:Spt:175075.0,174693.1] || -> node4(s31)*. % 76.16/76.37 175079[91:MRR:825.0,175077.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 175082[91:Res:53.1,175079.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 175084[92:Spt:175082.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 175086[92:Res:175084.0,61.1] always3(s31) || -> . % 76.16/76.37 175087[92:SSi:175086.0,78205.0,78208.0,165523.0,174692.0,175077.0] || -> . % 76.16/76.37 175088[92:Spt:175087.0,175082.0,175084.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 175089[92:Spt:175087.0,175082.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 175093[92:Res:175089.0,61.1] always3(s32) || -> . % 76.16/76.37 175094[92:SSi:175093.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 175095[90:Spt:175094.0,174691.0,174692.0] || until2p7(s31)*+ -> . % 76.16/76.37 175096[90:Spt:175094.0,174691.1] || -> node4(s30)*. % 76.16/76.37 175098[90:MRR:828.0,175096.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 175101[90:Res:53.1,175098.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 175106[91:Spt:175101.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 175108[91:Res:175106.0,61.1] always3(s30) || -> . % 76.16/76.37 175109[91:SSi:175108.0,78200.0,78204.0,165522.0,174690.0,175096.0] || -> . % 76.16/76.37 175110[91:Spt:175109.0,175101.0,175106.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.37 175111[91:Spt:175109.0,175101.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 175115[91:Res:175111.0,61.1] always3(s31) || -> . % 76.16/76.37 175116[91:SSi:175115.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 175117[89:Spt:175116.0,174689.0,174690.0] || until2p7(s30)*+ -> . % 76.16/76.37 175118[89:Spt:175116.0,174689.1] || -> node4(s29)*. % 76.16/76.37 175120[89:MRR:831.0,175118.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.37 175123[89:Res:53.1,175120.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.37 175125[90:Spt:175123.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 175127[90:Res:175125.0,61.1] always3(s29) || -> . % 76.16/76.37 175128[90:SSi:175127.0,78196.0,78199.0,165521.0,174688.0,175118.0] || -> . % 76.16/76.37 175129[90:Spt:175128.0,175123.0,175125.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.37 175130[90:Spt:175128.0,175123.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 175134[90:Res:175130.0,61.1] always3(s30) || -> . % 76.16/76.37 175135[90:SSi:175134.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 175136[88:Spt:175135.0,174687.0,174688.0] || until2p7(s29)*+ -> . % 76.16/76.37 175137[88:Spt:175135.0,174687.1] || -> node4(s28)*. % 76.16/76.37 175139[88:MRR:834.0,175137.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.37 175142[88:Res:53.1,175139.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.37 175144[89:Spt:175142.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 175146[89:Res:175144.0,61.1] always3(s28) || -> . % 76.16/76.37 175147[89:SSi:175146.0,78191.0,78195.0,165520.0,174686.0,175137.0] || -> . % 76.16/76.37 175148[89:Spt:175147.0,175142.0,175144.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.37 175149[89:Spt:175147.0,175142.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 175153[89:Res:175149.0,61.1] always3(s29) || -> . % 76.16/76.37 175154[89:SSi:175153.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.37 175155[87:Spt:175154.0,174685.0,174686.0] || until2p7(s28)*+ -> . % 76.16/76.37 175156[87:Spt:175154.0,174685.1] || -> node4(s27)*. % 76.16/76.37 175158[87:MRR:837.0,175156.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.37 175161[87:Res:53.1,175158.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.37 175163[88:Spt:175161.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 175165[88:Res:175163.0,61.1] always3(s27) || -> . % 76.16/76.37 175166[88:SSi:175165.0,78187.0,78190.0,165519.0,174684.0,175156.0] || -> . % 76.16/76.37 175167[88:Spt:175166.0,175161.0,175163.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.37 175168[88:Spt:175166.0,175161.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 175172[88:Res:175168.0,61.1] always3(s28) || -> . % 76.16/76.37 175173[88:SSi:175172.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.37 175174[86:Spt:175173.0,174683.0,174684.0] || until2p7(s27)*+ -> . % 76.16/76.37 175175[86:Spt:175173.0,174683.1] || -> node4(s26)*. % 76.16/76.37 175177[86:MRR:840.0,175175.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.37 175180[86:Res:53.1,175177.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.37 175185[87:Spt:175180.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 175187[87:Res:175185.0,61.1] always3(s26) || -> . % 76.16/76.37 175188[87:SSi:175187.0,78182.0,78186.0,165518.0,174682.0,175175.0] || -> . % 76.16/76.37 175189[87:Spt:175188.0,175180.0,175185.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.37 175190[87:Spt:175188.0,175180.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 175194[87:Res:175190.0,61.1] always3(s27) || -> . % 76.16/76.37 175195[87:SSi:175194.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.37 175196[85:Spt:175195.0,174681.0,174682.0] || until2p7(s26)*+ -> . % 76.16/76.37 175197[85:Spt:175195.0,174681.1] || -> node4(s25)*. % 76.16/76.37 175199[85:MRR:843.0,175197.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.37 175202[85:Res:53.1,175199.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.37 175204[86:Spt:175202.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 175206[86:Res:175204.0,61.1] always3(s25) || -> . % 76.16/76.37 175207[86:SSi:175206.0,78178.0,78181.0,165517.0,174680.0,175197.0] || -> . % 76.16/76.37 175208[86:Spt:175207.0,175202.0,175204.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.37 175209[86:Spt:175207.0,175202.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 175213[86:Res:175209.0,61.1] always3(s26) || -> . % 76.16/76.37 175214[86:SSi:175213.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.37 175215[84:Spt:175214.0,174679.0,174680.0] || until2p7(s25)*+ -> . % 76.16/76.37 175216[84:Spt:175214.0,174679.1] || -> node4(s24)*. % 76.16/76.37 175218[84:MRR:846.0,175216.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.37 175221[84:Res:53.1,175218.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.37 175223[85:Spt:175221.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 175225[85:Res:175223.0,61.1] always3(s24) || -> . % 76.16/76.37 175226[85:SSi:175225.0,78173.0,78177.0,165516.0,174678.0,175216.0] || -> . % 76.16/76.37 175227[85:Spt:175226.0,175221.0,175223.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.37 175228[85:Spt:175226.0,175221.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 175232[85:Res:175228.0,61.1] always3(s25) || -> . % 76.16/76.37 175233[85:SSi:175232.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.37 175234[83:Spt:175233.0,174677.0,174678.0] || until2p7(s24)*+ -> . % 76.16/76.37 175235[83:Spt:175233.0,174677.1] || -> node4(s23)*. % 76.16/76.37 175237[83:MRR:849.0,175235.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.37 175240[83:Res:53.1,175237.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.37 175242[83:MRR:175240.0,174667.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 175244[83:Res:175242.0,61.1] always3(s24) || -> . % 76.16/76.37 175245[83:SSi:175244.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.37 175246[81:Spt:175245.0,174562.0,174565.0] || trans(s49,s23)*+ -> . % 76.16/76.37 175247[81:Spt:175245.0,174562.1,174562.2,174562.3,174562.4,174562.5,174562.6,174562.7,174562.8,174562.9,174562.10,174562.11,174562.12,174562.13,174562.14,174562.15,174562.16,174562.17,174562.18] || -> trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 175249[81:MRR:174564.1,175246.0] xuntil6(s49) || -> trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 175250[82:Spt:175247.0] || -> trans(s49,s22)*. % 76.16/76.37 175251[82:Res:175250.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s22)*. % 76.16/76.37 175253[82:Res:175250.0,60.0] || -> node2(s49,s22)*. % 76.16/76.37 175254[82:SSi:175251.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s22)*. % 76.16/76.37 175255[82:Res:175253.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)*. % 76.16/76.37 175348[82:SoR:175255.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)*. % 76.16/76.37 175350[82:SoR:175348.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)* xuntil6(s49). % 76.16/76.37 175351[82:SSi:175350.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s22,c_busy)* xuntil6(s49). % 76.16/76.37 175352[83:Spt:175351.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.37 175354[83:Res:175352.0,61.1] always3(s22) || -> . % 76.16/76.37 175355[83:SSi:175354.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.37 175356[83:Spt:175355.0,175351.1,175352.0] || m_main_v_state(s22,c_busy)*+ -> . % 76.16/76.37 175357[83:Spt:175355.0,175351.0,175351.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 175361[83:MRR:175348.2,175356.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 175362[83:Res:53.1,175357.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 175364[83:MRR:175362.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 175365[83:MRR:175254.0,175364.0] || -> until2p7(s22)*. % 76.16/76.37 175366[83:MRR:218.0,175365.0] || -> until2p7(s23)* node4(s22). % 76.16/76.37 175367[84:Spt:175366.0] || -> until2p7(s23)*. % 76.16/76.37 175368[84:MRR:219.0,175367.0] || -> until2p7(s24)* node4(s23). % 76.16/76.37 175369[85:Spt:175368.0] || -> until2p7(s24)*. % 76.16/76.37 175370[85:MRR:220.0,175369.0] || -> until2p7(s25)* node4(s24). % 76.16/76.37 175371[86:Spt:175370.0] || -> until2p7(s25)*. % 76.16/76.37 175372[86:MRR:221.0,175371.0] || -> until2p7(s26)* node4(s25). % 76.16/76.37 175373[87:Spt:175372.0] || -> until2p7(s26)*. % 76.16/76.37 175374[87:MRR:222.0,175373.0] || -> until2p7(s27)* node4(s26). % 76.16/76.37 175375[88:Spt:175374.0] || -> until2p7(s27)*. % 76.16/76.37 175376[88:MRR:223.0,175375.0] || -> until2p7(s28)* node4(s27). % 76.16/76.37 175377[89:Spt:175376.0] || -> until2p7(s28)*. % 76.16/76.37 175378[89:MRR:224.0,175377.0] || -> until2p7(s29)* node4(s28). % 76.16/76.37 175379[90:Spt:175378.0] || -> until2p7(s29)*. % 76.16/76.37 175380[90:MRR:225.0,175379.0] || -> until2p7(s30)* node4(s29). % 76.16/76.37 175381[91:Spt:175380.0] || -> until2p7(s30)*. % 76.16/76.37 175382[91:MRR:226.0,175381.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 175383[92:Spt:175382.0] || -> until2p7(s31)*. % 76.16/76.37 175384[92:MRR:227.0,175383.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 175385[93:Spt:175384.0] || -> until2p7(s32)*. % 76.16/76.37 175386[93:MRR:228.0,175385.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 175387[94:Spt:175386.0] || -> until2p7(s33)*. % 76.16/76.37 175388[94:MRR:229.0,175387.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 175389[95:Spt:175388.0] || -> until2p7(s34)*. % 76.16/76.37 175390[95:MRR:230.0,175389.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 175391[96:Spt:175390.0] || -> until2p7(s35)*. % 76.16/76.37 175392[96:MRR:231.0,175391.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 175393[97:Spt:175392.0] || -> until2p7(s36)*. % 76.16/76.37 175394[97:MRR:232.0,175393.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 175395[98:Spt:175394.0] || -> until2p7(s37)*. % 76.16/76.37 175396[98:MRR:235.0,175395.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 175397[99:Spt:175396.0] || -> until2p7(s38)*. % 76.16/76.37 175398[99:MRR:236.0,175397.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 175399[100:Spt:175398.0] || -> until2p7(s39)*. % 76.16/76.37 175400[100:MRR:237.0,175399.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 175401[101:Spt:175400.0] || -> until2p7(s40)*. % 76.16/76.37 175402[101:MRR:238.0,175401.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 175403[102:Spt:175402.0] || -> until2p7(s41)*. % 76.16/76.37 175404[102:MRR:239.0,175403.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 175405[103:Spt:175404.0] || -> until2p7(s42)*. % 76.16/76.37 175406[103:MRR:240.0,175405.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 175407[104:Spt:175406.0] || -> until2p7(s43)*. % 76.16/76.37 175408[104:MRR:241.0,175407.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 175409[105:Spt:175408.0] || -> until2p7(s44)*. % 76.16/76.37 175410[105:MRR:539.0,175409.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 175411[106:Spt:175410.0] || -> until2p7(s45)*. % 76.16/76.37 175412[106:MRR:544.0,175411.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 175413[107:Spt:175412.0] || -> until2p7(s46)*. % 76.16/76.37 175414[107:MRR:549.0,175413.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 175415[108:Spt:175414.0] || -> until2p7(s47)*. % 76.16/76.37 175416[108:MRR:554.0,175415.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 175417[109:Spt:175416.0] || -> until2p7(s48)*. % 76.16/76.37 175418[109:MRR:559.0,175417.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 175419[110:Spt:175418.0] || -> until2p7(s49)*. % 76.16/76.37 175420[110:MRR:194.0,175419.0] || -> node4(s49)*. % 76.16/76.37 175421[110:MRR:175361.0,175420.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 175422[110:Res:53.1,175421.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 175424[110:MRR:175422.0,78381.0] || -> . % 76.16/76.37 175425[110:Spt:175424.0,175418.0,175419.0] || until2p7(s49)*+ -> . % 76.16/76.37 175426[110:Spt:175424.0,175418.1] || -> node4(s48)*. % 76.16/76.37 175427[110:MRR:78384.0,175426.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 175430[110:Res:53.1,175427.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 175433[110:Res:175430.0,61.1] always3(s48) || -> . % 76.16/76.37 175434[110:SSi:175433.0,78281.0,78387.0,165540.0,175417.0,175426.0] || -> . % 76.16/76.37 175435[109:Spt:175434.0,175416.0,175417.0] || until2p7(s48)*+ -> . % 76.16/76.37 175436[109:Spt:175434.0,175416.1] || -> node4(s47)*. % 76.16/76.37 175438[109:MRR:777.0,175436.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 175453[109:Res:53.1,175438.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 175458[110:Spt:175453.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 175460[110:Res:175458.0,61.1] always3(s47) || -> . % 76.16/76.37 175461[110:SSi:175460.0,78277.0,78280.0,165539.0,175415.0,175436.0] || -> . % 76.16/76.37 175462[110:Spt:175461.0,175453.0,175458.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 175463[110:Spt:175461.0,175453.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 175467[110:Res:175463.0,61.1] always3(s48) || -> . % 76.16/76.37 175468[110:SSi:175467.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 175469[108:Spt:175468.0,175414.0,175415.0] || until2p7(s47)*+ -> . % 76.16/76.37 175470[108:Spt:175468.0,175414.1] || -> node4(s46)*. % 76.16/76.37 175472[108:MRR:780.0,175470.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 175479[108:Res:53.1,175472.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 175481[109:Spt:175479.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 175483[109:Res:175481.0,61.1] always3(s46) || -> . % 76.16/76.37 175484[109:SSi:175483.0,78272.0,78276.0,165538.0,175413.0,175470.0] || -> . % 76.16/76.37 175485[109:Spt:175484.0,175479.0,175481.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 175486[109:Spt:175484.0,175479.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 175490[109:Res:175486.0,61.1] always3(s47) || -> . % 76.16/76.37 175491[109:SSi:175490.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 175492[107:Spt:175491.0,175412.0,175413.0] || until2p7(s46)*+ -> . % 76.16/76.37 175493[107:Spt:175491.0,175412.1] || -> node4(s45)*. % 76.16/76.37 175495[107:MRR:783.0,175493.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 175498[107:Res:53.1,175495.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 175503[108:Spt:175498.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 175505[108:Res:175503.0,61.1] always3(s45) || -> . % 76.16/76.37 175506[108:SSi:175505.0,78268.0,78271.0,165537.0,175411.0,175493.0] || -> . % 76.16/76.37 175507[108:Spt:175506.0,175498.0,175503.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 175508[108:Spt:175506.0,175498.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 175512[108:Res:175508.0,61.1] always3(s46) || -> . % 76.16/76.37 175513[108:SSi:175512.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 175514[106:Spt:175513.0,175410.0,175411.0] || until2p7(s45)*+ -> . % 76.16/76.37 175515[106:Spt:175513.0,175410.1] || -> node4(s44)*. % 76.16/76.37 175517[106:MRR:786.0,175515.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 175520[106:Res:53.1,175517.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 175522[107:Spt:175520.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 175524[107:Res:175522.0,61.1] always3(s44) || -> . % 76.16/76.37 175525[107:SSi:175524.0,78263.0,78267.0,165536.0,175409.0,175515.0] || -> . % 76.16/76.37 175526[107:Spt:175525.0,175520.0,175522.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 175527[107:Spt:175525.0,175520.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 175531[107:Res:175527.0,61.1] always3(s45) || -> . % 76.16/76.37 175532[107:SSi:175531.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 175533[105:Spt:175532.0,175408.0,175409.0] || until2p7(s44)*+ -> . % 76.16/76.37 175534[105:Spt:175532.0,175408.1] || -> node4(s43)*. % 76.16/76.37 175536[105:MRR:789.0,175534.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 175539[105:Res:53.1,175536.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 175541[106:Spt:175539.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 175543[106:Res:175541.0,61.1] always3(s43) || -> . % 76.16/76.37 175544[106:SSi:175543.0,78259.0,78262.0,165535.0,175407.0,175534.0] || -> . % 76.16/76.37 175545[106:Spt:175544.0,175539.0,175541.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 175546[106:Spt:175544.0,175539.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 175550[106:Res:175546.0,61.1] always3(s44) || -> . % 76.16/76.37 175551[106:SSi:175550.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 175552[104:Spt:175551.0,175406.0,175407.0] || until2p7(s43)*+ -> . % 76.16/76.37 175553[104:Spt:175551.0,175406.1] || -> node4(s42)*. % 76.16/76.37 175555[104:MRR:792.0,175553.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 175558[104:Res:53.1,175555.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 175560[105:Spt:175558.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 175562[105:Res:175560.0,61.1] always3(s42) || -> . % 76.16/76.37 175563[105:SSi:175562.0,78254.0,78258.0,165534.0,175405.0,175553.0] || -> . % 76.16/76.37 175564[105:Spt:175563.0,175558.0,175560.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 175565[105:Spt:175563.0,175558.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 175569[105:Res:175565.0,61.1] always3(s43) || -> . % 76.16/76.37 175570[105:SSi:175569.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 175571[103:Spt:175570.0,175404.0,175405.0] || until2p7(s42)*+ -> . % 76.16/76.37 175572[103:Spt:175570.0,175404.1] || -> node4(s41)*. % 76.16/76.37 175574[103:MRR:795.0,175572.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 175577[103:Res:53.1,175574.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 175582[104:Spt:175577.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 175584[104:Res:175582.0,61.1] always3(s41) || -> . % 76.16/76.37 175585[104:SSi:175584.0,78250.0,78253.0,165533.0,175403.0,175572.0] || -> . % 76.16/76.37 175586[104:Spt:175585.0,175577.0,175582.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 175587[104:Spt:175585.0,175577.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 175591[104:Res:175587.0,61.1] always3(s42) || -> . % 76.16/76.37 175592[104:SSi:175591.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 175593[102:Spt:175592.0,175402.0,175403.0] || until2p7(s41)*+ -> . % 76.16/76.37 175594[102:Spt:175592.0,175402.1] || -> node4(s40)*. % 76.16/76.37 175596[102:MRR:798.0,175594.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 175599[102:Res:53.1,175596.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 175601[103:Spt:175599.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 175603[103:Res:175601.0,61.1] always3(s40) || -> . % 76.16/76.37 175604[103:SSi:175603.0,78245.0,78249.0,165532.0,175401.0,175594.0] || -> . % 76.16/76.37 175605[103:Spt:175604.0,175599.0,175601.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 175606[103:Spt:175604.0,175599.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 175610[103:Res:175606.0,61.1] always3(s41) || -> . % 76.16/76.37 175611[103:SSi:175610.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 175612[101:Spt:175611.0,175400.0,175401.0] || until2p7(s40)*+ -> . % 76.16/76.37 175613[101:Spt:175611.0,175400.1] || -> node4(s39)*. % 76.16/76.37 175615[101:MRR:801.0,175613.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 175618[101:Res:53.1,175615.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 175620[102:Spt:175618.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 175622[102:Res:175620.0,61.1] always3(s39) || -> . % 76.16/76.37 175623[102:SSi:175622.0,78241.0,78244.0,165531.0,175399.0,175613.0] || -> . % 76.16/76.37 175624[102:Spt:175623.0,175618.0,175620.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 175625[102:Spt:175623.0,175618.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 175629[102:Res:175625.0,61.1] always3(s40) || -> . % 76.16/76.37 175630[102:SSi:175629.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 175631[100:Spt:175630.0,175398.0,175399.0] || until2p7(s39)*+ -> . % 76.16/76.37 175632[100:Spt:175630.0,175398.1] || -> node4(s38)*. % 76.16/76.37 175634[100:MRR:804.0,175632.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 175637[100:Res:53.1,175634.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 175639[101:Spt:175637.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 175641[101:Res:175639.0,61.1] always3(s38) || -> . % 76.16/76.37 175642[101:SSi:175641.0,78236.0,78240.0,165530.0,175397.0,175632.0] || -> . % 76.16/76.37 175643[101:Spt:175642.0,175637.0,175639.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 175644[101:Spt:175642.0,175637.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 175648[101:Res:175644.0,61.1] always3(s39) || -> . % 76.16/76.37 175649[101:SSi:175648.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 175650[99:Spt:175649.0,175396.0,175397.0] || until2p7(s38)*+ -> . % 76.16/76.37 175651[99:Spt:175649.0,175396.1] || -> node4(s37)*. % 76.16/76.37 175653[99:MRR:807.0,175651.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 175656[99:Res:53.1,175653.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 175661[100:Spt:175656.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 175663[100:Res:175661.0,61.1] always3(s37) || -> . % 76.16/76.37 175664[100:SSi:175663.0,78232.0,78235.0,165529.0,175395.0,175651.0] || -> . % 76.16/76.37 175665[100:Spt:175664.0,175656.0,175661.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 175666[100:Spt:175664.0,175656.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 175670[100:Res:175666.0,61.1] always3(s38) || -> . % 76.16/76.37 175671[100:SSi:175670.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 175672[98:Spt:175671.0,175394.0,175395.0] || until2p7(s37)*+ -> . % 76.16/76.37 175673[98:Spt:175671.0,175394.1] || -> node4(s36)*. % 76.16/76.37 175675[98:MRR:810.0,175673.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 175678[98:Res:53.1,175675.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 175680[99:Spt:175678.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 175682[99:Res:175680.0,61.1] always3(s36) || -> . % 76.16/76.37 175683[99:SSi:175682.0,78227.0,78231.0,165528.0,175393.0,175673.0] || -> . % 76.16/76.37 175684[99:Spt:175683.0,175678.0,175680.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 175685[99:Spt:175683.0,175678.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 175689[99:Res:175685.0,61.1] always3(s37) || -> . % 76.16/76.37 175690[99:SSi:175689.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 175691[97:Spt:175690.0,175392.0,175393.0] || until2p7(s36)*+ -> . % 76.16/76.37 175692[97:Spt:175690.0,175392.1] || -> node4(s35)*. % 76.16/76.37 175694[97:MRR:813.0,175692.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 175697[97:Res:53.1,175694.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 175699[98:Spt:175697.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 175701[98:Res:175699.0,61.1] always3(s35) || -> . % 76.16/76.37 175702[98:SSi:175701.0,78223.0,78226.0,165527.0,175391.0,175692.0] || -> . % 76.16/76.37 175703[98:Spt:175702.0,175697.0,175699.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 175704[98:Spt:175702.0,175697.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 175708[98:Res:175704.0,61.1] always3(s36) || -> . % 76.16/76.37 175709[98:SSi:175708.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 175710[96:Spt:175709.0,175390.0,175391.0] || until2p7(s35)*+ -> . % 76.16/76.37 175711[96:Spt:175709.0,175390.1] || -> node4(s34)*. % 76.16/76.37 175713[96:MRR:816.0,175711.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 175716[96:Res:53.1,175713.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 175718[97:Spt:175716.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 175720[97:Res:175718.0,61.1] always3(s34) || -> . % 76.16/76.37 175721[97:SSi:175720.0,78218.0,78222.0,165526.0,175389.0,175711.0] || -> . % 76.16/76.37 175722[97:Spt:175721.0,175716.0,175718.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 175723[97:Spt:175721.0,175716.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 175727[97:Res:175723.0,61.1] always3(s35) || -> . % 76.16/76.37 175728[97:SSi:175727.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 175729[95:Spt:175728.0,175388.0,175389.0] || until2p7(s34)*+ -> . % 76.16/76.37 175730[95:Spt:175728.0,175388.1] || -> node4(s33)*. % 76.16/76.37 175732[95:MRR:819.0,175730.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 175735[95:Res:53.1,175732.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 175740[96:Spt:175735.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 175742[96:Res:175740.0,61.1] always3(s33) || -> . % 76.16/76.37 175743[96:SSi:175742.0,78214.0,78217.0,165525.0,175387.0,175730.0] || -> . % 76.16/76.37 175744[96:Spt:175743.0,175735.0,175740.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 175745[96:Spt:175743.0,175735.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 175749[96:Res:175745.0,61.1] always3(s34) || -> . % 76.16/76.37 175750[96:SSi:175749.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 175751[94:Spt:175750.0,175386.0,175387.0] || until2p7(s33)*+ -> . % 76.16/76.37 175752[94:Spt:175750.0,175386.1] || -> node4(s32)*. % 76.16/76.37 175754[94:MRR:822.0,175752.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 175757[94:Res:53.1,175754.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 175759[95:Spt:175757.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 175761[95:Res:175759.0,61.1] always3(s32) || -> . % 76.16/76.37 175762[95:SSi:175761.0,78209.0,78213.0,165524.0,175385.0,175752.0] || -> . % 76.16/76.37 175763[95:Spt:175762.0,175757.0,175759.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 175764[95:Spt:175762.0,175757.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 175768[95:Res:175764.0,61.1] always3(s33) || -> . % 76.16/76.37 175769[95:SSi:175768.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 175770[93:Spt:175769.0,175384.0,175385.0] || until2p7(s32)*+ -> . % 76.16/76.37 175771[93:Spt:175769.0,175384.1] || -> node4(s31)*. % 76.16/76.37 175773[93:MRR:825.0,175771.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 175776[93:Res:53.1,175773.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 175778[94:Spt:175776.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 175780[94:Res:175778.0,61.1] always3(s31) || -> . % 76.16/76.37 175781[94:SSi:175780.0,78205.0,78208.0,165523.0,175383.0,175771.0] || -> . % 76.16/76.37 175782[94:Spt:175781.0,175776.0,175778.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 175783[94:Spt:175781.0,175776.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 175787[94:Res:175783.0,61.1] always3(s32) || -> . % 76.16/76.37 175788[94:SSi:175787.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 175789[92:Spt:175788.0,175382.0,175383.0] || until2p7(s31)*+ -> . % 76.16/76.37 175790[92:Spt:175788.0,175382.1] || -> node4(s30)*. % 76.16/76.37 175792[92:MRR:828.0,175790.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 175795[92:Res:53.1,175792.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 175797[93:Spt:175795.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 175799[93:Res:175797.0,61.1] always3(s30) || -> . % 76.16/76.37 175800[93:SSi:175799.0,78200.0,78204.0,165522.0,175381.0,175790.0] || -> . % 76.16/76.37 175801[93:Spt:175800.0,175795.0,175797.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.37 175802[93:Spt:175800.0,175795.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 175806[93:Res:175802.0,61.1] always3(s31) || -> . % 76.16/76.37 175807[93:SSi:175806.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 175808[91:Spt:175807.0,175380.0,175381.0] || until2p7(s30)*+ -> . % 76.16/76.37 175809[91:Spt:175807.0,175380.1] || -> node4(s29)*. % 76.16/76.37 175811[91:MRR:831.0,175809.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.37 175814[91:Res:53.1,175811.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.37 175819[92:Spt:175814.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 175821[92:Res:175819.0,61.1] always3(s29) || -> . % 76.16/76.37 175822[92:SSi:175821.0,78196.0,78199.0,165521.0,175379.0,175809.0] || -> . % 76.16/76.37 175823[92:Spt:175822.0,175814.0,175819.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.37 175824[92:Spt:175822.0,175814.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 175828[92:Res:175824.0,61.1] always3(s30) || -> . % 76.16/76.37 175829[92:SSi:175828.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 175830[90:Spt:175829.0,175378.0,175379.0] || until2p7(s29)*+ -> . % 76.16/76.37 175831[90:Spt:175829.0,175378.1] || -> node4(s28)*. % 76.16/76.37 175833[90:MRR:834.0,175831.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.37 175836[90:Res:53.1,175833.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.37 175838[91:Spt:175836.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 175840[91:Res:175838.0,61.1] always3(s28) || -> . % 76.16/76.37 175841[91:SSi:175840.0,78191.0,78195.0,165520.0,175377.0,175831.0] || -> . % 76.16/76.37 175842[91:Spt:175841.0,175836.0,175838.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.37 175843[91:Spt:175841.0,175836.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 175847[91:Res:175843.0,61.1] always3(s29) || -> . % 76.16/76.37 175848[91:SSi:175847.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.37 175849[89:Spt:175848.0,175376.0,175377.0] || until2p7(s28)*+ -> . % 76.16/76.37 175850[89:Spt:175848.0,175376.1] || -> node4(s27)*. % 76.16/76.37 175852[89:MRR:837.0,175850.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.37 175855[89:Res:53.1,175852.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.37 175857[90:Spt:175855.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 175859[90:Res:175857.0,61.1] always3(s27) || -> . % 76.16/76.37 175860[90:SSi:175859.0,78187.0,78190.0,165519.0,175375.0,175850.0] || -> . % 76.16/76.37 175861[90:Spt:175860.0,175855.0,175857.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.37 175862[90:Spt:175860.0,175855.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 175866[90:Res:175862.0,61.1] always3(s28) || -> . % 76.16/76.37 175867[90:SSi:175866.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.37 175868[88:Spt:175867.0,175374.0,175375.0] || until2p7(s27)*+ -> . % 76.16/76.37 175869[88:Spt:175867.0,175374.1] || -> node4(s26)*. % 76.16/76.37 175871[88:MRR:840.0,175869.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.37 175874[88:Res:53.1,175871.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.37 175876[89:Spt:175874.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 175878[89:Res:175876.0,61.1] always3(s26) || -> . % 76.16/76.37 175879[89:SSi:175878.0,78182.0,78186.0,165518.0,175373.0,175869.0] || -> . % 76.16/76.37 175880[89:Spt:175879.0,175874.0,175876.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.37 175881[89:Spt:175879.0,175874.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 175885[89:Res:175881.0,61.1] always3(s27) || -> . % 76.16/76.37 175886[89:SSi:175885.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.37 175887[87:Spt:175886.0,175372.0,175373.0] || until2p7(s26)*+ -> . % 76.16/76.37 175888[87:Spt:175886.0,175372.1] || -> node4(s25)*. % 76.16/76.37 175890[87:MRR:843.0,175888.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.37 175893[87:Res:53.1,175890.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.37 175898[88:Spt:175893.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 175900[88:Res:175898.0,61.1] always3(s25) || -> . % 76.16/76.37 175901[88:SSi:175900.0,78178.0,78181.0,165517.0,175371.0,175888.0] || -> . % 76.16/76.37 175902[88:Spt:175901.0,175893.0,175898.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.37 175903[88:Spt:175901.0,175893.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 175907[88:Res:175903.0,61.1] always3(s26) || -> . % 76.16/76.37 175908[88:SSi:175907.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.37 175909[86:Spt:175908.0,175370.0,175371.0] || until2p7(s25)*+ -> . % 76.16/76.37 175910[86:Spt:175908.0,175370.1] || -> node4(s24)*. % 76.16/76.37 175912[86:MRR:846.0,175910.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.37 175915[86:Res:53.1,175912.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.37 175917[87:Spt:175915.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 175919[87:Res:175917.0,61.1] always3(s24) || -> . % 76.16/76.37 175920[87:SSi:175919.0,78173.0,78177.0,165516.0,175369.0,175910.0] || -> . % 76.16/76.37 175921[87:Spt:175920.0,175915.0,175917.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.37 175922[87:Spt:175920.0,175915.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 175926[87:Res:175922.0,61.1] always3(s25) || -> . % 76.16/76.37 175927[87:SSi:175926.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.37 175928[85:Spt:175927.0,175368.0,175369.0] || until2p7(s24)*+ -> . % 76.16/76.37 175929[85:Spt:175927.0,175368.1] || -> node4(s23)*. % 76.16/76.37 175931[85:MRR:849.0,175929.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.37 175934[85:Res:53.1,175931.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.37 175936[86:Spt:175934.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 175938[86:Res:175936.0,61.1] always3(s23) || -> . % 76.16/76.37 175939[86:SSi:175938.0,78169.0,78172.0,165515.0,175367.0,175929.0] || -> . % 76.16/76.37 175940[86:Spt:175939.0,175934.0,175936.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.37 175941[86:Spt:175939.0,175934.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 175945[86:Res:175941.0,61.1] always3(s24) || -> . % 76.16/76.37 175946[86:SSi:175945.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.37 175947[84:Spt:175946.0,175366.0,175367.0] || until2p7(s23)*+ -> . % 76.16/76.37 175948[84:Spt:175946.0,175366.1] || -> node4(s22)*. % 76.16/76.37 175950[84:MRR:852.0,175948.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.37 175953[84:Res:53.1,175950.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.37 175955[84:MRR:175953.0,175356.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 175957[84:Res:175955.0,61.1] always3(s23) || -> . % 76.16/76.37 175958[84:SSi:175957.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.37 175959[82:Spt:175958.0,175247.0,175250.0] || trans(s49,s22)*+ -> . % 76.16/76.37 175960[82:Spt:175958.0,175247.1,175247.2,175247.3,175247.4,175247.5,175247.6,175247.7,175247.8,175247.9,175247.10,175247.11,175247.12,175247.13,175247.14,175247.15,175247.16,175247.17] || -> trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 175962[82:MRR:175249.1,175959.0] xuntil6(s49) || -> trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 175963[83:Spt:175960.0] || -> trans(s49,s21)*. % 76.16/76.37 175964[83:Res:175963.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s21)*. % 76.16/76.37 175966[83:Res:175963.0,60.0] || -> node2(s49,s21)*. % 76.16/76.37 175967[83:SSi:175964.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s21)*. % 76.16/76.37 175968[83:Res:175966.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)*. % 76.16/76.37 176062[83:SoR:175968.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)*. % 76.16/76.37 176064[83:SoR:176062.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)* xuntil6(s49). % 76.16/76.37 176065[83:SSi:176064.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s21,c_busy)* xuntil6(s49). % 76.16/76.37 176066[84:Spt:176065.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.37 176068[84:Res:176066.0,61.1] always3(s21) || -> . % 76.16/76.37 176069[84:SSi:176068.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.37 176070[84:Spt:176069.0,176065.1,176066.0] || m_main_v_state(s21,c_busy)*+ -> . % 76.16/76.37 176071[84:Spt:176069.0,176065.0,176065.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 176075[84:MRR:176062.2,176070.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 176076[84:Res:53.1,176071.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 176078[84:MRR:176076.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 176079[84:MRR:175967.0,176078.0] || -> until2p7(s21)*. % 76.16/76.37 176080[84:MRR:217.0,176079.0] || -> until2p7(s22)* node4(s21). % 76.16/76.37 176081[85:Spt:176080.0] || -> until2p7(s22)*. % 76.16/76.37 176082[85:MRR:218.0,176081.0] || -> until2p7(s23)* node4(s22). % 76.16/76.37 176083[86:Spt:176082.0] || -> until2p7(s23)*. % 76.16/76.37 176084[86:MRR:219.0,176083.0] || -> until2p7(s24)* node4(s23). % 76.16/76.37 176085[87:Spt:176084.0] || -> until2p7(s24)*. % 76.16/76.37 176086[87:MRR:220.0,176085.0] || -> until2p7(s25)* node4(s24). % 76.16/76.37 176087[88:Spt:176086.0] || -> until2p7(s25)*. % 76.16/76.37 176088[88:MRR:221.0,176087.0] || -> until2p7(s26)* node4(s25). % 76.16/76.37 176089[89:Spt:176088.0] || -> until2p7(s26)*. % 76.16/76.37 176090[89:MRR:222.0,176089.0] || -> until2p7(s27)* node4(s26). % 76.16/76.37 176091[90:Spt:176090.0] || -> until2p7(s27)*. % 76.16/76.37 176092[90:MRR:223.0,176091.0] || -> until2p7(s28)* node4(s27). % 76.16/76.37 176093[91:Spt:176092.0] || -> until2p7(s28)*. % 76.16/76.37 176094[91:MRR:224.0,176093.0] || -> until2p7(s29)* node4(s28). % 76.16/76.37 176095[92:Spt:176094.0] || -> until2p7(s29)*. % 76.16/76.37 176096[92:MRR:225.0,176095.0] || -> until2p7(s30)* node4(s29). % 76.16/76.37 176097[93:Spt:176096.0] || -> until2p7(s30)*. % 76.16/76.37 176098[93:MRR:226.0,176097.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 176099[94:Spt:176098.0] || -> until2p7(s31)*. % 76.16/76.37 176100[94:MRR:227.0,176099.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 176101[95:Spt:176100.0] || -> until2p7(s32)*. % 76.16/76.37 176102[95:MRR:228.0,176101.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 176103[96:Spt:176102.0] || -> until2p7(s33)*. % 76.16/76.37 176104[96:MRR:229.0,176103.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 176105[97:Spt:176104.0] || -> until2p7(s34)*. % 76.16/76.37 176106[97:MRR:230.0,176105.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 176107[98:Spt:176106.0] || -> until2p7(s35)*. % 76.16/76.37 176108[98:MRR:231.0,176107.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 176109[99:Spt:176108.0] || -> until2p7(s36)*. % 76.16/76.37 176110[99:MRR:232.0,176109.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 176111[100:Spt:176110.0] || -> until2p7(s37)*. % 76.16/76.37 176112[100:MRR:235.0,176111.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 176113[101:Spt:176112.0] || -> until2p7(s38)*. % 76.16/76.37 176114[101:MRR:236.0,176113.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 176115[102:Spt:176114.0] || -> until2p7(s39)*. % 76.16/76.37 176116[102:MRR:237.0,176115.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 176117[103:Spt:176116.0] || -> until2p7(s40)*. % 76.16/76.37 176118[103:MRR:238.0,176117.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 176119[104:Spt:176118.0] || -> until2p7(s41)*. % 76.16/76.37 176120[104:MRR:239.0,176119.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 176121[105:Spt:176120.0] || -> until2p7(s42)*. % 76.16/76.37 176122[105:MRR:240.0,176121.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 176123[106:Spt:176122.0] || -> until2p7(s43)*. % 76.16/76.37 176124[106:MRR:241.0,176123.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 176125[107:Spt:176124.0] || -> until2p7(s44)*. % 76.16/76.37 176126[107:MRR:539.0,176125.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 176127[108:Spt:176126.0] || -> until2p7(s45)*. % 76.16/76.37 176128[108:MRR:544.0,176127.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 176129[109:Spt:176128.0] || -> until2p7(s46)*. % 76.16/76.37 176130[109:MRR:549.0,176129.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 176131[110:Spt:176130.0] || -> until2p7(s47)*. % 76.16/76.37 176132[110:MRR:554.0,176131.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 176133[111:Spt:176132.0] || -> until2p7(s48)*. % 76.16/76.37 176134[111:MRR:559.0,176133.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 176135[112:Spt:176134.0] || -> until2p7(s49)*. % 76.16/76.37 176136[112:MRR:194.0,176135.0] || -> node4(s49)*. % 76.16/76.37 176137[112:MRR:176075.0,176136.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 176141[112:Res:53.1,176137.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 176143[112:MRR:176141.0,78381.0] || -> . % 76.16/76.37 176144[112:Spt:176143.0,176134.0,176135.0] || until2p7(s49)*+ -> . % 76.16/76.37 176145[112:Spt:176143.0,176134.1] || -> node4(s48)*. % 76.16/76.37 176146[112:MRR:78384.0,176145.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 176149[112:Res:53.1,176146.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 176152[112:Res:176149.0,61.1] always3(s48) || -> . % 76.16/76.37 176153[112:SSi:176152.0,78281.0,78387.0,165540.0,176133.0,176145.0] || -> . % 76.16/76.37 176154[111:Spt:176153.0,176132.0,176133.0] || until2p7(s48)*+ -> . % 76.16/76.37 176155[111:Spt:176153.0,176132.1] || -> node4(s47)*. % 76.16/76.37 176157[111:MRR:777.0,176155.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 176169[111:Res:53.1,176157.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 176171[112:Spt:176169.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 176173[112:Res:176171.0,61.1] always3(s47) || -> . % 76.16/76.37 176174[112:SSi:176173.0,78277.0,78280.0,165539.0,176131.0,176155.0] || -> . % 76.16/76.37 176175[112:Spt:176174.0,176169.0,176171.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 176176[112:Spt:176174.0,176169.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 176180[112:Res:176176.0,61.1] always3(s48) || -> . % 76.16/76.37 176181[112:SSi:176180.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 176182[110:Spt:176181.0,176130.0,176131.0] || until2p7(s47)*+ -> . % 76.16/76.37 176183[110:Spt:176181.0,176130.1] || -> node4(s46)*. % 76.16/76.37 176185[110:MRR:780.0,176183.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 176192[110:Res:53.1,176185.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 176197[111:Spt:176192.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 176199[111:Res:176197.0,61.1] always3(s46) || -> . % 76.16/76.37 176200[111:SSi:176199.0,78272.0,78276.0,165538.0,176129.0,176183.0] || -> . % 76.16/76.37 176201[111:Spt:176200.0,176192.0,176197.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 176202[111:Spt:176200.0,176192.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 176206[111:Res:176202.0,61.1] always3(s47) || -> . % 76.16/76.37 176207[111:SSi:176206.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 176208[109:Spt:176207.0,176128.0,176129.0] || until2p7(s46)*+ -> . % 76.16/76.37 176209[109:Spt:176207.0,176128.1] || -> node4(s45)*. % 76.16/76.37 176211[109:MRR:783.0,176209.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 176214[109:Res:53.1,176211.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 176216[110:Spt:176214.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 176218[110:Res:176216.0,61.1] always3(s45) || -> . % 76.16/76.37 176219[110:SSi:176218.0,78268.0,78271.0,165537.0,176127.0,176209.0] || -> . % 76.16/76.37 176220[110:Spt:176219.0,176214.0,176216.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 176221[110:Spt:176219.0,176214.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 176225[110:Res:176221.0,61.1] always3(s46) || -> . % 76.16/76.37 176226[110:SSi:176225.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 176227[108:Spt:176226.0,176126.0,176127.0] || until2p7(s45)*+ -> . % 76.16/76.37 176228[108:Spt:176226.0,176126.1] || -> node4(s44)*. % 76.16/76.37 176230[108:MRR:786.0,176228.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 176233[108:Res:53.1,176230.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 176235[109:Spt:176233.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 176237[109:Res:176235.0,61.1] always3(s44) || -> . % 76.16/76.37 176238[109:SSi:176237.0,78263.0,78267.0,165536.0,176125.0,176228.0] || -> . % 76.16/76.37 176239[109:Spt:176238.0,176233.0,176235.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 176240[109:Spt:176238.0,176233.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 176244[109:Res:176240.0,61.1] always3(s45) || -> . % 76.16/76.37 176245[109:SSi:176244.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 176246[107:Spt:176245.0,176124.0,176125.0] || until2p7(s44)*+ -> . % 76.16/76.37 176247[107:Spt:176245.0,176124.1] || -> node4(s43)*. % 76.16/76.37 176249[107:MRR:789.0,176247.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 176252[107:Res:53.1,176249.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 176254[108:Spt:176252.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 176256[108:Res:176254.0,61.1] always3(s43) || -> . % 76.16/76.37 176257[108:SSi:176256.0,78259.0,78262.0,165535.0,176123.0,176247.0] || -> . % 76.16/76.37 176258[108:Spt:176257.0,176252.0,176254.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 176259[108:Spt:176257.0,176252.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 176263[108:Res:176259.0,61.1] always3(s44) || -> . % 76.16/76.37 176264[108:SSi:176263.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 176265[106:Spt:176264.0,176122.0,176123.0] || until2p7(s43)*+ -> . % 76.16/76.37 176266[106:Spt:176264.0,176122.1] || -> node4(s42)*. % 76.16/76.37 176268[106:MRR:792.0,176266.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 176271[106:Res:53.1,176268.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 176276[107:Spt:176271.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 176278[107:Res:176276.0,61.1] always3(s42) || -> . % 76.16/76.37 176279[107:SSi:176278.0,78254.0,78258.0,165534.0,176121.0,176266.0] || -> . % 76.16/76.37 176280[107:Spt:176279.0,176271.0,176276.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 176281[107:Spt:176279.0,176271.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 176285[107:Res:176281.0,61.1] always3(s43) || -> . % 76.16/76.37 176286[107:SSi:176285.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 176287[105:Spt:176286.0,176120.0,176121.0] || until2p7(s42)*+ -> . % 76.16/76.37 176288[105:Spt:176286.0,176120.1] || -> node4(s41)*. % 76.16/76.37 176290[105:MRR:795.0,176288.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 176293[105:Res:53.1,176290.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 176295[106:Spt:176293.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 176297[106:Res:176295.0,61.1] always3(s41) || -> . % 76.16/76.37 176298[106:SSi:176297.0,78250.0,78253.0,165533.0,176119.0,176288.0] || -> . % 76.16/76.37 176299[106:Spt:176298.0,176293.0,176295.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 176300[106:Spt:176298.0,176293.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 176304[106:Res:176300.0,61.1] always3(s42) || -> . % 76.16/76.37 176305[106:SSi:176304.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 176306[104:Spt:176305.0,176118.0,176119.0] || until2p7(s41)*+ -> . % 76.16/76.37 176307[104:Spt:176305.0,176118.1] || -> node4(s40)*. % 76.16/76.37 176309[104:MRR:798.0,176307.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 176312[104:Res:53.1,176309.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 176314[105:Spt:176312.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 176316[105:Res:176314.0,61.1] always3(s40) || -> . % 76.16/76.37 176317[105:SSi:176316.0,78245.0,78249.0,165532.0,176117.0,176307.0] || -> . % 76.16/76.37 176318[105:Spt:176317.0,176312.0,176314.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 176319[105:Spt:176317.0,176312.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 176323[105:Res:176319.0,61.1] always3(s41) || -> . % 76.16/76.37 176324[105:SSi:176323.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 176325[103:Spt:176324.0,176116.0,176117.0] || until2p7(s40)*+ -> . % 76.16/76.37 176326[103:Spt:176324.0,176116.1] || -> node4(s39)*. % 76.16/76.37 176328[103:MRR:801.0,176326.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 176331[103:Res:53.1,176328.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 176333[104:Spt:176331.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 176335[104:Res:176333.0,61.1] always3(s39) || -> . % 76.16/76.37 176336[104:SSi:176335.0,78241.0,78244.0,165531.0,176115.0,176326.0] || -> . % 76.16/76.37 176337[104:Spt:176336.0,176331.0,176333.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 176338[104:Spt:176336.0,176331.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 176342[104:Res:176338.0,61.1] always3(s40) || -> . % 76.16/76.37 176343[104:SSi:176342.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 176344[102:Spt:176343.0,176114.0,176115.0] || until2p7(s39)*+ -> . % 76.16/76.37 176345[102:Spt:176343.0,176114.1] || -> node4(s38)*. % 76.16/76.37 176347[102:MRR:804.0,176345.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 176350[102:Res:53.1,176347.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 176355[103:Spt:176350.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 176357[103:Res:176355.0,61.1] always3(s38) || -> . % 76.16/76.37 176358[103:SSi:176357.0,78236.0,78240.0,165530.0,176113.0,176345.0] || -> . % 76.16/76.37 176359[103:Spt:176358.0,176350.0,176355.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 176360[103:Spt:176358.0,176350.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 176364[103:Res:176360.0,61.1] always3(s39) || -> . % 76.16/76.37 176365[103:SSi:176364.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 176366[101:Spt:176365.0,176112.0,176113.0] || until2p7(s38)*+ -> . % 76.16/76.37 176367[101:Spt:176365.0,176112.1] || -> node4(s37)*. % 76.16/76.37 176369[101:MRR:807.0,176367.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 176372[101:Res:53.1,176369.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 176374[102:Spt:176372.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 176376[102:Res:176374.0,61.1] always3(s37) || -> . % 76.16/76.37 176377[102:SSi:176376.0,78232.0,78235.0,165529.0,176111.0,176367.0] || -> . % 76.16/76.37 176378[102:Spt:176377.0,176372.0,176374.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 176379[102:Spt:176377.0,176372.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 176383[102:Res:176379.0,61.1] always3(s38) || -> . % 76.16/76.37 176384[102:SSi:176383.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 176385[100:Spt:176384.0,176110.0,176111.0] || until2p7(s37)*+ -> . % 76.16/76.37 176386[100:Spt:176384.0,176110.1] || -> node4(s36)*. % 76.16/76.37 176388[100:MRR:810.0,176386.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 176391[100:Res:53.1,176388.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 176393[101:Spt:176391.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 176395[101:Res:176393.0,61.1] always3(s36) || -> . % 76.16/76.37 176396[101:SSi:176395.0,78227.0,78231.0,165528.0,176109.0,176386.0] || -> . % 76.16/76.37 176397[101:Spt:176396.0,176391.0,176393.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 176398[101:Spt:176396.0,176391.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 176402[101:Res:176398.0,61.1] always3(s37) || -> . % 76.16/76.37 176403[101:SSi:176402.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 176404[99:Spt:176403.0,176108.0,176109.0] || until2p7(s36)*+ -> . % 76.16/76.37 176405[99:Spt:176403.0,176108.1] || -> node4(s35)*. % 76.16/76.37 176407[99:MRR:813.0,176405.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 176410[99:Res:53.1,176407.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 176412[100:Spt:176410.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 176414[100:Res:176412.0,61.1] always3(s35) || -> . % 76.16/76.37 176415[100:SSi:176414.0,78223.0,78226.0,165527.0,176107.0,176405.0] || -> . % 76.16/76.37 176416[100:Spt:176415.0,176410.0,176412.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 176417[100:Spt:176415.0,176410.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 176421[100:Res:176417.0,61.1] always3(s36) || -> . % 76.16/76.37 176422[100:SSi:176421.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 176423[98:Spt:176422.0,176106.0,176107.0] || until2p7(s35)*+ -> . % 76.16/76.37 176424[98:Spt:176422.0,176106.1] || -> node4(s34)*. % 76.16/76.37 176426[98:MRR:816.0,176424.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 176429[98:Res:53.1,176426.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 176434[99:Spt:176429.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 176436[99:Res:176434.0,61.1] always3(s34) || -> . % 76.16/76.37 176437[99:SSi:176436.0,78218.0,78222.0,165526.0,176105.0,176424.0] || -> . % 76.16/76.37 176438[99:Spt:176437.0,176429.0,176434.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 176439[99:Spt:176437.0,176429.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 176443[99:Res:176439.0,61.1] always3(s35) || -> . % 76.16/76.37 176444[99:SSi:176443.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 176445[97:Spt:176444.0,176104.0,176105.0] || until2p7(s34)*+ -> . % 76.16/76.37 176446[97:Spt:176444.0,176104.1] || -> node4(s33)*. % 76.16/76.37 176448[97:MRR:819.0,176446.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 176451[97:Res:53.1,176448.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 176453[98:Spt:176451.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 176455[98:Res:176453.0,61.1] always3(s33) || -> . % 76.16/76.37 176456[98:SSi:176455.0,78214.0,78217.0,165525.0,176103.0,176446.0] || -> . % 76.16/76.37 176457[98:Spt:176456.0,176451.0,176453.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 176458[98:Spt:176456.0,176451.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 176462[98:Res:176458.0,61.1] always3(s34) || -> . % 76.16/76.37 176463[98:SSi:176462.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 176464[96:Spt:176463.0,176102.0,176103.0] || until2p7(s33)*+ -> . % 76.16/76.37 176465[96:Spt:176463.0,176102.1] || -> node4(s32)*. % 76.16/76.37 176467[96:MRR:822.0,176465.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 176470[96:Res:53.1,176467.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 176472[97:Spt:176470.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 176474[97:Res:176472.0,61.1] always3(s32) || -> . % 76.16/76.37 176475[97:SSi:176474.0,78209.0,78213.0,165524.0,176101.0,176465.0] || -> . % 76.16/76.37 176476[97:Spt:176475.0,176470.0,176472.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 176477[97:Spt:176475.0,176470.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 176481[97:Res:176477.0,61.1] always3(s33) || -> . % 76.16/76.37 176482[97:SSi:176481.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 176483[95:Spt:176482.0,176100.0,176101.0] || until2p7(s32)*+ -> . % 76.16/76.37 176484[95:Spt:176482.0,176100.1] || -> node4(s31)*. % 76.16/76.37 176486[95:MRR:825.0,176484.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 176489[95:Res:53.1,176486.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 176491[96:Spt:176489.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 176493[96:Res:176491.0,61.1] always3(s31) || -> . % 76.16/76.37 176494[96:SSi:176493.0,78205.0,78208.0,165523.0,176099.0,176484.0] || -> . % 76.16/76.37 176495[96:Spt:176494.0,176489.0,176491.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 176496[96:Spt:176494.0,176489.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 176500[96:Res:176496.0,61.1] always3(s32) || -> . % 76.16/76.37 176501[96:SSi:176500.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 176502[94:Spt:176501.0,176098.0,176099.0] || until2p7(s31)*+ -> . % 76.16/76.37 176503[94:Spt:176501.0,176098.1] || -> node4(s30)*. % 76.16/76.37 176505[94:MRR:828.0,176503.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 176508[94:Res:53.1,176505.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 176513[95:Spt:176508.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 176515[95:Res:176513.0,61.1] always3(s30) || -> . % 76.16/76.37 176516[95:SSi:176515.0,78200.0,78204.0,165522.0,176097.0,176503.0] || -> . % 76.16/76.37 176517[95:Spt:176516.0,176508.0,176513.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.37 176518[95:Spt:176516.0,176508.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 176522[95:Res:176518.0,61.1] always3(s31) || -> . % 76.16/76.37 176523[95:SSi:176522.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 176524[93:Spt:176523.0,176096.0,176097.0] || until2p7(s30)*+ -> . % 76.16/76.37 176525[93:Spt:176523.0,176096.1] || -> node4(s29)*. % 76.16/76.37 176527[93:MRR:831.0,176525.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.37 176530[93:Res:53.1,176527.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.37 176532[94:Spt:176530.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 176534[94:Res:176532.0,61.1] always3(s29) || -> . % 76.16/76.37 176535[94:SSi:176534.0,78196.0,78199.0,165521.0,176095.0,176525.0] || -> . % 76.16/76.37 176536[94:Spt:176535.0,176530.0,176532.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.37 176537[94:Spt:176535.0,176530.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 176541[94:Res:176537.0,61.1] always3(s30) || -> . % 76.16/76.37 176542[94:SSi:176541.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 176543[92:Spt:176542.0,176094.0,176095.0] || until2p7(s29)*+ -> . % 76.16/76.37 176544[92:Spt:176542.0,176094.1] || -> node4(s28)*. % 76.16/76.37 176546[92:MRR:834.0,176544.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.37 176549[92:Res:53.1,176546.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.37 176551[93:Spt:176549.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 176553[93:Res:176551.0,61.1] always3(s28) || -> . % 76.16/76.37 176554[93:SSi:176553.0,78191.0,78195.0,165520.0,176093.0,176544.0] || -> . % 76.16/76.37 176555[93:Spt:176554.0,176549.0,176551.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.37 176556[93:Spt:176554.0,176549.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 176560[93:Res:176556.0,61.1] always3(s29) || -> . % 76.16/76.37 176561[93:SSi:176560.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.37 176562[91:Spt:176561.0,176092.0,176093.0] || until2p7(s28)*+ -> . % 76.16/76.37 176563[91:Spt:176561.0,176092.1] || -> node4(s27)*. % 76.16/76.37 176565[91:MRR:837.0,176563.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.37 176568[91:Res:53.1,176565.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.37 176570[92:Spt:176568.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 176572[92:Res:176570.0,61.1] always3(s27) || -> . % 76.16/76.37 176573[92:SSi:176572.0,78187.0,78190.0,165519.0,176091.0,176563.0] || -> . % 76.16/76.37 176574[92:Spt:176573.0,176568.0,176570.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.37 176575[92:Spt:176573.0,176568.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 176579[92:Res:176575.0,61.1] always3(s28) || -> . % 76.16/76.37 176580[92:SSi:176579.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.37 176581[90:Spt:176580.0,176090.0,176091.0] || until2p7(s27)*+ -> . % 76.16/76.37 176582[90:Spt:176580.0,176090.1] || -> node4(s26)*. % 76.16/76.37 176584[90:MRR:840.0,176582.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.37 176587[90:Res:53.1,176584.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.37 176592[91:Spt:176587.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 176594[91:Res:176592.0,61.1] always3(s26) || -> . % 76.16/76.37 176595[91:SSi:176594.0,78182.0,78186.0,165518.0,176089.0,176582.0] || -> . % 76.16/76.37 176596[91:Spt:176595.0,176587.0,176592.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.37 176597[91:Spt:176595.0,176587.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 176601[91:Res:176597.0,61.1] always3(s27) || -> . % 76.16/76.37 176602[91:SSi:176601.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.37 176603[89:Spt:176602.0,176088.0,176089.0] || until2p7(s26)*+ -> . % 76.16/76.37 176604[89:Spt:176602.0,176088.1] || -> node4(s25)*. % 76.16/76.37 176606[89:MRR:843.0,176604.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.37 176609[89:Res:53.1,176606.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.37 176611[90:Spt:176609.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 176613[90:Res:176611.0,61.1] always3(s25) || -> . % 76.16/76.37 176614[90:SSi:176613.0,78178.0,78181.0,165517.0,176087.0,176604.0] || -> . % 76.16/76.37 176615[90:Spt:176614.0,176609.0,176611.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.37 176616[90:Spt:176614.0,176609.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 176620[90:Res:176616.0,61.1] always3(s26) || -> . % 76.16/76.37 176621[90:SSi:176620.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.37 176622[88:Spt:176621.0,176086.0,176087.0] || until2p7(s25)*+ -> . % 76.16/76.37 176623[88:Spt:176621.0,176086.1] || -> node4(s24)*. % 76.16/76.37 176625[88:MRR:846.0,176623.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.37 176628[88:Res:53.1,176625.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.37 176630[89:Spt:176628.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 176632[89:Res:176630.0,61.1] always3(s24) || -> . % 76.16/76.37 176633[89:SSi:176632.0,78173.0,78177.0,165516.0,176085.0,176623.0] || -> . % 76.16/76.37 176634[89:Spt:176633.0,176628.0,176630.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.37 176635[89:Spt:176633.0,176628.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 176639[89:Res:176635.0,61.1] always3(s25) || -> . % 76.16/76.37 176640[89:SSi:176639.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.37 176641[87:Spt:176640.0,176084.0,176085.0] || until2p7(s24)*+ -> . % 76.16/76.37 176642[87:Spt:176640.0,176084.1] || -> node4(s23)*. % 76.16/76.37 176644[87:MRR:849.0,176642.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.37 176647[87:Res:53.1,176644.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.37 176649[88:Spt:176647.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 176651[88:Res:176649.0,61.1] always3(s23) || -> . % 76.16/76.37 176652[88:SSi:176651.0,78169.0,78172.0,165515.0,176083.0,176642.0] || -> . % 76.16/76.37 176653[88:Spt:176652.0,176647.0,176649.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.37 176654[88:Spt:176652.0,176647.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 176658[88:Res:176654.0,61.1] always3(s24) || -> . % 76.16/76.37 176659[88:SSi:176658.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.37 176660[86:Spt:176659.0,176082.0,176083.0] || until2p7(s23)*+ -> . % 76.16/76.37 176661[86:Spt:176659.0,176082.1] || -> node4(s22)*. % 76.16/76.37 176663[86:MRR:852.0,176661.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.37 176666[86:Res:53.1,176663.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.37 176671[87:Spt:176666.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.37 176673[87:Res:176671.0,61.1] always3(s22) || -> . % 76.16/76.37 176674[87:SSi:176673.0,78164.0,78168.0,165514.0,176081.0,176661.0] || -> . % 76.16/76.37 176675[87:Spt:176674.0,176666.0,176671.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.37 176676[87:Spt:176674.0,176666.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 176680[87:Res:176676.0,61.1] always3(s23) || -> . % 76.16/76.37 176681[87:SSi:176680.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.37 176682[85:Spt:176681.0,176080.0,176081.0] || until2p7(s22)*+ -> . % 76.16/76.37 176683[85:Spt:176681.0,176080.1] || -> node4(s21)*. % 76.16/76.37 176685[85:MRR:855.0,176683.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.37 176688[85:Res:53.1,176685.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.37 176690[85:MRR:176688.0,176070.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.37 176692[85:Res:176690.0,61.1] always3(s22) || -> . % 76.16/76.37 176693[85:SSi:176692.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.37 176694[83:Spt:176693.0,175960.0,175963.0] || trans(s49,s21)*+ -> . % 76.16/76.37 176695[83:Spt:176693.0,175960.1,175960.2,175960.3,175960.4,175960.5,175960.6,175960.7,175960.8,175960.9,175960.10,175960.11,175960.12,175960.13,175960.14,175960.15,175960.16] || -> trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 176697[83:MRR:175962.1,176694.0] xuntil6(s49) || -> trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 176698[84:Spt:176695.0] || -> trans(s49,s20)*. % 76.16/76.37 176699[84:Res:176698.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s20)*. % 76.16/76.37 176701[84:Res:176698.0,60.0] || -> node2(s49,s20)*. % 76.16/76.37 176702[84:SSi:176699.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s20)*. % 76.16/76.37 176703[84:Res:176701.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)*. % 76.16/76.37 176801[84:SoR:176703.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)*. % 76.16/76.37 176803[84:SoR:176801.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)* xuntil6(s49). % 76.16/76.37 176804[84:SSi:176803.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s20,c_busy)* xuntil6(s49). % 76.16/76.37 176805[85:Spt:176804.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.37 176807[85:Res:176805.0,61.1] always3(s20) || -> . % 76.16/76.37 176808[85:SSi:176807.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.37 176809[85:Spt:176808.0,176804.1,176805.0] || m_main_v_state(s20,c_busy)*+ -> . % 76.16/76.37 176810[85:Spt:176808.0,176804.0,176804.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 176814[85:MRR:176801.2,176809.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 176815[85:Res:53.1,176810.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 176817[85:MRR:176815.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 176818[85:MRR:176702.0,176817.0] || -> until2p7(s20)*. % 76.16/76.37 176819[85:MRR:216.0,176818.0] || -> until2p7(s21)* node4(s20). % 76.16/76.37 176820[86:Spt:176819.0] || -> until2p7(s21)*. % 76.16/76.37 176821[86:MRR:217.0,176820.0] || -> until2p7(s22)* node4(s21). % 76.16/76.37 176822[87:Spt:176821.0] || -> until2p7(s22)*. % 76.16/76.37 176823[87:MRR:218.0,176822.0] || -> until2p7(s23)* node4(s22). % 76.16/76.37 176824[88:Spt:176823.0] || -> until2p7(s23)*. % 76.16/76.37 176825[88:MRR:219.0,176824.0] || -> until2p7(s24)* node4(s23). % 76.16/76.37 176826[89:Spt:176825.0] || -> until2p7(s24)*. % 76.16/76.37 176827[89:MRR:220.0,176826.0] || -> until2p7(s25)* node4(s24). % 76.16/76.37 176828[90:Spt:176827.0] || -> until2p7(s25)*. % 76.16/76.37 176829[90:MRR:221.0,176828.0] || -> until2p7(s26)* node4(s25). % 76.16/76.37 176830[91:Spt:176829.0] || -> until2p7(s26)*. % 76.16/76.37 176831[91:MRR:222.0,176830.0] || -> until2p7(s27)* node4(s26). % 76.16/76.37 176832[92:Spt:176831.0] || -> until2p7(s27)*. % 76.16/76.37 176833[92:MRR:223.0,176832.0] || -> until2p7(s28)* node4(s27). % 76.16/76.37 176834[93:Spt:176833.0] || -> until2p7(s28)*. % 76.16/76.37 176835[93:MRR:224.0,176834.0] || -> until2p7(s29)* node4(s28). % 76.16/76.37 176836[94:Spt:176835.0] || -> until2p7(s29)*. % 76.16/76.37 176837[94:MRR:225.0,176836.0] || -> until2p7(s30)* node4(s29). % 76.16/76.37 176838[95:Spt:176837.0] || -> until2p7(s30)*. % 76.16/76.37 176839[95:MRR:226.0,176838.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 176840[96:Spt:176839.0] || -> until2p7(s31)*. % 76.16/76.37 176841[96:MRR:227.0,176840.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 176842[97:Spt:176841.0] || -> until2p7(s32)*. % 76.16/76.37 176843[97:MRR:228.0,176842.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 176844[98:Spt:176843.0] || -> until2p7(s33)*. % 76.16/76.37 176845[98:MRR:229.0,176844.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 176846[99:Spt:176845.0] || -> until2p7(s34)*. % 76.16/76.37 176847[99:MRR:230.0,176846.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 176848[100:Spt:176847.0] || -> until2p7(s35)*. % 76.16/76.37 176849[100:MRR:231.0,176848.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 176850[101:Spt:176849.0] || -> until2p7(s36)*. % 76.16/76.37 176851[101:MRR:232.0,176850.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 176852[102:Spt:176851.0] || -> until2p7(s37)*. % 76.16/76.37 176853[102:MRR:235.0,176852.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 176854[103:Spt:176853.0] || -> until2p7(s38)*. % 76.16/76.37 176855[103:MRR:236.0,176854.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 176856[104:Spt:176855.0] || -> until2p7(s39)*. % 76.16/76.37 176857[104:MRR:237.0,176856.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 176858[105:Spt:176857.0] || -> until2p7(s40)*. % 76.16/76.37 176859[105:MRR:238.0,176858.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 176860[106:Spt:176859.0] || -> until2p7(s41)*. % 76.16/76.37 176861[106:MRR:239.0,176860.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 176862[107:Spt:176861.0] || -> until2p7(s42)*. % 76.16/76.37 176863[107:MRR:240.0,176862.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 176864[108:Spt:176863.0] || -> until2p7(s43)*. % 76.16/76.37 176865[108:MRR:241.0,176864.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 176866[109:Spt:176865.0] || -> until2p7(s44)*. % 76.16/76.37 176867[109:MRR:539.0,176866.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 176868[110:Spt:176867.0] || -> until2p7(s45)*. % 76.16/76.37 176869[110:MRR:544.0,176868.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 176870[111:Spt:176869.0] || -> until2p7(s46)*. % 76.16/76.37 176871[111:MRR:549.0,176870.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 176872[112:Spt:176871.0] || -> until2p7(s47)*. % 76.16/76.37 176873[112:MRR:554.0,176872.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 176874[113:Spt:176873.0] || -> until2p7(s48)*. % 76.16/76.37 176875[113:MRR:559.0,176874.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 176876[114:Spt:176875.0] || -> until2p7(s49)*. % 76.16/76.37 176877[114:MRR:194.0,176876.0] || -> node4(s49)*. % 76.16/76.37 176878[114:MRR:176814.0,176877.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 176879[114:Res:53.1,176878.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 176881[114:MRR:176879.0,78381.0] || -> . % 76.16/76.37 176882[114:Spt:176881.0,176875.0,176876.0] || until2p7(s49)*+ -> . % 76.16/76.37 176883[114:Spt:176881.0,176875.1] || -> node4(s48)*. % 76.16/76.37 176884[114:MRR:78384.0,176883.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 176887[114:Res:53.1,176884.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 176890[114:Res:176887.0,61.1] always3(s48) || -> . % 76.16/76.37 176891[114:SSi:176890.0,78281.0,78387.0,165540.0,176874.0,176883.0] || -> . % 76.16/76.37 176892[113:Spt:176891.0,176873.0,176874.0] || until2p7(s48)*+ -> . % 76.16/76.37 176893[113:Spt:176891.0,176873.1] || -> node4(s47)*. % 76.16/76.37 176895[113:MRR:777.0,176893.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 176910[113:Res:53.1,176895.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 176912[114:Spt:176910.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 176914[114:Res:176912.0,61.1] always3(s47) || -> . % 76.16/76.37 176915[114:SSi:176914.0,78277.0,78280.0,165539.0,176872.0,176893.0] || -> . % 76.16/76.37 176916[114:Spt:176915.0,176910.0,176912.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 176917[114:Spt:176915.0,176910.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 176921[114:Res:176917.0,61.1] always3(s48) || -> . % 76.16/76.37 176922[114:SSi:176921.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 176923[112:Spt:176922.0,176871.0,176872.0] || until2p7(s47)*+ -> . % 76.16/76.37 176924[112:Spt:176922.0,176871.1] || -> node4(s46)*. % 76.16/76.37 176926[112:MRR:780.0,176924.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 176936[112:Res:53.1,176926.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 176938[113:Spt:176936.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 176940[113:Res:176938.0,61.1] always3(s46) || -> . % 76.16/76.37 176941[113:SSi:176940.0,78272.0,78276.0,165538.0,176870.0,176924.0] || -> . % 76.16/76.37 176942[113:Spt:176941.0,176936.0,176938.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 176943[113:Spt:176941.0,176936.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 176947[113:Res:176943.0,61.1] always3(s47) || -> . % 76.16/76.37 176948[113:SSi:176947.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 176949[111:Spt:176948.0,176869.0,176870.0] || until2p7(s46)*+ -> . % 76.16/76.37 176950[111:Spt:176948.0,176869.1] || -> node4(s45)*. % 76.16/76.37 176952[111:MRR:783.0,176950.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 176955[111:Res:53.1,176952.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 176957[112:Spt:176955.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 176959[112:Res:176957.0,61.1] always3(s45) || -> . % 76.16/76.37 176960[112:SSi:176959.0,78268.0,78271.0,165537.0,176868.0,176950.0] || -> . % 76.16/76.37 176961[112:Spt:176960.0,176955.0,176957.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 176962[112:Spt:176960.0,176955.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 176966[112:Res:176962.0,61.1] always3(s46) || -> . % 76.16/76.37 176967[112:SSi:176966.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 176968[110:Spt:176967.0,176867.0,176868.0] || until2p7(s45)*+ -> . % 76.16/76.37 176969[110:Spt:176967.0,176867.1] || -> node4(s44)*. % 76.16/76.37 176971[110:MRR:786.0,176969.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 176974[110:Res:53.1,176971.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 176976[111:Spt:176974.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 176978[111:Res:176976.0,61.1] always3(s44) || -> . % 76.16/76.37 176979[111:SSi:176978.0,78263.0,78267.0,165536.0,176866.0,176969.0] || -> . % 76.16/76.37 176980[111:Spt:176979.0,176974.0,176976.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 176981[111:Spt:176979.0,176974.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 176985[111:Res:176981.0,61.1] always3(s45) || -> . % 76.16/76.37 176986[111:SSi:176985.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 176987[109:Spt:176986.0,176865.0,176866.0] || until2p7(s44)*+ -> . % 76.16/76.37 176988[109:Spt:176986.0,176865.1] || -> node4(s43)*. % 76.16/76.37 176990[109:MRR:789.0,176988.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 176993[109:Res:53.1,176990.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 176998[110:Spt:176993.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 177000[110:Res:176998.0,61.1] always3(s43) || -> . % 76.16/76.37 177001[110:SSi:177000.0,78259.0,78262.0,165535.0,176864.0,176988.0] || -> . % 76.16/76.37 177002[110:Spt:177001.0,176993.0,176998.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 177003[110:Spt:177001.0,176993.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 177007[110:Res:177003.0,61.1] always3(s44) || -> . % 76.16/76.37 177008[110:SSi:177007.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 177009[108:Spt:177008.0,176863.0,176864.0] || until2p7(s43)*+ -> . % 76.16/76.37 177010[108:Spt:177008.0,176863.1] || -> node4(s42)*. % 76.16/76.37 177012[108:MRR:792.0,177010.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 177015[108:Res:53.1,177012.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 177017[109:Spt:177015.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 177019[109:Res:177017.0,61.1] always3(s42) || -> . % 76.16/76.37 177020[109:SSi:177019.0,78254.0,78258.0,165534.0,176862.0,177010.0] || -> . % 76.16/76.37 177021[109:Spt:177020.0,177015.0,177017.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 177022[109:Spt:177020.0,177015.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 177026[109:Res:177022.0,61.1] always3(s43) || -> . % 76.16/76.37 177027[109:SSi:177026.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 177028[107:Spt:177027.0,176861.0,176862.0] || until2p7(s42)*+ -> . % 76.16/76.37 177029[107:Spt:177027.0,176861.1] || -> node4(s41)*. % 76.16/76.37 177031[107:MRR:795.0,177029.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 177034[107:Res:53.1,177031.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 177036[108:Spt:177034.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 177038[108:Res:177036.0,61.1] always3(s41) || -> . % 76.16/76.37 177039[108:SSi:177038.0,78250.0,78253.0,165533.0,176860.0,177029.0] || -> . % 76.16/76.37 177040[108:Spt:177039.0,177034.0,177036.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 177041[108:Spt:177039.0,177034.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 177045[108:Res:177041.0,61.1] always3(s42) || -> . % 76.16/76.37 177046[108:SSi:177045.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 177047[106:Spt:177046.0,176859.0,176860.0] || until2p7(s41)*+ -> . % 76.16/76.37 177048[106:Spt:177046.0,176859.1] || -> node4(s40)*. % 76.16/76.37 177050[106:MRR:798.0,177048.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 177053[106:Res:53.1,177050.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 177055[107:Spt:177053.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 177057[107:Res:177055.0,61.1] always3(s40) || -> . % 76.16/76.37 177058[107:SSi:177057.0,78245.0,78249.0,165532.0,176858.0,177048.0] || -> . % 76.16/76.37 177059[107:Spt:177058.0,177053.0,177055.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 177060[107:Spt:177058.0,177053.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 177064[107:Res:177060.0,61.1] always3(s41) || -> . % 76.16/76.37 177065[107:SSi:177064.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 177066[105:Spt:177065.0,176857.0,176858.0] || until2p7(s40)*+ -> . % 76.16/76.37 177067[105:Spt:177065.0,176857.1] || -> node4(s39)*. % 76.16/76.37 177069[105:MRR:801.0,177067.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 177072[105:Res:53.1,177069.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 177077[106:Spt:177072.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 177079[106:Res:177077.0,61.1] always3(s39) || -> . % 76.16/76.37 177080[106:SSi:177079.0,78241.0,78244.0,165531.0,176856.0,177067.0] || -> . % 76.16/76.37 177081[106:Spt:177080.0,177072.0,177077.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 177082[106:Spt:177080.0,177072.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 177086[106:Res:177082.0,61.1] always3(s40) || -> . % 76.16/76.37 177087[106:SSi:177086.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 177088[104:Spt:177087.0,176855.0,176856.0] || until2p7(s39)*+ -> . % 76.16/76.37 177089[104:Spt:177087.0,176855.1] || -> node4(s38)*. % 76.16/76.37 177091[104:MRR:804.0,177089.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 177094[104:Res:53.1,177091.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 177096[105:Spt:177094.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 177098[105:Res:177096.0,61.1] always3(s38) || -> . % 76.16/76.37 177099[105:SSi:177098.0,78236.0,78240.0,165530.0,176854.0,177089.0] || -> . % 76.16/76.37 177100[105:Spt:177099.0,177094.0,177096.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 177101[105:Spt:177099.0,177094.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 177105[105:Res:177101.0,61.1] always3(s39) || -> . % 76.16/76.37 177106[105:SSi:177105.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 177107[103:Spt:177106.0,176853.0,176854.0] || until2p7(s38)*+ -> . % 76.16/76.37 177108[103:Spt:177106.0,176853.1] || -> node4(s37)*. % 76.16/76.37 177110[103:MRR:807.0,177108.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 177113[103:Res:53.1,177110.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 177115[104:Spt:177113.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 177117[104:Res:177115.0,61.1] always3(s37) || -> . % 76.16/76.37 177118[104:SSi:177117.0,78232.0,78235.0,165529.0,176852.0,177108.0] || -> . % 76.16/76.37 177119[104:Spt:177118.0,177113.0,177115.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 177120[104:Spt:177118.0,177113.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 177124[104:Res:177120.0,61.1] always3(s38) || -> . % 76.16/76.37 177125[104:SSi:177124.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 177126[102:Spt:177125.0,176851.0,176852.0] || until2p7(s37)*+ -> . % 76.16/76.37 177127[102:Spt:177125.0,176851.1] || -> node4(s36)*. % 76.16/76.37 177129[102:MRR:810.0,177127.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 177132[102:Res:53.1,177129.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 177134[103:Spt:177132.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 177136[103:Res:177134.0,61.1] always3(s36) || -> . % 76.16/76.37 177137[103:SSi:177136.0,78227.0,78231.0,165528.0,176850.0,177127.0] || -> . % 76.16/76.37 177138[103:Spt:177137.0,177132.0,177134.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 177139[103:Spt:177137.0,177132.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 177143[103:Res:177139.0,61.1] always3(s37) || -> . % 76.16/76.37 177144[103:SSi:177143.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 177145[101:Spt:177144.0,176849.0,176850.0] || until2p7(s36)*+ -> . % 76.16/76.37 177146[101:Spt:177144.0,176849.1] || -> node4(s35)*. % 76.16/76.37 177148[101:MRR:813.0,177146.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 177151[101:Res:53.1,177148.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 177156[102:Spt:177151.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 177158[102:Res:177156.0,61.1] always3(s35) || -> . % 76.16/76.37 177159[102:SSi:177158.0,78223.0,78226.0,165527.0,176848.0,177146.0] || -> . % 76.16/76.37 177160[102:Spt:177159.0,177151.0,177156.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 177161[102:Spt:177159.0,177151.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 177165[102:Res:177161.0,61.1] always3(s36) || -> . % 76.16/76.37 177166[102:SSi:177165.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 177167[100:Spt:177166.0,176847.0,176848.0] || until2p7(s35)*+ -> . % 76.16/76.37 177168[100:Spt:177166.0,176847.1] || -> node4(s34)*. % 76.16/76.37 177170[100:MRR:816.0,177168.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 177173[100:Res:53.1,177170.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 177175[101:Spt:177173.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 177177[101:Res:177175.0,61.1] always3(s34) || -> . % 76.16/76.37 177178[101:SSi:177177.0,78218.0,78222.0,165526.0,176846.0,177168.0] || -> . % 76.16/76.37 177179[101:Spt:177178.0,177173.0,177175.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 177180[101:Spt:177178.0,177173.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 177184[101:Res:177180.0,61.1] always3(s35) || -> . % 76.16/76.37 177185[101:SSi:177184.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 177186[99:Spt:177185.0,176845.0,176846.0] || until2p7(s34)*+ -> . % 76.16/76.37 177187[99:Spt:177185.0,176845.1] || -> node4(s33)*. % 76.16/76.37 177189[99:MRR:819.0,177187.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 177192[99:Res:53.1,177189.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 177194[100:Spt:177192.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 177196[100:Res:177194.0,61.1] always3(s33) || -> . % 76.16/76.37 177197[100:SSi:177196.0,78214.0,78217.0,165525.0,176844.0,177187.0] || -> . % 76.16/76.37 177198[100:Spt:177197.0,177192.0,177194.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 177199[100:Spt:177197.0,177192.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 177203[100:Res:177199.0,61.1] always3(s34) || -> . % 76.16/76.37 177204[100:SSi:177203.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 177205[98:Spt:177204.0,176843.0,176844.0] || until2p7(s33)*+ -> . % 76.16/76.37 177206[98:Spt:177204.0,176843.1] || -> node4(s32)*. % 76.16/76.37 177208[98:MRR:822.0,177206.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 177211[98:Res:53.1,177208.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 177213[99:Spt:177211.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 177215[99:Res:177213.0,61.1] always3(s32) || -> . % 76.16/76.37 177216[99:SSi:177215.0,78209.0,78213.0,165524.0,176842.0,177206.0] || -> . % 76.16/76.37 177217[99:Spt:177216.0,177211.0,177213.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 177218[99:Spt:177216.0,177211.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 177222[99:Res:177218.0,61.1] always3(s33) || -> . % 76.16/76.37 177223[99:SSi:177222.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 177224[97:Spt:177223.0,176841.0,176842.0] || until2p7(s32)*+ -> . % 76.16/76.37 177225[97:Spt:177223.0,176841.1] || -> node4(s31)*. % 76.16/76.37 177227[97:MRR:825.0,177225.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 177230[97:Res:53.1,177227.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 177235[98:Spt:177230.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 177237[98:Res:177235.0,61.1] always3(s31) || -> . % 76.16/76.37 177238[98:SSi:177237.0,78205.0,78208.0,165523.0,176840.0,177225.0] || -> . % 76.16/76.37 177239[98:Spt:177238.0,177230.0,177235.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 177240[98:Spt:177238.0,177230.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 177244[98:Res:177240.0,61.1] always3(s32) || -> . % 76.16/76.37 177245[98:SSi:177244.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 177246[96:Spt:177245.0,176839.0,176840.0] || until2p7(s31)*+ -> . % 76.16/76.37 177247[96:Spt:177245.0,176839.1] || -> node4(s30)*. % 76.16/76.37 177249[96:MRR:828.0,177247.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 177252[96:Res:53.1,177249.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 177254[97:Spt:177252.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 177256[97:Res:177254.0,61.1] always3(s30) || -> . % 76.16/76.37 177257[97:SSi:177256.0,78200.0,78204.0,165522.0,176838.0,177247.0] || -> . % 76.16/76.37 177258[97:Spt:177257.0,177252.0,177254.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.37 177259[97:Spt:177257.0,177252.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 177263[97:Res:177259.0,61.1] always3(s31) || -> . % 76.16/76.37 177264[97:SSi:177263.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 177265[95:Spt:177264.0,176837.0,176838.0] || until2p7(s30)*+ -> . % 76.16/76.37 177266[95:Spt:177264.0,176837.1] || -> node4(s29)*. % 76.16/76.37 177268[95:MRR:831.0,177266.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.37 177271[95:Res:53.1,177268.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.37 177273[96:Spt:177271.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 177275[96:Res:177273.0,61.1] always3(s29) || -> . % 76.16/76.37 177276[96:SSi:177275.0,78196.0,78199.0,165521.0,176836.0,177266.0] || -> . % 76.16/76.37 177277[96:Spt:177276.0,177271.0,177273.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.37 177278[96:Spt:177276.0,177271.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 177282[96:Res:177278.0,61.1] always3(s30) || -> . % 76.16/76.37 177283[96:SSi:177282.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 177284[94:Spt:177283.0,176835.0,176836.0] || until2p7(s29)*+ -> . % 76.16/76.37 177285[94:Spt:177283.0,176835.1] || -> node4(s28)*. % 76.16/76.37 177287[94:MRR:834.0,177285.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.37 177290[94:Res:53.1,177287.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.37 177292[95:Spt:177290.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 177294[95:Res:177292.0,61.1] always3(s28) || -> . % 76.16/76.37 177295[95:SSi:177294.0,78191.0,78195.0,165520.0,176834.0,177285.0] || -> . % 76.16/76.37 177296[95:Spt:177295.0,177290.0,177292.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.37 177297[95:Spt:177295.0,177290.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 177301[95:Res:177297.0,61.1] always3(s29) || -> . % 76.16/76.37 177302[95:SSi:177301.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.37 177303[93:Spt:177302.0,176833.0,176834.0] || until2p7(s28)*+ -> . % 76.16/76.37 177304[93:Spt:177302.0,176833.1] || -> node4(s27)*. % 76.16/76.37 177306[93:MRR:837.0,177304.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.37 177309[93:Res:53.1,177306.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.37 177314[94:Spt:177309.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 177316[94:Res:177314.0,61.1] always3(s27) || -> . % 76.16/76.37 177317[94:SSi:177316.0,78187.0,78190.0,165519.0,176832.0,177304.0] || -> . % 76.16/76.37 177318[94:Spt:177317.0,177309.0,177314.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.37 177319[94:Spt:177317.0,177309.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 177323[94:Res:177319.0,61.1] always3(s28) || -> . % 76.16/76.37 177324[94:SSi:177323.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.37 177325[92:Spt:177324.0,176831.0,176832.0] || until2p7(s27)*+ -> . % 76.16/76.37 177326[92:Spt:177324.0,176831.1] || -> node4(s26)*. % 76.16/76.37 177328[92:MRR:840.0,177326.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.37 177331[92:Res:53.1,177328.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.37 177333[93:Spt:177331.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 177335[93:Res:177333.0,61.1] always3(s26) || -> . % 76.16/76.37 177336[93:SSi:177335.0,78182.0,78186.0,165518.0,176830.0,177326.0] || -> . % 76.16/76.37 177337[93:Spt:177336.0,177331.0,177333.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.37 177338[93:Spt:177336.0,177331.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 177342[93:Res:177338.0,61.1] always3(s27) || -> . % 76.16/76.37 177343[93:SSi:177342.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.37 177344[91:Spt:177343.0,176829.0,176830.0] || until2p7(s26)*+ -> . % 76.16/76.37 177345[91:Spt:177343.0,176829.1] || -> node4(s25)*. % 76.16/76.37 177347[91:MRR:843.0,177345.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.37 177350[91:Res:53.1,177347.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.37 177352[92:Spt:177350.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 177354[92:Res:177352.0,61.1] always3(s25) || -> . % 76.16/76.37 177355[92:SSi:177354.0,78178.0,78181.0,165517.0,176828.0,177345.0] || -> . % 76.16/76.37 177356[92:Spt:177355.0,177350.0,177352.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.37 177357[92:Spt:177355.0,177350.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 177361[92:Res:177357.0,61.1] always3(s26) || -> . % 76.16/76.37 177362[92:SSi:177361.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.37 177363[90:Spt:177362.0,176827.0,176828.0] || until2p7(s25)*+ -> . % 76.16/76.37 177364[90:Spt:177362.0,176827.1] || -> node4(s24)*. % 76.16/76.37 177366[90:MRR:846.0,177364.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.37 177369[90:Res:53.1,177366.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.37 177371[91:Spt:177369.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 177373[91:Res:177371.0,61.1] always3(s24) || -> . % 76.16/76.37 177374[91:SSi:177373.0,78173.0,78177.0,165516.0,176826.0,177364.0] || -> . % 76.16/76.37 177375[91:Spt:177374.0,177369.0,177371.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.37 177376[91:Spt:177374.0,177369.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 177380[91:Res:177376.0,61.1] always3(s25) || -> . % 76.16/76.37 177381[91:SSi:177380.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.37 177382[89:Spt:177381.0,176825.0,176826.0] || until2p7(s24)*+ -> . % 76.16/76.37 177383[89:Spt:177381.0,176825.1] || -> node4(s23)*. % 76.16/76.37 177385[89:MRR:849.0,177383.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.37 177388[89:Res:53.1,177385.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.37 177393[90:Spt:177388.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 177395[90:Res:177393.0,61.1] always3(s23) || -> . % 76.16/76.37 177396[90:SSi:177395.0,78169.0,78172.0,165515.0,176824.0,177383.0] || -> . % 76.16/76.37 177397[90:Spt:177396.0,177388.0,177393.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.37 177398[90:Spt:177396.0,177388.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 177402[90:Res:177398.0,61.1] always3(s24) || -> . % 76.16/76.37 177403[90:SSi:177402.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.37 177404[88:Spt:177403.0,176823.0,176824.0] || until2p7(s23)*+ -> . % 76.16/76.37 177405[88:Spt:177403.0,176823.1] || -> node4(s22)*. % 76.16/76.37 177407[88:MRR:852.0,177405.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.37 177410[88:Res:53.1,177407.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.37 177412[89:Spt:177410.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.37 177414[89:Res:177412.0,61.1] always3(s22) || -> . % 76.16/76.37 177415[89:SSi:177414.0,78164.0,78168.0,165514.0,176822.0,177405.0] || -> . % 76.16/76.37 177416[89:Spt:177415.0,177410.0,177412.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.37 177417[89:Spt:177415.0,177410.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 177421[89:Res:177417.0,61.1] always3(s23) || -> . % 76.16/76.37 177422[89:SSi:177421.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.37 177423[87:Spt:177422.0,176821.0,176822.0] || until2p7(s22)*+ -> . % 76.16/76.37 177424[87:Spt:177422.0,176821.1] || -> node4(s21)*. % 76.16/76.37 177426[87:MRR:855.0,177424.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.37 177429[87:Res:53.1,177426.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.37 177431[88:Spt:177429.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.37 177433[88:Res:177431.0,61.1] always3(s21) || -> . % 76.16/76.37 177434[88:SSi:177433.0,78160.0,78163.0,165513.0,176820.0,177424.0] || -> . % 76.16/76.37 177435[88:Spt:177434.0,177429.0,177431.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.37 177436[88:Spt:177434.0,177429.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.37 177440[88:Res:177436.0,61.1] always3(s22) || -> . % 76.16/76.37 177441[88:SSi:177440.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.37 177442[86:Spt:177441.0,176819.0,176820.0] || until2p7(s21)*+ -> . % 76.16/76.37 177443[86:Spt:177441.0,176819.1] || -> node4(s20)*. % 76.16/76.37 177445[86:MRR:858.0,177443.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.37 177448[86:Res:53.1,177445.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.37 177450[86:MRR:177448.0,176809.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.37 177452[86:Res:177450.0,61.1] always3(s21) || -> . % 76.16/76.37 177453[86:SSi:177452.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.37 177454[84:Spt:177453.0,176695.0,176698.0] || trans(s49,s20)*+ -> . % 76.16/76.37 177455[84:Spt:177453.0,176695.1,176695.2,176695.3,176695.4,176695.5,176695.6,176695.7,176695.8,176695.9,176695.10,176695.11,176695.12,176695.13,176695.14,176695.15] || -> trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 177457[84:MRR:176697.1,177454.0] xuntil6(s49) || -> trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 177458[85:Spt:177455.0] || -> trans(s49,s19)*. % 76.16/76.37 177459[85:Res:177458.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s19)*. % 76.16/76.37 177461[85:Res:177458.0,60.0] || -> node2(s49,s19)*. % 76.16/76.37 177462[85:SSi:177459.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s19)*. % 76.16/76.37 177463[85:Res:177461.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)*. % 76.16/76.37 177565[85:SoR:177463.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)*. % 76.16/76.37 177567[85:SoR:177565.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)* xuntil6(s49). % 76.16/76.37 177568[85:SSi:177567.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s19,c_busy)* xuntil6(s49). % 76.16/76.37 177569[86:Spt:177568.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.37 177571[86:Res:177569.0,61.1] always3(s19) || -> . % 76.16/76.37 177572[86:SSi:177571.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.37 177573[86:Spt:177572.0,177568.1,177569.0] || m_main_v_state(s19,c_busy)*+ -> . % 76.16/76.37 177574[86:Spt:177572.0,177568.0,177568.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 177578[86:MRR:177565.2,177573.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 177579[86:Res:53.1,177574.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 177581[86:MRR:177579.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 177582[86:MRR:177462.0,177581.0] || -> until2p7(s19)*. % 76.16/76.37 177583[86:MRR:215.0,177582.0] || -> until2p7(s20)* node4(s19). % 76.16/76.37 177584[87:Spt:177583.0] || -> until2p7(s20)*. % 76.16/76.37 177585[87:MRR:216.0,177584.0] || -> until2p7(s21)* node4(s20). % 76.16/76.37 177586[88:Spt:177585.0] || -> until2p7(s21)*. % 76.16/76.37 177587[88:MRR:217.0,177586.0] || -> until2p7(s22)* node4(s21). % 76.16/76.37 177588[89:Spt:177587.0] || -> until2p7(s22)*. % 76.16/76.37 177589[89:MRR:218.0,177588.0] || -> until2p7(s23)* node4(s22). % 76.16/76.37 177590[90:Spt:177589.0] || -> until2p7(s23)*. % 76.16/76.37 177591[90:MRR:219.0,177590.0] || -> until2p7(s24)* node4(s23). % 76.16/76.37 177592[91:Spt:177591.0] || -> until2p7(s24)*. % 76.16/76.37 177593[91:MRR:220.0,177592.0] || -> until2p7(s25)* node4(s24). % 76.16/76.37 177594[92:Spt:177593.0] || -> until2p7(s25)*. % 76.16/76.37 177595[92:MRR:221.0,177594.0] || -> until2p7(s26)* node4(s25). % 76.16/76.37 177596[93:Spt:177595.0] || -> until2p7(s26)*. % 76.16/76.37 177597[93:MRR:222.0,177596.0] || -> until2p7(s27)* node4(s26). % 76.16/76.37 177598[94:Spt:177597.0] || -> until2p7(s27)*. % 76.16/76.37 177599[94:MRR:223.0,177598.0] || -> until2p7(s28)* node4(s27). % 76.16/76.37 177600[95:Spt:177599.0] || -> until2p7(s28)*. % 76.16/76.37 177601[95:MRR:224.0,177600.0] || -> until2p7(s29)* node4(s28). % 76.16/76.37 177602[96:Spt:177601.0] || -> until2p7(s29)*. % 76.16/76.37 177603[96:MRR:225.0,177602.0] || -> until2p7(s30)* node4(s29). % 76.16/76.37 177604[97:Spt:177603.0] || -> until2p7(s30)*. % 76.16/76.37 177605[97:MRR:226.0,177604.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 177606[98:Spt:177605.0] || -> until2p7(s31)*. % 76.16/76.37 177607[98:MRR:227.0,177606.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 177608[99:Spt:177607.0] || -> until2p7(s32)*. % 76.16/76.37 177609[99:MRR:228.0,177608.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 177610[100:Spt:177609.0] || -> until2p7(s33)*. % 76.16/76.37 177611[100:MRR:229.0,177610.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 177612[101:Spt:177611.0] || -> until2p7(s34)*. % 76.16/76.37 177613[101:MRR:230.0,177612.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 177614[102:Spt:177613.0] || -> until2p7(s35)*. % 76.16/76.37 177615[102:MRR:231.0,177614.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 177616[103:Spt:177615.0] || -> until2p7(s36)*. % 76.16/76.37 177617[103:MRR:232.0,177616.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 177618[104:Spt:177617.0] || -> until2p7(s37)*. % 76.16/76.37 177619[104:MRR:235.0,177618.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 177620[105:Spt:177619.0] || -> until2p7(s38)*. % 76.16/76.37 177621[105:MRR:236.0,177620.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 177622[106:Spt:177621.0] || -> until2p7(s39)*. % 76.16/76.37 177623[106:MRR:237.0,177622.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 177624[107:Spt:177623.0] || -> until2p7(s40)*. % 76.16/76.37 177625[107:MRR:238.0,177624.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 177626[108:Spt:177625.0] || -> until2p7(s41)*. % 76.16/76.37 177627[108:MRR:239.0,177626.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 177628[109:Spt:177627.0] || -> until2p7(s42)*. % 76.16/76.37 177629[109:MRR:240.0,177628.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 177630[110:Spt:177629.0] || -> until2p7(s43)*. % 76.16/76.37 177631[110:MRR:241.0,177630.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 177632[111:Spt:177631.0] || -> until2p7(s44)*. % 76.16/76.37 177633[111:MRR:539.0,177632.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 177634[112:Spt:177633.0] || -> until2p7(s45)*. % 76.16/76.37 177635[112:MRR:544.0,177634.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 177636[113:Spt:177635.0] || -> until2p7(s46)*. % 76.16/76.37 177637[113:MRR:549.0,177636.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 177638[114:Spt:177637.0] || -> until2p7(s47)*. % 76.16/76.37 177639[114:MRR:554.0,177638.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 177640[115:Spt:177639.0] || -> until2p7(s48)*. % 76.16/76.37 177641[115:MRR:559.0,177640.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 177642[116:Spt:177641.0] || -> until2p7(s49)*. % 76.16/76.37 177643[116:MRR:194.0,177642.0] || -> node4(s49)*. % 76.16/76.37 177644[116:MRR:177578.0,177643.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 177645[116:Res:53.1,177644.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 177647[116:MRR:177645.0,78381.0] || -> . % 76.16/76.37 177648[116:Spt:177647.0,177641.0,177642.0] || until2p7(s49)*+ -> . % 76.16/76.37 177649[116:Spt:177647.0,177641.1] || -> node4(s48)*. % 76.16/76.37 177650[116:MRR:78384.0,177649.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 177653[116:Res:53.1,177650.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 177656[116:Res:177653.0,61.1] always3(s48) || -> . % 76.16/76.37 177657[116:SSi:177656.0,78281.0,78387.0,165540.0,177640.0,177649.0] || -> . % 76.16/76.37 177658[115:Spt:177657.0,177639.0,177640.0] || until2p7(s48)*+ -> . % 76.16/76.37 177659[115:Spt:177657.0,177639.1] || -> node4(s47)*. % 76.16/76.37 177661[115:MRR:777.0,177659.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 177676[115:Res:53.1,177661.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 177678[116:Spt:177676.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 177680[116:Res:177678.0,61.1] always3(s47) || -> . % 76.16/76.37 177681[116:SSi:177680.0,78277.0,78280.0,165539.0,177638.0,177659.0] || -> . % 76.16/76.37 177682[116:Spt:177681.0,177676.0,177678.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 177683[116:Spt:177681.0,177676.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 177687[116:Res:177683.0,61.1] always3(s48) || -> . % 76.16/76.37 177688[116:SSi:177687.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 177689[114:Spt:177688.0,177637.0,177638.0] || until2p7(s47)*+ -> . % 76.16/76.37 177690[114:Spt:177688.0,177637.1] || -> node4(s46)*. % 76.16/76.37 177692[114:MRR:780.0,177690.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 177702[114:Res:53.1,177692.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 177704[115:Spt:177702.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 177706[115:Res:177704.0,61.1] always3(s46) || -> . % 76.16/76.37 177707[115:SSi:177706.0,78272.0,78276.0,165538.0,177636.0,177690.0] || -> . % 76.16/76.37 177708[115:Spt:177707.0,177702.0,177704.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 177709[115:Spt:177707.0,177702.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 177713[115:Res:177709.0,61.1] always3(s47) || -> . % 76.16/76.37 177714[115:SSi:177713.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 177715[113:Spt:177714.0,177635.0,177636.0] || until2p7(s46)*+ -> . % 76.16/76.37 177716[113:Spt:177714.0,177635.1] || -> node4(s45)*. % 76.16/76.37 177718[113:MRR:783.0,177716.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 177721[113:Res:53.1,177718.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 177723[114:Spt:177721.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 177725[114:Res:177723.0,61.1] always3(s45) || -> . % 76.16/76.37 177726[114:SSi:177725.0,78268.0,78271.0,165537.0,177634.0,177716.0] || -> . % 76.16/76.37 177727[114:Spt:177726.0,177721.0,177723.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 177728[114:Spt:177726.0,177721.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 177732[114:Res:177728.0,61.1] always3(s46) || -> . % 76.16/76.37 177733[114:SSi:177732.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 177734[112:Spt:177733.0,177633.0,177634.0] || until2p7(s45)*+ -> . % 76.16/76.37 177735[112:Spt:177733.0,177633.1] || -> node4(s44)*. % 76.16/76.37 177737[112:MRR:786.0,177735.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 177740[112:Res:53.1,177737.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 177742[113:Spt:177740.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 177744[113:Res:177742.0,61.1] always3(s44) || -> . % 76.16/76.37 177745[113:SSi:177744.0,78263.0,78267.0,165536.0,177632.0,177735.0] || -> . % 76.16/76.37 177746[113:Spt:177745.0,177740.0,177742.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 177747[113:Spt:177745.0,177740.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 177751[113:Res:177747.0,61.1] always3(s45) || -> . % 76.16/76.37 177752[113:SSi:177751.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 177753[111:Spt:177752.0,177631.0,177632.0] || until2p7(s44)*+ -> . % 76.16/76.37 177754[111:Spt:177752.0,177631.1] || -> node4(s43)*. % 76.16/76.37 177756[111:MRR:789.0,177754.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 177759[111:Res:53.1,177756.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 177764[112:Spt:177759.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 177766[112:Res:177764.0,61.1] always3(s43) || -> . % 76.16/76.37 177767[112:SSi:177766.0,78259.0,78262.0,165535.0,177630.0,177754.0] || -> . % 76.16/76.37 177768[112:Spt:177767.0,177759.0,177764.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 177769[112:Spt:177767.0,177759.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 177773[112:Res:177769.0,61.1] always3(s44) || -> . % 76.16/76.37 177774[112:SSi:177773.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 177775[110:Spt:177774.0,177629.0,177630.0] || until2p7(s43)*+ -> . % 76.16/76.37 177776[110:Spt:177774.0,177629.1] || -> node4(s42)*. % 76.16/76.37 177778[110:MRR:792.0,177776.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 177781[110:Res:53.1,177778.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 177783[111:Spt:177781.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 177785[111:Res:177783.0,61.1] always3(s42) || -> . % 76.16/76.37 177786[111:SSi:177785.0,78254.0,78258.0,165534.0,177628.0,177776.0] || -> . % 76.16/76.37 177787[111:Spt:177786.0,177781.0,177783.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 177788[111:Spt:177786.0,177781.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 177792[111:Res:177788.0,61.1] always3(s43) || -> . % 76.16/76.37 177793[111:SSi:177792.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 177794[109:Spt:177793.0,177627.0,177628.0] || until2p7(s42)*+ -> . % 76.16/76.37 177795[109:Spt:177793.0,177627.1] || -> node4(s41)*. % 76.16/76.37 177797[109:MRR:795.0,177795.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 177800[109:Res:53.1,177797.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 177802[110:Spt:177800.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 177804[110:Res:177802.0,61.1] always3(s41) || -> . % 76.16/76.37 177805[110:SSi:177804.0,78250.0,78253.0,165533.0,177626.0,177795.0] || -> . % 76.16/76.37 177806[110:Spt:177805.0,177800.0,177802.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 177807[110:Spt:177805.0,177800.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 177811[110:Res:177807.0,61.1] always3(s42) || -> . % 76.16/76.37 177812[110:SSi:177811.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 177813[108:Spt:177812.0,177625.0,177626.0] || until2p7(s41)*+ -> . % 76.16/76.37 177814[108:Spt:177812.0,177625.1] || -> node4(s40)*. % 76.16/76.37 177816[108:MRR:798.0,177814.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 177819[108:Res:53.1,177816.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 177821[109:Spt:177819.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 177823[109:Res:177821.0,61.1] always3(s40) || -> . % 76.16/76.37 177824[109:SSi:177823.0,78245.0,78249.0,165532.0,177624.0,177814.0] || -> . % 76.16/76.37 177825[109:Spt:177824.0,177819.0,177821.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 177826[109:Spt:177824.0,177819.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 177830[109:Res:177826.0,61.1] always3(s41) || -> . % 76.16/76.37 177831[109:SSi:177830.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 177832[107:Spt:177831.0,177623.0,177624.0] || until2p7(s40)*+ -> . % 76.16/76.37 177833[107:Spt:177831.0,177623.1] || -> node4(s39)*. % 76.16/76.37 177835[107:MRR:801.0,177833.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 177838[107:Res:53.1,177835.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 177843[108:Spt:177838.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 177845[108:Res:177843.0,61.1] always3(s39) || -> . % 76.16/76.37 177846[108:SSi:177845.0,78241.0,78244.0,165531.0,177622.0,177833.0] || -> . % 76.16/76.37 177847[108:Spt:177846.0,177838.0,177843.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 177848[108:Spt:177846.0,177838.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 177852[108:Res:177848.0,61.1] always3(s40) || -> . % 76.16/76.37 177853[108:SSi:177852.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 177854[106:Spt:177853.0,177621.0,177622.0] || until2p7(s39)*+ -> . % 76.16/76.37 177855[106:Spt:177853.0,177621.1] || -> node4(s38)*. % 76.16/76.37 177857[106:MRR:804.0,177855.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 177860[106:Res:53.1,177857.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 177862[107:Spt:177860.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 177864[107:Res:177862.0,61.1] always3(s38) || -> . % 76.16/76.37 177865[107:SSi:177864.0,78236.0,78240.0,165530.0,177620.0,177855.0] || -> . % 76.16/76.37 177866[107:Spt:177865.0,177860.0,177862.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 177867[107:Spt:177865.0,177860.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 177871[107:Res:177867.0,61.1] always3(s39) || -> . % 76.16/76.37 177872[107:SSi:177871.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 177873[105:Spt:177872.0,177619.0,177620.0] || until2p7(s38)*+ -> . % 76.16/76.37 177874[105:Spt:177872.0,177619.1] || -> node4(s37)*. % 76.16/76.37 177876[105:MRR:807.0,177874.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 177879[105:Res:53.1,177876.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 177881[106:Spt:177879.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 177883[106:Res:177881.0,61.1] always3(s37) || -> . % 76.16/76.37 177884[106:SSi:177883.0,78232.0,78235.0,165529.0,177618.0,177874.0] || -> . % 76.16/76.37 177885[106:Spt:177884.0,177879.0,177881.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 177886[106:Spt:177884.0,177879.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 177890[106:Res:177886.0,61.1] always3(s38) || -> . % 76.16/76.37 177891[106:SSi:177890.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 177892[104:Spt:177891.0,177617.0,177618.0] || until2p7(s37)*+ -> . % 76.16/76.37 177893[104:Spt:177891.0,177617.1] || -> node4(s36)*. % 76.16/76.37 177895[104:MRR:810.0,177893.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 177898[104:Res:53.1,177895.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 177900[105:Spt:177898.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 177902[105:Res:177900.0,61.1] always3(s36) || -> . % 76.16/76.37 177903[105:SSi:177902.0,78227.0,78231.0,165528.0,177616.0,177893.0] || -> . % 76.16/76.37 177904[105:Spt:177903.0,177898.0,177900.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 177905[105:Spt:177903.0,177898.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 177909[105:Res:177905.0,61.1] always3(s37) || -> . % 76.16/76.37 177910[105:SSi:177909.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 177911[103:Spt:177910.0,177615.0,177616.0] || until2p7(s36)*+ -> . % 76.16/76.37 177912[103:Spt:177910.0,177615.1] || -> node4(s35)*. % 76.16/76.37 177914[103:MRR:813.0,177912.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 177917[103:Res:53.1,177914.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 177922[104:Spt:177917.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 177924[104:Res:177922.0,61.1] always3(s35) || -> . % 76.16/76.37 177925[104:SSi:177924.0,78223.0,78226.0,165527.0,177614.0,177912.0] || -> . % 76.16/76.37 177926[104:Spt:177925.0,177917.0,177922.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 177927[104:Spt:177925.0,177917.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 177931[104:Res:177927.0,61.1] always3(s36) || -> . % 76.16/76.37 177932[104:SSi:177931.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 177933[102:Spt:177932.0,177613.0,177614.0] || until2p7(s35)*+ -> . % 76.16/76.37 177934[102:Spt:177932.0,177613.1] || -> node4(s34)*. % 76.16/76.37 177936[102:MRR:816.0,177934.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 177939[102:Res:53.1,177936.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 177941[103:Spt:177939.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 177943[103:Res:177941.0,61.1] always3(s34) || -> . % 76.16/76.37 177944[103:SSi:177943.0,78218.0,78222.0,165526.0,177612.0,177934.0] || -> . % 76.16/76.37 177945[103:Spt:177944.0,177939.0,177941.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 177946[103:Spt:177944.0,177939.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 177950[103:Res:177946.0,61.1] always3(s35) || -> . % 76.16/76.37 177951[103:SSi:177950.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 177952[101:Spt:177951.0,177611.0,177612.0] || until2p7(s34)*+ -> . % 76.16/76.37 177953[101:Spt:177951.0,177611.1] || -> node4(s33)*. % 76.16/76.37 177955[101:MRR:819.0,177953.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 177958[101:Res:53.1,177955.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 177960[102:Spt:177958.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 177962[102:Res:177960.0,61.1] always3(s33) || -> . % 76.16/76.37 177963[102:SSi:177962.0,78214.0,78217.0,165525.0,177610.0,177953.0] || -> . % 76.16/76.37 177964[102:Spt:177963.0,177958.0,177960.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 177965[102:Spt:177963.0,177958.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 177969[102:Res:177965.0,61.1] always3(s34) || -> . % 76.16/76.37 177970[102:SSi:177969.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 177971[100:Spt:177970.0,177609.0,177610.0] || until2p7(s33)*+ -> . % 76.16/76.37 177972[100:Spt:177970.0,177609.1] || -> node4(s32)*. % 76.16/76.37 177974[100:MRR:822.0,177972.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 177977[100:Res:53.1,177974.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 177979[101:Spt:177977.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 177981[101:Res:177979.0,61.1] always3(s32) || -> . % 76.16/76.37 177982[101:SSi:177981.0,78209.0,78213.0,165524.0,177608.0,177972.0] || -> . % 76.16/76.37 177983[101:Spt:177982.0,177977.0,177979.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 177984[101:Spt:177982.0,177977.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 177988[101:Res:177984.0,61.1] always3(s33) || -> . % 76.16/76.37 177989[101:SSi:177988.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 177990[99:Spt:177989.0,177607.0,177608.0] || until2p7(s32)*+ -> . % 76.16/76.37 177991[99:Spt:177989.0,177607.1] || -> node4(s31)*. % 76.16/76.37 177993[99:MRR:825.0,177991.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 177996[99:Res:53.1,177993.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 178001[100:Spt:177996.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 178003[100:Res:178001.0,61.1] always3(s31) || -> . % 76.16/76.37 178004[100:SSi:178003.0,78205.0,78208.0,165523.0,177606.0,177991.0] || -> . % 76.16/76.37 178005[100:Spt:178004.0,177996.0,178001.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 178006[100:Spt:178004.0,177996.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 178010[100:Res:178006.0,61.1] always3(s32) || -> . % 76.16/76.37 178011[100:SSi:178010.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 178012[98:Spt:178011.0,177605.0,177606.0] || until2p7(s31)*+ -> . % 76.16/76.37 178013[98:Spt:178011.0,177605.1] || -> node4(s30)*. % 76.16/76.37 178015[98:MRR:828.0,178013.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 178018[98:Res:53.1,178015.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 178020[99:Spt:178018.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 178022[99:Res:178020.0,61.1] always3(s30) || -> . % 76.16/76.37 178023[99:SSi:178022.0,78200.0,78204.0,165522.0,177604.0,178013.0] || -> . % 76.16/76.37 178024[99:Spt:178023.0,178018.0,178020.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.37 178025[99:Spt:178023.0,178018.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 178029[99:Res:178025.0,61.1] always3(s31) || -> . % 76.16/76.37 178030[99:SSi:178029.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 178031[97:Spt:178030.0,177603.0,177604.0] || until2p7(s30)*+ -> . % 76.16/76.37 178032[97:Spt:178030.0,177603.1] || -> node4(s29)*. % 76.16/76.37 178034[97:MRR:831.0,178032.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.37 178037[97:Res:53.1,178034.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.37 178039[98:Spt:178037.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 178041[98:Res:178039.0,61.1] always3(s29) || -> . % 76.16/76.37 178042[98:SSi:178041.0,78196.0,78199.0,165521.0,177602.0,178032.0] || -> . % 76.16/76.37 178043[98:Spt:178042.0,178037.0,178039.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.37 178044[98:Spt:178042.0,178037.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 178048[98:Res:178044.0,61.1] always3(s30) || -> . % 76.16/76.37 178049[98:SSi:178048.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 178050[96:Spt:178049.0,177601.0,177602.0] || until2p7(s29)*+ -> . % 76.16/76.37 178051[96:Spt:178049.0,177601.1] || -> node4(s28)*. % 76.16/76.37 178053[96:MRR:834.0,178051.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.37 178056[96:Res:53.1,178053.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.37 178058[97:Spt:178056.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 178060[97:Res:178058.0,61.1] always3(s28) || -> . % 76.16/76.37 178061[97:SSi:178060.0,78191.0,78195.0,165520.0,177600.0,178051.0] || -> . % 76.16/76.37 178062[97:Spt:178061.0,178056.0,178058.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.37 178063[97:Spt:178061.0,178056.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 178067[97:Res:178063.0,61.1] always3(s29) || -> . % 76.16/76.37 178068[97:SSi:178067.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.37 178069[95:Spt:178068.0,177599.0,177600.0] || until2p7(s28)*+ -> . % 76.16/76.37 178070[95:Spt:178068.0,177599.1] || -> node4(s27)*. % 76.16/76.37 178072[95:MRR:837.0,178070.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.37 178075[95:Res:53.1,178072.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.37 178080[96:Spt:178075.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 178082[96:Res:178080.0,61.1] always3(s27) || -> . % 76.16/76.37 178083[96:SSi:178082.0,78187.0,78190.0,165519.0,177598.0,178070.0] || -> . % 76.16/76.37 178084[96:Spt:178083.0,178075.0,178080.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.37 178085[96:Spt:178083.0,178075.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 178089[96:Res:178085.0,61.1] always3(s28) || -> . % 76.16/76.37 178090[96:SSi:178089.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.37 178091[94:Spt:178090.0,177597.0,177598.0] || until2p7(s27)*+ -> . % 76.16/76.37 178092[94:Spt:178090.0,177597.1] || -> node4(s26)*. % 76.16/76.37 178094[94:MRR:840.0,178092.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.37 178097[94:Res:53.1,178094.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.37 178099[95:Spt:178097.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 178101[95:Res:178099.0,61.1] always3(s26) || -> . % 76.16/76.37 178102[95:SSi:178101.0,78182.0,78186.0,165518.0,177596.0,178092.0] || -> . % 76.16/76.37 178103[95:Spt:178102.0,178097.0,178099.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.37 178104[95:Spt:178102.0,178097.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 178108[95:Res:178104.0,61.1] always3(s27) || -> . % 76.16/76.37 178109[95:SSi:178108.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.37 178110[93:Spt:178109.0,177595.0,177596.0] || until2p7(s26)*+ -> . % 76.16/76.37 178111[93:Spt:178109.0,177595.1] || -> node4(s25)*. % 76.16/76.37 178113[93:MRR:843.0,178111.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.37 178116[93:Res:53.1,178113.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.37 178118[94:Spt:178116.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 178120[94:Res:178118.0,61.1] always3(s25) || -> . % 76.16/76.37 178121[94:SSi:178120.0,78178.0,78181.0,165517.0,177594.0,178111.0] || -> . % 76.16/76.37 178122[94:Spt:178121.0,178116.0,178118.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.37 178123[94:Spt:178121.0,178116.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 178127[94:Res:178123.0,61.1] always3(s26) || -> . % 76.16/76.37 178128[94:SSi:178127.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.37 178129[92:Spt:178128.0,177593.0,177594.0] || until2p7(s25)*+ -> . % 76.16/76.37 178130[92:Spt:178128.0,177593.1] || -> node4(s24)*. % 76.16/76.37 178132[92:MRR:846.0,178130.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.37 178135[92:Res:53.1,178132.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.37 178137[93:Spt:178135.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 178139[93:Res:178137.0,61.1] always3(s24) || -> . % 76.16/76.37 178140[93:SSi:178139.0,78173.0,78177.0,165516.0,177592.0,178130.0] || -> . % 76.16/76.37 178141[93:Spt:178140.0,178135.0,178137.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.37 178142[93:Spt:178140.0,178135.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 178146[93:Res:178142.0,61.1] always3(s25) || -> . % 76.16/76.37 178147[93:SSi:178146.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.37 178148[91:Spt:178147.0,177591.0,177592.0] || until2p7(s24)*+ -> . % 76.16/76.37 178149[91:Spt:178147.0,177591.1] || -> node4(s23)*. % 76.16/76.37 178151[91:MRR:849.0,178149.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.37 178154[91:Res:53.1,178151.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.37 178159[92:Spt:178154.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 178161[92:Res:178159.0,61.1] always3(s23) || -> . % 76.16/76.37 178162[92:SSi:178161.0,78169.0,78172.0,165515.0,177590.0,178149.0] || -> . % 76.16/76.37 178163[92:Spt:178162.0,178154.0,178159.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.37 178164[92:Spt:178162.0,178154.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 178168[92:Res:178164.0,61.1] always3(s24) || -> . % 76.16/76.37 178169[92:SSi:178168.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.37 178170[90:Spt:178169.0,177589.0,177590.0] || until2p7(s23)*+ -> . % 76.16/76.37 178171[90:Spt:178169.0,177589.1] || -> node4(s22)*. % 76.16/76.37 178173[90:MRR:852.0,178171.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.37 178176[90:Res:53.1,178173.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.37 178178[91:Spt:178176.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.37 178180[91:Res:178178.0,61.1] always3(s22) || -> . % 76.16/76.37 178181[91:SSi:178180.0,78164.0,78168.0,165514.0,177588.0,178171.0] || -> . % 76.16/76.37 178182[91:Spt:178181.0,178176.0,178178.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.37 178183[91:Spt:178181.0,178176.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 178187[91:Res:178183.0,61.1] always3(s23) || -> . % 76.16/76.37 178188[91:SSi:178187.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.37 178189[89:Spt:178188.0,177587.0,177588.0] || until2p7(s22)*+ -> . % 76.16/76.37 178190[89:Spt:178188.0,177587.1] || -> node4(s21)*. % 76.16/76.37 178192[89:MRR:855.0,178190.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.37 178195[89:Res:53.1,178192.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.37 178197[90:Spt:178195.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.37 178199[90:Res:178197.0,61.1] always3(s21) || -> . % 76.16/76.37 178200[90:SSi:178199.0,78160.0,78163.0,165513.0,177586.0,178190.0] || -> . % 76.16/76.37 178201[90:Spt:178200.0,178195.0,178197.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.37 178202[90:Spt:178200.0,178195.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.37 178206[90:Res:178202.0,61.1] always3(s22) || -> . % 76.16/76.37 178207[90:SSi:178206.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.37 178208[88:Spt:178207.0,177585.0,177586.0] || until2p7(s21)*+ -> . % 76.16/76.37 178209[88:Spt:178207.0,177585.1] || -> node4(s20)*. % 76.16/76.37 178211[88:MRR:858.0,178209.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.37 178214[88:Res:53.1,178211.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.37 178216[89:Spt:178214.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.37 178218[89:Res:178216.0,61.1] always3(s20) || -> . % 76.16/76.37 178219[89:SSi:178218.0,78155.0,78159.0,165512.0,177584.0,178209.0] || -> . % 76.16/76.37 178220[89:Spt:178219.0,178214.0,178216.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.37 178221[89:Spt:178219.0,178214.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.37 178225[89:Res:178221.0,61.1] always3(s21) || -> . % 76.16/76.37 178226[89:SSi:178225.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.37 178227[87:Spt:178226.0,177583.0,177584.0] || until2p7(s20)*+ -> . % 76.16/76.37 178228[87:Spt:178226.0,177583.1] || -> node4(s19)*. % 76.16/76.37 178230[87:MRR:861.0,178228.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.37 178233[87:Res:53.1,178230.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.37 178235[87:MRR:178233.0,177573.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.37 178240[87:Res:178235.0,61.1] always3(s20) || -> . % 76.16/76.37 178241[87:SSi:178240.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.37 178242[85:Spt:178241.0,177455.0,177458.0] || trans(s49,s19)*+ -> . % 76.16/76.37 178243[85:Spt:178241.0,177455.1,177455.2,177455.3,177455.4,177455.5,177455.6,177455.7,177455.8,177455.9,177455.10,177455.11,177455.12,177455.13,177455.14] || -> trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 178245[85:MRR:177457.1,178242.0] xuntil6(s49) || -> trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 178246[86:Spt:178243.0] || -> trans(s49,s18)*. % 76.16/76.37 178247[86:Res:178246.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s18)*. % 76.16/76.37 178249[86:Res:178246.0,60.0] || -> node2(s49,s18)*. % 76.16/76.37 178250[86:SSi:178247.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s18)*. % 76.16/76.37 178251[86:Res:178249.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)*. % 76.16/76.37 178354[86:SoR:178251.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)*. % 76.16/76.37 178356[86:SoR:178354.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)* xuntil6(s49). % 76.16/76.37 178357[86:SSi:178356.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s18,c_busy)* xuntil6(s49). % 76.16/76.37 178358[87:Spt:178357.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.37 178360[87:Res:178358.0,61.1] always3(s18) || -> . % 76.16/76.37 178361[87:SSi:178360.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.37 178362[87:Spt:178361.0,178357.1,178358.0] || m_main_v_state(s18,c_busy)*+ -> . % 76.16/76.37 178363[87:Spt:178361.0,178357.0,178357.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 178367[87:MRR:178354.2,178362.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 178368[87:Res:53.1,178363.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 178370[87:MRR:178368.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 178371[87:MRR:178250.0,178370.0] || -> until2p7(s18)*. % 76.16/76.37 178372[87:MRR:214.0,178371.0] || -> until2p7(s19)* node4(s18). % 76.16/76.37 178373[88:Spt:178372.0] || -> until2p7(s19)*. % 76.16/76.37 178374[88:MRR:215.0,178373.0] || -> until2p7(s20)* node4(s19). % 76.16/76.37 178375[89:Spt:178374.0] || -> until2p7(s20)*. % 76.16/76.37 178376[89:MRR:216.0,178375.0] || -> until2p7(s21)* node4(s20). % 76.16/76.37 178377[90:Spt:178376.0] || -> until2p7(s21)*. % 76.16/76.37 178378[90:MRR:217.0,178377.0] || -> until2p7(s22)* node4(s21). % 76.16/76.37 178379[91:Spt:178378.0] || -> until2p7(s22)*. % 76.16/76.37 178380[91:MRR:218.0,178379.0] || -> until2p7(s23)* node4(s22). % 76.16/76.37 178381[92:Spt:178380.0] || -> until2p7(s23)*. % 76.16/76.37 178382[92:MRR:219.0,178381.0] || -> until2p7(s24)* node4(s23). % 76.16/76.37 178383[93:Spt:178382.0] || -> until2p7(s24)*. % 76.16/76.37 178384[93:MRR:220.0,178383.0] || -> until2p7(s25)* node4(s24). % 76.16/76.37 178385[94:Spt:178384.0] || -> until2p7(s25)*. % 76.16/76.37 178386[94:MRR:221.0,178385.0] || -> until2p7(s26)* node4(s25). % 76.16/76.37 178387[95:Spt:178386.0] || -> until2p7(s26)*. % 76.16/76.37 178388[95:MRR:222.0,178387.0] || -> until2p7(s27)* node4(s26). % 76.16/76.37 178389[96:Spt:178388.0] || -> until2p7(s27)*. % 76.16/76.37 178390[96:MRR:223.0,178389.0] || -> until2p7(s28)* node4(s27). % 76.16/76.37 178391[97:Spt:178390.0] || -> until2p7(s28)*. % 76.16/76.37 178392[97:MRR:224.0,178391.0] || -> until2p7(s29)* node4(s28). % 76.16/76.37 178393[98:Spt:178392.0] || -> until2p7(s29)*. % 76.16/76.37 178394[98:MRR:225.0,178393.0] || -> until2p7(s30)* node4(s29). % 76.16/76.37 178395[99:Spt:178394.0] || -> until2p7(s30)*. % 76.16/76.37 178396[99:MRR:226.0,178395.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 178397[100:Spt:178396.0] || -> until2p7(s31)*. % 76.16/76.37 178398[100:MRR:227.0,178397.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 178399[101:Spt:178398.0] || -> until2p7(s32)*. % 76.16/76.37 178400[101:MRR:228.0,178399.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 178401[102:Spt:178400.0] || -> until2p7(s33)*. % 76.16/76.37 178402[102:MRR:229.0,178401.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 178403[103:Spt:178402.0] || -> until2p7(s34)*. % 76.16/76.37 178404[103:MRR:230.0,178403.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 178405[104:Spt:178404.0] || -> until2p7(s35)*. % 76.16/76.37 178406[104:MRR:231.0,178405.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 178407[105:Spt:178406.0] || -> until2p7(s36)*. % 76.16/76.37 178408[105:MRR:232.0,178407.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 178409[106:Spt:178408.0] || -> until2p7(s37)*. % 76.16/76.37 178410[106:MRR:235.0,178409.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 178411[107:Spt:178410.0] || -> until2p7(s38)*. % 76.16/76.37 178412[107:MRR:236.0,178411.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 178413[108:Spt:178412.0] || -> until2p7(s39)*. % 76.16/76.37 178414[108:MRR:237.0,178413.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 178415[109:Spt:178414.0] || -> until2p7(s40)*. % 76.16/76.37 178416[109:MRR:238.0,178415.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 178417[110:Spt:178416.0] || -> until2p7(s41)*. % 76.16/76.37 178418[110:MRR:239.0,178417.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 178419[111:Spt:178418.0] || -> until2p7(s42)*. % 76.16/76.37 178420[111:MRR:240.0,178419.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 178421[112:Spt:178420.0] || -> until2p7(s43)*. % 76.16/76.37 178422[112:MRR:241.0,178421.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 178423[113:Spt:178422.0] || -> until2p7(s44)*. % 76.16/76.37 178424[113:MRR:539.0,178423.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 178425[114:Spt:178424.0] || -> until2p7(s45)*. % 76.16/76.37 178426[114:MRR:544.0,178425.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 178427[115:Spt:178426.0] || -> until2p7(s46)*. % 76.16/76.37 178428[115:MRR:549.0,178427.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 178429[116:Spt:178428.0] || -> until2p7(s47)*. % 76.16/76.37 178430[116:MRR:554.0,178429.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 178431[117:Spt:178430.0] || -> until2p7(s48)*. % 76.16/76.37 178432[117:MRR:559.0,178431.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 178433[118:Spt:178432.0] || -> until2p7(s49)*. % 76.16/76.37 178434[118:MRR:194.0,178433.0] || -> node4(s49)*. % 76.16/76.37 178435[118:MRR:178367.0,178434.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 178439[118:Res:53.1,178435.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 178441[118:MRR:178439.0,78381.0] || -> . % 76.16/76.37 178442[118:Spt:178441.0,178432.0,178433.0] || until2p7(s49)*+ -> . % 76.16/76.37 178443[118:Spt:178441.0,178432.1] || -> node4(s48)*. % 76.16/76.37 178444[118:MRR:78384.0,178443.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 178447[118:Res:53.1,178444.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 178450[118:Res:178447.0,61.1] always3(s48) || -> . % 76.16/76.37 178451[118:SSi:178450.0,78281.0,78387.0,165540.0,178431.0,178443.0] || -> . % 76.16/76.37 178452[117:Spt:178451.0,178430.0,178431.0] || until2p7(s48)*+ -> . % 76.16/76.37 178453[117:Spt:178451.0,178430.1] || -> node4(s47)*. % 76.16/76.37 178455[117:MRR:777.0,178453.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 178467[117:Res:53.1,178455.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 178469[118:Spt:178467.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 178471[118:Res:178469.0,61.1] always3(s47) || -> . % 76.16/76.37 178472[118:SSi:178471.0,78277.0,78280.0,165539.0,178429.0,178453.0] || -> . % 76.16/76.37 178473[118:Spt:178472.0,178467.0,178469.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 178474[118:Spt:178472.0,178467.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 178478[118:Res:178474.0,61.1] always3(s48) || -> . % 76.16/76.37 178479[118:SSi:178478.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 178480[116:Spt:178479.0,178428.0,178429.0] || until2p7(s47)*+ -> . % 76.16/76.37 178481[116:Spt:178479.0,178428.1] || -> node4(s46)*. % 76.16/76.37 178483[116:MRR:780.0,178481.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 178490[116:Res:53.1,178483.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 178495[117:Spt:178490.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 178497[117:Res:178495.0,61.1] always3(s46) || -> . % 76.16/76.37 178498[117:SSi:178497.0,78272.0,78276.0,165538.0,178427.0,178481.0] || -> . % 76.16/76.37 178499[117:Spt:178498.0,178490.0,178495.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 178500[117:Spt:178498.0,178490.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 178504[117:Res:178500.0,61.1] always3(s47) || -> . % 76.16/76.37 178505[117:SSi:178504.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 178506[115:Spt:178505.0,178426.0,178427.0] || until2p7(s46)*+ -> . % 76.16/76.37 178507[115:Spt:178505.0,178426.1] || -> node4(s45)*. % 76.16/76.37 178509[115:MRR:783.0,178507.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 178512[115:Res:53.1,178509.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 178514[116:Spt:178512.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 178516[116:Res:178514.0,61.1] always3(s45) || -> . % 76.16/76.37 178517[116:SSi:178516.0,78268.0,78271.0,165537.0,178425.0,178507.0] || -> . % 76.16/76.37 178518[116:Spt:178517.0,178512.0,178514.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 178519[116:Spt:178517.0,178512.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 178523[116:Res:178519.0,61.1] always3(s46) || -> . % 76.16/76.37 178524[116:SSi:178523.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 178525[114:Spt:178524.0,178424.0,178425.0] || until2p7(s45)*+ -> . % 76.16/76.37 178526[114:Spt:178524.0,178424.1] || -> node4(s44)*. % 76.16/76.37 178528[114:MRR:786.0,178526.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 178531[114:Res:53.1,178528.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 178533[115:Spt:178531.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 178535[115:Res:178533.0,61.1] always3(s44) || -> . % 76.16/76.37 178536[115:SSi:178535.0,78263.0,78267.0,165536.0,178423.0,178526.0] || -> . % 76.16/76.37 178537[115:Spt:178536.0,178531.0,178533.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 178538[115:Spt:178536.0,178531.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 178542[115:Res:178538.0,61.1] always3(s45) || -> . % 76.16/76.37 178543[115:SSi:178542.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 178544[113:Spt:178543.0,178422.0,178423.0] || until2p7(s44)*+ -> . % 76.16/76.37 178545[113:Spt:178543.0,178422.1] || -> node4(s43)*. % 76.16/76.37 178547[113:MRR:789.0,178545.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 178550[113:Res:53.1,178547.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 178552[114:Spt:178550.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 178554[114:Res:178552.0,61.1] always3(s43) || -> . % 76.16/76.37 178555[114:SSi:178554.0,78259.0,78262.0,165535.0,178421.0,178545.0] || -> . % 76.16/76.37 178556[114:Spt:178555.0,178550.0,178552.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 178557[114:Spt:178555.0,178550.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 178561[114:Res:178557.0,61.1] always3(s44) || -> . % 76.16/76.37 178562[114:SSi:178561.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 178563[112:Spt:178562.0,178420.0,178421.0] || until2p7(s43)*+ -> . % 76.16/76.37 178564[112:Spt:178562.0,178420.1] || -> node4(s42)*. % 76.16/76.37 178566[112:MRR:792.0,178564.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 178569[112:Res:53.1,178566.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 178574[113:Spt:178569.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 178576[113:Res:178574.0,61.1] always3(s42) || -> . % 76.16/76.37 178577[113:SSi:178576.0,78254.0,78258.0,165534.0,178419.0,178564.0] || -> . % 76.16/76.37 178578[113:Spt:178577.0,178569.0,178574.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 178579[113:Spt:178577.0,178569.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 178583[113:Res:178579.0,61.1] always3(s43) || -> . % 76.16/76.37 178584[113:SSi:178583.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 178585[111:Spt:178584.0,178418.0,178419.0] || until2p7(s42)*+ -> . % 76.16/76.37 178586[111:Spt:178584.0,178418.1] || -> node4(s41)*. % 76.16/76.37 178588[111:MRR:795.0,178586.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 178591[111:Res:53.1,178588.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 178593[112:Spt:178591.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 178595[112:Res:178593.0,61.1] always3(s41) || -> . % 76.16/76.37 178596[112:SSi:178595.0,78250.0,78253.0,165533.0,178417.0,178586.0] || -> . % 76.16/76.37 178597[112:Spt:178596.0,178591.0,178593.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 178598[112:Spt:178596.0,178591.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 178602[112:Res:178598.0,61.1] always3(s42) || -> . % 76.16/76.37 178603[112:SSi:178602.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 178604[110:Spt:178603.0,178416.0,178417.0] || until2p7(s41)*+ -> . % 76.16/76.37 178605[110:Spt:178603.0,178416.1] || -> node4(s40)*. % 76.16/76.37 178607[110:MRR:798.0,178605.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 178610[110:Res:53.1,178607.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 178612[111:Spt:178610.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 178614[111:Res:178612.0,61.1] always3(s40) || -> . % 76.16/76.37 178615[111:SSi:178614.0,78245.0,78249.0,165532.0,178415.0,178605.0] || -> . % 76.16/76.37 178616[111:Spt:178615.0,178610.0,178612.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 178617[111:Spt:178615.0,178610.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 178621[111:Res:178617.0,61.1] always3(s41) || -> . % 76.16/76.37 178622[111:SSi:178621.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 178623[109:Spt:178622.0,178414.0,178415.0] || until2p7(s40)*+ -> . % 76.16/76.37 178624[109:Spt:178622.0,178414.1] || -> node4(s39)*. % 76.16/76.37 178626[109:MRR:801.0,178624.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 178629[109:Res:53.1,178626.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 178631[110:Spt:178629.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 178633[110:Res:178631.0,61.1] always3(s39) || -> . % 76.16/76.37 178634[110:SSi:178633.0,78241.0,78244.0,165531.0,178413.0,178624.0] || -> . % 76.16/76.37 178635[110:Spt:178634.0,178629.0,178631.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 178636[110:Spt:178634.0,178629.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 178640[110:Res:178636.0,61.1] always3(s40) || -> . % 76.16/76.37 178641[110:SSi:178640.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 178642[108:Spt:178641.0,178412.0,178413.0] || until2p7(s39)*+ -> . % 76.16/76.37 178643[108:Spt:178641.0,178412.1] || -> node4(s38)*. % 76.16/76.37 178645[108:MRR:804.0,178643.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 178648[108:Res:53.1,178645.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 178653[109:Spt:178648.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 178655[109:Res:178653.0,61.1] always3(s38) || -> . % 76.16/76.37 178656[109:SSi:178655.0,78236.0,78240.0,165530.0,178411.0,178643.0] || -> . % 76.16/76.37 178657[109:Spt:178656.0,178648.0,178653.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 178658[109:Spt:178656.0,178648.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 178662[109:Res:178658.0,61.1] always3(s39) || -> . % 76.16/76.37 178663[109:SSi:178662.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 178664[107:Spt:178663.0,178410.0,178411.0] || until2p7(s38)*+ -> . % 76.16/76.37 178665[107:Spt:178663.0,178410.1] || -> node4(s37)*. % 76.16/76.37 178667[107:MRR:807.0,178665.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 178670[107:Res:53.1,178667.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 178672[108:Spt:178670.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 178674[108:Res:178672.0,61.1] always3(s37) || -> . % 76.16/76.37 178675[108:SSi:178674.0,78232.0,78235.0,165529.0,178409.0,178665.0] || -> . % 76.16/76.37 178676[108:Spt:178675.0,178670.0,178672.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 178677[108:Spt:178675.0,178670.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 178681[108:Res:178677.0,61.1] always3(s38) || -> . % 76.16/76.37 178682[108:SSi:178681.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 178683[106:Spt:178682.0,178408.0,178409.0] || until2p7(s37)*+ -> . % 76.16/76.37 178684[106:Spt:178682.0,178408.1] || -> node4(s36)*. % 76.16/76.37 178686[106:MRR:810.0,178684.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 178689[106:Res:53.1,178686.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 178691[107:Spt:178689.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 178693[107:Res:178691.0,61.1] always3(s36) || -> . % 76.16/76.37 178694[107:SSi:178693.0,78227.0,78231.0,165528.0,178407.0,178684.0] || -> . % 76.16/76.37 178695[107:Spt:178694.0,178689.0,178691.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 178696[107:Spt:178694.0,178689.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 178700[107:Res:178696.0,61.1] always3(s37) || -> . % 76.16/76.37 178701[107:SSi:178700.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 178702[105:Spt:178701.0,178406.0,178407.0] || until2p7(s36)*+ -> . % 76.16/76.37 178703[105:Spt:178701.0,178406.1] || -> node4(s35)*. % 76.16/76.37 178705[105:MRR:813.0,178703.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 178708[105:Res:53.1,178705.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 178710[106:Spt:178708.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 178712[106:Res:178710.0,61.1] always3(s35) || -> . % 76.16/76.37 178713[106:SSi:178712.0,78223.0,78226.0,165527.0,178405.0,178703.0] || -> . % 76.16/76.37 178714[106:Spt:178713.0,178708.0,178710.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 178715[106:Spt:178713.0,178708.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 178719[106:Res:178715.0,61.1] always3(s36) || -> . % 76.16/76.37 178720[106:SSi:178719.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 178721[104:Spt:178720.0,178404.0,178405.0] || until2p7(s35)*+ -> . % 76.16/76.37 178722[104:Spt:178720.0,178404.1] || -> node4(s34)*. % 76.16/76.37 178724[104:MRR:816.0,178722.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 178727[104:Res:53.1,178724.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 178732[105:Spt:178727.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 178734[105:Res:178732.0,61.1] always3(s34) || -> . % 76.16/76.37 178735[105:SSi:178734.0,78218.0,78222.0,165526.0,178403.0,178722.0] || -> . % 76.16/76.37 178736[105:Spt:178735.0,178727.0,178732.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 178737[105:Spt:178735.0,178727.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 178741[105:Res:178737.0,61.1] always3(s35) || -> . % 76.16/76.37 178742[105:SSi:178741.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 178743[103:Spt:178742.0,178402.0,178403.0] || until2p7(s34)*+ -> . % 76.16/76.37 178744[103:Spt:178742.0,178402.1] || -> node4(s33)*. % 76.16/76.37 178746[103:MRR:819.0,178744.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 178749[103:Res:53.1,178746.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 178751[104:Spt:178749.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 178753[104:Res:178751.0,61.1] always3(s33) || -> . % 76.16/76.37 178754[104:SSi:178753.0,78214.0,78217.0,165525.0,178401.0,178744.0] || -> . % 76.16/76.37 178755[104:Spt:178754.0,178749.0,178751.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 178756[104:Spt:178754.0,178749.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 178760[104:Res:178756.0,61.1] always3(s34) || -> . % 76.16/76.37 178761[104:SSi:178760.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 178762[102:Spt:178761.0,178400.0,178401.0] || until2p7(s33)*+ -> . % 76.16/76.37 178763[102:Spt:178761.0,178400.1] || -> node4(s32)*. % 76.16/76.37 178765[102:MRR:822.0,178763.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 178768[102:Res:53.1,178765.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 178770[103:Spt:178768.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 178772[103:Res:178770.0,61.1] always3(s32) || -> . % 76.16/76.37 178773[103:SSi:178772.0,78209.0,78213.0,165524.0,178399.0,178763.0] || -> . % 76.16/76.37 178774[103:Spt:178773.0,178768.0,178770.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 178775[103:Spt:178773.0,178768.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 178779[103:Res:178775.0,61.1] always3(s33) || -> . % 76.16/76.37 178780[103:SSi:178779.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 178781[101:Spt:178780.0,178398.0,178399.0] || until2p7(s32)*+ -> . % 76.16/76.37 178782[101:Spt:178780.0,178398.1] || -> node4(s31)*. % 76.16/76.37 178784[101:MRR:825.0,178782.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 178787[101:Res:53.1,178784.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 178789[102:Spt:178787.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 178791[102:Res:178789.0,61.1] always3(s31) || -> . % 76.16/76.37 178792[102:SSi:178791.0,78205.0,78208.0,165523.0,178397.0,178782.0] || -> . % 76.16/76.37 178793[102:Spt:178792.0,178787.0,178789.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 178794[102:Spt:178792.0,178787.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 178798[102:Res:178794.0,61.1] always3(s32) || -> . % 76.16/76.37 178799[102:SSi:178798.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 178800[100:Spt:178799.0,178396.0,178397.0] || until2p7(s31)*+ -> . % 76.16/76.37 178801[100:Spt:178799.0,178396.1] || -> node4(s30)*. % 76.16/76.37 178803[100:MRR:828.0,178801.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 178806[100:Res:53.1,178803.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 178811[101:Spt:178806.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 178813[101:Res:178811.0,61.1] always3(s30) || -> . % 76.16/76.37 178814[101:SSi:178813.0,78200.0,78204.0,165522.0,178395.0,178801.0] || -> . % 76.16/76.37 178815[101:Spt:178814.0,178806.0,178811.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.37 178816[101:Spt:178814.0,178806.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 178820[101:Res:178816.0,61.1] always3(s31) || -> . % 76.16/76.37 178821[101:SSi:178820.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 178822[99:Spt:178821.0,178394.0,178395.0] || until2p7(s30)*+ -> . % 76.16/76.37 178823[99:Spt:178821.0,178394.1] || -> node4(s29)*. % 76.16/76.37 178825[99:MRR:831.0,178823.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.37 178828[99:Res:53.1,178825.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.37 178830[100:Spt:178828.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 178832[100:Res:178830.0,61.1] always3(s29) || -> . % 76.16/76.37 178833[100:SSi:178832.0,78196.0,78199.0,165521.0,178393.0,178823.0] || -> . % 76.16/76.37 178834[100:Spt:178833.0,178828.0,178830.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.37 178835[100:Spt:178833.0,178828.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 178839[100:Res:178835.0,61.1] always3(s30) || -> . % 76.16/76.37 178840[100:SSi:178839.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 178841[98:Spt:178840.0,178392.0,178393.0] || until2p7(s29)*+ -> . % 76.16/76.37 178842[98:Spt:178840.0,178392.1] || -> node4(s28)*. % 76.16/76.37 178844[98:MRR:834.0,178842.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.37 178847[98:Res:53.1,178844.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.37 178849[99:Spt:178847.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 178851[99:Res:178849.0,61.1] always3(s28) || -> . % 76.16/76.37 178852[99:SSi:178851.0,78191.0,78195.0,165520.0,178391.0,178842.0] || -> . % 76.16/76.37 178853[99:Spt:178852.0,178847.0,178849.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.37 178854[99:Spt:178852.0,178847.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 178858[99:Res:178854.0,61.1] always3(s29) || -> . % 76.16/76.37 178859[99:SSi:178858.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.37 178860[97:Spt:178859.0,178390.0,178391.0] || until2p7(s28)*+ -> . % 76.16/76.37 178861[97:Spt:178859.0,178390.1] || -> node4(s27)*. % 76.16/76.37 178863[97:MRR:837.0,178861.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.37 178866[97:Res:53.1,178863.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.37 178868[98:Spt:178866.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 178870[98:Res:178868.0,61.1] always3(s27) || -> . % 76.16/76.37 178871[98:SSi:178870.0,78187.0,78190.0,165519.0,178389.0,178861.0] || -> . % 76.16/76.37 178872[98:Spt:178871.0,178866.0,178868.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.37 178873[98:Spt:178871.0,178866.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 178877[98:Res:178873.0,61.1] always3(s28) || -> . % 76.16/76.37 178878[98:SSi:178877.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.37 178879[96:Spt:178878.0,178388.0,178389.0] || until2p7(s27)*+ -> . % 76.16/76.37 178880[96:Spt:178878.0,178388.1] || -> node4(s26)*. % 76.16/76.37 178882[96:MRR:840.0,178880.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.37 178885[96:Res:53.1,178882.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.37 178890[97:Spt:178885.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 178892[97:Res:178890.0,61.1] always3(s26) || -> . % 76.16/76.37 178893[97:SSi:178892.0,78182.0,78186.0,165518.0,178387.0,178880.0] || -> . % 76.16/76.37 178894[97:Spt:178893.0,178885.0,178890.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.37 178895[97:Spt:178893.0,178885.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 178899[97:Res:178895.0,61.1] always3(s27) || -> . % 76.16/76.37 178900[97:SSi:178899.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.37 178901[95:Spt:178900.0,178386.0,178387.0] || until2p7(s26)*+ -> . % 76.16/76.37 178902[95:Spt:178900.0,178386.1] || -> node4(s25)*. % 76.16/76.37 178904[95:MRR:843.0,178902.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.37 178907[95:Res:53.1,178904.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.37 178909[96:Spt:178907.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 178911[96:Res:178909.0,61.1] always3(s25) || -> . % 76.16/76.37 178912[96:SSi:178911.0,78178.0,78181.0,165517.0,178385.0,178902.0] || -> . % 76.16/76.37 178913[96:Spt:178912.0,178907.0,178909.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.37 178914[96:Spt:178912.0,178907.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 178918[96:Res:178914.0,61.1] always3(s26) || -> . % 76.16/76.37 178919[96:SSi:178918.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.37 178920[94:Spt:178919.0,178384.0,178385.0] || until2p7(s25)*+ -> . % 76.16/76.37 178921[94:Spt:178919.0,178384.1] || -> node4(s24)*. % 76.16/76.37 178923[94:MRR:846.0,178921.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.37 178926[94:Res:53.1,178923.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.37 178928[95:Spt:178926.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 178930[95:Res:178928.0,61.1] always3(s24) || -> . % 76.16/76.37 178931[95:SSi:178930.0,78173.0,78177.0,165516.0,178383.0,178921.0] || -> . % 76.16/76.37 178932[95:Spt:178931.0,178926.0,178928.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.37 178933[95:Spt:178931.0,178926.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 178937[95:Res:178933.0,61.1] always3(s25) || -> . % 76.16/76.37 178938[95:SSi:178937.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.37 178939[93:Spt:178938.0,178382.0,178383.0] || until2p7(s24)*+ -> . % 76.16/76.37 178940[93:Spt:178938.0,178382.1] || -> node4(s23)*. % 76.16/76.37 178942[93:MRR:849.0,178940.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.37 178945[93:Res:53.1,178942.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.37 178947[94:Spt:178945.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 178949[94:Res:178947.0,61.1] always3(s23) || -> . % 76.16/76.37 178950[94:SSi:178949.0,78169.0,78172.0,165515.0,178381.0,178940.0] || -> . % 76.16/76.37 178951[94:Spt:178950.0,178945.0,178947.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.37 178952[94:Spt:178950.0,178945.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 178956[94:Res:178952.0,61.1] always3(s24) || -> . % 76.16/76.37 178957[94:SSi:178956.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.37 178958[92:Spt:178957.0,178380.0,178381.0] || until2p7(s23)*+ -> . % 76.16/76.37 178959[92:Spt:178957.0,178380.1] || -> node4(s22)*. % 76.16/76.37 178961[92:MRR:852.0,178959.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.37 178964[92:Res:53.1,178961.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.37 178969[93:Spt:178964.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.37 178971[93:Res:178969.0,61.1] always3(s22) || -> . % 76.16/76.37 178972[93:SSi:178971.0,78164.0,78168.0,165514.0,178379.0,178959.0] || -> . % 76.16/76.37 178973[93:Spt:178972.0,178964.0,178969.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.37 178974[93:Spt:178972.0,178964.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 178978[93:Res:178974.0,61.1] always3(s23) || -> . % 76.16/76.37 178979[93:SSi:178978.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.37 178980[91:Spt:178979.0,178378.0,178379.0] || until2p7(s22)*+ -> . % 76.16/76.37 178981[91:Spt:178979.0,178378.1] || -> node4(s21)*. % 76.16/76.37 178983[91:MRR:855.0,178981.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.37 178986[91:Res:53.1,178983.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.37 178988[92:Spt:178986.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.37 178990[92:Res:178988.0,61.1] always3(s21) || -> . % 76.16/76.37 178991[92:SSi:178990.0,78160.0,78163.0,165513.0,178377.0,178981.0] || -> . % 76.16/76.37 178992[92:Spt:178991.0,178986.0,178988.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.37 178993[92:Spt:178991.0,178986.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.37 178997[92:Res:178993.0,61.1] always3(s22) || -> . % 76.16/76.37 178998[92:SSi:178997.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.37 178999[90:Spt:178998.0,178376.0,178377.0] || until2p7(s21)*+ -> . % 76.16/76.37 179000[90:Spt:178998.0,178376.1] || -> node4(s20)*. % 76.16/76.37 179002[90:MRR:858.0,179000.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.37 179005[90:Res:53.1,179002.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.37 179007[91:Spt:179005.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.37 179009[91:Res:179007.0,61.1] always3(s20) || -> . % 76.16/76.37 179010[91:SSi:179009.0,78155.0,78159.0,165512.0,178375.0,179000.0] || -> . % 76.16/76.37 179011[91:Spt:179010.0,179005.0,179007.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.37 179012[91:Spt:179010.0,179005.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.37 179016[91:Res:179012.0,61.1] always3(s21) || -> . % 76.16/76.37 179017[91:SSi:179016.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.37 179018[89:Spt:179017.0,178374.0,178375.0] || until2p7(s20)*+ -> . % 76.16/76.37 179019[89:Spt:179017.0,178374.1] || -> node4(s19)*. % 76.16/76.37 179021[89:MRR:861.0,179019.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.37 179024[89:Res:53.1,179021.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.37 179026[90:Spt:179024.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.37 179028[90:Res:179026.0,61.1] always3(s19) || -> . % 76.16/76.37 179029[90:SSi:179028.0,78151.0,78154.0,165511.0,178373.0,179019.0] || -> . % 76.16/76.37 179030[90:Spt:179029.0,179024.0,179026.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.37 179031[90:Spt:179029.0,179024.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.37 179035[90:Res:179031.0,61.1] always3(s20) || -> . % 76.16/76.37 179036[90:SSi:179035.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.37 179037[88:Spt:179036.0,178372.0,178373.0] || until2p7(s19)*+ -> . % 76.16/76.37 179038[88:Spt:179036.0,178372.1] || -> node4(s18)*. % 76.16/76.37 179040[88:MRR:864.0,179038.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.37 179043[88:Res:53.1,179040.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.37 179045[88:MRR:179043.0,178362.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.37 179050[88:Res:179045.0,61.1] always3(s19) || -> . % 76.16/76.37 179051[88:SSi:179050.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.37 179052[86:Spt:179051.0,178243.0,178246.0] || trans(s49,s18)*+ -> . % 76.16/76.37 179053[86:Spt:179051.0,178243.1,178243.2,178243.3,178243.4,178243.5,178243.6,178243.7,178243.8,178243.9,178243.10,178243.11,178243.12,178243.13] || -> trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.37 179055[86:MRR:178245.1,179052.0] xuntil6(s49) || -> trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.37 179056[87:Spt:179053.0] || -> trans(s49,s17)*. % 76.16/76.37 179057[87:Res:179056.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s17)*. % 76.16/76.37 179059[87:Res:179056.0,60.0] || -> node2(s49,s17)*. % 76.16/76.37 179060[87:SSi:179057.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s17)*. % 76.16/76.37 179061[87:Res:179059.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)*. % 76.16/76.37 179168[87:SoR:179061.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)*. % 76.16/76.37 179170[87:SoR:179168.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)* xuntil6(s49). % 76.16/76.37 179171[87:SSi:179170.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s17,c_busy)* xuntil6(s49). % 76.16/76.37 179172[88:Spt:179171.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.37 179174[88:Res:179172.0,61.1] always3(s17) || -> . % 76.16/76.37 179175[88:SSi:179174.0,78142.0,78145.0,165509.0] || -> . % 76.16/76.37 179176[88:Spt:179175.0,179171.1,179172.0] || m_main_v_state(s17,c_busy)*+ -> . % 76.16/76.37 179177[88:Spt:179175.0,179171.0,179171.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.37 179181[88:MRR:179168.2,179176.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.37 179182[88:Res:53.1,179177.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.37 179184[88:MRR:179182.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.37 179185[88:MRR:179060.0,179184.0] || -> until2p7(s17)*. % 76.16/76.37 179186[88:MRR:213.0,179185.0] || -> until2p7(s18)* node4(s17). % 76.16/76.37 179187[89:Spt:179186.0] || -> until2p7(s18)*. % 76.16/76.37 179188[89:MRR:214.0,179187.0] || -> until2p7(s19)* node4(s18). % 76.16/76.37 179189[90:Spt:179188.0] || -> until2p7(s19)*. % 76.16/76.37 179190[90:MRR:215.0,179189.0] || -> until2p7(s20)* node4(s19). % 76.16/76.37 179191[91:Spt:179190.0] || -> until2p7(s20)*. % 76.16/76.37 179192[91:MRR:216.0,179191.0] || -> until2p7(s21)* node4(s20). % 76.16/76.37 179193[92:Spt:179192.0] || -> until2p7(s21)*. % 76.16/76.37 179194[92:MRR:217.0,179193.0] || -> until2p7(s22)* node4(s21). % 76.16/76.37 179195[93:Spt:179194.0] || -> until2p7(s22)*. % 76.16/76.37 179196[93:MRR:218.0,179195.0] || -> until2p7(s23)* node4(s22). % 76.16/76.37 179197[94:Spt:179196.0] || -> until2p7(s23)*. % 76.16/76.37 179198[94:MRR:219.0,179197.0] || -> until2p7(s24)* node4(s23). % 76.16/76.37 179199[95:Spt:179198.0] || -> until2p7(s24)*. % 76.16/76.37 179200[95:MRR:220.0,179199.0] || -> until2p7(s25)* node4(s24). % 76.16/76.37 179201[96:Spt:179200.0] || -> until2p7(s25)*. % 76.16/76.37 179202[96:MRR:221.0,179201.0] || -> until2p7(s26)* node4(s25). % 76.16/76.37 179203[97:Spt:179202.0] || -> until2p7(s26)*. % 76.16/76.37 179204[97:MRR:222.0,179203.0] || -> until2p7(s27)* node4(s26). % 76.16/76.37 179205[98:Spt:179204.0] || -> until2p7(s27)*. % 76.16/76.37 179206[98:MRR:223.0,179205.0] || -> until2p7(s28)* node4(s27). % 76.16/76.37 179207[99:Spt:179206.0] || -> until2p7(s28)*. % 76.16/76.37 179208[99:MRR:224.0,179207.0] || -> until2p7(s29)* node4(s28). % 76.16/76.37 179209[100:Spt:179208.0] || -> until2p7(s29)*. % 76.16/76.37 179210[100:MRR:225.0,179209.0] || -> until2p7(s30)* node4(s29). % 76.16/76.37 179211[101:Spt:179210.0] || -> until2p7(s30)*. % 76.16/76.37 179212[101:MRR:226.0,179211.0] || -> until2p7(s31)* node4(s30). % 76.16/76.37 179213[102:Spt:179212.0] || -> until2p7(s31)*. % 76.16/76.37 179214[102:MRR:227.0,179213.0] || -> until2p7(s32)* node4(s31). % 76.16/76.37 179215[103:Spt:179214.0] || -> until2p7(s32)*. % 76.16/76.37 179216[103:MRR:228.0,179215.0] || -> until2p7(s33)* node4(s32). % 76.16/76.37 179217[104:Spt:179216.0] || -> until2p7(s33)*. % 76.16/76.37 179218[104:MRR:229.0,179217.0] || -> until2p7(s34)* node4(s33). % 76.16/76.37 179219[105:Spt:179218.0] || -> until2p7(s34)*. % 76.16/76.37 179220[105:MRR:230.0,179219.0] || -> until2p7(s35)* node4(s34). % 76.16/76.37 179221[106:Spt:179220.0] || -> until2p7(s35)*. % 76.16/76.37 179222[106:MRR:231.0,179221.0] || -> until2p7(s36)* node4(s35). % 76.16/76.37 179223[107:Spt:179222.0] || -> until2p7(s36)*. % 76.16/76.37 179224[107:MRR:232.0,179223.0] || -> until2p7(s37)* node4(s36). % 76.16/76.37 179225[108:Spt:179224.0] || -> until2p7(s37)*. % 76.16/76.37 179226[108:MRR:235.0,179225.0] || -> until2p7(s38)* node4(s37). % 76.16/76.37 179227[109:Spt:179226.0] || -> until2p7(s38)*. % 76.16/76.37 179228[109:MRR:236.0,179227.0] || -> until2p7(s39)* node4(s38). % 76.16/76.37 179229[110:Spt:179228.0] || -> until2p7(s39)*. % 76.16/76.37 179230[110:MRR:237.0,179229.0] || -> until2p7(s40)* node4(s39). % 76.16/76.37 179231[111:Spt:179230.0] || -> until2p7(s40)*. % 76.16/76.37 179232[111:MRR:238.0,179231.0] || -> until2p7(s41)* node4(s40). % 76.16/76.37 179233[112:Spt:179232.0] || -> until2p7(s41)*. % 76.16/76.37 179234[112:MRR:239.0,179233.0] || -> until2p7(s42)* node4(s41). % 76.16/76.37 179235[113:Spt:179234.0] || -> until2p7(s42)*. % 76.16/76.37 179236[113:MRR:240.0,179235.0] || -> until2p7(s43)* node4(s42). % 76.16/76.37 179237[114:Spt:179236.0] || -> until2p7(s43)*. % 76.16/76.37 179238[114:MRR:241.0,179237.0] || -> until2p7(s44)* node4(s43). % 76.16/76.37 179239[115:Spt:179238.0] || -> until2p7(s44)*. % 76.16/76.37 179240[115:MRR:539.0,179239.0] || -> until2p7(s45)* node4(s44). % 76.16/76.37 179241[116:Spt:179240.0] || -> until2p7(s45)*. % 76.16/76.37 179242[116:MRR:544.0,179241.0] || -> until2p7(s46)* node4(s45). % 76.16/76.37 179243[117:Spt:179242.0] || -> until2p7(s46)*. % 76.16/76.37 179244[117:MRR:549.0,179243.0] || -> until2p7(s47)* node4(s46). % 76.16/76.37 179245[118:Spt:179244.0] || -> until2p7(s47)*. % 76.16/76.37 179246[118:MRR:554.0,179245.0] || -> until2p7(s48)* node4(s47). % 76.16/76.37 179247[119:Spt:179246.0] || -> until2p7(s48)*. % 76.16/76.37 179248[119:MRR:559.0,179247.0] || -> until2p7(s49)* node4(s48). % 76.16/76.37 179249[120:Spt:179248.0] || -> until2p7(s49)*. % 76.16/76.37 179250[120:MRR:194.0,179249.0] || -> node4(s49)*. % 76.16/76.37 179251[120:MRR:179181.0,179250.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.37 179252[120:Res:53.1,179251.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.37 179254[120:MRR:179252.0,78381.0] || -> . % 76.16/76.37 179255[120:Spt:179254.0,179248.0,179249.0] || until2p7(s49)*+ -> . % 76.16/76.37 179256[120:Spt:179254.0,179248.1] || -> node4(s48)*. % 76.16/76.37 179257[120:MRR:78384.0,179256.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.37 179260[120:Res:53.1,179257.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 179263[120:Res:179260.0,61.1] always3(s48) || -> . % 76.16/76.37 179264[120:SSi:179263.0,78281.0,78387.0,165540.0,179247.0,179256.0] || -> . % 76.16/76.37 179265[119:Spt:179264.0,179246.0,179247.0] || until2p7(s48)*+ -> . % 76.16/76.37 179266[119:Spt:179264.0,179246.1] || -> node4(s47)*. % 76.16/76.37 179268[119:MRR:777.0,179266.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.37 179283[119:Res:53.1,179268.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.37 179288[120:Spt:179283.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 179290[120:Res:179288.0,61.1] always3(s47) || -> . % 76.16/76.37 179291[120:SSi:179290.0,78277.0,78280.0,165539.0,179245.0,179266.0] || -> . % 76.16/76.37 179292[120:Spt:179291.0,179283.0,179288.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.37 179293[120:Spt:179291.0,179283.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.37 179297[120:Res:179293.0,61.1] always3(s48) || -> . % 76.16/76.37 179298[120:SSi:179297.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.37 179299[118:Spt:179298.0,179244.0,179245.0] || until2p7(s47)*+ -> . % 76.16/76.37 179300[118:Spt:179298.0,179244.1] || -> node4(s46)*. % 76.16/76.37 179302[118:MRR:780.0,179300.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.37 179309[118:Res:53.1,179302.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.37 179311[119:Spt:179309.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 179313[119:Res:179311.0,61.1] always3(s46) || -> . % 76.16/76.37 179314[119:SSi:179313.0,78272.0,78276.0,165538.0,179243.0,179300.0] || -> . % 76.16/76.37 179315[119:Spt:179314.0,179309.0,179311.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.37 179316[119:Spt:179314.0,179309.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.37 179320[119:Res:179316.0,61.1] always3(s47) || -> . % 76.16/76.37 179321[119:SSi:179320.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.37 179322[117:Spt:179321.0,179242.0,179243.0] || until2p7(s46)*+ -> . % 76.16/76.37 179323[117:Spt:179321.0,179242.1] || -> node4(s45)*. % 76.16/76.37 179325[117:MRR:783.0,179323.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.37 179328[117:Res:53.1,179325.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.37 179333[118:Spt:179328.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 179335[118:Res:179333.0,61.1] always3(s45) || -> . % 76.16/76.37 179336[118:SSi:179335.0,78268.0,78271.0,165537.0,179241.0,179323.0] || -> . % 76.16/76.37 179337[118:Spt:179336.0,179328.0,179333.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.37 179338[118:Spt:179336.0,179328.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.37 179342[118:Res:179338.0,61.1] always3(s46) || -> . % 76.16/76.37 179343[118:SSi:179342.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.37 179344[116:Spt:179343.0,179240.0,179241.0] || until2p7(s45)*+ -> . % 76.16/76.37 179345[116:Spt:179343.0,179240.1] || -> node4(s44)*. % 76.16/76.37 179347[116:MRR:786.0,179345.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.37 179350[116:Res:53.1,179347.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.37 179352[117:Spt:179350.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 179354[117:Res:179352.0,61.1] always3(s44) || -> . % 76.16/76.37 179355[117:SSi:179354.0,78263.0,78267.0,165536.0,179239.0,179345.0] || -> . % 76.16/76.37 179356[117:Spt:179355.0,179350.0,179352.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.37 179357[117:Spt:179355.0,179350.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.37 179361[117:Res:179357.0,61.1] always3(s45) || -> . % 76.16/76.37 179362[117:SSi:179361.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.37 179363[115:Spt:179362.0,179238.0,179239.0] || until2p7(s44)*+ -> . % 76.16/76.37 179364[115:Spt:179362.0,179238.1] || -> node4(s43)*. % 76.16/76.37 179366[115:MRR:789.0,179364.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.37 179369[115:Res:53.1,179366.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.37 179371[116:Spt:179369.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 179373[116:Res:179371.0,61.1] always3(s43) || -> . % 76.16/76.37 179374[116:SSi:179373.0,78259.0,78262.0,165535.0,179237.0,179364.0] || -> . % 76.16/76.37 179375[116:Spt:179374.0,179369.0,179371.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.37 179376[116:Spt:179374.0,179369.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.37 179380[116:Res:179376.0,61.1] always3(s44) || -> . % 76.16/76.37 179381[116:SSi:179380.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.37 179382[114:Spt:179381.0,179236.0,179237.0] || until2p7(s43)*+ -> . % 76.16/76.37 179383[114:Spt:179381.0,179236.1] || -> node4(s42)*. % 76.16/76.37 179385[114:MRR:792.0,179383.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.37 179388[114:Res:53.1,179385.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.37 179390[115:Spt:179388.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 179392[115:Res:179390.0,61.1] always3(s42) || -> . % 76.16/76.37 179393[115:SSi:179392.0,78254.0,78258.0,165534.0,179235.0,179383.0] || -> . % 76.16/76.37 179394[115:Spt:179393.0,179388.0,179390.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.37 179395[115:Spt:179393.0,179388.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.37 179399[115:Res:179395.0,61.1] always3(s43) || -> . % 76.16/76.37 179400[115:SSi:179399.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.37 179401[113:Spt:179400.0,179234.0,179235.0] || until2p7(s42)*+ -> . % 76.16/76.37 179402[113:Spt:179400.0,179234.1] || -> node4(s41)*. % 76.16/76.37 179404[113:MRR:795.0,179402.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.37 179407[113:Res:53.1,179404.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.37 179412[114:Spt:179407.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 179414[114:Res:179412.0,61.1] always3(s41) || -> . % 76.16/76.37 179415[114:SSi:179414.0,78250.0,78253.0,165533.0,179233.0,179402.0] || -> . % 76.16/76.37 179416[114:Spt:179415.0,179407.0,179412.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.37 179417[114:Spt:179415.0,179407.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.37 179421[114:Res:179417.0,61.1] always3(s42) || -> . % 76.16/76.37 179422[114:SSi:179421.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.37 179423[112:Spt:179422.0,179232.0,179233.0] || until2p7(s41)*+ -> . % 76.16/76.37 179424[112:Spt:179422.0,179232.1] || -> node4(s40)*. % 76.16/76.37 179426[112:MRR:798.0,179424.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.37 179429[112:Res:53.1,179426.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.37 179431[113:Spt:179429.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 179433[113:Res:179431.0,61.1] always3(s40) || -> . % 76.16/76.37 179434[113:SSi:179433.0,78245.0,78249.0,165532.0,179231.0,179424.0] || -> . % 76.16/76.37 179435[113:Spt:179434.0,179429.0,179431.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.37 179436[113:Spt:179434.0,179429.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.37 179440[113:Res:179436.0,61.1] always3(s41) || -> . % 76.16/76.37 179441[113:SSi:179440.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.37 179442[111:Spt:179441.0,179230.0,179231.0] || until2p7(s40)*+ -> . % 76.16/76.37 179443[111:Spt:179441.0,179230.1] || -> node4(s39)*. % 76.16/76.37 179445[111:MRR:801.0,179443.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.37 179448[111:Res:53.1,179445.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.37 179450[112:Spt:179448.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 179452[112:Res:179450.0,61.1] always3(s39) || -> . % 76.16/76.37 179453[112:SSi:179452.0,78241.0,78244.0,165531.0,179229.0,179443.0] || -> . % 76.16/76.37 179454[112:Spt:179453.0,179448.0,179450.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.37 179455[112:Spt:179453.0,179448.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.37 179459[112:Res:179455.0,61.1] always3(s40) || -> . % 76.16/76.37 179460[112:SSi:179459.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.37 179461[110:Spt:179460.0,179228.0,179229.0] || until2p7(s39)*+ -> . % 76.16/76.37 179462[110:Spt:179460.0,179228.1] || -> node4(s38)*. % 76.16/76.37 179464[110:MRR:804.0,179462.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.37 179467[110:Res:53.1,179464.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.37 179469[111:Spt:179467.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 179471[111:Res:179469.0,61.1] always3(s38) || -> . % 76.16/76.37 179472[111:SSi:179471.0,78236.0,78240.0,165530.0,179227.0,179462.0] || -> . % 76.16/76.37 179473[111:Spt:179472.0,179467.0,179469.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.37 179474[111:Spt:179472.0,179467.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.37 179478[111:Res:179474.0,61.1] always3(s39) || -> . % 76.16/76.37 179479[111:SSi:179478.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.37 179480[109:Spt:179479.0,179226.0,179227.0] || until2p7(s38)*+ -> . % 76.16/76.37 179481[109:Spt:179479.0,179226.1] || -> node4(s37)*. % 76.16/76.37 179483[109:MRR:807.0,179481.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.37 179486[109:Res:53.1,179483.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.37 179491[110:Spt:179486.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 179493[110:Res:179491.0,61.1] always3(s37) || -> . % 76.16/76.37 179494[110:SSi:179493.0,78232.0,78235.0,165529.0,179225.0,179481.0] || -> . % 76.16/76.37 179495[110:Spt:179494.0,179486.0,179491.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.37 179496[110:Spt:179494.0,179486.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.37 179500[110:Res:179496.0,61.1] always3(s38) || -> . % 76.16/76.37 179501[110:SSi:179500.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.37 179502[108:Spt:179501.0,179224.0,179225.0] || until2p7(s37)*+ -> . % 76.16/76.37 179503[108:Spt:179501.0,179224.1] || -> node4(s36)*. % 76.16/76.37 179505[108:MRR:810.0,179503.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.37 179508[108:Res:53.1,179505.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.37 179510[109:Spt:179508.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 179512[109:Res:179510.0,61.1] always3(s36) || -> . % 76.16/76.37 179513[109:SSi:179512.0,78227.0,78231.0,165528.0,179223.0,179503.0] || -> . % 76.16/76.37 179514[109:Spt:179513.0,179508.0,179510.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.37 179515[109:Spt:179513.0,179508.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.37 179519[109:Res:179515.0,61.1] always3(s37) || -> . % 76.16/76.37 179520[109:SSi:179519.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.37 179521[107:Spt:179520.0,179222.0,179223.0] || until2p7(s36)*+ -> . % 76.16/76.37 179522[107:Spt:179520.0,179222.1] || -> node4(s35)*. % 76.16/76.37 179524[107:MRR:813.0,179522.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.37 179527[107:Res:53.1,179524.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.37 179529[108:Spt:179527.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 179531[108:Res:179529.0,61.1] always3(s35) || -> . % 76.16/76.37 179532[108:SSi:179531.0,78223.0,78226.0,165527.0,179221.0,179522.0] || -> . % 76.16/76.37 179533[108:Spt:179532.0,179527.0,179529.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.37 179534[108:Spt:179532.0,179527.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.37 179538[108:Res:179534.0,61.1] always3(s36) || -> . % 76.16/76.37 179539[108:SSi:179538.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.37 179540[106:Spt:179539.0,179220.0,179221.0] || until2p7(s35)*+ -> . % 76.16/76.37 179541[106:Spt:179539.0,179220.1] || -> node4(s34)*. % 76.16/76.37 179543[106:MRR:816.0,179541.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.37 179546[106:Res:53.1,179543.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.37 179548[107:Spt:179546.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 179550[107:Res:179548.0,61.1] always3(s34) || -> . % 76.16/76.37 179551[107:SSi:179550.0,78218.0,78222.0,165526.0,179219.0,179541.0] || -> . % 76.16/76.37 179552[107:Spt:179551.0,179546.0,179548.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.37 179553[107:Spt:179551.0,179546.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.37 179557[107:Res:179553.0,61.1] always3(s35) || -> . % 76.16/76.37 179558[107:SSi:179557.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.37 179559[105:Spt:179558.0,179218.0,179219.0] || until2p7(s34)*+ -> . % 76.16/76.37 179560[105:Spt:179558.0,179218.1] || -> node4(s33)*. % 76.16/76.37 179562[105:MRR:819.0,179560.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.37 179565[105:Res:53.1,179562.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.37 179570[106:Spt:179565.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 179572[106:Res:179570.0,61.1] always3(s33) || -> . % 76.16/76.37 179573[106:SSi:179572.0,78214.0,78217.0,165525.0,179217.0,179560.0] || -> . % 76.16/76.37 179574[106:Spt:179573.0,179565.0,179570.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.37 179575[106:Spt:179573.0,179565.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.37 179579[106:Res:179575.0,61.1] always3(s34) || -> . % 76.16/76.37 179580[106:SSi:179579.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.37 179581[104:Spt:179580.0,179216.0,179217.0] || until2p7(s33)*+ -> . % 76.16/76.37 179582[104:Spt:179580.0,179216.1] || -> node4(s32)*. % 76.16/76.37 179584[104:MRR:822.0,179582.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.37 179587[104:Res:53.1,179584.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.37 179589[105:Spt:179587.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 179591[105:Res:179589.0,61.1] always3(s32) || -> . % 76.16/76.37 179592[105:SSi:179591.0,78209.0,78213.0,165524.0,179215.0,179582.0] || -> . % 76.16/76.37 179593[105:Spt:179592.0,179587.0,179589.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.37 179594[105:Spt:179592.0,179587.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.37 179598[105:Res:179594.0,61.1] always3(s33) || -> . % 76.16/76.37 179599[105:SSi:179598.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.37 179600[103:Spt:179599.0,179214.0,179215.0] || until2p7(s32)*+ -> . % 76.16/76.37 179601[103:Spt:179599.0,179214.1] || -> node4(s31)*. % 76.16/76.37 179603[103:MRR:825.0,179601.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.37 179606[103:Res:53.1,179603.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.37 179608[104:Spt:179606.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 179610[104:Res:179608.0,61.1] always3(s31) || -> . % 76.16/76.37 179611[104:SSi:179610.0,78205.0,78208.0,165523.0,179213.0,179601.0] || -> . % 76.16/76.37 179612[104:Spt:179611.0,179606.0,179608.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.37 179613[104:Spt:179611.0,179606.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.37 179617[104:Res:179613.0,61.1] always3(s32) || -> . % 76.16/76.37 179618[104:SSi:179617.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.37 179619[102:Spt:179618.0,179212.0,179213.0] || until2p7(s31)*+ -> . % 76.16/76.37 179620[102:Spt:179618.0,179212.1] || -> node4(s30)*. % 76.16/76.37 179622[102:MRR:828.0,179620.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.37 179625[102:Res:53.1,179622.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.37 179627[103:Spt:179625.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 179629[103:Res:179627.0,61.1] always3(s30) || -> . % 76.16/76.37 179630[103:SSi:179629.0,78200.0,78204.0,165522.0,179211.0,179620.0] || -> . % 76.16/76.37 179631[103:Spt:179630.0,179625.0,179627.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.37 179632[103:Spt:179630.0,179625.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.37 179636[103:Res:179632.0,61.1] always3(s31) || -> . % 76.16/76.37 179637[103:SSi:179636.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.37 179638[101:Spt:179637.0,179210.0,179211.0] || until2p7(s30)*+ -> . % 76.16/76.37 179639[101:Spt:179637.0,179210.1] || -> node4(s29)*. % 76.16/76.37 179641[101:MRR:831.0,179639.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.37 179644[101:Res:53.1,179641.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.37 179649[102:Spt:179644.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 179651[102:Res:179649.0,61.1] always3(s29) || -> . % 76.16/76.37 179652[102:SSi:179651.0,78196.0,78199.0,165521.0,179209.0,179639.0] || -> . % 76.16/76.37 179653[102:Spt:179652.0,179644.0,179649.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.37 179654[102:Spt:179652.0,179644.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.37 179658[102:Res:179654.0,61.1] always3(s30) || -> . % 76.16/76.37 179659[102:SSi:179658.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.37 179660[100:Spt:179659.0,179208.0,179209.0] || until2p7(s29)*+ -> . % 76.16/76.37 179661[100:Spt:179659.0,179208.1] || -> node4(s28)*. % 76.16/76.37 179663[100:MRR:834.0,179661.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.37 179666[100:Res:53.1,179663.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.37 179668[101:Spt:179666.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 179670[101:Res:179668.0,61.1] always3(s28) || -> . % 76.16/76.37 179671[101:SSi:179670.0,78191.0,78195.0,165520.0,179207.0,179661.0] || -> . % 76.16/76.37 179672[101:Spt:179671.0,179666.0,179668.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.37 179673[101:Spt:179671.0,179666.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.37 179677[101:Res:179673.0,61.1] always3(s29) || -> . % 76.16/76.37 179678[101:SSi:179677.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.37 179679[99:Spt:179678.0,179206.0,179207.0] || until2p7(s28)*+ -> . % 76.16/76.37 179680[99:Spt:179678.0,179206.1] || -> node4(s27)*. % 76.16/76.37 179682[99:MRR:837.0,179680.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.37 179685[99:Res:53.1,179682.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.37 179687[100:Spt:179685.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 179689[100:Res:179687.0,61.1] always3(s27) || -> . % 76.16/76.37 179690[100:SSi:179689.0,78187.0,78190.0,165519.0,179205.0,179680.0] || -> . % 76.16/76.37 179691[100:Spt:179690.0,179685.0,179687.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.37 179692[100:Spt:179690.0,179685.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.37 179696[100:Res:179692.0,61.1] always3(s28) || -> . % 76.16/76.37 179697[100:SSi:179696.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.37 179698[98:Spt:179697.0,179204.0,179205.0] || until2p7(s27)*+ -> . % 76.16/76.37 179699[98:Spt:179697.0,179204.1] || -> node4(s26)*. % 76.16/76.37 179701[98:MRR:840.0,179699.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.37 179704[98:Res:53.1,179701.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.37 179706[99:Spt:179704.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 179708[99:Res:179706.0,61.1] always3(s26) || -> . % 76.16/76.37 179709[99:SSi:179708.0,78182.0,78186.0,165518.0,179203.0,179699.0] || -> . % 76.16/76.37 179710[99:Spt:179709.0,179704.0,179706.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.37 179711[99:Spt:179709.0,179704.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.37 179715[99:Res:179711.0,61.1] always3(s27) || -> . % 76.16/76.37 179716[99:SSi:179715.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.37 179717[97:Spt:179716.0,179202.0,179203.0] || until2p7(s26)*+ -> . % 76.16/76.37 179718[97:Spt:179716.0,179202.1] || -> node4(s25)*. % 76.16/76.37 179720[97:MRR:843.0,179718.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.37 179723[97:Res:53.1,179720.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.37 179728[98:Spt:179723.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 179730[98:Res:179728.0,61.1] always3(s25) || -> . % 76.16/76.37 179731[98:SSi:179730.0,78178.0,78181.0,165517.0,179201.0,179718.0] || -> . % 76.16/76.37 179732[98:Spt:179731.0,179723.0,179728.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.37 179733[98:Spt:179731.0,179723.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.37 179737[98:Res:179733.0,61.1] always3(s26) || -> . % 76.16/76.37 179738[98:SSi:179737.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.37 179739[96:Spt:179738.0,179200.0,179201.0] || until2p7(s25)*+ -> . % 76.16/76.37 179740[96:Spt:179738.0,179200.1] || -> node4(s24)*. % 76.16/76.37 179742[96:MRR:846.0,179740.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.37 179745[96:Res:53.1,179742.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.37 179747[97:Spt:179745.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 179749[97:Res:179747.0,61.1] always3(s24) || -> . % 76.16/76.37 179750[97:SSi:179749.0,78173.0,78177.0,165516.0,179199.0,179740.0] || -> . % 76.16/76.37 179751[97:Spt:179750.0,179745.0,179747.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.37 179752[97:Spt:179750.0,179745.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.37 179756[97:Res:179752.0,61.1] always3(s25) || -> . % 76.16/76.37 179757[97:SSi:179756.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.37 179758[95:Spt:179757.0,179198.0,179199.0] || until2p7(s24)*+ -> . % 76.16/76.37 179759[95:Spt:179757.0,179198.1] || -> node4(s23)*. % 76.16/76.37 179761[95:MRR:849.0,179759.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.37 179764[95:Res:53.1,179761.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.37 179766[96:Spt:179764.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 179768[96:Res:179766.0,61.1] always3(s23) || -> . % 76.16/76.37 179769[96:SSi:179768.0,78169.0,78172.0,165515.0,179197.0,179759.0] || -> . % 76.16/76.37 179770[96:Spt:179769.0,179764.0,179766.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.37 179771[96:Spt:179769.0,179764.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.37 179775[96:Res:179771.0,61.1] always3(s24) || -> . % 76.16/76.37 179776[96:SSi:179775.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.37 179777[94:Spt:179776.0,179196.0,179197.0] || until2p7(s23)*+ -> . % 76.16/76.37 179778[94:Spt:179776.0,179196.1] || -> node4(s22)*. % 76.16/76.37 179780[94:MRR:852.0,179778.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.37 179783[94:Res:53.1,179780.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.37 179785[95:Spt:179783.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.37 179787[95:Res:179785.0,61.1] always3(s22) || -> . % 76.16/76.37 179788[95:SSi:179787.0,78164.0,78168.0,165514.0,179195.0,179778.0] || -> . % 76.16/76.37 179789[95:Spt:179788.0,179783.0,179785.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.37 179790[95:Spt:179788.0,179783.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.37 179794[95:Res:179790.0,61.1] always3(s23) || -> . % 76.16/76.37 179795[95:SSi:179794.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.37 179796[93:Spt:179795.0,179194.0,179195.0] || until2p7(s22)*+ -> . % 76.16/76.37 179797[93:Spt:179795.0,179194.1] || -> node4(s21)*. % 76.16/76.37 179799[93:MRR:855.0,179797.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.37 179802[93:Res:53.1,179799.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.37 179807[94:Spt:179802.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.37 179809[94:Res:179807.0,61.1] always3(s21) || -> . % 76.16/76.37 179810[94:SSi:179809.0,78160.0,78163.0,165513.0,179193.0,179797.0] || -> . % 76.16/76.37 179811[94:Spt:179810.0,179802.0,179807.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.37 179812[94:Spt:179810.0,179802.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.37 179816[94:Res:179812.0,61.1] always3(s22) || -> . % 76.16/76.37 179817[94:SSi:179816.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.37 179818[92:Spt:179817.0,179192.0,179193.0] || until2p7(s21)*+ -> . % 76.16/76.37 179819[92:Spt:179817.0,179192.1] || -> node4(s20)*. % 76.16/76.37 179821[92:MRR:858.0,179819.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.37 179824[92:Res:53.1,179821.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.37 179826[93:Spt:179824.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.37 179828[93:Res:179826.0,61.1] always3(s20) || -> . % 76.16/76.37 179829[93:SSi:179828.0,78155.0,78159.0,165512.0,179191.0,179819.0] || -> . % 76.16/76.37 179830[93:Spt:179829.0,179824.0,179826.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.37 179831[93:Spt:179829.0,179824.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.37 179835[93:Res:179831.0,61.1] always3(s21) || -> . % 76.16/76.37 179836[93:SSi:179835.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.37 179837[91:Spt:179836.0,179190.0,179191.0] || until2p7(s20)*+ -> . % 76.16/76.37 179838[91:Spt:179836.0,179190.1] || -> node4(s19)*. % 76.16/76.37 179840[91:MRR:861.0,179838.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.37 179843[91:Res:53.1,179840.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.37 179845[92:Spt:179843.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.37 179847[92:Res:179845.0,61.1] always3(s19) || -> . % 76.16/76.37 179848[92:SSi:179847.0,78151.0,78154.0,165511.0,179189.0,179838.0] || -> . % 76.16/76.37 179849[92:Spt:179848.0,179843.0,179845.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.37 179850[92:Spt:179848.0,179843.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.37 179854[92:Res:179850.0,61.1] always3(s20) || -> . % 76.16/76.37 179855[92:SSi:179854.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.37 179856[90:Spt:179855.0,179188.0,179189.0] || until2p7(s19)*+ -> . % 76.16/76.37 179857[90:Spt:179855.0,179188.1] || -> node4(s18)*. % 76.16/76.37 179859[90:MRR:864.0,179857.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.37 179862[90:Res:53.1,179859.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.37 179864[91:Spt:179862.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.37 179866[91:Res:179864.0,61.1] always3(s18) || -> . % 76.16/76.37 179867[91:SSi:179866.0,78146.0,78150.0,165510.0,179187.0,179857.0] || -> . % 76.16/76.37 179868[91:Spt:179867.0,179862.0,179864.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.37 179869[91:Spt:179867.0,179862.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.37 179873[91:Res:179869.0,61.1] always3(s19) || -> . % 76.16/76.37 179874[91:SSi:179873.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.37 179875[89:Spt:179874.0,179186.0,179187.0] || until2p7(s18)*+ -> . % 76.16/76.37 179876[89:Spt:179874.0,179186.1] || -> node4(s17)*. % 76.16/76.37 179878[89:MRR:867.0,179876.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.37 179881[89:Res:53.1,179878.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.37 179883[89:MRR:179881.0,179176.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.37 179888[89:Res:179883.0,61.1] always3(s18) || -> . % 76.16/76.37 179889[89:SSi:179888.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.38 179890[87:Spt:179889.0,179053.0,179056.0] || trans(s49,s17)*+ -> . % 76.16/76.38 179891[87:Spt:179889.0,179053.1,179053.2,179053.3,179053.4,179053.5,179053.6,179053.7,179053.8,179053.9,179053.10,179053.11,179053.12] || -> trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.38 179893[87:MRR:179055.1,179890.0] xuntil6(s49) || -> trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.38 179894[88:Spt:179891.0] || -> trans(s49,s16)*. % 76.16/76.38 179895[88:Res:179894.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s16)*. % 76.16/76.38 179897[88:Res:179894.0,60.0] || -> node2(s49,s16)*. % 76.16/76.38 179898[88:SSi:179895.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s16)*. % 76.16/76.38 179899[88:Res:179897.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 180007[88:SoR:179899.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 180009[88:SoR:180007.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)* xuntil6(s49). % 76.16/76.38 180010[88:SSi:180009.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s16,c_busy)* xuntil6(s49). % 76.16/76.38 180011[89:Spt:180010.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 180013[89:Res:180011.0,61.1] always3(s16) || -> . % 76.16/76.38 180014[89:SSi:180013.0,78137.0,78141.0,165508.0] || -> . % 76.16/76.38 180015[89:Spt:180014.0,180010.1,180011.0] || m_main_v_state(s16,c_busy)*+ -> . % 76.16/76.38 180016[89:Spt:180014.0,180010.0,180010.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.38 180020[89:MRR:180007.2,180015.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.38 180021[89:Res:53.1,180016.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.38 180023[89:MRR:180021.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.38 180024[89:MRR:179898.0,180023.0] || -> until2p7(s16)*. % 76.16/76.38 180025[89:MRR:212.0,180024.0] || -> until2p7(s17)* node4(s16). % 76.16/76.38 180026[90:Spt:180025.0] || -> until2p7(s17)*. % 76.16/76.38 180027[90:MRR:213.0,180026.0] || -> until2p7(s18)* node4(s17). % 76.16/76.38 180028[91:Spt:180027.0] || -> until2p7(s18)*. % 76.16/76.38 180029[91:MRR:214.0,180028.0] || -> until2p7(s19)* node4(s18). % 76.16/76.38 180030[92:Spt:180029.0] || -> until2p7(s19)*. % 76.16/76.38 180031[92:MRR:215.0,180030.0] || -> until2p7(s20)* node4(s19). % 76.16/76.38 180032[93:Spt:180031.0] || -> until2p7(s20)*. % 76.16/76.38 180033[93:MRR:216.0,180032.0] || -> until2p7(s21)* node4(s20). % 76.16/76.38 180034[94:Spt:180033.0] || -> until2p7(s21)*. % 76.16/76.38 180035[94:MRR:217.0,180034.0] || -> until2p7(s22)* node4(s21). % 76.16/76.38 180036[95:Spt:180035.0] || -> until2p7(s22)*. % 76.16/76.38 180037[95:MRR:218.0,180036.0] || -> until2p7(s23)* node4(s22). % 76.16/76.38 180038[96:Spt:180037.0] || -> until2p7(s23)*. % 76.16/76.38 180039[96:MRR:219.0,180038.0] || -> until2p7(s24)* node4(s23). % 76.16/76.38 180040[97:Spt:180039.0] || -> until2p7(s24)*. % 76.16/76.38 180041[97:MRR:220.0,180040.0] || -> until2p7(s25)* node4(s24). % 76.16/76.38 180042[98:Spt:180041.0] || -> until2p7(s25)*. % 76.16/76.38 180043[98:MRR:221.0,180042.0] || -> until2p7(s26)* node4(s25). % 76.16/76.38 180044[99:Spt:180043.0] || -> until2p7(s26)*. % 76.16/76.38 180045[99:MRR:222.0,180044.0] || -> until2p7(s27)* node4(s26). % 76.16/76.38 180046[100:Spt:180045.0] || -> until2p7(s27)*. % 76.16/76.38 180047[100:MRR:223.0,180046.0] || -> until2p7(s28)* node4(s27). % 76.16/76.38 180048[101:Spt:180047.0] || -> until2p7(s28)*. % 76.16/76.38 180049[101:MRR:224.0,180048.0] || -> until2p7(s29)* node4(s28). % 76.16/76.38 180050[102:Spt:180049.0] || -> until2p7(s29)*. % 76.16/76.38 180051[102:MRR:225.0,180050.0] || -> until2p7(s30)* node4(s29). % 76.16/76.38 180052[103:Spt:180051.0] || -> until2p7(s30)*. % 76.16/76.38 180053[103:MRR:226.0,180052.0] || -> until2p7(s31)* node4(s30). % 76.16/76.38 180054[104:Spt:180053.0] || -> until2p7(s31)*. % 76.16/76.38 180055[104:MRR:227.0,180054.0] || -> until2p7(s32)* node4(s31). % 76.16/76.38 180056[105:Spt:180055.0] || -> until2p7(s32)*. % 76.16/76.38 180057[105:MRR:228.0,180056.0] || -> until2p7(s33)* node4(s32). % 76.16/76.38 180058[106:Spt:180057.0] || -> until2p7(s33)*. % 76.16/76.38 180059[106:MRR:229.0,180058.0] || -> until2p7(s34)* node4(s33). % 76.16/76.38 180060[107:Spt:180059.0] || -> until2p7(s34)*. % 76.16/76.38 180061[107:MRR:230.0,180060.0] || -> until2p7(s35)* node4(s34). % 76.16/76.38 180062[108:Spt:180061.0] || -> until2p7(s35)*. % 76.16/76.38 180063[108:MRR:231.0,180062.0] || -> until2p7(s36)* node4(s35). % 76.16/76.38 180064[109:Spt:180063.0] || -> until2p7(s36)*. % 76.16/76.38 180065[109:MRR:232.0,180064.0] || -> until2p7(s37)* node4(s36). % 76.16/76.38 180066[110:Spt:180065.0] || -> until2p7(s37)*. % 76.16/76.38 180067[110:MRR:235.0,180066.0] || -> until2p7(s38)* node4(s37). % 76.16/76.38 180068[111:Spt:180067.0] || -> until2p7(s38)*. % 76.16/76.38 180069[111:MRR:236.0,180068.0] || -> until2p7(s39)* node4(s38). % 76.16/76.38 180070[112:Spt:180069.0] || -> until2p7(s39)*. % 76.16/76.38 180071[112:MRR:237.0,180070.0] || -> until2p7(s40)* node4(s39). % 76.16/76.38 180072[113:Spt:180071.0] || -> until2p7(s40)*. % 76.16/76.38 180073[113:MRR:238.0,180072.0] || -> until2p7(s41)* node4(s40). % 76.16/76.38 180074[114:Spt:180073.0] || -> until2p7(s41)*. % 76.16/76.38 180075[114:MRR:239.0,180074.0] || -> until2p7(s42)* node4(s41). % 76.16/76.38 180076[115:Spt:180075.0] || -> until2p7(s42)*. % 76.16/76.38 180077[115:MRR:240.0,180076.0] || -> until2p7(s43)* node4(s42). % 76.16/76.38 180078[116:Spt:180077.0] || -> until2p7(s43)*. % 76.16/76.38 180079[116:MRR:241.0,180078.0] || -> until2p7(s44)* node4(s43). % 76.16/76.38 180080[117:Spt:180079.0] || -> until2p7(s44)*. % 76.16/76.38 180081[117:MRR:539.0,180080.0] || -> until2p7(s45)* node4(s44). % 76.16/76.38 180082[118:Spt:180081.0] || -> until2p7(s45)*. % 76.16/76.38 180083[118:MRR:544.0,180082.0] || -> until2p7(s46)* node4(s45). % 76.16/76.38 180084[119:Spt:180083.0] || -> until2p7(s46)*. % 76.16/76.38 180085[119:MRR:549.0,180084.0] || -> until2p7(s47)* node4(s46). % 76.16/76.38 180086[120:Spt:180085.0] || -> until2p7(s47)*. % 76.16/76.38 180087[120:MRR:554.0,180086.0] || -> until2p7(s48)* node4(s47). % 76.16/76.38 180088[121:Spt:180087.0] || -> until2p7(s48)*. % 76.16/76.38 180089[121:MRR:559.0,180088.0] || -> until2p7(s49)* node4(s48). % 76.16/76.38 180090[122:Spt:180089.0] || -> until2p7(s49)*. % 76.16/76.38 180091[122:MRR:194.0,180090.0] || -> node4(s49)*. % 76.16/76.38 180092[122:MRR:180020.0,180091.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.38 180096[122:Res:53.1,180092.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.38 180098[122:MRR:180096.0,78381.0] || -> . % 76.16/76.38 180099[122:Spt:180098.0,180089.0,180090.0] || until2p7(s49)*+ -> . % 76.16/76.38 180100[122:Spt:180098.0,180089.1] || -> node4(s48)*. % 76.16/76.38 180101[122:MRR:78384.0,180100.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.38 180104[122:Res:53.1,180101.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 180107[122:Res:180104.0,61.1] always3(s48) || -> . % 76.16/76.38 180108[122:SSi:180107.0,78281.0,78387.0,165540.0,180088.0,180100.0] || -> . % 76.16/76.38 180109[121:Spt:180108.0,180087.0,180088.0] || until2p7(s48)*+ -> . % 76.16/76.38 180110[121:Spt:180108.0,180087.1] || -> node4(s47)*. % 76.16/76.38 180112[121:MRR:777.0,180110.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.38 180124[121:Res:53.1,180112.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.38 180126[122:Spt:180124.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 180128[122:Res:180126.0,61.1] always3(s47) || -> . % 76.16/76.38 180129[122:SSi:180128.0,78277.0,78280.0,165539.0,180086.0,180110.0] || -> . % 76.16/76.38 180130[122:Spt:180129.0,180124.0,180126.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.38 180131[122:Spt:180129.0,180124.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 180135[122:Res:180131.0,61.1] always3(s48) || -> . % 76.16/76.38 180136[122:SSi:180135.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.38 180137[120:Spt:180136.0,180085.0,180086.0] || until2p7(s47)*+ -> . % 76.16/76.38 180138[120:Spt:180136.0,180085.1] || -> node4(s46)*. % 76.16/76.38 180140[120:MRR:780.0,180138.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.38 180147[120:Res:53.1,180140.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.38 180152[121:Spt:180147.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 180154[121:Res:180152.0,61.1] always3(s46) || -> . % 76.16/76.38 180155[121:SSi:180154.0,78272.0,78276.0,165538.0,180084.0,180138.0] || -> . % 76.16/76.38 180156[121:Spt:180155.0,180147.0,180152.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.38 180157[121:Spt:180155.0,180147.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 180161[121:Res:180157.0,61.1] always3(s47) || -> . % 76.16/76.38 180162[121:SSi:180161.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.38 180163[119:Spt:180162.0,180083.0,180084.0] || until2p7(s46)*+ -> . % 76.16/76.38 180164[119:Spt:180162.0,180083.1] || -> node4(s45)*. % 76.16/76.38 180166[119:MRR:783.0,180164.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.38 180169[119:Res:53.1,180166.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.38 180171[120:Spt:180169.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 180173[120:Res:180171.0,61.1] always3(s45) || -> . % 76.16/76.38 180174[120:SSi:180173.0,78268.0,78271.0,165537.0,180082.0,180164.0] || -> . % 76.16/76.38 180175[120:Spt:180174.0,180169.0,180171.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.38 180176[120:Spt:180174.0,180169.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 180180[120:Res:180176.0,61.1] always3(s46) || -> . % 76.16/76.38 180181[120:SSi:180180.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.38 180182[118:Spt:180181.0,180081.0,180082.0] || until2p7(s45)*+ -> . % 76.16/76.38 180183[118:Spt:180181.0,180081.1] || -> node4(s44)*. % 76.16/76.38 180185[118:MRR:786.0,180183.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.38 180188[118:Res:53.1,180185.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.38 180190[119:Spt:180188.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 180192[119:Res:180190.0,61.1] always3(s44) || -> . % 76.16/76.38 180193[119:SSi:180192.0,78263.0,78267.0,165536.0,180080.0,180183.0] || -> . % 76.16/76.38 180194[119:Spt:180193.0,180188.0,180190.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.38 180195[119:Spt:180193.0,180188.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 180199[119:Res:180195.0,61.1] always3(s45) || -> . % 76.16/76.38 180200[119:SSi:180199.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.38 180201[117:Spt:180200.0,180079.0,180080.0] || until2p7(s44)*+ -> . % 76.16/76.38 180202[117:Spt:180200.0,180079.1] || -> node4(s43)*. % 76.16/76.38 180204[117:MRR:789.0,180202.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.38 180207[117:Res:53.1,180204.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.38 180209[118:Spt:180207.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 180211[118:Res:180209.0,61.1] always3(s43) || -> . % 76.16/76.38 180212[118:SSi:180211.0,78259.0,78262.0,165535.0,180078.0,180202.0] || -> . % 76.16/76.38 180213[118:Spt:180212.0,180207.0,180209.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.38 180214[118:Spt:180212.0,180207.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 180218[118:Res:180214.0,61.1] always3(s44) || -> . % 76.16/76.38 180219[118:SSi:180218.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.38 180220[116:Spt:180219.0,180077.0,180078.0] || until2p7(s43)*+ -> . % 76.16/76.38 180221[116:Spt:180219.0,180077.1] || -> node4(s42)*. % 76.16/76.38 180223[116:MRR:792.0,180221.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.38 180226[116:Res:53.1,180223.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.38 180231[117:Spt:180226.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 180233[117:Res:180231.0,61.1] always3(s42) || -> . % 76.16/76.38 180234[117:SSi:180233.0,78254.0,78258.0,165534.0,180076.0,180221.0] || -> . % 76.16/76.38 180235[117:Spt:180234.0,180226.0,180231.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.38 180236[117:Spt:180234.0,180226.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 180240[117:Res:180236.0,61.1] always3(s43) || -> . % 76.16/76.38 180241[117:SSi:180240.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.38 180242[115:Spt:180241.0,180075.0,180076.0] || until2p7(s42)*+ -> . % 76.16/76.38 180243[115:Spt:180241.0,180075.1] || -> node4(s41)*. % 76.16/76.38 180245[115:MRR:795.0,180243.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.38 180248[115:Res:53.1,180245.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.38 180250[116:Spt:180248.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 180252[116:Res:180250.0,61.1] always3(s41) || -> . % 76.16/76.38 180253[116:SSi:180252.0,78250.0,78253.0,165533.0,180074.0,180243.0] || -> . % 76.16/76.38 180254[116:Spt:180253.0,180248.0,180250.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.38 180255[116:Spt:180253.0,180248.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 180259[116:Res:180255.0,61.1] always3(s42) || -> . % 76.16/76.38 180260[116:SSi:180259.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.38 180261[114:Spt:180260.0,180073.0,180074.0] || until2p7(s41)*+ -> . % 76.16/76.38 180262[114:Spt:180260.0,180073.1] || -> node4(s40)*. % 76.16/76.38 180264[114:MRR:798.0,180262.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.38 180267[114:Res:53.1,180264.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.38 180269[115:Spt:180267.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 180271[115:Res:180269.0,61.1] always3(s40) || -> . % 76.16/76.38 180272[115:SSi:180271.0,78245.0,78249.0,165532.0,180072.0,180262.0] || -> . % 76.16/76.38 180273[115:Spt:180272.0,180267.0,180269.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.38 180274[115:Spt:180272.0,180267.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 180278[115:Res:180274.0,61.1] always3(s41) || -> . % 76.16/76.38 180279[115:SSi:180278.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.38 180280[113:Spt:180279.0,180071.0,180072.0] || until2p7(s40)*+ -> . % 76.16/76.38 180281[113:Spt:180279.0,180071.1] || -> node4(s39)*. % 76.16/76.38 180283[113:MRR:801.0,180281.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.38 180286[113:Res:53.1,180283.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.38 180288[114:Spt:180286.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 180290[114:Res:180288.0,61.1] always3(s39) || -> . % 76.16/76.38 180291[114:SSi:180290.0,78241.0,78244.0,165531.0,180070.0,180281.0] || -> . % 76.16/76.38 180292[114:Spt:180291.0,180286.0,180288.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.38 180293[114:Spt:180291.0,180286.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 180297[114:Res:180293.0,61.1] always3(s40) || -> . % 76.16/76.38 180298[114:SSi:180297.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.38 180299[112:Spt:180298.0,180069.0,180070.0] || until2p7(s39)*+ -> . % 76.16/76.38 180300[112:Spt:180298.0,180069.1] || -> node4(s38)*. % 76.16/76.38 180302[112:MRR:804.0,180300.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.38 180305[112:Res:53.1,180302.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.38 180310[113:Spt:180305.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 180312[113:Res:180310.0,61.1] always3(s38) || -> . % 76.16/76.38 180313[113:SSi:180312.0,78236.0,78240.0,165530.0,180068.0,180300.0] || -> . % 76.16/76.38 180314[113:Spt:180313.0,180305.0,180310.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.38 180315[113:Spt:180313.0,180305.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 180319[113:Res:180315.0,61.1] always3(s39) || -> . % 76.16/76.38 180320[113:SSi:180319.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.38 180321[111:Spt:180320.0,180067.0,180068.0] || until2p7(s38)*+ -> . % 76.16/76.38 180322[111:Spt:180320.0,180067.1] || -> node4(s37)*. % 76.16/76.38 180324[111:MRR:807.0,180322.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.38 180327[111:Res:53.1,180324.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.38 180329[112:Spt:180327.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 180331[112:Res:180329.0,61.1] always3(s37) || -> . % 76.16/76.38 180332[112:SSi:180331.0,78232.0,78235.0,165529.0,180066.0,180322.0] || -> . % 76.16/76.38 180333[112:Spt:180332.0,180327.0,180329.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.38 180334[112:Spt:180332.0,180327.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 180338[112:Res:180334.0,61.1] always3(s38) || -> . % 76.16/76.38 180339[112:SSi:180338.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.38 180340[110:Spt:180339.0,180065.0,180066.0] || until2p7(s37)*+ -> . % 76.16/76.38 180341[110:Spt:180339.0,180065.1] || -> node4(s36)*. % 76.16/76.38 180343[110:MRR:810.0,180341.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.38 180346[110:Res:53.1,180343.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.38 180348[111:Spt:180346.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 180350[111:Res:180348.0,61.1] always3(s36) || -> . % 76.16/76.38 180351[111:SSi:180350.0,78227.0,78231.0,165528.0,180064.0,180341.0] || -> . % 76.16/76.38 180352[111:Spt:180351.0,180346.0,180348.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.38 180353[111:Spt:180351.0,180346.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 180357[111:Res:180353.0,61.1] always3(s37) || -> . % 76.16/76.38 180358[111:SSi:180357.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.38 180359[109:Spt:180358.0,180063.0,180064.0] || until2p7(s36)*+ -> . % 76.16/76.38 180360[109:Spt:180358.0,180063.1] || -> node4(s35)*. % 76.16/76.38 180362[109:MRR:813.0,180360.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.38 180365[109:Res:53.1,180362.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.38 180367[110:Spt:180365.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 180369[110:Res:180367.0,61.1] always3(s35) || -> . % 76.16/76.38 180370[110:SSi:180369.0,78223.0,78226.0,165527.0,180062.0,180360.0] || -> . % 76.16/76.38 180371[110:Spt:180370.0,180365.0,180367.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.38 180372[110:Spt:180370.0,180365.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 180376[110:Res:180372.0,61.1] always3(s36) || -> . % 76.16/76.38 180377[110:SSi:180376.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.38 180378[108:Spt:180377.0,180061.0,180062.0] || until2p7(s35)*+ -> . % 76.16/76.38 180379[108:Spt:180377.0,180061.1] || -> node4(s34)*. % 76.16/76.38 180381[108:MRR:816.0,180379.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.38 180384[108:Res:53.1,180381.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.38 180389[109:Spt:180384.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 180391[109:Res:180389.0,61.1] always3(s34) || -> . % 76.16/76.38 180392[109:SSi:180391.0,78218.0,78222.0,165526.0,180060.0,180379.0] || -> . % 76.16/76.38 180393[109:Spt:180392.0,180384.0,180389.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.38 180394[109:Spt:180392.0,180384.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 180398[109:Res:180394.0,61.1] always3(s35) || -> . % 76.16/76.38 180399[109:SSi:180398.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.38 180400[107:Spt:180399.0,180059.0,180060.0] || until2p7(s34)*+ -> . % 76.16/76.38 180401[107:Spt:180399.0,180059.1] || -> node4(s33)*. % 76.16/76.38 180403[107:MRR:819.0,180401.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.38 180406[107:Res:53.1,180403.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.38 180408[108:Spt:180406.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 180410[108:Res:180408.0,61.1] always3(s33) || -> . % 76.16/76.38 180411[108:SSi:180410.0,78214.0,78217.0,165525.0,180058.0,180401.0] || -> . % 76.16/76.38 180412[108:Spt:180411.0,180406.0,180408.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.38 180413[108:Spt:180411.0,180406.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 180417[108:Res:180413.0,61.1] always3(s34) || -> . % 76.16/76.38 180418[108:SSi:180417.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.38 180419[106:Spt:180418.0,180057.0,180058.0] || until2p7(s33)*+ -> . % 76.16/76.38 180420[106:Spt:180418.0,180057.1] || -> node4(s32)*. % 76.16/76.38 180422[106:MRR:822.0,180420.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.38 180425[106:Res:53.1,180422.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.38 180427[107:Spt:180425.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 180429[107:Res:180427.0,61.1] always3(s32) || -> . % 76.16/76.38 180430[107:SSi:180429.0,78209.0,78213.0,165524.0,180056.0,180420.0] || -> . % 76.16/76.38 180431[107:Spt:180430.0,180425.0,180427.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.38 180432[107:Spt:180430.0,180425.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 180436[107:Res:180432.0,61.1] always3(s33) || -> . % 76.16/76.38 180437[107:SSi:180436.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.38 180438[105:Spt:180437.0,180055.0,180056.0] || until2p7(s32)*+ -> . % 76.16/76.38 180439[105:Spt:180437.0,180055.1] || -> node4(s31)*. % 76.16/76.38 180441[105:MRR:825.0,180439.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.38 180444[105:Res:53.1,180441.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.38 180446[106:Spt:180444.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 180448[106:Res:180446.0,61.1] always3(s31) || -> . % 76.16/76.38 180449[106:SSi:180448.0,78205.0,78208.0,165523.0,180054.0,180439.0] || -> . % 76.16/76.38 180450[106:Spt:180449.0,180444.0,180446.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.38 180451[106:Spt:180449.0,180444.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 180455[106:Res:180451.0,61.1] always3(s32) || -> . % 76.16/76.38 180456[106:SSi:180455.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.38 180457[104:Spt:180456.0,180053.0,180054.0] || until2p7(s31)*+ -> . % 76.16/76.38 180458[104:Spt:180456.0,180053.1] || -> node4(s30)*. % 76.16/76.38 180460[104:MRR:828.0,180458.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.38 180463[104:Res:53.1,180460.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.38 180468[105:Spt:180463.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 180470[105:Res:180468.0,61.1] always3(s30) || -> . % 76.16/76.38 180471[105:SSi:180470.0,78200.0,78204.0,165522.0,180052.0,180458.0] || -> . % 76.16/76.38 180472[105:Spt:180471.0,180463.0,180468.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.38 180473[105:Spt:180471.0,180463.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 180477[105:Res:180473.0,61.1] always3(s31) || -> . % 76.16/76.38 180478[105:SSi:180477.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.38 180479[103:Spt:180478.0,180051.0,180052.0] || until2p7(s30)*+ -> . % 76.16/76.38 180480[103:Spt:180478.0,180051.1] || -> node4(s29)*. % 76.16/76.38 180482[103:MRR:831.0,180480.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.38 180485[103:Res:53.1,180482.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.38 180487[104:Spt:180485.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 180489[104:Res:180487.0,61.1] always3(s29) || -> . % 76.16/76.38 180490[104:SSi:180489.0,78196.0,78199.0,165521.0,180050.0,180480.0] || -> . % 76.16/76.38 180491[104:Spt:180490.0,180485.0,180487.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.38 180492[104:Spt:180490.0,180485.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 180496[104:Res:180492.0,61.1] always3(s30) || -> . % 76.16/76.38 180497[104:SSi:180496.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.38 180498[102:Spt:180497.0,180049.0,180050.0] || until2p7(s29)*+ -> . % 76.16/76.38 180499[102:Spt:180497.0,180049.1] || -> node4(s28)*. % 76.16/76.38 180501[102:MRR:834.0,180499.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.38 180504[102:Res:53.1,180501.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.38 180506[103:Spt:180504.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 180508[103:Res:180506.0,61.1] always3(s28) || -> . % 76.16/76.38 180509[103:SSi:180508.0,78191.0,78195.0,165520.0,180048.0,180499.0] || -> . % 76.16/76.38 180510[103:Spt:180509.0,180504.0,180506.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.38 180511[103:Spt:180509.0,180504.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 180515[103:Res:180511.0,61.1] always3(s29) || -> . % 76.16/76.38 180516[103:SSi:180515.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.38 180517[101:Spt:180516.0,180047.0,180048.0] || until2p7(s28)*+ -> . % 76.16/76.38 180518[101:Spt:180516.0,180047.1] || -> node4(s27)*. % 76.16/76.38 180520[101:MRR:837.0,180518.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.38 180523[101:Res:53.1,180520.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.38 180525[102:Spt:180523.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 180527[102:Res:180525.0,61.1] always3(s27) || -> . % 76.16/76.38 180528[102:SSi:180527.0,78187.0,78190.0,165519.0,180046.0,180518.0] || -> . % 76.16/76.38 180529[102:Spt:180528.0,180523.0,180525.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.38 180530[102:Spt:180528.0,180523.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 180534[102:Res:180530.0,61.1] always3(s28) || -> . % 76.16/76.38 180535[102:SSi:180534.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.38 180536[100:Spt:180535.0,180045.0,180046.0] || until2p7(s27)*+ -> . % 76.16/76.38 180537[100:Spt:180535.0,180045.1] || -> node4(s26)*. % 76.16/76.38 180539[100:MRR:840.0,180537.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.38 180542[100:Res:53.1,180539.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.38 180547[101:Spt:180542.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 180549[101:Res:180547.0,61.1] always3(s26) || -> . % 76.16/76.38 180550[101:SSi:180549.0,78182.0,78186.0,165518.0,180044.0,180537.0] || -> . % 76.16/76.38 180551[101:Spt:180550.0,180542.0,180547.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.38 180552[101:Spt:180550.0,180542.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 180556[101:Res:180552.0,61.1] always3(s27) || -> . % 76.16/76.38 180557[101:SSi:180556.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.38 180558[99:Spt:180557.0,180043.0,180044.0] || until2p7(s26)*+ -> . % 76.16/76.38 180559[99:Spt:180557.0,180043.1] || -> node4(s25)*. % 76.16/76.38 180561[99:MRR:843.0,180559.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.38 180564[99:Res:53.1,180561.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.38 180566[100:Spt:180564.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 180568[100:Res:180566.0,61.1] always3(s25) || -> . % 76.16/76.38 180569[100:SSi:180568.0,78178.0,78181.0,165517.0,180042.0,180559.0] || -> . % 76.16/76.38 180570[100:Spt:180569.0,180564.0,180566.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.38 180571[100:Spt:180569.0,180564.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 180575[100:Res:180571.0,61.1] always3(s26) || -> . % 76.16/76.38 180576[100:SSi:180575.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.38 180577[98:Spt:180576.0,180041.0,180042.0] || until2p7(s25)*+ -> . % 76.16/76.38 180578[98:Spt:180576.0,180041.1] || -> node4(s24)*. % 76.16/76.38 180580[98:MRR:846.0,180578.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.38 180583[98:Res:53.1,180580.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.38 180585[99:Spt:180583.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 180587[99:Res:180585.0,61.1] always3(s24) || -> . % 76.16/76.38 180588[99:SSi:180587.0,78173.0,78177.0,165516.0,180040.0,180578.0] || -> . % 76.16/76.38 180589[99:Spt:180588.0,180583.0,180585.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.38 180590[99:Spt:180588.0,180583.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 180594[99:Res:180590.0,61.1] always3(s25) || -> . % 76.16/76.38 180595[99:SSi:180594.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.38 180596[97:Spt:180595.0,180039.0,180040.0] || until2p7(s24)*+ -> . % 76.16/76.38 180597[97:Spt:180595.0,180039.1] || -> node4(s23)*. % 76.16/76.38 180599[97:MRR:849.0,180597.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.38 180602[97:Res:53.1,180599.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.38 180604[98:Spt:180602.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 180606[98:Res:180604.0,61.1] always3(s23) || -> . % 76.16/76.38 180607[98:SSi:180606.0,78169.0,78172.0,165515.0,180038.0,180597.0] || -> . % 76.16/76.38 180608[98:Spt:180607.0,180602.0,180604.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.38 180609[98:Spt:180607.0,180602.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 180613[98:Res:180609.0,61.1] always3(s24) || -> . % 76.16/76.38 180614[98:SSi:180613.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.38 180615[96:Spt:180614.0,180037.0,180038.0] || until2p7(s23)*+ -> . % 76.16/76.38 180616[96:Spt:180614.0,180037.1] || -> node4(s22)*. % 76.16/76.38 180618[96:MRR:852.0,180616.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.38 180621[96:Res:53.1,180618.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.38 180626[97:Spt:180621.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 180628[97:Res:180626.0,61.1] always3(s22) || -> . % 76.16/76.38 180629[97:SSi:180628.0,78164.0,78168.0,165514.0,180036.0,180616.0] || -> . % 76.16/76.38 180630[97:Spt:180629.0,180621.0,180626.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.38 180631[97:Spt:180629.0,180621.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 180635[97:Res:180631.0,61.1] always3(s23) || -> . % 76.16/76.38 180636[97:SSi:180635.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.38 180637[95:Spt:180636.0,180035.0,180036.0] || until2p7(s22)*+ -> . % 76.16/76.38 180638[95:Spt:180636.0,180035.1] || -> node4(s21)*. % 76.16/76.38 180640[95:MRR:855.0,180638.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.38 180643[95:Res:53.1,180640.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.38 180645[96:Spt:180643.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 180647[96:Res:180645.0,61.1] always3(s21) || -> . % 76.16/76.38 180648[96:SSi:180647.0,78160.0,78163.0,165513.0,180034.0,180638.0] || -> . % 76.16/76.38 180649[96:Spt:180648.0,180643.0,180645.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.38 180650[96:Spt:180648.0,180643.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 180654[96:Res:180650.0,61.1] always3(s22) || -> . % 76.16/76.38 180655[96:SSi:180654.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.38 180656[94:Spt:180655.0,180033.0,180034.0] || until2p7(s21)*+ -> . % 76.16/76.38 180657[94:Spt:180655.0,180033.1] || -> node4(s20)*. % 76.16/76.38 180659[94:MRR:858.0,180657.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.38 180662[94:Res:53.1,180659.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.38 180664[95:Spt:180662.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 180666[95:Res:180664.0,61.1] always3(s20) || -> . % 76.16/76.38 180667[95:SSi:180666.0,78155.0,78159.0,165512.0,180032.0,180657.0] || -> . % 76.16/76.38 180668[95:Spt:180667.0,180662.0,180664.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.38 180669[95:Spt:180667.0,180662.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 180673[95:Res:180669.0,61.1] always3(s21) || -> . % 76.16/76.38 180674[95:SSi:180673.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.38 180675[93:Spt:180674.0,180031.0,180032.0] || until2p7(s20)*+ -> . % 76.16/76.38 180676[93:Spt:180674.0,180031.1] || -> node4(s19)*. % 76.16/76.38 180678[93:MRR:861.0,180676.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.38 180681[93:Res:53.1,180678.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.38 180683[94:Spt:180681.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 180685[94:Res:180683.0,61.1] always3(s19) || -> . % 76.16/76.38 180686[94:SSi:180685.0,78151.0,78154.0,165511.0,180030.0,180676.0] || -> . % 76.16/76.38 180687[94:Spt:180686.0,180681.0,180683.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.38 180688[94:Spt:180686.0,180681.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 180692[94:Res:180688.0,61.1] always3(s20) || -> . % 76.16/76.38 180693[94:SSi:180692.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.38 180694[92:Spt:180693.0,180029.0,180030.0] || until2p7(s19)*+ -> . % 76.16/76.38 180695[92:Spt:180693.0,180029.1] || -> node4(s18)*. % 76.16/76.38 180697[92:MRR:864.0,180695.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.38 180700[92:Res:53.1,180697.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.38 180705[93:Spt:180700.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 180707[93:Res:180705.0,61.1] always3(s18) || -> . % 76.16/76.38 180708[93:SSi:180707.0,78146.0,78150.0,165510.0,180028.0,180695.0] || -> . % 76.16/76.38 180709[93:Spt:180708.0,180700.0,180705.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.38 180710[93:Spt:180708.0,180700.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 180714[93:Res:180710.0,61.1] always3(s19) || -> . % 76.16/76.38 180715[93:SSi:180714.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.38 180716[91:Spt:180715.0,180027.0,180028.0] || until2p7(s18)*+ -> . % 76.16/76.38 180717[91:Spt:180715.0,180027.1] || -> node4(s17)*. % 76.16/76.38 180719[91:MRR:867.0,180717.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.38 180722[91:Res:53.1,180719.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.38 180724[92:Spt:180722.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 180726[92:Res:180724.0,61.1] always3(s17) || -> . % 76.16/76.38 180727[92:SSi:180726.0,78142.0,78145.0,165509.0,180026.0,180717.0] || -> . % 76.16/76.38 180728[92:Spt:180727.0,180722.0,180724.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.38 180729[92:Spt:180727.0,180722.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 180733[92:Res:180729.0,61.1] always3(s18) || -> . % 76.16/76.38 180734[92:SSi:180733.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.38 180735[90:Spt:180734.0,180025.0,180026.0] || until2p7(s17)*+ -> . % 76.16/76.38 180736[90:Spt:180734.0,180025.1] || -> node4(s16)*. % 76.16/76.38 180738[90:MRR:870.0,180736.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.38 180741[90:Res:53.1,180738.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.38 180743[90:MRR:180741.0,180015.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 180745[90:Res:180743.0,61.1] always3(s17) || -> . % 76.16/76.38 180746[90:SSi:180745.0,78142.0,78145.0,165509.0] || -> . % 76.16/76.38 180747[88:Spt:180746.0,179891.0,179894.0] || trans(s49,s16)*+ -> . % 76.16/76.38 180748[88:Spt:180746.0,179891.1,179891.2,179891.3,179891.4,179891.5,179891.6,179891.7,179891.8,179891.9,179891.10,179891.11] || -> trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.38 180750[88:MRR:179893.1,180747.0] xuntil6(s49) || -> trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.38 180751[89:Spt:180748.0] || -> trans(s49,s15)*. % 76.16/76.38 180752[89:Res:180751.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s15)*. % 76.16/76.38 180754[89:Res:180751.0,60.0] || -> node2(s49,s15)*. % 76.16/76.38 180755[89:SSi:180752.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s15)*. % 76.16/76.38 180756[89:Res:180754.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 180871[89:SoR:180756.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 180873[89:SoR:180871.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)* xuntil6(s49). % 76.16/76.38 180874[89:SSi:180873.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s15,c_busy)* xuntil6(s49). % 76.16/76.38 180875[90:Spt:180874.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 180877[90:Res:180875.0,61.1] always3(s15) || -> . % 76.16/76.38 180878[90:SSi:180877.0,78133.0,78136.0,165507.0] || -> . % 76.16/76.38 180879[90:Spt:180878.0,180874.1,180875.0] || m_main_v_state(s15,c_busy)*+ -> . % 76.16/76.38 180880[90:Spt:180878.0,180874.0,180874.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.38 180884[90:MRR:180871.2,180879.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.38 180885[90:Res:53.1,180880.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.38 180887[90:MRR:180885.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.38 180888[90:MRR:180755.0,180887.0] || -> until2p7(s15)*. % 76.16/76.38 180889[90:MRR:211.0,180888.0] || -> until2p7(s16)* node4(s15). % 76.16/76.38 180890[91:Spt:180889.0] || -> until2p7(s16)*. % 76.16/76.38 180891[91:MRR:212.0,180890.0] || -> until2p7(s17)* node4(s16). % 76.16/76.38 180892[92:Spt:180891.0] || -> until2p7(s17)*. % 76.16/76.38 180893[92:MRR:213.0,180892.0] || -> until2p7(s18)* node4(s17). % 76.16/76.38 180894[93:Spt:180893.0] || -> until2p7(s18)*. % 76.16/76.38 180895[93:MRR:214.0,180894.0] || -> until2p7(s19)* node4(s18). % 76.16/76.38 180896[94:Spt:180895.0] || -> until2p7(s19)*. % 76.16/76.38 180897[94:MRR:215.0,180896.0] || -> until2p7(s20)* node4(s19). % 76.16/76.38 180898[95:Spt:180897.0] || -> until2p7(s20)*. % 76.16/76.38 180899[95:MRR:216.0,180898.0] || -> until2p7(s21)* node4(s20). % 76.16/76.38 180900[96:Spt:180899.0] || -> until2p7(s21)*. % 76.16/76.38 180901[96:MRR:217.0,180900.0] || -> until2p7(s22)* node4(s21). % 76.16/76.38 180902[97:Spt:180901.0] || -> until2p7(s22)*. % 76.16/76.38 180903[97:MRR:218.0,180902.0] || -> until2p7(s23)* node4(s22). % 76.16/76.38 180904[98:Spt:180903.0] || -> until2p7(s23)*. % 76.16/76.38 180905[98:MRR:219.0,180904.0] || -> until2p7(s24)* node4(s23). % 76.16/76.38 180906[99:Spt:180905.0] || -> until2p7(s24)*. % 76.16/76.38 180907[99:MRR:220.0,180906.0] || -> until2p7(s25)* node4(s24). % 76.16/76.38 180908[100:Spt:180907.0] || -> until2p7(s25)*. % 76.16/76.38 180909[100:MRR:221.0,180908.0] || -> until2p7(s26)* node4(s25). % 76.16/76.38 180910[101:Spt:180909.0] || -> until2p7(s26)*. % 76.16/76.38 180911[101:MRR:222.0,180910.0] || -> until2p7(s27)* node4(s26). % 76.16/76.38 180912[102:Spt:180911.0] || -> until2p7(s27)*. % 76.16/76.38 180913[102:MRR:223.0,180912.0] || -> until2p7(s28)* node4(s27). % 76.16/76.38 180914[103:Spt:180913.0] || -> until2p7(s28)*. % 76.16/76.38 180915[103:MRR:224.0,180914.0] || -> until2p7(s29)* node4(s28). % 76.16/76.38 180916[104:Spt:180915.0] || -> until2p7(s29)*. % 76.16/76.38 180917[104:MRR:225.0,180916.0] || -> until2p7(s30)* node4(s29). % 76.16/76.38 180918[105:Spt:180917.0] || -> until2p7(s30)*. % 76.16/76.38 180919[105:MRR:226.0,180918.0] || -> until2p7(s31)* node4(s30). % 76.16/76.38 180920[106:Spt:180919.0] || -> until2p7(s31)*. % 76.16/76.38 180921[106:MRR:227.0,180920.0] || -> until2p7(s32)* node4(s31). % 76.16/76.38 180922[107:Spt:180921.0] || -> until2p7(s32)*. % 76.16/76.38 180923[107:MRR:228.0,180922.0] || -> until2p7(s33)* node4(s32). % 76.16/76.38 180924[108:Spt:180923.0] || -> until2p7(s33)*. % 76.16/76.38 180925[108:MRR:229.0,180924.0] || -> until2p7(s34)* node4(s33). % 76.16/76.38 180926[109:Spt:180925.0] || -> until2p7(s34)*. % 76.16/76.38 180927[109:MRR:230.0,180926.0] || -> until2p7(s35)* node4(s34). % 76.16/76.38 180928[110:Spt:180927.0] || -> until2p7(s35)*. % 76.16/76.38 180929[110:MRR:231.0,180928.0] || -> until2p7(s36)* node4(s35). % 76.16/76.38 180930[111:Spt:180929.0] || -> until2p7(s36)*. % 76.16/76.38 180931[111:MRR:232.0,180930.0] || -> until2p7(s37)* node4(s36). % 76.16/76.38 180932[112:Spt:180931.0] || -> until2p7(s37)*. % 76.16/76.38 180933[112:MRR:235.0,180932.0] || -> until2p7(s38)* node4(s37). % 76.16/76.38 180934[113:Spt:180933.0] || -> until2p7(s38)*. % 76.16/76.38 180935[113:MRR:236.0,180934.0] || -> until2p7(s39)* node4(s38). % 76.16/76.38 180936[114:Spt:180935.0] || -> until2p7(s39)*. % 76.16/76.38 180937[114:MRR:237.0,180936.0] || -> until2p7(s40)* node4(s39). % 76.16/76.38 180938[115:Spt:180937.0] || -> until2p7(s40)*. % 76.16/76.38 180939[115:MRR:238.0,180938.0] || -> until2p7(s41)* node4(s40). % 76.16/76.38 180940[116:Spt:180939.0] || -> until2p7(s41)*. % 76.16/76.38 180941[116:MRR:239.0,180940.0] || -> until2p7(s42)* node4(s41). % 76.16/76.38 180942[117:Spt:180941.0] || -> until2p7(s42)*. % 76.16/76.38 180943[117:MRR:240.0,180942.0] || -> until2p7(s43)* node4(s42). % 76.16/76.38 180944[118:Spt:180943.0] || -> until2p7(s43)*. % 76.16/76.38 180945[118:MRR:241.0,180944.0] || -> until2p7(s44)* node4(s43). % 76.16/76.38 180946[119:Spt:180945.0] || -> until2p7(s44)*. % 76.16/76.38 180947[119:MRR:539.0,180946.0] || -> until2p7(s45)* node4(s44). % 76.16/76.38 180948[120:Spt:180947.0] || -> until2p7(s45)*. % 76.16/76.38 180949[120:MRR:544.0,180948.0] || -> until2p7(s46)* node4(s45). % 76.16/76.38 180950[121:Spt:180949.0] || -> until2p7(s46)*. % 76.16/76.38 180951[121:MRR:549.0,180950.0] || -> until2p7(s47)* node4(s46). % 76.16/76.38 180952[122:Spt:180951.0] || -> until2p7(s47)*. % 76.16/76.38 180953[122:MRR:554.0,180952.0] || -> until2p7(s48)* node4(s47). % 76.16/76.38 180954[123:Spt:180953.0] || -> until2p7(s48)*. % 76.16/76.38 180955[123:MRR:559.0,180954.0] || -> until2p7(s49)* node4(s48). % 76.16/76.38 180956[124:Spt:180955.0] || -> until2p7(s49)*. % 76.16/76.38 180957[124:MRR:194.0,180956.0] || -> node4(s49)*. % 76.16/76.38 180958[124:MRR:180884.0,180957.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.38 180959[124:Res:53.1,180958.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.38 180961[124:MRR:180959.0,78381.0] || -> . % 76.16/76.38 180962[124:Spt:180961.0,180955.0,180956.0] || until2p7(s49)*+ -> . % 76.16/76.38 180963[124:Spt:180961.0,180955.1] || -> node4(s48)*. % 76.16/76.38 180964[124:MRR:78384.0,180963.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.38 180967[124:Res:53.1,180964.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 180970[124:Res:180967.0,61.1] always3(s48) || -> . % 76.16/76.38 180971[124:SSi:180970.0,78281.0,78387.0,165540.0,180954.0,180963.0] || -> . % 76.16/76.38 180972[123:Spt:180971.0,180953.0,180954.0] || until2p7(s48)*+ -> . % 76.16/76.38 180973[123:Spt:180971.0,180953.1] || -> node4(s47)*. % 76.16/76.38 180975[123:MRR:777.0,180973.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.38 180990[123:Res:53.1,180975.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.38 180992[124:Spt:180990.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 180994[124:Res:180992.0,61.1] always3(s47) || -> . % 76.16/76.38 180995[124:SSi:180994.0,78277.0,78280.0,165539.0,180952.0,180973.0] || -> . % 76.16/76.38 180996[124:Spt:180995.0,180990.0,180992.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.38 180997[124:Spt:180995.0,180990.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 181001[124:Res:180997.0,61.1] always3(s48) || -> . % 76.16/76.38 181002[124:SSi:181001.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.38 181003[122:Spt:181002.0,180951.0,180952.0] || until2p7(s47)*+ -> . % 76.16/76.38 181004[122:Spt:181002.0,180951.1] || -> node4(s46)*. % 76.16/76.38 181006[122:MRR:780.0,181004.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.38 181016[122:Res:53.1,181006.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.38 181018[123:Spt:181016.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 181020[123:Res:181018.0,61.1] always3(s46) || -> . % 76.16/76.38 181021[123:SSi:181020.0,78272.0,78276.0,165538.0,180950.0,181004.0] || -> . % 76.16/76.38 181022[123:Spt:181021.0,181016.0,181018.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.38 181023[123:Spt:181021.0,181016.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 181027[123:Res:181023.0,61.1] always3(s47) || -> . % 76.16/76.38 181028[123:SSi:181027.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.38 181029[121:Spt:181028.0,180949.0,180950.0] || until2p7(s46)*+ -> . % 76.16/76.38 181030[121:Spt:181028.0,180949.1] || -> node4(s45)*. % 76.16/76.38 181032[121:MRR:783.0,181030.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.38 181035[121:Res:53.1,181032.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.38 181037[122:Spt:181035.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 181039[122:Res:181037.0,61.1] always3(s45) || -> . % 76.16/76.38 181040[122:SSi:181039.0,78268.0,78271.0,165537.0,180948.0,181030.0] || -> . % 76.16/76.38 181041[122:Spt:181040.0,181035.0,181037.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.38 181042[122:Spt:181040.0,181035.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 181046[122:Res:181042.0,61.1] always3(s46) || -> . % 76.16/76.38 181047[122:SSi:181046.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.38 181048[120:Spt:181047.0,180947.0,180948.0] || until2p7(s45)*+ -> . % 76.16/76.38 181049[120:Spt:181047.0,180947.1] || -> node4(s44)*. % 76.16/76.38 181051[120:MRR:786.0,181049.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.38 181054[120:Res:53.1,181051.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.38 181056[121:Spt:181054.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 181058[121:Res:181056.0,61.1] always3(s44) || -> . % 76.16/76.38 181059[121:SSi:181058.0,78263.0,78267.0,165536.0,180946.0,181049.0] || -> . % 76.16/76.38 181060[121:Spt:181059.0,181054.0,181056.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.38 181061[121:Spt:181059.0,181054.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 181065[121:Res:181061.0,61.1] always3(s45) || -> . % 76.16/76.38 181066[121:SSi:181065.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.38 181067[119:Spt:181066.0,180945.0,180946.0] || until2p7(s44)*+ -> . % 76.16/76.38 181068[119:Spt:181066.0,180945.1] || -> node4(s43)*. % 76.16/76.38 181070[119:MRR:789.0,181068.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.38 181073[119:Res:53.1,181070.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.38 181078[120:Spt:181073.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 181080[120:Res:181078.0,61.1] always3(s43) || -> . % 76.16/76.38 181081[120:SSi:181080.0,78259.0,78262.0,165535.0,180944.0,181068.0] || -> . % 76.16/76.38 181082[120:Spt:181081.0,181073.0,181078.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.38 181083[120:Spt:181081.0,181073.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 181087[120:Res:181083.0,61.1] always3(s44) || -> . % 76.16/76.38 181088[120:SSi:181087.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.38 181089[118:Spt:181088.0,180943.0,180944.0] || until2p7(s43)*+ -> . % 76.16/76.38 181090[118:Spt:181088.0,180943.1] || -> node4(s42)*. % 76.16/76.38 181092[118:MRR:792.0,181090.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.38 181095[118:Res:53.1,181092.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.38 181097[119:Spt:181095.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 181099[119:Res:181097.0,61.1] always3(s42) || -> . % 76.16/76.38 181100[119:SSi:181099.0,78254.0,78258.0,165534.0,180942.0,181090.0] || -> . % 76.16/76.38 181101[119:Spt:181100.0,181095.0,181097.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.38 181102[119:Spt:181100.0,181095.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 181106[119:Res:181102.0,61.1] always3(s43) || -> . % 76.16/76.38 181107[119:SSi:181106.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.38 181108[117:Spt:181107.0,180941.0,180942.0] || until2p7(s42)*+ -> . % 76.16/76.38 181109[117:Spt:181107.0,180941.1] || -> node4(s41)*. % 76.16/76.38 181111[117:MRR:795.0,181109.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.38 181114[117:Res:53.1,181111.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.38 181116[118:Spt:181114.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 181118[118:Res:181116.0,61.1] always3(s41) || -> . % 76.16/76.38 181119[118:SSi:181118.0,78250.0,78253.0,165533.0,180940.0,181109.0] || -> . % 76.16/76.38 181120[118:Spt:181119.0,181114.0,181116.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.38 181121[118:Spt:181119.0,181114.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 181125[118:Res:181121.0,61.1] always3(s42) || -> . % 76.16/76.38 181126[118:SSi:181125.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.38 181127[116:Spt:181126.0,180939.0,180940.0] || until2p7(s41)*+ -> . % 76.16/76.38 181128[116:Spt:181126.0,180939.1] || -> node4(s40)*. % 76.16/76.38 181130[116:MRR:798.0,181128.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.38 181133[116:Res:53.1,181130.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.38 181135[117:Spt:181133.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 181137[117:Res:181135.0,61.1] always3(s40) || -> . % 76.16/76.38 181138[117:SSi:181137.0,78245.0,78249.0,165532.0,180938.0,181128.0] || -> . % 76.16/76.38 181139[117:Spt:181138.0,181133.0,181135.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.38 181140[117:Spt:181138.0,181133.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 181144[117:Res:181140.0,61.1] always3(s41) || -> . % 76.16/76.38 181145[117:SSi:181144.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.38 181146[115:Spt:181145.0,180937.0,180938.0] || until2p7(s40)*+ -> . % 76.16/76.38 181147[115:Spt:181145.0,180937.1] || -> node4(s39)*. % 76.16/76.38 181149[115:MRR:801.0,181147.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.38 181152[115:Res:53.1,181149.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.38 181157[116:Spt:181152.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 181159[116:Res:181157.0,61.1] always3(s39) || -> . % 76.16/76.38 181160[116:SSi:181159.0,78241.0,78244.0,165531.0,180936.0,181147.0] || -> . % 76.16/76.38 181161[116:Spt:181160.0,181152.0,181157.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.38 181162[116:Spt:181160.0,181152.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 181166[116:Res:181162.0,61.1] always3(s40) || -> . % 76.16/76.38 181167[116:SSi:181166.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.38 181168[114:Spt:181167.0,180935.0,180936.0] || until2p7(s39)*+ -> . % 76.16/76.38 181169[114:Spt:181167.0,180935.1] || -> node4(s38)*. % 76.16/76.38 181171[114:MRR:804.0,181169.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.38 181174[114:Res:53.1,181171.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.38 181176[115:Spt:181174.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 181178[115:Res:181176.0,61.1] always3(s38) || -> . % 76.16/76.38 181179[115:SSi:181178.0,78236.0,78240.0,165530.0,180934.0,181169.0] || -> . % 76.16/76.38 181180[115:Spt:181179.0,181174.0,181176.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.38 181181[115:Spt:181179.0,181174.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 181185[115:Res:181181.0,61.1] always3(s39) || -> . % 76.16/76.38 181186[115:SSi:181185.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.38 181187[113:Spt:181186.0,180933.0,180934.0] || until2p7(s38)*+ -> . % 76.16/76.38 181188[113:Spt:181186.0,180933.1] || -> node4(s37)*. % 76.16/76.38 181190[113:MRR:807.0,181188.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.38 181193[113:Res:53.1,181190.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.38 181195[114:Spt:181193.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 181197[114:Res:181195.0,61.1] always3(s37) || -> . % 76.16/76.38 181198[114:SSi:181197.0,78232.0,78235.0,165529.0,180932.0,181188.0] || -> . % 76.16/76.38 181199[114:Spt:181198.0,181193.0,181195.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.38 181200[114:Spt:181198.0,181193.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 181204[114:Res:181200.0,61.1] always3(s38) || -> . % 76.16/76.38 181205[114:SSi:181204.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.38 181206[112:Spt:181205.0,180931.0,180932.0] || until2p7(s37)*+ -> . % 76.16/76.38 181207[112:Spt:181205.0,180931.1] || -> node4(s36)*. % 76.16/76.38 181209[112:MRR:810.0,181207.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.38 181212[112:Res:53.1,181209.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.38 181214[113:Spt:181212.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 181216[113:Res:181214.0,61.1] always3(s36) || -> . % 76.16/76.38 181217[113:SSi:181216.0,78227.0,78231.0,165528.0,180930.0,181207.0] || -> . % 76.16/76.38 181218[113:Spt:181217.0,181212.0,181214.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.38 181219[113:Spt:181217.0,181212.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 181223[113:Res:181219.0,61.1] always3(s37) || -> . % 76.16/76.38 181224[113:SSi:181223.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.38 181225[111:Spt:181224.0,180929.0,180930.0] || until2p7(s36)*+ -> . % 76.16/76.38 181226[111:Spt:181224.0,180929.1] || -> node4(s35)*. % 76.16/76.38 181228[111:MRR:813.0,181226.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.38 181231[111:Res:53.1,181228.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.38 181236[112:Spt:181231.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 181238[112:Res:181236.0,61.1] always3(s35) || -> . % 76.16/76.38 181239[112:SSi:181238.0,78223.0,78226.0,165527.0,180928.0,181226.0] || -> . % 76.16/76.38 181240[112:Spt:181239.0,181231.0,181236.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.38 181241[112:Spt:181239.0,181231.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 181245[112:Res:181241.0,61.1] always3(s36) || -> . % 76.16/76.38 181246[112:SSi:181245.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.38 181247[110:Spt:181246.0,180927.0,180928.0] || until2p7(s35)*+ -> . % 76.16/76.38 181248[110:Spt:181246.0,180927.1] || -> node4(s34)*. % 76.16/76.38 181250[110:MRR:816.0,181248.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.38 181253[110:Res:53.1,181250.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.38 181255[111:Spt:181253.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 181257[111:Res:181255.0,61.1] always3(s34) || -> . % 76.16/76.38 181258[111:SSi:181257.0,78218.0,78222.0,165526.0,180926.0,181248.0] || -> . % 76.16/76.38 181259[111:Spt:181258.0,181253.0,181255.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.38 181260[111:Spt:181258.0,181253.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 181264[111:Res:181260.0,61.1] always3(s35) || -> . % 76.16/76.38 181265[111:SSi:181264.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.38 181266[109:Spt:181265.0,180925.0,180926.0] || until2p7(s34)*+ -> . % 76.16/76.38 181267[109:Spt:181265.0,180925.1] || -> node4(s33)*. % 76.16/76.38 181269[109:MRR:819.0,181267.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.38 181272[109:Res:53.1,181269.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.38 181274[110:Spt:181272.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 181276[110:Res:181274.0,61.1] always3(s33) || -> . % 76.16/76.38 181277[110:SSi:181276.0,78214.0,78217.0,165525.0,180924.0,181267.0] || -> . % 76.16/76.38 181278[110:Spt:181277.0,181272.0,181274.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.38 181279[110:Spt:181277.0,181272.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 181283[110:Res:181279.0,61.1] always3(s34) || -> . % 76.16/76.38 181284[110:SSi:181283.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.38 181285[108:Spt:181284.0,180923.0,180924.0] || until2p7(s33)*+ -> . % 76.16/76.38 181286[108:Spt:181284.0,180923.1] || -> node4(s32)*. % 76.16/76.38 181288[108:MRR:822.0,181286.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.38 181291[108:Res:53.1,181288.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.38 181293[109:Spt:181291.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 181295[109:Res:181293.0,61.1] always3(s32) || -> . % 76.16/76.38 181296[109:SSi:181295.0,78209.0,78213.0,165524.0,180922.0,181286.0] || -> . % 76.16/76.38 181297[109:Spt:181296.0,181291.0,181293.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.38 181298[109:Spt:181296.0,181291.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 181302[109:Res:181298.0,61.1] always3(s33) || -> . % 76.16/76.38 181303[109:SSi:181302.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.38 181304[107:Spt:181303.0,180921.0,180922.0] || until2p7(s32)*+ -> . % 76.16/76.38 181305[107:Spt:181303.0,180921.1] || -> node4(s31)*. % 76.16/76.38 181307[107:MRR:825.0,181305.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.38 181310[107:Res:53.1,181307.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.38 181315[108:Spt:181310.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 181317[108:Res:181315.0,61.1] always3(s31) || -> . % 76.16/76.38 181318[108:SSi:181317.0,78205.0,78208.0,165523.0,180920.0,181305.0] || -> . % 76.16/76.38 181319[108:Spt:181318.0,181310.0,181315.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.38 181320[108:Spt:181318.0,181310.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 181324[108:Res:181320.0,61.1] always3(s32) || -> . % 76.16/76.38 181325[108:SSi:181324.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.38 181326[106:Spt:181325.0,180919.0,180920.0] || until2p7(s31)*+ -> . % 76.16/76.38 181327[106:Spt:181325.0,180919.1] || -> node4(s30)*. % 76.16/76.38 181329[106:MRR:828.0,181327.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.38 181332[106:Res:53.1,181329.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.38 181334[107:Spt:181332.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 181336[107:Res:181334.0,61.1] always3(s30) || -> . % 76.16/76.38 181337[107:SSi:181336.0,78200.0,78204.0,165522.0,180918.0,181327.0] || -> . % 76.16/76.38 181338[107:Spt:181337.0,181332.0,181334.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.38 181339[107:Spt:181337.0,181332.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 181343[107:Res:181339.0,61.1] always3(s31) || -> . % 76.16/76.38 181344[107:SSi:181343.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.38 181345[105:Spt:181344.0,180917.0,180918.0] || until2p7(s30)*+ -> . % 76.16/76.38 181346[105:Spt:181344.0,180917.1] || -> node4(s29)*. % 76.16/76.38 181348[105:MRR:831.0,181346.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.38 181351[105:Res:53.1,181348.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.38 181353[106:Spt:181351.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 181355[106:Res:181353.0,61.1] always3(s29) || -> . % 76.16/76.38 181356[106:SSi:181355.0,78196.0,78199.0,165521.0,180916.0,181346.0] || -> . % 76.16/76.38 181357[106:Spt:181356.0,181351.0,181353.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.38 181358[106:Spt:181356.0,181351.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 181362[106:Res:181358.0,61.1] always3(s30) || -> . % 76.16/76.38 181363[106:SSi:181362.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.38 181364[104:Spt:181363.0,180915.0,180916.0] || until2p7(s29)*+ -> . % 76.16/76.38 181365[104:Spt:181363.0,180915.1] || -> node4(s28)*. % 76.16/76.38 181367[104:MRR:834.0,181365.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.38 181370[104:Res:53.1,181367.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.38 181372[105:Spt:181370.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 181374[105:Res:181372.0,61.1] always3(s28) || -> . % 76.16/76.38 181375[105:SSi:181374.0,78191.0,78195.0,165520.0,180914.0,181365.0] || -> . % 76.16/76.38 181376[105:Spt:181375.0,181370.0,181372.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.38 181377[105:Spt:181375.0,181370.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 181381[105:Res:181377.0,61.1] always3(s29) || -> . % 76.16/76.38 181382[105:SSi:181381.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.38 181383[103:Spt:181382.0,180913.0,180914.0] || until2p7(s28)*+ -> . % 76.16/76.38 181384[103:Spt:181382.0,180913.1] || -> node4(s27)*. % 76.16/76.38 181386[103:MRR:837.0,181384.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.38 181389[103:Res:53.1,181386.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.38 181394[104:Spt:181389.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 181396[104:Res:181394.0,61.1] always3(s27) || -> . % 76.16/76.38 181397[104:SSi:181396.0,78187.0,78190.0,165519.0,180912.0,181384.0] || -> . % 76.16/76.38 181398[104:Spt:181397.0,181389.0,181394.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.38 181399[104:Spt:181397.0,181389.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 181403[104:Res:181399.0,61.1] always3(s28) || -> . % 76.16/76.38 181404[104:SSi:181403.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.38 181405[102:Spt:181404.0,180911.0,180912.0] || until2p7(s27)*+ -> . % 76.16/76.38 181406[102:Spt:181404.0,180911.1] || -> node4(s26)*. % 76.16/76.38 181408[102:MRR:840.0,181406.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.38 181411[102:Res:53.1,181408.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.38 181413[103:Spt:181411.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 181415[103:Res:181413.0,61.1] always3(s26) || -> . % 76.16/76.38 181416[103:SSi:181415.0,78182.0,78186.0,165518.0,180910.0,181406.0] || -> . % 76.16/76.38 181417[103:Spt:181416.0,181411.0,181413.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.38 181418[103:Spt:181416.0,181411.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 181422[103:Res:181418.0,61.1] always3(s27) || -> . % 76.16/76.38 181423[103:SSi:181422.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.38 181424[101:Spt:181423.0,180909.0,180910.0] || until2p7(s26)*+ -> . % 76.16/76.38 181425[101:Spt:181423.0,180909.1] || -> node4(s25)*. % 76.16/76.38 181427[101:MRR:843.0,181425.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.38 181430[101:Res:53.1,181427.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.38 181432[102:Spt:181430.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 181434[102:Res:181432.0,61.1] always3(s25) || -> . % 76.16/76.38 181435[102:SSi:181434.0,78178.0,78181.0,165517.0,180908.0,181425.0] || -> . % 76.16/76.38 181436[102:Spt:181435.0,181430.0,181432.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.38 181437[102:Spt:181435.0,181430.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 181441[102:Res:181437.0,61.1] always3(s26) || -> . % 76.16/76.38 181442[102:SSi:181441.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.38 181443[100:Spt:181442.0,180907.0,180908.0] || until2p7(s25)*+ -> . % 76.16/76.38 181444[100:Spt:181442.0,180907.1] || -> node4(s24)*. % 76.16/76.38 181446[100:MRR:846.0,181444.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.38 181449[100:Res:53.1,181446.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.38 181451[101:Spt:181449.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 181453[101:Res:181451.0,61.1] always3(s24) || -> . % 76.16/76.38 181454[101:SSi:181453.0,78173.0,78177.0,165516.0,180906.0,181444.0] || -> . % 76.16/76.38 181455[101:Spt:181454.0,181449.0,181451.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.38 181456[101:Spt:181454.0,181449.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 181460[101:Res:181456.0,61.1] always3(s25) || -> . % 76.16/76.38 181461[101:SSi:181460.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.38 181462[99:Spt:181461.0,180905.0,180906.0] || until2p7(s24)*+ -> . % 76.16/76.38 181463[99:Spt:181461.0,180905.1] || -> node4(s23)*. % 76.16/76.38 181465[99:MRR:849.0,181463.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.38 181468[99:Res:53.1,181465.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.38 181473[100:Spt:181468.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 181475[100:Res:181473.0,61.1] always3(s23) || -> . % 76.16/76.38 181476[100:SSi:181475.0,78169.0,78172.0,165515.0,180904.0,181463.0] || -> . % 76.16/76.38 181477[100:Spt:181476.0,181468.0,181473.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.38 181478[100:Spt:181476.0,181468.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 181482[100:Res:181478.0,61.1] always3(s24) || -> . % 76.16/76.38 181483[100:SSi:181482.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.38 181484[98:Spt:181483.0,180903.0,180904.0] || until2p7(s23)*+ -> . % 76.16/76.38 181485[98:Spt:181483.0,180903.1] || -> node4(s22)*. % 76.16/76.38 181487[98:MRR:852.0,181485.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.38 181490[98:Res:53.1,181487.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.38 181492[99:Spt:181490.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 181494[99:Res:181492.0,61.1] always3(s22) || -> . % 76.16/76.38 181495[99:SSi:181494.0,78164.0,78168.0,165514.0,180902.0,181485.0] || -> . % 76.16/76.38 181496[99:Spt:181495.0,181490.0,181492.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.38 181497[99:Spt:181495.0,181490.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 181501[99:Res:181497.0,61.1] always3(s23) || -> . % 76.16/76.38 181502[99:SSi:181501.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.38 181503[97:Spt:181502.0,180901.0,180902.0] || until2p7(s22)*+ -> . % 76.16/76.38 181504[97:Spt:181502.0,180901.1] || -> node4(s21)*. % 76.16/76.38 181506[97:MRR:855.0,181504.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.38 181509[97:Res:53.1,181506.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.38 181511[98:Spt:181509.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 181513[98:Res:181511.0,61.1] always3(s21) || -> . % 76.16/76.38 181514[98:SSi:181513.0,78160.0,78163.0,165513.0,180900.0,181504.0] || -> . % 76.16/76.38 181515[98:Spt:181514.0,181509.0,181511.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.38 181516[98:Spt:181514.0,181509.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 181520[98:Res:181516.0,61.1] always3(s22) || -> . % 76.16/76.38 181521[98:SSi:181520.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.38 181522[96:Spt:181521.0,180899.0,180900.0] || until2p7(s21)*+ -> . % 76.16/76.38 181523[96:Spt:181521.0,180899.1] || -> node4(s20)*. % 76.16/76.38 181525[96:MRR:858.0,181523.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.38 181528[96:Res:53.1,181525.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.38 181530[97:Spt:181528.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 181532[97:Res:181530.0,61.1] always3(s20) || -> . % 76.16/76.38 181533[97:SSi:181532.0,78155.0,78159.0,165512.0,180898.0,181523.0] || -> . % 76.16/76.38 181534[97:Spt:181533.0,181528.0,181530.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.38 181535[97:Spt:181533.0,181528.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 181539[97:Res:181535.0,61.1] always3(s21) || -> . % 76.16/76.38 181540[97:SSi:181539.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.38 181541[95:Spt:181540.0,180897.0,180898.0] || until2p7(s20)*+ -> . % 76.16/76.38 181542[95:Spt:181540.0,180897.1] || -> node4(s19)*. % 76.16/76.38 181544[95:MRR:861.0,181542.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.38 181547[95:Res:53.1,181544.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.38 181552[96:Spt:181547.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 181554[96:Res:181552.0,61.1] always3(s19) || -> . % 76.16/76.38 181555[96:SSi:181554.0,78151.0,78154.0,165511.0,180896.0,181542.0] || -> . % 76.16/76.38 181556[96:Spt:181555.0,181547.0,181552.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.38 181557[96:Spt:181555.0,181547.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 181561[96:Res:181557.0,61.1] always3(s20) || -> . % 76.16/76.38 181562[96:SSi:181561.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.38 181563[94:Spt:181562.0,180895.0,180896.0] || until2p7(s19)*+ -> . % 76.16/76.38 181564[94:Spt:181562.0,180895.1] || -> node4(s18)*. % 76.16/76.38 181566[94:MRR:864.0,181564.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.38 181569[94:Res:53.1,181566.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.38 181571[95:Spt:181569.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 181573[95:Res:181571.0,61.1] always3(s18) || -> . % 76.16/76.38 181574[95:SSi:181573.0,78146.0,78150.0,165510.0,180894.0,181564.0] || -> . % 76.16/76.38 181575[95:Spt:181574.0,181569.0,181571.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.38 181576[95:Spt:181574.0,181569.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 181580[95:Res:181576.0,61.1] always3(s19) || -> . % 76.16/76.38 181581[95:SSi:181580.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.38 181582[93:Spt:181581.0,180893.0,180894.0] || until2p7(s18)*+ -> . % 76.16/76.38 181583[93:Spt:181581.0,180893.1] || -> node4(s17)*. % 76.16/76.38 181585[93:MRR:867.0,181583.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.38 181588[93:Res:53.1,181585.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.38 181590[94:Spt:181588.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 181592[94:Res:181590.0,61.1] always3(s17) || -> . % 76.16/76.38 181593[94:SSi:181592.0,78142.0,78145.0,165509.0,180892.0,181583.0] || -> . % 76.16/76.38 181594[94:Spt:181593.0,181588.0,181590.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.38 181595[94:Spt:181593.0,181588.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 181599[94:Res:181595.0,61.1] always3(s18) || -> . % 76.16/76.38 181600[94:SSi:181599.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.38 181601[92:Spt:181600.0,180891.0,180892.0] || until2p7(s17)*+ -> . % 76.16/76.38 181602[92:Spt:181600.0,180891.1] || -> node4(s16)*. % 76.16/76.38 181604[92:MRR:870.0,181602.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.38 181607[92:Res:53.1,181604.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.38 181609[93:Spt:181607.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 181611[93:Res:181609.0,61.1] always3(s16) || -> . % 76.16/76.38 181612[93:SSi:181611.0,78137.0,78141.0,165508.0,180890.0,181602.0] || -> . % 76.16/76.38 181613[93:Spt:181612.0,181607.0,181609.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.38 181614[93:Spt:181612.0,181607.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 181618[93:Res:181614.0,61.1] always3(s17) || -> . % 76.16/76.38 181619[93:SSi:181618.0,78142.0,78145.0,165509.0] || -> . % 76.16/76.38 181620[91:Spt:181619.0,180889.0,180890.0] || until2p7(s16)*+ -> . % 76.16/76.38 181621[91:Spt:181619.0,180889.1] || -> node4(s15)*. % 76.16/76.38 181623[91:MRR:873.0,181621.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.38 181626[91:Res:53.1,181623.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.38 181628[91:MRR:181626.0,180879.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 181633[91:Res:181628.0,61.1] always3(s16) || -> . % 76.16/76.38 181634[91:SSi:181633.0,78137.0,78141.0,165508.0] || -> . % 76.16/76.38 181635[89:Spt:181634.0,180748.0,180751.0] || trans(s49,s15)*+ -> . % 76.16/76.38 181636[89:Spt:181634.0,180748.1,180748.2,180748.3,180748.4,180748.5,180748.6,180748.7,180748.8,180748.9,180748.10] || -> trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.38 181638[89:MRR:180750.1,181635.0] xuntil6(s49) || -> trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.38 181639[90:Spt:181636.0] || -> trans(s49,s14)*. % 76.16/76.38 181640[90:Res:181639.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s14)*. % 76.16/76.38 181642[90:Res:181639.0,60.0] || -> node2(s49,s14)*. % 76.16/76.38 181643[90:SSi:181640.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s14)*. % 76.16/76.38 181644[90:Res:181642.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 181760[90:SoR:181644.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 181762[90:SoR:181760.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)* xuntil6(s49). % 76.16/76.38 181763[90:SSi:181762.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s14,c_busy)* xuntil6(s49). % 76.16/76.38 181764[91:Spt:181763.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 181766[91:Res:181764.0,61.1] always3(s14) || -> . % 76.16/76.38 181767[91:SSi:181766.0,78128.0,78132.0,165506.0] || -> . % 76.16/76.38 181768[91:Spt:181767.0,181763.1,181764.0] || m_main_v_state(s14,c_busy)*+ -> . % 76.16/76.38 181769[91:Spt:181767.0,181763.0,181763.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.38 181773[91:MRR:181760.2,181768.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.38 181774[91:Res:53.1,181769.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.38 181776[91:MRR:181774.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.38 181777[91:MRR:181643.0,181776.0] || -> until2p7(s14)*. % 76.16/76.38 181778[91:MRR:210.0,181777.0] || -> until2p7(s15)* node4(s14). % 76.16/76.38 181779[92:Spt:181778.0] || -> until2p7(s15)*. % 76.16/76.38 181780[92:MRR:211.0,181779.0] || -> until2p7(s16)* node4(s15). % 76.16/76.38 181781[93:Spt:181780.0] || -> until2p7(s16)*. % 76.16/76.38 181782[93:MRR:212.0,181781.0] || -> until2p7(s17)* node4(s16). % 76.16/76.38 181783[94:Spt:181782.0] || -> until2p7(s17)*. % 76.16/76.38 181784[94:MRR:213.0,181783.0] || -> until2p7(s18)* node4(s17). % 76.16/76.38 181785[95:Spt:181784.0] || -> until2p7(s18)*. % 76.16/76.38 181786[95:MRR:214.0,181785.0] || -> until2p7(s19)* node4(s18). % 76.16/76.38 181787[96:Spt:181786.0] || -> until2p7(s19)*. % 76.16/76.38 181788[96:MRR:215.0,181787.0] || -> until2p7(s20)* node4(s19). % 76.16/76.38 181789[97:Spt:181788.0] || -> until2p7(s20)*. % 76.16/76.38 181790[97:MRR:216.0,181789.0] || -> until2p7(s21)* node4(s20). % 76.16/76.38 181791[98:Spt:181790.0] || -> until2p7(s21)*. % 76.16/76.38 181792[98:MRR:217.0,181791.0] || -> until2p7(s22)* node4(s21). % 76.16/76.38 181793[99:Spt:181792.0] || -> until2p7(s22)*. % 76.16/76.38 181794[99:MRR:218.0,181793.0] || -> until2p7(s23)* node4(s22). % 76.16/76.38 181795[100:Spt:181794.0] || -> until2p7(s23)*. % 76.16/76.38 181796[100:MRR:219.0,181795.0] || -> until2p7(s24)* node4(s23). % 76.16/76.38 181797[101:Spt:181796.0] || -> until2p7(s24)*. % 76.16/76.38 181798[101:MRR:220.0,181797.0] || -> until2p7(s25)* node4(s24). % 76.16/76.38 181799[102:Spt:181798.0] || -> until2p7(s25)*. % 76.16/76.38 181800[102:MRR:221.0,181799.0] || -> until2p7(s26)* node4(s25). % 76.16/76.38 181801[103:Spt:181800.0] || -> until2p7(s26)*. % 76.16/76.38 181802[103:MRR:222.0,181801.0] || -> until2p7(s27)* node4(s26). % 76.16/76.38 181803[104:Spt:181802.0] || -> until2p7(s27)*. % 76.16/76.38 181804[104:MRR:223.0,181803.0] || -> until2p7(s28)* node4(s27). % 76.16/76.38 181805[105:Spt:181804.0] || -> until2p7(s28)*. % 76.16/76.38 181806[105:MRR:224.0,181805.0] || -> until2p7(s29)* node4(s28). % 76.16/76.38 181807[106:Spt:181806.0] || -> until2p7(s29)*. % 76.16/76.38 181808[106:MRR:225.0,181807.0] || -> until2p7(s30)* node4(s29). % 76.16/76.38 181809[107:Spt:181808.0] || -> until2p7(s30)*. % 76.16/76.38 181810[107:MRR:226.0,181809.0] || -> until2p7(s31)* node4(s30). % 76.16/76.38 181811[108:Spt:181810.0] || -> until2p7(s31)*. % 76.16/76.38 181812[108:MRR:227.0,181811.0] || -> until2p7(s32)* node4(s31). % 76.16/76.38 181813[109:Spt:181812.0] || -> until2p7(s32)*. % 76.16/76.38 181814[109:MRR:228.0,181813.0] || -> until2p7(s33)* node4(s32). % 76.16/76.38 181815[110:Spt:181814.0] || -> until2p7(s33)*. % 76.16/76.38 181816[110:MRR:229.0,181815.0] || -> until2p7(s34)* node4(s33). % 76.16/76.38 181817[111:Spt:181816.0] || -> until2p7(s34)*. % 76.16/76.38 181818[111:MRR:230.0,181817.0] || -> until2p7(s35)* node4(s34). % 76.16/76.38 181819[112:Spt:181818.0] || -> until2p7(s35)*. % 76.16/76.38 181820[112:MRR:231.0,181819.0] || -> until2p7(s36)* node4(s35). % 76.16/76.38 181821[113:Spt:181820.0] || -> until2p7(s36)*. % 76.16/76.38 181822[113:MRR:232.0,181821.0] || -> until2p7(s37)* node4(s36). % 76.16/76.38 181823[114:Spt:181822.0] || -> until2p7(s37)*. % 76.16/76.38 181824[114:MRR:235.0,181823.0] || -> until2p7(s38)* node4(s37). % 76.16/76.38 181825[115:Spt:181824.0] || -> until2p7(s38)*. % 76.16/76.38 181826[115:MRR:236.0,181825.0] || -> until2p7(s39)* node4(s38). % 76.16/76.38 181827[116:Spt:181826.0] || -> until2p7(s39)*. % 76.16/76.38 181828[116:MRR:237.0,181827.0] || -> until2p7(s40)* node4(s39). % 76.16/76.38 181829[117:Spt:181828.0] || -> until2p7(s40)*. % 76.16/76.38 181830[117:MRR:238.0,181829.0] || -> until2p7(s41)* node4(s40). % 76.16/76.38 181831[118:Spt:181830.0] || -> until2p7(s41)*. % 76.16/76.38 181832[118:MRR:239.0,181831.0] || -> until2p7(s42)* node4(s41). % 76.16/76.38 181833[119:Spt:181832.0] || -> until2p7(s42)*. % 76.16/76.38 181834[119:MRR:240.0,181833.0] || -> until2p7(s43)* node4(s42). % 76.16/76.38 181835[120:Spt:181834.0] || -> until2p7(s43)*. % 76.16/76.38 181836[120:MRR:241.0,181835.0] || -> until2p7(s44)* node4(s43). % 76.16/76.38 181837[121:Spt:181836.0] || -> until2p7(s44)*. % 76.16/76.38 181838[121:MRR:539.0,181837.0] || -> until2p7(s45)* node4(s44). % 76.16/76.38 181839[122:Spt:181838.0] || -> until2p7(s45)*. % 76.16/76.38 181840[122:MRR:544.0,181839.0] || -> until2p7(s46)* node4(s45). % 76.16/76.38 181841[123:Spt:181840.0] || -> until2p7(s46)*. % 76.16/76.38 181842[123:MRR:549.0,181841.0] || -> until2p7(s47)* node4(s46). % 76.16/76.38 181843[124:Spt:181842.0] || -> until2p7(s47)*. % 76.16/76.38 181844[124:MRR:554.0,181843.0] || -> until2p7(s48)* node4(s47). % 76.16/76.38 181845[125:Spt:181844.0] || -> until2p7(s48)*. % 76.16/76.38 181846[125:MRR:559.0,181845.0] || -> until2p7(s49)* node4(s48). % 76.16/76.38 181847[126:Spt:181846.0] || -> until2p7(s49)*. % 76.16/76.38 181848[126:MRR:194.0,181847.0] || -> node4(s49)*. % 76.16/76.38 181849[126:MRR:181773.0,181848.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.38 181850[126:Res:53.1,181849.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.38 181852[126:MRR:181850.0,78381.0] || -> . % 76.16/76.38 181853[126:Spt:181852.0,181846.0,181847.0] || until2p7(s49)*+ -> . % 76.16/76.38 181854[126:Spt:181852.0,181846.1] || -> node4(s48)*. % 76.16/76.38 181855[126:MRR:78384.0,181854.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.38 181858[126:Res:53.1,181855.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 181861[126:Res:181858.0,61.1] always3(s48) || -> . % 76.16/76.38 181862[126:SSi:181861.0,78281.0,78387.0,165540.0,181845.0,181854.0] || -> . % 76.16/76.38 181863[125:Spt:181862.0,181844.0,181845.0] || until2p7(s48)*+ -> . % 76.16/76.38 181864[125:Spt:181862.0,181844.1] || -> node4(s47)*. % 76.16/76.38 181866[125:MRR:777.0,181864.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.38 181881[125:Res:53.1,181866.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.38 181883[126:Spt:181881.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 181885[126:Res:181883.0,61.1] always3(s47) || -> . % 76.16/76.38 181886[126:SSi:181885.0,78277.0,78280.0,165539.0,181843.0,181864.0] || -> . % 76.16/76.38 181887[126:Spt:181886.0,181881.0,181883.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.38 181888[126:Spt:181886.0,181881.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 181892[126:Res:181888.0,61.1] always3(s48) || -> . % 76.16/76.38 181893[126:SSi:181892.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.38 181894[124:Spt:181893.0,181842.0,181843.0] || until2p7(s47)*+ -> . % 76.16/76.38 181895[124:Spt:181893.0,181842.1] || -> node4(s46)*. % 76.16/76.38 181897[124:MRR:780.0,181895.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.38 181907[124:Res:53.1,181897.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.38 181909[125:Spt:181907.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 181911[125:Res:181909.0,61.1] always3(s46) || -> . % 76.16/76.38 181912[125:SSi:181911.0,78272.0,78276.0,165538.0,181841.0,181895.0] || -> . % 76.16/76.38 181913[125:Spt:181912.0,181907.0,181909.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.38 181914[125:Spt:181912.0,181907.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 181918[125:Res:181914.0,61.1] always3(s47) || -> . % 76.16/76.38 181919[125:SSi:181918.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.38 181920[123:Spt:181919.0,181840.0,181841.0] || until2p7(s46)*+ -> . % 76.16/76.38 181921[123:Spt:181919.0,181840.1] || -> node4(s45)*. % 76.16/76.38 181923[123:MRR:783.0,181921.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.38 181926[123:Res:53.1,181923.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.38 181928[124:Spt:181926.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 181930[124:Res:181928.0,61.1] always3(s45) || -> . % 76.16/76.38 181931[124:SSi:181930.0,78268.0,78271.0,165537.0,181839.0,181921.0] || -> . % 76.16/76.38 181932[124:Spt:181931.0,181926.0,181928.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.38 181933[124:Spt:181931.0,181926.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 181937[124:Res:181933.0,61.1] always3(s46) || -> . % 76.16/76.38 181938[124:SSi:181937.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.38 181939[122:Spt:181938.0,181838.0,181839.0] || until2p7(s45)*+ -> . % 76.16/76.38 181940[122:Spt:181938.0,181838.1] || -> node4(s44)*. % 76.16/76.38 181942[122:MRR:786.0,181940.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.38 181945[122:Res:53.1,181942.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.38 181947[123:Spt:181945.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 181949[123:Res:181947.0,61.1] always3(s44) || -> . % 76.16/76.38 181950[123:SSi:181949.0,78263.0,78267.0,165536.0,181837.0,181940.0] || -> . % 76.16/76.38 181951[123:Spt:181950.0,181945.0,181947.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.38 181952[123:Spt:181950.0,181945.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 181956[123:Res:181952.0,61.1] always3(s45) || -> . % 76.16/76.38 181957[123:SSi:181956.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.38 181958[121:Spt:181957.0,181836.0,181837.0] || until2p7(s44)*+ -> . % 76.16/76.38 181959[121:Spt:181957.0,181836.1] || -> node4(s43)*. % 76.16/76.38 181961[121:MRR:789.0,181959.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.38 181964[121:Res:53.1,181961.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.38 181969[122:Spt:181964.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 181971[122:Res:181969.0,61.1] always3(s43) || -> . % 76.16/76.38 181972[122:SSi:181971.0,78259.0,78262.0,165535.0,181835.0,181959.0] || -> . % 76.16/76.38 181973[122:Spt:181972.0,181964.0,181969.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.38 181974[122:Spt:181972.0,181964.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 181978[122:Res:181974.0,61.1] always3(s44) || -> . % 76.16/76.38 181979[122:SSi:181978.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.38 181980[120:Spt:181979.0,181834.0,181835.0] || until2p7(s43)*+ -> . % 76.16/76.38 181981[120:Spt:181979.0,181834.1] || -> node4(s42)*. % 76.16/76.38 181983[120:MRR:792.0,181981.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.38 181986[120:Res:53.1,181983.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.38 181988[121:Spt:181986.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 181990[121:Res:181988.0,61.1] always3(s42) || -> . % 76.16/76.38 181991[121:SSi:181990.0,78254.0,78258.0,165534.0,181833.0,181981.0] || -> . % 76.16/76.38 181992[121:Spt:181991.0,181986.0,181988.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.38 181993[121:Spt:181991.0,181986.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 181997[121:Res:181993.0,61.1] always3(s43) || -> . % 76.16/76.38 181998[121:SSi:181997.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.38 181999[119:Spt:181998.0,181832.0,181833.0] || until2p7(s42)*+ -> . % 76.16/76.38 182000[119:Spt:181998.0,181832.1] || -> node4(s41)*. % 76.16/76.38 182002[119:MRR:795.0,182000.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.38 182005[119:Res:53.1,182002.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.38 182007[120:Spt:182005.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 182009[120:Res:182007.0,61.1] always3(s41) || -> . % 76.16/76.38 182010[120:SSi:182009.0,78250.0,78253.0,165533.0,181831.0,182000.0] || -> . % 76.16/76.38 182011[120:Spt:182010.0,182005.0,182007.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.38 182012[120:Spt:182010.0,182005.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 182016[120:Res:182012.0,61.1] always3(s42) || -> . % 76.16/76.38 182017[120:SSi:182016.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.38 182018[118:Spt:182017.0,181830.0,181831.0] || until2p7(s41)*+ -> . % 76.16/76.38 182019[118:Spt:182017.0,181830.1] || -> node4(s40)*. % 76.16/76.38 182021[118:MRR:798.0,182019.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.38 182024[118:Res:53.1,182021.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.38 182026[119:Spt:182024.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 182028[119:Res:182026.0,61.1] always3(s40) || -> . % 76.16/76.38 182029[119:SSi:182028.0,78245.0,78249.0,165532.0,181829.0,182019.0] || -> . % 76.16/76.38 182030[119:Spt:182029.0,182024.0,182026.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.38 182031[119:Spt:182029.0,182024.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 182035[119:Res:182031.0,61.1] always3(s41) || -> . % 76.16/76.38 182036[119:SSi:182035.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.38 182037[117:Spt:182036.0,181828.0,181829.0] || until2p7(s40)*+ -> . % 76.16/76.38 182038[117:Spt:182036.0,181828.1] || -> node4(s39)*. % 76.16/76.38 182040[117:MRR:801.0,182038.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.38 182043[117:Res:53.1,182040.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.38 182048[118:Spt:182043.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 182050[118:Res:182048.0,61.1] always3(s39) || -> . % 76.16/76.38 182051[118:SSi:182050.0,78241.0,78244.0,165531.0,181827.0,182038.0] || -> . % 76.16/76.38 182052[118:Spt:182051.0,182043.0,182048.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.38 182053[118:Spt:182051.0,182043.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 182057[118:Res:182053.0,61.1] always3(s40) || -> . % 76.16/76.38 182058[118:SSi:182057.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.38 182059[116:Spt:182058.0,181826.0,181827.0] || until2p7(s39)*+ -> . % 76.16/76.38 182060[116:Spt:182058.0,181826.1] || -> node4(s38)*. % 76.16/76.38 182062[116:MRR:804.0,182060.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.38 182065[116:Res:53.1,182062.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.38 182067[117:Spt:182065.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 182069[117:Res:182067.0,61.1] always3(s38) || -> . % 76.16/76.38 182070[117:SSi:182069.0,78236.0,78240.0,165530.0,181825.0,182060.0] || -> . % 76.16/76.38 182071[117:Spt:182070.0,182065.0,182067.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.38 182072[117:Spt:182070.0,182065.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 182076[117:Res:182072.0,61.1] always3(s39) || -> . % 76.16/76.38 182077[117:SSi:182076.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.38 182078[115:Spt:182077.0,181824.0,181825.0] || until2p7(s38)*+ -> . % 76.16/76.38 182079[115:Spt:182077.0,181824.1] || -> node4(s37)*. % 76.16/76.38 182081[115:MRR:807.0,182079.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.38 182084[115:Res:53.1,182081.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.38 182086[116:Spt:182084.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 182088[116:Res:182086.0,61.1] always3(s37) || -> . % 76.16/76.38 182089[116:SSi:182088.0,78232.0,78235.0,165529.0,181823.0,182079.0] || -> . % 76.16/76.38 182090[116:Spt:182089.0,182084.0,182086.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.38 182091[116:Spt:182089.0,182084.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 182095[116:Res:182091.0,61.1] always3(s38) || -> . % 76.16/76.38 182096[116:SSi:182095.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.38 182097[114:Spt:182096.0,181822.0,181823.0] || until2p7(s37)*+ -> . % 76.16/76.38 182098[114:Spt:182096.0,181822.1] || -> node4(s36)*. % 76.16/76.38 182100[114:MRR:810.0,182098.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.38 182103[114:Res:53.1,182100.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.38 182105[115:Spt:182103.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 182107[115:Res:182105.0,61.1] always3(s36) || -> . % 76.16/76.38 182108[115:SSi:182107.0,78227.0,78231.0,165528.0,181821.0,182098.0] || -> . % 76.16/76.38 182109[115:Spt:182108.0,182103.0,182105.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.38 182110[115:Spt:182108.0,182103.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 182114[115:Res:182110.0,61.1] always3(s37) || -> . % 76.16/76.38 182115[115:SSi:182114.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.38 182116[113:Spt:182115.0,181820.0,181821.0] || until2p7(s36)*+ -> . % 76.16/76.38 182117[113:Spt:182115.0,181820.1] || -> node4(s35)*. % 76.16/76.38 182119[113:MRR:813.0,182117.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.38 182122[113:Res:53.1,182119.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.38 182127[114:Spt:182122.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 182129[114:Res:182127.0,61.1] always3(s35) || -> . % 76.16/76.38 182130[114:SSi:182129.0,78223.0,78226.0,165527.0,181819.0,182117.0] || -> . % 76.16/76.38 182131[114:Spt:182130.0,182122.0,182127.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.38 182132[114:Spt:182130.0,182122.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 182136[114:Res:182132.0,61.1] always3(s36) || -> . % 76.16/76.38 182137[114:SSi:182136.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.38 182138[112:Spt:182137.0,181818.0,181819.0] || until2p7(s35)*+ -> . % 76.16/76.38 182139[112:Spt:182137.0,181818.1] || -> node4(s34)*. % 76.16/76.38 182141[112:MRR:816.0,182139.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.38 182144[112:Res:53.1,182141.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.38 182146[113:Spt:182144.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 182148[113:Res:182146.0,61.1] always3(s34) || -> . % 76.16/76.38 182149[113:SSi:182148.0,78218.0,78222.0,165526.0,181817.0,182139.0] || -> . % 76.16/76.38 182150[113:Spt:182149.0,182144.0,182146.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.38 182151[113:Spt:182149.0,182144.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 182155[113:Res:182151.0,61.1] always3(s35) || -> . % 76.16/76.38 182156[113:SSi:182155.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.38 182157[111:Spt:182156.0,181816.0,181817.0] || until2p7(s34)*+ -> . % 76.16/76.38 182158[111:Spt:182156.0,181816.1] || -> node4(s33)*. % 76.16/76.38 182160[111:MRR:819.0,182158.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.38 182163[111:Res:53.1,182160.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.38 182165[112:Spt:182163.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 182167[112:Res:182165.0,61.1] always3(s33) || -> . % 76.16/76.38 182168[112:SSi:182167.0,78214.0,78217.0,165525.0,181815.0,182158.0] || -> . % 76.16/76.38 182169[112:Spt:182168.0,182163.0,182165.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.38 182170[112:Spt:182168.0,182163.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 182174[112:Res:182170.0,61.1] always3(s34) || -> . % 76.16/76.38 182175[112:SSi:182174.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.38 182176[110:Spt:182175.0,181814.0,181815.0] || until2p7(s33)*+ -> . % 76.16/76.38 182177[110:Spt:182175.0,181814.1] || -> node4(s32)*. % 76.16/76.38 182179[110:MRR:822.0,182177.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.38 182182[110:Res:53.1,182179.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.38 182184[111:Spt:182182.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 182186[111:Res:182184.0,61.1] always3(s32) || -> . % 76.16/76.38 182187[111:SSi:182186.0,78209.0,78213.0,165524.0,181813.0,182177.0] || -> . % 76.16/76.38 182188[111:Spt:182187.0,182182.0,182184.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.38 182189[111:Spt:182187.0,182182.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 182193[111:Res:182189.0,61.1] always3(s33) || -> . % 76.16/76.38 182194[111:SSi:182193.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.38 182195[109:Spt:182194.0,181812.0,181813.0] || until2p7(s32)*+ -> . % 76.16/76.38 182196[109:Spt:182194.0,181812.1] || -> node4(s31)*. % 76.16/76.38 182198[109:MRR:825.0,182196.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.38 182201[109:Res:53.1,182198.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.38 182206[110:Spt:182201.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 182208[110:Res:182206.0,61.1] always3(s31) || -> . % 76.16/76.38 182209[110:SSi:182208.0,78205.0,78208.0,165523.0,181811.0,182196.0] || -> . % 76.16/76.38 182210[110:Spt:182209.0,182201.0,182206.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.38 182211[110:Spt:182209.0,182201.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 182215[110:Res:182211.0,61.1] always3(s32) || -> . % 76.16/76.38 182216[110:SSi:182215.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.38 182217[108:Spt:182216.0,181810.0,181811.0] || until2p7(s31)*+ -> . % 76.16/76.38 182218[108:Spt:182216.0,181810.1] || -> node4(s30)*. % 76.16/76.38 182220[108:MRR:828.0,182218.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.38 182223[108:Res:53.1,182220.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.38 182225[109:Spt:182223.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 182227[109:Res:182225.0,61.1] always3(s30) || -> . % 76.16/76.38 182228[109:SSi:182227.0,78200.0,78204.0,165522.0,181809.0,182218.0] || -> . % 76.16/76.38 182229[109:Spt:182228.0,182223.0,182225.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.38 182230[109:Spt:182228.0,182223.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 182234[109:Res:182230.0,61.1] always3(s31) || -> . % 76.16/76.38 182235[109:SSi:182234.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.38 182236[107:Spt:182235.0,181808.0,181809.0] || until2p7(s30)*+ -> . % 76.16/76.38 182237[107:Spt:182235.0,181808.1] || -> node4(s29)*. % 76.16/76.38 182239[107:MRR:831.0,182237.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.38 182242[107:Res:53.1,182239.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.38 182244[108:Spt:182242.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 182246[108:Res:182244.0,61.1] always3(s29) || -> . % 76.16/76.38 182247[108:SSi:182246.0,78196.0,78199.0,165521.0,181807.0,182237.0] || -> . % 76.16/76.38 182248[108:Spt:182247.0,182242.0,182244.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.38 182249[108:Spt:182247.0,182242.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 182253[108:Res:182249.0,61.1] always3(s30) || -> . % 76.16/76.38 182254[108:SSi:182253.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.38 182255[106:Spt:182254.0,181806.0,181807.0] || until2p7(s29)*+ -> . % 76.16/76.38 182256[106:Spt:182254.0,181806.1] || -> node4(s28)*. % 76.16/76.38 182258[106:MRR:834.0,182256.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.38 182261[106:Res:53.1,182258.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.38 182263[107:Spt:182261.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 182265[107:Res:182263.0,61.1] always3(s28) || -> . % 76.16/76.38 182266[107:SSi:182265.0,78191.0,78195.0,165520.0,181805.0,182256.0] || -> . % 76.16/76.38 182267[107:Spt:182266.0,182261.0,182263.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.38 182268[107:Spt:182266.0,182261.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 182272[107:Res:182268.0,61.1] always3(s29) || -> . % 76.16/76.38 182273[107:SSi:182272.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.38 182274[105:Spt:182273.0,181804.0,181805.0] || until2p7(s28)*+ -> . % 76.16/76.38 182275[105:Spt:182273.0,181804.1] || -> node4(s27)*. % 76.16/76.38 182277[105:MRR:837.0,182275.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.38 182280[105:Res:53.1,182277.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.38 182285[106:Spt:182280.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 182287[106:Res:182285.0,61.1] always3(s27) || -> . % 76.16/76.38 182288[106:SSi:182287.0,78187.0,78190.0,165519.0,181803.0,182275.0] || -> . % 76.16/76.38 182289[106:Spt:182288.0,182280.0,182285.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.38 182290[106:Spt:182288.0,182280.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 182294[106:Res:182290.0,61.1] always3(s28) || -> . % 76.16/76.38 182295[106:SSi:182294.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.38 182296[104:Spt:182295.0,181802.0,181803.0] || until2p7(s27)*+ -> . % 76.16/76.38 182297[104:Spt:182295.0,181802.1] || -> node4(s26)*. % 76.16/76.38 182299[104:MRR:840.0,182297.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.38 182302[104:Res:53.1,182299.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.38 182304[105:Spt:182302.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 182306[105:Res:182304.0,61.1] always3(s26) || -> . % 76.16/76.38 182307[105:SSi:182306.0,78182.0,78186.0,165518.0,181801.0,182297.0] || -> . % 76.16/76.38 182308[105:Spt:182307.0,182302.0,182304.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.38 182309[105:Spt:182307.0,182302.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 182313[105:Res:182309.0,61.1] always3(s27) || -> . % 76.16/76.38 182314[105:SSi:182313.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.38 182315[103:Spt:182314.0,181800.0,181801.0] || until2p7(s26)*+ -> . % 76.16/76.38 182316[103:Spt:182314.0,181800.1] || -> node4(s25)*. % 76.16/76.38 182318[103:MRR:843.0,182316.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.38 182321[103:Res:53.1,182318.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.38 182323[104:Spt:182321.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 182325[104:Res:182323.0,61.1] always3(s25) || -> . % 76.16/76.38 182326[104:SSi:182325.0,78178.0,78181.0,165517.0,181799.0,182316.0] || -> . % 76.16/76.38 182327[104:Spt:182326.0,182321.0,182323.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.38 182328[104:Spt:182326.0,182321.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 182332[104:Res:182328.0,61.1] always3(s26) || -> . % 76.16/76.38 182333[104:SSi:182332.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.38 182334[102:Spt:182333.0,181798.0,181799.0] || until2p7(s25)*+ -> . % 76.16/76.38 182335[102:Spt:182333.0,181798.1] || -> node4(s24)*. % 76.16/76.38 182337[102:MRR:846.0,182335.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.38 182340[102:Res:53.1,182337.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.38 182342[103:Spt:182340.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 182344[103:Res:182342.0,61.1] always3(s24) || -> . % 76.16/76.38 182345[103:SSi:182344.0,78173.0,78177.0,165516.0,181797.0,182335.0] || -> . % 76.16/76.38 182346[103:Spt:182345.0,182340.0,182342.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.38 182347[103:Spt:182345.0,182340.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 182351[103:Res:182347.0,61.1] always3(s25) || -> . % 76.16/76.38 182352[103:SSi:182351.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.38 182353[101:Spt:182352.0,181796.0,181797.0] || until2p7(s24)*+ -> . % 76.16/76.38 182354[101:Spt:182352.0,181796.1] || -> node4(s23)*. % 76.16/76.38 182356[101:MRR:849.0,182354.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.38 182359[101:Res:53.1,182356.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.38 182364[102:Spt:182359.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 182366[102:Res:182364.0,61.1] always3(s23) || -> . % 76.16/76.38 182367[102:SSi:182366.0,78169.0,78172.0,165515.0,181795.0,182354.0] || -> . % 76.16/76.38 182368[102:Spt:182367.0,182359.0,182364.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.38 182369[102:Spt:182367.0,182359.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 182373[102:Res:182369.0,61.1] always3(s24) || -> . % 76.16/76.38 182374[102:SSi:182373.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.38 182375[100:Spt:182374.0,181794.0,181795.0] || until2p7(s23)*+ -> . % 76.16/76.38 182376[100:Spt:182374.0,181794.1] || -> node4(s22)*. % 76.16/76.38 182378[100:MRR:852.0,182376.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.38 182381[100:Res:53.1,182378.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.38 182383[101:Spt:182381.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 182385[101:Res:182383.0,61.1] always3(s22) || -> . % 76.16/76.38 182386[101:SSi:182385.0,78164.0,78168.0,165514.0,181793.0,182376.0] || -> . % 76.16/76.38 182387[101:Spt:182386.0,182381.0,182383.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.38 182388[101:Spt:182386.0,182381.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 182392[101:Res:182388.0,61.1] always3(s23) || -> . % 76.16/76.38 182393[101:SSi:182392.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.38 182394[99:Spt:182393.0,181792.0,181793.0] || until2p7(s22)*+ -> . % 76.16/76.38 182395[99:Spt:182393.0,181792.1] || -> node4(s21)*. % 76.16/76.38 182397[99:MRR:855.0,182395.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.38 182400[99:Res:53.1,182397.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.38 182402[100:Spt:182400.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 182404[100:Res:182402.0,61.1] always3(s21) || -> . % 76.16/76.38 182405[100:SSi:182404.0,78160.0,78163.0,165513.0,181791.0,182395.0] || -> . % 76.16/76.38 182406[100:Spt:182405.0,182400.0,182402.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.38 182407[100:Spt:182405.0,182400.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 182411[100:Res:182407.0,61.1] always3(s22) || -> . % 76.16/76.38 182412[100:SSi:182411.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.38 182413[98:Spt:182412.0,181790.0,181791.0] || until2p7(s21)*+ -> . % 76.16/76.38 182414[98:Spt:182412.0,181790.1] || -> node4(s20)*. % 76.16/76.38 182416[98:MRR:858.0,182414.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.38 182419[98:Res:53.1,182416.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.38 182421[99:Spt:182419.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 182423[99:Res:182421.0,61.1] always3(s20) || -> . % 76.16/76.38 182424[99:SSi:182423.0,78155.0,78159.0,165512.0,181789.0,182414.0] || -> . % 76.16/76.38 182425[99:Spt:182424.0,182419.0,182421.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.38 182426[99:Spt:182424.0,182419.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 182430[99:Res:182426.0,61.1] always3(s21) || -> . % 76.16/76.38 182431[99:SSi:182430.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.38 182432[97:Spt:182431.0,181788.0,181789.0] || until2p7(s20)*+ -> . % 76.16/76.38 182433[97:Spt:182431.0,181788.1] || -> node4(s19)*. % 76.16/76.38 182435[97:MRR:861.0,182433.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.38 182438[97:Res:53.1,182435.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.38 182443[98:Spt:182438.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 182445[98:Res:182443.0,61.1] always3(s19) || -> . % 76.16/76.38 182446[98:SSi:182445.0,78151.0,78154.0,165511.0,181787.0,182433.0] || -> . % 76.16/76.38 182447[98:Spt:182446.0,182438.0,182443.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.38 182448[98:Spt:182446.0,182438.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 182452[98:Res:182448.0,61.1] always3(s20) || -> . % 76.16/76.38 182453[98:SSi:182452.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.38 182454[96:Spt:182453.0,181786.0,181787.0] || until2p7(s19)*+ -> . % 76.16/76.38 182455[96:Spt:182453.0,181786.1] || -> node4(s18)*. % 76.16/76.38 182457[96:MRR:864.0,182455.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.38 182460[96:Res:53.1,182457.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.38 182462[97:Spt:182460.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 182464[97:Res:182462.0,61.1] always3(s18) || -> . % 76.16/76.38 182465[97:SSi:182464.0,78146.0,78150.0,165510.0,181785.0,182455.0] || -> . % 76.16/76.38 182466[97:Spt:182465.0,182460.0,182462.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.38 182467[97:Spt:182465.0,182460.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 182471[97:Res:182467.0,61.1] always3(s19) || -> . % 76.16/76.38 182472[97:SSi:182471.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.38 182473[95:Spt:182472.0,181784.0,181785.0] || until2p7(s18)*+ -> . % 76.16/76.38 182474[95:Spt:182472.0,181784.1] || -> node4(s17)*. % 76.16/76.38 182476[95:MRR:867.0,182474.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.38 182479[95:Res:53.1,182476.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.38 182481[96:Spt:182479.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 182483[96:Res:182481.0,61.1] always3(s17) || -> . % 76.16/76.38 182484[96:SSi:182483.0,78142.0,78145.0,165509.0,181783.0,182474.0] || -> . % 76.16/76.38 182485[96:Spt:182484.0,182479.0,182481.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.38 182486[96:Spt:182484.0,182479.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 182490[96:Res:182486.0,61.1] always3(s18) || -> . % 76.16/76.38 182491[96:SSi:182490.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.38 182492[94:Spt:182491.0,181782.0,181783.0] || until2p7(s17)*+ -> . % 76.16/76.38 182493[94:Spt:182491.0,181782.1] || -> node4(s16)*. % 76.16/76.38 182495[94:MRR:870.0,182493.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.38 182498[94:Res:53.1,182495.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.38 182500[95:Spt:182498.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 182502[95:Res:182500.0,61.1] always3(s16) || -> . % 76.16/76.38 182503[95:SSi:182502.0,78137.0,78141.0,165508.0,181781.0,182493.0] || -> . % 76.16/76.38 182504[95:Spt:182503.0,182498.0,182500.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.38 182505[95:Spt:182503.0,182498.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 182509[95:Res:182505.0,61.1] always3(s17) || -> . % 76.16/76.38 182510[95:SSi:182509.0,78142.0,78145.0,165509.0] || -> . % 76.16/76.38 182511[93:Spt:182510.0,181780.0,181781.0] || until2p7(s16)*+ -> . % 76.16/76.38 182512[93:Spt:182510.0,181780.1] || -> node4(s15)*. % 76.16/76.38 182514[93:MRR:873.0,182512.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.38 182517[93:Res:53.1,182514.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.38 182522[94:Spt:182517.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 182524[94:Res:182522.0,61.1] always3(s15) || -> . % 76.16/76.38 182525[94:SSi:182524.0,78133.0,78136.0,165507.0,181779.0,182512.0] || -> . % 76.16/76.38 182526[94:Spt:182525.0,182517.0,182522.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.38 182527[94:Spt:182525.0,182517.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 182531[94:Res:182527.0,61.1] always3(s16) || -> . % 76.16/76.38 182532[94:SSi:182531.0,78137.0,78141.0,165508.0] || -> . % 76.16/76.38 182533[92:Spt:182532.0,181778.0,181779.0] || until2p7(s15)*+ -> . % 76.16/76.38 182534[92:Spt:182532.0,181778.1] || -> node4(s14)*. % 76.16/76.38 182536[92:MRR:876.0,182534.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.38 182539[92:Res:53.1,182536.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.38 182541[92:MRR:182539.0,181768.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 182543[92:Res:182541.0,61.1] always3(s15) || -> . % 76.16/76.38 182544[92:SSi:182543.0,78133.0,78136.0,165507.0] || -> . % 76.16/76.38 182545[90:Spt:182544.0,181636.0,181639.0] || trans(s49,s14)*+ -> . % 76.16/76.38 182546[90:Spt:182544.0,181636.1,181636.2,181636.3,181636.4,181636.5,181636.6,181636.7,181636.8,181636.9] || -> trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.38 182548[90:MRR:181638.1,182545.0] xuntil6(s49) || -> trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.38 182549[91:Spt:182546.0] || -> trans(s49,s13)*. % 76.16/76.38 182550[91:Res:182549.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s13)*. % 76.16/76.38 182552[91:Res:182549.0,60.0] || -> node2(s49,s13)*. % 76.16/76.38 182553[91:SSi:182550.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s13)*. % 76.16/76.38 182554[91:Res:182552.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 182674[91:SoR:182554.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 182676[91:SoR:182674.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)* xuntil6(s49). % 76.16/76.38 182677[91:SSi:182676.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s13,c_busy)* xuntil6(s49). % 76.16/76.38 182678[92:Spt:182677.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 182680[92:Res:182678.0,61.1] always3(s13) || -> . % 76.16/76.38 182681[92:SSi:182680.0,78124.0,78127.0,165505.0] || -> . % 76.16/76.38 182682[92:Spt:182681.0,182677.1,182678.0] || m_main_v_state(s13,c_busy)*+ -> . % 76.16/76.38 182683[92:Spt:182681.0,182677.0,182677.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.38 182687[92:MRR:182674.2,182682.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.38 182688[92:Res:53.1,182683.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.38 182690[92:MRR:182688.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.38 182691[92:MRR:182553.0,182690.0] || -> until2p7(s13)*. % 76.16/76.38 182692[92:MRR:209.0,182691.0] || -> until2p7(s14)* node4(s13). % 76.16/76.38 182693[93:Spt:182692.0] || -> until2p7(s14)*. % 76.16/76.38 182694[93:MRR:210.0,182693.0] || -> until2p7(s15)* node4(s14). % 76.16/76.38 182695[94:Spt:182694.0] || -> until2p7(s15)*. % 76.16/76.38 182696[94:MRR:211.0,182695.0] || -> until2p7(s16)* node4(s15). % 76.16/76.38 182697[95:Spt:182696.0] || -> until2p7(s16)*. % 76.16/76.38 182698[95:MRR:212.0,182697.0] || -> until2p7(s17)* node4(s16). % 76.16/76.38 182699[96:Spt:182698.0] || -> until2p7(s17)*. % 76.16/76.38 182700[96:MRR:213.0,182699.0] || -> until2p7(s18)* node4(s17). % 76.16/76.38 182701[97:Spt:182700.0] || -> until2p7(s18)*. % 76.16/76.38 182702[97:MRR:214.0,182701.0] || -> until2p7(s19)* node4(s18). % 76.16/76.38 182703[98:Spt:182702.0] || -> until2p7(s19)*. % 76.16/76.38 182704[98:MRR:215.0,182703.0] || -> until2p7(s20)* node4(s19). % 76.16/76.38 182705[99:Spt:182704.0] || -> until2p7(s20)*. % 76.16/76.38 182706[99:MRR:216.0,182705.0] || -> until2p7(s21)* node4(s20). % 76.16/76.38 182707[100:Spt:182706.0] || -> until2p7(s21)*. % 76.16/76.38 182708[100:MRR:217.0,182707.0] || -> until2p7(s22)* node4(s21). % 76.16/76.38 182709[101:Spt:182708.0] || -> until2p7(s22)*. % 76.16/76.38 182710[101:MRR:218.0,182709.0] || -> until2p7(s23)* node4(s22). % 76.16/76.38 182711[102:Spt:182710.0] || -> until2p7(s23)*. % 76.16/76.38 182712[102:MRR:219.0,182711.0] || -> until2p7(s24)* node4(s23). % 76.16/76.38 182713[103:Spt:182712.0] || -> until2p7(s24)*. % 76.16/76.38 182714[103:MRR:220.0,182713.0] || -> until2p7(s25)* node4(s24). % 76.16/76.38 182715[104:Spt:182714.0] || -> until2p7(s25)*. % 76.16/76.38 182716[104:MRR:221.0,182715.0] || -> until2p7(s26)* node4(s25). % 76.16/76.38 182717[105:Spt:182716.0] || -> until2p7(s26)*. % 76.16/76.38 182718[105:MRR:222.0,182717.0] || -> until2p7(s27)* node4(s26). % 76.16/76.38 182719[106:Spt:182718.0] || -> until2p7(s27)*. % 76.16/76.38 182720[106:MRR:223.0,182719.0] || -> until2p7(s28)* node4(s27). % 76.16/76.38 182721[107:Spt:182720.0] || -> until2p7(s28)*. % 76.16/76.38 182722[107:MRR:224.0,182721.0] || -> until2p7(s29)* node4(s28). % 76.16/76.38 182723[108:Spt:182722.0] || -> until2p7(s29)*. % 76.16/76.38 182724[108:MRR:225.0,182723.0] || -> until2p7(s30)* node4(s29). % 76.16/76.38 182725[109:Spt:182724.0] || -> until2p7(s30)*. % 76.16/76.38 182726[109:MRR:226.0,182725.0] || -> until2p7(s31)* node4(s30). % 76.16/76.38 182727[110:Spt:182726.0] || -> until2p7(s31)*. % 76.16/76.38 182728[110:MRR:227.0,182727.0] || -> until2p7(s32)* node4(s31). % 76.16/76.38 182729[111:Spt:182728.0] || -> until2p7(s32)*. % 76.16/76.38 182730[111:MRR:228.0,182729.0] || -> until2p7(s33)* node4(s32). % 76.16/76.38 182731[112:Spt:182730.0] || -> until2p7(s33)*. % 76.16/76.38 182732[112:MRR:229.0,182731.0] || -> until2p7(s34)* node4(s33). % 76.16/76.38 182733[113:Spt:182732.0] || -> until2p7(s34)*. % 76.16/76.38 182734[113:MRR:230.0,182733.0] || -> until2p7(s35)* node4(s34). % 76.16/76.38 182735[114:Spt:182734.0] || -> until2p7(s35)*. % 76.16/76.38 182736[114:MRR:231.0,182735.0] || -> until2p7(s36)* node4(s35). % 76.16/76.38 182737[115:Spt:182736.0] || -> until2p7(s36)*. % 76.16/76.38 182738[115:MRR:232.0,182737.0] || -> until2p7(s37)* node4(s36). % 76.16/76.38 182739[116:Spt:182738.0] || -> until2p7(s37)*. % 76.16/76.38 182740[116:MRR:235.0,182739.0] || -> until2p7(s38)* node4(s37). % 76.16/76.38 182741[117:Spt:182740.0] || -> until2p7(s38)*. % 76.16/76.38 182742[117:MRR:236.0,182741.0] || -> until2p7(s39)* node4(s38). % 76.16/76.38 182743[118:Spt:182742.0] || -> until2p7(s39)*. % 76.16/76.38 182744[118:MRR:237.0,182743.0] || -> until2p7(s40)* node4(s39). % 76.16/76.38 182745[119:Spt:182744.0] || -> until2p7(s40)*. % 76.16/76.38 182746[119:MRR:238.0,182745.0] || -> until2p7(s41)* node4(s40). % 76.16/76.38 182747[120:Spt:182746.0] || -> until2p7(s41)*. % 76.16/76.38 182748[120:MRR:239.0,182747.0] || -> until2p7(s42)* node4(s41). % 76.16/76.38 182749[121:Spt:182748.0] || -> until2p7(s42)*. % 76.16/76.38 182750[121:MRR:240.0,182749.0] || -> until2p7(s43)* node4(s42). % 76.16/76.38 182751[122:Spt:182750.0] || -> until2p7(s43)*. % 76.16/76.38 182752[122:MRR:241.0,182751.0] || -> until2p7(s44)* node4(s43). % 76.16/76.38 182753[123:Spt:182752.0] || -> until2p7(s44)*. % 76.16/76.38 182754[123:MRR:539.0,182753.0] || -> until2p7(s45)* node4(s44). % 76.16/76.38 182755[124:Spt:182754.0] || -> until2p7(s45)*. % 76.16/76.38 182756[124:MRR:544.0,182755.0] || -> until2p7(s46)* node4(s45). % 76.16/76.38 182757[125:Spt:182756.0] || -> until2p7(s46)*. % 76.16/76.38 182758[125:MRR:549.0,182757.0] || -> until2p7(s47)* node4(s46). % 76.16/76.38 182759[126:Spt:182758.0] || -> until2p7(s47)*. % 76.16/76.38 182760[126:MRR:554.0,182759.0] || -> until2p7(s48)* node4(s47). % 76.16/76.38 182761[127:Spt:182760.0] || -> until2p7(s48)*. % 76.16/76.38 182762[127:MRR:559.0,182761.0] || -> until2p7(s49)* node4(s48). % 76.16/76.38 182763[128:Spt:182762.0] || -> until2p7(s49)*. % 76.16/76.38 182764[128:MRR:194.0,182763.0] || -> node4(s49)*. % 76.16/76.38 182765[128:MRR:182687.0,182764.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.38 182769[128:Res:53.1,182765.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.38 182771[128:MRR:182769.0,78381.0] || -> . % 76.16/76.38 182772[128:Spt:182771.0,182762.0,182763.0] || until2p7(s49)*+ -> . % 76.16/76.38 182773[128:Spt:182771.0,182762.1] || -> node4(s48)*. % 76.16/76.38 182774[128:MRR:78384.0,182773.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.38 182777[128:Res:53.1,182774.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 182780[128:Res:182777.0,61.1] always3(s48) || -> . % 76.16/76.38 182781[128:SSi:182780.0,78281.0,78387.0,165540.0,182761.0,182773.0] || -> . % 76.16/76.38 182782[127:Spt:182781.0,182760.0,182761.0] || until2p7(s48)*+ -> . % 76.16/76.38 182783[127:Spt:182781.0,182760.1] || -> node4(s47)*. % 76.16/76.38 182785[127:MRR:777.0,182783.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.38 182797[127:Res:53.1,182785.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.38 182799[128:Spt:182797.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 182801[128:Res:182799.0,61.1] always3(s47) || -> . % 76.16/76.38 182802[128:SSi:182801.0,78277.0,78280.0,165539.0,182759.0,182783.0] || -> . % 76.16/76.38 182803[128:Spt:182802.0,182797.0,182799.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.38 182804[128:Spt:182802.0,182797.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 182808[128:Res:182804.0,61.1] always3(s48) || -> . % 76.16/76.38 182809[128:SSi:182808.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.38 182810[126:Spt:182809.0,182758.0,182759.0] || until2p7(s47)*+ -> . % 76.16/76.38 182811[126:Spt:182809.0,182758.1] || -> node4(s46)*. % 76.16/76.38 182813[126:MRR:780.0,182811.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.38 182820[126:Res:53.1,182813.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.38 182825[127:Spt:182820.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 182827[127:Res:182825.0,61.1] always3(s46) || -> . % 76.16/76.38 182828[127:SSi:182827.0,78272.0,78276.0,165538.0,182757.0,182811.0] || -> . % 76.16/76.38 182829[127:Spt:182828.0,182820.0,182825.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.38 182830[127:Spt:182828.0,182820.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 182834[127:Res:182830.0,61.1] always3(s47) || -> . % 76.16/76.38 182835[127:SSi:182834.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.38 182836[125:Spt:182835.0,182756.0,182757.0] || until2p7(s46)*+ -> . % 76.16/76.38 182837[125:Spt:182835.0,182756.1] || -> node4(s45)*. % 76.16/76.38 182839[125:MRR:783.0,182837.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.38 182842[125:Res:53.1,182839.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.38 182844[126:Spt:182842.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 182846[126:Res:182844.0,61.1] always3(s45) || -> . % 76.16/76.38 182847[126:SSi:182846.0,78268.0,78271.0,165537.0,182755.0,182837.0] || -> . % 76.16/76.38 182848[126:Spt:182847.0,182842.0,182844.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.38 182849[126:Spt:182847.0,182842.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 182853[126:Res:182849.0,61.1] always3(s46) || -> . % 76.16/76.38 182854[126:SSi:182853.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.38 182855[124:Spt:182854.0,182754.0,182755.0] || until2p7(s45)*+ -> . % 76.16/76.38 182856[124:Spt:182854.0,182754.1] || -> node4(s44)*. % 76.16/76.38 182858[124:MRR:786.0,182856.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.38 182861[124:Res:53.1,182858.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.38 182863[125:Spt:182861.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 182865[125:Res:182863.0,61.1] always3(s44) || -> . % 76.16/76.38 182866[125:SSi:182865.0,78263.0,78267.0,165536.0,182753.0,182856.0] || -> . % 76.16/76.38 182867[125:Spt:182866.0,182861.0,182863.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.38 182868[125:Spt:182866.0,182861.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 182872[125:Res:182868.0,61.1] always3(s45) || -> . % 76.16/76.38 182873[125:SSi:182872.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.38 182874[123:Spt:182873.0,182752.0,182753.0] || until2p7(s44)*+ -> . % 76.16/76.38 182875[123:Spt:182873.0,182752.1] || -> node4(s43)*. % 76.16/76.38 182877[123:MRR:789.0,182875.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.38 182880[123:Res:53.1,182877.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.38 182882[124:Spt:182880.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 182884[124:Res:182882.0,61.1] always3(s43) || -> . % 76.16/76.38 182885[124:SSi:182884.0,78259.0,78262.0,165535.0,182751.0,182875.0] || -> . % 76.16/76.38 182886[124:Spt:182885.0,182880.0,182882.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.38 182887[124:Spt:182885.0,182880.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 182891[124:Res:182887.0,61.1] always3(s44) || -> . % 76.16/76.38 182892[124:SSi:182891.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.38 182893[122:Spt:182892.0,182750.0,182751.0] || until2p7(s43)*+ -> . % 76.16/76.38 182894[122:Spt:182892.0,182750.1] || -> node4(s42)*. % 76.16/76.38 182896[122:MRR:792.0,182894.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.38 182899[122:Res:53.1,182896.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.38 182904[123:Spt:182899.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 182906[123:Res:182904.0,61.1] always3(s42) || -> . % 76.16/76.38 182907[123:SSi:182906.0,78254.0,78258.0,165534.0,182749.0,182894.0] || -> . % 76.16/76.38 182908[123:Spt:182907.0,182899.0,182904.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.38 182909[123:Spt:182907.0,182899.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 182913[123:Res:182909.0,61.1] always3(s43) || -> . % 76.16/76.38 182914[123:SSi:182913.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.38 182915[121:Spt:182914.0,182748.0,182749.0] || until2p7(s42)*+ -> . % 76.16/76.38 182916[121:Spt:182914.0,182748.1] || -> node4(s41)*. % 76.16/76.38 182918[121:MRR:795.0,182916.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.38 182921[121:Res:53.1,182918.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.38 182923[122:Spt:182921.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 182925[122:Res:182923.0,61.1] always3(s41) || -> . % 76.16/76.38 182926[122:SSi:182925.0,78250.0,78253.0,165533.0,182747.0,182916.0] || -> . % 76.16/76.38 182927[122:Spt:182926.0,182921.0,182923.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.38 182928[122:Spt:182926.0,182921.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 182932[122:Res:182928.0,61.1] always3(s42) || -> . % 76.16/76.38 182933[122:SSi:182932.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.38 182934[120:Spt:182933.0,182746.0,182747.0] || until2p7(s41)*+ -> . % 76.16/76.38 182935[120:Spt:182933.0,182746.1] || -> node4(s40)*. % 76.16/76.38 182937[120:MRR:798.0,182935.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.38 182940[120:Res:53.1,182937.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.38 182942[121:Spt:182940.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 182944[121:Res:182942.0,61.1] always3(s40) || -> . % 76.16/76.38 182945[121:SSi:182944.0,78245.0,78249.0,165532.0,182745.0,182935.0] || -> . % 76.16/76.38 182946[121:Spt:182945.0,182940.0,182942.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.38 182947[121:Spt:182945.0,182940.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 182951[121:Res:182947.0,61.1] always3(s41) || -> . % 76.16/76.38 182952[121:SSi:182951.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.38 182953[119:Spt:182952.0,182744.0,182745.0] || until2p7(s40)*+ -> . % 76.16/76.38 182954[119:Spt:182952.0,182744.1] || -> node4(s39)*. % 76.16/76.38 182956[119:MRR:801.0,182954.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.38 182959[119:Res:53.1,182956.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.38 182961[120:Spt:182959.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 182963[120:Res:182961.0,61.1] always3(s39) || -> . % 76.16/76.38 182964[120:SSi:182963.0,78241.0,78244.0,165531.0,182743.0,182954.0] || -> . % 76.16/76.38 182965[120:Spt:182964.0,182959.0,182961.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.38 182966[120:Spt:182964.0,182959.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 182970[120:Res:182966.0,61.1] always3(s40) || -> . % 76.16/76.38 182971[120:SSi:182970.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.38 182972[118:Spt:182971.0,182742.0,182743.0] || until2p7(s39)*+ -> . % 76.16/76.38 182973[118:Spt:182971.0,182742.1] || -> node4(s38)*. % 76.16/76.38 182975[118:MRR:804.0,182973.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.38 182978[118:Res:53.1,182975.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.38 182983[119:Spt:182978.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 182985[119:Res:182983.0,61.1] always3(s38) || -> . % 76.16/76.38 182986[119:SSi:182985.0,78236.0,78240.0,165530.0,182741.0,182973.0] || -> . % 76.16/76.38 182987[119:Spt:182986.0,182978.0,182983.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.38 182988[119:Spt:182986.0,182978.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 182992[119:Res:182988.0,61.1] always3(s39) || -> . % 76.16/76.38 182993[119:SSi:182992.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.38 182994[117:Spt:182993.0,182740.0,182741.0] || until2p7(s38)*+ -> . % 76.16/76.38 182995[117:Spt:182993.0,182740.1] || -> node4(s37)*. % 76.16/76.38 182997[117:MRR:807.0,182995.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.38 183000[117:Res:53.1,182997.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.38 183002[118:Spt:183000.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 183004[118:Res:183002.0,61.1] always3(s37) || -> . % 76.16/76.38 183005[118:SSi:183004.0,78232.0,78235.0,165529.0,182739.0,182995.0] || -> . % 76.16/76.38 183006[118:Spt:183005.0,183000.0,183002.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.38 183007[118:Spt:183005.0,183000.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 183011[118:Res:183007.0,61.1] always3(s38) || -> . % 76.16/76.38 183012[118:SSi:183011.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.38 183013[116:Spt:183012.0,182738.0,182739.0] || until2p7(s37)*+ -> . % 76.16/76.38 183014[116:Spt:183012.0,182738.1] || -> node4(s36)*. % 76.16/76.38 183016[116:MRR:810.0,183014.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.38 183019[116:Res:53.1,183016.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.38 183021[117:Spt:183019.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 183023[117:Res:183021.0,61.1] always3(s36) || -> . % 76.16/76.38 183024[117:SSi:183023.0,78227.0,78231.0,165528.0,182737.0,183014.0] || -> . % 76.16/76.38 183025[117:Spt:183024.0,183019.0,183021.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.38 183026[117:Spt:183024.0,183019.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 183030[117:Res:183026.0,61.1] always3(s37) || -> . % 76.16/76.38 183031[117:SSi:183030.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.38 183032[115:Spt:183031.0,182736.0,182737.0] || until2p7(s36)*+ -> . % 76.16/76.38 183033[115:Spt:183031.0,182736.1] || -> node4(s35)*. % 76.16/76.38 183035[115:MRR:813.0,183033.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.38 183038[115:Res:53.1,183035.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.38 183040[116:Spt:183038.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 183042[116:Res:183040.0,61.1] always3(s35) || -> . % 76.16/76.38 183043[116:SSi:183042.0,78223.0,78226.0,165527.0,182735.0,183033.0] || -> . % 76.16/76.38 183044[116:Spt:183043.0,183038.0,183040.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.38 183045[116:Spt:183043.0,183038.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 183049[116:Res:183045.0,61.1] always3(s36) || -> . % 76.16/76.38 183050[116:SSi:183049.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.38 183051[114:Spt:183050.0,182734.0,182735.0] || until2p7(s35)*+ -> . % 76.16/76.38 183052[114:Spt:183050.0,182734.1] || -> node4(s34)*. % 76.16/76.38 183054[114:MRR:816.0,183052.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.38 183057[114:Res:53.1,183054.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.38 183062[115:Spt:183057.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 183064[115:Res:183062.0,61.1] always3(s34) || -> . % 76.16/76.38 183065[115:SSi:183064.0,78218.0,78222.0,165526.0,182733.0,183052.0] || -> . % 76.16/76.38 183066[115:Spt:183065.0,183057.0,183062.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.38 183067[115:Spt:183065.0,183057.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 183071[115:Res:183067.0,61.1] always3(s35) || -> . % 76.16/76.38 183072[115:SSi:183071.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.38 183073[113:Spt:183072.0,182732.0,182733.0] || until2p7(s34)*+ -> . % 76.16/76.38 183074[113:Spt:183072.0,182732.1] || -> node4(s33)*. % 76.16/76.38 183076[113:MRR:819.0,183074.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.38 183079[113:Res:53.1,183076.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.38 183081[114:Spt:183079.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 183083[114:Res:183081.0,61.1] always3(s33) || -> . % 76.16/76.38 183084[114:SSi:183083.0,78214.0,78217.0,165525.0,182731.0,183074.0] || -> . % 76.16/76.38 183085[114:Spt:183084.0,183079.0,183081.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.38 183086[114:Spt:183084.0,183079.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 183090[114:Res:183086.0,61.1] always3(s34) || -> . % 76.16/76.38 183091[114:SSi:183090.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.38 183092[112:Spt:183091.0,182730.0,182731.0] || until2p7(s33)*+ -> . % 76.16/76.38 183093[112:Spt:183091.0,182730.1] || -> node4(s32)*. % 76.16/76.38 183095[112:MRR:822.0,183093.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.38 183098[112:Res:53.1,183095.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.38 183100[113:Spt:183098.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 183102[113:Res:183100.0,61.1] always3(s32) || -> . % 76.16/76.38 183103[113:SSi:183102.0,78209.0,78213.0,165524.0,182729.0,183093.0] || -> . % 76.16/76.38 183104[113:Spt:183103.0,183098.0,183100.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.38 183105[113:Spt:183103.0,183098.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 183109[113:Res:183105.0,61.1] always3(s33) || -> . % 76.16/76.38 183110[113:SSi:183109.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.38 183111[111:Spt:183110.0,182728.0,182729.0] || until2p7(s32)*+ -> . % 76.16/76.38 183112[111:Spt:183110.0,182728.1] || -> node4(s31)*. % 76.16/76.38 183114[111:MRR:825.0,183112.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.38 183117[111:Res:53.1,183114.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.38 183119[112:Spt:183117.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 183121[112:Res:183119.0,61.1] always3(s31) || -> . % 76.16/76.38 183122[112:SSi:183121.0,78205.0,78208.0,165523.0,182727.0,183112.0] || -> . % 76.16/76.38 183123[112:Spt:183122.0,183117.0,183119.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.38 183124[112:Spt:183122.0,183117.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 183128[112:Res:183124.0,61.1] always3(s32) || -> . % 76.16/76.38 183129[112:SSi:183128.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.38 183130[110:Spt:183129.0,182726.0,182727.0] || until2p7(s31)*+ -> . % 76.16/76.38 183131[110:Spt:183129.0,182726.1] || -> node4(s30)*. % 76.16/76.38 183133[110:MRR:828.0,183131.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.38 183136[110:Res:53.1,183133.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.38 183141[111:Spt:183136.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 183143[111:Res:183141.0,61.1] always3(s30) || -> . % 76.16/76.38 183144[111:SSi:183143.0,78200.0,78204.0,165522.0,182725.0,183131.0] || -> . % 76.16/76.38 183145[111:Spt:183144.0,183136.0,183141.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.38 183146[111:Spt:183144.0,183136.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 183150[111:Res:183146.0,61.1] always3(s31) || -> . % 76.16/76.38 183151[111:SSi:183150.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.38 183152[109:Spt:183151.0,182724.0,182725.0] || until2p7(s30)*+ -> . % 76.16/76.38 183153[109:Spt:183151.0,182724.1] || -> node4(s29)*. % 76.16/76.38 183155[109:MRR:831.0,183153.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.38 183158[109:Res:53.1,183155.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.38 183160[110:Spt:183158.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 183162[110:Res:183160.0,61.1] always3(s29) || -> . % 76.16/76.38 183163[110:SSi:183162.0,78196.0,78199.0,165521.0,182723.0,183153.0] || -> . % 76.16/76.38 183164[110:Spt:183163.0,183158.0,183160.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.38 183165[110:Spt:183163.0,183158.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 183169[110:Res:183165.0,61.1] always3(s30) || -> . % 76.16/76.38 183170[110:SSi:183169.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.38 183171[108:Spt:183170.0,182722.0,182723.0] || until2p7(s29)*+ -> . % 76.16/76.38 183172[108:Spt:183170.0,182722.1] || -> node4(s28)*. % 76.16/76.38 183174[108:MRR:834.0,183172.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.38 183177[108:Res:53.1,183174.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.38 183179[109:Spt:183177.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 183181[109:Res:183179.0,61.1] always3(s28) || -> . % 76.16/76.38 183182[109:SSi:183181.0,78191.0,78195.0,165520.0,182721.0,183172.0] || -> . % 76.16/76.38 183183[109:Spt:183182.0,183177.0,183179.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.38 183184[109:Spt:183182.0,183177.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 183188[109:Res:183184.0,61.1] always3(s29) || -> . % 76.16/76.38 183189[109:SSi:183188.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.38 183190[107:Spt:183189.0,182720.0,182721.0] || until2p7(s28)*+ -> . % 76.16/76.38 183191[107:Spt:183189.0,182720.1] || -> node4(s27)*. % 76.16/76.38 183193[107:MRR:837.0,183191.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.38 183196[107:Res:53.1,183193.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.38 183198[108:Spt:183196.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 183200[108:Res:183198.0,61.1] always3(s27) || -> . % 76.16/76.38 183201[108:SSi:183200.0,78187.0,78190.0,165519.0,182719.0,183191.0] || -> . % 76.16/76.38 183202[108:Spt:183201.0,183196.0,183198.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.38 183203[108:Spt:183201.0,183196.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 183207[108:Res:183203.0,61.1] always3(s28) || -> . % 76.16/76.38 183208[108:SSi:183207.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.38 183209[106:Spt:183208.0,182718.0,182719.0] || until2p7(s27)*+ -> . % 76.16/76.38 183210[106:Spt:183208.0,182718.1] || -> node4(s26)*. % 76.16/76.38 183212[106:MRR:840.0,183210.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.38 183215[106:Res:53.1,183212.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.38 183220[107:Spt:183215.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 183222[107:Res:183220.0,61.1] always3(s26) || -> . % 76.16/76.38 183223[107:SSi:183222.0,78182.0,78186.0,165518.0,182717.0,183210.0] || -> . % 76.16/76.38 183224[107:Spt:183223.0,183215.0,183220.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.38 183225[107:Spt:183223.0,183215.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 183229[107:Res:183225.0,61.1] always3(s27) || -> . % 76.16/76.38 183230[107:SSi:183229.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.38 183231[105:Spt:183230.0,182716.0,182717.0] || until2p7(s26)*+ -> . % 76.16/76.38 183232[105:Spt:183230.0,182716.1] || -> node4(s25)*. % 76.16/76.38 183234[105:MRR:843.0,183232.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.38 183237[105:Res:53.1,183234.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.38 183239[106:Spt:183237.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 183241[106:Res:183239.0,61.1] always3(s25) || -> . % 76.16/76.38 183242[106:SSi:183241.0,78178.0,78181.0,165517.0,182715.0,183232.0] || -> . % 76.16/76.38 183243[106:Spt:183242.0,183237.0,183239.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.38 183244[106:Spt:183242.0,183237.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 183248[106:Res:183244.0,61.1] always3(s26) || -> . % 76.16/76.38 183249[106:SSi:183248.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.38 183250[104:Spt:183249.0,182714.0,182715.0] || until2p7(s25)*+ -> . % 76.16/76.38 183251[104:Spt:183249.0,182714.1] || -> node4(s24)*. % 76.16/76.38 183253[104:MRR:846.0,183251.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.38 183256[104:Res:53.1,183253.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.38 183258[105:Spt:183256.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 183260[105:Res:183258.0,61.1] always3(s24) || -> . % 76.16/76.38 183261[105:SSi:183260.0,78173.0,78177.0,165516.0,182713.0,183251.0] || -> . % 76.16/76.38 183262[105:Spt:183261.0,183256.0,183258.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.38 183263[105:Spt:183261.0,183256.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 183267[105:Res:183263.0,61.1] always3(s25) || -> . % 76.16/76.38 183268[105:SSi:183267.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.38 183269[103:Spt:183268.0,182712.0,182713.0] || until2p7(s24)*+ -> . % 76.16/76.38 183270[103:Spt:183268.0,182712.1] || -> node4(s23)*. % 76.16/76.38 183272[103:MRR:849.0,183270.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.38 183275[103:Res:53.1,183272.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.38 183277[104:Spt:183275.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 183279[104:Res:183277.0,61.1] always3(s23) || -> . % 76.16/76.38 183280[104:SSi:183279.0,78169.0,78172.0,165515.0,182711.0,183270.0] || -> . % 76.16/76.38 183281[104:Spt:183280.0,183275.0,183277.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.38 183282[104:Spt:183280.0,183275.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 183286[104:Res:183282.0,61.1] always3(s24) || -> . % 76.16/76.38 183287[104:SSi:183286.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.38 183288[102:Spt:183287.0,182710.0,182711.0] || until2p7(s23)*+ -> . % 76.16/76.38 183289[102:Spt:183287.0,182710.1] || -> node4(s22)*. % 76.16/76.38 183291[102:MRR:852.0,183289.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.38 183294[102:Res:53.1,183291.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.38 183299[103:Spt:183294.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 183301[103:Res:183299.0,61.1] always3(s22) || -> . % 76.16/76.38 183302[103:SSi:183301.0,78164.0,78168.0,165514.0,182709.0,183289.0] || -> . % 76.16/76.38 183303[103:Spt:183302.0,183294.0,183299.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.38 183304[103:Spt:183302.0,183294.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 183308[103:Res:183304.0,61.1] always3(s23) || -> . % 76.16/76.38 183309[103:SSi:183308.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.38 183310[101:Spt:183309.0,182708.0,182709.0] || until2p7(s22)*+ -> . % 76.16/76.38 183311[101:Spt:183309.0,182708.1] || -> node4(s21)*. % 76.16/76.38 183313[101:MRR:855.0,183311.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.38 183316[101:Res:53.1,183313.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.38 183318[102:Spt:183316.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 183320[102:Res:183318.0,61.1] always3(s21) || -> . % 76.16/76.38 183321[102:SSi:183320.0,78160.0,78163.0,165513.0,182707.0,183311.0] || -> . % 76.16/76.38 183322[102:Spt:183321.0,183316.0,183318.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.38 183323[102:Spt:183321.0,183316.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 183327[102:Res:183323.0,61.1] always3(s22) || -> . % 76.16/76.38 183328[102:SSi:183327.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.38 183329[100:Spt:183328.0,182706.0,182707.0] || until2p7(s21)*+ -> . % 76.16/76.38 183330[100:Spt:183328.0,182706.1] || -> node4(s20)*. % 76.16/76.38 183332[100:MRR:858.0,183330.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.38 183335[100:Res:53.1,183332.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.38 183337[101:Spt:183335.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 183339[101:Res:183337.0,61.1] always3(s20) || -> . % 76.16/76.38 183340[101:SSi:183339.0,78155.0,78159.0,165512.0,182705.0,183330.0] || -> . % 76.16/76.38 183341[101:Spt:183340.0,183335.0,183337.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.38 183342[101:Spt:183340.0,183335.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 183346[101:Res:183342.0,61.1] always3(s21) || -> . % 76.16/76.38 183347[101:SSi:183346.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.38 183348[99:Spt:183347.0,182704.0,182705.0] || until2p7(s20)*+ -> . % 76.16/76.38 183349[99:Spt:183347.0,182704.1] || -> node4(s19)*. % 76.16/76.38 183351[99:MRR:861.0,183349.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.38 183354[99:Res:53.1,183351.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.38 183356[100:Spt:183354.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 183358[100:Res:183356.0,61.1] always3(s19) || -> . % 76.16/76.38 183359[100:SSi:183358.0,78151.0,78154.0,165511.0,182703.0,183349.0] || -> . % 76.16/76.38 183360[100:Spt:183359.0,183354.0,183356.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.38 183361[100:Spt:183359.0,183354.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 183365[100:Res:183361.0,61.1] always3(s20) || -> . % 76.16/76.38 183366[100:SSi:183365.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.38 183367[98:Spt:183366.0,182702.0,182703.0] || until2p7(s19)*+ -> . % 76.16/76.38 183368[98:Spt:183366.0,182702.1] || -> node4(s18)*. % 76.16/76.38 183370[98:MRR:864.0,183368.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.38 183373[98:Res:53.1,183370.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.38 183378[99:Spt:183373.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 183380[99:Res:183378.0,61.1] always3(s18) || -> . % 76.16/76.38 183381[99:SSi:183380.0,78146.0,78150.0,165510.0,182701.0,183368.0] || -> . % 76.16/76.38 183382[99:Spt:183381.0,183373.0,183378.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.38 183383[99:Spt:183381.0,183373.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 183387[99:Res:183383.0,61.1] always3(s19) || -> . % 76.16/76.38 183388[99:SSi:183387.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.38 183389[97:Spt:183388.0,182700.0,182701.0] || until2p7(s18)*+ -> . % 76.16/76.38 183390[97:Spt:183388.0,182700.1] || -> node4(s17)*. % 76.16/76.38 183392[97:MRR:867.0,183390.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.38 183395[97:Res:53.1,183392.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.38 183397[98:Spt:183395.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 183399[98:Res:183397.0,61.1] always3(s17) || -> . % 76.16/76.38 183400[98:SSi:183399.0,78142.0,78145.0,165509.0,182699.0,183390.0] || -> . % 76.16/76.38 183401[98:Spt:183400.0,183395.0,183397.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.38 183402[98:Spt:183400.0,183395.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 183406[98:Res:183402.0,61.1] always3(s18) || -> . % 76.16/76.38 183407[98:SSi:183406.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.38 183408[96:Spt:183407.0,182698.0,182699.0] || until2p7(s17)*+ -> . % 76.16/76.38 183409[96:Spt:183407.0,182698.1] || -> node4(s16)*. % 76.16/76.38 183411[96:MRR:870.0,183409.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.38 183414[96:Res:53.1,183411.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.38 183416[97:Spt:183414.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 183418[97:Res:183416.0,61.1] always3(s16) || -> . % 76.16/76.38 183419[97:SSi:183418.0,78137.0,78141.0,165508.0,182697.0,183409.0] || -> . % 76.16/76.38 183420[97:Spt:183419.0,183414.0,183416.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.38 183421[97:Spt:183419.0,183414.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 183425[97:Res:183421.0,61.1] always3(s17) || -> . % 76.16/76.38 183426[97:SSi:183425.0,78142.0,78145.0,165509.0] || -> . % 76.16/76.38 183427[95:Spt:183426.0,182696.0,182697.0] || until2p7(s16)*+ -> . % 76.16/76.38 183428[95:Spt:183426.0,182696.1] || -> node4(s15)*. % 76.16/76.38 183430[95:MRR:873.0,183428.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.38 183433[95:Res:53.1,183430.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.38 183435[96:Spt:183433.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 183437[96:Res:183435.0,61.1] always3(s15) || -> . % 76.16/76.38 183438[96:SSi:183437.0,78133.0,78136.0,165507.0,182695.0,183428.0] || -> . % 76.16/76.38 183439[96:Spt:183438.0,183433.0,183435.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.38 183440[96:Spt:183438.0,183433.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 183444[96:Res:183440.0,61.1] always3(s16) || -> . % 76.16/76.38 183445[96:SSi:183444.0,78137.0,78141.0,165508.0] || -> . % 76.16/76.38 183446[94:Spt:183445.0,182694.0,182695.0] || until2p7(s15)*+ -> . % 76.16/76.38 183447[94:Spt:183445.0,182694.1] || -> node4(s14)*. % 76.16/76.38 183449[94:MRR:876.0,183447.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.38 183452[94:Res:53.1,183449.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.38 183457[95:Spt:183452.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 183459[95:Res:183457.0,61.1] always3(s14) || -> . % 76.16/76.38 183460[95:SSi:183459.0,78128.0,78132.0,165506.0,182693.0,183447.0] || -> . % 76.16/76.38 183461[95:Spt:183460.0,183452.0,183457.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.38 183462[95:Spt:183460.0,183452.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 183466[95:Res:183462.0,61.1] always3(s15) || -> . % 76.16/76.38 183467[95:SSi:183466.0,78133.0,78136.0,165507.0] || -> . % 76.16/76.38 183468[93:Spt:183467.0,182692.0,182693.0] || until2p7(s14)*+ -> . % 76.16/76.38 183469[93:Spt:183467.0,182692.1] || -> node4(s13)*. % 76.16/76.38 183471[93:MRR:879.0,183469.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.38 183474[93:Res:53.1,183471.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.38 183476[93:MRR:183474.0,182682.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 183478[93:Res:183476.0,61.1] always3(s14) || -> . % 76.16/76.38 183479[93:SSi:183478.0,78128.0,78132.0,165506.0] || -> . % 76.16/76.38 183480[91:Spt:183479.0,182546.0,182549.0] || trans(s49,s13)*+ -> . % 76.16/76.38 183481[91:Spt:183479.0,182546.1,182546.2,182546.3,182546.4,182546.5,182546.6,182546.7,182546.8] || -> trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.38 183483[91:MRR:182548.1,183480.0] xuntil6(s49) || -> trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.38 183484[92:Spt:183481.0] || -> trans(s49,s12)*. % 76.16/76.38 183485[92:Res:183484.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s12)*. % 76.16/76.38 183487[92:Res:183484.0,60.0] || -> node2(s49,s12)*. % 76.16/76.38 183488[92:SSi:183485.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s12)*. % 76.16/76.38 183489[92:Res:183487.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)*. % 76.16/76.38 183613[92:SoR:183489.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)*. % 76.16/76.38 183615[92:SoR:183613.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)* xuntil6(s49). % 76.16/76.38 183616[92:SSi:183615.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s12,c_busy)* xuntil6(s49). % 76.16/76.38 183617[93:Spt:183616.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.38 183619[93:Res:183617.0,61.1] always3(s12) || -> . % 76.16/76.38 183620[93:SSi:183619.0,78119.0,78123.0,165504.0] || -> . % 76.16/76.38 183621[93:Spt:183620.0,183616.1,183617.0] || m_main_v_state(s12,c_busy)*+ -> . % 76.16/76.38 183622[93:Spt:183620.0,183616.0,183616.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.38 183626[93:MRR:183613.2,183621.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.38 183627[93:Res:53.1,183622.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.38 183629[93:MRR:183627.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.38 183630[93:MRR:183488.0,183629.0] || -> until2p7(s12)*. % 76.16/76.38 183631[93:MRR:208.0,183630.0] || -> until2p7(s13)* node4(s12). % 76.16/76.38 183632[94:Spt:183631.0] || -> until2p7(s13)*. % 76.16/76.38 183633[94:MRR:209.0,183632.0] || -> until2p7(s14)* node4(s13). % 76.16/76.38 183634[95:Spt:183633.0] || -> until2p7(s14)*. % 76.16/76.38 183635[95:MRR:210.0,183634.0] || -> until2p7(s15)* node4(s14). % 76.16/76.38 183636[96:Spt:183635.0] || -> until2p7(s15)*. % 76.16/76.38 183637[96:MRR:211.0,183636.0] || -> until2p7(s16)* node4(s15). % 76.16/76.38 183638[97:Spt:183637.0] || -> until2p7(s16)*. % 76.16/76.38 183639[97:MRR:212.0,183638.0] || -> until2p7(s17)* node4(s16). % 76.16/76.38 183640[98:Spt:183639.0] || -> until2p7(s17)*. % 76.16/76.38 183641[98:MRR:213.0,183640.0] || -> until2p7(s18)* node4(s17). % 76.16/76.38 183642[99:Spt:183641.0] || -> until2p7(s18)*. % 76.16/76.38 183643[99:MRR:214.0,183642.0] || -> until2p7(s19)* node4(s18). % 76.16/76.38 183644[100:Spt:183643.0] || -> until2p7(s19)*. % 76.16/76.38 183645[100:MRR:215.0,183644.0] || -> until2p7(s20)* node4(s19). % 76.16/76.38 183646[101:Spt:183645.0] || -> until2p7(s20)*. % 76.16/76.38 183647[101:MRR:216.0,183646.0] || -> until2p7(s21)* node4(s20). % 76.16/76.38 183648[102:Spt:183647.0] || -> until2p7(s21)*. % 76.16/76.38 183649[102:MRR:217.0,183648.0] || -> until2p7(s22)* node4(s21). % 76.16/76.38 183650[103:Spt:183649.0] || -> until2p7(s22)*. % 76.16/76.38 183651[103:MRR:218.0,183650.0] || -> until2p7(s23)* node4(s22). % 76.16/76.38 183652[104:Spt:183651.0] || -> until2p7(s23)*. % 76.16/76.38 183653[104:MRR:219.0,183652.0] || -> until2p7(s24)* node4(s23). % 76.16/76.38 183654[105:Spt:183653.0] || -> until2p7(s24)*. % 76.16/76.38 183655[105:MRR:220.0,183654.0] || -> until2p7(s25)* node4(s24). % 76.16/76.38 183656[106:Spt:183655.0] || -> until2p7(s25)*. % 76.16/76.38 183657[106:MRR:221.0,183656.0] || -> until2p7(s26)* node4(s25). % 76.16/76.38 183658[107:Spt:183657.0] || -> until2p7(s26)*. % 76.16/76.38 183659[107:MRR:222.0,183658.0] || -> until2p7(s27)* node4(s26). % 76.16/76.38 183660[108:Spt:183659.0] || -> until2p7(s27)*. % 76.16/76.38 183661[108:MRR:223.0,183660.0] || -> until2p7(s28)* node4(s27). % 76.16/76.38 183662[109:Spt:183661.0] || -> until2p7(s28)*. % 76.16/76.38 183663[109:MRR:224.0,183662.0] || -> until2p7(s29)* node4(s28). % 76.16/76.38 183664[110:Spt:183663.0] || -> until2p7(s29)*. % 76.16/76.38 183665[110:MRR:225.0,183664.0] || -> until2p7(s30)* node4(s29). % 76.16/76.38 183666[111:Spt:183665.0] || -> until2p7(s30)*. % 76.16/76.38 183667[111:MRR:226.0,183666.0] || -> until2p7(s31)* node4(s30). % 76.16/76.38 183668[112:Spt:183667.0] || -> until2p7(s31)*. % 76.16/76.38 183669[112:MRR:227.0,183668.0] || -> until2p7(s32)* node4(s31). % 76.16/76.38 183670[113:Spt:183669.0] || -> until2p7(s32)*. % 76.16/76.38 183671[113:MRR:228.0,183670.0] || -> until2p7(s33)* node4(s32). % 76.16/76.38 183672[114:Spt:183671.0] || -> until2p7(s33)*. % 76.16/76.38 183673[114:MRR:229.0,183672.0] || -> until2p7(s34)* node4(s33). % 76.16/76.38 183674[115:Spt:183673.0] || -> until2p7(s34)*. % 76.16/76.38 183675[115:MRR:230.0,183674.0] || -> until2p7(s35)* node4(s34). % 76.16/76.38 183676[116:Spt:183675.0] || -> until2p7(s35)*. % 76.16/76.38 183677[116:MRR:231.0,183676.0] || -> until2p7(s36)* node4(s35). % 76.16/76.38 183678[117:Spt:183677.0] || -> until2p7(s36)*. % 76.16/76.38 183679[117:MRR:232.0,183678.0] || -> until2p7(s37)* node4(s36). % 76.16/76.38 183680[118:Spt:183679.0] || -> until2p7(s37)*. % 76.16/76.38 183681[118:MRR:235.0,183680.0] || -> until2p7(s38)* node4(s37). % 76.16/76.38 183682[119:Spt:183681.0] || -> until2p7(s38)*. % 76.16/76.38 183683[119:MRR:236.0,183682.0] || -> until2p7(s39)* node4(s38). % 76.16/76.38 183684[120:Spt:183683.0] || -> until2p7(s39)*. % 76.16/76.38 183685[120:MRR:237.0,183684.0] || -> until2p7(s40)* node4(s39). % 76.16/76.38 183686[121:Spt:183685.0] || -> until2p7(s40)*. % 76.16/76.38 183687[121:MRR:238.0,183686.0] || -> until2p7(s41)* node4(s40). % 76.16/76.38 183688[122:Spt:183687.0] || -> until2p7(s41)*. % 76.16/76.38 183689[122:MRR:239.0,183688.0] || -> until2p7(s42)* node4(s41). % 76.16/76.38 183690[123:Spt:183689.0] || -> until2p7(s42)*. % 76.16/76.38 183691[123:MRR:240.0,183690.0] || -> until2p7(s43)* node4(s42). % 76.16/76.38 183692[124:Spt:183691.0] || -> until2p7(s43)*. % 76.16/76.38 183693[124:MRR:241.0,183692.0] || -> until2p7(s44)* node4(s43). % 76.16/76.38 183694[125:Spt:183693.0] || -> until2p7(s44)*. % 76.16/76.38 183695[125:MRR:539.0,183694.0] || -> until2p7(s45)* node4(s44). % 76.16/76.38 183696[126:Spt:183695.0] || -> until2p7(s45)*. % 76.16/76.38 183697[126:MRR:544.0,183696.0] || -> until2p7(s46)* node4(s45). % 76.16/76.38 183698[127:Spt:183697.0] || -> until2p7(s46)*. % 76.16/76.38 183699[127:MRR:549.0,183698.0] || -> until2p7(s47)* node4(s46). % 76.16/76.38 183700[128:Spt:183699.0] || -> until2p7(s47)*. % 76.16/76.38 183701[128:MRR:554.0,183700.0] || -> until2p7(s48)* node4(s47). % 76.16/76.38 183702[129:Spt:183701.0] || -> until2p7(s48)*. % 76.16/76.38 183703[129:MRR:559.0,183702.0] || -> until2p7(s49)* node4(s48). % 76.16/76.38 183704[130:Spt:183703.0] || -> until2p7(s49)*. % 76.16/76.38 183705[130:MRR:194.0,183704.0] || -> node4(s49)*. % 76.16/76.38 183706[130:MRR:183626.0,183705.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.38 183707[130:Res:53.1,183706.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.38 183709[130:MRR:183707.0,78381.0] || -> . % 76.16/76.38 183710[130:Spt:183709.0,183703.0,183704.0] || until2p7(s49)*+ -> . % 76.16/76.38 183711[130:Spt:183709.0,183703.1] || -> node4(s48)*. % 76.16/76.38 183712[130:MRR:78384.0,183711.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.38 183715[130:Res:53.1,183712.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 183718[130:Res:183715.0,61.1] always3(s48) || -> . % 76.16/76.38 183719[130:SSi:183718.0,78281.0,78387.0,165540.0,183702.0,183711.0] || -> . % 76.16/76.38 183720[129:Spt:183719.0,183701.0,183702.0] || until2p7(s48)*+ -> . % 76.16/76.38 183721[129:Spt:183719.0,183701.1] || -> node4(s47)*. % 76.16/76.38 183723[129:MRR:777.0,183721.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.38 183738[129:Res:53.1,183723.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.38 183743[130:Spt:183738.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 183745[130:Res:183743.0,61.1] always3(s47) || -> . % 76.16/76.38 183746[130:SSi:183745.0,78277.0,78280.0,165539.0,183700.0,183721.0] || -> . % 76.16/76.38 183747[130:Spt:183746.0,183738.0,183743.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.38 183748[130:Spt:183746.0,183738.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 183752[130:Res:183748.0,61.1] always3(s48) || -> . % 76.16/76.38 183753[130:SSi:183752.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.38 183754[128:Spt:183753.0,183699.0,183700.0] || until2p7(s47)*+ -> . % 76.16/76.38 183755[128:Spt:183753.0,183699.1] || -> node4(s46)*. % 76.16/76.38 183757[128:MRR:780.0,183755.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.38 183764[128:Res:53.1,183757.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.38 183766[129:Spt:183764.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 183768[129:Res:183766.0,61.1] always3(s46) || -> . % 76.16/76.38 183769[129:SSi:183768.0,78272.0,78276.0,165538.0,183698.0,183755.0] || -> . % 76.16/76.38 183770[129:Spt:183769.0,183764.0,183766.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.38 183771[129:Spt:183769.0,183764.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 183775[129:Res:183771.0,61.1] always3(s47) || -> . % 76.16/76.38 183776[129:SSi:183775.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.38 183777[127:Spt:183776.0,183697.0,183698.0] || until2p7(s46)*+ -> . % 76.16/76.38 183778[127:Spt:183776.0,183697.1] || -> node4(s45)*. % 76.16/76.38 183780[127:MRR:783.0,183778.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.38 183783[127:Res:53.1,183780.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.38 183788[128:Spt:183783.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 183790[128:Res:183788.0,61.1] always3(s45) || -> . % 76.16/76.38 183791[128:SSi:183790.0,78268.0,78271.0,165537.0,183696.0,183778.0] || -> . % 76.16/76.38 183792[128:Spt:183791.0,183783.0,183788.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.38 183793[128:Spt:183791.0,183783.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 183797[128:Res:183793.0,61.1] always3(s46) || -> . % 76.16/76.38 183798[128:SSi:183797.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.38 183799[126:Spt:183798.0,183695.0,183696.0] || until2p7(s45)*+ -> . % 76.16/76.38 183800[126:Spt:183798.0,183695.1] || -> node4(s44)*. % 76.16/76.38 183802[126:MRR:786.0,183800.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.38 183805[126:Res:53.1,183802.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.38 183807[127:Spt:183805.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 183809[127:Res:183807.0,61.1] always3(s44) || -> . % 76.16/76.38 183810[127:SSi:183809.0,78263.0,78267.0,165536.0,183694.0,183800.0] || -> . % 76.16/76.38 183811[127:Spt:183810.0,183805.0,183807.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.38 183812[127:Spt:183810.0,183805.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 183816[127:Res:183812.0,61.1] always3(s45) || -> . % 76.16/76.38 183817[127:SSi:183816.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.38 183818[125:Spt:183817.0,183693.0,183694.0] || until2p7(s44)*+ -> . % 76.16/76.38 183819[125:Spt:183817.0,183693.1] || -> node4(s43)*. % 76.16/76.38 183821[125:MRR:789.0,183819.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.38 183824[125:Res:53.1,183821.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.38 183826[126:Spt:183824.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 183828[126:Res:183826.0,61.1] always3(s43) || -> . % 76.16/76.38 183829[126:SSi:183828.0,78259.0,78262.0,165535.0,183692.0,183819.0] || -> . % 76.16/76.38 183830[126:Spt:183829.0,183824.0,183826.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.38 183831[126:Spt:183829.0,183824.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 183835[126:Res:183831.0,61.1] always3(s44) || -> . % 76.16/76.38 183836[126:SSi:183835.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.38 183837[124:Spt:183836.0,183691.0,183692.0] || until2p7(s43)*+ -> . % 76.16/76.38 183838[124:Spt:183836.0,183691.1] || -> node4(s42)*. % 76.16/76.38 183840[124:MRR:792.0,183838.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.38 183843[124:Res:53.1,183840.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.38 183845[125:Spt:183843.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 183847[125:Res:183845.0,61.1] always3(s42) || -> . % 76.16/76.38 183848[125:SSi:183847.0,78254.0,78258.0,165534.0,183690.0,183838.0] || -> . % 76.16/76.38 183849[125:Spt:183848.0,183843.0,183845.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.38 183850[125:Spt:183848.0,183843.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 183854[125:Res:183850.0,61.1] always3(s43) || -> . % 76.16/76.38 183855[125:SSi:183854.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.38 183856[123:Spt:183855.0,183689.0,183690.0] || until2p7(s42)*+ -> . % 76.16/76.38 183857[123:Spt:183855.0,183689.1] || -> node4(s41)*. % 76.16/76.38 183859[123:MRR:795.0,183857.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.38 183862[123:Res:53.1,183859.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.38 183867[124:Spt:183862.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 183869[124:Res:183867.0,61.1] always3(s41) || -> . % 76.16/76.38 183870[124:SSi:183869.0,78250.0,78253.0,165533.0,183688.0,183857.0] || -> . % 76.16/76.38 183871[124:Spt:183870.0,183862.0,183867.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.38 183872[124:Spt:183870.0,183862.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 183876[124:Res:183872.0,61.1] always3(s42) || -> . % 76.16/76.38 183877[124:SSi:183876.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.38 183878[122:Spt:183877.0,183687.0,183688.0] || until2p7(s41)*+ -> . % 76.16/76.38 183879[122:Spt:183877.0,183687.1] || -> node4(s40)*. % 76.16/76.38 183881[122:MRR:798.0,183879.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.38 183884[122:Res:53.1,183881.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.38 183886[123:Spt:183884.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 183888[123:Res:183886.0,61.1] always3(s40) || -> . % 76.16/76.38 183889[123:SSi:183888.0,78245.0,78249.0,165532.0,183686.0,183879.0] || -> . % 76.16/76.38 183890[123:Spt:183889.0,183884.0,183886.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.38 183891[123:Spt:183889.0,183884.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 183895[123:Res:183891.0,61.1] always3(s41) || -> . % 76.16/76.38 183896[123:SSi:183895.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.38 183897[121:Spt:183896.0,183685.0,183686.0] || until2p7(s40)*+ -> . % 76.16/76.38 183898[121:Spt:183896.0,183685.1] || -> node4(s39)*. % 76.16/76.38 183900[121:MRR:801.0,183898.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.38 183903[121:Res:53.1,183900.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.38 183905[122:Spt:183903.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 183907[122:Res:183905.0,61.1] always3(s39) || -> . % 76.16/76.38 183908[122:SSi:183907.0,78241.0,78244.0,165531.0,183684.0,183898.0] || -> . % 76.16/76.38 183909[122:Spt:183908.0,183903.0,183905.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.38 183910[122:Spt:183908.0,183903.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 183914[122:Res:183910.0,61.1] always3(s40) || -> . % 76.16/76.38 183915[122:SSi:183914.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.38 183916[120:Spt:183915.0,183683.0,183684.0] || until2p7(s39)*+ -> . % 76.16/76.38 183917[120:Spt:183915.0,183683.1] || -> node4(s38)*. % 76.16/76.38 183919[120:MRR:804.0,183917.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.38 183922[120:Res:53.1,183919.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.38 183924[121:Spt:183922.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 183926[121:Res:183924.0,61.1] always3(s38) || -> . % 76.16/76.38 183927[121:SSi:183926.0,78236.0,78240.0,165530.0,183682.0,183917.0] || -> . % 76.16/76.38 183928[121:Spt:183927.0,183922.0,183924.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.38 183929[121:Spt:183927.0,183922.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 183933[121:Res:183929.0,61.1] always3(s39) || -> . % 76.16/76.38 183934[121:SSi:183933.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.38 183935[119:Spt:183934.0,183681.0,183682.0] || until2p7(s38)*+ -> . % 76.16/76.38 183936[119:Spt:183934.0,183681.1] || -> node4(s37)*. % 76.16/76.38 183938[119:MRR:807.0,183936.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.38 183941[119:Res:53.1,183938.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.38 183946[120:Spt:183941.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 183948[120:Res:183946.0,61.1] always3(s37) || -> . % 76.16/76.38 183949[120:SSi:183948.0,78232.0,78235.0,165529.0,183680.0,183936.0] || -> . % 76.16/76.38 183950[120:Spt:183949.0,183941.0,183946.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.38 183951[120:Spt:183949.0,183941.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 183955[120:Res:183951.0,61.1] always3(s38) || -> . % 76.16/76.38 183956[120:SSi:183955.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.38 183957[118:Spt:183956.0,183679.0,183680.0] || until2p7(s37)*+ -> . % 76.16/76.38 183958[118:Spt:183956.0,183679.1] || -> node4(s36)*. % 76.16/76.38 183960[118:MRR:810.0,183958.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.38 183963[118:Res:53.1,183960.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.38 183965[119:Spt:183963.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 183967[119:Res:183965.0,61.1] always3(s36) || -> . % 76.16/76.38 183968[119:SSi:183967.0,78227.0,78231.0,165528.0,183678.0,183958.0] || -> . % 76.16/76.38 183969[119:Spt:183968.0,183963.0,183965.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.38 183970[119:Spt:183968.0,183963.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 183974[119:Res:183970.0,61.1] always3(s37) || -> . % 76.16/76.38 183975[119:SSi:183974.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.38 183976[117:Spt:183975.0,183677.0,183678.0] || until2p7(s36)*+ -> . % 76.16/76.38 183977[117:Spt:183975.0,183677.1] || -> node4(s35)*. % 76.16/76.38 183979[117:MRR:813.0,183977.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.38 183982[117:Res:53.1,183979.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.38 183984[118:Spt:183982.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 183986[118:Res:183984.0,61.1] always3(s35) || -> . % 76.16/76.38 183987[118:SSi:183986.0,78223.0,78226.0,165527.0,183676.0,183977.0] || -> . % 76.16/76.38 183988[118:Spt:183987.0,183982.0,183984.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.38 183989[118:Spt:183987.0,183982.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 183993[118:Res:183989.0,61.1] always3(s36) || -> . % 76.16/76.38 183994[118:SSi:183993.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.38 183995[116:Spt:183994.0,183675.0,183676.0] || until2p7(s35)*+ -> . % 76.16/76.38 183996[116:Spt:183994.0,183675.1] || -> node4(s34)*. % 76.16/76.38 183998[116:MRR:816.0,183996.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.38 184001[116:Res:53.1,183998.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.38 184003[117:Spt:184001.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 184005[117:Res:184003.0,61.1] always3(s34) || -> . % 76.16/76.38 184006[117:SSi:184005.0,78218.0,78222.0,165526.0,183674.0,183996.0] || -> . % 76.16/76.38 184007[117:Spt:184006.0,184001.0,184003.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.38 184008[117:Spt:184006.0,184001.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 184012[117:Res:184008.0,61.1] always3(s35) || -> . % 76.16/76.38 184013[117:SSi:184012.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.38 184014[115:Spt:184013.0,183673.0,183674.0] || until2p7(s34)*+ -> . % 76.16/76.38 184015[115:Spt:184013.0,183673.1] || -> node4(s33)*. % 76.16/76.38 184017[115:MRR:819.0,184015.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.38 184020[115:Res:53.1,184017.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.38 184025[116:Spt:184020.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 184027[116:Res:184025.0,61.1] always3(s33) || -> . % 76.16/76.38 184028[116:SSi:184027.0,78214.0,78217.0,165525.0,183672.0,184015.0] || -> . % 76.16/76.38 184029[116:Spt:184028.0,184020.0,184025.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.38 184030[116:Spt:184028.0,184020.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 184034[116:Res:184030.0,61.1] always3(s34) || -> . % 76.16/76.38 184035[116:SSi:184034.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.38 184036[114:Spt:184035.0,183671.0,183672.0] || until2p7(s33)*+ -> . % 76.16/76.38 184037[114:Spt:184035.0,183671.1] || -> node4(s32)*. % 76.16/76.38 184039[114:MRR:822.0,184037.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.38 184042[114:Res:53.1,184039.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.38 184044[115:Spt:184042.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 184046[115:Res:184044.0,61.1] always3(s32) || -> . % 76.16/76.38 184047[115:SSi:184046.0,78209.0,78213.0,165524.0,183670.0,184037.0] || -> . % 76.16/76.38 184048[115:Spt:184047.0,184042.0,184044.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.38 184049[115:Spt:184047.0,184042.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 184053[115:Res:184049.0,61.1] always3(s33) || -> . % 76.16/76.38 184054[115:SSi:184053.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.38 184055[113:Spt:184054.0,183669.0,183670.0] || until2p7(s32)*+ -> . % 76.16/76.38 184056[113:Spt:184054.0,183669.1] || -> node4(s31)*. % 76.16/76.38 184058[113:MRR:825.0,184056.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.38 184061[113:Res:53.1,184058.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.38 184063[114:Spt:184061.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 184065[114:Res:184063.0,61.1] always3(s31) || -> . % 76.16/76.38 184066[114:SSi:184065.0,78205.0,78208.0,165523.0,183668.0,184056.0] || -> . % 76.16/76.38 184067[114:Spt:184066.0,184061.0,184063.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.38 184068[114:Spt:184066.0,184061.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 184072[114:Res:184068.0,61.1] always3(s32) || -> . % 76.16/76.38 184073[114:SSi:184072.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.38 184074[112:Spt:184073.0,183667.0,183668.0] || until2p7(s31)*+ -> . % 76.16/76.38 184075[112:Spt:184073.0,183667.1] || -> node4(s30)*. % 76.16/76.38 184077[112:MRR:828.0,184075.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.38 184080[112:Res:53.1,184077.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.38 184082[113:Spt:184080.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 184084[113:Res:184082.0,61.1] always3(s30) || -> . % 76.16/76.38 184085[113:SSi:184084.0,78200.0,78204.0,165522.0,183666.0,184075.0] || -> . % 76.16/76.38 184086[113:Spt:184085.0,184080.0,184082.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.38 184087[113:Spt:184085.0,184080.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 184091[113:Res:184087.0,61.1] always3(s31) || -> . % 76.16/76.38 184092[113:SSi:184091.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.38 184093[111:Spt:184092.0,183665.0,183666.0] || until2p7(s30)*+ -> . % 76.16/76.38 184094[111:Spt:184092.0,183665.1] || -> node4(s29)*. % 76.16/76.38 184096[111:MRR:831.0,184094.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.38 184099[111:Res:53.1,184096.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.38 184104[112:Spt:184099.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 184106[112:Res:184104.0,61.1] always3(s29) || -> . % 76.16/76.38 184107[112:SSi:184106.0,78196.0,78199.0,165521.0,183664.0,184094.0] || -> . % 76.16/76.38 184108[112:Spt:184107.0,184099.0,184104.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.38 184109[112:Spt:184107.0,184099.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 184113[112:Res:184109.0,61.1] always3(s30) || -> . % 76.16/76.38 184114[112:SSi:184113.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.38 184115[110:Spt:184114.0,183663.0,183664.0] || until2p7(s29)*+ -> . % 76.16/76.38 184116[110:Spt:184114.0,183663.1] || -> node4(s28)*. % 76.16/76.38 184118[110:MRR:834.0,184116.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.38 184121[110:Res:53.1,184118.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.38 184123[111:Spt:184121.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 184125[111:Res:184123.0,61.1] always3(s28) || -> . % 76.16/76.38 184126[111:SSi:184125.0,78191.0,78195.0,165520.0,183662.0,184116.0] || -> . % 76.16/76.38 184127[111:Spt:184126.0,184121.0,184123.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.38 184128[111:Spt:184126.0,184121.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 184132[111:Res:184128.0,61.1] always3(s29) || -> . % 76.16/76.38 184133[111:SSi:184132.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.38 184134[109:Spt:184133.0,183661.0,183662.0] || until2p7(s28)*+ -> . % 76.16/76.38 184135[109:Spt:184133.0,183661.1] || -> node4(s27)*. % 76.16/76.38 184137[109:MRR:837.0,184135.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.38 184140[109:Res:53.1,184137.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.38 184142[110:Spt:184140.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 184144[110:Res:184142.0,61.1] always3(s27) || -> . % 76.16/76.38 184145[110:SSi:184144.0,78187.0,78190.0,165519.0,183660.0,184135.0] || -> . % 76.16/76.38 184146[110:Spt:184145.0,184140.0,184142.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.38 184147[110:Spt:184145.0,184140.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 184151[110:Res:184147.0,61.1] always3(s28) || -> . % 76.16/76.38 184152[110:SSi:184151.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.38 184153[108:Spt:184152.0,183659.0,183660.0] || until2p7(s27)*+ -> . % 76.16/76.38 184154[108:Spt:184152.0,183659.1] || -> node4(s26)*. % 76.16/76.38 184156[108:MRR:840.0,184154.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.38 184159[108:Res:53.1,184156.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.38 184161[109:Spt:184159.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 184163[109:Res:184161.0,61.1] always3(s26) || -> . % 76.16/76.38 184164[109:SSi:184163.0,78182.0,78186.0,165518.0,183658.0,184154.0] || -> . % 76.16/76.38 184165[109:Spt:184164.0,184159.0,184161.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.38 184166[109:Spt:184164.0,184159.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 184170[109:Res:184166.0,61.1] always3(s27) || -> . % 76.16/76.38 184171[109:SSi:184170.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.38 184172[107:Spt:184171.0,183657.0,183658.0] || until2p7(s26)*+ -> . % 76.16/76.38 184173[107:Spt:184171.0,183657.1] || -> node4(s25)*. % 76.16/76.38 184175[107:MRR:843.0,184173.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.38 184178[107:Res:53.1,184175.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.38 184183[108:Spt:184178.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 184185[108:Res:184183.0,61.1] always3(s25) || -> . % 76.16/76.38 184186[108:SSi:184185.0,78178.0,78181.0,165517.0,183656.0,184173.0] || -> . % 76.16/76.38 184187[108:Spt:184186.0,184178.0,184183.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.38 184188[108:Spt:184186.0,184178.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 184192[108:Res:184188.0,61.1] always3(s26) || -> . % 76.16/76.38 184193[108:SSi:184192.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.38 184194[106:Spt:184193.0,183655.0,183656.0] || until2p7(s25)*+ -> . % 76.16/76.38 184195[106:Spt:184193.0,183655.1] || -> node4(s24)*. % 76.16/76.38 184197[106:MRR:846.0,184195.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.38 184200[106:Res:53.1,184197.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.38 184202[107:Spt:184200.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 184204[107:Res:184202.0,61.1] always3(s24) || -> . % 76.16/76.38 184205[107:SSi:184204.0,78173.0,78177.0,165516.0,183654.0,184195.0] || -> . % 76.16/76.38 184206[107:Spt:184205.0,184200.0,184202.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.38 184207[107:Spt:184205.0,184200.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 184211[107:Res:184207.0,61.1] always3(s25) || -> . % 76.16/76.38 184212[107:SSi:184211.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.38 184213[105:Spt:184212.0,183653.0,183654.0] || until2p7(s24)*+ -> . % 76.16/76.38 184214[105:Spt:184212.0,183653.1] || -> node4(s23)*. % 76.16/76.38 184216[105:MRR:849.0,184214.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.38 184219[105:Res:53.1,184216.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.38 184221[106:Spt:184219.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 184223[106:Res:184221.0,61.1] always3(s23) || -> . % 76.16/76.38 184224[106:SSi:184223.0,78169.0,78172.0,165515.0,183652.0,184214.0] || -> . % 76.16/76.38 184225[106:Spt:184224.0,184219.0,184221.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.38 184226[106:Spt:184224.0,184219.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 184230[106:Res:184226.0,61.1] always3(s24) || -> . % 76.16/76.38 184231[106:SSi:184230.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.38 184232[104:Spt:184231.0,183651.0,183652.0] || until2p7(s23)*+ -> . % 76.16/76.38 184233[104:Spt:184231.0,183651.1] || -> node4(s22)*. % 76.16/76.38 184235[104:MRR:852.0,184233.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.38 184238[104:Res:53.1,184235.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.38 184240[105:Spt:184238.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 184242[105:Res:184240.0,61.1] always3(s22) || -> . % 76.16/76.38 184243[105:SSi:184242.0,78164.0,78168.0,165514.0,183650.0,184233.0] || -> . % 76.16/76.38 184244[105:Spt:184243.0,184238.0,184240.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.38 184245[105:Spt:184243.0,184238.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 184249[105:Res:184245.0,61.1] always3(s23) || -> . % 76.16/76.38 184250[105:SSi:184249.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.38 184251[103:Spt:184250.0,183649.0,183650.0] || until2p7(s22)*+ -> . % 76.16/76.38 184252[103:Spt:184250.0,183649.1] || -> node4(s21)*. % 76.16/76.38 184254[103:MRR:855.0,184252.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.38 184257[103:Res:53.1,184254.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.38 184262[104:Spt:184257.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 184264[104:Res:184262.0,61.1] always3(s21) || -> . % 76.16/76.38 184265[104:SSi:184264.0,78160.0,78163.0,165513.0,183648.0,184252.0] || -> . % 76.16/76.38 184266[104:Spt:184265.0,184257.0,184262.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.38 184267[104:Spt:184265.0,184257.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 184271[104:Res:184267.0,61.1] always3(s22) || -> . % 76.16/76.38 184272[104:SSi:184271.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.38 184273[102:Spt:184272.0,183647.0,183648.0] || until2p7(s21)*+ -> . % 76.16/76.38 184274[102:Spt:184272.0,183647.1] || -> node4(s20)*. % 76.16/76.38 184276[102:MRR:858.0,184274.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.38 184279[102:Res:53.1,184276.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.38 184281[103:Spt:184279.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 184283[103:Res:184281.0,61.1] always3(s20) || -> . % 76.16/76.38 184284[103:SSi:184283.0,78155.0,78159.0,165512.0,183646.0,184274.0] || -> . % 76.16/76.38 184285[103:Spt:184284.0,184279.0,184281.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.38 184286[103:Spt:184284.0,184279.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 184290[103:Res:184286.0,61.1] always3(s21) || -> . % 76.16/76.38 184291[103:SSi:184290.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.38 184292[101:Spt:184291.0,183645.0,183646.0] || until2p7(s20)*+ -> . % 76.16/76.38 184293[101:Spt:184291.0,183645.1] || -> node4(s19)*. % 76.16/76.38 184295[101:MRR:861.0,184293.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.38 184298[101:Res:53.1,184295.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.38 184300[102:Spt:184298.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 184302[102:Res:184300.0,61.1] always3(s19) || -> . % 76.16/76.38 184303[102:SSi:184302.0,78151.0,78154.0,165511.0,183644.0,184293.0] || -> . % 76.16/76.38 184304[102:Spt:184303.0,184298.0,184300.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.38 184305[102:Spt:184303.0,184298.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 184309[102:Res:184305.0,61.1] always3(s20) || -> . % 76.16/76.38 184310[102:SSi:184309.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.38 184311[100:Spt:184310.0,183643.0,183644.0] || until2p7(s19)*+ -> . % 76.16/76.38 184312[100:Spt:184310.0,183643.1] || -> node4(s18)*. % 76.16/76.38 184314[100:MRR:864.0,184312.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.38 184317[100:Res:53.1,184314.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.38 184319[101:Spt:184317.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 184321[101:Res:184319.0,61.1] always3(s18) || -> . % 76.16/76.38 184322[101:SSi:184321.0,78146.0,78150.0,165510.0,183642.0,184312.0] || -> . % 76.16/76.38 184323[101:Spt:184322.0,184317.0,184319.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.38 184324[101:Spt:184322.0,184317.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 184328[101:Res:184324.0,61.1] always3(s19) || -> . % 76.16/76.38 184329[101:SSi:184328.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.38 184330[99:Spt:184329.0,183641.0,183642.0] || until2p7(s18)*+ -> . % 76.16/76.38 184331[99:Spt:184329.0,183641.1] || -> node4(s17)*. % 76.16/76.38 184333[99:MRR:867.0,184331.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.38 184336[99:Res:53.1,184333.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.38 184341[100:Spt:184336.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 184343[100:Res:184341.0,61.1] always3(s17) || -> . % 76.16/76.38 184344[100:SSi:184343.0,78142.0,78145.0,165509.0,183640.0,184331.0] || -> . % 76.16/76.38 184345[100:Spt:184344.0,184336.0,184341.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.38 184346[100:Spt:184344.0,184336.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 184350[100:Res:184346.0,61.1] always3(s18) || -> . % 76.16/76.38 184351[100:SSi:184350.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.38 184352[98:Spt:184351.0,183639.0,183640.0] || until2p7(s17)*+ -> . % 76.16/76.38 184353[98:Spt:184351.0,183639.1] || -> node4(s16)*. % 76.16/76.38 184355[98:MRR:870.0,184353.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.38 184358[98:Res:53.1,184355.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.38 184360[99:Spt:184358.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 184362[99:Res:184360.0,61.1] always3(s16) || -> . % 76.16/76.38 184363[99:SSi:184362.0,78137.0,78141.0,165508.0,183638.0,184353.0] || -> . % 76.16/76.38 184364[99:Spt:184363.0,184358.0,184360.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.38 184365[99:Spt:184363.0,184358.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 184369[99:Res:184365.0,61.1] always3(s17) || -> . % 76.16/76.38 184370[99:SSi:184369.0,78142.0,78145.0,165509.0] || -> . % 76.16/76.38 184371[97:Spt:184370.0,183637.0,183638.0] || until2p7(s16)*+ -> . % 76.16/76.38 184372[97:Spt:184370.0,183637.1] || -> node4(s15)*. % 76.16/76.38 184374[97:MRR:873.0,184372.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.38 184377[97:Res:53.1,184374.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.38 184379[98:Spt:184377.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 184381[98:Res:184379.0,61.1] always3(s15) || -> . % 76.16/76.38 184382[98:SSi:184381.0,78133.0,78136.0,165507.0,183636.0,184372.0] || -> . % 76.16/76.38 184383[98:Spt:184382.0,184377.0,184379.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.38 184384[98:Spt:184382.0,184377.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 184388[98:Res:184384.0,61.1] always3(s16) || -> . % 76.16/76.38 184389[98:SSi:184388.0,78137.0,78141.0,165508.0] || -> . % 76.16/76.38 184390[96:Spt:184389.0,183635.0,183636.0] || until2p7(s15)*+ -> . % 76.16/76.38 184391[96:Spt:184389.0,183635.1] || -> node4(s14)*. % 76.16/76.38 184393[96:MRR:876.0,184391.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.38 184396[96:Res:53.1,184393.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.38 184398[97:Spt:184396.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 184400[97:Res:184398.0,61.1] always3(s14) || -> . % 76.16/76.38 184401[97:SSi:184400.0,78128.0,78132.0,165506.0,183634.0,184391.0] || -> . % 76.16/76.38 184402[97:Spt:184401.0,184396.0,184398.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.38 184403[97:Spt:184401.0,184396.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 184407[97:Res:184403.0,61.1] always3(s15) || -> . % 76.16/76.38 184408[97:SSi:184407.0,78133.0,78136.0,165507.0] || -> . % 76.16/76.38 184409[95:Spt:184408.0,183633.0,183634.0] || until2p7(s14)*+ -> . % 76.16/76.38 184410[95:Spt:184408.0,183633.1] || -> node4(s13)*. % 76.16/76.38 184412[95:MRR:879.0,184410.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.38 184415[95:Res:53.1,184412.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.38 184420[96:Spt:184415.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 184422[96:Res:184420.0,61.1] always3(s13) || -> . % 76.16/76.38 184423[96:SSi:184422.0,78124.0,78127.0,165505.0,183632.0,184410.0] || -> . % 76.16/76.38 184424[96:Spt:184423.0,184415.0,184420.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.38 184425[96:Spt:184423.0,184415.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 184429[96:Res:184425.0,61.1] always3(s14) || -> . % 76.16/76.38 184430[96:SSi:184429.0,78128.0,78132.0,165506.0] || -> . % 76.16/76.38 184431[94:Spt:184430.0,183631.0,183632.0] || until2p7(s13)*+ -> . % 76.16/76.38 184432[94:Spt:184430.0,183631.1] || -> node4(s12)*. % 76.16/76.38 184434[94:MRR:882.0,184432.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.38 184437[94:Res:53.1,184434.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.38 184439[94:MRR:184437.0,183621.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 184441[94:Res:184439.0,61.1] always3(s13) || -> . % 76.16/76.38 184442[94:SSi:184441.0,78124.0,78127.0,165505.0] || -> . % 76.16/76.38 184443[92:Spt:184442.0,183481.0,183484.0] || trans(s49,s12)*+ -> . % 76.16/76.38 184444[92:Spt:184442.0,183481.1,183481.2,183481.3,183481.4,183481.5,183481.6,183481.7] || -> trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.38 184446[92:MRR:183483.1,184443.0] xuntil6(s49) || -> trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.38 184447[93:Spt:184444.0] || -> trans(s49,s11)*. % 76.16/76.38 184448[93:Res:184447.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s11)*. % 76.16/76.38 184450[93:Res:184447.0,60.0] || -> node2(s49,s11)*. % 76.16/76.38 184451[93:SSi:184448.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s11)*. % 76.16/76.38 184452[93:Res:184450.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)*. % 76.16/76.38 184577[93:SoR:184452.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)*. % 76.16/76.38 184579[93:SoR:184577.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)* xuntil6(s49). % 76.16/76.38 184580[93:SSi:184579.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s11,c_busy)* xuntil6(s49). % 76.16/76.38 184581[94:Spt:184580.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.38 184583[94:Res:184581.0,61.1] always3(s11) || -> . % 76.16/76.38 184584[94:SSi:184583.0,78115.0,78118.0,165503.0] || -> . % 76.16/76.38 184585[94:Spt:184584.0,184580.1,184581.0] || m_main_v_state(s11,c_busy)*+ -> . % 76.16/76.38 184586[94:Spt:184584.0,184580.0,184580.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.38 184590[94:MRR:184577.2,184585.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.38 184591[94:Res:53.1,184586.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.38 184593[94:MRR:184591.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.38 184594[94:MRR:184451.0,184593.0] || -> until2p7(s11)*. % 76.16/76.38 184595[94:MRR:207.0,184594.0] || -> until2p7(s12)* node4(s11). % 76.16/76.38 184596[95:Spt:184595.0] || -> until2p7(s12)*. % 76.16/76.38 184597[95:MRR:208.0,184596.0] || -> until2p7(s13)* node4(s12). % 76.16/76.38 184598[96:Spt:184597.0] || -> until2p7(s13)*. % 76.16/76.38 184599[96:MRR:209.0,184598.0] || -> until2p7(s14)* node4(s13). % 76.16/76.38 184600[97:Spt:184599.0] || -> until2p7(s14)*. % 76.16/76.38 184601[97:MRR:210.0,184600.0] || -> until2p7(s15)* node4(s14). % 76.16/76.38 184602[98:Spt:184601.0] || -> until2p7(s15)*. % 76.16/76.38 184603[98:MRR:211.0,184602.0] || -> until2p7(s16)* node4(s15). % 76.16/76.38 184604[99:Spt:184603.0] || -> until2p7(s16)*. % 76.16/76.38 184605[99:MRR:212.0,184604.0] || -> until2p7(s17)* node4(s16). % 76.16/76.38 184606[100:Spt:184605.0] || -> until2p7(s17)*. % 76.16/76.38 184607[100:MRR:213.0,184606.0] || -> until2p7(s18)* node4(s17). % 76.16/76.38 184608[101:Spt:184607.0] || -> until2p7(s18)*. % 76.16/76.38 184609[101:MRR:214.0,184608.0] || -> until2p7(s19)* node4(s18). % 76.16/76.38 184610[102:Spt:184609.0] || -> until2p7(s19)*. % 76.16/76.38 184611[102:MRR:215.0,184610.0] || -> until2p7(s20)* node4(s19). % 76.16/76.38 184612[103:Spt:184611.0] || -> until2p7(s20)*. % 76.16/76.38 184613[103:MRR:216.0,184612.0] || -> until2p7(s21)* node4(s20). % 76.16/76.38 184614[104:Spt:184613.0] || -> until2p7(s21)*. % 76.16/76.38 184615[104:MRR:217.0,184614.0] || -> until2p7(s22)* node4(s21). % 76.16/76.38 184616[105:Spt:184615.0] || -> until2p7(s22)*. % 76.16/76.38 184617[105:MRR:218.0,184616.0] || -> until2p7(s23)* node4(s22). % 76.16/76.38 184618[106:Spt:184617.0] || -> until2p7(s23)*. % 76.16/76.38 184619[106:MRR:219.0,184618.0] || -> until2p7(s24)* node4(s23). % 76.16/76.38 184620[107:Spt:184619.0] || -> until2p7(s24)*. % 76.16/76.38 184621[107:MRR:220.0,184620.0] || -> until2p7(s25)* node4(s24). % 76.16/76.38 184622[108:Spt:184621.0] || -> until2p7(s25)*. % 76.16/76.38 184623[108:MRR:221.0,184622.0] || -> until2p7(s26)* node4(s25). % 76.16/76.38 184624[109:Spt:184623.0] || -> until2p7(s26)*. % 76.16/76.38 184625[109:MRR:222.0,184624.0] || -> until2p7(s27)* node4(s26). % 76.16/76.38 184626[110:Spt:184625.0] || -> until2p7(s27)*. % 76.16/76.38 184627[110:MRR:223.0,184626.0] || -> until2p7(s28)* node4(s27). % 76.16/76.38 184628[111:Spt:184627.0] || -> until2p7(s28)*. % 76.16/76.38 184629[111:MRR:224.0,184628.0] || -> until2p7(s29)* node4(s28). % 76.16/76.38 184630[112:Spt:184629.0] || -> until2p7(s29)*. % 76.16/76.38 184631[112:MRR:225.0,184630.0] || -> until2p7(s30)* node4(s29). % 76.16/76.38 184632[113:Spt:184631.0] || -> until2p7(s30)*. % 76.16/76.38 184633[113:MRR:226.0,184632.0] || -> until2p7(s31)* node4(s30). % 76.16/76.38 184634[114:Spt:184633.0] || -> until2p7(s31)*. % 76.16/76.38 184635[114:MRR:227.0,184634.0] || -> until2p7(s32)* node4(s31). % 76.16/76.38 184636[115:Spt:184635.0] || -> until2p7(s32)*. % 76.16/76.38 184637[115:MRR:228.0,184636.0] || -> until2p7(s33)* node4(s32). % 76.16/76.38 184638[116:Spt:184637.0] || -> until2p7(s33)*. % 76.16/76.38 184639[116:MRR:229.0,184638.0] || -> until2p7(s34)* node4(s33). % 76.16/76.38 184640[117:Spt:184639.0] || -> until2p7(s34)*. % 76.16/76.38 184641[117:MRR:230.0,184640.0] || -> until2p7(s35)* node4(s34). % 76.16/76.38 184642[118:Spt:184641.0] || -> until2p7(s35)*. % 76.16/76.38 184643[118:MRR:231.0,184642.0] || -> until2p7(s36)* node4(s35). % 76.16/76.38 184644[119:Spt:184643.0] || -> until2p7(s36)*. % 76.16/76.38 184645[119:MRR:232.0,184644.0] || -> until2p7(s37)* node4(s36). % 76.16/76.38 184646[120:Spt:184645.0] || -> until2p7(s37)*. % 76.16/76.38 184647[120:MRR:235.0,184646.0] || -> until2p7(s38)* node4(s37). % 76.16/76.38 184648[121:Spt:184647.0] || -> until2p7(s38)*. % 76.16/76.38 184649[121:MRR:236.0,184648.0] || -> until2p7(s39)* node4(s38). % 76.16/76.38 184650[122:Spt:184649.0] || -> until2p7(s39)*. % 76.16/76.38 184651[122:MRR:237.0,184650.0] || -> until2p7(s40)* node4(s39). % 76.16/76.38 184652[123:Spt:184651.0] || -> until2p7(s40)*. % 76.16/76.38 184653[123:MRR:238.0,184652.0] || -> until2p7(s41)* node4(s40). % 76.16/76.38 184654[124:Spt:184653.0] || -> until2p7(s41)*. % 76.16/76.38 184655[124:MRR:239.0,184654.0] || -> until2p7(s42)* node4(s41). % 76.16/76.38 184656[125:Spt:184655.0] || -> until2p7(s42)*. % 76.16/76.38 184657[125:MRR:240.0,184656.0] || -> until2p7(s43)* node4(s42). % 76.16/76.38 184658[126:Spt:184657.0] || -> until2p7(s43)*. % 76.16/76.38 184659[126:MRR:241.0,184658.0] || -> until2p7(s44)* node4(s43). % 76.16/76.38 184660[127:Spt:184659.0] || -> until2p7(s44)*. % 76.16/76.38 184661[127:MRR:539.0,184660.0] || -> until2p7(s45)* node4(s44). % 76.16/76.38 184662[128:Spt:184661.0] || -> until2p7(s45)*. % 76.16/76.38 184663[128:MRR:544.0,184662.0] || -> until2p7(s46)* node4(s45). % 76.16/76.38 184664[129:Spt:184663.0] || -> until2p7(s46)*. % 76.16/76.38 184665[129:MRR:549.0,184664.0] || -> until2p7(s47)* node4(s46). % 76.16/76.38 184666[130:Spt:184665.0] || -> until2p7(s47)*. % 76.16/76.38 184667[130:MRR:554.0,184666.0] || -> until2p7(s48)* node4(s47). % 76.16/76.38 184668[131:Spt:184667.0] || -> until2p7(s48)*. % 76.16/76.38 184669[131:MRR:559.0,184668.0] || -> until2p7(s49)* node4(s48). % 76.16/76.38 184670[132:Spt:184669.0] || -> until2p7(s49)*. % 76.16/76.38 184671[132:MRR:194.0,184670.0] || -> node4(s49)*. % 76.16/76.38 184672[132:MRR:184590.0,184671.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.38 184676[132:Res:53.1,184672.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.38 184678[132:MRR:184676.0,78381.0] || -> . % 76.16/76.38 184679[132:Spt:184678.0,184669.0,184670.0] || until2p7(s49)*+ -> . % 76.16/76.38 184680[132:Spt:184678.0,184669.1] || -> node4(s48)*. % 76.16/76.38 184681[132:MRR:78384.0,184680.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.38 184684[132:Res:53.1,184681.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 184687[132:Res:184684.0,61.1] always3(s48) || -> . % 76.16/76.38 184688[132:SSi:184687.0,78281.0,78387.0,165540.0,184668.0,184680.0] || -> . % 76.16/76.38 184689[131:Spt:184688.0,184667.0,184668.0] || until2p7(s48)*+ -> . % 76.16/76.38 184690[131:Spt:184688.0,184667.1] || -> node4(s47)*. % 76.16/76.38 184692[131:MRR:777.0,184690.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.38 184704[131:Res:53.1,184692.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.38 184706[132:Spt:184704.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 184708[132:Res:184706.0,61.1] always3(s47) || -> . % 76.16/76.38 184709[132:SSi:184708.0,78277.0,78280.0,165539.0,184666.0,184690.0] || -> . % 76.16/76.38 184710[132:Spt:184709.0,184704.0,184706.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.38 184711[132:Spt:184709.0,184704.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 184715[132:Res:184711.0,61.1] always3(s48) || -> . % 76.16/76.38 184716[132:SSi:184715.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.38 184717[130:Spt:184716.0,184665.0,184666.0] || until2p7(s47)*+ -> . % 76.16/76.38 184718[130:Spt:184716.0,184665.1] || -> node4(s46)*. % 76.16/76.38 184720[130:MRR:780.0,184718.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.38 184727[130:Res:53.1,184720.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.38 184732[131:Spt:184727.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 184734[131:Res:184732.0,61.1] always3(s46) || -> . % 76.16/76.38 184735[131:SSi:184734.0,78272.0,78276.0,165538.0,184664.0,184718.0] || -> . % 76.16/76.38 184736[131:Spt:184735.0,184727.0,184732.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.38 184737[131:Spt:184735.0,184727.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 184741[131:Res:184737.0,61.1] always3(s47) || -> . % 76.16/76.38 184742[131:SSi:184741.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.38 184743[129:Spt:184742.0,184663.0,184664.0] || until2p7(s46)*+ -> . % 76.16/76.38 184744[129:Spt:184742.0,184663.1] || -> node4(s45)*. % 76.16/76.38 184746[129:MRR:783.0,184744.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.38 184749[129:Res:53.1,184746.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.38 184751[130:Spt:184749.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 184753[130:Res:184751.0,61.1] always3(s45) || -> . % 76.16/76.38 184754[130:SSi:184753.0,78268.0,78271.0,165537.0,184662.0,184744.0] || -> . % 76.16/76.38 184755[130:Spt:184754.0,184749.0,184751.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.38 184756[130:Spt:184754.0,184749.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 184760[130:Res:184756.0,61.1] always3(s46) || -> . % 76.16/76.38 184761[130:SSi:184760.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.38 184762[128:Spt:184761.0,184661.0,184662.0] || until2p7(s45)*+ -> . % 76.16/76.38 184763[128:Spt:184761.0,184661.1] || -> node4(s44)*. % 76.16/76.38 184765[128:MRR:786.0,184763.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.38 184768[128:Res:53.1,184765.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.38 184770[129:Spt:184768.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 184772[129:Res:184770.0,61.1] always3(s44) || -> . % 76.16/76.38 184773[129:SSi:184772.0,78263.0,78267.0,165536.0,184660.0,184763.0] || -> . % 76.16/76.38 184774[129:Spt:184773.0,184768.0,184770.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.38 184775[129:Spt:184773.0,184768.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 184779[129:Res:184775.0,61.1] always3(s45) || -> . % 76.16/76.38 184780[129:SSi:184779.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.38 184781[127:Spt:184780.0,184659.0,184660.0] || until2p7(s44)*+ -> . % 76.16/76.38 184782[127:Spt:184780.0,184659.1] || -> node4(s43)*. % 76.16/76.38 184784[127:MRR:789.0,184782.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.38 184787[127:Res:53.1,184784.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.38 184789[128:Spt:184787.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 184791[128:Res:184789.0,61.1] always3(s43) || -> . % 76.16/76.38 184792[128:SSi:184791.0,78259.0,78262.0,165535.0,184658.0,184782.0] || -> . % 76.16/76.38 184793[128:Spt:184792.0,184787.0,184789.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.38 184794[128:Spt:184792.0,184787.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 184798[128:Res:184794.0,61.1] always3(s44) || -> . % 76.16/76.38 184799[128:SSi:184798.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.38 184800[126:Spt:184799.0,184657.0,184658.0] || until2p7(s43)*+ -> . % 76.16/76.38 184801[126:Spt:184799.0,184657.1] || -> node4(s42)*. % 76.16/76.38 184803[126:MRR:792.0,184801.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.38 184806[126:Res:53.1,184803.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.38 184811[127:Spt:184806.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 184813[127:Res:184811.0,61.1] always3(s42) || -> . % 76.16/76.38 184814[127:SSi:184813.0,78254.0,78258.0,165534.0,184656.0,184801.0] || -> . % 76.16/76.38 184815[127:Spt:184814.0,184806.0,184811.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.38 184816[127:Spt:184814.0,184806.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 184820[127:Res:184816.0,61.1] always3(s43) || -> . % 76.16/76.38 184821[127:SSi:184820.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.38 184822[125:Spt:184821.0,184655.0,184656.0] || until2p7(s42)*+ -> . % 76.16/76.38 184823[125:Spt:184821.0,184655.1] || -> node4(s41)*. % 76.16/76.38 184825[125:MRR:795.0,184823.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.38 184828[125:Res:53.1,184825.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.38 184830[126:Spt:184828.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 184832[126:Res:184830.0,61.1] always3(s41) || -> . % 76.16/76.38 184833[126:SSi:184832.0,78250.0,78253.0,165533.0,184654.0,184823.0] || -> . % 76.16/76.38 184834[126:Spt:184833.0,184828.0,184830.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.38 184835[126:Spt:184833.0,184828.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 184839[126:Res:184835.0,61.1] always3(s42) || -> . % 76.16/76.38 184840[126:SSi:184839.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.38 184841[124:Spt:184840.0,184653.0,184654.0] || until2p7(s41)*+ -> . % 76.16/76.38 184842[124:Spt:184840.0,184653.1] || -> node4(s40)*. % 76.16/76.38 184844[124:MRR:798.0,184842.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.38 184847[124:Res:53.1,184844.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.38 184849[125:Spt:184847.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 184851[125:Res:184849.0,61.1] always3(s40) || -> . % 76.16/76.38 184852[125:SSi:184851.0,78245.0,78249.0,165532.0,184652.0,184842.0] || -> . % 76.16/76.38 184853[125:Spt:184852.0,184847.0,184849.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.38 184854[125:Spt:184852.0,184847.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 184858[125:Res:184854.0,61.1] always3(s41) || -> . % 76.16/76.38 184859[125:SSi:184858.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.38 184860[123:Spt:184859.0,184651.0,184652.0] || until2p7(s40)*+ -> . % 76.16/76.38 184861[123:Spt:184859.0,184651.1] || -> node4(s39)*. % 76.16/76.38 184863[123:MRR:801.0,184861.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.38 184866[123:Res:53.1,184863.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.38 184868[124:Spt:184866.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 184870[124:Res:184868.0,61.1] always3(s39) || -> . % 76.16/76.38 184871[124:SSi:184870.0,78241.0,78244.0,165531.0,184650.0,184861.0] || -> . % 76.16/76.38 184872[124:Spt:184871.0,184866.0,184868.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.38 184873[124:Spt:184871.0,184866.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 184877[124:Res:184873.0,61.1] always3(s40) || -> . % 76.16/76.38 184878[124:SSi:184877.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.38 184879[122:Spt:184878.0,184649.0,184650.0] || until2p7(s39)*+ -> . % 76.16/76.38 184880[122:Spt:184878.0,184649.1] || -> node4(s38)*. % 76.16/76.38 184882[122:MRR:804.0,184880.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.38 184885[122:Res:53.1,184882.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.38 184890[123:Spt:184885.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 184892[123:Res:184890.0,61.1] always3(s38) || -> . % 76.16/76.38 184893[123:SSi:184892.0,78236.0,78240.0,165530.0,184648.0,184880.0] || -> . % 76.16/76.38 184894[123:Spt:184893.0,184885.0,184890.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.38 184895[123:Spt:184893.0,184885.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 184899[123:Res:184895.0,61.1] always3(s39) || -> . % 76.16/76.38 184900[123:SSi:184899.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.38 184901[121:Spt:184900.0,184647.0,184648.0] || until2p7(s38)*+ -> . % 76.16/76.38 184902[121:Spt:184900.0,184647.1] || -> node4(s37)*. % 76.16/76.38 184904[121:MRR:807.0,184902.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.38 184907[121:Res:53.1,184904.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.38 184909[122:Spt:184907.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 184911[122:Res:184909.0,61.1] always3(s37) || -> . % 76.16/76.38 184912[122:SSi:184911.0,78232.0,78235.0,165529.0,184646.0,184902.0] || -> . % 76.16/76.38 184913[122:Spt:184912.0,184907.0,184909.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.38 184914[122:Spt:184912.0,184907.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 184918[122:Res:184914.0,61.1] always3(s38) || -> . % 76.16/76.38 184919[122:SSi:184918.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.38 184920[120:Spt:184919.0,184645.0,184646.0] || until2p7(s37)*+ -> . % 76.16/76.38 184921[120:Spt:184919.0,184645.1] || -> node4(s36)*. % 76.16/76.38 184923[120:MRR:810.0,184921.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.38 184926[120:Res:53.1,184923.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.38 184928[121:Spt:184926.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 184930[121:Res:184928.0,61.1] always3(s36) || -> . % 76.16/76.38 184931[121:SSi:184930.0,78227.0,78231.0,165528.0,184644.0,184921.0] || -> . % 76.16/76.38 184932[121:Spt:184931.0,184926.0,184928.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.38 184933[121:Spt:184931.0,184926.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 184937[121:Res:184933.0,61.1] always3(s37) || -> . % 76.16/76.38 184938[121:SSi:184937.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.38 184939[119:Spt:184938.0,184643.0,184644.0] || until2p7(s36)*+ -> . % 76.16/76.38 184940[119:Spt:184938.0,184643.1] || -> node4(s35)*. % 76.16/76.38 184942[119:MRR:813.0,184940.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.38 184945[119:Res:53.1,184942.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.38 184947[120:Spt:184945.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 184949[120:Res:184947.0,61.1] always3(s35) || -> . % 76.16/76.38 184950[120:SSi:184949.0,78223.0,78226.0,165527.0,184642.0,184940.0] || -> . % 76.16/76.38 184951[120:Spt:184950.0,184945.0,184947.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.38 184952[120:Spt:184950.0,184945.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 184956[120:Res:184952.0,61.1] always3(s36) || -> . % 76.16/76.38 184957[120:SSi:184956.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.38 184958[118:Spt:184957.0,184641.0,184642.0] || until2p7(s35)*+ -> . % 76.16/76.38 184959[118:Spt:184957.0,184641.1] || -> node4(s34)*. % 76.16/76.38 184961[118:MRR:816.0,184959.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.38 184964[118:Res:53.1,184961.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.38 184969[119:Spt:184964.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 184971[119:Res:184969.0,61.1] always3(s34) || -> . % 76.16/76.38 184972[119:SSi:184971.0,78218.0,78222.0,165526.0,184640.0,184959.0] || -> . % 76.16/76.38 184973[119:Spt:184972.0,184964.0,184969.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.38 184974[119:Spt:184972.0,184964.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 184978[119:Res:184974.0,61.1] always3(s35) || -> . % 76.16/76.38 184979[119:SSi:184978.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.38 184980[117:Spt:184979.0,184639.0,184640.0] || until2p7(s34)*+ -> . % 76.16/76.38 184981[117:Spt:184979.0,184639.1] || -> node4(s33)*. % 76.16/76.38 184983[117:MRR:819.0,184981.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.38 184986[117:Res:53.1,184983.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.38 184988[118:Spt:184986.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 184990[118:Res:184988.0,61.1] always3(s33) || -> . % 76.16/76.38 184991[118:SSi:184990.0,78214.0,78217.0,165525.0,184638.0,184981.0] || -> . % 76.16/76.38 184992[118:Spt:184991.0,184986.0,184988.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.38 184993[118:Spt:184991.0,184986.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 184997[118:Res:184993.0,61.1] always3(s34) || -> . % 76.16/76.38 184998[118:SSi:184997.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.38 184999[116:Spt:184998.0,184637.0,184638.0] || until2p7(s33)*+ -> . % 76.16/76.38 185000[116:Spt:184998.0,184637.1] || -> node4(s32)*. % 76.16/76.38 185002[116:MRR:822.0,185000.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.38 185005[116:Res:53.1,185002.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.38 185007[117:Spt:185005.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 185009[117:Res:185007.0,61.1] always3(s32) || -> . % 76.16/76.38 185010[117:SSi:185009.0,78209.0,78213.0,165524.0,184636.0,185000.0] || -> . % 76.16/76.38 185011[117:Spt:185010.0,185005.0,185007.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.38 185012[117:Spt:185010.0,185005.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 185016[117:Res:185012.0,61.1] always3(s33) || -> . % 76.16/76.38 185017[117:SSi:185016.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.38 185018[115:Spt:185017.0,184635.0,184636.0] || until2p7(s32)*+ -> . % 76.16/76.38 185019[115:Spt:185017.0,184635.1] || -> node4(s31)*. % 76.16/76.38 185021[115:MRR:825.0,185019.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.38 185024[115:Res:53.1,185021.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.38 185026[116:Spt:185024.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 185028[116:Res:185026.0,61.1] always3(s31) || -> . % 76.16/76.38 185029[116:SSi:185028.0,78205.0,78208.0,165523.0,184634.0,185019.0] || -> . % 76.16/76.38 185030[116:Spt:185029.0,185024.0,185026.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.38 185031[116:Spt:185029.0,185024.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 185035[116:Res:185031.0,61.1] always3(s32) || -> . % 76.16/76.38 185036[116:SSi:185035.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.38 185037[114:Spt:185036.0,184633.0,184634.0] || until2p7(s31)*+ -> . % 76.16/76.38 185038[114:Spt:185036.0,184633.1] || -> node4(s30)*. % 76.16/76.38 185040[114:MRR:828.0,185038.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.38 185043[114:Res:53.1,185040.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.38 185048[115:Spt:185043.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 185050[115:Res:185048.0,61.1] always3(s30) || -> . % 76.16/76.38 185051[115:SSi:185050.0,78200.0,78204.0,165522.0,184632.0,185038.0] || -> . % 76.16/76.38 185052[115:Spt:185051.0,185043.0,185048.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.38 185053[115:Spt:185051.0,185043.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 185057[115:Res:185053.0,61.1] always3(s31) || -> . % 76.16/76.38 185058[115:SSi:185057.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.38 185059[113:Spt:185058.0,184631.0,184632.0] || until2p7(s30)*+ -> . % 76.16/76.38 185060[113:Spt:185058.0,184631.1] || -> node4(s29)*. % 76.16/76.38 185062[113:MRR:831.0,185060.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.38 185065[113:Res:53.1,185062.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.38 185067[114:Spt:185065.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 185069[114:Res:185067.0,61.1] always3(s29) || -> . % 76.16/76.38 185070[114:SSi:185069.0,78196.0,78199.0,165521.0,184630.0,185060.0] || -> . % 76.16/76.38 185071[114:Spt:185070.0,185065.0,185067.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.38 185072[114:Spt:185070.0,185065.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 185076[114:Res:185072.0,61.1] always3(s30) || -> . % 76.16/76.38 185077[114:SSi:185076.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.38 185078[112:Spt:185077.0,184629.0,184630.0] || until2p7(s29)*+ -> . % 76.16/76.38 185079[112:Spt:185077.0,184629.1] || -> node4(s28)*. % 76.16/76.38 185081[112:MRR:834.0,185079.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.38 185084[112:Res:53.1,185081.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.38 185086[113:Spt:185084.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 185088[113:Res:185086.0,61.1] always3(s28) || -> . % 76.16/76.38 185089[113:SSi:185088.0,78191.0,78195.0,165520.0,184628.0,185079.0] || -> . % 76.16/76.38 185090[113:Spt:185089.0,185084.0,185086.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.38 185091[113:Spt:185089.0,185084.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 185095[113:Res:185091.0,61.1] always3(s29) || -> . % 76.16/76.38 185096[113:SSi:185095.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.38 185097[111:Spt:185096.0,184627.0,184628.0] || until2p7(s28)*+ -> . % 76.16/76.38 185098[111:Spt:185096.0,184627.1] || -> node4(s27)*. % 76.16/76.38 185100[111:MRR:837.0,185098.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.38 185103[111:Res:53.1,185100.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.38 185105[112:Spt:185103.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 185107[112:Res:185105.0,61.1] always3(s27) || -> . % 76.16/76.38 185108[112:SSi:185107.0,78187.0,78190.0,165519.0,184626.0,185098.0] || -> . % 76.16/76.38 185109[112:Spt:185108.0,185103.0,185105.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.38 185110[112:Spt:185108.0,185103.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 185114[112:Res:185110.0,61.1] always3(s28) || -> . % 76.16/76.38 185115[112:SSi:185114.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.38 185116[110:Spt:185115.0,184625.0,184626.0] || until2p7(s27)*+ -> . % 76.16/76.38 185117[110:Spt:185115.0,184625.1] || -> node4(s26)*. % 76.16/76.38 185119[110:MRR:840.0,185117.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.38 185122[110:Res:53.1,185119.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.38 185127[111:Spt:185122.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 185129[111:Res:185127.0,61.1] always3(s26) || -> . % 76.16/76.38 185130[111:SSi:185129.0,78182.0,78186.0,165518.0,184624.0,185117.0] || -> . % 76.16/76.38 185131[111:Spt:185130.0,185122.0,185127.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.38 185132[111:Spt:185130.0,185122.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 185136[111:Res:185132.0,61.1] always3(s27) || -> . % 76.16/76.38 185137[111:SSi:185136.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.38 185138[109:Spt:185137.0,184623.0,184624.0] || until2p7(s26)*+ -> . % 76.16/76.38 185139[109:Spt:185137.0,184623.1] || -> node4(s25)*. % 76.16/76.38 185141[109:MRR:843.0,185139.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.38 185144[109:Res:53.1,185141.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.38 185146[110:Spt:185144.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 185148[110:Res:185146.0,61.1] always3(s25) || -> . % 76.16/76.38 185149[110:SSi:185148.0,78178.0,78181.0,165517.0,184622.0,185139.0] || -> . % 76.16/76.38 185150[110:Spt:185149.0,185144.0,185146.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.38 185151[110:Spt:185149.0,185144.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 185155[110:Res:185151.0,61.1] always3(s26) || -> . % 76.16/76.38 185156[110:SSi:185155.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.38 185157[108:Spt:185156.0,184621.0,184622.0] || until2p7(s25)*+ -> . % 76.16/76.38 185158[108:Spt:185156.0,184621.1] || -> node4(s24)*. % 76.16/76.38 185160[108:MRR:846.0,185158.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.38 185163[108:Res:53.1,185160.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.38 185165[109:Spt:185163.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 185167[109:Res:185165.0,61.1] always3(s24) || -> . % 76.16/76.38 185168[109:SSi:185167.0,78173.0,78177.0,165516.0,184620.0,185158.0] || -> . % 76.16/76.38 185169[109:Spt:185168.0,185163.0,185165.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.38 185170[109:Spt:185168.0,185163.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 185174[109:Res:185170.0,61.1] always3(s25) || -> . % 76.16/76.38 185175[109:SSi:185174.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.38 185176[107:Spt:185175.0,184619.0,184620.0] || until2p7(s24)*+ -> . % 76.16/76.38 185177[107:Spt:185175.0,184619.1] || -> node4(s23)*. % 76.16/76.38 185179[107:MRR:849.0,185177.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.38 185182[107:Res:53.1,185179.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.38 185184[108:Spt:185182.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 185186[108:Res:185184.0,61.1] always3(s23) || -> . % 76.16/76.38 185187[108:SSi:185186.0,78169.0,78172.0,165515.0,184618.0,185177.0] || -> . % 76.16/76.38 185188[108:Spt:185187.0,185182.0,185184.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.38 185189[108:Spt:185187.0,185182.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 185193[108:Res:185189.0,61.1] always3(s24) || -> . % 76.16/76.38 185194[108:SSi:185193.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.38 185195[106:Spt:185194.0,184617.0,184618.0] || until2p7(s23)*+ -> . % 76.16/76.38 185196[106:Spt:185194.0,184617.1] || -> node4(s22)*. % 76.16/76.38 185198[106:MRR:852.0,185196.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.38 185201[106:Res:53.1,185198.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.38 185206[107:Spt:185201.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 185208[107:Res:185206.0,61.1] always3(s22) || -> . % 76.16/76.38 185209[107:SSi:185208.0,78164.0,78168.0,165514.0,184616.0,185196.0] || -> . % 76.16/76.38 185210[107:Spt:185209.0,185201.0,185206.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.38 185211[107:Spt:185209.0,185201.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 185215[107:Res:185211.0,61.1] always3(s23) || -> . % 76.16/76.38 185216[107:SSi:185215.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.38 185217[105:Spt:185216.0,184615.0,184616.0] || until2p7(s22)*+ -> . % 76.16/76.38 185218[105:Spt:185216.0,184615.1] || -> node4(s21)*. % 76.16/76.38 185220[105:MRR:855.0,185218.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.38 185223[105:Res:53.1,185220.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.38 185225[106:Spt:185223.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 185227[106:Res:185225.0,61.1] always3(s21) || -> . % 76.16/76.38 185228[106:SSi:185227.0,78160.0,78163.0,165513.0,184614.0,185218.0] || -> . % 76.16/76.38 185229[106:Spt:185228.0,185223.0,185225.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.38 185230[106:Spt:185228.0,185223.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 185234[106:Res:185230.0,61.1] always3(s22) || -> . % 76.16/76.38 185235[106:SSi:185234.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.38 185236[104:Spt:185235.0,184613.0,184614.0] || until2p7(s21)*+ -> . % 76.16/76.38 185237[104:Spt:185235.0,184613.1] || -> node4(s20)*. % 76.16/76.38 185239[104:MRR:858.0,185237.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.38 185242[104:Res:53.1,185239.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.38 185244[105:Spt:185242.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 185246[105:Res:185244.0,61.1] always3(s20) || -> . % 76.16/76.38 185247[105:SSi:185246.0,78155.0,78159.0,165512.0,184612.0,185237.0] || -> . % 76.16/76.38 185248[105:Spt:185247.0,185242.0,185244.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.38 185249[105:Spt:185247.0,185242.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 185253[105:Res:185249.0,61.1] always3(s21) || -> . % 76.16/76.38 185254[105:SSi:185253.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.38 185255[103:Spt:185254.0,184611.0,184612.0] || until2p7(s20)*+ -> . % 76.16/76.38 185256[103:Spt:185254.0,184611.1] || -> node4(s19)*. % 76.16/76.38 185258[103:MRR:861.0,185256.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.38 185261[103:Res:53.1,185258.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.38 185263[104:Spt:185261.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 185265[104:Res:185263.0,61.1] always3(s19) || -> . % 76.16/76.38 185266[104:SSi:185265.0,78151.0,78154.0,165511.0,184610.0,185256.0] || -> . % 76.16/76.38 185267[104:Spt:185266.0,185261.0,185263.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.38 185268[104:Spt:185266.0,185261.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 185272[104:Res:185268.0,61.1] always3(s20) || -> . % 76.16/76.38 185273[104:SSi:185272.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.38 185274[102:Spt:185273.0,184609.0,184610.0] || until2p7(s19)*+ -> . % 76.16/76.38 185275[102:Spt:185273.0,184609.1] || -> node4(s18)*. % 76.16/76.38 185277[102:MRR:864.0,185275.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.38 185280[102:Res:53.1,185277.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.38 185285[103:Spt:185280.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 185287[103:Res:185285.0,61.1] always3(s18) || -> . % 76.16/76.38 185288[103:SSi:185287.0,78146.0,78150.0,165510.0,184608.0,185275.0] || -> . % 76.16/76.38 185289[103:Spt:185288.0,185280.0,185285.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.38 185290[103:Spt:185288.0,185280.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 185294[103:Res:185290.0,61.1] always3(s19) || -> . % 76.16/76.38 185295[103:SSi:185294.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.38 185296[101:Spt:185295.0,184607.0,184608.0] || until2p7(s18)*+ -> . % 76.16/76.38 185297[101:Spt:185295.0,184607.1] || -> node4(s17)*. % 76.16/76.38 185299[101:MRR:867.0,185297.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.38 185302[101:Res:53.1,185299.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.38 185304[102:Spt:185302.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 185306[102:Res:185304.0,61.1] always3(s17) || -> . % 76.16/76.38 185307[102:SSi:185306.0,78142.0,78145.0,165509.0,184606.0,185297.0] || -> . % 76.16/76.38 185308[102:Spt:185307.0,185302.0,185304.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.38 185309[102:Spt:185307.0,185302.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 185313[102:Res:185309.0,61.1] always3(s18) || -> . % 76.16/76.38 185314[102:SSi:185313.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.38 185315[100:Spt:185314.0,184605.0,184606.0] || until2p7(s17)*+ -> . % 76.16/76.38 185316[100:Spt:185314.0,184605.1] || -> node4(s16)*. % 76.16/76.38 185318[100:MRR:870.0,185316.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.38 185321[100:Res:53.1,185318.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.38 185323[101:Spt:185321.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 185325[101:Res:185323.0,61.1] always3(s16) || -> . % 76.16/76.38 185326[101:SSi:185325.0,78137.0,78141.0,165508.0,184604.0,185316.0] || -> . % 76.16/76.38 185327[101:Spt:185326.0,185321.0,185323.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.38 185328[101:Spt:185326.0,185321.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 185332[101:Res:185328.0,61.1] always3(s17) || -> . % 76.16/76.38 185333[101:SSi:185332.0,78142.0,78145.0,165509.0] || -> . % 76.16/76.38 185334[99:Spt:185333.0,184603.0,184604.0] || until2p7(s16)*+ -> . % 76.16/76.38 185335[99:Spt:185333.0,184603.1] || -> node4(s15)*. % 76.16/76.38 185337[99:MRR:873.0,185335.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.38 185340[99:Res:53.1,185337.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.38 185342[100:Spt:185340.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 185344[100:Res:185342.0,61.1] always3(s15) || -> . % 76.16/76.38 185345[100:SSi:185344.0,78133.0,78136.0,165507.0,184602.0,185335.0] || -> . % 76.16/76.38 185346[100:Spt:185345.0,185340.0,185342.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.38 185347[100:Spt:185345.0,185340.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 185351[100:Res:185347.0,61.1] always3(s16) || -> . % 76.16/76.38 185352[100:SSi:185351.0,78137.0,78141.0,165508.0] || -> . % 76.16/76.38 185353[98:Spt:185352.0,184601.0,184602.0] || until2p7(s15)*+ -> . % 76.16/76.38 185354[98:Spt:185352.0,184601.1] || -> node4(s14)*. % 76.16/76.38 185356[98:MRR:876.0,185354.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.38 185359[98:Res:53.1,185356.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.38 185364[99:Spt:185359.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 185366[99:Res:185364.0,61.1] always3(s14) || -> . % 76.16/76.38 185367[99:SSi:185366.0,78128.0,78132.0,165506.0,184600.0,185354.0] || -> . % 76.16/76.38 185368[99:Spt:185367.0,185359.0,185364.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.38 185369[99:Spt:185367.0,185359.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 185373[99:Res:185369.0,61.1] always3(s15) || -> . % 76.16/76.38 185374[99:SSi:185373.0,78133.0,78136.0,165507.0] || -> . % 76.16/76.38 185375[97:Spt:185374.0,184599.0,184600.0] || until2p7(s14)*+ -> . % 76.16/76.38 185376[97:Spt:185374.0,184599.1] || -> node4(s13)*. % 76.16/76.38 185378[97:MRR:879.0,185376.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.38 185381[97:Res:53.1,185378.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.38 185383[98:Spt:185381.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 185385[98:Res:185383.0,61.1] always3(s13) || -> . % 76.16/76.38 185386[98:SSi:185385.0,78124.0,78127.0,165505.0,184598.0,185376.0] || -> . % 76.16/76.38 185387[98:Spt:185386.0,185381.0,185383.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.38 185388[98:Spt:185386.0,185381.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 185392[98:Res:185388.0,61.1] always3(s14) || -> . % 76.16/76.38 185393[98:SSi:185392.0,78128.0,78132.0,165506.0] || -> . % 76.16/76.38 185394[96:Spt:185393.0,184597.0,184598.0] || until2p7(s13)*+ -> . % 76.16/76.38 185395[96:Spt:185393.0,184597.1] || -> node4(s12)*. % 76.16/76.38 185397[96:MRR:882.0,185395.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.38 185400[96:Res:53.1,185397.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.38 185402[97:Spt:185400.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.38 185404[97:Res:185402.0,61.1] always3(s12) || -> . % 76.16/76.38 185405[97:SSi:185404.0,78119.0,78123.0,165504.0,184596.0,185395.0] || -> . % 76.16/76.38 185406[97:Spt:185405.0,185400.0,185402.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.38 185407[97:Spt:185405.0,185400.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 185411[97:Res:185407.0,61.1] always3(s13) || -> . % 76.16/76.38 185412[97:SSi:185411.0,78124.0,78127.0,165505.0] || -> . % 76.16/76.38 185413[95:Spt:185412.0,184595.0,184596.0] || until2p7(s12)*+ -> . % 76.16/76.38 185414[95:Spt:185412.0,184595.1] || -> node4(s11)*. % 76.16/76.38 185416[95:MRR:885.0,185414.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.38 185419[95:Res:53.1,185416.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.38 185421[95:MRR:185419.0,184585.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.38 185423[95:Res:185421.0,61.1] always3(s12) || -> . % 76.16/76.38 185424[95:SSi:185423.0,78119.0,78123.0,165504.0] || -> . % 76.16/76.38 185425[93:Spt:185424.0,184444.0,184447.0] || trans(s49,s11)*+ -> . % 76.16/76.38 185426[93:Spt:185424.0,184444.1,184444.2,184444.3,184444.4,184444.5,184444.6] || -> trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.38 185428[93:MRR:184446.1,185425.0] xuntil6(s49) || -> trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.38 185429[94:Spt:185426.0] || -> trans(s49,s10)*. % 76.16/76.38 185430[94:Res:185429.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s10)*. % 76.16/76.38 185432[94:Res:185429.0,60.0] || -> node2(s49,s10)*. % 76.16/76.38 185433[94:SSi:185430.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s10)*. % 76.16/76.38 185434[94:Res:185432.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)*. % 76.16/76.38 185566[94:SoR:185434.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)*. % 76.16/76.38 185568[94:SoR:185566.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)* xuntil6(s49). % 76.16/76.38 185569[94:SSi:185568.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s10,c_busy)* xuntil6(s49). % 76.16/76.38 185570[95:Spt:185569.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.38 185572[95:Res:185570.0,61.1] always3(s10) || -> . % 76.16/76.38 185573[95:SSi:185572.0,78110.0,78114.0,165502.0] || -> . % 76.16/76.38 185574[95:Spt:185573.0,185569.1,185570.0] || m_main_v_state(s10,c_busy)*+ -> . % 76.16/76.38 185575[95:Spt:185573.0,185569.0,185569.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.38 185579[95:MRR:185566.2,185574.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.38 185580[95:Res:53.1,185575.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.38 185582[95:MRR:185580.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.38 185583[95:MRR:185433.0,185582.0] || -> until2p7(s10)*. % 76.16/76.38 185584[95:MRR:206.0,185583.0] || -> until2p7(s11)* node4(s10). % 76.16/76.38 185585[96:Spt:185584.0] || -> until2p7(s11)*. % 76.16/76.38 185586[96:MRR:207.0,185585.0] || -> until2p7(s12)* node4(s11). % 76.16/76.38 185587[97:Spt:185586.0] || -> until2p7(s12)*. % 76.16/76.38 185588[97:MRR:208.0,185587.0] || -> until2p7(s13)* node4(s12). % 76.16/76.38 185589[98:Spt:185588.0] || -> until2p7(s13)*. % 76.16/76.38 185590[98:MRR:209.0,185589.0] || -> until2p7(s14)* node4(s13). % 76.16/76.38 185591[99:Spt:185590.0] || -> until2p7(s14)*. % 76.16/76.38 185592[99:MRR:210.0,185591.0] || -> until2p7(s15)* node4(s14). % 76.16/76.38 185593[100:Spt:185592.0] || -> until2p7(s15)*. % 76.16/76.38 185594[100:MRR:211.0,185593.0] || -> until2p7(s16)* node4(s15). % 76.16/76.38 185595[101:Spt:185594.0] || -> until2p7(s16)*. % 76.16/76.38 185596[101:MRR:212.0,185595.0] || -> until2p7(s17)* node4(s16). % 76.16/76.38 185597[102:Spt:185596.0] || -> until2p7(s17)*. % 76.16/76.38 185598[102:MRR:213.0,185597.0] || -> until2p7(s18)* node4(s17). % 76.16/76.38 185599[103:Spt:185598.0] || -> until2p7(s18)*. % 76.16/76.38 185600[103:MRR:214.0,185599.0] || -> until2p7(s19)* node4(s18). % 76.16/76.38 185601[104:Spt:185600.0] || -> until2p7(s19)*. % 76.16/76.38 185602[104:MRR:215.0,185601.0] || -> until2p7(s20)* node4(s19). % 76.16/76.38 185603[105:Spt:185602.0] || -> until2p7(s20)*. % 76.16/76.38 185604[105:MRR:216.0,185603.0] || -> until2p7(s21)* node4(s20). % 76.16/76.38 185605[106:Spt:185604.0] || -> until2p7(s21)*. % 76.16/76.38 185606[106:MRR:217.0,185605.0] || -> until2p7(s22)* node4(s21). % 76.16/76.38 185607[107:Spt:185606.0] || -> until2p7(s22)*. % 76.16/76.38 185608[107:MRR:218.0,185607.0] || -> until2p7(s23)* node4(s22). % 76.16/76.38 185609[108:Spt:185608.0] || -> until2p7(s23)*. % 76.16/76.38 185610[108:MRR:219.0,185609.0] || -> until2p7(s24)* node4(s23). % 76.16/76.38 185611[109:Spt:185610.0] || -> until2p7(s24)*. % 76.16/76.38 185612[109:MRR:220.0,185611.0] || -> until2p7(s25)* node4(s24). % 76.16/76.38 185613[110:Spt:185612.0] || -> until2p7(s25)*. % 76.16/76.38 185614[110:MRR:221.0,185613.0] || -> until2p7(s26)* node4(s25). % 76.16/76.38 185615[111:Spt:185614.0] || -> until2p7(s26)*. % 76.16/76.38 185616[111:MRR:222.0,185615.0] || -> until2p7(s27)* node4(s26). % 76.16/76.38 185617[112:Spt:185616.0] || -> until2p7(s27)*. % 76.16/76.38 185618[112:MRR:223.0,185617.0] || -> until2p7(s28)* node4(s27). % 76.16/76.38 185619[113:Spt:185618.0] || -> until2p7(s28)*. % 76.16/76.38 185620[113:MRR:224.0,185619.0] || -> until2p7(s29)* node4(s28). % 76.16/76.38 185621[114:Spt:185620.0] || -> until2p7(s29)*. % 76.16/76.38 185622[114:MRR:225.0,185621.0] || -> until2p7(s30)* node4(s29). % 76.16/76.38 185623[115:Spt:185622.0] || -> until2p7(s30)*. % 76.16/76.38 185624[115:MRR:226.0,185623.0] || -> until2p7(s31)* node4(s30). % 76.16/76.38 185625[116:Spt:185624.0] || -> until2p7(s31)*. % 76.16/76.38 185626[116:MRR:227.0,185625.0] || -> until2p7(s32)* node4(s31). % 76.16/76.38 185627[117:Spt:185626.0] || -> until2p7(s32)*. % 76.16/76.38 185628[117:MRR:228.0,185627.0] || -> until2p7(s33)* node4(s32). % 76.16/76.38 185629[118:Spt:185628.0] || -> until2p7(s33)*. % 76.16/76.38 185630[118:MRR:229.0,185629.0] || -> until2p7(s34)* node4(s33). % 76.16/76.38 185631[119:Spt:185630.0] || -> until2p7(s34)*. % 76.16/76.38 185632[119:MRR:230.0,185631.0] || -> until2p7(s35)* node4(s34). % 76.16/76.38 185633[120:Spt:185632.0] || -> until2p7(s35)*. % 76.16/76.38 185634[120:MRR:231.0,185633.0] || -> until2p7(s36)* node4(s35). % 76.16/76.38 185635[121:Spt:185634.0] || -> until2p7(s36)*. % 76.16/76.38 185636[121:MRR:232.0,185635.0] || -> until2p7(s37)* node4(s36). % 76.16/76.38 185637[122:Spt:185636.0] || -> until2p7(s37)*. % 76.16/76.38 185638[122:MRR:235.0,185637.0] || -> until2p7(s38)* node4(s37). % 76.16/76.38 185639[123:Spt:185638.0] || -> until2p7(s38)*. % 76.16/76.38 185640[123:MRR:236.0,185639.0] || -> until2p7(s39)* node4(s38). % 76.16/76.38 185641[124:Spt:185640.0] || -> until2p7(s39)*. % 76.16/76.38 185642[124:MRR:237.0,185641.0] || -> until2p7(s40)* node4(s39). % 76.16/76.38 185643[125:Spt:185642.0] || -> until2p7(s40)*. % 76.16/76.38 185644[125:MRR:238.0,185643.0] || -> until2p7(s41)* node4(s40). % 76.16/76.38 185645[126:Spt:185644.0] || -> until2p7(s41)*. % 76.16/76.38 185646[126:MRR:239.0,185645.0] || -> until2p7(s42)* node4(s41). % 76.16/76.38 185647[127:Spt:185646.0] || -> until2p7(s42)*. % 76.16/76.38 185648[127:MRR:240.0,185647.0] || -> until2p7(s43)* node4(s42). % 76.16/76.38 185649[128:Spt:185648.0] || -> until2p7(s43)*. % 76.16/76.38 185650[128:MRR:241.0,185649.0] || -> until2p7(s44)* node4(s43). % 76.16/76.38 185651[129:Spt:185650.0] || -> until2p7(s44)*. % 76.16/76.38 185652[129:MRR:539.0,185651.0] || -> until2p7(s45)* node4(s44). % 76.16/76.38 185653[130:Spt:185652.0] || -> until2p7(s45)*. % 76.16/76.38 185654[130:MRR:544.0,185653.0] || -> until2p7(s46)* node4(s45). % 76.16/76.38 185655[131:Spt:185654.0] || -> until2p7(s46)*. % 76.16/76.38 185656[131:MRR:549.0,185655.0] || -> until2p7(s47)* node4(s46). % 76.16/76.38 185657[132:Spt:185656.0] || -> until2p7(s47)*. % 76.16/76.38 185658[132:MRR:554.0,185657.0] || -> until2p7(s48)* node4(s47). % 76.16/76.38 185659[133:Spt:185658.0] || -> until2p7(s48)*. % 76.16/76.38 185660[133:MRR:559.0,185659.0] || -> until2p7(s49)* node4(s48). % 76.16/76.38 185661[134:Spt:185660.0] || -> until2p7(s49)*. % 76.16/76.38 185662[134:MRR:194.0,185661.0] || -> node4(s49)*. % 76.16/76.38 185663[134:MRR:185579.0,185662.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.38 185664[134:Res:53.1,185663.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.38 185666[134:MRR:185664.0,78381.0] || -> . % 76.16/76.38 185667[134:Spt:185666.0,185660.0,185661.0] || until2p7(s49)*+ -> . % 76.16/76.38 185668[134:Spt:185666.0,185660.1] || -> node4(s48)*. % 76.16/76.38 185669[134:MRR:78384.0,185668.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.38 185672[134:Res:53.1,185669.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 185675[134:Res:185672.0,61.1] always3(s48) || -> . % 76.16/76.38 185676[134:SSi:185675.0,78281.0,78387.0,165540.0,185659.0,185668.0] || -> . % 76.16/76.38 185677[133:Spt:185676.0,185658.0,185659.0] || until2p7(s48)*+ -> . % 76.16/76.38 185678[133:Spt:185676.0,185658.1] || -> node4(s47)*. % 76.16/76.38 185680[133:MRR:777.0,185678.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.38 185695[133:Res:53.1,185680.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.38 185697[134:Spt:185695.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 185699[134:Res:185697.0,61.1] always3(s47) || -> . % 76.16/76.38 185700[134:SSi:185699.0,78277.0,78280.0,165539.0,185657.0,185678.0] || -> . % 76.16/76.38 185701[134:Spt:185700.0,185695.0,185697.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.38 185702[134:Spt:185700.0,185695.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 185706[134:Res:185702.0,61.1] always3(s48) || -> . % 76.16/76.38 185707[134:SSi:185706.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.38 185708[132:Spt:185707.0,185656.0,185657.0] || until2p7(s47)*+ -> . % 76.16/76.38 185709[132:Spt:185707.0,185656.1] || -> node4(s46)*. % 76.16/76.38 185711[132:MRR:780.0,185709.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.38 185721[132:Res:53.1,185711.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.38 185723[133:Spt:185721.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 185725[133:Res:185723.0,61.1] always3(s46) || -> . % 76.16/76.38 185726[133:SSi:185725.0,78272.0,78276.0,165538.0,185655.0,185709.0] || -> . % 76.16/76.38 185727[133:Spt:185726.0,185721.0,185723.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.38 185728[133:Spt:185726.0,185721.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 185732[133:Res:185728.0,61.1] always3(s47) || -> . % 76.16/76.38 185733[133:SSi:185732.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.38 185734[131:Spt:185733.0,185654.0,185655.0] || until2p7(s46)*+ -> . % 76.16/76.38 185735[131:Spt:185733.0,185654.1] || -> node4(s45)*. % 76.16/76.38 185737[131:MRR:783.0,185735.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.38 185740[131:Res:53.1,185737.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.38 185742[132:Spt:185740.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 185744[132:Res:185742.0,61.1] always3(s45) || -> . % 76.16/76.38 185745[132:SSi:185744.0,78268.0,78271.0,165537.0,185653.0,185735.0] || -> . % 76.16/76.38 185746[132:Spt:185745.0,185740.0,185742.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.38 185747[132:Spt:185745.0,185740.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 185751[132:Res:185747.0,61.1] always3(s46) || -> . % 76.16/76.38 185752[132:SSi:185751.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.38 185753[130:Spt:185752.0,185652.0,185653.0] || until2p7(s45)*+ -> . % 76.16/76.38 185754[130:Spt:185752.0,185652.1] || -> node4(s44)*. % 76.16/76.38 185756[130:MRR:786.0,185754.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.38 185759[130:Res:53.1,185756.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.38 185761[131:Spt:185759.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 185763[131:Res:185761.0,61.1] always3(s44) || -> . % 76.16/76.38 185764[131:SSi:185763.0,78263.0,78267.0,165536.0,185651.0,185754.0] || -> . % 76.16/76.38 185765[131:Spt:185764.0,185759.0,185761.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.38 185766[131:Spt:185764.0,185759.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 185770[131:Res:185766.0,61.1] always3(s45) || -> . % 76.16/76.38 185771[131:SSi:185770.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.38 185772[129:Spt:185771.0,185650.0,185651.0] || until2p7(s44)*+ -> . % 76.16/76.38 185773[129:Spt:185771.0,185650.1] || -> node4(s43)*. % 76.16/76.38 185775[129:MRR:789.0,185773.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.38 185778[129:Res:53.1,185775.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.38 185783[130:Spt:185778.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 185785[130:Res:185783.0,61.1] always3(s43) || -> . % 76.16/76.38 185786[130:SSi:185785.0,78259.0,78262.0,165535.0,185649.0,185773.0] || -> . % 76.16/76.38 185787[130:Spt:185786.0,185778.0,185783.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.38 185788[130:Spt:185786.0,185778.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 185792[130:Res:185788.0,61.1] always3(s44) || -> . % 76.16/76.38 185793[130:SSi:185792.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.38 185794[128:Spt:185793.0,185648.0,185649.0] || until2p7(s43)*+ -> . % 76.16/76.38 185795[128:Spt:185793.0,185648.1] || -> node4(s42)*. % 76.16/76.38 185797[128:MRR:792.0,185795.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.38 185800[128:Res:53.1,185797.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.38 185802[129:Spt:185800.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 185804[129:Res:185802.0,61.1] always3(s42) || -> . % 76.16/76.38 185805[129:SSi:185804.0,78254.0,78258.0,165534.0,185647.0,185795.0] || -> . % 76.16/76.38 185806[129:Spt:185805.0,185800.0,185802.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.38 185807[129:Spt:185805.0,185800.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 185811[129:Res:185807.0,61.1] always3(s43) || -> . % 76.16/76.38 185812[129:SSi:185811.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.38 185813[127:Spt:185812.0,185646.0,185647.0] || until2p7(s42)*+ -> . % 76.16/76.38 185814[127:Spt:185812.0,185646.1] || -> node4(s41)*. % 76.16/76.38 185816[127:MRR:795.0,185814.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.38 185819[127:Res:53.1,185816.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.38 185821[128:Spt:185819.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 185823[128:Res:185821.0,61.1] always3(s41) || -> . % 76.16/76.38 185824[128:SSi:185823.0,78250.0,78253.0,165533.0,185645.0,185814.0] || -> . % 76.16/76.38 185825[128:Spt:185824.0,185819.0,185821.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.38 185826[128:Spt:185824.0,185819.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 185830[128:Res:185826.0,61.1] always3(s42) || -> . % 76.16/76.38 185831[128:SSi:185830.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.38 185832[126:Spt:185831.0,185644.0,185645.0] || until2p7(s41)*+ -> . % 76.16/76.38 185833[126:Spt:185831.0,185644.1] || -> node4(s40)*. % 76.16/76.38 185835[126:MRR:798.0,185833.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.38 185838[126:Res:53.1,185835.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.38 185840[127:Spt:185838.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 185842[127:Res:185840.0,61.1] always3(s40) || -> . % 76.16/76.38 185843[127:SSi:185842.0,78245.0,78249.0,165532.0,185643.0,185833.0] || -> . % 76.16/76.38 185844[127:Spt:185843.0,185838.0,185840.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.38 185845[127:Spt:185843.0,185838.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 185849[127:Res:185845.0,61.1] always3(s41) || -> . % 76.16/76.38 185850[127:SSi:185849.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.38 185851[125:Spt:185850.0,185642.0,185643.0] || until2p7(s40)*+ -> . % 76.16/76.38 185852[125:Spt:185850.0,185642.1] || -> node4(s39)*. % 76.16/76.38 185854[125:MRR:801.0,185852.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.38 185857[125:Res:53.1,185854.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.38 185862[126:Spt:185857.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 185864[126:Res:185862.0,61.1] always3(s39) || -> . % 76.16/76.38 185865[126:SSi:185864.0,78241.0,78244.0,165531.0,185641.0,185852.0] || -> . % 76.16/76.38 185866[126:Spt:185865.0,185857.0,185862.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.38 185867[126:Spt:185865.0,185857.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 185871[126:Res:185867.0,61.1] always3(s40) || -> . % 76.16/76.38 185872[126:SSi:185871.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.38 185873[124:Spt:185872.0,185640.0,185641.0] || until2p7(s39)*+ -> . % 76.16/76.38 185874[124:Spt:185872.0,185640.1] || -> node4(s38)*. % 76.16/76.38 185876[124:MRR:804.0,185874.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.38 185879[124:Res:53.1,185876.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.38 185881[125:Spt:185879.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 185883[125:Res:185881.0,61.1] always3(s38) || -> . % 76.16/76.38 185884[125:SSi:185883.0,78236.0,78240.0,165530.0,185639.0,185874.0] || -> . % 76.16/76.38 185885[125:Spt:185884.0,185879.0,185881.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.38 185886[125:Spt:185884.0,185879.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 185890[125:Res:185886.0,61.1] always3(s39) || -> . % 76.16/76.38 185891[125:SSi:185890.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.38 185892[123:Spt:185891.0,185638.0,185639.0] || until2p7(s38)*+ -> . % 76.16/76.38 185893[123:Spt:185891.0,185638.1] || -> node4(s37)*. % 76.16/76.38 185895[123:MRR:807.0,185893.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.38 185898[123:Res:53.1,185895.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.38 185900[124:Spt:185898.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 185902[124:Res:185900.0,61.1] always3(s37) || -> . % 76.16/76.38 185903[124:SSi:185902.0,78232.0,78235.0,165529.0,185637.0,185893.0] || -> . % 76.16/76.38 185904[124:Spt:185903.0,185898.0,185900.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.38 185905[124:Spt:185903.0,185898.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 185909[124:Res:185905.0,61.1] always3(s38) || -> . % 76.16/76.38 185910[124:SSi:185909.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.38 185911[122:Spt:185910.0,185636.0,185637.0] || until2p7(s37)*+ -> . % 76.16/76.38 185912[122:Spt:185910.0,185636.1] || -> node4(s36)*. % 76.16/76.38 185914[122:MRR:810.0,185912.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.38 185917[122:Res:53.1,185914.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.38 185919[123:Spt:185917.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 185921[123:Res:185919.0,61.1] always3(s36) || -> . % 76.16/76.38 185922[123:SSi:185921.0,78227.0,78231.0,165528.0,185635.0,185912.0] || -> . % 76.16/76.38 185923[123:Spt:185922.0,185917.0,185919.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.38 185924[123:Spt:185922.0,185917.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 185928[123:Res:185924.0,61.1] always3(s37) || -> . % 76.16/76.38 185929[123:SSi:185928.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.38 185930[121:Spt:185929.0,185634.0,185635.0] || until2p7(s36)*+ -> . % 76.16/76.38 185931[121:Spt:185929.0,185634.1] || -> node4(s35)*. % 76.16/76.38 185933[121:MRR:813.0,185931.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.38 185936[121:Res:53.1,185933.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.38 185941[122:Spt:185936.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 185943[122:Res:185941.0,61.1] always3(s35) || -> . % 76.16/76.38 185944[122:SSi:185943.0,78223.0,78226.0,165527.0,185633.0,185931.0] || -> . % 76.16/76.38 185945[122:Spt:185944.0,185936.0,185941.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.38 185946[122:Spt:185944.0,185936.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 185950[122:Res:185946.0,61.1] always3(s36) || -> . % 76.16/76.38 185951[122:SSi:185950.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.38 185952[120:Spt:185951.0,185632.0,185633.0] || until2p7(s35)*+ -> . % 76.16/76.38 185953[120:Spt:185951.0,185632.1] || -> node4(s34)*. % 76.16/76.38 185955[120:MRR:816.0,185953.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.38 185958[120:Res:53.1,185955.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.38 185960[121:Spt:185958.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 185962[121:Res:185960.0,61.1] always3(s34) || -> . % 76.16/76.38 185963[121:SSi:185962.0,78218.0,78222.0,165526.0,185631.0,185953.0] || -> . % 76.16/76.38 185964[121:Spt:185963.0,185958.0,185960.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.38 185965[121:Spt:185963.0,185958.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 185969[121:Res:185965.0,61.1] always3(s35) || -> . % 76.16/76.38 185970[121:SSi:185969.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.38 185971[119:Spt:185970.0,185630.0,185631.0] || until2p7(s34)*+ -> . % 76.16/76.38 185972[119:Spt:185970.0,185630.1] || -> node4(s33)*. % 76.16/76.38 185974[119:MRR:819.0,185972.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.38 185977[119:Res:53.1,185974.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.38 185979[120:Spt:185977.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 185981[120:Res:185979.0,61.1] always3(s33) || -> . % 76.16/76.38 185982[120:SSi:185981.0,78214.0,78217.0,165525.0,185629.0,185972.0] || -> . % 76.16/76.38 185983[120:Spt:185982.0,185977.0,185979.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.38 185984[120:Spt:185982.0,185977.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 185988[120:Res:185984.0,61.1] always3(s34) || -> . % 76.16/76.38 185989[120:SSi:185988.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.38 185990[118:Spt:185989.0,185628.0,185629.0] || until2p7(s33)*+ -> . % 76.16/76.38 185991[118:Spt:185989.0,185628.1] || -> node4(s32)*. % 76.16/76.38 185993[118:MRR:822.0,185991.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.38 185996[118:Res:53.1,185993.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.38 185998[119:Spt:185996.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 186000[119:Res:185998.0,61.1] always3(s32) || -> . % 76.16/76.38 186001[119:SSi:186000.0,78209.0,78213.0,165524.0,185627.0,185991.0] || -> . % 76.16/76.38 186002[119:Spt:186001.0,185996.0,185998.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.38 186003[119:Spt:186001.0,185996.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 186007[119:Res:186003.0,61.1] always3(s33) || -> . % 76.16/76.38 186008[119:SSi:186007.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.38 186009[117:Spt:186008.0,185626.0,185627.0] || until2p7(s32)*+ -> . % 76.16/76.38 186010[117:Spt:186008.0,185626.1] || -> node4(s31)*. % 76.16/76.38 186012[117:MRR:825.0,186010.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.38 186015[117:Res:53.1,186012.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.38 186020[118:Spt:186015.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 186022[118:Res:186020.0,61.1] always3(s31) || -> . % 76.16/76.38 186023[118:SSi:186022.0,78205.0,78208.0,165523.0,185625.0,186010.0] || -> . % 76.16/76.38 186024[118:Spt:186023.0,186015.0,186020.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.38 186025[118:Spt:186023.0,186015.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 186029[118:Res:186025.0,61.1] always3(s32) || -> . % 76.16/76.38 186030[118:SSi:186029.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.38 186031[116:Spt:186030.0,185624.0,185625.0] || until2p7(s31)*+ -> . % 76.16/76.38 186032[116:Spt:186030.0,185624.1] || -> node4(s30)*. % 76.16/76.38 186034[116:MRR:828.0,186032.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.38 186037[116:Res:53.1,186034.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.38 186039[117:Spt:186037.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 186041[117:Res:186039.0,61.1] always3(s30) || -> . % 76.16/76.38 186042[117:SSi:186041.0,78200.0,78204.0,165522.0,185623.0,186032.0] || -> . % 76.16/76.38 186043[117:Spt:186042.0,186037.0,186039.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.38 186044[117:Spt:186042.0,186037.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 186048[117:Res:186044.0,61.1] always3(s31) || -> . % 76.16/76.38 186049[117:SSi:186048.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.38 186050[115:Spt:186049.0,185622.0,185623.0] || until2p7(s30)*+ -> . % 76.16/76.38 186051[115:Spt:186049.0,185622.1] || -> node4(s29)*. % 76.16/76.38 186053[115:MRR:831.0,186051.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.38 186056[115:Res:53.1,186053.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.38 186058[116:Spt:186056.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 186060[116:Res:186058.0,61.1] always3(s29) || -> . % 76.16/76.38 186061[116:SSi:186060.0,78196.0,78199.0,165521.0,185621.0,186051.0] || -> . % 76.16/76.38 186062[116:Spt:186061.0,186056.0,186058.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.38 186063[116:Spt:186061.0,186056.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 186067[116:Res:186063.0,61.1] always3(s30) || -> . % 76.16/76.38 186068[116:SSi:186067.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.38 186069[114:Spt:186068.0,185620.0,185621.0] || until2p7(s29)*+ -> . % 76.16/76.38 186070[114:Spt:186068.0,185620.1] || -> node4(s28)*. % 76.16/76.38 186072[114:MRR:834.0,186070.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.38 186075[114:Res:53.1,186072.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.38 186077[115:Spt:186075.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 186079[115:Res:186077.0,61.1] always3(s28) || -> . % 76.16/76.38 186080[115:SSi:186079.0,78191.0,78195.0,165520.0,185619.0,186070.0] || -> . % 76.16/76.38 186081[115:Spt:186080.0,186075.0,186077.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.38 186082[115:Spt:186080.0,186075.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 186086[115:Res:186082.0,61.1] always3(s29) || -> . % 76.16/76.38 186087[115:SSi:186086.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.38 186088[113:Spt:186087.0,185618.0,185619.0] || until2p7(s28)*+ -> . % 76.16/76.38 186089[113:Spt:186087.0,185618.1] || -> node4(s27)*. % 76.16/76.38 186091[113:MRR:837.0,186089.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.38 186094[113:Res:53.1,186091.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.38 186099[114:Spt:186094.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 186101[114:Res:186099.0,61.1] always3(s27) || -> . % 76.16/76.38 186102[114:SSi:186101.0,78187.0,78190.0,165519.0,185617.0,186089.0] || -> . % 76.16/76.38 186103[114:Spt:186102.0,186094.0,186099.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.38 186104[114:Spt:186102.0,186094.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 186108[114:Res:186104.0,61.1] always3(s28) || -> . % 76.16/76.38 186109[114:SSi:186108.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.38 186110[112:Spt:186109.0,185616.0,185617.0] || until2p7(s27)*+ -> . % 76.16/76.38 186111[112:Spt:186109.0,185616.1] || -> node4(s26)*. % 76.16/76.38 186113[112:MRR:840.0,186111.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.38 186116[112:Res:53.1,186113.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.38 186118[113:Spt:186116.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 186120[113:Res:186118.0,61.1] always3(s26) || -> . % 76.16/76.38 186121[113:SSi:186120.0,78182.0,78186.0,165518.0,185615.0,186111.0] || -> . % 76.16/76.38 186122[113:Spt:186121.0,186116.0,186118.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.38 186123[113:Spt:186121.0,186116.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 186127[113:Res:186123.0,61.1] always3(s27) || -> . % 76.16/76.38 186128[113:SSi:186127.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.38 186129[111:Spt:186128.0,185614.0,185615.0] || until2p7(s26)*+ -> . % 76.16/76.38 186130[111:Spt:186128.0,185614.1] || -> node4(s25)*. % 76.16/76.38 186132[111:MRR:843.0,186130.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.38 186135[111:Res:53.1,186132.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.38 186137[112:Spt:186135.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 186139[112:Res:186137.0,61.1] always3(s25) || -> . % 76.16/76.38 186140[112:SSi:186139.0,78178.0,78181.0,165517.0,185613.0,186130.0] || -> . % 76.16/76.38 186141[112:Spt:186140.0,186135.0,186137.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.38 186142[112:Spt:186140.0,186135.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 186146[112:Res:186142.0,61.1] always3(s26) || -> . % 76.16/76.38 186147[112:SSi:186146.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.38 186148[110:Spt:186147.0,185612.0,185613.0] || until2p7(s25)*+ -> . % 76.16/76.38 186149[110:Spt:186147.0,185612.1] || -> node4(s24)*. % 76.16/76.38 186151[110:MRR:846.0,186149.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.38 186154[110:Res:53.1,186151.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.38 186156[111:Spt:186154.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 186158[111:Res:186156.0,61.1] always3(s24) || -> . % 76.16/76.38 186159[111:SSi:186158.0,78173.0,78177.0,165516.0,185611.0,186149.0] || -> . % 76.16/76.38 186160[111:Spt:186159.0,186154.0,186156.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.38 186161[111:Spt:186159.0,186154.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 186165[111:Res:186161.0,61.1] always3(s25) || -> . % 76.16/76.38 186166[111:SSi:186165.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.38 186167[109:Spt:186166.0,185610.0,185611.0] || until2p7(s24)*+ -> . % 76.16/76.38 186168[109:Spt:186166.0,185610.1] || -> node4(s23)*. % 76.16/76.38 186170[109:MRR:849.0,186168.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.38 186173[109:Res:53.1,186170.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.38 186178[110:Spt:186173.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 186180[110:Res:186178.0,61.1] always3(s23) || -> . % 76.16/76.38 186181[110:SSi:186180.0,78169.0,78172.0,165515.0,185609.0,186168.0] || -> . % 76.16/76.38 186182[110:Spt:186181.0,186173.0,186178.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.38 186183[110:Spt:186181.0,186173.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 186187[110:Res:186183.0,61.1] always3(s24) || -> . % 76.16/76.38 186188[110:SSi:186187.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.38 186189[108:Spt:186188.0,185608.0,185609.0] || until2p7(s23)*+ -> . % 76.16/76.38 186190[108:Spt:186188.0,185608.1] || -> node4(s22)*. % 76.16/76.38 186192[108:MRR:852.0,186190.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.38 186195[108:Res:53.1,186192.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.38 186197[109:Spt:186195.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 186199[109:Res:186197.0,61.1] always3(s22) || -> . % 76.16/76.38 186200[109:SSi:186199.0,78164.0,78168.0,165514.0,185607.0,186190.0] || -> . % 76.16/76.38 186201[109:Spt:186200.0,186195.0,186197.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.38 186202[109:Spt:186200.0,186195.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 186206[109:Res:186202.0,61.1] always3(s23) || -> . % 76.16/76.38 186207[109:SSi:186206.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.38 186208[107:Spt:186207.0,185606.0,185607.0] || until2p7(s22)*+ -> . % 76.16/76.38 186209[107:Spt:186207.0,185606.1] || -> node4(s21)*. % 76.16/76.38 186211[107:MRR:855.0,186209.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.38 186214[107:Res:53.1,186211.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.38 186216[108:Spt:186214.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 186218[108:Res:186216.0,61.1] always3(s21) || -> . % 76.16/76.38 186219[108:SSi:186218.0,78160.0,78163.0,165513.0,185605.0,186209.0] || -> . % 76.16/76.38 186220[108:Spt:186219.0,186214.0,186216.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.38 186221[108:Spt:186219.0,186214.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 186225[108:Res:186221.0,61.1] always3(s22) || -> . % 76.16/76.38 186226[108:SSi:186225.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.38 186227[106:Spt:186226.0,185604.0,185605.0] || until2p7(s21)*+ -> . % 76.16/76.38 186228[106:Spt:186226.0,185604.1] || -> node4(s20)*. % 76.16/76.38 186230[106:MRR:858.0,186228.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.38 186233[106:Res:53.1,186230.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.38 186235[107:Spt:186233.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 186237[107:Res:186235.0,61.1] always3(s20) || -> . % 76.16/76.38 186238[107:SSi:186237.0,78155.0,78159.0,165512.0,185603.0,186228.0] || -> . % 76.16/76.38 186239[107:Spt:186238.0,186233.0,186235.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.38 186240[107:Spt:186238.0,186233.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 186244[107:Res:186240.0,61.1] always3(s21) || -> . % 76.16/76.38 186245[107:SSi:186244.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.38 186246[105:Spt:186245.0,185602.0,185603.0] || until2p7(s20)*+ -> . % 76.16/76.38 186247[105:Spt:186245.0,185602.1] || -> node4(s19)*. % 76.16/76.38 186249[105:MRR:861.0,186247.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.38 186252[105:Res:53.1,186249.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.38 186257[106:Spt:186252.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 186259[106:Res:186257.0,61.1] always3(s19) || -> . % 76.16/76.38 186260[106:SSi:186259.0,78151.0,78154.0,165511.0,185601.0,186247.0] || -> . % 76.16/76.38 186261[106:Spt:186260.0,186252.0,186257.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.38 186262[106:Spt:186260.0,186252.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 186266[106:Res:186262.0,61.1] always3(s20) || -> . % 76.16/76.38 186267[106:SSi:186266.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.38 186268[104:Spt:186267.0,185600.0,185601.0] || until2p7(s19)*+ -> . % 76.16/76.38 186269[104:Spt:186267.0,185600.1] || -> node4(s18)*. % 76.16/76.38 186271[104:MRR:864.0,186269.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.38 186274[104:Res:53.1,186271.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.38 186276[105:Spt:186274.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 186278[105:Res:186276.0,61.1] always3(s18) || -> . % 76.16/76.38 186279[105:SSi:186278.0,78146.0,78150.0,165510.0,185599.0,186269.0] || -> . % 76.16/76.38 186280[105:Spt:186279.0,186274.0,186276.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.38 186281[105:Spt:186279.0,186274.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 186285[105:Res:186281.0,61.1] always3(s19) || -> . % 76.16/76.38 186286[105:SSi:186285.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.38 186287[103:Spt:186286.0,185598.0,185599.0] || until2p7(s18)*+ -> . % 76.16/76.38 186288[103:Spt:186286.0,185598.1] || -> node4(s17)*. % 76.16/76.38 186290[103:MRR:867.0,186288.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.38 186293[103:Res:53.1,186290.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.38 186295[104:Spt:186293.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 186297[104:Res:186295.0,61.1] always3(s17) || -> . % 76.16/76.38 186298[104:SSi:186297.0,78142.0,78145.0,165509.0,185597.0,186288.0] || -> . % 76.16/76.38 186299[104:Spt:186298.0,186293.0,186295.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.38 186300[104:Spt:186298.0,186293.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 186304[104:Res:186300.0,61.1] always3(s18) || -> . % 76.16/76.38 186305[104:SSi:186304.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.38 186306[102:Spt:186305.0,185596.0,185597.0] || until2p7(s17)*+ -> . % 76.16/76.38 186307[102:Spt:186305.0,185596.1] || -> node4(s16)*. % 76.16/76.38 186309[102:MRR:870.0,186307.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.38 186312[102:Res:53.1,186309.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.38 186314[103:Spt:186312.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 186316[103:Res:186314.0,61.1] always3(s16) || -> . % 76.16/76.38 186317[103:SSi:186316.0,78137.0,78141.0,165508.0,185595.0,186307.0] || -> . % 76.16/76.38 186318[103:Spt:186317.0,186312.0,186314.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.38 186319[103:Spt:186317.0,186312.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 186323[103:Res:186319.0,61.1] always3(s17) || -> . % 76.16/76.38 186324[103:SSi:186323.0,78142.0,78145.0,165509.0] || -> . % 76.16/76.38 186325[101:Spt:186324.0,185594.0,185595.0] || until2p7(s16)*+ -> . % 76.16/76.38 186326[101:Spt:186324.0,185594.1] || -> node4(s15)*. % 76.16/76.38 186328[101:MRR:873.0,186326.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.38 186331[101:Res:53.1,186328.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.38 186336[102:Spt:186331.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 186338[102:Res:186336.0,61.1] always3(s15) || -> . % 76.16/76.38 186339[102:SSi:186338.0,78133.0,78136.0,165507.0,185593.0,186326.0] || -> . % 76.16/76.38 186340[102:Spt:186339.0,186331.0,186336.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.38 186341[102:Spt:186339.0,186331.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 186345[102:Res:186341.0,61.1] always3(s16) || -> . % 76.16/76.38 186346[102:SSi:186345.0,78137.0,78141.0,165508.0] || -> . % 76.16/76.38 186347[100:Spt:186346.0,185592.0,185593.0] || until2p7(s15)*+ -> . % 76.16/76.38 186348[100:Spt:186346.0,185592.1] || -> node4(s14)*. % 76.16/76.38 186350[100:MRR:876.0,186348.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.38 186353[100:Res:53.1,186350.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.38 186355[101:Spt:186353.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 186357[101:Res:186355.0,61.1] always3(s14) || -> . % 76.16/76.38 186358[101:SSi:186357.0,78128.0,78132.0,165506.0,185591.0,186348.0] || -> . % 76.16/76.38 186359[101:Spt:186358.0,186353.0,186355.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.38 186360[101:Spt:186358.0,186353.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 186364[101:Res:186360.0,61.1] always3(s15) || -> . % 76.16/76.38 186365[101:SSi:186364.0,78133.0,78136.0,165507.0] || -> . % 76.16/76.38 186366[99:Spt:186365.0,185590.0,185591.0] || until2p7(s14)*+ -> . % 76.16/76.38 186367[99:Spt:186365.0,185590.1] || -> node4(s13)*. % 76.16/76.38 186369[99:MRR:879.0,186367.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.38 186372[99:Res:53.1,186369.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.38 186374[100:Spt:186372.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 186376[100:Res:186374.0,61.1] always3(s13) || -> . % 76.16/76.38 186377[100:SSi:186376.0,78124.0,78127.0,165505.0,185589.0,186367.0] || -> . % 76.16/76.38 186378[100:Spt:186377.0,186372.0,186374.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.38 186379[100:Spt:186377.0,186372.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 186383[100:Res:186379.0,61.1] always3(s14) || -> . % 76.16/76.38 186384[100:SSi:186383.0,78128.0,78132.0,165506.0] || -> . % 76.16/76.38 186385[98:Spt:186384.0,185588.0,185589.0] || until2p7(s13)*+ -> . % 76.16/76.38 186386[98:Spt:186384.0,185588.1] || -> node4(s12)*. % 76.16/76.38 186388[98:MRR:882.0,186386.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.38 186391[98:Res:53.1,186388.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.38 186393[99:Spt:186391.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.38 186395[99:Res:186393.0,61.1] always3(s12) || -> . % 76.16/76.38 186396[99:SSi:186395.0,78119.0,78123.0,165504.0,185587.0,186386.0] || -> . % 76.16/76.38 186397[99:Spt:186396.0,186391.0,186393.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.38 186398[99:Spt:186396.0,186391.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 186402[99:Res:186398.0,61.1] always3(s13) || -> . % 76.16/76.38 186403[99:SSi:186402.0,78124.0,78127.0,165505.0] || -> . % 76.16/76.38 186404[97:Spt:186403.0,185586.0,185587.0] || until2p7(s12)*+ -> . % 76.16/76.38 186405[97:Spt:186403.0,185586.1] || -> node4(s11)*. % 76.16/76.38 186407[97:MRR:885.0,186405.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.38 186410[97:Res:53.1,186407.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.38 186415[98:Spt:186410.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.38 186417[98:Res:186415.0,61.1] always3(s11) || -> . % 76.16/76.38 186418[98:SSi:186417.0,78115.0,78118.0,165503.0,185585.0,186405.0] || -> . % 76.16/76.38 186419[98:Spt:186418.0,186410.0,186415.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.38 186420[98:Spt:186418.0,186410.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.38 186424[98:Res:186420.0,61.1] always3(s12) || -> . % 76.16/76.38 186425[98:SSi:186424.0,78119.0,78123.0,165504.0] || -> . % 76.16/76.38 186426[96:Spt:186425.0,185584.0,185585.0] || until2p7(s11)*+ -> . % 76.16/76.38 186427[96:Spt:186425.0,185584.1] || -> node4(s10)*. % 76.16/76.38 186429[96:MRR:888.0,186427.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.38 186432[96:Res:53.1,186429.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.38 186434[96:MRR:186432.0,185574.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.38 186436[96:Res:186434.0,61.1] always3(s11) || -> . % 76.16/76.38 186437[96:SSi:186436.0,78115.0,78118.0,165503.0] || -> . % 76.16/76.38 186438[94:Spt:186437.0,185426.0,185429.0] || trans(s49,s10)*+ -> . % 76.16/76.38 186439[94:Spt:186437.0,185426.1,185426.2,185426.3,185426.4,185426.5] || -> trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.38 186441[94:MRR:185428.1,186438.0] xuntil6(s49) || -> trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.38 186442[95:Spt:186439.0] || -> trans(s49,s9)*. % 76.16/76.38 186443[95:Res:186442.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s9)*. % 76.16/76.38 186445[95:Res:186442.0,60.0] || -> node2(s49,s9)*. % 76.16/76.38 186446[95:SSi:186443.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s9)*. % 76.16/76.38 186447[95:Res:186445.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)*. % 76.16/76.38 186580[95:SoR:186447.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)*. % 76.16/76.38 186582[95:SoR:186580.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)* xuntil6(s49). % 76.16/76.38 186583[95:SSi:186582.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s9,c_busy)* xuntil6(s49). % 76.16/76.38 186584[96:Spt:186583.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.38 186586[96:Res:186584.0,61.1] always3(s9) || -> . % 76.16/76.38 186587[96:SSi:186586.0,78106.0,78109.0,165501.0] || -> . % 76.16/76.38 186588[96:Spt:186587.0,186583.1,186584.0] || m_main_v_state(s9,c_busy)*+ -> . % 76.16/76.38 186589[96:Spt:186587.0,186583.0,186583.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.38 186593[96:MRR:186580.2,186588.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.38 186594[96:Res:53.1,186589.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.38 186596[96:MRR:186594.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.38 186597[96:MRR:186446.0,186596.0] || -> until2p7(s9)*. % 76.16/76.38 186598[96:MRR:205.0,186597.0] || -> until2p7(s10)* node4(s9). % 76.16/76.38 186599[97:Spt:186598.0] || -> until2p7(s10)*. % 76.16/76.38 186600[97:MRR:206.0,186599.0] || -> until2p7(s11)* node4(s10). % 76.16/76.38 186601[98:Spt:186600.0] || -> until2p7(s11)*. % 76.16/76.38 186602[98:MRR:207.0,186601.0] || -> until2p7(s12)* node4(s11). % 76.16/76.38 186603[99:Spt:186602.0] || -> until2p7(s12)*. % 76.16/76.38 186604[99:MRR:208.0,186603.0] || -> until2p7(s13)* node4(s12). % 76.16/76.38 186605[100:Spt:186604.0] || -> until2p7(s13)*. % 76.16/76.38 186606[100:MRR:209.0,186605.0] || -> until2p7(s14)* node4(s13). % 76.16/76.38 186607[101:Spt:186606.0] || -> until2p7(s14)*. % 76.16/76.38 186608[101:MRR:210.0,186607.0] || -> until2p7(s15)* node4(s14). % 76.16/76.38 186609[102:Spt:186608.0] || -> until2p7(s15)*. % 76.16/76.38 186610[102:MRR:211.0,186609.0] || -> until2p7(s16)* node4(s15). % 76.16/76.38 186611[103:Spt:186610.0] || -> until2p7(s16)*. % 76.16/76.38 186612[103:MRR:212.0,186611.0] || -> until2p7(s17)* node4(s16). % 76.16/76.38 186613[104:Spt:186612.0] || -> until2p7(s17)*. % 76.16/76.38 186614[104:MRR:213.0,186613.0] || -> until2p7(s18)* node4(s17). % 76.16/76.38 186615[105:Spt:186614.0] || -> until2p7(s18)*. % 76.16/76.38 186616[105:MRR:214.0,186615.0] || -> until2p7(s19)* node4(s18). % 76.16/76.38 186617[106:Spt:186616.0] || -> until2p7(s19)*. % 76.16/76.38 186618[106:MRR:215.0,186617.0] || -> until2p7(s20)* node4(s19). % 76.16/76.38 186619[107:Spt:186618.0] || -> until2p7(s20)*. % 76.16/76.38 186620[107:MRR:216.0,186619.0] || -> until2p7(s21)* node4(s20). % 76.16/76.38 186621[108:Spt:186620.0] || -> until2p7(s21)*. % 76.16/76.38 186622[108:MRR:217.0,186621.0] || -> until2p7(s22)* node4(s21). % 76.16/76.38 186623[109:Spt:186622.0] || -> until2p7(s22)*. % 76.16/76.38 186624[109:MRR:218.0,186623.0] || -> until2p7(s23)* node4(s22). % 76.16/76.38 186625[110:Spt:186624.0] || -> until2p7(s23)*. % 76.16/76.38 186626[110:MRR:219.0,186625.0] || -> until2p7(s24)* node4(s23). % 76.16/76.38 186627[111:Spt:186626.0] || -> until2p7(s24)*. % 76.16/76.38 186628[111:MRR:220.0,186627.0] || -> until2p7(s25)* node4(s24). % 76.16/76.38 186629[112:Spt:186628.0] || -> until2p7(s25)*. % 76.16/76.38 186630[112:MRR:221.0,186629.0] || -> until2p7(s26)* node4(s25). % 76.16/76.38 186631[113:Spt:186630.0] || -> until2p7(s26)*. % 76.16/76.38 186632[113:MRR:222.0,186631.0] || -> until2p7(s27)* node4(s26). % 76.16/76.38 186633[114:Spt:186632.0] || -> until2p7(s27)*. % 76.16/76.38 186634[114:MRR:223.0,186633.0] || -> until2p7(s28)* node4(s27). % 76.16/76.38 186635[115:Spt:186634.0] || -> until2p7(s28)*. % 76.16/76.38 186636[115:MRR:224.0,186635.0] || -> until2p7(s29)* node4(s28). % 76.16/76.38 186637[116:Spt:186636.0] || -> until2p7(s29)*. % 76.16/76.38 186638[116:MRR:225.0,186637.0] || -> until2p7(s30)* node4(s29). % 76.16/76.38 186639[117:Spt:186638.0] || -> until2p7(s30)*. % 76.16/76.38 186640[117:MRR:226.0,186639.0] || -> until2p7(s31)* node4(s30). % 76.16/76.38 186641[118:Spt:186640.0] || -> until2p7(s31)*. % 76.16/76.38 186642[118:MRR:227.0,186641.0] || -> until2p7(s32)* node4(s31). % 76.16/76.38 186643[119:Spt:186642.0] || -> until2p7(s32)*. % 76.16/76.38 186644[119:MRR:228.0,186643.0] || -> until2p7(s33)* node4(s32). % 76.16/76.38 186645[120:Spt:186644.0] || -> until2p7(s33)*. % 76.16/76.38 186646[120:MRR:229.0,186645.0] || -> until2p7(s34)* node4(s33). % 76.16/76.38 186647[121:Spt:186646.0] || -> until2p7(s34)*. % 76.16/76.38 186648[121:MRR:230.0,186647.0] || -> until2p7(s35)* node4(s34). % 76.16/76.38 186649[122:Spt:186648.0] || -> until2p7(s35)*. % 76.16/76.38 186650[122:MRR:231.0,186649.0] || -> until2p7(s36)* node4(s35). % 76.16/76.38 186651[123:Spt:186650.0] || -> until2p7(s36)*. % 76.16/76.38 186652[123:MRR:232.0,186651.0] || -> until2p7(s37)* node4(s36). % 76.16/76.38 186653[124:Spt:186652.0] || -> until2p7(s37)*. % 76.16/76.38 186654[124:MRR:235.0,186653.0] || -> until2p7(s38)* node4(s37). % 76.16/76.38 186655[125:Spt:186654.0] || -> until2p7(s38)*. % 76.16/76.38 186656[125:MRR:236.0,186655.0] || -> until2p7(s39)* node4(s38). % 76.16/76.38 186657[126:Spt:186656.0] || -> until2p7(s39)*. % 76.16/76.38 186658[126:MRR:237.0,186657.0] || -> until2p7(s40)* node4(s39). % 76.16/76.38 186659[127:Spt:186658.0] || -> until2p7(s40)*. % 76.16/76.38 186660[127:MRR:238.0,186659.0] || -> until2p7(s41)* node4(s40). % 76.16/76.38 186661[128:Spt:186660.0] || -> until2p7(s41)*. % 76.16/76.38 186662[128:MRR:239.0,186661.0] || -> until2p7(s42)* node4(s41). % 76.16/76.38 186663[129:Spt:186662.0] || -> until2p7(s42)*. % 76.16/76.38 186664[129:MRR:240.0,186663.0] || -> until2p7(s43)* node4(s42). % 76.16/76.38 186665[130:Spt:186664.0] || -> until2p7(s43)*. % 76.16/76.38 186666[130:MRR:241.0,186665.0] || -> until2p7(s44)* node4(s43). % 76.16/76.38 186667[131:Spt:186666.0] || -> until2p7(s44)*. % 76.16/76.38 186668[131:MRR:539.0,186667.0] || -> until2p7(s45)* node4(s44). % 76.16/76.38 186669[132:Spt:186668.0] || -> until2p7(s45)*. % 76.16/76.38 186670[132:MRR:544.0,186669.0] || -> until2p7(s46)* node4(s45). % 76.16/76.38 186671[133:Spt:186670.0] || -> until2p7(s46)*. % 76.16/76.38 186672[133:MRR:549.0,186671.0] || -> until2p7(s47)* node4(s46). % 76.16/76.38 186673[134:Spt:186672.0] || -> until2p7(s47)*. % 76.16/76.38 186674[134:MRR:554.0,186673.0] || -> until2p7(s48)* node4(s47). % 76.16/76.38 186675[135:Spt:186674.0] || -> until2p7(s48)*. % 76.16/76.38 186676[135:MRR:559.0,186675.0] || -> until2p7(s49)* node4(s48). % 76.16/76.38 186677[136:Spt:186676.0] || -> until2p7(s49)*. % 76.16/76.38 186678[136:MRR:194.0,186677.0] || -> node4(s49)*. % 76.16/76.38 186679[136:MRR:186593.0,186678.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.38 186680[136:Res:53.1,186679.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.38 186682[136:MRR:186680.0,78381.0] || -> . % 76.16/76.38 186683[136:Spt:186682.0,186676.0,186677.0] || until2p7(s49)*+ -> . % 76.16/76.38 186684[136:Spt:186682.0,186676.1] || -> node4(s48)*. % 76.16/76.38 186685[136:MRR:78384.0,186684.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.38 186688[136:Res:53.1,186685.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 186691[136:Res:186688.0,61.1] always3(s48) || -> . % 76.16/76.38 186692[136:SSi:186691.0,78281.0,78387.0,165540.0,186675.0,186684.0] || -> . % 76.16/76.38 186693[135:Spt:186692.0,186674.0,186675.0] || until2p7(s48)*+ -> . % 76.16/76.38 186694[135:Spt:186692.0,186674.1] || -> node4(s47)*. % 76.16/76.38 186696[135:MRR:777.0,186694.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.38 186711[135:Res:53.1,186696.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.38 186713[136:Spt:186711.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 186715[136:Res:186713.0,61.1] always3(s47) || -> . % 76.16/76.38 186716[136:SSi:186715.0,78277.0,78280.0,165539.0,186673.0,186694.0] || -> . % 76.16/76.38 186717[136:Spt:186716.0,186711.0,186713.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.38 186718[136:Spt:186716.0,186711.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 186722[136:Res:186718.0,61.1] always3(s48) || -> . % 76.16/76.38 186723[136:SSi:186722.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.38 186724[134:Spt:186723.0,186672.0,186673.0] || until2p7(s47)*+ -> . % 76.16/76.38 186725[134:Spt:186723.0,186672.1] || -> node4(s46)*. % 76.16/76.38 186727[134:MRR:780.0,186725.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.38 186737[134:Res:53.1,186727.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.38 186739[135:Spt:186737.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 186741[135:Res:186739.0,61.1] always3(s46) || -> . % 76.16/76.38 186742[135:SSi:186741.0,78272.0,78276.0,165538.0,186671.0,186725.0] || -> . % 76.16/76.38 186743[135:Spt:186742.0,186737.0,186739.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.38 186744[135:Spt:186742.0,186737.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 186748[135:Res:186744.0,61.1] always3(s47) || -> . % 76.16/76.38 186749[135:SSi:186748.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.38 186750[133:Spt:186749.0,186670.0,186671.0] || until2p7(s46)*+ -> . % 76.16/76.38 186751[133:Spt:186749.0,186670.1] || -> node4(s45)*. % 76.16/76.38 186753[133:MRR:783.0,186751.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.38 186756[133:Res:53.1,186753.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.38 186758[134:Spt:186756.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 186760[134:Res:186758.0,61.1] always3(s45) || -> . % 76.16/76.38 186761[134:SSi:186760.0,78268.0,78271.0,165537.0,186669.0,186751.0] || -> . % 76.16/76.38 186762[134:Spt:186761.0,186756.0,186758.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.38 186763[134:Spt:186761.0,186756.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 186767[134:Res:186763.0,61.1] always3(s46) || -> . % 76.16/76.38 186768[134:SSi:186767.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.38 186769[132:Spt:186768.0,186668.0,186669.0] || until2p7(s45)*+ -> . % 76.16/76.38 186770[132:Spt:186768.0,186668.1] || -> node4(s44)*. % 76.16/76.38 186772[132:MRR:786.0,186770.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.38 186775[132:Res:53.1,186772.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.38 186777[133:Spt:186775.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 186779[133:Res:186777.0,61.1] always3(s44) || -> . % 76.16/76.38 186780[133:SSi:186779.0,78263.0,78267.0,165536.0,186667.0,186770.0] || -> . % 76.16/76.38 186781[133:Spt:186780.0,186775.0,186777.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.38 186782[133:Spt:186780.0,186775.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 186786[133:Res:186782.0,61.1] always3(s45) || -> . % 76.16/76.38 186787[133:SSi:186786.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.38 186788[131:Spt:186787.0,186666.0,186667.0] || until2p7(s44)*+ -> . % 76.16/76.38 186789[131:Spt:186787.0,186666.1] || -> node4(s43)*. % 76.16/76.38 186791[131:MRR:789.0,186789.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.38 186794[131:Res:53.1,186791.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.38 186799[132:Spt:186794.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 186801[132:Res:186799.0,61.1] always3(s43) || -> . % 76.16/76.38 186802[132:SSi:186801.0,78259.0,78262.0,165535.0,186665.0,186789.0] || -> . % 76.16/76.38 186803[132:Spt:186802.0,186794.0,186799.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.38 186804[132:Spt:186802.0,186794.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 186808[132:Res:186804.0,61.1] always3(s44) || -> . % 76.16/76.38 186809[132:SSi:186808.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.38 186810[130:Spt:186809.0,186664.0,186665.0] || until2p7(s43)*+ -> . % 76.16/76.38 186811[130:Spt:186809.0,186664.1] || -> node4(s42)*. % 76.16/76.38 186813[130:MRR:792.0,186811.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.38 186816[130:Res:53.1,186813.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.38 186818[131:Spt:186816.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 186820[131:Res:186818.0,61.1] always3(s42) || -> . % 76.16/76.38 186821[131:SSi:186820.0,78254.0,78258.0,165534.0,186663.0,186811.0] || -> . % 76.16/76.38 186822[131:Spt:186821.0,186816.0,186818.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.38 186823[131:Spt:186821.0,186816.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 186827[131:Res:186823.0,61.1] always3(s43) || -> . % 76.16/76.38 186828[131:SSi:186827.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.38 186829[129:Spt:186828.0,186662.0,186663.0] || until2p7(s42)*+ -> . % 76.16/76.38 186830[129:Spt:186828.0,186662.1] || -> node4(s41)*. % 76.16/76.38 186832[129:MRR:795.0,186830.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.38 186835[129:Res:53.1,186832.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.38 186837[130:Spt:186835.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 186839[130:Res:186837.0,61.1] always3(s41) || -> . % 76.16/76.38 186840[130:SSi:186839.0,78250.0,78253.0,165533.0,186661.0,186830.0] || -> . % 76.16/76.38 186841[130:Spt:186840.0,186835.0,186837.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.38 186842[130:Spt:186840.0,186835.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 186846[130:Res:186842.0,61.1] always3(s42) || -> . % 76.16/76.38 186847[130:SSi:186846.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.38 186848[128:Spt:186847.0,186660.0,186661.0] || until2p7(s41)*+ -> . % 76.16/76.38 186849[128:Spt:186847.0,186660.1] || -> node4(s40)*. % 76.16/76.38 186851[128:MRR:798.0,186849.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.38 186854[128:Res:53.1,186851.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.38 186856[129:Spt:186854.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 186858[129:Res:186856.0,61.1] always3(s40) || -> . % 76.16/76.38 186859[129:SSi:186858.0,78245.0,78249.0,165532.0,186659.0,186849.0] || -> . % 76.16/76.38 186860[129:Spt:186859.0,186854.0,186856.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.38 186861[129:Spt:186859.0,186854.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 186865[129:Res:186861.0,61.1] always3(s41) || -> . % 76.16/76.38 186866[129:SSi:186865.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.38 186867[127:Spt:186866.0,186658.0,186659.0] || until2p7(s40)*+ -> . % 76.16/76.38 186868[127:Spt:186866.0,186658.1] || -> node4(s39)*. % 76.16/76.38 186870[127:MRR:801.0,186868.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.38 186873[127:Res:53.1,186870.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.38 186878[128:Spt:186873.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 186880[128:Res:186878.0,61.1] always3(s39) || -> . % 76.16/76.38 186881[128:SSi:186880.0,78241.0,78244.0,165531.0,186657.0,186868.0] || -> . % 76.16/76.38 186882[128:Spt:186881.0,186873.0,186878.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.38 186883[128:Spt:186881.0,186873.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 186887[128:Res:186883.0,61.1] always3(s40) || -> . % 76.16/76.38 186888[128:SSi:186887.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.38 186889[126:Spt:186888.0,186656.0,186657.0] || until2p7(s39)*+ -> . % 76.16/76.38 186890[126:Spt:186888.0,186656.1] || -> node4(s38)*. % 76.16/76.38 186892[126:MRR:804.0,186890.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.38 186895[126:Res:53.1,186892.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.38 186897[127:Spt:186895.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 186899[127:Res:186897.0,61.1] always3(s38) || -> . % 76.16/76.38 186900[127:SSi:186899.0,78236.0,78240.0,165530.0,186655.0,186890.0] || -> . % 76.16/76.38 186901[127:Spt:186900.0,186895.0,186897.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.38 186902[127:Spt:186900.0,186895.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 186906[127:Res:186902.0,61.1] always3(s39) || -> . % 76.16/76.38 186907[127:SSi:186906.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.38 186908[125:Spt:186907.0,186654.0,186655.0] || until2p7(s38)*+ -> . % 76.16/76.38 186909[125:Spt:186907.0,186654.1] || -> node4(s37)*. % 76.16/76.38 186911[125:MRR:807.0,186909.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.38 186914[125:Res:53.1,186911.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.38 186916[126:Spt:186914.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 186918[126:Res:186916.0,61.1] always3(s37) || -> . % 76.16/76.38 186919[126:SSi:186918.0,78232.0,78235.0,165529.0,186653.0,186909.0] || -> . % 76.16/76.38 186920[126:Spt:186919.0,186914.0,186916.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.38 186921[126:Spt:186919.0,186914.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 186925[126:Res:186921.0,61.1] always3(s38) || -> . % 76.16/76.38 186926[126:SSi:186925.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.38 186927[124:Spt:186926.0,186652.0,186653.0] || until2p7(s37)*+ -> . % 76.16/76.38 186928[124:Spt:186926.0,186652.1] || -> node4(s36)*. % 76.16/76.38 186930[124:MRR:810.0,186928.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.38 186933[124:Res:53.1,186930.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.38 186935[125:Spt:186933.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 186937[125:Res:186935.0,61.1] always3(s36) || -> . % 76.16/76.38 186938[125:SSi:186937.0,78227.0,78231.0,165528.0,186651.0,186928.0] || -> . % 76.16/76.38 186939[125:Spt:186938.0,186933.0,186935.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.38 186940[125:Spt:186938.0,186933.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 186944[125:Res:186940.0,61.1] always3(s37) || -> . % 76.16/76.38 186945[125:SSi:186944.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.38 186946[123:Spt:186945.0,186650.0,186651.0] || until2p7(s36)*+ -> . % 76.16/76.38 186947[123:Spt:186945.0,186650.1] || -> node4(s35)*. % 76.16/76.38 186949[123:MRR:813.0,186947.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.38 186952[123:Res:53.1,186949.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.38 186957[124:Spt:186952.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 186959[124:Res:186957.0,61.1] always3(s35) || -> . % 76.16/76.38 186960[124:SSi:186959.0,78223.0,78226.0,165527.0,186649.0,186947.0] || -> . % 76.16/76.38 186961[124:Spt:186960.0,186952.0,186957.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.38 186962[124:Spt:186960.0,186952.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 186966[124:Res:186962.0,61.1] always3(s36) || -> . % 76.16/76.38 186967[124:SSi:186966.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.38 186968[122:Spt:186967.0,186648.0,186649.0] || until2p7(s35)*+ -> . % 76.16/76.38 186969[122:Spt:186967.0,186648.1] || -> node4(s34)*. % 76.16/76.38 186971[122:MRR:816.0,186969.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.38 186974[122:Res:53.1,186971.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.38 186976[123:Spt:186974.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 186978[123:Res:186976.0,61.1] always3(s34) || -> . % 76.16/76.38 186979[123:SSi:186978.0,78218.0,78222.0,165526.0,186647.0,186969.0] || -> . % 76.16/76.38 186980[123:Spt:186979.0,186974.0,186976.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.38 186981[123:Spt:186979.0,186974.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 186985[123:Res:186981.0,61.1] always3(s35) || -> . % 76.16/76.38 186986[123:SSi:186985.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.38 186987[121:Spt:186986.0,186646.0,186647.0] || until2p7(s34)*+ -> . % 76.16/76.38 186988[121:Spt:186986.0,186646.1] || -> node4(s33)*. % 76.16/76.38 186990[121:MRR:819.0,186988.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.38 186993[121:Res:53.1,186990.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.38 186995[122:Spt:186993.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 186997[122:Res:186995.0,61.1] always3(s33) || -> . % 76.16/76.38 186998[122:SSi:186997.0,78214.0,78217.0,165525.0,186645.0,186988.0] || -> . % 76.16/76.38 186999[122:Spt:186998.0,186993.0,186995.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.38 187000[122:Spt:186998.0,186993.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 187004[122:Res:187000.0,61.1] always3(s34) || -> . % 76.16/76.38 187005[122:SSi:187004.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.38 187006[120:Spt:187005.0,186644.0,186645.0] || until2p7(s33)*+ -> . % 76.16/76.38 187007[120:Spt:187005.0,186644.1] || -> node4(s32)*. % 76.16/76.38 187009[120:MRR:822.0,187007.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.38 187012[120:Res:53.1,187009.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.38 187014[121:Spt:187012.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 187016[121:Res:187014.0,61.1] always3(s32) || -> . % 76.16/76.38 187017[121:SSi:187016.0,78209.0,78213.0,165524.0,186643.0,187007.0] || -> . % 76.16/76.38 187018[121:Spt:187017.0,187012.0,187014.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.38 187019[121:Spt:187017.0,187012.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 187023[121:Res:187019.0,61.1] always3(s33) || -> . % 76.16/76.38 187024[121:SSi:187023.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.38 187025[119:Spt:187024.0,186642.0,186643.0] || until2p7(s32)*+ -> . % 76.16/76.38 187026[119:Spt:187024.0,186642.1] || -> node4(s31)*. % 76.16/76.38 187028[119:MRR:825.0,187026.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.38 187031[119:Res:53.1,187028.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.38 187036[120:Spt:187031.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 187038[120:Res:187036.0,61.1] always3(s31) || -> . % 76.16/76.38 187039[120:SSi:187038.0,78205.0,78208.0,165523.0,186641.0,187026.0] || -> . % 76.16/76.38 187040[120:Spt:187039.0,187031.0,187036.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.38 187041[120:Spt:187039.0,187031.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 187045[120:Res:187041.0,61.1] always3(s32) || -> . % 76.16/76.38 187046[120:SSi:187045.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.38 187047[118:Spt:187046.0,186640.0,186641.0] || until2p7(s31)*+ -> . % 76.16/76.38 187048[118:Spt:187046.0,186640.1] || -> node4(s30)*. % 76.16/76.38 187050[118:MRR:828.0,187048.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.38 187053[118:Res:53.1,187050.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.38 187055[119:Spt:187053.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 187057[119:Res:187055.0,61.1] always3(s30) || -> . % 76.16/76.38 187058[119:SSi:187057.0,78200.0,78204.0,165522.0,186639.0,187048.0] || -> . % 76.16/76.38 187059[119:Spt:187058.0,187053.0,187055.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.38 187060[119:Spt:187058.0,187053.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 187064[119:Res:187060.0,61.1] always3(s31) || -> . % 76.16/76.38 187065[119:SSi:187064.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.38 187066[117:Spt:187065.0,186638.0,186639.0] || until2p7(s30)*+ -> . % 76.16/76.38 187067[117:Spt:187065.0,186638.1] || -> node4(s29)*. % 76.16/76.38 187069[117:MRR:831.0,187067.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.38 187072[117:Res:53.1,187069.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.38 187074[118:Spt:187072.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 187076[118:Res:187074.0,61.1] always3(s29) || -> . % 76.16/76.38 187077[118:SSi:187076.0,78196.0,78199.0,165521.0,186637.0,187067.0] || -> . % 76.16/76.38 187078[118:Spt:187077.0,187072.0,187074.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.38 187079[118:Spt:187077.0,187072.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 187083[118:Res:187079.0,61.1] always3(s30) || -> . % 76.16/76.38 187084[118:SSi:187083.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.38 187085[116:Spt:187084.0,186636.0,186637.0] || until2p7(s29)*+ -> . % 76.16/76.38 187086[116:Spt:187084.0,186636.1] || -> node4(s28)*. % 76.16/76.38 187088[116:MRR:834.0,187086.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.38 187091[116:Res:53.1,187088.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.38 187093[117:Spt:187091.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 187095[117:Res:187093.0,61.1] always3(s28) || -> . % 76.16/76.38 187096[117:SSi:187095.0,78191.0,78195.0,165520.0,186635.0,187086.0] || -> . % 76.16/76.38 187097[117:Spt:187096.0,187091.0,187093.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.38 187098[117:Spt:187096.0,187091.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 187102[117:Res:187098.0,61.1] always3(s29) || -> . % 76.16/76.38 187103[117:SSi:187102.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.38 187104[115:Spt:187103.0,186634.0,186635.0] || until2p7(s28)*+ -> . % 76.16/76.38 187105[115:Spt:187103.0,186634.1] || -> node4(s27)*. % 76.16/76.38 187107[115:MRR:837.0,187105.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.38 187110[115:Res:53.1,187107.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.38 187115[116:Spt:187110.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 187117[116:Res:187115.0,61.1] always3(s27) || -> . % 76.16/76.38 187118[116:SSi:187117.0,78187.0,78190.0,165519.0,186633.0,187105.0] || -> . % 76.16/76.38 187119[116:Spt:187118.0,187110.0,187115.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.38 187120[116:Spt:187118.0,187110.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 187124[116:Res:187120.0,61.1] always3(s28) || -> . % 76.16/76.38 187125[116:SSi:187124.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.38 187126[114:Spt:187125.0,186632.0,186633.0] || until2p7(s27)*+ -> . % 76.16/76.38 187127[114:Spt:187125.0,186632.1] || -> node4(s26)*. % 76.16/76.38 187129[114:MRR:840.0,187127.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.38 187132[114:Res:53.1,187129.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.38 187134[115:Spt:187132.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 187136[115:Res:187134.0,61.1] always3(s26) || -> . % 76.16/76.38 187137[115:SSi:187136.0,78182.0,78186.0,165518.0,186631.0,187127.0] || -> . % 76.16/76.38 187138[115:Spt:187137.0,187132.0,187134.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.38 187139[115:Spt:187137.0,187132.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 187143[115:Res:187139.0,61.1] always3(s27) || -> . % 76.16/76.38 187144[115:SSi:187143.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.38 187145[113:Spt:187144.0,186630.0,186631.0] || until2p7(s26)*+ -> . % 76.16/76.38 187146[113:Spt:187144.0,186630.1] || -> node4(s25)*. % 76.16/76.38 187148[113:MRR:843.0,187146.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.38 187151[113:Res:53.1,187148.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.38 187153[114:Spt:187151.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 187155[114:Res:187153.0,61.1] always3(s25) || -> . % 76.16/76.38 187156[114:SSi:187155.0,78178.0,78181.0,165517.0,186629.0,187146.0] || -> . % 76.16/76.38 187157[114:Spt:187156.0,187151.0,187153.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.38 187158[114:Spt:187156.0,187151.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 187162[114:Res:187158.0,61.1] always3(s26) || -> . % 76.16/76.38 187163[114:SSi:187162.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.38 187164[112:Spt:187163.0,186628.0,186629.0] || until2p7(s25)*+ -> . % 76.16/76.38 187165[112:Spt:187163.0,186628.1] || -> node4(s24)*. % 76.16/76.38 187167[112:MRR:846.0,187165.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.38 187170[112:Res:53.1,187167.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.38 187172[113:Spt:187170.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 187174[113:Res:187172.0,61.1] always3(s24) || -> . % 76.16/76.38 187175[113:SSi:187174.0,78173.0,78177.0,165516.0,186627.0,187165.0] || -> . % 76.16/76.38 187176[113:Spt:187175.0,187170.0,187172.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.38 187177[113:Spt:187175.0,187170.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 187181[113:Res:187177.0,61.1] always3(s25) || -> . % 76.16/76.38 187182[113:SSi:187181.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.38 187183[111:Spt:187182.0,186626.0,186627.0] || until2p7(s24)*+ -> . % 76.16/76.38 187184[111:Spt:187182.0,186626.1] || -> node4(s23)*. % 76.16/76.38 187186[111:MRR:849.0,187184.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.38 187189[111:Res:53.1,187186.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.38 187194[112:Spt:187189.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 187196[112:Res:187194.0,61.1] always3(s23) || -> . % 76.16/76.38 187197[112:SSi:187196.0,78169.0,78172.0,165515.0,186625.0,187184.0] || -> . % 76.16/76.38 187198[112:Spt:187197.0,187189.0,187194.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.38 187199[112:Spt:187197.0,187189.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 187203[112:Res:187199.0,61.1] always3(s24) || -> . % 76.16/76.38 187204[112:SSi:187203.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.38 187205[110:Spt:187204.0,186624.0,186625.0] || until2p7(s23)*+ -> . % 76.16/76.38 187206[110:Spt:187204.0,186624.1] || -> node4(s22)*. % 76.16/76.38 187208[110:MRR:852.0,187206.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.38 187211[110:Res:53.1,187208.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.38 187213[111:Spt:187211.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 187215[111:Res:187213.0,61.1] always3(s22) || -> . % 76.16/76.38 187216[111:SSi:187215.0,78164.0,78168.0,165514.0,186623.0,187206.0] || -> . % 76.16/76.38 187217[111:Spt:187216.0,187211.0,187213.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.38 187218[111:Spt:187216.0,187211.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 187222[111:Res:187218.0,61.1] always3(s23) || -> . % 76.16/76.38 187223[111:SSi:187222.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.38 187224[109:Spt:187223.0,186622.0,186623.0] || until2p7(s22)*+ -> . % 76.16/76.38 187225[109:Spt:187223.0,186622.1] || -> node4(s21)*. % 76.16/76.38 187227[109:MRR:855.0,187225.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.38 187230[109:Res:53.1,187227.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.38 187232[110:Spt:187230.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 187234[110:Res:187232.0,61.1] always3(s21) || -> . % 76.16/76.38 187235[110:SSi:187234.0,78160.0,78163.0,165513.0,186621.0,187225.0] || -> . % 76.16/76.38 187236[110:Spt:187235.0,187230.0,187232.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.38 187237[110:Spt:187235.0,187230.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 187241[110:Res:187237.0,61.1] always3(s22) || -> . % 76.16/76.38 187242[110:SSi:187241.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.38 187243[108:Spt:187242.0,186620.0,186621.0] || until2p7(s21)*+ -> . % 76.16/76.38 187244[108:Spt:187242.0,186620.1] || -> node4(s20)*. % 76.16/76.38 187246[108:MRR:858.0,187244.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.38 187249[108:Res:53.1,187246.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.38 187251[109:Spt:187249.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 187253[109:Res:187251.0,61.1] always3(s20) || -> . % 76.16/76.38 187254[109:SSi:187253.0,78155.0,78159.0,165512.0,186619.0,187244.0] || -> . % 76.16/76.38 187255[109:Spt:187254.0,187249.0,187251.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.38 187256[109:Spt:187254.0,187249.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 187260[109:Res:187256.0,61.1] always3(s21) || -> . % 76.16/76.38 187261[109:SSi:187260.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.38 187262[107:Spt:187261.0,186618.0,186619.0] || until2p7(s20)*+ -> . % 76.16/76.38 187263[107:Spt:187261.0,186618.1] || -> node4(s19)*. % 76.16/76.38 187265[107:MRR:861.0,187263.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.38 187268[107:Res:53.1,187265.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.38 187273[108:Spt:187268.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 187275[108:Res:187273.0,61.1] always3(s19) || -> . % 76.16/76.38 187276[108:SSi:187275.0,78151.0,78154.0,165511.0,186617.0,187263.0] || -> . % 76.16/76.38 187277[108:Spt:187276.0,187268.0,187273.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.38 187278[108:Spt:187276.0,187268.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 187282[108:Res:187278.0,61.1] always3(s20) || -> . % 76.16/76.38 187283[108:SSi:187282.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.38 187284[106:Spt:187283.0,186616.0,186617.0] || until2p7(s19)*+ -> . % 76.16/76.38 187285[106:Spt:187283.0,186616.1] || -> node4(s18)*. % 76.16/76.38 187287[106:MRR:864.0,187285.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.38 187290[106:Res:53.1,187287.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.38 187292[107:Spt:187290.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 187294[107:Res:187292.0,61.1] always3(s18) || -> . % 76.16/76.38 187295[107:SSi:187294.0,78146.0,78150.0,165510.0,186615.0,187285.0] || -> . % 76.16/76.38 187296[107:Spt:187295.0,187290.0,187292.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.38 187297[107:Spt:187295.0,187290.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 187301[107:Res:187297.0,61.1] always3(s19) || -> . % 76.16/76.38 187302[107:SSi:187301.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.38 187303[105:Spt:187302.0,186614.0,186615.0] || until2p7(s18)*+ -> . % 76.16/76.38 187304[105:Spt:187302.0,186614.1] || -> node4(s17)*. % 76.16/76.38 187306[105:MRR:867.0,187304.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.38 187309[105:Res:53.1,187306.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.38 187311[106:Spt:187309.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 187313[106:Res:187311.0,61.1] always3(s17) || -> . % 76.16/76.38 187314[106:SSi:187313.0,78142.0,78145.0,165509.0,186613.0,187304.0] || -> . % 76.16/76.38 187315[106:Spt:187314.0,187309.0,187311.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.38 187316[106:Spt:187314.0,187309.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 187320[106:Res:187316.0,61.1] always3(s18) || -> . % 76.16/76.38 187321[106:SSi:187320.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.38 187322[104:Spt:187321.0,186612.0,186613.0] || until2p7(s17)*+ -> . % 76.16/76.38 187323[104:Spt:187321.0,186612.1] || -> node4(s16)*. % 76.16/76.38 187325[104:MRR:870.0,187323.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.38 187328[104:Res:53.1,187325.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.38 187330[105:Spt:187328.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 187332[105:Res:187330.0,61.1] always3(s16) || -> . % 76.16/76.38 187333[105:SSi:187332.0,78137.0,78141.0,165508.0,186611.0,187323.0] || -> . % 76.16/76.38 187334[105:Spt:187333.0,187328.0,187330.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.38 187335[105:Spt:187333.0,187328.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 187339[105:Res:187335.0,61.1] always3(s17) || -> . % 76.16/76.38 187340[105:SSi:187339.0,78142.0,78145.0,165509.0] || -> . % 76.16/76.38 187341[103:Spt:187340.0,186610.0,186611.0] || until2p7(s16)*+ -> . % 76.16/76.38 187342[103:Spt:187340.0,186610.1] || -> node4(s15)*. % 76.16/76.38 187344[103:MRR:873.0,187342.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.38 187347[103:Res:53.1,187344.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.38 187352[104:Spt:187347.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 187354[104:Res:187352.0,61.1] always3(s15) || -> . % 76.16/76.38 187355[104:SSi:187354.0,78133.0,78136.0,165507.0,186609.0,187342.0] || -> . % 76.16/76.38 187356[104:Spt:187355.0,187347.0,187352.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.38 187357[104:Spt:187355.0,187347.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 187361[104:Res:187357.0,61.1] always3(s16) || -> . % 76.16/76.38 187362[104:SSi:187361.0,78137.0,78141.0,165508.0] || -> . % 76.16/76.38 187363[102:Spt:187362.0,186608.0,186609.0] || until2p7(s15)*+ -> . % 76.16/76.38 187364[102:Spt:187362.0,186608.1] || -> node4(s14)*. % 76.16/76.38 187366[102:MRR:876.0,187364.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.38 187369[102:Res:53.1,187366.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.38 187371[103:Spt:187369.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 187373[103:Res:187371.0,61.1] always3(s14) || -> . % 76.16/76.38 187374[103:SSi:187373.0,78128.0,78132.0,165506.0,186607.0,187364.0] || -> . % 76.16/76.38 187375[103:Spt:187374.0,187369.0,187371.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.38 187376[103:Spt:187374.0,187369.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 187380[103:Res:187376.0,61.1] always3(s15) || -> . % 76.16/76.38 187381[103:SSi:187380.0,78133.0,78136.0,165507.0] || -> . % 76.16/76.38 187382[101:Spt:187381.0,186606.0,186607.0] || until2p7(s14)*+ -> . % 76.16/76.38 187383[101:Spt:187381.0,186606.1] || -> node4(s13)*. % 76.16/76.38 187385[101:MRR:879.0,187383.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.38 187388[101:Res:53.1,187385.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.38 187390[102:Spt:187388.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 187392[102:Res:187390.0,61.1] always3(s13) || -> . % 76.16/76.38 187393[102:SSi:187392.0,78124.0,78127.0,165505.0,186605.0,187383.0] || -> . % 76.16/76.38 187394[102:Spt:187393.0,187388.0,187390.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.38 187395[102:Spt:187393.0,187388.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 187399[102:Res:187395.0,61.1] always3(s14) || -> . % 76.16/76.38 187400[102:SSi:187399.0,78128.0,78132.0,165506.0] || -> . % 76.16/76.38 187401[100:Spt:187400.0,186604.0,186605.0] || until2p7(s13)*+ -> . % 76.16/76.38 187402[100:Spt:187400.0,186604.1] || -> node4(s12)*. % 76.16/76.38 187404[100:MRR:882.0,187402.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.38 187407[100:Res:53.1,187404.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.38 187409[101:Spt:187407.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.38 187411[101:Res:187409.0,61.1] always3(s12) || -> . % 76.16/76.38 187412[101:SSi:187411.0,78119.0,78123.0,165504.0,186603.0,187402.0] || -> . % 76.16/76.38 187413[101:Spt:187412.0,187407.0,187409.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.38 187414[101:Spt:187412.0,187407.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 187418[101:Res:187414.0,61.1] always3(s13) || -> . % 76.16/76.38 187419[101:SSi:187418.0,78124.0,78127.0,165505.0] || -> . % 76.16/76.38 187420[99:Spt:187419.0,186602.0,186603.0] || until2p7(s12)*+ -> . % 76.16/76.38 187421[99:Spt:187419.0,186602.1] || -> node4(s11)*. % 76.16/76.38 187423[99:MRR:885.0,187421.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.38 187426[99:Res:53.1,187423.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.38 187431[100:Spt:187426.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.38 187433[100:Res:187431.0,61.1] always3(s11) || -> . % 76.16/76.38 187434[100:SSi:187433.0,78115.0,78118.0,165503.0,186601.0,187421.0] || -> . % 76.16/76.38 187435[100:Spt:187434.0,187426.0,187431.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.38 187436[100:Spt:187434.0,187426.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.38 187440[100:Res:187436.0,61.1] always3(s12) || -> . % 76.16/76.38 187441[100:SSi:187440.0,78119.0,78123.0,165504.0] || -> . % 76.16/76.38 187442[98:Spt:187441.0,186600.0,186601.0] || until2p7(s11)*+ -> . % 76.16/76.38 187443[98:Spt:187441.0,186600.1] || -> node4(s10)*. % 76.16/76.38 187445[98:MRR:888.0,187443.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.38 187448[98:Res:53.1,187445.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.38 187450[99:Spt:187448.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.38 187452[99:Res:187450.0,61.1] always3(s10) || -> . % 76.16/76.38 187453[99:SSi:187452.0,78110.0,78114.0,165502.0,186599.0,187443.0] || -> . % 76.16/76.38 187454[99:Spt:187453.0,187448.0,187450.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.38 187455[99:Spt:187453.0,187448.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.38 187459[99:Res:187455.0,61.1] always3(s11) || -> . % 76.16/76.38 187460[99:SSi:187459.0,78115.0,78118.0,165503.0] || -> . % 76.16/76.38 187461[97:Spt:187460.0,186598.0,186599.0] || until2p7(s10)*+ -> . % 76.16/76.38 187462[97:Spt:187460.0,186598.1] || -> node4(s9)*. % 76.16/76.38 187464[97:MRR:891.0,187462.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.38 187467[97:Res:53.1,187464.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.38 187469[97:MRR:187467.0,186588.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.38 187471[97:Res:187469.0,61.1] always3(s10) || -> . % 76.16/76.38 187472[97:SSi:187471.0,78110.0,78114.0,165502.0] || -> . % 76.16/76.38 187473[95:Spt:187472.0,186439.0,186442.0] || trans(s49,s9)*+ -> . % 76.16/76.38 187474[95:Spt:187472.0,186439.1,186439.2,186439.3,186439.4] || -> trans(s49,s8) trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.38 187476[95:MRR:186441.1,187473.0] xuntil6(s49) || -> trans(s49,s8) trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.38 187477[96:Spt:187474.0] || -> trans(s49,s8)*. % 76.16/76.38 187478[96:Res:187477.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s8)*. % 76.16/76.38 187480[96:Res:187477.0,60.0] || -> node2(s49,s8)*. % 76.16/76.38 187481[96:SSi:187478.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s8)*. % 76.16/76.38 187482[96:Res:187480.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)*. % 76.16/76.38 187619[96:SoR:187482.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)*. % 76.16/76.38 187621[96:SoR:187619.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)* xuntil6(s49). % 76.16/76.38 187622[96:SSi:187621.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s8,c_busy)* xuntil6(s49). % 76.16/76.38 187623[97:Spt:187622.1] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.38 187625[97:Res:187623.0,61.1] always3(s8) || -> . % 76.16/76.38 187626[97:SSi:187625.0,78101.0,78105.0,165500.0] || -> . % 76.16/76.38 187627[97:Spt:187626.0,187622.1,187623.0] || m_main_v_state(s8,c_busy)*+ -> . % 76.16/76.38 187628[97:Spt:187626.0,187622.0,187622.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.38 187632[97:MRR:187619.2,187627.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.38 187633[97:Res:53.1,187628.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.38 187635[97:MRR:187633.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.38 187636[97:MRR:187481.0,187635.0] || -> until2p7(s8)*. % 76.16/76.38 187637[97:MRR:204.0,187636.0] || -> until2p7(s9)* node4(s8). % 76.16/76.38 187638[98:Spt:187637.0] || -> until2p7(s9)*. % 76.16/76.38 187639[98:MRR:205.0,187638.0] || -> until2p7(s10)* node4(s9). % 76.16/76.38 187640[99:Spt:187639.0] || -> until2p7(s10)*. % 76.16/76.38 187641[99:MRR:206.0,187640.0] || -> until2p7(s11)* node4(s10). % 76.16/76.38 187642[100:Spt:187641.0] || -> until2p7(s11)*. % 76.16/76.38 187643[100:MRR:207.0,187642.0] || -> until2p7(s12)* node4(s11). % 76.16/76.38 187644[101:Spt:187643.0] || -> until2p7(s12)*. % 76.16/76.38 187645[101:MRR:208.0,187644.0] || -> until2p7(s13)* node4(s12). % 76.16/76.38 187646[102:Spt:187645.0] || -> until2p7(s13)*. % 76.16/76.38 187647[102:MRR:209.0,187646.0] || -> until2p7(s14)* node4(s13). % 76.16/76.38 187648[103:Spt:187647.0] || -> until2p7(s14)*. % 76.16/76.38 187649[103:MRR:210.0,187648.0] || -> until2p7(s15)* node4(s14). % 76.16/76.38 187650[104:Spt:187649.0] || -> until2p7(s15)*. % 76.16/76.38 187651[104:MRR:211.0,187650.0] || -> until2p7(s16)* node4(s15). % 76.16/76.38 187652[105:Spt:187651.0] || -> until2p7(s16)*. % 76.16/76.38 187653[105:MRR:212.0,187652.0] || -> until2p7(s17)* node4(s16). % 76.16/76.38 187654[106:Spt:187653.0] || -> until2p7(s17)*. % 76.16/76.38 187655[106:MRR:213.0,187654.0] || -> until2p7(s18)* node4(s17). % 76.16/76.38 187656[107:Spt:187655.0] || -> until2p7(s18)*. % 76.16/76.38 187657[107:MRR:214.0,187656.0] || -> until2p7(s19)* node4(s18). % 76.16/76.38 187658[108:Spt:187657.0] || -> until2p7(s19)*. % 76.16/76.38 187659[108:MRR:215.0,187658.0] || -> until2p7(s20)* node4(s19). % 76.16/76.38 187660[109:Spt:187659.0] || -> until2p7(s20)*. % 76.16/76.38 187661[109:MRR:216.0,187660.0] || -> until2p7(s21)* node4(s20). % 76.16/76.38 187662[110:Spt:187661.0] || -> until2p7(s21)*. % 76.16/76.38 187663[110:MRR:217.0,187662.0] || -> until2p7(s22)* node4(s21). % 76.16/76.38 187664[111:Spt:187663.0] || -> until2p7(s22)*. % 76.16/76.38 187665[111:MRR:218.0,187664.0] || -> until2p7(s23)* node4(s22). % 76.16/76.38 187666[112:Spt:187665.0] || -> until2p7(s23)*. % 76.16/76.38 187667[112:MRR:219.0,187666.0] || -> until2p7(s24)* node4(s23). % 76.16/76.38 187668[113:Spt:187667.0] || -> until2p7(s24)*. % 76.16/76.38 187669[113:MRR:220.0,187668.0] || -> until2p7(s25)* node4(s24). % 76.16/76.38 187670[114:Spt:187669.0] || -> until2p7(s25)*. % 76.16/76.38 187671[114:MRR:221.0,187670.0] || -> until2p7(s26)* node4(s25). % 76.16/76.38 187672[115:Spt:187671.0] || -> until2p7(s26)*. % 76.16/76.38 187673[115:MRR:222.0,187672.0] || -> until2p7(s27)* node4(s26). % 76.16/76.38 187674[116:Spt:187673.0] || -> until2p7(s27)*. % 76.16/76.38 187675[116:MRR:223.0,187674.0] || -> until2p7(s28)* node4(s27). % 76.16/76.38 187676[117:Spt:187675.0] || -> until2p7(s28)*. % 76.16/76.38 187677[117:MRR:224.0,187676.0] || -> until2p7(s29)* node4(s28). % 76.16/76.38 187678[118:Spt:187677.0] || -> until2p7(s29)*. % 76.16/76.38 187679[118:MRR:225.0,187678.0] || -> until2p7(s30)* node4(s29). % 76.16/76.38 187680[119:Spt:187679.0] || -> until2p7(s30)*. % 76.16/76.38 187681[119:MRR:226.0,187680.0] || -> until2p7(s31)* node4(s30). % 76.16/76.38 187682[120:Spt:187681.0] || -> until2p7(s31)*. % 76.16/76.38 187683[120:MRR:227.0,187682.0] || -> until2p7(s32)* node4(s31). % 76.16/76.38 187684[121:Spt:187683.0] || -> until2p7(s32)*. % 76.16/76.38 187685[121:MRR:228.0,187684.0] || -> until2p7(s33)* node4(s32). % 76.16/76.38 187686[122:Spt:187685.0] || -> until2p7(s33)*. % 76.16/76.38 187687[122:MRR:229.0,187686.0] || -> until2p7(s34)* node4(s33). % 76.16/76.38 187688[123:Spt:187687.0] || -> until2p7(s34)*. % 76.16/76.38 187689[123:MRR:230.0,187688.0] || -> until2p7(s35)* node4(s34). % 76.16/76.38 187690[124:Spt:187689.0] || -> until2p7(s35)*. % 76.16/76.38 187691[124:MRR:231.0,187690.0] || -> until2p7(s36)* node4(s35). % 76.16/76.38 187692[125:Spt:187691.0] || -> until2p7(s36)*. % 76.16/76.38 187693[125:MRR:232.0,187692.0] || -> until2p7(s37)* node4(s36). % 76.16/76.38 187694[126:Spt:187693.0] || -> until2p7(s37)*. % 76.16/76.38 187695[126:MRR:235.0,187694.0] || -> until2p7(s38)* node4(s37). % 76.16/76.38 187696[127:Spt:187695.0] || -> until2p7(s38)*. % 76.16/76.38 187697[127:MRR:236.0,187696.0] || -> until2p7(s39)* node4(s38). % 76.16/76.38 187698[128:Spt:187697.0] || -> until2p7(s39)*. % 76.16/76.38 187699[128:MRR:237.0,187698.0] || -> until2p7(s40)* node4(s39). % 76.16/76.38 187700[129:Spt:187699.0] || -> until2p7(s40)*. % 76.16/76.38 187701[129:MRR:238.0,187700.0] || -> until2p7(s41)* node4(s40). % 76.16/76.38 187702[130:Spt:187701.0] || -> until2p7(s41)*. % 76.16/76.38 187703[130:MRR:239.0,187702.0] || -> until2p7(s42)* node4(s41). % 76.16/76.38 187704[131:Spt:187703.0] || -> until2p7(s42)*. % 76.16/76.38 187705[131:MRR:240.0,187704.0] || -> until2p7(s43)* node4(s42). % 76.16/76.38 187706[132:Spt:187705.0] || -> until2p7(s43)*. % 76.16/76.38 187707[132:MRR:241.0,187706.0] || -> until2p7(s44)* node4(s43). % 76.16/76.38 187708[133:Spt:187707.0] || -> until2p7(s44)*. % 76.16/76.38 187709[133:MRR:539.0,187708.0] || -> until2p7(s45)* node4(s44). % 76.16/76.38 187710[134:Spt:187709.0] || -> until2p7(s45)*. % 76.16/76.38 187711[134:MRR:544.0,187710.0] || -> until2p7(s46)* node4(s45). % 76.16/76.38 187712[135:Spt:187711.0] || -> until2p7(s46)*. % 76.16/76.38 187713[135:MRR:549.0,187712.0] || -> until2p7(s47)* node4(s46). % 76.16/76.38 187714[136:Spt:187713.0] || -> until2p7(s47)*. % 76.16/76.38 187715[136:MRR:554.0,187714.0] || -> until2p7(s48)* node4(s47). % 76.16/76.38 187716[137:Spt:187715.0] || -> until2p7(s48)*. % 76.16/76.38 187717[137:MRR:559.0,187716.0] || -> until2p7(s49)* node4(s48). % 76.16/76.38 187718[138:Spt:187717.0] || -> until2p7(s49)*. % 76.16/76.38 187719[138:MRR:194.0,187718.0] || -> node4(s49)*. % 76.16/76.38 187720[138:MRR:187632.0,187719.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.38 187724[138:Res:53.1,187720.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.38 187726[138:MRR:187724.0,78381.0] || -> . % 76.16/76.38 187727[138:Spt:187726.0,187717.0,187718.0] || until2p7(s49)*+ -> . % 76.16/76.38 187728[138:Spt:187726.0,187717.1] || -> node4(s48)*. % 76.16/76.38 187729[138:MRR:78384.0,187728.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.38 187732[138:Res:53.1,187729.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 187735[138:Res:187732.0,61.1] always3(s48) || -> . % 76.16/76.38 187736[138:SSi:187735.0,78281.0,78387.0,165540.0,187716.0,187728.0] || -> . % 76.16/76.38 187737[137:Spt:187736.0,187715.0,187716.0] || until2p7(s48)*+ -> . % 76.16/76.38 187738[137:Spt:187736.0,187715.1] || -> node4(s47)*. % 76.16/76.38 187740[137:MRR:777.0,187738.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.38 187752[137:Res:53.1,187740.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.38 187754[138:Spt:187752.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 187756[138:Res:187754.0,61.1] always3(s47) || -> . % 76.16/76.38 187757[138:SSi:187756.0,78277.0,78280.0,165539.0,187714.0,187738.0] || -> . % 76.16/76.38 187758[138:Spt:187757.0,187752.0,187754.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.38 187759[138:Spt:187757.0,187752.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 187763[138:Res:187759.0,61.1] always3(s48) || -> . % 76.16/76.38 187764[138:SSi:187763.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.38 187765[136:Spt:187764.0,187713.0,187714.0] || until2p7(s47)*+ -> . % 76.16/76.38 187766[136:Spt:187764.0,187713.1] || -> node4(s46)*. % 76.16/76.38 187768[136:MRR:780.0,187766.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.38 187775[136:Res:53.1,187768.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.38 187780[137:Spt:187775.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 187782[137:Res:187780.0,61.1] always3(s46) || -> . % 76.16/76.38 187783[137:SSi:187782.0,78272.0,78276.0,165538.0,187712.0,187766.0] || -> . % 76.16/76.38 187784[137:Spt:187783.0,187775.0,187780.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.38 187785[137:Spt:187783.0,187775.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 187789[137:Res:187785.0,61.1] always3(s47) || -> . % 76.16/76.38 187790[137:SSi:187789.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.38 187791[135:Spt:187790.0,187711.0,187712.0] || until2p7(s46)*+ -> . % 76.16/76.38 187792[135:Spt:187790.0,187711.1] || -> node4(s45)*. % 76.16/76.38 187794[135:MRR:783.0,187792.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.38 187797[135:Res:53.1,187794.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.38 187799[136:Spt:187797.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 187801[136:Res:187799.0,61.1] always3(s45) || -> . % 76.16/76.38 187802[136:SSi:187801.0,78268.0,78271.0,165537.0,187710.0,187792.0] || -> . % 76.16/76.38 187803[136:Spt:187802.0,187797.0,187799.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.38 187804[136:Spt:187802.0,187797.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 187808[136:Res:187804.0,61.1] always3(s46) || -> . % 76.16/76.38 187809[136:SSi:187808.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.38 187810[134:Spt:187809.0,187709.0,187710.0] || until2p7(s45)*+ -> . % 76.16/76.38 187811[134:Spt:187809.0,187709.1] || -> node4(s44)*. % 76.16/76.38 187813[134:MRR:786.0,187811.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.38 187816[134:Res:53.1,187813.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.38 187818[135:Spt:187816.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 187820[135:Res:187818.0,61.1] always3(s44) || -> . % 76.16/76.38 187821[135:SSi:187820.0,78263.0,78267.0,165536.0,187708.0,187811.0] || -> . % 76.16/76.38 187822[135:Spt:187821.0,187816.0,187818.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.38 187823[135:Spt:187821.0,187816.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 187827[135:Res:187823.0,61.1] always3(s45) || -> . % 76.16/76.38 187828[135:SSi:187827.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.38 187829[133:Spt:187828.0,187707.0,187708.0] || until2p7(s44)*+ -> . % 76.16/76.38 187830[133:Spt:187828.0,187707.1] || -> node4(s43)*. % 76.16/76.38 187832[133:MRR:789.0,187830.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.38 187835[133:Res:53.1,187832.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.38 187837[134:Spt:187835.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 187839[134:Res:187837.0,61.1] always3(s43) || -> . % 76.16/76.38 187840[134:SSi:187839.0,78259.0,78262.0,165535.0,187706.0,187830.0] || -> . % 76.16/76.38 187841[134:Spt:187840.0,187835.0,187837.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.38 187842[134:Spt:187840.0,187835.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 187846[134:Res:187842.0,61.1] always3(s44) || -> . % 76.16/76.38 187847[134:SSi:187846.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.38 187848[132:Spt:187847.0,187705.0,187706.0] || until2p7(s43)*+ -> . % 76.16/76.38 187849[132:Spt:187847.0,187705.1] || -> node4(s42)*. % 76.16/76.38 187851[132:MRR:792.0,187849.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.38 187854[132:Res:53.1,187851.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.38 187859[133:Spt:187854.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 187861[133:Res:187859.0,61.1] always3(s42) || -> . % 76.16/76.38 187862[133:SSi:187861.0,78254.0,78258.0,165534.0,187704.0,187849.0] || -> . % 76.16/76.38 187863[133:Spt:187862.0,187854.0,187859.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.38 187864[133:Spt:187862.0,187854.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 187868[133:Res:187864.0,61.1] always3(s43) || -> . % 76.16/76.38 187869[133:SSi:187868.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.38 187870[131:Spt:187869.0,187703.0,187704.0] || until2p7(s42)*+ -> . % 76.16/76.38 187871[131:Spt:187869.0,187703.1] || -> node4(s41)*. % 76.16/76.38 187873[131:MRR:795.0,187871.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.38 187876[131:Res:53.1,187873.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.38 187878[132:Spt:187876.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 187880[132:Res:187878.0,61.1] always3(s41) || -> . % 76.16/76.38 187881[132:SSi:187880.0,78250.0,78253.0,165533.0,187702.0,187871.0] || -> . % 76.16/76.38 187882[132:Spt:187881.0,187876.0,187878.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.38 187883[132:Spt:187881.0,187876.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 187887[132:Res:187883.0,61.1] always3(s42) || -> . % 76.16/76.38 187888[132:SSi:187887.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.38 187889[130:Spt:187888.0,187701.0,187702.0] || until2p7(s41)*+ -> . % 76.16/76.38 187890[130:Spt:187888.0,187701.1] || -> node4(s40)*. % 76.16/76.38 187892[130:MRR:798.0,187890.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.38 187895[130:Res:53.1,187892.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.38 187897[131:Spt:187895.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 187899[131:Res:187897.0,61.1] always3(s40) || -> . % 76.16/76.38 187900[131:SSi:187899.0,78245.0,78249.0,165532.0,187700.0,187890.0] || -> . % 76.16/76.38 187901[131:Spt:187900.0,187895.0,187897.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.38 187902[131:Spt:187900.0,187895.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 187906[131:Res:187902.0,61.1] always3(s41) || -> . % 76.16/76.38 187907[131:SSi:187906.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.38 187908[129:Spt:187907.0,187699.0,187700.0] || until2p7(s40)*+ -> . % 76.16/76.38 187909[129:Spt:187907.0,187699.1] || -> node4(s39)*. % 76.16/76.38 187911[129:MRR:801.0,187909.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.38 187914[129:Res:53.1,187911.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.38 187916[130:Spt:187914.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 187918[130:Res:187916.0,61.1] always3(s39) || -> . % 76.16/76.38 187919[130:SSi:187918.0,78241.0,78244.0,165531.0,187698.0,187909.0] || -> . % 76.16/76.38 187920[130:Spt:187919.0,187914.0,187916.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.38 187921[130:Spt:187919.0,187914.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 187925[130:Res:187921.0,61.1] always3(s40) || -> . % 76.16/76.38 187926[130:SSi:187925.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.38 187927[128:Spt:187926.0,187697.0,187698.0] || until2p7(s39)*+ -> . % 76.16/76.38 187928[128:Spt:187926.0,187697.1] || -> node4(s38)*. % 76.16/76.38 187930[128:MRR:804.0,187928.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.38 187933[128:Res:53.1,187930.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.38 187938[129:Spt:187933.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 187940[129:Res:187938.0,61.1] always3(s38) || -> . % 76.16/76.38 187941[129:SSi:187940.0,78236.0,78240.0,165530.0,187696.0,187928.0] || -> . % 76.16/76.38 187942[129:Spt:187941.0,187933.0,187938.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.38 187943[129:Spt:187941.0,187933.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 187947[129:Res:187943.0,61.1] always3(s39) || -> . % 76.16/76.38 187948[129:SSi:187947.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.38 187949[127:Spt:187948.0,187695.0,187696.0] || until2p7(s38)*+ -> . % 76.16/76.38 187950[127:Spt:187948.0,187695.1] || -> node4(s37)*. % 76.16/76.38 187952[127:MRR:807.0,187950.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.38 187955[127:Res:53.1,187952.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.38 187957[128:Spt:187955.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 187959[128:Res:187957.0,61.1] always3(s37) || -> . % 76.16/76.38 187960[128:SSi:187959.0,78232.0,78235.0,165529.0,187694.0,187950.0] || -> . % 76.16/76.38 187961[128:Spt:187960.0,187955.0,187957.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.38 187962[128:Spt:187960.0,187955.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 187966[128:Res:187962.0,61.1] always3(s38) || -> . % 76.16/76.38 187967[128:SSi:187966.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.38 187968[126:Spt:187967.0,187693.0,187694.0] || until2p7(s37)*+ -> . % 76.16/76.38 187969[126:Spt:187967.0,187693.1] || -> node4(s36)*. % 76.16/76.38 187971[126:MRR:810.0,187969.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.38 187974[126:Res:53.1,187971.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.38 187976[127:Spt:187974.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 187978[127:Res:187976.0,61.1] always3(s36) || -> . % 76.16/76.38 187979[127:SSi:187978.0,78227.0,78231.0,165528.0,187692.0,187969.0] || -> . % 76.16/76.38 187980[127:Spt:187979.0,187974.0,187976.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.38 187981[127:Spt:187979.0,187974.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 187985[127:Res:187981.0,61.1] always3(s37) || -> . % 76.16/76.38 187986[127:SSi:187985.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.38 187987[125:Spt:187986.0,187691.0,187692.0] || until2p7(s36)*+ -> . % 76.16/76.38 187988[125:Spt:187986.0,187691.1] || -> node4(s35)*. % 76.16/76.38 187990[125:MRR:813.0,187988.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.38 187993[125:Res:53.1,187990.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.38 187995[126:Spt:187993.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 187997[126:Res:187995.0,61.1] always3(s35) || -> . % 76.16/76.38 187998[126:SSi:187997.0,78223.0,78226.0,165527.0,187690.0,187988.0] || -> . % 76.16/76.38 187999[126:Spt:187998.0,187993.0,187995.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.38 188000[126:Spt:187998.0,187993.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 188004[126:Res:188000.0,61.1] always3(s36) || -> . % 76.16/76.38 188005[126:SSi:188004.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.38 188006[124:Spt:188005.0,187689.0,187690.0] || until2p7(s35)*+ -> . % 76.16/76.38 188007[124:Spt:188005.0,187689.1] || -> node4(s34)*. % 76.16/76.38 188009[124:MRR:816.0,188007.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.38 188012[124:Res:53.1,188009.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.38 188017[125:Spt:188012.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 188019[125:Res:188017.0,61.1] always3(s34) || -> . % 76.16/76.38 188020[125:SSi:188019.0,78218.0,78222.0,165526.0,187688.0,188007.0] || -> . % 76.16/76.38 188021[125:Spt:188020.0,188012.0,188017.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.38 188022[125:Spt:188020.0,188012.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 188026[125:Res:188022.0,61.1] always3(s35) || -> . % 76.16/76.38 188027[125:SSi:188026.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.38 188028[123:Spt:188027.0,187687.0,187688.0] || until2p7(s34)*+ -> . % 76.16/76.38 188029[123:Spt:188027.0,187687.1] || -> node4(s33)*. % 76.16/76.38 188031[123:MRR:819.0,188029.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.38 188034[123:Res:53.1,188031.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.38 188036[124:Spt:188034.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 188038[124:Res:188036.0,61.1] always3(s33) || -> . % 76.16/76.38 188039[124:SSi:188038.0,78214.0,78217.0,165525.0,187686.0,188029.0] || -> . % 76.16/76.38 188040[124:Spt:188039.0,188034.0,188036.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.38 188041[124:Spt:188039.0,188034.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 188045[124:Res:188041.0,61.1] always3(s34) || -> . % 76.16/76.38 188046[124:SSi:188045.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.38 188047[122:Spt:188046.0,187685.0,187686.0] || until2p7(s33)*+ -> . % 76.16/76.38 188048[122:Spt:188046.0,187685.1] || -> node4(s32)*. % 76.16/76.38 188050[122:MRR:822.0,188048.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.38 188053[122:Res:53.1,188050.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.38 188055[123:Spt:188053.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 188057[123:Res:188055.0,61.1] always3(s32) || -> . % 76.16/76.38 188058[123:SSi:188057.0,78209.0,78213.0,165524.0,187684.0,188048.0] || -> . % 76.16/76.38 188059[123:Spt:188058.0,188053.0,188055.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.38 188060[123:Spt:188058.0,188053.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 188064[123:Res:188060.0,61.1] always3(s33) || -> . % 76.16/76.38 188065[123:SSi:188064.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.38 188066[121:Spt:188065.0,187683.0,187684.0] || until2p7(s32)*+ -> . % 76.16/76.38 188067[121:Spt:188065.0,187683.1] || -> node4(s31)*. % 76.16/76.38 188069[121:MRR:825.0,188067.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.38 188072[121:Res:53.1,188069.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.38 188074[122:Spt:188072.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 188076[122:Res:188074.0,61.1] always3(s31) || -> . % 76.16/76.38 188077[122:SSi:188076.0,78205.0,78208.0,165523.0,187682.0,188067.0] || -> . % 76.16/76.38 188078[122:Spt:188077.0,188072.0,188074.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.38 188079[122:Spt:188077.0,188072.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 188083[122:Res:188079.0,61.1] always3(s32) || -> . % 76.16/76.38 188084[122:SSi:188083.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.38 188085[120:Spt:188084.0,187681.0,187682.0] || until2p7(s31)*+ -> . % 76.16/76.38 188086[120:Spt:188084.0,187681.1] || -> node4(s30)*. % 76.16/76.38 188088[120:MRR:828.0,188086.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.38 188091[120:Res:53.1,188088.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.38 188096[121:Spt:188091.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 188098[121:Res:188096.0,61.1] always3(s30) || -> . % 76.16/76.38 188099[121:SSi:188098.0,78200.0,78204.0,165522.0,187680.0,188086.0] || -> . % 76.16/76.38 188100[121:Spt:188099.0,188091.0,188096.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.38 188101[121:Spt:188099.0,188091.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 188105[121:Res:188101.0,61.1] always3(s31) || -> . % 76.16/76.38 188106[121:SSi:188105.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.38 188107[119:Spt:188106.0,187679.0,187680.0] || until2p7(s30)*+ -> . % 76.16/76.38 188108[119:Spt:188106.0,187679.1] || -> node4(s29)*. % 76.16/76.38 188110[119:MRR:831.0,188108.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.38 188113[119:Res:53.1,188110.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.38 188115[120:Spt:188113.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 188117[120:Res:188115.0,61.1] always3(s29) || -> . % 76.16/76.38 188118[120:SSi:188117.0,78196.0,78199.0,165521.0,187678.0,188108.0] || -> . % 76.16/76.38 188119[120:Spt:188118.0,188113.0,188115.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.38 188120[120:Spt:188118.0,188113.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 188124[120:Res:188120.0,61.1] always3(s30) || -> . % 76.16/76.38 188125[120:SSi:188124.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.38 188126[118:Spt:188125.0,187677.0,187678.0] || until2p7(s29)*+ -> . % 76.16/76.38 188127[118:Spt:188125.0,187677.1] || -> node4(s28)*. % 76.16/76.38 188129[118:MRR:834.0,188127.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.38 188132[118:Res:53.1,188129.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.38 188134[119:Spt:188132.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 188136[119:Res:188134.0,61.1] always3(s28) || -> . % 76.16/76.38 188137[119:SSi:188136.0,78191.0,78195.0,165520.0,187676.0,188127.0] || -> . % 76.16/76.38 188138[119:Spt:188137.0,188132.0,188134.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.38 188139[119:Spt:188137.0,188132.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 188143[119:Res:188139.0,61.1] always3(s29) || -> . % 76.16/76.38 188144[119:SSi:188143.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.38 188145[117:Spt:188144.0,187675.0,187676.0] || until2p7(s28)*+ -> . % 76.16/76.38 188146[117:Spt:188144.0,187675.1] || -> node4(s27)*. % 76.16/76.38 188148[117:MRR:837.0,188146.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.38 188151[117:Res:53.1,188148.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.38 188153[118:Spt:188151.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 188155[118:Res:188153.0,61.1] always3(s27) || -> . % 76.16/76.38 188156[118:SSi:188155.0,78187.0,78190.0,165519.0,187674.0,188146.0] || -> . % 76.16/76.38 188157[118:Spt:188156.0,188151.0,188153.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.38 188158[118:Spt:188156.0,188151.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 188162[118:Res:188158.0,61.1] always3(s28) || -> . % 76.16/76.38 188163[118:SSi:188162.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.38 188164[116:Spt:188163.0,187673.0,187674.0] || until2p7(s27)*+ -> . % 76.16/76.38 188165[116:Spt:188163.0,187673.1] || -> node4(s26)*. % 76.16/76.38 188167[116:MRR:840.0,188165.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.38 188170[116:Res:53.1,188167.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.38 188175[117:Spt:188170.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 188177[117:Res:188175.0,61.1] always3(s26) || -> . % 76.16/76.38 188178[117:SSi:188177.0,78182.0,78186.0,165518.0,187672.0,188165.0] || -> . % 76.16/76.38 188179[117:Spt:188178.0,188170.0,188175.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.38 188180[117:Spt:188178.0,188170.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 188184[117:Res:188180.0,61.1] always3(s27) || -> . % 76.16/76.38 188185[117:SSi:188184.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.38 188186[115:Spt:188185.0,187671.0,187672.0] || until2p7(s26)*+ -> . % 76.16/76.38 188187[115:Spt:188185.0,187671.1] || -> node4(s25)*. % 76.16/76.38 188189[115:MRR:843.0,188187.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.38 188192[115:Res:53.1,188189.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.38 188194[116:Spt:188192.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 188196[116:Res:188194.0,61.1] always3(s25) || -> . % 76.16/76.38 188197[116:SSi:188196.0,78178.0,78181.0,165517.0,187670.0,188187.0] || -> . % 76.16/76.38 188198[116:Spt:188197.0,188192.0,188194.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.38 188199[116:Spt:188197.0,188192.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 188203[116:Res:188199.0,61.1] always3(s26) || -> . % 76.16/76.38 188204[116:SSi:188203.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.38 188205[114:Spt:188204.0,187669.0,187670.0] || until2p7(s25)*+ -> . % 76.16/76.38 188206[114:Spt:188204.0,187669.1] || -> node4(s24)*. % 76.16/76.38 188208[114:MRR:846.0,188206.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.38 188211[114:Res:53.1,188208.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.38 188213[115:Spt:188211.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 188215[115:Res:188213.0,61.1] always3(s24) || -> . % 76.16/76.38 188216[115:SSi:188215.0,78173.0,78177.0,165516.0,187668.0,188206.0] || -> . % 76.16/76.38 188217[115:Spt:188216.0,188211.0,188213.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.38 188218[115:Spt:188216.0,188211.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 188222[115:Res:188218.0,61.1] always3(s25) || -> . % 76.16/76.38 188223[115:SSi:188222.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.38 188224[113:Spt:188223.0,187667.0,187668.0] || until2p7(s24)*+ -> . % 76.16/76.38 188225[113:Spt:188223.0,187667.1] || -> node4(s23)*. % 76.16/76.38 188227[113:MRR:849.0,188225.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.38 188230[113:Res:53.1,188227.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.38 188232[114:Spt:188230.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 188234[114:Res:188232.0,61.1] always3(s23) || -> . % 76.16/76.38 188235[114:SSi:188234.0,78169.0,78172.0,165515.0,187666.0,188225.0] || -> . % 76.16/76.38 188236[114:Spt:188235.0,188230.0,188232.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.38 188237[114:Spt:188235.0,188230.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 188241[114:Res:188237.0,61.1] always3(s24) || -> . % 76.16/76.38 188242[114:SSi:188241.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.38 188243[112:Spt:188242.0,187665.0,187666.0] || until2p7(s23)*+ -> . % 76.16/76.38 188244[112:Spt:188242.0,187665.1] || -> node4(s22)*. % 76.16/76.38 188246[112:MRR:852.0,188244.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.38 188249[112:Res:53.1,188246.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.38 188254[113:Spt:188249.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 188256[113:Res:188254.0,61.1] always3(s22) || -> . % 76.16/76.38 188257[113:SSi:188256.0,78164.0,78168.0,165514.0,187664.0,188244.0] || -> . % 76.16/76.38 188258[113:Spt:188257.0,188249.0,188254.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.38 188259[113:Spt:188257.0,188249.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 188263[113:Res:188259.0,61.1] always3(s23) || -> . % 76.16/76.38 188264[113:SSi:188263.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.38 188265[111:Spt:188264.0,187663.0,187664.0] || until2p7(s22)*+ -> . % 76.16/76.38 188266[111:Spt:188264.0,187663.1] || -> node4(s21)*. % 76.16/76.38 188268[111:MRR:855.0,188266.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.38 188271[111:Res:53.1,188268.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.38 188273[112:Spt:188271.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 188275[112:Res:188273.0,61.1] always3(s21) || -> . % 76.16/76.38 188276[112:SSi:188275.0,78160.0,78163.0,165513.0,187662.0,188266.0] || -> . % 76.16/76.38 188277[112:Spt:188276.0,188271.0,188273.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.38 188278[112:Spt:188276.0,188271.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 188282[112:Res:188278.0,61.1] always3(s22) || -> . % 76.16/76.38 188283[112:SSi:188282.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.38 188284[110:Spt:188283.0,187661.0,187662.0] || until2p7(s21)*+ -> . % 76.16/76.38 188285[110:Spt:188283.0,187661.1] || -> node4(s20)*. % 76.16/76.38 188287[110:MRR:858.0,188285.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.38 188290[110:Res:53.1,188287.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.38 188292[111:Spt:188290.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 188294[111:Res:188292.0,61.1] always3(s20) || -> . % 76.16/76.38 188295[111:SSi:188294.0,78155.0,78159.0,165512.0,187660.0,188285.0] || -> . % 76.16/76.38 188296[111:Spt:188295.0,188290.0,188292.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.38 188297[111:Spt:188295.0,188290.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 188301[111:Res:188297.0,61.1] always3(s21) || -> . % 76.16/76.38 188302[111:SSi:188301.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.38 188303[109:Spt:188302.0,187659.0,187660.0] || until2p7(s20)*+ -> . % 76.16/76.38 188304[109:Spt:188302.0,187659.1] || -> node4(s19)*. % 76.16/76.38 188306[109:MRR:861.0,188304.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.38 188309[109:Res:53.1,188306.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.38 188311[110:Spt:188309.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 188313[110:Res:188311.0,61.1] always3(s19) || -> . % 76.16/76.38 188314[110:SSi:188313.0,78151.0,78154.0,165511.0,187658.0,188304.0] || -> . % 76.16/76.38 188315[110:Spt:188314.0,188309.0,188311.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.38 188316[110:Spt:188314.0,188309.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 188320[110:Res:188316.0,61.1] always3(s20) || -> . % 76.16/76.38 188321[110:SSi:188320.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.38 188322[108:Spt:188321.0,187657.0,187658.0] || until2p7(s19)*+ -> . % 76.16/76.38 188323[108:Spt:188321.0,187657.1] || -> node4(s18)*. % 76.16/76.38 188325[108:MRR:864.0,188323.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.38 188328[108:Res:53.1,188325.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.38 188333[109:Spt:188328.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 188335[109:Res:188333.0,61.1] always3(s18) || -> . % 76.16/76.38 188336[109:SSi:188335.0,78146.0,78150.0,165510.0,187656.0,188323.0] || -> . % 76.16/76.38 188337[109:Spt:188336.0,188328.0,188333.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.38 188338[109:Spt:188336.0,188328.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 188342[109:Res:188338.0,61.1] always3(s19) || -> . % 76.16/76.38 188343[109:SSi:188342.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.38 188344[107:Spt:188343.0,187655.0,187656.0] || until2p7(s18)*+ -> . % 76.16/76.38 188345[107:Spt:188343.0,187655.1] || -> node4(s17)*. % 76.16/76.38 188347[107:MRR:867.0,188345.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.38 188350[107:Res:53.1,188347.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.38 188352[108:Spt:188350.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 188354[108:Res:188352.0,61.1] always3(s17) || -> . % 76.16/76.38 188355[108:SSi:188354.0,78142.0,78145.0,165509.0,187654.0,188345.0] || -> . % 76.16/76.38 188356[108:Spt:188355.0,188350.0,188352.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.38 188357[108:Spt:188355.0,188350.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 188361[108:Res:188357.0,61.1] always3(s18) || -> . % 76.16/76.38 188362[108:SSi:188361.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.38 188363[106:Spt:188362.0,187653.0,187654.0] || until2p7(s17)*+ -> . % 76.16/76.38 188364[106:Spt:188362.0,187653.1] || -> node4(s16)*. % 76.16/76.38 188366[106:MRR:870.0,188364.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.38 188369[106:Res:53.1,188366.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.38 188371[107:Spt:188369.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 188373[107:Res:188371.0,61.1] always3(s16) || -> . % 76.16/76.38 188374[107:SSi:188373.0,78137.0,78141.0,165508.0,187652.0,188364.0] || -> . % 76.16/76.38 188375[107:Spt:188374.0,188369.0,188371.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.38 188376[107:Spt:188374.0,188369.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 188380[107:Res:188376.0,61.1] always3(s17) || -> . % 76.16/76.38 188381[107:SSi:188380.0,78142.0,78145.0,165509.0] || -> . % 76.16/76.38 188382[105:Spt:188381.0,187651.0,187652.0] || until2p7(s16)*+ -> . % 76.16/76.38 188383[105:Spt:188381.0,187651.1] || -> node4(s15)*. % 76.16/76.38 188385[105:MRR:873.0,188383.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.38 188388[105:Res:53.1,188385.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.38 188390[106:Spt:188388.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 188392[106:Res:188390.0,61.1] always3(s15) || -> . % 76.16/76.38 188393[106:SSi:188392.0,78133.0,78136.0,165507.0,187650.0,188383.0] || -> . % 76.16/76.38 188394[106:Spt:188393.0,188388.0,188390.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.38 188395[106:Spt:188393.0,188388.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 188399[106:Res:188395.0,61.1] always3(s16) || -> . % 76.16/76.38 188400[106:SSi:188399.0,78137.0,78141.0,165508.0] || -> . % 76.16/76.38 188401[104:Spt:188400.0,187649.0,187650.0] || until2p7(s15)*+ -> . % 76.16/76.38 188402[104:Spt:188400.0,187649.1] || -> node4(s14)*. % 76.16/76.38 188404[104:MRR:876.0,188402.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.38 188407[104:Res:53.1,188404.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.38 188412[105:Spt:188407.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 188414[105:Res:188412.0,61.1] always3(s14) || -> . % 76.16/76.38 188415[105:SSi:188414.0,78128.0,78132.0,165506.0,187648.0,188402.0] || -> . % 76.16/76.38 188416[105:Spt:188415.0,188407.0,188412.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.38 188417[105:Spt:188415.0,188407.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 188421[105:Res:188417.0,61.1] always3(s15) || -> . % 76.16/76.38 188422[105:SSi:188421.0,78133.0,78136.0,165507.0] || -> . % 76.16/76.38 188423[103:Spt:188422.0,187647.0,187648.0] || until2p7(s14)*+ -> . % 76.16/76.38 188424[103:Spt:188422.0,187647.1] || -> node4(s13)*. % 76.16/76.38 188426[103:MRR:879.0,188424.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.38 188429[103:Res:53.1,188426.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.38 188431[104:Spt:188429.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 188433[104:Res:188431.0,61.1] always3(s13) || -> . % 76.16/76.38 188434[104:SSi:188433.0,78124.0,78127.0,165505.0,187646.0,188424.0] || -> . % 76.16/76.38 188435[104:Spt:188434.0,188429.0,188431.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.38 188436[104:Spt:188434.0,188429.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 188440[104:Res:188436.0,61.1] always3(s14) || -> . % 76.16/76.38 188441[104:SSi:188440.0,78128.0,78132.0,165506.0] || -> . % 76.16/76.38 188442[102:Spt:188441.0,187645.0,187646.0] || until2p7(s13)*+ -> . % 76.16/76.38 188443[102:Spt:188441.0,187645.1] || -> node4(s12)*. % 76.16/76.38 188445[102:MRR:882.0,188443.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.38 188448[102:Res:53.1,188445.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.38 188450[103:Spt:188448.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.38 188452[103:Res:188450.0,61.1] always3(s12) || -> . % 76.16/76.38 188453[103:SSi:188452.0,78119.0,78123.0,165504.0,187644.0,188443.0] || -> . % 76.16/76.38 188454[103:Spt:188453.0,188448.0,188450.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.38 188455[103:Spt:188453.0,188448.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 188459[103:Res:188455.0,61.1] always3(s13) || -> . % 76.16/76.38 188460[103:SSi:188459.0,78124.0,78127.0,165505.0] || -> . % 76.16/76.38 188461[101:Spt:188460.0,187643.0,187644.0] || until2p7(s12)*+ -> . % 76.16/76.38 188462[101:Spt:188460.0,187643.1] || -> node4(s11)*. % 76.16/76.38 188464[101:MRR:885.0,188462.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.38 188467[101:Res:53.1,188464.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.38 188469[102:Spt:188467.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.38 188471[102:Res:188469.0,61.1] always3(s11) || -> . % 76.16/76.38 188472[102:SSi:188471.0,78115.0,78118.0,165503.0,187642.0,188462.0] || -> . % 76.16/76.38 188473[102:Spt:188472.0,188467.0,188469.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.38 188474[102:Spt:188472.0,188467.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.38 188478[102:Res:188474.0,61.1] always3(s12) || -> . % 76.16/76.38 188479[102:SSi:188478.0,78119.0,78123.0,165504.0] || -> . % 76.16/76.38 188480[100:Spt:188479.0,187641.0,187642.0] || until2p7(s11)*+ -> . % 76.16/76.38 188481[100:Spt:188479.0,187641.1] || -> node4(s10)*. % 76.16/76.38 188483[100:MRR:888.0,188481.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.38 188486[100:Res:53.1,188483.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.38 188491[101:Spt:188486.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.38 188493[101:Res:188491.0,61.1] always3(s10) || -> . % 76.16/76.38 188494[101:SSi:188493.0,78110.0,78114.0,165502.0,187640.0,188481.0] || -> . % 76.16/76.38 188495[101:Spt:188494.0,188486.0,188491.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.38 188496[101:Spt:188494.0,188486.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.38 188500[101:Res:188496.0,61.1] always3(s11) || -> . % 76.16/76.38 188501[101:SSi:188500.0,78115.0,78118.0,165503.0] || -> . % 76.16/76.38 188502[99:Spt:188501.0,187639.0,187640.0] || until2p7(s10)*+ -> . % 76.16/76.38 188503[99:Spt:188501.0,187639.1] || -> node4(s9)*. % 76.16/76.38 188505[99:MRR:891.0,188503.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.38 188508[99:Res:53.1,188505.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.38 188510[100:Spt:188508.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.38 188512[100:Res:188510.0,61.1] always3(s9) || -> . % 76.16/76.38 188513[100:SSi:188512.0,78106.0,78109.0,165501.0,187638.0,188503.0] || -> . % 76.16/76.38 188514[100:Spt:188513.0,188508.0,188510.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.38 188515[100:Spt:188513.0,188508.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.38 188519[100:Res:188515.0,61.1] always3(s10) || -> . % 76.16/76.38 188520[100:SSi:188519.0,78110.0,78114.0,165502.0] || -> . % 76.16/76.38 188521[98:Spt:188520.0,187637.0,187638.0] || until2p7(s9)*+ -> . % 76.16/76.38 188522[98:Spt:188520.0,187637.1] || -> node4(s8)*. % 76.16/76.38 188524[98:MRR:894.0,188522.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.38 188527[98:Res:53.1,188524.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.38 188529[98:MRR:188527.0,187627.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.38 188531[98:Res:188529.0,61.1] always3(s9) || -> . % 76.16/76.38 188532[98:SSi:188531.0,78106.0,78109.0,165501.0] || -> . % 76.16/76.38 188533[96:Spt:188532.0,187474.0,187477.0] || trans(s49,s8)*+ -> . % 76.16/76.38 188534[96:Spt:188532.0,187474.1,187474.2,187474.3] || -> trans(s49,s7) trans(s49,s6) node2(s49,s5)*. % 76.16/76.38 188536[96:MRR:187476.1,188533.0] xuntil6(s49) || -> trans(s49,s7) trans(s49,s6)* until2p7(s5). % 76.16/76.38 188537[97:Spt:188534.0] || -> trans(s49,s7)*. % 76.16/76.38 188538[97:Res:188537.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s7)*. % 76.16/76.38 188540[97:Res:188537.0,60.0] || -> node2(s49,s7)*. % 76.16/76.38 188541[97:SSi:188538.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s7)*. % 76.16/76.38 188542[97:Res:188540.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)*. % 76.16/76.38 188683[97:SoR:188542.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)*. % 76.16/76.38 188685[97:SoR:188683.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)* xuntil6(s49). % 76.16/76.38 188686[97:SSi:188685.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s7,c_busy)* xuntil6(s49). % 76.16/76.38 188687[98:Spt:188686.1] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.38 188689[98:Res:188687.0,61.1] always3(s7) || -> . % 76.16/76.38 188690[98:SSi:188689.0,78097.0,78100.0,165499.0] || -> . % 76.16/76.38 188691[98:Spt:188690.0,188686.1,188687.0] || m_main_v_state(s7,c_busy)*+ -> . % 76.16/76.38 188692[98:Spt:188690.0,188686.0,188686.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.38 188696[98:MRR:188683.2,188691.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.38 188697[98:Res:53.1,188692.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.38 188699[98:MRR:188697.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.38 188700[98:MRR:188541.0,188699.0] || -> until2p7(s7)*. % 76.16/76.38 188701[98:MRR:203.0,188700.0] || -> until2p7(s8)* node4(s7). % 76.16/76.38 188702[99:Spt:188701.0] || -> until2p7(s8)*. % 76.16/76.38 188703[99:MRR:204.0,188702.0] || -> until2p7(s9)* node4(s8). % 76.16/76.38 188704[100:Spt:188703.0] || -> until2p7(s9)*. % 76.16/76.38 188705[100:MRR:205.0,188704.0] || -> until2p7(s10)* node4(s9). % 76.16/76.38 188706[101:Spt:188705.0] || -> until2p7(s10)*. % 76.16/76.38 188707[101:MRR:206.0,188706.0] || -> until2p7(s11)* node4(s10). % 76.16/76.38 188708[102:Spt:188707.0] || -> until2p7(s11)*. % 76.16/76.38 188709[102:MRR:207.0,188708.0] || -> until2p7(s12)* node4(s11). % 76.16/76.38 188710[103:Spt:188709.0] || -> until2p7(s12)*. % 76.16/76.38 188711[103:MRR:208.0,188710.0] || -> until2p7(s13)* node4(s12). % 76.16/76.38 188712[104:Spt:188711.0] || -> until2p7(s13)*. % 76.16/76.38 188713[104:MRR:209.0,188712.0] || -> until2p7(s14)* node4(s13). % 76.16/76.38 188714[105:Spt:188713.0] || -> until2p7(s14)*. % 76.16/76.38 188715[105:MRR:210.0,188714.0] || -> until2p7(s15)* node4(s14). % 76.16/76.38 188716[106:Spt:188715.0] || -> until2p7(s15)*. % 76.16/76.38 188717[106:MRR:211.0,188716.0] || -> until2p7(s16)* node4(s15). % 76.16/76.38 188718[107:Spt:188717.0] || -> until2p7(s16)*. % 76.16/76.38 188719[107:MRR:212.0,188718.0] || -> until2p7(s17)* node4(s16). % 76.16/76.38 188720[108:Spt:188719.0] || -> until2p7(s17)*. % 76.16/76.38 188721[108:MRR:213.0,188720.0] || -> until2p7(s18)* node4(s17). % 76.16/76.38 188722[109:Spt:188721.0] || -> until2p7(s18)*. % 76.16/76.38 188723[109:MRR:214.0,188722.0] || -> until2p7(s19)* node4(s18). % 76.16/76.38 188724[110:Spt:188723.0] || -> until2p7(s19)*. % 76.16/76.38 188725[110:MRR:215.0,188724.0] || -> until2p7(s20)* node4(s19). % 76.16/76.38 188726[111:Spt:188725.0] || -> until2p7(s20)*. % 76.16/76.38 188727[111:MRR:216.0,188726.0] || -> until2p7(s21)* node4(s20). % 76.16/76.38 188728[112:Spt:188727.0] || -> until2p7(s21)*. % 76.16/76.38 188729[112:MRR:217.0,188728.0] || -> until2p7(s22)* node4(s21). % 76.16/76.38 188730[113:Spt:188729.0] || -> until2p7(s22)*. % 76.16/76.38 188731[113:MRR:218.0,188730.0] || -> until2p7(s23)* node4(s22). % 76.16/76.38 188732[114:Spt:188731.0] || -> until2p7(s23)*. % 76.16/76.38 188733[114:MRR:219.0,188732.0] || -> until2p7(s24)* node4(s23). % 76.16/76.38 188734[115:Spt:188733.0] || -> until2p7(s24)*. % 76.16/76.38 188735[115:MRR:220.0,188734.0] || -> until2p7(s25)* node4(s24). % 76.16/76.38 188736[116:Spt:188735.0] || -> until2p7(s25)*. % 76.16/76.38 188737[116:MRR:221.0,188736.0] || -> until2p7(s26)* node4(s25). % 76.16/76.38 188738[117:Spt:188737.0] || -> until2p7(s26)*. % 76.16/76.38 188739[117:MRR:222.0,188738.0] || -> until2p7(s27)* node4(s26). % 76.16/76.38 188740[118:Spt:188739.0] || -> until2p7(s27)*. % 76.16/76.38 188741[118:MRR:223.0,188740.0] || -> until2p7(s28)* node4(s27). % 76.16/76.38 188742[119:Spt:188741.0] || -> until2p7(s28)*. % 76.16/76.38 188743[119:MRR:224.0,188742.0] || -> until2p7(s29)* node4(s28). % 76.16/76.38 188744[120:Spt:188743.0] || -> until2p7(s29)*. % 76.16/76.38 188745[120:MRR:225.0,188744.0] || -> until2p7(s30)* node4(s29). % 76.16/76.38 188746[121:Spt:188745.0] || -> until2p7(s30)*. % 76.16/76.38 188747[121:MRR:226.0,188746.0] || -> until2p7(s31)* node4(s30). % 76.16/76.38 188748[122:Spt:188747.0] || -> until2p7(s31)*. % 76.16/76.38 188749[122:MRR:227.0,188748.0] || -> until2p7(s32)* node4(s31). % 76.16/76.38 188750[123:Spt:188749.0] || -> until2p7(s32)*. % 76.16/76.38 188751[123:MRR:228.0,188750.0] || -> until2p7(s33)* node4(s32). % 76.16/76.38 188752[124:Spt:188751.0] || -> until2p7(s33)*. % 76.16/76.38 188753[124:MRR:229.0,188752.0] || -> until2p7(s34)* node4(s33). % 76.16/76.38 188754[125:Spt:188753.0] || -> until2p7(s34)*. % 76.16/76.38 188755[125:MRR:230.0,188754.0] || -> until2p7(s35)* node4(s34). % 76.16/76.38 188756[126:Spt:188755.0] || -> until2p7(s35)*. % 76.16/76.38 188757[126:MRR:231.0,188756.0] || -> until2p7(s36)* node4(s35). % 76.16/76.38 188758[127:Spt:188757.0] || -> until2p7(s36)*. % 76.16/76.38 188759[127:MRR:232.0,188758.0] || -> until2p7(s37)* node4(s36). % 76.16/76.38 188760[128:Spt:188759.0] || -> until2p7(s37)*. % 76.16/76.38 188761[128:MRR:235.0,188760.0] || -> until2p7(s38)* node4(s37). % 76.16/76.38 188762[129:Spt:188761.0] || -> until2p7(s38)*. % 76.16/76.38 188763[129:MRR:236.0,188762.0] || -> until2p7(s39)* node4(s38). % 76.16/76.38 188764[130:Spt:188763.0] || -> until2p7(s39)*. % 76.16/76.38 188765[130:MRR:237.0,188764.0] || -> until2p7(s40)* node4(s39). % 76.16/76.38 188766[131:Spt:188765.0] || -> until2p7(s40)*. % 76.16/76.38 188767[131:MRR:238.0,188766.0] || -> until2p7(s41)* node4(s40). % 76.16/76.38 188768[132:Spt:188767.0] || -> until2p7(s41)*. % 76.16/76.38 188769[132:MRR:239.0,188768.0] || -> until2p7(s42)* node4(s41). % 76.16/76.38 188770[133:Spt:188769.0] || -> until2p7(s42)*. % 76.16/76.38 188771[133:MRR:240.0,188770.0] || -> until2p7(s43)* node4(s42). % 76.16/76.38 188772[134:Spt:188771.0] || -> until2p7(s43)*. % 76.16/76.38 188773[134:MRR:241.0,188772.0] || -> until2p7(s44)* node4(s43). % 76.16/76.38 188774[135:Spt:188773.0] || -> until2p7(s44)*. % 76.16/76.38 188775[135:MRR:539.0,188774.0] || -> until2p7(s45)* node4(s44). % 76.16/76.38 188776[136:Spt:188775.0] || -> until2p7(s45)*. % 76.16/76.38 188777[136:MRR:544.0,188776.0] || -> until2p7(s46)* node4(s45). % 76.16/76.38 188778[137:Spt:188777.0] || -> until2p7(s46)*. % 76.16/76.38 188779[137:MRR:549.0,188778.0] || -> until2p7(s47)* node4(s46). % 76.16/76.38 188780[138:Spt:188779.0] || -> until2p7(s47)*. % 76.16/76.38 188781[138:MRR:554.0,188780.0] || -> until2p7(s48)* node4(s47). % 76.16/76.38 188782[139:Spt:188781.0] || -> until2p7(s48)*. % 76.16/76.38 188783[139:MRR:559.0,188782.0] || -> until2p7(s49)* node4(s48). % 76.16/76.38 188784[140:Spt:188783.0] || -> until2p7(s49)*. % 76.16/76.38 188785[140:MRR:194.0,188784.0] || -> node4(s49)*. % 76.16/76.38 188786[140:MRR:188696.0,188785.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.38 188787[140:Res:53.1,188786.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.38 188789[140:MRR:188787.0,78381.0] || -> . % 76.16/76.38 188790[140:Spt:188789.0,188783.0,188784.0] || until2p7(s49)*+ -> . % 76.16/76.38 188791[140:Spt:188789.0,188783.1] || -> node4(s48)*. % 76.16/76.38 188792[140:MRR:78384.0,188791.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.38 188795[140:Res:53.1,188792.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 188798[140:Res:188795.0,61.1] always3(s48) || -> . % 76.16/76.38 188799[140:SSi:188798.0,78281.0,78387.0,165540.0,188782.0,188791.0] || -> . % 76.16/76.38 188800[139:Spt:188799.0,188781.0,188782.0] || until2p7(s48)*+ -> . % 76.16/76.38 188801[139:Spt:188799.0,188781.1] || -> node4(s47)*. % 76.16/76.38 188803[139:MRR:777.0,188801.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.38 188818[139:Res:53.1,188803.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.38 188823[140:Spt:188818.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 188825[140:Res:188823.0,61.1] always3(s47) || -> . % 76.16/76.38 188826[140:SSi:188825.0,78277.0,78280.0,165539.0,188780.0,188801.0] || -> . % 76.16/76.38 188827[140:Spt:188826.0,188818.0,188823.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.38 188828[140:Spt:188826.0,188818.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 188832[140:Res:188828.0,61.1] always3(s48) || -> . % 76.16/76.38 188833[140:SSi:188832.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.38 188834[138:Spt:188833.0,188779.0,188780.0] || until2p7(s47)*+ -> . % 76.16/76.38 188835[138:Spt:188833.0,188779.1] || -> node4(s46)*. % 76.16/76.38 188837[138:MRR:780.0,188835.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.38 188844[138:Res:53.1,188837.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.38 188846[139:Spt:188844.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 188848[139:Res:188846.0,61.1] always3(s46) || -> . % 76.16/76.38 188849[139:SSi:188848.0,78272.0,78276.0,165538.0,188778.0,188835.0] || -> . % 76.16/76.38 188850[139:Spt:188849.0,188844.0,188846.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.38 188851[139:Spt:188849.0,188844.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 188855[139:Res:188851.0,61.1] always3(s47) || -> . % 76.16/76.38 188856[139:SSi:188855.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.38 188857[137:Spt:188856.0,188777.0,188778.0] || until2p7(s46)*+ -> . % 76.16/76.38 188858[137:Spt:188856.0,188777.1] || -> node4(s45)*. % 76.16/76.38 188860[137:MRR:783.0,188858.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.38 188863[137:Res:53.1,188860.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.38 188868[138:Spt:188863.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 188870[138:Res:188868.0,61.1] always3(s45) || -> . % 76.16/76.38 188871[138:SSi:188870.0,78268.0,78271.0,165537.0,188776.0,188858.0] || -> . % 76.16/76.38 188872[138:Spt:188871.0,188863.0,188868.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.38 188873[138:Spt:188871.0,188863.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 188877[138:Res:188873.0,61.1] always3(s46) || -> . % 76.16/76.38 188878[138:SSi:188877.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.38 188879[136:Spt:188878.0,188775.0,188776.0] || until2p7(s45)*+ -> . % 76.16/76.38 188880[136:Spt:188878.0,188775.1] || -> node4(s44)*. % 76.16/76.38 188882[136:MRR:786.0,188880.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.38 188885[136:Res:53.1,188882.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.38 188887[137:Spt:188885.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 188889[137:Res:188887.0,61.1] always3(s44) || -> . % 76.16/76.38 188890[137:SSi:188889.0,78263.0,78267.0,165536.0,188774.0,188880.0] || -> . % 76.16/76.38 188891[137:Spt:188890.0,188885.0,188887.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.38 188892[137:Spt:188890.0,188885.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 188896[137:Res:188892.0,61.1] always3(s45) || -> . % 76.16/76.38 188897[137:SSi:188896.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.38 188898[135:Spt:188897.0,188773.0,188774.0] || until2p7(s44)*+ -> . % 76.16/76.38 188899[135:Spt:188897.0,188773.1] || -> node4(s43)*. % 76.16/76.38 188901[135:MRR:789.0,188899.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.38 188904[135:Res:53.1,188901.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.38 188906[136:Spt:188904.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 188908[136:Res:188906.0,61.1] always3(s43) || -> . % 76.16/76.38 188909[136:SSi:188908.0,78259.0,78262.0,165535.0,188772.0,188899.0] || -> . % 76.16/76.38 188910[136:Spt:188909.0,188904.0,188906.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.38 188911[136:Spt:188909.0,188904.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 188915[136:Res:188911.0,61.1] always3(s44) || -> . % 76.16/76.38 188916[136:SSi:188915.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.38 188917[134:Spt:188916.0,188771.0,188772.0] || until2p7(s43)*+ -> . % 76.16/76.38 188918[134:Spt:188916.0,188771.1] || -> node4(s42)*. % 76.16/76.38 188920[134:MRR:792.0,188918.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.38 188923[134:Res:53.1,188920.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.38 188925[135:Spt:188923.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 188927[135:Res:188925.0,61.1] always3(s42) || -> . % 76.16/76.38 188928[135:SSi:188927.0,78254.0,78258.0,165534.0,188770.0,188918.0] || -> . % 76.16/76.38 188929[135:Spt:188928.0,188923.0,188925.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.38 188930[135:Spt:188928.0,188923.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 188934[135:Res:188930.0,61.1] always3(s43) || -> . % 76.16/76.38 188935[135:SSi:188934.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.38 188936[133:Spt:188935.0,188769.0,188770.0] || until2p7(s42)*+ -> . % 76.16/76.38 188937[133:Spt:188935.0,188769.1] || -> node4(s41)*. % 76.16/76.38 188939[133:MRR:795.0,188937.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.38 188942[133:Res:53.1,188939.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.38 188947[134:Spt:188942.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 188949[134:Res:188947.0,61.1] always3(s41) || -> . % 76.16/76.38 188950[134:SSi:188949.0,78250.0,78253.0,165533.0,188768.0,188937.0] || -> . % 76.16/76.38 188951[134:Spt:188950.0,188942.0,188947.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.38 188952[134:Spt:188950.0,188942.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 188956[134:Res:188952.0,61.1] always3(s42) || -> . % 76.16/76.38 188957[134:SSi:188956.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.38 188958[132:Spt:188957.0,188767.0,188768.0] || until2p7(s41)*+ -> . % 76.16/76.38 188959[132:Spt:188957.0,188767.1] || -> node4(s40)*. % 76.16/76.38 188961[132:MRR:798.0,188959.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.38 188964[132:Res:53.1,188961.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.38 188966[133:Spt:188964.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 188968[133:Res:188966.0,61.1] always3(s40) || -> . % 76.16/76.38 188969[133:SSi:188968.0,78245.0,78249.0,165532.0,188766.0,188959.0] || -> . % 76.16/76.38 188970[133:Spt:188969.0,188964.0,188966.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.38 188971[133:Spt:188969.0,188964.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.38 188975[133:Res:188971.0,61.1] always3(s41) || -> . % 76.16/76.38 188976[133:SSi:188975.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.38 188977[131:Spt:188976.0,188765.0,188766.0] || until2p7(s40)*+ -> . % 76.16/76.38 188978[131:Spt:188976.0,188765.1] || -> node4(s39)*. % 76.16/76.38 188980[131:MRR:801.0,188978.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.38 188983[131:Res:53.1,188980.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.38 188985[132:Spt:188983.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 188987[132:Res:188985.0,61.1] always3(s39) || -> . % 76.16/76.38 188988[132:SSi:188987.0,78241.0,78244.0,165531.0,188764.0,188978.0] || -> . % 76.16/76.38 188989[132:Spt:188988.0,188983.0,188985.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.38 188990[132:Spt:188988.0,188983.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.38 188994[132:Res:188990.0,61.1] always3(s40) || -> . % 76.16/76.38 188995[132:SSi:188994.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.38 188996[130:Spt:188995.0,188763.0,188764.0] || until2p7(s39)*+ -> . % 76.16/76.38 188997[130:Spt:188995.0,188763.1] || -> node4(s38)*. % 76.16/76.38 188999[130:MRR:804.0,188997.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.38 189002[130:Res:53.1,188999.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.38 189004[131:Spt:189002.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 189006[131:Res:189004.0,61.1] always3(s38) || -> . % 76.16/76.38 189007[131:SSi:189006.0,78236.0,78240.0,165530.0,188762.0,188997.0] || -> . % 76.16/76.38 189008[131:Spt:189007.0,189002.0,189004.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.38 189009[131:Spt:189007.0,189002.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.38 189013[131:Res:189009.0,61.1] always3(s39) || -> . % 76.16/76.38 189014[131:SSi:189013.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.38 189015[129:Spt:189014.0,188761.0,188762.0] || until2p7(s38)*+ -> . % 76.16/76.38 189016[129:Spt:189014.0,188761.1] || -> node4(s37)*. % 76.16/76.38 189018[129:MRR:807.0,189016.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.38 189021[129:Res:53.1,189018.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.38 189026[130:Spt:189021.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 189028[130:Res:189026.0,61.1] always3(s37) || -> . % 76.16/76.38 189029[130:SSi:189028.0,78232.0,78235.0,165529.0,188760.0,189016.0] || -> . % 76.16/76.38 189030[130:Spt:189029.0,189021.0,189026.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.38 189031[130:Spt:189029.0,189021.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.38 189035[130:Res:189031.0,61.1] always3(s38) || -> . % 76.16/76.38 189036[130:SSi:189035.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.38 189037[128:Spt:189036.0,188759.0,188760.0] || until2p7(s37)*+ -> . % 76.16/76.38 189038[128:Spt:189036.0,188759.1] || -> node4(s36)*. % 76.16/76.38 189040[128:MRR:810.0,189038.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.38 189043[128:Res:53.1,189040.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.38 189045[129:Spt:189043.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 189047[129:Res:189045.0,61.1] always3(s36) || -> . % 76.16/76.38 189048[129:SSi:189047.0,78227.0,78231.0,165528.0,188758.0,189038.0] || -> . % 76.16/76.38 189049[129:Spt:189048.0,189043.0,189045.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.38 189050[129:Spt:189048.0,189043.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.38 189054[129:Res:189050.0,61.1] always3(s37) || -> . % 76.16/76.38 189055[129:SSi:189054.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.38 189056[127:Spt:189055.0,188757.0,188758.0] || until2p7(s36)*+ -> . % 76.16/76.38 189057[127:Spt:189055.0,188757.1] || -> node4(s35)*. % 76.16/76.38 189059[127:MRR:813.0,189057.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.38 189062[127:Res:53.1,189059.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.38 189064[128:Spt:189062.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 189066[128:Res:189064.0,61.1] always3(s35) || -> . % 76.16/76.38 189067[128:SSi:189066.0,78223.0,78226.0,165527.0,188756.0,189057.0] || -> . % 76.16/76.38 189068[128:Spt:189067.0,189062.0,189064.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.38 189069[128:Spt:189067.0,189062.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.38 189073[128:Res:189069.0,61.1] always3(s36) || -> . % 76.16/76.38 189074[128:SSi:189073.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.38 189075[126:Spt:189074.0,188755.0,188756.0] || until2p7(s35)*+ -> . % 76.16/76.38 189076[126:Spt:189074.0,188755.1] || -> node4(s34)*. % 76.16/76.38 189078[126:MRR:816.0,189076.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.38 189081[126:Res:53.1,189078.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.38 189083[127:Spt:189081.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 189085[127:Res:189083.0,61.1] always3(s34) || -> . % 76.16/76.38 189086[127:SSi:189085.0,78218.0,78222.0,165526.0,188754.0,189076.0] || -> . % 76.16/76.38 189087[127:Spt:189086.0,189081.0,189083.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.38 189088[127:Spt:189086.0,189081.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.38 189092[127:Res:189088.0,61.1] always3(s35) || -> . % 76.16/76.38 189093[127:SSi:189092.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.38 189094[125:Spt:189093.0,188753.0,188754.0] || until2p7(s34)*+ -> . % 76.16/76.38 189095[125:Spt:189093.0,188753.1] || -> node4(s33)*. % 76.16/76.38 189097[125:MRR:819.0,189095.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.38 189100[125:Res:53.1,189097.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.38 189105[126:Spt:189100.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 189107[126:Res:189105.0,61.1] always3(s33) || -> . % 76.16/76.38 189108[126:SSi:189107.0,78214.0,78217.0,165525.0,188752.0,189095.0] || -> . % 76.16/76.38 189109[126:Spt:189108.0,189100.0,189105.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.38 189110[126:Spt:189108.0,189100.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.38 189114[126:Res:189110.0,61.1] always3(s34) || -> . % 76.16/76.38 189115[126:SSi:189114.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.38 189116[124:Spt:189115.0,188751.0,188752.0] || until2p7(s33)*+ -> . % 76.16/76.38 189117[124:Spt:189115.0,188751.1] || -> node4(s32)*. % 76.16/76.38 189119[124:MRR:822.0,189117.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.38 189122[124:Res:53.1,189119.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.38 189124[125:Spt:189122.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 189126[125:Res:189124.0,61.1] always3(s32) || -> . % 76.16/76.38 189127[125:SSi:189126.0,78209.0,78213.0,165524.0,188750.0,189117.0] || -> . % 76.16/76.38 189128[125:Spt:189127.0,189122.0,189124.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.38 189129[125:Spt:189127.0,189122.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.38 189133[125:Res:189129.0,61.1] always3(s33) || -> . % 76.16/76.38 189134[125:SSi:189133.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.38 189135[123:Spt:189134.0,188749.0,188750.0] || until2p7(s32)*+ -> . % 76.16/76.38 189136[123:Spt:189134.0,188749.1] || -> node4(s31)*. % 76.16/76.38 189138[123:MRR:825.0,189136.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.38 189141[123:Res:53.1,189138.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.38 189143[124:Spt:189141.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 189145[124:Res:189143.0,61.1] always3(s31) || -> . % 76.16/76.38 189146[124:SSi:189145.0,78205.0,78208.0,165523.0,188748.0,189136.0] || -> . % 76.16/76.38 189147[124:Spt:189146.0,189141.0,189143.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.38 189148[124:Spt:189146.0,189141.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.38 189152[124:Res:189148.0,61.1] always3(s32) || -> . % 76.16/76.38 189153[124:SSi:189152.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.38 189154[122:Spt:189153.0,188747.0,188748.0] || until2p7(s31)*+ -> . % 76.16/76.38 189155[122:Spt:189153.0,188747.1] || -> node4(s30)*. % 76.16/76.38 189157[122:MRR:828.0,189155.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.38 189160[122:Res:53.1,189157.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.38 189162[123:Spt:189160.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 189164[123:Res:189162.0,61.1] always3(s30) || -> . % 76.16/76.38 189165[123:SSi:189164.0,78200.0,78204.0,165522.0,188746.0,189155.0] || -> . % 76.16/76.38 189166[123:Spt:189165.0,189160.0,189162.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.38 189167[123:Spt:189165.0,189160.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.38 189171[123:Res:189167.0,61.1] always3(s31) || -> . % 76.16/76.38 189172[123:SSi:189171.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.38 189173[121:Spt:189172.0,188745.0,188746.0] || until2p7(s30)*+ -> . % 76.16/76.38 189174[121:Spt:189172.0,188745.1] || -> node4(s29)*. % 76.16/76.38 189176[121:MRR:831.0,189174.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.38 189179[121:Res:53.1,189176.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.38 189184[122:Spt:189179.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 189186[122:Res:189184.0,61.1] always3(s29) || -> . % 76.16/76.38 189187[122:SSi:189186.0,78196.0,78199.0,165521.0,188744.0,189174.0] || -> . % 76.16/76.38 189188[122:Spt:189187.0,189179.0,189184.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.38 189189[122:Spt:189187.0,189179.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.38 189193[122:Res:189189.0,61.1] always3(s30) || -> . % 76.16/76.38 189194[122:SSi:189193.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.38 189195[120:Spt:189194.0,188743.0,188744.0] || until2p7(s29)*+ -> . % 76.16/76.38 189196[120:Spt:189194.0,188743.1] || -> node4(s28)*. % 76.16/76.38 189198[120:MRR:834.0,189196.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.38 189201[120:Res:53.1,189198.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.38 189203[121:Spt:189201.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 189205[121:Res:189203.0,61.1] always3(s28) || -> . % 76.16/76.38 189206[121:SSi:189205.0,78191.0,78195.0,165520.0,188742.0,189196.0] || -> . % 76.16/76.38 189207[121:Spt:189206.0,189201.0,189203.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.38 189208[121:Spt:189206.0,189201.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.38 189212[121:Res:189208.0,61.1] always3(s29) || -> . % 76.16/76.38 189213[121:SSi:189212.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.38 189214[119:Spt:189213.0,188741.0,188742.0] || until2p7(s28)*+ -> . % 76.16/76.38 189215[119:Spt:189213.0,188741.1] || -> node4(s27)*. % 76.16/76.38 189217[119:MRR:837.0,189215.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.38 189220[119:Res:53.1,189217.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.38 189222[120:Spt:189220.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 189224[120:Res:189222.0,61.1] always3(s27) || -> . % 76.16/76.38 189225[120:SSi:189224.0,78187.0,78190.0,165519.0,188740.0,189215.0] || -> . % 76.16/76.38 189226[120:Spt:189225.0,189220.0,189222.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.38 189227[120:Spt:189225.0,189220.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.38 189231[120:Res:189227.0,61.1] always3(s28) || -> . % 76.16/76.38 189232[120:SSi:189231.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.38 189233[118:Spt:189232.0,188739.0,188740.0] || until2p7(s27)*+ -> . % 76.16/76.38 189234[118:Spt:189232.0,188739.1] || -> node4(s26)*. % 76.16/76.38 189236[118:MRR:840.0,189234.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.38 189239[118:Res:53.1,189236.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.38 189241[119:Spt:189239.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 189243[119:Res:189241.0,61.1] always3(s26) || -> . % 76.16/76.38 189244[119:SSi:189243.0,78182.0,78186.0,165518.0,188738.0,189234.0] || -> . % 76.16/76.38 189245[119:Spt:189244.0,189239.0,189241.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.38 189246[119:Spt:189244.0,189239.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.38 189250[119:Res:189246.0,61.1] always3(s27) || -> . % 76.16/76.38 189251[119:SSi:189250.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.38 189252[117:Spt:189251.0,188737.0,188738.0] || until2p7(s26)*+ -> . % 76.16/76.38 189253[117:Spt:189251.0,188737.1] || -> node4(s25)*. % 76.16/76.38 189255[117:MRR:843.0,189253.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.38 189258[117:Res:53.1,189255.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.38 189263[118:Spt:189258.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 189265[118:Res:189263.0,61.1] always3(s25) || -> . % 76.16/76.38 189266[118:SSi:189265.0,78178.0,78181.0,165517.0,188736.0,189253.0] || -> . % 76.16/76.38 189267[118:Spt:189266.0,189258.0,189263.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.38 189268[118:Spt:189266.0,189258.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.38 189272[118:Res:189268.0,61.1] always3(s26) || -> . % 76.16/76.38 189273[118:SSi:189272.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.38 189274[116:Spt:189273.0,188735.0,188736.0] || until2p7(s25)*+ -> . % 76.16/76.38 189275[116:Spt:189273.0,188735.1] || -> node4(s24)*. % 76.16/76.38 189277[116:MRR:846.0,189275.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.38 189280[116:Res:53.1,189277.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.38 189282[117:Spt:189280.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 189284[117:Res:189282.0,61.1] always3(s24) || -> . % 76.16/76.38 189285[117:SSi:189284.0,78173.0,78177.0,165516.0,188734.0,189275.0] || -> . % 76.16/76.38 189286[117:Spt:189285.0,189280.0,189282.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.38 189287[117:Spt:189285.0,189280.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.38 189291[117:Res:189287.0,61.1] always3(s25) || -> . % 76.16/76.38 189292[117:SSi:189291.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.38 189293[115:Spt:189292.0,188733.0,188734.0] || until2p7(s24)*+ -> . % 76.16/76.38 189294[115:Spt:189292.0,188733.1] || -> node4(s23)*. % 76.16/76.38 189296[115:MRR:849.0,189294.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.38 189299[115:Res:53.1,189296.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.38 189301[116:Spt:189299.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 189303[116:Res:189301.0,61.1] always3(s23) || -> . % 76.16/76.38 189304[116:SSi:189303.0,78169.0,78172.0,165515.0,188732.0,189294.0] || -> . % 76.16/76.38 189305[116:Spt:189304.0,189299.0,189301.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.38 189306[116:Spt:189304.0,189299.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.38 189310[116:Res:189306.0,61.1] always3(s24) || -> . % 76.16/76.38 189311[116:SSi:189310.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.38 189312[114:Spt:189311.0,188731.0,188732.0] || until2p7(s23)*+ -> . % 76.16/76.38 189313[114:Spt:189311.0,188731.1] || -> node4(s22)*. % 76.16/76.38 189315[114:MRR:852.0,189313.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.38 189318[114:Res:53.1,189315.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.38 189320[115:Spt:189318.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 189322[115:Res:189320.0,61.1] always3(s22) || -> . % 76.16/76.38 189323[115:SSi:189322.0,78164.0,78168.0,165514.0,188730.0,189313.0] || -> . % 76.16/76.38 189324[115:Spt:189323.0,189318.0,189320.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.38 189325[115:Spt:189323.0,189318.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.38 189329[115:Res:189325.0,61.1] always3(s23) || -> . % 76.16/76.38 189330[115:SSi:189329.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.38 189331[113:Spt:189330.0,188729.0,188730.0] || until2p7(s22)*+ -> . % 76.16/76.38 189332[113:Spt:189330.0,188729.1] || -> node4(s21)*. % 76.16/76.38 189334[113:MRR:855.0,189332.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.38 189337[113:Res:53.1,189334.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.38 189342[114:Spt:189337.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 189344[114:Res:189342.0,61.1] always3(s21) || -> . % 76.16/76.38 189345[114:SSi:189344.0,78160.0,78163.0,165513.0,188728.0,189332.0] || -> . % 76.16/76.38 189346[114:Spt:189345.0,189337.0,189342.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.38 189347[114:Spt:189345.0,189337.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.38 189351[114:Res:189347.0,61.1] always3(s22) || -> . % 76.16/76.38 189352[114:SSi:189351.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.38 189353[112:Spt:189352.0,188727.0,188728.0] || until2p7(s21)*+ -> . % 76.16/76.38 189354[112:Spt:189352.0,188727.1] || -> node4(s20)*. % 76.16/76.38 189356[112:MRR:858.0,189354.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.38 189359[112:Res:53.1,189356.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.38 189361[113:Spt:189359.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 189363[113:Res:189361.0,61.1] always3(s20) || -> . % 76.16/76.38 189364[113:SSi:189363.0,78155.0,78159.0,165512.0,188726.0,189354.0] || -> . % 76.16/76.38 189365[113:Spt:189364.0,189359.0,189361.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.38 189366[113:Spt:189364.0,189359.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.38 189370[113:Res:189366.0,61.1] always3(s21) || -> . % 76.16/76.38 189371[113:SSi:189370.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.38 189372[111:Spt:189371.0,188725.0,188726.0] || until2p7(s20)*+ -> . % 76.16/76.38 189373[111:Spt:189371.0,188725.1] || -> node4(s19)*. % 76.16/76.38 189375[111:MRR:861.0,189373.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.38 189378[111:Res:53.1,189375.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.38 189380[112:Spt:189378.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 189382[112:Res:189380.0,61.1] always3(s19) || -> . % 76.16/76.38 189383[112:SSi:189382.0,78151.0,78154.0,165511.0,188724.0,189373.0] || -> . % 76.16/76.38 189384[112:Spt:189383.0,189378.0,189380.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.38 189385[112:Spt:189383.0,189378.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.38 189389[112:Res:189385.0,61.1] always3(s20) || -> . % 76.16/76.38 189390[112:SSi:189389.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.38 189391[110:Spt:189390.0,188723.0,188724.0] || until2p7(s19)*+ -> . % 76.16/76.38 189392[110:Spt:189390.0,188723.1] || -> node4(s18)*. % 76.16/76.38 189394[110:MRR:864.0,189392.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.38 189397[110:Res:53.1,189394.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.38 189399[111:Spt:189397.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 189401[111:Res:189399.0,61.1] always3(s18) || -> . % 76.16/76.38 189402[111:SSi:189401.0,78146.0,78150.0,165510.0,188722.0,189392.0] || -> . % 76.16/76.38 189403[111:Spt:189402.0,189397.0,189399.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.38 189404[111:Spt:189402.0,189397.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.38 189408[111:Res:189404.0,61.1] always3(s19) || -> . % 76.16/76.38 189409[111:SSi:189408.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.38 189410[109:Spt:189409.0,188721.0,188722.0] || until2p7(s18)*+ -> . % 76.16/76.38 189411[109:Spt:189409.0,188721.1] || -> node4(s17)*. % 76.16/76.38 189413[109:MRR:867.0,189411.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.38 189416[109:Res:53.1,189413.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.38 189421[110:Spt:189416.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 189423[110:Res:189421.0,61.1] always3(s17) || -> . % 76.16/76.38 189424[110:SSi:189423.0,78142.0,78145.0,165509.0,188720.0,189411.0] || -> . % 76.16/76.38 189425[110:Spt:189424.0,189416.0,189421.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.38 189426[110:Spt:189424.0,189416.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.38 189430[110:Res:189426.0,61.1] always3(s18) || -> . % 76.16/76.38 189431[110:SSi:189430.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.38 189432[108:Spt:189431.0,188719.0,188720.0] || until2p7(s17)*+ -> . % 76.16/76.38 189433[108:Spt:189431.0,188719.1] || -> node4(s16)*. % 76.16/76.38 189435[108:MRR:870.0,189433.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.38 189438[108:Res:53.1,189435.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.38 189440[109:Spt:189438.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 189442[109:Res:189440.0,61.1] always3(s16) || -> . % 76.16/76.38 189443[109:SSi:189442.0,78137.0,78141.0,165508.0,188718.0,189433.0] || -> . % 76.16/76.38 189444[109:Spt:189443.0,189438.0,189440.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.38 189445[109:Spt:189443.0,189438.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.38 189449[109:Res:189445.0,61.1] always3(s17) || -> . % 76.16/76.38 189450[109:SSi:189449.0,78142.0,78145.0,165509.0] || -> . % 76.16/76.38 189451[107:Spt:189450.0,188717.0,188718.0] || until2p7(s16)*+ -> . % 76.16/76.38 189452[107:Spt:189450.0,188717.1] || -> node4(s15)*. % 76.16/76.38 189454[107:MRR:873.0,189452.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.38 189457[107:Res:53.1,189454.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.38 189459[108:Spt:189457.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 189461[108:Res:189459.0,61.1] always3(s15) || -> . % 76.16/76.38 189462[108:SSi:189461.0,78133.0,78136.0,165507.0,188716.0,189452.0] || -> . % 76.16/76.38 189463[108:Spt:189462.0,189457.0,189459.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.38 189464[108:Spt:189462.0,189457.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.38 189468[108:Res:189464.0,61.1] always3(s16) || -> . % 76.16/76.38 189469[108:SSi:189468.0,78137.0,78141.0,165508.0] || -> . % 76.16/76.38 189470[106:Spt:189469.0,188715.0,188716.0] || until2p7(s15)*+ -> . % 76.16/76.38 189471[106:Spt:189469.0,188715.1] || -> node4(s14)*. % 76.16/76.38 189473[106:MRR:876.0,189471.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.38 189476[106:Res:53.1,189473.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.38 189478[107:Spt:189476.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 189480[107:Res:189478.0,61.1] always3(s14) || -> . % 76.16/76.38 189481[107:SSi:189480.0,78128.0,78132.0,165506.0,188714.0,189471.0] || -> . % 76.16/76.38 189482[107:Spt:189481.0,189476.0,189478.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.38 189483[107:Spt:189481.0,189476.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.38 189487[107:Res:189483.0,61.1] always3(s15) || -> . % 76.16/76.38 189488[107:SSi:189487.0,78133.0,78136.0,165507.0] || -> . % 76.16/76.38 189489[105:Spt:189488.0,188713.0,188714.0] || until2p7(s14)*+ -> . % 76.16/76.38 189490[105:Spt:189488.0,188713.1] || -> node4(s13)*. % 76.16/76.38 189492[105:MRR:879.0,189490.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.38 189495[105:Res:53.1,189492.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.38 189500[106:Spt:189495.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 189502[106:Res:189500.0,61.1] always3(s13) || -> . % 76.16/76.38 189503[106:SSi:189502.0,78124.0,78127.0,165505.0,188712.0,189490.0] || -> . % 76.16/76.38 189504[106:Spt:189503.0,189495.0,189500.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.38 189505[106:Spt:189503.0,189495.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.38 189509[106:Res:189505.0,61.1] always3(s14) || -> . % 76.16/76.38 189510[106:SSi:189509.0,78128.0,78132.0,165506.0] || -> . % 76.16/76.38 189511[104:Spt:189510.0,188711.0,188712.0] || until2p7(s13)*+ -> . % 76.16/76.38 189512[104:Spt:189510.0,188711.1] || -> node4(s12)*. % 76.16/76.38 189514[104:MRR:882.0,189512.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.38 189517[104:Res:53.1,189514.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.38 189519[105:Spt:189517.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.38 189521[105:Res:189519.0,61.1] always3(s12) || -> . % 76.16/76.38 189522[105:SSi:189521.0,78119.0,78123.0,165504.0,188710.0,189512.0] || -> . % 76.16/76.38 189523[105:Spt:189522.0,189517.0,189519.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.38 189524[105:Spt:189522.0,189517.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.38 189528[105:Res:189524.0,61.1] always3(s13) || -> . % 76.16/76.38 189529[105:SSi:189528.0,78124.0,78127.0,165505.0] || -> . % 76.16/76.38 189530[103:Spt:189529.0,188709.0,188710.0] || until2p7(s12)*+ -> . % 76.16/76.38 189531[103:Spt:189529.0,188709.1] || -> node4(s11)*. % 76.16/76.38 189533[103:MRR:885.0,189531.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.38 189536[103:Res:53.1,189533.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.38 189538[104:Spt:189536.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.38 189540[104:Res:189538.0,61.1] always3(s11) || -> . % 76.16/76.38 189541[104:SSi:189540.0,78115.0,78118.0,165503.0,188708.0,189531.0] || -> . % 76.16/76.38 189542[104:Spt:189541.0,189536.0,189538.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.38 189543[104:Spt:189541.0,189536.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.38 189547[104:Res:189543.0,61.1] always3(s12) || -> . % 76.16/76.38 189548[104:SSi:189547.0,78119.0,78123.0,165504.0] || -> . % 76.16/76.38 189549[102:Spt:189548.0,188707.0,188708.0] || until2p7(s11)*+ -> . % 76.16/76.38 189550[102:Spt:189548.0,188707.1] || -> node4(s10)*. % 76.16/76.38 189552[102:MRR:888.0,189550.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.38 189555[102:Res:53.1,189552.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.38 189557[103:Spt:189555.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.38 189559[103:Res:189557.0,61.1] always3(s10) || -> . % 76.16/76.38 189560[103:SSi:189559.0,78110.0,78114.0,165502.0,188706.0,189550.0] || -> . % 76.16/76.38 189561[103:Spt:189560.0,189555.0,189557.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.38 189562[103:Spt:189560.0,189555.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.38 189566[103:Res:189562.0,61.1] always3(s11) || -> . % 76.16/76.38 189567[103:SSi:189566.0,78115.0,78118.0,165503.0] || -> . % 76.16/76.38 189568[101:Spt:189567.0,188705.0,188706.0] || until2p7(s10)*+ -> . % 76.16/76.38 189569[101:Spt:189567.0,188705.1] || -> node4(s9)*. % 76.16/76.38 189571[101:MRR:891.0,189569.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.38 189574[101:Res:53.1,189571.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.38 189579[102:Spt:189574.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.38 189581[102:Res:189579.0,61.1] always3(s9) || -> . % 76.16/76.38 189582[102:SSi:189581.0,78106.0,78109.0,165501.0,188704.0,189569.0] || -> . % 76.16/76.38 189583[102:Spt:189582.0,189574.0,189579.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.38 189584[102:Spt:189582.0,189574.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.38 189588[102:Res:189584.0,61.1] always3(s10) || -> . % 76.16/76.38 189589[102:SSi:189588.0,78110.0,78114.0,165502.0] || -> . % 76.16/76.38 189590[100:Spt:189589.0,188703.0,188704.0] || until2p7(s9)*+ -> . % 76.16/76.38 189591[100:Spt:189589.0,188703.1] || -> node4(s8)*. % 76.16/76.38 189593[100:MRR:894.0,189591.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.38 189596[100:Res:53.1,189593.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.38 189598[101:Spt:189596.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.38 189600[101:Res:189598.0,61.1] always3(s8) || -> . % 76.16/76.38 189601[101:SSi:189600.0,78101.0,78105.0,165500.0,188702.0,189591.0] || -> . % 76.16/76.38 189602[101:Spt:189601.0,189596.0,189598.0] || m_main_v_state(s8,c_busy)* -> . % 76.16/76.38 189603[101:Spt:189601.0,189596.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.38 189607[101:Res:189603.0,61.1] always3(s9) || -> . % 76.16/76.38 189608[101:SSi:189607.0,78106.0,78109.0,165501.0] || -> . % 76.16/76.38 189609[99:Spt:189608.0,188701.0,188702.0] || until2p7(s8)*+ -> . % 76.16/76.38 189610[99:Spt:189608.0,188701.1] || -> node4(s7)*. % 76.16/76.38 189612[99:MRR:897.0,189610.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.16/76.38 189615[99:Res:53.1,189612.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.16/76.38 189617[99:MRR:189615.0,188691.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.38 189619[99:Res:189617.0,61.1] always3(s8) || -> . % 76.16/76.38 189620[99:SSi:189619.0,78101.0,78105.0,165500.0] || -> . % 76.16/76.38 189621[97:Spt:189620.0,188534.0,188537.0] || trans(s49,s7)*+ -> . % 76.16/76.38 189622[97:Spt:189620.0,188534.1,188534.2] || -> trans(s49,s6) node2(s49,s5)*. % 76.16/76.38 189624[97:MRR:188536.1,189621.0] xuntil6(s49) || -> trans(s49,s6)* until2p7(s5). % 76.16/76.38 189625[98:Spt:189622.0] || -> trans(s49,s6)*. % 76.16/76.38 189626[98:Res:189625.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s6)*. % 76.16/76.38 189628[98:Res:189625.0,60.0] || -> node2(s49,s6)*. % 76.16/76.38 189629[98:SSi:189626.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s6)*. % 76.16/76.38 189630[98:Res:189628.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)*. % 76.16/76.38 189772[98:SoR:189630.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)*. % 76.16/76.38 189774[98:SoR:189772.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)* xuntil6(s49). % 76.16/76.38 189775[98:SSi:189774.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s6,c_busy)* xuntil6(s49). % 76.16/76.38 189776[99:Spt:189775.1] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.38 189778[99:Res:189776.0,61.1] always3(s6) || -> . % 76.16/76.38 189779[99:SSi:189778.0,78093.0,78096.0,165498.0] || -> . % 76.16/76.38 189780[99:Spt:189779.0,189775.1,189776.0] || m_main_v_state(s6,c_busy)*+ -> . % 76.16/76.38 189781[99:Spt:189779.0,189775.0,189775.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.38 189785[99:MRR:189772.2,189780.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.38 189786[99:Res:53.1,189781.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.38 189788[99:MRR:189786.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.38 189789[99:MRR:189629.0,189788.0] || -> until2p7(s6)*. % 76.16/76.38 189790[99:MRR:202.0,189789.0] || -> until2p7(s7)* node4(s6). % 76.16/76.38 189791[100:Spt:189790.0] || -> until2p7(s7)*. % 76.16/76.38 189792[100:MRR:203.0,189791.0] || -> until2p7(s8)* node4(s7). % 76.16/76.38 189793[101:Spt:189792.0] || -> until2p7(s8)*. % 76.16/76.38 189794[101:MRR:204.0,189793.0] || -> until2p7(s9)* node4(s8). % 76.16/76.38 189795[102:Spt:189794.0] || -> until2p7(s9)*. % 76.16/76.38 189796[102:MRR:205.0,189795.0] || -> until2p7(s10)* node4(s9). % 76.16/76.38 189797[103:Spt:189796.0] || -> until2p7(s10)*. % 76.16/76.38 189798[103:MRR:206.0,189797.0] || -> until2p7(s11)* node4(s10). % 76.16/76.38 189799[104:Spt:189798.0] || -> until2p7(s11)*. % 76.16/76.38 189800[104:MRR:207.0,189799.0] || -> until2p7(s12)* node4(s11). % 76.16/76.38 189801[105:Spt:189800.0] || -> until2p7(s12)*. % 76.16/76.38 189802[105:MRR:208.0,189801.0] || -> until2p7(s13)* node4(s12). % 76.16/76.38 189803[106:Spt:189802.0] || -> until2p7(s13)*. % 76.16/76.38 189804[106:MRR:209.0,189803.0] || -> until2p7(s14)* node4(s13). % 76.16/76.38 189805[107:Spt:189804.0] || -> until2p7(s14)*. % 76.16/76.38 189806[107:MRR:210.0,189805.0] || -> until2p7(s15)* node4(s14). % 76.16/76.38 189807[108:Spt:189806.0] || -> until2p7(s15)*. % 76.16/76.38 189808[108:MRR:211.0,189807.0] || -> until2p7(s16)* node4(s15). % 76.16/76.38 189809[109:Spt:189808.0] || -> until2p7(s16)*. % 76.16/76.38 189810[109:MRR:212.0,189809.0] || -> until2p7(s17)* node4(s16). % 76.16/76.38 189811[110:Spt:189810.0] || -> until2p7(s17)*. % 76.16/76.38 189812[110:MRR:213.0,189811.0] || -> until2p7(s18)* node4(s17). % 76.16/76.38 189813[111:Spt:189812.0] || -> until2p7(s18)*. % 76.16/76.38 189814[111:MRR:214.0,189813.0] || -> until2p7(s19)* node4(s18). % 76.16/76.38 189815[112:Spt:189814.0] || -> until2p7(s19)*. % 76.16/76.38 189816[112:MRR:215.0,189815.0] || -> until2p7(s20)* node4(s19). % 76.16/76.38 189817[113:Spt:189816.0] || -> until2p7(s20)*. % 76.16/76.38 189818[113:MRR:216.0,189817.0] || -> until2p7(s21)* node4(s20). % 76.16/76.38 189819[114:Spt:189818.0] || -> until2p7(s21)*. % 76.16/76.38 189820[114:MRR:217.0,189819.0] || -> until2p7(s22)* node4(s21). % 76.16/76.38 189821[115:Spt:189820.0] || -> until2p7(s22)*. % 76.16/76.38 189822[115:MRR:218.0,189821.0] || -> until2p7(s23)* node4(s22). % 76.16/76.38 189823[116:Spt:189822.0] || -> until2p7(s23)*. % 76.16/76.38 189824[116:MRR:219.0,189823.0] || -> until2p7(s24)* node4(s23). % 76.16/76.38 189825[117:Spt:189824.0] || -> until2p7(s24)*. % 76.16/76.38 189826[117:MRR:220.0,189825.0] || -> until2p7(s25)* node4(s24). % 76.16/76.38 189827[118:Spt:189826.0] || -> until2p7(s25)*. % 76.16/76.38 189828[118:MRR:221.0,189827.0] || -> until2p7(s26)* node4(s25). % 76.16/76.38 189829[119:Spt:189828.0] || -> until2p7(s26)*. % 76.16/76.38 189830[119:MRR:222.0,189829.0] || -> until2p7(s27)* node4(s26). % 76.16/76.38 189831[120:Spt:189830.0] || -> until2p7(s27)*. % 76.16/76.38 189832[120:MRR:223.0,189831.0] || -> until2p7(s28)* node4(s27). % 76.16/76.38 189833[121:Spt:189832.0] || -> until2p7(s28)*. % 76.16/76.38 189834[121:MRR:224.0,189833.0] || -> until2p7(s29)* node4(s28). % 76.16/76.38 189835[122:Spt:189834.0] || -> until2p7(s29)*. % 76.16/76.38 189836[122:MRR:225.0,189835.0] || -> until2p7(s30)* node4(s29). % 76.16/76.38 189837[123:Spt:189836.0] || -> until2p7(s30)*. % 76.16/76.38 189838[123:MRR:226.0,189837.0] || -> until2p7(s31)* node4(s30). % 76.16/76.38 189839[124:Spt:189838.0] || -> until2p7(s31)*. % 76.16/76.38 189840[124:MRR:227.0,189839.0] || -> until2p7(s32)* node4(s31). % 76.16/76.38 189841[125:Spt:189840.0] || -> until2p7(s32)*. % 76.16/76.38 189842[125:MRR:228.0,189841.0] || -> until2p7(s33)* node4(s32). % 76.16/76.38 189843[126:Spt:189842.0] || -> until2p7(s33)*. % 76.16/76.38 189844[126:MRR:229.0,189843.0] || -> until2p7(s34)* node4(s33). % 76.16/76.38 189845[127:Spt:189844.0] || -> until2p7(s34)*. % 76.16/76.38 189846[127:MRR:230.0,189845.0] || -> until2p7(s35)* node4(s34). % 76.16/76.38 189847[128:Spt:189846.0] || -> until2p7(s35)*. % 76.16/76.38 189848[128:MRR:231.0,189847.0] || -> until2p7(s36)* node4(s35). % 76.16/76.38 189849[129:Spt:189848.0] || -> until2p7(s36)*. % 76.16/76.38 189850[129:MRR:232.0,189849.0] || -> until2p7(s37)* node4(s36). % 76.16/76.38 189851[130:Spt:189850.0] || -> until2p7(s37)*. % 76.16/76.38 189852[130:MRR:235.0,189851.0] || -> until2p7(s38)* node4(s37). % 76.16/76.38 189853[131:Spt:189852.0] || -> until2p7(s38)*. % 76.16/76.38 189854[131:MRR:236.0,189853.0] || -> until2p7(s39)* node4(s38). % 76.16/76.38 189855[132:Spt:189854.0] || -> until2p7(s39)*. % 76.16/76.38 189856[132:MRR:237.0,189855.0] || -> until2p7(s40)* node4(s39). % 76.16/76.38 189857[133:Spt:189856.0] || -> until2p7(s40)*. % 76.16/76.38 189858[133:MRR:238.0,189857.0] || -> until2p7(s41)* node4(s40). % 76.16/76.38 189859[134:Spt:189858.0] || -> until2p7(s41)*. % 76.16/76.38 189860[134:MRR:239.0,189859.0] || -> until2p7(s42)* node4(s41). % 76.16/76.38 189861[135:Spt:189860.0] || -> until2p7(s42)*. % 76.16/76.38 189862[135:MRR:240.0,189861.0] || -> until2p7(s43)* node4(s42). % 76.16/76.38 189863[136:Spt:189862.0] || -> until2p7(s43)*. % 76.16/76.38 189864[136:MRR:241.0,189863.0] || -> until2p7(s44)* node4(s43). % 76.16/76.38 189865[137:Spt:189864.0] || -> until2p7(s44)*. % 76.16/76.38 189866[137:MRR:539.0,189865.0] || -> until2p7(s45)* node4(s44). % 76.16/76.38 189867[138:Spt:189866.0] || -> until2p7(s45)*. % 76.16/76.38 189868[138:MRR:544.0,189867.0] || -> until2p7(s46)* node4(s45). % 76.16/76.38 189869[139:Spt:189868.0] || -> until2p7(s46)*. % 76.16/76.38 189870[139:MRR:549.0,189869.0] || -> until2p7(s47)* node4(s46). % 76.16/76.38 189871[140:Spt:189870.0] || -> until2p7(s47)*. % 76.16/76.38 189872[140:MRR:554.0,189871.0] || -> until2p7(s48)* node4(s47). % 76.16/76.38 189873[141:Spt:189872.0] || -> until2p7(s48)*. % 76.16/76.38 189874[141:MRR:559.0,189873.0] || -> until2p7(s49)* node4(s48). % 76.16/76.38 189875[142:Spt:189874.0] || -> until2p7(s49)*. % 76.16/76.38 189876[142:MRR:194.0,189875.0] || -> node4(s49)*. % 76.16/76.38 189877[142:MRR:189785.0,189876.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.38 189881[142:Res:53.1,189877.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.38 189883[142:MRR:189881.0,78381.0] || -> . % 76.16/76.38 189884[142:Spt:189883.0,189874.0,189875.0] || until2p7(s49)*+ -> . % 76.16/76.38 189885[142:Spt:189883.0,189874.1] || -> node4(s48)*. % 76.16/76.38 189886[142:MRR:78384.0,189885.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.38 189889[142:Res:53.1,189886.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 189892[142:Res:189889.0,61.1] always3(s48) || -> . % 76.16/76.38 189893[142:SSi:189892.0,78281.0,78387.0,165540.0,189873.0,189885.0] || -> . % 76.16/76.38 189894[141:Spt:189893.0,189872.0,189873.0] || until2p7(s48)*+ -> . % 76.16/76.38 189895[141:Spt:189893.0,189872.1] || -> node4(s47)*. % 76.16/76.38 189897[141:MRR:777.0,189895.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.38 189909[141:Res:53.1,189897.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.38 189911[142:Spt:189909.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 189913[142:Res:189911.0,61.1] always3(s47) || -> . % 76.16/76.38 189914[142:SSi:189913.0,78277.0,78280.0,165539.0,189871.0,189895.0] || -> . % 76.16/76.38 189915[142:Spt:189914.0,189909.0,189911.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.38 189916[142:Spt:189914.0,189909.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.38 189920[142:Res:189916.0,61.1] always3(s48) || -> . % 76.16/76.38 189921[142:SSi:189920.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.38 189922[140:Spt:189921.0,189870.0,189871.0] || until2p7(s47)*+ -> . % 76.16/76.38 189923[140:Spt:189921.0,189870.1] || -> node4(s46)*. % 76.16/76.38 189925[140:MRR:780.0,189923.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.38 189932[140:Res:53.1,189925.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.38 189937[141:Spt:189932.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 189939[141:Res:189937.0,61.1] always3(s46) || -> . % 76.16/76.38 189940[141:SSi:189939.0,78272.0,78276.0,165538.0,189869.0,189923.0] || -> . % 76.16/76.38 189941[141:Spt:189940.0,189932.0,189937.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.38 189942[141:Spt:189940.0,189932.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.38 189946[141:Res:189942.0,61.1] always3(s47) || -> . % 76.16/76.38 189947[141:SSi:189946.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.38 189948[139:Spt:189947.0,189868.0,189869.0] || until2p7(s46)*+ -> . % 76.16/76.38 189949[139:Spt:189947.0,189868.1] || -> node4(s45)*. % 76.16/76.38 189951[139:MRR:783.0,189949.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.38 189954[139:Res:53.1,189951.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.38 189956[140:Spt:189954.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 189958[140:Res:189956.0,61.1] always3(s45) || -> . % 76.16/76.38 189959[140:SSi:189958.0,78268.0,78271.0,165537.0,189867.0,189949.0] || -> . % 76.16/76.38 189960[140:Spt:189959.0,189954.0,189956.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.38 189961[140:Spt:189959.0,189954.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.38 189965[140:Res:189961.0,61.1] always3(s46) || -> . % 76.16/76.38 189966[140:SSi:189965.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.38 189967[138:Spt:189966.0,189866.0,189867.0] || until2p7(s45)*+ -> . % 76.16/76.38 189968[138:Spt:189966.0,189866.1] || -> node4(s44)*. % 76.16/76.38 189970[138:MRR:786.0,189968.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.38 189973[138:Res:53.1,189970.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.38 189975[139:Spt:189973.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 189977[139:Res:189975.0,61.1] always3(s44) || -> . % 76.16/76.38 189978[139:SSi:189977.0,78263.0,78267.0,165536.0,189865.0,189968.0] || -> . % 76.16/76.38 189979[139:Spt:189978.0,189973.0,189975.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.38 189980[139:Spt:189978.0,189973.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.38 189984[139:Res:189980.0,61.1] always3(s45) || -> . % 76.16/76.38 189985[139:SSi:189984.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.38 189986[137:Spt:189985.0,189864.0,189865.0] || until2p7(s44)*+ -> . % 76.16/76.38 189987[137:Spt:189985.0,189864.1] || -> node4(s43)*. % 76.16/76.38 189989[137:MRR:789.0,189987.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.38 189992[137:Res:53.1,189989.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.38 189994[138:Spt:189992.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.38 189996[138:Res:189994.0,61.1] always3(s43) || -> . % 76.16/76.38 189997[138:SSi:189996.0,78259.0,78262.0,165535.0,189863.0,189987.0] || -> . % 76.16/76.38 189998[138:Spt:189997.0,189992.0,189994.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.38 189999[138:Spt:189997.0,189992.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.38 190003[138:Res:189999.0,61.1] always3(s44) || -> . % 76.16/76.38 190004[138:SSi:190003.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.38 190005[136:Spt:190004.0,189862.0,189863.0] || until2p7(s43)*+ -> . % 76.16/76.38 190006[136:Spt:190004.0,189862.1] || -> node4(s42)*. % 76.16/76.38 190008[136:MRR:792.0,190006.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.38 190011[136:Res:53.1,190008.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.38 190016[137:Spt:190011.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.38 190018[137:Res:190016.0,61.1] always3(s42) || -> . % 76.16/76.38 190019[137:SSi:190018.0,78254.0,78258.0,165534.0,189861.0,190006.0] || -> . % 76.16/76.38 190020[137:Spt:190019.0,190011.0,190016.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.38 190021[137:Spt:190019.0,190011.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 190025[137:Res:190021.0,61.1] always3(s43) || -> . % 76.16/76.39 190026[137:SSi:190025.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.39 190027[135:Spt:190026.0,189860.0,189861.0] || until2p7(s42)*+ -> . % 76.16/76.39 190028[135:Spt:190026.0,189860.1] || -> node4(s41)*. % 76.16/76.39 190030[135:MRR:795.0,190028.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 190033[135:Res:53.1,190030.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 190035[136:Spt:190033.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 190037[136:Res:190035.0,61.1] always3(s41) || -> . % 76.16/76.39 190038[136:SSi:190037.0,78250.0,78253.0,165533.0,189859.0,190028.0] || -> . % 76.16/76.39 190039[136:Spt:190038.0,190033.0,190035.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 190040[136:Spt:190038.0,190033.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 190044[136:Res:190040.0,61.1] always3(s42) || -> . % 76.16/76.39 190045[136:SSi:190044.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.39 190046[134:Spt:190045.0,189858.0,189859.0] || until2p7(s41)*+ -> . % 76.16/76.39 190047[134:Spt:190045.0,189858.1] || -> node4(s40)*. % 76.16/76.39 190049[134:MRR:798.0,190047.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 190052[134:Res:53.1,190049.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 190054[135:Spt:190052.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 190056[135:Res:190054.0,61.1] always3(s40) || -> . % 76.16/76.39 190057[135:SSi:190056.0,78245.0,78249.0,165532.0,189857.0,190047.0] || -> . % 76.16/76.39 190058[135:Spt:190057.0,190052.0,190054.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 190059[135:Spt:190057.0,190052.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 190063[135:Res:190059.0,61.1] always3(s41) || -> . % 76.16/76.39 190064[135:SSi:190063.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.39 190065[133:Spt:190064.0,189856.0,189857.0] || until2p7(s40)*+ -> . % 76.16/76.39 190066[133:Spt:190064.0,189856.1] || -> node4(s39)*. % 76.16/76.39 190068[133:MRR:801.0,190066.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 190071[133:Res:53.1,190068.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 190073[134:Spt:190071.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 190075[134:Res:190073.0,61.1] always3(s39) || -> . % 76.16/76.39 190076[134:SSi:190075.0,78241.0,78244.0,165531.0,189855.0,190066.0] || -> . % 76.16/76.39 190077[134:Spt:190076.0,190071.0,190073.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 190078[134:Spt:190076.0,190071.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 190082[134:Res:190078.0,61.1] always3(s40) || -> . % 76.16/76.39 190083[134:SSi:190082.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.39 190084[132:Spt:190083.0,189854.0,189855.0] || until2p7(s39)*+ -> . % 76.16/76.39 190085[132:Spt:190083.0,189854.1] || -> node4(s38)*. % 76.16/76.39 190087[132:MRR:804.0,190085.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 190090[132:Res:53.1,190087.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 190095[133:Spt:190090.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 190097[133:Res:190095.0,61.1] always3(s38) || -> . % 76.16/76.39 190098[133:SSi:190097.0,78236.0,78240.0,165530.0,189853.0,190085.0] || -> . % 76.16/76.39 190099[133:Spt:190098.0,190090.0,190095.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 190100[133:Spt:190098.0,190090.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 190104[133:Res:190100.0,61.1] always3(s39) || -> . % 76.16/76.39 190105[133:SSi:190104.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.39 190106[131:Spt:190105.0,189852.0,189853.0] || until2p7(s38)*+ -> . % 76.16/76.39 190107[131:Spt:190105.0,189852.1] || -> node4(s37)*. % 76.16/76.39 190109[131:MRR:807.0,190107.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 190112[131:Res:53.1,190109.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 190114[132:Spt:190112.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 190116[132:Res:190114.0,61.1] always3(s37) || -> . % 76.16/76.39 190117[132:SSi:190116.0,78232.0,78235.0,165529.0,189851.0,190107.0] || -> . % 76.16/76.39 190118[132:Spt:190117.0,190112.0,190114.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.39 190119[132:Spt:190117.0,190112.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 190123[132:Res:190119.0,61.1] always3(s38) || -> . % 76.16/76.39 190124[132:SSi:190123.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.39 190125[130:Spt:190124.0,189850.0,189851.0] || until2p7(s37)*+ -> . % 76.16/76.39 190126[130:Spt:190124.0,189850.1] || -> node4(s36)*. % 76.16/76.39 190128[130:MRR:810.0,190126.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.39 190131[130:Res:53.1,190128.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.39 190133[131:Spt:190131.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 190135[131:Res:190133.0,61.1] always3(s36) || -> . % 76.16/76.39 190136[131:SSi:190135.0,78227.0,78231.0,165528.0,189849.0,190126.0] || -> . % 76.16/76.39 190137[131:Spt:190136.0,190131.0,190133.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.39 190138[131:Spt:190136.0,190131.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 190142[131:Res:190138.0,61.1] always3(s37) || -> . % 76.16/76.39 190143[131:SSi:190142.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.39 190144[129:Spt:190143.0,189848.0,189849.0] || until2p7(s36)*+ -> . % 76.16/76.39 190145[129:Spt:190143.0,189848.1] || -> node4(s35)*. % 76.16/76.39 190147[129:MRR:813.0,190145.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.39 190150[129:Res:53.1,190147.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.39 190152[130:Spt:190150.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 190154[130:Res:190152.0,61.1] always3(s35) || -> . % 76.16/76.39 190155[130:SSi:190154.0,78223.0,78226.0,165527.0,189847.0,190145.0] || -> . % 76.16/76.39 190156[130:Spt:190155.0,190150.0,190152.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.39 190157[130:Spt:190155.0,190150.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 190161[130:Res:190157.0,61.1] always3(s36) || -> . % 76.16/76.39 190162[130:SSi:190161.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.39 190163[128:Spt:190162.0,189846.0,189847.0] || until2p7(s35)*+ -> . % 76.16/76.39 190164[128:Spt:190162.0,189846.1] || -> node4(s34)*. % 76.16/76.39 190166[128:MRR:816.0,190164.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.39 190169[128:Res:53.1,190166.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.39 190174[129:Spt:190169.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 190176[129:Res:190174.0,61.1] always3(s34) || -> . % 76.16/76.39 190177[129:SSi:190176.0,78218.0,78222.0,165526.0,189845.0,190164.0] || -> . % 76.16/76.39 190178[129:Spt:190177.0,190169.0,190174.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.39 190179[129:Spt:190177.0,190169.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 190183[129:Res:190179.0,61.1] always3(s35) || -> . % 76.16/76.39 190184[129:SSi:190183.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.39 190185[127:Spt:190184.0,189844.0,189845.0] || until2p7(s34)*+ -> . % 76.16/76.39 190186[127:Spt:190184.0,189844.1] || -> node4(s33)*. % 76.16/76.39 190188[127:MRR:819.0,190186.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.39 190191[127:Res:53.1,190188.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.39 190193[128:Spt:190191.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 190195[128:Res:190193.0,61.1] always3(s33) || -> . % 76.16/76.39 190196[128:SSi:190195.0,78214.0,78217.0,165525.0,189843.0,190186.0] || -> . % 76.16/76.39 190197[128:Spt:190196.0,190191.0,190193.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.39 190198[128:Spt:190196.0,190191.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 190202[128:Res:190198.0,61.1] always3(s34) || -> . % 76.16/76.39 190203[128:SSi:190202.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.39 190204[126:Spt:190203.0,189842.0,189843.0] || until2p7(s33)*+ -> . % 76.16/76.39 190205[126:Spt:190203.0,189842.1] || -> node4(s32)*. % 76.16/76.39 190207[126:MRR:822.0,190205.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.39 190210[126:Res:53.1,190207.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.39 190212[127:Spt:190210.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 190214[127:Res:190212.0,61.1] always3(s32) || -> . % 76.16/76.39 190215[127:SSi:190214.0,78209.0,78213.0,165524.0,189841.0,190205.0] || -> . % 76.16/76.39 190216[127:Spt:190215.0,190210.0,190212.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.39 190217[127:Spt:190215.0,190210.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 190221[127:Res:190217.0,61.1] always3(s33) || -> . % 76.16/76.39 190222[127:SSi:190221.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.39 190223[125:Spt:190222.0,189840.0,189841.0] || until2p7(s32)*+ -> . % 76.16/76.39 190224[125:Spt:190222.0,189840.1] || -> node4(s31)*. % 76.16/76.39 190226[125:MRR:825.0,190224.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.39 190229[125:Res:53.1,190226.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.39 190231[126:Spt:190229.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 190233[126:Res:190231.0,61.1] always3(s31) || -> . % 76.16/76.39 190234[126:SSi:190233.0,78205.0,78208.0,165523.0,189839.0,190224.0] || -> . % 76.16/76.39 190235[126:Spt:190234.0,190229.0,190231.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.39 190236[126:Spt:190234.0,190229.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 190240[126:Res:190236.0,61.1] always3(s32) || -> . % 76.16/76.39 190241[126:SSi:190240.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.39 190242[124:Spt:190241.0,189838.0,189839.0] || until2p7(s31)*+ -> . % 76.16/76.39 190243[124:Spt:190241.0,189838.1] || -> node4(s30)*. % 76.16/76.39 190245[124:MRR:828.0,190243.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.39 190248[124:Res:53.1,190245.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.39 190253[125:Spt:190248.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 190255[125:Res:190253.0,61.1] always3(s30) || -> . % 76.16/76.39 190256[125:SSi:190255.0,78200.0,78204.0,165522.0,189837.0,190243.0] || -> . % 76.16/76.39 190257[125:Spt:190256.0,190248.0,190253.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.39 190258[125:Spt:190256.0,190248.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 190262[125:Res:190258.0,61.1] always3(s31) || -> . % 76.16/76.39 190263[125:SSi:190262.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.39 190264[123:Spt:190263.0,189836.0,189837.0] || until2p7(s30)*+ -> . % 76.16/76.39 190265[123:Spt:190263.0,189836.1] || -> node4(s29)*. % 76.16/76.39 190267[123:MRR:831.0,190265.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.39 190270[123:Res:53.1,190267.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.39 190272[124:Spt:190270.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.39 190274[124:Res:190272.0,61.1] always3(s29) || -> . % 76.16/76.39 190275[124:SSi:190274.0,78196.0,78199.0,165521.0,189835.0,190265.0] || -> . % 76.16/76.39 190276[124:Spt:190275.0,190270.0,190272.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.39 190277[124:Spt:190275.0,190270.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 190281[124:Res:190277.0,61.1] always3(s30) || -> . % 76.16/76.39 190282[124:SSi:190281.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.39 190283[122:Spt:190282.0,189834.0,189835.0] || until2p7(s29)*+ -> . % 76.16/76.39 190284[122:Spt:190282.0,189834.1] || -> node4(s28)*. % 76.16/76.39 190286[122:MRR:834.0,190284.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.39 190289[122:Res:53.1,190286.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.39 190291[123:Spt:190289.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.39 190293[123:Res:190291.0,61.1] always3(s28) || -> . % 76.16/76.39 190294[123:SSi:190293.0,78191.0,78195.0,165520.0,189833.0,190284.0] || -> . % 76.16/76.39 190295[123:Spt:190294.0,190289.0,190291.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.39 190296[123:Spt:190294.0,190289.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.39 190300[123:Res:190296.0,61.1] always3(s29) || -> . % 76.16/76.39 190301[123:SSi:190300.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.39 190302[121:Spt:190301.0,189832.0,189833.0] || until2p7(s28)*+ -> . % 76.16/76.39 190303[121:Spt:190301.0,189832.1] || -> node4(s27)*. % 76.16/76.39 190305[121:MRR:837.0,190303.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.39 190308[121:Res:53.1,190305.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.39 190310[122:Spt:190308.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.39 190312[122:Res:190310.0,61.1] always3(s27) || -> . % 76.16/76.39 190313[122:SSi:190312.0,78187.0,78190.0,165519.0,189831.0,190303.0] || -> . % 76.16/76.39 190314[122:Spt:190313.0,190308.0,190310.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.39 190315[122:Spt:190313.0,190308.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.39 190319[122:Res:190315.0,61.1] always3(s28) || -> . % 76.16/76.39 190320[122:SSi:190319.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.39 190321[120:Spt:190320.0,189830.0,189831.0] || until2p7(s27)*+ -> . % 76.16/76.39 190322[120:Spt:190320.0,189830.1] || -> node4(s26)*. % 76.16/76.39 190324[120:MRR:840.0,190322.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.39 190327[120:Res:53.1,190324.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.39 190332[121:Spt:190327.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.39 190334[121:Res:190332.0,61.1] always3(s26) || -> . % 76.16/76.39 190335[121:SSi:190334.0,78182.0,78186.0,165518.0,189829.0,190322.0] || -> . % 76.16/76.39 190336[121:Spt:190335.0,190327.0,190332.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.39 190337[121:Spt:190335.0,190327.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.39 190341[121:Res:190337.0,61.1] always3(s27) || -> . % 76.16/76.39 190342[121:SSi:190341.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.39 190343[119:Spt:190342.0,189828.0,189829.0] || until2p7(s26)*+ -> . % 76.16/76.39 190344[119:Spt:190342.0,189828.1] || -> node4(s25)*. % 76.16/76.39 190346[119:MRR:843.0,190344.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.39 190349[119:Res:53.1,190346.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.39 190351[120:Spt:190349.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.39 190353[120:Res:190351.0,61.1] always3(s25) || -> . % 76.16/76.39 190354[120:SSi:190353.0,78178.0,78181.0,165517.0,189827.0,190344.0] || -> . % 76.16/76.39 190355[120:Spt:190354.0,190349.0,190351.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.39 190356[120:Spt:190354.0,190349.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.39 190360[120:Res:190356.0,61.1] always3(s26) || -> . % 76.16/76.39 190361[120:SSi:190360.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.39 190362[118:Spt:190361.0,189826.0,189827.0] || until2p7(s25)*+ -> . % 76.16/76.39 190363[118:Spt:190361.0,189826.1] || -> node4(s24)*. % 76.16/76.39 190365[118:MRR:846.0,190363.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.39 190368[118:Res:53.1,190365.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.39 190370[119:Spt:190368.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.39 190372[119:Res:190370.0,61.1] always3(s24) || -> . % 76.16/76.39 190373[119:SSi:190372.0,78173.0,78177.0,165516.0,189825.0,190363.0] || -> . % 76.16/76.39 190374[119:Spt:190373.0,190368.0,190370.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.39 190375[119:Spt:190373.0,190368.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.39 190379[119:Res:190375.0,61.1] always3(s25) || -> . % 76.16/76.39 190380[119:SSi:190379.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.39 190381[117:Spt:190380.0,189824.0,189825.0] || until2p7(s24)*+ -> . % 76.16/76.39 190382[117:Spt:190380.0,189824.1] || -> node4(s23)*. % 76.16/76.39 190384[117:MRR:849.0,190382.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.39 190387[117:Res:53.1,190384.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.39 190389[118:Spt:190387.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.39 190391[118:Res:190389.0,61.1] always3(s23) || -> . % 76.16/76.39 190392[118:SSi:190391.0,78169.0,78172.0,165515.0,189823.0,190382.0] || -> . % 76.16/76.39 190393[118:Spt:190392.0,190387.0,190389.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.39 190394[118:Spt:190392.0,190387.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.39 190398[118:Res:190394.0,61.1] always3(s24) || -> . % 76.16/76.39 190399[118:SSi:190398.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.39 190400[116:Spt:190399.0,189822.0,189823.0] || until2p7(s23)*+ -> . % 76.16/76.39 190401[116:Spt:190399.0,189822.1] || -> node4(s22)*. % 76.16/76.39 190403[116:MRR:852.0,190401.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.39 190406[116:Res:53.1,190403.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.39 190411[117:Spt:190406.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.39 190413[117:Res:190411.0,61.1] always3(s22) || -> . % 76.16/76.39 190414[117:SSi:190413.0,78164.0,78168.0,165514.0,189821.0,190401.0] || -> . % 76.16/76.39 190415[117:Spt:190414.0,190406.0,190411.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.39 190416[117:Spt:190414.0,190406.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.39 190420[117:Res:190416.0,61.1] always3(s23) || -> . % 76.16/76.39 190421[117:SSi:190420.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.39 190422[115:Spt:190421.0,189820.0,189821.0] || until2p7(s22)*+ -> . % 76.16/76.39 190423[115:Spt:190421.0,189820.1] || -> node4(s21)*. % 76.16/76.39 190425[115:MRR:855.0,190423.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.39 190428[115:Res:53.1,190425.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.39 190430[116:Spt:190428.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.39 190432[116:Res:190430.0,61.1] always3(s21) || -> . % 76.16/76.39 190433[116:SSi:190432.0,78160.0,78163.0,165513.0,189819.0,190423.0] || -> . % 76.16/76.39 190434[116:Spt:190433.0,190428.0,190430.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.39 190435[116:Spt:190433.0,190428.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.39 190439[116:Res:190435.0,61.1] always3(s22) || -> . % 76.16/76.39 190440[116:SSi:190439.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.39 190441[114:Spt:190440.0,189818.0,189819.0] || until2p7(s21)*+ -> . % 76.16/76.39 190442[114:Spt:190440.0,189818.1] || -> node4(s20)*. % 76.16/76.39 190444[114:MRR:858.0,190442.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.39 190447[114:Res:53.1,190444.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.39 190449[115:Spt:190447.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.39 190451[115:Res:190449.0,61.1] always3(s20) || -> . % 76.16/76.39 190452[115:SSi:190451.0,78155.0,78159.0,165512.0,189817.0,190442.0] || -> . % 76.16/76.39 190453[115:Spt:190452.0,190447.0,190449.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.39 190454[115:Spt:190452.0,190447.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.39 190458[115:Res:190454.0,61.1] always3(s21) || -> . % 76.16/76.39 190459[115:SSi:190458.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.39 190460[113:Spt:190459.0,189816.0,189817.0] || until2p7(s20)*+ -> . % 76.16/76.39 190461[113:Spt:190459.0,189816.1] || -> node4(s19)*. % 76.16/76.39 190463[113:MRR:861.0,190461.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.39 190466[113:Res:53.1,190463.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.39 190468[114:Spt:190466.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.39 190470[114:Res:190468.0,61.1] always3(s19) || -> . % 76.16/76.39 190471[114:SSi:190470.0,78151.0,78154.0,165511.0,189815.0,190461.0] || -> . % 76.16/76.39 190472[114:Spt:190471.0,190466.0,190468.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.39 190473[114:Spt:190471.0,190466.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.39 190477[114:Res:190473.0,61.1] always3(s20) || -> . % 76.16/76.39 190478[114:SSi:190477.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.39 190479[112:Spt:190478.0,189814.0,189815.0] || until2p7(s19)*+ -> . % 76.16/76.39 190480[112:Spt:190478.0,189814.1] || -> node4(s18)*. % 76.16/76.39 190482[112:MRR:864.0,190480.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.39 190485[112:Res:53.1,190482.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.39 190490[113:Spt:190485.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.39 190492[113:Res:190490.0,61.1] always3(s18) || -> . % 76.16/76.39 190493[113:SSi:190492.0,78146.0,78150.0,165510.0,189813.0,190480.0] || -> . % 76.16/76.39 190494[113:Spt:190493.0,190485.0,190490.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.39 190495[113:Spt:190493.0,190485.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.39 190499[113:Res:190495.0,61.1] always3(s19) || -> . % 76.16/76.39 190500[113:SSi:190499.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.39 190501[111:Spt:190500.0,189812.0,189813.0] || until2p7(s18)*+ -> . % 76.16/76.39 190502[111:Spt:190500.0,189812.1] || -> node4(s17)*. % 76.16/76.39 190504[111:MRR:867.0,190502.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.39 190507[111:Res:53.1,190504.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.39 190509[112:Spt:190507.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.39 190511[112:Res:190509.0,61.1] always3(s17) || -> . % 76.16/76.39 190512[112:SSi:190511.0,78142.0,78145.0,165509.0,189811.0,190502.0] || -> . % 76.16/76.39 190513[112:Spt:190512.0,190507.0,190509.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.39 190514[112:Spt:190512.0,190507.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.39 190518[112:Res:190514.0,61.1] always3(s18) || -> . % 76.16/76.39 190519[112:SSi:190518.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.39 190520[110:Spt:190519.0,189810.0,189811.0] || until2p7(s17)*+ -> . % 76.16/76.39 190521[110:Spt:190519.0,189810.1] || -> node4(s16)*. % 76.16/76.39 190523[110:MRR:870.0,190521.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.39 190526[110:Res:53.1,190523.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.39 190528[111:Spt:190526.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.39 190530[111:Res:190528.0,61.1] always3(s16) || -> . % 76.16/76.39 190531[111:SSi:190530.0,78137.0,78141.0,165508.0,189809.0,190521.0] || -> . % 76.16/76.39 190532[111:Spt:190531.0,190526.0,190528.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.39 190533[111:Spt:190531.0,190526.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.39 190537[111:Res:190533.0,61.1] always3(s17) || -> . % 76.16/76.39 190538[111:SSi:190537.0,78142.0,78145.0,165509.0] || -> . % 76.16/76.39 190539[109:Spt:190538.0,189808.0,189809.0] || until2p7(s16)*+ -> . % 76.16/76.39 190540[109:Spt:190538.0,189808.1] || -> node4(s15)*. % 76.16/76.39 190542[109:MRR:873.0,190540.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.39 190545[109:Res:53.1,190542.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.39 190547[110:Spt:190545.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.39 190549[110:Res:190547.0,61.1] always3(s15) || -> . % 76.16/76.39 190550[110:SSi:190549.0,78133.0,78136.0,165507.0,189807.0,190540.0] || -> . % 76.16/76.39 190551[110:Spt:190550.0,190545.0,190547.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.39 190552[110:Spt:190550.0,190545.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.39 190556[110:Res:190552.0,61.1] always3(s16) || -> . % 76.16/76.39 190557[110:SSi:190556.0,78137.0,78141.0,165508.0] || -> . % 76.16/76.39 190558[108:Spt:190557.0,189806.0,189807.0] || until2p7(s15)*+ -> . % 76.16/76.39 190559[108:Spt:190557.0,189806.1] || -> node4(s14)*. % 76.16/76.39 190561[108:MRR:876.0,190559.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.39 190564[108:Res:53.1,190561.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.39 190569[109:Spt:190564.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.39 190571[109:Res:190569.0,61.1] always3(s14) || -> . % 76.16/76.39 190572[109:SSi:190571.0,78128.0,78132.0,165506.0,189805.0,190559.0] || -> . % 76.16/76.39 190573[109:Spt:190572.0,190564.0,190569.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.39 190574[109:Spt:190572.0,190564.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.39 190578[109:Res:190574.0,61.1] always3(s15) || -> . % 76.16/76.39 190579[109:SSi:190578.0,78133.0,78136.0,165507.0] || -> . % 76.16/76.39 190580[107:Spt:190579.0,189804.0,189805.0] || until2p7(s14)*+ -> . % 76.16/76.39 190581[107:Spt:190579.0,189804.1] || -> node4(s13)*. % 76.16/76.39 190583[107:MRR:879.0,190581.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.39 190586[107:Res:53.1,190583.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.39 190588[108:Spt:190586.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.39 190590[108:Res:190588.0,61.1] always3(s13) || -> . % 76.16/76.39 190591[108:SSi:190590.0,78124.0,78127.0,165505.0,189803.0,190581.0] || -> . % 76.16/76.39 190592[108:Spt:190591.0,190586.0,190588.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.39 190593[108:Spt:190591.0,190586.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.39 190597[108:Res:190593.0,61.1] always3(s14) || -> . % 76.16/76.39 190598[108:SSi:190597.0,78128.0,78132.0,165506.0] || -> . % 76.16/76.39 190599[106:Spt:190598.0,189802.0,189803.0] || until2p7(s13)*+ -> . % 76.16/76.39 190600[106:Spt:190598.0,189802.1] || -> node4(s12)*. % 76.16/76.39 190602[106:MRR:882.0,190600.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.39 190605[106:Res:53.1,190602.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.39 190607[107:Spt:190605.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.39 190609[107:Res:190607.0,61.1] always3(s12) || -> . % 76.16/76.39 190610[107:SSi:190609.0,78119.0,78123.0,165504.0,189801.0,190600.0] || -> . % 76.16/76.39 190611[107:Spt:190610.0,190605.0,190607.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.39 190612[107:Spt:190610.0,190605.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.39 190616[107:Res:190612.0,61.1] always3(s13) || -> . % 76.16/76.39 190617[107:SSi:190616.0,78124.0,78127.0,165505.0] || -> . % 76.16/76.39 190618[105:Spt:190617.0,189800.0,189801.0] || until2p7(s12)*+ -> . % 76.16/76.39 190619[105:Spt:190617.0,189800.1] || -> node4(s11)*. % 76.16/76.39 190621[105:MRR:885.0,190619.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.39 190624[105:Res:53.1,190621.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.39 190626[106:Spt:190624.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.39 190628[106:Res:190626.0,61.1] always3(s11) || -> . % 76.16/76.39 190629[106:SSi:190628.0,78115.0,78118.0,165503.0,189799.0,190619.0] || -> . % 76.16/76.39 190630[106:Spt:190629.0,190624.0,190626.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.39 190631[106:Spt:190629.0,190624.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.39 190635[106:Res:190631.0,61.1] always3(s12) || -> . % 76.16/76.39 190636[106:SSi:190635.0,78119.0,78123.0,165504.0] || -> . % 76.16/76.39 190637[104:Spt:190636.0,189798.0,189799.0] || until2p7(s11)*+ -> . % 76.16/76.39 190638[104:Spt:190636.0,189798.1] || -> node4(s10)*. % 76.16/76.39 190640[104:MRR:888.0,190638.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.39 190643[104:Res:53.1,190640.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.39 190648[105:Spt:190643.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.39 190650[105:Res:190648.0,61.1] always3(s10) || -> . % 76.16/76.39 190651[105:SSi:190650.0,78110.0,78114.0,165502.0,189797.0,190638.0] || -> . % 76.16/76.39 190652[105:Spt:190651.0,190643.0,190648.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.39 190653[105:Spt:190651.0,190643.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.39 190657[105:Res:190653.0,61.1] always3(s11) || -> . % 76.16/76.39 190658[105:SSi:190657.0,78115.0,78118.0,165503.0] || -> . % 76.16/76.39 190659[103:Spt:190658.0,189796.0,189797.0] || until2p7(s10)*+ -> . % 76.16/76.39 190660[103:Spt:190658.0,189796.1] || -> node4(s9)*. % 76.16/76.39 190662[103:MRR:891.0,190660.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.39 190665[103:Res:53.1,190662.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.39 190667[104:Spt:190665.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.39 190669[104:Res:190667.0,61.1] always3(s9) || -> . % 76.16/76.39 190670[104:SSi:190669.0,78106.0,78109.0,165501.0,189795.0,190660.0] || -> . % 76.16/76.39 190671[104:Spt:190670.0,190665.0,190667.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.39 190672[104:Spt:190670.0,190665.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.39 190676[104:Res:190672.0,61.1] always3(s10) || -> . % 76.16/76.39 190677[104:SSi:190676.0,78110.0,78114.0,165502.0] || -> . % 76.16/76.39 190678[102:Spt:190677.0,189794.0,189795.0] || until2p7(s9)*+ -> . % 76.16/76.39 190679[102:Spt:190677.0,189794.1] || -> node4(s8)*. % 76.16/76.39 190681[102:MRR:894.0,190679.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.39 190684[102:Res:53.1,190681.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.39 190686[103:Spt:190684.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.39 190688[103:Res:190686.0,61.1] always3(s8) || -> . % 76.16/76.39 190689[103:SSi:190688.0,78101.0,78105.0,165500.0,189793.0,190679.0] || -> . % 76.16/76.39 190690[103:Spt:190689.0,190684.0,190686.0] || m_main_v_state(s8,c_busy)* -> . % 76.16/76.39 190691[103:Spt:190689.0,190684.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.39 190695[103:Res:190691.0,61.1] always3(s9) || -> . % 76.16/76.39 190696[103:SSi:190695.0,78106.0,78109.0,165501.0] || -> . % 76.16/76.39 190697[101:Spt:190696.0,189792.0,189793.0] || until2p7(s8)*+ -> . % 76.16/76.39 190698[101:Spt:190696.0,189792.1] || -> node4(s7)*. % 76.16/76.39 190700[101:MRR:897.0,190698.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.16/76.39 190703[101:Res:53.1,190700.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.16/76.39 190705[102:Spt:190703.0] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.39 190707[102:Res:190705.0,61.1] always3(s7) || -> . % 76.16/76.39 190708[102:SSi:190707.0,78097.0,78100.0,165499.0,189791.0,190698.0] || -> . % 76.16/76.39 190709[102:Spt:190708.0,190703.0,190705.0] || m_main_v_state(s7,c_busy)* -> . % 76.16/76.39 190710[102:Spt:190708.0,190703.1] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.39 190714[102:Res:190710.0,61.1] always3(s8) || -> . % 76.16/76.39 190715[102:SSi:190714.0,78101.0,78105.0,165500.0] || -> . % 76.16/76.39 190716[100:Spt:190715.0,189790.0,189791.0] || until2p7(s7)*+ -> . % 76.16/76.39 190717[100:Spt:190715.0,189790.1] || -> node4(s6)*. % 76.16/76.39 190719[100:MRR:900.0,190717.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.16/76.39 190722[100:Res:53.1,190719.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.16/76.39 190724[100:MRR:190722.0,189780.0] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.39 190729[100:Res:190724.0,61.1] always3(s7) || -> . % 76.16/76.39 190730[100:SSi:190729.0,78097.0,78100.0,165499.0] || -> . % 76.16/76.39 190731[98:Spt:190730.0,189622.0,189625.0] || trans(s49,s6)*+ -> . % 76.16/76.39 190732[98:Spt:190730.0,189622.1] || -> node2(s49,s5)*. % 76.16/76.39 190734[98:MRR:189624.1,190731.0] xuntil6(s49) || -> until2p7(s5)*. % 76.16/76.39 190735[98:Res:190732.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)*. % 76.16/76.39 190884[98:SoR:190735.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)*. % 76.16/76.39 190886[98:SoR:190884.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s5,c_busy)* xuntil6(s49). % 76.16/76.39 190887[98:SSi:190886.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s5,c_busy)* xuntil6(s49). % 76.16/76.39 190888[99:Spt:190887.1] || -> m_main_v_state(s5,c_busy)*. % 76.16/76.39 190890[99:Res:190888.0,61.1] always3(s5) || -> . % 76.16/76.39 190891[99:SSi:190890.0,78089.0,78092.0,165497.0] || -> . % 76.16/76.39 190892[99:Spt:190891.0,190887.1,190888.0] || m_main_v_state(s5,c_busy)*+ -> . % 76.16/76.39 190893[99:Spt:190891.0,190887.0,190887.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 190896[99:MRR:190884.2,190892.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 190897[99:Res:53.1,190893.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 190899[99:MRR:190897.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 190900[99:MRR:190734.0,190899.0] || -> until2p7(s5)*. % 76.16/76.39 190901[99:MRR:201.0,190900.0] || -> until2p7(s6)* node4(s5). % 76.16/76.39 190902[100:Spt:190901.0] || -> until2p7(s6)*. % 76.16/76.39 190903[100:MRR:202.0,190902.0] || -> until2p7(s7)* node4(s6). % 76.16/76.39 190904[101:Spt:190903.0] || -> until2p7(s7)*. % 76.16/76.39 190905[101:MRR:203.0,190904.0] || -> until2p7(s8)* node4(s7). % 76.16/76.39 190906[102:Spt:190905.0] || -> until2p7(s8)*. % 76.16/76.39 190907[102:MRR:204.0,190906.0] || -> until2p7(s9)* node4(s8). % 76.16/76.39 190908[103:Spt:190907.0] || -> until2p7(s9)*. % 76.16/76.39 190909[103:MRR:205.0,190908.0] || -> until2p7(s10)* node4(s9). % 76.16/76.39 190910[104:Spt:190909.0] || -> until2p7(s10)*. % 76.16/76.39 190911[104:MRR:206.0,190910.0] || -> until2p7(s11)* node4(s10). % 76.16/76.39 190912[105:Spt:190911.0] || -> until2p7(s11)*. % 76.16/76.39 190913[105:MRR:207.0,190912.0] || -> until2p7(s12)* node4(s11). % 76.16/76.39 190914[106:Spt:190913.0] || -> until2p7(s12)*. % 76.16/76.39 190915[106:MRR:208.0,190914.0] || -> until2p7(s13)* node4(s12). % 76.16/76.39 190916[107:Spt:190915.0] || -> until2p7(s13)*. % 76.16/76.39 190917[107:MRR:209.0,190916.0] || -> until2p7(s14)* node4(s13). % 76.16/76.39 190918[108:Spt:190917.0] || -> until2p7(s14)*. % 76.16/76.39 190919[108:MRR:210.0,190918.0] || -> until2p7(s15)* node4(s14). % 76.16/76.39 190920[109:Spt:190919.0] || -> until2p7(s15)*. % 76.16/76.39 190921[109:MRR:211.0,190920.0] || -> until2p7(s16)* node4(s15). % 76.16/76.39 190922[110:Spt:190921.0] || -> until2p7(s16)*. % 76.16/76.39 190923[110:MRR:212.0,190922.0] || -> until2p7(s17)* node4(s16). % 76.16/76.39 190924[111:Spt:190923.0] || -> until2p7(s17)*. % 76.16/76.39 190925[111:MRR:213.0,190924.0] || -> until2p7(s18)* node4(s17). % 76.16/76.39 190926[112:Spt:190925.0] || -> until2p7(s18)*. % 76.16/76.39 190927[112:MRR:214.0,190926.0] || -> until2p7(s19)* node4(s18). % 76.16/76.39 190928[113:Spt:190927.0] || -> until2p7(s19)*. % 76.16/76.39 190929[113:MRR:215.0,190928.0] || -> until2p7(s20)* node4(s19). % 76.16/76.39 190930[114:Spt:190929.0] || -> until2p7(s20)*. % 76.16/76.39 190931[114:MRR:216.0,190930.0] || -> until2p7(s21)* node4(s20). % 76.16/76.39 190932[115:Spt:190931.0] || -> until2p7(s21)*. % 76.16/76.39 190933[115:MRR:217.0,190932.0] || -> until2p7(s22)* node4(s21). % 76.16/76.39 190934[116:Spt:190933.0] || -> until2p7(s22)*. % 76.16/76.39 190935[116:MRR:218.0,190934.0] || -> until2p7(s23)* node4(s22). % 76.16/76.39 190936[117:Spt:190935.0] || -> until2p7(s23)*. % 76.16/76.39 190937[117:MRR:219.0,190936.0] || -> until2p7(s24)* node4(s23). % 76.16/76.39 190938[118:Spt:190937.0] || -> until2p7(s24)*. % 76.16/76.39 190939[118:MRR:220.0,190938.0] || -> until2p7(s25)* node4(s24). % 76.16/76.39 190940[119:Spt:190939.0] || -> until2p7(s25)*. % 76.16/76.39 190941[119:MRR:221.0,190940.0] || -> until2p7(s26)* node4(s25). % 76.16/76.39 190942[120:Spt:190941.0] || -> until2p7(s26)*. % 76.16/76.39 190943[120:MRR:222.0,190942.0] || -> until2p7(s27)* node4(s26). % 76.16/76.39 190944[121:Spt:190943.0] || -> until2p7(s27)*. % 76.16/76.39 190945[121:MRR:223.0,190944.0] || -> until2p7(s28)* node4(s27). % 76.16/76.39 190946[122:Spt:190945.0] || -> until2p7(s28)*. % 76.16/76.39 190947[122:MRR:224.0,190946.0] || -> until2p7(s29)* node4(s28). % 76.16/76.39 190948[123:Spt:190947.0] || -> until2p7(s29)*. % 76.16/76.39 190949[123:MRR:225.0,190948.0] || -> until2p7(s30)* node4(s29). % 76.16/76.39 190950[124:Spt:190949.0] || -> until2p7(s30)*. % 76.16/76.39 190951[124:MRR:226.0,190950.0] || -> until2p7(s31)* node4(s30). % 76.16/76.39 190952[125:Spt:190951.0] || -> until2p7(s31)*. % 76.16/76.39 190953[125:MRR:227.0,190952.0] || -> until2p7(s32)* node4(s31). % 76.16/76.39 190954[126:Spt:190953.0] || -> until2p7(s32)*. % 76.16/76.39 190955[126:MRR:228.0,190954.0] || -> until2p7(s33)* node4(s32). % 76.16/76.39 190956[127:Spt:190955.0] || -> until2p7(s33)*. % 76.16/76.39 190957[127:MRR:229.0,190956.0] || -> until2p7(s34)* node4(s33). % 76.16/76.39 190958[128:Spt:190957.0] || -> until2p7(s34)*. % 76.16/76.39 190959[128:MRR:230.0,190958.0] || -> until2p7(s35)* node4(s34). % 76.16/76.39 190960[129:Spt:190959.0] || -> until2p7(s35)*. % 76.16/76.39 190961[129:MRR:231.0,190960.0] || -> until2p7(s36)* node4(s35). % 76.16/76.39 190962[130:Spt:190961.0] || -> until2p7(s36)*. % 76.16/76.39 190963[130:MRR:232.0,190962.0] || -> until2p7(s37)* node4(s36). % 76.16/76.39 190964[131:Spt:190963.0] || -> until2p7(s37)*. % 76.16/76.39 190965[131:MRR:235.0,190964.0] || -> until2p7(s38)* node4(s37). % 76.16/76.39 190966[132:Spt:190965.0] || -> until2p7(s38)*. % 76.16/76.39 190967[132:MRR:236.0,190966.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 190968[133:Spt:190967.0] || -> until2p7(s39)*. % 76.16/76.39 190969[133:MRR:237.0,190968.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 190970[134:Spt:190969.0] || -> until2p7(s40)*. % 76.16/76.39 190971[134:MRR:238.0,190970.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 190972[135:Spt:190971.0] || -> until2p7(s41)*. % 76.16/76.39 190973[135:MRR:239.0,190972.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 190974[136:Spt:190973.0] || -> until2p7(s42)*. % 76.16/76.39 190975[136:MRR:240.0,190974.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 190976[137:Spt:190975.0] || -> until2p7(s43)*. % 76.16/76.39 190977[137:MRR:241.0,190976.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 190978[138:Spt:190977.0] || -> until2p7(s44)*. % 76.16/76.39 190979[138:MRR:539.0,190978.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 190980[139:Spt:190979.0] || -> until2p7(s45)*. % 76.16/76.39 190981[139:MRR:544.0,190980.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 190982[140:Spt:190981.0] || -> until2p7(s46)*. % 76.16/76.39 190983[140:MRR:549.0,190982.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 190984[141:Spt:190983.0] || -> until2p7(s47)*. % 76.16/76.39 190985[141:MRR:554.0,190984.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 190986[142:Spt:190985.0] || -> until2p7(s48)*. % 76.16/76.39 190987[142:MRR:559.0,190986.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 190988[143:Spt:190987.0] || -> until2p7(s49)*. % 76.16/76.39 190989[143:MRR:194.0,190988.0] || -> node4(s49)*. % 76.16/76.39 190990[143:MRR:190896.0,190989.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 190991[143:Res:53.1,190990.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 190993[143:MRR:190991.0,78381.0] || -> . % 76.16/76.39 190994[143:Spt:190993.0,190987.0,190988.0] || until2p7(s49)*+ -> . % 76.16/76.39 190995[143:Spt:190993.0,190987.1] || -> node4(s48)*. % 76.16/76.39 190996[143:MRR:78384.0,190995.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 190999[143:Res:53.1,190996.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 191002[143:Res:190999.0,61.1] always3(s48) || -> . % 76.16/76.39 191003[143:SSi:191002.0,78281.0,78387.0,165540.0,190986.0,190995.0] || -> . % 76.16/76.39 191004[142:Spt:191003.0,190985.0,190986.0] || until2p7(s48)*+ -> . % 76.16/76.39 191005[142:Spt:191003.0,190985.1] || -> node4(s47)*. % 76.16/76.39 191007[142:MRR:777.0,191005.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 191021[142:Res:53.1,191007.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 191023[143:Spt:191021.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 191025[143:Res:191023.0,61.1] always3(s47) || -> . % 76.16/76.39 191026[143:SSi:191025.0,78277.0,78280.0,165539.0,190984.0,191005.0] || -> . % 76.16/76.39 191027[143:Spt:191026.0,191021.0,191023.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 191028[143:Spt:191026.0,191021.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 191032[143:Res:191028.0,61.1] always3(s48) || -> . % 76.16/76.39 191033[143:SSi:191032.0,78281.0,78387.0,165540.0] || -> . % 76.16/76.39 191034[141:Spt:191033.0,190983.0,190984.0] || until2p7(s47)*+ -> . % 76.16/76.39 191035[141:Spt:191033.0,190983.1] || -> node4(s46)*. % 76.16/76.39 191037[141:MRR:780.0,191035.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 191044[141:Res:53.1,191037.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 191049[142:Spt:191044.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 191051[142:Res:191049.0,61.1] always3(s46) || -> . % 76.16/76.39 191052[142:SSi:191051.0,78272.0,78276.0,165538.0,190982.0,191035.0] || -> . % 76.16/76.39 191053[142:Spt:191052.0,191044.0,191049.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 191054[142:Spt:191052.0,191044.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 191058[142:Res:191054.0,61.1] always3(s47) || -> . % 76.16/76.39 191059[142:SSi:191058.0,78277.0,78280.0,165539.0] || -> . % 76.16/76.39 191060[140:Spt:191059.0,190981.0,190982.0] || until2p7(s46)*+ -> . % 76.16/76.39 191061[140:Spt:191059.0,190981.1] || -> node4(s45)*. % 76.16/76.39 191063[140:MRR:783.0,191061.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 191066[140:Res:53.1,191063.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 191068[141:Spt:191066.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 191070[141:Res:191068.0,61.1] always3(s45) || -> . % 76.16/76.39 191071[141:SSi:191070.0,78268.0,78271.0,165537.0,190980.0,191061.0] || -> . % 76.16/76.39 191072[141:Spt:191071.0,191066.0,191068.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 191073[141:Spt:191071.0,191066.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 191077[141:Res:191073.0,61.1] always3(s46) || -> . % 76.16/76.39 191078[141:SSi:191077.0,78272.0,78276.0,165538.0] || -> . % 76.16/76.39 191079[139:Spt:191078.0,190979.0,190980.0] || until2p7(s45)*+ -> . % 76.16/76.39 191080[139:Spt:191078.0,190979.1] || -> node4(s44)*. % 76.16/76.39 191082[139:MRR:786.0,191080.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 191085[139:Res:53.1,191082.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 191087[140:Spt:191085.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 191089[140:Res:191087.0,61.1] always3(s44) || -> . % 76.16/76.39 191090[140:SSi:191089.0,78263.0,78267.0,165536.0,190978.0,191080.0] || -> . % 76.16/76.39 191091[140:Spt:191090.0,191085.0,191087.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 191092[140:Spt:191090.0,191085.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 191096[140:Res:191092.0,61.1] always3(s45) || -> . % 76.16/76.39 191097[140:SSi:191096.0,78268.0,78271.0,165537.0] || -> . % 76.16/76.39 191098[138:Spt:191097.0,190977.0,190978.0] || until2p7(s44)*+ -> . % 76.16/76.39 191099[138:Spt:191097.0,190977.1] || -> node4(s43)*. % 76.16/76.39 191101[138:MRR:789.0,191099.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 191104[138:Res:53.1,191101.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 191106[139:Spt:191104.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 191108[139:Res:191106.0,61.1] always3(s43) || -> . % 76.16/76.39 191109[139:SSi:191108.0,78259.0,78262.0,165535.0,190976.0,191099.0] || -> . % 76.16/76.39 191110[139:Spt:191109.0,191104.0,191106.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 191111[139:Spt:191109.0,191104.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 191115[139:Res:191111.0,61.1] always3(s44) || -> . % 76.16/76.39 191116[139:SSi:191115.0,78263.0,78267.0,165536.0] || -> . % 76.16/76.39 191117[137:Spt:191116.0,190975.0,190976.0] || until2p7(s43)*+ -> . % 76.16/76.39 191118[137:Spt:191116.0,190975.1] || -> node4(s42)*. % 76.16/76.39 191120[137:MRR:792.0,191118.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 191123[137:Res:53.1,191120.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 191128[138:Spt:191123.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 191130[138:Res:191128.0,61.1] always3(s42) || -> . % 76.16/76.39 191131[138:SSi:191130.0,78254.0,78258.0,165534.0,190974.0,191118.0] || -> . % 76.16/76.39 191132[138:Spt:191131.0,191123.0,191128.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 191133[138:Spt:191131.0,191123.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 191137[138:Res:191133.0,61.1] always3(s43) || -> . % 76.16/76.39 191138[138:SSi:191137.0,78259.0,78262.0,165535.0] || -> . % 76.16/76.39 191139[136:Spt:191138.0,190973.0,190974.0] || until2p7(s42)*+ -> . % 76.16/76.39 191140[136:Spt:191138.0,190973.1] || -> node4(s41)*. % 76.16/76.39 191142[136:MRR:795.0,191140.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 191145[136:Res:53.1,191142.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 191147[137:Spt:191145.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 191149[137:Res:191147.0,61.1] always3(s41) || -> . % 76.16/76.39 191150[137:SSi:191149.0,78250.0,78253.0,165533.0,190972.0,191140.0] || -> . % 76.16/76.39 191151[137:Spt:191150.0,191145.0,191147.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 191152[137:Spt:191150.0,191145.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 191156[137:Res:191152.0,61.1] always3(s42) || -> . % 76.16/76.39 191157[137:SSi:191156.0,78254.0,78258.0,165534.0] || -> . % 76.16/76.39 191158[135:Spt:191157.0,190971.0,190972.0] || until2p7(s41)*+ -> . % 76.16/76.39 191159[135:Spt:191157.0,190971.1] || -> node4(s40)*. % 76.16/76.39 191161[135:MRR:798.0,191159.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 191164[135:Res:53.1,191161.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 191166[136:Spt:191164.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 191168[136:Res:191166.0,61.1] always3(s40) || -> . % 76.16/76.39 191169[136:SSi:191168.0,78245.0,78249.0,165532.0,190970.0,191159.0] || -> . % 76.16/76.39 191170[136:Spt:191169.0,191164.0,191166.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 191171[136:Spt:191169.0,191164.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 191175[136:Res:191171.0,61.1] always3(s41) || -> . % 76.16/76.39 191176[136:SSi:191175.0,78250.0,78253.0,165533.0] || -> . % 76.16/76.39 191177[134:Spt:191176.0,190969.0,190970.0] || until2p7(s40)*+ -> . % 76.16/76.39 191178[134:Spt:191176.0,190969.1] || -> node4(s39)*. % 76.16/76.39 191180[134:MRR:801.0,191178.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 191183[134:Res:53.1,191180.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 191185[135:Spt:191183.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 191187[135:Res:191185.0,61.1] always3(s39) || -> . % 76.16/76.39 191188[135:SSi:191187.0,78241.0,78244.0,165531.0,190968.0,191178.0] || -> . % 76.16/76.39 191189[135:Spt:191188.0,191183.0,191185.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 191190[135:Spt:191188.0,191183.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 191194[135:Res:191190.0,61.1] always3(s40) || -> . % 76.16/76.39 191195[135:SSi:191194.0,78245.0,78249.0,165532.0] || -> . % 76.16/76.39 191196[133:Spt:191195.0,190967.0,190968.0] || until2p7(s39)*+ -> . % 76.16/76.39 191197[133:Spt:191195.0,190967.1] || -> node4(s38)*. % 76.16/76.39 191199[133:MRR:804.0,191197.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 191202[133:Res:53.1,191199.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 191207[134:Spt:191202.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 191209[134:Res:191207.0,61.1] always3(s38) || -> . % 76.16/76.39 191210[134:SSi:191209.0,78236.0,78240.0,165530.0,190966.0,191197.0] || -> . % 76.16/76.39 191211[134:Spt:191210.0,191202.0,191207.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 191212[134:Spt:191210.0,191202.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 191216[134:Res:191212.0,61.1] always3(s39) || -> . % 76.16/76.39 191217[134:SSi:191216.0,78241.0,78244.0,165531.0] || -> . % 76.16/76.39 191218[132:Spt:191217.0,190965.0,190966.0] || until2p7(s38)*+ -> . % 76.16/76.39 191219[132:Spt:191217.0,190965.1] || -> node4(s37)*. % 76.16/76.39 191221[132:MRR:807.0,191219.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 191224[132:Res:53.1,191221.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 191226[133:Spt:191224.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 191228[133:Res:191226.0,61.1] always3(s37) || -> . % 76.16/76.39 191229[133:SSi:191228.0,78232.0,78235.0,165529.0,190964.0,191219.0] || -> . % 76.16/76.39 191230[133:Spt:191229.0,191224.0,191226.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.39 191231[133:Spt:191229.0,191224.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 191235[133:Res:191231.0,61.1] always3(s38) || -> . % 76.16/76.39 191236[133:SSi:191235.0,78236.0,78240.0,165530.0] || -> . % 76.16/76.39 191237[131:Spt:191236.0,190963.0,190964.0] || until2p7(s37)*+ -> . % 76.16/76.39 191238[131:Spt:191236.0,190963.1] || -> node4(s36)*. % 76.16/76.39 191240[131:MRR:810.0,191238.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.39 191243[131:Res:53.1,191240.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.39 191245[132:Spt:191243.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 191247[132:Res:191245.0,61.1] always3(s36) || -> . % 76.16/76.39 191248[132:SSi:191247.0,78227.0,78231.0,165528.0,190962.0,191238.0] || -> . % 76.16/76.39 191249[132:Spt:191248.0,191243.0,191245.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.39 191250[132:Spt:191248.0,191243.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 191254[132:Res:191250.0,61.1] always3(s37) || -> . % 76.16/76.39 191255[132:SSi:191254.0,78232.0,78235.0,165529.0] || -> . % 76.16/76.39 191256[130:Spt:191255.0,190961.0,190962.0] || until2p7(s36)*+ -> . % 76.16/76.39 191257[130:Spt:191255.0,190961.1] || -> node4(s35)*. % 76.16/76.39 191259[130:MRR:813.0,191257.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.39 191262[130:Res:53.1,191259.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.39 191264[131:Spt:191262.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 191266[131:Res:191264.0,61.1] always3(s35) || -> . % 76.16/76.39 191267[131:SSi:191266.0,78223.0,78226.0,165527.0,190960.0,191257.0] || -> . % 76.16/76.39 191268[131:Spt:191267.0,191262.0,191264.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.39 191269[131:Spt:191267.0,191262.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 191273[131:Res:191269.0,61.1] always3(s36) || -> . % 76.16/76.39 191274[131:SSi:191273.0,78227.0,78231.0,165528.0] || -> . % 76.16/76.39 191275[129:Spt:191274.0,190959.0,190960.0] || until2p7(s35)*+ -> . % 76.16/76.39 191276[129:Spt:191274.0,190959.1] || -> node4(s34)*. % 76.16/76.39 191278[129:MRR:816.0,191276.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.39 191281[129:Res:53.1,191278.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.39 191286[130:Spt:191281.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 191288[130:Res:191286.0,61.1] always3(s34) || -> . % 76.16/76.39 191289[130:SSi:191288.0,78218.0,78222.0,165526.0,190958.0,191276.0] || -> . % 76.16/76.39 191290[130:Spt:191289.0,191281.0,191286.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.39 191291[130:Spt:191289.0,191281.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 191295[130:Res:191291.0,61.1] always3(s35) || -> . % 76.16/76.39 191296[130:SSi:191295.0,78223.0,78226.0,165527.0] || -> . % 76.16/76.39 191297[128:Spt:191296.0,190957.0,190958.0] || until2p7(s34)*+ -> . % 76.16/76.39 191298[128:Spt:191296.0,190957.1] || -> node4(s33)*. % 76.16/76.39 191300[128:MRR:819.0,191298.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.39 191303[128:Res:53.1,191300.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.39 191305[129:Spt:191303.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 191307[129:Res:191305.0,61.1] always3(s33) || -> . % 76.16/76.39 191308[129:SSi:191307.0,78214.0,78217.0,165525.0,190956.0,191298.0] || -> . % 76.16/76.39 191309[129:Spt:191308.0,191303.0,191305.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.39 191310[129:Spt:191308.0,191303.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 191314[129:Res:191310.0,61.1] always3(s34) || -> . % 76.16/76.39 191315[129:SSi:191314.0,78218.0,78222.0,165526.0] || -> . % 76.16/76.39 191316[127:Spt:191315.0,190955.0,190956.0] || until2p7(s33)*+ -> . % 76.16/76.39 191317[127:Spt:191315.0,190955.1] || -> node4(s32)*. % 76.16/76.39 191319[127:MRR:822.0,191317.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.39 191322[127:Res:53.1,191319.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.39 191324[128:Spt:191322.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 191326[128:Res:191324.0,61.1] always3(s32) || -> . % 76.16/76.39 191327[128:SSi:191326.0,78209.0,78213.0,165524.0,190954.0,191317.0] || -> . % 76.16/76.39 191328[128:Spt:191327.0,191322.0,191324.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.39 191329[128:Spt:191327.0,191322.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 191333[128:Res:191329.0,61.1] always3(s33) || -> . % 76.16/76.39 191334[128:SSi:191333.0,78214.0,78217.0,165525.0] || -> . % 76.16/76.39 191335[126:Spt:191334.0,190953.0,190954.0] || until2p7(s32)*+ -> . % 76.16/76.39 191336[126:Spt:191334.0,190953.1] || -> node4(s31)*. % 76.16/76.39 191338[126:MRR:825.0,191336.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.39 191341[126:Res:53.1,191338.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.39 191343[127:Spt:191341.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 191345[127:Res:191343.0,61.1] always3(s31) || -> . % 76.16/76.39 191346[127:SSi:191345.0,78205.0,78208.0,165523.0,190952.0,191336.0] || -> . % 76.16/76.39 191347[127:Spt:191346.0,191341.0,191343.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.39 191348[127:Spt:191346.0,191341.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 191352[127:Res:191348.0,61.1] always3(s32) || -> . % 76.16/76.39 191353[127:SSi:191352.0,78209.0,78213.0,165524.0] || -> . % 76.16/76.39 191354[125:Spt:191353.0,190951.0,190952.0] || until2p7(s31)*+ -> . % 76.16/76.39 191355[125:Spt:191353.0,190951.1] || -> node4(s30)*. % 76.16/76.39 191357[125:MRR:828.0,191355.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.39 191360[125:Res:53.1,191357.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.39 191365[126:Spt:191360.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 191367[126:Res:191365.0,61.1] always3(s30) || -> . % 76.16/76.39 191368[126:SSi:191367.0,78200.0,78204.0,165522.0,190950.0,191355.0] || -> . % 76.16/76.39 191369[126:Spt:191368.0,191360.0,191365.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.39 191370[126:Spt:191368.0,191360.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 191374[126:Res:191370.0,61.1] always3(s31) || -> . % 76.16/76.39 191375[126:SSi:191374.0,78205.0,78208.0,165523.0] || -> . % 76.16/76.39 191376[124:Spt:191375.0,190949.0,190950.0] || until2p7(s30)*+ -> . % 76.16/76.39 191377[124:Spt:191375.0,190949.1] || -> node4(s29)*. % 76.16/76.39 191379[124:MRR:831.0,191377.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.39 191382[124:Res:53.1,191379.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.39 191384[125:Spt:191382.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.39 191386[125:Res:191384.0,61.1] always3(s29) || -> . % 76.16/76.39 191387[125:SSi:191386.0,78196.0,78199.0,165521.0,190948.0,191377.0] || -> . % 76.16/76.39 191388[125:Spt:191387.0,191382.0,191384.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.39 191389[125:Spt:191387.0,191382.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 191393[125:Res:191389.0,61.1] always3(s30) || -> . % 76.16/76.39 191394[125:SSi:191393.0,78200.0,78204.0,165522.0] || -> . % 76.16/76.39 191395[123:Spt:191394.0,190947.0,190948.0] || until2p7(s29)*+ -> . % 76.16/76.39 191396[123:Spt:191394.0,190947.1] || -> node4(s28)*. % 76.16/76.39 191398[123:MRR:834.0,191396.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.39 191401[123:Res:53.1,191398.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.39 191403[124:Spt:191401.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.39 191405[124:Res:191403.0,61.1] always3(s28) || -> . % 76.16/76.39 191406[124:SSi:191405.0,78191.0,78195.0,165520.0,190946.0,191396.0] || -> . % 76.16/76.39 191407[124:Spt:191406.0,191401.0,191403.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.39 191408[124:Spt:191406.0,191401.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.39 191412[124:Res:191408.0,61.1] always3(s29) || -> . % 76.16/76.39 191413[124:SSi:191412.0,78196.0,78199.0,165521.0] || -> . % 76.16/76.39 191414[122:Spt:191413.0,190945.0,190946.0] || until2p7(s28)*+ -> . % 76.16/76.39 191415[122:Spt:191413.0,190945.1] || -> node4(s27)*. % 76.16/76.39 191417[122:MRR:837.0,191415.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.39 191420[122:Res:53.1,191417.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.39 191422[123:Spt:191420.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.39 191424[123:Res:191422.0,61.1] always3(s27) || -> . % 76.16/76.39 191425[123:SSi:191424.0,78187.0,78190.0,165519.0,190944.0,191415.0] || -> . % 76.16/76.39 191426[123:Spt:191425.0,191420.0,191422.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.39 191427[123:Spt:191425.0,191420.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.39 191431[123:Res:191427.0,61.1] always3(s28) || -> . % 76.16/76.39 191432[123:SSi:191431.0,78191.0,78195.0,165520.0] || -> . % 76.16/76.39 191433[121:Spt:191432.0,190943.0,190944.0] || until2p7(s27)*+ -> . % 76.16/76.39 191434[121:Spt:191432.0,190943.1] || -> node4(s26)*. % 76.16/76.39 191436[121:MRR:840.0,191434.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.39 191439[121:Res:53.1,191436.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.39 191444[122:Spt:191439.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.39 191446[122:Res:191444.0,61.1] always3(s26) || -> . % 76.16/76.39 191447[122:SSi:191446.0,78182.0,78186.0,165518.0,190942.0,191434.0] || -> . % 76.16/76.39 191448[122:Spt:191447.0,191439.0,191444.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.39 191449[122:Spt:191447.0,191439.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.39 191453[122:Res:191449.0,61.1] always3(s27) || -> . % 76.16/76.39 191454[122:SSi:191453.0,78187.0,78190.0,165519.0] || -> . % 76.16/76.39 191455[120:Spt:191454.0,190941.0,190942.0] || until2p7(s26)*+ -> . % 76.16/76.39 191456[120:Spt:191454.0,190941.1] || -> node4(s25)*. % 76.16/76.39 191458[120:MRR:843.0,191456.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.39 191461[120:Res:53.1,191458.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.39 191463[121:Spt:191461.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.39 191465[121:Res:191463.0,61.1] always3(s25) || -> . % 76.16/76.39 191466[121:SSi:191465.0,78178.0,78181.0,165517.0,190940.0,191456.0] || -> . % 76.16/76.39 191467[121:Spt:191466.0,191461.0,191463.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.39 191468[121:Spt:191466.0,191461.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.39 191472[121:Res:191468.0,61.1] always3(s26) || -> . % 76.16/76.39 191473[121:SSi:191472.0,78182.0,78186.0,165518.0] || -> . % 76.16/76.39 191474[119:Spt:191473.0,190939.0,190940.0] || until2p7(s25)*+ -> . % 76.16/76.39 191475[119:Spt:191473.0,190939.1] || -> node4(s24)*. % 76.16/76.39 191477[119:MRR:846.0,191475.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.39 191480[119:Res:53.1,191477.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.39 191482[120:Spt:191480.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.39 191484[120:Res:191482.0,61.1] always3(s24) || -> . % 76.16/76.39 191485[120:SSi:191484.0,78173.0,78177.0,165516.0,190938.0,191475.0] || -> . % 76.16/76.39 191486[120:Spt:191485.0,191480.0,191482.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.39 191487[120:Spt:191485.0,191480.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.39 191491[120:Res:191487.0,61.1] always3(s25) || -> . % 76.16/76.39 191492[120:SSi:191491.0,78178.0,78181.0,165517.0] || -> . % 76.16/76.39 191493[118:Spt:191492.0,190937.0,190938.0] || until2p7(s24)*+ -> . % 76.16/76.39 191494[118:Spt:191492.0,190937.1] || -> node4(s23)*. % 76.16/76.39 191496[118:MRR:849.0,191494.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.39 191499[118:Res:53.1,191496.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.39 191501[119:Spt:191499.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.39 191503[119:Res:191501.0,61.1] always3(s23) || -> . % 76.16/76.39 191504[119:SSi:191503.0,78169.0,78172.0,165515.0,190936.0,191494.0] || -> . % 76.16/76.39 191505[119:Spt:191504.0,191499.0,191501.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.39 191506[119:Spt:191504.0,191499.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.39 191510[119:Res:191506.0,61.1] always3(s24) || -> . % 76.16/76.39 191511[119:SSi:191510.0,78173.0,78177.0,165516.0] || -> . % 76.16/76.39 191512[117:Spt:191511.0,190935.0,190936.0] || until2p7(s23)*+ -> . % 76.16/76.39 191513[117:Spt:191511.0,190935.1] || -> node4(s22)*. % 76.16/76.39 191515[117:MRR:852.0,191513.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.39 191518[117:Res:53.1,191515.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.39 191523[118:Spt:191518.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.39 191525[118:Res:191523.0,61.1] always3(s22) || -> . % 76.16/76.39 191526[118:SSi:191525.0,78164.0,78168.0,165514.0,190934.0,191513.0] || -> . % 76.16/76.39 191527[118:Spt:191526.0,191518.0,191523.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.39 191528[118:Spt:191526.0,191518.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.39 191532[118:Res:191528.0,61.1] always3(s23) || -> . % 76.16/76.39 191533[118:SSi:191532.0,78169.0,78172.0,165515.0] || -> . % 76.16/76.39 191534[116:Spt:191533.0,190933.0,190934.0] || until2p7(s22)*+ -> . % 76.16/76.39 191535[116:Spt:191533.0,190933.1] || -> node4(s21)*. % 76.16/76.39 191537[116:MRR:855.0,191535.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.39 191540[116:Res:53.1,191537.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.39 191542[117:Spt:191540.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.39 191544[117:Res:191542.0,61.1] always3(s21) || -> . % 76.16/76.39 191545[117:SSi:191544.0,78160.0,78163.0,165513.0,190932.0,191535.0] || -> . % 76.16/76.39 191546[117:Spt:191545.0,191540.0,191542.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.39 191547[117:Spt:191545.0,191540.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.39 191551[117:Res:191547.0,61.1] always3(s22) || -> . % 76.16/76.39 191552[117:SSi:191551.0,78164.0,78168.0,165514.0] || -> . % 76.16/76.39 191553[115:Spt:191552.0,190931.0,190932.0] || until2p7(s21)*+ -> . % 76.16/76.39 191554[115:Spt:191552.0,190931.1] || -> node4(s20)*. % 76.16/76.39 191556[115:MRR:858.0,191554.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.39 191559[115:Res:53.1,191556.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.39 191561[116:Spt:191559.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.39 191563[116:Res:191561.0,61.1] always3(s20) || -> . % 76.16/76.39 191564[116:SSi:191563.0,78155.0,78159.0,165512.0,190930.0,191554.0] || -> . % 76.16/76.39 191565[116:Spt:191564.0,191559.0,191561.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.39 191566[116:Spt:191564.0,191559.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.39 191570[116:Res:191566.0,61.1] always3(s21) || -> . % 76.16/76.39 191571[116:SSi:191570.0,78160.0,78163.0,165513.0] || -> . % 76.16/76.39 191572[114:Spt:191571.0,190929.0,190930.0] || until2p7(s20)*+ -> . % 76.16/76.39 191573[114:Spt:191571.0,190929.1] || -> node4(s19)*. % 76.16/76.39 191575[114:MRR:861.0,191573.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.39 191578[114:Res:53.1,191575.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.39 191580[115:Spt:191578.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.39 191582[115:Res:191580.0,61.1] always3(s19) || -> . % 76.16/76.39 191583[115:SSi:191582.0,78151.0,78154.0,165511.0,190928.0,191573.0] || -> . % 76.16/76.39 191584[115:Spt:191583.0,191578.0,191580.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.39 191585[115:Spt:191583.0,191578.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.39 191589[115:Res:191585.0,61.1] always3(s20) || -> . % 76.16/76.39 191590[115:SSi:191589.0,78155.0,78159.0,165512.0] || -> . % 76.16/76.39 191591[113:Spt:191590.0,190927.0,190928.0] || until2p7(s19)*+ -> . % 76.16/76.39 191592[113:Spt:191590.0,190927.1] || -> node4(s18)*. % 76.16/76.39 191594[113:MRR:864.0,191592.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.39 191597[113:Res:53.1,191594.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.39 191602[114:Spt:191597.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.39 191604[114:Res:191602.0,61.1] always3(s18) || -> . % 76.16/76.39 191605[114:SSi:191604.0,78146.0,78150.0,165510.0,190926.0,191592.0] || -> . % 76.16/76.39 191606[114:Spt:191605.0,191597.0,191602.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.39 191607[114:Spt:191605.0,191597.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.39 191611[114:Res:191607.0,61.1] always3(s19) || -> . % 76.16/76.39 191612[114:SSi:191611.0,78151.0,78154.0,165511.0] || -> . % 76.16/76.39 191613[112:Spt:191612.0,190925.0,190926.0] || until2p7(s18)*+ -> . % 76.16/76.39 191614[112:Spt:191612.0,190925.1] || -> node4(s17)*. % 76.16/76.39 191616[112:MRR:867.0,191614.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.39 191619[112:Res:53.1,191616.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.39 191621[113:Spt:191619.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.39 191623[113:Res:191621.0,61.1] always3(s17) || -> . % 76.16/76.39 191624[113:SSi:191623.0,78142.0,78145.0,165509.0,190924.0,191614.0] || -> . % 76.16/76.39 191625[113:Spt:191624.0,191619.0,191621.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.39 191626[113:Spt:191624.0,191619.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.39 191630[113:Res:191626.0,61.1] always3(s18) || -> . % 76.16/76.39 191631[113:SSi:191630.0,78146.0,78150.0,165510.0] || -> . % 76.16/76.39 191632[111:Spt:191631.0,190923.0,190924.0] || until2p7(s17)*+ -> . % 76.16/76.39 191633[111:Spt:191631.0,190923.1] || -> node4(s16)*. % 76.16/76.39 191635[111:MRR:870.0,191633.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.39 191638[111:Res:53.1,191635.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.39 191640[112:Spt:191638.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.39 191642[112:Res:191640.0,61.1] always3(s16) || -> . % 76.16/76.39 191643[112:SSi:191642.0,78137.0,78141.0,165508.0,190922.0,191633.0] || -> . % 76.16/76.39 191644[112:Spt:191643.0,191638.0,191640.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.39 191645[112:Spt:191643.0,191638.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.39 191649[112:Res:191645.0,61.1] always3(s17) || -> . % 76.16/76.39 191650[112:SSi:191649.0,78142.0,78145.0,165509.0] || -> . % 76.16/76.39 191651[110:Spt:191650.0,190921.0,190922.0] || until2p7(s16)*+ -> . % 76.16/76.39 191652[110:Spt:191650.0,190921.1] || -> node4(s15)*. % 76.16/76.39 191654[110:MRR:873.0,191652.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.39 191657[110:Res:53.1,191654.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.39 191659[111:Spt:191657.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.39 191661[111:Res:191659.0,61.1] always3(s15) || -> . % 76.16/76.39 191662[111:SSi:191661.0,78133.0,78136.0,165507.0,190920.0,191652.0] || -> . % 76.16/76.39 191663[111:Spt:191662.0,191657.0,191659.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.39 191664[111:Spt:191662.0,191657.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.39 191668[111:Res:191664.0,61.1] always3(s16) || -> . % 76.16/76.39 191669[111:SSi:191668.0,78137.0,78141.0,165508.0] || -> . % 76.16/76.39 191670[109:Spt:191669.0,190919.0,190920.0] || until2p7(s15)*+ -> . % 76.16/76.39 191671[109:Spt:191669.0,190919.1] || -> node4(s14)*. % 76.16/76.39 191673[109:MRR:876.0,191671.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.39 191676[109:Res:53.1,191673.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.39 191681[110:Spt:191676.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.39 191683[110:Res:191681.0,61.1] always3(s14) || -> . % 76.16/76.39 191684[110:SSi:191683.0,78128.0,78132.0,165506.0,190918.0,191671.0] || -> . % 76.16/76.39 191685[110:Spt:191684.0,191676.0,191681.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.39 191686[110:Spt:191684.0,191676.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.39 191690[110:Res:191686.0,61.1] always3(s15) || -> . % 76.16/76.39 191691[110:SSi:191690.0,78133.0,78136.0,165507.0] || -> . % 76.16/76.39 191692[108:Spt:191691.0,190917.0,190918.0] || until2p7(s14)*+ -> . % 76.16/76.39 191693[108:Spt:191691.0,190917.1] || -> node4(s13)*. % 76.16/76.39 191695[108:MRR:879.0,191693.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.39 191698[108:Res:53.1,191695.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.39 191700[109:Spt:191698.0] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.39 191702[109:Res:191700.0,61.1] always3(s13) || -> . % 76.16/76.39 191703[109:SSi:191702.0,78124.0,78127.0,165505.0,190916.0,191693.0] || -> . % 76.16/76.39 191704[109:Spt:191703.0,191698.0,191700.0] || m_main_v_state(s13,c_busy)* -> . % 76.16/76.39 191705[109:Spt:191703.0,191698.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.39 191709[109:Res:191705.0,61.1] always3(s14) || -> . % 76.16/76.39 191710[109:SSi:191709.0,78128.0,78132.0,165506.0] || -> . % 76.16/76.39 191711[107:Spt:191710.0,190915.0,190916.0] || until2p7(s13)*+ -> . % 76.16/76.39 191712[107:Spt:191710.0,190915.1] || -> node4(s12)*. % 76.16/76.39 191714[107:MRR:882.0,191712.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.16/76.39 191717[107:Res:53.1,191714.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.16/76.39 191719[108:Spt:191717.0] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.39 191721[108:Res:191719.0,61.1] always3(s12) || -> . % 76.16/76.39 191722[108:SSi:191721.0,78119.0,78123.0,165504.0,190914.0,191712.0] || -> . % 76.16/76.39 191723[108:Spt:191722.0,191717.0,191719.0] || m_main_v_state(s12,c_busy)* -> . % 76.16/76.39 191724[108:Spt:191722.0,191717.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.39 191728[108:Res:191724.0,61.1] always3(s13) || -> . % 76.16/76.39 191729[108:SSi:191728.0,78124.0,78127.0,165505.0] || -> . % 76.16/76.39 191730[106:Spt:191729.0,190913.0,190914.0] || until2p7(s12)*+ -> . % 76.16/76.39 191731[106:Spt:191729.0,190913.1] || -> node4(s11)*. % 76.16/76.39 191733[106:MRR:885.0,191731.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.16/76.39 191736[106:Res:53.1,191733.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.16/76.39 191738[107:Spt:191736.0] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.39 191740[107:Res:191738.0,61.1] always3(s11) || -> . % 76.16/76.39 191741[107:SSi:191740.0,78115.0,78118.0,165503.0,190912.0,191731.0] || -> . % 76.16/76.39 191742[107:Spt:191741.0,191736.0,191738.0] || m_main_v_state(s11,c_busy)* -> . % 76.16/76.39 191743[107:Spt:191741.0,191736.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.39 191747[107:Res:191743.0,61.1] always3(s12) || -> . % 76.16/76.39 191748[107:SSi:191747.0,78119.0,78123.0,165504.0] || -> . % 76.16/76.39 191749[105:Spt:191748.0,190911.0,190912.0] || until2p7(s11)*+ -> . % 76.16/76.39 191750[105:Spt:191748.0,190911.1] || -> node4(s10)*. % 76.16/76.39 191752[105:MRR:888.0,191750.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.16/76.39 191755[105:Res:53.1,191752.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.16/76.39 191760[106:Spt:191755.0] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.39 191762[106:Res:191760.0,61.1] always3(s10) || -> . % 76.16/76.39 191763[106:SSi:191762.0,78110.0,78114.0,165502.0,190910.0,191750.0] || -> . % 76.16/76.39 191764[106:Spt:191763.0,191755.0,191760.0] || m_main_v_state(s10,c_busy)* -> . % 76.16/76.39 191765[106:Spt:191763.0,191755.1] || -> m_main_v_state(s11,c_busy)*. % 76.16/76.39 191769[106:Res:191765.0,61.1] always3(s11) || -> . % 76.16/76.39 191770[106:SSi:191769.0,78115.0,78118.0,165503.0] || -> . % 76.16/76.39 191771[104:Spt:191770.0,190909.0,190910.0] || until2p7(s10)*+ -> . % 76.16/76.39 191772[104:Spt:191770.0,190909.1] || -> node4(s9)*. % 76.16/76.39 191774[104:MRR:891.0,191772.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.16/76.39 191777[104:Res:53.1,191774.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.16/76.39 191779[105:Spt:191777.0] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.39 191781[105:Res:191779.0,61.1] always3(s9) || -> . % 76.16/76.39 191782[105:SSi:191781.0,78106.0,78109.0,165501.0,190908.0,191772.0] || -> . % 76.16/76.39 191783[105:Spt:191782.0,191777.0,191779.0] || m_main_v_state(s9,c_busy)* -> . % 76.16/76.39 191784[105:Spt:191782.0,191777.1] || -> m_main_v_state(s10,c_busy)*. % 76.16/76.39 191788[105:Res:191784.0,61.1] always3(s10) || -> . % 76.16/76.39 191789[105:SSi:191788.0,78110.0,78114.0,165502.0] || -> . % 76.16/76.39 191790[103:Spt:191789.0,190907.0,190908.0] || until2p7(s9)*+ -> . % 76.16/76.39 191791[103:Spt:191789.0,190907.1] || -> node4(s8)*. % 76.16/76.39 191793[103:MRR:894.0,191791.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.16/76.39 191796[103:Res:53.1,191793.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.16/76.39 191798[104:Spt:191796.0] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.39 191800[104:Res:191798.0,61.1] always3(s8) || -> . % 76.16/76.39 191801[104:SSi:191800.0,78101.0,78105.0,165500.0,190906.0,191791.0] || -> . % 76.16/76.39 191802[104:Spt:191801.0,191796.0,191798.0] || m_main_v_state(s8,c_busy)* -> . % 76.16/76.39 191803[104:Spt:191801.0,191796.1] || -> m_main_v_state(s9,c_busy)*. % 76.16/76.39 191807[104:Res:191803.0,61.1] always3(s9) || -> . % 76.16/76.39 191808[104:SSi:191807.0,78106.0,78109.0,165501.0] || -> . % 76.16/76.39 191809[102:Spt:191808.0,190905.0,190906.0] || until2p7(s8)*+ -> . % 76.16/76.39 191810[102:Spt:191808.0,190905.1] || -> node4(s7)*. % 76.16/76.39 191812[102:MRR:897.0,191810.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.16/76.39 191815[102:Res:53.1,191812.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.16/76.39 191817[103:Spt:191815.0] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.39 191819[103:Res:191817.0,61.1] always3(s7) || -> . % 76.16/76.39 191820[103:SSi:191819.0,78097.0,78100.0,165499.0,190904.0,191810.0] || -> . % 76.16/76.39 191821[103:Spt:191820.0,191815.0,191817.0] || m_main_v_state(s7,c_busy)* -> . % 76.16/76.39 191822[103:Spt:191820.0,191815.1] || -> m_main_v_state(s8,c_busy)*. % 76.16/76.39 191826[103:Res:191822.0,61.1] always3(s8) || -> . % 76.16/76.39 191827[103:SSi:191826.0,78101.0,78105.0,165500.0] || -> . % 76.16/76.39 191828[101:Spt:191827.0,190903.0,190904.0] || until2p7(s7)*+ -> . % 76.16/76.39 191829[101:Spt:191827.0,190903.1] || -> node4(s6)*. % 76.16/76.39 191831[101:MRR:900.0,191829.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.16/76.39 191834[101:Res:53.1,191831.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.16/76.39 191839[102:Spt:191834.0] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.39 191841[102:Res:191839.0,61.1] always3(s6) || -> . % 76.16/76.39 191842[102:SSi:191841.0,78093.0,78096.0,165498.0,190902.0,191829.0] || -> . % 76.16/76.39 191843[102:Spt:191842.0,191834.0,191839.0] || m_main_v_state(s6,c_busy)* -> . % 76.16/76.39 191844[102:Spt:191842.0,191834.1] || -> m_main_v_state(s7,c_busy)*. % 76.16/76.39 191848[102:Res:191844.0,61.1] always3(s7) || -> . % 76.16/76.39 191849[102:SSi:191848.0,78097.0,78100.0,165499.0] || -> . % 76.16/76.39 191850[100:Spt:191849.0,190901.0,190902.0] || until2p7(s6)*+ -> . % 76.16/76.39 191851[100:Spt:191849.0,190901.1] || -> node4(s5)*. % 76.16/76.39 191853[100:MRR:903.0,191851.0] || m_main_v_state(s5,c_ready)*+ -> m_main_v_state(s6,c_busy). % 76.16/76.39 191856[100:Res:53.1,191853.0] || -> m_main_v_state(s5,c_busy)* m_main_v_state(s6,c_busy). % 76.16/76.39 191858[100:MRR:191856.0,190892.0] || -> m_main_v_state(s6,c_busy)*. % 76.16/76.39 191860[100:Res:191858.0,61.1] always3(s6) || -> . % 76.16/76.39 191861[100:SSi:191860.0,78093.0,78096.0,165498.0] || -> . % 76.16/76.39 191862[54:Spt:191861.0,165254.44,165497.0] || always3(s5)*+ -> . % 76.16/76.39 191863[54:Spt:191861.0,165254.0,165254.1,165254.2,165254.3,165254.4,165254.5,165254.6,165254.7,165254.8,165254.9,165254.10,165254.11,165254.12,165254.13,165254.14,165254.15,165254.16,165254.17,165254.18,165254.19,165254.20,165254.21,165254.22,165254.23,165254.24,165254.25,165254.26,165254.27,165254.28,165254.29,165254.30,165254.31,165254.32,165254.33,165254.34,165254.35,165254.36,165254.37,165254.38,165254.39,165254.40,165254.41,165254.42,165254.43] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) trans(s49,s6)*. % 76.16/76.39 191865[54:Res:191863.43,69.2] xuntil6(s49) last(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 191866[54:Res:191863.43,62.1] always3(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* always3(s6). % 76.16/76.39 191867[54:Res:191863.43,60.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 191868[54:SSi:191866.0,50.0,78285.0,78388.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* always3(s6). % 76.16/76.39 191869[54:SSi:191865.1,50.0,78285.0,78388.0] xuntil6(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 192105[55:Spt:191868.43] || -> always3(s6)*. % 76.16/76.39 192106[55:MRR:516.0,192105.0] || -> always3(s7)*. % 76.16/76.39 192107[55:MRR:513.0,192106.0] || -> always3(s8)*. % 76.16/76.39 192108[55:MRR:510.0,192107.0] || -> always3(s9)*. % 76.16/76.39 192109[55:MRR:507.0,192108.0] || -> always3(s10)*. % 76.16/76.39 192110[55:MRR:504.0,192109.0] || -> always3(s11)*. % 76.16/76.39 192111[55:MRR:501.0,192110.0] || -> always3(s12)*. % 76.16/76.39 192112[55:MRR:498.0,192111.0] || -> always3(s13)*. % 76.16/76.39 192113[55:MRR:495.0,192112.0] || -> always3(s14)*. % 76.16/76.39 192114[55:MRR:492.0,192113.0] || -> always3(s15)*. % 76.16/76.39 192115[55:MRR:489.0,192114.0] || -> always3(s16)*. % 76.16/76.39 192116[55:MRR:486.0,192115.0] || -> always3(s17)*. % 76.16/76.39 192117[55:MRR:483.0,192116.0] || -> always3(s18)*. % 76.16/76.39 192118[55:MRR:480.0,192117.0] || -> always3(s19)*. % 76.16/76.39 192119[55:MRR:477.0,192118.0] || -> always3(s20)*. % 76.16/76.39 192120[55:MRR:474.0,192119.0] || -> always3(s21)*. % 76.16/76.39 192121[55:MRR:471.0,192120.0] || -> always3(s22)*. % 76.16/76.39 192122[55:MRR:468.0,192121.0] || -> always3(s23)*. % 76.16/76.39 192123[55:MRR:465.0,192122.0] || -> always3(s24)*. % 76.16/76.39 192124[55:MRR:462.0,192123.0] || -> always3(s25)*. % 76.16/76.39 192125[55:MRR:459.0,192124.0] || -> always3(s26)*. % 76.16/76.39 192126[55:MRR:456.0,192125.0] || -> always3(s27)*. % 76.16/76.39 192127[55:MRR:453.0,192126.0] || -> always3(s28)*. % 76.16/76.39 192128[55:MRR:450.0,192127.0] || -> always3(s29)*. % 76.16/76.39 192129[55:MRR:427.0,192128.0] || -> always3(s30)*. % 76.16/76.39 192130[55:MRR:425.0,192129.0] || -> always3(s31)*. % 76.16/76.39 192131[55:MRR:423.0,192130.0] || -> always3(s32)*. % 76.16/76.39 192132[55:MRR:421.0,192131.0] || -> always3(s33)*. % 76.16/76.39 192133[55:MRR:370.0,192132.0] || -> always3(s34)*. % 76.16/76.39 192134[55:MRR:368.0,192133.0] || -> always3(s35)*. % 76.16/76.39 192135[55:MRR:366.0,192134.0] || -> always3(s36)*. % 76.16/76.39 192136[55:MRR:364.0,192135.0] || -> always3(s37)*. % 76.16/76.39 192137[55:MRR:313.0,192136.0] || -> always3(s38)*. % 76.16/76.39 192138[55:MRR:311.0,192137.0] || -> always3(s39)*. % 76.16/76.39 192139[55:MRR:309.0,192138.0] || -> always3(s40)*. % 76.16/76.39 192140[55:MRR:307.0,192139.0] || -> always3(s41)*. % 76.16/76.39 192141[55:MRR:306.0,192140.0] || -> always3(s42)*. % 76.16/76.39 192142[55:MRR:305.0,192141.0] || -> always3(s43)*. % 76.16/76.39 192143[55:MRR:304.0,192142.0] || -> always3(s44)*. % 76.16/76.39 192144[55:MRR:303.0,192143.0] || -> always3(s45)*. % 76.16/76.39 192145[55:MRR:302.0,192144.0] || -> always3(s46)*. % 76.16/76.39 192146[55:MRR:301.0,192145.0] || -> always3(s47)*. % 76.16/76.39 192147[55:MRR:300.0,192146.0] || -> always3(s48)*. % 76.16/76.39 192148[56:Spt:191867.0] || -> trans(s49,s49)*. % 76.16/76.39 192149[56:Res:192148.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s49)*. % 76.16/76.39 192151[56:Res:192148.0,60.0] || -> node2(s49,s49)*. % 76.16/76.39 192152[56:SSi:192149.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s49)*. % 76.16/76.39 192153[56:Res:192151.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> m_main_v_state(s49,c_busy). % 76.16/76.39 192154[56:MRR:192153.1,192153.2,53.1,78381.0] m_main_v_request(s49) || -> . % 76.16/76.39 192156[56:SoR:192154.0,64.1] node4(s49) || -> . % 76.16/76.39 192157[56:MRR:194.1,192156.0] until2p7(s49) || -> . % 76.16/76.39 192160[56:MRR:192152.1,192157.0] xuntil6(s49) || -> . % 76.16/76.39 192161[56:SoR:192156.0,66.2] until5(s49) || -> xuntil6(s49)*. % 76.16/76.39 192162[56:SSi:192161.0,50.0,78285.0,78388.0] || -> xuntil6(s49)*. % 76.16/76.39 192163[56:MRR:192162.0,192160.0] || -> . % 76.16/76.39 192164[56:Spt:192163.0,191867.0,192148.0] || trans(s49,s49)*+ -> . % 76.16/76.39 192165[56:Spt:192163.0,191867.1,191867.2,191867.3,191867.4,191867.5,191867.6,191867.7,191867.8,191867.9,191867.10,191867.11,191867.12,191867.13,191867.14,191867.15,191867.16,191867.17,191867.18,191867.19,191867.20,191867.21,191867.22,191867.23,191867.24,191867.25,191867.26,191867.27,191867.28,191867.29,191867.30,191867.31,191867.32,191867.33,191867.34,191867.35,191867.36,191867.37,191867.38,191867.39,191867.40,191867.41,191867.42,191867.43] || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 192167[56:MRR:191869.1,192164.0] xuntil6(s49) || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 192168[57:Spt:192165.0] || -> trans(s49,s48)*. % 76.16/76.39 192169[57:Res:192168.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s48)*. % 76.16/76.39 192171[57:Res:192168.0,60.0] || -> node2(s49,s48)*. % 76.16/76.39 192172[57:SSi:192169.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s48)*. % 76.16/76.39 192173[57:Res:192171.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192176[57:SoR:192173.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192178[57:SoR:192176.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)* xuntil6(s49). % 76.16/76.39 192179[57:SSi:192178.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s48,c_busy)* xuntil6(s49). % 76.16/76.39 192180[58:Spt:192179.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192182[58:Res:192180.0,61.1] always3(s48) || -> . % 76.16/76.39 192183[58:SSi:192182.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 192184[58:Spt:192183.0,192179.1,192180.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.16/76.39 192185[58:Spt:192183.0,192179.0,192179.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 192189[58:MRR:192176.2,192184.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 192190[58:Res:53.1,192185.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 192192[58:MRR:192190.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 192193[58:MRR:192172.0,192192.0] || -> until2p7(s48)*. % 76.16/76.39 192194[58:MRR:559.0,192193.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 192195[59:Spt:192194.0] || -> until2p7(s49)*. % 76.16/76.39 192196[59:MRR:194.0,192195.0] || -> node4(s49)*. % 76.16/76.39 192197[59:MRR:192189.0,192196.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 192198[59:Res:53.1,192197.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 192200[59:MRR:192198.0,78381.0] || -> . % 76.16/76.39 192201[59:Spt:192200.0,192194.0,192195.0] || until2p7(s49)*+ -> . % 76.16/76.39 192202[59:Spt:192200.0,192194.1] || -> node4(s48)*. % 76.16/76.39 192203[59:MRR:78384.0,192202.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 192206[59:Res:53.1,192203.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192208[59:MRR:192206.0,192184.0] || -> . % 76.16/76.39 192209[57:Spt:192208.0,192165.0,192168.0] || trans(s49,s48)*+ -> . % 76.16/76.39 192210[57:Spt:192208.0,192165.1,192165.2,192165.3,192165.4,192165.5,192165.6,192165.7,192165.8,192165.9,192165.10,192165.11,192165.12,192165.13,192165.14,192165.15,192165.16,192165.17,192165.18,192165.19,192165.20,192165.21,192165.22,192165.23,192165.24,192165.25,192165.26,192165.27,192165.28,192165.29,192165.30,192165.31,192165.32,192165.33,192165.34,192165.35,192165.36,192165.37,192165.38,192165.39,192165.40,192165.41,192165.42] || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 192212[57:MRR:192167.1,192209.0] xuntil6(s49) || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 192213[58:Spt:192210.0] || -> trans(s49,s47)*. % 76.16/76.39 192214[58:Res:192213.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s47)*. % 76.16/76.39 192216[58:Res:192213.0,60.0] || -> node2(s49,s47)*. % 76.16/76.39 192217[58:SSi:192214.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s47)*. % 76.16/76.39 192218[58:Res:192216.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 192230[58:SoR:192218.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 192232[58:SoR:192230.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 76.16/76.39 192233[58:SSi:192232.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 76.16/76.39 192234[59:Spt:192233.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 192236[59:Res:192234.0,61.1] always3(s47) || -> . % 76.16/76.39 192237[59:SSi:192236.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 192238[59:Spt:192237.0,192233.1,192234.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.16/76.39 192239[59:Spt:192237.0,192233.0,192233.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 192243[59:MRR:192230.2,192238.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 192244[59:Res:53.1,192239.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 192246[59:MRR:192244.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 192247[59:MRR:192217.0,192246.0] || -> until2p7(s47)*. % 76.16/76.39 192248[59:MRR:554.0,192247.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 192249[60:Spt:192248.0] || -> until2p7(s48)*. % 76.16/76.39 192250[60:MRR:559.0,192249.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 192251[61:Spt:192250.0] || -> until2p7(s49)*. % 76.16/76.39 192252[61:MRR:194.0,192251.0] || -> node4(s49)*. % 76.16/76.39 192253[61:MRR:192243.0,192252.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 192254[61:Res:53.1,192253.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 192256[61:MRR:192254.0,78381.0] || -> . % 76.16/76.39 192257[61:Spt:192256.0,192250.0,192251.0] || until2p7(s49)*+ -> . % 76.16/76.39 192258[61:Spt:192256.0,192250.1] || -> node4(s48)*. % 76.16/76.39 192259[61:MRR:78384.0,192258.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 192262[61:Res:53.1,192259.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192265[61:Res:192262.0,61.1] always3(s48) || -> . % 76.16/76.39 192266[61:SSi:192265.0,78281.0,78387.0,192147.0,192249.0,192258.0] || -> . % 76.16/76.39 192267[60:Spt:192266.0,192248.0,192249.0] || until2p7(s48)*+ -> . % 76.16/76.39 192268[60:Spt:192266.0,192248.1] || -> node4(s47)*. % 76.16/76.39 192270[60:MRR:777.0,192268.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 192285[60:Res:53.1,192270.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 192287[60:MRR:192285.0,192238.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192289[60:Res:192287.0,61.1] always3(s48) || -> . % 76.16/76.39 192290[60:SSi:192289.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 192291[58:Spt:192290.0,192210.0,192213.0] || trans(s49,s47)*+ -> . % 76.16/76.39 192292[58:Spt:192290.0,192210.1,192210.2,192210.3,192210.4,192210.5,192210.6,192210.7,192210.8,192210.9,192210.10,192210.11,192210.12,192210.13,192210.14,192210.15,192210.16,192210.17,192210.18,192210.19,192210.20,192210.21,192210.22,192210.23,192210.24,192210.25,192210.26,192210.27,192210.28,192210.29,192210.30,192210.31,192210.32,192210.33,192210.34,192210.35,192210.36,192210.37,192210.38,192210.39,192210.40,192210.41] || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 192294[58:MRR:192212.1,192291.0] xuntil6(s49) || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 192295[59:Spt:192292.0] || -> trans(s49,s46)*. % 76.16/76.39 192296[59:Res:192295.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s46)*. % 76.16/76.39 192298[59:Res:192295.0,60.0] || -> node2(s49,s46)*. % 76.16/76.39 192299[59:SSi:192296.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s46)*. % 76.16/76.39 192300[59:Res:192298.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 192316[59:SoR:192300.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 192318[59:SoR:192316.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)* xuntil6(s49). % 76.16/76.39 192319[59:SSi:192318.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s46,c_busy)* xuntil6(s49). % 76.16/76.39 192320[60:Spt:192319.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 192322[60:Res:192320.0,61.1] always3(s46) || -> . % 76.16/76.39 192323[60:SSi:192322.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 192324[60:Spt:192323.0,192319.1,192320.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.16/76.39 192325[60:Spt:192323.0,192319.0,192319.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 192329[60:MRR:192316.2,192324.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 192330[60:Res:53.1,192325.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 192332[60:MRR:192330.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 192333[60:MRR:192299.0,192332.0] || -> until2p7(s46)*. % 76.16/76.39 192334[60:MRR:549.0,192333.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 192335[61:Spt:192334.0] || -> until2p7(s47)*. % 76.16/76.39 192336[61:MRR:554.0,192335.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 192337[62:Spt:192336.0] || -> until2p7(s48)*. % 76.16/76.39 192338[62:MRR:559.0,192337.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 192339[63:Spt:192338.0] || -> until2p7(s49)*. % 76.16/76.39 192340[63:MRR:194.0,192339.0] || -> node4(s49)*. % 76.16/76.39 192341[63:MRR:192329.0,192340.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 192342[63:Res:53.1,192341.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 192344[63:MRR:192342.0,78381.0] || -> . % 76.16/76.39 192345[63:Spt:192344.0,192338.0,192339.0] || until2p7(s49)*+ -> . % 76.16/76.39 192346[63:Spt:192344.0,192338.1] || -> node4(s48)*. % 76.16/76.39 192347[63:MRR:78384.0,192346.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 192350[63:Res:53.1,192347.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192353[63:Res:192350.0,61.1] always3(s48) || -> . % 76.16/76.39 192354[63:SSi:192353.0,78281.0,78387.0,192147.0,192337.0,192346.0] || -> . % 76.16/76.39 192355[62:Spt:192354.0,192336.0,192337.0] || until2p7(s48)*+ -> . % 76.16/76.39 192356[62:Spt:192354.0,192336.1] || -> node4(s47)*. % 76.16/76.39 192358[62:MRR:777.0,192356.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 192373[62:Res:53.1,192358.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 192378[63:Spt:192373.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 192380[63:Res:192378.0,61.1] always3(s47) || -> . % 76.16/76.39 192381[63:SSi:192380.0,78277.0,78280.0,192146.0,192335.0,192356.0] || -> . % 76.16/76.39 192382[63:Spt:192381.0,192373.0,192378.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 192383[63:Spt:192381.0,192373.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192387[63:Res:192383.0,61.1] always3(s48) || -> . % 76.16/76.39 192388[63:SSi:192387.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 192389[61:Spt:192388.0,192334.0,192335.0] || until2p7(s47)*+ -> . % 76.16/76.39 192390[61:Spt:192388.0,192334.1] || -> node4(s46)*. % 76.16/76.39 192392[61:MRR:780.0,192390.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 192399[61:Res:53.1,192392.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 192401[61:MRR:192399.0,192324.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 192403[61:Res:192401.0,61.1] always3(s47) || -> . % 76.16/76.39 192404[61:SSi:192403.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 192405[59:Spt:192404.0,192292.0,192295.0] || trans(s49,s46)*+ -> . % 76.16/76.39 192406[59:Spt:192404.0,192292.1,192292.2,192292.3,192292.4,192292.5,192292.6,192292.7,192292.8,192292.9,192292.10,192292.11,192292.12,192292.13,192292.14,192292.15,192292.16,192292.17,192292.18,192292.19,192292.20,192292.21,192292.22,192292.23,192292.24,192292.25,192292.26,192292.27,192292.28,192292.29,192292.30,192292.31,192292.32,192292.33,192292.34,192292.35,192292.36,192292.37,192292.38,192292.39,192292.40] || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 192408[59:MRR:192294.1,192405.0] xuntil6(s49) || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 192409[60:Spt:192406.0] || -> trans(s49,s45)*. % 76.16/76.39 192410[60:Res:192409.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s45)*. % 76.16/76.39 192412[60:Res:192409.0,60.0] || -> node2(s49,s45)*. % 76.16/76.39 192413[60:SSi:192410.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s45)*. % 76.16/76.39 192414[60:Res:192412.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 192430[60:SoR:192414.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 192432[60:SoR:192430.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)* xuntil6(s49). % 76.16/76.39 192433[60:SSi:192432.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s45,c_busy)* xuntil6(s49). % 76.16/76.39 192434[61:Spt:192433.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 192436[61:Res:192434.0,61.1] always3(s45) || -> . % 76.16/76.39 192437[61:SSi:192436.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 192438[61:Spt:192437.0,192433.1,192434.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.16/76.39 192439[61:Spt:192437.0,192433.0,192433.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 192443[61:MRR:192430.2,192438.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 192444[61:Res:53.1,192439.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 192446[61:MRR:192444.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 192447[61:MRR:192413.0,192446.0] || -> until2p7(s45)*. % 76.16/76.39 192448[61:MRR:544.0,192447.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 192449[62:Spt:192448.0] || -> until2p7(s46)*. % 76.16/76.39 192450[62:MRR:549.0,192449.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 192451[63:Spt:192450.0] || -> until2p7(s47)*. % 76.16/76.39 192452[63:MRR:554.0,192451.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 192453[64:Spt:192452.0] || -> until2p7(s48)*. % 76.16/76.39 192454[64:MRR:559.0,192453.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 192455[65:Spt:192454.0] || -> until2p7(s49)*. % 76.16/76.39 192456[65:MRR:194.0,192455.0] || -> node4(s49)*. % 76.16/76.39 192457[65:MRR:192443.0,192456.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 192458[65:Res:53.1,192457.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 192460[65:MRR:192458.0,78381.0] || -> . % 76.16/76.39 192461[65:Spt:192460.0,192454.0,192455.0] || until2p7(s49)*+ -> . % 76.16/76.39 192462[65:Spt:192460.0,192454.1] || -> node4(s48)*. % 76.16/76.39 192463[65:MRR:78384.0,192462.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 192466[65:Res:53.1,192463.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192469[65:Res:192466.0,61.1] always3(s48) || -> . % 76.16/76.39 192470[65:SSi:192469.0,78281.0,78387.0,192147.0,192453.0,192462.0] || -> . % 76.16/76.39 192471[64:Spt:192470.0,192452.0,192453.0] || until2p7(s48)*+ -> . % 76.16/76.39 192472[64:Spt:192470.0,192452.1] || -> node4(s47)*. % 76.16/76.39 192474[64:MRR:777.0,192472.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 192492[64:Res:53.1,192474.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 192494[65:Spt:192492.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 192496[65:Res:192494.0,61.1] always3(s47) || -> . % 76.16/76.39 192497[65:SSi:192496.0,78277.0,78280.0,192146.0,192451.0,192472.0] || -> . % 76.16/76.39 192498[65:Spt:192497.0,192492.0,192494.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 192499[65:Spt:192497.0,192492.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192503[65:Res:192499.0,61.1] always3(s48) || -> . % 76.16/76.39 192504[65:SSi:192503.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 192505[63:Spt:192504.0,192450.0,192451.0] || until2p7(s47)*+ -> . % 76.16/76.39 192506[63:Spt:192504.0,192450.1] || -> node4(s46)*. % 76.16/76.39 192508[63:MRR:780.0,192506.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 192515[63:Res:53.1,192508.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 192520[64:Spt:192515.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 192522[64:Res:192520.0,61.1] always3(s46) || -> . % 76.16/76.39 192523[64:SSi:192522.0,78272.0,78276.0,192145.0,192449.0,192506.0] || -> . % 76.16/76.39 192524[64:Spt:192523.0,192515.0,192520.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 192525[64:Spt:192523.0,192515.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 192529[64:Res:192525.0,61.1] always3(s47) || -> . % 76.16/76.39 192530[64:SSi:192529.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 192531[62:Spt:192530.0,192448.0,192449.0] || until2p7(s46)*+ -> . % 76.16/76.39 192532[62:Spt:192530.0,192448.1] || -> node4(s45)*. % 76.16/76.39 192534[62:MRR:783.0,192532.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 192537[62:Res:53.1,192534.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 192539[62:MRR:192537.0,192438.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 192541[62:Res:192539.0,61.1] always3(s46) || -> . % 76.16/76.39 192542[62:SSi:192541.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 192543[60:Spt:192542.0,192406.0,192409.0] || trans(s49,s45)*+ -> . % 76.16/76.39 192544[60:Spt:192542.0,192406.1,192406.2,192406.3,192406.4,192406.5,192406.6,192406.7,192406.8,192406.9,192406.10,192406.11,192406.12,192406.13,192406.14,192406.15,192406.16,192406.17,192406.18,192406.19,192406.20,192406.21,192406.22,192406.23,192406.24,192406.25,192406.26,192406.27,192406.28,192406.29,192406.30,192406.31,192406.32,192406.33,192406.34,192406.35,192406.36,192406.37,192406.38,192406.39] || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 192546[60:MRR:192408.1,192543.0] xuntil6(s49) || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 192547[61:Spt:192544.0] || -> trans(s49,s44)*. % 76.16/76.39 192548[61:Res:192547.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s44)*. % 76.16/76.39 192550[61:Res:192547.0,60.0] || -> node2(s49,s44)*. % 76.16/76.39 192551[61:SSi:192548.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s44)*. % 76.16/76.39 192552[61:Res:192550.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 192572[61:SoR:192552.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 192574[61:SoR:192572.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)* xuntil6(s49). % 76.16/76.39 192575[61:SSi:192574.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s44,c_busy)* xuntil6(s49). % 76.16/76.39 192576[62:Spt:192575.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 192578[62:Res:192576.0,61.1] always3(s44) || -> . % 76.16/76.39 192579[62:SSi:192578.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 192580[62:Spt:192579.0,192575.1,192576.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.16/76.39 192581[62:Spt:192579.0,192575.0,192575.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 192585[62:MRR:192572.2,192580.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 192586[62:Res:53.1,192581.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 192588[62:MRR:192586.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 192589[62:MRR:192551.0,192588.0] || -> until2p7(s44)*. % 76.16/76.39 192590[62:MRR:539.0,192589.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 192591[63:Spt:192590.0] || -> until2p7(s45)*. % 76.16/76.39 192592[63:MRR:544.0,192591.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 192593[64:Spt:192592.0] || -> until2p7(s46)*. % 76.16/76.39 192594[64:MRR:549.0,192593.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 192595[65:Spt:192594.0] || -> until2p7(s47)*. % 76.16/76.39 192596[65:MRR:554.0,192595.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 192597[66:Spt:192596.0] || -> until2p7(s48)*. % 76.16/76.39 192598[66:MRR:559.0,192597.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 192599[67:Spt:192598.0] || -> until2p7(s49)*. % 76.16/76.39 192600[67:MRR:194.0,192599.0] || -> node4(s49)*. % 76.16/76.39 192601[67:MRR:192585.0,192600.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 192605[67:Res:53.1,192601.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 192607[67:MRR:192605.0,78381.0] || -> . % 76.16/76.39 192608[67:Spt:192607.0,192598.0,192599.0] || until2p7(s49)*+ -> . % 76.16/76.39 192609[67:Spt:192607.0,192598.1] || -> node4(s48)*. % 76.16/76.39 192610[67:MRR:78384.0,192609.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 192613[67:Res:53.1,192610.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192616[67:Res:192613.0,61.1] always3(s48) || -> . % 76.16/76.39 192617[67:SSi:192616.0,78281.0,78387.0,192147.0,192597.0,192609.0] || -> . % 76.16/76.39 192618[66:Spt:192617.0,192596.0,192597.0] || until2p7(s48)*+ -> . % 76.16/76.39 192619[66:Spt:192617.0,192596.1] || -> node4(s47)*. % 76.16/76.39 192621[66:MRR:777.0,192619.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 192633[66:Res:53.1,192621.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 192635[67:Spt:192633.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 192637[67:Res:192635.0,61.1] always3(s47) || -> . % 76.16/76.39 192638[67:SSi:192637.0,78277.0,78280.0,192146.0,192595.0,192619.0] || -> . % 76.16/76.39 192639[67:Spt:192638.0,192633.0,192635.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 192640[67:Spt:192638.0,192633.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192644[67:Res:192640.0,61.1] always3(s48) || -> . % 76.16/76.39 192645[67:SSi:192644.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 192646[65:Spt:192645.0,192594.0,192595.0] || until2p7(s47)*+ -> . % 76.16/76.39 192647[65:Spt:192645.0,192594.1] || -> node4(s46)*. % 76.16/76.39 192649[65:MRR:780.0,192647.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 192656[65:Res:53.1,192649.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 192661[66:Spt:192656.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 192663[66:Res:192661.0,61.1] always3(s46) || -> . % 76.16/76.39 192664[66:SSi:192663.0,78272.0,78276.0,192145.0,192593.0,192647.0] || -> . % 76.16/76.39 192665[66:Spt:192664.0,192656.0,192661.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 192666[66:Spt:192664.0,192656.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 192670[66:Res:192666.0,61.1] always3(s47) || -> . % 76.16/76.39 192671[66:SSi:192670.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 192672[64:Spt:192671.0,192592.0,192593.0] || until2p7(s46)*+ -> . % 76.16/76.39 192673[64:Spt:192671.0,192592.1] || -> node4(s45)*. % 76.16/76.39 192675[64:MRR:783.0,192673.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 192678[64:Res:53.1,192675.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 192680[65:Spt:192678.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 192682[65:Res:192680.0,61.1] always3(s45) || -> . % 76.16/76.39 192683[65:SSi:192682.0,78268.0,78271.0,192144.0,192591.0,192673.0] || -> . % 76.16/76.39 192684[65:Spt:192683.0,192678.0,192680.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 192685[65:Spt:192683.0,192678.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 192689[65:Res:192685.0,61.1] always3(s46) || -> . % 76.16/76.39 192690[65:SSi:192689.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 192691[63:Spt:192690.0,192590.0,192591.0] || until2p7(s45)*+ -> . % 76.16/76.39 192692[63:Spt:192690.0,192590.1] || -> node4(s44)*. % 76.16/76.39 192694[63:MRR:786.0,192692.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 192697[63:Res:53.1,192694.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 192699[63:MRR:192697.0,192580.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 192701[63:Res:192699.0,61.1] always3(s45) || -> . % 76.16/76.39 192702[63:SSi:192701.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 192703[61:Spt:192702.0,192544.0,192547.0] || trans(s49,s44)*+ -> . % 76.16/76.39 192704[61:Spt:192702.0,192544.1,192544.2,192544.3,192544.4,192544.5,192544.6,192544.7,192544.8,192544.9,192544.10,192544.11,192544.12,192544.13,192544.14,192544.15,192544.16,192544.17,192544.18,192544.19,192544.20,192544.21,192544.22,192544.23,192544.24,192544.25,192544.26,192544.27,192544.28,192544.29,192544.30,192544.31,192544.32,192544.33,192544.34,192544.35,192544.36,192544.37,192544.38] || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 192706[61:MRR:192546.1,192703.0] xuntil6(s49) || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 192707[62:Spt:192704.0] || -> trans(s49,s43)*. % 76.16/76.39 192708[62:Res:192707.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s43)*. % 76.16/76.39 192710[62:Res:192707.0,60.0] || -> node2(s49,s43)*. % 76.16/76.39 192711[62:SSi:192708.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s43)*. % 76.16/76.39 192712[62:Res:192710.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 192736[62:SoR:192712.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 192738[62:SoR:192736.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 76.16/76.39 192739[62:SSi:192738.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 76.16/76.39 192740[63:Spt:192739.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 192742[63:Res:192740.0,61.1] always3(s43) || -> . % 76.16/76.39 192743[63:SSi:192742.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 192744[63:Spt:192743.0,192739.1,192740.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.16/76.39 192745[63:Spt:192743.0,192739.0,192739.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 192749[63:MRR:192736.2,192744.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 192750[63:Res:53.1,192745.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 192752[63:MRR:192750.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 192753[63:MRR:192711.0,192752.0] || -> until2p7(s43)*. % 76.16/76.39 192754[63:MRR:241.0,192753.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 192755[64:Spt:192754.0] || -> until2p7(s44)*. % 76.16/76.39 192756[64:MRR:539.0,192755.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 192757[65:Spt:192756.0] || -> until2p7(s45)*. % 76.16/76.39 192758[65:MRR:544.0,192757.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 192759[66:Spt:192758.0] || -> until2p7(s46)*. % 76.16/76.39 192760[66:MRR:549.0,192759.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 192761[67:Spt:192760.0] || -> until2p7(s47)*. % 76.16/76.39 192762[67:MRR:554.0,192761.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 192763[68:Spt:192762.0] || -> until2p7(s48)*. % 76.16/76.39 192764[68:MRR:559.0,192763.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 192765[69:Spt:192764.0] || -> until2p7(s49)*. % 76.16/76.39 192766[69:MRR:194.0,192765.0] || -> node4(s49)*. % 76.16/76.39 192767[69:MRR:192749.0,192766.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 192768[69:Res:53.1,192767.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 192770[69:MRR:192768.0,78381.0] || -> . % 76.16/76.39 192771[69:Spt:192770.0,192764.0,192765.0] || until2p7(s49)*+ -> . % 76.16/76.39 192772[69:Spt:192770.0,192764.1] || -> node4(s48)*. % 76.16/76.39 192773[69:MRR:78384.0,192772.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 192776[69:Res:53.1,192773.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192779[69:Res:192776.0,61.1] always3(s48) || -> . % 76.16/76.39 192780[69:SSi:192779.0,78281.0,78387.0,192147.0,192763.0,192772.0] || -> . % 76.16/76.39 192781[68:Spt:192780.0,192762.0,192763.0] || until2p7(s48)*+ -> . % 76.16/76.39 192782[68:Spt:192780.0,192762.1] || -> node4(s47)*. % 76.16/76.39 192784[68:MRR:777.0,192782.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 192802[68:Res:53.1,192784.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 192804[69:Spt:192802.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 192806[69:Res:192804.0,61.1] always3(s47) || -> . % 76.16/76.39 192807[69:SSi:192806.0,78277.0,78280.0,192146.0,192761.0,192782.0] || -> . % 76.16/76.39 192808[69:Spt:192807.0,192802.0,192804.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 192809[69:Spt:192807.0,192802.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192813[69:Res:192809.0,61.1] always3(s48) || -> . % 76.16/76.39 192814[69:SSi:192813.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 192815[67:Spt:192814.0,192760.0,192761.0] || until2p7(s47)*+ -> . % 76.16/76.39 192816[67:Spt:192814.0,192760.1] || -> node4(s46)*. % 76.16/76.39 192818[67:MRR:780.0,192816.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 192825[67:Res:53.1,192818.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 192830[68:Spt:192825.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 192832[68:Res:192830.0,61.1] always3(s46) || -> . % 76.16/76.39 192833[68:SSi:192832.0,78272.0,78276.0,192145.0,192759.0,192816.0] || -> . % 76.16/76.39 192834[68:Spt:192833.0,192825.0,192830.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 192835[68:Spt:192833.0,192825.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 192839[68:Res:192835.0,61.1] always3(s47) || -> . % 76.16/76.39 192840[68:SSi:192839.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 192841[66:Spt:192840.0,192758.0,192759.0] || until2p7(s46)*+ -> . % 76.16/76.39 192842[66:Spt:192840.0,192758.1] || -> node4(s45)*. % 76.16/76.39 192844[66:MRR:783.0,192842.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 192847[66:Res:53.1,192844.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 192849[67:Spt:192847.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 192851[67:Res:192849.0,61.1] always3(s45) || -> . % 76.16/76.39 192852[67:SSi:192851.0,78268.0,78271.0,192144.0,192757.0,192842.0] || -> . % 76.16/76.39 192853[67:Spt:192852.0,192847.0,192849.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 192854[67:Spt:192852.0,192847.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 192858[67:Res:192854.0,61.1] always3(s46) || -> . % 76.16/76.39 192859[67:SSi:192858.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 192860[65:Spt:192859.0,192756.0,192757.0] || until2p7(s45)*+ -> . % 76.16/76.39 192861[65:Spt:192859.0,192756.1] || -> node4(s44)*. % 76.16/76.39 192863[65:MRR:786.0,192861.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 192866[65:Res:53.1,192863.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 192868[66:Spt:192866.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 192870[66:Res:192868.0,61.1] always3(s44) || -> . % 76.16/76.39 192871[66:SSi:192870.0,78263.0,78267.0,192143.0,192755.0,192861.0] || -> . % 76.16/76.39 192872[66:Spt:192871.0,192866.0,192868.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 192873[66:Spt:192871.0,192866.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 192877[66:Res:192873.0,61.1] always3(s45) || -> . % 76.16/76.39 192878[66:SSi:192877.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 192879[64:Spt:192878.0,192754.0,192755.0] || until2p7(s44)*+ -> . % 76.16/76.39 192880[64:Spt:192878.0,192754.1] || -> node4(s43)*. % 76.16/76.39 192882[64:MRR:789.0,192880.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 192885[64:Res:53.1,192882.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 192887[64:MRR:192885.0,192744.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 192889[64:Res:192887.0,61.1] always3(s44) || -> . % 76.16/76.39 192890[64:SSi:192889.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 192891[62:Spt:192890.0,192704.0,192707.0] || trans(s49,s43)*+ -> . % 76.16/76.39 192892[62:Spt:192890.0,192704.1,192704.2,192704.3,192704.4,192704.5,192704.6,192704.7,192704.8,192704.9,192704.10,192704.11,192704.12,192704.13,192704.14,192704.15,192704.16,192704.17,192704.18,192704.19,192704.20,192704.21,192704.22,192704.23,192704.24,192704.25,192704.26,192704.27,192704.28,192704.29,192704.30,192704.31,192704.32,192704.33,192704.34,192704.35,192704.36,192704.37] || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 192894[62:MRR:192706.1,192891.0] xuntil6(s49) || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 192895[63:Spt:192892.0] || -> trans(s49,s42)*. % 76.16/76.39 192896[63:Res:192895.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s42)*. % 76.16/76.39 192898[63:Res:192895.0,60.0] || -> node2(s49,s42)*. % 76.16/76.39 192899[63:SSi:192896.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s42)*. % 76.16/76.39 192900[63:Res:192898.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 192928[63:SoR:192900.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 192930[63:SoR:192928.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)* xuntil6(s49). % 76.16/76.39 192931[63:SSi:192930.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s42,c_busy)* xuntil6(s49). % 76.16/76.39 192932[64:Spt:192931.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 192934[64:Res:192932.0,61.1] always3(s42) || -> . % 76.16/76.39 192935[64:SSi:192934.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 192936[64:Spt:192935.0,192931.1,192932.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.16/76.39 192937[64:Spt:192935.0,192931.0,192931.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 192941[64:MRR:192928.2,192936.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 192942[64:Res:53.1,192937.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 192944[64:MRR:192942.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 192945[64:MRR:192899.0,192944.0] || -> until2p7(s42)*. % 76.16/76.39 192946[64:MRR:240.0,192945.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 192947[65:Spt:192946.0] || -> until2p7(s43)*. % 76.16/76.39 192948[65:MRR:241.0,192947.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 192949[66:Spt:192948.0] || -> until2p7(s44)*. % 76.16/76.39 192950[66:MRR:539.0,192949.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 192951[67:Spt:192950.0] || -> until2p7(s45)*. % 76.16/76.39 192952[67:MRR:544.0,192951.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 192953[68:Spt:192952.0] || -> until2p7(s46)*. % 76.16/76.39 192954[68:MRR:549.0,192953.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 192955[69:Spt:192954.0] || -> until2p7(s47)*. % 76.16/76.39 192956[69:MRR:554.0,192955.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 192957[70:Spt:192956.0] || -> until2p7(s48)*. % 76.16/76.39 192958[70:MRR:559.0,192957.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 192959[71:Spt:192958.0] || -> until2p7(s49)*. % 76.16/76.39 192960[71:MRR:194.0,192959.0] || -> node4(s49)*. % 76.16/76.39 192961[71:MRR:192941.0,192960.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 192962[71:Res:53.1,192961.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 192964[71:MRR:192962.0,78381.0] || -> . % 76.16/76.39 192965[71:Spt:192964.0,192958.0,192959.0] || until2p7(s49)*+ -> . % 76.16/76.39 192966[71:Spt:192964.0,192958.1] || -> node4(s48)*. % 76.16/76.39 192967[71:MRR:78384.0,192966.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 192970[71:Res:53.1,192967.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 192973[71:Res:192970.0,61.1] always3(s48) || -> . % 76.16/76.39 192974[71:SSi:192973.0,78281.0,78387.0,192147.0,192957.0,192966.0] || -> . % 76.16/76.39 192975[70:Spt:192974.0,192956.0,192957.0] || until2p7(s48)*+ -> . % 76.16/76.39 192976[70:Spt:192974.0,192956.1] || -> node4(s47)*. % 76.16/76.39 192978[70:MRR:777.0,192976.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 192993[70:Res:53.1,192978.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 192998[71:Spt:192993.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 193000[71:Res:192998.0,61.1] always3(s47) || -> . % 76.16/76.39 193001[71:SSi:193000.0,78277.0,78280.0,192146.0,192955.0,192976.0] || -> . % 76.16/76.39 193002[71:Spt:193001.0,192993.0,192998.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 193003[71:Spt:193001.0,192993.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 193007[71:Res:193003.0,61.1] always3(s48) || -> . % 76.16/76.39 193008[71:SSi:193007.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 193009[69:Spt:193008.0,192954.0,192955.0] || until2p7(s47)*+ -> . % 76.16/76.39 193010[69:Spt:193008.0,192954.1] || -> node4(s46)*. % 76.16/76.39 193012[69:MRR:780.0,193010.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 193019[69:Res:53.1,193012.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 193021[70:Spt:193019.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 193023[70:Res:193021.0,61.1] always3(s46) || -> . % 76.16/76.39 193024[70:SSi:193023.0,78272.0,78276.0,192145.0,192953.0,193010.0] || -> . % 76.16/76.39 193025[70:Spt:193024.0,193019.0,193021.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 193026[70:Spt:193024.0,193019.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 193030[70:Res:193026.0,61.1] always3(s47) || -> . % 76.16/76.39 193031[70:SSi:193030.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 193032[68:Spt:193031.0,192952.0,192953.0] || until2p7(s46)*+ -> . % 76.16/76.39 193033[68:Spt:193031.0,192952.1] || -> node4(s45)*. % 76.16/76.39 193035[68:MRR:783.0,193033.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 193038[68:Res:53.1,193035.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 193043[69:Spt:193038.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 193045[69:Res:193043.0,61.1] always3(s45) || -> . % 76.16/76.39 193046[69:SSi:193045.0,78268.0,78271.0,192144.0,192951.0,193033.0] || -> . % 76.16/76.39 193047[69:Spt:193046.0,193038.0,193043.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 193048[69:Spt:193046.0,193038.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 193052[69:Res:193048.0,61.1] always3(s46) || -> . % 76.16/76.39 193053[69:SSi:193052.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 193054[67:Spt:193053.0,192950.0,192951.0] || until2p7(s45)*+ -> . % 76.16/76.39 193055[67:Spt:193053.0,192950.1] || -> node4(s44)*. % 76.16/76.39 193057[67:MRR:786.0,193055.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 193060[67:Res:53.1,193057.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 193062[68:Spt:193060.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 193064[68:Res:193062.0,61.1] always3(s44) || -> . % 76.16/76.39 193065[68:SSi:193064.0,78263.0,78267.0,192143.0,192949.0,193055.0] || -> . % 76.16/76.39 193066[68:Spt:193065.0,193060.0,193062.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 193067[68:Spt:193065.0,193060.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 193071[68:Res:193067.0,61.1] always3(s45) || -> . % 76.16/76.39 193072[68:SSi:193071.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 193073[66:Spt:193072.0,192948.0,192949.0] || until2p7(s44)*+ -> . % 76.16/76.39 193074[66:Spt:193072.0,192948.1] || -> node4(s43)*. % 76.16/76.39 193076[66:MRR:789.0,193074.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 193079[66:Res:53.1,193076.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 193081[67:Spt:193079.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 193083[67:Res:193081.0,61.1] always3(s43) || -> . % 76.16/76.39 193084[67:SSi:193083.0,78259.0,78262.0,192142.0,192947.0,193074.0] || -> . % 76.16/76.39 193085[67:Spt:193084.0,193079.0,193081.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 193086[67:Spt:193084.0,193079.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 193090[67:Res:193086.0,61.1] always3(s44) || -> . % 76.16/76.39 193091[67:SSi:193090.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 193092[65:Spt:193091.0,192946.0,192947.0] || until2p7(s43)*+ -> . % 76.16/76.39 193093[65:Spt:193091.0,192946.1] || -> node4(s42)*. % 76.16/76.39 193095[65:MRR:792.0,193093.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 193098[65:Res:53.1,193095.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 193100[65:MRR:193098.0,192936.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 193102[65:Res:193100.0,61.1] always3(s43) || -> . % 76.16/76.39 193103[65:SSi:193102.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 193104[63:Spt:193103.0,192892.0,192895.0] || trans(s49,s42)*+ -> . % 76.16/76.39 193105[63:Spt:193103.0,192892.1,192892.2,192892.3,192892.4,192892.5,192892.6,192892.7,192892.8,192892.9,192892.10,192892.11,192892.12,192892.13,192892.14,192892.15,192892.16,192892.17,192892.18,192892.19,192892.20,192892.21,192892.22,192892.23,192892.24,192892.25,192892.26,192892.27,192892.28,192892.29,192892.30,192892.31,192892.32,192892.33,192892.34,192892.35,192892.36] || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 193107[63:MRR:192894.1,193104.0] xuntil6(s49) || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 193108[64:Spt:193105.0] || -> trans(s49,s41)*. % 76.16/76.39 193109[64:Res:193108.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s41)*. % 76.16/76.39 193111[64:Res:193108.0,60.0] || -> node2(s49,s41)*. % 76.16/76.39 193112[64:SSi:193109.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s41)*. % 76.16/76.39 193113[64:Res:193111.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 193142[64:SoR:193113.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 193144[64:SoR:193142.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)* xuntil6(s49). % 76.16/76.39 193145[64:SSi:193144.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s41,c_busy)* xuntil6(s49). % 76.16/76.39 193146[65:Spt:193145.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 193148[65:Res:193146.0,61.1] always3(s41) || -> . % 76.16/76.39 193149[65:SSi:193148.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 193150[65:Spt:193149.0,193145.1,193146.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.16/76.39 193151[65:Spt:193149.0,193145.0,193145.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 193155[65:MRR:193142.2,193150.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 193156[65:Res:53.1,193151.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 193158[65:MRR:193156.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 193159[65:MRR:193112.0,193158.0] || -> until2p7(s41)*. % 76.16/76.39 193160[65:MRR:239.0,193159.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 193161[66:Spt:193160.0] || -> until2p7(s42)*. % 76.16/76.39 193162[66:MRR:240.0,193161.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 193163[67:Spt:193162.0] || -> until2p7(s43)*. % 76.16/76.39 193164[67:MRR:241.0,193163.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 193165[68:Spt:193164.0] || -> until2p7(s44)*. % 76.16/76.39 193166[68:MRR:539.0,193165.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 193167[69:Spt:193166.0] || -> until2p7(s45)*. % 76.16/76.39 193168[69:MRR:544.0,193167.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 193169[70:Spt:193168.0] || -> until2p7(s46)*. % 76.16/76.39 193170[70:MRR:549.0,193169.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 193171[71:Spt:193170.0] || -> until2p7(s47)*. % 76.16/76.39 193172[71:MRR:554.0,193171.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 193173[72:Spt:193172.0] || -> until2p7(s48)*. % 76.16/76.39 193174[72:MRR:559.0,193173.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 193175[73:Spt:193174.0] || -> until2p7(s49)*. % 76.16/76.39 193176[73:MRR:194.0,193175.0] || -> node4(s49)*. % 76.16/76.39 193177[73:MRR:193155.0,193176.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 193181[73:Res:53.1,193177.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 193183[73:MRR:193181.0,78381.0] || -> . % 76.16/76.39 193184[73:Spt:193183.0,193174.0,193175.0] || until2p7(s49)*+ -> . % 76.16/76.39 193185[73:Spt:193183.0,193174.1] || -> node4(s48)*. % 76.16/76.39 193186[73:MRR:78384.0,193185.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 193189[73:Res:53.1,193186.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 193192[73:Res:193189.0,61.1] always3(s48) || -> . % 76.16/76.39 193193[73:SSi:193192.0,78281.0,78387.0,192147.0,193173.0,193185.0] || -> . % 76.16/76.39 193194[72:Spt:193193.0,193172.0,193173.0] || until2p7(s48)*+ -> . % 76.16/76.39 193195[72:Spt:193193.0,193172.1] || -> node4(s47)*. % 76.16/76.39 193197[72:MRR:777.0,193195.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 193209[72:Res:53.1,193197.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 193211[73:Spt:193209.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 193213[73:Res:193211.0,61.1] always3(s47) || -> . % 76.16/76.39 193214[73:SSi:193213.0,78277.0,78280.0,192146.0,193171.0,193195.0] || -> . % 76.16/76.39 193215[73:Spt:193214.0,193209.0,193211.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 193216[73:Spt:193214.0,193209.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 193220[73:Res:193216.0,61.1] always3(s48) || -> . % 76.16/76.39 193221[73:SSi:193220.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 193222[71:Spt:193221.0,193170.0,193171.0] || until2p7(s47)*+ -> . % 76.16/76.39 193223[71:Spt:193221.0,193170.1] || -> node4(s46)*. % 76.16/76.39 193225[71:MRR:780.0,193223.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 193232[71:Res:53.1,193225.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 193237[72:Spt:193232.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 193239[72:Res:193237.0,61.1] always3(s46) || -> . % 76.16/76.39 193240[72:SSi:193239.0,78272.0,78276.0,192145.0,193169.0,193223.0] || -> . % 76.16/76.39 193241[72:Spt:193240.0,193232.0,193237.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 193242[72:Spt:193240.0,193232.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 193246[72:Res:193242.0,61.1] always3(s47) || -> . % 76.16/76.39 193247[72:SSi:193246.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 193248[70:Spt:193247.0,193168.0,193169.0] || until2p7(s46)*+ -> . % 76.16/76.39 193249[70:Spt:193247.0,193168.1] || -> node4(s45)*. % 76.16/76.39 193251[70:MRR:783.0,193249.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 193254[70:Res:53.1,193251.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 193256[71:Spt:193254.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 193258[71:Res:193256.0,61.1] always3(s45) || -> . % 76.16/76.39 193259[71:SSi:193258.0,78268.0,78271.0,192144.0,193167.0,193249.0] || -> . % 76.16/76.39 193260[71:Spt:193259.0,193254.0,193256.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 193261[71:Spt:193259.0,193254.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 193265[71:Res:193261.0,61.1] always3(s46) || -> . % 76.16/76.39 193266[71:SSi:193265.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 193267[69:Spt:193266.0,193166.0,193167.0] || until2p7(s45)*+ -> . % 76.16/76.39 193268[69:Spt:193266.0,193166.1] || -> node4(s44)*. % 76.16/76.39 193270[69:MRR:786.0,193268.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 193273[69:Res:53.1,193270.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 193275[70:Spt:193273.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 193277[70:Res:193275.0,61.1] always3(s44) || -> . % 76.16/76.39 193278[70:SSi:193277.0,78263.0,78267.0,192143.0,193165.0,193268.0] || -> . % 76.16/76.39 193279[70:Spt:193278.0,193273.0,193275.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 193280[70:Spt:193278.0,193273.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 193284[70:Res:193280.0,61.1] always3(s45) || -> . % 76.16/76.39 193285[70:SSi:193284.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 193286[68:Spt:193285.0,193164.0,193165.0] || until2p7(s44)*+ -> . % 76.16/76.39 193287[68:Spt:193285.0,193164.1] || -> node4(s43)*. % 76.16/76.39 193289[68:MRR:789.0,193287.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 193292[68:Res:53.1,193289.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 193294[69:Spt:193292.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 193296[69:Res:193294.0,61.1] always3(s43) || -> . % 76.16/76.39 193297[69:SSi:193296.0,78259.0,78262.0,192142.0,193163.0,193287.0] || -> . % 76.16/76.39 193298[69:Spt:193297.0,193292.0,193294.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 193299[69:Spt:193297.0,193292.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 193303[69:Res:193299.0,61.1] always3(s44) || -> . % 76.16/76.39 193304[69:SSi:193303.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 193305[67:Spt:193304.0,193162.0,193163.0] || until2p7(s43)*+ -> . % 76.16/76.39 193306[67:Spt:193304.0,193162.1] || -> node4(s42)*. % 76.16/76.39 193308[67:MRR:792.0,193306.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 193311[67:Res:53.1,193308.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 193316[68:Spt:193311.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 193318[68:Res:193316.0,61.1] always3(s42) || -> . % 76.16/76.39 193319[68:SSi:193318.0,78254.0,78258.0,192141.0,193161.0,193306.0] || -> . % 76.16/76.39 193320[68:Spt:193319.0,193311.0,193316.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 193321[68:Spt:193319.0,193311.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 193325[68:Res:193321.0,61.1] always3(s43) || -> . % 76.16/76.39 193326[68:SSi:193325.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 193327[66:Spt:193326.0,193160.0,193161.0] || until2p7(s42)*+ -> . % 76.16/76.39 193328[66:Spt:193326.0,193160.1] || -> node4(s41)*. % 76.16/76.39 193330[66:MRR:795.0,193328.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 193333[66:Res:53.1,193330.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 193335[66:MRR:193333.0,193150.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 193337[66:Res:193335.0,61.1] always3(s42) || -> . % 76.16/76.39 193338[66:SSi:193337.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 193339[64:Spt:193338.0,193105.0,193108.0] || trans(s49,s41)*+ -> . % 76.16/76.39 193340[64:Spt:193338.0,193105.1,193105.2,193105.3,193105.4,193105.5,193105.6,193105.7,193105.8,193105.9,193105.10,193105.11,193105.12,193105.13,193105.14,193105.15,193105.16,193105.17,193105.18,193105.19,193105.20,193105.21,193105.22,193105.23,193105.24,193105.25,193105.26,193105.27,193105.28,193105.29,193105.30,193105.31,193105.32,193105.33,193105.34,193105.35] || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 193342[64:MRR:193107.1,193339.0] xuntil6(s49) || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 193343[65:Spt:193340.0] || -> trans(s49,s40)*. % 76.16/76.39 193344[65:Res:193343.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s40)*. % 76.16/76.39 193346[65:Res:193343.0,60.0] || -> node2(s49,s40)*. % 76.16/76.39 193347[65:SSi:193344.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s40)*. % 76.16/76.39 193348[65:Res:193346.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 193381[65:SoR:193348.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 193383[65:SoR:193381.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)* xuntil6(s49). % 76.16/76.39 193384[65:SSi:193383.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s40,c_busy)* xuntil6(s49). % 76.16/76.39 193385[66:Spt:193384.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 193387[66:Res:193385.0,61.1] always3(s40) || -> . % 76.16/76.39 193388[66:SSi:193387.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 193389[66:Spt:193388.0,193384.1,193385.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.16/76.39 193390[66:Spt:193388.0,193384.0,193384.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 193394[66:MRR:193381.2,193389.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 193395[66:Res:53.1,193390.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 193397[66:MRR:193395.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 193398[66:MRR:193347.0,193397.0] || -> until2p7(s40)*. % 76.16/76.39 193399[66:MRR:238.0,193398.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 193400[67:Spt:193399.0] || -> until2p7(s41)*. % 76.16/76.39 193401[67:MRR:239.0,193400.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 193402[68:Spt:193401.0] || -> until2p7(s42)*. % 76.16/76.39 193403[68:MRR:240.0,193402.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 193404[69:Spt:193403.0] || -> until2p7(s43)*. % 76.16/76.39 193405[69:MRR:241.0,193404.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 193406[70:Spt:193405.0] || -> until2p7(s44)*. % 76.16/76.39 193407[70:MRR:539.0,193406.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 193408[71:Spt:193407.0] || -> until2p7(s45)*. % 76.16/76.39 193409[71:MRR:544.0,193408.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 193410[72:Spt:193409.0] || -> until2p7(s46)*. % 76.16/76.39 193411[72:MRR:549.0,193410.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 193412[73:Spt:193411.0] || -> until2p7(s47)*. % 76.16/76.39 193413[73:MRR:554.0,193412.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 193414[74:Spt:193413.0] || -> until2p7(s48)*. % 76.16/76.39 193415[74:MRR:559.0,193414.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 193416[75:Spt:193415.0] || -> until2p7(s49)*. % 76.16/76.39 193417[75:MRR:194.0,193416.0] || -> node4(s49)*. % 76.16/76.39 193418[75:MRR:193394.0,193417.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 193419[75:Res:53.1,193418.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 193421[75:MRR:193419.0,78381.0] || -> . % 76.16/76.39 193422[75:Spt:193421.0,193415.0,193416.0] || until2p7(s49)*+ -> . % 76.16/76.39 193423[75:Spt:193421.0,193415.1] || -> node4(s48)*. % 76.16/76.39 193424[75:MRR:78384.0,193423.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 193427[75:Res:53.1,193424.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 193430[75:Res:193427.0,61.1] always3(s48) || -> . % 76.16/76.39 193431[75:SSi:193430.0,78281.0,78387.0,192147.0,193414.0,193423.0] || -> . % 76.16/76.39 193432[74:Spt:193431.0,193413.0,193414.0] || until2p7(s48)*+ -> . % 76.16/76.39 193433[74:Spt:193431.0,193413.1] || -> node4(s47)*. % 76.16/76.39 193435[74:MRR:777.0,193433.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 193450[74:Res:53.1,193435.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 193452[75:Spt:193450.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 193454[75:Res:193452.0,61.1] always3(s47) || -> . % 76.16/76.39 193455[75:SSi:193454.0,78277.0,78280.0,192146.0,193412.0,193433.0] || -> . % 76.16/76.39 193456[75:Spt:193455.0,193450.0,193452.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 193457[75:Spt:193455.0,193450.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 193461[75:Res:193457.0,61.1] always3(s48) || -> . % 76.16/76.39 193462[75:SSi:193461.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 193463[73:Spt:193462.0,193411.0,193412.0] || until2p7(s47)*+ -> . % 76.16/76.39 193464[73:Spt:193462.0,193411.1] || -> node4(s46)*. % 76.16/76.39 193466[73:MRR:780.0,193464.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 193476[73:Res:53.1,193466.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 193478[74:Spt:193476.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 193480[74:Res:193478.0,61.1] always3(s46) || -> . % 76.16/76.39 193481[74:SSi:193480.0,78272.0,78276.0,192145.0,193410.0,193464.0] || -> . % 76.16/76.39 193482[74:Spt:193481.0,193476.0,193478.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 193483[74:Spt:193481.0,193476.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 193487[74:Res:193483.0,61.1] always3(s47) || -> . % 76.16/76.39 193488[74:SSi:193487.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 193489[72:Spt:193488.0,193409.0,193410.0] || until2p7(s46)*+ -> . % 76.16/76.39 193490[72:Spt:193488.0,193409.1] || -> node4(s45)*. % 76.16/76.39 193492[72:MRR:783.0,193490.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 193495[72:Res:53.1,193492.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 193497[73:Spt:193495.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 193499[73:Res:193497.0,61.1] always3(s45) || -> . % 76.16/76.39 193500[73:SSi:193499.0,78268.0,78271.0,192144.0,193408.0,193490.0] || -> . % 76.16/76.39 193501[73:Spt:193500.0,193495.0,193497.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 193502[73:Spt:193500.0,193495.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 193506[73:Res:193502.0,61.1] always3(s46) || -> . % 76.16/76.39 193507[73:SSi:193506.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 193508[71:Spt:193507.0,193407.0,193408.0] || until2p7(s45)*+ -> . % 76.16/76.39 193509[71:Spt:193507.0,193407.1] || -> node4(s44)*. % 76.16/76.39 193511[71:MRR:786.0,193509.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 193514[71:Res:53.1,193511.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 193516[72:Spt:193514.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 193518[72:Res:193516.0,61.1] always3(s44) || -> . % 76.16/76.39 193519[72:SSi:193518.0,78263.0,78267.0,192143.0,193406.0,193509.0] || -> . % 76.16/76.39 193520[72:Spt:193519.0,193514.0,193516.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 193521[72:Spt:193519.0,193514.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 193525[72:Res:193521.0,61.1] always3(s45) || -> . % 76.16/76.39 193526[72:SSi:193525.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 193527[70:Spt:193526.0,193405.0,193406.0] || until2p7(s44)*+ -> . % 76.16/76.39 193528[70:Spt:193526.0,193405.1] || -> node4(s43)*. % 76.16/76.39 193530[70:MRR:789.0,193528.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 193533[70:Res:53.1,193530.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 193538[71:Spt:193533.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 193540[71:Res:193538.0,61.1] always3(s43) || -> . % 76.16/76.39 193541[71:SSi:193540.0,78259.0,78262.0,192142.0,193404.0,193528.0] || -> . % 76.16/76.39 193542[71:Spt:193541.0,193533.0,193538.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 193543[71:Spt:193541.0,193533.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 193547[71:Res:193543.0,61.1] always3(s44) || -> . % 76.16/76.39 193548[71:SSi:193547.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 193549[69:Spt:193548.0,193403.0,193404.0] || until2p7(s43)*+ -> . % 76.16/76.39 193550[69:Spt:193548.0,193403.1] || -> node4(s42)*. % 76.16/76.39 193552[69:MRR:792.0,193550.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 193555[69:Res:53.1,193552.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 193557[70:Spt:193555.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 193559[70:Res:193557.0,61.1] always3(s42) || -> . % 76.16/76.39 193560[70:SSi:193559.0,78254.0,78258.0,192141.0,193402.0,193550.0] || -> . % 76.16/76.39 193561[70:Spt:193560.0,193555.0,193557.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 193562[70:Spt:193560.0,193555.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 193566[70:Res:193562.0,61.1] always3(s43) || -> . % 76.16/76.39 193567[70:SSi:193566.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 193568[68:Spt:193567.0,193401.0,193402.0] || until2p7(s42)*+ -> . % 76.16/76.39 193569[68:Spt:193567.0,193401.1] || -> node4(s41)*. % 76.16/76.39 193571[68:MRR:795.0,193569.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 193574[68:Res:53.1,193571.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 193576[69:Spt:193574.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 193578[69:Res:193576.0,61.1] always3(s41) || -> . % 76.16/76.39 193579[69:SSi:193578.0,78250.0,78253.0,192140.0,193400.0,193569.0] || -> . % 76.16/76.39 193580[69:Spt:193579.0,193574.0,193576.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 193581[69:Spt:193579.0,193574.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 193585[69:Res:193581.0,61.1] always3(s42) || -> . % 76.16/76.39 193586[69:SSi:193585.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 193587[67:Spt:193586.0,193399.0,193400.0] || until2p7(s41)*+ -> . % 76.16/76.39 193588[67:Spt:193586.0,193399.1] || -> node4(s40)*. % 76.16/76.39 193590[67:MRR:798.0,193588.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 193593[67:Res:53.1,193590.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 193595[67:MRR:193593.0,193389.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 193597[67:Res:193595.0,61.1] always3(s41) || -> . % 76.16/76.39 193598[67:SSi:193597.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 193599[65:Spt:193598.0,193340.0,193343.0] || trans(s49,s40)*+ -> . % 76.16/76.39 193600[65:Spt:193598.0,193340.1,193340.2,193340.3,193340.4,193340.5,193340.6,193340.7,193340.8,193340.9,193340.10,193340.11,193340.12,193340.13,193340.14,193340.15,193340.16,193340.17,193340.18,193340.19,193340.20,193340.21,193340.22,193340.23,193340.24,193340.25,193340.26,193340.27,193340.28,193340.29,193340.30,193340.31,193340.32,193340.33,193340.34] || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 193602[65:MRR:193342.1,193599.0] xuntil6(s49) || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 193603[66:Spt:193600.0] || -> trans(s49,s39)*. % 76.16/76.39 193604[66:Res:193603.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s39)*. % 76.16/76.39 193606[66:Res:193603.0,60.0] || -> node2(s49,s39)*. % 76.16/76.39 193607[66:SSi:193604.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s39)*. % 76.16/76.39 193608[66:Res:193606.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 193645[66:SoR:193608.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 193647[66:SoR:193645.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 76.16/76.39 193648[66:SSi:193647.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 76.16/76.39 193649[67:Spt:193648.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 193651[67:Res:193649.0,61.1] always3(s39) || -> . % 76.16/76.39 193652[67:SSi:193651.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 193653[67:Spt:193652.0,193648.1,193649.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.16/76.39 193654[67:Spt:193652.0,193648.0,193648.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 193658[67:MRR:193645.2,193653.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 193659[67:Res:53.1,193654.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 193661[67:MRR:193659.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 193662[67:MRR:193607.0,193661.0] || -> until2p7(s39)*. % 76.16/76.39 193663[67:MRR:237.0,193662.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 193664[68:Spt:193663.0] || -> until2p7(s40)*. % 76.16/76.39 193665[68:MRR:238.0,193664.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 193666[69:Spt:193665.0] || -> until2p7(s41)*. % 76.16/76.39 193667[69:MRR:239.0,193666.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 193668[70:Spt:193667.0] || -> until2p7(s42)*. % 76.16/76.39 193669[70:MRR:240.0,193668.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 193670[71:Spt:193669.0] || -> until2p7(s43)*. % 76.16/76.39 193671[71:MRR:241.0,193670.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 193672[72:Spt:193671.0] || -> until2p7(s44)*. % 76.16/76.39 193673[72:MRR:539.0,193672.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 193674[73:Spt:193673.0] || -> until2p7(s45)*. % 76.16/76.39 193675[73:MRR:544.0,193674.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 193676[74:Spt:193675.0] || -> until2p7(s46)*. % 76.16/76.39 193677[74:MRR:549.0,193676.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 193678[75:Spt:193677.0] || -> until2p7(s47)*. % 76.16/76.39 193679[75:MRR:554.0,193678.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 193680[76:Spt:193679.0] || -> until2p7(s48)*. % 76.16/76.39 193681[76:MRR:559.0,193680.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 193682[77:Spt:193681.0] || -> until2p7(s49)*. % 76.16/76.39 193683[77:MRR:194.0,193682.0] || -> node4(s49)*. % 76.16/76.39 193684[77:MRR:193658.0,193683.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 193685[77:Res:53.1,193684.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 193687[77:MRR:193685.0,78381.0] || -> . % 76.16/76.39 193688[77:Spt:193687.0,193681.0,193682.0] || until2p7(s49)*+ -> . % 76.16/76.39 193689[77:Spt:193687.0,193681.1] || -> node4(s48)*. % 76.16/76.39 193690[77:MRR:78384.0,193689.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 193693[77:Res:53.1,193690.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 193696[77:Res:193693.0,61.1] always3(s48) || -> . % 76.16/76.39 193697[77:SSi:193696.0,78281.0,78387.0,192147.0,193680.0,193689.0] || -> . % 76.16/76.39 193698[76:Spt:193697.0,193679.0,193680.0] || until2p7(s48)*+ -> . % 76.16/76.39 193699[76:Spt:193697.0,193679.1] || -> node4(s47)*. % 76.16/76.39 193701[76:MRR:777.0,193699.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 193716[76:Res:53.1,193701.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 193718[77:Spt:193716.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 193720[77:Res:193718.0,61.1] always3(s47) || -> . % 76.16/76.39 193721[77:SSi:193720.0,78277.0,78280.0,192146.0,193678.0,193699.0] || -> . % 76.16/76.39 193722[77:Spt:193721.0,193716.0,193718.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 193723[77:Spt:193721.0,193716.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 193727[77:Res:193723.0,61.1] always3(s48) || -> . % 76.16/76.39 193728[77:SSi:193727.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 193729[75:Spt:193728.0,193677.0,193678.0] || until2p7(s47)*+ -> . % 76.16/76.39 193730[75:Spt:193728.0,193677.1] || -> node4(s46)*. % 76.16/76.39 193732[75:MRR:780.0,193730.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 193742[75:Res:53.1,193732.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 193744[76:Spt:193742.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 193746[76:Res:193744.0,61.1] always3(s46) || -> . % 76.16/76.39 193747[76:SSi:193746.0,78272.0,78276.0,192145.0,193676.0,193730.0] || -> . % 76.16/76.39 193748[76:Spt:193747.0,193742.0,193744.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 193749[76:Spt:193747.0,193742.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 193753[76:Res:193749.0,61.1] always3(s47) || -> . % 76.16/76.39 193754[76:SSi:193753.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 193755[74:Spt:193754.0,193675.0,193676.0] || until2p7(s46)*+ -> . % 76.16/76.39 193756[74:Spt:193754.0,193675.1] || -> node4(s45)*. % 76.16/76.39 193758[74:MRR:783.0,193756.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 193761[74:Res:53.1,193758.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 193763[75:Spt:193761.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 193765[75:Res:193763.0,61.1] always3(s45) || -> . % 76.16/76.39 193766[75:SSi:193765.0,78268.0,78271.0,192144.0,193674.0,193756.0] || -> . % 76.16/76.39 193767[75:Spt:193766.0,193761.0,193763.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 193768[75:Spt:193766.0,193761.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 193772[75:Res:193768.0,61.1] always3(s46) || -> . % 76.16/76.39 193773[75:SSi:193772.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 193774[73:Spt:193773.0,193673.0,193674.0] || until2p7(s45)*+ -> . % 76.16/76.39 193775[73:Spt:193773.0,193673.1] || -> node4(s44)*. % 76.16/76.39 193777[73:MRR:786.0,193775.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 193780[73:Res:53.1,193777.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 193782[74:Spt:193780.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 193784[74:Res:193782.0,61.1] always3(s44) || -> . % 76.16/76.39 193785[74:SSi:193784.0,78263.0,78267.0,192143.0,193672.0,193775.0] || -> . % 76.16/76.39 193786[74:Spt:193785.0,193780.0,193782.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 193787[74:Spt:193785.0,193780.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 193791[74:Res:193787.0,61.1] always3(s45) || -> . % 76.16/76.39 193792[74:SSi:193791.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 193793[72:Spt:193792.0,193671.0,193672.0] || until2p7(s44)*+ -> . % 76.16/76.39 193794[72:Spt:193792.0,193671.1] || -> node4(s43)*. % 76.16/76.39 193796[72:MRR:789.0,193794.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 193799[72:Res:53.1,193796.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 193804[73:Spt:193799.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 193806[73:Res:193804.0,61.1] always3(s43) || -> . % 76.16/76.39 193807[73:SSi:193806.0,78259.0,78262.0,192142.0,193670.0,193794.0] || -> . % 76.16/76.39 193808[73:Spt:193807.0,193799.0,193804.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 193809[73:Spt:193807.0,193799.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 193813[73:Res:193809.0,61.1] always3(s44) || -> . % 76.16/76.39 193814[73:SSi:193813.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 193815[71:Spt:193814.0,193669.0,193670.0] || until2p7(s43)*+ -> . % 76.16/76.39 193816[71:Spt:193814.0,193669.1] || -> node4(s42)*. % 76.16/76.39 193818[71:MRR:792.0,193816.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 193821[71:Res:53.1,193818.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 193823[72:Spt:193821.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 193825[72:Res:193823.0,61.1] always3(s42) || -> . % 76.16/76.39 193826[72:SSi:193825.0,78254.0,78258.0,192141.0,193668.0,193816.0] || -> . % 76.16/76.39 193827[72:Spt:193826.0,193821.0,193823.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 193828[72:Spt:193826.0,193821.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 193832[72:Res:193828.0,61.1] always3(s43) || -> . % 76.16/76.39 193833[72:SSi:193832.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 193834[70:Spt:193833.0,193667.0,193668.0] || until2p7(s42)*+ -> . % 76.16/76.39 193835[70:Spt:193833.0,193667.1] || -> node4(s41)*. % 76.16/76.39 193837[70:MRR:795.0,193835.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 193840[70:Res:53.1,193837.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 193842[71:Spt:193840.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 193844[71:Res:193842.0,61.1] always3(s41) || -> . % 76.16/76.39 193845[71:SSi:193844.0,78250.0,78253.0,192140.0,193666.0,193835.0] || -> . % 76.16/76.39 193846[71:Spt:193845.0,193840.0,193842.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 193847[71:Spt:193845.0,193840.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 193851[71:Res:193847.0,61.1] always3(s42) || -> . % 76.16/76.39 193852[71:SSi:193851.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 193853[69:Spt:193852.0,193665.0,193666.0] || until2p7(s41)*+ -> . % 76.16/76.39 193854[69:Spt:193852.0,193665.1] || -> node4(s40)*. % 76.16/76.39 193856[69:MRR:798.0,193854.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 193859[69:Res:53.1,193856.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 193861[70:Spt:193859.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 193863[70:Res:193861.0,61.1] always3(s40) || -> . % 76.16/76.39 193864[70:SSi:193863.0,78245.0,78249.0,192139.0,193664.0,193854.0] || -> . % 76.16/76.39 193865[70:Spt:193864.0,193859.0,193861.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 193866[70:Spt:193864.0,193859.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 193870[70:Res:193866.0,61.1] always3(s41) || -> . % 76.16/76.39 193871[70:SSi:193870.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 193872[68:Spt:193871.0,193663.0,193664.0] || until2p7(s40)*+ -> . % 76.16/76.39 193873[68:Spt:193871.0,193663.1] || -> node4(s39)*. % 76.16/76.39 193875[68:MRR:801.0,193873.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 193878[68:Res:53.1,193875.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 193880[68:MRR:193878.0,193653.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 193885[68:Res:193880.0,61.1] always3(s40) || -> . % 76.16/76.39 193886[68:SSi:193885.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 193887[66:Spt:193886.0,193600.0,193603.0] || trans(s49,s39)*+ -> . % 76.16/76.39 193888[66:Spt:193886.0,193600.1,193600.2,193600.3,193600.4,193600.5,193600.6,193600.7,193600.8,193600.9,193600.10,193600.11,193600.12,193600.13,193600.14,193600.15,193600.16,193600.17,193600.18,193600.19,193600.20,193600.21,193600.22,193600.23,193600.24,193600.25,193600.26,193600.27,193600.28,193600.29,193600.30,193600.31,193600.32,193600.33] || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 193890[66:MRR:193602.1,193887.0] xuntil6(s49) || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 193891[67:Spt:193888.0] || -> trans(s49,s38)*. % 76.16/76.39 193892[67:Res:193891.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s38)*. % 76.16/76.39 193894[67:Res:193891.0,60.0] || -> node2(s49,s38)*. % 76.16/76.39 193895[67:SSi:193892.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s38)*. % 76.16/76.39 193896[67:Res:193894.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 193934[67:SoR:193896.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 193936[67:SoR:193934.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)* xuntil6(s49). % 76.16/76.39 193937[67:SSi:193936.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s38,c_busy)* xuntil6(s49). % 76.16/76.39 193938[68:Spt:193937.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 193940[68:Res:193938.0,61.1] always3(s38) || -> . % 76.16/76.39 193941[68:SSi:193940.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.39 193942[68:Spt:193941.0,193937.1,193938.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.16/76.39 193943[68:Spt:193941.0,193937.0,193937.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 193947[68:MRR:193934.2,193942.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 193948[68:Res:53.1,193943.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 193950[68:MRR:193948.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 193951[68:MRR:193895.0,193950.0] || -> until2p7(s38)*. % 76.16/76.39 193952[68:MRR:236.0,193951.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 193953[69:Spt:193952.0] || -> until2p7(s39)*. % 76.16/76.39 193954[69:MRR:237.0,193953.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 193955[70:Spt:193954.0] || -> until2p7(s40)*. % 76.16/76.39 193956[70:MRR:238.0,193955.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 193957[71:Spt:193956.0] || -> until2p7(s41)*. % 76.16/76.39 193958[71:MRR:239.0,193957.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 193959[72:Spt:193958.0] || -> until2p7(s42)*. % 76.16/76.39 193960[72:MRR:240.0,193959.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 193961[73:Spt:193960.0] || -> until2p7(s43)*. % 76.16/76.39 193962[73:MRR:241.0,193961.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 193963[74:Spt:193962.0] || -> until2p7(s44)*. % 76.16/76.39 193964[74:MRR:539.0,193963.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 193965[75:Spt:193964.0] || -> until2p7(s45)*. % 76.16/76.39 193966[75:MRR:544.0,193965.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 193967[76:Spt:193966.0] || -> until2p7(s46)*. % 76.16/76.39 193968[76:MRR:549.0,193967.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 193969[77:Spt:193968.0] || -> until2p7(s47)*. % 76.16/76.39 193970[77:MRR:554.0,193969.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 193971[78:Spt:193970.0] || -> until2p7(s48)*. % 76.16/76.39 193972[78:MRR:559.0,193971.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 193973[79:Spt:193972.0] || -> until2p7(s49)*. % 76.16/76.39 193974[79:MRR:194.0,193973.0] || -> node4(s49)*. % 76.16/76.39 193975[79:MRR:193947.0,193974.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 193979[79:Res:53.1,193975.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 193981[79:MRR:193979.0,78381.0] || -> . % 76.16/76.39 193982[79:Spt:193981.0,193972.0,193973.0] || until2p7(s49)*+ -> . % 76.16/76.39 193983[79:Spt:193981.0,193972.1] || -> node4(s48)*. % 76.16/76.39 193984[79:MRR:78384.0,193983.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 193987[79:Res:53.1,193984.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 193990[79:Res:193987.0,61.1] always3(s48) || -> . % 76.16/76.39 193991[79:SSi:193990.0,78281.0,78387.0,192147.0,193971.0,193983.0] || -> . % 76.16/76.39 193992[78:Spt:193991.0,193970.0,193971.0] || until2p7(s48)*+ -> . % 76.16/76.39 193993[78:Spt:193991.0,193970.1] || -> node4(s47)*. % 76.16/76.39 193995[78:MRR:777.0,193993.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 194007[78:Res:53.1,193995.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 194009[79:Spt:194007.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 194011[79:Res:194009.0,61.1] always3(s47) || -> . % 76.16/76.39 194012[79:SSi:194011.0,78277.0,78280.0,192146.0,193969.0,193993.0] || -> . % 76.16/76.39 194013[79:Spt:194012.0,194007.0,194009.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 194014[79:Spt:194012.0,194007.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 194018[79:Res:194014.0,61.1] always3(s48) || -> . % 76.16/76.39 194019[79:SSi:194018.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 194020[77:Spt:194019.0,193968.0,193969.0] || until2p7(s47)*+ -> . % 76.16/76.39 194021[77:Spt:194019.0,193968.1] || -> node4(s46)*. % 76.16/76.39 194023[77:MRR:780.0,194021.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 194030[77:Res:53.1,194023.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 194035[78:Spt:194030.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 194037[78:Res:194035.0,61.1] always3(s46) || -> . % 76.16/76.39 194038[78:SSi:194037.0,78272.0,78276.0,192145.0,193967.0,194021.0] || -> . % 76.16/76.39 194039[78:Spt:194038.0,194030.0,194035.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 194040[78:Spt:194038.0,194030.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 194044[78:Res:194040.0,61.1] always3(s47) || -> . % 76.16/76.39 194045[78:SSi:194044.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 194046[76:Spt:194045.0,193966.0,193967.0] || until2p7(s46)*+ -> . % 76.16/76.39 194047[76:Spt:194045.0,193966.1] || -> node4(s45)*. % 76.16/76.39 194049[76:MRR:783.0,194047.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 194052[76:Res:53.1,194049.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 194054[77:Spt:194052.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 194056[77:Res:194054.0,61.1] always3(s45) || -> . % 76.16/76.39 194057[77:SSi:194056.0,78268.0,78271.0,192144.0,193965.0,194047.0] || -> . % 76.16/76.39 194058[77:Spt:194057.0,194052.0,194054.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 194059[77:Spt:194057.0,194052.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 194063[77:Res:194059.0,61.1] always3(s46) || -> . % 76.16/76.39 194064[77:SSi:194063.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 194065[75:Spt:194064.0,193964.0,193965.0] || until2p7(s45)*+ -> . % 76.16/76.39 194066[75:Spt:194064.0,193964.1] || -> node4(s44)*. % 76.16/76.39 194068[75:MRR:786.0,194066.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 194071[75:Res:53.1,194068.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 194073[76:Spt:194071.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 194075[76:Res:194073.0,61.1] always3(s44) || -> . % 76.16/76.39 194076[76:SSi:194075.0,78263.0,78267.0,192143.0,193963.0,194066.0] || -> . % 76.16/76.39 194077[76:Spt:194076.0,194071.0,194073.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 194078[76:Spt:194076.0,194071.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 194082[76:Res:194078.0,61.1] always3(s45) || -> . % 76.16/76.39 194083[76:SSi:194082.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 194084[74:Spt:194083.0,193962.0,193963.0] || until2p7(s44)*+ -> . % 76.16/76.39 194085[74:Spt:194083.0,193962.1] || -> node4(s43)*. % 76.16/76.39 194087[74:MRR:789.0,194085.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 194090[74:Res:53.1,194087.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 194092[75:Spt:194090.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 194094[75:Res:194092.0,61.1] always3(s43) || -> . % 76.16/76.39 194095[75:SSi:194094.0,78259.0,78262.0,192142.0,193961.0,194085.0] || -> . % 76.16/76.39 194096[75:Spt:194095.0,194090.0,194092.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 194097[75:Spt:194095.0,194090.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 194101[75:Res:194097.0,61.1] always3(s44) || -> . % 76.16/76.39 194102[75:SSi:194101.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 194103[73:Spt:194102.0,193960.0,193961.0] || until2p7(s43)*+ -> . % 76.16/76.39 194104[73:Spt:194102.0,193960.1] || -> node4(s42)*. % 76.16/76.39 194106[73:MRR:792.0,194104.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 194109[73:Res:53.1,194106.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 194114[74:Spt:194109.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 194116[74:Res:194114.0,61.1] always3(s42) || -> . % 76.16/76.39 194117[74:SSi:194116.0,78254.0,78258.0,192141.0,193959.0,194104.0] || -> . % 76.16/76.39 194118[74:Spt:194117.0,194109.0,194114.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 194119[74:Spt:194117.0,194109.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 194123[74:Res:194119.0,61.1] always3(s43) || -> . % 76.16/76.39 194124[74:SSi:194123.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 194125[72:Spt:194124.0,193958.0,193959.0] || until2p7(s42)*+ -> . % 76.16/76.39 194126[72:Spt:194124.0,193958.1] || -> node4(s41)*. % 76.16/76.39 194128[72:MRR:795.0,194126.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 194131[72:Res:53.1,194128.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 194133[73:Spt:194131.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 194135[73:Res:194133.0,61.1] always3(s41) || -> . % 76.16/76.39 194136[73:SSi:194135.0,78250.0,78253.0,192140.0,193957.0,194126.0] || -> . % 76.16/76.39 194137[73:Spt:194136.0,194131.0,194133.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 194138[73:Spt:194136.0,194131.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 194142[73:Res:194138.0,61.1] always3(s42) || -> . % 76.16/76.39 194143[73:SSi:194142.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 194144[71:Spt:194143.0,193956.0,193957.0] || until2p7(s41)*+ -> . % 76.16/76.39 194145[71:Spt:194143.0,193956.1] || -> node4(s40)*. % 76.16/76.39 194147[71:MRR:798.0,194145.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 194150[71:Res:53.1,194147.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 194152[72:Spt:194150.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 194154[72:Res:194152.0,61.1] always3(s40) || -> . % 76.16/76.39 194155[72:SSi:194154.0,78245.0,78249.0,192139.0,193955.0,194145.0] || -> . % 76.16/76.39 194156[72:Spt:194155.0,194150.0,194152.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 194157[72:Spt:194155.0,194150.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 194161[72:Res:194157.0,61.1] always3(s41) || -> . % 76.16/76.39 194162[72:SSi:194161.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 194163[70:Spt:194162.0,193954.0,193955.0] || until2p7(s40)*+ -> . % 76.16/76.39 194164[70:Spt:194162.0,193954.1] || -> node4(s39)*. % 76.16/76.39 194166[70:MRR:801.0,194164.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 194169[70:Res:53.1,194166.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 194171[71:Spt:194169.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 194173[71:Res:194171.0,61.1] always3(s39) || -> . % 76.16/76.39 194174[71:SSi:194173.0,78241.0,78244.0,192138.0,193953.0,194164.0] || -> . % 76.16/76.39 194175[71:Spt:194174.0,194169.0,194171.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 194176[71:Spt:194174.0,194169.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 194180[71:Res:194176.0,61.1] always3(s40) || -> . % 76.16/76.39 194181[71:SSi:194180.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 194182[69:Spt:194181.0,193952.0,193953.0] || until2p7(s39)*+ -> . % 76.16/76.39 194183[69:Spt:194181.0,193952.1] || -> node4(s38)*. % 76.16/76.39 194185[69:MRR:804.0,194183.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 194188[69:Res:53.1,194185.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 194190[69:MRR:194188.0,193942.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 194195[69:Res:194190.0,61.1] always3(s39) || -> . % 76.16/76.39 194196[69:SSi:194195.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 194197[67:Spt:194196.0,193888.0,193891.0] || trans(s49,s38)*+ -> . % 76.16/76.39 194198[67:Spt:194196.0,193888.1,193888.2,193888.3,193888.4,193888.5,193888.6,193888.7,193888.8,193888.9,193888.10,193888.11,193888.12,193888.13,193888.14,193888.15,193888.16,193888.17,193888.18,193888.19,193888.20,193888.21,193888.22,193888.23,193888.24,193888.25,193888.26,193888.27,193888.28,193888.29,193888.30,193888.31,193888.32] || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 194200[67:MRR:193890.1,194197.0] xuntil6(s49) || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 194201[68:Spt:194198.0] || -> trans(s49,s37)*. % 76.16/76.39 194202[68:Res:194201.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s37)*. % 76.16/76.39 194204[68:Res:194201.0,60.0] || -> node2(s49,s37)*. % 76.16/76.39 194205[68:SSi:194202.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s37)*. % 76.16/76.39 194206[68:Res:194204.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 194248[68:SoR:194206.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 194250[68:SoR:194248.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)* xuntil6(s49). % 76.16/76.39 194251[68:SSi:194250.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s37,c_busy)* xuntil6(s49). % 76.16/76.39 194252[69:Spt:194251.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 194254[69:Res:194252.0,61.1] always3(s37) || -> . % 76.16/76.39 194255[69:SSi:194254.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.39 194256[69:Spt:194255.0,194251.1,194252.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.16/76.39 194257[69:Spt:194255.0,194251.0,194251.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 194261[69:MRR:194248.2,194256.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 194262[69:Res:53.1,194257.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 194264[69:MRR:194262.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 194265[69:MRR:194205.0,194264.0] || -> until2p7(s37)*. % 76.16/76.39 194266[69:MRR:235.0,194265.0] || -> until2p7(s38)* node4(s37). % 76.16/76.39 194267[70:Spt:194266.0] || -> until2p7(s38)*. % 76.16/76.39 194268[70:MRR:236.0,194267.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 194269[71:Spt:194268.0] || -> until2p7(s39)*. % 76.16/76.39 194270[71:MRR:237.0,194269.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 194271[72:Spt:194270.0] || -> until2p7(s40)*. % 76.16/76.39 194272[72:MRR:238.0,194271.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 194273[73:Spt:194272.0] || -> until2p7(s41)*. % 76.16/76.39 194274[73:MRR:239.0,194273.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 194275[74:Spt:194274.0] || -> until2p7(s42)*. % 76.16/76.39 194276[74:MRR:240.0,194275.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 194277[75:Spt:194276.0] || -> until2p7(s43)*. % 76.16/76.39 194278[75:MRR:241.0,194277.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 194279[76:Spt:194278.0] || -> until2p7(s44)*. % 76.16/76.39 194280[76:MRR:539.0,194279.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 194281[77:Spt:194280.0] || -> until2p7(s45)*. % 76.16/76.39 194282[77:MRR:544.0,194281.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 194283[78:Spt:194282.0] || -> until2p7(s46)*. % 76.16/76.39 194284[78:MRR:549.0,194283.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 194285[79:Spt:194284.0] || -> until2p7(s47)*. % 76.16/76.39 194286[79:MRR:554.0,194285.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 194287[80:Spt:194286.0] || -> until2p7(s48)*. % 76.16/76.39 194288[80:MRR:559.0,194287.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 194289[81:Spt:194288.0] || -> until2p7(s49)*. % 76.16/76.39 194290[81:MRR:194.0,194289.0] || -> node4(s49)*. % 76.16/76.39 194291[81:MRR:194261.0,194290.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 194292[81:Res:53.1,194291.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 194294[81:MRR:194292.0,78381.0] || -> . % 76.16/76.39 194295[81:Spt:194294.0,194288.0,194289.0] || until2p7(s49)*+ -> . % 76.16/76.39 194296[81:Spt:194294.0,194288.1] || -> node4(s48)*. % 76.16/76.39 194297[81:MRR:78384.0,194296.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 194300[81:Res:53.1,194297.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 194303[81:Res:194300.0,61.1] always3(s48) || -> . % 76.16/76.39 194304[81:SSi:194303.0,78281.0,78387.0,192147.0,194287.0,194296.0] || -> . % 76.16/76.39 194305[80:Spt:194304.0,194286.0,194287.0] || until2p7(s48)*+ -> . % 76.16/76.39 194306[80:Spt:194304.0,194286.1] || -> node4(s47)*. % 76.16/76.39 194308[80:MRR:777.0,194306.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 194323[80:Res:53.1,194308.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 194328[81:Spt:194323.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 194330[81:Res:194328.0,61.1] always3(s47) || -> . % 76.16/76.39 194331[81:SSi:194330.0,78277.0,78280.0,192146.0,194285.0,194306.0] || -> . % 76.16/76.39 194332[81:Spt:194331.0,194323.0,194328.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 194333[81:Spt:194331.0,194323.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 194337[81:Res:194333.0,61.1] always3(s48) || -> . % 76.16/76.39 194338[81:SSi:194337.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 194339[79:Spt:194338.0,194284.0,194285.0] || until2p7(s47)*+ -> . % 76.16/76.39 194340[79:Spt:194338.0,194284.1] || -> node4(s46)*. % 76.16/76.39 194342[79:MRR:780.0,194340.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 194349[79:Res:53.1,194342.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 194351[80:Spt:194349.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 194353[80:Res:194351.0,61.1] always3(s46) || -> . % 76.16/76.39 194354[80:SSi:194353.0,78272.0,78276.0,192145.0,194283.0,194340.0] || -> . % 76.16/76.39 194355[80:Spt:194354.0,194349.0,194351.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 194356[80:Spt:194354.0,194349.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 194360[80:Res:194356.0,61.1] always3(s47) || -> . % 76.16/76.39 194361[80:SSi:194360.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 194362[78:Spt:194361.0,194282.0,194283.0] || until2p7(s46)*+ -> . % 76.16/76.39 194363[78:Spt:194361.0,194282.1] || -> node4(s45)*. % 76.16/76.39 194365[78:MRR:783.0,194363.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 194368[78:Res:53.1,194365.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 194373[79:Spt:194368.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 194375[79:Res:194373.0,61.1] always3(s45) || -> . % 76.16/76.39 194376[79:SSi:194375.0,78268.0,78271.0,192144.0,194281.0,194363.0] || -> . % 76.16/76.39 194377[79:Spt:194376.0,194368.0,194373.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 194378[79:Spt:194376.0,194368.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 194382[79:Res:194378.0,61.1] always3(s46) || -> . % 76.16/76.39 194383[79:SSi:194382.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 194384[77:Spt:194383.0,194280.0,194281.0] || until2p7(s45)*+ -> . % 76.16/76.39 194385[77:Spt:194383.0,194280.1] || -> node4(s44)*. % 76.16/76.39 194387[77:MRR:786.0,194385.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 194390[77:Res:53.1,194387.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 194392[78:Spt:194390.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 194394[78:Res:194392.0,61.1] always3(s44) || -> . % 76.16/76.39 194395[78:SSi:194394.0,78263.0,78267.0,192143.0,194279.0,194385.0] || -> . % 76.16/76.39 194396[78:Spt:194395.0,194390.0,194392.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 194397[78:Spt:194395.0,194390.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 194401[78:Res:194397.0,61.1] always3(s45) || -> . % 76.16/76.39 194402[78:SSi:194401.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 194403[76:Spt:194402.0,194278.0,194279.0] || until2p7(s44)*+ -> . % 76.16/76.39 194404[76:Spt:194402.0,194278.1] || -> node4(s43)*. % 76.16/76.39 194406[76:MRR:789.0,194404.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 194409[76:Res:53.1,194406.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 194411[77:Spt:194409.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 194413[77:Res:194411.0,61.1] always3(s43) || -> . % 76.16/76.39 194414[77:SSi:194413.0,78259.0,78262.0,192142.0,194277.0,194404.0] || -> . % 76.16/76.39 194415[77:Spt:194414.0,194409.0,194411.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 194416[77:Spt:194414.0,194409.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 194420[77:Res:194416.0,61.1] always3(s44) || -> . % 76.16/76.39 194421[77:SSi:194420.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 194422[75:Spt:194421.0,194276.0,194277.0] || until2p7(s43)*+ -> . % 76.16/76.39 194423[75:Spt:194421.0,194276.1] || -> node4(s42)*. % 76.16/76.39 194425[75:MRR:792.0,194423.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 194428[75:Res:53.1,194425.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 194430[76:Spt:194428.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 194432[76:Res:194430.0,61.1] always3(s42) || -> . % 76.16/76.39 194433[76:SSi:194432.0,78254.0,78258.0,192141.0,194275.0,194423.0] || -> . % 76.16/76.39 194434[76:Spt:194433.0,194428.0,194430.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 194435[76:Spt:194433.0,194428.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 194439[76:Res:194435.0,61.1] always3(s43) || -> . % 76.16/76.39 194440[76:SSi:194439.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 194441[74:Spt:194440.0,194274.0,194275.0] || until2p7(s42)*+ -> . % 76.16/76.39 194442[74:Spt:194440.0,194274.1] || -> node4(s41)*. % 76.16/76.39 194444[74:MRR:795.0,194442.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 194447[74:Res:53.1,194444.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 194452[75:Spt:194447.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 194454[75:Res:194452.0,61.1] always3(s41) || -> . % 76.16/76.39 194455[75:SSi:194454.0,78250.0,78253.0,192140.0,194273.0,194442.0] || -> . % 76.16/76.39 194456[75:Spt:194455.0,194447.0,194452.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 194457[75:Spt:194455.0,194447.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 194461[75:Res:194457.0,61.1] always3(s42) || -> . % 76.16/76.39 194462[75:SSi:194461.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 194463[73:Spt:194462.0,194272.0,194273.0] || until2p7(s41)*+ -> . % 76.16/76.39 194464[73:Spt:194462.0,194272.1] || -> node4(s40)*. % 76.16/76.39 194466[73:MRR:798.0,194464.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 194469[73:Res:53.1,194466.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 194471[74:Spt:194469.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 194473[74:Res:194471.0,61.1] always3(s40) || -> . % 76.16/76.39 194474[74:SSi:194473.0,78245.0,78249.0,192139.0,194271.0,194464.0] || -> . % 76.16/76.39 194475[74:Spt:194474.0,194469.0,194471.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 194476[74:Spt:194474.0,194469.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 194480[74:Res:194476.0,61.1] always3(s41) || -> . % 76.16/76.39 194481[74:SSi:194480.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 194482[72:Spt:194481.0,194270.0,194271.0] || until2p7(s40)*+ -> . % 76.16/76.39 194483[72:Spt:194481.0,194270.1] || -> node4(s39)*. % 76.16/76.39 194485[72:MRR:801.0,194483.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 194488[72:Res:53.1,194485.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 194490[73:Spt:194488.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 194492[73:Res:194490.0,61.1] always3(s39) || -> . % 76.16/76.39 194493[73:SSi:194492.0,78241.0,78244.0,192138.0,194269.0,194483.0] || -> . % 76.16/76.39 194494[73:Spt:194493.0,194488.0,194490.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 194495[73:Spt:194493.0,194488.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 194499[73:Res:194495.0,61.1] always3(s40) || -> . % 76.16/76.39 194500[73:SSi:194499.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 194501[71:Spt:194500.0,194268.0,194269.0] || until2p7(s39)*+ -> . % 76.16/76.39 194502[71:Spt:194500.0,194268.1] || -> node4(s38)*. % 76.16/76.39 194504[71:MRR:804.0,194502.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 194507[71:Res:53.1,194504.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 194509[72:Spt:194507.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 194511[72:Res:194509.0,61.1] always3(s38) || -> . % 76.16/76.39 194512[72:SSi:194511.0,78236.0,78240.0,192137.0,194267.0,194502.0] || -> . % 76.16/76.39 194513[72:Spt:194512.0,194507.0,194509.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 194514[72:Spt:194512.0,194507.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 194518[72:Res:194514.0,61.1] always3(s39) || -> . % 76.16/76.39 194519[72:SSi:194518.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 194520[70:Spt:194519.0,194266.0,194267.0] || until2p7(s38)*+ -> . % 76.16/76.39 194521[70:Spt:194519.0,194266.1] || -> node4(s37)*. % 76.16/76.39 194523[70:MRR:807.0,194521.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 194526[70:Res:53.1,194523.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 194528[70:MRR:194526.0,194256.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 194533[70:Res:194528.0,61.1] always3(s38) || -> . % 76.16/76.39 194534[70:SSi:194533.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.39 194535[68:Spt:194534.0,194198.0,194201.0] || trans(s49,s37)*+ -> . % 76.16/76.39 194536[68:Spt:194534.0,194198.1,194198.2,194198.3,194198.4,194198.5,194198.6,194198.7,194198.8,194198.9,194198.10,194198.11,194198.12,194198.13,194198.14,194198.15,194198.16,194198.17,194198.18,194198.19,194198.20,194198.21,194198.22,194198.23,194198.24,194198.25,194198.26,194198.27,194198.28,194198.29,194198.30,194198.31] || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 194538[68:MRR:194200.1,194535.0] xuntil6(s49) || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 194539[69:Spt:194536.0] || -> trans(s49,s36)*. % 76.16/76.39 194540[69:Res:194539.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s36)*. % 76.16/76.39 194542[69:Res:194539.0,60.0] || -> node2(s49,s36)*. % 76.16/76.39 194543[69:SSi:194540.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s36)*. % 76.16/76.39 194544[69:Res:194542.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 194587[69:SoR:194544.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 194589[69:SoR:194587.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)* xuntil6(s49). % 76.16/76.39 194590[69:SSi:194589.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s36,c_busy)* xuntil6(s49). % 76.16/76.39 194591[70:Spt:194590.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 194593[70:Res:194591.0,61.1] always3(s36) || -> . % 76.16/76.39 194594[70:SSi:194593.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.39 194595[70:Spt:194594.0,194590.1,194591.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.16/76.39 194596[70:Spt:194594.0,194590.0,194590.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 194600[70:MRR:194587.2,194595.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 194601[70:Res:53.1,194596.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 194603[70:MRR:194601.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 194604[70:MRR:194543.0,194603.0] || -> until2p7(s36)*. % 76.16/76.39 194605[70:MRR:232.0,194604.0] || -> until2p7(s37)* node4(s36). % 76.16/76.39 194606[71:Spt:194605.0] || -> until2p7(s37)*. % 76.16/76.39 194607[71:MRR:235.0,194606.0] || -> until2p7(s38)* node4(s37). % 76.16/76.39 194608[72:Spt:194607.0] || -> until2p7(s38)*. % 76.16/76.39 194609[72:MRR:236.0,194608.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 194610[73:Spt:194609.0] || -> until2p7(s39)*. % 76.16/76.39 194611[73:MRR:237.0,194610.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 194612[74:Spt:194611.0] || -> until2p7(s40)*. % 76.16/76.39 194613[74:MRR:238.0,194612.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 194614[75:Spt:194613.0] || -> until2p7(s41)*. % 76.16/76.39 194615[75:MRR:239.0,194614.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 194616[76:Spt:194615.0] || -> until2p7(s42)*. % 76.16/76.39 194617[76:MRR:240.0,194616.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 194618[77:Spt:194617.0] || -> until2p7(s43)*. % 76.16/76.39 194619[77:MRR:241.0,194618.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 194620[78:Spt:194619.0] || -> until2p7(s44)*. % 76.16/76.39 194621[78:MRR:539.0,194620.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 194622[79:Spt:194621.0] || -> until2p7(s45)*. % 76.16/76.39 194623[79:MRR:544.0,194622.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 194624[80:Spt:194623.0] || -> until2p7(s46)*. % 76.16/76.39 194625[80:MRR:549.0,194624.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 194626[81:Spt:194625.0] || -> until2p7(s47)*. % 76.16/76.39 194627[81:MRR:554.0,194626.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 194628[82:Spt:194627.0] || -> until2p7(s48)*. % 76.16/76.39 194629[82:MRR:559.0,194628.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 194630[83:Spt:194629.0] || -> until2p7(s49)*. % 76.16/76.39 194631[83:MRR:194.0,194630.0] || -> node4(s49)*. % 76.16/76.39 194632[83:MRR:194600.0,194631.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 194636[83:Res:53.1,194632.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 194638[83:MRR:194636.0,78381.0] || -> . % 76.16/76.39 194639[83:Spt:194638.0,194629.0,194630.0] || until2p7(s49)*+ -> . % 76.16/76.39 194640[83:Spt:194638.0,194629.1] || -> node4(s48)*. % 76.16/76.39 194641[83:MRR:78384.0,194640.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 194644[83:Res:53.1,194641.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 194647[83:Res:194644.0,61.1] always3(s48) || -> . % 76.16/76.39 194648[83:SSi:194647.0,78281.0,78387.0,192147.0,194628.0,194640.0] || -> . % 76.16/76.39 194649[82:Spt:194648.0,194627.0,194628.0] || until2p7(s48)*+ -> . % 76.16/76.39 194650[82:Spt:194648.0,194627.1] || -> node4(s47)*. % 76.16/76.39 194652[82:MRR:777.0,194650.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 194664[82:Res:53.1,194652.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 194666[83:Spt:194664.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 194668[83:Res:194666.0,61.1] always3(s47) || -> . % 76.16/76.39 194669[83:SSi:194668.0,78277.0,78280.0,192146.0,194626.0,194650.0] || -> . % 76.16/76.39 194670[83:Spt:194669.0,194664.0,194666.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 194671[83:Spt:194669.0,194664.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 194675[83:Res:194671.0,61.1] always3(s48) || -> . % 76.16/76.39 194676[83:SSi:194675.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 194677[81:Spt:194676.0,194625.0,194626.0] || until2p7(s47)*+ -> . % 76.16/76.39 194678[81:Spt:194676.0,194625.1] || -> node4(s46)*. % 76.16/76.39 194680[81:MRR:780.0,194678.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 194687[81:Res:53.1,194680.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 194692[82:Spt:194687.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 194694[82:Res:194692.0,61.1] always3(s46) || -> . % 76.16/76.39 194695[82:SSi:194694.0,78272.0,78276.0,192145.0,194624.0,194678.0] || -> . % 76.16/76.39 194696[82:Spt:194695.0,194687.0,194692.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 194697[82:Spt:194695.0,194687.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 194701[82:Res:194697.0,61.1] always3(s47) || -> . % 76.16/76.39 194702[82:SSi:194701.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 194703[80:Spt:194702.0,194623.0,194624.0] || until2p7(s46)*+ -> . % 76.16/76.39 194704[80:Spt:194702.0,194623.1] || -> node4(s45)*. % 76.16/76.39 194706[80:MRR:783.0,194704.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 194709[80:Res:53.1,194706.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 194711[81:Spt:194709.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 194713[81:Res:194711.0,61.1] always3(s45) || -> . % 76.16/76.39 194714[81:SSi:194713.0,78268.0,78271.0,192144.0,194622.0,194704.0] || -> . % 76.16/76.39 194715[81:Spt:194714.0,194709.0,194711.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 194716[81:Spt:194714.0,194709.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 194720[81:Res:194716.0,61.1] always3(s46) || -> . % 76.16/76.39 194721[81:SSi:194720.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 194722[79:Spt:194721.0,194621.0,194622.0] || until2p7(s45)*+ -> . % 76.16/76.39 194723[79:Spt:194721.0,194621.1] || -> node4(s44)*. % 76.16/76.39 194725[79:MRR:786.0,194723.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 194728[79:Res:53.1,194725.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 194730[80:Spt:194728.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 194732[80:Res:194730.0,61.1] always3(s44) || -> . % 76.16/76.39 194733[80:SSi:194732.0,78263.0,78267.0,192143.0,194620.0,194723.0] || -> . % 76.16/76.39 194734[80:Spt:194733.0,194728.0,194730.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 194735[80:Spt:194733.0,194728.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 194739[80:Res:194735.0,61.1] always3(s45) || -> . % 76.16/76.39 194740[80:SSi:194739.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 194741[78:Spt:194740.0,194619.0,194620.0] || until2p7(s44)*+ -> . % 76.16/76.39 194742[78:Spt:194740.0,194619.1] || -> node4(s43)*. % 76.16/76.39 194744[78:MRR:789.0,194742.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 194747[78:Res:53.1,194744.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 194749[79:Spt:194747.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 194751[79:Res:194749.0,61.1] always3(s43) || -> . % 76.16/76.39 194752[79:SSi:194751.0,78259.0,78262.0,192142.0,194618.0,194742.0] || -> . % 76.16/76.39 194753[79:Spt:194752.0,194747.0,194749.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 194754[79:Spt:194752.0,194747.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 194758[79:Res:194754.0,61.1] always3(s44) || -> . % 76.16/76.39 194759[79:SSi:194758.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 194760[77:Spt:194759.0,194617.0,194618.0] || until2p7(s43)*+ -> . % 76.16/76.39 194761[77:Spt:194759.0,194617.1] || -> node4(s42)*. % 76.16/76.39 194763[77:MRR:792.0,194761.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 194766[77:Res:53.1,194763.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 194771[78:Spt:194766.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 194773[78:Res:194771.0,61.1] always3(s42) || -> . % 76.16/76.39 194774[78:SSi:194773.0,78254.0,78258.0,192141.0,194616.0,194761.0] || -> . % 76.16/76.39 194775[78:Spt:194774.0,194766.0,194771.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 194776[78:Spt:194774.0,194766.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 194780[78:Res:194776.0,61.1] always3(s43) || -> . % 76.16/76.39 194781[78:SSi:194780.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 194782[76:Spt:194781.0,194615.0,194616.0] || until2p7(s42)*+ -> . % 76.16/76.39 194783[76:Spt:194781.0,194615.1] || -> node4(s41)*. % 76.16/76.39 194785[76:MRR:795.0,194783.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 194788[76:Res:53.1,194785.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 194790[77:Spt:194788.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 194792[77:Res:194790.0,61.1] always3(s41) || -> . % 76.16/76.39 194793[77:SSi:194792.0,78250.0,78253.0,192140.0,194614.0,194783.0] || -> . % 76.16/76.39 194794[77:Spt:194793.0,194788.0,194790.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 194795[77:Spt:194793.0,194788.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 194799[77:Res:194795.0,61.1] always3(s42) || -> . % 76.16/76.39 194800[77:SSi:194799.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 194801[75:Spt:194800.0,194613.0,194614.0] || until2p7(s41)*+ -> . % 76.16/76.39 194802[75:Spt:194800.0,194613.1] || -> node4(s40)*. % 76.16/76.39 194804[75:MRR:798.0,194802.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 194807[75:Res:53.1,194804.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 194809[76:Spt:194807.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 194811[76:Res:194809.0,61.1] always3(s40) || -> . % 76.16/76.39 194812[76:SSi:194811.0,78245.0,78249.0,192139.0,194612.0,194802.0] || -> . % 76.16/76.39 194813[76:Spt:194812.0,194807.0,194809.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 194814[76:Spt:194812.0,194807.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 194818[76:Res:194814.0,61.1] always3(s41) || -> . % 76.16/76.39 194819[76:SSi:194818.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 194820[74:Spt:194819.0,194611.0,194612.0] || until2p7(s40)*+ -> . % 76.16/76.39 194821[74:Spt:194819.0,194611.1] || -> node4(s39)*. % 76.16/76.39 194823[74:MRR:801.0,194821.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 194826[74:Res:53.1,194823.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 194828[75:Spt:194826.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 194830[75:Res:194828.0,61.1] always3(s39) || -> . % 76.16/76.39 194831[75:SSi:194830.0,78241.0,78244.0,192138.0,194610.0,194821.0] || -> . % 76.16/76.39 194832[75:Spt:194831.0,194826.0,194828.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 194833[75:Spt:194831.0,194826.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 194837[75:Res:194833.0,61.1] always3(s40) || -> . % 76.16/76.39 194838[75:SSi:194837.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 194839[73:Spt:194838.0,194609.0,194610.0] || until2p7(s39)*+ -> . % 76.16/76.39 194840[73:Spt:194838.0,194609.1] || -> node4(s38)*. % 76.16/76.39 194842[73:MRR:804.0,194840.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 194845[73:Res:53.1,194842.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 194850[74:Spt:194845.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 194852[74:Res:194850.0,61.1] always3(s38) || -> . % 76.16/76.39 194853[74:SSi:194852.0,78236.0,78240.0,192137.0,194608.0,194840.0] || -> . % 76.16/76.39 194854[74:Spt:194853.0,194845.0,194850.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 194855[74:Spt:194853.0,194845.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 194859[74:Res:194855.0,61.1] always3(s39) || -> . % 76.16/76.39 194860[74:SSi:194859.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 194861[72:Spt:194860.0,194607.0,194608.0] || until2p7(s38)*+ -> . % 76.16/76.39 194862[72:Spt:194860.0,194607.1] || -> node4(s37)*. % 76.16/76.39 194864[72:MRR:807.0,194862.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 194867[72:Res:53.1,194864.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 194869[73:Spt:194867.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 194871[73:Res:194869.0,61.1] always3(s37) || -> . % 76.16/76.39 194872[73:SSi:194871.0,78232.0,78235.0,192136.0,194606.0,194862.0] || -> . % 76.16/76.39 194873[73:Spt:194872.0,194867.0,194869.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.39 194874[73:Spt:194872.0,194867.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 194878[73:Res:194874.0,61.1] always3(s38) || -> . % 76.16/76.39 194879[73:SSi:194878.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.39 194880[71:Spt:194879.0,194605.0,194606.0] || until2p7(s37)*+ -> . % 76.16/76.39 194881[71:Spt:194879.0,194605.1] || -> node4(s36)*. % 76.16/76.39 194883[71:MRR:810.0,194881.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.39 194886[71:Res:53.1,194883.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.39 194888[71:MRR:194886.0,194595.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 194890[71:Res:194888.0,61.1] always3(s37) || -> . % 76.16/76.39 194891[71:SSi:194890.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.39 194892[69:Spt:194891.0,194536.0,194539.0] || trans(s49,s36)*+ -> . % 76.16/76.39 194893[69:Spt:194891.0,194536.1,194536.2,194536.3,194536.4,194536.5,194536.6,194536.7,194536.8,194536.9,194536.10,194536.11,194536.12,194536.13,194536.14,194536.15,194536.16,194536.17,194536.18,194536.19,194536.20,194536.21,194536.22,194536.23,194536.24,194536.25,194536.26,194536.27,194536.28,194536.29,194536.30] || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 194895[69:MRR:194538.1,194892.0] xuntil6(s49) || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 194896[70:Spt:194893.0] || -> trans(s49,s35)*. % 76.16/76.39 194897[70:Res:194896.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s35)*. % 76.16/76.39 194899[70:Res:194896.0,60.0] || -> node2(s49,s35)*. % 76.16/76.39 194900[70:SSi:194897.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s35)*. % 76.16/76.39 194901[70:Res:194899.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 194951[70:SoR:194901.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 194953[70:SoR:194951.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 76.16/76.39 194954[70:SSi:194953.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 76.16/76.39 194955[71:Spt:194954.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 194957[71:Res:194955.0,61.1] always3(s35) || -> . % 76.16/76.39 194958[71:SSi:194957.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.39 194959[71:Spt:194958.0,194954.1,194955.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.16/76.39 194960[71:Spt:194958.0,194954.0,194954.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 194964[71:MRR:194951.2,194959.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 194965[71:Res:53.1,194960.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 194967[71:MRR:194965.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 194968[71:MRR:194900.0,194967.0] || -> until2p7(s35)*. % 76.16/76.39 194969[71:MRR:231.0,194968.0] || -> until2p7(s36)* node4(s35). % 76.16/76.39 194970[72:Spt:194969.0] || -> until2p7(s36)*. % 76.16/76.39 194971[72:MRR:232.0,194970.0] || -> until2p7(s37)* node4(s36). % 76.16/76.39 194972[73:Spt:194971.0] || -> until2p7(s37)*. % 76.16/76.39 194973[73:MRR:235.0,194972.0] || -> until2p7(s38)* node4(s37). % 76.16/76.39 194974[74:Spt:194973.0] || -> until2p7(s38)*. % 76.16/76.39 194975[74:MRR:236.0,194974.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 194976[75:Spt:194975.0] || -> until2p7(s39)*. % 76.16/76.39 194977[75:MRR:237.0,194976.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 194978[76:Spt:194977.0] || -> until2p7(s40)*. % 76.16/76.39 194979[76:MRR:238.0,194978.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 194980[77:Spt:194979.0] || -> until2p7(s41)*. % 76.16/76.39 194981[77:MRR:239.0,194980.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 194982[78:Spt:194981.0] || -> until2p7(s42)*. % 76.16/76.39 194983[78:MRR:240.0,194982.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 194984[79:Spt:194983.0] || -> until2p7(s43)*. % 76.16/76.39 194985[79:MRR:241.0,194984.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 194986[80:Spt:194985.0] || -> until2p7(s44)*. % 76.16/76.39 194987[80:MRR:539.0,194986.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 194988[81:Spt:194987.0] || -> until2p7(s45)*. % 76.16/76.39 194989[81:MRR:544.0,194988.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 194990[82:Spt:194989.0] || -> until2p7(s46)*. % 76.16/76.39 194991[82:MRR:549.0,194990.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 194992[83:Spt:194991.0] || -> until2p7(s47)*. % 76.16/76.39 194993[83:MRR:554.0,194992.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 194994[84:Spt:194993.0] || -> until2p7(s48)*. % 76.16/76.39 194995[84:MRR:559.0,194994.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 194996[85:Spt:194995.0] || -> until2p7(s49)*. % 76.16/76.39 194997[85:MRR:194.0,194996.0] || -> node4(s49)*. % 76.16/76.39 194998[85:MRR:194964.0,194997.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 194999[85:Res:53.1,194998.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 195001[85:MRR:194999.0,78381.0] || -> . % 76.16/76.39 195002[85:Spt:195001.0,194995.0,194996.0] || until2p7(s49)*+ -> . % 76.16/76.39 195003[85:Spt:195001.0,194995.1] || -> node4(s48)*. % 76.16/76.39 195004[85:MRR:78384.0,195003.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 195007[85:Res:53.1,195004.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 195010[85:Res:195007.0,61.1] always3(s48) || -> . % 76.16/76.39 195011[85:SSi:195010.0,78281.0,78387.0,192147.0,194994.0,195003.0] || -> . % 76.16/76.39 195012[84:Spt:195011.0,194993.0,194994.0] || until2p7(s48)*+ -> . % 76.16/76.39 195013[84:Spt:195011.0,194993.1] || -> node4(s47)*. % 76.16/76.39 195015[84:MRR:777.0,195013.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 195030[84:Res:53.1,195015.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 195032[85:Spt:195030.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 195034[85:Res:195032.0,61.1] always3(s47) || -> . % 76.16/76.39 195035[85:SSi:195034.0,78277.0,78280.0,192146.0,194992.0,195013.0] || -> . % 76.16/76.39 195036[85:Spt:195035.0,195030.0,195032.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 195037[85:Spt:195035.0,195030.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 195041[85:Res:195037.0,61.1] always3(s48) || -> . % 76.16/76.39 195042[85:SSi:195041.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 195043[83:Spt:195042.0,194991.0,194992.0] || until2p7(s47)*+ -> . % 76.16/76.39 195044[83:Spt:195042.0,194991.1] || -> node4(s46)*. % 76.16/76.39 195046[83:MRR:780.0,195044.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 195056[83:Res:53.1,195046.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 195058[84:Spt:195056.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 195060[84:Res:195058.0,61.1] always3(s46) || -> . % 76.16/76.39 195061[84:SSi:195060.0,78272.0,78276.0,192145.0,194990.0,195044.0] || -> . % 76.16/76.39 195062[84:Spt:195061.0,195056.0,195058.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 195063[84:Spt:195061.0,195056.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 195067[84:Res:195063.0,61.1] always3(s47) || -> . % 76.16/76.39 195068[84:SSi:195067.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 195069[82:Spt:195068.0,194989.0,194990.0] || until2p7(s46)*+ -> . % 76.16/76.39 195070[82:Spt:195068.0,194989.1] || -> node4(s45)*. % 76.16/76.39 195072[82:MRR:783.0,195070.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 195075[82:Res:53.1,195072.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 195077[83:Spt:195075.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 195079[83:Res:195077.0,61.1] always3(s45) || -> . % 76.16/76.39 195080[83:SSi:195079.0,78268.0,78271.0,192144.0,194988.0,195070.0] || -> . % 76.16/76.39 195081[83:Spt:195080.0,195075.0,195077.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 195082[83:Spt:195080.0,195075.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 195086[83:Res:195082.0,61.1] always3(s46) || -> . % 76.16/76.39 195087[83:SSi:195086.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 195088[81:Spt:195087.0,194987.0,194988.0] || until2p7(s45)*+ -> . % 76.16/76.39 195089[81:Spt:195087.0,194987.1] || -> node4(s44)*. % 76.16/76.39 195091[81:MRR:786.0,195089.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 195094[81:Res:53.1,195091.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 195096[82:Spt:195094.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 195098[82:Res:195096.0,61.1] always3(s44) || -> . % 76.16/76.39 195099[82:SSi:195098.0,78263.0,78267.0,192143.0,194986.0,195089.0] || -> . % 76.16/76.39 195100[82:Spt:195099.0,195094.0,195096.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 195101[82:Spt:195099.0,195094.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 195105[82:Res:195101.0,61.1] always3(s45) || -> . % 76.16/76.39 195106[82:SSi:195105.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 195107[80:Spt:195106.0,194985.0,194986.0] || until2p7(s44)*+ -> . % 76.16/76.39 195108[80:Spt:195106.0,194985.1] || -> node4(s43)*. % 76.16/76.39 195110[80:MRR:789.0,195108.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 195113[80:Res:53.1,195110.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 195118[81:Spt:195113.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 195120[81:Res:195118.0,61.1] always3(s43) || -> . % 76.16/76.39 195121[81:SSi:195120.0,78259.0,78262.0,192142.0,194984.0,195108.0] || -> . % 76.16/76.39 195122[81:Spt:195121.0,195113.0,195118.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 195123[81:Spt:195121.0,195113.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 195127[81:Res:195123.0,61.1] always3(s44) || -> . % 76.16/76.39 195128[81:SSi:195127.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 195129[79:Spt:195128.0,194983.0,194984.0] || until2p7(s43)*+ -> . % 76.16/76.39 195130[79:Spt:195128.0,194983.1] || -> node4(s42)*. % 76.16/76.39 195132[79:MRR:792.0,195130.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 195135[79:Res:53.1,195132.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 195137[80:Spt:195135.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 195139[80:Res:195137.0,61.1] always3(s42) || -> . % 76.16/76.39 195140[80:SSi:195139.0,78254.0,78258.0,192141.0,194982.0,195130.0] || -> . % 76.16/76.39 195141[80:Spt:195140.0,195135.0,195137.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 195142[80:Spt:195140.0,195135.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 195146[80:Res:195142.0,61.1] always3(s43) || -> . % 76.16/76.39 195147[80:SSi:195146.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 195148[78:Spt:195147.0,194981.0,194982.0] || until2p7(s42)*+ -> . % 76.16/76.39 195149[78:Spt:195147.0,194981.1] || -> node4(s41)*. % 76.16/76.39 195151[78:MRR:795.0,195149.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 195154[78:Res:53.1,195151.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 195156[79:Spt:195154.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 195158[79:Res:195156.0,61.1] always3(s41) || -> . % 76.16/76.39 195159[79:SSi:195158.0,78250.0,78253.0,192140.0,194980.0,195149.0] || -> . % 76.16/76.39 195160[79:Spt:195159.0,195154.0,195156.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 195161[79:Spt:195159.0,195154.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 195165[79:Res:195161.0,61.1] always3(s42) || -> . % 76.16/76.39 195166[79:SSi:195165.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 195167[77:Spt:195166.0,194979.0,194980.0] || until2p7(s41)*+ -> . % 76.16/76.39 195168[77:Spt:195166.0,194979.1] || -> node4(s40)*. % 76.16/76.39 195170[77:MRR:798.0,195168.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 195173[77:Res:53.1,195170.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 195175[78:Spt:195173.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 195177[78:Res:195175.0,61.1] always3(s40) || -> . % 76.16/76.39 195178[78:SSi:195177.0,78245.0,78249.0,192139.0,194978.0,195168.0] || -> . % 76.16/76.39 195179[78:Spt:195178.0,195173.0,195175.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 195180[78:Spt:195178.0,195173.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 195184[78:Res:195180.0,61.1] always3(s41) || -> . % 76.16/76.39 195185[78:SSi:195184.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 195186[76:Spt:195185.0,194977.0,194978.0] || until2p7(s40)*+ -> . % 76.16/76.39 195187[76:Spt:195185.0,194977.1] || -> node4(s39)*. % 76.16/76.39 195189[76:MRR:801.0,195187.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 195192[76:Res:53.1,195189.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 195197[77:Spt:195192.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 195199[77:Res:195197.0,61.1] always3(s39) || -> . % 76.16/76.39 195200[77:SSi:195199.0,78241.0,78244.0,192138.0,194976.0,195187.0] || -> . % 76.16/76.39 195201[77:Spt:195200.0,195192.0,195197.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 195202[77:Spt:195200.0,195192.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 195206[77:Res:195202.0,61.1] always3(s40) || -> . % 76.16/76.39 195207[77:SSi:195206.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 195208[75:Spt:195207.0,194975.0,194976.0] || until2p7(s39)*+ -> . % 76.16/76.39 195209[75:Spt:195207.0,194975.1] || -> node4(s38)*. % 76.16/76.39 195211[75:MRR:804.0,195209.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 195214[75:Res:53.1,195211.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 195216[76:Spt:195214.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 195218[76:Res:195216.0,61.1] always3(s38) || -> . % 76.16/76.39 195219[76:SSi:195218.0,78236.0,78240.0,192137.0,194974.0,195209.0] || -> . % 76.16/76.39 195220[76:Spt:195219.0,195214.0,195216.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 195221[76:Spt:195219.0,195214.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 195225[76:Res:195221.0,61.1] always3(s39) || -> . % 76.16/76.39 195226[76:SSi:195225.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 195227[74:Spt:195226.0,194973.0,194974.0] || until2p7(s38)*+ -> . % 76.16/76.39 195228[74:Spt:195226.0,194973.1] || -> node4(s37)*. % 76.16/76.39 195230[74:MRR:807.0,195228.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 195233[74:Res:53.1,195230.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 195235[75:Spt:195233.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 195237[75:Res:195235.0,61.1] always3(s37) || -> . % 76.16/76.39 195238[75:SSi:195237.0,78232.0,78235.0,192136.0,194972.0,195228.0] || -> . % 76.16/76.39 195239[75:Spt:195238.0,195233.0,195235.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.39 195240[75:Spt:195238.0,195233.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 195244[75:Res:195240.0,61.1] always3(s38) || -> . % 76.16/76.39 195245[75:SSi:195244.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.39 195246[73:Spt:195245.0,194971.0,194972.0] || until2p7(s37)*+ -> . % 76.16/76.39 195247[73:Spt:195245.0,194971.1] || -> node4(s36)*. % 76.16/76.39 195249[73:MRR:810.0,195247.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.39 195252[73:Res:53.1,195249.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.39 195254[74:Spt:195252.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 195256[74:Res:195254.0,61.1] always3(s36) || -> . % 76.16/76.39 195257[74:SSi:195256.0,78227.0,78231.0,192135.0,194970.0,195247.0] || -> . % 76.16/76.39 195258[74:Spt:195257.0,195252.0,195254.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.39 195259[74:Spt:195257.0,195252.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 195263[74:Res:195259.0,61.1] always3(s37) || -> . % 76.16/76.39 195264[74:SSi:195263.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.39 195265[72:Spt:195264.0,194969.0,194970.0] || until2p7(s36)*+ -> . % 76.16/76.39 195266[72:Spt:195264.0,194969.1] || -> node4(s35)*. % 76.16/76.39 195268[72:MRR:813.0,195266.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.39 195271[72:Res:53.1,195268.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.39 195273[72:MRR:195271.0,194959.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 195278[72:Res:195273.0,61.1] always3(s36) || -> . % 76.16/76.39 195279[72:SSi:195278.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.39 195280[70:Spt:195279.0,194893.0,194896.0] || trans(s49,s35)*+ -> . % 76.16/76.39 195281[70:Spt:195279.0,194893.1,194893.2,194893.3,194893.4,194893.5,194893.6,194893.7,194893.8,194893.9,194893.10,194893.11,194893.12,194893.13,194893.14,194893.15,194893.16,194893.17,194893.18,194893.19,194893.20,194893.21,194893.22,194893.23,194893.24,194893.25,194893.26,194893.27,194893.28,194893.29] || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 195283[70:MRR:194895.1,195280.0] xuntil6(s49) || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 195284[71:Spt:195281.0] || -> trans(s49,s34)*. % 76.16/76.39 195285[71:Res:195284.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s34)*. % 76.16/76.39 195287[71:Res:195284.0,60.0] || -> node2(s49,s34)*. % 76.16/76.39 195288[71:SSi:195285.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s34)*. % 76.16/76.39 195289[71:Res:195287.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 195340[71:SoR:195289.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 195342[71:SoR:195340.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)* xuntil6(s49). % 76.16/76.39 195343[71:SSi:195342.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s34,c_busy)* xuntil6(s49). % 76.16/76.39 195344[72:Spt:195343.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 195346[72:Res:195344.0,61.1] always3(s34) || -> . % 76.16/76.39 195347[72:SSi:195346.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.39 195348[72:Spt:195347.0,195343.1,195344.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.16/76.39 195349[72:Spt:195347.0,195343.0,195343.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 195353[72:MRR:195340.2,195348.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 195354[72:Res:53.1,195349.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 195356[72:MRR:195354.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 195357[72:MRR:195288.0,195356.0] || -> until2p7(s34)*. % 76.16/76.39 195358[72:MRR:230.0,195357.0] || -> until2p7(s35)* node4(s34). % 76.16/76.39 195359[73:Spt:195358.0] || -> until2p7(s35)*. % 76.16/76.39 195360[73:MRR:231.0,195359.0] || -> until2p7(s36)* node4(s35). % 76.16/76.39 195361[74:Spt:195360.0] || -> until2p7(s36)*. % 76.16/76.39 195362[74:MRR:232.0,195361.0] || -> until2p7(s37)* node4(s36). % 76.16/76.39 195363[75:Spt:195362.0] || -> until2p7(s37)*. % 76.16/76.39 195364[75:MRR:235.0,195363.0] || -> until2p7(s38)* node4(s37). % 76.16/76.39 195365[76:Spt:195364.0] || -> until2p7(s38)*. % 76.16/76.39 195366[76:MRR:236.0,195365.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 195367[77:Spt:195366.0] || -> until2p7(s39)*. % 76.16/76.39 195368[77:MRR:237.0,195367.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 195369[78:Spt:195368.0] || -> until2p7(s40)*. % 76.16/76.39 195370[78:MRR:238.0,195369.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 195371[79:Spt:195370.0] || -> until2p7(s41)*. % 76.16/76.39 195372[79:MRR:239.0,195371.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 195373[80:Spt:195372.0] || -> until2p7(s42)*. % 76.16/76.39 195374[80:MRR:240.0,195373.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 195375[81:Spt:195374.0] || -> until2p7(s43)*. % 76.16/76.39 195376[81:MRR:241.0,195375.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 195377[82:Spt:195376.0] || -> until2p7(s44)*. % 76.16/76.39 195378[82:MRR:539.0,195377.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 195379[83:Spt:195378.0] || -> until2p7(s45)*. % 76.16/76.39 195380[83:MRR:544.0,195379.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 195381[84:Spt:195380.0] || -> until2p7(s46)*. % 76.16/76.39 195382[84:MRR:549.0,195381.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 195383[85:Spt:195382.0] || -> until2p7(s47)*. % 76.16/76.39 195384[85:MRR:554.0,195383.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 195385[86:Spt:195384.0] || -> until2p7(s48)*. % 76.16/76.39 195386[86:MRR:559.0,195385.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 195387[87:Spt:195386.0] || -> until2p7(s49)*. % 76.16/76.39 195388[87:MRR:194.0,195387.0] || -> node4(s49)*. % 76.16/76.39 195389[87:MRR:195353.0,195388.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 195390[87:Res:53.1,195389.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 195392[87:MRR:195390.0,78381.0] || -> . % 76.16/76.39 195393[87:Spt:195392.0,195386.0,195387.0] || until2p7(s49)*+ -> . % 76.16/76.39 195394[87:Spt:195392.0,195386.1] || -> node4(s48)*. % 76.16/76.39 195395[87:MRR:78384.0,195394.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 195398[87:Res:53.1,195395.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 195401[87:Res:195398.0,61.1] always3(s48) || -> . % 76.16/76.39 195402[87:SSi:195401.0,78281.0,78387.0,192147.0,195385.0,195394.0] || -> . % 76.16/76.39 195403[86:Spt:195402.0,195384.0,195385.0] || until2p7(s48)*+ -> . % 76.16/76.39 195404[86:Spt:195402.0,195384.1] || -> node4(s47)*. % 76.16/76.39 195406[86:MRR:777.0,195404.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 195421[86:Res:53.1,195406.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 195423[87:Spt:195421.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 195425[87:Res:195423.0,61.1] always3(s47) || -> . % 76.16/76.39 195426[87:SSi:195425.0,78277.0,78280.0,192146.0,195383.0,195404.0] || -> . % 76.16/76.39 195427[87:Spt:195426.0,195421.0,195423.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 195428[87:Spt:195426.0,195421.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 195432[87:Res:195428.0,61.1] always3(s48) || -> . % 76.16/76.39 195433[87:SSi:195432.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 195434[85:Spt:195433.0,195382.0,195383.0] || until2p7(s47)*+ -> . % 76.16/76.39 195435[85:Spt:195433.0,195382.1] || -> node4(s46)*. % 76.16/76.39 195437[85:MRR:780.0,195435.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 195447[85:Res:53.1,195437.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 195449[86:Spt:195447.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 195451[86:Res:195449.0,61.1] always3(s46) || -> . % 76.16/76.39 195452[86:SSi:195451.0,78272.0,78276.0,192145.0,195381.0,195435.0] || -> . % 76.16/76.39 195453[86:Spt:195452.0,195447.0,195449.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 195454[86:Spt:195452.0,195447.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 195458[86:Res:195454.0,61.1] always3(s47) || -> . % 76.16/76.39 195459[86:SSi:195458.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 195460[84:Spt:195459.0,195380.0,195381.0] || until2p7(s46)*+ -> . % 76.16/76.39 195461[84:Spt:195459.0,195380.1] || -> node4(s45)*. % 76.16/76.39 195463[84:MRR:783.0,195461.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 195466[84:Res:53.1,195463.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 195468[85:Spt:195466.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 195470[85:Res:195468.0,61.1] always3(s45) || -> . % 76.16/76.39 195471[85:SSi:195470.0,78268.0,78271.0,192144.0,195379.0,195461.0] || -> . % 76.16/76.39 195472[85:Spt:195471.0,195466.0,195468.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 195473[85:Spt:195471.0,195466.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 195477[85:Res:195473.0,61.1] always3(s46) || -> . % 76.16/76.39 195478[85:SSi:195477.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 195479[83:Spt:195478.0,195378.0,195379.0] || until2p7(s45)*+ -> . % 76.16/76.39 195480[83:Spt:195478.0,195378.1] || -> node4(s44)*. % 76.16/76.39 195482[83:MRR:786.0,195480.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 195485[83:Res:53.1,195482.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 195487[84:Spt:195485.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 195489[84:Res:195487.0,61.1] always3(s44) || -> . % 76.16/76.39 195490[84:SSi:195489.0,78263.0,78267.0,192143.0,195377.0,195480.0] || -> . % 76.16/76.39 195491[84:Spt:195490.0,195485.0,195487.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 195492[84:Spt:195490.0,195485.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 195496[84:Res:195492.0,61.1] always3(s45) || -> . % 76.16/76.39 195497[84:SSi:195496.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 195498[82:Spt:195497.0,195376.0,195377.0] || until2p7(s44)*+ -> . % 76.16/76.39 195499[82:Spt:195497.0,195376.1] || -> node4(s43)*. % 76.16/76.39 195501[82:MRR:789.0,195499.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 195504[82:Res:53.1,195501.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 195509[83:Spt:195504.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 195511[83:Res:195509.0,61.1] always3(s43) || -> . % 76.16/76.39 195512[83:SSi:195511.0,78259.0,78262.0,192142.0,195375.0,195499.0] || -> . % 76.16/76.39 195513[83:Spt:195512.0,195504.0,195509.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 195514[83:Spt:195512.0,195504.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 195518[83:Res:195514.0,61.1] always3(s44) || -> . % 76.16/76.39 195519[83:SSi:195518.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 195520[81:Spt:195519.0,195374.0,195375.0] || until2p7(s43)*+ -> . % 76.16/76.39 195521[81:Spt:195519.0,195374.1] || -> node4(s42)*. % 76.16/76.39 195523[81:MRR:792.0,195521.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 195526[81:Res:53.1,195523.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 195528[82:Spt:195526.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 195530[82:Res:195528.0,61.1] always3(s42) || -> . % 76.16/76.39 195531[82:SSi:195530.0,78254.0,78258.0,192141.0,195373.0,195521.0] || -> . % 76.16/76.39 195532[82:Spt:195531.0,195526.0,195528.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 195533[82:Spt:195531.0,195526.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 195537[82:Res:195533.0,61.1] always3(s43) || -> . % 76.16/76.39 195538[82:SSi:195537.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 195539[80:Spt:195538.0,195372.0,195373.0] || until2p7(s42)*+ -> . % 76.16/76.39 195540[80:Spt:195538.0,195372.1] || -> node4(s41)*. % 76.16/76.39 195542[80:MRR:795.0,195540.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 195545[80:Res:53.1,195542.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 195547[81:Spt:195545.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 195549[81:Res:195547.0,61.1] always3(s41) || -> . % 76.16/76.39 195550[81:SSi:195549.0,78250.0,78253.0,192140.0,195371.0,195540.0] || -> . % 76.16/76.39 195551[81:Spt:195550.0,195545.0,195547.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 195552[81:Spt:195550.0,195545.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 195556[81:Res:195552.0,61.1] always3(s42) || -> . % 76.16/76.39 195557[81:SSi:195556.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 195558[79:Spt:195557.0,195370.0,195371.0] || until2p7(s41)*+ -> . % 76.16/76.39 195559[79:Spt:195557.0,195370.1] || -> node4(s40)*. % 76.16/76.39 195561[79:MRR:798.0,195559.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 195564[79:Res:53.1,195561.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 195566[80:Spt:195564.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 195568[80:Res:195566.0,61.1] always3(s40) || -> . % 76.16/76.39 195569[80:SSi:195568.0,78245.0,78249.0,192139.0,195369.0,195559.0] || -> . % 76.16/76.39 195570[80:Spt:195569.0,195564.0,195566.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 195571[80:Spt:195569.0,195564.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 195575[80:Res:195571.0,61.1] always3(s41) || -> . % 76.16/76.39 195576[80:SSi:195575.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 195577[78:Spt:195576.0,195368.0,195369.0] || until2p7(s40)*+ -> . % 76.16/76.39 195578[78:Spt:195576.0,195368.1] || -> node4(s39)*. % 76.16/76.39 195580[78:MRR:801.0,195578.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 195583[78:Res:53.1,195580.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 195588[79:Spt:195583.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 195590[79:Res:195588.0,61.1] always3(s39) || -> . % 76.16/76.39 195591[79:SSi:195590.0,78241.0,78244.0,192138.0,195367.0,195578.0] || -> . % 76.16/76.39 195592[79:Spt:195591.0,195583.0,195588.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 195593[79:Spt:195591.0,195583.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 195597[79:Res:195593.0,61.1] always3(s40) || -> . % 76.16/76.39 195598[79:SSi:195597.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 195599[77:Spt:195598.0,195366.0,195367.0] || until2p7(s39)*+ -> . % 76.16/76.39 195600[77:Spt:195598.0,195366.1] || -> node4(s38)*. % 76.16/76.39 195602[77:MRR:804.0,195600.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 195605[77:Res:53.1,195602.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 195607[78:Spt:195605.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 195609[78:Res:195607.0,61.1] always3(s38) || -> . % 76.16/76.39 195610[78:SSi:195609.0,78236.0,78240.0,192137.0,195365.0,195600.0] || -> . % 76.16/76.39 195611[78:Spt:195610.0,195605.0,195607.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 195612[78:Spt:195610.0,195605.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 195616[78:Res:195612.0,61.1] always3(s39) || -> . % 76.16/76.39 195617[78:SSi:195616.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 195618[76:Spt:195617.0,195364.0,195365.0] || until2p7(s38)*+ -> . % 76.16/76.39 195619[76:Spt:195617.0,195364.1] || -> node4(s37)*. % 76.16/76.39 195621[76:MRR:807.0,195619.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 195624[76:Res:53.1,195621.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 195626[77:Spt:195624.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 195628[77:Res:195626.0,61.1] always3(s37) || -> . % 76.16/76.39 195629[77:SSi:195628.0,78232.0,78235.0,192136.0,195363.0,195619.0] || -> . % 76.16/76.39 195630[77:Spt:195629.0,195624.0,195626.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.39 195631[77:Spt:195629.0,195624.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 195635[77:Res:195631.0,61.1] always3(s38) || -> . % 76.16/76.39 195636[77:SSi:195635.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.39 195637[75:Spt:195636.0,195362.0,195363.0] || until2p7(s37)*+ -> . % 76.16/76.39 195638[75:Spt:195636.0,195362.1] || -> node4(s36)*. % 76.16/76.39 195640[75:MRR:810.0,195638.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.39 195643[75:Res:53.1,195640.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.39 195645[76:Spt:195643.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 195647[76:Res:195645.0,61.1] always3(s36) || -> . % 76.16/76.39 195648[76:SSi:195647.0,78227.0,78231.0,192135.0,195361.0,195638.0] || -> . % 76.16/76.39 195649[76:Spt:195648.0,195643.0,195645.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.39 195650[76:Spt:195648.0,195643.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 195654[76:Res:195650.0,61.1] always3(s37) || -> . % 76.16/76.39 195655[76:SSi:195654.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.39 195656[74:Spt:195655.0,195360.0,195361.0] || until2p7(s36)*+ -> . % 76.16/76.39 195657[74:Spt:195655.0,195360.1] || -> node4(s35)*. % 76.16/76.39 195659[74:MRR:813.0,195657.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.39 195662[74:Res:53.1,195659.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.39 195667[75:Spt:195662.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 195669[75:Res:195667.0,61.1] always3(s35) || -> . % 76.16/76.39 195670[75:SSi:195669.0,78223.0,78226.0,192134.0,195359.0,195657.0] || -> . % 76.16/76.39 195671[75:Spt:195670.0,195662.0,195667.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.39 195672[75:Spt:195670.0,195662.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 195676[75:Res:195672.0,61.1] always3(s36) || -> . % 76.16/76.39 195677[75:SSi:195676.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.39 195678[73:Spt:195677.0,195358.0,195359.0] || until2p7(s35)*+ -> . % 76.16/76.39 195679[73:Spt:195677.0,195358.1] || -> node4(s34)*. % 76.16/76.39 195681[73:MRR:816.0,195679.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.39 195684[73:Res:53.1,195681.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.39 195686[73:MRR:195684.0,195348.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 195688[73:Res:195686.0,61.1] always3(s35) || -> . % 76.16/76.39 195689[73:SSi:195688.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.39 195690[71:Spt:195689.0,195281.0,195284.0] || trans(s49,s34)*+ -> . % 76.16/76.39 195691[71:Spt:195689.0,195281.1,195281.2,195281.3,195281.4,195281.5,195281.6,195281.7,195281.8,195281.9,195281.10,195281.11,195281.12,195281.13,195281.14,195281.15,195281.16,195281.17,195281.18,195281.19,195281.20,195281.21,195281.22,195281.23,195281.24,195281.25,195281.26,195281.27,195281.28] || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 195693[71:MRR:195283.1,195690.0] xuntil6(s49) || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 195694[72:Spt:195691.0] || -> trans(s49,s33)*. % 76.16/76.39 195695[72:Res:195694.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s33)*. % 76.16/76.39 195697[72:Res:195694.0,60.0] || -> node2(s49,s33)*. % 76.16/76.39 195698[72:SSi:195695.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s33)*. % 76.16/76.39 195699[72:Res:195697.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 195754[72:SoR:195699.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 195756[72:SoR:195754.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.16/76.39 195757[72:SSi:195756.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.16/76.39 195758[73:Spt:195757.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 195760[73:Res:195758.0,61.1] always3(s33) || -> . % 76.16/76.39 195761[73:SSi:195760.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.39 195762[73:Spt:195761.0,195757.1,195758.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.16/76.39 195763[73:Spt:195761.0,195757.0,195757.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 195767[73:MRR:195754.2,195762.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 195768[73:Res:53.1,195763.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 195770[73:MRR:195768.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 195771[73:MRR:195698.0,195770.0] || -> until2p7(s33)*. % 76.16/76.39 195772[73:MRR:229.0,195771.0] || -> until2p7(s34)* node4(s33). % 76.16/76.39 195773[74:Spt:195772.0] || -> until2p7(s34)*. % 76.16/76.39 195774[74:MRR:230.0,195773.0] || -> until2p7(s35)* node4(s34). % 76.16/76.39 195775[75:Spt:195774.0] || -> until2p7(s35)*. % 76.16/76.39 195776[75:MRR:231.0,195775.0] || -> until2p7(s36)* node4(s35). % 76.16/76.39 195777[76:Spt:195776.0] || -> until2p7(s36)*. % 76.16/76.39 195778[76:MRR:232.0,195777.0] || -> until2p7(s37)* node4(s36). % 76.16/76.39 195779[77:Spt:195778.0] || -> until2p7(s37)*. % 76.16/76.39 195780[77:MRR:235.0,195779.0] || -> until2p7(s38)* node4(s37). % 76.16/76.39 195781[78:Spt:195780.0] || -> until2p7(s38)*. % 76.16/76.39 195782[78:MRR:236.0,195781.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 195783[79:Spt:195782.0] || -> until2p7(s39)*. % 76.16/76.39 195784[79:MRR:237.0,195783.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 195785[80:Spt:195784.0] || -> until2p7(s40)*. % 76.16/76.39 195786[80:MRR:238.0,195785.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 195787[81:Spt:195786.0] || -> until2p7(s41)*. % 76.16/76.39 195788[81:MRR:239.0,195787.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 195789[82:Spt:195788.0] || -> until2p7(s42)*. % 76.16/76.39 195790[82:MRR:240.0,195789.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 195791[83:Spt:195790.0] || -> until2p7(s43)*. % 76.16/76.39 195792[83:MRR:241.0,195791.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 195793[84:Spt:195792.0] || -> until2p7(s44)*. % 76.16/76.39 195794[84:MRR:539.0,195793.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 195795[85:Spt:195794.0] || -> until2p7(s45)*. % 76.16/76.39 195796[85:MRR:544.0,195795.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 195797[86:Spt:195796.0] || -> until2p7(s46)*. % 76.16/76.39 195798[86:MRR:549.0,195797.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 195799[87:Spt:195798.0] || -> until2p7(s47)*. % 76.16/76.39 195800[87:MRR:554.0,195799.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 195801[88:Spt:195800.0] || -> until2p7(s48)*. % 76.16/76.39 195802[88:MRR:559.0,195801.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 195803[89:Spt:195802.0] || -> until2p7(s49)*. % 76.16/76.39 195804[89:MRR:194.0,195803.0] || -> node4(s49)*. % 76.16/76.39 195805[89:MRR:195767.0,195804.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 195809[89:Res:53.1,195805.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 195811[89:MRR:195809.0,78381.0] || -> . % 76.16/76.39 195812[89:Spt:195811.0,195802.0,195803.0] || until2p7(s49)*+ -> . % 76.16/76.39 195813[89:Spt:195811.0,195802.1] || -> node4(s48)*. % 76.16/76.39 195814[89:MRR:78384.0,195813.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 195817[89:Res:53.1,195814.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 195820[89:Res:195817.0,61.1] always3(s48) || -> . % 76.16/76.39 195821[89:SSi:195820.0,78281.0,78387.0,192147.0,195801.0,195813.0] || -> . % 76.16/76.39 195822[88:Spt:195821.0,195800.0,195801.0] || until2p7(s48)*+ -> . % 76.16/76.39 195823[88:Spt:195821.0,195800.1] || -> node4(s47)*. % 76.16/76.39 195825[88:MRR:777.0,195823.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 195837[88:Res:53.1,195825.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 195839[89:Spt:195837.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 195841[89:Res:195839.0,61.1] always3(s47) || -> . % 76.16/76.39 195842[89:SSi:195841.0,78277.0,78280.0,192146.0,195799.0,195823.0] || -> . % 76.16/76.39 195843[89:Spt:195842.0,195837.0,195839.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 195844[89:Spt:195842.0,195837.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 195848[89:Res:195844.0,61.1] always3(s48) || -> . % 76.16/76.39 195849[89:SSi:195848.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 195850[87:Spt:195849.0,195798.0,195799.0] || until2p7(s47)*+ -> . % 76.16/76.39 195851[87:Spt:195849.0,195798.1] || -> node4(s46)*. % 76.16/76.39 195853[87:MRR:780.0,195851.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 195860[87:Res:53.1,195853.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 195865[88:Spt:195860.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 195867[88:Res:195865.0,61.1] always3(s46) || -> . % 76.16/76.39 195868[88:SSi:195867.0,78272.0,78276.0,192145.0,195797.0,195851.0] || -> . % 76.16/76.39 195869[88:Spt:195868.0,195860.0,195865.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 195870[88:Spt:195868.0,195860.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 195874[88:Res:195870.0,61.1] always3(s47) || -> . % 76.16/76.39 195875[88:SSi:195874.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 195876[86:Spt:195875.0,195796.0,195797.0] || until2p7(s46)*+ -> . % 76.16/76.39 195877[86:Spt:195875.0,195796.1] || -> node4(s45)*. % 76.16/76.39 195879[86:MRR:783.0,195877.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 195882[86:Res:53.1,195879.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 195884[87:Spt:195882.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 195886[87:Res:195884.0,61.1] always3(s45) || -> . % 76.16/76.39 195887[87:SSi:195886.0,78268.0,78271.0,192144.0,195795.0,195877.0] || -> . % 76.16/76.39 195888[87:Spt:195887.0,195882.0,195884.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 195889[87:Spt:195887.0,195882.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 195893[87:Res:195889.0,61.1] always3(s46) || -> . % 76.16/76.39 195894[87:SSi:195893.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 195895[85:Spt:195894.0,195794.0,195795.0] || until2p7(s45)*+ -> . % 76.16/76.39 195896[85:Spt:195894.0,195794.1] || -> node4(s44)*. % 76.16/76.39 195898[85:MRR:786.0,195896.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 195901[85:Res:53.1,195898.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 195903[86:Spt:195901.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 195905[86:Res:195903.0,61.1] always3(s44) || -> . % 76.16/76.39 195906[86:SSi:195905.0,78263.0,78267.0,192143.0,195793.0,195896.0] || -> . % 76.16/76.39 195907[86:Spt:195906.0,195901.0,195903.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 195908[86:Spt:195906.0,195901.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 195912[86:Res:195908.0,61.1] always3(s45) || -> . % 76.16/76.39 195913[86:SSi:195912.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 195914[84:Spt:195913.0,195792.0,195793.0] || until2p7(s44)*+ -> . % 76.16/76.39 195915[84:Spt:195913.0,195792.1] || -> node4(s43)*. % 76.16/76.39 195917[84:MRR:789.0,195915.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 195920[84:Res:53.1,195917.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 195922[85:Spt:195920.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 195924[85:Res:195922.0,61.1] always3(s43) || -> . % 76.16/76.39 195925[85:SSi:195924.0,78259.0,78262.0,192142.0,195791.0,195915.0] || -> . % 76.16/76.39 195926[85:Spt:195925.0,195920.0,195922.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 195927[85:Spt:195925.0,195920.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 195931[85:Res:195927.0,61.1] always3(s44) || -> . % 76.16/76.39 195932[85:SSi:195931.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 195933[83:Spt:195932.0,195790.0,195791.0] || until2p7(s43)*+ -> . % 76.16/76.39 195934[83:Spt:195932.0,195790.1] || -> node4(s42)*. % 76.16/76.39 195936[83:MRR:792.0,195934.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 195939[83:Res:53.1,195936.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 195944[84:Spt:195939.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 195946[84:Res:195944.0,61.1] always3(s42) || -> . % 76.16/76.39 195947[84:SSi:195946.0,78254.0,78258.0,192141.0,195789.0,195934.0] || -> . % 76.16/76.39 195948[84:Spt:195947.0,195939.0,195944.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 195949[84:Spt:195947.0,195939.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 195953[84:Res:195949.0,61.1] always3(s43) || -> . % 76.16/76.39 195954[84:SSi:195953.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 195955[82:Spt:195954.0,195788.0,195789.0] || until2p7(s42)*+ -> . % 76.16/76.39 195956[82:Spt:195954.0,195788.1] || -> node4(s41)*. % 76.16/76.39 195958[82:MRR:795.0,195956.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 195961[82:Res:53.1,195958.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 195963[83:Spt:195961.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 195965[83:Res:195963.0,61.1] always3(s41) || -> . % 76.16/76.39 195966[83:SSi:195965.0,78250.0,78253.0,192140.0,195787.0,195956.0] || -> . % 76.16/76.39 195967[83:Spt:195966.0,195961.0,195963.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 195968[83:Spt:195966.0,195961.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 195972[83:Res:195968.0,61.1] always3(s42) || -> . % 76.16/76.39 195973[83:SSi:195972.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 195974[81:Spt:195973.0,195786.0,195787.0] || until2p7(s41)*+ -> . % 76.16/76.39 195975[81:Spt:195973.0,195786.1] || -> node4(s40)*. % 76.16/76.39 195977[81:MRR:798.0,195975.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 195980[81:Res:53.1,195977.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 195982[82:Spt:195980.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 195984[82:Res:195982.0,61.1] always3(s40) || -> . % 76.16/76.39 195985[82:SSi:195984.0,78245.0,78249.0,192139.0,195785.0,195975.0] || -> . % 76.16/76.39 195986[82:Spt:195985.0,195980.0,195982.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 195987[82:Spt:195985.0,195980.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 195991[82:Res:195987.0,61.1] always3(s41) || -> . % 76.16/76.39 195992[82:SSi:195991.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 195993[80:Spt:195992.0,195784.0,195785.0] || until2p7(s40)*+ -> . % 76.16/76.39 195994[80:Spt:195992.0,195784.1] || -> node4(s39)*. % 76.16/76.39 195996[80:MRR:801.0,195994.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 195999[80:Res:53.1,195996.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 196001[81:Spt:195999.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 196003[81:Res:196001.0,61.1] always3(s39) || -> . % 76.16/76.39 196004[81:SSi:196003.0,78241.0,78244.0,192138.0,195783.0,195994.0] || -> . % 76.16/76.39 196005[81:Spt:196004.0,195999.0,196001.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 196006[81:Spt:196004.0,195999.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 196010[81:Res:196006.0,61.1] always3(s40) || -> . % 76.16/76.39 196011[81:SSi:196010.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 196012[79:Spt:196011.0,195782.0,195783.0] || until2p7(s39)*+ -> . % 76.16/76.39 196013[79:Spt:196011.0,195782.1] || -> node4(s38)*. % 76.16/76.39 196015[79:MRR:804.0,196013.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 196018[79:Res:53.1,196015.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 196023[80:Spt:196018.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 196025[80:Res:196023.0,61.1] always3(s38) || -> . % 76.16/76.39 196026[80:SSi:196025.0,78236.0,78240.0,192137.0,195781.0,196013.0] || -> . % 76.16/76.39 196027[80:Spt:196026.0,196018.0,196023.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 196028[80:Spt:196026.0,196018.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 196032[80:Res:196028.0,61.1] always3(s39) || -> . % 76.16/76.39 196033[80:SSi:196032.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 196034[78:Spt:196033.0,195780.0,195781.0] || until2p7(s38)*+ -> . % 76.16/76.39 196035[78:Spt:196033.0,195780.1] || -> node4(s37)*. % 76.16/76.39 196037[78:MRR:807.0,196035.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 196040[78:Res:53.1,196037.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 196042[79:Spt:196040.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 196044[79:Res:196042.0,61.1] always3(s37) || -> . % 76.16/76.39 196045[79:SSi:196044.0,78232.0,78235.0,192136.0,195779.0,196035.0] || -> . % 76.16/76.39 196046[79:Spt:196045.0,196040.0,196042.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.39 196047[79:Spt:196045.0,196040.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 196051[79:Res:196047.0,61.1] always3(s38) || -> . % 76.16/76.39 196052[79:SSi:196051.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.39 196053[77:Spt:196052.0,195778.0,195779.0] || until2p7(s37)*+ -> . % 76.16/76.39 196054[77:Spt:196052.0,195778.1] || -> node4(s36)*. % 76.16/76.39 196056[77:MRR:810.0,196054.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.39 196059[77:Res:53.1,196056.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.39 196061[78:Spt:196059.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 196063[78:Res:196061.0,61.1] always3(s36) || -> . % 76.16/76.39 196064[78:SSi:196063.0,78227.0,78231.0,192135.0,195777.0,196054.0] || -> . % 76.16/76.39 196065[78:Spt:196064.0,196059.0,196061.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.39 196066[78:Spt:196064.0,196059.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 196070[78:Res:196066.0,61.1] always3(s37) || -> . % 76.16/76.39 196071[78:SSi:196070.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.39 196072[76:Spt:196071.0,195776.0,195777.0] || until2p7(s36)*+ -> . % 76.16/76.39 196073[76:Spt:196071.0,195776.1] || -> node4(s35)*. % 76.16/76.39 196075[76:MRR:813.0,196073.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.39 196078[76:Res:53.1,196075.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.39 196080[77:Spt:196078.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 196082[77:Res:196080.0,61.1] always3(s35) || -> . % 76.16/76.39 196083[77:SSi:196082.0,78223.0,78226.0,192134.0,195775.0,196073.0] || -> . % 76.16/76.39 196084[77:Spt:196083.0,196078.0,196080.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.39 196085[77:Spt:196083.0,196078.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 196089[77:Res:196085.0,61.1] always3(s36) || -> . % 76.16/76.39 196090[77:SSi:196089.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.39 196091[75:Spt:196090.0,195774.0,195775.0] || until2p7(s35)*+ -> . % 76.16/76.39 196092[75:Spt:196090.0,195774.1] || -> node4(s34)*. % 76.16/76.39 196094[75:MRR:816.0,196092.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.39 196097[75:Res:53.1,196094.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.39 196102[76:Spt:196097.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 196104[76:Res:196102.0,61.1] always3(s34) || -> . % 76.16/76.39 196105[76:SSi:196104.0,78218.0,78222.0,192133.0,195773.0,196092.0] || -> . % 76.16/76.39 196106[76:Spt:196105.0,196097.0,196102.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.39 196107[76:Spt:196105.0,196097.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 196111[76:Res:196107.0,61.1] always3(s35) || -> . % 76.16/76.39 196112[76:SSi:196111.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.39 196113[74:Spt:196112.0,195772.0,195773.0] || until2p7(s34)*+ -> . % 76.16/76.39 196114[74:Spt:196112.0,195772.1] || -> node4(s33)*. % 76.16/76.39 196116[74:MRR:819.0,196114.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.39 196119[74:Res:53.1,196116.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.39 196121[74:MRR:196119.0,195762.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 196123[74:Res:196121.0,61.1] always3(s34) || -> . % 76.16/76.39 196124[74:SSi:196123.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.39 196125[72:Spt:196124.0,195691.0,195694.0] || trans(s49,s33)*+ -> . % 76.16/76.39 196126[72:Spt:196124.0,195691.1,195691.2,195691.3,195691.4,195691.5,195691.6,195691.7,195691.8,195691.9,195691.10,195691.11,195691.12,195691.13,195691.14,195691.15,195691.16,195691.17,195691.18,195691.19,195691.20,195691.21,195691.22,195691.23,195691.24,195691.25,195691.26,195691.27] || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 196128[72:MRR:195693.1,196125.0] xuntil6(s49) || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 196129[73:Spt:196126.0] || -> trans(s49,s32)*. % 76.16/76.39 196130[73:Res:196129.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s32)*. % 76.16/76.39 196132[73:Res:196129.0,60.0] || -> node2(s49,s32)*. % 76.16/76.39 196133[73:SSi:196130.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s32)*. % 76.16/76.39 196134[73:Res:196132.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 196193[73:SoR:196134.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 196195[73:SoR:196193.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)* xuntil6(s49). % 76.16/76.39 196196[73:SSi:196195.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s32,c_busy)* xuntil6(s49). % 76.16/76.39 196197[74:Spt:196196.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 196199[74:Res:196197.0,61.1] always3(s32) || -> . % 76.16/76.39 196200[74:SSi:196199.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.39 196201[74:Spt:196200.0,196196.1,196197.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.16/76.39 196202[74:Spt:196200.0,196196.0,196196.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 196206[74:MRR:196193.2,196201.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 196207[74:Res:53.1,196202.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 196209[74:MRR:196207.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 196210[74:MRR:196133.0,196209.0] || -> until2p7(s32)*. % 76.16/76.39 196211[74:MRR:228.0,196210.0] || -> until2p7(s33)* node4(s32). % 76.16/76.39 196212[75:Spt:196211.0] || -> until2p7(s33)*. % 76.16/76.39 196213[75:MRR:229.0,196212.0] || -> until2p7(s34)* node4(s33). % 76.16/76.39 196214[76:Spt:196213.0] || -> until2p7(s34)*. % 76.16/76.39 196215[76:MRR:230.0,196214.0] || -> until2p7(s35)* node4(s34). % 76.16/76.39 196216[77:Spt:196215.0] || -> until2p7(s35)*. % 76.16/76.39 196217[77:MRR:231.0,196216.0] || -> until2p7(s36)* node4(s35). % 76.16/76.39 196218[78:Spt:196217.0] || -> until2p7(s36)*. % 76.16/76.39 196219[78:MRR:232.0,196218.0] || -> until2p7(s37)* node4(s36). % 76.16/76.39 196220[79:Spt:196219.0] || -> until2p7(s37)*. % 76.16/76.39 196221[79:MRR:235.0,196220.0] || -> until2p7(s38)* node4(s37). % 76.16/76.39 196222[80:Spt:196221.0] || -> until2p7(s38)*. % 76.16/76.39 196223[80:MRR:236.0,196222.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 196224[81:Spt:196223.0] || -> until2p7(s39)*. % 76.16/76.39 196225[81:MRR:237.0,196224.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 196226[82:Spt:196225.0] || -> until2p7(s40)*. % 76.16/76.39 196227[82:MRR:238.0,196226.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 196228[83:Spt:196227.0] || -> until2p7(s41)*. % 76.16/76.39 196229[83:MRR:239.0,196228.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 196230[84:Spt:196229.0] || -> until2p7(s42)*. % 76.16/76.39 196231[84:MRR:240.0,196230.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 196232[85:Spt:196231.0] || -> until2p7(s43)*. % 76.16/76.39 196233[85:MRR:241.0,196232.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 196234[86:Spt:196233.0] || -> until2p7(s44)*. % 76.16/76.39 196235[86:MRR:539.0,196234.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 196236[87:Spt:196235.0] || -> until2p7(s45)*. % 76.16/76.39 196237[87:MRR:544.0,196236.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 196238[88:Spt:196237.0] || -> until2p7(s46)*. % 76.16/76.39 196239[88:MRR:549.0,196238.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 196240[89:Spt:196239.0] || -> until2p7(s47)*. % 76.16/76.39 196241[89:MRR:554.0,196240.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 196242[90:Spt:196241.0] || -> until2p7(s48)*. % 76.16/76.39 196243[90:MRR:559.0,196242.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 196244[91:Spt:196243.0] || -> until2p7(s49)*. % 76.16/76.39 196245[91:MRR:194.0,196244.0] || -> node4(s49)*. % 76.16/76.39 196246[91:MRR:196206.0,196245.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 196247[91:Res:53.1,196246.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 196249[91:MRR:196247.0,78381.0] || -> . % 76.16/76.39 196250[91:Spt:196249.0,196243.0,196244.0] || until2p7(s49)*+ -> . % 76.16/76.39 196251[91:Spt:196249.0,196243.1] || -> node4(s48)*. % 76.16/76.39 196252[91:MRR:78384.0,196251.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 196255[91:Res:53.1,196252.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 196258[91:Res:196255.0,61.1] always3(s48) || -> . % 76.16/76.39 196259[91:SSi:196258.0,78281.0,78387.0,192147.0,196242.0,196251.0] || -> . % 76.16/76.39 196260[90:Spt:196259.0,196241.0,196242.0] || until2p7(s48)*+ -> . % 76.16/76.39 196261[90:Spt:196259.0,196241.1] || -> node4(s47)*. % 76.16/76.39 196263[90:MRR:777.0,196261.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 196278[90:Res:53.1,196263.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 196283[91:Spt:196278.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 196285[91:Res:196283.0,61.1] always3(s47) || -> . % 76.16/76.39 196286[91:SSi:196285.0,78277.0,78280.0,192146.0,196240.0,196261.0] || -> . % 76.16/76.39 196287[91:Spt:196286.0,196278.0,196283.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 196288[91:Spt:196286.0,196278.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 196292[91:Res:196288.0,61.1] always3(s48) || -> . % 76.16/76.39 196293[91:SSi:196292.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 196294[89:Spt:196293.0,196239.0,196240.0] || until2p7(s47)*+ -> . % 76.16/76.39 196295[89:Spt:196293.0,196239.1] || -> node4(s46)*. % 76.16/76.39 196297[89:MRR:780.0,196295.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 196304[89:Res:53.1,196297.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 196306[90:Spt:196304.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 196308[90:Res:196306.0,61.1] always3(s46) || -> . % 76.16/76.39 196309[90:SSi:196308.0,78272.0,78276.0,192145.0,196238.0,196295.0] || -> . % 76.16/76.39 196310[90:Spt:196309.0,196304.0,196306.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 196311[90:Spt:196309.0,196304.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 196315[90:Res:196311.0,61.1] always3(s47) || -> . % 76.16/76.39 196316[90:SSi:196315.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 196317[88:Spt:196316.0,196237.0,196238.0] || until2p7(s46)*+ -> . % 76.16/76.39 196318[88:Spt:196316.0,196237.1] || -> node4(s45)*. % 76.16/76.39 196320[88:MRR:783.0,196318.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 196323[88:Res:53.1,196320.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 196328[89:Spt:196323.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 196330[89:Res:196328.0,61.1] always3(s45) || -> . % 76.16/76.39 196331[89:SSi:196330.0,78268.0,78271.0,192144.0,196236.0,196318.0] || -> . % 76.16/76.39 196332[89:Spt:196331.0,196323.0,196328.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 196333[89:Spt:196331.0,196323.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 196337[89:Res:196333.0,61.1] always3(s46) || -> . % 76.16/76.39 196338[89:SSi:196337.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 196339[87:Spt:196338.0,196235.0,196236.0] || until2p7(s45)*+ -> . % 76.16/76.39 196340[87:Spt:196338.0,196235.1] || -> node4(s44)*. % 76.16/76.39 196342[87:MRR:786.0,196340.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 196345[87:Res:53.1,196342.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 196347[88:Spt:196345.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 196349[88:Res:196347.0,61.1] always3(s44) || -> . % 76.16/76.39 196350[88:SSi:196349.0,78263.0,78267.0,192143.0,196234.0,196340.0] || -> . % 76.16/76.39 196351[88:Spt:196350.0,196345.0,196347.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 196352[88:Spt:196350.0,196345.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 196356[88:Res:196352.0,61.1] always3(s45) || -> . % 76.16/76.39 196357[88:SSi:196356.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 196358[86:Spt:196357.0,196233.0,196234.0] || until2p7(s44)*+ -> . % 76.16/76.39 196359[86:Spt:196357.0,196233.1] || -> node4(s43)*. % 76.16/76.39 196361[86:MRR:789.0,196359.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 196364[86:Res:53.1,196361.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 196366[87:Spt:196364.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 196368[87:Res:196366.0,61.1] always3(s43) || -> . % 76.16/76.39 196369[87:SSi:196368.0,78259.0,78262.0,192142.0,196232.0,196359.0] || -> . % 76.16/76.39 196370[87:Spt:196369.0,196364.0,196366.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 196371[87:Spt:196369.0,196364.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 196375[87:Res:196371.0,61.1] always3(s44) || -> . % 76.16/76.39 196376[87:SSi:196375.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 196377[85:Spt:196376.0,196231.0,196232.0] || until2p7(s43)*+ -> . % 76.16/76.39 196378[85:Spt:196376.0,196231.1] || -> node4(s42)*. % 76.16/76.39 196380[85:MRR:792.0,196378.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 196383[85:Res:53.1,196380.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 196385[86:Spt:196383.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 196387[86:Res:196385.0,61.1] always3(s42) || -> . % 76.16/76.39 196388[86:SSi:196387.0,78254.0,78258.0,192141.0,196230.0,196378.0] || -> . % 76.16/76.39 196389[86:Spt:196388.0,196383.0,196385.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 196390[86:Spt:196388.0,196383.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 196394[86:Res:196390.0,61.1] always3(s43) || -> . % 76.16/76.39 196395[86:SSi:196394.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 196396[84:Spt:196395.0,196229.0,196230.0] || until2p7(s42)*+ -> . % 76.16/76.39 196397[84:Spt:196395.0,196229.1] || -> node4(s41)*. % 76.16/76.39 196399[84:MRR:795.0,196397.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 196402[84:Res:53.1,196399.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 196407[85:Spt:196402.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 196409[85:Res:196407.0,61.1] always3(s41) || -> . % 76.16/76.39 196410[85:SSi:196409.0,78250.0,78253.0,192140.0,196228.0,196397.0] || -> . % 76.16/76.39 196411[85:Spt:196410.0,196402.0,196407.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 196412[85:Spt:196410.0,196402.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 196416[85:Res:196412.0,61.1] always3(s42) || -> . % 76.16/76.39 196417[85:SSi:196416.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 196418[83:Spt:196417.0,196227.0,196228.0] || until2p7(s41)*+ -> . % 76.16/76.39 196419[83:Spt:196417.0,196227.1] || -> node4(s40)*. % 76.16/76.39 196421[83:MRR:798.0,196419.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 196424[83:Res:53.1,196421.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 196426[84:Spt:196424.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 196428[84:Res:196426.0,61.1] always3(s40) || -> . % 76.16/76.39 196429[84:SSi:196428.0,78245.0,78249.0,192139.0,196226.0,196419.0] || -> . % 76.16/76.39 196430[84:Spt:196429.0,196424.0,196426.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 196431[84:Spt:196429.0,196424.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 196435[84:Res:196431.0,61.1] always3(s41) || -> . % 76.16/76.39 196436[84:SSi:196435.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 196437[82:Spt:196436.0,196225.0,196226.0] || until2p7(s40)*+ -> . % 76.16/76.39 196438[82:Spt:196436.0,196225.1] || -> node4(s39)*. % 76.16/76.39 196440[82:MRR:801.0,196438.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 196443[82:Res:53.1,196440.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 196445[83:Spt:196443.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 196447[83:Res:196445.0,61.1] always3(s39) || -> . % 76.16/76.39 196448[83:SSi:196447.0,78241.0,78244.0,192138.0,196224.0,196438.0] || -> . % 76.16/76.39 196449[83:Spt:196448.0,196443.0,196445.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 196450[83:Spt:196448.0,196443.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 196454[83:Res:196450.0,61.1] always3(s40) || -> . % 76.16/76.39 196455[83:SSi:196454.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 196456[81:Spt:196455.0,196223.0,196224.0] || until2p7(s39)*+ -> . % 76.16/76.39 196457[81:Spt:196455.0,196223.1] || -> node4(s38)*. % 76.16/76.39 196459[81:MRR:804.0,196457.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 196462[81:Res:53.1,196459.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 196464[82:Spt:196462.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 196466[82:Res:196464.0,61.1] always3(s38) || -> . % 76.16/76.39 196467[82:SSi:196466.0,78236.0,78240.0,192137.0,196222.0,196457.0] || -> . % 76.16/76.39 196468[82:Spt:196467.0,196462.0,196464.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 196469[82:Spt:196467.0,196462.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 196473[82:Res:196469.0,61.1] always3(s39) || -> . % 76.16/76.39 196474[82:SSi:196473.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 196475[80:Spt:196474.0,196221.0,196222.0] || until2p7(s38)*+ -> . % 76.16/76.39 196476[80:Spt:196474.0,196221.1] || -> node4(s37)*. % 76.16/76.39 196478[80:MRR:807.0,196476.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 196481[80:Res:53.1,196478.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 196486[81:Spt:196481.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 196488[81:Res:196486.0,61.1] always3(s37) || -> . % 76.16/76.39 196489[81:SSi:196488.0,78232.0,78235.0,192136.0,196220.0,196476.0] || -> . % 76.16/76.39 196490[81:Spt:196489.0,196481.0,196486.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.39 196491[81:Spt:196489.0,196481.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 196495[81:Res:196491.0,61.1] always3(s38) || -> . % 76.16/76.39 196496[81:SSi:196495.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.39 196497[79:Spt:196496.0,196219.0,196220.0] || until2p7(s37)*+ -> . % 76.16/76.39 196498[79:Spt:196496.0,196219.1] || -> node4(s36)*. % 76.16/76.39 196500[79:MRR:810.0,196498.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.39 196503[79:Res:53.1,196500.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.39 196505[80:Spt:196503.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 196507[80:Res:196505.0,61.1] always3(s36) || -> . % 76.16/76.39 196508[80:SSi:196507.0,78227.0,78231.0,192135.0,196218.0,196498.0] || -> . % 76.16/76.39 196509[80:Spt:196508.0,196503.0,196505.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.39 196510[80:Spt:196508.0,196503.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 196514[80:Res:196510.0,61.1] always3(s37) || -> . % 76.16/76.39 196515[80:SSi:196514.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.39 196516[78:Spt:196515.0,196217.0,196218.0] || until2p7(s36)*+ -> . % 76.16/76.39 196517[78:Spt:196515.0,196217.1] || -> node4(s35)*. % 76.16/76.39 196519[78:MRR:813.0,196517.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.39 196522[78:Res:53.1,196519.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.39 196524[79:Spt:196522.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 196526[79:Res:196524.0,61.1] always3(s35) || -> . % 76.16/76.39 196527[79:SSi:196526.0,78223.0,78226.0,192134.0,196216.0,196517.0] || -> . % 76.16/76.39 196528[79:Spt:196527.0,196522.0,196524.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.39 196529[79:Spt:196527.0,196522.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 196533[79:Res:196529.0,61.1] always3(s36) || -> . % 76.16/76.39 196534[79:SSi:196533.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.39 196535[77:Spt:196534.0,196215.0,196216.0] || until2p7(s35)*+ -> . % 76.16/76.39 196536[77:Spt:196534.0,196215.1] || -> node4(s34)*. % 76.16/76.39 196538[77:MRR:816.0,196536.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.39 196541[77:Res:53.1,196538.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.39 196543[78:Spt:196541.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 196545[78:Res:196543.0,61.1] always3(s34) || -> . % 76.16/76.39 196546[78:SSi:196545.0,78218.0,78222.0,192133.0,196214.0,196536.0] || -> . % 76.16/76.39 196547[78:Spt:196546.0,196541.0,196543.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.39 196548[78:Spt:196546.0,196541.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 196552[78:Res:196548.0,61.1] always3(s35) || -> . % 76.16/76.39 196553[78:SSi:196552.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.39 196554[76:Spt:196553.0,196213.0,196214.0] || until2p7(s34)*+ -> . % 76.16/76.39 196555[76:Spt:196553.0,196213.1] || -> node4(s33)*. % 76.16/76.39 196557[76:MRR:819.0,196555.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.39 196560[76:Res:53.1,196557.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.39 196565[77:Spt:196560.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 196567[77:Res:196565.0,61.1] always3(s33) || -> . % 76.16/76.39 196568[77:SSi:196567.0,78214.0,78217.0,192132.0,196212.0,196555.0] || -> . % 76.16/76.39 196569[77:Spt:196568.0,196560.0,196565.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.39 196570[77:Spt:196568.0,196560.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 196574[77:Res:196570.0,61.1] always3(s34) || -> . % 76.16/76.39 196575[77:SSi:196574.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.39 196576[75:Spt:196575.0,196211.0,196212.0] || until2p7(s33)*+ -> . % 76.16/76.39 196577[75:Spt:196575.0,196211.1] || -> node4(s32)*. % 76.16/76.39 196579[75:MRR:822.0,196577.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.39 196582[75:Res:53.1,196579.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.39 196584[75:MRR:196582.0,196201.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 196586[75:Res:196584.0,61.1] always3(s33) || -> . % 76.16/76.39 196587[75:SSi:196586.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.39 196588[73:Spt:196587.0,196126.0,196129.0] || trans(s49,s32)*+ -> . % 76.16/76.39 196589[73:Spt:196587.0,196126.1,196126.2,196126.3,196126.4,196126.5,196126.6,196126.7,196126.8,196126.9,196126.10,196126.11,196126.12,196126.13,196126.14,196126.15,196126.16,196126.17,196126.18,196126.19,196126.20,196126.21,196126.22,196126.23,196126.24,196126.25,196126.26] || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 196591[73:MRR:196128.1,196588.0] xuntil6(s49) || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 196592[74:Spt:196589.0] || -> trans(s49,s31)*. % 76.16/76.39 196593[74:Res:196592.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s31)*. % 76.16/76.39 196595[74:Res:196592.0,60.0] || -> node2(s49,s31)*. % 76.16/76.39 196596[74:SSi:196593.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s31)*. % 76.16/76.39 196597[74:Res:196595.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 196657[74:SoR:196597.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 196659[74:SoR:196657.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.16/76.39 196660[74:SSi:196659.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.16/76.39 196661[75:Spt:196660.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 196663[75:Res:196661.0,61.1] always3(s31) || -> . % 76.16/76.39 196664[75:SSi:196663.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.39 196665[75:Spt:196664.0,196660.1,196661.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.16/76.39 196666[75:Spt:196664.0,196660.0,196660.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 196670[75:MRR:196657.2,196665.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 196671[75:Res:53.1,196666.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 196673[75:MRR:196671.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 196674[75:MRR:196596.0,196673.0] || -> until2p7(s31)*. % 76.16/76.39 196675[75:MRR:227.0,196674.0] || -> until2p7(s32)* node4(s31). % 76.16/76.39 196676[76:Spt:196675.0] || -> until2p7(s32)*. % 76.16/76.39 196677[76:MRR:228.0,196676.0] || -> until2p7(s33)* node4(s32). % 76.16/76.39 196678[77:Spt:196677.0] || -> until2p7(s33)*. % 76.16/76.39 196679[77:MRR:229.0,196678.0] || -> until2p7(s34)* node4(s33). % 76.16/76.39 196680[78:Spt:196679.0] || -> until2p7(s34)*. % 76.16/76.39 196681[78:MRR:230.0,196680.0] || -> until2p7(s35)* node4(s34). % 76.16/76.39 196682[79:Spt:196681.0] || -> until2p7(s35)*. % 76.16/76.39 196683[79:MRR:231.0,196682.0] || -> until2p7(s36)* node4(s35). % 76.16/76.39 196684[80:Spt:196683.0] || -> until2p7(s36)*. % 76.16/76.39 196685[80:MRR:232.0,196684.0] || -> until2p7(s37)* node4(s36). % 76.16/76.39 196686[81:Spt:196685.0] || -> until2p7(s37)*. % 76.16/76.39 196687[81:MRR:235.0,196686.0] || -> until2p7(s38)* node4(s37). % 76.16/76.39 196688[82:Spt:196687.0] || -> until2p7(s38)*. % 76.16/76.39 196689[82:MRR:236.0,196688.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 196690[83:Spt:196689.0] || -> until2p7(s39)*. % 76.16/76.39 196691[83:MRR:237.0,196690.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 196692[84:Spt:196691.0] || -> until2p7(s40)*. % 76.16/76.39 196693[84:MRR:238.0,196692.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 196694[85:Spt:196693.0] || -> until2p7(s41)*. % 76.16/76.39 196695[85:MRR:239.0,196694.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 196696[86:Spt:196695.0] || -> until2p7(s42)*. % 76.16/76.39 196697[86:MRR:240.0,196696.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 196698[87:Spt:196697.0] || -> until2p7(s43)*. % 76.16/76.39 196699[87:MRR:241.0,196698.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 196700[88:Spt:196699.0] || -> until2p7(s44)*. % 76.16/76.39 196701[88:MRR:539.0,196700.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 196702[89:Spt:196701.0] || -> until2p7(s45)*. % 76.16/76.39 196703[89:MRR:544.0,196702.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 196704[90:Spt:196703.0] || -> until2p7(s46)*. % 76.16/76.39 196705[90:MRR:549.0,196704.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 196706[91:Spt:196705.0] || -> until2p7(s47)*. % 76.16/76.39 196707[91:MRR:554.0,196706.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 196708[92:Spt:196707.0] || -> until2p7(s48)*. % 76.16/76.39 196709[92:MRR:559.0,196708.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 196710[93:Spt:196709.0] || -> until2p7(s49)*. % 76.16/76.39 196711[93:MRR:194.0,196710.0] || -> node4(s49)*. % 76.16/76.39 196712[93:MRR:196670.0,196711.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 196716[93:Res:53.1,196712.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 196718[93:MRR:196716.0,78381.0] || -> . % 76.16/76.39 196719[93:Spt:196718.0,196709.0,196710.0] || until2p7(s49)*+ -> . % 76.16/76.39 196720[93:Spt:196718.0,196709.1] || -> node4(s48)*. % 76.16/76.39 196721[93:MRR:78384.0,196720.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 196724[93:Res:53.1,196721.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 196727[93:Res:196724.0,61.1] always3(s48) || -> . % 76.16/76.39 196728[93:SSi:196727.0,78281.0,78387.0,192147.0,196708.0,196720.0] || -> . % 76.16/76.39 196729[92:Spt:196728.0,196707.0,196708.0] || until2p7(s48)*+ -> . % 76.16/76.39 196730[92:Spt:196728.0,196707.1] || -> node4(s47)*. % 76.16/76.39 196732[92:MRR:777.0,196730.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 196744[92:Res:53.1,196732.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 196746[93:Spt:196744.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 196748[93:Res:196746.0,61.1] always3(s47) || -> . % 76.16/76.39 196749[93:SSi:196748.0,78277.0,78280.0,192146.0,196706.0,196730.0] || -> . % 76.16/76.39 196750[93:Spt:196749.0,196744.0,196746.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 196751[93:Spt:196749.0,196744.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 196755[93:Res:196751.0,61.1] always3(s48) || -> . % 76.16/76.39 196756[93:SSi:196755.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 196757[91:Spt:196756.0,196705.0,196706.0] || until2p7(s47)*+ -> . % 76.16/76.39 196758[91:Spt:196756.0,196705.1] || -> node4(s46)*. % 76.16/76.39 196760[91:MRR:780.0,196758.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 196767[91:Res:53.1,196760.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 196772[92:Spt:196767.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 196774[92:Res:196772.0,61.1] always3(s46) || -> . % 76.16/76.39 196775[92:SSi:196774.0,78272.0,78276.0,192145.0,196704.0,196758.0] || -> . % 76.16/76.39 196776[92:Spt:196775.0,196767.0,196772.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 196777[92:Spt:196775.0,196767.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 196781[92:Res:196777.0,61.1] always3(s47) || -> . % 76.16/76.39 196782[92:SSi:196781.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 196783[90:Spt:196782.0,196703.0,196704.0] || until2p7(s46)*+ -> . % 76.16/76.39 196784[90:Spt:196782.0,196703.1] || -> node4(s45)*. % 76.16/76.39 196786[90:MRR:783.0,196784.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 196789[90:Res:53.1,196786.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 196791[91:Spt:196789.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 196793[91:Res:196791.0,61.1] always3(s45) || -> . % 76.16/76.39 196794[91:SSi:196793.0,78268.0,78271.0,192144.0,196702.0,196784.0] || -> . % 76.16/76.39 196795[91:Spt:196794.0,196789.0,196791.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 196796[91:Spt:196794.0,196789.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 196800[91:Res:196796.0,61.1] always3(s46) || -> . % 76.16/76.39 196801[91:SSi:196800.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 196802[89:Spt:196801.0,196701.0,196702.0] || until2p7(s45)*+ -> . % 76.16/76.39 196803[89:Spt:196801.0,196701.1] || -> node4(s44)*. % 76.16/76.39 196805[89:MRR:786.0,196803.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 196808[89:Res:53.1,196805.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 196810[90:Spt:196808.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 196812[90:Res:196810.0,61.1] always3(s44) || -> . % 76.16/76.39 196813[90:SSi:196812.0,78263.0,78267.0,192143.0,196700.0,196803.0] || -> . % 76.16/76.39 196814[90:Spt:196813.0,196808.0,196810.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 196815[90:Spt:196813.0,196808.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 196819[90:Res:196815.0,61.1] always3(s45) || -> . % 76.16/76.39 196820[90:SSi:196819.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 196821[88:Spt:196820.0,196699.0,196700.0] || until2p7(s44)*+ -> . % 76.16/76.39 196822[88:Spt:196820.0,196699.1] || -> node4(s43)*. % 76.16/76.39 196824[88:MRR:789.0,196822.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 196827[88:Res:53.1,196824.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 196829[89:Spt:196827.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 196831[89:Res:196829.0,61.1] always3(s43) || -> . % 76.16/76.39 196832[89:SSi:196831.0,78259.0,78262.0,192142.0,196698.0,196822.0] || -> . % 76.16/76.39 196833[89:Spt:196832.0,196827.0,196829.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 196834[89:Spt:196832.0,196827.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 196838[89:Res:196834.0,61.1] always3(s44) || -> . % 76.16/76.39 196839[89:SSi:196838.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 196840[87:Spt:196839.0,196697.0,196698.0] || until2p7(s43)*+ -> . % 76.16/76.39 196841[87:Spt:196839.0,196697.1] || -> node4(s42)*. % 76.16/76.39 196843[87:MRR:792.0,196841.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 196846[87:Res:53.1,196843.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 196851[88:Spt:196846.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 196853[88:Res:196851.0,61.1] always3(s42) || -> . % 76.16/76.39 196854[88:SSi:196853.0,78254.0,78258.0,192141.0,196696.0,196841.0] || -> . % 76.16/76.39 196855[88:Spt:196854.0,196846.0,196851.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 196856[88:Spt:196854.0,196846.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 196860[88:Res:196856.0,61.1] always3(s43) || -> . % 76.16/76.39 196861[88:SSi:196860.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 196862[86:Spt:196861.0,196695.0,196696.0] || until2p7(s42)*+ -> . % 76.16/76.39 196863[86:Spt:196861.0,196695.1] || -> node4(s41)*. % 76.16/76.39 196865[86:MRR:795.0,196863.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 196868[86:Res:53.1,196865.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 196870[87:Spt:196868.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 196872[87:Res:196870.0,61.1] always3(s41) || -> . % 76.16/76.39 196873[87:SSi:196872.0,78250.0,78253.0,192140.0,196694.0,196863.0] || -> . % 76.16/76.39 196874[87:Spt:196873.0,196868.0,196870.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 196875[87:Spt:196873.0,196868.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 196879[87:Res:196875.0,61.1] always3(s42) || -> . % 76.16/76.39 196880[87:SSi:196879.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 196881[85:Spt:196880.0,196693.0,196694.0] || until2p7(s41)*+ -> . % 76.16/76.39 196882[85:Spt:196880.0,196693.1] || -> node4(s40)*. % 76.16/76.39 196884[85:MRR:798.0,196882.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 196887[85:Res:53.1,196884.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 196889[86:Spt:196887.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 196891[86:Res:196889.0,61.1] always3(s40) || -> . % 76.16/76.39 196892[86:SSi:196891.0,78245.0,78249.0,192139.0,196692.0,196882.0] || -> . % 76.16/76.39 196893[86:Spt:196892.0,196887.0,196889.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 196894[86:Spt:196892.0,196887.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 196898[86:Res:196894.0,61.1] always3(s41) || -> . % 76.16/76.39 196899[86:SSi:196898.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 196900[84:Spt:196899.0,196691.0,196692.0] || until2p7(s40)*+ -> . % 76.16/76.39 196901[84:Spt:196899.0,196691.1] || -> node4(s39)*. % 76.16/76.39 196903[84:MRR:801.0,196901.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 196906[84:Res:53.1,196903.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 196908[85:Spt:196906.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 196910[85:Res:196908.0,61.1] always3(s39) || -> . % 76.16/76.39 196911[85:SSi:196910.0,78241.0,78244.0,192138.0,196690.0,196901.0] || -> . % 76.16/76.39 196912[85:Spt:196911.0,196906.0,196908.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 196913[85:Spt:196911.0,196906.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 196917[85:Res:196913.0,61.1] always3(s40) || -> . % 76.16/76.39 196918[85:SSi:196917.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 196919[83:Spt:196918.0,196689.0,196690.0] || until2p7(s39)*+ -> . % 76.16/76.39 196920[83:Spt:196918.0,196689.1] || -> node4(s38)*. % 76.16/76.39 196922[83:MRR:804.0,196920.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 196925[83:Res:53.1,196922.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 196930[84:Spt:196925.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 196932[84:Res:196930.0,61.1] always3(s38) || -> . % 76.16/76.39 196933[84:SSi:196932.0,78236.0,78240.0,192137.0,196688.0,196920.0] || -> . % 76.16/76.39 196934[84:Spt:196933.0,196925.0,196930.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 196935[84:Spt:196933.0,196925.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 196939[84:Res:196935.0,61.1] always3(s39) || -> . % 76.16/76.39 196940[84:SSi:196939.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 196941[82:Spt:196940.0,196687.0,196688.0] || until2p7(s38)*+ -> . % 76.16/76.39 196942[82:Spt:196940.0,196687.1] || -> node4(s37)*. % 76.16/76.39 196944[82:MRR:807.0,196942.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 196947[82:Res:53.1,196944.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 196949[83:Spt:196947.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 196951[83:Res:196949.0,61.1] always3(s37) || -> . % 76.16/76.39 196952[83:SSi:196951.0,78232.0,78235.0,192136.0,196686.0,196942.0] || -> . % 76.16/76.39 196953[83:Spt:196952.0,196947.0,196949.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.39 196954[83:Spt:196952.0,196947.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 196958[83:Res:196954.0,61.1] always3(s38) || -> . % 76.16/76.39 196959[83:SSi:196958.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.39 196960[81:Spt:196959.0,196685.0,196686.0] || until2p7(s37)*+ -> . % 76.16/76.39 196961[81:Spt:196959.0,196685.1] || -> node4(s36)*. % 76.16/76.39 196963[81:MRR:810.0,196961.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.39 196966[81:Res:53.1,196963.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.39 196968[82:Spt:196966.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 196970[82:Res:196968.0,61.1] always3(s36) || -> . % 76.16/76.39 196971[82:SSi:196970.0,78227.0,78231.0,192135.0,196684.0,196961.0] || -> . % 76.16/76.39 196972[82:Spt:196971.0,196966.0,196968.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.39 196973[82:Spt:196971.0,196966.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 196977[82:Res:196973.0,61.1] always3(s37) || -> . % 76.16/76.39 196978[82:SSi:196977.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.39 196979[80:Spt:196978.0,196683.0,196684.0] || until2p7(s36)*+ -> . % 76.16/76.39 196980[80:Spt:196978.0,196683.1] || -> node4(s35)*. % 76.16/76.39 196982[80:MRR:813.0,196980.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.39 196985[80:Res:53.1,196982.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.39 196987[81:Spt:196985.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 196989[81:Res:196987.0,61.1] always3(s35) || -> . % 76.16/76.39 196990[81:SSi:196989.0,78223.0,78226.0,192134.0,196682.0,196980.0] || -> . % 76.16/76.39 196991[81:Spt:196990.0,196985.0,196987.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.39 196992[81:Spt:196990.0,196985.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 196996[81:Res:196992.0,61.1] always3(s36) || -> . % 76.16/76.39 196997[81:SSi:196996.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.39 196998[79:Spt:196997.0,196681.0,196682.0] || until2p7(s35)*+ -> . % 76.16/76.39 196999[79:Spt:196997.0,196681.1] || -> node4(s34)*. % 76.16/76.39 197001[79:MRR:816.0,196999.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.39 197004[79:Res:53.1,197001.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.39 197009[80:Spt:197004.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 197011[80:Res:197009.0,61.1] always3(s34) || -> . % 76.16/76.39 197012[80:SSi:197011.0,78218.0,78222.0,192133.0,196680.0,196999.0] || -> . % 76.16/76.39 197013[80:Spt:197012.0,197004.0,197009.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.39 197014[80:Spt:197012.0,197004.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 197018[80:Res:197014.0,61.1] always3(s35) || -> . % 76.16/76.39 197019[80:SSi:197018.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.39 197020[78:Spt:197019.0,196679.0,196680.0] || until2p7(s34)*+ -> . % 76.16/76.39 197021[78:Spt:197019.0,196679.1] || -> node4(s33)*. % 76.16/76.39 197023[78:MRR:819.0,197021.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.39 197026[78:Res:53.1,197023.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.39 197028[79:Spt:197026.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 197030[79:Res:197028.0,61.1] always3(s33) || -> . % 76.16/76.39 197031[79:SSi:197030.0,78214.0,78217.0,192132.0,196678.0,197021.0] || -> . % 76.16/76.39 197032[79:Spt:197031.0,197026.0,197028.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.39 197033[79:Spt:197031.0,197026.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 197037[79:Res:197033.0,61.1] always3(s34) || -> . % 76.16/76.39 197038[79:SSi:197037.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.39 197039[77:Spt:197038.0,196677.0,196678.0] || until2p7(s33)*+ -> . % 76.16/76.39 197040[77:Spt:197038.0,196677.1] || -> node4(s32)*. % 76.16/76.39 197042[77:MRR:822.0,197040.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.39 197045[77:Res:53.1,197042.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.39 197047[78:Spt:197045.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 197049[78:Res:197047.0,61.1] always3(s32) || -> . % 76.16/76.39 197050[78:SSi:197049.0,78209.0,78213.0,192131.0,196676.0,197040.0] || -> . % 76.16/76.39 197051[78:Spt:197050.0,197045.0,197047.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.39 197052[78:Spt:197050.0,197045.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 197056[78:Res:197052.0,61.1] always3(s33) || -> . % 76.16/76.39 197057[78:SSi:197056.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.39 197058[76:Spt:197057.0,196675.0,196676.0] || until2p7(s32)*+ -> . % 76.16/76.39 197059[76:Spt:197057.0,196675.1] || -> node4(s31)*. % 76.16/76.39 197061[76:MRR:825.0,197059.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.39 197064[76:Res:53.1,197061.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.39 197066[76:MRR:197064.0,196665.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 197068[76:Res:197066.0,61.1] always3(s32) || -> . % 76.16/76.39 197069[76:SSi:197068.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.39 197070[74:Spt:197069.0,196589.0,196592.0] || trans(s49,s31)*+ -> . % 76.16/76.39 197071[74:Spt:197069.0,196589.1,196589.2,196589.3,196589.4,196589.5,196589.6,196589.7,196589.8,196589.9,196589.10,196589.11,196589.12,196589.13,196589.14,196589.15,196589.16,196589.17,196589.18,196589.19,196589.20,196589.21,196589.22,196589.23,196589.24,196589.25] || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 197073[74:MRR:196591.1,197070.0] xuntil6(s49) || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 197074[75:Spt:197071.0] || -> trans(s49,s30)*. % 76.16/76.39 197075[75:Res:197074.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s30)*. % 76.16/76.39 197077[75:Res:197074.0,60.0] || -> node2(s49,s30)*. % 76.16/76.39 197078[75:SSi:197075.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s30)*. % 76.16/76.39 197079[75:Res:197077.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 197146[75:SoR:197079.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 197148[75:SoR:197146.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)* xuntil6(s49). % 76.16/76.39 197149[75:SSi:197148.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s30,c_busy)* xuntil6(s49). % 76.16/76.39 197150[76:Spt:197149.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 197152[76:Res:197150.0,61.1] always3(s30) || -> . % 76.16/76.39 197153[76:SSi:197152.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.39 197154[76:Spt:197153.0,197149.1,197150.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.16/76.39 197155[76:Spt:197153.0,197149.0,197149.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 197159[76:MRR:197146.2,197154.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 197160[76:Res:53.1,197155.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 197162[76:MRR:197160.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 197163[76:MRR:197078.0,197162.0] || -> until2p7(s30)*. % 76.16/76.39 197164[76:MRR:226.0,197163.0] || -> until2p7(s31)* node4(s30). % 76.16/76.39 197165[77:Spt:197164.0] || -> until2p7(s31)*. % 76.16/76.39 197166[77:MRR:227.0,197165.0] || -> until2p7(s32)* node4(s31). % 76.16/76.39 197167[78:Spt:197166.0] || -> until2p7(s32)*. % 76.16/76.39 197168[78:MRR:228.0,197167.0] || -> until2p7(s33)* node4(s32). % 76.16/76.39 197169[79:Spt:197168.0] || -> until2p7(s33)*. % 76.16/76.39 197170[79:MRR:229.0,197169.0] || -> until2p7(s34)* node4(s33). % 76.16/76.39 197171[80:Spt:197170.0] || -> until2p7(s34)*. % 76.16/76.39 197172[80:MRR:230.0,197171.0] || -> until2p7(s35)* node4(s34). % 76.16/76.39 197173[81:Spt:197172.0] || -> until2p7(s35)*. % 76.16/76.39 197174[81:MRR:231.0,197173.0] || -> until2p7(s36)* node4(s35). % 76.16/76.39 197175[82:Spt:197174.0] || -> until2p7(s36)*. % 76.16/76.39 197176[82:MRR:232.0,197175.0] || -> until2p7(s37)* node4(s36). % 76.16/76.39 197177[83:Spt:197176.0] || -> until2p7(s37)*. % 76.16/76.39 197178[83:MRR:235.0,197177.0] || -> until2p7(s38)* node4(s37). % 76.16/76.39 197179[84:Spt:197178.0] || -> until2p7(s38)*. % 76.16/76.39 197180[84:MRR:236.0,197179.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 197181[85:Spt:197180.0] || -> until2p7(s39)*. % 76.16/76.39 197182[85:MRR:237.0,197181.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 197183[86:Spt:197182.0] || -> until2p7(s40)*. % 76.16/76.39 197184[86:MRR:238.0,197183.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 197185[87:Spt:197184.0] || -> until2p7(s41)*. % 76.16/76.39 197186[87:MRR:239.0,197185.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 197187[88:Spt:197186.0] || -> until2p7(s42)*. % 76.16/76.39 197188[88:MRR:240.0,197187.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 197189[89:Spt:197188.0] || -> until2p7(s43)*. % 76.16/76.39 197190[89:MRR:241.0,197189.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 197191[90:Spt:197190.0] || -> until2p7(s44)*. % 76.16/76.39 197192[90:MRR:539.0,197191.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 197193[91:Spt:197192.0] || -> until2p7(s45)*. % 76.16/76.39 197194[91:MRR:544.0,197193.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 197195[92:Spt:197194.0] || -> until2p7(s46)*. % 76.16/76.39 197196[92:MRR:549.0,197195.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 197197[93:Spt:197196.0] || -> until2p7(s47)*. % 76.16/76.39 197198[93:MRR:554.0,197197.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 197199[94:Spt:197198.0] || -> until2p7(s48)*. % 76.16/76.39 197200[94:MRR:559.0,197199.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 197201[95:Spt:197200.0] || -> until2p7(s49)*. % 76.16/76.39 197202[95:MRR:194.0,197201.0] || -> node4(s49)*. % 76.16/76.39 197203[95:MRR:197159.0,197202.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 197204[95:Res:53.1,197203.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 197206[95:MRR:197204.0,78381.0] || -> . % 76.16/76.39 197207[95:Spt:197206.0,197200.0,197201.0] || until2p7(s49)*+ -> . % 76.16/76.39 197208[95:Spt:197206.0,197200.1] || -> node4(s48)*. % 76.16/76.39 197209[95:MRR:78384.0,197208.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 197212[95:Res:53.1,197209.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 197215[95:Res:197212.0,61.1] always3(s48) || -> . % 76.16/76.39 197216[95:SSi:197215.0,78281.0,78387.0,192147.0,197199.0,197208.0] || -> . % 76.16/76.39 197217[94:Spt:197216.0,197198.0,197199.0] || until2p7(s48)*+ -> . % 76.16/76.39 197218[94:Spt:197216.0,197198.1] || -> node4(s47)*. % 76.16/76.39 197220[94:MRR:777.0,197218.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 197235[94:Res:53.1,197220.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 197237[95:Spt:197235.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 197239[95:Res:197237.0,61.1] always3(s47) || -> . % 76.16/76.39 197240[95:SSi:197239.0,78277.0,78280.0,192146.0,197197.0,197218.0] || -> . % 76.16/76.39 197241[95:Spt:197240.0,197235.0,197237.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 197242[95:Spt:197240.0,197235.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 197246[95:Res:197242.0,61.1] always3(s48) || -> . % 76.16/76.39 197247[95:SSi:197246.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 197248[93:Spt:197247.0,197196.0,197197.0] || until2p7(s47)*+ -> . % 76.16/76.39 197249[93:Spt:197247.0,197196.1] || -> node4(s46)*. % 76.16/76.39 197251[93:MRR:780.0,197249.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 197261[93:Res:53.1,197251.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 197263[94:Spt:197261.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 197265[94:Res:197263.0,61.1] always3(s46) || -> . % 76.16/76.39 197266[94:SSi:197265.0,78272.0,78276.0,192145.0,197195.0,197249.0] || -> . % 76.16/76.39 197267[94:Spt:197266.0,197261.0,197263.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 197268[94:Spt:197266.0,197261.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 197272[94:Res:197268.0,61.1] always3(s47) || -> . % 76.16/76.39 197273[94:SSi:197272.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 197274[92:Spt:197273.0,197194.0,197195.0] || until2p7(s46)*+ -> . % 76.16/76.39 197275[92:Spt:197273.0,197194.1] || -> node4(s45)*. % 76.16/76.39 197277[92:MRR:783.0,197275.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 197280[92:Res:53.1,197277.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 197282[93:Spt:197280.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 197284[93:Res:197282.0,61.1] always3(s45) || -> . % 76.16/76.39 197285[93:SSi:197284.0,78268.0,78271.0,192144.0,197193.0,197275.0] || -> . % 76.16/76.39 197286[93:Spt:197285.0,197280.0,197282.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 197287[93:Spt:197285.0,197280.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 197291[93:Res:197287.0,61.1] always3(s46) || -> . % 76.16/76.39 197292[93:SSi:197291.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 197293[91:Spt:197292.0,197192.0,197193.0] || until2p7(s45)*+ -> . % 76.16/76.39 197294[91:Spt:197292.0,197192.1] || -> node4(s44)*. % 76.16/76.39 197296[91:MRR:786.0,197294.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 197299[91:Res:53.1,197296.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 197301[92:Spt:197299.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 197303[92:Res:197301.0,61.1] always3(s44) || -> . % 76.16/76.39 197304[92:SSi:197303.0,78263.0,78267.0,192143.0,197191.0,197294.0] || -> . % 76.16/76.39 197305[92:Spt:197304.0,197299.0,197301.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 197306[92:Spt:197304.0,197299.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 197310[92:Res:197306.0,61.1] always3(s45) || -> . % 76.16/76.39 197311[92:SSi:197310.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 197312[90:Spt:197311.0,197190.0,197191.0] || until2p7(s44)*+ -> . % 76.16/76.39 197313[90:Spt:197311.0,197190.1] || -> node4(s43)*. % 76.16/76.39 197315[90:MRR:789.0,197313.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 197318[90:Res:53.1,197315.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 197323[91:Spt:197318.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 197325[91:Res:197323.0,61.1] always3(s43) || -> . % 76.16/76.39 197326[91:SSi:197325.0,78259.0,78262.0,192142.0,197189.0,197313.0] || -> . % 76.16/76.39 197327[91:Spt:197326.0,197318.0,197323.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 197328[91:Spt:197326.0,197318.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 197332[91:Res:197328.0,61.1] always3(s44) || -> . % 76.16/76.39 197333[91:SSi:197332.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 197334[89:Spt:197333.0,197188.0,197189.0] || until2p7(s43)*+ -> . % 76.16/76.39 197335[89:Spt:197333.0,197188.1] || -> node4(s42)*. % 76.16/76.39 197337[89:MRR:792.0,197335.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 197340[89:Res:53.1,197337.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 197342[90:Spt:197340.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 197344[90:Res:197342.0,61.1] always3(s42) || -> . % 76.16/76.39 197345[90:SSi:197344.0,78254.0,78258.0,192141.0,197187.0,197335.0] || -> . % 76.16/76.39 197346[90:Spt:197345.0,197340.0,197342.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 197347[90:Spt:197345.0,197340.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 197351[90:Res:197347.0,61.1] always3(s43) || -> . % 76.16/76.39 197352[90:SSi:197351.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 197353[88:Spt:197352.0,197186.0,197187.0] || until2p7(s42)*+ -> . % 76.16/76.39 197354[88:Spt:197352.0,197186.1] || -> node4(s41)*. % 76.16/76.39 197356[88:MRR:795.0,197354.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 197359[88:Res:53.1,197356.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 197361[89:Spt:197359.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 197363[89:Res:197361.0,61.1] always3(s41) || -> . % 76.16/76.39 197364[89:SSi:197363.0,78250.0,78253.0,192140.0,197185.0,197354.0] || -> . % 76.16/76.39 197365[89:Spt:197364.0,197359.0,197361.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 197366[89:Spt:197364.0,197359.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 197370[89:Res:197366.0,61.1] always3(s42) || -> . % 76.16/76.39 197371[89:SSi:197370.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 197372[87:Spt:197371.0,197184.0,197185.0] || until2p7(s41)*+ -> . % 76.16/76.39 197373[87:Spt:197371.0,197184.1] || -> node4(s40)*. % 76.16/76.39 197375[87:MRR:798.0,197373.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 197378[87:Res:53.1,197375.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 197380[88:Spt:197378.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 197382[88:Res:197380.0,61.1] always3(s40) || -> . % 76.16/76.39 197383[88:SSi:197382.0,78245.0,78249.0,192139.0,197183.0,197373.0] || -> . % 76.16/76.39 197384[88:Spt:197383.0,197378.0,197380.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 197385[88:Spt:197383.0,197378.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 197389[88:Res:197385.0,61.1] always3(s41) || -> . % 76.16/76.39 197390[88:SSi:197389.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 197391[86:Spt:197390.0,197182.0,197183.0] || until2p7(s40)*+ -> . % 76.16/76.39 197392[86:Spt:197390.0,197182.1] || -> node4(s39)*. % 76.16/76.39 197394[86:MRR:801.0,197392.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 197397[86:Res:53.1,197394.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 197402[87:Spt:197397.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 197404[87:Res:197402.0,61.1] always3(s39) || -> . % 76.16/76.39 197405[87:SSi:197404.0,78241.0,78244.0,192138.0,197181.0,197392.0] || -> . % 76.16/76.39 197406[87:Spt:197405.0,197397.0,197402.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 197407[87:Spt:197405.0,197397.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 197411[87:Res:197407.0,61.1] always3(s40) || -> . % 76.16/76.39 197412[87:SSi:197411.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 197413[85:Spt:197412.0,197180.0,197181.0] || until2p7(s39)*+ -> . % 76.16/76.39 197414[85:Spt:197412.0,197180.1] || -> node4(s38)*. % 76.16/76.39 197416[85:MRR:804.0,197414.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 197419[85:Res:53.1,197416.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 197421[86:Spt:197419.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 197423[86:Res:197421.0,61.1] always3(s38) || -> . % 76.16/76.39 197424[86:SSi:197423.0,78236.0,78240.0,192137.0,197179.0,197414.0] || -> . % 76.16/76.39 197425[86:Spt:197424.0,197419.0,197421.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 197426[86:Spt:197424.0,197419.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 197430[86:Res:197426.0,61.1] always3(s39) || -> . % 76.16/76.39 197431[86:SSi:197430.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 197432[84:Spt:197431.0,197178.0,197179.0] || until2p7(s38)*+ -> . % 76.16/76.39 197433[84:Spt:197431.0,197178.1] || -> node4(s37)*. % 76.16/76.39 197435[84:MRR:807.0,197433.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 197438[84:Res:53.1,197435.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 197440[85:Spt:197438.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 197442[85:Res:197440.0,61.1] always3(s37) || -> . % 76.16/76.39 197443[85:SSi:197442.0,78232.0,78235.0,192136.0,197177.0,197433.0] || -> . % 76.16/76.39 197444[85:Spt:197443.0,197438.0,197440.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.39 197445[85:Spt:197443.0,197438.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 197449[85:Res:197445.0,61.1] always3(s38) || -> . % 76.16/76.39 197450[85:SSi:197449.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.39 197451[83:Spt:197450.0,197176.0,197177.0] || until2p7(s37)*+ -> . % 76.16/76.39 197452[83:Spt:197450.0,197176.1] || -> node4(s36)*. % 76.16/76.39 197454[83:MRR:810.0,197452.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.39 197457[83:Res:53.1,197454.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.39 197459[84:Spt:197457.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 197461[84:Res:197459.0,61.1] always3(s36) || -> . % 76.16/76.39 197462[84:SSi:197461.0,78227.0,78231.0,192135.0,197175.0,197452.0] || -> . % 76.16/76.39 197463[84:Spt:197462.0,197457.0,197459.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.39 197464[84:Spt:197462.0,197457.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 197468[84:Res:197464.0,61.1] always3(s37) || -> . % 76.16/76.39 197469[84:SSi:197468.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.39 197470[82:Spt:197469.0,197174.0,197175.0] || until2p7(s36)*+ -> . % 76.16/76.39 197471[82:Spt:197469.0,197174.1] || -> node4(s35)*. % 76.16/76.39 197473[82:MRR:813.0,197471.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.39 197476[82:Res:53.1,197473.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.39 197481[83:Spt:197476.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 197483[83:Res:197481.0,61.1] always3(s35) || -> . % 76.16/76.39 197484[83:SSi:197483.0,78223.0,78226.0,192134.0,197173.0,197471.0] || -> . % 76.16/76.39 197485[83:Spt:197484.0,197476.0,197481.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.39 197486[83:Spt:197484.0,197476.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 197490[83:Res:197486.0,61.1] always3(s36) || -> . % 76.16/76.39 197491[83:SSi:197490.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.39 197492[81:Spt:197491.0,197172.0,197173.0] || until2p7(s35)*+ -> . % 76.16/76.39 197493[81:Spt:197491.0,197172.1] || -> node4(s34)*. % 76.16/76.39 197495[81:MRR:816.0,197493.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.39 197498[81:Res:53.1,197495.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.39 197500[82:Spt:197498.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 197502[82:Res:197500.0,61.1] always3(s34) || -> . % 76.16/76.39 197503[82:SSi:197502.0,78218.0,78222.0,192133.0,197171.0,197493.0] || -> . % 76.16/76.39 197504[82:Spt:197503.0,197498.0,197500.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.39 197505[82:Spt:197503.0,197498.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 197509[82:Res:197505.0,61.1] always3(s35) || -> . % 76.16/76.39 197510[82:SSi:197509.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.39 197511[80:Spt:197510.0,197170.0,197171.0] || until2p7(s34)*+ -> . % 76.16/76.39 197512[80:Spt:197510.0,197170.1] || -> node4(s33)*. % 76.16/76.39 197514[80:MRR:819.0,197512.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.39 197517[80:Res:53.1,197514.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.39 197519[81:Spt:197517.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 197521[81:Res:197519.0,61.1] always3(s33) || -> . % 76.16/76.39 197522[81:SSi:197521.0,78214.0,78217.0,192132.0,197169.0,197512.0] || -> . % 76.16/76.39 197523[81:Spt:197522.0,197517.0,197519.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.39 197524[81:Spt:197522.0,197517.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 197528[81:Res:197524.0,61.1] always3(s34) || -> . % 76.16/76.39 197529[81:SSi:197528.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.39 197530[79:Spt:197529.0,197168.0,197169.0] || until2p7(s33)*+ -> . % 76.16/76.39 197531[79:Spt:197529.0,197168.1] || -> node4(s32)*. % 76.16/76.39 197533[79:MRR:822.0,197531.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.39 197536[79:Res:53.1,197533.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.39 197538[80:Spt:197536.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 197540[80:Res:197538.0,61.1] always3(s32) || -> . % 76.16/76.39 197541[80:SSi:197540.0,78209.0,78213.0,192131.0,197167.0,197531.0] || -> . % 76.16/76.39 197542[80:Spt:197541.0,197536.0,197538.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.39 197543[80:Spt:197541.0,197536.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 197547[80:Res:197543.0,61.1] always3(s33) || -> . % 76.16/76.39 197548[80:SSi:197547.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.39 197549[78:Spt:197548.0,197166.0,197167.0] || until2p7(s32)*+ -> . % 76.16/76.39 197550[78:Spt:197548.0,197166.1] || -> node4(s31)*. % 76.16/76.39 197552[78:MRR:825.0,197550.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.39 197555[78:Res:53.1,197552.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.39 197560[79:Spt:197555.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 197562[79:Res:197560.0,61.1] always3(s31) || -> . % 76.16/76.39 197563[79:SSi:197562.0,78205.0,78208.0,192130.0,197165.0,197550.0] || -> . % 76.16/76.39 197564[79:Spt:197563.0,197555.0,197560.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.39 197565[79:Spt:197563.0,197555.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 197569[79:Res:197565.0,61.1] always3(s32) || -> . % 76.16/76.39 197570[79:SSi:197569.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.39 197571[77:Spt:197570.0,197164.0,197165.0] || until2p7(s31)*+ -> . % 76.16/76.39 197572[77:Spt:197570.0,197164.1] || -> node4(s30)*. % 76.16/76.39 197574[77:MRR:828.0,197572.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.39 197577[77:Res:53.1,197574.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.39 197579[77:MRR:197577.0,197154.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 197581[77:Res:197579.0,61.1] always3(s31) || -> . % 76.16/76.39 197582[77:SSi:197581.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.39 197583[75:Spt:197582.0,197071.0,197074.0] || trans(s49,s30)*+ -> . % 76.16/76.39 197584[75:Spt:197582.0,197071.1,197071.2,197071.3,197071.4,197071.5,197071.6,197071.7,197071.8,197071.9,197071.10,197071.11,197071.12,197071.13,197071.14,197071.15,197071.16,197071.17,197071.18,197071.19,197071.20,197071.21,197071.22,197071.23,197071.24] || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 197586[75:MRR:197073.1,197583.0] xuntil6(s49) || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 197587[76:Spt:197584.0] || -> trans(s49,s29)*. % 76.16/76.39 197588[76:Res:197587.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s29)*. % 76.16/76.39 197590[76:Res:197587.0,60.0] || -> node2(s49,s29)*. % 76.16/76.39 197591[76:SSi:197588.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s29)*. % 76.16/76.39 197592[76:Res:197590.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.16/76.39 197660[76:SoR:197592.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.16/76.39 197662[76:SoR:197660.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.16/76.39 197663[76:SSi:197662.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.16/76.39 197664[77:Spt:197663.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.39 197666[77:Res:197664.0,61.1] always3(s29) || -> . % 76.16/76.39 197667[77:SSi:197666.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.39 197668[77:Spt:197667.0,197663.1,197664.0] || m_main_v_state(s29,c_busy)*+ -> . % 76.16/76.39 197669[77:Spt:197667.0,197663.0,197663.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 197673[77:MRR:197660.2,197668.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 197674[77:Res:53.1,197669.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 197676[77:MRR:197674.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 197677[77:MRR:197591.0,197676.0] || -> until2p7(s29)*. % 76.16/76.39 197678[77:MRR:225.0,197677.0] || -> until2p7(s30)* node4(s29). % 76.16/76.39 197679[78:Spt:197678.0] || -> until2p7(s30)*. % 76.16/76.39 197680[78:MRR:226.0,197679.0] || -> until2p7(s31)* node4(s30). % 76.16/76.39 197681[79:Spt:197680.0] || -> until2p7(s31)*. % 76.16/76.39 197682[79:MRR:227.0,197681.0] || -> until2p7(s32)* node4(s31). % 76.16/76.39 197683[80:Spt:197682.0] || -> until2p7(s32)*. % 76.16/76.39 197684[80:MRR:228.0,197683.0] || -> until2p7(s33)* node4(s32). % 76.16/76.39 197685[81:Spt:197684.0] || -> until2p7(s33)*. % 76.16/76.39 197686[81:MRR:229.0,197685.0] || -> until2p7(s34)* node4(s33). % 76.16/76.39 197687[82:Spt:197686.0] || -> until2p7(s34)*. % 76.16/76.39 197688[82:MRR:230.0,197687.0] || -> until2p7(s35)* node4(s34). % 76.16/76.39 197689[83:Spt:197688.0] || -> until2p7(s35)*. % 76.16/76.39 197690[83:MRR:231.0,197689.0] || -> until2p7(s36)* node4(s35). % 76.16/76.39 197691[84:Spt:197690.0] || -> until2p7(s36)*. % 76.16/76.39 197692[84:MRR:232.0,197691.0] || -> until2p7(s37)* node4(s36). % 76.16/76.39 197693[85:Spt:197692.0] || -> until2p7(s37)*. % 76.16/76.39 197694[85:MRR:235.0,197693.0] || -> until2p7(s38)* node4(s37). % 76.16/76.39 197695[86:Spt:197694.0] || -> until2p7(s38)*. % 76.16/76.39 197696[86:MRR:236.0,197695.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 197697[87:Spt:197696.0] || -> until2p7(s39)*. % 76.16/76.39 197698[87:MRR:237.0,197697.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 197699[88:Spt:197698.0] || -> until2p7(s40)*. % 76.16/76.39 197700[88:MRR:238.0,197699.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 197701[89:Spt:197700.0] || -> until2p7(s41)*. % 76.16/76.39 197702[89:MRR:239.0,197701.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 197703[90:Spt:197702.0] || -> until2p7(s42)*. % 76.16/76.39 197704[90:MRR:240.0,197703.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 197705[91:Spt:197704.0] || -> until2p7(s43)*. % 76.16/76.39 197706[91:MRR:241.0,197705.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 197707[92:Spt:197706.0] || -> until2p7(s44)*. % 76.16/76.39 197708[92:MRR:539.0,197707.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 197709[93:Spt:197708.0] || -> until2p7(s45)*. % 76.16/76.39 197710[93:MRR:544.0,197709.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 197711[94:Spt:197710.0] || -> until2p7(s46)*. % 76.16/76.39 197712[94:MRR:549.0,197711.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 197713[95:Spt:197712.0] || -> until2p7(s47)*. % 76.16/76.39 197714[95:MRR:554.0,197713.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 197715[96:Spt:197714.0] || -> until2p7(s48)*. % 76.16/76.39 197716[96:MRR:559.0,197715.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 197717[97:Spt:197716.0] || -> until2p7(s49)*. % 76.16/76.39 197718[97:MRR:194.0,197717.0] || -> node4(s49)*. % 76.16/76.39 197719[97:MRR:197673.0,197718.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 197720[97:Res:53.1,197719.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 197722[97:MRR:197720.0,78381.0] || -> . % 76.16/76.39 197723[97:Spt:197722.0,197716.0,197717.0] || until2p7(s49)*+ -> . % 76.16/76.39 197724[97:Spt:197722.0,197716.1] || -> node4(s48)*. % 76.16/76.39 197725[97:MRR:78384.0,197724.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 197728[97:Res:53.1,197725.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 197731[97:Res:197728.0,61.1] always3(s48) || -> . % 76.16/76.39 197732[97:SSi:197731.0,78281.0,78387.0,192147.0,197715.0,197724.0] || -> . % 76.16/76.39 197733[96:Spt:197732.0,197714.0,197715.0] || until2p7(s48)*+ -> . % 76.16/76.39 197734[96:Spt:197732.0,197714.1] || -> node4(s47)*. % 76.16/76.39 197736[96:MRR:777.0,197734.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 197751[96:Res:53.1,197736.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 197753[97:Spt:197751.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 197755[97:Res:197753.0,61.1] always3(s47) || -> . % 76.16/76.39 197756[97:SSi:197755.0,78277.0,78280.0,192146.0,197713.0,197734.0] || -> . % 76.16/76.39 197757[97:Spt:197756.0,197751.0,197753.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 197758[97:Spt:197756.0,197751.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 197762[97:Res:197758.0,61.1] always3(s48) || -> . % 76.16/76.39 197763[97:SSi:197762.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 197764[95:Spt:197763.0,197712.0,197713.0] || until2p7(s47)*+ -> . % 76.16/76.39 197765[95:Spt:197763.0,197712.1] || -> node4(s46)*. % 76.16/76.39 197767[95:MRR:780.0,197765.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 197777[95:Res:53.1,197767.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 197779[96:Spt:197777.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 197781[96:Res:197779.0,61.1] always3(s46) || -> . % 76.16/76.39 197782[96:SSi:197781.0,78272.0,78276.0,192145.0,197711.0,197765.0] || -> . % 76.16/76.39 197783[96:Spt:197782.0,197777.0,197779.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 197784[96:Spt:197782.0,197777.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 197788[96:Res:197784.0,61.1] always3(s47) || -> . % 76.16/76.39 197789[96:SSi:197788.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 197790[94:Spt:197789.0,197710.0,197711.0] || until2p7(s46)*+ -> . % 76.16/76.39 197791[94:Spt:197789.0,197710.1] || -> node4(s45)*. % 76.16/76.39 197793[94:MRR:783.0,197791.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 197796[94:Res:53.1,197793.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 197798[95:Spt:197796.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 197800[95:Res:197798.0,61.1] always3(s45) || -> . % 76.16/76.39 197801[95:SSi:197800.0,78268.0,78271.0,192144.0,197709.0,197791.0] || -> . % 76.16/76.39 197802[95:Spt:197801.0,197796.0,197798.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 197803[95:Spt:197801.0,197796.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 197807[95:Res:197803.0,61.1] always3(s46) || -> . % 76.16/76.39 197808[95:SSi:197807.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 197809[93:Spt:197808.0,197708.0,197709.0] || until2p7(s45)*+ -> . % 76.16/76.39 197810[93:Spt:197808.0,197708.1] || -> node4(s44)*. % 76.16/76.39 197812[93:MRR:786.0,197810.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 197815[93:Res:53.1,197812.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 197817[94:Spt:197815.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 197819[94:Res:197817.0,61.1] always3(s44) || -> . % 76.16/76.39 197820[94:SSi:197819.0,78263.0,78267.0,192143.0,197707.0,197810.0] || -> . % 76.16/76.39 197821[94:Spt:197820.0,197815.0,197817.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 197822[94:Spt:197820.0,197815.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 197826[94:Res:197822.0,61.1] always3(s45) || -> . % 76.16/76.39 197827[94:SSi:197826.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 197828[92:Spt:197827.0,197706.0,197707.0] || until2p7(s44)*+ -> . % 76.16/76.39 197829[92:Spt:197827.0,197706.1] || -> node4(s43)*. % 76.16/76.39 197831[92:MRR:789.0,197829.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 197834[92:Res:53.1,197831.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 197839[93:Spt:197834.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 197841[93:Res:197839.0,61.1] always3(s43) || -> . % 76.16/76.39 197842[93:SSi:197841.0,78259.0,78262.0,192142.0,197705.0,197829.0] || -> . % 76.16/76.39 197843[93:Spt:197842.0,197834.0,197839.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 197844[93:Spt:197842.0,197834.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 197848[93:Res:197844.0,61.1] always3(s44) || -> . % 76.16/76.39 197849[93:SSi:197848.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 197850[91:Spt:197849.0,197704.0,197705.0] || until2p7(s43)*+ -> . % 76.16/76.39 197851[91:Spt:197849.0,197704.1] || -> node4(s42)*. % 76.16/76.39 197853[91:MRR:792.0,197851.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 197856[91:Res:53.1,197853.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 197858[92:Spt:197856.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 197860[92:Res:197858.0,61.1] always3(s42) || -> . % 76.16/76.39 197861[92:SSi:197860.0,78254.0,78258.0,192141.0,197703.0,197851.0] || -> . % 76.16/76.39 197862[92:Spt:197861.0,197856.0,197858.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 197863[92:Spt:197861.0,197856.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 197867[92:Res:197863.0,61.1] always3(s43) || -> . % 76.16/76.39 197868[92:SSi:197867.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 197869[90:Spt:197868.0,197702.0,197703.0] || until2p7(s42)*+ -> . % 76.16/76.39 197870[90:Spt:197868.0,197702.1] || -> node4(s41)*. % 76.16/76.39 197872[90:MRR:795.0,197870.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 197875[90:Res:53.1,197872.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 197877[91:Spt:197875.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 197879[91:Res:197877.0,61.1] always3(s41) || -> . % 76.16/76.39 197880[91:SSi:197879.0,78250.0,78253.0,192140.0,197701.0,197870.0] || -> . % 76.16/76.39 197881[91:Spt:197880.0,197875.0,197877.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 197882[91:Spt:197880.0,197875.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 197886[91:Res:197882.0,61.1] always3(s42) || -> . % 76.16/76.39 197887[91:SSi:197886.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 197888[89:Spt:197887.0,197700.0,197701.0] || until2p7(s41)*+ -> . % 76.16/76.39 197889[89:Spt:197887.0,197700.1] || -> node4(s40)*. % 76.16/76.39 197891[89:MRR:798.0,197889.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 197894[89:Res:53.1,197891.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 197896[90:Spt:197894.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 197898[90:Res:197896.0,61.1] always3(s40) || -> . % 76.16/76.39 197899[90:SSi:197898.0,78245.0,78249.0,192139.0,197699.0,197889.0] || -> . % 76.16/76.39 197900[90:Spt:197899.0,197894.0,197896.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 197901[90:Spt:197899.0,197894.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 197905[90:Res:197901.0,61.1] always3(s41) || -> . % 76.16/76.39 197906[90:SSi:197905.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 197907[88:Spt:197906.0,197698.0,197699.0] || until2p7(s40)*+ -> . % 76.16/76.39 197908[88:Spt:197906.0,197698.1] || -> node4(s39)*. % 76.16/76.39 197910[88:MRR:801.0,197908.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 197913[88:Res:53.1,197910.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 197918[89:Spt:197913.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 197920[89:Res:197918.0,61.1] always3(s39) || -> . % 76.16/76.39 197921[89:SSi:197920.0,78241.0,78244.0,192138.0,197697.0,197908.0] || -> . % 76.16/76.39 197922[89:Spt:197921.0,197913.0,197918.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 197923[89:Spt:197921.0,197913.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 197927[89:Res:197923.0,61.1] always3(s40) || -> . % 76.16/76.39 197928[89:SSi:197927.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 197929[87:Spt:197928.0,197696.0,197697.0] || until2p7(s39)*+ -> . % 76.16/76.39 197930[87:Spt:197928.0,197696.1] || -> node4(s38)*. % 76.16/76.39 197932[87:MRR:804.0,197930.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 197935[87:Res:53.1,197932.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 197937[88:Spt:197935.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 197939[88:Res:197937.0,61.1] always3(s38) || -> . % 76.16/76.39 197940[88:SSi:197939.0,78236.0,78240.0,192137.0,197695.0,197930.0] || -> . % 76.16/76.39 197941[88:Spt:197940.0,197935.0,197937.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 197942[88:Spt:197940.0,197935.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 197946[88:Res:197942.0,61.1] always3(s39) || -> . % 76.16/76.39 197947[88:SSi:197946.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 197948[86:Spt:197947.0,197694.0,197695.0] || until2p7(s38)*+ -> . % 76.16/76.39 197949[86:Spt:197947.0,197694.1] || -> node4(s37)*. % 76.16/76.39 197951[86:MRR:807.0,197949.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 197954[86:Res:53.1,197951.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 197956[87:Spt:197954.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 197958[87:Res:197956.0,61.1] always3(s37) || -> . % 76.16/76.39 197959[87:SSi:197958.0,78232.0,78235.0,192136.0,197693.0,197949.0] || -> . % 76.16/76.39 197960[87:Spt:197959.0,197954.0,197956.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.39 197961[87:Spt:197959.0,197954.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 197965[87:Res:197961.0,61.1] always3(s38) || -> . % 76.16/76.39 197966[87:SSi:197965.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.39 197967[85:Spt:197966.0,197692.0,197693.0] || until2p7(s37)*+ -> . % 76.16/76.39 197968[85:Spt:197966.0,197692.1] || -> node4(s36)*. % 76.16/76.39 197970[85:MRR:810.0,197968.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.39 197973[85:Res:53.1,197970.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.39 197975[86:Spt:197973.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 197977[86:Res:197975.0,61.1] always3(s36) || -> . % 76.16/76.39 197978[86:SSi:197977.0,78227.0,78231.0,192135.0,197691.0,197968.0] || -> . % 76.16/76.39 197979[86:Spt:197978.0,197973.0,197975.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.39 197980[86:Spt:197978.0,197973.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 197984[86:Res:197980.0,61.1] always3(s37) || -> . % 76.16/76.39 197985[86:SSi:197984.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.39 197986[84:Spt:197985.0,197690.0,197691.0] || until2p7(s36)*+ -> . % 76.16/76.39 197987[84:Spt:197985.0,197690.1] || -> node4(s35)*. % 76.16/76.39 197989[84:MRR:813.0,197987.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.39 197992[84:Res:53.1,197989.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.39 197997[85:Spt:197992.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 197999[85:Res:197997.0,61.1] always3(s35) || -> . % 76.16/76.39 198000[85:SSi:197999.0,78223.0,78226.0,192134.0,197689.0,197987.0] || -> . % 76.16/76.39 198001[85:Spt:198000.0,197992.0,197997.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.39 198002[85:Spt:198000.0,197992.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 198006[85:Res:198002.0,61.1] always3(s36) || -> . % 76.16/76.39 198007[85:SSi:198006.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.39 198008[83:Spt:198007.0,197688.0,197689.0] || until2p7(s35)*+ -> . % 76.16/76.39 198009[83:Spt:198007.0,197688.1] || -> node4(s34)*. % 76.16/76.39 198011[83:MRR:816.0,198009.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.39 198014[83:Res:53.1,198011.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.39 198016[84:Spt:198014.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 198018[84:Res:198016.0,61.1] always3(s34) || -> . % 76.16/76.39 198019[84:SSi:198018.0,78218.0,78222.0,192133.0,197687.0,198009.0] || -> . % 76.16/76.39 198020[84:Spt:198019.0,198014.0,198016.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.39 198021[84:Spt:198019.0,198014.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 198025[84:Res:198021.0,61.1] always3(s35) || -> . % 76.16/76.39 198026[84:SSi:198025.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.39 198027[82:Spt:198026.0,197686.0,197687.0] || until2p7(s34)*+ -> . % 76.16/76.39 198028[82:Spt:198026.0,197686.1] || -> node4(s33)*. % 76.16/76.39 198030[82:MRR:819.0,198028.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.39 198033[82:Res:53.1,198030.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.39 198035[83:Spt:198033.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 198037[83:Res:198035.0,61.1] always3(s33) || -> . % 76.16/76.39 198038[83:SSi:198037.0,78214.0,78217.0,192132.0,197685.0,198028.0] || -> . % 76.16/76.39 198039[83:Spt:198038.0,198033.0,198035.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.39 198040[83:Spt:198038.0,198033.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 198044[83:Res:198040.0,61.1] always3(s34) || -> . % 76.16/76.39 198045[83:SSi:198044.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.39 198046[81:Spt:198045.0,197684.0,197685.0] || until2p7(s33)*+ -> . % 76.16/76.39 198047[81:Spt:198045.0,197684.1] || -> node4(s32)*. % 76.16/76.39 198049[81:MRR:822.0,198047.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.39 198052[81:Res:53.1,198049.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.39 198054[82:Spt:198052.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 198056[82:Res:198054.0,61.1] always3(s32) || -> . % 76.16/76.39 198057[82:SSi:198056.0,78209.0,78213.0,192131.0,197683.0,198047.0] || -> . % 76.16/76.39 198058[82:Spt:198057.0,198052.0,198054.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.39 198059[82:Spt:198057.0,198052.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 198063[82:Res:198059.0,61.1] always3(s33) || -> . % 76.16/76.39 198064[82:SSi:198063.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.39 198065[80:Spt:198064.0,197682.0,197683.0] || until2p7(s32)*+ -> . % 76.16/76.39 198066[80:Spt:198064.0,197682.1] || -> node4(s31)*. % 76.16/76.39 198068[80:MRR:825.0,198066.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.39 198071[80:Res:53.1,198068.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.39 198076[81:Spt:198071.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 198078[81:Res:198076.0,61.1] always3(s31) || -> . % 76.16/76.39 198079[81:SSi:198078.0,78205.0,78208.0,192130.0,197681.0,198066.0] || -> . % 76.16/76.39 198080[81:Spt:198079.0,198071.0,198076.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.39 198081[81:Spt:198079.0,198071.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 198085[81:Res:198081.0,61.1] always3(s32) || -> . % 76.16/76.39 198086[81:SSi:198085.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.39 198087[79:Spt:198086.0,197680.0,197681.0] || until2p7(s31)*+ -> . % 76.16/76.39 198088[79:Spt:198086.0,197680.1] || -> node4(s30)*. % 76.16/76.39 198090[79:MRR:828.0,198088.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.39 198093[79:Res:53.1,198090.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.39 198095[80:Spt:198093.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 198097[80:Res:198095.0,61.1] always3(s30) || -> . % 76.16/76.39 198098[80:SSi:198097.0,78200.0,78204.0,192129.0,197679.0,198088.0] || -> . % 76.16/76.39 198099[80:Spt:198098.0,198093.0,198095.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.39 198100[80:Spt:198098.0,198093.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 198104[80:Res:198100.0,61.1] always3(s31) || -> . % 76.16/76.39 198105[80:SSi:198104.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.39 198106[78:Spt:198105.0,197678.0,197679.0] || until2p7(s30)*+ -> . % 76.16/76.39 198107[78:Spt:198105.0,197678.1] || -> node4(s29)*. % 76.16/76.39 198109[78:MRR:831.0,198107.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.39 198112[78:Res:53.1,198109.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.39 198114[78:MRR:198112.0,197668.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 198116[78:Res:198114.0,61.1] always3(s30) || -> . % 76.16/76.39 198117[78:SSi:198116.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.39 198118[76:Spt:198117.0,197584.0,197587.0] || trans(s49,s29)*+ -> . % 76.16/76.39 198119[76:Spt:198117.0,197584.1,197584.2,197584.3,197584.4,197584.5,197584.6,197584.7,197584.8,197584.9,197584.10,197584.11,197584.12,197584.13,197584.14,197584.15,197584.16,197584.17,197584.18,197584.19,197584.20,197584.21,197584.22,197584.23] || -> trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 198121[76:MRR:197586.1,198118.0] xuntil6(s49) || -> trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 198122[77:Spt:198119.0] || -> trans(s49,s28)*. % 76.16/76.39 198123[77:Res:198122.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s28)*. % 76.16/76.39 198125[77:Res:198122.0,60.0] || -> node2(s49,s28)*. % 76.16/76.39 198126[77:SSi:198123.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s28)*. % 76.16/76.39 198127[77:Res:198125.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)*. % 76.16/76.39 198199[77:SoR:198127.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)*. % 76.16/76.39 198201[77:SoR:198199.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s28,c_busy)* xuntil6(s49). % 76.16/76.39 198202[77:SSi:198201.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s28,c_busy)* xuntil6(s49). % 76.16/76.39 198203[78:Spt:198202.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.39 198205[78:Res:198203.0,61.1] always3(s28) || -> . % 76.16/76.39 198206[78:SSi:198205.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.39 198207[78:Spt:198206.0,198202.1,198203.0] || m_main_v_state(s28,c_busy)*+ -> . % 76.16/76.39 198208[78:Spt:198206.0,198202.0,198202.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 198212[78:MRR:198199.2,198207.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 198213[78:Res:53.1,198208.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 198215[78:MRR:198213.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 198216[78:MRR:198126.0,198215.0] || -> until2p7(s28)*. % 76.16/76.39 198217[78:MRR:224.0,198216.0] || -> until2p7(s29)* node4(s28). % 76.16/76.39 198218[79:Spt:198217.0] || -> until2p7(s29)*. % 76.16/76.39 198219[79:MRR:225.0,198218.0] || -> until2p7(s30)* node4(s29). % 76.16/76.39 198220[80:Spt:198219.0] || -> until2p7(s30)*. % 76.16/76.39 198221[80:MRR:226.0,198220.0] || -> until2p7(s31)* node4(s30). % 76.16/76.39 198222[81:Spt:198221.0] || -> until2p7(s31)*. % 76.16/76.39 198223[81:MRR:227.0,198222.0] || -> until2p7(s32)* node4(s31). % 76.16/76.39 198224[82:Spt:198223.0] || -> until2p7(s32)*. % 76.16/76.39 198225[82:MRR:228.0,198224.0] || -> until2p7(s33)* node4(s32). % 76.16/76.39 198226[83:Spt:198225.0] || -> until2p7(s33)*. % 76.16/76.39 198227[83:MRR:229.0,198226.0] || -> until2p7(s34)* node4(s33). % 76.16/76.39 198228[84:Spt:198227.0] || -> until2p7(s34)*. % 76.16/76.39 198229[84:MRR:230.0,198228.0] || -> until2p7(s35)* node4(s34). % 76.16/76.39 198230[85:Spt:198229.0] || -> until2p7(s35)*. % 76.16/76.39 198231[85:MRR:231.0,198230.0] || -> until2p7(s36)* node4(s35). % 76.16/76.39 198232[86:Spt:198231.0] || -> until2p7(s36)*. % 76.16/76.39 198233[86:MRR:232.0,198232.0] || -> until2p7(s37)* node4(s36). % 76.16/76.39 198234[87:Spt:198233.0] || -> until2p7(s37)*. % 76.16/76.39 198235[87:MRR:235.0,198234.0] || -> until2p7(s38)* node4(s37). % 76.16/76.39 198236[88:Spt:198235.0] || -> until2p7(s38)*. % 76.16/76.39 198237[88:MRR:236.0,198236.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 198238[89:Spt:198237.0] || -> until2p7(s39)*. % 76.16/76.39 198239[89:MRR:237.0,198238.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 198240[90:Spt:198239.0] || -> until2p7(s40)*. % 76.16/76.39 198241[90:MRR:238.0,198240.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 198242[91:Spt:198241.0] || -> until2p7(s41)*. % 76.16/76.39 198243[91:MRR:239.0,198242.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 198244[92:Spt:198243.0] || -> until2p7(s42)*. % 76.16/76.39 198245[92:MRR:240.0,198244.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 198246[93:Spt:198245.0] || -> until2p7(s43)*. % 76.16/76.39 198247[93:MRR:241.0,198246.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 198248[94:Spt:198247.0] || -> until2p7(s44)*. % 76.16/76.39 198249[94:MRR:539.0,198248.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 198250[95:Spt:198249.0] || -> until2p7(s45)*. % 76.16/76.39 198251[95:MRR:544.0,198250.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 198252[96:Spt:198251.0] || -> until2p7(s46)*. % 76.16/76.39 198253[96:MRR:549.0,198252.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 198254[97:Spt:198253.0] || -> until2p7(s47)*. % 76.16/76.39 198255[97:MRR:554.0,198254.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 198256[98:Spt:198255.0] || -> until2p7(s48)*. % 76.16/76.39 198257[98:MRR:559.0,198256.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 198258[99:Spt:198257.0] || -> until2p7(s49)*. % 76.16/76.39 198259[99:MRR:194.0,198258.0] || -> node4(s49)*. % 76.16/76.39 198260[99:MRR:198212.0,198259.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 198264[99:Res:53.1,198260.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 198266[99:MRR:198264.0,78381.0] || -> . % 76.16/76.39 198267[99:Spt:198266.0,198257.0,198258.0] || until2p7(s49)*+ -> . % 76.16/76.39 198268[99:Spt:198266.0,198257.1] || -> node4(s48)*. % 76.16/76.39 198269[99:MRR:78384.0,198268.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 198272[99:Res:53.1,198269.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 198275[99:Res:198272.0,61.1] always3(s48) || -> . % 76.16/76.39 198276[99:SSi:198275.0,78281.0,78387.0,192147.0,198256.0,198268.0] || -> . % 76.16/76.39 198277[98:Spt:198276.0,198255.0,198256.0] || until2p7(s48)*+ -> . % 76.16/76.39 198278[98:Spt:198276.0,198255.1] || -> node4(s47)*. % 76.16/76.39 198280[98:MRR:777.0,198278.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 198292[98:Res:53.1,198280.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 198294[99:Spt:198292.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 198296[99:Res:198294.0,61.1] always3(s47) || -> . % 76.16/76.39 198297[99:SSi:198296.0,78277.0,78280.0,192146.0,198254.0,198278.0] || -> . % 76.16/76.39 198298[99:Spt:198297.0,198292.0,198294.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 198299[99:Spt:198297.0,198292.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 198303[99:Res:198299.0,61.1] always3(s48) || -> . % 76.16/76.39 198304[99:SSi:198303.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 198305[97:Spt:198304.0,198253.0,198254.0] || until2p7(s47)*+ -> . % 76.16/76.39 198306[97:Spt:198304.0,198253.1] || -> node4(s46)*. % 76.16/76.39 198308[97:MRR:780.0,198306.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 198315[97:Res:53.1,198308.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 198320[98:Spt:198315.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 198322[98:Res:198320.0,61.1] always3(s46) || -> . % 76.16/76.39 198323[98:SSi:198322.0,78272.0,78276.0,192145.0,198252.0,198306.0] || -> . % 76.16/76.39 198324[98:Spt:198323.0,198315.0,198320.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 198325[98:Spt:198323.0,198315.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 198329[98:Res:198325.0,61.1] always3(s47) || -> . % 76.16/76.39 198330[98:SSi:198329.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 198331[96:Spt:198330.0,198251.0,198252.0] || until2p7(s46)*+ -> . % 76.16/76.39 198332[96:Spt:198330.0,198251.1] || -> node4(s45)*. % 76.16/76.39 198334[96:MRR:783.0,198332.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 198337[96:Res:53.1,198334.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 198339[97:Spt:198337.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 198341[97:Res:198339.0,61.1] always3(s45) || -> . % 76.16/76.39 198342[97:SSi:198341.0,78268.0,78271.0,192144.0,198250.0,198332.0] || -> . % 76.16/76.39 198343[97:Spt:198342.0,198337.0,198339.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 198344[97:Spt:198342.0,198337.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 198348[97:Res:198344.0,61.1] always3(s46) || -> . % 76.16/76.39 198349[97:SSi:198348.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 198350[95:Spt:198349.0,198249.0,198250.0] || until2p7(s45)*+ -> . % 76.16/76.39 198351[95:Spt:198349.0,198249.1] || -> node4(s44)*. % 76.16/76.39 198353[95:MRR:786.0,198351.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 198356[95:Res:53.1,198353.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 198358[96:Spt:198356.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 198360[96:Res:198358.0,61.1] always3(s44) || -> . % 76.16/76.39 198361[96:SSi:198360.0,78263.0,78267.0,192143.0,198248.0,198351.0] || -> . % 76.16/76.39 198362[96:Spt:198361.0,198356.0,198358.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 198363[96:Spt:198361.0,198356.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 198367[96:Res:198363.0,61.1] always3(s45) || -> . % 76.16/76.39 198368[96:SSi:198367.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 198369[94:Spt:198368.0,198247.0,198248.0] || until2p7(s44)*+ -> . % 76.16/76.39 198370[94:Spt:198368.0,198247.1] || -> node4(s43)*. % 76.16/76.39 198372[94:MRR:789.0,198370.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 198375[94:Res:53.1,198372.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 198377[95:Spt:198375.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 198379[95:Res:198377.0,61.1] always3(s43) || -> . % 76.16/76.39 198380[95:SSi:198379.0,78259.0,78262.0,192142.0,198246.0,198370.0] || -> . % 76.16/76.39 198381[95:Spt:198380.0,198375.0,198377.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 198382[95:Spt:198380.0,198375.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 198386[95:Res:198382.0,61.1] always3(s44) || -> . % 76.16/76.39 198387[95:SSi:198386.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 198388[93:Spt:198387.0,198245.0,198246.0] || until2p7(s43)*+ -> . % 76.16/76.39 198389[93:Spt:198387.0,198245.1] || -> node4(s42)*. % 76.16/76.39 198391[93:MRR:792.0,198389.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 198394[93:Res:53.1,198391.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 198399[94:Spt:198394.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 198401[94:Res:198399.0,61.1] always3(s42) || -> . % 76.16/76.39 198402[94:SSi:198401.0,78254.0,78258.0,192141.0,198244.0,198389.0] || -> . % 76.16/76.39 198403[94:Spt:198402.0,198394.0,198399.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 198404[94:Spt:198402.0,198394.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 198408[94:Res:198404.0,61.1] always3(s43) || -> . % 76.16/76.39 198409[94:SSi:198408.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 198410[92:Spt:198409.0,198243.0,198244.0] || until2p7(s42)*+ -> . % 76.16/76.39 198411[92:Spt:198409.0,198243.1] || -> node4(s41)*. % 76.16/76.39 198413[92:MRR:795.0,198411.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 198416[92:Res:53.1,198413.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 198418[93:Spt:198416.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 198420[93:Res:198418.0,61.1] always3(s41) || -> . % 76.16/76.39 198421[93:SSi:198420.0,78250.0,78253.0,192140.0,198242.0,198411.0] || -> . % 76.16/76.39 198422[93:Spt:198421.0,198416.0,198418.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 198423[93:Spt:198421.0,198416.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 198427[93:Res:198423.0,61.1] always3(s42) || -> . % 76.16/76.39 198428[93:SSi:198427.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 198429[91:Spt:198428.0,198241.0,198242.0] || until2p7(s41)*+ -> . % 76.16/76.39 198430[91:Spt:198428.0,198241.1] || -> node4(s40)*. % 76.16/76.39 198432[91:MRR:798.0,198430.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 198435[91:Res:53.1,198432.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 198437[92:Spt:198435.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 198439[92:Res:198437.0,61.1] always3(s40) || -> . % 76.16/76.39 198440[92:SSi:198439.0,78245.0,78249.0,192139.0,198240.0,198430.0] || -> . % 76.16/76.39 198441[92:Spt:198440.0,198435.0,198437.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 198442[92:Spt:198440.0,198435.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 198446[92:Res:198442.0,61.1] always3(s41) || -> . % 76.16/76.39 198447[92:SSi:198446.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 198448[90:Spt:198447.0,198239.0,198240.0] || until2p7(s40)*+ -> . % 76.16/76.39 198449[90:Spt:198447.0,198239.1] || -> node4(s39)*. % 76.16/76.39 198451[90:MRR:801.0,198449.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 198454[90:Res:53.1,198451.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 198456[91:Spt:198454.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 198458[91:Res:198456.0,61.1] always3(s39) || -> . % 76.16/76.39 198459[91:SSi:198458.0,78241.0,78244.0,192138.0,198238.0,198449.0] || -> . % 76.16/76.39 198460[91:Spt:198459.0,198454.0,198456.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 198461[91:Spt:198459.0,198454.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 198465[91:Res:198461.0,61.1] always3(s40) || -> . % 76.16/76.39 198466[91:SSi:198465.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 198467[89:Spt:198466.0,198237.0,198238.0] || until2p7(s39)*+ -> . % 76.16/76.39 198468[89:Spt:198466.0,198237.1] || -> node4(s38)*. % 76.16/76.39 198470[89:MRR:804.0,198468.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 198473[89:Res:53.1,198470.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 198478[90:Spt:198473.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 198480[90:Res:198478.0,61.1] always3(s38) || -> . % 76.16/76.39 198481[90:SSi:198480.0,78236.0,78240.0,192137.0,198236.0,198468.0] || -> . % 76.16/76.39 198482[90:Spt:198481.0,198473.0,198478.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 198483[90:Spt:198481.0,198473.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 198487[90:Res:198483.0,61.1] always3(s39) || -> . % 76.16/76.39 198488[90:SSi:198487.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 198489[88:Spt:198488.0,198235.0,198236.0] || until2p7(s38)*+ -> . % 76.16/76.39 198490[88:Spt:198488.0,198235.1] || -> node4(s37)*. % 76.16/76.39 198492[88:MRR:807.0,198490.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 198495[88:Res:53.1,198492.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 198497[89:Spt:198495.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 198499[89:Res:198497.0,61.1] always3(s37) || -> . % 76.16/76.39 198500[89:SSi:198499.0,78232.0,78235.0,192136.0,198234.0,198490.0] || -> . % 76.16/76.39 198501[89:Spt:198500.0,198495.0,198497.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.39 198502[89:Spt:198500.0,198495.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 198506[89:Res:198502.0,61.1] always3(s38) || -> . % 76.16/76.39 198507[89:SSi:198506.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.39 198508[87:Spt:198507.0,198233.0,198234.0] || until2p7(s37)*+ -> . % 76.16/76.39 198509[87:Spt:198507.0,198233.1] || -> node4(s36)*. % 76.16/76.39 198511[87:MRR:810.0,198509.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.39 198514[87:Res:53.1,198511.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.39 198516[88:Spt:198514.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 198518[88:Res:198516.0,61.1] always3(s36) || -> . % 76.16/76.39 198519[88:SSi:198518.0,78227.0,78231.0,192135.0,198232.0,198509.0] || -> . % 76.16/76.39 198520[88:Spt:198519.0,198514.0,198516.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.39 198521[88:Spt:198519.0,198514.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 198525[88:Res:198521.0,61.1] always3(s37) || -> . % 76.16/76.39 198526[88:SSi:198525.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.39 198527[86:Spt:198526.0,198231.0,198232.0] || until2p7(s36)*+ -> . % 76.16/76.39 198528[86:Spt:198526.0,198231.1] || -> node4(s35)*. % 76.16/76.39 198530[86:MRR:813.0,198528.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.39 198533[86:Res:53.1,198530.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.39 198535[87:Spt:198533.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 198537[87:Res:198535.0,61.1] always3(s35) || -> . % 76.16/76.39 198538[87:SSi:198537.0,78223.0,78226.0,192134.0,198230.0,198528.0] || -> . % 76.16/76.39 198539[87:Spt:198538.0,198533.0,198535.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.39 198540[87:Spt:198538.0,198533.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 198544[87:Res:198540.0,61.1] always3(s36) || -> . % 76.16/76.39 198545[87:SSi:198544.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.39 198546[85:Spt:198545.0,198229.0,198230.0] || until2p7(s35)*+ -> . % 76.16/76.39 198547[85:Spt:198545.0,198229.1] || -> node4(s34)*. % 76.16/76.39 198549[85:MRR:816.0,198547.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.39 198552[85:Res:53.1,198549.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.39 198557[86:Spt:198552.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 198559[86:Res:198557.0,61.1] always3(s34) || -> . % 76.16/76.39 198560[86:SSi:198559.0,78218.0,78222.0,192133.0,198228.0,198547.0] || -> . % 76.16/76.39 198561[86:Spt:198560.0,198552.0,198557.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.39 198562[86:Spt:198560.0,198552.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 198566[86:Res:198562.0,61.1] always3(s35) || -> . % 76.16/76.39 198567[86:SSi:198566.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.39 198568[84:Spt:198567.0,198227.0,198228.0] || until2p7(s34)*+ -> . % 76.16/76.39 198569[84:Spt:198567.0,198227.1] || -> node4(s33)*. % 76.16/76.39 198571[84:MRR:819.0,198569.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.39 198574[84:Res:53.1,198571.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.39 198576[85:Spt:198574.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 198578[85:Res:198576.0,61.1] always3(s33) || -> . % 76.16/76.39 198579[85:SSi:198578.0,78214.0,78217.0,192132.0,198226.0,198569.0] || -> . % 76.16/76.39 198580[85:Spt:198579.0,198574.0,198576.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.39 198581[85:Spt:198579.0,198574.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 198585[85:Res:198581.0,61.1] always3(s34) || -> . % 76.16/76.39 198586[85:SSi:198585.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.39 198587[83:Spt:198586.0,198225.0,198226.0] || until2p7(s33)*+ -> . % 76.16/76.39 198588[83:Spt:198586.0,198225.1] || -> node4(s32)*. % 76.16/76.39 198590[83:MRR:822.0,198588.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.39 198593[83:Res:53.1,198590.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.39 198595[84:Spt:198593.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 198597[84:Res:198595.0,61.1] always3(s32) || -> . % 76.16/76.39 198598[84:SSi:198597.0,78209.0,78213.0,192131.0,198224.0,198588.0] || -> . % 76.16/76.39 198599[84:Spt:198598.0,198593.0,198595.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.39 198600[84:Spt:198598.0,198593.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 198604[84:Res:198600.0,61.1] always3(s33) || -> . % 76.16/76.39 198605[84:SSi:198604.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.39 198606[82:Spt:198605.0,198223.0,198224.0] || until2p7(s32)*+ -> . % 76.16/76.39 198607[82:Spt:198605.0,198223.1] || -> node4(s31)*. % 76.16/76.39 198609[82:MRR:825.0,198607.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.39 198612[82:Res:53.1,198609.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.39 198614[83:Spt:198612.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 198616[83:Res:198614.0,61.1] always3(s31) || -> . % 76.16/76.39 198617[83:SSi:198616.0,78205.0,78208.0,192130.0,198222.0,198607.0] || -> . % 76.16/76.39 198618[83:Spt:198617.0,198612.0,198614.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.39 198619[83:Spt:198617.0,198612.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 198623[83:Res:198619.0,61.1] always3(s32) || -> . % 76.16/76.39 198624[83:SSi:198623.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.39 198625[81:Spt:198624.0,198221.0,198222.0] || until2p7(s31)*+ -> . % 76.16/76.39 198626[81:Spt:198624.0,198221.1] || -> node4(s30)*. % 76.16/76.39 198628[81:MRR:828.0,198626.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.39 198631[81:Res:53.1,198628.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.39 198636[82:Spt:198631.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 198638[82:Res:198636.0,61.1] always3(s30) || -> . % 76.16/76.39 198639[82:SSi:198638.0,78200.0,78204.0,192129.0,198220.0,198626.0] || -> . % 76.16/76.39 198640[82:Spt:198639.0,198631.0,198636.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.39 198641[82:Spt:198639.0,198631.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 198645[82:Res:198641.0,61.1] always3(s31) || -> . % 76.16/76.39 198646[82:SSi:198645.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.39 198647[80:Spt:198646.0,198219.0,198220.0] || until2p7(s30)*+ -> . % 76.16/76.39 198648[80:Spt:198646.0,198219.1] || -> node4(s29)*. % 76.16/76.39 198650[80:MRR:831.0,198648.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.39 198653[80:Res:53.1,198650.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.39 198655[81:Spt:198653.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.39 198657[81:Res:198655.0,61.1] always3(s29) || -> . % 76.16/76.39 198658[81:SSi:198657.0,78196.0,78199.0,192128.0,198218.0,198648.0] || -> . % 76.16/76.39 198659[81:Spt:198658.0,198653.0,198655.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.39 198660[81:Spt:198658.0,198653.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 198664[81:Res:198660.0,61.1] always3(s30) || -> . % 76.16/76.39 198665[81:SSi:198664.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.39 198666[79:Spt:198665.0,198217.0,198218.0] || until2p7(s29)*+ -> . % 76.16/76.39 198667[79:Spt:198665.0,198217.1] || -> node4(s28)*. % 76.16/76.39 198669[79:MRR:834.0,198667.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.39 198672[79:Res:53.1,198669.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.39 198674[79:MRR:198672.0,198207.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.39 198676[79:Res:198674.0,61.1] always3(s29) || -> . % 76.16/76.39 198677[79:SSi:198676.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.39 198678[77:Spt:198677.0,198119.0,198122.0] || trans(s49,s28)*+ -> . % 76.16/76.39 198679[77:Spt:198677.0,198119.1,198119.2,198119.3,198119.4,198119.5,198119.6,198119.7,198119.8,198119.9,198119.10,198119.11,198119.12,198119.13,198119.14,198119.15,198119.16,198119.17,198119.18,198119.19,198119.20,198119.21,198119.22] || -> trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 198681[77:MRR:198121.1,198678.0] xuntil6(s49) || -> trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 198682[78:Spt:198679.0] || -> trans(s49,s27)*. % 76.16/76.39 198683[78:Res:198682.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s27)*. % 76.16/76.39 198685[78:Res:198682.0,60.0] || -> node2(s49,s27)*. % 76.16/76.39 198686[78:SSi:198683.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s27)*. % 76.16/76.39 198687[78:Res:198685.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)*. % 76.16/76.39 198763[78:SoR:198687.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)*. % 76.16/76.39 198765[78:SoR:198763.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s27,c_busy)* xuntil6(s49). % 76.16/76.39 198766[78:SSi:198765.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s27,c_busy)* xuntil6(s49). % 76.16/76.39 198767[79:Spt:198766.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.39 198769[79:Res:198767.0,61.1] always3(s27) || -> . % 76.16/76.39 198770[79:SSi:198769.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.39 198771[79:Spt:198770.0,198766.1,198767.0] || m_main_v_state(s27,c_busy)*+ -> . % 76.16/76.39 198772[79:Spt:198770.0,198766.0,198766.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 198776[79:MRR:198763.2,198771.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 198777[79:Res:53.1,198772.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 198779[79:MRR:198777.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 198780[79:MRR:198686.0,198779.0] || -> until2p7(s27)*. % 76.16/76.39 198781[79:MRR:223.0,198780.0] || -> until2p7(s28)* node4(s27). % 76.16/76.39 198782[80:Spt:198781.0] || -> until2p7(s28)*. % 76.16/76.39 198783[80:MRR:224.0,198782.0] || -> until2p7(s29)* node4(s28). % 76.16/76.39 198784[81:Spt:198783.0] || -> until2p7(s29)*. % 76.16/76.39 198785[81:MRR:225.0,198784.0] || -> until2p7(s30)* node4(s29). % 76.16/76.39 198786[82:Spt:198785.0] || -> until2p7(s30)*. % 76.16/76.39 198787[82:MRR:226.0,198786.0] || -> until2p7(s31)* node4(s30). % 76.16/76.39 198788[83:Spt:198787.0] || -> until2p7(s31)*. % 76.16/76.39 198789[83:MRR:227.0,198788.0] || -> until2p7(s32)* node4(s31). % 76.16/76.39 198790[84:Spt:198789.0] || -> until2p7(s32)*. % 76.16/76.39 198791[84:MRR:228.0,198790.0] || -> until2p7(s33)* node4(s32). % 76.16/76.39 198792[85:Spt:198791.0] || -> until2p7(s33)*. % 76.16/76.39 198793[85:MRR:229.0,198792.0] || -> until2p7(s34)* node4(s33). % 76.16/76.39 198794[86:Spt:198793.0] || -> until2p7(s34)*. % 76.16/76.39 198795[86:MRR:230.0,198794.0] || -> until2p7(s35)* node4(s34). % 76.16/76.39 198796[87:Spt:198795.0] || -> until2p7(s35)*. % 76.16/76.39 198797[87:MRR:231.0,198796.0] || -> until2p7(s36)* node4(s35). % 76.16/76.39 198798[88:Spt:198797.0] || -> until2p7(s36)*. % 76.16/76.39 198799[88:MRR:232.0,198798.0] || -> until2p7(s37)* node4(s36). % 76.16/76.39 198800[89:Spt:198799.0] || -> until2p7(s37)*. % 76.16/76.39 198801[89:MRR:235.0,198800.0] || -> until2p7(s38)* node4(s37). % 76.16/76.39 198802[90:Spt:198801.0] || -> until2p7(s38)*. % 76.16/76.39 198803[90:MRR:236.0,198802.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 198804[91:Spt:198803.0] || -> until2p7(s39)*. % 76.16/76.39 198805[91:MRR:237.0,198804.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 198806[92:Spt:198805.0] || -> until2p7(s40)*. % 76.16/76.39 198807[92:MRR:238.0,198806.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 198808[93:Spt:198807.0] || -> until2p7(s41)*. % 76.16/76.39 198809[93:MRR:239.0,198808.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 198810[94:Spt:198809.0] || -> until2p7(s42)*. % 76.16/76.39 198811[94:MRR:240.0,198810.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 198812[95:Spt:198811.0] || -> until2p7(s43)*. % 76.16/76.39 198813[95:MRR:241.0,198812.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 198814[96:Spt:198813.0] || -> until2p7(s44)*. % 76.16/76.39 198815[96:MRR:539.0,198814.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 198816[97:Spt:198815.0] || -> until2p7(s45)*. % 76.16/76.39 198817[97:MRR:544.0,198816.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 198818[98:Spt:198817.0] || -> until2p7(s46)*. % 76.16/76.39 198819[98:MRR:549.0,198818.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 198820[99:Spt:198819.0] || -> until2p7(s47)*. % 76.16/76.39 198821[99:MRR:554.0,198820.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 198822[100:Spt:198821.0] || -> until2p7(s48)*. % 76.16/76.39 198823[100:MRR:559.0,198822.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 198824[101:Spt:198823.0] || -> until2p7(s49)*. % 76.16/76.39 198825[101:MRR:194.0,198824.0] || -> node4(s49)*. % 76.16/76.39 198826[101:MRR:198776.0,198825.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 198827[101:Res:53.1,198826.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 198829[101:MRR:198827.0,78381.0] || -> . % 76.16/76.39 198830[101:Spt:198829.0,198823.0,198824.0] || until2p7(s49)*+ -> . % 76.16/76.39 198831[101:Spt:198829.0,198823.1] || -> node4(s48)*. % 76.16/76.39 198832[101:MRR:78384.0,198831.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 198835[101:Res:53.1,198832.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 198838[101:Res:198835.0,61.1] always3(s48) || -> . % 76.16/76.39 198839[101:SSi:198838.0,78281.0,78387.0,192147.0,198822.0,198831.0] || -> . % 76.16/76.39 198840[100:Spt:198839.0,198821.0,198822.0] || until2p7(s48)*+ -> . % 76.16/76.39 198841[100:Spt:198839.0,198821.1] || -> node4(s47)*. % 76.16/76.39 198843[100:MRR:777.0,198841.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 198858[100:Res:53.1,198843.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 198863[101:Spt:198858.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 198865[101:Res:198863.0,61.1] always3(s47) || -> . % 76.16/76.39 198866[101:SSi:198865.0,78277.0,78280.0,192146.0,198820.0,198841.0] || -> . % 76.16/76.39 198867[101:Spt:198866.0,198858.0,198863.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 198868[101:Spt:198866.0,198858.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 198872[101:Res:198868.0,61.1] always3(s48) || -> . % 76.16/76.39 198873[101:SSi:198872.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 198874[99:Spt:198873.0,198819.0,198820.0] || until2p7(s47)*+ -> . % 76.16/76.39 198875[99:Spt:198873.0,198819.1] || -> node4(s46)*. % 76.16/76.39 198877[99:MRR:780.0,198875.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 198884[99:Res:53.1,198877.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 198886[100:Spt:198884.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 198888[100:Res:198886.0,61.1] always3(s46) || -> . % 76.16/76.39 198889[100:SSi:198888.0,78272.0,78276.0,192145.0,198818.0,198875.0] || -> . % 76.16/76.39 198890[100:Spt:198889.0,198884.0,198886.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 198891[100:Spt:198889.0,198884.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 198895[100:Res:198891.0,61.1] always3(s47) || -> . % 76.16/76.39 198896[100:SSi:198895.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 198897[98:Spt:198896.0,198817.0,198818.0] || until2p7(s46)*+ -> . % 76.16/76.39 198898[98:Spt:198896.0,198817.1] || -> node4(s45)*. % 76.16/76.39 198900[98:MRR:783.0,198898.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 198903[98:Res:53.1,198900.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 198908[99:Spt:198903.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 198910[99:Res:198908.0,61.1] always3(s45) || -> . % 76.16/76.39 198911[99:SSi:198910.0,78268.0,78271.0,192144.0,198816.0,198898.0] || -> . % 76.16/76.39 198912[99:Spt:198911.0,198903.0,198908.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 198913[99:Spt:198911.0,198903.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 198917[99:Res:198913.0,61.1] always3(s46) || -> . % 76.16/76.39 198918[99:SSi:198917.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 198919[97:Spt:198918.0,198815.0,198816.0] || until2p7(s45)*+ -> . % 76.16/76.39 198920[97:Spt:198918.0,198815.1] || -> node4(s44)*. % 76.16/76.39 198922[97:MRR:786.0,198920.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 198925[97:Res:53.1,198922.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 198927[98:Spt:198925.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 198929[98:Res:198927.0,61.1] always3(s44) || -> . % 76.16/76.39 198930[98:SSi:198929.0,78263.0,78267.0,192143.0,198814.0,198920.0] || -> . % 76.16/76.39 198931[98:Spt:198930.0,198925.0,198927.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 198932[98:Spt:198930.0,198925.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 198936[98:Res:198932.0,61.1] always3(s45) || -> . % 76.16/76.39 198937[98:SSi:198936.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 198938[96:Spt:198937.0,198813.0,198814.0] || until2p7(s44)*+ -> . % 76.16/76.39 198939[96:Spt:198937.0,198813.1] || -> node4(s43)*. % 76.16/76.39 198941[96:MRR:789.0,198939.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 198944[96:Res:53.1,198941.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 198946[97:Spt:198944.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 198948[97:Res:198946.0,61.1] always3(s43) || -> . % 76.16/76.39 198949[97:SSi:198948.0,78259.0,78262.0,192142.0,198812.0,198939.0] || -> . % 76.16/76.39 198950[97:Spt:198949.0,198944.0,198946.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 198951[97:Spt:198949.0,198944.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 198955[97:Res:198951.0,61.1] always3(s44) || -> . % 76.16/76.39 198956[97:SSi:198955.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 198957[95:Spt:198956.0,198811.0,198812.0] || until2p7(s43)*+ -> . % 76.16/76.39 198958[95:Spt:198956.0,198811.1] || -> node4(s42)*. % 76.16/76.39 198960[95:MRR:792.0,198958.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 198963[95:Res:53.1,198960.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 198965[96:Spt:198963.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 198967[96:Res:198965.0,61.1] always3(s42) || -> . % 76.16/76.39 198968[96:SSi:198967.0,78254.0,78258.0,192141.0,198810.0,198958.0] || -> . % 76.16/76.39 198969[96:Spt:198968.0,198963.0,198965.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 198970[96:Spt:198968.0,198963.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 198974[96:Res:198970.0,61.1] always3(s43) || -> . % 76.16/76.39 198975[96:SSi:198974.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 198976[94:Spt:198975.0,198809.0,198810.0] || until2p7(s42)*+ -> . % 76.16/76.39 198977[94:Spt:198975.0,198809.1] || -> node4(s41)*. % 76.16/76.39 198979[94:MRR:795.0,198977.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 198982[94:Res:53.1,198979.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 198987[95:Spt:198982.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 198989[95:Res:198987.0,61.1] always3(s41) || -> . % 76.16/76.39 198990[95:SSi:198989.0,78250.0,78253.0,192140.0,198808.0,198977.0] || -> . % 76.16/76.39 198991[95:Spt:198990.0,198982.0,198987.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 198992[95:Spt:198990.0,198982.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 198996[95:Res:198992.0,61.1] always3(s42) || -> . % 76.16/76.39 198997[95:SSi:198996.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 198998[93:Spt:198997.0,198807.0,198808.0] || until2p7(s41)*+ -> . % 76.16/76.39 198999[93:Spt:198997.0,198807.1] || -> node4(s40)*. % 76.16/76.39 199001[93:MRR:798.0,198999.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 199004[93:Res:53.1,199001.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 199006[94:Spt:199004.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 199008[94:Res:199006.0,61.1] always3(s40) || -> . % 76.16/76.39 199009[94:SSi:199008.0,78245.0,78249.0,192139.0,198806.0,198999.0] || -> . % 76.16/76.39 199010[94:Spt:199009.0,199004.0,199006.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 199011[94:Spt:199009.0,199004.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 199015[94:Res:199011.0,61.1] always3(s41) || -> . % 76.16/76.39 199016[94:SSi:199015.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 199017[92:Spt:199016.0,198805.0,198806.0] || until2p7(s40)*+ -> . % 76.16/76.39 199018[92:Spt:199016.0,198805.1] || -> node4(s39)*. % 76.16/76.39 199020[92:MRR:801.0,199018.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 199023[92:Res:53.1,199020.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 199025[93:Spt:199023.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 199027[93:Res:199025.0,61.1] always3(s39) || -> . % 76.16/76.39 199028[93:SSi:199027.0,78241.0,78244.0,192138.0,198804.0,199018.0] || -> . % 76.16/76.39 199029[93:Spt:199028.0,199023.0,199025.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 199030[93:Spt:199028.0,199023.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 199034[93:Res:199030.0,61.1] always3(s40) || -> . % 76.16/76.39 199035[93:SSi:199034.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 199036[91:Spt:199035.0,198803.0,198804.0] || until2p7(s39)*+ -> . % 76.16/76.39 199037[91:Spt:199035.0,198803.1] || -> node4(s38)*. % 76.16/76.39 199039[91:MRR:804.0,199037.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 199042[91:Res:53.1,199039.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 199044[92:Spt:199042.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 199046[92:Res:199044.0,61.1] always3(s38) || -> . % 76.16/76.39 199047[92:SSi:199046.0,78236.0,78240.0,192137.0,198802.0,199037.0] || -> . % 76.16/76.39 199048[92:Spt:199047.0,199042.0,199044.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 199049[92:Spt:199047.0,199042.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 199053[92:Res:199049.0,61.1] always3(s39) || -> . % 76.16/76.39 199054[92:SSi:199053.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 199055[90:Spt:199054.0,198801.0,198802.0] || until2p7(s38)*+ -> . % 76.16/76.39 199056[90:Spt:199054.0,198801.1] || -> node4(s37)*. % 76.16/76.39 199058[90:MRR:807.0,199056.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 199061[90:Res:53.1,199058.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 199066[91:Spt:199061.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 199068[91:Res:199066.0,61.1] always3(s37) || -> . % 76.16/76.39 199069[91:SSi:199068.0,78232.0,78235.0,192136.0,198800.0,199056.0] || -> . % 76.16/76.39 199070[91:Spt:199069.0,199061.0,199066.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.39 199071[91:Spt:199069.0,199061.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 199075[91:Res:199071.0,61.1] always3(s38) || -> . % 76.16/76.39 199076[91:SSi:199075.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.39 199077[89:Spt:199076.0,198799.0,198800.0] || until2p7(s37)*+ -> . % 76.16/76.39 199078[89:Spt:199076.0,198799.1] || -> node4(s36)*. % 76.16/76.39 199080[89:MRR:810.0,199078.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.39 199083[89:Res:53.1,199080.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.39 199085[90:Spt:199083.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 199087[90:Res:199085.0,61.1] always3(s36) || -> . % 76.16/76.39 199088[90:SSi:199087.0,78227.0,78231.0,192135.0,198798.0,199078.0] || -> . % 76.16/76.39 199089[90:Spt:199088.0,199083.0,199085.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.39 199090[90:Spt:199088.0,199083.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 199094[90:Res:199090.0,61.1] always3(s37) || -> . % 76.16/76.39 199095[90:SSi:199094.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.39 199096[88:Spt:199095.0,198797.0,198798.0] || until2p7(s36)*+ -> . % 76.16/76.39 199097[88:Spt:199095.0,198797.1] || -> node4(s35)*. % 76.16/76.39 199099[88:MRR:813.0,199097.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.39 199102[88:Res:53.1,199099.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.39 199104[89:Spt:199102.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 199106[89:Res:199104.0,61.1] always3(s35) || -> . % 76.16/76.39 199107[89:SSi:199106.0,78223.0,78226.0,192134.0,198796.0,199097.0] || -> . % 76.16/76.39 199108[89:Spt:199107.0,199102.0,199104.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.39 199109[89:Spt:199107.0,199102.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 199113[89:Res:199109.0,61.1] always3(s36) || -> . % 76.16/76.39 199114[89:SSi:199113.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.39 199115[87:Spt:199114.0,198795.0,198796.0] || until2p7(s35)*+ -> . % 76.16/76.39 199116[87:Spt:199114.0,198795.1] || -> node4(s34)*. % 76.16/76.39 199118[87:MRR:816.0,199116.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.39 199121[87:Res:53.1,199118.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.39 199123[88:Spt:199121.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 199125[88:Res:199123.0,61.1] always3(s34) || -> . % 76.16/76.39 199126[88:SSi:199125.0,78218.0,78222.0,192133.0,198794.0,199116.0] || -> . % 76.16/76.39 199127[88:Spt:199126.0,199121.0,199123.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.39 199128[88:Spt:199126.0,199121.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 199132[88:Res:199128.0,61.1] always3(s35) || -> . % 76.16/76.39 199133[88:SSi:199132.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.39 199134[86:Spt:199133.0,198793.0,198794.0] || until2p7(s34)*+ -> . % 76.16/76.39 199135[86:Spt:199133.0,198793.1] || -> node4(s33)*. % 76.16/76.39 199137[86:MRR:819.0,199135.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.39 199140[86:Res:53.1,199137.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.39 199145[87:Spt:199140.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 199147[87:Res:199145.0,61.1] always3(s33) || -> . % 76.16/76.39 199148[87:SSi:199147.0,78214.0,78217.0,192132.0,198792.0,199135.0] || -> . % 76.16/76.39 199149[87:Spt:199148.0,199140.0,199145.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.39 199150[87:Spt:199148.0,199140.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 199154[87:Res:199150.0,61.1] always3(s34) || -> . % 76.16/76.39 199155[87:SSi:199154.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.39 199156[85:Spt:199155.0,198791.0,198792.0] || until2p7(s33)*+ -> . % 76.16/76.39 199157[85:Spt:199155.0,198791.1] || -> node4(s32)*. % 76.16/76.39 199159[85:MRR:822.0,199157.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.39 199162[85:Res:53.1,199159.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.39 199164[86:Spt:199162.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 199166[86:Res:199164.0,61.1] always3(s32) || -> . % 76.16/76.39 199167[86:SSi:199166.0,78209.0,78213.0,192131.0,198790.0,199157.0] || -> . % 76.16/76.39 199168[86:Spt:199167.0,199162.0,199164.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.39 199169[86:Spt:199167.0,199162.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 199173[86:Res:199169.0,61.1] always3(s33) || -> . % 76.16/76.39 199174[86:SSi:199173.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.39 199175[84:Spt:199174.0,198789.0,198790.0] || until2p7(s32)*+ -> . % 76.16/76.39 199176[84:Spt:199174.0,198789.1] || -> node4(s31)*. % 76.16/76.39 199178[84:MRR:825.0,199176.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.39 199181[84:Res:53.1,199178.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.39 199183[85:Spt:199181.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 199185[85:Res:199183.0,61.1] always3(s31) || -> . % 76.16/76.39 199186[85:SSi:199185.0,78205.0,78208.0,192130.0,198788.0,199176.0] || -> . % 76.16/76.39 199187[85:Spt:199186.0,199181.0,199183.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.39 199188[85:Spt:199186.0,199181.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 199192[85:Res:199188.0,61.1] always3(s32) || -> . % 76.16/76.39 199193[85:SSi:199192.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.39 199194[83:Spt:199193.0,198787.0,198788.0] || until2p7(s31)*+ -> . % 76.16/76.39 199195[83:Spt:199193.0,198787.1] || -> node4(s30)*. % 76.16/76.39 199197[83:MRR:828.0,199195.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.39 199200[83:Res:53.1,199197.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.39 199202[84:Spt:199200.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 199204[84:Res:199202.0,61.1] always3(s30) || -> . % 76.16/76.39 199205[84:SSi:199204.0,78200.0,78204.0,192129.0,198786.0,199195.0] || -> . % 76.16/76.39 199206[84:Spt:199205.0,199200.0,199202.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.39 199207[84:Spt:199205.0,199200.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 199211[84:Res:199207.0,61.1] always3(s31) || -> . % 76.16/76.39 199212[84:SSi:199211.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.39 199213[82:Spt:199212.0,198785.0,198786.0] || until2p7(s30)*+ -> . % 76.16/76.39 199214[82:Spt:199212.0,198785.1] || -> node4(s29)*. % 76.16/76.39 199216[82:MRR:831.0,199214.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.39 199219[82:Res:53.1,199216.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.39 199224[83:Spt:199219.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.39 199226[83:Res:199224.0,61.1] always3(s29) || -> . % 76.16/76.39 199227[83:SSi:199226.0,78196.0,78199.0,192128.0,198784.0,199214.0] || -> . % 76.16/76.39 199228[83:Spt:199227.0,199219.0,199224.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.39 199229[83:Spt:199227.0,199219.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 199233[83:Res:199229.0,61.1] always3(s30) || -> . % 76.16/76.39 199234[83:SSi:199233.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.39 199235[81:Spt:199234.0,198783.0,198784.0] || until2p7(s29)*+ -> . % 76.16/76.39 199236[81:Spt:199234.0,198783.1] || -> node4(s28)*. % 76.16/76.39 199238[81:MRR:834.0,199236.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.39 199241[81:Res:53.1,199238.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.39 199243[82:Spt:199241.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.39 199245[82:Res:199243.0,61.1] always3(s28) || -> . % 76.16/76.39 199246[82:SSi:199245.0,78191.0,78195.0,192127.0,198782.0,199236.0] || -> . % 76.16/76.39 199247[82:Spt:199246.0,199241.0,199243.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.39 199248[82:Spt:199246.0,199241.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.39 199252[82:Res:199248.0,61.1] always3(s29) || -> . % 76.16/76.39 199253[82:SSi:199252.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.39 199254[80:Spt:199253.0,198781.0,198782.0] || until2p7(s28)*+ -> . % 76.16/76.39 199255[80:Spt:199253.0,198781.1] || -> node4(s27)*. % 76.16/76.39 199257[80:MRR:837.0,199255.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.39 199260[80:Res:53.1,199257.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.39 199262[80:MRR:199260.0,198771.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.39 199264[80:Res:199262.0,61.1] always3(s28) || -> . % 76.16/76.39 199265[80:SSi:199264.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.39 199266[78:Spt:199265.0,198679.0,198682.0] || trans(s49,s27)*+ -> . % 76.16/76.39 199267[78:Spt:199265.0,198679.1,198679.2,198679.3,198679.4,198679.5,198679.6,198679.7,198679.8,198679.9,198679.10,198679.11,198679.12,198679.13,198679.14,198679.15,198679.16,198679.17,198679.18,198679.19,198679.20,198679.21] || -> trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.39 199269[78:MRR:198681.1,199266.0] xuntil6(s49) || -> trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.39 199270[79:Spt:199267.0] || -> trans(s49,s26)*. % 76.16/76.39 199271[79:Res:199270.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s26)*. % 76.16/76.39 199273[79:Res:199270.0,60.0] || -> node2(s49,s26)*. % 76.16/76.39 199274[79:SSi:199271.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s26)*. % 76.16/76.39 199275[79:Res:199273.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)*. % 76.16/76.39 199352[79:SoR:199275.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)*. % 76.16/76.39 199354[79:SoR:199352.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s26,c_busy)* xuntil6(s49). % 76.16/76.39 199355[79:SSi:199354.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s26,c_busy)* xuntil6(s49). % 76.16/76.39 199356[80:Spt:199355.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.39 199358[80:Res:199356.0,61.1] always3(s26) || -> . % 76.16/76.39 199359[80:SSi:199358.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.39 199360[80:Spt:199359.0,199355.1,199356.0] || m_main_v_state(s26,c_busy)*+ -> . % 76.16/76.39 199361[80:Spt:199359.0,199355.0,199355.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.39 199365[80:MRR:199352.2,199360.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.39 199366[80:Res:53.1,199361.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.39 199368[80:MRR:199366.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.39 199369[80:MRR:199274.0,199368.0] || -> until2p7(s26)*. % 76.16/76.39 199370[80:MRR:222.0,199369.0] || -> until2p7(s27)* node4(s26). % 76.16/76.39 199371[81:Spt:199370.0] || -> until2p7(s27)*. % 76.16/76.39 199372[81:MRR:223.0,199371.0] || -> until2p7(s28)* node4(s27). % 76.16/76.39 199373[82:Spt:199372.0] || -> until2p7(s28)*. % 76.16/76.39 199374[82:MRR:224.0,199373.0] || -> until2p7(s29)* node4(s28). % 76.16/76.39 199375[83:Spt:199374.0] || -> until2p7(s29)*. % 76.16/76.39 199376[83:MRR:225.0,199375.0] || -> until2p7(s30)* node4(s29). % 76.16/76.39 199377[84:Spt:199376.0] || -> until2p7(s30)*. % 76.16/76.39 199378[84:MRR:226.0,199377.0] || -> until2p7(s31)* node4(s30). % 76.16/76.39 199379[85:Spt:199378.0] || -> until2p7(s31)*. % 76.16/76.39 199380[85:MRR:227.0,199379.0] || -> until2p7(s32)* node4(s31). % 76.16/76.39 199381[86:Spt:199380.0] || -> until2p7(s32)*. % 76.16/76.39 199382[86:MRR:228.0,199381.0] || -> until2p7(s33)* node4(s32). % 76.16/76.39 199383[87:Spt:199382.0] || -> until2p7(s33)*. % 76.16/76.39 199384[87:MRR:229.0,199383.0] || -> until2p7(s34)* node4(s33). % 76.16/76.39 199385[88:Spt:199384.0] || -> until2p7(s34)*. % 76.16/76.39 199386[88:MRR:230.0,199385.0] || -> until2p7(s35)* node4(s34). % 76.16/76.39 199387[89:Spt:199386.0] || -> until2p7(s35)*. % 76.16/76.39 199388[89:MRR:231.0,199387.0] || -> until2p7(s36)* node4(s35). % 76.16/76.39 199389[90:Spt:199388.0] || -> until2p7(s36)*. % 76.16/76.39 199390[90:MRR:232.0,199389.0] || -> until2p7(s37)* node4(s36). % 76.16/76.39 199391[91:Spt:199390.0] || -> until2p7(s37)*. % 76.16/76.39 199392[91:MRR:235.0,199391.0] || -> until2p7(s38)* node4(s37). % 76.16/76.39 199393[92:Spt:199392.0] || -> until2p7(s38)*. % 76.16/76.39 199394[92:MRR:236.0,199393.0] || -> until2p7(s39)* node4(s38). % 76.16/76.39 199395[93:Spt:199394.0] || -> until2p7(s39)*. % 76.16/76.39 199396[93:MRR:237.0,199395.0] || -> until2p7(s40)* node4(s39). % 76.16/76.39 199397[94:Spt:199396.0] || -> until2p7(s40)*. % 76.16/76.39 199398[94:MRR:238.0,199397.0] || -> until2p7(s41)* node4(s40). % 76.16/76.39 199399[95:Spt:199398.0] || -> until2p7(s41)*. % 76.16/76.39 199400[95:MRR:239.0,199399.0] || -> until2p7(s42)* node4(s41). % 76.16/76.39 199401[96:Spt:199400.0] || -> until2p7(s42)*. % 76.16/76.39 199402[96:MRR:240.0,199401.0] || -> until2p7(s43)* node4(s42). % 76.16/76.39 199403[97:Spt:199402.0] || -> until2p7(s43)*. % 76.16/76.39 199404[97:MRR:241.0,199403.0] || -> until2p7(s44)* node4(s43). % 76.16/76.39 199405[98:Spt:199404.0] || -> until2p7(s44)*. % 76.16/76.39 199406[98:MRR:539.0,199405.0] || -> until2p7(s45)* node4(s44). % 76.16/76.39 199407[99:Spt:199406.0] || -> until2p7(s45)*. % 76.16/76.39 199408[99:MRR:544.0,199407.0] || -> until2p7(s46)* node4(s45). % 76.16/76.39 199409[100:Spt:199408.0] || -> until2p7(s46)*. % 76.16/76.39 199410[100:MRR:549.0,199409.0] || -> until2p7(s47)* node4(s46). % 76.16/76.39 199411[101:Spt:199410.0] || -> until2p7(s47)*. % 76.16/76.39 199412[101:MRR:554.0,199411.0] || -> until2p7(s48)* node4(s47). % 76.16/76.39 199413[102:Spt:199412.0] || -> until2p7(s48)*. % 76.16/76.39 199414[102:MRR:559.0,199413.0] || -> until2p7(s49)* node4(s48). % 76.16/76.39 199415[103:Spt:199414.0] || -> until2p7(s49)*. % 76.16/76.39 199416[103:MRR:194.0,199415.0] || -> node4(s49)*. % 76.16/76.39 199417[103:MRR:199365.0,199416.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.39 199421[103:Res:53.1,199417.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.39 199423[103:MRR:199421.0,78381.0] || -> . % 76.16/76.39 199424[103:Spt:199423.0,199414.0,199415.0] || until2p7(s49)*+ -> . % 76.16/76.39 199425[103:Spt:199423.0,199414.1] || -> node4(s48)*. % 76.16/76.39 199426[103:MRR:78384.0,199425.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.39 199429[103:Res:53.1,199426.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 199432[103:Res:199429.0,61.1] always3(s48) || -> . % 76.16/76.39 199433[103:SSi:199432.0,78281.0,78387.0,192147.0,199413.0,199425.0] || -> . % 76.16/76.39 199434[102:Spt:199433.0,199412.0,199413.0] || until2p7(s48)*+ -> . % 76.16/76.39 199435[102:Spt:199433.0,199412.1] || -> node4(s47)*. % 76.16/76.39 199437[102:MRR:777.0,199435.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.39 199449[102:Res:53.1,199437.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.39 199451[103:Spt:199449.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 199453[103:Res:199451.0,61.1] always3(s47) || -> . % 76.16/76.39 199454[103:SSi:199453.0,78277.0,78280.0,192146.0,199411.0,199435.0] || -> . % 76.16/76.39 199455[103:Spt:199454.0,199449.0,199451.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.39 199456[103:Spt:199454.0,199449.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.39 199460[103:Res:199456.0,61.1] always3(s48) || -> . % 76.16/76.39 199461[103:SSi:199460.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.39 199462[101:Spt:199461.0,199410.0,199411.0] || until2p7(s47)*+ -> . % 76.16/76.39 199463[101:Spt:199461.0,199410.1] || -> node4(s46)*. % 76.16/76.39 199465[101:MRR:780.0,199463.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.39 199472[101:Res:53.1,199465.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.39 199477[102:Spt:199472.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 199479[102:Res:199477.0,61.1] always3(s46) || -> . % 76.16/76.39 199480[102:SSi:199479.0,78272.0,78276.0,192145.0,199409.0,199463.0] || -> . % 76.16/76.39 199481[102:Spt:199480.0,199472.0,199477.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.39 199482[102:Spt:199480.0,199472.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.39 199486[102:Res:199482.0,61.1] always3(s47) || -> . % 76.16/76.39 199487[102:SSi:199486.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.39 199488[100:Spt:199487.0,199408.0,199409.0] || until2p7(s46)*+ -> . % 76.16/76.39 199489[100:Spt:199487.0,199408.1] || -> node4(s45)*. % 76.16/76.39 199491[100:MRR:783.0,199489.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.39 199494[100:Res:53.1,199491.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.39 199496[101:Spt:199494.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 199498[101:Res:199496.0,61.1] always3(s45) || -> . % 76.16/76.39 199499[101:SSi:199498.0,78268.0,78271.0,192144.0,199407.0,199489.0] || -> . % 76.16/76.39 199500[101:Spt:199499.0,199494.0,199496.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.39 199501[101:Spt:199499.0,199494.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.39 199505[101:Res:199501.0,61.1] always3(s46) || -> . % 76.16/76.39 199506[101:SSi:199505.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.39 199507[99:Spt:199506.0,199406.0,199407.0] || until2p7(s45)*+ -> . % 76.16/76.39 199508[99:Spt:199506.0,199406.1] || -> node4(s44)*. % 76.16/76.39 199510[99:MRR:786.0,199508.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.39 199513[99:Res:53.1,199510.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.39 199515[100:Spt:199513.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 199517[100:Res:199515.0,61.1] always3(s44) || -> . % 76.16/76.39 199518[100:SSi:199517.0,78263.0,78267.0,192143.0,199405.0,199508.0] || -> . % 76.16/76.39 199519[100:Spt:199518.0,199513.0,199515.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.39 199520[100:Spt:199518.0,199513.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.39 199524[100:Res:199520.0,61.1] always3(s45) || -> . % 76.16/76.39 199525[100:SSi:199524.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.39 199526[98:Spt:199525.0,199404.0,199405.0] || until2p7(s44)*+ -> . % 76.16/76.39 199527[98:Spt:199525.0,199404.1] || -> node4(s43)*. % 76.16/76.39 199529[98:MRR:789.0,199527.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.39 199532[98:Res:53.1,199529.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.39 199534[99:Spt:199532.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 199536[99:Res:199534.0,61.1] always3(s43) || -> . % 76.16/76.39 199537[99:SSi:199536.0,78259.0,78262.0,192142.0,199403.0,199527.0] || -> . % 76.16/76.39 199538[99:Spt:199537.0,199532.0,199534.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.39 199539[99:Spt:199537.0,199532.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.39 199543[99:Res:199539.0,61.1] always3(s44) || -> . % 76.16/76.39 199544[99:SSi:199543.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.39 199545[97:Spt:199544.0,199402.0,199403.0] || until2p7(s43)*+ -> . % 76.16/76.39 199546[97:Spt:199544.0,199402.1] || -> node4(s42)*. % 76.16/76.39 199548[97:MRR:792.0,199546.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.39 199551[97:Res:53.1,199548.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.39 199556[98:Spt:199551.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 199558[98:Res:199556.0,61.1] always3(s42) || -> . % 76.16/76.39 199559[98:SSi:199558.0,78254.0,78258.0,192141.0,199401.0,199546.0] || -> . % 76.16/76.39 199560[98:Spt:199559.0,199551.0,199556.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.39 199561[98:Spt:199559.0,199551.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.39 199565[98:Res:199561.0,61.1] always3(s43) || -> . % 76.16/76.39 199566[98:SSi:199565.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.39 199567[96:Spt:199566.0,199400.0,199401.0] || until2p7(s42)*+ -> . % 76.16/76.39 199568[96:Spt:199566.0,199400.1] || -> node4(s41)*. % 76.16/76.39 199570[96:MRR:795.0,199568.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.39 199573[96:Res:53.1,199570.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.39 199575[97:Spt:199573.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 199577[97:Res:199575.0,61.1] always3(s41) || -> . % 76.16/76.39 199578[97:SSi:199577.0,78250.0,78253.0,192140.0,199399.0,199568.0] || -> . % 76.16/76.39 199579[97:Spt:199578.0,199573.0,199575.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.39 199580[97:Spt:199578.0,199573.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.39 199584[97:Res:199580.0,61.1] always3(s42) || -> . % 76.16/76.39 199585[97:SSi:199584.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.39 199586[95:Spt:199585.0,199398.0,199399.0] || until2p7(s41)*+ -> . % 76.16/76.39 199587[95:Spt:199585.0,199398.1] || -> node4(s40)*. % 76.16/76.39 199589[95:MRR:798.0,199587.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.39 199592[95:Res:53.1,199589.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.39 199594[96:Spt:199592.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 199596[96:Res:199594.0,61.1] always3(s40) || -> . % 76.16/76.39 199597[96:SSi:199596.0,78245.0,78249.0,192139.0,199397.0,199587.0] || -> . % 76.16/76.39 199598[96:Spt:199597.0,199592.0,199594.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.39 199599[96:Spt:199597.0,199592.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.39 199603[96:Res:199599.0,61.1] always3(s41) || -> . % 76.16/76.39 199604[96:SSi:199603.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.39 199605[94:Spt:199604.0,199396.0,199397.0] || until2p7(s40)*+ -> . % 76.16/76.39 199606[94:Spt:199604.0,199396.1] || -> node4(s39)*. % 76.16/76.39 199608[94:MRR:801.0,199606.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.39 199611[94:Res:53.1,199608.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.39 199613[95:Spt:199611.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 199615[95:Res:199613.0,61.1] always3(s39) || -> . % 76.16/76.39 199616[95:SSi:199615.0,78241.0,78244.0,192138.0,199395.0,199606.0] || -> . % 76.16/76.39 199617[95:Spt:199616.0,199611.0,199613.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.39 199618[95:Spt:199616.0,199611.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.39 199622[95:Res:199618.0,61.1] always3(s40) || -> . % 76.16/76.39 199623[95:SSi:199622.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.39 199624[93:Spt:199623.0,199394.0,199395.0] || until2p7(s39)*+ -> . % 76.16/76.39 199625[93:Spt:199623.0,199394.1] || -> node4(s38)*. % 76.16/76.39 199627[93:MRR:804.0,199625.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.39 199630[93:Res:53.1,199627.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.39 199635[94:Spt:199630.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 199637[94:Res:199635.0,61.1] always3(s38) || -> . % 76.16/76.39 199638[94:SSi:199637.0,78236.0,78240.0,192137.0,199393.0,199625.0] || -> . % 76.16/76.39 199639[94:Spt:199638.0,199630.0,199635.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.39 199640[94:Spt:199638.0,199630.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.39 199644[94:Res:199640.0,61.1] always3(s39) || -> . % 76.16/76.39 199645[94:SSi:199644.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.39 199646[92:Spt:199645.0,199392.0,199393.0] || until2p7(s38)*+ -> . % 76.16/76.39 199647[92:Spt:199645.0,199392.1] || -> node4(s37)*. % 76.16/76.39 199649[92:MRR:807.0,199647.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.39 199652[92:Res:53.1,199649.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.39 199654[93:Spt:199652.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 199656[93:Res:199654.0,61.1] always3(s37) || -> . % 76.16/76.39 199657[93:SSi:199656.0,78232.0,78235.0,192136.0,199391.0,199647.0] || -> . % 76.16/76.39 199658[93:Spt:199657.0,199652.0,199654.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.39 199659[93:Spt:199657.0,199652.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.39 199663[93:Res:199659.0,61.1] always3(s38) || -> . % 76.16/76.39 199664[93:SSi:199663.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.39 199665[91:Spt:199664.0,199390.0,199391.0] || until2p7(s37)*+ -> . % 76.16/76.39 199666[91:Spt:199664.0,199390.1] || -> node4(s36)*. % 76.16/76.39 199668[91:MRR:810.0,199666.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.39 199671[91:Res:53.1,199668.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.39 199673[92:Spt:199671.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 199675[92:Res:199673.0,61.1] always3(s36) || -> . % 76.16/76.39 199676[92:SSi:199675.0,78227.0,78231.0,192135.0,199389.0,199666.0] || -> . % 76.16/76.39 199677[92:Spt:199676.0,199671.0,199673.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.39 199678[92:Spt:199676.0,199671.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.39 199682[92:Res:199678.0,61.1] always3(s37) || -> . % 76.16/76.39 199683[92:SSi:199682.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.39 199684[90:Spt:199683.0,199388.0,199389.0] || until2p7(s36)*+ -> . % 76.16/76.39 199685[90:Spt:199683.0,199388.1] || -> node4(s35)*. % 76.16/76.39 199687[90:MRR:813.0,199685.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.39 199690[90:Res:53.1,199687.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.39 199692[91:Spt:199690.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 199694[91:Res:199692.0,61.1] always3(s35) || -> . % 76.16/76.39 199695[91:SSi:199694.0,78223.0,78226.0,192134.0,199387.0,199685.0] || -> . % 76.16/76.39 199696[91:Spt:199695.0,199690.0,199692.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.39 199697[91:Spt:199695.0,199690.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.39 199701[91:Res:199697.0,61.1] always3(s36) || -> . % 76.16/76.39 199702[91:SSi:199701.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.39 199703[89:Spt:199702.0,199386.0,199387.0] || until2p7(s35)*+ -> . % 76.16/76.39 199704[89:Spt:199702.0,199386.1] || -> node4(s34)*. % 76.16/76.39 199706[89:MRR:816.0,199704.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.39 199709[89:Res:53.1,199706.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.39 199714[90:Spt:199709.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 199716[90:Res:199714.0,61.1] always3(s34) || -> . % 76.16/76.39 199717[90:SSi:199716.0,78218.0,78222.0,192133.0,199385.0,199704.0] || -> . % 76.16/76.39 199718[90:Spt:199717.0,199709.0,199714.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.39 199719[90:Spt:199717.0,199709.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.39 199723[90:Res:199719.0,61.1] always3(s35) || -> . % 76.16/76.39 199724[90:SSi:199723.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.39 199725[88:Spt:199724.0,199384.0,199385.0] || until2p7(s34)*+ -> . % 76.16/76.39 199726[88:Spt:199724.0,199384.1] || -> node4(s33)*. % 76.16/76.39 199728[88:MRR:819.0,199726.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.39 199731[88:Res:53.1,199728.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.39 199733[89:Spt:199731.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 199735[89:Res:199733.0,61.1] always3(s33) || -> . % 76.16/76.39 199736[89:SSi:199735.0,78214.0,78217.0,192132.0,199383.0,199726.0] || -> . % 76.16/76.39 199737[89:Spt:199736.0,199731.0,199733.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.39 199738[89:Spt:199736.0,199731.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.39 199742[89:Res:199738.0,61.1] always3(s34) || -> . % 76.16/76.39 199743[89:SSi:199742.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.39 199744[87:Spt:199743.0,199382.0,199383.0] || until2p7(s33)*+ -> . % 76.16/76.39 199745[87:Spt:199743.0,199382.1] || -> node4(s32)*. % 76.16/76.39 199747[87:MRR:822.0,199745.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.39 199750[87:Res:53.1,199747.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.39 199752[88:Spt:199750.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 199754[88:Res:199752.0,61.1] always3(s32) || -> . % 76.16/76.39 199755[88:SSi:199754.0,78209.0,78213.0,192131.0,199381.0,199745.0] || -> . % 76.16/76.39 199756[88:Spt:199755.0,199750.0,199752.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.39 199757[88:Spt:199755.0,199750.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.39 199761[88:Res:199757.0,61.1] always3(s33) || -> . % 76.16/76.39 199762[88:SSi:199761.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.39 199763[86:Spt:199762.0,199380.0,199381.0] || until2p7(s32)*+ -> . % 76.16/76.39 199764[86:Spt:199762.0,199380.1] || -> node4(s31)*. % 76.16/76.39 199766[86:MRR:825.0,199764.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.39 199769[86:Res:53.1,199766.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.39 199771[87:Spt:199769.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 199773[87:Res:199771.0,61.1] always3(s31) || -> . % 76.16/76.39 199774[87:SSi:199773.0,78205.0,78208.0,192130.0,199379.0,199764.0] || -> . % 76.16/76.39 199775[87:Spt:199774.0,199769.0,199771.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.39 199776[87:Spt:199774.0,199769.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.39 199780[87:Res:199776.0,61.1] always3(s32) || -> . % 76.16/76.39 199781[87:SSi:199780.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.39 199782[85:Spt:199781.0,199378.0,199379.0] || until2p7(s31)*+ -> . % 76.16/76.39 199783[85:Spt:199781.0,199378.1] || -> node4(s30)*. % 76.16/76.39 199785[85:MRR:828.0,199783.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.39 199788[85:Res:53.1,199785.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.39 199793[86:Spt:199788.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.39 199795[86:Res:199793.0,61.1] always3(s30) || -> . % 76.16/76.39 199796[86:SSi:199795.0,78200.0,78204.0,192129.0,199377.0,199783.0] || -> . % 76.16/76.39 199797[86:Spt:199796.0,199788.0,199793.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.39 199798[86:Spt:199796.0,199788.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.39 199802[86:Res:199798.0,61.1] always3(s31) || -> . % 76.16/76.39 199803[86:SSi:199802.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.39 199804[84:Spt:199803.0,199376.0,199377.0] || until2p7(s30)*+ -> . % 76.16/76.39 199805[84:Spt:199803.0,199376.1] || -> node4(s29)*. % 76.16/76.39 199807[84:MRR:831.0,199805.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.40 199810[84:Res:53.1,199807.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.40 199812[85:Spt:199810.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 199814[85:Res:199812.0,61.1] always3(s29) || -> . % 76.16/76.40 199815[85:SSi:199814.0,78196.0,78199.0,192128.0,199375.0,199805.0] || -> . % 76.16/76.40 199816[85:Spt:199815.0,199810.0,199812.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.40 199817[85:Spt:199815.0,199810.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 199821[85:Res:199817.0,61.1] always3(s30) || -> . % 76.16/76.40 199822[85:SSi:199821.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.40 199823[83:Spt:199822.0,199374.0,199375.0] || until2p7(s29)*+ -> . % 76.16/76.40 199824[83:Spt:199822.0,199374.1] || -> node4(s28)*. % 76.16/76.40 199826[83:MRR:834.0,199824.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.40 199829[83:Res:53.1,199826.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.40 199831[84:Spt:199829.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 199833[84:Res:199831.0,61.1] always3(s28) || -> . % 76.16/76.40 199834[84:SSi:199833.0,78191.0,78195.0,192127.0,199373.0,199824.0] || -> . % 76.16/76.40 199835[84:Spt:199834.0,199829.0,199831.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.40 199836[84:Spt:199834.0,199829.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 199840[84:Res:199836.0,61.1] always3(s29) || -> . % 76.16/76.40 199841[84:SSi:199840.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.40 199842[82:Spt:199841.0,199372.0,199373.0] || until2p7(s28)*+ -> . % 76.16/76.40 199843[82:Spt:199841.0,199372.1] || -> node4(s27)*. % 76.16/76.40 199845[82:MRR:837.0,199843.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.40 199848[82:Res:53.1,199845.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.40 199850[83:Spt:199848.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 199852[83:Res:199850.0,61.1] always3(s27) || -> . % 76.16/76.40 199853[83:SSi:199852.0,78187.0,78190.0,192126.0,199371.0,199843.0] || -> . % 76.16/76.40 199854[83:Spt:199853.0,199848.0,199850.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.40 199855[83:Spt:199853.0,199848.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 199859[83:Res:199855.0,61.1] always3(s28) || -> . % 76.16/76.40 199860[83:SSi:199859.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.40 199861[81:Spt:199860.0,199370.0,199371.0] || until2p7(s27)*+ -> . % 76.16/76.40 199862[81:Spt:199860.0,199370.1] || -> node4(s26)*. % 76.16/76.40 199864[81:MRR:840.0,199862.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.40 199867[81:Res:53.1,199864.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.40 199869[81:MRR:199867.0,199360.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 199874[81:Res:199869.0,61.1] always3(s27) || -> . % 76.16/76.40 199875[81:SSi:199874.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.40 199876[79:Spt:199875.0,199267.0,199270.0] || trans(s49,s26)*+ -> . % 76.16/76.40 199877[79:Spt:199875.0,199267.1,199267.2,199267.3,199267.4,199267.5,199267.6,199267.7,199267.8,199267.9,199267.10,199267.11,199267.12,199267.13,199267.14,199267.15,199267.16,199267.17,199267.18,199267.19,199267.20] || -> trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.40 199879[79:MRR:199269.1,199876.0] xuntil6(s49) || -> trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.40 199880[80:Spt:199877.0] || -> trans(s49,s25)*. % 76.16/76.40 199881[80:Res:199880.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s25)*. % 76.16/76.40 199883[80:Res:199880.0,60.0] || -> node2(s49,s25)*. % 76.16/76.40 199884[80:SSi:199881.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s25)*. % 76.16/76.40 199885[80:Res:199883.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 199966[80:SoR:199885.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 199968[80:SoR:199966.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s25,c_busy)* xuntil6(s49). % 76.16/76.40 199969[80:SSi:199968.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s25,c_busy)* xuntil6(s49). % 76.16/76.40 199970[81:Spt:199969.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 199972[81:Res:199970.0,61.1] always3(s25) || -> . % 76.16/76.40 199973[81:SSi:199972.0,78178.0,78181.0,192124.0] || -> . % 76.16/76.40 199974[81:Spt:199973.0,199969.1,199970.0] || m_main_v_state(s25,c_busy)*+ -> . % 76.16/76.40 199975[81:Spt:199973.0,199969.0,199969.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.40 199979[81:MRR:199966.2,199974.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.40 199980[81:Res:53.1,199975.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.40 199982[81:MRR:199980.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.40 199983[81:MRR:199884.0,199982.0] || -> until2p7(s25)*. % 76.16/76.40 199984[81:MRR:221.0,199983.0] || -> until2p7(s26)* node4(s25). % 76.16/76.40 199985[82:Spt:199984.0] || -> until2p7(s26)*. % 76.16/76.40 199986[82:MRR:222.0,199985.0] || -> until2p7(s27)* node4(s26). % 76.16/76.40 199987[83:Spt:199986.0] || -> until2p7(s27)*. % 76.16/76.40 199988[83:MRR:223.0,199987.0] || -> until2p7(s28)* node4(s27). % 76.16/76.40 199989[84:Spt:199988.0] || -> until2p7(s28)*. % 76.16/76.40 199990[84:MRR:224.0,199989.0] || -> until2p7(s29)* node4(s28). % 76.16/76.40 199991[85:Spt:199990.0] || -> until2p7(s29)*. % 76.16/76.40 199992[85:MRR:225.0,199991.0] || -> until2p7(s30)* node4(s29). % 76.16/76.40 199993[86:Spt:199992.0] || -> until2p7(s30)*. % 76.16/76.40 199994[86:MRR:226.0,199993.0] || -> until2p7(s31)* node4(s30). % 76.16/76.40 199995[87:Spt:199994.0] || -> until2p7(s31)*. % 76.16/76.40 199996[87:MRR:227.0,199995.0] || -> until2p7(s32)* node4(s31). % 76.16/76.40 199997[88:Spt:199996.0] || -> until2p7(s32)*. % 76.16/76.40 199998[88:MRR:228.0,199997.0] || -> until2p7(s33)* node4(s32). % 76.16/76.40 199999[89:Spt:199998.0] || -> until2p7(s33)*. % 76.16/76.40 200000[89:MRR:229.0,199999.0] || -> until2p7(s34)* node4(s33). % 76.16/76.40 200001[90:Spt:200000.0] || -> until2p7(s34)*. % 76.16/76.40 200002[90:MRR:230.0,200001.0] || -> until2p7(s35)* node4(s34). % 76.16/76.40 200003[91:Spt:200002.0] || -> until2p7(s35)*. % 76.16/76.40 200004[91:MRR:231.0,200003.0] || -> until2p7(s36)* node4(s35). % 76.16/76.40 200005[92:Spt:200004.0] || -> until2p7(s36)*. % 76.16/76.40 200006[92:MRR:232.0,200005.0] || -> until2p7(s37)* node4(s36). % 76.16/76.40 200007[93:Spt:200006.0] || -> until2p7(s37)*. % 76.16/76.40 200008[93:MRR:235.0,200007.0] || -> until2p7(s38)* node4(s37). % 76.16/76.40 200009[94:Spt:200008.0] || -> until2p7(s38)*. % 76.16/76.40 200010[94:MRR:236.0,200009.0] || -> until2p7(s39)* node4(s38). % 76.16/76.40 200011[95:Spt:200010.0] || -> until2p7(s39)*. % 76.16/76.40 200012[95:MRR:237.0,200011.0] || -> until2p7(s40)* node4(s39). % 76.16/76.40 200013[96:Spt:200012.0] || -> until2p7(s40)*. % 76.16/76.40 200014[96:MRR:238.0,200013.0] || -> until2p7(s41)* node4(s40). % 76.16/76.40 200015[97:Spt:200014.0] || -> until2p7(s41)*. % 76.16/76.40 200016[97:MRR:239.0,200015.0] || -> until2p7(s42)* node4(s41). % 76.16/76.40 200017[98:Spt:200016.0] || -> until2p7(s42)*. % 76.16/76.40 200018[98:MRR:240.0,200017.0] || -> until2p7(s43)* node4(s42). % 76.16/76.40 200019[99:Spt:200018.0] || -> until2p7(s43)*. % 76.16/76.40 200020[99:MRR:241.0,200019.0] || -> until2p7(s44)* node4(s43). % 76.16/76.40 200021[100:Spt:200020.0] || -> until2p7(s44)*. % 76.16/76.40 200022[100:MRR:539.0,200021.0] || -> until2p7(s45)* node4(s44). % 76.16/76.40 200023[101:Spt:200022.0] || -> until2p7(s45)*. % 76.16/76.40 200024[101:MRR:544.0,200023.0] || -> until2p7(s46)* node4(s45). % 76.16/76.40 200025[102:Spt:200024.0] || -> until2p7(s46)*. % 76.16/76.40 200026[102:MRR:549.0,200025.0] || -> until2p7(s47)* node4(s46). % 76.16/76.40 200027[103:Spt:200026.0] || -> until2p7(s47)*. % 76.16/76.40 200028[103:MRR:554.0,200027.0] || -> until2p7(s48)* node4(s47). % 76.16/76.40 200029[104:Spt:200028.0] || -> until2p7(s48)*. % 76.16/76.40 200030[104:MRR:559.0,200029.0] || -> until2p7(s49)* node4(s48). % 76.16/76.40 200031[105:Spt:200030.0] || -> until2p7(s49)*. % 76.16/76.40 200032[105:MRR:194.0,200031.0] || -> node4(s49)*. % 76.16/76.40 200033[105:MRR:199979.0,200032.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.40 200034[105:Res:53.1,200033.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.40 200036[105:MRR:200034.0,78381.0] || -> . % 76.16/76.40 200037[105:Spt:200036.0,200030.0,200031.0] || until2p7(s49)*+ -> . % 76.16/76.40 200038[105:Spt:200036.0,200030.1] || -> node4(s48)*. % 76.16/76.40 200039[105:MRR:78384.0,200038.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.40 200042[105:Res:53.1,200039.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 200045[105:Res:200042.0,61.1] always3(s48) || -> . % 76.16/76.40 200046[105:SSi:200045.0,78281.0,78387.0,192147.0,200029.0,200038.0] || -> . % 76.16/76.40 200047[104:Spt:200046.0,200028.0,200029.0] || until2p7(s48)*+ -> . % 76.16/76.40 200048[104:Spt:200046.0,200028.1] || -> node4(s47)*. % 76.16/76.40 200050[104:MRR:777.0,200048.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.40 200065[104:Res:53.1,200050.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.40 200067[105:Spt:200065.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 200069[105:Res:200067.0,61.1] always3(s47) || -> . % 76.16/76.40 200070[105:SSi:200069.0,78277.0,78280.0,192146.0,200027.0,200048.0] || -> . % 76.16/76.40 200071[105:Spt:200070.0,200065.0,200067.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.40 200072[105:Spt:200070.0,200065.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 200076[105:Res:200072.0,61.1] always3(s48) || -> . % 76.16/76.40 200077[105:SSi:200076.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.40 200078[103:Spt:200077.0,200026.0,200027.0] || until2p7(s47)*+ -> . % 76.16/76.40 200079[103:Spt:200077.0,200026.1] || -> node4(s46)*. % 76.16/76.40 200081[103:MRR:780.0,200079.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.40 200091[103:Res:53.1,200081.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.40 200093[104:Spt:200091.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 200095[104:Res:200093.0,61.1] always3(s46) || -> . % 76.16/76.40 200096[104:SSi:200095.0,78272.0,78276.0,192145.0,200025.0,200079.0] || -> . % 76.16/76.40 200097[104:Spt:200096.0,200091.0,200093.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.40 200098[104:Spt:200096.0,200091.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 200102[104:Res:200098.0,61.1] always3(s47) || -> . % 76.16/76.40 200103[104:SSi:200102.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.40 200104[102:Spt:200103.0,200024.0,200025.0] || until2p7(s46)*+ -> . % 76.16/76.40 200105[102:Spt:200103.0,200024.1] || -> node4(s45)*. % 76.16/76.40 200107[102:MRR:783.0,200105.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.40 200110[102:Res:53.1,200107.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.40 200112[103:Spt:200110.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 200114[103:Res:200112.0,61.1] always3(s45) || -> . % 76.16/76.40 200115[103:SSi:200114.0,78268.0,78271.0,192144.0,200023.0,200105.0] || -> . % 76.16/76.40 200116[103:Spt:200115.0,200110.0,200112.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.40 200117[103:Spt:200115.0,200110.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 200121[103:Res:200117.0,61.1] always3(s46) || -> . % 76.16/76.40 200122[103:SSi:200121.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.40 200123[101:Spt:200122.0,200022.0,200023.0] || until2p7(s45)*+ -> . % 76.16/76.40 200124[101:Spt:200122.0,200022.1] || -> node4(s44)*. % 76.16/76.40 200126[101:MRR:786.0,200124.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.40 200129[101:Res:53.1,200126.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.40 200131[102:Spt:200129.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 200133[102:Res:200131.0,61.1] always3(s44) || -> . % 76.16/76.40 200134[102:SSi:200133.0,78263.0,78267.0,192143.0,200021.0,200124.0] || -> . % 76.16/76.40 200135[102:Spt:200134.0,200129.0,200131.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.40 200136[102:Spt:200134.0,200129.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 200140[102:Res:200136.0,61.1] always3(s45) || -> . % 76.16/76.40 200141[102:SSi:200140.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.40 200142[100:Spt:200141.0,200020.0,200021.0] || until2p7(s44)*+ -> . % 76.16/76.40 200143[100:Spt:200141.0,200020.1] || -> node4(s43)*. % 76.16/76.40 200145[100:MRR:789.0,200143.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.40 200148[100:Res:53.1,200145.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.40 200153[101:Spt:200148.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 200155[101:Res:200153.0,61.1] always3(s43) || -> . % 76.16/76.40 200156[101:SSi:200155.0,78259.0,78262.0,192142.0,200019.0,200143.0] || -> . % 76.16/76.40 200157[101:Spt:200156.0,200148.0,200153.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.40 200158[101:Spt:200156.0,200148.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 200162[101:Res:200158.0,61.1] always3(s44) || -> . % 76.16/76.40 200163[101:SSi:200162.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.40 200164[99:Spt:200163.0,200018.0,200019.0] || until2p7(s43)*+ -> . % 76.16/76.40 200165[99:Spt:200163.0,200018.1] || -> node4(s42)*. % 76.16/76.40 200167[99:MRR:792.0,200165.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.40 200170[99:Res:53.1,200167.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.40 200172[100:Spt:200170.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 200174[100:Res:200172.0,61.1] always3(s42) || -> . % 76.16/76.40 200175[100:SSi:200174.0,78254.0,78258.0,192141.0,200017.0,200165.0] || -> . % 76.16/76.40 200176[100:Spt:200175.0,200170.0,200172.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.40 200177[100:Spt:200175.0,200170.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 200181[100:Res:200177.0,61.1] always3(s43) || -> . % 76.16/76.40 200182[100:SSi:200181.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.40 200183[98:Spt:200182.0,200016.0,200017.0] || until2p7(s42)*+ -> . % 76.16/76.40 200184[98:Spt:200182.0,200016.1] || -> node4(s41)*. % 76.16/76.40 200186[98:MRR:795.0,200184.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.40 200189[98:Res:53.1,200186.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.40 200191[99:Spt:200189.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 200193[99:Res:200191.0,61.1] always3(s41) || -> . % 76.16/76.40 200194[99:SSi:200193.0,78250.0,78253.0,192140.0,200015.0,200184.0] || -> . % 76.16/76.40 200195[99:Spt:200194.0,200189.0,200191.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.40 200196[99:Spt:200194.0,200189.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 200200[99:Res:200196.0,61.1] always3(s42) || -> . % 76.16/76.40 200201[99:SSi:200200.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.40 200202[97:Spt:200201.0,200014.0,200015.0] || until2p7(s41)*+ -> . % 76.16/76.40 200203[97:Spt:200201.0,200014.1] || -> node4(s40)*. % 76.16/76.40 200205[97:MRR:798.0,200203.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.40 200208[97:Res:53.1,200205.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.40 200210[98:Spt:200208.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 200212[98:Res:200210.0,61.1] always3(s40) || -> . % 76.16/76.40 200213[98:SSi:200212.0,78245.0,78249.0,192139.0,200013.0,200203.0] || -> . % 76.16/76.40 200214[98:Spt:200213.0,200208.0,200210.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.40 200215[98:Spt:200213.0,200208.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 200219[98:Res:200215.0,61.1] always3(s41) || -> . % 76.16/76.40 200220[98:SSi:200219.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.40 200221[96:Spt:200220.0,200012.0,200013.0] || until2p7(s40)*+ -> . % 76.16/76.40 200222[96:Spt:200220.0,200012.1] || -> node4(s39)*. % 76.16/76.40 200224[96:MRR:801.0,200222.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.40 200227[96:Res:53.1,200224.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.40 200232[97:Spt:200227.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 200234[97:Res:200232.0,61.1] always3(s39) || -> . % 76.16/76.40 200235[97:SSi:200234.0,78241.0,78244.0,192138.0,200011.0,200222.0] || -> . % 76.16/76.40 200236[97:Spt:200235.0,200227.0,200232.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.40 200237[97:Spt:200235.0,200227.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 200241[97:Res:200237.0,61.1] always3(s40) || -> . % 76.16/76.40 200242[97:SSi:200241.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.40 200243[95:Spt:200242.0,200010.0,200011.0] || until2p7(s39)*+ -> . % 76.16/76.40 200244[95:Spt:200242.0,200010.1] || -> node4(s38)*. % 76.16/76.40 200246[95:MRR:804.0,200244.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.40 200249[95:Res:53.1,200246.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.40 200251[96:Spt:200249.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 200253[96:Res:200251.0,61.1] always3(s38) || -> . % 76.16/76.40 200254[96:SSi:200253.0,78236.0,78240.0,192137.0,200009.0,200244.0] || -> . % 76.16/76.40 200255[96:Spt:200254.0,200249.0,200251.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.40 200256[96:Spt:200254.0,200249.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 200260[96:Res:200256.0,61.1] always3(s39) || -> . % 76.16/76.40 200261[96:SSi:200260.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.40 200262[94:Spt:200261.0,200008.0,200009.0] || until2p7(s38)*+ -> . % 76.16/76.40 200263[94:Spt:200261.0,200008.1] || -> node4(s37)*. % 76.16/76.40 200265[94:MRR:807.0,200263.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.40 200268[94:Res:53.1,200265.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.40 200270[95:Spt:200268.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 200272[95:Res:200270.0,61.1] always3(s37) || -> . % 76.16/76.40 200273[95:SSi:200272.0,78232.0,78235.0,192136.0,200007.0,200263.0] || -> . % 76.16/76.40 200274[95:Spt:200273.0,200268.0,200270.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.40 200275[95:Spt:200273.0,200268.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 200279[95:Res:200275.0,61.1] always3(s38) || -> . % 76.16/76.40 200280[95:SSi:200279.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.40 200281[93:Spt:200280.0,200006.0,200007.0] || until2p7(s37)*+ -> . % 76.16/76.40 200282[93:Spt:200280.0,200006.1] || -> node4(s36)*. % 76.16/76.40 200284[93:MRR:810.0,200282.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.40 200287[93:Res:53.1,200284.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.40 200289[94:Spt:200287.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 200291[94:Res:200289.0,61.1] always3(s36) || -> . % 76.16/76.40 200292[94:SSi:200291.0,78227.0,78231.0,192135.0,200005.0,200282.0] || -> . % 76.16/76.40 200293[94:Spt:200292.0,200287.0,200289.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.40 200294[94:Spt:200292.0,200287.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 200298[94:Res:200294.0,61.1] always3(s37) || -> . % 76.16/76.40 200299[94:SSi:200298.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.40 200300[92:Spt:200299.0,200004.0,200005.0] || until2p7(s36)*+ -> . % 76.16/76.40 200301[92:Spt:200299.0,200004.1] || -> node4(s35)*. % 76.16/76.40 200303[92:MRR:813.0,200301.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.40 200306[92:Res:53.1,200303.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.40 200311[93:Spt:200306.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 200313[93:Res:200311.0,61.1] always3(s35) || -> . % 76.16/76.40 200314[93:SSi:200313.0,78223.0,78226.0,192134.0,200003.0,200301.0] || -> . % 76.16/76.40 200315[93:Spt:200314.0,200306.0,200311.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.40 200316[93:Spt:200314.0,200306.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 200320[93:Res:200316.0,61.1] always3(s36) || -> . % 76.16/76.40 200321[93:SSi:200320.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.40 200322[91:Spt:200321.0,200002.0,200003.0] || until2p7(s35)*+ -> . % 76.16/76.40 200323[91:Spt:200321.0,200002.1] || -> node4(s34)*. % 76.16/76.40 200325[91:MRR:816.0,200323.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.40 200328[91:Res:53.1,200325.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.40 200330[92:Spt:200328.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 200332[92:Res:200330.0,61.1] always3(s34) || -> . % 76.16/76.40 200333[92:SSi:200332.0,78218.0,78222.0,192133.0,200001.0,200323.0] || -> . % 76.16/76.40 200334[92:Spt:200333.0,200328.0,200330.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.40 200335[92:Spt:200333.0,200328.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 200339[92:Res:200335.0,61.1] always3(s35) || -> . % 76.16/76.40 200340[92:SSi:200339.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.40 200341[90:Spt:200340.0,200000.0,200001.0] || until2p7(s34)*+ -> . % 76.16/76.40 200342[90:Spt:200340.0,200000.1] || -> node4(s33)*. % 76.16/76.40 200344[90:MRR:819.0,200342.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.40 200347[90:Res:53.1,200344.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.40 200349[91:Spt:200347.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 200351[91:Res:200349.0,61.1] always3(s33) || -> . % 76.16/76.40 200352[91:SSi:200351.0,78214.0,78217.0,192132.0,199999.0,200342.0] || -> . % 76.16/76.40 200353[91:Spt:200352.0,200347.0,200349.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.40 200354[91:Spt:200352.0,200347.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 200358[91:Res:200354.0,61.1] always3(s34) || -> . % 76.16/76.40 200359[91:SSi:200358.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.40 200360[89:Spt:200359.0,199998.0,199999.0] || until2p7(s33)*+ -> . % 76.16/76.40 200361[89:Spt:200359.0,199998.1] || -> node4(s32)*. % 76.16/76.40 200363[89:MRR:822.0,200361.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.40 200366[89:Res:53.1,200363.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.40 200368[90:Spt:200366.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 200370[90:Res:200368.0,61.1] always3(s32) || -> . % 76.16/76.40 200371[90:SSi:200370.0,78209.0,78213.0,192131.0,199997.0,200361.0] || -> . % 76.16/76.40 200372[90:Spt:200371.0,200366.0,200368.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.40 200373[90:Spt:200371.0,200366.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 200377[90:Res:200373.0,61.1] always3(s33) || -> . % 76.16/76.40 200378[90:SSi:200377.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.40 200379[88:Spt:200378.0,199996.0,199997.0] || until2p7(s32)*+ -> . % 76.16/76.40 200380[88:Spt:200378.0,199996.1] || -> node4(s31)*. % 76.16/76.40 200382[88:MRR:825.0,200380.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.40 200385[88:Res:53.1,200382.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.40 200390[89:Spt:200385.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 200392[89:Res:200390.0,61.1] always3(s31) || -> . % 76.16/76.40 200393[89:SSi:200392.0,78205.0,78208.0,192130.0,199995.0,200380.0] || -> . % 76.16/76.40 200394[89:Spt:200393.0,200385.0,200390.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.40 200395[89:Spt:200393.0,200385.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 200399[89:Res:200395.0,61.1] always3(s32) || -> . % 76.16/76.40 200400[89:SSi:200399.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.40 200401[87:Spt:200400.0,199994.0,199995.0] || until2p7(s31)*+ -> . % 76.16/76.40 200402[87:Spt:200400.0,199994.1] || -> node4(s30)*. % 76.16/76.40 200404[87:MRR:828.0,200402.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.40 200407[87:Res:53.1,200404.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.40 200409[88:Spt:200407.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 200411[88:Res:200409.0,61.1] always3(s30) || -> . % 76.16/76.40 200412[88:SSi:200411.0,78200.0,78204.0,192129.0,199993.0,200402.0] || -> . % 76.16/76.40 200413[88:Spt:200412.0,200407.0,200409.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.40 200414[88:Spt:200412.0,200407.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 200418[88:Res:200414.0,61.1] always3(s31) || -> . % 76.16/76.40 200419[88:SSi:200418.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.40 200420[86:Spt:200419.0,199992.0,199993.0] || until2p7(s30)*+ -> . % 76.16/76.40 200421[86:Spt:200419.0,199992.1] || -> node4(s29)*. % 76.16/76.40 200423[86:MRR:831.0,200421.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.40 200426[86:Res:53.1,200423.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.40 200428[87:Spt:200426.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 200430[87:Res:200428.0,61.1] always3(s29) || -> . % 76.16/76.40 200431[87:SSi:200430.0,78196.0,78199.0,192128.0,199991.0,200421.0] || -> . % 76.16/76.40 200432[87:Spt:200431.0,200426.0,200428.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.40 200433[87:Spt:200431.0,200426.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 200437[87:Res:200433.0,61.1] always3(s30) || -> . % 76.16/76.40 200438[87:SSi:200437.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.40 200439[85:Spt:200438.0,199990.0,199991.0] || until2p7(s29)*+ -> . % 76.16/76.40 200440[85:Spt:200438.0,199990.1] || -> node4(s28)*. % 76.16/76.40 200442[85:MRR:834.0,200440.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.40 200445[85:Res:53.1,200442.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.40 200447[86:Spt:200445.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 200449[86:Res:200447.0,61.1] always3(s28) || -> . % 76.16/76.40 200450[86:SSi:200449.0,78191.0,78195.0,192127.0,199989.0,200440.0] || -> . % 76.16/76.40 200451[86:Spt:200450.0,200445.0,200447.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.40 200452[86:Spt:200450.0,200445.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 200456[86:Res:200452.0,61.1] always3(s29) || -> . % 76.16/76.40 200457[86:SSi:200456.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.40 200458[84:Spt:200457.0,199988.0,199989.0] || until2p7(s28)*+ -> . % 76.16/76.40 200459[84:Spt:200457.0,199988.1] || -> node4(s27)*. % 76.16/76.40 200461[84:MRR:837.0,200459.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.40 200464[84:Res:53.1,200461.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.40 200469[85:Spt:200464.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 200471[85:Res:200469.0,61.1] always3(s27) || -> . % 76.16/76.40 200472[85:SSi:200471.0,78187.0,78190.0,192126.0,199987.0,200459.0] || -> . % 76.16/76.40 200473[85:Spt:200472.0,200464.0,200469.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.40 200474[85:Spt:200472.0,200464.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 200478[85:Res:200474.0,61.1] always3(s28) || -> . % 76.16/76.40 200479[85:SSi:200478.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.40 200480[83:Spt:200479.0,199986.0,199987.0] || until2p7(s27)*+ -> . % 76.16/76.40 200481[83:Spt:200479.0,199986.1] || -> node4(s26)*. % 76.16/76.40 200483[83:MRR:840.0,200481.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.40 200486[83:Res:53.1,200483.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.40 200488[84:Spt:200486.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 200490[84:Res:200488.0,61.1] always3(s26) || -> . % 76.16/76.40 200491[84:SSi:200490.0,78182.0,78186.0,192125.0,199985.0,200481.0] || -> . % 76.16/76.40 200492[84:Spt:200491.0,200486.0,200488.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.40 200493[84:Spt:200491.0,200486.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 200497[84:Res:200493.0,61.1] always3(s27) || -> . % 76.16/76.40 200498[84:SSi:200497.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.40 200499[82:Spt:200498.0,199984.0,199985.0] || until2p7(s26)*+ -> . % 76.16/76.40 200500[82:Spt:200498.0,199984.1] || -> node4(s25)*. % 76.16/76.40 200502[82:MRR:843.0,200500.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.40 200505[82:Res:53.1,200502.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.40 200507[82:MRR:200505.0,199974.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 200509[82:Res:200507.0,61.1] always3(s26) || -> . % 76.16/76.40 200510[82:SSi:200509.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.40 200511[80:Spt:200510.0,199877.0,199880.0] || trans(s49,s25)*+ -> . % 76.16/76.40 200512[80:Spt:200510.0,199877.1,199877.2,199877.3,199877.4,199877.5,199877.6,199877.7,199877.8,199877.9,199877.10,199877.11,199877.12,199877.13,199877.14,199877.15,199877.16,199877.17,199877.18,199877.19] || -> trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.40 200514[80:MRR:199879.1,200511.0] xuntil6(s49) || -> trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.40 200515[81:Spt:200512.0] || -> trans(s49,s24)*. % 76.16/76.40 200516[81:Res:200515.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s24)*. % 76.16/76.40 200518[81:Res:200515.0,60.0] || -> node2(s49,s24)*. % 76.16/76.40 200519[81:SSi:200516.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s24)*. % 76.16/76.40 200520[81:Res:200518.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 200605[81:SoR:200520.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 200607[81:SoR:200605.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s24,c_busy)* xuntil6(s49). % 76.16/76.40 200608[81:SSi:200607.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s24,c_busy)* xuntil6(s49). % 76.16/76.40 200609[82:Spt:200608.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 200611[82:Res:200609.0,61.1] always3(s24) || -> . % 76.16/76.40 200612[82:SSi:200611.0,78173.0,78177.0,192123.0] || -> . % 76.16/76.40 200613[82:Spt:200612.0,200608.1,200609.0] || m_main_v_state(s24,c_busy)*+ -> . % 76.16/76.40 200614[82:Spt:200612.0,200608.0,200608.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.40 200618[82:MRR:200605.2,200613.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.40 200619[82:Res:53.1,200614.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.40 200621[82:MRR:200619.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.40 200622[82:MRR:200519.0,200621.0] || -> until2p7(s24)*. % 76.16/76.40 200623[82:MRR:220.0,200622.0] || -> until2p7(s25)* node4(s24). % 76.16/76.40 200624[83:Spt:200623.0] || -> until2p7(s25)*. % 76.16/76.40 200625[83:MRR:221.0,200624.0] || -> until2p7(s26)* node4(s25). % 76.16/76.40 200626[84:Spt:200625.0] || -> until2p7(s26)*. % 76.16/76.40 200627[84:MRR:222.0,200626.0] || -> until2p7(s27)* node4(s26). % 76.16/76.40 200628[85:Spt:200627.0] || -> until2p7(s27)*. % 76.16/76.40 200629[85:MRR:223.0,200628.0] || -> until2p7(s28)* node4(s27). % 76.16/76.40 200630[86:Spt:200629.0] || -> until2p7(s28)*. % 76.16/76.40 200631[86:MRR:224.0,200630.0] || -> until2p7(s29)* node4(s28). % 76.16/76.40 200632[87:Spt:200631.0] || -> until2p7(s29)*. % 76.16/76.40 200633[87:MRR:225.0,200632.0] || -> until2p7(s30)* node4(s29). % 76.16/76.40 200634[88:Spt:200633.0] || -> until2p7(s30)*. % 76.16/76.40 200635[88:MRR:226.0,200634.0] || -> until2p7(s31)* node4(s30). % 76.16/76.40 200636[89:Spt:200635.0] || -> until2p7(s31)*. % 76.16/76.40 200637[89:MRR:227.0,200636.0] || -> until2p7(s32)* node4(s31). % 76.16/76.40 200638[90:Spt:200637.0] || -> until2p7(s32)*. % 76.16/76.40 200639[90:MRR:228.0,200638.0] || -> until2p7(s33)* node4(s32). % 76.16/76.40 200640[91:Spt:200639.0] || -> until2p7(s33)*. % 76.16/76.40 200641[91:MRR:229.0,200640.0] || -> until2p7(s34)* node4(s33). % 76.16/76.40 200642[92:Spt:200641.0] || -> until2p7(s34)*. % 76.16/76.40 200643[92:MRR:230.0,200642.0] || -> until2p7(s35)* node4(s34). % 76.16/76.40 200644[93:Spt:200643.0] || -> until2p7(s35)*. % 76.16/76.40 200645[93:MRR:231.0,200644.0] || -> until2p7(s36)* node4(s35). % 76.16/76.40 200646[94:Spt:200645.0] || -> until2p7(s36)*. % 76.16/76.40 200647[94:MRR:232.0,200646.0] || -> until2p7(s37)* node4(s36). % 76.16/76.40 200648[95:Spt:200647.0] || -> until2p7(s37)*. % 76.16/76.40 200649[95:MRR:235.0,200648.0] || -> until2p7(s38)* node4(s37). % 76.16/76.40 200650[96:Spt:200649.0] || -> until2p7(s38)*. % 76.16/76.40 200651[96:MRR:236.0,200650.0] || -> until2p7(s39)* node4(s38). % 76.16/76.40 200652[97:Spt:200651.0] || -> until2p7(s39)*. % 76.16/76.40 200653[97:MRR:237.0,200652.0] || -> until2p7(s40)* node4(s39). % 76.16/76.40 200654[98:Spt:200653.0] || -> until2p7(s40)*. % 76.16/76.40 200655[98:MRR:238.0,200654.0] || -> until2p7(s41)* node4(s40). % 76.16/76.40 200656[99:Spt:200655.0] || -> until2p7(s41)*. % 76.16/76.40 200657[99:MRR:239.0,200656.0] || -> until2p7(s42)* node4(s41). % 76.16/76.40 200658[100:Spt:200657.0] || -> until2p7(s42)*. % 76.16/76.40 200659[100:MRR:240.0,200658.0] || -> until2p7(s43)* node4(s42). % 76.16/76.40 200660[101:Spt:200659.0] || -> until2p7(s43)*. % 76.16/76.40 200661[101:MRR:241.0,200660.0] || -> until2p7(s44)* node4(s43). % 76.16/76.40 200662[102:Spt:200661.0] || -> until2p7(s44)*. % 76.16/76.40 200663[102:MRR:539.0,200662.0] || -> until2p7(s45)* node4(s44). % 76.16/76.40 200664[103:Spt:200663.0] || -> until2p7(s45)*. % 76.16/76.40 200665[103:MRR:544.0,200664.0] || -> until2p7(s46)* node4(s45). % 76.16/76.40 200666[104:Spt:200665.0] || -> until2p7(s46)*. % 76.16/76.40 200667[104:MRR:549.0,200666.0] || -> until2p7(s47)* node4(s46). % 76.16/76.40 200668[105:Spt:200667.0] || -> until2p7(s47)*. % 76.16/76.40 200669[105:MRR:554.0,200668.0] || -> until2p7(s48)* node4(s47). % 76.16/76.40 200670[106:Spt:200669.0] || -> until2p7(s48)*. % 76.16/76.40 200671[106:MRR:559.0,200670.0] || -> until2p7(s49)* node4(s48). % 76.16/76.40 200672[107:Spt:200671.0] || -> until2p7(s49)*. % 76.16/76.40 200673[107:MRR:194.0,200672.0] || -> node4(s49)*. % 76.16/76.40 200674[107:MRR:200618.0,200673.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.40 200675[107:Res:53.1,200674.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.40 200677[107:MRR:200675.0,78381.0] || -> . % 76.16/76.40 200678[107:Spt:200677.0,200671.0,200672.0] || until2p7(s49)*+ -> . % 76.16/76.40 200679[107:Spt:200677.0,200671.1] || -> node4(s48)*. % 76.16/76.40 200680[107:MRR:78384.0,200679.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.40 200683[107:Res:53.1,200680.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 200686[107:Res:200683.0,61.1] always3(s48) || -> . % 76.16/76.40 200687[107:SSi:200686.0,78281.0,78387.0,192147.0,200670.0,200679.0] || -> . % 76.16/76.40 200688[106:Spt:200687.0,200669.0,200670.0] || until2p7(s48)*+ -> . % 76.16/76.40 200689[106:Spt:200687.0,200669.1] || -> node4(s47)*. % 76.16/76.40 200691[106:MRR:777.0,200689.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.40 200706[106:Res:53.1,200691.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.40 200708[107:Spt:200706.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 200710[107:Res:200708.0,61.1] always3(s47) || -> . % 76.16/76.40 200711[107:SSi:200710.0,78277.0,78280.0,192146.0,200668.0,200689.0] || -> . % 76.16/76.40 200712[107:Spt:200711.0,200706.0,200708.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.40 200713[107:Spt:200711.0,200706.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 200717[107:Res:200713.0,61.1] always3(s48) || -> . % 76.16/76.40 200718[107:SSi:200717.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.40 200719[105:Spt:200718.0,200667.0,200668.0] || until2p7(s47)*+ -> . % 76.16/76.40 200720[105:Spt:200718.0,200667.1] || -> node4(s46)*. % 76.16/76.40 200722[105:MRR:780.0,200720.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.40 200732[105:Res:53.1,200722.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.40 200734[106:Spt:200732.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 200736[106:Res:200734.0,61.1] always3(s46) || -> . % 76.16/76.40 200737[106:SSi:200736.0,78272.0,78276.0,192145.0,200666.0,200720.0] || -> . % 76.16/76.40 200738[106:Spt:200737.0,200732.0,200734.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.40 200739[106:Spt:200737.0,200732.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 200743[106:Res:200739.0,61.1] always3(s47) || -> . % 76.16/76.40 200744[106:SSi:200743.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.40 200745[104:Spt:200744.0,200665.0,200666.0] || until2p7(s46)*+ -> . % 76.16/76.40 200746[104:Spt:200744.0,200665.1] || -> node4(s45)*. % 76.16/76.40 200748[104:MRR:783.0,200746.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.40 200751[104:Res:53.1,200748.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.40 200753[105:Spt:200751.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 200755[105:Res:200753.0,61.1] always3(s45) || -> . % 76.16/76.40 200756[105:SSi:200755.0,78268.0,78271.0,192144.0,200664.0,200746.0] || -> . % 76.16/76.40 200757[105:Spt:200756.0,200751.0,200753.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.40 200758[105:Spt:200756.0,200751.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 200762[105:Res:200758.0,61.1] always3(s46) || -> . % 76.16/76.40 200763[105:SSi:200762.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.40 200764[103:Spt:200763.0,200663.0,200664.0] || until2p7(s45)*+ -> . % 76.16/76.40 200765[103:Spt:200763.0,200663.1] || -> node4(s44)*. % 76.16/76.40 200767[103:MRR:786.0,200765.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.40 200770[103:Res:53.1,200767.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.40 200772[104:Spt:200770.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 200774[104:Res:200772.0,61.1] always3(s44) || -> . % 76.16/76.40 200775[104:SSi:200774.0,78263.0,78267.0,192143.0,200662.0,200765.0] || -> . % 76.16/76.40 200776[104:Spt:200775.0,200770.0,200772.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.40 200777[104:Spt:200775.0,200770.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 200781[104:Res:200777.0,61.1] always3(s45) || -> . % 76.16/76.40 200782[104:SSi:200781.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.40 200783[102:Spt:200782.0,200661.0,200662.0] || until2p7(s44)*+ -> . % 76.16/76.40 200784[102:Spt:200782.0,200661.1] || -> node4(s43)*. % 76.16/76.40 200786[102:MRR:789.0,200784.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.40 200789[102:Res:53.1,200786.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.40 200794[103:Spt:200789.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 200796[103:Res:200794.0,61.1] always3(s43) || -> . % 76.16/76.40 200797[103:SSi:200796.0,78259.0,78262.0,192142.0,200660.0,200784.0] || -> . % 76.16/76.40 200798[103:Spt:200797.0,200789.0,200794.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.40 200799[103:Spt:200797.0,200789.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 200803[103:Res:200799.0,61.1] always3(s44) || -> . % 76.16/76.40 200804[103:SSi:200803.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.40 200805[101:Spt:200804.0,200659.0,200660.0] || until2p7(s43)*+ -> . % 76.16/76.40 200806[101:Spt:200804.0,200659.1] || -> node4(s42)*. % 76.16/76.40 200808[101:MRR:792.0,200806.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.40 200811[101:Res:53.1,200808.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.40 200813[102:Spt:200811.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 200815[102:Res:200813.0,61.1] always3(s42) || -> . % 76.16/76.40 200816[102:SSi:200815.0,78254.0,78258.0,192141.0,200658.0,200806.0] || -> . % 76.16/76.40 200817[102:Spt:200816.0,200811.0,200813.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.40 200818[102:Spt:200816.0,200811.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 200822[102:Res:200818.0,61.1] always3(s43) || -> . % 76.16/76.40 200823[102:SSi:200822.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.40 200824[100:Spt:200823.0,200657.0,200658.0] || until2p7(s42)*+ -> . % 76.16/76.40 200825[100:Spt:200823.0,200657.1] || -> node4(s41)*. % 76.16/76.40 200827[100:MRR:795.0,200825.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.40 200830[100:Res:53.1,200827.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.40 200832[101:Spt:200830.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 200834[101:Res:200832.0,61.1] always3(s41) || -> . % 76.16/76.40 200835[101:SSi:200834.0,78250.0,78253.0,192140.0,200656.0,200825.0] || -> . % 76.16/76.40 200836[101:Spt:200835.0,200830.0,200832.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.40 200837[101:Spt:200835.0,200830.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 200841[101:Res:200837.0,61.1] always3(s42) || -> . % 76.16/76.40 200842[101:SSi:200841.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.40 200843[99:Spt:200842.0,200655.0,200656.0] || until2p7(s41)*+ -> . % 76.16/76.40 200844[99:Spt:200842.0,200655.1] || -> node4(s40)*. % 76.16/76.40 200846[99:MRR:798.0,200844.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.40 200849[99:Res:53.1,200846.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.40 200851[100:Spt:200849.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 200853[100:Res:200851.0,61.1] always3(s40) || -> . % 76.16/76.40 200854[100:SSi:200853.0,78245.0,78249.0,192139.0,200654.0,200844.0] || -> . % 76.16/76.40 200855[100:Spt:200854.0,200849.0,200851.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.40 200856[100:Spt:200854.0,200849.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 200860[100:Res:200856.0,61.1] always3(s41) || -> . % 76.16/76.40 200861[100:SSi:200860.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.40 200862[98:Spt:200861.0,200653.0,200654.0] || until2p7(s40)*+ -> . % 76.16/76.40 200863[98:Spt:200861.0,200653.1] || -> node4(s39)*. % 76.16/76.40 200865[98:MRR:801.0,200863.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.40 200868[98:Res:53.1,200865.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.40 200873[99:Spt:200868.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 200875[99:Res:200873.0,61.1] always3(s39) || -> . % 76.16/76.40 200876[99:SSi:200875.0,78241.0,78244.0,192138.0,200652.0,200863.0] || -> . % 76.16/76.40 200877[99:Spt:200876.0,200868.0,200873.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.40 200878[99:Spt:200876.0,200868.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 200882[99:Res:200878.0,61.1] always3(s40) || -> . % 76.16/76.40 200883[99:SSi:200882.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.40 200884[97:Spt:200883.0,200651.0,200652.0] || until2p7(s39)*+ -> . % 76.16/76.40 200885[97:Spt:200883.0,200651.1] || -> node4(s38)*. % 76.16/76.40 200887[97:MRR:804.0,200885.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.40 200890[97:Res:53.1,200887.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.40 200892[98:Spt:200890.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 200894[98:Res:200892.0,61.1] always3(s38) || -> . % 76.16/76.40 200895[98:SSi:200894.0,78236.0,78240.0,192137.0,200650.0,200885.0] || -> . % 76.16/76.40 200896[98:Spt:200895.0,200890.0,200892.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.40 200897[98:Spt:200895.0,200890.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 200901[98:Res:200897.0,61.1] always3(s39) || -> . % 76.16/76.40 200902[98:SSi:200901.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.40 200903[96:Spt:200902.0,200649.0,200650.0] || until2p7(s38)*+ -> . % 76.16/76.40 200904[96:Spt:200902.0,200649.1] || -> node4(s37)*. % 76.16/76.40 200906[96:MRR:807.0,200904.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.40 200909[96:Res:53.1,200906.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.40 200911[97:Spt:200909.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 200913[97:Res:200911.0,61.1] always3(s37) || -> . % 76.16/76.40 200914[97:SSi:200913.0,78232.0,78235.0,192136.0,200648.0,200904.0] || -> . % 76.16/76.40 200915[97:Spt:200914.0,200909.0,200911.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.40 200916[97:Spt:200914.0,200909.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 200920[97:Res:200916.0,61.1] always3(s38) || -> . % 76.16/76.40 200921[97:SSi:200920.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.40 200922[95:Spt:200921.0,200647.0,200648.0] || until2p7(s37)*+ -> . % 76.16/76.40 200923[95:Spt:200921.0,200647.1] || -> node4(s36)*. % 76.16/76.40 200925[95:MRR:810.0,200923.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.40 200928[95:Res:53.1,200925.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.40 200930[96:Spt:200928.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 200932[96:Res:200930.0,61.1] always3(s36) || -> . % 76.16/76.40 200933[96:SSi:200932.0,78227.0,78231.0,192135.0,200646.0,200923.0] || -> . % 76.16/76.40 200934[96:Spt:200933.0,200928.0,200930.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.40 200935[96:Spt:200933.0,200928.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 200939[96:Res:200935.0,61.1] always3(s37) || -> . % 76.16/76.40 200940[96:SSi:200939.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.40 200941[94:Spt:200940.0,200645.0,200646.0] || until2p7(s36)*+ -> . % 76.16/76.40 200942[94:Spt:200940.0,200645.1] || -> node4(s35)*. % 76.16/76.40 200944[94:MRR:813.0,200942.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.40 200947[94:Res:53.1,200944.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.40 200952[95:Spt:200947.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 200954[95:Res:200952.0,61.1] always3(s35) || -> . % 76.16/76.40 200955[95:SSi:200954.0,78223.0,78226.0,192134.0,200644.0,200942.0] || -> . % 76.16/76.40 200956[95:Spt:200955.0,200947.0,200952.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.40 200957[95:Spt:200955.0,200947.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 200961[95:Res:200957.0,61.1] always3(s36) || -> . % 76.16/76.40 200962[95:SSi:200961.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.40 200963[93:Spt:200962.0,200643.0,200644.0] || until2p7(s35)*+ -> . % 76.16/76.40 200964[93:Spt:200962.0,200643.1] || -> node4(s34)*. % 76.16/76.40 200966[93:MRR:816.0,200964.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.40 200969[93:Res:53.1,200966.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.40 200971[94:Spt:200969.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 200973[94:Res:200971.0,61.1] always3(s34) || -> . % 76.16/76.40 200974[94:SSi:200973.0,78218.0,78222.0,192133.0,200642.0,200964.0] || -> . % 76.16/76.40 200975[94:Spt:200974.0,200969.0,200971.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.40 200976[94:Spt:200974.0,200969.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 200980[94:Res:200976.0,61.1] always3(s35) || -> . % 76.16/76.40 200981[94:SSi:200980.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.40 200982[92:Spt:200981.0,200641.0,200642.0] || until2p7(s34)*+ -> . % 76.16/76.40 200983[92:Spt:200981.0,200641.1] || -> node4(s33)*. % 76.16/76.40 200985[92:MRR:819.0,200983.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.40 200988[92:Res:53.1,200985.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.40 200990[93:Spt:200988.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 200992[93:Res:200990.0,61.1] always3(s33) || -> . % 76.16/76.40 200993[93:SSi:200992.0,78214.0,78217.0,192132.0,200640.0,200983.0] || -> . % 76.16/76.40 200994[93:Spt:200993.0,200988.0,200990.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.40 200995[93:Spt:200993.0,200988.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 200999[93:Res:200995.0,61.1] always3(s34) || -> . % 76.16/76.40 201000[93:SSi:200999.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.40 201001[91:Spt:201000.0,200639.0,200640.0] || until2p7(s33)*+ -> . % 76.16/76.40 201002[91:Spt:201000.0,200639.1] || -> node4(s32)*. % 76.16/76.40 201004[91:MRR:822.0,201002.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.40 201007[91:Res:53.1,201004.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.40 201009[92:Spt:201007.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 201011[92:Res:201009.0,61.1] always3(s32) || -> . % 76.16/76.40 201012[92:SSi:201011.0,78209.0,78213.0,192131.0,200638.0,201002.0] || -> . % 76.16/76.40 201013[92:Spt:201012.0,201007.0,201009.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.40 201014[92:Spt:201012.0,201007.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 201018[92:Res:201014.0,61.1] always3(s33) || -> . % 76.16/76.40 201019[92:SSi:201018.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.40 201020[90:Spt:201019.0,200637.0,200638.0] || until2p7(s32)*+ -> . % 76.16/76.40 201021[90:Spt:201019.0,200637.1] || -> node4(s31)*. % 76.16/76.40 201023[90:MRR:825.0,201021.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.40 201026[90:Res:53.1,201023.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.40 201031[91:Spt:201026.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 201033[91:Res:201031.0,61.1] always3(s31) || -> . % 76.16/76.40 201034[91:SSi:201033.0,78205.0,78208.0,192130.0,200636.0,201021.0] || -> . % 76.16/76.40 201035[91:Spt:201034.0,201026.0,201031.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.40 201036[91:Spt:201034.0,201026.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 201040[91:Res:201036.0,61.1] always3(s32) || -> . % 76.16/76.40 201041[91:SSi:201040.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.40 201042[89:Spt:201041.0,200635.0,200636.0] || until2p7(s31)*+ -> . % 76.16/76.40 201043[89:Spt:201041.0,200635.1] || -> node4(s30)*. % 76.16/76.40 201045[89:MRR:828.0,201043.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.40 201048[89:Res:53.1,201045.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.40 201050[90:Spt:201048.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 201052[90:Res:201050.0,61.1] always3(s30) || -> . % 76.16/76.40 201053[90:SSi:201052.0,78200.0,78204.0,192129.0,200634.0,201043.0] || -> . % 76.16/76.40 201054[90:Spt:201053.0,201048.0,201050.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.40 201055[90:Spt:201053.0,201048.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 201059[90:Res:201055.0,61.1] always3(s31) || -> . % 76.16/76.40 201060[90:SSi:201059.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.40 201061[88:Spt:201060.0,200633.0,200634.0] || until2p7(s30)*+ -> . % 76.16/76.40 201062[88:Spt:201060.0,200633.1] || -> node4(s29)*. % 76.16/76.40 201064[88:MRR:831.0,201062.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.40 201067[88:Res:53.1,201064.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.40 201069[89:Spt:201067.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 201071[89:Res:201069.0,61.1] always3(s29) || -> . % 76.16/76.40 201072[89:SSi:201071.0,78196.0,78199.0,192128.0,200632.0,201062.0] || -> . % 76.16/76.40 201073[89:Spt:201072.0,201067.0,201069.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.40 201074[89:Spt:201072.0,201067.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 201078[89:Res:201074.0,61.1] always3(s30) || -> . % 76.16/76.40 201079[89:SSi:201078.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.40 201080[87:Spt:201079.0,200631.0,200632.0] || until2p7(s29)*+ -> . % 76.16/76.40 201081[87:Spt:201079.0,200631.1] || -> node4(s28)*. % 76.16/76.40 201083[87:MRR:834.0,201081.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.40 201086[87:Res:53.1,201083.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.40 201088[88:Spt:201086.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 201090[88:Res:201088.0,61.1] always3(s28) || -> . % 76.16/76.40 201091[88:SSi:201090.0,78191.0,78195.0,192127.0,200630.0,201081.0] || -> . % 76.16/76.40 201092[88:Spt:201091.0,201086.0,201088.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.40 201093[88:Spt:201091.0,201086.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 201097[88:Res:201093.0,61.1] always3(s29) || -> . % 76.16/76.40 201098[88:SSi:201097.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.40 201099[86:Spt:201098.0,200629.0,200630.0] || until2p7(s28)*+ -> . % 76.16/76.40 201100[86:Spt:201098.0,200629.1] || -> node4(s27)*. % 76.16/76.40 201102[86:MRR:837.0,201100.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.40 201105[86:Res:53.1,201102.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.40 201110[87:Spt:201105.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 201112[87:Res:201110.0,61.1] always3(s27) || -> . % 76.16/76.40 201113[87:SSi:201112.0,78187.0,78190.0,192126.0,200628.0,201100.0] || -> . % 76.16/76.40 201114[87:Spt:201113.0,201105.0,201110.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.40 201115[87:Spt:201113.0,201105.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 201119[87:Res:201115.0,61.1] always3(s28) || -> . % 76.16/76.40 201120[87:SSi:201119.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.40 201121[85:Spt:201120.0,200627.0,200628.0] || until2p7(s27)*+ -> . % 76.16/76.40 201122[85:Spt:201120.0,200627.1] || -> node4(s26)*. % 76.16/76.40 201124[85:MRR:840.0,201122.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.40 201127[85:Res:53.1,201124.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.40 201129[86:Spt:201127.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 201131[86:Res:201129.0,61.1] always3(s26) || -> . % 76.16/76.40 201132[86:SSi:201131.0,78182.0,78186.0,192125.0,200626.0,201122.0] || -> . % 76.16/76.40 201133[86:Spt:201132.0,201127.0,201129.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.40 201134[86:Spt:201132.0,201127.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 201138[86:Res:201134.0,61.1] always3(s27) || -> . % 76.16/76.40 201139[86:SSi:201138.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.40 201140[84:Spt:201139.0,200625.0,200626.0] || until2p7(s26)*+ -> . % 76.16/76.40 201141[84:Spt:201139.0,200625.1] || -> node4(s25)*. % 76.16/76.40 201143[84:MRR:843.0,201141.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.40 201146[84:Res:53.1,201143.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.40 201148[85:Spt:201146.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 201150[85:Res:201148.0,61.1] always3(s25) || -> . % 76.16/76.40 201151[85:SSi:201150.0,78178.0,78181.0,192124.0,200624.0,201141.0] || -> . % 76.16/76.40 201152[85:Spt:201151.0,201146.0,201148.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.40 201153[85:Spt:201151.0,201146.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 201157[85:Res:201153.0,61.1] always3(s26) || -> . % 76.16/76.40 201158[85:SSi:201157.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.40 201159[83:Spt:201158.0,200623.0,200624.0] || until2p7(s25)*+ -> . % 76.16/76.40 201160[83:Spt:201158.0,200623.1] || -> node4(s24)*. % 76.16/76.40 201162[83:MRR:846.0,201160.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.40 201165[83:Res:53.1,201162.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.40 201167[83:MRR:201165.0,200613.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 201169[83:Res:201167.0,61.1] always3(s25) || -> . % 76.16/76.40 201170[83:SSi:201169.0,78178.0,78181.0,192124.0] || -> . % 76.16/76.40 201171[81:Spt:201170.0,200512.0,200515.0] || trans(s49,s24)*+ -> . % 76.16/76.40 201172[81:Spt:201170.0,200512.1,200512.2,200512.3,200512.4,200512.5,200512.6,200512.7,200512.8,200512.9,200512.10,200512.11,200512.12,200512.13,200512.14,200512.15,200512.16,200512.17,200512.18] || -> trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.40 201174[81:MRR:200514.1,201171.0] xuntil6(s49) || -> trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.40 201175[82:Spt:201172.0] || -> trans(s49,s23)*. % 76.16/76.40 201176[82:Res:201175.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s23)*. % 76.16/76.40 201178[82:Res:201175.0,60.0] || -> node2(s49,s23)*. % 76.16/76.40 201179[82:SSi:201176.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s23)*. % 76.16/76.40 201180[82:Res:201178.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 201269[82:SoR:201180.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 201271[82:SoR:201269.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s23,c_busy)* xuntil6(s49). % 76.16/76.40 201272[82:SSi:201271.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s23,c_busy)* xuntil6(s49). % 76.16/76.40 201273[83:Spt:201272.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 201275[83:Res:201273.0,61.1] always3(s23) || -> . % 76.16/76.40 201276[83:SSi:201275.0,78169.0,78172.0,192122.0] || -> . % 76.16/76.40 201277[83:Spt:201276.0,201272.1,201273.0] || m_main_v_state(s23,c_busy)*+ -> . % 76.16/76.40 201278[83:Spt:201276.0,201272.0,201272.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.40 201282[83:MRR:201269.2,201277.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.40 201283[83:Res:53.1,201278.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.40 201285[83:MRR:201283.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.40 201286[83:MRR:201179.0,201285.0] || -> until2p7(s23)*. % 76.16/76.40 201287[83:MRR:219.0,201286.0] || -> until2p7(s24)* node4(s23). % 76.16/76.40 201288[84:Spt:201287.0] || -> until2p7(s24)*. % 76.16/76.40 201289[84:MRR:220.0,201288.0] || -> until2p7(s25)* node4(s24). % 76.16/76.40 201290[85:Spt:201289.0] || -> until2p7(s25)*. % 76.16/76.40 201291[85:MRR:221.0,201290.0] || -> until2p7(s26)* node4(s25). % 76.16/76.40 201292[86:Spt:201291.0] || -> until2p7(s26)*. % 76.16/76.40 201293[86:MRR:222.0,201292.0] || -> until2p7(s27)* node4(s26). % 76.16/76.40 201294[87:Spt:201293.0] || -> until2p7(s27)*. % 76.16/76.40 201295[87:MRR:223.0,201294.0] || -> until2p7(s28)* node4(s27). % 76.16/76.40 201296[88:Spt:201295.0] || -> until2p7(s28)*. % 76.16/76.40 201297[88:MRR:224.0,201296.0] || -> until2p7(s29)* node4(s28). % 76.16/76.40 201298[89:Spt:201297.0] || -> until2p7(s29)*. % 76.16/76.40 201299[89:MRR:225.0,201298.0] || -> until2p7(s30)* node4(s29). % 76.16/76.40 201300[90:Spt:201299.0] || -> until2p7(s30)*. % 76.16/76.40 201301[90:MRR:226.0,201300.0] || -> until2p7(s31)* node4(s30). % 76.16/76.40 201302[91:Spt:201301.0] || -> until2p7(s31)*. % 76.16/76.40 201303[91:MRR:227.0,201302.0] || -> until2p7(s32)* node4(s31). % 76.16/76.40 201304[92:Spt:201303.0] || -> until2p7(s32)*. % 76.16/76.40 201305[92:MRR:228.0,201304.0] || -> until2p7(s33)* node4(s32). % 76.16/76.40 201306[93:Spt:201305.0] || -> until2p7(s33)*. % 76.16/76.40 201307[93:MRR:229.0,201306.0] || -> until2p7(s34)* node4(s33). % 76.16/76.40 201308[94:Spt:201307.0] || -> until2p7(s34)*. % 76.16/76.40 201309[94:MRR:230.0,201308.0] || -> until2p7(s35)* node4(s34). % 76.16/76.40 201310[95:Spt:201309.0] || -> until2p7(s35)*. % 76.16/76.40 201311[95:MRR:231.0,201310.0] || -> until2p7(s36)* node4(s35). % 76.16/76.40 201312[96:Spt:201311.0] || -> until2p7(s36)*. % 76.16/76.40 201313[96:MRR:232.0,201312.0] || -> until2p7(s37)* node4(s36). % 76.16/76.40 201314[97:Spt:201313.0] || -> until2p7(s37)*. % 76.16/76.40 201315[97:MRR:235.0,201314.0] || -> until2p7(s38)* node4(s37). % 76.16/76.40 201316[98:Spt:201315.0] || -> until2p7(s38)*. % 76.16/76.40 201317[98:MRR:236.0,201316.0] || -> until2p7(s39)* node4(s38). % 76.16/76.40 201318[99:Spt:201317.0] || -> until2p7(s39)*. % 76.16/76.40 201319[99:MRR:237.0,201318.0] || -> until2p7(s40)* node4(s39). % 76.16/76.40 201320[100:Spt:201319.0] || -> until2p7(s40)*. % 76.16/76.40 201321[100:MRR:238.0,201320.0] || -> until2p7(s41)* node4(s40). % 76.16/76.40 201322[101:Spt:201321.0] || -> until2p7(s41)*. % 76.16/76.40 201323[101:MRR:239.0,201322.0] || -> until2p7(s42)* node4(s41). % 76.16/76.40 201324[102:Spt:201323.0] || -> until2p7(s42)*. % 76.16/76.40 201325[102:MRR:240.0,201324.0] || -> until2p7(s43)* node4(s42). % 76.16/76.40 201326[103:Spt:201325.0] || -> until2p7(s43)*. % 76.16/76.40 201327[103:MRR:241.0,201326.0] || -> until2p7(s44)* node4(s43). % 76.16/76.40 201328[104:Spt:201327.0] || -> until2p7(s44)*. % 76.16/76.40 201329[104:MRR:539.0,201328.0] || -> until2p7(s45)* node4(s44). % 76.16/76.40 201330[105:Spt:201329.0] || -> until2p7(s45)*. % 76.16/76.40 201331[105:MRR:544.0,201330.0] || -> until2p7(s46)* node4(s45). % 76.16/76.40 201332[106:Spt:201331.0] || -> until2p7(s46)*. % 76.16/76.40 201333[106:MRR:549.0,201332.0] || -> until2p7(s47)* node4(s46). % 76.16/76.40 201334[107:Spt:201333.0] || -> until2p7(s47)*. % 76.16/76.40 201335[107:MRR:554.0,201334.0] || -> until2p7(s48)* node4(s47). % 76.16/76.40 201336[108:Spt:201335.0] || -> until2p7(s48)*. % 76.16/76.40 201337[108:MRR:559.0,201336.0] || -> until2p7(s49)* node4(s48). % 76.16/76.40 201338[109:Spt:201337.0] || -> until2p7(s49)*. % 76.16/76.40 201339[109:MRR:194.0,201338.0] || -> node4(s49)*. % 76.16/76.40 201340[109:MRR:201282.0,201339.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.40 201344[109:Res:53.1,201340.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.40 201346[109:MRR:201344.0,78381.0] || -> . % 76.16/76.40 201347[109:Spt:201346.0,201337.0,201338.0] || until2p7(s49)*+ -> . % 76.16/76.40 201348[109:Spt:201346.0,201337.1] || -> node4(s48)*. % 76.16/76.40 201349[109:MRR:78384.0,201348.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.40 201352[109:Res:53.1,201349.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 201355[109:Res:201352.0,61.1] always3(s48) || -> . % 76.16/76.40 201356[109:SSi:201355.0,78281.0,78387.0,192147.0,201336.0,201348.0] || -> . % 76.16/76.40 201357[108:Spt:201356.0,201335.0,201336.0] || until2p7(s48)*+ -> . % 76.16/76.40 201358[108:Spt:201356.0,201335.1] || -> node4(s47)*. % 76.16/76.40 201360[108:MRR:777.0,201358.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.40 201372[108:Res:53.1,201360.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.40 201374[109:Spt:201372.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 201376[109:Res:201374.0,61.1] always3(s47) || -> . % 76.16/76.40 201377[109:SSi:201376.0,78277.0,78280.0,192146.0,201334.0,201358.0] || -> . % 76.16/76.40 201378[109:Spt:201377.0,201372.0,201374.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.40 201379[109:Spt:201377.0,201372.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 201383[109:Res:201379.0,61.1] always3(s48) || -> . % 76.16/76.40 201384[109:SSi:201383.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.40 201385[107:Spt:201384.0,201333.0,201334.0] || until2p7(s47)*+ -> . % 76.16/76.40 201386[107:Spt:201384.0,201333.1] || -> node4(s46)*. % 76.16/76.40 201388[107:MRR:780.0,201386.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.40 201395[107:Res:53.1,201388.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.40 201400[108:Spt:201395.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 201402[108:Res:201400.0,61.1] always3(s46) || -> . % 76.16/76.40 201403[108:SSi:201402.0,78272.0,78276.0,192145.0,201332.0,201386.0] || -> . % 76.16/76.40 201404[108:Spt:201403.0,201395.0,201400.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.40 201405[108:Spt:201403.0,201395.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 201409[108:Res:201405.0,61.1] always3(s47) || -> . % 76.16/76.40 201410[108:SSi:201409.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.40 201411[106:Spt:201410.0,201331.0,201332.0] || until2p7(s46)*+ -> . % 76.16/76.40 201412[106:Spt:201410.0,201331.1] || -> node4(s45)*. % 76.16/76.40 201414[106:MRR:783.0,201412.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.40 201417[106:Res:53.1,201414.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.40 201419[107:Spt:201417.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 201421[107:Res:201419.0,61.1] always3(s45) || -> . % 76.16/76.40 201422[107:SSi:201421.0,78268.0,78271.0,192144.0,201330.0,201412.0] || -> . % 76.16/76.40 201423[107:Spt:201422.0,201417.0,201419.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.40 201424[107:Spt:201422.0,201417.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 201428[107:Res:201424.0,61.1] always3(s46) || -> . % 76.16/76.40 201429[107:SSi:201428.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.40 201430[105:Spt:201429.0,201329.0,201330.0] || until2p7(s45)*+ -> . % 76.16/76.40 201431[105:Spt:201429.0,201329.1] || -> node4(s44)*. % 76.16/76.40 201433[105:MRR:786.0,201431.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.40 201436[105:Res:53.1,201433.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.40 201438[106:Spt:201436.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 201440[106:Res:201438.0,61.1] always3(s44) || -> . % 76.16/76.40 201441[106:SSi:201440.0,78263.0,78267.0,192143.0,201328.0,201431.0] || -> . % 76.16/76.40 201442[106:Spt:201441.0,201436.0,201438.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.40 201443[106:Spt:201441.0,201436.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 201447[106:Res:201443.0,61.1] always3(s45) || -> . % 76.16/76.40 201448[106:SSi:201447.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.40 201449[104:Spt:201448.0,201327.0,201328.0] || until2p7(s44)*+ -> . % 76.16/76.40 201450[104:Spt:201448.0,201327.1] || -> node4(s43)*. % 76.16/76.40 201452[104:MRR:789.0,201450.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.40 201455[104:Res:53.1,201452.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.40 201457[105:Spt:201455.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 201459[105:Res:201457.0,61.1] always3(s43) || -> . % 76.16/76.40 201460[105:SSi:201459.0,78259.0,78262.0,192142.0,201326.0,201450.0] || -> . % 76.16/76.40 201461[105:Spt:201460.0,201455.0,201457.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.40 201462[105:Spt:201460.0,201455.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 201466[105:Res:201462.0,61.1] always3(s44) || -> . % 76.16/76.40 201467[105:SSi:201466.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.40 201468[103:Spt:201467.0,201325.0,201326.0] || until2p7(s43)*+ -> . % 76.16/76.40 201469[103:Spt:201467.0,201325.1] || -> node4(s42)*. % 76.16/76.40 201471[103:MRR:792.0,201469.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.40 201474[103:Res:53.1,201471.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.40 201479[104:Spt:201474.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 201481[104:Res:201479.0,61.1] always3(s42) || -> . % 76.16/76.40 201482[104:SSi:201481.0,78254.0,78258.0,192141.0,201324.0,201469.0] || -> . % 76.16/76.40 201483[104:Spt:201482.0,201474.0,201479.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.40 201484[104:Spt:201482.0,201474.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 201488[104:Res:201484.0,61.1] always3(s43) || -> . % 76.16/76.40 201489[104:SSi:201488.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.40 201490[102:Spt:201489.0,201323.0,201324.0] || until2p7(s42)*+ -> . % 76.16/76.40 201491[102:Spt:201489.0,201323.1] || -> node4(s41)*. % 76.16/76.40 201493[102:MRR:795.0,201491.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.40 201496[102:Res:53.1,201493.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.40 201498[103:Spt:201496.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 201500[103:Res:201498.0,61.1] always3(s41) || -> . % 76.16/76.40 201501[103:SSi:201500.0,78250.0,78253.0,192140.0,201322.0,201491.0] || -> . % 76.16/76.40 201502[103:Spt:201501.0,201496.0,201498.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.40 201503[103:Spt:201501.0,201496.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 201507[103:Res:201503.0,61.1] always3(s42) || -> . % 76.16/76.40 201508[103:SSi:201507.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.40 201509[101:Spt:201508.0,201321.0,201322.0] || until2p7(s41)*+ -> . % 76.16/76.40 201510[101:Spt:201508.0,201321.1] || -> node4(s40)*. % 76.16/76.40 201512[101:MRR:798.0,201510.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.40 201515[101:Res:53.1,201512.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.40 201517[102:Spt:201515.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 201519[102:Res:201517.0,61.1] always3(s40) || -> . % 76.16/76.40 201520[102:SSi:201519.0,78245.0,78249.0,192139.0,201320.0,201510.0] || -> . % 76.16/76.40 201521[102:Spt:201520.0,201515.0,201517.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.40 201522[102:Spt:201520.0,201515.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 201526[102:Res:201522.0,61.1] always3(s41) || -> . % 76.16/76.40 201527[102:SSi:201526.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.40 201528[100:Spt:201527.0,201319.0,201320.0] || until2p7(s40)*+ -> . % 76.16/76.40 201529[100:Spt:201527.0,201319.1] || -> node4(s39)*. % 76.16/76.40 201531[100:MRR:801.0,201529.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.40 201534[100:Res:53.1,201531.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.40 201536[101:Spt:201534.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 201538[101:Res:201536.0,61.1] always3(s39) || -> . % 76.16/76.40 201539[101:SSi:201538.0,78241.0,78244.0,192138.0,201318.0,201529.0] || -> . % 76.16/76.40 201540[101:Spt:201539.0,201534.0,201536.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.40 201541[101:Spt:201539.0,201534.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 201545[101:Res:201541.0,61.1] always3(s40) || -> . % 76.16/76.40 201546[101:SSi:201545.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.40 201547[99:Spt:201546.0,201317.0,201318.0] || until2p7(s39)*+ -> . % 76.16/76.40 201548[99:Spt:201546.0,201317.1] || -> node4(s38)*. % 76.16/76.40 201550[99:MRR:804.0,201548.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.40 201553[99:Res:53.1,201550.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.40 201558[100:Spt:201553.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 201560[100:Res:201558.0,61.1] always3(s38) || -> . % 76.16/76.40 201561[100:SSi:201560.0,78236.0,78240.0,192137.0,201316.0,201548.0] || -> . % 76.16/76.40 201562[100:Spt:201561.0,201553.0,201558.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.40 201563[100:Spt:201561.0,201553.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 201567[100:Res:201563.0,61.1] always3(s39) || -> . % 76.16/76.40 201568[100:SSi:201567.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.40 201569[98:Spt:201568.0,201315.0,201316.0] || until2p7(s38)*+ -> . % 76.16/76.40 201570[98:Spt:201568.0,201315.1] || -> node4(s37)*. % 76.16/76.40 201572[98:MRR:807.0,201570.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.40 201575[98:Res:53.1,201572.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.40 201577[99:Spt:201575.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 201579[99:Res:201577.0,61.1] always3(s37) || -> . % 76.16/76.40 201580[99:SSi:201579.0,78232.0,78235.0,192136.0,201314.0,201570.0] || -> . % 76.16/76.40 201581[99:Spt:201580.0,201575.0,201577.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.40 201582[99:Spt:201580.0,201575.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 201586[99:Res:201582.0,61.1] always3(s38) || -> . % 76.16/76.40 201587[99:SSi:201586.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.40 201588[97:Spt:201587.0,201313.0,201314.0] || until2p7(s37)*+ -> . % 76.16/76.40 201589[97:Spt:201587.0,201313.1] || -> node4(s36)*. % 76.16/76.40 201591[97:MRR:810.0,201589.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.40 201594[97:Res:53.1,201591.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.40 201596[98:Spt:201594.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 201598[98:Res:201596.0,61.1] always3(s36) || -> . % 76.16/76.40 201599[98:SSi:201598.0,78227.0,78231.0,192135.0,201312.0,201589.0] || -> . % 76.16/76.40 201600[98:Spt:201599.0,201594.0,201596.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.40 201601[98:Spt:201599.0,201594.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 201605[98:Res:201601.0,61.1] always3(s37) || -> . % 76.16/76.40 201606[98:SSi:201605.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.40 201607[96:Spt:201606.0,201311.0,201312.0] || until2p7(s36)*+ -> . % 76.16/76.40 201608[96:Spt:201606.0,201311.1] || -> node4(s35)*. % 76.16/76.40 201610[96:MRR:813.0,201608.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.40 201613[96:Res:53.1,201610.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.40 201615[97:Spt:201613.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 201617[97:Res:201615.0,61.1] always3(s35) || -> . % 76.16/76.40 201618[97:SSi:201617.0,78223.0,78226.0,192134.0,201310.0,201608.0] || -> . % 76.16/76.40 201619[97:Spt:201618.0,201613.0,201615.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.40 201620[97:Spt:201618.0,201613.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 201624[97:Res:201620.0,61.1] always3(s36) || -> . % 76.16/76.40 201625[97:SSi:201624.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.40 201626[95:Spt:201625.0,201309.0,201310.0] || until2p7(s35)*+ -> . % 76.16/76.40 201627[95:Spt:201625.0,201309.1] || -> node4(s34)*. % 76.16/76.40 201629[95:MRR:816.0,201627.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.40 201632[95:Res:53.1,201629.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.40 201637[96:Spt:201632.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 201639[96:Res:201637.0,61.1] always3(s34) || -> . % 76.16/76.40 201640[96:SSi:201639.0,78218.0,78222.0,192133.0,201308.0,201627.0] || -> . % 76.16/76.40 201641[96:Spt:201640.0,201632.0,201637.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.40 201642[96:Spt:201640.0,201632.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 201646[96:Res:201642.0,61.1] always3(s35) || -> . % 76.16/76.40 201647[96:SSi:201646.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.40 201648[94:Spt:201647.0,201307.0,201308.0] || until2p7(s34)*+ -> . % 76.16/76.40 201649[94:Spt:201647.0,201307.1] || -> node4(s33)*. % 76.16/76.40 201651[94:MRR:819.0,201649.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.40 201654[94:Res:53.1,201651.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.40 201656[95:Spt:201654.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 201658[95:Res:201656.0,61.1] always3(s33) || -> . % 76.16/76.40 201659[95:SSi:201658.0,78214.0,78217.0,192132.0,201306.0,201649.0] || -> . % 76.16/76.40 201660[95:Spt:201659.0,201654.0,201656.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.40 201661[95:Spt:201659.0,201654.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 201665[95:Res:201661.0,61.1] always3(s34) || -> . % 76.16/76.40 201666[95:SSi:201665.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.40 201667[93:Spt:201666.0,201305.0,201306.0] || until2p7(s33)*+ -> . % 76.16/76.40 201668[93:Spt:201666.0,201305.1] || -> node4(s32)*. % 76.16/76.40 201670[93:MRR:822.0,201668.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.40 201673[93:Res:53.1,201670.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.40 201675[94:Spt:201673.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 201677[94:Res:201675.0,61.1] always3(s32) || -> . % 76.16/76.40 201678[94:SSi:201677.0,78209.0,78213.0,192131.0,201304.0,201668.0] || -> . % 76.16/76.40 201679[94:Spt:201678.0,201673.0,201675.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.40 201680[94:Spt:201678.0,201673.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 201684[94:Res:201680.0,61.1] always3(s33) || -> . % 76.16/76.40 201685[94:SSi:201684.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.40 201686[92:Spt:201685.0,201303.0,201304.0] || until2p7(s32)*+ -> . % 76.16/76.40 201687[92:Spt:201685.0,201303.1] || -> node4(s31)*. % 76.16/76.40 201689[92:MRR:825.0,201687.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.40 201692[92:Res:53.1,201689.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.40 201694[93:Spt:201692.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 201696[93:Res:201694.0,61.1] always3(s31) || -> . % 76.16/76.40 201697[93:SSi:201696.0,78205.0,78208.0,192130.0,201302.0,201687.0] || -> . % 76.16/76.40 201698[93:Spt:201697.0,201692.0,201694.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.40 201699[93:Spt:201697.0,201692.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 201703[93:Res:201699.0,61.1] always3(s32) || -> . % 76.16/76.40 201704[93:SSi:201703.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.40 201705[91:Spt:201704.0,201301.0,201302.0] || until2p7(s31)*+ -> . % 76.16/76.40 201706[91:Spt:201704.0,201301.1] || -> node4(s30)*. % 76.16/76.40 201708[91:MRR:828.0,201706.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.40 201711[91:Res:53.1,201708.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.40 201716[92:Spt:201711.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 201718[92:Res:201716.0,61.1] always3(s30) || -> . % 76.16/76.40 201719[92:SSi:201718.0,78200.0,78204.0,192129.0,201300.0,201706.0] || -> . % 76.16/76.40 201720[92:Spt:201719.0,201711.0,201716.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.40 201721[92:Spt:201719.0,201711.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 201725[92:Res:201721.0,61.1] always3(s31) || -> . % 76.16/76.40 201726[92:SSi:201725.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.40 201727[90:Spt:201726.0,201299.0,201300.0] || until2p7(s30)*+ -> . % 76.16/76.40 201728[90:Spt:201726.0,201299.1] || -> node4(s29)*. % 76.16/76.40 201730[90:MRR:831.0,201728.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.40 201733[90:Res:53.1,201730.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.40 201735[91:Spt:201733.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 201737[91:Res:201735.0,61.1] always3(s29) || -> . % 76.16/76.40 201738[91:SSi:201737.0,78196.0,78199.0,192128.0,201298.0,201728.0] || -> . % 76.16/76.40 201739[91:Spt:201738.0,201733.0,201735.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.40 201740[91:Spt:201738.0,201733.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 201744[91:Res:201740.0,61.1] always3(s30) || -> . % 76.16/76.40 201745[91:SSi:201744.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.40 201746[89:Spt:201745.0,201297.0,201298.0] || until2p7(s29)*+ -> . % 76.16/76.40 201747[89:Spt:201745.0,201297.1] || -> node4(s28)*. % 76.16/76.40 201749[89:MRR:834.0,201747.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.40 201752[89:Res:53.1,201749.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.40 201754[90:Spt:201752.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 201756[90:Res:201754.0,61.1] always3(s28) || -> . % 76.16/76.40 201757[90:SSi:201756.0,78191.0,78195.0,192127.0,201296.0,201747.0] || -> . % 76.16/76.40 201758[90:Spt:201757.0,201752.0,201754.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.40 201759[90:Spt:201757.0,201752.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 201763[90:Res:201759.0,61.1] always3(s29) || -> . % 76.16/76.40 201764[90:SSi:201763.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.40 201765[88:Spt:201764.0,201295.0,201296.0] || until2p7(s28)*+ -> . % 76.16/76.40 201766[88:Spt:201764.0,201295.1] || -> node4(s27)*. % 76.16/76.40 201768[88:MRR:837.0,201766.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.40 201771[88:Res:53.1,201768.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.40 201773[89:Spt:201771.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 201775[89:Res:201773.0,61.1] always3(s27) || -> . % 76.16/76.40 201776[89:SSi:201775.0,78187.0,78190.0,192126.0,201294.0,201766.0] || -> . % 76.16/76.40 201777[89:Spt:201776.0,201771.0,201773.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.40 201778[89:Spt:201776.0,201771.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 201782[89:Res:201778.0,61.1] always3(s28) || -> . % 76.16/76.40 201783[89:SSi:201782.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.40 201784[87:Spt:201783.0,201293.0,201294.0] || until2p7(s27)*+ -> . % 76.16/76.40 201785[87:Spt:201783.0,201293.1] || -> node4(s26)*. % 76.16/76.40 201787[87:MRR:840.0,201785.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.40 201790[87:Res:53.1,201787.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.40 201795[88:Spt:201790.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 201797[88:Res:201795.0,61.1] always3(s26) || -> . % 76.16/76.40 201798[88:SSi:201797.0,78182.0,78186.0,192125.0,201292.0,201785.0] || -> . % 76.16/76.40 201799[88:Spt:201798.0,201790.0,201795.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.40 201800[88:Spt:201798.0,201790.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 201804[88:Res:201800.0,61.1] always3(s27) || -> . % 76.16/76.40 201805[88:SSi:201804.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.40 201806[86:Spt:201805.0,201291.0,201292.0] || until2p7(s26)*+ -> . % 76.16/76.40 201807[86:Spt:201805.0,201291.1] || -> node4(s25)*. % 76.16/76.40 201809[86:MRR:843.0,201807.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.40 201812[86:Res:53.1,201809.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.40 201814[87:Spt:201812.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 201816[87:Res:201814.0,61.1] always3(s25) || -> . % 76.16/76.40 201817[87:SSi:201816.0,78178.0,78181.0,192124.0,201290.0,201807.0] || -> . % 76.16/76.40 201818[87:Spt:201817.0,201812.0,201814.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.40 201819[87:Spt:201817.0,201812.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 201823[87:Res:201819.0,61.1] always3(s26) || -> . % 76.16/76.40 201824[87:SSi:201823.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.40 201825[85:Spt:201824.0,201289.0,201290.0] || until2p7(s25)*+ -> . % 76.16/76.40 201826[85:Spt:201824.0,201289.1] || -> node4(s24)*. % 76.16/76.40 201828[85:MRR:846.0,201826.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.40 201831[85:Res:53.1,201828.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.40 201833[86:Spt:201831.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 201835[86:Res:201833.0,61.1] always3(s24) || -> . % 76.16/76.40 201836[86:SSi:201835.0,78173.0,78177.0,192123.0,201288.0,201826.0] || -> . % 76.16/76.40 201837[86:Spt:201836.0,201831.0,201833.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.40 201838[86:Spt:201836.0,201831.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 201842[86:Res:201838.0,61.1] always3(s25) || -> . % 76.16/76.40 201843[86:SSi:201842.0,78178.0,78181.0,192124.0] || -> . % 76.16/76.40 201844[84:Spt:201843.0,201287.0,201288.0] || until2p7(s24)*+ -> . % 76.16/76.40 201845[84:Spt:201843.0,201287.1] || -> node4(s23)*. % 76.16/76.40 201847[84:MRR:849.0,201845.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.40 201850[84:Res:53.1,201847.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.40 201852[84:MRR:201850.0,201277.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 201854[84:Res:201852.0,61.1] always3(s24) || -> . % 76.16/76.40 201855[84:SSi:201854.0,78173.0,78177.0,192123.0] || -> . % 76.16/76.40 201856[82:Spt:201855.0,201172.0,201175.0] || trans(s49,s23)*+ -> . % 76.16/76.40 201857[82:Spt:201855.0,201172.1,201172.2,201172.3,201172.4,201172.5,201172.6,201172.7,201172.8,201172.9,201172.10,201172.11,201172.12,201172.13,201172.14,201172.15,201172.16,201172.17] || -> trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.40 201859[82:MRR:201174.1,201856.0] xuntil6(s49) || -> trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.40 201860[83:Spt:201857.0] || -> trans(s49,s22)*. % 76.16/76.40 201861[83:Res:201860.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s22)*. % 76.16/76.40 201863[83:Res:201860.0,60.0] || -> node2(s49,s22)*. % 76.16/76.40 201864[83:SSi:201861.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s22)*. % 76.16/76.40 201865[83:Res:201863.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 201958[83:SoR:201865.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 201960[83:SoR:201958.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s22,c_busy)* xuntil6(s49). % 76.16/76.40 201961[83:SSi:201960.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s22,c_busy)* xuntil6(s49). % 76.16/76.40 201962[84:Spt:201961.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 201964[84:Res:201962.0,61.1] always3(s22) || -> . % 76.16/76.40 201965[84:SSi:201964.0,78164.0,78168.0,192121.0] || -> . % 76.16/76.40 201966[84:Spt:201965.0,201961.1,201962.0] || m_main_v_state(s22,c_busy)*+ -> . % 76.16/76.40 201967[84:Spt:201965.0,201961.0,201961.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.40 201971[84:MRR:201958.2,201966.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.40 201972[84:Res:53.1,201967.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.40 201974[84:MRR:201972.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.40 201975[84:MRR:201864.0,201974.0] || -> until2p7(s22)*. % 76.16/76.40 201976[84:MRR:218.0,201975.0] || -> until2p7(s23)* node4(s22). % 76.16/76.40 201977[85:Spt:201976.0] || -> until2p7(s23)*. % 76.16/76.40 201978[85:MRR:219.0,201977.0] || -> until2p7(s24)* node4(s23). % 76.16/76.40 201979[86:Spt:201978.0] || -> until2p7(s24)*. % 76.16/76.40 201980[86:MRR:220.0,201979.0] || -> until2p7(s25)* node4(s24). % 76.16/76.40 201981[87:Spt:201980.0] || -> until2p7(s25)*. % 76.16/76.40 201982[87:MRR:221.0,201981.0] || -> until2p7(s26)* node4(s25). % 76.16/76.40 201983[88:Spt:201982.0] || -> until2p7(s26)*. % 76.16/76.40 201984[88:MRR:222.0,201983.0] || -> until2p7(s27)* node4(s26). % 76.16/76.40 201985[89:Spt:201984.0] || -> until2p7(s27)*. % 76.16/76.40 201986[89:MRR:223.0,201985.0] || -> until2p7(s28)* node4(s27). % 76.16/76.40 201987[90:Spt:201986.0] || -> until2p7(s28)*. % 76.16/76.40 201988[90:MRR:224.0,201987.0] || -> until2p7(s29)* node4(s28). % 76.16/76.40 201989[91:Spt:201988.0] || -> until2p7(s29)*. % 76.16/76.40 201990[91:MRR:225.0,201989.0] || -> until2p7(s30)* node4(s29). % 76.16/76.40 201991[92:Spt:201990.0] || -> until2p7(s30)*. % 76.16/76.40 201992[92:MRR:226.0,201991.0] || -> until2p7(s31)* node4(s30). % 76.16/76.40 201993[93:Spt:201992.0] || -> until2p7(s31)*. % 76.16/76.40 201994[93:MRR:227.0,201993.0] || -> until2p7(s32)* node4(s31). % 76.16/76.40 201995[94:Spt:201994.0] || -> until2p7(s32)*. % 76.16/76.40 201996[94:MRR:228.0,201995.0] || -> until2p7(s33)* node4(s32). % 76.16/76.40 201997[95:Spt:201996.0] || -> until2p7(s33)*. % 76.16/76.40 201998[95:MRR:229.0,201997.0] || -> until2p7(s34)* node4(s33). % 76.16/76.40 201999[96:Spt:201998.0] || -> until2p7(s34)*. % 76.16/76.40 202000[96:MRR:230.0,201999.0] || -> until2p7(s35)* node4(s34). % 76.16/76.40 202001[97:Spt:202000.0] || -> until2p7(s35)*. % 76.16/76.40 202002[97:MRR:231.0,202001.0] || -> until2p7(s36)* node4(s35). % 76.16/76.40 202003[98:Spt:202002.0] || -> until2p7(s36)*. % 76.16/76.40 202004[98:MRR:232.0,202003.0] || -> until2p7(s37)* node4(s36). % 76.16/76.40 202005[99:Spt:202004.0] || -> until2p7(s37)*. % 76.16/76.40 202006[99:MRR:235.0,202005.0] || -> until2p7(s38)* node4(s37). % 76.16/76.40 202007[100:Spt:202006.0] || -> until2p7(s38)*. % 76.16/76.40 202008[100:MRR:236.0,202007.0] || -> until2p7(s39)* node4(s38). % 76.16/76.40 202009[101:Spt:202008.0] || -> until2p7(s39)*. % 76.16/76.40 202010[101:MRR:237.0,202009.0] || -> until2p7(s40)* node4(s39). % 76.16/76.40 202011[102:Spt:202010.0] || -> until2p7(s40)*. % 76.16/76.40 202012[102:MRR:238.0,202011.0] || -> until2p7(s41)* node4(s40). % 76.16/76.40 202013[103:Spt:202012.0] || -> until2p7(s41)*. % 76.16/76.40 202014[103:MRR:239.0,202013.0] || -> until2p7(s42)* node4(s41). % 76.16/76.40 202015[104:Spt:202014.0] || -> until2p7(s42)*. % 76.16/76.40 202016[104:MRR:240.0,202015.0] || -> until2p7(s43)* node4(s42). % 76.16/76.40 202017[105:Spt:202016.0] || -> until2p7(s43)*. % 76.16/76.40 202018[105:MRR:241.0,202017.0] || -> until2p7(s44)* node4(s43). % 76.16/76.40 202019[106:Spt:202018.0] || -> until2p7(s44)*. % 76.16/76.40 202020[106:MRR:539.0,202019.0] || -> until2p7(s45)* node4(s44). % 76.16/76.40 202021[107:Spt:202020.0] || -> until2p7(s45)*. % 76.16/76.40 202022[107:MRR:544.0,202021.0] || -> until2p7(s46)* node4(s45). % 76.16/76.40 202023[108:Spt:202022.0] || -> until2p7(s46)*. % 76.16/76.40 202024[108:MRR:549.0,202023.0] || -> until2p7(s47)* node4(s46). % 76.16/76.40 202025[109:Spt:202024.0] || -> until2p7(s47)*. % 76.16/76.40 202026[109:MRR:554.0,202025.0] || -> until2p7(s48)* node4(s47). % 76.16/76.40 202027[110:Spt:202026.0] || -> until2p7(s48)*. % 76.16/76.40 202028[110:MRR:559.0,202027.0] || -> until2p7(s49)* node4(s48). % 76.16/76.40 202029[111:Spt:202028.0] || -> until2p7(s49)*. % 76.16/76.40 202030[111:MRR:194.0,202029.0] || -> node4(s49)*. % 76.16/76.40 202031[111:MRR:201971.0,202030.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.40 202032[111:Res:53.1,202031.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.40 202034[111:MRR:202032.0,78381.0] || -> . % 76.16/76.40 202035[111:Spt:202034.0,202028.0,202029.0] || until2p7(s49)*+ -> . % 76.16/76.40 202036[111:Spt:202034.0,202028.1] || -> node4(s48)*. % 76.16/76.40 202037[111:MRR:78384.0,202036.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.40 202040[111:Res:53.1,202037.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 202043[111:Res:202040.0,61.1] always3(s48) || -> . % 76.16/76.40 202044[111:SSi:202043.0,78281.0,78387.0,192147.0,202027.0,202036.0] || -> . % 76.16/76.40 202045[110:Spt:202044.0,202026.0,202027.0] || until2p7(s48)*+ -> . % 76.16/76.40 202046[110:Spt:202044.0,202026.1] || -> node4(s47)*. % 76.16/76.40 202048[110:MRR:777.0,202046.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.40 202063[110:Res:53.1,202048.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.40 202068[111:Spt:202063.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 202070[111:Res:202068.0,61.1] always3(s47) || -> . % 76.16/76.40 202071[111:SSi:202070.0,78277.0,78280.0,192146.0,202025.0,202046.0] || -> . % 76.16/76.40 202072[111:Spt:202071.0,202063.0,202068.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.40 202073[111:Spt:202071.0,202063.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 202077[111:Res:202073.0,61.1] always3(s48) || -> . % 76.16/76.40 202078[111:SSi:202077.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.40 202079[109:Spt:202078.0,202024.0,202025.0] || until2p7(s47)*+ -> . % 76.16/76.40 202080[109:Spt:202078.0,202024.1] || -> node4(s46)*. % 76.16/76.40 202082[109:MRR:780.0,202080.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.40 202089[109:Res:53.1,202082.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.40 202091[110:Spt:202089.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 202093[110:Res:202091.0,61.1] always3(s46) || -> . % 76.16/76.40 202094[110:SSi:202093.0,78272.0,78276.0,192145.0,202023.0,202080.0] || -> . % 76.16/76.40 202095[110:Spt:202094.0,202089.0,202091.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.40 202096[110:Spt:202094.0,202089.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 202100[110:Res:202096.0,61.1] always3(s47) || -> . % 76.16/76.40 202101[110:SSi:202100.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.40 202102[108:Spt:202101.0,202022.0,202023.0] || until2p7(s46)*+ -> . % 76.16/76.40 202103[108:Spt:202101.0,202022.1] || -> node4(s45)*. % 76.16/76.40 202105[108:MRR:783.0,202103.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.40 202108[108:Res:53.1,202105.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.40 202113[109:Spt:202108.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 202115[109:Res:202113.0,61.1] always3(s45) || -> . % 76.16/76.40 202116[109:SSi:202115.0,78268.0,78271.0,192144.0,202021.0,202103.0] || -> . % 76.16/76.40 202117[109:Spt:202116.0,202108.0,202113.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.40 202118[109:Spt:202116.0,202108.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 202122[109:Res:202118.0,61.1] always3(s46) || -> . % 76.16/76.40 202123[109:SSi:202122.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.40 202124[107:Spt:202123.0,202020.0,202021.0] || until2p7(s45)*+ -> . % 76.16/76.40 202125[107:Spt:202123.0,202020.1] || -> node4(s44)*. % 76.16/76.40 202127[107:MRR:786.0,202125.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.40 202130[107:Res:53.1,202127.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.40 202132[108:Spt:202130.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 202134[108:Res:202132.0,61.1] always3(s44) || -> . % 76.16/76.40 202135[108:SSi:202134.0,78263.0,78267.0,192143.0,202019.0,202125.0] || -> . % 76.16/76.40 202136[108:Spt:202135.0,202130.0,202132.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.40 202137[108:Spt:202135.0,202130.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 202141[108:Res:202137.0,61.1] always3(s45) || -> . % 76.16/76.40 202142[108:SSi:202141.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.40 202143[106:Spt:202142.0,202018.0,202019.0] || until2p7(s44)*+ -> . % 76.16/76.40 202144[106:Spt:202142.0,202018.1] || -> node4(s43)*. % 76.16/76.40 202146[106:MRR:789.0,202144.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.40 202149[106:Res:53.1,202146.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.40 202151[107:Spt:202149.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 202153[107:Res:202151.0,61.1] always3(s43) || -> . % 76.16/76.40 202154[107:SSi:202153.0,78259.0,78262.0,192142.0,202017.0,202144.0] || -> . % 76.16/76.40 202155[107:Spt:202154.0,202149.0,202151.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.40 202156[107:Spt:202154.0,202149.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 202160[107:Res:202156.0,61.1] always3(s44) || -> . % 76.16/76.40 202161[107:SSi:202160.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.40 202162[105:Spt:202161.0,202016.0,202017.0] || until2p7(s43)*+ -> . % 76.16/76.40 202163[105:Spt:202161.0,202016.1] || -> node4(s42)*. % 76.16/76.40 202165[105:MRR:792.0,202163.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.40 202168[105:Res:53.1,202165.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.40 202170[106:Spt:202168.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 202172[106:Res:202170.0,61.1] always3(s42) || -> . % 76.16/76.40 202173[106:SSi:202172.0,78254.0,78258.0,192141.0,202015.0,202163.0] || -> . % 76.16/76.40 202174[106:Spt:202173.0,202168.0,202170.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.40 202175[106:Spt:202173.0,202168.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 202179[106:Res:202175.0,61.1] always3(s43) || -> . % 76.16/76.40 202180[106:SSi:202179.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.40 202181[104:Spt:202180.0,202014.0,202015.0] || until2p7(s42)*+ -> . % 76.16/76.40 202182[104:Spt:202180.0,202014.1] || -> node4(s41)*. % 76.16/76.40 202184[104:MRR:795.0,202182.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.40 202187[104:Res:53.1,202184.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.40 202192[105:Spt:202187.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 202194[105:Res:202192.0,61.1] always3(s41) || -> . % 76.16/76.40 202195[105:SSi:202194.0,78250.0,78253.0,192140.0,202013.0,202182.0] || -> . % 76.16/76.40 202196[105:Spt:202195.0,202187.0,202192.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.40 202197[105:Spt:202195.0,202187.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 202201[105:Res:202197.0,61.1] always3(s42) || -> . % 76.16/76.40 202202[105:SSi:202201.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.40 202203[103:Spt:202202.0,202012.0,202013.0] || until2p7(s41)*+ -> . % 76.16/76.40 202204[103:Spt:202202.0,202012.1] || -> node4(s40)*. % 76.16/76.40 202206[103:MRR:798.0,202204.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.40 202209[103:Res:53.1,202206.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.40 202211[104:Spt:202209.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 202213[104:Res:202211.0,61.1] always3(s40) || -> . % 76.16/76.40 202214[104:SSi:202213.0,78245.0,78249.0,192139.0,202011.0,202204.0] || -> . % 76.16/76.40 202215[104:Spt:202214.0,202209.0,202211.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.40 202216[104:Spt:202214.0,202209.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 202220[104:Res:202216.0,61.1] always3(s41) || -> . % 76.16/76.40 202221[104:SSi:202220.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.40 202222[102:Spt:202221.0,202010.0,202011.0] || until2p7(s40)*+ -> . % 76.16/76.40 202223[102:Spt:202221.0,202010.1] || -> node4(s39)*. % 76.16/76.40 202225[102:MRR:801.0,202223.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.40 202228[102:Res:53.1,202225.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.40 202230[103:Spt:202228.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 202232[103:Res:202230.0,61.1] always3(s39) || -> . % 76.16/76.40 202233[103:SSi:202232.0,78241.0,78244.0,192138.0,202009.0,202223.0] || -> . % 76.16/76.40 202234[103:Spt:202233.0,202228.0,202230.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.40 202235[103:Spt:202233.0,202228.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 202239[103:Res:202235.0,61.1] always3(s40) || -> . % 76.16/76.40 202240[103:SSi:202239.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.40 202241[101:Spt:202240.0,202008.0,202009.0] || until2p7(s39)*+ -> . % 76.16/76.40 202242[101:Spt:202240.0,202008.1] || -> node4(s38)*. % 76.16/76.40 202244[101:MRR:804.0,202242.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.40 202247[101:Res:53.1,202244.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.40 202249[102:Spt:202247.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 202251[102:Res:202249.0,61.1] always3(s38) || -> . % 76.16/76.40 202252[102:SSi:202251.0,78236.0,78240.0,192137.0,202007.0,202242.0] || -> . % 76.16/76.40 202253[102:Spt:202252.0,202247.0,202249.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.40 202254[102:Spt:202252.0,202247.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 202258[102:Res:202254.0,61.1] always3(s39) || -> . % 76.16/76.40 202259[102:SSi:202258.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.40 202260[100:Spt:202259.0,202006.0,202007.0] || until2p7(s38)*+ -> . % 76.16/76.40 202261[100:Spt:202259.0,202006.1] || -> node4(s37)*. % 76.16/76.40 202263[100:MRR:807.0,202261.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.40 202266[100:Res:53.1,202263.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.40 202271[101:Spt:202266.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 202273[101:Res:202271.0,61.1] always3(s37) || -> . % 76.16/76.40 202274[101:SSi:202273.0,78232.0,78235.0,192136.0,202005.0,202261.0] || -> . % 76.16/76.40 202275[101:Spt:202274.0,202266.0,202271.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.40 202276[101:Spt:202274.0,202266.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 202280[101:Res:202276.0,61.1] always3(s38) || -> . % 76.16/76.40 202281[101:SSi:202280.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.40 202282[99:Spt:202281.0,202004.0,202005.0] || until2p7(s37)*+ -> . % 76.16/76.40 202283[99:Spt:202281.0,202004.1] || -> node4(s36)*. % 76.16/76.40 202285[99:MRR:810.0,202283.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.40 202288[99:Res:53.1,202285.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.40 202290[100:Spt:202288.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 202292[100:Res:202290.0,61.1] always3(s36) || -> . % 76.16/76.40 202293[100:SSi:202292.0,78227.0,78231.0,192135.0,202003.0,202283.0] || -> . % 76.16/76.40 202294[100:Spt:202293.0,202288.0,202290.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.40 202295[100:Spt:202293.0,202288.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 202299[100:Res:202295.0,61.1] always3(s37) || -> . % 76.16/76.40 202300[100:SSi:202299.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.40 202301[98:Spt:202300.0,202002.0,202003.0] || until2p7(s36)*+ -> . % 76.16/76.40 202302[98:Spt:202300.0,202002.1] || -> node4(s35)*. % 76.16/76.40 202304[98:MRR:813.0,202302.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.40 202307[98:Res:53.1,202304.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.40 202309[99:Spt:202307.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 202311[99:Res:202309.0,61.1] always3(s35) || -> . % 76.16/76.40 202312[99:SSi:202311.0,78223.0,78226.0,192134.0,202001.0,202302.0] || -> . % 76.16/76.40 202313[99:Spt:202312.0,202307.0,202309.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.40 202314[99:Spt:202312.0,202307.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 202318[99:Res:202314.0,61.1] always3(s36) || -> . % 76.16/76.40 202319[99:SSi:202318.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.40 202320[97:Spt:202319.0,202000.0,202001.0] || until2p7(s35)*+ -> . % 76.16/76.40 202321[97:Spt:202319.0,202000.1] || -> node4(s34)*. % 76.16/76.40 202323[97:MRR:816.0,202321.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.40 202326[97:Res:53.1,202323.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.40 202328[98:Spt:202326.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 202330[98:Res:202328.0,61.1] always3(s34) || -> . % 76.16/76.40 202331[98:SSi:202330.0,78218.0,78222.0,192133.0,201999.0,202321.0] || -> . % 76.16/76.40 202332[98:Spt:202331.0,202326.0,202328.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.40 202333[98:Spt:202331.0,202326.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 202337[98:Res:202333.0,61.1] always3(s35) || -> . % 76.16/76.40 202338[98:SSi:202337.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.40 202339[96:Spt:202338.0,201998.0,201999.0] || until2p7(s34)*+ -> . % 76.16/76.40 202340[96:Spt:202338.0,201998.1] || -> node4(s33)*. % 76.16/76.40 202342[96:MRR:819.0,202340.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.40 202345[96:Res:53.1,202342.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.40 202350[97:Spt:202345.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 202352[97:Res:202350.0,61.1] always3(s33) || -> . % 76.16/76.40 202353[97:SSi:202352.0,78214.0,78217.0,192132.0,201997.0,202340.0] || -> . % 76.16/76.40 202354[97:Spt:202353.0,202345.0,202350.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.40 202355[97:Spt:202353.0,202345.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 202359[97:Res:202355.0,61.1] always3(s34) || -> . % 76.16/76.40 202360[97:SSi:202359.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.40 202361[95:Spt:202360.0,201996.0,201997.0] || until2p7(s33)*+ -> . % 76.16/76.40 202362[95:Spt:202360.0,201996.1] || -> node4(s32)*. % 76.16/76.40 202364[95:MRR:822.0,202362.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.40 202367[95:Res:53.1,202364.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.40 202369[96:Spt:202367.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 202371[96:Res:202369.0,61.1] always3(s32) || -> . % 76.16/76.40 202372[96:SSi:202371.0,78209.0,78213.0,192131.0,201995.0,202362.0] || -> . % 76.16/76.40 202373[96:Spt:202372.0,202367.0,202369.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.40 202374[96:Spt:202372.0,202367.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 202378[96:Res:202374.0,61.1] always3(s33) || -> . % 76.16/76.40 202379[96:SSi:202378.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.40 202380[94:Spt:202379.0,201994.0,201995.0] || until2p7(s32)*+ -> . % 76.16/76.40 202381[94:Spt:202379.0,201994.1] || -> node4(s31)*. % 76.16/76.40 202383[94:MRR:825.0,202381.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.40 202386[94:Res:53.1,202383.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.40 202388[95:Spt:202386.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 202390[95:Res:202388.0,61.1] always3(s31) || -> . % 76.16/76.40 202391[95:SSi:202390.0,78205.0,78208.0,192130.0,201993.0,202381.0] || -> . % 76.16/76.40 202392[95:Spt:202391.0,202386.0,202388.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.40 202393[95:Spt:202391.0,202386.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 202397[95:Res:202393.0,61.1] always3(s32) || -> . % 76.16/76.40 202398[95:SSi:202397.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.40 202399[93:Spt:202398.0,201992.0,201993.0] || until2p7(s31)*+ -> . % 76.16/76.40 202400[93:Spt:202398.0,201992.1] || -> node4(s30)*. % 76.16/76.40 202402[93:MRR:828.0,202400.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.40 202405[93:Res:53.1,202402.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.40 202407[94:Spt:202405.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 202409[94:Res:202407.0,61.1] always3(s30) || -> . % 76.16/76.40 202410[94:SSi:202409.0,78200.0,78204.0,192129.0,201991.0,202400.0] || -> . % 76.16/76.40 202411[94:Spt:202410.0,202405.0,202407.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.40 202412[94:Spt:202410.0,202405.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 202416[94:Res:202412.0,61.1] always3(s31) || -> . % 76.16/76.40 202417[94:SSi:202416.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.40 202418[92:Spt:202417.0,201990.0,201991.0] || until2p7(s30)*+ -> . % 76.16/76.40 202419[92:Spt:202417.0,201990.1] || -> node4(s29)*. % 76.16/76.40 202421[92:MRR:831.0,202419.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.40 202424[92:Res:53.1,202421.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.40 202429[93:Spt:202424.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 202431[93:Res:202429.0,61.1] always3(s29) || -> . % 76.16/76.40 202432[93:SSi:202431.0,78196.0,78199.0,192128.0,201989.0,202419.0] || -> . % 76.16/76.40 202433[93:Spt:202432.0,202424.0,202429.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.40 202434[93:Spt:202432.0,202424.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 202438[93:Res:202434.0,61.1] always3(s30) || -> . % 76.16/76.40 202439[93:SSi:202438.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.40 202440[91:Spt:202439.0,201988.0,201989.0] || until2p7(s29)*+ -> . % 76.16/76.40 202441[91:Spt:202439.0,201988.1] || -> node4(s28)*. % 76.16/76.40 202443[91:MRR:834.0,202441.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.40 202446[91:Res:53.1,202443.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.40 202448[92:Spt:202446.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 202450[92:Res:202448.0,61.1] always3(s28) || -> . % 76.16/76.40 202451[92:SSi:202450.0,78191.0,78195.0,192127.0,201987.0,202441.0] || -> . % 76.16/76.40 202452[92:Spt:202451.0,202446.0,202448.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.40 202453[92:Spt:202451.0,202446.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 202457[92:Res:202453.0,61.1] always3(s29) || -> . % 76.16/76.40 202458[92:SSi:202457.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.40 202459[90:Spt:202458.0,201986.0,201987.0] || until2p7(s28)*+ -> . % 76.16/76.40 202460[90:Spt:202458.0,201986.1] || -> node4(s27)*. % 76.16/76.40 202462[90:MRR:837.0,202460.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.40 202465[90:Res:53.1,202462.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.40 202467[91:Spt:202465.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 202469[91:Res:202467.0,61.1] always3(s27) || -> . % 76.16/76.40 202470[91:SSi:202469.0,78187.0,78190.0,192126.0,201985.0,202460.0] || -> . % 76.16/76.40 202471[91:Spt:202470.0,202465.0,202467.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.40 202472[91:Spt:202470.0,202465.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 202476[91:Res:202472.0,61.1] always3(s28) || -> . % 76.16/76.40 202477[91:SSi:202476.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.40 202478[89:Spt:202477.0,201984.0,201985.0] || until2p7(s27)*+ -> . % 76.16/76.40 202479[89:Spt:202477.0,201984.1] || -> node4(s26)*. % 76.16/76.40 202481[89:MRR:840.0,202479.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.40 202484[89:Res:53.1,202481.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.40 202486[90:Spt:202484.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 202488[90:Res:202486.0,61.1] always3(s26) || -> . % 76.16/76.40 202489[90:SSi:202488.0,78182.0,78186.0,192125.0,201983.0,202479.0] || -> . % 76.16/76.40 202490[90:Spt:202489.0,202484.0,202486.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.40 202491[90:Spt:202489.0,202484.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 202495[90:Res:202491.0,61.1] always3(s27) || -> . % 76.16/76.40 202496[90:SSi:202495.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.40 202497[88:Spt:202496.0,201982.0,201983.0] || until2p7(s26)*+ -> . % 76.16/76.40 202498[88:Spt:202496.0,201982.1] || -> node4(s25)*. % 76.16/76.40 202500[88:MRR:843.0,202498.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.40 202503[88:Res:53.1,202500.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.40 202508[89:Spt:202503.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 202510[89:Res:202508.0,61.1] always3(s25) || -> . % 76.16/76.40 202511[89:SSi:202510.0,78178.0,78181.0,192124.0,201981.0,202498.0] || -> . % 76.16/76.40 202512[89:Spt:202511.0,202503.0,202508.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.40 202513[89:Spt:202511.0,202503.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 202517[89:Res:202513.0,61.1] always3(s26) || -> . % 76.16/76.40 202518[89:SSi:202517.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.40 202519[87:Spt:202518.0,201980.0,201981.0] || until2p7(s25)*+ -> . % 76.16/76.40 202520[87:Spt:202518.0,201980.1] || -> node4(s24)*. % 76.16/76.40 202522[87:MRR:846.0,202520.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.40 202525[87:Res:53.1,202522.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.40 202527[88:Spt:202525.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 202529[88:Res:202527.0,61.1] always3(s24) || -> . % 76.16/76.40 202530[88:SSi:202529.0,78173.0,78177.0,192123.0,201979.0,202520.0] || -> . % 76.16/76.40 202531[88:Spt:202530.0,202525.0,202527.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.40 202532[88:Spt:202530.0,202525.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 202536[88:Res:202532.0,61.1] always3(s25) || -> . % 76.16/76.40 202537[88:SSi:202536.0,78178.0,78181.0,192124.0] || -> . % 76.16/76.40 202538[86:Spt:202537.0,201978.0,201979.0] || until2p7(s24)*+ -> . % 76.16/76.40 202539[86:Spt:202537.0,201978.1] || -> node4(s23)*. % 76.16/76.40 202541[86:MRR:849.0,202539.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.40 202544[86:Res:53.1,202541.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.40 202546[87:Spt:202544.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 202548[87:Res:202546.0,61.1] always3(s23) || -> . % 76.16/76.40 202549[87:SSi:202548.0,78169.0,78172.0,192122.0,201977.0,202539.0] || -> . % 76.16/76.40 202550[87:Spt:202549.0,202544.0,202546.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.40 202551[87:Spt:202549.0,202544.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 202555[87:Res:202551.0,61.1] always3(s24) || -> . % 76.16/76.40 202556[87:SSi:202555.0,78173.0,78177.0,192123.0] || -> . % 76.16/76.40 202557[85:Spt:202556.0,201976.0,201977.0] || until2p7(s23)*+ -> . % 76.16/76.40 202558[85:Spt:202556.0,201976.1] || -> node4(s22)*. % 76.16/76.40 202560[85:MRR:852.0,202558.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.40 202563[85:Res:53.1,202560.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.40 202565[85:MRR:202563.0,201966.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 202567[85:Res:202565.0,61.1] always3(s23) || -> . % 76.16/76.40 202568[85:SSi:202567.0,78169.0,78172.0,192122.0] || -> . % 76.16/76.40 202569[83:Spt:202568.0,201857.0,201860.0] || trans(s49,s22)*+ -> . % 76.16/76.40 202570[83:Spt:202568.0,201857.1,201857.2,201857.3,201857.4,201857.5,201857.6,201857.7,201857.8,201857.9,201857.10,201857.11,201857.12,201857.13,201857.14,201857.15,201857.16] || -> trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.40 202572[83:MRR:201859.1,202569.0] xuntil6(s49) || -> trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.40 202573[84:Spt:202570.0] || -> trans(s49,s21)*. % 76.16/76.40 202574[84:Res:202573.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s21)*. % 76.16/76.40 202576[84:Res:202573.0,60.0] || -> node2(s49,s21)*. % 76.16/76.40 202577[84:SSi:202574.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s21)*. % 76.16/76.40 202578[84:Res:202576.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 202672[84:SoR:202578.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 202674[84:SoR:202672.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s21,c_busy)* xuntil6(s49). % 76.16/76.40 202675[84:SSi:202674.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s21,c_busy)* xuntil6(s49). % 76.16/76.40 202676[85:Spt:202675.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 202678[85:Res:202676.0,61.1] always3(s21) || -> . % 76.16/76.40 202679[85:SSi:202678.0,78160.0,78163.0,192120.0] || -> . % 76.16/76.40 202680[85:Spt:202679.0,202675.1,202676.0] || m_main_v_state(s21,c_busy)*+ -> . % 76.16/76.40 202681[85:Spt:202679.0,202675.0,202675.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.40 202685[85:MRR:202672.2,202680.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.40 202686[85:Res:53.1,202681.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.40 202688[85:MRR:202686.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.40 202689[85:MRR:202577.0,202688.0] || -> until2p7(s21)*. % 76.16/76.40 202690[85:MRR:217.0,202689.0] || -> until2p7(s22)* node4(s21). % 76.16/76.40 202691[86:Spt:202690.0] || -> until2p7(s22)*. % 76.16/76.40 202692[86:MRR:218.0,202691.0] || -> until2p7(s23)* node4(s22). % 76.16/76.40 202693[87:Spt:202692.0] || -> until2p7(s23)*. % 76.16/76.40 202694[87:MRR:219.0,202693.0] || -> until2p7(s24)* node4(s23). % 76.16/76.40 202695[88:Spt:202694.0] || -> until2p7(s24)*. % 76.16/76.40 202696[88:MRR:220.0,202695.0] || -> until2p7(s25)* node4(s24). % 76.16/76.40 202697[89:Spt:202696.0] || -> until2p7(s25)*. % 76.16/76.40 202698[89:MRR:221.0,202697.0] || -> until2p7(s26)* node4(s25). % 76.16/76.40 202699[90:Spt:202698.0] || -> until2p7(s26)*. % 76.16/76.40 202700[90:MRR:222.0,202699.0] || -> until2p7(s27)* node4(s26). % 76.16/76.40 202701[91:Spt:202700.0] || -> until2p7(s27)*. % 76.16/76.40 202702[91:MRR:223.0,202701.0] || -> until2p7(s28)* node4(s27). % 76.16/76.40 202703[92:Spt:202702.0] || -> until2p7(s28)*. % 76.16/76.40 202704[92:MRR:224.0,202703.0] || -> until2p7(s29)* node4(s28). % 76.16/76.40 202705[93:Spt:202704.0] || -> until2p7(s29)*. % 76.16/76.40 202706[93:MRR:225.0,202705.0] || -> until2p7(s30)* node4(s29). % 76.16/76.40 202707[94:Spt:202706.0] || -> until2p7(s30)*. % 76.16/76.40 202708[94:MRR:226.0,202707.0] || -> until2p7(s31)* node4(s30). % 76.16/76.40 202709[95:Spt:202708.0] || -> until2p7(s31)*. % 76.16/76.40 202710[95:MRR:227.0,202709.0] || -> until2p7(s32)* node4(s31). % 76.16/76.40 202711[96:Spt:202710.0] || -> until2p7(s32)*. % 76.16/76.40 202712[96:MRR:228.0,202711.0] || -> until2p7(s33)* node4(s32). % 76.16/76.40 202713[97:Spt:202712.0] || -> until2p7(s33)*. % 76.16/76.40 202714[97:MRR:229.0,202713.0] || -> until2p7(s34)* node4(s33). % 76.16/76.40 202715[98:Spt:202714.0] || -> until2p7(s34)*. % 76.16/76.40 202716[98:MRR:230.0,202715.0] || -> until2p7(s35)* node4(s34). % 76.16/76.40 202717[99:Spt:202716.0] || -> until2p7(s35)*. % 76.16/76.40 202718[99:MRR:231.0,202717.0] || -> until2p7(s36)* node4(s35). % 76.16/76.40 202719[100:Spt:202718.0] || -> until2p7(s36)*. % 76.16/76.40 202720[100:MRR:232.0,202719.0] || -> until2p7(s37)* node4(s36). % 76.16/76.40 202721[101:Spt:202720.0] || -> until2p7(s37)*. % 76.16/76.40 202722[101:MRR:235.0,202721.0] || -> until2p7(s38)* node4(s37). % 76.16/76.40 202723[102:Spt:202722.0] || -> until2p7(s38)*. % 76.16/76.40 202724[102:MRR:236.0,202723.0] || -> until2p7(s39)* node4(s38). % 76.16/76.40 202725[103:Spt:202724.0] || -> until2p7(s39)*. % 76.16/76.40 202726[103:MRR:237.0,202725.0] || -> until2p7(s40)* node4(s39). % 76.16/76.40 202727[104:Spt:202726.0] || -> until2p7(s40)*. % 76.16/76.40 202728[104:MRR:238.0,202727.0] || -> until2p7(s41)* node4(s40). % 76.16/76.40 202729[105:Spt:202728.0] || -> until2p7(s41)*. % 76.16/76.40 202730[105:MRR:239.0,202729.0] || -> until2p7(s42)* node4(s41). % 76.16/76.40 202731[106:Spt:202730.0] || -> until2p7(s42)*. % 76.16/76.40 202732[106:MRR:240.0,202731.0] || -> until2p7(s43)* node4(s42). % 76.16/76.40 202733[107:Spt:202732.0] || -> until2p7(s43)*. % 76.16/76.40 202734[107:MRR:241.0,202733.0] || -> until2p7(s44)* node4(s43). % 76.16/76.40 202735[108:Spt:202734.0] || -> until2p7(s44)*. % 76.16/76.40 202736[108:MRR:539.0,202735.0] || -> until2p7(s45)* node4(s44). % 76.16/76.40 202737[109:Spt:202736.0] || -> until2p7(s45)*. % 76.16/76.40 202738[109:MRR:544.0,202737.0] || -> until2p7(s46)* node4(s45). % 76.16/76.40 202739[110:Spt:202738.0] || -> until2p7(s46)*. % 76.16/76.40 202740[110:MRR:549.0,202739.0] || -> until2p7(s47)* node4(s46). % 76.16/76.40 202741[111:Spt:202740.0] || -> until2p7(s47)*. % 76.16/76.40 202742[111:MRR:554.0,202741.0] || -> until2p7(s48)* node4(s47). % 76.16/76.40 202743[112:Spt:202742.0] || -> until2p7(s48)*. % 76.16/76.40 202744[112:MRR:559.0,202743.0] || -> until2p7(s49)* node4(s48). % 76.16/76.40 202745[113:Spt:202744.0] || -> until2p7(s49)*. % 76.16/76.40 202746[113:MRR:194.0,202745.0] || -> node4(s49)*. % 76.16/76.40 202747[113:MRR:202685.0,202746.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.40 202751[113:Res:53.1,202747.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.40 202753[113:MRR:202751.0,78381.0] || -> . % 76.16/76.40 202754[113:Spt:202753.0,202744.0,202745.0] || until2p7(s49)*+ -> . % 76.16/76.40 202755[113:Spt:202753.0,202744.1] || -> node4(s48)*. % 76.16/76.40 202756[113:MRR:78384.0,202755.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.40 202759[113:Res:53.1,202756.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 202762[113:Res:202759.0,61.1] always3(s48) || -> . % 76.16/76.40 202763[113:SSi:202762.0,78281.0,78387.0,192147.0,202743.0,202755.0] || -> . % 76.16/76.40 202764[112:Spt:202763.0,202742.0,202743.0] || until2p7(s48)*+ -> . % 76.16/76.40 202765[112:Spt:202763.0,202742.1] || -> node4(s47)*. % 76.16/76.40 202767[112:MRR:777.0,202765.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.40 202779[112:Res:53.1,202767.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.40 202781[113:Spt:202779.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 202783[113:Res:202781.0,61.1] always3(s47) || -> . % 76.16/76.40 202784[113:SSi:202783.0,78277.0,78280.0,192146.0,202741.0,202765.0] || -> . % 76.16/76.40 202785[113:Spt:202784.0,202779.0,202781.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.40 202786[113:Spt:202784.0,202779.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 202790[113:Res:202786.0,61.1] always3(s48) || -> . % 76.16/76.40 202791[113:SSi:202790.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.40 202792[111:Spt:202791.0,202740.0,202741.0] || until2p7(s47)*+ -> . % 76.16/76.40 202793[111:Spt:202791.0,202740.1] || -> node4(s46)*. % 76.16/76.40 202795[111:MRR:780.0,202793.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.40 202802[111:Res:53.1,202795.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.40 202807[112:Spt:202802.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 202809[112:Res:202807.0,61.1] always3(s46) || -> . % 76.16/76.40 202810[112:SSi:202809.0,78272.0,78276.0,192145.0,202739.0,202793.0] || -> . % 76.16/76.40 202811[112:Spt:202810.0,202802.0,202807.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.40 202812[112:Spt:202810.0,202802.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 202816[112:Res:202812.0,61.1] always3(s47) || -> . % 76.16/76.40 202817[112:SSi:202816.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.40 202818[110:Spt:202817.0,202738.0,202739.0] || until2p7(s46)*+ -> . % 76.16/76.40 202819[110:Spt:202817.0,202738.1] || -> node4(s45)*. % 76.16/76.40 202821[110:MRR:783.0,202819.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.40 202824[110:Res:53.1,202821.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.40 202826[111:Spt:202824.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 202828[111:Res:202826.0,61.1] always3(s45) || -> . % 76.16/76.40 202829[111:SSi:202828.0,78268.0,78271.0,192144.0,202737.0,202819.0] || -> . % 76.16/76.40 202830[111:Spt:202829.0,202824.0,202826.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.40 202831[111:Spt:202829.0,202824.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 202835[111:Res:202831.0,61.1] always3(s46) || -> . % 76.16/76.40 202836[111:SSi:202835.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.40 202837[109:Spt:202836.0,202736.0,202737.0] || until2p7(s45)*+ -> . % 76.16/76.40 202838[109:Spt:202836.0,202736.1] || -> node4(s44)*. % 76.16/76.40 202840[109:MRR:786.0,202838.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.40 202843[109:Res:53.1,202840.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.40 202845[110:Spt:202843.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 202847[110:Res:202845.0,61.1] always3(s44) || -> . % 76.16/76.40 202848[110:SSi:202847.0,78263.0,78267.0,192143.0,202735.0,202838.0] || -> . % 76.16/76.40 202849[110:Spt:202848.0,202843.0,202845.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.40 202850[110:Spt:202848.0,202843.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 202854[110:Res:202850.0,61.1] always3(s45) || -> . % 76.16/76.40 202855[110:SSi:202854.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.40 202856[108:Spt:202855.0,202734.0,202735.0] || until2p7(s44)*+ -> . % 76.16/76.40 202857[108:Spt:202855.0,202734.1] || -> node4(s43)*. % 76.16/76.40 202859[108:MRR:789.0,202857.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.40 202862[108:Res:53.1,202859.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.40 202864[109:Spt:202862.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 202866[109:Res:202864.0,61.1] always3(s43) || -> . % 76.16/76.40 202867[109:SSi:202866.0,78259.0,78262.0,192142.0,202733.0,202857.0] || -> . % 76.16/76.40 202868[109:Spt:202867.0,202862.0,202864.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.40 202869[109:Spt:202867.0,202862.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 202873[109:Res:202869.0,61.1] always3(s44) || -> . % 76.16/76.40 202874[109:SSi:202873.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.40 202875[107:Spt:202874.0,202732.0,202733.0] || until2p7(s43)*+ -> . % 76.16/76.40 202876[107:Spt:202874.0,202732.1] || -> node4(s42)*. % 76.16/76.40 202878[107:MRR:792.0,202876.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.40 202881[107:Res:53.1,202878.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.40 202886[108:Spt:202881.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 202888[108:Res:202886.0,61.1] always3(s42) || -> . % 76.16/76.40 202889[108:SSi:202888.0,78254.0,78258.0,192141.0,202731.0,202876.0] || -> . % 76.16/76.40 202890[108:Spt:202889.0,202881.0,202886.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.40 202891[108:Spt:202889.0,202881.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 202895[108:Res:202891.0,61.1] always3(s43) || -> . % 76.16/76.40 202896[108:SSi:202895.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.40 202897[106:Spt:202896.0,202730.0,202731.0] || until2p7(s42)*+ -> . % 76.16/76.40 202898[106:Spt:202896.0,202730.1] || -> node4(s41)*. % 76.16/76.40 202900[106:MRR:795.0,202898.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.40 202903[106:Res:53.1,202900.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.40 202905[107:Spt:202903.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 202907[107:Res:202905.0,61.1] always3(s41) || -> . % 76.16/76.40 202908[107:SSi:202907.0,78250.0,78253.0,192140.0,202729.0,202898.0] || -> . % 76.16/76.40 202909[107:Spt:202908.0,202903.0,202905.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.40 202910[107:Spt:202908.0,202903.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 202914[107:Res:202910.0,61.1] always3(s42) || -> . % 76.16/76.40 202915[107:SSi:202914.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.40 202916[105:Spt:202915.0,202728.0,202729.0] || until2p7(s41)*+ -> . % 76.16/76.40 202917[105:Spt:202915.0,202728.1] || -> node4(s40)*. % 76.16/76.40 202919[105:MRR:798.0,202917.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.40 202922[105:Res:53.1,202919.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.40 202924[106:Spt:202922.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 202926[106:Res:202924.0,61.1] always3(s40) || -> . % 76.16/76.40 202927[106:SSi:202926.0,78245.0,78249.0,192139.0,202727.0,202917.0] || -> . % 76.16/76.40 202928[106:Spt:202927.0,202922.0,202924.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.40 202929[106:Spt:202927.0,202922.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 202933[106:Res:202929.0,61.1] always3(s41) || -> . % 76.16/76.40 202934[106:SSi:202933.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.40 202935[104:Spt:202934.0,202726.0,202727.0] || until2p7(s40)*+ -> . % 76.16/76.40 202936[104:Spt:202934.0,202726.1] || -> node4(s39)*. % 76.16/76.40 202938[104:MRR:801.0,202936.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.40 202941[104:Res:53.1,202938.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.40 202943[105:Spt:202941.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 202945[105:Res:202943.0,61.1] always3(s39) || -> . % 76.16/76.40 202946[105:SSi:202945.0,78241.0,78244.0,192138.0,202725.0,202936.0] || -> . % 76.16/76.40 202947[105:Spt:202946.0,202941.0,202943.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.40 202948[105:Spt:202946.0,202941.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 202952[105:Res:202948.0,61.1] always3(s40) || -> . % 76.16/76.40 202953[105:SSi:202952.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.40 202954[103:Spt:202953.0,202724.0,202725.0] || until2p7(s39)*+ -> . % 76.16/76.40 202955[103:Spt:202953.0,202724.1] || -> node4(s38)*. % 76.16/76.40 202957[103:MRR:804.0,202955.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.40 202960[103:Res:53.1,202957.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.40 202965[104:Spt:202960.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 202967[104:Res:202965.0,61.1] always3(s38) || -> . % 76.16/76.40 202968[104:SSi:202967.0,78236.0,78240.0,192137.0,202723.0,202955.0] || -> . % 76.16/76.40 202969[104:Spt:202968.0,202960.0,202965.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.40 202970[104:Spt:202968.0,202960.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 202974[104:Res:202970.0,61.1] always3(s39) || -> . % 76.16/76.40 202975[104:SSi:202974.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.40 202976[102:Spt:202975.0,202722.0,202723.0] || until2p7(s38)*+ -> . % 76.16/76.40 202977[102:Spt:202975.0,202722.1] || -> node4(s37)*. % 76.16/76.40 202979[102:MRR:807.0,202977.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.40 202982[102:Res:53.1,202979.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.40 202984[103:Spt:202982.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 202986[103:Res:202984.0,61.1] always3(s37) || -> . % 76.16/76.40 202987[103:SSi:202986.0,78232.0,78235.0,192136.0,202721.0,202977.0] || -> . % 76.16/76.40 202988[103:Spt:202987.0,202982.0,202984.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.40 202989[103:Spt:202987.0,202982.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 202993[103:Res:202989.0,61.1] always3(s38) || -> . % 76.16/76.40 202994[103:SSi:202993.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.40 202995[101:Spt:202994.0,202720.0,202721.0] || until2p7(s37)*+ -> . % 76.16/76.40 202996[101:Spt:202994.0,202720.1] || -> node4(s36)*. % 76.16/76.40 202998[101:MRR:810.0,202996.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.40 203001[101:Res:53.1,202998.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.40 203003[102:Spt:203001.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 203005[102:Res:203003.0,61.1] always3(s36) || -> . % 76.16/76.40 203006[102:SSi:203005.0,78227.0,78231.0,192135.0,202719.0,202996.0] || -> . % 76.16/76.40 203007[102:Spt:203006.0,203001.0,203003.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.40 203008[102:Spt:203006.0,203001.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 203012[102:Res:203008.0,61.1] always3(s37) || -> . % 76.16/76.40 203013[102:SSi:203012.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.40 203014[100:Spt:203013.0,202718.0,202719.0] || until2p7(s36)*+ -> . % 76.16/76.40 203015[100:Spt:203013.0,202718.1] || -> node4(s35)*. % 76.16/76.40 203017[100:MRR:813.0,203015.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.40 203020[100:Res:53.1,203017.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.40 203022[101:Spt:203020.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 203024[101:Res:203022.0,61.1] always3(s35) || -> . % 76.16/76.40 203025[101:SSi:203024.0,78223.0,78226.0,192134.0,202717.0,203015.0] || -> . % 76.16/76.40 203026[101:Spt:203025.0,203020.0,203022.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.40 203027[101:Spt:203025.0,203020.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 203031[101:Res:203027.0,61.1] always3(s36) || -> . % 76.16/76.40 203032[101:SSi:203031.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.40 203033[99:Spt:203032.0,202716.0,202717.0] || until2p7(s35)*+ -> . % 76.16/76.40 203034[99:Spt:203032.0,202716.1] || -> node4(s34)*. % 76.16/76.40 203036[99:MRR:816.0,203034.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.40 203039[99:Res:53.1,203036.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.40 203044[100:Spt:203039.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 203046[100:Res:203044.0,61.1] always3(s34) || -> . % 76.16/76.40 203047[100:SSi:203046.0,78218.0,78222.0,192133.0,202715.0,203034.0] || -> . % 76.16/76.40 203048[100:Spt:203047.0,203039.0,203044.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.40 203049[100:Spt:203047.0,203039.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 203053[100:Res:203049.0,61.1] always3(s35) || -> . % 76.16/76.40 203054[100:SSi:203053.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.40 203055[98:Spt:203054.0,202714.0,202715.0] || until2p7(s34)*+ -> . % 76.16/76.40 203056[98:Spt:203054.0,202714.1] || -> node4(s33)*. % 76.16/76.40 203058[98:MRR:819.0,203056.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.40 203061[98:Res:53.1,203058.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.40 203063[99:Spt:203061.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 203065[99:Res:203063.0,61.1] always3(s33) || -> . % 76.16/76.40 203066[99:SSi:203065.0,78214.0,78217.0,192132.0,202713.0,203056.0] || -> . % 76.16/76.40 203067[99:Spt:203066.0,203061.0,203063.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.40 203068[99:Spt:203066.0,203061.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 203072[99:Res:203068.0,61.1] always3(s34) || -> . % 76.16/76.40 203073[99:SSi:203072.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.40 203074[97:Spt:203073.0,202712.0,202713.0] || until2p7(s33)*+ -> . % 76.16/76.40 203075[97:Spt:203073.0,202712.1] || -> node4(s32)*. % 76.16/76.40 203077[97:MRR:822.0,203075.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.40 203080[97:Res:53.1,203077.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.40 203082[98:Spt:203080.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 203084[98:Res:203082.0,61.1] always3(s32) || -> . % 76.16/76.40 203085[98:SSi:203084.0,78209.0,78213.0,192131.0,202711.0,203075.0] || -> . % 76.16/76.40 203086[98:Spt:203085.0,203080.0,203082.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.40 203087[98:Spt:203085.0,203080.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 203091[98:Res:203087.0,61.1] always3(s33) || -> . % 76.16/76.40 203092[98:SSi:203091.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.40 203093[96:Spt:203092.0,202710.0,202711.0] || until2p7(s32)*+ -> . % 76.16/76.40 203094[96:Spt:203092.0,202710.1] || -> node4(s31)*. % 76.16/76.40 203096[96:MRR:825.0,203094.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.40 203099[96:Res:53.1,203096.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.40 203101[97:Spt:203099.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 203103[97:Res:203101.0,61.1] always3(s31) || -> . % 76.16/76.40 203104[97:SSi:203103.0,78205.0,78208.0,192130.0,202709.0,203094.0] || -> . % 76.16/76.40 203105[97:Spt:203104.0,203099.0,203101.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.40 203106[97:Spt:203104.0,203099.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 203110[97:Res:203106.0,61.1] always3(s32) || -> . % 76.16/76.40 203111[97:SSi:203110.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.40 203112[95:Spt:203111.0,202708.0,202709.0] || until2p7(s31)*+ -> . % 76.16/76.40 203113[95:Spt:203111.0,202708.1] || -> node4(s30)*. % 76.16/76.40 203115[95:MRR:828.0,203113.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.40 203118[95:Res:53.1,203115.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.40 203123[96:Spt:203118.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 203125[96:Res:203123.0,61.1] always3(s30) || -> . % 76.16/76.40 203126[96:SSi:203125.0,78200.0,78204.0,192129.0,202707.0,203113.0] || -> . % 76.16/76.40 203127[96:Spt:203126.0,203118.0,203123.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.40 203128[96:Spt:203126.0,203118.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 203132[96:Res:203128.0,61.1] always3(s31) || -> . % 76.16/76.40 203133[96:SSi:203132.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.40 203134[94:Spt:203133.0,202706.0,202707.0] || until2p7(s30)*+ -> . % 76.16/76.40 203135[94:Spt:203133.0,202706.1] || -> node4(s29)*. % 76.16/76.40 203137[94:MRR:831.0,203135.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.40 203140[94:Res:53.1,203137.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.40 203142[95:Spt:203140.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 203144[95:Res:203142.0,61.1] always3(s29) || -> . % 76.16/76.40 203145[95:SSi:203144.0,78196.0,78199.0,192128.0,202705.0,203135.0] || -> . % 76.16/76.40 203146[95:Spt:203145.0,203140.0,203142.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.40 203147[95:Spt:203145.0,203140.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 203151[95:Res:203147.0,61.1] always3(s30) || -> . % 76.16/76.40 203152[95:SSi:203151.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.40 203153[93:Spt:203152.0,202704.0,202705.0] || until2p7(s29)*+ -> . % 76.16/76.40 203154[93:Spt:203152.0,202704.1] || -> node4(s28)*. % 76.16/76.40 203156[93:MRR:834.0,203154.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.40 203159[93:Res:53.1,203156.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.40 203161[94:Spt:203159.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 203163[94:Res:203161.0,61.1] always3(s28) || -> . % 76.16/76.40 203164[94:SSi:203163.0,78191.0,78195.0,192127.0,202703.0,203154.0] || -> . % 76.16/76.40 203165[94:Spt:203164.0,203159.0,203161.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.40 203166[94:Spt:203164.0,203159.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 203170[94:Res:203166.0,61.1] always3(s29) || -> . % 76.16/76.40 203171[94:SSi:203170.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.40 203172[92:Spt:203171.0,202702.0,202703.0] || until2p7(s28)*+ -> . % 76.16/76.40 203173[92:Spt:203171.0,202702.1] || -> node4(s27)*. % 76.16/76.40 203175[92:MRR:837.0,203173.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.40 203178[92:Res:53.1,203175.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.40 203180[93:Spt:203178.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 203182[93:Res:203180.0,61.1] always3(s27) || -> . % 76.16/76.40 203183[93:SSi:203182.0,78187.0,78190.0,192126.0,202701.0,203173.0] || -> . % 76.16/76.40 203184[93:Spt:203183.0,203178.0,203180.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.40 203185[93:Spt:203183.0,203178.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 203189[93:Res:203185.0,61.1] always3(s28) || -> . % 76.16/76.40 203190[93:SSi:203189.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.40 203191[91:Spt:203190.0,202700.0,202701.0] || until2p7(s27)*+ -> . % 76.16/76.40 203192[91:Spt:203190.0,202700.1] || -> node4(s26)*. % 76.16/76.40 203194[91:MRR:840.0,203192.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.40 203197[91:Res:53.1,203194.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.40 203202[92:Spt:203197.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 203204[92:Res:203202.0,61.1] always3(s26) || -> . % 76.16/76.40 203205[92:SSi:203204.0,78182.0,78186.0,192125.0,202699.0,203192.0] || -> . % 76.16/76.40 203206[92:Spt:203205.0,203197.0,203202.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.40 203207[92:Spt:203205.0,203197.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 203211[92:Res:203207.0,61.1] always3(s27) || -> . % 76.16/76.40 203212[92:SSi:203211.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.40 203213[90:Spt:203212.0,202698.0,202699.0] || until2p7(s26)*+ -> . % 76.16/76.40 203214[90:Spt:203212.0,202698.1] || -> node4(s25)*. % 76.16/76.40 203216[90:MRR:843.0,203214.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.40 203219[90:Res:53.1,203216.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.40 203221[91:Spt:203219.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 203223[91:Res:203221.0,61.1] always3(s25) || -> . % 76.16/76.40 203224[91:SSi:203223.0,78178.0,78181.0,192124.0,202697.0,203214.0] || -> . % 76.16/76.40 203225[91:Spt:203224.0,203219.0,203221.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.40 203226[91:Spt:203224.0,203219.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 203230[91:Res:203226.0,61.1] always3(s26) || -> . % 76.16/76.40 203231[91:SSi:203230.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.40 203232[89:Spt:203231.0,202696.0,202697.0] || until2p7(s25)*+ -> . % 76.16/76.40 203233[89:Spt:203231.0,202696.1] || -> node4(s24)*. % 76.16/76.40 203235[89:MRR:846.0,203233.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.40 203238[89:Res:53.1,203235.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.40 203240[90:Spt:203238.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 203242[90:Res:203240.0,61.1] always3(s24) || -> . % 76.16/76.40 203243[90:SSi:203242.0,78173.0,78177.0,192123.0,202695.0,203233.0] || -> . % 76.16/76.40 203244[90:Spt:203243.0,203238.0,203240.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.40 203245[90:Spt:203243.0,203238.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 203249[90:Res:203245.0,61.1] always3(s25) || -> . % 76.16/76.40 203250[90:SSi:203249.0,78178.0,78181.0,192124.0] || -> . % 76.16/76.40 203251[88:Spt:203250.0,202694.0,202695.0] || until2p7(s24)*+ -> . % 76.16/76.40 203252[88:Spt:203250.0,202694.1] || -> node4(s23)*. % 76.16/76.40 203254[88:MRR:849.0,203252.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.40 203257[88:Res:53.1,203254.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.40 203259[89:Spt:203257.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 203261[89:Res:203259.0,61.1] always3(s23) || -> . % 76.16/76.40 203262[89:SSi:203261.0,78169.0,78172.0,192122.0,202693.0,203252.0] || -> . % 76.16/76.40 203263[89:Spt:203262.0,203257.0,203259.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.40 203264[89:Spt:203262.0,203257.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 203268[89:Res:203264.0,61.1] always3(s24) || -> . % 76.16/76.40 203269[89:SSi:203268.0,78173.0,78177.0,192123.0] || -> . % 76.16/76.40 203270[87:Spt:203269.0,202692.0,202693.0] || until2p7(s23)*+ -> . % 76.16/76.40 203271[87:Spt:203269.0,202692.1] || -> node4(s22)*. % 76.16/76.40 203273[87:MRR:852.0,203271.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.40 203276[87:Res:53.1,203273.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.40 203281[88:Spt:203276.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 203283[88:Res:203281.0,61.1] always3(s22) || -> . % 76.16/76.40 203284[88:SSi:203283.0,78164.0,78168.0,192121.0,202691.0,203271.0] || -> . % 76.16/76.40 203285[88:Spt:203284.0,203276.0,203281.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.40 203286[88:Spt:203284.0,203276.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 203290[88:Res:203286.0,61.1] always3(s23) || -> . % 76.16/76.40 203291[88:SSi:203290.0,78169.0,78172.0,192122.0] || -> . % 76.16/76.40 203292[86:Spt:203291.0,202690.0,202691.0] || until2p7(s22)*+ -> . % 76.16/76.40 203293[86:Spt:203291.0,202690.1] || -> node4(s21)*. % 76.16/76.40 203295[86:MRR:855.0,203293.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.40 203298[86:Res:53.1,203295.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.40 203300[86:MRR:203298.0,202680.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 203302[86:Res:203300.0,61.1] always3(s22) || -> . % 76.16/76.40 203303[86:SSi:203302.0,78164.0,78168.0,192121.0] || -> . % 76.16/76.40 203304[84:Spt:203303.0,202570.0,202573.0] || trans(s49,s21)*+ -> . % 76.16/76.40 203305[84:Spt:203303.0,202570.1,202570.2,202570.3,202570.4,202570.5,202570.6,202570.7,202570.8,202570.9,202570.10,202570.11,202570.12,202570.13,202570.14,202570.15] || -> trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.40 203307[84:MRR:202572.1,203304.0] xuntil6(s49) || -> trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.40 203308[85:Spt:203305.0] || -> trans(s49,s20)*. % 76.16/76.40 203309[85:Res:203308.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s20)*. % 76.16/76.40 203311[85:Res:203308.0,60.0] || -> node2(s49,s20)*. % 76.16/76.40 203312[85:SSi:203309.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s20)*. % 76.16/76.40 203313[85:Res:203311.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 203411[85:SoR:203313.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 203413[85:SoR:203411.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s20,c_busy)* xuntil6(s49). % 76.16/76.40 203414[85:SSi:203413.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s20,c_busy)* xuntil6(s49). % 76.16/76.40 203415[86:Spt:203414.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 203417[86:Res:203415.0,61.1] always3(s20) || -> . % 76.16/76.40 203418[86:SSi:203417.0,78155.0,78159.0,192119.0] || -> . % 76.16/76.40 203419[86:Spt:203418.0,203414.1,203415.0] || m_main_v_state(s20,c_busy)*+ -> . % 76.16/76.40 203420[86:Spt:203418.0,203414.0,203414.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.40 203424[86:MRR:203411.2,203419.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.40 203425[86:Res:53.1,203420.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.40 203427[86:MRR:203425.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.40 203428[86:MRR:203312.0,203427.0] || -> until2p7(s20)*. % 76.16/76.40 203429[86:MRR:216.0,203428.0] || -> until2p7(s21)* node4(s20). % 76.16/76.40 203430[87:Spt:203429.0] || -> until2p7(s21)*. % 76.16/76.40 203431[87:MRR:217.0,203430.0] || -> until2p7(s22)* node4(s21). % 76.16/76.40 203432[88:Spt:203431.0] || -> until2p7(s22)*. % 76.16/76.40 203433[88:MRR:218.0,203432.0] || -> until2p7(s23)* node4(s22). % 76.16/76.40 203434[89:Spt:203433.0] || -> until2p7(s23)*. % 76.16/76.40 203435[89:MRR:219.0,203434.0] || -> until2p7(s24)* node4(s23). % 76.16/76.40 203436[90:Spt:203435.0] || -> until2p7(s24)*. % 76.16/76.40 203437[90:MRR:220.0,203436.0] || -> until2p7(s25)* node4(s24). % 76.16/76.40 203438[91:Spt:203437.0] || -> until2p7(s25)*. % 76.16/76.40 203439[91:MRR:221.0,203438.0] || -> until2p7(s26)* node4(s25). % 76.16/76.40 203440[92:Spt:203439.0] || -> until2p7(s26)*. % 76.16/76.40 203441[92:MRR:222.0,203440.0] || -> until2p7(s27)* node4(s26). % 76.16/76.40 203442[93:Spt:203441.0] || -> until2p7(s27)*. % 76.16/76.40 203443[93:MRR:223.0,203442.0] || -> until2p7(s28)* node4(s27). % 76.16/76.40 203444[94:Spt:203443.0] || -> until2p7(s28)*. % 76.16/76.40 203445[94:MRR:224.0,203444.0] || -> until2p7(s29)* node4(s28). % 76.16/76.40 203446[95:Spt:203445.0] || -> until2p7(s29)*. % 76.16/76.40 203447[95:MRR:225.0,203446.0] || -> until2p7(s30)* node4(s29). % 76.16/76.40 203448[96:Spt:203447.0] || -> until2p7(s30)*. % 76.16/76.40 203449[96:MRR:226.0,203448.0] || -> until2p7(s31)* node4(s30). % 76.16/76.40 203450[97:Spt:203449.0] || -> until2p7(s31)*. % 76.16/76.40 203451[97:MRR:227.0,203450.0] || -> until2p7(s32)* node4(s31). % 76.16/76.40 203452[98:Spt:203451.0] || -> until2p7(s32)*. % 76.16/76.40 203453[98:MRR:228.0,203452.0] || -> until2p7(s33)* node4(s32). % 76.16/76.40 203454[99:Spt:203453.0] || -> until2p7(s33)*. % 76.16/76.40 203455[99:MRR:229.0,203454.0] || -> until2p7(s34)* node4(s33). % 76.16/76.40 203456[100:Spt:203455.0] || -> until2p7(s34)*. % 76.16/76.40 203457[100:MRR:230.0,203456.0] || -> until2p7(s35)* node4(s34). % 76.16/76.40 203458[101:Spt:203457.0] || -> until2p7(s35)*. % 76.16/76.40 203459[101:MRR:231.0,203458.0] || -> until2p7(s36)* node4(s35). % 76.16/76.40 203460[102:Spt:203459.0] || -> until2p7(s36)*. % 76.16/76.40 203461[102:MRR:232.0,203460.0] || -> until2p7(s37)* node4(s36). % 76.16/76.40 203462[103:Spt:203461.0] || -> until2p7(s37)*. % 76.16/76.40 203463[103:MRR:235.0,203462.0] || -> until2p7(s38)* node4(s37). % 76.16/76.40 203464[104:Spt:203463.0] || -> until2p7(s38)*. % 76.16/76.40 203465[104:MRR:236.0,203464.0] || -> until2p7(s39)* node4(s38). % 76.16/76.40 203466[105:Spt:203465.0] || -> until2p7(s39)*. % 76.16/76.40 203467[105:MRR:237.0,203466.0] || -> until2p7(s40)* node4(s39). % 76.16/76.40 203468[106:Spt:203467.0] || -> until2p7(s40)*. % 76.16/76.40 203469[106:MRR:238.0,203468.0] || -> until2p7(s41)* node4(s40). % 76.16/76.40 203470[107:Spt:203469.0] || -> until2p7(s41)*. % 76.16/76.40 203471[107:MRR:239.0,203470.0] || -> until2p7(s42)* node4(s41). % 76.16/76.40 203472[108:Spt:203471.0] || -> until2p7(s42)*. % 76.16/76.40 203473[108:MRR:240.0,203472.0] || -> until2p7(s43)* node4(s42). % 76.16/76.40 203474[109:Spt:203473.0] || -> until2p7(s43)*. % 76.16/76.40 203475[109:MRR:241.0,203474.0] || -> until2p7(s44)* node4(s43). % 76.16/76.40 203476[110:Spt:203475.0] || -> until2p7(s44)*. % 76.16/76.40 203477[110:MRR:539.0,203476.0] || -> until2p7(s45)* node4(s44). % 76.16/76.40 203478[111:Spt:203477.0] || -> until2p7(s45)*. % 76.16/76.40 203479[111:MRR:544.0,203478.0] || -> until2p7(s46)* node4(s45). % 76.16/76.40 203480[112:Spt:203479.0] || -> until2p7(s46)*. % 76.16/76.40 203481[112:MRR:549.0,203480.0] || -> until2p7(s47)* node4(s46). % 76.16/76.40 203482[113:Spt:203481.0] || -> until2p7(s47)*. % 76.16/76.40 203483[113:MRR:554.0,203482.0] || -> until2p7(s48)* node4(s47). % 76.16/76.40 203484[114:Spt:203483.0] || -> until2p7(s48)*. % 76.16/76.40 203485[114:MRR:559.0,203484.0] || -> until2p7(s49)* node4(s48). % 76.16/76.40 203486[115:Spt:203485.0] || -> until2p7(s49)*. % 76.16/76.40 203487[115:MRR:194.0,203486.0] || -> node4(s49)*. % 76.16/76.40 203488[115:MRR:203424.0,203487.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.40 203489[115:Res:53.1,203488.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.40 203491[115:MRR:203489.0,78381.0] || -> . % 76.16/76.40 203492[115:Spt:203491.0,203485.0,203486.0] || until2p7(s49)*+ -> . % 76.16/76.40 203493[115:Spt:203491.0,203485.1] || -> node4(s48)*. % 76.16/76.40 203494[115:MRR:78384.0,203493.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.40 203497[115:Res:53.1,203494.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 203500[115:Res:203497.0,61.1] always3(s48) || -> . % 76.16/76.40 203501[115:SSi:203500.0,78281.0,78387.0,192147.0,203484.0,203493.0] || -> . % 76.16/76.40 203502[114:Spt:203501.0,203483.0,203484.0] || until2p7(s48)*+ -> . % 76.16/76.40 203503[114:Spt:203501.0,203483.1] || -> node4(s47)*. % 76.16/76.40 203505[114:MRR:777.0,203503.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.40 203520[114:Res:53.1,203505.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.40 203522[115:Spt:203520.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 203524[115:Res:203522.0,61.1] always3(s47) || -> . % 76.16/76.40 203525[115:SSi:203524.0,78277.0,78280.0,192146.0,203482.0,203503.0] || -> . % 76.16/76.40 203526[115:Spt:203525.0,203520.0,203522.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.40 203527[115:Spt:203525.0,203520.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 203531[115:Res:203527.0,61.1] always3(s48) || -> . % 76.16/76.40 203532[115:SSi:203531.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.40 203533[113:Spt:203532.0,203481.0,203482.0] || until2p7(s47)*+ -> . % 76.16/76.40 203534[113:Spt:203532.0,203481.1] || -> node4(s46)*. % 76.16/76.40 203536[113:MRR:780.0,203534.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.40 203546[113:Res:53.1,203536.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.40 203548[114:Spt:203546.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 203550[114:Res:203548.0,61.1] always3(s46) || -> . % 76.16/76.40 203551[114:SSi:203550.0,78272.0,78276.0,192145.0,203480.0,203534.0] || -> . % 76.16/76.40 203552[114:Spt:203551.0,203546.0,203548.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.40 203553[114:Spt:203551.0,203546.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 203557[114:Res:203553.0,61.1] always3(s47) || -> . % 76.16/76.40 203558[114:SSi:203557.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.40 203559[112:Spt:203558.0,203479.0,203480.0] || until2p7(s46)*+ -> . % 76.16/76.40 203560[112:Spt:203558.0,203479.1] || -> node4(s45)*. % 76.16/76.40 203562[112:MRR:783.0,203560.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.40 203565[112:Res:53.1,203562.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.40 203567[113:Spt:203565.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 203569[113:Res:203567.0,61.1] always3(s45) || -> . % 76.16/76.40 203570[113:SSi:203569.0,78268.0,78271.0,192144.0,203478.0,203560.0] || -> . % 76.16/76.40 203571[113:Spt:203570.0,203565.0,203567.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.40 203572[113:Spt:203570.0,203565.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 203576[113:Res:203572.0,61.1] always3(s46) || -> . % 76.16/76.40 203577[113:SSi:203576.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.40 203578[111:Spt:203577.0,203477.0,203478.0] || until2p7(s45)*+ -> . % 76.16/76.40 203579[111:Spt:203577.0,203477.1] || -> node4(s44)*. % 76.16/76.40 203581[111:MRR:786.0,203579.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.40 203584[111:Res:53.1,203581.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.40 203586[112:Spt:203584.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 203588[112:Res:203586.0,61.1] always3(s44) || -> . % 76.16/76.40 203589[112:SSi:203588.0,78263.0,78267.0,192143.0,203476.0,203579.0] || -> . % 76.16/76.40 203590[112:Spt:203589.0,203584.0,203586.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.40 203591[112:Spt:203589.0,203584.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 203595[112:Res:203591.0,61.1] always3(s45) || -> . % 76.16/76.40 203596[112:SSi:203595.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.40 203597[110:Spt:203596.0,203475.0,203476.0] || until2p7(s44)*+ -> . % 76.16/76.40 203598[110:Spt:203596.0,203475.1] || -> node4(s43)*. % 76.16/76.40 203600[110:MRR:789.0,203598.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.40 203603[110:Res:53.1,203600.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.40 203608[111:Spt:203603.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 203610[111:Res:203608.0,61.1] always3(s43) || -> . % 76.16/76.40 203611[111:SSi:203610.0,78259.0,78262.0,192142.0,203474.0,203598.0] || -> . % 76.16/76.40 203612[111:Spt:203611.0,203603.0,203608.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.40 203613[111:Spt:203611.0,203603.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 203617[111:Res:203613.0,61.1] always3(s44) || -> . % 76.16/76.40 203618[111:SSi:203617.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.40 203619[109:Spt:203618.0,203473.0,203474.0] || until2p7(s43)*+ -> . % 76.16/76.40 203620[109:Spt:203618.0,203473.1] || -> node4(s42)*. % 76.16/76.40 203622[109:MRR:792.0,203620.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.40 203625[109:Res:53.1,203622.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.40 203627[110:Spt:203625.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 203629[110:Res:203627.0,61.1] always3(s42) || -> . % 76.16/76.40 203630[110:SSi:203629.0,78254.0,78258.0,192141.0,203472.0,203620.0] || -> . % 76.16/76.40 203631[110:Spt:203630.0,203625.0,203627.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.40 203632[110:Spt:203630.0,203625.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 203636[110:Res:203632.0,61.1] always3(s43) || -> . % 76.16/76.40 203637[110:SSi:203636.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.40 203638[108:Spt:203637.0,203471.0,203472.0] || until2p7(s42)*+ -> . % 76.16/76.40 203639[108:Spt:203637.0,203471.1] || -> node4(s41)*. % 76.16/76.40 203641[108:MRR:795.0,203639.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.40 203644[108:Res:53.1,203641.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.40 203646[109:Spt:203644.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 203648[109:Res:203646.0,61.1] always3(s41) || -> . % 76.16/76.40 203649[109:SSi:203648.0,78250.0,78253.0,192140.0,203470.0,203639.0] || -> . % 76.16/76.40 203650[109:Spt:203649.0,203644.0,203646.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.40 203651[109:Spt:203649.0,203644.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 203655[109:Res:203651.0,61.1] always3(s42) || -> . % 76.16/76.40 203656[109:SSi:203655.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.40 203657[107:Spt:203656.0,203469.0,203470.0] || until2p7(s41)*+ -> . % 76.16/76.40 203658[107:Spt:203656.0,203469.1] || -> node4(s40)*. % 76.16/76.40 203660[107:MRR:798.0,203658.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.40 203663[107:Res:53.1,203660.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.40 203665[108:Spt:203663.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 203667[108:Res:203665.0,61.1] always3(s40) || -> . % 76.16/76.40 203668[108:SSi:203667.0,78245.0,78249.0,192139.0,203468.0,203658.0] || -> . % 76.16/76.40 203669[108:Spt:203668.0,203663.0,203665.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.40 203670[108:Spt:203668.0,203663.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 203674[108:Res:203670.0,61.1] always3(s41) || -> . % 76.16/76.40 203675[108:SSi:203674.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.40 203676[106:Spt:203675.0,203467.0,203468.0] || until2p7(s40)*+ -> . % 76.16/76.40 203677[106:Spt:203675.0,203467.1] || -> node4(s39)*. % 76.16/76.40 203679[106:MRR:801.0,203677.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.40 203682[106:Res:53.1,203679.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.40 203687[107:Spt:203682.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 203689[107:Res:203687.0,61.1] always3(s39) || -> . % 76.16/76.40 203690[107:SSi:203689.0,78241.0,78244.0,192138.0,203466.0,203677.0] || -> . % 76.16/76.40 203691[107:Spt:203690.0,203682.0,203687.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.40 203692[107:Spt:203690.0,203682.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 203696[107:Res:203692.0,61.1] always3(s40) || -> . % 76.16/76.40 203697[107:SSi:203696.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.40 203698[105:Spt:203697.0,203465.0,203466.0] || until2p7(s39)*+ -> . % 76.16/76.40 203699[105:Spt:203697.0,203465.1] || -> node4(s38)*. % 76.16/76.40 203701[105:MRR:804.0,203699.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.40 203704[105:Res:53.1,203701.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.40 203706[106:Spt:203704.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 203708[106:Res:203706.0,61.1] always3(s38) || -> . % 76.16/76.40 203709[106:SSi:203708.0,78236.0,78240.0,192137.0,203464.0,203699.0] || -> . % 76.16/76.40 203710[106:Spt:203709.0,203704.0,203706.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.40 203711[106:Spt:203709.0,203704.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 203715[106:Res:203711.0,61.1] always3(s39) || -> . % 76.16/76.40 203716[106:SSi:203715.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.40 203717[104:Spt:203716.0,203463.0,203464.0] || until2p7(s38)*+ -> . % 76.16/76.40 203718[104:Spt:203716.0,203463.1] || -> node4(s37)*. % 76.16/76.40 203720[104:MRR:807.0,203718.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.40 203723[104:Res:53.1,203720.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.40 203725[105:Spt:203723.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 203727[105:Res:203725.0,61.1] always3(s37) || -> . % 76.16/76.40 203728[105:SSi:203727.0,78232.0,78235.0,192136.0,203462.0,203718.0] || -> . % 76.16/76.40 203729[105:Spt:203728.0,203723.0,203725.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.40 203730[105:Spt:203728.0,203723.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 203734[105:Res:203730.0,61.1] always3(s38) || -> . % 76.16/76.40 203735[105:SSi:203734.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.40 203736[103:Spt:203735.0,203461.0,203462.0] || until2p7(s37)*+ -> . % 76.16/76.40 203737[103:Spt:203735.0,203461.1] || -> node4(s36)*. % 76.16/76.40 203739[103:MRR:810.0,203737.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.40 203742[103:Res:53.1,203739.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.40 203744[104:Spt:203742.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 203746[104:Res:203744.0,61.1] always3(s36) || -> . % 76.16/76.40 203747[104:SSi:203746.0,78227.0,78231.0,192135.0,203460.0,203737.0] || -> . % 76.16/76.40 203748[104:Spt:203747.0,203742.0,203744.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.40 203749[104:Spt:203747.0,203742.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 203753[104:Res:203749.0,61.1] always3(s37) || -> . % 76.16/76.40 203754[104:SSi:203753.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.40 203755[102:Spt:203754.0,203459.0,203460.0] || until2p7(s36)*+ -> . % 76.16/76.40 203756[102:Spt:203754.0,203459.1] || -> node4(s35)*. % 76.16/76.40 203758[102:MRR:813.0,203756.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.40 203761[102:Res:53.1,203758.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.40 203766[103:Spt:203761.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 203768[103:Res:203766.0,61.1] always3(s35) || -> . % 76.16/76.40 203769[103:SSi:203768.0,78223.0,78226.0,192134.0,203458.0,203756.0] || -> . % 76.16/76.40 203770[103:Spt:203769.0,203761.0,203766.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.40 203771[103:Spt:203769.0,203761.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 203775[103:Res:203771.0,61.1] always3(s36) || -> . % 76.16/76.40 203776[103:SSi:203775.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.40 203777[101:Spt:203776.0,203457.0,203458.0] || until2p7(s35)*+ -> . % 76.16/76.40 203778[101:Spt:203776.0,203457.1] || -> node4(s34)*. % 76.16/76.40 203780[101:MRR:816.0,203778.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.40 203783[101:Res:53.1,203780.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.40 203785[102:Spt:203783.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 203787[102:Res:203785.0,61.1] always3(s34) || -> . % 76.16/76.40 203788[102:SSi:203787.0,78218.0,78222.0,192133.0,203456.0,203778.0] || -> . % 76.16/76.40 203789[102:Spt:203788.0,203783.0,203785.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.40 203790[102:Spt:203788.0,203783.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 203794[102:Res:203790.0,61.1] always3(s35) || -> . % 76.16/76.40 203795[102:SSi:203794.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.40 203796[100:Spt:203795.0,203455.0,203456.0] || until2p7(s34)*+ -> . % 76.16/76.40 203797[100:Spt:203795.0,203455.1] || -> node4(s33)*. % 76.16/76.40 203799[100:MRR:819.0,203797.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.40 203802[100:Res:53.1,203799.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.40 203804[101:Spt:203802.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 203806[101:Res:203804.0,61.1] always3(s33) || -> . % 76.16/76.40 203807[101:SSi:203806.0,78214.0,78217.0,192132.0,203454.0,203797.0] || -> . % 76.16/76.40 203808[101:Spt:203807.0,203802.0,203804.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.40 203809[101:Spt:203807.0,203802.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 203813[101:Res:203809.0,61.1] always3(s34) || -> . % 76.16/76.40 203814[101:SSi:203813.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.40 203815[99:Spt:203814.0,203453.0,203454.0] || until2p7(s33)*+ -> . % 76.16/76.40 203816[99:Spt:203814.0,203453.1] || -> node4(s32)*. % 76.16/76.40 203818[99:MRR:822.0,203816.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.40 203821[99:Res:53.1,203818.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.40 203823[100:Spt:203821.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 203825[100:Res:203823.0,61.1] always3(s32) || -> . % 76.16/76.40 203826[100:SSi:203825.0,78209.0,78213.0,192131.0,203452.0,203816.0] || -> . % 76.16/76.40 203827[100:Spt:203826.0,203821.0,203823.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.40 203828[100:Spt:203826.0,203821.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 203832[100:Res:203828.0,61.1] always3(s33) || -> . % 76.16/76.40 203833[100:SSi:203832.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.40 203834[98:Spt:203833.0,203451.0,203452.0] || until2p7(s32)*+ -> . % 76.16/76.40 203835[98:Spt:203833.0,203451.1] || -> node4(s31)*. % 76.16/76.40 203837[98:MRR:825.0,203835.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.40 203840[98:Res:53.1,203837.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.40 203845[99:Spt:203840.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 203847[99:Res:203845.0,61.1] always3(s31) || -> . % 76.16/76.40 203848[99:SSi:203847.0,78205.0,78208.0,192130.0,203450.0,203835.0] || -> . % 76.16/76.40 203849[99:Spt:203848.0,203840.0,203845.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.40 203850[99:Spt:203848.0,203840.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 203854[99:Res:203850.0,61.1] always3(s32) || -> . % 76.16/76.40 203855[99:SSi:203854.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.40 203856[97:Spt:203855.0,203449.0,203450.0] || until2p7(s31)*+ -> . % 76.16/76.40 203857[97:Spt:203855.0,203449.1] || -> node4(s30)*. % 76.16/76.40 203859[97:MRR:828.0,203857.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.40 203862[97:Res:53.1,203859.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.40 203864[98:Spt:203862.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 203866[98:Res:203864.0,61.1] always3(s30) || -> . % 76.16/76.40 203867[98:SSi:203866.0,78200.0,78204.0,192129.0,203448.0,203857.0] || -> . % 76.16/76.40 203868[98:Spt:203867.0,203862.0,203864.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.40 203869[98:Spt:203867.0,203862.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 203873[98:Res:203869.0,61.1] always3(s31) || -> . % 76.16/76.40 203874[98:SSi:203873.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.40 203875[96:Spt:203874.0,203447.0,203448.0] || until2p7(s30)*+ -> . % 76.16/76.40 203876[96:Spt:203874.0,203447.1] || -> node4(s29)*. % 76.16/76.40 203878[96:MRR:831.0,203876.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.40 203881[96:Res:53.1,203878.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.40 203883[97:Spt:203881.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 203885[97:Res:203883.0,61.1] always3(s29) || -> . % 76.16/76.40 203886[97:SSi:203885.0,78196.0,78199.0,192128.0,203446.0,203876.0] || -> . % 76.16/76.40 203887[97:Spt:203886.0,203881.0,203883.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.40 203888[97:Spt:203886.0,203881.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 203892[97:Res:203888.0,61.1] always3(s30) || -> . % 76.16/76.40 203893[97:SSi:203892.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.40 203894[95:Spt:203893.0,203445.0,203446.0] || until2p7(s29)*+ -> . % 76.16/76.40 203895[95:Spt:203893.0,203445.1] || -> node4(s28)*. % 76.16/76.40 203897[95:MRR:834.0,203895.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.40 203900[95:Res:53.1,203897.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.40 203902[96:Spt:203900.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 203904[96:Res:203902.0,61.1] always3(s28) || -> . % 76.16/76.40 203905[96:SSi:203904.0,78191.0,78195.0,192127.0,203444.0,203895.0] || -> . % 76.16/76.40 203906[96:Spt:203905.0,203900.0,203902.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.40 203907[96:Spt:203905.0,203900.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 203911[96:Res:203907.0,61.1] always3(s29) || -> . % 76.16/76.40 203912[96:SSi:203911.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.40 203913[94:Spt:203912.0,203443.0,203444.0] || until2p7(s28)*+ -> . % 76.16/76.40 203914[94:Spt:203912.0,203443.1] || -> node4(s27)*. % 76.16/76.40 203916[94:MRR:837.0,203914.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.40 203919[94:Res:53.1,203916.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.40 203924[95:Spt:203919.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 203926[95:Res:203924.0,61.1] always3(s27) || -> . % 76.16/76.40 203927[95:SSi:203926.0,78187.0,78190.0,192126.0,203442.0,203914.0] || -> . % 76.16/76.40 203928[95:Spt:203927.0,203919.0,203924.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.40 203929[95:Spt:203927.0,203919.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 203933[95:Res:203929.0,61.1] always3(s28) || -> . % 76.16/76.40 203934[95:SSi:203933.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.40 203935[93:Spt:203934.0,203441.0,203442.0] || until2p7(s27)*+ -> . % 76.16/76.40 203936[93:Spt:203934.0,203441.1] || -> node4(s26)*. % 76.16/76.40 203938[93:MRR:840.0,203936.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.40 203941[93:Res:53.1,203938.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.40 203943[94:Spt:203941.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 203945[94:Res:203943.0,61.1] always3(s26) || -> . % 76.16/76.40 203946[94:SSi:203945.0,78182.0,78186.0,192125.0,203440.0,203936.0] || -> . % 76.16/76.40 203947[94:Spt:203946.0,203941.0,203943.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.40 203948[94:Spt:203946.0,203941.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 203952[94:Res:203948.0,61.1] always3(s27) || -> . % 76.16/76.40 203953[94:SSi:203952.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.40 203954[92:Spt:203953.0,203439.0,203440.0] || until2p7(s26)*+ -> . % 76.16/76.40 203955[92:Spt:203953.0,203439.1] || -> node4(s25)*. % 76.16/76.40 203957[92:MRR:843.0,203955.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.40 203960[92:Res:53.1,203957.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.40 203962[93:Spt:203960.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 203964[93:Res:203962.0,61.1] always3(s25) || -> . % 76.16/76.40 203965[93:SSi:203964.0,78178.0,78181.0,192124.0,203438.0,203955.0] || -> . % 76.16/76.40 203966[93:Spt:203965.0,203960.0,203962.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.40 203967[93:Spt:203965.0,203960.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 203971[93:Res:203967.0,61.1] always3(s26) || -> . % 76.16/76.40 203972[93:SSi:203971.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.40 203973[91:Spt:203972.0,203437.0,203438.0] || until2p7(s25)*+ -> . % 76.16/76.40 203974[91:Spt:203972.0,203437.1] || -> node4(s24)*. % 76.16/76.40 203976[91:MRR:846.0,203974.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.40 203979[91:Res:53.1,203976.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.40 203981[92:Spt:203979.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 203983[92:Res:203981.0,61.1] always3(s24) || -> . % 76.16/76.40 203984[92:SSi:203983.0,78173.0,78177.0,192123.0,203436.0,203974.0] || -> . % 76.16/76.40 203985[92:Spt:203984.0,203979.0,203981.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.40 203986[92:Spt:203984.0,203979.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 203990[92:Res:203986.0,61.1] always3(s25) || -> . % 76.16/76.40 203991[92:SSi:203990.0,78178.0,78181.0,192124.0] || -> . % 76.16/76.40 203992[90:Spt:203991.0,203435.0,203436.0] || until2p7(s24)*+ -> . % 76.16/76.40 203993[90:Spt:203991.0,203435.1] || -> node4(s23)*. % 76.16/76.40 203995[90:MRR:849.0,203993.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.40 203998[90:Res:53.1,203995.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.40 204003[91:Spt:203998.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 204005[91:Res:204003.0,61.1] always3(s23) || -> . % 76.16/76.40 204006[91:SSi:204005.0,78169.0,78172.0,192122.0,203434.0,203993.0] || -> . % 76.16/76.40 204007[91:Spt:204006.0,203998.0,204003.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.40 204008[91:Spt:204006.0,203998.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 204012[91:Res:204008.0,61.1] always3(s24) || -> . % 76.16/76.40 204013[91:SSi:204012.0,78173.0,78177.0,192123.0] || -> . % 76.16/76.40 204014[89:Spt:204013.0,203433.0,203434.0] || until2p7(s23)*+ -> . % 76.16/76.40 204015[89:Spt:204013.0,203433.1] || -> node4(s22)*. % 76.16/76.40 204017[89:MRR:852.0,204015.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.40 204020[89:Res:53.1,204017.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.40 204022[90:Spt:204020.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 204024[90:Res:204022.0,61.1] always3(s22) || -> . % 76.16/76.40 204025[90:SSi:204024.0,78164.0,78168.0,192121.0,203432.0,204015.0] || -> . % 76.16/76.40 204026[90:Spt:204025.0,204020.0,204022.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.40 204027[90:Spt:204025.0,204020.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 204031[90:Res:204027.0,61.1] always3(s23) || -> . % 76.16/76.40 204032[90:SSi:204031.0,78169.0,78172.0,192122.0] || -> . % 76.16/76.40 204033[88:Spt:204032.0,203431.0,203432.0] || until2p7(s22)*+ -> . % 76.16/76.40 204034[88:Spt:204032.0,203431.1] || -> node4(s21)*. % 76.16/76.40 204036[88:MRR:855.0,204034.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.40 204039[88:Res:53.1,204036.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.40 204041[89:Spt:204039.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 204043[89:Res:204041.0,61.1] always3(s21) || -> . % 76.16/76.40 204044[89:SSi:204043.0,78160.0,78163.0,192120.0,203430.0,204034.0] || -> . % 76.16/76.40 204045[89:Spt:204044.0,204039.0,204041.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.40 204046[89:Spt:204044.0,204039.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 204050[89:Res:204046.0,61.1] always3(s22) || -> . % 76.16/76.40 204051[89:SSi:204050.0,78164.0,78168.0,192121.0] || -> . % 76.16/76.40 204052[87:Spt:204051.0,203429.0,203430.0] || until2p7(s21)*+ -> . % 76.16/76.40 204053[87:Spt:204051.0,203429.1] || -> node4(s20)*. % 76.16/76.40 204055[87:MRR:858.0,204053.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.40 204058[87:Res:53.1,204055.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.40 204060[87:MRR:204058.0,203419.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 204062[87:Res:204060.0,61.1] always3(s21) || -> . % 76.16/76.40 204063[87:SSi:204062.0,78160.0,78163.0,192120.0] || -> . % 76.16/76.40 204064[85:Spt:204063.0,203305.0,203308.0] || trans(s49,s20)*+ -> . % 76.16/76.40 204065[85:Spt:204063.0,203305.1,203305.2,203305.3,203305.4,203305.5,203305.6,203305.7,203305.8,203305.9,203305.10,203305.11,203305.12,203305.13,203305.14] || -> trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.40 204067[85:MRR:203307.1,204064.0] xuntil6(s49) || -> trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.40 204068[86:Spt:204065.0] || -> trans(s49,s19)*. % 76.16/76.40 204069[86:Res:204068.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s19)*. % 76.16/76.40 204071[86:Res:204068.0,60.0] || -> node2(s49,s19)*. % 76.16/76.40 204072[86:SSi:204069.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s19)*. % 76.16/76.40 204073[86:Res:204071.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)*. % 76.16/76.40 204175[86:SoR:204073.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)*. % 76.16/76.40 204177[86:SoR:204175.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s19,c_busy)* xuntil6(s49). % 76.16/76.40 204178[86:SSi:204177.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s19,c_busy)* xuntil6(s49). % 76.16/76.40 204179[87:Spt:204178.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.40 204181[87:Res:204179.0,61.1] always3(s19) || -> . % 76.16/76.40 204182[87:SSi:204181.0,78151.0,78154.0,192118.0] || -> . % 76.16/76.40 204183[87:Spt:204182.0,204178.1,204179.0] || m_main_v_state(s19,c_busy)*+ -> . % 76.16/76.40 204184[87:Spt:204182.0,204178.0,204178.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.40 204188[87:MRR:204175.2,204183.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.40 204189[87:Res:53.1,204184.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.40 204191[87:MRR:204189.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.40 204192[87:MRR:204072.0,204191.0] || -> until2p7(s19)*. % 76.16/76.40 204193[87:MRR:215.0,204192.0] || -> until2p7(s20)* node4(s19). % 76.16/76.40 204194[88:Spt:204193.0] || -> until2p7(s20)*. % 76.16/76.40 204195[88:MRR:216.0,204194.0] || -> until2p7(s21)* node4(s20). % 76.16/76.40 204196[89:Spt:204195.0] || -> until2p7(s21)*. % 76.16/76.40 204197[89:MRR:217.0,204196.0] || -> until2p7(s22)* node4(s21). % 76.16/76.40 204198[90:Spt:204197.0] || -> until2p7(s22)*. % 76.16/76.40 204199[90:MRR:218.0,204198.0] || -> until2p7(s23)* node4(s22). % 76.16/76.40 204200[91:Spt:204199.0] || -> until2p7(s23)*. % 76.16/76.40 204201[91:MRR:219.0,204200.0] || -> until2p7(s24)* node4(s23). % 76.16/76.40 204202[92:Spt:204201.0] || -> until2p7(s24)*. % 76.16/76.40 204203[92:MRR:220.0,204202.0] || -> until2p7(s25)* node4(s24). % 76.16/76.40 204204[93:Spt:204203.0] || -> until2p7(s25)*. % 76.16/76.40 204205[93:MRR:221.0,204204.0] || -> until2p7(s26)* node4(s25). % 76.16/76.40 204206[94:Spt:204205.0] || -> until2p7(s26)*. % 76.16/76.40 204207[94:MRR:222.0,204206.0] || -> until2p7(s27)* node4(s26). % 76.16/76.40 204208[95:Spt:204207.0] || -> until2p7(s27)*. % 76.16/76.40 204209[95:MRR:223.0,204208.0] || -> until2p7(s28)* node4(s27). % 76.16/76.40 204210[96:Spt:204209.0] || -> until2p7(s28)*. % 76.16/76.40 204211[96:MRR:224.0,204210.0] || -> until2p7(s29)* node4(s28). % 76.16/76.40 204212[97:Spt:204211.0] || -> until2p7(s29)*. % 76.16/76.40 204213[97:MRR:225.0,204212.0] || -> until2p7(s30)* node4(s29). % 76.16/76.40 204214[98:Spt:204213.0] || -> until2p7(s30)*. % 76.16/76.40 204215[98:MRR:226.0,204214.0] || -> until2p7(s31)* node4(s30). % 76.16/76.40 204216[99:Spt:204215.0] || -> until2p7(s31)*. % 76.16/76.40 204217[99:MRR:227.0,204216.0] || -> until2p7(s32)* node4(s31). % 76.16/76.40 204218[100:Spt:204217.0] || -> until2p7(s32)*. % 76.16/76.40 204219[100:MRR:228.0,204218.0] || -> until2p7(s33)* node4(s32). % 76.16/76.40 204220[101:Spt:204219.0] || -> until2p7(s33)*. % 76.16/76.40 204221[101:MRR:229.0,204220.0] || -> until2p7(s34)* node4(s33). % 76.16/76.40 204222[102:Spt:204221.0] || -> until2p7(s34)*. % 76.16/76.40 204223[102:MRR:230.0,204222.0] || -> until2p7(s35)* node4(s34). % 76.16/76.40 204224[103:Spt:204223.0] || -> until2p7(s35)*. % 76.16/76.40 204225[103:MRR:231.0,204224.0] || -> until2p7(s36)* node4(s35). % 76.16/76.40 204226[104:Spt:204225.0] || -> until2p7(s36)*. % 76.16/76.40 204227[104:MRR:232.0,204226.0] || -> until2p7(s37)* node4(s36). % 76.16/76.40 204228[105:Spt:204227.0] || -> until2p7(s37)*. % 76.16/76.40 204229[105:MRR:235.0,204228.0] || -> until2p7(s38)* node4(s37). % 76.16/76.40 204230[106:Spt:204229.0] || -> until2p7(s38)*. % 76.16/76.40 204231[106:MRR:236.0,204230.0] || -> until2p7(s39)* node4(s38). % 76.16/76.40 204232[107:Spt:204231.0] || -> until2p7(s39)*. % 76.16/76.40 204233[107:MRR:237.0,204232.0] || -> until2p7(s40)* node4(s39). % 76.16/76.40 204234[108:Spt:204233.0] || -> until2p7(s40)*. % 76.16/76.40 204235[108:MRR:238.0,204234.0] || -> until2p7(s41)* node4(s40). % 76.16/76.40 204236[109:Spt:204235.0] || -> until2p7(s41)*. % 76.16/76.40 204237[109:MRR:239.0,204236.0] || -> until2p7(s42)* node4(s41). % 76.16/76.40 204238[110:Spt:204237.0] || -> until2p7(s42)*. % 76.16/76.40 204239[110:MRR:240.0,204238.0] || -> until2p7(s43)* node4(s42). % 76.16/76.40 204240[111:Spt:204239.0] || -> until2p7(s43)*. % 76.16/76.40 204241[111:MRR:241.0,204240.0] || -> until2p7(s44)* node4(s43). % 76.16/76.40 204242[112:Spt:204241.0] || -> until2p7(s44)*. % 76.16/76.40 204243[112:MRR:539.0,204242.0] || -> until2p7(s45)* node4(s44). % 76.16/76.40 204244[113:Spt:204243.0] || -> until2p7(s45)*. % 76.16/76.40 204245[113:MRR:544.0,204244.0] || -> until2p7(s46)* node4(s45). % 76.16/76.40 204246[114:Spt:204245.0] || -> until2p7(s46)*. % 76.16/76.40 204247[114:MRR:549.0,204246.0] || -> until2p7(s47)* node4(s46). % 76.16/76.40 204248[115:Spt:204247.0] || -> until2p7(s47)*. % 76.16/76.40 204249[115:MRR:554.0,204248.0] || -> until2p7(s48)* node4(s47). % 76.16/76.40 204250[116:Spt:204249.0] || -> until2p7(s48)*. % 76.16/76.40 204251[116:MRR:559.0,204250.0] || -> until2p7(s49)* node4(s48). % 76.16/76.40 204252[117:Spt:204251.0] || -> until2p7(s49)*. % 76.16/76.40 204253[117:MRR:194.0,204252.0] || -> node4(s49)*. % 76.16/76.40 204254[117:MRR:204188.0,204253.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.40 204255[117:Res:53.1,204254.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.40 204257[117:MRR:204255.0,78381.0] || -> . % 76.16/76.40 204258[117:Spt:204257.0,204251.0,204252.0] || until2p7(s49)*+ -> . % 76.16/76.40 204259[117:Spt:204257.0,204251.1] || -> node4(s48)*. % 76.16/76.40 204260[117:MRR:78384.0,204259.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.40 204263[117:Res:53.1,204260.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 204266[117:Res:204263.0,61.1] always3(s48) || -> . % 76.16/76.40 204267[117:SSi:204266.0,78281.0,78387.0,192147.0,204250.0,204259.0] || -> . % 76.16/76.40 204268[116:Spt:204267.0,204249.0,204250.0] || until2p7(s48)*+ -> . % 76.16/76.40 204269[116:Spt:204267.0,204249.1] || -> node4(s47)*. % 76.16/76.40 204271[116:MRR:777.0,204269.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.40 204286[116:Res:53.1,204271.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.40 204288[117:Spt:204286.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 204290[117:Res:204288.0,61.1] always3(s47) || -> . % 76.16/76.40 204291[117:SSi:204290.0,78277.0,78280.0,192146.0,204248.0,204269.0] || -> . % 76.16/76.40 204292[117:Spt:204291.0,204286.0,204288.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.40 204293[117:Spt:204291.0,204286.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 204297[117:Res:204293.0,61.1] always3(s48) || -> . % 76.16/76.40 204298[117:SSi:204297.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.40 204299[115:Spt:204298.0,204247.0,204248.0] || until2p7(s47)*+ -> . % 76.16/76.40 204300[115:Spt:204298.0,204247.1] || -> node4(s46)*. % 76.16/76.40 204302[115:MRR:780.0,204300.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.40 204312[115:Res:53.1,204302.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.40 204314[116:Spt:204312.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 204316[116:Res:204314.0,61.1] always3(s46) || -> . % 76.16/76.40 204317[116:SSi:204316.0,78272.0,78276.0,192145.0,204246.0,204300.0] || -> . % 76.16/76.40 204318[116:Spt:204317.0,204312.0,204314.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.40 204319[116:Spt:204317.0,204312.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 204323[116:Res:204319.0,61.1] always3(s47) || -> . % 76.16/76.40 204324[116:SSi:204323.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.40 204325[114:Spt:204324.0,204245.0,204246.0] || until2p7(s46)*+ -> . % 76.16/76.40 204326[114:Spt:204324.0,204245.1] || -> node4(s45)*. % 76.16/76.40 204328[114:MRR:783.0,204326.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.40 204331[114:Res:53.1,204328.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.40 204333[115:Spt:204331.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 204335[115:Res:204333.0,61.1] always3(s45) || -> . % 76.16/76.40 204336[115:SSi:204335.0,78268.0,78271.0,192144.0,204244.0,204326.0] || -> . % 76.16/76.40 204337[115:Spt:204336.0,204331.0,204333.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.40 204338[115:Spt:204336.0,204331.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 204342[115:Res:204338.0,61.1] always3(s46) || -> . % 76.16/76.40 204343[115:SSi:204342.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.40 204344[113:Spt:204343.0,204243.0,204244.0] || until2p7(s45)*+ -> . % 76.16/76.40 204345[113:Spt:204343.0,204243.1] || -> node4(s44)*. % 76.16/76.40 204347[113:MRR:786.0,204345.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.40 204350[113:Res:53.1,204347.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.40 204352[114:Spt:204350.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 204354[114:Res:204352.0,61.1] always3(s44) || -> . % 76.16/76.40 204355[114:SSi:204354.0,78263.0,78267.0,192143.0,204242.0,204345.0] || -> . % 76.16/76.40 204356[114:Spt:204355.0,204350.0,204352.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.40 204357[114:Spt:204355.0,204350.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 204361[114:Res:204357.0,61.1] always3(s45) || -> . % 76.16/76.40 204362[114:SSi:204361.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.40 204363[112:Spt:204362.0,204241.0,204242.0] || until2p7(s44)*+ -> . % 76.16/76.40 204364[112:Spt:204362.0,204241.1] || -> node4(s43)*. % 76.16/76.40 204366[112:MRR:789.0,204364.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.40 204369[112:Res:53.1,204366.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.40 204374[113:Spt:204369.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 204376[113:Res:204374.0,61.1] always3(s43) || -> . % 76.16/76.40 204377[113:SSi:204376.0,78259.0,78262.0,192142.0,204240.0,204364.0] || -> . % 76.16/76.40 204378[113:Spt:204377.0,204369.0,204374.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.40 204379[113:Spt:204377.0,204369.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 204383[113:Res:204379.0,61.1] always3(s44) || -> . % 76.16/76.40 204384[113:SSi:204383.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.40 204385[111:Spt:204384.0,204239.0,204240.0] || until2p7(s43)*+ -> . % 76.16/76.40 204386[111:Spt:204384.0,204239.1] || -> node4(s42)*. % 76.16/76.40 204388[111:MRR:792.0,204386.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.40 204391[111:Res:53.1,204388.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.40 204393[112:Spt:204391.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 204395[112:Res:204393.0,61.1] always3(s42) || -> . % 76.16/76.40 204396[112:SSi:204395.0,78254.0,78258.0,192141.0,204238.0,204386.0] || -> . % 76.16/76.40 204397[112:Spt:204396.0,204391.0,204393.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.40 204398[112:Spt:204396.0,204391.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 204402[112:Res:204398.0,61.1] always3(s43) || -> . % 76.16/76.40 204403[112:SSi:204402.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.40 204404[110:Spt:204403.0,204237.0,204238.0] || until2p7(s42)*+ -> . % 76.16/76.40 204405[110:Spt:204403.0,204237.1] || -> node4(s41)*. % 76.16/76.40 204407[110:MRR:795.0,204405.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.40 204410[110:Res:53.1,204407.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.40 204412[111:Spt:204410.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 204414[111:Res:204412.0,61.1] always3(s41) || -> . % 76.16/76.40 204415[111:SSi:204414.0,78250.0,78253.0,192140.0,204236.0,204405.0] || -> . % 76.16/76.40 204416[111:Spt:204415.0,204410.0,204412.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.40 204417[111:Spt:204415.0,204410.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 204421[111:Res:204417.0,61.1] always3(s42) || -> . % 76.16/76.40 204422[111:SSi:204421.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.40 204423[109:Spt:204422.0,204235.0,204236.0] || until2p7(s41)*+ -> . % 76.16/76.40 204424[109:Spt:204422.0,204235.1] || -> node4(s40)*. % 76.16/76.40 204426[109:MRR:798.0,204424.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.40 204429[109:Res:53.1,204426.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.40 204431[110:Spt:204429.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 204433[110:Res:204431.0,61.1] always3(s40) || -> . % 76.16/76.40 204434[110:SSi:204433.0,78245.0,78249.0,192139.0,204234.0,204424.0] || -> . % 76.16/76.40 204435[110:Spt:204434.0,204429.0,204431.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.40 204436[110:Spt:204434.0,204429.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 204440[110:Res:204436.0,61.1] always3(s41) || -> . % 76.16/76.40 204441[110:SSi:204440.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.40 204442[108:Spt:204441.0,204233.0,204234.0] || until2p7(s40)*+ -> . % 76.16/76.40 204443[108:Spt:204441.0,204233.1] || -> node4(s39)*. % 76.16/76.40 204445[108:MRR:801.0,204443.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.40 204448[108:Res:53.1,204445.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.40 204453[109:Spt:204448.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 204455[109:Res:204453.0,61.1] always3(s39) || -> . % 76.16/76.40 204456[109:SSi:204455.0,78241.0,78244.0,192138.0,204232.0,204443.0] || -> . % 76.16/76.40 204457[109:Spt:204456.0,204448.0,204453.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.40 204458[109:Spt:204456.0,204448.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 204462[109:Res:204458.0,61.1] always3(s40) || -> . % 76.16/76.40 204463[109:SSi:204462.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.40 204464[107:Spt:204463.0,204231.0,204232.0] || until2p7(s39)*+ -> . % 76.16/76.40 204465[107:Spt:204463.0,204231.1] || -> node4(s38)*. % 76.16/76.40 204467[107:MRR:804.0,204465.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.40 204470[107:Res:53.1,204467.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.40 204472[108:Spt:204470.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 204474[108:Res:204472.0,61.1] always3(s38) || -> . % 76.16/76.40 204475[108:SSi:204474.0,78236.0,78240.0,192137.0,204230.0,204465.0] || -> . % 76.16/76.40 204476[108:Spt:204475.0,204470.0,204472.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.40 204477[108:Spt:204475.0,204470.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 204481[108:Res:204477.0,61.1] always3(s39) || -> . % 76.16/76.40 204482[108:SSi:204481.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.40 204483[106:Spt:204482.0,204229.0,204230.0] || until2p7(s38)*+ -> . % 76.16/76.40 204484[106:Spt:204482.0,204229.1] || -> node4(s37)*. % 76.16/76.40 204486[106:MRR:807.0,204484.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.40 204489[106:Res:53.1,204486.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.40 204491[107:Spt:204489.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 204493[107:Res:204491.0,61.1] always3(s37) || -> . % 76.16/76.40 204494[107:SSi:204493.0,78232.0,78235.0,192136.0,204228.0,204484.0] || -> . % 76.16/76.40 204495[107:Spt:204494.0,204489.0,204491.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.40 204496[107:Spt:204494.0,204489.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 204500[107:Res:204496.0,61.1] always3(s38) || -> . % 76.16/76.40 204501[107:SSi:204500.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.40 204502[105:Spt:204501.0,204227.0,204228.0] || until2p7(s37)*+ -> . % 76.16/76.40 204503[105:Spt:204501.0,204227.1] || -> node4(s36)*. % 76.16/76.40 204505[105:MRR:810.0,204503.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.40 204508[105:Res:53.1,204505.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.40 204510[106:Spt:204508.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 204512[106:Res:204510.0,61.1] always3(s36) || -> . % 76.16/76.40 204513[106:SSi:204512.0,78227.0,78231.0,192135.0,204226.0,204503.0] || -> . % 76.16/76.40 204514[106:Spt:204513.0,204508.0,204510.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.40 204515[106:Spt:204513.0,204508.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 204519[106:Res:204515.0,61.1] always3(s37) || -> . % 76.16/76.40 204520[106:SSi:204519.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.40 204521[104:Spt:204520.0,204225.0,204226.0] || until2p7(s36)*+ -> . % 76.16/76.40 204522[104:Spt:204520.0,204225.1] || -> node4(s35)*. % 76.16/76.40 204524[104:MRR:813.0,204522.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.40 204527[104:Res:53.1,204524.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.40 204532[105:Spt:204527.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 204534[105:Res:204532.0,61.1] always3(s35) || -> . % 76.16/76.40 204535[105:SSi:204534.0,78223.0,78226.0,192134.0,204224.0,204522.0] || -> . % 76.16/76.40 204536[105:Spt:204535.0,204527.0,204532.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.40 204537[105:Spt:204535.0,204527.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 204541[105:Res:204537.0,61.1] always3(s36) || -> . % 76.16/76.40 204542[105:SSi:204541.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.40 204543[103:Spt:204542.0,204223.0,204224.0] || until2p7(s35)*+ -> . % 76.16/76.40 204544[103:Spt:204542.0,204223.1] || -> node4(s34)*. % 76.16/76.40 204546[103:MRR:816.0,204544.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.40 204549[103:Res:53.1,204546.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.40 204551[104:Spt:204549.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 204553[104:Res:204551.0,61.1] always3(s34) || -> . % 76.16/76.40 204554[104:SSi:204553.0,78218.0,78222.0,192133.0,204222.0,204544.0] || -> . % 76.16/76.40 204555[104:Spt:204554.0,204549.0,204551.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.40 204556[104:Spt:204554.0,204549.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 204560[104:Res:204556.0,61.1] always3(s35) || -> . % 76.16/76.40 204561[104:SSi:204560.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.40 204562[102:Spt:204561.0,204221.0,204222.0] || until2p7(s34)*+ -> . % 76.16/76.40 204563[102:Spt:204561.0,204221.1] || -> node4(s33)*. % 76.16/76.40 204565[102:MRR:819.0,204563.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.40 204568[102:Res:53.1,204565.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.40 204570[103:Spt:204568.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 204572[103:Res:204570.0,61.1] always3(s33) || -> . % 76.16/76.40 204573[103:SSi:204572.0,78214.0,78217.0,192132.0,204220.0,204563.0] || -> . % 76.16/76.40 204574[103:Spt:204573.0,204568.0,204570.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.40 204575[103:Spt:204573.0,204568.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 204579[103:Res:204575.0,61.1] always3(s34) || -> . % 76.16/76.40 204580[103:SSi:204579.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.40 204581[101:Spt:204580.0,204219.0,204220.0] || until2p7(s33)*+ -> . % 76.16/76.40 204582[101:Spt:204580.0,204219.1] || -> node4(s32)*. % 76.16/76.40 204584[101:MRR:822.0,204582.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.40 204587[101:Res:53.1,204584.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.40 204589[102:Spt:204587.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 204591[102:Res:204589.0,61.1] always3(s32) || -> . % 76.16/76.40 204592[102:SSi:204591.0,78209.0,78213.0,192131.0,204218.0,204582.0] || -> . % 76.16/76.40 204593[102:Spt:204592.0,204587.0,204589.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.40 204594[102:Spt:204592.0,204587.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 204598[102:Res:204594.0,61.1] always3(s33) || -> . % 76.16/76.40 204599[102:SSi:204598.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.40 204600[100:Spt:204599.0,204217.0,204218.0] || until2p7(s32)*+ -> . % 76.16/76.40 204601[100:Spt:204599.0,204217.1] || -> node4(s31)*. % 76.16/76.40 204603[100:MRR:825.0,204601.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.40 204606[100:Res:53.1,204603.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.40 204611[101:Spt:204606.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 204613[101:Res:204611.0,61.1] always3(s31) || -> . % 76.16/76.40 204614[101:SSi:204613.0,78205.0,78208.0,192130.0,204216.0,204601.0] || -> . % 76.16/76.40 204615[101:Spt:204614.0,204606.0,204611.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.40 204616[101:Spt:204614.0,204606.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 204620[101:Res:204616.0,61.1] always3(s32) || -> . % 76.16/76.40 204621[101:SSi:204620.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.40 204622[99:Spt:204621.0,204215.0,204216.0] || until2p7(s31)*+ -> . % 76.16/76.40 204623[99:Spt:204621.0,204215.1] || -> node4(s30)*. % 76.16/76.40 204625[99:MRR:828.0,204623.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.40 204628[99:Res:53.1,204625.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.40 204630[100:Spt:204628.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 204632[100:Res:204630.0,61.1] always3(s30) || -> . % 76.16/76.40 204633[100:SSi:204632.0,78200.0,78204.0,192129.0,204214.0,204623.0] || -> . % 76.16/76.40 204634[100:Spt:204633.0,204628.0,204630.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.40 204635[100:Spt:204633.0,204628.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 204639[100:Res:204635.0,61.1] always3(s31) || -> . % 76.16/76.40 204640[100:SSi:204639.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.40 204641[98:Spt:204640.0,204213.0,204214.0] || until2p7(s30)*+ -> . % 76.16/76.40 204642[98:Spt:204640.0,204213.1] || -> node4(s29)*. % 76.16/76.40 204644[98:MRR:831.0,204642.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.40 204647[98:Res:53.1,204644.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.40 204649[99:Spt:204647.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 204651[99:Res:204649.0,61.1] always3(s29) || -> . % 76.16/76.40 204652[99:SSi:204651.0,78196.0,78199.0,192128.0,204212.0,204642.0] || -> . % 76.16/76.40 204653[99:Spt:204652.0,204647.0,204649.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.40 204654[99:Spt:204652.0,204647.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 204658[99:Res:204654.0,61.1] always3(s30) || -> . % 76.16/76.40 204659[99:SSi:204658.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.40 204660[97:Spt:204659.0,204211.0,204212.0] || until2p7(s29)*+ -> . % 76.16/76.40 204661[97:Spt:204659.0,204211.1] || -> node4(s28)*. % 76.16/76.40 204663[97:MRR:834.0,204661.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.40 204666[97:Res:53.1,204663.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.40 204668[98:Spt:204666.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 204670[98:Res:204668.0,61.1] always3(s28) || -> . % 76.16/76.40 204671[98:SSi:204670.0,78191.0,78195.0,192127.0,204210.0,204661.0] || -> . % 76.16/76.40 204672[98:Spt:204671.0,204666.0,204668.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.40 204673[98:Spt:204671.0,204666.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 204677[98:Res:204673.0,61.1] always3(s29) || -> . % 76.16/76.40 204678[98:SSi:204677.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.40 204679[96:Spt:204678.0,204209.0,204210.0] || until2p7(s28)*+ -> . % 76.16/76.40 204680[96:Spt:204678.0,204209.1] || -> node4(s27)*. % 76.16/76.40 204682[96:MRR:837.0,204680.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.40 204685[96:Res:53.1,204682.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.40 204690[97:Spt:204685.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 204692[97:Res:204690.0,61.1] always3(s27) || -> . % 76.16/76.40 204693[97:SSi:204692.0,78187.0,78190.0,192126.0,204208.0,204680.0] || -> . % 76.16/76.40 204694[97:Spt:204693.0,204685.0,204690.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.40 204695[97:Spt:204693.0,204685.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 204699[97:Res:204695.0,61.1] always3(s28) || -> . % 76.16/76.40 204700[97:SSi:204699.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.40 204701[95:Spt:204700.0,204207.0,204208.0] || until2p7(s27)*+ -> . % 76.16/76.40 204702[95:Spt:204700.0,204207.1] || -> node4(s26)*. % 76.16/76.40 204704[95:MRR:840.0,204702.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.40 204707[95:Res:53.1,204704.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.40 204709[96:Spt:204707.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 204711[96:Res:204709.0,61.1] always3(s26) || -> . % 76.16/76.40 204712[96:SSi:204711.0,78182.0,78186.0,192125.0,204206.0,204702.0] || -> . % 76.16/76.40 204713[96:Spt:204712.0,204707.0,204709.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.40 204714[96:Spt:204712.0,204707.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 204718[96:Res:204714.0,61.1] always3(s27) || -> . % 76.16/76.40 204719[96:SSi:204718.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.40 204720[94:Spt:204719.0,204205.0,204206.0] || until2p7(s26)*+ -> . % 76.16/76.40 204721[94:Spt:204719.0,204205.1] || -> node4(s25)*. % 76.16/76.40 204723[94:MRR:843.0,204721.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.40 204726[94:Res:53.1,204723.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.40 204728[95:Spt:204726.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 204730[95:Res:204728.0,61.1] always3(s25) || -> . % 76.16/76.40 204731[95:SSi:204730.0,78178.0,78181.0,192124.0,204204.0,204721.0] || -> . % 76.16/76.40 204732[95:Spt:204731.0,204726.0,204728.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.40 204733[95:Spt:204731.0,204726.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 204737[95:Res:204733.0,61.1] always3(s26) || -> . % 76.16/76.40 204738[95:SSi:204737.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.40 204739[93:Spt:204738.0,204203.0,204204.0] || until2p7(s25)*+ -> . % 76.16/76.40 204740[93:Spt:204738.0,204203.1] || -> node4(s24)*. % 76.16/76.40 204742[93:MRR:846.0,204740.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.40 204745[93:Res:53.1,204742.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.40 204747[94:Spt:204745.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 204749[94:Res:204747.0,61.1] always3(s24) || -> . % 76.16/76.40 204750[94:SSi:204749.0,78173.0,78177.0,192123.0,204202.0,204740.0] || -> . % 76.16/76.40 204751[94:Spt:204750.0,204745.0,204747.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.40 204752[94:Spt:204750.0,204745.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 204756[94:Res:204752.0,61.1] always3(s25) || -> . % 76.16/76.40 204757[94:SSi:204756.0,78178.0,78181.0,192124.0] || -> . % 76.16/76.40 204758[92:Spt:204757.0,204201.0,204202.0] || until2p7(s24)*+ -> . % 76.16/76.40 204759[92:Spt:204757.0,204201.1] || -> node4(s23)*. % 76.16/76.40 204761[92:MRR:849.0,204759.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.40 204764[92:Res:53.1,204761.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.40 204769[93:Spt:204764.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 204771[93:Res:204769.0,61.1] always3(s23) || -> . % 76.16/76.40 204772[93:SSi:204771.0,78169.0,78172.0,192122.0,204200.0,204759.0] || -> . % 76.16/76.40 204773[93:Spt:204772.0,204764.0,204769.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.40 204774[93:Spt:204772.0,204764.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 204778[93:Res:204774.0,61.1] always3(s24) || -> . % 76.16/76.40 204779[93:SSi:204778.0,78173.0,78177.0,192123.0] || -> . % 76.16/76.40 204780[91:Spt:204779.0,204199.0,204200.0] || until2p7(s23)*+ -> . % 76.16/76.40 204781[91:Spt:204779.0,204199.1] || -> node4(s22)*. % 76.16/76.40 204783[91:MRR:852.0,204781.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.40 204786[91:Res:53.1,204783.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.40 204788[92:Spt:204786.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 204790[92:Res:204788.0,61.1] always3(s22) || -> . % 76.16/76.40 204791[92:SSi:204790.0,78164.0,78168.0,192121.0,204198.0,204781.0] || -> . % 76.16/76.40 204792[92:Spt:204791.0,204786.0,204788.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.40 204793[92:Spt:204791.0,204786.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 204797[92:Res:204793.0,61.1] always3(s23) || -> . % 76.16/76.40 204798[92:SSi:204797.0,78169.0,78172.0,192122.0] || -> . % 76.16/76.40 204799[90:Spt:204798.0,204197.0,204198.0] || until2p7(s22)*+ -> . % 76.16/76.40 204800[90:Spt:204798.0,204197.1] || -> node4(s21)*. % 76.16/76.40 204802[90:MRR:855.0,204800.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.40 204805[90:Res:53.1,204802.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.40 204807[91:Spt:204805.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 204809[91:Res:204807.0,61.1] always3(s21) || -> . % 76.16/76.40 204810[91:SSi:204809.0,78160.0,78163.0,192120.0,204196.0,204800.0] || -> . % 76.16/76.40 204811[91:Spt:204810.0,204805.0,204807.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.40 204812[91:Spt:204810.0,204805.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 204816[91:Res:204812.0,61.1] always3(s22) || -> . % 76.16/76.40 204817[91:SSi:204816.0,78164.0,78168.0,192121.0] || -> . % 76.16/76.40 204818[89:Spt:204817.0,204195.0,204196.0] || until2p7(s21)*+ -> . % 76.16/76.40 204819[89:Spt:204817.0,204195.1] || -> node4(s20)*. % 76.16/76.40 204821[89:MRR:858.0,204819.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.40 204824[89:Res:53.1,204821.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.40 204826[90:Spt:204824.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 204828[90:Res:204826.0,61.1] always3(s20) || -> . % 76.16/76.40 204829[90:SSi:204828.0,78155.0,78159.0,192119.0,204194.0,204819.0] || -> . % 76.16/76.40 204830[90:Spt:204829.0,204824.0,204826.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.40 204831[90:Spt:204829.0,204824.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 204835[90:Res:204831.0,61.1] always3(s21) || -> . % 76.16/76.40 204836[90:SSi:204835.0,78160.0,78163.0,192120.0] || -> . % 76.16/76.40 204837[88:Spt:204836.0,204193.0,204194.0] || until2p7(s20)*+ -> . % 76.16/76.40 204838[88:Spt:204836.0,204193.1] || -> node4(s19)*. % 76.16/76.40 204840[88:MRR:861.0,204838.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.40 204843[88:Res:53.1,204840.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.40 204845[88:MRR:204843.0,204183.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 204850[88:Res:204845.0,61.1] always3(s20) || -> . % 76.16/76.40 204851[88:SSi:204850.0,78155.0,78159.0,192119.0] || -> . % 76.16/76.40 204852[86:Spt:204851.0,204065.0,204068.0] || trans(s49,s19)*+ -> . % 76.16/76.40 204853[86:Spt:204851.0,204065.1,204065.2,204065.3,204065.4,204065.5,204065.6,204065.7,204065.8,204065.9,204065.10,204065.11,204065.12,204065.13] || -> trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.40 204855[86:MRR:204067.1,204852.0] xuntil6(s49) || -> trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.40 204856[87:Spt:204853.0] || -> trans(s49,s18)*. % 76.16/76.40 204857[87:Res:204856.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s18)*. % 76.16/76.40 204859[87:Res:204856.0,60.0] || -> node2(s49,s18)*. % 76.16/76.40 204860[87:SSi:204857.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s18)*. % 76.16/76.40 204861[87:Res:204859.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)*. % 76.16/76.40 204964[87:SoR:204861.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)*. % 76.16/76.40 204966[87:SoR:204964.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s18,c_busy)* xuntil6(s49). % 76.16/76.40 204967[87:SSi:204966.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s18,c_busy)* xuntil6(s49). % 76.16/76.40 204968[88:Spt:204967.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.40 204970[88:Res:204968.0,61.1] always3(s18) || -> . % 76.16/76.40 204971[88:SSi:204970.0,78146.0,78150.0,192117.0] || -> . % 76.16/76.40 204972[88:Spt:204971.0,204967.1,204968.0] || m_main_v_state(s18,c_busy)*+ -> . % 76.16/76.40 204973[88:Spt:204971.0,204967.0,204967.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.40 204977[88:MRR:204964.2,204972.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.40 204978[88:Res:53.1,204973.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.40 204980[88:MRR:204978.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.40 204981[88:MRR:204860.0,204980.0] || -> until2p7(s18)*. % 76.16/76.40 204982[88:MRR:214.0,204981.0] || -> until2p7(s19)* node4(s18). % 76.16/76.40 204983[89:Spt:204982.0] || -> until2p7(s19)*. % 76.16/76.40 204984[89:MRR:215.0,204983.0] || -> until2p7(s20)* node4(s19). % 76.16/76.40 204985[90:Spt:204984.0] || -> until2p7(s20)*. % 76.16/76.40 204986[90:MRR:216.0,204985.0] || -> until2p7(s21)* node4(s20). % 76.16/76.40 204987[91:Spt:204986.0] || -> until2p7(s21)*. % 76.16/76.40 204988[91:MRR:217.0,204987.0] || -> until2p7(s22)* node4(s21). % 76.16/76.40 204989[92:Spt:204988.0] || -> until2p7(s22)*. % 76.16/76.40 204990[92:MRR:218.0,204989.0] || -> until2p7(s23)* node4(s22). % 76.16/76.40 204991[93:Spt:204990.0] || -> until2p7(s23)*. % 76.16/76.40 204992[93:MRR:219.0,204991.0] || -> until2p7(s24)* node4(s23). % 76.16/76.40 204993[94:Spt:204992.0] || -> until2p7(s24)*. % 76.16/76.40 204994[94:MRR:220.0,204993.0] || -> until2p7(s25)* node4(s24). % 76.16/76.40 204995[95:Spt:204994.0] || -> until2p7(s25)*. % 76.16/76.40 204996[95:MRR:221.0,204995.0] || -> until2p7(s26)* node4(s25). % 76.16/76.40 204997[96:Spt:204996.0] || -> until2p7(s26)*. % 76.16/76.40 204998[96:MRR:222.0,204997.0] || -> until2p7(s27)* node4(s26). % 76.16/76.40 204999[97:Spt:204998.0] || -> until2p7(s27)*. % 76.16/76.40 205000[97:MRR:223.0,204999.0] || -> until2p7(s28)* node4(s27). % 76.16/76.40 205001[98:Spt:205000.0] || -> until2p7(s28)*. % 76.16/76.40 205002[98:MRR:224.0,205001.0] || -> until2p7(s29)* node4(s28). % 76.16/76.40 205003[99:Spt:205002.0] || -> until2p7(s29)*. % 76.16/76.40 205004[99:MRR:225.0,205003.0] || -> until2p7(s30)* node4(s29). % 76.16/76.40 205005[100:Spt:205004.0] || -> until2p7(s30)*. % 76.16/76.40 205006[100:MRR:226.0,205005.0] || -> until2p7(s31)* node4(s30). % 76.16/76.40 205007[101:Spt:205006.0] || -> until2p7(s31)*. % 76.16/76.40 205008[101:MRR:227.0,205007.0] || -> until2p7(s32)* node4(s31). % 76.16/76.40 205009[102:Spt:205008.0] || -> until2p7(s32)*. % 76.16/76.40 205010[102:MRR:228.0,205009.0] || -> until2p7(s33)* node4(s32). % 76.16/76.40 205011[103:Spt:205010.0] || -> until2p7(s33)*. % 76.16/76.40 205012[103:MRR:229.0,205011.0] || -> until2p7(s34)* node4(s33). % 76.16/76.40 205013[104:Spt:205012.0] || -> until2p7(s34)*. % 76.16/76.40 205014[104:MRR:230.0,205013.0] || -> until2p7(s35)* node4(s34). % 76.16/76.40 205015[105:Spt:205014.0] || -> until2p7(s35)*. % 76.16/76.40 205016[105:MRR:231.0,205015.0] || -> until2p7(s36)* node4(s35). % 76.16/76.40 205017[106:Spt:205016.0] || -> until2p7(s36)*. % 76.16/76.40 205018[106:MRR:232.0,205017.0] || -> until2p7(s37)* node4(s36). % 76.16/76.40 205019[107:Spt:205018.0] || -> until2p7(s37)*. % 76.16/76.40 205020[107:MRR:235.0,205019.0] || -> until2p7(s38)* node4(s37). % 76.16/76.40 205021[108:Spt:205020.0] || -> until2p7(s38)*. % 76.16/76.40 205022[108:MRR:236.0,205021.0] || -> until2p7(s39)* node4(s38). % 76.16/76.40 205023[109:Spt:205022.0] || -> until2p7(s39)*. % 76.16/76.40 205024[109:MRR:237.0,205023.0] || -> until2p7(s40)* node4(s39). % 76.16/76.40 205025[110:Spt:205024.0] || -> until2p7(s40)*. % 76.16/76.40 205026[110:MRR:238.0,205025.0] || -> until2p7(s41)* node4(s40). % 76.16/76.40 205027[111:Spt:205026.0] || -> until2p7(s41)*. % 76.16/76.40 205028[111:MRR:239.0,205027.0] || -> until2p7(s42)* node4(s41). % 76.16/76.40 205029[112:Spt:205028.0] || -> until2p7(s42)*. % 76.16/76.40 205030[112:MRR:240.0,205029.0] || -> until2p7(s43)* node4(s42). % 76.16/76.40 205031[113:Spt:205030.0] || -> until2p7(s43)*. % 76.16/76.40 205032[113:MRR:241.0,205031.0] || -> until2p7(s44)* node4(s43). % 76.16/76.40 205033[114:Spt:205032.0] || -> until2p7(s44)*. % 76.16/76.40 205034[114:MRR:539.0,205033.0] || -> until2p7(s45)* node4(s44). % 76.16/76.40 205035[115:Spt:205034.0] || -> until2p7(s45)*. % 76.16/76.40 205036[115:MRR:544.0,205035.0] || -> until2p7(s46)* node4(s45). % 76.16/76.40 205037[116:Spt:205036.0] || -> until2p7(s46)*. % 76.16/76.40 205038[116:MRR:549.0,205037.0] || -> until2p7(s47)* node4(s46). % 76.16/76.40 205039[117:Spt:205038.0] || -> until2p7(s47)*. % 76.16/76.40 205040[117:MRR:554.0,205039.0] || -> until2p7(s48)* node4(s47). % 76.16/76.40 205041[118:Spt:205040.0] || -> until2p7(s48)*. % 76.16/76.40 205042[118:MRR:559.0,205041.0] || -> until2p7(s49)* node4(s48). % 76.16/76.40 205043[119:Spt:205042.0] || -> until2p7(s49)*. % 76.16/76.40 205044[119:MRR:194.0,205043.0] || -> node4(s49)*. % 76.16/76.40 205045[119:MRR:204977.0,205044.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.40 205049[119:Res:53.1,205045.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.40 205051[119:MRR:205049.0,78381.0] || -> . % 76.16/76.40 205052[119:Spt:205051.0,205042.0,205043.0] || until2p7(s49)*+ -> . % 76.16/76.40 205053[119:Spt:205051.0,205042.1] || -> node4(s48)*. % 76.16/76.40 205054[119:MRR:78384.0,205053.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.40 205057[119:Res:53.1,205054.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 205060[119:Res:205057.0,61.1] always3(s48) || -> . % 76.16/76.40 205061[119:SSi:205060.0,78281.0,78387.0,192147.0,205041.0,205053.0] || -> . % 76.16/76.40 205062[118:Spt:205061.0,205040.0,205041.0] || until2p7(s48)*+ -> . % 76.16/76.40 205063[118:Spt:205061.0,205040.1] || -> node4(s47)*. % 76.16/76.40 205065[118:MRR:777.0,205063.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.40 205077[118:Res:53.1,205065.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.40 205079[119:Spt:205077.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 205081[119:Res:205079.0,61.1] always3(s47) || -> . % 76.16/76.40 205082[119:SSi:205081.0,78277.0,78280.0,192146.0,205039.0,205063.0] || -> . % 76.16/76.40 205083[119:Spt:205082.0,205077.0,205079.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.40 205084[119:Spt:205082.0,205077.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 205088[119:Res:205084.0,61.1] always3(s48) || -> . % 76.16/76.40 205089[119:SSi:205088.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.40 205090[117:Spt:205089.0,205038.0,205039.0] || until2p7(s47)*+ -> . % 76.16/76.40 205091[117:Spt:205089.0,205038.1] || -> node4(s46)*. % 76.16/76.40 205093[117:MRR:780.0,205091.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.40 205100[117:Res:53.1,205093.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.40 205105[118:Spt:205100.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 205107[118:Res:205105.0,61.1] always3(s46) || -> . % 76.16/76.40 205108[118:SSi:205107.0,78272.0,78276.0,192145.0,205037.0,205091.0] || -> . % 76.16/76.40 205109[118:Spt:205108.0,205100.0,205105.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.40 205110[118:Spt:205108.0,205100.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 205114[118:Res:205110.0,61.1] always3(s47) || -> . % 76.16/76.40 205115[118:SSi:205114.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.40 205116[116:Spt:205115.0,205036.0,205037.0] || until2p7(s46)*+ -> . % 76.16/76.40 205117[116:Spt:205115.0,205036.1] || -> node4(s45)*. % 76.16/76.40 205119[116:MRR:783.0,205117.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.40 205122[116:Res:53.1,205119.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.40 205124[117:Spt:205122.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 205126[117:Res:205124.0,61.1] always3(s45) || -> . % 76.16/76.40 205127[117:SSi:205126.0,78268.0,78271.0,192144.0,205035.0,205117.0] || -> . % 76.16/76.40 205128[117:Spt:205127.0,205122.0,205124.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.40 205129[117:Spt:205127.0,205122.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 205133[117:Res:205129.0,61.1] always3(s46) || -> . % 76.16/76.40 205134[117:SSi:205133.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.40 205135[115:Spt:205134.0,205034.0,205035.0] || until2p7(s45)*+ -> . % 76.16/76.40 205136[115:Spt:205134.0,205034.1] || -> node4(s44)*. % 76.16/76.40 205138[115:MRR:786.0,205136.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.40 205141[115:Res:53.1,205138.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.40 205143[116:Spt:205141.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 205145[116:Res:205143.0,61.1] always3(s44) || -> . % 76.16/76.40 205146[116:SSi:205145.0,78263.0,78267.0,192143.0,205033.0,205136.0] || -> . % 76.16/76.40 205147[116:Spt:205146.0,205141.0,205143.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.40 205148[116:Spt:205146.0,205141.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 205152[116:Res:205148.0,61.1] always3(s45) || -> . % 76.16/76.40 205153[116:SSi:205152.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.40 205154[114:Spt:205153.0,205032.0,205033.0] || until2p7(s44)*+ -> . % 76.16/76.40 205155[114:Spt:205153.0,205032.1] || -> node4(s43)*. % 76.16/76.40 205157[114:MRR:789.0,205155.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.40 205160[114:Res:53.1,205157.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.40 205162[115:Spt:205160.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 205164[115:Res:205162.0,61.1] always3(s43) || -> . % 76.16/76.40 205165[115:SSi:205164.0,78259.0,78262.0,192142.0,205031.0,205155.0] || -> . % 76.16/76.40 205166[115:Spt:205165.0,205160.0,205162.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.40 205167[115:Spt:205165.0,205160.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 205171[115:Res:205167.0,61.1] always3(s44) || -> . % 76.16/76.40 205172[115:SSi:205171.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.40 205173[113:Spt:205172.0,205030.0,205031.0] || until2p7(s43)*+ -> . % 76.16/76.40 205174[113:Spt:205172.0,205030.1] || -> node4(s42)*. % 76.16/76.40 205176[113:MRR:792.0,205174.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.40 205179[113:Res:53.1,205176.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.40 205184[114:Spt:205179.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 205186[114:Res:205184.0,61.1] always3(s42) || -> . % 76.16/76.40 205187[114:SSi:205186.0,78254.0,78258.0,192141.0,205029.0,205174.0] || -> . % 76.16/76.40 205188[114:Spt:205187.0,205179.0,205184.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.40 205189[114:Spt:205187.0,205179.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 205193[114:Res:205189.0,61.1] always3(s43) || -> . % 76.16/76.40 205194[114:SSi:205193.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.40 205195[112:Spt:205194.0,205028.0,205029.0] || until2p7(s42)*+ -> . % 76.16/76.40 205196[112:Spt:205194.0,205028.1] || -> node4(s41)*. % 76.16/76.40 205198[112:MRR:795.0,205196.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.40 205201[112:Res:53.1,205198.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.40 205203[113:Spt:205201.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 205205[113:Res:205203.0,61.1] always3(s41) || -> . % 76.16/76.40 205206[113:SSi:205205.0,78250.0,78253.0,192140.0,205027.0,205196.0] || -> . % 76.16/76.40 205207[113:Spt:205206.0,205201.0,205203.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.40 205208[113:Spt:205206.0,205201.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 205212[113:Res:205208.0,61.1] always3(s42) || -> . % 76.16/76.40 205213[113:SSi:205212.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.40 205214[111:Spt:205213.0,205026.0,205027.0] || until2p7(s41)*+ -> . % 76.16/76.40 205215[111:Spt:205213.0,205026.1] || -> node4(s40)*. % 76.16/76.40 205217[111:MRR:798.0,205215.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.40 205220[111:Res:53.1,205217.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.40 205222[112:Spt:205220.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 205224[112:Res:205222.0,61.1] always3(s40) || -> . % 76.16/76.40 205225[112:SSi:205224.0,78245.0,78249.0,192139.0,205025.0,205215.0] || -> . % 76.16/76.40 205226[112:Spt:205225.0,205220.0,205222.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.40 205227[112:Spt:205225.0,205220.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 205231[112:Res:205227.0,61.1] always3(s41) || -> . % 76.16/76.40 205232[112:SSi:205231.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.40 205233[110:Spt:205232.0,205024.0,205025.0] || until2p7(s40)*+ -> . % 76.16/76.40 205234[110:Spt:205232.0,205024.1] || -> node4(s39)*. % 76.16/76.40 205236[110:MRR:801.0,205234.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.40 205239[110:Res:53.1,205236.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.40 205241[111:Spt:205239.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 205243[111:Res:205241.0,61.1] always3(s39) || -> . % 76.16/76.40 205244[111:SSi:205243.0,78241.0,78244.0,192138.0,205023.0,205234.0] || -> . % 76.16/76.40 205245[111:Spt:205244.0,205239.0,205241.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.40 205246[111:Spt:205244.0,205239.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 205250[111:Res:205246.0,61.1] always3(s40) || -> . % 76.16/76.40 205251[111:SSi:205250.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.40 205252[109:Spt:205251.0,205022.0,205023.0] || until2p7(s39)*+ -> . % 76.16/76.40 205253[109:Spt:205251.0,205022.1] || -> node4(s38)*. % 76.16/76.40 205255[109:MRR:804.0,205253.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.40 205258[109:Res:53.1,205255.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.40 205263[110:Spt:205258.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 205265[110:Res:205263.0,61.1] always3(s38) || -> . % 76.16/76.40 205266[110:SSi:205265.0,78236.0,78240.0,192137.0,205021.0,205253.0] || -> . % 76.16/76.40 205267[110:Spt:205266.0,205258.0,205263.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.40 205268[110:Spt:205266.0,205258.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 205272[110:Res:205268.0,61.1] always3(s39) || -> . % 76.16/76.40 205273[110:SSi:205272.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.40 205274[108:Spt:205273.0,205020.0,205021.0] || until2p7(s38)*+ -> . % 76.16/76.40 205275[108:Spt:205273.0,205020.1] || -> node4(s37)*. % 76.16/76.40 205277[108:MRR:807.0,205275.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.40 205280[108:Res:53.1,205277.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.40 205282[109:Spt:205280.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 205284[109:Res:205282.0,61.1] always3(s37) || -> . % 76.16/76.40 205285[109:SSi:205284.0,78232.0,78235.0,192136.0,205019.0,205275.0] || -> . % 76.16/76.40 205286[109:Spt:205285.0,205280.0,205282.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.40 205287[109:Spt:205285.0,205280.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 205291[109:Res:205287.0,61.1] always3(s38) || -> . % 76.16/76.40 205292[109:SSi:205291.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.40 205293[107:Spt:205292.0,205018.0,205019.0] || until2p7(s37)*+ -> . % 76.16/76.40 205294[107:Spt:205292.0,205018.1] || -> node4(s36)*. % 76.16/76.40 205296[107:MRR:810.0,205294.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.40 205299[107:Res:53.1,205296.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.40 205301[108:Spt:205299.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 205303[108:Res:205301.0,61.1] always3(s36) || -> . % 76.16/76.40 205304[108:SSi:205303.0,78227.0,78231.0,192135.0,205017.0,205294.0] || -> . % 76.16/76.40 205305[108:Spt:205304.0,205299.0,205301.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.40 205306[108:Spt:205304.0,205299.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 205310[108:Res:205306.0,61.1] always3(s37) || -> . % 76.16/76.40 205311[108:SSi:205310.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.40 205312[106:Spt:205311.0,205016.0,205017.0] || until2p7(s36)*+ -> . % 76.16/76.40 205313[106:Spt:205311.0,205016.1] || -> node4(s35)*. % 76.16/76.40 205315[106:MRR:813.0,205313.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.40 205318[106:Res:53.1,205315.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.40 205320[107:Spt:205318.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 205322[107:Res:205320.0,61.1] always3(s35) || -> . % 76.16/76.40 205323[107:SSi:205322.0,78223.0,78226.0,192134.0,205015.0,205313.0] || -> . % 76.16/76.40 205324[107:Spt:205323.0,205318.0,205320.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.40 205325[107:Spt:205323.0,205318.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 205329[107:Res:205325.0,61.1] always3(s36) || -> . % 76.16/76.40 205330[107:SSi:205329.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.40 205331[105:Spt:205330.0,205014.0,205015.0] || until2p7(s35)*+ -> . % 76.16/76.40 205332[105:Spt:205330.0,205014.1] || -> node4(s34)*. % 76.16/76.40 205334[105:MRR:816.0,205332.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.40 205337[105:Res:53.1,205334.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.40 205342[106:Spt:205337.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 205344[106:Res:205342.0,61.1] always3(s34) || -> . % 76.16/76.40 205345[106:SSi:205344.0,78218.0,78222.0,192133.0,205013.0,205332.0] || -> . % 76.16/76.40 205346[106:Spt:205345.0,205337.0,205342.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.40 205347[106:Spt:205345.0,205337.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 205351[106:Res:205347.0,61.1] always3(s35) || -> . % 76.16/76.40 205352[106:SSi:205351.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.40 205353[104:Spt:205352.0,205012.0,205013.0] || until2p7(s34)*+ -> . % 76.16/76.40 205354[104:Spt:205352.0,205012.1] || -> node4(s33)*. % 76.16/76.40 205356[104:MRR:819.0,205354.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.40 205359[104:Res:53.1,205356.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.40 205361[105:Spt:205359.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 205363[105:Res:205361.0,61.1] always3(s33) || -> . % 76.16/76.40 205364[105:SSi:205363.0,78214.0,78217.0,192132.0,205011.0,205354.0] || -> . % 76.16/76.40 205365[105:Spt:205364.0,205359.0,205361.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.40 205366[105:Spt:205364.0,205359.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 205370[105:Res:205366.0,61.1] always3(s34) || -> . % 76.16/76.40 205371[105:SSi:205370.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.40 205372[103:Spt:205371.0,205010.0,205011.0] || until2p7(s33)*+ -> . % 76.16/76.40 205373[103:Spt:205371.0,205010.1] || -> node4(s32)*. % 76.16/76.40 205375[103:MRR:822.0,205373.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.40 205378[103:Res:53.1,205375.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.40 205380[104:Spt:205378.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 205382[104:Res:205380.0,61.1] always3(s32) || -> . % 76.16/76.40 205383[104:SSi:205382.0,78209.0,78213.0,192131.0,205009.0,205373.0] || -> . % 76.16/76.40 205384[104:Spt:205383.0,205378.0,205380.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.40 205385[104:Spt:205383.0,205378.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 205389[104:Res:205385.0,61.1] always3(s33) || -> . % 76.16/76.40 205390[104:SSi:205389.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.40 205391[102:Spt:205390.0,205008.0,205009.0] || until2p7(s32)*+ -> . % 76.16/76.40 205392[102:Spt:205390.0,205008.1] || -> node4(s31)*. % 76.16/76.40 205394[102:MRR:825.0,205392.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.40 205397[102:Res:53.1,205394.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.40 205399[103:Spt:205397.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 205401[103:Res:205399.0,61.1] always3(s31) || -> . % 76.16/76.40 205402[103:SSi:205401.0,78205.0,78208.0,192130.0,205007.0,205392.0] || -> . % 76.16/76.40 205403[103:Spt:205402.0,205397.0,205399.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.40 205404[103:Spt:205402.0,205397.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 205408[103:Res:205404.0,61.1] always3(s32) || -> . % 76.16/76.40 205409[103:SSi:205408.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.40 205410[101:Spt:205409.0,205006.0,205007.0] || until2p7(s31)*+ -> . % 76.16/76.40 205411[101:Spt:205409.0,205006.1] || -> node4(s30)*. % 76.16/76.40 205413[101:MRR:828.0,205411.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.40 205416[101:Res:53.1,205413.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.40 205421[102:Spt:205416.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 205423[102:Res:205421.0,61.1] always3(s30) || -> . % 76.16/76.40 205424[102:SSi:205423.0,78200.0,78204.0,192129.0,205005.0,205411.0] || -> . % 76.16/76.40 205425[102:Spt:205424.0,205416.0,205421.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.40 205426[102:Spt:205424.0,205416.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 205430[102:Res:205426.0,61.1] always3(s31) || -> . % 76.16/76.40 205431[102:SSi:205430.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.40 205432[100:Spt:205431.0,205004.0,205005.0] || until2p7(s30)*+ -> . % 76.16/76.40 205433[100:Spt:205431.0,205004.1] || -> node4(s29)*. % 76.16/76.40 205435[100:MRR:831.0,205433.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.40 205438[100:Res:53.1,205435.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.40 205440[101:Spt:205438.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 205442[101:Res:205440.0,61.1] always3(s29) || -> . % 76.16/76.40 205443[101:SSi:205442.0,78196.0,78199.0,192128.0,205003.0,205433.0] || -> . % 76.16/76.40 205444[101:Spt:205443.0,205438.0,205440.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.40 205445[101:Spt:205443.0,205438.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 205449[101:Res:205445.0,61.1] always3(s30) || -> . % 76.16/76.40 205450[101:SSi:205449.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.40 205451[99:Spt:205450.0,205002.0,205003.0] || until2p7(s29)*+ -> . % 76.16/76.40 205452[99:Spt:205450.0,205002.1] || -> node4(s28)*. % 76.16/76.40 205454[99:MRR:834.0,205452.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.40 205457[99:Res:53.1,205454.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.40 205459[100:Spt:205457.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 205461[100:Res:205459.0,61.1] always3(s28) || -> . % 76.16/76.40 205462[100:SSi:205461.0,78191.0,78195.0,192127.0,205001.0,205452.0] || -> . % 76.16/76.40 205463[100:Spt:205462.0,205457.0,205459.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.40 205464[100:Spt:205462.0,205457.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 205468[100:Res:205464.0,61.1] always3(s29) || -> . % 76.16/76.40 205469[100:SSi:205468.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.40 205470[98:Spt:205469.0,205000.0,205001.0] || until2p7(s28)*+ -> . % 76.16/76.40 205471[98:Spt:205469.0,205000.1] || -> node4(s27)*. % 76.16/76.40 205473[98:MRR:837.0,205471.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.40 205476[98:Res:53.1,205473.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.40 205478[99:Spt:205476.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 205480[99:Res:205478.0,61.1] always3(s27) || -> . % 76.16/76.40 205481[99:SSi:205480.0,78187.0,78190.0,192126.0,204999.0,205471.0] || -> . % 76.16/76.40 205482[99:Spt:205481.0,205476.0,205478.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.40 205483[99:Spt:205481.0,205476.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 205487[99:Res:205483.0,61.1] always3(s28) || -> . % 76.16/76.40 205488[99:SSi:205487.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.40 205489[97:Spt:205488.0,204998.0,204999.0] || until2p7(s27)*+ -> . % 76.16/76.40 205490[97:Spt:205488.0,204998.1] || -> node4(s26)*. % 76.16/76.40 205492[97:MRR:840.0,205490.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.40 205495[97:Res:53.1,205492.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.40 205500[98:Spt:205495.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 205502[98:Res:205500.0,61.1] always3(s26) || -> . % 76.16/76.40 205503[98:SSi:205502.0,78182.0,78186.0,192125.0,204997.0,205490.0] || -> . % 76.16/76.40 205504[98:Spt:205503.0,205495.0,205500.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.40 205505[98:Spt:205503.0,205495.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 205509[98:Res:205505.0,61.1] always3(s27) || -> . % 76.16/76.40 205510[98:SSi:205509.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.40 205511[96:Spt:205510.0,204996.0,204997.0] || until2p7(s26)*+ -> . % 76.16/76.40 205512[96:Spt:205510.0,204996.1] || -> node4(s25)*. % 76.16/76.40 205514[96:MRR:843.0,205512.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.40 205517[96:Res:53.1,205514.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.40 205519[97:Spt:205517.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 205521[97:Res:205519.0,61.1] always3(s25) || -> . % 76.16/76.40 205522[97:SSi:205521.0,78178.0,78181.0,192124.0,204995.0,205512.0] || -> . % 76.16/76.40 205523[97:Spt:205522.0,205517.0,205519.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.40 205524[97:Spt:205522.0,205517.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 205528[97:Res:205524.0,61.1] always3(s26) || -> . % 76.16/76.40 205529[97:SSi:205528.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.40 205530[95:Spt:205529.0,204994.0,204995.0] || until2p7(s25)*+ -> . % 76.16/76.40 205531[95:Spt:205529.0,204994.1] || -> node4(s24)*. % 76.16/76.40 205533[95:MRR:846.0,205531.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.40 205536[95:Res:53.1,205533.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.40 205538[96:Spt:205536.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 205540[96:Res:205538.0,61.1] always3(s24) || -> . % 76.16/76.40 205541[96:SSi:205540.0,78173.0,78177.0,192123.0,204993.0,205531.0] || -> . % 76.16/76.40 205542[96:Spt:205541.0,205536.0,205538.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.40 205543[96:Spt:205541.0,205536.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 205547[96:Res:205543.0,61.1] always3(s25) || -> . % 76.16/76.40 205548[96:SSi:205547.0,78178.0,78181.0,192124.0] || -> . % 76.16/76.40 205549[94:Spt:205548.0,204992.0,204993.0] || until2p7(s24)*+ -> . % 76.16/76.40 205550[94:Spt:205548.0,204992.1] || -> node4(s23)*. % 76.16/76.40 205552[94:MRR:849.0,205550.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.40 205555[94:Res:53.1,205552.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.40 205557[95:Spt:205555.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 205559[95:Res:205557.0,61.1] always3(s23) || -> . % 76.16/76.40 205560[95:SSi:205559.0,78169.0,78172.0,192122.0,204991.0,205550.0] || -> . % 76.16/76.40 205561[95:Spt:205560.0,205555.0,205557.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.40 205562[95:Spt:205560.0,205555.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 205566[95:Res:205562.0,61.1] always3(s24) || -> . % 76.16/76.40 205567[95:SSi:205566.0,78173.0,78177.0,192123.0] || -> . % 76.16/76.40 205568[93:Spt:205567.0,204990.0,204991.0] || until2p7(s23)*+ -> . % 76.16/76.40 205569[93:Spt:205567.0,204990.1] || -> node4(s22)*. % 76.16/76.40 205571[93:MRR:852.0,205569.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.40 205574[93:Res:53.1,205571.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.40 205579[94:Spt:205574.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 205581[94:Res:205579.0,61.1] always3(s22) || -> . % 76.16/76.40 205582[94:SSi:205581.0,78164.0,78168.0,192121.0,204989.0,205569.0] || -> . % 76.16/76.40 205583[94:Spt:205582.0,205574.0,205579.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.40 205584[94:Spt:205582.0,205574.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 205588[94:Res:205584.0,61.1] always3(s23) || -> . % 76.16/76.40 205589[94:SSi:205588.0,78169.0,78172.0,192122.0] || -> . % 76.16/76.40 205590[92:Spt:205589.0,204988.0,204989.0] || until2p7(s22)*+ -> . % 76.16/76.40 205591[92:Spt:205589.0,204988.1] || -> node4(s21)*. % 76.16/76.40 205593[92:MRR:855.0,205591.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.40 205596[92:Res:53.1,205593.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.40 205598[93:Spt:205596.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 205600[93:Res:205598.0,61.1] always3(s21) || -> . % 76.16/76.40 205601[93:SSi:205600.0,78160.0,78163.0,192120.0,204987.0,205591.0] || -> . % 76.16/76.40 205602[93:Spt:205601.0,205596.0,205598.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.40 205603[93:Spt:205601.0,205596.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 205607[93:Res:205603.0,61.1] always3(s22) || -> . % 76.16/76.40 205608[93:SSi:205607.0,78164.0,78168.0,192121.0] || -> . % 76.16/76.40 205609[91:Spt:205608.0,204986.0,204987.0] || until2p7(s21)*+ -> . % 76.16/76.40 205610[91:Spt:205608.0,204986.1] || -> node4(s20)*. % 76.16/76.40 205612[91:MRR:858.0,205610.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.40 205615[91:Res:53.1,205612.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.40 205617[92:Spt:205615.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 205619[92:Res:205617.0,61.1] always3(s20) || -> . % 76.16/76.40 205620[92:SSi:205619.0,78155.0,78159.0,192119.0,204985.0,205610.0] || -> . % 76.16/76.40 205621[92:Spt:205620.0,205615.0,205617.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.40 205622[92:Spt:205620.0,205615.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 205626[92:Res:205622.0,61.1] always3(s21) || -> . % 76.16/76.40 205627[92:SSi:205626.0,78160.0,78163.0,192120.0] || -> . % 76.16/76.40 205628[90:Spt:205627.0,204984.0,204985.0] || until2p7(s20)*+ -> . % 76.16/76.40 205629[90:Spt:205627.0,204984.1] || -> node4(s19)*. % 76.16/76.40 205631[90:MRR:861.0,205629.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.40 205634[90:Res:53.1,205631.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.40 205636[91:Spt:205634.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.40 205638[91:Res:205636.0,61.1] always3(s19) || -> . % 76.16/76.40 205639[91:SSi:205638.0,78151.0,78154.0,192118.0,204983.0,205629.0] || -> . % 76.16/76.40 205640[91:Spt:205639.0,205634.0,205636.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.40 205641[91:Spt:205639.0,205634.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 205645[91:Res:205641.0,61.1] always3(s20) || -> . % 76.16/76.40 205646[91:SSi:205645.0,78155.0,78159.0,192119.0] || -> . % 76.16/76.40 205647[89:Spt:205646.0,204982.0,204983.0] || until2p7(s19)*+ -> . % 76.16/76.40 205648[89:Spt:205646.0,204982.1] || -> node4(s18)*. % 76.16/76.40 205650[89:MRR:864.0,205648.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.40 205653[89:Res:53.1,205650.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.40 205655[89:MRR:205653.0,204972.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.40 205660[89:Res:205655.0,61.1] always3(s19) || -> . % 76.16/76.40 205661[89:SSi:205660.0,78151.0,78154.0,192118.0] || -> . % 76.16/76.40 205662[87:Spt:205661.0,204853.0,204856.0] || trans(s49,s18)*+ -> . % 76.16/76.40 205663[87:Spt:205661.0,204853.1,204853.2,204853.3,204853.4,204853.5,204853.6,204853.7,204853.8,204853.9,204853.10,204853.11,204853.12] || -> trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.40 205665[87:MRR:204855.1,205662.0] xuntil6(s49) || -> trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.40 205666[88:Spt:205663.0] || -> trans(s49,s17)*. % 76.16/76.40 205667[88:Res:205666.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s17)*. % 76.16/76.40 205669[88:Res:205666.0,60.0] || -> node2(s49,s17)*. % 76.16/76.40 205670[88:SSi:205667.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s17)*. % 76.16/76.40 205671[88:Res:205669.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)*. % 76.16/76.40 205778[88:SoR:205671.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)*. % 76.16/76.40 205780[88:SoR:205778.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s17,c_busy)* xuntil6(s49). % 76.16/76.40 205781[88:SSi:205780.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s17,c_busy)* xuntil6(s49). % 76.16/76.40 205782[89:Spt:205781.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.40 205784[89:Res:205782.0,61.1] always3(s17) || -> . % 76.16/76.40 205785[89:SSi:205784.0,78142.0,78145.0,192116.0] || -> . % 76.16/76.40 205786[89:Spt:205785.0,205781.1,205782.0] || m_main_v_state(s17,c_busy)*+ -> . % 76.16/76.40 205787[89:Spt:205785.0,205781.0,205781.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.40 205791[89:MRR:205778.2,205786.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.40 205792[89:Res:53.1,205787.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.40 205794[89:MRR:205792.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.40 205795[89:MRR:205670.0,205794.0] || -> until2p7(s17)*. % 76.16/76.40 205796[89:MRR:213.0,205795.0] || -> until2p7(s18)* node4(s17). % 76.16/76.40 205797[90:Spt:205796.0] || -> until2p7(s18)*. % 76.16/76.40 205798[90:MRR:214.0,205797.0] || -> until2p7(s19)* node4(s18). % 76.16/76.40 205799[91:Spt:205798.0] || -> until2p7(s19)*. % 76.16/76.40 205800[91:MRR:215.0,205799.0] || -> until2p7(s20)* node4(s19). % 76.16/76.40 205801[92:Spt:205800.0] || -> until2p7(s20)*. % 76.16/76.40 205802[92:MRR:216.0,205801.0] || -> until2p7(s21)* node4(s20). % 76.16/76.40 205803[93:Spt:205802.0] || -> until2p7(s21)*. % 76.16/76.40 205804[93:MRR:217.0,205803.0] || -> until2p7(s22)* node4(s21). % 76.16/76.40 205805[94:Spt:205804.0] || -> until2p7(s22)*. % 76.16/76.40 205806[94:MRR:218.0,205805.0] || -> until2p7(s23)* node4(s22). % 76.16/76.40 205807[95:Spt:205806.0] || -> until2p7(s23)*. % 76.16/76.40 205808[95:MRR:219.0,205807.0] || -> until2p7(s24)* node4(s23). % 76.16/76.40 205809[96:Spt:205808.0] || -> until2p7(s24)*. % 76.16/76.40 205810[96:MRR:220.0,205809.0] || -> until2p7(s25)* node4(s24). % 76.16/76.40 205811[97:Spt:205810.0] || -> until2p7(s25)*. % 76.16/76.40 205812[97:MRR:221.0,205811.0] || -> until2p7(s26)* node4(s25). % 76.16/76.40 205813[98:Spt:205812.0] || -> until2p7(s26)*. % 76.16/76.40 205814[98:MRR:222.0,205813.0] || -> until2p7(s27)* node4(s26). % 76.16/76.40 205815[99:Spt:205814.0] || -> until2p7(s27)*. % 76.16/76.40 205816[99:MRR:223.0,205815.0] || -> until2p7(s28)* node4(s27). % 76.16/76.40 205817[100:Spt:205816.0] || -> until2p7(s28)*. % 76.16/76.40 205818[100:MRR:224.0,205817.0] || -> until2p7(s29)* node4(s28). % 76.16/76.40 205819[101:Spt:205818.0] || -> until2p7(s29)*. % 76.16/76.40 205820[101:MRR:225.0,205819.0] || -> until2p7(s30)* node4(s29). % 76.16/76.40 205821[102:Spt:205820.0] || -> until2p7(s30)*. % 76.16/76.40 205822[102:MRR:226.0,205821.0] || -> until2p7(s31)* node4(s30). % 76.16/76.40 205823[103:Spt:205822.0] || -> until2p7(s31)*. % 76.16/76.40 205824[103:MRR:227.0,205823.0] || -> until2p7(s32)* node4(s31). % 76.16/76.40 205825[104:Spt:205824.0] || -> until2p7(s32)*. % 76.16/76.40 205826[104:MRR:228.0,205825.0] || -> until2p7(s33)* node4(s32). % 76.16/76.40 205827[105:Spt:205826.0] || -> until2p7(s33)*. % 76.16/76.40 205828[105:MRR:229.0,205827.0] || -> until2p7(s34)* node4(s33). % 76.16/76.40 205829[106:Spt:205828.0] || -> until2p7(s34)*. % 76.16/76.40 205830[106:MRR:230.0,205829.0] || -> until2p7(s35)* node4(s34). % 76.16/76.40 205831[107:Spt:205830.0] || -> until2p7(s35)*. % 76.16/76.40 205832[107:MRR:231.0,205831.0] || -> until2p7(s36)* node4(s35). % 76.16/76.40 205833[108:Spt:205832.0] || -> until2p7(s36)*. % 76.16/76.40 205834[108:MRR:232.0,205833.0] || -> until2p7(s37)* node4(s36). % 76.16/76.40 205835[109:Spt:205834.0] || -> until2p7(s37)*. % 76.16/76.40 205836[109:MRR:235.0,205835.0] || -> until2p7(s38)* node4(s37). % 76.16/76.40 205837[110:Spt:205836.0] || -> until2p7(s38)*. % 76.16/76.40 205838[110:MRR:236.0,205837.0] || -> until2p7(s39)* node4(s38). % 76.16/76.40 205839[111:Spt:205838.0] || -> until2p7(s39)*. % 76.16/76.40 205840[111:MRR:237.0,205839.0] || -> until2p7(s40)* node4(s39). % 76.16/76.40 205841[112:Spt:205840.0] || -> until2p7(s40)*. % 76.16/76.40 205842[112:MRR:238.0,205841.0] || -> until2p7(s41)* node4(s40). % 76.16/76.40 205843[113:Spt:205842.0] || -> until2p7(s41)*. % 76.16/76.40 205844[113:MRR:239.0,205843.0] || -> until2p7(s42)* node4(s41). % 76.16/76.40 205845[114:Spt:205844.0] || -> until2p7(s42)*. % 76.16/76.40 205846[114:MRR:240.0,205845.0] || -> until2p7(s43)* node4(s42). % 76.16/76.40 205847[115:Spt:205846.0] || -> until2p7(s43)*. % 76.16/76.40 205848[115:MRR:241.0,205847.0] || -> until2p7(s44)* node4(s43). % 76.16/76.40 205849[116:Spt:205848.0] || -> until2p7(s44)*. % 76.16/76.40 205850[116:MRR:539.0,205849.0] || -> until2p7(s45)* node4(s44). % 76.16/76.40 205851[117:Spt:205850.0] || -> until2p7(s45)*. % 76.16/76.40 205852[117:MRR:544.0,205851.0] || -> until2p7(s46)* node4(s45). % 76.16/76.40 205853[118:Spt:205852.0] || -> until2p7(s46)*. % 76.16/76.40 205854[118:MRR:549.0,205853.0] || -> until2p7(s47)* node4(s46). % 76.16/76.40 205855[119:Spt:205854.0] || -> until2p7(s47)*. % 76.16/76.40 205856[119:MRR:554.0,205855.0] || -> until2p7(s48)* node4(s47). % 76.16/76.40 205857[120:Spt:205856.0] || -> until2p7(s48)*. % 76.16/76.40 205858[120:MRR:559.0,205857.0] || -> until2p7(s49)* node4(s48). % 76.16/76.40 205859[121:Spt:205858.0] || -> until2p7(s49)*. % 76.16/76.40 205860[121:MRR:194.0,205859.0] || -> node4(s49)*. % 76.16/76.40 205861[121:MRR:205791.0,205860.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.40 205862[121:Res:53.1,205861.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.40 205864[121:MRR:205862.0,78381.0] || -> . % 76.16/76.40 205865[121:Spt:205864.0,205858.0,205859.0] || until2p7(s49)*+ -> . % 76.16/76.40 205866[121:Spt:205864.0,205858.1] || -> node4(s48)*. % 76.16/76.40 205867[121:MRR:78384.0,205866.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.40 205870[121:Res:53.1,205867.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 205873[121:Res:205870.0,61.1] always3(s48) || -> . % 76.16/76.40 205874[121:SSi:205873.0,78281.0,78387.0,192147.0,205857.0,205866.0] || -> . % 76.16/76.40 205875[120:Spt:205874.0,205856.0,205857.0] || until2p7(s48)*+ -> . % 76.16/76.40 205876[120:Spt:205874.0,205856.1] || -> node4(s47)*. % 76.16/76.40 205878[120:MRR:777.0,205876.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.40 205893[120:Res:53.1,205878.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.40 205898[121:Spt:205893.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 205900[121:Res:205898.0,61.1] always3(s47) || -> . % 76.16/76.40 205901[121:SSi:205900.0,78277.0,78280.0,192146.0,205855.0,205876.0] || -> . % 76.16/76.40 205902[121:Spt:205901.0,205893.0,205898.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.40 205903[121:Spt:205901.0,205893.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 205907[121:Res:205903.0,61.1] always3(s48) || -> . % 76.16/76.40 205908[121:SSi:205907.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.40 205909[119:Spt:205908.0,205854.0,205855.0] || until2p7(s47)*+ -> . % 76.16/76.40 205910[119:Spt:205908.0,205854.1] || -> node4(s46)*. % 76.16/76.40 205912[119:MRR:780.0,205910.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.40 205919[119:Res:53.1,205912.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.40 205921[120:Spt:205919.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 205923[120:Res:205921.0,61.1] always3(s46) || -> . % 76.16/76.40 205924[120:SSi:205923.0,78272.0,78276.0,192145.0,205853.0,205910.0] || -> . % 76.16/76.40 205925[120:Spt:205924.0,205919.0,205921.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.40 205926[120:Spt:205924.0,205919.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 205930[120:Res:205926.0,61.1] always3(s47) || -> . % 76.16/76.40 205931[120:SSi:205930.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.40 205932[118:Spt:205931.0,205852.0,205853.0] || until2p7(s46)*+ -> . % 76.16/76.40 205933[118:Spt:205931.0,205852.1] || -> node4(s45)*. % 76.16/76.40 205935[118:MRR:783.0,205933.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.40 205938[118:Res:53.1,205935.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.40 205943[119:Spt:205938.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 205945[119:Res:205943.0,61.1] always3(s45) || -> . % 76.16/76.40 205946[119:SSi:205945.0,78268.0,78271.0,192144.0,205851.0,205933.0] || -> . % 76.16/76.40 205947[119:Spt:205946.0,205938.0,205943.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.40 205948[119:Spt:205946.0,205938.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 205952[119:Res:205948.0,61.1] always3(s46) || -> . % 76.16/76.40 205953[119:SSi:205952.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.40 205954[117:Spt:205953.0,205850.0,205851.0] || until2p7(s45)*+ -> . % 76.16/76.40 205955[117:Spt:205953.0,205850.1] || -> node4(s44)*. % 76.16/76.40 205957[117:MRR:786.0,205955.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.40 205960[117:Res:53.1,205957.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.40 205962[118:Spt:205960.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 205964[118:Res:205962.0,61.1] always3(s44) || -> . % 76.16/76.40 205965[118:SSi:205964.0,78263.0,78267.0,192143.0,205849.0,205955.0] || -> . % 76.16/76.40 205966[118:Spt:205965.0,205960.0,205962.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.40 205967[118:Spt:205965.0,205960.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 205971[118:Res:205967.0,61.1] always3(s45) || -> . % 76.16/76.40 205972[118:SSi:205971.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.40 205973[116:Spt:205972.0,205848.0,205849.0] || until2p7(s44)*+ -> . % 76.16/76.40 205974[116:Spt:205972.0,205848.1] || -> node4(s43)*. % 76.16/76.40 205976[116:MRR:789.0,205974.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.40 205979[116:Res:53.1,205976.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.40 205981[117:Spt:205979.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 205983[117:Res:205981.0,61.1] always3(s43) || -> . % 76.16/76.40 205984[117:SSi:205983.0,78259.0,78262.0,192142.0,205847.0,205974.0] || -> . % 76.16/76.40 205985[117:Spt:205984.0,205979.0,205981.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.40 205986[117:Spt:205984.0,205979.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 205990[117:Res:205986.0,61.1] always3(s44) || -> . % 76.16/76.40 205991[117:SSi:205990.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.40 205992[115:Spt:205991.0,205846.0,205847.0] || until2p7(s43)*+ -> . % 76.16/76.40 205993[115:Spt:205991.0,205846.1] || -> node4(s42)*. % 76.16/76.40 205995[115:MRR:792.0,205993.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.40 205998[115:Res:53.1,205995.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.40 206000[116:Spt:205998.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 206002[116:Res:206000.0,61.1] always3(s42) || -> . % 76.16/76.40 206003[116:SSi:206002.0,78254.0,78258.0,192141.0,205845.0,205993.0] || -> . % 76.16/76.40 206004[116:Spt:206003.0,205998.0,206000.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.40 206005[116:Spt:206003.0,205998.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 206009[116:Res:206005.0,61.1] always3(s43) || -> . % 76.16/76.40 206010[116:SSi:206009.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.40 206011[114:Spt:206010.0,205844.0,205845.0] || until2p7(s42)*+ -> . % 76.16/76.40 206012[114:Spt:206010.0,205844.1] || -> node4(s41)*. % 76.16/76.40 206014[114:MRR:795.0,206012.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.40 206017[114:Res:53.1,206014.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.40 206022[115:Spt:206017.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 206024[115:Res:206022.0,61.1] always3(s41) || -> . % 76.16/76.40 206025[115:SSi:206024.0,78250.0,78253.0,192140.0,205843.0,206012.0] || -> . % 76.16/76.40 206026[115:Spt:206025.0,206017.0,206022.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.40 206027[115:Spt:206025.0,206017.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 206031[115:Res:206027.0,61.1] always3(s42) || -> . % 76.16/76.40 206032[115:SSi:206031.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.40 206033[113:Spt:206032.0,205842.0,205843.0] || until2p7(s41)*+ -> . % 76.16/76.40 206034[113:Spt:206032.0,205842.1] || -> node4(s40)*. % 76.16/76.40 206036[113:MRR:798.0,206034.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.40 206039[113:Res:53.1,206036.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.40 206041[114:Spt:206039.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 206043[114:Res:206041.0,61.1] always3(s40) || -> . % 76.16/76.40 206044[114:SSi:206043.0,78245.0,78249.0,192139.0,205841.0,206034.0] || -> . % 76.16/76.40 206045[114:Spt:206044.0,206039.0,206041.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.40 206046[114:Spt:206044.0,206039.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 206050[114:Res:206046.0,61.1] always3(s41) || -> . % 76.16/76.40 206051[114:SSi:206050.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.40 206052[112:Spt:206051.0,205840.0,205841.0] || until2p7(s40)*+ -> . % 76.16/76.40 206053[112:Spt:206051.0,205840.1] || -> node4(s39)*. % 76.16/76.40 206055[112:MRR:801.0,206053.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.40 206058[112:Res:53.1,206055.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.40 206060[113:Spt:206058.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 206062[113:Res:206060.0,61.1] always3(s39) || -> . % 76.16/76.40 206063[113:SSi:206062.0,78241.0,78244.0,192138.0,205839.0,206053.0] || -> . % 76.16/76.40 206064[113:Spt:206063.0,206058.0,206060.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.40 206065[113:Spt:206063.0,206058.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 206069[113:Res:206065.0,61.1] always3(s40) || -> . % 76.16/76.40 206070[113:SSi:206069.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.40 206071[111:Spt:206070.0,205838.0,205839.0] || until2p7(s39)*+ -> . % 76.16/76.40 206072[111:Spt:206070.0,205838.1] || -> node4(s38)*. % 76.16/76.40 206074[111:MRR:804.0,206072.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.40 206077[111:Res:53.1,206074.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.40 206079[112:Spt:206077.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 206081[112:Res:206079.0,61.1] always3(s38) || -> . % 76.16/76.40 206082[112:SSi:206081.0,78236.0,78240.0,192137.0,205837.0,206072.0] || -> . % 76.16/76.40 206083[112:Spt:206082.0,206077.0,206079.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.40 206084[112:Spt:206082.0,206077.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 206088[112:Res:206084.0,61.1] always3(s39) || -> . % 76.16/76.40 206089[112:SSi:206088.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.40 206090[110:Spt:206089.0,205836.0,205837.0] || until2p7(s38)*+ -> . % 76.16/76.40 206091[110:Spt:206089.0,205836.1] || -> node4(s37)*. % 76.16/76.40 206093[110:MRR:807.0,206091.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.40 206096[110:Res:53.1,206093.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.40 206101[111:Spt:206096.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 206103[111:Res:206101.0,61.1] always3(s37) || -> . % 76.16/76.40 206104[111:SSi:206103.0,78232.0,78235.0,192136.0,205835.0,206091.0] || -> . % 76.16/76.40 206105[111:Spt:206104.0,206096.0,206101.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.40 206106[111:Spt:206104.0,206096.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 206110[111:Res:206106.0,61.1] always3(s38) || -> . % 76.16/76.40 206111[111:SSi:206110.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.40 206112[109:Spt:206111.0,205834.0,205835.0] || until2p7(s37)*+ -> . % 76.16/76.40 206113[109:Spt:206111.0,205834.1] || -> node4(s36)*. % 76.16/76.40 206115[109:MRR:810.0,206113.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.40 206118[109:Res:53.1,206115.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.40 206120[110:Spt:206118.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 206122[110:Res:206120.0,61.1] always3(s36) || -> . % 76.16/76.40 206123[110:SSi:206122.0,78227.0,78231.0,192135.0,205833.0,206113.0] || -> . % 76.16/76.40 206124[110:Spt:206123.0,206118.0,206120.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.40 206125[110:Spt:206123.0,206118.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 206129[110:Res:206125.0,61.1] always3(s37) || -> . % 76.16/76.40 206130[110:SSi:206129.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.40 206131[108:Spt:206130.0,205832.0,205833.0] || until2p7(s36)*+ -> . % 76.16/76.40 206132[108:Spt:206130.0,205832.1] || -> node4(s35)*. % 76.16/76.40 206134[108:MRR:813.0,206132.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.40 206137[108:Res:53.1,206134.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.40 206139[109:Spt:206137.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 206141[109:Res:206139.0,61.1] always3(s35) || -> . % 76.16/76.40 206142[109:SSi:206141.0,78223.0,78226.0,192134.0,205831.0,206132.0] || -> . % 76.16/76.40 206143[109:Spt:206142.0,206137.0,206139.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.40 206144[109:Spt:206142.0,206137.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 206148[109:Res:206144.0,61.1] always3(s36) || -> . % 76.16/76.40 206149[109:SSi:206148.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.40 206150[107:Spt:206149.0,205830.0,205831.0] || until2p7(s35)*+ -> . % 76.16/76.40 206151[107:Spt:206149.0,205830.1] || -> node4(s34)*. % 76.16/76.40 206153[107:MRR:816.0,206151.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.40 206156[107:Res:53.1,206153.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.40 206158[108:Spt:206156.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 206160[108:Res:206158.0,61.1] always3(s34) || -> . % 76.16/76.40 206161[108:SSi:206160.0,78218.0,78222.0,192133.0,205829.0,206151.0] || -> . % 76.16/76.40 206162[108:Spt:206161.0,206156.0,206158.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.40 206163[108:Spt:206161.0,206156.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 206167[108:Res:206163.0,61.1] always3(s35) || -> . % 76.16/76.40 206168[108:SSi:206167.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.40 206169[106:Spt:206168.0,205828.0,205829.0] || until2p7(s34)*+ -> . % 76.16/76.40 206170[106:Spt:206168.0,205828.1] || -> node4(s33)*. % 76.16/76.40 206172[106:MRR:819.0,206170.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.40 206175[106:Res:53.1,206172.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.40 206180[107:Spt:206175.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 206182[107:Res:206180.0,61.1] always3(s33) || -> . % 76.16/76.40 206183[107:SSi:206182.0,78214.0,78217.0,192132.0,205827.0,206170.0] || -> . % 76.16/76.40 206184[107:Spt:206183.0,206175.0,206180.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.40 206185[107:Spt:206183.0,206175.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 206189[107:Res:206185.0,61.1] always3(s34) || -> . % 76.16/76.40 206190[107:SSi:206189.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.40 206191[105:Spt:206190.0,205826.0,205827.0] || until2p7(s33)*+ -> . % 76.16/76.40 206192[105:Spt:206190.0,205826.1] || -> node4(s32)*. % 76.16/76.40 206194[105:MRR:822.0,206192.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.40 206197[105:Res:53.1,206194.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.40 206199[106:Spt:206197.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 206201[106:Res:206199.0,61.1] always3(s32) || -> . % 76.16/76.40 206202[106:SSi:206201.0,78209.0,78213.0,192131.0,205825.0,206192.0] || -> . % 76.16/76.40 206203[106:Spt:206202.0,206197.0,206199.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.40 206204[106:Spt:206202.0,206197.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 206208[106:Res:206204.0,61.1] always3(s33) || -> . % 76.16/76.40 206209[106:SSi:206208.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.40 206210[104:Spt:206209.0,205824.0,205825.0] || until2p7(s32)*+ -> . % 76.16/76.40 206211[104:Spt:206209.0,205824.1] || -> node4(s31)*. % 76.16/76.40 206213[104:MRR:825.0,206211.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.40 206216[104:Res:53.1,206213.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.40 206218[105:Spt:206216.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 206220[105:Res:206218.0,61.1] always3(s31) || -> . % 76.16/76.40 206221[105:SSi:206220.0,78205.0,78208.0,192130.0,205823.0,206211.0] || -> . % 76.16/76.40 206222[105:Spt:206221.0,206216.0,206218.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.40 206223[105:Spt:206221.0,206216.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 206227[105:Res:206223.0,61.1] always3(s32) || -> . % 76.16/76.40 206228[105:SSi:206227.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.40 206229[103:Spt:206228.0,205822.0,205823.0] || until2p7(s31)*+ -> . % 76.16/76.40 206230[103:Spt:206228.0,205822.1] || -> node4(s30)*. % 76.16/76.40 206232[103:MRR:828.0,206230.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.40 206235[103:Res:53.1,206232.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.40 206237[104:Spt:206235.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 206239[104:Res:206237.0,61.1] always3(s30) || -> . % 76.16/76.40 206240[104:SSi:206239.0,78200.0,78204.0,192129.0,205821.0,206230.0] || -> . % 76.16/76.40 206241[104:Spt:206240.0,206235.0,206237.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.40 206242[104:Spt:206240.0,206235.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 206246[104:Res:206242.0,61.1] always3(s31) || -> . % 76.16/76.40 206247[104:SSi:206246.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.40 206248[102:Spt:206247.0,205820.0,205821.0] || until2p7(s30)*+ -> . % 76.16/76.40 206249[102:Spt:206247.0,205820.1] || -> node4(s29)*. % 76.16/76.40 206251[102:MRR:831.0,206249.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.40 206254[102:Res:53.1,206251.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.40 206259[103:Spt:206254.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 206261[103:Res:206259.0,61.1] always3(s29) || -> . % 76.16/76.40 206262[103:SSi:206261.0,78196.0,78199.0,192128.0,205819.0,206249.0] || -> . % 76.16/76.40 206263[103:Spt:206262.0,206254.0,206259.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.40 206264[103:Spt:206262.0,206254.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 206268[103:Res:206264.0,61.1] always3(s30) || -> . % 76.16/76.40 206269[103:SSi:206268.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.40 206270[101:Spt:206269.0,205818.0,205819.0] || until2p7(s29)*+ -> . % 76.16/76.40 206271[101:Spt:206269.0,205818.1] || -> node4(s28)*. % 76.16/76.40 206273[101:MRR:834.0,206271.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.40 206276[101:Res:53.1,206273.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.40 206278[102:Spt:206276.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 206280[102:Res:206278.0,61.1] always3(s28) || -> . % 76.16/76.40 206281[102:SSi:206280.0,78191.0,78195.0,192127.0,205817.0,206271.0] || -> . % 76.16/76.40 206282[102:Spt:206281.0,206276.0,206278.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.40 206283[102:Spt:206281.0,206276.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 206287[102:Res:206283.0,61.1] always3(s29) || -> . % 76.16/76.40 206288[102:SSi:206287.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.40 206289[100:Spt:206288.0,205816.0,205817.0] || until2p7(s28)*+ -> . % 76.16/76.40 206290[100:Spt:206288.0,205816.1] || -> node4(s27)*. % 76.16/76.40 206292[100:MRR:837.0,206290.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.40 206295[100:Res:53.1,206292.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.40 206297[101:Spt:206295.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 206299[101:Res:206297.0,61.1] always3(s27) || -> . % 76.16/76.40 206300[101:SSi:206299.0,78187.0,78190.0,192126.0,205815.0,206290.0] || -> . % 76.16/76.40 206301[101:Spt:206300.0,206295.0,206297.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.40 206302[101:Spt:206300.0,206295.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 206306[101:Res:206302.0,61.1] always3(s28) || -> . % 76.16/76.40 206307[101:SSi:206306.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.40 206308[99:Spt:206307.0,205814.0,205815.0] || until2p7(s27)*+ -> . % 76.16/76.40 206309[99:Spt:206307.0,205814.1] || -> node4(s26)*. % 76.16/76.40 206311[99:MRR:840.0,206309.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.40 206314[99:Res:53.1,206311.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.40 206316[100:Spt:206314.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 206318[100:Res:206316.0,61.1] always3(s26) || -> . % 76.16/76.40 206319[100:SSi:206318.0,78182.0,78186.0,192125.0,205813.0,206309.0] || -> . % 76.16/76.40 206320[100:Spt:206319.0,206314.0,206316.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.40 206321[100:Spt:206319.0,206314.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 206325[100:Res:206321.0,61.1] always3(s27) || -> . % 76.16/76.40 206326[100:SSi:206325.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.40 206327[98:Spt:206326.0,205812.0,205813.0] || until2p7(s26)*+ -> . % 76.16/76.40 206328[98:Spt:206326.0,205812.1] || -> node4(s25)*. % 76.16/76.40 206330[98:MRR:843.0,206328.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.40 206333[98:Res:53.1,206330.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.40 206338[99:Spt:206333.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 206340[99:Res:206338.0,61.1] always3(s25) || -> . % 76.16/76.40 206341[99:SSi:206340.0,78178.0,78181.0,192124.0,205811.0,206328.0] || -> . % 76.16/76.40 206342[99:Spt:206341.0,206333.0,206338.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.40 206343[99:Spt:206341.0,206333.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 206347[99:Res:206343.0,61.1] always3(s26) || -> . % 76.16/76.40 206348[99:SSi:206347.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.40 206349[97:Spt:206348.0,205810.0,205811.0] || until2p7(s25)*+ -> . % 76.16/76.40 206350[97:Spt:206348.0,205810.1] || -> node4(s24)*. % 76.16/76.40 206352[97:MRR:846.0,206350.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.40 206355[97:Res:53.1,206352.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.40 206357[98:Spt:206355.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 206359[98:Res:206357.0,61.1] always3(s24) || -> . % 76.16/76.40 206360[98:SSi:206359.0,78173.0,78177.0,192123.0,205809.0,206350.0] || -> . % 76.16/76.40 206361[98:Spt:206360.0,206355.0,206357.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.40 206362[98:Spt:206360.0,206355.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 206366[98:Res:206362.0,61.1] always3(s25) || -> . % 76.16/76.40 206367[98:SSi:206366.0,78178.0,78181.0,192124.0] || -> . % 76.16/76.40 206368[96:Spt:206367.0,205808.0,205809.0] || until2p7(s24)*+ -> . % 76.16/76.40 206369[96:Spt:206367.0,205808.1] || -> node4(s23)*. % 76.16/76.40 206371[96:MRR:849.0,206369.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.40 206374[96:Res:53.1,206371.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.40 206376[97:Spt:206374.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 206378[97:Res:206376.0,61.1] always3(s23) || -> . % 76.16/76.40 206379[97:SSi:206378.0,78169.0,78172.0,192122.0,205807.0,206369.0] || -> . % 76.16/76.40 206380[97:Spt:206379.0,206374.0,206376.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.40 206381[97:Spt:206379.0,206374.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 206385[97:Res:206381.0,61.1] always3(s24) || -> . % 76.16/76.40 206386[97:SSi:206385.0,78173.0,78177.0,192123.0] || -> . % 76.16/76.40 206387[95:Spt:206386.0,205806.0,205807.0] || until2p7(s23)*+ -> . % 76.16/76.40 206388[95:Spt:206386.0,205806.1] || -> node4(s22)*. % 76.16/76.40 206390[95:MRR:852.0,206388.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.40 206393[95:Res:53.1,206390.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.40 206395[96:Spt:206393.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 206397[96:Res:206395.0,61.1] always3(s22) || -> . % 76.16/76.40 206398[96:SSi:206397.0,78164.0,78168.0,192121.0,205805.0,206388.0] || -> . % 76.16/76.40 206399[96:Spt:206398.0,206393.0,206395.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.40 206400[96:Spt:206398.0,206393.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 206404[96:Res:206400.0,61.1] always3(s23) || -> . % 76.16/76.40 206405[96:SSi:206404.0,78169.0,78172.0,192122.0] || -> . % 76.16/76.40 206406[94:Spt:206405.0,205804.0,205805.0] || until2p7(s22)*+ -> . % 76.16/76.40 206407[94:Spt:206405.0,205804.1] || -> node4(s21)*. % 76.16/76.40 206409[94:MRR:855.0,206407.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.40 206412[94:Res:53.1,206409.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.40 206417[95:Spt:206412.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 206419[95:Res:206417.0,61.1] always3(s21) || -> . % 76.16/76.40 206420[95:SSi:206419.0,78160.0,78163.0,192120.0,205803.0,206407.0] || -> . % 76.16/76.40 206421[95:Spt:206420.0,206412.0,206417.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.40 206422[95:Spt:206420.0,206412.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 206426[95:Res:206422.0,61.1] always3(s22) || -> . % 76.16/76.40 206427[95:SSi:206426.0,78164.0,78168.0,192121.0] || -> . % 76.16/76.40 206428[93:Spt:206427.0,205802.0,205803.0] || until2p7(s21)*+ -> . % 76.16/76.40 206429[93:Spt:206427.0,205802.1] || -> node4(s20)*. % 76.16/76.40 206431[93:MRR:858.0,206429.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.40 206434[93:Res:53.1,206431.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.40 206436[94:Spt:206434.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 206438[94:Res:206436.0,61.1] always3(s20) || -> . % 76.16/76.40 206439[94:SSi:206438.0,78155.0,78159.0,192119.0,205801.0,206429.0] || -> . % 76.16/76.40 206440[94:Spt:206439.0,206434.0,206436.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.40 206441[94:Spt:206439.0,206434.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 206445[94:Res:206441.0,61.1] always3(s21) || -> . % 76.16/76.40 206446[94:SSi:206445.0,78160.0,78163.0,192120.0] || -> . % 76.16/76.40 206447[92:Spt:206446.0,205800.0,205801.0] || until2p7(s20)*+ -> . % 76.16/76.40 206448[92:Spt:206446.0,205800.1] || -> node4(s19)*. % 76.16/76.40 206450[92:MRR:861.0,206448.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.40 206453[92:Res:53.1,206450.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.40 206455[93:Spt:206453.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.40 206457[93:Res:206455.0,61.1] always3(s19) || -> . % 76.16/76.40 206458[93:SSi:206457.0,78151.0,78154.0,192118.0,205799.0,206448.0] || -> . % 76.16/76.40 206459[93:Spt:206458.0,206453.0,206455.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.40 206460[93:Spt:206458.0,206453.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 206464[93:Res:206460.0,61.1] always3(s20) || -> . % 76.16/76.40 206465[93:SSi:206464.0,78155.0,78159.0,192119.0] || -> . % 76.16/76.40 206466[91:Spt:206465.0,205798.0,205799.0] || until2p7(s19)*+ -> . % 76.16/76.40 206467[91:Spt:206465.0,205798.1] || -> node4(s18)*. % 76.16/76.40 206469[91:MRR:864.0,206467.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.40 206472[91:Res:53.1,206469.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.40 206474[92:Spt:206472.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.40 206476[92:Res:206474.0,61.1] always3(s18) || -> . % 76.16/76.40 206477[92:SSi:206476.0,78146.0,78150.0,192117.0,205797.0,206467.0] || -> . % 76.16/76.40 206478[92:Spt:206477.0,206472.0,206474.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.40 206479[92:Spt:206477.0,206472.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.40 206483[92:Res:206479.0,61.1] always3(s19) || -> . % 76.16/76.40 206484[92:SSi:206483.0,78151.0,78154.0,192118.0] || -> . % 76.16/76.40 206485[90:Spt:206484.0,205796.0,205797.0] || until2p7(s18)*+ -> . % 76.16/76.40 206486[90:Spt:206484.0,205796.1] || -> node4(s17)*. % 76.16/76.40 206488[90:MRR:867.0,206486.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.40 206491[90:Res:53.1,206488.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.40 206493[90:MRR:206491.0,205786.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.40 206498[90:Res:206493.0,61.1] always3(s18) || -> . % 76.16/76.40 206499[90:SSi:206498.0,78146.0,78150.0,192117.0] || -> . % 76.16/76.40 206500[88:Spt:206499.0,205663.0,205666.0] || trans(s49,s17)*+ -> . % 76.16/76.40 206501[88:Spt:206499.0,205663.1,205663.2,205663.3,205663.4,205663.5,205663.6,205663.7,205663.8,205663.9,205663.10,205663.11] || -> trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.40 206503[88:MRR:205665.1,206500.0] xuntil6(s49) || -> trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.40 206504[89:Spt:206501.0] || -> trans(s49,s16)*. % 76.16/76.40 206505[89:Res:206504.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s16)*. % 76.16/76.40 206507[89:Res:206504.0,60.0] || -> node2(s49,s16)*. % 76.16/76.40 206508[89:SSi:206505.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s16)*. % 76.16/76.40 206509[89:Res:206507.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)*. % 76.16/76.40 206617[89:SoR:206509.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)*. % 76.16/76.40 206619[89:SoR:206617.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s16,c_busy)* xuntil6(s49). % 76.16/76.40 206620[89:SSi:206619.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s16,c_busy)* xuntil6(s49). % 76.16/76.40 206621[90:Spt:206620.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.40 206623[90:Res:206621.0,61.1] always3(s16) || -> . % 76.16/76.40 206624[90:SSi:206623.0,78137.0,78141.0,192115.0] || -> . % 76.16/76.40 206625[90:Spt:206624.0,206620.1,206621.0] || m_main_v_state(s16,c_busy)*+ -> . % 76.16/76.40 206626[90:Spt:206624.0,206620.0,206620.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.40 206630[90:MRR:206617.2,206625.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.40 206631[90:Res:53.1,206626.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.40 206633[90:MRR:206631.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.40 206634[90:MRR:206508.0,206633.0] || -> until2p7(s16)*. % 76.16/76.40 206635[90:MRR:212.0,206634.0] || -> until2p7(s17)* node4(s16). % 76.16/76.40 206636[91:Spt:206635.0] || -> until2p7(s17)*. % 76.16/76.40 206637[91:MRR:213.0,206636.0] || -> until2p7(s18)* node4(s17). % 76.16/76.40 206638[92:Spt:206637.0] || -> until2p7(s18)*. % 76.16/76.40 206639[92:MRR:214.0,206638.0] || -> until2p7(s19)* node4(s18). % 76.16/76.40 206640[93:Spt:206639.0] || -> until2p7(s19)*. % 76.16/76.40 206641[93:MRR:215.0,206640.0] || -> until2p7(s20)* node4(s19). % 76.16/76.40 206642[94:Spt:206641.0] || -> until2p7(s20)*. % 76.16/76.40 206643[94:MRR:216.0,206642.0] || -> until2p7(s21)* node4(s20). % 76.16/76.40 206644[95:Spt:206643.0] || -> until2p7(s21)*. % 76.16/76.40 206645[95:MRR:217.0,206644.0] || -> until2p7(s22)* node4(s21). % 76.16/76.40 206646[96:Spt:206645.0] || -> until2p7(s22)*. % 76.16/76.40 206647[96:MRR:218.0,206646.0] || -> until2p7(s23)* node4(s22). % 76.16/76.40 206648[97:Spt:206647.0] || -> until2p7(s23)*. % 76.16/76.40 206649[97:MRR:219.0,206648.0] || -> until2p7(s24)* node4(s23). % 76.16/76.40 206650[98:Spt:206649.0] || -> until2p7(s24)*. % 76.16/76.40 206651[98:MRR:220.0,206650.0] || -> until2p7(s25)* node4(s24). % 76.16/76.40 206652[99:Spt:206651.0] || -> until2p7(s25)*. % 76.16/76.40 206653[99:MRR:221.0,206652.0] || -> until2p7(s26)* node4(s25). % 76.16/76.40 206654[100:Spt:206653.0] || -> until2p7(s26)*. % 76.16/76.40 206655[100:MRR:222.0,206654.0] || -> until2p7(s27)* node4(s26). % 76.16/76.40 206656[101:Spt:206655.0] || -> until2p7(s27)*. % 76.16/76.40 206657[101:MRR:223.0,206656.0] || -> until2p7(s28)* node4(s27). % 76.16/76.40 206658[102:Spt:206657.0] || -> until2p7(s28)*. % 76.16/76.40 206659[102:MRR:224.0,206658.0] || -> until2p7(s29)* node4(s28). % 76.16/76.40 206660[103:Spt:206659.0] || -> until2p7(s29)*. % 76.16/76.40 206661[103:MRR:225.0,206660.0] || -> until2p7(s30)* node4(s29). % 76.16/76.40 206662[104:Spt:206661.0] || -> until2p7(s30)*. % 76.16/76.40 206663[104:MRR:226.0,206662.0] || -> until2p7(s31)* node4(s30). % 76.16/76.40 206664[105:Spt:206663.0] || -> until2p7(s31)*. % 76.16/76.40 206665[105:MRR:227.0,206664.0] || -> until2p7(s32)* node4(s31). % 76.16/76.40 206666[106:Spt:206665.0] || -> until2p7(s32)*. % 76.16/76.40 206667[106:MRR:228.0,206666.0] || -> until2p7(s33)* node4(s32). % 76.16/76.40 206668[107:Spt:206667.0] || -> until2p7(s33)*. % 76.16/76.40 206669[107:MRR:229.0,206668.0] || -> until2p7(s34)* node4(s33). % 76.16/76.40 206670[108:Spt:206669.0] || -> until2p7(s34)*. % 76.16/76.40 206671[108:MRR:230.0,206670.0] || -> until2p7(s35)* node4(s34). % 76.16/76.40 206672[109:Spt:206671.0] || -> until2p7(s35)*. % 76.16/76.40 206673[109:MRR:231.0,206672.0] || -> until2p7(s36)* node4(s35). % 76.16/76.40 206674[110:Spt:206673.0] || -> until2p7(s36)*. % 76.16/76.40 206675[110:MRR:232.0,206674.0] || -> until2p7(s37)* node4(s36). % 76.16/76.40 206676[111:Spt:206675.0] || -> until2p7(s37)*. % 76.16/76.40 206677[111:MRR:235.0,206676.0] || -> until2p7(s38)* node4(s37). % 76.16/76.40 206678[112:Spt:206677.0] || -> until2p7(s38)*. % 76.16/76.40 206679[112:MRR:236.0,206678.0] || -> until2p7(s39)* node4(s38). % 76.16/76.40 206680[113:Spt:206679.0] || -> until2p7(s39)*. % 76.16/76.40 206681[113:MRR:237.0,206680.0] || -> until2p7(s40)* node4(s39). % 76.16/76.40 206682[114:Spt:206681.0] || -> until2p7(s40)*. % 76.16/76.40 206683[114:MRR:238.0,206682.0] || -> until2p7(s41)* node4(s40). % 76.16/76.40 206684[115:Spt:206683.0] || -> until2p7(s41)*. % 76.16/76.40 206685[115:MRR:239.0,206684.0] || -> until2p7(s42)* node4(s41). % 76.16/76.40 206686[116:Spt:206685.0] || -> until2p7(s42)*. % 76.16/76.40 206687[116:MRR:240.0,206686.0] || -> until2p7(s43)* node4(s42). % 76.16/76.40 206688[117:Spt:206687.0] || -> until2p7(s43)*. % 76.16/76.40 206689[117:MRR:241.0,206688.0] || -> until2p7(s44)* node4(s43). % 76.16/76.40 206690[118:Spt:206689.0] || -> until2p7(s44)*. % 76.16/76.40 206691[118:MRR:539.0,206690.0] || -> until2p7(s45)* node4(s44). % 76.16/76.40 206692[119:Spt:206691.0] || -> until2p7(s45)*. % 76.16/76.40 206693[119:MRR:544.0,206692.0] || -> until2p7(s46)* node4(s45). % 76.16/76.40 206694[120:Spt:206693.0] || -> until2p7(s46)*. % 76.16/76.40 206695[120:MRR:549.0,206694.0] || -> until2p7(s47)* node4(s46). % 76.16/76.40 206696[121:Spt:206695.0] || -> until2p7(s47)*. % 76.16/76.40 206697[121:MRR:554.0,206696.0] || -> until2p7(s48)* node4(s47). % 76.16/76.40 206698[122:Spt:206697.0] || -> until2p7(s48)*. % 76.16/76.40 206699[122:MRR:559.0,206698.0] || -> until2p7(s49)* node4(s48). % 76.16/76.40 206700[123:Spt:206699.0] || -> until2p7(s49)*. % 76.16/76.40 206701[123:MRR:194.0,206700.0] || -> node4(s49)*. % 76.16/76.40 206702[123:MRR:206630.0,206701.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.40 206706[123:Res:53.1,206702.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.40 206708[123:MRR:206706.0,78381.0] || -> . % 76.16/76.40 206709[123:Spt:206708.0,206699.0,206700.0] || until2p7(s49)*+ -> . % 76.16/76.40 206710[123:Spt:206708.0,206699.1] || -> node4(s48)*. % 76.16/76.40 206711[123:MRR:78384.0,206710.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.40 206714[123:Res:53.1,206711.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 206717[123:Res:206714.0,61.1] always3(s48) || -> . % 76.16/76.40 206718[123:SSi:206717.0,78281.0,78387.0,192147.0,206698.0,206710.0] || -> . % 76.16/76.40 206719[122:Spt:206718.0,206697.0,206698.0] || until2p7(s48)*+ -> . % 76.16/76.40 206720[122:Spt:206718.0,206697.1] || -> node4(s47)*. % 76.16/76.40 206722[122:MRR:777.0,206720.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.40 206734[122:Res:53.1,206722.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.40 206736[123:Spt:206734.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 206738[123:Res:206736.0,61.1] always3(s47) || -> . % 76.16/76.40 206739[123:SSi:206738.0,78277.0,78280.0,192146.0,206696.0,206720.0] || -> . % 76.16/76.40 206740[123:Spt:206739.0,206734.0,206736.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.40 206741[123:Spt:206739.0,206734.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 206745[123:Res:206741.0,61.1] always3(s48) || -> . % 76.16/76.40 206746[123:SSi:206745.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.40 206747[121:Spt:206746.0,206695.0,206696.0] || until2p7(s47)*+ -> . % 76.16/76.40 206748[121:Spt:206746.0,206695.1] || -> node4(s46)*. % 76.16/76.40 206750[121:MRR:780.0,206748.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.40 206757[121:Res:53.1,206750.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.40 206762[122:Spt:206757.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 206764[122:Res:206762.0,61.1] always3(s46) || -> . % 76.16/76.40 206765[122:SSi:206764.0,78272.0,78276.0,192145.0,206694.0,206748.0] || -> . % 76.16/76.40 206766[122:Spt:206765.0,206757.0,206762.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.40 206767[122:Spt:206765.0,206757.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 206771[122:Res:206767.0,61.1] always3(s47) || -> . % 76.16/76.40 206772[122:SSi:206771.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.40 206773[120:Spt:206772.0,206693.0,206694.0] || until2p7(s46)*+ -> . % 76.16/76.40 206774[120:Spt:206772.0,206693.1] || -> node4(s45)*. % 76.16/76.40 206776[120:MRR:783.0,206774.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.40 206779[120:Res:53.1,206776.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.40 206781[121:Spt:206779.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 206783[121:Res:206781.0,61.1] always3(s45) || -> . % 76.16/76.40 206784[121:SSi:206783.0,78268.0,78271.0,192144.0,206692.0,206774.0] || -> . % 76.16/76.40 206785[121:Spt:206784.0,206779.0,206781.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.40 206786[121:Spt:206784.0,206779.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 206790[121:Res:206786.0,61.1] always3(s46) || -> . % 76.16/76.40 206791[121:SSi:206790.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.40 206792[119:Spt:206791.0,206691.0,206692.0] || until2p7(s45)*+ -> . % 76.16/76.40 206793[119:Spt:206791.0,206691.1] || -> node4(s44)*. % 76.16/76.40 206795[119:MRR:786.0,206793.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.40 206798[119:Res:53.1,206795.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.40 206800[120:Spt:206798.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 206802[120:Res:206800.0,61.1] always3(s44) || -> . % 76.16/76.40 206803[120:SSi:206802.0,78263.0,78267.0,192143.0,206690.0,206793.0] || -> . % 76.16/76.40 206804[120:Spt:206803.0,206798.0,206800.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.40 206805[120:Spt:206803.0,206798.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 206809[120:Res:206805.0,61.1] always3(s45) || -> . % 76.16/76.40 206810[120:SSi:206809.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.40 206811[118:Spt:206810.0,206689.0,206690.0] || until2p7(s44)*+ -> . % 76.16/76.40 206812[118:Spt:206810.0,206689.1] || -> node4(s43)*. % 76.16/76.40 206814[118:MRR:789.0,206812.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.40 206817[118:Res:53.1,206814.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.40 206819[119:Spt:206817.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 206821[119:Res:206819.0,61.1] always3(s43) || -> . % 76.16/76.40 206822[119:SSi:206821.0,78259.0,78262.0,192142.0,206688.0,206812.0] || -> . % 76.16/76.40 206823[119:Spt:206822.0,206817.0,206819.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.40 206824[119:Spt:206822.0,206817.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 206828[119:Res:206824.0,61.1] always3(s44) || -> . % 76.16/76.40 206829[119:SSi:206828.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.40 206830[117:Spt:206829.0,206687.0,206688.0] || until2p7(s43)*+ -> . % 76.16/76.40 206831[117:Spt:206829.0,206687.1] || -> node4(s42)*. % 76.16/76.40 206833[117:MRR:792.0,206831.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.40 206836[117:Res:53.1,206833.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.40 206841[118:Spt:206836.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 206843[118:Res:206841.0,61.1] always3(s42) || -> . % 76.16/76.40 206844[118:SSi:206843.0,78254.0,78258.0,192141.0,206686.0,206831.0] || -> . % 76.16/76.40 206845[118:Spt:206844.0,206836.0,206841.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.40 206846[118:Spt:206844.0,206836.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 206850[118:Res:206846.0,61.1] always3(s43) || -> . % 76.16/76.40 206851[118:SSi:206850.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.40 206852[116:Spt:206851.0,206685.0,206686.0] || until2p7(s42)*+ -> . % 76.16/76.40 206853[116:Spt:206851.0,206685.1] || -> node4(s41)*. % 76.16/76.40 206855[116:MRR:795.0,206853.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.40 206858[116:Res:53.1,206855.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.40 206860[117:Spt:206858.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 206862[117:Res:206860.0,61.1] always3(s41) || -> . % 76.16/76.40 206863[117:SSi:206862.0,78250.0,78253.0,192140.0,206684.0,206853.0] || -> . % 76.16/76.40 206864[117:Spt:206863.0,206858.0,206860.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.40 206865[117:Spt:206863.0,206858.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 206869[117:Res:206865.0,61.1] always3(s42) || -> . % 76.16/76.40 206870[117:SSi:206869.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.40 206871[115:Spt:206870.0,206683.0,206684.0] || until2p7(s41)*+ -> . % 76.16/76.40 206872[115:Spt:206870.0,206683.1] || -> node4(s40)*. % 76.16/76.40 206874[115:MRR:798.0,206872.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.40 206877[115:Res:53.1,206874.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.40 206879[116:Spt:206877.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 206881[116:Res:206879.0,61.1] always3(s40) || -> . % 76.16/76.40 206882[116:SSi:206881.0,78245.0,78249.0,192139.0,206682.0,206872.0] || -> . % 76.16/76.40 206883[116:Spt:206882.0,206877.0,206879.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.40 206884[116:Spt:206882.0,206877.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 206888[116:Res:206884.0,61.1] always3(s41) || -> . % 76.16/76.40 206889[116:SSi:206888.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.40 206890[114:Spt:206889.0,206681.0,206682.0] || until2p7(s40)*+ -> . % 76.16/76.40 206891[114:Spt:206889.0,206681.1] || -> node4(s39)*. % 76.16/76.40 206893[114:MRR:801.0,206891.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.40 206896[114:Res:53.1,206893.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.40 206898[115:Spt:206896.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 206900[115:Res:206898.0,61.1] always3(s39) || -> . % 76.16/76.40 206901[115:SSi:206900.0,78241.0,78244.0,192138.0,206680.0,206891.0] || -> . % 76.16/76.40 206902[115:Spt:206901.0,206896.0,206898.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.40 206903[115:Spt:206901.0,206896.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 206907[115:Res:206903.0,61.1] always3(s40) || -> . % 76.16/76.40 206908[115:SSi:206907.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.40 206909[113:Spt:206908.0,206679.0,206680.0] || until2p7(s39)*+ -> . % 76.16/76.40 206910[113:Spt:206908.0,206679.1] || -> node4(s38)*. % 76.16/76.40 206912[113:MRR:804.0,206910.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.40 206915[113:Res:53.1,206912.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.40 206920[114:Spt:206915.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 206922[114:Res:206920.0,61.1] always3(s38) || -> . % 76.16/76.40 206923[114:SSi:206922.0,78236.0,78240.0,192137.0,206678.0,206910.0] || -> . % 76.16/76.40 206924[114:Spt:206923.0,206915.0,206920.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.40 206925[114:Spt:206923.0,206915.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 206929[114:Res:206925.0,61.1] always3(s39) || -> . % 76.16/76.40 206930[114:SSi:206929.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.40 206931[112:Spt:206930.0,206677.0,206678.0] || until2p7(s38)*+ -> . % 76.16/76.40 206932[112:Spt:206930.0,206677.1] || -> node4(s37)*. % 76.16/76.40 206934[112:MRR:807.0,206932.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.40 206937[112:Res:53.1,206934.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.40 206939[113:Spt:206937.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 206941[113:Res:206939.0,61.1] always3(s37) || -> . % 76.16/76.40 206942[113:SSi:206941.0,78232.0,78235.0,192136.0,206676.0,206932.0] || -> . % 76.16/76.40 206943[113:Spt:206942.0,206937.0,206939.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.40 206944[113:Spt:206942.0,206937.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 206948[113:Res:206944.0,61.1] always3(s38) || -> . % 76.16/76.40 206949[113:SSi:206948.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.40 206950[111:Spt:206949.0,206675.0,206676.0] || until2p7(s37)*+ -> . % 76.16/76.40 206951[111:Spt:206949.0,206675.1] || -> node4(s36)*. % 76.16/76.40 206953[111:MRR:810.0,206951.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.40 206956[111:Res:53.1,206953.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.40 206958[112:Spt:206956.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 206960[112:Res:206958.0,61.1] always3(s36) || -> . % 76.16/76.40 206961[112:SSi:206960.0,78227.0,78231.0,192135.0,206674.0,206951.0] || -> . % 76.16/76.40 206962[112:Spt:206961.0,206956.0,206958.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.40 206963[112:Spt:206961.0,206956.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 206967[112:Res:206963.0,61.1] always3(s37) || -> . % 76.16/76.40 206968[112:SSi:206967.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.40 206969[110:Spt:206968.0,206673.0,206674.0] || until2p7(s36)*+ -> . % 76.16/76.40 206970[110:Spt:206968.0,206673.1] || -> node4(s35)*. % 76.16/76.40 206972[110:MRR:813.0,206970.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.40 206975[110:Res:53.1,206972.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.40 206977[111:Spt:206975.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 206979[111:Res:206977.0,61.1] always3(s35) || -> . % 76.16/76.40 206980[111:SSi:206979.0,78223.0,78226.0,192134.0,206672.0,206970.0] || -> . % 76.16/76.40 206981[111:Spt:206980.0,206975.0,206977.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.40 206982[111:Spt:206980.0,206975.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 206986[111:Res:206982.0,61.1] always3(s36) || -> . % 76.16/76.40 206987[111:SSi:206986.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.40 206988[109:Spt:206987.0,206671.0,206672.0] || until2p7(s35)*+ -> . % 76.16/76.40 206989[109:Spt:206987.0,206671.1] || -> node4(s34)*. % 76.16/76.40 206991[109:MRR:816.0,206989.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.40 206994[109:Res:53.1,206991.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.40 206999[110:Spt:206994.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 207001[110:Res:206999.0,61.1] always3(s34) || -> . % 76.16/76.40 207002[110:SSi:207001.0,78218.0,78222.0,192133.0,206670.0,206989.0] || -> . % 76.16/76.40 207003[110:Spt:207002.0,206994.0,206999.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.40 207004[110:Spt:207002.0,206994.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 207008[110:Res:207004.0,61.1] always3(s35) || -> . % 76.16/76.40 207009[110:SSi:207008.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.40 207010[108:Spt:207009.0,206669.0,206670.0] || until2p7(s34)*+ -> . % 76.16/76.40 207011[108:Spt:207009.0,206669.1] || -> node4(s33)*. % 76.16/76.40 207013[108:MRR:819.0,207011.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.40 207016[108:Res:53.1,207013.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.40 207018[109:Spt:207016.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 207020[109:Res:207018.0,61.1] always3(s33) || -> . % 76.16/76.40 207021[109:SSi:207020.0,78214.0,78217.0,192132.0,206668.0,207011.0] || -> . % 76.16/76.40 207022[109:Spt:207021.0,207016.0,207018.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.40 207023[109:Spt:207021.0,207016.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 207027[109:Res:207023.0,61.1] always3(s34) || -> . % 76.16/76.40 207028[109:SSi:207027.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.40 207029[107:Spt:207028.0,206667.0,206668.0] || until2p7(s33)*+ -> . % 76.16/76.40 207030[107:Spt:207028.0,206667.1] || -> node4(s32)*. % 76.16/76.40 207032[107:MRR:822.0,207030.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.40 207035[107:Res:53.1,207032.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.40 207037[108:Spt:207035.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 207039[108:Res:207037.0,61.1] always3(s32) || -> . % 76.16/76.40 207040[108:SSi:207039.0,78209.0,78213.0,192131.0,206666.0,207030.0] || -> . % 76.16/76.40 207041[108:Spt:207040.0,207035.0,207037.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.40 207042[108:Spt:207040.0,207035.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 207046[108:Res:207042.0,61.1] always3(s33) || -> . % 76.16/76.40 207047[108:SSi:207046.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.40 207048[106:Spt:207047.0,206665.0,206666.0] || until2p7(s32)*+ -> . % 76.16/76.40 207049[106:Spt:207047.0,206665.1] || -> node4(s31)*. % 76.16/76.40 207051[106:MRR:825.0,207049.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.40 207054[106:Res:53.1,207051.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.40 207056[107:Spt:207054.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 207058[107:Res:207056.0,61.1] always3(s31) || -> . % 76.16/76.40 207059[107:SSi:207058.0,78205.0,78208.0,192130.0,206664.0,207049.0] || -> . % 76.16/76.40 207060[107:Spt:207059.0,207054.0,207056.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.40 207061[107:Spt:207059.0,207054.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 207065[107:Res:207061.0,61.1] always3(s32) || -> . % 76.16/76.40 207066[107:SSi:207065.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.40 207067[105:Spt:207066.0,206663.0,206664.0] || until2p7(s31)*+ -> . % 76.16/76.40 207068[105:Spt:207066.0,206663.1] || -> node4(s30)*. % 76.16/76.40 207070[105:MRR:828.0,207068.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.40 207073[105:Res:53.1,207070.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.40 207078[106:Spt:207073.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 207080[106:Res:207078.0,61.1] always3(s30) || -> . % 76.16/76.40 207081[106:SSi:207080.0,78200.0,78204.0,192129.0,206662.0,207068.0] || -> . % 76.16/76.40 207082[106:Spt:207081.0,207073.0,207078.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.40 207083[106:Spt:207081.0,207073.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 207087[106:Res:207083.0,61.1] always3(s31) || -> . % 76.16/76.40 207088[106:SSi:207087.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.40 207089[104:Spt:207088.0,206661.0,206662.0] || until2p7(s30)*+ -> . % 76.16/76.40 207090[104:Spt:207088.0,206661.1] || -> node4(s29)*. % 76.16/76.40 207092[104:MRR:831.0,207090.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.40 207095[104:Res:53.1,207092.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.40 207097[105:Spt:207095.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 207099[105:Res:207097.0,61.1] always3(s29) || -> . % 76.16/76.40 207100[105:SSi:207099.0,78196.0,78199.0,192128.0,206660.0,207090.0] || -> . % 76.16/76.40 207101[105:Spt:207100.0,207095.0,207097.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.40 207102[105:Spt:207100.0,207095.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 207106[105:Res:207102.0,61.1] always3(s30) || -> . % 76.16/76.40 207107[105:SSi:207106.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.40 207108[103:Spt:207107.0,206659.0,206660.0] || until2p7(s29)*+ -> . % 76.16/76.40 207109[103:Spt:207107.0,206659.1] || -> node4(s28)*. % 76.16/76.40 207111[103:MRR:834.0,207109.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.40 207114[103:Res:53.1,207111.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.40 207116[104:Spt:207114.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 207118[104:Res:207116.0,61.1] always3(s28) || -> . % 76.16/76.40 207119[104:SSi:207118.0,78191.0,78195.0,192127.0,206658.0,207109.0] || -> . % 76.16/76.40 207120[104:Spt:207119.0,207114.0,207116.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.40 207121[104:Spt:207119.0,207114.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 207125[104:Res:207121.0,61.1] always3(s29) || -> . % 76.16/76.40 207126[104:SSi:207125.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.40 207127[102:Spt:207126.0,206657.0,206658.0] || until2p7(s28)*+ -> . % 76.16/76.40 207128[102:Spt:207126.0,206657.1] || -> node4(s27)*. % 76.16/76.40 207130[102:MRR:837.0,207128.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.40 207133[102:Res:53.1,207130.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.40 207135[103:Spt:207133.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 207137[103:Res:207135.0,61.1] always3(s27) || -> . % 76.16/76.40 207138[103:SSi:207137.0,78187.0,78190.0,192126.0,206656.0,207128.0] || -> . % 76.16/76.40 207139[103:Spt:207138.0,207133.0,207135.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.40 207140[103:Spt:207138.0,207133.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 207144[103:Res:207140.0,61.1] always3(s28) || -> . % 76.16/76.40 207145[103:SSi:207144.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.40 207146[101:Spt:207145.0,206655.0,206656.0] || until2p7(s27)*+ -> . % 76.16/76.40 207147[101:Spt:207145.0,206655.1] || -> node4(s26)*. % 76.16/76.40 207149[101:MRR:840.0,207147.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.40 207152[101:Res:53.1,207149.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.40 207157[102:Spt:207152.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 207159[102:Res:207157.0,61.1] always3(s26) || -> . % 76.16/76.40 207160[102:SSi:207159.0,78182.0,78186.0,192125.0,206654.0,207147.0] || -> . % 76.16/76.40 207161[102:Spt:207160.0,207152.0,207157.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.40 207162[102:Spt:207160.0,207152.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 207166[102:Res:207162.0,61.1] always3(s27) || -> . % 76.16/76.40 207167[102:SSi:207166.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.40 207168[100:Spt:207167.0,206653.0,206654.0] || until2p7(s26)*+ -> . % 76.16/76.40 207169[100:Spt:207167.0,206653.1] || -> node4(s25)*. % 76.16/76.40 207171[100:MRR:843.0,207169.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.40 207174[100:Res:53.1,207171.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.40 207176[101:Spt:207174.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 207178[101:Res:207176.0,61.1] always3(s25) || -> . % 76.16/76.40 207179[101:SSi:207178.0,78178.0,78181.0,192124.0,206652.0,207169.0] || -> . % 76.16/76.40 207180[101:Spt:207179.0,207174.0,207176.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.40 207181[101:Spt:207179.0,207174.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 207185[101:Res:207181.0,61.1] always3(s26) || -> . % 76.16/76.40 207186[101:SSi:207185.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.40 207187[99:Spt:207186.0,206651.0,206652.0] || until2p7(s25)*+ -> . % 76.16/76.40 207188[99:Spt:207186.0,206651.1] || -> node4(s24)*. % 76.16/76.40 207190[99:MRR:846.0,207188.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.40 207193[99:Res:53.1,207190.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.40 207195[100:Spt:207193.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 207197[100:Res:207195.0,61.1] always3(s24) || -> . % 76.16/76.40 207198[100:SSi:207197.0,78173.0,78177.0,192123.0,206650.0,207188.0] || -> . % 76.16/76.40 207199[100:Spt:207198.0,207193.0,207195.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.40 207200[100:Spt:207198.0,207193.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 207204[100:Res:207200.0,61.1] always3(s25) || -> . % 76.16/76.40 207205[100:SSi:207204.0,78178.0,78181.0,192124.0] || -> . % 76.16/76.40 207206[98:Spt:207205.0,206649.0,206650.0] || until2p7(s24)*+ -> . % 76.16/76.40 207207[98:Spt:207205.0,206649.1] || -> node4(s23)*. % 76.16/76.40 207209[98:MRR:849.0,207207.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.40 207212[98:Res:53.1,207209.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.40 207214[99:Spt:207212.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 207216[99:Res:207214.0,61.1] always3(s23) || -> . % 76.16/76.40 207217[99:SSi:207216.0,78169.0,78172.0,192122.0,206648.0,207207.0] || -> . % 76.16/76.40 207218[99:Spt:207217.0,207212.0,207214.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.40 207219[99:Spt:207217.0,207212.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 207223[99:Res:207219.0,61.1] always3(s24) || -> . % 76.16/76.40 207224[99:SSi:207223.0,78173.0,78177.0,192123.0] || -> . % 76.16/76.40 207225[97:Spt:207224.0,206647.0,206648.0] || until2p7(s23)*+ -> . % 76.16/76.40 207226[97:Spt:207224.0,206647.1] || -> node4(s22)*. % 76.16/76.40 207228[97:MRR:852.0,207226.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.40 207231[97:Res:53.1,207228.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.40 207236[98:Spt:207231.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 207238[98:Res:207236.0,61.1] always3(s22) || -> . % 76.16/76.40 207239[98:SSi:207238.0,78164.0,78168.0,192121.0,206646.0,207226.0] || -> . % 76.16/76.40 207240[98:Spt:207239.0,207231.0,207236.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.40 207241[98:Spt:207239.0,207231.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 207245[98:Res:207241.0,61.1] always3(s23) || -> . % 76.16/76.40 207246[98:SSi:207245.0,78169.0,78172.0,192122.0] || -> . % 76.16/76.40 207247[96:Spt:207246.0,206645.0,206646.0] || until2p7(s22)*+ -> . % 76.16/76.40 207248[96:Spt:207246.0,206645.1] || -> node4(s21)*. % 76.16/76.40 207250[96:MRR:855.0,207248.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.40 207253[96:Res:53.1,207250.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.40 207255[97:Spt:207253.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 207257[97:Res:207255.0,61.1] always3(s21) || -> . % 76.16/76.40 207258[97:SSi:207257.0,78160.0,78163.0,192120.0,206644.0,207248.0] || -> . % 76.16/76.40 207259[97:Spt:207258.0,207253.0,207255.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.40 207260[97:Spt:207258.0,207253.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 207264[97:Res:207260.0,61.1] always3(s22) || -> . % 76.16/76.40 207265[97:SSi:207264.0,78164.0,78168.0,192121.0] || -> . % 76.16/76.40 207266[95:Spt:207265.0,206643.0,206644.0] || until2p7(s21)*+ -> . % 76.16/76.40 207267[95:Spt:207265.0,206643.1] || -> node4(s20)*. % 76.16/76.40 207269[95:MRR:858.0,207267.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.40 207272[95:Res:53.1,207269.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.40 207274[96:Spt:207272.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 207276[96:Res:207274.0,61.1] always3(s20) || -> . % 76.16/76.40 207277[96:SSi:207276.0,78155.0,78159.0,192119.0,206642.0,207267.0] || -> . % 76.16/76.40 207278[96:Spt:207277.0,207272.0,207274.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.40 207279[96:Spt:207277.0,207272.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 207283[96:Res:207279.0,61.1] always3(s21) || -> . % 76.16/76.40 207284[96:SSi:207283.0,78160.0,78163.0,192120.0] || -> . % 76.16/76.40 207285[94:Spt:207284.0,206641.0,206642.0] || until2p7(s20)*+ -> . % 76.16/76.40 207286[94:Spt:207284.0,206641.1] || -> node4(s19)*. % 76.16/76.40 207288[94:MRR:861.0,207286.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.40 207291[94:Res:53.1,207288.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.40 207293[95:Spt:207291.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.40 207295[95:Res:207293.0,61.1] always3(s19) || -> . % 76.16/76.40 207296[95:SSi:207295.0,78151.0,78154.0,192118.0,206640.0,207286.0] || -> . % 76.16/76.40 207297[95:Spt:207296.0,207291.0,207293.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.40 207298[95:Spt:207296.0,207291.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 207302[95:Res:207298.0,61.1] always3(s20) || -> . % 76.16/76.40 207303[95:SSi:207302.0,78155.0,78159.0,192119.0] || -> . % 76.16/76.40 207304[93:Spt:207303.0,206639.0,206640.0] || until2p7(s19)*+ -> . % 76.16/76.40 207305[93:Spt:207303.0,206639.1] || -> node4(s18)*. % 76.16/76.40 207307[93:MRR:864.0,207305.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.40 207310[93:Res:53.1,207307.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.40 207315[94:Spt:207310.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.40 207317[94:Res:207315.0,61.1] always3(s18) || -> . % 76.16/76.40 207318[94:SSi:207317.0,78146.0,78150.0,192117.0,206638.0,207305.0] || -> . % 76.16/76.40 207319[94:Spt:207318.0,207310.0,207315.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.40 207320[94:Spt:207318.0,207310.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.40 207324[94:Res:207320.0,61.1] always3(s19) || -> . % 76.16/76.40 207325[94:SSi:207324.0,78151.0,78154.0,192118.0] || -> . % 76.16/76.40 207326[92:Spt:207325.0,206637.0,206638.0] || until2p7(s18)*+ -> . % 76.16/76.40 207327[92:Spt:207325.0,206637.1] || -> node4(s17)*. % 76.16/76.40 207329[92:MRR:867.0,207327.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.40 207332[92:Res:53.1,207329.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.40 207334[93:Spt:207332.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.40 207336[93:Res:207334.0,61.1] always3(s17) || -> . % 76.16/76.40 207337[93:SSi:207336.0,78142.0,78145.0,192116.0,206636.0,207327.0] || -> . % 76.16/76.40 207338[93:Spt:207337.0,207332.0,207334.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.40 207339[93:Spt:207337.0,207332.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.40 207343[93:Res:207339.0,61.1] always3(s18) || -> . % 76.16/76.40 207344[93:SSi:207343.0,78146.0,78150.0,192117.0] || -> . % 76.16/76.40 207345[91:Spt:207344.0,206635.0,206636.0] || until2p7(s17)*+ -> . % 76.16/76.40 207346[91:Spt:207344.0,206635.1] || -> node4(s16)*. % 76.16/76.40 207348[91:MRR:870.0,207346.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.40 207351[91:Res:53.1,207348.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.40 207353[91:MRR:207351.0,206625.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.40 207355[91:Res:207353.0,61.1] always3(s17) || -> . % 76.16/76.40 207356[91:SSi:207355.0,78142.0,78145.0,192116.0] || -> . % 76.16/76.40 207357[89:Spt:207356.0,206501.0,206504.0] || trans(s49,s16)*+ -> . % 76.16/76.40 207358[89:Spt:207356.0,206501.1,206501.2,206501.3,206501.4,206501.5,206501.6,206501.7,206501.8,206501.9,206501.10] || -> trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.40 207360[89:MRR:206503.1,207357.0] xuntil6(s49) || -> trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.40 207361[90:Spt:207358.0] || -> trans(s49,s15)*. % 76.16/76.40 207362[90:Res:207361.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s15)*. % 76.16/76.40 207364[90:Res:207361.0,60.0] || -> node2(s49,s15)*. % 76.16/76.40 207365[90:SSi:207362.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s15)*. % 76.16/76.40 207366[90:Res:207364.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)*. % 76.16/76.40 207481[90:SoR:207366.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)*. % 76.16/76.40 207483[90:SoR:207481.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s15,c_busy)* xuntil6(s49). % 76.16/76.40 207484[90:SSi:207483.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s15,c_busy)* xuntil6(s49). % 76.16/76.40 207485[91:Spt:207484.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.40 207487[91:Res:207485.0,61.1] always3(s15) || -> . % 76.16/76.40 207488[91:SSi:207487.0,78133.0,78136.0,192114.0] || -> . % 76.16/76.40 207489[91:Spt:207488.0,207484.1,207485.0] || m_main_v_state(s15,c_busy)*+ -> . % 76.16/76.40 207490[91:Spt:207488.0,207484.0,207484.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.40 207494[91:MRR:207481.2,207489.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.40 207495[91:Res:53.1,207490.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.40 207497[91:MRR:207495.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.40 207498[91:MRR:207365.0,207497.0] || -> until2p7(s15)*. % 76.16/76.40 207499[91:MRR:211.0,207498.0] || -> until2p7(s16)* node4(s15). % 76.16/76.40 207500[92:Spt:207499.0] || -> until2p7(s16)*. % 76.16/76.40 207501[92:MRR:212.0,207500.0] || -> until2p7(s17)* node4(s16). % 76.16/76.40 207502[93:Spt:207501.0] || -> until2p7(s17)*. % 76.16/76.40 207503[93:MRR:213.0,207502.0] || -> until2p7(s18)* node4(s17). % 76.16/76.40 207504[94:Spt:207503.0] || -> until2p7(s18)*. % 76.16/76.40 207505[94:MRR:214.0,207504.0] || -> until2p7(s19)* node4(s18). % 76.16/76.40 207506[95:Spt:207505.0] || -> until2p7(s19)*. % 76.16/76.40 207507[95:MRR:215.0,207506.0] || -> until2p7(s20)* node4(s19). % 76.16/76.40 207508[96:Spt:207507.0] || -> until2p7(s20)*. % 76.16/76.40 207509[96:MRR:216.0,207508.0] || -> until2p7(s21)* node4(s20). % 76.16/76.40 207510[97:Spt:207509.0] || -> until2p7(s21)*. % 76.16/76.40 207511[97:MRR:217.0,207510.0] || -> until2p7(s22)* node4(s21). % 76.16/76.40 207512[98:Spt:207511.0] || -> until2p7(s22)*. % 76.16/76.40 207513[98:MRR:218.0,207512.0] || -> until2p7(s23)* node4(s22). % 76.16/76.40 207514[99:Spt:207513.0] || -> until2p7(s23)*. % 76.16/76.40 207515[99:MRR:219.0,207514.0] || -> until2p7(s24)* node4(s23). % 76.16/76.40 207516[100:Spt:207515.0] || -> until2p7(s24)*. % 76.16/76.40 207517[100:MRR:220.0,207516.0] || -> until2p7(s25)* node4(s24). % 76.16/76.40 207518[101:Spt:207517.0] || -> until2p7(s25)*. % 76.16/76.40 207519[101:MRR:221.0,207518.0] || -> until2p7(s26)* node4(s25). % 76.16/76.40 207520[102:Spt:207519.0] || -> until2p7(s26)*. % 76.16/76.40 207521[102:MRR:222.0,207520.0] || -> until2p7(s27)* node4(s26). % 76.16/76.40 207522[103:Spt:207521.0] || -> until2p7(s27)*. % 76.16/76.40 207523[103:MRR:223.0,207522.0] || -> until2p7(s28)* node4(s27). % 76.16/76.40 207524[104:Spt:207523.0] || -> until2p7(s28)*. % 76.16/76.40 207525[104:MRR:224.0,207524.0] || -> until2p7(s29)* node4(s28). % 76.16/76.40 207526[105:Spt:207525.0] || -> until2p7(s29)*. % 76.16/76.40 207527[105:MRR:225.0,207526.0] || -> until2p7(s30)* node4(s29). % 76.16/76.40 207528[106:Spt:207527.0] || -> until2p7(s30)*. % 76.16/76.40 207529[106:MRR:226.0,207528.0] || -> until2p7(s31)* node4(s30). % 76.16/76.40 207530[107:Spt:207529.0] || -> until2p7(s31)*. % 76.16/76.40 207531[107:MRR:227.0,207530.0] || -> until2p7(s32)* node4(s31). % 76.16/76.40 207532[108:Spt:207531.0] || -> until2p7(s32)*. % 76.16/76.40 207533[108:MRR:228.0,207532.0] || -> until2p7(s33)* node4(s32). % 76.16/76.40 207534[109:Spt:207533.0] || -> until2p7(s33)*. % 76.16/76.40 207535[109:MRR:229.0,207534.0] || -> until2p7(s34)* node4(s33). % 76.16/76.40 207536[110:Spt:207535.0] || -> until2p7(s34)*. % 76.16/76.40 207537[110:MRR:230.0,207536.0] || -> until2p7(s35)* node4(s34). % 76.16/76.40 207538[111:Spt:207537.0] || -> until2p7(s35)*. % 76.16/76.40 207539[111:MRR:231.0,207538.0] || -> until2p7(s36)* node4(s35). % 76.16/76.40 207540[112:Spt:207539.0] || -> until2p7(s36)*. % 76.16/76.40 207541[112:MRR:232.0,207540.0] || -> until2p7(s37)* node4(s36). % 76.16/76.40 207542[113:Spt:207541.0] || -> until2p7(s37)*. % 76.16/76.40 207543[113:MRR:235.0,207542.0] || -> until2p7(s38)* node4(s37). % 76.16/76.40 207544[114:Spt:207543.0] || -> until2p7(s38)*. % 76.16/76.40 207545[114:MRR:236.0,207544.0] || -> until2p7(s39)* node4(s38). % 76.16/76.40 207546[115:Spt:207545.0] || -> until2p7(s39)*. % 76.16/76.40 207547[115:MRR:237.0,207546.0] || -> until2p7(s40)* node4(s39). % 76.16/76.40 207548[116:Spt:207547.0] || -> until2p7(s40)*. % 76.16/76.40 207549[116:MRR:238.0,207548.0] || -> until2p7(s41)* node4(s40). % 76.16/76.40 207550[117:Spt:207549.0] || -> until2p7(s41)*. % 76.16/76.40 207551[117:MRR:239.0,207550.0] || -> until2p7(s42)* node4(s41). % 76.16/76.40 207552[118:Spt:207551.0] || -> until2p7(s42)*. % 76.16/76.40 207553[118:MRR:240.0,207552.0] || -> until2p7(s43)* node4(s42). % 76.16/76.40 207554[119:Spt:207553.0] || -> until2p7(s43)*. % 76.16/76.40 207555[119:MRR:241.0,207554.0] || -> until2p7(s44)* node4(s43). % 76.16/76.40 207556[120:Spt:207555.0] || -> until2p7(s44)*. % 76.16/76.40 207557[120:MRR:539.0,207556.0] || -> until2p7(s45)* node4(s44). % 76.16/76.40 207558[121:Spt:207557.0] || -> until2p7(s45)*. % 76.16/76.40 207559[121:MRR:544.0,207558.0] || -> until2p7(s46)* node4(s45). % 76.16/76.40 207560[122:Spt:207559.0] || -> until2p7(s46)*. % 76.16/76.40 207561[122:MRR:549.0,207560.0] || -> until2p7(s47)* node4(s46). % 76.16/76.40 207562[123:Spt:207561.0] || -> until2p7(s47)*. % 76.16/76.40 207563[123:MRR:554.0,207562.0] || -> until2p7(s48)* node4(s47). % 76.16/76.40 207564[124:Spt:207563.0] || -> until2p7(s48)*. % 76.16/76.40 207565[124:MRR:559.0,207564.0] || -> until2p7(s49)* node4(s48). % 76.16/76.40 207566[125:Spt:207565.0] || -> until2p7(s49)*. % 76.16/76.40 207567[125:MRR:194.0,207566.0] || -> node4(s49)*. % 76.16/76.40 207568[125:MRR:207494.0,207567.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.40 207569[125:Res:53.1,207568.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.40 207571[125:MRR:207569.0,78381.0] || -> . % 76.16/76.40 207572[125:Spt:207571.0,207565.0,207566.0] || until2p7(s49)*+ -> . % 76.16/76.40 207573[125:Spt:207571.0,207565.1] || -> node4(s48)*. % 76.16/76.40 207574[125:MRR:78384.0,207573.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.40 207577[125:Res:53.1,207574.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 207580[125:Res:207577.0,61.1] always3(s48) || -> . % 76.16/76.40 207581[125:SSi:207580.0,78281.0,78387.0,192147.0,207564.0,207573.0] || -> . % 76.16/76.40 207582[124:Spt:207581.0,207563.0,207564.0] || until2p7(s48)*+ -> . % 76.16/76.40 207583[124:Spt:207581.0,207563.1] || -> node4(s47)*. % 76.16/76.40 207585[124:MRR:777.0,207583.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.40 207600[124:Res:53.1,207585.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.40 207602[125:Spt:207600.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 207604[125:Res:207602.0,61.1] always3(s47) || -> . % 76.16/76.40 207605[125:SSi:207604.0,78277.0,78280.0,192146.0,207562.0,207583.0] || -> . % 76.16/76.40 207606[125:Spt:207605.0,207600.0,207602.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.40 207607[125:Spt:207605.0,207600.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 207611[125:Res:207607.0,61.1] always3(s48) || -> . % 76.16/76.40 207612[125:SSi:207611.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.40 207613[123:Spt:207612.0,207561.0,207562.0] || until2p7(s47)*+ -> . % 76.16/76.40 207614[123:Spt:207612.0,207561.1] || -> node4(s46)*. % 76.16/76.40 207616[123:MRR:780.0,207614.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.40 207626[123:Res:53.1,207616.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.40 207628[124:Spt:207626.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 207630[124:Res:207628.0,61.1] always3(s46) || -> . % 76.16/76.40 207631[124:SSi:207630.0,78272.0,78276.0,192145.0,207560.0,207614.0] || -> . % 76.16/76.40 207632[124:Spt:207631.0,207626.0,207628.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.40 207633[124:Spt:207631.0,207626.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 207637[124:Res:207633.0,61.1] always3(s47) || -> . % 76.16/76.40 207638[124:SSi:207637.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.40 207639[122:Spt:207638.0,207559.0,207560.0] || until2p7(s46)*+ -> . % 76.16/76.40 207640[122:Spt:207638.0,207559.1] || -> node4(s45)*. % 76.16/76.40 207642[122:MRR:783.0,207640.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.40 207645[122:Res:53.1,207642.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.40 207647[123:Spt:207645.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 207649[123:Res:207647.0,61.1] always3(s45) || -> . % 76.16/76.40 207650[123:SSi:207649.0,78268.0,78271.0,192144.0,207558.0,207640.0] || -> . % 76.16/76.40 207651[123:Spt:207650.0,207645.0,207647.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.40 207652[123:Spt:207650.0,207645.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 207656[123:Res:207652.0,61.1] always3(s46) || -> . % 76.16/76.40 207657[123:SSi:207656.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.40 207658[121:Spt:207657.0,207557.0,207558.0] || until2p7(s45)*+ -> . % 76.16/76.40 207659[121:Spt:207657.0,207557.1] || -> node4(s44)*. % 76.16/76.40 207661[121:MRR:786.0,207659.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.40 207664[121:Res:53.1,207661.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.40 207666[122:Spt:207664.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 207668[122:Res:207666.0,61.1] always3(s44) || -> . % 76.16/76.40 207669[122:SSi:207668.0,78263.0,78267.0,192143.0,207556.0,207659.0] || -> . % 76.16/76.40 207670[122:Spt:207669.0,207664.0,207666.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.40 207671[122:Spt:207669.0,207664.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 207675[122:Res:207671.0,61.1] always3(s45) || -> . % 76.16/76.40 207676[122:SSi:207675.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.40 207677[120:Spt:207676.0,207555.0,207556.0] || until2p7(s44)*+ -> . % 76.16/76.40 207678[120:Spt:207676.0,207555.1] || -> node4(s43)*. % 76.16/76.40 207680[120:MRR:789.0,207678.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.40 207683[120:Res:53.1,207680.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.40 207688[121:Spt:207683.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 207690[121:Res:207688.0,61.1] always3(s43) || -> . % 76.16/76.40 207691[121:SSi:207690.0,78259.0,78262.0,192142.0,207554.0,207678.0] || -> . % 76.16/76.40 207692[121:Spt:207691.0,207683.0,207688.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.40 207693[121:Spt:207691.0,207683.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 207697[121:Res:207693.0,61.1] always3(s44) || -> . % 76.16/76.40 207698[121:SSi:207697.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.40 207699[119:Spt:207698.0,207553.0,207554.0] || until2p7(s43)*+ -> . % 76.16/76.40 207700[119:Spt:207698.0,207553.1] || -> node4(s42)*. % 76.16/76.40 207702[119:MRR:792.0,207700.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.40 207705[119:Res:53.1,207702.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.40 207707[120:Spt:207705.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 207709[120:Res:207707.0,61.1] always3(s42) || -> . % 76.16/76.40 207710[120:SSi:207709.0,78254.0,78258.0,192141.0,207552.0,207700.0] || -> . % 76.16/76.40 207711[120:Spt:207710.0,207705.0,207707.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.40 207712[120:Spt:207710.0,207705.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 207716[120:Res:207712.0,61.1] always3(s43) || -> . % 76.16/76.40 207717[120:SSi:207716.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.40 207718[118:Spt:207717.0,207551.0,207552.0] || until2p7(s42)*+ -> . % 76.16/76.40 207719[118:Spt:207717.0,207551.1] || -> node4(s41)*. % 76.16/76.40 207721[118:MRR:795.0,207719.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.40 207724[118:Res:53.1,207721.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.40 207726[119:Spt:207724.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 207728[119:Res:207726.0,61.1] always3(s41) || -> . % 76.16/76.40 207729[119:SSi:207728.0,78250.0,78253.0,192140.0,207550.0,207719.0] || -> . % 76.16/76.40 207730[119:Spt:207729.0,207724.0,207726.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.40 207731[119:Spt:207729.0,207724.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 207735[119:Res:207731.0,61.1] always3(s42) || -> . % 76.16/76.40 207736[119:SSi:207735.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.40 207737[117:Spt:207736.0,207549.0,207550.0] || until2p7(s41)*+ -> . % 76.16/76.40 207738[117:Spt:207736.0,207549.1] || -> node4(s40)*. % 76.16/76.40 207740[117:MRR:798.0,207738.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.40 207743[117:Res:53.1,207740.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.40 207745[118:Spt:207743.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 207747[118:Res:207745.0,61.1] always3(s40) || -> . % 76.16/76.40 207748[118:SSi:207747.0,78245.0,78249.0,192139.0,207548.0,207738.0] || -> . % 76.16/76.40 207749[118:Spt:207748.0,207743.0,207745.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.40 207750[118:Spt:207748.0,207743.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 207754[118:Res:207750.0,61.1] always3(s41) || -> . % 76.16/76.40 207755[118:SSi:207754.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.40 207756[116:Spt:207755.0,207547.0,207548.0] || until2p7(s40)*+ -> . % 76.16/76.40 207757[116:Spt:207755.0,207547.1] || -> node4(s39)*. % 76.16/76.40 207759[116:MRR:801.0,207757.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.40 207762[116:Res:53.1,207759.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.40 207767[117:Spt:207762.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 207769[117:Res:207767.0,61.1] always3(s39) || -> . % 76.16/76.40 207770[117:SSi:207769.0,78241.0,78244.0,192138.0,207546.0,207757.0] || -> . % 76.16/76.40 207771[117:Spt:207770.0,207762.0,207767.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.40 207772[117:Spt:207770.0,207762.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 207776[117:Res:207772.0,61.1] always3(s40) || -> . % 76.16/76.40 207777[117:SSi:207776.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.40 207778[115:Spt:207777.0,207545.0,207546.0] || until2p7(s39)*+ -> . % 76.16/76.40 207779[115:Spt:207777.0,207545.1] || -> node4(s38)*. % 76.16/76.40 207781[115:MRR:804.0,207779.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.40 207784[115:Res:53.1,207781.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.40 207786[116:Spt:207784.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 207788[116:Res:207786.0,61.1] always3(s38) || -> . % 76.16/76.40 207789[116:SSi:207788.0,78236.0,78240.0,192137.0,207544.0,207779.0] || -> . % 76.16/76.40 207790[116:Spt:207789.0,207784.0,207786.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.40 207791[116:Spt:207789.0,207784.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 207795[116:Res:207791.0,61.1] always3(s39) || -> . % 76.16/76.40 207796[116:SSi:207795.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.40 207797[114:Spt:207796.0,207543.0,207544.0] || until2p7(s38)*+ -> . % 76.16/76.40 207798[114:Spt:207796.0,207543.1] || -> node4(s37)*. % 76.16/76.40 207800[114:MRR:807.0,207798.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.40 207803[114:Res:53.1,207800.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.40 207805[115:Spt:207803.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 207807[115:Res:207805.0,61.1] always3(s37) || -> . % 76.16/76.40 207808[115:SSi:207807.0,78232.0,78235.0,192136.0,207542.0,207798.0] || -> . % 76.16/76.40 207809[115:Spt:207808.0,207803.0,207805.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.40 207810[115:Spt:207808.0,207803.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 207814[115:Res:207810.0,61.1] always3(s38) || -> . % 76.16/76.40 207815[115:SSi:207814.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.40 207816[113:Spt:207815.0,207541.0,207542.0] || until2p7(s37)*+ -> . % 76.16/76.40 207817[113:Spt:207815.0,207541.1] || -> node4(s36)*. % 76.16/76.40 207819[113:MRR:810.0,207817.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.40 207822[113:Res:53.1,207819.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.40 207824[114:Spt:207822.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 207826[114:Res:207824.0,61.1] always3(s36) || -> . % 76.16/76.40 207827[114:SSi:207826.0,78227.0,78231.0,192135.0,207540.0,207817.0] || -> . % 76.16/76.40 207828[114:Spt:207827.0,207822.0,207824.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.40 207829[114:Spt:207827.0,207822.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 207833[114:Res:207829.0,61.1] always3(s37) || -> . % 76.16/76.40 207834[114:SSi:207833.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.40 207835[112:Spt:207834.0,207539.0,207540.0] || until2p7(s36)*+ -> . % 76.16/76.40 207836[112:Spt:207834.0,207539.1] || -> node4(s35)*. % 76.16/76.40 207838[112:MRR:813.0,207836.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.40 207841[112:Res:53.1,207838.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.40 207846[113:Spt:207841.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 207848[113:Res:207846.0,61.1] always3(s35) || -> . % 76.16/76.40 207849[113:SSi:207848.0,78223.0,78226.0,192134.0,207538.0,207836.0] || -> . % 76.16/76.40 207850[113:Spt:207849.0,207841.0,207846.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.40 207851[113:Spt:207849.0,207841.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 207855[113:Res:207851.0,61.1] always3(s36) || -> . % 76.16/76.40 207856[113:SSi:207855.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.40 207857[111:Spt:207856.0,207537.0,207538.0] || until2p7(s35)*+ -> . % 76.16/76.40 207858[111:Spt:207856.0,207537.1] || -> node4(s34)*. % 76.16/76.40 207860[111:MRR:816.0,207858.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.40 207863[111:Res:53.1,207860.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.40 207865[112:Spt:207863.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 207867[112:Res:207865.0,61.1] always3(s34) || -> . % 76.16/76.40 207868[112:SSi:207867.0,78218.0,78222.0,192133.0,207536.0,207858.0] || -> . % 76.16/76.40 207869[112:Spt:207868.0,207863.0,207865.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.40 207870[112:Spt:207868.0,207863.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 207874[112:Res:207870.0,61.1] always3(s35) || -> . % 76.16/76.40 207875[112:SSi:207874.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.40 207876[110:Spt:207875.0,207535.0,207536.0] || until2p7(s34)*+ -> . % 76.16/76.40 207877[110:Spt:207875.0,207535.1] || -> node4(s33)*. % 76.16/76.40 207879[110:MRR:819.0,207877.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.40 207882[110:Res:53.1,207879.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.40 207884[111:Spt:207882.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 207886[111:Res:207884.0,61.1] always3(s33) || -> . % 76.16/76.40 207887[111:SSi:207886.0,78214.0,78217.0,192132.0,207534.0,207877.0] || -> . % 76.16/76.40 207888[111:Spt:207887.0,207882.0,207884.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.40 207889[111:Spt:207887.0,207882.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 207893[111:Res:207889.0,61.1] always3(s34) || -> . % 76.16/76.40 207894[111:SSi:207893.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.40 207895[109:Spt:207894.0,207533.0,207534.0] || until2p7(s33)*+ -> . % 76.16/76.40 207896[109:Spt:207894.0,207533.1] || -> node4(s32)*. % 76.16/76.40 207898[109:MRR:822.0,207896.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.40 207901[109:Res:53.1,207898.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.40 207903[110:Spt:207901.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 207905[110:Res:207903.0,61.1] always3(s32) || -> . % 76.16/76.40 207906[110:SSi:207905.0,78209.0,78213.0,192131.0,207532.0,207896.0] || -> . % 76.16/76.40 207907[110:Spt:207906.0,207901.0,207903.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.40 207908[110:Spt:207906.0,207901.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 207912[110:Res:207908.0,61.1] always3(s33) || -> . % 76.16/76.40 207913[110:SSi:207912.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.40 207914[108:Spt:207913.0,207531.0,207532.0] || until2p7(s32)*+ -> . % 76.16/76.40 207915[108:Spt:207913.0,207531.1] || -> node4(s31)*. % 76.16/76.40 207917[108:MRR:825.0,207915.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.40 207920[108:Res:53.1,207917.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.40 207925[109:Spt:207920.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 207927[109:Res:207925.0,61.1] always3(s31) || -> . % 76.16/76.40 207928[109:SSi:207927.0,78205.0,78208.0,192130.0,207530.0,207915.0] || -> . % 76.16/76.40 207929[109:Spt:207928.0,207920.0,207925.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.40 207930[109:Spt:207928.0,207920.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 207934[109:Res:207930.0,61.1] always3(s32) || -> . % 76.16/76.40 207935[109:SSi:207934.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.40 207936[107:Spt:207935.0,207529.0,207530.0] || until2p7(s31)*+ -> . % 76.16/76.40 207937[107:Spt:207935.0,207529.1] || -> node4(s30)*. % 76.16/76.40 207939[107:MRR:828.0,207937.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.40 207942[107:Res:53.1,207939.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.40 207944[108:Spt:207942.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 207946[108:Res:207944.0,61.1] always3(s30) || -> . % 76.16/76.40 207947[108:SSi:207946.0,78200.0,78204.0,192129.0,207528.0,207937.0] || -> . % 76.16/76.40 207948[108:Spt:207947.0,207942.0,207944.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.40 207949[108:Spt:207947.0,207942.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 207953[108:Res:207949.0,61.1] always3(s31) || -> . % 76.16/76.40 207954[108:SSi:207953.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.40 207955[106:Spt:207954.0,207527.0,207528.0] || until2p7(s30)*+ -> . % 76.16/76.40 207956[106:Spt:207954.0,207527.1] || -> node4(s29)*. % 76.16/76.40 207958[106:MRR:831.0,207956.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.40 207961[106:Res:53.1,207958.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.40 207963[107:Spt:207961.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 207965[107:Res:207963.0,61.1] always3(s29) || -> . % 76.16/76.40 207966[107:SSi:207965.0,78196.0,78199.0,192128.0,207526.0,207956.0] || -> . % 76.16/76.40 207967[107:Spt:207966.0,207961.0,207963.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.40 207968[107:Spt:207966.0,207961.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 207972[107:Res:207968.0,61.1] always3(s30) || -> . % 76.16/76.40 207973[107:SSi:207972.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.40 207974[105:Spt:207973.0,207525.0,207526.0] || until2p7(s29)*+ -> . % 76.16/76.40 207975[105:Spt:207973.0,207525.1] || -> node4(s28)*. % 76.16/76.40 207977[105:MRR:834.0,207975.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.40 207980[105:Res:53.1,207977.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.40 207982[106:Spt:207980.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 207984[106:Res:207982.0,61.1] always3(s28) || -> . % 76.16/76.40 207985[106:SSi:207984.0,78191.0,78195.0,192127.0,207524.0,207975.0] || -> . % 76.16/76.40 207986[106:Spt:207985.0,207980.0,207982.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.40 207987[106:Spt:207985.0,207980.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 207991[106:Res:207987.0,61.1] always3(s29) || -> . % 76.16/76.40 207992[106:SSi:207991.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.40 207993[104:Spt:207992.0,207523.0,207524.0] || until2p7(s28)*+ -> . % 76.16/76.40 207994[104:Spt:207992.0,207523.1] || -> node4(s27)*. % 76.16/76.40 207996[104:MRR:837.0,207994.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.40 207999[104:Res:53.1,207996.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.40 208004[105:Spt:207999.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 208006[105:Res:208004.0,61.1] always3(s27) || -> . % 76.16/76.40 208007[105:SSi:208006.0,78187.0,78190.0,192126.0,207522.0,207994.0] || -> . % 76.16/76.40 208008[105:Spt:208007.0,207999.0,208004.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.40 208009[105:Spt:208007.0,207999.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 208013[105:Res:208009.0,61.1] always3(s28) || -> . % 76.16/76.40 208014[105:SSi:208013.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.40 208015[103:Spt:208014.0,207521.0,207522.0] || until2p7(s27)*+ -> . % 76.16/76.40 208016[103:Spt:208014.0,207521.1] || -> node4(s26)*. % 76.16/76.40 208018[103:MRR:840.0,208016.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.40 208021[103:Res:53.1,208018.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.40 208023[104:Spt:208021.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 208025[104:Res:208023.0,61.1] always3(s26) || -> . % 76.16/76.40 208026[104:SSi:208025.0,78182.0,78186.0,192125.0,207520.0,208016.0] || -> . % 76.16/76.40 208027[104:Spt:208026.0,208021.0,208023.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.40 208028[104:Spt:208026.0,208021.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 208032[104:Res:208028.0,61.1] always3(s27) || -> . % 76.16/76.40 208033[104:SSi:208032.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.40 208034[102:Spt:208033.0,207519.0,207520.0] || until2p7(s26)*+ -> . % 76.16/76.40 208035[102:Spt:208033.0,207519.1] || -> node4(s25)*. % 76.16/76.40 208037[102:MRR:843.0,208035.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.40 208040[102:Res:53.1,208037.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.40 208042[103:Spt:208040.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 208044[103:Res:208042.0,61.1] always3(s25) || -> . % 76.16/76.40 208045[103:SSi:208044.0,78178.0,78181.0,192124.0,207518.0,208035.0] || -> . % 76.16/76.40 208046[103:Spt:208045.0,208040.0,208042.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.40 208047[103:Spt:208045.0,208040.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 208051[103:Res:208047.0,61.1] always3(s26) || -> . % 76.16/76.40 208052[103:SSi:208051.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.40 208053[101:Spt:208052.0,207517.0,207518.0] || until2p7(s25)*+ -> . % 76.16/76.40 208054[101:Spt:208052.0,207517.1] || -> node4(s24)*. % 76.16/76.40 208056[101:MRR:846.0,208054.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.40 208059[101:Res:53.1,208056.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.40 208061[102:Spt:208059.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 208063[102:Res:208061.0,61.1] always3(s24) || -> . % 76.16/76.40 208064[102:SSi:208063.0,78173.0,78177.0,192123.0,207516.0,208054.0] || -> . % 76.16/76.40 208065[102:Spt:208064.0,208059.0,208061.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.40 208066[102:Spt:208064.0,208059.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 208070[102:Res:208066.0,61.1] always3(s25) || -> . % 76.16/76.40 208071[102:SSi:208070.0,78178.0,78181.0,192124.0] || -> . % 76.16/76.40 208072[100:Spt:208071.0,207515.0,207516.0] || until2p7(s24)*+ -> . % 76.16/76.40 208073[100:Spt:208071.0,207515.1] || -> node4(s23)*. % 76.16/76.40 208075[100:MRR:849.0,208073.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.40 208078[100:Res:53.1,208075.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.40 208083[101:Spt:208078.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 208085[101:Res:208083.0,61.1] always3(s23) || -> . % 76.16/76.40 208086[101:SSi:208085.0,78169.0,78172.0,192122.0,207514.0,208073.0] || -> . % 76.16/76.40 208087[101:Spt:208086.0,208078.0,208083.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.40 208088[101:Spt:208086.0,208078.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 208092[101:Res:208088.0,61.1] always3(s24) || -> . % 76.16/76.40 208093[101:SSi:208092.0,78173.0,78177.0,192123.0] || -> . % 76.16/76.40 208094[99:Spt:208093.0,207513.0,207514.0] || until2p7(s23)*+ -> . % 76.16/76.40 208095[99:Spt:208093.0,207513.1] || -> node4(s22)*. % 76.16/76.40 208097[99:MRR:852.0,208095.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.40 208100[99:Res:53.1,208097.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.40 208102[100:Spt:208100.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 208104[100:Res:208102.0,61.1] always3(s22) || -> . % 76.16/76.40 208105[100:SSi:208104.0,78164.0,78168.0,192121.0,207512.0,208095.0] || -> . % 76.16/76.40 208106[100:Spt:208105.0,208100.0,208102.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.40 208107[100:Spt:208105.0,208100.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 208111[100:Res:208107.0,61.1] always3(s23) || -> . % 76.16/76.40 208112[100:SSi:208111.0,78169.0,78172.0,192122.0] || -> . % 76.16/76.40 208113[98:Spt:208112.0,207511.0,207512.0] || until2p7(s22)*+ -> . % 76.16/76.40 208114[98:Spt:208112.0,207511.1] || -> node4(s21)*. % 76.16/76.40 208116[98:MRR:855.0,208114.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.40 208119[98:Res:53.1,208116.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.40 208121[99:Spt:208119.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 208123[99:Res:208121.0,61.1] always3(s21) || -> . % 76.16/76.40 208124[99:SSi:208123.0,78160.0,78163.0,192120.0,207510.0,208114.0] || -> . % 76.16/76.40 208125[99:Spt:208124.0,208119.0,208121.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.40 208126[99:Spt:208124.0,208119.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 208130[99:Res:208126.0,61.1] always3(s22) || -> . % 76.16/76.40 208131[99:SSi:208130.0,78164.0,78168.0,192121.0] || -> . % 76.16/76.40 208132[97:Spt:208131.0,207509.0,207510.0] || until2p7(s21)*+ -> . % 76.16/76.40 208133[97:Spt:208131.0,207509.1] || -> node4(s20)*. % 76.16/76.40 208135[97:MRR:858.0,208133.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.40 208138[97:Res:53.1,208135.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.40 208140[98:Spt:208138.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 208142[98:Res:208140.0,61.1] always3(s20) || -> . % 76.16/76.40 208143[98:SSi:208142.0,78155.0,78159.0,192119.0,207508.0,208133.0] || -> . % 76.16/76.40 208144[98:Spt:208143.0,208138.0,208140.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.40 208145[98:Spt:208143.0,208138.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 208149[98:Res:208145.0,61.1] always3(s21) || -> . % 76.16/76.40 208150[98:SSi:208149.0,78160.0,78163.0,192120.0] || -> . % 76.16/76.40 208151[96:Spt:208150.0,207507.0,207508.0] || until2p7(s20)*+ -> . % 76.16/76.40 208152[96:Spt:208150.0,207507.1] || -> node4(s19)*. % 76.16/76.40 208154[96:MRR:861.0,208152.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.40 208157[96:Res:53.1,208154.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.40 208162[97:Spt:208157.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.40 208164[97:Res:208162.0,61.1] always3(s19) || -> . % 76.16/76.40 208165[97:SSi:208164.0,78151.0,78154.0,192118.0,207506.0,208152.0] || -> . % 76.16/76.40 208166[97:Spt:208165.0,208157.0,208162.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.40 208167[97:Spt:208165.0,208157.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 208171[97:Res:208167.0,61.1] always3(s20) || -> . % 76.16/76.40 208172[97:SSi:208171.0,78155.0,78159.0,192119.0] || -> . % 76.16/76.40 208173[95:Spt:208172.0,207505.0,207506.0] || until2p7(s19)*+ -> . % 76.16/76.40 208174[95:Spt:208172.0,207505.1] || -> node4(s18)*. % 76.16/76.40 208176[95:MRR:864.0,208174.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.40 208179[95:Res:53.1,208176.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.40 208181[96:Spt:208179.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.40 208183[96:Res:208181.0,61.1] always3(s18) || -> . % 76.16/76.40 208184[96:SSi:208183.0,78146.0,78150.0,192117.0,207504.0,208174.0] || -> . % 76.16/76.40 208185[96:Spt:208184.0,208179.0,208181.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.40 208186[96:Spt:208184.0,208179.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.40 208190[96:Res:208186.0,61.1] always3(s19) || -> . % 76.16/76.40 208191[96:SSi:208190.0,78151.0,78154.0,192118.0] || -> . % 76.16/76.40 208192[94:Spt:208191.0,207503.0,207504.0] || until2p7(s18)*+ -> . % 76.16/76.40 208193[94:Spt:208191.0,207503.1] || -> node4(s17)*. % 76.16/76.40 208195[94:MRR:867.0,208193.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.40 208198[94:Res:53.1,208195.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.40 208200[95:Spt:208198.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.40 208202[95:Res:208200.0,61.1] always3(s17) || -> . % 76.16/76.40 208203[95:SSi:208202.0,78142.0,78145.0,192116.0,207502.0,208193.0] || -> . % 76.16/76.40 208204[95:Spt:208203.0,208198.0,208200.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.40 208205[95:Spt:208203.0,208198.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.40 208209[95:Res:208205.0,61.1] always3(s18) || -> . % 76.16/76.40 208210[95:SSi:208209.0,78146.0,78150.0,192117.0] || -> . % 76.16/76.40 208211[93:Spt:208210.0,207501.0,207502.0] || until2p7(s17)*+ -> . % 76.16/76.40 208212[93:Spt:208210.0,207501.1] || -> node4(s16)*. % 76.16/76.40 208214[93:MRR:870.0,208212.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.40 208217[93:Res:53.1,208214.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.40 208219[94:Spt:208217.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.40 208221[94:Res:208219.0,61.1] always3(s16) || -> . % 76.16/76.40 208222[94:SSi:208221.0,78137.0,78141.0,192115.0,207500.0,208212.0] || -> . % 76.16/76.40 208223[94:Spt:208222.0,208217.0,208219.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.40 208224[94:Spt:208222.0,208217.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.40 208228[94:Res:208224.0,61.1] always3(s17) || -> . % 76.16/76.40 208229[94:SSi:208228.0,78142.0,78145.0,192116.0] || -> . % 76.16/76.40 208230[92:Spt:208229.0,207499.0,207500.0] || until2p7(s16)*+ -> . % 76.16/76.40 208231[92:Spt:208229.0,207499.1] || -> node4(s15)*. % 76.16/76.40 208233[92:MRR:873.0,208231.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.40 208236[92:Res:53.1,208233.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.40 208238[92:MRR:208236.0,207489.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.40 208243[92:Res:208238.0,61.1] always3(s16) || -> . % 76.16/76.40 208244[92:SSi:208243.0,78137.0,78141.0,192115.0] || -> . % 76.16/76.40 208245[90:Spt:208244.0,207358.0,207361.0] || trans(s49,s15)*+ -> . % 76.16/76.40 208246[90:Spt:208244.0,207358.1,207358.2,207358.3,207358.4,207358.5,207358.6,207358.7,207358.8,207358.9] || -> trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.40 208248[90:MRR:207360.1,208245.0] xuntil6(s49) || -> trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.40 208249[91:Spt:208246.0] || -> trans(s49,s14)*. % 76.16/76.40 208250[91:Res:208249.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s14)*. % 76.16/76.40 208252[91:Res:208249.0,60.0] || -> node2(s49,s14)*. % 76.16/76.40 208253[91:SSi:208250.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s14)*. % 76.16/76.40 208254[91:Res:208252.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)*. % 76.16/76.40 208370[91:SoR:208254.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)*. % 76.16/76.40 208372[91:SoR:208370.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s14,c_busy)* xuntil6(s49). % 76.16/76.40 208373[91:SSi:208372.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s14,c_busy)* xuntil6(s49). % 76.16/76.40 208374[92:Spt:208373.1] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.40 208376[92:Res:208374.0,61.1] always3(s14) || -> . % 76.16/76.40 208377[92:SSi:208376.0,78128.0,78132.0,192113.0] || -> . % 76.16/76.40 208378[92:Spt:208377.0,208373.1,208374.0] || m_main_v_state(s14,c_busy)*+ -> . % 76.16/76.40 208379[92:Spt:208377.0,208373.0,208373.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.40 208383[92:MRR:208370.2,208378.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.40 208384[92:Res:53.1,208379.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.40 208386[92:MRR:208384.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.40 208387[92:MRR:208253.0,208386.0] || -> until2p7(s14)*. % 76.16/76.40 208388[92:MRR:210.0,208387.0] || -> until2p7(s15)* node4(s14). % 76.16/76.40 208389[93:Spt:208388.0] || -> until2p7(s15)*. % 76.16/76.40 208390[93:MRR:211.0,208389.0] || -> until2p7(s16)* node4(s15). % 76.16/76.40 208391[94:Spt:208390.0] || -> until2p7(s16)*. % 76.16/76.40 208392[94:MRR:212.0,208391.0] || -> until2p7(s17)* node4(s16). % 76.16/76.40 208393[95:Spt:208392.0] || -> until2p7(s17)*. % 76.16/76.40 208394[95:MRR:213.0,208393.0] || -> until2p7(s18)* node4(s17). % 76.16/76.40 208395[96:Spt:208394.0] || -> until2p7(s18)*. % 76.16/76.40 208396[96:MRR:214.0,208395.0] || -> until2p7(s19)* node4(s18). % 76.16/76.40 208397[97:Spt:208396.0] || -> until2p7(s19)*. % 76.16/76.40 208398[97:MRR:215.0,208397.0] || -> until2p7(s20)* node4(s19). % 76.16/76.40 208399[98:Spt:208398.0] || -> until2p7(s20)*. % 76.16/76.40 208400[98:MRR:216.0,208399.0] || -> until2p7(s21)* node4(s20). % 76.16/76.40 208401[99:Spt:208400.0] || -> until2p7(s21)*. % 76.16/76.40 208402[99:MRR:217.0,208401.0] || -> until2p7(s22)* node4(s21). % 76.16/76.40 208403[100:Spt:208402.0] || -> until2p7(s22)*. % 76.16/76.40 208404[100:MRR:218.0,208403.0] || -> until2p7(s23)* node4(s22). % 76.16/76.40 208405[101:Spt:208404.0] || -> until2p7(s23)*. % 76.16/76.40 208406[101:MRR:219.0,208405.0] || -> until2p7(s24)* node4(s23). % 76.16/76.40 208407[102:Spt:208406.0] || -> until2p7(s24)*. % 76.16/76.40 208408[102:MRR:220.0,208407.0] || -> until2p7(s25)* node4(s24). % 76.16/76.40 208409[103:Spt:208408.0] || -> until2p7(s25)*. % 76.16/76.40 208410[103:MRR:221.0,208409.0] || -> until2p7(s26)* node4(s25). % 76.16/76.40 208411[104:Spt:208410.0] || -> until2p7(s26)*. % 76.16/76.40 208412[104:MRR:222.0,208411.0] || -> until2p7(s27)* node4(s26). % 76.16/76.40 208413[105:Spt:208412.0] || -> until2p7(s27)*. % 76.16/76.40 208414[105:MRR:223.0,208413.0] || -> until2p7(s28)* node4(s27). % 76.16/76.40 208415[106:Spt:208414.0] || -> until2p7(s28)*. % 76.16/76.40 208416[106:MRR:224.0,208415.0] || -> until2p7(s29)* node4(s28). % 76.16/76.40 208417[107:Spt:208416.0] || -> until2p7(s29)*. % 76.16/76.40 208418[107:MRR:225.0,208417.0] || -> until2p7(s30)* node4(s29). % 76.16/76.40 208419[108:Spt:208418.0] || -> until2p7(s30)*. % 76.16/76.40 208420[108:MRR:226.0,208419.0] || -> until2p7(s31)* node4(s30). % 76.16/76.40 208421[109:Spt:208420.0] || -> until2p7(s31)*. % 76.16/76.40 208422[109:MRR:227.0,208421.0] || -> until2p7(s32)* node4(s31). % 76.16/76.40 208423[110:Spt:208422.0] || -> until2p7(s32)*. % 76.16/76.40 208424[110:MRR:228.0,208423.0] || -> until2p7(s33)* node4(s32). % 76.16/76.40 208425[111:Spt:208424.0] || -> until2p7(s33)*. % 76.16/76.40 208426[111:MRR:229.0,208425.0] || -> until2p7(s34)* node4(s33). % 76.16/76.40 208427[112:Spt:208426.0] || -> until2p7(s34)*. % 76.16/76.40 208428[112:MRR:230.0,208427.0] || -> until2p7(s35)* node4(s34). % 76.16/76.40 208429[113:Spt:208428.0] || -> until2p7(s35)*. % 76.16/76.40 208430[113:MRR:231.0,208429.0] || -> until2p7(s36)* node4(s35). % 76.16/76.40 208431[114:Spt:208430.0] || -> until2p7(s36)*. % 76.16/76.40 208432[114:MRR:232.0,208431.0] || -> until2p7(s37)* node4(s36). % 76.16/76.40 208433[115:Spt:208432.0] || -> until2p7(s37)*. % 76.16/76.40 208434[115:MRR:235.0,208433.0] || -> until2p7(s38)* node4(s37). % 76.16/76.40 208435[116:Spt:208434.0] || -> until2p7(s38)*. % 76.16/76.40 208436[116:MRR:236.0,208435.0] || -> until2p7(s39)* node4(s38). % 76.16/76.40 208437[117:Spt:208436.0] || -> until2p7(s39)*. % 76.16/76.40 208438[117:MRR:237.0,208437.0] || -> until2p7(s40)* node4(s39). % 76.16/76.40 208439[118:Spt:208438.0] || -> until2p7(s40)*. % 76.16/76.40 208440[118:MRR:238.0,208439.0] || -> until2p7(s41)* node4(s40). % 76.16/76.40 208441[119:Spt:208440.0] || -> until2p7(s41)*. % 76.16/76.40 208442[119:MRR:239.0,208441.0] || -> until2p7(s42)* node4(s41). % 76.16/76.40 208443[120:Spt:208442.0] || -> until2p7(s42)*. % 76.16/76.40 208444[120:MRR:240.0,208443.0] || -> until2p7(s43)* node4(s42). % 76.16/76.40 208445[121:Spt:208444.0] || -> until2p7(s43)*. % 76.16/76.40 208446[121:MRR:241.0,208445.0] || -> until2p7(s44)* node4(s43). % 76.16/76.40 208447[122:Spt:208446.0] || -> until2p7(s44)*. % 76.16/76.40 208448[122:MRR:539.0,208447.0] || -> until2p7(s45)* node4(s44). % 76.16/76.40 208449[123:Spt:208448.0] || -> until2p7(s45)*. % 76.16/76.40 208450[123:MRR:544.0,208449.0] || -> until2p7(s46)* node4(s45). % 76.16/76.40 208451[124:Spt:208450.0] || -> until2p7(s46)*. % 76.16/76.40 208452[124:MRR:549.0,208451.0] || -> until2p7(s47)* node4(s46). % 76.16/76.40 208453[125:Spt:208452.0] || -> until2p7(s47)*. % 76.16/76.40 208454[125:MRR:554.0,208453.0] || -> until2p7(s48)* node4(s47). % 76.16/76.40 208455[126:Spt:208454.0] || -> until2p7(s48)*. % 76.16/76.40 208456[126:MRR:559.0,208455.0] || -> until2p7(s49)* node4(s48). % 76.16/76.40 208457[127:Spt:208456.0] || -> until2p7(s49)*. % 76.16/76.40 208458[127:MRR:194.0,208457.0] || -> node4(s49)*. % 76.16/76.40 208459[127:MRR:208383.0,208458.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.40 208460[127:Res:53.1,208459.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.40 208462[127:MRR:208460.0,78381.0] || -> . % 76.16/76.40 208463[127:Spt:208462.0,208456.0,208457.0] || until2p7(s49)*+ -> . % 76.16/76.40 208464[127:Spt:208462.0,208456.1] || -> node4(s48)*. % 76.16/76.40 208465[127:MRR:78384.0,208464.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.40 208468[127:Res:53.1,208465.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 208471[127:Res:208468.0,61.1] always3(s48) || -> . % 76.16/76.40 208472[127:SSi:208471.0,78281.0,78387.0,192147.0,208455.0,208464.0] || -> . % 76.16/76.40 208473[126:Spt:208472.0,208454.0,208455.0] || until2p7(s48)*+ -> . % 76.16/76.40 208474[126:Spt:208472.0,208454.1] || -> node4(s47)*. % 76.16/76.40 208476[126:MRR:777.0,208474.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.40 208491[126:Res:53.1,208476.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.40 208493[127:Spt:208491.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 208495[127:Res:208493.0,61.1] always3(s47) || -> . % 76.16/76.40 208496[127:SSi:208495.0,78277.0,78280.0,192146.0,208453.0,208474.0] || -> . % 76.16/76.40 208497[127:Spt:208496.0,208491.0,208493.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.40 208498[127:Spt:208496.0,208491.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.40 208502[127:Res:208498.0,61.1] always3(s48) || -> . % 76.16/76.40 208503[127:SSi:208502.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.40 208504[125:Spt:208503.0,208452.0,208453.0] || until2p7(s47)*+ -> . % 76.16/76.40 208505[125:Spt:208503.0,208452.1] || -> node4(s46)*. % 76.16/76.40 208507[125:MRR:780.0,208505.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.40 208517[125:Res:53.1,208507.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.40 208519[126:Spt:208517.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 208521[126:Res:208519.0,61.1] always3(s46) || -> . % 76.16/76.40 208522[126:SSi:208521.0,78272.0,78276.0,192145.0,208451.0,208505.0] || -> . % 76.16/76.40 208523[126:Spt:208522.0,208517.0,208519.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.40 208524[126:Spt:208522.0,208517.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.40 208528[126:Res:208524.0,61.1] always3(s47) || -> . % 76.16/76.40 208529[126:SSi:208528.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.40 208530[124:Spt:208529.0,208450.0,208451.0] || until2p7(s46)*+ -> . % 76.16/76.40 208531[124:Spt:208529.0,208450.1] || -> node4(s45)*. % 76.16/76.40 208533[124:MRR:783.0,208531.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.40 208536[124:Res:53.1,208533.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.40 208538[125:Spt:208536.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 208540[125:Res:208538.0,61.1] always3(s45) || -> . % 76.16/76.40 208541[125:SSi:208540.0,78268.0,78271.0,192144.0,208449.0,208531.0] || -> . % 76.16/76.40 208542[125:Spt:208541.0,208536.0,208538.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.40 208543[125:Spt:208541.0,208536.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.40 208547[125:Res:208543.0,61.1] always3(s46) || -> . % 76.16/76.40 208548[125:SSi:208547.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.40 208549[123:Spt:208548.0,208448.0,208449.0] || until2p7(s45)*+ -> . % 76.16/76.40 208550[123:Spt:208548.0,208448.1] || -> node4(s44)*. % 76.16/76.40 208552[123:MRR:786.0,208550.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.40 208555[123:Res:53.1,208552.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.40 208557[124:Spt:208555.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 208559[124:Res:208557.0,61.1] always3(s44) || -> . % 76.16/76.40 208560[124:SSi:208559.0,78263.0,78267.0,192143.0,208447.0,208550.0] || -> . % 76.16/76.40 208561[124:Spt:208560.0,208555.0,208557.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.40 208562[124:Spt:208560.0,208555.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.40 208566[124:Res:208562.0,61.1] always3(s45) || -> . % 76.16/76.40 208567[124:SSi:208566.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.40 208568[122:Spt:208567.0,208446.0,208447.0] || until2p7(s44)*+ -> . % 76.16/76.40 208569[122:Spt:208567.0,208446.1] || -> node4(s43)*. % 76.16/76.40 208571[122:MRR:789.0,208569.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.40 208574[122:Res:53.1,208571.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.40 208579[123:Spt:208574.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 208581[123:Res:208579.0,61.1] always3(s43) || -> . % 76.16/76.40 208582[123:SSi:208581.0,78259.0,78262.0,192142.0,208445.0,208569.0] || -> . % 76.16/76.40 208583[123:Spt:208582.0,208574.0,208579.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.40 208584[123:Spt:208582.0,208574.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.40 208588[123:Res:208584.0,61.1] always3(s44) || -> . % 76.16/76.40 208589[123:SSi:208588.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.40 208590[121:Spt:208589.0,208444.0,208445.0] || until2p7(s43)*+ -> . % 76.16/76.40 208591[121:Spt:208589.0,208444.1] || -> node4(s42)*. % 76.16/76.40 208593[121:MRR:792.0,208591.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.40 208596[121:Res:53.1,208593.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.40 208598[122:Spt:208596.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 208600[122:Res:208598.0,61.1] always3(s42) || -> . % 76.16/76.40 208601[122:SSi:208600.0,78254.0,78258.0,192141.0,208443.0,208591.0] || -> . % 76.16/76.40 208602[122:Spt:208601.0,208596.0,208598.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.40 208603[122:Spt:208601.0,208596.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.40 208607[122:Res:208603.0,61.1] always3(s43) || -> . % 76.16/76.40 208608[122:SSi:208607.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.40 208609[120:Spt:208608.0,208442.0,208443.0] || until2p7(s42)*+ -> . % 76.16/76.40 208610[120:Spt:208608.0,208442.1] || -> node4(s41)*. % 76.16/76.40 208612[120:MRR:795.0,208610.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.40 208615[120:Res:53.1,208612.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.40 208617[121:Spt:208615.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 208619[121:Res:208617.0,61.1] always3(s41) || -> . % 76.16/76.40 208620[121:SSi:208619.0,78250.0,78253.0,192140.0,208441.0,208610.0] || -> . % 76.16/76.40 208621[121:Spt:208620.0,208615.0,208617.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.40 208622[121:Spt:208620.0,208615.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.40 208626[121:Res:208622.0,61.1] always3(s42) || -> . % 76.16/76.40 208627[121:SSi:208626.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.40 208628[119:Spt:208627.0,208440.0,208441.0] || until2p7(s41)*+ -> . % 76.16/76.40 208629[119:Spt:208627.0,208440.1] || -> node4(s40)*. % 76.16/76.40 208631[119:MRR:798.0,208629.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.40 208634[119:Res:53.1,208631.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.40 208636[120:Spt:208634.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 208638[120:Res:208636.0,61.1] always3(s40) || -> . % 76.16/76.40 208639[120:SSi:208638.0,78245.0,78249.0,192139.0,208439.0,208629.0] || -> . % 76.16/76.40 208640[120:Spt:208639.0,208634.0,208636.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.40 208641[120:Spt:208639.0,208634.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.40 208645[120:Res:208641.0,61.1] always3(s41) || -> . % 76.16/76.40 208646[120:SSi:208645.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.40 208647[118:Spt:208646.0,208438.0,208439.0] || until2p7(s40)*+ -> . % 76.16/76.40 208648[118:Spt:208646.0,208438.1] || -> node4(s39)*. % 76.16/76.40 208650[118:MRR:801.0,208648.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.40 208653[118:Res:53.1,208650.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.40 208658[119:Spt:208653.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 208660[119:Res:208658.0,61.1] always3(s39) || -> . % 76.16/76.40 208661[119:SSi:208660.0,78241.0,78244.0,192138.0,208437.0,208648.0] || -> . % 76.16/76.40 208662[119:Spt:208661.0,208653.0,208658.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.40 208663[119:Spt:208661.0,208653.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.40 208667[119:Res:208663.0,61.1] always3(s40) || -> . % 76.16/76.40 208668[119:SSi:208667.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.40 208669[117:Spt:208668.0,208436.0,208437.0] || until2p7(s39)*+ -> . % 76.16/76.40 208670[117:Spt:208668.0,208436.1] || -> node4(s38)*. % 76.16/76.40 208672[117:MRR:804.0,208670.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.40 208675[117:Res:53.1,208672.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.40 208677[118:Spt:208675.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 208679[118:Res:208677.0,61.1] always3(s38) || -> . % 76.16/76.40 208680[118:SSi:208679.0,78236.0,78240.0,192137.0,208435.0,208670.0] || -> . % 76.16/76.40 208681[118:Spt:208680.0,208675.0,208677.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.40 208682[118:Spt:208680.0,208675.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.40 208686[118:Res:208682.0,61.1] always3(s39) || -> . % 76.16/76.40 208687[118:SSi:208686.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.40 208688[116:Spt:208687.0,208434.0,208435.0] || until2p7(s38)*+ -> . % 76.16/76.40 208689[116:Spt:208687.0,208434.1] || -> node4(s37)*. % 76.16/76.40 208691[116:MRR:807.0,208689.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.40 208694[116:Res:53.1,208691.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.40 208696[117:Spt:208694.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 208698[117:Res:208696.0,61.1] always3(s37) || -> . % 76.16/76.40 208699[117:SSi:208698.0,78232.0,78235.0,192136.0,208433.0,208689.0] || -> . % 76.16/76.40 208700[117:Spt:208699.0,208694.0,208696.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.40 208701[117:Spt:208699.0,208694.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.40 208705[117:Res:208701.0,61.1] always3(s38) || -> . % 76.16/76.40 208706[117:SSi:208705.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.40 208707[115:Spt:208706.0,208432.0,208433.0] || until2p7(s37)*+ -> . % 76.16/76.40 208708[115:Spt:208706.0,208432.1] || -> node4(s36)*. % 76.16/76.40 208710[115:MRR:810.0,208708.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.40 208713[115:Res:53.1,208710.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.40 208715[116:Spt:208713.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 208717[116:Res:208715.0,61.1] always3(s36) || -> . % 76.16/76.40 208718[116:SSi:208717.0,78227.0,78231.0,192135.0,208431.0,208708.0] || -> . % 76.16/76.40 208719[116:Spt:208718.0,208713.0,208715.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.40 208720[116:Spt:208718.0,208713.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.40 208724[116:Res:208720.0,61.1] always3(s37) || -> . % 76.16/76.40 208725[116:SSi:208724.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.40 208726[114:Spt:208725.0,208430.0,208431.0] || until2p7(s36)*+ -> . % 76.16/76.40 208727[114:Spt:208725.0,208430.1] || -> node4(s35)*. % 76.16/76.40 208729[114:MRR:813.0,208727.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.40 208732[114:Res:53.1,208729.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.40 208737[115:Spt:208732.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 208739[115:Res:208737.0,61.1] always3(s35) || -> . % 76.16/76.40 208740[115:SSi:208739.0,78223.0,78226.0,192134.0,208429.0,208727.0] || -> . % 76.16/76.40 208741[115:Spt:208740.0,208732.0,208737.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.40 208742[115:Spt:208740.0,208732.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.40 208746[115:Res:208742.0,61.1] always3(s36) || -> . % 76.16/76.40 208747[115:SSi:208746.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.40 208748[113:Spt:208747.0,208428.0,208429.0] || until2p7(s35)*+ -> . % 76.16/76.40 208749[113:Spt:208747.0,208428.1] || -> node4(s34)*. % 76.16/76.40 208751[113:MRR:816.0,208749.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.40 208754[113:Res:53.1,208751.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.40 208756[114:Spt:208754.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 208758[114:Res:208756.0,61.1] always3(s34) || -> . % 76.16/76.40 208759[114:SSi:208758.0,78218.0,78222.0,192133.0,208427.0,208749.0] || -> . % 76.16/76.40 208760[114:Spt:208759.0,208754.0,208756.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.40 208761[114:Spt:208759.0,208754.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.40 208765[114:Res:208761.0,61.1] always3(s35) || -> . % 76.16/76.40 208766[114:SSi:208765.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.40 208767[112:Spt:208766.0,208426.0,208427.0] || until2p7(s34)*+ -> . % 76.16/76.40 208768[112:Spt:208766.0,208426.1] || -> node4(s33)*. % 76.16/76.40 208770[112:MRR:819.0,208768.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.40 208773[112:Res:53.1,208770.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.40 208775[113:Spt:208773.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 208777[113:Res:208775.0,61.1] always3(s33) || -> . % 76.16/76.40 208778[113:SSi:208777.0,78214.0,78217.0,192132.0,208425.0,208768.0] || -> . % 76.16/76.40 208779[113:Spt:208778.0,208773.0,208775.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.40 208780[113:Spt:208778.0,208773.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.40 208784[113:Res:208780.0,61.1] always3(s34) || -> . % 76.16/76.40 208785[113:SSi:208784.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.40 208786[111:Spt:208785.0,208424.0,208425.0] || until2p7(s33)*+ -> . % 76.16/76.40 208787[111:Spt:208785.0,208424.1] || -> node4(s32)*. % 76.16/76.40 208789[111:MRR:822.0,208787.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.40 208792[111:Res:53.1,208789.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.40 208794[112:Spt:208792.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 208796[112:Res:208794.0,61.1] always3(s32) || -> . % 76.16/76.40 208797[112:SSi:208796.0,78209.0,78213.0,192131.0,208423.0,208787.0] || -> . % 76.16/76.40 208798[112:Spt:208797.0,208792.0,208794.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.40 208799[112:Spt:208797.0,208792.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.40 208803[112:Res:208799.0,61.1] always3(s33) || -> . % 76.16/76.40 208804[112:SSi:208803.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.40 208805[110:Spt:208804.0,208422.0,208423.0] || until2p7(s32)*+ -> . % 76.16/76.40 208806[110:Spt:208804.0,208422.1] || -> node4(s31)*. % 76.16/76.40 208808[110:MRR:825.0,208806.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.40 208811[110:Res:53.1,208808.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.40 208816[111:Spt:208811.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 208818[111:Res:208816.0,61.1] always3(s31) || -> . % 76.16/76.40 208819[111:SSi:208818.0,78205.0,78208.0,192130.0,208421.0,208806.0] || -> . % 76.16/76.40 208820[111:Spt:208819.0,208811.0,208816.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.40 208821[111:Spt:208819.0,208811.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.40 208825[111:Res:208821.0,61.1] always3(s32) || -> . % 76.16/76.40 208826[111:SSi:208825.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.40 208827[109:Spt:208826.0,208420.0,208421.0] || until2p7(s31)*+ -> . % 76.16/76.40 208828[109:Spt:208826.0,208420.1] || -> node4(s30)*. % 76.16/76.40 208830[109:MRR:828.0,208828.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.40 208833[109:Res:53.1,208830.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.40 208835[110:Spt:208833.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 208837[110:Res:208835.0,61.1] always3(s30) || -> . % 76.16/76.40 208838[110:SSi:208837.0,78200.0,78204.0,192129.0,208419.0,208828.0] || -> . % 76.16/76.40 208839[110:Spt:208838.0,208833.0,208835.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.40 208840[110:Spt:208838.0,208833.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.40 208844[110:Res:208840.0,61.1] always3(s31) || -> . % 76.16/76.40 208845[110:SSi:208844.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.40 208846[108:Spt:208845.0,208418.0,208419.0] || until2p7(s30)*+ -> . % 76.16/76.40 208847[108:Spt:208845.0,208418.1] || -> node4(s29)*. % 76.16/76.40 208849[108:MRR:831.0,208847.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.40 208852[108:Res:53.1,208849.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.40 208854[109:Spt:208852.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 208856[109:Res:208854.0,61.1] always3(s29) || -> . % 76.16/76.40 208857[109:SSi:208856.0,78196.0,78199.0,192128.0,208417.0,208847.0] || -> . % 76.16/76.40 208858[109:Spt:208857.0,208852.0,208854.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.40 208859[109:Spt:208857.0,208852.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.40 208863[109:Res:208859.0,61.1] always3(s30) || -> . % 76.16/76.40 208864[109:SSi:208863.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.40 208865[107:Spt:208864.0,208416.0,208417.0] || until2p7(s29)*+ -> . % 76.16/76.40 208866[107:Spt:208864.0,208416.1] || -> node4(s28)*. % 76.16/76.40 208868[107:MRR:834.0,208866.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.40 208871[107:Res:53.1,208868.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.40 208873[108:Spt:208871.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 208875[108:Res:208873.0,61.1] always3(s28) || -> . % 76.16/76.40 208876[108:SSi:208875.0,78191.0,78195.0,192127.0,208415.0,208866.0] || -> . % 76.16/76.40 208877[108:Spt:208876.0,208871.0,208873.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.40 208878[108:Spt:208876.0,208871.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.40 208882[108:Res:208878.0,61.1] always3(s29) || -> . % 76.16/76.40 208883[108:SSi:208882.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.40 208884[106:Spt:208883.0,208414.0,208415.0] || until2p7(s28)*+ -> . % 76.16/76.40 208885[106:Spt:208883.0,208414.1] || -> node4(s27)*. % 76.16/76.40 208887[106:MRR:837.0,208885.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.40 208890[106:Res:53.1,208887.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.40 208895[107:Spt:208890.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 208897[107:Res:208895.0,61.1] always3(s27) || -> . % 76.16/76.40 208898[107:SSi:208897.0,78187.0,78190.0,192126.0,208413.0,208885.0] || -> . % 76.16/76.40 208899[107:Spt:208898.0,208890.0,208895.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.40 208900[107:Spt:208898.0,208890.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.40 208904[107:Res:208900.0,61.1] always3(s28) || -> . % 76.16/76.40 208905[107:SSi:208904.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.40 208906[105:Spt:208905.0,208412.0,208413.0] || until2p7(s27)*+ -> . % 76.16/76.40 208907[105:Spt:208905.0,208412.1] || -> node4(s26)*. % 76.16/76.40 208909[105:MRR:840.0,208907.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.40 208912[105:Res:53.1,208909.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.40 208914[106:Spt:208912.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 208916[106:Res:208914.0,61.1] always3(s26) || -> . % 76.16/76.40 208917[106:SSi:208916.0,78182.0,78186.0,192125.0,208411.0,208907.0] || -> . % 76.16/76.40 208918[106:Spt:208917.0,208912.0,208914.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.40 208919[106:Spt:208917.0,208912.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.40 208923[106:Res:208919.0,61.1] always3(s27) || -> . % 76.16/76.40 208924[106:SSi:208923.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.40 208925[104:Spt:208924.0,208410.0,208411.0] || until2p7(s26)*+ -> . % 76.16/76.40 208926[104:Spt:208924.0,208410.1] || -> node4(s25)*. % 76.16/76.40 208928[104:MRR:843.0,208926.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.40 208931[104:Res:53.1,208928.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.40 208933[105:Spt:208931.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 208935[105:Res:208933.0,61.1] always3(s25) || -> . % 76.16/76.40 208936[105:SSi:208935.0,78178.0,78181.0,192124.0,208409.0,208926.0] || -> . % 76.16/76.40 208937[105:Spt:208936.0,208931.0,208933.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.40 208938[105:Spt:208936.0,208931.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.40 208942[105:Res:208938.0,61.1] always3(s26) || -> . % 76.16/76.40 208943[105:SSi:208942.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.40 208944[103:Spt:208943.0,208408.0,208409.0] || until2p7(s25)*+ -> . % 76.16/76.40 208945[103:Spt:208943.0,208408.1] || -> node4(s24)*. % 76.16/76.40 208947[103:MRR:846.0,208945.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.40 208950[103:Res:53.1,208947.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.40 208952[104:Spt:208950.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 208954[104:Res:208952.0,61.1] always3(s24) || -> . % 76.16/76.40 208955[104:SSi:208954.0,78173.0,78177.0,192123.0,208407.0,208945.0] || -> . % 76.16/76.40 208956[104:Spt:208955.0,208950.0,208952.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.40 208957[104:Spt:208955.0,208950.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.40 208961[104:Res:208957.0,61.1] always3(s25) || -> . % 76.16/76.40 208962[104:SSi:208961.0,78178.0,78181.0,192124.0] || -> . % 76.16/76.40 208963[102:Spt:208962.0,208406.0,208407.0] || until2p7(s24)*+ -> . % 76.16/76.40 208964[102:Spt:208962.0,208406.1] || -> node4(s23)*. % 76.16/76.40 208966[102:MRR:849.0,208964.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.40 208969[102:Res:53.1,208966.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.40 208974[103:Spt:208969.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 208976[103:Res:208974.0,61.1] always3(s23) || -> . % 76.16/76.40 208977[103:SSi:208976.0,78169.0,78172.0,192122.0,208405.0,208964.0] || -> . % 76.16/76.40 208978[103:Spt:208977.0,208969.0,208974.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.40 208979[103:Spt:208977.0,208969.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.40 208983[103:Res:208979.0,61.1] always3(s24) || -> . % 76.16/76.40 208984[103:SSi:208983.0,78173.0,78177.0,192123.0] || -> . % 76.16/76.40 208985[101:Spt:208984.0,208404.0,208405.0] || until2p7(s23)*+ -> . % 76.16/76.40 208986[101:Spt:208984.0,208404.1] || -> node4(s22)*. % 76.16/76.40 208988[101:MRR:852.0,208986.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.40 208991[101:Res:53.1,208988.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.40 208993[102:Spt:208991.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 208995[102:Res:208993.0,61.1] always3(s22) || -> . % 76.16/76.40 208996[102:SSi:208995.0,78164.0,78168.0,192121.0,208403.0,208986.0] || -> . % 76.16/76.40 208997[102:Spt:208996.0,208991.0,208993.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.40 208998[102:Spt:208996.0,208991.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.40 209002[102:Res:208998.0,61.1] always3(s23) || -> . % 76.16/76.40 209003[102:SSi:209002.0,78169.0,78172.0,192122.0] || -> . % 76.16/76.40 209004[100:Spt:209003.0,208402.0,208403.0] || until2p7(s22)*+ -> . % 76.16/76.40 209005[100:Spt:209003.0,208402.1] || -> node4(s21)*. % 76.16/76.40 209007[100:MRR:855.0,209005.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.40 209010[100:Res:53.1,209007.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.40 209012[101:Spt:209010.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 209014[101:Res:209012.0,61.1] always3(s21) || -> . % 76.16/76.40 209015[101:SSi:209014.0,78160.0,78163.0,192120.0,208401.0,209005.0] || -> . % 76.16/76.40 209016[101:Spt:209015.0,209010.0,209012.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.40 209017[101:Spt:209015.0,209010.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.40 209021[101:Res:209017.0,61.1] always3(s22) || -> . % 76.16/76.40 209022[101:SSi:209021.0,78164.0,78168.0,192121.0] || -> . % 76.16/76.40 209023[99:Spt:209022.0,208400.0,208401.0] || until2p7(s21)*+ -> . % 76.16/76.40 209024[99:Spt:209022.0,208400.1] || -> node4(s20)*. % 76.16/76.40 209026[99:MRR:858.0,209024.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.40 209029[99:Res:53.1,209026.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.40 209031[100:Spt:209029.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 209033[100:Res:209031.0,61.1] always3(s20) || -> . % 76.16/76.40 209034[100:SSi:209033.0,78155.0,78159.0,192119.0,208399.0,209024.0] || -> . % 76.16/76.40 209035[100:Spt:209034.0,209029.0,209031.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.40 209036[100:Spt:209034.0,209029.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.40 209040[100:Res:209036.0,61.1] always3(s21) || -> . % 76.16/76.40 209041[100:SSi:209040.0,78160.0,78163.0,192120.0] || -> . % 76.16/76.40 209042[98:Spt:209041.0,208398.0,208399.0] || until2p7(s20)*+ -> . % 76.16/76.40 209043[98:Spt:209041.0,208398.1] || -> node4(s19)*. % 76.16/76.40 209045[98:MRR:861.0,209043.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.40 209048[98:Res:53.1,209045.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.40 209053[99:Spt:209048.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.40 209055[99:Res:209053.0,61.1] always3(s19) || -> . % 76.16/76.40 209056[99:SSi:209055.0,78151.0,78154.0,192118.0,208397.0,209043.0] || -> . % 76.16/76.40 209057[99:Spt:209056.0,209048.0,209053.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.40 209058[99:Spt:209056.0,209048.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.40 209062[99:Res:209058.0,61.1] always3(s20) || -> . % 76.16/76.40 209063[99:SSi:209062.0,78155.0,78159.0,192119.0] || -> . % 76.16/76.40 209064[97:Spt:209063.0,208396.0,208397.0] || until2p7(s19)*+ -> . % 76.16/76.40 209065[97:Spt:209063.0,208396.1] || -> node4(s18)*. % 76.16/76.40 209067[97:MRR:864.0,209065.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.40 209070[97:Res:53.1,209067.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.40 209072[98:Spt:209070.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.40 209074[98:Res:209072.0,61.1] always3(s18) || -> . % 76.16/76.40 209075[98:SSi:209074.0,78146.0,78150.0,192117.0,208395.0,209065.0] || -> . % 76.16/76.40 209076[98:Spt:209075.0,209070.0,209072.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.40 209077[98:Spt:209075.0,209070.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.40 209081[98:Res:209077.0,61.1] always3(s19) || -> . % 76.16/76.40 209082[98:SSi:209081.0,78151.0,78154.0,192118.0] || -> . % 76.16/76.40 209083[96:Spt:209082.0,208394.0,208395.0] || until2p7(s18)*+ -> . % 76.16/76.40 209084[96:Spt:209082.0,208394.1] || -> node4(s17)*. % 76.16/76.40 209086[96:MRR:867.0,209084.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.40 209089[96:Res:53.1,209086.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.40 209091[97:Spt:209089.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.40 209093[97:Res:209091.0,61.1] always3(s17) || -> . % 76.16/76.40 209094[97:SSi:209093.0,78142.0,78145.0,192116.0,208393.0,209084.0] || -> . % 76.16/76.40 209095[97:Spt:209094.0,209089.0,209091.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.40 209096[97:Spt:209094.0,209089.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.40 209100[97:Res:209096.0,61.1] always3(s18) || -> . % 76.16/76.40 209101[97:SSi:209100.0,78146.0,78150.0,192117.0] || -> . % 76.16/76.40 209102[95:Spt:209101.0,208392.0,208393.0] || until2p7(s17)*+ -> . % 76.16/76.40 209103[95:Spt:209101.0,208392.1] || -> node4(s16)*. % 76.16/76.40 209105[95:MRR:870.0,209103.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.40 209108[95:Res:53.1,209105.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.40 209110[96:Spt:209108.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.40 209112[96:Res:209110.0,61.1] always3(s16) || -> . % 76.16/76.40 209113[96:SSi:209112.0,78137.0,78141.0,192115.0,208391.0,209103.0] || -> . % 76.16/76.40 209114[96:Spt:209113.0,209108.0,209110.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.40 209115[96:Spt:209113.0,209108.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.40 209119[96:Res:209115.0,61.1] always3(s17) || -> . % 76.16/76.40 209120[96:SSi:209119.0,78142.0,78145.0,192116.0] || -> . % 76.16/76.40 209121[94:Spt:209120.0,208390.0,208391.0] || until2p7(s16)*+ -> . % 76.16/76.40 209122[94:Spt:209120.0,208390.1] || -> node4(s15)*. % 76.16/76.40 209124[94:MRR:873.0,209122.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.40 209127[94:Res:53.1,209124.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.40 209132[95:Spt:209127.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.40 209134[95:Res:209132.0,61.1] always3(s15) || -> . % 76.16/76.40 209135[95:SSi:209134.0,78133.0,78136.0,192114.0,208389.0,209122.0] || -> . % 76.16/76.40 209136[95:Spt:209135.0,209127.0,209132.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.40 209137[95:Spt:209135.0,209127.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.40 209141[95:Res:209137.0,61.1] always3(s16) || -> . % 76.16/76.40 209142[95:SSi:209141.0,78137.0,78141.0,192115.0] || -> . % 76.16/76.40 209143[93:Spt:209142.0,208388.0,208389.0] || until2p7(s15)*+ -> . % 76.16/76.40 209144[93:Spt:209142.0,208388.1] || -> node4(s14)*. % 76.16/76.40 209146[93:MRR:876.0,209144.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.40 209149[93:Res:53.1,209146.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.40 209151[93:MRR:209149.0,208378.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.40 209153[93:Res:209151.0,61.1] always3(s15) || -> . % 76.16/76.40 209154[93:SSi:209153.0,78133.0,78136.0,192114.0] || -> . % 76.16/76.40 209155[91:Spt:209154.0,208246.0,208249.0] || trans(s49,s14)*+ -> . % 76.16/76.40 209156[91:Spt:209154.0,208246.1,208246.2,208246.3,208246.4,208246.5,208246.6,208246.7,208246.8] || -> trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.40 209158[91:MRR:208248.1,209155.0] xuntil6(s49) || -> trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.40 209159[92:Spt:209156.0] || -> trans(s49,s13)*. % 76.16/76.40 209160[92:Res:209159.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s13)*. % 76.16/76.40 209162[92:Res:209159.0,60.0] || -> node2(s49,s13)*. % 76.16/76.40 209163[92:SSi:209160.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s13)*. % 76.16/76.40 209164[92:Res:209162.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)*. % 76.16/76.41 209284[92:SoR:209164.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)*. % 76.16/76.41 209286[92:SoR:209284.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s13,c_busy)* xuntil6(s49). % 76.16/76.41 209287[92:SSi:209286.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s13,c_busy)* xuntil6(s49). % 76.16/76.41 209288[93:Spt:209287.1] || -> m_main_v_state(s13,c_busy)*. % 76.16/76.41 209290[93:Res:209288.0,61.1] always3(s13) || -> . % 76.16/76.41 209291[93:SSi:209290.0,78124.0,78127.0,192112.0] || -> . % 76.16/76.41 209292[93:Spt:209291.0,209287.1,209288.0] || m_main_v_state(s13,c_busy)*+ -> . % 76.16/76.41 209293[93:Spt:209291.0,209287.0,209287.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.41 209297[93:MRR:209284.2,209292.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.41 209298[93:Res:53.1,209293.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.41 209300[93:MRR:209298.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.41 209301[93:MRR:209163.0,209300.0] || -> until2p7(s13)*. % 76.16/76.41 209302[93:MRR:209.0,209301.0] || -> until2p7(s14)* node4(s13). % 76.16/76.41 209303[94:Spt:209302.0] || -> until2p7(s14)*. % 76.16/76.41 209304[94:MRR:210.0,209303.0] || -> until2p7(s15)* node4(s14). % 76.16/76.41 209305[95:Spt:209304.0] || -> until2p7(s15)*. % 76.16/76.41 209306[95:MRR:211.0,209305.0] || -> until2p7(s16)* node4(s15). % 76.16/76.41 209307[96:Spt:209306.0] || -> until2p7(s16)*. % 76.16/76.41 209308[96:MRR:212.0,209307.0] || -> until2p7(s17)* node4(s16). % 76.16/76.41 209309[97:Spt:209308.0] || -> until2p7(s17)*. % 76.16/76.41 209310[97:MRR:213.0,209309.0] || -> until2p7(s18)* node4(s17). % 76.16/76.41 209311[98:Spt:209310.0] || -> until2p7(s18)*. % 76.16/76.41 209312[98:MRR:214.0,209311.0] || -> until2p7(s19)* node4(s18). % 76.16/76.41 209313[99:Spt:209312.0] || -> until2p7(s19)*. % 76.16/76.41 209314[99:MRR:215.0,209313.0] || -> until2p7(s20)* node4(s19). % 76.16/76.41 209315[100:Spt:209314.0] || -> until2p7(s20)*. % 76.16/76.41 209316[100:MRR:216.0,209315.0] || -> until2p7(s21)* node4(s20). % 76.16/76.41 209317[101:Spt:209316.0] || -> until2p7(s21)*. % 76.16/76.41 209318[101:MRR:217.0,209317.0] || -> until2p7(s22)* node4(s21). % 76.16/76.41 209319[102:Spt:209318.0] || -> until2p7(s22)*. % 76.16/76.41 209320[102:MRR:218.0,209319.0] || -> until2p7(s23)* node4(s22). % 76.16/76.41 209321[103:Spt:209320.0] || -> until2p7(s23)*. % 76.16/76.41 209322[103:MRR:219.0,209321.0] || -> until2p7(s24)* node4(s23). % 76.16/76.41 209323[104:Spt:209322.0] || -> until2p7(s24)*. % 76.16/76.41 209324[104:MRR:220.0,209323.0] || -> until2p7(s25)* node4(s24). % 76.16/76.41 209325[105:Spt:209324.0] || -> until2p7(s25)*. % 76.16/76.41 209326[105:MRR:221.0,209325.0] || -> until2p7(s26)* node4(s25). % 76.16/76.41 209327[106:Spt:209326.0] || -> until2p7(s26)*. % 76.16/76.41 209328[106:MRR:222.0,209327.0] || -> until2p7(s27)* node4(s26). % 76.16/76.41 209329[107:Spt:209328.0] || -> until2p7(s27)*. % 76.16/76.41 209330[107:MRR:223.0,209329.0] || -> until2p7(s28)* node4(s27). % 76.16/76.41 209331[108:Spt:209330.0] || -> until2p7(s28)*. % 76.16/76.41 209332[108:MRR:224.0,209331.0] || -> until2p7(s29)* node4(s28). % 76.16/76.41 209333[109:Spt:209332.0] || -> until2p7(s29)*. % 76.16/76.41 209334[109:MRR:225.0,209333.0] || -> until2p7(s30)* node4(s29). % 76.16/76.41 209335[110:Spt:209334.0] || -> until2p7(s30)*. % 76.16/76.41 209336[110:MRR:226.0,209335.0] || -> until2p7(s31)* node4(s30). % 76.16/76.41 209337[111:Spt:209336.0] || -> until2p7(s31)*. % 76.16/76.41 209338[111:MRR:227.0,209337.0] || -> until2p7(s32)* node4(s31). % 76.16/76.41 209339[112:Spt:209338.0] || -> until2p7(s32)*. % 76.16/76.41 209340[112:MRR:228.0,209339.0] || -> until2p7(s33)* node4(s32). % 76.16/76.41 209341[113:Spt:209340.0] || -> until2p7(s33)*. % 76.16/76.41 209342[113:MRR:229.0,209341.0] || -> until2p7(s34)* node4(s33). % 76.16/76.41 209343[114:Spt:209342.0] || -> until2p7(s34)*. % 76.16/76.41 209344[114:MRR:230.0,209343.0] || -> until2p7(s35)* node4(s34). % 76.16/76.41 209345[115:Spt:209344.0] || -> until2p7(s35)*. % 76.16/76.41 209346[115:MRR:231.0,209345.0] || -> until2p7(s36)* node4(s35). % 76.16/76.41 209347[116:Spt:209346.0] || -> until2p7(s36)*. % 76.16/76.41 209348[116:MRR:232.0,209347.0] || -> until2p7(s37)* node4(s36). % 76.16/76.41 209349[117:Spt:209348.0] || -> until2p7(s37)*. % 76.16/76.41 209350[117:MRR:235.0,209349.0] || -> until2p7(s38)* node4(s37). % 76.16/76.41 209351[118:Spt:209350.0] || -> until2p7(s38)*. % 76.16/76.41 209352[118:MRR:236.0,209351.0] || -> until2p7(s39)* node4(s38). % 76.16/76.41 209353[119:Spt:209352.0] || -> until2p7(s39)*. % 76.16/76.41 209354[119:MRR:237.0,209353.0] || -> until2p7(s40)* node4(s39). % 76.16/76.41 209355[120:Spt:209354.0] || -> until2p7(s40)*. % 76.16/76.41 209356[120:MRR:238.0,209355.0] || -> until2p7(s41)* node4(s40). % 76.16/76.41 209357[121:Spt:209356.0] || -> until2p7(s41)*. % 76.16/76.41 209358[121:MRR:239.0,209357.0] || -> until2p7(s42)* node4(s41). % 76.16/76.41 209359[122:Spt:209358.0] || -> until2p7(s42)*. % 76.16/76.41 209360[122:MRR:240.0,209359.0] || -> until2p7(s43)* node4(s42). % 76.16/76.41 209361[123:Spt:209360.0] || -> until2p7(s43)*. % 76.16/76.41 209362[123:MRR:241.0,209361.0] || -> until2p7(s44)* node4(s43). % 76.16/76.41 209363[124:Spt:209362.0] || -> until2p7(s44)*. % 76.16/76.41 209364[124:MRR:539.0,209363.0] || -> until2p7(s45)* node4(s44). % 76.16/76.41 209365[125:Spt:209364.0] || -> until2p7(s45)*. % 76.16/76.41 209366[125:MRR:544.0,209365.0] || -> until2p7(s46)* node4(s45). % 76.16/76.41 209367[126:Spt:209366.0] || -> until2p7(s46)*. % 76.16/76.41 209368[126:MRR:549.0,209367.0] || -> until2p7(s47)* node4(s46). % 76.16/76.41 209369[127:Spt:209368.0] || -> until2p7(s47)*. % 76.16/76.41 209370[127:MRR:554.0,209369.0] || -> until2p7(s48)* node4(s47). % 76.16/76.41 209371[128:Spt:209370.0] || -> until2p7(s48)*. % 76.16/76.41 209372[128:MRR:559.0,209371.0] || -> until2p7(s49)* node4(s48). % 76.16/76.41 209373[129:Spt:209372.0] || -> until2p7(s49)*. % 76.16/76.41 209374[129:MRR:194.0,209373.0] || -> node4(s49)*. % 76.16/76.41 209375[129:MRR:209297.0,209374.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.16/76.41 209379[129:Res:53.1,209375.0] || -> m_main_v_state(s49,c_busy)*. % 76.16/76.41 209381[129:MRR:209379.0,78381.0] || -> . % 76.16/76.41 209382[129:Spt:209381.0,209372.0,209373.0] || until2p7(s49)*+ -> . % 76.16/76.41 209383[129:Spt:209381.0,209372.1] || -> node4(s48)*. % 76.16/76.41 209384[129:MRR:78384.0,209383.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.16/76.41 209387[129:Res:53.1,209384.0] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.41 209390[129:Res:209387.0,61.1] always3(s48) || -> . % 76.16/76.41 209391[129:SSi:209390.0,78281.0,78387.0,192147.0,209371.0,209383.0] || -> . % 76.16/76.41 209392[128:Spt:209391.0,209370.0,209371.0] || until2p7(s48)*+ -> . % 76.16/76.41 209393[128:Spt:209391.0,209370.1] || -> node4(s47)*. % 76.16/76.41 209395[128:MRR:777.0,209393.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.16/76.41 209407[128:Res:53.1,209395.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.16/76.41 209409[129:Spt:209407.0] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.41 209411[129:Res:209409.0,61.1] always3(s47) || -> . % 76.16/76.41 209412[129:SSi:209411.0,78277.0,78280.0,192146.0,209369.0,209393.0] || -> . % 76.16/76.41 209413[129:Spt:209412.0,209407.0,209409.0] || m_main_v_state(s47,c_busy)* -> . % 76.16/76.41 209414[129:Spt:209412.0,209407.1] || -> m_main_v_state(s48,c_busy)*. % 76.16/76.41 209418[129:Res:209414.0,61.1] always3(s48) || -> . % 76.16/76.41 209419[129:SSi:209418.0,78281.0,78387.0,192147.0] || -> . % 76.16/76.41 209420[127:Spt:209419.0,209368.0,209369.0] || until2p7(s47)*+ -> . % 76.16/76.41 209421[127:Spt:209419.0,209368.1] || -> node4(s46)*. % 76.16/76.41 209423[127:MRR:780.0,209421.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.16/76.41 209430[127:Res:53.1,209423.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.16/76.41 209435[128:Spt:209430.0] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.41 209437[128:Res:209435.0,61.1] always3(s46) || -> . % 76.16/76.41 209438[128:SSi:209437.0,78272.0,78276.0,192145.0,209367.0,209421.0] || -> . % 76.16/76.41 209439[128:Spt:209438.0,209430.0,209435.0] || m_main_v_state(s46,c_busy)* -> . % 76.16/76.41 209440[128:Spt:209438.0,209430.1] || -> m_main_v_state(s47,c_busy)*. % 76.16/76.41 209444[128:Res:209440.0,61.1] always3(s47) || -> . % 76.16/76.41 209445[128:SSi:209444.0,78277.0,78280.0,192146.0] || -> . % 76.16/76.41 209446[126:Spt:209445.0,209366.0,209367.0] || until2p7(s46)*+ -> . % 76.16/76.41 209447[126:Spt:209445.0,209366.1] || -> node4(s45)*. % 76.16/76.41 209449[126:MRR:783.0,209447.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.16/76.41 209452[126:Res:53.1,209449.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.16/76.41 209454[127:Spt:209452.0] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.41 209456[127:Res:209454.0,61.1] always3(s45) || -> . % 76.16/76.41 209457[127:SSi:209456.0,78268.0,78271.0,192144.0,209365.0,209447.0] || -> . % 76.16/76.41 209458[127:Spt:209457.0,209452.0,209454.0] || m_main_v_state(s45,c_busy)* -> . % 76.16/76.41 209459[127:Spt:209457.0,209452.1] || -> m_main_v_state(s46,c_busy)*. % 76.16/76.41 209463[127:Res:209459.0,61.1] always3(s46) || -> . % 76.16/76.41 209464[127:SSi:209463.0,78272.0,78276.0,192145.0] || -> . % 76.16/76.41 209465[125:Spt:209464.0,209364.0,209365.0] || until2p7(s45)*+ -> . % 76.16/76.41 209466[125:Spt:209464.0,209364.1] || -> node4(s44)*. % 76.16/76.41 209468[125:MRR:786.0,209466.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.16/76.41 209471[125:Res:53.1,209468.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.16/76.41 209473[126:Spt:209471.0] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.41 209475[126:Res:209473.0,61.1] always3(s44) || -> . % 76.16/76.41 209476[126:SSi:209475.0,78263.0,78267.0,192143.0,209363.0,209466.0] || -> . % 76.16/76.41 209477[126:Spt:209476.0,209471.0,209473.0] || m_main_v_state(s44,c_busy)* -> . % 76.16/76.41 209478[126:Spt:209476.0,209471.1] || -> m_main_v_state(s45,c_busy)*. % 76.16/76.41 209482[126:Res:209478.0,61.1] always3(s45) || -> . % 76.16/76.41 209483[126:SSi:209482.0,78268.0,78271.0,192144.0] || -> . % 76.16/76.41 209484[124:Spt:209483.0,209362.0,209363.0] || until2p7(s44)*+ -> . % 76.16/76.41 209485[124:Spt:209483.0,209362.1] || -> node4(s43)*. % 76.16/76.41 209487[124:MRR:789.0,209485.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.16/76.41 209490[124:Res:53.1,209487.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.16/76.41 209492[125:Spt:209490.0] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.41 209494[125:Res:209492.0,61.1] always3(s43) || -> . % 76.16/76.41 209495[125:SSi:209494.0,78259.0,78262.0,192142.0,209361.0,209485.0] || -> . % 76.16/76.41 209496[125:Spt:209495.0,209490.0,209492.0] || m_main_v_state(s43,c_busy)* -> . % 76.16/76.41 209497[125:Spt:209495.0,209490.1] || -> m_main_v_state(s44,c_busy)*. % 76.16/76.41 209501[125:Res:209497.0,61.1] always3(s44) || -> . % 76.16/76.41 209502[125:SSi:209501.0,78263.0,78267.0,192143.0] || -> . % 76.16/76.41 209503[123:Spt:209502.0,209360.0,209361.0] || until2p7(s43)*+ -> . % 76.16/76.41 209504[123:Spt:209502.0,209360.1] || -> node4(s42)*. % 76.16/76.41 209506[123:MRR:792.0,209504.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.16/76.41 209509[123:Res:53.1,209506.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.16/76.41 209514[124:Spt:209509.0] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.41 209516[124:Res:209514.0,61.1] always3(s42) || -> . % 76.16/76.41 209517[124:SSi:209516.0,78254.0,78258.0,192141.0,209359.0,209504.0] || -> . % 76.16/76.41 209518[124:Spt:209517.0,209509.0,209514.0] || m_main_v_state(s42,c_busy)* -> . % 76.16/76.41 209519[124:Spt:209517.0,209509.1] || -> m_main_v_state(s43,c_busy)*. % 76.16/76.41 209523[124:Res:209519.0,61.1] always3(s43) || -> . % 76.16/76.41 209524[124:SSi:209523.0,78259.0,78262.0,192142.0] || -> . % 76.16/76.41 209525[122:Spt:209524.0,209358.0,209359.0] || until2p7(s42)*+ -> . % 76.16/76.41 209526[122:Spt:209524.0,209358.1] || -> node4(s41)*. % 76.16/76.41 209528[122:MRR:795.0,209526.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.16/76.41 209531[122:Res:53.1,209528.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.16/76.41 209533[123:Spt:209531.0] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.41 209535[123:Res:209533.0,61.1] always3(s41) || -> . % 76.16/76.41 209536[123:SSi:209535.0,78250.0,78253.0,192140.0,209357.0,209526.0] || -> . % 76.16/76.41 209537[123:Spt:209536.0,209531.0,209533.0] || m_main_v_state(s41,c_busy)* -> . % 76.16/76.41 209538[123:Spt:209536.0,209531.1] || -> m_main_v_state(s42,c_busy)*. % 76.16/76.41 209542[123:Res:209538.0,61.1] always3(s42) || -> . % 76.16/76.41 209543[123:SSi:209542.0,78254.0,78258.0,192141.0] || -> . % 76.16/76.41 209544[121:Spt:209543.0,209356.0,209357.0] || until2p7(s41)*+ -> . % 76.16/76.41 209545[121:Spt:209543.0,209356.1] || -> node4(s40)*. % 76.16/76.41 209547[121:MRR:798.0,209545.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.16/76.41 209550[121:Res:53.1,209547.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.16/76.41 209552[122:Spt:209550.0] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.41 209554[122:Res:209552.0,61.1] always3(s40) || -> . % 76.16/76.41 209555[122:SSi:209554.0,78245.0,78249.0,192139.0,209355.0,209545.0] || -> . % 76.16/76.41 209556[122:Spt:209555.0,209550.0,209552.0] || m_main_v_state(s40,c_busy)* -> . % 76.16/76.41 209557[122:Spt:209555.0,209550.1] || -> m_main_v_state(s41,c_busy)*. % 76.16/76.41 209561[122:Res:209557.0,61.1] always3(s41) || -> . % 76.16/76.41 209562[122:SSi:209561.0,78250.0,78253.0,192140.0] || -> . % 76.16/76.41 209563[120:Spt:209562.0,209354.0,209355.0] || until2p7(s40)*+ -> . % 76.16/76.41 209564[120:Spt:209562.0,209354.1] || -> node4(s39)*. % 76.16/76.41 209566[120:MRR:801.0,209564.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.16/76.41 209569[120:Res:53.1,209566.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.16/76.41 209571[121:Spt:209569.0] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.41 209573[121:Res:209571.0,61.1] always3(s39) || -> . % 76.16/76.41 209574[121:SSi:209573.0,78241.0,78244.0,192138.0,209353.0,209564.0] || -> . % 76.16/76.41 209575[121:Spt:209574.0,209569.0,209571.0] || m_main_v_state(s39,c_busy)* -> . % 76.16/76.41 209576[121:Spt:209574.0,209569.1] || -> m_main_v_state(s40,c_busy)*. % 76.16/76.41 209580[121:Res:209576.0,61.1] always3(s40) || -> . % 76.16/76.41 209581[121:SSi:209580.0,78245.0,78249.0,192139.0] || -> . % 76.16/76.41 209582[119:Spt:209581.0,209352.0,209353.0] || until2p7(s39)*+ -> . % 76.16/76.41 209583[119:Spt:209581.0,209352.1] || -> node4(s38)*. % 76.16/76.41 209585[119:MRR:804.0,209583.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.16/76.41 209588[119:Res:53.1,209585.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.16/76.41 209593[120:Spt:209588.0] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.41 209595[120:Res:209593.0,61.1] always3(s38) || -> . % 76.16/76.41 209596[120:SSi:209595.0,78236.0,78240.0,192137.0,209351.0,209583.0] || -> . % 76.16/76.41 209597[120:Spt:209596.0,209588.0,209593.0] || m_main_v_state(s38,c_busy)* -> . % 76.16/76.41 209598[120:Spt:209596.0,209588.1] || -> m_main_v_state(s39,c_busy)*. % 76.16/76.41 209602[120:Res:209598.0,61.1] always3(s39) || -> . % 76.16/76.41 209603[120:SSi:209602.0,78241.0,78244.0,192138.0] || -> . % 76.16/76.41 209604[118:Spt:209603.0,209350.0,209351.0] || until2p7(s38)*+ -> . % 76.16/76.41 209605[118:Spt:209603.0,209350.1] || -> node4(s37)*. % 76.16/76.41 209607[118:MRR:807.0,209605.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.16/76.41 209610[118:Res:53.1,209607.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.16/76.41 209612[119:Spt:209610.0] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.41 209614[119:Res:209612.0,61.1] always3(s37) || -> . % 76.16/76.41 209615[119:SSi:209614.0,78232.0,78235.0,192136.0,209349.0,209605.0] || -> . % 76.16/76.41 209616[119:Spt:209615.0,209610.0,209612.0] || m_main_v_state(s37,c_busy)* -> . % 76.16/76.41 209617[119:Spt:209615.0,209610.1] || -> m_main_v_state(s38,c_busy)*. % 76.16/76.41 209621[119:Res:209617.0,61.1] always3(s38) || -> . % 76.16/76.41 209622[119:SSi:209621.0,78236.0,78240.0,192137.0] || -> . % 76.16/76.41 209623[117:Spt:209622.0,209348.0,209349.0] || until2p7(s37)*+ -> . % 76.16/76.41 209624[117:Spt:209622.0,209348.1] || -> node4(s36)*. % 76.16/76.41 209626[117:MRR:810.0,209624.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.16/76.41 209629[117:Res:53.1,209626.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.16/76.41 209631[118:Spt:209629.0] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.41 209633[118:Res:209631.0,61.1] always3(s36) || -> . % 76.16/76.41 209634[118:SSi:209633.0,78227.0,78231.0,192135.0,209347.0,209624.0] || -> . % 76.16/76.41 209635[118:Spt:209634.0,209629.0,209631.0] || m_main_v_state(s36,c_busy)* -> . % 76.16/76.41 209636[118:Spt:209634.0,209629.1] || -> m_main_v_state(s37,c_busy)*. % 76.16/76.41 209640[118:Res:209636.0,61.1] always3(s37) || -> . % 76.16/76.41 209641[118:SSi:209640.0,78232.0,78235.0,192136.0] || -> . % 76.16/76.41 209642[116:Spt:209641.0,209346.0,209347.0] || until2p7(s36)*+ -> . % 76.16/76.41 209643[116:Spt:209641.0,209346.1] || -> node4(s35)*. % 76.16/76.41 209645[116:MRR:813.0,209643.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.16/76.41 209648[116:Res:53.1,209645.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.16/76.41 209650[117:Spt:209648.0] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.41 209652[117:Res:209650.0,61.1] always3(s35) || -> . % 76.16/76.41 209653[117:SSi:209652.0,78223.0,78226.0,192134.0,209345.0,209643.0] || -> . % 76.16/76.41 209654[117:Spt:209653.0,209648.0,209650.0] || m_main_v_state(s35,c_busy)* -> . % 76.16/76.41 209655[117:Spt:209653.0,209648.1] || -> m_main_v_state(s36,c_busy)*. % 76.16/76.41 209659[117:Res:209655.0,61.1] always3(s36) || -> . % 76.16/76.41 209660[117:SSi:209659.0,78227.0,78231.0,192135.0] || -> . % 76.16/76.41 209661[115:Spt:209660.0,209344.0,209345.0] || until2p7(s35)*+ -> . % 76.16/76.41 209662[115:Spt:209660.0,209344.1] || -> node4(s34)*. % 76.16/76.41 209664[115:MRR:816.0,209662.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.16/76.41 209667[115:Res:53.1,209664.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.16/76.41 209672[116:Spt:209667.0] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.41 209674[116:Res:209672.0,61.1] always3(s34) || -> . % 76.16/76.41 209675[116:SSi:209674.0,78218.0,78222.0,192133.0,209343.0,209662.0] || -> . % 76.16/76.41 209676[116:Spt:209675.0,209667.0,209672.0] || m_main_v_state(s34,c_busy)* -> . % 76.16/76.41 209677[116:Spt:209675.0,209667.1] || -> m_main_v_state(s35,c_busy)*. % 76.16/76.41 209681[116:Res:209677.0,61.1] always3(s35) || -> . % 76.16/76.41 209682[116:SSi:209681.0,78223.0,78226.0,192134.0] || -> . % 76.16/76.41 209683[114:Spt:209682.0,209342.0,209343.0] || until2p7(s34)*+ -> . % 76.16/76.41 209684[114:Spt:209682.0,209342.1] || -> node4(s33)*. % 76.16/76.41 209686[114:MRR:819.0,209684.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.16/76.41 209689[114:Res:53.1,209686.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.16/76.41 209691[115:Spt:209689.0] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.41 209693[115:Res:209691.0,61.1] always3(s33) || -> . % 76.16/76.41 209694[115:SSi:209693.0,78214.0,78217.0,192132.0,209341.0,209684.0] || -> . % 76.16/76.41 209695[115:Spt:209694.0,209689.0,209691.0] || m_main_v_state(s33,c_busy)* -> . % 76.16/76.41 209696[115:Spt:209694.0,209689.1] || -> m_main_v_state(s34,c_busy)*. % 76.16/76.41 209700[115:Res:209696.0,61.1] always3(s34) || -> . % 76.16/76.41 209701[115:SSi:209700.0,78218.0,78222.0,192133.0] || -> . % 76.16/76.41 209702[113:Spt:209701.0,209340.0,209341.0] || until2p7(s33)*+ -> . % 76.16/76.41 209703[113:Spt:209701.0,209340.1] || -> node4(s32)*. % 76.16/76.41 209705[113:MRR:822.0,209703.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.16/76.41 209708[113:Res:53.1,209705.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.16/76.41 209710[114:Spt:209708.0] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.41 209712[114:Res:209710.0,61.1] always3(s32) || -> . % 76.16/76.41 209713[114:SSi:209712.0,78209.0,78213.0,192131.0,209339.0,209703.0] || -> . % 76.16/76.41 209714[114:Spt:209713.0,209708.0,209710.0] || m_main_v_state(s32,c_busy)* -> . % 76.16/76.41 209715[114:Spt:209713.0,209708.1] || -> m_main_v_state(s33,c_busy)*. % 76.16/76.41 209719[114:Res:209715.0,61.1] always3(s33) || -> . % 76.16/76.41 209720[114:SSi:209719.0,78214.0,78217.0,192132.0] || -> . % 76.16/76.41 209721[112:Spt:209720.0,209338.0,209339.0] || until2p7(s32)*+ -> . % 76.16/76.41 209722[112:Spt:209720.0,209338.1] || -> node4(s31)*. % 76.16/76.41 209724[112:MRR:825.0,209722.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.16/76.41 209727[112:Res:53.1,209724.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.16/76.41 209729[113:Spt:209727.0] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.41 209731[113:Res:209729.0,61.1] always3(s31) || -> . % 76.16/76.41 209732[113:SSi:209731.0,78205.0,78208.0,192130.0,209337.0,209722.0] || -> . % 76.16/76.41 209733[113:Spt:209732.0,209727.0,209729.0] || m_main_v_state(s31,c_busy)* -> . % 76.16/76.41 209734[113:Spt:209732.0,209727.1] || -> m_main_v_state(s32,c_busy)*. % 76.16/76.41 209738[113:Res:209734.0,61.1] always3(s32) || -> . % 76.16/76.41 209739[113:SSi:209738.0,78209.0,78213.0,192131.0] || -> . % 76.16/76.41 209740[111:Spt:209739.0,209336.0,209337.0] || until2p7(s31)*+ -> . % 76.16/76.41 209741[111:Spt:209739.0,209336.1] || -> node4(s30)*. % 76.16/76.41 209743[111:MRR:828.0,209741.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.16/76.41 209746[111:Res:53.1,209743.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.16/76.41 209751[112:Spt:209746.0] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.41 209753[112:Res:209751.0,61.1] always3(s30) || -> . % 76.16/76.41 209754[112:SSi:209753.0,78200.0,78204.0,192129.0,209335.0,209741.0] || -> . % 76.16/76.41 209755[112:Spt:209754.0,209746.0,209751.0] || m_main_v_state(s30,c_busy)* -> . % 76.16/76.41 209756[112:Spt:209754.0,209746.1] || -> m_main_v_state(s31,c_busy)*. % 76.16/76.41 209760[112:Res:209756.0,61.1] always3(s31) || -> . % 76.16/76.41 209761[112:SSi:209760.0,78205.0,78208.0,192130.0] || -> . % 76.16/76.41 209762[110:Spt:209761.0,209334.0,209335.0] || until2p7(s30)*+ -> . % 76.16/76.41 209763[110:Spt:209761.0,209334.1] || -> node4(s29)*. % 76.16/76.41 209765[110:MRR:831.0,209763.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.16/76.41 209768[110:Res:53.1,209765.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.16/76.41 209770[111:Spt:209768.0] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.41 209772[111:Res:209770.0,61.1] always3(s29) || -> . % 76.16/76.41 209773[111:SSi:209772.0,78196.0,78199.0,192128.0,209333.0,209763.0] || -> . % 76.16/76.41 209774[111:Spt:209773.0,209768.0,209770.0] || m_main_v_state(s29,c_busy)* -> . % 76.16/76.41 209775[111:Spt:209773.0,209768.1] || -> m_main_v_state(s30,c_busy)*. % 76.16/76.41 209779[111:Res:209775.0,61.1] always3(s30) || -> . % 76.16/76.41 209780[111:SSi:209779.0,78200.0,78204.0,192129.0] || -> . % 76.16/76.41 209781[109:Spt:209780.0,209332.0,209333.0] || until2p7(s29)*+ -> . % 76.16/76.41 209782[109:Spt:209780.0,209332.1] || -> node4(s28)*. % 76.16/76.41 209784[109:MRR:834.0,209782.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.16/76.41 209787[109:Res:53.1,209784.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.16/76.41 209789[110:Spt:209787.0] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.41 209791[110:Res:209789.0,61.1] always3(s28) || -> . % 76.16/76.41 209792[110:SSi:209791.0,78191.0,78195.0,192127.0,209331.0,209782.0] || -> . % 76.16/76.41 209793[110:Spt:209792.0,209787.0,209789.0] || m_main_v_state(s28,c_busy)* -> . % 76.16/76.41 209794[110:Spt:209792.0,209787.1] || -> m_main_v_state(s29,c_busy)*. % 76.16/76.41 209798[110:Res:209794.0,61.1] always3(s29) || -> . % 76.16/76.41 209799[110:SSi:209798.0,78196.0,78199.0,192128.0] || -> . % 76.16/76.41 209800[108:Spt:209799.0,209330.0,209331.0] || until2p7(s28)*+ -> . % 76.16/76.41 209801[108:Spt:209799.0,209330.1] || -> node4(s27)*. % 76.16/76.41 209803[108:MRR:837.0,209801.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.16/76.41 209806[108:Res:53.1,209803.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.16/76.41 209808[109:Spt:209806.0] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.41 209810[109:Res:209808.0,61.1] always3(s27) || -> . % 76.16/76.41 209811[109:SSi:209810.0,78187.0,78190.0,192126.0,209329.0,209801.0] || -> . % 76.16/76.41 209812[109:Spt:209811.0,209806.0,209808.0] || m_main_v_state(s27,c_busy)* -> . % 76.16/76.41 209813[109:Spt:209811.0,209806.1] || -> m_main_v_state(s28,c_busy)*. % 76.16/76.41 209817[109:Res:209813.0,61.1] always3(s28) || -> . % 76.16/76.41 209818[109:SSi:209817.0,78191.0,78195.0,192127.0] || -> . % 76.16/76.41 209819[107:Spt:209818.0,209328.0,209329.0] || until2p7(s27)*+ -> . % 76.16/76.41 209820[107:Spt:209818.0,209328.1] || -> node4(s26)*. % 76.16/76.41 209822[107:MRR:840.0,209820.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.16/76.41 209825[107:Res:53.1,209822.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.16/76.41 209830[108:Spt:209825.0] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.41 209832[108:Res:209830.0,61.1] always3(s26) || -> . % 76.16/76.41 209833[108:SSi:209832.0,78182.0,78186.0,192125.0,209327.0,209820.0] || -> . % 76.16/76.41 209834[108:Spt:209833.0,209825.0,209830.0] || m_main_v_state(s26,c_busy)* -> . % 76.16/76.41 209835[108:Spt:209833.0,209825.1] || -> m_main_v_state(s27,c_busy)*. % 76.16/76.41 209839[108:Res:209835.0,61.1] always3(s27) || -> . % 76.16/76.41 209840[108:SSi:209839.0,78187.0,78190.0,192126.0] || -> . % 76.16/76.41 209841[106:Spt:209840.0,209326.0,209327.0] || until2p7(s26)*+ -> . % 76.16/76.41 209842[106:Spt:209840.0,209326.1] || -> node4(s25)*. % 76.16/76.41 209844[106:MRR:843.0,209842.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.16/76.41 209847[106:Res:53.1,209844.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.16/76.41 209849[107:Spt:209847.0] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.41 209851[107:Res:209849.0,61.1] always3(s25) || -> . % 76.16/76.41 209852[107:SSi:209851.0,78178.0,78181.0,192124.0,209325.0,209842.0] || -> . % 76.16/76.41 209853[107:Spt:209852.0,209847.0,209849.0] || m_main_v_state(s25,c_busy)* -> . % 76.16/76.41 209854[107:Spt:209852.0,209847.1] || -> m_main_v_state(s26,c_busy)*. % 76.16/76.41 209858[107:Res:209854.0,61.1] always3(s26) || -> . % 76.16/76.41 209859[107:SSi:209858.0,78182.0,78186.0,192125.0] || -> . % 76.16/76.41 209860[105:Spt:209859.0,209324.0,209325.0] || until2p7(s25)*+ -> . % 76.16/76.41 209861[105:Spt:209859.0,209324.1] || -> node4(s24)*. % 76.16/76.41 209863[105:MRR:846.0,209861.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.16/76.41 209866[105:Res:53.1,209863.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.16/76.41 209868[106:Spt:209866.0] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.41 209870[106:Res:209868.0,61.1] always3(s24) || -> . % 76.16/76.41 209871[106:SSi:209870.0,78173.0,78177.0,192123.0,209323.0,209861.0] || -> . % 76.16/76.41 209872[106:Spt:209871.0,209866.0,209868.0] || m_main_v_state(s24,c_busy)* -> . % 76.16/76.41 209873[106:Spt:209871.0,209866.1] || -> m_main_v_state(s25,c_busy)*. % 76.16/76.41 209877[106:Res:209873.0,61.1] always3(s25) || -> . % 76.16/76.41 209878[106:SSi:209877.0,78178.0,78181.0,192124.0] || -> . % 76.16/76.41 209879[104:Spt:209878.0,209322.0,209323.0] || until2p7(s24)*+ -> . % 76.16/76.41 209880[104:Spt:209878.0,209322.1] || -> node4(s23)*. % 76.16/76.41 209882[104:MRR:849.0,209880.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.16/76.41 209885[104:Res:53.1,209882.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.16/76.41 209887[105:Spt:209885.0] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.41 209889[105:Res:209887.0,61.1] always3(s23) || -> . % 76.16/76.41 209890[105:SSi:209889.0,78169.0,78172.0,192122.0,209321.0,209880.0] || -> . % 76.16/76.41 209891[105:Spt:209890.0,209885.0,209887.0] || m_main_v_state(s23,c_busy)* -> . % 76.16/76.41 209892[105:Spt:209890.0,209885.1] || -> m_main_v_state(s24,c_busy)*. % 76.16/76.41 209896[105:Res:209892.0,61.1] always3(s24) || -> . % 76.16/76.41 209897[105:SSi:209896.0,78173.0,78177.0,192123.0] || -> . % 76.16/76.41 209898[103:Spt:209897.0,209320.0,209321.0] || until2p7(s23)*+ -> . % 76.16/76.41 209899[103:Spt:209897.0,209320.1] || -> node4(s22)*. % 76.16/76.41 209901[103:MRR:852.0,209899.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.16/76.41 209904[103:Res:53.1,209901.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.16/76.41 209909[104:Spt:209904.0] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.41 209911[104:Res:209909.0,61.1] always3(s22) || -> . % 76.16/76.41 209912[104:SSi:209911.0,78164.0,78168.0,192121.0,209319.0,209899.0] || -> . % 76.16/76.41 209913[104:Spt:209912.0,209904.0,209909.0] || m_main_v_state(s22,c_busy)* -> . % 76.16/76.41 209914[104:Spt:209912.0,209904.1] || -> m_main_v_state(s23,c_busy)*. % 76.16/76.41 209918[104:Res:209914.0,61.1] always3(s23) || -> . % 76.16/76.41 209919[104:SSi:209918.0,78169.0,78172.0,192122.0] || -> . % 76.16/76.41 209920[102:Spt:209919.0,209318.0,209319.0] || until2p7(s22)*+ -> . % 76.16/76.41 209921[102:Spt:209919.0,209318.1] || -> node4(s21)*. % 76.16/76.41 209923[102:MRR:855.0,209921.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.16/76.41 209926[102:Res:53.1,209923.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.16/76.41 209928[103:Spt:209926.0] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.41 209930[103:Res:209928.0,61.1] always3(s21) || -> . % 76.16/76.41 209931[103:SSi:209930.0,78160.0,78163.0,192120.0,209317.0,209921.0] || -> . % 76.16/76.41 209932[103:Spt:209931.0,209926.0,209928.0] || m_main_v_state(s21,c_busy)* -> . % 76.16/76.41 209933[103:Spt:209931.0,209926.1] || -> m_main_v_state(s22,c_busy)*. % 76.16/76.41 209937[103:Res:209933.0,61.1] always3(s22) || -> . % 76.16/76.41 209938[103:SSi:209937.0,78164.0,78168.0,192121.0] || -> . % 76.16/76.41 209939[101:Spt:209938.0,209316.0,209317.0] || until2p7(s21)*+ -> . % 76.16/76.41 209940[101:Spt:209938.0,209316.1] || -> node4(s20)*. % 76.16/76.41 209942[101:MRR:858.0,209940.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.16/76.41 209945[101:Res:53.1,209942.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.16/76.41 209947[102:Spt:209945.0] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.41 209949[102:Res:209947.0,61.1] always3(s20) || -> . % 76.16/76.41 209950[102:SSi:209949.0,78155.0,78159.0,192119.0,209315.0,209940.0] || -> . % 76.16/76.41 209951[102:Spt:209950.0,209945.0,209947.0] || m_main_v_state(s20,c_busy)* -> . % 76.16/76.41 209952[102:Spt:209950.0,209945.1] || -> m_main_v_state(s21,c_busy)*. % 76.16/76.41 209956[102:Res:209952.0,61.1] always3(s21) || -> . % 76.16/76.41 209957[102:SSi:209956.0,78160.0,78163.0,192120.0] || -> . % 76.16/76.41 209958[100:Spt:209957.0,209314.0,209315.0] || until2p7(s20)*+ -> . % 76.16/76.41 209959[100:Spt:209957.0,209314.1] || -> node4(s19)*. % 76.16/76.41 209961[100:MRR:861.0,209959.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.16/76.41 209964[100:Res:53.1,209961.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.16/76.41 209966[101:Spt:209964.0] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.41 209968[101:Res:209966.0,61.1] always3(s19) || -> . % 76.16/76.41 209969[101:SSi:209968.0,78151.0,78154.0,192118.0,209313.0,209959.0] || -> . % 76.16/76.41 209970[101:Spt:209969.0,209964.0,209966.0] || m_main_v_state(s19,c_busy)* -> . % 76.16/76.41 209971[101:Spt:209969.0,209964.1] || -> m_main_v_state(s20,c_busy)*. % 76.16/76.41 209975[101:Res:209971.0,61.1] always3(s20) || -> . % 76.16/76.41 209976[101:SSi:209975.0,78155.0,78159.0,192119.0] || -> . % 76.16/76.41 209977[99:Spt:209976.0,209312.0,209313.0] || until2p7(s19)*+ -> . % 76.16/76.41 209978[99:Spt:209976.0,209312.1] || -> node4(s18)*. % 76.16/76.41 209980[99:MRR:864.0,209978.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.16/76.41 209983[99:Res:53.1,209980.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.16/76.41 209988[100:Spt:209983.0] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.41 209990[100:Res:209988.0,61.1] always3(s18) || -> . % 76.16/76.41 209991[100:SSi:209990.0,78146.0,78150.0,192117.0,209311.0,209978.0] || -> . % 76.16/76.41 209992[100:Spt:209991.0,209983.0,209988.0] || m_main_v_state(s18,c_busy)* -> . % 76.16/76.41 209993[100:Spt:209991.0,209983.1] || -> m_main_v_state(s19,c_busy)*. % 76.16/76.41 209997[100:Res:209993.0,61.1] always3(s19) || -> . % 76.16/76.41 209998[100:SSi:209997.0,78151.0,78154.0,192118.0] || -> . % 76.16/76.41 209999[98:Spt:209998.0,209310.0,209311.0] || until2p7(s18)*+ -> . % 76.16/76.41 210000[98:Spt:209998.0,209310.1] || -> node4(s17)*. % 76.16/76.41 210002[98:MRR:867.0,210000.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.16/76.41 210005[98:Res:53.1,210002.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.16/76.41 210007[99:Spt:210005.0] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.41 210009[99:Res:210007.0,61.1] always3(s17) || -> . % 76.16/76.41 210010[99:SSi:210009.0,78142.0,78145.0,192116.0,209309.0,210000.0] || -> . % 76.16/76.41 210011[99:Spt:210010.0,210005.0,210007.0] || m_main_v_state(s17,c_busy)* -> . % 76.16/76.41 210012[99:Spt:210010.0,210005.1] || -> m_main_v_state(s18,c_busy)*. % 76.16/76.41 210016[99:Res:210012.0,61.1] always3(s18) || -> . % 76.16/76.41 210017[99:SSi:210016.0,78146.0,78150.0,192117.0] || -> . % 76.16/76.41 210018[97:Spt:210017.0,209308.0,209309.0] || until2p7(s17)*+ -> . % 76.16/76.41 210019[97:Spt:210017.0,209308.1] || -> node4(s16)*. % 76.16/76.41 210021[97:MRR:870.0,210019.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.16/76.41 210024[97:Res:53.1,210021.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.16/76.41 210026[98:Spt:210024.0] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.41 210028[98:Res:210026.0,61.1] always3(s16) || -> . % 76.16/76.41 210029[98:SSi:210028.0,78137.0,78141.0,192115.0,209307.0,210019.0] || -> . % 76.16/76.41 210030[98:Spt:210029.0,210024.0,210026.0] || m_main_v_state(s16,c_busy)* -> . % 76.16/76.41 210031[98:Spt:210029.0,210024.1] || -> m_main_v_state(s17,c_busy)*. % 76.16/76.41 210035[98:Res:210031.0,61.1] always3(s17) || -> . % 76.16/76.41 210036[98:SSi:210035.0,78142.0,78145.0,192116.0] || -> . % 76.16/76.41 210037[96:Spt:210036.0,209306.0,209307.0] || until2p7(s16)*+ -> . % 76.16/76.41 210038[96:Spt:210036.0,209306.1] || -> node4(s15)*. % 76.16/76.41 210040[96:MRR:873.0,210038.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.16/76.41 210043[96:Res:53.1,210040.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.16/76.41 210045[97:Spt:210043.0] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.41 210047[97:Res:210045.0,61.1] always3(s15) || -> . % 76.16/76.41 210048[97:SSi:210047.0,78133.0,78136.0,192114.0,209305.0,210038.0] || -> . % 76.16/76.41 210049[97:Spt:210048.0,210043.0,210045.0] || m_main_v_state(s15,c_busy)* -> . % 76.16/76.41 210050[97:Spt:210048.0,210043.1] || -> m_main_v_state(s16,c_busy)*. % 76.16/76.41 210054[97:Res:210050.0,61.1] always3(s16) || -> . % 76.16/76.41 210055[97:SSi:210054.0,78137.0,78141.0,192115.0] || -> . % 76.16/76.41 210056[95:Spt:210055.0,209304.0,209305.0] || until2p7(s15)*+ -> . % 76.16/76.41 210057[95:Spt:210055.0,209304.1] || -> node4(s14)*. % 76.16/76.41 210059[95:MRR:876.0,210057.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.16/76.41 210062[95:Res:53.1,210059.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.16/76.41 210067[96:Spt:210062.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.41 210069[96:Res:210067.0,61.1] always3(s14) || -> . % 76.16/76.41 210070[96:SSi:210069.0,78128.0,78132.0,192113.0,209303.0,210057.0] || -> . % 76.16/76.41 210071[96:Spt:210070.0,210062.0,210067.0] || m_main_v_state(s14,c_busy)* -> . % 76.16/76.41 210072[96:Spt:210070.0,210062.1] || -> m_main_v_state(s15,c_busy)*. % 76.16/76.41 210076[96:Res:210072.0,61.1] always3(s15) || -> . % 76.16/76.41 210077[96:SSi:210076.0,78133.0,78136.0,192114.0] || -> . % 76.16/76.41 210078[94:Spt:210077.0,209302.0,209303.0] || until2p7(s14)*+ -> . % 76.16/76.41 210079[94:Spt:210077.0,209302.1] || -> node4(s13)*. % 76.16/76.41 210081[94:MRR:879.0,210079.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.16/76.41 210084[94:Res:53.1,210081.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.16/76.41 210086[94:MRR:210084.0,209292.0] || -> m_main_v_state(s14,c_busy)*. % 76.16/76.41 210088[94:Res:210086.0,61.1] always3(s14) || -> . % 76.16/76.41 210089[94:SSi:210088.0,78128.0,78132.0,192113.0] || -> . % 76.16/76.41 210090[92:Spt:210089.0,209156.0,209159.0] || trans(s49,s13)*+ -> . % 76.16/76.41 210091[92:Spt:210089.0,209156.1,209156.2,209156.3,209156.4,209156.5,209156.6,209156.7] || -> trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.16/76.41 210093[92:MRR:209158.1,210090.0] xuntil6(s49) || -> trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.16/76.41 210094[93:Spt:210091.0] || -> trans(s49,s12)*. % 76.16/76.41 210095[93:Res:210094.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s12)*. % 76.16/76.41 210097[93:Res:210094.0,60.0] || -> node2(s49,s12)*. % 76.16/76.41 210098[93:SSi:210095.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s12)*. % 76.16/76.41 210099[93:Res:210097.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)*. % 76.16/76.41 210223[93:SoR:210099.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)*. % 76.16/76.41 210225[93:SoR:210223.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s12,c_busy)* xuntil6(s49). % 76.16/76.41 210226[93:SSi:210225.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s12,c_busy)* xuntil6(s49). % 76.16/76.41 210227[94:Spt:210226.1] || -> m_main_v_state(s12,c_busy)*. % 76.16/76.41 210229[94:Res:210227.0,61.1] always3(s12) || -> . % 76.16/76.41 210230[94:SSi:210229.0,78119.0,78123.0,192111.0] || -> . % 76.16/76.41 210231[94:Spt:210230.0,210226.1,210227.0] || m_main_v_state(s12,c_busy)*+ -> . % 76.16/76.41 210232[94:Spt:210230.0,210226.0,210226.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.16/76.41 210236[94:MRR:210223.2,210231.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.16/76.41 210237[94:Res:53.1,210232.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.16/76.41 210239[94:MRR:210237.0,78381.0] || -> xuntil6(s49)*. % 76.16/76.41 210240[94:MRR:210098.0,210239.0] || -> until2p7(s12)*. % 76.16/76.41 210241[94:MRR:208.0,210240.0] || -> until2p7(s13)* node4(s12). % 76.16/76.41 210242[95:Spt:210241.0] || -> until2p7(s13)*. % 76.16/76.41 210243[95:MRR:209.0,210242.0] || -> until2p7(s14)* node4(s13). % 76.16/76.41 210244[96:Spt:210243.0] || -> until2p7(s14)*. % 76.16/76.41 210245[96:MRR:210.0,210244.0] || -> until2p7(s15)* node4(s14). % 76.16/76.41 210246[97:Spt:210245.0] || -> until2p7(s15)*. % 76.16/76.41 210247[97:MRR:211.0,210246.0] || -> until2p7(s16)* node4(s15). % 76.16/76.41 210248[98:Spt:210247.0] || -> until2p7(s16)*. % 76.16/76.41 210249[98:MRR:212.0,210248.0] || -> until2p7(s17)* node4(s16). % 76.16/76.41 210250[99:Spt:210249.0] || -> until2p7(s17)*. % 76.16/76.41 210251[99:MRR:213.0,210250.0] || -> until2p7(s18)* node4(s17). % 76.16/76.41 210252[100:Spt:210251.0] || -> until2p7(s18)*. % 76.16/76.41 210253[100:MRR:214.0,210252.0] || -> until2p7(s19)* node4(s18). % 76.16/76.41 210254[101:Spt:210253.0] || -> until2p7(s19)*. % 76.16/76.41 210255[101:MRR:215.0,210254.0] || -> until2p7(s20)* node4(s19). % 76.16/76.41 210256[102:Spt:210255.0] || -> until2p7(s20)*. % 76.16/76.41 210257[102:MRR:216.0,210256.0] || -> until2p7(s21)* node4(s20). % 76.16/76.41 210258[103:Spt:210257.0] || -> until2p7(s21)*. % 76.16/76.41 210259[103:MRR:217.0,210258.0] || -> until2p7(s22)* node4(s21). % 76.16/76.41 210260[104:Spt:210259.0] || -> until2p7(s22)*. % 76.16/76.41 210261[104:MRR:218.0,210260.0] || -> until2p7(s23)* node4(s22). % 76.30/76.41 210262[105:Spt:210261.0] || -> until2p7(s23)*. % 76.30/76.41 210263[105:MRR:219.0,210262.0] || -> until2p7(s24)* node4(s23). % 76.30/76.41 210264[106:Spt:210263.0] || -> until2p7(s24)*. % 76.30/76.41 210265[106:MRR:220.0,210264.0] || -> until2p7(s25)* node4(s24). % 76.30/76.41 210266[107:Spt:210265.0] || -> until2p7(s25)*. % 76.30/76.41 210267[107:MRR:221.0,210266.0] || -> until2p7(s26)* node4(s25). % 76.30/76.41 210268[108:Spt:210267.0] || -> until2p7(s26)*. % 76.30/76.41 210269[108:MRR:222.0,210268.0] || -> until2p7(s27)* node4(s26). % 76.30/76.41 210270[109:Spt:210269.0] || -> until2p7(s27)*. % 76.30/76.41 210271[109:MRR:223.0,210270.0] || -> until2p7(s28)* node4(s27). % 76.30/76.41 210272[110:Spt:210271.0] || -> until2p7(s28)*. % 76.30/76.41 210273[110:MRR:224.0,210272.0] || -> until2p7(s29)* node4(s28). % 76.30/76.41 210274[111:Spt:210273.0] || -> until2p7(s29)*. % 76.30/76.41 210275[111:MRR:225.0,210274.0] || -> until2p7(s30)* node4(s29). % 76.30/76.41 210276[112:Spt:210275.0] || -> until2p7(s30)*. % 76.30/76.41 210277[112:MRR:226.0,210276.0] || -> until2p7(s31)* node4(s30). % 76.30/76.41 210278[113:Spt:210277.0] || -> until2p7(s31)*. % 76.30/76.41 210279[113:MRR:227.0,210278.0] || -> until2p7(s32)* node4(s31). % 76.30/76.41 210280[114:Spt:210279.0] || -> until2p7(s32)*. % 76.30/76.41 210281[114:MRR:228.0,210280.0] || -> until2p7(s33)* node4(s32). % 76.30/76.41 210282[115:Spt:210281.0] || -> until2p7(s33)*. % 76.30/76.41 210283[115:MRR:229.0,210282.0] || -> until2p7(s34)* node4(s33). % 76.30/76.41 210284[116:Spt:210283.0] || -> until2p7(s34)*. % 76.30/76.41 210285[116:MRR:230.0,210284.0] || -> until2p7(s35)* node4(s34). % 76.30/76.41 210286[117:Spt:210285.0] || -> until2p7(s35)*. % 76.30/76.41 210287[117:MRR:231.0,210286.0] || -> until2p7(s36)* node4(s35). % 76.30/76.41 210288[118:Spt:210287.0] || -> until2p7(s36)*. % 76.30/76.41 210289[118:MRR:232.0,210288.0] || -> until2p7(s37)* node4(s36). % 76.30/76.41 210290[119:Spt:210289.0] || -> until2p7(s37)*. % 76.30/76.41 210291[119:MRR:235.0,210290.0] || -> until2p7(s38)* node4(s37). % 76.30/76.41 210292[120:Spt:210291.0] || -> until2p7(s38)*. % 76.30/76.41 210293[120:MRR:236.0,210292.0] || -> until2p7(s39)* node4(s38). % 76.30/76.41 210294[121:Spt:210293.0] || -> until2p7(s39)*. % 76.30/76.41 210295[121:MRR:237.0,210294.0] || -> until2p7(s40)* node4(s39). % 76.30/76.41 210296[122:Spt:210295.0] || -> until2p7(s40)*. % 76.30/76.41 210297[122:MRR:238.0,210296.0] || -> until2p7(s41)* node4(s40). % 76.30/76.41 210298[123:Spt:210297.0] || -> until2p7(s41)*. % 76.30/76.41 210299[123:MRR:239.0,210298.0] || -> until2p7(s42)* node4(s41). % 76.30/76.41 210300[124:Spt:210299.0] || -> until2p7(s42)*. % 76.30/76.41 210301[124:MRR:240.0,210300.0] || -> until2p7(s43)* node4(s42). % 76.30/76.41 210302[125:Spt:210301.0] || -> until2p7(s43)*. % 76.30/76.41 210303[125:MRR:241.0,210302.0] || -> until2p7(s44)* node4(s43). % 76.30/76.41 210304[126:Spt:210303.0] || -> until2p7(s44)*. % 76.30/76.41 210305[126:MRR:539.0,210304.0] || -> until2p7(s45)* node4(s44). % 76.30/76.41 210306[127:Spt:210305.0] || -> until2p7(s45)*. % 76.30/76.41 210307[127:MRR:544.0,210306.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 210308[128:Spt:210307.0] || -> until2p7(s46)*. % 76.30/76.41 210309[128:MRR:549.0,210308.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 210310[129:Spt:210309.0] || -> until2p7(s47)*. % 76.30/76.41 210311[129:MRR:554.0,210310.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 210312[130:Spt:210311.0] || -> until2p7(s48)*. % 76.30/76.41 210313[130:MRR:559.0,210312.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 210314[131:Spt:210313.0] || -> until2p7(s49)*. % 76.30/76.41 210315[131:MRR:194.0,210314.0] || -> node4(s49)*. % 76.30/76.41 210316[131:MRR:210236.0,210315.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 210317[131:Res:53.1,210316.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 210319[131:MRR:210317.0,78381.0] || -> . % 76.30/76.41 210320[131:Spt:210319.0,210313.0,210314.0] || until2p7(s49)*+ -> . % 76.30/76.41 210321[131:Spt:210319.0,210313.1] || -> node4(s48)*. % 76.30/76.41 210322[131:MRR:78384.0,210321.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 210325[131:Res:53.1,210322.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 210328[131:Res:210325.0,61.1] always3(s48) || -> . % 76.30/76.41 210329[131:SSi:210328.0,78281.0,78387.0,192147.0,210312.0,210321.0] || -> . % 76.30/76.41 210330[130:Spt:210329.0,210311.0,210312.0] || until2p7(s48)*+ -> . % 76.30/76.41 210331[130:Spt:210329.0,210311.1] || -> node4(s47)*. % 76.30/76.41 210333[130:MRR:777.0,210331.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 210348[130:Res:53.1,210333.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 210353[131:Spt:210348.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 210355[131:Res:210353.0,61.1] always3(s47) || -> . % 76.30/76.41 210356[131:SSi:210355.0,78277.0,78280.0,192146.0,210310.0,210331.0] || -> . % 76.30/76.41 210357[131:Spt:210356.0,210348.0,210353.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 210358[131:Spt:210356.0,210348.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 210362[131:Res:210358.0,61.1] always3(s48) || -> . % 76.30/76.41 210363[131:SSi:210362.0,78281.0,78387.0,192147.0] || -> . % 76.30/76.41 210364[129:Spt:210363.0,210309.0,210310.0] || until2p7(s47)*+ -> . % 76.30/76.41 210365[129:Spt:210363.0,210309.1] || -> node4(s46)*. % 76.30/76.41 210367[129:MRR:780.0,210365.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 210374[129:Res:53.1,210367.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 210376[130:Spt:210374.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 210378[130:Res:210376.0,61.1] always3(s46) || -> . % 76.30/76.41 210379[130:SSi:210378.0,78272.0,78276.0,192145.0,210308.0,210365.0] || -> . % 76.30/76.41 210380[130:Spt:210379.0,210374.0,210376.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 210381[130:Spt:210379.0,210374.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 210385[130:Res:210381.0,61.1] always3(s47) || -> . % 76.30/76.41 210386[130:SSi:210385.0,78277.0,78280.0,192146.0] || -> . % 76.30/76.41 210387[128:Spt:210386.0,210307.0,210308.0] || until2p7(s46)*+ -> . % 76.30/76.41 210388[128:Spt:210386.0,210307.1] || -> node4(s45)*. % 76.30/76.41 210390[128:MRR:783.0,210388.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 210393[128:Res:53.1,210390.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 210398[129:Spt:210393.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 210400[129:Res:210398.0,61.1] always3(s45) || -> . % 76.30/76.41 210401[129:SSi:210400.0,78268.0,78271.0,192144.0,210306.0,210388.0] || -> . % 76.30/76.41 210402[129:Spt:210401.0,210393.0,210398.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.41 210403[129:Spt:210401.0,210393.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 210407[129:Res:210403.0,61.1] always3(s46) || -> . % 76.30/76.41 210408[129:SSi:210407.0,78272.0,78276.0,192145.0] || -> . % 76.30/76.41 210409[127:Spt:210408.0,210305.0,210306.0] || until2p7(s45)*+ -> . % 76.30/76.41 210410[127:Spt:210408.0,210305.1] || -> node4(s44)*. % 76.30/76.41 210412[127:MRR:786.0,210410.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.41 210415[127:Res:53.1,210412.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.41 210417[128:Spt:210415.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 210419[128:Res:210417.0,61.1] always3(s44) || -> . % 76.30/76.41 210420[128:SSi:210419.0,78263.0,78267.0,192143.0,210304.0,210410.0] || -> . % 76.30/76.41 210421[128:Spt:210420.0,210415.0,210417.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.41 210422[128:Spt:210420.0,210415.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 210426[128:Res:210422.0,61.1] always3(s45) || -> . % 76.30/76.41 210427[128:SSi:210426.0,78268.0,78271.0,192144.0] || -> . % 76.30/76.41 210428[126:Spt:210427.0,210303.0,210304.0] || until2p7(s44)*+ -> . % 76.30/76.41 210429[126:Spt:210427.0,210303.1] || -> node4(s43)*. % 76.30/76.41 210431[126:MRR:789.0,210429.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.41 210434[126:Res:53.1,210431.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.41 210436[127:Spt:210434.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 210438[127:Res:210436.0,61.1] always3(s43) || -> . % 76.30/76.41 210439[127:SSi:210438.0,78259.0,78262.0,192142.0,210302.0,210429.0] || -> . % 76.30/76.41 210440[127:Spt:210439.0,210434.0,210436.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.41 210441[127:Spt:210439.0,210434.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 210445[127:Res:210441.0,61.1] always3(s44) || -> . % 76.30/76.41 210446[127:SSi:210445.0,78263.0,78267.0,192143.0] || -> . % 76.30/76.41 210447[125:Spt:210446.0,210301.0,210302.0] || until2p7(s43)*+ -> . % 76.30/76.41 210448[125:Spt:210446.0,210301.1] || -> node4(s42)*. % 76.30/76.41 210450[125:MRR:792.0,210448.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.41 210453[125:Res:53.1,210450.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.41 210455[126:Spt:210453.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 210457[126:Res:210455.0,61.1] always3(s42) || -> . % 76.30/76.41 210458[126:SSi:210457.0,78254.0,78258.0,192141.0,210300.0,210448.0] || -> . % 76.30/76.41 210459[126:Spt:210458.0,210453.0,210455.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.41 210460[126:Spt:210458.0,210453.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 210464[126:Res:210460.0,61.1] always3(s43) || -> . % 76.30/76.41 210465[126:SSi:210464.0,78259.0,78262.0,192142.0] || -> . % 76.30/76.41 210466[124:Spt:210465.0,210299.0,210300.0] || until2p7(s42)*+ -> . % 76.30/76.41 210467[124:Spt:210465.0,210299.1] || -> node4(s41)*. % 76.30/76.41 210469[124:MRR:795.0,210467.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.41 210472[124:Res:53.1,210469.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.41 210477[125:Spt:210472.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 210479[125:Res:210477.0,61.1] always3(s41) || -> . % 76.30/76.41 210480[125:SSi:210479.0,78250.0,78253.0,192140.0,210298.0,210467.0] || -> . % 76.30/76.41 210481[125:Spt:210480.0,210472.0,210477.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.41 210482[125:Spt:210480.0,210472.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 210486[125:Res:210482.0,61.1] always3(s42) || -> . % 76.30/76.41 210487[125:SSi:210486.0,78254.0,78258.0,192141.0] || -> . % 76.30/76.41 210488[123:Spt:210487.0,210297.0,210298.0] || until2p7(s41)*+ -> . % 76.30/76.41 210489[123:Spt:210487.0,210297.1] || -> node4(s40)*. % 76.30/76.41 210491[123:MRR:798.0,210489.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.41 210494[123:Res:53.1,210491.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.41 210496[124:Spt:210494.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 210498[124:Res:210496.0,61.1] always3(s40) || -> . % 76.30/76.41 210499[124:SSi:210498.0,78245.0,78249.0,192139.0,210296.0,210489.0] || -> . % 76.30/76.41 210500[124:Spt:210499.0,210494.0,210496.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.41 210501[124:Spt:210499.0,210494.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 210505[124:Res:210501.0,61.1] always3(s41) || -> . % 76.30/76.41 210506[124:SSi:210505.0,78250.0,78253.0,192140.0] || -> . % 76.30/76.41 210507[122:Spt:210506.0,210295.0,210296.0] || until2p7(s40)*+ -> . % 76.30/76.41 210508[122:Spt:210506.0,210295.1] || -> node4(s39)*. % 76.30/76.41 210510[122:MRR:801.0,210508.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.41 210513[122:Res:53.1,210510.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.41 210515[123:Spt:210513.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 210517[123:Res:210515.0,61.1] always3(s39) || -> . % 76.30/76.41 210518[123:SSi:210517.0,78241.0,78244.0,192138.0,210294.0,210508.0] || -> . % 76.30/76.41 210519[123:Spt:210518.0,210513.0,210515.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.41 210520[123:Spt:210518.0,210513.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 210524[123:Res:210520.0,61.1] always3(s40) || -> . % 76.30/76.41 210525[123:SSi:210524.0,78245.0,78249.0,192139.0] || -> . % 76.30/76.41 210526[121:Spt:210525.0,210293.0,210294.0] || until2p7(s39)*+ -> . % 76.30/76.41 210527[121:Spt:210525.0,210293.1] || -> node4(s38)*. % 76.30/76.41 210529[121:MRR:804.0,210527.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.41 210532[121:Res:53.1,210529.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.41 210534[122:Spt:210532.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 210536[122:Res:210534.0,61.1] always3(s38) || -> . % 76.30/76.41 210537[122:SSi:210536.0,78236.0,78240.0,192137.0,210292.0,210527.0] || -> . % 76.30/76.41 210538[122:Spt:210537.0,210532.0,210534.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.41 210539[122:Spt:210537.0,210532.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 210543[122:Res:210539.0,61.1] always3(s39) || -> . % 76.30/76.41 210544[122:SSi:210543.0,78241.0,78244.0,192138.0] || -> . % 76.30/76.41 210545[120:Spt:210544.0,210291.0,210292.0] || until2p7(s38)*+ -> . % 76.30/76.41 210546[120:Spt:210544.0,210291.1] || -> node4(s37)*. % 76.30/76.41 210548[120:MRR:807.0,210546.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.41 210551[120:Res:53.1,210548.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.41 210556[121:Spt:210551.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 210558[121:Res:210556.0,61.1] always3(s37) || -> . % 76.30/76.41 210559[121:SSi:210558.0,78232.0,78235.0,192136.0,210290.0,210546.0] || -> . % 76.30/76.41 210560[121:Spt:210559.0,210551.0,210556.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.41 210561[121:Spt:210559.0,210551.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 210565[121:Res:210561.0,61.1] always3(s38) || -> . % 76.30/76.41 210566[121:SSi:210565.0,78236.0,78240.0,192137.0] || -> . % 76.30/76.41 210567[119:Spt:210566.0,210289.0,210290.0] || until2p7(s37)*+ -> . % 76.30/76.41 210568[119:Spt:210566.0,210289.1] || -> node4(s36)*. % 76.30/76.41 210570[119:MRR:810.0,210568.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.41 210573[119:Res:53.1,210570.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.41 210575[120:Spt:210573.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 210577[120:Res:210575.0,61.1] always3(s36) || -> . % 76.30/76.41 210578[120:SSi:210577.0,78227.0,78231.0,192135.0,210288.0,210568.0] || -> . % 76.30/76.41 210579[120:Spt:210578.0,210573.0,210575.0] || m_main_v_state(s36,c_busy)* -> . % 76.30/76.41 210580[120:Spt:210578.0,210573.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 210584[120:Res:210580.0,61.1] always3(s37) || -> . % 76.30/76.41 210585[120:SSi:210584.0,78232.0,78235.0,192136.0] || -> . % 76.30/76.41 210586[118:Spt:210585.0,210287.0,210288.0] || until2p7(s36)*+ -> . % 76.30/76.41 210587[118:Spt:210585.0,210287.1] || -> node4(s35)*. % 76.30/76.41 210589[118:MRR:813.0,210587.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.30/76.41 210592[118:Res:53.1,210589.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.30/76.41 210594[119:Spt:210592.0] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 210596[119:Res:210594.0,61.1] always3(s35) || -> . % 76.30/76.41 210597[119:SSi:210596.0,78223.0,78226.0,192134.0,210286.0,210587.0] || -> . % 76.30/76.41 210598[119:Spt:210597.0,210592.0,210594.0] || m_main_v_state(s35,c_busy)* -> . % 76.30/76.41 210599[119:Spt:210597.0,210592.1] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 210603[119:Res:210599.0,61.1] always3(s36) || -> . % 76.30/76.41 210604[119:SSi:210603.0,78227.0,78231.0,192135.0] || -> . % 76.30/76.41 210605[117:Spt:210604.0,210285.0,210286.0] || until2p7(s35)*+ -> . % 76.30/76.41 210606[117:Spt:210604.0,210285.1] || -> node4(s34)*. % 76.30/76.41 210608[117:MRR:816.0,210606.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.30/76.41 210611[117:Res:53.1,210608.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.30/76.41 210613[118:Spt:210611.0] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 210615[118:Res:210613.0,61.1] always3(s34) || -> . % 76.30/76.41 210616[118:SSi:210615.0,78218.0,78222.0,192133.0,210284.0,210606.0] || -> . % 76.30/76.41 210617[118:Spt:210616.0,210611.0,210613.0] || m_main_v_state(s34,c_busy)* -> . % 76.30/76.41 210618[118:Spt:210616.0,210611.1] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 210622[118:Res:210618.0,61.1] always3(s35) || -> . % 76.30/76.41 210623[118:SSi:210622.0,78223.0,78226.0,192134.0] || -> . % 76.30/76.41 210624[116:Spt:210623.0,210283.0,210284.0] || until2p7(s34)*+ -> . % 76.30/76.41 210625[116:Spt:210623.0,210283.1] || -> node4(s33)*. % 76.30/76.41 210627[116:MRR:819.0,210625.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.30/76.41 210630[116:Res:53.1,210627.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.30/76.41 210635[117:Spt:210630.0] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 210637[117:Res:210635.0,61.1] always3(s33) || -> . % 76.30/76.41 210638[117:SSi:210637.0,78214.0,78217.0,192132.0,210282.0,210625.0] || -> . % 76.30/76.41 210639[117:Spt:210638.0,210630.0,210635.0] || m_main_v_state(s33,c_busy)* -> . % 76.30/76.41 210640[117:Spt:210638.0,210630.1] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 210644[117:Res:210640.0,61.1] always3(s34) || -> . % 76.30/76.41 210645[117:SSi:210644.0,78218.0,78222.0,192133.0] || -> . % 76.30/76.41 210646[115:Spt:210645.0,210281.0,210282.0] || until2p7(s33)*+ -> . % 76.30/76.41 210647[115:Spt:210645.0,210281.1] || -> node4(s32)*. % 76.30/76.41 210649[115:MRR:822.0,210647.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.30/76.41 210652[115:Res:53.1,210649.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.30/76.41 210654[116:Spt:210652.0] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 210656[116:Res:210654.0,61.1] always3(s32) || -> . % 76.30/76.41 210657[116:SSi:210656.0,78209.0,78213.0,192131.0,210280.0,210647.0] || -> . % 76.30/76.41 210658[116:Spt:210657.0,210652.0,210654.0] || m_main_v_state(s32,c_busy)* -> . % 76.30/76.41 210659[116:Spt:210657.0,210652.1] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 210663[116:Res:210659.0,61.1] always3(s33) || -> . % 76.30/76.41 210664[116:SSi:210663.0,78214.0,78217.0,192132.0] || -> . % 76.30/76.41 210665[114:Spt:210664.0,210279.0,210280.0] || until2p7(s32)*+ -> . % 76.30/76.41 210666[114:Spt:210664.0,210279.1] || -> node4(s31)*. % 76.30/76.41 210668[114:MRR:825.0,210666.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.30/76.41 210671[114:Res:53.1,210668.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.30/76.41 210673[115:Spt:210671.0] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 210675[115:Res:210673.0,61.1] always3(s31) || -> . % 76.30/76.41 210676[115:SSi:210675.0,78205.0,78208.0,192130.0,210278.0,210666.0] || -> . % 76.30/76.41 210677[115:Spt:210676.0,210671.0,210673.0] || m_main_v_state(s31,c_busy)* -> . % 76.30/76.41 210678[115:Spt:210676.0,210671.1] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 210682[115:Res:210678.0,61.1] always3(s32) || -> . % 76.30/76.41 210683[115:SSi:210682.0,78209.0,78213.0,192131.0] || -> . % 76.30/76.41 210684[113:Spt:210683.0,210277.0,210278.0] || until2p7(s31)*+ -> . % 76.30/76.41 210685[113:Spt:210683.0,210277.1] || -> node4(s30)*. % 76.30/76.41 210687[113:MRR:828.0,210685.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.30/76.41 210690[113:Res:53.1,210687.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.30/76.41 210692[114:Spt:210690.0] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 210694[114:Res:210692.0,61.1] always3(s30) || -> . % 76.30/76.41 210695[114:SSi:210694.0,78200.0,78204.0,192129.0,210276.0,210685.0] || -> . % 76.30/76.41 210696[114:Spt:210695.0,210690.0,210692.0] || m_main_v_state(s30,c_busy)* -> . % 76.30/76.41 210697[114:Spt:210695.0,210690.1] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 210701[114:Res:210697.0,61.1] always3(s31) || -> . % 76.30/76.41 210702[114:SSi:210701.0,78205.0,78208.0,192130.0] || -> . % 76.30/76.41 210703[112:Spt:210702.0,210275.0,210276.0] || until2p7(s30)*+ -> . % 76.30/76.41 210704[112:Spt:210702.0,210275.1] || -> node4(s29)*. % 76.30/76.41 210706[112:MRR:831.0,210704.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.30/76.41 210709[112:Res:53.1,210706.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.30/76.41 210714[113:Spt:210709.0] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 210716[113:Res:210714.0,61.1] always3(s29) || -> . % 76.30/76.41 210717[113:SSi:210716.0,78196.0,78199.0,192128.0,210274.0,210704.0] || -> . % 76.30/76.41 210718[113:Spt:210717.0,210709.0,210714.0] || m_main_v_state(s29,c_busy)* -> . % 76.30/76.41 210719[113:Spt:210717.0,210709.1] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 210723[113:Res:210719.0,61.1] always3(s30) || -> . % 76.30/76.41 210724[113:SSi:210723.0,78200.0,78204.0,192129.0] || -> . % 76.30/76.41 210725[111:Spt:210724.0,210273.0,210274.0] || until2p7(s29)*+ -> . % 76.30/76.41 210726[111:Spt:210724.0,210273.1] || -> node4(s28)*. % 76.30/76.41 210728[111:MRR:834.0,210726.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.30/76.41 210731[111:Res:53.1,210728.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.30/76.41 210733[112:Spt:210731.0] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 210735[112:Res:210733.0,61.1] always3(s28) || -> . % 76.30/76.41 210736[112:SSi:210735.0,78191.0,78195.0,192127.0,210272.0,210726.0] || -> . % 76.30/76.41 210737[112:Spt:210736.0,210731.0,210733.0] || m_main_v_state(s28,c_busy)* -> . % 76.30/76.41 210738[112:Spt:210736.0,210731.1] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 210742[112:Res:210738.0,61.1] always3(s29) || -> . % 76.30/76.41 210743[112:SSi:210742.0,78196.0,78199.0,192128.0] || -> . % 76.30/76.41 210744[110:Spt:210743.0,210271.0,210272.0] || until2p7(s28)*+ -> . % 76.30/76.41 210745[110:Spt:210743.0,210271.1] || -> node4(s27)*. % 76.30/76.41 210747[110:MRR:837.0,210745.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.30/76.41 210750[110:Res:53.1,210747.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.30/76.41 210752[111:Spt:210750.0] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 210754[111:Res:210752.0,61.1] always3(s27) || -> . % 76.30/76.41 210755[111:SSi:210754.0,78187.0,78190.0,192126.0,210270.0,210745.0] || -> . % 76.30/76.41 210756[111:Spt:210755.0,210750.0,210752.0] || m_main_v_state(s27,c_busy)* -> . % 76.30/76.41 210757[111:Spt:210755.0,210750.1] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 210761[111:Res:210757.0,61.1] always3(s28) || -> . % 76.30/76.41 210762[111:SSi:210761.0,78191.0,78195.0,192127.0] || -> . % 76.30/76.41 210763[109:Spt:210762.0,210269.0,210270.0] || until2p7(s27)*+ -> . % 76.30/76.41 210764[109:Spt:210762.0,210269.1] || -> node4(s26)*. % 76.30/76.41 210766[109:MRR:840.0,210764.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.30/76.41 210769[109:Res:53.1,210766.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.30/76.41 210771[110:Spt:210769.0] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 210773[110:Res:210771.0,61.1] always3(s26) || -> . % 76.30/76.41 210774[110:SSi:210773.0,78182.0,78186.0,192125.0,210268.0,210764.0] || -> . % 76.30/76.41 210775[110:Spt:210774.0,210769.0,210771.0] || m_main_v_state(s26,c_busy)* -> . % 76.30/76.41 210776[110:Spt:210774.0,210769.1] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 210780[110:Res:210776.0,61.1] always3(s27) || -> . % 76.30/76.41 210781[110:SSi:210780.0,78187.0,78190.0,192126.0] || -> . % 76.30/76.41 210782[108:Spt:210781.0,210267.0,210268.0] || until2p7(s26)*+ -> . % 76.30/76.41 210783[108:Spt:210781.0,210267.1] || -> node4(s25)*. % 76.30/76.41 210785[108:MRR:843.0,210783.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.30/76.41 210788[108:Res:53.1,210785.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.30/76.41 210793[109:Spt:210788.0] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 210795[109:Res:210793.0,61.1] always3(s25) || -> . % 76.30/76.41 210796[109:SSi:210795.0,78178.0,78181.0,192124.0,210266.0,210783.0] || -> . % 76.30/76.41 210797[109:Spt:210796.0,210788.0,210793.0] || m_main_v_state(s25,c_busy)* -> . % 76.30/76.41 210798[109:Spt:210796.0,210788.1] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 210802[109:Res:210798.0,61.1] always3(s26) || -> . % 76.30/76.41 210803[109:SSi:210802.0,78182.0,78186.0,192125.0] || -> . % 76.30/76.41 210804[107:Spt:210803.0,210265.0,210266.0] || until2p7(s25)*+ -> . % 76.30/76.41 210805[107:Spt:210803.0,210265.1] || -> node4(s24)*. % 76.30/76.41 210807[107:MRR:846.0,210805.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.30/76.41 210810[107:Res:53.1,210807.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.30/76.41 210812[108:Spt:210810.0] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 210814[108:Res:210812.0,61.1] always3(s24) || -> . % 76.30/76.41 210815[108:SSi:210814.0,78173.0,78177.0,192123.0,210264.0,210805.0] || -> . % 76.30/76.41 210816[108:Spt:210815.0,210810.0,210812.0] || m_main_v_state(s24,c_busy)* -> . % 76.30/76.41 210817[108:Spt:210815.0,210810.1] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 210821[108:Res:210817.0,61.1] always3(s25) || -> . % 76.30/76.41 210822[108:SSi:210821.0,78178.0,78181.0,192124.0] || -> . % 76.30/76.41 210823[106:Spt:210822.0,210263.0,210264.0] || until2p7(s24)*+ -> . % 76.30/76.41 210824[106:Spt:210822.0,210263.1] || -> node4(s23)*. % 76.30/76.41 210826[106:MRR:849.0,210824.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.30/76.41 210829[106:Res:53.1,210826.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.30/76.41 210831[107:Spt:210829.0] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 210833[107:Res:210831.0,61.1] always3(s23) || -> . % 76.30/76.41 210834[107:SSi:210833.0,78169.0,78172.0,192122.0,210262.0,210824.0] || -> . % 76.30/76.41 210835[107:Spt:210834.0,210829.0,210831.0] || m_main_v_state(s23,c_busy)* -> . % 76.30/76.41 210836[107:Spt:210834.0,210829.1] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 210840[107:Res:210836.0,61.1] always3(s24) || -> . % 76.30/76.41 210841[107:SSi:210840.0,78173.0,78177.0,192123.0] || -> . % 76.30/76.41 210842[105:Spt:210841.0,210261.0,210262.0] || until2p7(s23)*+ -> . % 76.30/76.41 210843[105:Spt:210841.0,210261.1] || -> node4(s22)*. % 76.30/76.41 210845[105:MRR:852.0,210843.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.30/76.41 210848[105:Res:53.1,210845.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.30/76.41 210850[106:Spt:210848.0] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 210852[106:Res:210850.0,61.1] always3(s22) || -> . % 76.30/76.41 210853[106:SSi:210852.0,78164.0,78168.0,192121.0,210260.0,210843.0] || -> . % 76.30/76.41 210854[106:Spt:210853.0,210848.0,210850.0] || m_main_v_state(s22,c_busy)* -> . % 76.30/76.41 210855[106:Spt:210853.0,210848.1] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 210859[106:Res:210855.0,61.1] always3(s23) || -> . % 76.30/76.41 210860[106:SSi:210859.0,78169.0,78172.0,192122.0] || -> . % 76.30/76.41 210861[104:Spt:210860.0,210259.0,210260.0] || until2p7(s22)*+ -> . % 76.30/76.41 210862[104:Spt:210860.0,210259.1] || -> node4(s21)*. % 76.30/76.41 210864[104:MRR:855.0,210862.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.30/76.41 210867[104:Res:53.1,210864.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.30/76.41 210872[105:Spt:210867.0] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 210874[105:Res:210872.0,61.1] always3(s21) || -> . % 76.30/76.41 210875[105:SSi:210874.0,78160.0,78163.0,192120.0,210258.0,210862.0] || -> . % 76.30/76.41 210876[105:Spt:210875.0,210867.0,210872.0] || m_main_v_state(s21,c_busy)* -> . % 76.30/76.41 210877[105:Spt:210875.0,210867.1] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 210881[105:Res:210877.0,61.1] always3(s22) || -> . % 76.30/76.41 210882[105:SSi:210881.0,78164.0,78168.0,192121.0] || -> . % 76.30/76.41 210883[103:Spt:210882.0,210257.0,210258.0] || until2p7(s21)*+ -> . % 76.30/76.41 210884[103:Spt:210882.0,210257.1] || -> node4(s20)*. % 76.30/76.41 210886[103:MRR:858.0,210884.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.30/76.41 210889[103:Res:53.1,210886.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.30/76.41 210891[104:Spt:210889.0] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 210893[104:Res:210891.0,61.1] always3(s20) || -> . % 76.30/76.41 210894[104:SSi:210893.0,78155.0,78159.0,192119.0,210256.0,210884.0] || -> . % 76.30/76.41 210895[104:Spt:210894.0,210889.0,210891.0] || m_main_v_state(s20,c_busy)* -> . % 76.30/76.41 210896[104:Spt:210894.0,210889.1] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 210900[104:Res:210896.0,61.1] always3(s21) || -> . % 76.30/76.41 210901[104:SSi:210900.0,78160.0,78163.0,192120.0] || -> . % 76.30/76.41 210902[102:Spt:210901.0,210255.0,210256.0] || until2p7(s20)*+ -> . % 76.30/76.41 210903[102:Spt:210901.0,210255.1] || -> node4(s19)*. % 76.30/76.41 210905[102:MRR:861.0,210903.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.30/76.41 210908[102:Res:53.1,210905.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.30/76.41 210910[103:Spt:210908.0] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 210912[103:Res:210910.0,61.1] always3(s19) || -> . % 76.30/76.41 210913[103:SSi:210912.0,78151.0,78154.0,192118.0,210254.0,210903.0] || -> . % 76.30/76.41 210914[103:Spt:210913.0,210908.0,210910.0] || m_main_v_state(s19,c_busy)* -> . % 76.30/76.41 210915[103:Spt:210913.0,210908.1] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 210919[103:Res:210915.0,61.1] always3(s20) || -> . % 76.30/76.41 210920[103:SSi:210919.0,78155.0,78159.0,192119.0] || -> . % 76.30/76.41 210921[101:Spt:210920.0,210253.0,210254.0] || until2p7(s19)*+ -> . % 76.30/76.41 210922[101:Spt:210920.0,210253.1] || -> node4(s18)*. % 76.30/76.41 210924[101:MRR:864.0,210922.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.30/76.41 210927[101:Res:53.1,210924.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.30/76.41 210929[102:Spt:210927.0] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 210931[102:Res:210929.0,61.1] always3(s18) || -> . % 76.30/76.41 210932[102:SSi:210931.0,78146.0,78150.0,192117.0,210252.0,210922.0] || -> . % 76.30/76.41 210933[102:Spt:210932.0,210927.0,210929.0] || m_main_v_state(s18,c_busy)* -> . % 76.30/76.41 210934[102:Spt:210932.0,210927.1] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 210938[102:Res:210934.0,61.1] always3(s19) || -> . % 76.30/76.41 210939[102:SSi:210938.0,78151.0,78154.0,192118.0] || -> . % 76.30/76.41 210940[100:Spt:210939.0,210251.0,210252.0] || until2p7(s18)*+ -> . % 76.30/76.41 210941[100:Spt:210939.0,210251.1] || -> node4(s17)*. % 76.30/76.41 210943[100:MRR:867.0,210941.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.30/76.41 210946[100:Res:53.1,210943.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.30/76.41 210951[101:Spt:210946.0] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 210953[101:Res:210951.0,61.1] always3(s17) || -> . % 76.30/76.41 210954[101:SSi:210953.0,78142.0,78145.0,192116.0,210250.0,210941.0] || -> . % 76.30/76.41 210955[101:Spt:210954.0,210946.0,210951.0] || m_main_v_state(s17,c_busy)* -> . % 76.30/76.41 210956[101:Spt:210954.0,210946.1] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 210960[101:Res:210956.0,61.1] always3(s18) || -> . % 76.30/76.41 210961[101:SSi:210960.0,78146.0,78150.0,192117.0] || -> . % 76.30/76.41 210962[99:Spt:210961.0,210249.0,210250.0] || until2p7(s17)*+ -> . % 76.30/76.41 210963[99:Spt:210961.0,210249.1] || -> node4(s16)*. % 76.30/76.41 210965[99:MRR:870.0,210963.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.30/76.41 210968[99:Res:53.1,210965.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.30/76.41 210970[100:Spt:210968.0] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 210972[100:Res:210970.0,61.1] always3(s16) || -> . % 76.30/76.41 210973[100:SSi:210972.0,78137.0,78141.0,192115.0,210248.0,210963.0] || -> . % 76.30/76.41 210974[100:Spt:210973.0,210968.0,210970.0] || m_main_v_state(s16,c_busy)* -> . % 76.30/76.41 210975[100:Spt:210973.0,210968.1] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 210979[100:Res:210975.0,61.1] always3(s17) || -> . % 76.30/76.41 210980[100:SSi:210979.0,78142.0,78145.0,192116.0] || -> . % 76.30/76.41 210981[98:Spt:210980.0,210247.0,210248.0] || until2p7(s16)*+ -> . % 76.30/76.41 210982[98:Spt:210980.0,210247.1] || -> node4(s15)*. % 76.30/76.41 210984[98:MRR:873.0,210982.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.30/76.41 210987[98:Res:53.1,210984.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.30/76.41 210989[99:Spt:210987.0] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 210991[99:Res:210989.0,61.1] always3(s15) || -> . % 76.30/76.41 210992[99:SSi:210991.0,78133.0,78136.0,192114.0,210246.0,210982.0] || -> . % 76.30/76.41 210993[99:Spt:210992.0,210987.0,210989.0] || m_main_v_state(s15,c_busy)* -> . % 76.30/76.41 210994[99:Spt:210992.0,210987.1] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 210998[99:Res:210994.0,61.1] always3(s16) || -> . % 76.30/76.41 210999[99:SSi:210998.0,78137.0,78141.0,192115.0] || -> . % 76.30/76.41 211000[97:Spt:210999.0,210245.0,210246.0] || until2p7(s15)*+ -> . % 76.30/76.41 211001[97:Spt:210999.0,210245.1] || -> node4(s14)*. % 76.30/76.41 211003[97:MRR:876.0,211001.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.30/76.41 211006[97:Res:53.1,211003.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.30/76.41 211008[98:Spt:211006.0] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 211010[98:Res:211008.0,61.1] always3(s14) || -> . % 76.30/76.41 211011[98:SSi:211010.0,78128.0,78132.0,192113.0,210244.0,211001.0] || -> . % 76.30/76.41 211012[98:Spt:211011.0,211006.0,211008.0] || m_main_v_state(s14,c_busy)* -> . % 76.30/76.41 211013[98:Spt:211011.0,211006.1] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 211017[98:Res:211013.0,61.1] always3(s15) || -> . % 76.30/76.41 211018[98:SSi:211017.0,78133.0,78136.0,192114.0] || -> . % 76.30/76.41 211019[96:Spt:211018.0,210243.0,210244.0] || until2p7(s14)*+ -> . % 76.30/76.41 211020[96:Spt:211018.0,210243.1] || -> node4(s13)*. % 76.30/76.41 211022[96:MRR:879.0,211020.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.30/76.41 211025[96:Res:53.1,211022.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.30/76.41 211030[97:Spt:211025.0] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 211032[97:Res:211030.0,61.1] always3(s13) || -> . % 76.30/76.41 211033[97:SSi:211032.0,78124.0,78127.0,192112.0,210242.0,211020.0] || -> . % 76.30/76.41 211034[97:Spt:211033.0,211025.0,211030.0] || m_main_v_state(s13,c_busy)* -> . % 76.30/76.41 211035[97:Spt:211033.0,211025.1] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 211039[97:Res:211035.0,61.1] always3(s14) || -> . % 76.30/76.41 211040[97:SSi:211039.0,78128.0,78132.0,192113.0] || -> . % 76.30/76.41 211041[95:Spt:211040.0,210241.0,210242.0] || until2p7(s13)*+ -> . % 76.30/76.41 211042[95:Spt:211040.0,210241.1] || -> node4(s12)*. % 76.30/76.41 211044[95:MRR:882.0,211042.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.30/76.41 211047[95:Res:53.1,211044.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.30/76.41 211049[95:MRR:211047.0,210231.0] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 211051[95:Res:211049.0,61.1] always3(s13) || -> . % 76.30/76.41 211052[95:SSi:211051.0,78124.0,78127.0,192112.0] || -> . % 76.30/76.41 211053[93:Spt:211052.0,210091.0,210094.0] || trans(s49,s12)*+ -> . % 76.30/76.41 211054[93:Spt:211052.0,210091.1,210091.2,210091.3,210091.4,210091.5,210091.6] || -> trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.30/76.41 211056[93:MRR:210093.1,211053.0] xuntil6(s49) || -> trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.30/76.41 211057[94:Spt:211054.0] || -> trans(s49,s11)*. % 76.30/76.41 211058[94:Res:211057.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s11)*. % 76.30/76.41 211060[94:Res:211057.0,60.0] || -> node2(s49,s11)*. % 76.30/76.41 211061[94:SSi:211058.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s11)*. % 76.30/76.41 211062[94:Res:211060.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)*. % 76.30/76.41 211187[94:SoR:211062.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)*. % 76.30/76.41 211189[94:SoR:211187.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s11,c_busy)* xuntil6(s49). % 76.30/76.41 211190[94:SSi:211189.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s11,c_busy)* xuntil6(s49). % 76.30/76.41 211191[95:Spt:211190.1] || -> m_main_v_state(s11,c_busy)*. % 76.30/76.41 211193[95:Res:211191.0,61.1] always3(s11) || -> . % 76.30/76.41 211194[95:SSi:211193.0,78115.0,78118.0,192110.0] || -> . % 76.30/76.41 211195[95:Spt:211194.0,211190.1,211191.0] || m_main_v_state(s11,c_busy)*+ -> . % 76.30/76.41 211196[95:Spt:211194.0,211190.0,211190.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 211200[95:MRR:211187.2,211195.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 211201[95:Res:53.1,211196.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 211203[95:MRR:211201.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 211204[95:MRR:211061.0,211203.0] || -> until2p7(s11)*. % 76.30/76.41 211205[95:MRR:207.0,211204.0] || -> until2p7(s12)* node4(s11). % 76.30/76.41 211206[96:Spt:211205.0] || -> until2p7(s12)*. % 76.30/76.41 211207[96:MRR:208.0,211206.0] || -> until2p7(s13)* node4(s12). % 76.30/76.41 211208[97:Spt:211207.0] || -> until2p7(s13)*. % 76.30/76.41 211209[97:MRR:209.0,211208.0] || -> until2p7(s14)* node4(s13). % 76.30/76.41 211210[98:Spt:211209.0] || -> until2p7(s14)*. % 76.30/76.41 211211[98:MRR:210.0,211210.0] || -> until2p7(s15)* node4(s14). % 76.30/76.41 211212[99:Spt:211211.0] || -> until2p7(s15)*. % 76.30/76.41 211213[99:MRR:211.0,211212.0] || -> until2p7(s16)* node4(s15). % 76.30/76.41 211214[100:Spt:211213.0] || -> until2p7(s16)*. % 76.30/76.41 211215[100:MRR:212.0,211214.0] || -> until2p7(s17)* node4(s16). % 76.30/76.41 211216[101:Spt:211215.0] || -> until2p7(s17)*. % 76.30/76.41 211217[101:MRR:213.0,211216.0] || -> until2p7(s18)* node4(s17). % 76.30/76.41 211218[102:Spt:211217.0] || -> until2p7(s18)*. % 76.30/76.41 211219[102:MRR:214.0,211218.0] || -> until2p7(s19)* node4(s18). % 76.30/76.41 211220[103:Spt:211219.0] || -> until2p7(s19)*. % 76.30/76.41 211221[103:MRR:215.0,211220.0] || -> until2p7(s20)* node4(s19). % 76.30/76.41 211222[104:Spt:211221.0] || -> until2p7(s20)*. % 76.30/76.41 211223[104:MRR:216.0,211222.0] || -> until2p7(s21)* node4(s20). % 76.30/76.41 211224[105:Spt:211223.0] || -> until2p7(s21)*. % 76.30/76.41 211225[105:MRR:217.0,211224.0] || -> until2p7(s22)* node4(s21). % 76.30/76.41 211226[106:Spt:211225.0] || -> until2p7(s22)*. % 76.30/76.41 211227[106:MRR:218.0,211226.0] || -> until2p7(s23)* node4(s22). % 76.30/76.41 211228[107:Spt:211227.0] || -> until2p7(s23)*. % 76.30/76.41 211229[107:MRR:219.0,211228.0] || -> until2p7(s24)* node4(s23). % 76.30/76.41 211230[108:Spt:211229.0] || -> until2p7(s24)*. % 76.30/76.41 211231[108:MRR:220.0,211230.0] || -> until2p7(s25)* node4(s24). % 76.30/76.41 211232[109:Spt:211231.0] || -> until2p7(s25)*. % 76.30/76.41 211233[109:MRR:221.0,211232.0] || -> until2p7(s26)* node4(s25). % 76.30/76.41 211234[110:Spt:211233.0] || -> until2p7(s26)*. % 76.30/76.41 211235[110:MRR:222.0,211234.0] || -> until2p7(s27)* node4(s26). % 76.30/76.41 211236[111:Spt:211235.0] || -> until2p7(s27)*. % 76.30/76.41 211237[111:MRR:223.0,211236.0] || -> until2p7(s28)* node4(s27). % 76.30/76.41 211238[112:Spt:211237.0] || -> until2p7(s28)*. % 76.30/76.41 211239[112:MRR:224.0,211238.0] || -> until2p7(s29)* node4(s28). % 76.30/76.41 211240[113:Spt:211239.0] || -> until2p7(s29)*. % 76.30/76.41 211241[113:MRR:225.0,211240.0] || -> until2p7(s30)* node4(s29). % 76.30/76.41 211242[114:Spt:211241.0] || -> until2p7(s30)*. % 76.30/76.41 211243[114:MRR:226.0,211242.0] || -> until2p7(s31)* node4(s30). % 76.30/76.41 211244[115:Spt:211243.0] || -> until2p7(s31)*. % 76.30/76.41 211245[115:MRR:227.0,211244.0] || -> until2p7(s32)* node4(s31). % 76.30/76.41 211246[116:Spt:211245.0] || -> until2p7(s32)*. % 76.30/76.41 211247[116:MRR:228.0,211246.0] || -> until2p7(s33)* node4(s32). % 76.30/76.41 211248[117:Spt:211247.0] || -> until2p7(s33)*. % 76.30/76.41 211249[117:MRR:229.0,211248.0] || -> until2p7(s34)* node4(s33). % 76.30/76.41 211250[118:Spt:211249.0] || -> until2p7(s34)*. % 76.30/76.41 211251[118:MRR:230.0,211250.0] || -> until2p7(s35)* node4(s34). % 76.30/76.41 211252[119:Spt:211251.0] || -> until2p7(s35)*. % 76.30/76.41 211253[119:MRR:231.0,211252.0] || -> until2p7(s36)* node4(s35). % 76.30/76.41 211254[120:Spt:211253.0] || -> until2p7(s36)*. % 76.30/76.41 211255[120:MRR:232.0,211254.0] || -> until2p7(s37)* node4(s36). % 76.30/76.41 211256[121:Spt:211255.0] || -> until2p7(s37)*. % 76.30/76.41 211257[121:MRR:235.0,211256.0] || -> until2p7(s38)* node4(s37). % 76.30/76.41 211258[122:Spt:211257.0] || -> until2p7(s38)*. % 76.30/76.41 211259[122:MRR:236.0,211258.0] || -> until2p7(s39)* node4(s38). % 76.30/76.41 211260[123:Spt:211259.0] || -> until2p7(s39)*. % 76.30/76.41 211261[123:MRR:237.0,211260.0] || -> until2p7(s40)* node4(s39). % 76.30/76.41 211262[124:Spt:211261.0] || -> until2p7(s40)*. % 76.30/76.41 211263[124:MRR:238.0,211262.0] || -> until2p7(s41)* node4(s40). % 76.30/76.41 211264[125:Spt:211263.0] || -> until2p7(s41)*. % 76.30/76.41 211265[125:MRR:239.0,211264.0] || -> until2p7(s42)* node4(s41). % 76.30/76.41 211266[126:Spt:211265.0] || -> until2p7(s42)*. % 76.30/76.41 211267[126:MRR:240.0,211266.0] || -> until2p7(s43)* node4(s42). % 76.30/76.41 211268[127:Spt:211267.0] || -> until2p7(s43)*. % 76.30/76.41 211269[127:MRR:241.0,211268.0] || -> until2p7(s44)* node4(s43). % 76.30/76.41 211270[128:Spt:211269.0] || -> until2p7(s44)*. % 76.30/76.41 211271[128:MRR:539.0,211270.0] || -> until2p7(s45)* node4(s44). % 76.30/76.41 211272[129:Spt:211271.0] || -> until2p7(s45)*. % 76.30/76.41 211273[129:MRR:544.0,211272.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 211274[130:Spt:211273.0] || -> until2p7(s46)*. % 76.30/76.41 211275[130:MRR:549.0,211274.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 211276[131:Spt:211275.0] || -> until2p7(s47)*. % 76.30/76.41 211277[131:MRR:554.0,211276.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 211278[132:Spt:211277.0] || -> until2p7(s48)*. % 76.30/76.41 211279[132:MRR:559.0,211278.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 211280[133:Spt:211279.0] || -> until2p7(s49)*. % 76.30/76.41 211281[133:MRR:194.0,211280.0] || -> node4(s49)*. % 76.30/76.41 211282[133:MRR:211200.0,211281.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 211286[133:Res:53.1,211282.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 211288[133:MRR:211286.0,78381.0] || -> . % 76.30/76.41 211289[133:Spt:211288.0,211279.0,211280.0] || until2p7(s49)*+ -> . % 76.30/76.41 211290[133:Spt:211288.0,211279.1] || -> node4(s48)*. % 76.30/76.41 211291[133:MRR:78384.0,211290.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 211294[133:Res:53.1,211291.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 211297[133:Res:211294.0,61.1] always3(s48) || -> . % 76.30/76.41 211298[133:SSi:211297.0,78281.0,78387.0,192147.0,211278.0,211290.0] || -> . % 76.30/76.41 211299[132:Spt:211298.0,211277.0,211278.0] || until2p7(s48)*+ -> . % 76.30/76.41 211300[132:Spt:211298.0,211277.1] || -> node4(s47)*. % 76.30/76.41 211302[132:MRR:777.0,211300.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 211314[132:Res:53.1,211302.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 211316[133:Spt:211314.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 211318[133:Res:211316.0,61.1] always3(s47) || -> . % 76.30/76.41 211319[133:SSi:211318.0,78277.0,78280.0,192146.0,211276.0,211300.0] || -> . % 76.30/76.41 211320[133:Spt:211319.0,211314.0,211316.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 211321[133:Spt:211319.0,211314.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 211325[133:Res:211321.0,61.1] always3(s48) || -> . % 76.30/76.41 211326[133:SSi:211325.0,78281.0,78387.0,192147.0] || -> . % 76.30/76.41 211327[131:Spt:211326.0,211275.0,211276.0] || until2p7(s47)*+ -> . % 76.30/76.41 211328[131:Spt:211326.0,211275.1] || -> node4(s46)*. % 76.30/76.41 211330[131:MRR:780.0,211328.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 211337[131:Res:53.1,211330.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 211342[132:Spt:211337.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 211344[132:Res:211342.0,61.1] always3(s46) || -> . % 76.30/76.41 211345[132:SSi:211344.0,78272.0,78276.0,192145.0,211274.0,211328.0] || -> . % 76.30/76.41 211346[132:Spt:211345.0,211337.0,211342.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 211347[132:Spt:211345.0,211337.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 211351[132:Res:211347.0,61.1] always3(s47) || -> . % 76.30/76.41 211352[132:SSi:211351.0,78277.0,78280.0,192146.0] || -> . % 76.30/76.41 211353[130:Spt:211352.0,211273.0,211274.0] || until2p7(s46)*+ -> . % 76.30/76.41 211354[130:Spt:211352.0,211273.1] || -> node4(s45)*. % 76.30/76.41 211356[130:MRR:783.0,211354.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 211359[130:Res:53.1,211356.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 211361[131:Spt:211359.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 211363[131:Res:211361.0,61.1] always3(s45) || -> . % 76.30/76.41 211364[131:SSi:211363.0,78268.0,78271.0,192144.0,211272.0,211354.0] || -> . % 76.30/76.41 211365[131:Spt:211364.0,211359.0,211361.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.41 211366[131:Spt:211364.0,211359.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 211370[131:Res:211366.0,61.1] always3(s46) || -> . % 76.30/76.41 211371[131:SSi:211370.0,78272.0,78276.0,192145.0] || -> . % 76.30/76.41 211372[129:Spt:211371.0,211271.0,211272.0] || until2p7(s45)*+ -> . % 76.30/76.41 211373[129:Spt:211371.0,211271.1] || -> node4(s44)*. % 76.30/76.41 211375[129:MRR:786.0,211373.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.41 211378[129:Res:53.1,211375.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.41 211380[130:Spt:211378.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 211382[130:Res:211380.0,61.1] always3(s44) || -> . % 76.30/76.41 211383[130:SSi:211382.0,78263.0,78267.0,192143.0,211270.0,211373.0] || -> . % 76.30/76.41 211384[130:Spt:211383.0,211378.0,211380.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.41 211385[130:Spt:211383.0,211378.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 211389[130:Res:211385.0,61.1] always3(s45) || -> . % 76.30/76.41 211390[130:SSi:211389.0,78268.0,78271.0,192144.0] || -> . % 76.30/76.41 211391[128:Spt:211390.0,211269.0,211270.0] || until2p7(s44)*+ -> . % 76.30/76.41 211392[128:Spt:211390.0,211269.1] || -> node4(s43)*. % 76.30/76.41 211394[128:MRR:789.0,211392.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.41 211397[128:Res:53.1,211394.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.41 211399[129:Spt:211397.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 211401[129:Res:211399.0,61.1] always3(s43) || -> . % 76.30/76.41 211402[129:SSi:211401.0,78259.0,78262.0,192142.0,211268.0,211392.0] || -> . % 76.30/76.41 211403[129:Spt:211402.0,211397.0,211399.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.41 211404[129:Spt:211402.0,211397.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 211408[129:Res:211404.0,61.1] always3(s44) || -> . % 76.30/76.41 211409[129:SSi:211408.0,78263.0,78267.0,192143.0] || -> . % 76.30/76.41 211410[127:Spt:211409.0,211267.0,211268.0] || until2p7(s43)*+ -> . % 76.30/76.41 211411[127:Spt:211409.0,211267.1] || -> node4(s42)*. % 76.30/76.41 211413[127:MRR:792.0,211411.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.41 211416[127:Res:53.1,211413.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.41 211421[128:Spt:211416.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 211423[128:Res:211421.0,61.1] always3(s42) || -> . % 76.30/76.41 211424[128:SSi:211423.0,78254.0,78258.0,192141.0,211266.0,211411.0] || -> . % 76.30/76.41 211425[128:Spt:211424.0,211416.0,211421.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.41 211426[128:Spt:211424.0,211416.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 211430[128:Res:211426.0,61.1] always3(s43) || -> . % 76.30/76.41 211431[128:SSi:211430.0,78259.0,78262.0,192142.0] || -> . % 76.30/76.41 211432[126:Spt:211431.0,211265.0,211266.0] || until2p7(s42)*+ -> . % 76.30/76.41 211433[126:Spt:211431.0,211265.1] || -> node4(s41)*. % 76.30/76.41 211435[126:MRR:795.0,211433.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.41 211438[126:Res:53.1,211435.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.41 211440[127:Spt:211438.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 211442[127:Res:211440.0,61.1] always3(s41) || -> . % 76.30/76.41 211443[127:SSi:211442.0,78250.0,78253.0,192140.0,211264.0,211433.0] || -> . % 76.30/76.41 211444[127:Spt:211443.0,211438.0,211440.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.41 211445[127:Spt:211443.0,211438.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 211449[127:Res:211445.0,61.1] always3(s42) || -> . % 76.30/76.41 211450[127:SSi:211449.0,78254.0,78258.0,192141.0] || -> . % 76.30/76.41 211451[125:Spt:211450.0,211263.0,211264.0] || until2p7(s41)*+ -> . % 76.30/76.41 211452[125:Spt:211450.0,211263.1] || -> node4(s40)*. % 76.30/76.41 211454[125:MRR:798.0,211452.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.41 211457[125:Res:53.1,211454.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.41 211459[126:Spt:211457.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 211461[126:Res:211459.0,61.1] always3(s40) || -> . % 76.30/76.41 211462[126:SSi:211461.0,78245.0,78249.0,192139.0,211262.0,211452.0] || -> . % 76.30/76.41 211463[126:Spt:211462.0,211457.0,211459.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.41 211464[126:Spt:211462.0,211457.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 211468[126:Res:211464.0,61.1] always3(s41) || -> . % 76.30/76.41 211469[126:SSi:211468.0,78250.0,78253.0,192140.0] || -> . % 76.30/76.41 211470[124:Spt:211469.0,211261.0,211262.0] || until2p7(s40)*+ -> . % 76.30/76.41 211471[124:Spt:211469.0,211261.1] || -> node4(s39)*. % 76.30/76.41 211473[124:MRR:801.0,211471.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.41 211476[124:Res:53.1,211473.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.41 211478[125:Spt:211476.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 211480[125:Res:211478.0,61.1] always3(s39) || -> . % 76.30/76.41 211481[125:SSi:211480.0,78241.0,78244.0,192138.0,211260.0,211471.0] || -> . % 76.30/76.41 211482[125:Spt:211481.0,211476.0,211478.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.41 211483[125:Spt:211481.0,211476.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 211487[125:Res:211483.0,61.1] always3(s40) || -> . % 76.30/76.41 211488[125:SSi:211487.0,78245.0,78249.0,192139.0] || -> . % 76.30/76.41 211489[123:Spt:211488.0,211259.0,211260.0] || until2p7(s39)*+ -> . % 76.30/76.41 211490[123:Spt:211488.0,211259.1] || -> node4(s38)*. % 76.30/76.41 211492[123:MRR:804.0,211490.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.41 211495[123:Res:53.1,211492.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.41 211500[124:Spt:211495.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 211502[124:Res:211500.0,61.1] always3(s38) || -> . % 76.30/76.41 211503[124:SSi:211502.0,78236.0,78240.0,192137.0,211258.0,211490.0] || -> . % 76.30/76.41 211504[124:Spt:211503.0,211495.0,211500.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.41 211505[124:Spt:211503.0,211495.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 211509[124:Res:211505.0,61.1] always3(s39) || -> . % 76.30/76.41 211510[124:SSi:211509.0,78241.0,78244.0,192138.0] || -> . % 76.30/76.41 211511[122:Spt:211510.0,211257.0,211258.0] || until2p7(s38)*+ -> . % 76.30/76.41 211512[122:Spt:211510.0,211257.1] || -> node4(s37)*. % 76.30/76.41 211514[122:MRR:807.0,211512.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.41 211517[122:Res:53.1,211514.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.41 211519[123:Spt:211517.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 211521[123:Res:211519.0,61.1] always3(s37) || -> . % 76.30/76.41 211522[123:SSi:211521.0,78232.0,78235.0,192136.0,211256.0,211512.0] || -> . % 76.30/76.41 211523[123:Spt:211522.0,211517.0,211519.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.41 211524[123:Spt:211522.0,211517.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 211528[123:Res:211524.0,61.1] always3(s38) || -> . % 76.30/76.41 211529[123:SSi:211528.0,78236.0,78240.0,192137.0] || -> . % 76.30/76.41 211530[121:Spt:211529.0,211255.0,211256.0] || until2p7(s37)*+ -> . % 76.30/76.41 211531[121:Spt:211529.0,211255.1] || -> node4(s36)*. % 76.30/76.41 211533[121:MRR:810.0,211531.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.41 211536[121:Res:53.1,211533.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.41 211538[122:Spt:211536.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 211540[122:Res:211538.0,61.1] always3(s36) || -> . % 76.30/76.41 211541[122:SSi:211540.0,78227.0,78231.0,192135.0,211254.0,211531.0] || -> . % 76.30/76.41 211542[122:Spt:211541.0,211536.0,211538.0] || m_main_v_state(s36,c_busy)* -> . % 76.30/76.41 211543[122:Spt:211541.0,211536.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 211547[122:Res:211543.0,61.1] always3(s37) || -> . % 76.30/76.41 211548[122:SSi:211547.0,78232.0,78235.0,192136.0] || -> . % 76.30/76.41 211549[120:Spt:211548.0,211253.0,211254.0] || until2p7(s36)*+ -> . % 76.30/76.41 211550[120:Spt:211548.0,211253.1] || -> node4(s35)*. % 76.30/76.41 211552[120:MRR:813.0,211550.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.30/76.41 211555[120:Res:53.1,211552.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.30/76.41 211557[121:Spt:211555.0] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 211559[121:Res:211557.0,61.1] always3(s35) || -> . % 76.30/76.41 211560[121:SSi:211559.0,78223.0,78226.0,192134.0,211252.0,211550.0] || -> . % 76.30/76.41 211561[121:Spt:211560.0,211555.0,211557.0] || m_main_v_state(s35,c_busy)* -> . % 76.30/76.41 211562[121:Spt:211560.0,211555.1] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 211566[121:Res:211562.0,61.1] always3(s36) || -> . % 76.30/76.41 211567[121:SSi:211566.0,78227.0,78231.0,192135.0] || -> . % 76.30/76.41 211568[119:Spt:211567.0,211251.0,211252.0] || until2p7(s35)*+ -> . % 76.30/76.41 211569[119:Spt:211567.0,211251.1] || -> node4(s34)*. % 76.30/76.41 211571[119:MRR:816.0,211569.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.30/76.41 211574[119:Res:53.1,211571.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.30/76.41 211579[120:Spt:211574.0] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 211581[120:Res:211579.0,61.1] always3(s34) || -> . % 76.30/76.41 211582[120:SSi:211581.0,78218.0,78222.0,192133.0,211250.0,211569.0] || -> . % 76.30/76.41 211583[120:Spt:211582.0,211574.0,211579.0] || m_main_v_state(s34,c_busy)* -> . % 76.30/76.41 211584[120:Spt:211582.0,211574.1] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 211588[120:Res:211584.0,61.1] always3(s35) || -> . % 76.30/76.41 211589[120:SSi:211588.0,78223.0,78226.0,192134.0] || -> . % 76.30/76.41 211590[118:Spt:211589.0,211249.0,211250.0] || until2p7(s34)*+ -> . % 76.30/76.41 211591[118:Spt:211589.0,211249.1] || -> node4(s33)*. % 76.30/76.41 211593[118:MRR:819.0,211591.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.30/76.41 211596[118:Res:53.1,211593.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.30/76.41 211598[119:Spt:211596.0] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 211600[119:Res:211598.0,61.1] always3(s33) || -> . % 76.30/76.41 211601[119:SSi:211600.0,78214.0,78217.0,192132.0,211248.0,211591.0] || -> . % 76.30/76.41 211602[119:Spt:211601.0,211596.0,211598.0] || m_main_v_state(s33,c_busy)* -> . % 76.30/76.41 211603[119:Spt:211601.0,211596.1] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 211607[119:Res:211603.0,61.1] always3(s34) || -> . % 76.30/76.41 211608[119:SSi:211607.0,78218.0,78222.0,192133.0] || -> . % 76.30/76.41 211609[117:Spt:211608.0,211247.0,211248.0] || until2p7(s33)*+ -> . % 76.30/76.41 211610[117:Spt:211608.0,211247.1] || -> node4(s32)*. % 76.30/76.41 211612[117:MRR:822.0,211610.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.30/76.41 211615[117:Res:53.1,211612.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.30/76.41 211617[118:Spt:211615.0] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 211619[118:Res:211617.0,61.1] always3(s32) || -> . % 76.30/76.41 211620[118:SSi:211619.0,78209.0,78213.0,192131.0,211246.0,211610.0] || -> . % 76.30/76.41 211621[118:Spt:211620.0,211615.0,211617.0] || m_main_v_state(s32,c_busy)* -> . % 76.30/76.41 211622[118:Spt:211620.0,211615.1] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 211626[118:Res:211622.0,61.1] always3(s33) || -> . % 76.30/76.41 211627[118:SSi:211626.0,78214.0,78217.0,192132.0] || -> . % 76.30/76.41 211628[116:Spt:211627.0,211245.0,211246.0] || until2p7(s32)*+ -> . % 76.30/76.41 211629[116:Spt:211627.0,211245.1] || -> node4(s31)*. % 76.30/76.41 211631[116:MRR:825.0,211629.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.30/76.41 211634[116:Res:53.1,211631.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.30/76.41 211636[117:Spt:211634.0] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 211638[117:Res:211636.0,61.1] always3(s31) || -> . % 76.30/76.41 211639[117:SSi:211638.0,78205.0,78208.0,192130.0,211244.0,211629.0] || -> . % 76.30/76.41 211640[117:Spt:211639.0,211634.0,211636.0] || m_main_v_state(s31,c_busy)* -> . % 76.30/76.41 211641[117:Spt:211639.0,211634.1] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 211645[117:Res:211641.0,61.1] always3(s32) || -> . % 76.30/76.41 211646[117:SSi:211645.0,78209.0,78213.0,192131.0] || -> . % 76.30/76.41 211647[115:Spt:211646.0,211243.0,211244.0] || until2p7(s31)*+ -> . % 76.30/76.41 211648[115:Spt:211646.0,211243.1] || -> node4(s30)*. % 76.30/76.41 211650[115:MRR:828.0,211648.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.30/76.41 211653[115:Res:53.1,211650.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.30/76.41 211658[116:Spt:211653.0] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 211660[116:Res:211658.0,61.1] always3(s30) || -> . % 76.30/76.41 211661[116:SSi:211660.0,78200.0,78204.0,192129.0,211242.0,211648.0] || -> . % 76.30/76.41 211662[116:Spt:211661.0,211653.0,211658.0] || m_main_v_state(s30,c_busy)* -> . % 76.30/76.41 211663[116:Spt:211661.0,211653.1] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 211667[116:Res:211663.0,61.1] always3(s31) || -> . % 76.30/76.41 211668[116:SSi:211667.0,78205.0,78208.0,192130.0] || -> . % 76.30/76.41 211669[114:Spt:211668.0,211241.0,211242.0] || until2p7(s30)*+ -> . % 76.30/76.41 211670[114:Spt:211668.0,211241.1] || -> node4(s29)*. % 76.30/76.41 211672[114:MRR:831.0,211670.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.30/76.41 211675[114:Res:53.1,211672.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.30/76.41 211677[115:Spt:211675.0] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 211679[115:Res:211677.0,61.1] always3(s29) || -> . % 76.30/76.41 211680[115:SSi:211679.0,78196.0,78199.0,192128.0,211240.0,211670.0] || -> . % 76.30/76.41 211681[115:Spt:211680.0,211675.0,211677.0] || m_main_v_state(s29,c_busy)* -> . % 76.30/76.41 211682[115:Spt:211680.0,211675.1] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 211686[115:Res:211682.0,61.1] always3(s30) || -> . % 76.30/76.41 211687[115:SSi:211686.0,78200.0,78204.0,192129.0] || -> . % 76.30/76.41 211688[113:Spt:211687.0,211239.0,211240.0] || until2p7(s29)*+ -> . % 76.30/76.41 211689[113:Spt:211687.0,211239.1] || -> node4(s28)*. % 76.30/76.41 211691[113:MRR:834.0,211689.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.30/76.41 211694[113:Res:53.1,211691.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.30/76.41 211696[114:Spt:211694.0] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 211698[114:Res:211696.0,61.1] always3(s28) || -> . % 76.30/76.41 211699[114:SSi:211698.0,78191.0,78195.0,192127.0,211238.0,211689.0] || -> . % 76.30/76.41 211700[114:Spt:211699.0,211694.0,211696.0] || m_main_v_state(s28,c_busy)* -> . % 76.30/76.41 211701[114:Spt:211699.0,211694.1] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 211705[114:Res:211701.0,61.1] always3(s29) || -> . % 76.30/76.41 211706[114:SSi:211705.0,78196.0,78199.0,192128.0] || -> . % 76.30/76.41 211707[112:Spt:211706.0,211237.0,211238.0] || until2p7(s28)*+ -> . % 76.30/76.41 211708[112:Spt:211706.0,211237.1] || -> node4(s27)*. % 76.30/76.41 211710[112:MRR:837.0,211708.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.30/76.41 211713[112:Res:53.1,211710.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.30/76.41 211715[113:Spt:211713.0] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 211717[113:Res:211715.0,61.1] always3(s27) || -> . % 76.30/76.41 211718[113:SSi:211717.0,78187.0,78190.0,192126.0,211236.0,211708.0] || -> . % 76.30/76.41 211719[113:Spt:211718.0,211713.0,211715.0] || m_main_v_state(s27,c_busy)* -> . % 76.30/76.41 211720[113:Spt:211718.0,211713.1] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 211724[113:Res:211720.0,61.1] always3(s28) || -> . % 76.30/76.41 211725[113:SSi:211724.0,78191.0,78195.0,192127.0] || -> . % 76.30/76.41 211726[111:Spt:211725.0,211235.0,211236.0] || until2p7(s27)*+ -> . % 76.30/76.41 211727[111:Spt:211725.0,211235.1] || -> node4(s26)*. % 76.30/76.41 211729[111:MRR:840.0,211727.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.30/76.41 211732[111:Res:53.1,211729.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.30/76.41 211737[112:Spt:211732.0] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 211739[112:Res:211737.0,61.1] always3(s26) || -> . % 76.30/76.41 211740[112:SSi:211739.0,78182.0,78186.0,192125.0,211234.0,211727.0] || -> . % 76.30/76.41 211741[112:Spt:211740.0,211732.0,211737.0] || m_main_v_state(s26,c_busy)* -> . % 76.30/76.41 211742[112:Spt:211740.0,211732.1] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 211746[112:Res:211742.0,61.1] always3(s27) || -> . % 76.30/76.41 211747[112:SSi:211746.0,78187.0,78190.0,192126.0] || -> . % 76.30/76.41 211748[110:Spt:211747.0,211233.0,211234.0] || until2p7(s26)*+ -> . % 76.30/76.41 211749[110:Spt:211747.0,211233.1] || -> node4(s25)*. % 76.30/76.41 211751[110:MRR:843.0,211749.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.30/76.41 211754[110:Res:53.1,211751.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.30/76.41 211756[111:Spt:211754.0] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 211758[111:Res:211756.0,61.1] always3(s25) || -> . % 76.30/76.41 211759[111:SSi:211758.0,78178.0,78181.0,192124.0,211232.0,211749.0] || -> . % 76.30/76.41 211760[111:Spt:211759.0,211754.0,211756.0] || m_main_v_state(s25,c_busy)* -> . % 76.30/76.41 211761[111:Spt:211759.0,211754.1] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 211765[111:Res:211761.0,61.1] always3(s26) || -> . % 76.30/76.41 211766[111:SSi:211765.0,78182.0,78186.0,192125.0] || -> . % 76.30/76.41 211767[109:Spt:211766.0,211231.0,211232.0] || until2p7(s25)*+ -> . % 76.30/76.41 211768[109:Spt:211766.0,211231.1] || -> node4(s24)*. % 76.30/76.41 211770[109:MRR:846.0,211768.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.30/76.41 211773[109:Res:53.1,211770.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.30/76.41 211775[110:Spt:211773.0] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 211777[110:Res:211775.0,61.1] always3(s24) || -> . % 76.30/76.41 211778[110:SSi:211777.0,78173.0,78177.0,192123.0,211230.0,211768.0] || -> . % 76.30/76.41 211779[110:Spt:211778.0,211773.0,211775.0] || m_main_v_state(s24,c_busy)* -> . % 76.30/76.41 211780[110:Spt:211778.0,211773.1] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 211784[110:Res:211780.0,61.1] always3(s25) || -> . % 76.30/76.41 211785[110:SSi:211784.0,78178.0,78181.0,192124.0] || -> . % 76.30/76.41 211786[108:Spt:211785.0,211229.0,211230.0] || until2p7(s24)*+ -> . % 76.30/76.41 211787[108:Spt:211785.0,211229.1] || -> node4(s23)*. % 76.30/76.41 211789[108:MRR:849.0,211787.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.30/76.41 211792[108:Res:53.1,211789.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.30/76.41 211794[109:Spt:211792.0] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 211796[109:Res:211794.0,61.1] always3(s23) || -> . % 76.30/76.41 211797[109:SSi:211796.0,78169.0,78172.0,192122.0,211228.0,211787.0] || -> . % 76.30/76.41 211798[109:Spt:211797.0,211792.0,211794.0] || m_main_v_state(s23,c_busy)* -> . % 76.30/76.41 211799[109:Spt:211797.0,211792.1] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 211803[109:Res:211799.0,61.1] always3(s24) || -> . % 76.30/76.41 211804[109:SSi:211803.0,78173.0,78177.0,192123.0] || -> . % 76.30/76.41 211805[107:Spt:211804.0,211227.0,211228.0] || until2p7(s23)*+ -> . % 76.30/76.41 211806[107:Spt:211804.0,211227.1] || -> node4(s22)*. % 76.30/76.41 211808[107:MRR:852.0,211806.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.30/76.41 211811[107:Res:53.1,211808.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.30/76.41 211816[108:Spt:211811.0] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 211818[108:Res:211816.0,61.1] always3(s22) || -> . % 76.30/76.41 211819[108:SSi:211818.0,78164.0,78168.0,192121.0,211226.0,211806.0] || -> . % 76.30/76.41 211820[108:Spt:211819.0,211811.0,211816.0] || m_main_v_state(s22,c_busy)* -> . % 76.30/76.41 211821[108:Spt:211819.0,211811.1] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 211825[108:Res:211821.0,61.1] always3(s23) || -> . % 76.30/76.41 211826[108:SSi:211825.0,78169.0,78172.0,192122.0] || -> . % 76.30/76.41 211827[106:Spt:211826.0,211225.0,211226.0] || until2p7(s22)*+ -> . % 76.30/76.41 211828[106:Spt:211826.0,211225.1] || -> node4(s21)*. % 76.30/76.41 211830[106:MRR:855.0,211828.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.30/76.41 211833[106:Res:53.1,211830.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.30/76.41 211835[107:Spt:211833.0] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 211837[107:Res:211835.0,61.1] always3(s21) || -> . % 76.30/76.41 211838[107:SSi:211837.0,78160.0,78163.0,192120.0,211224.0,211828.0] || -> . % 76.30/76.41 211839[107:Spt:211838.0,211833.0,211835.0] || m_main_v_state(s21,c_busy)* -> . % 76.30/76.41 211840[107:Spt:211838.0,211833.1] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 211844[107:Res:211840.0,61.1] always3(s22) || -> . % 76.30/76.41 211845[107:SSi:211844.0,78164.0,78168.0,192121.0] || -> . % 76.30/76.41 211846[105:Spt:211845.0,211223.0,211224.0] || until2p7(s21)*+ -> . % 76.30/76.41 211847[105:Spt:211845.0,211223.1] || -> node4(s20)*. % 76.30/76.41 211849[105:MRR:858.0,211847.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.30/76.41 211852[105:Res:53.1,211849.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.30/76.41 211854[106:Spt:211852.0] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 211856[106:Res:211854.0,61.1] always3(s20) || -> . % 76.30/76.41 211857[106:SSi:211856.0,78155.0,78159.0,192119.0,211222.0,211847.0] || -> . % 76.30/76.41 211858[106:Spt:211857.0,211852.0,211854.0] || m_main_v_state(s20,c_busy)* -> . % 76.30/76.41 211859[106:Spt:211857.0,211852.1] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 211863[106:Res:211859.0,61.1] always3(s21) || -> . % 76.30/76.41 211864[106:SSi:211863.0,78160.0,78163.0,192120.0] || -> . % 76.30/76.41 211865[104:Spt:211864.0,211221.0,211222.0] || until2p7(s20)*+ -> . % 76.30/76.41 211866[104:Spt:211864.0,211221.1] || -> node4(s19)*. % 76.30/76.41 211868[104:MRR:861.0,211866.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.30/76.41 211871[104:Res:53.1,211868.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.30/76.41 211873[105:Spt:211871.0] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 211875[105:Res:211873.0,61.1] always3(s19) || -> . % 76.30/76.41 211876[105:SSi:211875.0,78151.0,78154.0,192118.0,211220.0,211866.0] || -> . % 76.30/76.41 211877[105:Spt:211876.0,211871.0,211873.0] || m_main_v_state(s19,c_busy)* -> . % 76.30/76.41 211878[105:Spt:211876.0,211871.1] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 211882[105:Res:211878.0,61.1] always3(s20) || -> . % 76.30/76.41 211883[105:SSi:211882.0,78155.0,78159.0,192119.0] || -> . % 76.30/76.41 211884[103:Spt:211883.0,211219.0,211220.0] || until2p7(s19)*+ -> . % 76.30/76.41 211885[103:Spt:211883.0,211219.1] || -> node4(s18)*. % 76.30/76.41 211887[103:MRR:864.0,211885.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.30/76.41 211890[103:Res:53.1,211887.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.30/76.41 211895[104:Spt:211890.0] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 211897[104:Res:211895.0,61.1] always3(s18) || -> . % 76.30/76.41 211898[104:SSi:211897.0,78146.0,78150.0,192117.0,211218.0,211885.0] || -> . % 76.30/76.41 211899[104:Spt:211898.0,211890.0,211895.0] || m_main_v_state(s18,c_busy)* -> . % 76.30/76.41 211900[104:Spt:211898.0,211890.1] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 211904[104:Res:211900.0,61.1] always3(s19) || -> . % 76.30/76.41 211905[104:SSi:211904.0,78151.0,78154.0,192118.0] || -> . % 76.30/76.41 211906[102:Spt:211905.0,211217.0,211218.0] || until2p7(s18)*+ -> . % 76.30/76.41 211907[102:Spt:211905.0,211217.1] || -> node4(s17)*. % 76.30/76.41 211909[102:MRR:867.0,211907.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.30/76.41 211912[102:Res:53.1,211909.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.30/76.41 211914[103:Spt:211912.0] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 211916[103:Res:211914.0,61.1] always3(s17) || -> . % 76.30/76.41 211917[103:SSi:211916.0,78142.0,78145.0,192116.0,211216.0,211907.0] || -> . % 76.30/76.41 211918[103:Spt:211917.0,211912.0,211914.0] || m_main_v_state(s17,c_busy)* -> . % 76.30/76.41 211919[103:Spt:211917.0,211912.1] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 211923[103:Res:211919.0,61.1] always3(s18) || -> . % 76.30/76.41 211924[103:SSi:211923.0,78146.0,78150.0,192117.0] || -> . % 76.30/76.41 211925[101:Spt:211924.0,211215.0,211216.0] || until2p7(s17)*+ -> . % 76.30/76.41 211926[101:Spt:211924.0,211215.1] || -> node4(s16)*. % 76.30/76.41 211928[101:MRR:870.0,211926.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.30/76.41 211931[101:Res:53.1,211928.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.30/76.41 211933[102:Spt:211931.0] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 211935[102:Res:211933.0,61.1] always3(s16) || -> . % 76.30/76.41 211936[102:SSi:211935.0,78137.0,78141.0,192115.0,211214.0,211926.0] || -> . % 76.30/76.41 211937[102:Spt:211936.0,211931.0,211933.0] || m_main_v_state(s16,c_busy)* -> . % 76.30/76.41 211938[102:Spt:211936.0,211931.1] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 211942[102:Res:211938.0,61.1] always3(s17) || -> . % 76.30/76.41 211943[102:SSi:211942.0,78142.0,78145.0,192116.0] || -> . % 76.30/76.41 211944[100:Spt:211943.0,211213.0,211214.0] || until2p7(s16)*+ -> . % 76.30/76.41 211945[100:Spt:211943.0,211213.1] || -> node4(s15)*. % 76.30/76.41 211947[100:MRR:873.0,211945.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.30/76.41 211950[100:Res:53.1,211947.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.30/76.41 211952[101:Spt:211950.0] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 211954[101:Res:211952.0,61.1] always3(s15) || -> . % 76.30/76.41 211955[101:SSi:211954.0,78133.0,78136.0,192114.0,211212.0,211945.0] || -> . % 76.30/76.41 211956[101:Spt:211955.0,211950.0,211952.0] || m_main_v_state(s15,c_busy)* -> . % 76.30/76.41 211957[101:Spt:211955.0,211950.1] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 211961[101:Res:211957.0,61.1] always3(s16) || -> . % 76.30/76.41 211962[101:SSi:211961.0,78137.0,78141.0,192115.0] || -> . % 76.30/76.41 211963[99:Spt:211962.0,211211.0,211212.0] || until2p7(s15)*+ -> . % 76.30/76.41 211964[99:Spt:211962.0,211211.1] || -> node4(s14)*. % 76.30/76.41 211966[99:MRR:876.0,211964.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.30/76.41 211969[99:Res:53.1,211966.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.30/76.41 211974[100:Spt:211969.0] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 211976[100:Res:211974.0,61.1] always3(s14) || -> . % 76.30/76.41 211977[100:SSi:211976.0,78128.0,78132.0,192113.0,211210.0,211964.0] || -> . % 76.30/76.41 211978[100:Spt:211977.0,211969.0,211974.0] || m_main_v_state(s14,c_busy)* -> . % 76.30/76.41 211979[100:Spt:211977.0,211969.1] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 211983[100:Res:211979.0,61.1] always3(s15) || -> . % 76.30/76.41 211984[100:SSi:211983.0,78133.0,78136.0,192114.0] || -> . % 76.30/76.41 211985[98:Spt:211984.0,211209.0,211210.0] || until2p7(s14)*+ -> . % 76.30/76.41 211986[98:Spt:211984.0,211209.1] || -> node4(s13)*. % 76.30/76.41 211988[98:MRR:879.0,211986.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.30/76.41 211991[98:Res:53.1,211988.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.30/76.41 211993[99:Spt:211991.0] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 211995[99:Res:211993.0,61.1] always3(s13) || -> . % 76.30/76.41 211996[99:SSi:211995.0,78124.0,78127.0,192112.0,211208.0,211986.0] || -> . % 76.30/76.41 211997[99:Spt:211996.0,211991.0,211993.0] || m_main_v_state(s13,c_busy)* -> . % 76.30/76.41 211998[99:Spt:211996.0,211991.1] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 212002[99:Res:211998.0,61.1] always3(s14) || -> . % 76.30/76.41 212003[99:SSi:212002.0,78128.0,78132.0,192113.0] || -> . % 76.30/76.41 212004[97:Spt:212003.0,211207.0,211208.0] || until2p7(s13)*+ -> . % 76.30/76.41 212005[97:Spt:212003.0,211207.1] || -> node4(s12)*. % 76.30/76.41 212007[97:MRR:882.0,212005.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.30/76.41 212010[97:Res:53.1,212007.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.30/76.41 212012[98:Spt:212010.0] || -> m_main_v_state(s12,c_busy)*. % 76.30/76.41 212014[98:Res:212012.0,61.1] always3(s12) || -> . % 76.30/76.41 212015[98:SSi:212014.0,78119.0,78123.0,192111.0,211206.0,212005.0] || -> . % 76.30/76.41 212016[98:Spt:212015.0,212010.0,212012.0] || m_main_v_state(s12,c_busy)* -> . % 76.30/76.41 212017[98:Spt:212015.0,212010.1] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 212021[98:Res:212017.0,61.1] always3(s13) || -> . % 76.30/76.41 212022[98:SSi:212021.0,78124.0,78127.0,192112.0] || -> . % 76.30/76.41 212023[96:Spt:212022.0,211205.0,211206.0] || until2p7(s12)*+ -> . % 76.30/76.41 212024[96:Spt:212022.0,211205.1] || -> node4(s11)*. % 76.30/76.41 212026[96:MRR:885.0,212024.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.30/76.41 212029[96:Res:53.1,212026.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.30/76.41 212031[96:MRR:212029.0,211195.0] || -> m_main_v_state(s12,c_busy)*. % 76.30/76.41 212033[96:Res:212031.0,61.1] always3(s12) || -> . % 76.30/76.41 212034[96:SSi:212033.0,78119.0,78123.0,192111.0] || -> . % 76.30/76.41 212035[94:Spt:212034.0,211054.0,211057.0] || trans(s49,s11)*+ -> . % 76.30/76.41 212036[94:Spt:212034.0,211054.1,211054.2,211054.3,211054.4,211054.5] || -> trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.30/76.41 212038[94:MRR:211056.1,212035.0] xuntil6(s49) || -> trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.30/76.41 212039[95:Spt:212036.0] || -> trans(s49,s10)*. % 76.30/76.41 212040[95:Res:212039.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s10)*. % 76.30/76.41 212042[95:Res:212039.0,60.0] || -> node2(s49,s10)*. % 76.30/76.41 212043[95:SSi:212040.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s10)*. % 76.30/76.41 212044[95:Res:212042.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)*. % 76.30/76.41 212176[95:SoR:212044.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)*. % 76.30/76.41 212178[95:SoR:212176.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s10,c_busy)* xuntil6(s49). % 76.30/76.41 212179[95:SSi:212178.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s10,c_busy)* xuntil6(s49). % 76.30/76.41 212180[96:Spt:212179.1] || -> m_main_v_state(s10,c_busy)*. % 76.30/76.41 212182[96:Res:212180.0,61.1] always3(s10) || -> . % 76.30/76.41 212183[96:SSi:212182.0,78110.0,78114.0,192109.0] || -> . % 76.30/76.41 212184[96:Spt:212183.0,212179.1,212180.0] || m_main_v_state(s10,c_busy)*+ -> . % 76.30/76.41 212185[96:Spt:212183.0,212179.0,212179.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 212189[96:MRR:212176.2,212184.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 212190[96:Res:53.1,212185.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 212192[96:MRR:212190.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 212193[96:MRR:212043.0,212192.0] || -> until2p7(s10)*. % 76.30/76.41 212194[96:MRR:206.0,212193.0] || -> until2p7(s11)* node4(s10). % 76.30/76.41 212195[97:Spt:212194.0] || -> until2p7(s11)*. % 76.30/76.41 212196[97:MRR:207.0,212195.0] || -> until2p7(s12)* node4(s11). % 76.30/76.41 212197[98:Spt:212196.0] || -> until2p7(s12)*. % 76.30/76.41 212198[98:MRR:208.0,212197.0] || -> until2p7(s13)* node4(s12). % 76.30/76.41 212199[99:Spt:212198.0] || -> until2p7(s13)*. % 76.30/76.41 212200[99:MRR:209.0,212199.0] || -> until2p7(s14)* node4(s13). % 76.30/76.41 212201[100:Spt:212200.0] || -> until2p7(s14)*. % 76.30/76.41 212202[100:MRR:210.0,212201.0] || -> until2p7(s15)* node4(s14). % 76.30/76.41 212203[101:Spt:212202.0] || -> until2p7(s15)*. % 76.30/76.41 212204[101:MRR:211.0,212203.0] || -> until2p7(s16)* node4(s15). % 76.30/76.41 212205[102:Spt:212204.0] || -> until2p7(s16)*. % 76.30/76.41 212206[102:MRR:212.0,212205.0] || -> until2p7(s17)* node4(s16). % 76.30/76.41 212207[103:Spt:212206.0] || -> until2p7(s17)*. % 76.30/76.41 212208[103:MRR:213.0,212207.0] || -> until2p7(s18)* node4(s17). % 76.30/76.41 212209[104:Spt:212208.0] || -> until2p7(s18)*. % 76.30/76.41 212210[104:MRR:214.0,212209.0] || -> until2p7(s19)* node4(s18). % 76.30/76.41 212211[105:Spt:212210.0] || -> until2p7(s19)*. % 76.30/76.41 212212[105:MRR:215.0,212211.0] || -> until2p7(s20)* node4(s19). % 76.30/76.41 212213[106:Spt:212212.0] || -> until2p7(s20)*. % 76.30/76.41 212214[106:MRR:216.0,212213.0] || -> until2p7(s21)* node4(s20). % 76.30/76.41 212215[107:Spt:212214.0] || -> until2p7(s21)*. % 76.30/76.41 212216[107:MRR:217.0,212215.0] || -> until2p7(s22)* node4(s21). % 76.30/76.41 212217[108:Spt:212216.0] || -> until2p7(s22)*. % 76.30/76.41 212218[108:MRR:218.0,212217.0] || -> until2p7(s23)* node4(s22). % 76.30/76.41 212219[109:Spt:212218.0] || -> until2p7(s23)*. % 76.30/76.41 212220[109:MRR:219.0,212219.0] || -> until2p7(s24)* node4(s23). % 76.30/76.41 212221[110:Spt:212220.0] || -> until2p7(s24)*. % 76.30/76.41 212222[110:MRR:220.0,212221.0] || -> until2p7(s25)* node4(s24). % 76.30/76.41 212223[111:Spt:212222.0] || -> until2p7(s25)*. % 76.30/76.41 212224[111:MRR:221.0,212223.0] || -> until2p7(s26)* node4(s25). % 76.30/76.41 212225[112:Spt:212224.0] || -> until2p7(s26)*. % 76.30/76.41 212226[112:MRR:222.0,212225.0] || -> until2p7(s27)* node4(s26). % 76.30/76.41 212227[113:Spt:212226.0] || -> until2p7(s27)*. % 76.30/76.41 212228[113:MRR:223.0,212227.0] || -> until2p7(s28)* node4(s27). % 76.30/76.41 212229[114:Spt:212228.0] || -> until2p7(s28)*. % 76.30/76.41 212230[114:MRR:224.0,212229.0] || -> until2p7(s29)* node4(s28). % 76.30/76.41 212231[115:Spt:212230.0] || -> until2p7(s29)*. % 76.30/76.41 212232[115:MRR:225.0,212231.0] || -> until2p7(s30)* node4(s29). % 76.30/76.41 212233[116:Spt:212232.0] || -> until2p7(s30)*. % 76.30/76.41 212234[116:MRR:226.0,212233.0] || -> until2p7(s31)* node4(s30). % 76.30/76.41 212235[117:Spt:212234.0] || -> until2p7(s31)*. % 76.30/76.41 212236[117:MRR:227.0,212235.0] || -> until2p7(s32)* node4(s31). % 76.30/76.41 212237[118:Spt:212236.0] || -> until2p7(s32)*. % 76.30/76.41 212238[118:MRR:228.0,212237.0] || -> until2p7(s33)* node4(s32). % 76.30/76.41 212239[119:Spt:212238.0] || -> until2p7(s33)*. % 76.30/76.41 212240[119:MRR:229.0,212239.0] || -> until2p7(s34)* node4(s33). % 76.30/76.41 212241[120:Spt:212240.0] || -> until2p7(s34)*. % 76.30/76.41 212242[120:MRR:230.0,212241.0] || -> until2p7(s35)* node4(s34). % 76.30/76.41 212243[121:Spt:212242.0] || -> until2p7(s35)*. % 76.30/76.41 212244[121:MRR:231.0,212243.0] || -> until2p7(s36)* node4(s35). % 76.30/76.41 212245[122:Spt:212244.0] || -> until2p7(s36)*. % 76.30/76.41 212246[122:MRR:232.0,212245.0] || -> until2p7(s37)* node4(s36). % 76.30/76.41 212247[123:Spt:212246.0] || -> until2p7(s37)*. % 76.30/76.41 212248[123:MRR:235.0,212247.0] || -> until2p7(s38)* node4(s37). % 76.30/76.41 212249[124:Spt:212248.0] || -> until2p7(s38)*. % 76.30/76.41 212250[124:MRR:236.0,212249.0] || -> until2p7(s39)* node4(s38). % 76.30/76.41 212251[125:Spt:212250.0] || -> until2p7(s39)*. % 76.30/76.41 212252[125:MRR:237.0,212251.0] || -> until2p7(s40)* node4(s39). % 76.30/76.41 212253[126:Spt:212252.0] || -> until2p7(s40)*. % 76.30/76.41 212254[126:MRR:238.0,212253.0] || -> until2p7(s41)* node4(s40). % 76.30/76.41 212255[127:Spt:212254.0] || -> until2p7(s41)*. % 76.30/76.41 212256[127:MRR:239.0,212255.0] || -> until2p7(s42)* node4(s41). % 76.30/76.41 212257[128:Spt:212256.0] || -> until2p7(s42)*. % 76.30/76.41 212258[128:MRR:240.0,212257.0] || -> until2p7(s43)* node4(s42). % 76.30/76.41 212259[129:Spt:212258.0] || -> until2p7(s43)*. % 76.30/76.41 212260[129:MRR:241.0,212259.0] || -> until2p7(s44)* node4(s43). % 76.30/76.41 212261[130:Spt:212260.0] || -> until2p7(s44)*. % 76.30/76.41 212262[130:MRR:539.0,212261.0] || -> until2p7(s45)* node4(s44). % 76.30/76.41 212263[131:Spt:212262.0] || -> until2p7(s45)*. % 76.30/76.41 212264[131:MRR:544.0,212263.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 212265[132:Spt:212264.0] || -> until2p7(s46)*. % 76.30/76.41 212266[132:MRR:549.0,212265.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 212267[133:Spt:212266.0] || -> until2p7(s47)*. % 76.30/76.41 212268[133:MRR:554.0,212267.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 212269[134:Spt:212268.0] || -> until2p7(s48)*. % 76.30/76.41 212270[134:MRR:559.0,212269.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 212271[135:Spt:212270.0] || -> until2p7(s49)*. % 76.30/76.41 212272[135:MRR:194.0,212271.0] || -> node4(s49)*. % 76.30/76.41 212273[135:MRR:212189.0,212272.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 212274[135:Res:53.1,212273.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 212276[135:MRR:212274.0,78381.0] || -> . % 76.30/76.41 212277[135:Spt:212276.0,212270.0,212271.0] || until2p7(s49)*+ -> . % 76.30/76.41 212278[135:Spt:212276.0,212270.1] || -> node4(s48)*. % 76.30/76.41 212279[135:MRR:78384.0,212278.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 212282[135:Res:53.1,212279.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 212285[135:Res:212282.0,61.1] always3(s48) || -> . % 76.30/76.41 212286[135:SSi:212285.0,78281.0,78387.0,192147.0,212269.0,212278.0] || -> . % 76.30/76.41 212287[134:Spt:212286.0,212268.0,212269.0] || until2p7(s48)*+ -> . % 76.30/76.41 212288[134:Spt:212286.0,212268.1] || -> node4(s47)*. % 76.30/76.41 212290[134:MRR:777.0,212288.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 212305[134:Res:53.1,212290.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 212307[135:Spt:212305.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 212309[135:Res:212307.0,61.1] always3(s47) || -> . % 76.30/76.41 212310[135:SSi:212309.0,78277.0,78280.0,192146.0,212267.0,212288.0] || -> . % 76.30/76.41 212311[135:Spt:212310.0,212305.0,212307.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 212312[135:Spt:212310.0,212305.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 212316[135:Res:212312.0,61.1] always3(s48) || -> . % 76.30/76.41 212317[135:SSi:212316.0,78281.0,78387.0,192147.0] || -> . % 76.30/76.41 212318[133:Spt:212317.0,212266.0,212267.0] || until2p7(s47)*+ -> . % 76.30/76.41 212319[133:Spt:212317.0,212266.1] || -> node4(s46)*. % 76.30/76.41 212321[133:MRR:780.0,212319.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 212331[133:Res:53.1,212321.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 212333[134:Spt:212331.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 212335[134:Res:212333.0,61.1] always3(s46) || -> . % 76.30/76.41 212336[134:SSi:212335.0,78272.0,78276.0,192145.0,212265.0,212319.0] || -> . % 76.30/76.41 212337[134:Spt:212336.0,212331.0,212333.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 212338[134:Spt:212336.0,212331.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 212342[134:Res:212338.0,61.1] always3(s47) || -> . % 76.30/76.41 212343[134:SSi:212342.0,78277.0,78280.0,192146.0] || -> . % 76.30/76.41 212344[132:Spt:212343.0,212264.0,212265.0] || until2p7(s46)*+ -> . % 76.30/76.41 212345[132:Spt:212343.0,212264.1] || -> node4(s45)*. % 76.30/76.41 212347[132:MRR:783.0,212345.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 212350[132:Res:53.1,212347.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 212352[133:Spt:212350.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 212354[133:Res:212352.0,61.1] always3(s45) || -> . % 76.30/76.41 212355[133:SSi:212354.0,78268.0,78271.0,192144.0,212263.0,212345.0] || -> . % 76.30/76.41 212356[133:Spt:212355.0,212350.0,212352.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.41 212357[133:Spt:212355.0,212350.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 212361[133:Res:212357.0,61.1] always3(s46) || -> . % 76.30/76.41 212362[133:SSi:212361.0,78272.0,78276.0,192145.0] || -> . % 76.30/76.41 212363[131:Spt:212362.0,212262.0,212263.0] || until2p7(s45)*+ -> . % 76.30/76.41 212364[131:Spt:212362.0,212262.1] || -> node4(s44)*. % 76.30/76.41 212366[131:MRR:786.0,212364.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.41 212369[131:Res:53.1,212366.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.41 212371[132:Spt:212369.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 212373[132:Res:212371.0,61.1] always3(s44) || -> . % 76.30/76.41 212374[132:SSi:212373.0,78263.0,78267.0,192143.0,212261.0,212364.0] || -> . % 76.30/76.41 212375[132:Spt:212374.0,212369.0,212371.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.41 212376[132:Spt:212374.0,212369.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 212380[132:Res:212376.0,61.1] always3(s45) || -> . % 76.30/76.41 212381[132:SSi:212380.0,78268.0,78271.0,192144.0] || -> . % 76.30/76.41 212382[130:Spt:212381.0,212260.0,212261.0] || until2p7(s44)*+ -> . % 76.30/76.41 212383[130:Spt:212381.0,212260.1] || -> node4(s43)*. % 76.30/76.41 212385[130:MRR:789.0,212383.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.41 212388[130:Res:53.1,212385.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.41 212393[131:Spt:212388.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 212395[131:Res:212393.0,61.1] always3(s43) || -> . % 76.30/76.41 212396[131:SSi:212395.0,78259.0,78262.0,192142.0,212259.0,212383.0] || -> . % 76.30/76.41 212397[131:Spt:212396.0,212388.0,212393.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.41 212398[131:Spt:212396.0,212388.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 212402[131:Res:212398.0,61.1] always3(s44) || -> . % 76.30/76.41 212403[131:SSi:212402.0,78263.0,78267.0,192143.0] || -> . % 76.30/76.41 212404[129:Spt:212403.0,212258.0,212259.0] || until2p7(s43)*+ -> . % 76.30/76.41 212405[129:Spt:212403.0,212258.1] || -> node4(s42)*. % 76.30/76.41 212407[129:MRR:792.0,212405.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.41 212410[129:Res:53.1,212407.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.41 212412[130:Spt:212410.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 212414[130:Res:212412.0,61.1] always3(s42) || -> . % 76.30/76.41 212415[130:SSi:212414.0,78254.0,78258.0,192141.0,212257.0,212405.0] || -> . % 76.30/76.41 212416[130:Spt:212415.0,212410.0,212412.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.41 212417[130:Spt:212415.0,212410.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 212421[130:Res:212417.0,61.1] always3(s43) || -> . % 76.30/76.41 212422[130:SSi:212421.0,78259.0,78262.0,192142.0] || -> . % 76.30/76.41 212423[128:Spt:212422.0,212256.0,212257.0] || until2p7(s42)*+ -> . % 76.30/76.41 212424[128:Spt:212422.0,212256.1] || -> node4(s41)*. % 76.30/76.41 212426[128:MRR:795.0,212424.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.41 212429[128:Res:53.1,212426.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.41 212431[129:Spt:212429.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 212433[129:Res:212431.0,61.1] always3(s41) || -> . % 76.30/76.41 212434[129:SSi:212433.0,78250.0,78253.0,192140.0,212255.0,212424.0] || -> . % 76.30/76.41 212435[129:Spt:212434.0,212429.0,212431.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.41 212436[129:Spt:212434.0,212429.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 212440[129:Res:212436.0,61.1] always3(s42) || -> . % 76.30/76.41 212441[129:SSi:212440.0,78254.0,78258.0,192141.0] || -> . % 76.30/76.41 212442[127:Spt:212441.0,212254.0,212255.0] || until2p7(s41)*+ -> . % 76.30/76.41 212443[127:Spt:212441.0,212254.1] || -> node4(s40)*. % 76.30/76.41 212445[127:MRR:798.0,212443.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.41 212448[127:Res:53.1,212445.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.41 212450[128:Spt:212448.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 212452[128:Res:212450.0,61.1] always3(s40) || -> . % 76.30/76.41 212453[128:SSi:212452.0,78245.0,78249.0,192139.0,212253.0,212443.0] || -> . % 76.30/76.41 212454[128:Spt:212453.0,212448.0,212450.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.41 212455[128:Spt:212453.0,212448.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 212459[128:Res:212455.0,61.1] always3(s41) || -> . % 76.30/76.41 212460[128:SSi:212459.0,78250.0,78253.0,192140.0] || -> . % 76.30/76.41 212461[126:Spt:212460.0,212252.0,212253.0] || until2p7(s40)*+ -> . % 76.30/76.41 212462[126:Spt:212460.0,212252.1] || -> node4(s39)*. % 76.30/76.41 212464[126:MRR:801.0,212462.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.41 212467[126:Res:53.1,212464.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.41 212472[127:Spt:212467.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 212474[127:Res:212472.0,61.1] always3(s39) || -> . % 76.30/76.41 212475[127:SSi:212474.0,78241.0,78244.0,192138.0,212251.0,212462.0] || -> . % 76.30/76.41 212476[127:Spt:212475.0,212467.0,212472.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.41 212477[127:Spt:212475.0,212467.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 212481[127:Res:212477.0,61.1] always3(s40) || -> . % 76.30/76.41 212482[127:SSi:212481.0,78245.0,78249.0,192139.0] || -> . % 76.30/76.41 212483[125:Spt:212482.0,212250.0,212251.0] || until2p7(s39)*+ -> . % 76.30/76.41 212484[125:Spt:212482.0,212250.1] || -> node4(s38)*. % 76.30/76.41 212486[125:MRR:804.0,212484.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.41 212489[125:Res:53.1,212486.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.41 212491[126:Spt:212489.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 212493[126:Res:212491.0,61.1] always3(s38) || -> . % 76.30/76.41 212494[126:SSi:212493.0,78236.0,78240.0,192137.0,212249.0,212484.0] || -> . % 76.30/76.41 212495[126:Spt:212494.0,212489.0,212491.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.41 212496[126:Spt:212494.0,212489.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 212500[126:Res:212496.0,61.1] always3(s39) || -> . % 76.30/76.41 212501[126:SSi:212500.0,78241.0,78244.0,192138.0] || -> . % 76.30/76.41 212502[124:Spt:212501.0,212248.0,212249.0] || until2p7(s38)*+ -> . % 76.30/76.41 212503[124:Spt:212501.0,212248.1] || -> node4(s37)*. % 76.30/76.41 212505[124:MRR:807.0,212503.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.41 212508[124:Res:53.1,212505.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.41 212510[125:Spt:212508.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 212512[125:Res:212510.0,61.1] always3(s37) || -> . % 76.30/76.41 212513[125:SSi:212512.0,78232.0,78235.0,192136.0,212247.0,212503.0] || -> . % 76.30/76.41 212514[125:Spt:212513.0,212508.0,212510.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.41 212515[125:Spt:212513.0,212508.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 212519[125:Res:212515.0,61.1] always3(s38) || -> . % 76.30/76.41 212520[125:SSi:212519.0,78236.0,78240.0,192137.0] || -> . % 76.30/76.41 212521[123:Spt:212520.0,212246.0,212247.0] || until2p7(s37)*+ -> . % 76.30/76.41 212522[123:Spt:212520.0,212246.1] || -> node4(s36)*. % 76.30/76.41 212524[123:MRR:810.0,212522.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.41 212527[123:Res:53.1,212524.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.41 212529[124:Spt:212527.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 212531[124:Res:212529.0,61.1] always3(s36) || -> . % 76.30/76.41 212532[124:SSi:212531.0,78227.0,78231.0,192135.0,212245.0,212522.0] || -> . % 76.30/76.41 212533[124:Spt:212532.0,212527.0,212529.0] || m_main_v_state(s36,c_busy)* -> . % 76.30/76.41 212534[124:Spt:212532.0,212527.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 212538[124:Res:212534.0,61.1] always3(s37) || -> . % 76.30/76.41 212539[124:SSi:212538.0,78232.0,78235.0,192136.0] || -> . % 76.30/76.41 212540[122:Spt:212539.0,212244.0,212245.0] || until2p7(s36)*+ -> . % 76.30/76.41 212541[122:Spt:212539.0,212244.1] || -> node4(s35)*. % 76.30/76.41 212543[122:MRR:813.0,212541.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.30/76.41 212546[122:Res:53.1,212543.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.30/76.41 212551[123:Spt:212546.0] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 212553[123:Res:212551.0,61.1] always3(s35) || -> . % 76.30/76.41 212554[123:SSi:212553.0,78223.0,78226.0,192134.0,212243.0,212541.0] || -> . % 76.30/76.41 212555[123:Spt:212554.0,212546.0,212551.0] || m_main_v_state(s35,c_busy)* -> . % 76.30/76.41 212556[123:Spt:212554.0,212546.1] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 212560[123:Res:212556.0,61.1] always3(s36) || -> . % 76.30/76.41 212561[123:SSi:212560.0,78227.0,78231.0,192135.0] || -> . % 76.30/76.41 212562[121:Spt:212561.0,212242.0,212243.0] || until2p7(s35)*+ -> . % 76.30/76.41 212563[121:Spt:212561.0,212242.1] || -> node4(s34)*. % 76.30/76.41 212565[121:MRR:816.0,212563.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.30/76.41 212568[121:Res:53.1,212565.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.30/76.41 212570[122:Spt:212568.0] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 212572[122:Res:212570.0,61.1] always3(s34) || -> . % 76.30/76.41 212573[122:SSi:212572.0,78218.0,78222.0,192133.0,212241.0,212563.0] || -> . % 76.30/76.41 212574[122:Spt:212573.0,212568.0,212570.0] || m_main_v_state(s34,c_busy)* -> . % 76.30/76.41 212575[122:Spt:212573.0,212568.1] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 212579[122:Res:212575.0,61.1] always3(s35) || -> . % 76.30/76.41 212580[122:SSi:212579.0,78223.0,78226.0,192134.0] || -> . % 76.30/76.41 212581[120:Spt:212580.0,212240.0,212241.0] || until2p7(s34)*+ -> . % 76.30/76.41 212582[120:Spt:212580.0,212240.1] || -> node4(s33)*. % 76.30/76.41 212584[120:MRR:819.0,212582.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.30/76.41 212587[120:Res:53.1,212584.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.30/76.41 212589[121:Spt:212587.0] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 212591[121:Res:212589.0,61.1] always3(s33) || -> . % 76.30/76.41 212592[121:SSi:212591.0,78214.0,78217.0,192132.0,212239.0,212582.0] || -> . % 76.30/76.41 212593[121:Spt:212592.0,212587.0,212589.0] || m_main_v_state(s33,c_busy)* -> . % 76.30/76.41 212594[121:Spt:212592.0,212587.1] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 212598[121:Res:212594.0,61.1] always3(s34) || -> . % 76.30/76.41 212599[121:SSi:212598.0,78218.0,78222.0,192133.0] || -> . % 76.30/76.41 212600[119:Spt:212599.0,212238.0,212239.0] || until2p7(s33)*+ -> . % 76.30/76.41 212601[119:Spt:212599.0,212238.1] || -> node4(s32)*. % 76.30/76.41 212603[119:MRR:822.0,212601.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.30/76.41 212606[119:Res:53.1,212603.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.30/76.41 212608[120:Spt:212606.0] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 212610[120:Res:212608.0,61.1] always3(s32) || -> . % 76.30/76.41 212611[120:SSi:212610.0,78209.0,78213.0,192131.0,212237.0,212601.0] || -> . % 76.30/76.41 212612[120:Spt:212611.0,212606.0,212608.0] || m_main_v_state(s32,c_busy)* -> . % 76.30/76.41 212613[120:Spt:212611.0,212606.1] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 212617[120:Res:212613.0,61.1] always3(s33) || -> . % 76.30/76.41 212618[120:SSi:212617.0,78214.0,78217.0,192132.0] || -> . % 76.30/76.41 212619[118:Spt:212618.0,212236.0,212237.0] || until2p7(s32)*+ -> . % 76.30/76.41 212620[118:Spt:212618.0,212236.1] || -> node4(s31)*. % 76.30/76.41 212622[118:MRR:825.0,212620.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.30/76.41 212625[118:Res:53.1,212622.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.30/76.41 212630[119:Spt:212625.0] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 212632[119:Res:212630.0,61.1] always3(s31) || -> . % 76.30/76.41 212633[119:SSi:212632.0,78205.0,78208.0,192130.0,212235.0,212620.0] || -> . % 76.30/76.41 212634[119:Spt:212633.0,212625.0,212630.0] || m_main_v_state(s31,c_busy)* -> . % 76.30/76.41 212635[119:Spt:212633.0,212625.1] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 212639[119:Res:212635.0,61.1] always3(s32) || -> . % 76.30/76.41 212640[119:SSi:212639.0,78209.0,78213.0,192131.0] || -> . % 76.30/76.41 212641[117:Spt:212640.0,212234.0,212235.0] || until2p7(s31)*+ -> . % 76.30/76.41 212642[117:Spt:212640.0,212234.1] || -> node4(s30)*. % 76.30/76.41 212644[117:MRR:828.0,212642.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.30/76.41 212647[117:Res:53.1,212644.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.30/76.41 212649[118:Spt:212647.0] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 212651[118:Res:212649.0,61.1] always3(s30) || -> . % 76.30/76.41 212652[118:SSi:212651.0,78200.0,78204.0,192129.0,212233.0,212642.0] || -> . % 76.30/76.41 212653[118:Spt:212652.0,212647.0,212649.0] || m_main_v_state(s30,c_busy)* -> . % 76.30/76.41 212654[118:Spt:212652.0,212647.1] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 212658[118:Res:212654.0,61.1] always3(s31) || -> . % 76.30/76.41 212659[118:SSi:212658.0,78205.0,78208.0,192130.0] || -> . % 76.30/76.41 212660[116:Spt:212659.0,212232.0,212233.0] || until2p7(s30)*+ -> . % 76.30/76.41 212661[116:Spt:212659.0,212232.1] || -> node4(s29)*. % 76.30/76.41 212663[116:MRR:831.0,212661.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.30/76.41 212666[116:Res:53.1,212663.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.30/76.41 212668[117:Spt:212666.0] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 212670[117:Res:212668.0,61.1] always3(s29) || -> . % 76.30/76.41 212671[117:SSi:212670.0,78196.0,78199.0,192128.0,212231.0,212661.0] || -> . % 76.30/76.41 212672[117:Spt:212671.0,212666.0,212668.0] || m_main_v_state(s29,c_busy)* -> . % 76.30/76.41 212673[117:Spt:212671.0,212666.1] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 212677[117:Res:212673.0,61.1] always3(s30) || -> . % 76.30/76.41 212678[117:SSi:212677.0,78200.0,78204.0,192129.0] || -> . % 76.30/76.41 212679[115:Spt:212678.0,212230.0,212231.0] || until2p7(s29)*+ -> . % 76.30/76.41 212680[115:Spt:212678.0,212230.1] || -> node4(s28)*. % 76.30/76.41 212682[115:MRR:834.0,212680.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.30/76.41 212685[115:Res:53.1,212682.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.30/76.41 212687[116:Spt:212685.0] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 212689[116:Res:212687.0,61.1] always3(s28) || -> . % 76.30/76.41 212690[116:SSi:212689.0,78191.0,78195.0,192127.0,212229.0,212680.0] || -> . % 76.30/76.41 212691[116:Spt:212690.0,212685.0,212687.0] || m_main_v_state(s28,c_busy)* -> . % 76.30/76.41 212692[116:Spt:212690.0,212685.1] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 212696[116:Res:212692.0,61.1] always3(s29) || -> . % 76.30/76.41 212697[116:SSi:212696.0,78196.0,78199.0,192128.0] || -> . % 76.30/76.41 212698[114:Spt:212697.0,212228.0,212229.0] || until2p7(s28)*+ -> . % 76.30/76.41 212699[114:Spt:212697.0,212228.1] || -> node4(s27)*. % 76.30/76.41 212701[114:MRR:837.0,212699.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.30/76.41 212704[114:Res:53.1,212701.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.30/76.41 212709[115:Spt:212704.0] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 212711[115:Res:212709.0,61.1] always3(s27) || -> . % 76.30/76.41 212712[115:SSi:212711.0,78187.0,78190.0,192126.0,212227.0,212699.0] || -> . % 76.30/76.41 212713[115:Spt:212712.0,212704.0,212709.0] || m_main_v_state(s27,c_busy)* -> . % 76.30/76.41 212714[115:Spt:212712.0,212704.1] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 212718[115:Res:212714.0,61.1] always3(s28) || -> . % 76.30/76.41 212719[115:SSi:212718.0,78191.0,78195.0,192127.0] || -> . % 76.30/76.41 212720[113:Spt:212719.0,212226.0,212227.0] || until2p7(s27)*+ -> . % 76.30/76.41 212721[113:Spt:212719.0,212226.1] || -> node4(s26)*. % 76.30/76.41 212723[113:MRR:840.0,212721.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.30/76.41 212726[113:Res:53.1,212723.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.30/76.41 212728[114:Spt:212726.0] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 212730[114:Res:212728.0,61.1] always3(s26) || -> . % 76.30/76.41 212731[114:SSi:212730.0,78182.0,78186.0,192125.0,212225.0,212721.0] || -> . % 76.30/76.41 212732[114:Spt:212731.0,212726.0,212728.0] || m_main_v_state(s26,c_busy)* -> . % 76.30/76.41 212733[114:Spt:212731.0,212726.1] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 212737[114:Res:212733.0,61.1] always3(s27) || -> . % 76.30/76.41 212738[114:SSi:212737.0,78187.0,78190.0,192126.0] || -> . % 76.30/76.41 212739[112:Spt:212738.0,212224.0,212225.0] || until2p7(s26)*+ -> . % 76.30/76.41 212740[112:Spt:212738.0,212224.1] || -> node4(s25)*. % 76.30/76.41 212742[112:MRR:843.0,212740.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.30/76.41 212745[112:Res:53.1,212742.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.30/76.41 212747[113:Spt:212745.0] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 212749[113:Res:212747.0,61.1] always3(s25) || -> . % 76.30/76.41 212750[113:SSi:212749.0,78178.0,78181.0,192124.0,212223.0,212740.0] || -> . % 76.30/76.41 212751[113:Spt:212750.0,212745.0,212747.0] || m_main_v_state(s25,c_busy)* -> . % 76.30/76.41 212752[113:Spt:212750.0,212745.1] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 212756[113:Res:212752.0,61.1] always3(s26) || -> . % 76.30/76.41 212757[113:SSi:212756.0,78182.0,78186.0,192125.0] || -> . % 76.30/76.41 212758[111:Spt:212757.0,212222.0,212223.0] || until2p7(s25)*+ -> . % 76.30/76.41 212759[111:Spt:212757.0,212222.1] || -> node4(s24)*. % 76.30/76.41 212761[111:MRR:846.0,212759.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.30/76.41 212764[111:Res:53.1,212761.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.30/76.41 212766[112:Spt:212764.0] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 212768[112:Res:212766.0,61.1] always3(s24) || -> . % 76.30/76.41 212769[112:SSi:212768.0,78173.0,78177.0,192123.0,212221.0,212759.0] || -> . % 76.30/76.41 212770[112:Spt:212769.0,212764.0,212766.0] || m_main_v_state(s24,c_busy)* -> . % 76.30/76.41 212771[112:Spt:212769.0,212764.1] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 212775[112:Res:212771.0,61.1] always3(s25) || -> . % 76.30/76.41 212776[112:SSi:212775.0,78178.0,78181.0,192124.0] || -> . % 76.30/76.41 212777[110:Spt:212776.0,212220.0,212221.0] || until2p7(s24)*+ -> . % 76.30/76.41 212778[110:Spt:212776.0,212220.1] || -> node4(s23)*. % 76.30/76.41 212780[110:MRR:849.0,212778.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.30/76.41 212783[110:Res:53.1,212780.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.30/76.41 212788[111:Spt:212783.0] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 212790[111:Res:212788.0,61.1] always3(s23) || -> . % 76.30/76.41 212791[111:SSi:212790.0,78169.0,78172.0,192122.0,212219.0,212778.0] || -> . % 76.30/76.41 212792[111:Spt:212791.0,212783.0,212788.0] || m_main_v_state(s23,c_busy)* -> . % 76.30/76.41 212793[111:Spt:212791.0,212783.1] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 212797[111:Res:212793.0,61.1] always3(s24) || -> . % 76.30/76.41 212798[111:SSi:212797.0,78173.0,78177.0,192123.0] || -> . % 76.30/76.41 212799[109:Spt:212798.0,212218.0,212219.0] || until2p7(s23)*+ -> . % 76.30/76.41 212800[109:Spt:212798.0,212218.1] || -> node4(s22)*. % 76.30/76.41 212802[109:MRR:852.0,212800.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.30/76.41 212805[109:Res:53.1,212802.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.30/76.41 212807[110:Spt:212805.0] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 212809[110:Res:212807.0,61.1] always3(s22) || -> . % 76.30/76.41 212810[110:SSi:212809.0,78164.0,78168.0,192121.0,212217.0,212800.0] || -> . % 76.30/76.41 212811[110:Spt:212810.0,212805.0,212807.0] || m_main_v_state(s22,c_busy)* -> . % 76.30/76.41 212812[110:Spt:212810.0,212805.1] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 212816[110:Res:212812.0,61.1] always3(s23) || -> . % 76.30/76.41 212817[110:SSi:212816.0,78169.0,78172.0,192122.0] || -> . % 76.30/76.41 212818[108:Spt:212817.0,212216.0,212217.0] || until2p7(s22)*+ -> . % 76.30/76.41 212819[108:Spt:212817.0,212216.1] || -> node4(s21)*. % 76.30/76.41 212821[108:MRR:855.0,212819.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.30/76.41 212824[108:Res:53.1,212821.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.30/76.41 212826[109:Spt:212824.0] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 212828[109:Res:212826.0,61.1] always3(s21) || -> . % 76.30/76.41 212829[109:SSi:212828.0,78160.0,78163.0,192120.0,212215.0,212819.0] || -> . % 76.30/76.41 212830[109:Spt:212829.0,212824.0,212826.0] || m_main_v_state(s21,c_busy)* -> . % 76.30/76.41 212831[109:Spt:212829.0,212824.1] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 212835[109:Res:212831.0,61.1] always3(s22) || -> . % 76.30/76.41 212836[109:SSi:212835.0,78164.0,78168.0,192121.0] || -> . % 76.30/76.41 212837[107:Spt:212836.0,212214.0,212215.0] || until2p7(s21)*+ -> . % 76.30/76.41 212838[107:Spt:212836.0,212214.1] || -> node4(s20)*. % 76.30/76.41 212840[107:MRR:858.0,212838.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.30/76.41 212843[107:Res:53.1,212840.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.30/76.41 212845[108:Spt:212843.0] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 212847[108:Res:212845.0,61.1] always3(s20) || -> . % 76.30/76.41 212848[108:SSi:212847.0,78155.0,78159.0,192119.0,212213.0,212838.0] || -> . % 76.30/76.41 212849[108:Spt:212848.0,212843.0,212845.0] || m_main_v_state(s20,c_busy)* -> . % 76.30/76.41 212850[108:Spt:212848.0,212843.1] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 212854[108:Res:212850.0,61.1] always3(s21) || -> . % 76.30/76.41 212855[108:SSi:212854.0,78160.0,78163.0,192120.0] || -> . % 76.30/76.41 212856[106:Spt:212855.0,212212.0,212213.0] || until2p7(s20)*+ -> . % 76.30/76.41 212857[106:Spt:212855.0,212212.1] || -> node4(s19)*. % 76.30/76.41 212859[106:MRR:861.0,212857.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.30/76.41 212862[106:Res:53.1,212859.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.30/76.41 212867[107:Spt:212862.0] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 212869[107:Res:212867.0,61.1] always3(s19) || -> . % 76.30/76.41 212870[107:SSi:212869.0,78151.0,78154.0,192118.0,212211.0,212857.0] || -> . % 76.30/76.41 212871[107:Spt:212870.0,212862.0,212867.0] || m_main_v_state(s19,c_busy)* -> . % 76.30/76.41 212872[107:Spt:212870.0,212862.1] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 212876[107:Res:212872.0,61.1] always3(s20) || -> . % 76.30/76.41 212877[107:SSi:212876.0,78155.0,78159.0,192119.0] || -> . % 76.30/76.41 212878[105:Spt:212877.0,212210.0,212211.0] || until2p7(s19)*+ -> . % 76.30/76.41 212879[105:Spt:212877.0,212210.1] || -> node4(s18)*. % 76.30/76.41 212881[105:MRR:864.0,212879.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.30/76.41 212884[105:Res:53.1,212881.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.30/76.41 212886[106:Spt:212884.0] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 212888[106:Res:212886.0,61.1] always3(s18) || -> . % 76.30/76.41 212889[106:SSi:212888.0,78146.0,78150.0,192117.0,212209.0,212879.0] || -> . % 76.30/76.41 212890[106:Spt:212889.0,212884.0,212886.0] || m_main_v_state(s18,c_busy)* -> . % 76.30/76.41 212891[106:Spt:212889.0,212884.1] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 212895[106:Res:212891.0,61.1] always3(s19) || -> . % 76.30/76.41 212896[106:SSi:212895.0,78151.0,78154.0,192118.0] || -> . % 76.30/76.41 212897[104:Spt:212896.0,212208.0,212209.0] || until2p7(s18)*+ -> . % 76.30/76.41 212898[104:Spt:212896.0,212208.1] || -> node4(s17)*. % 76.30/76.41 212900[104:MRR:867.0,212898.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.30/76.41 212903[104:Res:53.1,212900.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.30/76.41 212905[105:Spt:212903.0] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 212907[105:Res:212905.0,61.1] always3(s17) || -> . % 76.30/76.41 212908[105:SSi:212907.0,78142.0,78145.0,192116.0,212207.0,212898.0] || -> . % 76.30/76.41 212909[105:Spt:212908.0,212903.0,212905.0] || m_main_v_state(s17,c_busy)* -> . % 76.30/76.41 212910[105:Spt:212908.0,212903.1] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 212914[105:Res:212910.0,61.1] always3(s18) || -> . % 76.30/76.41 212915[105:SSi:212914.0,78146.0,78150.0,192117.0] || -> . % 76.30/76.41 212916[103:Spt:212915.0,212206.0,212207.0] || until2p7(s17)*+ -> . % 76.30/76.41 212917[103:Spt:212915.0,212206.1] || -> node4(s16)*. % 76.30/76.41 212919[103:MRR:870.0,212917.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.30/76.41 212922[103:Res:53.1,212919.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.30/76.41 212924[104:Spt:212922.0] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 212926[104:Res:212924.0,61.1] always3(s16) || -> . % 76.30/76.41 212927[104:SSi:212926.0,78137.0,78141.0,192115.0,212205.0,212917.0] || -> . % 76.30/76.41 212928[104:Spt:212927.0,212922.0,212924.0] || m_main_v_state(s16,c_busy)* -> . % 76.30/76.41 212929[104:Spt:212927.0,212922.1] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 212933[104:Res:212929.0,61.1] always3(s17) || -> . % 76.30/76.41 212934[104:SSi:212933.0,78142.0,78145.0,192116.0] || -> . % 76.30/76.41 212935[102:Spt:212934.0,212204.0,212205.0] || until2p7(s16)*+ -> . % 76.30/76.41 212936[102:Spt:212934.0,212204.1] || -> node4(s15)*. % 76.30/76.41 212938[102:MRR:873.0,212936.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.30/76.41 212941[102:Res:53.1,212938.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.30/76.41 212946[103:Spt:212941.0] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 212948[103:Res:212946.0,61.1] always3(s15) || -> . % 76.30/76.41 212949[103:SSi:212948.0,78133.0,78136.0,192114.0,212203.0,212936.0] || -> . % 76.30/76.41 212950[103:Spt:212949.0,212941.0,212946.0] || m_main_v_state(s15,c_busy)* -> . % 76.30/76.41 212951[103:Spt:212949.0,212941.1] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 212955[103:Res:212951.0,61.1] always3(s16) || -> . % 76.30/76.41 212956[103:SSi:212955.0,78137.0,78141.0,192115.0] || -> . % 76.30/76.41 212957[101:Spt:212956.0,212202.0,212203.0] || until2p7(s15)*+ -> . % 76.30/76.41 212958[101:Spt:212956.0,212202.1] || -> node4(s14)*. % 76.30/76.41 212960[101:MRR:876.0,212958.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.30/76.41 212963[101:Res:53.1,212960.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.30/76.41 212965[102:Spt:212963.0] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 212967[102:Res:212965.0,61.1] always3(s14) || -> . % 76.30/76.41 212968[102:SSi:212967.0,78128.0,78132.0,192113.0,212201.0,212958.0] || -> . % 76.30/76.41 212969[102:Spt:212968.0,212963.0,212965.0] || m_main_v_state(s14,c_busy)* -> . % 76.30/76.41 212970[102:Spt:212968.0,212963.1] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 212974[102:Res:212970.0,61.1] always3(s15) || -> . % 76.30/76.41 212975[102:SSi:212974.0,78133.0,78136.0,192114.0] || -> . % 76.30/76.41 212976[100:Spt:212975.0,212200.0,212201.0] || until2p7(s14)*+ -> . % 76.30/76.41 212977[100:Spt:212975.0,212200.1] || -> node4(s13)*. % 76.30/76.41 212979[100:MRR:879.0,212977.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.30/76.41 212982[100:Res:53.1,212979.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.30/76.41 212984[101:Spt:212982.0] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 212986[101:Res:212984.0,61.1] always3(s13) || -> . % 76.30/76.41 212987[101:SSi:212986.0,78124.0,78127.0,192112.0,212199.0,212977.0] || -> . % 76.30/76.41 212988[101:Spt:212987.0,212982.0,212984.0] || m_main_v_state(s13,c_busy)* -> . % 76.30/76.41 212989[101:Spt:212987.0,212982.1] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 212993[101:Res:212989.0,61.1] always3(s14) || -> . % 76.30/76.41 212994[101:SSi:212993.0,78128.0,78132.0,192113.0] || -> . % 76.30/76.41 212995[99:Spt:212994.0,212198.0,212199.0] || until2p7(s13)*+ -> . % 76.30/76.41 212996[99:Spt:212994.0,212198.1] || -> node4(s12)*. % 76.30/76.41 212998[99:MRR:882.0,212996.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.30/76.41 213001[99:Res:53.1,212998.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.30/76.41 213003[100:Spt:213001.0] || -> m_main_v_state(s12,c_busy)*. % 76.30/76.41 213005[100:Res:213003.0,61.1] always3(s12) || -> . % 76.30/76.41 213006[100:SSi:213005.0,78119.0,78123.0,192111.0,212197.0,212996.0] || -> . % 76.30/76.41 213007[100:Spt:213006.0,213001.0,213003.0] || m_main_v_state(s12,c_busy)* -> . % 76.30/76.41 213008[100:Spt:213006.0,213001.1] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 213012[100:Res:213008.0,61.1] always3(s13) || -> . % 76.30/76.41 213013[100:SSi:213012.0,78124.0,78127.0,192112.0] || -> . % 76.30/76.41 213014[98:Spt:213013.0,212196.0,212197.0] || until2p7(s12)*+ -> . % 76.30/76.41 213015[98:Spt:213013.0,212196.1] || -> node4(s11)*. % 76.30/76.41 213017[98:MRR:885.0,213015.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.30/76.41 213020[98:Res:53.1,213017.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.30/76.41 213025[99:Spt:213020.0] || -> m_main_v_state(s11,c_busy)*. % 76.30/76.41 213027[99:Res:213025.0,61.1] always3(s11) || -> . % 76.30/76.41 213028[99:SSi:213027.0,78115.0,78118.0,192110.0,212195.0,213015.0] || -> . % 76.30/76.41 213029[99:Spt:213028.0,213020.0,213025.0] || m_main_v_state(s11,c_busy)* -> . % 76.30/76.41 213030[99:Spt:213028.0,213020.1] || -> m_main_v_state(s12,c_busy)*. % 76.30/76.41 213034[99:Res:213030.0,61.1] always3(s12) || -> . % 76.30/76.41 213035[99:SSi:213034.0,78119.0,78123.0,192111.0] || -> . % 76.30/76.41 213036[97:Spt:213035.0,212194.0,212195.0] || until2p7(s11)*+ -> . % 76.30/76.41 213037[97:Spt:213035.0,212194.1] || -> node4(s10)*. % 76.30/76.41 213039[97:MRR:888.0,213037.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.30/76.41 213042[97:Res:53.1,213039.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.30/76.41 213044[97:MRR:213042.0,212184.0] || -> m_main_v_state(s11,c_busy)*. % 76.30/76.41 213046[97:Res:213044.0,61.1] always3(s11) || -> . % 76.30/76.41 213047[97:SSi:213046.0,78115.0,78118.0,192110.0] || -> . % 76.30/76.41 213048[95:Spt:213047.0,212036.0,212039.0] || trans(s49,s10)*+ -> . % 76.30/76.41 213049[95:Spt:213047.0,212036.1,212036.2,212036.3,212036.4] || -> trans(s49,s9) trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.30/76.41 213051[95:MRR:212038.1,213048.0] xuntil6(s49) || -> trans(s49,s9) trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.30/76.41 213052[96:Spt:213049.0] || -> trans(s49,s9)*. % 76.30/76.41 213053[96:Res:213052.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s9)*. % 76.30/76.41 213055[96:Res:213052.0,60.0] || -> node2(s49,s9)*. % 76.30/76.41 213056[96:SSi:213053.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s9)*. % 76.30/76.41 213057[96:Res:213055.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)*. % 76.30/76.41 213190[96:SoR:213057.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)*. % 76.30/76.41 213192[96:SoR:213190.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s9,c_busy)* xuntil6(s49). % 76.30/76.41 213193[96:SSi:213192.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s9,c_busy)* xuntil6(s49). % 76.30/76.41 213194[97:Spt:213193.1] || -> m_main_v_state(s9,c_busy)*. % 76.30/76.41 213196[97:Res:213194.0,61.1] always3(s9) || -> . % 76.30/76.41 213197[97:SSi:213196.0,78106.0,78109.0,192108.0] || -> . % 76.30/76.41 213198[97:Spt:213197.0,213193.1,213194.0] || m_main_v_state(s9,c_busy)*+ -> . % 76.30/76.41 213199[97:Spt:213197.0,213193.0,213193.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 213203[97:MRR:213190.2,213198.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 213204[97:Res:53.1,213199.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 213206[97:MRR:213204.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 213207[97:MRR:213056.0,213206.0] || -> until2p7(s9)*. % 76.30/76.41 213208[97:MRR:205.0,213207.0] || -> until2p7(s10)* node4(s9). % 76.30/76.41 213209[98:Spt:213208.0] || -> until2p7(s10)*. % 76.30/76.41 213210[98:MRR:206.0,213209.0] || -> until2p7(s11)* node4(s10). % 76.30/76.41 213211[99:Spt:213210.0] || -> until2p7(s11)*. % 76.30/76.41 213212[99:MRR:207.0,213211.0] || -> until2p7(s12)* node4(s11). % 76.30/76.41 213213[100:Spt:213212.0] || -> until2p7(s12)*. % 76.30/76.41 213214[100:MRR:208.0,213213.0] || -> until2p7(s13)* node4(s12). % 76.30/76.41 213215[101:Spt:213214.0] || -> until2p7(s13)*. % 76.30/76.41 213216[101:MRR:209.0,213215.0] || -> until2p7(s14)* node4(s13). % 76.30/76.41 213217[102:Spt:213216.0] || -> until2p7(s14)*. % 76.30/76.41 213218[102:MRR:210.0,213217.0] || -> until2p7(s15)* node4(s14). % 76.30/76.41 213219[103:Spt:213218.0] || -> until2p7(s15)*. % 76.30/76.41 213220[103:MRR:211.0,213219.0] || -> until2p7(s16)* node4(s15). % 76.30/76.41 213221[104:Spt:213220.0] || -> until2p7(s16)*. % 76.30/76.41 213222[104:MRR:212.0,213221.0] || -> until2p7(s17)* node4(s16). % 76.30/76.41 213223[105:Spt:213222.0] || -> until2p7(s17)*. % 76.30/76.41 213224[105:MRR:213.0,213223.0] || -> until2p7(s18)* node4(s17). % 76.30/76.41 213225[106:Spt:213224.0] || -> until2p7(s18)*. % 76.30/76.41 213226[106:MRR:214.0,213225.0] || -> until2p7(s19)* node4(s18). % 76.30/76.41 213227[107:Spt:213226.0] || -> until2p7(s19)*. % 76.30/76.41 213228[107:MRR:215.0,213227.0] || -> until2p7(s20)* node4(s19). % 76.30/76.41 213229[108:Spt:213228.0] || -> until2p7(s20)*. % 76.30/76.41 213230[108:MRR:216.0,213229.0] || -> until2p7(s21)* node4(s20). % 76.30/76.41 213231[109:Spt:213230.0] || -> until2p7(s21)*. % 76.30/76.41 213232[109:MRR:217.0,213231.0] || -> until2p7(s22)* node4(s21). % 76.30/76.41 213233[110:Spt:213232.0] || -> until2p7(s22)*. % 76.30/76.41 213234[110:MRR:218.0,213233.0] || -> until2p7(s23)* node4(s22). % 76.30/76.41 213235[111:Spt:213234.0] || -> until2p7(s23)*. % 76.30/76.41 213236[111:MRR:219.0,213235.0] || -> until2p7(s24)* node4(s23). % 76.30/76.41 213237[112:Spt:213236.0] || -> until2p7(s24)*. % 76.30/76.41 213238[112:MRR:220.0,213237.0] || -> until2p7(s25)* node4(s24). % 76.30/76.41 213239[113:Spt:213238.0] || -> until2p7(s25)*. % 76.30/76.41 213240[113:MRR:221.0,213239.0] || -> until2p7(s26)* node4(s25). % 76.30/76.41 213241[114:Spt:213240.0] || -> until2p7(s26)*. % 76.30/76.41 213242[114:MRR:222.0,213241.0] || -> until2p7(s27)* node4(s26). % 76.30/76.41 213243[115:Spt:213242.0] || -> until2p7(s27)*. % 76.30/76.41 213244[115:MRR:223.0,213243.0] || -> until2p7(s28)* node4(s27). % 76.30/76.41 213245[116:Spt:213244.0] || -> until2p7(s28)*. % 76.30/76.41 213246[116:MRR:224.0,213245.0] || -> until2p7(s29)* node4(s28). % 76.30/76.41 213247[117:Spt:213246.0] || -> until2p7(s29)*. % 76.30/76.41 213248[117:MRR:225.0,213247.0] || -> until2p7(s30)* node4(s29). % 76.30/76.41 213249[118:Spt:213248.0] || -> until2p7(s30)*. % 76.30/76.41 213250[118:MRR:226.0,213249.0] || -> until2p7(s31)* node4(s30). % 76.30/76.41 213251[119:Spt:213250.0] || -> until2p7(s31)*. % 76.30/76.41 213252[119:MRR:227.0,213251.0] || -> until2p7(s32)* node4(s31). % 76.30/76.41 213253[120:Spt:213252.0] || -> until2p7(s32)*. % 76.30/76.41 213254[120:MRR:228.0,213253.0] || -> until2p7(s33)* node4(s32). % 76.30/76.41 213255[121:Spt:213254.0] || -> until2p7(s33)*. % 76.30/76.41 213256[121:MRR:229.0,213255.0] || -> until2p7(s34)* node4(s33). % 76.30/76.41 213257[122:Spt:213256.0] || -> until2p7(s34)*. % 76.30/76.41 213258[122:MRR:230.0,213257.0] || -> until2p7(s35)* node4(s34). % 76.30/76.41 213259[123:Spt:213258.0] || -> until2p7(s35)*. % 76.30/76.41 213260[123:MRR:231.0,213259.0] || -> until2p7(s36)* node4(s35). % 76.30/76.41 213261[124:Spt:213260.0] || -> until2p7(s36)*. % 76.30/76.41 213262[124:MRR:232.0,213261.0] || -> until2p7(s37)* node4(s36). % 76.30/76.41 213263[125:Spt:213262.0] || -> until2p7(s37)*. % 76.30/76.41 213264[125:MRR:235.0,213263.0] || -> until2p7(s38)* node4(s37). % 76.30/76.41 213265[126:Spt:213264.0] || -> until2p7(s38)*. % 76.30/76.41 213266[126:MRR:236.0,213265.0] || -> until2p7(s39)* node4(s38). % 76.30/76.41 213267[127:Spt:213266.0] || -> until2p7(s39)*. % 76.30/76.41 213268[127:MRR:237.0,213267.0] || -> until2p7(s40)* node4(s39). % 76.30/76.41 213269[128:Spt:213268.0] || -> until2p7(s40)*. % 76.30/76.41 213270[128:MRR:238.0,213269.0] || -> until2p7(s41)* node4(s40). % 76.30/76.41 213271[129:Spt:213270.0] || -> until2p7(s41)*. % 76.30/76.41 213272[129:MRR:239.0,213271.0] || -> until2p7(s42)* node4(s41). % 76.30/76.41 213273[130:Spt:213272.0] || -> until2p7(s42)*. % 76.30/76.41 213274[130:MRR:240.0,213273.0] || -> until2p7(s43)* node4(s42). % 76.30/76.41 213275[131:Spt:213274.0] || -> until2p7(s43)*. % 76.30/76.41 213276[131:MRR:241.0,213275.0] || -> until2p7(s44)* node4(s43). % 76.30/76.41 213277[132:Spt:213276.0] || -> until2p7(s44)*. % 76.30/76.41 213278[132:MRR:539.0,213277.0] || -> until2p7(s45)* node4(s44). % 76.30/76.41 213279[133:Spt:213278.0] || -> until2p7(s45)*. % 76.30/76.41 213280[133:MRR:544.0,213279.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 213281[134:Spt:213280.0] || -> until2p7(s46)*. % 76.30/76.41 213282[134:MRR:549.0,213281.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 213283[135:Spt:213282.0] || -> until2p7(s47)*. % 76.30/76.41 213284[135:MRR:554.0,213283.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 213285[136:Spt:213284.0] || -> until2p7(s48)*. % 76.30/76.41 213286[136:MRR:559.0,213285.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 213287[137:Spt:213286.0] || -> until2p7(s49)*. % 76.30/76.41 213288[137:MRR:194.0,213287.0] || -> node4(s49)*. % 76.30/76.41 213289[137:MRR:213203.0,213288.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 213290[137:Res:53.1,213289.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 213292[137:MRR:213290.0,78381.0] || -> . % 76.30/76.41 213293[137:Spt:213292.0,213286.0,213287.0] || until2p7(s49)*+ -> . % 76.30/76.41 213294[137:Spt:213292.0,213286.1] || -> node4(s48)*. % 76.30/76.41 213295[137:MRR:78384.0,213294.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 213298[137:Res:53.1,213295.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 213301[137:Res:213298.0,61.1] always3(s48) || -> . % 76.30/76.41 213302[137:SSi:213301.0,78281.0,78387.0,192147.0,213285.0,213294.0] || -> . % 76.30/76.41 213303[136:Spt:213302.0,213284.0,213285.0] || until2p7(s48)*+ -> . % 76.30/76.41 213304[136:Spt:213302.0,213284.1] || -> node4(s47)*. % 76.30/76.41 213306[136:MRR:777.0,213304.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 213321[136:Res:53.1,213306.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 213323[137:Spt:213321.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 213325[137:Res:213323.0,61.1] always3(s47) || -> . % 76.30/76.41 213326[137:SSi:213325.0,78277.0,78280.0,192146.0,213283.0,213304.0] || -> . % 76.30/76.41 213327[137:Spt:213326.0,213321.0,213323.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 213328[137:Spt:213326.0,213321.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 213332[137:Res:213328.0,61.1] always3(s48) || -> . % 76.30/76.41 213333[137:SSi:213332.0,78281.0,78387.0,192147.0] || -> . % 76.30/76.41 213334[135:Spt:213333.0,213282.0,213283.0] || until2p7(s47)*+ -> . % 76.30/76.41 213335[135:Spt:213333.0,213282.1] || -> node4(s46)*. % 76.30/76.41 213337[135:MRR:780.0,213335.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 213347[135:Res:53.1,213337.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 213349[136:Spt:213347.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 213351[136:Res:213349.0,61.1] always3(s46) || -> . % 76.30/76.41 213352[136:SSi:213351.0,78272.0,78276.0,192145.0,213281.0,213335.0] || -> . % 76.30/76.41 213353[136:Spt:213352.0,213347.0,213349.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 213354[136:Spt:213352.0,213347.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 213358[136:Res:213354.0,61.1] always3(s47) || -> . % 76.30/76.41 213359[136:SSi:213358.0,78277.0,78280.0,192146.0] || -> . % 76.30/76.41 213360[134:Spt:213359.0,213280.0,213281.0] || until2p7(s46)*+ -> . % 76.30/76.41 213361[134:Spt:213359.0,213280.1] || -> node4(s45)*. % 76.30/76.41 213363[134:MRR:783.0,213361.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 213366[134:Res:53.1,213363.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 213368[135:Spt:213366.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 213370[135:Res:213368.0,61.1] always3(s45) || -> . % 76.30/76.41 213371[135:SSi:213370.0,78268.0,78271.0,192144.0,213279.0,213361.0] || -> . % 76.30/76.41 213372[135:Spt:213371.0,213366.0,213368.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.41 213373[135:Spt:213371.0,213366.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 213377[135:Res:213373.0,61.1] always3(s46) || -> . % 76.30/76.41 213378[135:SSi:213377.0,78272.0,78276.0,192145.0] || -> . % 76.30/76.41 213379[133:Spt:213378.0,213278.0,213279.0] || until2p7(s45)*+ -> . % 76.30/76.41 213380[133:Spt:213378.0,213278.1] || -> node4(s44)*. % 76.30/76.41 213382[133:MRR:786.0,213380.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.41 213385[133:Res:53.1,213382.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.41 213387[134:Spt:213385.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 213389[134:Res:213387.0,61.1] always3(s44) || -> . % 76.30/76.41 213390[134:SSi:213389.0,78263.0,78267.0,192143.0,213277.0,213380.0] || -> . % 76.30/76.41 213391[134:Spt:213390.0,213385.0,213387.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.41 213392[134:Spt:213390.0,213385.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 213396[134:Res:213392.0,61.1] always3(s45) || -> . % 76.30/76.41 213397[134:SSi:213396.0,78268.0,78271.0,192144.0] || -> . % 76.30/76.41 213398[132:Spt:213397.0,213276.0,213277.0] || until2p7(s44)*+ -> . % 76.30/76.41 213399[132:Spt:213397.0,213276.1] || -> node4(s43)*. % 76.30/76.41 213401[132:MRR:789.0,213399.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.41 213404[132:Res:53.1,213401.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.41 213409[133:Spt:213404.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 213411[133:Res:213409.0,61.1] always3(s43) || -> . % 76.30/76.41 213412[133:SSi:213411.0,78259.0,78262.0,192142.0,213275.0,213399.0] || -> . % 76.30/76.41 213413[133:Spt:213412.0,213404.0,213409.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.41 213414[133:Spt:213412.0,213404.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 213418[133:Res:213414.0,61.1] always3(s44) || -> . % 76.30/76.41 213419[133:SSi:213418.0,78263.0,78267.0,192143.0] || -> . % 76.30/76.41 213420[131:Spt:213419.0,213274.0,213275.0] || until2p7(s43)*+ -> . % 76.30/76.41 213421[131:Spt:213419.0,213274.1] || -> node4(s42)*. % 76.30/76.41 213423[131:MRR:792.0,213421.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.41 213426[131:Res:53.1,213423.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.41 213428[132:Spt:213426.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 213430[132:Res:213428.0,61.1] always3(s42) || -> . % 76.30/76.41 213431[132:SSi:213430.0,78254.0,78258.0,192141.0,213273.0,213421.0] || -> . % 76.30/76.41 213432[132:Spt:213431.0,213426.0,213428.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.41 213433[132:Spt:213431.0,213426.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 213437[132:Res:213433.0,61.1] always3(s43) || -> . % 76.30/76.41 213438[132:SSi:213437.0,78259.0,78262.0,192142.0] || -> . % 76.30/76.41 213439[130:Spt:213438.0,213272.0,213273.0] || until2p7(s42)*+ -> . % 76.30/76.41 213440[130:Spt:213438.0,213272.1] || -> node4(s41)*. % 76.30/76.41 213442[130:MRR:795.0,213440.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.41 213445[130:Res:53.1,213442.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.41 213447[131:Spt:213445.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 213449[131:Res:213447.0,61.1] always3(s41) || -> . % 76.30/76.41 213450[131:SSi:213449.0,78250.0,78253.0,192140.0,213271.0,213440.0] || -> . % 76.30/76.41 213451[131:Spt:213450.0,213445.0,213447.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.41 213452[131:Spt:213450.0,213445.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 213456[131:Res:213452.0,61.1] always3(s42) || -> . % 76.30/76.41 213457[131:SSi:213456.0,78254.0,78258.0,192141.0] || -> . % 76.30/76.41 213458[129:Spt:213457.0,213270.0,213271.0] || until2p7(s41)*+ -> . % 76.30/76.41 213459[129:Spt:213457.0,213270.1] || -> node4(s40)*. % 76.30/76.41 213461[129:MRR:798.0,213459.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.41 213464[129:Res:53.1,213461.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.41 213466[130:Spt:213464.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 213468[130:Res:213466.0,61.1] always3(s40) || -> . % 76.30/76.41 213469[130:SSi:213468.0,78245.0,78249.0,192139.0,213269.0,213459.0] || -> . % 76.30/76.41 213470[130:Spt:213469.0,213464.0,213466.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.41 213471[130:Spt:213469.0,213464.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 213475[130:Res:213471.0,61.1] always3(s41) || -> . % 76.30/76.41 213476[130:SSi:213475.0,78250.0,78253.0,192140.0] || -> . % 76.30/76.41 213477[128:Spt:213476.0,213268.0,213269.0] || until2p7(s40)*+ -> . % 76.30/76.41 213478[128:Spt:213476.0,213268.1] || -> node4(s39)*. % 76.30/76.41 213480[128:MRR:801.0,213478.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.41 213483[128:Res:53.1,213480.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.41 213488[129:Spt:213483.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 213490[129:Res:213488.0,61.1] always3(s39) || -> . % 76.30/76.41 213491[129:SSi:213490.0,78241.0,78244.0,192138.0,213267.0,213478.0] || -> . % 76.30/76.41 213492[129:Spt:213491.0,213483.0,213488.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.41 213493[129:Spt:213491.0,213483.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 213497[129:Res:213493.0,61.1] always3(s40) || -> . % 76.30/76.41 213498[129:SSi:213497.0,78245.0,78249.0,192139.0] || -> . % 76.30/76.41 213499[127:Spt:213498.0,213266.0,213267.0] || until2p7(s39)*+ -> . % 76.30/76.41 213500[127:Spt:213498.0,213266.1] || -> node4(s38)*. % 76.30/76.41 213502[127:MRR:804.0,213500.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.41 213505[127:Res:53.1,213502.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.41 213507[128:Spt:213505.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 213509[128:Res:213507.0,61.1] always3(s38) || -> . % 76.30/76.41 213510[128:SSi:213509.0,78236.0,78240.0,192137.0,213265.0,213500.0] || -> . % 76.30/76.41 213511[128:Spt:213510.0,213505.0,213507.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.41 213512[128:Spt:213510.0,213505.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 213516[128:Res:213512.0,61.1] always3(s39) || -> . % 76.30/76.41 213517[128:SSi:213516.0,78241.0,78244.0,192138.0] || -> . % 76.30/76.41 213518[126:Spt:213517.0,213264.0,213265.0] || until2p7(s38)*+ -> . % 76.30/76.41 213519[126:Spt:213517.0,213264.1] || -> node4(s37)*. % 76.30/76.41 213521[126:MRR:807.0,213519.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.41 213524[126:Res:53.1,213521.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.41 213526[127:Spt:213524.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 213528[127:Res:213526.0,61.1] always3(s37) || -> . % 76.30/76.41 213529[127:SSi:213528.0,78232.0,78235.0,192136.0,213263.0,213519.0] || -> . % 76.30/76.41 213530[127:Spt:213529.0,213524.0,213526.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.41 213531[127:Spt:213529.0,213524.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 213535[127:Res:213531.0,61.1] always3(s38) || -> . % 76.30/76.41 213536[127:SSi:213535.0,78236.0,78240.0,192137.0] || -> . % 76.30/76.41 213537[125:Spt:213536.0,213262.0,213263.0] || until2p7(s37)*+ -> . % 76.30/76.41 213538[125:Spt:213536.0,213262.1] || -> node4(s36)*. % 76.30/76.41 213540[125:MRR:810.0,213538.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.41 213543[125:Res:53.1,213540.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.41 213545[126:Spt:213543.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 213547[126:Res:213545.0,61.1] always3(s36) || -> . % 76.30/76.41 213548[126:SSi:213547.0,78227.0,78231.0,192135.0,213261.0,213538.0] || -> . % 76.30/76.41 213549[126:Spt:213548.0,213543.0,213545.0] || m_main_v_state(s36,c_busy)* -> . % 76.30/76.41 213550[126:Spt:213548.0,213543.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 213554[126:Res:213550.0,61.1] always3(s37) || -> . % 76.30/76.41 213555[126:SSi:213554.0,78232.0,78235.0,192136.0] || -> . % 76.30/76.41 213556[124:Spt:213555.0,213260.0,213261.0] || until2p7(s36)*+ -> . % 76.30/76.41 213557[124:Spt:213555.0,213260.1] || -> node4(s35)*. % 76.30/76.41 213559[124:MRR:813.0,213557.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.30/76.41 213562[124:Res:53.1,213559.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.30/76.41 213567[125:Spt:213562.0] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 213569[125:Res:213567.0,61.1] always3(s35) || -> . % 76.30/76.41 213570[125:SSi:213569.0,78223.0,78226.0,192134.0,213259.0,213557.0] || -> . % 76.30/76.41 213571[125:Spt:213570.0,213562.0,213567.0] || m_main_v_state(s35,c_busy)* -> . % 76.30/76.41 213572[125:Spt:213570.0,213562.1] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 213576[125:Res:213572.0,61.1] always3(s36) || -> . % 76.30/76.41 213577[125:SSi:213576.0,78227.0,78231.0,192135.0] || -> . % 76.30/76.41 213578[123:Spt:213577.0,213258.0,213259.0] || until2p7(s35)*+ -> . % 76.30/76.41 213579[123:Spt:213577.0,213258.1] || -> node4(s34)*. % 76.30/76.41 213581[123:MRR:816.0,213579.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.30/76.41 213584[123:Res:53.1,213581.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.30/76.41 213586[124:Spt:213584.0] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 213588[124:Res:213586.0,61.1] always3(s34) || -> . % 76.30/76.41 213589[124:SSi:213588.0,78218.0,78222.0,192133.0,213257.0,213579.0] || -> . % 76.30/76.41 213590[124:Spt:213589.0,213584.0,213586.0] || m_main_v_state(s34,c_busy)* -> . % 76.30/76.41 213591[124:Spt:213589.0,213584.1] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 213595[124:Res:213591.0,61.1] always3(s35) || -> . % 76.30/76.41 213596[124:SSi:213595.0,78223.0,78226.0,192134.0] || -> . % 76.30/76.41 213597[122:Spt:213596.0,213256.0,213257.0] || until2p7(s34)*+ -> . % 76.30/76.41 213598[122:Spt:213596.0,213256.1] || -> node4(s33)*. % 76.30/76.41 213600[122:MRR:819.0,213598.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.30/76.41 213603[122:Res:53.1,213600.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.30/76.41 213605[123:Spt:213603.0] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 213607[123:Res:213605.0,61.1] always3(s33) || -> . % 76.30/76.41 213608[123:SSi:213607.0,78214.0,78217.0,192132.0,213255.0,213598.0] || -> . % 76.30/76.41 213609[123:Spt:213608.0,213603.0,213605.0] || m_main_v_state(s33,c_busy)* -> . % 76.30/76.41 213610[123:Spt:213608.0,213603.1] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 213614[123:Res:213610.0,61.1] always3(s34) || -> . % 76.30/76.41 213615[123:SSi:213614.0,78218.0,78222.0,192133.0] || -> . % 76.30/76.41 213616[121:Spt:213615.0,213254.0,213255.0] || until2p7(s33)*+ -> . % 76.30/76.41 213617[121:Spt:213615.0,213254.1] || -> node4(s32)*. % 76.30/76.41 213619[121:MRR:822.0,213617.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.30/76.41 213622[121:Res:53.1,213619.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.30/76.41 213624[122:Spt:213622.0] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 213626[122:Res:213624.0,61.1] always3(s32) || -> . % 76.30/76.41 213627[122:SSi:213626.0,78209.0,78213.0,192131.0,213253.0,213617.0] || -> . % 76.30/76.41 213628[122:Spt:213627.0,213622.0,213624.0] || m_main_v_state(s32,c_busy)* -> . % 76.30/76.41 213629[122:Spt:213627.0,213622.1] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 213633[122:Res:213629.0,61.1] always3(s33) || -> . % 76.30/76.41 213634[122:SSi:213633.0,78214.0,78217.0,192132.0] || -> . % 76.30/76.41 213635[120:Spt:213634.0,213252.0,213253.0] || until2p7(s32)*+ -> . % 76.30/76.41 213636[120:Spt:213634.0,213252.1] || -> node4(s31)*. % 76.30/76.41 213638[120:MRR:825.0,213636.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.30/76.41 213641[120:Res:53.1,213638.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.30/76.41 213646[121:Spt:213641.0] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 213648[121:Res:213646.0,61.1] always3(s31) || -> . % 76.30/76.41 213649[121:SSi:213648.0,78205.0,78208.0,192130.0,213251.0,213636.0] || -> . % 76.30/76.41 213650[121:Spt:213649.0,213641.0,213646.0] || m_main_v_state(s31,c_busy)* -> . % 76.30/76.41 213651[121:Spt:213649.0,213641.1] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 213655[121:Res:213651.0,61.1] always3(s32) || -> . % 76.30/76.41 213656[121:SSi:213655.0,78209.0,78213.0,192131.0] || -> . % 76.30/76.41 213657[119:Spt:213656.0,213250.0,213251.0] || until2p7(s31)*+ -> . % 76.30/76.41 213658[119:Spt:213656.0,213250.1] || -> node4(s30)*. % 76.30/76.41 213660[119:MRR:828.0,213658.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.30/76.41 213663[119:Res:53.1,213660.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.30/76.41 213665[120:Spt:213663.0] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 213667[120:Res:213665.0,61.1] always3(s30) || -> . % 76.30/76.41 213668[120:SSi:213667.0,78200.0,78204.0,192129.0,213249.0,213658.0] || -> . % 76.30/76.41 213669[120:Spt:213668.0,213663.0,213665.0] || m_main_v_state(s30,c_busy)* -> . % 76.30/76.41 213670[120:Spt:213668.0,213663.1] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 213674[120:Res:213670.0,61.1] always3(s31) || -> . % 76.30/76.41 213675[120:SSi:213674.0,78205.0,78208.0,192130.0] || -> . % 76.30/76.41 213676[118:Spt:213675.0,213248.0,213249.0] || until2p7(s30)*+ -> . % 76.30/76.41 213677[118:Spt:213675.0,213248.1] || -> node4(s29)*. % 76.30/76.41 213679[118:MRR:831.0,213677.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.30/76.41 213682[118:Res:53.1,213679.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.30/76.41 213684[119:Spt:213682.0] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 213686[119:Res:213684.0,61.1] always3(s29) || -> . % 76.30/76.41 213687[119:SSi:213686.0,78196.0,78199.0,192128.0,213247.0,213677.0] || -> . % 76.30/76.41 213688[119:Spt:213687.0,213682.0,213684.0] || m_main_v_state(s29,c_busy)* -> . % 76.30/76.41 213689[119:Spt:213687.0,213682.1] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 213693[119:Res:213689.0,61.1] always3(s30) || -> . % 76.30/76.41 213694[119:SSi:213693.0,78200.0,78204.0,192129.0] || -> . % 76.30/76.41 213695[117:Spt:213694.0,213246.0,213247.0] || until2p7(s29)*+ -> . % 76.30/76.41 213696[117:Spt:213694.0,213246.1] || -> node4(s28)*. % 76.30/76.41 213698[117:MRR:834.0,213696.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.30/76.41 213701[117:Res:53.1,213698.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.30/76.41 213703[118:Spt:213701.0] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 213705[118:Res:213703.0,61.1] always3(s28) || -> . % 76.30/76.41 213706[118:SSi:213705.0,78191.0,78195.0,192127.0,213245.0,213696.0] || -> . % 76.30/76.41 213707[118:Spt:213706.0,213701.0,213703.0] || m_main_v_state(s28,c_busy)* -> . % 76.30/76.41 213708[118:Spt:213706.0,213701.1] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 213712[118:Res:213708.0,61.1] always3(s29) || -> . % 76.30/76.41 213713[118:SSi:213712.0,78196.0,78199.0,192128.0] || -> . % 76.30/76.41 213714[116:Spt:213713.0,213244.0,213245.0] || until2p7(s28)*+ -> . % 76.30/76.41 213715[116:Spt:213713.0,213244.1] || -> node4(s27)*. % 76.30/76.41 213717[116:MRR:837.0,213715.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.30/76.41 213720[116:Res:53.1,213717.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.30/76.41 213725[117:Spt:213720.0] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 213727[117:Res:213725.0,61.1] always3(s27) || -> . % 76.30/76.41 213728[117:SSi:213727.0,78187.0,78190.0,192126.0,213243.0,213715.0] || -> . % 76.30/76.41 213729[117:Spt:213728.0,213720.0,213725.0] || m_main_v_state(s27,c_busy)* -> . % 76.30/76.41 213730[117:Spt:213728.0,213720.1] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 213734[117:Res:213730.0,61.1] always3(s28) || -> . % 76.30/76.41 213735[117:SSi:213734.0,78191.0,78195.0,192127.0] || -> . % 76.30/76.41 213736[115:Spt:213735.0,213242.0,213243.0] || until2p7(s27)*+ -> . % 76.30/76.41 213737[115:Spt:213735.0,213242.1] || -> node4(s26)*. % 76.30/76.41 213739[115:MRR:840.0,213737.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.30/76.41 213742[115:Res:53.1,213739.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.30/76.41 213744[116:Spt:213742.0] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 213746[116:Res:213744.0,61.1] always3(s26) || -> . % 76.30/76.41 213747[116:SSi:213746.0,78182.0,78186.0,192125.0,213241.0,213737.0] || -> . % 76.30/76.41 213748[116:Spt:213747.0,213742.0,213744.0] || m_main_v_state(s26,c_busy)* -> . % 76.30/76.41 213749[116:Spt:213747.0,213742.1] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 213753[116:Res:213749.0,61.1] always3(s27) || -> . % 76.30/76.41 213754[116:SSi:213753.0,78187.0,78190.0,192126.0] || -> . % 76.30/76.41 213755[114:Spt:213754.0,213240.0,213241.0] || until2p7(s26)*+ -> . % 76.30/76.41 213756[114:Spt:213754.0,213240.1] || -> node4(s25)*. % 76.30/76.41 213758[114:MRR:843.0,213756.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.30/76.41 213761[114:Res:53.1,213758.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.30/76.41 213763[115:Spt:213761.0] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 213765[115:Res:213763.0,61.1] always3(s25) || -> . % 76.30/76.41 213766[115:SSi:213765.0,78178.0,78181.0,192124.0,213239.0,213756.0] || -> . % 76.30/76.41 213767[115:Spt:213766.0,213761.0,213763.0] || m_main_v_state(s25,c_busy)* -> . % 76.30/76.41 213768[115:Spt:213766.0,213761.1] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 213772[115:Res:213768.0,61.1] always3(s26) || -> . % 76.30/76.41 213773[115:SSi:213772.0,78182.0,78186.0,192125.0] || -> . % 76.30/76.41 213774[113:Spt:213773.0,213238.0,213239.0] || until2p7(s25)*+ -> . % 76.30/76.41 213775[113:Spt:213773.0,213238.1] || -> node4(s24)*. % 76.30/76.41 213777[113:MRR:846.0,213775.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.30/76.41 213780[113:Res:53.1,213777.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.30/76.41 213782[114:Spt:213780.0] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 213784[114:Res:213782.0,61.1] always3(s24) || -> . % 76.30/76.41 213785[114:SSi:213784.0,78173.0,78177.0,192123.0,213237.0,213775.0] || -> . % 76.30/76.41 213786[114:Spt:213785.0,213780.0,213782.0] || m_main_v_state(s24,c_busy)* -> . % 76.30/76.41 213787[114:Spt:213785.0,213780.1] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 213791[114:Res:213787.0,61.1] always3(s25) || -> . % 76.30/76.41 213792[114:SSi:213791.0,78178.0,78181.0,192124.0] || -> . % 76.30/76.41 213793[112:Spt:213792.0,213236.0,213237.0] || until2p7(s24)*+ -> . % 76.30/76.41 213794[112:Spt:213792.0,213236.1] || -> node4(s23)*. % 76.30/76.41 213796[112:MRR:849.0,213794.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.30/76.41 213799[112:Res:53.1,213796.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.30/76.41 213804[113:Spt:213799.0] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 213806[113:Res:213804.0,61.1] always3(s23) || -> . % 76.30/76.41 213807[113:SSi:213806.0,78169.0,78172.0,192122.0,213235.0,213794.0] || -> . % 76.30/76.41 213808[113:Spt:213807.0,213799.0,213804.0] || m_main_v_state(s23,c_busy)* -> . % 76.30/76.41 213809[113:Spt:213807.0,213799.1] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 213813[113:Res:213809.0,61.1] always3(s24) || -> . % 76.30/76.41 213814[113:SSi:213813.0,78173.0,78177.0,192123.0] || -> . % 76.30/76.41 213815[111:Spt:213814.0,213234.0,213235.0] || until2p7(s23)*+ -> . % 76.30/76.41 213816[111:Spt:213814.0,213234.1] || -> node4(s22)*. % 76.30/76.41 213818[111:MRR:852.0,213816.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.30/76.41 213821[111:Res:53.1,213818.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.30/76.41 213823[112:Spt:213821.0] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 213825[112:Res:213823.0,61.1] always3(s22) || -> . % 76.30/76.41 213826[112:SSi:213825.0,78164.0,78168.0,192121.0,213233.0,213816.0] || -> . % 76.30/76.41 213827[112:Spt:213826.0,213821.0,213823.0] || m_main_v_state(s22,c_busy)* -> . % 76.30/76.41 213828[112:Spt:213826.0,213821.1] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 213832[112:Res:213828.0,61.1] always3(s23) || -> . % 76.30/76.41 213833[112:SSi:213832.0,78169.0,78172.0,192122.0] || -> . % 76.30/76.41 213834[110:Spt:213833.0,213232.0,213233.0] || until2p7(s22)*+ -> . % 76.30/76.41 213835[110:Spt:213833.0,213232.1] || -> node4(s21)*. % 76.30/76.41 213837[110:MRR:855.0,213835.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.30/76.41 213840[110:Res:53.1,213837.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.30/76.41 213842[111:Spt:213840.0] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 213844[111:Res:213842.0,61.1] always3(s21) || -> . % 76.30/76.41 213845[111:SSi:213844.0,78160.0,78163.0,192120.0,213231.0,213835.0] || -> . % 76.30/76.41 213846[111:Spt:213845.0,213840.0,213842.0] || m_main_v_state(s21,c_busy)* -> . % 76.30/76.41 213847[111:Spt:213845.0,213840.1] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 213851[111:Res:213847.0,61.1] always3(s22) || -> . % 76.30/76.41 213852[111:SSi:213851.0,78164.0,78168.0,192121.0] || -> . % 76.30/76.41 213853[109:Spt:213852.0,213230.0,213231.0] || until2p7(s21)*+ -> . % 76.30/76.41 213854[109:Spt:213852.0,213230.1] || -> node4(s20)*. % 76.30/76.41 213856[109:MRR:858.0,213854.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.30/76.41 213859[109:Res:53.1,213856.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.30/76.41 213861[110:Spt:213859.0] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 213863[110:Res:213861.0,61.1] always3(s20) || -> . % 76.30/76.41 213864[110:SSi:213863.0,78155.0,78159.0,192119.0,213229.0,213854.0] || -> . % 76.30/76.41 213865[110:Spt:213864.0,213859.0,213861.0] || m_main_v_state(s20,c_busy)* -> . % 76.30/76.41 213866[110:Spt:213864.0,213859.1] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 213870[110:Res:213866.0,61.1] always3(s21) || -> . % 76.30/76.41 213871[110:SSi:213870.0,78160.0,78163.0,192120.0] || -> . % 76.30/76.41 213872[108:Spt:213871.0,213228.0,213229.0] || until2p7(s20)*+ -> . % 76.30/76.41 213873[108:Spt:213871.0,213228.1] || -> node4(s19)*. % 76.30/76.41 213875[108:MRR:861.0,213873.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.30/76.41 213878[108:Res:53.1,213875.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.30/76.41 213883[109:Spt:213878.0] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 213885[109:Res:213883.0,61.1] always3(s19) || -> . % 76.30/76.41 213886[109:SSi:213885.0,78151.0,78154.0,192118.0,213227.0,213873.0] || -> . % 76.30/76.41 213887[109:Spt:213886.0,213878.0,213883.0] || m_main_v_state(s19,c_busy)* -> . % 76.30/76.41 213888[109:Spt:213886.0,213878.1] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 213892[109:Res:213888.0,61.1] always3(s20) || -> . % 76.30/76.41 213893[109:SSi:213892.0,78155.0,78159.0,192119.0] || -> . % 76.30/76.41 213894[107:Spt:213893.0,213226.0,213227.0] || until2p7(s19)*+ -> . % 76.30/76.41 213895[107:Spt:213893.0,213226.1] || -> node4(s18)*. % 76.30/76.41 213897[107:MRR:864.0,213895.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.30/76.41 213900[107:Res:53.1,213897.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.30/76.41 213902[108:Spt:213900.0] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 213904[108:Res:213902.0,61.1] always3(s18) || -> . % 76.30/76.41 213905[108:SSi:213904.0,78146.0,78150.0,192117.0,213225.0,213895.0] || -> . % 76.30/76.41 213906[108:Spt:213905.0,213900.0,213902.0] || m_main_v_state(s18,c_busy)* -> . % 76.30/76.41 213907[108:Spt:213905.0,213900.1] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 213911[108:Res:213907.0,61.1] always3(s19) || -> . % 76.30/76.41 213912[108:SSi:213911.0,78151.0,78154.0,192118.0] || -> . % 76.30/76.41 213913[106:Spt:213912.0,213224.0,213225.0] || until2p7(s18)*+ -> . % 76.30/76.41 213914[106:Spt:213912.0,213224.1] || -> node4(s17)*. % 76.30/76.41 213916[106:MRR:867.0,213914.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.30/76.41 213919[106:Res:53.1,213916.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.30/76.41 213921[107:Spt:213919.0] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 213923[107:Res:213921.0,61.1] always3(s17) || -> . % 76.30/76.41 213924[107:SSi:213923.0,78142.0,78145.0,192116.0,213223.0,213914.0] || -> . % 76.30/76.41 213925[107:Spt:213924.0,213919.0,213921.0] || m_main_v_state(s17,c_busy)* -> . % 76.30/76.41 213926[107:Spt:213924.0,213919.1] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 213930[107:Res:213926.0,61.1] always3(s18) || -> . % 76.30/76.41 213931[107:SSi:213930.0,78146.0,78150.0,192117.0] || -> . % 76.30/76.41 213932[105:Spt:213931.0,213222.0,213223.0] || until2p7(s17)*+ -> . % 76.30/76.41 213933[105:Spt:213931.0,213222.1] || -> node4(s16)*. % 76.30/76.41 213935[105:MRR:870.0,213933.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.30/76.41 213938[105:Res:53.1,213935.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.30/76.41 213940[106:Spt:213938.0] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 213942[106:Res:213940.0,61.1] always3(s16) || -> . % 76.30/76.41 213943[106:SSi:213942.0,78137.0,78141.0,192115.0,213221.0,213933.0] || -> . % 76.30/76.41 213944[106:Spt:213943.0,213938.0,213940.0] || m_main_v_state(s16,c_busy)* -> . % 76.30/76.41 213945[106:Spt:213943.0,213938.1] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 213949[106:Res:213945.0,61.1] always3(s17) || -> . % 76.30/76.41 213950[106:SSi:213949.0,78142.0,78145.0,192116.0] || -> . % 76.30/76.41 213951[104:Spt:213950.0,213220.0,213221.0] || until2p7(s16)*+ -> . % 76.30/76.41 213952[104:Spt:213950.0,213220.1] || -> node4(s15)*. % 76.30/76.41 213954[104:MRR:873.0,213952.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.30/76.41 213957[104:Res:53.1,213954.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.30/76.41 213962[105:Spt:213957.0] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 213964[105:Res:213962.0,61.1] always3(s15) || -> . % 76.30/76.41 213965[105:SSi:213964.0,78133.0,78136.0,192114.0,213219.0,213952.0] || -> . % 76.30/76.41 213966[105:Spt:213965.0,213957.0,213962.0] || m_main_v_state(s15,c_busy)* -> . % 76.30/76.41 213967[105:Spt:213965.0,213957.1] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 213971[105:Res:213967.0,61.1] always3(s16) || -> . % 76.30/76.41 213972[105:SSi:213971.0,78137.0,78141.0,192115.0] || -> . % 76.30/76.41 213973[103:Spt:213972.0,213218.0,213219.0] || until2p7(s15)*+ -> . % 76.30/76.41 213974[103:Spt:213972.0,213218.1] || -> node4(s14)*. % 76.30/76.41 213976[103:MRR:876.0,213974.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.30/76.41 213979[103:Res:53.1,213976.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.30/76.41 213981[104:Spt:213979.0] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 213983[104:Res:213981.0,61.1] always3(s14) || -> . % 76.30/76.41 213984[104:SSi:213983.0,78128.0,78132.0,192113.0,213217.0,213974.0] || -> . % 76.30/76.41 213985[104:Spt:213984.0,213979.0,213981.0] || m_main_v_state(s14,c_busy)* -> . % 76.30/76.41 213986[104:Spt:213984.0,213979.1] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 213990[104:Res:213986.0,61.1] always3(s15) || -> . % 76.30/76.41 213991[104:SSi:213990.0,78133.0,78136.0,192114.0] || -> . % 76.30/76.41 213992[102:Spt:213991.0,213216.0,213217.0] || until2p7(s14)*+ -> . % 76.30/76.41 213993[102:Spt:213991.0,213216.1] || -> node4(s13)*. % 76.30/76.41 213995[102:MRR:879.0,213993.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.30/76.41 213998[102:Res:53.1,213995.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.30/76.41 214000[103:Spt:213998.0] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 214002[103:Res:214000.0,61.1] always3(s13) || -> . % 76.30/76.41 214003[103:SSi:214002.0,78124.0,78127.0,192112.0,213215.0,213993.0] || -> . % 76.30/76.41 214004[103:Spt:214003.0,213998.0,214000.0] || m_main_v_state(s13,c_busy)* -> . % 76.30/76.41 214005[103:Spt:214003.0,213998.1] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 214009[103:Res:214005.0,61.1] always3(s14) || -> . % 76.30/76.41 214010[103:SSi:214009.0,78128.0,78132.0,192113.0] || -> . % 76.30/76.41 214011[101:Spt:214010.0,213214.0,213215.0] || until2p7(s13)*+ -> . % 76.30/76.41 214012[101:Spt:214010.0,213214.1] || -> node4(s12)*. % 76.30/76.41 214014[101:MRR:882.0,214012.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.30/76.41 214017[101:Res:53.1,214014.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.30/76.41 214019[102:Spt:214017.0] || -> m_main_v_state(s12,c_busy)*. % 76.30/76.41 214021[102:Res:214019.0,61.1] always3(s12) || -> . % 76.30/76.41 214022[102:SSi:214021.0,78119.0,78123.0,192111.0,213213.0,214012.0] || -> . % 76.30/76.41 214023[102:Spt:214022.0,214017.0,214019.0] || m_main_v_state(s12,c_busy)* -> . % 76.30/76.41 214024[102:Spt:214022.0,214017.1] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 214028[102:Res:214024.0,61.1] always3(s13) || -> . % 76.30/76.41 214029[102:SSi:214028.0,78124.0,78127.0,192112.0] || -> . % 76.30/76.41 214030[100:Spt:214029.0,213212.0,213213.0] || until2p7(s12)*+ -> . % 76.30/76.41 214031[100:Spt:214029.0,213212.1] || -> node4(s11)*. % 76.30/76.41 214033[100:MRR:885.0,214031.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.30/76.41 214036[100:Res:53.1,214033.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.30/76.41 214041[101:Spt:214036.0] || -> m_main_v_state(s11,c_busy)*. % 76.30/76.41 214043[101:Res:214041.0,61.1] always3(s11) || -> . % 76.30/76.41 214044[101:SSi:214043.0,78115.0,78118.0,192110.0,213211.0,214031.0] || -> . % 76.30/76.41 214045[101:Spt:214044.0,214036.0,214041.0] || m_main_v_state(s11,c_busy)* -> . % 76.30/76.41 214046[101:Spt:214044.0,214036.1] || -> m_main_v_state(s12,c_busy)*. % 76.30/76.41 214050[101:Res:214046.0,61.1] always3(s12) || -> . % 76.30/76.41 214051[101:SSi:214050.0,78119.0,78123.0,192111.0] || -> . % 76.30/76.41 214052[99:Spt:214051.0,213210.0,213211.0] || until2p7(s11)*+ -> . % 76.30/76.41 214053[99:Spt:214051.0,213210.1] || -> node4(s10)*. % 76.30/76.41 214055[99:MRR:888.0,214053.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.30/76.41 214058[99:Res:53.1,214055.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.30/76.41 214060[100:Spt:214058.0] || -> m_main_v_state(s10,c_busy)*. % 76.30/76.41 214062[100:Res:214060.0,61.1] always3(s10) || -> . % 76.30/76.41 214063[100:SSi:214062.0,78110.0,78114.0,192109.0,213209.0,214053.0] || -> . % 76.30/76.41 214064[100:Spt:214063.0,214058.0,214060.0] || m_main_v_state(s10,c_busy)* -> . % 76.30/76.41 214065[100:Spt:214063.0,214058.1] || -> m_main_v_state(s11,c_busy)*. % 76.30/76.41 214069[100:Res:214065.0,61.1] always3(s11) || -> . % 76.30/76.41 214070[100:SSi:214069.0,78115.0,78118.0,192110.0] || -> . % 76.30/76.41 214071[98:Spt:214070.0,213208.0,213209.0] || until2p7(s10)*+ -> . % 76.30/76.41 214072[98:Spt:214070.0,213208.1] || -> node4(s9)*. % 76.30/76.41 214074[98:MRR:891.0,214072.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.30/76.41 214077[98:Res:53.1,214074.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.30/76.41 214079[98:MRR:214077.0,213198.0] || -> m_main_v_state(s10,c_busy)*. % 76.30/76.41 214081[98:Res:214079.0,61.1] always3(s10) || -> . % 76.30/76.41 214082[98:SSi:214081.0,78110.0,78114.0,192109.0] || -> . % 76.30/76.41 214083[96:Spt:214082.0,213049.0,213052.0] || trans(s49,s9)*+ -> . % 76.30/76.41 214084[96:Spt:214082.0,213049.1,213049.2,213049.3] || -> trans(s49,s8) trans(s49,s7) node2(s49,s6)*. % 76.30/76.41 214086[96:MRR:213051.1,214083.0] xuntil6(s49) || -> trans(s49,s8) trans(s49,s7)* until2p7(s6). % 76.30/76.41 214087[97:Spt:214084.0] || -> trans(s49,s8)*. % 76.30/76.41 214088[97:Res:214087.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s8)*. % 76.30/76.41 214090[97:Res:214087.0,60.0] || -> node2(s49,s8)*. % 76.30/76.41 214091[97:SSi:214088.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s8)*. % 76.30/76.41 214092[97:Res:214090.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)*. % 76.30/76.41 214229[97:SoR:214092.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)*. % 76.30/76.41 214231[97:SoR:214229.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s8,c_busy)* xuntil6(s49). % 76.30/76.41 214232[97:SSi:214231.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s8,c_busy)* xuntil6(s49). % 76.30/76.41 214233[98:Spt:214232.1] || -> m_main_v_state(s8,c_busy)*. % 76.30/76.41 214235[98:Res:214233.0,61.1] always3(s8) || -> . % 76.30/76.41 214236[98:SSi:214235.0,78101.0,78105.0,192107.0] || -> . % 76.30/76.41 214237[98:Spt:214236.0,214232.1,214233.0] || m_main_v_state(s8,c_busy)*+ -> . % 76.30/76.41 214238[98:Spt:214236.0,214232.0,214232.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 214242[98:MRR:214229.2,214237.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 214243[98:Res:53.1,214238.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 214245[98:MRR:214243.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 214246[98:MRR:214091.0,214245.0] || -> until2p7(s8)*. % 76.30/76.41 214247[98:MRR:204.0,214246.0] || -> until2p7(s9)* node4(s8). % 76.30/76.41 214248[99:Spt:214247.0] || -> until2p7(s9)*. % 76.30/76.41 214249[99:MRR:205.0,214248.0] || -> until2p7(s10)* node4(s9). % 76.30/76.41 214250[100:Spt:214249.0] || -> until2p7(s10)*. % 76.30/76.41 214251[100:MRR:206.0,214250.0] || -> until2p7(s11)* node4(s10). % 76.30/76.41 214252[101:Spt:214251.0] || -> until2p7(s11)*. % 76.30/76.41 214253[101:MRR:207.0,214252.0] || -> until2p7(s12)* node4(s11). % 76.30/76.41 214254[102:Spt:214253.0] || -> until2p7(s12)*. % 76.30/76.41 214255[102:MRR:208.0,214254.0] || -> until2p7(s13)* node4(s12). % 76.30/76.41 214256[103:Spt:214255.0] || -> until2p7(s13)*. % 76.30/76.41 214257[103:MRR:209.0,214256.0] || -> until2p7(s14)* node4(s13). % 76.30/76.41 214258[104:Spt:214257.0] || -> until2p7(s14)*. % 76.30/76.41 214259[104:MRR:210.0,214258.0] || -> until2p7(s15)* node4(s14). % 76.30/76.41 214260[105:Spt:214259.0] || -> until2p7(s15)*. % 76.30/76.41 214261[105:MRR:211.0,214260.0] || -> until2p7(s16)* node4(s15). % 76.30/76.41 214262[106:Spt:214261.0] || -> until2p7(s16)*. % 76.30/76.41 214263[106:MRR:212.0,214262.0] || -> until2p7(s17)* node4(s16). % 76.30/76.41 214264[107:Spt:214263.0] || -> until2p7(s17)*. % 76.30/76.41 214265[107:MRR:213.0,214264.0] || -> until2p7(s18)* node4(s17). % 76.30/76.41 214266[108:Spt:214265.0] || -> until2p7(s18)*. % 76.30/76.41 214267[108:MRR:214.0,214266.0] || -> until2p7(s19)* node4(s18). % 76.30/76.41 214268[109:Spt:214267.0] || -> until2p7(s19)*. % 76.30/76.41 214269[109:MRR:215.0,214268.0] || -> until2p7(s20)* node4(s19). % 76.30/76.41 214270[110:Spt:214269.0] || -> until2p7(s20)*. % 76.30/76.41 214271[110:MRR:216.0,214270.0] || -> until2p7(s21)* node4(s20). % 76.30/76.41 214272[111:Spt:214271.0] || -> until2p7(s21)*. % 76.30/76.41 214273[111:MRR:217.0,214272.0] || -> until2p7(s22)* node4(s21). % 76.30/76.41 214274[112:Spt:214273.0] || -> until2p7(s22)*. % 76.30/76.41 214275[112:MRR:218.0,214274.0] || -> until2p7(s23)* node4(s22). % 76.30/76.41 214276[113:Spt:214275.0] || -> until2p7(s23)*. % 76.30/76.41 214277[113:MRR:219.0,214276.0] || -> until2p7(s24)* node4(s23). % 76.30/76.41 214278[114:Spt:214277.0] || -> until2p7(s24)*. % 76.30/76.41 214279[114:MRR:220.0,214278.0] || -> until2p7(s25)* node4(s24). % 76.30/76.41 214280[115:Spt:214279.0] || -> until2p7(s25)*. % 76.30/76.41 214281[115:MRR:221.0,214280.0] || -> until2p7(s26)* node4(s25). % 76.30/76.41 214282[116:Spt:214281.0] || -> until2p7(s26)*. % 76.30/76.41 214283[116:MRR:222.0,214282.0] || -> until2p7(s27)* node4(s26). % 76.30/76.41 214284[117:Spt:214283.0] || -> until2p7(s27)*. % 76.30/76.41 214285[117:MRR:223.0,214284.0] || -> until2p7(s28)* node4(s27). % 76.30/76.41 214286[118:Spt:214285.0] || -> until2p7(s28)*. % 76.30/76.41 214287[118:MRR:224.0,214286.0] || -> until2p7(s29)* node4(s28). % 76.30/76.41 214288[119:Spt:214287.0] || -> until2p7(s29)*. % 76.30/76.41 214289[119:MRR:225.0,214288.0] || -> until2p7(s30)* node4(s29). % 76.30/76.41 214290[120:Spt:214289.0] || -> until2p7(s30)*. % 76.30/76.41 214291[120:MRR:226.0,214290.0] || -> until2p7(s31)* node4(s30). % 76.30/76.41 214292[121:Spt:214291.0] || -> until2p7(s31)*. % 76.30/76.41 214293[121:MRR:227.0,214292.0] || -> until2p7(s32)* node4(s31). % 76.30/76.41 214294[122:Spt:214293.0] || -> until2p7(s32)*. % 76.30/76.41 214295[122:MRR:228.0,214294.0] || -> until2p7(s33)* node4(s32). % 76.30/76.41 214296[123:Spt:214295.0] || -> until2p7(s33)*. % 76.30/76.41 214297[123:MRR:229.0,214296.0] || -> until2p7(s34)* node4(s33). % 76.30/76.41 214298[124:Spt:214297.0] || -> until2p7(s34)*. % 76.30/76.41 214299[124:MRR:230.0,214298.0] || -> until2p7(s35)* node4(s34). % 76.30/76.41 214300[125:Spt:214299.0] || -> until2p7(s35)*. % 76.30/76.41 214301[125:MRR:231.0,214300.0] || -> until2p7(s36)* node4(s35). % 76.30/76.41 214302[126:Spt:214301.0] || -> until2p7(s36)*. % 76.30/76.41 214303[126:MRR:232.0,214302.0] || -> until2p7(s37)* node4(s36). % 76.30/76.41 214304[127:Spt:214303.0] || -> until2p7(s37)*. % 76.30/76.41 214305[127:MRR:235.0,214304.0] || -> until2p7(s38)* node4(s37). % 76.30/76.41 214306[128:Spt:214305.0] || -> until2p7(s38)*. % 76.30/76.41 214307[128:MRR:236.0,214306.0] || -> until2p7(s39)* node4(s38). % 76.30/76.41 214308[129:Spt:214307.0] || -> until2p7(s39)*. % 76.30/76.41 214309[129:MRR:237.0,214308.0] || -> until2p7(s40)* node4(s39). % 76.30/76.41 214310[130:Spt:214309.0] || -> until2p7(s40)*. % 76.30/76.41 214311[130:MRR:238.0,214310.0] || -> until2p7(s41)* node4(s40). % 76.30/76.41 214312[131:Spt:214311.0] || -> until2p7(s41)*. % 76.30/76.41 214313[131:MRR:239.0,214312.0] || -> until2p7(s42)* node4(s41). % 76.30/76.41 214314[132:Spt:214313.0] || -> until2p7(s42)*. % 76.30/76.41 214315[132:MRR:240.0,214314.0] || -> until2p7(s43)* node4(s42). % 76.30/76.41 214316[133:Spt:214315.0] || -> until2p7(s43)*. % 76.30/76.41 214317[133:MRR:241.0,214316.0] || -> until2p7(s44)* node4(s43). % 76.30/76.41 214318[134:Spt:214317.0] || -> until2p7(s44)*. % 76.30/76.41 214319[134:MRR:539.0,214318.0] || -> until2p7(s45)* node4(s44). % 76.30/76.41 214320[135:Spt:214319.0] || -> until2p7(s45)*. % 76.30/76.41 214321[135:MRR:544.0,214320.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 214322[136:Spt:214321.0] || -> until2p7(s46)*. % 76.30/76.41 214323[136:MRR:549.0,214322.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 214324[137:Spt:214323.0] || -> until2p7(s47)*. % 76.30/76.41 214325[137:MRR:554.0,214324.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 214326[138:Spt:214325.0] || -> until2p7(s48)*. % 76.30/76.41 214327[138:MRR:559.0,214326.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 214328[139:Spt:214327.0] || -> until2p7(s49)*. % 76.30/76.41 214329[139:MRR:194.0,214328.0] || -> node4(s49)*. % 76.30/76.41 214330[139:MRR:214242.0,214329.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 214334[139:Res:53.1,214330.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 214336[139:MRR:214334.0,78381.0] || -> . % 76.30/76.41 214337[139:Spt:214336.0,214327.0,214328.0] || until2p7(s49)*+ -> . % 76.30/76.41 214338[139:Spt:214336.0,214327.1] || -> node4(s48)*. % 76.30/76.41 214339[139:MRR:78384.0,214338.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 214342[139:Res:53.1,214339.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 214345[139:Res:214342.0,61.1] always3(s48) || -> . % 76.30/76.41 214346[139:SSi:214345.0,78281.0,78387.0,192147.0,214326.0,214338.0] || -> . % 76.30/76.41 214347[138:Spt:214346.0,214325.0,214326.0] || until2p7(s48)*+ -> . % 76.30/76.41 214348[138:Spt:214346.0,214325.1] || -> node4(s47)*. % 76.30/76.41 214350[138:MRR:777.0,214348.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 214362[138:Res:53.1,214350.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 214364[139:Spt:214362.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 214366[139:Res:214364.0,61.1] always3(s47) || -> . % 76.30/76.41 214367[139:SSi:214366.0,78277.0,78280.0,192146.0,214324.0,214348.0] || -> . % 76.30/76.41 214368[139:Spt:214367.0,214362.0,214364.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 214369[139:Spt:214367.0,214362.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 214373[139:Res:214369.0,61.1] always3(s48) || -> . % 76.30/76.41 214374[139:SSi:214373.0,78281.0,78387.0,192147.0] || -> . % 76.30/76.41 214375[137:Spt:214374.0,214323.0,214324.0] || until2p7(s47)*+ -> . % 76.30/76.41 214376[137:Spt:214374.0,214323.1] || -> node4(s46)*. % 76.30/76.41 214378[137:MRR:780.0,214376.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 214385[137:Res:53.1,214378.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 214390[138:Spt:214385.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 214392[138:Res:214390.0,61.1] always3(s46) || -> . % 76.30/76.41 214393[138:SSi:214392.0,78272.0,78276.0,192145.0,214322.0,214376.0] || -> . % 76.30/76.41 214394[138:Spt:214393.0,214385.0,214390.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 214395[138:Spt:214393.0,214385.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 214399[138:Res:214395.0,61.1] always3(s47) || -> . % 76.30/76.41 214400[138:SSi:214399.0,78277.0,78280.0,192146.0] || -> . % 76.30/76.41 214401[136:Spt:214400.0,214321.0,214322.0] || until2p7(s46)*+ -> . % 76.30/76.41 214402[136:Spt:214400.0,214321.1] || -> node4(s45)*. % 76.30/76.41 214404[136:MRR:783.0,214402.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 214407[136:Res:53.1,214404.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 214409[137:Spt:214407.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 214411[137:Res:214409.0,61.1] always3(s45) || -> . % 76.30/76.41 214412[137:SSi:214411.0,78268.0,78271.0,192144.0,214320.0,214402.0] || -> . % 76.30/76.41 214413[137:Spt:214412.0,214407.0,214409.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.41 214414[137:Spt:214412.0,214407.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 214418[137:Res:214414.0,61.1] always3(s46) || -> . % 76.30/76.41 214419[137:SSi:214418.0,78272.0,78276.0,192145.0] || -> . % 76.30/76.41 214420[135:Spt:214419.0,214319.0,214320.0] || until2p7(s45)*+ -> . % 76.30/76.41 214421[135:Spt:214419.0,214319.1] || -> node4(s44)*. % 76.30/76.41 214423[135:MRR:786.0,214421.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.41 214426[135:Res:53.1,214423.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.41 214428[136:Spt:214426.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 214430[136:Res:214428.0,61.1] always3(s44) || -> . % 76.30/76.41 214431[136:SSi:214430.0,78263.0,78267.0,192143.0,214318.0,214421.0] || -> . % 76.30/76.41 214432[136:Spt:214431.0,214426.0,214428.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.41 214433[136:Spt:214431.0,214426.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 214437[136:Res:214433.0,61.1] always3(s45) || -> . % 76.30/76.41 214438[136:SSi:214437.0,78268.0,78271.0,192144.0] || -> . % 76.30/76.41 214439[134:Spt:214438.0,214317.0,214318.0] || until2p7(s44)*+ -> . % 76.30/76.41 214440[134:Spt:214438.0,214317.1] || -> node4(s43)*. % 76.30/76.41 214442[134:MRR:789.0,214440.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.41 214445[134:Res:53.1,214442.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.41 214447[135:Spt:214445.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 214449[135:Res:214447.0,61.1] always3(s43) || -> . % 76.30/76.41 214450[135:SSi:214449.0,78259.0,78262.0,192142.0,214316.0,214440.0] || -> . % 76.30/76.41 214451[135:Spt:214450.0,214445.0,214447.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.41 214452[135:Spt:214450.0,214445.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 214456[135:Res:214452.0,61.1] always3(s44) || -> . % 76.30/76.41 214457[135:SSi:214456.0,78263.0,78267.0,192143.0] || -> . % 76.30/76.41 214458[133:Spt:214457.0,214315.0,214316.0] || until2p7(s43)*+ -> . % 76.30/76.41 214459[133:Spt:214457.0,214315.1] || -> node4(s42)*. % 76.30/76.41 214461[133:MRR:792.0,214459.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.41 214464[133:Res:53.1,214461.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.41 214469[134:Spt:214464.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 214471[134:Res:214469.0,61.1] always3(s42) || -> . % 76.30/76.41 214472[134:SSi:214471.0,78254.0,78258.0,192141.0,214314.0,214459.0] || -> . % 76.30/76.41 214473[134:Spt:214472.0,214464.0,214469.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.41 214474[134:Spt:214472.0,214464.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 214478[134:Res:214474.0,61.1] always3(s43) || -> . % 76.30/76.41 214479[134:SSi:214478.0,78259.0,78262.0,192142.0] || -> . % 76.30/76.41 214480[132:Spt:214479.0,214313.0,214314.0] || until2p7(s42)*+ -> . % 76.30/76.41 214481[132:Spt:214479.0,214313.1] || -> node4(s41)*. % 76.30/76.41 214483[132:MRR:795.0,214481.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.41 214486[132:Res:53.1,214483.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.41 214488[133:Spt:214486.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 214490[133:Res:214488.0,61.1] always3(s41) || -> . % 76.30/76.41 214491[133:SSi:214490.0,78250.0,78253.0,192140.0,214312.0,214481.0] || -> . % 76.30/76.41 214492[133:Spt:214491.0,214486.0,214488.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.41 214493[133:Spt:214491.0,214486.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 214497[133:Res:214493.0,61.1] always3(s42) || -> . % 76.30/76.41 214498[133:SSi:214497.0,78254.0,78258.0,192141.0] || -> . % 76.30/76.41 214499[131:Spt:214498.0,214311.0,214312.0] || until2p7(s41)*+ -> . % 76.30/76.41 214500[131:Spt:214498.0,214311.1] || -> node4(s40)*. % 76.30/76.41 214502[131:MRR:798.0,214500.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.41 214505[131:Res:53.1,214502.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.41 214507[132:Spt:214505.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 214509[132:Res:214507.0,61.1] always3(s40) || -> . % 76.30/76.41 214510[132:SSi:214509.0,78245.0,78249.0,192139.0,214310.0,214500.0] || -> . % 76.30/76.41 214511[132:Spt:214510.0,214505.0,214507.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.41 214512[132:Spt:214510.0,214505.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 214516[132:Res:214512.0,61.1] always3(s41) || -> . % 76.30/76.41 214517[132:SSi:214516.0,78250.0,78253.0,192140.0] || -> . % 76.30/76.41 214518[130:Spt:214517.0,214309.0,214310.0] || until2p7(s40)*+ -> . % 76.30/76.41 214519[130:Spt:214517.0,214309.1] || -> node4(s39)*. % 76.30/76.41 214521[130:MRR:801.0,214519.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.41 214524[130:Res:53.1,214521.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.41 214526[131:Spt:214524.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 214528[131:Res:214526.0,61.1] always3(s39) || -> . % 76.30/76.41 214529[131:SSi:214528.0,78241.0,78244.0,192138.0,214308.0,214519.0] || -> . % 76.30/76.41 214530[131:Spt:214529.0,214524.0,214526.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.41 214531[131:Spt:214529.0,214524.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 214535[131:Res:214531.0,61.1] always3(s40) || -> . % 76.30/76.41 214536[131:SSi:214535.0,78245.0,78249.0,192139.0] || -> . % 76.30/76.41 214537[129:Spt:214536.0,214307.0,214308.0] || until2p7(s39)*+ -> . % 76.30/76.41 214538[129:Spt:214536.0,214307.1] || -> node4(s38)*. % 76.30/76.41 214540[129:MRR:804.0,214538.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.41 214543[129:Res:53.1,214540.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.41 214548[130:Spt:214543.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 214550[130:Res:214548.0,61.1] always3(s38) || -> . % 76.30/76.41 214551[130:SSi:214550.0,78236.0,78240.0,192137.0,214306.0,214538.0] || -> . % 76.30/76.41 214552[130:Spt:214551.0,214543.0,214548.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.41 214553[130:Spt:214551.0,214543.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 214557[130:Res:214553.0,61.1] always3(s39) || -> . % 76.30/76.41 214558[130:SSi:214557.0,78241.0,78244.0,192138.0] || -> . % 76.30/76.41 214559[128:Spt:214558.0,214305.0,214306.0] || until2p7(s38)*+ -> . % 76.30/76.41 214560[128:Spt:214558.0,214305.1] || -> node4(s37)*. % 76.30/76.41 214562[128:MRR:807.0,214560.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.41 214565[128:Res:53.1,214562.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.41 214567[129:Spt:214565.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 214569[129:Res:214567.0,61.1] always3(s37) || -> . % 76.30/76.41 214570[129:SSi:214569.0,78232.0,78235.0,192136.0,214304.0,214560.0] || -> . % 76.30/76.41 214571[129:Spt:214570.0,214565.0,214567.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.41 214572[129:Spt:214570.0,214565.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 214576[129:Res:214572.0,61.1] always3(s38) || -> . % 76.30/76.41 214577[129:SSi:214576.0,78236.0,78240.0,192137.0] || -> . % 76.30/76.41 214578[127:Spt:214577.0,214303.0,214304.0] || until2p7(s37)*+ -> . % 76.30/76.41 214579[127:Spt:214577.0,214303.1] || -> node4(s36)*. % 76.30/76.41 214581[127:MRR:810.0,214579.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.41 214584[127:Res:53.1,214581.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.41 214586[128:Spt:214584.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 214588[128:Res:214586.0,61.1] always3(s36) || -> . % 76.30/76.41 214589[128:SSi:214588.0,78227.0,78231.0,192135.0,214302.0,214579.0] || -> . % 76.30/76.41 214590[128:Spt:214589.0,214584.0,214586.0] || m_main_v_state(s36,c_busy)* -> . % 76.30/76.41 214591[128:Spt:214589.0,214584.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 214595[128:Res:214591.0,61.1] always3(s37) || -> . % 76.30/76.41 214596[128:SSi:214595.0,78232.0,78235.0,192136.0] || -> . % 76.30/76.41 214597[126:Spt:214596.0,214301.0,214302.0] || until2p7(s36)*+ -> . % 76.30/76.41 214598[126:Spt:214596.0,214301.1] || -> node4(s35)*. % 76.30/76.41 214600[126:MRR:813.0,214598.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.30/76.41 214603[126:Res:53.1,214600.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.30/76.41 214605[127:Spt:214603.0] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 214607[127:Res:214605.0,61.1] always3(s35) || -> . % 76.30/76.41 214608[127:SSi:214607.0,78223.0,78226.0,192134.0,214300.0,214598.0] || -> . % 76.30/76.41 214609[127:Spt:214608.0,214603.0,214605.0] || m_main_v_state(s35,c_busy)* -> . % 76.30/76.41 214610[127:Spt:214608.0,214603.1] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 214614[127:Res:214610.0,61.1] always3(s36) || -> . % 76.30/76.41 214615[127:SSi:214614.0,78227.0,78231.0,192135.0] || -> . % 76.30/76.41 214616[125:Spt:214615.0,214299.0,214300.0] || until2p7(s35)*+ -> . % 76.30/76.41 214617[125:Spt:214615.0,214299.1] || -> node4(s34)*. % 76.30/76.41 214619[125:MRR:816.0,214617.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.30/76.41 214622[125:Res:53.1,214619.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.30/76.41 214627[126:Spt:214622.0] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 214629[126:Res:214627.0,61.1] always3(s34) || -> . % 76.30/76.41 214630[126:SSi:214629.0,78218.0,78222.0,192133.0,214298.0,214617.0] || -> . % 76.30/76.41 214631[126:Spt:214630.0,214622.0,214627.0] || m_main_v_state(s34,c_busy)* -> . % 76.30/76.41 214632[126:Spt:214630.0,214622.1] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 214636[126:Res:214632.0,61.1] always3(s35) || -> . % 76.30/76.41 214637[126:SSi:214636.0,78223.0,78226.0,192134.0] || -> . % 76.30/76.41 214638[124:Spt:214637.0,214297.0,214298.0] || until2p7(s34)*+ -> . % 76.30/76.41 214639[124:Spt:214637.0,214297.1] || -> node4(s33)*. % 76.30/76.41 214641[124:MRR:819.0,214639.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.30/76.41 214644[124:Res:53.1,214641.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.30/76.41 214646[125:Spt:214644.0] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 214648[125:Res:214646.0,61.1] always3(s33) || -> . % 76.30/76.41 214649[125:SSi:214648.0,78214.0,78217.0,192132.0,214296.0,214639.0] || -> . % 76.30/76.41 214650[125:Spt:214649.0,214644.0,214646.0] || m_main_v_state(s33,c_busy)* -> . % 76.30/76.41 214651[125:Spt:214649.0,214644.1] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 214655[125:Res:214651.0,61.1] always3(s34) || -> . % 76.30/76.41 214656[125:SSi:214655.0,78218.0,78222.0,192133.0] || -> . % 76.30/76.41 214657[123:Spt:214656.0,214295.0,214296.0] || until2p7(s33)*+ -> . % 76.30/76.41 214658[123:Spt:214656.0,214295.1] || -> node4(s32)*. % 76.30/76.41 214660[123:MRR:822.0,214658.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.30/76.41 214663[123:Res:53.1,214660.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.30/76.41 214665[124:Spt:214663.0] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 214667[124:Res:214665.0,61.1] always3(s32) || -> . % 76.30/76.41 214668[124:SSi:214667.0,78209.0,78213.0,192131.0,214294.0,214658.0] || -> . % 76.30/76.41 214669[124:Spt:214668.0,214663.0,214665.0] || m_main_v_state(s32,c_busy)* -> . % 76.30/76.41 214670[124:Spt:214668.0,214663.1] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 214674[124:Res:214670.0,61.1] always3(s33) || -> . % 76.30/76.41 214675[124:SSi:214674.0,78214.0,78217.0,192132.0] || -> . % 76.30/76.41 214676[122:Spt:214675.0,214293.0,214294.0] || until2p7(s32)*+ -> . % 76.30/76.41 214677[122:Spt:214675.0,214293.1] || -> node4(s31)*. % 76.30/76.41 214679[122:MRR:825.0,214677.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.30/76.41 214682[122:Res:53.1,214679.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.30/76.41 214684[123:Spt:214682.0] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 214686[123:Res:214684.0,61.1] always3(s31) || -> . % 76.30/76.41 214687[123:SSi:214686.0,78205.0,78208.0,192130.0,214292.0,214677.0] || -> . % 76.30/76.41 214688[123:Spt:214687.0,214682.0,214684.0] || m_main_v_state(s31,c_busy)* -> . % 76.30/76.41 214689[123:Spt:214687.0,214682.1] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 214693[123:Res:214689.0,61.1] always3(s32) || -> . % 76.30/76.41 214694[123:SSi:214693.0,78209.0,78213.0,192131.0] || -> . % 76.30/76.41 214695[121:Spt:214694.0,214291.0,214292.0] || until2p7(s31)*+ -> . % 76.30/76.41 214696[121:Spt:214694.0,214291.1] || -> node4(s30)*. % 76.30/76.41 214698[121:MRR:828.0,214696.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.30/76.41 214701[121:Res:53.1,214698.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.30/76.41 214706[122:Spt:214701.0] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 214708[122:Res:214706.0,61.1] always3(s30) || -> . % 76.30/76.41 214709[122:SSi:214708.0,78200.0,78204.0,192129.0,214290.0,214696.0] || -> . % 76.30/76.41 214710[122:Spt:214709.0,214701.0,214706.0] || m_main_v_state(s30,c_busy)* -> . % 76.30/76.41 214711[122:Spt:214709.0,214701.1] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 214715[122:Res:214711.0,61.1] always3(s31) || -> . % 76.30/76.41 214716[122:SSi:214715.0,78205.0,78208.0,192130.0] || -> . % 76.30/76.41 214717[120:Spt:214716.0,214289.0,214290.0] || until2p7(s30)*+ -> . % 76.30/76.41 214718[120:Spt:214716.0,214289.1] || -> node4(s29)*. % 76.30/76.41 214720[120:MRR:831.0,214718.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.30/76.41 214723[120:Res:53.1,214720.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.30/76.41 214725[121:Spt:214723.0] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 214727[121:Res:214725.0,61.1] always3(s29) || -> . % 76.30/76.41 214728[121:SSi:214727.0,78196.0,78199.0,192128.0,214288.0,214718.0] || -> . % 76.30/76.41 214729[121:Spt:214728.0,214723.0,214725.0] || m_main_v_state(s29,c_busy)* -> . % 76.30/76.41 214730[121:Spt:214728.0,214723.1] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 214734[121:Res:214730.0,61.1] always3(s30) || -> . % 76.30/76.41 214735[121:SSi:214734.0,78200.0,78204.0,192129.0] || -> . % 76.30/76.41 214736[119:Spt:214735.0,214287.0,214288.0] || until2p7(s29)*+ -> . % 76.30/76.41 214737[119:Spt:214735.0,214287.1] || -> node4(s28)*. % 76.30/76.41 214739[119:MRR:834.0,214737.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.30/76.41 214742[119:Res:53.1,214739.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.30/76.41 214744[120:Spt:214742.0] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 214746[120:Res:214744.0,61.1] always3(s28) || -> . % 76.30/76.41 214747[120:SSi:214746.0,78191.0,78195.0,192127.0,214286.0,214737.0] || -> . % 76.30/76.41 214748[120:Spt:214747.0,214742.0,214744.0] || m_main_v_state(s28,c_busy)* -> . % 76.30/76.41 214749[120:Spt:214747.0,214742.1] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 214753[120:Res:214749.0,61.1] always3(s29) || -> . % 76.30/76.41 214754[120:SSi:214753.0,78196.0,78199.0,192128.0] || -> . % 76.30/76.41 214755[118:Spt:214754.0,214285.0,214286.0] || until2p7(s28)*+ -> . % 76.30/76.41 214756[118:Spt:214754.0,214285.1] || -> node4(s27)*. % 76.30/76.41 214758[118:MRR:837.0,214756.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.30/76.41 214761[118:Res:53.1,214758.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.30/76.41 214763[119:Spt:214761.0] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 214765[119:Res:214763.0,61.1] always3(s27) || -> . % 76.30/76.41 214766[119:SSi:214765.0,78187.0,78190.0,192126.0,214284.0,214756.0] || -> . % 76.30/76.41 214767[119:Spt:214766.0,214761.0,214763.0] || m_main_v_state(s27,c_busy)* -> . % 76.30/76.41 214768[119:Spt:214766.0,214761.1] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 214772[119:Res:214768.0,61.1] always3(s28) || -> . % 76.30/76.41 214773[119:SSi:214772.0,78191.0,78195.0,192127.0] || -> . % 76.30/76.41 214774[117:Spt:214773.0,214283.0,214284.0] || until2p7(s27)*+ -> . % 76.30/76.41 214775[117:Spt:214773.0,214283.1] || -> node4(s26)*. % 76.30/76.41 214777[117:MRR:840.0,214775.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.30/76.41 214780[117:Res:53.1,214777.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.30/76.41 214785[118:Spt:214780.0] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 214787[118:Res:214785.0,61.1] always3(s26) || -> . % 76.30/76.41 214788[118:SSi:214787.0,78182.0,78186.0,192125.0,214282.0,214775.0] || -> . % 76.30/76.41 214789[118:Spt:214788.0,214780.0,214785.0] || m_main_v_state(s26,c_busy)* -> . % 76.30/76.41 214790[118:Spt:214788.0,214780.1] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 214794[118:Res:214790.0,61.1] always3(s27) || -> . % 76.30/76.41 214795[118:SSi:214794.0,78187.0,78190.0,192126.0] || -> . % 76.30/76.41 214796[116:Spt:214795.0,214281.0,214282.0] || until2p7(s26)*+ -> . % 76.30/76.41 214797[116:Spt:214795.0,214281.1] || -> node4(s25)*. % 76.30/76.41 214799[116:MRR:843.0,214797.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.30/76.41 214802[116:Res:53.1,214799.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.30/76.41 214804[117:Spt:214802.0] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 214806[117:Res:214804.0,61.1] always3(s25) || -> . % 76.30/76.41 214807[117:SSi:214806.0,78178.0,78181.0,192124.0,214280.0,214797.0] || -> . % 76.30/76.41 214808[117:Spt:214807.0,214802.0,214804.0] || m_main_v_state(s25,c_busy)* -> . % 76.30/76.41 214809[117:Spt:214807.0,214802.1] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 214813[117:Res:214809.0,61.1] always3(s26) || -> . % 76.30/76.41 214814[117:SSi:214813.0,78182.0,78186.0,192125.0] || -> . % 76.30/76.41 214815[115:Spt:214814.0,214279.0,214280.0] || until2p7(s25)*+ -> . % 76.30/76.41 214816[115:Spt:214814.0,214279.1] || -> node4(s24)*. % 76.30/76.41 214818[115:MRR:846.0,214816.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.30/76.41 214821[115:Res:53.1,214818.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.30/76.41 214823[116:Spt:214821.0] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 214825[116:Res:214823.0,61.1] always3(s24) || -> . % 76.30/76.41 214826[116:SSi:214825.0,78173.0,78177.0,192123.0,214278.0,214816.0] || -> . % 76.30/76.41 214827[116:Spt:214826.0,214821.0,214823.0] || m_main_v_state(s24,c_busy)* -> . % 76.30/76.41 214828[116:Spt:214826.0,214821.1] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 214832[116:Res:214828.0,61.1] always3(s25) || -> . % 76.30/76.41 214833[116:SSi:214832.0,78178.0,78181.0,192124.0] || -> . % 76.30/76.41 214834[114:Spt:214833.0,214277.0,214278.0] || until2p7(s24)*+ -> . % 76.30/76.41 214835[114:Spt:214833.0,214277.1] || -> node4(s23)*. % 76.30/76.41 214837[114:MRR:849.0,214835.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.30/76.41 214840[114:Res:53.1,214837.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.30/76.41 214842[115:Spt:214840.0] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 214844[115:Res:214842.0,61.1] always3(s23) || -> . % 76.30/76.41 214845[115:SSi:214844.0,78169.0,78172.0,192122.0,214276.0,214835.0] || -> . % 76.30/76.41 214846[115:Spt:214845.0,214840.0,214842.0] || m_main_v_state(s23,c_busy)* -> . % 76.30/76.41 214847[115:Spt:214845.0,214840.1] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 214851[115:Res:214847.0,61.1] always3(s24) || -> . % 76.30/76.41 214852[115:SSi:214851.0,78173.0,78177.0,192123.0] || -> . % 76.30/76.41 214853[113:Spt:214852.0,214275.0,214276.0] || until2p7(s23)*+ -> . % 76.30/76.41 214854[113:Spt:214852.0,214275.1] || -> node4(s22)*. % 76.30/76.41 214856[113:MRR:852.0,214854.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.30/76.41 214859[113:Res:53.1,214856.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.30/76.41 214864[114:Spt:214859.0] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 214866[114:Res:214864.0,61.1] always3(s22) || -> . % 76.30/76.41 214867[114:SSi:214866.0,78164.0,78168.0,192121.0,214274.0,214854.0] || -> . % 76.30/76.41 214868[114:Spt:214867.0,214859.0,214864.0] || m_main_v_state(s22,c_busy)* -> . % 76.30/76.41 214869[114:Spt:214867.0,214859.1] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 214873[114:Res:214869.0,61.1] always3(s23) || -> . % 76.30/76.41 214874[114:SSi:214873.0,78169.0,78172.0,192122.0] || -> . % 76.30/76.41 214875[112:Spt:214874.0,214273.0,214274.0] || until2p7(s22)*+ -> . % 76.30/76.41 214876[112:Spt:214874.0,214273.1] || -> node4(s21)*. % 76.30/76.41 214878[112:MRR:855.0,214876.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.30/76.41 214881[112:Res:53.1,214878.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.30/76.41 214883[113:Spt:214881.0] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 214885[113:Res:214883.0,61.1] always3(s21) || -> . % 76.30/76.41 214886[113:SSi:214885.0,78160.0,78163.0,192120.0,214272.0,214876.0] || -> . % 76.30/76.41 214887[113:Spt:214886.0,214881.0,214883.0] || m_main_v_state(s21,c_busy)* -> . % 76.30/76.41 214888[113:Spt:214886.0,214881.1] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 214892[113:Res:214888.0,61.1] always3(s22) || -> . % 76.30/76.41 214893[113:SSi:214892.0,78164.0,78168.0,192121.0] || -> . % 76.30/76.41 214894[111:Spt:214893.0,214271.0,214272.0] || until2p7(s21)*+ -> . % 76.30/76.41 214895[111:Spt:214893.0,214271.1] || -> node4(s20)*. % 76.30/76.41 214897[111:MRR:858.0,214895.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.30/76.41 214900[111:Res:53.1,214897.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.30/76.41 214902[112:Spt:214900.0] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 214904[112:Res:214902.0,61.1] always3(s20) || -> . % 76.30/76.41 214905[112:SSi:214904.0,78155.0,78159.0,192119.0,214270.0,214895.0] || -> . % 76.30/76.41 214906[112:Spt:214905.0,214900.0,214902.0] || m_main_v_state(s20,c_busy)* -> . % 76.30/76.41 214907[112:Spt:214905.0,214900.1] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 214911[112:Res:214907.0,61.1] always3(s21) || -> . % 76.30/76.41 214912[112:SSi:214911.0,78160.0,78163.0,192120.0] || -> . % 76.30/76.41 214913[110:Spt:214912.0,214269.0,214270.0] || until2p7(s20)*+ -> . % 76.30/76.41 214914[110:Spt:214912.0,214269.1] || -> node4(s19)*. % 76.30/76.41 214916[110:MRR:861.0,214914.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.30/76.41 214919[110:Res:53.1,214916.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.30/76.41 214921[111:Spt:214919.0] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 214923[111:Res:214921.0,61.1] always3(s19) || -> . % 76.30/76.41 214924[111:SSi:214923.0,78151.0,78154.0,192118.0,214268.0,214914.0] || -> . % 76.30/76.41 214925[111:Spt:214924.0,214919.0,214921.0] || m_main_v_state(s19,c_busy)* -> . % 76.30/76.41 214926[111:Spt:214924.0,214919.1] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 214930[111:Res:214926.0,61.1] always3(s20) || -> . % 76.30/76.41 214931[111:SSi:214930.0,78155.0,78159.0,192119.0] || -> . % 76.30/76.41 214932[109:Spt:214931.0,214267.0,214268.0] || until2p7(s19)*+ -> . % 76.30/76.41 214933[109:Spt:214931.0,214267.1] || -> node4(s18)*. % 76.30/76.41 214935[109:MRR:864.0,214933.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.30/76.41 214938[109:Res:53.1,214935.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.30/76.41 214943[110:Spt:214938.0] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 214945[110:Res:214943.0,61.1] always3(s18) || -> . % 76.30/76.41 214946[110:SSi:214945.0,78146.0,78150.0,192117.0,214266.0,214933.0] || -> . % 76.30/76.41 214947[110:Spt:214946.0,214938.0,214943.0] || m_main_v_state(s18,c_busy)* -> . % 76.30/76.41 214948[110:Spt:214946.0,214938.1] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 214952[110:Res:214948.0,61.1] always3(s19) || -> . % 76.30/76.41 214953[110:SSi:214952.0,78151.0,78154.0,192118.0] || -> . % 76.30/76.41 214954[108:Spt:214953.0,214265.0,214266.0] || until2p7(s18)*+ -> . % 76.30/76.41 214955[108:Spt:214953.0,214265.1] || -> node4(s17)*. % 76.30/76.41 214957[108:MRR:867.0,214955.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.30/76.41 214960[108:Res:53.1,214957.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.30/76.41 214962[109:Spt:214960.0] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 214964[109:Res:214962.0,61.1] always3(s17) || -> . % 76.30/76.41 214965[109:SSi:214964.0,78142.0,78145.0,192116.0,214264.0,214955.0] || -> . % 76.30/76.41 214966[109:Spt:214965.0,214960.0,214962.0] || m_main_v_state(s17,c_busy)* -> . % 76.30/76.41 214967[109:Spt:214965.0,214960.1] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 214971[109:Res:214967.0,61.1] always3(s18) || -> . % 76.30/76.41 214972[109:SSi:214971.0,78146.0,78150.0,192117.0] || -> . % 76.30/76.41 214973[107:Spt:214972.0,214263.0,214264.0] || until2p7(s17)*+ -> . % 76.30/76.41 214974[107:Spt:214972.0,214263.1] || -> node4(s16)*. % 76.30/76.41 214976[107:MRR:870.0,214974.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.30/76.41 214979[107:Res:53.1,214976.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.30/76.41 214981[108:Spt:214979.0] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 214983[108:Res:214981.0,61.1] always3(s16) || -> . % 76.30/76.41 214984[108:SSi:214983.0,78137.0,78141.0,192115.0,214262.0,214974.0] || -> . % 76.30/76.41 214985[108:Spt:214984.0,214979.0,214981.0] || m_main_v_state(s16,c_busy)* -> . % 76.30/76.41 214986[108:Spt:214984.0,214979.1] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 214990[108:Res:214986.0,61.1] always3(s17) || -> . % 76.30/76.41 214991[108:SSi:214990.0,78142.0,78145.0,192116.0] || -> . % 76.30/76.41 214992[106:Spt:214991.0,214261.0,214262.0] || until2p7(s16)*+ -> . % 76.30/76.41 214993[106:Spt:214991.0,214261.1] || -> node4(s15)*. % 76.30/76.41 214995[106:MRR:873.0,214993.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.30/76.41 214998[106:Res:53.1,214995.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.30/76.41 215000[107:Spt:214998.0] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 215002[107:Res:215000.0,61.1] always3(s15) || -> . % 76.30/76.41 215003[107:SSi:215002.0,78133.0,78136.0,192114.0,214260.0,214993.0] || -> . % 76.30/76.41 215004[107:Spt:215003.0,214998.0,215000.0] || m_main_v_state(s15,c_busy)* -> . % 76.30/76.41 215005[107:Spt:215003.0,214998.1] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 215009[107:Res:215005.0,61.1] always3(s16) || -> . % 76.30/76.41 215010[107:SSi:215009.0,78137.0,78141.0,192115.0] || -> . % 76.30/76.41 215011[105:Spt:215010.0,214259.0,214260.0] || until2p7(s15)*+ -> . % 76.30/76.41 215012[105:Spt:215010.0,214259.1] || -> node4(s14)*. % 76.30/76.41 215014[105:MRR:876.0,215012.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.30/76.41 215017[105:Res:53.1,215014.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.30/76.41 215022[106:Spt:215017.0] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 215024[106:Res:215022.0,61.1] always3(s14) || -> . % 76.30/76.41 215025[106:SSi:215024.0,78128.0,78132.0,192113.0,214258.0,215012.0] || -> . % 76.30/76.41 215026[106:Spt:215025.0,215017.0,215022.0] || m_main_v_state(s14,c_busy)* -> . % 76.30/76.41 215027[106:Spt:215025.0,215017.1] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 215031[106:Res:215027.0,61.1] always3(s15) || -> . % 76.30/76.41 215032[106:SSi:215031.0,78133.0,78136.0,192114.0] || -> . % 76.30/76.41 215033[104:Spt:215032.0,214257.0,214258.0] || until2p7(s14)*+ -> . % 76.30/76.41 215034[104:Spt:215032.0,214257.1] || -> node4(s13)*. % 76.30/76.41 215036[104:MRR:879.0,215034.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.30/76.41 215039[104:Res:53.1,215036.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.30/76.41 215041[105:Spt:215039.0] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 215043[105:Res:215041.0,61.1] always3(s13) || -> . % 76.30/76.41 215044[105:SSi:215043.0,78124.0,78127.0,192112.0,214256.0,215034.0] || -> . % 76.30/76.41 215045[105:Spt:215044.0,215039.0,215041.0] || m_main_v_state(s13,c_busy)* -> . % 76.30/76.41 215046[105:Spt:215044.0,215039.1] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 215050[105:Res:215046.0,61.1] always3(s14) || -> . % 76.30/76.41 215051[105:SSi:215050.0,78128.0,78132.0,192113.0] || -> . % 76.30/76.41 215052[103:Spt:215051.0,214255.0,214256.0] || until2p7(s13)*+ -> . % 76.30/76.41 215053[103:Spt:215051.0,214255.1] || -> node4(s12)*. % 76.30/76.41 215055[103:MRR:882.0,215053.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.30/76.41 215058[103:Res:53.1,215055.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.30/76.41 215060[104:Spt:215058.0] || -> m_main_v_state(s12,c_busy)*. % 76.30/76.41 215062[104:Res:215060.0,61.1] always3(s12) || -> . % 76.30/76.41 215063[104:SSi:215062.0,78119.0,78123.0,192111.0,214254.0,215053.0] || -> . % 76.30/76.41 215064[104:Spt:215063.0,215058.0,215060.0] || m_main_v_state(s12,c_busy)* -> . % 76.30/76.41 215065[104:Spt:215063.0,215058.1] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 215069[104:Res:215065.0,61.1] always3(s13) || -> . % 76.30/76.41 215070[104:SSi:215069.0,78124.0,78127.0,192112.0] || -> . % 76.30/76.41 215071[102:Spt:215070.0,214253.0,214254.0] || until2p7(s12)*+ -> . % 76.30/76.41 215072[102:Spt:215070.0,214253.1] || -> node4(s11)*. % 76.30/76.41 215074[102:MRR:885.0,215072.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.30/76.41 215077[102:Res:53.1,215074.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.30/76.41 215079[103:Spt:215077.0] || -> m_main_v_state(s11,c_busy)*. % 76.30/76.41 215081[103:Res:215079.0,61.1] always3(s11) || -> . % 76.30/76.41 215082[103:SSi:215081.0,78115.0,78118.0,192110.0,214252.0,215072.0] || -> . % 76.30/76.41 215083[103:Spt:215082.0,215077.0,215079.0] || m_main_v_state(s11,c_busy)* -> . % 76.30/76.41 215084[103:Spt:215082.0,215077.1] || -> m_main_v_state(s12,c_busy)*. % 76.30/76.41 215088[103:Res:215084.0,61.1] always3(s12) || -> . % 76.30/76.41 215089[103:SSi:215088.0,78119.0,78123.0,192111.0] || -> . % 76.30/76.41 215090[101:Spt:215089.0,214251.0,214252.0] || until2p7(s11)*+ -> . % 76.30/76.41 215091[101:Spt:215089.0,214251.1] || -> node4(s10)*. % 76.30/76.41 215093[101:MRR:888.0,215091.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.30/76.41 215096[101:Res:53.1,215093.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.30/76.41 215101[102:Spt:215096.0] || -> m_main_v_state(s10,c_busy)*. % 76.30/76.41 215103[102:Res:215101.0,61.1] always3(s10) || -> . % 76.30/76.41 215104[102:SSi:215103.0,78110.0,78114.0,192109.0,214250.0,215091.0] || -> . % 76.30/76.41 215105[102:Spt:215104.0,215096.0,215101.0] || m_main_v_state(s10,c_busy)* -> . % 76.30/76.41 215106[102:Spt:215104.0,215096.1] || -> m_main_v_state(s11,c_busy)*. % 76.30/76.41 215110[102:Res:215106.0,61.1] always3(s11) || -> . % 76.30/76.41 215111[102:SSi:215110.0,78115.0,78118.0,192110.0] || -> . % 76.30/76.41 215112[100:Spt:215111.0,214249.0,214250.0] || until2p7(s10)*+ -> . % 76.30/76.41 215113[100:Spt:215111.0,214249.1] || -> node4(s9)*. % 76.30/76.41 215115[100:MRR:891.0,215113.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.30/76.41 215118[100:Res:53.1,215115.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.30/76.41 215120[101:Spt:215118.0] || -> m_main_v_state(s9,c_busy)*. % 76.30/76.41 215122[101:Res:215120.0,61.1] always3(s9) || -> . % 76.30/76.41 215123[101:SSi:215122.0,78106.0,78109.0,192108.0,214248.0,215113.0] || -> . % 76.30/76.41 215124[101:Spt:215123.0,215118.0,215120.0] || m_main_v_state(s9,c_busy)* -> . % 76.30/76.41 215125[101:Spt:215123.0,215118.1] || -> m_main_v_state(s10,c_busy)*. % 76.30/76.41 215129[101:Res:215125.0,61.1] always3(s10) || -> . % 76.30/76.41 215130[101:SSi:215129.0,78110.0,78114.0,192109.0] || -> . % 76.30/76.41 215131[99:Spt:215130.0,214247.0,214248.0] || until2p7(s9)*+ -> . % 76.30/76.41 215132[99:Spt:215130.0,214247.1] || -> node4(s8)*. % 76.30/76.41 215134[99:MRR:894.0,215132.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.30/76.41 215137[99:Res:53.1,215134.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.30/76.41 215139[99:MRR:215137.0,214237.0] || -> m_main_v_state(s9,c_busy)*. % 76.30/76.41 215141[99:Res:215139.0,61.1] always3(s9) || -> . % 76.30/76.41 215142[99:SSi:215141.0,78106.0,78109.0,192108.0] || -> . % 76.30/76.41 215143[97:Spt:215142.0,214084.0,214087.0] || trans(s49,s8)*+ -> . % 76.30/76.41 215144[97:Spt:215142.0,214084.1,214084.2] || -> trans(s49,s7) node2(s49,s6)*. % 76.30/76.41 215146[97:MRR:214086.1,215143.0] xuntil6(s49) || -> trans(s49,s7)* until2p7(s6). % 76.30/76.41 215147[98:Spt:215144.0] || -> trans(s49,s7)*. % 76.30/76.41 215148[98:Res:215147.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s7)*. % 76.30/76.41 215150[98:Res:215147.0,60.0] || -> node2(s49,s7)*. % 76.30/76.41 215151[98:SSi:215148.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s7)*. % 76.30/76.41 215152[98:Res:215150.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)*. % 76.30/76.41 215293[98:SoR:215152.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)*. % 76.30/76.41 215295[98:SoR:215293.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s7,c_busy)* xuntil6(s49). % 76.30/76.41 215296[98:SSi:215295.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s7,c_busy)* xuntil6(s49). % 76.30/76.41 215297[99:Spt:215296.1] || -> m_main_v_state(s7,c_busy)*. % 76.30/76.41 215299[99:Res:215297.0,61.1] always3(s7) || -> . % 76.30/76.41 215300[99:SSi:215299.0,78097.0,78100.0,192106.0] || -> . % 76.30/76.41 215301[99:Spt:215300.0,215296.1,215297.0] || m_main_v_state(s7,c_busy)*+ -> . % 76.30/76.41 215302[99:Spt:215300.0,215296.0,215296.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 215306[99:MRR:215293.2,215301.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 215307[99:Res:53.1,215302.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 215309[99:MRR:215307.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 215310[99:MRR:215151.0,215309.0] || -> until2p7(s7)*. % 76.30/76.41 215311[99:MRR:203.0,215310.0] || -> until2p7(s8)* node4(s7). % 76.30/76.41 215312[100:Spt:215311.0] || -> until2p7(s8)*. % 76.30/76.41 215313[100:MRR:204.0,215312.0] || -> until2p7(s9)* node4(s8). % 76.30/76.41 215314[101:Spt:215313.0] || -> until2p7(s9)*. % 76.30/76.41 215315[101:MRR:205.0,215314.0] || -> until2p7(s10)* node4(s9). % 76.30/76.41 215316[102:Spt:215315.0] || -> until2p7(s10)*. % 76.30/76.41 215317[102:MRR:206.0,215316.0] || -> until2p7(s11)* node4(s10). % 76.30/76.41 215318[103:Spt:215317.0] || -> until2p7(s11)*. % 76.30/76.41 215319[103:MRR:207.0,215318.0] || -> until2p7(s12)* node4(s11). % 76.30/76.41 215320[104:Spt:215319.0] || -> until2p7(s12)*. % 76.30/76.41 215321[104:MRR:208.0,215320.0] || -> until2p7(s13)* node4(s12). % 76.30/76.41 215322[105:Spt:215321.0] || -> until2p7(s13)*. % 76.30/76.41 215323[105:MRR:209.0,215322.0] || -> until2p7(s14)* node4(s13). % 76.30/76.41 215324[106:Spt:215323.0] || -> until2p7(s14)*. % 76.30/76.41 215325[106:MRR:210.0,215324.0] || -> until2p7(s15)* node4(s14). % 76.30/76.41 215326[107:Spt:215325.0] || -> until2p7(s15)*. % 76.30/76.41 215327[107:MRR:211.0,215326.0] || -> until2p7(s16)* node4(s15). % 76.30/76.41 215328[108:Spt:215327.0] || -> until2p7(s16)*. % 76.30/76.41 215329[108:MRR:212.0,215328.0] || -> until2p7(s17)* node4(s16). % 76.30/76.41 215330[109:Spt:215329.0] || -> until2p7(s17)*. % 76.30/76.41 215331[109:MRR:213.0,215330.0] || -> until2p7(s18)* node4(s17). % 76.30/76.41 215332[110:Spt:215331.0] || -> until2p7(s18)*. % 76.30/76.41 215333[110:MRR:214.0,215332.0] || -> until2p7(s19)* node4(s18). % 76.30/76.41 215334[111:Spt:215333.0] || -> until2p7(s19)*. % 76.30/76.41 215335[111:MRR:215.0,215334.0] || -> until2p7(s20)* node4(s19). % 76.30/76.41 215336[112:Spt:215335.0] || -> until2p7(s20)*. % 76.30/76.41 215337[112:MRR:216.0,215336.0] || -> until2p7(s21)* node4(s20). % 76.30/76.41 215338[113:Spt:215337.0] || -> until2p7(s21)*. % 76.30/76.41 215339[113:MRR:217.0,215338.0] || -> until2p7(s22)* node4(s21). % 76.30/76.41 215340[114:Spt:215339.0] || -> until2p7(s22)*. % 76.30/76.41 215341[114:MRR:218.0,215340.0] || -> until2p7(s23)* node4(s22). % 76.30/76.41 215342[115:Spt:215341.0] || -> until2p7(s23)*. % 76.30/76.41 215343[115:MRR:219.0,215342.0] || -> until2p7(s24)* node4(s23). % 76.30/76.41 215344[116:Spt:215343.0] || -> until2p7(s24)*. % 76.30/76.41 215345[116:MRR:220.0,215344.0] || -> until2p7(s25)* node4(s24). % 76.30/76.41 215346[117:Spt:215345.0] || -> until2p7(s25)*. % 76.30/76.41 215347[117:MRR:221.0,215346.0] || -> until2p7(s26)* node4(s25). % 76.30/76.41 215348[118:Spt:215347.0] || -> until2p7(s26)*. % 76.30/76.41 215349[118:MRR:222.0,215348.0] || -> until2p7(s27)* node4(s26). % 76.30/76.41 215350[119:Spt:215349.0] || -> until2p7(s27)*. % 76.30/76.41 215351[119:MRR:223.0,215350.0] || -> until2p7(s28)* node4(s27). % 76.30/76.41 215352[120:Spt:215351.0] || -> until2p7(s28)*. % 76.30/76.41 215353[120:MRR:224.0,215352.0] || -> until2p7(s29)* node4(s28). % 76.30/76.41 215354[121:Spt:215353.0] || -> until2p7(s29)*. % 76.30/76.41 215355[121:MRR:225.0,215354.0] || -> until2p7(s30)* node4(s29). % 76.30/76.41 215356[122:Spt:215355.0] || -> until2p7(s30)*. % 76.30/76.41 215357[122:MRR:226.0,215356.0] || -> until2p7(s31)* node4(s30). % 76.30/76.41 215358[123:Spt:215357.0] || -> until2p7(s31)*. % 76.30/76.41 215359[123:MRR:227.0,215358.0] || -> until2p7(s32)* node4(s31). % 76.30/76.41 215360[124:Spt:215359.0] || -> until2p7(s32)*. % 76.30/76.41 215361[124:MRR:228.0,215360.0] || -> until2p7(s33)* node4(s32). % 76.30/76.41 215362[125:Spt:215361.0] || -> until2p7(s33)*. % 76.30/76.41 215363[125:MRR:229.0,215362.0] || -> until2p7(s34)* node4(s33). % 76.30/76.41 215364[126:Spt:215363.0] || -> until2p7(s34)*. % 76.30/76.41 215365[126:MRR:230.0,215364.0] || -> until2p7(s35)* node4(s34). % 76.30/76.41 215366[127:Spt:215365.0] || -> until2p7(s35)*. % 76.30/76.41 215367[127:MRR:231.0,215366.0] || -> until2p7(s36)* node4(s35). % 76.30/76.41 215368[128:Spt:215367.0] || -> until2p7(s36)*. % 76.30/76.41 215369[128:MRR:232.0,215368.0] || -> until2p7(s37)* node4(s36). % 76.30/76.41 215370[129:Spt:215369.0] || -> until2p7(s37)*. % 76.30/76.41 215371[129:MRR:235.0,215370.0] || -> until2p7(s38)* node4(s37). % 76.30/76.41 215372[130:Spt:215371.0] || -> until2p7(s38)*. % 76.30/76.41 215373[130:MRR:236.0,215372.0] || -> until2p7(s39)* node4(s38). % 76.30/76.41 215374[131:Spt:215373.0] || -> until2p7(s39)*. % 76.30/76.41 215375[131:MRR:237.0,215374.0] || -> until2p7(s40)* node4(s39). % 76.30/76.41 215376[132:Spt:215375.0] || -> until2p7(s40)*. % 76.30/76.41 215377[132:MRR:238.0,215376.0] || -> until2p7(s41)* node4(s40). % 76.30/76.41 215378[133:Spt:215377.0] || -> until2p7(s41)*. % 76.30/76.41 215379[133:MRR:239.0,215378.0] || -> until2p7(s42)* node4(s41). % 76.30/76.41 215380[134:Spt:215379.0] || -> until2p7(s42)*. % 76.30/76.41 215381[134:MRR:240.0,215380.0] || -> until2p7(s43)* node4(s42). % 76.30/76.41 215382[135:Spt:215381.0] || -> until2p7(s43)*. % 76.30/76.41 215383[135:MRR:241.0,215382.0] || -> until2p7(s44)* node4(s43). % 76.30/76.41 215384[136:Spt:215383.0] || -> until2p7(s44)*. % 76.30/76.41 215385[136:MRR:539.0,215384.0] || -> until2p7(s45)* node4(s44). % 76.30/76.41 215386[137:Spt:215385.0] || -> until2p7(s45)*. % 76.30/76.41 215387[137:MRR:544.0,215386.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 215388[138:Spt:215387.0] || -> until2p7(s46)*. % 76.30/76.41 215389[138:MRR:549.0,215388.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 215390[139:Spt:215389.0] || -> until2p7(s47)*. % 76.30/76.41 215391[139:MRR:554.0,215390.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 215392[140:Spt:215391.0] || -> until2p7(s48)*. % 76.30/76.41 215393[140:MRR:559.0,215392.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 215394[141:Spt:215393.0] || -> until2p7(s49)*. % 76.30/76.41 215395[141:MRR:194.0,215394.0] || -> node4(s49)*. % 76.30/76.41 215396[141:MRR:215306.0,215395.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 215397[141:Res:53.1,215396.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 215399[141:MRR:215397.0,78381.0] || -> . % 76.30/76.41 215400[141:Spt:215399.0,215393.0,215394.0] || until2p7(s49)*+ -> . % 76.30/76.41 215401[141:Spt:215399.0,215393.1] || -> node4(s48)*. % 76.30/76.41 215402[141:MRR:78384.0,215401.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 215405[141:Res:53.1,215402.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 215408[141:Res:215405.0,61.1] always3(s48) || -> . % 76.30/76.41 215409[141:SSi:215408.0,78281.0,78387.0,192147.0,215392.0,215401.0] || -> . % 76.30/76.41 215410[140:Spt:215409.0,215391.0,215392.0] || until2p7(s48)*+ -> . % 76.30/76.41 215411[140:Spt:215409.0,215391.1] || -> node4(s47)*. % 76.30/76.41 215413[140:MRR:777.0,215411.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 215428[140:Res:53.1,215413.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 215433[141:Spt:215428.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 215435[141:Res:215433.0,61.1] always3(s47) || -> . % 76.30/76.41 215436[141:SSi:215435.0,78277.0,78280.0,192146.0,215390.0,215411.0] || -> . % 76.30/76.41 215437[141:Spt:215436.0,215428.0,215433.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 215438[141:Spt:215436.0,215428.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 215442[141:Res:215438.0,61.1] always3(s48) || -> . % 76.30/76.41 215443[141:SSi:215442.0,78281.0,78387.0,192147.0] || -> . % 76.30/76.41 215444[139:Spt:215443.0,215389.0,215390.0] || until2p7(s47)*+ -> . % 76.30/76.41 215445[139:Spt:215443.0,215389.1] || -> node4(s46)*. % 76.30/76.41 215447[139:MRR:780.0,215445.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 215454[139:Res:53.1,215447.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 215456[140:Spt:215454.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 215458[140:Res:215456.0,61.1] always3(s46) || -> . % 76.30/76.41 215459[140:SSi:215458.0,78272.0,78276.0,192145.0,215388.0,215445.0] || -> . % 76.30/76.41 215460[140:Spt:215459.0,215454.0,215456.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 215461[140:Spt:215459.0,215454.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 215465[140:Res:215461.0,61.1] always3(s47) || -> . % 76.30/76.41 215466[140:SSi:215465.0,78277.0,78280.0,192146.0] || -> . % 76.30/76.41 215467[138:Spt:215466.0,215387.0,215388.0] || until2p7(s46)*+ -> . % 76.30/76.41 215468[138:Spt:215466.0,215387.1] || -> node4(s45)*. % 76.30/76.41 215470[138:MRR:783.0,215468.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 215473[138:Res:53.1,215470.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 215478[139:Spt:215473.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 215480[139:Res:215478.0,61.1] always3(s45) || -> . % 76.30/76.41 215481[139:SSi:215480.0,78268.0,78271.0,192144.0,215386.0,215468.0] || -> . % 76.30/76.41 215482[139:Spt:215481.0,215473.0,215478.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.41 215483[139:Spt:215481.0,215473.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 215487[139:Res:215483.0,61.1] always3(s46) || -> . % 76.30/76.41 215488[139:SSi:215487.0,78272.0,78276.0,192145.0] || -> . % 76.30/76.41 215489[137:Spt:215488.0,215385.0,215386.0] || until2p7(s45)*+ -> . % 76.30/76.41 215490[137:Spt:215488.0,215385.1] || -> node4(s44)*. % 76.30/76.41 215492[137:MRR:786.0,215490.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.41 215495[137:Res:53.1,215492.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.41 215497[138:Spt:215495.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 215499[138:Res:215497.0,61.1] always3(s44) || -> . % 76.30/76.41 215500[138:SSi:215499.0,78263.0,78267.0,192143.0,215384.0,215490.0] || -> . % 76.30/76.41 215501[138:Spt:215500.0,215495.0,215497.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.41 215502[138:Spt:215500.0,215495.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 215506[138:Res:215502.0,61.1] always3(s45) || -> . % 76.30/76.41 215507[138:SSi:215506.0,78268.0,78271.0,192144.0] || -> . % 76.30/76.41 215508[136:Spt:215507.0,215383.0,215384.0] || until2p7(s44)*+ -> . % 76.30/76.41 215509[136:Spt:215507.0,215383.1] || -> node4(s43)*. % 76.30/76.41 215511[136:MRR:789.0,215509.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.41 215514[136:Res:53.1,215511.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.41 215516[137:Spt:215514.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 215518[137:Res:215516.0,61.1] always3(s43) || -> . % 76.30/76.41 215519[137:SSi:215518.0,78259.0,78262.0,192142.0,215382.0,215509.0] || -> . % 76.30/76.41 215520[137:Spt:215519.0,215514.0,215516.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.41 215521[137:Spt:215519.0,215514.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 215525[137:Res:215521.0,61.1] always3(s44) || -> . % 76.30/76.41 215526[137:SSi:215525.0,78263.0,78267.0,192143.0] || -> . % 76.30/76.41 215527[135:Spt:215526.0,215381.0,215382.0] || until2p7(s43)*+ -> . % 76.30/76.41 215528[135:Spt:215526.0,215381.1] || -> node4(s42)*. % 76.30/76.41 215530[135:MRR:792.0,215528.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.41 215533[135:Res:53.1,215530.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.41 215535[136:Spt:215533.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 215537[136:Res:215535.0,61.1] always3(s42) || -> . % 76.30/76.41 215538[136:SSi:215537.0,78254.0,78258.0,192141.0,215380.0,215528.0] || -> . % 76.30/76.41 215539[136:Spt:215538.0,215533.0,215535.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.41 215540[136:Spt:215538.0,215533.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 215544[136:Res:215540.0,61.1] always3(s43) || -> . % 76.30/76.41 215545[136:SSi:215544.0,78259.0,78262.0,192142.0] || -> . % 76.30/76.41 215546[134:Spt:215545.0,215379.0,215380.0] || until2p7(s42)*+ -> . % 76.30/76.41 215547[134:Spt:215545.0,215379.1] || -> node4(s41)*. % 76.30/76.41 215549[134:MRR:795.0,215547.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.41 215552[134:Res:53.1,215549.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.41 215557[135:Spt:215552.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 215559[135:Res:215557.0,61.1] always3(s41) || -> . % 76.30/76.41 215560[135:SSi:215559.0,78250.0,78253.0,192140.0,215378.0,215547.0] || -> . % 76.30/76.41 215561[135:Spt:215560.0,215552.0,215557.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.41 215562[135:Spt:215560.0,215552.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 215566[135:Res:215562.0,61.1] always3(s42) || -> . % 76.30/76.41 215567[135:SSi:215566.0,78254.0,78258.0,192141.0] || -> . % 76.30/76.41 215568[133:Spt:215567.0,215377.0,215378.0] || until2p7(s41)*+ -> . % 76.30/76.41 215569[133:Spt:215567.0,215377.1] || -> node4(s40)*. % 76.30/76.41 215571[133:MRR:798.0,215569.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.41 215574[133:Res:53.1,215571.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.41 215576[134:Spt:215574.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 215578[134:Res:215576.0,61.1] always3(s40) || -> . % 76.30/76.41 215579[134:SSi:215578.0,78245.0,78249.0,192139.0,215376.0,215569.0] || -> . % 76.30/76.41 215580[134:Spt:215579.0,215574.0,215576.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.41 215581[134:Spt:215579.0,215574.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 215585[134:Res:215581.0,61.1] always3(s41) || -> . % 76.30/76.41 215586[134:SSi:215585.0,78250.0,78253.0,192140.0] || -> . % 76.30/76.41 215587[132:Spt:215586.0,215375.0,215376.0] || until2p7(s40)*+ -> . % 76.30/76.41 215588[132:Spt:215586.0,215375.1] || -> node4(s39)*. % 76.30/76.41 215590[132:MRR:801.0,215588.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.41 215593[132:Res:53.1,215590.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.41 215595[133:Spt:215593.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 215597[133:Res:215595.0,61.1] always3(s39) || -> . % 76.30/76.41 215598[133:SSi:215597.0,78241.0,78244.0,192138.0,215374.0,215588.0] || -> . % 76.30/76.41 215599[133:Spt:215598.0,215593.0,215595.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.41 215600[133:Spt:215598.0,215593.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 215604[133:Res:215600.0,61.1] always3(s40) || -> . % 76.30/76.41 215605[133:SSi:215604.0,78245.0,78249.0,192139.0] || -> . % 76.30/76.41 215606[131:Spt:215605.0,215373.0,215374.0] || until2p7(s39)*+ -> . % 76.30/76.41 215607[131:Spt:215605.0,215373.1] || -> node4(s38)*. % 76.30/76.41 215609[131:MRR:804.0,215607.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.41 215612[131:Res:53.1,215609.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.41 215614[132:Spt:215612.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 215616[132:Res:215614.0,61.1] always3(s38) || -> . % 76.30/76.41 215617[132:SSi:215616.0,78236.0,78240.0,192137.0,215372.0,215607.0] || -> . % 76.30/76.41 215618[132:Spt:215617.0,215612.0,215614.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.41 215619[132:Spt:215617.0,215612.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 215623[132:Res:215619.0,61.1] always3(s39) || -> . % 76.30/76.41 215624[132:SSi:215623.0,78241.0,78244.0,192138.0] || -> . % 76.30/76.41 215625[130:Spt:215624.0,215371.0,215372.0] || until2p7(s38)*+ -> . % 76.30/76.41 215626[130:Spt:215624.0,215371.1] || -> node4(s37)*. % 76.30/76.41 215628[130:MRR:807.0,215626.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.41 215631[130:Res:53.1,215628.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.41 215636[131:Spt:215631.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 215638[131:Res:215636.0,61.1] always3(s37) || -> . % 76.30/76.41 215639[131:SSi:215638.0,78232.0,78235.0,192136.0,215370.0,215626.0] || -> . % 76.30/76.41 215640[131:Spt:215639.0,215631.0,215636.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.41 215641[131:Spt:215639.0,215631.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 215645[131:Res:215641.0,61.1] always3(s38) || -> . % 76.30/76.41 215646[131:SSi:215645.0,78236.0,78240.0,192137.0] || -> . % 76.30/76.41 215647[129:Spt:215646.0,215369.0,215370.0] || until2p7(s37)*+ -> . % 76.30/76.41 215648[129:Spt:215646.0,215369.1] || -> node4(s36)*. % 76.30/76.41 215650[129:MRR:810.0,215648.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.41 215653[129:Res:53.1,215650.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.41 215655[130:Spt:215653.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 215657[130:Res:215655.0,61.1] always3(s36) || -> . % 76.30/76.41 215658[130:SSi:215657.0,78227.0,78231.0,192135.0,215368.0,215648.0] || -> . % 76.30/76.41 215659[130:Spt:215658.0,215653.0,215655.0] || m_main_v_state(s36,c_busy)* -> . % 76.30/76.41 215660[130:Spt:215658.0,215653.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 215664[130:Res:215660.0,61.1] always3(s37) || -> . % 76.30/76.41 215665[130:SSi:215664.0,78232.0,78235.0,192136.0] || -> . % 76.30/76.41 215666[128:Spt:215665.0,215367.0,215368.0] || until2p7(s36)*+ -> . % 76.30/76.41 215667[128:Spt:215665.0,215367.1] || -> node4(s35)*. % 76.30/76.41 215669[128:MRR:813.0,215667.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.30/76.41 215672[128:Res:53.1,215669.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.30/76.41 215674[129:Spt:215672.0] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 215676[129:Res:215674.0,61.1] always3(s35) || -> . % 76.30/76.41 215677[129:SSi:215676.0,78223.0,78226.0,192134.0,215366.0,215667.0] || -> . % 76.30/76.41 215678[129:Spt:215677.0,215672.0,215674.0] || m_main_v_state(s35,c_busy)* -> . % 76.30/76.41 215679[129:Spt:215677.0,215672.1] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 215683[129:Res:215679.0,61.1] always3(s36) || -> . % 76.30/76.41 215684[129:SSi:215683.0,78227.0,78231.0,192135.0] || -> . % 76.30/76.41 215685[127:Spt:215684.0,215365.0,215366.0] || until2p7(s35)*+ -> . % 76.30/76.41 215686[127:Spt:215684.0,215365.1] || -> node4(s34)*. % 76.30/76.41 215688[127:MRR:816.0,215686.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.30/76.41 215691[127:Res:53.1,215688.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.30/76.41 215693[128:Spt:215691.0] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 215695[128:Res:215693.0,61.1] always3(s34) || -> . % 76.30/76.41 215696[128:SSi:215695.0,78218.0,78222.0,192133.0,215364.0,215686.0] || -> . % 76.30/76.41 215697[128:Spt:215696.0,215691.0,215693.0] || m_main_v_state(s34,c_busy)* -> . % 76.30/76.41 215698[128:Spt:215696.0,215691.1] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 215702[128:Res:215698.0,61.1] always3(s35) || -> . % 76.30/76.41 215703[128:SSi:215702.0,78223.0,78226.0,192134.0] || -> . % 76.30/76.41 215704[126:Spt:215703.0,215363.0,215364.0] || until2p7(s34)*+ -> . % 76.30/76.41 215705[126:Spt:215703.0,215363.1] || -> node4(s33)*. % 76.30/76.41 215707[126:MRR:819.0,215705.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.30/76.41 215710[126:Res:53.1,215707.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.30/76.41 215715[127:Spt:215710.0] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 215717[127:Res:215715.0,61.1] always3(s33) || -> . % 76.30/76.41 215718[127:SSi:215717.0,78214.0,78217.0,192132.0,215362.0,215705.0] || -> . % 76.30/76.41 215719[127:Spt:215718.0,215710.0,215715.0] || m_main_v_state(s33,c_busy)* -> . % 76.30/76.41 215720[127:Spt:215718.0,215710.1] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 215724[127:Res:215720.0,61.1] always3(s34) || -> . % 76.30/76.41 215725[127:SSi:215724.0,78218.0,78222.0,192133.0] || -> . % 76.30/76.41 215726[125:Spt:215725.0,215361.0,215362.0] || until2p7(s33)*+ -> . % 76.30/76.41 215727[125:Spt:215725.0,215361.1] || -> node4(s32)*. % 76.30/76.41 215729[125:MRR:822.0,215727.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.30/76.41 215732[125:Res:53.1,215729.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.30/76.41 215734[126:Spt:215732.0] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 215736[126:Res:215734.0,61.1] always3(s32) || -> . % 76.30/76.41 215737[126:SSi:215736.0,78209.0,78213.0,192131.0,215360.0,215727.0] || -> . % 76.30/76.41 215738[126:Spt:215737.0,215732.0,215734.0] || m_main_v_state(s32,c_busy)* -> . % 76.30/76.41 215739[126:Spt:215737.0,215732.1] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 215743[126:Res:215739.0,61.1] always3(s33) || -> . % 76.30/76.41 215744[126:SSi:215743.0,78214.0,78217.0,192132.0] || -> . % 76.30/76.41 215745[124:Spt:215744.0,215359.0,215360.0] || until2p7(s32)*+ -> . % 76.30/76.41 215746[124:Spt:215744.0,215359.1] || -> node4(s31)*. % 76.30/76.41 215748[124:MRR:825.0,215746.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.30/76.41 215751[124:Res:53.1,215748.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.30/76.41 215753[125:Spt:215751.0] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 215755[125:Res:215753.0,61.1] always3(s31) || -> . % 76.30/76.41 215756[125:SSi:215755.0,78205.0,78208.0,192130.0,215358.0,215746.0] || -> . % 76.30/76.41 215757[125:Spt:215756.0,215751.0,215753.0] || m_main_v_state(s31,c_busy)* -> . % 76.30/76.41 215758[125:Spt:215756.0,215751.1] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 215762[125:Res:215758.0,61.1] always3(s32) || -> . % 76.30/76.41 215763[125:SSi:215762.0,78209.0,78213.0,192131.0] || -> . % 76.30/76.41 215764[123:Spt:215763.0,215357.0,215358.0] || until2p7(s31)*+ -> . % 76.30/76.41 215765[123:Spt:215763.0,215357.1] || -> node4(s30)*. % 76.30/76.41 215767[123:MRR:828.0,215765.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.30/76.41 215770[123:Res:53.1,215767.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.30/76.41 215772[124:Spt:215770.0] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 215774[124:Res:215772.0,61.1] always3(s30) || -> . % 76.30/76.41 215775[124:SSi:215774.0,78200.0,78204.0,192129.0,215356.0,215765.0] || -> . % 76.30/76.41 215776[124:Spt:215775.0,215770.0,215772.0] || m_main_v_state(s30,c_busy)* -> . % 76.30/76.41 215777[124:Spt:215775.0,215770.1] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 215781[124:Res:215777.0,61.1] always3(s31) || -> . % 76.30/76.41 215782[124:SSi:215781.0,78205.0,78208.0,192130.0] || -> . % 76.30/76.41 215783[122:Spt:215782.0,215355.0,215356.0] || until2p7(s30)*+ -> . % 76.30/76.41 215784[122:Spt:215782.0,215355.1] || -> node4(s29)*. % 76.30/76.41 215786[122:MRR:831.0,215784.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.30/76.41 215789[122:Res:53.1,215786.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.30/76.41 215794[123:Spt:215789.0] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 215796[123:Res:215794.0,61.1] always3(s29) || -> . % 76.30/76.41 215797[123:SSi:215796.0,78196.0,78199.0,192128.0,215354.0,215784.0] || -> . % 76.30/76.41 215798[123:Spt:215797.0,215789.0,215794.0] || m_main_v_state(s29,c_busy)* -> . % 76.30/76.41 215799[123:Spt:215797.0,215789.1] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 215803[123:Res:215799.0,61.1] always3(s30) || -> . % 76.30/76.41 215804[123:SSi:215803.0,78200.0,78204.0,192129.0] || -> . % 76.30/76.41 215805[121:Spt:215804.0,215353.0,215354.0] || until2p7(s29)*+ -> . % 76.30/76.41 215806[121:Spt:215804.0,215353.1] || -> node4(s28)*. % 76.30/76.41 215808[121:MRR:834.0,215806.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.30/76.41 215811[121:Res:53.1,215808.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.30/76.41 215813[122:Spt:215811.0] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 215815[122:Res:215813.0,61.1] always3(s28) || -> . % 76.30/76.41 215816[122:SSi:215815.0,78191.0,78195.0,192127.0,215352.0,215806.0] || -> . % 76.30/76.41 215817[122:Spt:215816.0,215811.0,215813.0] || m_main_v_state(s28,c_busy)* -> . % 76.30/76.41 215818[122:Spt:215816.0,215811.1] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 215822[122:Res:215818.0,61.1] always3(s29) || -> . % 76.30/76.41 215823[122:SSi:215822.0,78196.0,78199.0,192128.0] || -> . % 76.30/76.41 215824[120:Spt:215823.0,215351.0,215352.0] || until2p7(s28)*+ -> . % 76.30/76.41 215825[120:Spt:215823.0,215351.1] || -> node4(s27)*. % 76.30/76.41 215827[120:MRR:837.0,215825.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.30/76.41 215830[120:Res:53.1,215827.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.30/76.41 215832[121:Spt:215830.0] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 215834[121:Res:215832.0,61.1] always3(s27) || -> . % 76.30/76.41 215835[121:SSi:215834.0,78187.0,78190.0,192126.0,215350.0,215825.0] || -> . % 76.30/76.41 215836[121:Spt:215835.0,215830.0,215832.0] || m_main_v_state(s27,c_busy)* -> . % 76.30/76.41 215837[121:Spt:215835.0,215830.1] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 215841[121:Res:215837.0,61.1] always3(s28) || -> . % 76.30/76.41 215842[121:SSi:215841.0,78191.0,78195.0,192127.0] || -> . % 76.30/76.41 215843[119:Spt:215842.0,215349.0,215350.0] || until2p7(s27)*+ -> . % 76.30/76.41 215844[119:Spt:215842.0,215349.1] || -> node4(s26)*. % 76.30/76.41 215846[119:MRR:840.0,215844.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.30/76.41 215849[119:Res:53.1,215846.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.30/76.41 215851[120:Spt:215849.0] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 215853[120:Res:215851.0,61.1] always3(s26) || -> . % 76.30/76.41 215854[120:SSi:215853.0,78182.0,78186.0,192125.0,215348.0,215844.0] || -> . % 76.30/76.41 215855[120:Spt:215854.0,215849.0,215851.0] || m_main_v_state(s26,c_busy)* -> . % 76.30/76.41 215856[120:Spt:215854.0,215849.1] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 215860[120:Res:215856.0,61.1] always3(s27) || -> . % 76.30/76.41 215861[120:SSi:215860.0,78187.0,78190.0,192126.0] || -> . % 76.30/76.41 215862[118:Spt:215861.0,215347.0,215348.0] || until2p7(s26)*+ -> . % 76.30/76.41 215863[118:Spt:215861.0,215347.1] || -> node4(s25)*. % 76.30/76.41 215865[118:MRR:843.0,215863.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.30/76.41 215868[118:Res:53.1,215865.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.30/76.41 215873[119:Spt:215868.0] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 215875[119:Res:215873.0,61.1] always3(s25) || -> . % 76.30/76.41 215876[119:SSi:215875.0,78178.0,78181.0,192124.0,215346.0,215863.0] || -> . % 76.30/76.41 215877[119:Spt:215876.0,215868.0,215873.0] || m_main_v_state(s25,c_busy)* -> . % 76.30/76.41 215878[119:Spt:215876.0,215868.1] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 215882[119:Res:215878.0,61.1] always3(s26) || -> . % 76.30/76.41 215883[119:SSi:215882.0,78182.0,78186.0,192125.0] || -> . % 76.30/76.41 215884[117:Spt:215883.0,215345.0,215346.0] || until2p7(s25)*+ -> . % 76.30/76.41 215885[117:Spt:215883.0,215345.1] || -> node4(s24)*. % 76.30/76.41 215887[117:MRR:846.0,215885.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.30/76.41 215890[117:Res:53.1,215887.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.30/76.41 215892[118:Spt:215890.0] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 215894[118:Res:215892.0,61.1] always3(s24) || -> . % 76.30/76.41 215895[118:SSi:215894.0,78173.0,78177.0,192123.0,215344.0,215885.0] || -> . % 76.30/76.41 215896[118:Spt:215895.0,215890.0,215892.0] || m_main_v_state(s24,c_busy)* -> . % 76.30/76.41 215897[118:Spt:215895.0,215890.1] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 215901[118:Res:215897.0,61.1] always3(s25) || -> . % 76.30/76.41 215902[118:SSi:215901.0,78178.0,78181.0,192124.0] || -> . % 76.30/76.41 215903[116:Spt:215902.0,215343.0,215344.0] || until2p7(s24)*+ -> . % 76.30/76.41 215904[116:Spt:215902.0,215343.1] || -> node4(s23)*. % 76.30/76.41 215906[116:MRR:849.0,215904.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.30/76.41 215909[116:Res:53.1,215906.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.30/76.41 215911[117:Spt:215909.0] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 215913[117:Res:215911.0,61.1] always3(s23) || -> . % 76.30/76.41 215914[117:SSi:215913.0,78169.0,78172.0,192122.0,215342.0,215904.0] || -> . % 76.30/76.41 215915[117:Spt:215914.0,215909.0,215911.0] || m_main_v_state(s23,c_busy)* -> . % 76.30/76.41 215916[117:Spt:215914.0,215909.1] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 215920[117:Res:215916.0,61.1] always3(s24) || -> . % 76.30/76.41 215921[117:SSi:215920.0,78173.0,78177.0,192123.0] || -> . % 76.30/76.41 215922[115:Spt:215921.0,215341.0,215342.0] || until2p7(s23)*+ -> . % 76.30/76.41 215923[115:Spt:215921.0,215341.1] || -> node4(s22)*. % 76.30/76.41 215925[115:MRR:852.0,215923.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.30/76.41 215928[115:Res:53.1,215925.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.30/76.41 215930[116:Spt:215928.0] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 215932[116:Res:215930.0,61.1] always3(s22) || -> . % 76.30/76.41 215933[116:SSi:215932.0,78164.0,78168.0,192121.0,215340.0,215923.0] || -> . % 76.30/76.41 215934[116:Spt:215933.0,215928.0,215930.0] || m_main_v_state(s22,c_busy)* -> . % 76.30/76.41 215935[116:Spt:215933.0,215928.1] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 215939[116:Res:215935.0,61.1] always3(s23) || -> . % 76.30/76.41 215940[116:SSi:215939.0,78169.0,78172.0,192122.0] || -> . % 76.30/76.41 215941[114:Spt:215940.0,215339.0,215340.0] || until2p7(s22)*+ -> . % 76.30/76.41 215942[114:Spt:215940.0,215339.1] || -> node4(s21)*. % 76.30/76.41 215944[114:MRR:855.0,215942.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.30/76.41 215947[114:Res:53.1,215944.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.30/76.41 215952[115:Spt:215947.0] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 215954[115:Res:215952.0,61.1] always3(s21) || -> . % 76.30/76.41 215955[115:SSi:215954.0,78160.0,78163.0,192120.0,215338.0,215942.0] || -> . % 76.30/76.41 215956[115:Spt:215955.0,215947.0,215952.0] || m_main_v_state(s21,c_busy)* -> . % 76.30/76.41 215957[115:Spt:215955.0,215947.1] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 215961[115:Res:215957.0,61.1] always3(s22) || -> . % 76.30/76.41 215962[115:SSi:215961.0,78164.0,78168.0,192121.0] || -> . % 76.30/76.41 215963[113:Spt:215962.0,215337.0,215338.0] || until2p7(s21)*+ -> . % 76.30/76.41 215964[113:Spt:215962.0,215337.1] || -> node4(s20)*. % 76.30/76.41 215966[113:MRR:858.0,215964.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.30/76.41 215969[113:Res:53.1,215966.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.30/76.41 215971[114:Spt:215969.0] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 215973[114:Res:215971.0,61.1] always3(s20) || -> . % 76.30/76.41 215974[114:SSi:215973.0,78155.0,78159.0,192119.0,215336.0,215964.0] || -> . % 76.30/76.41 215975[114:Spt:215974.0,215969.0,215971.0] || m_main_v_state(s20,c_busy)* -> . % 76.30/76.41 215976[114:Spt:215974.0,215969.1] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 215980[114:Res:215976.0,61.1] always3(s21) || -> . % 76.30/76.41 215981[114:SSi:215980.0,78160.0,78163.0,192120.0] || -> . % 76.30/76.41 215982[112:Spt:215981.0,215335.0,215336.0] || until2p7(s20)*+ -> . % 76.30/76.41 215983[112:Spt:215981.0,215335.1] || -> node4(s19)*. % 76.30/76.41 215985[112:MRR:861.0,215983.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.30/76.41 215988[112:Res:53.1,215985.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.30/76.41 215990[113:Spt:215988.0] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 215992[113:Res:215990.0,61.1] always3(s19) || -> . % 76.30/76.41 215993[113:SSi:215992.0,78151.0,78154.0,192118.0,215334.0,215983.0] || -> . % 76.30/76.41 215994[113:Spt:215993.0,215988.0,215990.0] || m_main_v_state(s19,c_busy)* -> . % 76.30/76.41 215995[113:Spt:215993.0,215988.1] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 215999[113:Res:215995.0,61.1] always3(s20) || -> . % 76.30/76.41 216000[113:SSi:215999.0,78155.0,78159.0,192119.0] || -> . % 76.30/76.41 216001[111:Spt:216000.0,215333.0,215334.0] || until2p7(s19)*+ -> . % 76.30/76.41 216002[111:Spt:216000.0,215333.1] || -> node4(s18)*. % 76.30/76.41 216004[111:MRR:864.0,216002.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.30/76.41 216007[111:Res:53.1,216004.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.30/76.41 216009[112:Spt:216007.0] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 216011[112:Res:216009.0,61.1] always3(s18) || -> . % 76.30/76.41 216012[112:SSi:216011.0,78146.0,78150.0,192117.0,215332.0,216002.0] || -> . % 76.30/76.41 216013[112:Spt:216012.0,216007.0,216009.0] || m_main_v_state(s18,c_busy)* -> . % 76.30/76.41 216014[112:Spt:216012.0,216007.1] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 216018[112:Res:216014.0,61.1] always3(s19) || -> . % 76.30/76.41 216019[112:SSi:216018.0,78151.0,78154.0,192118.0] || -> . % 76.30/76.41 216020[110:Spt:216019.0,215331.0,215332.0] || until2p7(s18)*+ -> . % 76.30/76.41 216021[110:Spt:216019.0,215331.1] || -> node4(s17)*. % 76.30/76.41 216023[110:MRR:867.0,216021.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.30/76.41 216026[110:Res:53.1,216023.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.30/76.41 216031[111:Spt:216026.0] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 216033[111:Res:216031.0,61.1] always3(s17) || -> . % 76.30/76.41 216034[111:SSi:216033.0,78142.0,78145.0,192116.0,215330.0,216021.0] || -> . % 76.30/76.41 216035[111:Spt:216034.0,216026.0,216031.0] || m_main_v_state(s17,c_busy)* -> . % 76.30/76.41 216036[111:Spt:216034.0,216026.1] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 216040[111:Res:216036.0,61.1] always3(s18) || -> . % 76.30/76.41 216041[111:SSi:216040.0,78146.0,78150.0,192117.0] || -> . % 76.30/76.41 216042[109:Spt:216041.0,215329.0,215330.0] || until2p7(s17)*+ -> . % 76.30/76.41 216043[109:Spt:216041.0,215329.1] || -> node4(s16)*. % 76.30/76.41 216045[109:MRR:870.0,216043.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.30/76.41 216048[109:Res:53.1,216045.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.30/76.41 216050[110:Spt:216048.0] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 216052[110:Res:216050.0,61.1] always3(s16) || -> . % 76.30/76.41 216053[110:SSi:216052.0,78137.0,78141.0,192115.0,215328.0,216043.0] || -> . % 76.30/76.41 216054[110:Spt:216053.0,216048.0,216050.0] || m_main_v_state(s16,c_busy)* -> . % 76.30/76.41 216055[110:Spt:216053.0,216048.1] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 216059[110:Res:216055.0,61.1] always3(s17) || -> . % 76.30/76.41 216060[110:SSi:216059.0,78142.0,78145.0,192116.0] || -> . % 76.30/76.41 216061[108:Spt:216060.0,215327.0,215328.0] || until2p7(s16)*+ -> . % 76.30/76.41 216062[108:Spt:216060.0,215327.1] || -> node4(s15)*. % 76.30/76.41 216064[108:MRR:873.0,216062.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.30/76.41 216067[108:Res:53.1,216064.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.30/76.41 216069[109:Spt:216067.0] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 216071[109:Res:216069.0,61.1] always3(s15) || -> . % 76.30/76.41 216072[109:SSi:216071.0,78133.0,78136.0,192114.0,215326.0,216062.0] || -> . % 76.30/76.41 216073[109:Spt:216072.0,216067.0,216069.0] || m_main_v_state(s15,c_busy)* -> . % 76.30/76.41 216074[109:Spt:216072.0,216067.1] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 216078[109:Res:216074.0,61.1] always3(s16) || -> . % 76.30/76.41 216079[109:SSi:216078.0,78137.0,78141.0,192115.0] || -> . % 76.30/76.41 216080[107:Spt:216079.0,215325.0,215326.0] || until2p7(s15)*+ -> . % 76.30/76.41 216081[107:Spt:216079.0,215325.1] || -> node4(s14)*. % 76.30/76.41 216083[107:MRR:876.0,216081.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.30/76.41 216086[107:Res:53.1,216083.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.30/76.41 216088[108:Spt:216086.0] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 216090[108:Res:216088.0,61.1] always3(s14) || -> . % 76.30/76.41 216091[108:SSi:216090.0,78128.0,78132.0,192113.0,215324.0,216081.0] || -> . % 76.30/76.41 216092[108:Spt:216091.0,216086.0,216088.0] || m_main_v_state(s14,c_busy)* -> . % 76.30/76.41 216093[108:Spt:216091.0,216086.1] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 216097[108:Res:216093.0,61.1] always3(s15) || -> . % 76.30/76.41 216098[108:SSi:216097.0,78133.0,78136.0,192114.0] || -> . % 76.30/76.41 216099[106:Spt:216098.0,215323.0,215324.0] || until2p7(s14)*+ -> . % 76.30/76.41 216100[106:Spt:216098.0,215323.1] || -> node4(s13)*. % 76.30/76.41 216102[106:MRR:879.0,216100.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.30/76.41 216105[106:Res:53.1,216102.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.30/76.41 216110[107:Spt:216105.0] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 216112[107:Res:216110.0,61.1] always3(s13) || -> . % 76.30/76.41 216113[107:SSi:216112.0,78124.0,78127.0,192112.0,215322.0,216100.0] || -> . % 76.30/76.41 216114[107:Spt:216113.0,216105.0,216110.0] || m_main_v_state(s13,c_busy)* -> . % 76.30/76.41 216115[107:Spt:216113.0,216105.1] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 216119[107:Res:216115.0,61.1] always3(s14) || -> . % 76.30/76.41 216120[107:SSi:216119.0,78128.0,78132.0,192113.0] || -> . % 76.30/76.41 216121[105:Spt:216120.0,215321.0,215322.0] || until2p7(s13)*+ -> . % 76.30/76.41 216122[105:Spt:216120.0,215321.1] || -> node4(s12)*. % 76.30/76.41 216124[105:MRR:882.0,216122.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.30/76.41 216127[105:Res:53.1,216124.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.30/76.41 216129[106:Spt:216127.0] || -> m_main_v_state(s12,c_busy)*. % 76.30/76.41 216131[106:Res:216129.0,61.1] always3(s12) || -> . % 76.30/76.41 216132[106:SSi:216131.0,78119.0,78123.0,192111.0,215320.0,216122.0] || -> . % 76.30/76.41 216133[106:Spt:216132.0,216127.0,216129.0] || m_main_v_state(s12,c_busy)* -> . % 76.30/76.41 216134[106:Spt:216132.0,216127.1] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 216138[106:Res:216134.0,61.1] always3(s13) || -> . % 76.30/76.41 216139[106:SSi:216138.0,78124.0,78127.0,192112.0] || -> . % 76.30/76.41 216140[104:Spt:216139.0,215319.0,215320.0] || until2p7(s12)*+ -> . % 76.30/76.41 216141[104:Spt:216139.0,215319.1] || -> node4(s11)*. % 76.30/76.41 216143[104:MRR:885.0,216141.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.30/76.41 216146[104:Res:53.1,216143.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.30/76.41 216148[105:Spt:216146.0] || -> m_main_v_state(s11,c_busy)*. % 76.30/76.41 216150[105:Res:216148.0,61.1] always3(s11) || -> . % 76.30/76.41 216151[105:SSi:216150.0,78115.0,78118.0,192110.0,215318.0,216141.0] || -> . % 76.30/76.41 216152[105:Spt:216151.0,216146.0,216148.0] || m_main_v_state(s11,c_busy)* -> . % 76.30/76.41 216153[105:Spt:216151.0,216146.1] || -> m_main_v_state(s12,c_busy)*. % 76.30/76.41 216157[105:Res:216153.0,61.1] always3(s12) || -> . % 76.30/76.41 216158[105:SSi:216157.0,78119.0,78123.0,192111.0] || -> . % 76.30/76.41 216159[103:Spt:216158.0,215317.0,215318.0] || until2p7(s11)*+ -> . % 76.30/76.41 216160[103:Spt:216158.0,215317.1] || -> node4(s10)*. % 76.30/76.41 216162[103:MRR:888.0,216160.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.30/76.41 216165[103:Res:53.1,216162.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.30/76.41 216167[104:Spt:216165.0] || -> m_main_v_state(s10,c_busy)*. % 76.30/76.41 216169[104:Res:216167.0,61.1] always3(s10) || -> . % 76.30/76.41 216170[104:SSi:216169.0,78110.0,78114.0,192109.0,215316.0,216160.0] || -> . % 76.30/76.41 216171[104:Spt:216170.0,216165.0,216167.0] || m_main_v_state(s10,c_busy)* -> . % 76.30/76.41 216172[104:Spt:216170.0,216165.1] || -> m_main_v_state(s11,c_busy)*. % 76.30/76.41 216176[104:Res:216172.0,61.1] always3(s11) || -> . % 76.30/76.41 216177[104:SSi:216176.0,78115.0,78118.0,192110.0] || -> . % 76.30/76.41 216178[102:Spt:216177.0,215315.0,215316.0] || until2p7(s10)*+ -> . % 76.30/76.41 216179[102:Spt:216177.0,215315.1] || -> node4(s9)*. % 76.30/76.41 216181[102:MRR:891.0,216179.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.30/76.41 216184[102:Res:53.1,216181.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.30/76.41 216189[103:Spt:216184.0] || -> m_main_v_state(s9,c_busy)*. % 76.30/76.41 216191[103:Res:216189.0,61.1] always3(s9) || -> . % 76.30/76.41 216192[103:SSi:216191.0,78106.0,78109.0,192108.0,215314.0,216179.0] || -> . % 76.30/76.41 216193[103:Spt:216192.0,216184.0,216189.0] || m_main_v_state(s9,c_busy)* -> . % 76.30/76.41 216194[103:Spt:216192.0,216184.1] || -> m_main_v_state(s10,c_busy)*. % 76.30/76.41 216198[103:Res:216194.0,61.1] always3(s10) || -> . % 76.30/76.41 216199[103:SSi:216198.0,78110.0,78114.0,192109.0] || -> . % 76.30/76.41 216200[101:Spt:216199.0,215313.0,215314.0] || until2p7(s9)*+ -> . % 76.30/76.41 216201[101:Spt:216199.0,215313.1] || -> node4(s8)*. % 76.30/76.41 216203[101:MRR:894.0,216201.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.30/76.41 216206[101:Res:53.1,216203.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.30/76.41 216208[102:Spt:216206.0] || -> m_main_v_state(s8,c_busy)*. % 76.30/76.41 216210[102:Res:216208.0,61.1] always3(s8) || -> . % 76.30/76.41 216211[102:SSi:216210.0,78101.0,78105.0,192107.0,215312.0,216201.0] || -> . % 76.30/76.41 216212[102:Spt:216211.0,216206.0,216208.0] || m_main_v_state(s8,c_busy)* -> . % 76.30/76.41 216213[102:Spt:216211.0,216206.1] || -> m_main_v_state(s9,c_busy)*. % 76.30/76.41 216217[102:Res:216213.0,61.1] always3(s9) || -> . % 76.30/76.41 216218[102:SSi:216217.0,78106.0,78109.0,192108.0] || -> . % 76.30/76.41 216219[100:Spt:216218.0,215311.0,215312.0] || until2p7(s8)*+ -> . % 76.30/76.41 216220[100:Spt:216218.0,215311.1] || -> node4(s7)*. % 76.30/76.41 216222[100:MRR:897.0,216220.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.30/76.41 216225[100:Res:53.1,216222.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.30/76.41 216227[100:MRR:216225.0,215301.0] || -> m_main_v_state(s8,c_busy)*. % 76.30/76.41 216229[100:Res:216227.0,61.1] always3(s8) || -> . % 76.30/76.41 216230[100:SSi:216229.0,78101.0,78105.0,192107.0] || -> . % 76.30/76.41 216231[98:Spt:216230.0,215144.0,215147.0] || trans(s49,s7)*+ -> . % 76.30/76.41 216232[98:Spt:216230.0,215144.1] || -> node2(s49,s6)*. % 76.30/76.41 216234[98:MRR:215146.1,216231.0] xuntil6(s49) || -> until2p7(s6)*. % 76.30/76.41 216235[98:Res:216232.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)*. % 76.30/76.41 216380[98:SoR:216235.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)*. % 76.30/76.41 216382[98:SoR:216380.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s6,c_busy)* xuntil6(s49). % 76.30/76.41 216383[98:SSi:216382.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s6,c_busy)* xuntil6(s49). % 76.30/76.41 216384[99:Spt:216383.1] || -> m_main_v_state(s6,c_busy)*. % 76.30/76.41 216386[99:Res:216384.0,61.1] always3(s6) || -> . % 76.30/76.41 216387[99:SSi:216386.0,78093.0,78096.0,192105.0] || -> . % 76.30/76.41 216388[99:Spt:216387.0,216383.1,216384.0] || m_main_v_state(s6,c_busy)*+ -> . % 76.30/76.41 216389[99:Spt:216387.0,216383.0,216383.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 216392[99:MRR:216380.2,216388.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 216393[99:Res:53.1,216389.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 216395[99:MRR:216393.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 216396[99:MRR:216234.0,216395.0] || -> until2p7(s6)*. % 76.30/76.41 216397[99:MRR:202.0,216396.0] || -> until2p7(s7)* node4(s6). % 76.30/76.41 216398[100:Spt:216397.0] || -> until2p7(s7)*. % 76.30/76.41 216399[100:MRR:203.0,216398.0] || -> until2p7(s8)* node4(s7). % 76.30/76.41 216400[101:Spt:216399.0] || -> until2p7(s8)*. % 76.30/76.41 216401[101:MRR:204.0,216400.0] || -> until2p7(s9)* node4(s8). % 76.30/76.41 216402[102:Spt:216401.0] || -> until2p7(s9)*. % 76.30/76.41 216403[102:MRR:205.0,216402.0] || -> until2p7(s10)* node4(s9). % 76.30/76.41 216404[103:Spt:216403.0] || -> until2p7(s10)*. % 76.30/76.41 216405[103:MRR:206.0,216404.0] || -> until2p7(s11)* node4(s10). % 76.30/76.41 216406[104:Spt:216405.0] || -> until2p7(s11)*. % 76.30/76.41 216407[104:MRR:207.0,216406.0] || -> until2p7(s12)* node4(s11). % 76.30/76.41 216408[105:Spt:216407.0] || -> until2p7(s12)*. % 76.30/76.41 216409[105:MRR:208.0,216408.0] || -> until2p7(s13)* node4(s12). % 76.30/76.41 216410[106:Spt:216409.0] || -> until2p7(s13)*. % 76.30/76.41 216411[106:MRR:209.0,216410.0] || -> until2p7(s14)* node4(s13). % 76.30/76.41 216412[107:Spt:216411.0] || -> until2p7(s14)*. % 76.30/76.41 216413[107:MRR:210.0,216412.0] || -> until2p7(s15)* node4(s14). % 76.30/76.41 216414[108:Spt:216413.0] || -> until2p7(s15)*. % 76.30/76.41 216415[108:MRR:211.0,216414.0] || -> until2p7(s16)* node4(s15). % 76.30/76.41 216416[109:Spt:216415.0] || -> until2p7(s16)*. % 76.30/76.41 216417[109:MRR:212.0,216416.0] || -> until2p7(s17)* node4(s16). % 76.30/76.41 216418[110:Spt:216417.0] || -> until2p7(s17)*. % 76.30/76.41 216419[110:MRR:213.0,216418.0] || -> until2p7(s18)* node4(s17). % 76.30/76.41 216420[111:Spt:216419.0] || -> until2p7(s18)*. % 76.30/76.41 216421[111:MRR:214.0,216420.0] || -> until2p7(s19)* node4(s18). % 76.30/76.41 216422[112:Spt:216421.0] || -> until2p7(s19)*. % 76.30/76.41 216423[112:MRR:215.0,216422.0] || -> until2p7(s20)* node4(s19). % 76.30/76.41 216424[113:Spt:216423.0] || -> until2p7(s20)*. % 76.30/76.41 216425[113:MRR:216.0,216424.0] || -> until2p7(s21)* node4(s20). % 76.30/76.41 216426[114:Spt:216425.0] || -> until2p7(s21)*. % 76.30/76.41 216427[114:MRR:217.0,216426.0] || -> until2p7(s22)* node4(s21). % 76.30/76.41 216428[115:Spt:216427.0] || -> until2p7(s22)*. % 76.30/76.41 216429[115:MRR:218.0,216428.0] || -> until2p7(s23)* node4(s22). % 76.30/76.41 216430[116:Spt:216429.0] || -> until2p7(s23)*. % 76.30/76.41 216431[116:MRR:219.0,216430.0] || -> until2p7(s24)* node4(s23). % 76.30/76.41 216432[117:Spt:216431.0] || -> until2p7(s24)*. % 76.30/76.41 216433[117:MRR:220.0,216432.0] || -> until2p7(s25)* node4(s24). % 76.30/76.41 216434[118:Spt:216433.0] || -> until2p7(s25)*. % 76.30/76.41 216435[118:MRR:221.0,216434.0] || -> until2p7(s26)* node4(s25). % 76.30/76.41 216436[119:Spt:216435.0] || -> until2p7(s26)*. % 76.30/76.41 216437[119:MRR:222.0,216436.0] || -> until2p7(s27)* node4(s26). % 76.30/76.41 216438[120:Spt:216437.0] || -> until2p7(s27)*. % 76.30/76.41 216439[120:MRR:223.0,216438.0] || -> until2p7(s28)* node4(s27). % 76.30/76.41 216440[121:Spt:216439.0] || -> until2p7(s28)*. % 76.30/76.41 216441[121:MRR:224.0,216440.0] || -> until2p7(s29)* node4(s28). % 76.30/76.41 216442[122:Spt:216441.0] || -> until2p7(s29)*. % 76.30/76.41 216443[122:MRR:225.0,216442.0] || -> until2p7(s30)* node4(s29). % 76.30/76.41 216444[123:Spt:216443.0] || -> until2p7(s30)*. % 76.30/76.41 216445[123:MRR:226.0,216444.0] || -> until2p7(s31)* node4(s30). % 76.30/76.41 216446[124:Spt:216445.0] || -> until2p7(s31)*. % 76.30/76.41 216447[124:MRR:227.0,216446.0] || -> until2p7(s32)* node4(s31). % 76.30/76.41 216448[125:Spt:216447.0] || -> until2p7(s32)*. % 76.30/76.41 216449[125:MRR:228.0,216448.0] || -> until2p7(s33)* node4(s32). % 76.30/76.41 216450[126:Spt:216449.0] || -> until2p7(s33)*. % 76.30/76.41 216451[126:MRR:229.0,216450.0] || -> until2p7(s34)* node4(s33). % 76.30/76.41 216452[127:Spt:216451.0] || -> until2p7(s34)*. % 76.30/76.41 216453[127:MRR:230.0,216452.0] || -> until2p7(s35)* node4(s34). % 76.30/76.41 216454[128:Spt:216453.0] || -> until2p7(s35)*. % 76.30/76.41 216455[128:MRR:231.0,216454.0] || -> until2p7(s36)* node4(s35). % 76.30/76.41 216456[129:Spt:216455.0] || -> until2p7(s36)*. % 76.30/76.41 216457[129:MRR:232.0,216456.0] || -> until2p7(s37)* node4(s36). % 76.30/76.41 216458[130:Spt:216457.0] || -> until2p7(s37)*. % 76.30/76.41 216459[130:MRR:235.0,216458.0] || -> until2p7(s38)* node4(s37). % 76.30/76.41 216460[131:Spt:216459.0] || -> until2p7(s38)*. % 76.30/76.41 216461[131:MRR:236.0,216460.0] || -> until2p7(s39)* node4(s38). % 76.30/76.41 216462[132:Spt:216461.0] || -> until2p7(s39)*. % 76.30/76.41 216463[132:MRR:237.0,216462.0] || -> until2p7(s40)* node4(s39). % 76.30/76.41 216464[133:Spt:216463.0] || -> until2p7(s40)*. % 76.30/76.41 216465[133:MRR:238.0,216464.0] || -> until2p7(s41)* node4(s40). % 76.30/76.41 216466[134:Spt:216465.0] || -> until2p7(s41)*. % 76.30/76.41 216467[134:MRR:239.0,216466.0] || -> until2p7(s42)* node4(s41). % 76.30/76.41 216468[135:Spt:216467.0] || -> until2p7(s42)*. % 76.30/76.41 216469[135:MRR:240.0,216468.0] || -> until2p7(s43)* node4(s42). % 76.30/76.41 216470[136:Spt:216469.0] || -> until2p7(s43)*. % 76.30/76.41 216471[136:MRR:241.0,216470.0] || -> until2p7(s44)* node4(s43). % 76.30/76.41 216472[137:Spt:216471.0] || -> until2p7(s44)*. % 76.30/76.41 216473[137:MRR:539.0,216472.0] || -> until2p7(s45)* node4(s44). % 76.30/76.41 216474[138:Spt:216473.0] || -> until2p7(s45)*. % 76.30/76.41 216475[138:MRR:544.0,216474.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 216476[139:Spt:216475.0] || -> until2p7(s46)*. % 76.30/76.41 216477[139:MRR:549.0,216476.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 216478[140:Spt:216477.0] || -> until2p7(s47)*. % 76.30/76.41 216479[140:MRR:554.0,216478.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 216480[141:Spt:216479.0] || -> until2p7(s48)*. % 76.30/76.41 216481[141:MRR:559.0,216480.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 216482[142:Spt:216481.0] || -> until2p7(s49)*. % 76.30/76.41 216483[142:MRR:194.0,216482.0] || -> node4(s49)*. % 76.30/76.41 216484[142:MRR:216392.0,216483.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 216488[142:Res:53.1,216484.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 216490[142:MRR:216488.0,78381.0] || -> . % 76.30/76.41 216491[142:Spt:216490.0,216481.0,216482.0] || until2p7(s49)*+ -> . % 76.30/76.41 216492[142:Spt:216490.0,216481.1] || -> node4(s48)*. % 76.30/76.41 216493[142:MRR:78384.0,216492.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 216496[142:Res:53.1,216493.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 216499[142:Res:216496.0,61.1] always3(s48) || -> . % 76.30/76.41 216500[142:SSi:216499.0,78281.0,78387.0,192147.0,216480.0,216492.0] || -> . % 76.30/76.41 216501[141:Spt:216500.0,216479.0,216480.0] || until2p7(s48)*+ -> . % 76.30/76.41 216502[141:Spt:216500.0,216479.1] || -> node4(s47)*. % 76.30/76.41 216504[141:MRR:777.0,216502.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 216518[141:Res:53.1,216504.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 216520[142:Spt:216518.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 216522[142:Res:216520.0,61.1] always3(s47) || -> . % 76.30/76.41 216523[142:SSi:216522.0,78277.0,78280.0,192146.0,216478.0,216502.0] || -> . % 76.30/76.41 216524[142:Spt:216523.0,216518.0,216520.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 216525[142:Spt:216523.0,216518.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 216529[142:Res:216525.0,61.1] always3(s48) || -> . % 76.30/76.41 216530[142:SSi:216529.0,78281.0,78387.0,192147.0] || -> . % 76.30/76.41 216531[140:Spt:216530.0,216477.0,216478.0] || until2p7(s47)*+ -> . % 76.30/76.41 216532[140:Spt:216530.0,216477.1] || -> node4(s46)*. % 76.30/76.41 216534[140:MRR:780.0,216532.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 216541[140:Res:53.1,216534.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 216546[141:Spt:216541.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 216548[141:Res:216546.0,61.1] always3(s46) || -> . % 76.30/76.41 216549[141:SSi:216548.0,78272.0,78276.0,192145.0,216476.0,216532.0] || -> . % 76.30/76.41 216550[141:Spt:216549.0,216541.0,216546.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 216551[141:Spt:216549.0,216541.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 216555[141:Res:216551.0,61.1] always3(s47) || -> . % 76.30/76.41 216556[141:SSi:216555.0,78277.0,78280.0,192146.0] || -> . % 76.30/76.41 216557[139:Spt:216556.0,216475.0,216476.0] || until2p7(s46)*+ -> . % 76.30/76.41 216558[139:Spt:216556.0,216475.1] || -> node4(s45)*. % 76.30/76.41 216560[139:MRR:783.0,216558.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 216563[139:Res:53.1,216560.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 216565[140:Spt:216563.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 216567[140:Res:216565.0,61.1] always3(s45) || -> . % 76.30/76.41 216568[140:SSi:216567.0,78268.0,78271.0,192144.0,216474.0,216558.0] || -> . % 76.30/76.41 216569[140:Spt:216568.0,216563.0,216565.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.41 216570[140:Spt:216568.0,216563.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 216574[140:Res:216570.0,61.1] always3(s46) || -> . % 76.30/76.41 216575[140:SSi:216574.0,78272.0,78276.0,192145.0] || -> . % 76.30/76.41 216576[138:Spt:216575.0,216473.0,216474.0] || until2p7(s45)*+ -> . % 76.30/76.41 216577[138:Spt:216575.0,216473.1] || -> node4(s44)*. % 76.30/76.41 216579[138:MRR:786.0,216577.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.41 216582[138:Res:53.1,216579.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.41 216584[139:Spt:216582.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 216586[139:Res:216584.0,61.1] always3(s44) || -> . % 76.30/76.41 216587[139:SSi:216586.0,78263.0,78267.0,192143.0,216472.0,216577.0] || -> . % 76.30/76.41 216588[139:Spt:216587.0,216582.0,216584.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.41 216589[139:Spt:216587.0,216582.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 216593[139:Res:216589.0,61.1] always3(s45) || -> . % 76.30/76.41 216594[139:SSi:216593.0,78268.0,78271.0,192144.0] || -> . % 76.30/76.41 216595[137:Spt:216594.0,216471.0,216472.0] || until2p7(s44)*+ -> . % 76.30/76.41 216596[137:Spt:216594.0,216471.1] || -> node4(s43)*. % 76.30/76.41 216598[137:MRR:789.0,216596.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.41 216601[137:Res:53.1,216598.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.41 216603[138:Spt:216601.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 216605[138:Res:216603.0,61.1] always3(s43) || -> . % 76.30/76.41 216606[138:SSi:216605.0,78259.0,78262.0,192142.0,216470.0,216596.0] || -> . % 76.30/76.41 216607[138:Spt:216606.0,216601.0,216603.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.41 216608[138:Spt:216606.0,216601.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 216612[138:Res:216608.0,61.1] always3(s44) || -> . % 76.30/76.41 216613[138:SSi:216612.0,78263.0,78267.0,192143.0] || -> . % 76.30/76.41 216614[136:Spt:216613.0,216469.0,216470.0] || until2p7(s43)*+ -> . % 76.30/76.41 216615[136:Spt:216613.0,216469.1] || -> node4(s42)*. % 76.30/76.41 216617[136:MRR:792.0,216615.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.41 216620[136:Res:53.1,216617.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.41 216625[137:Spt:216620.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 216627[137:Res:216625.0,61.1] always3(s42) || -> . % 76.30/76.41 216628[137:SSi:216627.0,78254.0,78258.0,192141.0,216468.0,216615.0] || -> . % 76.30/76.41 216629[137:Spt:216628.0,216620.0,216625.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.41 216630[137:Spt:216628.0,216620.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 216634[137:Res:216630.0,61.1] always3(s43) || -> . % 76.30/76.41 216635[137:SSi:216634.0,78259.0,78262.0,192142.0] || -> . % 76.30/76.41 216636[135:Spt:216635.0,216467.0,216468.0] || until2p7(s42)*+ -> . % 76.30/76.41 216637[135:Spt:216635.0,216467.1] || -> node4(s41)*. % 76.30/76.41 216639[135:MRR:795.0,216637.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.41 216642[135:Res:53.1,216639.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.41 216644[136:Spt:216642.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 216646[136:Res:216644.0,61.1] always3(s41) || -> . % 76.30/76.41 216647[136:SSi:216646.0,78250.0,78253.0,192140.0,216466.0,216637.0] || -> . % 76.30/76.41 216648[136:Spt:216647.0,216642.0,216644.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.41 216649[136:Spt:216647.0,216642.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 216653[136:Res:216649.0,61.1] always3(s42) || -> . % 76.30/76.41 216654[136:SSi:216653.0,78254.0,78258.0,192141.0] || -> . % 76.30/76.41 216655[134:Spt:216654.0,216465.0,216466.0] || until2p7(s41)*+ -> . % 76.30/76.41 216656[134:Spt:216654.0,216465.1] || -> node4(s40)*. % 76.30/76.41 216658[134:MRR:798.0,216656.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.41 216661[134:Res:53.1,216658.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.41 216663[135:Spt:216661.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 216665[135:Res:216663.0,61.1] always3(s40) || -> . % 76.30/76.41 216666[135:SSi:216665.0,78245.0,78249.0,192139.0,216464.0,216656.0] || -> . % 76.30/76.41 216667[135:Spt:216666.0,216661.0,216663.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.41 216668[135:Spt:216666.0,216661.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 216672[135:Res:216668.0,61.1] always3(s41) || -> . % 76.30/76.41 216673[135:SSi:216672.0,78250.0,78253.0,192140.0] || -> . % 76.30/76.41 216674[133:Spt:216673.0,216463.0,216464.0] || until2p7(s40)*+ -> . % 76.30/76.41 216675[133:Spt:216673.0,216463.1] || -> node4(s39)*. % 76.30/76.41 216677[133:MRR:801.0,216675.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.41 216680[133:Res:53.1,216677.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.41 216682[134:Spt:216680.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 216684[134:Res:216682.0,61.1] always3(s39) || -> . % 76.30/76.41 216685[134:SSi:216684.0,78241.0,78244.0,192138.0,216462.0,216675.0] || -> . % 76.30/76.41 216686[134:Spt:216685.0,216680.0,216682.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.41 216687[134:Spt:216685.0,216680.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 216691[134:Res:216687.0,61.1] always3(s40) || -> . % 76.30/76.41 216692[134:SSi:216691.0,78245.0,78249.0,192139.0] || -> . % 76.30/76.41 216693[132:Spt:216692.0,216461.0,216462.0] || until2p7(s39)*+ -> . % 76.30/76.41 216694[132:Spt:216692.0,216461.1] || -> node4(s38)*. % 76.30/76.41 216696[132:MRR:804.0,216694.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.41 216699[132:Res:53.1,216696.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.41 216704[133:Spt:216699.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 216706[133:Res:216704.0,61.1] always3(s38) || -> . % 76.30/76.41 216707[133:SSi:216706.0,78236.0,78240.0,192137.0,216460.0,216694.0] || -> . % 76.30/76.41 216708[133:Spt:216707.0,216699.0,216704.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.41 216709[133:Spt:216707.0,216699.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 216713[133:Res:216709.0,61.1] always3(s39) || -> . % 76.30/76.41 216714[133:SSi:216713.0,78241.0,78244.0,192138.0] || -> . % 76.30/76.41 216715[131:Spt:216714.0,216459.0,216460.0] || until2p7(s38)*+ -> . % 76.30/76.41 216716[131:Spt:216714.0,216459.1] || -> node4(s37)*. % 76.30/76.41 216718[131:MRR:807.0,216716.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.41 216721[131:Res:53.1,216718.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.41 216723[132:Spt:216721.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 216725[132:Res:216723.0,61.1] always3(s37) || -> . % 76.30/76.41 216726[132:SSi:216725.0,78232.0,78235.0,192136.0,216458.0,216716.0] || -> . % 76.30/76.41 216727[132:Spt:216726.0,216721.0,216723.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.41 216728[132:Spt:216726.0,216721.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.41 216732[132:Res:216728.0,61.1] always3(s38) || -> . % 76.30/76.41 216733[132:SSi:216732.0,78236.0,78240.0,192137.0] || -> . % 76.30/76.41 216734[130:Spt:216733.0,216457.0,216458.0] || until2p7(s37)*+ -> . % 76.30/76.41 216735[130:Spt:216733.0,216457.1] || -> node4(s36)*. % 76.30/76.41 216737[130:MRR:810.0,216735.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.41 216740[130:Res:53.1,216737.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.41 216742[131:Spt:216740.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 216744[131:Res:216742.0,61.1] always3(s36) || -> . % 76.30/76.41 216745[131:SSi:216744.0,78227.0,78231.0,192135.0,216456.0,216735.0] || -> . % 76.30/76.41 216746[131:Spt:216745.0,216740.0,216742.0] || m_main_v_state(s36,c_busy)* -> . % 76.30/76.41 216747[131:Spt:216745.0,216740.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.41 216751[131:Res:216747.0,61.1] always3(s37) || -> . % 76.30/76.41 216752[131:SSi:216751.0,78232.0,78235.0,192136.0] || -> . % 76.30/76.41 216753[129:Spt:216752.0,216455.0,216456.0] || until2p7(s36)*+ -> . % 76.30/76.41 216754[129:Spt:216752.0,216455.1] || -> node4(s35)*. % 76.30/76.41 216756[129:MRR:813.0,216754.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.30/76.41 216759[129:Res:53.1,216756.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.30/76.41 216761[130:Spt:216759.0] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 216763[130:Res:216761.0,61.1] always3(s35) || -> . % 76.30/76.41 216764[130:SSi:216763.0,78223.0,78226.0,192134.0,216454.0,216754.0] || -> . % 76.30/76.41 216765[130:Spt:216764.0,216759.0,216761.0] || m_main_v_state(s35,c_busy)* -> . % 76.30/76.41 216766[130:Spt:216764.0,216759.1] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.41 216770[130:Res:216766.0,61.1] always3(s36) || -> . % 76.30/76.41 216771[130:SSi:216770.0,78227.0,78231.0,192135.0] || -> . % 76.30/76.41 216772[128:Spt:216771.0,216453.0,216454.0] || until2p7(s35)*+ -> . % 76.30/76.41 216773[128:Spt:216771.0,216453.1] || -> node4(s34)*. % 76.30/76.41 216775[128:MRR:816.0,216773.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.30/76.41 216778[128:Res:53.1,216775.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.30/76.41 216783[129:Spt:216778.0] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 216785[129:Res:216783.0,61.1] always3(s34) || -> . % 76.30/76.41 216786[129:SSi:216785.0,78218.0,78222.0,192133.0,216452.0,216773.0] || -> . % 76.30/76.41 216787[129:Spt:216786.0,216778.0,216783.0] || m_main_v_state(s34,c_busy)* -> . % 76.30/76.41 216788[129:Spt:216786.0,216778.1] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.41 216792[129:Res:216788.0,61.1] always3(s35) || -> . % 76.30/76.41 216793[129:SSi:216792.0,78223.0,78226.0,192134.0] || -> . % 76.30/76.41 216794[127:Spt:216793.0,216451.0,216452.0] || until2p7(s34)*+ -> . % 76.30/76.41 216795[127:Spt:216793.0,216451.1] || -> node4(s33)*. % 76.30/76.41 216797[127:MRR:819.0,216795.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.30/76.41 216800[127:Res:53.1,216797.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.30/76.41 216802[128:Spt:216800.0] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 216804[128:Res:216802.0,61.1] always3(s33) || -> . % 76.30/76.41 216805[128:SSi:216804.0,78214.0,78217.0,192132.0,216450.0,216795.0] || -> . % 76.30/76.41 216806[128:Spt:216805.0,216800.0,216802.0] || m_main_v_state(s33,c_busy)* -> . % 76.30/76.41 216807[128:Spt:216805.0,216800.1] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.41 216811[128:Res:216807.0,61.1] always3(s34) || -> . % 76.30/76.41 216812[128:SSi:216811.0,78218.0,78222.0,192133.0] || -> . % 76.30/76.41 216813[126:Spt:216812.0,216449.0,216450.0] || until2p7(s33)*+ -> . % 76.30/76.41 216814[126:Spt:216812.0,216449.1] || -> node4(s32)*. % 76.30/76.41 216816[126:MRR:822.0,216814.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.30/76.41 216819[126:Res:53.1,216816.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.30/76.41 216821[127:Spt:216819.0] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 216823[127:Res:216821.0,61.1] always3(s32) || -> . % 76.30/76.41 216824[127:SSi:216823.0,78209.0,78213.0,192131.0,216448.0,216814.0] || -> . % 76.30/76.41 216825[127:Spt:216824.0,216819.0,216821.0] || m_main_v_state(s32,c_busy)* -> . % 76.30/76.41 216826[127:Spt:216824.0,216819.1] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.41 216830[127:Res:216826.0,61.1] always3(s33) || -> . % 76.30/76.41 216831[127:SSi:216830.0,78214.0,78217.0,192132.0] || -> . % 76.30/76.41 216832[125:Spt:216831.0,216447.0,216448.0] || until2p7(s32)*+ -> . % 76.30/76.41 216833[125:Spt:216831.0,216447.1] || -> node4(s31)*. % 76.30/76.41 216835[125:MRR:825.0,216833.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.30/76.41 216838[125:Res:53.1,216835.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.30/76.41 216840[126:Spt:216838.0] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 216842[126:Res:216840.0,61.1] always3(s31) || -> . % 76.30/76.41 216843[126:SSi:216842.0,78205.0,78208.0,192130.0,216446.0,216833.0] || -> . % 76.30/76.41 216844[126:Spt:216843.0,216838.0,216840.0] || m_main_v_state(s31,c_busy)* -> . % 76.30/76.41 216845[126:Spt:216843.0,216838.1] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.41 216849[126:Res:216845.0,61.1] always3(s32) || -> . % 76.30/76.41 216850[126:SSi:216849.0,78209.0,78213.0,192131.0] || -> . % 76.30/76.41 216851[124:Spt:216850.0,216445.0,216446.0] || until2p7(s31)*+ -> . % 76.30/76.41 216852[124:Spt:216850.0,216445.1] || -> node4(s30)*. % 76.30/76.41 216854[124:MRR:828.0,216852.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.30/76.41 216857[124:Res:53.1,216854.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.30/76.41 216862[125:Spt:216857.0] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 216864[125:Res:216862.0,61.1] always3(s30) || -> . % 76.30/76.41 216865[125:SSi:216864.0,78200.0,78204.0,192129.0,216444.0,216852.0] || -> . % 76.30/76.41 216866[125:Spt:216865.0,216857.0,216862.0] || m_main_v_state(s30,c_busy)* -> . % 76.30/76.41 216867[125:Spt:216865.0,216857.1] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.41 216871[125:Res:216867.0,61.1] always3(s31) || -> . % 76.30/76.41 216872[125:SSi:216871.0,78205.0,78208.0,192130.0] || -> . % 76.30/76.41 216873[123:Spt:216872.0,216443.0,216444.0] || until2p7(s30)*+ -> . % 76.30/76.41 216874[123:Spt:216872.0,216443.1] || -> node4(s29)*. % 76.30/76.41 216876[123:MRR:831.0,216874.0] || m_main_v_state(s29,c_ready)*+ -> m_main_v_state(s30,c_busy). % 76.30/76.41 216879[123:Res:53.1,216876.0] || -> m_main_v_state(s29,c_busy)* m_main_v_state(s30,c_busy). % 76.30/76.41 216881[124:Spt:216879.0] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 216883[124:Res:216881.0,61.1] always3(s29) || -> . % 76.30/76.41 216884[124:SSi:216883.0,78196.0,78199.0,192128.0,216442.0,216874.0] || -> . % 76.30/76.41 216885[124:Spt:216884.0,216879.0,216881.0] || m_main_v_state(s29,c_busy)* -> . % 76.30/76.41 216886[124:Spt:216884.0,216879.1] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.41 216890[124:Res:216886.0,61.1] always3(s30) || -> . % 76.30/76.41 216891[124:SSi:216890.0,78200.0,78204.0,192129.0] || -> . % 76.30/76.41 216892[122:Spt:216891.0,216441.0,216442.0] || until2p7(s29)*+ -> . % 76.30/76.41 216893[122:Spt:216891.0,216441.1] || -> node4(s28)*. % 76.30/76.41 216895[122:MRR:834.0,216893.0] || m_main_v_state(s28,c_ready)*+ -> m_main_v_state(s29,c_busy). % 76.30/76.41 216898[122:Res:53.1,216895.0] || -> m_main_v_state(s28,c_busy)* m_main_v_state(s29,c_busy). % 76.30/76.41 216900[123:Spt:216898.0] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 216902[123:Res:216900.0,61.1] always3(s28) || -> . % 76.30/76.41 216903[123:SSi:216902.0,78191.0,78195.0,192127.0,216440.0,216893.0] || -> . % 76.30/76.41 216904[123:Spt:216903.0,216898.0,216900.0] || m_main_v_state(s28,c_busy)* -> . % 76.30/76.41 216905[123:Spt:216903.0,216898.1] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.41 216909[123:Res:216905.0,61.1] always3(s29) || -> . % 76.30/76.41 216910[123:SSi:216909.0,78196.0,78199.0,192128.0] || -> . % 76.30/76.41 216911[121:Spt:216910.0,216439.0,216440.0] || until2p7(s28)*+ -> . % 76.30/76.41 216912[121:Spt:216910.0,216439.1] || -> node4(s27)*. % 76.30/76.41 216914[121:MRR:837.0,216912.0] || m_main_v_state(s27,c_ready)*+ -> m_main_v_state(s28,c_busy). % 76.30/76.41 216917[121:Res:53.1,216914.0] || -> m_main_v_state(s27,c_busy)* m_main_v_state(s28,c_busy). % 76.30/76.41 216919[122:Spt:216917.0] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 216921[122:Res:216919.0,61.1] always3(s27) || -> . % 76.30/76.41 216922[122:SSi:216921.0,78187.0,78190.0,192126.0,216438.0,216912.0] || -> . % 76.30/76.41 216923[122:Spt:216922.0,216917.0,216919.0] || m_main_v_state(s27,c_busy)* -> . % 76.30/76.41 216924[122:Spt:216922.0,216917.1] || -> m_main_v_state(s28,c_busy)*. % 76.30/76.41 216928[122:Res:216924.0,61.1] always3(s28) || -> . % 76.30/76.41 216929[122:SSi:216928.0,78191.0,78195.0,192127.0] || -> . % 76.30/76.41 216930[120:Spt:216929.0,216437.0,216438.0] || until2p7(s27)*+ -> . % 76.30/76.41 216931[120:Spt:216929.0,216437.1] || -> node4(s26)*. % 76.30/76.41 216933[120:MRR:840.0,216931.0] || m_main_v_state(s26,c_ready)*+ -> m_main_v_state(s27,c_busy). % 76.30/76.41 216936[120:Res:53.1,216933.0] || -> m_main_v_state(s26,c_busy)* m_main_v_state(s27,c_busy). % 76.30/76.41 216941[121:Spt:216936.0] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 216943[121:Res:216941.0,61.1] always3(s26) || -> . % 76.30/76.41 216944[121:SSi:216943.0,78182.0,78186.0,192125.0,216436.0,216931.0] || -> . % 76.30/76.41 216945[121:Spt:216944.0,216936.0,216941.0] || m_main_v_state(s26,c_busy)* -> . % 76.30/76.41 216946[121:Spt:216944.0,216936.1] || -> m_main_v_state(s27,c_busy)*. % 76.30/76.41 216950[121:Res:216946.0,61.1] always3(s27) || -> . % 76.30/76.41 216951[121:SSi:216950.0,78187.0,78190.0,192126.0] || -> . % 76.30/76.41 216952[119:Spt:216951.0,216435.0,216436.0] || until2p7(s26)*+ -> . % 76.30/76.41 216953[119:Spt:216951.0,216435.1] || -> node4(s25)*. % 76.30/76.41 216955[119:MRR:843.0,216953.0] || m_main_v_state(s25,c_ready)*+ -> m_main_v_state(s26,c_busy). % 76.30/76.41 216958[119:Res:53.1,216955.0] || -> m_main_v_state(s25,c_busy)* m_main_v_state(s26,c_busy). % 76.30/76.41 216960[120:Spt:216958.0] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 216962[120:Res:216960.0,61.1] always3(s25) || -> . % 76.30/76.41 216963[120:SSi:216962.0,78178.0,78181.0,192124.0,216434.0,216953.0] || -> . % 76.30/76.41 216964[120:Spt:216963.0,216958.0,216960.0] || m_main_v_state(s25,c_busy)* -> . % 76.30/76.41 216965[120:Spt:216963.0,216958.1] || -> m_main_v_state(s26,c_busy)*. % 76.30/76.41 216969[120:Res:216965.0,61.1] always3(s26) || -> . % 76.30/76.41 216970[120:SSi:216969.0,78182.0,78186.0,192125.0] || -> . % 76.30/76.41 216971[118:Spt:216970.0,216433.0,216434.0] || until2p7(s25)*+ -> . % 76.30/76.41 216972[118:Spt:216970.0,216433.1] || -> node4(s24)*. % 76.30/76.41 216974[118:MRR:846.0,216972.0] || m_main_v_state(s24,c_ready)*+ -> m_main_v_state(s25,c_busy). % 76.30/76.41 216977[118:Res:53.1,216974.0] || -> m_main_v_state(s24,c_busy)* m_main_v_state(s25,c_busy). % 76.30/76.41 216979[119:Spt:216977.0] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 216981[119:Res:216979.0,61.1] always3(s24) || -> . % 76.30/76.41 216982[119:SSi:216981.0,78173.0,78177.0,192123.0,216432.0,216972.0] || -> . % 76.30/76.41 216983[119:Spt:216982.0,216977.0,216979.0] || m_main_v_state(s24,c_busy)* -> . % 76.30/76.41 216984[119:Spt:216982.0,216977.1] || -> m_main_v_state(s25,c_busy)*. % 76.30/76.41 216988[119:Res:216984.0,61.1] always3(s25) || -> . % 76.30/76.41 216989[119:SSi:216988.0,78178.0,78181.0,192124.0] || -> . % 76.30/76.41 216990[117:Spt:216989.0,216431.0,216432.0] || until2p7(s24)*+ -> . % 76.30/76.41 216991[117:Spt:216989.0,216431.1] || -> node4(s23)*. % 76.30/76.41 216993[117:MRR:849.0,216991.0] || m_main_v_state(s23,c_ready)*+ -> m_main_v_state(s24,c_busy). % 76.30/76.41 216996[117:Res:53.1,216993.0] || -> m_main_v_state(s23,c_busy)* m_main_v_state(s24,c_busy). % 76.30/76.41 216998[118:Spt:216996.0] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 217000[118:Res:216998.0,61.1] always3(s23) || -> . % 76.30/76.41 217001[118:SSi:217000.0,78169.0,78172.0,192122.0,216430.0,216991.0] || -> . % 76.30/76.41 217002[118:Spt:217001.0,216996.0,216998.0] || m_main_v_state(s23,c_busy)* -> . % 76.30/76.41 217003[118:Spt:217001.0,216996.1] || -> m_main_v_state(s24,c_busy)*. % 76.30/76.41 217007[118:Res:217003.0,61.1] always3(s24) || -> . % 76.30/76.41 217008[118:SSi:217007.0,78173.0,78177.0,192123.0] || -> . % 76.30/76.41 217009[116:Spt:217008.0,216429.0,216430.0] || until2p7(s23)*+ -> . % 76.30/76.41 217010[116:Spt:217008.0,216429.1] || -> node4(s22)*. % 76.30/76.41 217012[116:MRR:852.0,217010.0] || m_main_v_state(s22,c_ready)*+ -> m_main_v_state(s23,c_busy). % 76.30/76.41 217015[116:Res:53.1,217012.0] || -> m_main_v_state(s22,c_busy)* m_main_v_state(s23,c_busy). % 76.30/76.41 217020[117:Spt:217015.0] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 217022[117:Res:217020.0,61.1] always3(s22) || -> . % 76.30/76.41 217023[117:SSi:217022.0,78164.0,78168.0,192121.0,216428.0,217010.0] || -> . % 76.30/76.41 217024[117:Spt:217023.0,217015.0,217020.0] || m_main_v_state(s22,c_busy)* -> . % 76.30/76.41 217025[117:Spt:217023.0,217015.1] || -> m_main_v_state(s23,c_busy)*. % 76.30/76.41 217029[117:Res:217025.0,61.1] always3(s23) || -> . % 76.30/76.41 217030[117:SSi:217029.0,78169.0,78172.0,192122.0] || -> . % 76.30/76.41 217031[115:Spt:217030.0,216427.0,216428.0] || until2p7(s22)*+ -> . % 76.30/76.41 217032[115:Spt:217030.0,216427.1] || -> node4(s21)*. % 76.30/76.41 217034[115:MRR:855.0,217032.0] || m_main_v_state(s21,c_ready)*+ -> m_main_v_state(s22,c_busy). % 76.30/76.41 217037[115:Res:53.1,217034.0] || -> m_main_v_state(s21,c_busy)* m_main_v_state(s22,c_busy). % 76.30/76.41 217039[116:Spt:217037.0] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 217041[116:Res:217039.0,61.1] always3(s21) || -> . % 76.30/76.41 217042[116:SSi:217041.0,78160.0,78163.0,192120.0,216426.0,217032.0] || -> . % 76.30/76.41 217043[116:Spt:217042.0,217037.0,217039.0] || m_main_v_state(s21,c_busy)* -> . % 76.30/76.41 217044[116:Spt:217042.0,217037.1] || -> m_main_v_state(s22,c_busy)*. % 76.30/76.41 217048[116:Res:217044.0,61.1] always3(s22) || -> . % 76.30/76.41 217049[116:SSi:217048.0,78164.0,78168.0,192121.0] || -> . % 76.30/76.41 217050[114:Spt:217049.0,216425.0,216426.0] || until2p7(s21)*+ -> . % 76.30/76.41 217051[114:Spt:217049.0,216425.1] || -> node4(s20)*. % 76.30/76.41 217053[114:MRR:858.0,217051.0] || m_main_v_state(s20,c_ready)*+ -> m_main_v_state(s21,c_busy). % 76.30/76.41 217056[114:Res:53.1,217053.0] || -> m_main_v_state(s20,c_busy)* m_main_v_state(s21,c_busy). % 76.30/76.41 217058[115:Spt:217056.0] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 217060[115:Res:217058.0,61.1] always3(s20) || -> . % 76.30/76.41 217061[115:SSi:217060.0,78155.0,78159.0,192119.0,216424.0,217051.0] || -> . % 76.30/76.41 217062[115:Spt:217061.0,217056.0,217058.0] || m_main_v_state(s20,c_busy)* -> . % 76.30/76.41 217063[115:Spt:217061.0,217056.1] || -> m_main_v_state(s21,c_busy)*. % 76.30/76.41 217067[115:Res:217063.0,61.1] always3(s21) || -> . % 76.30/76.41 217068[115:SSi:217067.0,78160.0,78163.0,192120.0] || -> . % 76.30/76.41 217069[113:Spt:217068.0,216423.0,216424.0] || until2p7(s20)*+ -> . % 76.30/76.41 217070[113:Spt:217068.0,216423.1] || -> node4(s19)*. % 76.30/76.41 217072[113:MRR:861.0,217070.0] || m_main_v_state(s19,c_ready)*+ -> m_main_v_state(s20,c_busy). % 76.30/76.41 217075[113:Res:53.1,217072.0] || -> m_main_v_state(s19,c_busy)* m_main_v_state(s20,c_busy). % 76.30/76.41 217077[114:Spt:217075.0] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 217079[114:Res:217077.0,61.1] always3(s19) || -> . % 76.30/76.41 217080[114:SSi:217079.0,78151.0,78154.0,192118.0,216422.0,217070.0] || -> . % 76.30/76.41 217081[114:Spt:217080.0,217075.0,217077.0] || m_main_v_state(s19,c_busy)* -> . % 76.30/76.41 217082[114:Spt:217080.0,217075.1] || -> m_main_v_state(s20,c_busy)*. % 76.30/76.41 217086[114:Res:217082.0,61.1] always3(s20) || -> . % 76.30/76.41 217087[114:SSi:217086.0,78155.0,78159.0,192119.0] || -> . % 76.30/76.41 217088[112:Spt:217087.0,216421.0,216422.0] || until2p7(s19)*+ -> . % 76.30/76.41 217089[112:Spt:217087.0,216421.1] || -> node4(s18)*. % 76.30/76.41 217091[112:MRR:864.0,217089.0] || m_main_v_state(s18,c_ready)*+ -> m_main_v_state(s19,c_busy). % 76.30/76.41 217094[112:Res:53.1,217091.0] || -> m_main_v_state(s18,c_busy)* m_main_v_state(s19,c_busy). % 76.30/76.41 217099[113:Spt:217094.0] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 217101[113:Res:217099.0,61.1] always3(s18) || -> . % 76.30/76.41 217102[113:SSi:217101.0,78146.0,78150.0,192117.0,216420.0,217089.0] || -> . % 76.30/76.41 217103[113:Spt:217102.0,217094.0,217099.0] || m_main_v_state(s18,c_busy)* -> . % 76.30/76.41 217104[113:Spt:217102.0,217094.1] || -> m_main_v_state(s19,c_busy)*. % 76.30/76.41 217108[113:Res:217104.0,61.1] always3(s19) || -> . % 76.30/76.41 217109[113:SSi:217108.0,78151.0,78154.0,192118.0] || -> . % 76.30/76.41 217110[111:Spt:217109.0,216419.0,216420.0] || until2p7(s18)*+ -> . % 76.30/76.41 217111[111:Spt:217109.0,216419.1] || -> node4(s17)*. % 76.30/76.41 217113[111:MRR:867.0,217111.0] || m_main_v_state(s17,c_ready)*+ -> m_main_v_state(s18,c_busy). % 76.30/76.41 217116[111:Res:53.1,217113.0] || -> m_main_v_state(s17,c_busy)* m_main_v_state(s18,c_busy). % 76.30/76.41 217118[112:Spt:217116.0] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 217120[112:Res:217118.0,61.1] always3(s17) || -> . % 76.30/76.41 217121[112:SSi:217120.0,78142.0,78145.0,192116.0,216418.0,217111.0] || -> . % 76.30/76.41 217122[112:Spt:217121.0,217116.0,217118.0] || m_main_v_state(s17,c_busy)* -> . % 76.30/76.41 217123[112:Spt:217121.0,217116.1] || -> m_main_v_state(s18,c_busy)*. % 76.30/76.41 217127[112:Res:217123.0,61.1] always3(s18) || -> . % 76.30/76.41 217128[112:SSi:217127.0,78146.0,78150.0,192117.0] || -> . % 76.30/76.41 217129[110:Spt:217128.0,216417.0,216418.0] || until2p7(s17)*+ -> . % 76.30/76.41 217130[110:Spt:217128.0,216417.1] || -> node4(s16)*. % 76.30/76.41 217132[110:MRR:870.0,217130.0] || m_main_v_state(s16,c_ready)*+ -> m_main_v_state(s17,c_busy). % 76.30/76.41 217135[110:Res:53.1,217132.0] || -> m_main_v_state(s16,c_busy)* m_main_v_state(s17,c_busy). % 76.30/76.41 217137[111:Spt:217135.0] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 217139[111:Res:217137.0,61.1] always3(s16) || -> . % 76.30/76.41 217140[111:SSi:217139.0,78137.0,78141.0,192115.0,216416.0,217130.0] || -> . % 76.30/76.41 217141[111:Spt:217140.0,217135.0,217137.0] || m_main_v_state(s16,c_busy)* -> . % 76.30/76.41 217142[111:Spt:217140.0,217135.1] || -> m_main_v_state(s17,c_busy)*. % 76.30/76.41 217146[111:Res:217142.0,61.1] always3(s17) || -> . % 76.30/76.41 217147[111:SSi:217146.0,78142.0,78145.0,192116.0] || -> . % 76.30/76.41 217148[109:Spt:217147.0,216415.0,216416.0] || until2p7(s16)*+ -> . % 76.30/76.41 217149[109:Spt:217147.0,216415.1] || -> node4(s15)*. % 76.30/76.41 217151[109:MRR:873.0,217149.0] || m_main_v_state(s15,c_ready)*+ -> m_main_v_state(s16,c_busy). % 76.30/76.41 217154[109:Res:53.1,217151.0] || -> m_main_v_state(s15,c_busy)* m_main_v_state(s16,c_busy). % 76.30/76.41 217156[110:Spt:217154.0] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 217158[110:Res:217156.0,61.1] always3(s15) || -> . % 76.30/76.41 217159[110:SSi:217158.0,78133.0,78136.0,192114.0,216414.0,217149.0] || -> . % 76.30/76.41 217160[110:Spt:217159.0,217154.0,217156.0] || m_main_v_state(s15,c_busy)* -> . % 76.30/76.41 217161[110:Spt:217159.0,217154.1] || -> m_main_v_state(s16,c_busy)*. % 76.30/76.41 217165[110:Res:217161.0,61.1] always3(s16) || -> . % 76.30/76.41 217166[110:SSi:217165.0,78137.0,78141.0,192115.0] || -> . % 76.30/76.41 217167[108:Spt:217166.0,216413.0,216414.0] || until2p7(s15)*+ -> . % 76.30/76.41 217168[108:Spt:217166.0,216413.1] || -> node4(s14)*. % 76.30/76.41 217170[108:MRR:876.0,217168.0] || m_main_v_state(s14,c_ready)*+ -> m_main_v_state(s15,c_busy). % 76.30/76.41 217173[108:Res:53.1,217170.0] || -> m_main_v_state(s14,c_busy)* m_main_v_state(s15,c_busy). % 76.30/76.41 217178[109:Spt:217173.0] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 217180[109:Res:217178.0,61.1] always3(s14) || -> . % 76.30/76.41 217181[109:SSi:217180.0,78128.0,78132.0,192113.0,216412.0,217168.0] || -> . % 76.30/76.41 217182[109:Spt:217181.0,217173.0,217178.0] || m_main_v_state(s14,c_busy)* -> . % 76.30/76.41 217183[109:Spt:217181.0,217173.1] || -> m_main_v_state(s15,c_busy)*. % 76.30/76.41 217187[109:Res:217183.0,61.1] always3(s15) || -> . % 76.30/76.41 217188[109:SSi:217187.0,78133.0,78136.0,192114.0] || -> . % 76.30/76.41 217189[107:Spt:217188.0,216411.0,216412.0] || until2p7(s14)*+ -> . % 76.30/76.41 217190[107:Spt:217188.0,216411.1] || -> node4(s13)*. % 76.30/76.41 217192[107:MRR:879.0,217190.0] || m_main_v_state(s13,c_ready)*+ -> m_main_v_state(s14,c_busy). % 76.30/76.41 217195[107:Res:53.1,217192.0] || -> m_main_v_state(s13,c_busy)* m_main_v_state(s14,c_busy). % 76.30/76.41 217197[108:Spt:217195.0] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 217199[108:Res:217197.0,61.1] always3(s13) || -> . % 76.30/76.41 217200[108:SSi:217199.0,78124.0,78127.0,192112.0,216410.0,217190.0] || -> . % 76.30/76.41 217201[108:Spt:217200.0,217195.0,217197.0] || m_main_v_state(s13,c_busy)* -> . % 76.30/76.41 217202[108:Spt:217200.0,217195.1] || -> m_main_v_state(s14,c_busy)*. % 76.30/76.41 217206[108:Res:217202.0,61.1] always3(s14) || -> . % 76.30/76.41 217207[108:SSi:217206.0,78128.0,78132.0,192113.0] || -> . % 76.30/76.41 217208[106:Spt:217207.0,216409.0,216410.0] || until2p7(s13)*+ -> . % 76.30/76.41 217209[106:Spt:217207.0,216409.1] || -> node4(s12)*. % 76.30/76.41 217211[106:MRR:882.0,217209.0] || m_main_v_state(s12,c_ready)*+ -> m_main_v_state(s13,c_busy). % 76.30/76.41 217214[106:Res:53.1,217211.0] || -> m_main_v_state(s12,c_busy)* m_main_v_state(s13,c_busy). % 76.30/76.41 217216[107:Spt:217214.0] || -> m_main_v_state(s12,c_busy)*. % 76.30/76.41 217218[107:Res:217216.0,61.1] always3(s12) || -> . % 76.30/76.41 217219[107:SSi:217218.0,78119.0,78123.0,192111.0,216408.0,217209.0] || -> . % 76.30/76.41 217220[107:Spt:217219.0,217214.0,217216.0] || m_main_v_state(s12,c_busy)* -> . % 76.30/76.41 217221[107:Spt:217219.0,217214.1] || -> m_main_v_state(s13,c_busy)*. % 76.30/76.41 217225[107:Res:217221.0,61.1] always3(s13) || -> . % 76.30/76.41 217226[107:SSi:217225.0,78124.0,78127.0,192112.0] || -> . % 76.30/76.41 217227[105:Spt:217226.0,216407.0,216408.0] || until2p7(s12)*+ -> . % 76.30/76.41 217228[105:Spt:217226.0,216407.1] || -> node4(s11)*. % 76.30/76.41 217230[105:MRR:885.0,217228.0] || m_main_v_state(s11,c_ready)*+ -> m_main_v_state(s12,c_busy). % 76.30/76.41 217233[105:Res:53.1,217230.0] || -> m_main_v_state(s11,c_busy)* m_main_v_state(s12,c_busy). % 76.30/76.41 217235[106:Spt:217233.0] || -> m_main_v_state(s11,c_busy)*. % 76.30/76.41 217237[106:Res:217235.0,61.1] always3(s11) || -> . % 76.30/76.41 217238[106:SSi:217237.0,78115.0,78118.0,192110.0,216406.0,217228.0] || -> . % 76.30/76.41 217239[106:Spt:217238.0,217233.0,217235.0] || m_main_v_state(s11,c_busy)* -> . % 76.30/76.41 217240[106:Spt:217238.0,217233.1] || -> m_main_v_state(s12,c_busy)*. % 76.30/76.41 217244[106:Res:217240.0,61.1] always3(s12) || -> . % 76.30/76.41 217245[106:SSi:217244.0,78119.0,78123.0,192111.0] || -> . % 76.30/76.41 217246[104:Spt:217245.0,216405.0,216406.0] || until2p7(s11)*+ -> . % 76.30/76.41 217247[104:Spt:217245.0,216405.1] || -> node4(s10)*. % 76.30/76.41 217249[104:MRR:888.0,217247.0] || m_main_v_state(s10,c_ready)*+ -> m_main_v_state(s11,c_busy). % 76.30/76.41 217252[104:Res:53.1,217249.0] || -> m_main_v_state(s10,c_busy)* m_main_v_state(s11,c_busy). % 76.30/76.41 217257[105:Spt:217252.0] || -> m_main_v_state(s10,c_busy)*. % 76.30/76.41 217259[105:Res:217257.0,61.1] always3(s10) || -> . % 76.30/76.41 217260[105:SSi:217259.0,78110.0,78114.0,192109.0,216404.0,217247.0] || -> . % 76.30/76.41 217261[105:Spt:217260.0,217252.0,217257.0] || m_main_v_state(s10,c_busy)* -> . % 76.30/76.41 217262[105:Spt:217260.0,217252.1] || -> m_main_v_state(s11,c_busy)*. % 76.30/76.41 217266[105:Res:217262.0,61.1] always3(s11) || -> . % 76.30/76.41 217267[105:SSi:217266.0,78115.0,78118.0,192110.0] || -> . % 76.30/76.41 217268[103:Spt:217267.0,216403.0,216404.0] || until2p7(s10)*+ -> . % 76.30/76.41 217269[103:Spt:217267.0,216403.1] || -> node4(s9)*. % 76.30/76.41 217271[103:MRR:891.0,217269.0] || m_main_v_state(s9,c_ready)*+ -> m_main_v_state(s10,c_busy). % 76.30/76.41 217274[103:Res:53.1,217271.0] || -> m_main_v_state(s9,c_busy)* m_main_v_state(s10,c_busy). % 76.30/76.41 217276[104:Spt:217274.0] || -> m_main_v_state(s9,c_busy)*. % 76.30/76.41 217278[104:Res:217276.0,61.1] always3(s9) || -> . % 76.30/76.41 217279[104:SSi:217278.0,78106.0,78109.0,192108.0,216402.0,217269.0] || -> . % 76.30/76.41 217280[104:Spt:217279.0,217274.0,217276.0] || m_main_v_state(s9,c_busy)* -> . % 76.30/76.41 217281[104:Spt:217279.0,217274.1] || -> m_main_v_state(s10,c_busy)*. % 76.30/76.41 217285[104:Res:217281.0,61.1] always3(s10) || -> . % 76.30/76.41 217286[104:SSi:217285.0,78110.0,78114.0,192109.0] || -> . % 76.30/76.41 217287[102:Spt:217286.0,216401.0,216402.0] || until2p7(s9)*+ -> . % 76.30/76.41 217288[102:Spt:217286.0,216401.1] || -> node4(s8)*. % 76.30/76.41 217290[102:MRR:894.0,217288.0] || m_main_v_state(s8,c_ready)*+ -> m_main_v_state(s9,c_busy). % 76.30/76.41 217293[102:Res:53.1,217290.0] || -> m_main_v_state(s8,c_busy)* m_main_v_state(s9,c_busy). % 76.30/76.41 217295[103:Spt:217293.0] || -> m_main_v_state(s8,c_busy)*. % 76.30/76.41 217297[103:Res:217295.0,61.1] always3(s8) || -> . % 76.30/76.41 217298[103:SSi:217297.0,78101.0,78105.0,192107.0,216400.0,217288.0] || -> . % 76.30/76.41 217299[103:Spt:217298.0,217293.0,217295.0] || m_main_v_state(s8,c_busy)* -> . % 76.30/76.41 217300[103:Spt:217298.0,217293.1] || -> m_main_v_state(s9,c_busy)*. % 76.30/76.41 217304[103:Res:217300.0,61.1] always3(s9) || -> . % 76.30/76.41 217305[103:SSi:217304.0,78106.0,78109.0,192108.0] || -> . % 76.30/76.41 217306[101:Spt:217305.0,216399.0,216400.0] || until2p7(s8)*+ -> . % 76.30/76.41 217307[101:Spt:217305.0,216399.1] || -> node4(s7)*. % 76.30/76.41 217309[101:MRR:897.0,217307.0] || m_main_v_state(s7,c_ready)*+ -> m_main_v_state(s8,c_busy). % 76.30/76.41 217312[101:Res:53.1,217309.0] || -> m_main_v_state(s7,c_busy)* m_main_v_state(s8,c_busy). % 76.30/76.41 217314[102:Spt:217312.0] || -> m_main_v_state(s7,c_busy)*. % 76.30/76.41 217316[102:Res:217314.0,61.1] always3(s7) || -> . % 76.30/76.41 217317[102:SSi:217316.0,78097.0,78100.0,192106.0,216398.0,217307.0] || -> . % 76.30/76.41 217318[102:Spt:217317.0,217312.0,217314.0] || m_main_v_state(s7,c_busy)* -> . % 76.30/76.41 217319[102:Spt:217317.0,217312.1] || -> m_main_v_state(s8,c_busy)*. % 76.30/76.41 217323[102:Res:217319.0,61.1] always3(s8) || -> . % 76.30/76.41 217324[102:SSi:217323.0,78101.0,78105.0,192107.0] || -> . % 76.30/76.41 217325[100:Spt:217324.0,216397.0,216398.0] || until2p7(s7)*+ -> . % 76.30/76.41 217326[100:Spt:217324.0,216397.1] || -> node4(s6)*. % 76.30/76.41 217328[100:MRR:900.0,217326.0] || m_main_v_state(s6,c_ready)*+ -> m_main_v_state(s7,c_busy). % 76.30/76.41 217331[100:Res:53.1,217328.0] || -> m_main_v_state(s6,c_busy)* m_main_v_state(s7,c_busy). % 76.30/76.41 217333[100:MRR:217331.0,216388.0] || -> m_main_v_state(s7,c_busy)*. % 76.30/76.41 217338[100:Res:217333.0,61.1] always3(s7) || -> . % 76.30/76.41 217339[100:SSi:217338.0,78097.0,78100.0,192106.0] || -> . % 76.30/76.41 217340[55:Spt:217339.0,191868.43,192105.0] || always3(s6)*+ -> . % 76.30/76.41 217341[55:Spt:217339.0,191868.0,191868.1,191868.2,191868.3,191868.4,191868.5,191868.6,191868.7,191868.8,191868.9,191868.10,191868.11,191868.12,191868.13,191868.14,191868.15,191868.16,191868.17,191868.18,191868.19,191868.20,191868.21,191868.22,191868.23,191868.24,191868.25,191868.26,191868.27,191868.28,191868.29,191868.30,191868.31,191868.32,191868.33,191868.34,191868.35,191868.36,191868.37,191868.38,191868.39,191868.40,191868.41,191868.42] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) trans(s49,s7)*. % 76.30/76.41 217343[55:Res:217341.42,69.2] xuntil6(s49) last(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.41 217344[55:Res:217341.42,62.1] always3(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* always3(s7). % 76.30/76.41 217345[55:Res:217341.42,60.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.41 217346[55:SSi:217344.0,50.0,78285.0,78388.0] || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* always3(s7). % 76.30/76.41 217347[55:SSi:217343.1,50.0,78285.0,78388.0] xuntil6(s49) || -> trans(s49,s49) trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.41 217577[56:Spt:217346.42] || -> always3(s7)*. % 76.30/76.41 217578[56:MRR:513.0,217577.0] || -> always3(s8)*. % 76.30/76.41 217579[56:MRR:510.0,217578.0] || -> always3(s9)*. % 76.30/76.41 217580[56:MRR:507.0,217579.0] || -> always3(s10)*. % 76.30/76.41 217581[56:MRR:504.0,217580.0] || -> always3(s11)*. % 76.30/76.41 217582[56:MRR:501.0,217581.0] || -> always3(s12)*. % 76.30/76.41 217583[56:MRR:498.0,217582.0] || -> always3(s13)*. % 76.30/76.41 217584[56:MRR:495.0,217583.0] || -> always3(s14)*. % 76.30/76.41 217585[56:MRR:492.0,217584.0] || -> always3(s15)*. % 76.30/76.41 217586[56:MRR:489.0,217585.0] || -> always3(s16)*. % 76.30/76.41 217587[56:MRR:486.0,217586.0] || -> always3(s17)*. % 76.30/76.41 217588[56:MRR:483.0,217587.0] || -> always3(s18)*. % 76.30/76.41 217589[56:MRR:480.0,217588.0] || -> always3(s19)*. % 76.30/76.41 217590[56:MRR:477.0,217589.0] || -> always3(s20)*. % 76.30/76.41 217591[56:MRR:474.0,217590.0] || -> always3(s21)*. % 76.30/76.41 217592[56:MRR:471.0,217591.0] || -> always3(s22)*. % 76.30/76.41 217593[56:MRR:468.0,217592.0] || -> always3(s23)*. % 76.30/76.41 217594[56:MRR:465.0,217593.0] || -> always3(s24)*. % 76.30/76.41 217595[56:MRR:462.0,217594.0] || -> always3(s25)*. % 76.30/76.41 217596[56:MRR:459.0,217595.0] || -> always3(s26)*. % 76.30/76.41 217597[56:MRR:456.0,217596.0] || -> always3(s27)*. % 76.30/76.41 217598[56:MRR:453.0,217597.0] || -> always3(s28)*. % 76.30/76.41 217599[56:MRR:450.0,217598.0] || -> always3(s29)*. % 76.30/76.41 217600[56:MRR:427.0,217599.0] || -> always3(s30)*. % 76.30/76.41 217601[56:MRR:425.0,217600.0] || -> always3(s31)*. % 76.30/76.41 217602[56:MRR:423.0,217601.0] || -> always3(s32)*. % 76.30/76.41 217603[56:MRR:421.0,217602.0] || -> always3(s33)*. % 76.30/76.41 217604[56:MRR:370.0,217603.0] || -> always3(s34)*. % 76.30/76.41 217605[56:MRR:368.0,217604.0] || -> always3(s35)*. % 76.30/76.41 217606[56:MRR:366.0,217605.0] || -> always3(s36)*. % 76.30/76.41 217607[56:MRR:364.0,217606.0] || -> always3(s37)*. % 76.30/76.41 217608[56:MRR:313.0,217607.0] || -> always3(s38)*. % 76.30/76.41 217609[56:MRR:311.0,217608.0] || -> always3(s39)*. % 76.30/76.41 217610[56:MRR:309.0,217609.0] || -> always3(s40)*. % 76.30/76.41 217611[56:MRR:307.0,217610.0] || -> always3(s41)*. % 76.30/76.41 217612[56:MRR:306.0,217611.0] || -> always3(s42)*. % 76.30/76.41 217613[56:MRR:305.0,217612.0] || -> always3(s43)*. % 76.30/76.41 217614[56:MRR:304.0,217613.0] || -> always3(s44)*. % 76.30/76.41 217615[56:MRR:303.0,217614.0] || -> always3(s45)*. % 76.30/76.41 217616[56:MRR:302.0,217615.0] || -> always3(s46)*. % 76.30/76.41 217617[56:MRR:301.0,217616.0] || -> always3(s47)*. % 76.30/76.41 217618[56:MRR:300.0,217617.0] || -> always3(s48)*. % 76.30/76.41 217619[57:Spt:217345.0] || -> trans(s49,s49)*. % 76.30/76.41 217620[57:Res:217619.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s49)*. % 76.30/76.41 217622[57:Res:217619.0,60.0] || -> node2(s49,s49)*. % 76.30/76.41 217623[57:SSi:217620.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s49)*. % 76.30/76.41 217624[57:Res:217622.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready)* -> m_main_v_state(s49,c_busy). % 76.30/76.41 217625[57:MRR:217624.1,217624.2,53.1,78381.0] m_main_v_request(s49) || -> . % 76.30/76.41 217627[57:SoR:217625.0,64.1] node4(s49) || -> . % 76.30/76.41 217628[57:MRR:194.1,217627.0] until2p7(s49) || -> . % 76.30/76.41 217631[57:MRR:217623.1,217628.0] xuntil6(s49) || -> . % 76.30/76.41 217632[57:SoR:217627.0,66.2] until5(s49) || -> xuntil6(s49)*. % 76.30/76.41 217633[57:SSi:217632.0,50.0,78285.0,78388.0] || -> xuntil6(s49)*. % 76.30/76.41 217634[57:MRR:217633.0,217631.0] || -> . % 76.30/76.41 217635[57:Spt:217634.0,217345.0,217619.0] || trans(s49,s49)*+ -> . % 76.30/76.41 217636[57:Spt:217634.0,217345.1,217345.2,217345.3,217345.4,217345.5,217345.6,217345.7,217345.8,217345.9,217345.10,217345.11,217345.12,217345.13,217345.14,217345.15,217345.16,217345.17,217345.18,217345.19,217345.20,217345.21,217345.22,217345.23,217345.24,217345.25,217345.26,217345.27,217345.28,217345.29,217345.30,217345.31,217345.32,217345.33,217345.34,217345.35,217345.36,217345.37,217345.38,217345.39,217345.40,217345.41,217345.42] || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.41 217638[57:MRR:217347.1,217635.0] xuntil6(s49) || -> trans(s49,s48) trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.41 217639[58:Spt:217636.0] || -> trans(s49,s48)*. % 76.30/76.41 217640[58:Res:217639.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s48)*. % 76.30/76.41 217642[58:Res:217639.0,60.0] || -> node2(s49,s48)*. % 76.30/76.41 217643[58:SSi:217640.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s48)*. % 76.30/76.41 217644[58:Res:217642.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 217647[58:SoR:217644.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 217649[58:SoR:217647.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s48,c_busy)* xuntil6(s49). % 76.30/76.41 217650[58:SSi:217649.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s48,c_busy)* xuntil6(s49). % 76.30/76.41 217651[59:Spt:217650.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 217653[59:Res:217651.0,61.1] always3(s48) || -> . % 76.30/76.41 217654[59:SSi:217653.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.41 217655[59:Spt:217654.0,217650.1,217651.0] || m_main_v_state(s48,c_busy)*+ -> . % 76.30/76.41 217656[59:Spt:217654.0,217650.0,217650.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 217660[59:MRR:217647.2,217655.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 217661[59:Res:53.1,217656.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 217663[59:MRR:217661.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 217664[59:MRR:217643.0,217663.0] || -> until2p7(s48)*. % 76.30/76.41 217665[59:MRR:559.0,217664.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 217666[60:Spt:217665.0] || -> until2p7(s49)*. % 76.30/76.41 217667[60:MRR:194.0,217666.0] || -> node4(s49)*. % 76.30/76.41 217668[60:MRR:217660.0,217667.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 217669[60:Res:53.1,217668.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 217671[60:MRR:217669.0,78381.0] || -> . % 76.30/76.41 217672[60:Spt:217671.0,217665.0,217666.0] || until2p7(s49)*+ -> . % 76.30/76.41 217673[60:Spt:217671.0,217665.1] || -> node4(s48)*. % 76.30/76.41 217674[60:MRR:78384.0,217673.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 217677[60:Res:53.1,217674.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 217679[60:MRR:217677.0,217655.0] || -> . % 76.30/76.41 217680[58:Spt:217679.0,217636.0,217639.0] || trans(s49,s48)*+ -> . % 76.30/76.41 217681[58:Spt:217679.0,217636.1,217636.2,217636.3,217636.4,217636.5,217636.6,217636.7,217636.8,217636.9,217636.10,217636.11,217636.12,217636.13,217636.14,217636.15,217636.16,217636.17,217636.18,217636.19,217636.20,217636.21,217636.22,217636.23,217636.24,217636.25,217636.26,217636.27,217636.28,217636.29,217636.30,217636.31,217636.32,217636.33,217636.34,217636.35,217636.36,217636.37,217636.38,217636.39,217636.40,217636.41] || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.41 217683[58:MRR:217638.1,217680.0] xuntil6(s49) || -> trans(s49,s47) trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.41 217684[59:Spt:217681.0] || -> trans(s49,s47)*. % 76.30/76.41 217685[59:Res:217684.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s47)*. % 76.30/76.41 217687[59:Res:217684.0,60.0] || -> node2(s49,s47)*. % 76.30/76.41 217688[59:SSi:217685.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s47)*. % 76.30/76.41 217689[59:Res:217687.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 217701[59:SoR:217689.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 217703[59:SoR:217701.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 76.30/76.41 217704[59:SSi:217703.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s47,c_busy)* xuntil6(s49). % 76.30/76.41 217705[60:Spt:217704.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 217707[60:Res:217705.0,61.1] always3(s47) || -> . % 76.30/76.41 217708[60:SSi:217707.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.41 217709[60:Spt:217708.0,217704.1,217705.0] || m_main_v_state(s47,c_busy)*+ -> . % 76.30/76.41 217710[60:Spt:217708.0,217704.0,217704.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 217714[60:MRR:217701.2,217709.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 217715[60:Res:53.1,217710.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 217717[60:MRR:217715.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 217718[60:MRR:217688.0,217717.0] || -> until2p7(s47)*. % 76.30/76.41 217719[60:MRR:554.0,217718.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 217720[61:Spt:217719.0] || -> until2p7(s48)*. % 76.30/76.41 217721[61:MRR:559.0,217720.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 217722[62:Spt:217721.0] || -> until2p7(s49)*. % 76.30/76.41 217723[62:MRR:194.0,217722.0] || -> node4(s49)*. % 76.30/76.41 217724[62:MRR:217714.0,217723.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 217725[62:Res:53.1,217724.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 217727[62:MRR:217725.0,78381.0] || -> . % 76.30/76.41 217728[62:Spt:217727.0,217721.0,217722.0] || until2p7(s49)*+ -> . % 76.30/76.41 217729[62:Spt:217727.0,217721.1] || -> node4(s48)*. % 76.30/76.41 217730[62:MRR:78384.0,217729.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 217733[62:Res:53.1,217730.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 217736[62:Res:217733.0,61.1] always3(s48) || -> . % 76.30/76.41 217737[62:SSi:217736.0,78281.0,78387.0,217618.0,217720.0,217729.0] || -> . % 76.30/76.41 217738[61:Spt:217737.0,217719.0,217720.0] || until2p7(s48)*+ -> . % 76.30/76.41 217739[61:Spt:217737.0,217719.1] || -> node4(s47)*. % 76.30/76.41 217741[61:MRR:777.0,217739.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 217756[61:Res:53.1,217741.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 217758[61:MRR:217756.0,217709.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 217760[61:Res:217758.0,61.1] always3(s48) || -> . % 76.30/76.41 217761[61:SSi:217760.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.41 217762[59:Spt:217761.0,217681.0,217684.0] || trans(s49,s47)*+ -> . % 76.30/76.41 217763[59:Spt:217761.0,217681.1,217681.2,217681.3,217681.4,217681.5,217681.6,217681.7,217681.8,217681.9,217681.10,217681.11,217681.12,217681.13,217681.14,217681.15,217681.16,217681.17,217681.18,217681.19,217681.20,217681.21,217681.22,217681.23,217681.24,217681.25,217681.26,217681.27,217681.28,217681.29,217681.30,217681.31,217681.32,217681.33,217681.34,217681.35,217681.36,217681.37,217681.38,217681.39,217681.40] || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.41 217765[59:MRR:217683.1,217762.0] xuntil6(s49) || -> trans(s49,s46) trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.41 217766[60:Spt:217763.0] || -> trans(s49,s46)*. % 76.30/76.41 217767[60:Res:217766.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s46)*. % 76.30/76.41 217769[60:Res:217766.0,60.0] || -> node2(s49,s46)*. % 76.30/76.41 217770[60:SSi:217767.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s46)*. % 76.30/76.41 217771[60:Res:217769.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 217787[60:SoR:217771.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 217789[60:SoR:217787.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s46,c_busy)* xuntil6(s49). % 76.30/76.41 217790[60:SSi:217789.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s46,c_busy)* xuntil6(s49). % 76.30/76.41 217791[61:Spt:217790.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 217793[61:Res:217791.0,61.1] always3(s46) || -> . % 76.30/76.41 217794[61:SSi:217793.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.41 217795[61:Spt:217794.0,217790.1,217791.0] || m_main_v_state(s46,c_busy)*+ -> . % 76.30/76.41 217796[61:Spt:217794.0,217790.0,217790.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 217800[61:MRR:217787.2,217795.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 217801[61:Res:53.1,217796.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 217803[61:MRR:217801.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 217804[61:MRR:217770.0,217803.0] || -> until2p7(s46)*. % 76.30/76.41 217805[61:MRR:549.0,217804.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 217806[62:Spt:217805.0] || -> until2p7(s47)*. % 76.30/76.41 217807[62:MRR:554.0,217806.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 217808[63:Spt:217807.0] || -> until2p7(s48)*. % 76.30/76.41 217809[63:MRR:559.0,217808.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 217810[64:Spt:217809.0] || -> until2p7(s49)*. % 76.30/76.41 217811[64:MRR:194.0,217810.0] || -> node4(s49)*. % 76.30/76.41 217812[64:MRR:217800.0,217811.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 217813[64:Res:53.1,217812.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 217815[64:MRR:217813.0,78381.0] || -> . % 76.30/76.41 217816[64:Spt:217815.0,217809.0,217810.0] || until2p7(s49)*+ -> . % 76.30/76.41 217817[64:Spt:217815.0,217809.1] || -> node4(s48)*. % 76.30/76.41 217818[64:MRR:78384.0,217817.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 217821[64:Res:53.1,217818.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 217824[64:Res:217821.0,61.1] always3(s48) || -> . % 76.30/76.41 217825[64:SSi:217824.0,78281.0,78387.0,217618.0,217808.0,217817.0] || -> . % 76.30/76.41 217826[63:Spt:217825.0,217807.0,217808.0] || until2p7(s48)*+ -> . % 76.30/76.41 217827[63:Spt:217825.0,217807.1] || -> node4(s47)*. % 76.30/76.41 217829[63:MRR:777.0,217827.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 217844[63:Res:53.1,217829.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 217849[64:Spt:217844.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 217851[64:Res:217849.0,61.1] always3(s47) || -> . % 76.30/76.41 217852[64:SSi:217851.0,78277.0,78280.0,217617.0,217806.0,217827.0] || -> . % 76.30/76.41 217853[64:Spt:217852.0,217844.0,217849.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 217854[64:Spt:217852.0,217844.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 217858[64:Res:217854.0,61.1] always3(s48) || -> . % 76.30/76.41 217859[64:SSi:217858.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.41 217860[62:Spt:217859.0,217805.0,217806.0] || until2p7(s47)*+ -> . % 76.30/76.41 217861[62:Spt:217859.0,217805.1] || -> node4(s46)*. % 76.30/76.41 217863[62:MRR:780.0,217861.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 217870[62:Res:53.1,217863.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 217872[62:MRR:217870.0,217795.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 217874[62:Res:217872.0,61.1] always3(s47) || -> . % 76.30/76.41 217875[62:SSi:217874.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.41 217876[60:Spt:217875.0,217763.0,217766.0] || trans(s49,s46)*+ -> . % 76.30/76.41 217877[60:Spt:217875.0,217763.1,217763.2,217763.3,217763.4,217763.5,217763.6,217763.7,217763.8,217763.9,217763.10,217763.11,217763.12,217763.13,217763.14,217763.15,217763.16,217763.17,217763.18,217763.19,217763.20,217763.21,217763.22,217763.23,217763.24,217763.25,217763.26,217763.27,217763.28,217763.29,217763.30,217763.31,217763.32,217763.33,217763.34,217763.35,217763.36,217763.37,217763.38,217763.39] || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.41 217879[60:MRR:217765.1,217876.0] xuntil6(s49) || -> trans(s49,s45) trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.41 217880[61:Spt:217877.0] || -> trans(s49,s45)*. % 76.30/76.41 217881[61:Res:217880.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s45)*. % 76.30/76.41 217883[61:Res:217880.0,60.0] || -> node2(s49,s45)*. % 76.30/76.41 217884[61:SSi:217881.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s45)*. % 76.30/76.41 217885[61:Res:217883.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 217901[61:SoR:217885.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 217903[61:SoR:217901.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s45,c_busy)* xuntil6(s49). % 76.30/76.41 217904[61:SSi:217903.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s45,c_busy)* xuntil6(s49). % 76.30/76.41 217905[62:Spt:217904.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 217907[62:Res:217905.0,61.1] always3(s45) || -> . % 76.30/76.41 217908[62:SSi:217907.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.41 217909[62:Spt:217908.0,217904.1,217905.0] || m_main_v_state(s45,c_busy)*+ -> . % 76.30/76.41 217910[62:Spt:217908.0,217904.0,217904.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 217914[62:MRR:217901.2,217909.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 217915[62:Res:53.1,217910.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 217917[62:MRR:217915.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 217918[62:MRR:217884.0,217917.0] || -> until2p7(s45)*. % 76.30/76.41 217919[62:MRR:544.0,217918.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 217920[63:Spt:217919.0] || -> until2p7(s46)*. % 76.30/76.41 217921[63:MRR:549.0,217920.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 217922[64:Spt:217921.0] || -> until2p7(s47)*. % 76.30/76.41 217923[64:MRR:554.0,217922.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 217924[65:Spt:217923.0] || -> until2p7(s48)*. % 76.30/76.41 217925[65:MRR:559.0,217924.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 217926[66:Spt:217925.0] || -> until2p7(s49)*. % 76.30/76.41 217927[66:MRR:194.0,217926.0] || -> node4(s49)*. % 76.30/76.41 217928[66:MRR:217914.0,217927.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 217929[66:Res:53.1,217928.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 217931[66:MRR:217929.0,78381.0] || -> . % 76.30/76.41 217932[66:Spt:217931.0,217925.0,217926.0] || until2p7(s49)*+ -> . % 76.30/76.41 217933[66:Spt:217931.0,217925.1] || -> node4(s48)*. % 76.30/76.41 217934[66:MRR:78384.0,217933.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 217937[66:Res:53.1,217934.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 217940[66:Res:217937.0,61.1] always3(s48) || -> . % 76.30/76.41 217941[66:SSi:217940.0,78281.0,78387.0,217618.0,217924.0,217933.0] || -> . % 76.30/76.41 217942[65:Spt:217941.0,217923.0,217924.0] || until2p7(s48)*+ -> . % 76.30/76.41 217943[65:Spt:217941.0,217923.1] || -> node4(s47)*. % 76.30/76.41 217945[65:MRR:777.0,217943.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 217963[65:Res:53.1,217945.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 217965[66:Spt:217963.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 217967[66:Res:217965.0,61.1] always3(s47) || -> . % 76.30/76.41 217968[66:SSi:217967.0,78277.0,78280.0,217617.0,217922.0,217943.0] || -> . % 76.30/76.41 217969[66:Spt:217968.0,217963.0,217965.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 217970[66:Spt:217968.0,217963.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 217974[66:Res:217970.0,61.1] always3(s48) || -> . % 76.30/76.41 217975[66:SSi:217974.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.41 217976[64:Spt:217975.0,217921.0,217922.0] || until2p7(s47)*+ -> . % 76.30/76.41 217977[64:Spt:217975.0,217921.1] || -> node4(s46)*. % 76.30/76.41 217979[64:MRR:780.0,217977.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 217986[64:Res:53.1,217979.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 217991[65:Spt:217986.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 217993[65:Res:217991.0,61.1] always3(s46) || -> . % 76.30/76.41 217994[65:SSi:217993.0,78272.0,78276.0,217616.0,217920.0,217977.0] || -> . % 76.30/76.41 217995[65:Spt:217994.0,217986.0,217991.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 217996[65:Spt:217994.0,217986.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 218000[65:Res:217996.0,61.1] always3(s47) || -> . % 76.30/76.41 218001[65:SSi:218000.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.41 218002[63:Spt:218001.0,217919.0,217920.0] || until2p7(s46)*+ -> . % 76.30/76.41 218003[63:Spt:218001.0,217919.1] || -> node4(s45)*. % 76.30/76.41 218005[63:MRR:783.0,218003.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 218008[63:Res:53.1,218005.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 218010[63:MRR:218008.0,217909.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 218012[63:Res:218010.0,61.1] always3(s46) || -> . % 76.30/76.41 218013[63:SSi:218012.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.41 218014[61:Spt:218013.0,217877.0,217880.0] || trans(s49,s45)*+ -> . % 76.30/76.41 218015[61:Spt:218013.0,217877.1,217877.2,217877.3,217877.4,217877.5,217877.6,217877.7,217877.8,217877.9,217877.10,217877.11,217877.12,217877.13,217877.14,217877.15,217877.16,217877.17,217877.18,217877.19,217877.20,217877.21,217877.22,217877.23,217877.24,217877.25,217877.26,217877.27,217877.28,217877.29,217877.30,217877.31,217877.32,217877.33,217877.34,217877.35,217877.36,217877.37,217877.38] || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.41 218017[61:MRR:217879.1,218014.0] xuntil6(s49) || -> trans(s49,s44) trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.41 218018[62:Spt:218015.0] || -> trans(s49,s44)*. % 76.30/76.41 218019[62:Res:218018.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s44)*. % 76.30/76.41 218021[62:Res:218018.0,60.0] || -> node2(s49,s44)*. % 76.30/76.41 218022[62:SSi:218019.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s44)*. % 76.30/76.41 218023[62:Res:218021.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 218043[62:SoR:218023.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 218045[62:SoR:218043.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s44,c_busy)* xuntil6(s49). % 76.30/76.41 218046[62:SSi:218045.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s44,c_busy)* xuntil6(s49). % 76.30/76.41 218047[63:Spt:218046.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 218049[63:Res:218047.0,61.1] always3(s44) || -> . % 76.30/76.41 218050[63:SSi:218049.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.41 218051[63:Spt:218050.0,218046.1,218047.0] || m_main_v_state(s44,c_busy)*+ -> . % 76.30/76.41 218052[63:Spt:218050.0,218046.0,218046.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 218056[63:MRR:218043.2,218051.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 218057[63:Res:53.1,218052.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 218059[63:MRR:218057.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 218060[63:MRR:218022.0,218059.0] || -> until2p7(s44)*. % 76.30/76.41 218061[63:MRR:539.0,218060.0] || -> until2p7(s45)* node4(s44). % 76.30/76.41 218062[64:Spt:218061.0] || -> until2p7(s45)*. % 76.30/76.41 218063[64:MRR:544.0,218062.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 218064[65:Spt:218063.0] || -> until2p7(s46)*. % 76.30/76.41 218065[65:MRR:549.0,218064.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 218066[66:Spt:218065.0] || -> until2p7(s47)*. % 76.30/76.41 218067[66:MRR:554.0,218066.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 218068[67:Spt:218067.0] || -> until2p7(s48)*. % 76.30/76.41 218069[67:MRR:559.0,218068.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 218070[68:Spt:218069.0] || -> until2p7(s49)*. % 76.30/76.41 218071[68:MRR:194.0,218070.0] || -> node4(s49)*. % 76.30/76.41 218072[68:MRR:218056.0,218071.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 218076[68:Res:53.1,218072.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 218078[68:MRR:218076.0,78381.0] || -> . % 76.30/76.41 218079[68:Spt:218078.0,218069.0,218070.0] || until2p7(s49)*+ -> . % 76.30/76.41 218080[68:Spt:218078.0,218069.1] || -> node4(s48)*. % 76.30/76.41 218081[68:MRR:78384.0,218080.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 218084[68:Res:53.1,218081.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 218087[68:Res:218084.0,61.1] always3(s48) || -> . % 76.30/76.41 218088[68:SSi:218087.0,78281.0,78387.0,217618.0,218068.0,218080.0] || -> . % 76.30/76.41 218089[67:Spt:218088.0,218067.0,218068.0] || until2p7(s48)*+ -> . % 76.30/76.41 218090[67:Spt:218088.0,218067.1] || -> node4(s47)*. % 76.30/76.41 218092[67:MRR:777.0,218090.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 218104[67:Res:53.1,218092.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 218106[68:Spt:218104.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 218108[68:Res:218106.0,61.1] always3(s47) || -> . % 76.30/76.41 218109[68:SSi:218108.0,78277.0,78280.0,217617.0,218066.0,218090.0] || -> . % 76.30/76.41 218110[68:Spt:218109.0,218104.0,218106.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 218111[68:Spt:218109.0,218104.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 218115[68:Res:218111.0,61.1] always3(s48) || -> . % 76.30/76.41 218116[68:SSi:218115.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.41 218117[66:Spt:218116.0,218065.0,218066.0] || until2p7(s47)*+ -> . % 76.30/76.41 218118[66:Spt:218116.0,218065.1] || -> node4(s46)*. % 76.30/76.41 218120[66:MRR:780.0,218118.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 218127[66:Res:53.1,218120.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 218132[67:Spt:218127.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 218134[67:Res:218132.0,61.1] always3(s46) || -> . % 76.30/76.41 218135[67:SSi:218134.0,78272.0,78276.0,217616.0,218064.0,218118.0] || -> . % 76.30/76.41 218136[67:Spt:218135.0,218127.0,218132.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 218137[67:Spt:218135.0,218127.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 218141[67:Res:218137.0,61.1] always3(s47) || -> . % 76.30/76.41 218142[67:SSi:218141.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.41 218143[65:Spt:218142.0,218063.0,218064.0] || until2p7(s46)*+ -> . % 76.30/76.41 218144[65:Spt:218142.0,218063.1] || -> node4(s45)*. % 76.30/76.41 218146[65:MRR:783.0,218144.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 218149[65:Res:53.1,218146.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 218151[66:Spt:218149.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 218153[66:Res:218151.0,61.1] always3(s45) || -> . % 76.30/76.41 218154[66:SSi:218153.0,78268.0,78271.0,217615.0,218062.0,218144.0] || -> . % 76.30/76.41 218155[66:Spt:218154.0,218149.0,218151.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.41 218156[66:Spt:218154.0,218149.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 218160[66:Res:218156.0,61.1] always3(s46) || -> . % 76.30/76.41 218161[66:SSi:218160.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.41 218162[64:Spt:218161.0,218061.0,218062.0] || until2p7(s45)*+ -> . % 76.30/76.41 218163[64:Spt:218161.0,218061.1] || -> node4(s44)*. % 76.30/76.41 218165[64:MRR:786.0,218163.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.41 218168[64:Res:53.1,218165.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.41 218170[64:MRR:218168.0,218051.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 218172[64:Res:218170.0,61.1] always3(s45) || -> . % 76.30/76.41 218173[64:SSi:218172.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.41 218174[62:Spt:218173.0,218015.0,218018.0] || trans(s49,s44)*+ -> . % 76.30/76.41 218175[62:Spt:218173.0,218015.1,218015.2,218015.3,218015.4,218015.5,218015.6,218015.7,218015.8,218015.9,218015.10,218015.11,218015.12,218015.13,218015.14,218015.15,218015.16,218015.17,218015.18,218015.19,218015.20,218015.21,218015.22,218015.23,218015.24,218015.25,218015.26,218015.27,218015.28,218015.29,218015.30,218015.31,218015.32,218015.33,218015.34,218015.35,218015.36,218015.37] || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.41 218177[62:MRR:218017.1,218174.0] xuntil6(s49) || -> trans(s49,s43) trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.41 218178[63:Spt:218175.0] || -> trans(s49,s43)*. % 76.30/76.41 218179[63:Res:218178.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s43)*. % 76.30/76.41 218181[63:Res:218178.0,60.0] || -> node2(s49,s43)*. % 76.30/76.41 218182[63:SSi:218179.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s43)*. % 76.30/76.41 218183[63:Res:218181.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 218207[63:SoR:218183.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 218209[63:SoR:218207.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 76.30/76.41 218210[63:SSi:218209.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s43,c_busy)* xuntil6(s49). % 76.30/76.41 218211[64:Spt:218210.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 218213[64:Res:218211.0,61.1] always3(s43) || -> . % 76.30/76.41 218214[64:SSi:218213.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.41 218215[64:Spt:218214.0,218210.1,218211.0] || m_main_v_state(s43,c_busy)*+ -> . % 76.30/76.41 218216[64:Spt:218214.0,218210.0,218210.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 218220[64:MRR:218207.2,218215.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 218221[64:Res:53.1,218216.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 218223[64:MRR:218221.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 218224[64:MRR:218182.0,218223.0] || -> until2p7(s43)*. % 76.30/76.41 218225[64:MRR:241.0,218224.0] || -> until2p7(s44)* node4(s43). % 76.30/76.41 218226[65:Spt:218225.0] || -> until2p7(s44)*. % 76.30/76.41 218227[65:MRR:539.0,218226.0] || -> until2p7(s45)* node4(s44). % 76.30/76.41 218228[66:Spt:218227.0] || -> until2p7(s45)*. % 76.30/76.41 218229[66:MRR:544.0,218228.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 218230[67:Spt:218229.0] || -> until2p7(s46)*. % 76.30/76.41 218231[67:MRR:549.0,218230.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 218232[68:Spt:218231.0] || -> until2p7(s47)*. % 76.30/76.41 218233[68:MRR:554.0,218232.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 218234[69:Spt:218233.0] || -> until2p7(s48)*. % 76.30/76.41 218235[69:MRR:559.0,218234.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 218236[70:Spt:218235.0] || -> until2p7(s49)*. % 76.30/76.41 218237[70:MRR:194.0,218236.0] || -> node4(s49)*. % 76.30/76.41 218238[70:MRR:218220.0,218237.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 218239[70:Res:53.1,218238.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 218241[70:MRR:218239.0,78381.0] || -> . % 76.30/76.41 218242[70:Spt:218241.0,218235.0,218236.0] || until2p7(s49)*+ -> . % 76.30/76.41 218243[70:Spt:218241.0,218235.1] || -> node4(s48)*. % 76.30/76.41 218244[70:MRR:78384.0,218243.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 218247[70:Res:53.1,218244.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 218250[70:Res:218247.0,61.1] always3(s48) || -> . % 76.30/76.41 218251[70:SSi:218250.0,78281.0,78387.0,217618.0,218234.0,218243.0] || -> . % 76.30/76.41 218252[69:Spt:218251.0,218233.0,218234.0] || until2p7(s48)*+ -> . % 76.30/76.41 218253[69:Spt:218251.0,218233.1] || -> node4(s47)*. % 76.30/76.41 218255[69:MRR:777.0,218253.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 218273[69:Res:53.1,218255.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 218275[70:Spt:218273.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 218277[70:Res:218275.0,61.1] always3(s47) || -> . % 76.30/76.41 218278[70:SSi:218277.0,78277.0,78280.0,217617.0,218232.0,218253.0] || -> . % 76.30/76.41 218279[70:Spt:218278.0,218273.0,218275.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 218280[70:Spt:218278.0,218273.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 218284[70:Res:218280.0,61.1] always3(s48) || -> . % 76.30/76.41 218285[70:SSi:218284.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.41 218286[68:Spt:218285.0,218231.0,218232.0] || until2p7(s47)*+ -> . % 76.30/76.41 218287[68:Spt:218285.0,218231.1] || -> node4(s46)*. % 76.30/76.41 218289[68:MRR:780.0,218287.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 218296[68:Res:53.1,218289.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 218301[69:Spt:218296.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 218303[69:Res:218301.0,61.1] always3(s46) || -> . % 76.30/76.41 218304[69:SSi:218303.0,78272.0,78276.0,217616.0,218230.0,218287.0] || -> . % 76.30/76.41 218305[69:Spt:218304.0,218296.0,218301.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 218306[69:Spt:218304.0,218296.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 218310[69:Res:218306.0,61.1] always3(s47) || -> . % 76.30/76.41 218311[69:SSi:218310.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.41 218312[67:Spt:218311.0,218229.0,218230.0] || until2p7(s46)*+ -> . % 76.30/76.41 218313[67:Spt:218311.0,218229.1] || -> node4(s45)*. % 76.30/76.41 218315[67:MRR:783.0,218313.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 218318[67:Res:53.1,218315.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 218320[68:Spt:218318.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 218322[68:Res:218320.0,61.1] always3(s45) || -> . % 76.30/76.41 218323[68:SSi:218322.0,78268.0,78271.0,217615.0,218228.0,218313.0] || -> . % 76.30/76.41 218324[68:Spt:218323.0,218318.0,218320.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.41 218325[68:Spt:218323.0,218318.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 218329[68:Res:218325.0,61.1] always3(s46) || -> . % 76.30/76.41 218330[68:SSi:218329.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.41 218331[66:Spt:218330.0,218227.0,218228.0] || until2p7(s45)*+ -> . % 76.30/76.41 218332[66:Spt:218330.0,218227.1] || -> node4(s44)*. % 76.30/76.41 218334[66:MRR:786.0,218332.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.41 218337[66:Res:53.1,218334.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.41 218339[67:Spt:218337.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 218341[67:Res:218339.0,61.1] always3(s44) || -> . % 76.30/76.41 218342[67:SSi:218341.0,78263.0,78267.0,217614.0,218226.0,218332.0] || -> . % 76.30/76.41 218343[67:Spt:218342.0,218337.0,218339.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.41 218344[67:Spt:218342.0,218337.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 218348[67:Res:218344.0,61.1] always3(s45) || -> . % 76.30/76.41 218349[67:SSi:218348.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.41 218350[65:Spt:218349.0,218225.0,218226.0] || until2p7(s44)*+ -> . % 76.30/76.41 218351[65:Spt:218349.0,218225.1] || -> node4(s43)*. % 76.30/76.41 218353[65:MRR:789.0,218351.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.41 218356[65:Res:53.1,218353.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.41 218358[65:MRR:218356.0,218215.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 218360[65:Res:218358.0,61.1] always3(s44) || -> . % 76.30/76.41 218361[65:SSi:218360.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.41 218362[63:Spt:218361.0,218175.0,218178.0] || trans(s49,s43)*+ -> . % 76.30/76.41 218363[63:Spt:218361.0,218175.1,218175.2,218175.3,218175.4,218175.5,218175.6,218175.7,218175.8,218175.9,218175.10,218175.11,218175.12,218175.13,218175.14,218175.15,218175.16,218175.17,218175.18,218175.19,218175.20,218175.21,218175.22,218175.23,218175.24,218175.25,218175.26,218175.27,218175.28,218175.29,218175.30,218175.31,218175.32,218175.33,218175.34,218175.35,218175.36] || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.41 218365[63:MRR:218177.1,218362.0] xuntil6(s49) || -> trans(s49,s42) trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.41 218366[64:Spt:218363.0] || -> trans(s49,s42)*. % 76.30/76.41 218367[64:Res:218366.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s42)*. % 76.30/76.41 218369[64:Res:218366.0,60.0] || -> node2(s49,s42)*. % 76.30/76.41 218370[64:SSi:218367.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s42)*. % 76.30/76.41 218371[64:Res:218369.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 218399[64:SoR:218371.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 218401[64:SoR:218399.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s42,c_busy)* xuntil6(s49). % 76.30/76.41 218402[64:SSi:218401.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s42,c_busy)* xuntil6(s49). % 76.30/76.41 218403[65:Spt:218402.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 218405[65:Res:218403.0,61.1] always3(s42) || -> . % 76.30/76.41 218406[65:SSi:218405.0,78254.0,78258.0,217612.0] || -> . % 76.30/76.41 218407[65:Spt:218406.0,218402.1,218403.0] || m_main_v_state(s42,c_busy)*+ -> . % 76.30/76.41 218408[65:Spt:218406.0,218402.0,218402.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 218412[65:MRR:218399.2,218407.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 218413[65:Res:53.1,218408.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 218415[65:MRR:218413.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 218416[65:MRR:218370.0,218415.0] || -> until2p7(s42)*. % 76.30/76.41 218417[65:MRR:240.0,218416.0] || -> until2p7(s43)* node4(s42). % 76.30/76.41 218418[66:Spt:218417.0] || -> until2p7(s43)*. % 76.30/76.41 218419[66:MRR:241.0,218418.0] || -> until2p7(s44)* node4(s43). % 76.30/76.41 218420[67:Spt:218419.0] || -> until2p7(s44)*. % 76.30/76.41 218421[67:MRR:539.0,218420.0] || -> until2p7(s45)* node4(s44). % 76.30/76.41 218422[68:Spt:218421.0] || -> until2p7(s45)*. % 76.30/76.41 218423[68:MRR:544.0,218422.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 218424[69:Spt:218423.0] || -> until2p7(s46)*. % 76.30/76.41 218425[69:MRR:549.0,218424.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 218426[70:Spt:218425.0] || -> until2p7(s47)*. % 76.30/76.41 218427[70:MRR:554.0,218426.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 218428[71:Spt:218427.0] || -> until2p7(s48)*. % 76.30/76.41 218429[71:MRR:559.0,218428.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 218430[72:Spt:218429.0] || -> until2p7(s49)*. % 76.30/76.41 218431[72:MRR:194.0,218430.0] || -> node4(s49)*. % 76.30/76.41 218432[72:MRR:218412.0,218431.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 218433[72:Res:53.1,218432.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 218435[72:MRR:218433.0,78381.0] || -> . % 76.30/76.41 218436[72:Spt:218435.0,218429.0,218430.0] || until2p7(s49)*+ -> . % 76.30/76.41 218437[72:Spt:218435.0,218429.1] || -> node4(s48)*. % 76.30/76.41 218438[72:MRR:78384.0,218437.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 218441[72:Res:53.1,218438.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 218444[72:Res:218441.0,61.1] always3(s48) || -> . % 76.30/76.41 218445[72:SSi:218444.0,78281.0,78387.0,217618.0,218428.0,218437.0] || -> . % 76.30/76.41 218446[71:Spt:218445.0,218427.0,218428.0] || until2p7(s48)*+ -> . % 76.30/76.41 218447[71:Spt:218445.0,218427.1] || -> node4(s47)*. % 76.30/76.41 218449[71:MRR:777.0,218447.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 218464[71:Res:53.1,218449.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 218469[72:Spt:218464.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 218471[72:Res:218469.0,61.1] always3(s47) || -> . % 76.30/76.41 218472[72:SSi:218471.0,78277.0,78280.0,217617.0,218426.0,218447.0] || -> . % 76.30/76.41 218473[72:Spt:218472.0,218464.0,218469.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 218474[72:Spt:218472.0,218464.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 218478[72:Res:218474.0,61.1] always3(s48) || -> . % 76.30/76.41 218479[72:SSi:218478.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.41 218480[70:Spt:218479.0,218425.0,218426.0] || until2p7(s47)*+ -> . % 76.30/76.41 218481[70:Spt:218479.0,218425.1] || -> node4(s46)*. % 76.30/76.41 218483[70:MRR:780.0,218481.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 218490[70:Res:53.1,218483.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 218492[71:Spt:218490.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 218494[71:Res:218492.0,61.1] always3(s46) || -> . % 76.30/76.41 218495[71:SSi:218494.0,78272.0,78276.0,217616.0,218424.0,218481.0] || -> . % 76.30/76.41 218496[71:Spt:218495.0,218490.0,218492.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 218497[71:Spt:218495.0,218490.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 218501[71:Res:218497.0,61.1] always3(s47) || -> . % 76.30/76.41 218502[71:SSi:218501.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.41 218503[69:Spt:218502.0,218423.0,218424.0] || until2p7(s46)*+ -> . % 76.30/76.41 218504[69:Spt:218502.0,218423.1] || -> node4(s45)*. % 76.30/76.41 218506[69:MRR:783.0,218504.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 218509[69:Res:53.1,218506.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 218514[70:Spt:218509.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 218516[70:Res:218514.0,61.1] always3(s45) || -> . % 76.30/76.41 218517[70:SSi:218516.0,78268.0,78271.0,217615.0,218422.0,218504.0] || -> . % 76.30/76.41 218518[70:Spt:218517.0,218509.0,218514.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.41 218519[70:Spt:218517.0,218509.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 218523[70:Res:218519.0,61.1] always3(s46) || -> . % 76.30/76.41 218524[70:SSi:218523.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.41 218525[68:Spt:218524.0,218421.0,218422.0] || until2p7(s45)*+ -> . % 76.30/76.41 218526[68:Spt:218524.0,218421.1] || -> node4(s44)*. % 76.30/76.41 218528[68:MRR:786.0,218526.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.41 218531[68:Res:53.1,218528.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.41 218533[69:Spt:218531.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 218535[69:Res:218533.0,61.1] always3(s44) || -> . % 76.30/76.41 218536[69:SSi:218535.0,78263.0,78267.0,217614.0,218420.0,218526.0] || -> . % 76.30/76.41 218537[69:Spt:218536.0,218531.0,218533.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.41 218538[69:Spt:218536.0,218531.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 218542[69:Res:218538.0,61.1] always3(s45) || -> . % 76.30/76.41 218543[69:SSi:218542.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.41 218544[67:Spt:218543.0,218419.0,218420.0] || until2p7(s44)*+ -> . % 76.30/76.41 218545[67:Spt:218543.0,218419.1] || -> node4(s43)*. % 76.30/76.41 218547[67:MRR:789.0,218545.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.41 218550[67:Res:53.1,218547.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.41 218552[68:Spt:218550.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 218554[68:Res:218552.0,61.1] always3(s43) || -> . % 76.30/76.41 218555[68:SSi:218554.0,78259.0,78262.0,217613.0,218418.0,218545.0] || -> . % 76.30/76.41 218556[68:Spt:218555.0,218550.0,218552.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.41 218557[68:Spt:218555.0,218550.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 218561[68:Res:218557.0,61.1] always3(s44) || -> . % 76.30/76.41 218562[68:SSi:218561.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.41 218563[66:Spt:218562.0,218417.0,218418.0] || until2p7(s43)*+ -> . % 76.30/76.41 218564[66:Spt:218562.0,218417.1] || -> node4(s42)*. % 76.30/76.41 218566[66:MRR:792.0,218564.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.41 218569[66:Res:53.1,218566.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.41 218571[66:MRR:218569.0,218407.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 218573[66:Res:218571.0,61.1] always3(s43) || -> . % 76.30/76.41 218574[66:SSi:218573.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.41 218575[64:Spt:218574.0,218363.0,218366.0] || trans(s49,s42)*+ -> . % 76.30/76.41 218576[64:Spt:218574.0,218363.1,218363.2,218363.3,218363.4,218363.5,218363.6,218363.7,218363.8,218363.9,218363.10,218363.11,218363.12,218363.13,218363.14,218363.15,218363.16,218363.17,218363.18,218363.19,218363.20,218363.21,218363.22,218363.23,218363.24,218363.25,218363.26,218363.27,218363.28,218363.29,218363.30,218363.31,218363.32,218363.33,218363.34,218363.35] || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.41 218578[64:MRR:218365.1,218575.0] xuntil6(s49) || -> trans(s49,s41) trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.41 218579[65:Spt:218576.0] || -> trans(s49,s41)*. % 76.30/76.41 218580[65:Res:218579.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s41)*. % 76.30/76.41 218582[65:Res:218579.0,60.0] || -> node2(s49,s41)*. % 76.30/76.41 218583[65:SSi:218580.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s41)*. % 76.30/76.41 218584[65:Res:218582.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 218613[65:SoR:218584.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 218615[65:SoR:218613.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s41,c_busy)* xuntil6(s49). % 76.30/76.41 218616[65:SSi:218615.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s41,c_busy)* xuntil6(s49). % 76.30/76.41 218617[66:Spt:218616.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 218619[66:Res:218617.0,61.1] always3(s41) || -> . % 76.30/76.41 218620[66:SSi:218619.0,78250.0,78253.0,217611.0] || -> . % 76.30/76.41 218621[66:Spt:218620.0,218616.1,218617.0] || m_main_v_state(s41,c_busy)*+ -> . % 76.30/76.41 218622[66:Spt:218620.0,218616.0,218616.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 218626[66:MRR:218613.2,218621.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 218627[66:Res:53.1,218622.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 218629[66:MRR:218627.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 218630[66:MRR:218583.0,218629.0] || -> until2p7(s41)*. % 76.30/76.41 218631[66:MRR:239.0,218630.0] || -> until2p7(s42)* node4(s41). % 76.30/76.41 218632[67:Spt:218631.0] || -> until2p7(s42)*. % 76.30/76.41 218633[67:MRR:240.0,218632.0] || -> until2p7(s43)* node4(s42). % 76.30/76.41 218634[68:Spt:218633.0] || -> until2p7(s43)*. % 76.30/76.41 218635[68:MRR:241.0,218634.0] || -> until2p7(s44)* node4(s43). % 76.30/76.41 218636[69:Spt:218635.0] || -> until2p7(s44)*. % 76.30/76.41 218637[69:MRR:539.0,218636.0] || -> until2p7(s45)* node4(s44). % 76.30/76.41 218638[70:Spt:218637.0] || -> until2p7(s45)*. % 76.30/76.41 218639[70:MRR:544.0,218638.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 218640[71:Spt:218639.0] || -> until2p7(s46)*. % 76.30/76.41 218641[71:MRR:549.0,218640.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 218642[72:Spt:218641.0] || -> until2p7(s47)*. % 76.30/76.41 218643[72:MRR:554.0,218642.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 218644[73:Spt:218643.0] || -> until2p7(s48)*. % 76.30/76.41 218645[73:MRR:559.0,218644.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 218646[74:Spt:218645.0] || -> until2p7(s49)*. % 76.30/76.41 218647[74:MRR:194.0,218646.0] || -> node4(s49)*. % 76.30/76.41 218648[74:MRR:218626.0,218647.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 218652[74:Res:53.1,218648.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 218654[74:MRR:218652.0,78381.0] || -> . % 76.30/76.41 218655[74:Spt:218654.0,218645.0,218646.0] || until2p7(s49)*+ -> . % 76.30/76.41 218656[74:Spt:218654.0,218645.1] || -> node4(s48)*. % 76.30/76.41 218657[74:MRR:78384.0,218656.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 218660[74:Res:53.1,218657.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 218663[74:Res:218660.0,61.1] always3(s48) || -> . % 76.30/76.41 218664[74:SSi:218663.0,78281.0,78387.0,217618.0,218644.0,218656.0] || -> . % 76.30/76.41 218665[73:Spt:218664.0,218643.0,218644.0] || until2p7(s48)*+ -> . % 76.30/76.41 218666[73:Spt:218664.0,218643.1] || -> node4(s47)*. % 76.30/76.41 218668[73:MRR:777.0,218666.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 218680[73:Res:53.1,218668.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 218682[74:Spt:218680.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 218684[74:Res:218682.0,61.1] always3(s47) || -> . % 76.30/76.41 218685[74:SSi:218684.0,78277.0,78280.0,217617.0,218642.0,218666.0] || -> . % 76.30/76.41 218686[74:Spt:218685.0,218680.0,218682.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 218687[74:Spt:218685.0,218680.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 218691[74:Res:218687.0,61.1] always3(s48) || -> . % 76.30/76.41 218692[74:SSi:218691.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.41 218693[72:Spt:218692.0,218641.0,218642.0] || until2p7(s47)*+ -> . % 76.30/76.41 218694[72:Spt:218692.0,218641.1] || -> node4(s46)*. % 76.30/76.41 218696[72:MRR:780.0,218694.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 218703[72:Res:53.1,218696.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 218708[73:Spt:218703.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 218710[73:Res:218708.0,61.1] always3(s46) || -> . % 76.30/76.41 218711[73:SSi:218710.0,78272.0,78276.0,217616.0,218640.0,218694.0] || -> . % 76.30/76.41 218712[73:Spt:218711.0,218703.0,218708.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 218713[73:Spt:218711.0,218703.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 218717[73:Res:218713.0,61.1] always3(s47) || -> . % 76.30/76.41 218718[73:SSi:218717.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.41 218719[71:Spt:218718.0,218639.0,218640.0] || until2p7(s46)*+ -> . % 76.30/76.41 218720[71:Spt:218718.0,218639.1] || -> node4(s45)*. % 76.30/76.41 218722[71:MRR:783.0,218720.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 218725[71:Res:53.1,218722.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 218727[72:Spt:218725.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 218729[72:Res:218727.0,61.1] always3(s45) || -> . % 76.30/76.41 218730[72:SSi:218729.0,78268.0,78271.0,217615.0,218638.0,218720.0] || -> . % 76.30/76.41 218731[72:Spt:218730.0,218725.0,218727.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.41 218732[72:Spt:218730.0,218725.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 218736[72:Res:218732.0,61.1] always3(s46) || -> . % 76.30/76.41 218737[72:SSi:218736.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.41 218738[70:Spt:218737.0,218637.0,218638.0] || until2p7(s45)*+ -> . % 76.30/76.41 218739[70:Spt:218737.0,218637.1] || -> node4(s44)*. % 76.30/76.41 218741[70:MRR:786.0,218739.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.41 218744[70:Res:53.1,218741.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.41 218746[71:Spt:218744.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 218748[71:Res:218746.0,61.1] always3(s44) || -> . % 76.30/76.41 218749[71:SSi:218748.0,78263.0,78267.0,217614.0,218636.0,218739.0] || -> . % 76.30/76.41 218750[71:Spt:218749.0,218744.0,218746.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.41 218751[71:Spt:218749.0,218744.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 218755[71:Res:218751.0,61.1] always3(s45) || -> . % 76.30/76.41 218756[71:SSi:218755.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.41 218757[69:Spt:218756.0,218635.0,218636.0] || until2p7(s44)*+ -> . % 76.30/76.41 218758[69:Spt:218756.0,218635.1] || -> node4(s43)*. % 76.30/76.41 218760[69:MRR:789.0,218758.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.41 218763[69:Res:53.1,218760.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.41 218765[70:Spt:218763.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 218767[70:Res:218765.0,61.1] always3(s43) || -> . % 76.30/76.41 218768[70:SSi:218767.0,78259.0,78262.0,217613.0,218634.0,218758.0] || -> . % 76.30/76.41 218769[70:Spt:218768.0,218763.0,218765.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.41 218770[70:Spt:218768.0,218763.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 218774[70:Res:218770.0,61.1] always3(s44) || -> . % 76.30/76.41 218775[70:SSi:218774.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.41 218776[68:Spt:218775.0,218633.0,218634.0] || until2p7(s43)*+ -> . % 76.30/76.41 218777[68:Spt:218775.0,218633.1] || -> node4(s42)*. % 76.30/76.41 218779[68:MRR:792.0,218777.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.41 218782[68:Res:53.1,218779.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.41 218787[69:Spt:218782.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 218789[69:Res:218787.0,61.1] always3(s42) || -> . % 76.30/76.41 218790[69:SSi:218789.0,78254.0,78258.0,217612.0,218632.0,218777.0] || -> . % 76.30/76.41 218791[69:Spt:218790.0,218782.0,218787.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.41 218792[69:Spt:218790.0,218782.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 218796[69:Res:218792.0,61.1] always3(s43) || -> . % 76.30/76.41 218797[69:SSi:218796.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.41 218798[67:Spt:218797.0,218631.0,218632.0] || until2p7(s42)*+ -> . % 76.30/76.41 218799[67:Spt:218797.0,218631.1] || -> node4(s41)*. % 76.30/76.41 218801[67:MRR:795.0,218799.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.41 218804[67:Res:53.1,218801.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.41 218806[67:MRR:218804.0,218621.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 218808[67:Res:218806.0,61.1] always3(s42) || -> . % 76.30/76.41 218809[67:SSi:218808.0,78254.0,78258.0,217612.0] || -> . % 76.30/76.41 218810[65:Spt:218809.0,218576.0,218579.0] || trans(s49,s41)*+ -> . % 76.30/76.41 218811[65:Spt:218809.0,218576.1,218576.2,218576.3,218576.4,218576.5,218576.6,218576.7,218576.8,218576.9,218576.10,218576.11,218576.12,218576.13,218576.14,218576.15,218576.16,218576.17,218576.18,218576.19,218576.20,218576.21,218576.22,218576.23,218576.24,218576.25,218576.26,218576.27,218576.28,218576.29,218576.30,218576.31,218576.32,218576.33,218576.34] || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.41 218813[65:MRR:218578.1,218810.0] xuntil6(s49) || -> trans(s49,s40) trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.41 218814[66:Spt:218811.0] || -> trans(s49,s40)*. % 76.30/76.41 218815[66:Res:218814.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s40)*. % 76.30/76.41 218817[66:Res:218814.0,60.0] || -> node2(s49,s40)*. % 76.30/76.41 218818[66:SSi:218815.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s40)*. % 76.30/76.41 218819[66:Res:218817.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 218852[66:SoR:218819.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 218854[66:SoR:218852.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s40,c_busy)* xuntil6(s49). % 76.30/76.41 218855[66:SSi:218854.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s40,c_busy)* xuntil6(s49). % 76.30/76.41 218856[67:Spt:218855.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.41 218858[67:Res:218856.0,61.1] always3(s40) || -> . % 76.30/76.41 218859[67:SSi:218858.0,78245.0,78249.0,217610.0] || -> . % 76.30/76.41 218860[67:Spt:218859.0,218855.1,218856.0] || m_main_v_state(s40,c_busy)*+ -> . % 76.30/76.41 218861[67:Spt:218859.0,218855.0,218855.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 218865[67:MRR:218852.2,218860.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 218866[67:Res:53.1,218861.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 218868[67:MRR:218866.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 218869[67:MRR:218818.0,218868.0] || -> until2p7(s40)*. % 76.30/76.41 218870[67:MRR:238.0,218869.0] || -> until2p7(s41)* node4(s40). % 76.30/76.41 218871[68:Spt:218870.0] || -> until2p7(s41)*. % 76.30/76.41 218872[68:MRR:239.0,218871.0] || -> until2p7(s42)* node4(s41). % 76.30/76.41 218873[69:Spt:218872.0] || -> until2p7(s42)*. % 76.30/76.41 218874[69:MRR:240.0,218873.0] || -> until2p7(s43)* node4(s42). % 76.30/76.41 218875[70:Spt:218874.0] || -> until2p7(s43)*. % 76.30/76.41 218876[70:MRR:241.0,218875.0] || -> until2p7(s44)* node4(s43). % 76.30/76.41 218877[71:Spt:218876.0] || -> until2p7(s44)*. % 76.30/76.41 218878[71:MRR:539.0,218877.0] || -> until2p7(s45)* node4(s44). % 76.30/76.41 218879[72:Spt:218878.0] || -> until2p7(s45)*. % 76.30/76.41 218880[72:MRR:544.0,218879.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 218881[73:Spt:218880.0] || -> until2p7(s46)*. % 76.30/76.41 218882[73:MRR:549.0,218881.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 218883[74:Spt:218882.0] || -> until2p7(s47)*. % 76.30/76.41 218884[74:MRR:554.0,218883.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 218885[75:Spt:218884.0] || -> until2p7(s48)*. % 76.30/76.41 218886[75:MRR:559.0,218885.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 218887[76:Spt:218886.0] || -> until2p7(s49)*. % 76.30/76.41 218888[76:MRR:194.0,218887.0] || -> node4(s49)*. % 76.30/76.41 218889[76:MRR:218865.0,218888.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 218890[76:Res:53.1,218889.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 218892[76:MRR:218890.0,78381.0] || -> . % 76.30/76.41 218893[76:Spt:218892.0,218886.0,218887.0] || until2p7(s49)*+ -> . % 76.30/76.41 218894[76:Spt:218892.0,218886.1] || -> node4(s48)*. % 76.30/76.41 218895[76:MRR:78384.0,218894.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 218898[76:Res:53.1,218895.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 218901[76:Res:218898.0,61.1] always3(s48) || -> . % 76.30/76.41 218902[76:SSi:218901.0,78281.0,78387.0,217618.0,218885.0,218894.0] || -> . % 76.30/76.41 218903[75:Spt:218902.0,218884.0,218885.0] || until2p7(s48)*+ -> . % 76.30/76.41 218904[75:Spt:218902.0,218884.1] || -> node4(s47)*. % 76.30/76.41 218906[75:MRR:777.0,218904.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 218921[75:Res:53.1,218906.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 218923[76:Spt:218921.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 218925[76:Res:218923.0,61.1] always3(s47) || -> . % 76.30/76.41 218926[76:SSi:218925.0,78277.0,78280.0,217617.0,218883.0,218904.0] || -> . % 76.30/76.41 218927[76:Spt:218926.0,218921.0,218923.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 218928[76:Spt:218926.0,218921.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 218932[76:Res:218928.0,61.1] always3(s48) || -> . % 76.30/76.41 218933[76:SSi:218932.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.41 218934[74:Spt:218933.0,218882.0,218883.0] || until2p7(s47)*+ -> . % 76.30/76.41 218935[74:Spt:218933.0,218882.1] || -> node4(s46)*. % 76.30/76.41 218937[74:MRR:780.0,218935.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 218947[74:Res:53.1,218937.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 218949[75:Spt:218947.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 218951[75:Res:218949.0,61.1] always3(s46) || -> . % 76.30/76.41 218952[75:SSi:218951.0,78272.0,78276.0,217616.0,218881.0,218935.0] || -> . % 76.30/76.41 218953[75:Spt:218952.0,218947.0,218949.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 218954[75:Spt:218952.0,218947.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 218958[75:Res:218954.0,61.1] always3(s47) || -> . % 76.30/76.41 218959[75:SSi:218958.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.41 218960[73:Spt:218959.0,218880.0,218881.0] || until2p7(s46)*+ -> . % 76.30/76.41 218961[73:Spt:218959.0,218880.1] || -> node4(s45)*. % 76.30/76.41 218963[73:MRR:783.0,218961.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 218966[73:Res:53.1,218963.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 218968[74:Spt:218966.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 218970[74:Res:218968.0,61.1] always3(s45) || -> . % 76.30/76.41 218971[74:SSi:218970.0,78268.0,78271.0,217615.0,218879.0,218961.0] || -> . % 76.30/76.41 218972[74:Spt:218971.0,218966.0,218968.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.41 218973[74:Spt:218971.0,218966.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 218977[74:Res:218973.0,61.1] always3(s46) || -> . % 76.30/76.41 218978[74:SSi:218977.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.41 218979[72:Spt:218978.0,218878.0,218879.0] || until2p7(s45)*+ -> . % 76.30/76.41 218980[72:Spt:218978.0,218878.1] || -> node4(s44)*. % 76.30/76.41 218982[72:MRR:786.0,218980.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.41 218985[72:Res:53.1,218982.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.41 218987[73:Spt:218985.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 218989[73:Res:218987.0,61.1] always3(s44) || -> . % 76.30/76.41 218990[73:SSi:218989.0,78263.0,78267.0,217614.0,218877.0,218980.0] || -> . % 76.30/76.41 218991[73:Spt:218990.0,218985.0,218987.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.41 218992[73:Spt:218990.0,218985.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 218996[73:Res:218992.0,61.1] always3(s45) || -> . % 76.30/76.41 218997[73:SSi:218996.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.41 218998[71:Spt:218997.0,218876.0,218877.0] || until2p7(s44)*+ -> . % 76.30/76.41 218999[71:Spt:218997.0,218876.1] || -> node4(s43)*. % 76.30/76.41 219001[71:MRR:789.0,218999.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.41 219004[71:Res:53.1,219001.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.41 219009[72:Spt:219004.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 219011[72:Res:219009.0,61.1] always3(s43) || -> . % 76.30/76.41 219012[72:SSi:219011.0,78259.0,78262.0,217613.0,218875.0,218999.0] || -> . % 76.30/76.41 219013[72:Spt:219012.0,219004.0,219009.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.41 219014[72:Spt:219012.0,219004.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 219018[72:Res:219014.0,61.1] always3(s44) || -> . % 76.30/76.41 219019[72:SSi:219018.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.41 219020[70:Spt:219019.0,218874.0,218875.0] || until2p7(s43)*+ -> . % 76.30/76.41 219021[70:Spt:219019.0,218874.1] || -> node4(s42)*. % 76.30/76.41 219023[70:MRR:792.0,219021.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.41 219026[70:Res:53.1,219023.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.41 219028[71:Spt:219026.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 219030[71:Res:219028.0,61.1] always3(s42) || -> . % 76.30/76.41 219031[71:SSi:219030.0,78254.0,78258.0,217612.0,218873.0,219021.0] || -> . % 76.30/76.41 219032[71:Spt:219031.0,219026.0,219028.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.41 219033[71:Spt:219031.0,219026.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 219037[71:Res:219033.0,61.1] always3(s43) || -> . % 76.30/76.41 219038[71:SSi:219037.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.41 219039[69:Spt:219038.0,218872.0,218873.0] || until2p7(s42)*+ -> . % 76.30/76.41 219040[69:Spt:219038.0,218872.1] || -> node4(s41)*. % 76.30/76.41 219042[69:MRR:795.0,219040.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.41 219045[69:Res:53.1,219042.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.41 219047[70:Spt:219045.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 219049[70:Res:219047.0,61.1] always3(s41) || -> . % 76.30/76.41 219050[70:SSi:219049.0,78250.0,78253.0,217611.0,218871.0,219040.0] || -> . % 76.30/76.41 219051[70:Spt:219050.0,219045.0,219047.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.41 219052[70:Spt:219050.0,219045.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 219056[70:Res:219052.0,61.1] always3(s42) || -> . % 76.30/76.41 219057[70:SSi:219056.0,78254.0,78258.0,217612.0] || -> . % 76.30/76.41 219058[68:Spt:219057.0,218870.0,218871.0] || until2p7(s41)*+ -> . % 76.30/76.41 219059[68:Spt:219057.0,218870.1] || -> node4(s40)*. % 76.30/76.41 219061[68:MRR:798.0,219059.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.41 219064[68:Res:53.1,219061.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.41 219066[68:MRR:219064.0,218860.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.41 219068[68:Res:219066.0,61.1] always3(s41) || -> . % 76.30/76.41 219069[68:SSi:219068.0,78250.0,78253.0,217611.0] || -> . % 76.30/76.41 219070[66:Spt:219069.0,218811.0,218814.0] || trans(s49,s40)*+ -> . % 76.30/76.41 219071[66:Spt:219069.0,218811.1,218811.2,218811.3,218811.4,218811.5,218811.6,218811.7,218811.8,218811.9,218811.10,218811.11,218811.12,218811.13,218811.14,218811.15,218811.16,218811.17,218811.18,218811.19,218811.20,218811.21,218811.22,218811.23,218811.24,218811.25,218811.26,218811.27,218811.28,218811.29,218811.30,218811.31,218811.32,218811.33] || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.41 219073[66:MRR:218813.1,219070.0] xuntil6(s49) || -> trans(s49,s39) trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.41 219074[67:Spt:219071.0] || -> trans(s49,s39)*. % 76.30/76.41 219075[67:Res:219074.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s39)*. % 76.30/76.41 219077[67:Res:219074.0,60.0] || -> node2(s49,s39)*. % 76.30/76.41 219078[67:SSi:219075.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s39)*. % 76.30/76.41 219079[67:Res:219077.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 219116[67:SoR:219079.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 219118[67:SoR:219116.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 76.30/76.41 219119[67:SSi:219118.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s39,c_busy)* xuntil6(s49). % 76.30/76.41 219120[68:Spt:219119.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.41 219122[68:Res:219120.0,61.1] always3(s39) || -> . % 76.30/76.41 219123[68:SSi:219122.0,78241.0,78244.0,217609.0] || -> . % 76.30/76.41 219124[68:Spt:219123.0,219119.1,219120.0] || m_main_v_state(s39,c_busy)*+ -> . % 76.30/76.41 219125[68:Spt:219123.0,219119.0,219119.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.41 219129[68:MRR:219116.2,219124.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.41 219130[68:Res:53.1,219125.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.41 219132[68:MRR:219130.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.41 219133[68:MRR:219078.0,219132.0] || -> until2p7(s39)*. % 76.30/76.41 219134[68:MRR:237.0,219133.0] || -> until2p7(s40)* node4(s39). % 76.30/76.41 219135[69:Spt:219134.0] || -> until2p7(s40)*. % 76.30/76.41 219136[69:MRR:238.0,219135.0] || -> until2p7(s41)* node4(s40). % 76.30/76.41 219137[70:Spt:219136.0] || -> until2p7(s41)*. % 76.30/76.41 219138[70:MRR:239.0,219137.0] || -> until2p7(s42)* node4(s41). % 76.30/76.41 219139[71:Spt:219138.0] || -> until2p7(s42)*. % 76.30/76.41 219140[71:MRR:240.0,219139.0] || -> until2p7(s43)* node4(s42). % 76.30/76.41 219141[72:Spt:219140.0] || -> until2p7(s43)*. % 76.30/76.41 219142[72:MRR:241.0,219141.0] || -> until2p7(s44)* node4(s43). % 76.30/76.41 219143[73:Spt:219142.0] || -> until2p7(s44)*. % 76.30/76.41 219144[73:MRR:539.0,219143.0] || -> until2p7(s45)* node4(s44). % 76.30/76.41 219145[74:Spt:219144.0] || -> until2p7(s45)*. % 76.30/76.41 219146[74:MRR:544.0,219145.0] || -> until2p7(s46)* node4(s45). % 76.30/76.41 219147[75:Spt:219146.0] || -> until2p7(s46)*. % 76.30/76.41 219148[75:MRR:549.0,219147.0] || -> until2p7(s47)* node4(s46). % 76.30/76.41 219149[76:Spt:219148.0] || -> until2p7(s47)*. % 76.30/76.41 219150[76:MRR:554.0,219149.0] || -> until2p7(s48)* node4(s47). % 76.30/76.41 219151[77:Spt:219150.0] || -> until2p7(s48)*. % 76.30/76.41 219152[77:MRR:559.0,219151.0] || -> until2p7(s49)* node4(s48). % 76.30/76.41 219153[78:Spt:219152.0] || -> until2p7(s49)*. % 76.30/76.41 219154[78:MRR:194.0,219153.0] || -> node4(s49)*. % 76.30/76.41 219155[78:MRR:219129.0,219154.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.41 219156[78:Res:53.1,219155.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.41 219158[78:MRR:219156.0,78381.0] || -> . % 76.30/76.41 219159[78:Spt:219158.0,219152.0,219153.0] || until2p7(s49)*+ -> . % 76.30/76.41 219160[78:Spt:219158.0,219152.1] || -> node4(s48)*. % 76.30/76.41 219161[78:MRR:78384.0,219160.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.41 219164[78:Res:53.1,219161.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 219167[78:Res:219164.0,61.1] always3(s48) || -> . % 76.30/76.41 219168[78:SSi:219167.0,78281.0,78387.0,217618.0,219151.0,219160.0] || -> . % 76.30/76.41 219169[77:Spt:219168.0,219150.0,219151.0] || until2p7(s48)*+ -> . % 76.30/76.41 219170[77:Spt:219168.0,219150.1] || -> node4(s47)*. % 76.30/76.41 219172[77:MRR:777.0,219170.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.41 219187[77:Res:53.1,219172.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.41 219189[78:Spt:219187.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 219191[78:Res:219189.0,61.1] always3(s47) || -> . % 76.30/76.41 219192[78:SSi:219191.0,78277.0,78280.0,217617.0,219149.0,219170.0] || -> . % 76.30/76.41 219193[78:Spt:219192.0,219187.0,219189.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.41 219194[78:Spt:219192.0,219187.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.41 219198[78:Res:219194.0,61.1] always3(s48) || -> . % 76.30/76.41 219199[78:SSi:219198.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.41 219200[76:Spt:219199.0,219148.0,219149.0] || until2p7(s47)*+ -> . % 76.30/76.41 219201[76:Spt:219199.0,219148.1] || -> node4(s46)*. % 76.30/76.41 219203[76:MRR:780.0,219201.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.41 219213[76:Res:53.1,219203.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.41 219215[77:Spt:219213.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 219217[77:Res:219215.0,61.1] always3(s46) || -> . % 76.30/76.41 219218[77:SSi:219217.0,78272.0,78276.0,217616.0,219147.0,219201.0] || -> . % 76.30/76.41 219219[77:Spt:219218.0,219213.0,219215.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.41 219220[77:Spt:219218.0,219213.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.41 219224[77:Res:219220.0,61.1] always3(s47) || -> . % 76.30/76.41 219225[77:SSi:219224.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.41 219226[75:Spt:219225.0,219146.0,219147.0] || until2p7(s46)*+ -> . % 76.30/76.41 219227[75:Spt:219225.0,219146.1] || -> node4(s45)*. % 76.30/76.41 219229[75:MRR:783.0,219227.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.41 219232[75:Res:53.1,219229.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.41 219234[76:Spt:219232.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 219236[76:Res:219234.0,61.1] always3(s45) || -> . % 76.30/76.41 219237[76:SSi:219236.0,78268.0,78271.0,217615.0,219145.0,219227.0] || -> . % 76.30/76.41 219238[76:Spt:219237.0,219232.0,219234.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.41 219239[76:Spt:219237.0,219232.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.41 219243[76:Res:219239.0,61.1] always3(s46) || -> . % 76.30/76.41 219244[76:SSi:219243.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.41 219245[74:Spt:219244.0,219144.0,219145.0] || until2p7(s45)*+ -> . % 76.30/76.41 219246[74:Spt:219244.0,219144.1] || -> node4(s44)*. % 76.30/76.41 219248[74:MRR:786.0,219246.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.41 219251[74:Res:53.1,219248.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.41 219253[75:Spt:219251.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 219255[75:Res:219253.0,61.1] always3(s44) || -> . % 76.30/76.41 219256[75:SSi:219255.0,78263.0,78267.0,217614.0,219143.0,219246.0] || -> . % 76.30/76.41 219257[75:Spt:219256.0,219251.0,219253.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.41 219258[75:Spt:219256.0,219251.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.41 219262[75:Res:219258.0,61.1] always3(s45) || -> . % 76.30/76.41 219263[75:SSi:219262.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.41 219264[73:Spt:219263.0,219142.0,219143.0] || until2p7(s44)*+ -> . % 76.30/76.41 219265[73:Spt:219263.0,219142.1] || -> node4(s43)*. % 76.30/76.41 219267[73:MRR:789.0,219265.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.41 219270[73:Res:53.1,219267.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.41 219275[74:Spt:219270.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.41 219277[74:Res:219275.0,61.1] always3(s43) || -> . % 76.30/76.41 219278[74:SSi:219277.0,78259.0,78262.0,217613.0,219141.0,219265.0] || -> . % 76.30/76.41 219279[74:Spt:219278.0,219270.0,219275.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.41 219280[74:Spt:219278.0,219270.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.41 219284[74:Res:219280.0,61.1] always3(s44) || -> . % 76.30/76.41 219285[74:SSi:219284.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.41 219286[72:Spt:219285.0,219140.0,219141.0] || until2p7(s43)*+ -> . % 76.30/76.41 219287[72:Spt:219285.0,219140.1] || -> node4(s42)*. % 76.30/76.41 219289[72:MRR:792.0,219287.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.41 219292[72:Res:53.1,219289.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.41 219294[73:Spt:219292.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.41 219296[73:Res:219294.0,61.1] always3(s42) || -> . % 76.30/76.41 219297[73:SSi:219296.0,78254.0,78258.0,217612.0,219139.0,219287.0] || -> . % 76.30/76.41 219298[73:Spt:219297.0,219292.0,219294.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.41 219299[73:Spt:219297.0,219292.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 219303[73:Res:219299.0,61.1] always3(s43) || -> . % 76.30/76.42 219304[73:SSi:219303.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.42 219305[71:Spt:219304.0,219138.0,219139.0] || until2p7(s42)*+ -> . % 76.30/76.42 219306[71:Spt:219304.0,219138.1] || -> node4(s41)*. % 76.30/76.42 219308[71:MRR:795.0,219306.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.42 219311[71:Res:53.1,219308.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.42 219313[72:Spt:219311.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 219315[72:Res:219313.0,61.1] always3(s41) || -> . % 76.30/76.42 219316[72:SSi:219315.0,78250.0,78253.0,217611.0,219137.0,219306.0] || -> . % 76.30/76.42 219317[72:Spt:219316.0,219311.0,219313.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.42 219318[72:Spt:219316.0,219311.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 219322[72:Res:219318.0,61.1] always3(s42) || -> . % 76.30/76.42 219323[72:SSi:219322.0,78254.0,78258.0,217612.0] || -> . % 76.30/76.42 219324[70:Spt:219323.0,219136.0,219137.0] || until2p7(s41)*+ -> . % 76.30/76.42 219325[70:Spt:219323.0,219136.1] || -> node4(s40)*. % 76.30/76.42 219327[70:MRR:798.0,219325.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.42 219330[70:Res:53.1,219327.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.42 219332[71:Spt:219330.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 219334[71:Res:219332.0,61.1] always3(s40) || -> . % 76.30/76.42 219335[71:SSi:219334.0,78245.0,78249.0,217610.0,219135.0,219325.0] || -> . % 76.30/76.42 219336[71:Spt:219335.0,219330.0,219332.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.42 219337[71:Spt:219335.0,219330.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 219341[71:Res:219337.0,61.1] always3(s41) || -> . % 76.30/76.42 219342[71:SSi:219341.0,78250.0,78253.0,217611.0] || -> . % 76.30/76.42 219343[69:Spt:219342.0,219134.0,219135.0] || until2p7(s40)*+ -> . % 76.30/76.42 219344[69:Spt:219342.0,219134.1] || -> node4(s39)*. % 76.30/76.42 219346[69:MRR:801.0,219344.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.42 219349[69:Res:53.1,219346.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.42 219351[69:MRR:219349.0,219124.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 219356[69:Res:219351.0,61.1] always3(s40) || -> . % 76.30/76.42 219357[69:SSi:219356.0,78245.0,78249.0,217610.0] || -> . % 76.30/76.42 219358[67:Spt:219357.0,219071.0,219074.0] || trans(s49,s39)*+ -> . % 76.30/76.42 219359[67:Spt:219357.0,219071.1,219071.2,219071.3,219071.4,219071.5,219071.6,219071.7,219071.8,219071.9,219071.10,219071.11,219071.12,219071.13,219071.14,219071.15,219071.16,219071.17,219071.18,219071.19,219071.20,219071.21,219071.22,219071.23,219071.24,219071.25,219071.26,219071.27,219071.28,219071.29,219071.30,219071.31,219071.32] || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.42 219361[67:MRR:219073.1,219358.0] xuntil6(s49) || -> trans(s49,s38) trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.42 219362[68:Spt:219359.0] || -> trans(s49,s38)*. % 76.30/76.42 219363[68:Res:219362.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s38)*. % 76.30/76.42 219365[68:Res:219362.0,60.0] || -> node2(s49,s38)*. % 76.30/76.42 219366[68:SSi:219363.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s38)*. % 76.30/76.42 219367[68:Res:219365.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 219405[68:SoR:219367.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 219407[68:SoR:219405.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s38,c_busy)* xuntil6(s49). % 76.30/76.42 219408[68:SSi:219407.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s38,c_busy)* xuntil6(s49). % 76.30/76.42 219409[69:Spt:219408.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 219411[69:Res:219409.0,61.1] always3(s38) || -> . % 76.30/76.42 219412[69:SSi:219411.0,78236.0,78240.0,217608.0] || -> . % 76.30/76.42 219413[69:Spt:219412.0,219408.1,219409.0] || m_main_v_state(s38,c_busy)*+ -> . % 76.30/76.42 219414[69:Spt:219412.0,219408.0,219408.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.42 219418[69:MRR:219405.2,219413.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.42 219419[69:Res:53.1,219414.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.42 219421[69:MRR:219419.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.42 219422[69:MRR:219366.0,219421.0] || -> until2p7(s38)*. % 76.30/76.42 219423[69:MRR:236.0,219422.0] || -> until2p7(s39)* node4(s38). % 76.30/76.42 219424[70:Spt:219423.0] || -> until2p7(s39)*. % 76.30/76.42 219425[70:MRR:237.0,219424.0] || -> until2p7(s40)* node4(s39). % 76.30/76.42 219426[71:Spt:219425.0] || -> until2p7(s40)*. % 76.30/76.42 219427[71:MRR:238.0,219426.0] || -> until2p7(s41)* node4(s40). % 76.30/76.42 219428[72:Spt:219427.0] || -> until2p7(s41)*. % 76.30/76.42 219429[72:MRR:239.0,219428.0] || -> until2p7(s42)* node4(s41). % 76.30/76.42 219430[73:Spt:219429.0] || -> until2p7(s42)*. % 76.30/76.42 219431[73:MRR:240.0,219430.0] || -> until2p7(s43)* node4(s42). % 76.30/76.42 219432[74:Spt:219431.0] || -> until2p7(s43)*. % 76.30/76.42 219433[74:MRR:241.0,219432.0] || -> until2p7(s44)* node4(s43). % 76.30/76.42 219434[75:Spt:219433.0] || -> until2p7(s44)*. % 76.30/76.42 219435[75:MRR:539.0,219434.0] || -> until2p7(s45)* node4(s44). % 76.30/76.42 219436[76:Spt:219435.0] || -> until2p7(s45)*. % 76.30/76.42 219437[76:MRR:544.0,219436.0] || -> until2p7(s46)* node4(s45). % 76.30/76.42 219438[77:Spt:219437.0] || -> until2p7(s46)*. % 76.30/76.42 219439[77:MRR:549.0,219438.0] || -> until2p7(s47)* node4(s46). % 76.30/76.42 219440[78:Spt:219439.0] || -> until2p7(s47)*. % 76.30/76.42 219441[78:MRR:554.0,219440.0] || -> until2p7(s48)* node4(s47). % 76.30/76.42 219442[79:Spt:219441.0] || -> until2p7(s48)*. % 76.30/76.42 219443[79:MRR:559.0,219442.0] || -> until2p7(s49)* node4(s48). % 76.30/76.42 219444[80:Spt:219443.0] || -> until2p7(s49)*. % 76.30/76.42 219445[80:MRR:194.0,219444.0] || -> node4(s49)*. % 76.30/76.42 219446[80:MRR:219418.0,219445.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.42 219450[80:Res:53.1,219446.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.42 219452[80:MRR:219450.0,78381.0] || -> . % 76.30/76.42 219453[80:Spt:219452.0,219443.0,219444.0] || until2p7(s49)*+ -> . % 76.30/76.42 219454[80:Spt:219452.0,219443.1] || -> node4(s48)*. % 76.30/76.42 219455[80:MRR:78384.0,219454.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.42 219458[80:Res:53.1,219455.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 219461[80:Res:219458.0,61.1] always3(s48) || -> . % 76.30/76.42 219462[80:SSi:219461.0,78281.0,78387.0,217618.0,219442.0,219454.0] || -> . % 76.30/76.42 219463[79:Spt:219462.0,219441.0,219442.0] || until2p7(s48)*+ -> . % 76.30/76.42 219464[79:Spt:219462.0,219441.1] || -> node4(s47)*. % 76.30/76.42 219466[79:MRR:777.0,219464.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.42 219478[79:Res:53.1,219466.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.42 219480[80:Spt:219478.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 219482[80:Res:219480.0,61.1] always3(s47) || -> . % 76.30/76.42 219483[80:SSi:219482.0,78277.0,78280.0,217617.0,219440.0,219464.0] || -> . % 76.30/76.42 219484[80:Spt:219483.0,219478.0,219480.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.42 219485[80:Spt:219483.0,219478.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 219489[80:Res:219485.0,61.1] always3(s48) || -> . % 76.30/76.42 219490[80:SSi:219489.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.42 219491[78:Spt:219490.0,219439.0,219440.0] || until2p7(s47)*+ -> . % 76.30/76.42 219492[78:Spt:219490.0,219439.1] || -> node4(s46)*. % 76.30/76.42 219494[78:MRR:780.0,219492.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.42 219501[78:Res:53.1,219494.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.42 219506[79:Spt:219501.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 219508[79:Res:219506.0,61.1] always3(s46) || -> . % 76.30/76.42 219509[79:SSi:219508.0,78272.0,78276.0,217616.0,219438.0,219492.0] || -> . % 76.30/76.42 219510[79:Spt:219509.0,219501.0,219506.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.42 219511[79:Spt:219509.0,219501.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 219515[79:Res:219511.0,61.1] always3(s47) || -> . % 76.30/76.42 219516[79:SSi:219515.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.42 219517[77:Spt:219516.0,219437.0,219438.0] || until2p7(s46)*+ -> . % 76.30/76.42 219518[77:Spt:219516.0,219437.1] || -> node4(s45)*. % 76.30/76.42 219520[77:MRR:783.0,219518.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.42 219523[77:Res:53.1,219520.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.42 219525[78:Spt:219523.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 219527[78:Res:219525.0,61.1] always3(s45) || -> . % 76.30/76.42 219528[78:SSi:219527.0,78268.0,78271.0,217615.0,219436.0,219518.0] || -> . % 76.30/76.42 219529[78:Spt:219528.0,219523.0,219525.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.42 219530[78:Spt:219528.0,219523.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 219534[78:Res:219530.0,61.1] always3(s46) || -> . % 76.30/76.42 219535[78:SSi:219534.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.42 219536[76:Spt:219535.0,219435.0,219436.0] || until2p7(s45)*+ -> . % 76.30/76.42 219537[76:Spt:219535.0,219435.1] || -> node4(s44)*. % 76.30/76.42 219539[76:MRR:786.0,219537.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.42 219542[76:Res:53.1,219539.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.42 219544[77:Spt:219542.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 219546[77:Res:219544.0,61.1] always3(s44) || -> . % 76.30/76.42 219547[77:SSi:219546.0,78263.0,78267.0,217614.0,219434.0,219537.0] || -> . % 76.30/76.42 219548[77:Spt:219547.0,219542.0,219544.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.42 219549[77:Spt:219547.0,219542.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 219553[77:Res:219549.0,61.1] always3(s45) || -> . % 76.30/76.42 219554[77:SSi:219553.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.42 219555[75:Spt:219554.0,219433.0,219434.0] || until2p7(s44)*+ -> . % 76.30/76.42 219556[75:Spt:219554.0,219433.1] || -> node4(s43)*. % 76.30/76.42 219558[75:MRR:789.0,219556.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.42 219561[75:Res:53.1,219558.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.42 219563[76:Spt:219561.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 219565[76:Res:219563.0,61.1] always3(s43) || -> . % 76.30/76.42 219566[76:SSi:219565.0,78259.0,78262.0,217613.0,219432.0,219556.0] || -> . % 76.30/76.42 219567[76:Spt:219566.0,219561.0,219563.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.42 219568[76:Spt:219566.0,219561.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 219572[76:Res:219568.0,61.1] always3(s44) || -> . % 76.30/76.42 219573[76:SSi:219572.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.42 219574[74:Spt:219573.0,219431.0,219432.0] || until2p7(s43)*+ -> . % 76.30/76.42 219575[74:Spt:219573.0,219431.1] || -> node4(s42)*. % 76.30/76.42 219577[74:MRR:792.0,219575.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.42 219580[74:Res:53.1,219577.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.42 219585[75:Spt:219580.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 219587[75:Res:219585.0,61.1] always3(s42) || -> . % 76.30/76.42 219588[75:SSi:219587.0,78254.0,78258.0,217612.0,219430.0,219575.0] || -> . % 76.30/76.42 219589[75:Spt:219588.0,219580.0,219585.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.42 219590[75:Spt:219588.0,219580.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 219594[75:Res:219590.0,61.1] always3(s43) || -> . % 76.30/76.42 219595[75:SSi:219594.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.42 219596[73:Spt:219595.0,219429.0,219430.0] || until2p7(s42)*+ -> . % 76.30/76.42 219597[73:Spt:219595.0,219429.1] || -> node4(s41)*. % 76.30/76.42 219599[73:MRR:795.0,219597.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.42 219602[73:Res:53.1,219599.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.42 219604[74:Spt:219602.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 219606[74:Res:219604.0,61.1] always3(s41) || -> . % 76.30/76.42 219607[74:SSi:219606.0,78250.0,78253.0,217611.0,219428.0,219597.0] || -> . % 76.30/76.42 219608[74:Spt:219607.0,219602.0,219604.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.42 219609[74:Spt:219607.0,219602.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 219613[74:Res:219609.0,61.1] always3(s42) || -> . % 76.30/76.42 219614[74:SSi:219613.0,78254.0,78258.0,217612.0] || -> . % 76.30/76.42 219615[72:Spt:219614.0,219427.0,219428.0] || until2p7(s41)*+ -> . % 76.30/76.42 219616[72:Spt:219614.0,219427.1] || -> node4(s40)*. % 76.30/76.42 219618[72:MRR:798.0,219616.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.42 219621[72:Res:53.1,219618.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.42 219623[73:Spt:219621.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 219625[73:Res:219623.0,61.1] always3(s40) || -> . % 76.30/76.42 219626[73:SSi:219625.0,78245.0,78249.0,217610.0,219426.0,219616.0] || -> . % 76.30/76.42 219627[73:Spt:219626.0,219621.0,219623.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.42 219628[73:Spt:219626.0,219621.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 219632[73:Res:219628.0,61.1] always3(s41) || -> . % 76.30/76.42 219633[73:SSi:219632.0,78250.0,78253.0,217611.0] || -> . % 76.30/76.42 219634[71:Spt:219633.0,219425.0,219426.0] || until2p7(s40)*+ -> . % 76.30/76.42 219635[71:Spt:219633.0,219425.1] || -> node4(s39)*. % 76.30/76.42 219637[71:MRR:801.0,219635.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.42 219640[71:Res:53.1,219637.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.42 219642[72:Spt:219640.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 219644[72:Res:219642.0,61.1] always3(s39) || -> . % 76.30/76.42 219645[72:SSi:219644.0,78241.0,78244.0,217609.0,219424.0,219635.0] || -> . % 76.30/76.42 219646[72:Spt:219645.0,219640.0,219642.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.42 219647[72:Spt:219645.0,219640.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 219651[72:Res:219647.0,61.1] always3(s40) || -> . % 76.30/76.42 219652[72:SSi:219651.0,78245.0,78249.0,217610.0] || -> . % 76.30/76.42 219653[70:Spt:219652.0,219423.0,219424.0] || until2p7(s39)*+ -> . % 76.30/76.42 219654[70:Spt:219652.0,219423.1] || -> node4(s38)*. % 76.30/76.42 219656[70:MRR:804.0,219654.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.42 219659[70:Res:53.1,219656.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.42 219661[70:MRR:219659.0,219413.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 219666[70:Res:219661.0,61.1] always3(s39) || -> . % 76.30/76.42 219667[70:SSi:219666.0,78241.0,78244.0,217609.0] || -> . % 76.30/76.42 219668[68:Spt:219667.0,219359.0,219362.0] || trans(s49,s38)*+ -> . % 76.30/76.42 219669[68:Spt:219667.0,219359.1,219359.2,219359.3,219359.4,219359.5,219359.6,219359.7,219359.8,219359.9,219359.10,219359.11,219359.12,219359.13,219359.14,219359.15,219359.16,219359.17,219359.18,219359.19,219359.20,219359.21,219359.22,219359.23,219359.24,219359.25,219359.26,219359.27,219359.28,219359.29,219359.30,219359.31] || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.42 219671[68:MRR:219361.1,219668.0] xuntil6(s49) || -> trans(s49,s37) trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.42 219672[69:Spt:219669.0] || -> trans(s49,s37)*. % 76.30/76.42 219673[69:Res:219672.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s37)*. % 76.30/76.42 219675[69:Res:219672.0,60.0] || -> node2(s49,s37)*. % 76.30/76.42 219676[69:SSi:219673.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s37)*. % 76.30/76.42 219677[69:Res:219675.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 219719[69:SoR:219677.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 219721[69:SoR:219719.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s37,c_busy)* xuntil6(s49). % 76.30/76.42 219722[69:SSi:219721.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s37,c_busy)* xuntil6(s49). % 76.30/76.42 219723[70:Spt:219722.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 219725[70:Res:219723.0,61.1] always3(s37) || -> . % 76.30/76.42 219726[70:SSi:219725.0,78232.0,78235.0,217607.0] || -> . % 76.30/76.42 219727[70:Spt:219726.0,219722.1,219723.0] || m_main_v_state(s37,c_busy)*+ -> . % 76.30/76.42 219728[70:Spt:219726.0,219722.0,219722.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.42 219732[70:MRR:219719.2,219727.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.42 219733[70:Res:53.1,219728.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.42 219735[70:MRR:219733.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.42 219736[70:MRR:219676.0,219735.0] || -> until2p7(s37)*. % 76.30/76.42 219737[70:MRR:235.0,219736.0] || -> until2p7(s38)* node4(s37). % 76.30/76.42 219738[71:Spt:219737.0] || -> until2p7(s38)*. % 76.30/76.42 219739[71:MRR:236.0,219738.0] || -> until2p7(s39)* node4(s38). % 76.30/76.42 219740[72:Spt:219739.0] || -> until2p7(s39)*. % 76.30/76.42 219741[72:MRR:237.0,219740.0] || -> until2p7(s40)* node4(s39). % 76.30/76.42 219742[73:Spt:219741.0] || -> until2p7(s40)*. % 76.30/76.42 219743[73:MRR:238.0,219742.0] || -> until2p7(s41)* node4(s40). % 76.30/76.42 219744[74:Spt:219743.0] || -> until2p7(s41)*. % 76.30/76.42 219745[74:MRR:239.0,219744.0] || -> until2p7(s42)* node4(s41). % 76.30/76.42 219746[75:Spt:219745.0] || -> until2p7(s42)*. % 76.30/76.42 219747[75:MRR:240.0,219746.0] || -> until2p7(s43)* node4(s42). % 76.30/76.42 219748[76:Spt:219747.0] || -> until2p7(s43)*. % 76.30/76.42 219749[76:MRR:241.0,219748.0] || -> until2p7(s44)* node4(s43). % 76.30/76.42 219750[77:Spt:219749.0] || -> until2p7(s44)*. % 76.30/76.42 219751[77:MRR:539.0,219750.0] || -> until2p7(s45)* node4(s44). % 76.30/76.42 219752[78:Spt:219751.0] || -> until2p7(s45)*. % 76.30/76.42 219753[78:MRR:544.0,219752.0] || -> until2p7(s46)* node4(s45). % 76.30/76.42 219754[79:Spt:219753.0] || -> until2p7(s46)*. % 76.30/76.42 219755[79:MRR:549.0,219754.0] || -> until2p7(s47)* node4(s46). % 76.30/76.42 219756[80:Spt:219755.0] || -> until2p7(s47)*. % 76.30/76.42 219757[80:MRR:554.0,219756.0] || -> until2p7(s48)* node4(s47). % 76.30/76.42 219758[81:Spt:219757.0] || -> until2p7(s48)*. % 76.30/76.42 219759[81:MRR:559.0,219758.0] || -> until2p7(s49)* node4(s48). % 76.30/76.42 219760[82:Spt:219759.0] || -> until2p7(s49)*. % 76.30/76.42 219761[82:MRR:194.0,219760.0] || -> node4(s49)*. % 76.30/76.42 219762[82:MRR:219732.0,219761.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.42 219763[82:Res:53.1,219762.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.42 219765[82:MRR:219763.0,78381.0] || -> . % 76.30/76.42 219766[82:Spt:219765.0,219759.0,219760.0] || until2p7(s49)*+ -> . % 76.30/76.42 219767[82:Spt:219765.0,219759.1] || -> node4(s48)*. % 76.30/76.42 219768[82:MRR:78384.0,219767.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.42 219771[82:Res:53.1,219768.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 219774[82:Res:219771.0,61.1] always3(s48) || -> . % 76.30/76.42 219775[82:SSi:219774.0,78281.0,78387.0,217618.0,219758.0,219767.0] || -> . % 76.30/76.42 219776[81:Spt:219775.0,219757.0,219758.0] || until2p7(s48)*+ -> . % 76.30/76.42 219777[81:Spt:219775.0,219757.1] || -> node4(s47)*. % 76.30/76.42 219779[81:MRR:777.0,219777.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.42 219794[81:Res:53.1,219779.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.42 219799[82:Spt:219794.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 219801[82:Res:219799.0,61.1] always3(s47) || -> . % 76.30/76.42 219802[82:SSi:219801.0,78277.0,78280.0,217617.0,219756.0,219777.0] || -> . % 76.30/76.42 219803[82:Spt:219802.0,219794.0,219799.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.42 219804[82:Spt:219802.0,219794.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 219808[82:Res:219804.0,61.1] always3(s48) || -> . % 76.30/76.42 219809[82:SSi:219808.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.42 219810[80:Spt:219809.0,219755.0,219756.0] || until2p7(s47)*+ -> . % 76.30/76.42 219811[80:Spt:219809.0,219755.1] || -> node4(s46)*. % 76.30/76.42 219813[80:MRR:780.0,219811.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.42 219820[80:Res:53.1,219813.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.42 219822[81:Spt:219820.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 219824[81:Res:219822.0,61.1] always3(s46) || -> . % 76.30/76.42 219825[81:SSi:219824.0,78272.0,78276.0,217616.0,219754.0,219811.0] || -> . % 76.30/76.42 219826[81:Spt:219825.0,219820.0,219822.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.42 219827[81:Spt:219825.0,219820.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 219831[81:Res:219827.0,61.1] always3(s47) || -> . % 76.30/76.42 219832[81:SSi:219831.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.42 219833[79:Spt:219832.0,219753.0,219754.0] || until2p7(s46)*+ -> . % 76.30/76.42 219834[79:Spt:219832.0,219753.1] || -> node4(s45)*. % 76.30/76.42 219836[79:MRR:783.0,219834.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.42 219839[79:Res:53.1,219836.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.42 219844[80:Spt:219839.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 219846[80:Res:219844.0,61.1] always3(s45) || -> . % 76.30/76.42 219847[80:SSi:219846.0,78268.0,78271.0,217615.0,219752.0,219834.0] || -> . % 76.30/76.42 219848[80:Spt:219847.0,219839.0,219844.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.42 219849[80:Spt:219847.0,219839.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 219853[80:Res:219849.0,61.1] always3(s46) || -> . % 76.30/76.42 219854[80:SSi:219853.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.42 219855[78:Spt:219854.0,219751.0,219752.0] || until2p7(s45)*+ -> . % 76.30/76.42 219856[78:Spt:219854.0,219751.1] || -> node4(s44)*. % 76.30/76.42 219858[78:MRR:786.0,219856.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.42 219861[78:Res:53.1,219858.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.42 219863[79:Spt:219861.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 219865[79:Res:219863.0,61.1] always3(s44) || -> . % 76.30/76.42 219866[79:SSi:219865.0,78263.0,78267.0,217614.0,219750.0,219856.0] || -> . % 76.30/76.42 219867[79:Spt:219866.0,219861.0,219863.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.42 219868[79:Spt:219866.0,219861.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 219872[79:Res:219868.0,61.1] always3(s45) || -> . % 76.30/76.42 219873[79:SSi:219872.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.42 219874[77:Spt:219873.0,219749.0,219750.0] || until2p7(s44)*+ -> . % 76.30/76.42 219875[77:Spt:219873.0,219749.1] || -> node4(s43)*. % 76.30/76.42 219877[77:MRR:789.0,219875.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.42 219880[77:Res:53.1,219877.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.42 219882[78:Spt:219880.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 219884[78:Res:219882.0,61.1] always3(s43) || -> . % 76.30/76.42 219885[78:SSi:219884.0,78259.0,78262.0,217613.0,219748.0,219875.0] || -> . % 76.30/76.42 219886[78:Spt:219885.0,219880.0,219882.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.42 219887[78:Spt:219885.0,219880.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 219891[78:Res:219887.0,61.1] always3(s44) || -> . % 76.30/76.42 219892[78:SSi:219891.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.42 219893[76:Spt:219892.0,219747.0,219748.0] || until2p7(s43)*+ -> . % 76.30/76.42 219894[76:Spt:219892.0,219747.1] || -> node4(s42)*. % 76.30/76.42 219896[76:MRR:792.0,219894.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.42 219899[76:Res:53.1,219896.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.42 219901[77:Spt:219899.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 219903[77:Res:219901.0,61.1] always3(s42) || -> . % 76.30/76.42 219904[77:SSi:219903.0,78254.0,78258.0,217612.0,219746.0,219894.0] || -> . % 76.30/76.42 219905[77:Spt:219904.0,219899.0,219901.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.42 219906[77:Spt:219904.0,219899.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 219910[77:Res:219906.0,61.1] always3(s43) || -> . % 76.30/76.42 219911[77:SSi:219910.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.42 219912[75:Spt:219911.0,219745.0,219746.0] || until2p7(s42)*+ -> . % 76.30/76.42 219913[75:Spt:219911.0,219745.1] || -> node4(s41)*. % 76.30/76.42 219915[75:MRR:795.0,219913.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.42 219918[75:Res:53.1,219915.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.42 219923[76:Spt:219918.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 219925[76:Res:219923.0,61.1] always3(s41) || -> . % 76.30/76.42 219926[76:SSi:219925.0,78250.0,78253.0,217611.0,219744.0,219913.0] || -> . % 76.30/76.42 219927[76:Spt:219926.0,219918.0,219923.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.42 219928[76:Spt:219926.0,219918.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 219932[76:Res:219928.0,61.1] always3(s42) || -> . % 76.30/76.42 219933[76:SSi:219932.0,78254.0,78258.0,217612.0] || -> . % 76.30/76.42 219934[74:Spt:219933.0,219743.0,219744.0] || until2p7(s41)*+ -> . % 76.30/76.42 219935[74:Spt:219933.0,219743.1] || -> node4(s40)*. % 76.30/76.42 219937[74:MRR:798.0,219935.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.42 219940[74:Res:53.1,219937.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.42 219942[75:Spt:219940.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 219944[75:Res:219942.0,61.1] always3(s40) || -> . % 76.30/76.42 219945[75:SSi:219944.0,78245.0,78249.0,217610.0,219742.0,219935.0] || -> . % 76.30/76.42 219946[75:Spt:219945.0,219940.0,219942.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.42 219947[75:Spt:219945.0,219940.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 219951[75:Res:219947.0,61.1] always3(s41) || -> . % 76.30/76.42 219952[75:SSi:219951.0,78250.0,78253.0,217611.0] || -> . % 76.30/76.42 219953[73:Spt:219952.0,219741.0,219742.0] || until2p7(s40)*+ -> . % 76.30/76.42 219954[73:Spt:219952.0,219741.1] || -> node4(s39)*. % 76.30/76.42 219956[73:MRR:801.0,219954.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.42 219959[73:Res:53.1,219956.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.42 219961[74:Spt:219959.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 219963[74:Res:219961.0,61.1] always3(s39) || -> . % 76.30/76.42 219964[74:SSi:219963.0,78241.0,78244.0,217609.0,219740.0,219954.0] || -> . % 76.30/76.42 219965[74:Spt:219964.0,219959.0,219961.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.42 219966[74:Spt:219964.0,219959.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 219970[74:Res:219966.0,61.1] always3(s40) || -> . % 76.30/76.42 219971[74:SSi:219970.0,78245.0,78249.0,217610.0] || -> . % 76.30/76.42 219972[72:Spt:219971.0,219739.0,219740.0] || until2p7(s39)*+ -> . % 76.30/76.42 219973[72:Spt:219971.0,219739.1] || -> node4(s38)*. % 76.30/76.42 219975[72:MRR:804.0,219973.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.42 219978[72:Res:53.1,219975.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.42 219980[73:Spt:219978.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 219982[73:Res:219980.0,61.1] always3(s38) || -> . % 76.30/76.42 219983[73:SSi:219982.0,78236.0,78240.0,217608.0,219738.0,219973.0] || -> . % 76.30/76.42 219984[73:Spt:219983.0,219978.0,219980.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.42 219985[73:Spt:219983.0,219978.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 219989[73:Res:219985.0,61.1] always3(s39) || -> . % 76.30/76.42 219990[73:SSi:219989.0,78241.0,78244.0,217609.0] || -> . % 76.30/76.42 219991[71:Spt:219990.0,219737.0,219738.0] || until2p7(s38)*+ -> . % 76.30/76.42 219992[71:Spt:219990.0,219737.1] || -> node4(s37)*. % 76.30/76.42 219994[71:MRR:807.0,219992.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.42 219997[71:Res:53.1,219994.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.42 219999[71:MRR:219997.0,219727.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 220004[71:Res:219999.0,61.1] always3(s38) || -> . % 76.30/76.42 220005[71:SSi:220004.0,78236.0,78240.0,217608.0] || -> . % 76.30/76.42 220006[69:Spt:220005.0,219669.0,219672.0] || trans(s49,s37)*+ -> . % 76.30/76.42 220007[69:Spt:220005.0,219669.1,219669.2,219669.3,219669.4,219669.5,219669.6,219669.7,219669.8,219669.9,219669.10,219669.11,219669.12,219669.13,219669.14,219669.15,219669.16,219669.17,219669.18,219669.19,219669.20,219669.21,219669.22,219669.23,219669.24,219669.25,219669.26,219669.27,219669.28,219669.29,219669.30] || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.42 220009[69:MRR:219671.1,220006.0] xuntil6(s49) || -> trans(s49,s36) trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.42 220010[70:Spt:220007.0] || -> trans(s49,s36)*. % 76.30/76.42 220011[70:Res:220010.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s36)*. % 76.30/76.42 220013[70:Res:220010.0,60.0] || -> node2(s49,s36)*. % 76.30/76.42 220014[70:SSi:220011.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s36)*. % 76.30/76.42 220015[70:Res:220013.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 220058[70:SoR:220015.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 220060[70:SoR:220058.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s36,c_busy)* xuntil6(s49). % 76.30/76.42 220061[70:SSi:220060.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s36,c_busy)* xuntil6(s49). % 76.30/76.42 220062[71:Spt:220061.1] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 220064[71:Res:220062.0,61.1] always3(s36) || -> . % 76.30/76.42 220065[71:SSi:220064.0,78227.0,78231.0,217606.0] || -> . % 76.30/76.42 220066[71:Spt:220065.0,220061.1,220062.0] || m_main_v_state(s36,c_busy)*+ -> . % 76.30/76.42 220067[71:Spt:220065.0,220061.0,220061.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.42 220071[71:MRR:220058.2,220066.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.42 220072[71:Res:53.1,220067.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.42 220074[71:MRR:220072.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.42 220075[71:MRR:220014.0,220074.0] || -> until2p7(s36)*. % 76.30/76.42 220076[71:MRR:232.0,220075.0] || -> until2p7(s37)* node4(s36). % 76.30/76.42 220077[72:Spt:220076.0] || -> until2p7(s37)*. % 76.30/76.42 220078[72:MRR:235.0,220077.0] || -> until2p7(s38)* node4(s37). % 76.30/76.42 220079[73:Spt:220078.0] || -> until2p7(s38)*. % 76.30/76.42 220080[73:MRR:236.0,220079.0] || -> until2p7(s39)* node4(s38). % 76.30/76.42 220081[74:Spt:220080.0] || -> until2p7(s39)*. % 76.30/76.42 220082[74:MRR:237.0,220081.0] || -> until2p7(s40)* node4(s39). % 76.30/76.42 220083[75:Spt:220082.0] || -> until2p7(s40)*. % 76.30/76.42 220084[75:MRR:238.0,220083.0] || -> until2p7(s41)* node4(s40). % 76.30/76.42 220085[76:Spt:220084.0] || -> until2p7(s41)*. % 76.30/76.42 220086[76:MRR:239.0,220085.0] || -> until2p7(s42)* node4(s41). % 76.30/76.42 220087[77:Spt:220086.0] || -> until2p7(s42)*. % 76.30/76.42 220088[77:MRR:240.0,220087.0] || -> until2p7(s43)* node4(s42). % 76.30/76.42 220089[78:Spt:220088.0] || -> until2p7(s43)*. % 76.30/76.42 220090[78:MRR:241.0,220089.0] || -> until2p7(s44)* node4(s43). % 76.30/76.42 220091[79:Spt:220090.0] || -> until2p7(s44)*. % 76.30/76.42 220092[79:MRR:539.0,220091.0] || -> until2p7(s45)* node4(s44). % 76.30/76.42 220093[80:Spt:220092.0] || -> until2p7(s45)*. % 76.30/76.42 220094[80:MRR:544.0,220093.0] || -> until2p7(s46)* node4(s45). % 76.30/76.42 220095[81:Spt:220094.0] || -> until2p7(s46)*. % 76.30/76.42 220096[81:MRR:549.0,220095.0] || -> until2p7(s47)* node4(s46). % 76.30/76.42 220097[82:Spt:220096.0] || -> until2p7(s47)*. % 76.30/76.42 220098[82:MRR:554.0,220097.0] || -> until2p7(s48)* node4(s47). % 76.30/76.42 220099[83:Spt:220098.0] || -> until2p7(s48)*. % 76.30/76.42 220100[83:MRR:559.0,220099.0] || -> until2p7(s49)* node4(s48). % 76.30/76.42 220101[84:Spt:220100.0] || -> until2p7(s49)*. % 76.30/76.42 220102[84:MRR:194.0,220101.0] || -> node4(s49)*. % 76.30/76.42 220103[84:MRR:220071.0,220102.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.42 220107[84:Res:53.1,220103.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.42 220109[84:MRR:220107.0,78381.0] || -> . % 76.30/76.42 220110[84:Spt:220109.0,220100.0,220101.0] || until2p7(s49)*+ -> . % 76.30/76.42 220111[84:Spt:220109.0,220100.1] || -> node4(s48)*. % 76.30/76.42 220112[84:MRR:78384.0,220111.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.42 220115[84:Res:53.1,220112.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 220118[84:Res:220115.0,61.1] always3(s48) || -> . % 76.30/76.42 220119[84:SSi:220118.0,78281.0,78387.0,217618.0,220099.0,220111.0] || -> . % 76.30/76.42 220120[83:Spt:220119.0,220098.0,220099.0] || until2p7(s48)*+ -> . % 76.30/76.42 220121[83:Spt:220119.0,220098.1] || -> node4(s47)*. % 76.30/76.42 220123[83:MRR:777.0,220121.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.42 220135[83:Res:53.1,220123.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.42 220137[84:Spt:220135.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 220139[84:Res:220137.0,61.1] always3(s47) || -> . % 76.30/76.42 220140[84:SSi:220139.0,78277.0,78280.0,217617.0,220097.0,220121.0] || -> . % 76.30/76.42 220141[84:Spt:220140.0,220135.0,220137.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.42 220142[84:Spt:220140.0,220135.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 220146[84:Res:220142.0,61.1] always3(s48) || -> . % 76.30/76.42 220147[84:SSi:220146.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.42 220148[82:Spt:220147.0,220096.0,220097.0] || until2p7(s47)*+ -> . % 76.30/76.42 220149[82:Spt:220147.0,220096.1] || -> node4(s46)*. % 76.30/76.42 220151[82:MRR:780.0,220149.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.42 220158[82:Res:53.1,220151.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.42 220163[83:Spt:220158.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 220165[83:Res:220163.0,61.1] always3(s46) || -> . % 76.30/76.42 220166[83:SSi:220165.0,78272.0,78276.0,217616.0,220095.0,220149.0] || -> . % 76.30/76.42 220167[83:Spt:220166.0,220158.0,220163.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.42 220168[83:Spt:220166.0,220158.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 220172[83:Res:220168.0,61.1] always3(s47) || -> . % 76.30/76.42 220173[83:SSi:220172.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.42 220174[81:Spt:220173.0,220094.0,220095.0] || until2p7(s46)*+ -> . % 76.30/76.42 220175[81:Spt:220173.0,220094.1] || -> node4(s45)*. % 76.30/76.42 220177[81:MRR:783.0,220175.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.42 220180[81:Res:53.1,220177.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.42 220182[82:Spt:220180.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 220184[82:Res:220182.0,61.1] always3(s45) || -> . % 76.30/76.42 220185[82:SSi:220184.0,78268.0,78271.0,217615.0,220093.0,220175.0] || -> . % 76.30/76.42 220186[82:Spt:220185.0,220180.0,220182.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.42 220187[82:Spt:220185.0,220180.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 220191[82:Res:220187.0,61.1] always3(s46) || -> . % 76.30/76.42 220192[82:SSi:220191.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.42 220193[80:Spt:220192.0,220092.0,220093.0] || until2p7(s45)*+ -> . % 76.30/76.42 220194[80:Spt:220192.0,220092.1] || -> node4(s44)*. % 76.30/76.42 220196[80:MRR:786.0,220194.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.42 220199[80:Res:53.1,220196.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.42 220201[81:Spt:220199.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 220203[81:Res:220201.0,61.1] always3(s44) || -> . % 76.30/76.42 220204[81:SSi:220203.0,78263.0,78267.0,217614.0,220091.0,220194.0] || -> . % 76.30/76.42 220205[81:Spt:220204.0,220199.0,220201.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.42 220206[81:Spt:220204.0,220199.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 220210[81:Res:220206.0,61.1] always3(s45) || -> . % 76.30/76.42 220211[81:SSi:220210.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.42 220212[79:Spt:220211.0,220090.0,220091.0] || until2p7(s44)*+ -> . % 76.30/76.42 220213[79:Spt:220211.0,220090.1] || -> node4(s43)*. % 76.30/76.42 220215[79:MRR:789.0,220213.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.42 220218[79:Res:53.1,220215.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.42 220220[80:Spt:220218.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 220222[80:Res:220220.0,61.1] always3(s43) || -> . % 76.30/76.42 220223[80:SSi:220222.0,78259.0,78262.0,217613.0,220089.0,220213.0] || -> . % 76.30/76.42 220224[80:Spt:220223.0,220218.0,220220.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.42 220225[80:Spt:220223.0,220218.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 220229[80:Res:220225.0,61.1] always3(s44) || -> . % 76.30/76.42 220230[80:SSi:220229.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.42 220231[78:Spt:220230.0,220088.0,220089.0] || until2p7(s43)*+ -> . % 76.30/76.42 220232[78:Spt:220230.0,220088.1] || -> node4(s42)*. % 76.30/76.42 220234[78:MRR:792.0,220232.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.42 220237[78:Res:53.1,220234.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.42 220242[79:Spt:220237.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 220244[79:Res:220242.0,61.1] always3(s42) || -> . % 76.30/76.42 220245[79:SSi:220244.0,78254.0,78258.0,217612.0,220087.0,220232.0] || -> . % 76.30/76.42 220246[79:Spt:220245.0,220237.0,220242.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.42 220247[79:Spt:220245.0,220237.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 220251[79:Res:220247.0,61.1] always3(s43) || -> . % 76.30/76.42 220252[79:SSi:220251.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.42 220253[77:Spt:220252.0,220086.0,220087.0] || until2p7(s42)*+ -> . % 76.30/76.42 220254[77:Spt:220252.0,220086.1] || -> node4(s41)*. % 76.30/76.42 220256[77:MRR:795.0,220254.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.42 220259[77:Res:53.1,220256.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.42 220261[78:Spt:220259.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 220263[78:Res:220261.0,61.1] always3(s41) || -> . % 76.30/76.42 220264[78:SSi:220263.0,78250.0,78253.0,217611.0,220085.0,220254.0] || -> . % 76.30/76.42 220265[78:Spt:220264.0,220259.0,220261.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.42 220266[78:Spt:220264.0,220259.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 220270[78:Res:220266.0,61.1] always3(s42) || -> . % 76.30/76.42 220271[78:SSi:220270.0,78254.0,78258.0,217612.0] || -> . % 76.30/76.42 220272[76:Spt:220271.0,220084.0,220085.0] || until2p7(s41)*+ -> . % 76.30/76.42 220273[76:Spt:220271.0,220084.1] || -> node4(s40)*. % 76.30/76.42 220275[76:MRR:798.0,220273.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.42 220278[76:Res:53.1,220275.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.42 220280[77:Spt:220278.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 220282[77:Res:220280.0,61.1] always3(s40) || -> . % 76.30/76.42 220283[77:SSi:220282.0,78245.0,78249.0,217610.0,220083.0,220273.0] || -> . % 76.30/76.42 220284[77:Spt:220283.0,220278.0,220280.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.42 220285[77:Spt:220283.0,220278.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 220289[77:Res:220285.0,61.1] always3(s41) || -> . % 76.30/76.42 220290[77:SSi:220289.0,78250.0,78253.0,217611.0] || -> . % 76.30/76.42 220291[75:Spt:220290.0,220082.0,220083.0] || until2p7(s40)*+ -> . % 76.30/76.42 220292[75:Spt:220290.0,220082.1] || -> node4(s39)*. % 76.30/76.42 220294[75:MRR:801.0,220292.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.42 220297[75:Res:53.1,220294.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.42 220299[76:Spt:220297.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 220301[76:Res:220299.0,61.1] always3(s39) || -> . % 76.30/76.42 220302[76:SSi:220301.0,78241.0,78244.0,217609.0,220081.0,220292.0] || -> . % 76.30/76.42 220303[76:Spt:220302.0,220297.0,220299.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.42 220304[76:Spt:220302.0,220297.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 220308[76:Res:220304.0,61.1] always3(s40) || -> . % 76.30/76.42 220309[76:SSi:220308.0,78245.0,78249.0,217610.0] || -> . % 76.30/76.42 220310[74:Spt:220309.0,220080.0,220081.0] || until2p7(s39)*+ -> . % 76.30/76.42 220311[74:Spt:220309.0,220080.1] || -> node4(s38)*. % 76.30/76.42 220313[74:MRR:804.0,220311.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.42 220316[74:Res:53.1,220313.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.42 220321[75:Spt:220316.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 220323[75:Res:220321.0,61.1] always3(s38) || -> . % 76.30/76.42 220324[75:SSi:220323.0,78236.0,78240.0,217608.0,220079.0,220311.0] || -> . % 76.30/76.42 220325[75:Spt:220324.0,220316.0,220321.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.42 220326[75:Spt:220324.0,220316.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 220330[75:Res:220326.0,61.1] always3(s39) || -> . % 76.30/76.42 220331[75:SSi:220330.0,78241.0,78244.0,217609.0] || -> . % 76.30/76.42 220332[73:Spt:220331.0,220078.0,220079.0] || until2p7(s38)*+ -> . % 76.30/76.42 220333[73:Spt:220331.0,220078.1] || -> node4(s37)*. % 76.30/76.42 220335[73:MRR:807.0,220333.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.42 220338[73:Res:53.1,220335.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.42 220340[74:Spt:220338.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 220342[74:Res:220340.0,61.1] always3(s37) || -> . % 76.30/76.42 220343[74:SSi:220342.0,78232.0,78235.0,217607.0,220077.0,220333.0] || -> . % 76.30/76.42 220344[74:Spt:220343.0,220338.0,220340.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.42 220345[74:Spt:220343.0,220338.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 220349[74:Res:220345.0,61.1] always3(s38) || -> . % 76.30/76.42 220350[74:SSi:220349.0,78236.0,78240.0,217608.0] || -> . % 76.30/76.42 220351[72:Spt:220350.0,220076.0,220077.0] || until2p7(s37)*+ -> . % 76.30/76.42 220352[72:Spt:220350.0,220076.1] || -> node4(s36)*. % 76.30/76.42 220354[72:MRR:810.0,220352.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.42 220357[72:Res:53.1,220354.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.42 220359[72:MRR:220357.0,220066.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 220361[72:Res:220359.0,61.1] always3(s37) || -> . % 76.30/76.42 220362[72:SSi:220361.0,78232.0,78235.0,217607.0] || -> . % 76.30/76.42 220363[70:Spt:220362.0,220007.0,220010.0] || trans(s49,s36)*+ -> . % 76.30/76.42 220364[70:Spt:220362.0,220007.1,220007.2,220007.3,220007.4,220007.5,220007.6,220007.7,220007.8,220007.9,220007.10,220007.11,220007.12,220007.13,220007.14,220007.15,220007.16,220007.17,220007.18,220007.19,220007.20,220007.21,220007.22,220007.23,220007.24,220007.25,220007.26,220007.27,220007.28,220007.29] || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.42 220366[70:MRR:220009.1,220363.0] xuntil6(s49) || -> trans(s49,s35) trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.42 220367[71:Spt:220364.0] || -> trans(s49,s35)*. % 76.30/76.42 220368[71:Res:220367.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s35)*. % 76.30/76.42 220370[71:Res:220367.0,60.0] || -> node2(s49,s35)*. % 76.30/76.42 220371[71:SSi:220368.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s35)*. % 76.30/76.42 220372[71:Res:220370.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 76.30/76.42 220422[71:SoR:220372.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)*. % 76.30/76.42 220424[71:SoR:220422.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 76.30/76.42 220425[71:SSi:220424.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s35,c_busy)* xuntil6(s49). % 76.30/76.42 220426[72:Spt:220425.1] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.42 220428[72:Res:220426.0,61.1] always3(s35) || -> . % 76.30/76.42 220429[72:SSi:220428.0,78223.0,78226.0,217605.0] || -> . % 76.30/76.42 220430[72:Spt:220429.0,220425.1,220426.0] || m_main_v_state(s35,c_busy)*+ -> . % 76.30/76.42 220431[72:Spt:220429.0,220425.0,220425.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.42 220435[72:MRR:220422.2,220430.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.42 220436[72:Res:53.1,220431.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.42 220438[72:MRR:220436.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.42 220439[72:MRR:220371.0,220438.0] || -> until2p7(s35)*. % 76.30/76.42 220440[72:MRR:231.0,220439.0] || -> until2p7(s36)* node4(s35). % 76.30/76.42 220441[73:Spt:220440.0] || -> until2p7(s36)*. % 76.30/76.42 220442[73:MRR:232.0,220441.0] || -> until2p7(s37)* node4(s36). % 76.30/76.42 220443[74:Spt:220442.0] || -> until2p7(s37)*. % 76.30/76.42 220444[74:MRR:235.0,220443.0] || -> until2p7(s38)* node4(s37). % 76.30/76.42 220445[75:Spt:220444.0] || -> until2p7(s38)*. % 76.30/76.42 220446[75:MRR:236.0,220445.0] || -> until2p7(s39)* node4(s38). % 76.30/76.42 220447[76:Spt:220446.0] || -> until2p7(s39)*. % 76.30/76.42 220448[76:MRR:237.0,220447.0] || -> until2p7(s40)* node4(s39). % 76.30/76.42 220449[77:Spt:220448.0] || -> until2p7(s40)*. % 76.30/76.42 220450[77:MRR:238.0,220449.0] || -> until2p7(s41)* node4(s40). % 76.30/76.42 220451[78:Spt:220450.0] || -> until2p7(s41)*. % 76.30/76.42 220452[78:MRR:239.0,220451.0] || -> until2p7(s42)* node4(s41). % 76.30/76.42 220453[79:Spt:220452.0] || -> until2p7(s42)*. % 76.30/76.42 220454[79:MRR:240.0,220453.0] || -> until2p7(s43)* node4(s42). % 76.30/76.42 220455[80:Spt:220454.0] || -> until2p7(s43)*. % 76.30/76.42 220456[80:MRR:241.0,220455.0] || -> until2p7(s44)* node4(s43). % 76.30/76.42 220457[81:Spt:220456.0] || -> until2p7(s44)*. % 76.30/76.42 220458[81:MRR:539.0,220457.0] || -> until2p7(s45)* node4(s44). % 76.30/76.42 220459[82:Spt:220458.0] || -> until2p7(s45)*. % 76.30/76.42 220460[82:MRR:544.0,220459.0] || -> until2p7(s46)* node4(s45). % 76.30/76.42 220461[83:Spt:220460.0] || -> until2p7(s46)*. % 76.30/76.42 220462[83:MRR:549.0,220461.0] || -> until2p7(s47)* node4(s46). % 76.30/76.42 220463[84:Spt:220462.0] || -> until2p7(s47)*. % 76.30/76.42 220464[84:MRR:554.0,220463.0] || -> until2p7(s48)* node4(s47). % 76.30/76.42 220465[85:Spt:220464.0] || -> until2p7(s48)*. % 76.30/76.42 220466[85:MRR:559.0,220465.0] || -> until2p7(s49)* node4(s48). % 76.30/76.42 220467[86:Spt:220466.0] || -> until2p7(s49)*. % 76.30/76.42 220468[86:MRR:194.0,220467.0] || -> node4(s49)*. % 76.30/76.42 220469[86:MRR:220435.0,220468.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.42 220470[86:Res:53.1,220469.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.42 220472[86:MRR:220470.0,78381.0] || -> . % 76.30/76.42 220473[86:Spt:220472.0,220466.0,220467.0] || until2p7(s49)*+ -> . % 76.30/76.42 220474[86:Spt:220472.0,220466.1] || -> node4(s48)*. % 76.30/76.42 220475[86:MRR:78384.0,220474.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.42 220478[86:Res:53.1,220475.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 220481[86:Res:220478.0,61.1] always3(s48) || -> . % 76.30/76.42 220482[86:SSi:220481.0,78281.0,78387.0,217618.0,220465.0,220474.0] || -> . % 76.30/76.42 220483[85:Spt:220482.0,220464.0,220465.0] || until2p7(s48)*+ -> . % 76.30/76.42 220484[85:Spt:220482.0,220464.1] || -> node4(s47)*. % 76.30/76.42 220486[85:MRR:777.0,220484.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.42 220501[85:Res:53.1,220486.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.42 220503[86:Spt:220501.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 220505[86:Res:220503.0,61.1] always3(s47) || -> . % 76.30/76.42 220506[86:SSi:220505.0,78277.0,78280.0,217617.0,220463.0,220484.0] || -> . % 76.30/76.42 220507[86:Spt:220506.0,220501.0,220503.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.42 220508[86:Spt:220506.0,220501.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 220512[86:Res:220508.0,61.1] always3(s48) || -> . % 76.30/76.42 220513[86:SSi:220512.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.42 220514[84:Spt:220513.0,220462.0,220463.0] || until2p7(s47)*+ -> . % 76.30/76.42 220515[84:Spt:220513.0,220462.1] || -> node4(s46)*. % 76.30/76.42 220517[84:MRR:780.0,220515.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.42 220527[84:Res:53.1,220517.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.42 220529[85:Spt:220527.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 220531[85:Res:220529.0,61.1] always3(s46) || -> . % 76.30/76.42 220532[85:SSi:220531.0,78272.0,78276.0,217616.0,220461.0,220515.0] || -> . % 76.30/76.42 220533[85:Spt:220532.0,220527.0,220529.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.42 220534[85:Spt:220532.0,220527.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 220538[85:Res:220534.0,61.1] always3(s47) || -> . % 76.30/76.42 220539[85:SSi:220538.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.42 220540[83:Spt:220539.0,220460.0,220461.0] || until2p7(s46)*+ -> . % 76.30/76.42 220541[83:Spt:220539.0,220460.1] || -> node4(s45)*. % 76.30/76.42 220543[83:MRR:783.0,220541.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.42 220546[83:Res:53.1,220543.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.42 220548[84:Spt:220546.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 220550[84:Res:220548.0,61.1] always3(s45) || -> . % 76.30/76.42 220551[84:SSi:220550.0,78268.0,78271.0,217615.0,220459.0,220541.0] || -> . % 76.30/76.42 220552[84:Spt:220551.0,220546.0,220548.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.42 220553[84:Spt:220551.0,220546.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 220557[84:Res:220553.0,61.1] always3(s46) || -> . % 76.30/76.42 220558[84:SSi:220557.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.42 220559[82:Spt:220558.0,220458.0,220459.0] || until2p7(s45)*+ -> . % 76.30/76.42 220560[82:Spt:220558.0,220458.1] || -> node4(s44)*. % 76.30/76.42 220562[82:MRR:786.0,220560.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.42 220565[82:Res:53.1,220562.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.42 220567[83:Spt:220565.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 220569[83:Res:220567.0,61.1] always3(s44) || -> . % 76.30/76.42 220570[83:SSi:220569.0,78263.0,78267.0,217614.0,220457.0,220560.0] || -> . % 76.30/76.42 220571[83:Spt:220570.0,220565.0,220567.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.42 220572[83:Spt:220570.0,220565.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 220576[83:Res:220572.0,61.1] always3(s45) || -> . % 76.30/76.42 220577[83:SSi:220576.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.42 220578[81:Spt:220577.0,220456.0,220457.0] || until2p7(s44)*+ -> . % 76.30/76.42 220579[81:Spt:220577.0,220456.1] || -> node4(s43)*. % 76.30/76.42 220581[81:MRR:789.0,220579.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.42 220584[81:Res:53.1,220581.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.42 220589[82:Spt:220584.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 220591[82:Res:220589.0,61.1] always3(s43) || -> . % 76.30/76.42 220592[82:SSi:220591.0,78259.0,78262.0,217613.0,220455.0,220579.0] || -> . % 76.30/76.42 220593[82:Spt:220592.0,220584.0,220589.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.42 220594[82:Spt:220592.0,220584.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 220598[82:Res:220594.0,61.1] always3(s44) || -> . % 76.30/76.42 220599[82:SSi:220598.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.42 220600[80:Spt:220599.0,220454.0,220455.0] || until2p7(s43)*+ -> . % 76.30/76.42 220601[80:Spt:220599.0,220454.1] || -> node4(s42)*. % 76.30/76.42 220603[80:MRR:792.0,220601.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.42 220606[80:Res:53.1,220603.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.42 220608[81:Spt:220606.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 220610[81:Res:220608.0,61.1] always3(s42) || -> . % 76.30/76.42 220611[81:SSi:220610.0,78254.0,78258.0,217612.0,220453.0,220601.0] || -> . % 76.30/76.42 220612[81:Spt:220611.0,220606.0,220608.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.42 220613[81:Spt:220611.0,220606.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 220617[81:Res:220613.0,61.1] always3(s43) || -> . % 76.30/76.42 220618[81:SSi:220617.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.42 220619[79:Spt:220618.0,220452.0,220453.0] || until2p7(s42)*+ -> . % 76.30/76.42 220620[79:Spt:220618.0,220452.1] || -> node4(s41)*. % 76.30/76.42 220622[79:MRR:795.0,220620.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.42 220625[79:Res:53.1,220622.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.42 220627[80:Spt:220625.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 220629[80:Res:220627.0,61.1] always3(s41) || -> . % 76.30/76.42 220630[80:SSi:220629.0,78250.0,78253.0,217611.0,220451.0,220620.0] || -> . % 76.30/76.42 220631[80:Spt:220630.0,220625.0,220627.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.42 220632[80:Spt:220630.0,220625.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 220636[80:Res:220632.0,61.1] always3(s42) || -> . % 76.30/76.42 220637[80:SSi:220636.0,78254.0,78258.0,217612.0] || -> . % 76.30/76.42 220638[78:Spt:220637.0,220450.0,220451.0] || until2p7(s41)*+ -> . % 76.30/76.42 220639[78:Spt:220637.0,220450.1] || -> node4(s40)*. % 76.30/76.42 220641[78:MRR:798.0,220639.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.42 220644[78:Res:53.1,220641.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.42 220646[79:Spt:220644.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 220648[79:Res:220646.0,61.1] always3(s40) || -> . % 76.30/76.42 220649[79:SSi:220648.0,78245.0,78249.0,217610.0,220449.0,220639.0] || -> . % 76.30/76.42 220650[79:Spt:220649.0,220644.0,220646.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.42 220651[79:Spt:220649.0,220644.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 220655[79:Res:220651.0,61.1] always3(s41) || -> . % 76.30/76.42 220656[79:SSi:220655.0,78250.0,78253.0,217611.0] || -> . % 76.30/76.42 220657[77:Spt:220656.0,220448.0,220449.0] || until2p7(s40)*+ -> . % 76.30/76.42 220658[77:Spt:220656.0,220448.1] || -> node4(s39)*. % 76.30/76.42 220660[77:MRR:801.0,220658.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.42 220663[77:Res:53.1,220660.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.42 220668[78:Spt:220663.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 220670[78:Res:220668.0,61.1] always3(s39) || -> . % 76.30/76.42 220671[78:SSi:220670.0,78241.0,78244.0,217609.0,220447.0,220658.0] || -> . % 76.30/76.42 220672[78:Spt:220671.0,220663.0,220668.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.42 220673[78:Spt:220671.0,220663.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 220677[78:Res:220673.0,61.1] always3(s40) || -> . % 76.30/76.42 220678[78:SSi:220677.0,78245.0,78249.0,217610.0] || -> . % 76.30/76.42 220679[76:Spt:220678.0,220446.0,220447.0] || until2p7(s39)*+ -> . % 76.30/76.42 220680[76:Spt:220678.0,220446.1] || -> node4(s38)*. % 76.30/76.42 220682[76:MRR:804.0,220680.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.42 220685[76:Res:53.1,220682.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.42 220687[77:Spt:220685.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 220689[77:Res:220687.0,61.1] always3(s38) || -> . % 76.30/76.42 220690[77:SSi:220689.0,78236.0,78240.0,217608.0,220445.0,220680.0] || -> . % 76.30/76.42 220691[77:Spt:220690.0,220685.0,220687.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.42 220692[77:Spt:220690.0,220685.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 220696[77:Res:220692.0,61.1] always3(s39) || -> . % 76.30/76.42 220697[77:SSi:220696.0,78241.0,78244.0,217609.0] || -> . % 76.30/76.42 220698[75:Spt:220697.0,220444.0,220445.0] || until2p7(s38)*+ -> . % 76.30/76.42 220699[75:Spt:220697.0,220444.1] || -> node4(s37)*. % 76.30/76.42 220701[75:MRR:807.0,220699.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.42 220704[75:Res:53.1,220701.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.42 220706[76:Spt:220704.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 220708[76:Res:220706.0,61.1] always3(s37) || -> . % 76.30/76.42 220709[76:SSi:220708.0,78232.0,78235.0,217607.0,220443.0,220699.0] || -> . % 76.30/76.42 220710[76:Spt:220709.0,220704.0,220706.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.42 220711[76:Spt:220709.0,220704.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 220715[76:Res:220711.0,61.1] always3(s38) || -> . % 76.30/76.42 220716[76:SSi:220715.0,78236.0,78240.0,217608.0] || -> . % 76.30/76.42 220717[74:Spt:220716.0,220442.0,220443.0] || until2p7(s37)*+ -> . % 76.30/76.42 220718[74:Spt:220716.0,220442.1] || -> node4(s36)*. % 76.30/76.42 220720[74:MRR:810.0,220718.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.42 220723[74:Res:53.1,220720.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.42 220725[75:Spt:220723.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 220727[75:Res:220725.0,61.1] always3(s36) || -> . % 76.30/76.42 220728[75:SSi:220727.0,78227.0,78231.0,217606.0,220441.0,220718.0] || -> . % 76.30/76.42 220729[75:Spt:220728.0,220723.0,220725.0] || m_main_v_state(s36,c_busy)* -> . % 76.30/76.42 220730[75:Spt:220728.0,220723.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 220734[75:Res:220730.0,61.1] always3(s37) || -> . % 76.30/76.42 220735[75:SSi:220734.0,78232.0,78235.0,217607.0] || -> . % 76.30/76.42 220736[73:Spt:220735.0,220440.0,220441.0] || until2p7(s36)*+ -> . % 76.30/76.42 220737[73:Spt:220735.0,220440.1] || -> node4(s35)*. % 76.30/76.42 220739[73:MRR:813.0,220737.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.30/76.42 220742[73:Res:53.1,220739.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.30/76.42 220744[73:MRR:220742.0,220430.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 220749[73:Res:220744.0,61.1] always3(s36) || -> . % 76.30/76.42 220750[73:SSi:220749.0,78227.0,78231.0,217606.0] || -> . % 76.30/76.42 220751[71:Spt:220750.0,220364.0,220367.0] || trans(s49,s35)*+ -> . % 76.30/76.42 220752[71:Spt:220750.0,220364.1,220364.2,220364.3,220364.4,220364.5,220364.6,220364.7,220364.8,220364.9,220364.10,220364.11,220364.12,220364.13,220364.14,220364.15,220364.16,220364.17,220364.18,220364.19,220364.20,220364.21,220364.22,220364.23,220364.24,220364.25,220364.26,220364.27,220364.28] || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.42 220754[71:MRR:220366.1,220751.0] xuntil6(s49) || -> trans(s49,s34) trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.42 220755[72:Spt:220752.0] || -> trans(s49,s34)*. % 76.30/76.42 220756[72:Res:220755.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s34)*. % 76.30/76.42 220758[72:Res:220755.0,60.0] || -> node2(s49,s34)*. % 76.30/76.42 220759[72:SSi:220756.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s34)*. % 76.30/76.42 220760[72:Res:220758.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)*. % 76.30/76.42 220811[72:SoR:220760.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)*. % 76.30/76.42 220813[72:SoR:220811.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s34,c_busy)* xuntil6(s49). % 76.30/76.42 220814[72:SSi:220813.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s34,c_busy)* xuntil6(s49). % 76.30/76.42 220815[73:Spt:220814.1] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.42 220817[73:Res:220815.0,61.1] always3(s34) || -> . % 76.30/76.42 220818[73:SSi:220817.0,78218.0,78222.0,217604.0] || -> . % 76.30/76.42 220819[73:Spt:220818.0,220814.1,220815.0] || m_main_v_state(s34,c_busy)*+ -> . % 76.30/76.42 220820[73:Spt:220818.0,220814.0,220814.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.42 220824[73:MRR:220811.2,220819.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.42 220825[73:Res:53.1,220820.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.42 220827[73:MRR:220825.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.42 220828[73:MRR:220759.0,220827.0] || -> until2p7(s34)*. % 76.30/76.42 220829[73:MRR:230.0,220828.0] || -> until2p7(s35)* node4(s34). % 76.30/76.42 220830[74:Spt:220829.0] || -> until2p7(s35)*. % 76.30/76.42 220831[74:MRR:231.0,220830.0] || -> until2p7(s36)* node4(s35). % 76.30/76.42 220832[75:Spt:220831.0] || -> until2p7(s36)*. % 76.30/76.42 220833[75:MRR:232.0,220832.0] || -> until2p7(s37)* node4(s36). % 76.30/76.42 220834[76:Spt:220833.0] || -> until2p7(s37)*. % 76.30/76.42 220835[76:MRR:235.0,220834.0] || -> until2p7(s38)* node4(s37). % 76.30/76.42 220836[77:Spt:220835.0] || -> until2p7(s38)*. % 76.30/76.42 220837[77:MRR:236.0,220836.0] || -> until2p7(s39)* node4(s38). % 76.30/76.42 220838[78:Spt:220837.0] || -> until2p7(s39)*. % 76.30/76.42 220839[78:MRR:237.0,220838.0] || -> until2p7(s40)* node4(s39). % 76.30/76.42 220840[79:Spt:220839.0] || -> until2p7(s40)*. % 76.30/76.42 220841[79:MRR:238.0,220840.0] || -> until2p7(s41)* node4(s40). % 76.30/76.42 220842[80:Spt:220841.0] || -> until2p7(s41)*. % 76.30/76.42 220843[80:MRR:239.0,220842.0] || -> until2p7(s42)* node4(s41). % 76.30/76.42 220844[81:Spt:220843.0] || -> until2p7(s42)*. % 76.30/76.42 220845[81:MRR:240.0,220844.0] || -> until2p7(s43)* node4(s42). % 76.30/76.42 220846[82:Spt:220845.0] || -> until2p7(s43)*. % 76.30/76.42 220847[82:MRR:241.0,220846.0] || -> until2p7(s44)* node4(s43). % 76.30/76.42 220848[83:Spt:220847.0] || -> until2p7(s44)*. % 76.30/76.42 220849[83:MRR:539.0,220848.0] || -> until2p7(s45)* node4(s44). % 76.30/76.42 220850[84:Spt:220849.0] || -> until2p7(s45)*. % 76.30/76.42 220851[84:MRR:544.0,220850.0] || -> until2p7(s46)* node4(s45). % 76.30/76.42 220852[85:Spt:220851.0] || -> until2p7(s46)*. % 76.30/76.42 220853[85:MRR:549.0,220852.0] || -> until2p7(s47)* node4(s46). % 76.30/76.42 220854[86:Spt:220853.0] || -> until2p7(s47)*. % 76.30/76.42 220855[86:MRR:554.0,220854.0] || -> until2p7(s48)* node4(s47). % 76.30/76.42 220856[87:Spt:220855.0] || -> until2p7(s48)*. % 76.30/76.42 220857[87:MRR:559.0,220856.0] || -> until2p7(s49)* node4(s48). % 76.30/76.42 220858[88:Spt:220857.0] || -> until2p7(s49)*. % 76.30/76.42 220859[88:MRR:194.0,220858.0] || -> node4(s49)*. % 76.30/76.42 220860[88:MRR:220824.0,220859.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.42 220861[88:Res:53.1,220860.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.42 220863[88:MRR:220861.0,78381.0] || -> . % 76.30/76.42 220864[88:Spt:220863.0,220857.0,220858.0] || until2p7(s49)*+ -> . % 76.30/76.42 220865[88:Spt:220863.0,220857.1] || -> node4(s48)*. % 76.30/76.42 220866[88:MRR:78384.0,220865.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.42 220869[88:Res:53.1,220866.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 220872[88:Res:220869.0,61.1] always3(s48) || -> . % 76.30/76.42 220873[88:SSi:220872.0,78281.0,78387.0,217618.0,220856.0,220865.0] || -> . % 76.30/76.42 220874[87:Spt:220873.0,220855.0,220856.0] || until2p7(s48)*+ -> . % 76.30/76.42 220875[87:Spt:220873.0,220855.1] || -> node4(s47)*. % 76.30/76.42 220877[87:MRR:777.0,220875.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.42 220892[87:Res:53.1,220877.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.42 220894[88:Spt:220892.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 220896[88:Res:220894.0,61.1] always3(s47) || -> . % 76.30/76.42 220897[88:SSi:220896.0,78277.0,78280.0,217617.0,220854.0,220875.0] || -> . % 76.30/76.42 220898[88:Spt:220897.0,220892.0,220894.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.42 220899[88:Spt:220897.0,220892.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 220903[88:Res:220899.0,61.1] always3(s48) || -> . % 76.30/76.42 220904[88:SSi:220903.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.42 220905[86:Spt:220904.0,220853.0,220854.0] || until2p7(s47)*+ -> . % 76.30/76.42 220906[86:Spt:220904.0,220853.1] || -> node4(s46)*. % 76.30/76.42 220908[86:MRR:780.0,220906.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.42 220918[86:Res:53.1,220908.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.42 220920[87:Spt:220918.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 220922[87:Res:220920.0,61.1] always3(s46) || -> . % 76.30/76.42 220923[87:SSi:220922.0,78272.0,78276.0,217616.0,220852.0,220906.0] || -> . % 76.30/76.42 220924[87:Spt:220923.0,220918.0,220920.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.42 220925[87:Spt:220923.0,220918.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 220929[87:Res:220925.0,61.1] always3(s47) || -> . % 76.30/76.42 220930[87:SSi:220929.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.42 220931[85:Spt:220930.0,220851.0,220852.0] || until2p7(s46)*+ -> . % 76.30/76.42 220932[85:Spt:220930.0,220851.1] || -> node4(s45)*. % 76.30/76.42 220934[85:MRR:783.0,220932.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.42 220937[85:Res:53.1,220934.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.42 220939[86:Spt:220937.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 220941[86:Res:220939.0,61.1] always3(s45) || -> . % 76.30/76.42 220942[86:SSi:220941.0,78268.0,78271.0,217615.0,220850.0,220932.0] || -> . % 76.30/76.42 220943[86:Spt:220942.0,220937.0,220939.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.42 220944[86:Spt:220942.0,220937.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 220948[86:Res:220944.0,61.1] always3(s46) || -> . % 76.30/76.42 220949[86:SSi:220948.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.42 220950[84:Spt:220949.0,220849.0,220850.0] || until2p7(s45)*+ -> . % 76.30/76.42 220951[84:Spt:220949.0,220849.1] || -> node4(s44)*. % 76.30/76.42 220953[84:MRR:786.0,220951.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.42 220956[84:Res:53.1,220953.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.42 220958[85:Spt:220956.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 220960[85:Res:220958.0,61.1] always3(s44) || -> . % 76.30/76.42 220961[85:SSi:220960.0,78263.0,78267.0,217614.0,220848.0,220951.0] || -> . % 76.30/76.42 220962[85:Spt:220961.0,220956.0,220958.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.42 220963[85:Spt:220961.0,220956.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 220967[85:Res:220963.0,61.1] always3(s45) || -> . % 76.30/76.42 220968[85:SSi:220967.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.42 220969[83:Spt:220968.0,220847.0,220848.0] || until2p7(s44)*+ -> . % 76.30/76.42 220970[83:Spt:220968.0,220847.1] || -> node4(s43)*. % 76.30/76.42 220972[83:MRR:789.0,220970.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.42 220975[83:Res:53.1,220972.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.42 220980[84:Spt:220975.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 220982[84:Res:220980.0,61.1] always3(s43) || -> . % 76.30/76.42 220983[84:SSi:220982.0,78259.0,78262.0,217613.0,220846.0,220970.0] || -> . % 76.30/76.42 220984[84:Spt:220983.0,220975.0,220980.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.42 220985[84:Spt:220983.0,220975.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 220989[84:Res:220985.0,61.1] always3(s44) || -> . % 76.30/76.42 220990[84:SSi:220989.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.42 220991[82:Spt:220990.0,220845.0,220846.0] || until2p7(s43)*+ -> . % 76.30/76.42 220992[82:Spt:220990.0,220845.1] || -> node4(s42)*. % 76.30/76.42 220994[82:MRR:792.0,220992.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.42 220997[82:Res:53.1,220994.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.42 220999[83:Spt:220997.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 221001[83:Res:220999.0,61.1] always3(s42) || -> . % 76.30/76.42 221002[83:SSi:221001.0,78254.0,78258.0,217612.0,220844.0,220992.0] || -> . % 76.30/76.42 221003[83:Spt:221002.0,220997.0,220999.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.42 221004[83:Spt:221002.0,220997.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 221008[83:Res:221004.0,61.1] always3(s43) || -> . % 76.30/76.42 221009[83:SSi:221008.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.42 221010[81:Spt:221009.0,220843.0,220844.0] || until2p7(s42)*+ -> . % 76.30/76.42 221011[81:Spt:221009.0,220843.1] || -> node4(s41)*. % 76.30/76.42 221013[81:MRR:795.0,221011.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.42 221016[81:Res:53.1,221013.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.42 221018[82:Spt:221016.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 221020[82:Res:221018.0,61.1] always3(s41) || -> . % 76.30/76.42 221021[82:SSi:221020.0,78250.0,78253.0,217611.0,220842.0,221011.0] || -> . % 76.30/76.42 221022[82:Spt:221021.0,221016.0,221018.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.42 221023[82:Spt:221021.0,221016.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 221027[82:Res:221023.0,61.1] always3(s42) || -> . % 76.30/76.42 221028[82:SSi:221027.0,78254.0,78258.0,217612.0] || -> . % 76.30/76.42 221029[80:Spt:221028.0,220841.0,220842.0] || until2p7(s41)*+ -> . % 76.30/76.42 221030[80:Spt:221028.0,220841.1] || -> node4(s40)*. % 76.30/76.42 221032[80:MRR:798.0,221030.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.42 221035[80:Res:53.1,221032.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.42 221037[81:Spt:221035.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 221039[81:Res:221037.0,61.1] always3(s40) || -> . % 76.30/76.42 221040[81:SSi:221039.0,78245.0,78249.0,217610.0,220840.0,221030.0] || -> . % 76.30/76.42 221041[81:Spt:221040.0,221035.0,221037.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.42 221042[81:Spt:221040.0,221035.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 221046[81:Res:221042.0,61.1] always3(s41) || -> . % 76.30/76.42 221047[81:SSi:221046.0,78250.0,78253.0,217611.0] || -> . % 76.30/76.42 221048[79:Spt:221047.0,220839.0,220840.0] || until2p7(s40)*+ -> . % 76.30/76.42 221049[79:Spt:221047.0,220839.1] || -> node4(s39)*. % 76.30/76.42 221051[79:MRR:801.0,221049.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.42 221054[79:Res:53.1,221051.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.42 221059[80:Spt:221054.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 221061[80:Res:221059.0,61.1] always3(s39) || -> . % 76.30/76.42 221062[80:SSi:221061.0,78241.0,78244.0,217609.0,220838.0,221049.0] || -> . % 76.30/76.42 221063[80:Spt:221062.0,221054.0,221059.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.42 221064[80:Spt:221062.0,221054.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 221068[80:Res:221064.0,61.1] always3(s40) || -> . % 76.30/76.42 221069[80:SSi:221068.0,78245.0,78249.0,217610.0] || -> . % 76.30/76.42 221070[78:Spt:221069.0,220837.0,220838.0] || until2p7(s39)*+ -> . % 76.30/76.42 221071[78:Spt:221069.0,220837.1] || -> node4(s38)*. % 76.30/76.42 221073[78:MRR:804.0,221071.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.42 221076[78:Res:53.1,221073.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.42 221078[79:Spt:221076.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 221080[79:Res:221078.0,61.1] always3(s38) || -> . % 76.30/76.42 221081[79:SSi:221080.0,78236.0,78240.0,217608.0,220836.0,221071.0] || -> . % 76.30/76.42 221082[79:Spt:221081.0,221076.0,221078.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.42 221083[79:Spt:221081.0,221076.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 221087[79:Res:221083.0,61.1] always3(s39) || -> . % 76.30/76.42 221088[79:SSi:221087.0,78241.0,78244.0,217609.0] || -> . % 76.30/76.42 221089[77:Spt:221088.0,220835.0,220836.0] || until2p7(s38)*+ -> . % 76.30/76.42 221090[77:Spt:221088.0,220835.1] || -> node4(s37)*. % 76.30/76.42 221092[77:MRR:807.0,221090.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.42 221095[77:Res:53.1,221092.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.42 221097[78:Spt:221095.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 221099[78:Res:221097.0,61.1] always3(s37) || -> . % 76.30/76.42 221100[78:SSi:221099.0,78232.0,78235.0,217607.0,220834.0,221090.0] || -> . % 76.30/76.42 221101[78:Spt:221100.0,221095.0,221097.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.42 221102[78:Spt:221100.0,221095.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 221106[78:Res:221102.0,61.1] always3(s38) || -> . % 76.30/76.42 221107[78:SSi:221106.0,78236.0,78240.0,217608.0] || -> . % 76.30/76.42 221108[76:Spt:221107.0,220833.0,220834.0] || until2p7(s37)*+ -> . % 76.30/76.42 221109[76:Spt:221107.0,220833.1] || -> node4(s36)*. % 76.30/76.42 221111[76:MRR:810.0,221109.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.42 221114[76:Res:53.1,221111.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.42 221116[77:Spt:221114.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 221118[77:Res:221116.0,61.1] always3(s36) || -> . % 76.30/76.42 221119[77:SSi:221118.0,78227.0,78231.0,217606.0,220832.0,221109.0] || -> . % 76.30/76.42 221120[77:Spt:221119.0,221114.0,221116.0] || m_main_v_state(s36,c_busy)* -> . % 76.30/76.42 221121[77:Spt:221119.0,221114.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 221125[77:Res:221121.0,61.1] always3(s37) || -> . % 76.30/76.42 221126[77:SSi:221125.0,78232.0,78235.0,217607.0] || -> . % 76.30/76.42 221127[75:Spt:221126.0,220831.0,220832.0] || until2p7(s36)*+ -> . % 76.30/76.42 221128[75:Spt:221126.0,220831.1] || -> node4(s35)*. % 76.30/76.42 221130[75:MRR:813.0,221128.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.30/76.42 221133[75:Res:53.1,221130.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.30/76.42 221138[76:Spt:221133.0] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.42 221140[76:Res:221138.0,61.1] always3(s35) || -> . % 76.30/76.42 221141[76:SSi:221140.0,78223.0,78226.0,217605.0,220830.0,221128.0] || -> . % 76.30/76.42 221142[76:Spt:221141.0,221133.0,221138.0] || m_main_v_state(s35,c_busy)* -> . % 76.30/76.42 221143[76:Spt:221141.0,221133.1] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 221147[76:Res:221143.0,61.1] always3(s36) || -> . % 76.30/76.42 221148[76:SSi:221147.0,78227.0,78231.0,217606.0] || -> . % 76.30/76.42 221149[74:Spt:221148.0,220829.0,220830.0] || until2p7(s35)*+ -> . % 76.30/76.42 221150[74:Spt:221148.0,220829.1] || -> node4(s34)*. % 76.30/76.42 221152[74:MRR:816.0,221150.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.30/76.42 221155[74:Res:53.1,221152.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.30/76.42 221157[74:MRR:221155.0,220819.0] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.42 221159[74:Res:221157.0,61.1] always3(s35) || -> . % 76.30/76.42 221160[74:SSi:221159.0,78223.0,78226.0,217605.0] || -> . % 76.30/76.42 221161[72:Spt:221160.0,220752.0,220755.0] || trans(s49,s34)*+ -> . % 76.30/76.42 221162[72:Spt:221160.0,220752.1,220752.2,220752.3,220752.4,220752.5,220752.6,220752.7,220752.8,220752.9,220752.10,220752.11,220752.12,220752.13,220752.14,220752.15,220752.16,220752.17,220752.18,220752.19,220752.20,220752.21,220752.22,220752.23,220752.24,220752.25,220752.26,220752.27] || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.42 221164[72:MRR:220754.1,221161.0] xuntil6(s49) || -> trans(s49,s33) trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.42 221165[73:Spt:221162.0] || -> trans(s49,s33)*. % 76.30/76.42 221166[73:Res:221165.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s33)*. % 76.30/76.42 221168[73:Res:221165.0,60.0] || -> node2(s49,s33)*. % 76.30/76.42 221169[73:SSi:221166.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s33)*. % 76.30/76.42 221170[73:Res:221168.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.30/76.42 221225[73:SoR:221170.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)*. % 76.30/76.42 221227[73:SoR:221225.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.30/76.42 221228[73:SSi:221227.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s33,c_busy)* xuntil6(s49). % 76.30/76.42 221229[74:Spt:221228.1] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.42 221231[74:Res:221229.0,61.1] always3(s33) || -> . % 76.30/76.42 221232[74:SSi:221231.0,78214.0,78217.0,217603.0] || -> . % 76.30/76.42 221233[74:Spt:221232.0,221228.1,221229.0] || m_main_v_state(s33,c_busy)*+ -> . % 76.30/76.42 221234[74:Spt:221232.0,221228.0,221228.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.42 221238[74:MRR:221225.2,221233.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.42 221239[74:Res:53.1,221234.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.42 221241[74:MRR:221239.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.42 221242[74:MRR:221169.0,221241.0] || -> until2p7(s33)*. % 76.30/76.42 221243[74:MRR:229.0,221242.0] || -> until2p7(s34)* node4(s33). % 76.30/76.42 221244[75:Spt:221243.0] || -> until2p7(s34)*. % 76.30/76.42 221245[75:MRR:230.0,221244.0] || -> until2p7(s35)* node4(s34). % 76.30/76.42 221246[76:Spt:221245.0] || -> until2p7(s35)*. % 76.30/76.42 221247[76:MRR:231.0,221246.0] || -> until2p7(s36)* node4(s35). % 76.30/76.42 221248[77:Spt:221247.0] || -> until2p7(s36)*. % 76.30/76.42 221249[77:MRR:232.0,221248.0] || -> until2p7(s37)* node4(s36). % 76.30/76.42 221250[78:Spt:221249.0] || -> until2p7(s37)*. % 76.30/76.42 221251[78:MRR:235.0,221250.0] || -> until2p7(s38)* node4(s37). % 76.30/76.42 221252[79:Spt:221251.0] || -> until2p7(s38)*. % 76.30/76.42 221253[79:MRR:236.0,221252.0] || -> until2p7(s39)* node4(s38). % 76.30/76.42 221254[80:Spt:221253.0] || -> until2p7(s39)*. % 76.30/76.42 221255[80:MRR:237.0,221254.0] || -> until2p7(s40)* node4(s39). % 76.30/76.42 221256[81:Spt:221255.0] || -> until2p7(s40)*. % 76.30/76.42 221257[81:MRR:238.0,221256.0] || -> until2p7(s41)* node4(s40). % 76.30/76.42 221258[82:Spt:221257.0] || -> until2p7(s41)*. % 76.30/76.42 221259[82:MRR:239.0,221258.0] || -> until2p7(s42)* node4(s41). % 76.30/76.42 221260[83:Spt:221259.0] || -> until2p7(s42)*. % 76.30/76.42 221261[83:MRR:240.0,221260.0] || -> until2p7(s43)* node4(s42). % 76.30/76.42 221262[84:Spt:221261.0] || -> until2p7(s43)*. % 76.30/76.42 221263[84:MRR:241.0,221262.0] || -> until2p7(s44)* node4(s43). % 76.30/76.42 221264[85:Spt:221263.0] || -> until2p7(s44)*. % 76.30/76.42 221265[85:MRR:539.0,221264.0] || -> until2p7(s45)* node4(s44). % 76.30/76.42 221266[86:Spt:221265.0] || -> until2p7(s45)*. % 76.30/76.42 221267[86:MRR:544.0,221266.0] || -> until2p7(s46)* node4(s45). % 76.30/76.42 221268[87:Spt:221267.0] || -> until2p7(s46)*. % 76.30/76.42 221269[87:MRR:549.0,221268.0] || -> until2p7(s47)* node4(s46). % 76.30/76.42 221270[88:Spt:221269.0] || -> until2p7(s47)*. % 76.30/76.42 221271[88:MRR:554.0,221270.0] || -> until2p7(s48)* node4(s47). % 76.30/76.42 221272[89:Spt:221271.0] || -> until2p7(s48)*. % 76.30/76.42 221273[89:MRR:559.0,221272.0] || -> until2p7(s49)* node4(s48). % 76.30/76.42 221274[90:Spt:221273.0] || -> until2p7(s49)*. % 76.30/76.42 221275[90:MRR:194.0,221274.0] || -> node4(s49)*. % 76.30/76.42 221276[90:MRR:221238.0,221275.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.42 221280[90:Res:53.1,221276.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.42 221282[90:MRR:221280.0,78381.0] || -> . % 76.30/76.42 221283[90:Spt:221282.0,221273.0,221274.0] || until2p7(s49)*+ -> . % 76.30/76.42 221284[90:Spt:221282.0,221273.1] || -> node4(s48)*. % 76.30/76.42 221285[90:MRR:78384.0,221284.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.42 221288[90:Res:53.1,221285.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 221291[90:Res:221288.0,61.1] always3(s48) || -> . % 76.30/76.42 221292[90:SSi:221291.0,78281.0,78387.0,217618.0,221272.0,221284.0] || -> . % 76.30/76.42 221293[89:Spt:221292.0,221271.0,221272.0] || until2p7(s48)*+ -> . % 76.30/76.42 221294[89:Spt:221292.0,221271.1] || -> node4(s47)*. % 76.30/76.42 221296[89:MRR:777.0,221294.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.42 221308[89:Res:53.1,221296.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.42 221310[90:Spt:221308.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 221312[90:Res:221310.0,61.1] always3(s47) || -> . % 76.30/76.42 221313[90:SSi:221312.0,78277.0,78280.0,217617.0,221270.0,221294.0] || -> . % 76.30/76.42 221314[90:Spt:221313.0,221308.0,221310.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.42 221315[90:Spt:221313.0,221308.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 221319[90:Res:221315.0,61.1] always3(s48) || -> . % 76.30/76.42 221320[90:SSi:221319.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.42 221321[88:Spt:221320.0,221269.0,221270.0] || until2p7(s47)*+ -> . % 76.30/76.42 221322[88:Spt:221320.0,221269.1] || -> node4(s46)*. % 76.30/76.42 221324[88:MRR:780.0,221322.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.42 221331[88:Res:53.1,221324.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.42 221336[89:Spt:221331.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 221338[89:Res:221336.0,61.1] always3(s46) || -> . % 76.30/76.42 221339[89:SSi:221338.0,78272.0,78276.0,217616.0,221268.0,221322.0] || -> . % 76.30/76.42 221340[89:Spt:221339.0,221331.0,221336.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.42 221341[89:Spt:221339.0,221331.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 221345[89:Res:221341.0,61.1] always3(s47) || -> . % 76.30/76.42 221346[89:SSi:221345.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.42 221347[87:Spt:221346.0,221267.0,221268.0] || until2p7(s46)*+ -> . % 76.30/76.42 221348[87:Spt:221346.0,221267.1] || -> node4(s45)*. % 76.30/76.42 221350[87:MRR:783.0,221348.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.42 221353[87:Res:53.1,221350.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.42 221355[88:Spt:221353.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 221357[88:Res:221355.0,61.1] always3(s45) || -> . % 76.30/76.42 221358[88:SSi:221357.0,78268.0,78271.0,217615.0,221266.0,221348.0] || -> . % 76.30/76.42 221359[88:Spt:221358.0,221353.0,221355.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.42 221360[88:Spt:221358.0,221353.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 221364[88:Res:221360.0,61.1] always3(s46) || -> . % 76.30/76.42 221365[88:SSi:221364.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.42 221366[86:Spt:221365.0,221265.0,221266.0] || until2p7(s45)*+ -> . % 76.30/76.42 221367[86:Spt:221365.0,221265.1] || -> node4(s44)*. % 76.30/76.42 221369[86:MRR:786.0,221367.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.42 221372[86:Res:53.1,221369.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.42 221374[87:Spt:221372.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 221376[87:Res:221374.0,61.1] always3(s44) || -> . % 76.30/76.42 221377[87:SSi:221376.0,78263.0,78267.0,217614.0,221264.0,221367.0] || -> . % 76.30/76.42 221378[87:Spt:221377.0,221372.0,221374.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.42 221379[87:Spt:221377.0,221372.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 221383[87:Res:221379.0,61.1] always3(s45) || -> . % 76.30/76.42 221384[87:SSi:221383.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.42 221385[85:Spt:221384.0,221263.0,221264.0] || until2p7(s44)*+ -> . % 76.30/76.42 221386[85:Spt:221384.0,221263.1] || -> node4(s43)*. % 76.30/76.42 221388[85:MRR:789.0,221386.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.42 221391[85:Res:53.1,221388.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.42 221393[86:Spt:221391.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 221395[86:Res:221393.0,61.1] always3(s43) || -> . % 76.30/76.42 221396[86:SSi:221395.0,78259.0,78262.0,217613.0,221262.0,221386.0] || -> . % 76.30/76.42 221397[86:Spt:221396.0,221391.0,221393.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.42 221398[86:Spt:221396.0,221391.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 221402[86:Res:221398.0,61.1] always3(s44) || -> . % 76.30/76.42 221403[86:SSi:221402.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.42 221404[84:Spt:221403.0,221261.0,221262.0] || until2p7(s43)*+ -> . % 76.30/76.42 221405[84:Spt:221403.0,221261.1] || -> node4(s42)*. % 76.30/76.42 221407[84:MRR:792.0,221405.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.42 221410[84:Res:53.1,221407.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.42 221415[85:Spt:221410.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 221417[85:Res:221415.0,61.1] always3(s42) || -> . % 76.30/76.42 221418[85:SSi:221417.0,78254.0,78258.0,217612.0,221260.0,221405.0] || -> . % 76.30/76.42 221419[85:Spt:221418.0,221410.0,221415.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.42 221420[85:Spt:221418.0,221410.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 221424[85:Res:221420.0,61.1] always3(s43) || -> . % 76.30/76.42 221425[85:SSi:221424.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.42 221426[83:Spt:221425.0,221259.0,221260.0] || until2p7(s42)*+ -> . % 76.30/76.42 221427[83:Spt:221425.0,221259.1] || -> node4(s41)*. % 76.30/76.42 221429[83:MRR:795.0,221427.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.42 221432[83:Res:53.1,221429.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.42 221434[84:Spt:221432.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 221436[84:Res:221434.0,61.1] always3(s41) || -> . % 76.30/76.42 221437[84:SSi:221436.0,78250.0,78253.0,217611.0,221258.0,221427.0] || -> . % 76.30/76.42 221438[84:Spt:221437.0,221432.0,221434.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.42 221439[84:Spt:221437.0,221432.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 221443[84:Res:221439.0,61.1] always3(s42) || -> . % 76.30/76.42 221444[84:SSi:221443.0,78254.0,78258.0,217612.0] || -> . % 76.30/76.42 221445[82:Spt:221444.0,221257.0,221258.0] || until2p7(s41)*+ -> . % 76.30/76.42 221446[82:Spt:221444.0,221257.1] || -> node4(s40)*. % 76.30/76.42 221448[82:MRR:798.0,221446.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.42 221451[82:Res:53.1,221448.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.42 221453[83:Spt:221451.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 221455[83:Res:221453.0,61.1] always3(s40) || -> . % 76.30/76.42 221456[83:SSi:221455.0,78245.0,78249.0,217610.0,221256.0,221446.0] || -> . % 76.30/76.42 221457[83:Spt:221456.0,221451.0,221453.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.42 221458[83:Spt:221456.0,221451.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 221462[83:Res:221458.0,61.1] always3(s41) || -> . % 76.30/76.42 221463[83:SSi:221462.0,78250.0,78253.0,217611.0] || -> . % 76.30/76.42 221464[81:Spt:221463.0,221255.0,221256.0] || until2p7(s40)*+ -> . % 76.30/76.42 221465[81:Spt:221463.0,221255.1] || -> node4(s39)*. % 76.30/76.42 221467[81:MRR:801.0,221465.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.42 221470[81:Res:53.1,221467.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.42 221472[82:Spt:221470.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 221474[82:Res:221472.0,61.1] always3(s39) || -> . % 76.30/76.42 221475[82:SSi:221474.0,78241.0,78244.0,217609.0,221254.0,221465.0] || -> . % 76.30/76.42 221476[82:Spt:221475.0,221470.0,221472.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.42 221477[82:Spt:221475.0,221470.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 221481[82:Res:221477.0,61.1] always3(s40) || -> . % 76.30/76.42 221482[82:SSi:221481.0,78245.0,78249.0,217610.0] || -> . % 76.30/76.42 221483[80:Spt:221482.0,221253.0,221254.0] || until2p7(s39)*+ -> . % 76.30/76.42 221484[80:Spt:221482.0,221253.1] || -> node4(s38)*. % 76.30/76.42 221486[80:MRR:804.0,221484.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.42 221489[80:Res:53.1,221486.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.42 221494[81:Spt:221489.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 221496[81:Res:221494.0,61.1] always3(s38) || -> . % 76.30/76.42 221497[81:SSi:221496.0,78236.0,78240.0,217608.0,221252.0,221484.0] || -> . % 76.30/76.42 221498[81:Spt:221497.0,221489.0,221494.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.42 221499[81:Spt:221497.0,221489.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 221503[81:Res:221499.0,61.1] always3(s39) || -> . % 76.30/76.42 221504[81:SSi:221503.0,78241.0,78244.0,217609.0] || -> . % 76.30/76.42 221505[79:Spt:221504.0,221251.0,221252.0] || until2p7(s38)*+ -> . % 76.30/76.42 221506[79:Spt:221504.0,221251.1] || -> node4(s37)*. % 76.30/76.42 221508[79:MRR:807.0,221506.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.42 221511[79:Res:53.1,221508.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.42 221513[80:Spt:221511.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 221515[80:Res:221513.0,61.1] always3(s37) || -> . % 76.30/76.42 221516[80:SSi:221515.0,78232.0,78235.0,217607.0,221250.0,221506.0] || -> . % 76.30/76.42 221517[80:Spt:221516.0,221511.0,221513.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.42 221518[80:Spt:221516.0,221511.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 221522[80:Res:221518.0,61.1] always3(s38) || -> . % 76.30/76.42 221523[80:SSi:221522.0,78236.0,78240.0,217608.0] || -> . % 76.30/76.42 221524[78:Spt:221523.0,221249.0,221250.0] || until2p7(s37)*+ -> . % 76.30/76.42 221525[78:Spt:221523.0,221249.1] || -> node4(s36)*. % 76.30/76.42 221527[78:MRR:810.0,221525.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.42 221530[78:Res:53.1,221527.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.42 221532[79:Spt:221530.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 221534[79:Res:221532.0,61.1] always3(s36) || -> . % 76.30/76.42 221535[79:SSi:221534.0,78227.0,78231.0,217606.0,221248.0,221525.0] || -> . % 76.30/76.42 221536[79:Spt:221535.0,221530.0,221532.0] || m_main_v_state(s36,c_busy)* -> . % 76.30/76.42 221537[79:Spt:221535.0,221530.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 221541[79:Res:221537.0,61.1] always3(s37) || -> . % 76.30/76.42 221542[79:SSi:221541.0,78232.0,78235.0,217607.0] || -> . % 76.30/76.42 221543[77:Spt:221542.0,221247.0,221248.0] || until2p7(s36)*+ -> . % 76.30/76.42 221544[77:Spt:221542.0,221247.1] || -> node4(s35)*. % 76.30/76.42 221546[77:MRR:813.0,221544.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.30/76.42 221549[77:Res:53.1,221546.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.30/76.42 221551[78:Spt:221549.0] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.42 221553[78:Res:221551.0,61.1] always3(s35) || -> . % 76.30/76.42 221554[78:SSi:221553.0,78223.0,78226.0,217605.0,221246.0,221544.0] || -> . % 76.30/76.42 221555[78:Spt:221554.0,221549.0,221551.0] || m_main_v_state(s35,c_busy)* -> . % 76.30/76.42 221556[78:Spt:221554.0,221549.1] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 221560[78:Res:221556.0,61.1] always3(s36) || -> . % 76.30/76.42 221561[78:SSi:221560.0,78227.0,78231.0,217606.0] || -> . % 76.30/76.42 221562[76:Spt:221561.0,221245.0,221246.0] || until2p7(s35)*+ -> . % 76.30/76.42 221563[76:Spt:221561.0,221245.1] || -> node4(s34)*. % 76.30/76.42 221565[76:MRR:816.0,221563.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.30/76.42 221568[76:Res:53.1,221565.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.30/76.42 221573[77:Spt:221568.0] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.42 221575[77:Res:221573.0,61.1] always3(s34) || -> . % 76.30/76.42 221576[77:SSi:221575.0,78218.0,78222.0,217604.0,221244.0,221563.0] || -> . % 76.30/76.42 221577[77:Spt:221576.0,221568.0,221573.0] || m_main_v_state(s34,c_busy)* -> . % 76.30/76.42 221578[77:Spt:221576.0,221568.1] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.42 221582[77:Res:221578.0,61.1] always3(s35) || -> . % 76.30/76.42 221583[77:SSi:221582.0,78223.0,78226.0,217605.0] || -> . % 76.30/76.42 221584[75:Spt:221583.0,221243.0,221244.0] || until2p7(s34)*+ -> . % 76.30/76.42 221585[75:Spt:221583.0,221243.1] || -> node4(s33)*. % 76.30/76.42 221587[75:MRR:819.0,221585.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.30/76.42 221590[75:Res:53.1,221587.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.30/76.42 221592[75:MRR:221590.0,221233.0] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.42 221594[75:Res:221592.0,61.1] always3(s34) || -> . % 76.30/76.42 221595[75:SSi:221594.0,78218.0,78222.0,217604.0] || -> . % 76.30/76.42 221596[73:Spt:221595.0,221162.0,221165.0] || trans(s49,s33)*+ -> . % 76.30/76.42 221597[73:Spt:221595.0,221162.1,221162.2,221162.3,221162.4,221162.5,221162.6,221162.7,221162.8,221162.9,221162.10,221162.11,221162.12,221162.13,221162.14,221162.15,221162.16,221162.17,221162.18,221162.19,221162.20,221162.21,221162.22,221162.23,221162.24,221162.25,221162.26] || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.42 221599[73:MRR:221164.1,221596.0] xuntil6(s49) || -> trans(s49,s32) trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.42 221600[74:Spt:221597.0] || -> trans(s49,s32)*. % 76.30/76.42 221601[74:Res:221600.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s32)*. % 76.30/76.42 221603[74:Res:221600.0,60.0] || -> node2(s49,s32)*. % 76.30/76.42 221604[74:SSi:221601.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s32)*. % 76.30/76.42 221605[74:Res:221603.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)*. % 76.30/76.42 221664[74:SoR:221605.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)*. % 76.30/76.42 221666[74:SoR:221664.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s32,c_busy)* xuntil6(s49). % 76.30/76.42 221667[74:SSi:221666.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s32,c_busy)* xuntil6(s49). % 76.30/76.42 221668[75:Spt:221667.1] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.42 221670[75:Res:221668.0,61.1] always3(s32) || -> . % 76.30/76.42 221671[75:SSi:221670.0,78209.0,78213.0,217602.0] || -> . % 76.30/76.42 221672[75:Spt:221671.0,221667.1,221668.0] || m_main_v_state(s32,c_busy)*+ -> . % 76.30/76.42 221673[75:Spt:221671.0,221667.0,221667.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.42 221677[75:MRR:221664.2,221672.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.42 221678[75:Res:53.1,221673.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.42 221680[75:MRR:221678.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.42 221681[75:MRR:221604.0,221680.0] || -> until2p7(s32)*. % 76.30/76.42 221682[75:MRR:228.0,221681.0] || -> until2p7(s33)* node4(s32). % 76.30/76.42 221683[76:Spt:221682.0] || -> until2p7(s33)*. % 76.30/76.42 221684[76:MRR:229.0,221683.0] || -> until2p7(s34)* node4(s33). % 76.30/76.42 221685[77:Spt:221684.0] || -> until2p7(s34)*. % 76.30/76.42 221686[77:MRR:230.0,221685.0] || -> until2p7(s35)* node4(s34). % 76.30/76.42 221687[78:Spt:221686.0] || -> until2p7(s35)*. % 76.30/76.42 221688[78:MRR:231.0,221687.0] || -> until2p7(s36)* node4(s35). % 76.30/76.42 221689[79:Spt:221688.0] || -> until2p7(s36)*. % 76.30/76.42 221690[79:MRR:232.0,221689.0] || -> until2p7(s37)* node4(s36). % 76.30/76.42 221691[80:Spt:221690.0] || -> until2p7(s37)*. % 76.30/76.42 221692[80:MRR:235.0,221691.0] || -> until2p7(s38)* node4(s37). % 76.30/76.42 221693[81:Spt:221692.0] || -> until2p7(s38)*. % 76.30/76.42 221694[81:MRR:236.0,221693.0] || -> until2p7(s39)* node4(s38). % 76.30/76.42 221695[82:Spt:221694.0] || -> until2p7(s39)*. % 76.30/76.42 221696[82:MRR:237.0,221695.0] || -> until2p7(s40)* node4(s39). % 76.30/76.42 221697[83:Spt:221696.0] || -> until2p7(s40)*. % 76.30/76.42 221698[83:MRR:238.0,221697.0] || -> until2p7(s41)* node4(s40). % 76.30/76.42 221699[84:Spt:221698.0] || -> until2p7(s41)*. % 76.30/76.42 221700[84:MRR:239.0,221699.0] || -> until2p7(s42)* node4(s41). % 76.30/76.42 221701[85:Spt:221700.0] || -> until2p7(s42)*. % 76.30/76.42 221702[85:MRR:240.0,221701.0] || -> until2p7(s43)* node4(s42). % 76.30/76.42 221703[86:Spt:221702.0] || -> until2p7(s43)*. % 76.30/76.42 221704[86:MRR:241.0,221703.0] || -> until2p7(s44)* node4(s43). % 76.30/76.42 221705[87:Spt:221704.0] || -> until2p7(s44)*. % 76.30/76.42 221706[87:MRR:539.0,221705.0] || -> until2p7(s45)* node4(s44). % 76.30/76.42 221707[88:Spt:221706.0] || -> until2p7(s45)*. % 76.30/76.42 221708[88:MRR:544.0,221707.0] || -> until2p7(s46)* node4(s45). % 76.30/76.42 221709[89:Spt:221708.0] || -> until2p7(s46)*. % 76.30/76.42 221710[89:MRR:549.0,221709.0] || -> until2p7(s47)* node4(s46). % 76.30/76.42 221711[90:Spt:221710.0] || -> until2p7(s47)*. % 76.30/76.42 221712[90:MRR:554.0,221711.0] || -> until2p7(s48)* node4(s47). % 76.30/76.42 221713[91:Spt:221712.0] || -> until2p7(s48)*. % 76.30/76.42 221714[91:MRR:559.0,221713.0] || -> until2p7(s49)* node4(s48). % 76.30/76.42 221715[92:Spt:221714.0] || -> until2p7(s49)*. % 76.30/76.42 221716[92:MRR:194.0,221715.0] || -> node4(s49)*. % 76.30/76.42 221717[92:MRR:221677.0,221716.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.42 221718[92:Res:53.1,221717.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.42 221720[92:MRR:221718.0,78381.0] || -> . % 76.30/76.42 221721[92:Spt:221720.0,221714.0,221715.0] || until2p7(s49)*+ -> . % 76.30/76.42 221722[92:Spt:221720.0,221714.1] || -> node4(s48)*. % 76.30/76.42 221723[92:MRR:78384.0,221722.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.42 221726[92:Res:53.1,221723.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 221729[92:Res:221726.0,61.1] always3(s48) || -> . % 76.30/76.42 221730[92:SSi:221729.0,78281.0,78387.0,217618.0,221713.0,221722.0] || -> . % 76.30/76.42 221731[91:Spt:221730.0,221712.0,221713.0] || until2p7(s48)*+ -> . % 76.30/76.42 221732[91:Spt:221730.0,221712.1] || -> node4(s47)*. % 76.30/76.42 221734[91:MRR:777.0,221732.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.42 221749[91:Res:53.1,221734.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.42 221754[92:Spt:221749.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 221756[92:Res:221754.0,61.1] always3(s47) || -> . % 76.30/76.42 221757[92:SSi:221756.0,78277.0,78280.0,217617.0,221711.0,221732.0] || -> . % 76.30/76.42 221758[92:Spt:221757.0,221749.0,221754.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.42 221759[92:Spt:221757.0,221749.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 221763[92:Res:221759.0,61.1] always3(s48) || -> . % 76.30/76.42 221764[92:SSi:221763.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.42 221765[90:Spt:221764.0,221710.0,221711.0] || until2p7(s47)*+ -> . % 76.30/76.42 221766[90:Spt:221764.0,221710.1] || -> node4(s46)*. % 76.30/76.42 221768[90:MRR:780.0,221766.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.42 221775[90:Res:53.1,221768.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.42 221777[91:Spt:221775.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 221779[91:Res:221777.0,61.1] always3(s46) || -> . % 76.30/76.42 221780[91:SSi:221779.0,78272.0,78276.0,217616.0,221709.0,221766.0] || -> . % 76.30/76.42 221781[91:Spt:221780.0,221775.0,221777.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.42 221782[91:Spt:221780.0,221775.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 221786[91:Res:221782.0,61.1] always3(s47) || -> . % 76.30/76.42 221787[91:SSi:221786.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.42 221788[89:Spt:221787.0,221708.0,221709.0] || until2p7(s46)*+ -> . % 76.30/76.42 221789[89:Spt:221787.0,221708.1] || -> node4(s45)*. % 76.30/76.42 221791[89:MRR:783.0,221789.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.42 221794[89:Res:53.1,221791.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.42 221799[90:Spt:221794.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 221801[90:Res:221799.0,61.1] always3(s45) || -> . % 76.30/76.42 221802[90:SSi:221801.0,78268.0,78271.0,217615.0,221707.0,221789.0] || -> . % 76.30/76.42 221803[90:Spt:221802.0,221794.0,221799.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.42 221804[90:Spt:221802.0,221794.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 221808[90:Res:221804.0,61.1] always3(s46) || -> . % 76.30/76.42 221809[90:SSi:221808.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.42 221810[88:Spt:221809.0,221706.0,221707.0] || until2p7(s45)*+ -> . % 76.30/76.42 221811[88:Spt:221809.0,221706.1] || -> node4(s44)*. % 76.30/76.42 221813[88:MRR:786.0,221811.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.42 221816[88:Res:53.1,221813.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.42 221818[89:Spt:221816.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 221820[89:Res:221818.0,61.1] always3(s44) || -> . % 76.30/76.42 221821[89:SSi:221820.0,78263.0,78267.0,217614.0,221705.0,221811.0] || -> . % 76.30/76.42 221822[89:Spt:221821.0,221816.0,221818.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.42 221823[89:Spt:221821.0,221816.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 221827[89:Res:221823.0,61.1] always3(s45) || -> . % 76.30/76.42 221828[89:SSi:221827.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.42 221829[87:Spt:221828.0,221704.0,221705.0] || until2p7(s44)*+ -> . % 76.30/76.42 221830[87:Spt:221828.0,221704.1] || -> node4(s43)*. % 76.30/76.42 221832[87:MRR:789.0,221830.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.42 221835[87:Res:53.1,221832.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.42 221837[88:Spt:221835.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 221839[88:Res:221837.0,61.1] always3(s43) || -> . % 76.30/76.42 221840[88:SSi:221839.0,78259.0,78262.0,217613.0,221703.0,221830.0] || -> . % 76.30/76.42 221841[88:Spt:221840.0,221835.0,221837.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.42 221842[88:Spt:221840.0,221835.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 221846[88:Res:221842.0,61.1] always3(s44) || -> . % 76.30/76.42 221847[88:SSi:221846.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.42 221848[86:Spt:221847.0,221702.0,221703.0] || until2p7(s43)*+ -> . % 76.30/76.42 221849[86:Spt:221847.0,221702.1] || -> node4(s42)*. % 76.30/76.42 221851[86:MRR:792.0,221849.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.42 221854[86:Res:53.1,221851.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.42 221856[87:Spt:221854.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 221858[87:Res:221856.0,61.1] always3(s42) || -> . % 76.30/76.42 221859[87:SSi:221858.0,78254.0,78258.0,217612.0,221701.0,221849.0] || -> . % 76.30/76.42 221860[87:Spt:221859.0,221854.0,221856.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.42 221861[87:Spt:221859.0,221854.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 221865[87:Res:221861.0,61.1] always3(s43) || -> . % 76.30/76.42 221866[87:SSi:221865.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.42 221867[85:Spt:221866.0,221700.0,221701.0] || until2p7(s42)*+ -> . % 76.30/76.42 221868[85:Spt:221866.0,221700.1] || -> node4(s41)*. % 76.30/76.42 221870[85:MRR:795.0,221868.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.42 221873[85:Res:53.1,221870.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.42 221878[86:Spt:221873.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 221880[86:Res:221878.0,61.1] always3(s41) || -> . % 76.30/76.42 221881[86:SSi:221880.0,78250.0,78253.0,217611.0,221699.0,221868.0] || -> . % 76.30/76.42 221882[86:Spt:221881.0,221873.0,221878.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.42 221883[86:Spt:221881.0,221873.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 221887[86:Res:221883.0,61.1] always3(s42) || -> . % 76.30/76.42 221888[86:SSi:221887.0,78254.0,78258.0,217612.0] || -> . % 76.30/76.42 221889[84:Spt:221888.0,221698.0,221699.0] || until2p7(s41)*+ -> . % 76.30/76.42 221890[84:Spt:221888.0,221698.1] || -> node4(s40)*. % 76.30/76.42 221892[84:MRR:798.0,221890.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.42 221895[84:Res:53.1,221892.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.42 221897[85:Spt:221895.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 221899[85:Res:221897.0,61.1] always3(s40) || -> . % 76.30/76.42 221900[85:SSi:221899.0,78245.0,78249.0,217610.0,221697.0,221890.0] || -> . % 76.30/76.42 221901[85:Spt:221900.0,221895.0,221897.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.42 221902[85:Spt:221900.0,221895.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 221906[85:Res:221902.0,61.1] always3(s41) || -> . % 76.30/76.42 221907[85:SSi:221906.0,78250.0,78253.0,217611.0] || -> . % 76.30/76.42 221908[83:Spt:221907.0,221696.0,221697.0] || until2p7(s40)*+ -> . % 76.30/76.42 221909[83:Spt:221907.0,221696.1] || -> node4(s39)*. % 76.30/76.42 221911[83:MRR:801.0,221909.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.42 221914[83:Res:53.1,221911.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.42 221916[84:Spt:221914.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 221918[84:Res:221916.0,61.1] always3(s39) || -> . % 76.30/76.42 221919[84:SSi:221918.0,78241.0,78244.0,217609.0,221695.0,221909.0] || -> . % 76.30/76.42 221920[84:Spt:221919.0,221914.0,221916.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.42 221921[84:Spt:221919.0,221914.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 221925[84:Res:221921.0,61.1] always3(s40) || -> . % 76.30/76.42 221926[84:SSi:221925.0,78245.0,78249.0,217610.0] || -> . % 76.30/76.42 221927[82:Spt:221926.0,221694.0,221695.0] || until2p7(s39)*+ -> . % 76.30/76.42 221928[82:Spt:221926.0,221694.1] || -> node4(s38)*. % 76.30/76.42 221930[82:MRR:804.0,221928.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.42 221933[82:Res:53.1,221930.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.42 221935[83:Spt:221933.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 221937[83:Res:221935.0,61.1] always3(s38) || -> . % 76.30/76.42 221938[83:SSi:221937.0,78236.0,78240.0,217608.0,221693.0,221928.0] || -> . % 76.30/76.42 221939[83:Spt:221938.0,221933.0,221935.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.42 221940[83:Spt:221938.0,221933.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 221944[83:Res:221940.0,61.1] always3(s39) || -> . % 76.30/76.42 221945[83:SSi:221944.0,78241.0,78244.0,217609.0] || -> . % 76.30/76.42 221946[81:Spt:221945.0,221692.0,221693.0] || until2p7(s38)*+ -> . % 76.30/76.42 221947[81:Spt:221945.0,221692.1] || -> node4(s37)*. % 76.30/76.42 221949[81:MRR:807.0,221947.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.42 221952[81:Res:53.1,221949.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.42 221957[82:Spt:221952.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 221959[82:Res:221957.0,61.1] always3(s37) || -> . % 76.30/76.42 221960[82:SSi:221959.0,78232.0,78235.0,217607.0,221691.0,221947.0] || -> . % 76.30/76.42 221961[82:Spt:221960.0,221952.0,221957.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.42 221962[82:Spt:221960.0,221952.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 221966[82:Res:221962.0,61.1] always3(s38) || -> . % 76.30/76.42 221967[82:SSi:221966.0,78236.0,78240.0,217608.0] || -> . % 76.30/76.42 221968[80:Spt:221967.0,221690.0,221691.0] || until2p7(s37)*+ -> . % 76.30/76.42 221969[80:Spt:221967.0,221690.1] || -> node4(s36)*. % 76.30/76.42 221971[80:MRR:810.0,221969.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.42 221974[80:Res:53.1,221971.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.42 221976[81:Spt:221974.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 221978[81:Res:221976.0,61.1] always3(s36) || -> . % 76.30/76.42 221979[81:SSi:221978.0,78227.0,78231.0,217606.0,221689.0,221969.0] || -> . % 76.30/76.42 221980[81:Spt:221979.0,221974.0,221976.0] || m_main_v_state(s36,c_busy)* -> . % 76.30/76.42 221981[81:Spt:221979.0,221974.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 221985[81:Res:221981.0,61.1] always3(s37) || -> . % 76.30/76.42 221986[81:SSi:221985.0,78232.0,78235.0,217607.0] || -> . % 76.30/76.42 221987[79:Spt:221986.0,221688.0,221689.0] || until2p7(s36)*+ -> . % 76.30/76.42 221988[79:Spt:221986.0,221688.1] || -> node4(s35)*. % 76.30/76.42 221990[79:MRR:813.0,221988.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.30/76.42 221993[79:Res:53.1,221990.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.30/76.42 221995[80:Spt:221993.0] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.42 221997[80:Res:221995.0,61.1] always3(s35) || -> . % 76.30/76.42 221998[80:SSi:221997.0,78223.0,78226.0,217605.0,221687.0,221988.0] || -> . % 76.30/76.42 221999[80:Spt:221998.0,221993.0,221995.0] || m_main_v_state(s35,c_busy)* -> . % 76.30/76.42 222000[80:Spt:221998.0,221993.1] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 222004[80:Res:222000.0,61.1] always3(s36) || -> . % 76.30/76.42 222005[80:SSi:222004.0,78227.0,78231.0,217606.0] || -> . % 76.30/76.42 222006[78:Spt:222005.0,221686.0,221687.0] || until2p7(s35)*+ -> . % 76.30/76.42 222007[78:Spt:222005.0,221686.1] || -> node4(s34)*. % 76.30/76.42 222009[78:MRR:816.0,222007.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.30/76.42 222012[78:Res:53.1,222009.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.30/76.42 222014[79:Spt:222012.0] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.42 222016[79:Res:222014.0,61.1] always3(s34) || -> . % 76.30/76.42 222017[79:SSi:222016.0,78218.0,78222.0,217604.0,221685.0,222007.0] || -> . % 76.30/76.42 222018[79:Spt:222017.0,222012.0,222014.0] || m_main_v_state(s34,c_busy)* -> . % 76.30/76.42 222019[79:Spt:222017.0,222012.1] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.42 222023[79:Res:222019.0,61.1] always3(s35) || -> . % 76.30/76.42 222024[79:SSi:222023.0,78223.0,78226.0,217605.0] || -> . % 76.30/76.42 222025[77:Spt:222024.0,221684.0,221685.0] || until2p7(s34)*+ -> . % 76.30/76.42 222026[77:Spt:222024.0,221684.1] || -> node4(s33)*. % 76.30/76.42 222028[77:MRR:819.0,222026.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.30/76.42 222031[77:Res:53.1,222028.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.30/76.42 222036[78:Spt:222031.0] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.42 222038[78:Res:222036.0,61.1] always3(s33) || -> . % 76.30/76.42 222039[78:SSi:222038.0,78214.0,78217.0,217603.0,221683.0,222026.0] || -> . % 76.30/76.42 222040[78:Spt:222039.0,222031.0,222036.0] || m_main_v_state(s33,c_busy)* -> . % 76.30/76.42 222041[78:Spt:222039.0,222031.1] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.42 222045[78:Res:222041.0,61.1] always3(s34) || -> . % 76.30/76.42 222046[78:SSi:222045.0,78218.0,78222.0,217604.0] || -> . % 76.30/76.42 222047[76:Spt:222046.0,221682.0,221683.0] || until2p7(s33)*+ -> . % 76.30/76.42 222048[76:Spt:222046.0,221682.1] || -> node4(s32)*. % 76.30/76.42 222050[76:MRR:822.0,222048.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.30/76.42 222053[76:Res:53.1,222050.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.30/76.42 222055[76:MRR:222053.0,221672.0] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.42 222057[76:Res:222055.0,61.1] always3(s33) || -> . % 76.30/76.42 222058[76:SSi:222057.0,78214.0,78217.0,217603.0] || -> . % 76.30/76.42 222059[74:Spt:222058.0,221597.0,221600.0] || trans(s49,s32)*+ -> . % 76.30/76.42 222060[74:Spt:222058.0,221597.1,221597.2,221597.3,221597.4,221597.5,221597.6,221597.7,221597.8,221597.9,221597.10,221597.11,221597.12,221597.13,221597.14,221597.15,221597.16,221597.17,221597.18,221597.19,221597.20,221597.21,221597.22,221597.23,221597.24,221597.25] || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.42 222062[74:MRR:221599.1,222059.0] xuntil6(s49) || -> trans(s49,s31) trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.42 222063[75:Spt:222060.0] || -> trans(s49,s31)*. % 76.30/76.42 222064[75:Res:222063.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s31)*. % 76.30/76.42 222066[75:Res:222063.0,60.0] || -> node2(s49,s31)*. % 76.30/76.42 222067[75:SSi:222064.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s31)*. % 76.30/76.42 222068[75:Res:222066.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.30/76.42 222128[75:SoR:222068.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)*. % 76.30/76.42 222130[75:SoR:222128.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.30/76.42 222131[75:SSi:222130.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s31,c_busy)* xuntil6(s49). % 76.30/76.42 222132[76:Spt:222131.1] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.42 222134[76:Res:222132.0,61.1] always3(s31) || -> . % 76.30/76.42 222135[76:SSi:222134.0,78205.0,78208.0,217601.0] || -> . % 76.30/76.42 222136[76:Spt:222135.0,222131.1,222132.0] || m_main_v_state(s31,c_busy)*+ -> . % 76.30/76.42 222137[76:Spt:222135.0,222131.0,222131.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.42 222141[76:MRR:222128.2,222136.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.42 222142[76:Res:53.1,222137.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.42 222144[76:MRR:222142.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.42 222145[76:MRR:222067.0,222144.0] || -> until2p7(s31)*. % 76.30/76.42 222146[76:MRR:227.0,222145.0] || -> until2p7(s32)* node4(s31). % 76.30/76.42 222147[77:Spt:222146.0] || -> until2p7(s32)*. % 76.30/76.42 222148[77:MRR:228.0,222147.0] || -> until2p7(s33)* node4(s32). % 76.30/76.42 222149[78:Spt:222148.0] || -> until2p7(s33)*. % 76.30/76.42 222150[78:MRR:229.0,222149.0] || -> until2p7(s34)* node4(s33). % 76.30/76.42 222151[79:Spt:222150.0] || -> until2p7(s34)*. % 76.30/76.42 222152[79:MRR:230.0,222151.0] || -> until2p7(s35)* node4(s34). % 76.30/76.42 222153[80:Spt:222152.0] || -> until2p7(s35)*. % 76.30/76.42 222154[80:MRR:231.0,222153.0] || -> until2p7(s36)* node4(s35). % 76.30/76.42 222155[81:Spt:222154.0] || -> until2p7(s36)*. % 76.30/76.42 222156[81:MRR:232.0,222155.0] || -> until2p7(s37)* node4(s36). % 76.30/76.42 222157[82:Spt:222156.0] || -> until2p7(s37)*. % 76.30/76.42 222158[82:MRR:235.0,222157.0] || -> until2p7(s38)* node4(s37). % 76.30/76.42 222159[83:Spt:222158.0] || -> until2p7(s38)*. % 76.30/76.42 222160[83:MRR:236.0,222159.0] || -> until2p7(s39)* node4(s38). % 76.30/76.42 222161[84:Spt:222160.0] || -> until2p7(s39)*. % 76.30/76.42 222162[84:MRR:237.0,222161.0] || -> until2p7(s40)* node4(s39). % 76.30/76.42 222163[85:Spt:222162.0] || -> until2p7(s40)*. % 76.30/76.42 222164[85:MRR:238.0,222163.0] || -> until2p7(s41)* node4(s40). % 76.30/76.42 222165[86:Spt:222164.0] || -> until2p7(s41)*. % 76.30/76.42 222166[86:MRR:239.0,222165.0] || -> until2p7(s42)* node4(s41). % 76.30/76.42 222167[87:Spt:222166.0] || -> until2p7(s42)*. % 76.30/76.42 222168[87:MRR:240.0,222167.0] || -> until2p7(s43)* node4(s42). % 76.30/76.42 222169[88:Spt:222168.0] || -> until2p7(s43)*. % 76.30/76.42 222170[88:MRR:241.0,222169.0] || -> until2p7(s44)* node4(s43). % 76.30/76.42 222171[89:Spt:222170.0] || -> until2p7(s44)*. % 76.30/76.42 222172[89:MRR:539.0,222171.0] || -> until2p7(s45)* node4(s44). % 76.30/76.42 222173[90:Spt:222172.0] || -> until2p7(s45)*. % 76.30/76.42 222174[90:MRR:544.0,222173.0] || -> until2p7(s46)* node4(s45). % 76.30/76.42 222175[91:Spt:222174.0] || -> until2p7(s46)*. % 76.30/76.42 222176[91:MRR:549.0,222175.0] || -> until2p7(s47)* node4(s46). % 76.30/76.42 222177[92:Spt:222176.0] || -> until2p7(s47)*. % 76.30/76.42 222178[92:MRR:554.0,222177.0] || -> until2p7(s48)* node4(s47). % 76.30/76.42 222179[93:Spt:222178.0] || -> until2p7(s48)*. % 76.30/76.42 222180[93:MRR:559.0,222179.0] || -> until2p7(s49)* node4(s48). % 76.30/76.42 222181[94:Spt:222180.0] || -> until2p7(s49)*. % 76.30/76.42 222182[94:MRR:194.0,222181.0] || -> node4(s49)*. % 76.30/76.42 222183[94:MRR:222141.0,222182.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.42 222187[94:Res:53.1,222183.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.42 222189[94:MRR:222187.0,78381.0] || -> . % 76.30/76.42 222190[94:Spt:222189.0,222180.0,222181.0] || until2p7(s49)*+ -> . % 76.30/76.42 222191[94:Spt:222189.0,222180.1] || -> node4(s48)*. % 76.30/76.42 222192[94:MRR:78384.0,222191.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.42 222195[94:Res:53.1,222192.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 222198[94:Res:222195.0,61.1] always3(s48) || -> . % 76.30/76.42 222199[94:SSi:222198.0,78281.0,78387.0,217618.0,222179.0,222191.0] || -> . % 76.30/76.42 222200[93:Spt:222199.0,222178.0,222179.0] || until2p7(s48)*+ -> . % 76.30/76.42 222201[93:Spt:222199.0,222178.1] || -> node4(s47)*. % 76.30/76.42 222203[93:MRR:777.0,222201.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.42 222215[93:Res:53.1,222203.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.42 222217[94:Spt:222215.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 222219[94:Res:222217.0,61.1] always3(s47) || -> . % 76.30/76.42 222220[94:SSi:222219.0,78277.0,78280.0,217617.0,222177.0,222201.0] || -> . % 76.30/76.42 222221[94:Spt:222220.0,222215.0,222217.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.42 222222[94:Spt:222220.0,222215.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 222226[94:Res:222222.0,61.1] always3(s48) || -> . % 76.30/76.42 222227[94:SSi:222226.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.42 222228[92:Spt:222227.0,222176.0,222177.0] || until2p7(s47)*+ -> . % 76.30/76.42 222229[92:Spt:222227.0,222176.1] || -> node4(s46)*. % 76.30/76.42 222231[92:MRR:780.0,222229.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.42 222238[92:Res:53.1,222231.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.42 222243[93:Spt:222238.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 222245[93:Res:222243.0,61.1] always3(s46) || -> . % 76.30/76.42 222246[93:SSi:222245.0,78272.0,78276.0,217616.0,222175.0,222229.0] || -> . % 76.30/76.42 222247[93:Spt:222246.0,222238.0,222243.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.42 222248[93:Spt:222246.0,222238.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 222252[93:Res:222248.0,61.1] always3(s47) || -> . % 76.30/76.42 222253[93:SSi:222252.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.42 222254[91:Spt:222253.0,222174.0,222175.0] || until2p7(s46)*+ -> . % 76.30/76.42 222255[91:Spt:222253.0,222174.1] || -> node4(s45)*. % 76.30/76.42 222257[91:MRR:783.0,222255.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.42 222260[91:Res:53.1,222257.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.42 222262[92:Spt:222260.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 222264[92:Res:222262.0,61.1] always3(s45) || -> . % 76.30/76.42 222265[92:SSi:222264.0,78268.0,78271.0,217615.0,222173.0,222255.0] || -> . % 76.30/76.42 222266[92:Spt:222265.0,222260.0,222262.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.42 222267[92:Spt:222265.0,222260.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 222271[92:Res:222267.0,61.1] always3(s46) || -> . % 76.30/76.42 222272[92:SSi:222271.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.42 222273[90:Spt:222272.0,222172.0,222173.0] || until2p7(s45)*+ -> . % 76.30/76.42 222274[90:Spt:222272.0,222172.1] || -> node4(s44)*. % 76.30/76.42 222276[90:MRR:786.0,222274.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.42 222279[90:Res:53.1,222276.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.42 222281[91:Spt:222279.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 222283[91:Res:222281.0,61.1] always3(s44) || -> . % 76.30/76.42 222284[91:SSi:222283.0,78263.0,78267.0,217614.0,222171.0,222274.0] || -> . % 76.30/76.42 222285[91:Spt:222284.0,222279.0,222281.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.42 222286[91:Spt:222284.0,222279.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 222290[91:Res:222286.0,61.1] always3(s45) || -> . % 76.30/76.42 222291[91:SSi:222290.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.42 222292[89:Spt:222291.0,222170.0,222171.0] || until2p7(s44)*+ -> . % 76.30/76.42 222293[89:Spt:222291.0,222170.1] || -> node4(s43)*. % 76.30/76.42 222295[89:MRR:789.0,222293.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.42 222298[89:Res:53.1,222295.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.42 222300[90:Spt:222298.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 222302[90:Res:222300.0,61.1] always3(s43) || -> . % 76.30/76.42 222303[90:SSi:222302.0,78259.0,78262.0,217613.0,222169.0,222293.0] || -> . % 76.30/76.42 222304[90:Spt:222303.0,222298.0,222300.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.42 222305[90:Spt:222303.0,222298.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 222309[90:Res:222305.0,61.1] always3(s44) || -> . % 76.30/76.42 222310[90:SSi:222309.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.42 222311[88:Spt:222310.0,222168.0,222169.0] || until2p7(s43)*+ -> . % 76.30/76.42 222312[88:Spt:222310.0,222168.1] || -> node4(s42)*. % 76.30/76.42 222314[88:MRR:792.0,222312.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.42 222317[88:Res:53.1,222314.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.42 222322[89:Spt:222317.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 222324[89:Res:222322.0,61.1] always3(s42) || -> . % 76.30/76.42 222325[89:SSi:222324.0,78254.0,78258.0,217612.0,222167.0,222312.0] || -> . % 76.30/76.42 222326[89:Spt:222325.0,222317.0,222322.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.42 222327[89:Spt:222325.0,222317.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 222331[89:Res:222327.0,61.1] always3(s43) || -> . % 76.30/76.42 222332[89:SSi:222331.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.42 222333[87:Spt:222332.0,222166.0,222167.0] || until2p7(s42)*+ -> . % 76.30/76.42 222334[87:Spt:222332.0,222166.1] || -> node4(s41)*. % 76.30/76.42 222336[87:MRR:795.0,222334.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.42 222339[87:Res:53.1,222336.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.42 222341[88:Spt:222339.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 222343[88:Res:222341.0,61.1] always3(s41) || -> . % 76.30/76.42 222344[88:SSi:222343.0,78250.0,78253.0,217611.0,222165.0,222334.0] || -> . % 76.30/76.42 222345[88:Spt:222344.0,222339.0,222341.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.42 222346[88:Spt:222344.0,222339.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 222350[88:Res:222346.0,61.1] always3(s42) || -> . % 76.30/76.42 222351[88:SSi:222350.0,78254.0,78258.0,217612.0] || -> . % 76.30/76.42 222352[86:Spt:222351.0,222164.0,222165.0] || until2p7(s41)*+ -> . % 76.30/76.42 222353[86:Spt:222351.0,222164.1] || -> node4(s40)*. % 76.30/76.42 222355[86:MRR:798.0,222353.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.42 222358[86:Res:53.1,222355.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.42 222360[87:Spt:222358.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 222362[87:Res:222360.0,61.1] always3(s40) || -> . % 76.30/76.42 222363[87:SSi:222362.0,78245.0,78249.0,217610.0,222163.0,222353.0] || -> . % 76.30/76.42 222364[87:Spt:222363.0,222358.0,222360.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.42 222365[87:Spt:222363.0,222358.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 222369[87:Res:222365.0,61.1] always3(s41) || -> . % 76.30/76.42 222370[87:SSi:222369.0,78250.0,78253.0,217611.0] || -> . % 76.30/76.42 222371[85:Spt:222370.0,222162.0,222163.0] || until2p7(s40)*+ -> . % 76.30/76.42 222372[85:Spt:222370.0,222162.1] || -> node4(s39)*. % 76.30/76.42 222374[85:MRR:801.0,222372.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.42 222377[85:Res:53.1,222374.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.42 222379[86:Spt:222377.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 222381[86:Res:222379.0,61.1] always3(s39) || -> . % 76.30/76.42 222382[86:SSi:222381.0,78241.0,78244.0,217609.0,222161.0,222372.0] || -> . % 76.30/76.42 222383[86:Spt:222382.0,222377.0,222379.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.42 222384[86:Spt:222382.0,222377.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 222388[86:Res:222384.0,61.1] always3(s40) || -> . % 76.30/76.42 222389[86:SSi:222388.0,78245.0,78249.0,217610.0] || -> . % 76.30/76.42 222390[84:Spt:222389.0,222160.0,222161.0] || until2p7(s39)*+ -> . % 76.30/76.42 222391[84:Spt:222389.0,222160.1] || -> node4(s38)*. % 76.30/76.42 222393[84:MRR:804.0,222391.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.42 222396[84:Res:53.1,222393.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.42 222401[85:Spt:222396.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 222403[85:Res:222401.0,61.1] always3(s38) || -> . % 76.30/76.42 222404[85:SSi:222403.0,78236.0,78240.0,217608.0,222159.0,222391.0] || -> . % 76.30/76.42 222405[85:Spt:222404.0,222396.0,222401.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.42 222406[85:Spt:222404.0,222396.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 222410[85:Res:222406.0,61.1] always3(s39) || -> . % 76.30/76.42 222411[85:SSi:222410.0,78241.0,78244.0,217609.0] || -> . % 76.30/76.42 222412[83:Spt:222411.0,222158.0,222159.0] || until2p7(s38)*+ -> . % 76.30/76.42 222413[83:Spt:222411.0,222158.1] || -> node4(s37)*. % 76.30/76.42 222415[83:MRR:807.0,222413.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.42 222418[83:Res:53.1,222415.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.42 222420[84:Spt:222418.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 222422[84:Res:222420.0,61.1] always3(s37) || -> . % 76.30/76.42 222423[84:SSi:222422.0,78232.0,78235.0,217607.0,222157.0,222413.0] || -> . % 76.30/76.42 222424[84:Spt:222423.0,222418.0,222420.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.42 222425[84:Spt:222423.0,222418.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 222429[84:Res:222425.0,61.1] always3(s38) || -> . % 76.30/76.42 222430[84:SSi:222429.0,78236.0,78240.0,217608.0] || -> . % 76.30/76.42 222431[82:Spt:222430.0,222156.0,222157.0] || until2p7(s37)*+ -> . % 76.30/76.42 222432[82:Spt:222430.0,222156.1] || -> node4(s36)*. % 76.30/76.42 222434[82:MRR:810.0,222432.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.42 222437[82:Res:53.1,222434.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.42 222439[83:Spt:222437.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 222441[83:Res:222439.0,61.1] always3(s36) || -> . % 76.30/76.42 222442[83:SSi:222441.0,78227.0,78231.0,217606.0,222155.0,222432.0] || -> . % 76.30/76.42 222443[83:Spt:222442.0,222437.0,222439.0] || m_main_v_state(s36,c_busy)* -> . % 76.30/76.42 222444[83:Spt:222442.0,222437.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 222448[83:Res:222444.0,61.1] always3(s37) || -> . % 76.30/76.42 222449[83:SSi:222448.0,78232.0,78235.0,217607.0] || -> . % 76.30/76.42 222450[81:Spt:222449.0,222154.0,222155.0] || until2p7(s36)*+ -> . % 76.30/76.42 222451[81:Spt:222449.0,222154.1] || -> node4(s35)*. % 76.30/76.42 222453[81:MRR:813.0,222451.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.30/76.42 222456[81:Res:53.1,222453.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.30/76.42 222458[82:Spt:222456.0] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.42 222460[82:Res:222458.0,61.1] always3(s35) || -> . % 76.30/76.42 222461[82:SSi:222460.0,78223.0,78226.0,217605.0,222153.0,222451.0] || -> . % 76.30/76.42 222462[82:Spt:222461.0,222456.0,222458.0] || m_main_v_state(s35,c_busy)* -> . % 76.30/76.42 222463[82:Spt:222461.0,222456.1] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 222467[82:Res:222463.0,61.1] always3(s36) || -> . % 76.30/76.42 222468[82:SSi:222467.0,78227.0,78231.0,217606.0] || -> . % 76.30/76.42 222469[80:Spt:222468.0,222152.0,222153.0] || until2p7(s35)*+ -> . % 76.30/76.42 222470[80:Spt:222468.0,222152.1] || -> node4(s34)*. % 76.30/76.42 222472[80:MRR:816.0,222470.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.30/76.42 222475[80:Res:53.1,222472.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.30/76.42 222480[81:Spt:222475.0] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.42 222482[81:Res:222480.0,61.1] always3(s34) || -> . % 76.30/76.42 222483[81:SSi:222482.0,78218.0,78222.0,217604.0,222151.0,222470.0] || -> . % 76.30/76.42 222484[81:Spt:222483.0,222475.0,222480.0] || m_main_v_state(s34,c_busy)* -> . % 76.30/76.42 222485[81:Spt:222483.0,222475.1] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.42 222489[81:Res:222485.0,61.1] always3(s35) || -> . % 76.30/76.42 222490[81:SSi:222489.0,78223.0,78226.0,217605.0] || -> . % 76.30/76.42 222491[79:Spt:222490.0,222150.0,222151.0] || until2p7(s34)*+ -> . % 76.30/76.42 222492[79:Spt:222490.0,222150.1] || -> node4(s33)*. % 76.30/76.42 222494[79:MRR:819.0,222492.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.30/76.42 222497[79:Res:53.1,222494.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.30/76.42 222499[80:Spt:222497.0] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.42 222501[80:Res:222499.0,61.1] always3(s33) || -> . % 76.30/76.42 222502[80:SSi:222501.0,78214.0,78217.0,217603.0,222149.0,222492.0] || -> . % 76.30/76.42 222503[80:Spt:222502.0,222497.0,222499.0] || m_main_v_state(s33,c_busy)* -> . % 76.30/76.42 222504[80:Spt:222502.0,222497.1] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.42 222508[80:Res:222504.0,61.1] always3(s34) || -> . % 76.30/76.42 222509[80:SSi:222508.0,78218.0,78222.0,217604.0] || -> . % 76.30/76.42 222510[78:Spt:222509.0,222148.0,222149.0] || until2p7(s33)*+ -> . % 76.30/76.42 222511[78:Spt:222509.0,222148.1] || -> node4(s32)*. % 76.30/76.42 222513[78:MRR:822.0,222511.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.30/76.42 222516[78:Res:53.1,222513.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.30/76.42 222518[79:Spt:222516.0] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.42 222520[79:Res:222518.0,61.1] always3(s32) || -> . % 76.30/76.42 222521[79:SSi:222520.0,78209.0,78213.0,217602.0,222147.0,222511.0] || -> . % 76.30/76.42 222522[79:Spt:222521.0,222516.0,222518.0] || m_main_v_state(s32,c_busy)* -> . % 76.30/76.42 222523[79:Spt:222521.0,222516.1] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.42 222527[79:Res:222523.0,61.1] always3(s33) || -> . % 76.30/76.42 222528[79:SSi:222527.0,78214.0,78217.0,217603.0] || -> . % 76.30/76.42 222529[77:Spt:222528.0,222146.0,222147.0] || until2p7(s32)*+ -> . % 76.30/76.42 222530[77:Spt:222528.0,222146.1] || -> node4(s31)*. % 76.30/76.42 222532[77:MRR:825.0,222530.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.30/76.42 222535[77:Res:53.1,222532.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.30/76.42 222537[77:MRR:222535.0,222136.0] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.42 222539[77:Res:222537.0,61.1] always3(s32) || -> . % 76.30/76.42 222540[77:SSi:222539.0,78209.0,78213.0,217602.0] || -> . % 76.30/76.42 222541[75:Spt:222540.0,222060.0,222063.0] || trans(s49,s31)*+ -> . % 76.30/76.42 222542[75:Spt:222540.0,222060.1,222060.2,222060.3,222060.4,222060.5,222060.6,222060.7,222060.8,222060.9,222060.10,222060.11,222060.12,222060.13,222060.14,222060.15,222060.16,222060.17,222060.18,222060.19,222060.20,222060.21,222060.22,222060.23,222060.24] || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.42 222544[75:MRR:222062.1,222541.0] xuntil6(s49) || -> trans(s49,s30) trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.42 222545[76:Spt:222542.0] || -> trans(s49,s30)*. % 76.30/76.42 222546[76:Res:222545.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s30)*. % 76.30/76.42 222548[76:Res:222545.0,60.0] || -> node2(s49,s30)*. % 76.30/76.42 222549[76:SSi:222546.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s30)*. % 76.30/76.42 222550[76:Res:222548.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)*. % 76.30/76.42 222617[76:SoR:222550.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)*. % 76.30/76.42 222619[76:SoR:222617.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s30,c_busy)* xuntil6(s49). % 76.30/76.42 222620[76:SSi:222619.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s30,c_busy)* xuntil6(s49). % 76.30/76.42 222621[77:Spt:222620.1] || -> m_main_v_state(s30,c_busy)*. % 76.30/76.42 222623[77:Res:222621.0,61.1] always3(s30) || -> . % 76.30/76.42 222624[77:SSi:222623.0,78200.0,78204.0,217600.0] || -> . % 76.30/76.42 222625[77:Spt:222624.0,222620.1,222621.0] || m_main_v_state(s30,c_busy)*+ -> . % 76.30/76.42 222626[77:Spt:222624.0,222620.0,222620.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.42 222630[77:MRR:222617.2,222625.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.42 222631[77:Res:53.1,222626.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.42 222633[77:MRR:222631.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.42 222634[77:MRR:222549.0,222633.0] || -> until2p7(s30)*. % 76.30/76.42 222635[77:MRR:226.0,222634.0] || -> until2p7(s31)* node4(s30). % 76.30/76.42 222636[78:Spt:222635.0] || -> until2p7(s31)*. % 76.30/76.42 222637[78:MRR:227.0,222636.0] || -> until2p7(s32)* node4(s31). % 76.30/76.42 222638[79:Spt:222637.0] || -> until2p7(s32)*. % 76.30/76.42 222639[79:MRR:228.0,222638.0] || -> until2p7(s33)* node4(s32). % 76.30/76.42 222640[80:Spt:222639.0] || -> until2p7(s33)*. % 76.30/76.42 222641[80:MRR:229.0,222640.0] || -> until2p7(s34)* node4(s33). % 76.30/76.42 222642[81:Spt:222641.0] || -> until2p7(s34)*. % 76.30/76.42 222643[81:MRR:230.0,222642.0] || -> until2p7(s35)* node4(s34). % 76.30/76.42 222644[82:Spt:222643.0] || -> until2p7(s35)*. % 76.30/76.42 222645[82:MRR:231.0,222644.0] || -> until2p7(s36)* node4(s35). % 76.30/76.42 222646[83:Spt:222645.0] || -> until2p7(s36)*. % 76.30/76.42 222647[83:MRR:232.0,222646.0] || -> until2p7(s37)* node4(s36). % 76.30/76.42 222648[84:Spt:222647.0] || -> until2p7(s37)*. % 76.30/76.42 222649[84:MRR:235.0,222648.0] || -> until2p7(s38)* node4(s37). % 76.30/76.42 222650[85:Spt:222649.0] || -> until2p7(s38)*. % 76.30/76.42 222651[85:MRR:236.0,222650.0] || -> until2p7(s39)* node4(s38). % 76.30/76.42 222652[86:Spt:222651.0] || -> until2p7(s39)*. % 76.30/76.42 222653[86:MRR:237.0,222652.0] || -> until2p7(s40)* node4(s39). % 76.30/76.42 222654[87:Spt:222653.0] || -> until2p7(s40)*. % 76.30/76.42 222655[87:MRR:238.0,222654.0] || -> until2p7(s41)* node4(s40). % 76.30/76.42 222656[88:Spt:222655.0] || -> until2p7(s41)*. % 76.30/76.42 222657[88:MRR:239.0,222656.0] || -> until2p7(s42)* node4(s41). % 76.30/76.42 222658[89:Spt:222657.0] || -> until2p7(s42)*. % 76.30/76.42 222659[89:MRR:240.0,222658.0] || -> until2p7(s43)* node4(s42). % 76.30/76.42 222660[90:Spt:222659.0] || -> until2p7(s43)*. % 76.30/76.42 222661[90:MRR:241.0,222660.0] || -> until2p7(s44)* node4(s43). % 76.30/76.42 222662[91:Spt:222661.0] || -> until2p7(s44)*. % 76.30/76.42 222663[91:MRR:539.0,222662.0] || -> until2p7(s45)* node4(s44). % 76.30/76.42 222664[92:Spt:222663.0] || -> until2p7(s45)*. % 76.30/76.42 222665[92:MRR:544.0,222664.0] || -> until2p7(s46)* node4(s45). % 76.30/76.42 222666[93:Spt:222665.0] || -> until2p7(s46)*. % 76.30/76.42 222667[93:MRR:549.0,222666.0] || -> until2p7(s47)* node4(s46). % 76.30/76.42 222668[94:Spt:222667.0] || -> until2p7(s47)*. % 76.30/76.42 222669[94:MRR:554.0,222668.0] || -> until2p7(s48)* node4(s47). % 76.30/76.42 222670[95:Spt:222669.0] || -> until2p7(s48)*. % 76.30/76.42 222671[95:MRR:559.0,222670.0] || -> until2p7(s49)* node4(s48). % 76.30/76.42 222672[96:Spt:222671.0] || -> until2p7(s49)*. % 76.30/76.42 222673[96:MRR:194.0,222672.0] || -> node4(s49)*. % 76.30/76.42 222674[96:MRR:222630.0,222673.0] || m_main_v_state(s49,c_ready)*+ -> . % 76.30/76.42 222675[96:Res:53.1,222674.0] || -> m_main_v_state(s49,c_busy)*. % 76.30/76.42 222677[96:MRR:222675.0,78381.0] || -> . % 76.30/76.42 222678[96:Spt:222677.0,222671.0,222672.0] || until2p7(s49)*+ -> . % 76.30/76.42 222679[96:Spt:222677.0,222671.1] || -> node4(s48)*. % 76.30/76.42 222680[96:MRR:78384.0,222679.0] || m_main_v_state(s48,c_ready)*+ -> . % 76.30/76.42 222683[96:Res:53.1,222680.0] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 222686[96:Res:222683.0,61.1] always3(s48) || -> . % 76.30/76.42 222687[96:SSi:222686.0,78281.0,78387.0,217618.0,222670.0,222679.0] || -> . % 76.30/76.42 222688[95:Spt:222687.0,222669.0,222670.0] || until2p7(s48)*+ -> . % 76.30/76.42 222689[95:Spt:222687.0,222669.1] || -> node4(s47)*. % 76.30/76.42 222691[95:MRR:777.0,222689.0] || m_main_v_state(s47,c_ready)*+ -> m_main_v_state(s48,c_busy). % 76.30/76.42 222706[95:Res:53.1,222691.0] || -> m_main_v_state(s47,c_busy)* m_main_v_state(s48,c_busy). % 76.30/76.42 222708[96:Spt:222706.0] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 222710[96:Res:222708.0,61.1] always3(s47) || -> . % 76.30/76.42 222711[96:SSi:222710.0,78277.0,78280.0,217617.0,222668.0,222689.0] || -> . % 76.30/76.42 222712[96:Spt:222711.0,222706.0,222708.0] || m_main_v_state(s47,c_busy)* -> . % 76.30/76.42 222713[96:Spt:222711.0,222706.1] || -> m_main_v_state(s48,c_busy)*. % 76.30/76.42 222717[96:Res:222713.0,61.1] always3(s48) || -> . % 76.30/76.42 222718[96:SSi:222717.0,78281.0,78387.0,217618.0] || -> . % 76.30/76.42 222719[94:Spt:222718.0,222667.0,222668.0] || until2p7(s47)*+ -> . % 76.30/76.42 222720[94:Spt:222718.0,222667.1] || -> node4(s46)*. % 76.30/76.42 222722[94:MRR:780.0,222720.0] || m_main_v_state(s46,c_ready)*+ -> m_main_v_state(s47,c_busy). % 76.30/76.42 222732[94:Res:53.1,222722.0] || -> m_main_v_state(s46,c_busy)* m_main_v_state(s47,c_busy). % 76.30/76.42 222734[95:Spt:222732.0] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 222736[95:Res:222734.0,61.1] always3(s46) || -> . % 76.30/76.42 222737[95:SSi:222736.0,78272.0,78276.0,217616.0,222666.0,222720.0] || -> . % 76.30/76.42 222738[95:Spt:222737.0,222732.0,222734.0] || m_main_v_state(s46,c_busy)* -> . % 76.30/76.42 222739[95:Spt:222737.0,222732.1] || -> m_main_v_state(s47,c_busy)*. % 76.30/76.42 222743[95:Res:222739.0,61.1] always3(s47) || -> . % 76.30/76.42 222744[95:SSi:222743.0,78277.0,78280.0,217617.0] || -> . % 76.30/76.42 222745[93:Spt:222744.0,222665.0,222666.0] || until2p7(s46)*+ -> . % 76.30/76.42 222746[93:Spt:222744.0,222665.1] || -> node4(s45)*. % 76.30/76.42 222748[93:MRR:783.0,222746.0] || m_main_v_state(s45,c_ready)*+ -> m_main_v_state(s46,c_busy). % 76.30/76.42 222751[93:Res:53.1,222748.0] || -> m_main_v_state(s45,c_busy)* m_main_v_state(s46,c_busy). % 76.30/76.42 222753[94:Spt:222751.0] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 222755[94:Res:222753.0,61.1] always3(s45) || -> . % 76.30/76.42 222756[94:SSi:222755.0,78268.0,78271.0,217615.0,222664.0,222746.0] || -> . % 76.30/76.42 222757[94:Spt:222756.0,222751.0,222753.0] || m_main_v_state(s45,c_busy)* -> . % 76.30/76.42 222758[94:Spt:222756.0,222751.1] || -> m_main_v_state(s46,c_busy)*. % 76.30/76.42 222762[94:Res:222758.0,61.1] always3(s46) || -> . % 76.30/76.42 222763[94:SSi:222762.0,78272.0,78276.0,217616.0] || -> . % 76.30/76.42 222764[92:Spt:222763.0,222663.0,222664.0] || until2p7(s45)*+ -> . % 76.30/76.42 222765[92:Spt:222763.0,222663.1] || -> node4(s44)*. % 76.30/76.42 222767[92:MRR:786.0,222765.0] || m_main_v_state(s44,c_ready)*+ -> m_main_v_state(s45,c_busy). % 76.30/76.42 222770[92:Res:53.1,222767.0] || -> m_main_v_state(s44,c_busy)* m_main_v_state(s45,c_busy). % 76.30/76.42 222772[93:Spt:222770.0] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 222774[93:Res:222772.0,61.1] always3(s44) || -> . % 76.30/76.42 222775[93:SSi:222774.0,78263.0,78267.0,217614.0,222662.0,222765.0] || -> . % 76.30/76.42 222776[93:Spt:222775.0,222770.0,222772.0] || m_main_v_state(s44,c_busy)* -> . % 76.30/76.42 222777[93:Spt:222775.0,222770.1] || -> m_main_v_state(s45,c_busy)*. % 76.30/76.42 222781[93:Res:222777.0,61.1] always3(s45) || -> . % 76.30/76.42 222782[93:SSi:222781.0,78268.0,78271.0,217615.0] || -> . % 76.30/76.42 222783[91:Spt:222782.0,222661.0,222662.0] || until2p7(s44)*+ -> . % 76.30/76.42 222784[91:Spt:222782.0,222661.1] || -> node4(s43)*. % 76.30/76.42 222786[91:MRR:789.0,222784.0] || m_main_v_state(s43,c_ready)*+ -> m_main_v_state(s44,c_busy). % 76.30/76.42 222789[91:Res:53.1,222786.0] || -> m_main_v_state(s43,c_busy)* m_main_v_state(s44,c_busy). % 76.30/76.42 222794[92:Spt:222789.0] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 222796[92:Res:222794.0,61.1] always3(s43) || -> . % 76.30/76.42 222797[92:SSi:222796.0,78259.0,78262.0,217613.0,222660.0,222784.0] || -> . % 76.30/76.42 222798[92:Spt:222797.0,222789.0,222794.0] || m_main_v_state(s43,c_busy)* -> . % 76.30/76.42 222799[92:Spt:222797.0,222789.1] || -> m_main_v_state(s44,c_busy)*. % 76.30/76.42 222803[92:Res:222799.0,61.1] always3(s44) || -> . % 76.30/76.42 222804[92:SSi:222803.0,78263.0,78267.0,217614.0] || -> . % 76.30/76.42 222805[90:Spt:222804.0,222659.0,222660.0] || until2p7(s43)*+ -> . % 76.30/76.42 222806[90:Spt:222804.0,222659.1] || -> node4(s42)*. % 76.30/76.42 222808[90:MRR:792.0,222806.0] || m_main_v_state(s42,c_ready)*+ -> m_main_v_state(s43,c_busy). % 76.30/76.42 222811[90:Res:53.1,222808.0] || -> m_main_v_state(s42,c_busy)* m_main_v_state(s43,c_busy). % 76.30/76.42 222813[91:Spt:222811.0] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 222815[91:Res:222813.0,61.1] always3(s42) || -> . % 76.30/76.42 222816[91:SSi:222815.0,78254.0,78258.0,217612.0,222658.0,222806.0] || -> . % 76.30/76.42 222817[91:Spt:222816.0,222811.0,222813.0] || m_main_v_state(s42,c_busy)* -> . % 76.30/76.42 222818[91:Spt:222816.0,222811.1] || -> m_main_v_state(s43,c_busy)*. % 76.30/76.42 222822[91:Res:222818.0,61.1] always3(s43) || -> . % 76.30/76.42 222823[91:SSi:222822.0,78259.0,78262.0,217613.0] || -> . % 76.30/76.42 222824[89:Spt:222823.0,222657.0,222658.0] || until2p7(s42)*+ -> . % 76.30/76.42 222825[89:Spt:222823.0,222657.1] || -> node4(s41)*. % 76.30/76.42 222827[89:MRR:795.0,222825.0] || m_main_v_state(s41,c_ready)*+ -> m_main_v_state(s42,c_busy). % 76.30/76.42 222830[89:Res:53.1,222827.0] || -> m_main_v_state(s41,c_busy)* m_main_v_state(s42,c_busy). % 76.30/76.42 222832[90:Spt:222830.0] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 222834[90:Res:222832.0,61.1] always3(s41) || -> . % 76.30/76.42 222835[90:SSi:222834.0,78250.0,78253.0,217611.0,222656.0,222825.0] || -> . % 76.30/76.42 222836[90:Spt:222835.0,222830.0,222832.0] || m_main_v_state(s41,c_busy)* -> . % 76.30/76.42 222837[90:Spt:222835.0,222830.1] || -> m_main_v_state(s42,c_busy)*. % 76.30/76.42 222841[90:Res:222837.0,61.1] always3(s42) || -> . % 76.30/76.42 222842[90:SSi:222841.0,78254.0,78258.0,217612.0] || -> . % 76.30/76.42 222843[88:Spt:222842.0,222655.0,222656.0] || until2p7(s41)*+ -> . % 76.30/76.42 222844[88:Spt:222842.0,222655.1] || -> node4(s40)*. % 76.30/76.42 222846[88:MRR:798.0,222844.0] || m_main_v_state(s40,c_ready)*+ -> m_main_v_state(s41,c_busy). % 76.30/76.42 222849[88:Res:53.1,222846.0] || -> m_main_v_state(s40,c_busy)* m_main_v_state(s41,c_busy). % 76.30/76.42 222851[89:Spt:222849.0] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 222853[89:Res:222851.0,61.1] always3(s40) || -> . % 76.30/76.42 222854[89:SSi:222853.0,78245.0,78249.0,217610.0,222654.0,222844.0] || -> . % 76.30/76.42 222855[89:Spt:222854.0,222849.0,222851.0] || m_main_v_state(s40,c_busy)* -> . % 76.30/76.42 222856[89:Spt:222854.0,222849.1] || -> m_main_v_state(s41,c_busy)*. % 76.30/76.42 222860[89:Res:222856.0,61.1] always3(s41) || -> . % 76.30/76.42 222861[89:SSi:222860.0,78250.0,78253.0,217611.0] || -> . % 76.30/76.42 222862[87:Spt:222861.0,222653.0,222654.0] || until2p7(s40)*+ -> . % 76.30/76.42 222863[87:Spt:222861.0,222653.1] || -> node4(s39)*. % 76.30/76.42 222865[87:MRR:801.0,222863.0] || m_main_v_state(s39,c_ready)*+ -> m_main_v_state(s40,c_busy). % 76.30/76.42 222868[87:Res:53.1,222865.0] || -> m_main_v_state(s39,c_busy)* m_main_v_state(s40,c_busy). % 76.30/76.42 222873[88:Spt:222868.0] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 222875[88:Res:222873.0,61.1] always3(s39) || -> . % 76.30/76.42 222876[88:SSi:222875.0,78241.0,78244.0,217609.0,222652.0,222863.0] || -> . % 76.30/76.42 222877[88:Spt:222876.0,222868.0,222873.0] || m_main_v_state(s39,c_busy)* -> . % 76.30/76.42 222878[88:Spt:222876.0,222868.1] || -> m_main_v_state(s40,c_busy)*. % 76.30/76.42 222882[88:Res:222878.0,61.1] always3(s40) || -> . % 76.30/76.42 222883[88:SSi:222882.0,78245.0,78249.0,217610.0] || -> . % 76.30/76.42 222884[86:Spt:222883.0,222651.0,222652.0] || until2p7(s39)*+ -> . % 76.30/76.42 222885[86:Spt:222883.0,222651.1] || -> node4(s38)*. % 76.30/76.42 222887[86:MRR:804.0,222885.0] || m_main_v_state(s38,c_ready)*+ -> m_main_v_state(s39,c_busy). % 76.30/76.42 222890[86:Res:53.1,222887.0] || -> m_main_v_state(s38,c_busy)* m_main_v_state(s39,c_busy). % 76.30/76.42 222892[87:Spt:222890.0] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 222894[87:Res:222892.0,61.1] always3(s38) || -> . % 76.30/76.42 222895[87:SSi:222894.0,78236.0,78240.0,217608.0,222650.0,222885.0] || -> . % 76.30/76.42 222896[87:Spt:222895.0,222890.0,222892.0] || m_main_v_state(s38,c_busy)* -> . % 76.30/76.42 222897[87:Spt:222895.0,222890.1] || -> m_main_v_state(s39,c_busy)*. % 76.30/76.42 222901[87:Res:222897.0,61.1] always3(s39) || -> . % 76.30/76.42 222902[87:SSi:222901.0,78241.0,78244.0,217609.0] || -> . % 76.30/76.42 222903[85:Spt:222902.0,222649.0,222650.0] || until2p7(s38)*+ -> . % 76.30/76.42 222904[85:Spt:222902.0,222649.1] || -> node4(s37)*. % 76.30/76.42 222906[85:MRR:807.0,222904.0] || m_main_v_state(s37,c_ready)*+ -> m_main_v_state(s38,c_busy). % 76.30/76.42 222909[85:Res:53.1,222906.0] || -> m_main_v_state(s37,c_busy)* m_main_v_state(s38,c_busy). % 76.30/76.42 222911[86:Spt:222909.0] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 222913[86:Res:222911.0,61.1] always3(s37) || -> . % 76.30/76.42 222914[86:SSi:222913.0,78232.0,78235.0,217607.0,222648.0,222904.0] || -> . % 76.30/76.42 222915[86:Spt:222914.0,222909.0,222911.0] || m_main_v_state(s37,c_busy)* -> . % 76.30/76.42 222916[86:Spt:222914.0,222909.1] || -> m_main_v_state(s38,c_busy)*. % 76.30/76.42 222920[86:Res:222916.0,61.1] always3(s38) || -> . % 76.30/76.42 222921[86:SSi:222920.0,78236.0,78240.0,217608.0] || -> . % 76.30/76.42 222922[84:Spt:222921.0,222647.0,222648.0] || until2p7(s37)*+ -> . % 76.30/76.42 222923[84:Spt:222921.0,222647.1] || -> node4(s36)*. % 76.30/76.42 222925[84:MRR:810.0,222923.0] || m_main_v_state(s36,c_ready)*+ -> m_main_v_state(s37,c_busy). % 76.30/76.42 222928[84:Res:53.1,222925.0] || -> m_main_v_state(s36,c_busy)* m_main_v_state(s37,c_busy). % 76.30/76.42 222930[85:Spt:222928.0] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 222932[85:Res:222930.0,61.1] always3(s36) || -> . % 76.30/76.42 222933[85:SSi:222932.0,78227.0,78231.0,217606.0,222646.0,222923.0] || -> . % 76.30/76.42 222934[85:Spt:222933.0,222928.0,222930.0] || m_main_v_state(s36,c_busy)* -> . % 76.30/76.42 222935[85:Spt:222933.0,222928.1] || -> m_main_v_state(s37,c_busy)*. % 76.30/76.42 222939[85:Res:222935.0,61.1] always3(s37) || -> . % 76.30/76.42 222940[85:SSi:222939.0,78232.0,78235.0,217607.0] || -> . % 76.30/76.42 222941[83:Spt:222940.0,222645.0,222646.0] || until2p7(s36)*+ -> . % 76.30/76.42 222942[83:Spt:222940.0,222645.1] || -> node4(s35)*. % 76.30/76.42 222944[83:MRR:813.0,222942.0] || m_main_v_state(s35,c_ready)*+ -> m_main_v_state(s36,c_busy). % 76.30/76.42 222947[83:Res:53.1,222944.0] || -> m_main_v_state(s35,c_busy)* m_main_v_state(s36,c_busy). % 76.30/76.42 222952[84:Spt:222947.0] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.42 222954[84:Res:222952.0,61.1] always3(s35) || -> . % 76.30/76.42 222955[84:SSi:222954.0,78223.0,78226.0,217605.0,222644.0,222942.0] || -> . % 76.30/76.42 222956[84:Spt:222955.0,222947.0,222952.0] || m_main_v_state(s35,c_busy)* -> . % 76.30/76.42 222957[84:Spt:222955.0,222947.1] || -> m_main_v_state(s36,c_busy)*. % 76.30/76.42 222961[84:Res:222957.0,61.1] always3(s36) || -> . % 76.30/76.42 222962[84:SSi:222961.0,78227.0,78231.0,217606.0] || -> . % 76.30/76.42 222963[82:Spt:222962.0,222643.0,222644.0] || until2p7(s35)*+ -> . % 76.30/76.42 222964[82:Spt:222962.0,222643.1] || -> node4(s34)*. % 76.30/76.42 222966[82:MRR:816.0,222964.0] || m_main_v_state(s34,c_ready)*+ -> m_main_v_state(s35,c_busy). % 76.30/76.42 222969[82:Res:53.1,222966.0] || -> m_main_v_state(s34,c_busy)* m_main_v_state(s35,c_busy). % 76.30/76.42 222971[83:Spt:222969.0] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.42 222973[83:Res:222971.0,61.1] always3(s34) || -> . % 76.30/76.42 222974[83:SSi:222973.0,78218.0,78222.0,217604.0,222642.0,222964.0] || -> . % 76.30/76.42 222975[83:Spt:222974.0,222969.0,222971.0] || m_main_v_state(s34,c_busy)* -> . % 76.30/76.42 222976[83:Spt:222974.0,222969.1] || -> m_main_v_state(s35,c_busy)*. % 76.30/76.42 222980[83:Res:222976.0,61.1] always3(s35) || -> . % 76.30/76.42 222981[83:SSi:222980.0,78223.0,78226.0,217605.0] || -> . % 76.30/76.42 222982[81:Spt:222981.0,222641.0,222642.0] || until2p7(s34)*+ -> . % 76.30/76.42 222983[81:Spt:222981.0,222641.1] || -> node4(s33)*. % 76.30/76.42 222985[81:MRR:819.0,222983.0] || m_main_v_state(s33,c_ready)*+ -> m_main_v_state(s34,c_busy). % 76.30/76.42 222988[81:Res:53.1,222985.0] || -> m_main_v_state(s33,c_busy)* m_main_v_state(s34,c_busy). % 76.30/76.42 222990[82:Spt:222988.0] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.42 222992[82:Res:222990.0,61.1] always3(s33) || -> . % 76.30/76.42 222993[82:SSi:222992.0,78214.0,78217.0,217603.0,222640.0,222983.0] || -> . % 76.30/76.42 222994[82:Spt:222993.0,222988.0,222990.0] || m_main_v_state(s33,c_busy)* -> . % 76.30/76.42 222995[82:Spt:222993.0,222988.1] || -> m_main_v_state(s34,c_busy)*. % 76.30/76.42 222999[82:Res:222995.0,61.1] always3(s34) || -> . % 76.30/76.42 223000[82:SSi:222999.0,78218.0,78222.0,217604.0] || -> . % 76.30/76.42 223001[80:Spt:223000.0,222639.0,222640.0] || until2p7(s33)*+ -> . % 76.30/76.42 223002[80:Spt:223000.0,222639.1] || -> node4(s32)*. % 76.30/76.42 223004[80:MRR:822.0,223002.0] || m_main_v_state(s32,c_ready)*+ -> m_main_v_state(s33,c_busy). % 76.30/76.42 223007[80:Res:53.1,223004.0] || -> m_main_v_state(s32,c_busy)* m_main_v_state(s33,c_busy). % 76.30/76.42 223009[81:Spt:223007.0] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.42 223011[81:Res:223009.0,61.1] always3(s32) || -> . % 76.30/76.42 223012[81:SSi:223011.0,78209.0,78213.0,217602.0,222638.0,223002.0] || -> . % 76.30/76.42 223013[81:Spt:223012.0,223007.0,223009.0] || m_main_v_state(s32,c_busy)* -> . % 76.30/76.42 223014[81:Spt:223012.0,223007.1] || -> m_main_v_state(s33,c_busy)*. % 76.30/76.42 223018[81:Res:223014.0,61.1] always3(s33) || -> . % 76.30/76.42 223019[81:SSi:223018.0,78214.0,78217.0,217603.0] || -> . % 76.30/76.42 223020[79:Spt:223019.0,222637.0,222638.0] || until2p7(s32)*+ -> . % 76.30/76.42 223021[79:Spt:223019.0,222637.1] || -> node4(s31)*. % 76.30/76.42 223023[79:MRR:825.0,223021.0] || m_main_v_state(s31,c_ready)*+ -> m_main_v_state(s32,c_busy). % 76.30/76.42 223026[79:Res:53.1,223023.0] || -> m_main_v_state(s31,c_busy)* m_main_v_state(s32,c_busy). % 76.30/76.42 223031[80:Spt:223026.0] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.42 223033[80:Res:223031.0,61.1] always3(s31) || -> . % 76.30/76.42 223034[80:SSi:223033.0,78205.0,78208.0,217601.0,222636.0,223021.0] || -> . % 76.30/76.42 223035[80:Spt:223034.0,223026.0,223031.0] || m_main_v_state(s31,c_busy)* -> . % 76.30/76.42 223036[80:Spt:223034.0,223026.1] || -> m_main_v_state(s32,c_busy)*. % 76.30/76.42 223040[80:Res:223036.0,61.1] always3(s32) || -> . % 76.30/76.42 223041[80:SSi:223040.0,78209.0,78213.0,217602.0] || -> . % 76.30/76.42 223042[78:Spt:223041.0,222635.0,222636.0] || until2p7(s31)*+ -> . % 76.30/76.42 223043[78:Spt:223041.0,222635.1] || -> node4(s30)*. % 76.30/76.42 223045[78:MRR:828.0,223043.0] || m_main_v_state(s30,c_ready)*+ -> m_main_v_state(s31,c_busy). % 76.30/76.42 223048[78:Res:53.1,223045.0] || -> m_main_v_state(s30,c_busy)* m_main_v_state(s31,c_busy). % 76.30/76.42 223050[78:MRR:223048.0,222625.0] || -> m_main_v_state(s31,c_busy)*. % 76.30/76.42 223052[78:Res:223050.0,61.1] always3(s31) || -> . % 76.30/76.42 223053[78:SSi:223052.0,78205.0,78208.0,217601.0] || -> . % 76.30/76.42 223054[76:Spt:223053.0,222542.0,222545.0] || trans(s49,s30)*+ -> . % 76.30/76.42 223055[76:Spt:223053.0,222542.1,222542.2,222542.3,222542.4,222542.5,222542.6,222542.7,222542.8,222542.9,222542.10,222542.11,222542.12,222542.13,222542.14,222542.15,222542.16,222542.17,222542.18,222542.19,222542.20,222542.21,222542.22,222542.23] || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8) node2(s49,s7)*. % 76.30/76.42 223057[76:MRR:222544.1,223054.0] xuntil6(s49) || -> trans(s49,s29) trans(s49,s28) trans(s49,s27) trans(s49,s26) trans(s49,s25) trans(s49,s24) trans(s49,s23) trans(s49,s22) trans(s49,s21) trans(s49,s20) trans(s49,s19) trans(s49,s18) trans(s49,s17) trans(s49,s16) trans(s49,s15) trans(s49,s14) trans(s49,s13) trans(s49,s12) trans(s49,s11) trans(s49,s10) trans(s49,s9) trans(s49,s8)* until2p7(s7). % 76.30/76.42 223058[77:Spt:223055.0] || -> trans(s49,s29)*. % 76.30/76.42 223059[77:Res:223058.0,69.2] xuntil6(s49) last(s49) || -> until2p7(s29)*. % 76.30/76.42 223061[77:Res:223058.0,60.0] || -> node2(s49,s29)*. % 76.30/76.42 223062[77:SSi:223059.1,50.0,78285.0,78388.0] xuntil6(s49) || -> until2p7(s29)*. % 76.30/76.42 223063[77:Res:223061.0,58.1] m_main_v_request(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.30/76.42 223131[77:SoR:223063.0,64.1] node4(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)*. % 76.30/76.42 223133[77:SoR:223131.0,66.2] until5(s49) || m_main_v_state(s49,c_ready) -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.30/76.42 223134[77:SSi:223133.0,50.0,78285.0,78388.0] || m_main_v_state(s49,c_ready)+ -> m_main_v_state(s29,c_busy)* xuntil6(s49). % 76.30/76.42 223135[78:Spt:223134.1] || -> m_main_v_state(s29,c_busy)*. % 76.30/76.42 223137[78:Res:223135.0,61.1] always3(s29) || -> . % 76.30/76.42 223138[78:SSi:223137.0,78196.0,78199.0,217599.0] || -> . % 76.30/76.42 223139[78:Spt:223138.0,223134.1,223135.0] || m_main_v_state(s29,c_busy)*+ -> . % 76.30/76.42 223140[78:Spt:223138.0,223134.0,223134.2] || m_main_v_state(s49,c_ready)*+ -> xuntil6(s49). % 76.30/76.42 223144[78:MRR:223131.2,223139.0] node4(s49) || m_main_v_state(s49,c_ready)* -> . % 76.30/76.42 223145[78:Res:53.1,223140.0] || -> m_main_v_state(s49,c_busy)* xuntil6(s49). % 76.30/76.42 223147[78:MRR:223145.0,78381.0] || -> xuntil6(s49)*. % 76.30/76.42 223148[78:MRR:223062.0,223147.0] || -> until2p7(s29)*. % 76.30/76.42 223149[78:MRR:225.0,223148.0] || -> until2p7(s30)* node4(s29). % 76.30/76.42 223150[79:Spt:223149.0] || -> until2p7(s30)*. % 76.30/76.42 223151[79:MRR:226.0,223150.0] || -> until2p7(s31)* node4(s30). % 76.30/76.42 223152[80:Spt:223151.0] || -> until2p7(s31)*. % 76.30/76.42 223153[80:MRR:227.0,223152.0] || -> until2p7(s32)* node4(s31). % 76.30/76.42 223154[81:Spt:223153.0] || -> until2p7(s32)*. % 76.30/76.42 223155[81:MRR:228.0,223154.0] || -> until2p7(s33)* node4(s32). % 76.30/76.42 223156[82:Spt:223155.0] || -> until2p7(s33)*. % 76.30/76.42 223157[82:MRR:229.0,223156.0] || -> until2p7(s34)* node4(s33). % 76.30/76.42 223158[83:Spt:223157.0] || -> until2p7(s34)*. % 76.30/76.42 223159[83:MRR:230.0,223158.0] || -> until2p7(s35)* node4(s34). % 76.30/76.42 223160[84:Spt:223159.0] || ->