%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN524+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n056.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:42:14 EDT 2016
% Result : CounterSatisfiable 18.40s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN524+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.02/0.23 % Computer : n056.star.cs.uiowa.edu
% 0.02/0.23 % Model : x86_64 x86_64
% 0.02/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.02/0.23 % Memory : 32218.75MB
% 0.02/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.02/0.23 % CPULimit : 300
% 0.02/0.23 % DateTime : Sat Apr 9 00:13:24 CDT 2016
% 0.02/0.23 % CPUTime:
% 6.28/5.86 > val it = (): unit
% 6.58/6.17 Trying to find a model that refutes: ~ ((((((((((((((((((((ALL U.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 ((bnd_ndr1_1 U & ~ bnd_c3_2 U bnd_a157) &
% 6.58/6.17 bnd_c2_2 U bnd_a157 |
% 6.58/6.17 ~ bnd_c5_1 U) |
% 6.58/6.17 (ALL V.
% 6.58/6.17 bnd_ndr1_1 U -->
% 6.58/6.17 bnd_c1_2 U V | bnd_c5_2 U V)) |
% 6.58/6.17 bnd_c1_0) |
% 6.58/6.17 ((bnd_ndr1_0 & bnd_c3_1 bnd_a158) & bnd_c5_1 bnd_a158) &
% 6.58/6.17 (ALL W.
% 6.58/6.17 bnd_ndr1_1 bnd_a158 -->
% 6.58/6.17 (bnd_c1_2 bnd_a158 W | bnd_c5_2 bnd_a158 W) |
% 6.58/6.17 bnd_c4_2 bnd_a158 W)) &
% 6.58/6.17 ((~ bnd_c1_0 |
% 6.58/6.17 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a159) &
% 6.58/6.17 ~ bnd_c3_1 bnd_a159) &
% 6.58/6.17 bnd_ndr1_1 bnd_a159) &
% 6.58/6.17 ~ bnd_c3_2 bnd_a159 bnd_a160) &
% 6.58/6.17 ~ bnd_c5_2 bnd_a159 bnd_a160) |
% 6.58/6.17 (ALL X.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 (bnd_c1_1 X | bnd_c3_1 X) |
% 6.58/6.17 (ALL Y.
% 6.58/6.17 bnd_ndr1_1 X -->
% 6.58/6.17 ~ bnd_c5_2 X Y | bnd_c2_2 X Y)))) &
% 6.58/6.17 (((((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a161) &
% 6.58/6.17 bnd_ndr1_1 bnd_a161) &
% 6.58/6.17 bnd_c3_2 bnd_a161 bnd_a162) &
% 6.58/6.17 bnd_c5_2 bnd_a161 bnd_a162) &
% 6.58/6.17 bnd_c1_2 bnd_a161 bnd_a162) &
% 6.58/6.17 bnd_c4_1 bnd_a161 |
% 6.58/6.17 (ALL Z.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 (bnd_c2_1 Z |
% 6.58/6.17 (ALL X1.
% 6.58/6.17 bnd_ndr1_1 Z -->
% 6.58/6.17 ~ bnd_c4_2 Z X1 | ~ bnd_c1_2 Z X1)) |
% 6.58/6.17 bnd_c1_1 Z)) |
% 6.58/6.17 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a163) &
% 6.58/6.17 bnd_ndr1_1 bnd_a163) &
% 6.58/6.17 ~ bnd_c1_2 bnd_a163 bnd_a164) &
% 6.58/6.17 bnd_c5_2 bnd_a163 bnd_a164) &
% 6.58/6.17 ~ bnd_c3_2 bnd_a163 bnd_a164) &
% 6.58/6.17 ~ bnd_c2_1 bnd_a163)) &
% 6.58/6.17 (~ bnd_c5_0 |
% 6.58/6.17 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a165) &
% 6.58/6.17 bnd_ndr1_1 bnd_a165) &
% 6.58/6.17 bnd_c1_2 bnd_a165 bnd_a166) &
% 6.58/6.17 bnd_c3_2 bnd_a165 bnd_a166) &
% 6.58/6.17 ~ bnd_c5_2 bnd_a165 bnd_a166) &
% 6.58/6.17 (ALL X2.
% 6.58/6.17 bnd_ndr1_1 bnd_a165 -->
% 6.58/6.17 (bnd_c5_2 bnd_a165 X2 | ~ bnd_c3_2 bnd_a165 X2) |
% 6.58/6.17 bnd_c4_2 bnd_a165 X2))) &
% 6.58/6.17 ((~ bnd_c2_0 |
% 6.58/6.17 (ALL X3.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 (~ bnd_c5_1 X3 | ~ bnd_c2_1 X3) | bnd_c1_1 X3)) |
% 6.58/6.17 (((((bnd_ndr1_0 &
% 6.58/6.17 (ALL X4.
% 6.58/6.17 bnd_ndr1_1 bnd_a167 -->
% 6.58/6.17 (~ bnd_c2_2 bnd_a167 X4 |
% 6.58/6.17 ~ bnd_c1_2 bnd_a167 X4) |
% 6.58/6.17 bnd_c4_2 bnd_a167 X4)) &
% 6.58/6.17 (ALL X5.
% 6.58/6.17 bnd_ndr1_1 bnd_a167 -->
% 6.58/6.17 ~ bnd_c3_2 bnd_a167 X5 | ~ bnd_c1_2 bnd_a167 X5)) &
% 6.58/6.17 bnd_ndr1_1 bnd_a167) &
% 6.58/6.17 bnd_c2_2 bnd_a167 bnd_a168) &
% 6.58/6.17 bnd_c3_2 bnd_a167 bnd_a168) &
% 6.58/6.17 bnd_c4_2 bnd_a167 bnd_a168)) &
% 6.58/6.17 (((bnd_ndr1_0 & bnd_c3_1 bnd_a169) &
% 6.58/6.17 (ALL X6.
% 6.58/6.17 bnd_ndr1_1 bnd_a169 -->
% 6.58/6.17 (bnd_c2_2 bnd_a169 X6 | bnd_c3_2 bnd_a169 X6) |
% 6.58/6.17 bnd_c5_2 bnd_a169 X6) |
% 6.58/6.17 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a170) & ~ bnd_c3_1 bnd_a170) |
% 6.58/6.17 ((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a171) &
% 6.58/6.17 bnd_ndr1_1 bnd_a171) &
% 6.58/6.17 ~ bnd_c1_2 bnd_a171 bnd_a172) &
% 6.58/6.17 bnd_c3_2 bnd_a171 bnd_a172) &
% 6.58/6.17 (ALL X7.
% 6.58/6.17 bnd_ndr1_1 bnd_a171 -->
% 6.58/6.17 ~ bnd_c4_2 bnd_a171 X7 | ~ bnd_c5_2 bnd_a171 X7))) &
% 6.58/6.17 ((~ bnd_c5_0 |
% 6.58/6.17 (ALL X8.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 (bnd_ndr1_1 X8 & ~ bnd_c5_2 X8 bnd_a173) &
% 6.58/6.17 ~ bnd_c3_2 X8 bnd_a173)) |
% 6.58/6.17 (ALL X9.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 ((ALL X10.
% 6.58/6.17 bnd_ndr1_1 X9 -->
% 6.58/6.17 (bnd_c2_2 X9 X10 | bnd_c5_2 X9 X10) |
% 6.58/6.17 bnd_c4_2 X9 X10) |
% 6.58/6.17 ~ bnd_c2_1 X9) |
% 6.58/6.17 ~ bnd_c5_1 X9))) &
% 6.58/6.17 ((bnd_c3_0 | ~ bnd_c4_0) | bnd_c2_0)) &
% 6.58/6.17 ((~ bnd_c4_0 |
% 6.58/6.17 (ALL X11.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 (bnd_c1_1 X11 | ~ bnd_c3_1 X11) |
% 6.58/6.17 ((bnd_ndr1_1 X11 & ~ bnd_c2_2 X11 bnd_a174) &
% 6.58/6.17 ~ bnd_c5_2 X11 bnd_a174) &
% 6.58/6.17 ~ bnd_c1_2 X11 bnd_a174)) |
% 6.58/6.17 ((bnd_ndr1_0 & bnd_c1_1 bnd_a175) & bnd_c2_1 bnd_a175) &
% 6.58/6.17 (ALL X12.
% 6.58/6.17 bnd_ndr1_1 bnd_a175 -->
% 6.58/6.17 (bnd_c2_2 bnd_a175 X12 | ~ bnd_c3_2 bnd_a175 X12) |
% 6.58/6.17 bnd_c4_2 bnd_a175 X12))) &
% 6.58/6.17 (((ALL X13.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 (bnd_c4_1 X13 | ~ bnd_c5_1 X13) | ~ bnd_c2_1 X13) |
% 6.58/6.17 bnd_c3_0) |
% 6.58/6.17 (ALL X14.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 ((bnd_ndr1_1 X14 & ~ bnd_c4_2 X14 bnd_a176) &
% 6.58/6.17 bnd_c2_2 X14 bnd_a176 |
% 6.58/6.17 ((bnd_ndr1_1 X14 & bnd_c2_2 X14 bnd_a177) &
% 6.58/6.17 bnd_c4_2 X14 bnd_a177) &
% 6.58/6.17 bnd_c3_2 X14 bnd_a177) |
% 6.58/6.17 ~ bnd_c1_1 X14))) &
% 6.58/6.17 ((~ bnd_c2_0 |
% 6.58/6.17 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a178) & bnd_ndr1_1 bnd_a178) &
% 6.58/6.17 ~ bnd_c4_2 bnd_a178 bnd_a179) &
% 6.58/6.17 bnd_c5_2 bnd_a178 bnd_a179) &
% 6.58/6.17 (ALL X15.
% 6.58/6.17 bnd_ndr1_1 bnd_a178 -->
% 6.58/6.17 bnd_c4_2 bnd_a178 X15 | bnd_c3_2 bnd_a178 X15)) |
% 6.58/6.17 ~ bnd_c3_0)) &
% 6.58/6.17 ((~ bnd_c2_0 | ~ bnd_c3_0) |
% 6.58/6.17 (ALL X16.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 (~ bnd_c4_1 X16 | ~ bnd_c5_1 X16) | ~ bnd_c3_1 X16))) &
% 6.58/6.17 (((bnd_ndr1_0 & bnd_c2_1 bnd_a180) &
% 6.58/6.17 (ALL X17.
% 6.58/6.17 bnd_ndr1_1 bnd_a180 -->
% 6.58/6.17 (~ bnd_c5_2 bnd_a180 X17 | bnd_c4_2 bnd_a180 X17) |
% 6.58/6.17 ~ bnd_c1_2 bnd_a180 X17)) &
% 6.58/6.17 bnd_c3_1 bnd_a180 |
% 6.58/6.17 ~ bnd_c3_0)) &
% 6.58/6.17 ((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a181) &
% 6.58/6.17 (ALL X18.
% 6.58/6.17 bnd_ndr1_1 bnd_a181 -->
% 6.58/6.17 (~ bnd_c1_2 bnd_a181 X18 | bnd_c5_2 bnd_a181 X18) |
% 6.58/6.17 bnd_c3_2 bnd_a181 X18)) &
% 6.58/6.17 bnd_c1_1 bnd_a181 |
% 6.58/6.17 bnd_c4_0) |
% 6.58/6.17 bnd_c2_0)) &
% 6.58/6.17 ((bnd_c3_0 |
% 6.58/6.17 (ALL X19.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 (~ bnd_c1_1 X19 | ~ bnd_c4_1 X19) |
% 6.58/6.17 (ALL X20.
% 6.58/6.17 bnd_ndr1_1 X19 -->
% 6.58/6.17 (~ bnd_c4_2 X19 X20 | ~ bnd_c3_2 X19 X20) |
% 6.58/6.17 ~ bnd_c1_2 X19 X20))) |
% 6.58/6.17 (ALL X21.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 (bnd_c1_1 X21 |
% 6.58/6.17 ((bnd_ndr1_1 X21 & ~ bnd_c3_2 X21 bnd_a182) &
% 6.58/6.17 ~ bnd_c2_2 X21 bnd_a182) &
% 6.58/6.17 bnd_c5_2 X21 bnd_a182) |
% 6.58/6.17 (ALL X22.
% 6.58/6.17 bnd_ndr1_1 X21 -->
% 6.58/6.17 (bnd_c2_2 X21 X22 | bnd_c1_2 X21 X22) |
% 6.58/6.17 ~ bnd_c3_2 X21 X22)))) &
% 6.58/6.17 ((bnd_c1_0 | bnd_c5_0) |
% 6.58/6.17 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a183) & bnd_c1_2 bnd_a183 bnd_a184) &
% 6.58/6.17 ~ bnd_c5_2 bnd_a183 bnd_a184) &
% 6.58/6.17 bnd_c2_1 bnd_a183) &
% 6.58/6.17 (ALL X23.
% 6.58/6.17 bnd_ndr1_1 bnd_a183 -->
% 6.58/6.17 bnd_c3_2 bnd_a183 X23 | bnd_c2_2 bnd_a183 X23))) &
% 6.58/6.17 (bnd_c3_0 |
% 6.58/6.17 (ALL X24.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 ((bnd_ndr1_1 X24 & ~ bnd_c2_2 X24 bnd_a185) &
% 6.58/6.17 ~ bnd_c3_2 X24 bnd_a185 |
% 6.58/6.17 ~ bnd_c3_1 X24) |
% 6.58/6.17 (bnd_ndr1_1 X24 & ~ bnd_c1_2 X24 bnd_a186) &
% 6.58/6.17 bnd_c4_2 X24 bnd_a186))) &
% 6.58/6.17 (((ALL X25.
% 6.58/6.17 bnd_ndr1_0 -->
% 6.58/6.17 ((bnd_ndr1_1 X25 & bnd_c1_2 X25 bnd_a187) &
% 6.58/6.17 ~ bnd_c5_2 X25 bnd_a187) &
% 6.58/6.17 bnd_c2_2 X25 bnd_a187 |
% 6.58/6.17 ~ bnd_c2_1 X25) |
% 6.58/6.17 ~ bnd_c1_0) |
% 6.58/6.17 bnd_c5_0))
% 8.39/7.97 Unfolded term: ~ ((((((((((((((((((((ALL U.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 ((bnd_ndr1_1 U & ~ bnd_c3_2 U bnd_a157) &
% 8.39/7.97 bnd_c2_2 U bnd_a157 |
% 8.39/7.97 ~ bnd_c5_1 U) |
% 8.39/7.97 (ALL V.
% 8.39/7.97 bnd_ndr1_1 U -->
% 8.39/7.97 bnd_c1_2 U V | bnd_c5_2 U V)) |
% 8.39/7.97 bnd_c1_0) |
% 8.39/7.97 ((bnd_ndr1_0 & bnd_c3_1 bnd_a158) & bnd_c5_1 bnd_a158) &
% 8.39/7.97 (ALL W.
% 8.39/7.97 bnd_ndr1_1 bnd_a158 -->
% 8.39/7.97 (bnd_c1_2 bnd_a158 W | bnd_c5_2 bnd_a158 W) |
% 8.39/7.97 bnd_c4_2 bnd_a158 W)) &
% 8.39/7.97 ((~ bnd_c1_0 |
% 8.39/7.97 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a159) &
% 8.39/7.97 ~ bnd_c3_1 bnd_a159) &
% 8.39/7.97 bnd_ndr1_1 bnd_a159) &
% 8.39/7.97 ~ bnd_c3_2 bnd_a159 bnd_a160) &
% 8.39/7.97 ~ bnd_c5_2 bnd_a159 bnd_a160) |
% 8.39/7.97 (ALL X.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 (bnd_c1_1 X | bnd_c3_1 X) |
% 8.39/7.97 (ALL Y.
% 8.39/7.97 bnd_ndr1_1 X -->
% 8.39/7.97 ~ bnd_c5_2 X Y | bnd_c2_2 X Y)))) &
% 8.39/7.97 (((((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a161) &
% 8.39/7.97 bnd_ndr1_1 bnd_a161) &
% 8.39/7.97 bnd_c3_2 bnd_a161 bnd_a162) &
% 8.39/7.97 bnd_c5_2 bnd_a161 bnd_a162) &
% 8.39/7.97 bnd_c1_2 bnd_a161 bnd_a162) &
% 8.39/7.97 bnd_c4_1 bnd_a161 |
% 8.39/7.97 (ALL Z.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 (bnd_c2_1 Z |
% 8.39/7.97 (ALL X1.
% 8.39/7.97 bnd_ndr1_1 Z -->
% 8.39/7.97 ~ bnd_c4_2 Z X1 | ~ bnd_c1_2 Z X1)) |
% 8.39/7.97 bnd_c1_1 Z)) |
% 8.39/7.97 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a163) &
% 8.39/7.97 bnd_ndr1_1 bnd_a163) &
% 8.39/7.97 ~ bnd_c1_2 bnd_a163 bnd_a164) &
% 8.39/7.97 bnd_c5_2 bnd_a163 bnd_a164) &
% 8.39/7.97 ~ bnd_c3_2 bnd_a163 bnd_a164) &
% 8.39/7.97 ~ bnd_c2_1 bnd_a163)) &
% 8.39/7.97 (~ bnd_c5_0 |
% 8.39/7.97 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a165) &
% 8.39/7.97 bnd_ndr1_1 bnd_a165) &
% 8.39/7.97 bnd_c1_2 bnd_a165 bnd_a166) &
% 8.39/7.97 bnd_c3_2 bnd_a165 bnd_a166) &
% 8.39/7.97 ~ bnd_c5_2 bnd_a165 bnd_a166) &
% 8.39/7.97 (ALL X2.
% 8.39/7.97 bnd_ndr1_1 bnd_a165 -->
% 8.39/7.97 (bnd_c5_2 bnd_a165 X2 | ~ bnd_c3_2 bnd_a165 X2) |
% 8.39/7.97 bnd_c4_2 bnd_a165 X2))) &
% 8.39/7.97 ((~ bnd_c2_0 |
% 8.39/7.97 (ALL X3.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 (~ bnd_c5_1 X3 | ~ bnd_c2_1 X3) | bnd_c1_1 X3)) |
% 8.39/7.97 (((((bnd_ndr1_0 &
% 8.39/7.97 (ALL X4.
% 8.39/7.97 bnd_ndr1_1 bnd_a167 -->
% 8.39/7.97 (~ bnd_c2_2 bnd_a167 X4 |
% 8.39/7.97 ~ bnd_c1_2 bnd_a167 X4) |
% 8.39/7.97 bnd_c4_2 bnd_a167 X4)) &
% 8.39/7.97 (ALL X5.
% 8.39/7.97 bnd_ndr1_1 bnd_a167 -->
% 8.39/7.97 ~ bnd_c3_2 bnd_a167 X5 | ~ bnd_c1_2 bnd_a167 X5)) &
% 8.39/7.97 bnd_ndr1_1 bnd_a167) &
% 8.39/7.97 bnd_c2_2 bnd_a167 bnd_a168) &
% 8.39/7.97 bnd_c3_2 bnd_a167 bnd_a168) &
% 8.39/7.97 bnd_c4_2 bnd_a167 bnd_a168)) &
% 8.39/7.97 (((bnd_ndr1_0 & bnd_c3_1 bnd_a169) &
% 8.39/7.97 (ALL X6.
% 8.39/7.97 bnd_ndr1_1 bnd_a169 -->
% 8.39/7.97 (bnd_c2_2 bnd_a169 X6 | bnd_c3_2 bnd_a169 X6) |
% 8.39/7.97 bnd_c5_2 bnd_a169 X6) |
% 8.39/7.97 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a170) & ~ bnd_c3_1 bnd_a170) |
% 8.39/7.97 ((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a171) &
% 8.39/7.97 bnd_ndr1_1 bnd_a171) &
% 8.39/7.97 ~ bnd_c1_2 bnd_a171 bnd_a172) &
% 8.39/7.97 bnd_c3_2 bnd_a171 bnd_a172) &
% 8.39/7.97 (ALL X7.
% 8.39/7.97 bnd_ndr1_1 bnd_a171 -->
% 8.39/7.97 ~ bnd_c4_2 bnd_a171 X7 | ~ bnd_c5_2 bnd_a171 X7))) &
% 8.39/7.97 ((~ bnd_c5_0 |
% 8.39/7.97 (ALL X8.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 (bnd_ndr1_1 X8 & ~ bnd_c5_2 X8 bnd_a173) &
% 8.39/7.97 ~ bnd_c3_2 X8 bnd_a173)) |
% 8.39/7.97 (ALL X9.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 ((ALL X10.
% 8.39/7.97 bnd_ndr1_1 X9 -->
% 8.39/7.97 (bnd_c2_2 X9 X10 | bnd_c5_2 X9 X10) |
% 8.39/7.97 bnd_c4_2 X9 X10) |
% 8.39/7.97 ~ bnd_c2_1 X9) |
% 8.39/7.97 ~ bnd_c5_1 X9))) &
% 8.39/7.97 ((bnd_c3_0 | ~ bnd_c4_0) | bnd_c2_0)) &
% 8.39/7.97 ((~ bnd_c4_0 |
% 8.39/7.97 (ALL X11.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 (bnd_c1_1 X11 | ~ bnd_c3_1 X11) |
% 8.39/7.97 ((bnd_ndr1_1 X11 & ~ bnd_c2_2 X11 bnd_a174) &
% 8.39/7.97 ~ bnd_c5_2 X11 bnd_a174) &
% 8.39/7.97 ~ bnd_c1_2 X11 bnd_a174)) |
% 8.39/7.97 ((bnd_ndr1_0 & bnd_c1_1 bnd_a175) & bnd_c2_1 bnd_a175) &
% 8.39/7.97 (ALL X12.
% 8.39/7.97 bnd_ndr1_1 bnd_a175 -->
% 8.39/7.97 (bnd_c2_2 bnd_a175 X12 | ~ bnd_c3_2 bnd_a175 X12) |
% 8.39/7.97 bnd_c4_2 bnd_a175 X12))) &
% 8.39/7.97 (((ALL X13.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 (bnd_c4_1 X13 | ~ bnd_c5_1 X13) | ~ bnd_c2_1 X13) |
% 8.39/7.97 bnd_c3_0) |
% 8.39/7.97 (ALL X14.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 ((bnd_ndr1_1 X14 & ~ bnd_c4_2 X14 bnd_a176) &
% 8.39/7.97 bnd_c2_2 X14 bnd_a176 |
% 8.39/7.97 ((bnd_ndr1_1 X14 & bnd_c2_2 X14 bnd_a177) &
% 8.39/7.97 bnd_c4_2 X14 bnd_a177) &
% 8.39/7.97 bnd_c3_2 X14 bnd_a177) |
% 8.39/7.97 ~ bnd_c1_1 X14))) &
% 8.39/7.97 ((~ bnd_c2_0 |
% 8.39/7.97 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a178) & bnd_ndr1_1 bnd_a178) &
% 8.39/7.97 ~ bnd_c4_2 bnd_a178 bnd_a179) &
% 8.39/7.97 bnd_c5_2 bnd_a178 bnd_a179) &
% 8.39/7.97 (ALL X15.
% 8.39/7.97 bnd_ndr1_1 bnd_a178 -->
% 8.39/7.97 bnd_c4_2 bnd_a178 X15 | bnd_c3_2 bnd_a178 X15)) |
% 8.39/7.97 ~ bnd_c3_0)) &
% 8.39/7.97 ((~ bnd_c2_0 | ~ bnd_c3_0) |
% 8.39/7.97 (ALL X16.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 (~ bnd_c4_1 X16 | ~ bnd_c5_1 X16) | ~ bnd_c3_1 X16))) &
% 8.39/7.97 (((bnd_ndr1_0 & bnd_c2_1 bnd_a180) &
% 8.39/7.97 (ALL X17.
% 8.39/7.97 bnd_ndr1_1 bnd_a180 -->
% 8.39/7.97 (~ bnd_c5_2 bnd_a180 X17 | bnd_c4_2 bnd_a180 X17) |
% 8.39/7.97 ~ bnd_c1_2 bnd_a180 X17)) &
% 8.39/7.97 bnd_c3_1 bnd_a180 |
% 8.39/7.97 ~ bnd_c3_0)) &
% 8.39/7.97 ((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a181) &
% 8.39/7.97 (ALL X18.
% 8.39/7.97 bnd_ndr1_1 bnd_a181 -->
% 8.39/7.97 (~ bnd_c1_2 bnd_a181 X18 | bnd_c5_2 bnd_a181 X18) |
% 8.39/7.97 bnd_c3_2 bnd_a181 X18)) &
% 8.39/7.97 bnd_c1_1 bnd_a181 |
% 8.39/7.97 bnd_c4_0) |
% 8.39/7.97 bnd_c2_0)) &
% 8.39/7.97 ((bnd_c3_0 |
% 8.39/7.97 (ALL X19.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 (~ bnd_c1_1 X19 | ~ bnd_c4_1 X19) |
% 8.39/7.97 (ALL X20.
% 8.39/7.97 bnd_ndr1_1 X19 -->
% 8.39/7.97 (~ bnd_c4_2 X19 X20 | ~ bnd_c3_2 X19 X20) |
% 8.39/7.97 ~ bnd_c1_2 X19 X20))) |
% 8.39/7.97 (ALL X21.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 (bnd_c1_1 X21 |
% 8.39/7.97 ((bnd_ndr1_1 X21 & ~ bnd_c3_2 X21 bnd_a182) &
% 8.39/7.97 ~ bnd_c2_2 X21 bnd_a182) &
% 8.39/7.97 bnd_c5_2 X21 bnd_a182) |
% 8.39/7.97 (ALL X22.
% 8.39/7.97 bnd_ndr1_1 X21 -->
% 8.39/7.97 (bnd_c2_2 X21 X22 | bnd_c1_2 X21 X22) |
% 8.39/7.97 ~ bnd_c3_2 X21 X22)))) &
% 8.39/7.97 ((bnd_c1_0 | bnd_c5_0) |
% 8.39/7.97 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a183) & bnd_c1_2 bnd_a183 bnd_a184) &
% 8.39/7.97 ~ bnd_c5_2 bnd_a183 bnd_a184) &
% 8.39/7.97 bnd_c2_1 bnd_a183) &
% 8.39/7.97 (ALL X23.
% 8.39/7.97 bnd_ndr1_1 bnd_a183 -->
% 8.39/7.97 bnd_c3_2 bnd_a183 X23 | bnd_c2_2 bnd_a183 X23))) &
% 8.39/7.97 (bnd_c3_0 |
% 8.39/7.97 (ALL X24.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 ((bnd_ndr1_1 X24 & ~ bnd_c2_2 X24 bnd_a185) &
% 8.39/7.97 ~ bnd_c3_2 X24 bnd_a185 |
% 8.39/7.97 ~ bnd_c3_1 X24) |
% 8.39/7.97 (bnd_ndr1_1 X24 & ~ bnd_c1_2 X24 bnd_a186) &
% 8.39/7.97 bnd_c4_2 X24 bnd_a186))) &
% 8.39/7.97 (((ALL X25.
% 8.39/7.97 bnd_ndr1_0 -->
% 8.39/7.97 ((bnd_ndr1_1 X25 & bnd_c1_2 X25 bnd_a187) &
% 8.39/7.97 ~ bnd_c5_2 X25 bnd_a187) &
% 8.39/7.97 bnd_c2_2 X25 bnd_a187 |
% 8.39/7.97 ~ bnd_c2_1 X25) |
% 8.39/7.97 ~ bnd_c1_0) |
% 8.39/7.97 bnd_c5_0))
% 8.39/7.97 Adding axioms...
% 8.39/7.98 Typedef.type_definition_def
% 13.89/13.45 ...done.
% 13.89/13.46 Ground types: ?'b, TPTP_Interpret.ind
% 13.89/13.46 Translating term (sizes: 1, 1) ...
% 18.30/17.88 Invoking SAT solver...
% 18.40/17.99 Model found:
% 18.40/17.99 Size of types: ?'b: 1, TPTP_Interpret.ind: 1
% 18.40/17.99 bnd_a187: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a186: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a185: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a184: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a183: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a182: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a181: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a180: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a179: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a178: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a177: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a176: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a175: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a174: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_c4_0: False
% 18.40/17.99 bnd_c3_0: False
% 18.40/17.99 bnd_a173: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a172: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a171: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a170: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a169: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a168: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a167: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_c2_0: True
% 18.40/17.99 bnd_a166: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a165: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_c5_0: False
% 18.40/17.99 bnd_a164: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a163: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_c4_1: {(??.TPTP_Interpret.ind0, True)}
% 18.40/17.99 bnd_a162: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a161: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_c1_1: {(??.TPTP_Interpret.ind0, False)}
% 18.40/17.99 bnd_a160: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_a159: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_c2_1: {(??.TPTP_Interpret.ind0, False)}
% 18.40/17.99 bnd_c4_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 18.40/17.99 bnd_a158: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_c3_1: {(??.TPTP_Interpret.ind0, False)}
% 18.40/17.99 bnd_c1_0: True
% 18.40/17.99 bnd_c5_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 18.40/17.99 bnd_c1_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 18.40/17.99 bnd_c5_1: {(??.TPTP_Interpret.ind0, False)}
% 18.40/17.99 bnd_c2_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 18.40/17.99 bnd_a157: ??.TPTP_Interpret.ind0
% 18.40/17.99 bnd_c3_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 18.40/17.99 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, True)}
% 18.40/17.99 bnd_ndr1_0: True
% 18.40/17.99
% 18.40/17.99 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------